repo_name stringlengths 1 62 | dataset stringclasses 1
value | lang stringclasses 11
values | pr_id int64 1 20.1k | owner stringlengths 2 34 | reviewer stringlengths 2 39 | diff_hunk stringlengths 15 262k | code_review_comment stringlengths 1 99.6k |
|---|---|---|---|---|---|---|---|
intel-xpu-backend-for-triton | github_2023 | python | 1,075 | intel | FMarno | @@ -35,7 +35,7 @@ def __init__(
'prune_num_stages_by'(optional): a function used to prune num_stages. It takes configs:List[Config] as its input, and returns pruned configs.
"""
if not configs:
- self.configs = [Config({}, num_warps=4, num_stages=2, num_ctas=1)]
+ se... | I thought we wanted the default to be 16 for Intel? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,046 | intel | Dewei-Wang-sh | @@ -30,9 +30,14 @@ TritonIntelGPUToLLVMTypeConverter::TritonIntelGPUToLLVMTypeConverter(
addConversion([&](mlir::RankedTensorType type) -> mlir::Type {
unsigned num = type.getNumElements();
Type elmTy = type.getElementType();
- if (!type.getEncoding() ||
- isa<mlir::triton::gpu::DotOper... | Ha yes, we should re-examine this. |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,046 | intel | etiotto | @@ -221,7 +221,8 @@ class TritonGPUToLLVMPipelineManager {
intel::populateBF16CastsLLVMPatterns(typeConverter, patterns, benefit);
intel::populateControlFlowOpToLLVMPattern(typeConverter, patterns,
benefit);
- intel::populateTritonOpsToLLVMPatterns(typ... | `populateTritonOpsToLLVMPatterns` AFAIK is only used by the advanced path. Do we really need to pass the extra boolean ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,046 | intel | etiotto | @@ -617,4 +680,6 @@ void mlir::triton::intel::populateTritonOpsToLLVMPatterns(
patterns.add<MakeTensorPtrOpConversion>(typeConverter, benefit);
patterns.add<ReduceOpConversion>(typeConverter, benefit);
patterns.add<SplatOpConversion>(typeConverter, benefit);
+ if (isAdvancedPathEnabled) | This is always true. |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,046 | intel | whitneywhtsang | @@ -573,8 +579,36 @@ class BroadcastOpConversion
LogicalResult
matchAndRewrite(triton::BroadcastOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter) const override {
- rewriter.replaceOp(op, adaptor.getSrc());
- return success();
+ constexpr unsigned subgroupSize = 16; | would it be better to get subgroup size from module? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,046 | intel | Dewei-Wang-sh | @@ -650,6 +684,31 @@ class AddPtrOpConversion : public ConvertTritonGPUOpToLLVMPattern<AddPtrOp> {
}
};
+class MakeRangeOpConversion
+ : public ConvertTritonGPUOpToLLVMPattern<MakeRangeOp> {
+public:
+ using ConvertTritonGPUOpToLLVMPattern<
+ MakeRangeOp>::ConvertTritonGPUOpToLLVMPattern;
+ LogicalResul... | typically, we have a separate conversion for triton ops, that's why this file stands.
what's meaning here? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,046 | intel | Dewei-Wang-sh | @@ -650,6 +684,31 @@ class AddPtrOpConversion : public ConvertTritonGPUOpToLLVMPattern<AddPtrOp> {
}
};
+class MakeRangeOpConversion
+ : public ConvertTritonGPUOpToLLVMPattern<MakeRangeOp> {
+public:
+ using ConvertTritonGPUOpToLLVMPattern<
+ MakeRangeOp>::ConvertTritonGPUOpToLLVMPattern;
+ LogicalResul... | style: using auto or the exact type? we need to be consistent.
for me, I prefer auto since most of the time, people do not mess with the type. |
intel-xpu-backend-for-triton | github_2023 | python | 1,473 | intel | etiotto | @@ -143,6 +143,8 @@ def make_ttir(mod, metadata, opt):
passes.common.add_cse(pm)
passes.common.add_licm(pm)
passes.common.add_symbol_dce(pm)
+ if (os.getenv("TRITON_RAISE_BLOCK_POINTER", "0") == "1"): | Ideally we should raise regular ptrs to blocked ptrs by default.
Can you do that please ? |
intel-xpu-backend-for-triton | github_2023 | others | 2,213 | intel | anmyachev | @@ -219,60 +225,60 @@ run_microbench_tests() {
echo "****************************************************"
echo "***** Running Triton Micro Benchmark tests *****"
echo "****************************************************"
- python $TRITON_PROJ/benchmarks/micro_benchmarks/run_benchmarks.py
+ python3 $TRI... | I'm just wondering if this is still relevant, because it seemed to me that Python 2 is already so old that it's safe to just specify Python :) |
intel-xpu-backend-for-triton | github_2023 | others | 2,213 | intel | anmyachev | @@ -106,34 +106,40 @@ if [ "$VENV" = true ]; then
source .venv/bin/activate
fi
-export TRITON_PROJ=$BASE/intel-xpu-backend-for-triton
-export TRITON_PROJ_BUILD=$TRITON_PROJ/python/build
-export SCRIPTS_DIR=$(cd $(dirname "$0") && pwd)
+SCRIPTS_DIR="$( cd -- "$( dirname -- "${BASH_SOURCE[0]}" )" &> /dev/null && pw... | Is this a prerequisite for testing?
If the folder is deleted and triton is installed with pip, the tests won't work? |
intel-xpu-backend-for-triton | github_2023 | others | 2,213 | intel | anmyachev | @@ -106,34 +106,40 @@ if [ "$VENV" = true ]; then
source .venv/bin/activate
fi
-export TRITON_PROJ=$BASE/intel-xpu-backend-for-triton
-export TRITON_PROJ_BUILD=$TRITON_PROJ/python/build
-export SCRIPTS_DIR=$(cd $(dirname "$0") && pwd)
+SCRIPTS_DIR="$( cd -- "$( dirname -- "${BASH_SOURCE[0]}" )" &> /dev/null && pw... | Echoing some message to the user can be helpful. |
intel-xpu-backend-for-triton | github_2023 | python | 1,124 | intel | etiotto | @@ -1367,9 +1367,6 @@ def _validate_dtype(dtype, allowed_types, operand_name):
assert lhs_rank == rhs_rank == 2 or lhs_rank == rhs_rank == 3, f"Both inputs must be either 2D or 3D; (lhs: {lhs.shape} vs rhs: {rhs.shape})"
assert lhs.shape[-1].value == rhs.shape[
-2].value, f"First input shape ({lhs.sh... | why is this assert removed ? |
intel-xpu-backend-for-triton | github_2023 | python | 1,124 | intel | etiotto | @@ -119,6 +119,9 @@
num_warps=32),
triton.Config({'BLOCK_SIZE_M': 256, 'BLOCK_SIZE_N': 256, 'BLOCK_SIZE_K': 64, 'GROUP_SIZE_M': 4}, num_stages=4,
num_warps=32),
+ # For mxnxk=4x4096x512 | What is the motivation to add a new block shape? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,124 | intel | etiotto | @@ -254,8 +254,12 @@ createGenISA2DBlockRead(TritonGEN::Matrix2DBlockLoadOp op,
op.getY(), i32_val(1));
SmallVector<Type> argTypes{ptr_ty(context, 1), i32_ty, i32_ty, i32_ty,
vecType};
- SmallVector<Value> args{op.getPtr(), op.getBaseWidth(), op.getBaseHeight(),
- ... | Please reformat the comment on one line. This looks strange. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,124 | intel | etiotto | @@ -168,10 +168,45 @@ class LoadStorePrefetchOpConversion
getVectorType(cast<RankedTensorType>(op.getResult().getType()),
idx == 0 ? i16_ty : i32_ty);
bool vnni = (idx == 1) && dataSize <= 32;
+
+ // according to gfxspec: For vnni, max height is 32
+ constexpr unsign... | auto -> unsigned |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,124 | intel | etiotto | @@ -168,10 +168,45 @@ class LoadStorePrefetchOpConversion
getVectorType(cast<RankedTensorType>(op.getResult().getType()),
idx == 0 ? i16_ty : i32_ty);
bool vnni = (idx == 1) && dataSize <= 32;
+
+ // according to gfxspec: For vnni, max height is 32
+ constexpr unsign... | typo: eqaul -> equal |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,124 | intel | etiotto | @@ -168,10 +168,45 @@ class LoadStorePrefetchOpConversion
getVectorType(cast<RankedTensorType>(op.getResult().getType()),
idx == 0 ? i16_ty : i32_ty);
bool vnni = (idx == 1) && dataSize <= 32;
+
+ // according to gfxspec: For vnni, max height is 32
+ constexpr unsign... | auto -> unsigned ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,124 | intel | whitneywhtsang | @@ -254,8 +254,12 @@ createGenISA2DBlockRead(TritonGEN::Matrix2DBlockLoadOp op,
op.getY(), i32_val(1));
SmallVector<Type> argTypes{ptr_ty(context, 1), i32_ty, i32_ty, i32_ty,
vecType};
- SmallVector<Value> args{op.getPtr(), op.getBaseWidth(), op.getBaseHeight(),
- ... | As discussed, let's not add one in GEN to OCL lowering. But remove sub one from the user, and move that to GEN to GenISA lowering. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,124 | intel | Dewei-Wang-sh | @@ -168,10 +168,45 @@ class LoadStorePrefetchOpConversion
getVectorType(cast<RankedTensorType>(op.getResult().getType()),
idx == 0 ? i16_ty : i32_ty);
bool vnni = (idx == 1) && dataSize <= 32;
+
+ // according to gfxspec: For vnni, max height is 32
+ constexpr unsign... | if we need 2 loads, we should split it in match-target-size, the conversion pass serves for one op conversion. |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,178 | intel | victor-eds | @@ -20,7 +20,7 @@ std::string getTypeMangling(Type ty, bool isUnsigned) {
.Case([isUnsigned](IntegerType ty) -> std::string {
switch (ty.getWidth()) {
case 8:
- return "c";
+ return isUnsigned ? "c" : "h"; | ```suggestion
return isUnsigned ? "h" : "c";
```
`c` is for char, `h` for unsigned char (see https://itanium-cxx-abi.github.io/cxx-abi/abi.html#mangling-builtin) |
intel-xpu-backend-for-triton | github_2023 | others | 2,178 | intel | victor-eds | @@ -397,7 +397,7 @@ def TritonGEN_Matrix2DBlockPrefetchOp : TritonGEN_Op<"2Dblockprefetch">,
}
def TritonGEN_SIMDBlockReadOp: TritonGEN_Op<"simdblockread">,
- Results<(outs FixedVectorOf<[TritonGEN_MatrixElemType]>:$res)>,
+ Results<(outs FixedVectorOf<[AnyTypeOf<[AnyI8, AnyI16, AnyI32, AnyI64]>]>:$res)>, | Can we add float types and wider vectors and abstract in conversion to LLVM? |
intel-xpu-backend-for-triton | github_2023 | others | 2,178 | intel | victor-eds | @@ -418,7 +418,7 @@ def TritonGEN_SIMDBlockReadOp: TritonGEN_Op<"simdblockread">,
def TritonGEN_SIMDBlockWriteOp : TritonGEN_Op<"simdblockwrite">,
Arguments<(ins
Arg<LLVM_AnyPointer, "", [MemWrite]>:$ptr,
- FixedVectorOf<[TritonGEN_MatrixElemType]>:$val
+ FixedVectorOf<[AnyTypeOf<[AnyI8, AnyI16, AnyI32, ... | Same |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,178 | intel | victor-eds | @@ -1254,6 +1254,18 @@ struct TritonMatrix2DBlockPrefetchLowering
}
};
+static bool isTySIMDOCLBuiltinAvailable(VectorType vecTy) {
+ unsigned numElems = vecTy.getNumElements();
+ if (numElems == 1 || numElems == 2 || numElems == 4 || numElems == 8)
+ return true;
+
+ IntegerType elemTy = cast<IntegerType>(... | I don't see `ushort16` supported [here](https://github.com/KhronosGroup/OpenCL-Docs/blob/main/extensions/cl_intel_subgroup_local_block_io.asciidoc) |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,178 | intel | victor-eds | @@ -1266,7 +1278,16 @@ struct TritonSIMDBlockReadLowering
VectorType vecTy = op.getRes().getType();
// TODO: Remove GenISA lowering after PoC productization is completed.
- const StringLiteral funcName = "llvm.genx.GenISA.simdBlockRead";
+ std::string funcName = "llvm.genx.GenISA.simdBlockRead";
+ ... | Can you add a comment mentioning OCL builtin name here differs from regular mangling? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,178 | intel | victor-eds | @@ -1296,7 +1317,18 @@ struct TritonSIMDBlockWriteLowering
VectorType vecTy = op.getVal().getType();
// TODO: Remove GenISA lowering after PoC productization is completed.
- const StringLiteral funcName = "llvm.genx.GenISA.simdBlockWrite";
+ std::string funcName = "llvm.genx.GenISA.simdBlockWrite";
+ ... | Can we move this and above to a function to share code? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,178 | intel | etiotto | @@ -1266,7 +1278,16 @@ struct TritonSIMDBlockReadLowering
VectorType vecTy = op.getRes().getType();
// TODO: Remove GenISA lowering after PoC productization is completed.
- const StringLiteral funcName = "llvm.genx.GenISA.simdBlockRead";
+ std::string funcName = "llvm.genx.GenISA.simdBlockRead";
+ ... | remove false as is the default |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,178 | intel | etiotto | @@ -1266,7 +1278,16 @@ struct TritonSIMDBlockReadLowering
VectorType vecTy = op.getRes().getType();
// TODO: Remove GenISA lowering after PoC productization is completed.
- const StringLiteral funcName = "llvm.genx.GenISA.simdBlockRead";
+ std::string funcName = "llvm.genx.GenISA.simdBlockRead";
+ ... | `true -> true /*is_unsigned*/` |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,178 | intel | victor-eds | @@ -1231,6 +1231,40 @@ struct TritonMatrix2DBlockPrefetchLowering
}
};
+static bool isTySIMDOCLBuiltinAvailable(VectorType vecTy) {
+ unsigned numElems = vecTy.getNumElements();
+ if (numElems == 1 || numElems == 2 || numElems == 4 || numElems == 8)
+ return true;
+
+ // FIXME: Allow 16xi16 when SPIRV-LLVM ... | ```suggestion
constexpr bool isWrite = std::is_same_v<OpType, TritonGEN::SIMDBlockWriteOp>;
```
NIT |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,178 | intel | victor-eds | @@ -1231,6 +1231,40 @@ struct TritonMatrix2DBlockPrefetchLowering
}
};
+static bool isTySIMDOCLBuiltinAvailable(VectorType vecTy) {
+ unsigned numElems = vecTy.getNumElements();
+ if (numElems == 1 || numElems == 2 || numElems == 4 || numElems == 8)
+ return true;
+
+ // FIXME: Allow 16xi16 when SPIRV-LLVM ... | ```suggestion
if constexpr (isWrite)
funcName += "write";
else
funcName += "read";
```
NIT. Should be equivalent, but explicit. |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,178 | intel | victor-eds | @@ -1231,6 +1231,40 @@ struct TritonMatrix2DBlockPrefetchLowering
}
};
+static bool isTySIMDOCLBuiltinAvailable(VectorType vecTy) {
+ unsigned numElems = vecTy.getNumElements();
+ if (numElems == 1 || numElems == 2 || numElems == 4 || numElems == 8)
+ return true;
+
+ // FIXME: Allow 16xi16 when SPIRV-LLVM ... | ```suggestion
if constexpr (isWrite)
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,178 | intel | victor-eds | @@ -1231,6 +1231,44 @@ struct TritonMatrix2DBlockPrefetchLowering
}
};
+static bool isTySIMDOCLBuiltinAvailable(VectorType vecTy) {
+ unsigned numElems = vecTy.getNumElements();
+ if (numElems == 1 || numElems == 2 || numElems == 4 || numElems == 8)
+ return true;
+
+ // FIXME: Allow 16xi16 when SPIRV-LLVM ... | ```suggestion
intel::getTypeMangling(vecTy.getElementType(), /*isUnsigned=*/true);
if constexpr (isWrite)
funcName += intel::getTypeMangling(vecTy, /*isUnsigned=*/true);
```
Super NIT. Can merge as is. |
intel-xpu-backend-for-triton | github_2023 | others | 2,203 | intel | pbchekin | @@ -49,10 +53,20 @@ jobs:
run: |
pip install wheel
- - name: Setup PyTorch
+ - name: Setup PyTorch with IPEX
+ if: ${{ inputs.install_ipex }} | When triggered by cron all inputs are `null`, so you need a special handling for that case. For example:
* `${{ github.event_name == 'schedule' || inputs.install_ipex }}` to check if IPEX is enabled
* `${{ !(github.event_name == 'schedule' || inputs.install_ipex) }}` to check if IPEX is disabled
This github "featu... |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,182 | intel | etiotto | @@ -278,12 +280,12 @@ class LoadStorePrefetchOpConversion
base = gep(ptrToSharedMemTy, i16_ty, base, index);
if constexpr (std::is_same_v<OpType, LoadOp>) {
- VectorType v64f16Ty = VectorType::get(64, f16_ty);
+ VectorType v64f16Ty = VectorType::get(64, elemType); | The variable name indicates the vector element type is f16, however that is not always the case. Change variable name to `vecType` ? |
intel-xpu-backend-for-triton | github_2023 | others | 2,182 | intel | whitneywhtsang | @@ -231,15 +231,15 @@ module attributes {"triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 8 :
#dpas = #triton_intel_gpu.dpas<{repeatCount = 8, systolicDepth = 8, executionSize = 16, opsPerChan = 2, threadsPerWarp = 16, warpsPerCTA = [4, 2], repCluster = [1, 1], A = [8, 16], B = [16, 16], C = [8, 16]}>
#dot0 ... | In https://github.com/intel/intel-xpu-backend-for-triton/pull/2178, I would like to change simdBlockRead to only accept integer element type, as that's what supported from OpenCL builtins, is this change required? Or the change in AllocateSharedMemory.cpp is enough? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,182 | intel | whitneywhtsang | @@ -49,9 +49,14 @@ struct AllocateSharedMemory
IntegerAttr::get(IntegerType::get(ctx, 32), offset));
});
});
- mod->setAttr("triton_gpu.shared",
- IntegerAttr::get(IntegerType::get(ctx, 32),
- allocation.getSharedMemorySize()));
+ i... | originalSharedMemorySize or initialSharedMemorySize? |
intel-xpu-backend-for-triton | github_2023 | others | 1,156 | intel | pbchekin | @@ -0,0 +1,169 @@
+# https://github.com/intel/intel-xpu-backend-for-triton/issues/986 | Why this skip list contains more test cases that the existing default skip list? The run (https://github.com/intel/intel-xpu-backend-for-triton/actions/runs/9214379486) shows that we do not need to skip more tests than the current skip list has. |
intel-xpu-backend-for-triton | github_2023 | others | 1,156 | intel | pbchekin | @@ -50,3 +46,50 @@ if [ "$QUIET" = false ]; then
echo "AGAMA_VERSION=$AGAMA_VERSION"
echo "GPU_DEVICE=$GPU_DEVICE"
fi
+
+agama_to_driver_type() { | I think we do not need to detect what driver (rolling or lts) is currently installed. Instead, a specific runner should set an environment variable either to select a skip list or to select a release stream (if you still need it for some reason). |
intel-xpu-backend-for-triton | github_2023 | others | 1,486 | intel | Dewei-Wang-sh | @@ -0,0 +1,29 @@
+// RUN: triton-opt %s -triton-raise-block-pointer -canonicalize -convert-triton-to-tritongpu=target="xpu:DEVICE_ARCH.PVC threads-per-warp=16" -tritongpu-remove-layout-conversions --tritonintelgpu-accelerate-matmul --tritonintelgpu-remove-layout-conversions --tritonintelgpu-rewrite-tensor-pointer --i... | is this appropriate for a unit test?
how about adding an integration test and leave the unit test as clean/dedicated as possible? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,486 | intel | etiotto | @@ -50,6 +50,30 @@ struct PtrState {
return offsets.size();
}
+ bool isBlockPtr() const { return !order.empty(); } | You'll need to rebase (I pushed in your other PR with these changes). |
intel-xpu-backend-for-triton | github_2023 | others | 1,659 | intel | victor-eds | @@ -49,8 +49,8 @@ llvm.func @gen_special_regs() -> i32 {
// CHECK: llvm.call spir_funccc @_Z14get_num_groupsj([[TWO3]]) {{.*}} : (i32) -> i64
%12 = triton_gen.grid.dim.z : i32
- // CHECK: llvm.call spir_funccc @_Z25__spirv_BuiltInSubgroupIdv() {{.*}} : () -> i32
- %13 = triton_gen.subgroup.id : i32
+ // CHEC... | According to the OCL-SPIR-V client spec, this is `i32`, so this violates that.
After #1663, this operation should be removed, so I do not think we should be modifying it here.
We should not worry much about these casts anyway, as the compiler is smart and we will get the minimum number of them.
Let's focus on ... |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,128 | intel | etiotto | @@ -15,10 +17,57 @@ using namespace mlir::triton;
namespace mlir::LLVM::intel {
+static Type findShuffleType(RewriterBase &rewriter, Type valType) {
+ if (rewriter.getI8Type() == valType || rewriter.getI16Type() == valType ||
+ rewriter.getI32Type() == valType || rewriter.getI64Type() == valType ||
+ re... | add an assert msg |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,128 | intel | etiotto | @@ -15,10 +17,57 @@ using namespace mlir::triton;
namespace mlir::LLVM::intel {
+static Type findShuffleType(RewriterBase &rewriter, Type valType) {
+ if (rewriter.getI8Type() == valType || rewriter.getI16Type() == valType || | [nit]: Would be good to not create a type and instead use `valType.isInteger(8) || valType.isInteger(16) || ...` |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,128 | intel | victor-eds | @@ -6,6 +6,8 @@
//
//===----------------------------------------------------------------------===//
+#include "mlir/Dialect/GPU/IR/GPUDialect.h"
+
#include "Utility.h"
#include "intel/include/Dialect/TritonIntelGPU/IR/LinearLayoutConversions.h"
#include "intel/include/Dialect/TritonIntelGPU/Transforms/Utility.h" | ```suggestion
#include "Utility.h"
#include "mlir/Dialect/GPU/IR/GPUDialect.h"
#include "intel/include/Dialect/TritonIntelGPU/IR/LinearLayoutConversions.h"
#include "intel/include/Dialect/TritonIntelGPU/Transforms/Utility.h"
```
Keep `Utility.h` on top |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,128 | intel | victor-eds | @@ -15,10 +17,57 @@ using namespace mlir::triton;
namespace mlir::LLVM::intel {
+static Type findShuffleType(RewriterBase &rewriter, Type valType) {
+ if (rewriter.getI8Type() == valType || rewriter.getI16Type() == valType ||
+ rewriter.getI32Type() == valType || rewriter.getI64Type() == valType ||
+ re... | Move this closer to usage |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,128 | intel | victor-eds | @@ -15,10 +17,57 @@ using namespace mlir::triton;
namespace mlir::LLVM::intel {
+static Type findShuffleType(RewriterBase &rewriter, Type valType) {
+ if (rewriter.getI8Type() == valType || rewriter.getI16Type() == valType ||
+ rewriter.getI32Type() == valType || rewriter.getI64Type() == valType ||
+ re... | ```suggestion
Value widthConstant = int_32(width);
```
Or at least generate `LLVM::ConstantOp` |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,128 | intel | victor-eds | @@ -15,10 +17,57 @@ using namespace mlir::triton;
namespace mlir::LLVM::intel {
+static Type findShuffleType(RewriterBase &rewriter, Type valType) {
+ if (rewriter.getI8Type() == valType || rewriter.getI16Type() == valType ||
+ rewriter.getI32Type() == valType || rewriter.getI64Type() == valType ||
+ re... | ```suggestion
Value result =
rewriter.create<mlir::gpu::ShuffleOp>(loc, val, i, widthConstant, mode)
.getShuffleResult();
```
MLIR is cool! |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,128 | intel | victor-eds | @@ -15,10 +17,57 @@ using namespace mlir::triton;
namespace mlir::LLVM::intel {
+static Type findShuffleType(RewriterBase &rewriter, Type valType) { | Changing the logic of the function would also work:
1. Check if it's `bf16`
2. Check if the type's width is `<8`
3. *Assert* type is valid and return `valType` |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,045 | intel | etiotto | @@ -524,11 +531,25 @@ class ScfPattern : public OpRewritePattern<scf::ForOp> {
}
auto glue = cast<ttgi::GlueOp>(definingOp);
- for (Operation *user : result.getUsers()) {
- if (auto extract = dyn_cast<ttgi::ExtractOp>(user)) {
+ if (llvm::all_of(result.getUsers(),
+ ... | auto* -> Operation* |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,045 | intel | etiotto | @@ -524,11 +531,25 @@ class ScfPattern : public OpRewritePattern<scf::ForOp> {
}
auto glue = cast<ttgi::GlueOp>(definingOp);
- for (Operation *user : result.getUsers()) {
- if (auto extract = dyn_cast<ttgi::ExtractOp>(user)) {
+ if (llvm::all_of(result.getUsers(),
+ ... | auto * -> Operation * |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,045 | intel | Dewei-Wang-sh | @@ -514,6 +514,13 @@ class ScfPattern : public OpRewritePattern<scf::ForOp> {
// Replace uses of the original loop results with the new loop results.
userIndexMap.clear();
+
+ // If a results is used by another scf.for loop, we re-glue the individual
+ // results together to allow canonicalization of ... | we can extend the new condition by handling the scf.yield operation.
no need to add a map.
if the scf.yield has a operand whose def is glue, then split it into two operands |
intel-xpu-backend-for-triton | github_2023 | others | 2,126 | intel | pbchekin | @@ -0,0 +1,174 @@
+#!/usr/bin/env bash
+
+set -euo pipefail
+
+# Select what to install.
+BUILD_PYTORCH=false
+BUILD_LATEST=false
+FORCE_REINSTALL=false
+PYTORCH_CURRENT_COMMIT=""
+VENV=false
+for arg in "$@"; do
+ case $arg in
+ --source)
+ BUILD_PYTORCH=true
+ shift
+ ;;
+ --latest)
+ # Bui... | `ARGS` not used, I would recommend to exit with error on unknown argument. |
intel-xpu-backend-for-triton | github_2023 | others | 2,126 | intel | pbchekin | @@ -0,0 +1,174 @@
+#!/usr/bin/env bash
+
+set -euo pipefail
+
+# Select what to install.
+BUILD_PYTORCH=false
+BUILD_LATEST=false
+FORCE_REINSTALL=false
+PYTORCH_CURRENT_COMMIT=""
+VENV=false
+for arg in "$@"; do
+ case $arg in
+ --source)
+ BUILD_PYTORCH=true
+ shift
+ ;;
+ --latest)
+ # Bui... | Why do we need this? I would recommend removing it and rely on external configuration for `xtrace`. |
intel-xpu-backend-for-triton | github_2023 | others | 2,126 | intel | pbchekin | @@ -0,0 +1,174 @@
+#!/usr/bin/env bash
+
+set -euo pipefail
+
+# Select what to install.
+BUILD_PYTORCH=false
+BUILD_LATEST=false
+FORCE_REINSTALL=false
+PYTORCH_CURRENT_COMMIT=""
+VENV=false
+for arg in "$@"; do
+ case $arg in
+ --source)
+ BUILD_PYTORCH=true
+ shift
+ ;;
+ --latest)
+ # Bui... | For consistency
```suggestion
echo "***** Using pinned PyTorch commit $PYTORCH_PINNED_COMMIT by default. *****"
``` |
intel-xpu-backend-for-triton | github_2023 | others | 2,126 | intel | pbchekin | @@ -0,0 +1,174 @@
+#!/usr/bin/env bash
+
+set -euo pipefail
+
+# Select what to install.
+BUILD_PYTORCH=false
+BUILD_LATEST=false
+FORCE_REINSTALL=false
+PYTORCH_CURRENT_COMMIT=""
+VENV=false
+for arg in "$@"; do
+ case $arg in
+ --source)
+ BUILD_PYTORCH=true
+ shift
+ ;;
+ --latest)
+ # Bui... | For consistency
```suggestion
PYTORCH_CURRENT_COMMIT="$(python -c 'import torch;print(torch.__version__)')"
``` |
intel-xpu-backend-for-triton | github_2023 | others | 2,126 | intel | pbchekin | @@ -0,0 +1,174 @@
+#!/usr/bin/env bash
+
+set -euo pipefail
+
+# Select what to install.
+BUILD_PYTORCH=false
+BUILD_LATEST=false
+FORCE_REINSTALL=false
+PYTORCH_CURRENT_COMMIT=""
+VENV=false
+for arg in "$@"; do
+ case $arg in
+ --source)
+ BUILD_PYTORCH=true
+ shift
+ ;;
+ --latest)
+ # Bui... | ```suggestion
echo "**** The following pinned torch dependencies are installed: ****"
echo "$INSTALLED_PINNED_TORCH_DEPENDENCIES"
``` |
intel-xpu-backend-for-triton | github_2023 | others | 2,126 | intel | pbchekin | @@ -0,0 +1,174 @@
+#!/usr/bin/env bash
+
+set -euo pipefail
+
+# Select what to install.
+BUILD_PYTORCH=false
+BUILD_LATEST=false
+FORCE_REINSTALL=false
+PYTORCH_CURRENT_COMMIT=""
+VENV=false
+for arg in "$@"; do
+ case $arg in
+ --source)
+ BUILD_PYTORCH=true
+ shift
+ ;;
+ --latest)
+ # Bui... | For consistency
```suggestion
PYTHON_VERSION=$(python -c "import sys; print(f'{sys.version_info.major}.{sys.version_info.minor}')")
``` |
intel-xpu-backend-for-triton | github_2023 | others | 2,126 | intel | pbchekin | @@ -0,0 +1,174 @@
+#!/usr/bin/env bash
+
+set -euo pipefail
+
+# Select what to install.
+BUILD_PYTORCH=false
+BUILD_LATEST=false
+FORCE_REINSTALL=false
+PYTORCH_CURRENT_COMMIT=""
+VENV=false
+for arg in "$@"; do
+ case $arg in
+ --source)
+ BUILD_PYTORCH=true
+ shift
+ ;;
+ --latest)
+ # Bui... | For consistency with previous line
```suggestion
SCRIPTS_DIR=$ROOT/scripts
``` |
intel-xpu-backend-for-triton | github_2023 | others | 2,126 | intel | pbchekin | @@ -0,0 +1,174 @@
+#!/usr/bin/env bash
+
+set -euo pipefail
+
+# Select what to install.
+BUILD_PYTORCH=false
+BUILD_LATEST=false
+FORCE_REINSTALL=false
+PYTORCH_CURRENT_COMMIT=""
+VENV=false
+for arg in "$@"; do
+ case $arg in
+ --source)
+ BUILD_PYTORCH=true
+ shift
+ ;;
+ --latest)
+ # Bui... | `rm -rf` always returns 0, no need in `if`.
```suggestion
rm -rf $PYTORCH_PROJ
``` |
intel-xpu-backend-for-triton | github_2023 | others | 2,126 | intel | Retribution98 | @@ -0,0 +1,174 @@
+#!/usr/bin/env bash
+
+set -euo pipefail
+
+# Select what to install.
+BUILD_PYTORCH=false
+BUILD_LATEST=false
+FORCE_REINSTALL=false
+PYTORCH_CURRENT_COMMIT=""
+VENV=false
+for arg in "$@"; do
+ case $arg in
+ --source)
+ BUILD_PYTORCH=true
+ shift
+ ;;
+ --latest)
+ # Bui... | If we run this script in default mode without additional options from another script, and the environment has an incorrect version of torch, we will write a message, but the main script will not be interrupted, because the exit code is 0.
It seems to me that this is incorrect behavior, because a separate message will ... |
intel-xpu-backend-for-triton | github_2023 | others | 2,126 | intel | Retribution98 | @@ -0,0 +1,174 @@
+#!/usr/bin/env bash
+
+set -euo pipefail
+
+# Select what to install.
+BUILD_PYTORCH=false
+BUILD_LATEST=false
+FORCE_REINSTALL=false
+PYTORCH_CURRENT_COMMIT=""
+VENV=false
+for arg in "$@"; do
+ case $arg in
+ --source)
+ BUILD_PYTORCH=true
+ shift
+ ;;
+ --latest)
+ # Bui... | The same reason |
intel-xpu-backend-for-triton | github_2023 | others | 2,126 | intel | Retribution98 | @@ -0,0 +1,174 @@
+#!/usr/bin/env bash
+
+set -euo pipefail
+
+# Select what to install.
+BUILD_PYTORCH=false
+BUILD_LATEST=false
+FORCE_REINSTALL=false
+PYTORCH_CURRENT_COMMIT=""
+VENV=false
+for arg in "$@"; do
+ case $arg in
+ --source)
+ BUILD_PYTORCH=true
+ shift
+ ;;
+ --latest)
+ # Bui... | Since we want to keep this script as simple as possible and don't plan to allow the user to use it with custom torch directory, we don't need this condition.
```suggestion
BASE=$ROOT/.scripts_cache
``` |
intel-xpu-backend-for-triton | github_2023 | others | 2,126 | intel | Retribution98 | @@ -0,0 +1,174 @@
+#!/usr/bin/env bash
+
+set -euo pipefail
+
+# Select what to install.
+BUILD_PYTORCH=false
+BUILD_LATEST=false
+FORCE_REINSTALL=false
+PYTORCH_CURRENT_COMMIT=""
+VENV=false
+for arg in "$@"; do
+ case $arg in
+ --source)
+ BUILD_PYTORCH=true
+ shift
+ ;;
+ --latest)
+ # Bui... | Since we want to keep this script as simple as possible and don't plan to allow the user to use it with their own torch directory, maybe we should use a temporary directory (like for installing from wheels) and delete it immediately after the script finished? |
intel-xpu-backend-for-triton | github_2023 | others | 2,126 | intel | anmyachev | @@ -0,0 +1,169 @@
+#!/usr/bin/env bash
+
+set -euo pipefail
+
+# Select what to install.
+BUILD_PYTORCH=false
+BUILD_LATEST=false
+FORCE_REINSTALL=false
+PYTORCH_CURRENT_COMMIT=""
+VENV=false
+for arg in "$@"; do
+ case $arg in
+ --source)
+ BUILD_PYTORCH=true
+ shift
+ ;;
+ --latest)
+ # Bui... | Why don't we do this check when `"$BUILD_LATEST" = true` ? |
intel-xpu-backend-for-triton | github_2023 | others | 2,126 | intel | anmyachev | @@ -0,0 +1,169 @@
+#!/usr/bin/env bash
+
+set -euo pipefail
+
+# Select what to install.
+BUILD_PYTORCH=false
+BUILD_LATEST=false
+FORCE_REINSTALL=false
+PYTORCH_CURRENT_COMMIT=""
+VENV=false
+for arg in "$@"; do
+ case $arg in
+ --source)
+ BUILD_PYTORCH=true
+ shift
+ ;;
+ --latest)
+ # Bui... | ?
```suggestion
rm -rf $TEMP_DIR
``` |
intel-xpu-backend-for-triton | github_2023 | others | 2,126 | intel | anmyachev | @@ -0,0 +1,169 @@
+#!/usr/bin/env bash
+
+set -euo pipefail
+
+# Select what to install.
+BUILD_PYTORCH=false
+BUILD_LATEST=false
+FORCE_REINSTALL=false
+PYTORCH_CURRENT_COMMIT=""
+VENV=false
+for arg in "$@"; do
+ case $arg in
+ --source)
+ BUILD_PYTORCH=true
+ shift
+ ;;
+ --latest)
+ # Bui... | Why use `mkl-static mkl-include`? Isn't there enough of `mkl` from `PTDB`? |
intel-xpu-backend-for-triton | github_2023 | others | 2,163 | intel | arunjose696 | @@ -71,7 +71,8 @@ if pip show torch &>/dev/null; then
fi
if [ "$FORCE_REINSTALL" = false ]; then
echo "**** Exiting without action. ****"
- echo "**** INFO: Add --force-reinstall flag to force the PyTorch re-installation. ****"
+ echo "**** INFO: Run the install-pytorch script with the --force-reinstal... | ```suggestion
echo "**** INFO: Run the install-pytorch script with the --force-reinstall flag to force reinstallation of PyTorch,
``` |
intel-xpu-backend-for-triton | github_2023 | others | 2,163 | intel | YarShev | @@ -71,7 +71,8 @@ if pip show torch &>/dev/null; then
fi
if [ "$FORCE_REINSTALL" = false ]; then
echo "**** Exiting without action. ****"
- echo "**** INFO: Add --force-reinstall flag to force the PyTorch re-installation. ****"
+ echo "**** INFO: Run the install-pytorch script with the --force-reinstal... | ```suggestion
echo "**** INFO: Run the install-pytorch.sh script with the --force-reinstall flag to force reinstallation of PyTorch,
``` |
intel-xpu-backend-for-triton | github_2023 | others | 2,163 | intel | YarShev | @@ -125,7 +125,7 @@ fi
if [ "$TEST_BENCHMARK_SOFTMAX" = true ] || [ "$TEST_BENCHMARK_GEMM" = true ] || [ "$TEST_BENCHMARK_ATTENTION" = true ]; then
$SKIP_DEPS || $SCRIPTS_DIR/compile-pytorch-ipex.sh --pytorch --ipex --pinned --source $([ $VENV = true ] && echo "--venv")
else
- $SKIP_DEPS || $SCRIPTS_DIR/compile-p... | ```suggestion
$SKIP_DEPS || $SCRIPTS_DIR/install-pytorch.sh $([ $VENV = true ] && echo "--venv")
```
? |
intel-xpu-backend-for-triton | github_2023 | python | 2,154 | intel | LiyangLingIntel | @@ -86,22 +86,23 @@ def matmul_kernel_with_block_pointers(
configs=[
triton.Config(
{'BLOCK_SIZE_M': 256, 'BLOCK_SIZE_N': 256, 'BLOCK_SIZE_K': 32, 'GROUP_SIZE_M': 4, 'grf_mode': 'large'},
- num_stages=2, num_warps=32),
- triton.Config(
- {'BLOCK_SIZE_M': 256, 'BLO... | If we do not want more num_stages options, do we still need to use it here? |
intel-xpu-backend-for-triton | github_2023 | others | 2,028 | intel | pbchekin | @@ -51,6 +55,8 @@ jobs:
- name: Setup PyTorch
uses: ./.github/actions/setup-pytorch
+ with:
+ ref: ${{ inputs.pytorch_ref }} | Yes:
```
with:
repository: pytorch/pytorch
ref: ${{ inputs.pytorch_ref }}
```
Since we are planning to switch to upstream PyTorch we need to do the same for this workflow. |
intel-xpu-backend-for-triton | github_2023 | others | 2,151 | intel | pbchekin | @@ -138,6 +138,24 @@ jobs:
TAG=${{ inputs.tag || 'ci' }}
python ../../scripts/build_report.py $REPORTS/matmul-performance.csv $REPORTS/gemm-preop-exp-triton-report.csv --benchmark gemm-preop-exp --compiler triton --param_cols "B,M,K,N" --tflops_col Triton-TFlops --hbm_col "Triton-GB/s" --tag $TAG
... | It's the same benchmark as in the next step, copy & paste issue?
```suggestion
python gemm_postop_gelu_benchmark.py --reports $REPORTS
``` |
intel-xpu-backend-for-triton | github_2023 | python | 2,142 | intel | whitneywhtsang | @@ -62,8 +63,8 @@ def do_bench(fn, warmup=25, rep=100, grad_to_none=None, quantiles=None, fast_flu
estimate_ms = start_event.elapsed_time(end_event) / 5
# compute number of warmup and repeat
- n_warmup = max(warmup, int(warmup / estimate_ms)) | The change is to prevent running less number of times than requested. I am ok to revert, can you please check if there are any performance impact? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,061 | intel | whitneywhtsang | @@ -411,7 +411,6 @@ void PrefetchBlockPass::injectPrefetchOpsInBody(
auto prefetch =
b.create<ttgi::PrefetchOp>(loc, args[num + 1 + i], load.getCache(),
load.getEvict(), load.getIsVolatile());
- prefetchInsertPoint = prefetch; | This originally ensures that the next prefetch is inserted after the current prefetch. Why is it not good? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,061 | intel | whitneywhtsang | @@ -103,10 +103,12 @@ class ScheduleLoadPass
// HoHo, add fastmath for all
// may do this after llvm ir according to user fmath flag
mod.walk([&](Operation *op) {
- if (auto fmIf = dyn_cast<arith::ArithFastMathInterface>(op))
- op->setAttr(
- fmIf.getFastMathAttrName(),
- ... | What problem does adding fast math flag to `TruncFOp` create? accuracy failure? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,061 | intel | whitneywhtsang | @@ -170,6 +170,8 @@ unsigned ReduceOpHelper::getThreadsReductionAxis() {
bool ReduceOpHelper::isWarpSynchronous() {
auto srcLayout = getSrcLayout();
+ if (!srcLayout) | Can this change be upstreamed? |
intel-xpu-backend-for-triton | github_2023 | others | 2,061 | intel | whitneywhtsang | @@ -322,7 +324,7 @@ tt.func public @attn_fwd(%arg0: !tt.ptr<f16>, %arg1: !tt.ptr<f16>, %arg2: !tt.pt
%34 = arith.mulf %30, %24 : tensor<16x64xf32, #warp>
// CHECK: tt.expand_dims {{.*}} {axis = 1 : i32} : tensor<16xf32
- // CHECK: triton_intel_gpu.broadcast {{.*}} -> tensor<16x16xf32>
+ // CHECK: tt.b... | Why are we longer using `triton_intel_gpu.broadcast`? do we still need `triton_intel_gpu.broadcast`? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,061 | intel | whitneywhtsang | @@ -591,7 +591,7 @@ void MatchTargetSizePass::initNativeOperationSizes() {
nativeSizes.setDotShape(32, {8, 16, 8});
nativeSizes.setBlockMemShape(8, {16, 64, 32, 32});
- nativeSizes.setBlockMemShape(16, {32, 32, 32, 32});
+ nativeSizes.setBlockMemShape(16, {32, 32, 32, 16}); | How about this change, is it also a typo? |
intel-xpu-backend-for-triton | github_2023 | python | 2,071 | intel | pbchekin | @@ -729,7 +729,7 @@ def to_tensor(self, ret, dtype):
if hasattr(ret, "shape") and ret.shape:
ret_type = tl.block_type(dtype, ret.shape)
else:
- ret = np.array([ret], dtype=_get_np_dtype(dtype))
+ ret = np.array([ret]).astype(_get_np_dtype(dtype)) | Why is this not reproducible in upstream? |
intel-xpu-backend-for-triton | github_2023 | python | 2,071 | intel | pbchekin | @@ -665,8 +665,6 @@ def get_install_requires():
"autopep8",
"flake8",
"isort",
- # FIXME: pytorch<2.3.0 doesn't support numpy 2.0
- "numpy<2.0", | Keep "numpy" as test dependency as it's done in upstream (https://github.com/triton-lang/triton/blob/main/python/setup.py#L661). See also #2053. |
intel-xpu-backend-for-triton | github_2023 | others | 2,107 | intel | FMarno | @@ -141,4 +141,61 @@ def TTIG_BroadcastOp : TTIG_Op<"broadcast", [Pure, SameOperandsAndResultElementT
}];
}
+class IsLocalPointerToElementType<string pointer, string value, string summary> :
+ TypesMatchWith<summary, value, pointer, [{
+ ::mlir::triton::PointerType::get( }] # ElementType<"_self">.result #... | ```suggestion
within sub-groups.
``` |
intel-xpu-backend-for-triton | github_2023 | others | 2,107 | intel | FMarno | @@ -141,4 +141,61 @@ def TTIG_BroadcastOp : TTIG_Op<"broadcast", [Pure, SameOperandsAndResultElementT
}];
}
+class IsLocalPointerToElementType<string pointer, string value, string summary> :
+ TypesMatchWith<summary, value, pointer, [{
+ ::mlir::triton::PointerType::get( }] # ElementType<"_self">.result #... | This only works for a tensor that is size `subgroup_size by subgroup_size`, right? maybe that should be mentioned |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,107 | intel | FMarno | @@ -578,6 +578,58 @@ class BroadcastOpConversion
}
};
+class SubGroupTransposeOpConversion
+ : public ConvertTritonGPUOpToLLVMPattern<SubGroupTransposeOp> {
+public:
+ using ConvertTritonGPUOpToLLVMPattern<
+ SubGroupTransposeOp>::ConvertTritonGPUOpToLLVMPattern;
+
+ LogicalResult
+ matchAndRewrite(Sub... | Did you ever consider transposing on the read instead of the write?
Or maybe just using the SIMDBlockRead instead of a load? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,107 | intel | whitneywhtsang | @@ -578,6 +578,58 @@ class BroadcastOpConversion
}
};
+class SubGroupTransposeOpConversion
+ : public ConvertTritonGPUOpToLLVMPattern<SubGroupTransposeOp> {
+public:
+ using ConvertTritonGPUOpToLLVMPattern<
+ SubGroupTransposeOp>::ConvertTritonGPUOpToLLVMPattern;
+
+ LogicalResult
+ matchAndRewrite(Sub... | should the two early return failures be part of operation verifier? as they should not be generated in the first place. |
intel-xpu-backend-for-triton | github_2023 | others | 2,107 | intel | etiotto | @@ -141,4 +141,64 @@ def TTIG_BroadcastOp : TTIG_Op<"broadcast", [Pure, SameOperandsAndResultElementT
}];
}
+class IsLocalPointerToElementType<string pointer, string value, string summary> :
+ TypesMatchWith<summary, value, pointer, [{
+ ::mlir::triton::PointerType::get( }] # ElementType<"_self">.result #... | The matrix should be square so the rows should contain `sub_group_size-1` elements but they contain 2 elements. |
intel-xpu-backend-for-triton | github_2023 | others | 2,107 | intel | etiotto | @@ -141,4 +141,64 @@ def TTIG_BroadcastOp : TTIG_Op<"broadcast", [Pure, SameOperandsAndResultElementT
}];
}
+class IsLocalPointerToElementType<string pointer, string value, string summary> :
+ TypesMatchWith<summary, value, pointer, [{
+ ::mlir::triton::PointerType::get( }] # ElementType<"_self">.result #... | I don't understand. Where is the layout ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,127 | intel | etiotto | @@ -125,13 +125,13 @@ LogicalResult printLayoutFromFile(MLIRContext *context, StringRef filename,
if (names.empty())
// If no alias name is given, we print all layout attributes in the file.
- for (auto def : asmState.getAttributeAliasDefs()) {
+ for (const auto &def : asmState.getAttributeAliasDefs()) ... | If you want to make this change we should upstream it to avoid diverging. |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,127 | intel | etiotto | @@ -253,10 +253,6 @@ verify2DBlockLoadHWRestriction(TritonGEN::Matrix2DBlockLoadOp op) {
return op.emitOpError("expecting tile_height to be between 1 and 32");
if (tileWidth < 1 || tileWidth > 8)
return op.emitOpError("expecting tile_width to be between 1 and 8");
- if (tileWidth * vBlocks... | Thanks for the comment, very useful during code review. |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,127 | intel | whitneywhtsang | @@ -201,9 +201,6 @@ struct PrintOpConversion
std::string prefix = "%";
if (width.has_value()) {
prefix += std::to_string(*width);
- } else if (hex) {
- prefix += "0";
- prefix += std::to_string(type.getIntOrFloatBitWidth() / 4); | can we upstream this change in common `PrintOpToLLVM.cpp` as well? |
intel-xpu-backend-for-triton | github_2023 | others | 2,108 | intel | etiotto | @@ -59,18 +59,20 @@ module {
%39 = tt.dot %37, %38, %arg10 {inputPrecision = 0 : i32, maxNumImpreciseAcc = 0 : i32} : tensor<32x32xf16, #dot0_> * tensor<32x64xf16, #dot1_> -> tensor<32x64xf32, #warp>
// CHECK: scf.for
// CHECK: [[A:%.*]] = tt.load {{.*}} : !tt.ptr<tensor<32x32xf16>>
- // CHECK... | Need to add a lit test to show that if the loop is marked as a GEMM loop (triton_gpu.workload = 3) the loads of the tt.dot operands has larger size. |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,108 | intel | etiotto | @@ -5,6 +5,16 @@
namespace mlir {
+constexpr static char AttrWorkloadName[] = "triton_gpu.workload";
+enum class Workload {
+ // TODO: add more
+ None = 0, // pattern not match any of below
+ ElementWise = 1,
+ Reduction = 2, | Do we have lit tests to check enum values 1 and 2 ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,108 | intel | etiotto | @@ -51,6 +51,8 @@
#include "intel/include/Dialect/TritonGEN/IR/TritonGENDialect.h"
#include "intel/include/Dialect/TritonIntelGPU/IR/Dialect.h"
#include "intel/include/Dialect/TritonIntelGPU/Transforms/Passes.h"
+// For Workload | remove comment |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,734 | intel | victor-eds | @@ -128,7 +128,7 @@ class CallOpConversion : public mlir::RewritePattern {
auto operands = callOp.getOperands();
auto result = callOp.getResult();
- LLVM::LLVMFunctionType calleeType = callOp.getCalleeType().value();
+ LLVM::LLVMFunctionType calleeType = callOp.getVarCalleeType().value(); | Might be wrong, but this looks like it's querying indirect calls call types? |
intel-xpu-backend-for-triton | github_2023 | others | 1,734 | intel | whitneywhtsang | @@ -14,6 +14,7 @@ add_triton_plugin(TritonXPU
TritonIntelGPUToLLVM
TritonIntelGPUTransforms
TritonToTritonGPUWarp
+ MLIRGPUToLLVMSPV | alphabetical order? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,734 | intel | whitneywhtsang | @@ -262,6 +263,8 @@ class TritonGPUToLLVMPipelineManager {
triton::populateTritonGENToLLVMConversionPatterns(typeConverter, patterns);
triton::populateGPUToTritonGENConversionPatterns(typeConverter, patterns);
cf::populateControlFlowToLLVMConversionPatterns(typeConverter, patterns);
+
+ mlir::populate... | [optional]
```suggestion
populateGpuToLLVMSPVConversionPatterns(typeConverter, patterns);
``` |
intel-xpu-backend-for-triton | github_2023 | others | 1,734 | intel | etiotto | @@ -18,7 +18,7 @@ module attributes {"triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 32
// CHECK-DAG: %[[CST_16:.*]] = llvm.mlir.constant(16 : i32) : i32
// CHECK-DAG: %[[CST_0:.*]] = llvm.mlir.constant(0 : i32) : i32
// COM: The following operations is generated for the con... | The linkage is gone. Any difference in the generate LLVM IR for the call site (compared to using passthrough attributes) ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,734 | intel | etiotto | @@ -210,22 +210,16 @@ static void populateOpPatterns(LLVMTypeConverter &converter,
void mlir::triton::populateGPUToTritonGENConversionPatterns(
LLVMTypeConverter &converter, RewritePatternSet &patterns) {
populateWithGenerated(patterns);
- patterns.add<GPUBarrierOpLowering, GPUSubgroupReduceOpLowering>(conver... | Add FIXME here to indicate the TritonGEN dialect operations that should be removed. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,734 | intel | etiotto | @@ -2172,10 +2172,9 @@ struct IndexCastOpLowering
if (targetBits == sourceBits)
return {operands[0][0]};
if (targetBits < sourceBits)
- return {rewriter.replaceOpWithNewOp<LLVM::TruncOp>(op, elemTy,
- operands[0][0])};
- return {
- ... | Aren't these 2 lines going to gen. the same code as before ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 188 | intel | etiotto | @@ -0,0 +1,396 @@
+/*========================== begin_copyright_notice ============================
+
+Copyright (C) 2023 Intel Corporation
+
+SPDX-License-Identifier: MIT
+
+============================= end_copyright_notice ===========================*/ | I think we should use the same copyright as Triton:
```
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 188 | intel | etiotto | @@ -0,0 +1,396 @@
+/*========================== begin_copyright_notice ============================
+
+Copyright (C) 2023 Intel Corporation
+
+SPDX-License-Identifier: MIT
+
+============================= end_copyright_notice ===========================*/
+#pragma once
+
+// #include "common/LLVMWarningsPush.hpp" | Remove commented out code. |
intel-xpu-backend-for-triton | github_2023 | cpp | 188 | intel | etiotto | @@ -0,0 +1,74 @@
+/*========================== begin_copyright_notice ============================
+
+Copyright (C) 2017-2021 Intel Corporation
+
+SPDX-License-Identifier: MIT
+
+============================= end_copyright_notice ===========================*/ | I think we should use:
```
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
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