repo_name stringlengths 1 62 | dataset stringclasses 1
value | lang stringclasses 11
values | pr_id int64 1 20.1k | owner stringlengths 2 34 | reviewer stringlengths 2 39 | diff_hunk stringlengths 15 262k | code_review_comment stringlengths 1 99.6k |
|---|---|---|---|---|---|---|---|
intel-xpu-backend-for-triton | github_2023 | python | 1,857 | intel | pbchekin | @@ -10,17 +12,61 @@
ze_root = os.getenv("ZE_PATH", default="/usr/local")
include_dir = [os.path.join(ze_root, "include")]
-oneapi_root = os.getenv("ONEAPI_ROOT")
-if oneapi_root:
- include_dir += [
- os.path.join(oneapi_root, "compiler/latest/include"),
- os.path.join(oneapi_root, "compiler/latest/... | Nit:
```suggestion
if tuple(map(eval, sycl_rt.get("version").split("."))) < (2025, 0, 0):
``` |
intel-xpu-backend-for-triton | github_2023 | python | 1,857 | intel | pbchekin | @@ -10,17 +12,61 @@
ze_root = os.getenv("ZE_PATH", default="/usr/local")
include_dir = [os.path.join(ze_root, "include")]
-oneapi_root = os.getenv("ONEAPI_ROOT")
-if oneapi_root:
- include_dir += [
- os.path.join(oneapi_root, "compiler/latest/include"),
- os.path.join(oneapi_root, "compiler/latest/... | Nit:
```suggestion
for f in importlib.metadata.files("intel-sycl-rt"):
``` |
intel-xpu-backend-for-triton | github_2023 | python | 1,857 | intel | pbchekin | @@ -10,17 +12,61 @@
ze_root = os.getenv("ZE_PATH", default="/usr/local")
include_dir = [os.path.join(ze_root, "include")]
-oneapi_root = os.getenv("ONEAPI_ROOT")
-if oneapi_root:
- include_dir += [
- os.path.join(oneapi_root, "compiler/latest/include"),
- os.path.join(oneapi_root, "compiler/latest/... | ```suggestion
if f.name == "libsycl.so":
library_dir += [f.locate().parent.as_posix()]
``` |
intel-xpu-backend-for-triton | github_2023 | python | 1,857 | intel | vlad-penkin | @@ -1,26 +1,74 @@
+import importlib.metadata
import os
import hashlib
+import shutil
import tempfile
from pathlib import Path
from triton.runtime.build import _build
from triton.runtime.cache import get_cache_manager
from triton.backends.compiler import GPUTarget
from triton.backends.driver import DriverBase
+f... | ```suggestion
sycl_ver = Version(sycl_rt.get("version", "0.0.0"))
``` |
intel-xpu-backend-for-triton | github_2023 | python | 1,857 | intel | vlad-penkin | @@ -1,26 +1,74 @@
+import importlib.metadata
import os
import hashlib
+import shutil
import tempfile
from pathlib import Path
from triton.runtime.build import _build
from triton.runtime.cache import get_cache_manager
from triton.backends.compiler import GPUTarget
from triton.backends.driver import DriverBase
+f... | ```suggestion
from packaging.specifiers import SpecifierSet
``` |
intel-xpu-backend-for-triton | github_2023 | python | 1,857 | intel | vlad-penkin | @@ -1,26 +1,74 @@
+import importlib.metadata
import os
import hashlib
+import shutil
import tempfile
from pathlib import Path
from triton.runtime.build import _build
from triton.runtime.cache import get_cache_manager
from triton.backends.compiler import GPUTarget
from triton.backends.driver import DriverBase
+f... | ```suggestion
if sycl_ver in SpecifierSet("<2025.0.0a1"):
``` |
intel-xpu-backend-for-triton | github_2023 | python | 1,857 | intel | vlad-penkin | @@ -1,26 +1,74 @@
+import importlib.metadata
import os
import hashlib
+import shutil
import tempfile
from pathlib import Path
from triton.runtime.build import _build
from triton.runtime.cache import get_cache_manager
from triton.backends.compiler import GPUTarget
from triton.backends.driver import DriverBase
+f... | ```suggestion
"or install intel-sycl-rt>=2025.0.0 wheel"
) # yapf: disable
``` |
intel-xpu-backend-for-triton | github_2023 | python | 1,857 | intel | anmyachev | @@ -1,26 +1,74 @@
+import importlib.metadata
import os
import hashlib
+import shutil
import tempfile
from pathlib import Path
from triton.runtime.build import _build
from triton.runtime.cache import get_cache_manager
from triton.backends.compiler import GPUTarget
from triton.backends.driver import DriverBase
+f... | ```suggestion
include_dir, library_dir = find_sycl(include_dir)
``` |
intel-xpu-backend-for-triton | github_2023 | python | 1,857 | intel | anmyachev | @@ -1,26 +1,74 @@
+import importlib.metadata
import os
import hashlib
+import shutil
import tempfile
from pathlib import Path
from triton.runtime.build import _build
from triton.runtime.cache import get_cache_manager
from triton.backends.compiler import GPUTarget
from triton.backends.driver import DriverBase
+f... | ```suggestion
def find_sycl(include_dir: list[str]) -> tuple[list[str], list[str]]:
``` |
intel-xpu-backend-for-triton | github_2023 | python | 1,857 | intel | anmyachev | @@ -1,26 +1,74 @@
+import importlib.metadata
import os
import hashlib
+import shutil
import tempfile
from pathlib import Path
from triton.runtime.build import _build
from triton.runtime.cache import get_cache_manager
from triton.backends.compiler import GPUTarget
from triton.backends.driver import DriverBase
+f... | If a function return values, you should not change the implicitly passed values, such side effect is not expected.
```suggestion
"""
library_dir = []
include_dir = include_dir.copy()
``` |
intel-xpu-backend-for-triton | github_2023 | python | 1,857 | intel | anmyachev | @@ -1,26 +1,74 @@
+import importlib.metadata
import os
import hashlib
+import shutil
import tempfile
from pathlib import Path
from triton.runtime.build import _build
from triton.runtime.cache import get_cache_manager
from triton.backends.compiler import GPUTarget
from triton.backends.driver import DriverBase
+f... | ```suggestion
``` |
intel-xpu-backend-for-triton | github_2023 | python | 1,857 | intel | anmyachev | @@ -1,26 +1,74 @@
+import importlib.metadata
import os
import hashlib
+import shutil
import tempfile
from pathlib import Path
from triton.runtime.build import _build
from triton.runtime.cache import get_cache_manager
from triton.backends.compiler import GPUTarget
from triton.backends.driver import DriverBase
+f... | Why is this branch needed if the next step is to check `ONEAPI_ROOT` environment variable? |
intel-xpu-backend-for-triton | github_2023 | python | 1,857 | intel | anmyachev | @@ -1,26 +1,74 @@
+import importlib.metadata
import os
import hashlib
+import shutil
import tempfile
from pathlib import Path
from triton.runtime.build import _build
from triton.runtime.cache import get_cache_manager
from triton.backends.compiler import GPUTarget
from triton.backends.driver import DriverBase
+f... | The general practice is to save the long exception message in a variable and then use it when throwing exceptions:
```python
message = "long long message"
# case 1
raise AssertionError(message)
# case 2 similar to case 1
raise AssertionError(message)
``` |
intel-xpu-backend-for-triton | github_2023 | python | 2,009 | intel | anmyachev | @@ -431,3 +420,12 @@ def set_gpu_clock(ref_sm_clock=1350, ref_mem_clock=1215):
subprocess.check_output(["nvidia-smi", "-i", "0", "-pm", "0"])
subprocess.check_output(["nvidia-smi", "-i", "0", "-rgc"])
subprocess.check_output(["nvidia-smi", "-i", "0", "-rmc"])
+
+
+def nvsmi(attrs): | Where does this function come from? |
intel-xpu-backend-for-triton | github_2023 | python | 2,009 | intel | anmyachev | @@ -53,10 +53,12 @@ def _kernel(A, B, C, #
a = tl.load(a_block_ptr)
b = tl.load(b_block_ptr)
else:
- k_remaining = K - k * (BLOCK_K * SPLIT_K)
- _0 = tl.zeros((1, 1), dtype=C.dtype.element_ty)
- a = tl.load(a_block_ptr, mask=rk[None, :] < k_remaining,... | Could you create an issue and link to it here? |
intel-xpu-backend-for-triton | github_2023 | python | 1,879 | intel | etiotto | @@ -280,6 +280,7 @@ def make_spv(src, metadata, options):
metadata["build_flags"] = "-cl-intel-enable-auto-large-GRF-mode"
else:
metadata["build_flags"] = ""
+ metadata["build_flags"] += " -cl-fp64-gen-emu" | This change will cause IGC to use fp64 emulation on all target architectures (so not just on MTL).
What we want is to pass this flags only when the target architecture doesn't support fp64 natively. |
intel-xpu-backend-for-triton | github_2023 | others | 1,879 | intel | pbchekin | @@ -269,6 +269,16 @@ jobs:
export WORKSPACE=$GITHUB_WORKSPACE
cd pytorch
pip install pyyaml pandas scipy numpy psutil pyre_extensions torchrec
+
+ # `runner_label` takes precedence over `device`, so this is how we check
+ # that the workflow is definitely executed on A... | The most reliable way to detect A770 at the moment:
```
source ./scripts/capture-hw-details.sh
if [[ $GPU_DEVICE = *A770* ]]; then
...
fi
``` |
intel-xpu-backend-for-triton | github_2023 | others | 1,991 | intel | pbchekin | @@ -63,6 +63,15 @@ repos:
files: ^.github/workflows/integration-tests.yml.*
pass_filenames: false
+ - repo: https://github.com/PyCQA/bandit
+ rev: '1.7.9'
+ hooks:
+ - id: bandit
+ files: '^(benchmarks|scripts|third_party/intel)/.*\.py$'
+ args: ["-c", "bandit.yaml", "-s", "B404,B603... | `additional_dependencies` not needed |
intel-xpu-backend-for-triton | github_2023 | others | 1,982 | intel | pbchekin | @@ -74,11 +74,13 @@ jobs:
echo "REPORTS=$PWD/reports" >> $GITHUB_ENV
- name: Install benchmarks
+ id: install
run: |
cd benchmarks
python setup.py install
- name: Run Triton Softmax kernel benchmark
+ if: ${{ steps.install.outcome == 'success' &&... | Out of curiosity, have you tried
```suggestion
if: ${{ steps.install.outcome == 'success' && !cancelled() }}
``` |
intel-xpu-backend-for-triton | github_2023 | python | 1,962 | intel | pbchekin | @@ -48,7 +49,8 @@ def transform_df(df, param_cols, tflops_col, hbm_col, benchmark, compiler, tag):
n: os.getenv(n.upper(), default="")
for n in ["libigc1_version", "level_zero_version", "gpu_device", "agama_version"]
}
- assert host_info['gpu_device'], "Could not find GPU device description, w... | Let's use consistent quotes within the file
```suggestion
if not host_info["gpu_device"]:
``` |
intel-xpu-backend-for-triton | github_2023 | python | 1,962 | intel | pbchekin | @@ -59,11 +59,11 @@ def __post_init__(self):
str(default_libdir / 'libsycl-spir64-unknown-unknown.bc'))
object.__setattr__(self, 'extern_libs', tuple(extern_libs.items()))
assert self.num_warps > 0 and (self.num_warps & (self.num_warps - 1)) == 0, \
- ... | Why do we keep this `assert`? It is used for runtime validation and this is not a test. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,919 | intel | whitneywhtsang | @@ -50,47 +50,32 @@ class ScheduleLoadPass
mod.walk<WalkOrder::PreOrder>([&](scf::ForOp loop) {
visited.clear();
int group = -1;
- unsigned numGroups = 0;
- SmallVector<SmallVector<tt::DotOp>> dotsGroup;
+ SmallVector<std::pair<SmallVector<tt::DotOp>, int>> dotsGroup;
SmallVecto... | ```suggestion
auto [dots, groupId] = dotsGroup;
``` |
intel-xpu-backend-for-triton | github_2023 | others | 1,919 | intel | etiotto | @@ -180,3 +184,182 @@ module attributes {"triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 8 :
tt.return
}
}
+
+// -----
+// COM: Inst Schedule for GEMM case
+
+module attributes {"triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 32 : i32, "triton_gpu.threads-per-warp" = 16 : i32, triton_intel_... | I have another PR where I have simplified the first test. This new GEMM test can also be similarly simplified (remove attributes that aren't required, remove code that isn't required e.g. the stores at the end and any operation that can be made dead without altering the functionality of the test). |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,919 | intel | FMarno | @@ -50,47 +50,31 @@ class ScheduleLoadPass
mod.walk<WalkOrder::PreOrder>([&](scf::ForOp loop) {
visited.clear();
int group = -1;
- unsigned numGroups = 0;
- SmallVector<SmallVector<tt::DotOp>> dotsGroup;
+ SmallVector<std::pair<SmallVector<tt::DotOp>, int>> dotsGroup; | Why was this changed to a pair? the second value doesn't seem to be used |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,919 | intel | FMarno | @@ -61,36 +60,19 @@ class ScheduleLoadPass
dotsGroup.push_back(dots);
dots.clear();
}
- // mark first dot B as visited to not move
- if (currGroup == 0) {
- SmallVector<tt::DotOp> vec{dot};
- getNotVisitedUses(vec, 1);
- // a new set of schedule-gr... | instead of calling `getNotVisitedUses` twice, consider removing the `opIdx` arg and just doing two loops in the `getNotVisitedUses` function call. |
intel-xpu-backend-for-triton | github_2023 | others | 1,963 | intel | pbchekin | @@ -17,6 +17,18 @@ jobs:
- name: Checkout repository
uses: actions/checkout@v4
+ - name: Load pip cache | You are loading cache here but there is no save operation in the file. Not a big issue but mostly useless. |
intel-xpu-backend-for-triton | github_2023 | python | 1,654 | intel | whitneywhtsang | @@ -46,6 +46,7 @@ class XPUOptions:
allowed_dot_input_precisions: Tuple[str] = ("tf32", "tf32x3", "ieee")
allow_fp8e4nv: bool = False
allow_fp8e4b15: bool = True
+ grf_mode: tuple = ('small', 'large', 'default') | Do we want to support auto? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,654 | intel | whitneywhtsang | @@ -40,15 +46,18 @@ bool getBoolEnv(const std::string &env) {
std::tuple<ze_module_handle_t, ze_result_t>
create_module(ze_context_handle_t context, ze_device_handle_t device,
- uint32_t *binary_ptr, size_t binary_size) {
- const char *build_flags = "";
+ uint8_t *binary_ptr, size_t binar... | message for assertions? |
intel-xpu-backend-for-triton | github_2023 | c | 1,654 | intel | victor-eds | @@ -132,31 +131,64 @@ static PyObject *loadBinary(PyObject *self, PyObject *args) {
size_t binary_size = PyBytes_Size(py_bytes);
binary_size = binary_size / sizeof(uint32_t);
- uint32_t *binary_ptr = (uint32_t *)PyBytes_AsString(py_bytes);
- ;
+ uint8_t *binary_ptr = (uint8_t *)PyBytes_AsString(py_bytes);
... | ```suggestion
std::string buid_flags_str(build_flags);
```
NIT |
intel-xpu-backend-for-triton | github_2023 | python | 1,782 | intel | etiotto | @@ -24,7 +24,10 @@ def _path_to_binary(binary: str):
for p in paths:
bin = p.split(" ")[0]
if os.path.exists(bin) and os.path.isfile(bin):
- result = subprocess.check_output([bin, "--version"], stderr=subprocess.STDOUT)
+ try: | Why is this change in this PR ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,782 | intel | etiotto | @@ -287,6 +287,15 @@ DpasEncodingAttr::getSizePerThreadForOperands(unsigned opIdx) const {
}
}
+SmallVector<unsigned> DpasEncodingAttr::getElemsPerThreadForOperands(
+ ArrayRef<int64_t> shape, Type eltTy, unsigned opIdx) const {
+ SmallVector<unsigned> sizePerThread = getSizePerThreadForOperands(opIdx);
+ Sm... | do you really need the 2 c-style casts ? the SmallVector element type is unsigned so the cast should happen implicitly. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,782 | intel | etiotto | @@ -222,38 +222,33 @@ emitOffsetForDotOpLayout(const DotOperandEncodingAttr &dotLayout,
unsigned executionSize = dpasLayout.getExecutionSize();
unsigned opsPerChannel = dpasLayout.getOpsPerChannel();
- unsigned numRowsPerValue = 0u, numColsPerValue = 0u, packedOpsPerLane = 0u;
+ unsigned numRowsPerPackedValue... | remove this line |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,782 | intel | etiotto | @@ -455,6 +456,35 @@ emitOffsetForSliceLayout(const SliceEncodingAttr &sliceLayout,
// fewer than getTotalElementsPerThread() elements. In that case repeat the
// sequence.
int elemsPerThread = triton::gpu::getTotalElemsPerThread(type);
+
+ // llvm::outs() << "johnlu slice layout emit offset type:" << type ... | remove commented out code please |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,845 | intel | etiotto | @@ -21,9 +21,45 @@ void decomposeSplatOpToSharedLayoutConversion(ModuleOp module);
/// given |module| op, but bypass the decomposition if |shortcutFn| returns
/// true.
using ShortcutFn = std::function<bool(RankedTensorType &, RankedTensorType &)>;
+
+namespace {
+inline void addAttrs(Operation *op, ArrayRef<mlir::N... | Adding the definition here diverges from upstream |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,845 | intel | etiotto | @@ -21,9 +21,45 @@ void decomposeSplatOpToSharedLayoutConversion(ModuleOp module);
/// given |module| op, but bypass the decomposition if |shortcutFn| returns
/// true.
using ShortcutFn = std::function<bool(RankedTensorType &, RankedTensorType &)>;
+
+namespace {
+inline void addAttrs(Operation *op, ArrayRef<mlir::N... | This is not in the upstream file so adding it here makes the file diverge more from the upstream version |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,845 | intel | whitneywhtsang | @@ -14,136 +16,18 @@ namespace mlir::triton::gpu::intel {
namespace {
-// pass ws related named attrs.
-static void addAttrs(Operation *op, ArrayRef<NamedAttribute> attrs) {
- for (const NamedAttribute attr : attrs)
- op->setAttr(attr.getName(), attr.getValue());
-}
-
struct DecomposeUnsupportedConversions
... | [nit] to be consistent with NVidia version.
```suggestion
triton::gpu::decomposeSplatOpToSharedLayoutConversion(mod);
triton::gpu::decomposeTensorCoreToDotLayoutConversion(mod,
isDpasToDotShortcut);
triton::gpu::decomposeBlockedToDotLayoutConver... |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,808 | intel | etiotto | @@ -24,7 +24,12 @@ void postProcessLLVMIR(llvm::Module &mod) {
break;
}
};
-
+ for (auto &f : mod) { | Add an explanation of why we need this code (a comment). |
intel-xpu-backend-for-triton | github_2023 | others | 1,698 | intel | whitneywhtsang | @@ -0,0 +1,33 @@
+// RUN: triton-opt %s -split-input-file --tritonintelgpu-reduce-data-duplication | FileCheck %s
+
+#blocked = #triton_gpu.blocked<{sizePerThread = [4, 1], threadsPerWarp = [16, 1], warpsPerCTA = [1, 32], order = [0, 1]}>
+#mma1 = #triton_intel_gpu.dpas<{repeatCount = 8, systolicDepth = 8, executionSiz... | Please cleanup all the location info. |
intel-xpu-backend-for-triton | github_2023 | others | 1,698 | intel | whitneywhtsang | @@ -243,4 +243,15 @@ def TritonIntelGPUMatchTargetSize : Pass<"tritonintelgpu-match-target-size", "ml
"mlir::triton::gpu::intel::TritonIntelGPUDialect"];
}
+def TritonIntelGPUReduceDataDuplication: Pass<"tritonintelgpu-reduce-data-duplication", "mlir::ModuleOp"> {
+ let summary = "Reduce... | Can you please mention the difference between the TritonGPUReduceDataDuplication and TritonIntelGPUReduceDataDuplication, i.e., Intel DPAS layout handling? |
intel-xpu-backend-for-triton | github_2023 | others | 1,656 | intel | Dewei-Wang-sh | @@ -853,7 +853,7 @@ def TT_MakeTensorPtrOp : TT_Op<"make_tensor_ptr",
SameVariadicOperandSize,
TypesMatchWith<"infer pointer type from the result type",
"result", "base",
- ... | upstream pr created https://github.com/triton-lang/triton/pull/4407 |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,656 | intel | Dewei-Wang-sh | @@ -137,6 +137,74 @@ class MatchTargetSizePass
MLIRContext *ctx = &getContext();
ModuleOp m = getOperation();
+ // this is ad-hoc for Q SLM
+ char *env = std::getenv("TRITON_INTEL_ENABLE_SLM"); | how about defining it in getenv.hpp? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,656 | intel | victor-eds | @@ -843,7 +927,22 @@ void MatchTargetSizePass::transformGenericOp(Operation *op) {
llvm_unreachable("Unexpected operation");
}
- auto [shape, subType, subSize] = getSubTypeAndShape(type);
+ // for attension SLM
+ bool useSLM = false;
+ if (auto store = dyn_cast<tt::StoreOp>(op)) {
+ auto ptrTy = store.... | Can we use the `getAddrspace` you introduced here? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,656 | intel | victor-eds | @@ -137,6 +137,74 @@ class MatchTargetSizePass
MLIRContext *ctx = &getContext();
ModuleOp m = getOperation();
+ // this is ad-hoc for Q SLM
+ char *env = std::getenv("TRITON_INTEL_ENABLE_SLM");
+ const bool enableSLM = env ? (bool)std::atoi(env) : false;
+ if (enableSLM) {
+ dotWithSLMOpera... | This hack won't play well with my hack in #1735. I'll work on a fix when you get this merged. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,656 | intel | etiotto | @@ -22,7 +22,9 @@ unsigned getPointeeBitWidth(Type type);
Type getPointeeType(Type type);
-Type getPointerType(Type type);
+Type getPointerType(Type type, unsigned addressSpace = 1); | Need to upstream this change. Pls post a PR upstream. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,656 | intel | etiotto | @@ -157,7 +157,15 @@ Type getPointerTypeSameShape(Type type) {
}
}
-Type getPointerType(Type type) { return PointerType::get(type, 1); }
+Type getPointerType(Type type, unsigned addressSpace) {
+ return PointerType::get(type, addressSpace);
+}
+
+unsigned getAddrspace(Type type) { | This make sense only for pointer types. I think you can avoid having this utility function. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,656 | intel | etiotto | @@ -122,6 +124,10 @@ class LoadStorePrefetchOpConversion
ConversionPatternRewriter &rewriter) const override {
auto ptrType = cast<PointerType>(op.getPtr().getType());
auto tensorType = cast<RankedTensorType>(ptrType.getPointeeType());
+ auto addrSpace = ptrType.getAddressSpace(); | auto -> unsigned |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,656 | intel | etiotto | @@ -162,7 +168,57 @@ class LoadStorePrefetchOpConversion
Location loc = op.getLoc();
Value bytes =
i32_val(tensorType.getElementType().getIntOrFloatBitWidth() / 8);
-
+ if (isLocalSpace) {
+ Value llPtr = adaptor.getPtr();
+ // sg_size(16) x i64 = 64 x i16
+ VectorType v64i16Ty = Ve... | Use: `ptr_ty(rewriter.getContext(), 3)` to create the pointer, assign it to a variable and use that variable at line 183 as well. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,656 | intel | etiotto | @@ -162,7 +168,57 @@ class LoadStorePrefetchOpConversion
Location loc = op.getLoc();
Value bytes =
i32_val(tensorType.getElementType().getIntOrFloatBitWidth() / 8);
-
+ if (isLocalSpace) {
+ Value llPtr = adaptor.getPtr();
+ // sg_size(16) x i64 = 64 x i16
+ VectorType v64i16Ty = Ve... | use `constexpr StringRef` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,656 | intel | etiotto | @@ -162,7 +168,57 @@ class LoadStorePrefetchOpConversion
Location loc = op.getLoc();
Value bytes =
i32_val(tensorType.getElementType().getIntOrFloatBitWidth() / 8);
-
+ if (isLocalSpace) {
+ Value llPtr = adaptor.getPtr();
+ // sg_size(16) x i64 = 64 x i16
+ VectorType v64i16Ty = Ve... | else if -> if (after previous is returns) |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,656 | intel | etiotto | @@ -162,7 +168,57 @@ class LoadStorePrefetchOpConversion
Location loc = op.getLoc();
Value bytes =
i32_val(tensorType.getElementType().getIntOrFloatBitWidth() / 8);
-
+ if (isLocalSpace) {
+ Value llPtr = adaptor.getPtr();
+ // sg_size(16) x i64 = 64 x i16
+ VectorType v64i16Ty = Ve... | use `constexpr` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,656 | intel | etiotto | @@ -660,7 +738,12 @@ void MatchTargetSizePass::transformReduceOp(tt::ReduceOp op) {
void MatchTargetSizePass::transformMakeTensorPtrOp(tt::MakeTensorPtrOp op) {
Type resultType = op.getResult().getType();
- auto [shape, subType, subSize] = getSubTypeAndShape(resultType);
+ bool useSLM = false;
+ if (cast<tt::P... | ```suggestion
bool useSLM = (cast<tt::PointerType>(resultType).getAddressSpace() == 3);
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,656 | intel | etiotto | @@ -843,7 +927,22 @@ void MatchTargetSizePass::transformGenericOp(Operation *op) {
llvm_unreachable("Unexpected operation");
}
- auto [shape, subType, subSize] = getSubTypeAndShape(type);
+ // for attension SLM
+ bool useSLM = false;
+ if (auto store = dyn_cast<tt::StoreOp>(op)) {
+ auto ptrTy = store.... | ```suggestion
useSLM = (cast<tt::PointerType>(ptrTy).getAddressSpace() == 3) ;
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,656 | intel | etiotto | @@ -843,7 +927,22 @@ void MatchTargetSizePass::transformGenericOp(Operation *op) {
llvm_unreachable("Unexpected operation");
}
- auto [shape, subType, subSize] = getSubTypeAndShape(type);
+ // for attension SLM
+ bool useSLM = false;
+ if (auto store = dyn_cast<tt::StoreOp>(op)) {
+ auto ptrTy = store.... | ```suggestion
useSLM = (cast<tt::PointerType>(ptrTy).getAddressSpace() == 3) ;
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,656 | intel | etiotto | @@ -122,6 +124,10 @@ class LoadStorePrefetchOpConversion
ConversionPatternRewriter &rewriter) const override {
auto ptrType = cast<PointerType>(op.getPtr().getType());
auto tensorType = cast<RankedTensorType>(ptrType.getPointeeType());
+ auto addrSpace = ptrType.getAddressSpace();
+ c... | Comparing to the "magic number" 3 isn't ideal. We should compare to an enum instead.
We can use TritonGENMemorySpace::kWorkgroup |
intel-xpu-backend-for-triton | github_2023 | others | 1,656 | intel | etiotto | @@ -0,0 +1,62 @@
+// RUN: env TRITON_INTEL_ENABLE_SLM=1 triton-opt %s -split-input-file -tritonintelgpu-match-target-size | FileCheck %s --check-prefix=SLM-CHECK
+
+#warp = #triton_intel_gpu.warp<{sizePerThread = [32, 64], threadsPerWarp = [1, 1], order = [1, 0]}>
+#dot0_ = #triton_gpu.dot_op<{opIdx = 0, parent = #warp... | Remove attribute noinline, location information and tt.divisibility if not needed. |
intel-xpu-backend-for-triton | github_2023 | others | 1,656 | intel | etiotto | @@ -0,0 +1,62 @@
+// RUN: env TRITON_INTEL_ENABLE_SLM=1 triton-opt %s -split-input-file -tritonintelgpu-match-target-size | FileCheck %s --check-prefix=SLM-CHECK | check-prefix isn't required because this file contains only "SLM-CHECKs" |
intel-xpu-backend-for-triton | github_2023 | others | 1,656 | intel | etiotto | @@ -0,0 +1,62 @@
+// RUN: env TRITON_INTEL_ENABLE_SLM=1 triton-opt %s -split-input-file -tritonintelgpu-match-target-size | FileCheck %s --check-prefix=SLM-CHECK
+
+#warp = #triton_intel_gpu.warp<{sizePerThread = [32, 64], threadsPerWarp = [1, 1], order = [1, 0]}>
+#dot0_ = #triton_gpu.dot_op<{opIdx = 0, parent = #warp... | why using the trailing underscore in the name ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,656 | intel | etiotto | @@ -162,7 +168,57 @@ class LoadStorePrefetchOpConversion
Location loc = op.getLoc();
Value bytes =
i32_val(tensorType.getElementType().getIntOrFloatBitWidth() / 8);
-
+ if (isLocalSpace) {
+ Value llPtr = adaptor.getPtr();
+ // sg_size(16) x i64 = 64 x i16
+ VectorType v64i16Ty = Ve... | Use the void_ty macro here |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,656 | intel | etiotto | @@ -162,7 +168,57 @@ class LoadStorePrefetchOpConversion
Location loc = op.getLoc();
Value bytes =
i32_val(tensorType.getElementType().getIntOrFloatBitWidth() / 8);
-
+ if (isLocalSpace) {
+ Value llPtr = adaptor.getPtr();
+ // sg_size(16) x i64 = 64 x i16
+ VectorType v64i16Ty = Ve... | Use the `call` macro in Utility.h |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,656 | intel | etiotto | @@ -137,6 +137,74 @@ class MatchTargetSizePass
MLIRContext *ctx = &getContext();
ModuleOp m = getOperation();
+ // this is ad-hoc for Q SLM
+ char *env = std::getenv("TRITON_INTEL_ENABLE_SLM");
+ const bool enableSLM = env ? (bool)std::atoi(env) : false;
+ if (enableSLM) {
+ dotWithSLMOpera... | This is too fragile, this is walking the module to find the first `tt.load` operation in the first function in the module. The first function isn't guaranteed to be the kernel. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,656 | intel | whitneywhtsang | @@ -137,6 +137,74 @@ class MatchTargetSizePass
MLIRContext *ctx = &getContext();
ModuleOp m = getOperation();
+ // this is ad-hoc for Q SLM | Can the additional code be a separate function? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,656 | intel | whitneywhtsang | @@ -137,6 +137,74 @@ class MatchTargetSizePass
MLIRContext *ctx = &getContext();
ModuleOp m = getOperation();
+ // this is ad-hoc for Q SLM
+ char *env = std::getenv("TRITON_INTEL_ENABLE_SLM");
+ const bool enableSLM = env ? (bool)std::atoi(env) : false;
+ if (enableSLM) {
+ dotWithSLMOpera... | avoid big block of code by early return? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,656 | intel | Dewei-Wang-sh | @@ -552,20 +631,26 @@ MatchTargetSizePass::getSubOpSize(RankedTensorType type) const {
/// FIXME: add a map for look up
/// return [shape, subType, subSize] for a tensor (or pointer to tensor)
std::tuple<SmallVector<int64_t>, Type, SmallVector<int64_t>>
-MatchTargetSizePass::getSubTypeAndShape(Type type) const {
+Ma... | ```suggestion
// specific for flash attention
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,656 | intel | victor-eds | @@ -137,6 +140,78 @@ class MatchTargetSizePass
MLIRContext *ctx = &getContext();
ModuleOp m = getOperation();
+ // this is ad-hoc for Q SLM
+ char *env = std::getenv("TRITON_INTEL_ENABLE_SLM");
+ const bool enableSLM = env ? (bool)std::atoi(env) : false;
+ if (enableSLM) {
+ dotWithSLMOpera... | Can we use operations to allocate local memory instead of manually updating the function? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,656 | intel | victor-eds | @@ -552,20 +631,26 @@ MatchTargetSizePass::getSubOpSize(RankedTensorType type) const {
/// FIXME: add a map for look up
/// return [shape, subType, subSize] for a tensor (or pointer to tensor)
std::tuple<SmallVector<int64_t>, Type, SmallVector<int64_t>>
-MatchTargetSizePass::getSubTypeAndShape(Type type) const {
+Ma... | Will this work for other attention shapes? |
intel-xpu-backend-for-triton | github_2023 | others | 1,656 | intel | whitneywhtsang | @@ -507,4 +507,43 @@ def TritonGEN_Matrix2DBlockPrefetchOp : TritonGEN_Op<"2Dblockprefetch">,
let hasVerifier = 1;
}
+def TritonGEN_SIMDBlockReadOp: TritonGEN_Op<"simdblockread">,
+ Results<(outs FixedVectorOf<[TritonGEN_MatrixElemType]>:$res)>,
+ Arguments<(ins
+ Arg<LLVM_AnyPointer, "", [MemRead]>:$ptr
+ ... | There is no $val in this op
```suggestion
``` |
intel-xpu-backend-for-triton | github_2023 | others | 1,656 | intel | whitneywhtsang | @@ -377,3 +377,21 @@ llvm.func @triton_gen.dpas.bf16_accum(%c: vector<8xbf16>, %a : vector<8xi16>, %b
// CHECK-NEXT: {{%.*}} = llvm.bitcast [[RES]] : vector<8xi16> to vector<8xbf16>
llvm.return
}
+
+// -----
+
+llvm.func @triton_gen.simdblockwrite(%ptr: !llvm.ptr<3>, %val : vector<64xi16>) { | please also add function declaration CHECKs. |
intel-xpu-backend-for-triton | github_2023 | others | 1,656 | intel | whitneywhtsang | @@ -377,3 +377,21 @@ llvm.func @triton_gen.dpas.bf16_accum(%c: vector<8xbf16>, %a : vector<8xi16>, %b
// CHECK-NEXT: {{%.*}} = llvm.bitcast [[RES]] : vector<8xi16> to vector<8xbf16>
llvm.return
}
+
+// -----
+
+llvm.func @triton_gen.simdblockwrite(%ptr: !llvm.ptr<3>, %val : vector<64xi16>) {
+ // CHECK: llv... | What's the expected arguments? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,656 | intel | whitneywhtsang | @@ -1383,6 +1383,62 @@ struct TritonMatrix2DBlockPrefetchLowering
}
};
+struct TritonSIMDBlockWriteLowering
+ : public ConvertOpToLLVMPattern<TritonGEN::SIMDBlockWriteOp> {
+ using ConvertOpToLLVMPattern<
+ TritonGEN::SIMDBlockWriteOp>::ConvertOpToLLVMPattern;
+
+ LogicalResult
+ matchAndRewrite(Triton... | Do we already have a IGC ticket created for this GenISA? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,656 | intel | whitneywhtsang | @@ -1383,6 +1383,62 @@ struct TritonMatrix2DBlockPrefetchLowering
}
};
+struct TritonSIMDBlockWriteLowering
+ : public ConvertOpToLLVMPattern<TritonGEN::SIMDBlockWriteOp> {
+ using ConvertOpToLLVMPattern<
+ TritonGEN::SIMDBlockWriteOp>::ConvertOpToLLVMPattern;
+
+ LogicalResult
+ matchAndRewrite(Triton... | Why should it be this type? And why it should be in shared memory? Shouldn't this TritonGEN op works for other types or address spaces too? |
intel-xpu-backend-for-triton | github_2023 | others | 1,877 | intel | whitneywhtsang | @@ -90,12 +90,25 @@ jobs:
TRITON_INTEL_ENABLE_ADDRESS_PAYLOAD_OPT=1 \
IGC_VISAOptions=" -TotalGRFNum 256 -enableBCR -nolocalra -printregusage -DPASTokenReduction -enableHalfLSC -abiver 2" \
IGC_DisableLoopUnroll=1 \
- SYCL_PROGRAM_COMPILE_OPTIONS=" -vc-codegen -vc-disable-indva... | I thought you said this is needed for XeTLA, why is it no longer needed? |
intel-xpu-backend-for-triton | github_2023 | others | 1,877 | intel | whitneywhtsang | @@ -267,17 +272,36 @@ run_benchmark_gemm() {
TRITON_INTEL_ENABLE_ADDRESS_PAYLOAD_OPT=1 \
IGC_VISAOptions=" -TotalGRFNum 256 -enableBCR -nolocalra -printregusage -DPASTokenReduction -enableHalfLSC -abiver 2" \
IGC_DisableLoopUnroll=1 \
- SYCL_PROGRAM_COMPILE_OPTIONS=" -vc-codegen -vc-disable-indvars-opt -doubl... | Can we change the order for the two to match the order for GEMM? |
intel-xpu-backend-for-triton | github_2023 | python | 1,877 | intel | whitneywhtsang | @@ -193,13 +187,14 @@ def forward(q, k, v, causal, sm_scale):
benchmark_suit.Benchmark(
# argument names to use as an x-axis for the plot
x_names=['Z', 'H', 'N_CTX', 'D_HEAD'],
- x_vals=[[4, 48, 1024, 64]],
+ x_vals=[[4, 48, 1024, 64], [32, 32, 512, 64], [16, 32, 1024, 64], [8, 32, ... | Why are we not running Triton? |
intel-xpu-backend-for-triton | github_2023 | others | 1,877 | intel | etiotto | @@ -90,12 +90,25 @@ jobs:
TRITON_INTEL_ENABLE_ADDRESS_PAYLOAD_OPT=1 \
IGC_VISAOptions=" -TotalGRFNum 256 -enableBCR -nolocalra -printregusage -DPASTokenReduction -enableHalfLSC -abiver 2" \
IGC_DisableLoopUnroll=1 \
- SYCL_PROGRAM_COMPILE_OPTIONS=" -vc-codegen -vc-disable-indva... | We need to wait to make FlashAttention run on the llvm-target branch. First we need to complete the POC "productization". Only at that point we should remove this coverage. |
intel-xpu-backend-for-triton | github_2023 | python | 1,877 | intel | whitneywhtsang | @@ -193,13 +187,14 @@ def forward(q, k, v, causal, sm_scale):
benchmark_suit.Benchmark(
# argument names to use as an x-axis for the plot
x_names=['Z', 'H', 'N_CTX', 'D_HEAD'],
- x_vals=[[4, 48, 1024, 64]],
+ x_vals=[[4, 48, 1024, 64], [32, 32, 512, 64], [16, 32, 1024, 64], [8, 32, ... | Make each shape in a different line, so it is easier to comment out if needed. |
intel-xpu-backend-for-triton | github_2023 | others | 1,877 | intel | etiotto | @@ -111,14 +110,27 @@ jobs:
TRITON_INTEL_ENABLE_ADDRESS_PAYLOAD_OPT=1 \
IGC_VISAOptions=" -TotalGRFNum 256 -enableBCR -nolocalra -printregusage -DPASTokenReduction -enableHalfLSC -abiver 2" \
IGC_DisableLoopUnroll=1 \
- SYCL_PROGRAM_COMPILE_OPTIONS=" -vc-codegen -vc-disable-ind... | We have a feature to chose the large GRF mode automatically so can you please remove the -TotalGRFNum option here ?
We can also have 2 tests (one with extra IGC options and one without any extra options). That way we can track performance out-of-box vs with special IGC flags. |
intel-xpu-backend-for-triton | github_2023 | others | 1,877 | intel | etiotto | @@ -111,14 +110,27 @@ jobs:
TRITON_INTEL_ENABLE_ADDRESS_PAYLOAD_OPT=1 \
IGC_VISAOptions=" -TotalGRFNum 256 -enableBCR -nolocalra -printregusage -DPASTokenReduction -enableHalfLSC -abiver 2" \
IGC_DisableLoopUnroll=1 \
- SYCL_PROGRAM_COMPILE_OPTIONS=" -vc-codegen -vc-disable-ind... | Does this option matters in the advanced path ? Can we remove it ?
I think is important to clean up any IGC options that aren't absolutely needed to get performance. |
intel-xpu-backend-for-triton | github_2023 | others | 1,877 | intel | etiotto | @@ -268,18 +273,33 @@ run_benchmark_gemm() {
TRITON_INTEL_ENABLE_ADDRESS_PAYLOAD_OPT=1 \
IGC_VISAOptions=" -TotalGRFNum 256 -enableBCR -nolocalra -printregusage -DPASTokenReduction -enableHalfLSC -abiver 2" \ | `-TotalGRFNum 256` is not required for Triton, remove.
Are any of the other flags required ? |
intel-xpu-backend-for-triton | github_2023 | others | 1,877 | intel | etiotto | @@ -268,18 +273,33 @@ run_benchmark_gemm() {
TRITON_INTEL_ENABLE_ADDRESS_PAYLOAD_OPT=1 \
IGC_VISAOptions=" -TotalGRFNum 256 -enableBCR -nolocalra -printregusage -DPASTokenReduction -enableHalfLSC -abiver 2" \
IGC_DisableLoopUnroll=1 \
- SYCL_PROGRAM_COMPILE_OPTIONS=" -vc-codegen -vc-disable-indvars-opt -doubl... | Remove `-TotalGRFNum 256` |
intel-xpu-backend-for-triton | github_2023 | others | 1,877 | intel | etiotto | @@ -268,18 +273,33 @@ run_benchmark_gemm() {
TRITON_INTEL_ENABLE_ADDRESS_PAYLOAD_OPT=1 \
IGC_VISAOptions=" -TotalGRFNum 256 -enableBCR -nolocalra -printregusage -DPASTokenReduction -enableHalfLSC -abiver 2" \
IGC_DisableLoopUnroll=1 \
- SYCL_PROGRAM_COMPILE_OPTIONS=" -vc-codegen -vc-disable-indvars-opt -doubl... | Remove ` -TotalGRFNum 256` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,939 | intel | sommerlukas | @@ -88,24 +85,26 @@ static inline T checkSyclErrors(const std::tuple<T, ze_result_t> tuple) {
}
/** SYCL Functions **/
-std::tuple<sycl::kernel_bundle<sycl::bundle_state::executable> *,
- sycl::kernel *, int32_t, int32_t>
+std::tuple<sycl::kernel_bundle<sycl::bundle_state::executable>, sycl::kernel, | Yeah, I think returning by value makes sense. In the SYCL specification, it's common to accept parameters by reference (e.g., `queue&`, `device&`), but returns for classes with common reference semantics are usually by value, e.g.: https://registry.khronos.org/SYCL/specs/sycl-2020/html/sycl-2020.html#_the_kernel_bundle... |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,939 | intel | etiotto | @@ -88,24 +85,26 @@ static inline T checkSyclErrors(const std::tuple<T, ze_result_t> tuple) {
}
/** SYCL Functions **/
-std::tuple<sycl::kernel_bundle<sycl::bundle_state::executable> *,
- sycl::kernel *, int32_t, int32_t>
+std::tuple<sycl::kernel_bundle<sycl::bundle_state::executable>, sycl::kernel,
+ ... | Remove TODO? |
intel-xpu-backend-for-triton | github_2023 | python | 1,860 | intel | FMarno | @@ -373,7 +372,7 @@ def matmul(a, b, accum_dtype, res_dtype):
# Note: the torch.matmul and Triton implementations uses different
# algorithms so we need to adjust tolerance.
rtol = 1e-2 if dtype == torch.bfloat16 or accum_dtype in [torch.float16, torch.bfloat16] else 1e-3
- atol = 1e-2... | ```suggestion
atol = 1e-1 if accum_dtype == torch.float32 else 1e-2 if accum_dtype == torch.bfloat16 else 1e-3 if accum_dtype == torch.float16 else 1e-4
```
saying that, float32 having 2 orders of magnitude more absolute error seems very weird to me. |
intel-xpu-backend-for-triton | github_2023 | python | 1,860 | intel | etiotto | @@ -327,7 +327,6 @@ def matmul(a, b, accum_dtype, res_dtype):
# Still we can test our matrix multiplication with block pointers against a native torch implementation (i.e., cuBLAS).
torch.manual_seed(0)
-torch.xpu.set_fp32_math_mode(torch.xpu.utils.FP32MathMode.TF32) | This should work also when using upstream PyTorch. I do not think we should be fixing the tutorial. |
intel-xpu-backend-for-triton | github_2023 | others | 1,878 | intel | pbchekin | @@ -139,7 +139,7 @@ jobs:
key: ${{ runner.os }}-${{ steps.cache-key.outputs.pre_commit_hash }}
- name: Check pre-commit
run: |
- python3 -m pip install --upgrade pre-commit
+ python3 -m pip install --upgrade pre-commit bandit | This is upstream workflow, please keep as is. |
intel-xpu-backend-for-triton | github_2023 | others | 1,878 | intel | pbchekin | @@ -154,7 +154,7 @@ jobs:
- name: Check pre-commit
run: |
- python3 -m pip install --upgrade pre-commit
+ python3 -m pip install --upgrade pre-commit bandit | This is upstream workflow, please keep as is. |
intel-xpu-backend-for-triton | github_2023 | others | 1,878 | intel | pbchekin | @@ -63,6 +63,15 @@ repos:
files: ^.github/workflows/integration-tests.yml.*
pass_filenames: false
+ - repo: local
+ hooks:
+ - id: bandit-python-files
+ name: Check Python files for security issues
+ language: script
+ pass_filenames: false
+ stages: [manual, commit,... | Please do not use a custom script to scan only files changed in PR, `pre-commit` supports that already, see https://pre-commit.com/#pre-commit-run (`pre-commit run --from-ref ... --to-ref ...`). |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,895 | intel | victor-eds | @@ -27,7 +27,7 @@ constexpr unsigned shapeAndStridesBitwidth = 64;
std::optional<int64_t> getIntAttr(const OpFoldResult ofr) {
if (ofr.is<Attribute>() && isa<IntegerAttr>(ofr.get<Attribute>()))
- return cast<IntegerAttr>(ofr.get<Attribute>()).getInt();
+ return dyn_cast<IntegerAttr>(ofr.get<Attribute>()).ge... | `cast` should work as we have `isa<IntegerAttr>(ofr.get<Attribute>())` as a condition, right? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,895 | intel | victor-eds | @@ -56,20 +56,34 @@ std::optional<int64_t> getFoldedConstantValue(Operation *op) {
return intAttr.value();
}
- auto val = cast<Value>(results[0]);
+ auto val = dyn_cast<Value>(results[0]);
+ assert(val && "op must have at least one result"); | `cast` is better than `dyn_cast + assert` IMO |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,895 | intel | victor-eds | @@ -56,20 +56,34 @@ std::optional<int64_t> getFoldedConstantValue(Operation *op) {
return intAttr.value();
}
- auto val = cast<Value>(results[0]);
+ auto val = dyn_cast<Value>(results[0]);
+ assert(val && "op must have at least one result");
auto constOp = val.getDefiningOp<arith::ConstantOp>();
if (... | I think this change is not needed as `intAttr` is an optional value already. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,895 | intel | victor-eds | @@ -56,20 +56,34 @@ std::optional<int64_t> getFoldedConstantValue(Operation *op) {
return intAttr.value();
}
- auto val = cast<Value>(results[0]);
+ auto val = dyn_cast<Value>(results[0]);
+ assert(val && "op must have at least one result");
auto constOp = val.getDefiningOp<arith::ConstantOp>();
if (... | ```suggestion
return getFoldedConstantValue(defOp) == ref;
```
Use `bool operator==(const std::optional<T> &, const T &);` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,895 | intel | victor-eds | @@ -144,6 +158,14 @@ struct PtrState {
source = lhsState.source ? lhsState.source : rhsState.source;
+ if (lhsState.scalar && rhsState.scalar) {
+ auto addOp =
+ builder.create<arith::AddIOp>(loc, lhsState.scalar, rhsState.scalar);
+ scalar = addOp.getResult();
+ } else if (lhsState.ge... | Is the comment up to date? Wouldn't then the first branch be hit? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,895 | intel | victor-eds | @@ -711,6 +746,12 @@ struct TritonRaiseBlockPointer
OpBuilder &builder,
bool addedByPass = false) {
assert(state.isEmpty() && "state is a return argument");
+
+ if (knownPtrs.find(makeTPtrOp.getResult()) != knownPtrs.end()) {
... | ```suggestion
if (auto iter = knownPtrs.find(makeTPtrOp.getResult()); iter != knownPtrs.end()) {
state = *iter;
return success();
}
```
Same, right? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,895 | intel | victor-eds | @@ -858,11 +908,21 @@ struct TritonRaiseBlockPointer
return success();
}
+ SmallVector<int> boundary;
+ if (knownPtrs.find(ptr) != knownPtrs.end()) {
+ auto state = knownPtrs.lookup(ptr); | Same as above, store `find` result |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,895 | intel | victor-eds | @@ -1094,13 +1154,19 @@ LogicalResult TritonRaiseBlockPointer::visitAddPointerOperand(
auto resultType = cast<ShapedType>(op.getResult().getType());
Value offset = convertScalarToDtype(builder, loc, state.scalar, offsetType,
/*isUnsignedCast=*/true);
+ size_t i = 0;
for ... | You can use `llvm::enumerate` in the loop initializer instead of manually incrementing `i` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,895 | intel | etiotto | @@ -64,12 +64,17 @@ std::optional<int64_t> getFoldedConstantValue(Operation *op) {
return getIntAttr(constOp.getValue());
}
-// return true if the `val` value is a constant containing a value equal to zero
-bool hasConstZero(Value val) {
- auto intVal = getFoldedConstantValue(val.getDefiningOp());
- return (int... | We have similar function in `MaterializeBlockPointer.cpp`:
```
bool isConstant(Value v, unsigned expected) {
if (v.getDefiningOp() == nullptr)
return false;
if (auto stride = dyn_cast<arith::ConstantOp>(v.getDefiningOp())) {
if (auto strideInt = dyn_cast<IntegerAttr>(stride.getValue()))
if (s... |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,895 | intel | etiotto | @@ -64,12 +64,17 @@ std::optional<int64_t> getFoldedConstantValue(Operation *op) {
return getIntAttr(constOp.getValue());
}
-// return true if the `val` value is a constant containing a value equal to zero
-bool hasConstZero(Value val) {
- auto intVal = getFoldedConstantValue(val.getDefiningOp());
- return (int... | This function is just a wrapper around `hasConstEqualTo` can we just use that one ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,895 | intel | etiotto | @@ -693,8 +718,9 @@ struct TritonRaiseBlockPointer
Value result = op.getResult();
Value mapped = result;
if (isa<RankedTensorType>(result.getType())) {
- Value maketptrOp = state.createTTMakeTensorPtrOp(builder, loc);
- mapped = maketptrOp;
+ auto maketptrOp = state.createTTMakeTensorPtrOp... | auto -> Value |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,895 | intel | etiotto | @@ -858,11 +900,21 @@ struct TritonRaiseBlockPointer
return success();
}
+ SmallVector<int> boundary;
+ if (auto iter = knownPtrs.find(ptr); iter != knownPtrs.end()) {
+ auto state = iter->second;
+ for (int axis = 0; axis < state.shape.size(); ++axis) {
+ if (!hasConstZero(state.sh... | Remove the declaration and include the appropriate header file instead. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,895 | intel | whitneywhtsang | @@ -52,6 +52,10 @@ LLVM::CallOp createSPIRVBuiltinCall(Location loc,
ConversionPatternRewriter &rewriter,
LLVM::LLVMFuncOp func, ValueRange args);
+// Return true if the `val` value is a constant containing a value equal to
+// expected | ```suggestion
// expected.
``` |
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