repo_name stringlengths 1 62 | dataset stringclasses 1
value | lang stringclasses 11
values | pr_id int64 1 20.1k | owner stringlengths 2 34 | reviewer stringlengths 2 39 | diff_hunk stringlengths 15 262k | code_review_comment stringlengths 1 99.6k |
|---|---|---|---|---|---|---|---|
intel-xpu-backend-for-triton | github_2023 | cpp | 465 | intel | etiotto | @@ -129,56 +279,51 @@ class DotOpDPASConversionHelper {
}
}
- /// Generate the GENX dialect dpas operation. Rules (for PVC):
- /// - SD = 8
- /// - M = RC = 1,2,4,8 (we use 8)
- /// - N = exec_size = SIMD_width = 16
- /// - Size of A, B element type = {32,16,8}, for {tf32,bf16/f16,u8/i8}
- /// - K=... | Just return the RHS expression. No point storing it into a temp variable that is immediately returned. |
intel-xpu-backend-for-triton | github_2023 | cpp | 465 | intel | etiotto | @@ -129,56 +279,51 @@ class DotOpDPASConversionHelper {
}
}
- /// Generate the GENX dialect dpas operation. Rules (for PVC):
- /// - SD = 8
- /// - M = RC = 1,2,4,8 (we use 8)
- /// - N = exec_size = SIMD_width = 16
- /// - Size of A, B element type = {32,16,8}, for {tf32,bf16/f16,u8/i8}
- /// - K=... | auto -> unsigned (also the next line). |
intel-xpu-backend-for-triton | github_2023 | cpp | 465 | intel | etiotto | @@ -197,10 +342,10 @@ class DotOpDPASConversionHelper {
if (isa<FloatType>(resElemType)) {
if (width == 32)
return GENX::PrecisionType::TF32; | collapse lines 342 and 343. |
intel-xpu-backend-for-triton | github_2023 | cpp | 465 | intel | etiotto | @@ -695,14 +695,17 @@ class ConvertTritonGPUOpToLLVMPatternBase {
void emitDpasOffsetForCTA(const DpasEncodingAttr &dpasLayout,
SmallVector<SmallVector<unsigned>> &offsets,
unsigned ctaOffsetX, unsigned ctaOffsetY) const {
- unsigned elemsPerThreadPerGroup... | auto -> unsigned (or uint32_t given that is used few lines below). |
intel-xpu-backend-for-triton | github_2023 | others | 563 | intel | whitneywhtsang | @@ -294,8 +310,23 @@ jobs:
pip install vision/dist/*.whl
python -c "import torchvision; print(torchvision.__version__)"
- - name: Build torchtext wheels
+ - name: Save torchvision to a cache
+ if: ${{ (matrix.suite == 'timm_models' || matrix.suite == 'torchbench') && steps.torch... | ```suggestion
if: ${{ matrix.suite == 'torchbench' }}
``` |
intel-xpu-backend-for-triton | github_2023 | others | 563 | intel | whitneywhtsang | @@ -294,8 +310,23 @@ jobs:
pip install vision/dist/*.whl
python -c "import torchvision; print(torchvision.__version__)"
- - name: Build torchtext wheels
+ - name: Save torchvision to a cache
+ if: ${{ (matrix.suite == 'timm_models' || matrix.suite == 'torchbench') && steps.torch... | ```suggestion
if: ${{ matrix.suite == 'torchbench' && steps.torchtext-cache.outputs.status == 'miss'}}
``` |
intel-xpu-backend-for-triton | github_2023 | others | 563 | intel | whitneywhtsang | @@ -308,8 +339,23 @@ jobs:
pip install text/dist/*.whl
python -c "import torchtext; print(torchtext.__version__)"
- - name: Build torchaudio wheels
+ - name: Save torchtext to a cache
+ if: ${{ (matrix.suite == 'timm_models' || matrix.suite == 'torchbench') && steps.torchtext-ca... | ```suggestion
if: ${{ matrix.suite == 'torchbench' && steps.torchtext-cache.outputs.status == 'miss' }}
``` |
intel-xpu-backend-for-triton | github_2023 | others | 563 | intel | whitneywhtsang | @@ -308,8 +339,23 @@ jobs:
pip install text/dist/*.whl
python -c "import torchtext; print(torchtext.__version__)"
- - name: Build torchaudio wheels
+ - name: Save torchtext to a cache
+ if: ${{ (matrix.suite == 'timm_models' || matrix.suite == 'torchbench') && steps.torchtext-ca... | ```suggestion
if: ${{ matrix.suite == 'torchbench' }}
``` |
intel-xpu-backend-for-triton | github_2023 | others | 563 | intel | whitneywhtsang | @@ -308,8 +339,23 @@ jobs:
pip install text/dist/*.whl
python -c "import torchtext; print(torchtext.__version__)"
- - name: Build torchaudio wheels
+ - name: Save torchtext to a cache
+ if: ${{ (matrix.suite == 'timm_models' || matrix.suite == 'torchbench') && steps.torchtext-ca... | ```suggestion
if: ${{ matrix.suite == 'torchbench' && steps.torchaudio-cache.outputs.status == 'miss' }}
``` |
intel-xpu-backend-for-triton | github_2023 | others | 563 | intel | whitneywhtsang | @@ -322,8 +368,15 @@ jobs:
pip install audio/dist/*.whl
python -c "import torchaudio; print(torchaudio.__version__)"
- - name: Install PyTorch Benchmarks
- if: ${{ matrix.suite == 'timm_models' || matrix.suite == 'torchbench' }}
+ - name: Save torchaudio to a cache
+ if: ... | ```suggestion
if: ${{ matrix.suite == 'torchbench' && steps.torchaudio-cache.outputs.status == 'miss' }}
``` |
intel-xpu-backend-for-triton | github_2023 | others | 558 | intel | kurapov-peter | @@ -0,0 +1,329 @@
+//===-- GENOps.td - GEN IR dialect op definition file ------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | This might need further clarification |
intel-xpu-backend-for-triton | github_2023 | others | 541 | intel | whitneywhtsang | @@ -0,0 +1,41 @@
+add_triton_library(TritonIntelGPUToLLVM
+ ConvertLayoutOpToLLVM/SharedToDotOperandDPAS.cpp
+ ConvertLayoutOpToLLVM/SharedToDotOperandFMA.cpp
+ ConvertLayoutOpToLLVM/SharedToDotOperandMMAv1.cpp
+ ConvertLayoutOpToLLVM/SharedToDotOperandMMAv2.cpp
+ ConvertLayoutOpToLLVM.cpp
+ DotOpToLL... | why `TritonGPUToLLVM` doesn't dpends on `NVGPUConversionPassIncGen`, but `TritonIntelGPUToLLVM` dpends on `NVGPUIntelConversionPassIncGen` here? |
intel-xpu-backend-for-triton | github_2023 | cpp | 515 | intel | whitneywhtsang | @@ -498,8 +498,8 @@ static Value getModuleWarpSize(ConversionPatternRewriter &rewriter,
static Value getClusterCTAId(ConversionPatternRewriter &rewriter,
Location loc) {
- return rewriter.create<triton::nvgpu::ClusterCTAIdOp>(loc,
- ... | should we do different codegen for different target? For example,
```
Value getClusterCTAId(ConversionPatternRewriter &rewriter,
Location loc) const {
switch (target) {
case triton::Target::NVVM:
return rewriter.create<triton::nvgpu::ClusterCTAIdOp>(
loc, rewrit... |
intel-xpu-backend-for-triton | github_2023 | others | 517 | intel | chengjunlu | @@ -46,7 +46,7 @@ def TritonGPU_Dialect : Dialect {
static int getThreadsPerWarp(ModuleOp mod) {
Attribute threadsPerWarp = mod->getDiscardableAttr("triton_gpu.threads-per-warp");
if(!threadsPerWarp) {
- return 32;
+ return triton::gpu::TritonGPUDialect::getThreadsPerWarp(mod); | It goes endless nested recursive calling `getThreadsPerWarp` -> `getThreadsPerWarp`.
The default number of 32 is for the case that the old `ttgir` without the `threads-per-warp` attribute. |
intel-xpu-backend-for-triton | github_2023 | cpp | 520 | intel | etiotto | @@ -1663,9 +1663,12 @@ struct FpToFpOpConversion
cvt(res, operand);
return builder.launch(rewriter, loc, f32_ty, false);
} break;
- case mlir::triton::Target::GENX:
- return rewriter.create<GENX::FpToFpOp>(loc, f32_ty, v,
- GENX::RoundingMode::RTE);... | Add a TODO: the rounding mode should not be passed when we do an extension. |
intel-xpu-backend-for-triton | github_2023 | python | 516 | intel | whitneywhtsang | @@ -2577,28 +2577,40 @@ def kernel(In, Out, #
for col_b in [True, False]] + [(64, 64, 64, 4, False, False, 'chain-dot', False, 'bfloat16', 'float32')])
@pytest.mark.parametrize("num_ctas", num_ctas_list)
def test_dot(M, N, K, num_warps, col_a, col_b, epilogue, allow_tf32, in_dtype, out_dtype, num_ctas, device)... | Do we expect to fix this failure?
If yes, `pytest.skip("FIXME: shared memory out of resource")`, else `pytest.xfail("shared memory out of resource")` |
intel-xpu-backend-for-triton | github_2023 | others | 510 | intel | leshikus | @@ -62,13 +55,11 @@ jobs:
python3 -m pre_commit run --show-diff-on-failure --color=always --all-files --verbose
- name: Save pip cache
- if: ${{ hashFiles('.pip-cache') == '' }}
- run: |
- TMPDIR=/cache/${{ github.run_id }}-$RANDOM
- mkdir $TMPDIR
- cp -r $HO... | is the `path` actually the action output value? it seems more like the action parameter |
intel-xpu-backend-for-triton | github_2023 | python | 512 | intel | whitneywhtsang | @@ -1135,12 +1135,17 @@ def test_atomic_rmw(op, dtype_x_str, mode, sem, device):
'test_atomic_rmw for HIP currently broken in https://github.com/openai/triton. Use https://github.com/ROCmSoftwarePlatform/triton'
)
- check_cuda_only(device) | Note that `check_cuda_only` is in the upstream version of test_core.py. |
intel-xpu-backend-for-triton | github_2023 | others | 503 | intel | whitneywhtsang | @@ -212,52 +231,57 @@ jobs:
path: ${{ steps.triton-cache.outputs.path }}
dest: ${{ steps.triton-cache.outputs.dest }}
- # TODO: move to the base image
- - name: Install torchvision dependencies
- run: |
- sudo apt update -y
- sudo apt install -y libpng-dev libj... | pandas is needed for huggingface too |
intel-xpu-backend-for-triton | github_2023 | others | 503 | intel | whitneywhtsang | @@ -212,52 +233,56 @@ jobs:
path: ${{ steps.triton-cache.outputs.path }}
dest: ${{ steps.triton-cache.outputs.dest }}
- # TODO: move to the base image
- - name: Install torchvision dependencies
+ - name: Install python test dependencies
run: |
- sudo apt update -... | remove? |
intel-xpu-backend-for-triton | github_2023 | others | 462 | intel | pbchekin | @@ -0,0 +1,61 @@
+# Building Triton for Intel GPUs
+
+## Dependencies
+
+### Drivers
+
+To build triton from source, we need to start with installing GPU drivers. If you're using Data Center (PVC) GPUs, please follow the instructions from [here](https://dgpu-docs.intel.com/driver/installation.html#install-steps) of you... | ```suggestion
Next, we install python3 and venv in our system. For Ubuntu 22.04, follow these instructions
``` |
intel-xpu-backend-for-triton | github_2023 | others | 462 | intel | pbchekin | @@ -0,0 +1,61 @@
+# Building Triton for Intel GPUs
+
+## Dependencies
+
+### Drivers
+
+To build triton from source, we need to start with installing GPU drivers. If you're using Data Center (PVC) GPUs, please follow the instructions from [here](https://dgpu-docs.intel.com/driver/installation.html#install-steps) of you... | This requires oneAPI BaseKit mentioned here: https://github.com/intel/intel-xpu-backend-for-triton/blob/llvm-target/README.md?plain=1#L26. |
intel-xpu-backend-for-triton | github_2023 | others | 462 | intel | pbchekin | @@ -0,0 +1,61 @@
+# Building Triton for Intel GPUs
+
+## Dependencies
+
+### Drivers
+
+To build triton from source, we need to start with installing GPU drivers. If you're using Data Center (PVC) GPUs, please follow the instructions from [here](https://dgpu-docs.intel.com/driver/installation.html#install-steps) of you... | It would be nice to mention that Python needs to be 3.9 or 3.10 for other distributions. |
intel-xpu-backend-for-triton | github_2023 | others | 462 | intel | pbchekin | @@ -0,0 +1,63 @@
+# Building Triton for Intel GPUs
+
+## Dependencies
+
+### Drivers and OneAPI Toolkit
+
+To build triton from source, we need to start with installing GPU drivers. If you're using Data Center (PVC) GPUs, please follow the instructions from [here](https://dgpu-docs.intel.com/driver/installation.html#in... | ```suggestion
We also need to install OneAPI Basekit with version >= 2024.0.1. Please follow the instructions from [here](https://www.intel.com/content/www/us/en/developer/tools/oneapi/base-toolkit-download.html) to install it.
``` |
intel-xpu-backend-for-triton | github_2023 | others | 462 | intel | pbchekin | @@ -0,0 +1,63 @@
+# Building Triton for Intel GPUs
+
+## Dependencies
+
+### Drivers and OneAPI Toolkit
+
+To build triton from source, we need to start with installing GPU drivers. If you're using Data Center (PVC) GPUs, please follow the instructions from [here](https://dgpu-docs.intel.com/driver/installation.html#in... | Please add trailing new line to pass pre-commit check:
```suggestion
This should not throw any error!
``` |
intel-xpu-backend-for-triton | github_2023 | python | 492 | intel | whitneywhtsang | @@ -150,6 +150,8 @@ def test_attention_fwd_bwd(block, dtype, device, input_scale=1.0, scale=1 / 8.0,
if capability[0] < 7:
pytest.skip("Only test tl.dot() on devices with sm >= 70")
+ # Triton result is correct compared to CUDA result
+ # Torch is currently producing nan values
pytest... | ```suggestion
# Note: Triton result on XPU is correct compared to the result on CUDA.
pytest.skip("FIXME: Torch produces incorrect nan values")
``` |
intel-xpu-backend-for-triton | github_2023 | others | 476 | intel | whitneywhtsang | @@ -0,0 +1,275 @@
+name: E2E
+
+on:
+ workflow_dispatch:
+ schedule:
+ - cron: "5 1 * * *"
+
+permissions: read-all
+
+env:
+ BASE: /home/runner
+ LLVM_SYSPATH: /home/runner/packages/llvm
+ BACKEND: XPU
+ TRITON_DISABLE_LINE_INFO: 1
+ USE_AOT_DEVLIST: pvc
+ PYTHON_VERSION: "3.10"
+ PYTORCH_REPO: https://git... | Note: my runs used the wheel provided by IPEX team. Let's see if that may affect the results. |
intel-xpu-backend-for-triton | github_2023 | others | 476 | intel | whitneywhtsang | @@ -0,0 +1,275 @@
+name: E2E
+
+on:
+ workflow_dispatch:
+ schedule:
+ - cron: "5 1 * * *"
+
+permissions: read-all
+
+env:
+ BASE: /home/runner
+ LLVM_SYSPATH: /home/runner/packages/llvm
+ BACKEND: XPU
+ TRITON_DISABLE_LINE_INFO: 1
+ USE_AOT_DEVLIST: pvc
+ PYTHON_VERSION: "3.10"
+ PYTORCH_REPO: https://git... | Note: `skip-triton` option will be unable after https://github.com/intel/intel-xpu-backend-for-triton/pull/480/files.
```suggestion
./scripts/compile-triton.sh --llvm
``` |
intel-xpu-backend-for-triton | github_2023 | others | 476 | intel | whitneywhtsang | @@ -0,0 +1,275 @@
+name: E2E
+
+on:
+ workflow_dispatch:
+ schedule:
+ - cron: "5 1 * * *"
+
+permissions: read-all
+
+env:
+ BASE: /home/runner
+ LLVM_SYSPATH: /home/runner/packages/llvm
+ BACKEND: XPU
+ TRITON_DISABLE_LINE_INFO: 1
+ USE_AOT_DEVLIST: pvc
+ PYTHON_VERSION: "3.10"
+ PYTORCH_REPO: https://git... | Can we get the transformers version from https://github.com/Stonepia/pytorch/blob/dev/triton-test-3.0/.ci/docker/ci_commit_pins/huggingface.txt? |
intel-xpu-backend-for-triton | github_2023 | others | 476 | intel | whitneywhtsang | @@ -0,0 +1,275 @@
+name: E2E
+
+on:
+ workflow_dispatch:
+ schedule:
+ - cron: "5 1 * * *"
+
+permissions: read-all
+
+env:
+ BASE: /home/runner
+ LLVM_SYSPATH: /home/runner/packages/llvm
+ BACKEND: XPU
+ TRITON_DISABLE_LINE_INFO: 1
+ USE_AOT_DEVLIST: pvc
+ PYTHON_VERSION: "3.10"
+ PYTORCH_REPO: https://git... | According to https://github.com/intel/intel-xpu-backend-for-triton/wiki/End-to-End-Test#install-torch-vision, we also need to install `ffmpeg`, but the latest `ffmpeg` doesn't work with the pinned_commit, so we can do something like `conda install -c conda-forge 'ffmpeg<4.4'`. |
intel-xpu-backend-for-triton | github_2023 | others | 476 | intel | whitneywhtsang | @@ -0,0 +1,54 @@
+name: load
+description: Load a directory from a cache based on a shared directory
+inputs:
+ root:
+ description:
+ default: /cache
+ path:
+ description: A directory to load from a cache
+ required: true
+ key:
+ description: A cache key
+ required: true
+ symlink:
+ descrip... | ```suggestion
description: Create a symlink instead of copying from cache
``` |
intel-xpu-backend-for-triton | github_2023 | others | 476 | intel | whitneywhtsang | @@ -0,0 +1,286 @@
+name: E2E
+
+on:
+ workflow_dispatch:
+ schedule:
+ - cron: "5 1 * * *" | Just curious, why you pick 5 for minute? |
intel-xpu-backend-for-triton | github_2023 | others | 418 | intel | aregm | @@ -0,0 +1,514 @@
+# Triton architecture
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, however, the introduction is concise (use lin... | /s/pytorch/PyTorch |
intel-xpu-backend-for-triton | github_2023 | others | 418 | intel | aregm | @@ -0,0 +1,514 @@
+# Triton architecture
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, however, the introduction is concise (use lin... | ...call to the operator's native implementation in Aten. |
intel-xpu-backend-for-triton | github_2023 | others | 418 | intel | aregm | @@ -0,0 +1,514 @@
+# Triton architecture
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, however, the introduction is concise (use lin... | What is the original code to see before/after? |
intel-xpu-backend-for-triton | github_2023 | others | 418 | intel | aregm | @@ -0,0 +1,514 @@
+# Triton architecture
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, however, the introduction is concise (use lin... | This is good. |
intel-xpu-backend-for-triton | github_2023 | others | 418 | intel | aregm | @@ -0,0 +1,514 @@
+# Triton architecture
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, however, the introduction is concise (use lin... | import torch
import triton
import triton.language as tl |
intel-xpu-backend-for-triton | github_2023 | others | 418 | intel | aregm | @@ -0,0 +1,514 @@
+# Triton architecture
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, however, the introduction is concise (use lin... | What is SW? |
intel-xpu-backend-for-triton | github_2023 | others | 480 | intel | whitneywhtsang | @@ -33,18 +23,57 @@ for arg in "$@"; do
VENV=true
shift
;;
- --skip-triton) | CI uses this option, please update CI accordingly. |
intel-xpu-backend-for-triton | github_2023 | others | 480 | intel | whitneywhtsang | @@ -33,18 +23,57 @@ for arg in "$@"; do
VENV=true
shift
;;
- --skip-triton)
- SKIP_TRITON=true
+ --help)
+ echo "Example usage: ./compile-triton.sh [--llvm | --triton | --clean| --venv]" | [nit]
```suggestion
echo "Example usage: ./compile-triton.sh [--llvm | --triton | --clean | --venv]"
``` |
intel-xpu-backend-for-triton | github_2023 | others | 480 | intel | pbchekin | @@ -33,18 +23,57 @@ for arg in "$@"; do
VENV=true
shift
;;
- --skip-triton)
- SKIP_TRITON=true
+ --help)
+ echo "Example usage: ./compile-triton.sh [--llvm | --triton | --clean | --venv]"
+ exit 1
+ ;;
+ *)
+ ARGS+="${arg} "
shift
;;
esac
done
+... | I know it was in the previous version, but `deactivate` generates an error if we are not in venv. The error is ignored, because the script does not have `set -e` but anyways it is an error.
```suggestion
elif [ -n "$VIRTUAL_ENV" ]; then
echo "**** Cleaning up Python virtualenv ****"
deactivate
fi
``` |
intel-xpu-backend-for-triton | github_2023 | others | 480 | intel | whitneywhtsang | @@ -119,7 +148,6 @@ function build_llvm {
ninja check-mlir
check_rc
}
-build_llvm
############################################################################
# Install libGenISAIntrinsics.a | `Install libGenISAIntrinsics.a` needs to happen after `build_llvm`, or else `$PACKAGES_DIR/llvm/lib` is overwritten.
Suggest to move the `Install libGenISAIntrinsics.a` step to the end of `build_llvm`. |
intel-xpu-backend-for-triton | github_2023 | python | 484 | intel | whitneywhtsang | @@ -3187,8 +3187,8 @@ def kernel(x):
@pytest.mark.parametrize("device", ['xpu', 'cpu', 'cpu_pinned'])
def test_pointer_arguments(device):
- if is_xpu() and device in ['cpu', 'cpu_pinned']:
- pytest.skip("FIXME: Incorrect result on XPU")
+ if is_xpu() and device in ['cpu_pinned']:
+ pytest.skip("... | ```suggestion
pytest.xfail("RuntimeError: Pinned memory requires CUDA.")
``` |
intel-xpu-backend-for-triton | github_2023 | python | 475 | intel | etiotto | @@ -313,11 +313,11 @@ def test_layer_norm(M, N, dtype, eps=1e-5, device='xpu'):
y_ref.backward(dy, retain_graph=True)
dx_ref, dw_ref, db_ref = [_.grad.clone() for _ in [x, weight, bias]]
# compare
- assert torch.allclose(y_tri, y_ref, atol=1e-2, rtol=0)
- assert torch.allclose(dx_tri, dx_ref, atol=... | If we call this function with float32 (line 380) can we just put back the original code form the OpenAI version (which uses 1e-2 for all 4 comparisons) has ?
Rationale: It would be best to avoid potential merge conflicts. |
intel-xpu-backend-for-triton | github_2023 | others | 442 | intel | whitneywhtsang | @@ -223,3 +227,11 @@ jobs:
cp -r $HOME/.cache/pip/* $TMPDIR/
# ignore error if other job created a cache with the same key already
mv $TMPDIR $PIP_CACHE || true
+
+ - name: Pass rate
+ run: |
+ python3 scripts/pass_rate.py --reports ~/reports
+ mkdir -p /ca... | Does this work?
```suggestion
python3 scripts/pass_rate.py --reports ~/reports --json > $TMPFILE.json
``` |
intel-xpu-backend-for-triton | github_2023 | python | 442 | intel | whitneywhtsang | @@ -0,0 +1,122 @@
+"""Calculates and reports pass rate for unit tests."""
+
+import argparse
+import dataclasses
+import datetime
+import json
+import os
+import pathlib
+import platform
+import xml.etree.ElementTree as ET
+from typing import List
+
+
+@dataclasses.dataclass
+class ReportStats:
+ """Report stats."""... | Given that we xfailed all NVidia specific test cases, we may want to just print the second pass rate for simplicity. |
intel-xpu-backend-for-triton | github_2023 | cpp | 461 | intel | whitneywhtsang | @@ -45,6 +46,7 @@ inline void registerTritonDialects(mlir::DialectRegistry ®istry) {
// TODO: register Triton & TritonGPU passes
registry.insert<mlir::triton::TritonDialect, mlir::cf::ControlFlowDialect,
mlir::triton::nvidia_gpu::TritonNvidiaGPUDialect,
+ mlir::triton::gpu::... | [nit]
```suggestion
mlir::triton::gpu::intel::TritonIntelGPUDialect,
mlir::triton::nvidia_gpu::TritonNvidiaGPUDialect,
``` |
intel-xpu-backend-for-triton | github_2023 | others | 461 | intel | whitneywhtsang | @@ -2,3 +2,4 @@ add_subdirectory(Triton)
add_subdirectory(TritonGPU)
add_subdirectory(TritonNvidiaGPU)
add_subdirectory(NVGPU)
+add_subdirectory(TritonIntelGPU) | [nit]
```suggestion
add_subdirectory(TritonIntelGPU)
add_subdirectory(TritonNvidiaGPU)
add_subdirectory(NVGPU)
``` |
intel-xpu-backend-for-triton | github_2023 | others | 461 | intel | whitneywhtsang | @@ -0,0 +1,96 @@
+#ifndef TRITON_INTEL_GPU_ATTRDEFS
+#define TRITON_INTEL_GPU_ATTRDEFS
+
+include "mlir/IR/AttrTypeBase.td"
+include "triton/Dialect/TritonIntelGPU/IR/TritonIntelGPUDialect.td"
+include "triton/Dialect/TritonGPU/IR/TritonGPUAttrDefs.td"
+
+//===-----------------------------------------------------------... | ```suggestion
"unsigned":$opsPerChannel,
``` |
intel-xpu-backend-for-triton | github_2023 | others | 461 | intel | whitneywhtsang | @@ -0,0 +1,96 @@
+#ifndef TRITON_INTEL_GPU_ATTRDEFS
+#define TRITON_INTEL_GPU_ATTRDEFS
+
+include "mlir/IR/AttrTypeBase.td"
+include "triton/Dialect/TritonIntelGPU/IR/TritonIntelGPUDialect.td"
+include "triton/Dialect/TritonGPU/IR/TritonGPUAttrDefs.td"
+
+//===-----------------------------------------------------------... | ```suggestion
SmallVector<int64_t> getDPASRep(ArrayRef<int64_t> shape, int opIdx) const;
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 461 | intel | whitneywhtsang | @@ -13,14 +14,15 @@
using namespace mlir;
namespace tt = mlir::triton;
namespace ttg = mlir::triton::gpu;
+namespace ttig = mlir::triton::gpu::intel;
namespace {
using tt::DotOp;
using ttg::BlockedEncodingAttr;
using ttg::ConvertLayoutOp;
using ttg::DotOperandEncodingAttr;
-using ttg::DpasEncodingAttr;
using t... | ```suggestion
using triton::gpu::intel::DpasEncodingAttr;
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 461 | intel | whitneywhtsang | @@ -13,14 +14,15 @@
using namespace mlir;
namespace tt = mlir::triton;
namespace ttg = mlir::triton::gpu;
+namespace ttig = mlir::triton::gpu::intel; | ```suggestion
``` |
intel-xpu-backend-for-triton | github_2023 | python | 461 | intel | whitneywhtsang | @@ -163,15 +163,17 @@ def __str__(self):
class DpasLayout:
- def __init__(self, repeatCount, warps_per_cta, ctas_per_cga, cta_split_num, cta_order):
+ def __init__(self, repeatCount, systolic_depth, execution_size, ops_per_chan, threads_per_warp, warps_per_cta):
self.repeatCount = repeatCount
+ ... | remove? |
intel-xpu-backend-for-triton | github_2023 | cpp | 461 | intel | whitneywhtsang | @@ -108,7 +109,8 @@ void init_triton_intel(py::module &&m){
m.def("load_dialects", [](mlir::MLIRContext &context) {
mlir::DialectRegistry registry;
registry.insert<mlir::triton::nvidia_gpu::TritonNvidiaGPUDialect,
- mlir::triton::nvgpu::NVGPUDialect>();
+ mlir::triton:... | ```suggestion
mlir::triton::gpu::intel::TritonIntelGPUDialect,
mlir::triton::nvgpu::NVGPUDialect>();
``` |
intel-xpu-backend-for-triton | github_2023 | others | 461 | intel | whitneywhtsang | @@ -0,0 +1,96 @@
+#ifndef TRITON_INTEL_GPU_ATTRDEFS
+#define TRITON_INTEL_GPU_ATTRDEFS
+
+include "mlir/IR/AttrTypeBase.td"
+include "triton/Dialect/TritonIntelGPU/IR/TritonIntelGPUDialect.td"
+include "triton/Dialect/TritonGPU/IR/TritonGPUAttrDefs.td"
+
+//===-----------------------------------------------------------... | ```suggestion
The shape of the of XMX tensor core operation is defined by systolic depth, repeat count, execution size and operands per channel.
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 461 | intel | whitneywhtsang | @@ -0,0 +1,431 @@
+#include "triton/Dialect/Triton/IR/Dialect.h"
+
+#include <numeric>
+
+#include "mlir/IR/DialectImplementation.h"
+#include "mlir/IR/OpImplementation.h"
+#include "triton/Analysis/Utility.h"
+#include "triton/Dialect/TritonGPU/IR/Dialect.h"
+#include "triton/Dialect/TritonIntelGPU/IR/Dialect.h"
+
+#i... | remove |
intel-xpu-backend-for-triton | github_2023 | cpp | 461 | intel | etiotto | @@ -0,0 +1,26 @@
+#ifndef TRITON_DIALECT_TRITON_INTEL_GPU_IR_DIALECT_H_ | Drop trailing underscore:
TRITON_DIALECT_TRITON_INTEL_GPU_IR_DIALECT_H_ -> TRITON_DIALECT_TRITON_INTEL_GPU_IR_DIALECT_H
|
intel-xpu-backend-for-triton | github_2023 | others | 461 | intel | etiotto | @@ -0,0 +1,96 @@
+#ifndef TRITON_INTEL_GPU_ATTRDEFS
+#define TRITON_INTEL_GPU_ATTRDEFS
+
+include "mlir/IR/AttrTypeBase.td"
+include "triton/Dialect/TritonIntelGPU/IR/TritonIntelGPUDialect.td"
+include "triton/Dialect/TritonGPU/IR/TritonGPUAttrDefs.td"
+
+//===-----------------------------------------------------------... | MMA -> DPAS |
intel-xpu-backend-for-triton | github_2023 | others | 461 | intel | etiotto | @@ -0,0 +1,96 @@
+#ifndef TRITON_INTEL_GPU_ATTRDEFS
+#define TRITON_INTEL_GPU_ATTRDEFS
+
+include "mlir/IR/AttrTypeBase.td"
+include "triton/Dialect/TritonIntelGPU/IR/TritonIntelGPUDialect.td"
+include "triton/Dialect/TritonGPU/IR/TritonGPUAttrDefs.td"
+
+//===-----------------------------------------------------------... | Remove 2 empty lines pls. |
intel-xpu-backend-for-triton | github_2023 | others | 461 | intel | etiotto | @@ -0,0 +1,96 @@
+#ifndef TRITON_INTEL_GPU_ATTRDEFS
+#define TRITON_INTEL_GPU_ATTRDEFS
+
+include "mlir/IR/AttrTypeBase.td"
+include "triton/Dialect/TritonIntelGPU/IR/TritonIntelGPUDialect.td"
+include "triton/Dialect/TritonGPU/IR/TritonGPUAttrDefs.td"
+
+//===-----------------------------------------------------------... | type,. -> type. |
intel-xpu-backend-for-triton | github_2023 | others | 461 | intel | etiotto | @@ -0,0 +1,31 @@
+#ifndef TRITON_INTEL_GPU_DIALECT
+#define TRITON_INTEL_GPU_DIALECT
+
+include "mlir/IR/OpBase.td"
+
+def TritonIntelGPU_Dialect : Dialect {
+ let name = "triton_intel_gpu";
+
+ let cppNamespace = "::mlir::triton::gpu::intel";
+
+ let hasOperationAttrVerify = 1;
+
+ let description = [{
+ Triton... | why does this dialect depends on the TensorDialect ? |
intel-xpu-backend-for-triton | github_2023 | others | 461 | intel | etiotto | @@ -0,0 +1,19 @@
+#ifndef TRITON_INTEL_GPU_OPSDEFS
+#define TRITON_INTEL_GPU_OPSDEFS
+
+include "triton/Dialect/Triton/IR/TritonTypes.td"
+include "triton/Dialect/Triton/IR/TritonAttrDefs.td"
+include "triton/Dialect/TritonGPU/IR/TritonGPUDialect.td"
+include "triton/Dialect/TritonGPU/IR/TritonGPUTypes.td"
+include "tr... | Is this needed or can it be removed ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 461 | intel | etiotto | @@ -285,10 +285,15 @@ Value loadOperand(ConversionPatternRewriter &rewriter, Location loc,
auto sharedLayout = tensorTy.getEncoding().cast<SharedEncodingAttr>();
const ArrayRef<unsigned> order = sharedLayout.getOrder();
- Type elemTy = tensorTy.getElementType();
- SmallVector<int64_t> elemsPerInstr =
- e... | getXMXRep -> getDPASRepetitions |
intel-xpu-backend-for-triton | github_2023 | cpp | 461 | intel | etiotto | @@ -212,9 +212,6 @@ bool ReduceOpHelper::isSupportedLayout() {
if (auto mmaLayout = srcLayout.dyn_cast<triton::gpu::MmaEncodingTrait>()) {
return mmaLayout.supportReduction();
}
- if (auto dpasLayout = srcLayout.dyn_cast<triton::gpu::DpasEncodingAttr>()) { | Why can this be removed ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 461 | intel | etiotto | @@ -0,0 +1,431 @@
+#include "triton/Dialect/Triton/IR/Dialect.h"
+
+#include <numeric>
+
+#include "mlir/IR/DialectImplementation.h"
+#include "mlir/IR/OpImplementation.h"
+#include "triton/Analysis/Utility.h"
+#include "triton/Dialect/TritonGPU/IR/Dialect.h"
+#include "triton/Dialect/TritonIntelGPU/IR/Dialect.h"
+
+#i... | Please do fill this in this PR. |
intel-xpu-backend-for-triton | github_2023 | others | 461 | intel | etiotto | @@ -0,0 +1,28 @@
+#ifndef TRITON_INTEL_GPU_DIALECT
+#define TRITON_INTEL_GPU_DIALECT
+
+include "mlir/IR/OpBase.td"
+
+def TritonIntelGPU_Dialect : Dialect {
+ let name = "triton_intel_gpu";
+
+ let cppNamespace = "::mlir::triton::gpu::intel";
+
+ let description = [{
+ Triton Intel GPU Dialect.
+ }];
+
+ let d... | Remove, is empty. |
intel-xpu-backend-for-triton | github_2023 | cpp | 461 | intel | etiotto | @@ -0,0 +1,423 @@
+#include "triton/Dialect/Triton/IR/Dialect.h"
+
+#include <numeric>
+
+#include "mlir/IR/DialectImplementation.h"
+#include "mlir/IR/OpImplementation.h"
+#include "triton/Analysis/Utility.h"
+#include "triton/Dialect/TritonGPU/IR/Dialect.h"
+#include "triton/Dialect/TritonIntelGPU/IR/Dialect.h"
+
+#i... | MMA -> DPAS |
intel-xpu-backend-for-triton | github_2023 | cpp | 461 | intel | etiotto | @@ -0,0 +1,423 @@
+#include "triton/Dialect/Triton/IR/Dialect.h"
+
+#include <numeric>
+
+#include "mlir/IR/DialectImplementation.h"
+#include "mlir/IR/OpImplementation.h"
+#include "triton/Analysis/Utility.h"
+#include "triton/Dialect/TritonGPU/IR/Dialect.h"
+#include "triton/Dialect/TritonIntelGPU/IR/Dialect.h"
+
+#i... | mma -> DPAS |
intel-xpu-backend-for-triton | github_2023 | cpp | 461 | intel | etiotto | @@ -0,0 +1,423 @@
+#include "triton/Dialect/Triton/IR/Dialect.h"
+
+#include <numeric>
+
+#include "mlir/IR/DialectImplementation.h"
+#include "mlir/IR/OpImplementation.h"
+#include "triton/Analysis/Utility.h"
+#include "triton/Dialect/TritonGPU/IR/Dialect.h"
+#include "triton/Dialect/TritonIntelGPU/IR/Dialect.h"
+
+#i... | mmaRetEncoding -> dpasRetEncoding |
intel-xpu-backend-for-triton | github_2023 | others | 461 | intel | Jianhui-Li | @@ -537,123 +537,123 @@ module attributes {"triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 1 :
// -----
-#dpas = #triton_gpu.dpas<{repeatCount=8, warpsPerCTA=[1,1], CTAsPerCGA = [1, 1], CTASplitNum = [1, 1], CTAOrder = [0, 1]}>
-#dot_operand_a = #triton_gpu.dot_op<{opIdx=0, parent=#dpas}>
-#dot_operand_b... | if it is i8, then ops per chain should be 4, not 2. |
intel-xpu-backend-for-triton | github_2023 | others | 461 | intel | Jianhui-Li | @@ -537,123 +537,123 @@ module attributes {"triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 1 :
// -----
-#dpas = #triton_gpu.dpas<{repeatCount=8, warpsPerCTA=[1,1], CTAsPerCGA = [1, 1], CTASplitNum = [1, 1], CTAOrder = [0, 1]}>
-#dot_operand_a = #triton_gpu.dot_op<{opIdx=0, parent=#dpas}>
-#dot_operand_b... | what is purpose of "allowTF32 = true" when the data type is i8 and fp16? |
intel-xpu-backend-for-triton | github_2023 | others | 461 | intel | Jianhui-Li | @@ -537,123 +537,123 @@ module attributes {"triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 1 :
// -----
-#dpas = #triton_gpu.dpas<{repeatCount=8, warpsPerCTA=[1,1], CTAsPerCGA = [1, 1], CTASplitNum = [1, 1], CTAOrder = [0, 1]}>
-#dot_operand_a = #triton_gpu.dot_op<{opIdx=0, parent=#dpas}>
-#dot_operand_b... | warpsPerCTA = [1, 1] but "triton_gpu.num-warps" = 4 : i32
is the number of warps 1, or 4? |
intel-xpu-backend-for-triton | github_2023 | others | 461 | intel | Jianhui-Li | @@ -0,0 +1,94 @@
+#ifndef TRITON_INTEL_GPU_ATTRDEFS
+#define TRITON_INTEL_GPU_ATTRDEFS
+
+include "mlir/IR/AttrTypeBase.td"
+include "triton/Dialect/TritonIntelGPU/IR/TritonIntelGPUDialect.td"
+include "triton/Dialect/TritonGPU/IR/TritonGPUAttrDefs.td"
+
+//===-----------------------------------------------------------... | It is better to use Intel terminology consistently here. Say subgroupsPerWorkgroup |
intel-xpu-backend-for-triton | github_2023 | others | 461 | intel | Jianhui-Li | @@ -537,123 +537,123 @@ module attributes {"triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 1 :
// -----
-#dpas = #triton_gpu.dpas<{repeatCount=8, warpsPerCTA=[1,1], CTAsPerCGA = [1, 1], CTASplitNum = [1, 1], CTAOrder = [0, 1]}>
-#dot_operand_a = #triton_gpu.dot_op<{opIdx=0, parent=#dpas}>
-#dot_operand_b... | Need to assert (#blocked.threadsPerWarp[0] * #blocked.threadsPerWarp[0] == #mma.threadPerWarp) |
intel-xpu-backend-for-triton | github_2023 | cpp | 430 | intel | etiotto | @@ -30,14 +54,14 @@ computeWarpLevelHistogram(Location loc, RankedTensorType srcType,
// The histogram is distributed across threads, each thread owns `numBins /
// numThreadPerWarp` bins.
SmallVector<Value> warpLevelHistogram(numBins / numThreadPerWarp, zero);
+ Value laneId = and_(threadId, i32_val(numThrea... | To simplify merge conflict resolution it would work better to have:
```
if (target == Target::NVVM) {
// NV code here
} else {
// call generateVoteBallot
}
```
This way, if upstream code changes these lines we do not have to push the changes inside `generateVoteBallot`
|
intel-xpu-backend-for-triton | github_2023 | cpp | 430 | intel | etiotto | @@ -30,14 +54,14 @@ computeWarpLevelHistogram(Location loc, RankedTensorType srcType,
// The histogram is distributed across threads, each thread owns `numBins /
// numThreadPerWarp` bins.
SmallVector<Value> warpLevelHistogram(numBins / numThreadPerWarp, zero);
+ Value laneId = and_(threadId, i32_val(numThrea... | Can we just pass `threadMask` rather than passing -1 ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 430 | intel | etiotto | @@ -30,14 +54,14 @@ computeWarpLevelHistogram(Location loc, RankedTensorType srcType,
// The histogram is distributed across threads, each thread owns `numBins /
// numThreadPerWarp` bins.
SmallVector<Value> warpLevelHistogram(numBins / numThreadPerWarp, zero);
+ Value laneId = and_(threadId, i32_val(numThrea... | Can you compute this inside the `generateVoteBallot` (useful to reduce potential merge conflicts). |
intel-xpu-backend-for-triton | github_2023 | cpp | 414 | intel | whitneywhtsang | @@ -503,7 +503,9 @@ class ConvertTritonGPUOpToLLVMPatternBase {
auto warpsPerCTA = triton::gpu::getWarpsPerCTA(layout);
auto order = triton::gpu::getOrder(layout);
auto shapePerCTATile = triton::gpu::getShapePerCTATile(layout, shape);
- Value warpSize = i32_val(32);
+ auto mod = rewriter.... | AMD changed this line to `Value warpSize = i32_val(triton::gpu::getWarpSize(layout));`, can we do something similar?
https://github.com/intel/intel-xpu-backend-for-triton/blob/llvm-target/third_party/amd/lib/TritonAMDGPUToLLVM/TritonGPUToLLVMBase.h#L577 |
intel-xpu-backend-for-triton | github_2023 | python | 414 | intel | etiotto | @@ -369,11 +370,24 @@ def supports_target(target: tuple):
def __init__(self, target: tuple) -> None:
super().__init__(target)
- self.capability = target[1]
+ self.properties = target[1]
+ self.capability = self.properties["device_arch"]
assert isinstance(self.capability, in... | Instead of using 16 hard coded here, can you use the class member at line 340 you added ? |
intel-xpu-backend-for-triton | github_2023 | python | 414 | intel | etiotto | @@ -407,7 +407,12 @@ def format_of(ty):
sycl::queue stream = *(static_cast<sycl::queue*>(pStream));
sycl::kernel kernel = *(static_cast<sycl::kernel*>(pKrnl));
- auto threads_per_warp = 32;
+ int threads_per_warp = 32; | why is this 32 and not 16? |
intel-xpu-backend-for-triton | github_2023 | python | 414 | intel | whitneywhtsang | @@ -495,7 +496,7 @@ def make_llir(src, metadata, options, capability):
if options.extern_libs:
for name, path in options.extern_libs:
llvm.link_extern_lib(llvm_mod, path)
- llvm.optimize_module(llvm_mod, llvm.OPTIMIZE_O3)
+ llvm.optimize_module(llvm_mod, llvm.OPTIMIZ... | ```suggestion
llvm.optimize_module(llvm_mod, llvm.OPTIMIZE_O3)
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 414 | intel | whitneywhtsang | @@ -349,6 +346,10 @@ struct ReduceOpConversion
auto threadsPerWarp =
triton::gpu::getThreadsPerWarpWithUniqueData(srcLayout, srcShape);
auto order = getOrder(srcLayout);
+ Value warpSize = getModuleWarpSize(rewriter, loc); | Can we move them back to the original position? |
intel-xpu-backend-for-triton | github_2023 | python | 414 | intel | etiotto | @@ -2048,7 +2048,7 @@ def test_scan_layouts(M, N, src_layout, axis, device):
capability = 0
if torch.cuda.is_available():
capability = torch.cuda.get_device_capability()
- kernel = triton.compile(f.name, target=(device, capability))
+ kernel = triton.compile(f.name, target=(... | Do we have to explicitly set the threads per warp ? The default should work. |
intel-xpu-backend-for-triton | github_2023 | python | 414 | intel | etiotto | @@ -49,15 +49,15 @@ def test_assert(func: str):
x = torch.arange(0, shape[0], dtype=torch.int32, device='xpu')
y = torch.zeros(shape, dtype=x.dtype, device="xpu")
if func == "device_assert":
- kernel_device_assert[(1, )](x, y, BLOCK=shape[0])
+ kernel_device_assert[(1, )](x, y, BLOCK=shape[... | why do we need to explicitly state what the threads per warp size is ? |
intel-xpu-backend-for-triton | github_2023 | python | 414 | intel | etiotto | @@ -85,9 +85,9 @@ def test_print(func: str, data_type: str):
elif func == "static_print":
kernel_static_print[(1, )](x, y, BLOCK=shape[0], PLACEHOLDER=uuid.uuid4())
elif func == "no_arg_print":
- kernel_no_arg_print[(1, )](num_warps=4)
+ kernel_no_arg_print[(1, )](num_warps=4, threads_p... | This should work with any warp size and we shouldn't specify what is the size of the warp here. |
intel-xpu-backend-for-triton | github_2023 | python | 448 | intel | etiotto | @@ -4356,7 +4361,7 @@ def test_fp8_dot_acc(in_type_str, low_precision_acc, device):
pytest.skip('test_fp8_dot_acc for HIP currently broken in upstream.')
if is_xpu():
- pytest.xfail('test_fp8_dot_acc not supported on XPU.')
+ pytest.skip('FIXME: test_fp8_dot_acc not supported on XPU.') | Let's skip and investigate whether this is something we can support. |
intel-xpu-backend-for-triton | github_2023 | cpp | 434 | intel | whitneywhtsang | @@ -212,39 +212,44 @@ struct ReduceOpConversion
// region and the accumulator values as source.
void warpReduce(ConversionPatternRewriter &rewriter, Location loc,
SmallVector<Value> &acc, triton::ReduceOp op,
- unsigned numLaneToReduce, unsigned interleave) const {
- if (aut... | ```suggestion
if (target == Target::GENX)
return;
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 379 | intel | whitneywhtsang | @@ -1540,6 +1545,15 @@ struct InsertSliceAsyncOpConversion
LogicalResult
matchAndRewrite(triton::gpu::InsertSliceAsyncOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter) const override {
+
+ // This function should not be called on the genx target since all
+ // InsertSliceOps ... | ```suggestion
// InsertSliceAsyncOp would be decomposed into InsertSliceOps by the
``` |
intel-xpu-backend-for-triton | github_2023 | others | 379 | intel | whitneywhtsang | @@ -530,45 +530,6 @@ module attributes {"triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 8 :
// -----
-#block0 = #triton_gpu.blocked<{sizePerThread = [1], threadsPerWarp = [32], warpsPerCTA = [4], order = [0], CTAsPerCGA = [1], CTASplitNum = [1], CTAOrder = [0]}> | Note to other reviewers, this test is removed in https://github.com/intel/intel-xpu-backend-for-triton/commit/b39ae5550dc69e5ac8d981633cb7631642a9d224. |
intel-xpu-backend-for-triton | github_2023 | others | 432 | intel | pbchekin | @@ -81,8 +81,12 @@ fi
############################################################################
## Configure and build the llvm project.
-C_COMPILER=/usr/bin/gcc
-CXX_COMPILER=/usr/bin/g++
+if [ ! -d "$C_COMPILER" ] || [ ! -d "$CXX_COMPILER" ]; then | Wrong test `-d` for the variables. Also the logic is not clear: why if one is not set, then set both?
```
if [ -z "$C_COMPILER" ]; then
C_COMPILER="gcc"
fi
if [ -z "$CXX_COMPILER" ]; then
CXX_COMPILER="g++"
fi
```
|
intel-xpu-backend-for-triton | github_2023 | others | 432 | intel | pbchekin | @@ -1,7 +1,7 @@
#!/usr/bin/env bash
set +o xtrace
-if [ ! -d "$BASE" ]; then
+if [ ! -z "$BASE" ]; then | Bash `-z` is a test for empty string.
```suggestion
if [ -z "$BASE" ]; then
``` |
intel-xpu-backend-for-triton | github_2023 | others | 432 | intel | pbchekin | @@ -81,8 +81,14 @@ fi
############################################################################
## Configure and build the llvm project.
-C_COMPILER=/usr/bin/gcc
-CXX_COMPILER=/usr/bin/g++
+if [ ! -z "$C_COMPILER" ]; then | ```suggestion
if [ -z "$C_COMPILER" ]; then
``` |
intel-xpu-backend-for-triton | github_2023 | others | 432 | intel | pbchekin | @@ -81,8 +81,14 @@ fi
############################################################################
## Configure and build the llvm project.
-C_COMPILER=/usr/bin/gcc
-CXX_COMPILER=/usr/bin/g++
+if [ ! -z "$C_COMPILER" ]; then
+ C_COMPILER=`which gcc`
+ echo "**** C_COMPILER is set to $C_COMPILER ****"
+fi
+if [ ! ... | ```suggestion
if [ -z "$CXX_COMPILER" ]; then
``` |
intel-xpu-backend-for-triton | github_2023 | python | 424 | intel | whitneywhtsang | @@ -40,10 +40,6 @@ def is_spirv():
else:
THREADS_PER_WARP = 32
-if is_spirv(): | can we remove `is_spirv` function as well, this is the only user. |
intel-xpu-backend-for-triton | github_2023 | c | 429 | intel | whitneywhtsang | @@ -226,8 +229,14 @@ static PyObject *loadSyclBinary(PyObject *self, PyObject *args) {
auto l0_context = sycl::get_native<sycl::backend::ext_oneapi_level_zero>(ctx);
auto l0_module =
create_module(l0_context, l0_device, binary_ptr, binary_size);
-
+ | ```suggestion
``` |
intel-xpu-backend-for-triton | github_2023 | others | 420 | intel | pbchekin | @@ -4,7 +4,7 @@ set +o xtrace
if [ ! -d "$BASE" ]; then
echo "**** BASE is not given *****"
echo "**** Default BASE is set to /iusers/$USER ****" | This comment needs to be updated as well. |
intel-xpu-backend-for-triton | github_2023 | others | 420 | intel | pbchekin | @@ -4,7 +4,7 @@ set +o xtrace
if [ ! -d "$BASE" ]; then
echo "**** BASE is not given *****"
echo "**** Default BASE is set to /iusers/$USER ****"
- BASE=/iusers/$USER
+ BASE=$(dirname "$0")/../.. | What about setting it to $HOME instead? This script requires `$HOME/packages` anyway to compile Triton. |
intel-xpu-backend-for-triton | github_2023 | others | 420 | intel | pbchekin | @@ -3,8 +3,8 @@
set +o xtrace
if [ ! -d "$BASE" ]; then
echo "**** BASE is not given *****"
- echo "**** Default BASE is set to /iusers/$USER ****"
- BASE=/iusers/$USER
+ BASE=$(dirname "$0")/../.. | I am looking to the script and looks like $BASE needs to be absolute and currently it can be relative. For example, if i am running `./scripts/compile-triton.sh`, then BASE is `./scripts/../..` and we do `cd` in the following order:
```
cd $PACKAGES_DIR # cd ./scripts/../../packages,
cd $BASE # cd ./scripts/../.... |
intel-xpu-backend-for-triton | github_2023 | others | 420 | intel | pbchekin | @@ -43,8 +43,8 @@ fi
set +o xtrace
if [ ! -d "$BASE" ]; then
echo "**** BASE is not given *****"
- echo "**** Default BASE is set to /iusers/$USER ****"
- BASE=/iusers/$USER
+ BASE=$(dirname "$0")/../.. | Nit: use absolute BASE for consistency with `compile-triton.sh`. |
intel-xpu-backend-for-triton | github_2023 | cpp | 397 | intel | etiotto | @@ -1331,8 +1331,7 @@ struct FpToFpOpConversion
return builder.launch(rewriter, loc, f32_ty, false);
} break;
case mlir::triton::Target::GENX:
- return rewriter.create<GENX::FpToFpOp>(loc, f32_ty, v,
- GENX::RoundingMode::RTE);
+ return rewriter.cre... | Remove |
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