repo_name stringlengths 1 62 | dataset stringclasses 1
value | lang stringclasses 11
values | pr_id int64 1 20.1k | owner stringlengths 2 34 | reviewer stringlengths 2 39 | diff_hunk stringlengths 15 262k | code_review_comment stringlengths 1 99.6k |
|---|---|---|---|---|---|---|---|
intel-xpu-backend-for-triton | github_2023 | cpp | 734 | intel | victor-eds | @@ -84,6 +84,37 @@ struct GPUIndexIntrinsicOpLowering : public ConvertOpToLLVMPattern<Op> {
}
};
+template <typename SourceOp, typename TargetOp>
+class SingleDimLaunchConfigLowering : public ConvertOpToLLVMPattern<SourceOp> {
+private:
+ unsigned indexBitwidth;
+
+public:
+ explicit SingleDimLaunchConfigLoweri... | Make `32` a constant like `resBitWidth` |
intel-xpu-backend-for-triton | github_2023 | cpp | 734 | intel | chengjunlu | @@ -84,6 +84,37 @@ struct GPUIndexIntrinsicOpLowering : public ConvertOpToLLVMPattern<Op> {
}
};
+template <typename SourceOp, typename TargetOp>
+class SingleDimLaunchConfigLowering : public ConvertOpToLLVMPattern<SourceOp> {
+private:
+ unsigned indexBitwidth;
+
+public:
+ explicit SingleDimLaunchConfigLoweri... | Is it better to add assert to protect 3-D dimension ops from GPU dialect? |
intel-xpu-backend-for-triton | github_2023 | cpp | 734 | intel | etiotto | @@ -84,6 +84,37 @@ struct GPUIndexIntrinsicOpLowering : public ConvertOpToLLVMPattern<Op> {
}
};
+template <typename SourceOp, typename TargetOp>
+class SingleDimLaunchConfigLowering : public ConvertOpToLLVMPattern<SourceOp> {
+private:
+ unsigned indexBitwidth;
+
+public:
+ explicit SingleDimLaunchConfigLoweri... | auto -> Location |
intel-xpu-backend-for-triton | github_2023 | others | 734 | intel | etiotto | @@ -127,6 +127,18 @@ def TritonGEN_GridDimZOp : TritonGEN_Op<"grid.dim.z", [Pure]> {
}];
}
+//===----------------------------------------------------------------------===//
+// Subgroup index
+//===----------------------------------------------------------------------===//
+
+def TritonGEN_SubgroupIdOp : TritonGE... | Add description of the operator and summary. |
intel-xpu-backend-for-triton | github_2023 | cpp | 732 | intel | whitneywhtsang | @@ -104,10 +104,80 @@ std::string translateLLVMIRToASM(llvm::Module &module,
using ret = py::return_value_policy;
-void findKernels(llvm::Module &M, std::set<llvm::Function *> &functions) {
+static uint32_t findKernels(llvm::Module &M,
+ std::set<llvm::Function *> &functions) {
+ assert... | ```suggestion
++numKernels;
``` |
intel-xpu-backend-for-triton | github_2023 | others | 722 | intel | whitneywhtsang | @@ -1,8 +1,6 @@
// RUN: triton-opt %s --split-input-file --convert-triton-amdgpu-to-llvm | FileCheck %s
-// FIXME: Currently unable to invoke amd passes.
-// XFAIL: *
-// CHECK-LABEL: wmma_dot
+// CHECK-LABEL: wmma_dot | so reduce differences from openai repo:
```suggestion
// CHECK-LABEL: wmma_dot
``` |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture | Triton **A**rchitecture |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture
+###################
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, howev... | please write **T**riton with the capital first letter |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture
+###################
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, howev... | Rewrite to: "Triton [c1]_ [c10]_ serves two main purposes: as a Triton language JIT compiler and as a low-level backend compiler for PyTorch 2.0 [c2]_. While we mainly discuss the latter, we also consider the former and support other frameworks." |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture
+###################
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, howev... | Suggested chnages are in bold: "From the PyTorch **perspective**, a model FX graph [c3]_ is captured by Dynamo [c4]_ (and AOT Autograd if necessary)**,** which is **then** passed to Inductor [c5]_. The Inductor converts the broad set of PyTorch’s ATen operators into a narrower set of stable primitive operators (PrimTor... |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture
+###################
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, howev... | Code **G**eneration **O**verview |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture
+###################
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, howev... | Triton MLIR **C**ompiler **D**etails |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture
+###################
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, howev... | (**for example**, ptx/cubin in Nvidia case) |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture
+###################
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, howev... | global: replace "e.g." with "for example" |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture
+###################
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, howev... | In addition to the custom dialects**,** Triton reuses upstream ones like arith & math for math, scf/cf for control flow, index, func, nvvm for low-level GPU operations. |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture
+###################
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, howev... | removing views |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture
+###################
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, howev... | replace Future with Present tense |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture
+###################
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, howev... | **Note** that Inductor can replace these native aten implementations with triton templated kernels. |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture
+###################
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, howev... | Triton **F**rontend |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture
+###################
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, howev... | **P**ython-like |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture
+###################
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, howev... | in this case, **it equals** 1024 |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture
+###################
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, howev... | Triton **O**ptimizations |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture
+###################
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, howev... | There **are** some common passes like inline, |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture
+###################
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, howev... | Triton Dialect |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture
+###################
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, howev... | At this level, the optimizer runs: |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture
+###################
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, howev... | Shared Layout Class |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture
+###################
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, howev... | an array, fastest changing axis first**.** |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture
+###################
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, howev... | Boolean value; when set to true, means when matrix is stored **in** shared memory, there will be an offset not only in the stride dimension, but also in the leading dimension. |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture
+###################
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, howev... | Distributed Layout Class |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture
+###################
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, howev... | Blocked **L**ayout |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture
+###################
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, howev... | * **Order** – an array, fastest changing axis first**.** |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture
+###################
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, howev... | Below you can find a couple of examples from Triton’s inline doc |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture
+###################
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, howev... | global: Use capital first letters for each word (except articles, prepositions, conjunctions) in headings |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture
+###################
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, howev... | For Nvidia flow, these **are** emitted as inline assembly into LLVM |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture
+###################
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, howev... | Here is |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture
+###################
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, howev... | device-specific lowering |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture
+###################
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, howev... | From the execution perspective, the two modes are incompatible (in the driver) |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture
+###################
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, howev... | Thus, Intel GPU backed has two paths for Triton kernels compilation: |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture
+###################
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, howev... | users install **Intel® oneAPI Base Toolkit** to have access to the runtime library. |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture
+###################
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, howev... | Triton is typically used with PyTorch, where Triton kernels consume PyTorch tensors to represent custom operations. As a result, the Triton runtime must interact with PyTorch components to ensure synchronization. These components include |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture
+###################
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, howev... | Using the lowest level possible has **the** following benefits: |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture
+###################
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, howev... | Having one component use a low-level runtime while the other uses a high-level one creates interoperability issues. |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture
+###################
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, howev... | Ultimately, this means that Triton is forced to have a dependency on SYCL runtime only to wrap the native queue handles for other components to respect the synchronization point. |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture
+###################
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, howev... | Rewrite to: Another option is to integrate SYCL kernel invocation support into the Unified runtime, making it agnostic to the input. This approach positions the Unified runtime as a versatile tool for all components.
This enhancement enables Triton to operate independently of PyTorch, eliminating unnecessary depende... |
intel-xpu-backend-for-triton | github_2023 | others | 528 | intel | avladimi | @@ -0,0 +1,653 @@
+###################
+Triton architecture
+###################
+
+The goal of this document is to describe the high-level architecture and roadmap of the solution outlining components and interactions. The intended audience is triton & triton backend developers. No a priori knowledge is assumed, howev... | Triton will be able to operate independently of PyTorch, eliminating the need for redundant dependencies on the SYCL runtime. This allows Triton to showcase all the advantageous qualities of relying on a low-level runtime. |
intel-xpu-backend-for-triton | github_2023 | others | 677 | intel | etiotto | @@ -0,0 +1,40 @@
+// RUN: triton-opt %s -split-input-file --convert-triton-to-tritongpu-warp="num-warps=32" | FileCheck %s
+// CHECK: #triton_gpu.blocked<{sizePerThread = [32, 64], threadsPerWarp = [1, 1], warpsPerCTA = [8, 4], order = [1, 0]}>
+module {
+ tt.func public @matmul_kernel_with_block_pointers_0d1d2d3d4d5... | [nit]: Let's us a simpler name for the function (no "0d1d2d3d4d5d") |
intel-xpu-backend-for-triton | github_2023 | others | 677 | intel | etiotto | @@ -0,0 +1,40 @@
+// RUN: triton-opt %s -split-input-file --convert-triton-to-tritongpu-warp="num-warps=32" | FileCheck %s
+// CHECK: #triton_gpu.blocked<{sizePerThread = [32, 64], threadsPerWarp = [1, 1], warpsPerCTA = [8, 4], order = [1, 0]}> | Please add a CHECK in the function body to ensure this layout is used by the dot operation. |
intel-xpu-backend-for-triton | github_2023 | others | 677 | intel | etiotto | @@ -0,0 +1,41 @@
+// RUN: triton-opt %s -split-input-file | FileCheck %s
+// CHECK: tt.func
+#blocked = #triton_gpu.blocked<{sizePerThread = [32, 64], threadsPerWarp = [1, 1], warpsPerCTA = [8, 4], order = [1, 0]}>
+module attributes {"triton_gpu.compute-capability" = 90 : i32, "triton_gpu.num-ctas" = 1 : i32, "triton_... | remove "_0d1d2d3d4d5d" |
intel-xpu-backend-for-triton | github_2023 | others | 677 | intel | etiotto | @@ -0,0 +1,41 @@
+// RUN: triton-opt %s -split-input-file | FileCheck %s | Can we explicitly add the the conversion pass to run here. |
intel-xpu-backend-for-triton | github_2023 | others | 677 | intel | etiotto | @@ -34,4 +34,26 @@ def ConvertTritonToTritonGPU: Pass<"convert-triton-to-tritongpu", "mlir::ModuleO
];
}
+def ConvertTritonToTritonGPUWarp: Pass<"convert-triton-to-tritongpu-warp", "mlir::ModuleOp"> {
+ let summary = "Convert Triton to TritonGPU with warp distribute annotation";
+ let description = [{
+ | Missing description |
intel-xpu-backend-for-triton | github_2023 | cpp | 677 | intel | etiotto | @@ -19,11 +19,15 @@ constexpr static char AttrNumThreadsPerWarp[] = "triton_gpu.threads-per-warp";
// Create the pass with numWarps passed from cl::opt.
std::unique_ptr<OperationPass<ModuleOp>> createConvertTritonToTritonGPUPass();
+std::unique_ptr<OperationPass<ModuleOp>>
+createConvertTritonToTritonGPUWarpPass();... | int -> unsigned |
intel-xpu-backend-for-triton | github_2023 | cpp | 677 | intel | etiotto | @@ -0,0 +1,537 @@
+#include "triton/Conversion/TritonToTritonGPU/TritonToTritonGPUPass.h"
+
+#include "mlir/Dialect/Arith/IR/Arith.h"
+#include "mlir/Dialect/ControlFlow/IR/ControlFlowOps.h"
+#include "mlir/Dialect/GPU/IR/GPUDialect.h"
+#include "mlir/Dialect/Index/IR/IndexDialect.h"
+#include "mlir/Pass/Pass.h"
+#incl... | Please document what this pass does |
intel-xpu-backend-for-triton | github_2023 | cpp | 677 | intel | etiotto | @@ -0,0 +1,537 @@
+#include "triton/Conversion/TritonToTritonGPU/TritonToTritonGPUPass.h"
+
+#include "mlir/Dialect/Arith/IR/Arith.h"
+#include "mlir/Dialect/ControlFlow/IR/ControlFlowOps.h"
+#include "mlir/Dialect/GPU/IR/GPUDialect.h"
+#include "mlir/Dialect/Index/IR/IndexDialect.h"
+#include "mlir/Pass/Pass.h"
+#incl... | int -> unsigned |
intel-xpu-backend-for-triton | github_2023 | cpp | 677 | intel | etiotto | @@ -0,0 +1,537 @@
+#include "triton/Conversion/TritonToTritonGPU/TritonToTritonGPUPass.h" | Add copyright |
intel-xpu-backend-for-triton | github_2023 | cpp | 677 | intel | etiotto | @@ -0,0 +1,537 @@
+#include "triton/Conversion/TritonToTritonGPU/TritonToTritonGPUPass.h"
+
+#include "mlir/Dialect/Arith/IR/Arith.h"
+#include "mlir/Dialect/ControlFlow/IR/ControlFlowOps.h"
+#include "mlir/Dialect/GPU/IR/GPUDialect.h"
+#include "mlir/Dialect/Index/IR/IndexDialect.h"
+#include "mlir/Pass/Pass.h"
+#incl... | These traces should not be emitted by default. I suggest to use LLVM_DEBUG facilities to print out the traces. |
intel-xpu-backend-for-triton | github_2023 | cpp | 677 | intel | etiotto | @@ -0,0 +1,537 @@
+#include "triton/Conversion/TritonToTritonGPU/TritonToTritonGPUPass.h"
+
+#include "mlir/Dialect/Arith/IR/Arith.h"
+#include "mlir/Dialect/ControlFlow/IR/ControlFlowOps.h"
+#include "mlir/Dialect/GPU/IR/GPUDialect.h"
+#include "mlir/Dialect/Index/IR/IndexDialect.h"
+#include "mlir/Pass/Pass.h"
+#incl... | These `if`, `else if` chain should be changed into a switch. |
intel-xpu-backend-for-triton | github_2023 | cpp | 677 | intel | etiotto | @@ -0,0 +1,537 @@
+#include "triton/Conversion/TritonToTritonGPU/TritonToTritonGPUPass.h"
+
+#include "mlir/Dialect/Arith/IR/Arith.h"
+#include "mlir/Dialect/ControlFlow/IR/ControlFlowOps.h"
+#include "mlir/Dialect/GPU/IR/GPUDialect.h"
+#include "mlir/Dialect/Index/IR/IndexDialect.h"
+#include "mlir/Pass/Pass.h"
+#incl... | assert statement should have a msg. e.g. assert(cond && "msg"); |
intel-xpu-backend-for-triton | github_2023 | others | 677 | intel | whitneywhtsang | @@ -34,4 +34,28 @@ def ConvertTritonToTritonGPU: Pass<"convert-triton-to-tritongpu", "mlir::ModuleO
];
}
+def ConvertTritonToTritonGPUWarp: Pass<"convert-triton-to-tritongpu-warp", "mlir::ModuleOp"> {
+ let summary = "Convert Triton to TritonGPU with warp distribute annotation";
+ let description = [{
+ ... | ```suggestion
This pass first analyze the kernel's workload pattern (elementwise/reduction/gemm/attention),
and then figure out the best layout for key/anchor operation (dot in gemm case).
Afterwards, we can get all other operation’s layout through def/use chain.
Finally, each tensor... |
intel-xpu-backend-for-triton | github_2023 | cpp | 677 | intel | whitneywhtsang | @@ -0,0 +1,465 @@
+//===- TritonToTritonGPUWarpPass.cpp - ------------------------*- C++ -*-===//
+//
+// Copyright 2024 Intel Corporation
+// Part of the intel-xpu-backend-for-trito Project, under the Apache License
+// v2.0 with LLVM Exceptions. See https://llvm.org/LICENSE.txt for license
+// information. SPDX-Lice... | ```suggestion
/// This file implements a pass to convert triton to tritongpu with warp
/// distribute annotation. This pass first analyze the kernel's workload
/// pattern (elementwise/reduction/gemm/attention),
/// and then figure out the best layout for key/anchor operation (dot in
/// gemm case). Afterwards, we... |
intel-xpu-backend-for-triton | github_2023 | cpp | 677 | intel | whitneywhtsang | @@ -0,0 +1,465 @@
+//===- TritonToTritonGPUWarpPass.cpp - ------------------------*- C++ -*-===//
+//
+// Copyright 2024 Intel Corporation
+// Part of the intel-xpu-backend-for-trito Project, under the Apache License
+// v2.0 with LLVM Exceptions. See https://llvm.org/LICENSE.txt for license
+// information. SPDX-Lice... | Why do we need to define `DBGS`? It is only used in `LDBG`. |
intel-xpu-backend-for-triton | github_2023 | cpp | 677 | intel | whitneywhtsang | @@ -0,0 +1,465 @@
+//===- TritonToTritonGPUWarpPass.cpp - ------------------------*- C++ -*-===//
+//
+// Copyright 2024 Intel Corporation
+// Part of the intel-xpu-backend-for-trito Project, under the Apache License
+// v2.0 with LLVM Exceptions. See https://llvm.org/LICENSE.txt for license
+// information. SPDX-Lice... | This comment is confusing to me. |
intel-xpu-backend-for-triton | github_2023 | cpp | 677 | intel | whitneywhtsang | @@ -0,0 +1,465 @@
+//===- TritonToTritonGPUWarpPass.cpp - ------------------------*- C++ -*-===//
+//
+// Copyright 2024 Intel Corporation
+// Part of the intel-xpu-backend-for-trito Project, under the Apache License
+// v2.0 with LLVM Exceptions. See https://llvm.org/LICENSE.txt for license
+// information. SPDX-Lice... | ```suggestion
// TODO: add more
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 677 | intel | whitneywhtsang | @@ -0,0 +1,465 @@
+//===- TritonToTritonGPUWarpPass.cpp - ------------------------*- C++ -*-===//
+//
+// Copyright 2024 Intel Corporation
+// Part of the intel-xpu-backend-for-trito Project, under the Apache License
+// v2.0 with LLVM Exceptions. See https://llvm.org/LICENSE.txt for license
+// information. SPDX-Lice... | Can we guard all `dump`s in `LLVM_DEBUG`? |
intel-xpu-backend-for-triton | github_2023 | cpp | 677 | intel | whitneywhtsang | @@ -0,0 +1,465 @@
+//===- TritonToTritonGPUWarpPass.cpp - ------------------------*- C++ -*-===//
+//
+// Copyright 2024 Intel Corporation
+// Part of the intel-xpu-backend-for-trito Project, under the Apache License
+// v2.0 with LLVM Exceptions. See https://llvm.org/LICENSE.txt for license
+// information. SPDX-Lice... | ```suggestion
assert(dots.size() <= 2 && "only support 1 or 2 dot in a loop");
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 677 | intel | whitneywhtsang | @@ -0,0 +1,465 @@
+//===- TritonToTritonGPUWarpPass.cpp - ------------------------*- C++ -*-===//
+//
+// Copyright 2024 Intel Corporation
+// Part of the intel-xpu-backend-for-trito Project, under the Apache License
+// v2.0 with LLVM Exceptions. See https://llvm.org/LICENSE.txt for license
+// information. SPDX-Lice... | remove? |
intel-xpu-backend-for-triton | github_2023 | cpp | 677 | intel | whitneywhtsang | @@ -0,0 +1,465 @@
+//===- TritonToTritonGPUWarpPass.cpp - ------------------------*- C++ -*-===//
+//
+// Copyright 2024 Intel Corporation
+// Part of the intel-xpu-backend-for-trito Project, under the Apache License
+// v2.0 with LLVM Exceptions. See https://llvm.org/LICENSE.txt for license
+// information. SPDX-Lice... | is it possible to have both generic and block pointers in one loop? Should we give up in that case? |
intel-xpu-backend-for-triton | github_2023 | cpp | 713 | intel | whitneywhtsang | @@ -1706,22 +1706,42 @@ struct FpToFpOpConversion
static Value convertFp32ToFp16(Location loc,
ConversionPatternRewriter &rewriter,
const Value &v, const RoundingMode rounding) {
- auto ctx = rewriter.getContext();
+ MLIRContext *ctx = rewrite... | Please put a FIXME to indicate that we don't want to use `llvm.genx.GenISA.ftof`. |
intel-xpu-backend-for-triton | github_2023 | others | 711 | intel | pbchekin | @@ -60,10 +60,47 @@ export SCRIPTS_DIR=$(dirname "$0")
python3 -m pip install lit
python3 -m pip install pytest pytest-xdist pytest-rerunfailures
-$SCRIPTS_DIR/compile-pytorch-ipex.sh $ARGS
-if [ $? -ne 0 ]; then
- echo "FAILED: return code $?"
- exit $?
+# Determine if the installed PyTorch version is the same a... | What about using more universal way, like this:
```suggestion
PYTHON_VERSION=$( python -c "import sys; print(f'{sys.version_info.major}.{sys.version_info.minor}')" )
cd wheels-py${PYTHON_VERSION}*
``` |
intel-xpu-backend-for-triton | github_2023 | others | 711 | intel | etiotto | @@ -83,14 +138,13 @@ build_pytorch() {
echo "**** Cloning $PYTORCH_PROJ ****"
cd $BASE
git clone --single-branch -b dev/triton-test-3.0 --recurse-submodules --jobs 8 https://github.com/Stonepia/pytorch.git
+ PYTORCH_COMMIT_ID="$(<$BASE/intel-xpu-backend-for-triton/.github/pins/pytorch.txt)" | If `--pinned` is in effect then you can build the pinned commit, otherwise I think build whatever commit is in the source code tree (for both PyTorch and IPEX). |
intel-xpu-backend-for-triton | github_2023 | others | 711 | intel | etiotto | @@ -17,6 +19,14 @@ for arg in "$@"; do
BUILD_IPEX=true
shift
;;
+ --pinned)
+ BUILD_PINNED=true | After reading the changes I realized --pinned means to build a pinned commit (for PyTorch and/or IPEX). The `--source` flag is orthogonal so `--source --pinned` means to build a pinned commit from source, and `--pinned` means to download a pinned wheel.
Of course if the `gc` command is missing... then downloading t... |
intel-xpu-backend-for-triton | github_2023 | cpp | 704 | intel | ienkovich | @@ -58,7 +57,20 @@ computeWarpLevelHistogram(Location loc, RankedTensorType srcType,
numThreadPerWarp, rewriter);
ballotBits.push_back(bit);
}
- Value fullMask = i32_val(0xFFFFFFFF);
+
+ uint64_t fullMaskValue = 0x0; | You can use shorter `((uint64_t)1 << numThreadPerWarp) - 1` for all numThreadPerWarp < 64. |
intel-xpu-backend-for-triton | github_2023 | python | 704 | intel | whitneywhtsang | @@ -37,7 +37,7 @@ class XPUOptions:
num_ctas: int = 1
num_stages: int = 2
cluster_dims: tuple = (1, 1, 1)
- threads_per_warp: int = 32 | We need to careful that this change doesn't cause performance regression in TorchDynamo benchmarks. |
intel-xpu-backend-for-triton | github_2023 | cpp | 704 | intel | ienkovich | @@ -58,7 +57,9 @@ computeWarpLevelHistogram(Location loc, RankedTensorType srcType,
numThreadPerWarp, rewriter);
ballotBits.push_back(bit);
}
- Value fullMask = i32_val(0xFFFFFFFF);
+
+ uint64_t fullMaskValue = (1u << numThreadPerWarp) - 1u; | `(1u << 32)` is 0, so you should use 64bit integer here. |
intel-xpu-backend-for-triton | github_2023 | cpp | 710 | intel | whitneywhtsang | @@ -230,23 +231,24 @@ Type getSharedMemTy(Type argType) {
template <unsigned opIdx>
std::function<void(int, int)>
-getLoadMatrixFn(Value tensor, const SharedMemoryObject &smemObj,
+getLoadMatrixFn(MemDescType descTy, const SharedMemoryObject &smemObj,
DpasEncodingAttr dpasLayout, unsigned warpsPerT... | ```suggestion
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 710 | intel | etiotto | @@ -44,11 +44,10 @@ Value lowerSharedToDotOperandDPAS(
const DpasEncodingAttr &dpasLayout,
const DotOperandEncodingAttr &dotOperandLayout, bool isOuter) {
auto loc = op.getLoc();
- Value src = op.getSrc();
+ auto src = op.getSrc(); | Triton `uses` auto pervasively. The LLVM coding guidelines (https://llvm.org/docs/CodingStandards.html#use-auto-type-deduction-to-make-code-more-readable) state that `auto` should be used more sparingly:
```
Use auto if and only if it makes the code more readable or easier to maintain. Don’t “almost always” use ... |
intel-xpu-backend-for-triton | github_2023 | cpp | 690 | intel | whitneywhtsang | @@ -21,12 +21,25 @@ namespace py = pybind11;
void init_triton_intel_passes_ttgpuir(py::module &&m) {
using namespace mlir::triton::gpu;
+
+ // Device arch
+ py::enum_<mlir::triton::gpu::intel::DeviceArch>(m, "DEVICE_ARCH",
+ py::module_local())
+ .value("ATS... | Why do we need unknown, from device properties, we supposed to always know the device architecture, and if it is not ats or pvc, then we should add to the list? |
intel-xpu-backend-for-triton | github_2023 | cpp | 690 | intel | whitneywhtsang | @@ -12,8 +12,22 @@
#include "mlir/Pass/Pass.h"
namespace mlir {
+namespace triton {
+namespace gpu {
+namespace intel {
-std::unique_ptr<Pass> createTritonIntelGPUAccelerateMatmulPass();
+enum class DeviceArch {
+ ATS = 0,
+ PVC = 1,
+ UNKNOWN, | remove? |
intel-xpu-backend-for-triton | github_2023 | cpp | 690 | intel | whitneywhtsang | @@ -24,24 +25,152 @@
using namespace mlir;
namespace tt = mlir::triton;
namespace ttg = mlir::triton::gpu;
-namespace ttgi = mlir::triton::gpu::intel;
+namespace ttig = mlir::triton::gpu::intel; | Got the review comment before to change this from ttig to ttgi |
intel-xpu-backend-for-triton | github_2023 | cpp | 690 | intel | whitneywhtsang | @@ -24,24 +25,152 @@
using namespace mlir;
namespace tt = mlir::triton;
namespace ttg = mlir::triton::gpu;
-namespace ttgi = mlir::triton::gpu::intel;
+namespace ttig = mlir::triton::gpu::intel;
namespace {
using tt::DotOp;
using ttg::BlockedEncodingAttr;
using ttg::ConvertLayoutOp;
using ttg::DotOperandEncodin... | If DeviceArch::UNKNOWN is not allowed, then we don't need this assert. |
intel-xpu-backend-for-triton | github_2023 | others | 690 | intel | whitneywhtsang | @@ -0,0 +1,71 @@
+// RUN: triton-opt %s -split-input-file --tritonintelgpu-accelerate-matmul=device-architecture=PVC | FileCheck %s --check-prefix=CHECK-PVC
+// RUN: triton-opt %s -split-input-file --tritonintelgpu-accelerate-matmul=device-architecture=ATS | FileCheck %s --check-prefix=CHECK-ATS
+
+// CHECK-PVC: #[[MMA... | add CHECK-ATS to ensure dpas layout is not generated for ATS. |
intel-xpu-backend-for-triton | github_2023 | others | 690 | intel | whitneywhtsang | @@ -0,0 +1,71 @@
+// RUN: triton-opt %s -split-input-file --tritonintelgpu-accelerate-matmul=device-architecture=PVC | FileCheck %s --check-prefix=CHECK-PVC
+// RUN: triton-opt %s -split-input-file --tritonintelgpu-accelerate-matmul=device-architecture=ATS | FileCheck %s --check-prefix=CHECK-ATS
+
+// CHECK-PVC: #[[MMA... | add CHECK-PVC to ensure dpas layout is not generated for PVC. |
intel-xpu-backend-for-triton | github_2023 | python | 690 | intel | whitneywhtsang | @@ -111,7 +111,7 @@ def make_ttgir(mod, metadata, opt, capability):
intel.passes.ttnvgpuir.add_plan_cta(pm, cluster_info)
passes.ttgpuir.add_remove_layout_conversions(pm)
passes.ttgpuir.add_optimize_thread_locality(pm)
- passes.ttgpuir.add_accelerate_matmul(pm, capability)
+ int... | should we pass `DeviceArch::PVC` here? |
intel-xpu-backend-for-triton | github_2023 | cpp | 690 | intel | whitneywhtsang | @@ -12,8 +12,22 @@
#include "mlir/Pass/Pass.h"
namespace mlir {
+namespace triton {
+namespace gpu {
+namespace intel {
-std::unique_ptr<Pass> createTritonIntelGPUAccelerateMatmulPass();
+enum class DeviceArch {
+ ATS = 0,
+ PVC = 1,
+ NUMBER_INVALID, | Let's remove `NUMBER_INVALID`. |
intel-xpu-backend-for-triton | github_2023 | cpp | 690 | intel | etiotto | @@ -12,8 +12,22 @@
#include "mlir/Pass/Pass.h"
namespace mlir {
+namespace triton {
+namespace gpu {
+namespace intel {
-std::unique_ptr<Pass> createTritonIntelGPUAccelerateMatmulPass();
+enum class DeviceArch {
+ ATS = 0,
+ PVC = 1,
+ NUMBER_INVALID,
+};
+
+} // namespace intel
+} // namespace gpu
+} // names... | The default should be UNKNOWN |
intel-xpu-backend-for-triton | github_2023 | others | 690 | intel | etiotto | @@ -27,6 +27,15 @@ def TritonIntelGPUAccelerateMatmul
"mlir::triton::gpu::intel::TritonIntelGPUDialect",
"mlir::triton::TritonDialect"
];
+
+ let options = [
+ Option<"deviceArch", "device-architecture",
+ "mlir::triton::gpu::intel::DeviceArch", /*default*/" mlir::triton::gpu::intel::DeviceA... | add unknown as well |
intel-xpu-backend-for-triton | github_2023 | cpp | 690 | intel | etiotto | @@ -382,17 +379,6 @@ static void decomposeMixedModeDotOp(ModuleOp mod) {
if (!isFP8 || (isNativeHopperFP8 && mmaLayout.isHopper()))
return;
promoteType = builder.getF16Type();
- } else if (auto dpasLayout = D.getType() | Note: if this is common code it *should* handle all devices (from all vendors). IF it is not common code, then it should be in the third_party directory. OpenAI will prob. move this code into the third_party directory in the future. |
intel-xpu-backend-for-triton | github_2023 | cpp | 690 | intel | etiotto | @@ -31,17 +32,144 @@ using ttg::BlockedEncodingAttr;
using ttg::ConvertLayoutOp;
using ttg::DotOperandEncodingAttr;
using ttg::SliceEncodingAttr;
+using ttgi::DeviceArch;
using ttgi::DpasEncodingAttr;
+struct IntelDPASCapability {
+ uint32_t systolicDepth;
+ uint32_t repeatCount;
+ uint32_t executionSize;
+ u... | Remove the 2 and make the return small vector capable of handling any size. |
intel-xpu-backend-for-triton | github_2023 | cpp | 690 | intel | etiotto | @@ -31,17 +32,144 @@ using ttg::BlockedEncodingAttr;
using ttg::ConvertLayoutOp;
using ttg::DotOperandEncodingAttr;
using ttg::SliceEncodingAttr;
+using ttgi::DeviceArch;
using ttgi::DpasEncodingAttr;
+struct IntelDPASCapability {
+ uint32_t systolicDepth;
+ uint32_t repeatCount;
+ uint32_t executionSize;
+ u... | ```suggestion
SmallVector<unsigned> ret{1, 1};
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 690 | intel | etiotto | @@ -31,17 +32,144 @@ using ttg::BlockedEncodingAttr;
using ttg::ConvertLayoutOp;
using ttg::DotOperandEncodingAttr;
using ttg::SliceEncodingAttr;
+using ttgi::DeviceArch;
using ttgi::DpasEncodingAttr;
+struct IntelDPASCapability {
+ uint32_t systolicDepth;
+ uint32_t repeatCount;
+ uint32_t executionSize;
+ u... | The c-like cast is ugly. Remove it and change the enum class underlying data type to be uint32_t |
intel-xpu-backend-for-triton | github_2023 | cpp | 690 | intel | etiotto | @@ -31,17 +32,144 @@ using ttg::BlockedEncodingAttr;
using ttg::ConvertLayoutOp;
using ttg::DotOperandEncodingAttr;
using ttg::SliceEncodingAttr;
+using ttgi::DeviceArch;
using ttgi::DpasEncodingAttr;
+struct IntelDPASCapability {
+ uint32_t systolicDepth;
+ uint32_t repeatCount;
+ uint32_t executionSize;
+ u... | Instead of assigning can we just initialize (saves a copy). |
intel-xpu-backend-for-triton | github_2023 | cpp | 690 | intel | etiotto | @@ -31,17 +32,144 @@ using ttg::BlockedEncodingAttr;
using ttg::ConvertLayoutOp;
using ttg::DotOperandEncodingAttr;
using ttg::SliceEncodingAttr;
+using ttgi::DeviceArch;
using ttgi::DpasEncodingAttr;
+struct IntelDPASCapability {
+ uint32_t systolicDepth;
+ uint32_t repeatCount;
+ uint32_t executionSize;
+ u... | Please add comments to explain what this code snipped is doing. |
intel-xpu-backend-for-triton | github_2023 | cpp | 690 | intel | etiotto | @@ -31,17 +32,144 @@ using ttg::BlockedEncodingAttr;
using ttg::ConvertLayoutOp;
using ttg::DotOperandEncodingAttr;
using ttg::SliceEncodingAttr;
+using ttgi::DeviceArch;
using ttgi::DpasEncodingAttr;
+struct IntelDPASCapability {
+ uint32_t systolicDepth;
+ uint32_t repeatCount;
+ uint32_t executionSize;
+ u... | Add comments to explain the code gen strategy this class implements, which cases it can handle and which it cannot. |
intel-xpu-backend-for-triton | github_2023 | cpp | 690 | intel | etiotto | @@ -31,17 +32,144 @@ using ttg::BlockedEncodingAttr;
using ttg::ConvertLayoutOp;
using ttg::DotOperandEncodingAttr;
using ttg::SliceEncodingAttr;
+using ttgi::DeviceArch;
using ttgi::DpasEncodingAttr;
+struct IntelDPASCapability {
+ uint32_t systolicDepth;
+ uint32_t repeatCount;
+ uint32_t executionSize;
+ u... | Do not use auto when the return type is not immediately clear from the context please. |
intel-xpu-backend-for-triton | github_2023 | cpp | 690 | intel | etiotto | @@ -31,17 +32,144 @@ using ttg::BlockedEncodingAttr;
using ttg::ConvertLayoutOp;
using ttg::DotOperandEncodingAttr;
using ttg::SliceEncodingAttr;
+using ttgi::DeviceArch;
using ttgi::DpasEncodingAttr;
+struct IntelDPASCapability {
+ uint32_t systolicDepth;
+ uint32_t repeatCount;
+ uint32_t executionSize;
+ u... | int -> unsigned? numWarps can never be negative. |
intel-xpu-backend-for-triton | github_2023 | cpp | 690 | intel | etiotto | @@ -31,17 +32,144 @@ using ttg::BlockedEncodingAttr;
using ttg::ConvertLayoutOp;
using ttg::DotOperandEncodingAttr;
using ttg::SliceEncodingAttr;
+using ttgi::DeviceArch;
using ttgi::DpasEncodingAttr;
+struct IntelDPASCapability {
+ uint32_t systolicDepth;
+ uint32_t repeatCount;
+ uint32_t executionSize;
+ u... | auto -> IntelDPASCapability |
intel-xpu-backend-for-triton | github_2023 | cpp | 690 | intel | etiotto | @@ -31,17 +32,144 @@ using ttg::BlockedEncodingAttr;
using ttg::ConvertLayoutOp;
using ttg::DotOperandEncodingAttr;
using ttg::SliceEncodingAttr;
+using ttgi::DeviceArch;
using ttgi::DpasEncodingAttr;
+struct IntelDPASCapability {
+ uint32_t systolicDepth;
+ uint32_t repeatCount;
+ uint32_t executionSize;
+ u... | auto -> unsigned... let's use the proper C++ data type throughout. |
intel-xpu-backend-for-triton | github_2023 | cpp | 690 | intel | etiotto | @@ -108,21 +235,25 @@ class TritonIntelGPUAccelerateMatmulPass
TritonIntelGPUAccelerateMatmulPass> {
public:
TritonIntelGPUAccelerateMatmulPass() = default;
+ TritonIntelGPUAccelerateMatmulPass(ttgi::DeviceArch arch) {
+ this->deviceArch = arch;
+ } | ```suggestion
TritonIntelGPUAccelerateMatmulPass(ttgi::DeviceArch arch) : deviceArch(arch) { }
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 690 | intel | etiotto | @@ -108,21 +235,25 @@ class TritonIntelGPUAccelerateMatmulPass
TritonIntelGPUAccelerateMatmulPass> {
public:
TritonIntelGPUAccelerateMatmulPass() = default; | Can we remove this constructor, we should always pass a target arch. |
intel-xpu-backend-for-triton | github_2023 | cpp | 690 | intel | etiotto | @@ -14,8 +14,30 @@ namespace triton {
namespace gpu {
namespace intel {
-bool supportDPAS(DotOp op) {
- return getDPASType(op) != DPASEngineType::NOT_APPLICABLE;
+bool supportDPAS(DotOp op, DeviceArch arch) {
+ assert(arch < DeviceArch::NUMBER_INVALID && "invalid arch"); | If we had an Unknow arch this function should return false if the architecture is not known. So we can remove the assert. |
intel-xpu-backend-for-triton | github_2023 | cpp | 690 | intel | etiotto | @@ -21,12 +21,24 @@ namespace py = pybind11;
void init_triton_intel_passes_ttgpuir(py::module &&m) {
using namespace mlir::triton::gpu;
+
+ // Device arch
+ py::enum_<mlir::triton::gpu::intel::DeviceArch>(m, "DEVICE_ARCH",
+ py::module_local())
+ .value("ATS... | It should not be PVC by default. It should be unknown. When pytorch passes to Triton the device architecture we can use that information to affect the matmul codegen but by default we will have to generate FMAs.
|
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