repo_name stringlengths 1 62 | dataset stringclasses 1
value | lang stringclasses 11
values | pr_id int64 1 20.1k | owner stringlengths 2 34 | reviewer stringlengths 2 39 | diff_hunk stringlengths 15 262k | code_review_comment stringlengths 1 99.6k |
|---|---|---|---|---|---|---|---|
intel-xpu-backend-for-triton | github_2023 | others | 690 | intel | etiotto | @@ -27,6 +27,16 @@ def TritonIntelGPUAccelerateMatmul
"mlir::triton::gpu::intel::TritonIntelGPUDialect",
"mlir::triton::TritonDialect"
];
+
+ let options = [
+ Option<"deviceArch", "device-architecture",
+ "mlir::triton::gpu::intel::DeviceArch", /*default*/" mlir::triton::gpu::intel::DeviceA... | nit: Remove "Be conservative in optimization: |
intel-xpu-backend-for-triton | github_2023 | cpp | 623 | intel | whitneywhtsang | @@ -0,0 +1,143 @@
+//===- GPUOpsLowering.h - GPU FuncOp / ReturnOp lowering -------*- C++ -*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | change? |
intel-xpu-backend-for-triton | github_2023 | cpp | 623 | intel | whitneywhtsang | @@ -0,0 +1,184 @@
+//===- GPUToGENPass.cpp - MLIR GPU to GEN lowering passes -----------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | missing something like below?
```
std::unique_ptr<OperationPass<gpu::GPUModuleOp>>
mlir::createLowerGpuOpsToGENXOpsPass(unsigned indexBitwidth) {
return std::make_unique<GPUToGENPass>(indexBitwidth);
}
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 623 | intel | victor-eds | @@ -58,16 +60,16 @@ static LLVM::CallOp createDeviceFunctionCall(
rewriter.setInsertionPointToStart(moduleOp.getBody());
auto func = rewriter.create<LLVM::LLVMFuncOp>(loc, funcName, funcType);
func.setCConv(LLVM::cconv::CConv::SPIR_FUNC);
-
if (convergent)
- func->setAttr("passthrough", rewrite... | ```suggestion
func->setPassthroughAttr(convergentAttr);
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 623 | intel | victor-eds | @@ -58,16 +60,16 @@ static LLVM::CallOp createDeviceFunctionCall(
rewriter.setInsertionPointToStart(moduleOp.getBody());
auto func = rewriter.create<LLVM::LLVMFuncOp>(loc, funcName, funcType);
func.setCConv(LLVM::cconv::CConv::SPIR_FUNC);
-
if (convergent)
- func->setAttr("passthrough", rewrite... | Same as above |
intel-xpu-backend-for-triton | github_2023 | cpp | 623 | intel | victor-eds | @@ -0,0 +1,184 @@
+//===- GPUToGENPass.cpp - MLIR GPU to GEN lowering passes -----------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | Can we just?
```suggestion
using triton::impl::ConvertGPUToGENBase<GPUToGENPass>::ConvertGPUToGENBase;
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 623 | intel | victor-eds | @@ -0,0 +1,184 @@
+//===- GPUToGENPass.cpp - MLIR GPU to GEN lowering passes -----------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | We should have those defined in tablegen to have them as attributes |
intel-xpu-backend-for-triton | github_2023 | cpp | 623 | intel | victor-eds | @@ -0,0 +1,184 @@
+//===- GPUToGENPass.cpp - MLIR GPU to GEN lowering passes -----------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | Do we have a comprehensive list of `gpu` operations we cannot lower? Do we wanna document that here, e.g., in a comment? |
intel-xpu-backend-for-triton | github_2023 | cpp | 623 | intel | victor-eds | @@ -0,0 +1,184 @@
+//===- GPUToGENPass.cpp - MLIR GPU to GEN lowering passes -----------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | Maybe this can be handled in a cleaner way, but I guess we can live with this as is for now. Can we at least put a TODO comment here saying we're missing ops? |
intel-xpu-backend-for-triton | github_2023 | cpp | 623 | intel | victor-eds | @@ -0,0 +1,88 @@
+//===- IndexIntrinsicsOpLowering.h - GPU IndexOps Lowering class *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---... | Need to change? |
intel-xpu-backend-for-triton | github_2023 | cpp | 623 | intel | victor-eds | @@ -0,0 +1,120 @@
+//===- OpToFuncCallLowering.h - GPU ops lowering to custom calls *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | Idem |
intel-xpu-backend-for-triton | github_2023 | others | 623 | intel | whitneywhtsang | @@ -0,0 +1,36 @@
+//===-- Passes.td - GPU to GEN Conversion Passes -----------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---... | ```suggestion
let constructor = "mlir::createLowerGPUToGENPass()";
``` |
intel-xpu-backend-for-triton | github_2023 | others | 628 | intel | whitneywhtsang | @@ -67,3 +67,24 @@ llvm.func @gen.sub_group_shuffle() {
%16 = gen.sub_group_shuffle xor %15, %0 : f64 -> f64
llvm.return
}
+
+llvm.func @gen.fptofp(%a: f32, %b: f16) {
+ // CHECK-LABEL: gen.fptofp
+ // CHECK: %0 = gen.conv.fptofp %arg0 {roundingMode = rte} : f32 to f16
+ // CHECK-NEXT: %1 = gen.conv.fpto... | can we remove roundingMode for one of them for testing. |
intel-xpu-backend-for-triton | github_2023 | cpp | 628 | intel | whitneywhtsang | @@ -382,7 +443,8 @@ void mlir::triton::populateGENToLLVMConversionPatterns(
GENGridDimXLowering, GENGridDimYLowering, GENGridDimZLowering>(
converter);
// clang-format on
- patterns.add<GENBarrierLowering, SubGroupShuffleLowering>(converter);
+ patterns.add<GENBarrierLowering, GENSubGroupShu... | wonder why we don't add all patterns in one `patterns.add` |
intel-xpu-backend-for-triton | github_2023 | others | 628 | intel | victor-eds | @@ -0,0 +1,23 @@
+// RUN: triton-opt -split-input-file -verify-diagnostics %s
+
+llvm.func @triton_gen.fptofp(%a : i32) {
+ // expected-error @+1 {{custom op 'triton_gen.conv.fptofp' invalid kind of type specified}}
+ %0 = triton_gen.conv.fptofp %a {roundingMode = rte} : i32 to i16 | ```suggestion
%0 = triton_gen.fconvert rte %a : i32 to i16
```
I would drop the `conv` prefix, rename the instruction (optional, but I think this follows convention in other dialects like `spirv.FConvert`), and drop the braces as that is usually used for the attribute dictionary. |
intel-xpu-backend-for-triton | github_2023 | others | 628 | intel | victor-eds | @@ -0,0 +1,23 @@
+// RUN: triton-opt -split-input-file -verify-diagnostics %s
+
+llvm.func @triton_gen.fptofp(%a : i32) { | I don't think we need this test as this is testing the MLIR type system itself. Our operation's type is `AnyFloat -> AnyFloat` |
intel-xpu-backend-for-triton | github_2023 | others | 628 | intel | victor-eds | @@ -0,0 +1,23 @@
+// RUN: triton-opt -split-input-file -verify-diagnostics %s
+
+llvm.func @triton_gen.fptofp(%a : i32) {
+ // expected-error @+1 {{custom op 'triton_gen.conv.fptofp' invalid kind of type specified}}
+ %0 = triton_gen.conv.fptofp %a {roundingMode = rte} : i32 to i16
+ llvm.return
+}
+
+// -----
+
+ll... | This asymmetry, asking for a rounding mode depending on the input types is a bit weird to me... We can discuss, but is choosing a default (`rte`?) a valid option? |
intel-xpu-backend-for-triton | github_2023 | cpp | 628 | intel | victor-eds | @@ -127,6 +127,51 @@ static LLVM::CallOp createSubGroupShuffle(ConversionPatternRewriter &rewriter,
{value, mask}, true /*convergent*/);
}
+static LLVM::CallIntrinsicOp createFpToFp(TritonGEN::FpToFpOp op,
+ ConversionPatternRewriter &rewrit... | MLIR offers a mechanism to convert attributes to different dialects. Please, add a TODO here so we remember to replace this switch with that. |
intel-xpu-backend-for-triton | github_2023 | cpp | 628 | intel | victor-eds | @@ -127,6 +127,51 @@ static LLVM::CallOp createSubGroupShuffle(ConversionPatternRewriter &rewriter,
{value, mask}, true /*convergent*/);
}
+static LLVM::CallIntrinsicOp createFpToFp(TritonGEN::FpToFpOp op,
+ ConversionPatternRewriter &rewrit... | ```suggestion
? rewriter.getStringAttr(llvm::Intrinsic::getBaseName(llvm::Intrinsic::experimental_constrained_fptrunc))
: rewriter.getStringAttr(llvm::Intrinsic::getBaseName(llvm::Intrinsic::experimental_constrained_fpext))
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 628 | intel | victor-eds | @@ -127,6 +127,51 @@ static LLVM::CallOp createSubGroupShuffle(ConversionPatternRewriter &rewriter,
{value, mask}, true /*convergent*/);
}
+static LLVM::CallIntrinsicOp createFpToFp(TritonGEN::FpToFpOp op,
+ ConversionPatternRewriter &rewrit... | Adding the intrinsics as operations to the dialect is the way to go IMO. |
intel-xpu-backend-for-triton | github_2023 | others | 632 | intel | leshikus | @@ -102,6 +102,9 @@ jobs:
max-parallel: 2
fail-fast: false
timeout-minutes: 720
+ defaults:
+ run:
+ shell: bash -noprofile --norc -eo pipefail -c "source /home/runner/intel/oneapi/setvars.sh > /dev/null; source {0}" | I like adding `-eo pipefail` on the top level |
intel-xpu-backend-for-triton | github_2023 | cpp | 664 | intel | etiotto | @@ -218,16 +218,20 @@ DpasEncodingAttr::getShapePerCTATileForDotOperands(ArrayRef<int64_t> shape,
SmallVector<unsigned>
DpasEncodingAttr::getSizePerThreadForOperands(unsigned opIdx) const {
if (opIdx == 0) {
- auto shapeA = getShapeA();
- auto subGroupSize = getSubGroupSize();
- auto systolicDepth = getSy... | opsPerChannel == 4 is used for elem. type FP8. What about the case when operands are less than 8 bit precision? In that case opsPerChannel is 8. Do we need to pack them ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 664 | intel | etiotto | @@ -183,12 +183,19 @@ static LLVM::CallOp createGenISADPAS(TritonGEN::MatrixDPASOp op,
IntegerType int32Ty = rewriter.getIntegerType(32);
Value a = op.getA();
- auto aTy = VectorType::get(op.getRc(), int16Ty);
+ auto aOrigTy = cast<VectorType>(a.getType());
+ auto bitWidth = aOrigTy.getNumElements() *
+ ... | ```suggestion
if (aOrigTy != aTy)
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 664 | intel | etiotto | @@ -183,12 +183,19 @@ static LLVM::CallOp createGenISADPAS(TritonGEN::MatrixDPASOp op,
IntegerType int32Ty = rewriter.getIntegerType(32);
Value a = op.getA();
- auto aTy = VectorType::get(op.getRc(), int16Ty);
+ auto aOrigTy = cast<VectorType>(a.getType());
+ auto bitWidth = aOrigTy.getNumElements() * | auto -> unsigned |
intel-xpu-backend-for-triton | github_2023 | cpp | 664 | intel | etiotto | @@ -183,12 +183,19 @@ static LLVM::CallOp createGenISADPAS(TritonGEN::MatrixDPASOp op,
IntegerType int32Ty = rewriter.getIntegerType(32);
Value a = op.getA();
- auto aTy = VectorType::get(op.getRc(), int16Ty);
+ auto aOrigTy = cast<VectorType>(a.getType());
+ auto bitWidth = aOrigTy.getNumElements() *
+ ... | ```suggestion
if (bOrigTy != bTy)
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 664 | intel | etiotto | @@ -86,14 +86,19 @@ DpasMatmulLoader<opIdx>::computeLdsMatOffs(Value warpId, Value laneId,
unsigned threadsPerWarp = getThreadsPerWarp();
Value laneRowIndex, laneColIndex;
- unsigned repRowsPerInst, rowsPerWarp;
+ unsigned repRowsPerInst, rowsPerWarp, repOpsPerRow;
switch (opIdx) {
case 0: {
- rowsPe... | When opsPerChannel is 8 should we pack the operands ? |
intel-xpu-backend-for-triton | github_2023 | others | 663 | intel | etiotto | @@ -1,5 +1,5 @@
-add_library(TritonGenISAIntrinsics STATIC IMPORTED)
-set_target_properties(TritonGenISAIntrinsics
+add_library(GenISAIntrinsics STATIC IMPORTED GLOBAL) | Why the name change? We want to ensure the library Triton uses is the one within the TritonGen dialect. |
intel-xpu-backend-for-triton | github_2023 | cpp | 355 | intel | etiotto | @@ -448,5 +448,84 @@ Value addStringToModule(Location loc, ConversionPatternRewriter &rewriter,
return stringStart;
}
+static LLVM::LLVMFuncOp
+getSpirvPrintfDeclaration(ConversionPatternRewriter &rewriter) {
+ auto moduleOp =
+ rewriter.getBlock()->getParent()->getParentOfType<ModuleOp>();
+ StringRef fun... | We have this function `getSpirvPrintfDeclaration` here https://github.com/intel/intel-xpu-backend-for-triton/blob/64a4e507df38840e2edfeac85ad34f18299801d2/lib/Conversion/TritonGPUToLLVM/TritonGPUToLLVM.cpp#L315
It is currently in that file because `getVprintfDeclaration` is already in `TritonGPUToLLVM.cpp` (that one... |
intel-xpu-backend-for-triton | github_2023 | cpp | 355 | intel | etiotto | @@ -448,5 +448,84 @@ Value addStringToModule(Location loc, ConversionPatternRewriter &rewriter,
return stringStart;
}
+static LLVM::LLVMFuncOp
+getSpirvPrintfDeclaration(ConversionPatternRewriter &rewriter) {
+ auto moduleOp =
+ rewriter.getBlock()->getParent()->getParentOfType<ModuleOp>();
+ StringRef fun... | This function is already in https://github.com/intel/intel-xpu-backend-for-triton/blob/64a4e507df38840e2edfeac85ad34f18299801d2/lib/Conversion/TritonGPUToLLVM/TritonGPUToLLVM.cpp#L367
Having 2 versions is not necessary (And duplication of code creates maintenance problems) so we should have just one copy. |
intel-xpu-backend-for-triton | github_2023 | cpp | 355 | intel | etiotto | @@ -448,5 +448,84 @@ Value addStringToModule(Location loc, ConversionPatternRewriter &rewriter,
return stringStart;
}
+static LLVM::LLVMFuncOp
+getSpirvPrintfDeclaration(ConversionPatternRewriter &rewriter) {
+ auto moduleOp =
+ rewriter.getBlock()->getParent()->getParentOfType<ModuleOp>();
+ StringRef fun... | This is essentially a subset of https://github.com/intel/intel-xpu-backend-for-triton/blob/64a4e507df38840e2edfeac85ad34f18299801d2/lib/Conversion/TritonGPUToLLVM/TritonGPUToLLVM.cpp#L405
To avoid code duplication we could create a function here and use it from within `llPrintf` when target is GENX. WDYT ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 355 | intel | etiotto | @@ -448,5 +448,84 @@ Value addStringToModule(Location loc, ConversionPatternRewriter &rewriter,
return stringStart;
}
+static LLVM::LLVMFuncOp
+getSpirvPrintfDeclaration(ConversionPatternRewriter &rewriter) {
+ auto moduleOp =
+ rewriter.getBlock()->getParent()->getParentOfType<ModuleOp>();
+ StringRef fun... | This function exist in https://github.com/intel/intel-xpu-backend-for-triton/blob/64a4e507df38840e2edfeac85ad34f18299801d2/lib/Conversion/TritonGPUToLLVM/TritonGPUToLLVM.cpp#L392
|
intel-xpu-backend-for-triton | github_2023 | cpp | 355 | intel | whitneywhtsang | @@ -386,6 +386,62 @@ Value addStringToModule(Location loc, ConversionPatternRewriter &rewriter,
return stringStart;
}
+// declare __spirv_ocl_printf(i8*, ...) as external function
+LLVM::LLVMFuncOp
+getSpirvPrintfDeclaration(ConversionPatternRewriter &rewriter) {
+ auto moduleOp = rewriter.getBlock()->getParent(... | remove the comment here, as it is already added in the header file.
```suggestion
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 355 | intel | whitneywhtsang | @@ -37,7 +37,8 @@ struct PrintOpConversion
llvm::raw_string_ostream os(formatStr);
os << "pid (" << getFormatSubstr(pid[0]) << ", "
<< getFormatSubstr(pid[1]) << ", " << getFormatSubstr(pid[2]) << ")%s";
- llPrintf(formatStr, {pid[0], pid[1], pid[2], prefixStr}, rewriter);
+ mlir::LLVM... | can we use the defined `kernel_printf` in this file? |
intel-xpu-backend-for-triton | github_2023 | cpp | 355 | intel | etiotto | @@ -211,121 +213,6 @@ struct PrintOpConversion
assert(false && "not supported type");
return "";
}
- | Note: some of these functions are moved to Utility.cpp. |
intel-xpu-backend-for-triton | github_2023 | cpp | 355 | intel | etiotto | @@ -142,6 +142,10 @@ using namespace mlir::triton;
#define i32_arr_attr(...) rewriter.getI32ArrayAttr({__VA_ARGS__})
#define i64_arr_attr(...) rewriter.getI64ArrayAttr({__VA_ARGS__})
+// Kernel printf
+#define kernel_printf(fmt, ...) \
+ LLVM::utils::llPrintf(rewriter... | This macro can be used to invoke either of the `llPrintf` functions below, depending on the type of `fmt`. However when `fmt` is a StringRef the return value is ignored, which is an issue. For this reason I think using the `llPrintf` functions below directly is better. Can we remove this macro? |
intel-xpu-backend-for-triton | github_2023 | others | 676 | intel | leshikus | @@ -84,7 +84,7 @@ if [ ! -d "$PACKAGES_DIR" ]; then
mkdir $PACKAGES_DIR
fi
if [ $BASE != $HOME ]; then
- ln -s $PACKAGES_DIR $HOME/packages
+ ln -sfT $PACKAGES_DIR $HOME/packages | I used to use `ln -n` instead of `ln -T` yet it seems from docs to be the same. |
intel-xpu-backend-for-triton | github_2023 | others | 657 | intel | pbchekin | @@ -35,7 +37,7 @@ for arg in "$@"; do
done
set +o xtrace
-if [ -z "$BASE" ]; then
+if [ -z ${BASE:+x} ]; then | What about using `-v` check? It is shorter and, in some sense, more readable:
```suggestion
if [ ! -v BASE ]; then
```
IMHO, both forms are not good in terms of readability and both are advanced bash techniques, but `-v` may be more "natural". Alternatively, we can add `set -e` to the script, but avoid setting ... |
intel-xpu-backend-for-triton | github_2023 | others | 649 | intel | sommerlukas | @@ -114,3 +114,35 @@ llvm.func @triton_gen.sub_group_shuffle() {
%16 = triton_gen.sub_group_shuffle xor %15, %0 : f64 -> f64
llvm.return
}
+
+// -----
+
+llvm.func @triton_gen.2Dblockload(%ptr : !llvm.ptr, %base_width : i32, %base_height : i32, %base_pitch : i32, %x : i32, %y : i32) {
+ // CHECK: [[PTR:%.*... | What are `%arg1` etc. in this context? Should we also add `CHECK`-lines for them? |
intel-xpu-backend-for-triton | github_2023 | cpp | 649 | intel | whitneywhtsang | @@ -45,6 +45,20 @@ using namespace mlir::triton;
// Helper Functions
//===----------------------------------------------------------------------===//
+static LLVM::LLVMFuncOp
+getOrCreateFunction(StringRef funcName, Type retType, ArrayRef<Type> argTypes, | Can we use `LLVM::lookupOrCreateFn`? |
intel-xpu-backend-for-triton | github_2023 | others | 651 | intel | pbchekin | @@ -1,5 +1,5 @@
#!/usr/bin/env bash
-
+set -vx | Nit: not sure if this change is user friendly. Instead of modifying the script, which is actively used by humans, it is possible just to modify the workflow to archive the same result, for example:
```
bash -vx ./scripts/compile-triton.sh
```
But I am OK if @whitneywhtsang OK with it. |
intel-xpu-backend-for-triton | github_2023 | others | 651 | intel | pbchekin | @@ -28,7 +29,7 @@ jobs:
- "3.10"
defaults:
run:
- shell: bash -noprofile --norc -eo pipefail -c "source /home/runner/intel/oneapi/setvars.sh > /dev/null; source /home/runner/miniconda3/etc/profile.d/conda.sh; source {0}"
+ shell: bash -noprofile --norc -eo pipefail -c "source /home/... | Why replacing `;` with `&&` if we have `set -e` anyway? You said the number of symbols to type is important for you, so why typing more? |
intel-xpu-backend-for-triton | github_2023 | others | 651 | intel | pbchekin | @@ -106,76 +101,11 @@ jobs:
- name: Build Triton
run: |
- export DEBUG=1
- cd python
- conda activate triton
- pip install --no-build-isolation '.[build,tests,tutorials]'
+ conda run -n triton scripts/compile-triton.sh --triton
- name: Run core tes... | When you restore conda environment from cache, it contains pytorch and ipex and the test script skips building them from sources. This also explains why ../pytorch does not exist in "Run E2E test" step. |
intel-xpu-backend-for-triton | github_2023 | others | 648 | intel | pbchekin | @@ -63,7 +63,7 @@ jobs:
# Increase this value to reset cache
CACHE_NUMBER: 3
with:
- path: $HOME/packages
+ path: ${{ github.workspace }}/../packages | The directory `packages` needs to be in `$HOME` according to https://github.com/intel/intel-xpu-backend-for-triton/blob/llvm-target/python/setup.py#L304. |
intel-xpu-backend-for-triton | github_2023 | others | 648 | intel | pbchekin | @@ -85,7 +76,7 @@ build_pytorch() {
echo "****** Building $PYTORCH_PROJ ******"
cd $PYTORCH_PROJ
if [ ! -d "$PYTORCH_PROJ/dist" ]; then
- PYTORCH_COMMIT_ID="$(<.github/pins/pytorch.txt)"
+ PYTORCH_COMMIT_ID="$(<.github/pins/pytorch.txt)" || true | Just curious, why do you need `|| true` here? |
intel-xpu-backend-for-triton | github_2023 | others | 648 | intel | pbchekin | @@ -67,24 +59,13 @@ if [ "$VENV" = true ]; then
python3 -m venv .venv --prompt triton
source .venv/bin/activate
pip install ninja cmake wheel
-elif [ -n "$VIRTUAL_ENV" ]; then
+elif [ ! -z ${VIRTUAL_ENV+x} ]
+then | I am trying to understand what you are trying to achieve here. First, `then` moved to a new line, which is not consistent with `if .. then` in line 52. Second, if you want to check if `VIRTUAL_ENV` is set then you can use
```
elif [ -v VIRTUAL_ENV ]; then
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 642 | intel | whitneywhtsang | @@ -178,6 +183,58 @@ static LLVM::CallIntrinsicOp createFpToFp(TritonGEN::FpToFpOp op,
op.getArg());
}
+static LLVM::CallOp createGenISADPAS(TritonGEN::MatrixDPASOp op,
+ ConversionPatternRewriter &rewriter) {
+ auto moduleOp = rew... | ```suggestion
return rewriter.create<LLVM::CallOp>(loc, funcOp, args);
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 642 | intel | victor-eds | @@ -71,71 +68,52 @@ LogicalResult TritonGEN::MatrixDPASOp::verify() {
return this->emitOpError(
"3rd operand (B) bit-size should be systolic depth (8) times 32");
- return TypeSwitch<Type, LogicalResult>(AElemTy)
- .Case<Float32Type>([&](auto ty) -> LogicalResult {
- if (precision != Triton... | Isn't this `llvm_unreachable`? |
intel-xpu-backend-for-triton | github_2023 | cpp | 642 | intel | victor-eds | @@ -42,6 +44,20 @@ using namespace mlir::triton;
// Helper Functions
//===----------------------------------------------------------------------===//
+static LLVM::LLVMFuncOp
+getOrCreateFunction(StringRef funcName, Type retType, ArrayRef<Type> argTypes,
+ ModuleOp moduleOp, Location loc,
+ ... | Can we use [this](https://github.com/llvm/llvm-project/blob/0f501c30b9601627c236f9abca8a3befba5dc161/mlir/include/mlir/Dialect/LLVMIR/FunctionCallUtils.h#L65) instead? |
intel-xpu-backend-for-triton | github_2023 | cpp | 642 | intel | victor-eds | @@ -178,6 +183,56 @@ static LLVM::CallIntrinsicOp createFpToFp(TritonGEN::FpToFpOp op,
op.getArg());
}
+static LLVM::CallOp createGenISADPAS(TritonGEN::MatrixDPASOp op,
+ ConversionPatternRewriter &rewriter) {
+ auto moduleOp = rew... | Can we use [`llvm.call_intrinsic`](https://mlir.llvm.org/docs/Dialects/LLVM/#llvmcall_intrinsic-llvmcallintrinsicop) instead? Also, can we have a TODO to add that to the `llvm` dialect as a first class operation? |
intel-xpu-backend-for-triton | github_2023 | python | 634 | intel | etiotto | @@ -25,8 +25,9 @@ def test_op(Z, H, N_CTX, D_HEAD, dtype, causal, seq_par, device):
capability = torch.cuda.get_device_capability()
if capability[0] < 8:
pytest.skip("Flash attention only supported for compute capability >= 80")
- if dtype == torch.bfloat16 and os.environ.get("TRIT... | We should change the skip to an xfail (expected failure) so that we can compute the real pass rate accurately. |
intel-xpu-backend-for-triton | github_2023 | others | 634 | intel | whitneywhtsang | @@ -168,14 +168,7 @@ jobs:
run: |
cd python/test/unit
python3 -m pytest --junitxml=~/reports/interpreter_core.xml -vvv -n 4 -m interpreter language/test_core.py --device cpu
-
- # TODO: merge the two interpreter tests with env TRITON_INTERPRET=1 and device cpu
- - name: Run inte... | ```suggestion
python3 -m pytest --junitxml=~/reports/interpreter_flash_attention.xml -n 8 -m interpreter -vvv -s operators/test_flash_attention.py::test_op --device cpu
``` |
intel-xpu-backend-for-triton | github_2023 | others | 611 | intel | whitneywhtsang | @@ -51,8 +51,6 @@ done
if [ "$BUILD_PYTORCH" = false ] && [ "$BUILD_IPEX" = false ] \
&& [ "$BUILD_LLVM" = false ] && [ "$BUILD_TRITON" = false ]; then
- BUILD_PYTORCH=true | Can we check if torch and ipex are installed? |
intel-xpu-backend-for-triton | github_2023 | others | 619 | intel | leshikus | @@ -0,0 +1,41 @@
+name: get-commit-id
+description: Identify the latest commit id in the specific branch
+inputs:
+ repository:
+ description: Repository name with owner
+ branch:
+ description: Branch name
+ variable:
+ description: Environment variable that will contain commit id
+ default: ""
+ retri... | This is generally a good idea to add some sleep before retry happens. If the problem is due to some load issues, no need to add more stress load. |
intel-xpu-backend-for-triton | github_2023 | others | 616 | intel | pbchekin | @@ -51,8 +51,16 @@ done
if [ "$BUILD_PYTORCH" = false ] && [ "$BUILD_IPEX" = false ] \
&& [ "$BUILD_LLVM" = false ] && [ "$BUILD_TRITON" = false ]; then
- BUILD_PYTORCH=true
- BUILD_IPEX=true
+ # Avoid overriding the user's existing PyTorch by default.
+ pip show torch &>/dev/null
+ if [ $? != 0 ]; then | ```suggestion
if ! pip show torch &>/dev/null; then
``` |
intel-xpu-backend-for-triton | github_2023 | others | 616 | intel | pbchekin | @@ -51,8 +51,16 @@ done
if [ "$BUILD_PYTORCH" = false ] && [ "$BUILD_IPEX" = false ] \
&& [ "$BUILD_LLVM" = false ] && [ "$BUILD_TRITON" = false ]; then
- BUILD_PYTORCH=true
- BUILD_IPEX=true
+ # Avoid overriding the user's existing PyTorch by default.
+ pip show torch &>/dev/null
+ if [ $? != 0 ]; then
+ ... | ```suggestion
if ! pip show intel_extension_for_pytorch &>/dev/null; then
``` |
intel-xpu-backend-for-triton | github_2023 | others | 616 | intel | etiotto | @@ -0,0 +1,133 @@
+#!/usr/bin/env bash
+
+# Select what to build.
+BUILD_PYTORCH=false
+BUILD_IPEX=false
+CLEAN=false
+VENV=false
+for arg in "$@"; do
+ case $arg in
+ --pytorch)
+ BUILD_PYTORCH=true
+ shift
+ ;;
+ --ipex)
+ BUILD_IPEX=true
+ shift
+ ;;
+ --clean)
+ CLEAN=tr... | `/compile-triton.sh` -> `/compile-pytorch-ipex.sh` |
intel-xpu-backend-for-triton | github_2023 | others | 616 | intel | etiotto | @@ -0,0 +1,133 @@
+#!/usr/bin/env bash
+
+# Select what to build.
+BUILD_PYTORCH=false
+BUILD_IPEX=false
+CLEAN=false
+VENV=false
+for arg in "$@"; do
+ case $arg in
+ --pytorch)
+ BUILD_PYTORCH=true
+ shift
+ ;;
+ --ipex)
+ BUILD_IPEX=true
+ shift
+ ;;
+ --clean)
+ CLEAN=tr... | Wait. If the user had a version of IPEX/pytorch installed already this would cause it to be removed. I suggest removing the --clean option. |
intel-xpu-backend-for-triton | github_2023 | others | 616 | intel | pbchekin | @@ -0,0 +1,133 @@
+#!/usr/bin/env bash
+
+# Select what to build.
+BUILD_PYTORCH=false
+BUILD_IPEX=false
+CLEAN=false
+VENV=false
+for arg in "$@"; do
+ case $arg in
+ --pytorch)
+ BUILD_PYTORCH=true
+ shift
+ ;;
+ --ipex)
+ BUILD_IPEX=true
+ shift
+ ;;
+ --clean)
+ CLEAN=tr... | Not sure if this script needs to handle venv. If a normal use case is calling from `test-triton.sh`, then venv is already created and activated. |
intel-xpu-backend-for-triton | github_2023 | others | 616 | intel | etiotto | @@ -53,10 +53,11 @@ fi
export TRITON_PROJ=$BASE/intel-xpu-backend-for-triton
export TRITON_PROJ_BUILD=$TRITON_PROJ/python/build
+export SCRIPTS_DIR=$(dirname "$0")
python3 -m pip install lit
python3 -m pip install pytest pytest-xdist pytest-rerunfailures
-python3 -m pip install torch==2.1.0a0+cxx11.abi intel_ex... | I have a bit of a concern. We used to know exactly what wheel (source level) we used for pytorch and IPEX. Now that those components are built from source we no longer know the commit levels used by a test run.
What happens if we build those components and tests start failing ? How does a developer easily determine... |
intel-xpu-backend-for-triton | github_2023 | others | 616 | intel | Stonepia | @@ -0,0 +1,121 @@
+#!/usr/bin/env bash
+
+# Select what to build.
+BUILD_PYTORCH=false
+BUILD_IPEX=false
+CLEAN=false
+VENV=false
+for arg in "$@"; do
+ case $arg in
+ --pytorch)
+ BUILD_PYTORCH=true
+ shift
+ ;;
+ --ipex)
+ BUILD_IPEX=true
+ shift
+ ;;
+ --clean)
+ CLEAN=tr... | There are several dependencies need to be installed individually, you could refer to https://github.com/pytorch/pytorch?tab=readme-ov-file#install-dependencies for detail.
```Bash
conda install cmake ninja
pip install -r requirements.txt
conda install intel::mkl-static intel::mkl-include
``` |
intel-xpu-backend-for-triton | github_2023 | others | 616 | intel | Stonepia | @@ -0,0 +1,121 @@
+#!/usr/bin/env bash
+
+# Select what to build.
+BUILD_PYTORCH=false
+BUILD_IPEX=false
+CLEAN=false
+VENV=false
+for arg in "$@"; do
+ case $arg in
+ --pytorch)
+ BUILD_PYTORCH=true
+ shift
+ ;;
+ --ipex)
+ BUILD_IPEX=true
+ shift
+ ;;
+ --clean)
+ CLEAN=tr... | One additional thought is that, I didn't find the place you source the oneAPI toolkit, so I assume you will source it globally. However, It is recommended to ONLY source oneAPI during the build IPEX (DO NOT source it when building pytorch / triton).
You could find a reference at https://github.com/Stonepia/Tools/bl... |
intel-xpu-backend-for-triton | github_2023 | cpp | 609 | intel | etiotto | @@ -0,0 +1,15 @@
+#ifndef TRITON_DIALECT_TRITON_INTEL_GPU_TRANSFORMS_PASSES_H_ | Please add copyrights (LLVM one) to all new files. |
intel-xpu-backend-for-triton | github_2023 | others | 609 | intel | etiotto | @@ -0,0 +1,20 @@
+#ifndef TRITON_INTEL_GPU_PASSES
+#define TRITON_INTEL_GPU_PASSES
+
+include "mlir/Pass/PassBase.td"
+
+def TritonIntelGPUAccelerateMatmul : Pass<"tritonintelgpu-accelerate-matmul", "mlir::ModuleOp"> {
+ let summary = "intel accelerate matmul";
+
+ let description = [{
+ Optimize the input/output ... | ... of the `tl.dot` operation to make them compatible with the Intel DPAS instruction requirements. |
intel-xpu-backend-for-triton | github_2023 | others | 609 | intel | etiotto | @@ -0,0 +1,20 @@
+#ifndef TRITON_INTEL_GPU_PASSES
+#define TRITON_INTEL_GPU_PASSES
+
+include "mlir/Pass/PassBase.td"
+
+def TritonIntelGPUAccelerateMatmul : Pass<"tritonintelgpu-accelerate-matmul", "mlir::ModuleOp"> {
+ let summary = "intel accelerate matmul";
+
+ let description = [{
+ Optimize the input/output ... | #endif // TRITON_INTEL_GPU_PASSES
|
intel-xpu-backend-for-triton | github_2023 | cpp | 609 | intel | etiotto | @@ -0,0 +1,120 @@
+#include "mlir/IR/TypeUtilities.h" | Add copyright to all the "intel" files that do not have one pls. |
intel-xpu-backend-for-triton | github_2023 | cpp | 609 | intel | etiotto | @@ -0,0 +1,120 @@
+#include "mlir/IR/TypeUtilities.h"
+#include "mlir/Support/LogicalResult.h"
+#include "mlir/Transforms/GreedyPatternRewriteDriver.h"
+#include "triton/Analysis/Utility.h"
+#include "triton/Dialect/TritonGPU/IR/Dialect.h"
+#include "triton/Dialect/TritonGPU/Transforms/Passes.h"
+#include "triton/Diale... | ttig -> ttgi |
intel-xpu-backend-for-triton | github_2023 | cpp | 609 | intel | etiotto | @@ -0,0 +1,23 @@
+//===- Passes.h - Intel Pass Construction and Registration ------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---... | add newline before #endif |
intel-xpu-backend-for-triton | github_2023 | others | 609 | intel | etiotto | @@ -0,0 +1,29 @@
+//===-- Passes.td - Triton Intel pass definition file ------*- tablegen -*-===// | Triton Intel -> TritonIntelGPU |
intel-xpu-backend-for-triton | github_2023 | others | 609 | intel | etiotto | @@ -0,0 +1,29 @@
+//===-- Passes.td - Triton Intel pass definition file ------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---... | line exceeded 80 characters |
intel-xpu-backend-for-triton | github_2023 | python | 600 | intel | pbchekin | @@ -7,9 +7,14 @@
from triton.backends.driver import DriverBase
dirname = os.getenv("ZE_PATH", default="/usr/local")
-include_dir = [os.path.join(dirname, "include/level_zero")]
+oneapi_dirname = os.getenv("ONEAPI_ROOT", default="/opt/intel/oneapi")
+include_dir = [
+ os.path.join(dirname, "include"),
+ os.pat... | Let's try to avoid hard-coding oneAPI version. |
intel-xpu-backend-for-triton | github_2023 | python | 600 | intel | pbchekin | @@ -7,9 +7,14 @@
from triton.backends.driver import DriverBase
dirname = os.getenv("ZE_PATH", default="/usr/local")
-include_dir = [os.path.join(dirname, "include/level_zero")]
+oneapi_dirname = os.getenv("ONEAPI_ROOT", default="/opt/intel/oneapi") | Nitpick: looks like `oneapi_root` is more reasonable name for a local varable?
```suggestion
oneapi_root = os.getenv("ONEAPI_ROOT", default="/opt/intel/oneapi")
``` |
intel-xpu-backend-for-triton | github_2023 | others | 600 | intel | pbchekin | @@ -106,9 +112,76 @@ jobs:
path: ${{ steps.conda-cache.outputs.path }}
dest: ${{ steps.conda-cache.outputs.dest }}
+ - name: Run core tests
+ run: |
+ conda run --no-capture-output -n triton pip install pytest pytest-xdist
+ cd python/test/unit
+ conda run ... | If possible, let's find a way to activate conda environment in the beginning of the step. Having `conda run ...` for each line is overkill. |
intel-xpu-backend-for-triton | github_2023 | others | 600 | intel | pbchekin | @@ -75,6 +75,12 @@ jobs:
run: |
conda create -n triton --override-channels -c conda-forge python=${{ matrix.python }}.*
conda env update -f scripts/triton.yml
+ find /home/runner/intel/oneapi/ \( -name '*.so' -or -name '*.so.*' \) -exec cp -n {} $HOME/miniconda3/envs/triton/lib \... | That's terrible, but acceptable as a temporary step to a pure conda environment. |
intel-xpu-backend-for-triton | github_2023 | others | 600 | intel | pbchekin | @@ -75,6 +75,12 @@ jobs:
run: |
conda create -n triton --override-channels -c conda-forge python=${{ matrix.python }}.*
conda env update -f scripts/triton.yml
+ find /home/runner/intel/oneapi/ \( -name '*.so' -or -name '*.so.*' \) -exec cp -n {} $HOME/miniconda3/envs/triton/lib \... | Temporary it is OK to install torch and ipex from these wheels, but the main CI workflow currently is currently building both from sources. Eventually this pipeline needs to use the same code by making actions `setup-pytorch` and `setup-ipex` more generic to support coda, or by implementing a custom actions such as, fo... |
intel-xpu-backend-for-triton | github_2023 | others | 600 | intel | pbchekin | @@ -96,8 +103,68 @@ jobs:
- name: Build Triton
run: |
cd python
- conda run --no-capture-output -n triton pip install wheel
- conda run --no-capture-output -n triton pip install --no-build-isolation '.[tests]'
+ conda activate triton
+ pip install --no-buil... | Please rebase your branch and make the same change as in `build_and_test`:
```suggestion
python3 07-extern-functions.py
``` |
intel-xpu-backend-for-triton | github_2023 | others | 600 | intel | whitneywhtsang | @@ -96,8 +103,68 @@ jobs:
- name: Build Triton
run: |
cd python
- conda run --no-capture-output -n triton pip install wheel
- conda run --no-capture-output -n triton pip install --no-build-isolation '.[tests]'
+ conda activate triton
+ pip install --no-buil... | This session needs to be rebased too, please compare with build_and_test.yml. |
intel-xpu-backend-for-triton | github_2023 | others | 333 | intel | etiotto | @@ -1 +1,5 @@
-add_triton_plugin(TritonXPU ${CMAKE_CURRENT_SOURCE_DIR}/triton_xpu.cc)
\ No newline at end of file
+include_directories(${CMAKE_CURRENT_SOURCE_DIR}/include)
+include_directories(${CMAKE_CURRENT_BINARY_DIR}/include)
+add_subdirectory(include)
+add_subdirectory(lib)
+add_triton_plugin(TritonXPU ${CMAKE_CUR... | add newline |
intel-xpu-backend-for-triton | github_2023 | others | 593 | intel | pbchekin | @@ -0,0 +1,50 @@
+ARG INSTALLER_IMAGE=docker-registry.docker-registry.svc.cluster.local:5000/runner-conda:2024.0.1
+
+FROM $INSTALLER_IMAGE as installer
+
+FROM summerwind/actions-runner:ubuntu-22.04
+
+USER root
+
+RUN set -ex; \
+ export DEBIAN_FRONTEND=noninteractive; \
+ echo 'deb [arch=amd64 signed-by=/usr/s... | This needs to be moved to conda in the next iteration: build-essential, zlib1g-dev, cmake, ninja-build, wget, pkg-config. |
intel-xpu-backend-for-triton | github_2023 | others | 593 | intel | pbchekin | @@ -0,0 +1,193 @@
+name: Conda build and test
+
+on:
+ workflow_dispatch:
+ schedule:
+ - cron: "5 2 * * *"
+
+permissions: read-all
+
+env:
+ BASE: /home/runner
+ LLVM_SYSPATH: /home/runner/packages/llvm
+ BACKEND: XPU
+ TRITON_DISABLE_LINE_INFO: 1
+
+jobs:
+
+ integration-tests:
+ name: Integration tests... | Both Python 3.9 and 3.10 need to be enabled in the next iteration. |
intel-xpu-backend-for-triton | github_2023 | others | 593 | intel | pbchekin | @@ -0,0 +1,193 @@
+name: Conda build and test
+
+on:
+ workflow_dispatch:
+ schedule:
+ - cron: "5 2 * * *"
+
+permissions: read-all
+
+env:
+ BASE: /home/runner
+ LLVM_SYSPATH: /home/runner/packages/llvm
+ BACKEND: XPU
+ TRITON_DISABLE_LINE_INFO: 1
+
+jobs:
+
+ integration-tests:
+ name: Integration tests... | Nit: we don't need to commented out steps here, just remove (next PR is OK). |
intel-xpu-backend-for-triton | github_2023 | others | 593 | intel | pbchekin | @@ -1,13 +1,21 @@
-name: Docker image runner-base
+name: Build self-hosted runner image | Not sure if a workflow with parameters is better than two simple workflows for each image. |
intel-xpu-backend-for-triton | github_2023 | others | 587 | intel | pbchekin | @@ -160,12 +160,12 @@ jobs:
rm -rf ~/.triton
- name: Run interpreter tests
- env:
+ # env:
# TRITON_INTERPRET: "1" | Why `TRITON_INTERPRET` is not set while in the upstream workflow it is set? Without setting we are running the subset (tests marked with `interpreter`) that already executed in the "Run core tests" step. |
intel-xpu-backend-for-triton | github_2023 | others | 587 | intel | etiotto | @@ -116,13 +116,23 @@ run_core_tests() {
echo "FAILED: return code $?" ; exit $?
fi
- TRITON_DISABLE_LINE_INFO=1 python3 -m pytest -n 8 --verbose --device xpu operators/
+ # run test_line_info.py separately with TRITON_DISABLE_LINE_INFO=0
+ TRITON_DISABLE_LINE_INFO=0 python3 -m pytest --verbose --device xp... | @pbchekin when you parse the test results are we able to list the test results for the language tests twice, one for the case where the language tests are run with device "xpu" and the other with device "cpu". That way we can track the pass rate of these 2 categories. |
intel-xpu-backend-for-triton | github_2023 | cpp | 579 | intel | whitneywhtsang | @@ -0,0 +1,34 @@
+//===- GENToLLVMPass.h - GEN to LLVM dialect conversion ---------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---... | ```suggestion
namespace triton {
#define GEN_PASS_DECL
#include "intel/include/GENToLLVM/Passes.h.inc"
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 574 | intel | etiotto | @@ -263,7 +263,8 @@ struct LoadOpConversion
rewriter, loc, pred, SmallVector<Value, 1>{other_}, [&]() {
Value addrElem =
bitcast(ptrElems[vecStart], ptr_ty(ctx, 1 /*global*/));
- Value ret = load(retTy, addrElem);
+ uint32_t alignment = nWords * w... | If we have an array the alignment of the array should be equal to the alignment of its element type. Does this work for that case ? |
intel-xpu-backend-for-triton | github_2023 | others | 576 | intel | whitneywhtsang | @@ -0,0 +1,75 @@
+# Clones IPEX (or loads from cache) to directory "intel-extension-for-pytorch".
+# Uses the existing Python.
+# Sets the following environment variables:
+# * IPEX_REPO
+# * IPEX_BRANCH
+# * IPEX_COMMIT_ID
+name: setup-ipex
+description: Build and install IPEX wheels
+inputs:
+ oneapi:
+ descripti... | IIRC, building IPEX requires Torch to be installed, should we ensure it is the case? |
intel-xpu-backend-for-triton | github_2023 | cpp | 573 | intel | chengjunlu | @@ -180,7 +180,7 @@ struct ConvertLayoutOpConversion
SmallVector<Value> mmaColIdx(2);
SmallVector<Value> mmaRowIdx(2);
Value threadId = getThreadId(rewriter, loc);
- Value warpSize = i32_val(32);
+ Value warpSize = getModuleWarpSize(rewriter, loc); | Maybe we can skip the change for the NV logic to reduce the merge effort. |
intel-xpu-backend-for-triton | github_2023 | cpp | 573 | intel | chengjunlu | @@ -778,7 +778,7 @@ static SmallVector<Value> emitBaseIndexWithinCTAForMmaLayoutV2V3(
auto shapePerCTA = getShapePerCTA(mmaLayout, shape);
Value threadId = getThreadId(rewriter, loc);
- Value warpSize = i32_val(32);
+ Value warpSize = getModuleWarpSize(rewriter, loc); | This is for NV MMA too. |
intel-xpu-backend-for-triton | github_2023 | others | 565 | intel | sommerlukas | @@ -138,7 +150,8 @@ build_llvm() {
-DCMAKE_EXPORT_COMPILE_COMMANDS=ON \
-DCMAKE_INSTALL_PREFIX=$PACKAGES_DIR/llvm \
-DCMAKE_C_COMPILER=$C_COMPILER \
- -DCMAKE_CXX_COMPILER=$CXX_COMPILER ..
+ -DCMAKE_CXX_COMPILER=$CXX_COMPILER \
+ $ADDITIONAL_FLAGS | Would this immediately override the `CMAKE_CXX_COMPILER` set in the previous line? |
intel-xpu-backend-for-triton | github_2023 | cpp | 465 | intel | ienkovich | @@ -28,6 +43,133 @@ class DotOpDPASConversionHelper {
: dpasLayout(dpasLayout), rewriter(rewriter),
typeConverter(typeConverter), loc(loc), ctx(dpasLayout.getContext()) {}
+ static DPASEngineType getMmaType(triton::DotOp op) {
+ Value A = op.getA();
+ Value B = op.getB();
+ auto aTy = A.getT... | `S32_S32_S8_S8` here? |
intel-xpu-backend-for-triton | github_2023 | cpp | 465 | intel | ienkovich | @@ -28,6 +43,133 @@ class DotOpDPASConversionHelper {
: dpasLayout(dpasLayout), rewriter(rewriter),
typeConverter(typeConverter), loc(loc), ctx(dpasLayout.getContext()) {}
+ static DPASEngineType getMmaType(triton::DotOp op) {
+ Value A = op.getA();
+ Value B = op.getB();
+ auto aTy = A.getT... | What about `BF16_BF16_BF16_BF16`? |
intel-xpu-backend-for-triton | github_2023 | cpp | 465 | intel | etiotto | @@ -77,11 +77,10 @@ struct DotOpConversion : public ConvertTritonGPUOpToLLVMPattern<triton::DotOp> {
"Unsupported MMA kind found when converting DotOp to LLVM.");
}
- DpasEncodingAttr dpasLayout = D.getType()
- .cast<RankedTensorType>()
- ... | `supportDPAS(op)` was removed, what is the reason ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 465 | intel | etiotto | @@ -279,11 +280,10 @@ Value loadOperand(ConversionPatternRewriter &rewriter, Location loc,
auto dpasLayout = encoding.getParent().cast<DpasEncodingAttr>();
const SmallVector<unsigned> warpsPerCTA = dpasLayout.getWarpsPerCTA();
+ auto order = triton::gpu::getOrder(dpasLayout);
auto tensorTy = tensor.getTyp... | Would it be better to move line 283 here (for easier merge conflict resolution) ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 465 | intel | etiotto | @@ -28,6 +43,133 @@ class DotOpDPASConversionHelper {
: dpasLayout(dpasLayout), rewriter(rewriter),
typeConverter(typeConverter), loc(loc), ctx(dpasLayout.getContext()) {}
+ static DPASEngineType getMmaType(triton::DotOp op) {
+ Value A = op.getA();
+ Value B = op.getB();
+ auto aTy = A.getT... | What about the case where the result is BF16 ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 465 | intel | etiotto | @@ -28,6 +43,133 @@ class DotOpDPASConversionHelper {
: dpasLayout(dpasLayout), rewriter(rewriter),
typeConverter(typeConverter), loc(loc), ctx(dpasLayout.getContext()) {}
+ static DPASEngineType getMmaType(triton::DotOp op) {
+ Value A = op.getA();
+ Value B = op.getB();
+ auto aTy = A.getT... | Avoid using auto and use the static type please. Using a static type when the RHS type is not immediately obvious helps readability (this is the rule the LLVM community uses for C/C++ code). |
intel-xpu-backend-for-triton | github_2023 | cpp | 465 | intel | etiotto | @@ -28,6 +43,133 @@ class DotOpDPASConversionHelper {
: dpasLayout(dpasLayout), rewriter(rewriter),
typeConverter(typeConverter), loc(loc), ctx(dpasLayout.getContext()) {}
+ static DPASEngineType getMmaType(triton::DotOp op) {
+ Value A = op.getA();
+ Value B = op.getB();
+ auto aTy = A.getT... | ```suggestion
Type aTy = vec_ty(i32Ty, elemNumA / opsPerChan); // pack scalar to i32.
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 465 | intel | etiotto | @@ -28,6 +43,133 @@ class DotOpDPASConversionHelper {
: dpasLayout(dpasLayout), rewriter(rewriter),
typeConverter(typeConverter), loc(loc), ctx(dpasLayout.getContext()) {}
+ static DPASEngineType getMmaType(triton::DotOp op) {
+ Value A = op.getA();
+ Value B = op.getB();
+ auto aTy = A.getT... | Same comment as at line 102-103. When possible prefer initialization to assignment.
Also applies to other instances of the same code pattern. |
intel-xpu-backend-for-triton | github_2023 | cpp | 465 | intel | etiotto | @@ -28,6 +43,133 @@ class DotOpDPASConversionHelper {
: dpasLayout(dpasLayout), rewriter(rewriter),
typeConverter(typeConverter), loc(loc), ctx(dpasLayout.getContext()) {}
+ static DPASEngineType getMmaType(triton::DotOp op) {
+ Value A = op.getA();
+ Value B = op.getB();
+ auto aTy = A.getT... | Not mma, use dpas. |
intel-xpu-backend-for-triton | github_2023 | cpp | 465 | intel | etiotto | @@ -28,6 +43,133 @@ class DotOpDPASConversionHelper {
: dpasLayout(dpasLayout), rewriter(rewriter),
typeConverter(typeConverter), loc(loc), ctx(dpasLayout.getContext()) {}
+ static DPASEngineType getMmaType(triton::DotOp op) {
+ Value A = op.getA();
+ Value B = op.getB();
+ auto aTy = A.getT... | The GENX dialect will be renamed to GEN. Use `gen` rather than `genx` please. |
intel-xpu-backend-for-triton | github_2023 | cpp | 465 | intel | etiotto | @@ -129,56 +279,51 @@ class DotOpDPASConversionHelper {
}
}
- /// Generate the GENX dialect dpas operation. Rules (for PVC):
- /// - SD = 8
- /// - M = RC = 1,2,4,8 (we use 8)
- /// - N = exec_size = SIMD_width = 16
- /// - Size of A, B element type = {32,16,8}, for {tf32,bf16/f16,u8/i8}
- /// - K=... | add an assert message. |
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