Datasets:

MAI716
/

ICLayout-Bench

language:
  - en
tags:
  - integrated-circuits
  - electronic-design-automation
  - benchmark
license: other
license_name: component-specific
license_link: >-
  https://huggingface.co/datasets/MAI716/ICLayout-Bench/blob/main/README.md#licensing
configs:
  - config_name: default
    data_files:
      - split: test
        path: data.parquet

ICLayout-Bench Dataset

ICLayout-Bench provides 92 public circuit-layout tasks, including a 21-task core benchmark, for studying and evaluating automated IC layout. Given a transistor-level SPICE netlist and English requirements, a participant produces a GDS layout. The ICLayout-Bench evaluator checks physical correctness and measures post-layout electrical behavior and area under each task's declared conditions.

Each task includes requirements, a netlist, test stimuli, an evaluation contract and a qualified reference layout. Browsing these materials requires no EDA tools; running physical and electrical checks requires the evaluator and its declared external tools and process resources. Collection licenses differ, and the analog-db materials include noncommercial terms; see licensing.

Tasks and subsets

Process	All tasks	Core tasks	Circuit coverage	Resource declaration
FreePDK45	9	3	Logic cells, SRAM and peripheral circuits, differential amplifier	pdk.toml
GF180MCU	27	7	Amplifiers, comparators, regulators, temperature references, DAC, oscillator and scan logic	pdk.toml
IHP SG13G2	49	7	Amplifiers, feedback and sampled circuits, regulators, references and SiGe circuits	pdk.toml
SKY130A	7	4	Amplifiers, comparator, current mirror, power-on reset, sample-and-hold and DAC	pdk.toml
Total	92	21

The only Hugging Face configuration is default; its test split contains all 92 tasks. There are no separate training or validation splits. The core benchmark is a subset selected by in_core, not a separate split. Tasks outside core remain available for broader evaluation or focused exercises.

The core covers logic, storage, passive networks, sampling, oscillation, high-frequency behavior and feedback control while reducing repeated circuit families. It is a selection for capability coverage, not a measured difficulty ranking. core_order gives the evaluator's dispatch order, not difficulty. The full corpus is weighted toward amplifiers and RF: its presentation categories contain 52 Amplifiers & RF, 17 Mixed-signal, 14 Power & references and 9 Logic & memory tasks. Report the selected subset and per-task results when comparing participants.

Browse and download

To browse the task table with the Hugging Face datasets library:

from datasets import load_dataset

tasks = load_dataset("MAI716/ICLayout-Bench", split="test")
core = tasks.filter(lambda task: task["in_core"]).sort("core_order")
print(tasks[0]["problem"])

This loads the table, including the requirements text. It does not download the netlists, GDS references or other files addressed by the table's paths.

To download the complete dataset and read a task's files, use snapshot_download. The example loads the Parquet table from the same downloaded directory as the assets, keeping them at one revision:

from pathlib import Path
from datasets import load_dataset
from huggingface_hub import snapshot_download

revision = "main"  # Use a full dataset commit hash for repeatable experiments.
dataset_root = Path(snapshot_download(
    repo_id="MAI716/ICLayout-Bench",
    repo_type="dataset",
    revision=revision,
    local_dir="iclayout-bench-dataset",
)).resolve()
tasks = load_dataset(
    "parquet",
    data_files={"test": str(dataset_root / "data.parquet")},
    split="test",
)
task = next(task for task in tasks if task["id"] == "freepdk45.nangate45-pdk.NAND2_X1")
print(task["problem"])
print((dataset_root / task["netlist_path"]).read_text())
print("Contract:", dataset_root / task["case_path"])
print("Dataset root:", dataset_root)

A full dataset commit hash can also be passed as revision to load_dataset. For comparisons, record that revision together with the evaluator version, selected task IDs and evaluation environment.

Files and table fields

README.md
LICENSE
data.parquet                  # One row per task
tasks/<pdk>/
  pdk.toml                    # Pinned external resources and evaluation profiles
  <collection>/
    LICENSE                   # Collection and component terms
    NOTICE                    # Attribution, where present
    cases/<case>/
      case.toml               # Task metadata, inputs and evaluation contract
      problem.md              # Participant-facing requirements
      materials/              # Netlist and test stimuli
      reference/              # Reference layout

All table paths are relative to the dataset root. Paths inside case.toml are resolved relative to the case directory as specified by the evaluator. The table is a convenient view; the complete requirements and evaluation contract are in problem.md and case.toml.

Field	Meaning
`id`	Stable task identifier used for selection and evaluation.
`title`	Human-readable task title.
`pdk`, `collection`	Process and source collection in the directory hierarchy.
`category`, `summary`	Presentation category and brief circuit description.
`in_core`	Boolean membership in the core benchmark.
`core_order`	Positive integer dispatch order for core tasks; null outside core.
`task_kind`, `status`	Task type and qualification status; current tasks are qualified layout tasks.
`source_url`	Original circuit or design source for attribution.
`problem`	Full English requirements text, also available through `description_path`.
`case_path`, `case_sha256`	Contract file path and SHA-256 of its bytes.
`pdk_path`, `pdk_sha256`	Process resource declaration path and SHA-256 of its bytes.
`description_path`	Path to the requirements file.
`netlist_path`, `netlist_sha256`	Input SPICE netlist path and SHA-256 of its bytes.
`license_path`	Path to the collection license; also read any accompanying `NOTICE`.

Reference layouts are available for inspection. The standard benchmark runner provides only declared solver inputs and approved process resources to a participant; reference layouts are excluded. Use that runner when measuring participant performance to preserve the input boundary.

Evaluate a layout or check a reference

Install and configure the evaluator using its setup and tools guide. The dataset declares external PDK resources and evaluation profiles; it does not bundle the installed PDKs or EDA executables.

After preparing the required tools and resources, a reference check can use the directory downloaded above. Run this from the directory containing iclayout-bench-dataset, and choose a fresh output directory:

python -m benchmarking.engine.preview --dataset ./iclayout-bench-dataset run \
  --case freepdk45.nangate45-pdk.NAND2_X1 --output ./reference-check

This evaluates the supplied reference and writes local reports. It does not run a participant. For submitting candidate layouts or configuring participant experiments, see the evaluation guide and participant examples.

Evaluation checks the submitted artifact, design rules (DRC), netlist equivalence (LVS), declared geometry constraints and post-layout electrical requirements. Scores range from 0 to 100 and combine declared electrical quality with functional layout area. A valid reference demonstrates feasibility; it need not score 100. Tool failures or unavailable measurements can leave a score unknown; completed physical or functional rejections score zero. Exact checks, targets, weights and operating conditions belong to each task contract. See the evaluator's scoring definition.

Validation scope and limitations

The supplied references have passed their declared qualification plans. This establishes feasibility under the evaluated conditions. It does not measure participant performance or establish manufacturing signoff. Supplies, loads, temperatures, stimuli and observation windows vary by task; only the stated conditions are covered.

FreePDK45 uses predictive device models and estimated Magic RC extraction. Its community physical-check deck has known coverage limits, including an unimplemented different-potential well-spacing check.
GF180MCU uses the declared variant-D block-level checks and extraction. Chip-level density and seal-ring closure are outside this benchmark's scope.
IHP SG13G2 includes CMOS and SiGe tasks with case-specific extraction profiles. The core SiGe driver uses capacitance extraction; its high-frequency checks do not establish distributed resistance, inductance or complete RF signoff.
SKY130A uses the declared TT, 27 °C fixtures and distributed RC extraction; these tasks do not establish process-corner yield, mismatch or reliability.

Circuit names are source identifiers, not frequency or performance guarantees. For example, the case named DC_to_130_GHz_TIA.design_1 evaluates AC behavior only through 100 MHz. The VCO task evaluates the stated tuning and phase behavior, without a phase-noise or jitter claim. Read each problem before interpreting a result as evidence of circuit coverage.

Licensing

The root LICENSE is MIT and covers original project metadata and documentation. It does not replace the terms for task materials. Each row's license_path points to the applicable collection terms.

Task materials	Tasks	Included terms
analog-db derivatives in GF180MCU and IHP SG13G2	62	PolyForm Noncommercial 1.0.0, with additional retained component terms where applicable.
OpenRAM	3	GPL-3.0.
CircuitOpt, Jianxun-OTA and scan DFF	3	MIT.
Other collections	24	Apache-2.0; see each collection's `LICENSE` and `NOTICE`.

The dataset therefore uses component-specific license metadata on Hugging Face. Read the included terms for your selected tasks and retain applicable licenses, notices, attribution and modification notices when redistributing materials. External PDKs and EDA tools have separate licenses.