Add missing snapshots (batch 23/24)

snapshots/verilator_verilator_pr6870/test_regress/t/t_trace_timing1.v

@@ -0,0 +1,39 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`define STRINGIFY(x) `"x`"
+
+module t;
+
+   localparam CLOCK_CYCLE = 10;
+
+   logic rst;
+   logic clk;
+
+   initial begin
+      $dumpfile(`STRINGIFY(`TEST_DUMPFILE));
+      $dumpvars;
+   end
+
+   always #(CLOCK_CYCLE/2) clk = ~clk;
+
+   always begin
+      rst = 1;
+      clk = 0;
+      $display("[%0t] rst: %d, rst: %d", $time, rst, rst);
+
+      #CLOCK_CYCLE;
+      rst = 0;
+      $display("[%0t] rst: %d, rst: %d", $time, rst, rst);
+
+      #CLOCK_CYCLE;
+      $display("[%0t] rst: %d, rst: %d", $time, rst, rst);
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule

snapshots/verilator_verilator_pr6870/test_regress/t/t_trace_two_a.v

@@ -0,0 +1,83 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2020 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`define CONCAT(a, b) a``b
+`define STRINGIFY(x) `"x`"
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+
+   integer cyc; initial cyc=1;
+   integer c_trace_on;
+
+   sub sub ();
+
+   // verilator tracing_off
+   string  filename;
+   // verilator tracing_on
+
+   initial begin
+`ifdef TEST_FST
+      filename = {`STRINGIFY(`TEST_OBJ_DIR), "/simx.fst"};
+`else
+      filename = {`STRINGIFY(`TEST_OBJ_DIR), "/simx.vcd"};
+`endif
+
+`ifdef TEST_DUMP
+      $dumpfile(filename);
+      $dumpvars(0);  // Intentionally no ", top" for parsing coverage with just (expr)
+      $dumpvars(1, top);  // Intentionally checking parsing coverage
+      $dumpvars(1, top, top);  // Intentionally checking parsing coverage
+      $dumplimit(10 * 1024 * 1024);
+`elsif TEST_DUMPPORTS
+      $dumpports(top, filename);
+      $dumpportslimit(10 * 1024 * 1024, filename);
+`endif
+   end
+
+   always @ (posedge clk) begin
+      if (cyc != 0) begin
+         cyc <= cyc + 1;
+         c_trace_on <= cyc + 2;
+         if (cyc == 3) begin
+`ifdef TEST_DUMP
+            $dumpoff;
+`elsif TEST_DUMPPORTS
+            $dumpportsoff(filename);
+`endif
+         end
+         else if (cyc == 5) begin
+`ifdef TEST_DUMP
+            $dumpall;
+            $dumpflush;
+`elsif TEST_DUMPPORTS
+            $dumpportsall(filename);
+            $dumpportsflush(filename);
+`endif
+         end
+         else if (cyc == 7) begin
+`ifdef TEST_DUMP
+            $dumpon;
+`elsif TEST_DUMPPORTS
+            $dumpportson(filename);
+`endif
+         end
+         else if (cyc == 10) begin
+            $write("*-* All Finished *-*\n");
+            $finish;
+         end
+      end
+   end
+
+endmodule
+
+module sub;
+   integer inside_sub_a = 1;
+endmodule

snapshots/verilator_verilator_pr6870/test_regress/t/t_trace_two_b.v

@@ -0,0 +1,29 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2020 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+
+   integer cyc; initial cyc=1;
+   integer c_trace_on;
+   real    r;
+
+   sub sub ();
+
+   always @ (posedge clk) begin
+      if (cyc != 0) begin
+         r <= r + 0.1;
+      end
+   end
+endmodule
+
+module sub;
+   integer inside_sub_a = 2;
+endmodule

snapshots/verilator_verilator_pr6870/test_regress/t/t_trace_two_cc.cpp

@@ -0,0 +1,95 @@
+// DESCRIPTION: Verilator: Verilog Test
+//
+// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can
+// redistribute it and/or modify it under the terms of either the GNU
+// Lesser General Public License Version 3 or the Perl Artistic License
+// Version 2.0.
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+// clang-format off
+#include "verilatedos.h"
+#include VM_PREFIX_INCLUDE
+#include "Vt_trace_two_b.h"
+#include "verilated.h"
+#ifdef TEST_HDR_TRACE
+# ifdef TEST_FST
+#  include "verilated_fst_c.h"
+# else
+#  include "verilated_vcd_c.h"
+# endif
+#endif
+// clang-format on
+
+// Compile in place
+#include "Vt_trace_two_b__ALL.cpp"
+
+VM_PREFIX* ap;
+Vt_trace_two_b* bp;
+
+int main(int argc, char** argv) {
+    const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
+
+    uint64_t sim_time = 1100;
+    contextp->debug(0);
+    contextp->commandArgs(argc, argv);
+    contextp->traceEverOn(true);
+    srand48(5);
+    ap = new VM_PREFIX{contextp.get(), "topa"};
+    bp = new Vt_trace_two_b{contextp.get(), "topb"};
+
+    // clang-format off
+#ifdef TEST_HDR_TRACE
+    contextp->traceEverOn(true);
+# ifdef TEST_FST
+    VerilatedFstC* tfp = new VerilatedFstC;
+    ap->trace(tfp, 99);
+    bp->trace(tfp, 99);
+    tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.fst");
+# else
+    VerilatedVcdC* tfp = new VerilatedVcdC;
+    ap->trace(tfp, 99);
+    bp->trace(tfp, 99);
+    tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd");
+# endif
+#endif
+    // clang-format on
+
+#ifdef TEST_HDR_TRACE
+    ap->eval_step();
+    bp->eval_step();
+    ap->eval_end_step();
+    bp->eval_end_step();
+    if (tfp) tfp->dump(contextp->time());
+#endif
+
+    {
+        ap->clk = false;
+        contextp->timeInc(10);
+    }
+    while (contextp->time() < sim_time && !contextp->gotFinish()) {
+        ap->clk = !ap->clk;
+        bp->clk = ap->clk;
+        ap->eval_step();
+        bp->eval_step();
+        ap->eval_end_step();
+        bp->eval_end_step();
+#ifdef TEST_HDR_TRACE
+        if (tfp) tfp->dump(contextp->time());
+#endif
+        contextp->timeInc(5);
+    }
+    if (!contextp->gotFinish()) {
+        vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish");
+    }
+    ap->final();
+    bp->final();
+
+#ifdef TEST_HDR_TRACE
+    if (tfp) tfp->close();
+    VL_DO_DANGLING(delete tfp, tfp);
+#endif
+
+    VL_DO_DANGLING(delete ap, ap);
+    VL_DO_DANGLING(delete bp, bp);
+    return 0;
+}

snapshots/verilator_verilator_pr6870/test_regress/t/t_trace_two_dump_cc.out

@@ -0,0 +1,128 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module topa $end
+  $var wire 1 # clk $end
+  $scope module t $end
+   $var wire 1 # clk $end
+   $var wire 32 $ cyc [31:0] $end
+   $var wire 32 % c_trace_on [31:0] $end
+   $scope module sub $end
+    $var wire 32 & inside_sub_a [31:0] $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+ $scope module topb $end
+  $var wire 1 ( clk $end
+  $scope module t $end
+   $var wire 1 ( clk $end
+   $var wire 32 + cyc [31:0] $end
+   $var wire 32 , c_trace_on [31:0] $end
+   $var real 64 ) r $end
+   $scope module sub $end
+    $var wire 32 - inside_sub_a [31:0] $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#10
+1#
+b00000000000000000000000000000001 $
+b00000000000000000000000000000000 %
+1(
+r0 )
+b00000000000000000000000000000001 &
+b00000000000000000000000000000001 +
+b00000000000000000000000000000000 ,
+b00000000000000000000000000000010 -
+#15
+0#
+0(
+#20
+1#
+b00000000000000000000000000000010 $
+b00000000000000000000000000000011 %
+1(
+r0.1 )
+#25
+0#
+0(
+#30
+1#
+b00000000000000000000000000000011 $
+b00000000000000000000000000000100 %
+1(
+r0.2 )
+#35
+0#
+0(
+#40
+1#
+b00000000000000000000000000000100 $
+b00000000000000000000000000000101 %
+1(
+r0.3 )
+#45
+0#
+0(
+#50
+1#
+b00000000000000000000000000000101 $
+b00000000000000000000000000000110 %
+1(
+r0.4 )
+#55
+0#
+0(
+#60
+1#
+b00000000000000000000000000000110 $
+b00000000000000000000000000000111 %
+1(
+r0.5 )
+#65
+0#
+0(
+#70
+1#
+b00000000000000000000000000000111 $
+b00000000000000000000000000001000 %
+1(
+r0.6 )
+#75
+0#
+0(
+#80
+1#
+b00000000000000000000000000001000 $
+b00000000000000000000000000001001 %
+1(
+r0.7 )
+#85
+0#
+0(
+#90
+1#
+b00000000000000000000000000001001 $
+b00000000000000000000000000001010 %
+1(
+r0.7999999999999999 )
+#95
+0#
+0(
+#100
+1#
+b00000000000000000000000000001010 $
+b00000000000000000000000000001011 %
+1(
+r0.8999999999999999 )
+#105
+0#
+0(
+#110
+1#
+b00000000000000000000000000001011 $
+b00000000000000000000000000001100 %
+1(
+r0.9999999999999999 )

snapshots/verilator_verilator_pr6870/test_regress/t/t_trace_two_dump_cc.py

@@ -0,0 +1,40 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+# Test tracing with two models instanced
+import vltest_bootstrap
+
+test.scenarios('vlt_all')
+test.top_filename = "t_trace_two_a.v"
+test.pli_filename = "t/t_trace_two_cc.cpp"
+
+test.compile(make_main=False,
+             verilator_make_gmake=False,
+             top_filename='t_trace_two_b.v',
+             vm_prefix='Vt_trace_two_b',
+             verilator_flags2=['-trace'])
+
+test.run(logfile=test.obj_dir + "/make_first_ALL.log",
+         cmd=[
+             os.environ["MAKE"], "-C", "" + test.obj_dir, "-f", "Vt_trace_two_b.mk",
+             "Vt_trace_two_b__ALL.cpp"
+         ])
+
+test.compile(make_main=False,
+             top_filename='t_trace_two_a.v',
+             verilator_flags2=['-exe', '-trace', test.pli_filename],
+             v_flags2=['+define+TEST_DUMP'])
+
+test.execute()
+
+if test.vlt_all:
+    test.file_grep(test.trace_filename, r'\$enddefinitions')
+    test.vcd_identical(test.trace_filename, test.golden_filename)
+
+test.passes()

snapshots/verilator_verilator_pr6870/test_regress/t/t_trace_two_dump_sc.out

@@ -0,0 +1,123 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module topa $end
+  $scope module t $end
+   $var wire 1 # clk $end
+   $var wire 32 $ cyc [31:0] $end
+   $var wire 32 % c_trace_on [31:0] $end
+   $scope module sub $end
+    $var wire 32 & inside_sub_a [31:0] $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+ $scope module topb $end
+  $scope module t $end
+   $var wire 1 ( clk $end
+   $var wire 32 + cyc [31:0] $end
+   $var wire 32 , c_trace_on [31:0] $end
+   $var real 64 ) r $end
+   $scope module sub $end
+    $var wire 32 - inside_sub_a [31:0] $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+0#
+b00000000000000000000000000000001 $
+b00000000000000000000000000000000 %
+0(
+r0 )
+b00000000000000000000000000000001 &
+b00000000000000000000000000000001 +
+b00000000000000000000000000000000 ,
+b00000000000000000000000000000010 -
+#10000
+1#
+b00000000000000000000000000000010 $
+b00000000000000000000000000000011 %
+1(
+r0.1 )
+#15000
+0#
+0(
+#20000
+1#
+b00000000000000000000000000000011 $
+b00000000000000000000000000000100 %
+1(
+r0.2 )
+#25000
+0#
+0(
+#30000
+1#
+b00000000000000000000000000000100 $
+b00000000000000000000000000000101 %
+1(
+r0.3 )
+#35000
+0#
+0(
+#40000
+1#
+b00000000000000000000000000000101 $
+b00000000000000000000000000000110 %
+1(
+r0.4 )
+#45000
+0#
+0(
+#50000
+1#
+b00000000000000000000000000000110 $
+b00000000000000000000000000000111 %
+1(
+r0.5 )
+#55000
+0#
+0(
+#60000
+1#
+b00000000000000000000000000000111 $
+b00000000000000000000000000001000 %
+1(
+r0.6 )
+#65000
+0#
+0(
+#70000
+1#
+b00000000000000000000000000001000 $
+b00000000000000000000000000001001 %
+1(
+r0.7 )
+#75000
+0#
+0(
+#80000
+1#
+b00000000000000000000000000001001 $
+b00000000000000000000000000001010 %
+1(
+r0.7999999999999999 )
+#85000
+0#
+0(
+#90000
+1#
+b00000000000000000000000000001010 $
+b00000000000000000000000000001011 %
+1(
+r0.8999999999999999 )
+#95000
+0#
+0(
+#100000
+1#
+b00000000000000000000000000001011 $
+b00000000000000000000000000001100 %
+1(
+r0.9999999999999999 )

snapshots/verilator_verilator_pr6870/test_regress/t/t_trace_two_dump_sc.py

@@ -0,0 +1,42 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t_trace_two_a.v"
+test.pli_filename = "t/t_trace_two_sc.cpp"
+
+if not test.have_sc:
+    test.skip("No SystemC installed")
+
+test.compile(make_main=False,
+             verilator_make_gmake=False,
+             top_filename='t_trace_two_b.v',
+             vm_prefix='Vt_trace_two_b',
+             verilator_flags2=['-sc -trace'])
+
+test.run(logfile=test.obj_dir + "/make_first_ALL.log",
+         cmd=[
+             os.environ["MAKE"], "-C", test.obj_dir, "-f", "Vt_trace_two_b.mk",
+             "Vt_trace_two_b__ALL.cpp"
+         ])
+
+test.compile(make_main=False,
+             top_filename='t_trace_two_a.v',
+             verilator_flags2=['-sc', '-exe', '-trace', test.pli_filename],
+             v_flags2=['+define+TEST_DUMP'])
+
+test.execute()
+
+if test.vlt_all:
+    test.file_grep(test.trace_filename, r'\$enddefinitions')
+    test.vcd_identical(test.trace_filename, test.golden_filename)
+
+test.passes()

snapshots/verilator_verilator_pr6870/test_regress/t/t_trace_two_dumpfst_cc.out

@@ -0,0 +1,136 @@
+$date
+	Sat Mar 30 14:01:55 2024
+
+$end
+$version
+	fstWriter
+$end
+$timescale
+	1ps
+$end
+$scope module topa $end
+$var wire 1 ! clk $end
+$scope module t $end
+$var wire 1 ! clk $end
+$var integer 32 " cyc [31:0] $end
+$var integer 32 # c_trace_on [31:0] $end
+$scope module sub $end
+$var integer 32 $ inside_sub_a [31:0] $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope module topb $end
+$var wire 1 % clk $end
+$scope module t $end
+$var wire 1 % clk $end
+$var integer 32 & cyc [31:0] $end
+$var integer 32 ' c_trace_on [31:0] $end
+$var real 64 ( r $end
+$scope module sub $end
+$var integer 32 ) inside_sub_a [31:0] $end
+$upscope $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#10
+$dumpvars
+b00000000000000000000000000000010 )
+r0 (
+b00000000000000000000000000000000 '
+b00000000000000000000000000000001 &
+1%
+b00000000000000000000000000000001 $
+b00000000000000000000000000000000 #
+b00000000000000000000000000000001 "
+1!
+$end
+#15
+0!
+0%
+#20
+1%
+1!
+b00000000000000000000000000000010 "
+b00000000000000000000000000000011 #
+r0.1 (
+#25
+0!
+0%
+#30
+1%
+1!
+r0.2 (
+b00000000000000000000000000000100 #
+b00000000000000000000000000000011 "
+#35
+0!
+0%
+#40
+1%
+1!
+b00000000000000000000000000000100 "
+b00000000000000000000000000000101 #
+r0.3 (
+#45
+0!
+0%
+#50
+1%
+1!
+r0.4 (
+b00000000000000000000000000000110 #
+b00000000000000000000000000000101 "
+#55
+0!
+0%
+#60
+1%
+1!
+b00000000000000000000000000000110 "
+b00000000000000000000000000000111 #
+r0.5 (
+#65
+0!
+0%
+#70
+1%
+1!
+r0.6 (
+b00000000000000000000000000001000 #
+b00000000000000000000000000000111 "
+#75
+0!
+0%
+#80
+1%
+1!
+b00000000000000000000000000001000 "
+b00000000000000000000000000001001 #
+r0.7 (
+#85
+0!
+0%
+#90
+1%
+1!
+r0.7999999999999999 (
+b00000000000000000000000000001010 #
+b00000000000000000000000000001001 "
+#95
+0!
+0%
+#100
+1%
+1!
+b00000000000000000000000000001010 "
+b00000000000000000000000000001011 #
+r0.8999999999999999 (
+#105
+0!
+0%
+#110
+1%
+1!
+r0.9999999999999999 (
+b00000000000000000000000000001100 #
+b00000000000000000000000000001011 "

snapshots/verilator_verilator_pr6870/test_regress/t/t_trace_two_dumpfst_cc.py

@@ -0,0 +1,40 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+# Test tracing with two models instanced
+import vltest_bootstrap
+
+test.scenarios('vlt_all')
+test.top_filename = "t_trace_two_a.v"
+test.pli_filename = "t/t_trace_two_cc.cpp"
+
+test.compile(make_main=False,
+             verilator_make_gmake=False,
+             top_filename='t_trace_two_b.v',
+             vm_prefix='Vt_trace_two_b',
+             verilator_flags2=['--trace-fst --trace-threads 1 -DTEST_FST'])
+
+test.run(logfile=test.obj_dir + "/make_first_ALL.log",
+         cmd=[
+             os.environ["MAKE"], "-C", test.obj_dir, "-f", "Vt_trace_two_b.mk",
+             "Vt_trace_two_b__ALL.cpp"
+         ])
+
+test.compile(
+    make_main=False,
+    top_filename='t_trace_two_a.v',
+    verilator_flags2=['-exe', '--trace-fst --trace-threads 1', '-DTEST_FST', test.pli_filename],
+    v_flags2=['+define+TEST_DUMP'])
+
+test.execute()
+
+if test.vlt_all:
+    test.fst_identical(test.trace_filename, test.golden_filename)
+
+test.passes()

snapshots/verilator_verilator_pr6870/test_regress/t/t_trace_two_hdr_cc.out

@@ -0,0 +1,126 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+
+ $scope module topa $end
+  $var wire 1 # clk $end
+  $scope module t $end
+   $var wire 1 # clk $end
+   $var wire 32 $ cyc [31:0] $end
+   $var wire 32 % c_trace_on [31:0] $end
+   $scope module sub $end
+    $var wire 32 & inside_sub_a [31:0] $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+ $scope module topb $end
+  $var wire 1 ( clk $end
+  $scope module t $end
+   $var wire 1 ( clk $end
+   $var wire 32 + cyc [31:0] $end
+   $var wire 32 , c_trace_on [31:0] $end
+   $var real 64 ) r $end
+   $scope module sub $end
+    $var wire 32 - inside_sub_a [31:0] $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+0#
+b00000000000000000000000000000001 $
+b00000000000000000000000000000000 %
+0(
+r0 )
+b00000000000000000000000000000001 &
+b00000000000000000000000000000001 +
+b00000000000000000000000000000000 ,
+b00000000000000000000000000000010 -
+#10
+1#
+b00000000000000000000000000000010 $
+b00000000000000000000000000000011 %
+1(
+r0.1 )
+#15
+0#
+0(
+#20
+1#
+b00000000000000000000000000000011 $
+b00000000000000000000000000000100 %
+1(
+r0.2 )
+#25
+0#
+0(
+#30
+1#
+b00000000000000000000000000000100 $
+b00000000000000000000000000000101 %
+1(
+r0.3 )
+#35
+0#
+0(
+#40
+1#
+b00000000000000000000000000000101 $
+b00000000000000000000000000000110 %
+1(
+r0.4 )
+#45
+0#
+0(
+#50
+1#
+b00000000000000000000000000000110 $
+b00000000000000000000000000000111 %
+1(
+r0.5 )
+#55
+0#
+0(
+#60
+1#
+b00000000000000000000000000000111 $
+b00000000000000000000000000001000 %
+1(
+r0.6 )
+#65
+0#
+0(
+#70
+1#
+b00000000000000000000000000001000 $
+b00000000000000000000000000001001 %
+1(
+r0.7 )
+#75
+0#
+0(
+#80
+1#
+b00000000000000000000000000001001 $
+b00000000000000000000000000001010 %
+1(
+r0.7999999999999999 )
+#85
+0#
+0(
+#90
+1#
+b00000000000000000000000000001010 $
+b00000000000000000000000000001011 %
+1(
+r0.8999999999999999 )
+#95
+0#
+0(
+#100
+1#
+b00000000000000000000000000001011 $
+b00000000000000000000000000001100 %
+1(
+r0.9999999999999999 )

snapshots/verilator_verilator_pr6870/test_regress/t/t_trace_two_hdr_cc.py

@@ -0,0 +1,40 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+# Test tracing with two models instanced
+import vltest_bootstrap
+
+test.scenarios('vlt_all')
+test.top_filename = "t_trace_two_a.v"
+test.pli_filename = "t/t_trace_two_cc.cpp"
+
+test.compile(make_main=False,
+             verilator_make_gmake=False,
+             top_filename='t_trace_two_b.v',
+             vm_prefix='Vt_trace_two_b',
+             verilator_flags2=['-trace'])
+
+test.run(logfile=test.obj_dir + "/make_first_ALL.log",
+         cmd=[
+             os.environ["MAKE"], "-C", test.obj_dir, "-f", "Vt_trace_two_b.mk",
+             "Vt_trace_two_b__ALL.cpp"
+         ])
+
+test.compile(make_main=False,
+             top_filename='t_trace_two_a.v',
+             make_flags=['CPPFLAGS_ADD=-DTEST_HDR_TRACE=1'],
+             verilator_flags2=['-exe', '-trace', test.pli_filename])
+
+test.execute()
+
+if test.vlt_all:
+    test.file_grep(test.trace_filename, r'\$enddefinitions')
+    test.vcd_identical(test.trace_filename, test.golden_filename)
+
+test.passes()

snapshots/verilator_verilator_pr6870/test_regress/t/t_trace_two_hdr_sc.out

@@ -0,0 +1,124 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+
+ $scope module topa $end
+  $scope module t $end
+   $var wire 1 # clk $end
+   $var wire 32 $ cyc [31:0] $end
+   $var wire 32 % c_trace_on [31:0] $end
+   $scope module sub $end
+    $var wire 32 & inside_sub_a [31:0] $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+ $scope module topb $end
+  $scope module t $end
+   $var wire 1 ( clk $end
+   $var wire 32 + cyc [31:0] $end
+   $var wire 32 , c_trace_on [31:0] $end
+   $var real 64 ) r $end
+   $scope module sub $end
+    $var wire 32 - inside_sub_a [31:0] $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+0#
+b00000000000000000000000000000001 $
+b00000000000000000000000000000000 %
+0(
+r0 )
+b00000000000000000000000000000001 &
+b00000000000000000000000000000001 +
+b00000000000000000000000000000000 ,
+b00000000000000000000000000000010 -
+#10000
+1#
+b00000000000000000000000000000010 $
+b00000000000000000000000000000011 %
+1(
+r0.1 )
+#15000
+0#
+0(
+#20000
+1#
+b00000000000000000000000000000011 $
+b00000000000000000000000000000100 %
+1(
+r0.2 )
+#25000
+0#
+0(
+#30000
+1#
+b00000000000000000000000000000100 $
+b00000000000000000000000000000101 %
+1(
+r0.3 )
+#35000
+0#
+0(
+#40000
+1#
+b00000000000000000000000000000101 $
+b00000000000000000000000000000110 %
+1(
+r0.4 )
+#45000
+0#
+0(
+#50000
+1#
+b00000000000000000000000000000110 $
+b00000000000000000000000000000111 %
+1(
+r0.5 )
+#55000
+0#
+0(
+#60000
+1#
+b00000000000000000000000000000111 $
+b00000000000000000000000000001000 %
+1(
+r0.6 )
+#65000
+0#
+0(
+#70000
+1#
+b00000000000000000000000000001000 $
+b00000000000000000000000000001001 %
+1(
+r0.7 )
+#75000
+0#
+0(
+#80000
+1#
+b00000000000000000000000000001001 $
+b00000000000000000000000000001010 %
+1(
+r0.7999999999999999 )
+#85000
+0#
+0(
+#90000
+1#
+b00000000000000000000000000001010 $
+b00000000000000000000000000001011 %
+1(
+r0.8999999999999999 )
+#95000
+0#
+0(
+#100000
+1#
+b00000000000000000000000000001011 $
+b00000000000000000000000000001100 %
+1(
+r0.9999999999999999 )

snapshots/verilator_verilator_pr6870/test_regress/t/t_trace_two_hdr_sc.py

@@ -0,0 +1,42 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t_trace_two_a.v"
+test.pli_filename = "t/t_trace_two_sc.cpp"
+
+if not test.have_sc:
+    test.skip("No SystemC installed")
+
+test.compile(make_main=False,
+             verilator_make_gmake=False,
+             top_filename='t_trace_two_b.v',
+             vm_prefix='Vt_trace_two_b',
+             verilator_flags2=['-sc -trace'])
+
+test.run(logfile=test.obj_dir + "/make_first_ALL.log",
+         cmd=[
+             os.environ["MAKE"], "-C", test.obj_dir, "-f", "Vt_trace_two_b.mk",
+             "Vt_trace_two_b__ALL.cpp"
+         ])
+
+test.compile(make_main=False,
+             top_filename='t_trace_two_a.v',
+             make_flags=['CPPFLAGS_ADD=-DTEST_HDR_TRACE'],
+             verilator_flags2=['-sc', '-exe', '-trace', test.pli_filename])
+
+test.execute()
+
+if test.vlt_all:
+    test.file_grep(test.trace_filename, r'\$enddefinitions')
+    test.vcd_identical(test.trace_filename, test.golden_filename)
+
+test.passes()

snapshots/verilator_verilator_pr6870/test_regress/t/t_trace_two_hdrfst_cc.out

@@ -0,0 +1,133 @@
+$date
+	Wed Feb 23 00:03:39 2022
+
+$end
+$version
+	fstWriter
+$end
+$timescale
+	1ps
+$end
+$scope module topa $end
+$var wire 1 ! clk $end
+$scope module t $end
+$var wire 1 ! clk $end
+$var integer 32 " cyc [31:0] $end
+$var integer 32 # c_trace_on [31:0] $end
+$scope module sub $end
+$var integer 32 $ inside_sub_a [31:0] $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope module topb $end
+$var wire 1 % clk $end
+$scope module t $end
+$var wire 1 % clk $end
+$var integer 32 & cyc [31:0] $end
+$var integer 32 ' c_trace_on [31:0] $end
+$var real 64 ( r $end
+$scope module sub $end
+$var integer 32 ) inside_sub_a [31:0] $end
+$upscope $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+b00000000000000000000000000000010 )
+r0 (
+b00000000000000000000000000000000 '
+b00000000000000000000000000000001 &
+0%
+b00000000000000000000000000000001 $
+b00000000000000000000000000000000 #
+b00000000000000000000000000000001 "
+0!
+$end
+#10
+1!
+b00000000000000000000000000000010 "
+b00000000000000000000000000000011 #
+1%
+r0.1 (
+#15
+0%
+0!
+#20
+1!
+1%
+r0.2 (
+b00000000000000000000000000000100 #
+b00000000000000000000000000000011 "
+#25
+0%
+0!
+#30
+1!
+1%
+b00000000000000000000000000000100 "
+b00000000000000000000000000000101 #
+r0.3 (
+#35
+0%
+0!
+#40
+1!
+1%
+r0.4 (
+b00000000000000000000000000000110 #
+b00000000000000000000000000000101 "
+#45
+0%
+0!
+#50
+1!
+1%
+b00000000000000000000000000000110 "
+b00000000000000000000000000000111 #
+r0.5 (
+#55
+0%
+0!
+#60
+1!
+1%
+r0.6 (
+b00000000000000000000000000001000 #
+b00000000000000000000000000000111 "
+#65
+0%
+0!
+#70
+1!
+1%
+b00000000000000000000000000001000 "
+b00000000000000000000000000001001 #
+r0.7 (
+#75
+0%
+0!
+#80
+1!
+1%
+r0.7999999999999999 (
+b00000000000000000000000000001010 #
+b00000000000000000000000000001001 "
+#85
+0%
+0!
+#90
+1!
+1%
+b00000000000000000000000000001010 "
+b00000000000000000000000000001011 #
+r0.8999999999999999 (
+#95
+0%
+0!
+#100
+1!
+1%
+r0.9999999999999999 (
+b00000000000000000000000000001100 #
+b00000000000000000000000000001011 "

snapshots/verilator_verilator_pr6870/test_regress/t/t_trace_two_hdrfst_cc.py

@@ -0,0 +1,40 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+# Test tracing with two models instanced
+import vltest_bootstrap
+
+test.scenarios('vlt_all')
+test.top_filename = "t_trace_two_a.v"
+test.pli_filename = "t/t_trace_two_cc.cpp"
+
+test.compile(make_main=False,
+             verilator_make_gmake=False,
+             top_filename='t_trace_two_b.v',
+             vm_prefix='Vt_trace_two_b',
+             verilator_flags2=['--trace-fst --trace-threads 1'])
+
+test.run(logfile=test.obj_dir + "/make_first_ALL.log",
+         cmd=[
+             os.environ["MAKE"], "-C", "" + test.obj_dir, "-f", "Vt_trace_two_b.mk",
+             "Vt_trace_two_b__ALL.cpp"
+         ])
+
+test.compile(
+    make_main=False,
+    top_filename='t_trace_two_a.v',
+    make_flags=['CPPFLAGS_ADD="-DTEST_HDR_TRACE=1 -DTEST_FST=1"'],
+    verilator_flags2=['-exe', '--trace-fst --trace-threads 1', '-DTEST_FST', test.pli_filename])
+
+test.execute()
+
+if test.vlt_all:
+    test.fst_identical(test.trace_filename, test.golden_filename)
+
+test.passes()

snapshots/verilator_verilator_pr6870/test_regress/t/t_trace_two_port_cc.out

@@ -0,0 +1,128 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module topa $end
+  $var wire 1 # clk $end
+  $scope module t $end
+   $var wire 1 # clk $end
+   $var wire 32 $ cyc [31:0] $end
+   $var wire 32 % c_trace_on [31:0] $end
+   $scope module sub $end
+    $var wire 32 & inside_sub_a [31:0] $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+ $scope module topb $end
+  $var wire 1 ( clk $end
+  $scope module t $end
+   $var wire 1 ( clk $end
+   $var wire 32 + cyc [31:0] $end
+   $var wire 32 , c_trace_on [31:0] $end
+   $var real 64 ) r $end
+   $scope module sub $end
+    $var wire 32 - inside_sub_a [31:0] $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#10
+1#
+b00000000000000000000000000000001 $
+b00000000000000000000000000000000 %
+1(
+r0 )
+b00000000000000000000000000000001 &
+b00000000000000000000000000000001 +
+b00000000000000000000000000000000 ,
+b00000000000000000000000000000010 -
+#15
+0#
+0(
+#20
+1#
+b00000000000000000000000000000010 $
+b00000000000000000000000000000011 %
+1(
+r0.1 )
+#25
+0#
+0(
+#30
+1#
+b00000000000000000000000000000011 $
+b00000000000000000000000000000100 %
+1(
+r0.2 )
+#35
+0#
+0(
+#40
+1#
+b00000000000000000000000000000100 $
+b00000000000000000000000000000101 %
+1(
+r0.3 )
+#45
+0#
+0(
+#50
+1#
+b00000000000000000000000000000101 $
+b00000000000000000000000000000110 %
+1(
+r0.4 )
+#55
+0#
+0(
+#60
+1#
+b00000000000000000000000000000110 $
+b00000000000000000000000000000111 %
+1(
+r0.5 )
+#65
+0#
+0(
+#70
+1#
+b00000000000000000000000000000111 $
+b00000000000000000000000000001000 %
+1(
+r0.6 )
+#75
+0#
+0(
+#80
+1#
+b00000000000000000000000000001000 $
+b00000000000000000000000000001001 %
+1(
+r0.7 )
+#85
+0#
+0(
+#90
+1#
+b00000000000000000000000000001001 $
+b00000000000000000000000000001010 %
+1(
+r0.7999999999999999 )
+#95
+0#
+0(
+#100
+1#
+b00000000000000000000000000001010 $
+b00000000000000000000000000001011 %
+1(
+r0.8999999999999999 )
+#105
+0#
+0(
+#110
+1#
+b00000000000000000000000000001011 $
+b00000000000000000000000000001100 %
+1(
+r0.9999999999999999 )

snapshots/verilator_verilator_pr6870/test_regress/t/t_trace_two_port_cc.py

@@ -0,0 +1,40 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+# Test tracing with two models instanced
+import vltest_bootstrap
+
+test.scenarios('vlt_all')
+test.top_filename = "t_trace_two_a.v"
+test.pli_filename = "t/t_trace_two_cc.cpp"
+
+test.compile(make_main=False,
+             verilator_make_gmake=False,
+             top_filename='t_trace_two_b.v',
+             vm_prefix='Vt_trace_two_b',
+             verilator_flags2=['-trace'])
+
+test.run(logfile=test.obj_dir + "/make_first_ALL.log",
+         cmd=[
+             os.environ["MAKE"], "-C", test.obj_dir, "-f", "Vt_trace_two_b.mk",
+             "Vt_trace_two_b__ALL.cpp"
+         ])
+
+test.compile(make_main=False,
+             top_filename='t_trace_two_a.v',
+             verilator_flags2=['-exe', '-trace', test.pli_filename],
+             v_flags2=['+define+TEST_DUMPPORTS'])
+
+test.execute()
+
+if test.vlt_all:
+    test.file_grep(test.trace_filename, r'\$enddefinitions')
+    test.vcd_identical(test.trace_filename, test.golden_filename)
+
+test.passes()

snapshots/verilator_verilator_pr6870/test_regress/t/t_trace_two_port_sc.out

@@ -0,0 +1,123 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module topa $end
+  $scope module t $end
+   $var wire 1 # clk $end
+   $var wire 32 $ cyc [31:0] $end
+   $var wire 32 % c_trace_on [31:0] $end
+   $scope module sub $end
+    $var wire 32 & inside_sub_a [31:0] $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+ $scope module topb $end
+  $scope module t $end
+   $var wire 1 ( clk $end
+   $var wire 32 + cyc [31:0] $end
+   $var wire 32 , c_trace_on [31:0] $end
+   $var real 64 ) r $end
+   $scope module sub $end
+    $var wire 32 - inside_sub_a [31:0] $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+0#
+b00000000000000000000000000000001 $
+b00000000000000000000000000000000 %
+0(
+r0 )
+b00000000000000000000000000000001 &
+b00000000000000000000000000000001 +
+b00000000000000000000000000000000 ,
+b00000000000000000000000000000010 -
+#10000
+1#
+b00000000000000000000000000000010 $
+b00000000000000000000000000000011 %
+1(
+r0.1 )
+#15000
+0#
+0(
+#20000
+1#
+b00000000000000000000000000000011 $
+b00000000000000000000000000000100 %
+1(
+r0.2 )
+#25000
+0#
+0(
+#30000
+1#
+b00000000000000000000000000000100 $
+b00000000000000000000000000000101 %
+1(
+r0.3 )
+#35000
+0#
+0(
+#40000
+1#
+b00000000000000000000000000000101 $
+b00000000000000000000000000000110 %
+1(
+r0.4 )
+#45000
+0#
+0(
+#50000
+1#
+b00000000000000000000000000000110 $
+b00000000000000000000000000000111 %
+1(
+r0.5 )
+#55000
+0#
+0(
+#60000
+1#
+b00000000000000000000000000000111 $
+b00000000000000000000000000001000 %
+1(
+r0.6 )
+#65000
+0#
+0(
+#70000
+1#
+b00000000000000000000000000001000 $
+b00000000000000000000000000001001 %
+1(
+r0.7 )
+#75000
+0#
+0(
+#80000
+1#
+b00000000000000000000000000001001 $
+b00000000000000000000000000001010 %
+1(
+r0.7999999999999999 )
+#85000
+0#
+0(
+#90000
+1#
+b00000000000000000000000000001010 $
+b00000000000000000000000000001011 %
+1(
+r0.8999999999999999 )
+#95000
+0#
+0(
+#100000
+1#
+b00000000000000000000000000001011 $
+b00000000000000000000000000001100 %
+1(
+r0.9999999999999999 )

snapshots/verilator_verilator_pr6870/test_regress/t/t_trace_two_port_sc.py

@@ -0,0 +1,43 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+if not test.have_sc:
+    test.skip("No SystemC installed")
+
+top_filename = "t_trace_two_a.v"
+test.pli_filename = "t/t_trace_two_sc.cpp"
+
+test.compile(make_main=False,
+             verilator_make_gmake=False,
+             top_filename='t_trace_two_b.v',
+             vm_prefix='Vt_trace_two_b',
+             verilator_flags2=['-sc -trace'])
+
+test.run(logfile=test.obj_dir + "/make_first_ALL.log",
+         cmd=[
+             os.environ["MAKE"], "-C", test.obj_dir, "-f", "Vt_trace_two_b.mk",
+             "Vt_trace_two_b__ALL.cpp"
+         ])
+
+test.compile(make_main=False,
+             top_filename='t_trace_two_a.v',
+             verilator_flags2=['-sc', '-exe', '-trace', test.pli_filename],
+             v_flags2=['+define+TEST_DUMPPORTS'])
+
+test.execute()
+
+if test.vlt_all:
+    test.file_grep(test.trace_filename, r'\$enddefinitions')
+    test.vcd_identical(test.trace_filename, test.golden_filename)
+
+test.passes()

snapshots/verilator_verilator_pr6870/test_regress/t/t_trace_two_portfst_cc.out

@@ -0,0 +1,136 @@
+$date
+	Sat Mar 30 14:08:31 2024
+
+$end
+$version
+	fstWriter
+$end
+$timescale
+	1ps
+$end
+$scope module topa $end
+$var wire 1 ! clk $end
+$scope module t $end
+$var wire 1 ! clk $end
+$var integer 32 " cyc [31:0] $end
+$var integer 32 # c_trace_on [31:0] $end
+$scope module sub $end
+$var integer 32 $ inside_sub_a [31:0] $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope module topb $end
+$var wire 1 % clk $end
+$scope module t $end
+$var wire 1 % clk $end
+$var integer 32 & cyc [31:0] $end
+$var integer 32 ' c_trace_on [31:0] $end
+$var real 64 ( r $end
+$scope module sub $end
+$var integer 32 ) inside_sub_a [31:0] $end
+$upscope $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#10
+$dumpvars
+b00000000000000000000000000000010 )
+r0 (
+b00000000000000000000000000000000 '
+b00000000000000000000000000000001 &
+1%
+b00000000000000000000000000000001 $
+b00000000000000000000000000000000 #
+b00000000000000000000000000000001 "
+1!
+$end
+#15
+0!
+0%
+#20
+1%
+1!
+b00000000000000000000000000000010 "
+b00000000000000000000000000000011 #
+r0.1 (
+#25
+0!
+0%
+#30
+1%
+1!
+r0.2 (
+b00000000000000000000000000000100 #
+b00000000000000000000000000000011 "
+#35
+0!
+0%
+#40
+1%
+1!
+b00000000000000000000000000000100 "
+b00000000000000000000000000000101 #
+r0.3 (
+#45
+0!
+0%
+#50
+1%
+1!
+r0.4 (
+b00000000000000000000000000000110 #
+b00000000000000000000000000000101 "
+#55
+0!
+0%
+#60
+1%
+1!
+b00000000000000000000000000000110 "
+b00000000000000000000000000000111 #
+r0.5 (
+#65
+0!
+0%
+#70
+1%
+1!
+r0.6 (
+b00000000000000000000000000001000 #
+b00000000000000000000000000000111 "
+#75
+0!
+0%
+#80
+1%
+1!
+b00000000000000000000000000001000 "
+b00000000000000000000000000001001 #
+r0.7 (
+#85
+0!
+0%
+#90
+1%
+1!
+r0.7999999999999999 (
+b00000000000000000000000000001010 #
+b00000000000000000000000000001001 "
+#95
+0!
+0%
+#100
+1%
+1!
+b00000000000000000000000000001010 "
+b00000000000000000000000000001011 #
+r0.8999999999999999 (
+#105
+0!
+0%
+#110
+1%
+1!
+r0.9999999999999999 (
+b00000000000000000000000000001100 #
+b00000000000000000000000000001011 "

snapshots/verilator_verilator_pr6870/test_regress/t/t_trace_two_portfst_cc.py

@@ -0,0 +1,40 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+# Test tracing with two models instanced
+import vltest_bootstrap
+
+test.scenarios('vlt_all')
+test.top_filename = "t_trace_two_a.v"
+test.pli_filename = "t/t_trace_two_cc.cpp"
+
+test.compile(make_main=False,
+             verilator_make_gmake=False,
+             top_filename='t_trace_two_b.v',
+             vm_prefix='Vt_trace_two_b',
+             verilator_flags2=['--trace-fst --trace-threads 1'])
+
+test.run(logfile=test.obj_dir + "/make_first_ALL.log",
+         cmd=[
+             os.environ["MAKE"], "-C", "" + test.obj_dir, "-f", "Vt_trace_two_b.mk",
+             "Vt_trace_two_b__ALL.cpp"
+         ])
+
+test.compile(
+    make_main=False,
+    top_filename='t_trace_two_a.v',
+    verilator_flags2=['-exe', '--trace-fst --trace-threads 1', '-DTEST_FST', test.pli_filename],
+    v_flags2=['+define+TEST_DUMPPORTS'])
+
+test.execute()
+
+if test.vlt_all:
+    test.fst_identical(test.trace_filename, test.golden_filename)
+
+test.passes()

snapshots/verilator_verilator_pr6870/test_regress/t/t_trace_two_sc.cpp

@@ -0,0 +1,70 @@
+// DESCRIPTION: Verilator: Verilog Test
+//
+// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can
+// redistribute it and/or modify it under the terms of either the GNU
+// Lesser General Public License Version 3 or the Perl Artistic License
+// Version 2.0.
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+// clang-format off
+#include "verilatedos.h"
+#include VM_PREFIX_INCLUDE
+#include "Vt_trace_two_b.h"
+#include "verilated.h"
+#ifdef TEST_HDR_TRACE
+# include "verilated_vcd_sc.h"
+#endif
+// clang-format on
+
+// Compile in place
+#include "Vt_trace_two_b__ALL.cpp"
+
+// General headers
+#include "verilated.h"
+
+#include "systemc.h"
+
+VM_PREFIX* ap;
+Vt_trace_two_b* bp;
+
+int sc_main(int argc, char** argv) {
+    Verilated::debug(0);
+    Verilated::traceEverOn(true);
+    Verilated::commandArgs(argc, argv);
+
+    sc_signal<bool> clk;
+    sc_time sim_time(1100, SC_NS);
+    srand48(5);
+    ap = new VM_PREFIX{"topa"};
+    bp = new Vt_trace_two_b{"topb"};
+    ap->clk(clk);
+    bp->clk(clk);
+
+#ifdef TEST_HDR_TRACE
+    VerilatedVcdSc* tfp = new VerilatedVcdSc;
+    sc_core::sc_start(sc_core::SC_ZERO_TIME);
+    ap->trace(tfp, 99);
+    bp->trace(tfp, 99);
+    tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd");
+#endif
+    {
+        clk = false;
+        sc_start(10, SC_NS);
+    }
+    while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) {
+        clk = !clk;
+        sc_start(5, SC_NS);
+    }
+    if (!Verilated::gotFinish()) {
+        vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish");
+    }
+    ap->final();
+    bp->final();
+#ifdef TEST_HDR_TRACE
+    if (tfp) tfp->close();
+#endif
+
+    VL_DO_DANGLING(delete ap, ap);
+    VL_DO_DANGLING(delete bp, bp);
+    return 0;
+}

snapshots/verilator_verilator_pr6870/test_regress/t/t_trace_ub_misaligned_address.out

@@ -0,0 +1 @@
+*-* All Finished *-*

snapshots/verilator_verilator_pr6870/test_regress/t/t_trace_ub_misaligned_address.py

@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_trace_ub_misaligned_address.v"
+
+test.compile(verilator_flags2=["--binary --trace-vcd", "--runtime-debug"])
+
+test.execute(aslr_off=True)
+
+# Make sure that there are no additional messages (such as runtime messages
+# regarding undefined behavior).test.files_identical(test.obj_dir + "/vlt_sim.log", test.golden_filename, "logfile")
+
+test.passes()

snapshots/verilator_verilator_pr6870/test_regress/t/t_trace_ub_misaligned_address.v

@@ -0,0 +1,92 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// When compiled using -fsanitize=address,undefined this triggered:
+//
+//   verilated_trace_imp.h:875:5: runtime error: store to misaligned address ...
+//   verilated_trace.h:450:31: runtime error: load of misaligned address ...
+//
+// due to 32 bit aligned addresses being used for types which require
+// stricter alignment.
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by John Wehle.
+// SPDX-License-Identifier: CC0-1.0
+
+`define STRINGIFY(x) `"x`"
+
+module t;
+
+  wire [2:0] out;
+  reg        in;
+  reg [39:0] p;
+  reg        rst;
+  reg        clk;
+
+  initial begin
+    $dumpfile(`STRINGIFY(`TEST_DUMPFILE));
+    $dumpvars(0, test);
+
+    clk = 0;
+    rst = 0;
+
+    for (int i = 0; i < 2; i++)
+      begin
+        #10 rst = 1;
+        #10 rst = 0;
+
+        p = 40'b0000000000111111111111111111110000000000;
+
+        in = i[0];
+
+        for (int k = 0; k < 31; k++)
+          begin
+            in = p[39 - k] ^ i[0];
+            #1;
+          end
+
+        end
+
+    #30 $write("*-* All Finished *-*\n");
+    $finish;
+  end
+
+  always begin
+    #10 clk <= !clk;
+  end
+
+  Test test(.out(out), .in(in),
+            .clk(clk), .rst(rst));
+endmodule
+
+
+module Test(/*AUTOARG*/
+  // Outputs
+  out,
+  // Inputs
+  clk, in, rst
+  );
+
+  input             clk;
+  input             in;
+  input             rst;
+  output wire [2:0] out;
+
+  reg [2:0] s;
+  reg       sin;
+
+  assign out = s;
+
+  always @(posedge clk, posedge rst)
+    begin
+      s[0] <= s[2];
+      s[2] <= in;
+      s[1] <= sin;
+    end
+
+  always @(negedge clk, posedge rst)
+    if (rst)
+      sin <= 1'b0;
+    else
+      sin <= in;
+
+endmodule

snapshots/verilator_verilator_pr6870/test_regress/t/t_trace_wide_struct.py

@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(verilator_flags2=['--trace-vcd --trace-structs'])
+
+test.passes()

snapshots/verilator_verilator_pr6870/test_regress/t/t_trace_wide_struct.v

@@ -0,0 +1,23 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2011 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   typedef struct {
+       logic [64:0] long_signal;
+   } mystruct_t;
+
+   mystruct_t mystruct;
+
+   initial begin
+       $finish;
+   end
+
+endmodule

snapshots/verilator_verilator_pr6870/test_regress/t/t_tri_and_eqcase.out

@@ -0,0 +1,8 @@
+%Error-UNSUPPORTED: t/t_tri_and_eqcase.v:9:29: Unsupported tristate construct: AND in function getEnExprBasedOnOriginalp
+    9 |    logic b = 1'bz === (clk1 & clk2);
+      |                             ^
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error: Internal Error: t/t_tri_and_eqcase.v:9:19: ../V3Ast.cpp:#: Null item passed to setOp2p
+    9 |    logic b = 1'bz === (clk1 & clk2);
+      |                   ^~~
+                        ... This fatal error may be caused by the earlier error(s); resolve those first.

snapshots/verilator_verilator_pr6870/test_regress/t/t_tri_and_eqcase.py

@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.lint(fails=test.vlt_all, expect_filename=test.golden_filename)
+
+test.passes()

snapshots/verilator_verilator_pr6870/test_regress/t/t_tri_and_eqcase.v

@@ -0,0 +1,17 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (clk1, clk2);
+   input wire clk1, clk2;
+   logic b = 1'bz === (clk1 & clk2);
+
+   always begin
+      if (!b) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+endmodule

snapshots/verilator_verilator_pr6870/test_regress/t/t_tri_array.out

@@ -0,0 +1,10 @@
+%Error-UNSUPPORTED: t/t_tri_array.v:25:25: Unsupported LHS tristate construct: ARRAYSEL
+                                         : ... note: In instance 't'
+   25 |       Pad pad1 (.pad(pad[g]),
+      |                         ^
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error-UNSUPPORTED: t/t_tri_array.v:28:25: Unsupported LHS tristate construct: ARRAYSEL
+                                         : ... note: In instance 't'
+   28 |       Pad pad0 (.pad(pad[g]),
+      |                         ^
+%Error: Exiting due to

snapshots/verilator_verilator_pr6870/test_regress/t/t_tri_array.py

@@ -0,0 +1,19 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator_st')
+
+test.compile(fails=test.vlt_all, expect_filename=test.golden_filename)
+
+if not test.vlt_all:
+    test.execute()
+
+test.passes()

snapshots/verilator_verilator_pr6870/test_regress/t/t_tri_array.v

@@ -0,0 +1,70 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2014 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer      cyc = 0;
+   reg [63:0]   crc;
+   reg [63:0]   sum;
+
+   parameter NPAD = 4;
+
+   tri          pad [NPAD-1:0];  // Array
+   wire [NPAD-1:0] data0 = crc[0 +: 4];
+   wire [NPAD-1:0] data1 = crc[8 +: 4];
+   wire [NPAD-1:0] en    = crc[16 +: 4];
+
+   for (genvar g=0; g<NPAD; ++g) begin : gpad
+      Pad pad1 (.pad(pad[g]),
+                .ena(en[g]),
+                .data(data1[g]));
+      Pad pad0 (.pad(pad[g]),
+                .ena(!en[g]),
+                .data(data0[g]));
+   end
+
+   // Test loop
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
+`endif
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+      sum <= {60'h0, pad[3], pad[2], pad[1], pad[0]}
+             ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
+      if (cyc==0) begin
+         // Setup
+         crc <= 64'h5aef0c8d_d70a4497;
+         sum <= 64'h0;
+      end
+      else if (cyc<10) begin
+         sum <= 64'h0;
+      end
+      else if (cyc<90) begin
+      end
+      else if (cyc==99) begin
+         $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
+         if (crc !== 64'hc77bb9b3784ea091) $stop;
+         // What checksum will we end up with (above print should match)
+`define EXPECTED_SUM 64'he09fe6f2dfd7a302
+         if (sum !== `EXPECTED_SUM) $stop;
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+
+endmodule
+
+module Pad
+  (inout pad,
+   input ena,
+   input data);
+   assign pad = ena ? data : 1'bz;
+endmodule

snapshots/verilator_verilator_pr6870/test_regress/t/t_tri_array_bufif.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()

snapshots/verilator_verilator_pr6870/test_regress/t/t_tri_array_bufif.v

@@ -0,0 +1,118 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2011 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer      cyc = 0;
+   reg [63:0]   crc;
+   reg [63:0]   sum;
+
+   parameter DW = 4;
+   wire [3:0]  drv_a = crc[3:0];
+   wire [3:0]  drv_b = crc[7:4];
+   wire [3:0]  drv_e = crc[19:16];
+
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire [DW-1:0]        drv;                    // To/From test1 of Test1.v
+   wire [DW-1:0]        drv2;                   // From test2 of Test2.v
+   // End of automatics
+
+   Test1 test1 (/*AUTOINST*/
+                // Inouts
+                .drv                    (drv[DW-1:0]),
+                // Inputs
+                .drv_a                  (drv_a[DW-1:0]),
+                .drv_b                  (drv_b[DW-1:0]),
+                .drv_e                  (drv_e[DW-1:0]));
+   Test2 test2 (/*AUTOINST*/
+                // Outputs
+                .drv2                   (drv2[DW-1:0]),
+                // Inputs
+                .drv_a                  (drv_a[DW-1:0]),
+                .drv_b                  (drv_b[DW-1:0]),
+                .drv_e                  (drv_e[DW-1:0]));
+
+   // Aggregate outputs into a single result vector
+   wire [63:0] result = {60'h0, drv};
+
+   // Test loop
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%x drv=%x %x  (%b??%b:%b)\n", $time, cyc, crc, drv, drv2, drv_e,drv_a,drv_b);
+`endif
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+      sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
+      if (cyc==0) begin
+         // Setup
+         crc <= 64'h5aef0c8d_d70a4497;
+         sum <= 64'h0;
+      end
+      else if (cyc<10) begin
+         sum <= 64'h0;
+      end
+      else if (cyc<90) begin
+         if (drv2 != drv) $stop;
+      end
+      else if (cyc==99) begin
+         $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
+         if (crc !== 64'hc77bb9b3784ea091) $stop;
+         // What checksum will we end up with (above print should match)
+`define EXPECTED_SUM 64'hd95d216c5a2945d0
+         if (sum !== `EXPECTED_SUM) $stop;
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+
+endmodule
+
+module Test1 #(
+  parameter DW = 4
+)(
+  input  wire [DW-1:0] drv_a,
+  input  wire [DW-1:0] drv_b,
+  input  wire [DW-1:0] drv_e,
+  inout  wire [DW-1:0] drv
+);
+
+   wire   drv_0, drv_1, drv_2, drv_3;
+   bufif1 bufa0  (drv_0, drv_a[0],  drv_e[0]);
+   bufif1 bufb0  (drv_0, drv_b[0], ~drv_e[0]);
+   bufif1 bufa1  (drv_1, drv_a[1],  drv_e[1]);
+   bufif1 bufb1  (drv_1, drv_b[1], ~drv_e[1]);
+   bufif1 bufa2  (drv_2, drv_a[2],  drv_e[2]);
+   bufif1 bufb2  (drv_2, drv_b[2], ~drv_e[2]);
+   bufif1
+     bufa3  (drv_3, drv_a[3],  drv_e[3]),
+     bufb3  (drv_3, drv_b[3], ~drv_e[3]);
+   assign drv = {drv_3,drv_2,drv_1,drv_0};
+
+endmodule
+
+module Test2 #(
+  parameter DW = 4
+)(
+  input  wire [DW-1:0] drv_a,
+  input  wire [DW-1:0] drv_b,
+  input  wire [DW-1:0] drv_e,
+  inout  wire [DW-1:0] drv2
+);
+
+   wire [DW-1:0]       drv_all;
+   bufif1 bufa [DW-1:0] (drv_all, drv_a, drv_e);
+   // Below ~= bufif1 bufb [DW-1:0] (drv_all, drv_b, ~drv_e);
+   bufif1 bufb [DW-1:0] ({drv_all[3], drv_all[2], drv_all[1], drv_all[0]},
+                         {drv_b[3], drv_b[2], drv_b[1], drv_b[0]},
+                         {~drv_e[3], ~drv_e[2], ~drv_e[1], ~drv_e[0]});
+   assign drv2 = drv_all;
+
+endmodule

snapshots/verilator_verilator_pr6870/test_regress/t/t_tri_array_pull.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()

snapshots/verilator_verilator_pr6870/test_regress/t/t_tri_array_pull.v

@@ -0,0 +1,44 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2018 by Rod Steward.
+// SPDX-License-Identifier: CC0-1.0
+
+module IOBUF ( input T, input I, output O, inout IO );
+   assign O = IO;
+   assign IO = T ? 1'bz : I;
+endmodule
+
+module t
+  (
+   input [7:0]  inlines,
+   output [7:0] outlines,
+   inout [7:0]  iolines,
+
+   input        inctrl
+   );
+
+   generate for (genvar i = 4; i < 8; i = i+1) begin: Gen_D
+      IOBUF d ( .T(inctrl), .I(inlines[i]), .O(outlines[i]), .IO(iolines[i]) );
+      pullup d_pup (iolines[i]);
+   end
+   endgenerate
+
+   IOBUF d_0 ( .T(inctrl), .I(inlines[0]), .O(outlines[0]), .IO(iolines[0]) );
+   pullup d_0_pup (iolines[0]);
+
+   IOBUF d_1 ( .T(inctrl), .I(inlines[1]), .O(outlines[1]), .IO(iolines[1]) );
+   pullup d_1_pup (iolines[1]);
+
+   IOBUF d_2 ( .T(inctrl), .I(inlines[2]), .O(outlines[2]), .IO(iolines[2]) );
+   pullup d_2_pup (iolines[2]);
+
+   IOBUF d_3 ( .T(inctrl), .I(inlines[3]), .O(outlines[3]), .IO(iolines[3]) );
+   pullup d_3_pup (iolines[3]);
+
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule

snapshots/verilator_verilator_pr6870/test_regress/t/t_tri_compass_bad.out

@@ -0,0 +1,6 @@
+%Error-UNSUPPORTED: t/t_tri_compass_bad.v:16:12: Unsupported: tristate in top-level IO: '__pinNumber1'
+                                               : ... note: In instance 't'
+   16 |    sub sub(i, o);
+      |            ^
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error: Exiting due to

snapshots/verilator_verilator_pr6870/test_regress/t/t_tri_compass_bad.py

@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.lint(fails=True, expect_filename=test.golden_filename)
+
+test.passes()

snapshots/verilator_verilator_pr6870/test_regress/t/t_tri_compass_bad.v

@@ -0,0 +1,21 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2020 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t(/*AUTOARG*/
+   // Outputs
+   o,
+   // Inputs
+   i
+   );
+
+   input i;
+   output o;
+   sub sub(i, o);
+endmodule
+
+module sub(input i, output o);
+   assign o = (i===1'bz) ? 1'b0 : i;
+endmodule

snapshots/verilator_verilator_pr6870/test_regress/t/t_tri_cond_eqcase_with_1.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()

snapshots/verilator_verilator_pr6870/test_regress/t/t_tri_cond_eqcase_with_1.v

@@ -0,0 +1,21 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+   wire  a;
+   assign a = 1 === (clk ? 1 : 1'bz);
+
+   always begin
+      if (!a) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+endmodule

snapshots/verilator_verilator_pr6870/test_regress/t/t_tri_dangle.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute(all_run_flags=['+verilator+rand+reset+0'])
+
+test.passes()

snapshots/verilator_verilator_pr6870/test_regress/t/t_tri_dangle.v

@@ -0,0 +1,35 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2011 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+   // Inouts
+   AVDD, AVSS
+   );
+   inout AVDD;
+   inout  AVSS;
+
+   sub sub (/*AUTOINST*/
+            // Inouts
+            .AVDD                       (AVDD),
+            .AVSS                       (AVSS));
+
+   initial begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+   end
+endmodule
+
+module sub (/*AUTOARG*/
+   // Inouts
+   AVDD, AVSS
+   );
+   // verilator no_inline_module
+   inout AVDD;
+   inout AVSS;
+   tri NON_IO;
+   // +verilator+rand+reset+0 so z will read as zero
+   initial if (NON_IO !== 'z) $stop;
+endmodule

snapshots/verilator_verilator_pr6870/test_regress/t/t_tri_eqcase.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()

snapshots/verilator_verilator_pr6870/test_regress/t/t_tri_eqcase.v

@@ -0,0 +1,129 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2011 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer      cyc = 0;
+   reg [63:0]   crc;
+   reg [63:0]   sum;
+
+   wire [3:0]  drv_a = crc[3:0];
+   wire [3:0]  drv_b = crc[7:4];
+   wire [3:0]  drv_e = crc[19:16];
+
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire [8:0]           match1;                 // From test1 of Test1.v
+   wire [8:0]           match2;                 // From test2 of Test2.v
+   // End of automatics
+
+   Test1 test1 (/*AUTOINST*/
+                // Outputs
+                .match1                 (match1[8:0]),
+                // Inputs
+                .drv_a                  (drv_a[3:0]),
+                .drv_e                  (drv_e[3:0]));
+   Test2 test2 (/*AUTOINST*/
+                // Outputs
+                .match2                 (match2[8:0]),
+                // Inputs
+                .drv_a                  (drv_a[3:0]),
+                .drv_e                  (drv_e[3:0]));
+
+   // Aggregate outputs into a single result vector
+   wire [63:0]          result = {39'h0, match2, 7'h0, match1};
+
+   // Test loop
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%x m1=%x m2=%x  (%b??%b:%b)\n", $time, cyc, crc, match1, match2, drv_e,drv_a,drv_b);
+`endif
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+      sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
+      if (cyc==0) begin
+         // Setup
+         crc <= 64'h5aef0c8d_d70a4497;
+         sum <= 64'h0;
+      end
+      else if (cyc<10) begin
+         sum <= 64'h0;
+      end
+      else if (cyc<90) begin
+      end
+      else if (cyc==99) begin
+         $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
+         if (crc !== 64'hc77bb9b3784ea091) $stop;
+         // What checksum will we end up with (above print should match)
+`define EXPECTED_SUM 64'hc0c4a2b9aea7c4b4
+         if (sum !== `EXPECTED_SUM) $stop;
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+
+endmodule
+
+module Test1
+  (
+   input wire [3:0] drv_a,
+   input wire [3:0] drv_e,
+   output wire [8:0] match1
+   );
+
+   wire [2:1]       drv_all;
+   bufif1 bufa [2:1] (drv_all, drv_a[2:1], drv_e[2:1]);
+
+`ifdef VERILATOR
+   // At present Verilator only allows comparisons with Zs
+   assign match1[0] = (drv_a[2:1]== 2'b00 && drv_e[2:1]==2'b11);
+   assign match1[1] = (drv_a[2:1]== 2'b01 && drv_e[2:1]==2'b11);
+   assign match1[2] = (drv_a[2:1]== 2'b10 && drv_e[2:1]==2'b11);
+   assign match1[3] = (drv_a[2:1]== 2'b11 && drv_e[2:1]==2'b11);
+`else
+   assign match1[0] = drv_all === 2'b00;
+   assign match1[1] = drv_all === 2'b01;
+   assign match1[2] = drv_all === 2'b10;
+   assign match1[3] = drv_all === 2'b11;
+`endif
+   assign match1[4] = drv_all === 2'bz0;
+   assign match1[5] = drv_all === 2'bz1;
+   assign match1[6] = drv_all === 2'bzz;
+   assign match1[7] = drv_all === 2'b0z;
+   assign match1[8] = drv_all === 2'b1z;
+endmodule
+
+module Test2
+  (
+   input wire [3:0] drv_a,
+   input wire [3:0] drv_e,
+   output wire [8:0] match2
+   );
+
+   wire [2:1]       drv_all;
+   bufif1 bufa [2:1] (drv_all, drv_a[2:1], drv_e[2:1]);
+
+`ifdef VERILATOR
+   assign match2[0] = (drv_all !== 2'b00 || drv_e[2:1]!=2'b11);
+   assign match2[1] = (drv_all !== 2'b01 || drv_e[2:1]!=2'b11);
+   assign match2[2] = (drv_all !== 2'b10 || drv_e[2:1]!=2'b11);
+   assign match2[3] = (drv_all !== 2'b11 || drv_e[2:1]!=2'b11);
+`else
+   assign match2[0] = drv_all !== 2'b00;
+   assign match2[1] = drv_all !== 2'b01;
+   assign match2[2] = drv_all !== 2'b10;
+   assign match2[3] = drv_all !== 2'b11;
+`endif
+   assign match2[4] = drv_all !== 2'bz0;
+   assign match2[5] = drv_all !== 2'bz1;
+   assign match2[6] = drv_all !== 2'bzz;
+   assign match2[7] = drv_all !== 2'b0z;
+   assign match2[8] = drv_all !== 2'b1z;
+endmodule

snapshots/verilator_verilator_pr6870/test_regress/t/t_tri_eqcase_input.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()

snapshots/verilator_verilator_pr6870/test_regress/t/t_tri_eqcase_input.v

@@ -0,0 +1,20 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+   wire a = 1'bz === clk;
+
+   always begin
+      if (a) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+endmodule

snapshots/verilator_verilator_pr6870/test_regress/t/t_tri_gate.cpp

@@ -0,0 +1,56 @@
+// -*- mode: C++; c-file-style: "cc-mode" -*-
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2008 by Lane Brooks.
+// SPDX-License-Identifier: CC0-1.0
+
+#include VM_PREFIX_INCLUDE
+
+VM_PREFIX* tb = nullptr;
+
+bool check() {
+    bool pass;
+    int c = (tb->A >> tb->SEL) & 0x1;
+#ifdef TEST_VERBOSE
+    bool verbose = true;
+#else
+    bool verbose = false;
+#endif
+
+    if (tb->W == c && tb->X == c && tb->Y == c && tb->Z == c) {
+        pass = true;
+        if (verbose) printf("-  pass: ");
+    } else {
+        pass = false;
+        verbose = true;
+        printf("%%E-FAIL: ");
+    }
+    if (verbose) {
+        printf("SEL=%d A=%d   got: W=%d X=%d Y=%d Z=%d  exp: WXYZ=%d\n", tb->SEL, tb->A, tb->W,
+               tb->X, tb->Y, tb->Z, c);
+    }
+    return pass;
+}
+
+int main() {
+    Verilated::debug(0);
+    tb = new VM_PREFIX{"tb"};
+
+    // loop through every possibility and check the result
+    bool pass = true;
+    for (tb->SEL = 0; tb->SEL < 2; tb->SEL++) {
+        for (tb->A = 0; tb->A < 4; tb->A++) {
+            tb->eval();
+            if (!check()) pass = false;
+        }
+    }
+
+    if (pass) {
+        VL_PRINTF("*-* All Finished *-*\n");
+        tb->final();
+    } else {
+        vl_fatal(__FILE__, __LINE__, "top", "Unexpected results from tristate test\n");
+    }
+    VL_DO_DANGLING(delete tb, tb);
+    return 0;
+}