Add 13 missing issues and 1 missing patch

.gitattributes

@@ -805,3 +805,4 @@ Repos/HWE/agents/Lingxi/docs/Lingxi[[:space:]]Technical[[:space:]]Report[[:space
 Repos/HWE/agents/Lingxi/docs/Lingxi[[:space:]]v1.5[[:space:]]Technical[[:space:]]Report[[:space:]]200725.pdf filter=lfs diff=lfs merge=lfs -text
 Repos/HWE/agents/Lingxi/docs/Lingxi[[:space:]]v2.0[[:space:]]Technical[[:space:]]Report[[:space:]]2026.pdf filter=lfs diff=lfs merge=lfs -text
 Repos/HWE/agents/Lingxi/imgs/overview_fig.pdf filter=lfs diff=lfs merge=lfs -text
+patches/esa-tu-darmstadt_tapasco_pr105.patch filter=lfs diff=lfs merge=lfs -text

issues/OpenPOWERFoundation_a2o_pr18

@@ -0,0 +1,31 @@
+# Fix uncompliant begin in generate blocks
+
+Instance: OpenPOWERFoundation_a2o_pr18
+Source: https://github.com/OpenPOWERFoundation/a2o/pull/18
+Fetched: 2026-04-26
+Repository: OpenPOWERFoundation/a2o
+Pull request: #18
+Author: flaviens
+State: closed
+Base branch: master
+Head branch: fix_begin_genvar
+Created: 2022-10-26T08:57:01Z
+Updated: 2022-11-30T00:04:25Z
+Closed: 2022-11-30T00:04:25Z
+Merged: 2022-11-30T00:04:25Z
+
+Hi there!
+
+This fixes [this Verilog uncompliance issue](https://github.com/pulp-platform/morty/issues/50).
+
+Thanks!
+Flavien
+
+## Local Reproducer Notes
+
+OpenPOWERFoundation/a2o PR 18 reproducer.
+
+The reduced module keeps the PR's generate-block compliance issue observable
+as a design output while also exercising normal sequential behavior.  The buggy
+snapshot represents an unconditional `generate begin`; the patch changes it to
+the compliant `generate if (1) begin` form and raises the compliance output.

issues/alexforencich_verilog-pcie_pr19

@@ -0,0 +1,40 @@
+# Fix multi-driven net issue when S_RAM_SEL_WIDTH = 0
+
+Instance: alexforencich_verilog-pcie_pr19
+Source: https://github.com/alexforencich/verilog-pcie/pull/19
+Fetched: 2026-04-26
+Repository: alexforencich/verilog-pcie
+Pull request: #19
+Author: Basseuph
+State: closed
+Base branch: master
+Head branch: mle/fix_multi_net_driver
+Created: 2021-12-10T16:52:24Z
+Updated: 2021-12-10T20:56:16Z
+Closed: 2021-12-10T20:47:04Z
+Merged: 2021-12-10T20:47:04Z
+
+## PR Title
+Fix multi-driven net issue when S_RAM_SEL_WIDTH = 0
+
+## PR Description
+As per a discussion on slack we built a corundum design with a single interface and multiple ports and there were actually two issues. One was fixed already, see 3a124837115e51e2273ab7d1c61d80ee01f891c1 in verilog-pcie. A very similar one was still to be fixed and this PR now proposes the respective fix.
+
+The PR adapts the same fix that was already applied to the `dma_ram_demux_rd.v` module to the `dma_ram_demux_wr.v` module.
+
+## PR Comments
+
+**Basseuph** (Dec 10, 2021):
+The submitter's initial message explained the context and referenced a similar fix that had already been applied to the `dma_ram_demux_rd.v` module, noting this PR adapts that same solution to the `dma_ram_demux_wr.v` module.
+
+**alexforencich** (Dec 10, 2021):
+"LGTM" (looks good to me)
+
+**alexforencich** (Dec 10, 2021):
+"dang it, I thought I selected the right option to avoid the merge commit. I guess I need to clean that up..."
+
+**alexforencich** (Dec 10, 2021):
+"I just pulled it directly from your branch; I'll get this merged into Corundum shortly. Also, I recommend adding your MLE email address to your github profile so your commits will link back to your github account."
+
+## Linked Issues
+No linked issues are referenced in this pull request.

issues/chipsalliance_caliptra-rtl_pr757

@@ -0,0 +1,30 @@
+# [RTL] AXI Sub Arb fix. Add recovery inf synchros. Export trace signals. Move SS dbg unlock reg to pwrgood.
+
+Instance: chipsalliance_caliptra-rtl_pr757
+Source: https://github.com/chipsalliance/caliptra-rtl/pull/757
+Fetched: 2026-04-26
+Repository: chipsalliance/caliptra-rtl
+Pull request: #757
+Author: calebofearth
+State: closed
+Base branch: msft-daily-20250226
+Head branch: cwhitehead-msft-axi-sub-fix
+Created: 2025-02-26T06:10:12Z
+Updated: 2025-02-27T07:10:02Z
+Closed: 2025-02-27T07:09:58Z
+Merged: 2025-02-27T07:09:58Z
+
+AXI Sub Arb fix. 
+* Resolves #753 
+
+Add synchronizers to input signals from subsystem recovery interface. 
+Export RISC-V trace signals for debug.
+Move SS dbg unlock level reg to pwrgood so it's sticky and persists across warm resets without having to redo the debug unlock flow.
+
+## Local Reproducer Notes
+
+# chipsalliance_caliptra-rtl_pr757
+
+Minimal fail-to-pass Verilator case for the AXI subordinate arbiter priority fix.
+
+The buggy arbiter does not keep write priority while a held final write beat is still in progress, allowing a later read to steal the component interface. The patch keeps priority for any in-progress transfer.

issues/efabless_clear_pr20

@@ -0,0 +1,27 @@
+# Cocotb updates
+
+Instance: efabless_clear_pr20
+Source: https://github.com/efabless/clear/pull/20
+Fetched: 2026-04-26
+Repository: efabless/clear
+Pull request: #20
+Author: M0stafaRady
+State: closed
+Base branch: RTL-dev
+Head branch: cocotb-dev
+Created: 2023-04-05T10:01:26Z
+Updated: 2023-04-05T10:01:43Z
+Closed: 2023-04-05T10:01:43Z
+Merged: 2023-04-05T10:01:43Z
+
+- Develop script to get the hierarchy of the programming chain 
+- Add test for counter
+
+## Local Reproducer Notes
+
+efabless/clear PR 20 reproducer.
+
+The reduced RTL keeps the GPIO power-on macro touched by the PR and exposes
+the decoded GPIO 3 pull configuration as signals.  The buggy snapshot powers
+GPIO 3 up with the management pulldown setting; the patch changes it to the
+management pullup setting expected by the cocotb update.

issues/hdl-util_hdmi_pr12

@@ -0,0 +1,22 @@
+# Source tweaks for clean compilation on Verilator
+
+Instance: hdl-util_hdmi_pr12
+Source: https://github.com/hdl-util/hdmi/pull/12
+Fetched: 2026-04-26
+Repository: hdl-util/hdmi
+Pull request: #12
+Author: jamesbowman
+State: closed
+Base branch: master
+Head branch: master
+Created: 2020-07-17T20:58:39Z
+Updated: 2020-07-18T01:06:15Z
+Closed: 2020-07-18T01:06:15Z
+Merged: 2020-07-18T01:06:15Z
+
+Hi Sameer, I'm working on a verification testbench for your HDMI code base.
+This first commit makes some small syntax changes to get to clean build with Verilator and Icarus Verilog.
+
+The next steps are:
+ * a testbench that dumps the 3 x 10 bit TMDS values for N clocks
+ * a stream analyzer that verifies HDMI against the spec and the settings

issues/lowRISC_ibex_pr1821

@@ -0,0 +1,31 @@
+# [dv] Add MHPM Counter number param to SpikeCosim
+
+Instance: lowRISC_ibex_pr1821
+Source: https://github.com/lowRISC/ibex/pull/1821
+Fetched: 2026-04-26
+Repository: lowRISC/ibex
+Pull request: #1821
+Author: ctopal
+State: closed
+Base branch: master
+Head branch: mhpmcounter_spikecosim
+Created: 2022-09-28T16:20:26Z
+Updated: 2022-10-11T14:52:49Z
+Closed: 2022-10-11T14:52:42Z
+Merged: 2022-10-11T14:52:42Z
+
+This commit adds another field in SpikeCosim class so that Spike can hardcode the correct event registers.
+
+Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
+
+Needs: https://github.com/lowRISC/riscv-isa-sim/pull/17
+
+Resolves https://github.com/lowRISC/ibex/issues/1820
+
+## Local Reproducer Notes
+
+# lowRISC_ibex_pr1821
+
+Minimal fail-to-pass Verilator case for passing the MHPM counter count into the Spike cosim checker.
+
+The buggy checker ignores the configured MHPM counter count. The patch forwards it to the observable cosim creation configuration.

issues/lowRISC_opentitan_pr28469

@@ -0,0 +1,27 @@
+# [hw,pinmux,rtl] Remove sys reset when no strap sampling
+
+Instance: lowRISC_opentitan_pr28469
+Source: https://github.com/lowRISC/opentitan/pull/28469
+Fetched: 2026-04-26
+Repository: lowRISC/opentitan
+Pull request: #28469
+Author: Razer6
+State: closed
+Base branch: master
+Head branch: pinmux-sys-reset
+Created: 2025-10-11T22:52:30Z
+Updated: 2025-10-13T14:44:34Z
+Closed: 2025-10-13T14:44:33Z
+Merged: 2025-10-13T14:44:33Z
+
+The sys reset in pinmux is only needed for the strap sampling logic. Since that feature is gated behind an ipgen parameter, also gate the reset with this flag and remove it for Darjeeling.
+
+Closes https://github.com/lowRISC/opentitan/issues/25410
+
+## Local Reproducer Notes
+
+# lowRISC_opentitan_pr28469
+
+Minimal fail-to-pass Verilator case for removing the sys reset dependency from pinmux strap sampling.
+
+The buggy pinmux clears the sampled strap when `rst_sys_ni` is asserted low even though strap sampling should only depend on the primary reset. The patch ignores the sys reset for the sampled strap state.

issues/pulp-platform_carfield_pr27

@@ -0,0 +1,48 @@
+# hw: Bump security island
+
+Instance: pulp-platform_carfield_pr27
+Source: https://github.com/pulp-platform/carfield/pull/27
+Fetched: 2026-05-03
+Repository: pulp-platform/carfield
+Pull request: #27
+Author: alex96295
+State: closed
+Base branch: main
+Head branch: aottaviano/synth-fix
+Created: 2023-05-09
+Updated: 2023-07-21
+Closed: 2023-05-09
+Merged: 2023-05-09
+
+## PR Title
+hw: Bump security island
+
+## PR Description
+Remove behavioral string parameters: use combinational ROM and OTP. Fixes #26.
+
+## PR Comments
+
+**alex96295** (May 9, 2023):
+"Remove behavioral string parameters: use combinational ROM and OTP" / "Fixes #26"
+
+**alex96295** (May 9, 2023):
+Added the bug label.
+
+**alex96295** (May 9, 2023):
+Self-assigned the PR.
+
+**alex96295** (May 9, 2023):
+Requested review from luca-valente as code owner.
+
+**alex96295** (May 9, 2023):
+Merged commit 37d82b5 into main.
+
+**micprog** (Jul 21, 2023):
+Deleted the aottaviano/synth-fix branch.
+
+## Linked Issues
+
+**Issue #26: SYNTHESIS ERROR**
+Line 294 and 295 of carfield_pkg generate synthesis errors:
+"Error: ...carfield_pkg.sv:294: The construct 'string' is not supported in synthesis."
+"Error: ...carfield_pkg.sv:295: The construct 'string' is not supported in synthesis."

issues/pulp-platform_cheshire_pr189

@@ -0,0 +1,35 @@
+# hw: Fix uncached SPM execute region
+
+Instance: pulp-platform_cheshire_pr189
+Source: https://github.com/pulp-platform/cheshire/pull/189
+Fetched: 2026-04-26
+Repository: pulp-platform/cheshire
+Pull request: #189
+Author: paulsc96
+State: closed
+Base branch: main
+Head branch: paulsc/spmu-ex
+Created: 2025-03-28T11:57:58Z
+Updated: 2025-04-13T18:42:51Z
+Closed: 2025-04-13T18:42:50Z
+Merged: 2025-04-13T18:42:50Z
+
+Fixes #188.
+
+Changes:
+
+* Add uncached SPM as its own executable region (simplify parameterization a bit in the process)
+* Add a test `spm_uncached` executing from uncached SPM and verifying it is not cached
+
+Additional changes:
+
+* Add argument to DMA calls to enable dynamic use of decoupling flags (this breaks DMA API compatibility)
+* Add `wfi` to default trap handler (this quiets core on exceptions, including on unhandled `ebreak`)
+
+## Local Reproducer Notes
+
+# pulp-platform_cheshire_pr189
+
+Minimal fail-to-pass Verilator case for the uncached SPM execute region fix.
+
+The buggy configuration models cached and uncached SPM as one large executable region. The patch creates an explicit `AmSpmUnc` region and exposes cached and uncached SPM as separate execute rules.

issues/pulp-platform_cheshire_pr203

@@ -0,0 +1,31 @@
+# treewide: Update iDMA and fix 1D transfers
+
+Instance: pulp-platform_cheshire_pr203
+Source: https://github.com/pulp-platform/cheshire/pull/203
+Fetched: 2026-04-26
+Repository: pulp-platform/cheshire
+Pull request: #203
+Author: alex96295
+State: closed
+Base branch: main
+Head branch: aottaviano/dma
+Created: 2025-05-07T12:48:47Z
+Updated: 2025-07-08T20:06:36Z
+Closed: 2025-07-08T20:06:35Z
+Merged: 2025-07-08T20:06:35Z
+
+* [x] Move DMA to Regbus, simplifying interconnect and fixing a known issue with accessing beyond 32-bit boundary
+* [x] Fix DMA HAL for 1D transfers (currently not working)
+* [x] Update iDMA
+* [x] Add new regression test for 1D transfers to CI (https://iis-git.ee.ethz.ch/pulp-restricted/cheshire-nonfree/-/merge_requests/22)
+* [x] Fix #208.
+* [x] Add new regression test for accesses beyond 32-bit boundary (access over serial link)
+
+## Local Reproducer Notes
+
+pulp-platform/cheshire PR 203 reproducer.
+
+The reduced RTL models the 1D DMA programming path through the AXI-to-register
+adapter.  The buggy snapshot instantiates the legacy adapter, which gates a
+valid register write with test mode and drops the one-cycle start command.
+The patch switches the wrapper to the v2 adapter interface used by the PR.

issues/pulp-platform_register_interface_pr23

@@ -0,0 +1,40 @@
+# Add simple error slave
+
+Instance: pulp-platform_register_interface_pr23
+Source: https://github.com/pulp-platform/register_interface/pull/23
+Fetched: 2026-04-26
+Repository: pulp-platform/register_interface
+Pull request: #23
+Author: Vyeow
+State: closed
+Base branch: master
+Head branch: feature/err_slv
+Created: 2022-10-31T14:59:41Z
+Updated: 2022-11-02T08:03:34Z
+Closed: 2022-11-02T08:03:26Z
+Merged: 2022-11-02T08:03:26Z
+
+PR Title: Add simple error slave
+
+PR #23 (Merged November 2, 2022)
+
+Author: Vyeow
+Merged by: meggiman
+
+Description:
+The PR description was minimal. Vyeow noted that "req_i is not needed in the module, but thought it a good idea to keep it for cosmetic reasons."
+
+Review Comments:
+
+meggiman's Initial Feedback (Nov 1, 2022):
+
+1. Metadata files: Contributor requested updates to Bender.yml and src_files.yml to register the error slave module.
+
+2. Type parameter suggestion: Proposed adding a `payload_t` type parameter defaulting to `logic[DW-1:0]` to support packed struct payloads, noting: "the error slave cannot be used as is" without this flexibility.
+
+3. Parameter defaults: Recommended using `-1` as the default for DW to discourage using modules "without explicitly specifying the parameter values."
+
+4. Error value defaults: Suggested changing to `'0` as default, stating users should "explicitly choose which error value they want to return."
+
+Resolution:
+Vyeow implemented the requested changes in a second commit. Meggiman approved with "lgtm. Thanks a lot!" and merged the PR on November 2, 2022, subsequently deleting the feature branch.

issues/taichi-ishitani_tvip-axi_pr36

@@ -0,0 +1,46 @@
+# add null check to avoid null pointer exception
+
+Instance: taichi-ishitani_tvip-axi_pr36
+Source: https://github.com/taichi-ishitani/tvip-axi/pull/36
+Fetched: 2026-05-03
+Repository: taichi-ishitani/tvip-axi
+Pull request: #36
+Author: taichi-ishitani
+State: closed
+Base branch: master
+Head branch: fix_35
+Created: 2022-05-19
+Updated: 2022-05-19
+Closed: 2022-05-19
+Merged: 2022-05-19
+
+## PR Title
+add null check to avoid null pointer exception
+
+## PR Description
+"This PR is to fix #35."
+
+The change adds a null-check guard so that the slave driver does not dereference a null sequence-item handle when it is reset partway through a transaction; the issue had been reported as a NULL pointer dereference in `uvm_transaction::get_event_pool` triggered by `tue_sequence_item_base::get_event` / `ended` being called from `tvip_axi_slave_driver`'s start-delay thread after a mid-transaction reset.
+
+## PR Comments
+**taichi-ishitani** (May 19, 2022): "This PR is to fix #35." (Author/owner; this is the only conversation entry, posted at submission time.)
+
+No code-review comments were posted; the PR was self-merged by taichi-ishitani at commit e2d29ef. The branch `fix_35` was deleted shortly after merge.
+
+## Linked Issues
+**Issue #35 - "Another NULL pointer dereference after reset in the middle"** (closed by this PR).
+
+Issue body (verbatim from the source URL):
+"The latest version has another NULL pointer dereference as below:
+```
+xmsim: *E,TRNULLID: NULL pointer dereference.
+          File: /opt/eda/cadence/XCELIUM2103/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_transaction.svh, line = 521, pos = 14
+         Scope: worklib.uvm_pkg::uvm_transaction::get_event_pool
+          Time: 7134 NS + 13
+Verilog Stack Trace:
+0: function worklib.uvm_pkg::uvm_transaction::get_event_pool at /opt/eda/cadence/XCELIUM2103/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_transaction.svh:521
+1: function worklib.tue_pkg::tue_sequence_item_base#(uvm_pkg::uvm_sequence_item,tvip_axi_pkg::tvip_axi_configuration,tvip_axi_pkg::tvip_axi_status,tvip_axi_pkg::tvip_axi_configuration,tvip_axi_pkg::tvip_axi_status)::get_event at /path/to/tvip-axi/tue/src/seq/tue_sequence_item_base.svh:41
+2: function worklib.tue_pkg::tue_sequence_item_base#(uvm_pkg::uvm_sequence_item,tvip_axi_pkg::tvip_axi_configuration,tvip_axi_pkg::tvip_axi_status,tvip_axi_pkg::tvip_axi_configuration,tvip_axi_pkg::tvip_axi_status)::ended at /path/to/tvip-axi/tue/src/seq/tue_sequence_item_base.svh:51
+3: task worklib.tvip_axi_pkg::tvip_axi_slave_driver_start_delay_consumer@13753_2.delay_thread at /path/to/tvip-axi/src/tvip_axi_slave_driver.svh:66
+4: process in worklib.tvip_axi_pkg::tvip_axi_slave_driver_start_delay_consumer@13753_2.start_delay_thread.unmblk1 at /path/to/tvip-axi/src/tvip_axi_slave_driver.svh:48
+```"

issues/taichi-ishitani_tvip-axi_pr47

@@ -0,0 +1,50 @@
+# Problem with On the Fly Reset  
+
+- Source URL: https://github.com/taichi-ishitani/tvip-axi/issues/46
+
+Hi @taichi-ishitani ! I have a problem when i have reset on AXI.
+In my test I have AXI4 slave and DUT.  
+When i asserted reset the BValid, Bid not reset to zero.  
+The figure below 
+![1_problem](https://user-images.githubusercontent.com/35744340/209571013-9d82fc3e-18c5-40e0-9aba-e40201c0ee53.jpg)
+
+So i find the problem. I think it happened because of race conditions 
+https://github.com/taichi-ishitani/tvip-axi/blob/master/src/tvip_axi_slave_driver.svh#L524
+
+this happened after 
+```
+  protected task drive_response(bit valid, tvip_axi_slave_driver_response_item item);
+    vif.slave_cb.bvalid <= valid;
+    if (valid) begin
+      vif.slave_cb.bid    <= item.get_id();
+      vif.slave_cb.bresp  <= item.get_response_status();
+    end
+  endtask
+```
+This 
+  ```
+protected task reset_if();
+    vif.awready = configuration.default_awready;
+    vif.wready  = configuration.default_wready;
+    vif.bvalid  = '0;
+    vif.bid     = '0;
+    vif.bresp   = tvip_axi_response'(0);
+  endtask
+```
+
+So my decision 
+```
+  protected task drive_response(bit valid, tvip_axi_slave_driver_response_item item);
+    vif.bvalid <= valid;
+    if (valid) begin
+      vif.bid    <= item.get_id();
+      vif.bresp  <= item.get_response_status();
+    end
+  endtask
+```
+I'm not sure, that I understand your logic correctly, but in my case, it's work fine...
+
+![2_solve](https://user-images.githubusercontent.com/35744340/209571584-3d7cae05-5ffe-4947-88bb-d717157fa537.jpg)
+
+
+Best regards.

patches/esa-tu-darmstadt_tapasco_pr105.patch

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:0b6784a99021b65cf2b4bcca09af877b54bbaef11646437ba48efaaf1827b3ad
+size 62362245