Datasets:

PureOne
/

saelqir-m1-executable-weight-memory-v1.0

# Data dictionary and artifact semantics

This release preserves the original SÆLQIR-M1 1.0.0 package under `research/`. Paths below are relative to the repository root. The six CSV configurations contain **240 rows in total**, across unrelated numerical studies with different schemas. They are research records and explicit scenario calculations; they are not one common training table.

| CSV configuration | Frozen file | Rows | Record represents |
|---|---|---:|---|
| `atlas_cases` | `research/results/atlas_cases.csv` | 48 | One constructed four-tile sharing/fallback experiment |
| `roofline_scenarios` | `research/results/roofline_scenarios.csv` | 80 | One assumed model-size/bits/bandwidth/context scenario |
| `kv_accounting` | `research/results/kv_accounting.csv` | 4 | One context length and three explicit KV-cache payload calculations |
| `analog_behavioral` | `research/results/analog_behavioral.csv` | 16 | One ADC-bit/relative-variation surrogate setting, summarized over 30 seeds |
| `mhd_workload` | `research/results/mhd_workload.csv` | 80 | One admissible point in a dimensionless analytic MHD workload |
| `cost_sensitivity` | `research/results/cost_sensitivity.csv` | 12 | One assumed development-cost/production-volume scenario |

The generation code is `research/experiments/run_experiments.py`; numerical model definitions are in `research/src/saelqir/models.py`. These scripts overwrite their output records and figures when run directly. Reproduce in a new copy with `research/reproduce.py` to preserve the frozen source evidence. The original saved reproduction reports all six CSVs byte-identical to its original inputs; that historical report does not authenticate future regenerated files.

## Atlas cases

`atlas_cases.csv` has 12 seeds for each of four families: `identical`, `affine`, `low_rank`, `independent`. Each input has four structured 64×64 weight tiles with four coefficient slots per row. Local tile generation uses `np.random.default_rng(100 * seed + tile_index)`; the study's activation stream uses seed `20261014`.

| Column | Type / unit | Meaning |
|---|---|---|
| `family` | string | Construction family described below |
| `seed` | integer, unitless | Family repetition index, 0–11; not the full RNG initialization value for each tile |
| `joint_rank` | integer, binary dimensions | GF(2) rank of centered active sign patterns across all four tiles |
| `groups` | integer, groups | Number of feasible contiguous groups selected by the serial-cost partitioner |
| `baseline_cycles` | integer, reference cycles | Four separate tiles: 4 × (640 + 14 × 64) = 6,144 |
| `atlas_cycles` | integer, reference cycles | Sum of `640 + 14 × fused_rows` over selected feasible groups |
| `reference_speed_ratio` | float, unitless | `baseline_cycles / atlas_cycles`; a counted-schedule ratio |
| `baseline_frame_bytes` | integer, bytes | Sum of all four complete SLQ1 frames, including each 64-byte header |
| `atlas_frame_bytes` | integer, bytes | Sum of complete SLQ1 frames after exact feasible grouping |
| `exact_equal` | Boolean | Packed operator output equals concatenated original integer outputs for the generated activation vector |

`identical` shares the original column-label map. `affine` applies six-bit cyclic rotations and XOR translations to column labels and rotates character IDs, absorbing translation signs into coefficients. `low_rank` shares labels and masks character IDs with `7`, restricting active characters to three coordinate bits. `independent` retains unrelated generated label maps; excessive joint rank prevents sharing and the partitioner keeps separate feasible groups.

The partitioner enforces rank ≤6 and up to four tiles per group under the selected M1 model. The M1 schedule pads to 64 bins even when rank is lower, so `low_rank` does not automatically obtain a shorter hardware schedule. Bytes are exact format sizes; cycles exclude configuration, host transport, START acceptance and output stalls. These records are CPU arithmetic/representation evidence, not GPU or FPGA measurements.

For four compatible 64-row tiles, 4,352 → 3,968 bytes is **8.823529%** less storage; 6,144 → 4,224 reference cycles is **31.25%** less counted work. The ratio **1.454545** must not be presented as a measured device speedup.

## Roofline scenarios

`roofline_scenarios.csv` covers the Cartesian product of parameter counts `[3, 8, 14, 32, 70] × 10^9`, bits per weight `[4, 2]`, peak bandwidth `[64, 128, 256, 512] GB/s`, and contexts `[4096, 32768]`: **5 × 2 × 4 × 2 = 80 rows**.

| Column | Type / unit | Meaning |
|---|---|---|
| `parameters` | integer, parameters | Assumed dense model parameter count |
| `bits` | integer, bits/weight | Assumed stored weight payload precision |
| `bandwidth_gbs` | integer, decimal GB/s | Assumed peak bandwidth; 1 GB = 10^9 bytes |
| `context` | integer, tokens | Assumed context used for KV payload calculation |
| `all_rates_assumed` | Boolean | Always true: hardware rates in this study are assumptions |
| `weight_bytes` | float, bytes | `parameters × bits / 8` |
| `traffic_bytes` | float, bytes/step | Weight bytes plus assumed full KV payload traffic for the batch |
| `memory_ms` | float, milliseconds/step | Traffic divided by assumed effective bandwidth |
| `compute_ms` | float, milliseconds/step | Assumed `2 × parameters × batch` operations divided by assumed compute rate |
| `step_ms` | float, milliseconds/step | Larger of memory and compute times, plus fixed overhead |
| `per_sequence_tps` | float, tokens/second | Inverse of step time in seconds |
| `aggregate_tps` | float, tokens/second | Batch divided by step time in seconds |

For each shipped row, `batch = 1`, bandwidth efficiency `η = 0.65`, compute rate `C = 40 × 10^12` operations/s and fixed overhead `f = 0.001 s`. KV inputs are 32 layers, 8 KV heads, head dimension 128, 16 bits per value. With `P` parameters, `b` weight bits, peak bandwidth `B` in GB/s and KV payload `K`:

```text
W = P × b / 8
traffic = W + batch × K
t_memory = traffic / (B × 10^9 × 0.65)
t_compute = 2 × P × batch / (40 × 10^12)
t_step = max(t_memory, t_compute) + 0.001
per_sequence_tps = 1 / t_step
aggregate_tps = batch / t_step
```

The full KV payload term is an explicit simplified traffic assumption. This model does not establish real attention traffic, cache reuse, weight residency, parallelism, operator coverage, M1 integration speed or full-model quality. Weight payload omits actual model file metadata and representation overhead. The 2-bit rows do not claim that SÆLQIR-M1 successfully compresses an arbitrary model to 2 bits. No hardware benchmark was used to fit these rates.

## KV accounting

`kv_accounting.csv` evaluates contexts `[4096, 8192, 32768, 131072]`, batch 1, 32 layers and head dimension 128.

| Column | Type / unit | Meaning |
|---|---|---|
| `context` | integer, tokens | Number of stored context positions |
| `kv_fp16_bytes` | float, bytes | Grouped-query KV payload: 8 KV heads, 16 bits/value |
| `kv_int8_bytes` | float, bytes | Same 8 KV heads, assumed 8 bits/value |
| `kv_mha_fp16_bytes` | float, bytes | Multi-head KV payload: 32 KV heads, 16 bits/value |

The exact payload formula is:

```text
KV bytes = 2 × layers × KV_heads × head_dimension × context × (bits / 8) × batch
```

The factor 2 represents keys and values. The formula excludes allocator, alignment, scales, quantization metadata, page tables and activation workspace. `kv_int8_bytes` is a payload calculation, not validated KV quantization quality. For 32,768 tokens, the 16-bit/8-head payload is **4,294,967,296 bytes = 4 GiB**; weight compression does not remove it.

## Analog behavioral study

`analog_behavioral.csv` covers ADC bits `[6, 8, 10, 12]` and relative weight noise standard deviations `[0, 0.001, 0.01, 0.03]`: **16 rows**. Each row summarizes 30 variation seeds, 0–29. A single generated 64×64 integer matrix has entries in `[-7, 7]`; its generated 64-entry activation vector has entries in `[-127, 127]`. They come from the study RNG stream seeded `20261014` after the atlas activation draws.

| Column | Type / unit | Meaning |
|---|---|---|
| `adc_bits` | integer, bits | Assumed uniform output quantizer resolution |
| `relative_weight_sigma` | float, unitless | Standard deviation of independent multiplicative Gaussian variation |
| `relative_l2_mean` | float, unitless | Mean of 30 relative vector errors |
| `relative_l2_max` | float, unitless | Largest of those 30 relative vector errors |
| `simulation_only` | Boolean | Always true: behavioral surrogate, no physical device measurement |

For ideal `y₀ = W x`, the surrogate computes:

```text
W_noisy = W × (1 + Normal(0, sigma))     # independent elementwise variation
y = W_noisy x
F = max_row(sum(abs(W))) × max(1, max(abs(x)))
delta = 2 × F / (2^adc_bits − 1)
y_quantized = clip(round(y / delta) × delta, −F, F)
relative_error = norm(y_quantized − y₀, 2) / norm(y₀, 2)
```

The code applies NumPy's rounding behavior. Even sigma zero retains quantization error. No semiconductor parameters, cell programming, retention, drift, interconnect effects, input converters, actual ADC transfer curve, PVT variation or calibrated energy model are represented. These values cannot establish analog chip accuracy or efficiency.

## MHD numerical workload

`mhd_workload.csv` evaluates five `tau` values `[-0.5, -0.25, 0, 0.25, 0.5]` and 16 equally spaced angles in `[0, 2π)`: **80 rows**. This is an analytic scientific workload drawn from the supplied Issan et al. paper, *Analytic non-axisymmetric 3D MHD equilibria without stellarator symmetry*; it is unrelated to SRAM device physics.

| Column | Type / unit | Meaning |
|---|---|---|
| `tau` | float, dimensionless | Analytic equilibrium parameter |
| `phi` | float, radians | Angular sample coordinate |
| `divergence_abs` | float, dimensionless residual | Absolute divergence of the normalized analytic magnetic field |
| `tension_gradient_residual` | float, dimensionless residual | Euclidean norm of `J B + grad(Q)` |

The study fixes `epsilon = 0.5` and evaluates points:

```text
p(phi) = (sqrt(1.5) cos(phi), sqrt(0.5) sin(phi), 0.01)
```

For `a = sqrt(1 + epsilon)`, `b = sqrt(1 − epsilon)`, coordinates `(x,y,z)` and `s = x²/a² + y²/b²`:

```text
F = sqrt(1 − (1 − s)² − 4z² − 4 tau s z)
B_x = ((2z + tau s)x − a F y / b) / s
B_y = ((2z + tau s)y + b F x / a) / s
B_z = 1 − s − 2 tau z
Q = (1 − tau²)(x² + y² + 4z²)/2 + 2 tau z
```

The Jacobian `J` and gradient of `Q` are evaluated using complex-step differentiation with step `10^-25`. Records are `abs(trace(J))` and `norm(J @ B + grad(Q), 2)`. The script requires both maxima below `10^-12`; frozen maxima are approximately **4.4408921 × 10^-16** and **5.7955343 × 10^-16**. These are floating-point numerical identity checks, not physical measurements or independent validation of a memory chip.

## Cost sensitivity

`cost_sensitivity.csv` covers assumed development costs `[2, 10, 30] million USD` and production volumes `[1,000, 10,000, 100,000, 1,000,000]`: **12 rows**.

| Column | Type / unit | Meaning |
|---|---|---|
| `nre_usd_assumption` | integer, USD | Assumed nonrecurring development expenditure |
| `units_assumption` | integer, units | Assumed produced/sold volume |
| `nre_per_unit_usd` | float, USD/unit | Development expenditure divided by volume |
| `base_bom_usd_assumption` | integer, USD/unit | Fixed assumed base bill of materials, 350 |
| `burden_usd_assumption` | integer, USD/unit | Fixed assumed additional unit burden, 70 |
| `gross_margin_assumption` | float, fraction | Assumed gross margin, 0.3 |
| `needed_price_ex_tax_usd` | float, USD/unit | Illustrative required sale price before tax |

```text
nre_per_unit = nre / units
needed_price_ex_tax = (350 + 70 + nre_per_unit) / (1 − 0.30)
```

These are unquoted scenarios, not a production BOM, commercial offer, currency conversion or market forecast. Actual yield, licensing, logistics, warranty and development scope may change the inputs. The separate FPGA equipment planning range in `research/hardware/bom_planning.csv` is **US$508–999** and excludes labor, tax, shipping, proprietary tools and a new host computer; it is not the price of an integrated AI PC.

## Small digit model and protocol

The release includes newly trained small-model parameters and records needed to replay its packed first layer. It does **not** rehost the underlying handwritten-digit training dataset. Scripts load `sklearn.datasets.load_digits()` from the user's installed scikit-learn distribution; the original dataset and distribution retain their own attribution and terms.

The protocol in `research/results/digits_protocol.json` records seed **20261014**, **120 epochs**, learning rate **0.008**, 1,257 training indices, 270 calibration indices and 270 test indices. Splits are stratified, disjoint and total 1,797 source examples. The architecture is **64 inputs → 256 four-character hidden rows → ReLU → 10-class dense head**. Character IDs are selected before training, four distinct IDs per row. Training uses Adam with weight decay `10^-5`, batches of 128, and one CPU thread. Only the first operator is M1 eligible; the dense classification head remains ordinary arithmetic.

The dataset checksum is SHA-256 of concatenated little-endian signed int64 bytes for all source input features and labels:

```text
267f86e03ae0481efa68bbcf4dcd04133dbc88a3145b0551cb2221500a4881e0
```

Replay checks this hash before using saved split indices. The frozen parameters are architecture-trained, not an arbitrary pretrained LLM export. Optional retraining on the published split is replication, not a fresh holdout experiment.

| Artifact | Contents and semantics |
|---|---|
| `research/examples/digits_first_layer.slq` | Complete **3,968-byte SLQ1** frame: 64 inputs, 256 output rows, four coefficient slots/row, rank 6, coefficient fraction 14 and epoch 1. Coefficients are signed int16. Integer output is scaled by `2^-14` before hidden bias/ReLU. |
| `research/examples/digits_head.npz` | NumPy archive, loaded with `allow_pickle=False`: float32 `hidden_bias` shape `(256,)`, float32 `head_weight` shape `(10,256)`, float32 `head_bias` shape `(10,)`. Raw array payload totals **11,304 bytes**; archive headers are additional bytes. |
| `research/examples/digits_float_reference.npz` | Float32 pre-atlas `coeff` shape `(256,4)`, int64 `ids` shape `(256,4)`, and the same float32 biases/head arrays. Coefficients already include the training feature normalization factor `1/128`. Integer reconstruction is `round(coeff × 2^14)`. IDs select parity-character rows. |
| `research/results/digits_results.json` | Calibration/test accuracy, count, negative log-likelihood, format-byte accounting, atlas metadata and sparse training-history entries. `float32_reference` refers to FP32-trained parameters evaluated in NumPy float64, not native FP32 GPU execution. |
| `research/results/frozen_digits_replay.json` | Historical no-retraining replay: **270/270 exact integer vectors**, **263/270** correct classifications, dataset/frame hashes. New replay writes its own report under `build/`. |

The integer/atlas test accuracy is **97.4074%**, with NLL **0.09329479381719989**. The scalar INT4 comparator gets **264/270** correct (**97.7778%**) but NLL **0.11741103957092583**. Preserve both metrics; the experiment does not establish general model-quality superiority. The scalar comparator is a global-scale baseline reconstructed in the training script; it is distinct from the generic per-row-gain D4 fixture path.

Atlas metadata records **1,024 coefficient slots**, of which **45 are zero**, exact finite-field factorization and four source tiles. The packed first-layer ratio is **1.9375 bits per represented first-layer weight**, including its complete frame. It is not a whole-model bits-per-weight figure. Whole-model accounting must also include the unchanged head/bias arrays and any container metadata. The pre-atlas references allow an independent integer matrix to be reconstructed instead of trusting the fused frame alone.

## Binary arithmetic fixtures

`research/examples/vectors/` contains six FORK fixture sets; `research/examples/d4_vectors/` contains six generic D4 sets. Case indices 0–5 have output row counts **1, 4, 16, 64, 128, 256** respectively.

| Suffix | Binary contract |
|---|---|
| `.slq` | SLQ1 structured operator frame; 64-byte little-endian header, labels, counts, row offsets, character IDs and signed int16 coefficients |
| `.d4q` | D4Q1 generic INT4 frame; 64-byte header, signed int16 per-row gains and packed signed four-bit weights |
| `.x8` | Exactly 64 signed INT8 activations in input order; no header |
| `.expected.i64` | One little-endian signed int64 expected integer output per row; no header |

SLQ1 complete length is `64 + columns + 3 × rows + 3 × rows × terms`; with 64 columns/four terms this is `128 + 15 × rows`. D4Q1 complete length is `64 + 34 × rows`. D4 fixture outputs are `gain × (INT4_weights @ INT8_input)`. Case 0 deliberately uses signed extremes: weight −8, gain −32,768, activation −128.

`research/experiments/native_check.py` regenerates the FORK vectors with seed `20261014`, compiles the independent C++ state machine and compares six fixture sets at stall periods 0, 3 and 7, yielding **18 cases**. It also checks rejection of one corrupted frame. `research/experiments/d4_check.py` regenerates six D4 sets and compares an independently compiled C++ arithmetic reference. Neither check executes the supplied SystemVerilog.

The frames include CRC32 error detection for header/payload; CRC does not authenticate untrusted operators. Reserved fields and dimensions are checked by the decoders. Framing is specific to this release and is not Transformers, GGUF or the original quantization manuscript's EESAF format.

## Provenance and evidence boundaries

The original source release is authenticated by its nested `research/MANIFEST.json` and verified with `python research/verify_release.py`. Its hash verification covers 153 files; the manifest itself and `SHA256SUMS.txt` are excluded from recursive self-hashing. Release-preparation additions have their own outer manifest and must not be confused with the original frozen research results.

The four supplied source manuscripts are identified by filenames/hashes in `research/provenance/inputs.json`; their original PDFs are not bundled. The user-supplied architecture illustration is retained with the existing rights/provenance notice and is embedded in the preserved original manuscript. This release does not grant third-party image, paper, dataset, tool, vendor or patent rights. Consult `research/LICENSE_NOTICE.md` before public redistribution.

No saved CSV, small-model file or CPU fixture establishes HDL simulation, synthesis, timing closure, FPGA measurement, ASIC fabrication, GPU superiority, modern-LLM deployment quality, calibrated success probability or a finished integrated computer. Those remain future validation stages.

	# Data dictionary and artifact semantics

	This release preserves the original SÆLQIR-M1 1.0.0 package under `research/`. Paths below are relative to the repository root. The six CSV configurations contain 240 rows in total, across unrelated numerical studies with different schemas. They are research records and explicit scenario calculations; they are not one common training table.

	\| CSV configuration \| Frozen file \| Rows \| Record represents \|
	\|---\|---\|---:\|---\|
	\| `atlas_cases` \| `research/results/atlas_cases.csv` \| 48 \| One constructed four-tile sharing/fallback experiment \|
	\| `roofline_scenarios` \| `research/results/roofline_scenarios.csv` \| 80 \| One assumed model-size/bits/bandwidth/context scenario \|
	\| `kv_accounting` \| `research/results/kv_accounting.csv` \| 4 \| One context length and three explicit KV-cache payload calculations \|
	\| `analog_behavioral` \| `research/results/analog_behavioral.csv` \| 16 \| One ADC-bit/relative-variation surrogate setting, summarized over 30 seeds \|
	\| `mhd_workload` \| `research/results/mhd_workload.csv` \| 80 \| One admissible point in a dimensionless analytic MHD workload \|
	\| `cost_sensitivity` \| `research/results/cost_sensitivity.csv` \| 12 \| One assumed development-cost/production-volume scenario \|

	The generation code is `research/experiments/run_experiments.py`; numerical model definitions are in `research/src/saelqir/models.py`. These scripts overwrite their output records and figures when run directly. Reproduce in a new copy with `research/reproduce.py` to preserve the frozen source evidence. The original saved reproduction reports all six CSVs byte-identical to its original inputs; that historical report does not authenticate future regenerated files.

	## Atlas cases

	`atlas_cases.csv` has 12 seeds for each of four families: `identical`, `affine`, `low_rank`, `independent`. Each input has four structured 64×64 weight tiles with four coefficient slots per row. Local tile generation uses `np.random.default_rng(100 * seed + tile_index)`; the study's activation stream uses seed `20261014`.

	\| Column \| Type / unit \| Meaning \|
	\|---\|---\|---\|
	\| `family` \| string \| Construction family described below \|
	\| `seed` \| integer, unitless \| Family repetition index, 0–11; not the full RNG initialization value for each tile \|
	\| `joint_rank` \| integer, binary dimensions \| GF(2) rank of centered active sign patterns across all four tiles \|
	\| `groups` \| integer, groups \| Number of feasible contiguous groups selected by the serial-cost partitioner \|
	\| `baseline_cycles` \| integer, reference cycles \| Four separate tiles: 4 × (640 + 14 × 64) = 6,144 \|
	\| `atlas_cycles` \| integer, reference cycles \| Sum of `640 + 14 × fused_rows` over selected feasible groups \|
	\| `reference_speed_ratio` \| float, unitless \| `baseline_cycles / atlas_cycles`; a counted-schedule ratio \|
	\| `baseline_frame_bytes` \| integer, bytes \| Sum of all four complete SLQ1 frames, including each 64-byte header \|
	\| `atlas_frame_bytes` \| integer, bytes \| Sum of complete SLQ1 frames after exact feasible grouping \|
	\| `exact_equal` \| Boolean \| Packed operator output equals concatenated original integer outputs for the generated activation vector \|

	`identical` shares the original column-label map. `affine` applies six-bit cyclic rotations and XOR translations to column labels and rotates character IDs, absorbing translation signs into coefficients. `low_rank` shares labels and masks character IDs with `7`, restricting active characters to three coordinate bits. `independent` retains unrelated generated label maps; excessive joint rank prevents sharing and the partitioner keeps separate feasible groups.

	The partitioner enforces rank ≤6 and up to four tiles per group under the selected M1 model. The M1 schedule pads to 64 bins even when rank is lower, so `low_rank` does not automatically obtain a shorter hardware schedule. Bytes are exact format sizes; cycles exclude configuration, host transport, START acceptance and output stalls. These records are CPU arithmetic/representation evidence, not GPU or FPGA measurements.

	For four compatible 64-row tiles, 4,352 → 3,968 bytes is 8.823529% less storage; 6,144 → 4,224 reference cycles is 31.25% less counted work. The ratio 1.454545 must not be presented as a measured device speedup.

	## Roofline scenarios

	`roofline_scenarios.csv` covers the Cartesian product of parameter counts `[3, 8, 14, 32, 70] × 10^9`, bits per weight `[4, 2]`, peak bandwidth `[64, 128, 256, 512] GB/s`, and contexts `[4096, 32768]`: 5 × 2 × 4 × 2 = 80 rows.

	\| Column \| Type / unit \| Meaning \|
	\|---\|---\|---\|
	\| `parameters` \| integer, parameters \| Assumed dense model parameter count \|
	\| `bits` \| integer, bits/weight \| Assumed stored weight payload precision \|
	\| `bandwidth_gbs` \| integer, decimal GB/s \| Assumed peak bandwidth; 1 GB = 10^9 bytes \|
	\| `context` \| integer, tokens \| Assumed context used for KV payload calculation \|
	\| `all_rates_assumed` \| Boolean \| Always true: hardware rates in this study are assumptions \|
	\| `weight_bytes` \| float, bytes \| `parameters × bits / 8` \|
	\| `traffic_bytes` \| float, bytes/step \| Weight bytes plus assumed full KV payload traffic for the batch \|
	\| `memory_ms` \| float, milliseconds/step \| Traffic divided by assumed effective bandwidth \|
	\| `compute_ms` \| float, milliseconds/step \| Assumed `2 × parameters × batch` operations divided by assumed compute rate \|
	\| `step_ms` \| float, milliseconds/step \| Larger of memory and compute times, plus fixed overhead \|
	\| `per_sequence_tps` \| float, tokens/second \| Inverse of step time in seconds \|
	\| `aggregate_tps` \| float, tokens/second \| Batch divided by step time in seconds \|

	For each shipped row, `batch = 1`, bandwidth efficiency `η = 0.65`, compute rate `C = 40 × 10^12` operations/s and fixed overhead `f = 0.001 s`. KV inputs are 32 layers, 8 KV heads, head dimension 128, 16 bits per value. With `P` parameters, `b` weight bits, peak bandwidth `B` in GB/s and KV payload `K`:

	```text
	W = P × b / 8
	traffic = W + batch × K
	t_memory = traffic / (B × 10^9 × 0.65)
	t_compute = 2 × P × batch / (40 × 10^12)
	t_step = max(t_memory, t_compute) + 0.001
	per_sequence_tps = 1 / t_step
	aggregate_tps = batch / t_step
	```

	The full KV payload term is an explicit simplified traffic assumption. This model does not establish real attention traffic, cache reuse, weight residency, parallelism, operator coverage, M1 integration speed or full-model quality. Weight payload omits actual model file metadata and representation overhead. The 2-bit rows do not claim that SÆLQIR-M1 successfully compresses an arbitrary model to 2 bits. No hardware benchmark was used to fit these rates.

	## KV accounting

	`kv_accounting.csv` evaluates contexts `[4096, 8192, 32768, 131072]`, batch 1, 32 layers and head dimension 128.

	\| Column \| Type / unit \| Meaning \|
	\|---\|---\|---\|
	\| `context` \| integer, tokens \| Number of stored context positions \|
	\| `kv_fp16_bytes` \| float, bytes \| Grouped-query KV payload: 8 KV heads, 16 bits/value \|
	\| `kv_int8_bytes` \| float, bytes \| Same 8 KV heads, assumed 8 bits/value \|
	\| `kv_mha_fp16_bytes` \| float, bytes \| Multi-head KV payload: 32 KV heads, 16 bits/value \|

	The exact payload formula is:

	```text
	KV bytes = 2 × layers × KV_heads × head_dimension × context × (bits / 8) × batch
	```

	The factor 2 represents keys and values. The formula excludes allocator, alignment, scales, quantization metadata, page tables and activation workspace. `kv_int8_bytes` is a payload calculation, not validated KV quantization quality. For 32,768 tokens, the 16-bit/8-head payload is 4,294,967,296 bytes = 4 GiB; weight compression does not remove it.

	## Analog behavioral study

	`analog_behavioral.csv` covers ADC bits `[6, 8, 10, 12]` and relative weight noise standard deviations `[0, 0.001, 0.01, 0.03]`: 16 rows. Each row summarizes 30 variation seeds, 0–29. A single generated 64×64 integer matrix has entries in `[-7, 7]`; its generated 64-entry activation vector has entries in `[-127, 127]`. They come from the study RNG stream seeded `20261014` after the atlas activation draws.

	\| Column \| Type / unit \| Meaning \|
	\|---\|---\|---\|
	\| `adc_bits` \| integer, bits \| Assumed uniform output quantizer resolution \|
	\| `relative_weight_sigma` \| float, unitless \| Standard deviation of independent multiplicative Gaussian variation \|
	\| `relative_l2_mean` \| float, unitless \| Mean of 30 relative vector errors \|
	\| `relative_l2_max` \| float, unitless \| Largest of those 30 relative vector errors \|
	\| `simulation_only` \| Boolean \| Always true: behavioral surrogate, no physical device measurement \|

	For ideal `y₀ = W x`, the surrogate computes:

	```text
	W_noisy = W × (1 + Normal(0, sigma)) # independent elementwise variation
	y = W_noisy x
	F = max_row(sum(abs(W))) × max(1, max(abs(x)))
	delta = 2 × F / (2^adc_bits − 1)
	y_quantized = clip(round(y / delta) × delta, −F, F)
	relative_error = norm(y_quantized − y₀, 2) / norm(y₀, 2)
	```

	The code applies NumPy's rounding behavior. Even sigma zero retains quantization error. No semiconductor parameters, cell programming, retention, drift, interconnect effects, input converters, actual ADC transfer curve, PVT variation or calibrated energy model are represented. These values cannot establish analog chip accuracy or efficiency.

	## MHD numerical workload

	`mhd_workload.csv` evaluates five `tau` values `[-0.5, -0.25, 0, 0.25, 0.5]` and 16 equally spaced angles in `[0, 2π)`: 80 rows. This is an analytic scientific workload drawn from the supplied Issan et al. paper, Analytic non-axisymmetric 3D MHD equilibria without stellarator symmetry; it is unrelated to SRAM device physics.

	\| Column \| Type / unit \| Meaning \|
	\|---\|---\|---\|
	\| `tau` \| float, dimensionless \| Analytic equilibrium parameter \|
	\| `phi` \| float, radians \| Angular sample coordinate \|
	\| `divergence_abs` \| float, dimensionless residual \| Absolute divergence of the normalized analytic magnetic field \|
	\| `tension_gradient_residual` \| float, dimensionless residual \| Euclidean norm of `J B + grad(Q)` \|

	The study fixes `epsilon = 0.5` and evaluates points:

	```text
	p(phi) = (sqrt(1.5) cos(phi), sqrt(0.5) sin(phi), 0.01)
	```

	For `a = sqrt(1 + epsilon)`, `b = sqrt(1 − epsilon)`, coordinates `(x,y,z)` and `s = x²/a² + y²/b²`:

	```text
	F = sqrt(1 − (1 − s)² − 4z² − 4 tau s z)
	B_x = ((2z + tau s)x − a F y / b) / s
	B_y = ((2z + tau s)y + b F x / a) / s
	B_z = 1 − s − 2 tau z
	Q = (1 − tau²)(x² + y² + 4z²)/2 + 2 tau z
	```

	The Jacobian `J` and gradient of `Q` are evaluated using complex-step differentiation with step `10^-25`. Records are `abs(trace(J))` and `norm(J @ B + grad(Q), 2)`. The script requires both maxima below `10^-12`; frozen maxima are approximately 4.4408921 × 10^-16 and 5.7955343 × 10^-16. These are floating-point numerical identity checks, not physical measurements or independent validation of a memory chip.

	## Cost sensitivity

	`cost_sensitivity.csv` covers assumed development costs `[2, 10, 30] million USD` and production volumes `[1,000, 10,000, 100,000, 1,000,000]`: 12 rows.

	\| Column \| Type / unit \| Meaning \|
	\|---\|---\|---\|
	\| `nre_usd_assumption` \| integer, USD \| Assumed nonrecurring development expenditure \|
	\| `units_assumption` \| integer, units \| Assumed produced/sold volume \|
	\| `nre_per_unit_usd` \| float, USD/unit \| Development expenditure divided by volume \|
	\| `base_bom_usd_assumption` \| integer, USD/unit \| Fixed assumed base bill of materials, 350 \|
	\| `burden_usd_assumption` \| integer, USD/unit \| Fixed assumed additional unit burden, 70 \|
	\| `gross_margin_assumption` \| float, fraction \| Assumed gross margin, 0.3 \|
	\| `needed_price_ex_tax_usd` \| float, USD/unit \| Illustrative required sale price before tax \|

	```text
	nre_per_unit = nre / units
	needed_price_ex_tax = (350 + 70 + nre_per_unit) / (1 − 0.30)
	```

	These are unquoted scenarios, not a production BOM, commercial offer, currency conversion or market forecast. Actual yield, licensing, logistics, warranty and development scope may change the inputs. The separate FPGA equipment planning range in `research/hardware/bom_planning.csv` is US$508–999 and excludes labor, tax, shipping, proprietary tools and a new host computer; it is not the price of an integrated AI PC.

	## Small digit model and protocol

	The release includes newly trained small-model parameters and records needed to replay its packed first layer. It does not rehost the underlying handwritten-digit training dataset. Scripts load `sklearn.datasets.load_digits()` from the user's installed scikit-learn distribution; the original dataset and distribution retain their own attribution and terms.

	The protocol in `research/results/digits_protocol.json` records seed 20261014, 120 epochs, learning rate 0.008, 1,257 training indices, 270 calibration indices and 270 test indices. Splits are stratified, disjoint and total 1,797 source examples. The architecture is 64 inputs → 256 four-character hidden rows → ReLU → 10-class dense head. Character IDs are selected before training, four distinct IDs per row. Training uses Adam with weight decay `10^-5`, batches of 128, and one CPU thread. Only the first operator is M1 eligible; the dense classification head remains ordinary arithmetic.

	The dataset checksum is SHA-256 of concatenated little-endian signed int64 bytes for all source input features and labels:

	```text
	267f86e03ae0481efa68bbcf4dcd04133dbc88a3145b0551cb2221500a4881e0
	```

	Replay checks this hash before using saved split indices. The frozen parameters are architecture-trained, not an arbitrary pretrained LLM export. Optional retraining on the published split is replication, not a fresh holdout experiment.

	\| Artifact \| Contents and semantics \|
	\|---\|---\|
	\| `research/examples/digits_first_layer.slq` \| Complete 3,968-byte SLQ1 frame: 64 inputs, 256 output rows, four coefficient slots/row, rank 6, coefficient fraction 14 and epoch 1. Coefficients are signed int16. Integer output is scaled by `2^-14` before hidden bias/ReLU. \|
	\| `research/examples/digits_head.npz` \| NumPy archive, loaded with `allow_pickle=False`: float32 `hidden_bias` shape `(256,)`, float32 `head_weight` shape `(10,256)`, float32 `head_bias` shape `(10,)`. Raw array payload totals 11,304 bytes; archive headers are additional bytes. \|
	\| `research/examples/digits_float_reference.npz` \| Float32 pre-atlas `coeff` shape `(256,4)`, int64 `ids` shape `(256,4)`, and the same float32 biases/head arrays. Coefficients already include the training feature normalization factor `1/128`. Integer reconstruction is `round(coeff × 2^14)`. IDs select parity-character rows. \|
	\| `research/results/digits_results.json` \| Calibration/test accuracy, count, negative log-likelihood, format-byte accounting, atlas metadata and sparse training-history entries. `float32_reference` refers to FP32-trained parameters evaluated in NumPy float64, not native FP32 GPU execution. \|
	\| `research/results/frozen_digits_replay.json` \| Historical no-retraining replay: 270/270 exact integer vectors, 263/270 correct classifications, dataset/frame hashes. New replay writes its own report under `build/`. \|

	The integer/atlas test accuracy is 97.4074%, with NLL 0.09329479381719989. The scalar INT4 comparator gets 264/270 correct (97.7778%) but NLL 0.11741103957092583. Preserve both metrics; the experiment does not establish general model-quality superiority. The scalar comparator is a global-scale baseline reconstructed in the training script; it is distinct from the generic per-row-gain D4 fixture path.

	Atlas metadata records 1,024 coefficient slots, of which 45 are zero, exact finite-field factorization and four source tiles. The packed first-layer ratio is 1.9375 bits per represented first-layer weight, including its complete frame. It is not a whole-model bits-per-weight figure. Whole-model accounting must also include the unchanged head/bias arrays and any container metadata. The pre-atlas references allow an independent integer matrix to be reconstructed instead of trusting the fused frame alone.

	## Binary arithmetic fixtures

	`research/examples/vectors/` contains six FORK fixture sets; `research/examples/d4_vectors/` contains six generic D4 sets. Case indices 0–5 have output row counts 1, 4, 16, 64, 128, 256 respectively.

	\| Suffix \| Binary contract \|
	\|---\|---\|
	\| `.slq` \| SLQ1 structured operator frame; 64-byte little-endian header, labels, counts, row offsets, character IDs and signed int16 coefficients \|
	\| `.d4q` \| D4Q1 generic INT4 frame; 64-byte header, signed int16 per-row gains and packed signed four-bit weights \|
	\| `.x8` \| Exactly 64 signed INT8 activations in input order; no header \|
	\| `.expected.i64` \| One little-endian signed int64 expected integer output per row; no header \|

	SLQ1 complete length is `64 + columns + 3 × rows + 3 × rows × terms`; with 64 columns/four terms this is `128 + 15 × rows`. D4Q1 complete length is `64 + 34 × rows`. D4 fixture outputs are `gain × (INT4_weights @ INT8_input)`. Case 0 deliberately uses signed extremes: weight −8, gain −32,768, activation −128.

	`research/experiments/native_check.py` regenerates the FORK vectors with seed `20261014`, compiles the independent C++ state machine and compares six fixture sets at stall periods 0, 3 and 7, yielding 18 cases. It also checks rejection of one corrupted frame. `research/experiments/d4_check.py` regenerates six D4 sets and compares an independently compiled C++ arithmetic reference. Neither check executes the supplied SystemVerilog.

	The frames include CRC32 error detection for header/payload; CRC does not authenticate untrusted operators. Reserved fields and dimensions are checked by the decoders. Framing is specific to this release and is not Transformers, GGUF or the original quantization manuscript's EESAF format.

	## Provenance and evidence boundaries

	The original source release is authenticated by its nested `research/MANIFEST.json` and verified with `python research/verify_release.py`. Its hash verification covers 153 files; the manifest itself and `SHA256SUMS.txt` are excluded from recursive self-hashing. Release-preparation additions have their own outer manifest and must not be confused with the original frozen research results.

	The four supplied source manuscripts are identified by filenames/hashes in `research/provenance/inputs.json`; their original PDFs are not bundled. The user-supplied architecture illustration is retained with the existing rights/provenance notice and is embedded in the preserved original manuscript. This release does not grant third-party image, paper, dataset, tool, vendor or patent rights. Consult `research/LICENSE_NOTICE.md` before public redistribution.

	No saved CSV, small-model file or CPU fixture establishes HDL simulation, synthesis, timing closure, FPGA measurement, ASIC fabrication, GPU superiority, modern-LLM deployment quality, calibrated success probability or a finished integrated computer. Those remain future validation stages.