"},"path":{"kind":"string","value":"csrc/ops.h"},"language":{"kind":"string","value":"cpp"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"#pragma once\n\n#include <optional>\n#include <torch/library.h>\n\n#include \"core/scalar_type.hpp\"\n\n#include <vector>\n\ntorch::Tensor weak_ref_tensor(torch::Tensor& tensor) {\n // Ensure tensor is on CUDA\n if (!tensor.is_cuda()) {\n throw std::runtime_error(\"Tensor must be on CUDA device\");\n }\n\n // Get the raw data pointer\n void* data_ptr = tensor.data_ptr();\n\n // Get tensor sizes and strides\n std::vector<int64_t> sizes = tensor.sizes().vec();\n std::vector<int64_t> strides = tensor.strides().vec();\n\n // Get tensor options (dtype, device)\n auto options = tensor.options();\n\n // Create a new tensor from the raw data pointer\n auto new_tensor = torch::from_blob(data_ptr, sizes, strides, options);\n\n return new_tensor;\n}\n\nvoid paged_attention_v1(\n torch::Tensor& out, torch::Tensor& query, torch::Tensor& key_cache,\n torch::Tensor& value_cache, int64_t num_kv_heads, double scale,\n torch::Tensor& block_tables, torch::Tensor& seq_lens, int64_t block_size,\n int64_t max_seq_len, const std::optional<torch::Tensor>& alibi_slopes,\n const std::string& kv_cache_dtype, torch::Tensor& k_scale,\n torch::Tensor& v_scale, const int64_t tp_rank,\n const int64_t blocksparse_local_blocks,\n const int64_t blocksparse_vert_stride, const int64_t blocksparse_block_size,\n const int64_t blocksparse_head_sliding_step);\n\nvoid paged_attention_v2(\n torch::Tensor& out, torch::Tensor& exp_sums, torch::Tensor& max_logits,\n torch::Tensor& tmp_out, torch::Tensor& query, torch::Tensor& key_cache,\n torch::Tensor& value_cache, int64_t num_kv_heads, double scale,\n torch::Tensor& block_tables, torch::Tensor& seq_lens, int64_t block_size,\n int64_t max_seq_len, const std::optional<torch::Tensor>& alibi_slopes,\n const std::string& kv_cache_dtype, torch::Tensor& k_scale,\n torch::Tensor& v_scale, const int64_t tp_rank,\n const int64_t blocksparse_local_blocks,\n const int64_t blocksparse_vert_stride, const int64_t blocksparse_block_size,\n const int64_t blocksparse_head_sliding_step);\n\nvoid merge_attn_states(torch::Tensor& output,\n std::optional<torch::Tensor> output_lse,\n const torch::Tensor& prefix_output,\n const torch::Tensor& prefix_lse,\n const torch::Tensor& suffix_output,\n const torch::Tensor& suffix_lse);\n#ifndef USE_ROCM\nvoid convert_vertical_slash_indexes(\n torch::Tensor& block_count, // [BATCH, N_HEADS, NUM_ROWS]\n torch::Tensor& block_offset, // [BATCH, N_HEADS, NUM_ROWS, NNZ_S]\n torch::Tensor& column_count, // [BATCH, N_HEADS, NUM_ROWS]\n torch::Tensor& column_index, // [BATCH, N_HEADS, NUM_ROWS, NNZ_V]\n torch::Tensor q_seqlens, // [BATCH, ]\n torch::Tensor kv_seqlens, // [BATCH, ]\n torch::Tensor vertical_indexes, // [BATCH, N_HEADS, NNZ_V]\n torch::Tensor slash_indexes, // [BATCH, N_HEADS, NNZ_S]\n int64_t context_size, int64_t block_size_M, int64_t block_size_N,\n bool causal);\n\nvoid convert_vertical_slash_indexes_mergehead(\n torch::Tensor& block_count, // [BATCH, N_HEADS, NUM_ROWS]\n torch::Tensor& block_offset, // [BATCH, N_HEADS, NUM_ROWS, NNZ_S]\n torch::Tensor& column_count, // [BATCH, N_HEADS, NUM_ROWS]\n torch::Tensor& column_index, // [BATCH, N_HEADS, NUM_ROWS, NNZ_V]\n torch::Tensor q_seqlens, // [BATCH, ]\n torch::Tensor kv_seqlens, // [BATCH, ]\n torch::Tensor vertical_indexes, // [BATCH, N_HEADS, NNZ_V]\n torch::Tensor slash_indexes, // [BATCH, N_HEADS, NNZ_S]\n torch::Tensor vertical_indices_count, // [N_HEADS, ]\n torch::Tensor slash_indices_count, int64_t context_size,\n int64_t block_size_M, int64_t block_size_N, bool causal);\n#endif\n\nvoid rms_norm(torch::Tensor& out, torch::Tensor& input, torch::Tensor& weight,\n double epsilon);\n\nvoid fused_add_rms_norm(torch::Tensor& input, torch::Tensor& residual,\n torch::Tensor& weight, double epsilon);\n\nvoid fused_qk_norm_rope(torch::Tensor& qkv, int64_t num_heads_q,\n int64_t num_heads_k, int64_t num_heads_v,\n int64_t head_dim, double eps, torch::Tensor& q_weight,\n torch::Tensor& k_weight, torch::Tensor& cos_sin_cache,\n bool is_neox, torch::Tensor& position_ids);\n\nvoid apply_repetition_penalties_(torch::Tensor& logits,\n const torch::Tensor& prompt_mask,\n const torch::Tensor& output_mask,\n const torch::Tensor& repetition_penalties);\n\nvoid top_k_per_row(const torch::Tensor& logits, const torch::Tensor& rowStarts,\n const torch::Tensor& rowEnds, torch::Tensor& indices,\n int64_t numRows, int64_t stride0, int64_t stride1);\n\nvoid top_k_per_row_decode(const torch::Tensor& logits, int64_t next_n,\n const torch::Tensor& seq_lens, torch::Tensor& indices,\n int64_t numRows, int64_t stride0, int64_t stride1);\n\nvoid rms_norm_static_fp8_quant(torch::Tensor& out, torch::Tensor& input,\n torch::Tensor& weight, torch::Tensor& scale,\n double epsilon);\n\nvoid fused_add_rms_norm_static_fp8_quant(torch::Tensor& out,\n torch::Tensor& input,\n torch::Tensor& residual,\n torch::Tensor& weight,\n torch::Tensor& scale, double epsilon);\n\nvoid rms_norm_dynamic_per_token_quant(torch::Tensor& out,\n torch::Tensor const& input,\n torch::Tensor const& weight,\n torch::Tensor& scales,\n double const epsilon,\n std::optional<torch::Tensor> scale_ub,\n std::optional<torch::Tensor> residual);\n\nvoid rotary_embedding(torch::Tensor& positions, torch::Tensor& query,\n std::optional<torch::Tensor> key, int64_t head_size,\n torch::Tensor& cos_sin_cache, bool is_neox);\n\nvoid silu_and_mul(torch::Tensor& out, torch::Tensor& input);\n\nvoid silu_and_mul_quant(torch::Tensor& out, torch::Tensor& input,\n torch::Tensor& scale);\n\n#ifndef USE_ROCM\nvoid silu_and_mul_nvfp4_quant(torch::Tensor& out,\n torch::Tensor& output_block_scale,\n torch::Tensor& input,\n torch::Tensor& input_global_scale);\n#endif\nvoid persistent_masked_m_silu_mul_quant(\n const at::Tensor& input, // (E, T, 2*H)\n const at::Tensor& counts, // (E)\n at::Tensor& y_q, // (E, T, H) [OUT]\n at::Tensor& y_s, // (E, T, H//group_size) [OUT]\n bool use_ue8m0);\n\nvoid mul_and_silu(torch::Tensor& out, torch::Tensor& input);\n\nvoid gelu_and_mul(torch::Tensor& out, torch::Tensor& input);\n\nvoid gelu_tanh_and_mul(torch::Tensor& out, torch::Tensor& input);\n\nvoid fatrelu_and_mul(torch::Tensor& out, torch::Tensor& input,\n double threshold);\nvoid swigluoai_and_mul(torch::Tensor& out, torch::Tensor& input,\n double alpha = 1.702, double limit = 7.0);\n\nvoid gelu_new(torch::Tensor& out, torch::Tensor& input);\n\nvoid gelu_fast(torch::Tensor& out, torch::Tensor& input);\n\nvoid gelu_quick(torch::Tensor& out, torch::Tensor& input);\n\nvoid cutlass_mla_decode(torch::Tensor const& out, torch::Tensor const& q_nope,\n torch::Tensor const& q_pe,\n torch::Tensor const& kv_c_and_k_pe_cache,\n torch::Tensor const& seq_lens,\n torch::Tensor const& page_table, double scale);\n\ntorch::Tensor get_cuda_view_from_cpu_tensor(torch::Tensor& cpu_tensor);\n\n#ifndef USE_ROCM\n\ntorch::Tensor awq_gemm(torch::Tensor _in_feats, torch::Tensor _kernel,\n torch::Tensor _scaling_factors, torch::Tensor _zeros,\n int64_t split_k_iters);\n\ntorch::Tensor awq_dequantize(torch::Tensor _kernel,\n torch::Tensor _scaling_factors,\n torch::Tensor _zeros, int64_t split_k_iters,\n int64_t thx, int64_t thy);\n\ntorch::Tensor permute_cols(torch::Tensor const& A, torch::Tensor const& perm);\n#endif\n\ntorch::Tensor ggml_dequantize(torch::Tensor W, int64_t type, int64_t m,\n int64_t n,\n std::optional<at::ScalarType> const& dtype);\n\ntorch::Tensor ggml_mul_mat_vec_a8(torch::Tensor W, torch::Tensor X,\n int64_t type, int64_t row);\n\ntorch::Tensor ggml_mul_mat_a8(torch::Tensor W, torch::Tensor X, int64_t type,\n int64_t row);\n\ntorch::Tensor ggml_moe_a8(torch::Tensor X, torch::Tensor W,\n torch::Tensor sorted_token_ids,\n torch::Tensor expert_ids,\n torch::Tensor num_tokens_post_padded, int64_t type,\n int64_t row, int64_t top_k, int64_t tokens);\n\ntorch::Tensor ggml_moe_a8_vec(torch::Tensor X, torch::Tensor W,\n torch::Tensor topk_ids, int64_t top_k,\n int64_t type, int64_t row, int64_t tokens);\n\nint64_t ggml_moe_get_block_size(int64_t type);\n\n#ifndef USE_ROCM\n\nbool cutlass_scaled_mm_supports_fp4(int64_t cuda_device_capability);\nbool cutlass_scaled_mm_supports_fp8(int64_t cuda_device_capability);\nbool cutlass_scaled_mm_supports_block_fp8(int64_t cuda_device_capability);\nbool cutlass_group_gemm_supported(int64_t cuda_device_capability);\n\nvoid cutlass_scaled_fp4_mm(torch::Tensor& D, torch::Tensor const& A,\n torch::Tensor const& B, torch::Tensor const& A_sf,\n torch::Tensor const& B_sf,\n torch::Tensor const& alpha);\n\nvoid cutlass_scaled_mm(torch::Tensor& out, torch::Tensor const& a,\n torch::Tensor const& b, torch::Tensor const& a_scales,\n torch::Tensor const& b_scales,\n std::optional<torch::Tensor> const& bias);\n\nvoid cutlass_moe_mm(\n torch::Tensor& out_tensors, torch::Tensor const& a_tensors,\n torch::Tensor const& b_tensors, torch::Tensor const& a_scales,\n torch::Tensor const& b_scales, torch::Tensor const& expert_offsets,\n torch::Tensor const& problem_sizes, torch::Tensor const& a_strides,\n torch::Tensor const& b_strides, torch::Tensor const& c_strides,\n bool per_act_token, bool per_out_ch);\n\nvoid cutlass_fp4_group_mm(\n torch::Tensor& output, const torch::Tensor& a, const torch::Tensor& b,\n const torch::Tensor& a_blockscale, const torch::Tensor& b_blockscales,\n const torch::Tensor& alphas, const torch::Tensor& problem_sizes,\n const torch::Tensor& expert_offsets, const torch::Tensor& sf_offsets);\n\nvoid get_cutlass_moe_mm_data(\n const torch::Tensor& topk_ids, torch::Tensor& expert_offsets,\n torch::Tensor& problem_sizes1, torch::Tensor& problem_sizes2,\n torch::Tensor& input_permutation, torch::Tensor& output_permutation,\n const int64_t num_experts, const int64_t n, const int64_t k,\n const std::optional<torch::Tensor>& blockscale_offsets);\n\nvoid get_cutlass_moe_mm_problem_sizes(\n const torch::Tensor& topk_ids, torch::Tensor& problem_sizes1,\n torch::Tensor& problem_sizes2, const int64_t num_experts, const int64_t n,\n const int64_t k, const std::optional<torch::Tensor>& blockscale_offsets);\n\nvoid get_cutlass_pplx_moe_mm_data(torch::Tensor& expert_offsets,\n torch::Tensor& problem_sizes1,\n torch::Tensor& problem_sizes2,\n const torch::Tensor& expert_num_tokens,\n const int64_t num_local_experts,\n const int64_t padded_m, const int64_t n,\n const int64_t k);\n\nvoid cutlass_scaled_mm_azp(torch::Tensor& out, torch::Tensor const& a,\n torch::Tensor const& b,\n torch::Tensor const& a_scales,\n torch::Tensor const& b_scales,\n torch::Tensor const& azp_adj,\n std::optional<torch::Tensor> const& azp,\n std::optional<torch::Tensor> const& bias);\n\nbool cutlass_sparse_scaled_mm_supported(int64_t cuda_device_capability);\n\nvoid cutlass_scaled_sparse_mm(torch::Tensor& out, torch::Tensor const& a,\n torch::Tensor const& b, torch::Tensor const& e,\n torch::Tensor const& a_scales,\n torch::Tensor const& b_scales,\n std::optional<torch::Tensor> const& bias);\n\nstd::vector<torch::Tensor> cutlass_sparse_compress(torch::Tensor const& a);\n\nvoid scaled_fp4_quant(torch::Tensor& output, torch::Tensor const& input,\n torch::Tensor& output_scale,\n torch::Tensor const& input_scale);\n\nvoid scaled_fp4_experts_quant(\n torch::Tensor& output, torch::Tensor& output_scale,\n torch::Tensor const& input, torch::Tensor const& input_global_scale,\n torch::Tensor const& input_offset_by_experts,\n torch::Tensor const& output_scale_offset_by_experts);\n\nvoid per_token_group_quant_fp8(const torch::Tensor& input,\n torch::Tensor& output_q, torch::Tensor& output_s,\n int64_t group_size, double eps, double fp8_min,\n double fp8_max, bool scale_ue8m0);\n\nvoid per_token_group_quant_int8(const torch::Tensor& input,\n torch::Tensor& output_q,\n torch::Tensor& output_s, int64_t group_size,\n double eps, double int8_min, double int8_max);\n#endif\n\nvoid static_scaled_int8_quant(torch::Tensor& out, torch::Tensor const& input,\n torch::Tensor const& scale,\n std::optional<torch::Tensor> const& azp);\n\nvoid dynamic_scaled_int8_quant(torch::Tensor& out, torch::Tensor const& input,\n torch::Tensor& scales,\n std::optional<torch::Tensor> const& azp);\n\ntorch::Tensor gptq_gemm(torch::Tensor a, torch::Tensor b_q_weight,\n torch::Tensor b_gptq_qzeros,\n torch::Tensor b_gptq_scales, torch::Tensor b_g_idx,\n bool use_exllama, bool use_v2_format, int64_t bit);\n\nvoid gptq_shuffle(torch::Tensor q_weight, torch::Tensor q_perm, int64_t bit);\n\nvoid static_scaled_fp8_quant(torch::Tensor& out, torch::Tensor const& input,\n torch::Tensor const& scale);\n\nvoid dynamic_scaled_fp8_quant(torch::Tensor& out, torch::Tensor const& input,\n torch::Tensor& scale);\n\nvoid dynamic_per_token_scaled_fp8_quant(\n torch::Tensor& out, torch::Tensor const& input, torch::Tensor& scale,\n std::optional<torch::Tensor> const& scale_ub);\n\nvoid selective_scan_fwd(\n const torch::Tensor& u, const torch::Tensor& delta, const torch::Tensor& A,\n const torch::Tensor& B, const torch::Tensor& C,\n const std::optional<torch::Tensor>& D_,\n const std::optional<torch::Tensor>& z_,\n const std::optional<torch::Tensor>& delta_bias_, bool delta_softplus,\n const std::optional<torch::Tensor>& query_start_loc,\n const std::optional<torch::Tensor>& cache_indices,\n const std::optional<torch::Tensor>& has_initial_state,\n const torch::Tensor& ssm_states, int64_t pad_slot_id, int64_t block_size,\n const std::optional<torch::Tensor>& block_idx_first_scheduled_token,\n const std::optional<torch::Tensor>& block_idx_last_scheduled_token,\n const std::optional<torch::Tensor>& initial_state_idx);\n\ntorch::Tensor dynamic_4bit_int_moe_cpu(\n torch::Tensor x, torch::Tensor topk_ids, torch::Tensor topk_weights,\n torch::Tensor w13_packed, torch::Tensor w2_packed, int64_t H, int64_t I,\n int64_t I2, int64_t group_size, bool apply_router_weight_on_input,\n int64_t activation_kind);\n\nusing fptr_t = int64_t;\nfptr_t init_custom_ar(const std::vector<int64_t>& fake_ipc_ptrs,\n torch::Tensor& rank_data, int64_t rank,\n bool fully_connected);\nvoid all_reduce(fptr_t _fa, torch::Tensor& inp, torch::Tensor& out,\n fptr_t reg_buffer, int64_t reg_buffer_sz_bytes);\nvoid dispose(fptr_t _fa);\nint64_t meta_size();\nvoid register_buffer(fptr_t _fa, const std::vector<int64_t>& fake_ipc_ptrs);\nstd::tuple<std::vector<int64_t>, std::vector<int64_t>>\nget_graph_buffer_ipc_meta(fptr_t _fa);\nvoid register_graph_buffers(fptr_t _fa,\n const std::vector<std::vector<int64_t>>& handles,\n const std::vector<std::vector<int64_t>>& offsets);\nstd::tuple<int64_t, torch::Tensor> allocate_shared_buffer_and_handle(\n int64_t size);\nint64_t open_mem_handle(torch::Tensor& mem_handle);\nvoid free_shared_buffer(int64_t buffer);\n\ntorch::Tensor hadacore_transform(torch::Tensor& x, bool inplace);\n\n#ifdef USE_ROCM\nfptr_t init_custom_qr(int64_t rank, int64_t world_size,\n std::optional<int64_t> qr_max_size = std::nullopt);\nvoid qr_destroy(fptr_t _fa);\ntorch::Tensor qr_get_handle(fptr_t _fa);\nvoid qr_open_handles(fptr_t _fa, const std::vector<torch::Tensor>& handles);\nvoid qr_all_reduce(fptr_t _fa, torch::Tensor& inp, torch::Tensor& out,\n int64_t quant_level, bool cast_bf2half = false);\nint64_t qr_max_size();\n#endif\n"},"after_code":{"kind":"string","value":"#pragma once\n\n#include <optional>\n#include <torch/library.h>\n\n#include \"core/scalar_type.hpp\"\n\n#include <vector>\n\ntorch::Tensor weak_ref_tensor(torch::Tensor& tensor) {\n // Ensure tensor is on CUDA\n if (!tensor.is_cuda()) {\n throw std::runtime_error(\"Tensor must be on CUDA device\");\n }\n\n // Get the raw data pointer\n void* data_ptr = tensor.data_ptr();\n\n // Get tensor sizes and strides\n std::vector<int64_t> sizes = tensor.sizes().vec();\n std::vector<int64_t> strides = tensor.strides().vec();\n\n // Get tensor options (dtype, device)\n auto options = tensor.options();\n\n // Create a new tensor from the raw data pointer\n auto new_tensor = torch::from_blob(data_ptr, sizes, strides, options);\n\n return new_tensor;\n}\n\nvoid paged_attention_v1(\n torch::Tensor& out, torch::Tensor& query, torch::Tensor& key_cache,\n torch::Tensor& value_cache, int64_t num_kv_heads, double scale,\n torch::Tensor& block_tables, torch::Tensor& seq_lens, int64_t block_size,\n int64_t max_seq_len, const std::optional<torch::Tensor>& alibi_slopes,\n const std::string& kv_cache_dtype, torch::Tensor& k_scale,\n torch::Tensor& v_scale, const int64_t tp_rank,\n const int64_t blocksparse_local_blocks,\n const int64_t blocksparse_vert_stride, const int64_t blocksparse_block_size,\n const int64_t blocksparse_head_sliding_step);\n\nvoid paged_attention_v2(\n torch::Tensor& out, torch::Tensor& exp_sums, torch::Tensor& max_logits,\n torch::Tensor& tmp_out, torch::Tensor& query, torch::Tensor& key_cache,\n torch::Tensor& value_cache, int64_t num_kv_heads, double scale,\n torch::Tensor& block_tables, torch::Tensor& seq_lens, int64_t block_size,\n int64_t max_seq_len, const std::optional<torch::Tensor>& alibi_slopes,\n const std::string& kv_cache_dtype, torch::Tensor& k_scale,\n torch::Tensor& v_scale, const int64_t tp_rank,\n const int64_t blocksparse_local_blocks,\n const int64_t blocksparse_vert_stride, const int64_t blocksparse_block_size,\n const int64_t blocksparse_head_sliding_step);\n\nvoid merge_attn_states(torch::Tensor& output,\n std::optional<torch::Tensor> output_lse,\n const torch::Tensor& prefix_output,\n const torch::Tensor& prefix_lse,\n const torch::Tensor& suffix_output,\n const torch::Tensor& suffix_lse);\n#ifndef USE_ROCM\nvoid convert_vertical_slash_indexes(\n torch::Tensor& block_count, // [BATCH, N_HEADS, NUM_ROWS]\n torch::Tensor& block_offset, // [BATCH, N_HEADS, NUM_ROWS, NNZ_S]\n torch::Tensor& column_count, // [BATCH, N_HEADS, NUM_ROWS]\n torch::Tensor& column_index, // [BATCH, N_HEADS, NUM_ROWS, NNZ_V]\n torch::Tensor q_seqlens, // [BATCH, ]\n torch::Tensor kv_seqlens, // [BATCH, ]\n torch::Tensor vertical_indexes, // [BATCH, N_HEADS, NNZ_V]\n torch::Tensor slash_indexes, // [BATCH, N_HEADS, NNZ_S]\n int64_t context_size, int64_t block_size_M, int64_t block_size_N,\n bool causal);\n\nvoid convert_vertical_slash_indexes_mergehead(\n torch::Tensor& block_count, // [BATCH, N_HEADS, NUM_ROWS]\n torch::Tensor& block_offset, // [BATCH, N_HEADS, NUM_ROWS, NNZ_S]\n torch::Tensor& column_count, // [BATCH, N_HEADS, NUM_ROWS]\n torch::Tensor& column_index, // [BATCH, N_HEADS, NUM_ROWS, NNZ_V]\n torch::Tensor q_seqlens, // [BATCH, ]\n torch::Tensor kv_seqlens, // [BATCH, ]\n torch::Tensor vertical_indexes, // [BATCH, N_HEADS, NNZ_V]\n torch::Tensor slash_indexes, // [BATCH, N_HEADS, NNZ_S]\n torch::Tensor vertical_indices_count, // [N_HEADS, ]\n torch::Tensor slash_indices_count, int64_t context_size,\n int64_t block_size_M, int64_t block_size_N, bool causal);\n#endif\n\nvoid rms_norm(torch::Tensor& out, torch::Tensor& input, torch::Tensor& weight,\n double epsilon);\n\nvoid fused_add_rms_norm(torch::Tensor& input, torch::Tensor& residual,\n torch::Tensor& weight, double epsilon);\n\nvoid fused_qk_norm_rope(torch::Tensor& qkv, int64_t num_heads_q,\n int64_t num_heads_k, int64_t num_heads_v,\n int64_t head_dim, double eps, torch::Tensor& q_weight,\n torch::Tensor& k_weight, torch::Tensor& cos_sin_cache,\n bool is_neox, torch::Tensor& position_ids);\n\nvoid apply_repetition_penalties_(torch::Tensor& logits,\n const torch::Tensor& prompt_mask,\n const torch::Tensor& output_mask,\n const torch::Tensor& repetition_penalties);\n\nvoid top_k_per_row(const torch::Tensor& logits, const torch::Tensor& rowStarts,\n const torch::Tensor& rowEnds, torch::Tensor& indices,\n int64_t numRows, int64_t stride0, int64_t stride1);\n\nvoid top_k_per_row_decode(const torch::Tensor& logits, int64_t next_n,\n const torch::Tensor& seq_lens, torch::Tensor& indices,\n int64_t numRows, int64_t stride0, int64_t stride1);\n\nvoid rms_norm_static_fp8_quant(torch::Tensor& out, torch::Tensor& input,\n torch::Tensor& weight, torch::Tensor& scale,\n double epsilon);\n\nvoid fused_add_rms_norm_static_fp8_quant(torch::Tensor& out,\n torch::Tensor& input,\n torch::Tensor& residual,\n torch::Tensor& weight,\n torch::Tensor& scale, double epsilon);\n\nvoid rms_norm_dynamic_per_token_quant(torch::Tensor& out,\n torch::Tensor const& input,\n torch::Tensor const& weight,\n torch::Tensor& scales,\n double const epsilon,\n std::optional<torch::Tensor> scale_ub,\n std::optional<torch::Tensor> residual);\n\nvoid rotary_embedding(torch::Tensor& positions, torch::Tensor& query,\n std::optional<torch::Tensor> key, int64_t head_size,\n torch::Tensor& cos_sin_cache, bool is_neox);\n\nvoid silu_and_mul(torch::Tensor& out, torch::Tensor& input);\n\nvoid silu_and_mul_quant(torch::Tensor& out, torch::Tensor& input,\n torch::Tensor& scale);\n\n#ifndef USE_ROCM\nvoid silu_and_mul_nvfp4_quant(torch::Tensor& out,\n torch::Tensor& output_block_scale,\n torch::Tensor& input,\n torch::Tensor& input_global_scale);\n#endif\nvoid persistent_masked_m_silu_mul_quant(\n const at::Tensor& input, // (E, T, 2*H)\n const at::Tensor& counts, // (E)\n at::Tensor& y_q, // (E, T, H) [OUT]\n at::Tensor& y_s, // (E, T, H//group_size) [OUT]\n bool use_ue8m0);\n\nvoid mul_and_silu(torch::Tensor& out, torch::Tensor& input);\n\nvoid gelu_and_mul(torch::Tensor& out, torch::Tensor& input);\n\nvoid gelu_tanh_and_mul(torch::Tensor& out, torch::Tensor& input);\n\nvoid fatrelu_and_mul(torch::Tensor& out, torch::Tensor& input,\n double threshold);\nvoid swigluoai_and_mul(torch::Tensor& out, torch::Tensor& input,\n double alpha = 1.702, double limit = 7.0);\n\nvoid gelu_new(torch::Tensor& out, torch::Tensor& input);\n\nvoid gelu_fast(torch::Tensor& out, torch::Tensor& input);\n\nvoid gelu_quick(torch::Tensor& out, torch::Tensor& input);\n\nvoid cutlass_mla_decode(torch::Tensor const& out, torch::Tensor const& q_nope,\n torch::Tensor const& q_pe,\n torch::Tensor const& kv_c_and_k_pe_cache,\n torch::Tensor const& seq_lens,\n torch::Tensor const& page_table, double scale);\n\ntorch::Tensor get_cuda_view_from_cpu_tensor(torch::Tensor& cpu_tensor);\n\n#ifndef USE_ROCM\n\ntorch::Tensor awq_gemm(torch::Tensor _in_feats, torch::Tensor _kernel,\n torch::Tensor _scaling_factors, torch::Tensor _zeros,\n int64_t split_k_iters);\n\ntorch::Tensor awq_dequantize(torch::Tensor _kernel,\n torch::Tensor _scaling_factors,\n torch::Tensor _zeros, int64_t split_k_iters,\n int64_t thx, int64_t thy);\n\ntorch::Tensor permute_cols(torch::Tensor const& A, torch::Tensor const& perm);\n#endif\n\ntorch::Tensor ggml_dequantize(torch::Tensor W, int64_t type, int64_t m,\n int64_t n,\n std::optional<at::ScalarType> const& dtype);\n\ntorch::Tensor ggml_mul_mat_vec_a8(torch::Tensor W, torch::Tensor X,\n int64_t type, int64_t row);\n\ntorch::Tensor ggml_mul_mat_a8(torch::Tensor W, torch::Tensor X, int64_t type,\n int64_t row);\n\ntorch::Tensor ggml_moe_a8(torch::Tensor X, torch::Tensor W,\n torch::Tensor sorted_token_ids,\n torch::Tensor expert_ids,\n torch::Tensor num_tokens_post_padded, int64_t type,\n int64_t row, int64_t top_k, int64_t tokens);\n\ntorch::Tensor ggml_moe_a8_vec(torch::Tensor X, torch::Tensor W,\n torch::Tensor topk_ids, int64_t top_k,\n int64_t type, int64_t row, int64_t tokens);\n\nint64_t ggml_moe_get_block_size(int64_t type);\n\n#ifndef USE_ROCM\n\nbool cutlass_scaled_mm_supports_fp4(int64_t cuda_device_capability);\nbool cutlass_scaled_mm_supports_fp8(int64_t cuda_device_capability);\nbool cutlass_scaled_mm_supports_block_fp8(int64_t cuda_device_capability);\nbool cutlass_group_gemm_supported(int64_t cuda_device_capability);\n\nvoid cutlass_scaled_fp4_mm(torch::Tensor& D, torch::Tensor const& A,\n torch::Tensor const& B, torch::Tensor const& A_sf,\n torch::Tensor const& B_sf,\n torch::Tensor const& alpha);\n\nvoid cutlass_scaled_mm(torch::Tensor& out, torch::Tensor const& a,\n torch::Tensor const& b, torch::Tensor const& a_scales,\n torch::Tensor const& b_scales,\n std::optional<torch::Tensor> const& bias);\n\nvoid cutlass_moe_mm(\n torch::Tensor& out_tensors, torch::Tensor const& a_tensors,\n torch::Tensor const& b_tensors, torch::Tensor const& a_scales,\n torch::Tensor const& b_scales, torch::Tensor const& expert_offsets,\n torch::Tensor const& problem_sizes, torch::Tensor const& a_strides,\n torch::Tensor const& b_strides, torch::Tensor const& c_strides,\n bool per_act_token, bool per_out_ch);\n\nvoid cutlass_fp4_group_mm(\n torch::Tensor& output, const torch::Tensor& a, const torch::Tensor& b,\n const torch::Tensor& a_blockscale, const torch::Tensor& b_blockscales,\n const torch::Tensor& alphas, const torch::Tensor& problem_sizes,\n const torch::Tensor& expert_offsets, const torch::Tensor& sf_offsets);\n\nvoid get_cutlass_moe_mm_data(\n const torch::Tensor& topk_ids, torch::Tensor& expert_offsets,\n torch::Tensor& problem_sizes1, torch::Tensor& problem_sizes2,\n torch::Tensor& input_permutation, torch::Tensor& output_permutation,\n const int64_t num_experts, const int64_t n, const int64_t k,\n const std::optional<torch::Tensor>& blockscale_offsets);\n\nvoid get_cutlass_moe_mm_problem_sizes(\n const torch::Tensor& topk_ids, torch::Tensor& problem_sizes1,\n torch::Tensor& problem_sizes2, const int64_t num_experts, const int64_t n,\n const int64_t k, const std::optional<torch::Tensor>& blockscale_offsets);\n\nvoid get_cutlass_pplx_moe_mm_data(torch::Tensor& expert_offsets,\n torch::Tensor& problem_sizes1,\n torch::Tensor& problem_sizes2,\n const torch::Tensor& expert_num_tokens,\n const int64_t num_local_experts,\n const int64_t padded_m, const int64_t n,\n const int64_t k);\n\nvoid cutlass_scaled_mm_azp(torch::Tensor& out, torch::Tensor const& a,\n torch::Tensor const& b,\n torch::Tensor const& a_scales,\n torch::Tensor const& b_scales,\n torch::Tensor const& azp_adj,\n std::optional<torch::Tensor> const& azp,\n std::optional<torch::Tensor> const& bias);\n\nbool cutlass_sparse_scaled_mm_supported(int64_t cuda_device_capability);\n\nvoid cutlass_scaled_sparse_mm(torch::Tensor& out, torch::Tensor const& a,\n torch::Tensor const& b, torch::Tensor const& e,\n torch::Tensor const& a_scales,\n torch::Tensor const& b_scales,\n std::optional<torch::Tensor> const& bias);\n\nstd::vector<torch::Tensor> cutlass_sparse_compress(torch::Tensor const& a);\n\nvoid scaled_fp4_quant(torch::Tensor& output, torch::Tensor const& input,\n torch::Tensor& output_scale,\n torch::Tensor const& input_scale);\n\nvoid scaled_fp4_experts_quant(\n torch::Tensor& output, torch::Tensor& output_scale,\n torch::Tensor const& input, torch::Tensor const& input_global_scale,\n torch::Tensor const& input_offset_by_experts,\n torch::Tensor const& output_scale_offset_by_experts);\n\nvoid per_token_group_quant_fp8(const torch::Tensor& input,\n torch::Tensor& output_q, torch::Tensor& output_s,\n int64_t group_size, double eps, double fp8_min,\n double fp8_max, bool scale_ue8m0);\n\nvoid per_token_group_quant_int8(const torch::Tensor& input,\n torch::Tensor& output_q,\n torch::Tensor& output_s, int64_t group_size,\n double eps, double int8_min, double int8_max);\n\n// Fused activation quantisation + DeepGEMM-compatible UE8M0-packed scales.\nvoid per_token_group_quant_8bit_packed(const torch::Tensor& input,\n torch::Tensor& output_q,\n torch::Tensor& output_s_packed,\n int64_t group_size, double eps,\n double min_8bit, double max_8bit);\n\n#endif\n\nvoid static_scaled_int8_quant(torch::Tensor& out, torch::Tensor const& input,\n torch::Tensor const& scale,\n std::optional<torch::Tensor> const& azp);\n\nvoid dynamic_scaled_int8_quant(torch::Tensor& out, torch::Tensor const& input,\n torch::Tensor& scales,\n std::optional<torch::Tensor> const& azp);\n\ntorch::Tensor gptq_gemm(torch::Tensor a, torch::Tensor b_q_weight,\n torch::Tensor b_gptq_qzeros,\n torch::Tensor b_gptq_scales, torch::Tensor b_g_idx,\n bool use_exllama, bool use_v2_format, int64_t bit);\n\nvoid gptq_shuffle(torch::Tensor q_weight, torch::Tensor q_perm, int64_t bit);\n\nvoid static_scaled_fp8_quant(torch::Tensor& out, torch::Tensor const& input,\n torch::Tensor const& scale);\n\nvoid dynamic_scaled_fp8_quant(torch::Tensor& out, torch::Tensor const& input,\n torch::Tensor& scale);\n\nvoid dynamic_per_token_scaled_fp8_quant(\n torch::Tensor& out, torch::Tensor const& input, torch::Tensor& scale,\n std::optional<torch::Tensor> const& scale_ub);\n\nvoid selective_scan_fwd(\n const torch::Tensor& u, const torch::Tensor& delta, const torch::Tensor& A,\n const torch::Tensor& B, const torch::Tensor& C,\n const std::optional<torch::Tensor>& D_,\n const std::optional<torch::Tensor>& z_,\n const std::optional<torch::Tensor>& delta_bias_, bool delta_softplus,\n const std::optional<torch::Tensor>& query_start_loc,\n const std::optional<torch::Tensor>& cache_indices,\n const std::optional<torch::Tensor>& has_initial_state,\n const torch::Tensor& ssm_states, int64_t pad_slot_id, int64_t block_size,\n const std::optional<torch::Tensor>& block_idx_first_scheduled_token,\n const std::optional<torch::Tensor>& block_idx_last_scheduled_token,\n const std::optional<torch::Tensor>& initial_state_idx);\n\ntorch::Tensor dynamic_4bit_int_moe_cpu(\n torch::Tensor x, torch::Tensor topk_ids, torch::Tensor topk_weights,\n torch::Tensor w13_packed, torch::Tensor w2_packed, int64_t H, int64_t I,\n int64_t I2, int64_t group_size, bool apply_router_weight_on_input,\n int64_t activation_kind);\n\nusing fptr_t = int64_t;\nfptr_t init_custom_ar(const std::vector<int64_t>& fake_ipc_ptrs,\n torch::Tensor& rank_data, int64_t rank,\n bool fully_connected);\nvoid all_reduce(fptr_t _fa, torch::Tensor& inp, torch::Tensor& out,\n fptr_t reg_buffer, int64_t reg_buffer_sz_bytes);\nvoid dispose(fptr_t _fa);\nint64_t meta_size();\nvoid register_buffer(fptr_t _fa, const std::vector<int64_t>& fake_ipc_ptrs);\nstd::tuple<std::vector<int64_t>, std::vector<int64_t>>\nget_graph_buffer_ipc_meta(fptr_t _fa);\nvoid register_graph_buffers(fptr_t _fa,\n const std::vector<std::vector<int64_t>>& handles,\n const std::vector<std::vector<int64_t>>& offsets);\nstd::tuple<int64_t, torch::Tensor> allocate_shared_buffer_and_handle(\n int64_t size);\nint64_t open_mem_handle(torch::Tensor& mem_handle);\nvoid free_shared_buffer(int64_t buffer);\n\ntorch::Tensor hadacore_transform(torch::Tensor& x, bool inplace);\n\n#ifdef USE_ROCM\nfptr_t init_custom_qr(int64_t rank, int64_t world_size,\n std::optional<int64_t> qr_max_size = std::nullopt);\nvoid qr_destroy(fptr_t _fa);\ntorch::Tensor qr_get_handle(fptr_t _fa);\nvoid qr_open_handles(fptr_t _fa, const std::vector<torch::Tensor>& handles);\nvoid qr_all_reduce(fptr_t _fa, torch::Tensor& inp, torch::Tensor& out,\n int64_t quant_level, bool cast_bf2half = false);\nint64_t qr_max_size();\n#endif\n"},"diff":{"kind":"string","value":"--- csrc/ops.h\n+++ csrc/ops.h\n@@ -299,6 +299,14 @@\n torch::Tensor& output_q,\n torch::Tensor& output_s, int64_t group_size,\n double eps, double int8_min, double int8_max);\n+\n+// Fused activation quantisation + DeepGEMM-compatible UE8M0-packed scales.\n+void per_token_group_quant_8bit_packed(const torch::Tensor& input,\n+ torch::Tensor& output_q,\n+ torch::Tensor& output_s_packed,\n+ int64_t group_size, double eps,\n+ double min_8bit, double max_8bit);\n+\n #endif\n \n void static_scaled_int8_quant(torch::Tensor& out, torch::Tensor const& input,"},"lines_added":{"kind":"number","value":8,"string":"8"},"lines_removed":{"kind":"number","value":0,"string":"0"},"files_in_commit":{"kind":"number","value":5,"string":"5"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cpp kernel file from vllm (csrc/ops.h).\n\nGoal: [Perf] Deepgemm fused layout kernel for activations, 4.3% throughput improvement, 10.7% TTFT improvement.\nTarget hardware: unspecified\nTarget models: unspecified\n\nCurrent file:\n```cpp\n#pragma once\n\n#include <optional>\n#include <torch/library.h>\n\n#include \"core/scalar_type.hpp\"\n\n#include <vector>\n\ntorch::Tensor weak_ref_tensor(torch::Tensor& tensor) {\n // Ensure tensor is on CUDA\n if (!tensor.is_cuda()) {\n throw std::runtime_error(\"Tensor must be on CUDA device\");\n }\n\n // Get the raw data pointer\n void* data_ptr = tensor.data_ptr();\n\n // Get tensor sizes and strides\n std::vector<int64_t> sizes = tensor.sizes().vec();\n std::vector<int64_t> strides = tensor.strides().vec();\n\n // Get tensor options (dtype, device)\n auto options = tensor.options();\n\n // Create a new tensor from the raw data pointer\n auto new_tensor = torch::from_blob(data_ptr, sizes, strides, options);\n\n return new_tensor;\n}\n\nvoid paged_attention_v1(\n torch::Tensor& out, torch::Tensor& query, torch::Tensor& key_cache,\n torch::Tensor& value_cache, int64_t num_kv_heads, double scale,\n torch::Tensor& block_tables, torch::Tensor& seq_lens, int64_t block_size,\n int64_t max_seq_len, const std::optional<torch::Tensor>& alibi_slopes,\n const std::string& kv_cache_dtype, torch::Tensor& k_scale,\n torch::Tensor& v_scale, const int64_t tp_rank,\n const int64_t blocksparse_local_blocks,\n const int64_t blocksparse_vert_stride, const int64_t blocksparse_block_size,\n const int64_t blocksparse_head_sliding_step);\n\nvoid paged_attention_v2(\n torch::Tensor& out, torch::Tensor& exp_sums, torch::Tensor& max_logits,\n torch::Tensor& tmp_out, torch::Tensor& query, torch::Tensor& key_cache,\n torch::Tensor& value_cache, int64_t num_kv_heads, double scale,\n torch::Tensor& block_tables, torch::Tensor& seq_lens, int64_t block_size,\n int64_t max_seq_len, const std::optional<torch::Tensor>& alibi_slopes,\n const std::string& kv_cache_dtype, torch::Tensor& k_scale,\n torch::Tensor& v_scale, const int64_t tp_rank,\n const int64_t blocksparse_local_blocks,\n const int64_t blocksparse_vert_stride, const int64_t blocksparse_block_size,\n const int64_t blocksparse_head_sliding_step);\n\nvoid merge_attn_states(torch::Tensor& output,\n std::optional<torch::Tensor> output_lse,\n const torch::Tensor& prefix_output,\n const torch::Tensor& prefix_lse,\n const torch::Tensor& suffix_output,\n const torch::Tensor& suffix_lse);\n#ifndef USE_ROCM\nvoid convert_vertical_slash_indexes(\n torch::Tensor& block_count, // [BATCH, N_HEADS, NUM_ROWS]\n torch::Tensor& block_offset, // [BATCH, N_HEADS, NUM_ROWS, NNZ_S]\n torch::Tensor& column_count, // [BATCH, N_HEADS, NUM_ROWS]\n torch::Tensor& column_index, // [BATCH, N_HEADS, NUM_ROWS, NNZ_V]\n torch::Tensor q_seqlens, // [BATCH, ]\n torch::Tensor kv_seqlens, // [BATCH, ]\n torch::Tensor vertical_indexes, // [BATCH, N_HEADS, NNZ_V]\n torch::Tensor slash_indexes, // [BATCH, N_HEADS, NNZ_S]\n int64_t context_size, int64_t block_size_M, int64_t block_size_N,\n bool causal);\n\nvoid convert_vertical_slash_indexes_mergehead(\n torch::Tensor& block_count, // [BATCH, N_HEADS, NUM_ROWS]\n torch::Tensor& block_offset, // [BATCH, N_HEADS, NUM_ROWS, NNZ_S]\n torch::Tensor& column_count, // [BATCH, N_HEADS, NUM_ROWS]\n torch::Tensor& column_index, // [BATCH, N_HEADS, NUM_ROWS, NNZ_V]\n torch::Tensor q_seqlens, // [BATCH, ]\n torch::Tensor kv_seqlens, // [BATCH, ]\n torch::Tensor vertical_indexes, // [BATCH, N_HEADS, NNZ_V]\n torch::Tensor slash_indexes, // [BATCH, N_HEADS, NNZ_S]\n torch::Tensor vertical_indices_count, // [N_HEADS, ]\n torch::Tensor slash_indices_count, int64_t context_size,\n int64_t block_size_M, int64_t block_size_N, bool causal);\n#endif\n\nvoid rms_norm(torch::Tensor& out, torch::Tensor& input, torch::Tensor& weight,\n double epsilon);\n\nvoid fused_add_rms_norm(torch::Tensor& input, torch::Tensor& residual,\n torch::Tensor& weight, double epsilon);\n\nvoid fused_qk_norm_rope(torch::Tensor& qkv, int64_t num_heads_q,\n int64_t num_heads_k, int64_t num_heads_v,\n int64_t head_dim, double eps, torch::Tensor& q_weight,\n torch::Tensor& k_weight, torch::Tensor& cos_sin_cache,\n bool is_neox, torch::Tensor& position_ids);\n\nvoid apply_repetition_penalties_(torch::Tensor& logits,\n const torch::Tensor& prompt_mask,\n const torch::Tensor& output_mask,\n const torch::Tensor& repetition_penalties);\n\nvoid top_k_per_row(const torch::Tensor& logits, const torch::Tensor& rowStarts,\n const torch::Tensor& rowEnds, torch::Tensor& indices,\n int64_t numRows, int64_t stride0, int64_t stride1);\n\nvoid top_k_per_row_decode(const torch::Tensor& logits, int64_t next_n,\n const torch::Tensor& seq_lens, torch::Tensor& indices,\n int64_t numRows, int64_t stride0, int64_t stride1);\n\nvoid rms_norm_static_fp8_quant(torch::Tensor& out, torch::Tensor& input,\n torch::Tensor& weight, torch::Tensor& scale,\n double epsilon);\n\nvoid fused_add_rms_norm_static_fp8_quant(torch::Tensor& out,\n torch::Tensor& input,\n torch::Tensor& residual,\n torch::Tensor& weight,\n torch::Tensor& scale, double epsilon);\n\nvoid rms_norm_dynamic_per_token_quant(torch::Tensor& out,\n torch::Tensor const& input,\n torch::Tensor const& weight,\n torch::Tensor& scales,\n double const epsilon,\n std::optional<torch::Tensor> scale_ub,\n std::optional<torch::Tensor> residual);\n\nvoid rotary_embedding(torch::Tensor& positions, torch::Tensor& query,\n std::optional<torch::Tensor> key, int64_t head_size,\n torch::Tensor& cos_sin_cache, bool is_neox);\n\nvoid silu_and_mul(torch::Tensor& out, torch::Tensor& input);\n\nvoid silu_and_mul_quant(torch::Tensor& out, torch::Tensor& input,\n torch::Tensor& scale);\n\n#ifndef USE_ROCM\nvoid silu_and_mul_nvfp4_quant(torch::Tensor& out,\n torch::Tensor& output_block_scale,\n torch::Tensor& input,\n torch::Tensor& input_global_scale);\n#endif\nvoid persistent_masked_m_silu_mul_quant(\n const at::Tensor& input, // (E, T, 2*H)\n const at::Tensor& counts, // (E)\n at::Tensor& y_q, // (E, T, H) [OUT]\n at::Tensor& y_s, // (E, T, H//group_size) [OUT]\n bool use_ue8m0);\n\nvoid mul_and_silu(torch::Tensor& out, torch::Tensor& input);\n\nvoid gelu_and_mul(torch::Tensor& out, torch::Tensor& input);\n\nvoid gelu_tanh_and_mul(torch::Tensor& out, torch::Tensor& input);\n\nvoid fatrelu_and_mul(torch::Tensor& out, torch::Tensor& input,\n double threshold);\nvoid swigluoai_and_mul(torch::Tensor& out, torch::Tensor& input,\n double alpha = 1.702, double limit = 7.0);\n\nvoid gelu_new(torch::Tensor& out, torch::Tensor& input);\n\nvoid gelu_fast(torch::Tensor& out, torch::Tensor& input);\n\nvoid gelu_quick(torch::Tensor& out, torch::Tensor& input);\n\nvoid cutlass_mla_decode(torch::Tensor const& out, torch::Tensor const& q_nope,\n torch::Tensor const& q_pe,\n torch::Tensor const& kv_c_and_k_pe_cache,\n torch::Tensor const& seq_lens,\n torch::Tensor const& page_table, double scale);\n\ntorch::Tensor get_cuda_view_from_cpu_tensor(torch::Tensor& cpu_tensor);\n\n#ifndef USE_ROCM\n\ntorch::Tensor awq_gemm(torch::Tensor _in_feats, torch::Tensor _kernel,\n torch::Tensor _scaling_factors, torch::Tensor _zeros,\n int64_t split_k_iters);\n\ntorch::Tensor awq_dequantize(torch::Tensor _kernel,\n torch::Tensor _scaling_factors,\n torch::Tensor _zeros, int64_t split_k_iters,\n int64_t thx, int64_t thy);\n\ntorch::Tensor permute_cols(torch::Tensor const& A, torch::Tensor const& perm);\n#endif\n\ntorch::Tensor ggml_dequantize(torch::Tensor W, int64_t type, int64_t m,\n int64_t n,\n std::optional<at::ScalarType> const& dtype);\n\ntorch::Tensor ggml_mul_mat_vec_a8(torch::Tensor W, torch::Tensor X,\n int64_t type, int64_t row);\n\ntorch::Tensor ggml_mul_mat_a8(torch::Tensor W, torch::Tensor X, int64_t type,\n int64_t row);\n\ntorch::Tensor ggml_moe_a8(torch::Tensor X, torch::Tensor W,\n torch::Tensor sorted_token_ids,\n torch::Tensor expert_ids,\n torch::Tensor num_tokens_post_padded, int64_t type,\n int64_t row, int64_t top_k, int64_t tokens);\n\ntorch::Tensor ggml_moe_a8_vec(torch::Tensor X, torch::Tensor W,\n torch::Tensor topk_ids, int64_t top_k,\n int64_t type, int64_t row, int64_t tokens);\n\nint64_t ggml_moe_get_block_size(int64_t type);\n\n#ifndef USE_ROCM\n\nbool cutlass_scaled_mm_supports_fp4(int64_t cuda_device_capability);\nbool cutlass_scaled_mm_supports_fp8(int64_t cuda_device_capability);\nbool cutlass_scaled_mm_supports_block_fp8(int64_t cuda_device_capability);\nbool cutlass_group_gemm_supported(int64_t cuda_device_capability);\n\nvoid cutlass_scaled_fp4_mm(torch::Tensor& D, torch::Tensor const& A,\n torch::Tensor const& B, torch::Tensor const& A_sf,\n torch::Tensor const& B_sf,\n torch::Tensor const& alpha);\n\nvoid cutlass_scaled_mm(torch::Tensor& out, torch::Tensor const& a,\n torch::Tensor const& b, torch::Tensor const& a_scales,\n torch::Tensor const& b_scales,\n std::optional<torch::Tensor> const& bias);\n\nvoid cutlass_moe_mm(\n torch::Tensor& out_tensors, torch::Tensor const& a_tensors,\n torch::Tensor const& b_tensors, torch::Tensor const& a_scales,\n torch::Tensor const& b_scales, torch::Tensor const& expert_offsets,\n torch::Tensor const& problem_sizes, torch::Tensor const& a_strides,\n torch::Tensor const& b_strides, torch::Tensor const& c_strides,\n bool per_act_token, bool per_out_ch);\n\nvoid cutlass_fp4_group_mm(\n torch::Tensor& output, const torch::Tensor& a, const torch::Tensor& b,\n const torch::Tensor& a_blockscale, const torch::Tensor& b_blockscales,\n const torch::Tensor& alphas, const torch::Tensor& problem_sizes,\n const torch::Tensor& expert_offsets, const torch::Tensor& sf_offsets);\n\nvoid get_cutlass_moe_mm_data(\n const torch::Tensor& topk_ids, torch::Tensor& expert_offsets,\n torch::Tensor& problem_sizes1, torch::Tensor& problem_sizes2,\n torch::Tensor& input_permutation, torch::Tensor& output_permutation,\n const int64_t num_experts, const int64_t n, const int64_t k,\n const std::optional<torch::Tensor>& blockscale_offsets);\n\nvoid get_cutlass_moe_mm_problem_sizes(\n const torch::Tensor& topk_ids, torch::Tensor& problem_sizes1,\n torch::Tensor& problem_sizes2, const int64_t num_experts, const int64_t n,\n const int64_t k, const std::optional<torch::Tensor>& blockscale_offsets);\n\nvoid get_cutlass_pplx_moe_mm_data(torch::Tensor& expert_offsets,\n torch::Tensor& problem_sizes1,\n torch::Tensor& problem_sizes2,\n const torch::Tensor& expert_num_tokens,\n const int64_t num_local_experts,\n const int64_t padded_m, const int64_t n,\n const int64_t k);\n\nvoid cutlass_scaled_mm_azp(torch::Tensor& out, torch::Tensor const& a,\n torch::Tensor const& b,\n torch::Tensor const& a_scales,\n torch::Tensor const& b_scales,\n torch::Tensor const& azp_adj,\n std::optional<torch::Tensor> const& azp,\n std::optional<torch::Tensor> const& bias);\n\nbool cutlass_sparse_scaled_mm_supported(int64_t cuda_device_capability);\n\nvoid cutlass_scaled_sparse_mm(torch::Tensor& out, torch::Tensor const& a,\n torch::Tensor const& b, torch::Tensor const& e,\n torch::Tensor const& a_scales,\n torch::Tensor const& b_scales,\n std::optional<torch::Tensor> const& bias);\n\nstd::vector<torch::Tensor> cutlass_sparse_compress(torch::Tensor const& a);\n\nvoid scaled_fp4_quant(torch::Tensor& output, torch::Tensor const& input,\n torch::Tensor& output_scale,\n torch::Tensor const& input_scale);\n\nvoid scaled_fp4_experts_quant(\n torch::Tensor& output, torch::Tensor& output_scale,\n torch::Tensor const& input, torch::Tensor const& input_global_scale,\n torch::Tensor const& input_offset_by_experts,\n torch::Tensor const& output_scale_offset_by_experts);\n\nvoid per_token_group_quant_fp8(const torch::Tensor& input,\n torch::Tensor& output_q, torch::Tensor& output_s,\n int64_t group_size, double eps, double fp8_min,\n double fp8_max, bool scale_ue8m0);\n\nvoid per_token_group_quant_int8(const torch::Tensor& input,\n torch::Tensor& output_q,\n torch::Tensor& output_s, int64_t group_size,\n double eps, double int8_min, double int8_max);\n#endif\n\nvoid static_scaled_int8_quant(torch::Tensor& out, torch::Tensor const& input,\n torch::Tensor const& scale,\n std::optional<torch::Tensor> const& azp);\n\nvoid dynamic_scaled_int8_quant(torch::Tensor& out, torch::Tensor const& input,\n torch::Tensor& scales,\n std::optional<torch::Tensor> const& azp);\n\ntorch::Tensor gptq_gemm(torch::Tensor a, torch::Tensor b_q_weight,\n torch::Tensor b_gptq_qzeros,\n torch::Tensor b_gptq_scales, torch::Tensor b_g_idx,\n bool use_exllama, bool use_v2_format, int64_t bit);\n\nvoid gptq_shuffle(torch::Tensor q_weight, torch::Tensor q_perm, int64_t bit);\n\nvoid static_scaled_fp8_quant(torch::Tensor& out, torch::Tensor const& input,\n torch::Tensor const& scale);\n\nvoid dynamic_scaled_fp8_quant(torch::Tensor& out, torch::Tensor const& input,\n torch::Tensor& scale);\n\nvoid dynamic_per_token_scaled_fp8_quant(\n torch::Tensor& out, torch::Tensor const& input, torch::Tensor& scale,\n std::optional<torch::Tensor> const& scale_ub);\n\nvoid selective_scan_fwd(\n const torch::Tensor& u, const torch::Tensor& delta, const torch::Tensor& A,\n const torch::Tensor& B, const torch::Tensor& C,\n const std::optional<torch::Tensor>& D_,\n const std::optional<torch::Tensor>& z_,\n const std::optional<torch::Tensor>& delta_bias_, bool delta_softplus,\n const std::optional<torch::Tensor>& query_start_loc,\n const std::optional<torch::Tensor>& cache_indices,\n const std::optional<torch::Tensor>& has_initial_state,\n const torch::Tensor& ssm_states, int64_t pad_slot_id, int64_t block_size,\n const std::optional<torch::Tensor>& block_idx_first_scheduled_token,\n const std::optional<torch::Tensor>& block_idx_last_scheduled_token,\n const std::optional<torch::Tensor>& initial_state_idx);\n\ntorch::Tensor dynamic_4bit_int_moe_cpu(\n torch::Tensor x, torch::Tensor topk_ids, torch::Tensor topk_weights,\n torch::Tensor w13_packed, torch::Tensor w2_packed, int64_t H, int64_t I,\n int64_t I2, int64_t group_size, bool apply_router_weight_on_input,\n int64_t activation_kind);\n\nusing fptr_t = int64_t;\nfptr_t init_custom_ar(const std::vector<int64_t>& fake_ipc_ptrs,\n torch::Tensor& rank_data, int64_t rank,\n bool fully_connected);\nvoid all_reduce(fptr_t _fa, torch::Tensor& inp, torch::Tensor& out,\n fptr_t reg_buffer, int64_t reg_buffer_sz_bytes);\nvoid dispose(fptr_t _fa);\nint64_t meta_size();\nvoid register_buffer(fptr_t _fa, const std::vector<int64_t>& fake_ipc_ptrs);\nstd::tuple<std::vector<int64_t>, std::vector<int64_t>>\nget_graph_buffer_ipc_meta(fptr_t _fa);\nvoid register_graph_buffers(fptr_t _fa,\n const std::vector<std::vector<int64_t>>& handles,\n const std::vector<std::vector<int64_t>>& offsets);\nstd::tuple<int64_t, torch::Tensor> allocate_shared_buffer_and_handle(\n int64_t size);\nint64_t open_mem_handle(torch::Tensor& mem_handle);\nvoid free_shared_buffer(int64_t buffer);\n\ntorch::Tensor hadacore_transform(torch::Tensor& x, bool inplace);\n\n#ifdef USE_ROCM\nfptr_t init_custom_qr(int64_t rank, int64_t world_size,\n std::optional<int64_t> qr_max_size = std::nullopt);\nvoid qr_destroy(fptr_t _fa);\ntorch::Tensor qr_get_handle(fptr_t _fa);\nvoid qr_open_handles(fptr_t _fa, const std::vector<torch::Tensor>& handles);\nvoid qr_all_reduce(fptr_t _fa, torch::Tensor& inp, torch::Tensor& out,\n int64_t quant_level, bool cast_bf2half = false);\nint64_t qr_max_size();\n#endif\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## Purpose\n\nFused layout transform with per token group quant to get performance\n\nNamely, pack scales into a uint32 earlier and remove an additional kernel call\n\n## Test\n\n`vllm serve deepseek-ai/DeepSeek-V3.1 -tp 8 --enable-expert-parallel --port 9256 --enforce_eager`\n\n### Acc\n\n`lm_eval --model local-completions --model_args \"base_url=http://127.0.0.1:9256/v1/completions,model=deepseek-ai/DeepSeek-V3.1,num_concurrent=1024\" --tasks gsm8k`\n\n```bash\n|Tasks|Version| Filter |n-shot| Metric | |Value | |Stderr|\n|-----|------:|----------------|-----:|-----------|---|-----:|---|-----:|\n|gsm8k| 3|flexible-extract| 5|exact_match|↑ |0.9568|± |0.0056|\n| | |strict-match | 5|exact_match|↑ |0.9568|± |0.0056|\n```\n\n### Perf\n\n`vllm bench serve --model deepseek-ai/DeepSeek-V3.1 --dataset-name random --host 127.0.0.1 --port 9256 --random-input-len 2 --random-output-len 256 --request-rate inf --num-prompts 1024`\n\n```bash\nNow\n============ Serving Benchmark Result ============\nSuccessful requests: 1024 \nFailed requests: 0 \nBenchmark duration (s): 27.94 \nTotal input tokens: 3072 \nTotal generated tokens: 262144 \nRequest throughput (req/s): 36.65 \nOutput token throughput (tok/s): 9382.68 \nPeak output token throughput (tok/s): 10240.00 \nPeak concurrent requests: 1024.00 \nTotal Token throughput (tok/s): 9492.63 \n---------------Time to First Token----------------\nMean TTFT (ms): 1013.22 \nMedian TTFT (ms): 982.19 \nP99 TTFT (ms): 1157.11 \n-----Time per Output Token (excl. 1st token)------\nMean TPOT (ms): 105.02 \nMedian TPOT (ms): 105.08 \nP99 TPOT (ms): 105.26 \n---------------Inter-token Latency----------------\nMean ITL (ms): 105.02 \nMedian ITL (ms): 104.57 \nP99 ITL (ms): 131.10 \n==================================================\n\nMain\n============ Serving Benchmark Result ============\nSuccessful requests: 1024 \nFailed requests: 0 \nBenchmark duration (s): 29.15 \nTotal input tokens: 3072 \nTotal generated tokens: 262144 \nRequest throughput (req/s): 35.13 \nOutput token throughput (tok/s): 8994.31 \nPeak output token throughput (tok/s): 10132.00 \nPeak concurrent requests: 1024.00 \nTotal Token throughput (tok/s): 9099.71 \n---------------Time to First Token----------------\nMean TTFT (ms): 1121.89 \nMedian TTFT (ms): 1144.56 \nP99 TTFT (ms): 1241.25 \n-----Time per Output Token (excl. 1st token)------\nMean TPOT (ms): 109.30 \nMedian TPOT (ms): 109.29 \nP99 TPOT (ms): 109.40 \n---------------Inter-token Latency----------------\nMean ITL (ms): 109.30 \nMedian ITL (ms): 108.89 \nP99 ITL (ms): 125.29 \n==================================================\n```\n\n\n"},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":390,"cells":{"repo":{"kind":"string","value":"vllm"},"commit":{"kind":"string","value":"541a2ef892720489f770569417bc1bc4436dbb21"},"date":{"kind":"string","value":"2025-12-07T07:31:14-05:00"},"pr_number":{"kind":"number","value":29546,"string":"29,546"},"pr_url":{"kind":"string","value":"https://github.com/vllm-project/vllm/pull/29546"},"title":{"kind":"string","value":"[Perf] Deepgemm fused layout kernel for activations, 4.3% throughput improvement, 10.7% TTFT improvement. (#29546)"},"message":{"kind":"string","value":"[Perf] Deepgemm fused layout kernel for activations, 4.3% throughput improvement, 10.7% TTFT improvement. (#29546)\n\nSigned-off-by: yewentao256 <zhyanwentao@126.com>"},"path":{"kind":"string","value":"csrc/quantization/w8a8/fp8/per_token_group_quant.cu"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"#include <ATen/cuda/CUDAContext.h>\n\n#include \"quantization/w8a8/per_token_group_quant_8bit.h\"\n\n#include <cmath>\n\n#include <cuda_fp8.h>\n\n#include <torch/all.h>\n\n#include \"quantization/vectorization.cuh\"\n#include \"quantization/vectorization_utils.cuh\"\n#include \"dispatch_utils.h\"\n\n__device__ __forceinline__ float GroupReduceMax(float val) {\n unsigned mask = threadIdx.x % 32 >= 16 ? 0xffff0000 : 0x0000ffff;\n\n val = fmaxf(val, __shfl_xor_sync(mask, val, 8));\n val = fmaxf(val, __shfl_xor_sync(mask, val, 4));\n val = fmaxf(val, __shfl_xor_sync(mask, val, 2));\n val = fmaxf(val, __shfl_xor_sync(mask, val, 1));\n return val;\n}\n\ntemplate <typename T, typename DST_DTYPE, bool IS_COLUMN_MAJOR = false,\n bool SCALE_UE8M0 = false, typename scale_packed_t = float>\n__global__ void per_token_group_quant_8bit_kernel(\n const T* __restrict__ input, void* __restrict__ output_q,\n scale_packed_t* __restrict__ output_s, const int group_size,\n const int num_groups, const int groups_per_block, const float eps,\n const float min_8bit, const float max_8bit, const int scale_num_rows = 0,\n const int scale_stride = 0) {\n const int threads_per_group = 16;\n const int64_t local_group_id = threadIdx.x / threads_per_group;\n const int lane_id = threadIdx.x % threads_per_group;\n\n const int64_t block_group_id = blockIdx.x * groups_per_block;\n const int64_t global_group_id = block_group_id + local_group_id;\n const int64_t block_group_offset = global_group_id * group_size;\n\n float local_absmax = eps;\n\n using scale_element_t = float;\n static_assert(sizeof(scale_packed_t) % sizeof(scale_element_t) == 0);\n\n const T* group_input = input + block_group_offset;\n DST_DTYPE* group_output =\n static_cast<DST_DTYPE*>(output_q) + block_group_offset;\n scale_element_t* scale_output;\n\n if constexpr (IS_COLUMN_MAJOR) {\n const int num_elems_per_pack =\n static_cast<int>(sizeof(scale_packed_t) / sizeof(scale_element_t));\n const int scale_num_rows_element = scale_num_rows * num_elems_per_pack;\n const int row_idx = global_group_id / scale_num_rows_element;\n const int col_idx_raw = global_group_id % scale_num_rows_element;\n const int col_idx = col_idx_raw / num_elems_per_pack;\n const int pack_idx = col_idx_raw % num_elems_per_pack;\n scale_output = reinterpret_cast<scale_element_t*>(output_s) +\n (col_idx * scale_stride * num_elems_per_pack +\n row_idx * num_elems_per_pack + pack_idx);\n } else {\n scale_output = output_s + global_group_id;\n }\n\n // shared memory to cache each group's data to avoid double DRAM reads.\n extern __shared__ __align__(16) char smem_raw[];\n T* smem = reinterpret_cast<T*>(smem_raw);\n T* smem_group = smem + local_group_id * group_size;\n\n constexpr int vec_size = 16 / sizeof(T);\n using vec_t = vllm::vec_n_t<T, vec_size>;\n\n // copy global -> shared & compute absmax\n auto scalar_op_cache = [&] __device__(T & dst, const T& src) {\n float abs_v = fabsf(static_cast<float>(src));\n local_absmax = fmaxf(local_absmax, abs_v);\n dst = src;\n };\n\n vllm::vectorize_with_alignment<vec_size>(\n group_input, // in\n smem_group, // out (shared)\n group_size, // elements per group\n lane_id, // thread id\n threads_per_group, // stride in group\n scalar_op_cache); // scalar handler\n\n local_absmax = GroupReduceMax(local_absmax);\n\n float y_s = local_absmax / max_8bit;\n if constexpr (SCALE_UE8M0) {\n y_s = exp2f(ceilf(log2f(fmaxf(fabsf(y_s), 1e-10f))));\n }\n\n scale_element_t y_s_quant = y_s;\n\n if (lane_id == 0) {\n *scale_output = y_s_quant;\n }\n\n __syncthreads();\n\n // quantize shared -> global 8-bit\n auto scalar_op_quant = [&] __device__(DST_DTYPE & dst, const T& src) {\n float q = fminf(fmaxf(static_cast<float>(src) / y_s, min_8bit), max_8bit);\n dst = DST_DTYPE(q);\n };\n\n vllm::vectorize_with_alignment<vec_size>(\n smem_group, // in (shared)\n group_output, // out (global quant tensor)\n group_size, // elements\n lane_id, // tid\n threads_per_group, // stride\n scalar_op_quant); // scalar handler\n}\n\nvoid per_token_group_quant_8bit(const torch::Tensor& input,\n torch::Tensor& output_q,\n torch::Tensor& output_s, int64_t group_size,\n double eps, double min_8bit, double max_8bit,\n bool scale_ue8m0) {\n TORCH_CHECK(input.is_contiguous());\n TORCH_CHECK(output_q.is_contiguous());\n\n const int num_groups = input.numel() / group_size;\n\n TORCH_CHECK(input.numel() % group_size == 0);\n TORCH_CHECK(output_s.dim() == 2);\n\n cudaStream_t stream = at::cuda::getCurrentCUDAStream();\n\n constexpr int THREADS_PER_GROUP = 16;\n\n int groups_per_block = 1;\n\n if (num_groups % 16 == 0) {\n groups_per_block = 16;\n } else if (num_groups % 8 == 0) {\n groups_per_block = 8;\n } else if (num_groups % 4 == 0) {\n groups_per_block = 4;\n } else if (num_groups % 2 == 0) {\n groups_per_block = 2;\n }\n\n auto dst_type = output_q.scalar_type();\n const int num_blocks = num_groups / groups_per_block;\n const int num_threads = groups_per_block * THREADS_PER_GROUP;\n\n const bool is_column_major = output_s.stride(0) < output_s.stride(1);\n const int scale_num_rows = output_s.size(1);\n const int scale_stride = output_s.stride(1);\n\n#define LAUNCH_KERNEL(T, DST_DTYPE) \\\n do { \\\n dim3 grid(num_blocks); \\\n dim3 block(num_threads); \\\n size_t smem_bytes = \\\n static_cast<size_t>(groups_per_block) * group_size * sizeof(T); \\\n if (is_column_major) { \\\n if (scale_ue8m0) { \\\n per_token_group_quant_8bit_kernel<T, DST_DTYPE, true, true> \\\n <<<grid, block, smem_bytes, stream>>>( \\\n static_cast<T*>(input.data_ptr()), output_q.data_ptr(), \\\n static_cast<float*>(output_s.data_ptr()), group_size, \\\n num_groups, groups_per_block, (float)eps, (float)min_8bit, \\\n (float)max_8bit, scale_num_rows, scale_stride); \\\n } else { \\\n per_token_group_quant_8bit_kernel<T, DST_DTYPE, true, false> \\\n <<<grid, block, smem_bytes, stream>>>( \\\n static_cast<T*>(input.data_ptr()), output_q.data_ptr(), \\\n static_cast<float*>(output_s.data_ptr()), group_size, \\\n num_groups, groups_per_block, (float)eps, (float)min_8bit, \\\n (float)max_8bit, scale_num_rows, scale_stride); \\\n } \\\n } else { \\\n if (scale_ue8m0) { \\\n per_token_group_quant_8bit_kernel<T, DST_DTYPE, false, true> \\\n <<<grid, block, smem_bytes, stream>>>( \\\n static_cast<T*>(input.data_ptr()), output_q.data_ptr(), \\\n static_cast<float*>(output_s.data_ptr()), group_size, \\\n num_groups, groups_per_block, (float)eps, (float)min_8bit, \\\n (float)max_8bit); \\\n } else { \\\n per_token_group_quant_8bit_kernel<T, DST_DTYPE, false, false> \\\n <<<grid, block, smem_bytes, stream>>>( \\\n static_cast<T*>(input.data_ptr()), output_q.data_ptr(), \\\n static_cast<float*>(output_s.data_ptr()), group_size, \\\n num_groups, groups_per_block, (float)eps, (float)min_8bit, \\\n (float)max_8bit); \\\n } \\\n } \\\n } while (0)\n\n VLLM_DISPATCH_FLOATING_TYPES(\n input.scalar_type(), \"per_token_group_quant_8bit\", ([&] {\n if (dst_type == at::ScalarType::Float8_e4m3fn) {\n LAUNCH_KERNEL(scalar_t, __nv_fp8_e4m3);\n } else if (dst_type == at::ScalarType::Char) {\n LAUNCH_KERNEL(scalar_t, int8_t);\n }\n }));\n\n#undef LAUNCH_KERNEL\n}\n\nvoid per_token_group_quant_fp8(const torch::Tensor& input,\n torch::Tensor& output_q, torch::Tensor& output_s,\n int64_t group_size, double eps, double fp8_min,\n double fp8_max, bool scale_ue8m0) {\n per_token_group_quant_8bit(input, output_q, output_s, group_size, eps,\n fp8_min, fp8_max, scale_ue8m0);\n}"},"after_code":{"kind":"string","value":"#include <ATen/cuda/CUDAContext.h>\n\n#include \"quantization/w8a8/per_token_group_quant_8bit.h\"\n\n#include <cmath>\n\n#include <cuda_fp8.h>\n\n#include <torch/all.h>\n\n#include \"quantization/vectorization.cuh\"\n#include \"quantization/vectorization_utils.cuh\"\n#include \"dispatch_utils.h\"\n\n__device__ __forceinline__ float GroupReduceMax(float val) {\n unsigned mask = threadIdx.x % 32 >= 16 ? 0xffff0000 : 0x0000ffff;\n\n val = fmaxf(val, __shfl_xor_sync(mask, val, 8));\n val = fmaxf(val, __shfl_xor_sync(mask, val, 4));\n val = fmaxf(val, __shfl_xor_sync(mask, val, 2));\n val = fmaxf(val, __shfl_xor_sync(mask, val, 1));\n return val;\n}\n\ntemplate <typename T, typename DST_DTYPE, bool IS_COLUMN_MAJOR = false,\n bool SCALE_UE8M0 = false, typename scale_packed_t = float>\n__global__ void per_token_group_quant_8bit_kernel(\n const T* __restrict__ input, void* __restrict__ output_q,\n scale_packed_t* __restrict__ output_s, const int group_size,\n const int num_groups, const int groups_per_block, const float eps,\n const float min_8bit, const float max_8bit, const int scale_num_rows = 0,\n const int scale_stride = 0) {\n const int threads_per_group = 16;\n const int64_t local_group_id = threadIdx.x / threads_per_group;\n const int lane_id = threadIdx.x % threads_per_group;\n\n const int64_t block_group_id = blockIdx.x * groups_per_block;\n const int64_t global_group_id = block_group_id + local_group_id;\n const int64_t block_group_offset = global_group_id * group_size;\n\n float local_absmax = eps;\n\n using scale_element_t = float;\n static_assert(sizeof(scale_packed_t) % sizeof(scale_element_t) == 0);\n\n const T* group_input = input + block_group_offset;\n DST_DTYPE* group_output =\n static_cast<DST_DTYPE*>(output_q) + block_group_offset;\n scale_element_t* scale_output;\n\n if constexpr (IS_COLUMN_MAJOR) {\n const int num_elems_per_pack =\n static_cast<int>(sizeof(scale_packed_t) / sizeof(scale_element_t));\n const int scale_num_rows_element = scale_num_rows * num_elems_per_pack;\n const int row_idx = global_group_id / scale_num_rows_element;\n const int col_idx_raw = global_group_id % scale_num_rows_element;\n const int col_idx = col_idx_raw / num_elems_per_pack;\n const int pack_idx = col_idx_raw % num_elems_per_pack;\n scale_output = reinterpret_cast<scale_element_t*>(output_s) +\n (col_idx * scale_stride * num_elems_per_pack +\n row_idx * num_elems_per_pack + pack_idx);\n } else {\n scale_output = output_s + global_group_id;\n }\n\n // shared memory to cache each group's data to avoid double DRAM reads.\n extern __shared__ __align__(16) char smem_raw[];\n T* smem = reinterpret_cast<T*>(smem_raw);\n T* smem_group = smem + local_group_id * group_size;\n\n constexpr int vec_size = 16 / sizeof(T);\n using vec_t = vllm::vec_n_t<T, vec_size>;\n\n // copy global -> shared & compute absmax\n auto scalar_op_cache = [&] __device__(T & dst, const T& src) {\n float abs_v = fabsf(static_cast<float>(src));\n local_absmax = fmaxf(local_absmax, abs_v);\n dst = src;\n };\n\n vllm::vectorize_with_alignment<vec_size>(\n group_input, // in\n smem_group, // out (shared)\n group_size, // elements per group\n lane_id, // thread id\n threads_per_group, // stride in group\n scalar_op_cache); // scalar handler\n\n local_absmax = GroupReduceMax(local_absmax);\n\n float y_s = local_absmax / max_8bit;\n if constexpr (SCALE_UE8M0) {\n y_s = exp2f(ceilf(log2f(fmaxf(fabsf(y_s), 1e-10f))));\n }\n\n scale_element_t y_s_quant = y_s;\n\n if (lane_id == 0) {\n *scale_output = y_s_quant;\n }\n\n __syncthreads();\n\n // quantize shared -> global 8-bit\n auto scalar_op_quant = [&] __device__(DST_DTYPE & dst, const T& src) {\n float q = fminf(fmaxf(static_cast<float>(src) / y_s, min_8bit), max_8bit);\n dst = DST_DTYPE(q);\n };\n\n vllm::vectorize_with_alignment<vec_size>(\n smem_group, // in (shared)\n group_output, // out (global quant tensor)\n group_size, // elements\n lane_id, // tid\n threads_per_group, // stride\n scalar_op_quant); // scalar handler\n}\n\nvoid per_token_group_quant_8bit(const torch::Tensor& input,\n torch::Tensor& output_q,\n torch::Tensor& output_s, int64_t group_size,\n double eps, double min_8bit, double max_8bit,\n bool scale_ue8m0) {\n TORCH_CHECK(input.is_contiguous());\n TORCH_CHECK(output_q.is_contiguous());\n\n const int num_groups = input.numel() / group_size;\n\n TORCH_CHECK(input.numel() % group_size == 0);\n TORCH_CHECK(output_s.dim() == 2);\n\n cudaStream_t stream = at::cuda::getCurrentCUDAStream();\n\n constexpr int THREADS_PER_GROUP = 16;\n\n int groups_per_block = 1;\n\n if (num_groups % 16 == 0) {\n groups_per_block = 16;\n } else if (num_groups % 8 == 0) {\n groups_per_block = 8;\n } else if (num_groups % 4 == 0) {\n groups_per_block = 4;\n } else if (num_groups % 2 == 0) {\n groups_per_block = 2;\n }\n\n auto dst_type = output_q.scalar_type();\n const int num_blocks = num_groups / groups_per_block;\n const int num_threads = groups_per_block * THREADS_PER_GROUP;\n\n const bool is_column_major = output_s.stride(0) < output_s.stride(1);\n const int scale_num_rows = output_s.size(1);\n const int scale_stride = output_s.stride(1);\n\n#define LAUNCH_KERNEL(T, DST_DTYPE) \\\n do { \\\n dim3 grid(num_blocks); \\\n dim3 block(num_threads); \\\n size_t smem_bytes = \\\n static_cast<size_t>(groups_per_block) * group_size * sizeof(T); \\\n if (is_column_major) { \\\n if (scale_ue8m0) { \\\n per_token_group_quant_8bit_kernel<T, DST_DTYPE, true, true> \\\n <<<grid, block, smem_bytes, stream>>>( \\\n static_cast<T*>(input.data_ptr()), output_q.data_ptr(), \\\n static_cast<float*>(output_s.data_ptr()), group_size, \\\n num_groups, groups_per_block, (float)eps, (float)min_8bit, \\\n (float)max_8bit, scale_num_rows, scale_stride); \\\n } else { \\\n per_token_group_quant_8bit_kernel<T, DST_DTYPE, true, false> \\\n <<<grid, block, smem_bytes, stream>>>( \\\n static_cast<T*>(input.data_ptr()), output_q.data_ptr(), \\\n static_cast<float*>(output_s.data_ptr()), group_size, \\\n num_groups, groups_per_block, (float)eps, (float)min_8bit, \\\n (float)max_8bit, scale_num_rows, scale_stride); \\\n } \\\n } else { \\\n if (scale_ue8m0) { \\\n per_token_group_quant_8bit_kernel<T, DST_DTYPE, false, true> \\\n <<<grid, block, smem_bytes, stream>>>( \\\n static_cast<T*>(input.data_ptr()), output_q.data_ptr(), \\\n static_cast<float*>(output_s.data_ptr()), group_size, \\\n num_groups, groups_per_block, (float)eps, (float)min_8bit, \\\n (float)max_8bit); \\\n } else { \\\n per_token_group_quant_8bit_kernel<T, DST_DTYPE, false, false> \\\n <<<grid, block, smem_bytes, stream>>>( \\\n static_cast<T*>(input.data_ptr()), output_q.data_ptr(), \\\n static_cast<float*>(output_s.data_ptr()), group_size, \\\n num_groups, groups_per_block, (float)eps, (float)min_8bit, \\\n (float)max_8bit); \\\n } \\\n } \\\n } while (0)\n\n VLLM_DISPATCH_FLOATING_TYPES(\n input.scalar_type(), \"per_token_group_quant_8bit\", ([&] {\n if (dst_type == at::ScalarType::Float8_e4m3fn) {\n LAUNCH_KERNEL(scalar_t, __nv_fp8_e4m3);\n } else if (dst_type == at::ScalarType::Char) {\n LAUNCH_KERNEL(scalar_t, int8_t);\n }\n }));\n\n#undef LAUNCH_KERNEL\n}\n\ntemplate <typename T, typename DST_DTYPE>\n__global__ void per_token_group_quant_8bit_packed_kernel(\n const T* __restrict__ input, void* __restrict__ output_q,\n unsigned int* __restrict__ output_s_packed, const int group_size,\n const int num_groups, const int groups_per_block, const int groups_per_row,\n const int mn, const int tma_aligned_mn, const float eps,\n const float min_8bit, const float max_8bit) {\n const int threads_per_group = 16;\n const int64_t local_group_id = threadIdx.x / threads_per_group;\n const int lane_id = threadIdx.x % threads_per_group;\n\n const int64_t block_group_id = blockIdx.x * groups_per_block;\n const int64_t global_group_id = block_group_id + local_group_id;\n if (global_group_id >= num_groups) {\n return;\n }\n\n const int64_t block_group_offset = global_group_id * group_size;\n\n float local_absmax = eps;\n\n const T* group_input = input + block_group_offset;\n DST_DTYPE* group_output =\n static_cast<DST_DTYPE*>(output_q) + block_group_offset;\n\n // shared memory to cache each group's data to avoid double DRAM reads.\n extern __shared__ __align__(16) char smem_raw[];\n T* smem = reinterpret_cast<T*>(smem_raw);\n T* smem_group = smem + local_group_id * group_size;\n\n constexpr int vec_size = 16 / sizeof(T);\n using vec_t = vllm::vec_n_t<T, vec_size>;\n\n // copy global -> shared & compute absmax\n auto scalar_op_cache = [&] __device__(T & dst, const T& src) {\n float abs_v = fabsf(static_cast<float>(src));\n local_absmax = fmaxf(local_absmax, abs_v);\n dst = src;\n };\n\n vllm::vectorize_with_alignment<vec_size>(\n group_input, // in\n smem_group, // out (shared)\n group_size, // elements per group\n lane_id, // thread id\n threads_per_group, // stride in group\n scalar_op_cache); // scalar handler\n\n local_absmax = GroupReduceMax(local_absmax);\n\n float y_s = local_absmax / max_8bit;\n y_s = exp2f(ceilf(log2f(fmaxf(fabsf(y_s), 1e-10f))));\n\n // pack 4 scales into a uint32\n if (lane_id == 0) {\n // map flat group id to 2D indices (mn_idx, sf_k_idx)\n const int sf_k_idx = static_cast<int>(global_group_id % groups_per_row);\n const int mn_idx = static_cast<int>(global_group_id / groups_per_row);\n\n if (mn_idx < mn) {\n // each uint32 in output_s_packed stores 4 packed scales\n const int sf_k_pack_idx = sf_k_idx / 4;\n const int pos = sf_k_idx % 4;\n\n // reinterpret the UE8M0 scale y_s as IEEE bits, extract the 8-bit\n // exponent, and place it into the correct byte of the 32-bit word.\n const unsigned int bits = __float_as_uint(y_s);\n const unsigned int exponent = (bits >> 23u) & 0xffu;\n const unsigned int contrib = exponent << (pos * 8u);\n\n const int out_idx = sf_k_pack_idx * tma_aligned_mn + mn_idx;\n // atomically OR 8-bit exponent into the packed scales buffer\n atomicOr(output_s_packed + out_idx, contrib);\n }\n }\n\n __syncthreads();\n\n // quantize shared -> global 8-bit\n auto scalar_op_quant = [&] __device__(DST_DTYPE & dst, const T& src) {\n float q = fminf(fmaxf(static_cast<float>(src) / y_s, min_8bit), max_8bit);\n dst = DST_DTYPE(q);\n };\n\n vllm::vectorize_with_alignment<vec_size>(\n smem_group, // in (shared)\n group_output, // out (global quant tensor)\n group_size, // elements\n lane_id, // tid\n threads_per_group, // stride\n scalar_op_quant); // scalar handler\n}\n\nvoid per_token_group_quant_8bit_packed(const torch::Tensor& input,\n torch::Tensor& output_q,\n torch::Tensor& output_s_packed,\n int64_t group_size, double eps,\n double min_8bit, double max_8bit) {\n TORCH_CHECK(input.is_contiguous());\n TORCH_CHECK(output_q.is_contiguous());\n\n const int64_t k = input.size(-1);\n TORCH_CHECK(k % group_size == 0, \"Last dimension (\", k,\n \") must be divisible by group_size (\", group_size, \").\");\n\n const int64_t mn = input.numel() / k;\n const int64_t groups_per_row = k / group_size;\n const int64_t num_groups = mn * groups_per_row;\n\n TORCH_CHECK(output_s_packed.dim() == 2,\n \"output_s_packed must be 2D, got dim=\", output_s_packed.dim(),\n \".\");\n\n const int64_t k_num_packed_sfk = (groups_per_row + 3) / 4;\n const int64_t tma_aligned_mn = ((mn + 3) / 4) * 4;\n\n TORCH_CHECK(output_s_packed.scalar_type() == at::ScalarType::Int,\n \"output_s_packed must have dtype int32 for UE8M0-packed scales.\");\n // DeepGEMM expects SFA scales in MN-major form with shape\n // [mn, ceil_div(K, 128 * 4)] and TMA-aligned stride on the last\n // dimension.\n TORCH_CHECK(output_s_packed.size(0) == mn &&\n output_s_packed.size(1) == k_num_packed_sfk,\n \"output_s_packed shape must be [\", mn, \", \", k_num_packed_sfk,\n \"], but got [\", output_s_packed.size(0), \", \",\n output_s_packed.size(1), \"].\");\n\n cudaStream_t stream = at::cuda::getCurrentCUDAStream();\n\n constexpr int THREADS_PER_GROUP = 16;\n\n int groups_per_block = 1;\n\n if (num_groups % 16 == 0) {\n groups_per_block = 16;\n } else if (num_groups % 8 == 0) {\n groups_per_block = 8;\n } else if (num_groups % 4 == 0) {\n groups_per_block = 4;\n } else if (num_groups % 2 == 0) {\n groups_per_block = 2;\n }\n\n auto dst_type = output_q.scalar_type();\n const int num_blocks = num_groups / groups_per_block;\n const int num_threads = groups_per_block * THREADS_PER_GROUP;\n\n // zero-initialize packed scales, since we use atomicOr to accumulate\n // exponents from different groups.\n output_s_packed.zero_();\n\n#define LAUNCH_PACKED_KERNEL(T, DST_DTYPE) \\\n do { \\\n dim3 grid(num_blocks); \\\n dim3 block(num_threads); \\\n size_t smem_bytes = \\\n static_cast<size_t>(groups_per_block) * group_size * sizeof(T); \\\n per_token_group_quant_8bit_packed_kernel<T, DST_DTYPE> \\\n <<<grid, block, smem_bytes, stream>>>( \\\n static_cast<const T*>(input.data_ptr()), output_q.data_ptr(), \\\n reinterpret_cast<unsigned int*>(output_s_packed.data_ptr()), \\\n static_cast<int>(group_size), static_cast<int>(num_groups), \\\n groups_per_block, static_cast<int>(groups_per_row), \\\n static_cast<int>(mn), static_cast<int>(tma_aligned_mn), \\\n static_cast<float>(eps), static_cast<float>(min_8bit), \\\n static_cast<float>(max_8bit)); \\\n } while (0)\n\n VLLM_DISPATCH_FLOATING_TYPES(\n input.scalar_type(), \"per_token_group_quant_8bit_packed\", ([&] {\n if (dst_type == at::ScalarType::Float8_e4m3fn) {\n LAUNCH_PACKED_KERNEL(scalar_t, __nv_fp8_e4m3);\n } else if (dst_type == at::ScalarType::Char) {\n LAUNCH_PACKED_KERNEL(scalar_t, int8_t);\n } else {\n TORCH_CHECK(\n false,\n \"per_token_group_quant_8bit_packed only supports FP8/INT8 \"\n \"outputs.\");\n }\n }));\n\n#undef LAUNCH_PACKED_KERNEL\n}\n\nvoid per_token_group_quant_fp8(const torch::Tensor& input,\n torch::Tensor& output_q, torch::Tensor& output_s,\n int64_t group_size, double eps, double fp8_min,\n double fp8_max, bool scale_ue8m0) {\n per_token_group_quant_8bit(input, output_q, output_s, group_size, eps,\n fp8_min, fp8_max, scale_ue8m0);\n}"},"diff":{"kind":"string","value":"--- csrc/quantization/w8a8/fp8/per_token_group_quant.cu\n+++ csrc/quantization/w8a8/fp8/per_token_group_quant.cu\n@@ -206,6 +206,191 @@\n #undef LAUNCH_KERNEL\n }\n \n+template <typename T, typename DST_DTYPE>\n+__global__ void per_token_group_quant_8bit_packed_kernel(\n+ const T* __restrict__ input, void* __restrict__ output_q,\n+ unsigned int* __restrict__ output_s_packed, const int group_size,\n+ const int num_groups, const int groups_per_block, const int groups_per_row,\n+ const int mn, const int tma_aligned_mn, const float eps,\n+ const float min_8bit, const float max_8bit) {\n+ const int threads_per_group = 16;\n+ const int64_t local_group_id = threadIdx.x / threads_per_group;\n+ const int lane_id = threadIdx.x % threads_per_group;\n+\n+ const int64_t block_group_id = blockIdx.x * groups_per_block;\n+ const int64_t global_group_id = block_group_id + local_group_id;\n+ if (global_group_id >= num_groups) {\n+ return;\n+ }\n+\n+ const int64_t block_group_offset = global_group_id * group_size;\n+\n+ float local_absmax = eps;\n+\n+ const T* group_input = input + block_group_offset;\n+ DST_DTYPE* group_output =\n+ static_cast<DST_DTYPE*>(output_q) + block_group_offset;\n+\n+ // shared memory to cache each group's data to avoid double DRAM reads.\n+ extern __shared__ __align__(16) char smem_raw[];\n+ T* smem = reinterpret_cast<T*>(smem_raw);\n+ T* smem_group = smem + local_group_id * group_size;\n+\n+ constexpr int vec_size = 16 / sizeof(T);\n+ using vec_t = vllm::vec_n_t<T, vec_size>;\n+\n+ // copy global -> shared & compute absmax\n+ auto scalar_op_cache = [&] __device__(T & dst, const T& src) {\n+ float abs_v = fabsf(static_cast<float>(src));\n+ local_absmax = fmaxf(local_absmax, abs_v);\n+ dst = src;\n+ };\n+\n+ vllm::vectorize_with_alignment<vec_size>(\n+ group_input, // in\n+ smem_group, // out (shared)\n+ group_size, // elements per group\n+ lane_id, // thread id\n+ threads_per_group, // stride in group\n+ scalar_op_cache); // scalar handler\n+\n+ local_absmax = GroupReduceMax(local_absmax);\n+\n+ float y_s = local_absmax / max_8bit;\n+ y_s = exp2f(ceilf(log2f(fmaxf(fabsf(y_s), 1e-10f))));\n+\n+ // pack 4 scales into a uint32\n+ if (lane_id == 0) {\n+ // map flat group id to 2D indices (mn_idx, sf_k_idx)\n+ const int sf_k_idx = static_cast<int>(global_group_id % groups_per_row);\n+ const int mn_idx = static_cast<int>(global_group_id / groups_per_row);\n+\n+ if (mn_idx < mn) {\n+ // each uint32 in output_s_packed stores 4 packed scales\n+ const int sf_k_pack_idx = sf_k_idx / 4;\n+ const int pos = sf_k_idx % 4;\n+\n+ // reinterpret the UE8M0 scale y_s as IEEE bits, extract the 8-bit\n+ // exponent, and place it into the correct byte of the 32-bit word.\n+ const unsigned int bits = __float_as_uint(y_s);\n+ const unsigned int exponent = (bits >> 23u) & 0xffu;\n+ const unsigned int contrib = exponent << (pos * 8u);\n+\n+ const int out_idx = sf_k_pack_idx * tma_aligned_mn + mn_idx;\n+ // atomically OR 8-bit exponent into the packed scales buffer\n+ atomicOr(output_s_packed + out_idx, contrib);\n+ }\n+ }\n+\n+ __syncthreads();\n+\n+ // quantize shared -> global 8-bit\n+ auto scalar_op_quant = [&] __device__(DST_DTYPE & dst, const T& src) {\n+ float q = fminf(fmaxf(static_cast<float>(src) / y_s, min_8bit), max_8bit);\n+ dst = DST_DTYPE(q);\n+ };\n+\n+ vllm::vectorize_with_alignment<vec_size>(\n+ smem_group, // in (shared)\n+ group_output, // out (global quant tensor)\n+ group_size, // elements\n+ lane_id, // tid\n+ threads_per_group, // stride\n+ scalar_op_quant); // scalar handler\n+}\n+\n+void per_token_group_quant_8bit_packed(const torch::Tensor& input,\n+ torch::Tensor& output_q,\n+ torch::Tensor& output_s_packed,\n+ int64_t group_size, double eps,\n+ double min_8bit, double max_8bit) {\n+ TORCH_CHECK(input.is_contiguous());\n+ TORCH_CHECK(output_q.is_contiguous());\n+\n+ const int64_t k = input.size(-1);\n+ TORCH_CHECK(k % group_size == 0, \"Last dimension (\", k,\n+ \") must be divisible by group_size (\", group_size, \").\");\n+\n+ const int64_t mn = input.numel() / k;\n+ const int64_t groups_per_row = k / group_size;\n+ const int64_t num_groups = mn * groups_per_row;\n+\n+ TORCH_CHECK(output_s_packed.dim() == 2,\n+ \"output_s_packed must be 2D, got dim=\", output_s_packed.dim(),\n+ \".\");\n+\n+ const int64_t k_num_packed_sfk = (groups_per_row + 3) / 4;\n+ const int64_t tma_aligned_mn = ((mn + 3) / 4) * 4;\n+\n+ TORCH_CHECK(output_s_packed.scalar_type() == at::ScalarType::Int,\n+ \"output_s_packed must have dtype int32 for UE8M0-packed scales.\");\n+ // DeepGEMM expects SFA scales in MN-major form with shape\n+ // [mn, ceil_div(K, 128 * 4)] and TMA-aligned stride on the last\n+ // dimension.\n+ TORCH_CHECK(output_s_packed.size(0) == mn &&\n+ output_s_packed.size(1) == k_num_packed_sfk,\n+ \"output_s_packed shape must be [\", mn, \", \", k_num_packed_sfk,\n+ \"], but got [\", output_s_packed.size(0), \", \",\n+ output_s_packed.size(1), \"].\");\n+\n+ cudaStream_t stream = at::cuda::getCurrentCUDAStream();\n+\n+ constexpr int THREADS_PER_GROUP = 16;\n+\n+ int groups_per_block = 1;\n+\n+ if (num_groups % 16 == 0) {\n+ groups_per_block = 16;\n+ } else if (num_groups % 8 == 0) {\n+ groups_per_block = 8;\n+ } else if (num_groups % 4 == 0) {\n+ groups_per_block = 4;\n+ } else if (num_groups % 2 == 0) {\n+ groups_per_block = 2;\n+ }\n+\n+ auto dst_type = output_q.scalar_type();\n+ const int num_blocks = num_groups / groups_per_block;\n+ const int num_threads = groups_per_block * THREADS_PER_GROUP;\n+\n+ // zero-initialize packed scales, since we use atomicOr to accumulate\n+ // exponents from different groups.\n+ output_s_packed.zero_();\n+\n+#define LAUNCH_PACKED_KERNEL(T, DST_DTYPE) \\\n+ do { \\\n+ dim3 grid(num_blocks); \\\n+ dim3 block(num_threads); \\\n+ size_t smem_bytes = \\\n+ static_cast<size_t>(groups_per_block) * group_size * sizeof(T); \\\n+ per_token_group_quant_8bit_packed_kernel<T, DST_DTYPE> \\\n+ <<<grid, block, smem_bytes, stream>>>( \\\n+ static_cast<const T*>(input.data_ptr()), output_q.data_ptr(), \\\n+ reinterpret_cast<unsigned int*>(output_s_packed.data_ptr()), \\\n+ static_cast<int>(group_size), static_cast<int>(num_groups), \\\n+ groups_per_block, static_cast<int>(groups_per_row), \\\n+ static_cast<int>(mn), static_cast<int>(tma_aligned_mn), \\\n+ static_cast<float>(eps), static_cast<float>(min_8bit), \\\n+ static_cast<float>(max_8bit)); \\\n+ } while (0)\n+\n+ VLLM_DISPATCH_FLOATING_TYPES(\n+ input.scalar_type(), \"per_token_group_quant_8bit_packed\", ([&] {\n+ if (dst_type == at::ScalarType::Float8_e4m3fn) {\n+ LAUNCH_PACKED_KERNEL(scalar_t, __nv_fp8_e4m3);\n+ } else if (dst_type == at::ScalarType::Char) {\n+ LAUNCH_PACKED_KERNEL(scalar_t, int8_t);\n+ } else {\n+ TORCH_CHECK(\n+ false,\n+ \"per_token_group_quant_8bit_packed only supports FP8/INT8 \"\n+ \"outputs.\");\n+ }\n+ }));\n+\n+#undef LAUNCH_PACKED_KERNEL\n+}\n+\n void per_token_group_quant_fp8(const torch::Tensor& input,\n torch::Tensor& output_q, torch::Tensor& output_s,\n int64_t group_size, double eps, double fp8_min,"},"lines_added":{"kind":"number","value":185,"string":"185"},"lines_removed":{"kind":"number","value":0,"string":"0"},"files_in_commit":{"kind":"number","value":5,"string":"5"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from vllm (csrc/quantization/w8a8/fp8/per_token_group_quant.cu).\n\nGoal: [Perf] Deepgemm fused layout kernel for activations, 4.3% throughput improvement, 10.7% TTFT improvement.\nTarget hardware: unspecified\nTarget models: unspecified\n\nCurrent file:\n```cuda\n#include <ATen/cuda/CUDAContext.h>\n\n#include \"quantization/w8a8/per_token_group_quant_8bit.h\"\n\n#include <cmath>\n\n#include <cuda_fp8.h>\n\n#include <torch/all.h>\n\n#include \"quantization/vectorization.cuh\"\n#include \"quantization/vectorization_utils.cuh\"\n#include \"dispatch_utils.h\"\n\n__device__ __forceinline__ float GroupReduceMax(float val) {\n unsigned mask = threadIdx.x % 32 >= 16 ? 0xffff0000 : 0x0000ffff;\n\n val = fmaxf(val, __shfl_xor_sync(mask, val, 8));\n val = fmaxf(val, __shfl_xor_sync(mask, val, 4));\n val = fmaxf(val, __shfl_xor_sync(mask, val, 2));\n val = fmaxf(val, __shfl_xor_sync(mask, val, 1));\n return val;\n}\n\ntemplate <typename T, typename DST_DTYPE, bool IS_COLUMN_MAJOR = false,\n bool SCALE_UE8M0 = false, typename scale_packed_t = float>\n__global__ void per_token_group_quant_8bit_kernel(\n const T* __restrict__ input, void* __restrict__ output_q,\n scale_packed_t* __restrict__ output_s, const int group_size,\n const int num_groups, const int groups_per_block, const float eps,\n const float min_8bit, const float max_8bit, const int scale_num_rows = 0,\n const int scale_stride = 0) {\n const int threads_per_group = 16;\n const int64_t local_group_id = threadIdx.x / threads_per_group;\n const int lane_id = threadIdx.x % threads_per_group;\n\n const int64_t block_group_id = blockIdx.x * groups_per_block;\n const int64_t global_group_id = block_group_id + local_group_id;\n const int64_t block_group_offset = global_group_id * group_size;\n\n float local_absmax = eps;\n\n using scale_element_t = float;\n static_assert(sizeof(scale_packed_t) % sizeof(scale_element_t) == 0);\n\n const T* group_input = input + block_group_offset;\n DST_DTYPE* group_output =\n static_cast<DST_DTYPE*>(output_q) + block_group_offset;\n scale_element_t* scale_output;\n\n if constexpr (IS_COLUMN_MAJOR) {\n const int num_elems_per_pack =\n static_cast<int>(sizeof(scale_packed_t) / sizeof(scale_element_t));\n const int scale_num_rows_element = scale_num_rows * num_elems_per_pack;\n const int row_idx = global_group_id / scale_num_rows_element;\n const int col_idx_raw = global_group_id % scale_num_rows_element;\n const int col_idx = col_idx_raw / num_elems_per_pack;\n const int pack_idx = col_idx_raw % num_elems_per_pack;\n scale_output = reinterpret_cast<scale_element_t*>(output_s) +\n (col_idx * scale_stride * num_elems_per_pack +\n row_idx * num_elems_per_pack + pack_idx);\n } else {\n scale_output = output_s + global_group_id;\n }\n\n // shared memory to cache each group's data to avoid double DRAM reads.\n extern __shared__ __align__(16) char smem_raw[];\n T* smem = reinterpret_cast<T*>(smem_raw);\n T* smem_group = smem + local_group_id * group_size;\n\n constexpr int vec_size = 16 / sizeof(T);\n using vec_t = vllm::vec_n_t<T, vec_size>;\n\n // copy global -> shared & compute absmax\n auto scalar_op_cache = [&] __device__(T & dst, const T& src) {\n float abs_v = fabsf(static_cast<float>(src));\n local_absmax = fmaxf(local_absmax, abs_v);\n dst = src;\n };\n\n vllm::vectorize_with_alignment<vec_size>(\n group_input, // in\n smem_group, // out (shared)\n group_size, // elements per group\n lane_id, // thread id\n threads_per_group, // stride in group\n scalar_op_cache); // scalar handler\n\n local_absmax = GroupReduceMax(local_absmax);\n\n float y_s = local_absmax / max_8bit;\n if constexpr (SCALE_UE8M0) {\n y_s = exp2f(ceilf(log2f(fmaxf(fabsf(y_s), 1e-10f))));\n }\n\n scale_element_t y_s_quant = y_s;\n\n if (lane_id == 0) {\n *scale_output = y_s_quant;\n }\n\n __syncthreads();\n\n // quantize shared -> global 8-bit\n auto scalar_op_quant = [&] __device__(DST_DTYPE & dst, const T& src) {\n float q = fminf(fmaxf(static_cast<float>(src) / y_s, min_8bit), max_8bit);\n dst = DST_DTYPE(q);\n };\n\n vllm::vectorize_with_alignment<vec_size>(\n smem_group, // in (shared)\n group_output, // out (global quant tensor)\n group_size, // elements\n lane_id, // tid\n threads_per_group, // stride\n scalar_op_quant); // scalar handler\n}\n\nvoid per_token_group_quant_8bit(const torch::Tensor& input,\n torch::Tensor& output_q,\n torch::Tensor& output_s, int64_t group_size,\n double eps, double min_8bit, double max_8bit,\n bool scale_ue8m0) {\n TORCH_CHECK(input.is_contiguous());\n TORCH_CHECK(output_q.is_contiguous());\n\n const int num_groups = input.numel() / group_size;\n\n TORCH_CHECK(input.numel() % group_size == 0);\n TORCH_CHECK(output_s.dim() == 2);\n\n cudaStream_t stream = at::cuda::getCurrentCUDAStream();\n\n constexpr int THREADS_PER_GROUP = 16;\n\n int groups_per_block = 1;\n\n if (num_groups % 16 == 0) {\n groups_per_block = 16;\n } else if (num_groups % 8 == 0) {\n groups_per_block = 8;\n } else if (num_groups % 4 == 0) {\n groups_per_block = 4;\n } else if (num_groups % 2 == 0) {\n groups_per_block = 2;\n }\n\n auto dst_type = output_q.scalar_type();\n const int num_blocks = num_groups / groups_per_block;\n const int num_threads = groups_per_block * THREADS_PER_GROUP;\n\n const bool is_column_major = output_s.stride(0) < output_s.stride(1);\n const int scale_num_rows = output_s.size(1);\n const int scale_stride = output_s.stride(1);\n\n#define LAUNCH_KERNEL(T, DST_DTYPE) \\\n do { \\\n dim3 grid(num_blocks); \\\n dim3 block(num_threads); \\\n size_t smem_bytes = \\\n static_cast<size_t>(groups_per_block) * group_size * sizeof(T); \\\n if (is_column_major) { \\\n if (scale_ue8m0) { \\\n per_token_group_quant_8bit_kernel<T, DST_DTYPE, true, true> \\\n <<<grid, block, smem_bytes, stream>>>( \\\n static_cast<T*>(input.data_ptr()), output_q.data_ptr(), \\\n static_cast<float*>(output_s.data_ptr()), group_size, \\\n num_groups, groups_per_block, (float)eps, (float)min_8bit, \\\n (float)max_8bit, scale_num_rows, scale_stride); \\\n } else { \\\n per_token_group_quant_8bit_kernel<T, DST_DTYPE, true, false> \\\n <<<grid, block, smem_bytes, stream>>>( \\\n static_cast<T*>(input.data_ptr()), output_q.data_ptr(), \\\n static_cast<float*>(output_s.data_ptr()), group_size, \\\n num_groups, groups_per_block, (float)eps, (float)min_8bit, \\\n (float)max_8bit, scale_num_rows, scale_stride); \\\n } \\\n } else { \\\n if (scale_ue8m0) { \\\n per_token_group_quant_8bit_kernel<T, DST_DTYPE, false, true> \\\n <<<grid, block, smem_bytes, stream>>>( \\\n static_cast<T*>(input.data_ptr()), output_q.data_ptr(), \\\n static_cast<float*>(output_s.data_ptr()), group_size, \\\n num_groups, groups_per_block, (float)eps, (float)min_8bit, \\\n (float)max_8bit); \\\n } else { \\\n per_token_group_quant_8bit_kernel<T, DST_DTYPE, false, false> \\\n <<<grid, block, smem_bytes, stream>>>( \\\n static_cast<T*>(input.data_ptr()), output_q.data_ptr(), \\\n static_cast<float*>(output_s.data_ptr()), group_size, \\\n num_groups, groups_per_block, (float)eps, (float)min_8bit, \\\n (float)max_8bit); \\\n } \\\n } \\\n } while (0)\n\n VLLM_DISPATCH_FLOATING_TYPES(\n input.scalar_type(), \"per_token_group_quant_8bit\", ([&] {\n if (dst_type == at::ScalarType::Float8_e4m3fn) {\n LAUNCH_KERNEL(scalar_t, __nv_fp8_e4m3);\n } else if (dst_type == at::ScalarType::Char) {\n LAUNCH_KERNEL(scalar_t, int8_t);\n }\n }));\n\n#undef LAUNCH_KERNEL\n}\n\nvoid per_token_group_quant_fp8(const torch::Tensor& input,\n torch::Tensor& output_q, torch::Tensor& output_s,\n int64_t group_size, double eps, double fp8_min,\n double fp8_max, bool scale_ue8m0) {\n per_token_group_quant_8bit(input, output_q, output_s, group_size, eps,\n fp8_min, fp8_max, scale_ue8m0);\n}\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## Purpose\n\nFused layout transform with per token group quant to get performance\n\nNamely, pack scales into a uint32 earlier and remove an additional kernel call\n\n## Test\n\n`vllm serve deepseek-ai/DeepSeek-V3.1 -tp 8 --enable-expert-parallel --port 9256 --enforce_eager`\n\n### Acc\n\n`lm_eval --model local-completions --model_args \"base_url=http://127.0.0.1:9256/v1/completions,model=deepseek-ai/DeepSeek-V3.1,num_concurrent=1024\" --tasks gsm8k`\n\n```bash\n|Tasks|Version| Filter |n-shot| Metric | |Value | |Stderr|\n|-----|------:|----------------|-----:|-----------|---|-----:|---|-----:|\n|gsm8k| 3|flexible-extract| 5|exact_match|↑ |0.9568|± |0.0056|\n| | |strict-match | 5|exact_match|↑ |0.9568|± |0.0056|\n```\n\n### Perf\n\n`vllm bench serve --model deepseek-ai/DeepSeek-V3.1 --dataset-name random --host 127.0.0.1 --port 9256 --random-input-len 2 --random-output-len 256 --request-rate inf --num-prompts 1024`\n\n```bash\nNow\n============ Serving Benchmark Result ============\nSuccessful requests: 1024 \nFailed requests: 0 \nBenchmark duration (s): 27.94 \nTotal input tokens: 3072 \nTotal generated tokens: 262144 \nRequest throughput (req/s): 36.65 \nOutput token throughput (tok/s): 9382.68 \nPeak output token throughput (tok/s): 10240.00 \nPeak concurrent requests: 1024.00 \nTotal Token throughput (tok/s): 9492.63 \n---------------Time to First Token----------------\nMean TTFT (ms): 1013.22 \nMedian TTFT (ms): 982.19 \nP99 TTFT (ms): 1157.11 \n-----Time per Output Token (excl. 1st token)------\nMean TPOT (ms): 105.02 \nMedian TPOT (ms): 105.08 \nP99 TPOT (ms): 105.26 \n---------------Inter-token Latency----------------\nMean ITL (ms): 105.02 \nMedian ITL (ms): 104.57 \nP99 ITL (ms): 131.10 \n==================================================\n\nMain\n============ Serving Benchmark Result ============\nSuccessful requests: 1024 \nFailed requests: 0 \nBenchmark duration (s): 29.15 \nTotal input tokens: 3072 \nTotal generated tokens: 262144 \nRequest throughput (req/s): 35.13 \nOutput token throughput (tok/s): 8994.31 \nPeak output token throughput (tok/s): 10132.00 \nPeak concurrent requests: 1024.00 \nTotal Token throughput (tok/s): 9099.71 \n---------------Time to First Token----------------\nMean TTFT (ms): 1121.89 \nMedian TTFT (ms): 1144.56 \nP99 TTFT (ms): 1241.25 \n-----Time per Output Token (excl. 1st token)------\nMean TPOT (ms): 109.30 \nMedian TPOT (ms): 109.29 \nP99 TPOT (ms): 109.40 \n---------------Inter-token Latency----------------\nMean ITL (ms): 109.30 \nMedian ITL (ms): 108.89 \nP99 ITL (ms): 125.29 \n==================================================\n```\n\n\n"},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":391,"cells":{"repo":{"kind":"string","value":"vllm"},"commit":{"kind":"string","value":"541a2ef892720489f770569417bc1bc4436dbb21"},"date":{"kind":"string","value":"2025-12-07T07:31:14-05:00"},"pr_number":{"kind":"number","value":29546,"string":"29,546"},"pr_url":{"kind":"string","value":"https://github.com/vllm-project/vllm/pull/29546"},"title":{"kind":"string","value":"[Perf] Deepgemm fused layout kernel for activations, 4.3% throughput improvement, 10.7% TTFT improvement. (#29546)"},"message":{"kind":"string","value":"[Perf] Deepgemm fused layout kernel for activations, 4.3% throughput improvement, 10.7% TTFT improvement. (#29546)\n\nSigned-off-by: yewentao256 <zhyanwentao@126.com>"},"path":{"kind":"string","value":"csrc/torch_bindings.cpp"},"language":{"kind":"string","value":"cpp"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"#include \"cache.h\"\n#include \"cuda_utils.h\"\n#include \"ops.h\"\n#include \"core/registration.h\"\n\n#include <torch/library.h>\n#include <torch/version.h>\n\n// Note on op signatures:\n// The X_meta signatures are for the meta functions corresponding to op X.\n// They must be kept in sync with the signature for X. Generally, only\n// functions that return Tensors require a meta function.\n//\n// See the following links for detailed docs on op registration and function\n// schemas.\n// https://docs.google.com/document/d/1_W62p8WJOQQUzPsJYa7s701JXt0qf2OfLub2sbkHOaU/edit#heading=h.ptttacy8y1u9\n// https://github.com/pytorch/pytorch/blob/main/aten/src/ATen/native/README.md#annotations\n\nTORCH_LIBRARY_EXPAND(TORCH_EXTENSION_NAME, ops) {\n // vLLM custom ops\n //\n\n ops.def(\n \"persistent_masked_m_silu_mul_quant(Tensor input, Tensor counts, Tensor! \"\n \"y_q, Tensor! y_s,\"\n \"bool use_ue8m0) -> ()\");\n ops.impl(\"persistent_masked_m_silu_mul_quant\", torch::kCUDA,\n &persistent_masked_m_silu_mul_quant);\n\n ops.def(\"weak_ref_tensor(Tensor input) -> Tensor\");\n ops.impl(\"weak_ref_tensor\", torch::kCUDA, &weak_ref_tensor);\n\n ops.def(\"get_cuda_view_from_cpu_tensor(Tensor cpu_tensor) -> Tensor\");\n ops.impl(\"get_cuda_view_from_cpu_tensor\", torch::kCPU,\n &get_cuda_view_from_cpu_tensor);\n\n // Attention ops\n // Compute the attention between an input query and the cached\n // keys/values using PagedAttention.\n ops.def(\n \"paged_attention_v1(\"\n \" Tensor! out, Tensor query, Tensor key_cache,\"\n \" Tensor value_cache, int num_kv_heads, float scale,\"\n \" Tensor block_tables, Tensor seq_lens, int block_size,\"\n \" int max_seq_len, Tensor? alibi_slopes,\"\n \" str kv_cache_dtype, Tensor k_scale, Tensor v_scale,\"\n \" int tp_rank, int blocksparse_local_blocks,\"\n \" int blocksparse_vert_stride, int blocksparse_block_size,\"\n \" int blocksparse_head_sliding_step) -> ()\");\n ops.impl(\"paged_attention_v1\", torch::kCUDA, &paged_attention_v1);\n\n // PagedAttention V2.\n ops.def(\n \"paged_attention_v2(\"\n \" Tensor! out, Tensor! exp_sums, Tensor! max_logits,\"\n \" Tensor! tmp_out, Tensor query, Tensor key_cache,\"\n \" Tensor value_cache, int num_kv_heads, float scale,\"\n \" Tensor block_tables, Tensor seq_lens, int block_size,\"\n \" int max_seq_len, Tensor? alibi_slopes,\"\n \" str kv_cache_dtype, Tensor k_scale, Tensor v_scale,\"\n \" int tp_rank, int blocksparse_local_blocks,\"\n \" int blocksparse_vert_stride, int blocksparse_block_size,\"\n \" int blocksparse_head_sliding_step) -> ()\");\n ops.impl(\"paged_attention_v2\", torch::kCUDA, &paged_attention_v2);\n\n // Merge attn states\n // Implements section 2.2 of https://www.arxiv.org/pdf/2501.01005\n // can be used to combine partial attention results (in the split-KV case)\n ops.def(\n \"merge_attn_states(\"\n \" Tensor! output,\"\n \" Tensor!? output_lse,\"\n \" Tensor prefix_output,\"\n \" Tensor prefix_lse,\"\n \" Tensor suffix_output,\"\n \" Tensor suffix_lse) -> ()\");\n ops.impl(\"merge_attn_states\", torch::kCUDA, &merge_attn_states);\n#ifndef USE_ROCM\n ops.def(\n \"convert_vertical_slash_indexes(\"\n \" Tensor! block_count, Tensor! block_offset, \"\n \" Tensor! column_count, Tensor! column_index, \"\n \" Tensor q_seqlens, Tensor q_seqlens, \"\n \" Tensor vertical_indexes, Tensor slash_indexes, \"\n \" int context_size, int block_size_M, int block_size_N, \"\n \" bool causal) -> ()\");\n ops.impl(\"convert_vertical_slash_indexes\", torch::kCUDA,\n &convert_vertical_slash_indexes);\n\n ops.def(\n \"convert_vertical_slash_indexes_mergehead(\"\n \" Tensor! block_count, Tensor! block_offset, \"\n \" Tensor! column_count, Tensor! column_index, \"\n \" Tensor q_seqlens, Tensor q_seqlens, \"\n \" Tensor vertical_indexes, Tensor slash_indexes, \"\n \" Tensor vertical_indices_count, Tensor slash_indices_count, \"\n \" int context_size, int block_size_M, int block_size_N, \"\n \" bool causal) -> ()\");\n ops.impl(\"convert_vertical_slash_indexes_mergehead\", torch::kCUDA,\n &convert_vertical_slash_indexes_mergehead);\n#endif\n\n // Activation ops\n // Activation function used in SwiGLU.\n ops.def(\"silu_and_mul(Tensor! result, Tensor input) -> ()\");\n ops.impl(\"silu_and_mul\", torch::kCUDA, &silu_and_mul);\n\n ops.def(\n \"silu_and_mul_quant(Tensor! result, Tensor input, Tensor scale) -> ()\");\n ops.impl(\"silu_and_mul_quant\", torch::kCUDA, &silu_and_mul_quant);\n\n#ifndef USE_ROCM\n ops.def(\n \"silu_and_mul_nvfp4_quant(Tensor! result, Tensor! result_block_scale, \"\n \"Tensor input, Tensor input_global_scale) -> ()\");\n ops.impl(\"silu_and_mul_nvfp4_quant\", torch::kCUDA, &silu_and_mul_nvfp4_quant);\n#endif\n\n ops.def(\"mul_and_silu(Tensor! out, Tensor input) -> ()\");\n ops.impl(\"mul_and_silu\", torch::kCUDA, &mul_and_silu);\n\n // Activation function used in GeGLU with `none` approximation.\n ops.def(\"gelu_and_mul(Tensor! out, Tensor input) -> ()\");\n ops.impl(\"gelu_and_mul\", torch::kCUDA, &gelu_and_mul);\n\n // Activation function used in GeGLU with `tanh` approximation.\n ops.def(\"gelu_tanh_and_mul(Tensor! out, Tensor input) -> ()\");\n ops.impl(\"gelu_tanh_and_mul\", torch::kCUDA, &gelu_tanh_and_mul);\n\n // FATReLU implementation.\n ops.def(\"fatrelu_and_mul(Tensor! out, Tensor input, float threshold) -> ()\");\n ops.impl(\"fatrelu_and_mul\", torch::kCUDA, &fatrelu_and_mul);\n\n ops.def(\n \"swigluoai_and_mul(Tensor! out, Tensor input, float alpha=1.702, float \"\n \"limit=7.0) \"\n \"-> ()\");\n ops.impl(\"swigluoai_and_mul\", torch::kCUDA, &swigluoai_and_mul);\n\n // GELU implementation used in GPT-2.\n ops.def(\"gelu_new(Tensor! out, Tensor input) -> ()\");\n ops.impl(\"gelu_new\", torch::kCUDA, &gelu_new);\n\n // Approximate GELU implementation.\n ops.def(\"gelu_fast(Tensor! out, Tensor input) -> ()\");\n ops.impl(\"gelu_fast\", torch::kCUDA, &gelu_fast);\n\n // Quick GELU implementation.\n ops.def(\"gelu_quick(Tensor! out, Tensor input) -> ()\");\n ops.impl(\"gelu_quick\", torch::kCUDA, &gelu_quick);\n\n // Layernorm\n // Apply Root Mean Square (RMS) Normalization to the input tensor.\n ops.def(\n \"rms_norm(Tensor! result, Tensor input, Tensor weight, float epsilon) -> \"\n \"()\");\n ops.impl(\"rms_norm\", torch::kCUDA, &rms_norm);\n\n // In-place fused Add and RMS Normalization.\n ops.def(\n \"fused_add_rms_norm(Tensor! input, Tensor! residual, Tensor weight, \"\n \"float epsilon) -> ()\");\n ops.impl(\"fused_add_rms_norm\", torch::kCUDA, &fused_add_rms_norm);\n\n // Function for fused QK Norm and RoPE\n ops.def(\n \"fused_qk_norm_rope(Tensor! qkv, int num_heads_q, \"\n \"int num_heads_k, int num_heads_v, int head_dim, float eps, \"\n \"Tensor q_weight, Tensor k_weight, Tensor cos_sin_cache, \"\n \"bool is_neox, Tensor position_ids) -> ()\");\n ops.impl(\"fused_qk_norm_rope\", torch::kCUDA, &fused_qk_norm_rope);\n\n // Apply repetition penalties to logits in-place\n ops.def(\n \"apply_repetition_penalties_(Tensor! logits, Tensor prompt_mask, \"\n \"Tensor output_mask, Tensor repetition_penalties) -> ()\");\n ops.impl(\"apply_repetition_penalties_\", torch::kCUDA,\n &apply_repetition_penalties_);\n\n // Optimized top-k per row operation\n ops.def(\n \"top_k_per_row(Tensor logits, Tensor rowStarts, Tensor rowEnds, \"\n \"Tensor! indices, int numRows, int stride0, \"\n \"int stride1) -> ()\");\n ops.impl(\"top_k_per_row\", torch::kCUDA, &top_k_per_row);\n\n ops.def(\n \"top_k_per_row_decode(Tensor logits, int next_n, \"\n \"Tensor seq_lens, Tensor! indices, int numRows, \"\n \"int stride0, int stride1) -> ()\");\n ops.impl(\"top_k_per_row_decode\", torch::kCUDA, &top_k_per_row_decode);\n\n // Layernorm-quant\n // Apply Root Mean Square (RMS) Normalization to the input tensor.\n ops.def(\n \"rms_norm_static_fp8_quant(Tensor! result, Tensor input, Tensor weight, \"\n \"Tensor scale, float epsilon) -> \"\n \"()\");\n ops.impl(\"rms_norm_static_fp8_quant\", torch::kCUDA,\n &rms_norm_static_fp8_quant);\n\n // In-place fused Add and RMS Normalization.\n ops.def(\n \"fused_add_rms_norm_static_fp8_quant(Tensor! result, Tensor input, \"\n \"Tensor! residual, Tensor weight, \"\n \"Tensor scale, float epsilon) -> ()\");\n ops.impl(\"fused_add_rms_norm_static_fp8_quant\", torch::kCUDA,\n &fused_add_rms_norm_static_fp8_quant);\n\n // Fused Layernorm + Quant kernels\n ops.def(\n \"rms_norm_dynamic_per_token_quant(Tensor! result, Tensor input, \"\n \"Tensor weight, Tensor! scale, float epsilon, \"\n \"Tensor? scale_ub, Tensor!? residual) -> ()\");\n ops.impl(\"rms_norm_dynamic_per_token_quant\", torch::kCUDA,\n &rms_norm_dynamic_per_token_quant);\n\n // Rotary embedding\n // Apply GPT-NeoX or GPT-J style rotary embedding to query and key.\n ops.def(\n \"rotary_embedding(Tensor positions, Tensor! query,\"\n \" Tensor!? key, int head_size,\"\n \" Tensor cos_sin_cache, bool is_neox) -> ()\");\n ops.impl(\"rotary_embedding\", torch::kCUDA, &rotary_embedding);\n\n // Quantization ops\n#ifndef USE_ROCM\n // Quantized GEMM for AWQ.\n ops.def(\n \"awq_gemm(Tensor _in_feats, Tensor _kernel, Tensor _scaling_factors, \"\n \"Tensor _zeros, SymInt split_k_iters) -> Tensor\");\n ops.impl(\"awq_gemm\", torch::kCUDA, &awq_gemm);\n\n // Dequantization for AWQ.\n ops.def(\n \"awq_dequantize(Tensor _kernel, Tensor _scaling_factors, \"\n \"Tensor _zeros, SymInt split_k_iters, int thx, int thy) -> Tensor\");\n ops.impl(\"awq_dequantize\", torch::kCUDA, &awq_dequantize);\n\n // Note about marlin kernel 'workspace' arguments:\n // Technically these should be mutable since they are modified by the kernel.\n // But since they are set back to zero once the kernel is finished we can\n // hand wave and say that they have no net effect.\n //\n // The reason to mark 'workspace' as immutable is so that they don't interfere\n // with using ScalarType arguments in the ops. If they are marked as mutable,\n // pytorch throws an assert in\n // 'torch._higher_order_ops._register_effectful_op' that prevents these\n // kernels from being torch.compile'd.\n // See the following document for more info on custom types and ops that use\n // custom types:\n // https://docs.google.com/document/d/18fBMPuOJ0fY5ZQ6YyrHUppw9FA332CpNtgB6SOIgyuA\n\n // Marlin_24 (Sparse) Optimized Quantized GEMM for GPTQ.\n ops.def(\n \"gptq_marlin_24_gemm(Tensor a, Tensor b_q_weight, Tensor b_meta, \"\n \"Tensor b_scales, Tensor workspace, \"\n \"int b_q_type, \"\n \"SymInt size_m, SymInt size_n, SymInt size_k) -> Tensor\");\n // conditionally compiled so impl in source file\n\n // Machete (Dense) Optimized Mixed Precision GEMM for Hopper.\n ops.def(\n \"machete_supported_schedules(\"\n \" ScalarType a_type,\"\n \" int b_type,\"\n \" ScalarType? maybe_group_scales_type,\"\n \" ScalarType? maybe_group_zeros_type,\"\n \" ScalarType? maybe_channel_scales_type,\"\n \" ScalarType? maybe_token_scales_type,\"\n \" ScalarType? maybe_out_type\"\n \") -> str[]\");\n ops.def(\n \"machete_mm(\"\n \" Tensor A,\"\n \" Tensor B,\"\n \" int b_type,\"\n \" ScalarType? out_type,\"\n \" Tensor? group_scales,\"\n \" Tensor? group_zeros,\"\n \" int? group_size,\"\n \" Tensor? channel_scales,\"\n \" Tensor? token_scales,\"\n \" str? schedule\"\n \") -> Tensor\");\n ops.def(\n \"machete_prepack_B(\"\n \" Tensor B,\"\n \" ScalarType a_type,\"\n \" int b_type,\"\n \" ScalarType? group_scales_type\"\n \") -> Tensor\");\n // conditionally compiled so impl registration is in source file\n\n ops.def(\"permute_cols(Tensor A, Tensor perm) -> Tensor\");\n ops.impl(\"permute_cols\", torch::kCUDA, &permute_cols);\n\n // gptq_marlin Optimized Quantized GEMM for GPTQ.\n ops.def(\n \"gptq_marlin_gemm(Tensor a, Tensor? c_or_none, Tensor b_q_weight, \"\n \"Tensor? b_bias_or_none,Tensor b_scales, \"\n \"Tensor? a_scales, Tensor? global_scale, Tensor? b_zeros_or_none, \"\n \"Tensor? \"\n \"g_idx_or_none, Tensor? perm_or_none, Tensor workspace, int b_type_id, \"\n \"SymInt size_m, SymInt size_n, SymInt size_k, bool is_k_full, \"\n \"bool use_atomic_add, bool use_fp32_reduce, bool is_zp_float) -> Tensor\");\n // conditionally compiled so impl registration is in source file\n\n // gptq_marlin repack from GPTQ.\n ops.def(\n \"gptq_marlin_repack(Tensor b_q_weight, Tensor perm, \"\n \"SymInt size_k, SymInt size_n, int num_bits, bool is_a_8bit) -> Tensor\");\n // conditionally compiled so impl registrations are in source file\n\n // awq_marlin repack from AWQ.\n ops.def(\n \"awq_marlin_repack(Tensor b_q_weight, SymInt size_k, \"\n \"SymInt size_n, int num_bits, bool is_a_8bit) -> Tensor\");\n // conditionally compiled so impl registrations are in source file\n\n // preprocess W-int4A-fp8 weight for marlin kernel\n ops.def(\n \"marlin_int4_fp8_preprocess(Tensor qweight, \"\n \"Tensor? qzeros_or_none, bool inplace) -> Tensor\");\n // conditionally compiled so impl registrations are in source file\n\n // CUTLASS w4a8 GEMM\n ops.def(\n \"cutlass_w4a8_mm(\"\n \" Tensor A,\"\n \" Tensor B,\"\n \" Tensor group_scales,\"\n \" int group_size,\"\n \" Tensor channel_scales,\"\n \" Tensor token_scales,\"\n \" ScalarType? out_type,\"\n \" str? maybe_schedule\"\n \") -> Tensor\");\n // pack scales\n ops.def(\"cutlass_pack_scale_fp8(Tensor scales) -> Tensor\");\n // encode and reorder weight matrix\n ops.def(\"cutlass_encode_and_reorder_int4b(Tensor B) -> Tensor\");\n // conditionally compiled so impl registration is in source file\n\n#endif\n\n // Dequantization for GGML.\n ops.def(\n \"ggml_dequantize(Tensor W, int type, SymInt m, SymInt n, ScalarType? \"\n \"dtype) -> Tensor\");\n ops.impl(\"ggml_dequantize\", torch::kCUDA, &ggml_dequantize);\n\n // mmvq kernel for GGML.\n ops.def(\n \"ggml_mul_mat_vec_a8(Tensor W, Tensor X, int type, SymInt row) \"\n \"-> Tensor\");\n ops.impl(\"ggml_mul_mat_vec_a8\", torch::kCUDA, &ggml_mul_mat_vec_a8);\n\n // mmq kernel for GGML.\n ops.def(\n \"ggml_mul_mat_a8(Tensor W, Tensor X, int type, SymInt row) -> Tensor\");\n ops.impl(\"ggml_mul_mat_a8\", torch::kCUDA, &ggml_mul_mat_a8);\n\n // moe kernel for GGML.\n ops.def(\n \"ggml_moe_a8(Tensor X, Tensor W, \"\n \"Tensor sorted_token_ids, Tensor expert_ids, Tensor \"\n \"num_tokens_post_padded, \"\n \"int type, SymInt row, SymInt top_k, SymInt tokens) -> Tensor\");\n ops.impl(\"ggml_moe_a8\", torch::kCUDA, &ggml_moe_a8);\n\n ops.def(\n \"ggml_moe_a8_vec(Tensor X, Tensor W, \"\n \"Tensor topk_ids, int top_k, \"\n \"int type, SymInt row, SymInt tokens) -> Tensor\");\n ops.impl(\"ggml_moe_a8_vec\", torch::kCUDA, &ggml_moe_a8_vec);\n\n ops.def(\"ggml_moe_get_block_size\", &ggml_moe_get_block_size);\n\n#ifndef USE_ROCM\n // CUTLASS nvfp4 block scaled GEMM\n ops.def(\n \"cutlass_scaled_fp4_mm(Tensor! out, Tensor a, Tensor b,\"\n \" Tensor block_scale_a, Tensor block_scale_b,\"\n \" Tensor alpha) -> ()\");\n ops.impl(\"cutlass_scaled_fp4_mm\", torch::kCUDA, &cutlass_scaled_fp4_mm);\n\n // cutlass blockwise scaledgroup GEMM\n ops.def(\n \"cutlass_blockwise_scaled_grouped_mm(Tensor! output, Tensor a, Tensor b, \"\n \"Tensor scales_a, Tensor scales_b, \"\n \"Tensor problem_sizes, Tensor expert_offsets) -> ()\");\n // conditionally compiled so impl registration is in source file\n\n // cutlass nvfp4 block scaled group GEMM\n ops.def(\n \"cutlass_fp4_group_mm(Tensor! out, Tensor a, Tensor b,\"\n \" Tensor a_blockscale, Tensor b_blockscales, Tensor alphas,\"\n \" Tensor problem_sizes, Tensor expert_offsets, Tensor sf_offsets) -> ()\");\n // conditionally compiled so impl registration is in source file\n\n // CUTLASS w8a8 GEMM, supporting symmetric per-tensor or per-row/column\n // quantization, as well as bias\n ops.def(\n \"cutlass_scaled_mm(Tensor! out, Tensor a,\"\n \" Tensor b, Tensor a_scales,\"\n \" Tensor b_scales, Tensor? bias) -> ()\");\n ops.impl(\"cutlass_scaled_mm\", torch::kCUDA, &cutlass_scaled_mm);\n\n // CUTLASS w8a8 GEMM, supporting asymmetric per-tensor or per-row/column\n // quantization.\n ops.def(\n \"cutlass_scaled_mm_azp(Tensor! out, Tensor a,\"\n \" Tensor b, Tensor a_scales,\"\n \" Tensor b_scales, Tensor azp_adj,\"\n \" Tensor? azp, Tensor? bias) -> ()\");\n ops.impl(\"cutlass_scaled_mm_azp\", torch::kCUDA, &cutlass_scaled_mm_azp);\n\n // Check if cutlass scaled_mm is supported for CUDA devices of the given\n // capability\n ops.def(\"cutlass_scaled_mm_supports_fp8(int cuda_device_capability) -> bool\");\n ops.impl(\"cutlass_scaled_mm_supports_fp8\", &cutlass_scaled_mm_supports_fp8);\n\n // Check if cutlass grouped gemm is supported for CUDA devices of the given\n // capability\n ops.def(\"cutlass_group_gemm_supported(int cuda_device_capability) -> bool\");\n ops.impl(\"cutlass_group_gemm_supported\", &cutlass_group_gemm_supported);\n\n // CUTLASS w8a8 grouped GEMM\n ops.def(\n \"cutlass_moe_mm(Tensor! out_tensors, Tensor a_tensors, Tensor b_tensors, \"\n \" Tensor a_scales, Tensor b_scales, Tensor expert_offsets, \"\n \" Tensor problem_sizes, Tensor a_strides, \"\n \" Tensor b_strides, Tensor c_strides, bool per_act_token, \"\n \" bool per_out_ch) -> ()\");\n ops.impl(\"cutlass_moe_mm\", torch::kCUDA, &cutlass_moe_mm);\n\n // A function that computes data required to run fused MoE with w8a8 grouped\n // GEMM. It takes topk_ids as an input, and computes expert_offsets\n // (token start indices of each expert). In addition to this, it computes\n // problem sizes for each expert's multiplication used by the two mms called\n // from fused MoE operation, and arrays with permutations required to shuffle\n // and de-shuffle the input/output of the fused operation.\n ops.def(\n \"get_cutlass_moe_mm_data(Tensor topk_ids, Tensor! expert_offsets, \"\n \" Tensor! problem_sizes1, Tensor! problem_sizes2, \"\n \" Tensor! input_permutation, \"\n \" Tensor! output_permutation, int num_experts, \"\n \" int n, int k, Tensor? blockscale_offsets) -> \"\n \"()\");\n ops.impl(\"get_cutlass_moe_mm_data\", torch::kCUDA, &get_cutlass_moe_mm_data);\n\n // A function that computes problem sizes for each expert's multiplication\n // used by the two mms called from fused MoE operation. It takes topk_ids as\n // an input, and computes problem_sizes1 and problem_sizes2 only.\n ops.def(\n \"get_cutlass_moe_mm_problem_sizes(Tensor topk_ids, \"\n \" Tensor! problem_sizes1, \"\n \" Tensor! problem_sizes2, \"\n \" int num_experts, int n, int k, \"\n \" Tensor? blockscale_offsets) -> ()\");\n ops.impl(\"get_cutlass_moe_mm_problem_sizes\", torch::kCUDA,\n &get_cutlass_moe_mm_problem_sizes);\n\n // A function that computes data required to run fused MoE with w8a8 grouped\n // GEMM and PPLX. It takes expert_num_tokens and non_zero_expert_idxs\n // as an input, and computes expert_offsets (token start indices of each\n // expert). In addition to this, it computes problem sizes for each expert's\n // multiplication used by the two mms called from fused MoE operation.\n ops.def(\n \"get_cutlass_pplx_moe_mm_data(Tensor! expert_offsets, \"\n \" Tensor! problem_sizes1, \"\n \" Tensor! problem_sizes2, \"\n \" Tensor expert_num_tokens, \"\n \" int num_local_experts, int padded_m, \"\n \" int n, int k) -> ()\");\n ops.impl(\"get_cutlass_pplx_moe_mm_data\", torch::kCUDA,\n &get_cutlass_pplx_moe_mm_data);\n\n // Check if cutlass scaled_mm supports block quantization (used by DeepSeekV3)\n ops.def(\n \"cutlass_scaled_mm_supports_block_fp8(int cuda_device_capability) -> \"\n \"bool\");\n ops.impl(\"cutlass_scaled_mm_supports_block_fp8\",\n &cutlass_scaled_mm_supports_block_fp8);\n\n // Check if cutlass sparse scaled_mm is supported for CUDA devices of the\n // given capability\n ops.def(\n \"cutlass_sparse_scaled_mm_supported(int cuda_device_capability) -> bool\");\n ops.impl(\"cutlass_sparse_scaled_mm_supported\",\n &cutlass_sparse_scaled_mm_supported);\n\n // CUTLASS sparse GEMM, supporting symmetric per-tensor or per-row/column\n // quantization, as well as bias\n ops.def(\n \"cutlass_scaled_sparse_mm(Tensor! out, Tensor a,\"\n \" Tensor bt_nzs,\"\n \" Tensor bt_meta, Tensor a_scales,\"\n \" Tensor b_scales, Tensor? bias) -> ()\");\n ops.impl(\"cutlass_scaled_sparse_mm\", torch::kCUDA, &cutlass_scaled_sparse_mm);\n\n // CUTLASS sparse matrix compressor\n ops.def(\"cutlass_sparse_compress(Tensor a) -> Tensor[]\");\n ops.impl(\"cutlass_sparse_compress\", &cutlass_sparse_compress);\n\n // SM100 CUTLASS MLA decode\n ops.def(\n \"sm100_cutlass_mla_decode(Tensor! out, Tensor! lse, Tensor q_nope,\"\n \" Tensor q_pe, Tensor kv_c_and_k_pe_cache,\"\n \" Tensor seq_lens, Tensor page_table,\"\n \" Tensor workspace, float scale,\"\n \" int num_kv_splits) -> ()\");\n // conditionally compiled so impl in source file\n\n // SM100 CUTLASS MLA workspace\n ops.def(\n \"sm100_cutlass_mla_get_workspace_size(int max_seq_len, int num_batches,\"\n \" int sm_count, int num_kv_splits) \"\n \"-> int\");\n // conditionally compiled so impl in source file\n\n // Compute NVFP4 block quantized tensor.\n ops.def(\n \"scaled_fp4_quant(Tensor! output, Tensor input,\"\n \" Tensor! output_scale, Tensor input_scale) -> ()\");\n ops.impl(\"scaled_fp4_quant\", torch::kCUDA, &scaled_fp4_quant);\n\n // Compute NVFP4 experts quantization.\n ops.def(\n \"scaled_fp4_experts_quant(Tensor! output, Tensor! output_scale,\"\n \"Tensor input, Tensor input_global_scale, Tensor input_offset_by_experts,\"\n \"Tensor output_scale_offset_by_experts) -> ()\");\n ops.impl(\"scaled_fp4_experts_quant\", torch::kCUDA, &scaled_fp4_experts_quant);\n\n // Check if cutlass_scaled_mm_fp4 is supported for CUDA devices\n // of the given capability\n ops.def(\"cutlass_scaled_mm_supports_fp4(int cuda_device_capability) -> bool\");\n ops.impl(\"cutlass_scaled_mm_supports_fp4\", &cutlass_scaled_mm_supports_fp4);\n#endif\n\n // Quantized GEMM for GPTQ.\n // Note: even though the C++ inferred schema is correct for this op, it seems\n // to prevent the meta function registry.\n ops.def(\n \"gptq_gemm(Tensor a, Tensor b_q_weight, Tensor b_gptq_qzeros, \"\n \"Tensor b_gptq_scales, Tensor b_g_idx, bool use_exllama, bool \"\n \"use_v2_format, int bit) \"\n \"-> Tensor\");\n ops.impl(\"gptq_gemm\", torch::kCUDA, &gptq_gemm);\n\n // Post processing for GPTQ.\n ops.def(\"gptq_shuffle(Tensor! q_weight, Tensor q_perm, int bit) -> ()\");\n ops.impl(\"gptq_shuffle\", torch::kCUDA, &gptq_shuffle);\n\n // Compute FP8 quantized tensor for given scaling factor.\n ops.def(\n \"static_scaled_fp8_quant(Tensor! result, Tensor input, Tensor scale) -> \"\n \"()\");\n ops.impl(\"static_scaled_fp8_quant\", torch::kCUDA, &static_scaled_fp8_quant);\n\n // Compute dynamic-per-tensor FP8 quantized tensor and scaling factor.\n ops.def(\n \"dynamic_scaled_fp8_quant(Tensor! result, Tensor input, Tensor! scale) \"\n \"-> \"\n \"()\");\n ops.impl(\"dynamic_scaled_fp8_quant\", torch::kCUDA, &dynamic_scaled_fp8_quant);\n\n // Compute dynamic-per-token FP8 quantized tensor and scaling factor.\n ops.def(\n \"dynamic_per_token_scaled_fp8_quant(Tensor! result, Tensor input, \"\n \"Tensor! scale, Tensor? scale_ub) -> \"\n \"()\");\n ops.impl(\"dynamic_per_token_scaled_fp8_quant\", torch::kCUDA,\n &dynamic_per_token_scaled_fp8_quant);\n\n // Compute int8 quantized tensor for given scaling factor.\n ops.def(\n \"static_scaled_int8_quant(Tensor! result, Tensor input, Tensor scale,\"\n \"Tensor? azp) -> ()\");\n ops.impl(\"static_scaled_int8_quant\", torch::kCUDA, &static_scaled_int8_quant);\n\n // Compute int8 quantized tensor and scaling factor\n ops.def(\n \"dynamic_scaled_int8_quant(Tensor! result, Tensor input, Tensor! scale, \"\n \"Tensor!? azp) -> ()\");\n ops.impl(\"dynamic_scaled_int8_quant\", torch::kCUDA,\n &dynamic_scaled_int8_quant);\n\n // Mamba selective scan kernel\n ops.def(\n \"selective_scan_fwd(Tensor! u, Tensor! delta,\"\n \"Tensor! A, Tensor! B, Tensor! C,\"\n \"Tensor? D_, Tensor!? z_, Tensor? delta_bias_,\"\n \"bool delta_softplus,\"\n \"Tensor? query_start_loc,\"\n \"Tensor? cache_indices,\"\n \"Tensor? has_initial_state,\"\n \"Tensor! ssm_states,\"\n \"int pad_slot_id,\"\n \"int block_size,\"\n \"Tensor? block_idx_first_scheduled_token,\"\n \"Tensor? block_idx_last_scheduled_token,\"\n \"Tensor? initial_state_idx) -> ()\");\n ops.impl(\"selective_scan_fwd\", torch::kCUDA, &selective_scan_fwd);\n\n // Hadamard transforms\n ops.def(\"hadacore_transform(Tensor! x, bool inplace) -> Tensor\");\n\n#ifndef USE_ROCM\n // Compute per-token-group FP8 quantized tensor and scaling factor.\n ops.def(\n \"per_token_group_fp8_quant(Tensor input, Tensor! output_q, Tensor! \"\n \"output_s, \"\n \"int group_size, float eps, float fp8_min, float fp8_max, bool \"\n \"scale_ue8m0) -> ()\");\n ops.impl(\"per_token_group_fp8_quant\", torch::kCUDA,\n &per_token_group_quant_fp8);\n\n // Compute per-token-group INT8 quantized tensor and scaling factor.\n ops.def(\n \"per_token_group_quant_int8(Tensor input, Tensor! output_q, Tensor! \"\n \"output_s, int group_size, float eps, float int8_min, float int8_max) -> \"\n \"()\");\n ops.impl(\"per_token_group_quant_int8\", torch::kCUDA,\n &per_token_group_quant_int8);\n\n // reorder weight for AllSpark Ampere W8A16 Fused Gemm kernel\n ops.def(\n \"rearrange_kn_weight_as_n32k16_order(Tensor b_qweight, Tensor b_scales, \"\n \"Tensor? b_zeros, \"\n \"bool has_zp, Tensor! b_qweight_reorder, Tensor! b_scales_reorder, \"\n \"Tensor!? b_zeros_reorder, \"\n \"int K, int N, int N_32align) -> ()\");\n // conditionally compiled so impl in source file\n\n // AllSpark quantization ops\n ops.def(\n \"allspark_w8a16_gemm(Tensor a, Tensor b_qweight, Tensor b_scales, \"\n \"Tensor? b_qzeros, \"\n \"SymInt n, SymInt group_size, SymInt sm_count, SymInt sm_version, SymInt \"\n \"CUBLAS_M_THRESHOLD, bool has_zp, bool n32k16_reorder) -> Tensor\");\n // conditionally compiled so impl in source file\n#endif\n}\n\nTORCH_LIBRARY_EXPAND(CONCAT(TORCH_EXTENSION_NAME, _cache_ops), cache_ops) {\n // Cache ops\n // Swap in (out) the cache blocks from src to dst.\n cache_ops.def(\n \"swap_blocks(Tensor src, Tensor! dst, Tensor block_mapping) -> ()\");\n cache_ops.impl(\"swap_blocks\", torch::kCUDA, &swap_blocks);\n\n // Copy the cache blocks from src to dst.\n cache_ops.def(\n \"copy_blocks(Tensor(a!)[] key_caches, Tensor[](b!) value_caches, \"\n \"Tensor block_mapping) -> ()\");\n cache_ops.impl(\"copy_blocks\", torch::kCUDA, ©_blocks);\n\n cache_ops.def(\n \"copy_blocks_mla(Tensor(a!)[] kv_caches, Tensor block_mapping) -> ()\");\n cache_ops.impl(\"copy_blocks_mla\", torch::kCUDA, ©_blocks_mla);\n\n // Reshape the key and value tensors and cache them.\n cache_ops.def(\n \"reshape_and_cache(Tensor key, Tensor value,\"\n \" Tensor! key_cache, Tensor! value_cache,\"\n \" Tensor slot_mapping,\"\n \" str kv_cache_dtype,\"\n \" Tensor k_scale, Tensor v_scale) -> ()\");\n cache_ops.impl(\"reshape_and_cache\", torch::kCUDA, &reshape_and_cache);\n\n // Reshape the key and value tensors and cache them.\n cache_ops.def(\n \"reshape_and_cache_flash(Tensor key, Tensor value,\"\n \" Tensor! key_cache,\"\n \" Tensor! value_cache,\"\n \" Tensor slot_mapping,\"\n \" str kv_cache_dtype,\"\n \" Tensor k_scale, Tensor v_scale) -> ()\");\n cache_ops.impl(\"reshape_and_cache_flash\", torch::kCUDA,\n &reshape_and_cache_flash);\n\n // Concat kv_c and k_pe and cache them.\n cache_ops.def(\n \"concat_and_cache_mla(Tensor kv_c, Tensor k_pe,\"\n \" Tensor! kv_cache,\"\n \" Tensor slot_mapping,\"\n \" str kv_cache_dtype,\"\n \" Tensor scale) -> ()\");\n cache_ops.impl(\"concat_and_cache_mla\", torch::kCUDA, &concat_and_cache_mla);\n\n // Convert the key and value cache to fp8 data type.\n cache_ops.def(\n \"convert_fp8(Tensor! dst_cache, Tensor src_cache, float scale, \"\n \"str kv_cache_dtype) -> ()\");\n cache_ops.impl(\"convert_fp8\", torch::kCUDA, &convert_fp8);\n\n // Gather cache blocks from src_cache to dst, dequantizing from\n // src_cache's dtype to dst's dtype if necessary.\n cache_ops.def(\n \"gather_and_maybe_dequant_cache(Tensor src_cache, Tensor! dst, \"\n \" Tensor block_table, Tensor cu_seq_lens, \"\n \" Tensor token_to_seq, \"\n \" int num_tokens, \"\n \" str kv_cache_dtype, \"\n \" Tensor scale, Tensor? seq_starts) -> ()\");\n cache_ops.impl(\"gather_and_maybe_dequant_cache\", torch::kCUDA,\n &gather_and_maybe_dequant_cache);\n\n cache_ops.def(\n \"cp_gather_cache(Tensor src_cache, Tensor! dst, Tensor block_table, \"\n \"Tensor cu_seq_lens, int batch_size, Tensor? seq_starts) -> ()\");\n cache_ops.impl(\"cp_gather_cache\", torch::kCUDA, &cp_gather_cache);\n\n cache_ops.def(\n \"indexer_k_quant_and_cache(Tensor k, Tensor! kv_cache, Tensor \"\n \"slot_mapping, \"\n \"int quant_block_size, str kv_cache_dtype) -> ()\");\n cache_ops.impl(\"indexer_k_quant_and_cache\", torch::kCUDA,\n &indexer_k_quant_and_cache);\n\n cache_ops.def(\n \"cp_gather_indexer_k_quant_cache(Tensor kv_cache, Tensor! dst_k, Tensor! \"\n \"dst_scale, Tensor block_table, Tensor cu_seq_lens) -> ()\");\n cache_ops.impl(\"cp_gather_indexer_k_quant_cache\", torch::kCUDA,\n &cp_gather_indexer_k_quant_cache);\n}\n\nTORCH_LIBRARY_EXPAND(CONCAT(TORCH_EXTENSION_NAME, _cuda_utils), cuda_utils) {\n // Cuda utils\n\n // Gets the specified device attribute.\n cuda_utils.def(\"get_device_attribute(int attribute, int device_id) -> int\");\n cuda_utils.impl(\"get_device_attribute\", &get_device_attribute);\n\n // Gets the maximum shared memory per block device attribute.\n cuda_utils.def(\n \"get_max_shared_memory_per_block_device_attribute(int device_id) -> int\");\n cuda_utils.impl(\"get_max_shared_memory_per_block_device_attribute\",\n &get_max_shared_memory_per_block_device_attribute);\n}\n\nTORCH_LIBRARY_EXPAND(CONCAT(TORCH_EXTENSION_NAME, _custom_ar), custom_ar) {\n // Custom all-reduce kernels\n custom_ar.def(\n \"init_custom_ar(int[] ipc_tensors, Tensor rank_data, \"\n \"int rank, bool fully_connected) -> int\");\n custom_ar.impl(\"init_custom_ar\", torch::kCUDA, &init_custom_ar);\n custom_ar.def(\n \"all_reduce(int fa, Tensor inp, Tensor! out, int reg_buffer, \"\n \"int reg_buffer_sz_bytes) -> ()\");\n custom_ar.impl(\"all_reduce\", torch::kCUDA, &all_reduce);\n\n custom_ar.def(\"dispose\", &dispose);\n custom_ar.def(\"meta_size\", &meta_size);\n\n custom_ar.def(\"register_buffer\", ®ister_buffer);\n custom_ar.def(\"get_graph_buffer_ipc_meta\", &get_graph_buffer_ipc_meta);\n custom_ar.def(\"register_graph_buffers\", ®ister_graph_buffers);\n\n custom_ar.def(\"allocate_shared_buffer_and_handle\",\n &allocate_shared_buffer_and_handle);\n custom_ar.def(\"open_mem_handle(Tensor mem_handle) -> int\", &open_mem_handle);\n custom_ar.impl(\"open_mem_handle\", torch::kCPU, &open_mem_handle);\n\n custom_ar.def(\"free_shared_buffer\", &free_shared_buffer);\n#ifdef USE_ROCM\n // Quick Reduce all-reduce kernels\n custom_ar.def(\n \"qr_all_reduce(int fa, Tensor inp, Tensor out, int quant_level, bool \"\n \"cast_bf2half) -> ()\");\n custom_ar.impl(\"qr_all_reduce\", torch::kCUDA, &qr_all_reduce);\n\n custom_ar.def(\"init_custom_qr\", &init_custom_qr);\n custom_ar.def(\"qr_destroy\", &qr_destroy);\n\n custom_ar.def(\"qr_get_handle\", &qr_get_handle);\n\n custom_ar.def(\"qr_open_handles(int _fa, Tensor[](b!) handles) -> ()\");\n custom_ar.impl(\"qr_open_handles\", torch::kCPU, &qr_open_handles);\n\n // Max input size in bytes\n custom_ar.def(\"qr_max_size\", &qr_max_size);\n#endif\n}\n\nREGISTER_EXTENSION(TORCH_EXTENSION_NAME)\n"},"after_code":{"kind":"string","value":"#include \"cache.h\"\n#include \"cuda_utils.h\"\n#include \"ops.h\"\n#include \"core/registration.h\"\n\n#include <torch/library.h>\n#include <torch/version.h>\n\n// Note on op signatures:\n// The X_meta signatures are for the meta functions corresponding to op X.\n// They must be kept in sync with the signature for X. Generally, only\n// functions that return Tensors require a meta function.\n//\n// See the following links for detailed docs on op registration and function\n// schemas.\n// https://docs.google.com/document/d/1_W62p8WJOQQUzPsJYa7s701JXt0qf2OfLub2sbkHOaU/edit#heading=h.ptttacy8y1u9\n// https://github.com/pytorch/pytorch/blob/main/aten/src/ATen/native/README.md#annotations\n\nTORCH_LIBRARY_EXPAND(TORCH_EXTENSION_NAME, ops) {\n // vLLM custom ops\n //\n\n ops.def(\n \"persistent_masked_m_silu_mul_quant(Tensor input, Tensor counts, Tensor! \"\n \"y_q, Tensor! y_s,\"\n \"bool use_ue8m0) -> ()\");\n ops.impl(\"persistent_masked_m_silu_mul_quant\", torch::kCUDA,\n &persistent_masked_m_silu_mul_quant);\n\n ops.def(\"weak_ref_tensor(Tensor input) -> Tensor\");\n ops.impl(\"weak_ref_tensor\", torch::kCUDA, &weak_ref_tensor);\n\n ops.def(\"get_cuda_view_from_cpu_tensor(Tensor cpu_tensor) -> Tensor\");\n ops.impl(\"get_cuda_view_from_cpu_tensor\", torch::kCPU,\n &get_cuda_view_from_cpu_tensor);\n\n // Attention ops\n // Compute the attention between an input query and the cached\n // keys/values using PagedAttention.\n ops.def(\n \"paged_attention_v1(\"\n \" Tensor! out, Tensor query, Tensor key_cache,\"\n \" Tensor value_cache, int num_kv_heads, float scale,\"\n \" Tensor block_tables, Tensor seq_lens, int block_size,\"\n \" int max_seq_len, Tensor? alibi_slopes,\"\n \" str kv_cache_dtype, Tensor k_scale, Tensor v_scale,\"\n \" int tp_rank, int blocksparse_local_blocks,\"\n \" int blocksparse_vert_stride, int blocksparse_block_size,\"\n \" int blocksparse_head_sliding_step) -> ()\");\n ops.impl(\"paged_attention_v1\", torch::kCUDA, &paged_attention_v1);\n\n // PagedAttention V2.\n ops.def(\n \"paged_attention_v2(\"\n \" Tensor! out, Tensor! exp_sums, Tensor! max_logits,\"\n \" Tensor! tmp_out, Tensor query, Tensor key_cache,\"\n \" Tensor value_cache, int num_kv_heads, float scale,\"\n \" Tensor block_tables, Tensor seq_lens, int block_size,\"\n \" int max_seq_len, Tensor? alibi_slopes,\"\n \" str kv_cache_dtype, Tensor k_scale, Tensor v_scale,\"\n \" int tp_rank, int blocksparse_local_blocks,\"\n \" int blocksparse_vert_stride, int blocksparse_block_size,\"\n \" int blocksparse_head_sliding_step) -> ()\");\n ops.impl(\"paged_attention_v2\", torch::kCUDA, &paged_attention_v2);\n\n // Merge attn states\n // Implements section 2.2 of https://www.arxiv.org/pdf/2501.01005\n // can be used to combine partial attention results (in the split-KV case)\n ops.def(\n \"merge_attn_states(\"\n \" Tensor! output,\"\n \" Tensor!? output_lse,\"\n \" Tensor prefix_output,\"\n \" Tensor prefix_lse,\"\n \" Tensor suffix_output,\"\n \" Tensor suffix_lse) -> ()\");\n ops.impl(\"merge_attn_states\", torch::kCUDA, &merge_attn_states);\n#ifndef USE_ROCM\n ops.def(\n \"convert_vertical_slash_indexes(\"\n \" Tensor! block_count, Tensor! block_offset, \"\n \" Tensor! column_count, Tensor! column_index, \"\n \" Tensor q_seqlens, Tensor q_seqlens, \"\n \" Tensor vertical_indexes, Tensor slash_indexes, \"\n \" int context_size, int block_size_M, int block_size_N, \"\n \" bool causal) -> ()\");\n ops.impl(\"convert_vertical_slash_indexes\", torch::kCUDA,\n &convert_vertical_slash_indexes);\n\n ops.def(\n \"convert_vertical_slash_indexes_mergehead(\"\n \" Tensor! block_count, Tensor! block_offset, \"\n \" Tensor! column_count, Tensor! column_index, \"\n \" Tensor q_seqlens, Tensor q_seqlens, \"\n \" Tensor vertical_indexes, Tensor slash_indexes, \"\n \" Tensor vertical_indices_count, Tensor slash_indices_count, \"\n \" int context_size, int block_size_M, int block_size_N, \"\n \" bool causal) -> ()\");\n ops.impl(\"convert_vertical_slash_indexes_mergehead\", torch::kCUDA,\n &convert_vertical_slash_indexes_mergehead);\n#endif\n\n // Activation ops\n // Activation function used in SwiGLU.\n ops.def(\"silu_and_mul(Tensor! result, Tensor input) -> ()\");\n ops.impl(\"silu_and_mul\", torch::kCUDA, &silu_and_mul);\n\n ops.def(\n \"silu_and_mul_quant(Tensor! result, Tensor input, Tensor scale) -> ()\");\n ops.impl(\"silu_and_mul_quant\", torch::kCUDA, &silu_and_mul_quant);\n\n#ifndef USE_ROCM\n ops.def(\n \"silu_and_mul_nvfp4_quant(Tensor! result, Tensor! result_block_scale, \"\n \"Tensor input, Tensor input_global_scale) -> ()\");\n ops.impl(\"silu_and_mul_nvfp4_quant\", torch::kCUDA, &silu_and_mul_nvfp4_quant);\n#endif\n\n ops.def(\"mul_and_silu(Tensor! out, Tensor input) -> ()\");\n ops.impl(\"mul_and_silu\", torch::kCUDA, &mul_and_silu);\n\n // Activation function used in GeGLU with `none` approximation.\n ops.def(\"gelu_and_mul(Tensor! out, Tensor input) -> ()\");\n ops.impl(\"gelu_and_mul\", torch::kCUDA, &gelu_and_mul);\n\n // Activation function used in GeGLU with `tanh` approximation.\n ops.def(\"gelu_tanh_and_mul(Tensor! out, Tensor input) -> ()\");\n ops.impl(\"gelu_tanh_and_mul\", torch::kCUDA, &gelu_tanh_and_mul);\n\n // FATReLU implementation.\n ops.def(\"fatrelu_and_mul(Tensor! out, Tensor input, float threshold) -> ()\");\n ops.impl(\"fatrelu_and_mul\", torch::kCUDA, &fatrelu_and_mul);\n\n ops.def(\n \"swigluoai_and_mul(Tensor! out, Tensor input, float alpha=1.702, float \"\n \"limit=7.0) \"\n \"-> ()\");\n ops.impl(\"swigluoai_and_mul\", torch::kCUDA, &swigluoai_and_mul);\n\n // GELU implementation used in GPT-2.\n ops.def(\"gelu_new(Tensor! out, Tensor input) -> ()\");\n ops.impl(\"gelu_new\", torch::kCUDA, &gelu_new);\n\n // Approximate GELU implementation.\n ops.def(\"gelu_fast(Tensor! out, Tensor input) -> ()\");\n ops.impl(\"gelu_fast\", torch::kCUDA, &gelu_fast);\n\n // Quick GELU implementation.\n ops.def(\"gelu_quick(Tensor! out, Tensor input) -> ()\");\n ops.impl(\"gelu_quick\", torch::kCUDA, &gelu_quick);\n\n // Layernorm\n // Apply Root Mean Square (RMS) Normalization to the input tensor.\n ops.def(\n \"rms_norm(Tensor! result, Tensor input, Tensor weight, float epsilon) -> \"\n \"()\");\n ops.impl(\"rms_norm\", torch::kCUDA, &rms_norm);\n\n // In-place fused Add and RMS Normalization.\n ops.def(\n \"fused_add_rms_norm(Tensor! input, Tensor! residual, Tensor weight, \"\n \"float epsilon) -> ()\");\n ops.impl(\"fused_add_rms_norm\", torch::kCUDA, &fused_add_rms_norm);\n\n // Function for fused QK Norm and RoPE\n ops.def(\n \"fused_qk_norm_rope(Tensor! qkv, int num_heads_q, \"\n \"int num_heads_k, int num_heads_v, int head_dim, float eps, \"\n \"Tensor q_weight, Tensor k_weight, Tensor cos_sin_cache, \"\n \"bool is_neox, Tensor position_ids) -> ()\");\n ops.impl(\"fused_qk_norm_rope\", torch::kCUDA, &fused_qk_norm_rope);\n\n // Apply repetition penalties to logits in-place\n ops.def(\n \"apply_repetition_penalties_(Tensor! logits, Tensor prompt_mask, \"\n \"Tensor output_mask, Tensor repetition_penalties) -> ()\");\n ops.impl(\"apply_repetition_penalties_\", torch::kCUDA,\n &apply_repetition_penalties_);\n\n // Optimized top-k per row operation\n ops.def(\n \"top_k_per_row(Tensor logits, Tensor rowStarts, Tensor rowEnds, \"\n \"Tensor! indices, int numRows, int stride0, \"\n \"int stride1) -> ()\");\n ops.impl(\"top_k_per_row\", torch::kCUDA, &top_k_per_row);\n\n ops.def(\n \"top_k_per_row_decode(Tensor logits, int next_n, \"\n \"Tensor seq_lens, Tensor! indices, int numRows, \"\n \"int stride0, int stride1) -> ()\");\n ops.impl(\"top_k_per_row_decode\", torch::kCUDA, &top_k_per_row_decode);\n\n // Layernorm-quant\n // Apply Root Mean Square (RMS) Normalization to the input tensor.\n ops.def(\n \"rms_norm_static_fp8_quant(Tensor! result, Tensor input, Tensor weight, \"\n \"Tensor scale, float epsilon) -> \"\n \"()\");\n ops.impl(\"rms_norm_static_fp8_quant\", torch::kCUDA,\n &rms_norm_static_fp8_quant);\n\n // In-place fused Add and RMS Normalization.\n ops.def(\n \"fused_add_rms_norm_static_fp8_quant(Tensor! result, Tensor input, \"\n \"Tensor! residual, Tensor weight, \"\n \"Tensor scale, float epsilon) -> ()\");\n ops.impl(\"fused_add_rms_norm_static_fp8_quant\", torch::kCUDA,\n &fused_add_rms_norm_static_fp8_quant);\n\n // Fused Layernorm + Quant kernels\n ops.def(\n \"rms_norm_dynamic_per_token_quant(Tensor! result, Tensor input, \"\n \"Tensor weight, Tensor! scale, float epsilon, \"\n \"Tensor? scale_ub, Tensor!? residual) -> ()\");\n ops.impl(\"rms_norm_dynamic_per_token_quant\", torch::kCUDA,\n &rms_norm_dynamic_per_token_quant);\n\n // Rotary embedding\n // Apply GPT-NeoX or GPT-J style rotary embedding to query and key.\n ops.def(\n \"rotary_embedding(Tensor positions, Tensor! query,\"\n \" Tensor!? key, int head_size,\"\n \" Tensor cos_sin_cache, bool is_neox) -> ()\");\n ops.impl(\"rotary_embedding\", torch::kCUDA, &rotary_embedding);\n\n // Quantization ops\n#ifndef USE_ROCM\n // Quantized GEMM for AWQ.\n ops.def(\n \"awq_gemm(Tensor _in_feats, Tensor _kernel, Tensor _scaling_factors, \"\n \"Tensor _zeros, SymInt split_k_iters) -> Tensor\");\n ops.impl(\"awq_gemm\", torch::kCUDA, &awq_gemm);\n\n // Dequantization for AWQ.\n ops.def(\n \"awq_dequantize(Tensor _kernel, Tensor _scaling_factors, \"\n \"Tensor _zeros, SymInt split_k_iters, int thx, int thy) -> Tensor\");\n ops.impl(\"awq_dequantize\", torch::kCUDA, &awq_dequantize);\n\n // Note about marlin kernel 'workspace' arguments:\n // Technically these should be mutable since they are modified by the kernel.\n // But since they are set back to zero once the kernel is finished we can\n // hand wave and say that they have no net effect.\n //\n // The reason to mark 'workspace' as immutable is so that they don't interfere\n // with using ScalarType arguments in the ops. If they are marked as mutable,\n // pytorch throws an assert in\n // 'torch._higher_order_ops._register_effectful_op' that prevents these\n // kernels from being torch.compile'd.\n // See the following document for more info on custom types and ops that use\n // custom types:\n // https://docs.google.com/document/d/18fBMPuOJ0fY5ZQ6YyrHUppw9FA332CpNtgB6SOIgyuA\n\n // Marlin_24 (Sparse) Optimized Quantized GEMM for GPTQ.\n ops.def(\n \"gptq_marlin_24_gemm(Tensor a, Tensor b_q_weight, Tensor b_meta, \"\n \"Tensor b_scales, Tensor workspace, \"\n \"int b_q_type, \"\n \"SymInt size_m, SymInt size_n, SymInt size_k) -> Tensor\");\n // conditionally compiled so impl in source file\n\n // Machete (Dense) Optimized Mixed Precision GEMM for Hopper.\n ops.def(\n \"machete_supported_schedules(\"\n \" ScalarType a_type,\"\n \" int b_type,\"\n \" ScalarType? maybe_group_scales_type,\"\n \" ScalarType? maybe_group_zeros_type,\"\n \" ScalarType? maybe_channel_scales_type,\"\n \" ScalarType? maybe_token_scales_type,\"\n \" ScalarType? maybe_out_type\"\n \") -> str[]\");\n ops.def(\n \"machete_mm(\"\n \" Tensor A,\"\n \" Tensor B,\"\n \" int b_type,\"\n \" ScalarType? out_type,\"\n \" Tensor? group_scales,\"\n \" Tensor? group_zeros,\"\n \" int? group_size,\"\n \" Tensor? channel_scales,\"\n \" Tensor? token_scales,\"\n \" str? schedule\"\n \") -> Tensor\");\n ops.def(\n \"machete_prepack_B(\"\n \" Tensor B,\"\n \" ScalarType a_type,\"\n \" int b_type,\"\n \" ScalarType? group_scales_type\"\n \") -> Tensor\");\n // conditionally compiled so impl registration is in source file\n\n ops.def(\"permute_cols(Tensor A, Tensor perm) -> Tensor\");\n ops.impl(\"permute_cols\", torch::kCUDA, &permute_cols);\n\n // gptq_marlin Optimized Quantized GEMM for GPTQ.\n ops.def(\n \"gptq_marlin_gemm(Tensor a, Tensor? c_or_none, Tensor b_q_weight, \"\n \"Tensor? b_bias_or_none,Tensor b_scales, \"\n \"Tensor? a_scales, Tensor? global_scale, Tensor? b_zeros_or_none, \"\n \"Tensor? \"\n \"g_idx_or_none, Tensor? perm_or_none, Tensor workspace, int b_type_id, \"\n \"SymInt size_m, SymInt size_n, SymInt size_k, bool is_k_full, \"\n \"bool use_atomic_add, bool use_fp32_reduce, bool is_zp_float) -> Tensor\");\n // conditionally compiled so impl registration is in source file\n\n // gptq_marlin repack from GPTQ.\n ops.def(\n \"gptq_marlin_repack(Tensor b_q_weight, Tensor perm, \"\n \"SymInt size_k, SymInt size_n, int num_bits, bool is_a_8bit) -> Tensor\");\n // conditionally compiled so impl registrations are in source file\n\n // awq_marlin repack from AWQ.\n ops.def(\n \"awq_marlin_repack(Tensor b_q_weight, SymInt size_k, \"\n \"SymInt size_n, int num_bits, bool is_a_8bit) -> Tensor\");\n // conditionally compiled so impl registrations are in source file\n\n // preprocess W-int4A-fp8 weight for marlin kernel\n ops.def(\n \"marlin_int4_fp8_preprocess(Tensor qweight, \"\n \"Tensor? qzeros_or_none, bool inplace) -> Tensor\");\n // conditionally compiled so impl registrations are in source file\n\n // CUTLASS w4a8 GEMM\n ops.def(\n \"cutlass_w4a8_mm(\"\n \" Tensor A,\"\n \" Tensor B,\"\n \" Tensor group_scales,\"\n \" int group_size,\"\n \" Tensor channel_scales,\"\n \" Tensor token_scales,\"\n \" ScalarType? out_type,\"\n \" str? maybe_schedule\"\n \") -> Tensor\");\n // pack scales\n ops.def(\"cutlass_pack_scale_fp8(Tensor scales) -> Tensor\");\n // encode and reorder weight matrix\n ops.def(\"cutlass_encode_and_reorder_int4b(Tensor B) -> Tensor\");\n // conditionally compiled so impl registration is in source file\n\n#endif\n\n // Dequantization for GGML.\n ops.def(\n \"ggml_dequantize(Tensor W, int type, SymInt m, SymInt n, ScalarType? \"\n \"dtype) -> Tensor\");\n ops.impl(\"ggml_dequantize\", torch::kCUDA, &ggml_dequantize);\n\n // mmvq kernel for GGML.\n ops.def(\n \"ggml_mul_mat_vec_a8(Tensor W, Tensor X, int type, SymInt row) \"\n \"-> Tensor\");\n ops.impl(\"ggml_mul_mat_vec_a8\", torch::kCUDA, &ggml_mul_mat_vec_a8);\n\n // mmq kernel for GGML.\n ops.def(\n \"ggml_mul_mat_a8(Tensor W, Tensor X, int type, SymInt row) -> Tensor\");\n ops.impl(\"ggml_mul_mat_a8\", torch::kCUDA, &ggml_mul_mat_a8);\n\n // moe kernel for GGML.\n ops.def(\n \"ggml_moe_a8(Tensor X, Tensor W, \"\n \"Tensor sorted_token_ids, Tensor expert_ids, Tensor \"\n \"num_tokens_post_padded, \"\n \"int type, SymInt row, SymInt top_k, SymInt tokens) -> Tensor\");\n ops.impl(\"ggml_moe_a8\", torch::kCUDA, &ggml_moe_a8);\n\n ops.def(\n \"ggml_moe_a8_vec(Tensor X, Tensor W, \"\n \"Tensor topk_ids, int top_k, \"\n \"int type, SymInt row, SymInt tokens) -> Tensor\");\n ops.impl(\"ggml_moe_a8_vec\", torch::kCUDA, &ggml_moe_a8_vec);\n\n ops.def(\"ggml_moe_get_block_size\", &ggml_moe_get_block_size);\n\n#ifndef USE_ROCM\n // CUTLASS nvfp4 block scaled GEMM\n ops.def(\n \"cutlass_scaled_fp4_mm(Tensor! out, Tensor a, Tensor b,\"\n \" Tensor block_scale_a, Tensor block_scale_b,\"\n \" Tensor alpha) -> ()\");\n ops.impl(\"cutlass_scaled_fp4_mm\", torch::kCUDA, &cutlass_scaled_fp4_mm);\n\n // cutlass blockwise scaledgroup GEMM\n ops.def(\n \"cutlass_blockwise_scaled_grouped_mm(Tensor! output, Tensor a, Tensor b, \"\n \"Tensor scales_a, Tensor scales_b, \"\n \"Tensor problem_sizes, Tensor expert_offsets) -> ()\");\n // conditionally compiled so impl registration is in source file\n\n // cutlass nvfp4 block scaled group GEMM\n ops.def(\n \"cutlass_fp4_group_mm(Tensor! out, Tensor a, Tensor b,\"\n \" Tensor a_blockscale, Tensor b_blockscales, Tensor alphas,\"\n \" Tensor problem_sizes, Tensor expert_offsets, Tensor sf_offsets) -> ()\");\n // conditionally compiled so impl registration is in source file\n\n // CUTLASS w8a8 GEMM, supporting symmetric per-tensor or per-row/column\n // quantization, as well as bias\n ops.def(\n \"cutlass_scaled_mm(Tensor! out, Tensor a,\"\n \" Tensor b, Tensor a_scales,\"\n \" Tensor b_scales, Tensor? bias) -> ()\");\n ops.impl(\"cutlass_scaled_mm\", torch::kCUDA, &cutlass_scaled_mm);\n\n // CUTLASS w8a8 GEMM, supporting asymmetric per-tensor or per-row/column\n // quantization.\n ops.def(\n \"cutlass_scaled_mm_azp(Tensor! out, Tensor a,\"\n \" Tensor b, Tensor a_scales,\"\n \" Tensor b_scales, Tensor azp_adj,\"\n \" Tensor? azp, Tensor? bias) -> ()\");\n ops.impl(\"cutlass_scaled_mm_azp\", torch::kCUDA, &cutlass_scaled_mm_azp);\n\n // Check if cutlass scaled_mm is supported for CUDA devices of the given\n // capability\n ops.def(\"cutlass_scaled_mm_supports_fp8(int cuda_device_capability) -> bool\");\n ops.impl(\"cutlass_scaled_mm_supports_fp8\", &cutlass_scaled_mm_supports_fp8);\n\n // Check if cutlass grouped gemm is supported for CUDA devices of the given\n // capability\n ops.def(\"cutlass_group_gemm_supported(int cuda_device_capability) -> bool\");\n ops.impl(\"cutlass_group_gemm_supported\", &cutlass_group_gemm_supported);\n\n // CUTLASS w8a8 grouped GEMM\n ops.def(\n \"cutlass_moe_mm(Tensor! out_tensors, Tensor a_tensors, Tensor b_tensors, \"\n \" Tensor a_scales, Tensor b_scales, Tensor expert_offsets, \"\n \" Tensor problem_sizes, Tensor a_strides, \"\n \" Tensor b_strides, Tensor c_strides, bool per_act_token, \"\n \" bool per_out_ch) -> ()\");\n ops.impl(\"cutlass_moe_mm\", torch::kCUDA, &cutlass_moe_mm);\n\n // A function that computes data required to run fused MoE with w8a8 grouped\n // GEMM. It takes topk_ids as an input, and computes expert_offsets\n // (token start indices of each expert). In addition to this, it computes\n // problem sizes for each expert's multiplication used by the two mms called\n // from fused MoE operation, and arrays with permutations required to shuffle\n // and de-shuffle the input/output of the fused operation.\n ops.def(\n \"get_cutlass_moe_mm_data(Tensor topk_ids, Tensor! expert_offsets, \"\n \" Tensor! problem_sizes1, Tensor! problem_sizes2, \"\n \" Tensor! input_permutation, \"\n \" Tensor! output_permutation, int num_experts, \"\n \" int n, int k, Tensor? blockscale_offsets) -> \"\n \"()\");\n ops.impl(\"get_cutlass_moe_mm_data\", torch::kCUDA, &get_cutlass_moe_mm_data);\n\n // A function that computes problem sizes for each expert's multiplication\n // used by the two mms called from fused MoE operation. It takes topk_ids as\n // an input, and computes problem_sizes1 and problem_sizes2 only.\n ops.def(\n \"get_cutlass_moe_mm_problem_sizes(Tensor topk_ids, \"\n \" Tensor! problem_sizes1, \"\n \" Tensor! problem_sizes2, \"\n \" int num_experts, int n, int k, \"\n \" Tensor? blockscale_offsets) -> ()\");\n ops.impl(\"get_cutlass_moe_mm_problem_sizes\", torch::kCUDA,\n &get_cutlass_moe_mm_problem_sizes);\n\n // A function that computes data required to run fused MoE with w8a8 grouped\n // GEMM and PPLX. It takes expert_num_tokens and non_zero_expert_idxs\n // as an input, and computes expert_offsets (token start indices of each\n // expert). In addition to this, it computes problem sizes for each expert's\n // multiplication used by the two mms called from fused MoE operation.\n ops.def(\n \"get_cutlass_pplx_moe_mm_data(Tensor! expert_offsets, \"\n \" Tensor! problem_sizes1, \"\n \" Tensor! problem_sizes2, \"\n \" Tensor expert_num_tokens, \"\n \" int num_local_experts, int padded_m, \"\n \" int n, int k) -> ()\");\n ops.impl(\"get_cutlass_pplx_moe_mm_data\", torch::kCUDA,\n &get_cutlass_pplx_moe_mm_data);\n\n // Check if cutlass scaled_mm supports block quantization (used by DeepSeekV3)\n ops.def(\n \"cutlass_scaled_mm_supports_block_fp8(int cuda_device_capability) -> \"\n \"bool\");\n ops.impl(\"cutlass_scaled_mm_supports_block_fp8\",\n &cutlass_scaled_mm_supports_block_fp8);\n\n // Check if cutlass sparse scaled_mm is supported for CUDA devices of the\n // given capability\n ops.def(\n \"cutlass_sparse_scaled_mm_supported(int cuda_device_capability) -> bool\");\n ops.impl(\"cutlass_sparse_scaled_mm_supported\",\n &cutlass_sparse_scaled_mm_supported);\n\n // CUTLASS sparse GEMM, supporting symmetric per-tensor or per-row/column\n // quantization, as well as bias\n ops.def(\n \"cutlass_scaled_sparse_mm(Tensor! out, Tensor a,\"\n \" Tensor bt_nzs,\"\n \" Tensor bt_meta, Tensor a_scales,\"\n \" Tensor b_scales, Tensor? bias) -> ()\");\n ops.impl(\"cutlass_scaled_sparse_mm\", torch::kCUDA, &cutlass_scaled_sparse_mm);\n\n // CUTLASS sparse matrix compressor\n ops.def(\"cutlass_sparse_compress(Tensor a) -> Tensor[]\");\n ops.impl(\"cutlass_sparse_compress\", &cutlass_sparse_compress);\n\n // SM100 CUTLASS MLA decode\n ops.def(\n \"sm100_cutlass_mla_decode(Tensor! out, Tensor! lse, Tensor q_nope,\"\n \" Tensor q_pe, Tensor kv_c_and_k_pe_cache,\"\n \" Tensor seq_lens, Tensor page_table,\"\n \" Tensor workspace, float scale,\"\n \" int num_kv_splits) -> ()\");\n // conditionally compiled so impl in source file\n\n // SM100 CUTLASS MLA workspace\n ops.def(\n \"sm100_cutlass_mla_get_workspace_size(int max_seq_len, int num_batches,\"\n \" int sm_count, int num_kv_splits) \"\n \"-> int\");\n // conditionally compiled so impl in source file\n\n // Compute NVFP4 block quantized tensor.\n ops.def(\n \"scaled_fp4_quant(Tensor! output, Tensor input,\"\n \" Tensor! output_scale, Tensor input_scale) -> ()\");\n ops.impl(\"scaled_fp4_quant\", torch::kCUDA, &scaled_fp4_quant);\n\n // Compute NVFP4 experts quantization.\n ops.def(\n \"scaled_fp4_experts_quant(Tensor! output, Tensor! output_scale,\"\n \"Tensor input, Tensor input_global_scale, Tensor input_offset_by_experts,\"\n \"Tensor output_scale_offset_by_experts) -> ()\");\n ops.impl(\"scaled_fp4_experts_quant\", torch::kCUDA, &scaled_fp4_experts_quant);\n\n // Check if cutlass_scaled_mm_fp4 is supported for CUDA devices\n // of the given capability\n ops.def(\"cutlass_scaled_mm_supports_fp4(int cuda_device_capability) -> bool\");\n ops.impl(\"cutlass_scaled_mm_supports_fp4\", &cutlass_scaled_mm_supports_fp4);\n#endif\n\n // Quantized GEMM for GPTQ.\n // Note: even though the C++ inferred schema is correct for this op, it seems\n // to prevent the meta function registry.\n ops.def(\n \"gptq_gemm(Tensor a, Tensor b_q_weight, Tensor b_gptq_qzeros, \"\n \"Tensor b_gptq_scales, Tensor b_g_idx, bool use_exllama, bool \"\n \"use_v2_format, int bit) \"\n \"-> Tensor\");\n ops.impl(\"gptq_gemm\", torch::kCUDA, &gptq_gemm);\n\n // Post processing for GPTQ.\n ops.def(\"gptq_shuffle(Tensor! q_weight, Tensor q_perm, int bit) -> ()\");\n ops.impl(\"gptq_shuffle\", torch::kCUDA, &gptq_shuffle);\n\n // Compute FP8 quantized tensor for given scaling factor.\n ops.def(\n \"static_scaled_fp8_quant(Tensor! result, Tensor input, Tensor scale) -> \"\n \"()\");\n ops.impl(\"static_scaled_fp8_quant\", torch::kCUDA, &static_scaled_fp8_quant);\n\n // Compute dynamic-per-tensor FP8 quantized tensor and scaling factor.\n ops.def(\n \"dynamic_scaled_fp8_quant(Tensor! result, Tensor input, Tensor! scale) \"\n \"-> \"\n \"()\");\n ops.impl(\"dynamic_scaled_fp8_quant\", torch::kCUDA, &dynamic_scaled_fp8_quant);\n\n // Compute dynamic-per-token FP8 quantized tensor and scaling factor.\n ops.def(\n \"dynamic_per_token_scaled_fp8_quant(Tensor! result, Tensor input, \"\n \"Tensor! scale, Tensor? scale_ub) -> \"\n \"()\");\n ops.impl(\"dynamic_per_token_scaled_fp8_quant\", torch::kCUDA,\n &dynamic_per_token_scaled_fp8_quant);\n\n // Compute int8 quantized tensor for given scaling factor.\n ops.def(\n \"static_scaled_int8_quant(Tensor! result, Tensor input, Tensor scale,\"\n \"Tensor? azp) -> ()\");\n ops.impl(\"static_scaled_int8_quant\", torch::kCUDA, &static_scaled_int8_quant);\n\n // Compute int8 quantized tensor and scaling factor\n ops.def(\n \"dynamic_scaled_int8_quant(Tensor! result, Tensor input, Tensor! scale, \"\n \"Tensor!? azp) -> ()\");\n ops.impl(\"dynamic_scaled_int8_quant\", torch::kCUDA,\n &dynamic_scaled_int8_quant);\n\n // Mamba selective scan kernel\n ops.def(\n \"selective_scan_fwd(Tensor! u, Tensor! delta,\"\n \"Tensor! A, Tensor! B, Tensor! C,\"\n \"Tensor? D_, Tensor!? z_, Tensor? delta_bias_,\"\n \"bool delta_softplus,\"\n \"Tensor? query_start_loc,\"\n \"Tensor? cache_indices,\"\n \"Tensor? has_initial_state,\"\n \"Tensor! ssm_states,\"\n \"int pad_slot_id,\"\n \"int block_size,\"\n \"Tensor? block_idx_first_scheduled_token,\"\n \"Tensor? block_idx_last_scheduled_token,\"\n \"Tensor? initial_state_idx) -> ()\");\n ops.impl(\"selective_scan_fwd\", torch::kCUDA, &selective_scan_fwd);\n\n // Hadamard transforms\n ops.def(\"hadacore_transform(Tensor! x, bool inplace) -> Tensor\");\n\n#ifndef USE_ROCM\n // Compute per-token-group FP8 quantized tensor and scaling factor.\n ops.def(\n \"per_token_group_fp8_quant(Tensor input, Tensor! output_q, Tensor! \"\n \"output_s, \"\n \"int group_size, float eps, float fp8_min, float fp8_max, bool \"\n \"scale_ue8m0) -> ()\");\n ops.impl(\"per_token_group_fp8_quant\", torch::kCUDA,\n &per_token_group_quant_fp8);\n\n // Compute per-token-group 8-bit quantized tensor and UE8M0-packed,\n // TMA-aligned scales for DeepGEMM.\n ops.def(\n \"per_token_group_fp8_quant_packed(Tensor input, Tensor! output_q, \"\n \"Tensor! output_s_packed, int group_size, float eps, float fp8_min, \"\n \"float fp8_max) -> ()\");\n ops.impl(\"per_token_group_fp8_quant_packed\", torch::kCUDA,\n &per_token_group_quant_8bit_packed);\n\n // Compute per-token-group INT8 quantized tensor and scaling factor.\n ops.def(\n \"per_token_group_quant_int8(Tensor input, Tensor! output_q, Tensor! \"\n \"output_s, int group_size, float eps, float int8_min, float int8_max) -> \"\n \"()\");\n ops.impl(\"per_token_group_quant_int8\", torch::kCUDA,\n &per_token_group_quant_int8);\n\n // reorder weight for AllSpark Ampere W8A16 Fused Gemm kernel\n ops.def(\n \"rearrange_kn_weight_as_n32k16_order(Tensor b_qweight, Tensor b_scales, \"\n \"Tensor? b_zeros, \"\n \"bool has_zp, Tensor! b_qweight_reorder, Tensor! b_scales_reorder, \"\n \"Tensor!? b_zeros_reorder, \"\n \"int K, int N, int N_32align) -> ()\");\n // conditionally compiled so impl in source file\n\n // AllSpark quantization ops\n ops.def(\n \"allspark_w8a16_gemm(Tensor a, Tensor b_qweight, Tensor b_scales, \"\n \"Tensor? b_qzeros, \"\n \"SymInt n, SymInt group_size, SymInt sm_count, SymInt sm_version, SymInt \"\n \"CUBLAS_M_THRESHOLD, bool has_zp, bool n32k16_reorder) -> Tensor\");\n // conditionally compiled so impl in source file\n#endif\n}\n\nTORCH_LIBRARY_EXPAND(CONCAT(TORCH_EXTENSION_NAME, _cache_ops), cache_ops) {\n // Cache ops\n // Swap in (out) the cache blocks from src to dst.\n cache_ops.def(\n \"swap_blocks(Tensor src, Tensor! dst, Tensor block_mapping) -> ()\");\n cache_ops.impl(\"swap_blocks\", torch::kCUDA, &swap_blocks);\n\n // Copy the cache blocks from src to dst.\n cache_ops.def(\n \"copy_blocks(Tensor(a!)[] key_caches, Tensor[](b!) value_caches, \"\n \"Tensor block_mapping) -> ()\");\n cache_ops.impl(\"copy_blocks\", torch::kCUDA, ©_blocks);\n\n cache_ops.def(\n \"copy_blocks_mla(Tensor(a!)[] kv_caches, Tensor block_mapping) -> ()\");\n cache_ops.impl(\"copy_blocks_mla\", torch::kCUDA, ©_blocks_mla);\n\n // Reshape the key and value tensors and cache them.\n cache_ops.def(\n \"reshape_and_cache(Tensor key, Tensor value,\"\n \" Tensor! key_cache, Tensor! value_cache,\"\n \" Tensor slot_mapping,\"\n \" str kv_cache_dtype,\"\n \" Tensor k_scale, Tensor v_scale) -> ()\");\n cache_ops.impl(\"reshape_and_cache\", torch::kCUDA, &reshape_and_cache);\n\n // Reshape the key and value tensors and cache them.\n cache_ops.def(\n \"reshape_and_cache_flash(Tensor key, Tensor value,\"\n \" Tensor! key_cache,\"\n \" Tensor! value_cache,\"\n \" Tensor slot_mapping,\"\n \" str kv_cache_dtype,\"\n \" Tensor k_scale, Tensor v_scale) -> ()\");\n cache_ops.impl(\"reshape_and_cache_flash\", torch::kCUDA,\n &reshape_and_cache_flash);\n\n // Concat kv_c and k_pe and cache them.\n cache_ops.def(\n \"concat_and_cache_mla(Tensor kv_c, Tensor k_pe,\"\n \" Tensor! kv_cache,\"\n \" Tensor slot_mapping,\"\n \" str kv_cache_dtype,\"\n \" Tensor scale) -> ()\");\n cache_ops.impl(\"concat_and_cache_mla\", torch::kCUDA, &concat_and_cache_mla);\n\n // Convert the key and value cache to fp8 data type.\n cache_ops.def(\n \"convert_fp8(Tensor! dst_cache, Tensor src_cache, float scale, \"\n \"str kv_cache_dtype) -> ()\");\n cache_ops.impl(\"convert_fp8\", torch::kCUDA, &convert_fp8);\n\n // Gather cache blocks from src_cache to dst, dequantizing from\n // src_cache's dtype to dst's dtype if necessary.\n cache_ops.def(\n \"gather_and_maybe_dequant_cache(Tensor src_cache, Tensor! dst, \"\n \" Tensor block_table, Tensor cu_seq_lens, \"\n \" Tensor token_to_seq, \"\n \" int num_tokens, \"\n \" str kv_cache_dtype, \"\n \" Tensor scale, Tensor? seq_starts) -> ()\");\n cache_ops.impl(\"gather_and_maybe_dequant_cache\", torch::kCUDA,\n &gather_and_maybe_dequant_cache);\n\n cache_ops.def(\n \"cp_gather_cache(Tensor src_cache, Tensor! dst, Tensor block_table, \"\n \"Tensor cu_seq_lens, int batch_size, Tensor? seq_starts) -> ()\");\n cache_ops.impl(\"cp_gather_cache\", torch::kCUDA, &cp_gather_cache);\n\n cache_ops.def(\n \"indexer_k_quant_and_cache(Tensor k, Tensor! kv_cache, Tensor \"\n \"slot_mapping, \"\n \"int quant_block_size, str kv_cache_dtype) -> ()\");\n cache_ops.impl(\"indexer_k_quant_and_cache\", torch::kCUDA,\n &indexer_k_quant_and_cache);\n\n cache_ops.def(\n \"cp_gather_indexer_k_quant_cache(Tensor kv_cache, Tensor! dst_k, Tensor! \"\n \"dst_scale, Tensor block_table, Tensor cu_seq_lens) -> ()\");\n cache_ops.impl(\"cp_gather_indexer_k_quant_cache\", torch::kCUDA,\n &cp_gather_indexer_k_quant_cache);\n}\n\nTORCH_LIBRARY_EXPAND(CONCAT(TORCH_EXTENSION_NAME, _cuda_utils), cuda_utils) {\n // Cuda utils\n\n // Gets the specified device attribute.\n cuda_utils.def(\"get_device_attribute(int attribute, int device_id) -> int\");\n cuda_utils.impl(\"get_device_attribute\", &get_device_attribute);\n\n // Gets the maximum shared memory per block device attribute.\n cuda_utils.def(\n \"get_max_shared_memory_per_block_device_attribute(int device_id) -> int\");\n cuda_utils.impl(\"get_max_shared_memory_per_block_device_attribute\",\n &get_max_shared_memory_per_block_device_attribute);\n}\n\nTORCH_LIBRARY_EXPAND(CONCAT(TORCH_EXTENSION_NAME, _custom_ar), custom_ar) {\n // Custom all-reduce kernels\n custom_ar.def(\n \"init_custom_ar(int[] ipc_tensors, Tensor rank_data, \"\n \"int rank, bool fully_connected) -> int\");\n custom_ar.impl(\"init_custom_ar\", torch::kCUDA, &init_custom_ar);\n custom_ar.def(\n \"all_reduce(int fa, Tensor inp, Tensor! out, int reg_buffer, \"\n \"int reg_buffer_sz_bytes) -> ()\");\n custom_ar.impl(\"all_reduce\", torch::kCUDA, &all_reduce);\n\n custom_ar.def(\"dispose\", &dispose);\n custom_ar.def(\"meta_size\", &meta_size);\n\n custom_ar.def(\"register_buffer\", ®ister_buffer);\n custom_ar.def(\"get_graph_buffer_ipc_meta\", &get_graph_buffer_ipc_meta);\n custom_ar.def(\"register_graph_buffers\", ®ister_graph_buffers);\n\n custom_ar.def(\"allocate_shared_buffer_and_handle\",\n &allocate_shared_buffer_and_handle);\n custom_ar.def(\"open_mem_handle(Tensor mem_handle) -> int\", &open_mem_handle);\n custom_ar.impl(\"open_mem_handle\", torch::kCPU, &open_mem_handle);\n\n custom_ar.def(\"free_shared_buffer\", &free_shared_buffer);\n#ifdef USE_ROCM\n // Quick Reduce all-reduce kernels\n custom_ar.def(\n \"qr_all_reduce(int fa, Tensor inp, Tensor out, int quant_level, bool \"\n \"cast_bf2half) -> ()\");\n custom_ar.impl(\"qr_all_reduce\", torch::kCUDA, &qr_all_reduce);\n\n custom_ar.def(\"init_custom_qr\", &init_custom_qr);\n custom_ar.def(\"qr_destroy\", &qr_destroy);\n\n custom_ar.def(\"qr_get_handle\", &qr_get_handle);\n\n custom_ar.def(\"qr_open_handles(int _fa, Tensor[](b!) handles) -> ()\");\n custom_ar.impl(\"qr_open_handles\", torch::kCPU, &qr_open_handles);\n\n // Max input size in bytes\n custom_ar.def(\"qr_max_size\", &qr_max_size);\n#endif\n}\n\nREGISTER_EXTENSION(TORCH_EXTENSION_NAME)\n"},"diff":{"kind":"string","value":"--- csrc/torch_bindings.cpp\n+++ csrc/torch_bindings.cpp\n@@ -617,6 +617,15 @@\n ops.impl(\"per_token_group_fp8_quant\", torch::kCUDA,\n &per_token_group_quant_fp8);\n \n+ // Compute per-token-group 8-bit quantized tensor and UE8M0-packed,\n+ // TMA-aligned scales for DeepGEMM.\n+ ops.def(\n+ \"per_token_group_fp8_quant_packed(Tensor input, Tensor! output_q, \"\n+ \"Tensor! output_s_packed, int group_size, float eps, float fp8_min, \"\n+ \"float fp8_max) -> ()\");\n+ ops.impl(\"per_token_group_fp8_quant_packed\", torch::kCUDA,\n+ &per_token_group_quant_8bit_packed);\n+\n // Compute per-token-group INT8 quantized tensor and scaling factor.\n ops.def(\n \"per_token_group_quant_int8(Tensor input, Tensor! output_q, Tensor! \""},"lines_added":{"kind":"number","value":9,"string":"9"},"lines_removed":{"kind":"number","value":0,"string":"0"},"files_in_commit":{"kind":"number","value":5,"string":"5"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cpp kernel file from vllm (csrc/torch_bindings.cpp).\n\nGoal: [Perf] Deepgemm fused layout kernel for activations, 4.3% throughput improvement, 10.7% TTFT improvement.\nTarget hardware: unspecified\nTarget models: unspecified\n\nCurrent file:\n```cpp\n#include \"cache.h\"\n#include \"cuda_utils.h\"\n#include \"ops.h\"\n#include \"core/registration.h\"\n\n#include <torch/library.h>\n#include <torch/version.h>\n\n// Note on op signatures:\n// The X_meta signatures are for the meta functions corresponding to op X.\n// They must be kept in sync with the signature for X. Generally, only\n// functions that return Tensors require a meta function.\n//\n// See the following links for detailed docs on op registration and function\n// schemas.\n// https://docs.google.com/document/d/1_W62p8WJOQQUzPsJYa7s701JXt0qf2OfLub2sbkHOaU/edit#heading=h.ptttacy8y1u9\n// https://github.com/pytorch/pytorch/blob/main/aten/src/ATen/native/README.md#annotations\n\nTORCH_LIBRARY_EXPAND(TORCH_EXTENSION_NAME, ops) {\n // vLLM custom ops\n //\n\n ops.def(\n \"persistent_masked_m_silu_mul_quant(Tensor input, Tensor counts, Tensor! \"\n \"y_q, Tensor! y_s,\"\n \"bool use_ue8m0) -> ()\");\n ops.impl(\"persistent_masked_m_silu_mul_quant\", torch::kCUDA,\n &persistent_masked_m_silu_mul_quant);\n\n ops.def(\"weak_ref_tensor(Tensor input) -> Tensor\");\n ops.impl(\"weak_ref_tensor\", torch::kCUDA, &weak_ref_tensor);\n\n ops.def(\"get_cuda_view_from_cpu_tensor(Tensor cpu_tensor) -> Tensor\");\n ops.impl(\"get_cuda_view_from_cpu_tensor\", torch::kCPU,\n &get_cuda_view_from_cpu_tensor);\n\n // Attention ops\n // Compute the attention between an input query and the cached\n // keys/values using PagedAttention.\n ops.def(\n \"paged_attention_v1(\"\n \" Tensor! out, Tensor query, Tensor key_cache,\"\n \" Tensor value_cache, int num_kv_heads, float scale,\"\n \" Tensor block_tables, Tensor seq_lens, int block_size,\"\n \" int max_seq_len, Tensor? alibi_slopes,\"\n \" str kv_cache_dtype, Tensor k_scale, Tensor v_scale,\"\n \" int tp_rank, int blocksparse_local_blocks,\"\n \" int blocksparse_vert_stride, int blocksparse_block_size,\"\n \" int blocksparse_head_sliding_step) -> ()\");\n ops.impl(\"paged_attention_v1\", torch::kCUDA, &paged_attention_v1);\n\n // PagedAttention V2.\n ops.def(\n \"paged_attention_v2(\"\n \" Tensor! out, Tensor! exp_sums, Tensor! max_logits,\"\n \" Tensor! tmp_out, Tensor query, Tensor key_cache,\"\n \" Tensor value_cache, int num_kv_heads, float scale,\"\n \" Tensor block_tables, Tensor seq_lens, int block_size,\"\n \" int max_seq_len, Tensor? alibi_slopes,\"\n \" str kv_cache_dtype, Tensor k_scale, Tensor v_scale,\"\n \" int tp_rank, int blocksparse_local_blocks,\"\n \" int blocksparse_vert_stride, int blocksparse_block_size,\"\n \" int blocksparse_head_sliding_step) -> ()\");\n ops.impl(\"paged_attention_v2\", torch::kCUDA, &paged_attention_v2);\n\n // Merge attn states\n // Implements section 2.2 of https://www.arxiv.org/pdf/2501.01005\n // can be used to combine partial attention results (in the split-KV case)\n ops.def(\n \"merge_attn_states(\"\n \" Tensor! output,\"\n \" Tensor!? output_lse,\"\n \" Tensor prefix_output,\"\n \" Tensor prefix_lse,\"\n \" Tensor suffix_output,\"\n \" Tensor suffix_lse) -> ()\");\n ops.impl(\"merge_attn_states\", torch::kCUDA, &merge_attn_states);\n#ifndef USE_ROCM\n ops.def(\n \"convert_vertical_slash_indexes(\"\n \" Tensor! block_count, Tensor! block_offset, \"\n \" Tensor! column_count, Tensor! column_index, \"\n \" Tensor q_seqlens, Tensor q_seqlens, \"\n \" Tensor vertical_indexes, Tensor slash_indexes, \"\n \" int context_size, int block_size_M, int block_size_N, \"\n \" bool causal) -> ()\");\n ops.impl(\"convert_vertical_slash_indexes\", torch::kCUDA,\n &convert_vertical_slash_indexes);\n\n ops.def(\n \"convert_vertical_slash_indexes_mergehead(\"\n \" Tensor! block_count, Tensor! block_offset, \"\n \" Tensor! column_count, Tensor! column_index, \"\n \" Tensor q_seqlens, Tensor q_seqlens, \"\n \" Tensor vertical_indexes, Tensor slash_indexes, \"\n \" Tensor vertical_indices_count, Tensor slash_indices_count, \"\n \" int context_size, int block_size_M, int block_size_N, \"\n \" bool causal) -> ()\");\n ops.impl(\"convert_vertical_slash_indexes_mergehead\", torch::kCUDA,\n &convert_vertical_slash_indexes_mergehead);\n#endif\n\n // Activation ops\n // Activation function used in SwiGLU.\n ops.def(\"silu_and_mul(Tensor! result, Tensor input) -> ()\");\n ops.impl(\"silu_and_mul\", torch::kCUDA, &silu_and_mul);\n\n ops.def(\n \"silu_and_mul_quant(Tensor! result, Tensor input, Tensor scale) -> ()\");\n ops.impl(\"silu_and_mul_quant\", torch::kCUDA, &silu_and_mul_quant);\n\n#ifndef USE_ROCM\n ops.def(\n \"silu_and_mul_nvfp4_quant(Tensor! result, Tensor! result_block_scale, \"\n \"Tensor input, Tensor input_global_scale) -> ()\");\n ops.impl(\"silu_and_mul_nvfp4_quant\", torch::kCUDA, &silu_and_mul_nvfp4_quant);\n#endif\n\n ops.def(\"mul_and_silu(Tensor! out, Tensor input) -> ()\");\n ops.impl(\"mul_and_silu\", torch::kCUDA, &mul_and_silu);\n\n // Activation function used in GeGLU with `none` approximation.\n ops.def(\"gelu_and_mul(Tensor! out, Tensor input) -> ()\");\n ops.impl(\"gelu_and_mul\", torch::kCUDA, &gelu_and_mul);\n\n // Activation function used in GeGLU with `tanh` approximation.\n ops.def(\"gelu_tanh_and_mul(Tensor! out, Tensor input) -> ()\");\n ops.impl(\"gelu_tanh_and_mul\", torch::kCUDA, &gelu_tanh_and_mul);\n\n // FATReLU implementation.\n ops.def(\"fatrelu_and_mul(Tensor! out, Tensor input, float threshold) -> ()\");\n ops.impl(\"fatrelu_and_mul\", torch::kCUDA, &fatrelu_and_mul);\n\n ops.def(\n \"swigluoai_and_mul(Tensor! out, Tensor input, float alpha=1.702, float \"\n \"limit=7.0) \"\n \"-> ()\");\n ops.impl(\"swigluoai_and_mul\", torch::kCUDA, &swigluoai_and_mul);\n\n // GELU implementation used in GPT-2.\n ops.def(\"gelu_new(Tensor! out, Tensor input) -> ()\");\n ops.impl(\"gelu_new\", torch::kCUDA, &gelu_new);\n\n // Approximate GELU implementation.\n ops.def(\"gelu_fast(Tensor! out, Tensor input) -> ()\");\n ops.impl(\"gelu_fast\", torch::kCUDA, &gelu_fast);\n\n // Quick GELU implementation.\n ops.def(\"gelu_quick(Tensor! out, Tensor input) -> ()\");\n ops.impl(\"gelu_quick\", torch::kCUDA, &gelu_quick);\n\n // Layernorm\n // Apply Root Mean Square (RMS) Normalization to the input tensor.\n ops.def(\n \"rms_norm(Tensor! result, Tensor input, Tensor weight, float epsilon) -> \"\n \"()\");\n ops.impl(\"rms_norm\", torch::kCUDA, &rms_norm);\n\n // In-place fused Add and RMS Normalization.\n ops.def(\n \"fused_add_rms_norm(Tensor! input, Tensor! residual, Tensor weight, \"\n \"float epsilon) -> ()\");\n ops.impl(\"fused_add_rms_norm\", torch::kCUDA, &fused_add_rms_norm);\n\n // Function for fused QK Norm and RoPE\n ops.def(\n \"fused_qk_norm_rope(Tensor! qkv, int num_heads_q, \"\n \"int num_heads_k, int num_heads_v, int head_dim, float eps, \"\n \"Tensor q_weight, Tensor k_weight, Tensor cos_sin_cache, \"\n \"bool is_neox, Tensor position_ids) -> ()\");\n ops.impl(\"fused_qk_norm_rope\", torch::kCUDA, &fused_qk_norm_rope);\n\n // Apply repetition penalties to logits in-place\n ops.def(\n \"apply_repetition_penalties_(Tensor! logits, Tensor prompt_mask, \"\n \"Tensor output_mask, Tensor repetition_penalties) -> ()\");\n ops.impl(\"apply_repetition_penalties_\", torch::kCUDA,\n &apply_repetition_penalties_);\n\n // Optimized top-k per row operation\n ops.def(\n \"top_k_per_row(Tensor logits, Tensor rowStarts, Tensor rowEnds, \"\n \"Tensor! indices, int numRows, int stride0, \"\n \"int stride1) -> ()\");\n ops.impl(\"top_k_per_row\", torch::kCUDA, &top_k_per_row);\n\n ops.def(\n \"top_k_per_row_decode(Tensor logits, int next_n, \"\n \"Tensor seq_lens, Tensor! indices, int numRows, \"\n \"int stride0, int stride1) -> ()\");\n ops.impl(\"top_k_per_row_decode\", torch::kCUDA, &top_k_per_row_decode);\n\n // Layernorm-quant\n // Apply Root Mean Square (RMS) Normalization to the input tensor.\n ops.def(\n \"rms_norm_static_fp8_quant(Tensor! result, Tensor input, Tensor weight, \"\n \"Tensor scale, float epsilon) -> \"\n \"()\");\n ops.impl(\"rms_norm_static_fp8_quant\", torch::kCUDA,\n &rms_norm_static_fp8_quant);\n\n // In-place fused Add and RMS Normalization.\n ops.def(\n \"fused_add_rms_norm_static_fp8_quant(Tensor! result, Tensor input, \"\n \"Tensor! residual, Tensor weight, \"\n \"Tensor scale, float epsilon) -> ()\");\n ops.impl(\"fused_add_rms_norm_static_fp8_quant\", torch::kCUDA,\n &fused_add_rms_norm_static_fp8_quant);\n\n // Fused Layernorm + Quant kernels\n ops.def(\n \"rms_norm_dynamic_per_token_quant(Tensor! result, Tensor input, \"\n \"Tensor weight, Tensor! scale, float epsilon, \"\n \"Tensor? scale_ub, Tensor!? residual) -> ()\");\n ops.impl(\"rms_norm_dynamic_per_token_quant\", torch::kCUDA,\n &rms_norm_dynamic_per_token_quant);\n\n // Rotary embedding\n // Apply GPT-NeoX or GPT-J style rotary embedding to query and key.\n ops.def(\n \"rotary_embedding(Tensor positions, Tensor! query,\"\n \" Tensor!? key, int head_size,\"\n \" Tensor cos_sin_cache, bool is_neox) -> ()\");\n ops.impl(\"rotary_embedding\", torch::kCUDA, &rotary_embedding);\n\n // Quantization ops\n#ifndef USE_ROCM\n // Quantized GEMM for AWQ.\n ops.def(\n \"awq_gemm(Tensor _in_feats, Tensor _kernel, Tensor _scaling_factors, \"\n \"Tensor _zeros, SymInt split_k_iters) -> Tensor\");\n ops.impl(\"awq_gemm\", torch::kCUDA, &awq_gemm);\n\n // Dequantization for AWQ.\n ops.def(\n \"awq_dequantize(Tensor _kernel, Tensor _scaling_factors, \"\n \"Tensor _zeros, SymInt split_k_iters, int thx, int thy) -> Tensor\");\n ops.impl(\"awq_dequantize\", torch::kCUDA, &awq_dequantize);\n\n // Note about marlin kernel 'workspace' arguments:\n // Technically these should be mutable since they are modified by the kernel.\n // But since they are set back to zero once the kernel is finished we can\n // hand wave and say that they have no net effect.\n //\n // The reason to mark 'workspace' as immutable is so that they don't interfere\n // with using ScalarType arguments in the ops. If they are marked as mutable,\n // pytorch throws an assert in\n // 'torch._higher_order_ops._register_effectful_op' that prevents these\n // kernels from being torch.compile'd.\n // See the following document for more info on custom types and ops that use\n // custom types:\n // https://docs.google.com/document/d/18fBMPuOJ0fY5ZQ6YyrHUppw9FA332CpNtgB6SOIgyuA\n\n // Marlin_24 (Sparse) Optimized Quantized GEMM for GPTQ.\n ops.def(\n \"gptq_marlin_24_gemm(Tensor a, Tensor b_q_weight, Tensor b_meta, \"\n \"Tensor b_scales, Tensor workspace, \"\n \"int b_q_type, \"\n \"SymInt size_m, SymInt size_n, SymInt size_k) -> Tensor\");\n // conditionally compiled so impl in source file\n\n // Machete (Dense) Optimized Mixed Precision GEMM for Hopper.\n ops.def(\n \"machete_supported_schedules(\"\n \" ScalarType a_type,\"\n \" int b_type,\"\n \" ScalarType? maybe_group_scales_type,\"\n \" ScalarType? maybe_group_zeros_type,\"\n \" ScalarType? maybe_channel_scales_type,\"\n \" ScalarType? maybe_token_scales_type,\"\n \" ScalarType? maybe_out_type\"\n \") -> str[]\");\n ops.def(\n \"machete_mm(\"\n \" Tensor A,\"\n \" Tensor B,\"\n \" int b_type,\"\n \" ScalarType? out_type,\"\n \" Tensor? group_scales,\"\n \" Tensor? group_zeros,\"\n \" int? group_size,\"\n \" Tensor? channel_scales,\"\n \" Tensor? token_scales,\"\n \" str? schedule\"\n \") -> Tensor\");\n ops.def(\n \"machete_prepack_B(\"\n \" Tensor B,\"\n \" ScalarType a_type,\"\n \" int b_type,\"\n \" ScalarType? group_scales_type\"\n \") -> Tensor\");\n // conditionally compiled so impl registration is in source file\n\n ops.def(\"permute_cols(Tensor A, Tensor perm) -> Tensor\");\n ops.impl(\"permute_cols\", torch::kCUDA, &permute_cols);\n\n // gptq_marlin Optimized Quantized GEMM for GPTQ.\n ops.def(\n \"gptq_marlin_gemm(Tensor a, Tensor? c_or_none, Tensor b_q_weight, \"\n \"Tensor? b_bias_or_none,Tensor b_scales, \"\n \"Tensor? a_scales, Tensor? global_scale, Tensor? b_zeros_or_none, \"\n \"Tensor? \"\n \"g_idx_or_none, Tensor? perm_or_none, Tensor workspace, int b_type_id, \"\n \"SymInt size_m, SymInt size_n, SymInt size_k, bool is_k_full, \"\n \"bool use_atomic_add, bool use_fp32_reduce, bool is_zp_float) -> Tensor\");\n // conditionally compiled so impl registration is in source file\n\n // gptq_marlin repack from GPTQ.\n ops.def(\n \"gptq_marlin_repack(Tensor b_q_weight, Tensor perm, \"\n \"SymInt size_k, SymInt size_n, int num_bits, bool is_a_8bit) -> Tensor\");\n // conditionally compiled so impl registrations are in source file\n\n // awq_marlin repack from AWQ.\n ops.def(\n \"awq_marlin_repack(Tensor b_q_weight, SymInt size_k, \"\n \"SymInt size_n, int num_bits, bool is_a_8bit) -> Tensor\");\n // conditionally compiled so impl registrations are in source file\n\n // preprocess W-int4A-fp8 weight for marlin kernel\n ops.def(\n \"marlin_int4_fp8_preprocess(Tensor qweight, \"\n \"Tensor? qzeros_or_none, bool inplace) -> Tensor\");\n // conditionally compiled so impl registrations are in source file\n\n // CUTLASS w4a8 GEMM\n ops.def(\n \"cutlass_w4a8_mm(\"\n \" Tensor A,\"\n \" Tensor B,\"\n \" Tensor group_scales,\"\n \" int group_size,\"\n \" Tensor channel_scales,\"\n \" Tensor token_scales,\"\n \" ScalarType? out_type,\"\n \" str? maybe_schedule\"\n \") -> Tensor\");\n // pack scales\n ops.def(\"cutlass_pack_scale_fp8(Tensor scales) -> Tensor\");\n // encode and reorder weight matrix\n ops.def(\"cutlass_encode_and_reorder_int4b(Tensor B) -> Tensor\");\n // conditionally compiled so impl registration is in source file\n\n#endif\n\n // Dequantization for GGML.\n ops.def(\n \"ggml_dequantize(Tensor W, int type, SymInt m, SymInt n, ScalarType? \"\n \"dtype) -> Tensor\");\n ops.impl(\"ggml_dequantize\", torch::kCUDA, &ggml_dequantize);\n\n // mmvq kernel for GGML.\n ops.def(\n \"ggml_mul_mat_vec_a8(Tensor W, Tensor X, int type, SymInt row) \"\n \"-> Tensor\");\n ops.impl(\"ggml_mul_mat_vec_a8\", torch::kCUDA, &ggml_mul_mat_vec_a8);\n\n // mmq kernel for GGML.\n ops.def(\n \"ggml_mul_mat_a8(Tensor W, Tensor X, int type, SymInt row) -> Tensor\");\n ops.impl(\"ggml_mul_mat_a8\", torch::kCUDA, &ggml_mul_mat_a8);\n\n // moe kernel for GGML.\n ops.def(\n \"ggml_moe_a8(Tensor X, Tensor W, \"\n \"Tensor sorted_token_ids, Tensor expert_ids, Tensor \"\n \"num_tokens_post_padded, \"\n \"int type, SymInt row, SymInt top_k, SymInt tokens) -> Tensor\");\n ops.impl(\"ggml_moe_a8\", torch::kCUDA, &ggml_moe_a8);\n\n ops.def(\n \"ggml_moe_a8_vec(Tensor X, Tensor W, \"\n \"Tensor topk_ids, int top_k, \"\n \"int type, SymInt row, SymInt tokens) -> Tensor\");\n ops.impl(\"ggml_moe_a8_vec\", torch::kCUDA, &ggml_moe_a8_vec);\n\n ops.def(\"ggml_moe_get_block_size\", &ggml_moe_get_block_size);\n\n#ifndef USE_ROCM\n // CUTLASS nvfp4 block scaled GEMM\n ops.def(\n \"cutlass_scaled_fp4_mm(Tensor! out, Tensor a, Tensor b,\"\n \" Tensor block_scale_a, Tensor block_scale_b,\"\n \" Tensor alpha) -> ()\");\n ops.impl(\"cutlass_scaled_fp4_mm\", torch::kCUDA, &cutlass_scaled_fp4_mm);\n\n // cutlass blockwise scaledgroup GEMM\n ops.def(\n \"cutlass_blockwise_scaled_grouped_mm(Tensor! output, Tensor a, Tensor b, \"\n \"Tensor scales_a, Tensor scales_b, \"\n \"Tensor problem_sizes, Tensor expert_offsets) -> ()\");\n // conditionally compiled so impl registration is in source file\n\n // cutlass nvfp4 block scaled group GEMM\n ops.def(\n \"cutlass_fp4_group_mm(Tensor! out, Tensor a, Tensor b,\"\n \" Tensor a_blockscale, Tensor b_blockscales, Tensor alphas,\"\n \" Tensor problem_sizes, Tensor expert_offsets, Tensor sf_offsets) -> ()\");\n // conditionally compiled so impl registration is in source file\n\n // CUTLASS w8a8 GEMM, supporting symmetric per-tensor or per-row/column\n // quantization, as well as bias\n ops.def(\n \"cutlass_scaled_mm(Tensor! out, Tensor a,\"\n \" Tensor b, Tensor a_scales,\"\n \" Tensor b_scales, Tensor? bias) -> ()\");\n ops.impl(\"cutlass_scaled_mm\", torch::kCUDA, &cutlass_scaled_mm);\n\n // CUTLASS w8a8 GEMM, supporting asymmetric per-tensor or per-row/column\n // quantization.\n ops.def(\n \"cutlass_scaled_mm_azp(Tensor! out, Tensor a,\"\n \" Tensor b, Tensor a_scales,\"\n \" Tensor b_scales, Tensor azp_adj,\"\n \" Tensor? azp, Tensor? bias) -> ()\");\n ops.impl(\"cutlass_scaled_mm_azp\", torch::kCUDA, &cutlass_scaled_mm_azp);\n\n // Check if cutlass scaled_mm is supported for CUDA devices of the given\n // capability\n ops.def(\"cutlass_scaled_mm_supports_fp8(int cuda_device_capability) -> bool\");\n ops.impl(\"cutlass_scaled_mm_supports_fp8\", &cutlass_scaled_mm_supports_fp8);\n\n // Check if cutlass grouped gemm is supported for CUDA devices of the given\n // capability\n ops.def(\"cutlass_group_gemm_supported(int cuda_device_capability) -> bool\");\n ops.impl(\"cutlass_group_gemm_supported\", &cutlass_group_gemm_supported);\n\n // CUTLASS w8a8 grouped GEMM\n ops.def(\n \"cutlass_moe_mm(Tensor! out_tensors, Tensor a_tensors, Tensor b_tensors, \"\n \" Tensor a_scales, Tensor b_scales, Tensor expert_offsets, \"\n \" Tensor problem_sizes, Tensor a_strides, \"\n \" Tensor b_strides, Tensor c_strides, bool per_act_token, \"\n \" bool per_out_ch) -> ()\");\n ops.impl(\"cutlass_moe_mm\", torch::kCUDA, &cutlass_moe_mm);\n\n // A function that computes data required to run fused MoE with w8a8 grouped\n // GEMM. It takes topk_ids as an input, and computes expert_offsets\n // (token start indices of each expert). In addition to this, it computes\n // problem sizes for each expert's multiplication used by the two mms called\n // from fused MoE operation, and arrays with permutations required to shuffle\n // and de-shuffle the input/output of the fused operation.\n ops.def(\n \"get_cutlass_moe_mm_data(Tensor topk_ids, Tensor! expert_offsets, \"\n \" Tensor! problem_sizes1, Tensor! problem_sizes2, \"\n \" Tensor! input_permutation, \"\n \" Tensor! output_permutation, int num_experts, \"\n \" int n, int k, Tensor? blockscale_offsets) -> \"\n \"()\");\n ops.impl(\"get_cutlass_moe_mm_data\", torch::kCUDA, &get_cutlass_moe_mm_data);\n\n // A function that computes problem sizes for each expert's multiplication\n // used by the two mms called from fused MoE operation. It takes topk_ids as\n // an input, and computes problem_sizes1 and problem_sizes2 only.\n ops.def(\n \"get_cutlass_moe_mm_problem_sizes(Tensor topk_ids, \"\n \" Tensor! problem_sizes1, \"\n \" Tensor! problem_sizes2, \"\n \" int num_experts, int n, int k, \"\n \" Tensor? blockscale_offsets) -> ()\");\n ops.impl(\"get_cutlass_moe_mm_problem_sizes\", torch::kCUDA,\n &get_cutlass_moe_mm_problem_sizes);\n\n // A function that computes data required to run fused MoE with w8a8 grouped\n // GEMM and PPLX. It takes expert_num_tokens and non_zero_expert_idxs\n // as an input, and computes expert_offsets (token start indices of each\n // expert). In addition to this, it computes problem sizes for each expert's\n // multiplication used by the two mms called from fused MoE operation.\n ops.def(\n \"get_cutlass_pplx_moe_mm_data(Tensor! expert_offsets, \"\n \" Tensor! problem_sizes1, \"\n \" Tensor! problem_sizes2, \"\n \" Tensor expert_num_tokens, \"\n \" int num_local_experts, int padded_m, \"\n \" int n, int k) -> ()\");\n ops.impl(\"get_cutlass_pplx_moe_mm_data\", torch::kCUDA,\n &get_cutlass_pplx_moe_mm_data);\n\n // Check if cutlass scaled_mm supports block quantization (used by DeepSeekV3)\n ops.def(\n \"cutlass_scaled_mm_supports_block_fp8(int cuda_device_capability) -> \"\n \"bool\");\n ops.impl(\"cutlass_scaled_mm_supports_block_fp8\",\n &cutlass_scaled_mm_supports_block_fp8);\n\n // Check if cutlass sparse scaled_mm is supported for CUDA devices of the\n // given capability\n ops.def(\n \"cutlass_sparse_scaled_mm_supported(int cuda_device_capability) -> bool\");\n ops.impl(\"cutlass_sparse_scaled_mm_supported\",\n &cutlass_sparse_scaled_mm_supported);\n\n // CUTLASS sparse GEMM, supporting symmetric per-tensor or per-row/column\n // quantization, as well as bias\n ops.def(\n \"cutlass_scaled_sparse_mm(Tensor! out, Tensor a,\"\n \" Tensor bt_nzs,\"\n \" Tensor bt_meta, Tensor a_scales,\"\n \" Tensor b_scales, Tensor? bias) -> ()\");\n ops.impl(\"cutlass_scaled_sparse_mm\", torch::kCUDA, &cutlass_scaled_sparse_mm);\n\n // CUTLASS sparse matrix compressor\n ops.def(\"cutlass_sparse_compress(Tensor a) -> Tensor[]\");\n ops.impl(\"cutlass_sparse_compress\", &cutlass_sparse_compress);\n\n // SM100 CUTLASS MLA decode\n ops.def(\n \"sm100_cutlass_mla_decode(Tensor! out, Tensor! lse, Tensor q_nope,\"\n \" Tensor q_pe, Tensor kv_c_and_k_pe_cache,\"\n \" Tensor seq_lens, Tensor page_table,\"\n \" Tensor workspace, float scale,\"\n \" int num_kv_splits) -> ()\");\n // conditionally compiled so impl in source file\n\n // SM100 CUTLASS MLA workspace\n ops.def(\n \"sm100_cutlass_mla_get_workspace_size(int max_seq_len, int num_batches,\"\n \" int sm_count, int num_kv_splits) \"\n \"-> int\");\n // conditionally compiled so impl in source file\n\n // Compute NVFP4 block quantized tensor.\n ops.def(\n \"scaled_fp4_quant(Tensor! output, Tensor input,\"\n \" Tensor! output_scale, Tensor input_scale) -> ()\");\n ops.impl(\"scaled_fp4_quant\", torch::kCUDA, &scaled_fp4_quant);\n\n // Compute NVFP4 experts quantization.\n ops.def(\n \"scaled_fp4_experts_quant(Tensor! output, Tensor! output_scale,\"\n \"Tensor input, Tensor input_global_scale, Tensor input_offset_by_experts,\"\n \"Tensor output_scale_offset_by_experts) -> ()\");\n ops.impl(\"scaled_fp4_experts_quant\", torch::kCUDA, &scaled_fp4_experts_quant);\n\n // Check if cutlass_scaled_mm_fp4 is supported for CUDA devices\n // of the given capability\n ops.def(\"cutlass_scaled_mm_supports_fp4(int cuda_device_capability) -> bool\");\n ops.impl(\"cutlass_scaled_mm_supports_fp4\", &cutlass_scaled_mm_supports_fp4);\n#endif\n\n // Quantized GEMM for GPTQ.\n // Note: even though the C++ inferred schema is correct for this op, it seems\n // to prevent the meta function registry.\n ops.def(\n \"gptq_gemm(Tensor a, Tensor b_q_weight, Tensor b_gptq_qzeros, \"\n \"Tensor b_gptq_scales, Tensor b_g_idx, bool use_exllama, bool \"\n \"use_v2_format, int bit) \"\n \"-> Tensor\");\n ops.impl(\"gptq_gemm\", torch::kCUDA, &gptq_gemm);\n\n // Post processing for GPTQ.\n ops.def(\"gptq_shuffle(Tensor! q_weight, Tensor q_perm, int bit) -> ()\");\n ops.impl(\"gptq_shuffle\", torch::kCUDA, &gptq_shuffle);\n\n // Compute FP8 quantized tensor for given scaling factor.\n ops.def(\n \"static_scaled_fp8_quant(Tensor! result, Tensor input, Tensor scale) -> \"\n \"()\");\n ops.impl(\"static_scaled_fp8_quant\", torch::kCUDA, &static_scaled_fp8_quant);\n\n // Compute dynamic-per-tensor FP8 quantized tensor and scaling factor.\n ops.def(\n \"dynamic_scaled_fp8_quant(Tensor! result, Tensor input, Tensor! scale) \"\n \"-> \"\n \"()\");\n ops.impl(\"dynamic_scaled_fp8_quant\", torch::kCUDA, &dynamic_scaled_fp8_quant);\n\n // Compute dynamic-per-token FP8 quantized tensor and scaling factor.\n ops.def(\n \"dynamic_per_token_scaled_fp8_quant(Tensor! result, Tensor input, \"\n \"Tensor! scale, Tensor? scale_ub) -> \"\n \"()\");\n ops.impl(\"dynamic_per_token_scaled_fp8_quant\", torch::kCUDA,\n &dynamic_per_token_scaled_fp8_quant);\n\n // Compute int8 quantized tensor for given scaling factor.\n ops.def(\n \"static_scaled_int8_quant(Tensor! result, Tensor input, Tensor scale,\"\n \"Tensor? azp) -> ()\");\n ops.impl(\"static_scaled_int8_quant\", torch::kCUDA, &static_scaled_int8_quant);\n\n // Compute int8 quantized tensor and scaling factor\n ops.def(\n \"dynamic_scaled_int8_quant(Tensor! result, Tensor input, Tensor! scale, \"\n \"Tensor!? azp) -> ()\");\n ops.impl(\"dynamic_scaled_int8_quant\", torch::kCUDA,\n &dynamic_scaled_int8_quant);\n\n // Mamba selective scan kernel\n ops.def(\n \"selective_scan_fwd(Tensor! u, Tensor! delta,\"\n \"Tensor! A, Tensor! B, Tensor! C,\"\n \"Tensor? D_, Tensor!? z_, Tensor? delta_bias_,\"\n \"bool delta_softplus,\"\n \"Tensor? query_start_loc,\"\n \"Tensor? cache_indices,\"\n \"Tensor? has_initial_state,\"\n \"Tensor! ssm_states,\"\n \"int pad_slot_id,\"\n \"int block_size,\"\n \"Tensor? block_idx_first_scheduled_token,\"\n \"Tensor? block_idx_last_scheduled_token,\"\n \"Tensor? initial_state_idx) -> ()\");\n ops.impl(\"selective_scan_fwd\", torch::kCUDA, &selective_scan_fwd);\n\n // Hadamard transforms\n ops.def(\"hadacore_transform(Tensor! x, bool inplace) -> Tensor\");\n\n#ifndef USE_ROCM\n // Compute per-token-group FP8 quantized tensor and scaling factor.\n ops.def(\n \"per_token_group_fp8_quant(Tensor input, Tensor! output_q, Tensor! \"\n \"output_s, \"\n \"int group_size, float eps, float fp8_min, float fp8_max, bool \"\n \"scale_ue8m0) -> ()\");\n ops.impl(\"per_token_group_fp8_quant\", torch::kCUDA,\n &per_token_group_quant_fp8);\n\n // Compute per-token-group INT8 quantized tensor and scaling factor.\n ops.def(\n \"per_token_group_quant_int8(Tensor input, Tensor! output_q, Tensor! \"\n \"output_s, int group_size, float eps, float int8_min, float int8_max) -> \"\n \"()\");\n ops.impl(\"per_token_group_quant_int8\", torch::kCUDA,\n &per_token_group_quant_int8);\n\n // reorder weight for AllSpark Ampere W8A16 Fused Gemm kernel\n ops.def(\n \"rearrange_kn_weight_as_n32k16_order(Tensor b_qweight, Tensor b_scales, \"\n \"Tensor? b_zeros, \"\n \"bool has_zp, Tensor! b_qweight_reorder, Tensor! b_scales_reorder, \"\n \"Tensor!? b_zeros_reorder, \"\n \"int K, int N, int N_32align) -> ()\");\n // conditionally compiled so impl in source file\n\n // AllSpark quantization ops\n ops.def(\n \"allspark_w8a16_gemm(Tensor a, Tensor b_qweight, Tensor b_scales, \"\n \"Tensor? b_qzeros, \"\n \"SymInt n, SymInt group_size, SymInt sm_count, SymInt sm_version, SymInt \"\n \"CUBLAS_M_THRESHOLD, bool has_zp, bool n32k16_reorder) -> Tensor\");\n // conditionally compiled so impl in source file\n#endif\n}\n\nTORCH_LIBRARY_EXPAND(CONCAT(TORCH_EXTENSION_NAME, _cache_ops), cache_ops) {\n // Cache ops\n // Swap in (out) the cache blocks from src to dst.\n cache_ops.def(\n \"swap_blocks(Tensor src, Tensor! dst, Tensor block_mapping) -> ()\");\n cache_ops.impl(\"swap_blocks\", torch::kCUDA, &swap_blocks);\n\n // Copy the cache blocks from src to dst.\n cache_ops.def(\n \"copy_blocks(Tensor(a!)[] key_caches, Tensor[](b!) value_caches, \"\n \"Tensor block_mapping) -> ()\");\n cache_ops.impl(\"copy_blocks\", torch::kCUDA, ©_blocks);\n\n cache_ops.def(\n \"copy_blocks_mla(Tensor(a!)[] kv_caches, Tensor block_mapping) -> ()\");\n cache_ops.impl(\"copy_blocks_mla\", torch::kCUDA, ©_blocks_mla);\n\n // Reshape the key and value tensors and cache them.\n cache_ops.def(\n \"reshape_and_cache(Tensor key, Tensor value,\"\n \" Tensor! key_cache, Tensor! value_cache,\"\n \" Tensor slot_mapping,\"\n \" str kv_cache_dtype,\"\n \" Tensor k_scale, Tensor v_scale) -> ()\");\n cache_ops.impl(\"reshape_and_cache\", torch::kCUDA, &reshape_and_cache);\n\n // Reshape the key and value tensors and cache them.\n cache_ops.def(\n \"reshape_and_cache_flash(Tensor key, Tensor value,\"\n \" Tensor! key_cache,\"\n \" Tensor! value_cache,\"\n \" Tensor slot_mapping,\"\n \" str kv_cache_dtype,\"\n \" Tensor k_scale, Tensor v_scale) -> ()\");\n cache_ops.impl(\"reshape_and_cache_flash\", torch::kCUDA,\n &reshape_and_cache_flash);\n\n // Concat kv_c and k_pe and cache them.\n cache_ops.def(\n \"concat_and_cache_mla(Tensor kv_c, Tensor k_pe,\"\n \" Tensor! kv_cache,\"\n \" Tensor slot_mapping,\"\n \" str kv_cache_dtype,\"\n \" Tensor scale) -> ()\");\n cache_ops.impl(\"concat_and_cache_mla\", torch::kCUDA, &concat_and_cache_mla);\n\n // Convert the key and value cache to fp8 data type.\n cache_ops.def(\n \"convert_fp8(Tensor! dst_cache, Tensor src_cache, float scale, \"\n \"str kv_cache_dtype) -> ()\");\n cache_ops.impl(\"convert_fp8\", torch::kCUDA, &convert_fp8);\n\n // Gather cache blocks from src_cache to dst, dequantizing from\n // src_cache's dtype to dst's dtype if necessary.\n cache_ops.def(\n \"gather_and_maybe_dequant_cache(Tensor src_cache, Tensor! dst, \"\n \" Tensor block_table, Tensor cu_seq_lens, \"\n \" Tensor token_to_seq, \"\n \" int num_tokens, \"\n \" str kv_cache_dtype, \"\n \" Tensor scale, Tensor? seq_starts) -> ()\");\n cache_ops.impl(\"gather_and_maybe_dequant_cache\", torch::kCUDA,\n &gather_and_maybe_dequant_cache);\n\n cache_ops.def(\n \"cp_gather_cache(Tensor src_cache, Tensor! dst, Tensor block_table, \"\n \"Tensor cu_seq_lens, int batch_size, Tensor? seq_starts) -> ()\");\n cache_ops.impl(\"cp_gather_cache\", torch::kCUDA, &cp_gather_cache);\n\n cache_ops.def(\n \"indexer_k_quant_and_cache(Tensor k, Tensor! kv_cache, Tensor \"\n \"slot_mapping, \"\n \"int quant_block_size, str kv_cache_dtype) -> ()\");\n cache_ops.impl(\"indexer_k_quant_and_cache\", torch::kCUDA,\n &indexer_k_quant_and_cache);\n\n cache_ops.def(\n \"cp_gather_indexer_k_quant_cache(Tensor kv_cache, Tensor! dst_k, Tensor! \"\n \"dst_scale, Tensor block_table, Tensor cu_seq_lens) -> ()\");\n cache_ops.impl(\"cp_gather_indexer_k_quant_cache\", torch::kCUDA,\n &cp_gather_indexer_k_quant_cache);\n}\n\nTORCH_LIBRARY_EXPAND(CONCAT(TORCH_EXTENSION_NAME, _cuda_utils), cuda_utils) {\n // Cuda utils\n\n // Gets the specified device attribute.\n cuda_utils.def(\"get_device_attribute(int attribute, int device_id) -> int\");\n cuda_utils.impl(\"get_device_attribute\", &get_device_attribute);\n\n // Gets the maximum shared memory per block device attribute.\n cuda_utils.def(\n \"get_max_shared_memory_per_block_device_attribute(int device_id) -> int\");\n cuda_utils.impl(\"get_max_shared_memory_per_block_device_attribute\",\n &get_max_shared_memory_per_block_device_attribute);\n}\n\nTORCH_LIBRARY_EXPAND(CONCAT(TORCH_EXTENSION_NAME, _custom_ar), custom_ar) {\n // Custom all-reduce kernels\n custom_ar.def(\n \"init_custom_ar(int[] ipc_tensors, Tensor rank_data, \"\n \"int rank, bool fully_connected) -> int\");\n custom_ar.impl(\"init_custom_ar\", torch::kCUDA, &init_custom_ar);\n custom_ar.def(\n \"all_reduce(int fa, Tensor inp, Tensor! out, int reg_buffer, \"\n \"int reg_buffer_sz_bytes) -> ()\");\n custom_ar.impl(\"all_reduce\", torch::kCUDA, &all_reduce);\n\n custom_ar.def(\"dispose\", &dispose);\n custom_ar.def(\"meta_size\", &meta_size);\n\n custom_ar.def(\"register_buffer\", ®ister_buffer);\n custom_ar.def(\"get_graph_buffer_ipc_meta\", &get_graph_buffer_ipc_meta);\n custom_ar.def(\"register_graph_buffers\", ®ister_graph_buffers);\n\n custom_ar.def(\"allocate_shared_buffer_and_handle\",\n &allocate_shared_buffer_and_handle);\n custom_ar.def(\"open_mem_handle(Tensor mem_handle) -> int\", &open_mem_handle);\n custom_ar.impl(\"open_mem_handle\", torch::kCPU, &open_mem_handle);\n\n custom_ar.def(\"free_shared_buffer\", &free_shared_buffer);\n#ifdef USE_ROCM\n // Quick Reduce all-reduce kernels\n custom_ar.def(\n \"qr_all_reduce(int fa, Tensor inp, Tensor out, int quant_level, bool \"\n \"cast_bf2half) -> ()\");\n custom_ar.impl(\"qr_all_reduce\", torch::kCUDA, &qr_all_reduce);\n\n custom_ar.def(\"init_custom_qr\", &init_custom_qr);\n custom_ar.def(\"qr_destroy\", &qr_destroy);\n\n custom_ar.def(\"qr_get_handle\", &qr_get_handle);\n\n custom_ar.def(\"qr_open_handles(int _fa, Tensor[](b!) handles) -> ()\");\n custom_ar.impl(\"qr_open_handles\", torch::kCPU, &qr_open_handles);\n\n // Max input size in bytes\n custom_ar.def(\"qr_max_size\", &qr_max_size);\n#endif\n}\n\nREGISTER_EXTENSION(TORCH_EXTENSION_NAME)\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## Purpose\n\nFused layout transform with per token group quant to get performance\n\nNamely, pack scales into a uint32 earlier and remove an additional kernel call\n\n## Test\n\n`vllm serve deepseek-ai/DeepSeek-V3.1 -tp 8 --enable-expert-parallel --port 9256 --enforce_eager`\n\n### Acc\n\n`lm_eval --model local-completions --model_args \"base_url=http://127.0.0.1:9256/v1/completions,model=deepseek-ai/DeepSeek-V3.1,num_concurrent=1024\" --tasks gsm8k`\n\n```bash\n|Tasks|Version| Filter |n-shot| Metric | |Value | |Stderr|\n|-----|------:|----------------|-----:|-----------|---|-----:|---|-----:|\n|gsm8k| 3|flexible-extract| 5|exact_match|↑ |0.9568|± |0.0056|\n| | |strict-match | 5|exact_match|↑ |0.9568|± |0.0056|\n```\n\n### Perf\n\n`vllm bench serve --model deepseek-ai/DeepSeek-V3.1 --dataset-name random --host 127.0.0.1 --port 9256 --random-input-len 2 --random-output-len 256 --request-rate inf --num-prompts 1024`\n\n```bash\nNow\n============ Serving Benchmark Result ============\nSuccessful requests: 1024 \nFailed requests: 0 \nBenchmark duration (s): 27.94 \nTotal input tokens: 3072 \nTotal generated tokens: 262144 \nRequest throughput (req/s): 36.65 \nOutput token throughput (tok/s): 9382.68 \nPeak output token throughput (tok/s): 10240.00 \nPeak concurrent requests: 1024.00 \nTotal Token throughput (tok/s): 9492.63 \n---------------Time to First Token----------------\nMean TTFT (ms): 1013.22 \nMedian TTFT (ms): 982.19 \nP99 TTFT (ms): 1157.11 \n-----Time per Output Token (excl. 1st token)------\nMean TPOT (ms): 105.02 \nMedian TPOT (ms): 105.08 \nP99 TPOT (ms): 105.26 \n---------------Inter-token Latency----------------\nMean ITL (ms): 105.02 \nMedian ITL (ms): 104.57 \nP99 ITL (ms): 131.10 \n==================================================\n\nMain\n============ Serving Benchmark Result ============\nSuccessful requests: 1024 \nFailed requests: 0 \nBenchmark duration (s): 29.15 \nTotal input tokens: 3072 \nTotal generated tokens: 262144 \nRequest throughput (req/s): 35.13 \nOutput token throughput (tok/s): 8994.31 \nPeak output token throughput (tok/s): 10132.00 \nPeak concurrent requests: 1024.00 \nTotal Token throughput (tok/s): 9099.71 \n---------------Time to First Token----------------\nMean TTFT (ms): 1121.89 \nMedian TTFT (ms): 1144.56 \nP99 TTFT (ms): 1241.25 \n-----Time per Output Token (excl. 1st token)------\nMean TPOT (ms): 109.30 \nMedian TPOT (ms): 109.29 \nP99 TPOT (ms): 109.40 \n---------------Inter-token Latency----------------\nMean ITL (ms): 109.30 \nMedian ITL (ms): 108.89 \nP99 ITL (ms): 125.29 \n==================================================\n```\n\n\n"},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":392,"cells":{"repo":{"kind":"string","value":"vllm"},"commit":{"kind":"string","value":"541a2ef892720489f770569417bc1bc4436dbb21"},"date":{"kind":"string","value":"2025-12-07T07:31:14-05:00"},"pr_number":{"kind":"number","value":29546,"string":"29,546"},"pr_url":{"kind":"string","value":"https://github.com/vllm-project/vllm/pull/29546"},"title":{"kind":"string","value":"[Perf] Deepgemm fused layout kernel for activations, 4.3% throughput improvement, 10.7% TTFT improvement. (#29546)"},"message":{"kind":"string","value":"[Perf] Deepgemm fused layout kernel for activations, 4.3% throughput improvement, 10.7% TTFT improvement. (#29546)\n\nSigned-off-by: yewentao256 <zhyanwentao@126.com>"},"path":{"kind":"string","value":"vllm/model_executor/layers/quantization/utils/fp8_utils.py"},"language":{"kind":"string","value":"triton"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"# SPDX-License-Identifier: Apache-2.0\n# SPDX-FileCopyrightText: Copyright contributors to the vLLM project\n\n# Adapted from https://github.com/sgl-project/sglang/pull/2575\nimport functools\nimport json\nimport os\nfrom collections.abc import Callable, Sequence\nfrom typing import Any\n\nimport torch\n\nimport vllm.envs as envs\nfrom vllm import _custom_ops as ops\nfrom vllm._aiter_ops import rocm_aiter_ops\nfrom vllm.logger import init_logger\nfrom vllm.model_executor.layers.quantization.input_quant_fp8 import QuantFP8\nfrom vllm.model_executor.layers.quantization.utils.quant_utils import (\n GroupShape,\n group_broadcast,\n)\nfrom vllm.model_executor.layers.quantization.utils.w8a8_utils import (\n CUTLASS_BLOCK_FP8_SUPPORTED,\n)\nfrom vllm.model_executor.parameter import (\n BlockQuantScaleParameter,\n ChannelQuantScaleParameter,\n PerTensorScaleParameter,\n)\nfrom vllm.platforms import current_platform\nfrom vllm.triton_utils import tl, triton\nfrom vllm.utils.deep_gemm import (\n fp8_gemm_nt,\n is_deep_gemm_e8m0_used,\n is_deep_gemm_supported,\n should_use_deepgemm_for_fp8_linear,\n transform_sf_into_required_layout,\n)\nfrom vllm.utils.torch_utils import direct_register_custom_op\n\nlogger = init_logger(__name__)\n\n\ndef is_fp8(x: torch.dtype | torch.Tensor) -> bool:\n if isinstance(x, torch.Tensor):\n x = x.dtype\n return x == torch.float8_e4m3fn or x == torch.float8_e4m3fnuz\n\n\n# We need to pass in the is_hopper flag as argument because the function\n# current_platform.is_device_capability() is not supported by Torch compiler.\ndef cutlass_scaled_mm(\n A: torch.Tensor,\n B: torch.Tensor,\n As: torch.Tensor,\n Bs: torch.Tensor,\n block_size: list[int],\n output_dtype: torch.dtype = torch.float16,\n) -> torch.Tensor:\n return ops.cutlass_scaled_mm(\n A,\n B.T,\n out_dtype=output_dtype,\n scale_a=As,\n scale_b=Bs.T,\n )\n\n\n# TODO we should be able to change the type of block_size to GroupShape\n# after we resolve GroupShape compilation issue\n# https://github.com/vllm-project/vllm/issues/25270\ndef _w8a8_triton_block_scaled_mm_func(\n qx: torch.Tensor,\n weight: torch.Tensor,\n x_scale: torch.Tensor,\n weight_scale: torch.Tensor,\n block_size: list[int],\n output_dtype: torch.dtype,\n) -> torch.Tensor:\n return w8a8_triton_block_scaled_mm(\n qx, weight, x_scale, weight_scale, block_size, output_dtype\n )\n\n\ndef _w8a8_triton_block_scaled_mm_fake(\n qx: torch.Tensor,\n weight: torch.Tensor,\n x_scale: torch.Tensor,\n weight_scale: torch.Tensor,\n block_size: list[int],\n output_dtype: torch.dtype,\n) -> torch.Tensor:\n return torch.empty(\n (qx.size(0), weight.size(0)), dtype=output_dtype, device=qx.device\n )\n\n\ndirect_register_custom_op(\n \"w8a8_triton_block_scaled_mm_func\",\n _w8a8_triton_block_scaled_mm_func,\n fake_impl=_w8a8_triton_block_scaled_mm_fake,\n)\n\n\ndef _padded_cutlass(\n qx: torch.Tensor,\n weight: torch.Tensor,\n x_scale: torch.Tensor,\n weight_scale: torch.Tensor,\n block_size: list[int],\n output_dtype: torch.dtype,\n) -> torch.Tensor:\n pad_multiple = 4\n dim = qx.shape[0]\n padded = (\n dim if dim % pad_multiple == 0 else dim + pad_multiple - (dim % pad_multiple)\n )\n\n has_pad = padded > dim\n\n if has_pad:\n padded_shape = [padded, *qx.shape[1:]]\n padded_qx = torch.zeros(padded_shape, device=qx.device, dtype=qx.dtype)\n padded_qx[0 : qx.shape[0], ...].copy_(qx)\n\n padded_x_scale_shape = [*x_scale.shape[1:], padded]\n padded_x_scale = torch.ones(\n padded_x_scale_shape, device=x_scale.device, dtype=x_scale.dtype\n ).permute(-1, -2)\n padded_x_scale[0 : x_scale.shape[0], ...].copy_(x_scale)\n\n output = cutlass_scaled_mm(\n padded_qx, weight, padded_x_scale, weight_scale, block_size, output_dtype\n )\n return output[0 : qx.shape[0], ...]\n else:\n return cutlass_scaled_mm(\n qx, weight, x_scale, weight_scale, block_size, output_dtype\n )\n\n\ndef _padded_cutlass_fake(\n qx: torch.Tensor,\n weight: torch.Tensor,\n x_scale: torch.Tensor,\n weight_scale: torch.Tensor,\n block_size: list[int],\n output_dtype: torch.dtype,\n) -> torch.Tensor:\n return torch.empty(\n (qx.size(0), weight.size(0)), dtype=output_dtype, device=qx.device\n )\n\n\ndirect_register_custom_op(\n \"padded_cutlass\",\n _padded_cutlass,\n fake_impl=_padded_cutlass_fake,\n)\n\n\ndef _fp8_gemm_nt_op(\n q_input: torch.Tensor,\n input_scale: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n output: torch.Tensor,\n use_deep_gemm_e8m0: bool,\n) -> None:\n fp8_gemm_nt(\n (q_input, input_scale),\n (weight, weight_scale),\n output,\n is_deep_gemm_e8m0_used=use_deep_gemm_e8m0,\n )\n\n\ndef _fp8_gemm_nt_op_fake(\n q_input: torch.Tensor,\n input_scale: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n output: torch.Tensor,\n use_deep_gemm_e8m0: bool,\n) -> None:\n return None\n\n\ndirect_register_custom_op(\n \"fp8_gemm_nt_op\",\n _fp8_gemm_nt_op,\n mutates_args=[\"output\"],\n fake_impl=_fp8_gemm_nt_op_fake,\n)\n\n\n# TODO fix ROCm->Triton custom path:\n# https://github.com/vllm-project/vllm/issues/14397\nclass W8A8BlockFp8LinearOp:\n \"\"\"\n This class executes a Blocked FP8 linear layer using cutlass if supported\n and torch.scaled_mm otherwise.\n \"\"\"\n\n def __init__(\n self,\n weight_group_shape: GroupShape,\n act_quant_group_shape: GroupShape,\n cutlass_block_fp8_supported: bool = CUTLASS_BLOCK_FP8_SUPPORTED,\n use_aiter_and_is_supported: bool = False,\n ):\n self.weight_group_shape = weight_group_shape\n self.act_quant_group_shape = act_quant_group_shape\n self.is_deep_gemm_supported = is_deep_gemm_supported()\n self.is_hopper = current_platform.is_device_capability(90)\n self.use_deep_gemm_e8m0 = is_deep_gemm_e8m0_used()\n\n # Get the correct blockscale mul and input quant operations.\n # We can't use _dispatch_w8a8_blockscale_op to figure out if we want\n # to use deepgemm because we don't know the shape of weights (and\n # whether deepgemm supports it) at the init time.\n self.w8a8_blockscale_op, self.input_quant_op = (\n self._dispatch_w8a8_blockscale_op(\n cutlass_block_fp8_supported, use_aiter_and_is_supported\n )\n )\n self.deepgemm_input_quant_op = (\n QuantFP8(\n False,\n self.act_quant_group_shape,\n column_major_scales=True,\n use_ue8m0=self.use_deep_gemm_e8m0,\n )\n if self.is_deep_gemm_supported\n else None\n )\n\n def apply(\n self,\n input: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n input_scale: torch.Tensor | None = None,\n bias: torch.Tensor | None = None,\n ) -> torch.Tensor:\n assert input_scale is None\n # View input as 2D matrix for fp8 methods\n input_2d = input.view(-1, input.shape[-1])\n output_shape = [*input.shape[:-1], weight.shape[0]]\n output_dtype = input.dtype\n\n if should_use_deepgemm_for_fp8_linear(\n output_dtype, weight, self.is_deep_gemm_supported\n ):\n output = self._run_deepgemm(input_2d, weight, weight_scale)\n else:\n output = self.w8a8_blockscale_op(\n input_2d, weight, weight_scale, input_scale\n )\n\n if bias is not None:\n output = output + bias\n return output.to(dtype=input.dtype).view(*output_shape)\n\n def _run_deepgemm(\n self,\n input_2d: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n ) -> torch.Tensor:\n assert self.deepgemm_input_quant_op is not None\n q_input, input_scale = self.deepgemm_input_quant_op(input_2d)\n output = torch.empty(\n (q_input.shape[0], weight.shape[0]),\n dtype=torch.bfloat16,\n device=q_input.device,\n )\n torch.ops.vllm.fp8_gemm_nt_op(\n q_input, input_scale, weight, weight_scale, output, self.use_deep_gemm_e8m0\n )\n return output\n\n def _run_cutlass(\n self,\n input_2d: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n input_scale: torch.Tensor | None = None,\n ) -> torch.Tensor:\n assert input_scale is None\n assert self.input_quant_op is not None\n q_input, input_scale = self.input_quant_op(input_2d)\n if self.is_hopper:\n return torch.ops.vllm.padded_cutlass(\n q_input,\n weight,\n input_scale,\n weight_scale,\n list(self.weight_group_shape),\n input_2d.dtype,\n )\n else:\n return cutlass_scaled_mm(\n q_input,\n weight,\n input_scale,\n weight_scale,\n list(self.weight_group_shape),\n input_2d.dtype,\n )\n\n def _run_aiter(\n self,\n input_2d: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n input_scale: torch.Tensor | None = None,\n ) -> torch.Tensor:\n assert self.act_quant_group_shape == GroupShape(1, 128)\n\n n, k = weight.shape\n\n use_triton = (\n not current_platform.is_fp8_fnuz()\n and rocm_aiter_ops.is_triton_gemm_w8a8_tuned(n, k)\n )\n\n if use_triton:\n gemm_a8w8_blockscale_op = rocm_aiter_ops.triton_gemm_a8w8_blockscale\n else:\n gemm_a8w8_blockscale_op = rocm_aiter_ops.gemm_a8w8_blockscale\n\n if input_scale is not None:\n q_input = input_2d\n # MI350 case uses triton kernel\n elif use_triton:\n q_input, input_scale = per_token_group_quant_fp8(\n input_2d,\n self.act_quant_group_shape.col,\n column_major_scales=False,\n use_ue8m0=False,\n )\n # MI300 uses tuned AITER ASM/C++ kernel\n else:\n q_input, input_scale = rocm_aiter_ops.group_fp8_quant(input_2d)\n\n return gemm_a8w8_blockscale_op(\n q_input,\n weight,\n input_scale,\n weight_scale,\n list(self.weight_group_shape),\n output_dtype=input_2d.dtype,\n )\n\n def _run_triton(\n self,\n input_2d: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n input_scale: torch.Tensor | None = None,\n ) -> torch.Tensor:\n assert input_scale is None\n assert self.input_quant_op is not None\n q_input, input_scale = self.input_quant_op(input_2d)\n return torch.ops.vllm.w8a8_triton_block_scaled_mm_func(\n q_input,\n weight,\n input_scale,\n weight_scale,\n list(self.weight_group_shape),\n input_2d.dtype,\n )\n\n def _dispatch_w8a8_blockscale_op(\n self,\n use_cutlass: bool,\n use_aiter_and_is_supported: bool,\n ) -> tuple[\n Callable[\n [\n torch.Tensor,\n torch.Tensor,\n torch.Tensor,\n torch.Tensor | None,\n ],\n torch.Tensor,\n ],\n QuantFP8 | None,\n ]:\n if use_cutlass:\n return self._run_cutlass, (\n QuantFP8(\n False,\n self.act_quant_group_shape,\n column_major_scales=True,\n use_ue8m0=False,\n )\n )\n if use_aiter_and_is_supported:\n return self._run_aiter, None\n return self._run_triton, (\n QuantFP8(\n False,\n self.act_quant_group_shape,\n column_major_scales=False,\n use_ue8m0=False,\n )\n )\n\n\ndef input_to_float8(\n x: torch.Tensor, dtype: torch.dtype | None = None\n) -> tuple[torch.Tensor, torch.Tensor]:\n \"\"\"This function quantizes input values to float8 values \"\n \"with tensor-wise quantization.\"\"\"\n dtype = current_platform.fp8_dtype() if dtype is None else dtype\n finfo = torch.finfo(dtype)\n min_val, max_val = x.aminmax()\n amax = torch.maximum(min_val.abs(), max_val.abs()).clamp(min=1e-12)\n scale = finfo.max / amax\n x_scl_sat = (x * scale).clamp(min=finfo.min, max=finfo.max)\n return x_scl_sat.to(dtype).contiguous(), scale.float().reciprocal()\n\n\ndef block_quant_to_tensor_quant(\n x_q_block: torch.Tensor,\n x_s: torch.Tensor,\n) -> tuple[torch.Tensor, torch.Tensor]:\n \"\"\"This function converts block-wise quantization to tensor-wise\n quantization. The inputs are block-wise quantization tensor `x_q_block`,\n block-wise quantization scale and the block size.\n The outputs are tensor-wise quantization tensor and tensor-wise\n quantization scale. Note only float8 is supported for now.\n \"\"\"\n x_dq_block = group_broadcast(x_q_block, x_s)\n x_q_tensor, scale = input_to_float8(x_dq_block, dtype=x_q_block.dtype)\n return x_q_tensor, scale\n\n\n@triton.jit\ndef _per_token_group_quant_fp8(\n # Pointers to inputs and output\n y_ptr,\n y_q_ptr,\n y_s_ptr,\n group_size,\n # Num columns of y\n y_num_columns,\n y_row_stride,\n # Avoid to divide zero\n eps,\n # Information for float8\n fp8_min,\n fp8_max,\n use_ue8m0: tl.constexpr,\n # Meta-parameters\n BLOCK: tl.constexpr,\n):\n \"\"\"A Triton-accelerated function to perform per-token-group\n quantization on a tensor.\n This function converts the tensor values into float8 values.\n \"\"\"\n groups_per_row = y_num_columns // group_size\n\n # Map the program id to the row of X and Y it should compute.\n g_id = tl.program_id(0)\n row = g_id // groups_per_row\n row_g_id = g_id % groups_per_row\n\n # Ensure offset calculations use int64 to prevent overflow\n y_ptr_offset = (row.to(tl.int64) * y_row_stride) + (\n row_g_id.to(tl.int64) * group_size\n )\n y_ptr += y_ptr_offset\n\n y_q_ptr_offset = g_id.to(tl.int64) * group_size\n y_q_ptr += y_q_ptr_offset\n y_s_ptr += g_id\n\n cols = tl.arange(0, BLOCK) # N <= BLOCK\n mask = cols < group_size\n\n y = tl.load(y_ptr + cols, mask=mask, other=0.0).to(tl.float32)\n # Quant\n _absmax = tl.maximum(tl.max(tl.abs(y)), eps)\n scale_raw = _absmax / fp8_max\n y_s = tl.math.exp2(tl.ceil(tl.log2(scale_raw))) if use_ue8m0 else scale_raw\n y_q = tl.clamp(y / y_s, fp8_min, fp8_max).to(y_q_ptr.dtype.element_ty)\n\n tl.store(y_q_ptr + cols, y_q, mask=mask)\n tl.store(y_s_ptr, y_s)\n\n\n@triton.jit\ndef _silu_mul_per_token_group_quant_fp8_colmajor(\n y_ptr, # [M, N]\n y_q_ptr, # [M, N // 2]\n y_s_ptr, # [M, (N // 2) // GROUP_SIZE]\n M, # num tokens\n N, # intermediate size\n # Stride\n y_s_col_stride: tl.int64,\n # Information for float8\n eps,\n fp8_min,\n fp8_max,\n use_ue8m0: tl.constexpr,\n # Meta-parameters\n GROUP_SIZE: tl.constexpr,\n BLOCK_M: tl.constexpr,\n BLOCK_N: tl.constexpr,\n):\n # TODO(varun) : Add expert_ids so we may early-exit no-op thread blocks.\n \"\"\"\n Each thread block (BLOCK_N) computes [BLOCK_M, GROUP_SIZE] act-mul outputs. Then\n the thread block quantizes the [BLOCK_M, GROUP_SIZE] block of values and fills\n the outputs tensors at the right positions.\n \"\"\"\n\n pid_m = tl.program_id(0)\n pid_n = tl.program_id(1)\n N_2 = N // 2\n\n m_offset = pid_m * BLOCK_M\n n_offset = pid_n * BLOCK_N\n if m_offset >= M:\n return\n\n offs_n = tl.arange(0, BLOCK_N).to(tl.int64)\n offs_m = tl.arange(0, BLOCK_M).to(tl.int64)\n\n base_y_ptr = y_ptr + m_offset * N + n_offset\n\n act_in_ptrs = base_y_ptr + offs_m[:, None] * N + offs_n[None, :]\n\n act_in = tl.load(act_in_ptrs)\n mul_in = tl.load(act_in_ptrs + N_2)\n\n # silu & mul\n act_in = act_in.to(tl.float32)\n one_f32 = tl.cast(1, tl.float32)\n silu_out = (act_in / (one_f32 + tl.exp(-act_in))).to(y_ptr.dtype.element_ty)\n y = (silu_out * mul_in).to(tl.float32)\n\n # quant\n _absmax = tl.maximum(tl.max(tl.abs(y), axis=1), eps)\n scale_raw = _absmax / fp8_max\n y_s = tl.math.exp2(tl.ceil(tl.log2(scale_raw))) if use_ue8m0 else scale_raw\n y_s = tl.reshape(y_s, (BLOCK_M, 1))\n y_q = tl.clamp(y / y_s, fp8_min, fp8_max).to(y_q_ptr.dtype.element_ty)\n\n # store y_q\n base_y_q_ptr = y_q_ptr + m_offset * N_2 + n_offset\n y_q_ptrs = base_y_q_ptr + offs_m[:, None] * N_2 + offs_n[None, :]\n tl.store(y_q_ptrs, y_q)\n\n # store y_s\n group_id = n_offset // GROUP_SIZE\n base_y_s_ptr = y_s_ptr + group_id * y_s_col_stride + m_offset\n y_s_ptrs = base_y_s_ptr + offs_m\n y_s = tl.reshape(y_s, (BLOCK_M,))\n tl.store(y_s_ptrs, y_s)\n\n\ndef silu_mul_per_token_group_quant_fp8_colmajor(\n input: torch.Tensor, # [M, N]\n output: torch.Tensor | None = None, # [M, N // 2]\n use_ue8m0: bool | None = None,\n eps: float = 1e-10,\n):\n \"\"\"\n silu+mul + block-fp8 quant with group size 128.\n \"\"\"\n GROUP_SIZE = 128\n assert input.ndim == 2\n if output is not None:\n assert output.ndim == 2\n assert input.size(0) % GROUP_SIZE == 0\n assert input.size(1) % (GROUP_SIZE * 2) == 0\n\n if use_ue8m0 is None:\n use_ue8m0 = is_deep_gemm_e8m0_used()\n\n M, N = input.size()\n N_2 = N // 2\n\n if output is None:\n output = torch.empty((M, N_2), dtype=torch.float8_e4m3fn, device=input.device)\n\n output_scales = torch.empty(\n ((N_2 // GROUP_SIZE), M), dtype=torch.float32, device=input.device\n ).transpose(0, 1)\n\n BLOCK_M = 8\n BLOCK_N = GROUP_SIZE\n assert M % BLOCK_M == 0\n assert N_2 % BLOCK_N == 0\n\n finfo = torch.finfo(torch.float8_e4m3fn)\n fp8_min = finfo.min\n fp8_max = finfo.max\n\n # Force even division so we can avoid edgecases within the kernel.\n assert M % BLOCK_M == 0\n assert N_2 % BLOCK_N == 0\n grid = (M // BLOCK_M, N_2 // BLOCK_N)\n\n _silu_mul_per_token_group_quant_fp8_colmajor[grid](\n input,\n output,\n output_scales,\n M,\n N,\n output_scales.stride(-1),\n eps,\n fp8_min,\n fp8_max,\n use_ue8m0,\n GROUP_SIZE,\n BLOCK_M,\n BLOCK_N,\n )\n\n return output, output_scales\n\n\n@triton.jit\ndef _per_token_group_quant_fp8_colmajor(\n # Pointers to inputs and output\n y_ptr,\n y_q_ptr,\n y_s_ptr,\n group_size,\n # Num columns of y\n y_num_columns,\n y_row_stride,\n # Stride from one column to the next of y_s\n y_s_col_stride,\n # Avoid to divide zero\n eps,\n # Information for float8\n fp8_min,\n fp8_max,\n use_ue8m0: tl.constexpr,\n # Meta-parameters\n BLOCK: tl.constexpr,\n):\n \"\"\"A Triton-accelerated function to perform per-token-group\n quantization on a tensor.\n This function converts the tensor values into float8 values.\n \"\"\"\n groups_per_row = y_num_columns // group_size\n\n # Map the program id to the row of X and Y it should compute.\n g_id = tl.program_id(0)\n row = g_id // groups_per_row\n row_g_id = g_id % groups_per_row\n\n # Ensure offset calculations use int64 to prevent overflow\n y_ptr_offset = (row.to(tl.int64) * y_row_stride) + (\n row_g_id.to(tl.int64) * group_size\n )\n y_ptr += y_ptr_offset\n\n y_q_ptr_offset = g_id.to(tl.int64) * group_size\n y_q_ptr += y_q_ptr_offset\n\n # Convert g_id the flattened block coordinate to 2D so we can index\n # into the output y_scales matrix\n blocks_per_row = y_num_columns // group_size\n scale_col = g_id % blocks_per_row\n scale_row = g_id // blocks_per_row\n # Ensure offset calculation uses int64 for y_s_ptr\n y_s_ptr_offset = (scale_col.to(tl.int64) * y_s_col_stride) + scale_row.to(tl.int64)\n y_s_ptr += y_s_ptr_offset\n\n cols = tl.arange(0, BLOCK) # group_size <= BLOCK\n mask = cols < group_size\n\n y = tl.load(y_ptr + cols, mask=mask, other=0.0).to(tl.float32)\n # Quant\n _absmax = tl.maximum(tl.max(tl.abs(y)), eps)\n scale_raw = _absmax / fp8_max\n y_s = tl.math.exp2(tl.ceil(tl.log2(scale_raw))) if use_ue8m0 else scale_raw\n y_q = tl.clamp(y / y_s, fp8_min, fp8_max).to(y_q_ptr.dtype.element_ty)\n\n tl.store(y_q_ptr + cols, y_q, mask=mask)\n tl.store(y_s_ptr, y_s)\n\n\ndef per_token_group_quant_fp8(\n x: torch.Tensor,\n group_size: int,\n eps: float = 1e-10,\n dtype: torch.dtype | None = None,\n column_major_scales: bool = False,\n out_q: torch.Tensor | None = None,\n use_ue8m0: bool | None = None,\n) -> tuple[torch.Tensor, torch.Tensor]:\n \"\"\"Function to perform per-token-group quantization on an input tensor `x`.\n It converts the tensor values into signed float8 values and returns the\n quantized tensor along with the scaling factor used for quantization.\n Args:\n x: The input tensor with ndim >= 2.\n group_size: The group size used for quantization.\n eps: The minimum to avoid dividing zero.\n dtype: The dype of output tensor. Note that only `torch.float8_e4m3fn`\n is supported for now.\n column_major_scales: Outputs scales in column major.\n out_q: Optional output tensor. If not provided, function will create.\n Returns:\n tuple[torch.Tensor, torch.Tensor]: The quantized tensor and the\n scaling factor.\n \"\"\"\n if use_ue8m0 is None:\n use_ue8m0 = is_deep_gemm_e8m0_used()\n dtype = current_platform.fp8_dtype() if dtype is None else dtype\n assert x.shape[-1] % group_size == 0, (\n f\"the last dimension of `x` {x.shape[-1]} must be divisible \"\n f\"by `group_size` {group_size}\"\n )\n assert x.stride(-1) == 1, \"`x` groups must be contiguous\"\n\n finfo = torch.finfo(dtype)\n fp8_min = finfo.min\n fp8_max = finfo.max\n\n assert out_q is None or out_q.shape == x.shape\n x_q = out_q\n if x_q is None:\n x_q = torch.empty_like(x, device=x.device, dtype=dtype)\n\n # Allocate the scale tensor in either row- or column-major format.\n if column_major_scales:\n shape = (x.shape[-1] // group_size,) + x.shape[:-1]\n x_s = torch.empty(shape, device=x.device, dtype=torch.float32).permute(-1, -2)\n else:\n shape = x.shape[:-1] + (x.shape[-1] // group_size,)\n x_s = torch.empty(shape, device=x.device, dtype=torch.float32)\n\n # prefer CUDA kernel if available\n # TODO(bnell): this causes some fp8 moe test to fail.\n if current_platform.is_cuda() and x.is_contiguous():\n torch.ops._C.per_token_group_fp8_quant(\n x, x_q, x_s, group_size, eps, fp8_min, fp8_max, use_ue8m0\n )\n return x_q, x_s\n\n # TRITON FALLBACK\n M = x.numel() // group_size\n N = group_size\n BLOCK = triton.next_power_of_2(N)\n # heuristics for number of warps\n num_warps = min(max(BLOCK // 256, 1), 8)\n num_stages = 1\n if column_major_scales:\n _per_token_group_quant_fp8_colmajor[(M,)](\n x,\n x_q,\n x_s,\n group_size,\n x.shape[1],\n x.stride(0),\n x_s.stride(1),\n eps,\n fp8_min=fp8_min,\n fp8_max=fp8_max,\n use_ue8m0=use_ue8m0,\n BLOCK=BLOCK,\n num_warps=num_warps,\n num_stages=num_stages,\n )\n else:\n _per_token_group_quant_fp8[(M,)](\n x,\n x_q,\n x_s,\n group_size,\n x.shape[1],\n x.stride(0),\n eps,\n fp8_min=fp8_min,\n fp8_max=fp8_max,\n use_ue8m0=use_ue8m0,\n BLOCK=BLOCK,\n num_warps=num_warps,\n num_stages=num_stages,\n )\n\n return x_q, x_s\n\n\n@triton.jit\ndef _w8a8_triton_block_scaled_mm(\n # Pointers to inputs and output\n A,\n B,\n C,\n As,\n Bs,\n # Shape for matmul\n M,\n N,\n K,\n # Block size for block-wise quantization\n group_n,\n group_k,\n # Stride for inputs and output\n stride_am,\n stride_ak,\n stride_bk,\n stride_bn,\n stride_cm,\n stride_cn,\n stride_As_m,\n stride_As_k,\n stride_Bs_k,\n stride_Bs_n,\n # Meta-parameters\n BLOCK_SIZE_M: tl.constexpr,\n BLOCK_SIZE_N: tl.constexpr,\n BLOCK_SIZE_K: tl.constexpr,\n GROUP_SIZE_M: tl.constexpr,\n):\n \"\"\"Triton-accelerated function used to perform linear operations (dot\n product) on input tensors `A` and `B` with block-wise quantization, and\n store the result in output tensor `C`.\n \"\"\"\n\n pid = tl.program_id(axis=0)\n num_pid_m = tl.cdiv(M, BLOCK_SIZE_M)\n num_pid_n = tl.cdiv(N, BLOCK_SIZE_N)\n num_pid_in_group = GROUP_SIZE_M * num_pid_n\n group_id = pid // num_pid_in_group\n first_pid_m = group_id * GROUP_SIZE_M\n group_size_m = min(num_pid_m - first_pid_m, GROUP_SIZE_M)\n pid_m = first_pid_m + (pid % group_size_m)\n pid_n = (pid % num_pid_in_group) // group_size_m\n\n offs_am = (pid_m * BLOCK_SIZE_M + tl.arange(0, BLOCK_SIZE_M)) % M\n offs_bn = (pid_n * BLOCK_SIZE_N + tl.arange(0, BLOCK_SIZE_N)) % N\n offs_k = tl.arange(0, BLOCK_SIZE_K)\n a_ptrs = A + (offs_am[:, None] * stride_am + offs_k[None, :] * stride_ak)\n b_ptrs = B + (offs_k[:, None] * stride_bk + offs_bn[None, :] * stride_bn)\n\n As_ptrs = As + offs_am * stride_As_m\n offs_bsn = offs_bn // group_n\n Bs_ptrs = Bs + offs_bsn * stride_Bs_n\n\n accumulator = tl.zeros((BLOCK_SIZE_M, BLOCK_SIZE_N), dtype=tl.float32)\n for k in range(0, tl.cdiv(K, BLOCK_SIZE_K)):\n a = tl.load(a_ptrs, mask=offs_k[None, :] < K - k * BLOCK_SIZE_K, other=0.0)\n b = tl.load(b_ptrs, mask=offs_k[:, None] < K - k * BLOCK_SIZE_K, other=0.0)\n\n k_start = k * BLOCK_SIZE_K\n offs_ks = k_start // group_k\n a_s = tl.load(As_ptrs + offs_ks * stride_As_k)\n b_s = tl.load(Bs_ptrs + offs_ks * stride_Bs_k)\n\n accumulator += tl.dot(a, b) * a_s[:, None] * b_s[None, :]\n a_ptrs += BLOCK_SIZE_K * stride_ak\n b_ptrs += BLOCK_SIZE_K * stride_bk\n\n if C.dtype.element_ty == tl.bfloat16:\n c = accumulator.to(tl.bfloat16)\n elif C.dtype.element_ty == tl.float16:\n c = accumulator.to(tl.float16)\n else:\n c = accumulator.to(tl.float32)\n\n offs_cm = pid_m * BLOCK_SIZE_M + tl.arange(0, BLOCK_SIZE_M)\n offs_cn = pid_n * BLOCK_SIZE_N + tl.arange(0, BLOCK_SIZE_N)\n c_ptrs = C + stride_cm * offs_cm[:, None] + stride_cn * offs_cn[None, :]\n c_mask = (offs_cm[:, None] < M) & (offs_cn[None, :] < N)\n tl.store(c_ptrs, c, mask=c_mask)\n\n\n@functools.lru_cache\ndef get_w8a8_block_fp8_configs(\n N: int, K: int, block_n: int, block_k: int\n) -> dict[int, Any] | None:\n \"\"\"\n Return optimized configurations for the w8a8 block fp8 kernel.\n The return value will be a dictionary that maps an irregular grid of\n batch sizes to configurations of the w8a8 block fp8 kernel. To evaluate the\n kernel on a given batch size bs, the closest batch size in the grid should\n be picked and the associated configuration chosen to invoke the kernel.\n \"\"\"\n\n # First look up if an optimized configuration is available in the configs\n # directory\n device_name = current_platform.get_device_name().replace(\" \", \"_\")\n json_file_name = f\"N={N},K={K},device_name={device_name},dtype=fp8_w8a8,block_shape=[{block_n},{block_k}].json\" # noqa: E501\n\n config_file_path = os.path.join(\n os.path.dirname(os.path.realpath(__file__)), \"configs\", json_file_name\n )\n if os.path.exists(config_file_path):\n with open(config_file_path) as f:\n logger.info(\n \"Using configuration from %s for W8A8 Block FP8 kernel.\",\n config_file_path,\n )\n # If a configuration has been found, return it\n return {int(key): val for key, val in json.load(f).items()}\n\n # If no optimized configuration is available, we will use the default\n # configuration\n logger.warning(\n \"Using default W8A8 Block FP8 kernel config. Performance might \"\n \"be sub-optimal! Config file not found at %s\",\n config_file_path,\n )\n return None\n\n\ndef w8a8_triton_block_scaled_mm(\n A: torch.Tensor,\n B: torch.Tensor,\n As: torch.Tensor,\n Bs: torch.Tensor,\n block_size: list[int],\n output_dtype: torch.dtype = torch.float16,\n) -> torch.Tensor:\n \"\"\"This function performs matrix multiplication with block-wise\n quantization.\n It takes two input tensors `A` and `B` with scales `As` and `Bs`.\n The output is returned in the specified `output_dtype`.\n Args:\n A: The input tensor, e.g., activation.\n B: The input tensor, e.g., weight.\n As: The per-token-group quantization scale for `A`.\n Bs: The per-block quantization scale for `B`.\n block_size: The block size for per-block quantization. It should\n be 2-dim, e.g., [128, 128].\n output_dytpe: The dtype of the returned tensor.\n Returns:\n torch.Tensor: The result of matmul.\n \"\"\"\n assert len(block_size) == 2\n block_n, block_k = block_size[0], block_size[1]\n\n assert A.shape[-1] == B.shape[-1]\n assert A.shape[:-1] == As.shape[:-1] and A.is_contiguous()\n assert triton.cdiv(A.shape[-1], block_k) == As.shape[-1]\n M = A.numel() // A.shape[-1]\n\n assert B.ndim == 2 and Bs.ndim == 2\n N, K = B.shape\n assert triton.cdiv(N, block_n) == Bs.shape[0]\n assert triton.cdiv(K, block_k) == Bs.shape[1]\n\n C_shape = A.shape[:-1] + (N,)\n C = A.new_empty(C_shape, dtype=output_dtype)\n\n configs = get_w8a8_block_fp8_configs(N, K, block_size[0], block_size[1])\n if configs:\n # Get the optimal config if there is one\n config = configs[min(configs.keys(), key=lambda x: abs(x - M))]\n else:\n # Default config\n # Block-wise quant: BLOCK_SIZE_N must be divisible by block_size[0]\n # BLOCK_SIZE_K must be divisible by block_size[1]\n config = {\n \"BLOCK_SIZE_M\": 64,\n \"BLOCK_SIZE_N\": block_size[0],\n \"BLOCK_SIZE_K\": block_size[1],\n \"GROUP_SIZE_M\": 32,\n \"num_warps\": 4,\n \"num_stages\": 2,\n }\n\n def grid(META):\n return (\n triton.cdiv(M, META[\"BLOCK_SIZE_M\"]) * triton.cdiv(N, META[\"BLOCK_SIZE_N\"]),\n )\n\n _w8a8_triton_block_scaled_mm[grid](\n A,\n B,\n C,\n As,\n Bs,\n M,\n N,\n K,\n block_n,\n block_k,\n A.stride(-2),\n A.stride(-1),\n B.stride(1),\n B.stride(0),\n C.stride(-2),\n C.stride(-1),\n As.stride(-2),\n As.stride(-1),\n Bs.stride(1),\n Bs.stride(0),\n **config,\n )\n\n return C\n\n\ndef requant_weight_ue8m0_inplace(\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n block_size: Sequence[int] = (128, 128),\n) -> None:\n \"\"\"Re-quantise *weight* so that its per-block scaling factors are in the\n UE8M0 (power-of-two) format expected by the new DeepGEMM kernels inplace.\n\n Args:\n weight: Block-quantised weight tensor stored in `torch.float8_e4m3fn`.\n Expected shape `(..., M, K)`.\n weight_scale: Corresponding per-block scale tensor (`torch.float32`)\n with shape `(..., M // block_size[0], K // block_size[1])`.\n block_size: 2-element iterable `[block_m, block_k]` describing the\n block quantisation granularity.\n \"\"\"\n if weight.numel() == 0:\n return\n\n if weight.dtype != torch.float8_e4m3fn:\n raise ValueError(\n f\"Expected *weight* to be torch.float8_e4m3fn, got {weight.dtype} instead.\"\n )\n\n from vllm.utils.deep_gemm import per_block_cast_to_fp8\n\n block_m, block_k = int(block_size[0]), int(block_size[1])\n\n # Flatten leading dimensions so we can iterate over the last two dims.\n leading_shape = weight.shape[:-2]\n if len(leading_shape) == 0:\n w_view = weight.unsqueeze(0)\n s_view = weight_scale.unsqueeze(0)\n else:\n w_view = weight.reshape(-1, weight.shape[-2], weight.shape[-1])\n s_view = weight_scale.reshape(-1, *weight_scale.shape[-2:])\n\n num_mats = w_view.size(0)\n for idx in range(num_mats):\n w_q = w_view[idx]\n s_old = s_view[idx]\n\n # De-quantise with the *old* scaling factors (float32).\n m_cur, k_cur = w_q.shape\n s_float = s_old.to(torch.float32)\n # Expand scales along rows and cols by block size, then crop.\n s_exp_r = torch.repeat_interleave(s_float, block_m, dim=0)\n s_exp = torch.repeat_interleave(s_exp_r, block_k, dim=1)\n s_exp = s_exp[:m_cur, :k_cur]\n w_dq = w_q.to(torch.float32) * s_exp\n # Re-quantise using power-of-two scaling (UE8M0).\n w_requant, s_requant = per_block_cast_to_fp8(\n w_dq, [block_m, block_k], use_ue8m0=True\n )\n\n # Write back the results in-place.\n w_q.copy_(w_requant)\n s_old.copy_(s_requant)\n\n\ndef deepgemm_post_process_fp8_weight_block(\n wq: torch.Tensor, ws: torch.Tensor, quant_block_shape: tuple[int], use_e8m0: bool\n) -> tuple[torch.Tensor, torch.Tensor]:\n assert wq.dtype == torch.float8_e4m3fn, (\n \"Expected quantized tensor dtype \"\n f\"to be torch.float8_e4m3fn, got {wq.dtype} instead.\"\n )\n assert ws.dtype == torch.float32, (\n f\"Expected tensor scales dtype to be torch.float32, got {ws.dtype} instead\"\n )\n\n if use_e8m0:\n requant_weight_ue8m0_inplace(wq, ws, block_size=quant_block_shape)\n\n original_ndim = wq.ndim\n if wq.ndim == 2:\n assert ws.ndim == 2\n wq = wq.unsqueeze(0)\n ws = ws.unsqueeze(0)\n\n # From https://github.com/deepseek-ai/DeepGEMM/blob/c9f8b34dcdacc20aa746b786f983492c51072870/csrc/utils/layout.hpp#L46\n recipe = (1, 128, 128)\n\n # Ref : https://github.com/deepseek-ai/DeepGEMM/blob/c9f8b34dcdacc20aa746b786f983492c51072870/csrc/apis/gemm.hpp\n # DeepGemm uses the `transform_sf_into_required_layout` function to\n # represent scales in the correct format.\n dg_ws = transform_sf_into_required_layout(\n sf=ws,\n mn=wq.size(1),\n k=wq.size(2),\n recipe=recipe,\n num_groups=wq.size(0),\n # is the scale factors for A in (Refers to the argument A in A @ B).\n # Weights are B.\n is_sfa=False,\n )\n\n if original_ndim == 2:\n wq = wq.squeeze(0)\n dg_ws = dg_ws.squeeze(0)\n\n return wq, dg_ws\n\n\ndef _maybe_pad_fp8_weight(weight: torch.Tensor) -> torch.Tensor:\n \"\"\"Pad the weight tensor. This is an optimization on ROCm platform, which\n can benefit from tensors located far enough from one another in memory\"\"\"\n if (\n envs.VLLM_ROCM_FP8_PADDING\n and current_platform.is_rocm()\n and weight.stride(-1) == 1\n and (weight.stride(-2) * weight.element_size()) % 512 == 0\n ):\n num_pad = 256 // weight.element_size()\n import torch.nn.functional as F\n\n weight = F.pad(weight, (0, num_pad), \"constant\", 0)[..., :-num_pad]\n torch.cuda.empty_cache()\n return weight\n\n\ndef validate_fp8_block_shape(\n layer: torch.nn.Module,\n input_size: int,\n output_size: int,\n input_size_per_partition: int,\n output_partition_sizes: list[int],\n block_size: list[int],\n) -> None:\n \"\"\"Validate block quantization shapes for tensor parallelism.\"\"\"\n from vllm.distributed import get_tensor_model_parallel_world_size\n\n tp_size = getattr(layer, \"tp_size\", get_tensor_model_parallel_world_size())\n block_n, block_k = block_size[0], block_size[1]\n\n # Required by row parallel\n if (\n tp_size > 1\n and input_size // input_size_per_partition == tp_size\n and input_size_per_partition % block_k != 0\n ):\n raise ValueError(\n f\"Weight input_size_per_partition = {input_size_per_partition} \"\n f\"is not divisible by weight quantization block_k = {block_k}.\"\n )\n\n # Required by column parallel or enabling merged weights\n is_tp_split = tp_size > 1 and output_size // sum(output_partition_sizes) == tp_size\n is_merged_gemm = len(output_partition_sizes) > 1\n if is_tp_split or is_merged_gemm:\n sizes_to_check = output_partition_sizes\n if not is_tp_split and is_merged_gemm:\n # In case of merged matrices, we allow the last\n # matrix to not be a multiple of block size\n sizes_to_check = output_partition_sizes[:-1]\n for output_partition_size in sizes_to_check:\n if output_partition_size % block_n != 0:\n raise ValueError(\n f\"Weight output_partition_size = \"\n f\"{output_partition_size} is not divisible by \"\n f\"weight quantization block_n = {block_n}.\"\n )\n\n\ndef create_fp8_weight_parameter(\n output_size_per_partition: int,\n input_size_per_partition: int,\n weight_loader: Callable | None,\n) -> torch.nn.Parameter:\n \"\"\"Create FP8 weight parameter.\"\"\"\n from vllm.model_executor.parameter import ModelWeightParameter\n\n return ModelWeightParameter(\n data=torch.empty(\n output_size_per_partition,\n input_size_per_partition,\n dtype=torch.float8_e4m3fn,\n ),\n input_dim=1,\n output_dim=0,\n weight_loader=weight_loader,\n )\n\n\ndef create_fp8_scale_parameter(\n parameter_type: torch.nn.Parameter,\n output_partition_sizes: list[int],\n input_size_per_partition: int,\n block_size: list[int] | None,\n weight_loader: Callable | None,\n) -> torch.nn.Parameter:\n \"\"\"Create scale parameter based on quantization strategy.\"\"\"\n if parameter_type == ChannelQuantScaleParameter:\n scale = parameter_type(\n data=torch.empty((sum(output_partition_sizes), 1), dtype=torch.float32),\n output_dim=0,\n weight_loader=weight_loader,\n )\n elif parameter_type == BlockQuantScaleParameter:\n assert block_size is not None\n block_n, block_k = block_size[0], block_size[1]\n output_size_per_partition = sum(output_partition_sizes)\n scale = parameter_type(\n data=torch.empty(\n (output_size_per_partition + block_n - 1) // block_n,\n (input_size_per_partition + block_k - 1) // block_k,\n dtype=torch.float32,\n ),\n input_dim=1,\n output_dim=0,\n weight_loader=weight_loader,\n )\n elif parameter_type == PerTensorScaleParameter:\n scale = parameter_type(\n data=torch.empty(len(output_partition_sizes), dtype=torch.float32),\n weight_loader=weight_loader,\n )\n else:\n raise ValueError(f\"Unknown parameter type: {parameter_type}\")\n\n scale[:] = torch.finfo(torch.float32).min\n return scale\n\n\ndef create_fp8_input_scale(\n output_partition_sizes: list[int], weight_loader: Callable | None\n) -> torch.nn.Parameter:\n \"\"\"Create input scale parameter for static activation quantization.\"\"\"\n from vllm.model_executor.parameter import PerTensorScaleParameter\n\n scale = PerTensorScaleParameter(\n data=torch.empty(len(output_partition_sizes), dtype=torch.float32),\n weight_loader=weight_loader,\n )\n scale[:] = torch.finfo(torch.float32).min\n return scale\n\n\ndef process_fp8_weight_tensor_strategy(\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n logical_widths: list[int],\n input_scale: torch.Tensor | None = None,\n) -> tuple[torch.Tensor, torch.Tensor, torch.Tensor | None]:\n \"\"\"Process weights for tensor-wise quantization strategy.\"\"\"\n from vllm.model_executor.layers.quantization.utils.w8a8_utils import (\n normalize_e4m3fn_to_e4m3fnuz,\n requantize_with_max_scale,\n )\n\n if current_platform.is_fp8_fnuz():\n weight, weight_scale, input_scale = normalize_e4m3fn_to_e4m3fnuz(\n weight=weight, weight_scale=weight_scale, input_scale=input_scale\n )\n\n # Requantize with max scale\n weight_scale, weight = requantize_with_max_scale(\n weight=weight,\n weight_scale=weight_scale,\n logical_widths=logical_widths,\n )\n\n weight = _maybe_pad_fp8_weight(weight)\n return weight, weight_scale, input_scale\n\n\ndef process_fp8_weight_channel_strategy(\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n input_scale: torch.Tensor | None = None,\n) -> tuple[torch.Tensor, torch.Tensor, torch.Tensor | None]:\n \"\"\"Process weights for channel-wise quantization strategy.\"\"\"\n from vllm.model_executor.layers.quantization.utils.w8a8_utils import (\n normalize_e4m3fn_to_e4m3fnuz,\n )\n\n if current_platform.is_fp8_fnuz():\n weight, weight_scale, input_scale = normalize_e4m3fn_to_e4m3fnuz(\n weight=weight, weight_scale=weight_scale, input_scale=input_scale\n )\n\n return weight, weight_scale, input_scale\n\n\ndef process_fp8_weight_block_strategy(\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n) -> tuple[torch.Tensor, torch.Tensor]:\n \"\"\"Process weights for block-wise quantization strategy.\"\"\"\n from vllm.model_executor.layers.quantization.utils.w8a8_utils import (\n normalize_e4m3fn_to_e4m3fnuz,\n )\n\n if current_platform.is_fp8_fnuz():\n weight, weight_scale, _ = normalize_e4m3fn_to_e4m3fnuz(\n weight=weight, weight_scale=weight_scale\n )\n\n weight = _maybe_pad_fp8_weight(weight)\n return weight, weight_scale\n\n\ndef maybe_post_process_fp8_weight_block(layer: torch.nn.Module):\n assert layer.weight_block_size is not None\n\n from vllm.utils.deep_gemm import (\n is_deep_gemm_e8m0_used,\n should_use_deepgemm_for_fp8_linear,\n )\n\n # On Blackwell or Hopper, if E8M0 for DeepGemm is used, we need to\n # requantize the weight and input to the specific scale\n # at the same time.\n should_use_deepgemm = should_use_deepgemm_for_fp8_linear(\n layer.orig_dtype, layer.weight\n )\n if should_use_deepgemm:\n dg_weight, dg_weight_scale = deepgemm_post_process_fp8_weight_block(\n wq=layer.weight.data,\n ws=layer.weight_scale.data,\n quant_block_shape=tuple(layer.weight_block_size),\n use_e8m0=is_deep_gemm_e8m0_used(),\n )\n layer.weight = torch.nn.Parameter(dg_weight, requires_grad=False)\n layer.weight_scale = torch.nn.Parameter(dg_weight_scale, requires_grad=False)\n\n\ndef expert_weight_is_col_major(x: torch.Tensor) -> bool:\n assert x.dim() == 3\n b, m, n = x.shape\n return x.stride(0) == m * n and x.stride(1) == 1 and x.stride(2) == m\n"},"after_code":{"kind":"string","value":"# SPDX-License-Identifier: Apache-2.0\n# SPDX-FileCopyrightText: Copyright contributors to the vLLM project\n\n# Adapted from https://github.com/sgl-project/sglang/pull/2575\nimport functools\nimport json\nimport os\nfrom collections.abc import Callable, Sequence\nfrom typing import Any\n\nimport torch\n\nimport vllm.envs as envs\nfrom vllm import _custom_ops as ops\nfrom vllm._aiter_ops import rocm_aiter_ops\nfrom vllm.logger import init_logger\nfrom vllm.model_executor.layers.quantization.input_quant_fp8 import QuantFP8\nfrom vllm.model_executor.layers.quantization.utils.quant_utils import (\n GroupShape,\n group_broadcast,\n)\nfrom vllm.model_executor.layers.quantization.utils.w8a8_utils import (\n CUTLASS_BLOCK_FP8_SUPPORTED,\n)\nfrom vllm.model_executor.parameter import (\n BlockQuantScaleParameter,\n ChannelQuantScaleParameter,\n PerTensorScaleParameter,\n)\nfrom vllm.platforms import current_platform\nfrom vllm.triton_utils import tl, triton\nfrom vllm.utils.deep_gemm import (\n fp8_gemm_nt,\n is_deep_gemm_e8m0_used,\n is_deep_gemm_supported,\n should_use_deepgemm_for_fp8_linear,\n transform_sf_into_required_layout,\n)\nfrom vllm.utils.torch_utils import direct_register_custom_op\n\nlogger = init_logger(__name__)\n\n\ndef is_fp8(x: torch.dtype | torch.Tensor) -> bool:\n if isinstance(x, torch.Tensor):\n x = x.dtype\n return x == torch.float8_e4m3fn or x == torch.float8_e4m3fnuz\n\n\n# We need to pass in the is_hopper flag as argument because the function\n# current_platform.is_device_capability() is not supported by Torch compiler.\ndef cutlass_scaled_mm(\n A: torch.Tensor,\n B: torch.Tensor,\n As: torch.Tensor,\n Bs: torch.Tensor,\n block_size: list[int],\n output_dtype: torch.dtype = torch.float16,\n) -> torch.Tensor:\n return ops.cutlass_scaled_mm(\n A,\n B.T,\n out_dtype=output_dtype,\n scale_a=As,\n scale_b=Bs.T,\n )\n\n\n# TODO we should be able to change the type of block_size to GroupShape\n# after we resolve GroupShape compilation issue\n# https://github.com/vllm-project/vllm/issues/25270\ndef _w8a8_triton_block_scaled_mm_func(\n qx: torch.Tensor,\n weight: torch.Tensor,\n x_scale: torch.Tensor,\n weight_scale: torch.Tensor,\n block_size: list[int],\n output_dtype: torch.dtype,\n) -> torch.Tensor:\n return w8a8_triton_block_scaled_mm(\n qx, weight, x_scale, weight_scale, block_size, output_dtype\n )\n\n\ndef _w8a8_triton_block_scaled_mm_fake(\n qx: torch.Tensor,\n weight: torch.Tensor,\n x_scale: torch.Tensor,\n weight_scale: torch.Tensor,\n block_size: list[int],\n output_dtype: torch.dtype,\n) -> torch.Tensor:\n return torch.empty(\n (qx.size(0), weight.size(0)), dtype=output_dtype, device=qx.device\n )\n\n\ndirect_register_custom_op(\n \"w8a8_triton_block_scaled_mm_func\",\n _w8a8_triton_block_scaled_mm_func,\n fake_impl=_w8a8_triton_block_scaled_mm_fake,\n)\n\n\ndef _padded_cutlass(\n qx: torch.Tensor,\n weight: torch.Tensor,\n x_scale: torch.Tensor,\n weight_scale: torch.Tensor,\n block_size: list[int],\n output_dtype: torch.dtype,\n) -> torch.Tensor:\n pad_multiple = 4\n dim = qx.shape[0]\n padded = (\n dim if dim % pad_multiple == 0 else dim + pad_multiple - (dim % pad_multiple)\n )\n\n has_pad = padded > dim\n\n if has_pad:\n padded_shape = [padded, *qx.shape[1:]]\n padded_qx = torch.zeros(padded_shape, device=qx.device, dtype=qx.dtype)\n padded_qx[0 : qx.shape[0], ...].copy_(qx)\n\n padded_x_scale_shape = [*x_scale.shape[1:], padded]\n padded_x_scale = torch.ones(\n padded_x_scale_shape, device=x_scale.device, dtype=x_scale.dtype\n ).permute(-1, -2)\n padded_x_scale[0 : x_scale.shape[0], ...].copy_(x_scale)\n\n output = cutlass_scaled_mm(\n padded_qx, weight, padded_x_scale, weight_scale, block_size, output_dtype\n )\n return output[0 : qx.shape[0], ...]\n else:\n return cutlass_scaled_mm(\n qx, weight, x_scale, weight_scale, block_size, output_dtype\n )\n\n\ndef _padded_cutlass_fake(\n qx: torch.Tensor,\n weight: torch.Tensor,\n x_scale: torch.Tensor,\n weight_scale: torch.Tensor,\n block_size: list[int],\n output_dtype: torch.dtype,\n) -> torch.Tensor:\n return torch.empty(\n (qx.size(0), weight.size(0)), dtype=output_dtype, device=qx.device\n )\n\n\ndirect_register_custom_op(\n \"padded_cutlass\",\n _padded_cutlass,\n fake_impl=_padded_cutlass_fake,\n)\n\n\ndef _fp8_gemm_nt_op(\n q_input: torch.Tensor,\n input_scale: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n output: torch.Tensor,\n use_deep_gemm_e8m0: bool,\n) -> None:\n fp8_gemm_nt(\n (q_input, input_scale),\n (weight, weight_scale),\n output,\n is_deep_gemm_e8m0_used=use_deep_gemm_e8m0,\n )\n\n\ndef _fp8_gemm_nt_op_fake(\n q_input: torch.Tensor,\n input_scale: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n output: torch.Tensor,\n use_deep_gemm_e8m0: bool,\n) -> None:\n return None\n\n\ndirect_register_custom_op(\n \"fp8_gemm_nt_op\",\n _fp8_gemm_nt_op,\n mutates_args=[\"output\"],\n fake_impl=_fp8_gemm_nt_op_fake,\n)\n\n\n# TODO fix ROCm->Triton custom path:\n# https://github.com/vllm-project/vllm/issues/14397\nclass W8A8BlockFp8LinearOp:\n \"\"\"\n This class executes a Blocked FP8 linear layer using cutlass if supported\n and torch.scaled_mm otherwise.\n \"\"\"\n\n def __init__(\n self,\n weight_group_shape: GroupShape,\n act_quant_group_shape: GroupShape,\n cutlass_block_fp8_supported: bool = CUTLASS_BLOCK_FP8_SUPPORTED,\n use_aiter_and_is_supported: bool = False,\n ):\n self.weight_group_shape = weight_group_shape\n self.act_quant_group_shape = act_quant_group_shape\n self.is_deep_gemm_supported = is_deep_gemm_supported()\n self.is_hopper = current_platform.is_device_capability(90)\n self.use_deep_gemm_e8m0 = is_deep_gemm_e8m0_used()\n\n # Get the correct blockscale mul and input quant operations.\n # We can't use _dispatch_w8a8_blockscale_op to figure out if we want\n # to use deepgemm because we don't know the shape of weights (and\n # whether deepgemm supports it) at the init time.\n self.w8a8_blockscale_op, self.input_quant_op = (\n self._dispatch_w8a8_blockscale_op(\n cutlass_block_fp8_supported, use_aiter_and_is_supported\n )\n )\n self.deepgemm_input_quant_op = (\n QuantFP8(\n False,\n self.act_quant_group_shape,\n column_major_scales=True,\n use_ue8m0=self.use_deep_gemm_e8m0,\n )\n if self.is_deep_gemm_supported\n else None\n )\n\n def apply(\n self,\n input: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n input_scale: torch.Tensor | None = None,\n bias: torch.Tensor | None = None,\n ) -> torch.Tensor:\n assert input_scale is None\n # View input as 2D matrix for fp8 methods\n input_2d = input.view(-1, input.shape[-1])\n output_shape = [*input.shape[:-1], weight.shape[0]]\n output_dtype = input.dtype\n\n if should_use_deepgemm_for_fp8_linear(\n output_dtype, weight, self.is_deep_gemm_supported\n ):\n output = self._run_deepgemm(input_2d, weight, weight_scale)\n else:\n output = self.w8a8_blockscale_op(\n input_2d, weight, weight_scale, input_scale\n )\n\n if bias is not None:\n output = output + bias\n return output.to(dtype=input.dtype).view(*output_shape)\n\n def _run_deepgemm(\n self,\n input_2d: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n ) -> torch.Tensor:\n assert self.deepgemm_input_quant_op is not None\n q_input, input_scale = per_token_group_quant_fp8_packed_for_deepgemm(\n input_2d,\n group_size=self.act_quant_group_shape.col,\n use_ue8m0=True,\n )\n output = torch.empty(\n (q_input.shape[0], weight.shape[0]),\n dtype=torch.bfloat16,\n device=q_input.device,\n )\n torch.ops.vllm.fp8_gemm_nt_op(\n q_input, input_scale, weight, weight_scale, output, self.use_deep_gemm_e8m0\n )\n return output\n\n def _run_cutlass(\n self,\n input_2d: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n input_scale: torch.Tensor | None = None,\n ) -> torch.Tensor:\n assert input_scale is None\n assert self.input_quant_op is not None\n q_input, input_scale = self.input_quant_op(input_2d)\n if self.is_hopper:\n return torch.ops.vllm.padded_cutlass(\n q_input,\n weight,\n input_scale,\n weight_scale,\n list(self.weight_group_shape),\n input_2d.dtype,\n )\n else:\n return cutlass_scaled_mm(\n q_input,\n weight,\n input_scale,\n weight_scale,\n list(self.weight_group_shape),\n input_2d.dtype,\n )\n\n def _run_aiter(\n self,\n input_2d: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n input_scale: torch.Tensor | None = None,\n ) -> torch.Tensor:\n assert self.act_quant_group_shape == GroupShape(1, 128)\n\n n, k = weight.shape\n\n use_triton = (\n not current_platform.is_fp8_fnuz()\n and rocm_aiter_ops.is_triton_gemm_w8a8_tuned(n, k)\n )\n\n if use_triton:\n gemm_a8w8_blockscale_op = rocm_aiter_ops.triton_gemm_a8w8_blockscale\n else:\n gemm_a8w8_blockscale_op = rocm_aiter_ops.gemm_a8w8_blockscale\n\n if input_scale is not None:\n q_input = input_2d\n # MI350 case uses triton kernel\n elif use_triton:\n q_input, input_scale = per_token_group_quant_fp8(\n input_2d,\n self.act_quant_group_shape.col,\n column_major_scales=False,\n use_ue8m0=False,\n )\n # MI300 uses tuned AITER ASM/C++ kernel\n else:\n q_input, input_scale = rocm_aiter_ops.group_fp8_quant(input_2d)\n\n return gemm_a8w8_blockscale_op(\n q_input,\n weight,\n input_scale,\n weight_scale,\n list(self.weight_group_shape),\n output_dtype=input_2d.dtype,\n )\n\n def _run_triton(\n self,\n input_2d: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n input_scale: torch.Tensor | None = None,\n ) -> torch.Tensor:\n assert input_scale is None\n assert self.input_quant_op is not None\n q_input, input_scale = self.input_quant_op(input_2d)\n return torch.ops.vllm.w8a8_triton_block_scaled_mm_func(\n q_input,\n weight,\n input_scale,\n weight_scale,\n list(self.weight_group_shape),\n input_2d.dtype,\n )\n\n def _dispatch_w8a8_blockscale_op(\n self,\n use_cutlass: bool,\n use_aiter_and_is_supported: bool,\n ) -> tuple[\n Callable[\n [\n torch.Tensor,\n torch.Tensor,\n torch.Tensor,\n torch.Tensor | None,\n ],\n torch.Tensor,\n ],\n QuantFP8 | None,\n ]:\n if use_cutlass:\n return self._run_cutlass, (\n QuantFP8(\n False,\n self.act_quant_group_shape,\n column_major_scales=True,\n use_ue8m0=False,\n )\n )\n if use_aiter_and_is_supported:\n return self._run_aiter, None\n return self._run_triton, (\n QuantFP8(\n False,\n self.act_quant_group_shape,\n column_major_scales=False,\n use_ue8m0=False,\n )\n )\n\n\ndef input_to_float8(\n x: torch.Tensor, dtype: torch.dtype | None = None\n) -> tuple[torch.Tensor, torch.Tensor]:\n \"\"\"This function quantizes input values to float8 values \"\n \"with tensor-wise quantization.\"\"\"\n dtype = current_platform.fp8_dtype() if dtype is None else dtype\n finfo = torch.finfo(dtype)\n min_val, max_val = x.aminmax()\n amax = torch.maximum(min_val.abs(), max_val.abs()).clamp(min=1e-12)\n scale = finfo.max / amax\n x_scl_sat = (x * scale).clamp(min=finfo.min, max=finfo.max)\n return x_scl_sat.to(dtype).contiguous(), scale.float().reciprocal()\n\n\ndef block_quant_to_tensor_quant(\n x_q_block: torch.Tensor,\n x_s: torch.Tensor,\n) -> tuple[torch.Tensor, torch.Tensor]:\n \"\"\"This function converts block-wise quantization to tensor-wise\n quantization. The inputs are block-wise quantization tensor `x_q_block`,\n block-wise quantization scale and the block size.\n The outputs are tensor-wise quantization tensor and tensor-wise\n quantization scale. Note only float8 is supported for now.\n \"\"\"\n x_dq_block = group_broadcast(x_q_block, x_s)\n x_q_tensor, scale = input_to_float8(x_dq_block, dtype=x_q_block.dtype)\n return x_q_tensor, scale\n\n\n@triton.jit\ndef _per_token_group_quant_fp8(\n # Pointers to inputs and output\n y_ptr,\n y_q_ptr,\n y_s_ptr,\n group_size,\n # Num columns of y\n y_num_columns,\n y_row_stride,\n # Avoid to divide zero\n eps,\n # Information for float8\n fp8_min,\n fp8_max,\n use_ue8m0: tl.constexpr,\n # Meta-parameters\n BLOCK: tl.constexpr,\n):\n \"\"\"A Triton-accelerated function to perform per-token-group\n quantization on a tensor.\n This function converts the tensor values into float8 values.\n \"\"\"\n groups_per_row = y_num_columns // group_size\n\n # Map the program id to the row of X and Y it should compute.\n g_id = tl.program_id(0)\n row = g_id // groups_per_row\n row_g_id = g_id % groups_per_row\n\n # Ensure offset calculations use int64 to prevent overflow\n y_ptr_offset = (row.to(tl.int64) * y_row_stride) + (\n row_g_id.to(tl.int64) * group_size\n )\n y_ptr += y_ptr_offset\n\n y_q_ptr_offset = g_id.to(tl.int64) * group_size\n y_q_ptr += y_q_ptr_offset\n y_s_ptr += g_id\n\n cols = tl.arange(0, BLOCK) # N <= BLOCK\n mask = cols < group_size\n\n y = tl.load(y_ptr + cols, mask=mask, other=0.0).to(tl.float32)\n # Quant\n _absmax = tl.maximum(tl.max(tl.abs(y)), eps)\n scale_raw = _absmax / fp8_max\n y_s = tl.math.exp2(tl.ceil(tl.log2(scale_raw))) if use_ue8m0 else scale_raw\n y_q = tl.clamp(y / y_s, fp8_min, fp8_max).to(y_q_ptr.dtype.element_ty)\n\n tl.store(y_q_ptr + cols, y_q, mask=mask)\n tl.store(y_s_ptr, y_s)\n\n\n@triton.jit\ndef _silu_mul_per_token_group_quant_fp8_colmajor(\n y_ptr, # [M, N]\n y_q_ptr, # [M, N // 2]\n y_s_ptr, # [M, (N // 2) // GROUP_SIZE]\n M, # num tokens\n N, # intermediate size\n # Stride\n y_s_col_stride: tl.int64,\n # Information for float8\n eps,\n fp8_min,\n fp8_max,\n use_ue8m0: tl.constexpr,\n # Meta-parameters\n GROUP_SIZE: tl.constexpr,\n BLOCK_M: tl.constexpr,\n BLOCK_N: tl.constexpr,\n):\n # TODO(varun) : Add expert_ids so we may early-exit no-op thread blocks.\n \"\"\"\n Each thread block (BLOCK_N) computes [BLOCK_M, GROUP_SIZE] act-mul outputs. Then\n the thread block quantizes the [BLOCK_M, GROUP_SIZE] block of values and fills\n the outputs tensors at the right positions.\n \"\"\"\n\n pid_m = tl.program_id(0)\n pid_n = tl.program_id(1)\n N_2 = N // 2\n\n m_offset = pid_m * BLOCK_M\n n_offset = pid_n * BLOCK_N\n if m_offset >= M:\n return\n\n offs_n = tl.arange(0, BLOCK_N).to(tl.int64)\n offs_m = tl.arange(0, BLOCK_M).to(tl.int64)\n\n base_y_ptr = y_ptr + m_offset * N + n_offset\n\n act_in_ptrs = base_y_ptr + offs_m[:, None] * N + offs_n[None, :]\n\n act_in = tl.load(act_in_ptrs)\n mul_in = tl.load(act_in_ptrs + N_2)\n\n # silu & mul\n act_in = act_in.to(tl.float32)\n one_f32 = tl.cast(1, tl.float32)\n silu_out = (act_in / (one_f32 + tl.exp(-act_in))).to(y_ptr.dtype.element_ty)\n y = (silu_out * mul_in).to(tl.float32)\n\n # quant\n _absmax = tl.maximum(tl.max(tl.abs(y), axis=1), eps)\n scale_raw = _absmax / fp8_max\n y_s = tl.math.exp2(tl.ceil(tl.log2(scale_raw))) if use_ue8m0 else scale_raw\n y_s = tl.reshape(y_s, (BLOCK_M, 1))\n y_q = tl.clamp(y / y_s, fp8_min, fp8_max).to(y_q_ptr.dtype.element_ty)\n\n # store y_q\n base_y_q_ptr = y_q_ptr + m_offset * N_2 + n_offset\n y_q_ptrs = base_y_q_ptr + offs_m[:, None] * N_2 + offs_n[None, :]\n tl.store(y_q_ptrs, y_q)\n\n # store y_s\n group_id = n_offset // GROUP_SIZE\n base_y_s_ptr = y_s_ptr + group_id * y_s_col_stride + m_offset\n y_s_ptrs = base_y_s_ptr + offs_m\n y_s = tl.reshape(y_s, (BLOCK_M,))\n tl.store(y_s_ptrs, y_s)\n\n\ndef silu_mul_per_token_group_quant_fp8_colmajor(\n input: torch.Tensor, # [M, N]\n output: torch.Tensor | None = None, # [M, N // 2]\n use_ue8m0: bool | None = None,\n eps: float = 1e-10,\n):\n \"\"\"\n silu+mul + block-fp8 quant with group size 128.\n \"\"\"\n GROUP_SIZE = 128\n assert input.ndim == 2\n if output is not None:\n assert output.ndim == 2\n assert input.size(0) % GROUP_SIZE == 0\n assert input.size(1) % (GROUP_SIZE * 2) == 0\n\n if use_ue8m0 is None:\n use_ue8m0 = is_deep_gemm_e8m0_used()\n\n M, N = input.size()\n N_2 = N // 2\n\n if output is None:\n output = torch.empty((M, N_2), dtype=torch.float8_e4m3fn, device=input.device)\n\n output_scales = torch.empty(\n ((N_2 // GROUP_SIZE), M), dtype=torch.float32, device=input.device\n ).transpose(0, 1)\n\n BLOCK_M = 8\n BLOCK_N = GROUP_SIZE\n assert M % BLOCK_M == 0\n assert N_2 % BLOCK_N == 0\n\n finfo = torch.finfo(torch.float8_e4m3fn)\n fp8_min = finfo.min\n fp8_max = finfo.max\n\n # Force even division so we can avoid edgecases within the kernel.\n assert M % BLOCK_M == 0\n assert N_2 % BLOCK_N == 0\n grid = (M // BLOCK_M, N_2 // BLOCK_N)\n\n _silu_mul_per_token_group_quant_fp8_colmajor[grid](\n input,\n output,\n output_scales,\n M,\n N,\n output_scales.stride(-1),\n eps,\n fp8_min,\n fp8_max,\n use_ue8m0,\n GROUP_SIZE,\n BLOCK_M,\n BLOCK_N,\n )\n\n return output, output_scales\n\n\n@triton.jit\ndef _per_token_group_quant_fp8_colmajor(\n # Pointers to inputs and output\n y_ptr,\n y_q_ptr,\n y_s_ptr,\n group_size,\n # Num columns of y\n y_num_columns,\n y_row_stride,\n # Stride from one column to the next of y_s\n y_s_col_stride,\n # Avoid to divide zero\n eps,\n # Information for float8\n fp8_min,\n fp8_max,\n use_ue8m0: tl.constexpr,\n # Meta-parameters\n BLOCK: tl.constexpr,\n):\n \"\"\"A Triton-accelerated function to perform per-token-group\n quantization on a tensor.\n This function converts the tensor values into float8 values.\n \"\"\"\n groups_per_row = y_num_columns // group_size\n\n # Map the program id to the row of X and Y it should compute.\n g_id = tl.program_id(0)\n row = g_id // groups_per_row\n row_g_id = g_id % groups_per_row\n\n # Ensure offset calculations use int64 to prevent overflow\n y_ptr_offset = (row.to(tl.int64) * y_row_stride) + (\n row_g_id.to(tl.int64) * group_size\n )\n y_ptr += y_ptr_offset\n\n y_q_ptr_offset = g_id.to(tl.int64) * group_size\n y_q_ptr += y_q_ptr_offset\n\n # Convert g_id the flattened block coordinate to 2D so we can index\n # into the output y_scales matrix\n blocks_per_row = y_num_columns // group_size\n scale_col = g_id % blocks_per_row\n scale_row = g_id // blocks_per_row\n # Ensure offset calculation uses int64 for y_s_ptr\n y_s_ptr_offset = (scale_col.to(tl.int64) * y_s_col_stride) + scale_row.to(tl.int64)\n y_s_ptr += y_s_ptr_offset\n\n cols = tl.arange(0, BLOCK) # group_size <= BLOCK\n mask = cols < group_size\n\n y = tl.load(y_ptr + cols, mask=mask, other=0.0).to(tl.float32)\n # Quant\n _absmax = tl.maximum(tl.max(tl.abs(y)), eps)\n scale_raw = _absmax / fp8_max\n y_s = tl.math.exp2(tl.ceil(tl.log2(scale_raw))) if use_ue8m0 else scale_raw\n y_q = tl.clamp(y / y_s, fp8_min, fp8_max).to(y_q_ptr.dtype.element_ty)\n\n tl.store(y_q_ptr + cols, y_q, mask=mask)\n tl.store(y_s_ptr, y_s)\n\n\ndef per_token_group_quant_fp8(\n x: torch.Tensor,\n group_size: int,\n eps: float = 1e-10,\n dtype: torch.dtype | None = None,\n column_major_scales: bool = False,\n out_q: torch.Tensor | None = None,\n use_ue8m0: bool | None = None,\n) -> tuple[torch.Tensor, torch.Tensor]:\n \"\"\"Function to perform per-token-group quantization on an input tensor `x`.\n It converts the tensor values into signed float8 values and returns the\n quantized tensor along with the scaling factor used for quantization.\n Args:\n x: The input tensor with ndim >= 2.\n group_size: The group size used for quantization.\n eps: The minimum to avoid dividing zero.\n dtype: The dype of output tensor. Note that only `torch.float8_e4m3fn`\n is supported for now.\n column_major_scales: Outputs scales in column major.\n out_q: Optional output tensor. If not provided, function will create.\n Returns:\n tuple[torch.Tensor, torch.Tensor]: The quantized tensor and the\n scaling factor.\n \"\"\"\n if use_ue8m0 is None:\n use_ue8m0 = is_deep_gemm_e8m0_used()\n dtype = current_platform.fp8_dtype() if dtype is None else dtype\n assert x.shape[-1] % group_size == 0, (\n f\"the last dimension of `x` {x.shape[-1]} must be divisible \"\n f\"by `group_size` {group_size}\"\n )\n assert x.stride(-1) == 1, \"`x` groups must be contiguous\"\n\n finfo = torch.finfo(dtype)\n fp8_min = finfo.min\n fp8_max = finfo.max\n\n assert out_q is None or out_q.shape == x.shape\n x_q = out_q\n if x_q is None:\n x_q = torch.empty_like(x, device=x.device, dtype=dtype)\n\n # Allocate the scale tensor in either row- or column-major format.\n if column_major_scales:\n shape = (x.shape[-1] // group_size,) + x.shape[:-1]\n x_s = torch.empty(shape, device=x.device, dtype=torch.float32).permute(-1, -2)\n else:\n shape = x.shape[:-1] + (x.shape[-1] // group_size,)\n x_s = torch.empty(shape, device=x.device, dtype=torch.float32)\n\n # prefer CUDA kernel if available\n # TODO(bnell): this causes some fp8 moe test to fail.\n if current_platform.is_cuda() and x.is_contiguous():\n torch.ops._C.per_token_group_fp8_quant(\n x, x_q, x_s, group_size, eps, fp8_min, fp8_max, use_ue8m0\n )\n return x_q, x_s\n\n # TRITON FALLBACK\n M = x.numel() // group_size\n N = group_size\n BLOCK = triton.next_power_of_2(N)\n # heuristics for number of warps\n num_warps = min(max(BLOCK // 256, 1), 8)\n num_stages = 1\n if column_major_scales:\n _per_token_group_quant_fp8_colmajor[(M,)](\n x,\n x_q,\n x_s,\n group_size,\n x.shape[1],\n x.stride(0),\n x_s.stride(1),\n eps,\n fp8_min=fp8_min,\n fp8_max=fp8_max,\n use_ue8m0=use_ue8m0,\n BLOCK=BLOCK,\n num_warps=num_warps,\n num_stages=num_stages,\n )\n else:\n _per_token_group_quant_fp8[(M,)](\n x,\n x_q,\n x_s,\n group_size,\n x.shape[1],\n x.stride(0),\n eps,\n fp8_min=fp8_min,\n fp8_max=fp8_max,\n use_ue8m0=use_ue8m0,\n BLOCK=BLOCK,\n num_warps=num_warps,\n num_stages=num_stages,\n )\n\n return x_q, x_s\n\n\ndef per_token_group_quant_fp8_packed_for_deepgemm(\n x: torch.Tensor,\n group_size: int,\n eps: float = 1e-10,\n use_ue8m0: bool | None = None,\n out_q: torch.Tensor | None = None,\n) -> tuple[torch.Tensor, torch.Tensor]:\n \"\"\"FP8 per-token-group quantization for DeepGEMM.\n\n Returns:\n (x_q, x_s_packed)\n x_q: FP8 activations, same shape as `x`.\n x_s_packed: Int32 tensor with logical shape\n [mn, ceil(num_groups_per_row / 4)], laid out with\n TMA-aligned stride along the packed-K dimension\n \"\"\"\n if use_ue8m0 is None:\n use_ue8m0 = is_deep_gemm_e8m0_used()\n # for DeepGEMM UE8M0-packed layout we *require* UE8M0 scales.\n assert use_ue8m0, (\n \"per_token_group_quant_fp8_packed_for_deepgemm requires UE8M0 scales.\"\n )\n\n dtype = current_platform.fp8_dtype()\n assert x.shape[-1] % group_size == 0, (\n f\"the last dimension of `x` {x.shape[-1]} must be divisible \"\n f\"by `group_size` {group_size}\"\n )\n assert x.stride(-1) == 1, \"`x` groups must be contiguous\"\n\n finfo = torch.finfo(dtype)\n fp8_min, fp8_max = finfo.min, finfo.max\n\n # compute DeepGEMM-style packed scale tensor shape.\n hidden_dim = x.shape[-1]\n mn = x.numel() // hidden_dim\n num_groups_per_row = hidden_dim // group_size\n k_num_packed_sf_k = (num_groups_per_row + 3) // 4\n tma_aligned_mn = ((mn + 3) // 4) * 4\n\n x_s_packed = torch.empty_strided(\n (mn, k_num_packed_sf_k),\n (1, tma_aligned_mn),\n device=x.device,\n dtype=torch.int32,\n )\n\n # CUDA kernel path only (DeepGEMM + E8M0 is CUDA-specific).\n assert current_platform.is_cuda(), (\n \"per_token_group_quant_fp8_packed_for_deepgemm is only valid on CUDA \"\n \"platforms using DeepGEMM.\"\n )\n\n x_contiguous = x.contiguous()\n if out_q is not None:\n x_q_local = out_q\n else:\n x_q_local = torch.empty_like(x_contiguous, device=x.device, dtype=dtype)\n\n torch.ops._C.per_token_group_fp8_quant_packed(\n x_contiguous,\n x_q_local,\n x_s_packed,\n group_size,\n eps,\n fp8_min,\n fp8_max,\n )\n\n # return a tensor with the original logical shape.\n x_q = x_q_local.view_as(x)\n return x_q, x_s_packed\n\n\n@triton.jit\ndef _w8a8_triton_block_scaled_mm(\n # Pointers to inputs and output\n A,\n B,\n C,\n As,\n Bs,\n # Shape for matmul\n M,\n N,\n K,\n # Block size for block-wise quantization\n group_n,\n group_k,\n # Stride for inputs and output\n stride_am,\n stride_ak,\n stride_bk,\n stride_bn,\n stride_cm,\n stride_cn,\n stride_As_m,\n stride_As_k,\n stride_Bs_k,\n stride_Bs_n,\n # Meta-parameters\n BLOCK_SIZE_M: tl.constexpr,\n BLOCK_SIZE_N: tl.constexpr,\n BLOCK_SIZE_K: tl.constexpr,\n GROUP_SIZE_M: tl.constexpr,\n):\n \"\"\"Triton-accelerated function used to perform linear operations (dot\n product) on input tensors `A` and `B` with block-wise quantization, and\n store the result in output tensor `C`.\n \"\"\"\n\n pid = tl.program_id(axis=0)\n num_pid_m = tl.cdiv(M, BLOCK_SIZE_M)\n num_pid_n = tl.cdiv(N, BLOCK_SIZE_N)\n num_pid_in_group = GROUP_SIZE_M * num_pid_n\n group_id = pid // num_pid_in_group\n first_pid_m = group_id * GROUP_SIZE_M\n group_size_m = min(num_pid_m - first_pid_m, GROUP_SIZE_M)\n pid_m = first_pid_m + (pid % group_size_m)\n pid_n = (pid % num_pid_in_group) // group_size_m\n\n offs_am = (pid_m * BLOCK_SIZE_M + tl.arange(0, BLOCK_SIZE_M)) % M\n offs_bn = (pid_n * BLOCK_SIZE_N + tl.arange(0, BLOCK_SIZE_N)) % N\n offs_k = tl.arange(0, BLOCK_SIZE_K)\n a_ptrs = A + (offs_am[:, None] * stride_am + offs_k[None, :] * stride_ak)\n b_ptrs = B + (offs_k[:, None] * stride_bk + offs_bn[None, :] * stride_bn)\n\n As_ptrs = As + offs_am * stride_As_m\n offs_bsn = offs_bn // group_n\n Bs_ptrs = Bs + offs_bsn * stride_Bs_n\n\n accumulator = tl.zeros((BLOCK_SIZE_M, BLOCK_SIZE_N), dtype=tl.float32)\n for k in range(0, tl.cdiv(K, BLOCK_SIZE_K)):\n a = tl.load(a_ptrs, mask=offs_k[None, :] < K - k * BLOCK_SIZE_K, other=0.0)\n b = tl.load(b_ptrs, mask=offs_k[:, None] < K - k * BLOCK_SIZE_K, other=0.0)\n\n k_start = k * BLOCK_SIZE_K\n offs_ks = k_start // group_k\n a_s = tl.load(As_ptrs + offs_ks * stride_As_k)\n b_s = tl.load(Bs_ptrs + offs_ks * stride_Bs_k)\n\n accumulator += tl.dot(a, b) * a_s[:, None] * b_s[None, :]\n a_ptrs += BLOCK_SIZE_K * stride_ak\n b_ptrs += BLOCK_SIZE_K * stride_bk\n\n if C.dtype.element_ty == tl.bfloat16:\n c = accumulator.to(tl.bfloat16)\n elif C.dtype.element_ty == tl.float16:\n c = accumulator.to(tl.float16)\n else:\n c = accumulator.to(tl.float32)\n\n offs_cm = pid_m * BLOCK_SIZE_M + tl.arange(0, BLOCK_SIZE_M)\n offs_cn = pid_n * BLOCK_SIZE_N + tl.arange(0, BLOCK_SIZE_N)\n c_ptrs = C + stride_cm * offs_cm[:, None] + stride_cn * offs_cn[None, :]\n c_mask = (offs_cm[:, None] < M) & (offs_cn[None, :] < N)\n tl.store(c_ptrs, c, mask=c_mask)\n\n\n@functools.lru_cache\ndef get_w8a8_block_fp8_configs(\n N: int, K: int, block_n: int, block_k: int\n) -> dict[int, Any] | None:\n \"\"\"\n Return optimized configurations for the w8a8 block fp8 kernel.\n The return value will be a dictionary that maps an irregular grid of\n batch sizes to configurations of the w8a8 block fp8 kernel. To evaluate the\n kernel on a given batch size bs, the closest batch size in the grid should\n be picked and the associated configuration chosen to invoke the kernel.\n \"\"\"\n\n # First look up if an optimized configuration is available in the configs\n # directory\n device_name = current_platform.get_device_name().replace(\" \", \"_\")\n json_file_name = f\"N={N},K={K},device_name={device_name},dtype=fp8_w8a8,block_shape=[{block_n},{block_k}].json\" # noqa: E501\n\n config_file_path = os.path.join(\n os.path.dirname(os.path.realpath(__file__)), \"configs\", json_file_name\n )\n if os.path.exists(config_file_path):\n with open(config_file_path) as f:\n logger.info(\n \"Using configuration from %s for W8A8 Block FP8 kernel.\",\n config_file_path,\n )\n # If a configuration has been found, return it\n return {int(key): val for key, val in json.load(f).items()}\n\n # If no optimized configuration is available, we will use the default\n # configuration\n logger.warning(\n \"Using default W8A8 Block FP8 kernel config. Performance might \"\n \"be sub-optimal! Config file not found at %s\",\n config_file_path,\n )\n return None\n\n\ndef w8a8_triton_block_scaled_mm(\n A: torch.Tensor,\n B: torch.Tensor,\n As: torch.Tensor,\n Bs: torch.Tensor,\n block_size: list[int],\n output_dtype: torch.dtype = torch.float16,\n) -> torch.Tensor:\n \"\"\"This function performs matrix multiplication with block-wise\n quantization.\n It takes two input tensors `A` and `B` with scales `As` and `Bs`.\n The output is returned in the specified `output_dtype`.\n Args:\n A: The input tensor, e.g., activation.\n B: The input tensor, e.g., weight.\n As: The per-token-group quantization scale for `A`.\n Bs: The per-block quantization scale for `B`.\n block_size: The block size for per-block quantization. It should\n be 2-dim, e.g., [128, 128].\n output_dytpe: The dtype of the returned tensor.\n Returns:\n torch.Tensor: The result of matmul.\n \"\"\"\n assert len(block_size) == 2\n block_n, block_k = block_size[0], block_size[1]\n\n assert A.shape[-1] == B.shape[-1]\n assert A.shape[:-1] == As.shape[:-1] and A.is_contiguous()\n assert triton.cdiv(A.shape[-1], block_k) == As.shape[-1]\n M = A.numel() // A.shape[-1]\n\n assert B.ndim == 2 and Bs.ndim == 2\n N, K = B.shape\n assert triton.cdiv(N, block_n) == Bs.shape[0]\n assert triton.cdiv(K, block_k) == Bs.shape[1]\n\n C_shape = A.shape[:-1] + (N,)\n C = A.new_empty(C_shape, dtype=output_dtype)\n\n configs = get_w8a8_block_fp8_configs(N, K, block_size[0], block_size[1])\n if configs:\n # Get the optimal config if there is one\n config = configs[min(configs.keys(), key=lambda x: abs(x - M))]\n else:\n # Default config\n # Block-wise quant: BLOCK_SIZE_N must be divisible by block_size[0]\n # BLOCK_SIZE_K must be divisible by block_size[1]\n config = {\n \"BLOCK_SIZE_M\": 64,\n \"BLOCK_SIZE_N\": block_size[0],\n \"BLOCK_SIZE_K\": block_size[1],\n \"GROUP_SIZE_M\": 32,\n \"num_warps\": 4,\n \"num_stages\": 2,\n }\n\n def grid(META):\n return (\n triton.cdiv(M, META[\"BLOCK_SIZE_M\"]) * triton.cdiv(N, META[\"BLOCK_SIZE_N\"]),\n )\n\n _w8a8_triton_block_scaled_mm[grid](\n A,\n B,\n C,\n As,\n Bs,\n M,\n N,\n K,\n block_n,\n block_k,\n A.stride(-2),\n A.stride(-1),\n B.stride(1),\n B.stride(0),\n C.stride(-2),\n C.stride(-1),\n As.stride(-2),\n As.stride(-1),\n Bs.stride(1),\n Bs.stride(0),\n **config,\n )\n\n return C\n\n\ndef requant_weight_ue8m0_inplace(\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n block_size: Sequence[int] = (128, 128),\n) -> None:\n \"\"\"Re-quantise *weight* so that its per-block scaling factors are in the\n UE8M0 (power-of-two) format expected by the new DeepGEMM kernels inplace.\n\n Args:\n weight: Block-quantised weight tensor stored in `torch.float8_e4m3fn`.\n Expected shape `(..., M, K)`.\n weight_scale: Corresponding per-block scale tensor (`torch.float32`)\n with shape `(..., M // block_size[0], K // block_size[1])`.\n block_size: 2-element iterable `[block_m, block_k]` describing the\n block quantisation granularity.\n \"\"\"\n if weight.numel() == 0:\n return\n\n if weight.dtype != torch.float8_e4m3fn:\n raise ValueError(\n f\"Expected *weight* to be torch.float8_e4m3fn, got {weight.dtype} instead.\"\n )\n\n from vllm.utils.deep_gemm import per_block_cast_to_fp8\n\n block_m, block_k = int(block_size[0]), int(block_size[1])\n\n # Flatten leading dimensions so we can iterate over the last two dims.\n leading_shape = weight.shape[:-2]\n if len(leading_shape) == 0:\n w_view = weight.unsqueeze(0)\n s_view = weight_scale.unsqueeze(0)\n else:\n w_view = weight.reshape(-1, weight.shape[-2], weight.shape[-1])\n s_view = weight_scale.reshape(-1, *weight_scale.shape[-2:])\n\n num_mats = w_view.size(0)\n for idx in range(num_mats):\n w_q = w_view[idx]\n s_old = s_view[idx]\n\n # De-quantise with the *old* scaling factors (float32).\n m_cur, k_cur = w_q.shape\n s_float = s_old.to(torch.float32)\n # Expand scales along rows and cols by block size, then crop.\n s_exp_r = torch.repeat_interleave(s_float, block_m, dim=0)\n s_exp = torch.repeat_interleave(s_exp_r, block_k, dim=1)\n s_exp = s_exp[:m_cur, :k_cur]\n w_dq = w_q.to(torch.float32) * s_exp\n # Re-quantise using power-of-two scaling (UE8M0).\n w_requant, s_requant = per_block_cast_to_fp8(\n w_dq, [block_m, block_k], use_ue8m0=True\n )\n\n # Write back the results in-place.\n w_q.copy_(w_requant)\n s_old.copy_(s_requant)\n\n\ndef deepgemm_post_process_fp8_weight_block(\n wq: torch.Tensor, ws: torch.Tensor, quant_block_shape: tuple[int], use_e8m0: bool\n) -> tuple[torch.Tensor, torch.Tensor]:\n assert wq.dtype == torch.float8_e4m3fn, (\n \"Expected quantized tensor dtype \"\n f\"to be torch.float8_e4m3fn, got {wq.dtype} instead.\"\n )\n assert ws.dtype == torch.float32, (\n f\"Expected tensor scales dtype to be torch.float32, got {ws.dtype} instead\"\n )\n\n if use_e8m0:\n requant_weight_ue8m0_inplace(wq, ws, block_size=quant_block_shape)\n\n original_ndim = wq.ndim\n if wq.ndim == 2:\n assert ws.ndim == 2\n wq = wq.unsqueeze(0)\n ws = ws.unsqueeze(0)\n\n # From https://github.com/deepseek-ai/DeepGEMM/blob/c9f8b34dcdacc20aa746b786f983492c51072870/csrc/utils/layout.hpp#L46\n recipe = (1, 128, 128)\n\n # Ref : https://github.com/deepseek-ai/DeepGEMM/blob/c9f8b34dcdacc20aa746b786f983492c51072870/csrc/apis/gemm.hpp\n # DeepGemm uses the `transform_sf_into_required_layout` function to\n # represent scales in the correct format.\n dg_ws = transform_sf_into_required_layout(\n sf=ws,\n mn=wq.size(1),\n k=wq.size(2),\n recipe=recipe,\n num_groups=wq.size(0),\n # is the scale factors for A in (Refers to the argument A in A @ B).\n # Weights are B.\n is_sfa=False,\n )\n\n if original_ndim == 2:\n wq = wq.squeeze(0)\n dg_ws = dg_ws.squeeze(0)\n\n return wq, dg_ws\n\n\ndef _maybe_pad_fp8_weight(weight: torch.Tensor) -> torch.Tensor:\n \"\"\"Pad the weight tensor. This is an optimization on ROCm platform, which\n can benefit from tensors located far enough from one another in memory\"\"\"\n if (\n envs.VLLM_ROCM_FP8_PADDING\n and current_platform.is_rocm()\n and weight.stride(-1) == 1\n and (weight.stride(-2) * weight.element_size()) % 512 == 0\n ):\n num_pad = 256 // weight.element_size()\n import torch.nn.functional as F\n\n weight = F.pad(weight, (0, num_pad), \"constant\", 0)[..., :-num_pad]\n torch.cuda.empty_cache()\n return weight\n\n\ndef validate_fp8_block_shape(\n layer: torch.nn.Module,\n input_size: int,\n output_size: int,\n input_size_per_partition: int,\n output_partition_sizes: list[int],\n block_size: list[int],\n) -> None:\n \"\"\"Validate block quantization shapes for tensor parallelism.\"\"\"\n from vllm.distributed import get_tensor_model_parallel_world_size\n\n tp_size = getattr(layer, \"tp_size\", get_tensor_model_parallel_world_size())\n block_n, block_k = block_size[0], block_size[1]\n\n # Required by row parallel\n if (\n tp_size > 1\n and input_size // input_size_per_partition == tp_size\n and input_size_per_partition % block_k != 0\n ):\n raise ValueError(\n f\"Weight input_size_per_partition = {input_size_per_partition} \"\n f\"is not divisible by weight quantization block_k = {block_k}.\"\n )\n\n # Required by column parallel or enabling merged weights\n is_tp_split = tp_size > 1 and output_size // sum(output_partition_sizes) == tp_size\n is_merged_gemm = len(output_partition_sizes) > 1\n if is_tp_split or is_merged_gemm:\n sizes_to_check = output_partition_sizes\n if not is_tp_split and is_merged_gemm:\n # In case of merged matrices, we allow the last\n # matrix to not be a multiple of block size\n sizes_to_check = output_partition_sizes[:-1]\n for output_partition_size in sizes_to_check:\n if output_partition_size % block_n != 0:\n raise ValueError(\n f\"Weight output_partition_size = \"\n f\"{output_partition_size} is not divisible by \"\n f\"weight quantization block_n = {block_n}.\"\n )\n\n\ndef create_fp8_weight_parameter(\n output_size_per_partition: int,\n input_size_per_partition: int,\n weight_loader: Callable | None,\n) -> torch.nn.Parameter:\n \"\"\"Create FP8 weight parameter.\"\"\"\n from vllm.model_executor.parameter import ModelWeightParameter\n\n return ModelWeightParameter(\n data=torch.empty(\n output_size_per_partition,\n input_size_per_partition,\n dtype=torch.float8_e4m3fn,\n ),\n input_dim=1,\n output_dim=0,\n weight_loader=weight_loader,\n )\n\n\ndef create_fp8_scale_parameter(\n parameter_type: torch.nn.Parameter,\n output_partition_sizes: list[int],\n input_size_per_partition: int,\n block_size: list[int] | None,\n weight_loader: Callable | None,\n) -> torch.nn.Parameter:\n \"\"\"Create scale parameter based on quantization strategy.\"\"\"\n if parameter_type == ChannelQuantScaleParameter:\n scale = parameter_type(\n data=torch.empty((sum(output_partition_sizes), 1), dtype=torch.float32),\n output_dim=0,\n weight_loader=weight_loader,\n )\n elif parameter_type == BlockQuantScaleParameter:\n assert block_size is not None\n block_n, block_k = block_size[0], block_size[1]\n output_size_per_partition = sum(output_partition_sizes)\n scale = parameter_type(\n data=torch.empty(\n (output_size_per_partition + block_n - 1) // block_n,\n (input_size_per_partition + block_k - 1) // block_k,\n dtype=torch.float32,\n ),\n input_dim=1,\n output_dim=0,\n weight_loader=weight_loader,\n )\n elif parameter_type == PerTensorScaleParameter:\n scale = parameter_type(\n data=torch.empty(len(output_partition_sizes), dtype=torch.float32),\n weight_loader=weight_loader,\n )\n else:\n raise ValueError(f\"Unknown parameter type: {parameter_type}\")\n\n scale[:] = torch.finfo(torch.float32).min\n return scale\n\n\ndef create_fp8_input_scale(\n output_partition_sizes: list[int], weight_loader: Callable | None\n) -> torch.nn.Parameter:\n \"\"\"Create input scale parameter for static activation quantization.\"\"\"\n from vllm.model_executor.parameter import PerTensorScaleParameter\n\n scale = PerTensorScaleParameter(\n data=torch.empty(len(output_partition_sizes), dtype=torch.float32),\n weight_loader=weight_loader,\n )\n scale[:] = torch.finfo(torch.float32).min\n return scale\n\n\ndef process_fp8_weight_tensor_strategy(\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n logical_widths: list[int],\n input_scale: torch.Tensor | None = None,\n) -> tuple[torch.Tensor, torch.Tensor, torch.Tensor | None]:\n \"\"\"Process weights for tensor-wise quantization strategy.\"\"\"\n from vllm.model_executor.layers.quantization.utils.w8a8_utils import (\n normalize_e4m3fn_to_e4m3fnuz,\n requantize_with_max_scale,\n )\n\n if current_platform.is_fp8_fnuz():\n weight, weight_scale, input_scale = normalize_e4m3fn_to_e4m3fnuz(\n weight=weight, weight_scale=weight_scale, input_scale=input_scale\n )\n\n # Requantize with max scale\n weight_scale, weight = requantize_with_max_scale(\n weight=weight,\n weight_scale=weight_scale,\n logical_widths=logical_widths,\n )\n\n weight = _maybe_pad_fp8_weight(weight)\n return weight, weight_scale, input_scale\n\n\ndef process_fp8_weight_channel_strategy(\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n input_scale: torch.Tensor | None = None,\n) -> tuple[torch.Tensor, torch.Tensor, torch.Tensor | None]:\n \"\"\"Process weights for channel-wise quantization strategy.\"\"\"\n from vllm.model_executor.layers.quantization.utils.w8a8_utils import (\n normalize_e4m3fn_to_e4m3fnuz,\n )\n\n if current_platform.is_fp8_fnuz():\n weight, weight_scale, input_scale = normalize_e4m3fn_to_e4m3fnuz(\n weight=weight, weight_scale=weight_scale, input_scale=input_scale\n )\n\n return weight, weight_scale, input_scale\n\n\ndef process_fp8_weight_block_strategy(\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n) -> tuple[torch.Tensor, torch.Tensor]:\n \"\"\"Process weights for block-wise quantization strategy.\"\"\"\n from vllm.model_executor.layers.quantization.utils.w8a8_utils import (\n normalize_e4m3fn_to_e4m3fnuz,\n )\n\n if current_platform.is_fp8_fnuz():\n weight, weight_scale, _ = normalize_e4m3fn_to_e4m3fnuz(\n weight=weight, weight_scale=weight_scale\n )\n\n weight = _maybe_pad_fp8_weight(weight)\n return weight, weight_scale\n\n\ndef maybe_post_process_fp8_weight_block(layer: torch.nn.Module):\n assert layer.weight_block_size is not None\n\n from vllm.utils.deep_gemm import (\n is_deep_gemm_e8m0_used,\n should_use_deepgemm_for_fp8_linear,\n )\n\n # On Blackwell or Hopper, if E8M0 for DeepGemm is used, we need to\n # requantize the weight and input to the specific scale\n # at the same time.\n should_use_deepgemm = should_use_deepgemm_for_fp8_linear(\n layer.orig_dtype, layer.weight\n )\n if should_use_deepgemm:\n dg_weight, dg_weight_scale = deepgemm_post_process_fp8_weight_block(\n wq=layer.weight.data,\n ws=layer.weight_scale.data,\n quant_block_shape=tuple(layer.weight_block_size),\n use_e8m0=is_deep_gemm_e8m0_used(),\n )\n layer.weight = torch.nn.Parameter(dg_weight, requires_grad=False)\n layer.weight_scale = torch.nn.Parameter(dg_weight_scale, requires_grad=False)\n\n\ndef expert_weight_is_col_major(x: torch.Tensor) -> bool:\n assert x.dim() == 3\n b, m, n = x.shape\n return x.stride(0) == m * n and x.stride(1) == 1 and x.stride(2) == m\n"},"diff":{"kind":"string","value":"--- vllm/model_executor/layers/quantization/utils/fp8_utils.py\n+++ vllm/model_executor/layers/quantization/utils/fp8_utils.py\n@@ -269,7 +269,11 @@\n weight_scale: torch.Tensor,\n ) -> torch.Tensor:\n assert self.deepgemm_input_quant_op is not None\n- q_input, input_scale = self.deepgemm_input_quant_op(input_2d)\n+ q_input, input_scale = per_token_group_quant_fp8_packed_for_deepgemm(\n+ input_2d,\n+ group_size=self.act_quant_group_shape.col,\n+ use_ue8m0=True,\n+ )\n output = torch.empty(\n (q_input.shape[0], weight.shape[0]),\n dtype=torch.bfloat16,\n@@ -789,6 +793,80 @@\n )\n \n return x_q, x_s\n+\n+\n+def per_token_group_quant_fp8_packed_for_deepgemm(\n+ x: torch.Tensor,\n+ group_size: int,\n+ eps: float = 1e-10,\n+ use_ue8m0: bool | None = None,\n+ out_q: torch.Tensor | None = None,\n+) -> tuple[torch.Tensor, torch.Tensor]:\n+ \"\"\"FP8 per-token-group quantization for DeepGEMM.\n+\n+ Returns:\n+ (x_q, x_s_packed)\n+ x_q: FP8 activations, same shape as `x`.\n+ x_s_packed: Int32 tensor with logical shape\n+ [mn, ceil(num_groups_per_row / 4)], laid out with\n+ TMA-aligned stride along the packed-K dimension\n+ \"\"\"\n+ if use_ue8m0 is None:\n+ use_ue8m0 = is_deep_gemm_e8m0_used()\n+ # for DeepGEMM UE8M0-packed layout we *require* UE8M0 scales.\n+ assert use_ue8m0, (\n+ \"per_token_group_quant_fp8_packed_for_deepgemm requires UE8M0 scales.\"\n+ )\n+\n+ dtype = current_platform.fp8_dtype()\n+ assert x.shape[-1] % group_size == 0, (\n+ f\"the last dimension of `x` {x.shape[-1]} must be divisible \"\n+ f\"by `group_size` {group_size}\"\n+ )\n+ assert x.stride(-1) == 1, \"`x` groups must be contiguous\"\n+\n+ finfo = torch.finfo(dtype)\n+ fp8_min, fp8_max = finfo.min, finfo.max\n+\n+ # compute DeepGEMM-style packed scale tensor shape.\n+ hidden_dim = x.shape[-1]\n+ mn = x.numel() // hidden_dim\n+ num_groups_per_row = hidden_dim // group_size\n+ k_num_packed_sf_k = (num_groups_per_row + 3) // 4\n+ tma_aligned_mn = ((mn + 3) // 4) * 4\n+\n+ x_s_packed = torch.empty_strided(\n+ (mn, k_num_packed_sf_k),\n+ (1, tma_aligned_mn),\n+ device=x.device,\n+ dtype=torch.int32,\n+ )\n+\n+ # CUDA kernel path only (DeepGEMM + E8M0 is CUDA-specific).\n+ assert current_platform.is_cuda(), (\n+ \"per_token_group_quant_fp8_packed_for_deepgemm is only valid on CUDA \"\n+ \"platforms using DeepGEMM.\"\n+ )\n+\n+ x_contiguous = x.contiguous()\n+ if out_q is not None:\n+ x_q_local = out_q\n+ else:\n+ x_q_local = torch.empty_like(x_contiguous, device=x.device, dtype=dtype)\n+\n+ torch.ops._C.per_token_group_fp8_quant_packed(\n+ x_contiguous,\n+ x_q_local,\n+ x_s_packed,\n+ group_size,\n+ eps,\n+ fp8_min,\n+ fp8_max,\n+ )\n+\n+ # return a tensor with the original logical shape.\n+ x_q = x_q_local.view_as(x)\n+ return x_q, x_s_packed\n \n \n @triton.jit"},"lines_added":{"kind":"number","value":79,"string":"79"},"lines_removed":{"kind":"number","value":1,"string":"1"},"files_in_commit":{"kind":"number","value":5,"string":"5"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this triton kernel file from vllm (vllm/model_executor/layers/quantization/utils/fp8_utils.py).\n\nGoal: [Perf] Deepgemm fused layout kernel for activations, 4.3% throughput improvement, 10.7% TTFT improvement.\nTarget hardware: unspecified\nTarget models: unspecified\n\nCurrent file:\n```python\n# SPDX-License-Identifier: Apache-2.0\n# SPDX-FileCopyrightText: Copyright contributors to the vLLM project\n\n# Adapted from https://github.com/sgl-project/sglang/pull/2575\nimport functools\nimport json\nimport os\nfrom collections.abc import Callable, Sequence\nfrom typing import Any\n\nimport torch\n\nimport vllm.envs as envs\nfrom vllm import _custom_ops as ops\nfrom vllm._aiter_ops import rocm_aiter_ops\nfrom vllm.logger import init_logger\nfrom vllm.model_executor.layers.quantization.input_quant_fp8 import QuantFP8\nfrom vllm.model_executor.layers.quantization.utils.quant_utils import (\n GroupShape,\n group_broadcast,\n)\nfrom vllm.model_executor.layers.quantization.utils.w8a8_utils import (\n CUTLASS_BLOCK_FP8_SUPPORTED,\n)\nfrom vllm.model_executor.parameter import (\n BlockQuantScaleParameter,\n ChannelQuantScaleParameter,\n PerTensorScaleParameter,\n)\nfrom vllm.platforms import current_platform\nfrom vllm.triton_utils import tl, triton\nfrom vllm.utils.deep_gemm import (\n fp8_gemm_nt,\n is_deep_gemm_e8m0_used,\n is_deep_gemm_supported,\n should_use_deepgemm_for_fp8_linear,\n transform_sf_into_required_layout,\n)\nfrom vllm.utils.torch_utils import direct_register_custom_op\n\nlogger = init_logger(__name__)\n\n\ndef is_fp8(x: torch.dtype | torch.Tensor) -> bool:\n if isinstance(x, torch.Tensor):\n x = x.dtype\n return x == torch.float8_e4m3fn or x == torch.float8_e4m3fnuz\n\n\n# We need to pass in the is_hopper flag as argument because the function\n# current_platform.is_device_capability() is not supported by Torch compiler.\ndef cutlass_scaled_mm(\n A: torch.Tensor,\n B: torch.Tensor,\n As: torch.Tensor,\n Bs: torch.Tensor,\n block_size: list[int],\n output_dtype: torch.dtype = torch.float16,\n) -> torch.Tensor:\n return ops.cutlass_scaled_mm(\n A,\n B.T,\n out_dtype=output_dtype,\n scale_a=As,\n scale_b=Bs.T,\n )\n\n\n# TODO we should be able to change the type of block_size to GroupShape\n# after we resolve GroupShape compilation issue\n# https://github.com/vllm-project/vllm/issues/25270\ndef _w8a8_triton_block_scaled_mm_func(\n qx: torch.Tensor,\n weight: torch.Tensor,\n x_scale: torch.Tensor,\n weight_scale: torch.Tensor,\n block_size: list[int],\n output_dtype: torch.dtype,\n) -> torch.Tensor:\n return w8a8_triton_block_scaled_mm(\n qx, weight, x_scale, weight_scale, block_size, output_dtype\n )\n\n\ndef _w8a8_triton_block_scaled_mm_fake(\n qx: torch.Tensor,\n weight: torch.Tensor,\n x_scale: torch.Tensor,\n weight_scale: torch.Tensor,\n block_size: list[int],\n output_dtype: torch.dtype,\n) -> torch.Tensor:\n return torch.empty(\n (qx.size(0), weight.size(0)), dtype=output_dtype, device=qx.device\n )\n\n\ndirect_register_custom_op(\n \"w8a8_triton_block_scaled_mm_func\",\n _w8a8_triton_block_scaled_mm_func,\n fake_impl=_w8a8_triton_block_scaled_mm_fake,\n)\n\n\ndef _padded_cutlass(\n qx: torch.Tensor,\n weight: torch.Tensor,\n x_scale: torch.Tensor,\n weight_scale: torch.Tensor,\n block_size: list[int],\n output_dtype: torch.dtype,\n) -> torch.Tensor:\n pad_multiple = 4\n dim = qx.shape[0]\n padded = (\n dim if dim % pad_multiple == 0 else dim + pad_multiple - (dim % pad_multiple)\n )\n\n has_pad = padded > dim\n\n if has_pad:\n padded_shape = [padded, *qx.shape[1:]]\n padded_qx = torch.zeros(padded_shape, device=qx.device, dtype=qx.dtype)\n padded_qx[0 : qx.shape[0], ...].copy_(qx)\n\n padded_x_scale_shape = [*x_scale.shape[1:], padded]\n padded_x_scale = torch.ones(\n padded_x_scale_shape, device=x_scale.device, dtype=x_scale.dtype\n ).permute(-1, -2)\n padded_x_scale[0 : x_scale.shape[0], ...].copy_(x_scale)\n\n output = cutlass_scaled_mm(\n padded_qx, weight, padded_x_scale, weight_scale, block_size, output_dtype\n )\n return output[0 : qx.shape[0], ...]\n else:\n return cutlass_scaled_mm(\n qx, weight, x_scale, weight_scale, block_size, output_dtype\n )\n\n\ndef _padded_cutlass_fake(\n qx: torch.Tensor,\n weight: torch.Tensor,\n x_scale: torch.Tensor,\n weight_scale: torch.Tensor,\n block_size: list[int],\n output_dtype: torch.dtype,\n) -> torch.Tensor:\n return torch.empty(\n (qx.size(0), weight.size(0)), dtype=output_dtype, device=qx.device\n )\n\n\ndirect_register_custom_op(\n \"padded_cutlass\",\n _padded_cutlass,\n fake_impl=_padded_cutlass_fake,\n)\n\n\ndef _fp8_gemm_nt_op(\n q_input: torch.Tensor,\n input_scale: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n output: torch.Tensor,\n use_deep_gemm_e8m0: bool,\n) -> None:\n fp8_gemm_nt(\n (q_input, input_scale),\n (weight, weight_scale),\n output,\n is_deep_gemm_e8m0_used=use_deep_gemm_e8m0,\n )\n\n\ndef _fp8_gemm_nt_op_fake(\n q_input: torch.Tensor,\n input_scale: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n output: torch.Tensor,\n use_deep_gemm_e8m0: bool,\n) -> None:\n return None\n\n\ndirect_register_custom_op(\n \"fp8_gemm_nt_op\",\n _fp8_gemm_nt_op,\n mutates_args=[\"output\"],\n fake_impl=_fp8_gemm_nt_op_fake,\n)\n\n\n# TODO fix ROCm->Triton custom path:\n# https://github.com/vllm-project/vllm/issues/14397\nclass W8A8BlockFp8LinearOp:\n \"\"\"\n This class executes a Blocked FP8 linear layer using cutlass if supported\n and torch.scaled_mm otherwise.\n \"\"\"\n\n def __init__(\n self,\n weight_group_shape: GroupShape,\n act_quant_group_shape: GroupShape,\n cutlass_block_fp8_supported: bool = CUTLASS_BLOCK_FP8_SUPPORTED,\n use_aiter_and_is_supported: bool = False,\n ):\n self.weight_group_shape = weight_group_shape\n self.act_quant_group_shape = act_quant_group_shape\n self.is_deep_gemm_supported = is_deep_gemm_supported()\n self.is_hopper = current_platform.is_device_capability(90)\n self.use_deep_gemm_e8m0 = is_deep_gemm_e8m0_used()\n\n # Get the correct blockscale mul and input quant operations.\n # We can't use _dispatch_w8a8_blockscale_op to figure out if we want\n # to use deepgemm because we don't know the shape of weights (and\n # whether deepgemm supports it) at the init time.\n self.w8a8_blockscale_op, self.input_quant_op = (\n self._dispatch_w8a8_blockscale_op(\n cutlass_block_fp8_supported, use_aiter_and_is_supported\n )\n )\n self.deepgemm_input_quant_op = (\n QuantFP8(\n False,\n self.act_quant_group_shape,\n column_major_scales=True,\n use_ue8m0=self.use_deep_gemm_e8m0,\n )\n if self.is_deep_gemm_supported\n else None\n )\n\n def apply(\n self,\n input: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n input_scale: torch.Tensor | None = None,\n bias: torch.Tensor | None = None,\n ) -> torch.Tensor:\n assert input_scale is None\n # View input as 2D matrix for fp8 methods\n input_2d = input.view(-1, input.shape[-1])\n output_shape = [*input.shape[:-1], weight.shape[0]]\n output_dtype = input.dtype\n\n if should_use_deepgemm_for_fp8_linear(\n output_dtype, weight, self.is_deep_gemm_supported\n ):\n output = self._run_deepgemm(input_2d, weight, weight_scale)\n else:\n output = self.w8a8_blockscale_op(\n input_2d, weight, weight_scale, input_scale\n )\n\n if bias is not None:\n output = output + bias\n return output.to(dtype=input.dtype).view(*output_shape)\n\n def _run_deepgemm(\n self,\n input_2d: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n ) -> torch.Tensor:\n assert self.deepgemm_input_quant_op is not None\n q_input, input_scale = self.deepgemm_input_quant_op(input_2d)\n output = torch.empty(\n (q_input.shape[0], weight.shape[0]),\n dtype=torch.bfloat16,\n device=q_input.device,\n )\n torch.ops.vllm.fp8_gemm_nt_op(\n q_input, input_scale, weight, weight_scale, output, self.use_deep_gemm_e8m0\n )\n return output\n\n def _run_cutlass(\n self,\n input_2d: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n input_scale: torch.Tensor | None = None,\n ) -> torch.Tensor:\n assert input_scale is None\n assert self.input_quant_op is not None\n q_input, input_scale = self.input_quant_op(input_2d)\n if self.is_hopper:\n return torch.ops.vllm.padded_cutlass(\n q_input,\n weight,\n input_scale,\n weight_scale,\n list(self.weight_group_shape),\n input_2d.dtype,\n )\n else:\n return cutlass_scaled_mm(\n q_input,\n weight,\n input_scale,\n weight_scale,\n list(self.weight_group_shape),\n input_2d.dtype,\n )\n\n def _run_aiter(\n self,\n input_2d: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n input_scale: torch.Tensor | None = None,\n ) -> torch.Tensor:\n assert self.act_quant_group_shape == GroupShape(1, 128)\n\n n, k = weight.shape\n\n use_triton = (\n not current_platform.is_fp8_fnuz()\n and rocm_aiter_ops.is_triton_gemm_w8a8_tuned(n, k)\n )\n\n if use_triton:\n gemm_a8w8_blockscale_op = rocm_aiter_ops.triton_gemm_a8w8_blockscale\n else:\n gemm_a8w8_blockscale_op = rocm_aiter_ops.gemm_a8w8_blockscale\n\n if input_scale is not None:\n q_input = input_2d\n # MI350 case uses triton kernel\n elif use_triton:\n q_input, input_scale = per_token_group_quant_fp8(\n input_2d,\n self.act_quant_group_shape.col,\n column_major_scales=False,\n use_ue8m0=False,\n )\n # MI300 uses tuned AITER ASM/C++ kernel\n else:\n q_input, input_scale = rocm_aiter_ops.group_fp8_quant(input_2d)\n\n return gemm_a8w8_blockscale_op(\n q_input,\n weight,\n input_scale,\n weight_scale,\n list(self.weight_group_shape),\n output_dtype=input_2d.dtype,\n )\n\n def _run_triton(\n self,\n input_2d: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n input_scale: torch.Tensor | None = None,\n ) -> torch.Tensor:\n assert input_scale is None\n assert self.input_quant_op is not None\n q_input, input_scale = self.input_quant_op(input_2d)\n return torch.ops.vllm.w8a8_triton_block_scaled_mm_func(\n q_input,\n weight,\n input_scale,\n weight_scale,\n list(self.weight_group_shape),\n input_2d.dtype,\n )\n\n def _dispatch_w8a8_blockscale_op(\n self,\n use_cutlass: bool,\n use_aiter_and_is_supported: bool,\n ) -> tuple[\n Callable[\n [\n torch.Tensor,\n torch.Tensor,\n torch.Tensor,\n torch.Tensor | None,\n ],\n torch.Tensor,\n ],\n QuantFP8 | None,\n ]:\n if use_cutlass:\n return self._run_cutlass, (\n QuantFP8(\n False,\n self.act_quant_group_shape,\n column_major_scales=True,\n use_ue8m0=False,\n )\n )\n if use_aiter_and_is_supported:\n return self._run_aiter, None\n return self._run_triton, (\n QuantFP8(\n False,\n self.act_quant_group_shape,\n column_major_scales=False,\n use_ue8m0=False,\n )\n )\n\n\ndef input_to_float8(\n x: torch.Tensor, dtype: torch.dtype | None = None\n) -> tuple[torch.Tensor, torch.Tensor]:\n \"\"\"This function quantizes input values to float8 values \"\n \"with tensor-wise quantization.\"\"\"\n dtype = current_platform.fp8_dtype() if dtype is None else dtype\n finfo = torch.finfo(dtype)\n min_val, max_val = x.aminmax()\n amax = torch.maximum(min_val.abs(), max_val.abs()).clamp(min=1e-12)\n scale = finfo.max / amax\n x_scl_sat = (x * scale).clamp(min=finfo.min, max=finfo.max)\n return x_scl_sat.to(dtype).contiguous(), scale.float().reciprocal()\n\n\ndef block_quant_to_tensor_quant(\n x_q_block: torch.Tensor,\n x_s: torch.Tensor,\n) -> tuple[torch.Tensor, torch.Tensor]:\n \"\"\"This function converts block-wise quantization to tensor-wise\n quantization. The inputs are block-wise quantization tensor `x_q_block`,\n block-wise quantization scale and the block size.\n The outputs are tensor-wise quantization tensor and tensor-wise\n quantization scale. Note only float8 is supported for now.\n \"\"\"\n x_dq_block = group_broadcast(x_q_block, x_s)\n x_q_tensor, scale = input_to_float8(x_dq_block, dtype=x_q_block.dtype)\n return x_q_tensor, scale\n\n\n@triton.jit\ndef _per_token_group_quant_fp8(\n # Pointers to inputs and output\n y_ptr,\n y_q_ptr,\n y_s_ptr,\n group_size,\n # Num columns of y\n y_num_columns,\n y_row_stride,\n # Avoid to divide zero\n eps,\n # Information for float8\n fp8_min,\n fp8_max,\n use_ue8m0: tl.constexpr,\n # Meta-parameters\n BLOCK: tl.constexpr,\n):\n \"\"\"A Triton-accelerated function to perform per-token-group\n quantization on a tensor.\n This function converts the tensor values into float8 values.\n \"\"\"\n groups_per_row = y_num_columns // group_size\n\n # Map the program id to the row of X and Y it should compute.\n g_id = tl.program_id(0)\n row = g_id // groups_per_row\n row_g_id = g_id % groups_per_row\n\n # Ensure offset calculations use int64 to prevent overflow\n y_ptr_offset = (row.to(tl.int64) * y_row_stride) + (\n row_g_id.to(tl.int64) * group_size\n )\n y_ptr += y_ptr_offset\n\n y_q_ptr_offset = g_id.to(tl.int64) * group_size\n y_q_ptr += y_q_ptr_offset\n y_s_ptr += g_id\n\n cols = tl.arange(0, BLOCK) # N <= BLOCK\n mask = cols < group_size\n\n y = tl.load(y_ptr + cols, mask=mask, other=0.0).to(tl.float32)\n # Quant\n _absmax = tl.maximum(tl.max(tl.abs(y)), eps)\n scale_raw = _absmax / fp8_max\n y_s = tl.math.exp2(tl.ceil(tl.log2(scale_raw))) if use_ue8m0 else scale_raw\n y_q = tl.clamp(y / y_s, fp8_min, fp8_max).to(y_q_ptr.dtype.element_ty)\n\n tl.store(y_q_ptr + cols, y_q, mask=mask)\n tl.store(y_s_ptr, y_s)\n\n\n@triton.jit\ndef _silu_mul_per_token_group_quant_fp8_colmajor(\n y_ptr, # [M, N]\n y_q_ptr, # [M, N // 2]\n y_s_ptr, # [M, (N // 2) // GROUP_SIZE]\n M, # num tokens\n N, # intermediate size\n # Stride\n y_s_col_stride: tl.int64,\n # Information for float8\n eps,\n fp8_min,\n fp8_max,\n use_ue8m0: tl.constexpr,\n # Meta-parameters\n GROUP_SIZE: tl.constexpr,\n BLOCK_M: tl.constexpr,\n BLOCK_N: tl.constexpr,\n):\n # TODO(varun) : Add expert_ids so we may early-exit no-op thread blocks.\n \"\"\"\n Each thread block (BLOCK_N) computes [BLOCK_M, GROUP_SIZE] act-mul outputs. Then\n the thread block quantizes the [BLOCK_M, GROUP_SIZE] block of values and fills\n the outputs tensors at the right positions.\n \"\"\"\n\n pid_m = tl.program_id(0)\n pid_n = tl.program_id(1)\n N_2 = N // 2\n\n m_offset = pid_m * BLOCK_M\n n_offset = pid_n * BLOCK_N\n if m_offset >= M:\n return\n\n offs_n = tl.arange(0, BLOCK_N).to(tl.int64)\n offs_m = tl.arange(0, BLOCK_M).to(tl.int64)\n\n base_y_ptr = y_ptr + m_offset * N + n_offset\n\n act_in_ptrs = base_y_ptr + offs_m[:, None] * N + offs_n[None, :]\n\n act_in = tl.load(act_in_ptrs)\n mul_in = tl.load(act_in_ptrs + N_2)\n\n # silu & mul\n act_in = act_in.to(tl.float32)\n one_f32 = tl.cast(1, tl.float32)\n silu_out = (act_in / (one_f32 + tl.exp(-act_in))).to(y_ptr.dtype.element_ty)\n y = (silu_out * mul_in).to(tl.float32)\n\n # quant\n _absmax = tl.maximum(tl.max(tl.abs(y), axis=1), eps)\n scale_raw = _absmax / fp8_max\n y_s = tl.math.exp2(tl.ceil(tl.log2(scale_raw))) if use_ue8m0 else scale_raw\n y_s = tl.reshape(y_s, (BLOCK_M, 1))\n y_q = tl.clamp(y / y_s, fp8_min, fp8_max).to(y_q_ptr.dtype.element_ty)\n\n # store y_q\n base_y_q_ptr = y_q_ptr + m_offset * N_2 + n_offset\n y_q_ptrs = base_y_q_ptr + offs_m[:, None] * N_2 + offs_n[None, :]\n tl.store(y_q_ptrs, y_q)\n\n # store y_s\n group_id = n_offset // GROUP_SIZE\n base_y_s_ptr = y_s_ptr + group_id * y_s_col_stride + m_offset\n y_s_ptrs = base_y_s_ptr + offs_m\n y_s = tl.reshape(y_s, (BLOCK_M,))\n tl.store(y_s_ptrs, y_s)\n\n\ndef silu_mul_per_token_group_quant_fp8_colmajor(\n input: torch.Tensor, # [M, N]\n output: torch.Tensor | None = None, # [M, N // 2]\n use_ue8m0: bool | None = None,\n eps: float = 1e-10,\n):\n \"\"\"\n silu+mul + block-fp8 quant with group size 128.\n \"\"\"\n GROUP_SIZE = 128\n assert input.ndim == 2\n if output is not None:\n assert output.ndim == 2\n assert input.size(0) % GROUP_SIZE == 0\n assert input.size(1) % (GROUP_SIZE * 2) == 0\n\n if use_ue8m0 is None:\n use_ue8m0 = is_deep_gemm_e8m0_used()\n\n M, N = input.size()\n N_2 = N // 2\n\n if output is None:\n output = torch.empty((M, N_2), dtype=torch.float8_e4m3fn, device=input.device)\n\n output_scales = torch.empty(\n ((N_2 // GROUP_SIZE), M), dtype=torch.float32, device=input.device\n ).transpose(0, 1)\n\n BLOCK_M = 8\n BLOCK_N = GROUP_SIZE\n assert M % BLOCK_M == 0\n assert N_2 % BLOCK_N == 0\n\n finfo = torch.finfo(torch.float8_e4m3fn)\n fp8_min = finfo.min\n fp8_max = finfo.max\n\n # Force even division so we can avoid edgecases within the kernel.\n assert M % BLOCK_M == 0\n assert N_2 % BLOCK_N == 0\n grid = (M // BLOCK_M, N_2 // BLOCK_N)\n\n _silu_mul_per_token_group_quant_fp8_colmajor[grid](\n input,\n output,\n output_scales,\n M,\n N,\n output_scales.stride(-1),\n eps,\n fp8_min,\n fp8_max,\n use_ue8m0,\n GROUP_SIZE,\n BLOCK_M,\n BLOCK_N,\n )\n\n return output, output_scales\n\n\n@triton.jit\ndef _per_token_group_quant_fp8_colmajor(\n # Pointers to inputs and output\n y_ptr,\n y_q_ptr,\n y_s_ptr,\n group_size,\n # Num columns of y\n y_num_columns,\n y_row_stride,\n # Stride from one column to the next of y_s\n y_s_col_stride,\n # Avoid to divide zero\n eps,\n # Information for float8\n fp8_min,\n fp8_max,\n use_ue8m0: tl.constexpr,\n # Meta-parameters\n BLOCK: tl.constexpr,\n):\n \"\"\"A Triton-accelerated function to perform per-token-group\n quantization on a tensor.\n This function converts the tensor values into float8 values.\n \"\"\"\n groups_per_row = y_num_columns // group_size\n\n # Map the program id to the row of X and Y it should compute.\n g_id = tl.program_id(0)\n row = g_id // groups_per_row\n row_g_id = g_id % groups_per_row\n\n # Ensure offset calculations use int64 to prevent overflow\n y_ptr_offset = (row.to(tl.int64) * y_row_stride) + (\n row_g_id.to(tl.int64) * group_size\n )\n y_ptr += y_ptr_offset\n\n y_q_ptr_offset = g_id.to(tl.int64) * group_size\n y_q_ptr += y_q_ptr_offset\n\n # Convert g_id the flattened block coordinate to 2D so we can index\n # into the output y_scales matrix\n blocks_per_row = y_num_columns // group_size\n scale_col = g_id % blocks_per_row\n scale_row = g_id // blocks_per_row\n # Ensure offset calculation uses int64 for y_s_ptr\n y_s_ptr_offset = (scale_col.to(tl.int64) * y_s_col_stride) + scale_row.to(tl.int64)\n y_s_ptr += y_s_ptr_offset\n\n cols = tl.arange(0, BLOCK) # group_size <= BLOCK\n mask = cols < group_size\n\n y = tl.load(y_ptr + cols, mask=mask, other=0.0).to(tl.float32)\n # Quant\n _absmax = tl.maximum(tl.max(tl.abs(y)), eps)\n scale_raw = _absmax / fp8_max\n y_s = tl.math.exp2(tl.ceil(tl.log2(scale_raw))) if use_ue8m0 else scale_raw\n y_q = tl.clamp(y / y_s, fp8_min, fp8_max).to(y_q_ptr.dtype.element_ty)\n\n tl.store(y_q_ptr + cols, y_q, mask=mask)\n tl.store(y_s_ptr, y_s)\n\n\ndef per_token_group_quant_fp8(\n x: torch.Tensor,\n group_size: int,\n eps: float = 1e-10,\n dtype: torch.dtype | None = None,\n column_major_scales: bool = False,\n out_q: torch.Tensor | None = None,\n use_ue8m0: bool | None = None,\n) -> tuple[torch.Tensor, torch.Tensor]:\n \"\"\"Function to perform per-token-group quantization on an input tensor `x`.\n It converts the tensor values into signed float8 values and returns the\n quantized tensor along with the scaling factor used for quantization.\n Args:\n x: The input tensor with ndim >= 2.\n group_size: The group size used for quantization.\n eps: The minimum to avoid dividing zero.\n dtype: The dype of output tensor. Note that only `torch.float8_e4m3fn`\n is supported for now.\n column_major_scales: Outputs scales in column major.\n out_q: Optional output tensor. If not provided, function will create.\n Returns:\n tuple[torch.Tensor, torch.Tensor]: The quantized tensor and the\n scaling factor.\n \"\"\"\n if use_ue8m0 is None:\n use_ue8m0 = is_deep_gemm_e8m0_used()\n dtype = current_platform.fp8_dtype() if dtype is None else dtype\n assert x.shape[-1] % group_size == 0, (\n f\"the last dimension of `x` {x.shape[-1]} must be divisible \"\n f\"by `group_size` {group_size}\"\n )\n assert x.stride(-1) == 1, \"`x` groups must be contiguous\"\n\n finfo = torch.finfo(dtype)\n fp8_min = finfo.min\n fp8_max = finfo.max\n\n assert out_q is None or out_q.shape == x.shape\n x_q = out_q\n if x_q is None:\n x_q = torch.empty_like(x, device=x.device, dtype=dtype)\n\n # Allocate the scale tensor in either row- or column-major format.\n if column_major_scales:\n shape = (x.shape[-1] // group_size,) + x.shape[:-1]\n x_s = torch.empty(shape, device=x.device, dtype=torch.float32).permute(-1, -2)\n else:\n shape = x.shape[:-1] + (x.shape[-1] // group_size,)\n x_s = torch.empty(shape, device=x.device, dtype=torch.float32)\n\n # prefer CUDA kernel if available\n # TODO(bnell): this causes some fp8 moe test to fail.\n if current_platform.is_cuda() and x.is_contiguous():\n torch.ops._C.per_token_group_fp8_quant(\n x, x_q, x_s, group_size, eps, fp8_min, fp8_max, use_ue8m0\n )\n return x_q, x_s\n\n # TRITON FALLBACK\n M = x.numel() // group_size\n N = group_size\n BLOCK = triton.next_power_of_2(N)\n # heuristics for number of warps\n num_warps = min(max(BLOCK // 256, 1), 8)\n num_stages = 1\n if column_major_scales:\n _per_token_group_quant_fp8_colmajor[(M,)](\n x,\n x_q,\n x_s,\n group_size,\n x.shape[1],\n x.stride(0),\n x_s.stride(1),\n eps,\n fp8_min=fp8_min,\n fp8_max=fp8_max,\n use_ue8m0=use_ue8m0,\n BLOCK=BLOCK,\n num_warps=num_warps,\n num_stages=num_stages,\n )\n else:\n _per_token_group_quant_fp8[(M,)](\n x,\n x_q,\n x_s,\n group_size,\n x.shape[1],\n x.stride(0),\n eps,\n fp8_min=fp8_min,\n fp8_max=fp8_max,\n use_ue8m0=use_ue8m0,\n BLOCK=BLOCK,\n num_warps=num_warps,\n num_stages=num_stages,\n )\n\n return x_q, x_s\n\n\n@triton.jit\ndef _w8a8_triton_block_scaled_mm(\n # Pointers to inputs and output\n A,\n B,\n C,\n As,\n Bs,\n # Shape for matmul\n M,\n N,\n K,\n # Block size for block-wise quantization\n group_n,\n group_k,\n # Stride for inputs and output\n stride_am,\n stride_ak,\n stride_bk,\n stride_bn,\n stride_cm,\n stride_cn,\n stride_As_m,\n stride_As_k,\n stride_Bs_k,\n stride_Bs_n,\n # Meta-parameters\n BLOCK_SIZE_M: tl.constexpr,\n BLOCK_SIZE_N: tl.constexpr,\n BLOCK_SIZE_K: tl.constexpr,\n GROUP_SIZE_M: tl.constexpr,\n):\n \"\"\"Triton-accelerated function used to perform linear operations (dot\n product) on input tensors `A` and `B` with block-wise quantization, and\n store the result in output tensor `C`.\n \"\"\"\n\n pid = tl.program_id(axis=0)\n num_pid_m = tl.cdiv(M, BLOCK_SIZE_M)\n num_pid_n = tl.cdiv(N, BLOCK_SIZE_N)\n num_pid_in_group = GROUP_SIZE_M * num_pid_n\n group_id = pid // num_pid_in_group\n first_pid_m = group_id * GROUP_SIZE_M\n group_size_m = min(num_pid_m - first_pid_m, GROUP_SIZE_M)\n pid_m = first_pid_m + (pid % group_size_m)\n pid_n = (pid % num_pid_in_group) // group_size_m\n\n offs_am = (pid_m * BLOCK_SIZE_M + tl.arange(0, BLOCK_SIZE_M)) % M\n offs_bn = (pid_n * BLOCK_SIZE_N + tl.arange(0, BLOCK_SIZE_N)) % N\n offs_k = tl.arange(0, BLOCK_SIZE_K)\n a_ptrs = A + (offs_am[:, None] * stride_am + offs_k[None, :] * stride_ak)\n b_ptrs = B + (offs_k[:, None] * stride_bk + offs_bn[None, :] * stride_bn)\n\n As_ptrs = As + offs_am * stride_As_m\n offs_bsn = offs_bn // group_n\n Bs_ptrs = Bs + offs_bsn * stride_Bs_n\n\n accumulator = tl.zeros((BLOCK_SIZE_M, BLOCK_SIZE_N), dtype=tl.float32)\n for k in range(0, tl.cdiv(K, BLOCK_SIZE_K)):\n a = tl.load(a_ptrs, mask=offs_k[None, :] < K - k * BLOCK_SIZE_K, other=0.0)\n b = tl.load(b_ptrs, mask=offs_k[:, None] < K - k * BLOCK_SIZE_K, other=0.0)\n\n k_start = k * BLOCK_SIZE_K\n offs_ks = k_start // group_k\n a_s = tl.load(As_ptrs + offs_ks * stride_As_k)\n b_s = tl.load(Bs_ptrs + offs_ks * stride_Bs_k)\n\n accumulator += tl.dot(a, b) * a_s[:, None] * b_s[None, :]\n a_ptrs += BLOCK_SIZE_K * stride_ak\n b_ptrs += BLOCK_SIZE_K * stride_bk\n\n if C.dtype.element_ty == tl.bfloat16:\n c = accumulator.to(tl.bfloat16)\n elif C.dtype.element_ty == tl.float16:\n c = accumulator.to(tl.float16)\n else:\n c = accumulator.to(tl.float32)\n\n offs_cm = pid_m * BLOCK_SIZE_M + tl.arange(0, BLOCK_SIZE_M)\n offs_cn = pid_n * BLOCK_SIZE_N + tl.arange(0, BLOCK_SIZE_N)\n c_ptrs = C + stride_cm * offs_cm[:, None] + stride_cn * offs_cn[None, :]\n c_mask = (offs_cm[:, None] < M) & (offs_cn[None, :] < N)\n tl.store(c_ptrs, c, mask=c_mask)\n\n\n@functools.lru_cache\ndef get_w8a8_block_fp8_configs(\n N: int, K: int, block_n: int, block_k: int\n) -> dict[int, Any] | None:\n \"\"\"\n Return optimized configurations for the w8a8 block fp8 kernel.\n The return value will be a dictionary that maps an irregular grid of\n batch sizes to configurations of the w8a8 block fp8 kernel. To evaluate the\n kernel on a given batch size bs, the closest batch size in the grid should\n be picked and the associated configuration chosen to invoke the kernel.\n \"\"\"\n\n # First look up if an optimized configuration is available in the configs\n # directory\n device_name = current_platform.get_device_name().replace(\" \", \"_\")\n json_file_name = f\"N={N},K={K},device_name={device_name},dtype=fp8_w8a8,block_shape=[{block_n},{block_k}].json\" # noqa: E501\n\n config_file_path = os.path.join(\n os.path.dirname(os.path.realpath(__file__)), \"configs\", json_file_name\n )\n if os.path.exists(config_file_path):\n with open(config_file_path) as f:\n logger.info(\n \"Using configuration from %s for W8A8 Block FP8 kernel.\",\n config_file_path,\n )\n # If a configuration has been found, return it\n return {int(key): val for key, val in json.load(f).items()}\n\n # If no optimized configuration is available, we will use the default\n # configuration\n logger.warning(\n \"Using default W8A8 Block FP8 kernel config. Performance might \"\n \"be sub-optimal! Config file not found at %s\",\n config_file_path,\n )\n return None\n\n\ndef w8a8_triton_block_scaled_mm(\n A: torch.Tensor,\n B: torch.Tensor,\n As: torch.Tensor,\n Bs: torch.Tensor,\n block_size: list[int],\n output_dtype: torch.dtype = torch.float16,\n) -> torch.Tensor:\n \"\"\"This function performs matrix multiplication with block-wise\n quantization.\n It takes two input tensors `A` and `B` with scales `As` and `Bs`.\n The output is returned in the specified `output_dtype`.\n Args:\n A: The input tensor, e.g., activation.\n B: The input tensor, e.g., weight.\n As: The per-token-group quantization scale for `A`.\n Bs: The per-block quantization scale for `B`.\n block_size: The block size for per-block quantization. It should\n be 2-dim, e.g., [128, 128].\n output_dytpe: The dtype of the returned tensor.\n Returns:\n torch.Tensor: The result of matmul.\n \"\"\"\n assert len(block_size) == 2\n block_n, block_k = block_size[0], block_size[1]\n\n assert A.shape[-1] == B.shape[-1]\n assert A.shape[:-1] == As.shape[:-1] and A.is_contiguous()\n assert triton.cdiv(A.shape[-1], block_k) == As.shape[-1]\n M = A.numel() // A.shape[-1]\n\n assert B.ndim == 2 and Bs.ndim == 2\n N, K = B.shape\n assert triton.cdiv(N, block_n) == Bs.shape[0]\n assert triton.cdiv(K, block_k) == Bs.shape[1]\n\n C_shape = A.shape[:-1] + (N,)\n C = A.new_empty(C_shape, dtype=output_dtype)\n\n configs = get_w8a8_block_fp8_configs(N, K, block_size[0], block_size[1])\n if configs:\n # Get the optimal config if there is one\n config = configs[min(configs.keys(), key=lambda x: abs(x - M))]\n else:\n # Default config\n # Block-wise quant: BLOCK_SIZE_N must be divisible by block_size[0]\n # BLOCK_SIZE_K must be divisible by block_size[1]\n config = {\n \"BLOCK_SIZE_M\": 64,\n \"BLOCK_SIZE_N\": block_size[0],\n \"BLOCK_SIZE_K\": block_size[1],\n \"GROUP_SIZE_M\": 32,\n \"num_warps\": 4,\n \"num_stages\": 2,\n }\n\n def grid(META):\n return (\n triton.cdiv(M, META[\"BLOCK_SIZE_M\"]) * triton.cdiv(N, META[\"BLOCK_SIZE_N\"]),\n )\n\n _w8a8_triton_block_scaled_mm[grid](\n A,\n B,\n C,\n As,\n Bs,\n M,\n N,\n K,\n block_n,\n block_k,\n A.stride(-2),\n A.stride(-1),\n B.stride(1),\n B.stride(0),\n C.stride(-2),\n C.stride(-1),\n As.stride(-2),\n As.stride(-1),\n Bs.stride(1),\n Bs.stride(0),\n **config,\n )\n\n return C\n\n\ndef requant_weight_ue8m0_inplace(\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n block_size: Sequence[int] = (128, 128),\n) -> None:\n \"\"\"Re-quantise *weight* so that its per-block scaling factors are in the\n UE8M0 (power-of-two) format expected by the new DeepGEMM kernels inplace.\n\n Args:\n weight: Block-quantised weight tensor stored in `torch.float8_e4m3fn`.\n Expected shape `(..., M, K)`.\n weight_scale: Corresponding per-block scale tensor (`torch.float32`)\n with shape `(..., M // block_size[0], K // block_size[1])`.\n block_size: 2-element iterable `[block_m, block_k]` describing the\n block quantisation granularity.\n \"\"\"\n if weight.numel() == 0:\n return\n\n if weight.dtype != torch.float8_e4m3fn:\n raise ValueError(\n f\"Expected *weight* to be torch.float8_e4m3fn, got {weight.dtype} instead.\"\n )\n\n from vllm.utils.deep_gemm import per_block_cast_to_fp8\n\n block_m, block_k = int(block_size[0]), int(block_size[1])\n\n # Flatten leading dimensions so we can iterate over the last two dims.\n leading_shape = weight.shape[:-2]\n if len(leading_shape) == 0:\n w_view = weight.unsqueeze(0)\n s_view = weight_scale.unsqueeze(0)\n else:\n w_view = weight.reshape(-1, weight.shape[-2], weight.shape[-1])\n s_view = weight_scale.reshape(-1, *weight_scale.shape[-2:])\n\n num_mats = w_view.size(0)\n for idx in range(num_mats):\n w_q = w_view[idx]\n s_old = s_view[idx]\n\n # De-quantise with the *old* scaling factors (float32).\n m_cur, k_cur = w_q.shape\n s_float = s_old.to(torch.float32)\n # Expand scales along rows and cols by block size, then crop.\n s_exp_r = torch.repeat_interleave(s_float, block_m, dim=0)\n s_exp = torch.repeat_interleave(s_exp_r, block_k, dim=1)\n s_exp = s_exp[:m_cur, :k_cur]\n w_dq = w_q.to(torch.float32) * s_exp\n # Re-quantise using power-of-two scaling (UE8M0).\n w_requant, s_requant = per_block_cast_to_fp8(\n w_dq, [block_m, block_k], use_ue8m0=True\n )\n\n # Write back the results in-place.\n w_q.copy_(w_requant)\n s_old.copy_(s_requant)\n\n\ndef deepgemm_post_process_fp8_weight_block(\n wq: torch.Tensor, ws: torch.Tensor, quant_block_shape: tuple[int], use_e8m0: bool\n) -> tuple[torch.Tensor, torch.Tensor]:\n assert wq.dtype == torch.float8_e4m3fn, (\n \"Expected quantized tensor dtype \"\n f\"to be torch.float8_e4m3fn, got {wq.dtype} instead.\"\n )\n assert ws.dtype == torch.float32, (\n f\"Expected tensor scales dtype to be torch.float32, got {ws.dtype} instead\"\n )\n\n if use_e8m0:\n requant_weight_ue8m0_inplace(wq, ws, block_size=quant_block_shape)\n\n original_ndim = wq.ndim\n if wq.ndim == 2:\n assert ws.ndim == 2\n wq = wq.unsqueeze(0)\n ws = ws.unsqueeze(0)\n\n # From https://github.com/deepseek-ai/DeepGEMM/blob/c9f8b34dcdacc20aa746b786f983492c51072870/csrc/utils/layout.hpp#L46\n recipe = (1, 128, 128)\n\n # Ref : https://github.com/deepseek-ai/DeepGEMM/blob/c9f8b34dcdacc20aa746b786f983492c51072870/csrc/apis/gemm.hpp\n # DeepGemm uses the `transform_sf_into_required_layout` function to\n # represent scales in the correct format.\n dg_ws = transform_sf_into_required_layout(\n sf=ws,\n mn=wq.size(1),\n k=wq.size(2),\n recipe=recipe,\n num_groups=wq.size(0),\n # is the scale factors for A in (Refers to the argument A in A @ B).\n # Weights are B.\n is_sfa=False,\n )\n\n if original_ndim == 2:\n wq = wq.squeeze(0)\n dg_ws = dg_ws.squeeze(0)\n\n return wq, dg_ws\n\n\ndef _maybe_pad_fp8_weight(weight: torch.Tensor) -> torch.Tensor:\n \"\"\"Pad the weight tensor. This is an optimization on ROCm platform, which\n can benefit from tensors located far enough from one another in memory\"\"\"\n if (\n envs.VLLM_ROCM_FP8_PADDING\n and current_platform.is_rocm()\n and weight.stride(-1) == 1\n and (weight.stride(-2) * weight.element_size()) % 512 == 0\n ):\n num_pad = 256 // weight.element_size()\n import torch.nn.functional as F\n\n weight = F.pad(weight, (0, num_pad), \"constant\", 0)[..., :-num_pad]\n torch.cuda.empty_cache()\n return weight\n\n\ndef validate_fp8_block_shape(\n layer: torch.nn.Module,\n input_size: int,\n output_size: int,\n input_size_per_partition: int,\n output_partition_sizes: list[int],\n block_size: list[int],\n) -> None:\n \"\"\"Validate block quantization shapes for tensor parallelism.\"\"\"\n from vllm.distributed import get_tensor_model_parallel_world_size\n\n tp_size = getattr(layer, \"tp_size\", get_tensor_model_parallel_world_size())\n block_n, block_k = block_size[0], block_size[1]\n\n # Required by row parallel\n if (\n tp_size > 1\n and input_size // input_size_per_partition == tp_size\n and input_size_per_partition % block_k != 0\n ):\n raise ValueError(\n f\"Weight input_size_per_partition = {input_size_per_partition} \"\n f\"is not divisible by weight quantization block_k = {block_k}.\"\n )\n\n # Required by column parallel or enabling merged weights\n is_tp_split = tp_size > 1 and output_size // sum(output_partition_sizes) == tp_size\n is_merged_gemm = len(output_partition_sizes) > 1\n if is_tp_split or is_merged_gemm:\n sizes_to_check = output_partition_sizes\n if not is_tp_split and is_merged_gemm:\n # In case of merged matrices, we allow the last\n # matrix to not be a multiple of block size\n sizes_to_check = output_partition_sizes[:-1]\n for output_partition_size in sizes_to_check:\n if output_partition_size % block_n != 0:\n raise ValueError(\n f\"Weight output_partition_size = \"\n f\"{output_partition_size} is not divisible by \"\n f\"weight quantization block_n = {block_n}.\"\n )\n\n\ndef create_fp8_weight_parameter(\n output_size_per_partition: int,\n input_size_per_partition: int,\n weight_loader: Callable | None,\n) -> torch.nn.Parameter:\n \"\"\"Create FP8 weight parameter.\"\"\"\n from vllm.model_executor.parameter import ModelWeightParameter\n\n return ModelWeightParameter(\n data=torch.empty(\n output_size_per_partition,\n input_size_per_partition,\n dtype=torch.float8_e4m3fn,\n ),\n input_dim=1,\n output_dim=0,\n weight_loader=weight_loader,\n )\n\n\ndef create_fp8_scale_parameter(\n parameter_type: torch.nn.Parameter,\n output_partition_sizes: list[int],\n input_size_per_partition: int,\n block_size: list[int] | None,\n weight_loader: Callable | None,\n) -> torch.nn.Parameter:\n \"\"\"Create scale parameter based on quantization strategy.\"\"\"\n if parameter_type == ChannelQuantScaleParameter:\n scale = parameter_type(\n data=torch.empty((sum(output_partition_sizes), 1), dtype=torch.float32),\n output_dim=0,\n weight_loader=weight_loader,\n )\n elif parameter_type == BlockQuantScaleParameter:\n assert block_size is not None\n block_n, block_k = block_size[0], block_size[1]\n output_size_per_partition = sum(output_partition_sizes)\n scale = parameter_type(\n data=torch.empty(\n (output_size_per_partition + block_n - 1) // block_n,\n (input_size_per_partition + block_k - 1) // block_k,\n dtype=torch.float32,\n ),\n input_dim=1,\n output_dim=0,\n weight_loader=weight_loader,\n )\n elif parameter_type == PerTensorScaleParameter:\n scale = parameter_type(\n data=torch.empty(len(output_partition_sizes), dtype=torch.float32),\n weight_loader=weight_loader,\n )\n else:\n raise ValueError(f\"Unknown parameter type: {parameter_type}\")\n\n scale[:] = torch.finfo(torch.float32).min\n return scale\n\n\ndef create_fp8_input_scale(\n output_partition_sizes: list[int], weight_loader: Callable | None\n) -> torch.nn.Parameter:\n \"\"\"Create input scale parameter for static activation quantization.\"\"\"\n from vllm.model_executor.parameter import PerTensorScaleParameter\n\n scale = PerTensorScaleParameter(\n data=torch.empty(len(output_partition_sizes), dtype=torch.float32),\n weight_loader=weight_loader,\n )\n scale[:] = torch.finfo(torch.float32).min\n return scale\n\n\ndef process_fp8_weight_tensor_strategy(\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n logical_widths: list[int],\n input_scale: torch.Tensor | None = None,\n) -> tuple[torch.Tensor, torch.Tensor, torch.Tensor | None]:\n \"\"\"Process weights for tensor-wise quantization strategy.\"\"\"\n from vllm.model_executor.layers.quantization.utils.w8a8_utils import (\n normalize_e4m3fn_to_e4m3fnuz,\n requantize_with_max_scale,\n )\n\n if current_platform.is_fp8_fnuz():\n weight, weight_scale, input_scale = normalize_e4m3fn_to_e4m3fnuz(\n weight=weight, weight_scale=weight_scale, input_scale=input_scale\n )\n\n # Requantize with max scale\n weight_scale, weight = requantize_with_max_scale(\n weight=weight,\n weight_scale=weight_scale,\n logical_widths=logical_widths,\n )\n\n weight = _maybe_pad_fp8_weight(weight)\n return weight, weight_scale, input_scale\n\n\ndef process_fp8_weight_channel_strategy(\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n input_scale: torch.Tensor | None = None,\n) -> tuple[torch.Tensor, torch.Tensor, torch.Tensor | None]:\n \"\"\"Process weights for channel-wise quantization strategy.\"\"\"\n from vllm.model_executor.layers.quantization.utils.w8a8_utils import (\n normalize_e4m3fn_to_e4m3fnuz,\n )\n\n if current_platform.is_fp8_fnuz():\n weight, weight_scale, input_scale = normalize_e4m3fn_to_e4m3fnuz(\n weight=weight, weight_scale=weight_scale, input_scale=input_scale\n )\n\n return weight, weight_scale, input_scale\n\n\ndef process_fp8_weight_block_strategy(\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n) -> tuple[torch.Tensor, torch.Tensor]:\n \"\"\"Process weights for block-wise quantization strategy.\"\"\"\n from vllm.model_executor.layers.quantization.utils.w8a8_utils import (\n normalize_e4m3fn_to_e4m3fnuz,\n )\n\n if current_platform.is_fp8_fnuz():\n weight, weight_scale, _ = normalize_e4m3fn_to_e4m3fnuz(\n weight=weight, weight_scale=weight_scale\n )\n\n weight = _maybe_pad_fp8_weight(weight)\n return weight, weight_scale\n\n\ndef maybe_post_process_fp8_weight_block(layer: torch.nn.Module):\n assert layer.weight_block_size is not None\n\n from vllm.utils.deep_gemm import (\n is_deep_gemm_e8m0_used,\n should_use_deepgemm_for_fp8_linear,\n )\n\n # On Blackwell or Hopper, if E8M0 for DeepGemm is used, we need to\n # requantize the weight and input to the specific scale\n # at the same time.\n should_use_deepgemm = should_use_deepgemm_for_fp8_linear(\n layer.orig_dtype, layer.weight\n )\n if should_use_deepgemm:\n dg_weight, dg_weight_scale = deepgemm_post_process_fp8_weight_block(\n wq=layer.weight.data,\n ws=layer.weight_scale.data,\n quant_block_shape=tuple(layer.weight_block_size),\n use_e8m0=is_deep_gemm_e8m0_used(),\n )\n layer.weight = torch.nn.Parameter(dg_weight, requires_grad=False)\n layer.weight_scale = torch.nn.Parameter(dg_weight_scale, requires_grad=False)\n\n\ndef expert_weight_is_col_major(x: torch.Tensor) -> bool:\n assert x.dim() == 3\n b, m, n = x.shape\n return x.stride(0) == m * n and x.stride(1) == 1 and x.stride(2) == m\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## Purpose\n\nFused layout transform with per token group quant to get performance\n\nNamely, pack scales into a uint32 earlier and remove an additional kernel call\n\n## Test\n\n`vllm serve deepseek-ai/DeepSeek-V3.1 -tp 8 --enable-expert-parallel --port 9256 --enforce_eager`\n\n### Acc\n\n`lm_eval --model local-completions --model_args \"base_url=http://127.0.0.1:9256/v1/completions,model=deepseek-ai/DeepSeek-V3.1,num_concurrent=1024\" --tasks gsm8k`\n\n```bash\n|Tasks|Version| Filter |n-shot| Metric | |Value | |Stderr|\n|-----|------:|----------------|-----:|-----------|---|-----:|---|-----:|\n|gsm8k| 3|flexible-extract| 5|exact_match|↑ |0.9568|± |0.0056|\n| | |strict-match | 5|exact_match|↑ |0.9568|± |0.0056|\n```\n\n### Perf\n\n`vllm bench serve --model deepseek-ai/DeepSeek-V3.1 --dataset-name random --host 127.0.0.1 --port 9256 --random-input-len 2 --random-output-len 256 --request-rate inf --num-prompts 1024`\n\n```bash\nNow\n============ Serving Benchmark Result ============\nSuccessful requests: 1024 \nFailed requests: 0 \nBenchmark duration (s): 27.94 \nTotal input tokens: 3072 \nTotal generated tokens: 262144 \nRequest throughput (req/s): 36.65 \nOutput token throughput (tok/s): 9382.68 \nPeak output token throughput (tok/s): 10240.00 \nPeak concurrent requests: 1024.00 \nTotal Token throughput (tok/s): 9492.63 \n---------------Time to First Token----------------\nMean TTFT (ms): 1013.22 \nMedian TTFT (ms): 982.19 \nP99 TTFT (ms): 1157.11 \n-----Time per Output Token (excl. 1st token)------\nMean TPOT (ms): 105.02 \nMedian TPOT (ms): 105.08 \nP99 TPOT (ms): 105.26 \n---------------Inter-token Latency----------------\nMean ITL (ms): 105.02 \nMedian ITL (ms): 104.57 \nP99 ITL (ms): 131.10 \n==================================================\n\nMain\n============ Serving Benchmark Result ============\nSuccessful requests: 1024 \nFailed requests: 0 \nBenchmark duration (s): 29.15 \nTotal input tokens: 3072 \nTotal generated tokens: 262144 \nRequest throughput (req/s): 35.13 \nOutput token throughput (tok/s): 8994.31 \nPeak output token throughput (tok/s): 10132.00 \nPeak concurrent requests: 1024.00 \nTotal Token throughput (tok/s): 9099.71 \n---------------Time to First Token----------------\nMean TTFT (ms): 1121.89 \nMedian TTFT (ms): 1144.56 \nP99 TTFT (ms): 1241.25 \n-----Time per Output Token (excl. 1st token)------\nMean TPOT (ms): 109.30 \nMedian TPOT (ms): 109.29 \nP99 TPOT (ms): 109.40 \n---------------Inter-token Latency----------------\nMean ITL (ms): 109.30 \nMedian ITL (ms): 108.89 \nP99 ITL (ms): 125.29 \n==================================================\n```\n\n\n"},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":393,"cells":{"repo":{"kind":"string","value":"vllm"},"commit":{"kind":"string","value":"879ddb09c3b7b5a21f75e46ded148ce70f1c486e"},"date":{"kind":"string","value":"2025-12-07T17:58:47+08:00"},"pr_number":{"kind":"number","value":29642,"string":"29,642"},"pr_url":{"kind":"string","value":"https://github.com/vllm-project/vllm/pull/29642"},"title":{"kind":"string","value":"[Kernel][MoE] optimize `moe_align_block_size` (#29642)"},"message":{"kind":"string","value":"[Kernel][MoE] optimize `moe_align_block_size` (#29642)\n\nSigned-off-by: Jinzhen Lin <jinzhen.ljz@antgroup.com>\nCo-authored-by: Jee Jee Li <pandaleefree@gmail.com>"},"path":{"kind":"string","value":"csrc/moe/moe_align_sum_kernels.cu"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"#include <torch/all.h>\n#include <ATen/cuda/CUDAContext.h>\n#include <c10/cuda/CUDAGuard.h>\n#include <cub/cub.cuh>\n\n#include <ATen/ATen.h>\n#include <ATen/cuda/Atomic.cuh>\n\n#include \"../cuda_compat.h\"\n#include \"../dispatch_utils.h\"\n#include \"core/math.hpp\"\n\n#define CEILDIV(x, y) (((x) + (y) - 1) / (y))\n\nnamespace vllm {\nnamespace moe {\n\nnamespace batched_moe_align_block_size {\n\n// Note num_threads needs to be 1024 for BlockScan Reduction in the kernel.\nstatic constexpr int32_t num_threads = 1024;\nstatic constexpr int32_t num_blocks = 1;\n__global__ void batched_moe_align_block_size_kernel(\n int32_t const num_batches, int32_t const max_tokens_per_batch,\n int32_t const block_size, int32_t const* __restrict__ batch_num_tokens,\n int32_t* __restrict__ sorted_ids, int32_t* __restrict__ block_ids,\n int32_t* __restrict__ num_tokens_post_pad) {\n // TODO(varun): This is a naive implementation. Could be optimized.\n\n size_t const batch_id = threadIdx.x;\n size_t const stride = blockDim.x * gridDim.x;\n int32_t const num_blocks_per_batch =\n CEILDIV(max_tokens_per_batch, block_size);\n int32_t const sorted_ids_size =\n num_blocks_per_batch * num_batches * block_size;\n int32_t const block_ids_size = sorted_ids_size / block_size;\n int32_t const SENTINEL =\n num_batches * max_tokens_per_batch; // To denote invalid entries.\n // Intialize sorted_ids\n for (size_t i = threadIdx.x; i < sorted_ids_size; i += stride) {\n sorted_ids[i] = SENTINEL;\n }\n // Intialize expert_ids with -1\n for (size_t i = threadIdx.x; i < block_ids_size; i += stride) {\n block_ids[i] = -1;\n }\n\n int32_t b_num_tokens = 0;\n if (batch_id < num_batches) {\n b_num_tokens = batch_num_tokens[batch_id];\n }\n int32_t const ceil_b_num_tokens =\n CEILDIV(b_num_tokens, block_size) * block_size;\n\n // Compute prefix sum over token counts per expert\n using BlockScan = cub::BlockScan<int32_t, 1024>;\n __shared__ typename BlockScan::TempStorage temp_storage;\n int cumsum_val;\n BlockScan(temp_storage).ExclusiveSum(ceil_b_num_tokens, cumsum_val);\n __syncthreads();\n\n bool const is_last_batch = batch_id == (num_batches - 1);\n if (is_last_batch) {\n *num_tokens_post_pad = cumsum_val + ceil_b_num_tokens;\n }\n\n if (batch_id < num_batches) {\n int32_t const batch_offset = batch_id * max_tokens_per_batch;\n for (size_t i = 0; i < b_num_tokens; ++i) {\n sorted_ids[cumsum_val + i] = batch_offset + i;\n }\n\n int32_t const block_start = cumsum_val / block_size;\n int32_t const num_blocks = ceil_b_num_tokens / block_size;\n for (size_t i = 0; i < num_blocks; ++i) {\n block_ids[block_start + i] = batch_id;\n }\n }\n}\n} // namespace batched_moe_align_block_size\n\ntemplate <typename scalar_t>\n__global__ void moe_align_block_size_kernel(\n const scalar_t* __restrict__ topk_ids,\n int32_t* __restrict__ sorted_token_ids, int32_t* __restrict__ expert_ids,\n int32_t* __restrict__ total_tokens_post_pad, int32_t num_experts,\n int32_t padded_num_experts, int32_t experts_per_warp, int32_t block_size,\n size_t numel, int32_t* __restrict__ cumsum, int32_t max_num_tokens_padded) {\n extern __shared__ int32_t shared_counts[];\n\n // Initialize sorted_token_ids with numel\n for (size_t it = threadIdx.x; it < max_num_tokens_padded; it += blockDim.x) {\n sorted_token_ids[it] = numel;\n }\n\n const int warp_id = threadIdx.x / WARP_SIZE;\n const int my_expert_start = warp_id * experts_per_warp;\n\n for (int i = 0; i < experts_per_warp; ++i) {\n if (my_expert_start + i < padded_num_experts) {\n shared_counts[warp_id * experts_per_warp + i] = 0;\n }\n }\n\n __syncthreads();\n\n const size_t tid = threadIdx.x;\n const size_t stride = blockDim.x;\n\n for (size_t i = tid; i < numel; i += stride) {\n int expert_id = topk_ids[i];\n if (expert_id >= num_experts) {\n continue;\n }\n int warp_idx = expert_id / experts_per_warp;\n int expert_offset = expert_id % experts_per_warp;\n atomicAdd(&shared_counts[warp_idx * experts_per_warp + expert_offset], 1);\n }\n\n __syncthreads();\n\n // Compute prefix sum over token counts per expert\n using BlockScan = cub::BlockScan<int32_t, 1024>;\n __shared__ typename BlockScan::TempStorage temp_storage;\n\n int expert_count = 0;\n int expert_id = threadIdx.x;\n if (expert_id < num_experts) {\n int warp_idx = expert_id / experts_per_warp;\n int expert_offset = expert_id % experts_per_warp;\n expert_count = shared_counts[warp_idx * experts_per_warp + expert_offset];\n expert_count = CEILDIV(expert_count, block_size) * block_size;\n }\n\n int cumsum_val;\n BlockScan(temp_storage).ExclusiveSum(expert_count, cumsum_val);\n if (expert_id <= num_experts) {\n cumsum[expert_id] = cumsum_val;\n }\n\n if (expert_id == num_experts) {\n *total_tokens_post_pad = cumsum_val;\n }\n\n __syncthreads();\n\n if (threadIdx.x < num_experts) {\n for (int i = cumsum[threadIdx.x]; i < cumsum[threadIdx.x + 1];\n i += block_size) {\n expert_ids[i / block_size] = threadIdx.x;\n }\n }\n\n // Fill remaining expert_ids with 0\n const size_t fill_start_idx = cumsum[num_experts] / block_size + threadIdx.x;\n const size_t expert_ids_size = CEILDIV(max_num_tokens_padded, block_size);\n for (size_t i = fill_start_idx; i < expert_ids_size; i += blockDim.x) {\n expert_ids[i] = 0;\n }\n}\n\ntemplate <typename scalar_t>\n__global__ void count_and_sort_expert_tokens_kernel(\n const scalar_t* __restrict__ topk_ids,\n int32_t* __restrict__ sorted_token_ids, int32_t* __restrict__ cumsum_buffer,\n size_t numel, int32_t num_experts) {\n const size_t tid = blockIdx.x * blockDim.x + threadIdx.x;\n const size_t stride = blockDim.x * gridDim.x;\n\n for (size_t i = tid; i < numel; i += stride) {\n int32_t expert_id = topk_ids[i];\n if (expert_id >= num_experts) {\n continue;\n }\n int32_t rank_post_pad = atomicAdd(&cumsum_buffer[expert_id], 1);\n sorted_token_ids[rank_post_pad] = i;\n }\n}\n\ntemplate <typename scalar_t, int TOPK>\n__global__ void moe_sum_kernel(\n scalar_t* __restrict__ out, // [..., d]\n const scalar_t* __restrict__ input, // [..., topk, d]\n const int d) {\n const int64_t token_idx = blockIdx.x;\n for (int64_t idx = threadIdx.x; idx < d; idx += blockDim.x) {\n scalar_t x = 0.0;\n#pragma unroll\n for (int k = 0; k < TOPK; ++k) {\n x += VLLM_LDG(&input[token_idx * TOPK * d + k * d + idx]);\n }\n out[token_idx * d + idx] = x;\n }\n}\n\ntemplate <typename scalar_t>\n__global__ void moe_align_block_size_small_batch_expert_kernel(\n const scalar_t* __restrict__ topk_ids,\n int32_t* __restrict__ sorted_token_ids, int32_t* __restrict__ expert_ids,\n int32_t* __restrict__ total_tokens_post_pad, int32_t num_experts,\n int32_t block_size, size_t numel, int32_t max_num_tokens_padded) {\n // Initialize sorted_token_ids with numel\n for (size_t it = threadIdx.x; it < max_num_tokens_padded; it += blockDim.x) {\n sorted_token_ids[it] = numel;\n }\n\n const size_t tid = threadIdx.x;\n const size_t stride = blockDim.x;\n\n extern __shared__ int32_t shared_mem[];\n int32_t* cumsum = shared_mem;\n int32_t* tokens_cnts = (int32_t*)(shared_mem + num_experts + 1);\n\n for (int i = 0; i < num_experts; ++i) {\n tokens_cnts[(threadIdx.x + 1) * num_experts + i] = 0;\n }\n\n for (size_t i = tid; i < numel; i += stride) {\n ++tokens_cnts[(threadIdx.x + 1) * num_experts + topk_ids[i]];\n }\n\n __syncthreads();\n\n if (threadIdx.x < num_experts) {\n tokens_cnts[threadIdx.x] = 0;\n for (int i = 1; i <= blockDim.x; ++i) {\n tokens_cnts[i * num_experts + threadIdx.x] +=\n tokens_cnts[(i - 1) * num_experts + threadIdx.x];\n }\n }\n\n __syncthreads();\n\n if (threadIdx.x == 0) {\n cumsum[0] = 0;\n for (int i = 1; i <= num_experts; ++i) {\n cumsum[i] =\n cumsum[i - 1] +\n CEILDIV(tokens_cnts[blockDim.x * num_experts + i - 1], block_size) *\n block_size;\n }\n *total_tokens_post_pad = static_cast<int32_t>(cumsum[num_experts]);\n }\n\n __syncthreads();\n\n if (threadIdx.x < num_experts) {\n for (int i = cumsum[threadIdx.x]; i < cumsum[threadIdx.x + 1];\n i += block_size) {\n expert_ids[i / block_size] = threadIdx.x;\n }\n }\n\n // Fill remaining expert_ids with 0\n const size_t fill_start_idx = cumsum[num_experts] / block_size + threadIdx.x;\n const size_t expert_ids_size = CEILDIV(max_num_tokens_padded, block_size);\n for (size_t i = fill_start_idx; i < expert_ids_size; i += blockDim.x) {\n expert_ids[i] = 0;\n }\n\n for (size_t i = tid; i < numel; i += stride) {\n int32_t expert_id = topk_ids[i];\n int32_t rank_post_pad =\n tokens_cnts[threadIdx.x * num_experts + expert_id] + cumsum[expert_id];\n sorted_token_ids[rank_post_pad] = i;\n ++tokens_cnts[threadIdx.x * num_experts + expert_id];\n }\n}\n\n} // namespace moe\n} // namespace vllm\n\n// taken from\n// https://github.com/sgl-project/sglang/blob/8b5f83ed3b7d2a49ad5c5cd5aa61c5d502f47dbc\nvoid moe_align_block_size(torch::Tensor topk_ids, int64_t num_experts,\n int64_t block_size, torch::Tensor sorted_token_ids,\n torch::Tensor experts_ids,\n torch::Tensor num_tokens_post_pad) {\n const cudaStream_t stream = at::cuda::getCurrentCUDAStream();\n\n int64_t padded_num_experts =\n ((num_experts + WARP_SIZE - 1) / WARP_SIZE) * WARP_SIZE;\n int experts_per_warp = WARP_SIZE;\n int threads = 1024;\n threads = ((threads + WARP_SIZE - 1) / WARP_SIZE) * WARP_SIZE;\n\n // BlockScan uses 1024 threads and assigns one thread per expert.\n TORCH_CHECK(padded_num_experts < 1024,\n \"padded_num_experts must be less than 1024\");\n\n VLLM_DISPATCH_INTEGRAL_AND_UNSIGNED_TYPES(\n topk_ids.scalar_type(), \"moe_align_block_size_kernel\", [&] {\n // calc needed amount of shared mem for `cumsum` tensors\n auto options_int =\n torch::TensorOptions().dtype(torch::kInt).device(topk_ids.device());\n torch::Tensor cumsum_buffer =\n torch::empty({num_experts + 1}, options_int);\n bool small_batch_expert_mode =\n (topk_ids.numel() < 1024) && (num_experts <= 64);\n\n if (small_batch_expert_mode) {\n const int32_t threads = max((int32_t)num_experts, WARP_SIZE);\n const int32_t shared_mem_size =\n ((threads + 1) * num_experts + (num_experts + 1)) *\n sizeof(int32_t);\n\n auto small_batch_expert_kernel =\n vllm::moe::moe_align_block_size_small_batch_expert_kernel<\n scalar_t>;\n small_batch_expert_kernel<<<1, threads, shared_mem_size, stream>>>(\n topk_ids.data_ptr<scalar_t>(),\n sorted_token_ids.data_ptr<int32_t>(),\n experts_ids.data_ptr<int32_t>(),\n num_tokens_post_pad.data_ptr<int32_t>(), num_experts, block_size,\n topk_ids.numel(), sorted_token_ids.size(0));\n } else {\n auto align_kernel = vllm::moe::moe_align_block_size_kernel<scalar_t>;\n\n size_t num_warps = CEILDIV(padded_num_experts, experts_per_warp);\n size_t shared_mem_size =\n num_warps * experts_per_warp * sizeof(int32_t);\n\n align_kernel<<<1, threads, shared_mem_size, stream>>>(\n topk_ids.data_ptr<scalar_t>(),\n sorted_token_ids.data_ptr<int32_t>(),\n experts_ids.data_ptr<int32_t>(),\n num_tokens_post_pad.data_ptr<int32_t>(), num_experts,\n padded_num_experts, experts_per_warp, block_size,\n topk_ids.numel(), cumsum_buffer.data_ptr<int32_t>(),\n sorted_token_ids.size(0));\n\n const int block_threads = std::min(256, (int)threads);\n const int num_blocks =\n (topk_ids.numel() + block_threads - 1) / block_threads;\n const int max_blocks = 65535;\n const int actual_blocks = std::min(num_blocks, max_blocks);\n\n auto sort_kernel =\n vllm::moe::count_and_sort_expert_tokens_kernel<scalar_t>;\n sort_kernel<<<actual_blocks, block_threads, 0, stream>>>(\n topk_ids.data_ptr<scalar_t>(),\n sorted_token_ids.data_ptr<int32_t>(),\n cumsum_buffer.data_ptr<int32_t>(), topk_ids.numel(), num_experts);\n }\n });\n}\n\nvoid batched_moe_align_block_size(int64_t max_tokens_per_batch,\n int64_t block_size,\n torch::Tensor const& batch_num_tokens,\n torch::Tensor sorted_ids,\n torch::Tensor batch_ids,\n torch::Tensor num_tokens_post_pad) {\n namespace batched_kernel = vllm::moe::batched_moe_align_block_size;\n\n const cudaStream_t stream = at::cuda::getCurrentCUDAStream();\n int32_t const B = batch_num_tokens.size(0);\n int32_t const num_blocks_per_batch =\n round_to_next_multiple_of(max_tokens_per_batch, block_size) / block_size;\n int32_t const num_blocks = num_blocks_per_batch * B;\n int64_t const sorted_ids_size = num_blocks * block_size;\n\n TORCH_CHECK(sorted_ids.size(0) == sorted_ids_size);\n TORCH_CHECK(batch_ids.size(0) == sorted_ids_size / block_size);\n TORCH_CHECK(num_tokens_post_pad.size(0) == 1);\n TORCH_CHECK(B <= batched_kernel::num_threads);\n\n batched_kernel::batched_moe_align_block_size_kernel<<<\n batched_kernel::num_blocks, batched_kernel::num_threads, 0, stream>>>(\n B, max_tokens_per_batch, block_size, batch_num_tokens.data_ptr<int32_t>(),\n sorted_ids.data_ptr<int32_t>(), batch_ids.data_ptr<int32_t>(),\n num_tokens_post_pad.data_ptr<int32_t>());\n}\n\nvoid moe_sum(torch::Tensor& input, // [num_tokens, topk, hidden_size]\n torch::Tensor& output) // [num_tokens, hidden_size]\n{\n const int hidden_size = input.size(-1);\n const auto num_tokens = output.numel() / hidden_size;\n const int topk = input.size(1);\n\n dim3 grid(num_tokens);\n dim3 block(std::min(hidden_size, 1024));\n const at::cuda::OptionalCUDAGuard device_guard(device_of(output));\n const cudaStream_t stream = at::cuda::getCurrentCUDAStream();\n\n switch (topk) {\n case 2:\n VLLM_DISPATCH_FLOATING_TYPES(input.scalar_type(), \"moe_sum_kernel\", [&] {\n vllm::moe::moe_sum_kernel<scalar_t, 2><<<grid, block, 0, stream>>>(\n output.data_ptr<scalar_t>(), input.data_ptr<scalar_t>(),\n hidden_size);\n });\n break;\n\n case 3:\n VLLM_DISPATCH_FLOATING_TYPES(input.scalar_type(), \"moe_sum_kernel\", [&] {\n vllm::moe::moe_sum_kernel<scalar_t, 3><<<grid, block, 0, stream>>>(\n output.data_ptr<scalar_t>(), input.data_ptr<scalar_t>(),\n hidden_size);\n });\n break;\n\n case 4:\n VLLM_DISPATCH_FLOATING_TYPES(input.scalar_type(), \"moe_sum_kernel\", [&] {\n vllm::moe::moe_sum_kernel<scalar_t, 4><<<grid, block, 0, stream>>>(\n output.data_ptr<scalar_t>(), input.data_ptr<scalar_t>(),\n hidden_size);\n });\n break;\n\n default:\n at::sum_out(output, input, 1);\n break;\n }\n}\n"},"after_code":{"kind":"string","value":"#include <torch/all.h>\n#include <ATen/cuda/CUDAContext.h>\n#include <c10/cuda/CUDAGuard.h>\n#include <cub/cub.cuh>\n\n#include <ATen/ATen.h>\n#include <ATen/cuda/Atomic.cuh>\n\n#include \"../cuda_compat.h\"\n#include \"../dispatch_utils.h\"\n#include \"core/math.hpp\"\n\n#define CEILDIV(x, y) (((x) + (y) - 1) / (y))\n\nnamespace vllm {\nnamespace moe {\n\nnamespace batched_moe_align_block_size {\n\n// Note num_threads needs to be 1024 for BlockScan Reduction in the kernel.\nstatic constexpr int32_t num_threads = 1024;\nstatic constexpr int32_t num_blocks = 1;\n__global__ void batched_moe_align_block_size_kernel(\n int32_t const num_batches, int32_t const max_tokens_per_batch,\n int32_t const block_size, int32_t const* __restrict__ batch_num_tokens,\n int32_t* __restrict__ sorted_ids, int32_t* __restrict__ block_ids,\n int32_t* __restrict__ num_tokens_post_pad) {\n // TODO(varun): This is a naive implementation. Could be optimized.\n\n size_t const batch_id = threadIdx.x;\n size_t const stride = blockDim.x * gridDim.x;\n int32_t const num_blocks_per_batch =\n CEILDIV(max_tokens_per_batch, block_size);\n int32_t const sorted_ids_size =\n num_blocks_per_batch * num_batches * block_size;\n int32_t const block_ids_size = sorted_ids_size / block_size;\n int32_t const SENTINEL =\n num_batches * max_tokens_per_batch; // To denote invalid entries.\n // Intialize sorted_ids\n for (size_t i = threadIdx.x; i < sorted_ids_size; i += stride) {\n sorted_ids[i] = SENTINEL;\n }\n // Intialize expert_ids with -1\n for (size_t i = threadIdx.x; i < block_ids_size; i += stride) {\n block_ids[i] = -1;\n }\n\n int32_t b_num_tokens = 0;\n if (batch_id < num_batches) {\n b_num_tokens = batch_num_tokens[batch_id];\n }\n int32_t const ceil_b_num_tokens =\n CEILDIV(b_num_tokens, block_size) * block_size;\n\n // Compute prefix sum over token counts per expert\n using BlockScan = cub::BlockScan<int32_t, 1024>;\n __shared__ typename BlockScan::TempStorage temp_storage;\n int cumsum_val;\n BlockScan(temp_storage).ExclusiveSum(ceil_b_num_tokens, cumsum_val);\n __syncthreads();\n\n bool const is_last_batch = batch_id == (num_batches - 1);\n if (is_last_batch) {\n *num_tokens_post_pad = cumsum_val + ceil_b_num_tokens;\n }\n\n if (batch_id < num_batches) {\n int32_t const batch_offset = batch_id * max_tokens_per_batch;\n for (size_t i = 0; i < b_num_tokens; ++i) {\n sorted_ids[cumsum_val + i] = batch_offset + i;\n }\n\n int32_t const block_start = cumsum_val / block_size;\n int32_t const num_blocks = ceil_b_num_tokens / block_size;\n for (size_t i = 0; i < num_blocks; ++i) {\n block_ids[block_start + i] = batch_id;\n }\n }\n}\n} // namespace batched_moe_align_block_size\n\ntemplate <typename scalar_t>\n__global__ void moe_align_block_size_kernel(\n const scalar_t* __restrict__ topk_ids,\n int32_t* __restrict__ sorted_token_ids, int32_t* __restrict__ expert_ids,\n int32_t* __restrict__ total_tokens_post_pad,\n int32_t* __restrict__ expert_map, int32_t num_experts,\n int32_t padded_num_experts, int32_t experts_per_warp, int32_t block_size,\n size_t numel, int32_t* __restrict__ cumsum, int32_t max_num_tokens_padded,\n bool has_expert_map) {\n extern __shared__ int32_t shared_counts[];\n\n // Use a separate threadblock to fill sorted_token_ids.\n // This is safe since the current kernel does not use sorted_token_ids.\n if (blockIdx.x == 1) {\n // Initialize sorted_token_ids with numel\n for (size_t it = threadIdx.x; it < max_num_tokens_padded;\n it += blockDim.x) {\n sorted_token_ids[it] = numel;\n }\n return;\n }\n\n const int warp_id = threadIdx.x / WARP_SIZE;\n const int my_expert_start = warp_id * experts_per_warp;\n\n for (int i = 0; i < experts_per_warp; ++i) {\n if (my_expert_start + i < padded_num_experts) {\n shared_counts[warp_id * experts_per_warp + i] = 0;\n }\n }\n\n __syncthreads();\n\n const size_t tid = threadIdx.x;\n const size_t stride = blockDim.x;\n\n for (size_t i = tid; i < numel; i += stride) {\n int expert_id = topk_ids[i];\n if (expert_id >= num_experts) {\n continue;\n }\n if (has_expert_map) {\n expert_id = expert_map[expert_id];\n // filter invalid experts\n if (expert_id == -1) continue;\n }\n int warp_idx = expert_id / experts_per_warp;\n int expert_offset = expert_id % experts_per_warp;\n atomicAdd(&shared_counts[warp_idx * experts_per_warp + expert_offset], 1);\n }\n\n __syncthreads();\n\n // Compute prefix sum over token counts per expert\n using BlockScan = cub::BlockScan<int32_t, 1024>;\n __shared__ typename BlockScan::TempStorage temp_storage;\n\n int expert_count = 0;\n int expert_id = threadIdx.x;\n if (expert_id < num_experts) {\n int warp_idx = expert_id / experts_per_warp;\n int expert_offset = expert_id % experts_per_warp;\n expert_count = shared_counts[warp_idx * experts_per_warp + expert_offset];\n expert_count = CEILDIV(expert_count, block_size) * block_size;\n }\n\n int cumsum_val;\n BlockScan(temp_storage).ExclusiveSum(expert_count, cumsum_val);\n if (expert_id <= num_experts) {\n cumsum[expert_id] = cumsum_val;\n }\n\n if (expert_id == num_experts) {\n *total_tokens_post_pad = cumsum_val;\n }\n\n __syncthreads();\n\n if (threadIdx.x < num_experts) {\n for (int i = cumsum[threadIdx.x]; i < cumsum[threadIdx.x + 1];\n i += block_size) {\n expert_ids[i / block_size] = threadIdx.x;\n }\n }\n\n // Fill remaining expert_ids with 0\n const size_t fill_start_idx = cumsum[num_experts] / block_size + threadIdx.x;\n const size_t expert_ids_size = CEILDIV(max_num_tokens_padded, block_size);\n for (size_t i = fill_start_idx; i < expert_ids_size; i += blockDim.x) {\n expert_ids[i] = 0;\n }\n}\n\ntemplate <typename scalar_t>\n__global__ void count_and_sort_expert_tokens_kernel(\n const scalar_t* __restrict__ topk_ids,\n int32_t* __restrict__ sorted_token_ids, int32_t* __restrict__ cumsum_buffer,\n int32_t* __restrict__ expert_map, size_t numel, int32_t num_experts,\n bool has_expert_map) {\n const size_t tid = blockIdx.x * blockDim.x + threadIdx.x;\n const size_t stride = blockDim.x * gridDim.x;\n\n for (size_t i = tid; i < numel; i += stride) {\n int32_t expert_id = topk_ids[i];\n if (expert_id >= num_experts) {\n continue;\n }\n if (has_expert_map) {\n expert_id = expert_map[expert_id];\n // filter invalid experts\n if (expert_id == -1) continue;\n }\n int32_t rank_post_pad = atomicAdd(&cumsum_buffer[expert_id], 1);\n sorted_token_ids[rank_post_pad] = i;\n }\n}\n\ntemplate <typename scalar_t, int TOPK>\n__global__ void moe_sum_kernel(\n scalar_t* __restrict__ out, // [..., d]\n const scalar_t* __restrict__ input, // [..., topk, d]\n const int d) {\n const int64_t token_idx = blockIdx.x;\n for (int64_t idx = threadIdx.x; idx < d; idx += blockDim.x) {\n scalar_t x = 0.0;\n#pragma unroll\n for (int k = 0; k < TOPK; ++k) {\n x += VLLM_LDG(&input[token_idx * TOPK * d + k * d + idx]);\n }\n out[token_idx * d + idx] = x;\n }\n}\n\ntemplate <typename scalar_t, int32_t fill_threads>\n__global__ void moe_align_block_size_small_batch_expert_kernel(\n const scalar_t* __restrict__ topk_ids,\n int32_t* __restrict__ sorted_token_ids, int32_t* __restrict__ expert_ids,\n int32_t* __restrict__ total_tokens_post_pad,\n int32_t* __restrict__ expert_map, int32_t num_experts, int32_t block_size,\n size_t numel, int32_t max_num_tokens_padded, bool has_expert_map) {\n // Use an additional group of threads to fill sorted_token_ids.\n // Since the current kernel will use sorted_token_ids afterward,\n // we fill sorted_token_ids within the same threadblock to make\n // synchronization easier.\n if (threadIdx.x < fill_threads) {\n // Initialize sorted_token_ids with numel\n for (size_t it = threadIdx.x; it < max_num_tokens_padded;\n it += fill_threads) {\n sorted_token_ids[it] = numel;\n }\n // Three __syncthreads() corresponding to the other threads\n __syncthreads();\n __syncthreads();\n __syncthreads();\n return;\n }\n\n const size_t tid = threadIdx.x - fill_threads;\n const size_t stride = blockDim.x - fill_threads;\n\n extern __shared__ int32_t shared_mem[];\n int32_t* cumsum = shared_mem;\n int32_t* tokens_cnts = (int32_t*)(shared_mem + num_experts + 1);\n\n for (int i = 0; i < num_experts; ++i) {\n tokens_cnts[(tid + 1) * num_experts + i] = 0;\n }\n\n for (size_t i = tid; i < numel; i += stride) {\n int32_t expert_id = topk_ids[i];\n if (has_expert_map) {\n expert_id = expert_map[expert_id];\n // filter invalid expert\n if (expert_id == -1) continue;\n }\n ++tokens_cnts[(tid + 1) * num_experts + expert_id];\n }\n\n __syncthreads();\n\n if (tid < num_experts) {\n tokens_cnts[tid] = 0;\n for (int i = 1; i <= stride; ++i) {\n tokens_cnts[i * num_experts + tid] +=\n tokens_cnts[(i - 1) * num_experts + tid];\n }\n }\n\n __syncthreads();\n\n if (tid == 0) {\n cumsum[0] = 0;\n for (int i = 1; i <= num_experts; ++i) {\n cumsum[i] =\n cumsum[i - 1] +\n CEILDIV(tokens_cnts[stride * num_experts + i - 1], block_size) *\n block_size;\n }\n *total_tokens_post_pad = static_cast<int32_t>(cumsum[num_experts]);\n }\n\n __syncthreads();\n\n if (tid < num_experts) {\n for (int i = cumsum[tid]; i < cumsum[tid + 1]; i += block_size) {\n expert_ids[i / block_size] = tid;\n }\n }\n\n // Fill remaining expert_ids with 0\n const size_t fill_start_idx = cumsum[num_experts] / block_size + tid;\n const size_t expert_ids_size = CEILDIV(max_num_tokens_padded, block_size);\n for (size_t i = fill_start_idx; i < expert_ids_size; i += stride) {\n expert_ids[i] = 0;\n }\n\n for (size_t i = tid; i < numel; i += stride) {\n int32_t expert_id = topk_ids[i];\n if (has_expert_map) {\n expert_id = expert_map[expert_id];\n // filter invalid expert\n if (expert_id == -1) continue;\n }\n int32_t rank_post_pad =\n tokens_cnts[tid * num_experts + expert_id] + cumsum[expert_id];\n sorted_token_ids[rank_post_pad] = i;\n ++tokens_cnts[tid * num_experts + expert_id];\n }\n}\n\n} // namespace moe\n} // namespace vllm\n\n// taken from\n// https://github.com/sgl-project/sglang/blob/8b5f83ed3b7d2a49ad5c5cd5aa61c5d502f47dbc\nvoid moe_align_block_size(torch::Tensor topk_ids, int64_t num_experts,\n int64_t block_size, torch::Tensor sorted_token_ids,\n torch::Tensor experts_ids,\n torch::Tensor num_tokens_post_pad,\n std::optional<torch::Tensor> maybe_expert_map) {\n const cudaStream_t stream = at::cuda::getCurrentCUDAStream();\n\n int64_t padded_num_experts =\n ((num_experts + WARP_SIZE - 1) / WARP_SIZE) * WARP_SIZE;\n int experts_per_warp = WARP_SIZE;\n int threads = 1024;\n threads = ((threads + WARP_SIZE - 1) / WARP_SIZE) * WARP_SIZE;\n\n // BlockScan uses 1024 threads and assigns one thread per expert.\n TORCH_CHECK(padded_num_experts < 1024,\n \"padded_num_experts must be less than 1024\");\n auto options_int =\n torch::TensorOptions().dtype(torch::kInt).device(topk_ids.device());\n bool has_expert_map = maybe_expert_map.has_value();\n torch::Tensor expert_map;\n if (has_expert_map) {\n expert_map = maybe_expert_map.value();\n } else {\n expert_map = torch::empty({0}, options_int);\n }\n\n VLLM_DISPATCH_INTEGRAL_AND_UNSIGNED_TYPES(\n topk_ids.scalar_type(), \"moe_align_block_size_kernel\", [&] {\n // calc needed amount of shared mem for `cumsum` tensors\n bool small_batch_expert_mode =\n (topk_ids.numel() < 1024) && (num_experts <= 64);\n\n if (small_batch_expert_mode) {\n const int32_t threads = max((int32_t)num_experts, WARP_SIZE);\n const int32_t shared_mem_size =\n ((threads + 1) * num_experts + (num_experts + 1)) *\n sizeof(int32_t);\n\n // threadIdx.x >= fill_threads: counting experts and aligning\n // threadIdx.x < fill_threads: filling sorted_token_ids\n constexpr int32_t fill_threads = 256;\n auto small_batch_expert_kernel =\n vllm::moe::moe_align_block_size_small_batch_expert_kernel<\n scalar_t, fill_threads>;\n small_batch_expert_kernel<<<1, fill_threads + threads,\n shared_mem_size, stream>>>(\n topk_ids.data_ptr<scalar_t>(),\n sorted_token_ids.data_ptr<int32_t>(),\n experts_ids.data_ptr<int32_t>(),\n num_tokens_post_pad.data_ptr<int32_t>(),\n expert_map.data_ptr<int32_t>(), num_experts, block_size,\n topk_ids.numel(), sorted_token_ids.size(0), has_expert_map);\n } else {\n torch::Tensor cumsum_buffer =\n torch::empty({num_experts + 1}, options_int);\n auto align_kernel = vllm::moe::moe_align_block_size_kernel<scalar_t>;\n\n size_t num_warps = CEILDIV(padded_num_experts, experts_per_warp);\n size_t shared_mem_size =\n num_warps * experts_per_warp * sizeof(int32_t);\n\n // launch two threadblocks\n // blockIdx.x == 0: counting experts and aligning\n // blockIdx.x == 1: filling sorted_token_ids\n align_kernel<<<2, threads, shared_mem_size, stream>>>(\n topk_ids.data_ptr<scalar_t>(),\n sorted_token_ids.data_ptr<int32_t>(),\n experts_ids.data_ptr<int32_t>(),\n num_tokens_post_pad.data_ptr<int32_t>(),\n expert_map.data_ptr<int32_t>(), num_experts, padded_num_experts,\n experts_per_warp, block_size, topk_ids.numel(),\n cumsum_buffer.data_ptr<int32_t>(), sorted_token_ids.size(0),\n has_expert_map);\n\n const int block_threads = std::min(256, (int)threads);\n const int num_blocks =\n (topk_ids.numel() + block_threads - 1) / block_threads;\n const int max_blocks = 65535;\n const int actual_blocks = std::min(num_blocks, max_blocks);\n\n auto sort_kernel =\n vllm::moe::count_and_sort_expert_tokens_kernel<scalar_t>;\n sort_kernel<<<actual_blocks, block_threads, 0, stream>>>(\n topk_ids.data_ptr<scalar_t>(),\n sorted_token_ids.data_ptr<int32_t>(),\n cumsum_buffer.data_ptr<int32_t>(), expert_map.data_ptr<int32_t>(),\n topk_ids.numel(), num_experts, has_expert_map);\n }\n });\n}\n\nvoid batched_moe_align_block_size(int64_t max_tokens_per_batch,\n int64_t block_size,\n torch::Tensor const& batch_num_tokens,\n torch::Tensor sorted_ids,\n torch::Tensor batch_ids,\n torch::Tensor num_tokens_post_pad) {\n namespace batched_kernel = vllm::moe::batched_moe_align_block_size;\n\n const cudaStream_t stream = at::cuda::getCurrentCUDAStream();\n int32_t const B = batch_num_tokens.size(0);\n int32_t const num_blocks_per_batch =\n round_to_next_multiple_of(max_tokens_per_batch, block_size) / block_size;\n int32_t const num_blocks = num_blocks_per_batch * B;\n int64_t const sorted_ids_size = num_blocks * block_size;\n\n TORCH_CHECK(sorted_ids.size(0) == sorted_ids_size);\n TORCH_CHECK(batch_ids.size(0) == sorted_ids_size / block_size);\n TORCH_CHECK(num_tokens_post_pad.size(0) == 1);\n TORCH_CHECK(B <= batched_kernel::num_threads);\n\n batched_kernel::batched_moe_align_block_size_kernel<<<\n batched_kernel::num_blocks, batched_kernel::num_threads, 0, stream>>>(\n B, max_tokens_per_batch, block_size, batch_num_tokens.data_ptr<int32_t>(),\n sorted_ids.data_ptr<int32_t>(), batch_ids.data_ptr<int32_t>(),\n num_tokens_post_pad.data_ptr<int32_t>());\n}\n\nvoid moe_sum(torch::Tensor& input, // [num_tokens, topk, hidden_size]\n torch::Tensor& output) // [num_tokens, hidden_size]\n{\n const int hidden_size = input.size(-1);\n const auto num_tokens = output.numel() / hidden_size;\n const int topk = input.size(1);\n\n dim3 grid(num_tokens);\n dim3 block(std::min(hidden_size, 1024));\n const at::cuda::OptionalCUDAGuard device_guard(device_of(output));\n const cudaStream_t stream = at::cuda::getCurrentCUDAStream();\n\n switch (topk) {\n case 2:\n VLLM_DISPATCH_FLOATING_TYPES(input.scalar_type(), \"moe_sum_kernel\", [&] {\n vllm::moe::moe_sum_kernel<scalar_t, 2><<<grid, block, 0, stream>>>(\n output.data_ptr<scalar_t>(), input.data_ptr<scalar_t>(),\n hidden_size);\n });\n break;\n\n case 3:\n VLLM_DISPATCH_FLOATING_TYPES(input.scalar_type(), \"moe_sum_kernel\", [&] {\n vllm::moe::moe_sum_kernel<scalar_t, 3><<<grid, block, 0, stream>>>(\n output.data_ptr<scalar_t>(), input.data_ptr<scalar_t>(),\n hidden_size);\n });\n break;\n\n case 4:\n VLLM_DISPATCH_FLOATING_TYPES(input.scalar_type(), \"moe_sum_kernel\", [&] {\n vllm::moe::moe_sum_kernel<scalar_t, 4><<<grid, block, 0, stream>>>(\n output.data_ptr<scalar_t>(), input.data_ptr<scalar_t>(),\n hidden_size);\n });\n break;\n\n default:\n at::sum_out(output, input, 1);\n break;\n }\n}\n"},"diff":{"kind":"string","value":"--- csrc/moe/moe_align_sum_kernels.cu\n+++ csrc/moe/moe_align_sum_kernels.cu\n@@ -83,14 +83,22 @@\n __global__ void moe_align_block_size_kernel(\n const scalar_t* __restrict__ topk_ids,\n int32_t* __restrict__ sorted_token_ids, int32_t* __restrict__ expert_ids,\n- int32_t* __restrict__ total_tokens_post_pad, int32_t num_experts,\n+ int32_t* __restrict__ total_tokens_post_pad,\n+ int32_t* __restrict__ expert_map, int32_t num_experts,\n int32_t padded_num_experts, int32_t experts_per_warp, int32_t block_size,\n- size_t numel, int32_t* __restrict__ cumsum, int32_t max_num_tokens_padded) {\n+ size_t numel, int32_t* __restrict__ cumsum, int32_t max_num_tokens_padded,\n+ bool has_expert_map) {\n extern __shared__ int32_t shared_counts[];\n \n- // Initialize sorted_token_ids with numel\n- for (size_t it = threadIdx.x; it < max_num_tokens_padded; it += blockDim.x) {\n- sorted_token_ids[it] = numel;\n+ // Use a separate threadblock to fill sorted_token_ids.\n+ // This is safe since the current kernel does not use sorted_token_ids.\n+ if (blockIdx.x == 1) {\n+ // Initialize sorted_token_ids with numel\n+ for (size_t it = threadIdx.x; it < max_num_tokens_padded;\n+ it += blockDim.x) {\n+ sorted_token_ids[it] = numel;\n+ }\n+ return;\n }\n \n const int warp_id = threadIdx.x / WARP_SIZE;\n@@ -111,6 +119,11 @@\n int expert_id = topk_ids[i];\n if (expert_id >= num_experts) {\n continue;\n+ }\n+ if (has_expert_map) {\n+ expert_id = expert_map[expert_id];\n+ // filter invalid experts\n+ if (expert_id == -1) continue;\n }\n int warp_idx = expert_id / experts_per_warp;\n int expert_offset = expert_id % experts_per_warp;\n@@ -163,7 +176,8 @@\n __global__ void count_and_sort_expert_tokens_kernel(\n const scalar_t* __restrict__ topk_ids,\n int32_t* __restrict__ sorted_token_ids, int32_t* __restrict__ cumsum_buffer,\n- size_t numel, int32_t num_experts) {\n+ int32_t* __restrict__ expert_map, size_t numel, int32_t num_experts,\n+ bool has_expert_map) {\n const size_t tid = blockIdx.x * blockDim.x + threadIdx.x;\n const size_t stride = blockDim.x * gridDim.x;\n \n@@ -171,6 +185,11 @@\n int32_t expert_id = topk_ids[i];\n if (expert_id >= num_experts) {\n continue;\n+ }\n+ if (has_expert_map) {\n+ expert_id = expert_map[expert_id];\n+ // filter invalid experts\n+ if (expert_id == -1) continue;\n }\n int32_t rank_post_pad = atomicAdd(&cumsum_buffer[expert_id], 1);\n sorted_token_ids[rank_post_pad] = i;\n@@ -193,50 +212,69 @@\n }\n }\n \n-template <typename scalar_t>\n+template <typename scalar_t, int32_t fill_threads>\n __global__ void moe_align_block_size_small_batch_expert_kernel(\n const scalar_t* __restrict__ topk_ids,\n int32_t* __restrict__ sorted_token_ids, int32_t* __restrict__ expert_ids,\n- int32_t* __restrict__ total_tokens_post_pad, int32_t num_experts,\n- int32_t block_size, size_t numel, int32_t max_num_tokens_padded) {\n- // Initialize sorted_token_ids with numel\n- for (size_t it = threadIdx.x; it < max_num_tokens_padded; it += blockDim.x) {\n- sorted_token_ids[it] = numel;\n- }\n-\n- const size_t tid = threadIdx.x;\n- const size_t stride = blockDim.x;\n+ int32_t* __restrict__ total_tokens_post_pad,\n+ int32_t* __restrict__ expert_map, int32_t num_experts, int32_t block_size,\n+ size_t numel, int32_t max_num_tokens_padded, bool has_expert_map) {\n+ // Use an additional group of threads to fill sorted_token_ids.\n+ // Since the current kernel will use sorted_token_ids afterward,\n+ // we fill sorted_token_ids within the same threadblock to make\n+ // synchronization easier.\n+ if (threadIdx.x < fill_threads) {\n+ // Initialize sorted_token_ids with numel\n+ for (size_t it = threadIdx.x; it < max_num_tokens_padded;\n+ it += fill_threads) {\n+ sorted_token_ids[it] = numel;\n+ }\n+ // Three __syncthreads() corresponding to the other threads\n+ __syncthreads();\n+ __syncthreads();\n+ __syncthreads();\n+ return;\n+ }\n+\n+ const size_t tid = threadIdx.x - fill_threads;\n+ const size_t stride = blockDim.x - fill_threads;\n \n extern __shared__ int32_t shared_mem[];\n int32_t* cumsum = shared_mem;\n int32_t* tokens_cnts = (int32_t*)(shared_mem + num_experts + 1);\n \n for (int i = 0; i < num_experts; ++i) {\n- tokens_cnts[(threadIdx.x + 1) * num_experts + i] = 0;\n+ tokens_cnts[(tid + 1) * num_experts + i] = 0;\n }\n \n for (size_t i = tid; i < numel; i += stride) {\n- ++tokens_cnts[(threadIdx.x + 1) * num_experts + topk_ids[i]];\n- }\n-\n- __syncthreads();\n-\n- if (threadIdx.x < num_experts) {\n- tokens_cnts[threadIdx.x] = 0;\n- for (int i = 1; i <= blockDim.x; ++i) {\n- tokens_cnts[i * num_experts + threadIdx.x] +=\n- tokens_cnts[(i - 1) * num_experts + threadIdx.x];\n- }\n- }\n-\n- __syncthreads();\n-\n- if (threadIdx.x == 0) {\n+ int32_t expert_id = topk_ids[i];\n+ if (has_expert_map) {\n+ expert_id = expert_map[expert_id];\n+ // filter invalid expert\n+ if (expert_id == -1) continue;\n+ }\n+ ++tokens_cnts[(tid + 1) * num_experts + expert_id];\n+ }\n+\n+ __syncthreads();\n+\n+ if (tid < num_experts) {\n+ tokens_cnts[tid] = 0;\n+ for (int i = 1; i <= stride; ++i) {\n+ tokens_cnts[i * num_experts + tid] +=\n+ tokens_cnts[(i - 1) * num_experts + tid];\n+ }\n+ }\n+\n+ __syncthreads();\n+\n+ if (tid == 0) {\n cumsum[0] = 0;\n for (int i = 1; i <= num_experts; ++i) {\n cumsum[i] =\n cumsum[i - 1] +\n- CEILDIV(tokens_cnts[blockDim.x * num_experts + i - 1], block_size) *\n+ CEILDIV(tokens_cnts[stride * num_experts + i - 1], block_size) *\n block_size;\n }\n *total_tokens_post_pad = static_cast<int32_t>(cumsum[num_experts]);\n@@ -244,26 +282,30 @@\n \n __syncthreads();\n \n- if (threadIdx.x < num_experts) {\n- for (int i = cumsum[threadIdx.x]; i < cumsum[threadIdx.x + 1];\n- i += block_size) {\n- expert_ids[i / block_size] = threadIdx.x;\n+ if (tid < num_experts) {\n+ for (int i = cumsum[tid]; i < cumsum[tid + 1]; i += block_size) {\n+ expert_ids[i / block_size] = tid;\n }\n }\n \n // Fill remaining expert_ids with 0\n- const size_t fill_start_idx = cumsum[num_experts] / block_size + threadIdx.x;\n+ const size_t fill_start_idx = cumsum[num_experts] / block_size + tid;\n const size_t expert_ids_size = CEILDIV(max_num_tokens_padded, block_size);\n- for (size_t i = fill_start_idx; i < expert_ids_size; i += blockDim.x) {\n+ for (size_t i = fill_start_idx; i < expert_ids_size; i += stride) {\n expert_ids[i] = 0;\n }\n \n for (size_t i = tid; i < numel; i += stride) {\n int32_t expert_id = topk_ids[i];\n+ if (has_expert_map) {\n+ expert_id = expert_map[expert_id];\n+ // filter invalid expert\n+ if (expert_id == -1) continue;\n+ }\n int32_t rank_post_pad =\n- tokens_cnts[threadIdx.x * num_experts + expert_id] + cumsum[expert_id];\n+ tokens_cnts[tid * num_experts + expert_id] + cumsum[expert_id];\n sorted_token_ids[rank_post_pad] = i;\n- ++tokens_cnts[threadIdx.x * num_experts + expert_id];\n+ ++tokens_cnts[tid * num_experts + expert_id];\n }\n }\n \n@@ -275,7 +317,8 @@\n void moe_align_block_size(torch::Tensor topk_ids, int64_t num_experts,\n int64_t block_size, torch::Tensor sorted_token_ids,\n torch::Tensor experts_ids,\n- torch::Tensor num_tokens_post_pad) {\n+ torch::Tensor num_tokens_post_pad,\n+ std::optional<torch::Tensor> maybe_expert_map) {\n const cudaStream_t stream = at::cuda::getCurrentCUDAStream();\n \n int64_t padded_num_experts =\n@@ -287,14 +330,19 @@\n // BlockScan uses 1024 threads and assigns one thread per expert.\n TORCH_CHECK(padded_num_experts < 1024,\n \"padded_num_experts must be less than 1024\");\n+ auto options_int =\n+ torch::TensorOptions().dtype(torch::kInt).device(topk_ids.device());\n+ bool has_expert_map = maybe_expert_map.has_value();\n+ torch::Tensor expert_map;\n+ if (has_expert_map) {\n+ expert_map = maybe_expert_map.value();\n+ } else {\n+ expert_map = torch::empty({0}, options_int);\n+ }\n \n VLLM_DISPATCH_INTEGRAL_AND_UNSIGNED_TYPES(\n topk_ids.scalar_type(), \"moe_align_block_size_kernel\", [&] {\n // calc needed amount of shared mem for `cumsum` tensors\n- auto options_int =\n- torch::TensorOptions().dtype(torch::kInt).device(topk_ids.device());\n- torch::Tensor cumsum_buffer =\n- torch::empty({num_experts + 1}, options_int);\n bool small_batch_expert_mode =\n (topk_ids.numel() < 1024) && (num_experts <= 64);\n \n@@ -304,30 +352,41 @@\n ((threads + 1) * num_experts + (num_experts + 1)) *\n sizeof(int32_t);\n \n+ // threadIdx.x >= fill_threads: counting experts and aligning\n+ // threadIdx.x < fill_threads: filling sorted_token_ids\n+ constexpr int32_t fill_threads = 256;\n auto small_batch_expert_kernel =\n vllm::moe::moe_align_block_size_small_batch_expert_kernel<\n- scalar_t>;\n- small_batch_expert_kernel<<<1, threads, shared_mem_size, stream>>>(\n+ scalar_t, fill_threads>;\n+ small_batch_expert_kernel<<<1, fill_threads + threads,\n+ shared_mem_size, stream>>>(\n topk_ids.data_ptr<scalar_t>(),\n sorted_token_ids.data_ptr<int32_t>(),\n experts_ids.data_ptr<int32_t>(),\n- num_tokens_post_pad.data_ptr<int32_t>(), num_experts, block_size,\n- topk_ids.numel(), sorted_token_ids.size(0));\n+ num_tokens_post_pad.data_ptr<int32_t>(),\n+ expert_map.data_ptr<int32_t>(), num_experts, block_size,\n+ topk_ids.numel(), sorted_token_ids.size(0), has_expert_map);\n } else {\n+ torch::Tensor cumsum_buffer =\n+ torch::empty({num_experts + 1}, options_int);\n auto align_kernel = vllm::moe::moe_align_block_size_kernel<scalar_t>;\n \n size_t num_warps = CEILDIV(padded_num_experts, experts_per_warp);\n size_t shared_mem_size =\n num_warps * experts_per_warp * sizeof(int32_t);\n \n- align_kernel<<<1, threads, shared_mem_size, stream>>>(\n+ // launch two threadblocks\n+ // blockIdx.x == 0: counting experts and aligning\n+ // blockIdx.x == 1: filling sorted_token_ids\n+ align_kernel<<<2, threads, shared_mem_size, stream>>>(\n topk_ids.data_ptr<scalar_t>(),\n sorted_token_ids.data_ptr<int32_t>(),\n experts_ids.data_ptr<int32_t>(),\n- num_tokens_post_pad.data_ptr<int32_t>(), num_experts,\n- padded_num_experts, experts_per_warp, block_size,\n- topk_ids.numel(), cumsum_buffer.data_ptr<int32_t>(),\n- sorted_token_ids.size(0));\n+ num_tokens_post_pad.data_ptr<int32_t>(),\n+ expert_map.data_ptr<int32_t>(), num_experts, padded_num_experts,\n+ experts_per_warp, block_size, topk_ids.numel(),\n+ cumsum_buffer.data_ptr<int32_t>(), sorted_token_ids.size(0),\n+ has_expert_map);\n \n const int block_threads = std::min(256, (int)threads);\n const int num_blocks =\n@@ -340,7 +399,8 @@\n sort_kernel<<<actual_blocks, block_threads, 0, stream>>>(\n topk_ids.data_ptr<scalar_t>(),\n sorted_token_ids.data_ptr<int32_t>(),\n- cumsum_buffer.data_ptr<int32_t>(), topk_ids.numel(), num_experts);\n+ cumsum_buffer.data_ptr<int32_t>(), expert_map.data_ptr<int32_t>(),\n+ topk_ids.numel(), num_experts, has_expert_map);\n }\n });\n }"},"lines_added":{"kind":"number","value":117,"string":"117"},"lines_removed":{"kind":"number","value":57,"string":"57"},"files_in_commit":{"kind":"number","value":6,"string":"6"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from vllm (csrc/moe/moe_align_sum_kernels.cu).\n\nGoal: [Kernel][MoE] optimize `moe_align_block_size`\nTarget hardware: unspecified\nTarget models: unspecified\n\nCurrent file:\n```cuda\n#include <torch/all.h>\n#include <ATen/cuda/CUDAContext.h>\n#include <c10/cuda/CUDAGuard.h>\n#include <cub/cub.cuh>\n\n#include <ATen/ATen.h>\n#include <ATen/cuda/Atomic.cuh>\n\n#include \"../cuda_compat.h\"\n#include \"../dispatch_utils.h\"\n#include \"core/math.hpp\"\n\n#define CEILDIV(x, y) (((x) + (y) - 1) / (y))\n\nnamespace vllm {\nnamespace moe {\n\nnamespace batched_moe_align_block_size {\n\n// Note num_threads needs to be 1024 for BlockScan Reduction in the kernel.\nstatic constexpr int32_t num_threads = 1024;\nstatic constexpr int32_t num_blocks = 1;\n__global__ void batched_moe_align_block_size_kernel(\n int32_t const num_batches, int32_t const max_tokens_per_batch,\n int32_t const block_size, int32_t const* __restrict__ batch_num_tokens,\n int32_t* __restrict__ sorted_ids, int32_t* __restrict__ block_ids,\n int32_t* __restrict__ num_tokens_post_pad) {\n // TODO(varun): This is a naive implementation. Could be optimized.\n\n size_t const batch_id = threadIdx.x;\n size_t const stride = blockDim.x * gridDim.x;\n int32_t const num_blocks_per_batch =\n CEILDIV(max_tokens_per_batch, block_size);\n int32_t const sorted_ids_size =\n num_blocks_per_batch * num_batches * block_size;\n int32_t const block_ids_size = sorted_ids_size / block_size;\n int32_t const SENTINEL =\n num_batches * max_tokens_per_batch; // To denote invalid entries.\n // Intialize sorted_ids\n for (size_t i = threadIdx.x; i < sorted_ids_size; i += stride) {\n sorted_ids[i] = SENTINEL;\n }\n // Intialize expert_ids with -1\n for (size_t i = threadIdx.x; i < block_ids_size; i += stride) {\n block_ids[i] = -1;\n }\n\n int32_t b_num_tokens = 0;\n if (batch_id < num_batches) {\n b_num_tokens = batch_num_tokens[batch_id];\n }\n int32_t const ceil_b_num_tokens =\n CEILDIV(b_num_tokens, block_size) * block_size;\n\n // Compute prefix sum over token counts per expert\n using BlockScan = cub::BlockScan<int32_t, 1024>;\n __shared__ typename BlockScan::TempStorage temp_storage;\n int cumsum_val;\n BlockScan(temp_storage).ExclusiveSum(ceil_b_num_tokens, cumsum_val);\n __syncthreads();\n\n bool const is_last_batch = batch_id == (num_batches - 1);\n if (is_last_batch) {\n *num_tokens_post_pad = cumsum_val + ceil_b_num_tokens;\n }\n\n if (batch_id < num_batches) {\n int32_t const batch_offset = batch_id * max_tokens_per_batch;\n for (size_t i = 0; i < b_num_tokens; ++i) {\n sorted_ids[cumsum_val + i] = batch_offset + i;\n }\n\n int32_t const block_start = cumsum_val / block_size;\n int32_t const num_blocks = ceil_b_num_tokens / block_size;\n for (size_t i = 0; i < num_blocks; ++i) {\n block_ids[block_start + i] = batch_id;\n }\n }\n}\n} // namespace batched_moe_align_block_size\n\ntemplate <typename scalar_t>\n__global__ void moe_align_block_size_kernel(\n const scalar_t* __restrict__ topk_ids,\n int32_t* __restrict__ sorted_token_ids, int32_t* __restrict__ expert_ids,\n int32_t* __restrict__ total_tokens_post_pad, int32_t num_experts,\n int32_t padded_num_experts, int32_t experts_per_warp, int32_t block_size,\n size_t numel, int32_t* __restrict__ cumsum, int32_t max_num_tokens_padded) {\n extern __shared__ int32_t shared_counts[];\n\n // Initialize sorted_token_ids with numel\n for (size_t it = threadIdx.x; it < max_num_tokens_padded; it += blockDim.x) {\n sorted_token_ids[it] = numel;\n }\n\n const int warp_id = threadIdx.x / WARP_SIZE;\n const int my_expert_start = warp_id * experts_per_warp;\n\n for (int i = 0; i < experts_per_warp; ++i) {\n if (my_expert_start + i < padded_num_experts) {\n shared_counts[warp_id * experts_per_warp + i] = 0;\n }\n }\n\n __syncthreads();\n\n const size_t tid = threadIdx.x;\n const size_t stride = blockDim.x;\n\n for (size_t i = tid; i < numel; i += stride) {\n int expert_id = topk_ids[i];\n if (expert_id >= num_experts) {\n continue;\n }\n int warp_idx = expert_id / experts_per_warp;\n int expert_offset = expert_id % experts_per_warp;\n atomicAdd(&shared_counts[warp_idx * experts_per_warp + expert_offset], 1);\n }\n\n __syncthreads();\n\n // Compute prefix sum over token counts per expert\n using BlockScan = cub::BlockScan<int32_t, 1024>;\n __shared__ typename BlockScan::TempStorage temp_storage;\n\n int expert_count = 0;\n int expert_id = threadIdx.x;\n if (expert_id < num_experts) {\n int warp_idx = expert_id / experts_per_warp;\n int expert_offset = expert_id % experts_per_warp;\n expert_count = shared_counts[warp_idx * experts_per_warp + expert_offset];\n expert_count = CEILDIV(expert_count, block_size) * block_size;\n }\n\n int cumsum_val;\n BlockScan(temp_storage).ExclusiveSum(expert_count, cumsum_val);\n if (expert_id <= num_experts) {\n cumsum[expert_id] = cumsum_val;\n }\n\n if (expert_id == num_experts) {\n *total_tokens_post_pad = cumsum_val;\n }\n\n __syncthreads();\n\n if (threadIdx.x < num_experts) {\n for (int i = cumsum[threadIdx.x]; i < cumsum[threadIdx.x + 1];\n i += block_size) {\n expert_ids[i / block_size] = threadIdx.x;\n }\n }\n\n // Fill remaining expert_ids with 0\n const size_t fill_start_idx = cumsum[num_experts] / block_size + threadIdx.x;\n const size_t expert_ids_size = CEILDIV(max_num_tokens_padded, block_size);\n for (size_t i = fill_start_idx; i < expert_ids_size; i += blockDim.x) {\n expert_ids[i] = 0;\n }\n}\n\ntemplate <typename scalar_t>\n__global__ void count_and_sort_expert_tokens_kernel(\n const scalar_t* __restrict__ topk_ids,\n int32_t* __restrict__ sorted_token_ids, int32_t* __restrict__ cumsum_buffer,\n size_t numel, int32_t num_experts) {\n const size_t tid = blockIdx.x * blockDim.x + threadIdx.x;\n const size_t stride = blockDim.x * gridDim.x;\n\n for (size_t i = tid; i < numel; i += stride) {\n int32_t expert_id = topk_ids[i];\n if (expert_id >= num_experts) {\n continue;\n }\n int32_t rank_post_pad = atomicAdd(&cumsum_buffer[expert_id], 1);\n sorted_token_ids[rank_post_pad] = i;\n }\n}\n\ntemplate <typename scalar_t, int TOPK>\n__global__ void moe_sum_kernel(\n scalar_t* __restrict__ out, // [..., d]\n const scalar_t* __restrict__ input, // [..., topk, d]\n const int d) {\n const int64_t token_idx = blockIdx.x;\n for (int64_t idx = threadIdx.x; idx < d; idx += blockDim.x) {\n scalar_t x = 0.0;\n#pragma unroll\n for (int k = 0; k < TOPK; ++k) {\n x += VLLM_LDG(&input[token_idx * TOPK * d + k * d + idx]);\n }\n out[token_idx * d + idx] = x;\n }\n}\n\ntemplate <typename scalar_t>\n__global__ void moe_align_block_size_small_batch_expert_kernel(\n const scalar_t* __restrict__ topk_ids,\n int32_t* __restrict__ sorted_token_ids, int32_t* __restrict__ expert_ids,\n int32_t* __restrict__ total_tokens_post_pad, int32_t num_experts,\n int32_t block_size, size_t numel, int32_t max_num_tokens_padded) {\n // Initialize sorted_token_ids with numel\n for (size_t it = threadIdx.x; it < max_num_tokens_padded; it += blockDim.x) {\n sorted_token_ids[it] = numel;\n }\n\n const size_t tid = threadIdx.x;\n const size_t stride = blockDim.x;\n\n extern __shared__ int32_t shared_mem[];\n int32_t* cumsum = shared_mem;\n int32_t* tokens_cnts = (int32_t*)(shared_mem + num_experts + 1);\n\n for (int i = 0; i < num_experts; ++i) {\n tokens_cnts[(threadIdx.x + 1) * num_experts + i] = 0;\n }\n\n for (size_t i = tid; i < numel; i += stride) {\n ++tokens_cnts[(threadIdx.x + 1) * num_experts + topk_ids[i]];\n }\n\n __syncthreads();\n\n if (threadIdx.x < num_experts) {\n tokens_cnts[threadIdx.x] = 0;\n for (int i = 1; i <= blockDim.x; ++i) {\n tokens_cnts[i * num_experts + threadIdx.x] +=\n tokens_cnts[(i - 1) * num_experts + threadIdx.x];\n }\n }\n\n __syncthreads();\n\n if (threadIdx.x == 0) {\n cumsum[0] = 0;\n for (int i = 1; i <= num_experts; ++i) {\n cumsum[i] =\n cumsum[i - 1] +\n CEILDIV(tokens_cnts[blockDim.x * num_experts + i - 1], block_size) *\n block_size;\n }\n *total_tokens_post_pad = static_cast<int32_t>(cumsum[num_experts]);\n }\n\n __syncthreads();\n\n if (threadIdx.x < num_experts) {\n for (int i = cumsum[threadIdx.x]; i < cumsum[threadIdx.x + 1];\n i += block_size) {\n expert_ids[i / block_size] = threadIdx.x;\n }\n }\n\n // Fill remaining expert_ids with 0\n const size_t fill_start_idx = cumsum[num_experts] / block_size + threadIdx.x;\n const size_t expert_ids_size = CEILDIV(max_num_tokens_padded, block_size);\n for (size_t i = fill_start_idx; i < expert_ids_size; i += blockDim.x) {\n expert_ids[i] = 0;\n }\n\n for (size_t i = tid; i < numel; i += stride) {\n int32_t expert_id = topk_ids[i];\n int32_t rank_post_pad =\n tokens_cnts[threadIdx.x * num_experts + expert_id] + cumsum[expert_id];\n sorted_token_ids[rank_post_pad] = i;\n ++tokens_cnts[threadIdx.x * num_experts + expert_id];\n }\n}\n\n} // namespace moe\n} // namespace vllm\n\n// taken from\n// https://github.com/sgl-project/sglang/blob/8b5f83ed3b7d2a49ad5c5cd5aa61c5d502f47dbc\nvoid moe_align_block_size(torch::Tensor topk_ids, int64_t num_experts,\n int64_t block_size, torch::Tensor sorted_token_ids,\n torch::Tensor experts_ids,\n torch::Tensor num_tokens_post_pad) {\n const cudaStream_t stream = at::cuda::getCurrentCUDAStream();\n\n int64_t padded_num_experts =\n ((num_experts + WARP_SIZE - 1) / WARP_SIZE) * WARP_SIZE;\n int experts_per_warp = WARP_SIZE;\n int threads = 1024;\n threads = ((threads + WARP_SIZE - 1) / WARP_SIZE) * WARP_SIZE;\n\n // BlockScan uses 1024 threads and assigns one thread per expert.\n TORCH_CHECK(padded_num_experts < 1024,\n \"padded_num_experts must be less than 1024\");\n\n VLLM_DISPATCH_INTEGRAL_AND_UNSIGNED_TYPES(\n topk_ids.scalar_type(), \"moe_align_block_size_kernel\", [&] {\n // calc needed amount of shared mem for `cumsum` tensors\n auto options_int =\n torch::TensorOptions().dtype(torch::kInt).device(topk_ids.device());\n torch::Tensor cumsum_buffer =\n torch::empty({num_experts + 1}, options_int);\n bool small_batch_expert_mode =\n (topk_ids.numel() < 1024) && (num_experts <= 64);\n\n if (small_batch_expert_mode) {\n const int32_t threads = max((int32_t)num_experts, WARP_SIZE);\n const int32_t shared_mem_size =\n ((threads + 1) * num_experts + (num_experts + 1)) *\n sizeof(int32_t);\n\n auto small_batch_expert_kernel =\n vllm::moe::moe_align_block_size_small_batch_expert_kernel<\n scalar_t>;\n small_batch_expert_kernel<<<1, threads, shared_mem_size, stream>>>(\n topk_ids.data_ptr<scalar_t>(),\n sorted_token_ids.data_ptr<int32_t>(),\n experts_ids.data_ptr<int32_t>(),\n num_tokens_post_pad.data_ptr<int32_t>(), num_experts, block_size,\n topk_ids.numel(), sorted_token_ids.size(0));\n } else {\n auto align_kernel = vllm::moe::moe_align_block_size_kernel<scalar_t>;\n\n size_t num_warps = CEILDIV(padded_num_experts, experts_per_warp);\n size_t shared_mem_size =\n num_warps * experts_per_warp * sizeof(int32_t);\n\n align_kernel<<<1, threads, shared_mem_size, stream>>>(\n topk_ids.data_ptr<scalar_t>(),\n sorted_token_ids.data_ptr<int32_t>(),\n experts_ids.data_ptr<int32_t>(),\n num_tokens_post_pad.data_ptr<int32_t>(), num_experts,\n padded_num_experts, experts_per_warp, block_size,\n topk_ids.numel(), cumsum_buffer.data_ptr<int32_t>(),\n sorted_token_ids.size(0));\n\n const int block_threads = std::min(256, (int)threads);\n const int num_blocks =\n (topk_ids.numel() + block_threads - 1) / block_threads;\n const int max_blocks = 65535;\n const int actual_blocks = std::min(num_blocks, max_blocks);\n\n auto sort_kernel =\n vllm::moe::count_and_sort_expert_tokens_kernel<scalar_t>;\n sort_kernel<<<actual_blocks, block_threads, 0, stream>>>(\n topk_ids.data_ptr<scalar_t>(),\n sorted_token_ids.data_ptr<int32_t>(),\n cumsum_buffer.data_ptr<int32_t>(), topk_ids.numel(), num_experts);\n }\n });\n}\n\nvoid batched_moe_align_block_size(int64_t max_tokens_per_batch,\n int64_t block_size,\n torch::Tensor const& batch_num_tokens,\n torch::Tensor sorted_ids,\n torch::Tensor batch_ids,\n torch::Tensor num_tokens_post_pad) {\n namespace batched_kernel = vllm::moe::batched_moe_align_block_size;\n\n const cudaStream_t stream = at::cuda::getCurrentCUDAStream();\n int32_t const B = batch_num_tokens.size(0);\n int32_t const num_blocks_per_batch =\n round_to_next_multiple_of(max_tokens_per_batch, block_size) / block_size;\n int32_t const num_blocks = num_blocks_per_batch * B;\n int64_t const sorted_ids_size = num_blocks * block_size;\n\n TORCH_CHECK(sorted_ids.size(0) == sorted_ids_size);\n TORCH_CHECK(batch_ids.size(0) == sorted_ids_size / block_size);\n TORCH_CHECK(num_tokens_post_pad.size(0) == 1);\n TORCH_CHECK(B <= batched_kernel::num_threads);\n\n batched_kernel::batched_moe_align_block_size_kernel<<<\n batched_kernel::num_blocks, batched_kernel::num_threads, 0, stream>>>(\n B, max_tokens_per_batch, block_size, batch_num_tokens.data_ptr<int32_t>(),\n sorted_ids.data_ptr<int32_t>(), batch_ids.data_ptr<int32_t>(),\n num_tokens_post_pad.data_ptr<int32_t>());\n}\n\nvoid moe_sum(torch::Tensor& input, // [num_tokens, topk, hidden_size]\n torch::Tensor& output) // [num_tokens, hidden_size]\n{\n const int hidden_size = input.size(-1);\n const auto num_tokens = output.numel() / hidden_size;\n const int topk = input.size(1);\n\n dim3 grid(num_tokens);\n dim3 block(std::min(hidden_size, 1024));\n const at::cuda::OptionalCUDAGuard device_guard(device_of(output));\n const cudaStream_t stream = at::cuda::getCurrentCUDAStream();\n\n switch (topk) {\n case 2:\n VLLM_DISPATCH_FLOATING_TYPES(input.scalar_type(), \"moe_sum_kernel\", [&] {\n vllm::moe::moe_sum_kernel<scalar_t, 2><<<grid, block, 0, stream>>>(\n output.data_ptr<scalar_t>(), input.data_ptr<scalar_t>(),\n hidden_size);\n });\n break;\n\n case 3:\n VLLM_DISPATCH_FLOATING_TYPES(input.scalar_type(), \"moe_sum_kernel\", [&] {\n vllm::moe::moe_sum_kernel<scalar_t, 3><<<grid, block, 0, stream>>>(\n output.data_ptr<scalar_t>(), input.data_ptr<scalar_t>(),\n hidden_size);\n });\n break;\n\n case 4:\n VLLM_DISPATCH_FLOATING_TYPES(input.scalar_type(), \"moe_sum_kernel\", [&] {\n vllm::moe::moe_sum_kernel<scalar_t, 4><<<grid, block, 0, stream>>>(\n output.data_ptr<scalar_t>(), input.data_ptr<scalar_t>(),\n hidden_size);\n });\n break;\n\n default:\n at::sum_out(output, input, 1);\n break;\n }\n}\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## Introduction\nThis PR optimize `moe_align_block_size` from three aspects:\n\n1. For a small batch size, use the smallest possible value for `max_num_tokens_padded`.\n\n2. In the CUDA Kernel, use additional thread or threadblock resources to fill `sorted_token_ids`. The previous CUDA Kernel used very few computational resources, and the filling of `sorted_token_ids` and the counting of experts were performed sequentially. Since `sorted_token_ids` is only used again at the very end of the CUDA kernel, I changed this to be parallelized to accelerate kernel execution.\n\n3. For EP, all invalid experts are filtered out directly when counting the number of experts. This accelerates the execution of `moe_align_block_size` and also leads to a cleaner and faster implementation for the subsequent MoE kernel.\n\n\n## Kernel Bench\n\nOn RTX 4090\n\n```\nmoe-align-block-size-performance:\n num_tokens num_experts topk ep_size main PR\n0 1.0 16.0 1.0 1.0 8.192000 6.144000\n1 1.0 16.0 1.0 8.0 12.288000 6.144000\n2 1.0 16.0 2.0 1.0 7.168000 6.080000\n3 1.0 16.0 2.0 8.0 11.264000 5.120000\n4 1.0 16.0 8.0 1.0 7.232000 5.120000\n5 1.0 16.0 8.0 8.0 12.224000 6.144000\n6 1.0 64.0 1.0 1.0 13.312000 9.216000\n7 1.0 64.0 1.0 8.0 17.408000 9.216000\n8 1.0 64.0 2.0 1.0 13.312000 9.216000\n9 1.0 64.0 2.0 8.0 17.408000 9.216000\n10 1.0 64.0 8.0 1.0 13.312000 9.216000\n11 1.0 64.0 8.0 8.0 17.408000 9.216000\n12 1.0 224.0 1.0 1.0 10.240000 7.168000\n13 1.0 224.0 1.0 8.0 14.336000 7.168000\n14 1.0 224.0 2.0 1.0 10.240000 7.168000\n15 1.0 224.0 2.0 8.0 14.336000 7.168000\n16 1.0 224.0 8.0 1.0 10.240000 7.168000\n17 1.0 224.0 8.0 8.0 14.336000 7.168000\n18 1.0 256.0 1.0 1.0 10.240000 7.168000\n19 1.0 256.0 1.0 8.0 14.336000 8.192000\n20 1.0 256.0 2.0 1.0 10.240000 7.168000\n21 1.0 256.0 2.0 8.0 14.336000 8.192000\n22 1.0 256.0 8.0 1.0 10.240000 7.168000\n23 1.0 256.0 8.0 8.0 14.336000 8.192000\n24 1.0 280.0 1.0 1.0 11.264000 7.168000\n25 1.0 280.0 1.0 8.0 15.360000 7.168000\n26 1.0 280.0 2.0 1.0 11.264000 7.168000\n27 1.0 280.0 2.0 8.0 15.360000 7.168000\n28 1.0 280.0 8.0 1.0 11.264000 7.168000\n29 1.0 280.0 8.0 8.0 15.360000 7.168000\n30 1.0 512.0 1.0 1.0 13.312000 7.168000\n31 1.0 512.0 1.0 8.0 18.432001 7.168000\n32 1.0 512.0 2.0 1.0 13.312000 7.168000\n33 1.0 512.0 2.0 8.0 18.432001 7.168000\n34 1.0 512.0 8.0 1.0 13.312000 7.168000\n35 1.0 512.0 8.0 8.0 18.432001 7.168000\n36 16.0 16.0 1.0 1.0 7.168000 6.080000\n37 16.0 16.0 1.0 8.0 11.264000 6.144000\n38 16.0 16.0 2.0 1.0 7.168000 5.120000\n39 16.0 16.0 2.0 8.0 12.288000 5.120000\n40 16.0 16.0 8.0 1.0 8.192000 6.144000\n41 16.0 16.0 8.0 8.0 13.312000 7.168000\n42 16.0 64.0 1.0 1.0 13.312000 9.216000\n43 16.0 64.0 1.0 8.0 17.408000 9.216000\n44 16.0 64.0 2.0 1.0 13.312000 9.216000\n45 16.0 64.0 2.0 8.0 17.408000 9.216000\n46 16.0 64.0 8.0 1.0 13.312000 9.312000\n47 16.0 64.0 8.0 8.0 17.408000 9.216000\n48 16.0 224.0 1.0 1.0 10.240000 7.168000\n49 16.0 224.0 1.0 8.0 14.336000 8.192000\n50 16.0 224.0 2.0 1.0 10.240000 7.168000\n51 16.0 224.0 2.0 8.0 14.336000 8.192000\n52 16.0 224.0 8.0 1.0 10.240000 7.168000\n53 16.0 224.0 8.0 8.0 14.336000 8.192000\n54 16.0 256.0 1.0 1.0 10.240000 7.168000\n55 16.0 256.0 1.0 8.0 14.336000 8.192000\n56 16.0 256.0 2.0 1.0 10.240000 7.168000\n57 16.0 256.0 2.0 8.0 14.336000 8.192000\n58 16.0 256.0 8.0 1.0 10.240000 7.168000\n59 16.0 256.0 8.0 8.0 14.336000 8.192000\n60 16.0 280.0 1.0 1.0 11.264000 7.168000\n61 16.0 280.0 1.0 8.0 15.360000 8.192000\n62 16.0 280.0 2.0 1.0 11.136000 7.168000\n63 16.0 280.0 2.0 8.0 15.360000 8.192000\n64 16.0 280.0 8.0 1.0 11.264000 7.168000\n65 16.0 280.0 8.0 8.0 15.360000 8.192000\n66 16.0 512.0 1.0 1.0 13.312000 7.168000\n67 16.0 512.0 1.0 8.0 18.432001 8.192000\n68 16.0 512.0 2.0 1.0 13.312000 7.168000\n69 16.0 512.0 2.0 8.0 18.432001 8.192000\n70 16.0 512.0 8.0 1.0 13.312000 8.128000\n71 16.0 512.0 8.0 8.0 18.432001 8.192000\n72 256.0 16.0 1.0 1.0 9.216000 7.168000\n73 256.0 16.0 1.0 8.0 13.312000 8.192000\n74 256.0 16.0 2.0 1.0 12.288000 10.240000\n75 256.0 16.0 2.0 8.0 15.360000 11.264000\n76 256.0 16.0 8.0 1.0 8.192000 8.192000\n77 256.0 16.0 8.0 8.0 12.288000 8.192000\n78 256.0 64.0 1.0 1.0 14.336000 10.240000\n79 256.0 64.0 1.0 8.0 18.432001 10.736000\n80 256.0 64.0 2.0 1.0 14.336000 11.264000\n81 256.0 64.0 2.0 8.0 18.432001 12.288000\n82 256.0 64.0 8.0 1.0 9.216000 8.192000\n83 256.0 64.0 8.0 8.0 12.288000 8.192000\n84 256.0 224.0 1.0 1.0 10.240000 8.192000\n85 256.0 224.0 1.0 8.0 14.432000 8.192000\n86 256.0 224.0 2.0 1.0 10.240000 8.192000\n87 256.0 224.0 2.0 8.0 14.336000 8.192000\n88 256.0 224.0 8.0 1.0 11.264000 8.192000\n89 256.0 224.0 8.0 8.0 15.360000 8.192000\n90 256.0 256.0 1.0 1.0 10.240000 8.192000\n91 256.0 256.0 1.0 8.0 15.360000 8.192000\n92 256.0 256.0 2.0 1.0 10.240000 8.192000\n93 256.0 256.0 2.0 8.0 15.360000 8.192000\n94 256.0 256.0 8.0 1.0 11.264000 9.216000\n95 256.0 256.0 8.0 8.0 16.384000 8.192000\n96 256.0 280.0 1.0 1.0 11.264000 8.192000\n97 256.0 280.0 1.0 8.0 15.360000 8.192000\n98 256.0 280.0 2.0 1.0 11.264000 9.216000\n99 256.0 280.0 2.0 8.0 16.384000 9.216000\n100 256.0 280.0 8.0 1.0 11.264000 9.216000\n101 256.0 280.0 8.0 8.0 16.527999 9.216000\n102 256.0 512.0 1.0 1.0 13.312000 8.192000\n103 256.0 512.0 1.0 8.0 18.592000 8.192000\n104 256.0 512.0 2.0 1.0 13.312000 11.264000\n105 256.0 512.0 2.0 8.0 19.455999 11.264000\n106 256.0 512.0 8.0 1.0 14.336000 11.264000\n107 256.0 512.0 8.0 8.0 19.455999 11.264000\n108 4096.0 16.0 1.0 1.0 9.216000 9.216000\n109 4096.0 16.0 1.0 8.0 13.312000 9.216000\n110 4096.0 16.0 2.0 1.0 11.264000 11.264000\n111 4096.0 16.0 2.0 8.0 15.360000 10.240000\n112 4096.0 16.0 8.0 1.0 22.528000 20.608000\n113 4096.0 16.0 8.0 8.0 26.624000 19.455999\n114 4096.0 64.0 1.0 1.0 10.240000 9.216000\n115 4096.0 64.0 1.0 8.0 14.336000 9.216000\n116 4096.0 64.0 2.0 1.0 12.288000 11.264000\n117 4096.0 64.0 2.0 8.0 16.384000 10.240000\n118 4096.0 64.0 8.0 1.0 25.599999 23.552001\n119 4096.0 64.0 8.0 8.0 30.719999 18.432001\n120 4096.0 224.0 1.0 1.0 12.288000 9.216000\n121 4096.0 224.0 1.0 8.0 16.384000 9.216000\n122 4096.0 224.0 2.0 1.0 14.336000 11.264000\n123 4096.0 224.0 2.0 8.0 18.432001 10.240000\n124 4096.0 224.0 8.0 1.0 24.576001 20.479999\n125 4096.0 224.0 8.0 8.0 28.672000 19.455999\n126 4096.0 256.0 1.0 1.0 12.288000 9.216000\n127 4096.0 256.0 1.0 8.0 17.408000 9.216000\n128 4096.0 256.0 2.0 1.0 14.336000 11.264000\n129 4096.0 256.0 2.0 8.0 19.455999 10.240000\n130 4096.0 256.0 8.0 1.0 27.648000 23.552001\n131 4096.0 256.0 8.0 8.0 32.768000 19.455999\n132 4096.0 280.0 1.0 1.0 12.288000 9.216000\n133 4096.0 280.0 1.0 8.0 17.408000 9.216000\n134 4096.0 280.0 2.0 1.0 15.360000 11.264000\n135 4096.0 280.0 2.0 8.0 19.616000 10.240000\n136 4096.0 280.0 8.0 1.0 25.599999 21.504000\n137 4096.0 280.0 8.0 8.0 31.727999 19.455999\n138 4096.0 512.0 1.0 1.0 15.360000 12.288000\n139 4096.0 512.0 1.0 8.0 20.479999 12.192000\n140 4096.0 512.0 2.0 1.0 17.408000 13.280000\n141 4096.0 512.0 2.0 8.0 22.528000 12.288000\n142 4096.0 512.0 8.0 1.0 28.672000 21.504000\n143 4096.0 512.0 8.0 8.0 34.655999 19.455999\n```\n\n\n## Kernel Accuracy Test\n\nTested with\n\n```\npytest -sv test_moe_align_block_size.py::test_moe_align_block_size\n\npytest -sv test_moe_align_block_size.py::test_moe_align_block_size_with_expert_map\n```\n\nAll test cases are passed.\n\n## E2E Accuracy Test\n\nGSM8K (2-shot)\n\nWith Triton Kernel\n\n```\nvllm serve /data/pretrained_model/Qwen/Qwen1.5-MoE-A2.7B-Chat/ -tp 4 --served-model-name model --port 8002 --gpu-memory-utilization 0.75 --enable-expert-parallel\n\n\nlm_eval \\\n --model local-chat-completions \\\n --tasks gsm8k \\\n --num_fewshot 2 \\\n --batch_size auto \\\n --model_args \"model=model,base_url=http://localhost:8002/v1/chat/completions,max_gen_toks=512,num_concurrent=128,max_length=4096\" \\\n --apply_chat_template\n\n\n|Tasks|Version| Filter |n-shot| Metric | |Value | |Stderr|\n|-----|------:|----------------|-----:|-----------|---|-----:|---|-----:|\n|gsm8k| 3|flexible-extract| 2|exact_match|↑ |0.5095|± |0.0138|\n| | |strict-match | 2|exact_match|↑ |0.0258|± |0.0044|\n```\n\n\nWith Marlin Kernel\n\n```\nvllm serve /data/pretrained_model/Qwen/Qwen1.5-MoE-A2.7B-Chat-GPTQ-Int4/ -tp 4 --served-model-name model --port 8002 --gpu-memory-utilization 0.75 --enable-expert-parallel\n\n\nlm_eval \\\n --model local-chat-completions \\\n --tasks gsm8k \\\n --num_fewshot 2 \\\n --batch_size auto \\\n --model_args \"model=model,base_url=http://localhost:8002/v1/chat/completions,max_gen_toks=512,num_concurrent=128,max_length=4096\" \\\n --apply_chat_template\n\n\n|Tasks|Version| Filter |n-shot| Metric | |Value | |Stderr|\n|-----|------:|----------------|-----:|-----------|---|-----:|---|-----:|\n|gsm8k| 3|flexible-extract| 2|exact_match|↑ |0.4723|± |0.0138|\n| | |strict-match | 2|exact_match|↑ |0.0190|± |0.0038|\n```\n"},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":394,"cells":{"repo":{"kind":"string","value":"vllm"},"commit":{"kind":"string","value":"879ddb09c3b7b5a21f75e46ded148ce70f1c486e"},"date":{"kind":"string","value":"2025-12-07T17:58:47+08:00"},"pr_number":{"kind":"number","value":29642,"string":"29,642"},"pr_url":{"kind":"string","value":"https://github.com/vllm-project/vllm/pull/29642"},"title":{"kind":"string","value":"[Kernel][MoE] optimize `moe_align_block_size` (#29642)"},"message":{"kind":"string","value":"[Kernel][MoE] optimize `moe_align_block_size` (#29642)\n\nSigned-off-by: Jinzhen Lin <jinzhen.ljz@antgroup.com>\nCo-authored-by: Jee Jee Li <pandaleefree@gmail.com>"},"path":{"kind":"string","value":"csrc/moe/moe_ops.h"},"language":{"kind":"string","value":"cpp"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"#pragma once\n\n#include <torch/all.h>\n\nvoid topk_softmax(torch::Tensor& topk_weights, torch::Tensor& topk_indices,\n torch::Tensor& token_expert_indices,\n torch::Tensor& gating_output, bool renormalize);\n\nvoid moe_sum(torch::Tensor& input, torch::Tensor& output);\n\nvoid moe_align_block_size(torch::Tensor topk_ids, int64_t num_experts,\n int64_t block_size, torch::Tensor sorted_token_ids,\n torch::Tensor experts_ids,\n torch::Tensor num_tokens_post_pad);\n\nvoid batched_moe_align_block_size(int64_t max_tokens_per_batch,\n int64_t block_size,\n torch::Tensor const& expert_num_tokens,\n torch::Tensor sorted_ids,\n torch::Tensor expert_ids,\n torch::Tensor num_tokens_post_pad);\n\nvoid moe_lora_align_block_size(\n torch::Tensor topk_ids, torch::Tensor token_lora_mapping,\n int64_t num_experts, int64_t block_size, int64_t max_loras,\n int64_t max_num_tokens_padded, int64_t max_num_m_blocks,\n torch::Tensor sorted_token_ids, torch::Tensor expert_ids,\n torch::Tensor num_tokens_post_pad, torch::Tensor adapter_enabled,\n torch::Tensor lora_ids);\n#ifndef USE_ROCM\ntorch::Tensor moe_wna16_gemm(torch::Tensor input, torch::Tensor output,\n torch::Tensor b_qweight, torch::Tensor b_scales,\n std::optional<torch::Tensor> b_qzeros,\n std::optional<torch::Tensor> topk_weights,\n torch::Tensor sorted_token_ids,\n torch::Tensor expert_ids,\n torch::Tensor num_tokens_post_pad, int64_t top_k,\n int64_t BLOCK_SIZE_M, int64_t BLOCK_SIZE_N,\n int64_t BLOCK_SIZE_K, int64_t bit);\n\nstd::tuple<torch::Tensor, torch::Tensor> grouped_topk(\n torch::Tensor const& scores, int64_t n_group, int64_t topk_group,\n int64_t topk, bool renormalize, double routed_scaling_factor,\n torch::Tensor const& bias, int64_t scoring_func);\n#endif\n\nbool moe_permute_unpermute_supported();\n\nvoid shuffle_rows(const torch::Tensor& input_tensor,\n const torch::Tensor& dst2src_map,\n torch::Tensor& output_tensor);"},"after_code":{"kind":"string","value":"#pragma once\n\n#include <torch/all.h>\n\nvoid topk_softmax(torch::Tensor& topk_weights, torch::Tensor& topk_indices,\n torch::Tensor& token_expert_indices,\n torch::Tensor& gating_output, bool renormalize);\n\nvoid moe_sum(torch::Tensor& input, torch::Tensor& output);\n\nvoid moe_align_block_size(torch::Tensor topk_ids, int64_t num_experts,\n int64_t block_size, torch::Tensor sorted_token_ids,\n torch::Tensor experts_ids,\n torch::Tensor num_tokens_post_pad,\n std::optional<torch::Tensor> maybe_expert_map);\n\nvoid batched_moe_align_block_size(int64_t max_tokens_per_batch,\n int64_t block_size,\n torch::Tensor const& expert_num_tokens,\n torch::Tensor sorted_ids,\n torch::Tensor expert_ids,\n torch::Tensor num_tokens_post_pad);\n\nvoid moe_lora_align_block_size(\n torch::Tensor topk_ids, torch::Tensor token_lora_mapping,\n int64_t num_experts, int64_t block_size, int64_t max_loras,\n int64_t max_num_tokens_padded, int64_t max_num_m_blocks,\n torch::Tensor sorted_token_ids, torch::Tensor expert_ids,\n torch::Tensor num_tokens_post_pad, torch::Tensor adapter_enabled,\n torch::Tensor lora_ids);\n#ifndef USE_ROCM\ntorch::Tensor moe_wna16_gemm(torch::Tensor input, torch::Tensor output,\n torch::Tensor b_qweight, torch::Tensor b_scales,\n std::optional<torch::Tensor> b_qzeros,\n std::optional<torch::Tensor> topk_weights,\n torch::Tensor sorted_token_ids,\n torch::Tensor expert_ids,\n torch::Tensor num_tokens_post_pad, int64_t top_k,\n int64_t BLOCK_SIZE_M, int64_t BLOCK_SIZE_N,\n int64_t BLOCK_SIZE_K, int64_t bit);\n\nstd::tuple<torch::Tensor, torch::Tensor> grouped_topk(\n torch::Tensor const& scores, int64_t n_group, int64_t topk_group,\n int64_t topk, bool renormalize, double routed_scaling_factor,\n torch::Tensor const& bias, int64_t scoring_func);\n#endif\n\nbool moe_permute_unpermute_supported();\n\nvoid shuffle_rows(const torch::Tensor& input_tensor,\n const torch::Tensor& dst2src_map,\n torch::Tensor& output_tensor);"},"diff":{"kind":"string","value":"--- csrc/moe/moe_ops.h\n+++ csrc/moe/moe_ops.h\n@@ -11,7 +11,8 @@\n void moe_align_block_size(torch::Tensor topk_ids, int64_t num_experts,\n int64_t block_size, torch::Tensor sorted_token_ids,\n torch::Tensor experts_ids,\n- torch::Tensor num_tokens_post_pad);\n+ torch::Tensor num_tokens_post_pad,\n+ std::optional<torch::Tensor> maybe_expert_map);\n \n void batched_moe_align_block_size(int64_t max_tokens_per_batch,\n int64_t block_size,"},"lines_added":{"kind":"number","value":2,"string":"2"},"lines_removed":{"kind":"number","value":1,"string":"1"},"files_in_commit":{"kind":"number","value":6,"string":"6"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cpp kernel file from vllm (csrc/moe/moe_ops.h).\n\nGoal: [Kernel][MoE] optimize `moe_align_block_size`\nTarget hardware: unspecified\nTarget models: unspecified\n\nCurrent file:\n```cpp\n#pragma once\n\n#include <torch/all.h>\n\nvoid topk_softmax(torch::Tensor& topk_weights, torch::Tensor& topk_indices,\n torch::Tensor& token_expert_indices,\n torch::Tensor& gating_output, bool renormalize);\n\nvoid moe_sum(torch::Tensor& input, torch::Tensor& output);\n\nvoid moe_align_block_size(torch::Tensor topk_ids, int64_t num_experts,\n int64_t block_size, torch::Tensor sorted_token_ids,\n torch::Tensor experts_ids,\n torch::Tensor num_tokens_post_pad);\n\nvoid batched_moe_align_block_size(int64_t max_tokens_per_batch,\n int64_t block_size,\n torch::Tensor const& expert_num_tokens,\n torch::Tensor sorted_ids,\n torch::Tensor expert_ids,\n torch::Tensor num_tokens_post_pad);\n\nvoid moe_lora_align_block_size(\n torch::Tensor topk_ids, torch::Tensor token_lora_mapping,\n int64_t num_experts, int64_t block_size, int64_t max_loras,\n int64_t max_num_tokens_padded, int64_t max_num_m_blocks,\n torch::Tensor sorted_token_ids, torch::Tensor expert_ids,\n torch::Tensor num_tokens_post_pad, torch::Tensor adapter_enabled,\n torch::Tensor lora_ids);\n#ifndef USE_ROCM\ntorch::Tensor moe_wna16_gemm(torch::Tensor input, torch::Tensor output,\n torch::Tensor b_qweight, torch::Tensor b_scales,\n std::optional<torch::Tensor> b_qzeros,\n std::optional<torch::Tensor> topk_weights,\n torch::Tensor sorted_token_ids,\n torch::Tensor expert_ids,\n torch::Tensor num_tokens_post_pad, int64_t top_k,\n int64_t BLOCK_SIZE_M, int64_t BLOCK_SIZE_N,\n int64_t BLOCK_SIZE_K, int64_t bit);\n\nstd::tuple<torch::Tensor, torch::Tensor> grouped_topk(\n torch::Tensor const& scores, int64_t n_group, int64_t topk_group,\n int64_t topk, bool renormalize, double routed_scaling_factor,\n torch::Tensor const& bias, int64_t scoring_func);\n#endif\n\nbool moe_permute_unpermute_supported();\n\nvoid shuffle_rows(const torch::Tensor& input_tensor,\n const torch::Tensor& dst2src_map,\n torch::Tensor& output_tensor);\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## Introduction\nThis PR optimize `moe_align_block_size` from three aspects:\n\n1. For a small batch size, use the smallest possible value for `max_num_tokens_padded`.\n\n2. In the CUDA Kernel, use additional thread or threadblock resources to fill `sorted_token_ids`. The previous CUDA Kernel used very few computational resources, and the filling of `sorted_token_ids` and the counting of experts were performed sequentially. Since `sorted_token_ids` is only used again at the very end of the CUDA kernel, I changed this to be parallelized to accelerate kernel execution.\n\n3. For EP, all invalid experts are filtered out directly when counting the number of experts. This accelerates the execution of `moe_align_block_size` and also leads to a cleaner and faster implementation for the subsequent MoE kernel.\n\n\n## Kernel Bench\n\nOn RTX 4090\n\n```\nmoe-align-block-size-performance:\n num_tokens num_experts topk ep_size main PR\n0 1.0 16.0 1.0 1.0 8.192000 6.144000\n1 1.0 16.0 1.0 8.0 12.288000 6.144000\n2 1.0 16.0 2.0 1.0 7.168000 6.080000\n3 1.0 16.0 2.0 8.0 11.264000 5.120000\n4 1.0 16.0 8.0 1.0 7.232000 5.120000\n5 1.0 16.0 8.0 8.0 12.224000 6.144000\n6 1.0 64.0 1.0 1.0 13.312000 9.216000\n7 1.0 64.0 1.0 8.0 17.408000 9.216000\n8 1.0 64.0 2.0 1.0 13.312000 9.216000\n9 1.0 64.0 2.0 8.0 17.408000 9.216000\n10 1.0 64.0 8.0 1.0 13.312000 9.216000\n11 1.0 64.0 8.0 8.0 17.408000 9.216000\n12 1.0 224.0 1.0 1.0 10.240000 7.168000\n13 1.0 224.0 1.0 8.0 14.336000 7.168000\n14 1.0 224.0 2.0 1.0 10.240000 7.168000\n15 1.0 224.0 2.0 8.0 14.336000 7.168000\n16 1.0 224.0 8.0 1.0 10.240000 7.168000\n17 1.0 224.0 8.0 8.0 14.336000 7.168000\n18 1.0 256.0 1.0 1.0 10.240000 7.168000\n19 1.0 256.0 1.0 8.0 14.336000 8.192000\n20 1.0 256.0 2.0 1.0 10.240000 7.168000\n21 1.0 256.0 2.0 8.0 14.336000 8.192000\n22 1.0 256.0 8.0 1.0 10.240000 7.168000\n23 1.0 256.0 8.0 8.0 14.336000 8.192000\n24 1.0 280.0 1.0 1.0 11.264000 7.168000\n25 1.0 280.0 1.0 8.0 15.360000 7.168000\n26 1.0 280.0 2.0 1.0 11.264000 7.168000\n27 1.0 280.0 2.0 8.0 15.360000 7.168000\n28 1.0 280.0 8.0 1.0 11.264000 7.168000\n29 1.0 280.0 8.0 8.0 15.360000 7.168000\n30 1.0 512.0 1.0 1.0 13.312000 7.168000\n31 1.0 512.0 1.0 8.0 18.432001 7.168000\n32 1.0 512.0 2.0 1.0 13.312000 7.168000\n33 1.0 512.0 2.0 8.0 18.432001 7.168000\n34 1.0 512.0 8.0 1.0 13.312000 7.168000\n35 1.0 512.0 8.0 8.0 18.432001 7.168000\n36 16.0 16.0 1.0 1.0 7.168000 6.080000\n37 16.0 16.0 1.0 8.0 11.264000 6.144000\n38 16.0 16.0 2.0 1.0 7.168000 5.120000\n39 16.0 16.0 2.0 8.0 12.288000 5.120000\n40 16.0 16.0 8.0 1.0 8.192000 6.144000\n41 16.0 16.0 8.0 8.0 13.312000 7.168000\n42 16.0 64.0 1.0 1.0 13.312000 9.216000\n43 16.0 64.0 1.0 8.0 17.408000 9.216000\n44 16.0 64.0 2.0 1.0 13.312000 9.216000\n45 16.0 64.0 2.0 8.0 17.408000 9.216000\n46 16.0 64.0 8.0 1.0 13.312000 9.312000\n47 16.0 64.0 8.0 8.0 17.408000 9.216000\n48 16.0 224.0 1.0 1.0 10.240000 7.168000\n49 16.0 224.0 1.0 8.0 14.336000 8.192000\n50 16.0 224.0 2.0 1.0 10.240000 7.168000\n51 16.0 224.0 2.0 8.0 14.336000 8.192000\n52 16.0 224.0 8.0 1.0 10.240000 7.168000\n53 16.0 224.0 8.0 8.0 14.336000 8.192000\n54 16.0 256.0 1.0 1.0 10.240000 7.168000\n55 16.0 256.0 1.0 8.0 14.336000 8.192000\n56 16.0 256.0 2.0 1.0 10.240000 7.168000\n57 16.0 256.0 2.0 8.0 14.336000 8.192000\n58 16.0 256.0 8.0 1.0 10.240000 7.168000\n59 16.0 256.0 8.0 8.0 14.336000 8.192000\n60 16.0 280.0 1.0 1.0 11.264000 7.168000\n61 16.0 280.0 1.0 8.0 15.360000 8.192000\n62 16.0 280.0 2.0 1.0 11.136000 7.168000\n63 16.0 280.0 2.0 8.0 15.360000 8.192000\n64 16.0 280.0 8.0 1.0 11.264000 7.168000\n65 16.0 280.0 8.0 8.0 15.360000 8.192000\n66 16.0 512.0 1.0 1.0 13.312000 7.168000\n67 16.0 512.0 1.0 8.0 18.432001 8.192000\n68 16.0 512.0 2.0 1.0 13.312000 7.168000\n69 16.0 512.0 2.0 8.0 18.432001 8.192000\n70 16.0 512.0 8.0 1.0 13.312000 8.128000\n71 16.0 512.0 8.0 8.0 18.432001 8.192000\n72 256.0 16.0 1.0 1.0 9.216000 7.168000\n73 256.0 16.0 1.0 8.0 13.312000 8.192000\n74 256.0 16.0 2.0 1.0 12.288000 10.240000\n75 256.0 16.0 2.0 8.0 15.360000 11.264000\n76 256.0 16.0 8.0 1.0 8.192000 8.192000\n77 256.0 16.0 8.0 8.0 12.288000 8.192000\n78 256.0 64.0 1.0 1.0 14.336000 10.240000\n79 256.0 64.0 1.0 8.0 18.432001 10.736000\n80 256.0 64.0 2.0 1.0 14.336000 11.264000\n81 256.0 64.0 2.0 8.0 18.432001 12.288000\n82 256.0 64.0 8.0 1.0 9.216000 8.192000\n83 256.0 64.0 8.0 8.0 12.288000 8.192000\n84 256.0 224.0 1.0 1.0 10.240000 8.192000\n85 256.0 224.0 1.0 8.0 14.432000 8.192000\n86 256.0 224.0 2.0 1.0 10.240000 8.192000\n87 256.0 224.0 2.0 8.0 14.336000 8.192000\n88 256.0 224.0 8.0 1.0 11.264000 8.192000\n89 256.0 224.0 8.0 8.0 15.360000 8.192000\n90 256.0 256.0 1.0 1.0 10.240000 8.192000\n91 256.0 256.0 1.0 8.0 15.360000 8.192000\n92 256.0 256.0 2.0 1.0 10.240000 8.192000\n93 256.0 256.0 2.0 8.0 15.360000 8.192000\n94 256.0 256.0 8.0 1.0 11.264000 9.216000\n95 256.0 256.0 8.0 8.0 16.384000 8.192000\n96 256.0 280.0 1.0 1.0 11.264000 8.192000\n97 256.0 280.0 1.0 8.0 15.360000 8.192000\n98 256.0 280.0 2.0 1.0 11.264000 9.216000\n99 256.0 280.0 2.0 8.0 16.384000 9.216000\n100 256.0 280.0 8.0 1.0 11.264000 9.216000\n101 256.0 280.0 8.0 8.0 16.527999 9.216000\n102 256.0 512.0 1.0 1.0 13.312000 8.192000\n103 256.0 512.0 1.0 8.0 18.592000 8.192000\n104 256.0 512.0 2.0 1.0 13.312000 11.264000\n105 256.0 512.0 2.0 8.0 19.455999 11.264000\n106 256.0 512.0 8.0 1.0 14.336000 11.264000\n107 256.0 512.0 8.0 8.0 19.455999 11.264000\n108 4096.0 16.0 1.0 1.0 9.216000 9.216000\n109 4096.0 16.0 1.0 8.0 13.312000 9.216000\n110 4096.0 16.0 2.0 1.0 11.264000 11.264000\n111 4096.0 16.0 2.0 8.0 15.360000 10.240000\n112 4096.0 16.0 8.0 1.0 22.528000 20.608000\n113 4096.0 16.0 8.0 8.0 26.624000 19.455999\n114 4096.0 64.0 1.0 1.0 10.240000 9.216000\n115 4096.0 64.0 1.0 8.0 14.336000 9.216000\n116 4096.0 64.0 2.0 1.0 12.288000 11.264000\n117 4096.0 64.0 2.0 8.0 16.384000 10.240000\n118 4096.0 64.0 8.0 1.0 25.599999 23.552001\n119 4096.0 64.0 8.0 8.0 30.719999 18.432001\n120 4096.0 224.0 1.0 1.0 12.288000 9.216000\n121 4096.0 224.0 1.0 8.0 16.384000 9.216000\n122 4096.0 224.0 2.0 1.0 14.336000 11.264000\n123 4096.0 224.0 2.0 8.0 18.432001 10.240000\n124 4096.0 224.0 8.0 1.0 24.576001 20.479999\n125 4096.0 224.0 8.0 8.0 28.672000 19.455999\n126 4096.0 256.0 1.0 1.0 12.288000 9.216000\n127 4096.0 256.0 1.0 8.0 17.408000 9.216000\n128 4096.0 256.0 2.0 1.0 14.336000 11.264000\n129 4096.0 256.0 2.0 8.0 19.455999 10.240000\n130 4096.0 256.0 8.0 1.0 27.648000 23.552001\n131 4096.0 256.0 8.0 8.0 32.768000 19.455999\n132 4096.0 280.0 1.0 1.0 12.288000 9.216000\n133 4096.0 280.0 1.0 8.0 17.408000 9.216000\n134 4096.0 280.0 2.0 1.0 15.360000 11.264000\n135 4096.0 280.0 2.0 8.0 19.616000 10.240000\n136 4096.0 280.0 8.0 1.0 25.599999 21.504000\n137 4096.0 280.0 8.0 8.0 31.727999 19.455999\n138 4096.0 512.0 1.0 1.0 15.360000 12.288000\n139 4096.0 512.0 1.0 8.0 20.479999 12.192000\n140 4096.0 512.0 2.0 1.0 17.408000 13.280000\n141 4096.0 512.0 2.0 8.0 22.528000 12.288000\n142 4096.0 512.0 8.0 1.0 28.672000 21.504000\n143 4096.0 512.0 8.0 8.0 34.655999 19.455999\n```\n\n\n## Kernel Accuracy Test\n\nTested with\n\n```\npytest -sv test_moe_align_block_size.py::test_moe_align_block_size\n\npytest -sv test_moe_align_block_size.py::test_moe_align_block_size_with_expert_map\n```\n\nAll test cases are passed.\n\n## E2E Accuracy Test\n\nGSM8K (2-shot)\n\nWith Triton Kernel\n\n```\nvllm serve /data/pretrained_model/Qwen/Qwen1.5-MoE-A2.7B-Chat/ -tp 4 --served-model-name model --port 8002 --gpu-memory-utilization 0.75 --enable-expert-parallel\n\n\nlm_eval \\\n --model local-chat-completions \\\n --tasks gsm8k \\\n --num_fewshot 2 \\\n --batch_size auto \\\n --model_args \"model=model,base_url=http://localhost:8002/v1/chat/completions,max_gen_toks=512,num_concurrent=128,max_length=4096\" \\\n --apply_chat_template\n\n\n|Tasks|Version| Filter |n-shot| Metric | |Value | |Stderr|\n|-----|------:|----------------|-----:|-----------|---|-----:|---|-----:|\n|gsm8k| 3|flexible-extract| 2|exact_match|↑ |0.5095|± |0.0138|\n| | |strict-match | 2|exact_match|↑ |0.0258|± |0.0044|\n```\n\n\nWith Marlin Kernel\n\n```\nvllm serve /data/pretrained_model/Qwen/Qwen1.5-MoE-A2.7B-Chat-GPTQ-Int4/ -tp 4 --served-model-name model --port 8002 --gpu-memory-utilization 0.75 --enable-expert-parallel\n\n\nlm_eval \\\n --model local-chat-completions \\\n --tasks gsm8k \\\n --num_fewshot 2 \\\n --batch_size auto \\\n --model_args \"model=model,base_url=http://localhost:8002/v1/chat/completions,max_gen_toks=512,num_concurrent=128,max_length=4096\" \\\n --apply_chat_template\n\n\n|Tasks|Version| Filter |n-shot| Metric | |Value | |Stderr|\n|-----|------:|----------------|-----:|-----------|---|-----:|---|-----:|\n|gsm8k| 3|flexible-extract| 2|exact_match|↑ |0.4723|± |0.0138|\n| | |strict-match | 2|exact_match|↑ |0.0190|± |0.0038|\n```\n"},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":395,"cells":{"repo":{"kind":"string","value":"vllm"},"commit":{"kind":"string","value":"879ddb09c3b7b5a21f75e46ded148ce70f1c486e"},"date":{"kind":"string","value":"2025-12-07T17:58:47+08:00"},"pr_number":{"kind":"number","value":29642,"string":"29,642"},"pr_url":{"kind":"string","value":"https://github.com/vllm-project/vllm/pull/29642"},"title":{"kind":"string","value":"[Kernel][MoE] optimize `moe_align_block_size` (#29642)"},"message":{"kind":"string","value":"[Kernel][MoE] optimize `moe_align_block_size` (#29642)\n\nSigned-off-by: Jinzhen Lin <jinzhen.ljz@antgroup.com>\nCo-authored-by: Jee Jee Li <pandaleefree@gmail.com>"},"path":{"kind":"string","value":"csrc/moe/torch_bindings.cpp"},"language":{"kind":"string","value":"cpp"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"#include \"core/registration.h\"\n#include \"moe_ops.h\"\n\nTORCH_LIBRARY_EXPAND(TORCH_EXTENSION_NAME, m) {\n // Apply topk softmax to the gating outputs.\n m.def(\n \"topk_softmax(Tensor! topk_weights, Tensor! topk_indices, Tensor! \"\n \"token_expert_indices, Tensor gating_output, bool renormalize) -> ()\");\n m.impl(\"topk_softmax\", torch::kCUDA, &topk_softmax);\n\n // Calculate the result of moe by summing up the partial results\n // from all selected experts.\n m.def(\"moe_sum(Tensor input, Tensor! output) -> ()\");\n m.impl(\"moe_sum\", torch::kCUDA, &moe_sum);\n\n // Aligning the number of tokens to be processed by each expert such\n // that it is divisible by the block size.\n m.def(\n \"moe_align_block_size(Tensor topk_ids, int num_experts,\"\n \" int block_size, Tensor! sorted_token_ids,\"\n \" Tensor! experts_ids,\"\n \" Tensor! num_tokens_post_pad) -> ()\");\n m.impl(\"moe_align_block_size\", torch::kCUDA, &moe_align_block_size);\n\n // Aligning the number of tokens to be processed by each expert such\n // that it is divisible by the block size, but for the batched case.\n m.def(\n \"batched_moe_align_block_size(int max_tokens_per_batch,\"\n \" int block_size, Tensor expert_num_tokens,\"\n \" Tensor! sorted_token_ids,\"\n \" Tensor! experts_ids,\"\n \" Tensor! num_tokens_post_pad) -> ()\");\n m.impl(\"batched_moe_align_block_size\", torch::kCUDA,\n &batched_moe_align_block_size);\n\n // Aligning the number of tokens to be processed by each expert such\n // that it is divisible by the block size.\n m.def(\n \"moe_lora_align_block_size(Tensor topk_ids,\"\n \" Tensor token_lora_mapping,\"\n \" int num_experts,\"\n \" int block_size, int max_loras, \"\n \" int max_num_tokens_padded, \"\n \" int max_num_m_blocks, \"\n \" Tensor !sorted_token_ids,\"\n \" Tensor !experts_ids,\"\n \" Tensor !num_tokens_post_pad,\"\n \" Tensor !adapter_enabled,\"\n \" Tensor !lora_ids) -> () \");\n m.impl(\"moe_lora_align_block_size\", torch::kCUDA, &moe_lora_align_block_size);\n\n#ifndef USE_ROCM\n m.def(\n \"moe_wna16_gemm(Tensor input, Tensor! output, Tensor b_qweight, \"\n \"Tensor b_scales, Tensor? b_qzeros, \"\n \"Tensor? topk_weights, Tensor sorted_token_ids, \"\n \"Tensor expert_ids, Tensor num_tokens_post_pad, \"\n \"int top_k, int BLOCK_SIZE_M, int BLOCK_SIZE_N, int BLOCK_SIZE_K, \"\n \"int bit) -> Tensor\");\n\n m.impl(\"moe_wna16_gemm\", torch::kCUDA, &moe_wna16_gemm);\n\n m.def(\n \"moe_wna16_marlin_gemm(Tensor! a, Tensor? c_or_none,\"\n \"Tensor! b_q_weight, Tensor? b_bias_or_none,\"\n \"Tensor! b_scales, Tensor? a_scales, Tensor? global_scale, Tensor? \"\n \"b_zeros_or_none,\"\n \"Tensor? g_idx_or_none, Tensor? perm_or_none, Tensor! workspace,\"\n \"Tensor sorted_token_ids,\"\n \"Tensor! expert_ids, Tensor! num_tokens_past_padded,\"\n \"Tensor! topk_weights, int moe_block_size, int top_k, \"\n \"bool mul_topk_weights, bool is_ep, int b_type_id,\"\n \"int size_m, int size_n, int size_k,\"\n \"bool is_full_k, bool use_atomic_add,\"\n \"bool use_fp32_reduce, bool is_zp_float,\"\n \"int thread_k, int thread_n, int blocks_per_sm) -> Tensor\");\n\n m.def(\n \"marlin_gemm_moe(Tensor! a, Tensor! b_q_weights, Tensor! sorted_ids, \"\n \"Tensor! topk_weights, Tensor! topk_ids, Tensor! b_scales, Tensor! \"\n \"b_zeros, Tensor! g_idx, Tensor! perm, Tensor! workspace, \"\n \"int b_q_type, SymInt size_m, \"\n \"SymInt size_n, SymInt size_k, bool is_k_full, int num_experts, int \"\n \"topk, \"\n \"int moe_block_size, bool replicate_input, bool apply_weights)\"\n \" -> Tensor\");\n\n m.def(\n \"moe_permute(Tensor input, Tensor topk_ids,\"\n \"Tensor token_expert_indices, Tensor? expert_map, int n_expert,\"\n \"int n_local_expert,\"\n \"int topk, int? align_block_size,Tensor! permuted_input, Tensor! \"\n \"expert_first_token_offset, Tensor! inv_permuted_idx, Tensor! \"\n \"permuted_idx, Tensor! m_indices)->()\");\n\n m.def(\n \"moe_unpermute(Tensor permuted_hidden_states, Tensor topk_weights,\"\n \"Tensor inv_permuted_idx, Tensor? expert_first_token_offset, \"\n \"int topk, Tensor! hidden_states)->()\");\n\n m.def(\"moe_permute_unpermute_supported() -> bool\");\n m.impl(\"moe_permute_unpermute_supported\", &moe_permute_unpermute_supported);\n\n // Row shuffle for MoE\n m.def(\n \"shuffle_rows(Tensor input_tensor, Tensor dst2src_map, Tensor! \"\n \"output_tensor) -> ()\");\n m.impl(\"shuffle_rows\", torch::kCUDA, &shuffle_rows);\n\n // Apply grouped topk routing to select experts.\n m.def(\n \"grouped_topk(Tensor scores, int n_group, int \"\n \"topk_group, int topk, bool renormalize, float \"\n \"routed_scaling_factor, Tensor bias, int scoring_func) -> (Tensor, \"\n \"Tensor)\");\n m.impl(\"grouped_topk\", torch::kCUDA, &grouped_topk);\n#endif\n}\n\nREGISTER_EXTENSION(TORCH_EXTENSION_NAME)\n"},"after_code":{"kind":"string","value":"#include \"core/registration.h\"\n#include \"moe_ops.h\"\n\nTORCH_LIBRARY_EXPAND(TORCH_EXTENSION_NAME, m) {\n // Apply topk softmax to the gating outputs.\n m.def(\n \"topk_softmax(Tensor! topk_weights, Tensor! topk_indices, Tensor! \"\n \"token_expert_indices, Tensor gating_output, bool renormalize) -> ()\");\n m.impl(\"topk_softmax\", torch::kCUDA, &topk_softmax);\n\n // Calculate the result of moe by summing up the partial results\n // from all selected experts.\n m.def(\"moe_sum(Tensor input, Tensor! output) -> ()\");\n m.impl(\"moe_sum\", torch::kCUDA, &moe_sum);\n\n // Aligning the number of tokens to be processed by each expert such\n // that it is divisible by the block size.\n m.def(\n \"moe_align_block_size(Tensor topk_ids, int num_experts,\"\n \" int block_size, Tensor! sorted_token_ids,\"\n \" Tensor! experts_ids,\"\n \" Tensor! num_tokens_post_pad,\"\n \" Tensor? maybe_expert_map) -> ()\");\n m.impl(\"moe_align_block_size\", torch::kCUDA, &moe_align_block_size);\n\n // Aligning the number of tokens to be processed by each expert such\n // that it is divisible by the block size, but for the batched case.\n m.def(\n \"batched_moe_align_block_size(int max_tokens_per_batch,\"\n \" int block_size, Tensor expert_num_tokens,\"\n \" Tensor! sorted_token_ids,\"\n \" Tensor! experts_ids,\"\n \" Tensor! num_tokens_post_pad) -> ()\");\n m.impl(\"batched_moe_align_block_size\", torch::kCUDA,\n &batched_moe_align_block_size);\n\n // Aligning the number of tokens to be processed by each expert such\n // that it is divisible by the block size.\n m.def(\n \"moe_lora_align_block_size(Tensor topk_ids,\"\n \" Tensor token_lora_mapping,\"\n \" int num_experts,\"\n \" int block_size, int max_loras, \"\n \" int max_num_tokens_padded, \"\n \" int max_num_m_blocks, \"\n \" Tensor !sorted_token_ids,\"\n \" Tensor !experts_ids,\"\n \" Tensor !num_tokens_post_pad,\"\n \" Tensor !adapter_enabled,\"\n \" Tensor !lora_ids) -> () \");\n m.impl(\"moe_lora_align_block_size\", torch::kCUDA, &moe_lora_align_block_size);\n\n#ifndef USE_ROCM\n m.def(\n \"moe_wna16_gemm(Tensor input, Tensor! output, Tensor b_qweight, \"\n \"Tensor b_scales, Tensor? b_qzeros, \"\n \"Tensor? topk_weights, Tensor sorted_token_ids, \"\n \"Tensor expert_ids, Tensor num_tokens_post_pad, \"\n \"int top_k, int BLOCK_SIZE_M, int BLOCK_SIZE_N, int BLOCK_SIZE_K, \"\n \"int bit) -> Tensor\");\n\n m.impl(\"moe_wna16_gemm\", torch::kCUDA, &moe_wna16_gemm);\n\n m.def(\n \"moe_wna16_marlin_gemm(Tensor! a, Tensor? c_or_none,\"\n \"Tensor! b_q_weight, Tensor? b_bias_or_none,\"\n \"Tensor! b_scales, Tensor? a_scales, Tensor? global_scale, Tensor? \"\n \"b_zeros_or_none,\"\n \"Tensor? g_idx_or_none, Tensor? perm_or_none, Tensor! workspace,\"\n \"Tensor sorted_token_ids,\"\n \"Tensor! expert_ids, Tensor! num_tokens_past_padded,\"\n \"Tensor! topk_weights, int moe_block_size, int top_k, \"\n \"bool mul_topk_weights, bool is_ep, int b_type_id,\"\n \"int size_m, int size_n, int size_k,\"\n \"bool is_full_k, bool use_atomic_add,\"\n \"bool use_fp32_reduce, bool is_zp_float,\"\n \"int thread_k, int thread_n, int blocks_per_sm) -> Tensor\");\n\n m.def(\n \"marlin_gemm_moe(Tensor! a, Tensor! b_q_weights, Tensor! sorted_ids, \"\n \"Tensor! topk_weights, Tensor! topk_ids, Tensor! b_scales, Tensor! \"\n \"b_zeros, Tensor! g_idx, Tensor! perm, Tensor! workspace, \"\n \"int b_q_type, SymInt size_m, \"\n \"SymInt size_n, SymInt size_k, bool is_k_full, int num_experts, int \"\n \"topk, \"\n \"int moe_block_size, bool replicate_input, bool apply_weights)\"\n \" -> Tensor\");\n\n m.def(\n \"moe_permute(Tensor input, Tensor topk_ids,\"\n \"Tensor token_expert_indices, Tensor? expert_map, int n_expert,\"\n \"int n_local_expert,\"\n \"int topk, int? align_block_size,Tensor! permuted_input, Tensor! \"\n \"expert_first_token_offset, Tensor! inv_permuted_idx, Tensor! \"\n \"permuted_idx, Tensor! m_indices)->()\");\n\n m.def(\n \"moe_unpermute(Tensor permuted_hidden_states, Tensor topk_weights,\"\n \"Tensor inv_permuted_idx, Tensor? expert_first_token_offset, \"\n \"int topk, Tensor! hidden_states)->()\");\n\n m.def(\"moe_permute_unpermute_supported() -> bool\");\n m.impl(\"moe_permute_unpermute_supported\", &moe_permute_unpermute_supported);\n\n // Row shuffle for MoE\n m.def(\n \"shuffle_rows(Tensor input_tensor, Tensor dst2src_map, Tensor! \"\n \"output_tensor) -> ()\");\n m.impl(\"shuffle_rows\", torch::kCUDA, &shuffle_rows);\n\n // Apply grouped topk routing to select experts.\n m.def(\n \"grouped_topk(Tensor scores, int n_group, int \"\n \"topk_group, int topk, bool renormalize, float \"\n \"routed_scaling_factor, Tensor bias, int scoring_func) -> (Tensor, \"\n \"Tensor)\");\n m.impl(\"grouped_topk\", torch::kCUDA, &grouped_topk);\n#endif\n}\n\nREGISTER_EXTENSION(TORCH_EXTENSION_NAME)\n"},"diff":{"kind":"string","value":"--- csrc/moe/torch_bindings.cpp\n+++ csrc/moe/torch_bindings.cpp\n@@ -19,7 +19,8 @@\n \"moe_align_block_size(Tensor topk_ids, int num_experts,\"\n \" int block_size, Tensor! sorted_token_ids,\"\n \" Tensor! experts_ids,\"\n- \" Tensor! num_tokens_post_pad) -> ()\");\n+ \" Tensor! num_tokens_post_pad,\"\n+ \" Tensor? maybe_expert_map) -> ()\");\n m.impl(\"moe_align_block_size\", torch::kCUDA, &moe_align_block_size);\n \n // Aligning the number of tokens to be processed by each expert such"},"lines_added":{"kind":"number","value":2,"string":"2"},"lines_removed":{"kind":"number","value":1,"string":"1"},"files_in_commit":{"kind":"number","value":6,"string":"6"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cpp kernel file from vllm (csrc/moe/torch_bindings.cpp).\n\nGoal: [Kernel][MoE] optimize `moe_align_block_size`\nTarget hardware: unspecified\nTarget models: unspecified\n\nCurrent file:\n```cpp\n#include \"core/registration.h\"\n#include \"moe_ops.h\"\n\nTORCH_LIBRARY_EXPAND(TORCH_EXTENSION_NAME, m) {\n // Apply topk softmax to the gating outputs.\n m.def(\n \"topk_softmax(Tensor! topk_weights, Tensor! topk_indices, Tensor! \"\n \"token_expert_indices, Tensor gating_output, bool renormalize) -> ()\");\n m.impl(\"topk_softmax\", torch::kCUDA, &topk_softmax);\n\n // Calculate the result of moe by summing up the partial results\n // from all selected experts.\n m.def(\"moe_sum(Tensor input, Tensor! output) -> ()\");\n m.impl(\"moe_sum\", torch::kCUDA, &moe_sum);\n\n // Aligning the number of tokens to be processed by each expert such\n // that it is divisible by the block size.\n m.def(\n \"moe_align_block_size(Tensor topk_ids, int num_experts,\"\n \" int block_size, Tensor! sorted_token_ids,\"\n \" Tensor! experts_ids,\"\n \" Tensor! num_tokens_post_pad) -> ()\");\n m.impl(\"moe_align_block_size\", torch::kCUDA, &moe_align_block_size);\n\n // Aligning the number of tokens to be processed by each expert such\n // that it is divisible by the block size, but for the batched case.\n m.def(\n \"batched_moe_align_block_size(int max_tokens_per_batch,\"\n \" int block_size, Tensor expert_num_tokens,\"\n \" Tensor! sorted_token_ids,\"\n \" Tensor! experts_ids,\"\n \" Tensor! num_tokens_post_pad) -> ()\");\n m.impl(\"batched_moe_align_block_size\", torch::kCUDA,\n &batched_moe_align_block_size);\n\n // Aligning the number of tokens to be processed by each expert such\n // that it is divisible by the block size.\n m.def(\n \"moe_lora_align_block_size(Tensor topk_ids,\"\n \" Tensor token_lora_mapping,\"\n \" int num_experts,\"\n \" int block_size, int max_loras, \"\n \" int max_num_tokens_padded, \"\n \" int max_num_m_blocks, \"\n \" Tensor !sorted_token_ids,\"\n \" Tensor !experts_ids,\"\n \" Tensor !num_tokens_post_pad,\"\n \" Tensor !adapter_enabled,\"\n \" Tensor !lora_ids) -> () \");\n m.impl(\"moe_lora_align_block_size\", torch::kCUDA, &moe_lora_align_block_size);\n\n#ifndef USE_ROCM\n m.def(\n \"moe_wna16_gemm(Tensor input, Tensor! output, Tensor b_qweight, \"\n \"Tensor b_scales, Tensor? b_qzeros, \"\n \"Tensor? topk_weights, Tensor sorted_token_ids, \"\n \"Tensor expert_ids, Tensor num_tokens_post_pad, \"\n \"int top_k, int BLOCK_SIZE_M, int BLOCK_SIZE_N, int BLOCK_SIZE_K, \"\n \"int bit) -> Tensor\");\n\n m.impl(\"moe_wna16_gemm\", torch::kCUDA, &moe_wna16_gemm);\n\n m.def(\n \"moe_wna16_marlin_gemm(Tensor! a, Tensor? c_or_none,\"\n \"Tensor! b_q_weight, Tensor? b_bias_or_none,\"\n \"Tensor! b_scales, Tensor? a_scales, Tensor? global_scale, Tensor? \"\n \"b_zeros_or_none,\"\n \"Tensor? g_idx_or_none, Tensor? perm_or_none, Tensor! workspace,\"\n \"Tensor sorted_token_ids,\"\n \"Tensor! expert_ids, Tensor! num_tokens_past_padded,\"\n \"Tensor! topk_weights, int moe_block_size, int top_k, \"\n \"bool mul_topk_weights, bool is_ep, int b_type_id,\"\n \"int size_m, int size_n, int size_k,\"\n \"bool is_full_k, bool use_atomic_add,\"\n \"bool use_fp32_reduce, bool is_zp_float,\"\n \"int thread_k, int thread_n, int blocks_per_sm) -> Tensor\");\n\n m.def(\n \"marlin_gemm_moe(Tensor! a, Tensor! b_q_weights, Tensor! sorted_ids, \"\n \"Tensor! topk_weights, Tensor! topk_ids, Tensor! b_scales, Tensor! \"\n \"b_zeros, Tensor! g_idx, Tensor! perm, Tensor! workspace, \"\n \"int b_q_type, SymInt size_m, \"\n \"SymInt size_n, SymInt size_k, bool is_k_full, int num_experts, int \"\n \"topk, \"\n \"int moe_block_size, bool replicate_input, bool apply_weights)\"\n \" -> Tensor\");\n\n m.def(\n \"moe_permute(Tensor input, Tensor topk_ids,\"\n \"Tensor token_expert_indices, Tensor? expert_map, int n_expert,\"\n \"int n_local_expert,\"\n \"int topk, int? align_block_size,Tensor! permuted_input, Tensor! \"\n \"expert_first_token_offset, Tensor! inv_permuted_idx, Tensor! \"\n \"permuted_idx, Tensor! m_indices)->()\");\n\n m.def(\n \"moe_unpermute(Tensor permuted_hidden_states, Tensor topk_weights,\"\n \"Tensor inv_permuted_idx, Tensor? expert_first_token_offset, \"\n \"int topk, Tensor! hidden_states)->()\");\n\n m.def(\"moe_permute_unpermute_supported() -> bool\");\n m.impl(\"moe_permute_unpermute_supported\", &moe_permute_unpermute_supported);\n\n // Row shuffle for MoE\n m.def(\n \"shuffle_rows(Tensor input_tensor, Tensor dst2src_map, Tensor! \"\n \"output_tensor) -> ()\");\n m.impl(\"shuffle_rows\", torch::kCUDA, &shuffle_rows);\n\n // Apply grouped topk routing to select experts.\n m.def(\n \"grouped_topk(Tensor scores, int n_group, int \"\n \"topk_group, int topk, bool renormalize, float \"\n \"routed_scaling_factor, Tensor bias, int scoring_func) -> (Tensor, \"\n \"Tensor)\");\n m.impl(\"grouped_topk\", torch::kCUDA, &grouped_topk);\n#endif\n}\n\nREGISTER_EXTENSION(TORCH_EXTENSION_NAME)\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## Introduction\nThis PR optimize `moe_align_block_size` from three aspects:\n\n1. For a small batch size, use the smallest possible value for `max_num_tokens_padded`.\n\n2. In the CUDA Kernel, use additional thread or threadblock resources to fill `sorted_token_ids`. The previous CUDA Kernel used very few computational resources, and the filling of `sorted_token_ids` and the counting of experts were performed sequentially. Since `sorted_token_ids` is only used again at the very end of the CUDA kernel, I changed this to be parallelized to accelerate kernel execution.\n\n3. For EP, all invalid experts are filtered out directly when counting the number of experts. This accelerates the execution of `moe_align_block_size` and also leads to a cleaner and faster implementation for the subsequent MoE kernel.\n\n\n## Kernel Bench\n\nOn RTX 4090\n\n```\nmoe-align-block-size-performance:\n num_tokens num_experts topk ep_size main PR\n0 1.0 16.0 1.0 1.0 8.192000 6.144000\n1 1.0 16.0 1.0 8.0 12.288000 6.144000\n2 1.0 16.0 2.0 1.0 7.168000 6.080000\n3 1.0 16.0 2.0 8.0 11.264000 5.120000\n4 1.0 16.0 8.0 1.0 7.232000 5.120000\n5 1.0 16.0 8.0 8.0 12.224000 6.144000\n6 1.0 64.0 1.0 1.0 13.312000 9.216000\n7 1.0 64.0 1.0 8.0 17.408000 9.216000\n8 1.0 64.0 2.0 1.0 13.312000 9.216000\n9 1.0 64.0 2.0 8.0 17.408000 9.216000\n10 1.0 64.0 8.0 1.0 13.312000 9.216000\n11 1.0 64.0 8.0 8.0 17.408000 9.216000\n12 1.0 224.0 1.0 1.0 10.240000 7.168000\n13 1.0 224.0 1.0 8.0 14.336000 7.168000\n14 1.0 224.0 2.0 1.0 10.240000 7.168000\n15 1.0 224.0 2.0 8.0 14.336000 7.168000\n16 1.0 224.0 8.0 1.0 10.240000 7.168000\n17 1.0 224.0 8.0 8.0 14.336000 7.168000\n18 1.0 256.0 1.0 1.0 10.240000 7.168000\n19 1.0 256.0 1.0 8.0 14.336000 8.192000\n20 1.0 256.0 2.0 1.0 10.240000 7.168000\n21 1.0 256.0 2.0 8.0 14.336000 8.192000\n22 1.0 256.0 8.0 1.0 10.240000 7.168000\n23 1.0 256.0 8.0 8.0 14.336000 8.192000\n24 1.0 280.0 1.0 1.0 11.264000 7.168000\n25 1.0 280.0 1.0 8.0 15.360000 7.168000\n26 1.0 280.0 2.0 1.0 11.264000 7.168000\n27 1.0 280.0 2.0 8.0 15.360000 7.168000\n28 1.0 280.0 8.0 1.0 11.264000 7.168000\n29 1.0 280.0 8.0 8.0 15.360000 7.168000\n30 1.0 512.0 1.0 1.0 13.312000 7.168000\n31 1.0 512.0 1.0 8.0 18.432001 7.168000\n32 1.0 512.0 2.0 1.0 13.312000 7.168000\n33 1.0 512.0 2.0 8.0 18.432001 7.168000\n34 1.0 512.0 8.0 1.0 13.312000 7.168000\n35 1.0 512.0 8.0 8.0 18.432001 7.168000\n36 16.0 16.0 1.0 1.0 7.168000 6.080000\n37 16.0 16.0 1.0 8.0 11.264000 6.144000\n38 16.0 16.0 2.0 1.0 7.168000 5.120000\n39 16.0 16.0 2.0 8.0 12.288000 5.120000\n40 16.0 16.0 8.0 1.0 8.192000 6.144000\n41 16.0 16.0 8.0 8.0 13.312000 7.168000\n42 16.0 64.0 1.0 1.0 13.312000 9.216000\n43 16.0 64.0 1.0 8.0 17.408000 9.216000\n44 16.0 64.0 2.0 1.0 13.312000 9.216000\n45 16.0 64.0 2.0 8.0 17.408000 9.216000\n46 16.0 64.0 8.0 1.0 13.312000 9.312000\n47 16.0 64.0 8.0 8.0 17.408000 9.216000\n48 16.0 224.0 1.0 1.0 10.240000 7.168000\n49 16.0 224.0 1.0 8.0 14.336000 8.192000\n50 16.0 224.0 2.0 1.0 10.240000 7.168000\n51 16.0 224.0 2.0 8.0 14.336000 8.192000\n52 16.0 224.0 8.0 1.0 10.240000 7.168000\n53 16.0 224.0 8.0 8.0 14.336000 8.192000\n54 16.0 256.0 1.0 1.0 10.240000 7.168000\n55 16.0 256.0 1.0 8.0 14.336000 8.192000\n56 16.0 256.0 2.0 1.0 10.240000 7.168000\n57 16.0 256.0 2.0 8.0 14.336000 8.192000\n58 16.0 256.0 8.0 1.0 10.240000 7.168000\n59 16.0 256.0 8.0 8.0 14.336000 8.192000\n60 16.0 280.0 1.0 1.0 11.264000 7.168000\n61 16.0 280.0 1.0 8.0 15.360000 8.192000\n62 16.0 280.0 2.0 1.0 11.136000 7.168000\n63 16.0 280.0 2.0 8.0 15.360000 8.192000\n64 16.0 280.0 8.0 1.0 11.264000 7.168000\n65 16.0 280.0 8.0 8.0 15.360000 8.192000\n66 16.0 512.0 1.0 1.0 13.312000 7.168000\n67 16.0 512.0 1.0 8.0 18.432001 8.192000\n68 16.0 512.0 2.0 1.0 13.312000 7.168000\n69 16.0 512.0 2.0 8.0 18.432001 8.192000\n70 16.0 512.0 8.0 1.0 13.312000 8.128000\n71 16.0 512.0 8.0 8.0 18.432001 8.192000\n72 256.0 16.0 1.0 1.0 9.216000 7.168000\n73 256.0 16.0 1.0 8.0 13.312000 8.192000\n74 256.0 16.0 2.0 1.0 12.288000 10.240000\n75 256.0 16.0 2.0 8.0 15.360000 11.264000\n76 256.0 16.0 8.0 1.0 8.192000 8.192000\n77 256.0 16.0 8.0 8.0 12.288000 8.192000\n78 256.0 64.0 1.0 1.0 14.336000 10.240000\n79 256.0 64.0 1.0 8.0 18.432001 10.736000\n80 256.0 64.0 2.0 1.0 14.336000 11.264000\n81 256.0 64.0 2.0 8.0 18.432001 12.288000\n82 256.0 64.0 8.0 1.0 9.216000 8.192000\n83 256.0 64.0 8.0 8.0 12.288000 8.192000\n84 256.0 224.0 1.0 1.0 10.240000 8.192000\n85 256.0 224.0 1.0 8.0 14.432000 8.192000\n86 256.0 224.0 2.0 1.0 10.240000 8.192000\n87 256.0 224.0 2.0 8.0 14.336000 8.192000\n88 256.0 224.0 8.0 1.0 11.264000 8.192000\n89 256.0 224.0 8.0 8.0 15.360000 8.192000\n90 256.0 256.0 1.0 1.0 10.240000 8.192000\n91 256.0 256.0 1.0 8.0 15.360000 8.192000\n92 256.0 256.0 2.0 1.0 10.240000 8.192000\n93 256.0 256.0 2.0 8.0 15.360000 8.192000\n94 256.0 256.0 8.0 1.0 11.264000 9.216000\n95 256.0 256.0 8.0 8.0 16.384000 8.192000\n96 256.0 280.0 1.0 1.0 11.264000 8.192000\n97 256.0 280.0 1.0 8.0 15.360000 8.192000\n98 256.0 280.0 2.0 1.0 11.264000 9.216000\n99 256.0 280.0 2.0 8.0 16.384000 9.216000\n100 256.0 280.0 8.0 1.0 11.264000 9.216000\n101 256.0 280.0 8.0 8.0 16.527999 9.216000\n102 256.0 512.0 1.0 1.0 13.312000 8.192000\n103 256.0 512.0 1.0 8.0 18.592000 8.192000\n104 256.0 512.0 2.0 1.0 13.312000 11.264000\n105 256.0 512.0 2.0 8.0 19.455999 11.264000\n106 256.0 512.0 8.0 1.0 14.336000 11.264000\n107 256.0 512.0 8.0 8.0 19.455999 11.264000\n108 4096.0 16.0 1.0 1.0 9.216000 9.216000\n109 4096.0 16.0 1.0 8.0 13.312000 9.216000\n110 4096.0 16.0 2.0 1.0 11.264000 11.264000\n111 4096.0 16.0 2.0 8.0 15.360000 10.240000\n112 4096.0 16.0 8.0 1.0 22.528000 20.608000\n113 4096.0 16.0 8.0 8.0 26.624000 19.455999\n114 4096.0 64.0 1.0 1.0 10.240000 9.216000\n115 4096.0 64.0 1.0 8.0 14.336000 9.216000\n116 4096.0 64.0 2.0 1.0 12.288000 11.264000\n117 4096.0 64.0 2.0 8.0 16.384000 10.240000\n118 4096.0 64.0 8.0 1.0 25.599999 23.552001\n119 4096.0 64.0 8.0 8.0 30.719999 18.432001\n120 4096.0 224.0 1.0 1.0 12.288000 9.216000\n121 4096.0 224.0 1.0 8.0 16.384000 9.216000\n122 4096.0 224.0 2.0 1.0 14.336000 11.264000\n123 4096.0 224.0 2.0 8.0 18.432001 10.240000\n124 4096.0 224.0 8.0 1.0 24.576001 20.479999\n125 4096.0 224.0 8.0 8.0 28.672000 19.455999\n126 4096.0 256.0 1.0 1.0 12.288000 9.216000\n127 4096.0 256.0 1.0 8.0 17.408000 9.216000\n128 4096.0 256.0 2.0 1.0 14.336000 11.264000\n129 4096.0 256.0 2.0 8.0 19.455999 10.240000\n130 4096.0 256.0 8.0 1.0 27.648000 23.552001\n131 4096.0 256.0 8.0 8.0 32.768000 19.455999\n132 4096.0 280.0 1.0 1.0 12.288000 9.216000\n133 4096.0 280.0 1.0 8.0 17.408000 9.216000\n134 4096.0 280.0 2.0 1.0 15.360000 11.264000\n135 4096.0 280.0 2.0 8.0 19.616000 10.240000\n136 4096.0 280.0 8.0 1.0 25.599999 21.504000\n137 4096.0 280.0 8.0 8.0 31.727999 19.455999\n138 4096.0 512.0 1.0 1.0 15.360000 12.288000\n139 4096.0 512.0 1.0 8.0 20.479999 12.192000\n140 4096.0 512.0 2.0 1.0 17.408000 13.280000\n141 4096.0 512.0 2.0 8.0 22.528000 12.288000\n142 4096.0 512.0 8.0 1.0 28.672000 21.504000\n143 4096.0 512.0 8.0 8.0 34.655999 19.455999\n```\n\n\n## Kernel Accuracy Test\n\nTested with\n\n```\npytest -sv test_moe_align_block_size.py::test_moe_align_block_size\n\npytest -sv test_moe_align_block_size.py::test_moe_align_block_size_with_expert_map\n```\n\nAll test cases are passed.\n\n## E2E Accuracy Test\n\nGSM8K (2-shot)\n\nWith Triton Kernel\n\n```\nvllm serve /data/pretrained_model/Qwen/Qwen1.5-MoE-A2.7B-Chat/ -tp 4 --served-model-name model --port 8002 --gpu-memory-utilization 0.75 --enable-expert-parallel\n\n\nlm_eval \\\n --model local-chat-completions \\\n --tasks gsm8k \\\n --num_fewshot 2 \\\n --batch_size auto \\\n --model_args \"model=model,base_url=http://localhost:8002/v1/chat/completions,max_gen_toks=512,num_concurrent=128,max_length=4096\" \\\n --apply_chat_template\n\n\n|Tasks|Version| Filter |n-shot| Metric | |Value | |Stderr|\n|-----|------:|----------------|-----:|-----------|---|-----:|---|-----:|\n|gsm8k| 3|flexible-extract| 2|exact_match|↑ |0.5095|± |0.0138|\n| | |strict-match | 2|exact_match|↑ |0.0258|± |0.0044|\n```\n\n\nWith Marlin Kernel\n\n```\nvllm serve /data/pretrained_model/Qwen/Qwen1.5-MoE-A2.7B-Chat-GPTQ-Int4/ -tp 4 --served-model-name model --port 8002 --gpu-memory-utilization 0.75 --enable-expert-parallel\n\n\nlm_eval \\\n --model local-chat-completions \\\n --tasks gsm8k \\\n --num_fewshot 2 \\\n --batch_size auto \\\n --model_args \"model=model,base_url=http://localhost:8002/v1/chat/completions,max_gen_toks=512,num_concurrent=128,max_length=4096\" \\\n --apply_chat_template\n\n\n|Tasks|Version| Filter |n-shot| Metric | |Value | |Stderr|\n|-----|------:|----------------|-----:|-----------|---|-----:|---|-----:|\n|gsm8k| 3|flexible-extract| 2|exact_match|↑ |0.4723|± |0.0138|\n| | |strict-match | 2|exact_match|↑ |0.0190|± |0.0038|\n```\n"},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":396,"cells":{"repo":{"kind":"string","value":"vllm"},"commit":{"kind":"string","value":"879ddb09c3b7b5a21f75e46ded148ce70f1c486e"},"date":{"kind":"string","value":"2025-12-07T17:58:47+08:00"},"pr_number":{"kind":"number","value":29642,"string":"29,642"},"pr_url":{"kind":"string","value":"https://github.com/vllm-project/vllm/pull/29642"},"title":{"kind":"string","value":"[Kernel][MoE] optimize `moe_align_block_size` (#29642)"},"message":{"kind":"string","value":"[Kernel][MoE] optimize `moe_align_block_size` (#29642)\n\nSigned-off-by: Jinzhen Lin <jinzhen.ljz@antgroup.com>\nCo-authored-by: Jee Jee Li <pandaleefree@gmail.com>"},"path":{"kind":"string","value":"vllm/model_executor/layers/fused_moe/fused_moe.py"},"language":{"kind":"string","value":"triton"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"# SPDX-License-Identifier: Apache-2.0\n# SPDX-FileCopyrightText: Copyright contributors to the vLLM project\n\"\"\"Fused MoE Triton kernels.\"\"\"\n\nimport functools\nimport json\nimport os\nfrom collections.abc import Callable\nfrom typing import Any\n\nimport torch\nimport torch.nn.functional as F\n\nimport vllm.envs as envs\nimport vllm.model_executor.layers.fused_moe.modular_kernel as mk\nfrom vllm import _custom_ops as ops\nfrom vllm._aiter_ops import rocm_aiter_ops\nfrom vllm.logger import init_logger\nfrom vllm.model_executor.layers.batch_invariant import (\n vllm_is_batch_invariant,\n)\nfrom vllm.model_executor.layers.fused_moe.config import (\n FUSED_MOE_UNQUANTIZED_CONFIG,\n FusedMoEQuantConfig,\n _get_config_dtype_str,\n)\nfrom vllm.model_executor.layers.fused_moe.cutlass_moe import (\n _valid_cutlass_block_scaled_grouped_gemm,\n run_cutlass_block_scaled_fused_experts,\n)\nfrom vllm.model_executor.layers.fused_moe.deep_gemm_moe import (\n _valid_deep_gemm,\n deep_gemm_moe_fp8,\n)\nfrom vllm.model_executor.layers.fused_moe.moe_align_block_size import (\n moe_align_block_size,\n)\nfrom vllm.model_executor.layers.fused_moe.prepare_finalize import (\n MoEPrepareAndFinalizeNoEP,\n)\nfrom vllm.model_executor.layers.fused_moe.topk_weight_and_reduce import (\n TopKWeightAndReduceNoOP,\n)\nfrom vllm.model_executor.layers.fused_moe.utils import (\n _resize_cache,\n activation_without_mul,\n disable_inplace,\n moe_kernel_quantize_input,\n)\nfrom vllm.model_executor.layers.quantization.utils.mxfp4_utils import dequant_mxfp4\nfrom vllm.model_executor.layers.quantization.utils.mxfp6_utils import dequant_mxfp6\nfrom vllm.model_executor.layers.quantization.utils.ocp_mx_utils import OCP_MX_Scheme\nfrom vllm.model_executor.utils import maybe_disable_graph_partition\nfrom vllm.platforms import current_platform\nfrom vllm.triton_utils import tl, triton\nfrom vllm.utils.deep_gemm import is_deep_gemm_e8m0_used\nfrom vllm.utils.torch_utils import direct_register_custom_op, is_torch_equal_or_newer\n\nlogger = init_logger(__name__)\n\n\n@triton.jit\ndef write_zeros_to_output(\n c_ptr,\n stride_cm,\n stride_cn,\n pid_n,\n N,\n offs_token,\n token_mask,\n BLOCK_SIZE_M,\n BLOCK_SIZE_N,\n compute_type,\n):\n accumulator = tl.zeros((BLOCK_SIZE_M, BLOCK_SIZE_N), dtype=compute_type)\n offs_cn = pid_n * BLOCK_SIZE_N + tl.arange(0, BLOCK_SIZE_N)\n c_ptrs = c_ptr + stride_cm * offs_token[:, None] + stride_cn * offs_cn[None, :]\n c_mask = token_mask[:, None] & (offs_cn[None, :] < N)\n tl.store(c_ptrs, accumulator, mask=c_mask)\n\n\n@triton.jit\ndef fused_moe_kernel_gptq_awq(\n # Pointers to matrices\n a_ptr,\n b_ptr,\n c_ptr,\n b_scale_ptr,\n b_zp_ptr,\n topk_weights_ptr,\n sorted_token_ids_ptr,\n expert_ids_ptr,\n num_tokens_post_padded_ptr,\n # Matrix dimensions\n N: tl.constexpr,\n K: tl.constexpr,\n EM,\n num_valid_tokens,\n # The stride variables represent how much to increase the ptr by when\n # moving by 1 element in a particular dimension. E.g. `stride_am` is\n # how much to increase `a_ptr` by to get the element one row down\n # (A has M rows).\n stride_am,\n stride_ak,\n stride_be,\n stride_bk,\n stride_bn,\n stride_cm,\n stride_cn,\n stride_bse,\n stride_bsk,\n stride_bsn,\n stride_bze,\n stride_bzk,\n stride_bzn,\n block_k_diviable: tl.constexpr,\n group_size: tl.constexpr,\n # Meta-parameters\n BLOCK_SIZE_M: tl.constexpr,\n BLOCK_SIZE_N: tl.constexpr,\n BLOCK_SIZE_K: tl.constexpr,\n GROUP_SIZE_M: tl.constexpr,\n SPLIT_K: tl.constexpr,\n MUL_ROUTED_WEIGHT: tl.constexpr,\n top_k: tl.constexpr,\n compute_type: tl.constexpr,\n has_zp: tl.constexpr,\n use_int4_w4a16: tl.constexpr,\n use_int8_w8a16: tl.constexpr,\n):\n \"\"\"\n Implements the fused computation for a Mixture of Experts (MOE) using\n token and expert matrices.\n\n Key Parameters:\n - A: The input tensor representing tokens with shape (*, K), where '*' can\n be any shape representing batches and K is the feature dimension of\n each token.\n - B: The stacked MOE weight tensor with shape (E, N, K), where E is\n the number of experts, K is the input feature dimension, and N is\n the output feature dimension.\n - C: The output cache tensor with shape (M, topk, N), where M is the\n total number of tokens post padding, topk is the number of times\n each token is repeated, and N is the output feature dimension.\n - sorted_token_ids: A tensor containing the sorted indices of tokens,\n repeated topk times and arranged by the expert index they are\n assigned to.\n - expert_ids: A tensor containing the indices of the expert for each\n block. It determines which expert matrix from B should be used for\n each block in A.\n This kernel performs the multiplication of a token by its corresponding\n expert matrix as determined by `expert_ids`. The sorting of\n `sorted_token_ids` by expert index and padding ensures divisibility by\n BLOCK_SIZE_M, which is necessary to maintain consistency in block matrix\n multiplication across different blocks processed by the same expert.\n \"\"\"\n # -----------------------------------------------------------\n # Map program ids `pid` to the block of C it should compute.\n # This is done in a grouped ordering to promote L2 data reuse.\n pid = tl.program_id(axis=0)\n num_pid_m = tl.cdiv(EM, BLOCK_SIZE_M)\n num_pid_n = tl.cdiv(N, BLOCK_SIZE_N)\n num_pid_in_group = GROUP_SIZE_M * num_pid_n\n group_id = pid // num_pid_in_group\n first_pid_m = group_id * GROUP_SIZE_M\n group_size_m = min(num_pid_m - first_pid_m, GROUP_SIZE_M)\n pid_m = first_pid_m + ((pid % num_pid_in_group) % group_size_m)\n pid_n = (pid % num_pid_in_group) // group_size_m\n\n # ----------------------------------------------------------\n # Create pointers for the first blocks of A and B.\n # We will advance this pointer as we move in the K direction\n # and accumulate\n # `a_ptrs` is a block of [BLOCK_SIZE_M, BLOCK_SIZE_K] pointers\n # `b_ptrs` is a block of [BLOCK_SIZE_K, BLOCK_SIZE_N] pointers\n num_tokens_post_padded = tl.load(num_tokens_post_padded_ptr)\n if pid_m * BLOCK_SIZE_M >= num_tokens_post_padded:\n return\n offs_token_id = pid_m * BLOCK_SIZE_M + tl.arange(0, BLOCK_SIZE_M).to(tl.int64)\n offs_token = tl.load(sorted_token_ids_ptr + offs_token_id)\n token_mask = offs_token < num_valid_tokens\n\n off_experts = tl.load(expert_ids_ptr + pid_m).to(tl.int64)\n if off_experts == -1:\n # -----------------------------------------------------------\n # Write back zeros to the output when the expert is not\n # in the current expert parallel rank.\n write_zeros_to_output(\n c_ptr,\n stride_cm,\n stride_cn,\n pid_n,\n N,\n offs_token,\n token_mask,\n BLOCK_SIZE_M,\n BLOCK_SIZE_N,\n compute_type,\n )\n return\n\n offs_bn = (pid_n * BLOCK_SIZE_N + tl.arange(0, BLOCK_SIZE_N).to(tl.int64)) % N\n offs_k = tl.arange(0, BLOCK_SIZE_K)\n a_ptrs = a_ptr + (\n offs_token[:, None] // top_k * stride_am + offs_k[None, :] * stride_ak\n )\n\n if use_int4_w4a16:\n b_ptrs = (\n b_ptr\n + off_experts * stride_be\n + (offs_k[:, None] // 2) * stride_bk\n + offs_bn[None, :] * stride_bn\n )\n b_shifter = (offs_k[:, None] % 2) * 4\n elif use_int8_w8a16:\n b_ptrs = (\n b_ptr\n + off_experts * stride_be\n + offs_k[:, None] * stride_bk\n + offs_bn[None, :] * stride_bn\n )\n\n if not has_zp and use_int4_w4a16:\n b_zp_num = 8\n if not has_zp and use_int8_w8a16:\n b_zp_num = 128\n elif has_zp and use_int4_w4a16:\n b_zp_shifter = (offs_bn[None, :] % 2) * 4\n\n # -----------------------------------------------------------\n # Iterate to compute a block of the C matrix.\n # We accumulate into a `[BLOCK_SIZE_M, BLOCK_SIZE_N]` block\n # of fp32 values for higher accuracy.\n # `accumulator` will be converted back to fp16 after the loop.\n accumulator = tl.zeros((BLOCK_SIZE_M, BLOCK_SIZE_N), dtype=tl.float32)\n for k in range(0, tl.cdiv(K, BLOCK_SIZE_K)):\n # Load the next block of A and B, generate a mask by checking the\n # K dimension.\n\n if not block_k_diviable:\n k_mask = offs_k[:, None] < K - k * BLOCK_SIZE_K\n k_other = 0.0\n else:\n k_mask = None\n k_other = None\n\n a = tl.load(\n a_ptrs,\n mask=token_mask[:, None] & (offs_k[None, :] < K - k * BLOCK_SIZE_K),\n other=0.0,\n )\n b = tl.load(b_ptrs)\n if use_int4_w4a16:\n b = (b >> b_shifter) & 0xF\n\n b_scale_ptrs = (\n b_scale_ptr\n + off_experts * stride_bse\n + offs_bn[None, :] * stride_bsn\n + ((offs_k[:, None] + BLOCK_SIZE_K * k) // group_size) * stride_bsk\n )\n b_scale = tl.load(b_scale_ptrs, mask=k_mask, other=k_other)\n b_scale = b_scale.to(tl.float32)\n\n if has_zp and use_int4_w4a16:\n offs_k_true = (offs_k[:, None] + BLOCK_SIZE_K * k) // group_size\n b_zp_ptrs = (\n b_zp_ptr\n + off_experts * stride_bze\n + (offs_bn[None, :] // 2) * stride_bzn\n + offs_k_true * stride_bzk\n )\n b_zp = tl.load(b_zp_ptrs, mask=k_mask, other=k_other)\n b_zp = (b_zp >> b_zp_shifter) & 0xF\n b_zp = b_zp.to(tl.float32)\n elif has_zp and use_int8_w8a16:\n offs_k_true = (offs_k[:, None] + BLOCK_SIZE_K * k) // group_size\n b_zp_ptrs = (\n b_zp_ptr\n + off_experts * stride_bze\n + offs_bn[None, :] * stride_bzn\n + offs_k_true * stride_bzk\n )\n b_zp = tl.load(b_zp_ptrs, mask=k_mask, other=k_other)\n b_zp = b_zp.to(tl.float32)\n\n # We accumulate along the K dimension.\n if has_zp:\n b = ((b.to(tl.float32) - b_zp) * b_scale).to(compute_type)\n else:\n b = ((b.to(tl.float32) - b_zp_num) * b_scale).to(compute_type)\n accumulator = tl.dot(a, b, acc=accumulator)\n\n # Advance the ptrs to the next K block.\n a_ptrs += BLOCK_SIZE_K * stride_ak\n if use_int4_w4a16:\n b_ptrs += (BLOCK_SIZE_K // 2) * stride_bk\n else:\n b_ptrs += BLOCK_SIZE_K * stride_bk\n\n if MUL_ROUTED_WEIGHT:\n moe_weight = tl.load(topk_weights_ptr + offs_token, mask=token_mask, other=0)\n accumulator = accumulator * moe_weight[:, None]\n\n accumulator = accumulator.to(compute_type)\n # -----------------------------------------------------------\n # Write back the block of the output\n offs_cn = pid_n * BLOCK_SIZE_N + tl.arange(0, BLOCK_SIZE_N)\n c_ptrs = c_ptr + stride_cm * offs_token[:, None] + stride_cn * offs_cn[None, :]\n c_mask = token_mask[:, None] & (offs_cn[None, :] < N)\n tl.store(c_ptrs, accumulator, mask=c_mask)\n\n\n@triton.jit\ndef fused_moe_kernel(\n # Pointers to matrices\n a_ptr,\n b_ptr,\n c_ptr,\n b_bias_ptr,\n a_scale_ptr,\n b_scale_ptr,\n topk_weights_ptr,\n sorted_token_ids_ptr,\n expert_ids_ptr,\n num_tokens_post_padded_ptr,\n # Matrix dimensions\n N,\n K,\n EM,\n num_valid_tokens,\n # The stride variables represent how much to increase the ptr by when\n # moving by 1 element in a particular dimension. E.g. `stride_am` is\n # how much to increase `a_ptr` by to get the element one row down\n # (A has M rows).\n stride_am,\n stride_ak,\n stride_be,\n stride_bk,\n stride_bn,\n stride_cm,\n stride_cn,\n stride_asm,\n stride_ask,\n stride_bse,\n stride_bsk,\n stride_bsn,\n stride_bbe, # bias expert stride\n stride_bbn, # bias N stride\n # Block size for block-wise quantization\n group_n: tl.constexpr,\n group_k: tl.constexpr,\n # Meta-parameters\n BLOCK_SIZE_M: tl.constexpr,\n BLOCK_SIZE_N: tl.constexpr,\n BLOCK_SIZE_K: tl.constexpr,\n GROUP_SIZE_M: tl.constexpr,\n SPLIT_K: tl.constexpr,\n MUL_ROUTED_WEIGHT: tl.constexpr,\n top_k: tl.constexpr,\n compute_type: tl.constexpr,\n use_fp8_w8a8: tl.constexpr,\n use_int8_w8a8: tl.constexpr,\n use_int8_w8a16: tl.constexpr,\n per_channel_quant: tl.constexpr,\n HAS_BIAS: tl.constexpr,\n):\n \"\"\"\n Implements the fused computation for a Mixture of Experts (MOE) using\n token and expert matrices.\n\n Key Parameters:\n - A: The input tensor representing tokens with shape (*, K), where '*' can\n be any shape representing batches and K is the feature dimension of\n each token.\n - B: The stacked MOE weight tensor with shape (E, N, K), where E is\n the number of experts, K is the input feature dimension, and N is\n the output feature dimension.\n - C: The output cache tensor with shape (M, topk, N), where M is the\n total number of tokens post padding, topk is the number of times\n each token is repeated, and N is the output feature dimension.\n - sorted_token_ids: A tensor containing the sorted indices of tokens,\n repeated topk times and arranged by the expert index they are\n assigned to.\n - expert_ids: A tensor containing the indices of the expert for each\n block. It determines which expert matrix from B should be used for\n each block in A.\n This kernel performs the multiplication of a token by its corresponding\n expert matrix as determined by `expert_ids`. The sorting of\n `sorted_token_ids` by expert index and padding ensures divisibility by\n BLOCK_SIZE_M, which is necessary to maintain consistency in block matrix\n multiplication across different blocks processed by the same expert.\n \"\"\"\n # -----------------------------------------------------------\n # Map program ids `pid` to the block of C it should compute.\n # This is done in a grouped ordering to promote L2 data reuse.\n pid = tl.program_id(axis=0)\n num_pid_m = tl.cdiv(EM, BLOCK_SIZE_M)\n num_pid_n = tl.cdiv(N, BLOCK_SIZE_N)\n num_pid_in_group = GROUP_SIZE_M * num_pid_n\n group_id = pid // num_pid_in_group\n first_pid_m = group_id * GROUP_SIZE_M\n group_size_m = min(num_pid_m - first_pid_m, GROUP_SIZE_M)\n pid_m = first_pid_m + ((pid % num_pid_in_group) % group_size_m)\n pid_n = (pid % num_pid_in_group) // group_size_m\n\n # ----------------------------------------------------------\n # Create pointers for the first blocks of A and B.\n # We will advance this pointer as we move in the K direction\n # and accumulate\n # `a_ptrs` is a block of [BLOCK_SIZE_M, BLOCK_SIZE_K] pointers\n # `b_ptrs` is a block of [BLOCK_SIZE_K, BLOCK_SIZE_N] pointers\n num_tokens_post_padded = tl.load(num_tokens_post_padded_ptr)\n if pid_m * BLOCK_SIZE_M >= num_tokens_post_padded:\n return\n offs_token_id = pid_m * BLOCK_SIZE_M + tl.arange(0, BLOCK_SIZE_M).to(tl.int64)\n offs_token = tl.load(sorted_token_ids_ptr + offs_token_id)\n token_mask = offs_token < num_valid_tokens\n\n off_experts = tl.load(expert_ids_ptr + pid_m).to(tl.int64)\n if off_experts == -1:\n # -----------------------------------------------------------\n # Write back zeros to the output when the expert is not\n # in the current expert parallel rank.\n write_zeros_to_output(\n c_ptr,\n stride_cm,\n stride_cn,\n pid_n,\n N,\n offs_token,\n token_mask,\n BLOCK_SIZE_M,\n BLOCK_SIZE_N,\n compute_type,\n )\n return\n\n offs_bn = (pid_n * BLOCK_SIZE_N + tl.arange(0, BLOCK_SIZE_N).to(tl.int64)) % N\n offs_k = tl.arange(0, BLOCK_SIZE_K)\n a_ptrs = a_ptr + (\n offs_token[:, None] // top_k * stride_am + offs_k[None, :] * stride_ak\n )\n\n b_ptrs = (\n b_ptr\n + off_experts * stride_be\n + (offs_k[:, None] * stride_bk + offs_bn[None, :] * stride_bn)\n )\n if use_int8_w8a16:\n b_scale_ptrs = (\n b_scale_ptr + off_experts * stride_bse + offs_bn[None, :] * stride_bsn\n )\n b_scale = tl.load(b_scale_ptrs)\n\n if use_fp8_w8a8 or use_int8_w8a8:\n # block-wise\n if group_k > 0 and group_n > 0:\n a_scale_ptrs = a_scale_ptr + (offs_token // top_k) * stride_asm\n offs_bsn = offs_bn // group_n\n b_scale_ptrs = (\n b_scale_ptr + off_experts * stride_bse + offs_bsn * stride_bsn\n )\n # channel-wise\n elif per_channel_quant:\n b_scale_ptrs = (\n b_scale_ptr + off_experts * stride_bse + offs_bn[None, :] * stride_bsn\n )\n b_scale = tl.load(b_scale_ptrs)\n # Load per-token scale for activations\n a_scale_ptrs = a_scale_ptr + (offs_token // top_k) * stride_asm\n a_scale = tl.load(a_scale_ptrs, mask=token_mask, other=0.0)[:, None]\n # tensor-wise\n else:\n a_scale = tl.load(a_scale_ptr)\n b_scale = tl.load(b_scale_ptr + off_experts)\n if HAS_BIAS:\n # bias shape: [num_experts, N]\n bias_ptrs = b_bias_ptr + off_experts * stride_bbe + offs_bn * stride_bbn\n bias = tl.load(bias_ptrs, mask=(offs_bn < N), other=0.0)\n # -----------------------------------------------------------\n # Iterate to compute a block of the C matrix.\n # We accumulate into a `[BLOCK_SIZE_M, BLOCK_SIZE_N]` block\n # of fp32 values for higher accuracy.\n # `accumulator` will be converted back to fp16 after the loop.\n accumulator = tl.zeros((BLOCK_SIZE_M, BLOCK_SIZE_N), dtype=tl.float32)\n for k in range(0, tl.cdiv(K, BLOCK_SIZE_K)):\n # Load the next block of A and B, generate a mask by checking the\n # K dimension.\n a = tl.load(\n a_ptrs,\n mask=token_mask[:, None] & (offs_k[None, :] < K - k * BLOCK_SIZE_K),\n other=0.0,\n )\n b = tl.load(b_ptrs, mask=offs_k[:, None] < K - k * BLOCK_SIZE_K, other=0.0)\n # We accumulate along the K dimension.\n if use_int8_w8a16:\n accumulator = tl.dot(a, b.to(compute_type), acc=accumulator)\n elif use_fp8_w8a8 or use_int8_w8a8:\n if group_k > 0 and group_n > 0:\n k_start = k * BLOCK_SIZE_K\n offs_ks = k_start // group_k\n a_scale = tl.load(\n a_scale_ptrs + offs_ks * stride_ask, mask=token_mask, other=0.0\n )\n b_scale = tl.load(b_scale_ptrs + offs_ks * stride_bsk)\n\n accumulator += tl.dot(a, b) * a_scale[:, None] * b_scale[None, :]\n else:\n if use_fp8_w8a8:\n # acc used to enable fp8_fast_accum\n accumulator = tl.dot(a, b, acc=accumulator)\n else:\n accumulator += tl.dot(a, b)\n else:\n accumulator += tl.dot(a, b)\n # Advance the ptrs to the next K block.\n a_ptrs += BLOCK_SIZE_K * stride_ak\n b_ptrs += BLOCK_SIZE_K * stride_bk\n if HAS_BIAS:\n accumulator = accumulator + bias[None, :]\n if MUL_ROUTED_WEIGHT:\n moe_weight = tl.load(topk_weights_ptr + offs_token, mask=token_mask, other=0)\n accumulator = accumulator * moe_weight[:, None]\n if use_int8_w8a16:\n accumulator = (accumulator * b_scale).to(compute_type)\n elif use_fp8_w8a8 or use_int8_w8a8:\n if group_k > 0 and group_n > 0:\n accumulator = accumulator.to(compute_type)\n else:\n accumulator = (accumulator * a_scale * b_scale).to(compute_type)\n else:\n accumulator = accumulator.to(compute_type)\n\n # -----------------------------------------------------------\n # Write back the block of the output\n offs_cn = pid_n * BLOCK_SIZE_N + tl.arange(0, BLOCK_SIZE_N)\n c_ptrs = c_ptr + stride_cm * offs_token[:, None] + stride_cn * offs_cn[None, :]\n c_mask = token_mask[:, None] & (offs_cn[None, :] < N)\n tl.store(c_ptrs, accumulator, mask=c_mask)\n\n\ndef invoke_fused_moe_kernel(\n A: torch.Tensor,\n B: torch.Tensor,\n C: torch.Tensor,\n A_scale: torch.Tensor | None,\n B_scale: torch.Tensor | None,\n B_zp: torch.Tensor | None,\n topk_weights: torch.Tensor | None,\n sorted_token_ids: torch.Tensor,\n expert_ids: torch.Tensor,\n num_tokens_post_padded: torch.Tensor,\n mul_routed_weight: bool,\n top_k: int,\n config: dict[str, Any],\n compute_type: tl.dtype,\n use_fp8_w8a8: bool,\n use_int8_w8a8: bool,\n use_int8_w8a16: bool,\n use_int4_w4a16: bool,\n per_channel_quant: bool,\n block_shape: list[int] | None = None,\n B_bias: torch.Tensor | None = None,\n) -> None:\n assert topk_weights is not None or not mul_routed_weight\n assert topk_weights is None or topk_weights.stride(1) == 1\n assert sorted_token_ids.stride(0) == 1\n\n if use_fp8_w8a8 or use_int8_w8a8:\n assert B_scale is not None\n assert block_shape is None or triton.cdiv(\n B.size(-2), block_shape[0]\n ) == B_scale.size(-2)\n assert block_shape is None or triton.cdiv(\n B.size(-1), block_shape[1]\n ) == B_scale.size(-1)\n\n elif use_int8_w8a16 or use_int4_w4a16:\n assert B_scale is not None\n assert block_shape is None or block_shape[0] == 0\n else:\n assert A_scale is None\n assert B_scale is None\n\n M = A.size(0)\n num_tokens = M * top_k\n\n EM = sorted_token_ids.size(0)\n if A.size(0) < config[\"BLOCK_SIZE_M\"]:\n # optimize for small batch_size.\n # We assume that top_ids of each token is unique,\n # so num_valid_experts <= batch_size <= BLOCK_SIZE_M,\n # and we can skip some invalid blocks.\n EM = min(sorted_token_ids.size(0), A.size(0) * top_k * config[\"BLOCK_SIZE_M\"])\n grid = lambda META: (\n triton.cdiv(EM, META[\"BLOCK_SIZE_M\"])\n * triton.cdiv(B.size(1), META[\"BLOCK_SIZE_N\"]),\n )\n HAS_BIAS = B_bias is not None\n if (\n (use_int8_w8a16 or use_int4_w4a16)\n and block_shape is not None\n and block_shape[1] > 0\n ):\n assert B_scale is not None and B_scale.ndim == 3\n assert B_zp is None or B_zp.ndim == 3\n\n use_moe_wna16_cuda = should_moe_wna16_use_cuda(\n num_valid_tokens=num_tokens,\n group_size=block_shape[1],\n num_experts=B.size(0),\n bit=4 if use_int4_w4a16 else 8,\n )\n config = config.copy()\n config.update(\n get_moe_wna16_block_config(\n config=config,\n use_moe_wna16_cuda=use_moe_wna16_cuda,\n num_valid_tokens=num_tokens,\n size_k=A.size(1),\n size_n=B.size(1),\n num_experts=B.size(1),\n group_size=block_shape[1],\n real_top_k=top_k,\n block_size_m=config[\"BLOCK_SIZE_M\"],\n )\n )\n\n if use_moe_wna16_cuda:\n bit = 4 if use_int4_w4a16 else 8\n ops.moe_wna16_gemm(\n A,\n C,\n B,\n B_scale,\n B_zp,\n topk_weights if mul_routed_weight else None,\n sorted_token_ids,\n expert_ids,\n num_tokens_post_padded,\n top_k,\n config[\"BLOCK_SIZE_M\"],\n config[\"BLOCK_SIZE_N\"],\n config[\"BLOCK_SIZE_K\"],\n bit,\n )\n return\n fused_moe_kernel_gptq_awq[grid](\n A,\n B,\n C,\n B_scale,\n B_zp,\n topk_weights,\n sorted_token_ids,\n expert_ids,\n num_tokens_post_padded,\n B.size(1),\n A.size(1),\n EM,\n num_tokens,\n A.stride(0),\n A.stride(1),\n B.stride(0),\n B.stride(2),\n B.stride(1),\n C.stride(1),\n C.stride(2),\n B_scale.stride(0),\n B_scale.stride(2),\n B_scale.stride(1),\n B_zp.stride(0) if B_zp is not None else 0,\n B_zp.stride(2) if B_zp is not None else 0,\n B_zp.stride(1) if B_zp is not None else 0,\n block_k_diviable=A.size(1) % config[\"BLOCK_SIZE_K\"] == 0,\n group_size=block_shape[1],\n MUL_ROUTED_WEIGHT=mul_routed_weight,\n top_k=top_k,\n compute_type=compute_type,\n has_zp=B_zp is not None,\n use_int4_w4a16=use_int4_w4a16,\n use_int8_w8a16=use_int8_w8a16,\n **config,\n )\n else:\n config = config.copy()\n config[\"SPLIT_K\"] = 1\n BLOCK_SIZE_K = config.pop(\"BLOCK_SIZE_K\")\n if block_shape is not None:\n BLOCK_SIZE_K = min(BLOCK_SIZE_K, min(block_shape[0], block_shape[1]))\n fused_moe_kernel[grid](\n A,\n B,\n C,\n B_bias,\n A_scale,\n B_scale,\n topk_weights,\n sorted_token_ids,\n expert_ids,\n num_tokens_post_padded,\n B.size(1),\n B.size(2),\n EM,\n num_tokens,\n A.stride(0),\n A.stride(1),\n B.stride(0),\n B.stride(2),\n B.stride(1),\n C.stride(1),\n C.stride(2),\n A_scale.stride(0) if A_scale is not None and A_scale.ndim == 2 else 0,\n A_scale.stride(1) if A_scale is not None and A_scale.ndim == 2 else 0,\n B_scale.stride(0) if B_scale is not None and B_scale.ndim >= 2 else 0,\n B_scale.stride(2) if B_scale is not None and B_scale.ndim == 3 else 0,\n B_scale.stride(1) if B_scale is not None and B_scale.ndim >= 2 else 0,\n B_bias.stride(0) if B_bias is not None else 0,\n B_bias.stride(1) if B_bias is not None else 0,\n 0 if block_shape is None else block_shape[0],\n 0 if block_shape is None else block_shape[1],\n MUL_ROUTED_WEIGHT=mul_routed_weight,\n top_k=top_k,\n compute_type=compute_type,\n use_fp8_w8a8=use_fp8_w8a8,\n use_int8_w8a8=use_int8_w8a8,\n use_int8_w8a16=use_int8_w8a16,\n per_channel_quant=per_channel_quant,\n HAS_BIAS=HAS_BIAS,\n BLOCK_SIZE_K=BLOCK_SIZE_K,\n **config,\n )\n\n\n@triton.jit\ndef compute_identity_kernel(\n top_k: int,\n hidden_states_ptr: tl.tensor,\n expert_scales_ptr: tl.tensor,\n num_tokens: int,\n output_ptr: tl.tensor,\n hidden_dim: int,\n scales_stride: int,\n BLOCK_SIZE: tl.constexpr,\n) -> None:\n pid = tl.program_id(0)\n\n batch_id = pid // (hidden_dim // BLOCK_SIZE)\n dim_offset = pid % (hidden_dim // BLOCK_SIZE) * BLOCK_SIZE\n\n if batch_id >= num_tokens or dim_offset >= hidden_dim:\n return\n\n h = tl.load(\n hidden_states_ptr\n + batch_id * hidden_dim\n + dim_offset\n + tl.arange(0, BLOCK_SIZE),\n mask=(dim_offset + tl.arange(0, BLOCK_SIZE)) < hidden_dim,\n )\n\n result = tl.zeros([BLOCK_SIZE], dtype=tl.float32)\n for i in range(top_k):\n scale = tl.load(expert_scales_ptr + batch_id * scales_stride + i)\n result += h * scale\n\n tl.store(\n output_ptr + batch_id * hidden_dim + dim_offset + tl.arange(0, BLOCK_SIZE),\n result,\n mask=(dim_offset + tl.arange(0, BLOCK_SIZE)) < hidden_dim,\n )\n\n\ndef zero_experts_compute_triton(\n expert_indices: torch.Tensor,\n expert_scales: torch.Tensor,\n num_experts: int,\n zero_expert_type: str,\n hidden_states: torch.Tensor,\n) -> torch.Tensor:\n N = expert_indices.numel()\n top_k = expert_indices.size(-1)\n grid = lambda meta: (triton.cdiv(N, meta[\"BLOCK_SIZE\"]),)\n\n if zero_expert_type == \"identity\":\n zero_expert_mask = expert_indices < num_experts\n zero_expert_scales = expert_scales.clone()\n zero_expert_scales[zero_expert_mask] = 0.0\n\n normal_expert_mask = expert_indices >= num_experts\n expert_indices[normal_expert_mask] = 0\n expert_scales[normal_expert_mask] = 0.0\n\n output = torch.zeros_like(hidden_states).to(hidden_states.device)\n hidden_dim = hidden_states.size(-1)\n num_tokens = hidden_states.size(0)\n\n grid = lambda meta: (num_tokens * (hidden_dim // meta[\"BLOCK_SIZE\"]),)\n compute_identity_kernel[grid](\n top_k,\n hidden_states,\n zero_expert_scales,\n num_tokens,\n output,\n hidden_dim,\n zero_expert_scales.stride(0),\n BLOCK_SIZE=256,\n )\n\n return output\n\n\n# Adapted from: https://github.com/sgl-project/sglang/pull/2628\ndef get_config_file_name(\n E: int, N: int, dtype: str | None, block_shape: list[int] | None = None\n) -> str:\n device_name = current_platform.get_device_name().replace(\" \", \"_\")\n # Set device_name to H200 if a device from the H200 family is detected\n if \"H200\" in device_name.split(\"_\"):\n device_name = \"NVIDIA_H200\"\n dtype_selector = \"\" if not dtype else f\",dtype={dtype}\"\n block_shape_selector = (\n \"\" if not block_shape or not all(block_shape) else f\",block_shape={block_shape}\"\n ).replace(\" \", \"\")\n return f\"E={E},N={N},device_name={device_name}{dtype_selector}{block_shape_selector}.json\" # noqa: E501\n\n\n# Adapted from: https://github.com/sgl-project/sglang/pull/2628\n@functools.lru_cache\ndef get_moe_configs(\n E: int,\n N: int,\n dtype: str | None,\n block_n: int | None = None,\n block_k: int | None = None,\n) -> dict[int, Any] | None:\n \"\"\"\n Return optimized configurations for the fused MoE kernel.\n\n The return value will be a dictionary that maps an irregular grid of\n batch sizes to configurations of the fused_moe kernel. To evaluate the\n kernel on a given batch size bs, the closest batch size in the grid should\n be picked and the associated configuration chosen to invoke the kernel.\n \"\"\"\n\n # Avoid optimizing for the batch invariant case. Use default config\n if vllm_is_batch_invariant():\n return None\n\n # First look up if an optimized configuration is available in the configs\n # directory\n block_shape = [block_n, block_k] if block_n and block_k else None\n json_file_name = get_config_file_name(E, N, dtype, block_shape)\n\n config_file_paths = []\n\n # note that we prioritize user defined config\n user_defined_config_folder = envs.VLLM_TUNED_CONFIG_FOLDER\n if user_defined_config_folder is not None:\n user_defined_config_file_path = os.path.join(\n user_defined_config_folder, json_file_name\n )\n config_file_paths.append(user_defined_config_file_path)\n\n default_config_file_path = os.path.join(\n os.path.dirname(os.path.realpath(__file__)), \"configs\", json_file_name\n )\n config_file_paths.append(default_config_file_path)\n\n for config_file_path in config_file_paths:\n if os.path.exists(config_file_path):\n with open(config_file_path) as f:\n logger.info_once(\n \"Using configuration from %s for MoE layer.\",\n config_file_path,\n scope=\"global\",\n )\n # If a configuration has been found, return it\n tuned_config = json.load(f)\n # Delete triton_version from tuned_config\n tuned_config.pop(\"triton_version\", None)\n return {int(key): val for key, val in tuned_config.items()}\n\n # If no optimized configuration is available, we will use the default\n # configuration\n logger.warning(\n (\n \"Using default MoE config. Performance might be sub-optimal! \"\n \"Config file not found at %s\"\n ),\n config_file_paths,\n )\n return None\n\n\ndef get_moe_wna16_block_config(\n config: dict[str, int],\n use_moe_wna16_cuda: bool,\n num_valid_tokens: int,\n size_k: int,\n size_n: int,\n num_experts: int,\n group_size: int,\n real_top_k: int,\n block_size_m: int,\n):\n if \"BLOCK_SIZE_N\" in config and \"BLOCK_SIZE_K\" in config:\n # optimal block config is set\n return {}\n if not use_moe_wna16_cuda:\n # triton moe wna16 kernel\n if num_valid_tokens // real_top_k == 1:\n # if bs=1, use a smaller BLOCK_SIZE_N\n return {\"BLOCK_SIZE_N\": 32, \"BLOCK_SIZE_K\": 64}\n else:\n return {\"BLOCK_SIZE_N\": 64, \"BLOCK_SIZE_K\": 32}\n else:\n # cuda moe wna16 kernel\n # set default block_size 128, and increase them when num_blocks\n # is too large.\n block_size_n = 128\n block_size_k = 128\n if block_size_k <= group_size:\n block_size_k = group_size\n\n num_n_blocks = size_k // block_size_k\n num_k_blocks = size_n // block_size_k\n num_m_blocks = (\n num_valid_tokens + block_size_m - 1\n ) / block_size_m + num_experts\n if num_valid_tokens // real_top_k <= block_size_m:\n num_m_blocks = min(num_m_blocks, num_valid_tokens)\n num_blocks = num_m_blocks * num_n_blocks * num_k_blocks\n\n if size_k % 256 == 0 and num_blocks >= 256 and block_size_k < 256:\n block_size_k = 256\n num_blocks = num_blocks // (256 // block_size_k)\n\n if (\n num_m_blocks <= 16\n and size_k % (block_size_k * 2) == 0\n and size_k % (block_size_k * 2) == 0\n and block_size_k <= 512\n and num_blocks >= 512\n ):\n block_size_k = block_size_k * 2\n num_blocks = num_blocks // 2\n\n if num_blocks > 1024:\n block_size_n = 256\n num_n_blocks = num_n_blocks // 2\n num_blocks = num_blocks // 2\n\n if size_n <= 1024 and num_blocks >= 1024:\n # The kernel performance got much better with BLOCK_SIZE_N=1024\n # when num_blocks is large, event when N is small.\n # Not sure why, maybe it force the CUDA SM process only one block\n # at the same time.\n block_size_n = 1024\n\n return {\"BLOCK_SIZE_N\": block_size_n, \"BLOCK_SIZE_K\": block_size_k}\n\n\ndef should_moe_wna16_use_cuda(\n num_valid_tokens: int, group_size: int, num_experts: int, bit: int\n):\n return (\n current_platform.is_cuda()\n and bit == 4\n and group_size in [32, 64, 128]\n and num_valid_tokens / num_experts <= 6\n )\n\n\ndef get_default_config(\n M: int,\n E: int,\n N: int,\n K: int,\n topk: int,\n dtype: str | None,\n block_shape: list[int] | None = None,\n) -> dict[str, int]:\n if vllm_is_batch_invariant():\n config = {\n \"BLOCK_SIZE_M\": 64,\n \"BLOCK_SIZE_N\": 64,\n \"BLOCK_SIZE_K\": 32,\n \"GROUP_SIZE_M\": 8,\n \"SPLIT_K\": 1,\n }\n return config\n\n if dtype == \"fp8_w8a8\" and block_shape is not None:\n # Block-wise quant: BLOCK_SIZE_N must be divisible by block_shape[0]\n # BLOCK_SIZE_K must be divisible by block_shape[1]\n # num_stages=3 can cause triton.runtime.errors.OutOfResources\n # on ROCm, set it to 2 instead.\n config = {\n \"BLOCK_SIZE_M\": 64,\n \"BLOCK_SIZE_N\": block_shape[0],\n \"BLOCK_SIZE_K\": block_shape[1],\n \"GROUP_SIZE_M\": 32,\n \"SPLIT_K\": 1,\n \"num_warps\": 4,\n \"num_stages\": 3 if not current_platform.is_rocm() else 2,\n }\n elif dtype in [\"int4_w4a16\", \"int8_w8a16\"] and block_shape is not None:\n # moe wna16 kernels\n # only set BLOCK_SIZE_M\n # BLOCK_SIZE_N and BLOCK_SIZE_K would be set later\n bit = 4 if dtype == \"int4_w4a16\" else 8\n use_moe_wna16_cuda = should_moe_wna16_use_cuda(M * topk, block_shape[1], E, bit)\n if use_moe_wna16_cuda:\n config = {\"BLOCK_SIZE_M\": min(16, M), \"SPLIT_K\": 1}\n elif M <= 20:\n config = {\"BLOCK_SIZE_M\": 16, \"GROUP_SIZE_M\": 1, \"SPLIT_K\": 1}\n elif M <= 40:\n config = {\"BLOCK_SIZE_M\": 32, \"GROUP_SIZE_M\": 1, \"SPLIT_K\": 1}\n else:\n config = {\"BLOCK_SIZE_M\": 64, \"GROUP_SIZE_M\": 1, \"SPLIT_K\": 1}\n elif M <= E:\n config = {\n \"BLOCK_SIZE_M\": 16,\n \"BLOCK_SIZE_N\": 32,\n \"BLOCK_SIZE_K\": 64,\n \"GROUP_SIZE_M\": 1,\n \"SPLIT_K\": 1,\n }\n else:\n config = {\n \"BLOCK_SIZE_M\": 64,\n \"BLOCK_SIZE_N\": 64,\n \"BLOCK_SIZE_K\": 32,\n \"GROUP_SIZE_M\": 8,\n \"SPLIT_K\": 1,\n }\n return config\n\n\ndef try_get_optimal_moe_config(\n w1_shape: tuple[int, ...],\n w2_shape: tuple[int, ...],\n top_k: int,\n dtype: str | None,\n M: int,\n block_shape: list[int] | None = None,\n) -> dict[str, int]:\n from vllm.model_executor.layers.fused_moe import get_config\n\n override_config = get_config()\n if override_config:\n config = override_config\n else:\n # First try to load optimal config from the file\n E, _, N = w2_shape\n if dtype == \"int4_w4a16\":\n N = N * 2\n block_n = block_shape[0] if block_shape else 0\n block_k = block_shape[1] if block_shape else 0\n configs = get_moe_configs(E, N, dtype, block_n, block_k)\n\n if configs:\n # If an optimal configuration map has been found, look up the\n # optimal config\n config = configs[min(configs.keys(), key=lambda x: abs(x - M))]\n else:\n # Else use the default config\n config = get_default_config(M, E, N, w1_shape[2], top_k, dtype, block_shape)\n return config\n\n\ndef vllm_topk_softmax(\n topk_weights: torch.Tensor,\n topk_indices: torch.Tensor,\n token_expert_indices: torch.Tensor,\n gating_output: torch.Tensor,\n renormalize: bool,\n) -> tuple[torch.Tensor, ...]:\n ops.topk_softmax(\n topk_weights,\n topk_indices,\n token_expert_indices,\n gating_output,\n renormalize,\n )\n\n return topk_weights, topk_indices\n\n\ndef dispatch_topk_func(\n use_rocm_aiter: bool = False,\n) -> Callable[..., tuple[torch.Tensor, ...]]:\n if use_rocm_aiter:\n return rocm_aiter_ops.topk_softmax\n return vllm_topk_softmax\n\n\ndef fused_topk(\n hidden_states: torch.Tensor,\n gating_output: torch.Tensor,\n topk: int,\n renormalize: bool,\n indices_type: torch.dtype | None = None,\n) -> tuple[torch.Tensor, torch.Tensor, torch.Tensor]:\n assert hidden_states.size(0) == gating_output.size(0), \"Number of tokens mismatch\"\n\n M, _ = hidden_states.size()\n\n topk_weights = torch.empty(\n M, topk, dtype=torch.float32, device=hidden_states.device\n )\n topk_ids = torch.empty(\n M,\n topk,\n dtype=torch.int32 if indices_type is None else indices_type,\n device=hidden_states.device,\n )\n token_expert_indices = torch.empty(\n M, topk, dtype=torch.int32, device=hidden_states.device\n )\n\n topk_func = dispatch_topk_func(use_rocm_aiter=rocm_aiter_ops.is_fused_moe_enabled())\n topk_weights, topk_ids = topk_func(\n topk_weights, topk_ids, token_expert_indices, gating_output, renormalize\n )\n\n return topk_weights, topk_ids, token_expert_indices\n\n\ndef fused_topk_bias(\n hidden_states: torch.Tensor,\n gating_output: torch.Tensor,\n e_score_correction_bias: torch.Tensor,\n topk: int,\n renormalize: bool,\n):\n n_routed_experts = gating_output.shape[-1]\n scores = gating_output.softmax(dim=-1)\n scores_for_choice = scores.view(\n -1, n_routed_experts\n ) + e_score_correction_bias.unsqueeze(0)\n\n # For batch invariance, use sorted=True to ensure deterministic expert selection\n use_sorted = vllm_is_batch_invariant()\n topk_indices = torch.topk(scores_for_choice, k=topk, dim=-1, sorted=use_sorted)[1]\n topk_weights = scores.gather(1, topk_indices)\n if renormalize:\n topk_weights = topk_weights / topk_weights.sum(dim=-1, keepdim=True)\n return topk_weights.to(torch.float32), topk_indices.to(torch.int32)\n\n\n# This is used by the Deepseek-V2 and Deepseek-V3 model\n@torch.compile(\n dynamic=True,\n backend=current_platform.simple_compile_backend,\n options=maybe_disable_graph_partition(current_platform.simple_compile_backend),\n)\ndef grouped_topk(\n hidden_states: torch.Tensor,\n gating_output: torch.Tensor,\n topk: int,\n renormalize: bool,\n num_expert_group: int = 0,\n topk_group: int = 0,\n scoring_func: str = \"softmax\",\n routed_scaling_factor: float = 1.0,\n e_score_correction_bias: torch.Tensor | None = None,\n) -> tuple[torch.Tensor, torch.Tensor]:\n if (\n envs.VLLM_USE_FUSED_MOE_GROUPED_TOPK\n and current_platform.is_cuda()\n and num_expert_group <= 32\n and topk <= 32\n and e_score_correction_bias is not None\n ):\n return fused_grouped_topk(\n hidden_states=hidden_states,\n gating_output=gating_output,\n topk=topk,\n renormalize=renormalize,\n e_score_correction_bias=e_score_correction_bias,\n num_expert_group=num_expert_group,\n topk_group=topk_group,\n scoring_func=scoring_func,\n routed_scaling_factor=routed_scaling_factor,\n )\n\n assert hidden_states.size(0) == gating_output.size(0), \"Number of tokens mismatch\"\n\n if scoring_func == \"softmax\":\n scores = torch.softmax(gating_output, dim=-1)\n elif scoring_func == \"sigmoid\":\n scores = gating_output.sigmoid()\n else:\n raise ValueError(f\"Unsupported scoring function: {scoring_func}\")\n\n num_token = scores.size(0)\n if e_score_correction_bias is not None:\n # Store original scores before applying correction bias. We use biased\n # scores for expert selection but original scores for routing weights\n original_scores = scores\n scores = scores + e_score_correction_bias.unsqueeze(0)\n group_scores = (\n scores.view(num_token, num_expert_group, -1).topk(2, dim=-1)[0].sum(dim=-1)\n )\n else:\n group_scores = (\n scores.view(num_token, num_expert_group, -1).max(dim=-1).values\n ) # [n, n_group]\n\n # For batch invariance, use sorted=True to ensure deterministic expert selection\n use_sorted = vllm_is_batch_invariant()\n group_idx = torch.topk(group_scores, k=topk_group, dim=-1, sorted=use_sorted)[\n 1\n ] # [n, top_k_group]\n group_mask = torch.zeros_like(group_scores) # [n, n_group]\n group_mask.scatter_(1, group_idx, 1) # [n, n_group]\n score_mask = (\n group_mask.unsqueeze(-1)\n .expand(num_token, num_expert_group, scores.size(-1) // num_expert_group)\n .reshape(num_token, -1)\n ) # [n, e]\n tmp_scores = scores.masked_fill(~score_mask.bool(), float(\"-inf\")) # [n, e]\n\n if e_score_correction_bias is not None:\n topk_ids = torch.topk(tmp_scores, k=topk, dim=-1, sorted=use_sorted)[1]\n # Use original unbiased scores for the routing weights\n topk_weights = original_scores.gather(1, topk_ids)\n else:\n topk_weights, topk_ids = torch.topk(\n tmp_scores, k=topk, dim=-1, sorted=use_sorted\n )\n\n if renormalize:\n topk_weights = topk_weights / topk_weights.sum(dim=-1, keepdim=True)\n\n if routed_scaling_factor != 1.0:\n topk_weights = topk_weights * routed_scaling_factor\n return topk_weights.to(torch.float32), topk_ids.to(torch.int32)\n\n\n@torch.compile(dynamic=True, backend=current_platform.simple_compile_backend)\ndef eplb_map_to_physical_and_record(\n topk_ids: torch.Tensor,\n expert_load_view: torch.Tensor,\n logical_to_physical_map: torch.Tensor,\n logical_replica_count: torch.Tensor,\n) -> torch.Tensor:\n \"\"\"\n Map the logical expert ids to physical expert ids\n and record the expert load metrics.\n\n This will select a pseudo-random replica for each logical expert.\n Only used for EPLB.\n\n Args:\n topk_ids: The logical expert ids.\n expert_load_view: The expert load view.\n logical_to_physical_map: The logical to physical map.\n logical_replica_count: The logical replica count.\n\n Returns:\n The physical expert ids.\n \"\"\"\n\n # 1. Convert the logical expert ids to physical expert ids\n # Directly select a random replica for each logical expert\n\n # In case `indices_type` is not `torch.long` or `torch.int`,\n # e.g. `torch.uint32` as required by dispatch/combine kernels\n topk_ids_long = topk_ids.long()\n # Use (token position) modulo (replica count)\n # to deterministically choose a replica\n replica_count = logical_replica_count[topk_ids_long]\n # Flatten-position based index, reshaped back to `topk_ids` shape\n pos_indices = torch.arange(\n topk_ids.numel(), device=topk_ids.device, dtype=torch.long\n ).reshape_as(topk_ids)\n # Compute pseudo-random indices by modulo\n replica_indices = (pos_indices % replica_count).unsqueeze(-1)\n physical_ids = (\n logical_to_physical_map[topk_ids_long].gather(-1, replica_indices).squeeze(-1)\n )\n\n topk_ids = physical_ids\n\n # 2. Record expert load metrics.\n\n # TODO(bowen): When using `FusedMoEModularKernel`, this\n # can be done in a more unified way, since\n # `FusedMoEPrepareAndFinalize` will return the expert\n # token count, in some cases directly from the kernel.\n # However, now there are many code paths not using\n # the modular kernel, e.g. calling `fused_experts`,\n # so we decide to keep the logic here.\n #\n # If later refactor moved all the MoE kernel calls\n # to the modular kernel, we can move this logic there\n # to achieve better efficiency.\n\n # `expert_load_view`: (num_physical_experts,)\n\n # `torch.bincount` is not compilable, so use `scatter_add_` instead.\n topk_ids_flatten = topk_ids.flatten()\n expert_load_view.scatter_add_(\n dim=0,\n index=topk_ids_flatten.long(),\n src=torch.ones_like(topk_ids_flatten).to(expert_load_view),\n )\n return topk_ids\n\n\ndef fused_grouped_topk(\n hidden_states: torch.Tensor,\n gating_output: torch.Tensor,\n topk: int,\n renormalize: bool,\n e_score_correction_bias: torch.Tensor,\n num_expert_group: int = 0,\n topk_group: int = 0,\n scoring_func: str = \"softmax\",\n routed_scaling_factor: float = 1.0,\n) -> tuple[torch.Tensor, torch.Tensor]:\n assert hidden_states.size(0) == gating_output.size(0), \"Number of tokens mismatch\"\n\n if scoring_func == \"sigmoid\":\n # Fully fused kernel path for sigmoid\n topk_values, topk_indices = ops.grouped_topk(\n gating_output, # raw logits\n num_expert_group,\n topk_group,\n topk,\n renormalize,\n routed_scaling_factor,\n e_score_correction_bias.to(gating_output.dtype),\n 1, # scoring_func=1 for sigmoid\n )\n elif scoring_func == \"softmax\":\n # Apply softmax in Python, then use fused kernel\n # TODO: Add support for softmax in kernel\n scores = torch.softmax(gating_output, dim=-1)\n topk_values, topk_indices = ops.grouped_topk(\n scores, # pre-computed scores\n num_expert_group,\n topk_group,\n topk,\n renormalize,\n routed_scaling_factor,\n e_score_correction_bias.to(gating_output.dtype),\n 0, # scoring_func=0 (no activation, scores already computed)\n )\n else:\n raise ValueError(f\"Unsupported scoring function: {scoring_func}\")\n\n # Fused kernel outputs float32 values and int32 indices directly\n return topk_values, topk_indices\n\n\ndef inplace_fused_experts(\n hidden_states: torch.Tensor,\n w1: torch.Tensor,\n w2: torch.Tensor,\n topk_weights: torch.Tensor,\n topk_ids: torch.Tensor,\n activation: str = \"silu\",\n apply_router_weight_on_input: bool = False,\n use_fp8_w8a8: bool = False,\n use_int8_w8a8: bool = False,\n use_int8_w8a16: bool = False,\n use_int4_w4a16: bool = False,\n ocp_mx_scheme: str | None = None,\n per_channel_quant: bool = False,\n global_num_experts: int = -1,\n expert_map: torch.Tensor | None = None,\n w1_scale: torch.Tensor | None = None,\n w2_scale: torch.Tensor | None = None,\n w1_zp: torch.Tensor | None = None,\n w2_zp: torch.Tensor | None = None,\n a1_scale: torch.Tensor | None = None,\n a2_scale: torch.Tensor | None = None,\n block_shape: list[int] | None = None,\n w1_bias: torch.Tensor | None = None,\n w2_bias: torch.Tensor | None = None,\n) -> None:\n fused_experts_impl(\n hidden_states,\n w1,\n w2,\n topk_weights,\n topk_ids,\n True,\n activation,\n apply_router_weight_on_input,\n use_fp8_w8a8,\n use_int8_w8a8,\n use_int8_w8a16,\n use_int4_w4a16,\n ocp_mx_scheme,\n per_channel_quant,\n global_num_experts,\n expert_map,\n w1_scale,\n w2_scale,\n w1_zp,\n w2_zp,\n a1_scale,\n a2_scale,\n block_shape,\n w1_bias,\n w2_bias,\n )\n\n\ndef inplace_fused_experts_fake(\n hidden_states: torch.Tensor,\n w1: torch.Tensor,\n w2: torch.Tensor,\n topk_weights: torch.Tensor,\n topk_ids: torch.Tensor,\n activation: str = \"silu\",\n apply_router_weight_on_input: bool = False,\n use_fp8_w8a8: bool = False,\n use_int8_w8a8: bool = False,\n use_int8_w8a16: bool = False,\n use_int4_w4a16: bool = False,\n ocp_mx_scheme: str | None = None,\n per_channel_quant: bool = False,\n global_num_experts: int = -1,\n expert_map: torch.Tensor | None = None,\n w1_scale: torch.Tensor | None = None,\n w2_scale: torch.Tensor | None = None,\n w1_zp: torch.Tensor | None = None,\n w2_zp: torch.Tensor | None = None,\n a1_scale: torch.Tensor | None = None,\n a2_scale: torch.Tensor | None = None,\n block_shape: list[int] | None = None,\n w1_bias: torch.Tensor | None = None,\n w2_bias: torch.Tensor | None = None,\n) -> None:\n pass\n\n\ndirect_register_custom_op(\n op_name=\"inplace_fused_experts\",\n op_func=inplace_fused_experts,\n mutates_args=[\"hidden_states\"],\n fake_impl=inplace_fused_experts_fake,\n tags=(\n ()\n if is_torch_equal_or_newer(\"2.7.0\")\n else (torch.Tag.needs_fixed_stride_order,)\n ),\n)\n\n\ndef outplace_fused_experts(\n hidden_states: torch.Tensor,\n w1: torch.Tensor,\n w2: torch.Tensor,\n topk_weights: torch.Tensor,\n topk_ids: torch.Tensor,\n activation: str = \"silu\",\n apply_router_weight_on_input: bool = False,\n use_fp8_w8a8: bool = False,\n use_int8_w8a8: bool = False,\n use_int8_w8a16: bool = False,\n use_int4_w4a16: bool = False,\n ocp_mx_scheme: str | None = None,\n per_channel_quant: bool = False,\n global_num_experts: int = -1,\n expert_map: torch.Tensor | None = None,\n w1_scale: torch.Tensor | None = None,\n w2_scale: torch.Tensor | None = None,\n w1_zp: torch.Tensor | None = None,\n w2_zp: torch.Tensor | None = None,\n a1_scale: torch.Tensor | None = None,\n a2_scale: torch.Tensor | None = None,\n block_shape: list[int] | None = None,\n w1_bias: torch.Tensor | None = None,\n w2_bias: torch.Tensor | None = None,\n) -> torch.Tensor:\n return fused_experts_impl(\n hidden_states,\n w1,\n w2,\n topk_weights,\n topk_ids,\n False,\n activation,\n apply_router_weight_on_input,\n use_fp8_w8a8,\n use_int8_w8a8,\n use_int8_w8a16,\n use_int4_w4a16,\n ocp_mx_scheme,\n per_channel_quant,\n global_num_experts,\n expert_map,\n w1_scale,\n w2_scale,\n w1_zp,\n w2_zp,\n a1_scale,\n a2_scale,\n block_shape,\n w1_bias,\n w2_bias,\n )\n\n\ndef outplace_fused_experts_fake(\n hidden_states: torch.Tensor,\n w1: torch.Tensor,\n w2: torch.Tensor,\n topk_weights: torch.Tensor,\n topk_ids: torch.Tensor,\n activation: str = \"silu\",\n use_fp8_w8a8: bool = False,\n use_int8_w8a8: bool = False,\n use_int8_w8a16: bool = False,\n use_int4_w4a16: bool = False,\n ocp_mx_scheme: str | None = None,\n per_channel_quant: bool = False,\n global_num_experts: int = -1,\n expert_map: torch.Tensor | None = None,\n w1_scale: torch.Tensor | None = None,\n w2_scale: torch.Tensor | None = None,\n w1_zp: torch.Tensor | None = None,\n w2_zp: torch.Tensor | None = None,\n a1_scale: torch.Tensor | None = None,\n a2_scale: torch.Tensor | None = None,\n block_shape: list[int] | None = None,\n w1_bias: torch.Tensor | None = None,\n w2_bias: torch.Tensor | None = None,\n) -> torch.Tensor:\n return torch.empty_like(hidden_states)\n\n\ndirect_register_custom_op(\n op_name=\"outplace_fused_experts\",\n op_func=outplace_fused_experts,\n fake_impl=outplace_fused_experts_fake,\n tags=(\n ()\n if is_torch_equal_or_newer(\"2.7.0\")\n else (torch.Tag.needs_fixed_stride_order,)\n ),\n)\n\n\ndef torch_vllm_inplace_fused_experts(**kwargs) -> torch.Tensor:\n torch.ops.vllm.inplace_fused_experts(**kwargs)\n hidden_states = kwargs[\"hidden_states\"]\n return hidden_states\n\n\ndef torch_vllm_outplace_fused_experts(**kwargs) -> torch.Tensor:\n return torch.ops.vllm.outplace_fused_experts(**kwargs)\n\n\ndef dispatch_fused_experts_func(inplace: bool) -> Callable[..., torch.Tensor]:\n if inplace and not disable_inplace():\n return torch_vllm_inplace_fused_experts\n return torch_vllm_outplace_fused_experts\n\n\n# TODO (bnell): replace this with modular op. Can get rid of inplace/outplace\n# torch ops.\ndef fused_experts(\n hidden_states: torch.Tensor,\n w1: torch.Tensor,\n w2: torch.Tensor,\n topk_weights: torch.Tensor,\n topk_ids: torch.Tensor,\n inplace: bool = False,\n activation: str = \"silu\",\n apply_router_weight_on_input: bool = False,\n global_num_experts: int = -1,\n expert_map: torch.Tensor | None = None,\n quant_config: FusedMoEQuantConfig | None = None,\n allow_deep_gemm: bool = False,\n allow_cutlass_block_scaled_grouped_gemm: bool = False,\n) -> torch.Tensor:\n if quant_config is None:\n quant_config = FUSED_MOE_UNQUANTIZED_CONFIG\n use_fp8_w8a8 = quant_config.use_fp8_w8a8\n\n # For now, disable DeepGemm for small N (<= 512) until better\n # permute/unpermute ops are available.\n # However, on B200, we use DeepGemm for all cases because they only support\n # E8M0 scale, which means we requantize the weight and input to the specific\n # scale. Fallen back to cutlass or triton for some cases would cause\n # accuracy issue.\n if (\n allow_deep_gemm\n and quant_config.use_fp8_w8a8\n and (is_deep_gemm_e8m0_used() or _valid_deep_gemm(hidden_states, w1, w2))\n ):\n assert quant_config is not None\n assert apply_router_weight_on_input is False\n return deep_gemm_moe_fp8(\n hidden_states=hidden_states,\n w1=w1,\n w2=w2,\n topk_weights=topk_weights,\n topk_ids=topk_ids,\n inplace=inplace,\n activation=activation,\n global_num_experts=global_num_experts,\n expert_map=expert_map,\n w1_scale=quant_config.w1_scale,\n w2_scale=quant_config.w2_scale,\n a1_scale=quant_config.a1_scale,\n a2_scale=quant_config.a2_scale,\n apply_router_weight_on_input=apply_router_weight_on_input,\n )\n elif (\n allow_cutlass_block_scaled_grouped_gemm\n and use_fp8_w8a8\n and _valid_cutlass_block_scaled_grouped_gemm(\n w1, w2, inplace, activation, apply_router_weight_on_input, expert_map\n )\n ):\n assert quant_config is not None\n return run_cutlass_block_scaled_fused_experts(\n a=hidden_states,\n w1=w1,\n w2=w2,\n w1_scale=quant_config.w1_scale,\n w2_scale=quant_config.w2_scale,\n topk_weights=topk_weights,\n topk_ids=topk_ids,\n )\n else:\n return dispatch_fused_experts_func(inplace)(\n hidden_states=hidden_states,\n w1=w1,\n w2=w2,\n topk_weights=topk_weights,\n topk_ids=topk_ids,\n activation=activation,\n apply_router_weight_on_input=apply_router_weight_on_input,\n use_fp8_w8a8=quant_config.use_fp8_w8a8,\n use_int8_w8a8=quant_config.use_int8_w8a8,\n use_int8_w8a16=quant_config.use_int8_w8a16,\n use_int4_w4a16=quant_config.use_int4_w4a16,\n ocp_mx_scheme=quant_config.ocp_mx_scheme,\n per_channel_quant=quant_config.per_act_token_quant,\n global_num_experts=global_num_experts,\n expert_map=expert_map,\n w1_scale=quant_config.w1_scale,\n w2_scale=quant_config.w2_scale,\n w1_zp=quant_config.w1_zp,\n w2_zp=quant_config.w2_zp,\n a1_scale=quant_config.a1_scale,\n a2_scale=quant_config.a2_scale,\n block_shape=quant_config.block_shape,\n w1_bias=quant_config.w1_bias,\n w2_bias=quant_config.w2_bias,\n )\n\n\nSILU_NO_MUL: str = activation_without_mul(\"silu\")\nGELU_NO_MUL: str = activation_without_mul(\"gelu\")\nRELU2_NO_MUL: str = activation_without_mul(\"relu2\")\n\n\ndef _get_config_quant_dtype(\n use_fp8_w8a8: bool,\n use_int8_w8a8: bool,\n ocp_mx_scheme: str | None,\n) -> None | torch.dtype | str:\n \"\"\"\n Get the quantization type based on the quantization strategy flags.\n We don't have a quant_config at this point so we need to work backwards.\n A return type of None means no quantization is required because the\n input is unquantized or has been quantized prior to calling\n fused_experts_impl.\n \"\"\"\n if use_fp8_w8a8:\n return torch.float8_e4m3fn\n elif use_int8_w8a8:\n return torch.int8\n elif ocp_mx_scheme == \"w_mxfp4_a_mxfp4\":\n return \"mxfp4\"\n elif ocp_mx_scheme in {\"w_mxfp4_a_mxfp6_e3m2\", \"w_mxfp6_e3m2_a_mxfp6_e3m2\"}:\n return \"mxfp6_e3m2\"\n elif ocp_mx_scheme in {\"w_mxfp4_a_mxfp6_e2m3\", \"w_mxfp6_e2m3_a_mxfp6_e2m3\"}:\n return \"mxfp6_e2m3\"\n return None\n\n\ndef fused_experts_impl(\n hidden_states: torch.Tensor,\n w1: torch.Tensor,\n w2: torch.Tensor,\n topk_weights: torch.Tensor,\n topk_ids: torch.Tensor,\n inplace: bool = False,\n activation: str = \"silu\",\n apply_router_weight_on_input: bool = False,\n use_fp8_w8a8: bool = False,\n use_int8_w8a8: bool = False,\n use_int8_w8a16: bool = False,\n use_int4_w4a16: bool = False,\n ocp_mx_scheme: str | None = None,\n per_channel_quant: bool = False,\n global_num_experts: int = -1,\n expert_map: torch.Tensor | None = None,\n w1_scale: torch.Tensor | None = None,\n w2_scale: torch.Tensor | None = None,\n w1_zp: torch.Tensor | None = None,\n w2_zp: torch.Tensor | None = None,\n a1_scale: torch.Tensor | None = None,\n a2_scale: torch.Tensor | None = None,\n block_shape: list[int] | None = None,\n w1_bias: torch.Tensor | None = None,\n w2_bias: torch.Tensor | None = None,\n) -> torch.Tensor:\n # Check constraints.\n if use_int4_w4a16:\n assert hidden_states.size(1) // 2 == w1.size(2), \"Hidden size mismatch\"\n elif ocp_mx_scheme is not None:\n if ocp_mx_scheme in {\n \"w_mxfp4_a_mxfp4\",\n \"w_mxfp4_a_mxfp6_e3m2\",\n \"w_mxfp4_a_mxfp6_e2m3\",\n }:\n # 16bit activation and fp4x2 packed weight\n assert hidden_states.size(1) == w1.size(2) * 2, \"hidden size mismatch\"\n elif ocp_mx_scheme in {\n \"w_mxfp6_e3m2_a_mxfp6_e3m2\",\n \"w_mxfp6_e2m3_a_mxfp6_e2m3\",\n }:\n assert hidden_states.size(1) == (w1.size(2) * 4) // 3, (\n \"hidden size mismatch\"\n )\n else:\n raise NotImplementedError(f\"Unsupported ocp_mx_scheme={ocp_mx_scheme}\")\n else:\n assert hidden_states.size(1) == w1.size(2), (\n f\"Hidden size mismatch {hidden_states.size(1)} != {w1.size(2)}\"\n )\n\n assert topk_weights.size() == topk_ids.size(), \"topk shape mismatch\"\n assert hidden_states.is_contiguous(), \"Hidden_states must be contiguous\"\n assert w1.stride(-1) == 1, \"Stride of last dimension must be 1\"\n assert w2.stride(-1) == 1, \"Stride of last dimension must be 1\"\n assert hidden_states.dtype in [torch.float32, torch.float16, torch.bfloat16]\n\n num_tokens = hidden_states.size(0)\n E, N, _ = w1.size()\n K = w2.size(1)\n if global_num_experts == -1:\n global_num_experts = E\n top_k_num = topk_ids.size(1)\n # We execute the fused_moe kernel in chunks to circumvent this issue:\n # https://github.com/vllm-project/vllm/issues/5938\n CHUNK_SIZE = envs.VLLM_FUSED_MOE_CHUNK_SIZE\n M = min(num_tokens, CHUNK_SIZE)\n\n config_dtype = _get_config_dtype_str(\n use_fp8_w8a8=use_fp8_w8a8,\n use_int8_w8a16=use_int8_w8a16,\n use_int4_w4a16=use_int4_w4a16,\n ocp_mx_scheme=ocp_mx_scheme,\n dtype=hidden_states.dtype,\n )\n\n # Note: for use_int8_w8a16 or use_int4_w4a16, the activations are\n # quantized prior to calling fused_experts.\n quant_dtype = _get_config_quant_dtype(\n use_fp8_w8a8=use_fp8_w8a8,\n use_int8_w8a8=use_int8_w8a8,\n ocp_mx_scheme=ocp_mx_scheme,\n )\n\n get_config_func = functools.partial(\n try_get_optimal_moe_config,\n w1.size(),\n w2.size(),\n top_k_num,\n config_dtype,\n block_shape=block_shape,\n )\n\n config = get_config_func(M)\n\n # We can reuse the memory between these because by the time we need\n # cache3, we're done with cache1\n cache13 = torch.empty(\n M * top_k_num * max(N, K),\n device=hidden_states.device,\n dtype=hidden_states.dtype,\n )\n intermediate_cache1 = cache13[: M * top_k_num * N].view(M, top_k_num, N)\n intermediate_cache3 = cache13[: M * top_k_num * K].view(M, top_k_num, K)\n\n # This needs separate memory since it's used concurrently with cache1\n intermediate_cache2 = torch.empty(\n (M * top_k_num, N // 2), device=hidden_states.device, dtype=hidden_states.dtype\n )\n\n if hidden_states.dtype == torch.bfloat16:\n compute_type = tl.bfloat16\n elif hidden_states.dtype == torch.float16:\n compute_type = tl.float16\n elif hidden_states.dtype == torch.float32:\n compute_type = tl.float32\n else:\n raise ValueError(f\"Unsupported compute_type: {hidden_states.dtype}\")\n\n if inplace and not disable_inplace():\n out_hidden_states = hidden_states\n else:\n out_hidden_states = torch.empty_like(hidden_states)\n\n if ocp_mx_scheme is not None:\n # TODO: On platforms for which `current_platform.supports_mx()` is True\n # and for which we have a native OCP mx fused MOE kernel,\n # this dequantization step should not be done.\n if ocp_mx_scheme in {\n OCP_MX_Scheme.w_mxfp4_a_mxfp4,\n OCP_MX_Scheme.w_mxfp4_a_mxfp6_e3m2,\n OCP_MX_Scheme.w_mxfp4_a_mxfp6_e2m3,\n }:\n # Weight has to be dequantized for mxfp4 emulation.\n w1 = dequant_mxfp4(w1, w1_scale, hidden_states.dtype)\n w1_scale = None\n w2 = dequant_mxfp4(w2, w2_scale, hidden_states.dtype)\n w2_scale = None\n elif ocp_mx_scheme == OCP_MX_Scheme.w_mxfp6_e3m2_a_mxfp6_e3m2:\n w1 = dequant_mxfp6(\n w1, w1_scale, quant_dtype=\"fp6_e3m2\", float_dtype=hidden_states.dtype\n )\n w1_scale = None\n w2 = dequant_mxfp6(\n w2, w2_scale, quant_dtype=\"fp6_e3m2\", float_dtype=hidden_states.dtype\n )\n w2_scale = None\n elif ocp_mx_scheme == OCP_MX_Scheme.w_mxfp6_e2m3_a_mxfp6_e2m3:\n w1 = dequant_mxfp6(\n w1, w1_scale, quant_dtype=\"fp6_e2m3\", float_dtype=hidden_states.dtype\n )\n w1_scale = None\n w2 = dequant_mxfp6(\n w2, w2_scale, quant_dtype=\"fp6_e2m3\", float_dtype=hidden_states.dtype\n )\n w2_scale = None\n else:\n raise NotImplementedError(f\"Unsupported ocp_mx_scheme={ocp_mx_scheme}\")\n\n for chunk in range((num_tokens // CHUNK_SIZE) + 1):\n begin_chunk_idx, end_chunk_idx = (\n chunk * CHUNK_SIZE,\n min((chunk + 1) * CHUNK_SIZE, num_tokens),\n )\n curr_hidden_states = hidden_states[begin_chunk_idx:end_chunk_idx]\n tokens_in_chunk, _ = curr_hidden_states.size()\n\n if tokens_in_chunk == 0:\n break\n\n if tokens_in_chunk < CHUNK_SIZE and chunk > 0:\n # Adjust the intermediate cache size and config for the last\n # chunk. Note that in most cases we only have one chunk\n # so the cache size and config are already set correctly and\n # do not need to be adjusted.\n intermediate_cache1 = intermediate_cache1[:tokens_in_chunk]\n intermediate_cache2 = intermediate_cache2[\n : tokens_in_chunk * topk_ids.size(1)\n ]\n intermediate_cache3 = intermediate_cache3[:tokens_in_chunk]\n config = get_config_func(tokens_in_chunk)\n\n curr_topk_ids = topk_ids[begin_chunk_idx:end_chunk_idx]\n curr_topk_weights = topk_weights[begin_chunk_idx:end_chunk_idx]\n qcurr_hidden_states, a1q_scale = moe_kernel_quantize_input(\n A=curr_hidden_states,\n A_scale=a1_scale,\n quant_dtype=quant_dtype,\n per_act_token_quant=per_channel_quant,\n block_shape=block_shape,\n )\n\n sorted_token_ids, expert_ids, num_tokens_post_padded = moe_align_block_size(\n curr_topk_ids, config[\"BLOCK_SIZE_M\"], global_num_experts, expert_map\n )\n\n invoke_fused_moe_kernel(\n qcurr_hidden_states,\n w1,\n intermediate_cache1,\n a1q_scale,\n w1_scale,\n w1_zp,\n curr_topk_weights,\n sorted_token_ids,\n expert_ids,\n num_tokens_post_padded,\n apply_router_weight_on_input,\n top_k_num,\n config,\n compute_type=compute_type,\n use_fp8_w8a8=use_fp8_w8a8,\n use_int8_w8a8=use_int8_w8a8,\n use_int8_w8a16=use_int8_w8a16,\n use_int4_w4a16=use_int4_w4a16,\n per_channel_quant=per_channel_quant,\n block_shape=block_shape,\n B_bias=w1_bias,\n )\n\n # Activation function with multiplication\n if activation == \"silu\":\n torch.ops._C.silu_and_mul(\n intermediate_cache2, intermediate_cache1.view(-1, N)\n )\n elif activation == \"gelu\":\n torch.ops._C.gelu_and_mul(\n intermediate_cache2, intermediate_cache1.view(-1, N)\n )\n elif activation == \"swigluoai\":\n # alpha = 1.702, limit = 7.0\n torch.ops._C.swigluoai_and_mul(\n intermediate_cache2, intermediate_cache1.view(-1, N)\n )\n # Activation function without multiplication\n elif activation == SILU_NO_MUL:\n intermediate_cache2 = F.silu(intermediate_cache1.view(-1, N))\n elif activation == GELU_NO_MUL:\n intermediate_cache2 = F.gelu(intermediate_cache1.view(-1, N))\n elif activation == RELU2_NO_MUL:\n intermediate_cache2 = torch.square(F.relu(intermediate_cache1.view(-1, N)))\n else:\n raise ValueError(f\"Unsupported FusedMoe activation: {activation}.\")\n\n qintermediate_cache2, a2q_scale = moe_kernel_quantize_input(\n A=intermediate_cache2,\n A_scale=a2_scale,\n quant_dtype=quant_dtype,\n per_act_token_quant=per_channel_quant,\n block_shape=block_shape,\n )\n\n invoke_fused_moe_kernel(\n qintermediate_cache2,\n w2,\n intermediate_cache3,\n a2q_scale,\n w2_scale,\n w2_zp,\n curr_topk_weights,\n sorted_token_ids,\n expert_ids,\n num_tokens_post_padded,\n not apply_router_weight_on_input,\n 1,\n config,\n compute_type=compute_type,\n use_fp8_w8a8=use_fp8_w8a8,\n use_int8_w8a8=use_int8_w8a8,\n use_int8_w8a16=use_int8_w8a16,\n use_int4_w4a16=use_int4_w4a16,\n per_channel_quant=per_channel_quant,\n block_shape=block_shape,\n B_bias=w2_bias,\n )\n\n ops.moe_sum(\n intermediate_cache3.view(*intermediate_cache3.size()),\n out_hidden_states[begin_chunk_idx:end_chunk_idx],\n )\n\n return out_hidden_states\n\n\nclass TritonExperts(mk.FusedMoEPermuteExpertsUnpermute):\n def __init__(\n self,\n quant_config: FusedMoEQuantConfig,\n ):\n super().__init__(quant_config)\n\n @property\n def activation_formats(\n self,\n ) -> tuple[mk.FusedMoEActivationFormat, mk.FusedMoEActivationFormat]:\n return (\n mk.FusedMoEActivationFormat.Standard,\n mk.FusedMoEActivationFormat.Standard,\n )\n\n def supports_chunking(self) -> bool:\n return True\n\n def supports_expert_map(self) -> bool:\n return True\n\n def finalize_weight_and_reduce_impl(self) -> mk.TopKWeightAndReduce:\n return TopKWeightAndReduceNoOP()\n\n def workspace_shapes(\n self,\n M: int,\n N: int,\n K: int,\n topk: int,\n global_num_experts: int,\n local_num_experts: int,\n expert_tokens_meta: mk.ExpertTokensMetadata | None,\n ) -> tuple[tuple[int, ...], tuple[int, ...], tuple[int, ...]]:\n workspace1 = (M, topk, max(N // 2, K))\n workspace2 = (M, topk, max(N, K))\n output = (M, K)\n return (workspace1, workspace2, output)\n\n def apply(\n self,\n output: torch.Tensor,\n hidden_states: torch.Tensor,\n w1: torch.Tensor,\n w2: torch.Tensor,\n topk_weights: torch.Tensor,\n topk_ids: torch.Tensor,\n activation: str,\n global_num_experts: int,\n expert_map: torch.Tensor | None,\n a1q_scale: torch.Tensor | None,\n a2_scale: torch.Tensor | None,\n workspace13: torch.Tensor,\n workspace2: torch.Tensor,\n expert_tokens_meta: mk.ExpertTokensMetadata | None,\n apply_router_weight_on_input: bool,\n ):\n # Check constraints.\n if self.quant_config.use_int4_w4a16:\n assert hidden_states.size(-1) // 2 == w1.size(2), \"Hidden size mismatch\"\n else:\n assert hidden_states.size(-1) == w1.size(2), (\n f\"Hidden size mismatch {hidden_states.size(-1)} != {w1.size(2)}\"\n )\n\n assert hidden_states.is_contiguous(), \"Hidden_states must be contiguous\"\n assert hidden_states.dim() == 2\n assert w1.stride(-1) == 1, \"Stride of last dimension must be 1\"\n assert w2.stride(-1) == 1, \"Stride of last dimension must be 1\"\n assert hidden_states.dtype in [\n torch.float32,\n torch.float16,\n torch.bfloat16,\n torch.float8_e4m3fn,\n ]\n\n E, num_tokens, N, K, top_k_num = self.moe_problem_size(\n hidden_states, w1, w2, topk_ids\n )\n\n if global_num_experts == -1:\n global_num_experts = E\n\n config = try_get_optimal_moe_config(\n w1.size(),\n w2.size(),\n top_k_num,\n self.quant_config.config_name(hidden_states.dtype),\n num_tokens,\n block_shape=self.block_shape,\n )\n\n if hidden_states.dtype == torch.bfloat16:\n compute_type = tl.bfloat16\n elif hidden_states.dtype == torch.float16:\n compute_type = tl.float16\n elif hidden_states.dtype == torch.float32:\n compute_type = tl.float32\n elif hidden_states.dtype == torch.float8_e4m3fn:\n compute_type = tl.bfloat16\n else:\n raise ValueError(f\"Unsupported compute_type: {hidden_states.dtype}\")\n\n # Note that the output tensor might be in workspace1\n intermediate_cache1 = _resize_cache(workspace2, (num_tokens, top_k_num, N))\n intermediate_cache2 = _resize_cache(\n workspace13, (num_tokens * top_k_num, N // 2)\n )\n intermediate_cache3 = _resize_cache(workspace2, (num_tokens, top_k_num, K))\n\n sorted_token_ids, expert_ids, num_tokens_post_padded = moe_align_block_size(\n topk_ids, config[\"BLOCK_SIZE_M\"], global_num_experts, expert_map\n )\n\n invoke_fused_moe_kernel(\n hidden_states,\n w1,\n intermediate_cache1,\n a1q_scale,\n self.w1_scale,\n self.w1_zp,\n None, # topk_weights\n sorted_token_ids,\n expert_ids,\n num_tokens_post_padded,\n False, # mul_routed_weights\n top_k_num,\n config,\n compute_type=compute_type,\n use_fp8_w8a8=self.quant_config.use_fp8_w8a8,\n use_int8_w8a8=self.quant_config.use_int8_w8a8,\n use_int8_w8a16=self.quant_config.use_int8_w8a16,\n use_int4_w4a16=self.quant_config.use_int4_w4a16,\n per_channel_quant=self.per_act_token_quant,\n block_shape=self.block_shape,\n B_bias=self.w1_bias,\n )\n\n self.activation(\n activation, intermediate_cache2, intermediate_cache1.view(-1, N)\n )\n\n a2q_scale: torch.Tensor | None = None\n\n qintermediate_cache2, a2q_scale = moe_kernel_quantize_input(\n intermediate_cache2,\n a2_scale,\n self.quant_dtype,\n self.per_act_token_quant,\n self.block_shape,\n )\n\n invoke_fused_moe_kernel(\n qintermediate_cache2,\n w2,\n intermediate_cache3,\n a2q_scale,\n self.w2_scale,\n self.w2_zp,\n topk_weights,\n sorted_token_ids,\n expert_ids,\n num_tokens_post_padded,\n not apply_router_weight_on_input,\n 1,\n config,\n compute_type=compute_type,\n use_fp8_w8a8=self.quant_config.use_fp8_w8a8,\n use_int8_w8a8=self.quant_config.use_int8_w8a8,\n use_int8_w8a16=self.quant_config.use_int8_w8a16,\n use_int4_w4a16=self.quant_config.use_int4_w4a16,\n per_channel_quant=self.per_act_token_quant,\n block_shape=self.block_shape,\n B_bias=self.w2_bias,\n )\n\n # separate function is required for MoE + LoRA\n self.moe_sum(intermediate_cache3, output)\n\n def moe_sum(self, input: torch.Tensor, output: torch.Tensor) -> None:\n ops.moe_sum(input, output)\n\n\ndef modular_triton_fused_moe(\n quant_config: FusedMoEQuantConfig, shared_experts: torch.nn.Module | None = None\n) -> mk.FusedMoEModularKernel:\n return mk.FusedMoEModularKernel(\n MoEPrepareAndFinalizeNoEP(),\n TritonExperts(quant_config),\n shared_experts,\n )\n"},"after_code":{"kind":"string","value":"# SPDX-License-Identifier: Apache-2.0\n# SPDX-FileCopyrightText: Copyright contributors to the vLLM project\n\"\"\"Fused MoE Triton kernels.\"\"\"\n\nimport functools\nimport json\nimport os\nfrom collections.abc import Callable\nfrom typing import Any\n\nimport torch\nimport torch.nn.functional as F\n\nimport vllm.envs as envs\nimport vllm.model_executor.layers.fused_moe.modular_kernel as mk\nfrom vllm import _custom_ops as ops\nfrom vllm._aiter_ops import rocm_aiter_ops\nfrom vllm.logger import init_logger\nfrom vllm.model_executor.layers.batch_invariant import (\n vllm_is_batch_invariant,\n)\nfrom vllm.model_executor.layers.fused_moe.config import (\n FUSED_MOE_UNQUANTIZED_CONFIG,\n FusedMoEQuantConfig,\n _get_config_dtype_str,\n)\nfrom vllm.model_executor.layers.fused_moe.cutlass_moe import (\n _valid_cutlass_block_scaled_grouped_gemm,\n run_cutlass_block_scaled_fused_experts,\n)\nfrom vllm.model_executor.layers.fused_moe.deep_gemm_moe import (\n _valid_deep_gemm,\n deep_gemm_moe_fp8,\n)\nfrom vllm.model_executor.layers.fused_moe.moe_align_block_size import (\n moe_align_block_size,\n)\nfrom vllm.model_executor.layers.fused_moe.prepare_finalize import (\n MoEPrepareAndFinalizeNoEP,\n)\nfrom vllm.model_executor.layers.fused_moe.topk_weight_and_reduce import (\n TopKWeightAndReduceNoOP,\n)\nfrom vllm.model_executor.layers.fused_moe.utils import (\n _resize_cache,\n activation_without_mul,\n disable_inplace,\n moe_kernel_quantize_input,\n)\nfrom vllm.model_executor.layers.quantization.utils.mxfp4_utils import dequant_mxfp4\nfrom vllm.model_executor.layers.quantization.utils.mxfp6_utils import dequant_mxfp6\nfrom vllm.model_executor.layers.quantization.utils.ocp_mx_utils import OCP_MX_Scheme\nfrom vllm.model_executor.utils import maybe_disable_graph_partition\nfrom vllm.platforms import current_platform\nfrom vllm.triton_utils import tl, triton\nfrom vllm.utils.deep_gemm import is_deep_gemm_e8m0_used\nfrom vllm.utils.torch_utils import direct_register_custom_op, is_torch_equal_or_newer\n\nlogger = init_logger(__name__)\n\n\n@triton.jit\ndef write_zeros_to_output(\n c_ptr,\n stride_cm,\n stride_cn,\n pid_n,\n N,\n offs_token,\n token_mask,\n BLOCK_SIZE_M,\n BLOCK_SIZE_N,\n compute_type,\n):\n accumulator = tl.zeros((BLOCK_SIZE_M, BLOCK_SIZE_N), dtype=compute_type)\n offs_cn = pid_n * BLOCK_SIZE_N + tl.arange(0, BLOCK_SIZE_N)\n c_ptrs = c_ptr + stride_cm * offs_token[:, None] + stride_cn * offs_cn[None, :]\n c_mask = token_mask[:, None] & (offs_cn[None, :] < N)\n tl.store(c_ptrs, accumulator, mask=c_mask)\n\n\n@triton.jit\ndef fused_moe_kernel_gptq_awq(\n # Pointers to matrices\n a_ptr,\n b_ptr,\n c_ptr,\n b_scale_ptr,\n b_zp_ptr,\n topk_weights_ptr,\n sorted_token_ids_ptr,\n expert_ids_ptr,\n num_tokens_post_padded_ptr,\n # Matrix dimensions\n N: tl.constexpr,\n K: tl.constexpr,\n EM,\n num_valid_tokens,\n # The stride variables represent how much to increase the ptr by when\n # moving by 1 element in a particular dimension. E.g. `stride_am` is\n # how much to increase `a_ptr` by to get the element one row down\n # (A has M rows).\n stride_am,\n stride_ak,\n stride_be,\n stride_bk,\n stride_bn,\n stride_cm,\n stride_cn,\n stride_bse,\n stride_bsk,\n stride_bsn,\n stride_bze,\n stride_bzk,\n stride_bzn,\n block_k_diviable: tl.constexpr,\n group_size: tl.constexpr,\n # Meta-parameters\n BLOCK_SIZE_M: tl.constexpr,\n BLOCK_SIZE_N: tl.constexpr,\n BLOCK_SIZE_K: tl.constexpr,\n GROUP_SIZE_M: tl.constexpr,\n SPLIT_K: tl.constexpr,\n MUL_ROUTED_WEIGHT: tl.constexpr,\n top_k: tl.constexpr,\n compute_type: tl.constexpr,\n has_zp: tl.constexpr,\n use_int4_w4a16: tl.constexpr,\n use_int8_w8a16: tl.constexpr,\n):\n \"\"\"\n Implements the fused computation for a Mixture of Experts (MOE) using\n token and expert matrices.\n\n Key Parameters:\n - A: The input tensor representing tokens with shape (*, K), where '*' can\n be any shape representing batches and K is the feature dimension of\n each token.\n - B: The stacked MOE weight tensor with shape (E, N, K), where E is\n the number of experts, K is the input feature dimension, and N is\n the output feature dimension.\n - C: The output cache tensor with shape (M, topk, N), where M is the\n total number of tokens post padding, topk is the number of times\n each token is repeated, and N is the output feature dimension.\n - sorted_token_ids: A tensor containing the sorted indices of tokens,\n repeated topk times and arranged by the expert index they are\n assigned to.\n - expert_ids: A tensor containing the indices of the expert for each\n block. It determines which expert matrix from B should be used for\n each block in A.\n This kernel performs the multiplication of a token by its corresponding\n expert matrix as determined by `expert_ids`. The sorting of\n `sorted_token_ids` by expert index and padding ensures divisibility by\n BLOCK_SIZE_M, which is necessary to maintain consistency in block matrix\n multiplication across different blocks processed by the same expert.\n \"\"\"\n # -----------------------------------------------------------\n # Map program ids `pid` to the block of C it should compute.\n # This is done in a grouped ordering to promote L2 data reuse.\n pid = tl.program_id(axis=0)\n num_pid_m = tl.cdiv(EM, BLOCK_SIZE_M)\n num_pid_n = tl.cdiv(N, BLOCK_SIZE_N)\n num_pid_in_group = GROUP_SIZE_M * num_pid_n\n group_id = pid // num_pid_in_group\n first_pid_m = group_id * GROUP_SIZE_M\n group_size_m = min(num_pid_m - first_pid_m, GROUP_SIZE_M)\n pid_m = first_pid_m + ((pid % num_pid_in_group) % group_size_m)\n pid_n = (pid % num_pid_in_group) // group_size_m\n\n # ----------------------------------------------------------\n # Create pointers for the first blocks of A and B.\n # We will advance this pointer as we move in the K direction\n # and accumulate\n # `a_ptrs` is a block of [BLOCK_SIZE_M, BLOCK_SIZE_K] pointers\n # `b_ptrs` is a block of [BLOCK_SIZE_K, BLOCK_SIZE_N] pointers\n num_tokens_post_padded = tl.load(num_tokens_post_padded_ptr)\n if pid_m * BLOCK_SIZE_M >= num_tokens_post_padded:\n return\n offs_token_id = pid_m * BLOCK_SIZE_M + tl.arange(0, BLOCK_SIZE_M).to(tl.int64)\n offs_token = tl.load(sorted_token_ids_ptr + offs_token_id)\n token_mask = offs_token < num_valid_tokens\n\n off_experts = tl.load(expert_ids_ptr + pid_m).to(tl.int64)\n if off_experts == -1:\n # -----------------------------------------------------------\n # Write back zeros to the output when the expert is not\n # in the current expert parallel rank.\n write_zeros_to_output(\n c_ptr,\n stride_cm,\n stride_cn,\n pid_n,\n N,\n offs_token,\n token_mask,\n BLOCK_SIZE_M,\n BLOCK_SIZE_N,\n compute_type,\n )\n return\n\n offs_bn = (pid_n * BLOCK_SIZE_N + tl.arange(0, BLOCK_SIZE_N).to(tl.int64)) % N\n offs_k = tl.arange(0, BLOCK_SIZE_K)\n a_ptrs = a_ptr + (\n offs_token[:, None] // top_k * stride_am + offs_k[None, :] * stride_ak\n )\n\n if use_int4_w4a16:\n b_ptrs = (\n b_ptr\n + off_experts * stride_be\n + (offs_k[:, None] // 2) * stride_bk\n + offs_bn[None, :] * stride_bn\n )\n b_shifter = (offs_k[:, None] % 2) * 4\n elif use_int8_w8a16:\n b_ptrs = (\n b_ptr\n + off_experts * stride_be\n + offs_k[:, None] * stride_bk\n + offs_bn[None, :] * stride_bn\n )\n\n if not has_zp and use_int4_w4a16:\n b_zp_num = 8\n if not has_zp and use_int8_w8a16:\n b_zp_num = 128\n elif has_zp and use_int4_w4a16:\n b_zp_shifter = (offs_bn[None, :] % 2) * 4\n\n # -----------------------------------------------------------\n # Iterate to compute a block of the C matrix.\n # We accumulate into a `[BLOCK_SIZE_M, BLOCK_SIZE_N]` block\n # of fp32 values for higher accuracy.\n # `accumulator` will be converted back to fp16 after the loop.\n accumulator = tl.zeros((BLOCK_SIZE_M, BLOCK_SIZE_N), dtype=tl.float32)\n for k in range(0, tl.cdiv(K, BLOCK_SIZE_K)):\n # Load the next block of A and B, generate a mask by checking the\n # K dimension.\n\n if not block_k_diviable:\n k_mask = offs_k[:, None] < K - k * BLOCK_SIZE_K\n k_other = 0.0\n else:\n k_mask = None\n k_other = None\n\n a = tl.load(\n a_ptrs,\n mask=token_mask[:, None] & (offs_k[None, :] < K - k * BLOCK_SIZE_K),\n other=0.0,\n )\n b = tl.load(b_ptrs)\n if use_int4_w4a16:\n b = (b >> b_shifter) & 0xF\n\n b_scale_ptrs = (\n b_scale_ptr\n + off_experts * stride_bse\n + offs_bn[None, :] * stride_bsn\n + ((offs_k[:, None] + BLOCK_SIZE_K * k) // group_size) * stride_bsk\n )\n b_scale = tl.load(b_scale_ptrs, mask=k_mask, other=k_other)\n b_scale = b_scale.to(tl.float32)\n\n if has_zp and use_int4_w4a16:\n offs_k_true = (offs_k[:, None] + BLOCK_SIZE_K * k) // group_size\n b_zp_ptrs = (\n b_zp_ptr\n + off_experts * stride_bze\n + (offs_bn[None, :] // 2) * stride_bzn\n + offs_k_true * stride_bzk\n )\n b_zp = tl.load(b_zp_ptrs, mask=k_mask, other=k_other)\n b_zp = (b_zp >> b_zp_shifter) & 0xF\n b_zp = b_zp.to(tl.float32)\n elif has_zp and use_int8_w8a16:\n offs_k_true = (offs_k[:, None] + BLOCK_SIZE_K * k) // group_size\n b_zp_ptrs = (\n b_zp_ptr\n + off_experts * stride_bze\n + offs_bn[None, :] * stride_bzn\n + offs_k_true * stride_bzk\n )\n b_zp = tl.load(b_zp_ptrs, mask=k_mask, other=k_other)\n b_zp = b_zp.to(tl.float32)\n\n # We accumulate along the K dimension.\n if has_zp:\n b = ((b.to(tl.float32) - b_zp) * b_scale).to(compute_type)\n else:\n b = ((b.to(tl.float32) - b_zp_num) * b_scale).to(compute_type)\n accumulator = tl.dot(a, b, acc=accumulator)\n\n # Advance the ptrs to the next K block.\n a_ptrs += BLOCK_SIZE_K * stride_ak\n if use_int4_w4a16:\n b_ptrs += (BLOCK_SIZE_K // 2) * stride_bk\n else:\n b_ptrs += BLOCK_SIZE_K * stride_bk\n\n if MUL_ROUTED_WEIGHT:\n moe_weight = tl.load(topk_weights_ptr + offs_token, mask=token_mask, other=0)\n accumulator = accumulator * moe_weight[:, None]\n\n accumulator = accumulator.to(compute_type)\n # -----------------------------------------------------------\n # Write back the block of the output\n offs_cn = pid_n * BLOCK_SIZE_N + tl.arange(0, BLOCK_SIZE_N)\n c_ptrs = c_ptr + stride_cm * offs_token[:, None] + stride_cn * offs_cn[None, :]\n c_mask = token_mask[:, None] & (offs_cn[None, :] < N)\n tl.store(c_ptrs, accumulator, mask=c_mask)\n\n\n@triton.jit\ndef fused_moe_kernel(\n # Pointers to matrices\n a_ptr,\n b_ptr,\n c_ptr,\n b_bias_ptr,\n a_scale_ptr,\n b_scale_ptr,\n topk_weights_ptr,\n sorted_token_ids_ptr,\n expert_ids_ptr,\n num_tokens_post_padded_ptr,\n # Matrix dimensions\n N,\n K,\n EM,\n num_valid_tokens,\n # The stride variables represent how much to increase the ptr by when\n # moving by 1 element in a particular dimension. E.g. `stride_am` is\n # how much to increase `a_ptr` by to get the element one row down\n # (A has M rows).\n stride_am,\n stride_ak,\n stride_be,\n stride_bk,\n stride_bn,\n stride_cm,\n stride_cn,\n stride_asm,\n stride_ask,\n stride_bse,\n stride_bsk,\n stride_bsn,\n stride_bbe, # bias expert stride\n stride_bbn, # bias N stride\n # Block size for block-wise quantization\n group_n: tl.constexpr,\n group_k: tl.constexpr,\n # Meta-parameters\n BLOCK_SIZE_M: tl.constexpr,\n BLOCK_SIZE_N: tl.constexpr,\n BLOCK_SIZE_K: tl.constexpr,\n GROUP_SIZE_M: tl.constexpr,\n SPLIT_K: tl.constexpr,\n MUL_ROUTED_WEIGHT: tl.constexpr,\n top_k: tl.constexpr,\n compute_type: tl.constexpr,\n use_fp8_w8a8: tl.constexpr,\n use_int8_w8a8: tl.constexpr,\n use_int8_w8a16: tl.constexpr,\n per_channel_quant: tl.constexpr,\n HAS_BIAS: tl.constexpr,\n):\n \"\"\"\n Implements the fused computation for a Mixture of Experts (MOE) using\n token and expert matrices.\n\n Key Parameters:\n - A: The input tensor representing tokens with shape (*, K), where '*' can\n be any shape representing batches and K is the feature dimension of\n each token.\n - B: The stacked MOE weight tensor with shape (E, N, K), where E is\n the number of experts, K is the input feature dimension, and N is\n the output feature dimension.\n - C: The output cache tensor with shape (M, topk, N), where M is the\n total number of tokens post padding, topk is the number of times\n each token is repeated, and N is the output feature dimension.\n - sorted_token_ids: A tensor containing the sorted indices of tokens,\n repeated topk times and arranged by the expert index they are\n assigned to.\n - expert_ids: A tensor containing the indices of the expert for each\n block. It determines which expert matrix from B should be used for\n each block in A.\n This kernel performs the multiplication of a token by its corresponding\n expert matrix as determined by `expert_ids`. The sorting of\n `sorted_token_ids` by expert index and padding ensures divisibility by\n BLOCK_SIZE_M, which is necessary to maintain consistency in block matrix\n multiplication across different blocks processed by the same expert.\n \"\"\"\n # -----------------------------------------------------------\n # Map program ids `pid` to the block of C it should compute.\n # This is done in a grouped ordering to promote L2 data reuse.\n pid = tl.program_id(axis=0)\n num_pid_m = tl.cdiv(EM, BLOCK_SIZE_M)\n num_pid_n = tl.cdiv(N, BLOCK_SIZE_N)\n num_pid_in_group = GROUP_SIZE_M * num_pid_n\n group_id = pid // num_pid_in_group\n first_pid_m = group_id * GROUP_SIZE_M\n group_size_m = min(num_pid_m - first_pid_m, GROUP_SIZE_M)\n pid_m = first_pid_m + ((pid % num_pid_in_group) % group_size_m)\n pid_n = (pid % num_pid_in_group) // group_size_m\n\n # ----------------------------------------------------------\n # Create pointers for the first blocks of A and B.\n # We will advance this pointer as we move in the K direction\n # and accumulate\n # `a_ptrs` is a block of [BLOCK_SIZE_M, BLOCK_SIZE_K] pointers\n # `b_ptrs` is a block of [BLOCK_SIZE_K, BLOCK_SIZE_N] pointers\n num_tokens_post_padded = tl.load(num_tokens_post_padded_ptr)\n if pid_m * BLOCK_SIZE_M >= num_tokens_post_padded:\n return\n offs_token_id = pid_m * BLOCK_SIZE_M + tl.arange(0, BLOCK_SIZE_M).to(tl.int64)\n offs_token = tl.load(sorted_token_ids_ptr + offs_token_id)\n token_mask = offs_token < num_valid_tokens\n\n off_experts = tl.load(expert_ids_ptr + pid_m).to(tl.int64)\n if off_experts == -1:\n # -----------------------------------------------------------\n # Write back zeros to the output when the expert is not\n # in the current expert parallel rank.\n write_zeros_to_output(\n c_ptr,\n stride_cm,\n stride_cn,\n pid_n,\n N,\n offs_token,\n token_mask,\n BLOCK_SIZE_M,\n BLOCK_SIZE_N,\n compute_type,\n )\n return\n\n offs_bn = (pid_n * BLOCK_SIZE_N + tl.arange(0, BLOCK_SIZE_N).to(tl.int64)) % N\n offs_k = tl.arange(0, BLOCK_SIZE_K)\n a_ptrs = a_ptr + (\n offs_token[:, None] // top_k * stride_am + offs_k[None, :] * stride_ak\n )\n\n b_ptrs = (\n b_ptr\n + off_experts * stride_be\n + (offs_k[:, None] * stride_bk + offs_bn[None, :] * stride_bn)\n )\n if use_int8_w8a16:\n b_scale_ptrs = (\n b_scale_ptr + off_experts * stride_bse + offs_bn[None, :] * stride_bsn\n )\n b_scale = tl.load(b_scale_ptrs)\n\n if use_fp8_w8a8 or use_int8_w8a8:\n # block-wise\n if group_k > 0 and group_n > 0:\n a_scale_ptrs = a_scale_ptr + (offs_token // top_k) * stride_asm\n offs_bsn = offs_bn // group_n\n b_scale_ptrs = (\n b_scale_ptr + off_experts * stride_bse + offs_bsn * stride_bsn\n )\n # channel-wise\n elif per_channel_quant:\n b_scale_ptrs = (\n b_scale_ptr + off_experts * stride_bse + offs_bn[None, :] * stride_bsn\n )\n b_scale = tl.load(b_scale_ptrs)\n # Load per-token scale for activations\n a_scale_ptrs = a_scale_ptr + (offs_token // top_k) * stride_asm\n a_scale = tl.load(a_scale_ptrs, mask=token_mask, other=0.0)[:, None]\n # tensor-wise\n else:\n a_scale = tl.load(a_scale_ptr)\n b_scale = tl.load(b_scale_ptr + off_experts)\n if HAS_BIAS:\n # bias shape: [num_experts, N]\n bias_ptrs = b_bias_ptr + off_experts * stride_bbe + offs_bn * stride_bbn\n bias = tl.load(bias_ptrs, mask=(offs_bn < N), other=0.0)\n # -----------------------------------------------------------\n # Iterate to compute a block of the C matrix.\n # We accumulate into a `[BLOCK_SIZE_M, BLOCK_SIZE_N]` block\n # of fp32 values for higher accuracy.\n # `accumulator` will be converted back to fp16 after the loop.\n accumulator = tl.zeros((BLOCK_SIZE_M, BLOCK_SIZE_N), dtype=tl.float32)\n for k in range(0, tl.cdiv(K, BLOCK_SIZE_K)):\n # Load the next block of A and B, generate a mask by checking the\n # K dimension.\n a = tl.load(\n a_ptrs,\n mask=token_mask[:, None] & (offs_k[None, :] < K - k * BLOCK_SIZE_K),\n other=0.0,\n )\n b = tl.load(b_ptrs, mask=offs_k[:, None] < K - k * BLOCK_SIZE_K, other=0.0)\n # We accumulate along the K dimension.\n if use_int8_w8a16:\n accumulator = tl.dot(a, b.to(compute_type), acc=accumulator)\n elif use_fp8_w8a8 or use_int8_w8a8:\n if group_k > 0 and group_n > 0:\n k_start = k * BLOCK_SIZE_K\n offs_ks = k_start // group_k\n a_scale = tl.load(\n a_scale_ptrs + offs_ks * stride_ask, mask=token_mask, other=0.0\n )\n b_scale = tl.load(b_scale_ptrs + offs_ks * stride_bsk)\n\n accumulator += tl.dot(a, b) * a_scale[:, None] * b_scale[None, :]\n else:\n if use_fp8_w8a8:\n # acc used to enable fp8_fast_accum\n accumulator = tl.dot(a, b, acc=accumulator)\n else:\n accumulator += tl.dot(a, b)\n else:\n accumulator += tl.dot(a, b)\n # Advance the ptrs to the next K block.\n a_ptrs += BLOCK_SIZE_K * stride_ak\n b_ptrs += BLOCK_SIZE_K * stride_bk\n if HAS_BIAS:\n accumulator = accumulator + bias[None, :]\n if MUL_ROUTED_WEIGHT:\n moe_weight = tl.load(topk_weights_ptr + offs_token, mask=token_mask, other=0)\n accumulator = accumulator * moe_weight[:, None]\n if use_int8_w8a16:\n accumulator = (accumulator * b_scale).to(compute_type)\n elif use_fp8_w8a8 or use_int8_w8a8:\n if group_k > 0 and group_n > 0:\n accumulator = accumulator.to(compute_type)\n else:\n accumulator = (accumulator * a_scale * b_scale).to(compute_type)\n else:\n accumulator = accumulator.to(compute_type)\n\n # -----------------------------------------------------------\n # Write back the block of the output\n offs_cn = pid_n * BLOCK_SIZE_N + tl.arange(0, BLOCK_SIZE_N)\n c_ptrs = c_ptr + stride_cm * offs_token[:, None] + stride_cn * offs_cn[None, :]\n c_mask = token_mask[:, None] & (offs_cn[None, :] < N)\n tl.store(c_ptrs, accumulator, mask=c_mask)\n\n\ndef invoke_fused_moe_kernel(\n A: torch.Tensor,\n B: torch.Tensor,\n C: torch.Tensor,\n A_scale: torch.Tensor | None,\n B_scale: torch.Tensor | None,\n B_zp: torch.Tensor | None,\n topk_weights: torch.Tensor | None,\n sorted_token_ids: torch.Tensor,\n expert_ids: torch.Tensor,\n num_tokens_post_padded: torch.Tensor,\n mul_routed_weight: bool,\n top_k: int,\n config: dict[str, Any],\n compute_type: tl.dtype,\n use_fp8_w8a8: bool,\n use_int8_w8a8: bool,\n use_int8_w8a16: bool,\n use_int4_w4a16: bool,\n per_channel_quant: bool,\n block_shape: list[int] | None = None,\n B_bias: torch.Tensor | None = None,\n) -> None:\n assert topk_weights is not None or not mul_routed_weight\n assert topk_weights is None or topk_weights.stride(1) == 1\n assert sorted_token_ids.stride(0) == 1\n\n if use_fp8_w8a8 or use_int8_w8a8:\n assert B_scale is not None\n assert block_shape is None or triton.cdiv(\n B.size(-2), block_shape[0]\n ) == B_scale.size(-2)\n assert block_shape is None or triton.cdiv(\n B.size(-1), block_shape[1]\n ) == B_scale.size(-1)\n\n elif use_int8_w8a16 or use_int4_w4a16:\n assert B_scale is not None\n assert block_shape is None or block_shape[0] == 0\n else:\n assert A_scale is None\n assert B_scale is None\n\n M = A.size(0)\n num_tokens = M * top_k\n\n EM = sorted_token_ids.size(0)\n if A.size(0) < config[\"BLOCK_SIZE_M\"]:\n # optimize for small batch_size.\n # We assume that top_ids of each token is unique,\n # so num_valid_experts <= batch_size <= BLOCK_SIZE_M,\n # and we can skip some invalid blocks.\n EM = min(sorted_token_ids.size(0), A.size(0) * top_k * config[\"BLOCK_SIZE_M\"])\n grid = lambda META: (\n triton.cdiv(EM, META[\"BLOCK_SIZE_M\"])\n * triton.cdiv(B.size(1), META[\"BLOCK_SIZE_N\"]),\n )\n HAS_BIAS = B_bias is not None\n if (\n (use_int8_w8a16 or use_int4_w4a16)\n and block_shape is not None\n and block_shape[1] > 0\n ):\n assert B_scale is not None and B_scale.ndim == 3\n assert B_zp is None or B_zp.ndim == 3\n\n use_moe_wna16_cuda = should_moe_wna16_use_cuda(\n num_valid_tokens=num_tokens,\n group_size=block_shape[1],\n num_experts=B.size(0),\n bit=4 if use_int4_w4a16 else 8,\n )\n config = config.copy()\n config.update(\n get_moe_wna16_block_config(\n config=config,\n use_moe_wna16_cuda=use_moe_wna16_cuda,\n num_valid_tokens=num_tokens,\n size_k=A.size(1),\n size_n=B.size(1),\n num_experts=B.size(1),\n group_size=block_shape[1],\n real_top_k=top_k,\n block_size_m=config[\"BLOCK_SIZE_M\"],\n )\n )\n\n if use_moe_wna16_cuda:\n bit = 4 if use_int4_w4a16 else 8\n ops.moe_wna16_gemm(\n A,\n C,\n B,\n B_scale,\n B_zp,\n topk_weights if mul_routed_weight else None,\n sorted_token_ids,\n expert_ids,\n num_tokens_post_padded,\n top_k,\n config[\"BLOCK_SIZE_M\"],\n config[\"BLOCK_SIZE_N\"],\n config[\"BLOCK_SIZE_K\"],\n bit,\n )\n return\n fused_moe_kernel_gptq_awq[grid](\n A,\n B,\n C,\n B_scale,\n B_zp,\n topk_weights,\n sorted_token_ids,\n expert_ids,\n num_tokens_post_padded,\n B.size(1),\n A.size(1),\n EM,\n num_tokens,\n A.stride(0),\n A.stride(1),\n B.stride(0),\n B.stride(2),\n B.stride(1),\n C.stride(1),\n C.stride(2),\n B_scale.stride(0),\n B_scale.stride(2),\n B_scale.stride(1),\n B_zp.stride(0) if B_zp is not None else 0,\n B_zp.stride(2) if B_zp is not None else 0,\n B_zp.stride(1) if B_zp is not None else 0,\n block_k_diviable=A.size(1) % config[\"BLOCK_SIZE_K\"] == 0,\n group_size=block_shape[1],\n MUL_ROUTED_WEIGHT=mul_routed_weight,\n top_k=top_k,\n compute_type=compute_type,\n has_zp=B_zp is not None,\n use_int4_w4a16=use_int4_w4a16,\n use_int8_w8a16=use_int8_w8a16,\n **config,\n )\n else:\n config = config.copy()\n config[\"SPLIT_K\"] = 1\n BLOCK_SIZE_K = config.pop(\"BLOCK_SIZE_K\")\n if block_shape is not None:\n BLOCK_SIZE_K = min(BLOCK_SIZE_K, min(block_shape[0], block_shape[1]))\n fused_moe_kernel[grid](\n A,\n B,\n C,\n B_bias,\n A_scale,\n B_scale,\n topk_weights,\n sorted_token_ids,\n expert_ids,\n num_tokens_post_padded,\n B.size(1),\n B.size(2),\n EM,\n num_tokens,\n A.stride(0),\n A.stride(1),\n B.stride(0),\n B.stride(2),\n B.stride(1),\n C.stride(1),\n C.stride(2),\n A_scale.stride(0) if A_scale is not None and A_scale.ndim == 2 else 0,\n A_scale.stride(1) if A_scale is not None and A_scale.ndim == 2 else 0,\n B_scale.stride(0) if B_scale is not None and B_scale.ndim >= 2 else 0,\n B_scale.stride(2) if B_scale is not None and B_scale.ndim == 3 else 0,\n B_scale.stride(1) if B_scale is not None and B_scale.ndim >= 2 else 0,\n B_bias.stride(0) if B_bias is not None else 0,\n B_bias.stride(1) if B_bias is not None else 0,\n 0 if block_shape is None else block_shape[0],\n 0 if block_shape is None else block_shape[1],\n MUL_ROUTED_WEIGHT=mul_routed_weight,\n top_k=top_k,\n compute_type=compute_type,\n use_fp8_w8a8=use_fp8_w8a8,\n use_int8_w8a8=use_int8_w8a8,\n use_int8_w8a16=use_int8_w8a16,\n per_channel_quant=per_channel_quant,\n HAS_BIAS=HAS_BIAS,\n BLOCK_SIZE_K=BLOCK_SIZE_K,\n **config,\n )\n\n\n@triton.jit\ndef compute_identity_kernel(\n top_k: int,\n hidden_states_ptr: tl.tensor,\n expert_scales_ptr: tl.tensor,\n num_tokens: int,\n output_ptr: tl.tensor,\n hidden_dim: int,\n scales_stride: int,\n BLOCK_SIZE: tl.constexpr,\n) -> None:\n pid = tl.program_id(0)\n\n batch_id = pid // (hidden_dim // BLOCK_SIZE)\n dim_offset = pid % (hidden_dim // BLOCK_SIZE) * BLOCK_SIZE\n\n if batch_id >= num_tokens or dim_offset >= hidden_dim:\n return\n\n h = tl.load(\n hidden_states_ptr\n + batch_id * hidden_dim\n + dim_offset\n + tl.arange(0, BLOCK_SIZE),\n mask=(dim_offset + tl.arange(0, BLOCK_SIZE)) < hidden_dim,\n )\n\n result = tl.zeros([BLOCK_SIZE], dtype=tl.float32)\n for i in range(top_k):\n scale = tl.load(expert_scales_ptr + batch_id * scales_stride + i)\n result += h * scale\n\n tl.store(\n output_ptr + batch_id * hidden_dim + dim_offset + tl.arange(0, BLOCK_SIZE),\n result,\n mask=(dim_offset + tl.arange(0, BLOCK_SIZE)) < hidden_dim,\n )\n\n\ndef zero_experts_compute_triton(\n expert_indices: torch.Tensor,\n expert_scales: torch.Tensor,\n num_experts: int,\n zero_expert_type: str,\n hidden_states: torch.Tensor,\n) -> torch.Tensor:\n N = expert_indices.numel()\n top_k = expert_indices.size(-1)\n grid = lambda meta: (triton.cdiv(N, meta[\"BLOCK_SIZE\"]),)\n\n if zero_expert_type == \"identity\":\n zero_expert_mask = expert_indices < num_experts\n zero_expert_scales = expert_scales.clone()\n zero_expert_scales[zero_expert_mask] = 0.0\n\n normal_expert_mask = expert_indices >= num_experts\n expert_indices[normal_expert_mask] = 0\n expert_scales[normal_expert_mask] = 0.0\n\n output = torch.zeros_like(hidden_states).to(hidden_states.device)\n hidden_dim = hidden_states.size(-1)\n num_tokens = hidden_states.size(0)\n\n grid = lambda meta: (num_tokens * (hidden_dim // meta[\"BLOCK_SIZE\"]),)\n compute_identity_kernel[grid](\n top_k,\n hidden_states,\n zero_expert_scales,\n num_tokens,\n output,\n hidden_dim,\n zero_expert_scales.stride(0),\n BLOCK_SIZE=256,\n )\n\n return output\n\n\n# Adapted from: https://github.com/sgl-project/sglang/pull/2628\ndef get_config_file_name(\n E: int, N: int, dtype: str | None, block_shape: list[int] | None = None\n) -> str:\n device_name = current_platform.get_device_name().replace(\" \", \"_\")\n # Set device_name to H200 if a device from the H200 family is detected\n if \"H200\" in device_name.split(\"_\"):\n device_name = \"NVIDIA_H200\"\n dtype_selector = \"\" if not dtype else f\",dtype={dtype}\"\n block_shape_selector = (\n \"\" if not block_shape or not all(block_shape) else f\",block_shape={block_shape}\"\n ).replace(\" \", \"\")\n return f\"E={E},N={N},device_name={device_name}{dtype_selector}{block_shape_selector}.json\" # noqa: E501\n\n\n# Adapted from: https://github.com/sgl-project/sglang/pull/2628\n@functools.lru_cache\ndef get_moe_configs(\n E: int,\n N: int,\n dtype: str | None,\n block_n: int | None = None,\n block_k: int | None = None,\n) -> dict[int, Any] | None:\n \"\"\"\n Return optimized configurations for the fused MoE kernel.\n\n The return value will be a dictionary that maps an irregular grid of\n batch sizes to configurations of the fused_moe kernel. To evaluate the\n kernel on a given batch size bs, the closest batch size in the grid should\n be picked and the associated configuration chosen to invoke the kernel.\n \"\"\"\n\n # Avoid optimizing for the batch invariant case. Use default config\n if vllm_is_batch_invariant():\n return None\n\n # First look up if an optimized configuration is available in the configs\n # directory\n block_shape = [block_n, block_k] if block_n and block_k else None\n json_file_name = get_config_file_name(E, N, dtype, block_shape)\n\n config_file_paths = []\n\n # note that we prioritize user defined config\n user_defined_config_folder = envs.VLLM_TUNED_CONFIG_FOLDER\n if user_defined_config_folder is not None:\n user_defined_config_file_path = os.path.join(\n user_defined_config_folder, json_file_name\n )\n config_file_paths.append(user_defined_config_file_path)\n\n default_config_file_path = os.path.join(\n os.path.dirname(os.path.realpath(__file__)), \"configs\", json_file_name\n )\n config_file_paths.append(default_config_file_path)\n\n for config_file_path in config_file_paths:\n if os.path.exists(config_file_path):\n with open(config_file_path) as f:\n logger.info_once(\n \"Using configuration from %s for MoE layer.\",\n config_file_path,\n scope=\"global\",\n )\n # If a configuration has been found, return it\n tuned_config = json.load(f)\n # Delete triton_version from tuned_config\n tuned_config.pop(\"triton_version\", None)\n return {int(key): val for key, val in tuned_config.items()}\n\n # If no optimized configuration is available, we will use the default\n # configuration\n logger.warning(\n (\n \"Using default MoE config. Performance might be sub-optimal! \"\n \"Config file not found at %s\"\n ),\n config_file_paths,\n )\n return None\n\n\ndef get_moe_wna16_block_config(\n config: dict[str, int],\n use_moe_wna16_cuda: bool,\n num_valid_tokens: int,\n size_k: int,\n size_n: int,\n num_experts: int,\n group_size: int,\n real_top_k: int,\n block_size_m: int,\n):\n if \"BLOCK_SIZE_N\" in config and \"BLOCK_SIZE_K\" in config:\n # optimal block config is set\n return {}\n if not use_moe_wna16_cuda:\n # triton moe wna16 kernel\n if num_valid_tokens // real_top_k == 1:\n # if bs=1, use a smaller BLOCK_SIZE_N\n return {\"BLOCK_SIZE_N\": 32, \"BLOCK_SIZE_K\": 64}\n else:\n return {\"BLOCK_SIZE_N\": 64, \"BLOCK_SIZE_K\": 32}\n else:\n # cuda moe wna16 kernel\n # set default block_size 128, and increase them when num_blocks\n # is too large.\n block_size_n = 128\n block_size_k = 128\n if block_size_k <= group_size:\n block_size_k = group_size\n\n num_n_blocks = size_k // block_size_k\n num_k_blocks = size_n // block_size_k\n num_m_blocks = (\n num_valid_tokens + block_size_m - 1\n ) / block_size_m + num_experts\n if num_valid_tokens // real_top_k <= block_size_m:\n num_m_blocks = min(num_m_blocks, num_valid_tokens)\n num_blocks = num_m_blocks * num_n_blocks * num_k_blocks\n\n if size_k % 256 == 0 and num_blocks >= 256 and block_size_k < 256:\n block_size_k = 256\n num_blocks = num_blocks // (256 // block_size_k)\n\n if (\n num_m_blocks <= 16\n and size_k % (block_size_k * 2) == 0\n and size_k % (block_size_k * 2) == 0\n and block_size_k <= 512\n and num_blocks >= 512\n ):\n block_size_k = block_size_k * 2\n num_blocks = num_blocks // 2\n\n if num_blocks > 1024:\n block_size_n = 256\n num_n_blocks = num_n_blocks // 2\n num_blocks = num_blocks // 2\n\n if size_n <= 1024 and num_blocks >= 1024:\n # The kernel performance got much better with BLOCK_SIZE_N=1024\n # when num_blocks is large, event when N is small.\n # Not sure why, maybe it force the CUDA SM process only one block\n # at the same time.\n block_size_n = 1024\n\n return {\"BLOCK_SIZE_N\": block_size_n, \"BLOCK_SIZE_K\": block_size_k}\n\n\ndef should_moe_wna16_use_cuda(\n num_valid_tokens: int, group_size: int, num_experts: int, bit: int\n):\n return (\n current_platform.is_cuda()\n and bit == 4\n and group_size in [32, 64, 128]\n and num_valid_tokens / num_experts <= 6\n )\n\n\ndef get_default_config(\n M: int,\n E: int,\n N: int,\n K: int,\n topk: int,\n dtype: str | None,\n block_shape: list[int] | None = None,\n) -> dict[str, int]:\n if vllm_is_batch_invariant():\n config = {\n \"BLOCK_SIZE_M\": 64,\n \"BLOCK_SIZE_N\": 64,\n \"BLOCK_SIZE_K\": 32,\n \"GROUP_SIZE_M\": 8,\n \"SPLIT_K\": 1,\n }\n return config\n\n if dtype == \"fp8_w8a8\" and block_shape is not None:\n # Block-wise quant: BLOCK_SIZE_N must be divisible by block_shape[0]\n # BLOCK_SIZE_K must be divisible by block_shape[1]\n # num_stages=3 can cause triton.runtime.errors.OutOfResources\n # on ROCm, set it to 2 instead.\n config = {\n \"BLOCK_SIZE_M\": 64,\n \"BLOCK_SIZE_N\": block_shape[0],\n \"BLOCK_SIZE_K\": block_shape[1],\n \"GROUP_SIZE_M\": 32,\n \"SPLIT_K\": 1,\n \"num_warps\": 4,\n \"num_stages\": 3 if not current_platform.is_rocm() else 2,\n }\n elif dtype in [\"int4_w4a16\", \"int8_w8a16\"] and block_shape is not None:\n # moe wna16 kernels\n # only set BLOCK_SIZE_M\n # BLOCK_SIZE_N and BLOCK_SIZE_K would be set later\n bit = 4 if dtype == \"int4_w4a16\" else 8\n use_moe_wna16_cuda = should_moe_wna16_use_cuda(M * topk, block_shape[1], E, bit)\n if use_moe_wna16_cuda:\n config = {\"BLOCK_SIZE_M\": min(16, M), \"SPLIT_K\": 1}\n elif M <= 20:\n config = {\"BLOCK_SIZE_M\": 16, \"GROUP_SIZE_M\": 1, \"SPLIT_K\": 1}\n elif M <= 40:\n config = {\"BLOCK_SIZE_M\": 32, \"GROUP_SIZE_M\": 1, \"SPLIT_K\": 1}\n else:\n config = {\"BLOCK_SIZE_M\": 64, \"GROUP_SIZE_M\": 1, \"SPLIT_K\": 1}\n elif M <= E:\n config = {\n \"BLOCK_SIZE_M\": 16,\n \"BLOCK_SIZE_N\": 32,\n \"BLOCK_SIZE_K\": 64,\n \"GROUP_SIZE_M\": 1,\n \"SPLIT_K\": 1,\n }\n else:\n config = {\n \"BLOCK_SIZE_M\": 64,\n \"BLOCK_SIZE_N\": 64,\n \"BLOCK_SIZE_K\": 32,\n \"GROUP_SIZE_M\": 8,\n \"SPLIT_K\": 1,\n }\n return config\n\n\ndef try_get_optimal_moe_config(\n w1_shape: tuple[int, ...],\n w2_shape: tuple[int, ...],\n top_k: int,\n dtype: str | None,\n M: int,\n block_shape: list[int] | None = None,\n) -> dict[str, int]:\n from vllm.model_executor.layers.fused_moe import get_config\n\n override_config = get_config()\n if override_config:\n config = override_config\n else:\n # First try to load optimal config from the file\n E, _, N = w2_shape\n if dtype == \"int4_w4a16\":\n N = N * 2\n block_n = block_shape[0] if block_shape else 0\n block_k = block_shape[1] if block_shape else 0\n configs = get_moe_configs(E, N, dtype, block_n, block_k)\n\n if configs:\n # If an optimal configuration map has been found, look up the\n # optimal config\n config = configs[min(configs.keys(), key=lambda x: abs(x - M))]\n else:\n # Else use the default config\n config = get_default_config(M, E, N, w1_shape[2], top_k, dtype, block_shape)\n return config\n\n\ndef vllm_topk_softmax(\n topk_weights: torch.Tensor,\n topk_indices: torch.Tensor,\n token_expert_indices: torch.Tensor,\n gating_output: torch.Tensor,\n renormalize: bool,\n) -> tuple[torch.Tensor, ...]:\n ops.topk_softmax(\n topk_weights,\n topk_indices,\n token_expert_indices,\n gating_output,\n renormalize,\n )\n\n return topk_weights, topk_indices\n\n\ndef dispatch_topk_func(\n use_rocm_aiter: bool = False,\n) -> Callable[..., tuple[torch.Tensor, ...]]:\n if use_rocm_aiter:\n return rocm_aiter_ops.topk_softmax\n return vllm_topk_softmax\n\n\ndef fused_topk(\n hidden_states: torch.Tensor,\n gating_output: torch.Tensor,\n topk: int,\n renormalize: bool,\n indices_type: torch.dtype | None = None,\n) -> tuple[torch.Tensor, torch.Tensor, torch.Tensor]:\n assert hidden_states.size(0) == gating_output.size(0), \"Number of tokens mismatch\"\n\n M, _ = hidden_states.size()\n\n topk_weights = torch.empty(\n M, topk, dtype=torch.float32, device=hidden_states.device\n )\n topk_ids = torch.empty(\n M,\n topk,\n dtype=torch.int32 if indices_type is None else indices_type,\n device=hidden_states.device,\n )\n token_expert_indices = torch.empty(\n M, topk, dtype=torch.int32, device=hidden_states.device\n )\n\n topk_func = dispatch_topk_func(use_rocm_aiter=rocm_aiter_ops.is_fused_moe_enabled())\n topk_weights, topk_ids = topk_func(\n topk_weights, topk_ids, token_expert_indices, gating_output, renormalize\n )\n\n return topk_weights, topk_ids, token_expert_indices\n\n\ndef fused_topk_bias(\n hidden_states: torch.Tensor,\n gating_output: torch.Tensor,\n e_score_correction_bias: torch.Tensor,\n topk: int,\n renormalize: bool,\n):\n n_routed_experts = gating_output.shape[-1]\n scores = gating_output.softmax(dim=-1)\n scores_for_choice = scores.view(\n -1, n_routed_experts\n ) + e_score_correction_bias.unsqueeze(0)\n\n # For batch invariance, use sorted=True to ensure deterministic expert selection\n use_sorted = vllm_is_batch_invariant()\n topk_indices = torch.topk(scores_for_choice, k=topk, dim=-1, sorted=use_sorted)[1]\n topk_weights = scores.gather(1, topk_indices)\n if renormalize:\n topk_weights = topk_weights / topk_weights.sum(dim=-1, keepdim=True)\n return topk_weights.to(torch.float32), topk_indices.to(torch.int32)\n\n\n# This is used by the Deepseek-V2 and Deepseek-V3 model\n@torch.compile(\n dynamic=True,\n backend=current_platform.simple_compile_backend,\n options=maybe_disable_graph_partition(current_platform.simple_compile_backend),\n)\ndef grouped_topk(\n hidden_states: torch.Tensor,\n gating_output: torch.Tensor,\n topk: int,\n renormalize: bool,\n num_expert_group: int = 0,\n topk_group: int = 0,\n scoring_func: str = \"softmax\",\n routed_scaling_factor: float = 1.0,\n e_score_correction_bias: torch.Tensor | None = None,\n) -> tuple[torch.Tensor, torch.Tensor]:\n if (\n envs.VLLM_USE_FUSED_MOE_GROUPED_TOPK\n and current_platform.is_cuda()\n and num_expert_group <= 32\n and topk <= 32\n and e_score_correction_bias is not None\n ):\n return fused_grouped_topk(\n hidden_states=hidden_states,\n gating_output=gating_output,\n topk=topk,\n renormalize=renormalize,\n e_score_correction_bias=e_score_correction_bias,\n num_expert_group=num_expert_group,\n topk_group=topk_group,\n scoring_func=scoring_func,\n routed_scaling_factor=routed_scaling_factor,\n )\n\n assert hidden_states.size(0) == gating_output.size(0), \"Number of tokens mismatch\"\n\n if scoring_func == \"softmax\":\n scores = torch.softmax(gating_output, dim=-1)\n elif scoring_func == \"sigmoid\":\n scores = gating_output.sigmoid()\n else:\n raise ValueError(f\"Unsupported scoring function: {scoring_func}\")\n\n num_token = scores.size(0)\n if e_score_correction_bias is not None:\n # Store original scores before applying correction bias. We use biased\n # scores for expert selection but original scores for routing weights\n original_scores = scores\n scores = scores + e_score_correction_bias.unsqueeze(0)\n group_scores = (\n scores.view(num_token, num_expert_group, -1).topk(2, dim=-1)[0].sum(dim=-1)\n )\n else:\n group_scores = (\n scores.view(num_token, num_expert_group, -1).max(dim=-1).values\n ) # [n, n_group]\n\n # For batch invariance, use sorted=True to ensure deterministic expert selection\n use_sorted = vllm_is_batch_invariant()\n group_idx = torch.topk(group_scores, k=topk_group, dim=-1, sorted=use_sorted)[\n 1\n ] # [n, top_k_group]\n group_mask = torch.zeros_like(group_scores) # [n, n_group]\n group_mask.scatter_(1, group_idx, 1) # [n, n_group]\n score_mask = (\n group_mask.unsqueeze(-1)\n .expand(num_token, num_expert_group, scores.size(-1) // num_expert_group)\n .reshape(num_token, -1)\n ) # [n, e]\n tmp_scores = scores.masked_fill(~score_mask.bool(), float(\"-inf\")) # [n, e]\n\n if e_score_correction_bias is not None:\n topk_ids = torch.topk(tmp_scores, k=topk, dim=-1, sorted=use_sorted)[1]\n # Use original unbiased scores for the routing weights\n topk_weights = original_scores.gather(1, topk_ids)\n else:\n topk_weights, topk_ids = torch.topk(\n tmp_scores, k=topk, dim=-1, sorted=use_sorted\n )\n\n if renormalize:\n topk_weights = topk_weights / topk_weights.sum(dim=-1, keepdim=True)\n\n if routed_scaling_factor != 1.0:\n topk_weights = topk_weights * routed_scaling_factor\n return topk_weights.to(torch.float32), topk_ids.to(torch.int32)\n\n\n@torch.compile(dynamic=True, backend=current_platform.simple_compile_backend)\ndef eplb_map_to_physical_and_record(\n topk_ids: torch.Tensor,\n expert_load_view: torch.Tensor,\n logical_to_physical_map: torch.Tensor,\n logical_replica_count: torch.Tensor,\n) -> torch.Tensor:\n \"\"\"\n Map the logical expert ids to physical expert ids\n and record the expert load metrics.\n\n This will select a pseudo-random replica for each logical expert.\n Only used for EPLB.\n\n Args:\n topk_ids: The logical expert ids.\n expert_load_view: The expert load view.\n logical_to_physical_map: The logical to physical map.\n logical_replica_count: The logical replica count.\n\n Returns:\n The physical expert ids.\n \"\"\"\n\n # 1. Convert the logical expert ids to physical expert ids\n # Directly select a random replica for each logical expert\n\n # In case `indices_type` is not `torch.long` or `torch.int`,\n # e.g. `torch.uint32` as required by dispatch/combine kernels\n topk_ids_long = topk_ids.long()\n # Use (token position) modulo (replica count)\n # to deterministically choose a replica\n replica_count = logical_replica_count[topk_ids_long]\n # Flatten-position based index, reshaped back to `topk_ids` shape\n pos_indices = torch.arange(\n topk_ids.numel(), device=topk_ids.device, dtype=torch.long\n ).reshape_as(topk_ids)\n # Compute pseudo-random indices by modulo\n replica_indices = (pos_indices % replica_count).unsqueeze(-1)\n physical_ids = (\n logical_to_physical_map[topk_ids_long].gather(-1, replica_indices).squeeze(-1)\n )\n\n topk_ids = physical_ids\n\n # 2. Record expert load metrics.\n\n # TODO(bowen): When using `FusedMoEModularKernel`, this\n # can be done in a more unified way, since\n # `FusedMoEPrepareAndFinalize` will return the expert\n # token count, in some cases directly from the kernel.\n # However, now there are many code paths not using\n # the modular kernel, e.g. calling `fused_experts`,\n # so we decide to keep the logic here.\n #\n # If later refactor moved all the MoE kernel calls\n # to the modular kernel, we can move this logic there\n # to achieve better efficiency.\n\n # `expert_load_view`: (num_physical_experts,)\n\n # `torch.bincount` is not compilable, so use `scatter_add_` instead.\n topk_ids_flatten = topk_ids.flatten()\n expert_load_view.scatter_add_(\n dim=0,\n index=topk_ids_flatten.long(),\n src=torch.ones_like(topk_ids_flatten).to(expert_load_view),\n )\n return topk_ids\n\n\ndef fused_grouped_topk(\n hidden_states: torch.Tensor,\n gating_output: torch.Tensor,\n topk: int,\n renormalize: bool,\n e_score_correction_bias: torch.Tensor,\n num_expert_group: int = 0,\n topk_group: int = 0,\n scoring_func: str = \"softmax\",\n routed_scaling_factor: float = 1.0,\n) -> tuple[torch.Tensor, torch.Tensor]:\n assert hidden_states.size(0) == gating_output.size(0), \"Number of tokens mismatch\"\n\n if scoring_func == \"sigmoid\":\n # Fully fused kernel path for sigmoid\n topk_values, topk_indices = ops.grouped_topk(\n gating_output, # raw logits\n num_expert_group,\n topk_group,\n topk,\n renormalize,\n routed_scaling_factor,\n e_score_correction_bias.to(gating_output.dtype),\n 1, # scoring_func=1 for sigmoid\n )\n elif scoring_func == \"softmax\":\n # Apply softmax in Python, then use fused kernel\n # TODO: Add support for softmax in kernel\n scores = torch.softmax(gating_output, dim=-1)\n topk_values, topk_indices = ops.grouped_topk(\n scores, # pre-computed scores\n num_expert_group,\n topk_group,\n topk,\n renormalize,\n routed_scaling_factor,\n e_score_correction_bias.to(gating_output.dtype),\n 0, # scoring_func=0 (no activation, scores already computed)\n )\n else:\n raise ValueError(f\"Unsupported scoring function: {scoring_func}\")\n\n # Fused kernel outputs float32 values and int32 indices directly\n return topk_values, topk_indices\n\n\ndef inplace_fused_experts(\n hidden_states: torch.Tensor,\n w1: torch.Tensor,\n w2: torch.Tensor,\n topk_weights: torch.Tensor,\n topk_ids: torch.Tensor,\n activation: str = \"silu\",\n apply_router_weight_on_input: bool = False,\n use_fp8_w8a8: bool = False,\n use_int8_w8a8: bool = False,\n use_int8_w8a16: bool = False,\n use_int4_w4a16: bool = False,\n ocp_mx_scheme: str | None = None,\n per_channel_quant: bool = False,\n global_num_experts: int = -1,\n expert_map: torch.Tensor | None = None,\n w1_scale: torch.Tensor | None = None,\n w2_scale: torch.Tensor | None = None,\n w1_zp: torch.Tensor | None = None,\n w2_zp: torch.Tensor | None = None,\n a1_scale: torch.Tensor | None = None,\n a2_scale: torch.Tensor | None = None,\n block_shape: list[int] | None = None,\n w1_bias: torch.Tensor | None = None,\n w2_bias: torch.Tensor | None = None,\n) -> None:\n fused_experts_impl(\n hidden_states,\n w1,\n w2,\n topk_weights,\n topk_ids,\n True,\n activation,\n apply_router_weight_on_input,\n use_fp8_w8a8,\n use_int8_w8a8,\n use_int8_w8a16,\n use_int4_w4a16,\n ocp_mx_scheme,\n per_channel_quant,\n global_num_experts,\n expert_map,\n w1_scale,\n w2_scale,\n w1_zp,\n w2_zp,\n a1_scale,\n a2_scale,\n block_shape,\n w1_bias,\n w2_bias,\n )\n\n\ndef inplace_fused_experts_fake(\n hidden_states: torch.Tensor,\n w1: torch.Tensor,\n w2: torch.Tensor,\n topk_weights: torch.Tensor,\n topk_ids: torch.Tensor,\n activation: str = \"silu\",\n apply_router_weight_on_input: bool = False,\n use_fp8_w8a8: bool = False,\n use_int8_w8a8: bool = False,\n use_int8_w8a16: bool = False,\n use_int4_w4a16: bool = False,\n ocp_mx_scheme: str | None = None,\n per_channel_quant: bool = False,\n global_num_experts: int = -1,\n expert_map: torch.Tensor | None = None,\n w1_scale: torch.Tensor | None = None,\n w2_scale: torch.Tensor | None = None,\n w1_zp: torch.Tensor | None = None,\n w2_zp: torch.Tensor | None = None,\n a1_scale: torch.Tensor | None = None,\n a2_scale: torch.Tensor | None = None,\n block_shape: list[int] | None = None,\n w1_bias: torch.Tensor | None = None,\n w2_bias: torch.Tensor | None = None,\n) -> None:\n pass\n\n\ndirect_register_custom_op(\n op_name=\"inplace_fused_experts\",\n op_func=inplace_fused_experts,\n mutates_args=[\"hidden_states\"],\n fake_impl=inplace_fused_experts_fake,\n tags=(\n ()\n if is_torch_equal_or_newer(\"2.7.0\")\n else (torch.Tag.needs_fixed_stride_order,)\n ),\n)\n\n\ndef outplace_fused_experts(\n hidden_states: torch.Tensor,\n w1: torch.Tensor,\n w2: torch.Tensor,\n topk_weights: torch.Tensor,\n topk_ids: torch.Tensor,\n activation: str = \"silu\",\n apply_router_weight_on_input: bool = False,\n use_fp8_w8a8: bool = False,\n use_int8_w8a8: bool = False,\n use_int8_w8a16: bool = False,\n use_int4_w4a16: bool = False,\n ocp_mx_scheme: str | None = None,\n per_channel_quant: bool = False,\n global_num_experts: int = -1,\n expert_map: torch.Tensor | None = None,\n w1_scale: torch.Tensor | None = None,\n w2_scale: torch.Tensor | None = None,\n w1_zp: torch.Tensor | None = None,\n w2_zp: torch.Tensor | None = None,\n a1_scale: torch.Tensor | None = None,\n a2_scale: torch.Tensor | None = None,\n block_shape: list[int] | None = None,\n w1_bias: torch.Tensor | None = None,\n w2_bias: torch.Tensor | None = None,\n) -> torch.Tensor:\n return fused_experts_impl(\n hidden_states,\n w1,\n w2,\n topk_weights,\n topk_ids,\n False,\n activation,\n apply_router_weight_on_input,\n use_fp8_w8a8,\n use_int8_w8a8,\n use_int8_w8a16,\n use_int4_w4a16,\n ocp_mx_scheme,\n per_channel_quant,\n global_num_experts,\n expert_map,\n w1_scale,\n w2_scale,\n w1_zp,\n w2_zp,\n a1_scale,\n a2_scale,\n block_shape,\n w1_bias,\n w2_bias,\n )\n\n\ndef outplace_fused_experts_fake(\n hidden_states: torch.Tensor,\n w1: torch.Tensor,\n w2: torch.Tensor,\n topk_weights: torch.Tensor,\n topk_ids: torch.Tensor,\n activation: str = \"silu\",\n use_fp8_w8a8: bool = False,\n use_int8_w8a8: bool = False,\n use_int8_w8a16: bool = False,\n use_int4_w4a16: bool = False,\n ocp_mx_scheme: str | None = None,\n per_channel_quant: bool = False,\n global_num_experts: int = -1,\n expert_map: torch.Tensor | None = None,\n w1_scale: torch.Tensor | None = None,\n w2_scale: torch.Tensor | None = None,\n w1_zp: torch.Tensor | None = None,\n w2_zp: torch.Tensor | None = None,\n a1_scale: torch.Tensor | None = None,\n a2_scale: torch.Tensor | None = None,\n block_shape: list[int] | None = None,\n w1_bias: torch.Tensor | None = None,\n w2_bias: torch.Tensor | None = None,\n) -> torch.Tensor:\n return torch.empty_like(hidden_states)\n\n\ndirect_register_custom_op(\n op_name=\"outplace_fused_experts\",\n op_func=outplace_fused_experts,\n fake_impl=outplace_fused_experts_fake,\n tags=(\n ()\n if is_torch_equal_or_newer(\"2.7.0\")\n else (torch.Tag.needs_fixed_stride_order,)\n ),\n)\n\n\ndef torch_vllm_inplace_fused_experts(**kwargs) -> torch.Tensor:\n torch.ops.vllm.inplace_fused_experts(**kwargs)\n hidden_states = kwargs[\"hidden_states\"]\n return hidden_states\n\n\ndef torch_vllm_outplace_fused_experts(**kwargs) -> torch.Tensor:\n return torch.ops.vllm.outplace_fused_experts(**kwargs)\n\n\ndef dispatch_fused_experts_func(inplace: bool) -> Callable[..., torch.Tensor]:\n if inplace and not disable_inplace():\n return torch_vllm_inplace_fused_experts\n return torch_vllm_outplace_fused_experts\n\n\n# TODO (bnell): replace this with modular op. Can get rid of inplace/outplace\n# torch ops.\ndef fused_experts(\n hidden_states: torch.Tensor,\n w1: torch.Tensor,\n w2: torch.Tensor,\n topk_weights: torch.Tensor,\n topk_ids: torch.Tensor,\n inplace: bool = False,\n activation: str = \"silu\",\n apply_router_weight_on_input: bool = False,\n global_num_experts: int = -1,\n expert_map: torch.Tensor | None = None,\n quant_config: FusedMoEQuantConfig | None = None,\n allow_deep_gemm: bool = False,\n allow_cutlass_block_scaled_grouped_gemm: bool = False,\n) -> torch.Tensor:\n if quant_config is None:\n quant_config = FUSED_MOE_UNQUANTIZED_CONFIG\n use_fp8_w8a8 = quant_config.use_fp8_w8a8\n\n # For now, disable DeepGemm for small N (<= 512) until better\n # permute/unpermute ops are available.\n # However, on B200, we use DeepGemm for all cases because they only support\n # E8M0 scale, which means we requantize the weight and input to the specific\n # scale. Fallen back to cutlass or triton for some cases would cause\n # accuracy issue.\n if (\n allow_deep_gemm\n and quant_config.use_fp8_w8a8\n and (is_deep_gemm_e8m0_used() or _valid_deep_gemm(hidden_states, w1, w2))\n ):\n assert quant_config is not None\n assert apply_router_weight_on_input is False\n return deep_gemm_moe_fp8(\n hidden_states=hidden_states,\n w1=w1,\n w2=w2,\n topk_weights=topk_weights,\n topk_ids=topk_ids,\n inplace=inplace,\n activation=activation,\n global_num_experts=global_num_experts,\n expert_map=expert_map,\n w1_scale=quant_config.w1_scale,\n w2_scale=quant_config.w2_scale,\n a1_scale=quant_config.a1_scale,\n a2_scale=quant_config.a2_scale,\n apply_router_weight_on_input=apply_router_weight_on_input,\n )\n elif (\n allow_cutlass_block_scaled_grouped_gemm\n and use_fp8_w8a8\n and _valid_cutlass_block_scaled_grouped_gemm(\n w1, w2, inplace, activation, apply_router_weight_on_input, expert_map\n )\n ):\n assert quant_config is not None\n return run_cutlass_block_scaled_fused_experts(\n a=hidden_states,\n w1=w1,\n w2=w2,\n w1_scale=quant_config.w1_scale,\n w2_scale=quant_config.w2_scale,\n topk_weights=topk_weights,\n topk_ids=topk_ids,\n )\n else:\n return dispatch_fused_experts_func(inplace)(\n hidden_states=hidden_states,\n w1=w1,\n w2=w2,\n topk_weights=topk_weights,\n topk_ids=topk_ids,\n activation=activation,\n apply_router_weight_on_input=apply_router_weight_on_input,\n use_fp8_w8a8=quant_config.use_fp8_w8a8,\n use_int8_w8a8=quant_config.use_int8_w8a8,\n use_int8_w8a16=quant_config.use_int8_w8a16,\n use_int4_w4a16=quant_config.use_int4_w4a16,\n ocp_mx_scheme=quant_config.ocp_mx_scheme,\n per_channel_quant=quant_config.per_act_token_quant,\n global_num_experts=global_num_experts,\n expert_map=expert_map,\n w1_scale=quant_config.w1_scale,\n w2_scale=quant_config.w2_scale,\n w1_zp=quant_config.w1_zp,\n w2_zp=quant_config.w2_zp,\n a1_scale=quant_config.a1_scale,\n a2_scale=quant_config.a2_scale,\n block_shape=quant_config.block_shape,\n w1_bias=quant_config.w1_bias,\n w2_bias=quant_config.w2_bias,\n )\n\n\nSILU_NO_MUL: str = activation_without_mul(\"silu\")\nGELU_NO_MUL: str = activation_without_mul(\"gelu\")\nRELU2_NO_MUL: str = activation_without_mul(\"relu2\")\n\n\ndef _get_config_quant_dtype(\n use_fp8_w8a8: bool,\n use_int8_w8a8: bool,\n ocp_mx_scheme: str | None,\n) -> None | torch.dtype | str:\n \"\"\"\n Get the quantization type based on the quantization strategy flags.\n We don't have a quant_config at this point so we need to work backwards.\n A return type of None means no quantization is required because the\n input is unquantized or has been quantized prior to calling\n fused_experts_impl.\n \"\"\"\n if use_fp8_w8a8:\n return torch.float8_e4m3fn\n elif use_int8_w8a8:\n return torch.int8\n elif ocp_mx_scheme == \"w_mxfp4_a_mxfp4\":\n return \"mxfp4\"\n elif ocp_mx_scheme in {\"w_mxfp4_a_mxfp6_e3m2\", \"w_mxfp6_e3m2_a_mxfp6_e3m2\"}:\n return \"mxfp6_e3m2\"\n elif ocp_mx_scheme in {\"w_mxfp4_a_mxfp6_e2m3\", \"w_mxfp6_e2m3_a_mxfp6_e2m3\"}:\n return \"mxfp6_e2m3\"\n return None\n\n\ndef fused_experts_impl(\n hidden_states: torch.Tensor,\n w1: torch.Tensor,\n w2: torch.Tensor,\n topk_weights: torch.Tensor,\n topk_ids: torch.Tensor,\n inplace: bool = False,\n activation: str = \"silu\",\n apply_router_weight_on_input: bool = False,\n use_fp8_w8a8: bool = False,\n use_int8_w8a8: bool = False,\n use_int8_w8a16: bool = False,\n use_int4_w4a16: bool = False,\n ocp_mx_scheme: str | None = None,\n per_channel_quant: bool = False,\n global_num_experts: int = -1,\n expert_map: torch.Tensor | None = None,\n w1_scale: torch.Tensor | None = None,\n w2_scale: torch.Tensor | None = None,\n w1_zp: torch.Tensor | None = None,\n w2_zp: torch.Tensor | None = None,\n a1_scale: torch.Tensor | None = None,\n a2_scale: torch.Tensor | None = None,\n block_shape: list[int] | None = None,\n w1_bias: torch.Tensor | None = None,\n w2_bias: torch.Tensor | None = None,\n) -> torch.Tensor:\n # Check constraints.\n if use_int4_w4a16:\n assert hidden_states.size(1) // 2 == w1.size(2), \"Hidden size mismatch\"\n elif ocp_mx_scheme is not None:\n if ocp_mx_scheme in {\n \"w_mxfp4_a_mxfp4\",\n \"w_mxfp4_a_mxfp6_e3m2\",\n \"w_mxfp4_a_mxfp6_e2m3\",\n }:\n # 16bit activation and fp4x2 packed weight\n assert hidden_states.size(1) == w1.size(2) * 2, \"hidden size mismatch\"\n elif ocp_mx_scheme in {\n \"w_mxfp6_e3m2_a_mxfp6_e3m2\",\n \"w_mxfp6_e2m3_a_mxfp6_e2m3\",\n }:\n assert hidden_states.size(1) == (w1.size(2) * 4) // 3, (\n \"hidden size mismatch\"\n )\n else:\n raise NotImplementedError(f\"Unsupported ocp_mx_scheme={ocp_mx_scheme}\")\n else:\n assert hidden_states.size(1) == w1.size(2), (\n f\"Hidden size mismatch {hidden_states.size(1)} != {w1.size(2)}\"\n )\n\n assert topk_weights.size() == topk_ids.size(), \"topk shape mismatch\"\n assert hidden_states.is_contiguous(), \"Hidden_states must be contiguous\"\n assert w1.stride(-1) == 1, \"Stride of last dimension must be 1\"\n assert w2.stride(-1) == 1, \"Stride of last dimension must be 1\"\n assert hidden_states.dtype in [torch.float32, torch.float16, torch.bfloat16]\n\n num_tokens = hidden_states.size(0)\n E, N, _ = w1.size()\n K = w2.size(1)\n if global_num_experts == -1:\n global_num_experts = E\n top_k_num = topk_ids.size(1)\n # We execute the fused_moe kernel in chunks to circumvent this issue:\n # https://github.com/vllm-project/vllm/issues/5938\n CHUNK_SIZE = envs.VLLM_FUSED_MOE_CHUNK_SIZE\n M = min(num_tokens, CHUNK_SIZE)\n\n config_dtype = _get_config_dtype_str(\n use_fp8_w8a8=use_fp8_w8a8,\n use_int8_w8a16=use_int8_w8a16,\n use_int4_w4a16=use_int4_w4a16,\n ocp_mx_scheme=ocp_mx_scheme,\n dtype=hidden_states.dtype,\n )\n\n # Note: for use_int8_w8a16 or use_int4_w4a16, the activations are\n # quantized prior to calling fused_experts.\n quant_dtype = _get_config_quant_dtype(\n use_fp8_w8a8=use_fp8_w8a8,\n use_int8_w8a8=use_int8_w8a8,\n ocp_mx_scheme=ocp_mx_scheme,\n )\n\n get_config_func = functools.partial(\n try_get_optimal_moe_config,\n w1.size(),\n w2.size(),\n top_k_num,\n config_dtype,\n block_shape=block_shape,\n )\n\n config = get_config_func(M)\n\n # We can reuse the memory between these because by the time we need\n # cache3, we're done with cache1\n cache13 = torch.empty(\n M * top_k_num * max(N, K),\n device=hidden_states.device,\n dtype=hidden_states.dtype,\n )\n intermediate_cache1 = cache13[: M * top_k_num * N].view(M, top_k_num, N)\n intermediate_cache3 = cache13[: M * top_k_num * K].view(M, top_k_num, K)\n\n # This needs separate memory since it's used concurrently with cache1\n intermediate_cache2 = torch.empty(\n (M * top_k_num, N // 2), device=hidden_states.device, dtype=hidden_states.dtype\n )\n\n if hidden_states.dtype == torch.bfloat16:\n compute_type = tl.bfloat16\n elif hidden_states.dtype == torch.float16:\n compute_type = tl.float16\n elif hidden_states.dtype == torch.float32:\n compute_type = tl.float32\n else:\n raise ValueError(f\"Unsupported compute_type: {hidden_states.dtype}\")\n\n if inplace and not disable_inplace():\n out_hidden_states = hidden_states\n else:\n out_hidden_states = torch.empty_like(hidden_states)\n\n if ocp_mx_scheme is not None:\n # TODO: On platforms for which `current_platform.supports_mx()` is True\n # and for which we have a native OCP mx fused MOE kernel,\n # this dequantization step should not be done.\n if ocp_mx_scheme in {\n OCP_MX_Scheme.w_mxfp4_a_mxfp4,\n OCP_MX_Scheme.w_mxfp4_a_mxfp6_e3m2,\n OCP_MX_Scheme.w_mxfp4_a_mxfp6_e2m3,\n }:\n # Weight has to be dequantized for mxfp4 emulation.\n w1 = dequant_mxfp4(w1, w1_scale, hidden_states.dtype)\n w1_scale = None\n w2 = dequant_mxfp4(w2, w2_scale, hidden_states.dtype)\n w2_scale = None\n elif ocp_mx_scheme == OCP_MX_Scheme.w_mxfp6_e3m2_a_mxfp6_e3m2:\n w1 = dequant_mxfp6(\n w1, w1_scale, quant_dtype=\"fp6_e3m2\", float_dtype=hidden_states.dtype\n )\n w1_scale = None\n w2 = dequant_mxfp6(\n w2, w2_scale, quant_dtype=\"fp6_e3m2\", float_dtype=hidden_states.dtype\n )\n w2_scale = None\n elif ocp_mx_scheme == OCP_MX_Scheme.w_mxfp6_e2m3_a_mxfp6_e2m3:\n w1 = dequant_mxfp6(\n w1, w1_scale, quant_dtype=\"fp6_e2m3\", float_dtype=hidden_states.dtype\n )\n w1_scale = None\n w2 = dequant_mxfp6(\n w2, w2_scale, quant_dtype=\"fp6_e2m3\", float_dtype=hidden_states.dtype\n )\n w2_scale = None\n else:\n raise NotImplementedError(f\"Unsupported ocp_mx_scheme={ocp_mx_scheme}\")\n\n for chunk in range((num_tokens // CHUNK_SIZE) + 1):\n begin_chunk_idx, end_chunk_idx = (\n chunk * CHUNK_SIZE,\n min((chunk + 1) * CHUNK_SIZE, num_tokens),\n )\n curr_hidden_states = hidden_states[begin_chunk_idx:end_chunk_idx]\n tokens_in_chunk, _ = curr_hidden_states.size()\n\n if tokens_in_chunk == 0:\n break\n\n if tokens_in_chunk < CHUNK_SIZE and chunk > 0:\n # Adjust the intermediate cache size and config for the last\n # chunk. Note that in most cases we only have one chunk\n # so the cache size and config are already set correctly and\n # do not need to be adjusted.\n intermediate_cache1 = intermediate_cache1[:tokens_in_chunk]\n intermediate_cache2 = intermediate_cache2[\n : tokens_in_chunk * topk_ids.size(1)\n ]\n intermediate_cache3 = intermediate_cache3[:tokens_in_chunk]\n config = get_config_func(tokens_in_chunk)\n\n curr_topk_ids = topk_ids[begin_chunk_idx:end_chunk_idx]\n curr_topk_weights = topk_weights[begin_chunk_idx:end_chunk_idx]\n qcurr_hidden_states, a1q_scale = moe_kernel_quantize_input(\n A=curr_hidden_states,\n A_scale=a1_scale,\n quant_dtype=quant_dtype,\n per_act_token_quant=per_channel_quant,\n block_shape=block_shape,\n )\n\n sorted_token_ids, expert_ids, num_tokens_post_padded = moe_align_block_size(\n curr_topk_ids,\n config[\"BLOCK_SIZE_M\"],\n global_num_experts,\n expert_map,\n ignore_invalid_experts=True,\n )\n\n invoke_fused_moe_kernel(\n qcurr_hidden_states,\n w1,\n intermediate_cache1,\n a1q_scale,\n w1_scale,\n w1_zp,\n curr_topk_weights,\n sorted_token_ids,\n expert_ids,\n num_tokens_post_padded,\n apply_router_weight_on_input,\n top_k_num,\n config,\n compute_type=compute_type,\n use_fp8_w8a8=use_fp8_w8a8,\n use_int8_w8a8=use_int8_w8a8,\n use_int8_w8a16=use_int8_w8a16,\n use_int4_w4a16=use_int4_w4a16,\n per_channel_quant=per_channel_quant,\n block_shape=block_shape,\n B_bias=w1_bias,\n )\n\n # Activation function with multiplication\n if activation == \"silu\":\n torch.ops._C.silu_and_mul(\n intermediate_cache2, intermediate_cache1.view(-1, N)\n )\n elif activation == \"gelu\":\n torch.ops._C.gelu_and_mul(\n intermediate_cache2, intermediate_cache1.view(-1, N)\n )\n elif activation == \"swigluoai\":\n # alpha = 1.702, limit = 7.0\n torch.ops._C.swigluoai_and_mul(\n intermediate_cache2, intermediate_cache1.view(-1, N)\n )\n # Activation function without multiplication\n elif activation == SILU_NO_MUL:\n intermediate_cache2 = F.silu(intermediate_cache1.view(-1, N))\n elif activation == GELU_NO_MUL:\n intermediate_cache2 = F.gelu(intermediate_cache1.view(-1, N))\n elif activation == RELU2_NO_MUL:\n intermediate_cache2 = torch.square(F.relu(intermediate_cache1.view(-1, N)))\n else:\n raise ValueError(f\"Unsupported FusedMoe activation: {activation}.\")\n\n qintermediate_cache2, a2q_scale = moe_kernel_quantize_input(\n A=intermediate_cache2,\n A_scale=a2_scale,\n quant_dtype=quant_dtype,\n per_act_token_quant=per_channel_quant,\n block_shape=block_shape,\n )\n\n if expert_map is not None:\n intermediate_cache3.zero_()\n\n invoke_fused_moe_kernel(\n qintermediate_cache2,\n w2,\n intermediate_cache3,\n a2q_scale,\n w2_scale,\n w2_zp,\n curr_topk_weights,\n sorted_token_ids,\n expert_ids,\n num_tokens_post_padded,\n not apply_router_weight_on_input,\n 1,\n config,\n compute_type=compute_type,\n use_fp8_w8a8=use_fp8_w8a8,\n use_int8_w8a8=use_int8_w8a8,\n use_int8_w8a16=use_int8_w8a16,\n use_int4_w4a16=use_int4_w4a16,\n per_channel_quant=per_channel_quant,\n block_shape=block_shape,\n B_bias=w2_bias,\n )\n\n ops.moe_sum(\n intermediate_cache3.view(*intermediate_cache3.size()),\n out_hidden_states[begin_chunk_idx:end_chunk_idx],\n )\n\n return out_hidden_states\n\n\nclass TritonExperts(mk.FusedMoEPermuteExpertsUnpermute):\n def __init__(\n self,\n quant_config: FusedMoEQuantConfig,\n ):\n super().__init__(quant_config)\n\n @property\n def activation_formats(\n self,\n ) -> tuple[mk.FusedMoEActivationFormat, mk.FusedMoEActivationFormat]:\n return (\n mk.FusedMoEActivationFormat.Standard,\n mk.FusedMoEActivationFormat.Standard,\n )\n\n def supports_chunking(self) -> bool:\n return True\n\n def supports_expert_map(self) -> bool:\n return True\n\n def finalize_weight_and_reduce_impl(self) -> mk.TopKWeightAndReduce:\n return TopKWeightAndReduceNoOP()\n\n def workspace_shapes(\n self,\n M: int,\n N: int,\n K: int,\n topk: int,\n global_num_experts: int,\n local_num_experts: int,\n expert_tokens_meta: mk.ExpertTokensMetadata | None,\n ) -> tuple[tuple[int, ...], tuple[int, ...], tuple[int, ...]]:\n workspace1 = (M, topk, max(N // 2, K))\n workspace2 = (M, topk, max(N, K))\n output = (M, K)\n return (workspace1, workspace2, output)\n\n def apply(\n self,\n output: torch.Tensor,\n hidden_states: torch.Tensor,\n w1: torch.Tensor,\n w2: torch.Tensor,\n topk_weights: torch.Tensor,\n topk_ids: torch.Tensor,\n activation: str,\n global_num_experts: int,\n expert_map: torch.Tensor | None,\n a1q_scale: torch.Tensor | None,\n a2_scale: torch.Tensor | None,\n workspace13: torch.Tensor,\n workspace2: torch.Tensor,\n expert_tokens_meta: mk.ExpertTokensMetadata | None,\n apply_router_weight_on_input: bool,\n ):\n # Check constraints.\n if self.quant_config.use_int4_w4a16:\n assert hidden_states.size(-1) // 2 == w1.size(2), \"Hidden size mismatch\"\n else:\n assert hidden_states.size(-1) == w1.size(2), (\n f\"Hidden size mismatch {hidden_states.size(-1)} != {w1.size(2)}\"\n )\n\n assert hidden_states.is_contiguous(), \"Hidden_states must be contiguous\"\n assert hidden_states.dim() == 2\n assert w1.stride(-1) == 1, \"Stride of last dimension must be 1\"\n assert w2.stride(-1) == 1, \"Stride of last dimension must be 1\"\n assert hidden_states.dtype in [\n torch.float32,\n torch.float16,\n torch.bfloat16,\n torch.float8_e4m3fn,\n ]\n\n E, num_tokens, N, K, top_k_num = self.moe_problem_size(\n hidden_states, w1, w2, topk_ids\n )\n\n if global_num_experts == -1:\n global_num_experts = E\n\n config = try_get_optimal_moe_config(\n w1.size(),\n w2.size(),\n top_k_num,\n self.quant_config.config_name(hidden_states.dtype),\n num_tokens,\n block_shape=self.block_shape,\n )\n\n if hidden_states.dtype == torch.bfloat16:\n compute_type = tl.bfloat16\n elif hidden_states.dtype == torch.float16:\n compute_type = tl.float16\n elif hidden_states.dtype == torch.float32:\n compute_type = tl.float32\n elif hidden_states.dtype == torch.float8_e4m3fn:\n compute_type = tl.bfloat16\n else:\n raise ValueError(f\"Unsupported compute_type: {hidden_states.dtype}\")\n\n # Note that the output tensor might be in workspace1\n intermediate_cache1 = _resize_cache(workspace2, (num_tokens, top_k_num, N))\n intermediate_cache2 = _resize_cache(\n workspace13, (num_tokens * top_k_num, N // 2)\n )\n intermediate_cache3 = _resize_cache(workspace2, (num_tokens, top_k_num, K))\n\n sorted_token_ids, expert_ids, num_tokens_post_padded = moe_align_block_size(\n topk_ids, config[\"BLOCK_SIZE_M\"], global_num_experts, expert_map\n )\n\n invoke_fused_moe_kernel(\n hidden_states,\n w1,\n intermediate_cache1,\n a1q_scale,\n self.w1_scale,\n self.w1_zp,\n None, # topk_weights\n sorted_token_ids,\n expert_ids,\n num_tokens_post_padded,\n False, # mul_routed_weights\n top_k_num,\n config,\n compute_type=compute_type,\n use_fp8_w8a8=self.quant_config.use_fp8_w8a8,\n use_int8_w8a8=self.quant_config.use_int8_w8a8,\n use_int8_w8a16=self.quant_config.use_int8_w8a16,\n use_int4_w4a16=self.quant_config.use_int4_w4a16,\n per_channel_quant=self.per_act_token_quant,\n block_shape=self.block_shape,\n B_bias=self.w1_bias,\n )\n\n self.activation(\n activation, intermediate_cache2, intermediate_cache1.view(-1, N)\n )\n\n a2q_scale: torch.Tensor | None = None\n\n qintermediate_cache2, a2q_scale = moe_kernel_quantize_input(\n intermediate_cache2,\n a2_scale,\n self.quant_dtype,\n self.per_act_token_quant,\n self.block_shape,\n )\n\n invoke_fused_moe_kernel(\n qintermediate_cache2,\n w2,\n intermediate_cache3,\n a2q_scale,\n self.w2_scale,\n self.w2_zp,\n topk_weights,\n sorted_token_ids,\n expert_ids,\n num_tokens_post_padded,\n not apply_router_weight_on_input,\n 1,\n config,\n compute_type=compute_type,\n use_fp8_w8a8=self.quant_config.use_fp8_w8a8,\n use_int8_w8a8=self.quant_config.use_int8_w8a8,\n use_int8_w8a16=self.quant_config.use_int8_w8a16,\n use_int4_w4a16=self.quant_config.use_int4_w4a16,\n per_channel_quant=self.per_act_token_quant,\n block_shape=self.block_shape,\n B_bias=self.w2_bias,\n )\n\n # separate function is required for MoE + LoRA\n self.moe_sum(intermediate_cache3, output)\n\n def moe_sum(self, input: torch.Tensor, output: torch.Tensor) -> None:\n ops.moe_sum(input, output)\n\n\ndef modular_triton_fused_moe(\n quant_config: FusedMoEQuantConfig, shared_experts: torch.nn.Module | None = None\n) -> mk.FusedMoEModularKernel:\n return mk.FusedMoEModularKernel(\n MoEPrepareAndFinalizeNoEP(),\n TritonExperts(quant_config),\n shared_experts,\n )\n"},"diff":{"kind":"string","value":"--- vllm/model_executor/layers/fused_moe/fused_moe.py\n+++ vllm/model_executor/layers/fused_moe/fused_moe.py\n@@ -1887,7 +1887,11 @@\n )\n \n sorted_token_ids, expert_ids, num_tokens_post_padded = moe_align_block_size(\n- curr_topk_ids, config[\"BLOCK_SIZE_M\"], global_num_experts, expert_map\n+ curr_topk_ids,\n+ config[\"BLOCK_SIZE_M\"],\n+ global_num_experts,\n+ expert_map,\n+ ignore_invalid_experts=True,\n )\n \n invoke_fused_moe_kernel(\n@@ -1945,6 +1949,9 @@\n per_act_token_quant=per_channel_quant,\n block_shape=block_shape,\n )\n+\n+ if expert_map is not None:\n+ intermediate_cache3.zero_()\n \n invoke_fused_moe_kernel(\n qintermediate_cache2,"},"lines_added":{"kind":"number","value":8,"string":"8"},"lines_removed":{"kind":"number","value":1,"string":"1"},"files_in_commit":{"kind":"number","value":6,"string":"6"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this triton kernel file from vllm (vllm/model_executor/layers/fused_moe/fused_moe.py).\n\nGoal: [Kernel][MoE] optimize `moe_align_block_size`\nTarget hardware: unspecified\nTarget models: unspecified\n\nCurrent file:\n```python\n# SPDX-License-Identifier: Apache-2.0\n# SPDX-FileCopyrightText: Copyright contributors to the vLLM project\n\"\"\"Fused MoE Triton kernels.\"\"\"\n\nimport functools\nimport json\nimport os\nfrom collections.abc import Callable\nfrom typing import Any\n\nimport torch\nimport torch.nn.functional as F\n\nimport vllm.envs as envs\nimport vllm.model_executor.layers.fused_moe.modular_kernel as mk\nfrom vllm import _custom_ops as ops\nfrom vllm._aiter_ops import rocm_aiter_ops\nfrom vllm.logger import init_logger\nfrom vllm.model_executor.layers.batch_invariant import (\n vllm_is_batch_invariant,\n)\nfrom vllm.model_executor.layers.fused_moe.config import (\n FUSED_MOE_UNQUANTIZED_CONFIG,\n FusedMoEQuantConfig,\n _get_config_dtype_str,\n)\nfrom vllm.model_executor.layers.fused_moe.cutlass_moe import (\n _valid_cutlass_block_scaled_grouped_gemm,\n run_cutlass_block_scaled_fused_experts,\n)\nfrom vllm.model_executor.layers.fused_moe.deep_gemm_moe import (\n _valid_deep_gemm,\n deep_gemm_moe_fp8,\n)\nfrom vllm.model_executor.layers.fused_moe.moe_align_block_size import (\n moe_align_block_size,\n)\nfrom vllm.model_executor.layers.fused_moe.prepare_finalize import (\n MoEPrepareAndFinalizeNoEP,\n)\nfrom vllm.model_executor.layers.fused_moe.topk_weight_and_reduce import (\n TopKWeightAndReduceNoOP,\n)\nfrom vllm.model_executor.layers.fused_moe.utils import (\n _resize_cache,\n activation_without_mul,\n disable_inplace,\n moe_kernel_quantize_input,\n)\nfrom vllm.model_executor.layers.quantization.utils.mxfp4_utils import dequant_mxfp4\nfrom vllm.model_executor.layers.quantization.utils.mxfp6_utils import dequant_mxfp6\nfrom vllm.model_executor.layers.quantization.utils.ocp_mx_utils import OCP_MX_Scheme\nfrom vllm.model_executor.utils import maybe_disable_graph_partition\nfrom vllm.platforms import current_platform\nfrom vllm.triton_utils import tl, triton\nfrom vllm.utils.deep_gemm import is_deep_gemm_e8m0_used\nfrom vllm.utils.torch_utils import direct_register_custom_op, is_torch_equal_or_newer\n\nlogger = init_logger(__name__)\n\n\n@triton.jit\ndef write_zeros_to_output(\n c_ptr,\n stride_cm,\n stride_cn,\n pid_n,\n N,\n offs_token,\n token_mask,\n BLOCK_SIZE_M,\n BLOCK_SIZE_N,\n compute_type,\n):\n accumulator = tl.zeros((BLOCK_SIZE_M, BLOCK_SIZE_N), dtype=compute_type)\n offs_cn = pid_n * BLOCK_SIZE_N + tl.arange(0, BLOCK_SIZE_N)\n c_ptrs = c_ptr + stride_cm * offs_token[:, None] + stride_cn * offs_cn[None, :]\n c_mask = token_mask[:, None] & (offs_cn[None, :] < N)\n tl.store(c_ptrs, accumulator, mask=c_mask)\n\n\n@triton.jit\ndef fused_moe_kernel_gptq_awq(\n # Pointers to matrices\n a_ptr,\n b_ptr,\n c_ptr,\n b_scale_ptr,\n b_zp_ptr,\n topk_weights_ptr,\n sorted_token_ids_ptr,\n expert_ids_ptr,\n num_tokens_post_padded_ptr,\n # Matrix dimensions\n N: tl.constexpr,\n K: tl.constexpr,\n EM,\n num_valid_tokens,\n # The stride variables represent how much to increase the ptr by when\n # moving by 1 element in a particular dimension. E.g. `stride_am` is\n # how much to increase `a_ptr` by to get the element one row down\n # (A has M rows).\n stride_am,\n stride_ak,\n stride_be,\n stride_bk,\n stride_bn,\n stride_cm,\n stride_cn,\n stride_bse,\n stride_bsk,\n stride_bsn,\n stride_bze,\n stride_bzk,\n stride_bzn,\n block_k_diviable: tl.constexpr,\n group_size: tl.constexpr,\n # Meta-parameters\n BLOCK_SIZE_M: tl.constexpr,\n BLOCK_SIZE_N: tl.constexpr,\n BLOCK_SIZE_K: tl.constexpr,\n GROUP_SIZE_M: tl.constexpr,\n SPLIT_K: tl.constexpr,\n MUL_ROUTED_WEIGHT: tl.constexpr,\n top_k: tl.constexpr,\n compute_type: tl.constexpr,\n has_zp: tl.constexpr,\n use_int4_w4a16: tl.constexpr,\n use_int8_w8a16: tl.constexpr,\n):\n \"\"\"\n Implements the fused computation for a Mixture of Experts (MOE) using\n token and expert matrices.\n\n Key Parameters:\n - A: The input tensor representing tokens with shape (*, K), where '*' can\n be any shape representing batches and K is the feature dimension of\n each token.\n - B: The stacked MOE weight tensor with shape (E, N, K), where E is\n the number of experts, K is the input feature dimension, and N is\n the output feature dimension.\n - C: The output cache tensor with shape (M, topk, N), where M is the\n total number of tokens post padding, topk is the number of times\n each token is repeated, and N is the output feature dimension.\n - sorted_token_ids: A tensor containing the sorted indices of tokens,\n repeated topk times and arranged by the expert index they are\n assigned to.\n - expert_ids: A tensor containing the indices of the expert for each\n block. It determines which expert matrix from B should be used for\n each block in A.\n This kernel performs the multiplication of a token by its corresponding\n expert matrix as determined by `expert_ids`. The sorting of\n `sorted_token_ids` by expert index and padding ensures divisibility by\n BLOCK_SIZE_M, which is necessary to maintain consistency in block matrix\n multiplication across different blocks processed by the same expert.\n \"\"\"\n # -----------------------------------------------------------\n # Map program ids `pid` to the block of C it should compute.\n # This is done in a grouped ordering to promote L2 data reuse.\n pid = tl.program_id(axis=0)\n num_pid_m = tl.cdiv(EM, BLOCK_SIZE_M)\n num_pid_n = tl.cdiv(N, BLOCK_SIZE_N)\n num_pid_in_group = GROUP_SIZE_M * num_pid_n\n group_id = pid // num_pid_in_group\n first_pid_m = group_id * GROUP_SIZE_M\n group_size_m = min(num_pid_m - first_pid_m, GROUP_SIZE_M)\n pid_m = first_pid_m + ((pid % num_pid_in_group) % group_size_m)\n pid_n = (pid % num_pid_in_group) // group_size_m\n\n # ----------------------------------------------------------\n # Create pointers for the first blocks of A and B.\n # We will advance this pointer as we move in the K direction\n # and accumulate\n # `a_ptrs` is a block of [BLOCK_SIZE_M, BLOCK_SIZE_K] pointers\n # `b_ptrs` is a block of [BLOCK_SIZE_K, BLOCK_SIZE_N] pointers\n num_tokens_post_padded = tl.load(num_tokens_post_padded_ptr)\n if pid_m * BLOCK_SIZE_M >= num_tokens_post_padded:\n return\n offs_token_id = pid_m * BLOCK_SIZE_M + tl.arange(0, BLOCK_SIZE_M).to(tl.int64)\n offs_token = tl.load(sorted_token_ids_ptr + offs_token_id)\n token_mask = offs_token < num_valid_tokens\n\n off_experts = tl.load(expert_ids_ptr + pid_m).to(tl.int64)\n if off_experts == -1:\n # -----------------------------------------------------------\n # Write back zeros to the output when the expert is not\n # in the current expert parallel rank.\n write_zeros_to_output(\n c_ptr,\n stride_cm,\n stride_cn,\n pid_n,\n N,\n offs_token,\n token_mask,\n BLOCK_SIZE_M,\n BLOCK_SIZE_N,\n compute_type,\n )\n return\n\n offs_bn = (pid_n * BLOCK_SIZE_N + tl.arange(0, BLOCK_SIZE_N).to(tl.int64)) % N\n offs_k = tl.arange(0, BLOCK_SIZE_K)\n a_ptrs = a_ptr + (\n offs_token[:, None] // top_k * stride_am + offs_k[None, :] * stride_ak\n )\n\n if use_int4_w4a16:\n b_ptrs = (\n b_ptr\n + off_experts * stride_be\n + (offs_k[:, None] // 2) * stride_bk\n + offs_bn[None, :] * stride_bn\n )\n b_shifter = (offs_k[:, None] % 2) * 4\n elif use_int8_w8a16:\n b_ptrs = (\n b_ptr\n + off_experts * stride_be\n + offs_k[:, None] * stride_bk\n + offs_bn[None, :] * stride_bn\n )\n\n if not has_zp and use_int4_w4a16:\n b_zp_num = 8\n if not has_zp and use_int8_w8a16:\n b_zp_num = 128\n elif has_zp and use_int4_w4a16:\n b_zp_shifter = (offs_bn[None, :] % 2) * 4\n\n # -----------------------------------------------------------\n # Iterate to compute a block of the C matrix.\n # We accumulate into a `[BLOCK_SIZE_M, BLOCK_SIZE_N]` block\n # of fp32 values for higher accuracy.\n # `accumulator` will be converted back to fp16 after the loop.\n accumulator = tl.zeros((BLOCK_SIZE_M, BLOCK_SIZE_N), dtype=tl.float32)\n for k in range(0, tl.cdiv(K, BLOCK_SIZE_K)):\n # Load the next block of A and B, generate a mask by checking the\n # K dimension.\n\n if not block_k_diviable:\n k_mask = offs_k[:, None] < K - k * BLOCK_SIZE_K\n k_other = 0.0\n else:\n k_mask = None\n k_other = None\n\n a = tl.load(\n a_ptrs,\n mask=token_mask[:, None] & (offs_k[None, :] < K - k * BLOCK_SIZE_K),\n other=0.0,\n )\n b = tl.load(b_ptrs)\n if use_int4_w4a16:\n b = (b >> b_shifter) & 0xF\n\n b_scale_ptrs = (\n b_scale_ptr\n + off_experts * stride_bse\n + offs_bn[None, :] * stride_bsn\n + ((offs_k[:, None] + BLOCK_SIZE_K * k) // group_size) * stride_bsk\n )\n b_scale = tl.load(b_scale_ptrs, mask=k_mask, other=k_other)\n b_scale = b_scale.to(tl.float32)\n\n if has_zp and use_int4_w4a16:\n offs_k_true = (offs_k[:, None] + BLOCK_SIZE_K * k) // group_size\n b_zp_ptrs = (\n b_zp_ptr\n + off_experts * stride_bze\n + (offs_bn[None, :] // 2) * stride_bzn\n + offs_k_true * stride_bzk\n )\n b_zp = tl.load(b_zp_ptrs, mask=k_mask, other=k_other)\n b_zp = (b_zp >> b_zp_shifter) & 0xF\n b_zp = b_zp.to(tl.float32)\n elif has_zp and use_int8_w8a16:\n offs_k_true = (offs_k[:, None] + BLOCK_SIZE_K * k) // group_size\n b_zp_ptrs = (\n b_zp_ptr\n + off_experts * stride_bze\n + offs_bn[None, :] * stride_bzn\n + offs_k_true * stride_bzk\n )\n b_zp = tl.load(b_zp_ptrs, mask=k_mask, other=k_other)\n b_zp = b_zp.to(tl.float32)\n\n # We accumulate along the K dimension.\n if has_zp:\n b = ((b.to(tl.float32) - b_zp) * b_scale).to(compute_type)\n else:\n b = ((b.to(tl.float32) - b_zp_num) * b_scale).to(compute_type)\n accumulator = tl.dot(a, b, acc=accumulator)\n\n # Advance the ptrs to the next K block.\n a_ptrs += BLOCK_SIZE_K * stride_ak\n if use_int4_w4a16:\n b_ptrs += (BLOCK_SIZE_K // 2) * stride_bk\n else:\n b_ptrs += BLOCK_SIZE_K * stride_bk\n\n if MUL_ROUTED_WEIGHT:\n moe_weight = tl.load(topk_weights_ptr + offs_token, mask=token_mask, other=0)\n accumulator = accumulator * moe_weight[:, None]\n\n accumulator = accumulator.to(compute_type)\n # -----------------------------------------------------------\n # Write back the block of the output\n offs_cn = pid_n * BLOCK_SIZE_N + tl.arange(0, BLOCK_SIZE_N)\n c_ptrs = c_ptr + stride_cm * offs_token[:, None] + stride_cn * offs_cn[None, :]\n c_mask = token_mask[:, None] & (offs_cn[None, :] < N)\n tl.store(c_ptrs, accumulator, mask=c_mask)\n\n\n@triton.jit\ndef fused_moe_kernel(\n # Pointers to matrices\n a_ptr,\n b_ptr,\n c_ptr,\n b_bias_ptr,\n a_scale_ptr,\n b_scale_ptr,\n topk_weights_ptr,\n sorted_token_ids_ptr,\n expert_ids_ptr,\n num_tokens_post_padded_ptr,\n # Matrix dimensions\n N,\n K,\n EM,\n num_valid_tokens,\n # The stride variables represent how much to increase the ptr by when\n # moving by 1 element in a particular dimension. E.g. `stride_am` is\n # how much to increase `a_ptr` by to get the element one row down\n # (A has M rows).\n stride_am,\n stride_ak,\n stride_be,\n stride_bk,\n stride_bn,\n stride_cm,\n stride_cn,\n stride_asm,\n stride_ask,\n stride_bse,\n stride_bsk,\n stride_bsn,\n stride_bbe, # bias expert stride\n stride_bbn, # bias N stride\n # Block size for block-wise quantization\n group_n: tl.constexpr,\n group_k: tl.constexpr,\n # Meta-parameters\n BLOCK_SIZE_M: tl.constexpr,\n BLOCK_SIZE_N: tl.constexpr,\n BLOCK_SIZE_K: tl.constexpr,\n GROUP_SIZE_M: tl.constexpr,\n SPLIT_K: tl.constexpr,\n MUL_ROUTED_WEIGHT: tl.constexpr,\n top_k: tl.constexpr,\n compute_type: tl.constexpr,\n use_fp8_w8a8: tl.constexpr,\n use_int8_w8a8: tl.constexpr,\n use_int8_w8a16: tl.constexpr,\n per_channel_quant: tl.constexpr,\n HAS_BIAS: tl.constexpr,\n):\n \"\"\"\n Implements the fused computation for a Mixture of Experts (MOE) using\n token and expert matrices.\n\n Key Parameters:\n - A: The input tensor representing tokens with shape (*, K), where '*' can\n be any shape representing batches and K is the feature dimension of\n each token.\n - B: The stacked MOE weight tensor with shape (E, N, K), where E is\n the number of experts, K is the input feature dimension, and N is\n the output feature dimension.\n - C: The output cache tensor with shape (M, topk, N), where M is the\n total number of tokens post padding, topk is the number of times\n each token is repeated, and N is the output feature dimension.\n - sorted_token_ids: A tensor containing the sorted indices of tokens,\n repeated topk times and arranged by the expert index they are\n assigned to.\n - expert_ids: A tensor containing the indices of the expert for each\n block. It determines which expert matrix from B should be used for\n each block in A.\n This kernel performs the multiplication of a token by its corresponding\n expert matrix as determined by `expert_ids`. The sorting of\n `sorted_token_ids` by expert index and padding ensures divisibility by\n BLOCK_SIZE_M, which is necessary to maintain consistency in block matrix\n multiplication across different blocks processed by the same expert.\n \"\"\"\n # -----------------------------------------------------------\n # Map program ids `pid` to the block of C it should compute.\n # This is done in a grouped ordering to promote L2 data reuse.\n pid = tl.program_id(axis=0)\n num_pid_m = tl.cdiv(EM, BLOCK_SIZE_M)\n num_pid_n = tl.cdiv(N, BLOCK_SIZE_N)\n num_pid_in_group = GROUP_SIZE_M * num_pid_n\n group_id = pid // num_pid_in_group\n first_pid_m = group_id * GROUP_SIZE_M\n group_size_m = min(num_pid_m - first_pid_m, GROUP_SIZE_M)\n pid_m = first_pid_m + ((pid % num_pid_in_group) % group_size_m)\n pid_n = (pid % num_pid_in_group) // group_size_m\n\n # ----------------------------------------------------------\n # Create pointers for the first blocks of A and B.\n # We will advance this pointer as we move in the K direction\n # and accumulate\n # `a_ptrs` is a block of [BLOCK_SIZE_M, BLOCK_SIZE_K] pointers\n # `b_ptrs` is a block of [BLOCK_SIZE_K, BLOCK_SIZE_N] pointers\n num_tokens_post_padded = tl.load(num_tokens_post_padded_ptr)\n if pid_m * BLOCK_SIZE_M >= num_tokens_post_padded:\n return\n offs_token_id = pid_m * BLOCK_SIZE_M + tl.arange(0, BLOCK_SIZE_M).to(tl.int64)\n offs_token = tl.load(sorted_token_ids_ptr + offs_token_id)\n token_mask = offs_token < num_valid_tokens\n\n off_experts = tl.load(expert_ids_ptr + pid_m).to(tl.int64)\n if off_experts == -1:\n # -----------------------------------------------------------\n # Write back zeros to the output when the expert is not\n # in the current expert parallel rank.\n write_zeros_to_output(\n c_ptr,\n stride_cm,\n stride_cn,\n pid_n,\n N,\n offs_token,\n token_mask,\n BLOCK_SIZE_M,\n BLOCK_SIZE_N,\n compute_type,\n )\n return\n\n offs_bn = (pid_n * BLOCK_SIZE_N + tl.arange(0, BLOCK_SIZE_N).to(tl.int64)) % N\n offs_k = tl.arange(0, BLOCK_SIZE_K)\n a_ptrs = a_ptr + (\n offs_token[:, None] // top_k * stride_am + offs_k[None, :] * stride_ak\n )\n\n b_ptrs = (\n b_ptr\n + off_experts * stride_be\n + (offs_k[:, None] * stride_bk + offs_bn[None, :] * stride_bn)\n )\n if use_int8_w8a16:\n b_scale_ptrs = (\n b_scale_ptr + off_experts * stride_bse + offs_bn[None, :] * stride_bsn\n )\n b_scale = tl.load(b_scale_ptrs)\n\n if use_fp8_w8a8 or use_int8_w8a8:\n # block-wise\n if group_k > 0 and group_n > 0:\n a_scale_ptrs = a_scale_ptr + (offs_token // top_k) * stride_asm\n offs_bsn = offs_bn // group_n\n b_scale_ptrs = (\n b_scale_ptr + off_experts * stride_bse + offs_bsn * stride_bsn\n )\n # channel-wise\n elif per_channel_quant:\n b_scale_ptrs = (\n b_scale_ptr + off_experts * stride_bse + offs_bn[None, :] * stride_bsn\n )\n b_scale = tl.load(b_scale_ptrs)\n # Load per-token scale for activations\n a_scale_ptrs = a_scale_ptr + (offs_token // top_k) * stride_asm\n a_scale = tl.load(a_scale_ptrs, mask=token_mask, other=0.0)[:, None]\n # tensor-wise\n else:\n a_scale = tl.load(a_scale_ptr)\n b_scale = tl.load(b_scale_ptr + off_experts)\n if HAS_BIAS:\n # bias shape: [num_experts, N]\n bias_ptrs = b_bias_ptr + off_experts * stride_bbe + offs_bn * stride_bbn\n bias = tl.load(bias_ptrs, mask=(offs_bn < N), other=0.0)\n # -----------------------------------------------------------\n # Iterate to compute a block of the C matrix.\n # We accumulate into a `[BLOCK_SIZE_M, BLOCK_SIZE_N]` block\n # of fp32 values for higher accuracy.\n # `accumulator` will be converted back to fp16 after the loop.\n accumulator = tl.zeros((BLOCK_SIZE_M, BLOCK_SIZE_N), dtype=tl.float32)\n for k in range(0, tl.cdiv(K, BLOCK_SIZE_K)):\n # Load the next block of A and B, generate a mask by checking the\n # K dimension.\n a = tl.load(\n a_ptrs,\n mask=token_mask[:, None] & (offs_k[None, :] < K - k * BLOCK_SIZE_K),\n other=0.0,\n )\n b = tl.load(b_ptrs, mask=offs_k[:, None] < K - k * BLOCK_SIZE_K, other=0.0)\n # We accumulate along the K dimension.\n if use_int8_w8a16:\n accumulator = tl.dot(a, b.to(compute_type), acc=accumulator)\n elif use_fp8_w8a8 or use_int8_w8a8:\n if group_k > 0 and group_n > 0:\n k_start = k * BLOCK_SIZE_K\n offs_ks = k_start // group_k\n a_scale = tl.load(\n a_scale_ptrs + offs_ks * stride_ask, mask=token_mask, other=0.0\n )\n b_scale = tl.load(b_scale_ptrs + offs_ks * stride_bsk)\n\n accumulator += tl.dot(a, b) * a_scale[:, None] * b_scale[None, :]\n else:\n if use_fp8_w8a8:\n # acc used to enable fp8_fast_accum\n accumulator = tl.dot(a, b, acc=accumulator)\n else:\n accumulator += tl.dot(a, b)\n else:\n accumulator += tl.dot(a, b)\n # Advance the ptrs to the next K block.\n a_ptrs += BLOCK_SIZE_K * stride_ak\n b_ptrs += BLOCK_SIZE_K * stride_bk\n if HAS_BIAS:\n accumulator = accumulator + bias[None, :]\n if MUL_ROUTED_WEIGHT:\n moe_weight = tl.load(topk_weights_ptr + offs_token, mask=token_mask, other=0)\n accumulator = accumulator * moe_weight[:, None]\n if use_int8_w8a16:\n accumulator = (accumulator * b_scale).to(compute_type)\n elif use_fp8_w8a8 or use_int8_w8a8:\n if group_k > 0 and group_n > 0:\n accumulator = accumulator.to(compute_type)\n else:\n accumulator = (accumulator * a_scale * b_scale).to(compute_type)\n else:\n accumulator = accumulator.to(compute_type)\n\n # -----------------------------------------------------------\n # Write back the block of the output\n offs_cn = pid_n * BLOCK_SIZE_N + tl.arange(0, BLOCK_SIZE_N)\n c_ptrs = c_ptr + stride_cm * offs_token[:, None] + stride_cn * offs_cn[None, :]\n c_mask = token_mask[:, None] & (offs_cn[None, :] < N)\n tl.store(c_ptrs, accumulator, mask=c_mask)\n\n\ndef invoke_fused_moe_kernel(\n A: torch.Tensor,\n B: torch.Tensor,\n C: torch.Tensor,\n A_scale: torch.Tensor | None,\n B_scale: torch.Tensor | None,\n B_zp: torch.Tensor | None,\n topk_weights: torch.Tensor | None,\n sorted_token_ids: torch.Tensor,\n expert_ids: torch.Tensor,\n num_tokens_post_padded: torch.Tensor,\n mul_routed_weight: bool,\n top_k: int,\n config: dict[str, Any],\n compute_type: tl.dtype,\n use_fp8_w8a8: bool,\n use_int8_w8a8: bool,\n use_int8_w8a16: bool,\n use_int4_w4a16: bool,\n per_channel_quant: bool,\n block_shape: list[int] | None = None,\n B_bias: torch.Tensor | None = None,\n) -> None:\n assert topk_weights is not None or not mul_routed_weight\n assert topk_weights is None or topk_weights.stride(1) == 1\n assert sorted_token_ids.stride(0) == 1\n\n if use_fp8_w8a8 or use_int8_w8a8:\n assert B_scale is not None\n assert block_shape is None or triton.cdiv(\n B.size(-2), block_shape[0]\n ) == B_scale.size(-2)\n assert block_shape is None or triton.cdiv(\n B.size(-1), block_shape[1]\n ) == B_scale.size(-1)\n\n elif use_int8_w8a16 or use_int4_w4a16:\n assert B_scale is not None\n assert block_shape is None or block_shape[0] == 0\n else:\n assert A_scale is None\n assert B_scale is None\n\n M = A.size(0)\n num_tokens = M * top_k\n\n EM = sorted_token_ids.size(0)\n if A.size(0) < config[\"BLOCK_SIZE_M\"]:\n # optimize for small batch_size.\n # We assume that top_ids of each token is unique,\n # so num_valid_experts <= batch_size <= BLOCK_SIZE_M,\n # and we can skip some invalid blocks.\n EM = min(sorted_token_ids.size(0), A.size(0) * top_k * config[\"BLOCK_SIZE_M\"])\n grid = lambda META: (\n triton.cdiv(EM, META[\"BLOCK_SIZE_M\"])\n * triton.cdiv(B.size(1), META[\"BLOCK_SIZE_N\"]),\n )\n HAS_BIAS = B_bias is not None\n if (\n (use_int8_w8a16 or use_int4_w4a16)\n and block_shape is not None\n and block_shape[1] > 0\n ):\n assert B_scale is not None and B_scale.ndim == 3\n assert B_zp is None or B_zp.ndim == 3\n\n use_moe_wna16_cuda = should_moe_wna16_use_cuda(\n num_valid_tokens=num_tokens,\n group_size=block_shape[1],\n num_experts=B.size(0),\n bit=4 if use_int4_w4a16 else 8,\n )\n config = config.copy()\n config.update(\n get_moe_wna16_block_config(\n config=config,\n use_moe_wna16_cuda=use_moe_wna16_cuda,\n num_valid_tokens=num_tokens,\n size_k=A.size(1),\n size_n=B.size(1),\n num_experts=B.size(1),\n group_size=block_shape[1],\n real_top_k=top_k,\n block_size_m=config[\"BLOCK_SIZE_M\"],\n )\n )\n\n if use_moe_wna16_cuda:\n bit = 4 if use_int4_w4a16 else 8\n ops.moe_wna16_gemm(\n A,\n C,\n B,\n B_scale,\n B_zp,\n topk_weights if mul_routed_weight else None,\n sorted_token_ids,\n expert_ids,\n num_tokens_post_padded,\n top_k,\n config[\"BLOCK_SIZE_M\"],\n config[\"BLOCK_SIZE_N\"],\n config[\"BLOCK_SIZE_K\"],\n bit,\n )\n return\n fused_moe_kernel_gptq_awq[grid](\n A,\n B,\n C,\n B_scale,\n B_zp,\n topk_weights,\n sorted_token_ids,\n expert_ids,\n num_tokens_post_padded,\n B.size(1),\n A.size(1),\n EM,\n num_tokens,\n A.stride(0),\n A.stride(1),\n B.stride(0),\n B.stride(2),\n B.stride(1),\n C.stride(1),\n C.stride(2),\n B_scale.stride(0),\n B_scale.stride(2),\n B_scale.stride(1),\n B_zp.stride(0) if B_zp is not None else 0,\n B_zp.stride(2) if B_zp is not None else 0,\n B_zp.stride(1) if B_zp is not None else 0,\n block_k_diviable=A.size(1) % config[\"BLOCK_SIZE_K\"] == 0,\n group_size=block_shape[1],\n MUL_ROUTED_WEIGHT=mul_routed_weight,\n top_k=top_k,\n compute_type=compute_type,\n has_zp=B_zp is not None,\n use_int4_w4a16=use_int4_w4a16,\n use_int8_w8a16=use_int8_w8a16,\n **config,\n )\n else:\n config = config.copy()\n config[\"SPLIT_K\"] = 1\n BLOCK_SIZE_K = config.pop(\"BLOCK_SIZE_K\")\n if block_shape is not None:\n BLOCK_SIZE_K = min(BLOCK_SIZE_K, min(block_shape[0], block_shape[1]))\n fused_moe_kernel[grid](\n A,\n B,\n C,\n B_bias,\n A_scale,\n B_scale,\n topk_weights,\n sorted_token_ids,\n expert_ids,\n num_tokens_post_padded,\n B.size(1),\n B.size(2),\n EM,\n num_tokens,\n A.stride(0),\n A.stride(1),\n B.stride(0),\n B.stride(2),\n B.stride(1),\n C.stride(1),\n C.stride(2),\n A_scale.stride(0) if A_scale is not None and A_scale.ndim == 2 else 0,\n A_scale.stride(1) if A_scale is not None and A_scale.ndim == 2 else 0,\n B_scale.stride(0) if B_scale is not None and B_scale.ndim >= 2 else 0,\n B_scale.stride(2) if B_scale is not None and B_scale.ndim == 3 else 0,\n B_scale.stride(1) if B_scale is not None and B_scale.ndim >= 2 else 0,\n B_bias.stride(0) if B_bias is not None else 0,\n B_bias.stride(1) if B_bias is not None else 0,\n 0 if block_shape is None else block_shape[0],\n 0 if block_shape is None else block_shape[1],\n MUL_ROUTED_WEIGHT=mul_routed_weight,\n top_k=top_k,\n compute_type=compute_type,\n use_fp8_w8a8=use_fp8_w8a8,\n use_int8_w8a8=use_int8_w8a8,\n use_int8_w8a16=use_int8_w8a16,\n per_channel_quant=per_channel_quant,\n HAS_BIAS=HAS_BIAS,\n BLOCK_SIZE_K=BLOCK_SIZE_K,\n **config,\n )\n\n\n@triton.jit\ndef compute_identity_kernel(\n top_k: int,\n hidden_states_ptr: tl.tensor,\n expert_scales_ptr: tl.tensor,\n num_tokens: int,\n output_ptr: tl.tensor,\n hidden_dim: int,\n scales_stride: int,\n BLOCK_SIZE: tl.constexpr,\n) -> None:\n pid = tl.program_id(0)\n\n batch_id = pid // (hidden_dim // BLOCK_SIZE)\n dim_offset = pid % (hidden_dim // BLOCK_SIZE) * BLOCK_SIZE\n\n if batch_id >= num_tokens or dim_offset >= hidden_dim:\n return\n\n h = tl.load(\n hidden_states_ptr\n + batch_id * hidden_dim\n + dim_offset\n + tl.arange(0, BLOCK_SIZE),\n mask=(dim_offset + tl.arange(0, BLOCK_SIZE)) < hidden_dim,\n )\n\n result = tl.zeros([BLOCK_SIZE], dtype=tl.float32)\n for i in range(top_k):\n scale = tl.load(expert_scales_ptr + batch_id * scales_stride + i)\n result += h * scale\n\n tl.store(\n output_ptr + batch_id * hidden_dim + dim_offset + tl.arange(0, BLOCK_SIZE),\n result,\n mask=(dim_offset + tl.arange(0, BLOCK_SIZE)) < hidden_dim,\n )\n\n\ndef zero_experts_compute_triton(\n expert_indices: torch.Tensor,\n expert_scales: torch.Tensor,\n num_experts: int,\n zero_expert_type: str,\n hidden_states: torch.Tensor,\n) -> torch.Tensor:\n N = expert_indices.numel()\n top_k = expert_indices.size(-1)\n grid = lambda meta: (triton.cdiv(N, meta[\"BLOCK_SIZE\"]),)\n\n if zero_expert_type == \"identity\":\n zero_expert_mask = expert_indices < num_experts\n zero_expert_scales = expert_scales.clone()\n zero_expert_scales[zero_expert_mask] = 0.0\n\n normal_expert_mask = expert_indices >= num_experts\n expert_indices[normal_expert_mask] = 0\n expert_scales[normal_expert_mask] = 0.0\n\n output = torch.zeros_like(hidden_states).to(hidden_states.device)\n hidden_dim = hidden_states.size(-1)\n num_tokens = hidden_states.size(0)\n\n grid = lambda meta: (num_tokens * (hidden_dim // meta[\"BLOCK_SIZE\"]),)\n compute_identity_kernel[grid](\n top_k,\n hidden_states,\n zero_expert_scales,\n num_tokens,\n output,\n hidden_dim,\n zero_expert_scales.stride(0),\n BLOCK_SIZE=256,\n )\n\n return output\n\n\n# Adapted from: https://github.com/sgl-project/sglang/pull/2628\ndef get_config_file_name(\n E: int, N: int, dtype: str | None, block_shape: list[int] | None = None\n) -> str:\n device_name = current_platform.get_device_name().replace(\" \", \"_\")\n # Set device_name to H200 if a device from the H200 family is detected\n if \"H200\" in device_name.split(\"_\"):\n device_name = \"NVIDIA_H200\"\n dtype_selector = \"\" if not dtype else f\",dtype={dtype}\"\n block_shape_selector = (\n \"\" if not block_shape or not all(block_shape) else f\",block_shape={block_shape}\"\n ).replace(\" \", \"\")\n return f\"E={E},N={N},device_name={device_name}{dtype_selector}{block_shape_selector}.json\" # noqa: E501\n\n\n# Adapted from: https://github.com/sgl-project/sglang/pull/2628\n@functools.lru_cache\ndef get_moe_configs(\n E: int,\n N: int,\n dtype: str | None,\n block_n: int | None = None,\n block_k: int | None = None,\n) -> dict[int, Any] | None:\n \"\"\"\n Return optimized configurations for the fused MoE kernel.\n\n The return value will be a dictionary that maps an irregular grid of\n batch sizes to configurations of the fused_moe kernel. To evaluate the\n kernel on a given batch size bs, the closest batch size in the grid should\n be picked and the associated configuration chosen to invoke the kernel.\n \"\"\"\n\n # Avoid optimizing for the batch invariant case. Use default config\n if vllm_is_batch_invariant():\n return None\n\n # First look up if an optimized configuration is available in the configs\n # directory\n block_shape = [block_n, block_k] if block_n and block_k else None\n json_file_name = get_config_file_name(E, N, dtype, block_shape)\n\n config_file_paths = []\n\n # note that we prioritize user defined config\n user_defined_config_folder = envs.VLLM_TUNED_CONFIG_FOLDER\n if user_defined_config_folder is not None:\n user_defined_config_file_path = os.path.join(\n user_defined_config_folder, json_file_name\n )\n config_file_paths.append(user_defined_config_file_path)\n\n default_config_file_path = os.path.join(\n os.path.dirname(os.path.realpath(__file__)), \"configs\", json_file_name\n )\n config_file_paths.append(default_config_file_path)\n\n for config_file_path in config_file_paths:\n if os.path.exists(config_file_path):\n with open(config_file_path) as f:\n logger.info_once(\n \"Using configuration from %s for MoE layer.\",\n config_file_path,\n scope=\"global\",\n )\n # If a configuration has been found, return it\n tuned_config = json.load(f)\n # Delete triton_version from tuned_config\n tuned_config.pop(\"triton_version\", None)\n return {int(key): val for key, val in tuned_config.items()}\n\n # If no optimized configuration is available, we will use the default\n # configuration\n logger.warning(\n (\n \"Using default MoE config. Performance might be sub-optimal! \"\n \"Config file not found at %s\"\n ),\n config_file_paths,\n )\n return None\n\n\ndef get_moe_wna16_block_config(\n config: dict[str, int],\n use_moe_wna16_cuda: bool,\n num_valid_tokens: int,\n size_k: int,\n size_n: int,\n num_experts: int,\n group_size: int,\n real_top_k: int,\n block_size_m: int,\n):\n if \"BLOCK_SIZE_N\" in config and \"BLOCK_SIZE_K\" in config:\n # optimal block config is set\n return {}\n if not use_moe_wna16_cuda:\n # triton moe wna16 kernel\n if num_valid_tokens // real_top_k == 1:\n # if bs=1, use a smaller BLOCK_SIZE_N\n return {\"BLOCK_SIZE_N\": 32, \"BLOCK_SIZE_K\": 64}\n else:\n return {\"BLOCK_SIZE_N\": 64, \"BLOCK_SIZE_K\": 32}\n else:\n # cuda moe wna16 kernel\n # set default block_size 128, and increase them when num_blocks\n # is too large.\n block_size_n = 128\n block_size_k = 128\n if block_size_k <= group_size:\n block_size_k = group_size\n\n num_n_blocks = size_k // block_size_k\n num_k_blocks = size_n // block_size_k\n num_m_blocks = (\n num_valid_tokens + block_size_m - 1\n ) / block_size_m + num_experts\n if num_valid_tokens // real_top_k <= block_size_m:\n num_m_blocks = min(num_m_blocks, num_valid_tokens)\n num_blocks = num_m_blocks * num_n_blocks * num_k_blocks\n\n if size_k % 256 == 0 and num_blocks >= 256 and block_size_k < 256:\n block_size_k = 256\n num_blocks = num_blocks // (256 // block_size_k)\n\n if (\n num_m_blocks <= 16\n and size_k % (block_size_k * 2) == 0\n and size_k % (block_size_k * 2) == 0\n and block_size_k <= 512\n and num_blocks >= 512\n ):\n block_size_k = block_size_k * 2\n num_blocks = num_blocks // 2\n\n if num_blocks > 1024:\n block_size_n = 256\n num_n_blocks = num_n_blocks // 2\n num_blocks = num_blocks // 2\n\n if size_n <= 1024 and num_blocks >= 1024:\n # The kernel performance got much better with BLOCK_SIZE_N=1024\n # when num_blocks is large, event when N is small.\n # Not sure why, maybe it force the CUDA SM process only one block\n # at the same time.\n block_size_n = 1024\n\n return {\"BLOCK_SIZE_N\": block_size_n, \"BLOCK_SIZE_K\": block_size_k}\n\n\ndef should_moe_wna16_use_cuda(\n num_valid_tokens: int, group_size: int, num_experts: int, bit: int\n):\n return (\n current_platform.is_cuda()\n and bit == 4\n and group_size in [32, 64, 128]\n and num_valid_tokens / num_experts <= 6\n )\n\n\ndef get_default_config(\n M: int,\n E: int,\n N: int,\n K: int,\n topk: int,\n dtype: str | None,\n block_shape: list[int] | None = None,\n) -> dict[str, int]:\n if vllm_is_batch_invariant():\n config = {\n \"BLOCK_SIZE_M\": 64,\n \"BLOCK_SIZE_N\": 64,\n \"BLOCK_SIZE_K\": 32,\n \"GROUP_SIZE_M\": 8,\n \"SPLIT_K\": 1,\n }\n return config\n\n if dtype == \"fp8_w8a8\" and block_shape is not None:\n # Block-wise quant: BLOCK_SIZE_N must be divisible by block_shape[0]\n # BLOCK_SIZE_K must be divisible by block_shape[1]\n # num_stages=3 can cause triton.runtime.errors.OutOfResources\n # on ROCm, set it to 2 instead.\n config = {\n \"BLOCK_SIZE_M\": 64,\n \"BLOCK_SIZE_N\": block_shape[0],\n \"BLOCK_SIZE_K\": block_shape[1],\n \"GROUP_SIZE_M\": 32,\n \"SPLIT_K\": 1,\n \"num_warps\": 4,\n \"num_stages\": 3 if not current_platform.is_rocm() else 2,\n }\n elif dtype in [\"int4_w4a16\", \"int8_w8a16\"] and block_shape is not None:\n # moe wna16 kernels\n # only set BLOCK_SIZE_M\n # BLOCK_SIZE_N and BLOCK_SIZE_K would be set later\n bit = 4 if dtype == \"int4_w4a16\" else 8\n use_moe_wna16_cuda = should_moe_wna16_use_cuda(M * topk, block_shape[1], E, bit)\n if use_moe_wna16_cuda:\n config = {\"BLOCK_SIZE_M\": min(16, M), \"SPLIT_K\": 1}\n elif M <= 20:\n config = {\"BLOCK_SIZE_M\": 16, \"GROUP_SIZE_M\": 1, \"SPLIT_K\": 1}\n elif M <= 40:\n config = {\"BLOCK_SIZE_M\": 32, \"GROUP_SIZE_M\": 1, \"SPLIT_K\": 1}\n else:\n config = {\"BLOCK_SIZE_M\": 64, \"GROUP_SIZE_M\": 1, \"SPLIT_K\": 1}\n elif M <= E:\n config = {\n \"BLOCK_SIZE_M\": 16,\n \"BLOCK_SIZE_N\": 32,\n \"BLOCK_SIZE_K\": 64,\n \"GROUP_SIZE_M\": 1,\n \"SPLIT_K\": 1,\n }\n else:\n config = {\n \"BLOCK_SIZE_M\": 64,\n \"BLOCK_SIZE_N\": 64,\n \"BLOCK_SIZE_K\": 32,\n \"GROUP_SIZE_M\": 8,\n \"SPLIT_K\": 1,\n }\n return config\n\n\ndef try_get_optimal_moe_config(\n w1_shape: tuple[int, ...],\n w2_shape: tuple[int, ...],\n top_k: int,\n dtype: str | None,\n M: int,\n block_shape: list[int] | None = None,\n) -> dict[str, int]:\n from vllm.model_executor.layers.fused_moe import get_config\n\n override_config = get_config()\n if override_config:\n config = override_config\n else:\n # First try to load optimal config from the file\n E, _, N = w2_shape\n if dtype == \"int4_w4a16\":\n N = N * 2\n block_n = block_shape[0] if block_shape else 0\n block_k = block_shape[1] if block_shape else 0\n configs = get_moe_configs(E, N, dtype, block_n, block_k)\n\n if configs:\n # If an optimal configuration map has been found, look up the\n # optimal config\n config = configs[min(configs.keys(), key=lambda x: abs(x - M))]\n else:\n # Else use the default config\n config = get_default_config(M, E, N, w1_shape[2], top_k, dtype, block_shape)\n return config\n\n\ndef vllm_topk_softmax(\n topk_weights: torch.Tensor,\n topk_indices: torch.Tensor,\n token_expert_indices: torch.Tensor,\n gating_output: torch.Tensor,\n renormalize: bool,\n) -> tuple[torch.Tensor, ...]:\n ops.topk_softmax(\n topk_weights,\n topk_indices,\n token_expert_indices,\n gating_output,\n renormalize,\n )\n\n return topk_weights, topk_indices\n\n\ndef dispatch_topk_func(\n use_rocm_aiter: bool = False,\n) -> Callable[..., tuple[torch.Tensor, ...]]:\n if use_rocm_aiter:\n return rocm_aiter_ops.topk_softmax\n return vllm_topk_softmax\n\n\ndef fused_topk(\n hidden_states: torch.Tensor,\n gating_output: torch.Tensor,\n topk: int,\n renormalize: bool,\n indices_type: torch.dtype | None = None,\n) -> tuple[torch.Tensor, torch.Tensor, torch.Tensor]:\n assert hidden_states.size(0) == gating_output.size(0), \"Number of tokens mismatch\"\n\n M, _ = hidden_states.size()\n\n topk_weights = torch.empty(\n M, topk, dtype=torch.float32, device=hidden_states.device\n )\n topk_ids = torch.empty(\n M,\n topk,\n dtype=torch.int32 if indices_type is None else indices_type,\n device=hidden_states.device,\n )\n token_expert_indices = torch.empty(\n M, topk, dtype=torch.int32, device=hidden_states.device\n )\n\n topk_func = dispatch_topk_func(use_rocm_aiter=rocm_aiter_ops.is_fused_moe_enabled())\n topk_weights, topk_ids = topk_func(\n topk_weights, topk_ids, token_expert_indices, gating_output, renormalize\n )\n\n return topk_weights, topk_ids, token_expert_indices\n\n\ndef fused_topk_bias(\n hidden_states: torch.Tensor,\n gating_output: torch.Tensor,\n e_score_correction_bias: torch.Tensor,\n topk: int,\n renormalize: bool,\n):\n n_routed_experts = gating_output.shape[-1]\n scores = gating_output.softmax(dim=-1)\n scores_for_choice = scores.view(\n -1, n_routed_experts\n ) + e_score_correction_bias.unsqueeze(0)\n\n # For batch invariance, use sorted=True to ensure deterministic expert selection\n use_sorted = vllm_is_batch_invariant()\n topk_indices = torch.topk(scores_for_choice, k=topk, dim=-1, sorted=use_sorted)[1]\n topk_weights = scores.gather(1, topk_indices)\n if renormalize:\n topk_weights = topk_weights / topk_weights.sum(dim=-1, keepdim=True)\n return topk_weights.to(torch.float32), topk_indices.to(torch.int32)\n\n\n# This is used by the Deepseek-V2 and Deepseek-V3 model\n@torch.compile(\n dynamic=True,\n backend=current_platform.simple_compile_backend,\n options=maybe_disable_graph_partition(current_platform.simple_compile_backend),\n)\ndef grouped_topk(\n hidden_states: torch.Tensor,\n gating_output: torch.Tensor,\n topk: int,\n renormalize: bool,\n num_expert_group: int = 0,\n topk_group: int = 0,\n scoring_func: str = \"softmax\",\n routed_scaling_factor: float = 1.0,\n e_score_correction_bias: torch.Tensor | None = None,\n) -> tuple[torch.Tensor, torch.Tensor]:\n if (\n envs.VLLM_USE_FUSED_MOE_GROUPED_TOPK\n and current_platform.is_cuda()\n and num_expert_group <= 32\n and topk <= 32\n and e_score_correction_bias is not None\n ):\n return fused_grouped_topk(\n hidden_states=hidden_states,\n gating_output=gating_output,\n topk=topk,\n renormalize=renormalize,\n e_score_correction_bias=e_score_correction_bias,\n num_expert_group=num_expert_group,\n topk_group=topk_group,\n scoring_func=scoring_func,\n routed_scaling_factor=routed_scaling_factor,\n )\n\n assert hidden_states.size(0) == gating_output.size(0), \"Number of tokens mismatch\"\n\n if scoring_func == \"softmax\":\n scores = torch.softmax(gating_output, dim=-1)\n elif scoring_func == \"sigmoid\":\n scores = gating_output.sigmoid()\n else:\n raise ValueError(f\"Unsupported scoring function: {scoring_func}\")\n\n num_token = scores.size(0)\n if e_score_correction_bias is not None:\n # Store original scores before applying correction bias. We use biased\n # scores for expert selection but original scores for routing weights\n original_scores = scores\n scores = scores + e_score_correction_bias.unsqueeze(0)\n group_scores = (\n scores.view(num_token, num_expert_group, -1).topk(2, dim=-1)[0].sum(dim=-1)\n )\n else:\n group_scores = (\n scores.view(num_token, num_expert_group, -1).max(dim=-1).values\n ) # [n, n_group]\n\n # For batch invariance, use sorted=True to ensure deterministic expert selection\n use_sorted = vllm_is_batch_invariant()\n group_idx = torch.topk(group_scores, k=topk_group, dim=-1, sorted=use_sorted)[\n 1\n ] # [n, top_k_group]\n group_mask = torch.zeros_like(group_scores) # [n, n_group]\n group_mask.scatter_(1, group_idx, 1) # [n, n_group]\n score_mask = (\n group_mask.unsqueeze(-1)\n .expand(num_token, num_expert_group, scores.size(-1) // num_expert_group)\n .reshape(num_token, -1)\n ) # [n, e]\n tmp_scores = scores.masked_fill(~score_mask.bool(), float(\"-inf\")) # [n, e]\n\n if e_score_correction_bias is not None:\n topk_ids = torch.topk(tmp_scores, k=topk, dim=-1, sorted=use_sorted)[1]\n # Use original unbiased scores for the routing weights\n topk_weights = original_scores.gather(1, topk_ids)\n else:\n topk_weights, topk_ids = torch.topk(\n tmp_scores, k=topk, dim=-1, sorted=use_sorted\n )\n\n if renormalize:\n topk_weights = topk_weights / topk_weights.sum(dim=-1, keepdim=True)\n\n if routed_scaling_factor != 1.0:\n topk_weights = topk_weights * routed_scaling_factor\n return topk_weights.to(torch.float32), topk_ids.to(torch.int32)\n\n\n@torch.compile(dynamic=True, backend=current_platform.simple_compile_backend)\ndef eplb_map_to_physical_and_record(\n topk_ids: torch.Tensor,\n expert_load_view: torch.Tensor,\n logical_to_physical_map: torch.Tensor,\n logical_replica_count: torch.Tensor,\n) -> torch.Tensor:\n \"\"\"\n Map the logical expert ids to physical expert ids\n and record the expert load metrics.\n\n This will select a pseudo-random replica for each logical expert.\n Only used for EPLB.\n\n Args:\n topk_ids: The logical expert ids.\n expert_load_view: The expert load view.\n logical_to_physical_map: The logical to physical map.\n logical_replica_count: The logical replica count.\n\n Returns:\n The physical expert ids.\n \"\"\"\n\n # 1. Convert the logical expert ids to physical expert ids\n # Directly select a random replica for each logical expert\n\n # In case `indices_type` is not `torch.long` or `torch.int`,\n # e.g. `torch.uint32` as required by dispatch/combine kernels\n topk_ids_long = topk_ids.long()\n # Use (token position) modulo (replica count)\n # to deterministically choose a replica\n replica_count = logical_replica_count[topk_ids_long]\n # Flatten-position based index, reshaped back to `topk_ids` shape\n pos_indices = torch.arange(\n topk_ids.numel(), device=topk_ids.device, dtype=torch.long\n ).reshape_as(topk_ids)\n # Compute pseudo-random indices by modulo\n replica_indices = (pos_indices % replica_count).unsqueeze(-1)\n physical_ids = (\n logical_to_physical_map[topk_ids_long].gather(-1, replica_indices).squeeze(-1)\n )\n\n topk_ids = physical_ids\n\n # 2. Record expert load metrics.\n\n # TODO(bowen): When using `FusedMoEModularKernel`, this\n # can be done in a more unified way, since\n # `FusedMoEPrepareAndFinalize` will return the expert\n # token count, in some cases directly from the kernel.\n # However, now there are many code paths not using\n # the modular kernel, e.g. calling `fused_experts`,\n # so we decide to keep the logic here.\n #\n # If later refactor moved all the MoE kernel calls\n # to the modular kernel, we can move this logic there\n # to achieve better efficiency.\n\n # `expert_load_view`: (num_physical_experts,)\n\n # `torch.bincount` is not compilable, so use `scatter_add_` instead.\n topk_ids_flatten = topk_ids.flatten()\n expert_load_view.scatter_add_(\n dim=0,\n index=topk_ids_flatten.long(),\n src=torch.ones_like(topk_ids_flatten).to(expert_load_view),\n )\n return topk_ids\n\n\ndef fused_grouped_topk(\n hidden_states: torch.Tensor,\n gating_output: torch.Tensor,\n topk: int,\n renormalize: bool,\n e_score_correction_bias: torch.Tensor,\n num_expert_group: int = 0,\n topk_group: int = 0,\n scoring_func: str = \"softmax\",\n routed_scaling_factor: float = 1.0,\n) -> tuple[torch.Tensor, torch.Tensor]:\n assert hidden_states.size(0) == gating_output.size(0), \"Number of tokens mismatch\"\n\n if scoring_func == \"sigmoid\":\n # Fully fused kernel path for sigmoid\n topk_values, topk_indices = ops.grouped_topk(\n gating_output, # raw logits\n num_expert_group,\n topk_group,\n topk,\n renormalize,\n routed_scaling_factor,\n e_score_correction_bias.to(gating_output.dtype),\n 1, # scoring_func=1 for sigmoid\n )\n elif scoring_func == \"softmax\":\n # Apply softmax in Python, then use fused kernel\n # TODO: Add support for softmax in kernel\n scores = torch.softmax(gating_output, dim=-1)\n topk_values, topk_indices = ops.grouped_topk(\n scores, # pre-computed scores\n num_expert_group,\n topk_group,\n topk,\n renormalize,\n routed_scaling_factor,\n e_score_correction_bias.to(gating_output.dtype),\n 0, # scoring_func=0 (no activation, scores already computed)\n )\n else:\n raise ValueError(f\"Unsupported scoring function: {scoring_func}\")\n\n # Fused kernel outputs float32 values and int32 indices directly\n return topk_values, topk_indices\n\n\ndef inplace_fused_experts(\n hidden_states: torch.Tensor,\n w1: torch.Tensor,\n w2: torch.Tensor,\n topk_weights: torch.Tensor,\n topk_ids: torch.Tensor,\n activation: str = \"silu\",\n apply_router_weight_on_input: bool = False,\n use_fp8_w8a8: bool = False,\n use_int8_w8a8: bool = False,\n use_int8_w8a16: bool = False,\n use_int4_w4a16: bool = False,\n ocp_mx_scheme: str | None = None,\n per_channel_quant: bool = False,\n global_num_experts: int = -1,\n expert_map: torch.Tensor | None = None,\n w1_scale: torch.Tensor | None = None,\n w2_scale: torch.Tensor | None = None,\n w1_zp: torch.Tensor | None = None,\n w2_zp: torch.Tensor | None = None,\n a1_scale: torch.Tensor | None = None,\n a2_scale: torch.Tensor | None = None,\n block_shape: list[int] | None = None,\n w1_bias: torch.Tensor | None = None,\n w2_bias: torch.Tensor | None = None,\n) -> None:\n fused_experts_impl(\n hidden_states,\n w1,\n w2,\n topk_weights,\n topk_ids,\n True,\n activation,\n apply_router_weight_on_input,\n use_fp8_w8a8,\n use_int8_w8a8,\n use_int8_w8a16,\n use_int4_w4a16,\n ocp_mx_scheme,\n per_channel_quant,\n global_num_experts,\n expert_map,\n w1_scale,\n w2_scale,\n w1_zp,\n w2_zp,\n a1_scale,\n a2_scale,\n block_shape,\n w1_bias,\n w2_bias,\n )\n\n\ndef inplace_fused_experts_fake(\n hidden_states: torch.Tensor,\n w1: torch.Tensor,\n w2: torch.Tensor,\n topk_weights: torch.Tensor,\n topk_ids: torch.Tensor,\n activation: str = \"silu\",\n apply_router_weight_on_input: bool = False,\n use_fp8_w8a8: bool = False,\n use_int8_w8a8: bool = False,\n use_int8_w8a16: bool = False,\n use_int4_w4a16: bool = False,\n ocp_mx_scheme: str | None = None,\n per_channel_quant: bool = False,\n global_num_experts: int = -1,\n expert_map: torch.Tensor | None = None,\n w1_scale: torch.Tensor | None = None,\n w2_scale: torch.Tensor | None = None,\n w1_zp: torch.Tensor | None = None,\n w2_zp: torch.Tensor | None = None,\n a1_scale: torch.Tensor | None = None,\n a2_scale: torch.Tensor | None = None,\n block_shape: list[int] | None = None,\n w1_bias: torch.Tensor | None = None,\n w2_bias: torch.Tensor | None = None,\n) -> None:\n pass\n\n\ndirect_register_custom_op(\n op_name=\"inplace_fused_experts\",\n op_func=inplace_fused_experts,\n mutates_args=[\"hidden_states\"],\n fake_impl=inplace_fused_experts_fake,\n tags=(\n ()\n if is_torch_equal_or_newer(\"2.7.0\")\n else (torch.Tag.needs_fixed_stride_order,)\n ),\n)\n\n\ndef outplace_fused_experts(\n hidden_states: torch.Tensor,\n w1: torch.Tensor,\n w2: torch.Tensor,\n topk_weights: torch.Tensor,\n topk_ids: torch.Tensor,\n activation: str = \"silu\",\n apply_router_weight_on_input: bool = False,\n use_fp8_w8a8: bool = False,\n use_int8_w8a8: bool = False,\n use_int8_w8a16: bool = False,\n use_int4_w4a16: bool = False,\n ocp_mx_scheme: str | None = None,\n per_channel_quant: bool = False,\n global_num_experts: int = -1,\n expert_map: torch.Tensor | None = None,\n w1_scale: torch.Tensor | None = None,\n w2_scale: torch.Tensor | None = None,\n w1_zp: torch.Tensor | None = None,\n w2_zp: torch.Tensor | None = None,\n a1_scale: torch.Tensor | None = None,\n a2_scale: torch.Tensor | None = None,\n block_shape: list[int] | None = None,\n w1_bias: torch.Tensor | None = None,\n w2_bias: torch.Tensor | None = None,\n) -> torch.Tensor:\n return fused_experts_impl(\n hidden_states,\n w1,\n w2,\n topk_weights,\n topk_ids,\n False,\n activation,\n apply_router_weight_on_input,\n use_fp8_w8a8,\n use_int8_w8a8,\n use_int8_w8a16,\n use_int4_w4a16,\n ocp_mx_scheme,\n per_channel_quant,\n global_num_experts,\n expert_map,\n w1_scale,\n w2_scale,\n w1_zp,\n w2_zp,\n a1_scale,\n a2_scale,\n block_shape,\n w1_bias,\n w2_bias,\n )\n\n\ndef outplace_fused_experts_fake(\n hidden_states: torch.Tensor,\n w1: torch.Tensor,\n w2: torch.Tensor,\n topk_weights: torch.Tensor,\n topk_ids: torch.Tensor,\n activation: str = \"silu\",\n use_fp8_w8a8: bool = False,\n use_int8_w8a8: bool = False,\n use_int8_w8a16: bool = False,\n use_int4_w4a16: bool = False,\n ocp_mx_scheme: str | None = None,\n per_channel_quant: bool = False,\n global_num_experts: int = -1,\n expert_map: torch.Tensor | None = None,\n w1_scale: torch.Tensor | None = None,\n w2_scale: torch.Tensor | None = None,\n w1_zp: torch.Tensor | None = None,\n w2_zp: torch.Tensor | None = None,\n a1_scale: torch.Tensor | None = None,\n a2_scale: torch.Tensor | None = None,\n block_shape: list[int] | None = None,\n w1_bias: torch.Tensor | None = None,\n w2_bias: torch.Tensor | None = None,\n) -> torch.Tensor:\n return torch.empty_like(hidden_states)\n\n\ndirect_register_custom_op(\n op_name=\"outplace_fused_experts\",\n op_func=outplace_fused_experts,\n fake_impl=outplace_fused_experts_fake,\n tags=(\n ()\n if is_torch_equal_or_newer(\"2.7.0\")\n else (torch.Tag.needs_fixed_stride_order,)\n ),\n)\n\n\ndef torch_vllm_inplace_fused_experts(**kwargs) -> torch.Tensor:\n torch.ops.vllm.inplace_fused_experts(**kwargs)\n hidden_states = kwargs[\"hidden_states\"]\n return hidden_states\n\n\ndef torch_vllm_outplace_fused_experts(**kwargs) -> torch.Tensor:\n return torch.ops.vllm.outplace_fused_experts(**kwargs)\n\n\ndef dispatch_fused_experts_func(inplace: bool) -> Callable[..., torch.Tensor]:\n if inplace and not disable_inplace():\n return torch_vllm_inplace_fused_experts\n return torch_vllm_outplace_fused_experts\n\n\n# TODO (bnell): replace this with modular op. Can get rid of inplace/outplace\n# torch ops.\ndef fused_experts(\n hidden_states: torch.Tensor,\n w1: torch.Tensor,\n w2: torch.Tensor,\n topk_weights: torch.Tensor,\n topk_ids: torch.Tensor,\n inplace: bool = False,\n activation: str = \"silu\",\n apply_router_weight_on_input: bool = False,\n global_num_experts: int = -1,\n expert_map: torch.Tensor | None = None,\n quant_config: FusedMoEQuantConfig | None = None,\n allow_deep_gemm: bool = False,\n allow_cutlass_block_scaled_grouped_gemm: bool = False,\n) -> torch.Tensor:\n if quant_config is None:\n quant_config = FUSED_MOE_UNQUANTIZED_CONFIG\n use_fp8_w8a8 = quant_config.use_fp8_w8a8\n\n # For now, disable DeepGemm for small N (<= 512) until better\n # permute/unpermute ops are available.\n # However, on B200, we use DeepGemm for all cases because they only support\n # E8M0 scale, which means we requantize the weight and input to the specific\n # scale. Fallen back to cutlass or triton for some cases would cause\n # accuracy issue.\n if (\n allow_deep_gemm\n and quant_config.use_fp8_w8a8\n and (is_deep_gemm_e8m0_used() or _valid_deep_gemm(hidden_states, w1, w2))\n ):\n assert quant_config is not None\n assert apply_router_weight_on_input is False\n return deep_gemm_moe_fp8(\n hidden_states=hidden_states,\n w1=w1,\n w2=w2,\n topk_weights=topk_weights,\n topk_ids=topk_ids,\n inplace=inplace,\n activation=activation,\n global_num_experts=global_num_experts,\n expert_map=expert_map,\n w1_scale=quant_config.w1_scale,\n w2_scale=quant_config.w2_scale,\n a1_scale=quant_config.a1_scale,\n a2_scale=quant_config.a2_scale,\n apply_router_weight_on_input=apply_router_weight_on_input,\n )\n elif (\n allow_cutlass_block_scaled_grouped_gemm\n and use_fp8_w8a8\n and _valid_cutlass_block_scaled_grouped_gemm(\n w1, w2, inplace, activation, apply_router_weight_on_input, expert_map\n )\n ):\n assert quant_config is not None\n return run_cutlass_block_scaled_fused_experts(\n a=hidden_states,\n w1=w1,\n w2=w2,\n w1_scale=quant_config.w1_scale,\n w2_scale=quant_config.w2_scale,\n topk_weights=topk_weights,\n topk_ids=topk_ids,\n )\n else:\n return dispatch_fused_experts_func(inplace)(\n hidden_states=hidden_states,\n w1=w1,\n w2=w2,\n topk_weights=topk_weights,\n topk_ids=topk_ids,\n activation=activation,\n apply_router_weight_on_input=apply_router_weight_on_input,\n use_fp8_w8a8=quant_config.use_fp8_w8a8,\n use_int8_w8a8=quant_config.use_int8_w8a8,\n use_int8_w8a16=quant_config.use_int8_w8a16,\n use_int4_w4a16=quant_config.use_int4_w4a16,\n ocp_mx_scheme=quant_config.ocp_mx_scheme,\n per_channel_quant=quant_config.per_act_token_quant,\n global_num_experts=global_num_experts,\n expert_map=expert_map,\n w1_scale=quant_config.w1_scale,\n w2_scale=quant_config.w2_scale,\n w1_zp=quant_config.w1_zp,\n w2_zp=quant_config.w2_zp,\n a1_scale=quant_config.a1_scale,\n a2_scale=quant_config.a2_scale,\n block_shape=quant_config.block_shape,\n w1_bias=quant_config.w1_bias,\n w2_bias=quant_config.w2_bias,\n )\n\n\nSILU_NO_MUL: str = activation_without_mul(\"silu\")\nGELU_NO_MUL: str = activation_without_mul(\"gelu\")\nRELU2_NO_MUL: str = activation_without_mul(\"relu2\")\n\n\ndef _get_config_quant_dtype(\n use_fp8_w8a8: bool,\n use_int8_w8a8: bool,\n ocp_mx_scheme: str | None,\n) -> None | torch.dtype | str:\n \"\"\"\n Get the quantization type based on the quantization strategy flags.\n We don't have a quant_config at this point so we need to work backwards.\n A return type of None means no quantization is required because the\n input is unquantized or has been quantized prior to calling\n fused_experts_impl.\n \"\"\"\n if use_fp8_w8a8:\n return torch.float8_e4m3fn\n elif use_int8_w8a8:\n return torch.int8\n elif ocp_mx_scheme == \"w_mxfp4_a_mxfp4\":\n return \"mxfp4\"\n elif ocp_mx_scheme in {\"w_mxfp4_a_mxfp6_e3m2\", \"w_mxfp6_e3m2_a_mxfp6_e3m2\"}:\n return \"mxfp6_e3m2\"\n elif ocp_mx_scheme in {\"w_mxfp4_a_mxfp6_e2m3\", \"w_mxfp6_e2m3_a_mxfp6_e2m3\"}:\n return \"mxfp6_e2m3\"\n return None\n\n\ndef fused_experts_impl(\n hidden_states: torch.Tensor,\n w1: torch.Tensor,\n w2: torch.Tensor,\n topk_weights: torch.Tensor,\n topk_ids: torch.Tensor,\n inplace: bool = False,\n activation: str = \"silu\",\n apply_router_weight_on_input: bool = False,\n use_fp8_w8a8: bool = False,\n use_int8_w8a8: bool = False,\n use_int8_w8a16: bool = False,\n use_int4_w4a16: bool = False,\n ocp_mx_scheme: str | None = None,\n per_channel_quant: bool = False,\n global_num_experts: int = -1,\n expert_map: torch.Tensor | None = None,\n w1_scale: torch.Tensor | None = None,\n w2_scale: torch.Tensor | None = None,\n w1_zp: torch.Tensor | None = None,\n w2_zp: torch.Tensor | None = None,\n a1_scale: torch.Tensor | None = None,\n a2_scale: torch.Tensor | None = None,\n block_shape: list[int] | None = None,\n w1_bias: torch.Tensor | None = None,\n w2_bias: torch.Tensor | None = None,\n) -> torch.Tensor:\n # Check constraints.\n if use_int4_w4a16:\n assert hidden_states.size(1) // 2 == w1.size(2), \"Hidden size mismatch\"\n elif ocp_mx_scheme is not None:\n if ocp_mx_scheme in {\n \"w_mxfp4_a_mxfp4\",\n \"w_mxfp4_a_mxfp6_e3m2\",\n \"w_mxfp4_a_mxfp6_e2m3\",\n }:\n # 16bit activation and fp4x2 packed weight\n assert hidden_states.size(1) == w1.size(2) * 2, \"hidden size mismatch\"\n elif ocp_mx_scheme in {\n \"w_mxfp6_e3m2_a_mxfp6_e3m2\",\n \"w_mxfp6_e2m3_a_mxfp6_e2m3\",\n }:\n assert hidden_states.size(1) == (w1.size(2) * 4) // 3, (\n \"hidden size mismatch\"\n )\n else:\n raise NotImplementedError(f\"Unsupported ocp_mx_scheme={ocp_mx_scheme}\")\n else:\n assert hidden_states.size(1) == w1.size(2), (\n f\"Hidden size mismatch {hidden_states.size(1)} != {w1.size(2)}\"\n )\n\n assert topk_weights.size() == topk_ids.size(), \"topk shape mismatch\"\n assert hidden_states.is_contiguous(), \"Hidden_states must be contiguous\"\n assert w1.stride(-1) == 1, \"Stride of last dimension must be 1\"\n assert w2.stride(-1) == 1, \"Stride of last dimension must be 1\"\n assert hidden_states.dtype in [torch.float32, torch.float16, torch.bfloat16]\n\n num_tokens = hidden_states.size(0)\n E, N, _ = w1.size()\n K = w2.size(1)\n if global_num_experts == -1:\n global_num_experts = E\n top_k_num = topk_ids.size(1)\n # We execute the fused_moe kernel in chunks to circumvent this issue:\n # https://github.com/vllm-project/vllm/issues/5938\n CHUNK_SIZE = envs.VLLM_FUSED_MOE_CHUNK_SIZE\n M = min(num_tokens, CHUNK_SIZE)\n\n config_dtype = _get_config_dtype_str(\n use_fp8_w8a8=use_fp8_w8a8,\n use_int8_w8a16=use_int8_w8a16,\n use_int4_w4a16=use_int4_w4a16,\n ocp_mx_scheme=ocp_mx_scheme,\n dtype=hidden_states.dtype,\n )\n\n # Note: for use_int8_w8a16 or use_int4_w4a16, the activations are\n # quantized prior to calling fused_experts.\n quant_dtype = _get_config_quant_dtype(\n use_fp8_w8a8=use_fp8_w8a8,\n use_int8_w8a8=use_int8_w8a8,\n ocp_mx_scheme=ocp_mx_scheme,\n )\n\n get_config_func = functools.partial(\n try_get_optimal_moe_config,\n w1.size(),\n w2.size(),\n top_k_num,\n config_dtype,\n block_shape=block_shape,\n )\n\n config = get_config_func(M)\n\n # We can reuse the memory between these because by the time we need\n # cache3, we're done with cache1\n cache13 = torch.empty(\n M * top_k_num * max(N, K),\n device=hidden_states.device,\n dtype=hidden_states.dtype,\n )\n intermediate_cache1 = cache13[: M * top_k_num * N].view(M, top_k_num, N)\n intermediate_cache3 = cache13[: M * top_k_num * K].view(M, top_k_num, K)\n\n # This needs separate memory since it's used concurrently with cache1\n intermediate_cache2 = torch.empty(\n (M * top_k_num, N // 2), device=hidden_states.device, dtype=hidden_states.dtype\n )\n\n if hidden_states.dtype == torch.bfloat16:\n compute_type = tl.bfloat16\n elif hidden_states.dtype == torch.float16:\n compute_type = tl.float16\n elif hidden_states.dtype == torch.float32:\n compute_type = tl.float32\n else:\n raise ValueError(f\"Unsupported compute_type: {hidden_states.dtype}\")\n\n if inplace and not disable_inplace():\n out_hidden_states = hidden_states\n else:\n out_hidden_states = torch.empty_like(hidden_states)\n\n if ocp_mx_scheme is not None:\n # TODO: On platforms for which `current_platform.supports_mx()` is True\n # and for which we have a native OCP mx fused MOE kernel,\n # this dequantization step should not be done.\n if ocp_mx_scheme in {\n OCP_MX_Scheme.w_mxfp4_a_mxfp4,\n OCP_MX_Scheme.w_mxfp4_a_mxfp6_e3m2,\n OCP_MX_Scheme.w_mxfp4_a_mxfp6_e2m3,\n }:\n # Weight has to be dequantized for mxfp4 emulation.\n w1 = dequant_mxfp4(w1, w1_scale, hidden_states.dtype)\n w1_scale = None\n w2 = dequant_mxfp4(w2, w2_scale, hidden_states.dtype)\n w2_scale = None\n elif ocp_mx_scheme == OCP_MX_Scheme.w_mxfp6_e3m2_a_mxfp6_e3m2:\n w1 = dequant_mxfp6(\n w1, w1_scale, quant_dtype=\"fp6_e3m2\", float_dtype=hidden_states.dtype\n )\n w1_scale = None\n w2 = dequant_mxfp6(\n w2, w2_scale, quant_dtype=\"fp6_e3m2\", float_dtype=hidden_states.dtype\n )\n w2_scale = None\n elif ocp_mx_scheme == OCP_MX_Scheme.w_mxfp6_e2m3_a_mxfp6_e2m3:\n w1 = dequant_mxfp6(\n w1, w1_scale, quant_dtype=\"fp6_e2m3\", float_dtype=hidden_states.dtype\n )\n w1_scale = None\n w2 = dequant_mxfp6(\n w2, w2_scale, quant_dtype=\"fp6_e2m3\", float_dtype=hidden_states.dtype\n )\n w2_scale = None\n else:\n raise NotImplementedError(f\"Unsupported ocp_mx_scheme={ocp_mx_scheme}\")\n\n for chunk in range((num_tokens // CHUNK_SIZE) + 1):\n begin_chunk_idx, end_chunk_idx = (\n chunk * CHUNK_SIZE,\n min((chunk + 1) * CHUNK_SIZE, num_tokens),\n )\n curr_hidden_states = hidden_states[begin_chunk_idx:end_chunk_idx]\n tokens_in_chunk, _ = curr_hidden_states.size()\n\n if tokens_in_chunk == 0:\n break\n\n if tokens_in_chunk < CHUNK_SIZE and chunk > 0:\n # Adjust the intermediate cache size and config for the last\n # chunk. Note that in most cases we only have one chunk\n # so the cache size and config are already set correctly and\n # do not need to be adjusted.\n intermediate_cache1 = intermediate_cache1[:tokens_in_chunk]\n intermediate_cache2 = intermediate_cache2[\n : tokens_in_chunk * topk_ids.size(1)\n ]\n intermediate_cache3 = intermediate_cache3[:tokens_in_chunk]\n config = get_config_func(tokens_in_chunk)\n\n curr_topk_ids = topk_ids[begin_chunk_idx:end_chunk_idx]\n curr_topk_weights = topk_weights[begin_chunk_idx:end_chunk_idx]\n qcurr_hidden_states, a1q_scale = moe_kernel_quantize_input(\n A=curr_hidden_states,\n A_scale=a1_scale,\n quant_dtype=quant_dtype,\n per_act_token_quant=per_channel_quant,\n block_shape=block_shape,\n )\n\n sorted_token_ids, expert_ids, num_tokens_post_padded = moe_align_block_size(\n curr_topk_ids, config[\"BLOCK_SIZE_M\"], global_num_experts, expert_map\n )\n\n invoke_fused_moe_kernel(\n qcurr_hidden_states,\n w1,\n intermediate_cache1,\n a1q_scale,\n w1_scale,\n w1_zp,\n curr_topk_weights,\n sorted_token_ids,\n expert_ids,\n num_tokens_post_padded,\n apply_router_weight_on_input,\n top_k_num,\n config,\n compute_type=compute_type,\n use_fp8_w8a8=use_fp8_w8a8,\n use_int8_w8a8=use_int8_w8a8,\n use_int8_w8a16=use_int8_w8a16,\n use_int4_w4a16=use_int4_w4a16,\n per_channel_quant=per_channel_quant,\n block_shape=block_shape,\n B_bias=w1_bias,\n )\n\n # Activation function with multiplication\n if activation == \"silu\":\n torch.ops._C.silu_and_mul(\n intermediate_cache2, intermediate_cache1.view(-1, N)\n )\n elif activation == \"gelu\":\n torch.ops._C.gelu_and_mul(\n intermediate_cache2, intermediate_cache1.view(-1, N)\n )\n elif activation == \"swigluoai\":\n # alpha = 1.702, limit = 7.0\n torch.ops._C.swigluoai_and_mul(\n intermediate_cache2, intermediate_cache1.view(-1, N)\n )\n # Activation function without multiplication\n elif activation == SILU_NO_MUL:\n intermediate_cache2 = F.silu(intermediate_cache1.view(-1, N))\n elif activation == GELU_NO_MUL:\n intermediate_cache2 = F.gelu(intermediate_cache1.view(-1, N))\n elif activation == RELU2_NO_MUL:\n intermediate_cache2 = torch.square(F.relu(intermediate_cache1.view(-1, N)))\n else:\n raise ValueError(f\"Unsupported FusedMoe activation: {activation}.\")\n\n qintermediate_cache2, a2q_scale = moe_kernel_quantize_input(\n A=intermediate_cache2,\n A_scale=a2_scale,\n quant_dtype=quant_dtype,\n per_act_token_quant=per_channel_quant,\n block_shape=block_shape,\n )\n\n invoke_fused_moe_kernel(\n qintermediate_cache2,\n w2,\n intermediate_cache3,\n a2q_scale,\n w2_scale,\n w2_zp,\n curr_topk_weights,\n sorted_token_ids,\n expert_ids,\n num_tokens_post_padded,\n not apply_router_weight_on_input,\n 1,\n config,\n compute_type=compute_type,\n use_fp8_w8a8=use_fp8_w8a8,\n use_int8_w8a8=use_int8_w8a8,\n use_int8_w8a16=use_int8_w8a16,\n use_int4_w4a16=use_int4_w4a16,\n per_channel_quant=per_channel_quant,\n block_shape=block_shape,\n B_bias=w2_bias,\n )\n\n ops.moe_sum(\n intermediate_cache3.view(*intermediate_cache3.size()),\n out_hidden_states[begin_chunk_idx:end_chunk_idx],\n )\n\n return out_hidden_states\n\n\nclass TritonExperts(mk.FusedMoEPermuteExpertsUnpermute):\n def __init__(\n self,\n quant_config: FusedMoEQuantConfig,\n ):\n super().__init__(quant_config)\n\n @property\n def activation_formats(\n self,\n ) -> tuple[mk.FusedMoEActivationFormat, mk.FusedMoEActivationFormat]:\n return (\n mk.FusedMoEActivationFormat.Standard,\n mk.FusedMoEActivationFormat.Standard,\n )\n\n def supports_chunking(self) -> bool:\n return True\n\n def supports_expert_map(self) -> bool:\n return True\n\n def finalize_weight_and_reduce_impl(self) -> mk.TopKWeightAndReduce:\n return TopKWeightAndReduceNoOP()\n\n def workspace_shapes(\n self,\n M: int,\n N: int,\n K: int,\n topk: int,\n global_num_experts: int,\n local_num_experts: int,\n expert_tokens_meta: mk.ExpertTokensMetadata | None,\n ) -> tuple[tuple[int, ...], tuple[int, ...], tuple[int, ...]]:\n workspace1 = (M, topk, max(N // 2, K))\n workspace2 = (M, topk, max(N, K))\n output = (M, K)\n return (workspace1, workspace2, output)\n\n def apply(\n self,\n output: torch.Tensor,\n hidden_states: torch.Tensor,\n w1: torch.Tensor,\n w2: torch.Tensor,\n topk_weights: torch.Tensor,\n topk_ids: torch.Tensor,\n activation: str,\n global_num_experts: int,\n expert_map: torch.Tensor | None,\n a1q_scale: torch.Tensor | None,\n a2_scale: torch.Tensor | None,\n workspace13: torch.Tensor,\n workspace2: torch.Tensor,\n expert_tokens_meta: mk.ExpertTokensMetadata | None,\n apply_router_weight_on_input: bool,\n ):\n # Check constraints.\n if self.quant_config.use_int4_w4a16:\n assert hidden_states.size(-1) // 2 == w1.size(2), \"Hidden size mismatch\"\n else:\n assert hidden_states.size(-1) == w1.size(2), (\n f\"Hidden size mismatch {hidden_states.size(-1)} != {w1.size(2)}\"\n )\n\n assert hidden_states.is_contiguous(), \"Hidden_states must be contiguous\"\n assert hidden_states.dim() == 2\n assert w1.stride(-1) == 1, \"Stride of last dimension must be 1\"\n assert w2.stride(-1) == 1, \"Stride of last dimension must be 1\"\n assert hidden_states.dtype in [\n torch.float32,\n torch.float16,\n torch.bfloat16,\n torch.float8_e4m3fn,\n ]\n\n E, num_tokens, N, K, top_k_num = self.moe_problem_size(\n hidden_states, w1, w2, topk_ids\n )\n\n if global_num_experts == -1:\n global_num_experts = E\n\n config = try_get_optimal_moe_config(\n w1.size(),\n w2.size(),\n top_k_num,\n self.quant_config.config_name(hidden_states.dtype),\n num_tokens,\n block_shape=self.block_shape,\n )\n\n if hidden_states.dtype == torch.bfloat16:\n compute_type = tl.bfloat16\n elif hidden_states.dtype == torch.float16:\n compute_type = tl.float16\n elif hidden_states.dtype == torch.float32:\n compute_type = tl.float32\n elif hidden_states.dtype == torch.float8_e4m3fn:\n compute_type = tl.bfloat16\n else:\n raise ValueError(f\"Unsupported compute_type: {hidden_states.dtype}\")\n\n # Note that the output tensor might be in workspace1\n intermediate_cache1 = _resize_cache(workspace2, (num_tokens, top_k_num, N))\n intermediate_cache2 = _resize_cache(\n workspace13, (num_tokens * top_k_num, N // 2)\n )\n intermediate_cache3 = _resize_cache(workspace2, (num_tokens, top_k_num, K))\n\n sorted_token_ids, expert_ids, num_tokens_post_padded = moe_align_block_size(\n topk_ids, config[\"BLOCK_SIZE_M\"], global_num_experts, expert_map\n )\n\n invoke_fused_moe_kernel(\n hidden_states,\n w1,\n intermediate_cache1,\n a1q_scale,\n self.w1_scale,\n self.w1_zp,\n None, # topk_weights\n sorted_token_ids,\n expert_ids,\n num_tokens_post_padded,\n False, # mul_routed_weights\n top_k_num,\n config,\n compute_type=compute_type,\n use_fp8_w8a8=self.quant_config.use_fp8_w8a8,\n use_int8_w8a8=self.quant_config.use_int8_w8a8,\n use_int8_w8a16=self.quant_config.use_int8_w8a16,\n use_int4_w4a16=self.quant_config.use_int4_w4a16,\n per_channel_quant=self.per_act_token_quant,\n block_shape=self.block_shape,\n B_bias=self.w1_bias,\n )\n\n self.activation(\n activation, intermediate_cache2, intermediate_cache1.view(-1, N)\n )\n\n a2q_scale: torch.Tensor | None = None\n\n qintermediate_cache2, a2q_scale = moe_kernel_quantize_input(\n intermediate_cache2,\n a2_scale,\n self.quant_dtype,\n self.per_act_token_quant,\n self.block_shape,\n )\n\n invoke_fused_moe_kernel(\n qintermediate_cache2,\n w2,\n intermediate_cache3,\n a2q_scale,\n self.w2_scale,\n self.w2_zp,\n topk_weights,\n sorted_token_ids,\n expert_ids,\n num_tokens_post_padded,\n not apply_router_weight_on_input,\n 1,\n config,\n compute_type=compute_type,\n use_fp8_w8a8=self.quant_config.use_fp8_w8a8,\n use_int8_w8a8=self.quant_config.use_int8_w8a8,\n use_int8_w8a16=self.quant_config.use_int8_w8a16,\n use_int4_w4a16=self.quant_config.use_int4_w4a16,\n per_channel_quant=self.per_act_token_quant,\n block_shape=self.block_shape,\n B_bias=self.w2_bias,\n )\n\n # separate function is required for MoE + LoRA\n self.moe_sum(intermediate_cache3, output)\n\n def moe_sum(self, input: torch.Tensor, output: torch.Tensor) -> None:\n ops.moe_sum(input, output)\n\n\ndef modular_triton_fused_moe(\n quant_config: FusedMoEQuantConfig, shared_experts: torch.nn.Module | None = None\n) -> mk.FusedMoEModularKernel:\n return mk.FusedMoEModularKernel(\n MoEPrepareAndFinalizeNoEP(),\n TritonExperts(quant_config),\n shared_experts,\n )\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## Introduction\nThis PR optimize `moe_align_block_size` from three aspects:\n\n1. For a small batch size, use the smallest possible value for `max_num_tokens_padded`.\n\n2. In the CUDA Kernel, use additional thread or threadblock resources to fill `sorted_token_ids`. The previous CUDA Kernel used very few computational resources, and the filling of `sorted_token_ids` and the counting of experts were performed sequentially. Since `sorted_token_ids` is only used again at the very end of the CUDA kernel, I changed this to be parallelized to accelerate kernel execution.\n\n3. For EP, all invalid experts are filtered out directly when counting the number of experts. This accelerates the execution of `moe_align_block_size` and also leads to a cleaner and faster implementation for the subsequent MoE kernel.\n\n\n## Kernel Bench\n\nOn RTX 4090\n\n```\nmoe-align-block-size-performance:\n num_tokens num_experts topk ep_size main PR\n0 1.0 16.0 1.0 1.0 8.192000 6.144000\n1 1.0 16.0 1.0 8.0 12.288000 6.144000\n2 1.0 16.0 2.0 1.0 7.168000 6.080000\n3 1.0 16.0 2.0 8.0 11.264000 5.120000\n4 1.0 16.0 8.0 1.0 7.232000 5.120000\n5 1.0 16.0 8.0 8.0 12.224000 6.144000\n6 1.0 64.0 1.0 1.0 13.312000 9.216000\n7 1.0 64.0 1.0 8.0 17.408000 9.216000\n8 1.0 64.0 2.0 1.0 13.312000 9.216000\n9 1.0 64.0 2.0 8.0 17.408000 9.216000\n10 1.0 64.0 8.0 1.0 13.312000 9.216000\n11 1.0 64.0 8.0 8.0 17.408000 9.216000\n12 1.0 224.0 1.0 1.0 10.240000 7.168000\n13 1.0 224.0 1.0 8.0 14.336000 7.168000\n14 1.0 224.0 2.0 1.0 10.240000 7.168000\n15 1.0 224.0 2.0 8.0 14.336000 7.168000\n16 1.0 224.0 8.0 1.0 10.240000 7.168000\n17 1.0 224.0 8.0 8.0 14.336000 7.168000\n18 1.0 256.0 1.0 1.0 10.240000 7.168000\n19 1.0 256.0 1.0 8.0 14.336000 8.192000\n20 1.0 256.0 2.0 1.0 10.240000 7.168000\n21 1.0 256.0 2.0 8.0 14.336000 8.192000\n22 1.0 256.0 8.0 1.0 10.240000 7.168000\n23 1.0 256.0 8.0 8.0 14.336000 8.192000\n24 1.0 280.0 1.0 1.0 11.264000 7.168000\n25 1.0 280.0 1.0 8.0 15.360000 7.168000\n26 1.0 280.0 2.0 1.0 11.264000 7.168000\n27 1.0 280.0 2.0 8.0 15.360000 7.168000\n28 1.0 280.0 8.0 1.0 11.264000 7.168000\n29 1.0 280.0 8.0 8.0 15.360000 7.168000\n30 1.0 512.0 1.0 1.0 13.312000 7.168000\n31 1.0 512.0 1.0 8.0 18.432001 7.168000\n32 1.0 512.0 2.0 1.0 13.312000 7.168000\n33 1.0 512.0 2.0 8.0 18.432001 7.168000\n34 1.0 512.0 8.0 1.0 13.312000 7.168000\n35 1.0 512.0 8.0 8.0 18.432001 7.168000\n36 16.0 16.0 1.0 1.0 7.168000 6.080000\n37 16.0 16.0 1.0 8.0 11.264000 6.144000\n38 16.0 16.0 2.0 1.0 7.168000 5.120000\n39 16.0 16.0 2.0 8.0 12.288000 5.120000\n40 16.0 16.0 8.0 1.0 8.192000 6.144000\n41 16.0 16.0 8.0 8.0 13.312000 7.168000\n42 16.0 64.0 1.0 1.0 13.312000 9.216000\n43 16.0 64.0 1.0 8.0 17.408000 9.216000\n44 16.0 64.0 2.0 1.0 13.312000 9.216000\n45 16.0 64.0 2.0 8.0 17.408000 9.216000\n46 16.0 64.0 8.0 1.0 13.312000 9.312000\n47 16.0 64.0 8.0 8.0 17.408000 9.216000\n48 16.0 224.0 1.0 1.0 10.240000 7.168000\n49 16.0 224.0 1.0 8.0 14.336000 8.192000\n50 16.0 224.0 2.0 1.0 10.240000 7.168000\n51 16.0 224.0 2.0 8.0 14.336000 8.192000\n52 16.0 224.0 8.0 1.0 10.240000 7.168000\n53 16.0 224.0 8.0 8.0 14.336000 8.192000\n54 16.0 256.0 1.0 1.0 10.240000 7.168000\n55 16.0 256.0 1.0 8.0 14.336000 8.192000\n56 16.0 256.0 2.0 1.0 10.240000 7.168000\n57 16.0 256.0 2.0 8.0 14.336000 8.192000\n58 16.0 256.0 8.0 1.0 10.240000 7.168000\n59 16.0 256.0 8.0 8.0 14.336000 8.192000\n60 16.0 280.0 1.0 1.0 11.264000 7.168000\n61 16.0 280.0 1.0 8.0 15.360000 8.192000\n62 16.0 280.0 2.0 1.0 11.136000 7.168000\n63 16.0 280.0 2.0 8.0 15.360000 8.192000\n64 16.0 280.0 8.0 1.0 11.264000 7.168000\n65 16.0 280.0 8.0 8.0 15.360000 8.192000\n66 16.0 512.0 1.0 1.0 13.312000 7.168000\n67 16.0 512.0 1.0 8.0 18.432001 8.192000\n68 16.0 512.0 2.0 1.0 13.312000 7.168000\n69 16.0 512.0 2.0 8.0 18.432001 8.192000\n70 16.0 512.0 8.0 1.0 13.312000 8.128000\n71 16.0 512.0 8.0 8.0 18.432001 8.192000\n72 256.0 16.0 1.0 1.0 9.216000 7.168000\n73 256.0 16.0 1.0 8.0 13.312000 8.192000\n74 256.0 16.0 2.0 1.0 12.288000 10.240000\n75 256.0 16.0 2.0 8.0 15.360000 11.264000\n76 256.0 16.0 8.0 1.0 8.192000 8.192000\n77 256.0 16.0 8.0 8.0 12.288000 8.192000\n78 256.0 64.0 1.0 1.0 14.336000 10.240000\n79 256.0 64.0 1.0 8.0 18.432001 10.736000\n80 256.0 64.0 2.0 1.0 14.336000 11.264000\n81 256.0 64.0 2.0 8.0 18.432001 12.288000\n82 256.0 64.0 8.0 1.0 9.216000 8.192000\n83 256.0 64.0 8.0 8.0 12.288000 8.192000\n84 256.0 224.0 1.0 1.0 10.240000 8.192000\n85 256.0 224.0 1.0 8.0 14.432000 8.192000\n86 256.0 224.0 2.0 1.0 10.240000 8.192000\n87 256.0 224.0 2.0 8.0 14.336000 8.192000\n88 256.0 224.0 8.0 1.0 11.264000 8.192000\n89 256.0 224.0 8.0 8.0 15.360000 8.192000\n90 256.0 256.0 1.0 1.0 10.240000 8.192000\n91 256.0 256.0 1.0 8.0 15.360000 8.192000\n92 256.0 256.0 2.0 1.0 10.240000 8.192000\n93 256.0 256.0 2.0 8.0 15.360000 8.192000\n94 256.0 256.0 8.0 1.0 11.264000 9.216000\n95 256.0 256.0 8.0 8.0 16.384000 8.192000\n96 256.0 280.0 1.0 1.0 11.264000 8.192000\n97 256.0 280.0 1.0 8.0 15.360000 8.192000\n98 256.0 280.0 2.0 1.0 11.264000 9.216000\n99 256.0 280.0 2.0 8.0 16.384000 9.216000\n100 256.0 280.0 8.0 1.0 11.264000 9.216000\n101 256.0 280.0 8.0 8.0 16.527999 9.216000\n102 256.0 512.0 1.0 1.0 13.312000 8.192000\n103 256.0 512.0 1.0 8.0 18.592000 8.192000\n104 256.0 512.0 2.0 1.0 13.312000 11.264000\n105 256.0 512.0 2.0 8.0 19.455999 11.264000\n106 256.0 512.0 8.0 1.0 14.336000 11.264000\n107 256.0 512.0 8.0 8.0 19.455999 11.264000\n108 4096.0 16.0 1.0 1.0 9.216000 9.216000\n109 4096.0 16.0 1.0 8.0 13.312000 9.216000\n110 4096.0 16.0 2.0 1.0 11.264000 11.264000\n111 4096.0 16.0 2.0 8.0 15.360000 10.240000\n112 4096.0 16.0 8.0 1.0 22.528000 20.608000\n113 4096.0 16.0 8.0 8.0 26.624000 19.455999\n114 4096.0 64.0 1.0 1.0 10.240000 9.216000\n115 4096.0 64.0 1.0 8.0 14.336000 9.216000\n116 4096.0 64.0 2.0 1.0 12.288000 11.264000\n117 4096.0 64.0 2.0 8.0 16.384000 10.240000\n118 4096.0 64.0 8.0 1.0 25.599999 23.552001\n119 4096.0 64.0 8.0 8.0 30.719999 18.432001\n120 4096.0 224.0 1.0 1.0 12.288000 9.216000\n121 4096.0 224.0 1.0 8.0 16.384000 9.216000\n122 4096.0 224.0 2.0 1.0 14.336000 11.264000\n123 4096.0 224.0 2.0 8.0 18.432001 10.240000\n124 4096.0 224.0 8.0 1.0 24.576001 20.479999\n125 4096.0 224.0 8.0 8.0 28.672000 19.455999\n126 4096.0 256.0 1.0 1.0 12.288000 9.216000\n127 4096.0 256.0 1.0 8.0 17.408000 9.216000\n128 4096.0 256.0 2.0 1.0 14.336000 11.264000\n129 4096.0 256.0 2.0 8.0 19.455999 10.240000\n130 4096.0 256.0 8.0 1.0 27.648000 23.552001\n131 4096.0 256.0 8.0 8.0 32.768000 19.455999\n132 4096.0 280.0 1.0 1.0 12.288000 9.216000\n133 4096.0 280.0 1.0 8.0 17.408000 9.216000\n134 4096.0 280.0 2.0 1.0 15.360000 11.264000\n135 4096.0 280.0 2.0 8.0 19.616000 10.240000\n136 4096.0 280.0 8.0 1.0 25.599999 21.504000\n137 4096.0 280.0 8.0 8.0 31.727999 19.455999\n138 4096.0 512.0 1.0 1.0 15.360000 12.288000\n139 4096.0 512.0 1.0 8.0 20.479999 12.192000\n140 4096.0 512.0 2.0 1.0 17.408000 13.280000\n141 4096.0 512.0 2.0 8.0 22.528000 12.288000\n142 4096.0 512.0 8.0 1.0 28.672000 21.504000\n143 4096.0 512.0 8.0 8.0 34.655999 19.455999\n```\n\n\n## Kernel Accuracy Test\n\nTested with\n\n```\npytest -sv test_moe_align_block_size.py::test_moe_align_block_size\n\npytest -sv test_moe_align_block_size.py::test_moe_align_block_size_with_expert_map\n```\n\nAll test cases are passed.\n\n## E2E Accuracy Test\n\nGSM8K (2-shot)\n\nWith Triton Kernel\n\n```\nvllm serve /data/pretrained_model/Qwen/Qwen1.5-MoE-A2.7B-Chat/ -tp 4 --served-model-name model --port 8002 --gpu-memory-utilization 0.75 --enable-expert-parallel\n\n\nlm_eval \\\n --model local-chat-completions \\\n --tasks gsm8k \\\n --num_fewshot 2 \\\n --batch_size auto \\\n --model_args \"model=model,base_url=http://localhost:8002/v1/chat/completions,max_gen_toks=512,num_concurrent=128,max_length=4096\" \\\n --apply_chat_template\n\n\n|Tasks|Version| Filter |n-shot| Metric | |Value | |Stderr|\n|-----|------:|----------------|-----:|-----------|---|-----:|---|-----:|\n|gsm8k| 3|flexible-extract| 2|exact_match|↑ |0.5095|± |0.0138|\n| | |strict-match | 2|exact_match|↑ |0.0258|± |0.0044|\n```\n\n\nWith Marlin Kernel\n\n```\nvllm serve /data/pretrained_model/Qwen/Qwen1.5-MoE-A2.7B-Chat-GPTQ-Int4/ -tp 4 --served-model-name model --port 8002 --gpu-memory-utilization 0.75 --enable-expert-parallel\n\n\nlm_eval \\\n --model local-chat-completions \\\n --tasks gsm8k \\\n --num_fewshot 2 \\\n --batch_size auto \\\n --model_args \"model=model,base_url=http://localhost:8002/v1/chat/completions,max_gen_toks=512,num_concurrent=128,max_length=4096\" \\\n --apply_chat_template\n\n\n|Tasks|Version| Filter |n-shot| Metric | |Value | |Stderr|\n|-----|------:|----------------|-----:|-----------|---|-----:|---|-----:|\n|gsm8k| 3|flexible-extract| 2|exact_match|↑ |0.4723|± |0.0138|\n| | |strict-match | 2|exact_match|↑ |0.0190|± |0.0038|\n```\n"},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":397,"cells":{"repo":{"kind":"string","value":"vllm"},"commit":{"kind":"string","value":"9843e332da56307597deb2739bb83b85c18c5dde"},"date":{"kind":"string","value":"2025-12-05T08:09:20-05:00"},"pr_number":{"kind":"number","value":30068,"string":"30,068"},"pr_url":{"kind":"string","value":"https://github.com/vllm-project/vllm/pull/30068"},"title":{"kind":"string","value":"[CPU][Perf] Add fast vectorized exp impl from Arm Optimized Routines (#30068)"},"message":{"kind":"string","value":"[CPU][Perf] Add fast vectorized exp impl from Arm Optimized Routines (#30068)\n\nSigned-off-by: Ubuntu <ubuntu@ip-10-252-30-150.eu-west-1.compute.internal>\nSigned-off-by: Elham Harirpoush <elham.harirpoush@arm.com>\nCo-authored-by: Ubuntu <ubuntu@ip-10-252-30-150.eu-west-1.compute.internal>"},"path":{"kind":"string","value":"csrc/cpu/cpu_attn_impl.hpp"},"language":{"kind":"string","value":"cpp"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"#ifndef CPU_ATTN_HPP\n#define CPU_ATTN_HPP\n\n#include <type_traits>\n#include <cstddef>\n\n#if defined(__APPLE__)\n #include <sys/sysctl.h>\n#endif\n\n#include \"cpu_types.hpp\"\n#include \"scratchpad_manager.h\"\n#include \"cpu_attn_macros.h\"\n#include \"utils.hpp\"\n\nnamespace cpu_attention {\nenum class ISA { AMX, VEC, VEC16, NEON };\n\ntemplate <ISA isa, typename scalar_t, int64_t head_dim>\nclass AttentionImpl {};\n\nstruct AttentionWorkItemGroup {\n int32_t req_id;\n int32_t q_token_id_start;\n int32_t q_token_num;\n int32_t kv_split_pos_start;\n int32_t kv_split_pos_end;\n\n int64_t total_kv_len;\n int32_t split_id;\n int32_t local_split_id;\n\n AttentionWorkItemGroup(const int32_t req_id, const int32_t q_token_id_start,\n const int32_t kv_split_pos_start,\n const int32_t kv_split_pos_end)\n : req_id(req_id),\n q_token_id_start(q_token_id_start),\n q_token_num(0),\n kv_split_pos_start(kv_split_pos_start),\n kv_split_pos_end(kv_split_pos_end),\n total_kv_len(0),\n split_id(-1),\n local_split_id(0) {}\n\n std::string to_string() const {\n std::stringstream ss;\n ss << '[' << \"req_id: \" << req_id << \",\\n\";\n ss << \"q_token_id_start: \" << q_token_id_start << \",\\n\";\n ss << \"q_token_num: \" << q_token_num << \",\\n\";\n ss << \"kv_split_pos_start: \" << kv_split_pos_start << \",\\n\";\n ss << \"kv_split_pos_end: \" << kv_split_pos_end << \",\\n\";\n ss << \"total_kv_len: \" << total_kv_len << \",\\n\";\n ss << \"split_id: \" << split_id << \",\\n\";\n ss << \"local_split_id: \" << local_split_id << \",\\n\";\n ss << ']';\n\n return ss.str();\n }\n};\n\nstruct ReductionWorkItemGroup {\n int32_t req_id;\n int32_t q_token_id_start;\n int32_t q_token_id_num;\n int32_t split_start_id;\n int32_t split_num;\n\n ReductionWorkItemGroup(const int32_t req_id, const int32_t q_token_id_start,\n const int32_t q_token_id_num,\n const int32_t split_start_id)\n : req_id(req_id),\n q_token_id_start(q_token_id_start),\n q_token_id_num(q_token_id_num),\n split_start_id(split_start_id),\n split_num(0) {}\n\n std::string to_string() const {\n std::stringstream ss;\n ss << '[' << \"req_id: \" << req_id << \",\\n\";\n ss << \"q_token_id_start: \" << q_token_id_start << \",\\n\";\n ss << \"q_token_id_num: \" << q_token_id_num << \",\\n\";\n ss << \"split_start_id: \" << split_start_id << \",\\n\";\n ss << \"split_num: \" << split_num << \",\\n\";\n ss << ']';\n\n return ss.str();\n }\n};\n\nstruct AttentionMetadata {\n std::atomic_int64_t counter;\n char _padding1[56];\n ISA isa;\n int32_t workitem_group_num;\n int32_t reduction_item_num;\n int32_t reduction_split_num;\n int32_t thread_num;\n int32_t effective_thread_num; // non-zero item num in workitem_num_per_thread\n int32_t split_kv_q_token_num_threshold;\n int64_t attention_scratchpad_size_per_thread;\n int64_t reduction_scratchpad_size_per_kv_head;\n AttentionWorkItemGroup* workitem_groups_ptr;\n ReductionWorkItemGroup* reduction_items_ptr;\n int32_t cu_workitem_num_per_thread[1025] = {\n 0}; // prefix sum of workitem_num_per_thread\n char _padding2[56];\n\n AttentionMetadata(ISA isa, int32_t workitem_group_num,\n int32_t reduction_item_num, int32_t reduction_split_num,\n int32_t split_kv_q_token_num_threshold)\n : isa(isa),\n workitem_group_num(workitem_group_num),\n reduction_item_num(reduction_item_num),\n reduction_split_num(reduction_split_num),\n thread_num(omp_get_max_threads()),\n effective_thread_num(thread_num),\n split_kv_q_token_num_threshold(split_kv_q_token_num_threshold),\n attention_scratchpad_size_per_thread(0),\n reduction_scratchpad_size_per_kv_head(0),\n workitem_groups_ptr(\n (AttentionWorkItemGroup*)((char*)this + sizeof(AttentionMetadata))),\n reduction_items_ptr(\n (ReductionWorkItemGroup*)((char*)this + sizeof(AttentionMetadata) +\n workitem_group_num *\n sizeof(AttentionWorkItemGroup))),\n counter(0) {\n TORCH_CHECK_LE(thread_num, 1024);\n static_assert(sizeof(AttentionMetadata) % 64 == 0);\n TORCH_CHECK(reinterpret_cast<size_t>(this) % 64 == 0);\n }\n\n void reset_counter() { counter.store(0); }\n\n int64_t acquire_counter() { return counter++; }\n\n void print() const {\n std::stringstream ss;\n ss << \"ISA: \";\n switch (isa) {\n case ISA::AMX:\n ss << \"AMX, \";\n break;\n case ISA::VEC:\n ss << \"VEC, \";\n break;\n case ISA::VEC16:\n ss << \"VEC16, \";\n break;\n case ISA::NEON:\n ss << \"NEON, \";\n break;\n }\n ss << \"workitem_group_num: \" << workitem_group_num\n << \", reduction_item_num: \" << reduction_item_num\n << \", reduction_split_num: \" << reduction_split_num\n << \", thread_num: \" << thread_num\n << \", effective_thread_num: \" << effective_thread_num\n << \", attention_scratchpad_size_per_thread: \"\n << attention_scratchpad_size_per_thread\n << \", reduction_scratchpad_size_per_kv_head: \"\n << reduction_scratchpad_size_per_kv_head << \", workitem groups:\\n\";\n for (int32_t i = 0; i < workitem_group_num; ++i) {\n ss << (workitem_groups_ptr + i)->to_string() << \",\\n\";\n }\n\n ss << \"cu_workitem_num_per_thread: [\";\n for (int32_t i = 0; i < thread_num + 1; ++i) {\n ss << cu_workitem_num_per_thread[i] << \", \";\n }\n ss << \"]\\n\";\n\n ss << \"reduction items: \\n\";\n\n for (int32_t i = 0; i < reduction_item_num; ++i) {\n ss << (reduction_items_ptr + i)->to_string() << \",\\n\";\n }\n\n std::printf(\"%s\", ss.str().c_str());\n }\n};\n\n// Thread attention scratchpad contains:\n// - Q: q_tile_size * head_dim * q_buffer_elem_size, gather Q heads, especially\n// for GQA\n// - Q@K^T: max_num_q_per_iter * k_tile_size * logits_buffer_elem_size, logits\n// - Intermediate outputs: q_tile_size * head_dim * output_buffer_elem_size + 2\n// * q_tile_size * 4, partial output, max + sum (float)\n// Reduction scratchpad contains:\n// - flags: bool array to indicate wether the split is finished\n// - outputs: split_num * q_tile_size * head_dim * output_buffer_elem_size\n// - max, sum: 2 * split_num * q_tile_size * 4\nclass AttentionScratchPad {\n public:\n AttentionScratchPad(int64_t thread_id,\n const AttentionMetadata& attention_metadata,\n void* scratchpad_ptr)\n : thread_scratchpad_ptr(\n static_cast<int8_t*>(scratchpad_ptr) +\n thread_id *\n attention_metadata.attention_scratchpad_size_per_thread),\n reduction_scratchpad_ptr(\n static_cast<int8_t*>(scratchpad_ptr) +\n attention_metadata.thread_num *\n attention_metadata.attention_scratchpad_size_per_thread),\n reduction_scratchpad_size_per_kv_head(\n attention_metadata.reduction_scratchpad_size_per_kv_head) {}\n\n // for attention\n void update(const int64_t head_dim, const int64_t q_buffer_elem_size,\n const int64_t logits_buffer_elem_size,\n const int64_t output_buffer_elem_size,\n const int64_t max_num_q_per_iter, const int64_t q_head_tile_size,\n const int64_t kv_tile_size) {\n int64_t buffer_offset = 0;\n q_buffer_offset_ = buffer_offset;\n buffer_offset +=\n calcu_q_buffer_size(q_head_tile_size, head_dim, q_buffer_elem_size);\n logits_buffer_offset_ = buffer_offset;\n buffer_offset += calcu_logits_buffer_size(max_num_q_per_iter, kv_tile_size,\n logits_buffer_elem_size);\n output_buffer_offset_ = buffer_offset;\n buffer_offset += calcu_partial_output_buffer_size(\n q_head_tile_size, head_dim, output_buffer_elem_size);\n max_buffer_offset_ = buffer_offset;\n buffer_offset += calcu_partial_output_max_sum_buffer_size(q_head_tile_size);\n sum_buffer_offset_ = buffer_offset;\n }\n\n // for reduction\n void update(const int32_t kv_head_idx, const int32_t total_split_num,\n const int64_t head_dim, const int64_t q_head_tile_size,\n const int64_t output_buffer_elem_size) {\n int64_t buffer_offset = kv_head_idx * reduction_scratchpad_size_per_kv_head;\n reduce_flag_buffer_offset_ = buffer_offset;\n buffer_offset += calcu_reduce_flag_buffer_size(total_split_num);\n reduce_output_buffer_offset_ = buffer_offset;\n buffer_offset += calcu_reduce_output_buffer_size(\n total_split_num, q_head_tile_size, head_dim, output_buffer_elem_size);\n reduce_max_buffer_offset_ = buffer_offset;\n buffer_offset +=\n calcu_reduce_max_sum_buffer_size(total_split_num, q_head_tile_size);\n reduce_sum_buffer_offset_ = buffer_offset;\n }\n\n template <typename T>\n T* get_q_buffer() {\n return reinterpret_cast<T*>(thread_scratchpad_ptr + q_buffer_offset_);\n }\n\n float* get_logits_buffer() {\n return reinterpret_cast<float*>(thread_scratchpad_ptr +\n logits_buffer_offset_);\n }\n\n float* get_output_buffer() {\n return reinterpret_cast<float*>(thread_scratchpad_ptr +\n output_buffer_offset_);\n }\n\n float* get_max_buffer() {\n return reinterpret_cast<float*>(thread_scratchpad_ptr + max_buffer_offset_);\n }\n\n float* get_sum_buffer() {\n return reinterpret_cast<float*>(thread_scratchpad_ptr + sum_buffer_offset_);\n }\n\n volatile bool* get_reduce_flag_buffer() {\n return reinterpret_cast<volatile bool*>(reduction_scratchpad_ptr +\n reduce_flag_buffer_offset_);\n }\n\n float* get_reduce_output_buffer() {\n return reinterpret_cast<float*>(reduction_scratchpad_ptr +\n reduce_output_buffer_offset_);\n }\n\n float* get_reduce_max_buffer() {\n return reinterpret_cast<float*>(reduction_scratchpad_ptr +\n reduce_max_buffer_offset_);\n }\n\n float* get_reduce_sum_buffer() {\n return reinterpret_cast<float*>(reduction_scratchpad_ptr +\n reduce_sum_buffer_offset_);\n }\n\n int64_t get_thread_scratchpad_size() const {\n return 2 * sum_buffer_offset_ - max_buffer_offset_;\n }\n\n int64_t get_reduction_scratchpad_size() const {\n return 2 * reduce_sum_buffer_offset_ - reduce_max_buffer_offset_;\n }\n\n private:\n static int64_t round_to_64(const int64_t num) {\n return ((num + 63) >> 6) << 6;\n }\n\n static int64_t calcu_q_buffer_size(const int64_t q_tile_size,\n const int64_t head_dim,\n const int64_t elem_size) {\n return round_to_64(q_tile_size * head_dim * elem_size);\n }\n\n static int64_t calcu_logits_buffer_size(const int64_t max_num_q_per_iter,\n const int64_t k_tile_size,\n const int64_t elem_size) {\n return round_to_64(elem_size * max_num_q_per_iter * k_tile_size);\n }\n\n static int64_t calcu_partial_output_buffer_size(const int64_t q_tile_size,\n const int64_t head_dim,\n const int64_t elem_size) {\n return round_to_64(q_tile_size * head_dim * elem_size);\n }\n\n static int64_t calcu_partial_output_max_sum_buffer_size(\n const int64_t q_tile_size) {\n return round_to_64(q_tile_size * sizeof(float));\n }\n\n static int64_t calcu_reduce_flag_buffer_size(const int64_t total_split_num) {\n return round_to_64(total_split_num * sizeof(bool));\n }\n\n static int64_t calcu_reduce_max_sum_buffer_size(\n const int64_t total_split_num, const int32_t q_head_tile_size) {\n return round_to_64(total_split_num * q_head_tile_size * sizeof(float));\n }\n\n static int64_t calcu_reduce_output_buffer_size(\n const int64_t total_split_num, const int64_t q_head_tile_size,\n const int64_t head_dim, const int64_t output_buffer_elem_size) {\n return round_to_64(total_split_num * q_head_tile_size * head_dim *\n output_buffer_elem_size);\n }\n\n private:\n int8_t* thread_scratchpad_ptr;\n int8_t* reduction_scratchpad_ptr;\n int64_t reduction_scratchpad_size_per_kv_head;\n // attention buffers\n int64_t q_buffer_offset_;\n int64_t logits_buffer_offset_;\n int64_t output_buffer_offset_;\n int64_t max_buffer_offset_;\n int64_t sum_buffer_offset_;\n // reduction buffers\n int64_t reduce_flag_buffer_offset_;\n int64_t reduce_output_buffer_offset_;\n int64_t reduce_max_buffer_offset_;\n int64_t reduce_sum_buffer_offset_;\n};\n\nclass AttentionScheduler {\n public:\n struct ScheduleInput {\n int32_t num_reqs;\n int32_t elem_size;\n int32_t q_buffer_elem_size;\n int32_t logits_buffer_elem_size;\n int32_t output_buffer_elem_size;\n int32_t num_heads_q;\n int32_t num_heads_kv;\n int32_t head_dim;\n int32_t* query_start_loc;\n int32_t* seq_lens;\n int32_t left_sliding_window_size;\n int32_t right_sliding_window_size;\n bool casual;\n cpu_attention::ISA isa;\n int32_t max_num_q_per_iter; // max Q head num can be hold in registers\n int32_t kv_block_alignment; // context length alignment requirement\n bool enable_kv_split;\n };\n\n static constexpr int32_t MaxQTileIterNum = 128;\n\n AttentionScheduler() : available_cache_size_(get_available_l2_size()) {}\n\n torch::Tensor schedule(const ScheduleInput& input) const {\n const bool casual = input.casual;\n const int32_t thread_num = omp_get_max_threads();\n const int64_t cache_size = get_available_l2_size();\n const int32_t max_num_q_per_iter = input.max_num_q_per_iter;\n const int32_t kv_len_alignment = input.kv_block_alignment;\n int32_t q_head_per_kv = input.num_heads_q / input.num_heads_kv;\n const bool use_gqa = (max_num_q_per_iter % q_head_per_kv == 0);\n if (!use_gqa) {\n q_head_per_kv = 1; // fallback to MHA\n }\n const int32_t min_split_kv_len =\n ((max_num_q_per_iter * 4 + kv_len_alignment - 1) / kv_len_alignment) *\n kv_len_alignment;\n const int32_t max_num_q_token_per_iter = max_num_q_per_iter / q_head_per_kv;\n const int64_t default_tile_size = calcu_default_tile_size(\n cache_size, input.head_dim, input.elem_size, input.q_buffer_elem_size,\n input.logits_buffer_elem_size, input.output_buffer_elem_size,\n max_num_q_per_iter, max_num_q_per_iter);\n const int32_t default_tile_token_num = default_tile_size / q_head_per_kv;\n const int32_t split_kv_q_token_num_threshold =\n input.enable_kv_split ? 1 : 0;\n const int32_t left_sliding_window_size = input.left_sliding_window_size;\n const int32_t right_sliding_window_size = input.right_sliding_window_size;\n TORCH_CHECK_LE(split_kv_q_token_num_threshold * q_head_per_kv, 16);\n\n // get total kv len\n int64_t total_kv_len = 0;\n for (int32_t req_id = 0; req_id < input.num_reqs; ++req_id) {\n const int32_t seq_len = input.seq_lens[req_id];\n const int32_t q_token_num =\n input.query_start_loc[req_id + 1] - input.query_start_loc[req_id];\n const int32_t q_start_pos = (casual ? (seq_len - q_token_num) : 0);\n const int32_t kv_start_pos = 0;\n const int32_t kv_end_pos = seq_len;\n\n for (int32_t token_id = 0; token_id < q_token_num;\n token_id += max_num_q_token_per_iter) {\n const int32_t q_tile_token_num =\n std::min(max_num_q_token_per_iter, q_token_num - token_id);\n const int32_t q_tile_pos_left = q_start_pos + token_id;\n const int32_t q_tile_pos_right = q_tile_pos_left + q_tile_token_num;\n const auto [kv_tile_pos_left, kv_tile_pos_right] = calcu_kv_tile_pos(\n kv_start_pos, kv_end_pos, q_tile_pos_left, q_tile_pos_right,\n left_sliding_window_size, right_sliding_window_size);\n const auto [aligned_kv_tile_pos_left, aligned_kv_tile_pos_right] =\n align_kv_tile_pos(kv_tile_pos_left, kv_tile_pos_right,\n kv_len_alignment);\n\n int32_t curr_kv_len =\n aligned_kv_tile_pos_right - aligned_kv_tile_pos_left;\n total_kv_len += curr_kv_len;\n }\n }\n const int64_t kv_len_per_thread =\n (((total_kv_len / thread_num) + kv_len_alignment - 1) /\n kv_len_alignment) *\n kv_len_alignment * (use_gqa ? input.num_heads_kv : input.num_heads_q);\n std::vector<AttentionWorkItemGroup> workitems;\n std::vector<ReductionWorkItemGroup> reduce_workitems;\n workitems.reserve(1024);\n reduce_workitems.reserve(1024);\n std::vector<int32_t> workitem_num_per_thread(thread_num, 0);\n\n // split tasks\n int32_t curr_thread_id = 0;\n int64_t remaining_kv_len = kv_len_per_thread;\n int32_t cum_split_num = 0;\n for (int32_t req_id = 0; req_id < input.num_reqs; ++req_id) {\n const int32_t seq_len = input.seq_lens[req_id];\n const int32_t q_token_num =\n input.query_start_loc[req_id + 1] - input.query_start_loc[req_id];\n const int32_t q_start_pos = (casual ? (seq_len - q_token_num) : 0);\n const int32_t kv_start_pos = 0;\n const int32_t kv_end_pos = seq_len;\n int32_t local_split_id = 0;\n\n AttentionWorkItemGroup curr_workitem(req_id, 0, 0, seq_len);\n for (int32_t token_id = 0; token_id < q_token_num;\n token_id += max_num_q_token_per_iter) {\n const int32_t q_tile_token_num =\n std::min(max_num_q_token_per_iter, q_token_num - token_id);\n const int32_t q_tile_pos_left = q_start_pos + token_id;\n const int32_t q_tile_pos_right = q_tile_pos_left + q_tile_token_num;\n const auto [kv_tile_pos_left, kv_tile_pos_right] = calcu_kv_tile_pos(\n kv_start_pos, kv_end_pos, q_tile_pos_left, q_tile_pos_right,\n left_sliding_window_size, right_sliding_window_size);\n const auto [aligned_kv_tile_pos_left, aligned_kv_tile_pos_right] =\n align_kv_tile_pos(kv_tile_pos_left, kv_tile_pos_right,\n kv_len_alignment);\n int32_t curr_kv_len =\n aligned_kv_tile_pos_right - aligned_kv_tile_pos_left;\n int32_t kv_token_pos_start = aligned_kv_tile_pos_left;\n\n while (curr_kv_len > 0) {\n if (curr_kv_len <= (remaining_kv_len + min_split_kv_len) ||\n curr_thread_id == (thread_num - 1)) {\n curr_workitem.q_token_num += q_tile_token_num;\n curr_workitem.total_kv_len += curr_kv_len;\n remaining_kv_len -= curr_kv_len;\n curr_kv_len = 0;\n\n if (remaining_kv_len < 0) {\n // stop to accept more workitems\n remaining_kv_len -= min_split_kv_len;\n }\n\n if (curr_workitem.kv_split_pos_start != 0) {\n // got a partial kv spilt, need to create a single workitem\n curr_workitem.split_id = cum_split_num;\n curr_workitem.local_split_id = local_split_id;\n workitems.emplace_back(curr_workitem);\n ++workitem_num_per_thread[curr_thread_id];\n ++reduce_workitems.back().split_num;\n ++cum_split_num;\n\n curr_workitem = AttentionWorkItemGroup(\n req_id, token_id + max_num_q_token_per_iter, 0, seq_len);\n }\n\n break;\n }\n\n if (remaining_kv_len < min_split_kv_len &&\n (curr_workitem.total_kv_len > 0 ||\n workitem_num_per_thread[curr_thread_id] > 0)) {\n // remaining_kv_len is too short, and have allocated workitems, just\n // leave to next thread\n if (curr_workitem.total_kv_len > 0) {\n workitems.emplace_back(curr_workitem);\n ++workitem_num_per_thread[curr_thread_id];\n curr_workitem =\n AttentionWorkItemGroup(req_id, token_id, 0, seq_len);\n }\n\n // switch to next thread\n ++curr_thread_id;\n remaining_kv_len = kv_len_per_thread;\n\n // retry this iteration\n continue;\n }\n\n // only split tail splits with q_tile_token_num <=\n // split_kv_q_token_num_threshold\n if (token_id + max_num_q_token_per_iter < q_token_num ||\n q_tile_token_num > split_kv_q_token_num_threshold) {\n // if requires a new q tile iteration and already has workitems,\n // leave this workitem to next thread\n if (curr_workitem.q_token_num % default_tile_token_num == 0 &&\n (curr_workitem.total_kv_len > 0 ||\n workitem_num_per_thread[curr_thread_id] > 0)) {\n if (curr_workitem.total_kv_len > 0) {\n workitems.emplace_back(curr_workitem);\n ++workitem_num_per_thread[curr_thread_id];\n }\n curr_workitem =\n AttentionWorkItemGroup(req_id, token_id, 0, seq_len);\n\n // switch to next thread\n ++curr_thread_id;\n remaining_kv_len = kv_len_per_thread;\n }\n\n curr_workitem.q_token_num += q_tile_token_num;\n curr_workitem.total_kv_len += curr_kv_len;\n remaining_kv_len -= curr_kv_len;\n curr_kv_len = 0;\n break;\n }\n\n // split kv\n if (curr_workitem.total_kv_len > 0) {\n // write back curr workitem\n workitems.emplace_back(curr_workitem);\n ++workitem_num_per_thread[curr_thread_id];\n }\n\n if (kv_token_pos_start == aligned_kv_tile_pos_left) {\n // first split, init the workitem\n reduce_workitems.emplace_back(ReductionWorkItemGroup(\n req_id, token_id, q_tile_token_num, cum_split_num));\n }\n\n int32_t spilt_size =\n std::min(std::max(remaining_kv_len, (int64_t)min_split_kv_len),\n (int64_t)curr_kv_len);\n curr_workitem =\n AttentionWorkItemGroup(req_id, token_id, kv_token_pos_start,\n kv_token_pos_start + spilt_size);\n curr_workitem.q_token_num += q_tile_token_num;\n curr_workitem.total_kv_len += spilt_size;\n curr_workitem.split_id = cum_split_num;\n curr_workitem.local_split_id = local_split_id;\n workitems.emplace_back(curr_workitem);\n ++workitem_num_per_thread[curr_thread_id];\n ++reduce_workitems.back().split_num;\n ++cum_split_num;\n ++local_split_id;\n\n kv_token_pos_start += spilt_size;\n curr_kv_len -= spilt_size;\n curr_workitem = AttentionWorkItemGroup(req_id, token_id,\n kv_token_pos_start, seq_len);\n\n // switch to next thread\n ++curr_thread_id;\n remaining_kv_len = kv_len_per_thread;\n }\n }\n\n if (curr_workitem.total_kv_len > 0) {\n // write back curr workitem\n workitems.emplace_back(curr_workitem);\n ++workitem_num_per_thread[curr_thread_id];\n }\n }\n\n int64_t metadata_tensor_size =\n sizeof(AttentionMetadata) +\n workitems.size() * sizeof(AttentionWorkItemGroup) +\n reduce_workitems.size() * sizeof(ReductionWorkItemGroup);\n auto options =\n torch::TensorOptions().dtype(torch::kInt8).device(torch::kCPU);\n torch::Tensor metadata_tensor =\n torch::empty({metadata_tensor_size}, options);\n AttentionMetadata* metadata_ptr = new (metadata_tensor.data_ptr())\n AttentionMetadata(input.isa, workitems.size(), reduce_workitems.size(),\n cum_split_num, split_kv_q_token_num_threshold);\n AttentionWorkItemGroup* workitem_groups_ptr =\n metadata_ptr->workitem_groups_ptr;\n ReductionWorkItemGroup* reduction_items_ptr =\n metadata_ptr->reduction_items_ptr;\n std::memcpy(workitem_groups_ptr, workitems.data(),\n workitems.size() * sizeof(AttentionWorkItemGroup));\n std::memcpy(reduction_items_ptr, reduce_workitems.data(),\n reduce_workitems.size() * sizeof(ReductionWorkItemGroup));\n\n int32_t effective_thread_num = 0;\n for (; effective_thread_num < thread_num; ++effective_thread_num) {\n if (workitem_num_per_thread[effective_thread_num] == 0) {\n break;\n }\n }\n\n std::memcpy(metadata_ptr->cu_workitem_num_per_thread + 1,\n workitem_num_per_thread.data(),\n workitem_num_per_thread.size() * sizeof(int32_t));\n for (int32_t i = 1; i <= thread_num; ++i) {\n metadata_ptr->cu_workitem_num_per_thread[i] +=\n metadata_ptr->cu_workitem_num_per_thread[i - 1];\n }\n metadata_ptr->effective_thread_num = effective_thread_num;\n\n {\n // when q_tile_size = max_num_q_per_iter, requires max\n // attention_scratchpad_size\n AttentionScratchPad sc(0, *metadata_ptr, 0x0);\n int64_t n = AttentionScheduler::calcu_tile_size_with_constant_q(\n cache_size, input.head_dim, input.elem_size, input.q_buffer_elem_size,\n input.logits_buffer_elem_size, input.output_buffer_elem_size,\n max_num_q_per_iter, kv_len_alignment, max_num_q_per_iter, true);\n sc.update(input.head_dim, input.q_buffer_elem_size,\n input.logits_buffer_elem_size, input.output_buffer_elem_size,\n max_num_q_per_iter, max_num_q_per_iter, n);\n metadata_ptr->attention_scratchpad_size_per_thread =\n ((sc.get_thread_scratchpad_size() + 63) / 64) * 64;\n\n sc.update(0, metadata_ptr->reduction_split_num, input.head_dim,\n q_head_per_kv * split_kv_q_token_num_threshold,\n input.output_buffer_elem_size);\n metadata_ptr->reduction_scratchpad_size_per_kv_head =\n ((sc.get_reduction_scratchpad_size() + 63) / 64) * 64;\n }\n int64_t scratchpad_size =\n metadata_ptr->attention_scratchpad_size_per_thread *\n metadata_ptr->thread_num +\n metadata_ptr->reduction_scratchpad_size_per_kv_head *\n (use_gqa ? input.num_heads_kv : input.num_heads_q);\n DNNLScratchPadManager::get_dnnl_scratchpad_manager()->realloc(\n scratchpad_size);\n\n // metadata_ptr->print();\n\n // test out of boundary access\n // {\n // float* cache_ptr =\n // DNNLScratchPadManager::get_dnnl_scratchpad_manager()->get_data<float>();\n // for (int64_t i = 0; i < scratchpad_size / sizeof(float); ++i) {\n // cache_ptr[i] = std::numeric_limits<float>::quiet_NaN();\n // }\n // }\n\n return metadata_tensor;\n }\n\n FORCE_INLINE static std::pair<int32_t, int32_t> calcu_kv_tile_pos(\n int32_t kv_left_pos, int32_t kv_right_pos, int32_t q_left_pos,\n int32_t q_right_pos, int32_t sliding_window_left,\n int32_t sliding_window_right) {\n if (sliding_window_left != -1) {\n kv_left_pos = std::max(kv_left_pos, q_left_pos - sliding_window_left);\n }\n if (sliding_window_right != -1) {\n kv_right_pos = std::min(kv_right_pos, q_right_pos + sliding_window_right);\n }\n return {kv_left_pos, kv_right_pos};\n }\n\n FORCE_INLINE static std::pair<int32_t, int32_t> align_kv_tile_pos(\n int32_t kv_left_pos, int32_t kv_right_pos, int32_t align_factor) {\n kv_left_pos = (kv_left_pos / align_factor) * align_factor;\n kv_right_pos =\n ((kv_right_pos + align_factor - 1) / align_factor) * align_factor;\n return {kv_left_pos, kv_right_pos};\n }\n\n static int64_t calcu_default_tile_size(int64_t cache_size, int64_t head_dim,\n int64_t elem_size,\n int64_t q_buffer_elem_size,\n int64_t logits_buffer_elem_size,\n int64_t output_buffer_elem_size,\n int64_t max_num_q_per_iter,\n int64_t round_size) {\n // For CPU, different from CUDA, Q@K^T results should also be hold in cache,\n // using float32. Intermediate outputs should be float32 to be compatible\n // with AMX Then the cache includes:\n // - Q: q_tile_size * head_dim * q_buffer_elem_size\n // - K, V: 2 * k_tile_size * head_dim * elem_size\n // - Q@K^T: max_num_q_per_iter * k_tile_size * logits_buffer_elem_size\n // - Intermediate outputs: q_tile_size * head_dim * output_buffer_elem_size\n // By default, let tile_size = q_tile_size = k_tile_size. To record\n // is_first_iter states in a static array, require the default tile <= 128 *\n // max_num_q_per_iter\n\n int64_t tile_size =\n cache_size / (head_dim * (q_buffer_elem_size + 2 * elem_size +\n output_buffer_elem_size) +\n max_num_q_per_iter * logits_buffer_elem_size);\n tile_size = std::min(tile_size, MaxQTileIterNum * max_num_q_per_iter);\n int64_t rounded_tile_size = (tile_size / round_size) * round_size;\n return std::max(rounded_tile_size, round_size);\n }\n\n static int64_t calcu_tile_size_with_constant_q(\n int64_t cache_size, int64_t head_dim, int64_t elem_size,\n int64_t q_buffer_elem_size, int64_t logits_buffer_elem_size,\n int64_t output_buffer_elem_size, int64_t max_num_q_per_iter,\n int64_t round_size, int64_t q_tile_size, bool one_round) {\n // calculate tile_size with known q_tile_size\n // If one_round is True, the outer Q tile loop time is 1, then the K,V will\n // not be included in the cache\n int64_t tile_size;\n if (one_round) {\n tile_size =\n (cache_size - q_tile_size * head_dim *\n (q_buffer_elem_size + output_buffer_elem_size)) /\n (logits_buffer_elem_size * max_num_q_per_iter);\n } else {\n tile_size =\n (cache_size - q_tile_size * head_dim *\n (q_buffer_elem_size + output_buffer_elem_size)) /\n (logits_buffer_elem_size * max_num_q_per_iter +\n 2 * head_dim * elem_size);\n }\n int64_t rounded_tile_size = (tile_size / round_size) * round_size;\n return std::max(rounded_tile_size, round_size);\n }\n\n static int64_t get_available_l2_size() {\n static int64_t size = []() {\n#if defined(__APPLE__)\n // macOS doesn't have _SC_LEVEL2_CACHE_SIZE. Use sysctlbyname.\n int64_t l2_cache_size = 0;\n size_t len = sizeof(l2_cache_size);\n if (sysctlbyname(\"hw.l2cachesize\", &l2_cache_size, &len, NULL, 0) == 0 &&\n l2_cache_size > 0) {\n return l2_cache_size >> 1; // use 50% of L2 cache\n }\n // Fallback if sysctlbyname fails\n return 128LL * 1024 >> 1; // use 50% of 128KB\n#else\n long l2_cache_size = sysconf(_SC_LEVEL2_CACHE_SIZE);\n TORCH_CHECK_NE(l2_cache_size, -1);\n return l2_cache_size >> 1; // use 50% of L2 cache\n#endif\n }();\n return size;\n }\n\n private:\n int64_t available_cache_size_;\n};\n\nstruct AttentionInput {\n AttentionMetadata* metadata;\n int32_t num_tokens;\n int32_t num_heads;\n int32_t num_kv_heads;\n int32_t block_size;\n void* query;\n int64_t query_num_tokens_stride;\n int64_t query_num_heads_stride;\n int64_t cache_num_blocks_stride;\n int64_t cache_num_kv_heads_stride;\n int64_t blt_num_tokens_stride;\n void* key_cache;\n void* value_cache;\n void* output;\n int32_t* query_start_loc;\n int32_t* seq_lens;\n int32_t* block_table;\n float* alibi_slopes;\n c10::BFloat16* s_aux;\n float scale;\n bool causal;\n int32_t sliding_window_left;\n int32_t sliding_window_right;\n float softcap;\n};\n\n#define DEFINE_CPU_ATTENTION_PARAMS \\\n q_buffer_t *__restrict__ q_heads_buffer, \\\n kv_cache_t *__restrict__ k_head_cache_ptr, \\\n kv_cache_t *__restrict__ v_head_cache_ptr, \\\n logits_buffer_t *__restrict__ logits_buffer, \\\n float *__restrict__ partial_q_buffer, float *__restrict__ max_buffer, \\\n float *__restrict__ sum_buffer, int32_t *__restrict__ block_table, \\\n const int32_t kv_tile_start_pos, const int32_t kv_tile_end_pos, \\\n const int32_t kv_tile_token_num, \\\n const int64_t kv_cache_num_blocks_stride, const int32_t q_head_num, \\\n const int32_t q_token_num, const int32_t q_tile_start_pos, \\\n const int32_t q_heads_per_kv, const int32_t block_size, \\\n const int32_t left_window_size, const int32_t right_window_size, \\\n float scale, const float softcap_scale, \\\n const float *__restrict__ alibi_slopes, const bool is_first_iter, \\\n const bool use_sink, const bool debug_info\n\n#define CPU_ATTENTION_PARAMS \\\n q_heads_buffer, k_head_cache_ptr, v_head_cache_ptr, logits_buffer, \\\n partial_q_buffer, max_buffer, sum_buffer, block_table, \\\n kv_tile_start_pos, kv_tile_end_pos, kv_tile_token_num, \\\n kv_cache_num_blocks_stride, q_head_num, q_token_num, q_tile_start_pos, \\\n q_heads_per_kv, block_size, left_window_size, right_window_size, scale, \\\n softcap_scale, alibi_slopes, is_first_iter, use_sink, debug_info\n\nenum class AttentionGemmPhase { QK, PV };\n\ntemplate <typename T>\nstruct VecTypeTrait {\n using vec_t = void;\n};\n\ntemplate <>\nstruct VecTypeTrait<float> {\n using vec_t = vec_op::FP32Vec16;\n};\n\n// ARM only supports BF16 with ARMv8.6-A extension\n#if (defined(__aarch64__) && !defined(ARM_BF16_SUPPORT))\n#else\ntemplate <>\nstruct VecTypeTrait<c10::BFloat16> {\n using vec_t = vec_op::BF16Vec16;\n};\n#endif\n\n#if !defined(__powerpc__) && !defined(__s390x__)\ntemplate <>\nstruct VecTypeTrait<c10::Half> {\n using vec_t = vec_op::FP16Vec16;\n};\n#endif\n\ntemplate <typename T>\nvoid print_logits(const char* name, T* ptr, int32_t row, int32_t col,\n int32_t stride) {\n std::stringstream ss;\n ss << std::fixed << std::setprecision(5) << name << \": [\\n\";\n auto* curr_logits_buffer = ptr;\n for (int32_t m = 0; m < row; ++m) {\n for (int32_t n = 0; n < col; ++n) {\n ss << curr_logits_buffer[n] << \", \";\n }\n ss << \"\\n\";\n curr_logits_buffer += stride;\n }\n ss << \"]\\n\";\n std::printf(\"%s\", ss.str().c_str());\n}\n\ntemplate <typename attention_impl_t>\nclass AttentionMainLoop {\n public:\n using query_t = typename attention_impl_t::query_t;\n using q_buffer_t = typename attention_impl_t::q_buffer_t;\n using kv_cache_t = typename attention_impl_t::kv_cache_t;\n using logits_buffer_t = typename attention_impl_t::logits_buffer_t;\n using partial_output_buffer_t =\n typename attention_impl_t::partial_output_buffer_t;\n using prob_buffer_t = typename attention_impl_t::prob_buffer_t;\n\n static constexpr int64_t max_q_head_num_per_iter =\n attention_impl_t::MaxQHeadNumPerIteration;\n static constexpr int64_t blocksize_alignment =\n attention_impl_t::BlockSizeAlignment;\n static constexpr int64_t headdim_alignment =\n attention_impl_t::HeadDimAlignment;\n static constexpr int64_t head_dim = attention_impl_t::HeadDim;\n static constexpr ISA ISAType = attention_impl_t::ISAType;\n static constexpr bool scale_on_logits =\n attention_impl_t::scale_on_logits; // apply scale on logits, otherwise\n // apply scale on q_buffer\n\n template <typename tile_gemm_t>\n class Attention {\n public:\n // Args:\n // - q_heads_buffer: [MaxQHeadNumPerIteration, head_dim]\n // - k_head_cache_ptr: [num_blocks, block_size * head_dim]\n // - v_head_cache_ptr: [num_blocks, block_size * head_dim]\n // - logits_buffer: [MaxQHeadNumPerIteration, kv_tile_token_num], store Q@K\n // - logits partial_q_buffer: [MaxQHeadNumPerIteration, head_dim], store\n // partial output\n // - max_buffer: [MaxQHeadNumPerIteration, 1], store max logits\n // - sum_buffer: [MaxQHeadNumPerIteration, 1], store sum of exp\n // - block_table\n // - kv_tile_start_pos: start position of KV cache, aligned to\n // BlockSizeAlignment\n // - kv_tile_end_pos: end position of KV cache, aligned to\n // BlockSizeAlignment\n // - kv_tile_token_num: KV token num, aligned to BlockSizeAlignment\n // - kv_cache_num_blocks_stride\n // - q_head_num: head num of q_tile\n // - q_token_num: token num of q_tile, should be q_head_num /\n // q_heads_per_kv\n // - q_tile_start_pos: start pos of the first token in q_heads_buffer\n // - q_heads_per_kv\n // - block_size\n // - left_window_size\n // - right_window_size\n // - scale\n // - softcap_scale\n // - alibi_slopes\n // - is_first_iter\n // - use_sink\n // - debug_info\n void operator()(DEFINE_CPU_ATTENTION_PARAMS) {\n // k_cache_token_group_stride: stride of K cache when move to next\n // BlockSizeAlignment tokens in a block\n const int64_t k_cache_token_group_stride =\n attention_impl_t::k_cache_token_group_stride(block_size);\n // v_cache_token_group_stride: stride of V cache when move to next\n // BlockSizeAlignment tokens in a block\n const int64_t v_cache_token_group_stride =\n attention_impl_t::v_cache_token_group_stride(block_size);\n // v_cache_head_group_stride: stride of V cache when move to next\n // HeadDimAlignment head dims in a block\n const int64_t v_cache_head_group_stride =\n attention_impl_t::v_cache_head_group_stride(block_size);\n const int32_t token_group_num = kv_tile_token_num / blocksize_alignment;\n const int32_t token_group_num_per_block =\n block_size / blocksize_alignment;\n const int32_t start_block_idx = kv_tile_start_pos / block_size;\n const int32_t start_block_offset = kv_tile_start_pos % block_size;\n const int32_t start_block_group_offset =\n start_block_offset / blocksize_alignment;\n const int32_t end_block_idx =\n (kv_tile_start_pos + kv_tile_token_num - 1) / block_size + 1;\n\n // compute Q@K logits\n {\n int32_t curr_group_offset =\n start_block_group_offset * k_cache_token_group_stride;\n int32_t curr_group_num_in_block =\n token_group_num_per_block - start_block_group_offset;\n int32_t remaining_group_num = token_group_num;\n logits_buffer_t* curr_logits_buffer = logits_buffer;\n for (int32_t block_idx = start_block_idx; block_idx < end_block_idx;\n ++block_idx) {\n int32_t physical_block_idx = block_table[block_idx];\n kv_cache_t* k_cache_block_ptr =\n k_head_cache_ptr +\n physical_block_idx * kv_cache_num_blocks_stride +\n curr_group_offset;\n curr_group_num_in_block =\n std::min(remaining_group_num, curr_group_num_in_block);\n\n for (int32_t block_group_idx = 0;\n block_group_idx < curr_group_num_in_block; ++block_group_idx) {\n // logits_tile = q_tile @ k_tile, [MaxQHeadNumPerIteration,\n // BlockSizeAlignment] = [MaxQHeadNumPerIteration, head_dim] @\n // [head_dim, BlockSizeAlignment]\n\n // By default, logits_buffer, q_buffer and k_cache are row-major,\n // but may be packed by ISA implementation.\n tile_gemm_t::template gemm<AttentionGemmPhase::QK, head_dim>(\n q_head_num, q_heads_buffer, k_cache_block_ptr,\n curr_logits_buffer, head_dim, block_size, kv_tile_token_num,\n block_size, head_dim, false);\n\n if constexpr (scale_on_logits) {\n float* __restrict__ scale_curr_logits_buffer = curr_logits_buffer;\n vec_op::FP32Vec16 scale_vec(scale);\n for (int32_t i = 0; i < q_head_num; ++i) {\n static_assert(blocksize_alignment % 16 == 0);\n constexpr int32_t vec_num = blocksize_alignment / 16;\n vec_op::unroll_loop<int32_t, vec_num>([&](int32_t vec_idx) {\n vec_op::FP32Vec16 vec(scale_curr_logits_buffer +\n vec_idx * 16);\n vec = vec * scale_vec;\n vec.save(scale_curr_logits_buffer + vec_idx * 16);\n });\n scale_curr_logits_buffer += kv_tile_token_num;\n }\n }\n\n // Move buffer ptrs\n k_cache_block_ptr += k_cache_token_group_stride;\n curr_logits_buffer += blocksize_alignment;\n }\n\n // Update\n remaining_group_num -= curr_group_num_in_block;\n curr_group_offset = 0;\n curr_group_num_in_block = token_group_num_per_block;\n }\n }\n\n // process logits\n {\n // if (debug_info){\n // print_logits(\"raw logits\", logits_buffer, q_head_num,\n // kv_tile_token_num, kv_tile_token_num);\n // }\n\n if (softcap_scale != 0.0f) {\n apply_softcap(logits_buffer, kv_tile_token_num, q_head_num,\n kv_tile_token_num, softcap_scale);\n // print_logits(\"softcap raw logits\", logits_buffer, q_head_num,\n // kv_tile_token_num, kv_tile_token_num);\n }\n\n if (alibi_slopes != nullptr) {\n apply_alibi_slopes(logits_buffer, alibi_slopes, kv_tile_token_num,\n q_tile_start_pos, kv_tile_start_pos, q_token_num,\n kv_tile_token_num, q_heads_per_kv);\n\n // print_logits(\"alibi raw logits\", logits_buffer, q_head_num,\n // kv_tile_token_num, kv_tile_token_num);\n }\n\n apply_mask(logits_buffer, kv_tile_token_num, q_tile_start_pos,\n kv_tile_start_pos, kv_tile_end_pos, q_token_num,\n q_heads_per_kv, left_window_size, right_window_size);\n\n // if (debug_info){\n // print_logits(\"masked logits\", logits_buffer, q_head_num,\n // kv_tile_token_num, kv_tile_token_num);\n // print_logits(\"old_max\", max_buffer, 1, q_head_num, q_head_num);\n // print_logits(\"old_sum\", sum_buffer, 1, q_head_num, q_head_num);\n // }\n\n apply_softmax(logits_buffer, partial_q_buffer, max_buffer, sum_buffer,\n kv_tile_token_num, q_head_num, kv_tile_token_num,\n is_first_iter, use_sink);\n\n // if (debug_info){\n // print_logits(\"softmax logits\",\n // reinterpret_cast<prob_buffer_t*>(logits_buffer), q_head_num,\n // kv_tile_token_num, kv_tile_token_num * sizeof(logits_buffer_t) /\n // sizeof(prob_buffer_t));\n // print_logits(\"new_max\", max_buffer, 1, q_head_num, q_head_num);\n // print_logits(\"new_sum\", sum_buffer, 1, q_head_num, q_head_num);\n // }\n }\n\n // compute P@V\n {\n int32_t curr_group_offset =\n start_block_group_offset * v_cache_token_group_stride;\n int32_t curr_group_num_in_block =\n token_group_num_per_block - start_block_group_offset;\n int32_t remaining_group_num = token_group_num;\n int32_t head_dim_group_num = head_dim / headdim_alignment;\n prob_buffer_t* curr_prob_buffer =\n reinterpret_cast<prob_buffer_t*>(logits_buffer);\n int64_t prob_buffer_stride =\n kv_tile_token_num *\n (sizeof(logits_buffer_t) / sizeof(prob_buffer_t));\n partial_output_buffer_t* curr_partial_q_buffer = partial_q_buffer;\n bool accum_c = !is_first_iter;\n for (int32_t block_idx = start_block_idx; block_idx < end_block_idx;\n ++block_idx) {\n int32_t physical_block_idx = block_table[block_idx];\n kv_cache_t* v_cache_block_ptr =\n v_head_cache_ptr +\n physical_block_idx * kv_cache_num_blocks_stride +\n curr_group_offset;\n curr_group_num_in_block =\n std::min(remaining_group_num, curr_group_num_in_block);\n int32_t curr_token_num =\n curr_group_num_in_block * blocksize_alignment;\n\n for (int32_t head_dim_group_idx = 0;\n head_dim_group_idx < head_dim_group_num; ++head_dim_group_idx) {\n // output_tile = p_tile @ v_tile, [MaxQHeadNumPerIteration,\n // HeadDimAlignment] = [MaxQHeadNumPerIteration, block_size] @\n // [block_size, HeadDimAlignment]\n tile_gemm_t::template gemm<AttentionGemmPhase::PV, -1>(\n q_head_num, curr_prob_buffer, v_cache_block_ptr,\n curr_partial_q_buffer, prob_buffer_stride, head_dim, head_dim,\n block_size, curr_token_num, accum_c);\n\n // Update\n curr_partial_q_buffer += headdim_alignment;\n v_cache_block_ptr += v_cache_head_group_stride;\n }\n\n // Update\n remaining_group_num -= curr_group_num_in_block;\n curr_group_offset = 0;\n curr_group_num_in_block = token_group_num_per_block;\n curr_prob_buffer += curr_token_num;\n curr_partial_q_buffer = partial_q_buffer;\n accum_c = true;\n }\n }\n // if (debug_info) {\n // print_logits(\"output\", partial_q_buffer, q_head_num, head_dim,\n // head_dim);\n // }\n }\n\n void apply_mask(logits_buffer_t* __restrict__ logits_buffer,\n const int64_t logits_buffer_stride,\n const int32_t q_tile_start_pos,\n const int32_t kv_tile_start_pos,\n const int32_t kv_tile_end_pos, const int32_t q_token_num,\n const int32_t q_heads_per_kv,\n const int32_t sliding_window_left,\n const int32_t sliding_window_right) {\n // Apply mask\n constexpr logits_buffer_t neg_inf =\n -std::numeric_limits<logits_buffer_t>::infinity();\n logits_buffer_t* __restrict__ curr_logits_buffer = logits_buffer;\n int32_t curr_token_pos = q_tile_start_pos;\n for (int32_t token_idx = 0; token_idx < q_token_num; ++token_idx) {\n int32_t left_kv_pos = [&]() {\n int32_t pos = kv_tile_start_pos;\n if (sliding_window_left != -1) {\n pos = std::max(pos, curr_token_pos - sliding_window_left);\n }\n return pos;\n }();\n\n int32_t right_kv_pos = [&]() {\n int32_t pos = kv_tile_end_pos;\n if (sliding_window_right != -1) {\n pos = std::min(pos,\n std::max(kv_tile_start_pos,\n curr_token_pos + sliding_window_right + 1));\n }\n return pos;\n }();\n\n int32_t left_invalid_token_num = left_kv_pos - kv_tile_start_pos;\n int32_t right_invalid_token_num = kv_tile_end_pos - right_kv_pos;\n for (int32_t head_idx = 0; head_idx < q_heads_per_kv; ++head_idx) {\n logits_buffer_t* __restrict__ curr_logits_buffer_tail =\n curr_logits_buffer + right_kv_pos - kv_tile_start_pos;\n for (int32_t i = 0; i < left_invalid_token_num; ++i) {\n curr_logits_buffer[i] = neg_inf;\n }\n for (int32_t i = 0; i < right_invalid_token_num; ++i) {\n curr_logits_buffer_tail[i] = neg_inf;\n }\n\n curr_logits_buffer += logits_buffer_stride;\n }\n\n ++curr_token_pos;\n }\n }\n\n void apply_softmax(logits_buffer_t* __restrict__ logits_buffer,\n float* __restrict__ partial_q_buffer,\n float* __restrict__ max_buffer,\n float* __restrict__ sum_buffer,\n const int64_t logits_buffer_stride, int32_t q_head_num,\n int32_t kv_tile_token_num, bool is_first_iter,\n bool use_sink) {\n#ifdef DEFINE_FAST_EXP\n DEFINE_FAST_EXP\n#endif\n using prob_buffer_vec_t = typename VecTypeTrait<prob_buffer_t>::vec_t;\n static_assert(sizeof(prob_buffer_t) <= sizeof(logits_buffer_t));\n\n logits_buffer_t* __restrict__ curr_logits_buffer = logits_buffer;\n float* __restrict__ curr_partial_q_buffer = partial_q_buffer;\n const int32_t vec_num = kv_tile_token_num / 16;\n const int32_t head_vec_num = head_dim / 16;\n for (int32_t i = 0; i < q_head_num; ++i) {\n float init_max_val = max_buffer[i];\n float init_sum_val = sum_buffer[i];\n\n // apply scale and compute max\n vec_op::FP32Vec16 max_vec(init_max_val);\n {\n logits_buffer_t* __restrict__ curr_logits_buffer_iter =\n curr_logits_buffer;\n for (int32_t j = 0; j < vec_num; ++j) {\n vec_op::FP32Vec16 vec(curr_logits_buffer_iter);\n max_vec = vec.max(max_vec);\n\n curr_logits_buffer_iter += 16;\n }\n }\n float new_max_val = max_vec.reduce_max();\n float rescale_factor = init_max_val - new_max_val;\n\n // use same rescale threshold with FA4.\n // https://github.com/Dao-AILab/flash-attention/blob/1b8e1e641c6a179be9a0538b7f40fd595050b735/flash_attn/cute/flash_fwd_sm100.py#L1271\n bool need_rescale = rescale_factor < -8.0;\n if (!need_rescale) {\n new_max_val = init_max_val;\n } else {\n max_buffer[i] = new_max_val;\n }\n\n // sub max, compute exp and sum\n max_vec = vec_op::FP32Vec16(new_max_val);\n vec_op::FP32Vec16 sum_vec(0.0);\n {\n logits_buffer_t* __restrict__ curr_logits_buffer_iter =\n curr_logits_buffer;\n prob_buffer_t* __restrict__ curr_prob_buffer_iter =\n reinterpret_cast<prob_buffer_t*>(curr_logits_buffer);\n for (int32_t j = 0; j < vec_num; ++j) {\n vec_op::FP32Vec16 vec(curr_logits_buffer_iter);\n vec = vec - max_vec;\n\n // compute exp\n#ifdef DEFINE_FAST_EXP\n vec = fast_exp(vec);\n prob_buffer_vec_t output_vec(vec);\n output_vec.save(curr_prob_buffer_iter);\n#else\n vec.save(curr_logits_buffer_iter);\n for (int32_t k = 0; k < 16; ++k) {\n curr_logits_buffer_iter[k] = std::exp(curr_logits_buffer_iter[k]);\n }\n vec = vec_op::FP32Vec16(curr_logits_buffer_iter);\n#endif\n\n sum_vec = sum_vec + vec;\n\n curr_logits_buffer_iter += 16;\n curr_prob_buffer_iter += 16;\n }\n }\n float new_sum_val = sum_vec.reduce_sum();\n\n // rescale sum and partial outputs\n if (need_rescale) {\n // compute rescale factor\n#ifdef DEFINE_FAST_EXP\n vec_op::FP32Vec16 rescale_factor_vec(rescale_factor);\n rescale_factor_vec = fast_exp(rescale_factor_vec);\n rescale_factor = rescale_factor_vec.get_last_elem();\n#else\n rescale_factor = std::exp(rescale_factor);\n vec_op::FP32Vec16 rescale_factor_vec(rescale_factor);\n#endif\n\n // rescale sum\n new_sum_val += rescale_factor * init_sum_val;\n\n // rescale output\n if (!is_first_iter) {\n float* __restrict__ curr_partial_q_buffer_iter =\n curr_partial_q_buffer;\n for (int32_t j = 0; j < head_vec_num; ++j) {\n vec_op::FP32Vec16 vec(curr_partial_q_buffer_iter);\n vec = vec * rescale_factor_vec;\n vec.save(curr_partial_q_buffer_iter);\n\n curr_partial_q_buffer_iter += 16;\n }\n }\n } else {\n new_sum_val += init_sum_val;\n }\n\n sum_buffer[i] = new_sum_val;\n\n curr_logits_buffer += logits_buffer_stride;\n curr_partial_q_buffer += head_dim;\n }\n }\n\n void apply_softcap(logits_buffer_t* __restrict__ logits_buffer,\n const int64_t logits_buffer_stride, int32_t q_head_num,\n int32_t kv_tile_token_num, float softcap_scale) {\n#ifdef DEFINE_FAST_EXP\n DEFINE_FAST_EXP\n#endif\n float inv_softcap_scale = 1.0 / softcap_scale;\n vec_op::FP32Vec16 softcap_scale_vec(softcap_scale);\n vec_op::FP32Vec16 inv_softcap_scale_vec(inv_softcap_scale);\n vec_op::FP32Vec16 ones_vec(1.0);\n logits_buffer_t* __restrict__ curr_logits_buffer = logits_buffer;\n const int32_t vec_num = kv_tile_token_num / 16;\n for (int32_t i = 0; i < q_head_num; ++i) {\n logits_buffer_t* __restrict__ curr_logits_buffer_iter =\n curr_logits_buffer;\n for (int32_t j = 0; j < vec_num; ++j) {\n vec_op::FP32Vec16 vec(curr_logits_buffer_iter);\n vec = vec * inv_softcap_scale_vec;\n\n#ifdef DEFINE_FAST_EXP\n vec = fast_exp(vec);\n vec_op::FP32Vec16 inv_vec = ones_vec / vec;\n vec = (vec - inv_vec) / (vec + inv_vec);\n#else\n vec.save(curr_logits_buffer_iter);\n for (int k = 0; k < 16; ++k) {\n curr_logits_buffer_iter[k] = std::tanh(curr_logits_buffer_iter[k]);\n }\n vec = vec_op::FP32Vec16(curr_logits_buffer_iter);\n#endif\n vec = vec * softcap_scale_vec;\n vec.save(curr_logits_buffer_iter);\n\n curr_logits_buffer_iter += 16;\n }\n\n curr_logits_buffer += logits_buffer_stride;\n }\n }\n\n void apply_alibi_slopes(logits_buffer_t* __restrict__ logits_buffer,\n const float* __restrict__ alibi_slopes,\n const int64_t logits_buffer_stride,\n const int32_t q_tile_start_pos,\n const int32_t kv_tile_start_pos,\n const int32_t q_token_num,\n const int32_t kv_tile_token_num,\n const int32_t q_heads_per_kv) {\n alignas(64) constexpr float initial_arange_vals[16] = {\n 0.0f, 1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 6.0f, 7.0f,\n 8.0f, 9.0f, 10.0f, 11.0f, 12.0f, 13.0f, 14.0f, 15.0f};\n const int32_t vec_num = kv_tile_token_num / 16;\n\n vec_op::FP32Vec16 initial_arange_vals_vec(initial_arange_vals);\n initial_arange_vals_vec =\n initial_arange_vals_vec + vec_op::FP32Vec16((float)kv_tile_start_pos);\n vec_op::FP32Vec16 pos_offset_vec(16.0);\n logits_buffer_t* __restrict__ curr_logits_buffer = logits_buffer;\n for (int32_t i = 0; i < q_token_num; ++i) {\n vec_op::FP32Vec16 curr_q_pos_vec((float)(i + q_tile_start_pos));\n for (int32_t j = 0; j < q_heads_per_kv; ++j) {\n vec_op::FP32Vec16 alibi_scale_vec(alibi_slopes[j]);\n vec_op::FP32Vec16 curr_kv_pos_vec(initial_arange_vals_vec);\n logits_buffer_t* __restrict__ curr_logits_buffer_iter =\n curr_logits_buffer;\n for (int32_t k = 0; k < vec_num; ++k) {\n vec_op::FP32Vec16 alibi_bias_vec =\n alibi_scale_vec * (curr_kv_pos_vec - curr_q_pos_vec);\n vec_op::FP32Vec16 vec(curr_logits_buffer_iter);\n vec = vec + alibi_bias_vec;\n\n vec.save(curr_logits_buffer_iter);\n\n curr_kv_pos_vec = curr_kv_pos_vec + pos_offset_vec;\n curr_logits_buffer_iter += 16;\n }\n curr_logits_buffer += logits_buffer_stride;\n }\n }\n }\n };\n\n public:\n void operator()(const AttentionInput* input) {\n const int thread_num = omp_get_max_threads();\n TORCH_CHECK_EQ(input->metadata->thread_num, thread_num);\n std::atomic<int32_t> guard_counter(0);\n std::atomic<int32_t>* guard_counter_ptr = &guard_counter;\n\n#pragma omp parallel for schedule(static, 1)\n for (int thread_id = 0; thread_id < thread_num; ++thread_id) {\n AttentionMetadata& metadata = *input->metadata;\n if (metadata.workitem_group_num == 0) {\n continue;\n }\n\n attention_impl_t attn_impl;\n\n // general information\n const int32_t q_head_num = input->num_heads;\n const int32_t kv_head_num = input->num_kv_heads;\n const int32_t q_heads_per_kv = q_head_num / kv_head_num;\n const bool use_gqa =\n (max_q_head_num_per_iter % q_heads_per_kv == 0) ? true : false;\n const int32_t actual_kv_head_num = use_gqa ? kv_head_num : q_head_num;\n const int32_t actual_q_heads_per_kv = use_gqa ? q_heads_per_kv : 1;\n TORCH_CHECK_LE(actual_q_heads_per_kv, max_q_head_num_per_iter);\n const int32_t max_q_token_num_per_iter =\n max_q_head_num_per_iter / actual_q_heads_per_kv;\n const int64_t q_token_num_stride = input->query_num_tokens_stride;\n const int64_t q_head_num_stride = input->query_num_heads_stride;\n const int64_t kv_cache_head_num_stride = input->cache_num_kv_heads_stride;\n const int64_t kv_cache_block_num_stride = input->cache_num_blocks_stride;\n const int32_t sliding_window_left = input->sliding_window_left;\n const int32_t sliding_window_right = input->sliding_window_right;\n const int32_t block_size = input->block_size;\n const float scale = input->scale;\n const float softcap_scale = input->softcap;\n const float* alibi_slopes = input->alibi_slopes;\n const c10::BFloat16* s_aux = input->s_aux;\n\n const bool casual = input->causal;\n int32_t* const block_table = input->block_table;\n const int64_t block_table_stride = input->blt_num_tokens_stride;\n\n // init buffers\n void* scratchpad_ptr =\n DNNLScratchPadManager::get_dnnl_scratchpad_manager()\n ->get_data<void>();\n AttentionScratchPad buffer_manager(thread_id, metadata, scratchpad_ptr);\n\n const int32_t total_reduction_split_num = metadata.reduction_split_num;\n if (metadata.reduction_split_num > 0) {\n // reset split flag\n for (int32_t head_idx = thread_id; head_idx < actual_kv_head_num;\n head_idx += thread_num) {\n buffer_manager.update(head_idx, total_reduction_split_num, head_dim,\n 0, sizeof(partial_output_buffer_t));\n volatile bool* __restrict__ curr_flag_ptr =\n buffer_manager.get_reduce_flag_buffer();\n for (int32_t split_idx = 0; split_idx < total_reduction_split_num;\n ++split_idx) {\n curr_flag_ptr[split_idx] = false;\n }\n }\n }\n\n const int64_t available_cache_size =\n AttentionScheduler::get_available_l2_size();\n const int32_t default_tile_size =\n AttentionScheduler::calcu_default_tile_size(\n available_cache_size, head_dim, sizeof(kv_cache_t),\n sizeof(q_buffer_t), sizeof(logits_buffer_t),\n sizeof(partial_output_buffer_t), max_q_head_num_per_iter,\n max_q_head_num_per_iter);\n const int32_t default_q_tile_token_num =\n default_tile_size / actual_q_heads_per_kv;\n\n AttentionWorkItemGroup* const workitem_groups =\n metadata.workitem_groups_ptr;\n const int32_t* cu_workitem_num_per_thread =\n metadata.cu_workitem_num_per_thread;\n ReductionWorkItemGroup* const reduction_items =\n metadata.reduction_items_ptr;\n\n const int32_t effective_thread_num = metadata.effective_thread_num;\n const int32_t reduction_item_num = metadata.reduction_item_num;\n const int32_t split_kv_q_token_num_threshold =\n metadata.split_kv_q_token_num_threshold;\n const int32_t workitem_groups_counter_num =\n actual_kv_head_num * effective_thread_num;\n const int32_t reduction_items_counter_num =\n actual_kv_head_num * reduction_item_num;\n const int32_t total_counter_num =\n workitem_groups_counter_num + reduction_items_counter_num;\n\n if (metadata.reduction_split_num > 0) {\n ++(*guard_counter_ptr);\n while (guard_counter_ptr->load() != thread_num) {\n#ifdef FAST_SPINNING\n FAST_SPINNING\n#else\n std::this_thread::yield();\n#endif\n }\n }\n\n // main loop\n for (;;) {\n int64_t task_idx = metadata.acquire_counter();\n\n if (task_idx >= total_counter_num) {\n // no more tasks, leave loop\n break;\n }\n\n if (task_idx < workitem_groups_counter_num) {\n // attention task\n // map task_idx to workitem_groups\n const int32_t kv_head_idx = task_idx / effective_thread_num;\n const int32_t thread_offset = task_idx % effective_thread_num;\n AttentionWorkItemGroup* const curr_workitem_groups =\n workitem_groups + cu_workitem_num_per_thread[thread_offset];\n const int32_t curr_workitem_groups_num =\n cu_workitem_num_per_thread[thread_offset + 1] -\n cu_workitem_num_per_thread[thread_offset];\n\n const int32_t q_head_start_idx = kv_head_idx * actual_q_heads_per_kv;\n\n for (int32_t workitem_group_idx = 0;\n workitem_group_idx < curr_workitem_groups_num;\n ++workitem_group_idx) {\n AttentionWorkItemGroup* const current_workitem_group =\n &curr_workitem_groups[workitem_group_idx];\n\n const int32_t current_group_idx = current_workitem_group->req_id;\n const int32_t kv_start_pos =\n current_workitem_group->kv_split_pos_start;\n const int32_t kv_end_pos = current_workitem_group->kv_split_pos_end;\n const int32_t curr_spilt_id = current_workitem_group->split_id;\n const int32_t q_token_id_start =\n current_workitem_group->q_token_id_start;\n const int32_t q_token_num = current_workitem_group->q_token_num;\n\n // taskgroup general information\n const int32_t q_end = input->query_start_loc[current_group_idx + 1];\n const int32_t q_start = input->query_start_loc[current_group_idx];\n const int32_t seq_len = input->seq_lens[current_group_idx];\n const int32_t q_start_pos =\n (casual ? seq_len - (q_end - q_start) : 0);\n const int32_t block_num = (seq_len + block_size - 1) / block_size;\n // Only apply sink for the first KV split\n bool use_sink = (s_aux != nullptr &&\n current_workitem_group->local_split_id == 0);\n\n for (int32_t q_token_offset = 0; q_token_offset < q_token_num;\n q_token_offset += default_q_tile_token_num) {\n bool first_iter_flag[AttentionScheduler::MaxQTileIterNum];\n for (int32_t i = 0; i < AttentionScheduler::MaxQTileIterNum;\n ++i) {\n first_iter_flag[i] = true;\n }\n\n const int32_t q_token_start_idx =\n q_start + q_token_offset + q_token_id_start;\n const int32_t actual_q_token_num = std::min(\n default_q_tile_token_num, q_token_num - q_token_offset);\n const int32_t q_head_tile_size =\n actual_q_token_num * actual_q_heads_per_kv;\n const int32_t rounded_q_head_tile_size =\n ((q_head_tile_size + max_q_head_num_per_iter - 1) /\n max_q_head_num_per_iter) *\n max_q_head_num_per_iter;\n const int32_t kv_tile_size =\n AttentionScheduler::calcu_tile_size_with_constant_q(\n available_cache_size, head_dim, sizeof(kv_cache_t),\n sizeof(q_buffer_t), sizeof(logits_buffer_t),\n sizeof(partial_output_buffer_t), max_q_head_num_per_iter,\n blocksize_alignment, rounded_q_head_tile_size,\n rounded_q_head_tile_size <= max_q_head_num_per_iter);\n\n // update buffers\n buffer_manager.update(\n head_dim, sizeof(q_buffer_t), sizeof(logits_buffer_t),\n sizeof(partial_output_buffer_t), max_q_head_num_per_iter,\n rounded_q_head_tile_size, kv_tile_size);\n q_buffer_t* q_buffer = buffer_manager.get_q_buffer<q_buffer_t>();\n float* logits_buffer = buffer_manager.get_logits_buffer();\n float* partial_q_buffer = buffer_manager.get_output_buffer();\n float* max_buffer = buffer_manager.get_max_buffer();\n float* sum_buffer = buffer_manager.get_sum_buffer();\n\n const int32_t q_tile_start_pos =\n q_start_pos + q_token_offset + q_token_id_start;\n const int32_t q_tile_end_pos =\n q_tile_start_pos + actual_q_token_num;\n const auto [kv_tile_start_pos, kv_tile_end_pos] =\n AttentionScheduler::calcu_kv_tile_pos(\n kv_start_pos, kv_end_pos, q_tile_start_pos,\n q_tile_end_pos, sliding_window_left,\n sliding_window_right);\n const auto [rounded_kv_tile_start_pos, rounded_kv_tile_end_pos] =\n AttentionScheduler::align_kv_tile_pos(\n kv_tile_start_pos, kv_tile_end_pos, blocksize_alignment);\n\n int32_t curr_kv_head_idx =\n use_gqa ? kv_head_idx\n : (kv_head_idx /\n q_heads_per_kv); // for GQA disabled case\n\n // std::printf(\"thread_id: %d, req_id: %d, q_token_start: %d,\n // q_token_end: %d, q_head_start: %d, q_head_end: %d, kv_head_idx:\n // %d, kv_pos_start: %d, kv_pos_end: %d\\n\",\n // thread_id, current_group_idx,\n // q_token_start_idx, q_token_start_idx +\n // actual_q_token_num, q_head_start_idx,\n // q_head_start_idx + actual_q_heads_per_kv,\n // curr_kv_head_idx, kv_tile_start_pos,\n // kv_tile_end_pos);\n\n // move buffers\n kv_cache_t* curr_k_cache =\n reinterpret_cast<kv_cache_t*>(input->key_cache) +\n curr_kv_head_idx * kv_cache_head_num_stride;\n kv_cache_t* curr_v_cache =\n reinterpret_cast<kv_cache_t*>(input->value_cache) +\n curr_kv_head_idx * kv_cache_head_num_stride;\n query_t* const q_tile_ptr =\n reinterpret_cast<query_t*>(input->query) +\n q_token_start_idx * q_token_num_stride +\n q_head_start_idx * q_head_num_stride;\n size_t output_buffer_offset =\n q_token_start_idx * q_head_num * head_dim +\n q_head_start_idx * head_dim;\n int32_t* curr_block_table =\n block_table + current_group_idx * block_table_stride;\n const float* curr_alibi_slopes =\n (alibi_slopes != nullptr ? alibi_slopes + q_head_start_idx\n : nullptr);\n const c10::BFloat16* curr_s_aux =\n (s_aux != nullptr ? s_aux + q_head_start_idx : nullptr);\n\n // copy the Q tile to q_buffer, the logical layout of q_buffer is\n // [actual_q_token_num, actual_q_heads_per_kv, head_dim]\n {\n attn_impl.copy_q_heads_tile(\n q_tile_ptr, q_buffer, actual_q_token_num,\n actual_q_heads_per_kv, q_token_num_stride,\n q_head_num_stride, scale);\n }\n\n if (use_sink) {\n alignas(64) float s_aux_fp32[16];\n#if defined(__aarch64__) && !defined(ARM_BF16_SUPPORT)\n // ARM without native BF16 support: manual conversion\n for (int i = 0; i < 16; ++i) {\n s_aux_fp32[i] = static_cast<float>(curr_s_aux[i]);\n }\n#else\n // All other platforms have BF16Vec16 available\n vec_op::BF16Vec16 vec_bf16(curr_s_aux);\n vec_op::FP32Vec16 vec_fp32(vec_bf16);\n vec_fp32.save(s_aux_fp32);\n#endif\n\n float* __restrict__ curr_sum_buffer = sum_buffer;\n float* __restrict__ curr_max_buffer = max_buffer;\n for (int32_t token_idx = 0; token_idx < actual_q_token_num;\n ++token_idx) {\n for (int32_t head_idx = 0; head_idx < actual_q_heads_per_kv;\n ++head_idx) {\n curr_sum_buffer[head_idx] = 1.0f;\n curr_max_buffer[head_idx] = s_aux_fp32[head_idx];\n }\n\n curr_sum_buffer += actual_q_heads_per_kv;\n curr_max_buffer += actual_q_heads_per_kv;\n }\n } else {\n float* __restrict__ curr_sum_buffer = sum_buffer;\n float* __restrict__ curr_max_buffer = max_buffer;\n for (int32_t token_idx = 0; token_idx < actual_q_token_num;\n ++token_idx) {\n for (int32_t head_idx = 0; head_idx < actual_q_heads_per_kv;\n ++head_idx) {\n curr_sum_buffer[head_idx] = 0.0f;\n curr_max_buffer[head_idx] =\n std::numeric_limits<float>::lowest();\n }\n\n curr_sum_buffer += actual_q_heads_per_kv;\n curr_max_buffer += actual_q_heads_per_kv;\n }\n }\n\n // compute loop\n for (int32_t kv_tile_pos = rounded_kv_tile_start_pos;\n kv_tile_pos < rounded_kv_tile_end_pos;\n kv_tile_pos += kv_tile_size) {\n const int32_t kv_tile_pos_left = kv_tile_pos;\n const int32_t kv_tile_pos_right = std::min(\n kv_tile_pos_left + kv_tile_size, rounded_kv_tile_end_pos);\n for (int32_t q_head_tile_token_offset = 0;\n q_head_tile_token_offset < actual_q_token_num;\n q_head_tile_token_offset += max_q_token_num_per_iter) {\n const int32_t q_tile_pos_left =\n q_tile_start_pos + q_head_tile_token_offset;\n const int32_t q_tile_token_num =\n std::min(max_q_token_num_per_iter,\n actual_q_token_num - q_head_tile_token_offset);\n const int32_t q_tile_head_offset =\n q_head_tile_token_offset * actual_q_heads_per_kv;\n const int32_t q_tile_head_num =\n q_tile_token_num * actual_q_heads_per_kv;\n const int32_t q_tile_pos_right =\n q_tile_pos_left + q_tile_token_num;\n const auto [actual_kv_tile_pos_left,\n actual_kv_tile_pos_right] =\n AttentionScheduler::calcu_kv_tile_pos(\n kv_tile_pos_left, kv_tile_pos_right, q_tile_pos_left,\n q_tile_pos_right, sliding_window_left,\n sliding_window_right);\n const int32_t q_iter_idx =\n q_head_tile_token_offset / max_q_token_num_per_iter;\n\n if (actual_kv_tile_pos_right <= actual_kv_tile_pos_left) {\n continue;\n }\n\n // align kv_pos to blocksize_alignment\n const auto [aligned_actual_kv_tile_pos_left,\n aligned_actual_kv_tile_pos_right] =\n AttentionScheduler::align_kv_tile_pos(\n actual_kv_tile_pos_left, actual_kv_tile_pos_right,\n blocksize_alignment);\n const int32_t actual_kv_token_num =\n aligned_actual_kv_tile_pos_right -\n aligned_actual_kv_tile_pos_left;\n\n // std::printf(\"\\tq_iter_idx: %d, q_token_start: %d,\n // q_token_end: %d, q_token_num: %d, q_head_num: %d,\n // q_pos_start: %d, q_pos_end: %d, kv_pos_start: %d,\n // kv_pos_end: %d\\n\",\n // q_iter_idx, q_token_start_idx +\n // q_head_tile_token_offset, q_token_start_idx +\n // q_head_tile_token_offset + q_tile_token_num,\n // q_tile_token_num, q_tile_head_num,\n // q_tile_pos_left, q_tile_pos_right,\n // aligned_actual_kv_tile_pos_left,\n // aligned_actual_kv_tile_pos_right);\n\n // Move buffers\n q_buffer_t* curr_q_heads_buffer =\n q_buffer + q_tile_head_offset * head_dim;\n float* curr_partial_q_buffer =\n partial_q_buffer + q_tile_head_offset * head_dim;\n float* curr_max_buffer = max_buffer + q_tile_head_offset;\n float* curr_sum_buffer = sum_buffer + q_tile_head_offset;\n\n bool debug_info = false;\n // bool debug_info = (\n // q_head_start_idx == 4 &&\n // (q_token_start_idx + q_head_tile_token_offset) <=\n // 4\n // && (q_token_start_idx + q_head_tile_token_offset +\n // q_tile_token_num) > 4\n // );\n // if (debug_info) {\n // std::printf(\"\\tq_iter_idx: %d, q_token_start: %d,\"\n // \"q_token_end: %d, q_token_num: %d, q_head_num: %d,\"\n // \"q_pos_start: %d, q_pos_end: %d, kv_pos_start: %d,\"\n // \"kv_pos_end: %d\\n\",\n // q_iter_idx, q_token_start_idx +\n // q_head_tile_token_offset, q_token_start_idx\n // + q_head_tile_token_offset +\n // q_tile_token_num, q_tile_token_num,\n // q_tile_head_num, q_tile_pos_left,\n // q_tile_pos_right,\n // aligned_actual_kv_tile_pos_left,\n // aligned_actual_kv_tile_pos_right);\n // }\n\n attn_impl.template execute_attention<Attention>(\n curr_q_heads_buffer, curr_k_cache, curr_v_cache,\n logits_buffer, curr_partial_q_buffer, curr_max_buffer,\n curr_sum_buffer, curr_block_table,\n aligned_actual_kv_tile_pos_left,\n aligned_actual_kv_tile_pos_right, actual_kv_token_num,\n kv_cache_block_num_stride, q_tile_head_num,\n q_tile_token_num, q_tile_pos_left, actual_q_heads_per_kv,\n block_size, sliding_window_left, sliding_window_right,\n scale, softcap_scale, curr_alibi_slopes,\n first_iter_flag[q_iter_idx], use_sink, debug_info);\n first_iter_flag[q_iter_idx] = false;\n }\n }\n\n // write back partial results to output buffer or reduction buffer\n {\n if (curr_spilt_id == -1) {\n final_output(partial_q_buffer,\n reinterpret_cast<query_t*>(input->output) +\n output_buffer_offset,\n sum_buffer, actual_q_heads_per_kv,\n actual_q_token_num, q_head_num);\n } else {\n const int32_t stride =\n actual_q_heads_per_kv * split_kv_q_token_num_threshold;\n buffer_manager.update(kv_head_idx, total_reduction_split_num,\n head_dim, stride, sizeof(float));\n volatile bool* split_flag_buffer =\n buffer_manager.get_reduce_flag_buffer() + curr_spilt_id;\n float* split_output_buffer =\n buffer_manager.get_reduce_output_buffer() +\n curr_spilt_id * stride * head_dim;\n float* split_max_buffer =\n buffer_manager.get_reduce_max_buffer() +\n curr_spilt_id * stride;\n float* split_sum_buffer =\n buffer_manager.get_reduce_sum_buffer() +\n curr_spilt_id * stride;\n\n partial_output(partial_q_buffer, max_buffer, sum_buffer,\n q_head_tile_size, split_output_buffer,\n split_max_buffer, split_sum_buffer,\n split_flag_buffer);\n }\n }\n }\n }\n } else {\n task_idx -= workitem_groups_counter_num;\n const int32_t kv_head_idx = task_idx / reduction_item_num;\n const int32_t item_offset = task_idx % reduction_item_num;\n ReductionWorkItemGroup* const curr_workitem_groups =\n reduction_items + item_offset;\n const int32_t curr_output_token_idx =\n curr_workitem_groups->q_token_id_start;\n const int32_t curr_output_token_num =\n curr_workitem_groups->q_token_id_num;\n const int32_t curr_split_id = curr_workitem_groups->split_start_id;\n const int32_t curr_split_num = curr_workitem_groups->split_num;\n const int32_t current_group_idx = curr_workitem_groups->req_id;\n const int32_t curr_output_head_num =\n curr_output_token_num * actual_q_heads_per_kv;\n\n const int32_t q_start = input->query_start_loc[current_group_idx];\n const int32_t q_token_start_idx = q_start + curr_output_token_idx;\n const int32_t q_head_start_idx = kv_head_idx * actual_q_heads_per_kv;\n size_t output_buffer_offset =\n q_token_start_idx * q_head_num * head_dim +\n q_head_start_idx * head_dim;\n\n const int32_t stride =\n actual_q_heads_per_kv * split_kv_q_token_num_threshold;\n buffer_manager.update(kv_head_idx, total_reduction_split_num,\n head_dim, stride, sizeof(float));\n volatile bool* split_flag_buffer =\n buffer_manager.get_reduce_flag_buffer() + curr_split_id;\n float* split_output_buffer =\n buffer_manager.get_reduce_output_buffer() +\n curr_split_id * stride * head_dim;\n float* split_max_buffer =\n buffer_manager.get_reduce_max_buffer() + curr_split_id * stride;\n float* split_sum_buffer =\n buffer_manager.get_reduce_sum_buffer() + curr_split_id * stride;\n\n reduce_splits(split_output_buffer, split_max_buffer, split_sum_buffer,\n split_flag_buffer, stride, curr_output_head_num,\n curr_split_num);\n final_output(\n split_output_buffer,\n reinterpret_cast<query_t*>(input->output) + output_buffer_offset,\n split_sum_buffer, actual_q_heads_per_kv, curr_output_token_num,\n q_head_num);\n }\n }\n }\n // Reset counter for next call\n input->metadata->reset_counter();\n }\n\n void reduce_splits(float* __restrict__ split_output_buffer,\n float* __restrict__ split_max_buffer,\n float* __restrict__ split_sum_buffer,\n volatile bool* __restrict__ flags,\n const int32_t head_num_per_split,\n const int32_t curr_head_num, const int32_t split_num) {\n#ifdef DEFINE_FAST_EXP\n DEFINE_FAST_EXP\n#endif\n // restrict curr_head_num <= 16 in the scheduler\n // elems in split_max_buffer, split_sum_buffer are not cache alignment, use\n // local buffers to reduce false-sharing\n alignas(64) float local_max[16];\n alignas(64) float local_sum[16];\n\n float* __restrict__ curr_split_output_buffer = split_output_buffer;\n float* __restrict__ curr_split_max_buffer = split_max_buffer;\n float* __restrict__ curr_split_sum_buffer = split_sum_buffer;\n constexpr int32_t head_dim_group_num = head_dim / 16;\n for (int32_t split_idx = 0; split_idx < split_num; ++split_idx) {\n while (!flags[split_idx]) {\n#ifdef FAST_SPINNING\n FAST_SPINNING\n#else\n std::this_thread::yield();\n#endif\n }\n std::atomic_thread_fence(std::memory_order_acquire);\n\n if (split_idx > 0) {\n float* __restrict__ curr_output_buffer = split_output_buffer;\n float* __restrict__ curr_split_output_buffer_iter =\n curr_split_output_buffer;\n for (int32_t head_idx = 0; head_idx < curr_head_num; ++head_idx) {\n float final_max = local_max[head_idx];\n float curr_max = curr_split_max_buffer[head_idx];\n float final_sum = local_sum[head_idx];\n float curr_sum = curr_split_sum_buffer[head_idx];\n float* __restrict__ non_scale_output_iter =\n final_max > curr_max ? curr_output_buffer\n : curr_split_output_buffer_iter;\n float* __restrict__ scale_output_iter =\n final_max > curr_max ? curr_split_output_buffer_iter\n : curr_output_buffer;\n float rescale_factor = final_max > curr_max ? curr_max - final_max\n : final_max - curr_max;\n\n#ifdef DEFINE_FAST_EXP\n vec_op::FP32Vec16 rescale_factor_vec(rescale_factor);\n rescale_factor_vec = fast_exp(rescale_factor_vec);\n rescale_factor = rescale_factor_vec.get_last_elem();\n#else\n rescale_factor = std::exp(rescale_factor);\n vec_op::FP32Vec16 rescale_factor_vec(rescale_factor);\n#endif\n\n local_sum[head_idx] = final_max > curr_max\n ? final_sum + rescale_factor * curr_sum\n : rescale_factor * final_sum + curr_sum;\n\n final_max = std::max(final_max, curr_max);\n local_max[head_idx] = final_max;\n for (int32_t i = 0; i < head_dim_group_num; ++i) {\n vec_op::FP32Vec16 non_scale_vec(non_scale_output_iter);\n vec_op::FP32Vec16 scale_vec(scale_output_iter);\n vec_op::FP32Vec16 final_vec =\n non_scale_vec + scale_vec * rescale_factor_vec;\n final_vec.save(curr_output_buffer);\n\n non_scale_output_iter += 16;\n scale_output_iter += 16;\n curr_output_buffer += 16;\n }\n curr_split_output_buffer_iter += head_dim;\n }\n } else {\n vec_op::FP32Vec16 final_max(split_max_buffer);\n final_max.save(local_max);\n vec_op::FP32Vec16 final_sum(split_sum_buffer);\n final_sum.save(local_sum);\n }\n\n curr_split_output_buffer += head_num_per_split * head_dim;\n curr_split_max_buffer += head_num_per_split;\n curr_split_sum_buffer += head_num_per_split;\n }\n // write back final max and sum\n for (int32_t i = 0; i < curr_head_num; ++i) {\n split_max_buffer[i] = local_max[i];\n split_sum_buffer[i] = local_sum[i];\n }\n }\n\n void partial_output(float* __restrict__ partial_output_buffer,\n float* __restrict__ partial_max_buffer,\n float* __restrict__ partial_sum_buffer,\n int32_t curr_head_num,\n float* __restrict__ split_output_buffer,\n float* __restrict__ split_max_buffer,\n float* __restrict__ split_sum_buffer,\n volatile bool* __restrict__ flag) {\n float* __restrict__ curr_partial_output_buffer = partial_output_buffer;\n float* __restrict__ curr_split_output_buffer = split_output_buffer;\n constexpr int32_t head_dim_group_num = head_dim / 16;\n for (int32_t i = 0; i < curr_head_num; ++i) {\n split_max_buffer[i] = partial_max_buffer[i];\n split_sum_buffer[i] = partial_sum_buffer[i];\n for (int32_t j = 0; j < head_dim_group_num; ++j) {\n vec_op::FP32Vec16 vec(curr_partial_output_buffer);\n vec.save(curr_split_output_buffer);\n\n curr_partial_output_buffer += 16;\n curr_split_output_buffer += 16;\n }\n }\n std::atomic_thread_fence(std::memory_order_release);\n *flag = true;\n }\n\n void final_output(float* __restrict__ partial_q_buffer,\n query_t* __restrict__ curr_output_buffer,\n float* __restrict__ sum_buffer,\n const int32_t q_heads_per_kv,\n const int32_t actual_q_token_num,\n const int32_t q_head_num) {\n // final output\n using output_vec_t = typename VecTypeTrait<query_t>::vec_t;\n\n float* __restrict__ curr_partial_output_buffer = partial_q_buffer;\n float* __restrict__ curr_sum_buffer = sum_buffer;\n constexpr int32_t group_num_per_head = head_dim / 16;\n const int32_t partial_q_buffer_stride = q_heads_per_kv * head_dim;\n const int32_t output_buffer_stride = q_head_num * head_dim;\n for (int32_t token_idx = 0; token_idx < actual_q_token_num; ++token_idx) {\n float* __restrict__ curr_partial_output_buffer_iter =\n curr_partial_output_buffer;\n query_t* __restrict__ curr_output_buffer_iter = curr_output_buffer;\n for (int32_t head_idx = 0; head_idx < q_heads_per_kv; ++head_idx) {\n vec_op::FP32Vec16 inv_sum_scale_vec(1.0 / *curr_sum_buffer);\n\n for (int32_t i = 0; i < group_num_per_head; ++i) {\n vec_op::FP32Vec16 vec(curr_partial_output_buffer_iter);\n // divide the final sum val of softmax here\n vec = inv_sum_scale_vec * vec;\n\n // cast to query type\n output_vec_t output_vec(vec);\n output_vec.save(curr_output_buffer_iter);\n\n // update\n curr_partial_output_buffer_iter += 16;\n curr_output_buffer_iter += 16;\n }\n\n // update\n curr_sum_buffer += 1;\n }\n\n // update\n curr_partial_output_buffer += partial_q_buffer_stride;\n curr_output_buffer += output_buffer_stride;\n }\n }\n};\n\n} // namespace cpu_attention\n\n#endif\n"},"after_code":{"kind":"string","value":"#ifndef CPU_ATTN_HPP\n#define CPU_ATTN_HPP\n\n#include <type_traits>\n#include <cstddef>\n\n#if defined(__APPLE__)\n #include <sys/sysctl.h>\n#endif\n\n#include \"cpu_types.hpp\"\n#include \"scratchpad_manager.h\"\n#include \"cpu_attn_macros.h\"\n#include \"utils.hpp\"\n\nnamespace cpu_attention {\nenum class ISA { AMX, VEC, VEC16, NEON };\n\ntemplate <ISA isa, typename scalar_t, int64_t head_dim>\nclass AttentionImpl {};\n\nstruct AttentionWorkItemGroup {\n int32_t req_id;\n int32_t q_token_id_start;\n int32_t q_token_num;\n int32_t kv_split_pos_start;\n int32_t kv_split_pos_end;\n\n int64_t total_kv_len;\n int32_t split_id;\n int32_t local_split_id;\n\n AttentionWorkItemGroup(const int32_t req_id, const int32_t q_token_id_start,\n const int32_t kv_split_pos_start,\n const int32_t kv_split_pos_end)\n : req_id(req_id),\n q_token_id_start(q_token_id_start),\n q_token_num(0),\n kv_split_pos_start(kv_split_pos_start),\n kv_split_pos_end(kv_split_pos_end),\n total_kv_len(0),\n split_id(-1),\n local_split_id(0) {}\n\n std::string to_string() const {\n std::stringstream ss;\n ss << '[' << \"req_id: \" << req_id << \",\\n\";\n ss << \"q_token_id_start: \" << q_token_id_start << \",\\n\";\n ss << \"q_token_num: \" << q_token_num << \",\\n\";\n ss << \"kv_split_pos_start: \" << kv_split_pos_start << \",\\n\";\n ss << \"kv_split_pos_end: \" << kv_split_pos_end << \",\\n\";\n ss << \"total_kv_len: \" << total_kv_len << \",\\n\";\n ss << \"split_id: \" << split_id << \",\\n\";\n ss << \"local_split_id: \" << local_split_id << \",\\n\";\n ss << ']';\n\n return ss.str();\n }\n};\n\nstruct ReductionWorkItemGroup {\n int32_t req_id;\n int32_t q_token_id_start;\n int32_t q_token_id_num;\n int32_t split_start_id;\n int32_t split_num;\n\n ReductionWorkItemGroup(const int32_t req_id, const int32_t q_token_id_start,\n const int32_t q_token_id_num,\n const int32_t split_start_id)\n : req_id(req_id),\n q_token_id_start(q_token_id_start),\n q_token_id_num(q_token_id_num),\n split_start_id(split_start_id),\n split_num(0) {}\n\n std::string to_string() const {\n std::stringstream ss;\n ss << '[' << \"req_id: \" << req_id << \",\\n\";\n ss << \"q_token_id_start: \" << q_token_id_start << \",\\n\";\n ss << \"q_token_id_num: \" << q_token_id_num << \",\\n\";\n ss << \"split_start_id: \" << split_start_id << \",\\n\";\n ss << \"split_num: \" << split_num << \",\\n\";\n ss << ']';\n\n return ss.str();\n }\n};\n\nstruct AttentionMetadata {\n std::atomic_int64_t counter;\n char _padding1[56];\n ISA isa;\n int32_t workitem_group_num;\n int32_t reduction_item_num;\n int32_t reduction_split_num;\n int32_t thread_num;\n int32_t effective_thread_num; // non-zero item num in workitem_num_per_thread\n int32_t split_kv_q_token_num_threshold;\n int64_t attention_scratchpad_size_per_thread;\n int64_t reduction_scratchpad_size_per_kv_head;\n AttentionWorkItemGroup* workitem_groups_ptr;\n ReductionWorkItemGroup* reduction_items_ptr;\n int32_t cu_workitem_num_per_thread[1025] = {\n 0}; // prefix sum of workitem_num_per_thread\n char _padding2[56];\n\n AttentionMetadata(ISA isa, int32_t workitem_group_num,\n int32_t reduction_item_num, int32_t reduction_split_num,\n int32_t split_kv_q_token_num_threshold)\n : isa(isa),\n workitem_group_num(workitem_group_num),\n reduction_item_num(reduction_item_num),\n reduction_split_num(reduction_split_num),\n thread_num(omp_get_max_threads()),\n effective_thread_num(thread_num),\n split_kv_q_token_num_threshold(split_kv_q_token_num_threshold),\n attention_scratchpad_size_per_thread(0),\n reduction_scratchpad_size_per_kv_head(0),\n workitem_groups_ptr(\n (AttentionWorkItemGroup*)((char*)this + sizeof(AttentionMetadata))),\n reduction_items_ptr(\n (ReductionWorkItemGroup*)((char*)this + sizeof(AttentionMetadata) +\n workitem_group_num *\n sizeof(AttentionWorkItemGroup))),\n counter(0) {\n TORCH_CHECK_LE(thread_num, 1024);\n static_assert(sizeof(AttentionMetadata) % 64 == 0);\n TORCH_CHECK(reinterpret_cast<size_t>(this) % 64 == 0);\n }\n\n void reset_counter() { counter.store(0); }\n\n int64_t acquire_counter() { return counter++; }\n\n void print() const {\n std::stringstream ss;\n ss << \"ISA: \";\n switch (isa) {\n case ISA::AMX:\n ss << \"AMX, \";\n break;\n case ISA::VEC:\n ss << \"VEC, \";\n break;\n case ISA::VEC16:\n ss << \"VEC16, \";\n break;\n case ISA::NEON:\n ss << \"NEON, \";\n break;\n }\n ss << \"workitem_group_num: \" << workitem_group_num\n << \", reduction_item_num: \" << reduction_item_num\n << \", reduction_split_num: \" << reduction_split_num\n << \", thread_num: \" << thread_num\n << \", effective_thread_num: \" << effective_thread_num\n << \", attention_scratchpad_size_per_thread: \"\n << attention_scratchpad_size_per_thread\n << \", reduction_scratchpad_size_per_kv_head: \"\n << reduction_scratchpad_size_per_kv_head << \", workitem groups:\\n\";\n for (int32_t i = 0; i < workitem_group_num; ++i) {\n ss << (workitem_groups_ptr + i)->to_string() << \",\\n\";\n }\n\n ss << \"cu_workitem_num_per_thread: [\";\n for (int32_t i = 0; i < thread_num + 1; ++i) {\n ss << cu_workitem_num_per_thread[i] << \", \";\n }\n ss << \"]\\n\";\n\n ss << \"reduction items: \\n\";\n\n for (int32_t i = 0; i < reduction_item_num; ++i) {\n ss << (reduction_items_ptr + i)->to_string() << \",\\n\";\n }\n\n std::printf(\"%s\", ss.str().c_str());\n }\n};\n\n// Thread attention scratchpad contains:\n// - Q: q_tile_size * head_dim * q_buffer_elem_size, gather Q heads, especially\n// for GQA\n// - Q@K^T: max_num_q_per_iter * k_tile_size * logits_buffer_elem_size, logits\n// - Intermediate outputs: q_tile_size * head_dim * output_buffer_elem_size + 2\n// * q_tile_size * 4, partial output, max + sum (float)\n// Reduction scratchpad contains:\n// - flags: bool array to indicate wether the split is finished\n// - outputs: split_num * q_tile_size * head_dim * output_buffer_elem_size\n// - max, sum: 2 * split_num * q_tile_size * 4\nclass AttentionScratchPad {\n public:\n AttentionScratchPad(int64_t thread_id,\n const AttentionMetadata& attention_metadata,\n void* scratchpad_ptr)\n : thread_scratchpad_ptr(\n static_cast<int8_t*>(scratchpad_ptr) +\n thread_id *\n attention_metadata.attention_scratchpad_size_per_thread),\n reduction_scratchpad_ptr(\n static_cast<int8_t*>(scratchpad_ptr) +\n attention_metadata.thread_num *\n attention_metadata.attention_scratchpad_size_per_thread),\n reduction_scratchpad_size_per_kv_head(\n attention_metadata.reduction_scratchpad_size_per_kv_head) {}\n\n // for attention\n void update(const int64_t head_dim, const int64_t q_buffer_elem_size,\n const int64_t logits_buffer_elem_size,\n const int64_t output_buffer_elem_size,\n const int64_t max_num_q_per_iter, const int64_t q_head_tile_size,\n const int64_t kv_tile_size) {\n int64_t buffer_offset = 0;\n q_buffer_offset_ = buffer_offset;\n buffer_offset +=\n calcu_q_buffer_size(q_head_tile_size, head_dim, q_buffer_elem_size);\n logits_buffer_offset_ = buffer_offset;\n buffer_offset += calcu_logits_buffer_size(max_num_q_per_iter, kv_tile_size,\n logits_buffer_elem_size);\n output_buffer_offset_ = buffer_offset;\n buffer_offset += calcu_partial_output_buffer_size(\n q_head_tile_size, head_dim, output_buffer_elem_size);\n max_buffer_offset_ = buffer_offset;\n buffer_offset += calcu_partial_output_max_sum_buffer_size(q_head_tile_size);\n sum_buffer_offset_ = buffer_offset;\n }\n\n // for reduction\n void update(const int32_t kv_head_idx, const int32_t total_split_num,\n const int64_t head_dim, const int64_t q_head_tile_size,\n const int64_t output_buffer_elem_size) {\n int64_t buffer_offset = kv_head_idx * reduction_scratchpad_size_per_kv_head;\n reduce_flag_buffer_offset_ = buffer_offset;\n buffer_offset += calcu_reduce_flag_buffer_size(total_split_num);\n reduce_output_buffer_offset_ = buffer_offset;\n buffer_offset += calcu_reduce_output_buffer_size(\n total_split_num, q_head_tile_size, head_dim, output_buffer_elem_size);\n reduce_max_buffer_offset_ = buffer_offset;\n buffer_offset +=\n calcu_reduce_max_sum_buffer_size(total_split_num, q_head_tile_size);\n reduce_sum_buffer_offset_ = buffer_offset;\n }\n\n template <typename T>\n T* get_q_buffer() {\n return reinterpret_cast<T*>(thread_scratchpad_ptr + q_buffer_offset_);\n }\n\n float* get_logits_buffer() {\n return reinterpret_cast<float*>(thread_scratchpad_ptr +\n logits_buffer_offset_);\n }\n\n float* get_output_buffer() {\n return reinterpret_cast<float*>(thread_scratchpad_ptr +\n output_buffer_offset_);\n }\n\n float* get_max_buffer() {\n return reinterpret_cast<float*>(thread_scratchpad_ptr + max_buffer_offset_);\n }\n\n float* get_sum_buffer() {\n return reinterpret_cast<float*>(thread_scratchpad_ptr + sum_buffer_offset_);\n }\n\n volatile bool* get_reduce_flag_buffer() {\n return reinterpret_cast<volatile bool*>(reduction_scratchpad_ptr +\n reduce_flag_buffer_offset_);\n }\n\n float* get_reduce_output_buffer() {\n return reinterpret_cast<float*>(reduction_scratchpad_ptr +\n reduce_output_buffer_offset_);\n }\n\n float* get_reduce_max_buffer() {\n return reinterpret_cast<float*>(reduction_scratchpad_ptr +\n reduce_max_buffer_offset_);\n }\n\n float* get_reduce_sum_buffer() {\n return reinterpret_cast<float*>(reduction_scratchpad_ptr +\n reduce_sum_buffer_offset_);\n }\n\n int64_t get_thread_scratchpad_size() const {\n return 2 * sum_buffer_offset_ - max_buffer_offset_;\n }\n\n int64_t get_reduction_scratchpad_size() const {\n return 2 * reduce_sum_buffer_offset_ - reduce_max_buffer_offset_;\n }\n\n private:\n static int64_t round_to_64(const int64_t num) {\n return ((num + 63) >> 6) << 6;\n }\n\n static int64_t calcu_q_buffer_size(const int64_t q_tile_size,\n const int64_t head_dim,\n const int64_t elem_size) {\n return round_to_64(q_tile_size * head_dim * elem_size);\n }\n\n static int64_t calcu_logits_buffer_size(const int64_t max_num_q_per_iter,\n const int64_t k_tile_size,\n const int64_t elem_size) {\n return round_to_64(elem_size * max_num_q_per_iter * k_tile_size);\n }\n\n static int64_t calcu_partial_output_buffer_size(const int64_t q_tile_size,\n const int64_t head_dim,\n const int64_t elem_size) {\n return round_to_64(q_tile_size * head_dim * elem_size);\n }\n\n static int64_t calcu_partial_output_max_sum_buffer_size(\n const int64_t q_tile_size) {\n return round_to_64(q_tile_size * sizeof(float));\n }\n\n static int64_t calcu_reduce_flag_buffer_size(const int64_t total_split_num) {\n return round_to_64(total_split_num * sizeof(bool));\n }\n\n static int64_t calcu_reduce_max_sum_buffer_size(\n const int64_t total_split_num, const int32_t q_head_tile_size) {\n return round_to_64(total_split_num * q_head_tile_size * sizeof(float));\n }\n\n static int64_t calcu_reduce_output_buffer_size(\n const int64_t total_split_num, const int64_t q_head_tile_size,\n const int64_t head_dim, const int64_t output_buffer_elem_size) {\n return round_to_64(total_split_num * q_head_tile_size * head_dim *\n output_buffer_elem_size);\n }\n\n private:\n int8_t* thread_scratchpad_ptr;\n int8_t* reduction_scratchpad_ptr;\n int64_t reduction_scratchpad_size_per_kv_head;\n // attention buffers\n int64_t q_buffer_offset_;\n int64_t logits_buffer_offset_;\n int64_t output_buffer_offset_;\n int64_t max_buffer_offset_;\n int64_t sum_buffer_offset_;\n // reduction buffers\n int64_t reduce_flag_buffer_offset_;\n int64_t reduce_output_buffer_offset_;\n int64_t reduce_max_buffer_offset_;\n int64_t reduce_sum_buffer_offset_;\n};\n\nclass AttentionScheduler {\n public:\n struct ScheduleInput {\n int32_t num_reqs;\n int32_t elem_size;\n int32_t q_buffer_elem_size;\n int32_t logits_buffer_elem_size;\n int32_t output_buffer_elem_size;\n int32_t num_heads_q;\n int32_t num_heads_kv;\n int32_t head_dim;\n int32_t* query_start_loc;\n int32_t* seq_lens;\n int32_t left_sliding_window_size;\n int32_t right_sliding_window_size;\n bool casual;\n cpu_attention::ISA isa;\n int32_t max_num_q_per_iter; // max Q head num can be hold in registers\n int32_t kv_block_alignment; // context length alignment requirement\n bool enable_kv_split;\n };\n\n static constexpr int32_t MaxQTileIterNum = 128;\n\n AttentionScheduler() : available_cache_size_(get_available_l2_size()) {}\n\n torch::Tensor schedule(const ScheduleInput& input) const {\n const bool casual = input.casual;\n const int32_t thread_num = omp_get_max_threads();\n const int64_t cache_size = get_available_l2_size();\n const int32_t max_num_q_per_iter = input.max_num_q_per_iter;\n const int32_t kv_len_alignment = input.kv_block_alignment;\n int32_t q_head_per_kv = input.num_heads_q / input.num_heads_kv;\n const bool use_gqa = (max_num_q_per_iter % q_head_per_kv == 0);\n if (!use_gqa) {\n q_head_per_kv = 1; // fallback to MHA\n }\n const int32_t min_split_kv_len =\n ((max_num_q_per_iter * 4 + kv_len_alignment - 1) / kv_len_alignment) *\n kv_len_alignment;\n const int32_t max_num_q_token_per_iter = max_num_q_per_iter / q_head_per_kv;\n const int64_t default_tile_size = calcu_default_tile_size(\n cache_size, input.head_dim, input.elem_size, input.q_buffer_elem_size,\n input.logits_buffer_elem_size, input.output_buffer_elem_size,\n max_num_q_per_iter, max_num_q_per_iter);\n const int32_t default_tile_token_num = default_tile_size / q_head_per_kv;\n const int32_t split_kv_q_token_num_threshold =\n input.enable_kv_split ? 1 : 0;\n const int32_t left_sliding_window_size = input.left_sliding_window_size;\n const int32_t right_sliding_window_size = input.right_sliding_window_size;\n TORCH_CHECK_LE(split_kv_q_token_num_threshold * q_head_per_kv, 16);\n\n // get total kv len\n int64_t total_kv_len = 0;\n for (int32_t req_id = 0; req_id < input.num_reqs; ++req_id) {\n const int32_t seq_len = input.seq_lens[req_id];\n const int32_t q_token_num =\n input.query_start_loc[req_id + 1] - input.query_start_loc[req_id];\n const int32_t q_start_pos = (casual ? (seq_len - q_token_num) : 0);\n const int32_t kv_start_pos = 0;\n const int32_t kv_end_pos = seq_len;\n\n for (int32_t token_id = 0; token_id < q_token_num;\n token_id += max_num_q_token_per_iter) {\n const int32_t q_tile_token_num =\n std::min(max_num_q_token_per_iter, q_token_num - token_id);\n const int32_t q_tile_pos_left = q_start_pos + token_id;\n const int32_t q_tile_pos_right = q_tile_pos_left + q_tile_token_num;\n const auto [kv_tile_pos_left, kv_tile_pos_right] = calcu_kv_tile_pos(\n kv_start_pos, kv_end_pos, q_tile_pos_left, q_tile_pos_right,\n left_sliding_window_size, right_sliding_window_size);\n const auto [aligned_kv_tile_pos_left, aligned_kv_tile_pos_right] =\n align_kv_tile_pos(kv_tile_pos_left, kv_tile_pos_right,\n kv_len_alignment);\n\n int32_t curr_kv_len =\n aligned_kv_tile_pos_right - aligned_kv_tile_pos_left;\n total_kv_len += curr_kv_len;\n }\n }\n const int64_t kv_len_per_thread =\n (((total_kv_len / thread_num) + kv_len_alignment - 1) /\n kv_len_alignment) *\n kv_len_alignment * (use_gqa ? input.num_heads_kv : input.num_heads_q);\n std::vector<AttentionWorkItemGroup> workitems;\n std::vector<ReductionWorkItemGroup> reduce_workitems;\n workitems.reserve(1024);\n reduce_workitems.reserve(1024);\n std::vector<int32_t> workitem_num_per_thread(thread_num, 0);\n\n // split tasks\n int32_t curr_thread_id = 0;\n int64_t remaining_kv_len = kv_len_per_thread;\n int32_t cum_split_num = 0;\n for (int32_t req_id = 0; req_id < input.num_reqs; ++req_id) {\n const int32_t seq_len = input.seq_lens[req_id];\n const int32_t q_token_num =\n input.query_start_loc[req_id + 1] - input.query_start_loc[req_id];\n const int32_t q_start_pos = (casual ? (seq_len - q_token_num) : 0);\n const int32_t kv_start_pos = 0;\n const int32_t kv_end_pos = seq_len;\n int32_t local_split_id = 0;\n\n AttentionWorkItemGroup curr_workitem(req_id, 0, 0, seq_len);\n for (int32_t token_id = 0; token_id < q_token_num;\n token_id += max_num_q_token_per_iter) {\n const int32_t q_tile_token_num =\n std::min(max_num_q_token_per_iter, q_token_num - token_id);\n const int32_t q_tile_pos_left = q_start_pos + token_id;\n const int32_t q_tile_pos_right = q_tile_pos_left + q_tile_token_num;\n const auto [kv_tile_pos_left, kv_tile_pos_right] = calcu_kv_tile_pos(\n kv_start_pos, kv_end_pos, q_tile_pos_left, q_tile_pos_right,\n left_sliding_window_size, right_sliding_window_size);\n const auto [aligned_kv_tile_pos_left, aligned_kv_tile_pos_right] =\n align_kv_tile_pos(kv_tile_pos_left, kv_tile_pos_right,\n kv_len_alignment);\n int32_t curr_kv_len =\n aligned_kv_tile_pos_right - aligned_kv_tile_pos_left;\n int32_t kv_token_pos_start = aligned_kv_tile_pos_left;\n\n while (curr_kv_len > 0) {\n if (curr_kv_len <= (remaining_kv_len + min_split_kv_len) ||\n curr_thread_id == (thread_num - 1)) {\n curr_workitem.q_token_num += q_tile_token_num;\n curr_workitem.total_kv_len += curr_kv_len;\n remaining_kv_len -= curr_kv_len;\n curr_kv_len = 0;\n\n if (remaining_kv_len < 0) {\n // stop to accept more workitems\n remaining_kv_len -= min_split_kv_len;\n }\n\n if (curr_workitem.kv_split_pos_start != 0) {\n // got a partial kv spilt, need to create a single workitem\n curr_workitem.split_id = cum_split_num;\n curr_workitem.local_split_id = local_split_id;\n workitems.emplace_back(curr_workitem);\n ++workitem_num_per_thread[curr_thread_id];\n ++reduce_workitems.back().split_num;\n ++cum_split_num;\n\n curr_workitem = AttentionWorkItemGroup(\n req_id, token_id + max_num_q_token_per_iter, 0, seq_len);\n }\n\n break;\n }\n\n if (remaining_kv_len < min_split_kv_len &&\n (curr_workitem.total_kv_len > 0 ||\n workitem_num_per_thread[curr_thread_id] > 0)) {\n // remaining_kv_len is too short, and have allocated workitems, just\n // leave to next thread\n if (curr_workitem.total_kv_len > 0) {\n workitems.emplace_back(curr_workitem);\n ++workitem_num_per_thread[curr_thread_id];\n curr_workitem =\n AttentionWorkItemGroup(req_id, token_id, 0, seq_len);\n }\n\n // switch to next thread\n ++curr_thread_id;\n remaining_kv_len = kv_len_per_thread;\n\n // retry this iteration\n continue;\n }\n\n // only split tail splits with q_tile_token_num <=\n // split_kv_q_token_num_threshold\n if (token_id + max_num_q_token_per_iter < q_token_num ||\n q_tile_token_num > split_kv_q_token_num_threshold) {\n // if requires a new q tile iteration and already has workitems,\n // leave this workitem to next thread\n if (curr_workitem.q_token_num % default_tile_token_num == 0 &&\n (curr_workitem.total_kv_len > 0 ||\n workitem_num_per_thread[curr_thread_id] > 0)) {\n if (curr_workitem.total_kv_len > 0) {\n workitems.emplace_back(curr_workitem);\n ++workitem_num_per_thread[curr_thread_id];\n }\n curr_workitem =\n AttentionWorkItemGroup(req_id, token_id, 0, seq_len);\n\n // switch to next thread\n ++curr_thread_id;\n remaining_kv_len = kv_len_per_thread;\n }\n\n curr_workitem.q_token_num += q_tile_token_num;\n curr_workitem.total_kv_len += curr_kv_len;\n remaining_kv_len -= curr_kv_len;\n curr_kv_len = 0;\n break;\n }\n\n // split kv\n if (curr_workitem.total_kv_len > 0) {\n // write back curr workitem\n workitems.emplace_back(curr_workitem);\n ++workitem_num_per_thread[curr_thread_id];\n }\n\n if (kv_token_pos_start == aligned_kv_tile_pos_left) {\n // first split, init the workitem\n reduce_workitems.emplace_back(ReductionWorkItemGroup(\n req_id, token_id, q_tile_token_num, cum_split_num));\n }\n\n int32_t spilt_size =\n std::min(std::max(remaining_kv_len, (int64_t)min_split_kv_len),\n (int64_t)curr_kv_len);\n curr_workitem =\n AttentionWorkItemGroup(req_id, token_id, kv_token_pos_start,\n kv_token_pos_start + spilt_size);\n curr_workitem.q_token_num += q_tile_token_num;\n curr_workitem.total_kv_len += spilt_size;\n curr_workitem.split_id = cum_split_num;\n curr_workitem.local_split_id = local_split_id;\n workitems.emplace_back(curr_workitem);\n ++workitem_num_per_thread[curr_thread_id];\n ++reduce_workitems.back().split_num;\n ++cum_split_num;\n ++local_split_id;\n\n kv_token_pos_start += spilt_size;\n curr_kv_len -= spilt_size;\n curr_workitem = AttentionWorkItemGroup(req_id, token_id,\n kv_token_pos_start, seq_len);\n\n // switch to next thread\n ++curr_thread_id;\n remaining_kv_len = kv_len_per_thread;\n }\n }\n\n if (curr_workitem.total_kv_len > 0) {\n // write back curr workitem\n workitems.emplace_back(curr_workitem);\n ++workitem_num_per_thread[curr_thread_id];\n }\n }\n\n int64_t metadata_tensor_size =\n sizeof(AttentionMetadata) +\n workitems.size() * sizeof(AttentionWorkItemGroup) +\n reduce_workitems.size() * sizeof(ReductionWorkItemGroup);\n auto options =\n torch::TensorOptions().dtype(torch::kInt8).device(torch::kCPU);\n torch::Tensor metadata_tensor =\n torch::empty({metadata_tensor_size}, options);\n AttentionMetadata* metadata_ptr = new (metadata_tensor.data_ptr())\n AttentionMetadata(input.isa, workitems.size(), reduce_workitems.size(),\n cum_split_num, split_kv_q_token_num_threshold);\n AttentionWorkItemGroup* workitem_groups_ptr =\n metadata_ptr->workitem_groups_ptr;\n ReductionWorkItemGroup* reduction_items_ptr =\n metadata_ptr->reduction_items_ptr;\n std::memcpy(workitem_groups_ptr, workitems.data(),\n workitems.size() * sizeof(AttentionWorkItemGroup));\n std::memcpy(reduction_items_ptr, reduce_workitems.data(),\n reduce_workitems.size() * sizeof(ReductionWorkItemGroup));\n\n int32_t effective_thread_num = 0;\n for (; effective_thread_num < thread_num; ++effective_thread_num) {\n if (workitem_num_per_thread[effective_thread_num] == 0) {\n break;\n }\n }\n\n std::memcpy(metadata_ptr->cu_workitem_num_per_thread + 1,\n workitem_num_per_thread.data(),\n workitem_num_per_thread.size() * sizeof(int32_t));\n for (int32_t i = 1; i <= thread_num; ++i) {\n metadata_ptr->cu_workitem_num_per_thread[i] +=\n metadata_ptr->cu_workitem_num_per_thread[i - 1];\n }\n metadata_ptr->effective_thread_num = effective_thread_num;\n\n {\n // when q_tile_size = max_num_q_per_iter, requires max\n // attention_scratchpad_size\n AttentionScratchPad sc(0, *metadata_ptr, 0x0);\n int64_t n = AttentionScheduler::calcu_tile_size_with_constant_q(\n cache_size, input.head_dim, input.elem_size, input.q_buffer_elem_size,\n input.logits_buffer_elem_size, input.output_buffer_elem_size,\n max_num_q_per_iter, kv_len_alignment, max_num_q_per_iter, true);\n sc.update(input.head_dim, input.q_buffer_elem_size,\n input.logits_buffer_elem_size, input.output_buffer_elem_size,\n max_num_q_per_iter, max_num_q_per_iter, n);\n metadata_ptr->attention_scratchpad_size_per_thread =\n ((sc.get_thread_scratchpad_size() + 63) / 64) * 64;\n\n sc.update(0, metadata_ptr->reduction_split_num, input.head_dim,\n q_head_per_kv * split_kv_q_token_num_threshold,\n input.output_buffer_elem_size);\n metadata_ptr->reduction_scratchpad_size_per_kv_head =\n ((sc.get_reduction_scratchpad_size() + 63) / 64) * 64;\n }\n int64_t scratchpad_size =\n metadata_ptr->attention_scratchpad_size_per_thread *\n metadata_ptr->thread_num +\n metadata_ptr->reduction_scratchpad_size_per_kv_head *\n (use_gqa ? input.num_heads_kv : input.num_heads_q);\n DNNLScratchPadManager::get_dnnl_scratchpad_manager()->realloc(\n scratchpad_size);\n\n // metadata_ptr->print();\n\n // test out of boundary access\n // {\n // float* cache_ptr =\n // DNNLScratchPadManager::get_dnnl_scratchpad_manager()->get_data<float>();\n // for (int64_t i = 0; i < scratchpad_size / sizeof(float); ++i) {\n // cache_ptr[i] = std::numeric_limits<float>::quiet_NaN();\n // }\n // }\n\n return metadata_tensor;\n }\n\n FORCE_INLINE static std::pair<int32_t, int32_t> calcu_kv_tile_pos(\n int32_t kv_left_pos, int32_t kv_right_pos, int32_t q_left_pos,\n int32_t q_right_pos, int32_t sliding_window_left,\n int32_t sliding_window_right) {\n if (sliding_window_left != -1) {\n kv_left_pos = std::max(kv_left_pos, q_left_pos - sliding_window_left);\n }\n if (sliding_window_right != -1) {\n kv_right_pos = std::min(kv_right_pos, q_right_pos + sliding_window_right);\n }\n return {kv_left_pos, kv_right_pos};\n }\n\n FORCE_INLINE static std::pair<int32_t, int32_t> align_kv_tile_pos(\n int32_t kv_left_pos, int32_t kv_right_pos, int32_t align_factor) {\n kv_left_pos = (kv_left_pos / align_factor) * align_factor;\n kv_right_pos =\n ((kv_right_pos + align_factor - 1) / align_factor) * align_factor;\n return {kv_left_pos, kv_right_pos};\n }\n\n static int64_t calcu_default_tile_size(int64_t cache_size, int64_t head_dim,\n int64_t elem_size,\n int64_t q_buffer_elem_size,\n int64_t logits_buffer_elem_size,\n int64_t output_buffer_elem_size,\n int64_t max_num_q_per_iter,\n int64_t round_size) {\n // For CPU, different from CUDA, Q@K^T results should also be hold in cache,\n // using float32. Intermediate outputs should be float32 to be compatible\n // with AMX Then the cache includes:\n // - Q: q_tile_size * head_dim * q_buffer_elem_size\n // - K, V: 2 * k_tile_size * head_dim * elem_size\n // - Q@K^T: max_num_q_per_iter * k_tile_size * logits_buffer_elem_size\n // - Intermediate outputs: q_tile_size * head_dim * output_buffer_elem_size\n // By default, let tile_size = q_tile_size = k_tile_size. To record\n // is_first_iter states in a static array, require the default tile <= 128 *\n // max_num_q_per_iter\n\n int64_t tile_size =\n cache_size / (head_dim * (q_buffer_elem_size + 2 * elem_size +\n output_buffer_elem_size) +\n max_num_q_per_iter * logits_buffer_elem_size);\n tile_size = std::min(tile_size, MaxQTileIterNum * max_num_q_per_iter);\n int64_t rounded_tile_size = (tile_size / round_size) * round_size;\n return std::max(rounded_tile_size, round_size);\n }\n\n static int64_t calcu_tile_size_with_constant_q(\n int64_t cache_size, int64_t head_dim, int64_t elem_size,\n int64_t q_buffer_elem_size, int64_t logits_buffer_elem_size,\n int64_t output_buffer_elem_size, int64_t max_num_q_per_iter,\n int64_t round_size, int64_t q_tile_size, bool one_round) {\n // calculate tile_size with known q_tile_size\n // If one_round is True, the outer Q tile loop time is 1, then the K,V will\n // not be included in the cache\n int64_t tile_size;\n if (one_round) {\n tile_size =\n (cache_size - q_tile_size * head_dim *\n (q_buffer_elem_size + output_buffer_elem_size)) /\n (logits_buffer_elem_size * max_num_q_per_iter);\n } else {\n tile_size =\n (cache_size - q_tile_size * head_dim *\n (q_buffer_elem_size + output_buffer_elem_size)) /\n (logits_buffer_elem_size * max_num_q_per_iter +\n 2 * head_dim * elem_size);\n }\n int64_t rounded_tile_size = (tile_size / round_size) * round_size;\n return std::max(rounded_tile_size, round_size);\n }\n\n static int64_t get_available_l2_size() {\n static int64_t size = []() {\n#if defined(__APPLE__)\n // macOS doesn't have _SC_LEVEL2_CACHE_SIZE. Use sysctlbyname.\n int64_t l2_cache_size = 0;\n size_t len = sizeof(l2_cache_size);\n if (sysctlbyname(\"hw.l2cachesize\", &l2_cache_size, &len, NULL, 0) == 0 &&\n l2_cache_size > 0) {\n return l2_cache_size >> 1; // use 50% of L2 cache\n }\n // Fallback if sysctlbyname fails\n return 128LL * 1024 >> 1; // use 50% of 128KB\n#else\n long l2_cache_size = sysconf(_SC_LEVEL2_CACHE_SIZE);\n TORCH_CHECK_NE(l2_cache_size, -1);\n return l2_cache_size >> 1; // use 50% of L2 cache\n#endif\n }();\n return size;\n }\n\n private:\n int64_t available_cache_size_;\n};\n\nstruct AttentionInput {\n AttentionMetadata* metadata;\n int32_t num_tokens;\n int32_t num_heads;\n int32_t num_kv_heads;\n int32_t block_size;\n void* query;\n int64_t query_num_tokens_stride;\n int64_t query_num_heads_stride;\n int64_t cache_num_blocks_stride;\n int64_t cache_num_kv_heads_stride;\n int64_t blt_num_tokens_stride;\n void* key_cache;\n void* value_cache;\n void* output;\n int32_t* query_start_loc;\n int32_t* seq_lens;\n int32_t* block_table;\n float* alibi_slopes;\n c10::BFloat16* s_aux;\n float scale;\n bool causal;\n int32_t sliding_window_left;\n int32_t sliding_window_right;\n float softcap;\n};\n\n#define DEFINE_CPU_ATTENTION_PARAMS \\\n q_buffer_t *__restrict__ q_heads_buffer, \\\n kv_cache_t *__restrict__ k_head_cache_ptr, \\\n kv_cache_t *__restrict__ v_head_cache_ptr, \\\n logits_buffer_t *__restrict__ logits_buffer, \\\n float *__restrict__ partial_q_buffer, float *__restrict__ max_buffer, \\\n float *__restrict__ sum_buffer, int32_t *__restrict__ block_table, \\\n const int32_t kv_tile_start_pos, const int32_t kv_tile_end_pos, \\\n const int32_t kv_tile_token_num, \\\n const int64_t kv_cache_num_blocks_stride, const int32_t q_head_num, \\\n const int32_t q_token_num, const int32_t q_tile_start_pos, \\\n const int32_t q_heads_per_kv, const int32_t block_size, \\\n const int32_t left_window_size, const int32_t right_window_size, \\\n float scale, const float softcap_scale, \\\n const float *__restrict__ alibi_slopes, const bool is_first_iter, \\\n const bool use_sink, const bool debug_info\n\n#define CPU_ATTENTION_PARAMS \\\n q_heads_buffer, k_head_cache_ptr, v_head_cache_ptr, logits_buffer, \\\n partial_q_buffer, max_buffer, sum_buffer, block_table, \\\n kv_tile_start_pos, kv_tile_end_pos, kv_tile_token_num, \\\n kv_cache_num_blocks_stride, q_head_num, q_token_num, q_tile_start_pos, \\\n q_heads_per_kv, block_size, left_window_size, right_window_size, scale, \\\n softcap_scale, alibi_slopes, is_first_iter, use_sink, debug_info\n\nenum class AttentionGemmPhase { QK, PV };\n\ntemplate <typename T>\nstruct VecTypeTrait {\n using vec_t = void;\n};\n\ntemplate <>\nstruct VecTypeTrait<float> {\n using vec_t = vec_op::FP32Vec16;\n};\n\n// ARM only supports BF16 with ARMv8.6-A extension\n#if (defined(__aarch64__) && !defined(ARM_BF16_SUPPORT))\n#else\ntemplate <>\nstruct VecTypeTrait<c10::BFloat16> {\n using vec_t = vec_op::BF16Vec16;\n};\n#endif\n\n#if !defined(__powerpc__) && !defined(__s390x__)\ntemplate <>\nstruct VecTypeTrait<c10::Half> {\n using vec_t = vec_op::FP16Vec16;\n};\n#endif\n\ntemplate <typename T>\nvoid print_logits(const char* name, T* ptr, int32_t row, int32_t col,\n int32_t stride) {\n std::stringstream ss;\n ss << std::fixed << std::setprecision(5) << name << \": [\\n\";\n auto* curr_logits_buffer = ptr;\n for (int32_t m = 0; m < row; ++m) {\n for (int32_t n = 0; n < col; ++n) {\n ss << curr_logits_buffer[n] << \", \";\n }\n ss << \"\\n\";\n curr_logits_buffer += stride;\n }\n ss << \"]\\n\";\n std::printf(\"%s\", ss.str().c_str());\n}\n\ntemplate <typename attention_impl_t>\nclass AttentionMainLoop {\n public:\n using query_t = typename attention_impl_t::query_t;\n using q_buffer_t = typename attention_impl_t::q_buffer_t;\n using kv_cache_t = typename attention_impl_t::kv_cache_t;\n using logits_buffer_t = typename attention_impl_t::logits_buffer_t;\n using partial_output_buffer_t =\n typename attention_impl_t::partial_output_buffer_t;\n using prob_buffer_t = typename attention_impl_t::prob_buffer_t;\n\n static constexpr int64_t max_q_head_num_per_iter =\n attention_impl_t::MaxQHeadNumPerIteration;\n static constexpr int64_t blocksize_alignment =\n attention_impl_t::BlockSizeAlignment;\n static constexpr int64_t headdim_alignment =\n attention_impl_t::HeadDimAlignment;\n static constexpr int64_t head_dim = attention_impl_t::HeadDim;\n static constexpr ISA ISAType = attention_impl_t::ISAType;\n static constexpr bool scale_on_logits =\n attention_impl_t::scale_on_logits; // apply scale on logits, otherwise\n // apply scale on q_buffer\n\n template <typename tile_gemm_t>\n class Attention {\n public:\n // Args:\n // - q_heads_buffer: [MaxQHeadNumPerIteration, head_dim]\n // - k_head_cache_ptr: [num_blocks, block_size * head_dim]\n // - v_head_cache_ptr: [num_blocks, block_size * head_dim]\n // - logits_buffer: [MaxQHeadNumPerIteration, kv_tile_token_num], store Q@K\n // - logits partial_q_buffer: [MaxQHeadNumPerIteration, head_dim], store\n // partial output\n // - max_buffer: [MaxQHeadNumPerIteration, 1], store max logits\n // - sum_buffer: [MaxQHeadNumPerIteration, 1], store sum of exp\n // - block_table\n // - kv_tile_start_pos: start position of KV cache, aligned to\n // BlockSizeAlignment\n // - kv_tile_end_pos: end position of KV cache, aligned to\n // BlockSizeAlignment\n // - kv_tile_token_num: KV token num, aligned to BlockSizeAlignment\n // - kv_cache_num_blocks_stride\n // - q_head_num: head num of q_tile\n // - q_token_num: token num of q_tile, should be q_head_num /\n // q_heads_per_kv\n // - q_tile_start_pos: start pos of the first token in q_heads_buffer\n // - q_heads_per_kv\n // - block_size\n // - left_window_size\n // - right_window_size\n // - scale\n // - softcap_scale\n // - alibi_slopes\n // - is_first_iter\n // - use_sink\n // - debug_info\n void operator()(DEFINE_CPU_ATTENTION_PARAMS) {\n // k_cache_token_group_stride: stride of K cache when move to next\n // BlockSizeAlignment tokens in a block\n const int64_t k_cache_token_group_stride =\n attention_impl_t::k_cache_token_group_stride(block_size);\n // v_cache_token_group_stride: stride of V cache when move to next\n // BlockSizeAlignment tokens in a block\n const int64_t v_cache_token_group_stride =\n attention_impl_t::v_cache_token_group_stride(block_size);\n // v_cache_head_group_stride: stride of V cache when move to next\n // HeadDimAlignment head dims in a block\n const int64_t v_cache_head_group_stride =\n attention_impl_t::v_cache_head_group_stride(block_size);\n const int32_t token_group_num = kv_tile_token_num / blocksize_alignment;\n const int32_t token_group_num_per_block =\n block_size / blocksize_alignment;\n const int32_t start_block_idx = kv_tile_start_pos / block_size;\n const int32_t start_block_offset = kv_tile_start_pos % block_size;\n const int32_t start_block_group_offset =\n start_block_offset / blocksize_alignment;\n const int32_t end_block_idx =\n (kv_tile_start_pos + kv_tile_token_num - 1) / block_size + 1;\n\n // compute Q@K logits\n {\n int32_t curr_group_offset =\n start_block_group_offset * k_cache_token_group_stride;\n int32_t curr_group_num_in_block =\n token_group_num_per_block - start_block_group_offset;\n int32_t remaining_group_num = token_group_num;\n logits_buffer_t* curr_logits_buffer = logits_buffer;\n for (int32_t block_idx = start_block_idx; block_idx < end_block_idx;\n ++block_idx) {\n int32_t physical_block_idx = block_table[block_idx];\n kv_cache_t* k_cache_block_ptr =\n k_head_cache_ptr +\n physical_block_idx * kv_cache_num_blocks_stride +\n curr_group_offset;\n curr_group_num_in_block =\n std::min(remaining_group_num, curr_group_num_in_block);\n\n for (int32_t block_group_idx = 0;\n block_group_idx < curr_group_num_in_block; ++block_group_idx) {\n // logits_tile = q_tile @ k_tile, [MaxQHeadNumPerIteration,\n // BlockSizeAlignment] = [MaxQHeadNumPerIteration, head_dim] @\n // [head_dim, BlockSizeAlignment]\n\n // By default, logits_buffer, q_buffer and k_cache are row-major,\n // but may be packed by ISA implementation.\n tile_gemm_t::template gemm<AttentionGemmPhase::QK, head_dim>(\n q_head_num, q_heads_buffer, k_cache_block_ptr,\n curr_logits_buffer, head_dim, block_size, kv_tile_token_num,\n block_size, head_dim, false);\n\n if constexpr (scale_on_logits) {\n float* __restrict__ scale_curr_logits_buffer = curr_logits_buffer;\n vec_op::FP32Vec16 scale_vec(scale);\n for (int32_t i = 0; i < q_head_num; ++i) {\n static_assert(blocksize_alignment % 16 == 0);\n constexpr int32_t vec_num = blocksize_alignment / 16;\n vec_op::unroll_loop<int32_t, vec_num>([&](int32_t vec_idx) {\n vec_op::FP32Vec16 vec(scale_curr_logits_buffer +\n vec_idx * 16);\n vec = vec * scale_vec;\n vec.save(scale_curr_logits_buffer + vec_idx * 16);\n });\n scale_curr_logits_buffer += kv_tile_token_num;\n }\n }\n\n // Move buffer ptrs\n k_cache_block_ptr += k_cache_token_group_stride;\n curr_logits_buffer += blocksize_alignment;\n }\n\n // Update\n remaining_group_num -= curr_group_num_in_block;\n curr_group_offset = 0;\n curr_group_num_in_block = token_group_num_per_block;\n }\n }\n\n // process logits\n {\n // if (debug_info){\n // print_logits(\"raw logits\", logits_buffer, q_head_num,\n // kv_tile_token_num, kv_tile_token_num);\n // }\n\n if (softcap_scale != 0.0f) {\n apply_softcap(logits_buffer, kv_tile_token_num, q_head_num,\n kv_tile_token_num, softcap_scale);\n // print_logits(\"softcap raw logits\", logits_buffer, q_head_num,\n // kv_tile_token_num, kv_tile_token_num);\n }\n\n if (alibi_slopes != nullptr) {\n apply_alibi_slopes(logits_buffer, alibi_slopes, kv_tile_token_num,\n q_tile_start_pos, kv_tile_start_pos, q_token_num,\n kv_tile_token_num, q_heads_per_kv);\n\n // print_logits(\"alibi raw logits\", logits_buffer, q_head_num,\n // kv_tile_token_num, kv_tile_token_num);\n }\n\n apply_mask(logits_buffer, kv_tile_token_num, q_tile_start_pos,\n kv_tile_start_pos, kv_tile_end_pos, q_token_num,\n q_heads_per_kv, left_window_size, right_window_size);\n\n // if (debug_info){\n // print_logits(\"masked logits\", logits_buffer, q_head_num,\n // kv_tile_token_num, kv_tile_token_num);\n // print_logits(\"old_max\", max_buffer, 1, q_head_num, q_head_num);\n // print_logits(\"old_sum\", sum_buffer, 1, q_head_num, q_head_num);\n // }\n\n apply_softmax(logits_buffer, partial_q_buffer, max_buffer, sum_buffer,\n kv_tile_token_num, q_head_num, kv_tile_token_num,\n is_first_iter, use_sink);\n\n // if (debug_info){\n // print_logits(\"softmax logits\",\n // reinterpret_cast<prob_buffer_t*>(logits_buffer), q_head_num,\n // kv_tile_token_num, kv_tile_token_num * sizeof(logits_buffer_t) /\n // sizeof(prob_buffer_t));\n // print_logits(\"new_max\", max_buffer, 1, q_head_num, q_head_num);\n // print_logits(\"new_sum\", sum_buffer, 1, q_head_num, q_head_num);\n // }\n }\n\n // compute P@V\n {\n int32_t curr_group_offset =\n start_block_group_offset * v_cache_token_group_stride;\n int32_t curr_group_num_in_block =\n token_group_num_per_block - start_block_group_offset;\n int32_t remaining_group_num = token_group_num;\n int32_t head_dim_group_num = head_dim / headdim_alignment;\n prob_buffer_t* curr_prob_buffer =\n reinterpret_cast<prob_buffer_t*>(logits_buffer);\n int64_t prob_buffer_stride =\n kv_tile_token_num *\n (sizeof(logits_buffer_t) / sizeof(prob_buffer_t));\n partial_output_buffer_t* curr_partial_q_buffer = partial_q_buffer;\n bool accum_c = !is_first_iter;\n for (int32_t block_idx = start_block_idx; block_idx < end_block_idx;\n ++block_idx) {\n int32_t physical_block_idx = block_table[block_idx];\n kv_cache_t* v_cache_block_ptr =\n v_head_cache_ptr +\n physical_block_idx * kv_cache_num_blocks_stride +\n curr_group_offset;\n curr_group_num_in_block =\n std::min(remaining_group_num, curr_group_num_in_block);\n int32_t curr_token_num =\n curr_group_num_in_block * blocksize_alignment;\n\n for (int32_t head_dim_group_idx = 0;\n head_dim_group_idx < head_dim_group_num; ++head_dim_group_idx) {\n // output_tile = p_tile @ v_tile, [MaxQHeadNumPerIteration,\n // HeadDimAlignment] = [MaxQHeadNumPerIteration, block_size] @\n // [block_size, HeadDimAlignment]\n tile_gemm_t::template gemm<AttentionGemmPhase::PV, -1>(\n q_head_num, curr_prob_buffer, v_cache_block_ptr,\n curr_partial_q_buffer, prob_buffer_stride, head_dim, head_dim,\n block_size, curr_token_num, accum_c);\n\n // Update\n curr_partial_q_buffer += headdim_alignment;\n v_cache_block_ptr += v_cache_head_group_stride;\n }\n\n // Update\n remaining_group_num -= curr_group_num_in_block;\n curr_group_offset = 0;\n curr_group_num_in_block = token_group_num_per_block;\n curr_prob_buffer += curr_token_num;\n curr_partial_q_buffer = partial_q_buffer;\n accum_c = true;\n }\n }\n // if (debug_info) {\n // print_logits(\"output\", partial_q_buffer, q_head_num, head_dim,\n // head_dim);\n // }\n }\n\n void apply_mask(logits_buffer_t* __restrict__ logits_buffer,\n const int64_t logits_buffer_stride,\n const int32_t q_tile_start_pos,\n const int32_t kv_tile_start_pos,\n const int32_t kv_tile_end_pos, const int32_t q_token_num,\n const int32_t q_heads_per_kv,\n const int32_t sliding_window_left,\n const int32_t sliding_window_right) {\n // Apply mask\n constexpr logits_buffer_t neg_inf =\n -std::numeric_limits<logits_buffer_t>::infinity();\n logits_buffer_t* __restrict__ curr_logits_buffer = logits_buffer;\n int32_t curr_token_pos = q_tile_start_pos;\n for (int32_t token_idx = 0; token_idx < q_token_num; ++token_idx) {\n int32_t left_kv_pos = [&]() {\n int32_t pos = kv_tile_start_pos;\n if (sliding_window_left != -1) {\n pos = std::max(pos, curr_token_pos - sliding_window_left);\n }\n return pos;\n }();\n\n int32_t right_kv_pos = [&]() {\n int32_t pos = kv_tile_end_pos;\n if (sliding_window_right != -1) {\n pos = std::min(pos,\n std::max(kv_tile_start_pos,\n curr_token_pos + sliding_window_right + 1));\n }\n return pos;\n }();\n\n int32_t left_invalid_token_num = left_kv_pos - kv_tile_start_pos;\n int32_t right_invalid_token_num = kv_tile_end_pos - right_kv_pos;\n for (int32_t head_idx = 0; head_idx < q_heads_per_kv; ++head_idx) {\n logits_buffer_t* __restrict__ curr_logits_buffer_tail =\n curr_logits_buffer + right_kv_pos - kv_tile_start_pos;\n for (int32_t i = 0; i < left_invalid_token_num; ++i) {\n curr_logits_buffer[i] = neg_inf;\n }\n for (int32_t i = 0; i < right_invalid_token_num; ++i) {\n curr_logits_buffer_tail[i] = neg_inf;\n }\n\n curr_logits_buffer += logits_buffer_stride;\n }\n\n ++curr_token_pos;\n }\n }\n\n void apply_softmax(logits_buffer_t* __restrict__ logits_buffer,\n float* __restrict__ partial_q_buffer,\n float* __restrict__ max_buffer,\n float* __restrict__ sum_buffer,\n const int64_t logits_buffer_stride, int32_t q_head_num,\n int32_t kv_tile_token_num, bool is_first_iter,\n bool use_sink) {\n#ifdef DEFINE_FAST_EXP\n DEFINE_FAST_EXP\n#endif\n using prob_buffer_vec_t = typename VecTypeTrait<prob_buffer_t>::vec_t;\n static_assert(sizeof(prob_buffer_t) <= sizeof(logits_buffer_t));\n\n logits_buffer_t* __restrict__ curr_logits_buffer = logits_buffer;\n float* __restrict__ curr_partial_q_buffer = partial_q_buffer;\n const int32_t vec_num = kv_tile_token_num / 16;\n const int32_t head_vec_num = head_dim / 16;\n for (int32_t i = 0; i < q_head_num; ++i) {\n float init_max_val = max_buffer[i];\n float init_sum_val = sum_buffer[i];\n\n // apply scale and compute max\n vec_op::FP32Vec16 max_vec(init_max_val);\n {\n logits_buffer_t* __restrict__ curr_logits_buffer_iter =\n curr_logits_buffer;\n for (int32_t j = 0; j < vec_num; ++j) {\n vec_op::FP32Vec16 vec(curr_logits_buffer_iter);\n max_vec = vec.max(max_vec);\n\n curr_logits_buffer_iter += 16;\n }\n }\n float new_max_val = max_vec.reduce_max();\n float rescale_factor = init_max_val - new_max_val;\n\n // use same rescale threshold with FA4.\n // https://github.com/Dao-AILab/flash-attention/blob/1b8e1e641c6a179be9a0538b7f40fd595050b735/flash_attn/cute/flash_fwd_sm100.py#L1271\n bool need_rescale = rescale_factor < -8.0;\n if (!need_rescale) {\n new_max_val = init_max_val;\n } else {\n max_buffer[i] = new_max_val;\n }\n\n // sub max, compute exp and sum\n max_vec = vec_op::FP32Vec16(new_max_val);\n vec_op::FP32Vec16 sum_vec(0.0);\n {\n logits_buffer_t* __restrict__ curr_logits_buffer_iter =\n curr_logits_buffer;\n prob_buffer_t* __restrict__ curr_prob_buffer_iter =\n reinterpret_cast<prob_buffer_t*>(curr_logits_buffer);\n for (int32_t j = 0; j < vec_num; ++j) {\n vec_op::FP32Vec16 vec(curr_logits_buffer_iter);\n vec = vec - max_vec;\n\n // compute exp\n#ifdef DEFINE_FAST_EXP\n vec = fast_exp(vec);\n prob_buffer_vec_t output_vec(vec);\n output_vec.save(curr_prob_buffer_iter);\n#else\n vec.save(curr_logits_buffer_iter);\n for (int32_t k = 0; k < 16; ++k) {\n curr_logits_buffer_iter[k] = std::exp(curr_logits_buffer_iter[k]);\n }\n vec = vec_op::FP32Vec16(curr_logits_buffer_iter);\n#endif\n\n sum_vec = sum_vec + vec;\n\n curr_logits_buffer_iter += 16;\n curr_prob_buffer_iter += 16;\n }\n }\n float new_sum_val = sum_vec.reduce_sum();\n\n // rescale sum and partial outputs\n if (need_rescale) {\n // compute rescale factor\n rescale_factor = std::exp(rescale_factor);\n vec_op::FP32Vec16 rescale_factor_vec(rescale_factor);\n\n // rescale sum\n new_sum_val += rescale_factor * init_sum_val;\n\n // rescale output\n if (!is_first_iter) {\n float* __restrict__ curr_partial_q_buffer_iter =\n curr_partial_q_buffer;\n for (int32_t j = 0; j < head_vec_num; ++j) {\n vec_op::FP32Vec16 vec(curr_partial_q_buffer_iter);\n vec = vec * rescale_factor_vec;\n vec.save(curr_partial_q_buffer_iter);\n\n curr_partial_q_buffer_iter += 16;\n }\n }\n } else {\n new_sum_val += init_sum_val;\n }\n\n sum_buffer[i] = new_sum_val;\n\n curr_logits_buffer += logits_buffer_stride;\n curr_partial_q_buffer += head_dim;\n }\n }\n\n void apply_softcap(logits_buffer_t* __restrict__ logits_buffer,\n const int64_t logits_buffer_stride, int32_t q_head_num,\n int32_t kv_tile_token_num, float softcap_scale) {\n#ifdef DEFINE_FAST_EXP\n DEFINE_FAST_EXP\n#endif\n float inv_softcap_scale = 1.0 / softcap_scale;\n vec_op::FP32Vec16 softcap_scale_vec(softcap_scale);\n vec_op::FP32Vec16 inv_softcap_scale_vec(inv_softcap_scale);\n vec_op::FP32Vec16 ones_vec(1.0);\n logits_buffer_t* __restrict__ curr_logits_buffer = logits_buffer;\n const int32_t vec_num = kv_tile_token_num / 16;\n for (int32_t i = 0; i < q_head_num; ++i) {\n logits_buffer_t* __restrict__ curr_logits_buffer_iter =\n curr_logits_buffer;\n for (int32_t j = 0; j < vec_num; ++j) {\n vec_op::FP32Vec16 vec(curr_logits_buffer_iter);\n vec = vec * inv_softcap_scale_vec;\n\n#ifdef DEFINE_FAST_EXP\n vec = fast_exp(vec);\n vec_op::FP32Vec16 inv_vec = ones_vec / vec;\n vec = (vec - inv_vec) / (vec + inv_vec);\n#else\n vec.save(curr_logits_buffer_iter);\n for (int k = 0; k < 16; ++k) {\n curr_logits_buffer_iter[k] = std::tanh(curr_logits_buffer_iter[k]);\n }\n vec = vec_op::FP32Vec16(curr_logits_buffer_iter);\n#endif\n vec = vec * softcap_scale_vec;\n vec.save(curr_logits_buffer_iter);\n\n curr_logits_buffer_iter += 16;\n }\n\n curr_logits_buffer += logits_buffer_stride;\n }\n }\n\n void apply_alibi_slopes(logits_buffer_t* __restrict__ logits_buffer,\n const float* __restrict__ alibi_slopes,\n const int64_t logits_buffer_stride,\n const int32_t q_tile_start_pos,\n const int32_t kv_tile_start_pos,\n const int32_t q_token_num,\n const int32_t kv_tile_token_num,\n const int32_t q_heads_per_kv) {\n alignas(64) constexpr float initial_arange_vals[16] = {\n 0.0f, 1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 6.0f, 7.0f,\n 8.0f, 9.0f, 10.0f, 11.0f, 12.0f, 13.0f, 14.0f, 15.0f};\n const int32_t vec_num = kv_tile_token_num / 16;\n\n vec_op::FP32Vec16 initial_arange_vals_vec(initial_arange_vals);\n initial_arange_vals_vec =\n initial_arange_vals_vec + vec_op::FP32Vec16((float)kv_tile_start_pos);\n vec_op::FP32Vec16 pos_offset_vec(16.0);\n logits_buffer_t* __restrict__ curr_logits_buffer = logits_buffer;\n for (int32_t i = 0; i < q_token_num; ++i) {\n vec_op::FP32Vec16 curr_q_pos_vec((float)(i + q_tile_start_pos));\n for (int32_t j = 0; j < q_heads_per_kv; ++j) {\n vec_op::FP32Vec16 alibi_scale_vec(alibi_slopes[j]);\n vec_op::FP32Vec16 curr_kv_pos_vec(initial_arange_vals_vec);\n logits_buffer_t* __restrict__ curr_logits_buffer_iter =\n curr_logits_buffer;\n for (int32_t k = 0; k < vec_num; ++k) {\n vec_op::FP32Vec16 alibi_bias_vec =\n alibi_scale_vec * (curr_kv_pos_vec - curr_q_pos_vec);\n vec_op::FP32Vec16 vec(curr_logits_buffer_iter);\n vec = vec + alibi_bias_vec;\n\n vec.save(curr_logits_buffer_iter);\n\n curr_kv_pos_vec = curr_kv_pos_vec + pos_offset_vec;\n curr_logits_buffer_iter += 16;\n }\n curr_logits_buffer += logits_buffer_stride;\n }\n }\n }\n };\n\n public:\n void operator()(const AttentionInput* input) {\n const int thread_num = omp_get_max_threads();\n TORCH_CHECK_EQ(input->metadata->thread_num, thread_num);\n std::atomic<int32_t> guard_counter(0);\n std::atomic<int32_t>* guard_counter_ptr = &guard_counter;\n\n#pragma omp parallel for schedule(static, 1)\n for (int thread_id = 0; thread_id < thread_num; ++thread_id) {\n AttentionMetadata& metadata = *input->metadata;\n if (metadata.workitem_group_num == 0) {\n continue;\n }\n\n attention_impl_t attn_impl;\n\n // general information\n const int32_t q_head_num = input->num_heads;\n const int32_t kv_head_num = input->num_kv_heads;\n const int32_t q_heads_per_kv = q_head_num / kv_head_num;\n const bool use_gqa =\n (max_q_head_num_per_iter % q_heads_per_kv == 0) ? true : false;\n const int32_t actual_kv_head_num = use_gqa ? kv_head_num : q_head_num;\n const int32_t actual_q_heads_per_kv = use_gqa ? q_heads_per_kv : 1;\n TORCH_CHECK_LE(actual_q_heads_per_kv, max_q_head_num_per_iter);\n const int32_t max_q_token_num_per_iter =\n max_q_head_num_per_iter / actual_q_heads_per_kv;\n const int64_t q_token_num_stride = input->query_num_tokens_stride;\n const int64_t q_head_num_stride = input->query_num_heads_stride;\n const int64_t kv_cache_head_num_stride = input->cache_num_kv_heads_stride;\n const int64_t kv_cache_block_num_stride = input->cache_num_blocks_stride;\n const int32_t sliding_window_left = input->sliding_window_left;\n const int32_t sliding_window_right = input->sliding_window_right;\n const int32_t block_size = input->block_size;\n const float scale = input->scale;\n const float softcap_scale = input->softcap;\n const float* alibi_slopes = input->alibi_slopes;\n const c10::BFloat16* s_aux = input->s_aux;\n\n const bool casual = input->causal;\n int32_t* const block_table = input->block_table;\n const int64_t block_table_stride = input->blt_num_tokens_stride;\n\n // init buffers\n void* scratchpad_ptr =\n DNNLScratchPadManager::get_dnnl_scratchpad_manager()\n ->get_data<void>();\n AttentionScratchPad buffer_manager(thread_id, metadata, scratchpad_ptr);\n\n const int32_t total_reduction_split_num = metadata.reduction_split_num;\n if (metadata.reduction_split_num > 0) {\n // reset split flag\n for (int32_t head_idx = thread_id; head_idx < actual_kv_head_num;\n head_idx += thread_num) {\n buffer_manager.update(head_idx, total_reduction_split_num, head_dim,\n 0, sizeof(partial_output_buffer_t));\n volatile bool* __restrict__ curr_flag_ptr =\n buffer_manager.get_reduce_flag_buffer();\n for (int32_t split_idx = 0; split_idx < total_reduction_split_num;\n ++split_idx) {\n curr_flag_ptr[split_idx] = false;\n }\n }\n }\n\n const int64_t available_cache_size =\n AttentionScheduler::get_available_l2_size();\n const int32_t default_tile_size =\n AttentionScheduler::calcu_default_tile_size(\n available_cache_size, head_dim, sizeof(kv_cache_t),\n sizeof(q_buffer_t), sizeof(logits_buffer_t),\n sizeof(partial_output_buffer_t), max_q_head_num_per_iter,\n max_q_head_num_per_iter);\n const int32_t default_q_tile_token_num =\n default_tile_size / actual_q_heads_per_kv;\n\n AttentionWorkItemGroup* const workitem_groups =\n metadata.workitem_groups_ptr;\n const int32_t* cu_workitem_num_per_thread =\n metadata.cu_workitem_num_per_thread;\n ReductionWorkItemGroup* const reduction_items =\n metadata.reduction_items_ptr;\n\n const int32_t effective_thread_num = metadata.effective_thread_num;\n const int32_t reduction_item_num = metadata.reduction_item_num;\n const int32_t split_kv_q_token_num_threshold =\n metadata.split_kv_q_token_num_threshold;\n const int32_t workitem_groups_counter_num =\n actual_kv_head_num * effective_thread_num;\n const int32_t reduction_items_counter_num =\n actual_kv_head_num * reduction_item_num;\n const int32_t total_counter_num =\n workitem_groups_counter_num + reduction_items_counter_num;\n\n if (metadata.reduction_split_num > 0) {\n ++(*guard_counter_ptr);\n while (guard_counter_ptr->load() != thread_num) {\n#ifdef FAST_SPINNING\n FAST_SPINNING\n#else\n std::this_thread::yield();\n#endif\n }\n }\n\n // main loop\n for (;;) {\n int64_t task_idx = metadata.acquire_counter();\n\n if (task_idx >= total_counter_num) {\n // no more tasks, leave loop\n break;\n }\n\n if (task_idx < workitem_groups_counter_num) {\n // attention task\n // map task_idx to workitem_groups\n const int32_t kv_head_idx = task_idx / effective_thread_num;\n const int32_t thread_offset = task_idx % effective_thread_num;\n AttentionWorkItemGroup* const curr_workitem_groups =\n workitem_groups + cu_workitem_num_per_thread[thread_offset];\n const int32_t curr_workitem_groups_num =\n cu_workitem_num_per_thread[thread_offset + 1] -\n cu_workitem_num_per_thread[thread_offset];\n\n const int32_t q_head_start_idx = kv_head_idx * actual_q_heads_per_kv;\n\n for (int32_t workitem_group_idx = 0;\n workitem_group_idx < curr_workitem_groups_num;\n ++workitem_group_idx) {\n AttentionWorkItemGroup* const current_workitem_group =\n &curr_workitem_groups[workitem_group_idx];\n\n const int32_t current_group_idx = current_workitem_group->req_id;\n const int32_t kv_start_pos =\n current_workitem_group->kv_split_pos_start;\n const int32_t kv_end_pos = current_workitem_group->kv_split_pos_end;\n const int32_t curr_spilt_id = current_workitem_group->split_id;\n const int32_t q_token_id_start =\n current_workitem_group->q_token_id_start;\n const int32_t q_token_num = current_workitem_group->q_token_num;\n\n // taskgroup general information\n const int32_t q_end = input->query_start_loc[current_group_idx + 1];\n const int32_t q_start = input->query_start_loc[current_group_idx];\n const int32_t seq_len = input->seq_lens[current_group_idx];\n const int32_t q_start_pos =\n (casual ? seq_len - (q_end - q_start) : 0);\n const int32_t block_num = (seq_len + block_size - 1) / block_size;\n // Only apply sink for the first KV split\n bool use_sink = (s_aux != nullptr &&\n current_workitem_group->local_split_id == 0);\n\n for (int32_t q_token_offset = 0; q_token_offset < q_token_num;\n q_token_offset += default_q_tile_token_num) {\n bool first_iter_flag[AttentionScheduler::MaxQTileIterNum];\n for (int32_t i = 0; i < AttentionScheduler::MaxQTileIterNum;\n ++i) {\n first_iter_flag[i] = true;\n }\n\n const int32_t q_token_start_idx =\n q_start + q_token_offset + q_token_id_start;\n const int32_t actual_q_token_num = std::min(\n default_q_tile_token_num, q_token_num - q_token_offset);\n const int32_t q_head_tile_size =\n actual_q_token_num * actual_q_heads_per_kv;\n const int32_t rounded_q_head_tile_size =\n ((q_head_tile_size + max_q_head_num_per_iter - 1) /\n max_q_head_num_per_iter) *\n max_q_head_num_per_iter;\n const int32_t kv_tile_size =\n AttentionScheduler::calcu_tile_size_with_constant_q(\n available_cache_size, head_dim, sizeof(kv_cache_t),\n sizeof(q_buffer_t), sizeof(logits_buffer_t),\n sizeof(partial_output_buffer_t), max_q_head_num_per_iter,\n blocksize_alignment, rounded_q_head_tile_size,\n rounded_q_head_tile_size <= max_q_head_num_per_iter);\n\n // update buffers\n buffer_manager.update(\n head_dim, sizeof(q_buffer_t), sizeof(logits_buffer_t),\n sizeof(partial_output_buffer_t), max_q_head_num_per_iter,\n rounded_q_head_tile_size, kv_tile_size);\n q_buffer_t* q_buffer = buffer_manager.get_q_buffer<q_buffer_t>();\n float* logits_buffer = buffer_manager.get_logits_buffer();\n float* partial_q_buffer = buffer_manager.get_output_buffer();\n float* max_buffer = buffer_manager.get_max_buffer();\n float* sum_buffer = buffer_manager.get_sum_buffer();\n\n const int32_t q_tile_start_pos =\n q_start_pos + q_token_offset + q_token_id_start;\n const int32_t q_tile_end_pos =\n q_tile_start_pos + actual_q_token_num;\n const auto [kv_tile_start_pos, kv_tile_end_pos] =\n AttentionScheduler::calcu_kv_tile_pos(\n kv_start_pos, kv_end_pos, q_tile_start_pos,\n q_tile_end_pos, sliding_window_left,\n sliding_window_right);\n const auto [rounded_kv_tile_start_pos, rounded_kv_tile_end_pos] =\n AttentionScheduler::align_kv_tile_pos(\n kv_tile_start_pos, kv_tile_end_pos, blocksize_alignment);\n\n int32_t curr_kv_head_idx =\n use_gqa ? kv_head_idx\n : (kv_head_idx /\n q_heads_per_kv); // for GQA disabled case\n\n // std::printf(\"thread_id: %d, req_id: %d, q_token_start: %d,\n // q_token_end: %d, q_head_start: %d, q_head_end: %d, kv_head_idx:\n // %d, kv_pos_start: %d, kv_pos_end: %d\\n\",\n // thread_id, current_group_idx,\n // q_token_start_idx, q_token_start_idx +\n // actual_q_token_num, q_head_start_idx,\n // q_head_start_idx + actual_q_heads_per_kv,\n // curr_kv_head_idx, kv_tile_start_pos,\n // kv_tile_end_pos);\n\n // move buffers\n kv_cache_t* curr_k_cache =\n reinterpret_cast<kv_cache_t*>(input->key_cache) +\n curr_kv_head_idx * kv_cache_head_num_stride;\n kv_cache_t* curr_v_cache =\n reinterpret_cast<kv_cache_t*>(input->value_cache) +\n curr_kv_head_idx * kv_cache_head_num_stride;\n query_t* const q_tile_ptr =\n reinterpret_cast<query_t*>(input->query) +\n q_token_start_idx * q_token_num_stride +\n q_head_start_idx * q_head_num_stride;\n size_t output_buffer_offset =\n q_token_start_idx * q_head_num * head_dim +\n q_head_start_idx * head_dim;\n int32_t* curr_block_table =\n block_table + current_group_idx * block_table_stride;\n const float* curr_alibi_slopes =\n (alibi_slopes != nullptr ? alibi_slopes + q_head_start_idx\n : nullptr);\n const c10::BFloat16* curr_s_aux =\n (s_aux != nullptr ? s_aux + q_head_start_idx : nullptr);\n\n // copy the Q tile to q_buffer, the logical layout of q_buffer is\n // [actual_q_token_num, actual_q_heads_per_kv, head_dim]\n {\n attn_impl.copy_q_heads_tile(\n q_tile_ptr, q_buffer, actual_q_token_num,\n actual_q_heads_per_kv, q_token_num_stride,\n q_head_num_stride, scale);\n }\n\n if (use_sink) {\n alignas(64) float s_aux_fp32[16];\n#if defined(__aarch64__) && !defined(ARM_BF16_SUPPORT)\n // ARM without native BF16 support: manual conversion\n for (int i = 0; i < 16; ++i) {\n s_aux_fp32[i] = static_cast<float>(curr_s_aux[i]);\n }\n#else\n // All other platforms have BF16Vec16 available\n vec_op::BF16Vec16 vec_bf16(curr_s_aux);\n vec_op::FP32Vec16 vec_fp32(vec_bf16);\n vec_fp32.save(s_aux_fp32);\n#endif\n\n float* __restrict__ curr_sum_buffer = sum_buffer;\n float* __restrict__ curr_max_buffer = max_buffer;\n for (int32_t token_idx = 0; token_idx < actual_q_token_num;\n ++token_idx) {\n for (int32_t head_idx = 0; head_idx < actual_q_heads_per_kv;\n ++head_idx) {\n curr_sum_buffer[head_idx] = 1.0f;\n curr_max_buffer[head_idx] = s_aux_fp32[head_idx];\n }\n\n curr_sum_buffer += actual_q_heads_per_kv;\n curr_max_buffer += actual_q_heads_per_kv;\n }\n } else {\n float* __restrict__ curr_sum_buffer = sum_buffer;\n float* __restrict__ curr_max_buffer = max_buffer;\n for (int32_t token_idx = 0; token_idx < actual_q_token_num;\n ++token_idx) {\n for (int32_t head_idx = 0; head_idx < actual_q_heads_per_kv;\n ++head_idx) {\n curr_sum_buffer[head_idx] = 0.0f;\n curr_max_buffer[head_idx] =\n std::numeric_limits<float>::lowest();\n }\n\n curr_sum_buffer += actual_q_heads_per_kv;\n curr_max_buffer += actual_q_heads_per_kv;\n }\n }\n\n // compute loop\n for (int32_t kv_tile_pos = rounded_kv_tile_start_pos;\n kv_tile_pos < rounded_kv_tile_end_pos;\n kv_tile_pos += kv_tile_size) {\n const int32_t kv_tile_pos_left = kv_tile_pos;\n const int32_t kv_tile_pos_right = std::min(\n kv_tile_pos_left + kv_tile_size, rounded_kv_tile_end_pos);\n for (int32_t q_head_tile_token_offset = 0;\n q_head_tile_token_offset < actual_q_token_num;\n q_head_tile_token_offset += max_q_token_num_per_iter) {\n const int32_t q_tile_pos_left =\n q_tile_start_pos + q_head_tile_token_offset;\n const int32_t q_tile_token_num =\n std::min(max_q_token_num_per_iter,\n actual_q_token_num - q_head_tile_token_offset);\n const int32_t q_tile_head_offset =\n q_head_tile_token_offset * actual_q_heads_per_kv;\n const int32_t q_tile_head_num =\n q_tile_token_num * actual_q_heads_per_kv;\n const int32_t q_tile_pos_right =\n q_tile_pos_left + q_tile_token_num;\n const auto [actual_kv_tile_pos_left,\n actual_kv_tile_pos_right] =\n AttentionScheduler::calcu_kv_tile_pos(\n kv_tile_pos_left, kv_tile_pos_right, q_tile_pos_left,\n q_tile_pos_right, sliding_window_left,\n sliding_window_right);\n const int32_t q_iter_idx =\n q_head_tile_token_offset / max_q_token_num_per_iter;\n\n if (actual_kv_tile_pos_right <= actual_kv_tile_pos_left) {\n continue;\n }\n\n // align kv_pos to blocksize_alignment\n const auto [aligned_actual_kv_tile_pos_left,\n aligned_actual_kv_tile_pos_right] =\n AttentionScheduler::align_kv_tile_pos(\n actual_kv_tile_pos_left, actual_kv_tile_pos_right,\n blocksize_alignment);\n const int32_t actual_kv_token_num =\n aligned_actual_kv_tile_pos_right -\n aligned_actual_kv_tile_pos_left;\n\n // std::printf(\"\\tq_iter_idx: %d, q_token_start: %d,\n // q_token_end: %d, q_token_num: %d, q_head_num: %d,\n // q_pos_start: %d, q_pos_end: %d, kv_pos_start: %d,\n // kv_pos_end: %d\\n\",\n // q_iter_idx, q_token_start_idx +\n // q_head_tile_token_offset, q_token_start_idx +\n // q_head_tile_token_offset + q_tile_token_num,\n // q_tile_token_num, q_tile_head_num,\n // q_tile_pos_left, q_tile_pos_right,\n // aligned_actual_kv_tile_pos_left,\n // aligned_actual_kv_tile_pos_right);\n\n // Move buffers\n q_buffer_t* curr_q_heads_buffer =\n q_buffer + q_tile_head_offset * head_dim;\n float* curr_partial_q_buffer =\n partial_q_buffer + q_tile_head_offset * head_dim;\n float* curr_max_buffer = max_buffer + q_tile_head_offset;\n float* curr_sum_buffer = sum_buffer + q_tile_head_offset;\n\n bool debug_info = false;\n // bool debug_info = (\n // q_head_start_idx == 4 &&\n // (q_token_start_idx + q_head_tile_token_offset) <=\n // 4\n // && (q_token_start_idx + q_head_tile_token_offset +\n // q_tile_token_num) > 4\n // );\n // if (debug_info) {\n // std::printf(\"\\tq_iter_idx: %d, q_token_start: %d,\"\n // \"q_token_end: %d, q_token_num: %d, q_head_num: %d,\"\n // \"q_pos_start: %d, q_pos_end: %d, kv_pos_start: %d,\"\n // \"kv_pos_end: %d\\n\",\n // q_iter_idx, q_token_start_idx +\n // q_head_tile_token_offset, q_token_start_idx\n // + q_head_tile_token_offset +\n // q_tile_token_num, q_tile_token_num,\n // q_tile_head_num, q_tile_pos_left,\n // q_tile_pos_right,\n // aligned_actual_kv_tile_pos_left,\n // aligned_actual_kv_tile_pos_right);\n // }\n\n attn_impl.template execute_attention<Attention>(\n curr_q_heads_buffer, curr_k_cache, curr_v_cache,\n logits_buffer, curr_partial_q_buffer, curr_max_buffer,\n curr_sum_buffer, curr_block_table,\n aligned_actual_kv_tile_pos_left,\n aligned_actual_kv_tile_pos_right, actual_kv_token_num,\n kv_cache_block_num_stride, q_tile_head_num,\n q_tile_token_num, q_tile_pos_left, actual_q_heads_per_kv,\n block_size, sliding_window_left, sliding_window_right,\n scale, softcap_scale, curr_alibi_slopes,\n first_iter_flag[q_iter_idx], use_sink, debug_info);\n first_iter_flag[q_iter_idx] = false;\n }\n }\n\n // write back partial results to output buffer or reduction buffer\n {\n if (curr_spilt_id == -1) {\n final_output(partial_q_buffer,\n reinterpret_cast<query_t*>(input->output) +\n output_buffer_offset,\n sum_buffer, actual_q_heads_per_kv,\n actual_q_token_num, q_head_num);\n } else {\n const int32_t stride =\n actual_q_heads_per_kv * split_kv_q_token_num_threshold;\n buffer_manager.update(kv_head_idx, total_reduction_split_num,\n head_dim, stride, sizeof(float));\n volatile bool* split_flag_buffer =\n buffer_manager.get_reduce_flag_buffer() + curr_spilt_id;\n float* split_output_buffer =\n buffer_manager.get_reduce_output_buffer() +\n curr_spilt_id * stride * head_dim;\n float* split_max_buffer =\n buffer_manager.get_reduce_max_buffer() +\n curr_spilt_id * stride;\n float* split_sum_buffer =\n buffer_manager.get_reduce_sum_buffer() +\n curr_spilt_id * stride;\n\n partial_output(partial_q_buffer, max_buffer, sum_buffer,\n q_head_tile_size, split_output_buffer,\n split_max_buffer, split_sum_buffer,\n split_flag_buffer);\n }\n }\n }\n }\n } else {\n task_idx -= workitem_groups_counter_num;\n const int32_t kv_head_idx = task_idx / reduction_item_num;\n const int32_t item_offset = task_idx % reduction_item_num;\n ReductionWorkItemGroup* const curr_workitem_groups =\n reduction_items + item_offset;\n const int32_t curr_output_token_idx =\n curr_workitem_groups->q_token_id_start;\n const int32_t curr_output_token_num =\n curr_workitem_groups->q_token_id_num;\n const int32_t curr_split_id = curr_workitem_groups->split_start_id;\n const int32_t curr_split_num = curr_workitem_groups->split_num;\n const int32_t current_group_idx = curr_workitem_groups->req_id;\n const int32_t curr_output_head_num =\n curr_output_token_num * actual_q_heads_per_kv;\n\n const int32_t q_start = input->query_start_loc[current_group_idx];\n const int32_t q_token_start_idx = q_start + curr_output_token_idx;\n const int32_t q_head_start_idx = kv_head_idx * actual_q_heads_per_kv;\n size_t output_buffer_offset =\n q_token_start_idx * q_head_num * head_dim +\n q_head_start_idx * head_dim;\n\n const int32_t stride =\n actual_q_heads_per_kv * split_kv_q_token_num_threshold;\n buffer_manager.update(kv_head_idx, total_reduction_split_num,\n head_dim, stride, sizeof(float));\n volatile bool* split_flag_buffer =\n buffer_manager.get_reduce_flag_buffer() + curr_split_id;\n float* split_output_buffer =\n buffer_manager.get_reduce_output_buffer() +\n curr_split_id * stride * head_dim;\n float* split_max_buffer =\n buffer_manager.get_reduce_max_buffer() + curr_split_id * stride;\n float* split_sum_buffer =\n buffer_manager.get_reduce_sum_buffer() + curr_split_id * stride;\n\n reduce_splits(split_output_buffer, split_max_buffer, split_sum_buffer,\n split_flag_buffer, stride, curr_output_head_num,\n curr_split_num);\n final_output(\n split_output_buffer,\n reinterpret_cast<query_t*>(input->output) + output_buffer_offset,\n split_sum_buffer, actual_q_heads_per_kv, curr_output_token_num,\n q_head_num);\n }\n }\n }\n // Reset counter for next call\n input->metadata->reset_counter();\n }\n\n void reduce_splits(float* __restrict__ split_output_buffer,\n float* __restrict__ split_max_buffer,\n float* __restrict__ split_sum_buffer,\n volatile bool* __restrict__ flags,\n const int32_t head_num_per_split,\n const int32_t curr_head_num, const int32_t split_num) {\n#ifdef DEFINE_FAST_EXP\n DEFINE_FAST_EXP\n#endif\n // restrict curr_head_num <= 16 in the scheduler\n // elems in split_max_buffer, split_sum_buffer are not cache alignment, use\n // local buffers to reduce false-sharing\n alignas(64) float local_max[16];\n alignas(64) float local_sum[16];\n\n float* __restrict__ curr_split_output_buffer = split_output_buffer;\n float* __restrict__ curr_split_max_buffer = split_max_buffer;\n float* __restrict__ curr_split_sum_buffer = split_sum_buffer;\n constexpr int32_t head_dim_group_num = head_dim / 16;\n for (int32_t split_idx = 0; split_idx < split_num; ++split_idx) {\n while (!flags[split_idx]) {\n#ifdef FAST_SPINNING\n FAST_SPINNING\n#else\n std::this_thread::yield();\n#endif\n }\n std::atomic_thread_fence(std::memory_order_acquire);\n\n if (split_idx > 0) {\n float* __restrict__ curr_output_buffer = split_output_buffer;\n float* __restrict__ curr_split_output_buffer_iter =\n curr_split_output_buffer;\n for (int32_t head_idx = 0; head_idx < curr_head_num; ++head_idx) {\n float final_max = local_max[head_idx];\n float curr_max = curr_split_max_buffer[head_idx];\n float final_sum = local_sum[head_idx];\n float curr_sum = curr_split_sum_buffer[head_idx];\n float* __restrict__ non_scale_output_iter =\n final_max > curr_max ? curr_output_buffer\n : curr_split_output_buffer_iter;\n float* __restrict__ scale_output_iter =\n final_max > curr_max ? curr_split_output_buffer_iter\n : curr_output_buffer;\n float rescale_factor = final_max > curr_max ? curr_max - final_max\n : final_max - curr_max;\n rescale_factor = std::exp(rescale_factor);\n vec_op::FP32Vec16 rescale_factor_vec(rescale_factor);\n\n local_sum[head_idx] = final_max > curr_max\n ? final_sum + rescale_factor * curr_sum\n : rescale_factor * final_sum + curr_sum;\n\n final_max = std::max(final_max, curr_max);\n local_max[head_idx] = final_max;\n for (int32_t i = 0; i < head_dim_group_num; ++i) {\n vec_op::FP32Vec16 non_scale_vec(non_scale_output_iter);\n vec_op::FP32Vec16 scale_vec(scale_output_iter);\n vec_op::FP32Vec16 final_vec =\n non_scale_vec + scale_vec * rescale_factor_vec;\n final_vec.save(curr_output_buffer);\n\n non_scale_output_iter += 16;\n scale_output_iter += 16;\n curr_output_buffer += 16;\n }\n curr_split_output_buffer_iter += head_dim;\n }\n } else {\n vec_op::FP32Vec16 final_max(split_max_buffer);\n final_max.save(local_max);\n vec_op::FP32Vec16 final_sum(split_sum_buffer);\n final_sum.save(local_sum);\n }\n\n curr_split_output_buffer += head_num_per_split * head_dim;\n curr_split_max_buffer += head_num_per_split;\n curr_split_sum_buffer += head_num_per_split;\n }\n // write back final max and sum\n for (int32_t i = 0; i < curr_head_num; ++i) {\n split_max_buffer[i] = local_max[i];\n split_sum_buffer[i] = local_sum[i];\n }\n }\n\n void partial_output(float* __restrict__ partial_output_buffer,\n float* __restrict__ partial_max_buffer,\n float* __restrict__ partial_sum_buffer,\n int32_t curr_head_num,\n float* __restrict__ split_output_buffer,\n float* __restrict__ split_max_buffer,\n float* __restrict__ split_sum_buffer,\n volatile bool* __restrict__ flag) {\n float* __restrict__ curr_partial_output_buffer = partial_output_buffer;\n float* __restrict__ curr_split_output_buffer = split_output_buffer;\n constexpr int32_t head_dim_group_num = head_dim / 16;\n for (int32_t i = 0; i < curr_head_num; ++i) {\n split_max_buffer[i] = partial_max_buffer[i];\n split_sum_buffer[i] = partial_sum_buffer[i];\n for (int32_t j = 0; j < head_dim_group_num; ++j) {\n vec_op::FP32Vec16 vec(curr_partial_output_buffer);\n vec.save(curr_split_output_buffer);\n\n curr_partial_output_buffer += 16;\n curr_split_output_buffer += 16;\n }\n }\n std::atomic_thread_fence(std::memory_order_release);\n *flag = true;\n }\n\n void final_output(float* __restrict__ partial_q_buffer,\n query_t* __restrict__ curr_output_buffer,\n float* __restrict__ sum_buffer,\n const int32_t q_heads_per_kv,\n const int32_t actual_q_token_num,\n const int32_t q_head_num) {\n // final output\n using output_vec_t = typename VecTypeTrait<query_t>::vec_t;\n\n float* __restrict__ curr_partial_output_buffer = partial_q_buffer;\n float* __restrict__ curr_sum_buffer = sum_buffer;\n constexpr int32_t group_num_per_head = head_dim / 16;\n const int32_t partial_q_buffer_stride = q_heads_per_kv * head_dim;\n const int32_t output_buffer_stride = q_head_num * head_dim;\n for (int32_t token_idx = 0; token_idx < actual_q_token_num; ++token_idx) {\n float* __restrict__ curr_partial_output_buffer_iter =\n curr_partial_output_buffer;\n query_t* __restrict__ curr_output_buffer_iter = curr_output_buffer;\n for (int32_t head_idx = 0; head_idx < q_heads_per_kv; ++head_idx) {\n vec_op::FP32Vec16 inv_sum_scale_vec(1.0 / *curr_sum_buffer);\n\n for (int32_t i = 0; i < group_num_per_head; ++i) {\n vec_op::FP32Vec16 vec(curr_partial_output_buffer_iter);\n // divide the final sum val of softmax here\n vec = inv_sum_scale_vec * vec;\n\n // cast to query type\n output_vec_t output_vec(vec);\n output_vec.save(curr_output_buffer_iter);\n\n // update\n curr_partial_output_buffer_iter += 16;\n curr_output_buffer_iter += 16;\n }\n\n // update\n curr_sum_buffer += 1;\n }\n\n // update\n curr_partial_output_buffer += partial_q_buffer_stride;\n curr_output_buffer += output_buffer_stride;\n }\n }\n};\n\n} // namespace cpu_attention\n\n#endif\n"},"diff":{"kind":"string","value":"--- csrc/cpu/cpu_attn_impl.hpp\n+++ csrc/cpu/cpu_attn_impl.hpp\n@@ -1246,14 +1246,8 @@\n // rescale sum and partial outputs\n if (need_rescale) {\n // compute rescale factor\n-#ifdef DEFINE_FAST_EXP\n- vec_op::FP32Vec16 rescale_factor_vec(rescale_factor);\n- rescale_factor_vec = fast_exp(rescale_factor_vec);\n- rescale_factor = rescale_factor_vec.get_last_elem();\n-#else\n rescale_factor = std::exp(rescale_factor);\n vec_op::FP32Vec16 rescale_factor_vec(rescale_factor);\n-#endif\n \n // rescale sum\n new_sum_val += rescale_factor * init_sum_val;\n@@ -1889,15 +1883,8 @@\n : curr_output_buffer;\n float rescale_factor = final_max > curr_max ? curr_max - final_max\n : final_max - curr_max;\n-\n-#ifdef DEFINE_FAST_EXP\n- vec_op::FP32Vec16 rescale_factor_vec(rescale_factor);\n- rescale_factor_vec = fast_exp(rescale_factor_vec);\n- rescale_factor = rescale_factor_vec.get_last_elem();\n-#else\n rescale_factor = std::exp(rescale_factor);\n vec_op::FP32Vec16 rescale_factor_vec(rescale_factor);\n-#endif\n \n local_sum[head_idx] = final_max > curr_max\n ? final_sum + rescale_factor * curr_sum"},"lines_added":{"kind":"number","value":0,"string":"0"},"lines_removed":{"kind":"number","value":13,"string":"13"},"files_in_commit":{"kind":"number","value":2,"string":"2"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["CPU"],"string":"[\n \"CPU\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cpp kernel file from vllm (csrc/cpu/cpu_attn_impl.hpp).\n\nGoal: [CPU][Perf] Add fast vectorized exp impl from Arm Optimized Routines\nTarget hardware: CPU\nTarget models: unspecified\n\nCurrent file:\n```cpp\n#ifndef CPU_ATTN_HPP\n#define CPU_ATTN_HPP\n\n#include <type_traits>\n#include <cstddef>\n\n#if defined(__APPLE__)\n #include <sys/sysctl.h>\n#endif\n\n#include \"cpu_types.hpp\"\n#include \"scratchpad_manager.h\"\n#include \"cpu_attn_macros.h\"\n#include \"utils.hpp\"\n\nnamespace cpu_attention {\nenum class ISA { AMX, VEC, VEC16, NEON };\n\ntemplate <ISA isa, typename scalar_t, int64_t head_dim>\nclass AttentionImpl {};\n\nstruct AttentionWorkItemGroup {\n int32_t req_id;\n int32_t q_token_id_start;\n int32_t q_token_num;\n int32_t kv_split_pos_start;\n int32_t kv_split_pos_end;\n\n int64_t total_kv_len;\n int32_t split_id;\n int32_t local_split_id;\n\n AttentionWorkItemGroup(const int32_t req_id, const int32_t q_token_id_start,\n const int32_t kv_split_pos_start,\n const int32_t kv_split_pos_end)\n : req_id(req_id),\n q_token_id_start(q_token_id_start),\n q_token_num(0),\n kv_split_pos_start(kv_split_pos_start),\n kv_split_pos_end(kv_split_pos_end),\n total_kv_len(0),\n split_id(-1),\n local_split_id(0) {}\n\n std::string to_string() const {\n std::stringstream ss;\n ss << '[' << \"req_id: \" << req_id << \",\\n\";\n ss << \"q_token_id_start: \" << q_token_id_start << \",\\n\";\n ss << \"q_token_num: \" << q_token_num << \",\\n\";\n ss << \"kv_split_pos_start: \" << kv_split_pos_start << \",\\n\";\n ss << \"kv_split_pos_end: \" << kv_split_pos_end << \",\\n\";\n ss << \"total_kv_len: \" << total_kv_len << \",\\n\";\n ss << \"split_id: \" << split_id << \",\\n\";\n ss << \"local_split_id: \" << local_split_id << \",\\n\";\n ss << ']';\n\n return ss.str();\n }\n};\n\nstruct ReductionWorkItemGroup {\n int32_t req_id;\n int32_t q_token_id_start;\n int32_t q_token_id_num;\n int32_t split_start_id;\n int32_t split_num;\n\n ReductionWorkItemGroup(const int32_t req_id, const int32_t q_token_id_start,\n const int32_t q_token_id_num,\n const int32_t split_start_id)\n : req_id(req_id),\n q_token_id_start(q_token_id_start),\n q_token_id_num(q_token_id_num),\n split_start_id(split_start_id),\n split_num(0) {}\n\n std::string to_string() const {\n std::stringstream ss;\n ss << '[' << \"req_id: \" << req_id << \",\\n\";\n ss << \"q_token_id_start: \" << q_token_id_start << \",\\n\";\n ss << \"q_token_id_num: \" << q_token_id_num << \",\\n\";\n ss << \"split_start_id: \" << split_start_id << \",\\n\";\n ss << \"split_num: \" << split_num << \",\\n\";\n ss << ']';\n\n return ss.str();\n }\n};\n\nstruct AttentionMetadata {\n std::atomic_int64_t counter;\n char _padding1[56];\n ISA isa;\n int32_t workitem_group_num;\n int32_t reduction_item_num;\n int32_t reduction_split_num;\n int32_t thread_num;\n int32_t effective_thread_num; // non-zero item num in workitem_num_per_thread\n int32_t split_kv_q_token_num_threshold;\n int64_t attention_scratchpad_size_per_thread;\n int64_t reduction_scratchpad_size_per_kv_head;\n AttentionWorkItemGroup* workitem_groups_ptr;\n ReductionWorkItemGroup* reduction_items_ptr;\n int32_t cu_workitem_num_per_thread[1025] = {\n 0}; // prefix sum of workitem_num_per_thread\n char _padding2[56];\n\n AttentionMetadata(ISA isa, int32_t workitem_group_num,\n int32_t reduction_item_num, int32_t reduction_split_num,\n int32_t split_kv_q_token_num_threshold)\n : isa(isa),\n workitem_group_num(workitem_group_num),\n reduction_item_num(reduction_item_num),\n reduction_split_num(reduction_split_num),\n thread_num(omp_get_max_threads()),\n effective_thread_num(thread_num),\n split_kv_q_token_num_threshold(split_kv_q_token_num_threshold),\n attention_scratchpad_size_per_thread(0),\n reduction_scratchpad_size_per_kv_head(0),\n workitem_groups_ptr(\n (AttentionWorkItemGroup*)((char*)this + sizeof(AttentionMetadata))),\n reduction_items_ptr(\n (ReductionWorkItemGroup*)((char*)this + sizeof(AttentionMetadata) +\n workitem_group_num *\n sizeof(AttentionWorkItemGroup))),\n counter(0) {\n TORCH_CHECK_LE(thread_num, 1024);\n static_assert(sizeof(AttentionMetadata) % 64 == 0);\n TORCH_CHECK(reinterpret_cast<size_t>(this) % 64 == 0);\n }\n\n void reset_counter() { counter.store(0); }\n\n int64_t acquire_counter() { return counter++; }\n\n void print() const {\n std::stringstream ss;\n ss << \"ISA: \";\n switch (isa) {\n case ISA::AMX:\n ss << \"AMX, \";\n break;\n case ISA::VEC:\n ss << \"VEC, \";\n break;\n case ISA::VEC16:\n ss << \"VEC16, \";\n break;\n case ISA::NEON:\n ss << \"NEON, \";\n break;\n }\n ss << \"workitem_group_num: \" << workitem_group_num\n << \", reduction_item_num: \" << reduction_item_num\n << \", reduction_split_num: \" << reduction_split_num\n << \", thread_num: \" << thread_num\n << \", effective_thread_num: \" << effective_thread_num\n << \", attention_scratchpad_size_per_thread: \"\n << attention_scratchpad_size_per_thread\n << \", reduction_scratchpad_size_per_kv_head: \"\n << reduction_scratchpad_size_per_kv_head << \", workitem groups:\\n\";\n for (int32_t i = 0; i < workitem_group_num; ++i) {\n ss << (workitem_groups_ptr + i)->to_string() << \",\\n\";\n }\n\n ss << \"cu_workitem_num_per_thread: [\";\n for (int32_t i = 0; i < thread_num + 1; ++i) {\n ss << cu_workitem_num_per_thread[i] << \", \";\n }\n ss << \"]\\n\";\n\n ss << \"reduction items: \\n\";\n\n for (int32_t i = 0; i < reduction_item_num; ++i) {\n ss << (reduction_items_ptr + i)->to_string() << \",\\n\";\n }\n\n std::printf(\"%s\", ss.str().c_str());\n }\n};\n\n// Thread attention scratchpad contains:\n// - Q: q_tile_size * head_dim * q_buffer_elem_size, gather Q heads, especially\n// for GQA\n// - Q@K^T: max_num_q_per_iter * k_tile_size * logits_buffer_elem_size, logits\n// - Intermediate outputs: q_tile_size * head_dim * output_buffer_elem_size + 2\n// * q_tile_size * 4, partial output, max + sum (float)\n// Reduction scratchpad contains:\n// - flags: bool array to indicate wether the split is finished\n// - outputs: split_num * q_tile_size * head_dim * output_buffer_elem_size\n// - max, sum: 2 * split_num * q_tile_size * 4\nclass AttentionScratchPad {\n public:\n AttentionScratchPad(int64_t thread_id,\n const AttentionMetadata& attention_metadata,\n void* scratchpad_ptr)\n : thread_scratchpad_ptr(\n static_cast<int8_t*>(scratchpad_ptr) +\n thread_id *\n attention_metadata.attention_scratchpad_size_per_thread),\n reduction_scratchpad_ptr(\n static_cast<int8_t*>(scratchpad_ptr) +\n attention_metadata.thread_num *\n attention_metadata.attention_scratchpad_size_per_thread),\n reduction_scratchpad_size_per_kv_head(\n attention_metadata.reduction_scratchpad_size_per_kv_head) {}\n\n // for attention\n void update(const int64_t head_dim, const int64_t q_buffer_elem_size,\n const int64_t logits_buffer_elem_size,\n const int64_t output_buffer_elem_size,\n const int64_t max_num_q_per_iter, const int64_t q_head_tile_size,\n const int64_t kv_tile_size) {\n int64_t buffer_offset = 0;\n q_buffer_offset_ = buffer_offset;\n buffer_offset +=\n calcu_q_buffer_size(q_head_tile_size, head_dim, q_buffer_elem_size);\n logits_buffer_offset_ = buffer_offset;\n buffer_offset += calcu_logits_buffer_size(max_num_q_per_iter, kv_tile_size,\n logits_buffer_elem_size);\n output_buffer_offset_ = buffer_offset;\n buffer_offset += calcu_partial_output_buffer_size(\n q_head_tile_size, head_dim, output_buffer_elem_size);\n max_buffer_offset_ = buffer_offset;\n buffer_offset += calcu_partial_output_max_sum_buffer_size(q_head_tile_size);\n sum_buffer_offset_ = buffer_offset;\n }\n\n // for reduction\n void update(const int32_t kv_head_idx, const int32_t total_split_num,\n const int64_t head_dim, const int64_t q_head_tile_size,\n const int64_t output_buffer_elem_size) {\n int64_t buffer_offset = kv_head_idx * reduction_scratchpad_size_per_kv_head;\n reduce_flag_buffer_offset_ = buffer_offset;\n buffer_offset += calcu_reduce_flag_buffer_size(total_split_num);\n reduce_output_buffer_offset_ = buffer_offset;\n buffer_offset += calcu_reduce_output_buffer_size(\n total_split_num, q_head_tile_size, head_dim, output_buffer_elem_size);\n reduce_max_buffer_offset_ = buffer_offset;\n buffer_offset +=\n calcu_reduce_max_sum_buffer_size(total_split_num, q_head_tile_size);\n reduce_sum_buffer_offset_ = buffer_offset;\n }\n\n template <typename T>\n T* get_q_buffer() {\n return reinterpret_cast<T*>(thread_scratchpad_ptr + q_buffer_offset_);\n }\n\n float* get_logits_buffer() {\n return reinterpret_cast<float*>(thread_scratchpad_ptr +\n logits_buffer_offset_);\n }\n\n float* get_output_buffer() {\n return reinterpret_cast<float*>(thread_scratchpad_ptr +\n output_buffer_offset_);\n }\n\n float* get_max_buffer() {\n return reinterpret_cast<float*>(thread_scratchpad_ptr + max_buffer_offset_);\n }\n\n float* get_sum_buffer() {\n return reinterpret_cast<float*>(thread_scratchpad_ptr + sum_buffer_offset_);\n }\n\n volatile bool* get_reduce_flag_buffer() {\n return reinterpret_cast<volatile bool*>(reduction_scratchpad_ptr +\n reduce_flag_buffer_offset_);\n }\n\n float* get_reduce_output_buffer() {\n return reinterpret_cast<float*>(reduction_scratchpad_ptr +\n reduce_output_buffer_offset_);\n }\n\n float* get_reduce_max_buffer() {\n return reinterpret_cast<float*>(reduction_scratchpad_ptr +\n reduce_max_buffer_offset_);\n }\n\n float* get_reduce_sum_buffer() {\n return reinterpret_cast<float*>(reduction_scratchpad_ptr +\n reduce_sum_buffer_offset_);\n }\n\n int64_t get_thread_scratchpad_size() const {\n return 2 * sum_buffer_offset_ - max_buffer_offset_;\n }\n\n int64_t get_reduction_scratchpad_size() const {\n return 2 * reduce_sum_buffer_offset_ - reduce_max_buffer_offset_;\n }\n\n private:\n static int64_t round_to_64(const int64_t num) {\n return ((num + 63) >> 6) << 6;\n }\n\n static int64_t calcu_q_buffer_size(const int64_t q_tile_size,\n const int64_t head_dim,\n const int64_t elem_size) {\n return round_to_64(q_tile_size * head_dim * elem_size);\n }\n\n static int64_t calcu_logits_buffer_size(const int64_t max_num_q_per_iter,\n const int64_t k_tile_size,\n const int64_t elem_size) {\n return round_to_64(elem_size * max_num_q_per_iter * k_tile_size);\n }\n\n static int64_t calcu_partial_output_buffer_size(const int64_t q_tile_size,\n const int64_t head_dim,\n const int64_t elem_size) {\n return round_to_64(q_tile_size * head_dim * elem_size);\n }\n\n static int64_t calcu_partial_output_max_sum_buffer_size(\n const int64_t q_tile_size) {\n return round_to_64(q_tile_size * sizeof(float));\n }\n\n static int64_t calcu_reduce_flag_buffer_size(const int64_t total_split_num) {\n return round_to_64(total_split_num * sizeof(bool));\n }\n\n static int64_t calcu_reduce_max_sum_buffer_size(\n const int64_t total_split_num, const int32_t q_head_tile_size) {\n return round_to_64(total_split_num * q_head_tile_size * sizeof(float));\n }\n\n static int64_t calcu_reduce_output_buffer_size(\n const int64_t total_split_num, const int64_t q_head_tile_size,\n const int64_t head_dim, const int64_t output_buffer_elem_size) {\n return round_to_64(total_split_num * q_head_tile_size * head_dim *\n output_buffer_elem_size);\n }\n\n private:\n int8_t* thread_scratchpad_ptr;\n int8_t* reduction_scratchpad_ptr;\n int64_t reduction_scratchpad_size_per_kv_head;\n // attention buffers\n int64_t q_buffer_offset_;\n int64_t logits_buffer_offset_;\n int64_t output_buffer_offset_;\n int64_t max_buffer_offset_;\n int64_t sum_buffer_offset_;\n // reduction buffers\n int64_t reduce_flag_buffer_offset_;\n int64_t reduce_output_buffer_offset_;\n int64_t reduce_max_buffer_offset_;\n int64_t reduce_sum_buffer_offset_;\n};\n\nclass AttentionScheduler {\n public:\n struct ScheduleInput {\n int32_t num_reqs;\n int32_t elem_size;\n int32_t q_buffer_elem_size;\n int32_t logits_buffer_elem_size;\n int32_t output_buffer_elem_size;\n int32_t num_heads_q;\n int32_t num_heads_kv;\n int32_t head_dim;\n int32_t* query_start_loc;\n int32_t* seq_lens;\n int32_t left_sliding_window_size;\n int32_t right_sliding_window_size;\n bool casual;\n cpu_attention::ISA isa;\n int32_t max_num_q_per_iter; // max Q head num can be hold in registers\n int32_t kv_block_alignment; // context length alignment requirement\n bool enable_kv_split;\n };\n\n static constexpr int32_t MaxQTileIterNum = 128;\n\n AttentionScheduler() : available_cache_size_(get_available_l2_size()) {}\n\n torch::Tensor schedule(const ScheduleInput& input) const {\n const bool casual = input.casual;\n const int32_t thread_num = omp_get_max_threads();\n const int64_t cache_size = get_available_l2_size();\n const int32_t max_num_q_per_iter = input.max_num_q_per_iter;\n const int32_t kv_len_alignment = input.kv_block_alignment;\n int32_t q_head_per_kv = input.num_heads_q / input.num_heads_kv;\n const bool use_gqa = (max_num_q_per_iter % q_head_per_kv == 0);\n if (!use_gqa) {\n q_head_per_kv = 1; // fallback to MHA\n }\n const int32_t min_split_kv_len =\n ((max_num_q_per_iter * 4 + kv_len_alignment - 1) / kv_len_alignment) *\n kv_len_alignment;\n const int32_t max_num_q_token_per_iter = max_num_q_per_iter / q_head_per_kv;\n const int64_t default_tile_size = calcu_default_tile_size(\n cache_size, input.head_dim, input.elem_size, input.q_buffer_elem_size,\n input.logits_buffer_elem_size, input.output_buffer_elem_size,\n max_num_q_per_iter, max_num_q_per_iter);\n const int32_t default_tile_token_num = default_tile_size / q_head_per_kv;\n const int32_t split_kv_q_token_num_threshold =\n input.enable_kv_split ? 1 : 0;\n const int32_t left_sliding_window_size = input.left_sliding_window_size;\n const int32_t right_sliding_window_size = input.right_sliding_window_size;\n TORCH_CHECK_LE(split_kv_q_token_num_threshold * q_head_per_kv, 16);\n\n // get total kv len\n int64_t total_kv_len = 0;\n for (int32_t req_id = 0; req_id < input.num_reqs; ++req_id) {\n const int32_t seq_len = input.seq_lens[req_id];\n const int32_t q_token_num =\n input.query_start_loc[req_id + 1] - input.query_start_loc[req_id];\n const int32_t q_start_pos = (casual ? (seq_len - q_token_num) : 0);\n const int32_t kv_start_pos = 0;\n const int32_t kv_end_pos = seq_len;\n\n for (int32_t token_id = 0; token_id < q_token_num;\n token_id += max_num_q_token_per_iter) {\n const int32_t q_tile_token_num =\n std::min(max_num_q_token_per_iter, q_token_num - token_id);\n const int32_t q_tile_pos_left = q_start_pos + token_id;\n const int32_t q_tile_pos_right = q_tile_pos_left + q_tile_token_num;\n const auto [kv_tile_pos_left, kv_tile_pos_right] = calcu_kv_tile_pos(\n kv_start_pos, kv_end_pos, q_tile_pos_left, q_tile_pos_right,\n left_sliding_window_size, right_sliding_window_size);\n const auto [aligned_kv_tile_pos_left, aligned_kv_tile_pos_right] =\n align_kv_tile_pos(kv_tile_pos_left, kv_tile_pos_right,\n kv_len_alignment);\n\n int32_t curr_kv_len =\n aligned_kv_tile_pos_right - aligned_kv_tile_pos_left;\n total_kv_len += curr_kv_len;\n }\n }\n const int64_t kv_len_per_thread =\n (((total_kv_len / thread_num) + kv_len_alignment - 1) /\n kv_len_alignment) *\n kv_len_alignment * (use_gqa ? input.num_heads_kv : input.num_heads_q);\n std::vector<AttentionWorkItemGroup> workitems;\n std::vector<ReductionWorkItemGroup> reduce_workitems;\n workitems.reserve(1024);\n reduce_workitems.reserve(1024);\n std::vector<int32_t> workitem_num_per_thread(thread_num, 0);\n\n // split tasks\n int32_t curr_thread_id = 0;\n int64_t remaining_kv_len = kv_len_per_thread;\n int32_t cum_split_num = 0;\n for (int32_t req_id = 0; req_id < input.num_reqs; ++req_id) {\n const int32_t seq_len = input.seq_lens[req_id];\n const int32_t q_token_num =\n input.query_start_loc[req_id + 1] - input.query_start_loc[req_id];\n const int32_t q_start_pos = (casual ? (seq_len - q_token_num) : 0);\n const int32_t kv_start_pos = 0;\n const int32_t kv_end_pos = seq_len;\n int32_t local_split_id = 0;\n\n AttentionWorkItemGroup curr_workitem(req_id, 0, 0, seq_len);\n for (int32_t token_id = 0; token_id < q_token_num;\n token_id += max_num_q_token_per_iter) {\n const int32_t q_tile_token_num =\n std::min(max_num_q_token_per_iter, q_token_num - token_id);\n const int32_t q_tile_pos_left = q_start_pos + token_id;\n const int32_t q_tile_pos_right = q_tile_pos_left + q_tile_token_num;\n const auto [kv_tile_pos_left, kv_tile_pos_right] = calcu_kv_tile_pos(\n kv_start_pos, kv_end_pos, q_tile_pos_left, q_tile_pos_right,\n left_sliding_window_size, right_sliding_window_size);\n const auto [aligned_kv_tile_pos_left, aligned_kv_tile_pos_right] =\n align_kv_tile_pos(kv_tile_pos_left, kv_tile_pos_right,\n kv_len_alignment);\n int32_t curr_kv_len =\n aligned_kv_tile_pos_right - aligned_kv_tile_pos_left;\n int32_t kv_token_pos_start = aligned_kv_tile_pos_left;\n\n while (curr_kv_len > 0) {\n if (curr_kv_len <= (remaining_kv_len + min_split_kv_len) ||\n curr_thread_id == (thread_num - 1)) {\n curr_workitem.q_token_num += q_tile_token_num;\n curr_workitem.total_kv_len += curr_kv_len;\n remaining_kv_len -= curr_kv_len;\n curr_kv_len = 0;\n\n if (remaining_kv_len < 0) {\n // stop to accept more workitems\n remaining_kv_len -= min_split_kv_len;\n }\n\n if (curr_workitem.kv_split_pos_start != 0) {\n // got a partial kv spilt, need to create a single workitem\n curr_workitem.split_id = cum_split_num;\n curr_workitem.local_split_id = local_split_id;\n workitems.emplace_back(curr_workitem);\n ++workitem_num_per_thread[curr_thread_id];\n ++reduce_workitems.back().split_num;\n ++cum_split_num;\n\n curr_workitem = AttentionWorkItemGroup(\n req_id, token_id + max_num_q_token_per_iter, 0, seq_len);\n }\n\n break;\n }\n\n if (remaining_kv_len < min_split_kv_len &&\n (curr_workitem.total_kv_len > 0 ||\n workitem_num_per_thread[curr_thread_id] > 0)) {\n // remaining_kv_len is too short, and have allocated workitems, just\n // leave to next thread\n if (curr_workitem.total_kv_len > 0) {\n workitems.emplace_back(curr_workitem);\n ++workitem_num_per_thread[curr_thread_id];\n curr_workitem =\n AttentionWorkItemGroup(req_id, token_id, 0, seq_len);\n }\n\n // switch to next thread\n ++curr_thread_id;\n remaining_kv_len = kv_len_per_thread;\n\n // retry this iteration\n continue;\n }\n\n // only split tail splits with q_tile_token_num <=\n // split_kv_q_token_num_threshold\n if (token_id + max_num_q_token_per_iter < q_token_num ||\n q_tile_token_num > split_kv_q_token_num_threshold) {\n // if requires a new q tile iteration and already has workitems,\n // leave this workitem to next thread\n if (curr_workitem.q_token_num % default_tile_token_num == 0 &&\n (curr_workitem.total_kv_len > 0 ||\n workitem_num_per_thread[curr_thread_id] > 0)) {\n if (curr_workitem.total_kv_len > 0) {\n workitems.emplace_back(curr_workitem);\n ++workitem_num_per_thread[curr_thread_id];\n }\n curr_workitem =\n AttentionWorkItemGroup(req_id, token_id, 0, seq_len);\n\n // switch to next thread\n ++curr_thread_id;\n remaining_kv_len = kv_len_per_thread;\n }\n\n curr_workitem.q_token_num += q_tile_token_num;\n curr_workitem.total_kv_len += curr_kv_len;\n remaining_kv_len -= curr_kv_len;\n curr_kv_len = 0;\n break;\n }\n\n // split kv\n if (curr_workitem.total_kv_len > 0) {\n // write back curr workitem\n workitems.emplace_back(curr_workitem);\n ++workitem_num_per_thread[curr_thread_id];\n }\n\n if (kv_token_pos_start == aligned_kv_tile_pos_left) {\n // first split, init the workitem\n reduce_workitems.emplace_back(ReductionWorkItemGroup(\n req_id, token_id, q_tile_token_num, cum_split_num));\n }\n\n int32_t spilt_size =\n std::min(std::max(remaining_kv_len, (int64_t)min_split_kv_len),\n (int64_t)curr_kv_len);\n curr_workitem =\n AttentionWorkItemGroup(req_id, token_id, kv_token_pos_start,\n kv_token_pos_start + spilt_size);\n curr_workitem.q_token_num += q_tile_token_num;\n curr_workitem.total_kv_len += spilt_size;\n curr_workitem.split_id = cum_split_num;\n curr_workitem.local_split_id = local_split_id;\n workitems.emplace_back(curr_workitem);\n ++workitem_num_per_thread[curr_thread_id];\n ++reduce_workitems.back().split_num;\n ++cum_split_num;\n ++local_split_id;\n\n kv_token_pos_start += spilt_size;\n curr_kv_len -= spilt_size;\n curr_workitem = AttentionWorkItemGroup(req_id, token_id,\n kv_token_pos_start, seq_len);\n\n // switch to next thread\n ++curr_thread_id;\n remaining_kv_len = kv_len_per_thread;\n }\n }\n\n if (curr_workitem.total_kv_len > 0) {\n // write back curr workitem\n workitems.emplace_back(curr_workitem);\n ++workitem_num_per_thread[curr_thread_id];\n }\n }\n\n int64_t metadata_tensor_size =\n sizeof(AttentionMetadata) +\n workitems.size() * sizeof(AttentionWorkItemGroup) +\n reduce_workitems.size() * sizeof(ReductionWorkItemGroup);\n auto options =\n torch::TensorOptions().dtype(torch::kInt8).device(torch::kCPU);\n torch::Tensor metadata_tensor =\n torch::empty({metadata_tensor_size}, options);\n AttentionMetadata* metadata_ptr = new (metadata_tensor.data_ptr())\n AttentionMetadata(input.isa, workitems.size(), reduce_workitems.size(),\n cum_split_num, split_kv_q_token_num_threshold);\n AttentionWorkItemGroup* workitem_groups_ptr =\n metadata_ptr->workitem_groups_ptr;\n ReductionWorkItemGroup* reduction_items_ptr =\n metadata_ptr->reduction_items_ptr;\n std::memcpy(workitem_groups_ptr, workitems.data(),\n workitems.size() * sizeof(AttentionWorkItemGroup));\n std::memcpy(reduction_items_ptr, reduce_workitems.data(),\n reduce_workitems.size() * sizeof(ReductionWorkItemGroup));\n\n int32_t effective_thread_num = 0;\n for (; effective_thread_num < thread_num; ++effective_thread_num) {\n if (workitem_num_per_thread[effective_thread_num] == 0) {\n break;\n }\n }\n\n std::memcpy(metadata_ptr->cu_workitem_num_per_thread + 1,\n workitem_num_per_thread.data(),\n workitem_num_per_thread.size() * sizeof(int32_t));\n for (int32_t i = 1; i <= thread_num; ++i) {\n metadata_ptr->cu_workitem_num_per_thread[i] +=\n metadata_ptr->cu_workitem_num_per_thread[i - 1];\n }\n metadata_ptr->effective_thread_num = effective_thread_num;\n\n {\n // when q_tile_size = max_num_q_per_iter, requires max\n // attention_scratchpad_size\n AttentionScratchPad sc(0, *metadata_ptr, 0x0);\n int64_t n = AttentionScheduler::calcu_tile_size_with_constant_q(\n cache_size, input.head_dim, input.elem_size, input.q_buffer_elem_size,\n input.logits_buffer_elem_size, input.output_buffer_elem_size,\n max_num_q_per_iter, kv_len_alignment, max_num_q_per_iter, true);\n sc.update(input.head_dim, input.q_buffer_elem_size,\n input.logits_buffer_elem_size, input.output_buffer_elem_size,\n max_num_q_per_iter, max_num_q_per_iter, n);\n metadata_ptr->attention_scratchpad_size_per_thread =\n ((sc.get_thread_scratchpad_size() + 63) / 64) * 64;\n\n sc.update(0, metadata_ptr->reduction_split_num, input.head_dim,\n q_head_per_kv * split_kv_q_token_num_threshold,\n input.output_buffer_elem_size);\n metadata_ptr->reduction_scratchpad_size_per_kv_head =\n ((sc.get_reduction_scratchpad_size() + 63) / 64) * 64;\n }\n int64_t scratchpad_size =\n metadata_ptr->attention_scratchpad_size_per_thread *\n metadata_ptr->thread_num +\n metadata_ptr->reduction_scratchpad_size_per_kv_head *\n (use_gqa ? input.num_heads_kv : input.num_heads_q);\n DNNLScratchPadManager::get_dnnl_scratchpad_manager()->realloc(\n scratchpad_size);\n\n // metadata_ptr->print();\n\n // test out of boundary access\n // {\n // float* cache_ptr =\n // DNNLScratchPadManager::get_dnnl_scratchpad_manager()->get_data<float>();\n // for (int64_t i = 0; i < scratchpad_size / sizeof(float); ++i) {\n // cache_ptr[i] = std::numeric_limits<float>::quiet_NaN();\n // }\n // }\n\n return metadata_tensor;\n }\n\n FORCE_INLINE static std::pair<int32_t, int32_t> calcu_kv_tile_pos(\n int32_t kv_left_pos, int32_t kv_right_pos, int32_t q_left_pos,\n int32_t q_right_pos, int32_t sliding_window_left,\n int32_t sliding_window_right) {\n if (sliding_window_left != -1) {\n kv_left_pos = std::max(kv_left_pos, q_left_pos - sliding_window_left);\n }\n if (sliding_window_right != -1) {\n kv_right_pos = std::min(kv_right_pos, q_right_pos + sliding_window_right);\n }\n return {kv_left_pos, kv_right_pos};\n }\n\n FORCE_INLINE static std::pair<int32_t, int32_t> align_kv_tile_pos(\n int32_t kv_left_pos, int32_t kv_right_pos, int32_t align_factor) {\n kv_left_pos = (kv_left_pos / align_factor) * align_factor;\n kv_right_pos =\n ((kv_right_pos + align_factor - 1) / align_factor) * align_factor;\n return {kv_left_pos, kv_right_pos};\n }\n\n static int64_t calcu_default_tile_size(int64_t cache_size, int64_t head_dim,\n int64_t elem_size,\n int64_t q_buffer_elem_size,\n int64_t logits_buffer_elem_size,\n int64_t output_buffer_elem_size,\n int64_t max_num_q_per_iter,\n int64_t round_size) {\n // For CPU, different from CUDA, Q@K^T results should also be hold in cache,\n // using float32. Intermediate outputs should be float32 to be compatible\n // with AMX Then the cache includes:\n // - Q: q_tile_size * head_dim * q_buffer_elem_size\n // - K, V: 2 * k_tile_size * head_dim * elem_size\n // - Q@K^T: max_num_q_per_iter * k_tile_size * logits_buffer_elem_size\n // - Intermediate outputs: q_tile_size * head_dim * output_buffer_elem_size\n // By default, let tile_size = q_tile_size = k_tile_size. To record\n // is_first_iter states in a static array, require the default tile <= 128 *\n // max_num_q_per_iter\n\n int64_t tile_size =\n cache_size / (head_dim * (q_buffer_elem_size + 2 * elem_size +\n output_buffer_elem_size) +\n max_num_q_per_iter * logits_buffer_elem_size);\n tile_size = std::min(tile_size, MaxQTileIterNum * max_num_q_per_iter);\n int64_t rounded_tile_size = (tile_size / round_size) * round_size;\n return std::max(rounded_tile_size, round_size);\n }\n\n static int64_t calcu_tile_size_with_constant_q(\n int64_t cache_size, int64_t head_dim, int64_t elem_size,\n int64_t q_buffer_elem_size, int64_t logits_buffer_elem_size,\n int64_t output_buffer_elem_size, int64_t max_num_q_per_iter,\n int64_t round_size, int64_t q_tile_size, bool one_round) {\n // calculate tile_size with known q_tile_size\n // If one_round is True, the outer Q tile loop time is 1, then the K,V will\n // not be included in the cache\n int64_t tile_size;\n if (one_round) {\n tile_size =\n (cache_size - q_tile_size * head_dim *\n (q_buffer_elem_size + output_buffer_elem_size)) /\n (logits_buffer_elem_size * max_num_q_per_iter);\n } else {\n tile_size =\n (cache_size - q_tile_size * head_dim *\n (q_buffer_elem_size + output_buffer_elem_size)) /\n (logits_buffer_elem_size * max_num_q_per_iter +\n 2 * head_dim * elem_size);\n }\n int64_t rounded_tile_size = (tile_size / round_size) * round_size;\n return std::max(rounded_tile_size, round_size);\n }\n\n static int64_t get_available_l2_size() {\n static int64_t size = []() {\n#if defined(__APPLE__)\n // macOS doesn't have _SC_LEVEL2_CACHE_SIZE. Use sysctlbyname.\n int64_t l2_cache_size = 0;\n size_t len = sizeof(l2_cache_size);\n if (sysctlbyname(\"hw.l2cachesize\", &l2_cache_size, &len, NULL, 0) == 0 &&\n l2_cache_size > 0) {\n return l2_cache_size >> 1; // use 50% of L2 cache\n }\n // Fallback if sysctlbyname fails\n return 128LL * 1024 >> 1; // use 50% of 128KB\n#else\n long l2_cache_size = sysconf(_SC_LEVEL2_CACHE_SIZE);\n TORCH_CHECK_NE(l2_cache_size, -1);\n return l2_cache_size >> 1; // use 50% of L2 cache\n#endif\n }();\n return size;\n }\n\n private:\n int64_t available_cache_size_;\n};\n\nstruct AttentionInput {\n AttentionMetadata* metadata;\n int32_t num_tokens;\n int32_t num_heads;\n int32_t num_kv_heads;\n int32_t block_size;\n void* query;\n int64_t query_num_tokens_stride;\n int64_t query_num_heads_stride;\n int64_t cache_num_blocks_stride;\n int64_t cache_num_kv_heads_stride;\n int64_t blt_num_tokens_stride;\n void* key_cache;\n void* value_cache;\n void* output;\n int32_t* query_start_loc;\n int32_t* seq_lens;\n int32_t* block_table;\n float* alibi_slopes;\n c10::BFloat16* s_aux;\n float scale;\n bool causal;\n int32_t sliding_window_left;\n int32_t sliding_window_right;\n float softcap;\n};\n\n#define DEFINE_CPU_ATTENTION_PARAMS \\\n q_buffer_t *__restrict__ q_heads_buffer, \\\n kv_cache_t *__restrict__ k_head_cache_ptr, \\\n kv_cache_t *__restrict__ v_head_cache_ptr, \\\n logits_buffer_t *__restrict__ logits_buffer, \\\n float *__restrict__ partial_q_buffer, float *__restrict__ max_buffer, \\\n float *__restrict__ sum_buffer, int32_t *__restrict__ block_table, \\\n const int32_t kv_tile_start_pos, const int32_t kv_tile_end_pos, \\\n const int32_t kv_tile_token_num, \\\n const int64_t kv_cache_num_blocks_stride, const int32_t q_head_num, \\\n const int32_t q_token_num, const int32_t q_tile_start_pos, \\\n const int32_t q_heads_per_kv, const int32_t block_size, \\\n const int32_t left_window_size, const int32_t right_window_size, \\\n float scale, const float softcap_scale, \\\n const float *__restrict__ alibi_slopes, const bool is_first_iter, \\\n const bool use_sink, const bool debug_info\n\n#define CPU_ATTENTION_PARAMS \\\n q_heads_buffer, k_head_cache_ptr, v_head_cache_ptr, logits_buffer, \\\n partial_q_buffer, max_buffer, sum_buffer, block_table, \\\n kv_tile_start_pos, kv_tile_end_pos, kv_tile_token_num, \\\n kv_cache_num_blocks_stride, q_head_num, q_token_num, q_tile_start_pos, \\\n q_heads_per_kv, block_size, left_window_size, right_window_size, scale, \\\n softcap_scale, alibi_slopes, is_first_iter, use_sink, debug_info\n\nenum class AttentionGemmPhase { QK, PV };\n\ntemplate <typename T>\nstruct VecTypeTrait {\n using vec_t = void;\n};\n\ntemplate <>\nstruct VecTypeTrait<float> {\n using vec_t = vec_op::FP32Vec16;\n};\n\n// ARM only supports BF16 with ARMv8.6-A extension\n#if (defined(__aarch64__) && !defined(ARM_BF16_SUPPORT))\n#else\ntemplate <>\nstruct VecTypeTrait<c10::BFloat16> {\n using vec_t = vec_op::BF16Vec16;\n};\n#endif\n\n#if !defined(__powerpc__) && !defined(__s390x__)\ntemplate <>\nstruct VecTypeTrait<c10::Half> {\n using vec_t = vec_op::FP16Vec16;\n};\n#endif\n\ntemplate <typename T>\nvoid print_logits(const char* name, T* ptr, int32_t row, int32_t col,\n int32_t stride) {\n std::stringstream ss;\n ss << std::fixed << std::setprecision(5) << name << \": [\\n\";\n auto* curr_logits_buffer = ptr;\n for (int32_t m = 0; m < row; ++m) {\n for (int32_t n = 0; n < col; ++n) {\n ss << curr_logits_buffer[n] << \", \";\n }\n ss << \"\\n\";\n curr_logits_buffer += stride;\n }\n ss << \"]\\n\";\n std::printf(\"%s\", ss.str().c_str());\n}\n\ntemplate <typename attention_impl_t>\nclass AttentionMainLoop {\n public:\n using query_t = typename attention_impl_t::query_t;\n using q_buffer_t = typename attention_impl_t::q_buffer_t;\n using kv_cache_t = typename attention_impl_t::kv_cache_t;\n using logits_buffer_t = typename attention_impl_t::logits_buffer_t;\n using partial_output_buffer_t =\n typename attention_impl_t::partial_output_buffer_t;\n using prob_buffer_t = typename attention_impl_t::prob_buffer_t;\n\n static constexpr int64_t max_q_head_num_per_iter =\n attention_impl_t::MaxQHeadNumPerIteration;\n static constexpr int64_t blocksize_alignment =\n attention_impl_t::BlockSizeAlignment;\n static constexpr int64_t headdim_alignment =\n attention_impl_t::HeadDimAlignment;\n static constexpr int64_t head_dim = attention_impl_t::HeadDim;\n static constexpr ISA ISAType = attention_impl_t::ISAType;\n static constexpr bool scale_on_logits =\n attention_impl_t::scale_on_logits; // apply scale on logits, otherwise\n // apply scale on q_buffer\n\n template <typename tile_gemm_t>\n class Attention {\n public:\n // Args:\n // - q_heads_buffer: [MaxQHeadNumPerIteration, head_dim]\n // - k_head_cache_ptr: [num_blocks, block_size * head_dim]\n // - v_head_cache_ptr: [num_blocks, block_size * head_dim]\n // - logits_buffer: [MaxQHeadNumPerIteration, kv_tile_token_num], store Q@K\n // - logits partial_q_buffer: [MaxQHeadNumPerIteration, head_dim], store\n // partial output\n // - max_buffer: [MaxQHeadNumPerIteration, 1], store max logits\n // - sum_buffer: [MaxQHeadNumPerIteration, 1], store sum of exp\n // - block_table\n // - kv_tile_start_pos: start position of KV cache, aligned to\n // BlockSizeAlignment\n // - kv_tile_end_pos: end position of KV cache, aligned to\n // BlockSizeAlignment\n // - kv_tile_token_num: KV token num, aligned to BlockSizeAlignment\n // - kv_cache_num_blocks_stride\n // - q_head_num: head num of q_tile\n // - q_token_num: token num of q_tile, should be q_head_num /\n // q_heads_per_kv\n // - q_tile_start_pos: start pos of the first token in q_heads_buffer\n // - q_heads_per_kv\n // - block_size\n // - left_window_size\n // - right_window_size\n // - scale\n // - softcap_scale\n // - alibi_slopes\n // - is_first_iter\n // - use_sink\n // - debug_info\n void operator()(DEFINE_CPU_ATTENTION_PARAMS) {\n // k_cache_token_group_stride: stride of K cache when move to next\n // BlockSizeAlignment tokens in a block\n const int64_t k_cache_token_group_stride =\n attention_impl_t::k_cache_token_group_stride(block_size);\n // v_cache_token_group_stride: stride of V cache when move to next\n // BlockSizeAlignment tokens in a block\n const int64_t v_cache_token_group_stride =\n attention_impl_t::v_cache_token_group_stride(block_size);\n // v_cache_head_group_stride: stride of V cache when move to next\n // HeadDimAlignment head dims in a block\n const int64_t v_cache_head_group_stride =\n attention_impl_t::v_cache_head_group_stride(block_size);\n const int32_t token_group_num = kv_tile_token_num / blocksize_alignment;\n const int32_t token_group_num_per_block =\n block_size / blocksize_alignment;\n const int32_t start_block_idx = kv_tile_start_pos / block_size;\n const int32_t start_block_offset = kv_tile_start_pos % block_size;\n const int32_t start_block_group_offset =\n start_block_offset / blocksize_alignment;\n const int32_t end_block_idx =\n (kv_tile_start_pos + kv_tile_token_num - 1) / block_size + 1;\n\n // compute Q@K logits\n {\n int32_t curr_group_offset =\n start_block_group_offset * k_cache_token_group_stride;\n int32_t curr_group_num_in_block =\n token_group_num_per_block - start_block_group_offset;\n int32_t remaining_group_num = token_group_num;\n logits_buffer_t* curr_logits_buffer = logits_buffer;\n for (int32_t block_idx = start_block_idx; block_idx < end_block_idx;\n ++block_idx) {\n int32_t physical_block_idx = block_table[block_idx];\n kv_cache_t* k_cache_block_ptr =\n k_head_cache_ptr +\n physical_block_idx * kv_cache_num_blocks_stride +\n curr_group_offset;\n curr_group_num_in_block =\n std::min(remaining_group_num, curr_group_num_in_block);\n\n for (int32_t block_group_idx = 0;\n block_group_idx < curr_group_num_in_block; ++block_group_idx) {\n // logits_tile = q_tile @ k_tile, [MaxQHeadNumPerIteration,\n // BlockSizeAlignment] = [MaxQHeadNumPerIteration, head_dim] @\n // [head_dim, BlockSizeAlignment]\n\n // By default, logits_buffer, q_buffer and k_cache are row-major,\n // but may be packed by ISA implementation.\n tile_gemm_t::template gemm<AttentionGemmPhase::QK, head_dim>(\n q_head_num, q_heads_buffer, k_cache_block_ptr,\n curr_logits_buffer, head_dim, block_size, kv_tile_token_num,\n block_size, head_dim, false);\n\n if constexpr (scale_on_logits) {\n float* __restrict__ scale_curr_logits_buffer = curr_logits_buffer;\n vec_op::FP32Vec16 scale_vec(scale);\n for (int32_t i = 0; i < q_head_num; ++i) {\n static_assert(blocksize_alignment % 16 == 0);\n constexpr int32_t vec_num = blocksize_alignment / 16;\n vec_op::unroll_loop<int32_t, vec_num>([&](int32_t vec_idx) {\n vec_op::FP32Vec16 vec(scale_curr_logits_buffer +\n vec_idx * 16);\n vec = vec * scale_vec;\n vec.save(scale_curr_logits_buffer + vec_idx * 16);\n });\n scale_curr_logits_buffer += kv_tile_token_num;\n }\n }\n\n // Move buffer ptrs\n k_cache_block_ptr += k_cache_token_group_stride;\n curr_logits_buffer += blocksize_alignment;\n }\n\n // Update\n remaining_group_num -= curr_group_num_in_block;\n curr_group_offset = 0;\n curr_group_num_in_block = token_group_num_per_block;\n }\n }\n\n // process logits\n {\n // if (debug_info){\n // print_logits(\"raw logits\", logits_buffer, q_head_num,\n // kv_tile_token_num, kv_tile_token_num);\n // }\n\n if (softcap_scale != 0.0f) {\n apply_softcap(logits_buffer, kv_tile_token_num, q_head_num,\n kv_tile_token_num, softcap_scale);\n // print_logits(\"softcap raw logits\", logits_buffer, q_head_num,\n // kv_tile_token_num, kv_tile_token_num);\n }\n\n if (alibi_slopes != nullptr) {\n apply_alibi_slopes(logits_buffer, alibi_slopes, kv_tile_token_num,\n q_tile_start_pos, kv_tile_start_pos, q_token_num,\n kv_tile_token_num, q_heads_per_kv);\n\n // print_logits(\"alibi raw logits\", logits_buffer, q_head_num,\n // kv_tile_token_num, kv_tile_token_num);\n }\n\n apply_mask(logits_buffer, kv_tile_token_num, q_tile_start_pos,\n kv_tile_start_pos, kv_tile_end_pos, q_token_num,\n q_heads_per_kv, left_window_size, right_window_size);\n\n // if (debug_info){\n // print_logits(\"masked logits\", logits_buffer, q_head_num,\n // kv_tile_token_num, kv_tile_token_num);\n // print_logits(\"old_max\", max_buffer, 1, q_head_num, q_head_num);\n // print_logits(\"old_sum\", sum_buffer, 1, q_head_num, q_head_num);\n // }\n\n apply_softmax(logits_buffer, partial_q_buffer, max_buffer, sum_buffer,\n kv_tile_token_num, q_head_num, kv_tile_token_num,\n is_first_iter, use_sink);\n\n // if (debug_info){\n // print_logits(\"softmax logits\",\n // reinterpret_cast<prob_buffer_t*>(logits_buffer), q_head_num,\n // kv_tile_token_num, kv_tile_token_num * sizeof(logits_buffer_t) /\n // sizeof(prob_buffer_t));\n // print_logits(\"new_max\", max_buffer, 1, q_head_num, q_head_num);\n // print_logits(\"new_sum\", sum_buffer, 1, q_head_num, q_head_num);\n // }\n }\n\n // compute P@V\n {\n int32_t curr_group_offset =\n start_block_group_offset * v_cache_token_group_stride;\n int32_t curr_group_num_in_block =\n token_group_num_per_block - start_block_group_offset;\n int32_t remaining_group_num = token_group_num;\n int32_t head_dim_group_num = head_dim / headdim_alignment;\n prob_buffer_t* curr_prob_buffer =\n reinterpret_cast<prob_buffer_t*>(logits_buffer);\n int64_t prob_buffer_stride =\n kv_tile_token_num *\n (sizeof(logits_buffer_t) / sizeof(prob_buffer_t));\n partial_output_buffer_t* curr_partial_q_buffer = partial_q_buffer;\n bool accum_c = !is_first_iter;\n for (int32_t block_idx = start_block_idx; block_idx < end_block_idx;\n ++block_idx) {\n int32_t physical_block_idx = block_table[block_idx];\n kv_cache_t* v_cache_block_ptr =\n v_head_cache_ptr +\n physical_block_idx * kv_cache_num_blocks_stride +\n curr_group_offset;\n curr_group_num_in_block =\n std::min(remaining_group_num, curr_group_num_in_block);\n int32_t curr_token_num =\n curr_group_num_in_block * blocksize_alignment;\n\n for (int32_t head_dim_group_idx = 0;\n head_dim_group_idx < head_dim_group_num; ++head_dim_group_idx) {\n // output_tile = p_tile @ v_tile, [MaxQHeadNumPerIteration,\n // HeadDimAlignment] = [MaxQHeadNumPerIteration, block_size] @\n // [block_size, HeadDimAlignment]\n tile_gemm_t::template gemm<AttentionGemmPhase::PV, -1>(\n q_head_num, curr_prob_buffer, v_cache_block_ptr,\n curr_partial_q_buffer, prob_buffer_stride, head_dim, head_dim,\n block_size, curr_token_num, accum_c);\n\n // Update\n curr_partial_q_buffer += headdim_alignment;\n v_cache_block_ptr += v_cache_head_group_stride;\n }\n\n // Update\n remaining_group_num -= curr_group_num_in_block;\n curr_group_offset = 0;\n curr_group_num_in_block = token_group_num_per_block;\n curr_prob_buffer += curr_token_num;\n curr_partial_q_buffer = partial_q_buffer;\n accum_c = true;\n }\n }\n // if (debug_info) {\n // print_logits(\"output\", partial_q_buffer, q_head_num, head_dim,\n // head_dim);\n // }\n }\n\n void apply_mask(logits_buffer_t* __restrict__ logits_buffer,\n const int64_t logits_buffer_stride,\n const int32_t q_tile_start_pos,\n const int32_t kv_tile_start_pos,\n const int32_t kv_tile_end_pos, const int32_t q_token_num,\n const int32_t q_heads_per_kv,\n const int32_t sliding_window_left,\n const int32_t sliding_window_right) {\n // Apply mask\n constexpr logits_buffer_t neg_inf =\n -std::numeric_limits<logits_buffer_t>::infinity();\n logits_buffer_t* __restrict__ curr_logits_buffer = logits_buffer;\n int32_t curr_token_pos = q_tile_start_pos;\n for (int32_t token_idx = 0; token_idx < q_token_num; ++token_idx) {\n int32_t left_kv_pos = [&]() {\n int32_t pos = kv_tile_start_pos;\n if (sliding_window_left != -1) {\n pos = std::max(pos, curr_token_pos - sliding_window_left);\n }\n return pos;\n }();\n\n int32_t right_kv_pos = [&]() {\n int32_t pos = kv_tile_end_pos;\n if (sliding_window_right != -1) {\n pos = std::min(pos,\n std::max(kv_tile_start_pos,\n curr_token_pos + sliding_window_right + 1));\n }\n return pos;\n }();\n\n int32_t left_invalid_token_num = left_kv_pos - kv_tile_start_pos;\n int32_t right_invalid_token_num = kv_tile_end_pos - right_kv_pos;\n for (int32_t head_idx = 0; head_idx < q_heads_per_kv; ++head_idx) {\n logits_buffer_t* __restrict__ curr_logits_buffer_tail =\n curr_logits_buffer + right_kv_pos - kv_tile_start_pos;\n for (int32_t i = 0; i < left_invalid_token_num; ++i) {\n curr_logits_buffer[i] = neg_inf;\n }\n for (int32_t i = 0; i < right_invalid_token_num; ++i) {\n curr_logits_buffer_tail[i] = neg_inf;\n }\n\n curr_logits_buffer += logits_buffer_stride;\n }\n\n ++curr_token_pos;\n }\n }\n\n void apply_softmax(logits_buffer_t* __restrict__ logits_buffer,\n float* __restrict__ partial_q_buffer,\n float* __restrict__ max_buffer,\n float* __restrict__ sum_buffer,\n const int64_t logits_buffer_stride, int32_t q_head_num,\n int32_t kv_tile_token_num, bool is_first_iter,\n bool use_sink) {\n#ifdef DEFINE_FAST_EXP\n DEFINE_FAST_EXP\n#endif\n using prob_buffer_vec_t = typename VecTypeTrait<prob_buffer_t>::vec_t;\n static_assert(sizeof(prob_buffer_t) <= sizeof(logits_buffer_t));\n\n logits_buffer_t* __restrict__ curr_logits_buffer = logits_buffer;\n float* __restrict__ curr_partial_q_buffer = partial_q_buffer;\n const int32_t vec_num = kv_tile_token_num / 16;\n const int32_t head_vec_num = head_dim / 16;\n for (int32_t i = 0; i < q_head_num; ++i) {\n float init_max_val = max_buffer[i];\n float init_sum_val = sum_buffer[i];\n\n // apply scale and compute max\n vec_op::FP32Vec16 max_vec(init_max_val);\n {\n logits_buffer_t* __restrict__ curr_logits_buffer_iter =\n curr_logits_buffer;\n for (int32_t j = 0; j < vec_num; ++j) {\n vec_op::FP32Vec16 vec(curr_logits_buffer_iter);\n max_vec = vec.max(max_vec);\n\n curr_logits_buffer_iter += 16;\n }\n }\n float new_max_val = max_vec.reduce_max();\n float rescale_factor = init_max_val - new_max_val;\n\n // use same rescale threshold with FA4.\n // https://github.com/Dao-AILab/flash-attention/blob/1b8e1e641c6a179be9a0538b7f40fd595050b735/flash_attn/cute/flash_fwd_sm100.py#L1271\n bool need_rescale = rescale_factor < -8.0;\n if (!need_rescale) {\n new_max_val = init_max_val;\n } else {\n max_buffer[i] = new_max_val;\n }\n\n // sub max, compute exp and sum\n max_vec = vec_op::FP32Vec16(new_max_val);\n vec_op::FP32Vec16 sum_vec(0.0);\n {\n logits_buffer_t* __restrict__ curr_logits_buffer_iter =\n curr_logits_buffer;\n prob_buffer_t* __restrict__ curr_prob_buffer_iter =\n reinterpret_cast<prob_buffer_t*>(curr_logits_buffer);\n for (int32_t j = 0; j < vec_num; ++j) {\n vec_op::FP32Vec16 vec(curr_logits_buffer_iter);\n vec = vec - max_vec;\n\n // compute exp\n#ifdef DEFINE_FAST_EXP\n vec = fast_exp(vec);\n prob_buffer_vec_t output_vec(vec);\n output_vec.save(curr_prob_buffer_iter);\n#else\n vec.save(curr_logits_buffer_iter);\n for (int32_t k = 0; k < 16; ++k) {\n curr_logits_buffer_iter[k] = std::exp(curr_logits_buffer_iter[k]);\n }\n vec = vec_op::FP32Vec16(curr_logits_buffer_iter);\n#endif\n\n sum_vec = sum_vec + vec;\n\n curr_logits_buffer_iter += 16;\n curr_prob_buffer_iter += 16;\n }\n }\n float new_sum_val = sum_vec.reduce_sum();\n\n // rescale sum and partial outputs\n if (need_rescale) {\n // compute rescale factor\n#ifdef DEFINE_FAST_EXP\n vec_op::FP32Vec16 rescale_factor_vec(rescale_factor);\n rescale_factor_vec = fast_exp(rescale_factor_vec);\n rescale_factor = rescale_factor_vec.get_last_elem();\n#else\n rescale_factor = std::exp(rescale_factor);\n vec_op::FP32Vec16 rescale_factor_vec(rescale_factor);\n#endif\n\n // rescale sum\n new_sum_val += rescale_factor * init_sum_val;\n\n // rescale output\n if (!is_first_iter) {\n float* __restrict__ curr_partial_q_buffer_iter =\n curr_partial_q_buffer;\n for (int32_t j = 0; j < head_vec_num; ++j) {\n vec_op::FP32Vec16 vec(curr_partial_q_buffer_iter);\n vec = vec * rescale_factor_vec;\n vec.save(curr_partial_q_buffer_iter);\n\n curr_partial_q_buffer_iter += 16;\n }\n }\n } else {\n new_sum_val += init_sum_val;\n }\n\n sum_buffer[i] = new_sum_val;\n\n curr_logits_buffer += logits_buffer_stride;\n curr_partial_q_buffer += head_dim;\n }\n }\n\n void apply_softcap(logits_buffer_t* __restrict__ logits_buffer,\n const int64_t logits_buffer_stride, int32_t q_head_num,\n int32_t kv_tile_token_num, float softcap_scale) {\n#ifdef DEFINE_FAST_EXP\n DEFINE_FAST_EXP\n#endif\n float inv_softcap_scale = 1.0 / softcap_scale;\n vec_op::FP32Vec16 softcap_scale_vec(softcap_scale);\n vec_op::FP32Vec16 inv_softcap_scale_vec(inv_softcap_scale);\n vec_op::FP32Vec16 ones_vec(1.0);\n logits_buffer_t* __restrict__ curr_logits_buffer = logits_buffer;\n const int32_t vec_num = kv_tile_token_num / 16;\n for (int32_t i = 0; i < q_head_num; ++i) {\n logits_buffer_t* __restrict__ curr_logits_buffer_iter =\n curr_logits_buffer;\n for (int32_t j = 0; j < vec_num; ++j) {\n vec_op::FP32Vec16 vec(curr_logits_buffer_iter);\n vec = vec * inv_softcap_scale_vec;\n\n#ifdef DEFINE_FAST_EXP\n vec = fast_exp(vec);\n vec_op::FP32Vec16 inv_vec = ones_vec / vec;\n vec = (vec - inv_vec) / (vec + inv_vec);\n#else\n vec.save(curr_logits_buffer_iter);\n for (int k = 0; k < 16; ++k) {\n curr_logits_buffer_iter[k] = std::tanh(curr_logits_buffer_iter[k]);\n }\n vec = vec_op::FP32Vec16(curr_logits_buffer_iter);\n#endif\n vec = vec * softcap_scale_vec;\n vec.save(curr_logits_buffer_iter);\n\n curr_logits_buffer_iter += 16;\n }\n\n curr_logits_buffer += logits_buffer_stride;\n }\n }\n\n void apply_alibi_slopes(logits_buffer_t* __restrict__ logits_buffer,\n const float* __restrict__ alibi_slopes,\n const int64_t logits_buffer_stride,\n const int32_t q_tile_start_pos,\n const int32_t kv_tile_start_pos,\n const int32_t q_token_num,\n const int32_t kv_tile_token_num,\n const int32_t q_heads_per_kv) {\n alignas(64) constexpr float initial_arange_vals[16] = {\n 0.0f, 1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 6.0f, 7.0f,\n 8.0f, 9.0f, 10.0f, 11.0f, 12.0f, 13.0f, 14.0f, 15.0f};\n const int32_t vec_num = kv_tile_token_num / 16;\n\n vec_op::FP32Vec16 initial_arange_vals_vec(initial_arange_vals);\n initial_arange_vals_vec =\n initial_arange_vals_vec + vec_op::FP32Vec16((float)kv_tile_start_pos);\n vec_op::FP32Vec16 pos_offset_vec(16.0);\n logits_buffer_t* __restrict__ curr_logits_buffer = logits_buffer;\n for (int32_t i = 0; i < q_token_num; ++i) {\n vec_op::FP32Vec16 curr_q_pos_vec((float)(i + q_tile_start_pos));\n for (int32_t j = 0; j < q_heads_per_kv; ++j) {\n vec_op::FP32Vec16 alibi_scale_vec(alibi_slopes[j]);\n vec_op::FP32Vec16 curr_kv_pos_vec(initial_arange_vals_vec);\n logits_buffer_t* __restrict__ curr_logits_buffer_iter =\n curr_logits_buffer;\n for (int32_t k = 0; k < vec_num; ++k) {\n vec_op::FP32Vec16 alibi_bias_vec =\n alibi_scale_vec * (curr_kv_pos_vec - curr_q_pos_vec);\n vec_op::FP32Vec16 vec(curr_logits_buffer_iter);\n vec = vec + alibi_bias_vec;\n\n vec.save(curr_logits_buffer_iter);\n\n curr_kv_pos_vec = curr_kv_pos_vec + pos_offset_vec;\n curr_logits_buffer_iter += 16;\n }\n curr_logits_buffer += logits_buffer_stride;\n }\n }\n }\n };\n\n public:\n void operator()(const AttentionInput* input) {\n const int thread_num = omp_get_max_threads();\n TORCH_CHECK_EQ(input->metadata->thread_num, thread_num);\n std::atomic<int32_t> guard_counter(0);\n std::atomic<int32_t>* guard_counter_ptr = &guard_counter;\n\n#pragma omp parallel for schedule(static, 1)\n for (int thread_id = 0; thread_id < thread_num; ++thread_id) {\n AttentionMetadata& metadata = *input->metadata;\n if (metadata.workitem_group_num == 0) {\n continue;\n }\n\n attention_impl_t attn_impl;\n\n // general information\n const int32_t q_head_num = input->num_heads;\n const int32_t kv_head_num = input->num_kv_heads;\n const int32_t q_heads_per_kv = q_head_num / kv_head_num;\n const bool use_gqa =\n (max_q_head_num_per_iter % q_heads_per_kv == 0) ? true : false;\n const int32_t actual_kv_head_num = use_gqa ? kv_head_num : q_head_num;\n const int32_t actual_q_heads_per_kv = use_gqa ? q_heads_per_kv : 1;\n TORCH_CHECK_LE(actual_q_heads_per_kv, max_q_head_num_per_iter);\n const int32_t max_q_token_num_per_iter =\n max_q_head_num_per_iter / actual_q_heads_per_kv;\n const int64_t q_token_num_stride = input->query_num_tokens_stride;\n const int64_t q_head_num_stride = input->query_num_heads_stride;\n const int64_t kv_cache_head_num_stride = input->cache_num_kv_heads_stride;\n const int64_t kv_cache_block_num_stride = input->cache_num_blocks_stride;\n const int32_t sliding_window_left = input->sliding_window_left;\n const int32_t sliding_window_right = input->sliding_window_right;\n const int32_t block_size = input->block_size;\n const float scale = input->scale;\n const float softcap_scale = input->softcap;\n const float* alibi_slopes = input->alibi_slopes;\n const c10::BFloat16* s_aux = input->s_aux;\n\n const bool casual = input->causal;\n int32_t* const block_table = input->block_table;\n const int64_t block_table_stride = input->blt_num_tokens_stride;\n\n // init buffers\n void* scratchpad_ptr =\n DNNLScratchPadManager::get_dnnl_scratchpad_manager()\n ->get_data<void>();\n AttentionScratchPad buffer_manager(thread_id, metadata, scratchpad_ptr);\n\n const int32_t total_reduction_split_num = metadata.reduction_split_num;\n if (metadata.reduction_split_num > 0) {\n // reset split flag\n for (int32_t head_idx = thread_id; head_idx < actual_kv_head_num;\n head_idx += thread_num) {\n buffer_manager.update(head_idx, total_reduction_split_num, head_dim,\n 0, sizeof(partial_output_buffer_t));\n volatile bool* __restrict__ curr_flag_ptr =\n buffer_manager.get_reduce_flag_buffer();\n for (int32_t split_idx = 0; split_idx < total_reduction_split_num;\n ++split_idx) {\n curr_flag_ptr[split_idx] = false;\n }\n }\n }\n\n const int64_t available_cache_size =\n AttentionScheduler::get_available_l2_size();\n const int32_t default_tile_size =\n AttentionScheduler::calcu_default_tile_size(\n available_cache_size, head_dim, sizeof(kv_cache_t),\n sizeof(q_buffer_t), sizeof(logits_buffer_t),\n sizeof(partial_output_buffer_t), max_q_head_num_per_iter,\n max_q_head_num_per_iter);\n const int32_t default_q_tile_token_num =\n default_tile_size / actual_q_heads_per_kv;\n\n AttentionWorkItemGroup* const workitem_groups =\n metadata.workitem_groups_ptr;\n const int32_t* cu_workitem_num_per_thread =\n metadata.cu_workitem_num_per_thread;\n ReductionWorkItemGroup* const reduction_items =\n metadata.reduction_items_ptr;\n\n const int32_t effective_thread_num = metadata.effective_thread_num;\n const int32_t reduction_item_num = metadata.reduction_item_num;\n const int32_t split_kv_q_token_num_threshold =\n metadata.split_kv_q_token_num_threshold;\n const int32_t workitem_groups_counter_num =\n actual_kv_head_num * effective_thread_num;\n const int32_t reduction_items_counter_num =\n actual_kv_head_num * reduction_item_num;\n const int32_t total_counter_num =\n workitem_groups_counter_num + reduction_items_counter_num;\n\n if (metadata.reduction_split_num > 0) {\n ++(*guard_counter_ptr);\n while (guard_counter_ptr->load() != thread_num) {\n#ifdef FAST_SPINNING\n FAST_SPINNING\n#else\n std::this_thread::yield();\n#endif\n }\n }\n\n // main loop\n for (;;) {\n int64_t task_idx = metadata.acquire_counter();\n\n if (task_idx >= total_counter_num) {\n // no more tasks, leave loop\n break;\n }\n\n if (task_idx < workitem_groups_counter_num) {\n // attention task\n // map task_idx to workitem_groups\n const int32_t kv_head_idx = task_idx / effective_thread_num;\n const int32_t thread_offset = task_idx % effective_thread_num;\n AttentionWorkItemGroup* const curr_workitem_groups =\n workitem_groups + cu_workitem_num_per_thread[thread_offset];\n const int32_t curr_workitem_groups_num =\n cu_workitem_num_per_thread[thread_offset + 1] -\n cu_workitem_num_per_thread[thread_offset];\n\n const int32_t q_head_start_idx = kv_head_idx * actual_q_heads_per_kv;\n\n for (int32_t workitem_group_idx = 0;\n workitem_group_idx < curr_workitem_groups_num;\n ++workitem_group_idx) {\n AttentionWorkItemGroup* const current_workitem_group =\n &curr_workitem_groups[workitem_group_idx];\n\n const int32_t current_group_idx = current_workitem_group->req_id;\n const int32_t kv_start_pos =\n current_workitem_group->kv_split_pos_start;\n const int32_t kv_end_pos = current_workitem_group->kv_split_pos_end;\n const int32_t curr_spilt_id = current_workitem_group->split_id;\n const int32_t q_token_id_start =\n current_workitem_group->q_token_id_start;\n const int32_t q_token_num = current_workitem_group->q_token_num;\n\n // taskgroup general information\n const int32_t q_end = input->query_start_loc[current_group_idx + 1];\n const int32_t q_start = input->query_start_loc[current_group_idx];\n const int32_t seq_len = input->seq_lens[current_group_idx];\n const int32_t q_start_pos =\n (casual ? seq_len - (q_end - q_start) : 0);\n const int32_t block_num = (seq_len + block_size - 1) / block_size;\n // Only apply sink for the first KV split\n bool use_sink = (s_aux != nullptr &&\n current_workitem_group->local_split_id == 0);\n\n for (int32_t q_token_offset = 0; q_token_offset < q_token_num;\n q_token_offset += default_q_tile_token_num) {\n bool first_iter_flag[AttentionScheduler::MaxQTileIterNum];\n for (int32_t i = 0; i < AttentionScheduler::MaxQTileIterNum;\n ++i) {\n first_iter_flag[i] = true;\n }\n\n const int32_t q_token_start_idx =\n q_start + q_token_offset + q_token_id_start;\n const int32_t actual_q_token_num = std::min(\n default_q_tile_token_num, q_token_num - q_token_offset);\n const int32_t q_head_tile_size =\n actual_q_token_num * actual_q_heads_per_kv;\n const int32_t rounded_q_head_tile_size =\n ((q_head_tile_size + max_q_head_num_per_iter - 1) /\n max_q_head_num_per_iter) *\n max_q_head_num_per_iter;\n const int32_t kv_tile_size =\n AttentionScheduler::calcu_tile_size_with_constant_q(\n available_cache_size, head_dim, sizeof(kv_cache_t),\n sizeof(q_buffer_t), sizeof(logits_buffer_t),\n sizeof(partial_output_buffer_t), max_q_head_num_per_iter,\n blocksize_alignment, rounded_q_head_tile_size,\n rounded_q_head_tile_size <= max_q_head_num_per_iter);\n\n // update buffers\n buffer_manager.update(\n head_dim, sizeof(q_buffer_t), sizeof(logits_buffer_t),\n sizeof(partial_output_buffer_t), max_q_head_num_per_iter,\n rounded_q_head_tile_size, kv_tile_size);\n q_buffer_t* q_buffer = buffer_manager.get_q_buffer<q_buffer_t>();\n float* logits_buffer = buffer_manager.get_logits_buffer();\n float* partial_q_buffer = buffer_manager.get_output_buffer();\n float* max_buffer = buffer_manager.get_max_buffer();\n float* sum_buffer = buffer_manager.get_sum_buffer();\n\n const int32_t q_tile_start_pos =\n q_start_pos + q_token_offset + q_token_id_start;\n const int32_t q_tile_end_pos =\n q_tile_start_pos + actual_q_token_num;\n const auto [kv_tile_start_pos, kv_tile_end_pos] =\n AttentionScheduler::calcu_kv_tile_pos(\n kv_start_pos, kv_end_pos, q_tile_start_pos,\n q_tile_end_pos, sliding_window_left,\n sliding_window_right);\n const auto [rounded_kv_tile_start_pos, rounded_kv_tile_end_pos] =\n AttentionScheduler::align_kv_tile_pos(\n kv_tile_start_pos, kv_tile_end_pos, blocksize_alignment);\n\n int32_t curr_kv_head_idx =\n use_gqa ? kv_head_idx\n : (kv_head_idx /\n q_heads_per_kv); // for GQA disabled case\n\n // std::printf(\"thread_id: %d, req_id: %d, q_token_start: %d,\n // q_token_end: %d, q_head_start: %d, q_head_end: %d, kv_head_idx:\n // %d, kv_pos_start: %d, kv_pos_end: %d\\n\",\n // thread_id, current_group_idx,\n // q_token_start_idx, q_token_start_idx +\n // actual_q_token_num, q_head_start_idx,\n // q_head_start_idx + actual_q_heads_per_kv,\n // curr_kv_head_idx, kv_tile_start_pos,\n // kv_tile_end_pos);\n\n // move buffers\n kv_cache_t* curr_k_cache =\n reinterpret_cast<kv_cache_t*>(input->key_cache) +\n curr_kv_head_idx * kv_cache_head_num_stride;\n kv_cache_t* curr_v_cache =\n reinterpret_cast<kv_cache_t*>(input->value_cache) +\n curr_kv_head_idx * kv_cache_head_num_stride;\n query_t* const q_tile_ptr =\n reinterpret_cast<query_t*>(input->query) +\n q_token_start_idx * q_token_num_stride +\n q_head_start_idx * q_head_num_stride;\n size_t output_buffer_offset =\n q_token_start_idx * q_head_num * head_dim +\n q_head_start_idx * head_dim;\n int32_t* curr_block_table =\n block_table + current_group_idx * block_table_stride;\n const float* curr_alibi_slopes =\n (alibi_slopes != nullptr ? alibi_slopes + q_head_start_idx\n : nullptr);\n const c10::BFloat16* curr_s_aux =\n (s_aux != nullptr ? s_aux + q_head_start_idx : nullptr);\n\n // copy the Q tile to q_buffer, the logical layout of q_buffer is\n // [actual_q_token_num, actual_q_heads_per_kv, head_dim]\n {\n attn_impl.copy_q_heads_tile(\n q_tile_ptr, q_buffer, actual_q_token_num,\n actual_q_heads_per_kv, q_token_num_stride,\n q_head_num_stride, scale);\n }\n\n if (use_sink) {\n alignas(64) float s_aux_fp32[16];\n#if defined(__aarch64__) && !defined(ARM_BF16_SUPPORT)\n // ARM without native BF16 support: manual conversion\n for (int i = 0; i < 16; ++i) {\n s_aux_fp32[i] = static_cast<float>(curr_s_aux[i]);\n }\n#else\n // All other platforms have BF16Vec16 available\n vec_op::BF16Vec16 vec_bf16(curr_s_aux);\n vec_op::FP32Vec16 vec_fp32(vec_bf16);\n vec_fp32.save(s_aux_fp32);\n#endif\n\n float* __restrict__ curr_sum_buffer = sum_buffer;\n float* __restrict__ curr_max_buffer = max_buffer;\n for (int32_t token_idx = 0; token_idx < actual_q_token_num;\n ++token_idx) {\n for (int32_t head_idx = 0; head_idx < actual_q_heads_per_kv;\n ++head_idx) {\n curr_sum_buffer[head_idx] = 1.0f;\n curr_max_buffer[head_idx] = s_aux_fp32[head_idx];\n }\n\n curr_sum_buffer += actual_q_heads_per_kv;\n curr_max_buffer += actual_q_heads_per_kv;\n }\n } else {\n float* __restrict__ curr_sum_buffer = sum_buffer;\n float* __restrict__ curr_max_buffer = max_buffer;\n for (int32_t token_idx = 0; token_idx < actual_q_token_num;\n ++token_idx) {\n for (int32_t head_idx = 0; head_idx < actual_q_heads_per_kv;\n ++head_idx) {\n curr_sum_buffer[head_idx] = 0.0f;\n curr_max_buffer[head_idx] =\n std::numeric_limits<float>::lowest();\n }\n\n curr_sum_buffer += actual_q_heads_per_kv;\n curr_max_buffer += actual_q_heads_per_kv;\n }\n }\n\n // compute loop\n for (int32_t kv_tile_pos = rounded_kv_tile_start_pos;\n kv_tile_pos < rounded_kv_tile_end_pos;\n kv_tile_pos += kv_tile_size) {\n const int32_t kv_tile_pos_left = kv_tile_pos;\n const int32_t kv_tile_pos_right = std::min(\n kv_tile_pos_left + kv_tile_size, rounded_kv_tile_end_pos);\n for (int32_t q_head_tile_token_offset = 0;\n q_head_tile_token_offset < actual_q_token_num;\n q_head_tile_token_offset += max_q_token_num_per_iter) {\n const int32_t q_tile_pos_left =\n q_tile_start_pos + q_head_tile_token_offset;\n const int32_t q_tile_token_num =\n std::min(max_q_token_num_per_iter,\n actual_q_token_num - q_head_tile_token_offset);\n const int32_t q_tile_head_offset =\n q_head_tile_token_offset * actual_q_heads_per_kv;\n const int32_t q_tile_head_num =\n q_tile_token_num * actual_q_heads_per_kv;\n const int32_t q_tile_pos_right =\n q_tile_pos_left + q_tile_token_num;\n const auto [actual_kv_tile_pos_left,\n actual_kv_tile_pos_right] =\n AttentionScheduler::calcu_kv_tile_pos(\n kv_tile_pos_left, kv_tile_pos_right, q_tile_pos_left,\n q_tile_pos_right, sliding_window_left,\n sliding_window_right);\n const int32_t q_iter_idx =\n q_head_tile_token_offset / max_q_token_num_per_iter;\n\n if (actual_kv_tile_pos_right <= actual_kv_tile_pos_left) {\n continue;\n }\n\n // align kv_pos to blocksize_alignment\n const auto [aligned_actual_kv_tile_pos_left,\n aligned_actual_kv_tile_pos_right] =\n AttentionScheduler::align_kv_tile_pos(\n actual_kv_tile_pos_left, actual_kv_tile_pos_right,\n blocksize_alignment);\n const int32_t actual_kv_token_num =\n aligned_actual_kv_tile_pos_right -\n aligned_actual_kv_tile_pos_left;\n\n // std::printf(\"\\tq_iter_idx: %d, q_token_start: %d,\n // q_token_end: %d, q_token_num: %d, q_head_num: %d,\n // q_pos_start: %d, q_pos_end: %d, kv_pos_start: %d,\n // kv_pos_end: %d\\n\",\n // q_iter_idx, q_token_start_idx +\n // q_head_tile_token_offset, q_token_start_idx +\n // q_head_tile_token_offset + q_tile_token_num,\n // q_tile_token_num, q_tile_head_num,\n // q_tile_pos_left, q_tile_pos_right,\n // aligned_actual_kv_tile_pos_left,\n // aligned_actual_kv_tile_pos_right);\n\n // Move buffers\n q_buffer_t* curr_q_heads_buffer =\n q_buffer + q_tile_head_offset * head_dim;\n float* curr_partial_q_buffer =\n partial_q_buffer + q_tile_head_offset * head_dim;\n float* curr_max_buffer = max_buffer + q_tile_head_offset;\n float* curr_sum_buffer = sum_buffer + q_tile_head_offset;\n\n bool debug_info = false;\n // bool debug_info = (\n // q_head_start_idx == 4 &&\n // (q_token_start_idx + q_head_tile_token_offset) <=\n // 4\n // && (q_token_start_idx + q_head_tile_token_offset +\n // q_tile_token_num) > 4\n // );\n // if (debug_info) {\n // std::printf(\"\\tq_iter_idx: %d, q_token_start: %d,\"\n // \"q_token_end: %d, q_token_num: %d, q_head_num: %d,\"\n // \"q_pos_start: %d, q_pos_end: %d, kv_pos_start: %d,\"\n // \"kv_pos_end: %d\\n\",\n // q_iter_idx, q_token_start_idx +\n // q_head_tile_token_offset, q_token_start_idx\n // + q_head_tile_token_offset +\n // q_tile_token_num, q_tile_token_num,\n // q_tile_head_num, q_tile_pos_left,\n // q_tile_pos_right,\n // aligned_actual_kv_tile_pos_left,\n // aligned_actual_kv_tile_pos_right);\n // }\n\n attn_impl.template execute_attention<Attention>(\n curr_q_heads_buffer, curr_k_cache, curr_v_cache,\n logits_buffer, curr_partial_q_buffer, curr_max_buffer,\n curr_sum_buffer, curr_block_table,\n aligned_actual_kv_tile_pos_left,\n aligned_actual_kv_tile_pos_right, actual_kv_token_num,\n kv_cache_block_num_stride, q_tile_head_num,\n q_tile_token_num, q_tile_pos_left, actual_q_heads_per_kv,\n block_size, sliding_window_left, sliding_window_right,\n scale, softcap_scale, curr_alibi_slopes,\n first_iter_flag[q_iter_idx], use_sink, debug_info);\n first_iter_flag[q_iter_idx] = false;\n }\n }\n\n // write back partial results to output buffer or reduction buffer\n {\n if (curr_spilt_id == -1) {\n final_output(partial_q_buffer,\n reinterpret_cast<query_t*>(input->output) +\n output_buffer_offset,\n sum_buffer, actual_q_heads_per_kv,\n actual_q_token_num, q_head_num);\n } else {\n const int32_t stride =\n actual_q_heads_per_kv * split_kv_q_token_num_threshold;\n buffer_manager.update(kv_head_idx, total_reduction_split_num,\n head_dim, stride, sizeof(float));\n volatile bool* split_flag_buffer =\n buffer_manager.get_reduce_flag_buffer() + curr_spilt_id;\n float* split_output_buffer =\n buffer_manager.get_reduce_output_buffer() +\n curr_spilt_id * stride * head_dim;\n float* split_max_buffer =\n buffer_manager.get_reduce_max_buffer() +\n curr_spilt_id * stride;\n float* split_sum_buffer =\n buffer_manager.get_reduce_sum_buffer() +\n curr_spilt_id * stride;\n\n partial_output(partial_q_buffer, max_buffer, sum_buffer,\n q_head_tile_size, split_output_buffer,\n split_max_buffer, split_sum_buffer,\n split_flag_buffer);\n }\n }\n }\n }\n } else {\n task_idx -= workitem_groups_counter_num;\n const int32_t kv_head_idx = task_idx / reduction_item_num;\n const int32_t item_offset = task_idx % reduction_item_num;\n ReductionWorkItemGroup* const curr_workitem_groups =\n reduction_items + item_offset;\n const int32_t curr_output_token_idx =\n curr_workitem_groups->q_token_id_start;\n const int32_t curr_output_token_num =\n curr_workitem_groups->q_token_id_num;\n const int32_t curr_split_id = curr_workitem_groups->split_start_id;\n const int32_t curr_split_num = curr_workitem_groups->split_num;\n const int32_t current_group_idx = curr_workitem_groups->req_id;\n const int32_t curr_output_head_num =\n curr_output_token_num * actual_q_heads_per_kv;\n\n const int32_t q_start = input->query_start_loc[current_group_idx];\n const int32_t q_token_start_idx = q_start + curr_output_token_idx;\n const int32_t q_head_start_idx = kv_head_idx * actual_q_heads_per_kv;\n size_t output_buffer_offset =\n q_token_start_idx * q_head_num * head_dim +\n q_head_start_idx * head_dim;\n\n const int32_t stride =\n actual_q_heads_per_kv * split_kv_q_token_num_threshold;\n buffer_manager.update(kv_head_idx, total_reduction_split_num,\n head_dim, stride, sizeof(float));\n volatile bool* split_flag_buffer =\n buffer_manager.get_reduce_flag_buffer() + curr_split_id;\n float* split_output_buffer =\n buffer_manager.get_reduce_output_buffer() +\n curr_split_id * stride * head_dim;\n float* split_max_buffer =\n buffer_manager.get_reduce_max_buffer() + curr_split_id * stride;\n float* split_sum_buffer =\n buffer_manager.get_reduce_sum_buffer() + curr_split_id * stride;\n\n reduce_splits(split_output_buffer, split_max_buffer, split_sum_buffer,\n split_flag_buffer, stride, curr_output_head_num,\n curr_split_num);\n final_output(\n split_output_buffer,\n reinterpret_cast<query_t*>(input->output) + output_buffer_offset,\n split_sum_buffer, actual_q_heads_per_kv, curr_output_token_num,\n q_head_num);\n }\n }\n }\n // Reset counter for next call\n input->metadata->reset_counter();\n }\n\n void reduce_splits(float* __restrict__ split_output_buffer,\n float* __restrict__ split_max_buffer,\n float* __restrict__ split_sum_buffer,\n volatile bool* __restrict__ flags,\n const int32_t head_num_per_split,\n const int32_t curr_head_num, const int32_t split_num) {\n#ifdef DEFINE_FAST_EXP\n DEFINE_FAST_EXP\n#endif\n // restrict curr_head_num <= 16 in the scheduler\n // elems in split_max_buffer, split_sum_buffer are not cache alignment, use\n // local buffers to reduce false-sharing\n alignas(64) float local_max[16];\n alignas(64) float local_sum[16];\n\n float* __restrict__ curr_split_output_buffer = split_output_buffer;\n float* __restrict__ curr_split_max_buffer = split_max_buffer;\n float* __restrict__ curr_split_sum_buffer = split_sum_buffer;\n constexpr int32_t head_dim_group_num = head_dim / 16;\n for (int32_t split_idx = 0; split_idx < split_num; ++split_idx) {\n while (!flags[split_idx]) {\n#ifdef FAST_SPINNING\n FAST_SPINNING\n#else\n std::this_thread::yield();\n#endif\n }\n std::atomic_thread_fence(std::memory_order_acquire);\n\n if (split_idx > 0) {\n float* __restrict__ curr_output_buffer = split_output_buffer;\n float* __restrict__ curr_split_output_buffer_iter =\n curr_split_output_buffer;\n for (int32_t head_idx = 0; head_idx < curr_head_num; ++head_idx) {\n float final_max = local_max[head_idx];\n float curr_max = curr_split_max_buffer[head_idx];\n float final_sum = local_sum[head_idx];\n float curr_sum = curr_split_sum_buffer[head_idx];\n float* __restrict__ non_scale_output_iter =\n final_max > curr_max ? curr_output_buffer\n : curr_split_output_buffer_iter;\n float* __restrict__ scale_output_iter =\n final_max > curr_max ? curr_split_output_buffer_iter\n : curr_output_buffer;\n float rescale_factor = final_max > curr_max ? curr_max - final_max\n : final_max - curr_max;\n\n#ifdef DEFINE_FAST_EXP\n vec_op::FP32Vec16 rescale_factor_vec(rescale_factor);\n rescale_factor_vec = fast_exp(rescale_factor_vec);\n rescale_factor = rescale_factor_vec.get_last_elem();\n#else\n rescale_factor = std::exp(rescale_factor);\n vec_op::FP32Vec16 rescale_factor_vec(rescale_factor);\n#endif\n\n local_sum[head_idx] = final_max > curr_max\n ? final_sum + rescale_factor * curr_sum\n : rescale_factor * final_sum + curr_sum;\n\n final_max = std::max(final_max, curr_max);\n local_max[head_idx] = final_max;\n for (int32_t i = 0; i < head_dim_group_num; ++i) {\n vec_op::FP32Vec16 non_scale_vec(non_scale_output_iter);\n vec_op::FP32Vec16 scale_vec(scale_output_iter);\n vec_op::FP32Vec16 final_vec =\n non_scale_vec + scale_vec * rescale_factor_vec;\n final_vec.save(curr_output_buffer);\n\n non_scale_output_iter += 16;\n scale_output_iter += 16;\n curr_output_buffer += 16;\n }\n curr_split_output_buffer_iter += head_dim;\n }\n } else {\n vec_op::FP32Vec16 final_max(split_max_buffer);\n final_max.save(local_max);\n vec_op::FP32Vec16 final_sum(split_sum_buffer);\n final_sum.save(local_sum);\n }\n\n curr_split_output_buffer += head_num_per_split * head_dim;\n curr_split_max_buffer += head_num_per_split;\n curr_split_sum_buffer += head_num_per_split;\n }\n // write back final max and sum\n for (int32_t i = 0; i < curr_head_num; ++i) {\n split_max_buffer[i] = local_max[i];\n split_sum_buffer[i] = local_sum[i];\n }\n }\n\n void partial_output(float* __restrict__ partial_output_buffer,\n float* __restrict__ partial_max_buffer,\n float* __restrict__ partial_sum_buffer,\n int32_t curr_head_num,\n float* __restrict__ split_output_buffer,\n float* __restrict__ split_max_buffer,\n float* __restrict__ split_sum_buffer,\n volatile bool* __restrict__ flag) {\n float* __restrict__ curr_partial_output_buffer = partial_output_buffer;\n float* __restrict__ curr_split_output_buffer = split_output_buffer;\n constexpr int32_t head_dim_group_num = head_dim / 16;\n for (int32_t i = 0; i < curr_head_num; ++i) {\n split_max_buffer[i] = partial_max_buffer[i];\n split_sum_buffer[i] = partial_sum_buffer[i];\n for (int32_t j = 0; j < head_dim_group_num; ++j) {\n vec_op::FP32Vec16 vec(curr_partial_output_buffer);\n vec.save(curr_split_output_buffer);\n\n curr_partial_output_buffer += 16;\n curr_split_output_buffer += 16;\n }\n }\n std::atomic_thread_fence(std::memory_order_release);\n *flag = true;\n }\n\n void final_output(float* __restrict__ partial_q_buffer,\n query_t* __restrict__ curr_output_buffer,\n float* __restrict__ sum_buffer,\n const int32_t q_heads_per_kv,\n const int32_t actual_q_token_num,\n const int32_t q_head_num) {\n // final output\n using output_vec_t = typename VecTypeTrait<query_t>::vec_t;\n\n float* __restrict__ curr_partial_output_buffer = partial_q_buffer;\n float* __restrict__ curr_sum_buffer = sum_buffer;\n constexpr int32_t group_num_per_head = head_dim / 16;\n const int32_t partial_q_buffer_stride = q_heads_per_kv * head_dim;\n const int32_t output_buffer_stride = q_head_num * head_dim;\n for (int32_t token_idx = 0; token_idx < actual_q_token_num; ++token_idx) {\n float* __restrict__ curr_partial_output_buffer_iter =\n curr_partial_output_buffer;\n query_t* __restrict__ curr_output_buffer_iter = curr_output_buffer;\n for (int32_t head_idx = 0; head_idx < q_heads_per_kv; ++head_idx) {\n vec_op::FP32Vec16 inv_sum_scale_vec(1.0 / *curr_sum_buffer);\n\n for (int32_t i = 0; i < group_num_per_head; ++i) {\n vec_op::FP32Vec16 vec(curr_partial_output_buffer_iter);\n // divide the final sum val of softmax here\n vec = inv_sum_scale_vec * vec;\n\n // cast to query type\n output_vec_t output_vec(vec);\n output_vec.save(curr_output_buffer_iter);\n\n // update\n curr_partial_output_buffer_iter += 16;\n curr_output_buffer_iter += 16;\n }\n\n // update\n curr_sum_buffer += 1;\n }\n\n // update\n curr_partial_output_buffer += partial_q_buffer_stride;\n curr_output_buffer += output_buffer_stride;\n }\n }\n};\n\n} // namespace cpu_attention\n\n#endif\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- markdownlint-disable -->\n\n## Purpose\n\nThis accelerates paged attention by 20% on Arm Neoverse-V2 for batch size = 64, query tokens = kv tokens = 512, q heads = 32, kv heads = 8, head size = 128, block size = 128\n\n## Test Plan\n\n@fadara01 will test in CI\n\n## Test Result\n\n---\n<details>\n<summary> Essential Elements of an Effective PR Description Checklist </summary>\n\n- [Y] The purpose of the PR, such as \"Fix some issue (link existing issues this PR will resolve)\".\n- [Y] The test plan, such as providing test command.\n- [Y] The test results, such as pasting the results comparison before and after, or e2e results\n- [ ] (Optional) The necessary documentation update, such as updating `supported_models.md` and `examples` for a new model.\n- [ ] (Optional) Release notes update. If your change is user facing, please update the release notes draft in the [Google Doc](https://docs.google.com/document/d/1YyVqrgX4gHTtrstbq8oWUImOyPCKSGnJ7xtTpmXzlRs/edit?tab=t.0).\n</details>\n\n\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": \"Arm Neoverse-V2\", \"model\": null, \"shape\": \"q_heads=32,kv_heads=8,head_size=128,block_size=128\", \"batch_size\": 64, \"metric\": \"latency\", \"unit\": null, \"higher_is_better\": false, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.2, \"speedup\": 1.2}]"},"kernel_speedup":{"kind":"number","value":1.2,"string":"1.2"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":398,"cells":{"repo":{"kind":"string","value":"vllm"},"commit":{"kind":"string","value":"9843e332da56307597deb2739bb83b85c18c5dde"},"date":{"kind":"string","value":"2025-12-05T08:09:20-05:00"},"pr_number":{"kind":"number","value":30068,"string":"30,068"},"pr_url":{"kind":"string","value":"https://github.com/vllm-project/vllm/pull/30068"},"title":{"kind":"string","value":"[CPU][Perf] Add fast vectorized exp impl from Arm Optimized Routines (#30068)"},"message":{"kind":"string","value":"[CPU][Perf] Add fast vectorized exp impl from Arm Optimized Routines (#30068)\n\nSigned-off-by: Ubuntu <ubuntu@ip-10-252-30-150.eu-west-1.compute.internal>\nSigned-off-by: Elham Harirpoush <elham.harirpoush@arm.com>\nCo-authored-by: Ubuntu <ubuntu@ip-10-252-30-150.eu-west-1.compute.internal>"},"path":{"kind":"string","value":"csrc/cpu/cpu_attn_macros.h"},"language":{"kind":"string","value":"cpp"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"#ifndef CPU_ATTN_MACROS_H\n#define CPU_ATTN_MACROS_H\n\n// x86_64\n#ifdef __x86_64__\n #define FAST_SPINNING _mm_pause();\n\n #ifdef __AVX512F__\n #define DEFINE_FAST_EXP \\\n const __m512 vec_factorial_1 = _mm512_set1_ps(0.999999701f); \\\n const __m512 vec_factorial_2 = _mm512_set1_ps(0.499991506f); \\\n const __m512 vec_factorial_3 = _mm512_set1_ps(0.166676521f); \\\n const __m512 vec_factorial_4 = _mm512_set1_ps(0.0418978221f); \\\n const __m512 vec_factorial_5 = _mm512_set1_ps(0.00828929059f); \\\n const __m512 vec_exp_log2ef = \\\n _mm512_castsi512_ps(_mm512_set1_epi32(0x3fb8aa3b)); \\\n const __m512 vec_half = _mm512_set1_ps(0.5f); \\\n const __m512 vec_one = _mm512_set1_ps(1.f); \\\n const __m512 vec_zero = _mm512_set1_ps(0.f); \\\n const __m512 vec_two = _mm512_set1_ps(2.f); \\\n const __m512 vec_ln2f = \\\n _mm512_castsi512_ps(_mm512_set1_epi32(0x3f317218)); \\\n const __m512 vec_ln_flt_min = \\\n _mm512_castsi512_ps(_mm512_set1_epi32(0xc2aeac50)); \\\n const __m512 vec_ln_flt_max = \\\n _mm512_castsi512_ps(_mm512_set1_epi32(0x42b17218)); \\\n const __m512i vec_127 = _mm512_set1_epi32(0x0000007f); \\\n const int n_mantissa_bits = 23; \\\n auto fast_exp = [&](vec_op::FP32Vec16& vec) __attribute__(( \\\n always_inline)) { \\\n __m512 values = vec.reg; \\\n auto less_ln_flt_min_mask = \\\n _mm512_cmp_ps_mask(values, vec_ln_flt_min, 1 /*_CMP_LT_OS*/); \\\n auto vec_src = _mm512_min_ps(values, vec_ln_flt_max); \\\n vec_src = _mm512_max_ps(vec_src, vec_ln_flt_min); \\\n auto vec_fx = _mm512_fmadd_ps(vec_src, vec_exp_log2ef, vec_half); \\\n auto vec_fx_i = _mm512_cvt_roundps_epi32( \\\n vec_fx, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC); \\\n vec_fx = _mm512_cvtepi32_ps(vec_fx_i); \\\n auto vec_exp_poly = _mm512_fnmadd_ps(vec_fx, vec_ln2f, vec_src); \\\n auto vec_res = \\\n _mm512_fmadd_ps(vec_exp_poly, vec_factorial_5, vec_factorial_4); \\\n vec_res = _mm512_fmadd_ps(vec_exp_poly, vec_res, vec_factorial_3); \\\n vec_res = _mm512_fmadd_ps(vec_exp_poly, vec_res, vec_factorial_2); \\\n vec_res = _mm512_fmadd_ps(vec_exp_poly, vec_res, vec_factorial_1); \\\n vec_res = _mm512_fmadd_ps(vec_exp_poly, vec_res, vec_one); \\\n auto vec_exp_number = _mm512_sub_ps(vec_fx, vec_one); \\\n auto vec_exp_number_i = _mm512_cvtps_epi32(vec_exp_number); \\\n auto vec_two_pow_n_i = _mm512_add_epi32(vec_exp_number_i, vec_127); \\\n vec_two_pow_n_i = _mm512_slli_epi32(vec_two_pow_n_i, n_mantissa_bits); \\\n auto vec_two_pow_n = _mm512_castsi512_ps(vec_two_pow_n_i); \\\n vec_two_pow_n = _mm512_mask_blend_ps(less_ln_flt_min_mask, \\\n vec_two_pow_n, vec_zero); \\\n vec_res = _mm512_mul_ps(vec_res, vec_two_pow_n); \\\n vec_res = _mm512_mul_ps(vec_res, vec_two); \\\n vec_op::FP32Vec16 res(vec_res); \\\n return res; \\\n };\n #endif\n\n#endif\n\n#endif"},"after_code":{"kind":"string","value":"#ifndef CPU_ATTN_MACROS_H\n#define CPU_ATTN_MACROS_H\n\n// x86_64\n#ifdef __x86_64__\n #define FAST_SPINNING _mm_pause();\n\n #ifdef __AVX512F__\n #define DEFINE_FAST_EXP \\\n const __m512 vec_factorial_1 = _mm512_set1_ps(0.999999701f); \\\n const __m512 vec_factorial_2 = _mm512_set1_ps(0.499991506f); \\\n const __m512 vec_factorial_3 = _mm512_set1_ps(0.166676521f); \\\n const __m512 vec_factorial_4 = _mm512_set1_ps(0.0418978221f); \\\n const __m512 vec_factorial_5 = _mm512_set1_ps(0.00828929059f); \\\n const __m512 vec_exp_log2ef = \\\n _mm512_castsi512_ps(_mm512_set1_epi32(0x3fb8aa3b)); \\\n const __m512 vec_half = _mm512_set1_ps(0.5f); \\\n const __m512 vec_one = _mm512_set1_ps(1.f); \\\n const __m512 vec_zero = _mm512_set1_ps(0.f); \\\n const __m512 vec_two = _mm512_set1_ps(2.f); \\\n const __m512 vec_ln2f = \\\n _mm512_castsi512_ps(_mm512_set1_epi32(0x3f317218)); \\\n const __m512 vec_ln_flt_min = \\\n _mm512_castsi512_ps(_mm512_set1_epi32(0xc2aeac50)); \\\n const __m512 vec_ln_flt_max = \\\n _mm512_castsi512_ps(_mm512_set1_epi32(0x42b17218)); \\\n const __m512i vec_127 = _mm512_set1_epi32(0x0000007f); \\\n const int n_mantissa_bits = 23; \\\n auto fast_exp = [&](vec_op::FP32Vec16& vec) __attribute__(( \\\n always_inline)) { \\\n __m512 values = vec.reg; \\\n auto less_ln_flt_min_mask = \\\n _mm512_cmp_ps_mask(values, vec_ln_flt_min, 1 /*_CMP_LT_OS*/); \\\n auto vec_src = _mm512_min_ps(values, vec_ln_flt_max); \\\n vec_src = _mm512_max_ps(vec_src, vec_ln_flt_min); \\\n auto vec_fx = _mm512_fmadd_ps(vec_src, vec_exp_log2ef, vec_half); \\\n auto vec_fx_i = _mm512_cvt_roundps_epi32( \\\n vec_fx, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC); \\\n vec_fx = _mm512_cvtepi32_ps(vec_fx_i); \\\n auto vec_exp_poly = _mm512_fnmadd_ps(vec_fx, vec_ln2f, vec_src); \\\n auto vec_res = \\\n _mm512_fmadd_ps(vec_exp_poly, vec_factorial_5, vec_factorial_4); \\\n vec_res = _mm512_fmadd_ps(vec_exp_poly, vec_res, vec_factorial_3); \\\n vec_res = _mm512_fmadd_ps(vec_exp_poly, vec_res, vec_factorial_2); \\\n vec_res = _mm512_fmadd_ps(vec_exp_poly, vec_res, vec_factorial_1); \\\n vec_res = _mm512_fmadd_ps(vec_exp_poly, vec_res, vec_one); \\\n auto vec_exp_number = _mm512_sub_ps(vec_fx, vec_one); \\\n auto vec_exp_number_i = _mm512_cvtps_epi32(vec_exp_number); \\\n auto vec_two_pow_n_i = _mm512_add_epi32(vec_exp_number_i, vec_127); \\\n vec_two_pow_n_i = _mm512_slli_epi32(vec_two_pow_n_i, n_mantissa_bits); \\\n auto vec_two_pow_n = _mm512_castsi512_ps(vec_two_pow_n_i); \\\n vec_two_pow_n = _mm512_mask_blend_ps(less_ln_flt_min_mask, \\\n vec_two_pow_n, vec_zero); \\\n vec_res = _mm512_mul_ps(vec_res, vec_two_pow_n); \\\n vec_res = _mm512_mul_ps(vec_res, vec_two); \\\n vec_op::FP32Vec16 res(vec_res); \\\n return res; \\\n };\n #endif\n\n#endif\n\n#ifdef __aarch64__\n // Implementation copied from Arm Optimized Routines (expf AdvSIMD)\n // https://github.com/ARM-software/optimized-routines/blob/master/math/aarch64/advsimd/expf.c\n #include <limits>\n #define DEFINE_FAST_EXP \\\n const float32x4_t inv_ln2 = vdupq_n_f32(0x1.715476p+0f); \\\n const float ln2_hi = 0x1.62e4p-1f; \\\n const float ln2_lo = 0x1.7f7d1cp-20f; \\\n const float c0 = 0x1.0e4020p-7f; \\\n const float c2 = 0x1.555e66p-3f; \\\n const float32x4_t ln2_c02 = {ln2_hi, ln2_lo, c0, c2}; \\\n const uint32x4_t exponent_bias = vdupq_n_u32(0x3f800000); \\\n const float32x4_t c1 = vdupq_n_f32(0x1.573e2ep-5f); \\\n const float32x4_t c3 = vdupq_n_f32(0x1.fffdb6p-2f); \\\n const float32x4_t c4 = vdupq_n_f32(0x1.ffffecp-1f); \\\n const float32x4_t pos_special_bound = vdupq_n_f32(0x1.5d5e2ap+6f); \\\n const float32x4_t neg_special_bound = vnegq_f32(pos_special_bound); \\\n const float32x4_t inf = \\\n vdupq_n_f32(std::numeric_limits<float>::infinity()); \\\n const float32x4_t zero = vdupq_n_f32(0.0f); \\\n auto neon_expf = [&](float32x4_t values) __attribute__((always_inline)) { \\\n float32x4_t n = vrndaq_f32(vmulq_f32(values, inv_ln2)); \\\n float32x4_t r = vfmsq_laneq_f32(values, n, ln2_c02, 0); \\\n r = vfmsq_laneq_f32(r, n, ln2_c02, 1); \\\n uint32x4_t e = vshlq_n_u32(vreinterpretq_u32_s32(vcvtq_s32_f32(n)), 23); \\\n float32x4_t scale = vreinterpretq_f32_u32(vaddq_u32(e, exponent_bias)); \\\n float32x4_t r2 = vmulq_f32(r, r); \\\n float32x4_t p = vfmaq_laneq_f32(c1, r, ln2_c02, 2); \\\n float32x4_t q = vfmaq_laneq_f32(c3, r, ln2_c02, 3); \\\n q = vfmaq_f32(q, p, r2); \\\n p = vmulq_f32(c4, r); \\\n float32x4_t poly = vfmaq_f32(p, q, r2); \\\n poly = vfmaq_f32(scale, poly, scale); \\\n const uint32x4_t hi_mask = vcgeq_f32(values, pos_special_bound); \\\n const uint32x4_t lo_mask = vcleq_f32(values, neg_special_bound); \\\n poly = vbslq_f32(hi_mask, inf, poly); \\\n return vbslq_f32(lo_mask, zero, poly); \\\n }; \\\n auto fast_exp = [&](vec_op::FP32Vec16& vec) \\\n __attribute__((always_inline)) { \\\n float32x4x4_t result; \\\n result.val[0] = neon_expf(vec.reg.val[0]); \\\n result.val[1] = neon_expf(vec.reg.val[1]); \\\n result.val[2] = neon_expf(vec.reg.val[2]); \\\n result.val[3] = neon_expf(vec.reg.val[3]); \\\n return vec_op::FP32Vec16(result); \\\n };\n\n#endif // __aarch64__\n\n#endif"},"diff":{"kind":"string","value":"--- csrc/cpu/cpu_attn_macros.h\n+++ csrc/cpu/cpu_attn_macros.h\n@@ -60,4 +60,54 @@\n \n #endif\n \n+#ifdef __aarch64__\n+ // Implementation copied from Arm Optimized Routines (expf AdvSIMD)\n+ // https://github.com/ARM-software/optimized-routines/blob/master/math/aarch64/advsimd/expf.c\n+ #include <limits>\n+ #define DEFINE_FAST_EXP \\\n+ const float32x4_t inv_ln2 = vdupq_n_f32(0x1.715476p+0f); \\\n+ const float ln2_hi = 0x1.62e4p-1f; \\\n+ const float ln2_lo = 0x1.7f7d1cp-20f; \\\n+ const float c0 = 0x1.0e4020p-7f; \\\n+ const float c2 = 0x1.555e66p-3f; \\\n+ const float32x4_t ln2_c02 = {ln2_hi, ln2_lo, c0, c2}; \\\n+ const uint32x4_t exponent_bias = vdupq_n_u32(0x3f800000); \\\n+ const float32x4_t c1 = vdupq_n_f32(0x1.573e2ep-5f); \\\n+ const float32x4_t c3 = vdupq_n_f32(0x1.fffdb6p-2f); \\\n+ const float32x4_t c4 = vdupq_n_f32(0x1.ffffecp-1f); \\\n+ const float32x4_t pos_special_bound = vdupq_n_f32(0x1.5d5e2ap+6f); \\\n+ const float32x4_t neg_special_bound = vnegq_f32(pos_special_bound); \\\n+ const float32x4_t inf = \\\n+ vdupq_n_f32(std::numeric_limits<float>::infinity()); \\\n+ const float32x4_t zero = vdupq_n_f32(0.0f); \\\n+ auto neon_expf = [&](float32x4_t values) __attribute__((always_inline)) { \\\n+ float32x4_t n = vrndaq_f32(vmulq_f32(values, inv_ln2)); \\\n+ float32x4_t r = vfmsq_laneq_f32(values, n, ln2_c02, 0); \\\n+ r = vfmsq_laneq_f32(r, n, ln2_c02, 1); \\\n+ uint32x4_t e = vshlq_n_u32(vreinterpretq_u32_s32(vcvtq_s32_f32(n)), 23); \\\n+ float32x4_t scale = vreinterpretq_f32_u32(vaddq_u32(e, exponent_bias)); \\\n+ float32x4_t r2 = vmulq_f32(r, r); \\\n+ float32x4_t p = vfmaq_laneq_f32(c1, r, ln2_c02, 2); \\\n+ float32x4_t q = vfmaq_laneq_f32(c3, r, ln2_c02, 3); \\\n+ q = vfmaq_f32(q, p, r2); \\\n+ p = vmulq_f32(c4, r); \\\n+ float32x4_t poly = vfmaq_f32(p, q, r2); \\\n+ poly = vfmaq_f32(scale, poly, scale); \\\n+ const uint32x4_t hi_mask = vcgeq_f32(values, pos_special_bound); \\\n+ const uint32x4_t lo_mask = vcleq_f32(values, neg_special_bound); \\\n+ poly = vbslq_f32(hi_mask, inf, poly); \\\n+ return vbslq_f32(lo_mask, zero, poly); \\\n+ }; \\\n+ auto fast_exp = [&](vec_op::FP32Vec16& vec) \\\n+ __attribute__((always_inline)) { \\\n+ float32x4x4_t result; \\\n+ result.val[0] = neon_expf(vec.reg.val[0]); \\\n+ result.val[1] = neon_expf(vec.reg.val[1]); \\\n+ result.val[2] = neon_expf(vec.reg.val[2]); \\\n+ result.val[3] = neon_expf(vec.reg.val[3]); \\\n+ return vec_op::FP32Vec16(result); \\\n+ };\n+\n+#endif // __aarch64__\n+\n #endif"},"lines_added":{"kind":"number","value":50,"string":"50"},"lines_removed":{"kind":"number","value":0,"string":"0"},"files_in_commit":{"kind":"number","value":2,"string":"2"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["CPU"],"string":"[\n \"CPU\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cpp kernel file from vllm (csrc/cpu/cpu_attn_macros.h).\n\nGoal: [CPU][Perf] Add fast vectorized exp impl from Arm Optimized Routines\nTarget hardware: CPU\nTarget models: unspecified\n\nCurrent file:\n```cpp\n#ifndef CPU_ATTN_MACROS_H\n#define CPU_ATTN_MACROS_H\n\n// x86_64\n#ifdef __x86_64__\n #define FAST_SPINNING _mm_pause();\n\n #ifdef __AVX512F__\n #define DEFINE_FAST_EXP \\\n const __m512 vec_factorial_1 = _mm512_set1_ps(0.999999701f); \\\n const __m512 vec_factorial_2 = _mm512_set1_ps(0.499991506f); \\\n const __m512 vec_factorial_3 = _mm512_set1_ps(0.166676521f); \\\n const __m512 vec_factorial_4 = _mm512_set1_ps(0.0418978221f); \\\n const __m512 vec_factorial_5 = _mm512_set1_ps(0.00828929059f); \\\n const __m512 vec_exp_log2ef = \\\n _mm512_castsi512_ps(_mm512_set1_epi32(0x3fb8aa3b)); \\\n const __m512 vec_half = _mm512_set1_ps(0.5f); \\\n const __m512 vec_one = _mm512_set1_ps(1.f); \\\n const __m512 vec_zero = _mm512_set1_ps(0.f); \\\n const __m512 vec_two = _mm512_set1_ps(2.f); \\\n const __m512 vec_ln2f = \\\n _mm512_castsi512_ps(_mm512_set1_epi32(0x3f317218)); \\\n const __m512 vec_ln_flt_min = \\\n _mm512_castsi512_ps(_mm512_set1_epi32(0xc2aeac50)); \\\n const __m512 vec_ln_flt_max = \\\n _mm512_castsi512_ps(_mm512_set1_epi32(0x42b17218)); \\\n const __m512i vec_127 = _mm512_set1_epi32(0x0000007f); \\\n const int n_mantissa_bits = 23; \\\n auto fast_exp = [&](vec_op::FP32Vec16& vec) __attribute__(( \\\n always_inline)) { \\\n __m512 values = vec.reg; \\\n auto less_ln_flt_min_mask = \\\n _mm512_cmp_ps_mask(values, vec_ln_flt_min, 1 /*_CMP_LT_OS*/); \\\n auto vec_src = _mm512_min_ps(values, vec_ln_flt_max); \\\n vec_src = _mm512_max_ps(vec_src, vec_ln_flt_min); \\\n auto vec_fx = _mm512_fmadd_ps(vec_src, vec_exp_log2ef, vec_half); \\\n auto vec_fx_i = _mm512_cvt_roundps_epi32( \\\n vec_fx, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC); \\\n vec_fx = _mm512_cvtepi32_ps(vec_fx_i); \\\n auto vec_exp_poly = _mm512_fnmadd_ps(vec_fx, vec_ln2f, vec_src); \\\n auto vec_res = \\\n _mm512_fmadd_ps(vec_exp_poly, vec_factorial_5, vec_factorial_4); \\\n vec_res = _mm512_fmadd_ps(vec_exp_poly, vec_res, vec_factorial_3); \\\n vec_res = _mm512_fmadd_ps(vec_exp_poly, vec_res, vec_factorial_2); \\\n vec_res = _mm512_fmadd_ps(vec_exp_poly, vec_res, vec_factorial_1); \\\n vec_res = _mm512_fmadd_ps(vec_exp_poly, vec_res, vec_one); \\\n auto vec_exp_number = _mm512_sub_ps(vec_fx, vec_one); \\\n auto vec_exp_number_i = _mm512_cvtps_epi32(vec_exp_number); \\\n auto vec_two_pow_n_i = _mm512_add_epi32(vec_exp_number_i, vec_127); \\\n vec_two_pow_n_i = _mm512_slli_epi32(vec_two_pow_n_i, n_mantissa_bits); \\\n auto vec_two_pow_n = _mm512_castsi512_ps(vec_two_pow_n_i); \\\n vec_two_pow_n = _mm512_mask_blend_ps(less_ln_flt_min_mask, \\\n vec_two_pow_n, vec_zero); \\\n vec_res = _mm512_mul_ps(vec_res, vec_two_pow_n); \\\n vec_res = _mm512_mul_ps(vec_res, vec_two); \\\n vec_op::FP32Vec16 res(vec_res); \\\n return res; \\\n };\n #endif\n\n#endif\n\n#endif\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- markdownlint-disable -->\n\n## Purpose\n\nThis accelerates paged attention by 20% on Arm Neoverse-V2 for batch size = 64, query tokens = kv tokens = 512, q heads = 32, kv heads = 8, head size = 128, block size = 128\n\n## Test Plan\n\n@fadara01 will test in CI\n\n## Test Result\n\n---\n<details>\n<summary> Essential Elements of an Effective PR Description Checklist </summary>\n\n- [Y] The purpose of the PR, such as \"Fix some issue (link existing issues this PR will resolve)\".\n- [Y] The test plan, such as providing test command.\n- [Y] The test results, such as pasting the results comparison before and after, or e2e results\n- [ ] (Optional) The necessary documentation update, such as updating `supported_models.md` and `examples` for a new model.\n- [ ] (Optional) Release notes update. If your change is user facing, please update the release notes draft in the [Google Doc](https://docs.google.com/document/d/1YyVqrgX4gHTtrstbq8oWUImOyPCKSGnJ7xtTpmXzlRs/edit?tab=t.0).\n</details>\n\n\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": \"Arm Neoverse-V2\", \"model\": null, \"shape\": \"q_heads=32,kv_heads=8,head_size=128,block_size=128\", \"batch_size\": 64, \"metric\": \"latency\", \"unit\": null, \"higher_is_better\": false, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.2, \"speedup\": 1.2}]"},"kernel_speedup":{"kind":"number","value":1.2,"string":"1.2"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":399,"cells":{"repo":{"kind":"string","value":"vllm"},"commit":{"kind":"string","value":"19bee6d12d985c231b16374c99836376fc0c5706"},"date":{"kind":"string","value":"2025-12-03T13:04:59-05:00"},"pr_number":{"kind":"number","value":29470,"string":"29,470"},"pr_url":{"kind":"string","value":"https://github.com/vllm-project/vllm/pull/29470"},"title":{"kind":"string","value":"[Performance][DP/EP] Add silu_mul_per_token_group_quant_fp8_colmajor kernel (#29470)"},"message":{"kind":"string","value":"[Performance][DP/EP] Add silu_mul_per_token_group_quant_fp8_colmajor kernel (#29470)\n\nSigned-off-by: Varun Sundar Rabindranath <vsundarr@redhat.com>\nCo-authored-by: Varun Sundar Rabindranath <vsundarr@redhat.com>\nCo-authored-by: Tyler Michael Smith <tyler@neuralmagic.com>"},"path":{"kind":"string","value":"vllm/model_executor/layers/quantization/utils/fp8_utils.py"},"language":{"kind":"string","value":"triton"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"# SPDX-License-Identifier: Apache-2.0\n# SPDX-FileCopyrightText: Copyright contributors to the vLLM project\n\n# Adapted from https://github.com/sgl-project/sglang/pull/2575\nimport functools\nimport json\nimport os\nfrom collections.abc import Callable, Sequence\nfrom typing import Any\n\nimport torch\n\nimport vllm.envs as envs\nfrom vllm import _custom_ops as ops\nfrom vllm._aiter_ops import rocm_aiter_ops\nfrom vllm.logger import init_logger\nfrom vllm.model_executor.layers.quantization.input_quant_fp8 import QuantFP8\nfrom vllm.model_executor.layers.quantization.utils.quant_utils import (\n GroupShape,\n group_broadcast,\n)\nfrom vllm.model_executor.layers.quantization.utils.w8a8_utils import (\n CUTLASS_BLOCK_FP8_SUPPORTED,\n)\nfrom vllm.model_executor.parameter import (\n BlockQuantScaleParameter,\n ChannelQuantScaleParameter,\n PerTensorScaleParameter,\n)\nfrom vllm.platforms import current_platform\nfrom vllm.triton_utils import tl, triton\nfrom vllm.utils.deep_gemm import (\n fp8_gemm_nt,\n is_deep_gemm_e8m0_used,\n is_deep_gemm_supported,\n should_use_deepgemm_for_fp8_linear,\n transform_sf_into_required_layout,\n)\nfrom vllm.utils.torch_utils import direct_register_custom_op\n\nlogger = init_logger(__name__)\n\n\ndef is_fp8(x: torch.dtype | torch.Tensor) -> bool:\n if isinstance(x, torch.Tensor):\n x = x.dtype\n return x == torch.float8_e4m3fn or x == torch.float8_e4m3fnuz\n\n\n# We need to pass in the is_hopper flag as argument because the function\n# current_platform.is_device_capability() is not supported by Torch compiler.\ndef cutlass_scaled_mm(\n A: torch.Tensor,\n B: torch.Tensor,\n As: torch.Tensor,\n Bs: torch.Tensor,\n block_size: list[int],\n output_dtype: torch.dtype = torch.float16,\n) -> torch.Tensor:\n return ops.cutlass_scaled_mm(\n A,\n B.T,\n out_dtype=output_dtype,\n scale_a=As,\n scale_b=Bs.T,\n )\n\n\n# TODO we should be able to change the type of block_size to GroupShape\n# after we resolve GroupShape compilation issue\n# https://github.com/vllm-project/vllm/issues/25270\ndef _w8a8_triton_block_scaled_mm_func(\n qx: torch.Tensor,\n weight: torch.Tensor,\n x_scale: torch.Tensor,\n weight_scale: torch.Tensor,\n block_size: list[int],\n output_dtype: torch.dtype,\n) -> torch.Tensor:\n return w8a8_triton_block_scaled_mm(\n qx, weight, x_scale, weight_scale, block_size, output_dtype\n )\n\n\ndef _w8a8_triton_block_scaled_mm_fake(\n qx: torch.Tensor,\n weight: torch.Tensor,\n x_scale: torch.Tensor,\n weight_scale: torch.Tensor,\n block_size: list[int],\n output_dtype: torch.dtype,\n) -> torch.Tensor:\n return torch.empty(\n (qx.size(0), weight.size(0)), dtype=output_dtype, device=qx.device\n )\n\n\ndirect_register_custom_op(\n \"w8a8_triton_block_scaled_mm_func\",\n _w8a8_triton_block_scaled_mm_func,\n fake_impl=_w8a8_triton_block_scaled_mm_fake,\n)\n\n\ndef _padded_cutlass(\n qx: torch.Tensor,\n weight: torch.Tensor,\n x_scale: torch.Tensor,\n weight_scale: torch.Tensor,\n block_size: list[int],\n output_dtype: torch.dtype,\n) -> torch.Tensor:\n pad_multiple = 4\n dim = qx.shape[0]\n padded = (\n dim if dim % pad_multiple == 0 else dim + pad_multiple - (dim % pad_multiple)\n )\n\n has_pad = padded > dim\n\n if has_pad:\n padded_shape = [padded, *qx.shape[1:]]\n padded_qx = torch.zeros(padded_shape, device=qx.device, dtype=qx.dtype)\n padded_qx[0 : qx.shape[0], ...].copy_(qx)\n\n padded_x_scale_shape = [*x_scale.shape[1:], padded]\n padded_x_scale = torch.ones(\n padded_x_scale_shape, device=x_scale.device, dtype=x_scale.dtype\n ).permute(-1, -2)\n padded_x_scale[0 : x_scale.shape[0], ...].copy_(x_scale)\n\n output = cutlass_scaled_mm(\n padded_qx, weight, padded_x_scale, weight_scale, block_size, output_dtype\n )\n return output[0 : qx.shape[0], ...]\n else:\n return cutlass_scaled_mm(\n qx, weight, x_scale, weight_scale, block_size, output_dtype\n )\n\n\ndef _padded_cutlass_fake(\n qx: torch.Tensor,\n weight: torch.Tensor,\n x_scale: torch.Tensor,\n weight_scale: torch.Tensor,\n block_size: list[int],\n output_dtype: torch.dtype,\n) -> torch.Tensor:\n return torch.empty(\n (qx.size(0), weight.size(0)), dtype=output_dtype, device=qx.device\n )\n\n\ndirect_register_custom_op(\n \"padded_cutlass\",\n _padded_cutlass,\n fake_impl=_padded_cutlass_fake,\n)\n\n\ndef _fp8_gemm_nt_op(\n q_input: torch.Tensor,\n input_scale: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n output: torch.Tensor,\n use_deep_gemm_e8m0: bool,\n) -> None:\n fp8_gemm_nt(\n (q_input, input_scale),\n (weight, weight_scale),\n output,\n is_deep_gemm_e8m0_used=use_deep_gemm_e8m0,\n )\n\n\ndef _fp8_gemm_nt_op_fake(\n q_input: torch.Tensor,\n input_scale: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n output: torch.Tensor,\n use_deep_gemm_e8m0: bool,\n) -> None:\n return None\n\n\ndirect_register_custom_op(\n \"fp8_gemm_nt_op\",\n _fp8_gemm_nt_op,\n mutates_args=[\"output\"],\n fake_impl=_fp8_gemm_nt_op_fake,\n)\n\n\n# TODO fix ROCm->Triton custom path:\n# https://github.com/vllm-project/vllm/issues/14397\nclass W8A8BlockFp8LinearOp:\n \"\"\"\n This class executes a Blocked FP8 linear layer using cutlass if supported\n and torch.scaled_mm otherwise.\n \"\"\"\n\n def __init__(\n self,\n weight_group_shape: GroupShape,\n act_quant_group_shape: GroupShape,\n cutlass_block_fp8_supported: bool = CUTLASS_BLOCK_FP8_SUPPORTED,\n use_aiter_and_is_supported: bool = False,\n ):\n self.weight_group_shape = weight_group_shape\n self.act_quant_group_shape = act_quant_group_shape\n self.is_deep_gemm_supported = is_deep_gemm_supported()\n self.is_hopper = current_platform.is_device_capability(90)\n self.use_deep_gemm_e8m0 = is_deep_gemm_e8m0_used()\n\n # Get the correct blockscale mul and input quant operations.\n # We can't use _dispatch_w8a8_blockscale_op to figure out if we want\n # to use deepgemm because we don't know the shape of weights (and\n # whether deepgemm supports it) at the init time.\n self.w8a8_blockscale_op, self.input_quant_op = (\n self._dispatch_w8a8_blockscale_op(\n cutlass_block_fp8_supported, use_aiter_and_is_supported\n )\n )\n self.deepgemm_input_quant_op = (\n QuantFP8(\n False,\n self.act_quant_group_shape,\n column_major_scales=True,\n use_ue8m0=self.use_deep_gemm_e8m0,\n )\n if self.is_deep_gemm_supported\n else None\n )\n\n def apply(\n self,\n input: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n input_scale: torch.Tensor | None = None,\n bias: torch.Tensor | None = None,\n ) -> torch.Tensor:\n assert input_scale is None\n # View input as 2D matrix for fp8 methods\n input_2d = input.view(-1, input.shape[-1])\n output_shape = [*input.shape[:-1], weight.shape[0]]\n output_dtype = input.dtype\n\n if should_use_deepgemm_for_fp8_linear(\n output_dtype, weight, self.is_deep_gemm_supported\n ):\n output = self._run_deepgemm(input_2d, weight, weight_scale)\n else:\n output = self.w8a8_blockscale_op(\n input_2d, weight, weight_scale, input_scale\n )\n\n if bias is not None:\n output = output + bias\n return output.to(dtype=input.dtype).view(*output_shape)\n\n def _run_deepgemm(\n self,\n input_2d: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n ) -> torch.Tensor:\n assert self.deepgemm_input_quant_op is not None\n q_input, input_scale = self.deepgemm_input_quant_op(input_2d)\n output = torch.empty(\n (q_input.shape[0], weight.shape[0]),\n dtype=torch.bfloat16,\n device=q_input.device,\n )\n torch.ops.vllm.fp8_gemm_nt_op(\n q_input, input_scale, weight, weight_scale, output, self.use_deep_gemm_e8m0\n )\n return output\n\n def _run_cutlass(\n self,\n input_2d: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n input_scale: torch.Tensor | None = None,\n ) -> torch.Tensor:\n assert input_scale is None\n assert self.input_quant_op is not None\n q_input, input_scale = self.input_quant_op(input_2d)\n if self.is_hopper:\n return torch.ops.vllm.padded_cutlass(\n q_input,\n weight,\n input_scale,\n weight_scale,\n list(self.weight_group_shape),\n input_2d.dtype,\n )\n else:\n return cutlass_scaled_mm(\n q_input,\n weight,\n input_scale,\n weight_scale,\n list(self.weight_group_shape),\n input_2d.dtype,\n )\n\n def _run_aiter(\n self,\n input_2d: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n input_scale: torch.Tensor | None = None,\n ) -> torch.Tensor:\n assert self.act_quant_group_shape == GroupShape(1, 128)\n\n n, k = weight.shape\n\n use_triton = (\n not current_platform.is_fp8_fnuz()\n and rocm_aiter_ops.is_triton_gemm_w8a8_tuned(n, k)\n )\n\n if use_triton:\n gemm_a8w8_blockscale_op = rocm_aiter_ops.triton_gemm_a8w8_blockscale\n else:\n gemm_a8w8_blockscale_op = rocm_aiter_ops.gemm_a8w8_blockscale\n\n if input_scale is not None:\n q_input = input_2d\n # MI350 case uses triton kernel\n elif use_triton:\n q_input, input_scale = per_token_group_quant_fp8(\n input_2d,\n self.act_quant_group_shape.col,\n column_major_scales=False,\n use_ue8m0=False,\n )\n # MI300 uses tuned AITER ASM/C++ kernel\n else:\n q_input, input_scale = rocm_aiter_ops.group_fp8_quant(input_2d)\n\n return gemm_a8w8_blockscale_op(\n q_input,\n weight,\n input_scale,\n weight_scale,\n list(self.weight_group_shape),\n output_dtype=input_2d.dtype,\n )\n\n def _run_triton(\n self,\n input_2d: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n input_scale: torch.Tensor | None = None,\n ) -> torch.Tensor:\n assert input_scale is None\n assert self.input_quant_op is not None\n q_input, input_scale = self.input_quant_op(input_2d)\n return torch.ops.vllm.w8a8_triton_block_scaled_mm_func(\n q_input,\n weight,\n input_scale,\n weight_scale,\n list(self.weight_group_shape),\n input_2d.dtype,\n )\n\n def _dispatch_w8a8_blockscale_op(\n self,\n use_cutlass: bool,\n use_aiter_and_is_supported: bool,\n ) -> tuple[\n Callable[\n [\n torch.Tensor,\n torch.Tensor,\n torch.Tensor,\n torch.Tensor | None,\n ],\n torch.Tensor,\n ],\n QuantFP8 | None,\n ]:\n if use_cutlass:\n return self._run_cutlass, (\n QuantFP8(\n False,\n self.act_quant_group_shape,\n column_major_scales=True,\n use_ue8m0=False,\n )\n )\n if use_aiter_and_is_supported:\n return self._run_aiter, None\n return self._run_triton, (\n QuantFP8(\n False,\n self.act_quant_group_shape,\n column_major_scales=False,\n use_ue8m0=False,\n )\n )\n\n\ndef input_to_float8(\n x: torch.Tensor, dtype: torch.dtype | None = None\n) -> tuple[torch.Tensor, torch.Tensor]:\n \"\"\"This function quantizes input values to float8 values \"\n \"with tensor-wise quantization.\"\"\"\n dtype = current_platform.fp8_dtype() if dtype is None else dtype\n finfo = torch.finfo(dtype)\n min_val, max_val = x.aminmax()\n amax = torch.maximum(min_val.abs(), max_val.abs()).clamp(min=1e-12)\n scale = finfo.max / amax\n x_scl_sat = (x * scale).clamp(min=finfo.min, max=finfo.max)\n return x_scl_sat.to(dtype).contiguous(), scale.float().reciprocal()\n\n\ndef block_quant_to_tensor_quant(\n x_q_block: torch.Tensor,\n x_s: torch.Tensor,\n) -> tuple[torch.Tensor, torch.Tensor]:\n \"\"\"This function converts block-wise quantization to tensor-wise\n quantization. The inputs are block-wise quantization tensor `x_q_block`,\n block-wise quantization scale and the block size.\n The outputs are tensor-wise quantization tensor and tensor-wise\n quantization scale. Note only float8 is supported for now.\n \"\"\"\n x_dq_block = group_broadcast(x_q_block, x_s)\n x_q_tensor, scale = input_to_float8(x_dq_block, dtype=x_q_block.dtype)\n return x_q_tensor, scale\n\n\n@triton.jit\ndef _per_token_group_quant_fp8(\n # Pointers to inputs and output\n y_ptr,\n y_q_ptr,\n y_s_ptr,\n group_size,\n # Num columns of y\n y_num_columns,\n y_row_stride,\n # Avoid to divide zero\n eps,\n # Information for float8\n fp8_min,\n fp8_max,\n use_ue8m0: tl.constexpr,\n # Meta-parameters\n BLOCK: tl.constexpr,\n):\n \"\"\"A Triton-accelerated function to perform per-token-group\n quantization on a tensor.\n This function converts the tensor values into float8 values.\n \"\"\"\n groups_per_row = y_num_columns // group_size\n\n # Map the program id to the row of X and Y it should compute.\n g_id = tl.program_id(0)\n row = g_id // groups_per_row\n row_g_id = g_id % groups_per_row\n\n # Ensure offset calculations use int64 to prevent overflow\n y_ptr_offset = (row.to(tl.int64) * y_row_stride) + (\n row_g_id.to(tl.int64) * group_size\n )\n y_ptr += y_ptr_offset\n\n y_q_ptr_offset = g_id.to(tl.int64) * group_size\n y_q_ptr += y_q_ptr_offset\n y_s_ptr += g_id\n\n cols = tl.arange(0, BLOCK) # N <= BLOCK\n mask = cols < group_size\n\n y = tl.load(y_ptr + cols, mask=mask, other=0.0).to(tl.float32)\n # Quant\n _absmax = tl.maximum(tl.max(tl.abs(y)), eps)\n scale_raw = _absmax / fp8_max\n y_s = tl.math.exp2(tl.ceil(tl.log2(scale_raw))) if use_ue8m0 else scale_raw\n y_q = tl.clamp(y / y_s, fp8_min, fp8_max).to(y_q_ptr.dtype.element_ty)\n\n tl.store(y_q_ptr + cols, y_q, mask=mask)\n tl.store(y_s_ptr, y_s)\n\n\n@triton.jit\ndef _per_token_group_quant_fp8_colmajor(\n # Pointers to inputs and output\n y_ptr,\n y_q_ptr,\n y_s_ptr,\n group_size,\n # Num columns of y\n y_num_columns,\n y_row_stride,\n # Stride from one column to the next of y_s\n y_s_col_stride,\n # Avoid to divide zero\n eps,\n # Information for float8\n fp8_min,\n fp8_max,\n use_ue8m0: tl.constexpr,\n # Meta-parameters\n BLOCK: tl.constexpr,\n):\n \"\"\"A Triton-accelerated function to perform per-token-group\n quantization on a tensor.\n This function converts the tensor values into float8 values.\n \"\"\"\n groups_per_row = y_num_columns // group_size\n\n # Map the program id to the row of X and Y it should compute.\n g_id = tl.program_id(0)\n row = g_id // groups_per_row\n row_g_id = g_id % groups_per_row\n\n # Ensure offset calculations use int64 to prevent overflow\n y_ptr_offset = (row.to(tl.int64) * y_row_stride) + (\n row_g_id.to(tl.int64) * group_size\n )\n y_ptr += y_ptr_offset\n\n y_q_ptr_offset = g_id.to(tl.int64) * group_size\n y_q_ptr += y_q_ptr_offset\n\n # Convert g_id the flattened block coordinate to 2D so we can index\n # into the output y_scales matrix\n blocks_per_row = y_num_columns // group_size\n scale_col = g_id % blocks_per_row\n scale_row = g_id // blocks_per_row\n # Ensure offset calculation uses int64 for y_s_ptr\n y_s_ptr_offset = (scale_col.to(tl.int64) * y_s_col_stride) + scale_row.to(tl.int64)\n y_s_ptr += y_s_ptr_offset\n\n cols = tl.arange(0, BLOCK) # group_size <= BLOCK\n mask = cols < group_size\n\n y = tl.load(y_ptr + cols, mask=mask, other=0.0).to(tl.float32)\n # Quant\n _absmax = tl.maximum(tl.max(tl.abs(y)), eps)\n scale_raw = _absmax / fp8_max\n y_s = tl.math.exp2(tl.ceil(tl.log2(scale_raw))) if use_ue8m0 else scale_raw\n y_q = tl.clamp(y / y_s, fp8_min, fp8_max).to(y_q_ptr.dtype.element_ty)\n\n tl.store(y_q_ptr + cols, y_q, mask=mask)\n tl.store(y_s_ptr, y_s)\n\n\ndef per_token_group_quant_fp8(\n x: torch.Tensor,\n group_size: int,\n eps: float = 1e-10,\n dtype: torch.dtype | None = None,\n column_major_scales: bool = False,\n out_q: torch.Tensor | None = None,\n use_ue8m0: bool | None = None,\n) -> tuple[torch.Tensor, torch.Tensor]:\n \"\"\"Function to perform per-token-group quantization on an input tensor `x`.\n It converts the tensor values into signed float8 values and returns the\n quantized tensor along with the scaling factor used for quantization.\n Args:\n x: The input tensor with ndim >= 2.\n group_size: The group size used for quantization.\n eps: The minimum to avoid dividing zero.\n dtype: The dype of output tensor. Note that only `torch.float8_e4m3fn`\n is supported for now.\n column_major_scales: Outputs scales in column major.\n out_q: Optional output tensor. If not provided, function will create.\n Returns:\n tuple[torch.Tensor, torch.Tensor]: The quantized tensor and the\n scaling factor.\n \"\"\"\n if use_ue8m0 is None:\n use_ue8m0 = is_deep_gemm_e8m0_used()\n dtype = current_platform.fp8_dtype() if dtype is None else dtype\n assert x.shape[-1] % group_size == 0, (\n f\"the last dimension of `x` {x.shape[-1]} must be divisible \"\n f\"by `group_size` {group_size}\"\n )\n assert x.stride(-1) == 1, \"`x` groups must be contiguous\"\n\n finfo = torch.finfo(dtype)\n fp8_min = finfo.min\n fp8_max = finfo.max\n\n assert out_q is None or out_q.shape == x.shape\n x_q = out_q\n if x_q is None:\n x_q = torch.empty_like(x, device=x.device, dtype=dtype)\n\n # Allocate the scale tensor in either row- or column-major format.\n if column_major_scales:\n shape = (x.shape[-1] // group_size,) + x.shape[:-1]\n x_s = torch.empty(shape, device=x.device, dtype=torch.float32).permute(-1, -2)\n else:\n shape = x.shape[:-1] + (x.shape[-1] // group_size,)\n x_s = torch.empty(shape, device=x.device, dtype=torch.float32)\n\n # prefer CUDA kernel if available\n # TODO(bnell): this causes some fp8 moe test to fail.\n if current_platform.is_cuda() and x.is_contiguous():\n torch.ops._C.per_token_group_fp8_quant(\n x, x_q, x_s, group_size, eps, fp8_min, fp8_max, use_ue8m0\n )\n return x_q, x_s\n\n # TRITON FALLBACK\n M = x.numel() // group_size\n N = group_size\n BLOCK = triton.next_power_of_2(N)\n # heuristics for number of warps\n num_warps = min(max(BLOCK // 256, 1), 8)\n num_stages = 1\n if column_major_scales:\n _per_token_group_quant_fp8_colmajor[(M,)](\n x,\n x_q,\n x_s,\n group_size,\n x.shape[1],\n x.stride(0),\n x_s.stride(1),\n eps,\n fp8_min=fp8_min,\n fp8_max=fp8_max,\n use_ue8m0=use_ue8m0,\n BLOCK=BLOCK,\n num_warps=num_warps,\n num_stages=num_stages,\n )\n else:\n _per_token_group_quant_fp8[(M,)](\n x,\n x_q,\n x_s,\n group_size,\n x.shape[1],\n x.stride(0),\n eps,\n fp8_min=fp8_min,\n fp8_max=fp8_max,\n use_ue8m0=use_ue8m0,\n BLOCK=BLOCK,\n num_warps=num_warps,\n num_stages=num_stages,\n )\n\n return x_q, x_s\n\n\n@triton.jit\ndef _w8a8_triton_block_scaled_mm(\n # Pointers to inputs and output\n A,\n B,\n C,\n As,\n Bs,\n # Shape for matmul\n M,\n N,\n K,\n # Block size for block-wise quantization\n group_n,\n group_k,\n # Stride for inputs and output\n stride_am,\n stride_ak,\n stride_bk,\n stride_bn,\n stride_cm,\n stride_cn,\n stride_As_m,\n stride_As_k,\n stride_Bs_k,\n stride_Bs_n,\n # Meta-parameters\n BLOCK_SIZE_M: tl.constexpr,\n BLOCK_SIZE_N: tl.constexpr,\n BLOCK_SIZE_K: tl.constexpr,\n GROUP_SIZE_M: tl.constexpr,\n):\n \"\"\"Triton-accelerated function used to perform linear operations (dot\n product) on input tensors `A` and `B` with block-wise quantization, and\n store the result in output tensor `C`.\n \"\"\"\n\n pid = tl.program_id(axis=0)\n num_pid_m = tl.cdiv(M, BLOCK_SIZE_M)\n num_pid_n = tl.cdiv(N, BLOCK_SIZE_N)\n num_pid_in_group = GROUP_SIZE_M * num_pid_n\n group_id = pid // num_pid_in_group\n first_pid_m = group_id * GROUP_SIZE_M\n group_size_m = min(num_pid_m - first_pid_m, GROUP_SIZE_M)\n pid_m = first_pid_m + (pid % group_size_m)\n pid_n = (pid % num_pid_in_group) // group_size_m\n\n offs_am = (pid_m * BLOCK_SIZE_M + tl.arange(0, BLOCK_SIZE_M)) % M\n offs_bn = (pid_n * BLOCK_SIZE_N + tl.arange(0, BLOCK_SIZE_N)) % N\n offs_k = tl.arange(0, BLOCK_SIZE_K)\n a_ptrs = A + (offs_am[:, None] * stride_am + offs_k[None, :] * stride_ak)\n b_ptrs = B + (offs_k[:, None] * stride_bk + offs_bn[None, :] * stride_bn)\n\n As_ptrs = As + offs_am * stride_As_m\n offs_bsn = offs_bn // group_n\n Bs_ptrs = Bs + offs_bsn * stride_Bs_n\n\n accumulator = tl.zeros((BLOCK_SIZE_M, BLOCK_SIZE_N), dtype=tl.float32)\n for k in range(0, tl.cdiv(K, BLOCK_SIZE_K)):\n a = tl.load(a_ptrs, mask=offs_k[None, :] < K - k * BLOCK_SIZE_K, other=0.0)\n b = tl.load(b_ptrs, mask=offs_k[:, None] < K - k * BLOCK_SIZE_K, other=0.0)\n\n k_start = k * BLOCK_SIZE_K\n offs_ks = k_start // group_k\n a_s = tl.load(As_ptrs + offs_ks * stride_As_k)\n b_s = tl.load(Bs_ptrs + offs_ks * stride_Bs_k)\n\n accumulator += tl.dot(a, b) * a_s[:, None] * b_s[None, :]\n a_ptrs += BLOCK_SIZE_K * stride_ak\n b_ptrs += BLOCK_SIZE_K * stride_bk\n\n if C.dtype.element_ty == tl.bfloat16:\n c = accumulator.to(tl.bfloat16)\n elif C.dtype.element_ty == tl.float16:\n c = accumulator.to(tl.float16)\n else:\n c = accumulator.to(tl.float32)\n\n offs_cm = pid_m * BLOCK_SIZE_M + tl.arange(0, BLOCK_SIZE_M)\n offs_cn = pid_n * BLOCK_SIZE_N + tl.arange(0, BLOCK_SIZE_N)\n c_ptrs = C + stride_cm * offs_cm[:, None] + stride_cn * offs_cn[None, :]\n c_mask = (offs_cm[:, None] < M) & (offs_cn[None, :] < N)\n tl.store(c_ptrs, c, mask=c_mask)\n\n\n@functools.lru_cache\ndef get_w8a8_block_fp8_configs(\n N: int, K: int, block_n: int, block_k: int\n) -> dict[int, Any] | None:\n \"\"\"\n Return optimized configurations for the w8a8 block fp8 kernel.\n The return value will be a dictionary that maps an irregular grid of\n batch sizes to configurations of the w8a8 block fp8 kernel. To evaluate the\n kernel on a given batch size bs, the closest batch size in the grid should\n be picked and the associated configuration chosen to invoke the kernel.\n \"\"\"\n\n # First look up if an optimized configuration is available in the configs\n # directory\n device_name = current_platform.get_device_name().replace(\" \", \"_\")\n json_file_name = f\"N={N},K={K},device_name={device_name},dtype=fp8_w8a8,block_shape=[{block_n},{block_k}].json\" # noqa: E501\n\n config_file_path = os.path.join(\n os.path.dirname(os.path.realpath(__file__)), \"configs\", json_file_name\n )\n if os.path.exists(config_file_path):\n with open(config_file_path) as f:\n logger.info(\n \"Using configuration from %s for W8A8 Block FP8 kernel.\",\n config_file_path,\n )\n # If a configuration has been found, return it\n return {int(key): val for key, val in json.load(f).items()}\n\n # If no optimized configuration is available, we will use the default\n # configuration\n logger.warning(\n \"Using default W8A8 Block FP8 kernel config. Performance might \"\n \"be sub-optimal! Config file not found at %s\",\n config_file_path,\n )\n return None\n\n\ndef w8a8_triton_block_scaled_mm(\n A: torch.Tensor,\n B: torch.Tensor,\n As: torch.Tensor,\n Bs: torch.Tensor,\n block_size: list[int],\n output_dtype: torch.dtype = torch.float16,\n) -> torch.Tensor:\n \"\"\"This function performs matrix multiplication with block-wise\n quantization.\n It takes two input tensors `A` and `B` with scales `As` and `Bs`.\n The output is returned in the specified `output_dtype`.\n Args:\n A: The input tensor, e.g., activation.\n B: The input tensor, e.g., weight.\n As: The per-token-group quantization scale for `A`.\n Bs: The per-block quantization scale for `B`.\n block_size: The block size for per-block quantization. It should\n be 2-dim, e.g., [128, 128].\n output_dytpe: The dtype of the returned tensor.\n Returns:\n torch.Tensor: The result of matmul.\n \"\"\"\n assert len(block_size) == 2\n block_n, block_k = block_size[0], block_size[1]\n\n assert A.shape[-1] == B.shape[-1]\n assert A.shape[:-1] == As.shape[:-1] and A.is_contiguous()\n assert triton.cdiv(A.shape[-1], block_k) == As.shape[-1]\n M = A.numel() // A.shape[-1]\n\n assert B.ndim == 2 and Bs.ndim == 2\n N, K = B.shape\n assert triton.cdiv(N, block_n) == Bs.shape[0]\n assert triton.cdiv(K, block_k) == Bs.shape[1]\n\n C_shape = A.shape[:-1] + (N,)\n C = A.new_empty(C_shape, dtype=output_dtype)\n\n configs = get_w8a8_block_fp8_configs(N, K, block_size[0], block_size[1])\n if configs:\n # Get the optimal config if there is one\n config = configs[min(configs.keys(), key=lambda x: abs(x - M))]\n else:\n # Default config\n # Block-wise quant: BLOCK_SIZE_N must be divisible by block_size[0]\n # BLOCK_SIZE_K must be divisible by block_size[1]\n config = {\n \"BLOCK_SIZE_M\": 64,\n \"BLOCK_SIZE_N\": block_size[0],\n \"BLOCK_SIZE_K\": block_size[1],\n \"GROUP_SIZE_M\": 32,\n \"num_warps\": 4,\n \"num_stages\": 2,\n }\n\n def grid(META):\n return (\n triton.cdiv(M, META[\"BLOCK_SIZE_M\"]) * triton.cdiv(N, META[\"BLOCK_SIZE_N\"]),\n )\n\n _w8a8_triton_block_scaled_mm[grid](\n A,\n B,\n C,\n As,\n Bs,\n M,\n N,\n K,\n block_n,\n block_k,\n A.stride(-2),\n A.stride(-1),\n B.stride(1),\n B.stride(0),\n C.stride(-2),\n C.stride(-1),\n As.stride(-2),\n As.stride(-1),\n Bs.stride(1),\n Bs.stride(0),\n **config,\n )\n\n return C\n\n\ndef requant_weight_ue8m0_inplace(\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n block_size: Sequence[int] = (128, 128),\n) -> None:\n \"\"\"Re-quantise *weight* so that its per-block scaling factors are in the\n UE8M0 (power-of-two) format expected by the new DeepGEMM kernels inplace.\n\n Args:\n weight: Block-quantised weight tensor stored in `torch.float8_e4m3fn`.\n Expected shape `(..., M, K)`.\n weight_scale: Corresponding per-block scale tensor (`torch.float32`)\n with shape `(..., M // block_size[0], K // block_size[1])`.\n block_size: 2-element iterable `[block_m, block_k]` describing the\n block quantisation granularity.\n \"\"\"\n if weight.numel() == 0:\n return\n\n if weight.dtype != torch.float8_e4m3fn:\n raise ValueError(\n f\"Expected *weight* to be torch.float8_e4m3fn, got {weight.dtype} instead.\"\n )\n\n from vllm.utils.deep_gemm import per_block_cast_to_fp8\n\n block_m, block_k = int(block_size[0]), int(block_size[1])\n\n # Flatten leading dimensions so we can iterate over the last two dims.\n leading_shape = weight.shape[:-2]\n if len(leading_shape) == 0:\n w_view = weight.unsqueeze(0)\n s_view = weight_scale.unsqueeze(0)\n else:\n w_view = weight.reshape(-1, weight.shape[-2], weight.shape[-1])\n s_view = weight_scale.reshape(-1, *weight_scale.shape[-2:])\n\n num_mats = w_view.size(0)\n for idx in range(num_mats):\n w_q = w_view[idx]\n s_old = s_view[idx]\n\n # De-quantise with the *old* scaling factors (float32).\n m_cur, k_cur = w_q.shape\n s_float = s_old.to(torch.float32)\n # Expand scales along rows and cols by block size, then crop.\n s_exp_r = torch.repeat_interleave(s_float, block_m, dim=0)\n s_exp = torch.repeat_interleave(s_exp_r, block_k, dim=1)\n s_exp = s_exp[:m_cur, :k_cur]\n w_dq = w_q.to(torch.float32) * s_exp\n # Re-quantise using power-of-two scaling (UE8M0).\n w_requant, s_requant = per_block_cast_to_fp8(\n w_dq, [block_m, block_k], use_ue8m0=True\n )\n\n # Write back the results in-place.\n w_q.copy_(w_requant)\n s_old.copy_(s_requant)\n\n\ndef deepgemm_post_process_fp8_weight_block(\n wq: torch.Tensor, ws: torch.Tensor, quant_block_shape: tuple[int], use_e8m0: bool\n) -> tuple[torch.Tensor, torch.Tensor]:\n assert wq.dtype == torch.float8_e4m3fn, (\n \"Expected quantized tensor dtype \"\n f\"to be torch.float8_e4m3fn, got {wq.dtype} instead.\"\n )\n assert ws.dtype == torch.float32, (\n f\"Expected tensor scales dtype to be torch.float32, got {ws.dtype} instead\"\n )\n\n if use_e8m0:\n requant_weight_ue8m0_inplace(wq, ws, block_size=quant_block_shape)\n\n original_ndim = wq.ndim\n if wq.ndim == 2:\n assert ws.ndim == 2\n wq = wq.unsqueeze(0)\n ws = ws.unsqueeze(0)\n\n # From https://github.com/deepseek-ai/DeepGEMM/blob/c9f8b34dcdacc20aa746b786f983492c51072870/csrc/utils/layout.hpp#L46\n recipe = (1, 128, 128)\n\n # Ref : https://github.com/deepseek-ai/DeepGEMM/blob/c9f8b34dcdacc20aa746b786f983492c51072870/csrc/apis/gemm.hpp\n # DeepGemm uses the `transform_sf_into_required_layout` function to\n # represent scales in the correct format.\n dg_ws = transform_sf_into_required_layout(\n sf=ws,\n mn=wq.size(1),\n k=wq.size(2),\n recipe=recipe,\n num_groups=wq.size(0),\n # is the scale factors for A in (Refers to the argument A in A @ B).\n # Weights are B.\n is_sfa=False,\n )\n\n if original_ndim == 2:\n wq = wq.squeeze(0)\n dg_ws = dg_ws.squeeze(0)\n\n return wq, dg_ws\n\n\ndef _maybe_pad_fp8_weight(weight: torch.Tensor) -> torch.Tensor:\n \"\"\"Pad the weight tensor. This is an optimization on ROCm platform, which\n can benefit from tensors located far enough from one another in memory\"\"\"\n if (\n envs.VLLM_ROCM_FP8_PADDING\n and current_platform.is_rocm()\n and weight.stride(-1) == 1\n and (weight.stride(-2) * weight.element_size()) % 512 == 0\n ):\n num_pad = 256 // weight.element_size()\n import torch.nn.functional as F\n\n weight = F.pad(weight, (0, num_pad), \"constant\", 0)[..., :-num_pad]\n torch.cuda.empty_cache()\n return weight\n\n\ndef validate_fp8_block_shape(\n layer: torch.nn.Module,\n input_size: int,\n output_size: int,\n input_size_per_partition: int,\n output_partition_sizes: list[int],\n block_size: list[int],\n) -> None:\n \"\"\"Validate block quantization shapes for tensor parallelism.\"\"\"\n from vllm.distributed import get_tensor_model_parallel_world_size\n\n tp_size = getattr(layer, \"tp_size\", get_tensor_model_parallel_world_size())\n block_n, block_k = block_size[0], block_size[1]\n\n # Required by row parallel\n if (\n tp_size > 1\n and input_size // input_size_per_partition == tp_size\n and input_size_per_partition % block_k != 0\n ):\n raise ValueError(\n f\"Weight input_size_per_partition = {input_size_per_partition} \"\n f\"is not divisible by weight quantization block_k = {block_k}.\"\n )\n\n # Required by column parallel or enabling merged weights\n is_tp_split = tp_size > 1 and output_size // sum(output_partition_sizes) == tp_size\n is_merged_gemm = len(output_partition_sizes) > 1\n if is_tp_split or is_merged_gemm:\n sizes_to_check = output_partition_sizes\n if not is_tp_split and is_merged_gemm:\n # In case of merged matrices, we allow the last\n # matrix to not be a multiple of block size\n sizes_to_check = output_partition_sizes[:-1]\n for output_partition_size in sizes_to_check:\n if output_partition_size % block_n != 0:\n raise ValueError(\n f\"Weight output_partition_size = \"\n f\"{output_partition_size} is not divisible by \"\n f\"weight quantization block_n = {block_n}.\"\n )\n\n\ndef create_fp8_weight_parameter(\n output_size_per_partition: int,\n input_size_per_partition: int,\n weight_loader: Callable | None,\n) -> torch.nn.Parameter:\n \"\"\"Create FP8 weight parameter.\"\"\"\n from vllm.model_executor.parameter import ModelWeightParameter\n\n return ModelWeightParameter(\n data=torch.empty(\n output_size_per_partition,\n input_size_per_partition,\n dtype=torch.float8_e4m3fn,\n ),\n input_dim=1,\n output_dim=0,\n weight_loader=weight_loader,\n )\n\n\ndef create_fp8_scale_parameter(\n parameter_type: torch.nn.Parameter,\n output_partition_sizes: list[int],\n input_size_per_partition: int,\n block_size: list[int] | None,\n weight_loader: Callable | None,\n) -> torch.nn.Parameter:\n \"\"\"Create scale parameter based on quantization strategy.\"\"\"\n if parameter_type == ChannelQuantScaleParameter:\n scale = parameter_type(\n data=torch.empty((sum(output_partition_sizes), 1), dtype=torch.float32),\n output_dim=0,\n weight_loader=weight_loader,\n )\n elif parameter_type == BlockQuantScaleParameter:\n assert block_size is not None\n block_n, block_k = block_size[0], block_size[1]\n output_size_per_partition = sum(output_partition_sizes)\n scale = parameter_type(\n data=torch.empty(\n (output_size_per_partition + block_n - 1) // block_n,\n (input_size_per_partition + block_k - 1) // block_k,\n dtype=torch.float32,\n ),\n input_dim=1,\n output_dim=0,\n weight_loader=weight_loader,\n )\n elif parameter_type == PerTensorScaleParameter:\n scale = parameter_type(\n data=torch.empty(len(output_partition_sizes), dtype=torch.float32),\n weight_loader=weight_loader,\n )\n else:\n raise ValueError(f\"Unknown parameter type: {parameter_type}\")\n\n scale[:] = torch.finfo(torch.float32).min\n return scale\n\n\ndef create_fp8_input_scale(\n output_partition_sizes: list[int], weight_loader: Callable | None\n) -> torch.nn.Parameter:\n \"\"\"Create input scale parameter for static activation quantization.\"\"\"\n from vllm.model_executor.parameter import PerTensorScaleParameter\n\n scale = PerTensorScaleParameter(\n data=torch.empty(len(output_partition_sizes), dtype=torch.float32),\n weight_loader=weight_loader,\n )\n scale[:] = torch.finfo(torch.float32).min\n return scale\n\n\ndef process_fp8_weight_tensor_strategy(\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n logical_widths: list[int],\n input_scale: torch.Tensor | None = None,\n) -> tuple[torch.Tensor, torch.Tensor, torch.Tensor | None]:\n \"\"\"Process weights for tensor-wise quantization strategy.\"\"\"\n from vllm.model_executor.layers.quantization.utils.w8a8_utils import (\n normalize_e4m3fn_to_e4m3fnuz,\n requantize_with_max_scale,\n )\n\n if current_platform.is_fp8_fnuz():\n weight, weight_scale, input_scale = normalize_e4m3fn_to_e4m3fnuz(\n weight=weight, weight_scale=weight_scale, input_scale=input_scale\n )\n\n # Requantize with max scale\n weight_scale, weight = requantize_with_max_scale(\n weight=weight,\n weight_scale=weight_scale,\n logical_widths=logical_widths,\n )\n\n weight = _maybe_pad_fp8_weight(weight)\n return weight, weight_scale, input_scale\n\n\ndef process_fp8_weight_channel_strategy(\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n input_scale: torch.Tensor | None = None,\n) -> tuple[torch.Tensor, torch.Tensor, torch.Tensor | None]:\n \"\"\"Process weights for channel-wise quantization strategy.\"\"\"\n from vllm.model_executor.layers.quantization.utils.w8a8_utils import (\n normalize_e4m3fn_to_e4m3fnuz,\n )\n\n if current_platform.is_fp8_fnuz():\n weight, weight_scale, input_scale = normalize_e4m3fn_to_e4m3fnuz(\n weight=weight, weight_scale=weight_scale, input_scale=input_scale\n )\n\n return weight, weight_scale, input_scale\n\n\ndef process_fp8_weight_block_strategy(\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n) -> tuple[torch.Tensor, torch.Tensor]:\n \"\"\"Process weights for block-wise quantization strategy.\"\"\"\n from vllm.model_executor.layers.quantization.utils.w8a8_utils import (\n normalize_e4m3fn_to_e4m3fnuz,\n )\n\n if current_platform.is_fp8_fnuz():\n weight, weight_scale, _ = normalize_e4m3fn_to_e4m3fnuz(\n weight=weight, weight_scale=weight_scale\n )\n\n weight = _maybe_pad_fp8_weight(weight)\n return weight, weight_scale\n\n\ndef maybe_post_process_fp8_weight_block(layer: torch.nn.Module):\n assert layer.weight_block_size is not None\n\n from vllm.utils.deep_gemm import (\n is_deep_gemm_e8m0_used,\n should_use_deepgemm_for_fp8_linear,\n )\n\n # On Blackwell or Hopper, if E8M0 for DeepGemm is used, we need to\n # requantize the weight and input to the specific scale\n # at the same time.\n should_use_deepgemm = should_use_deepgemm_for_fp8_linear(\n layer.orig_dtype, layer.weight\n )\n if should_use_deepgemm:\n dg_weight, dg_weight_scale = deepgemm_post_process_fp8_weight_block(\n wq=layer.weight.data,\n ws=layer.weight_scale.data,\n quant_block_shape=tuple(layer.weight_block_size),\n use_e8m0=is_deep_gemm_e8m0_used(),\n )\n layer.weight = torch.nn.Parameter(dg_weight, requires_grad=False)\n layer.weight_scale = torch.nn.Parameter(dg_weight_scale, requires_grad=False)\n\n\ndef expert_weight_is_col_major(x: torch.Tensor) -> bool:\n assert x.dim() == 3\n b, m, n = x.shape\n return x.stride(0) == m * n and x.stride(1) == 1 and x.stride(2) == m\n"},"after_code":{"kind":"string","value":"# SPDX-License-Identifier: Apache-2.0\n# SPDX-FileCopyrightText: Copyright contributors to the vLLM project\n\n# Adapted from https://github.com/sgl-project/sglang/pull/2575\nimport functools\nimport json\nimport os\nfrom collections.abc import Callable, Sequence\nfrom typing import Any\n\nimport torch\n\nimport vllm.envs as envs\nfrom vllm import _custom_ops as ops\nfrom vllm._aiter_ops import rocm_aiter_ops\nfrom vllm.logger import init_logger\nfrom vllm.model_executor.layers.quantization.input_quant_fp8 import QuantFP8\nfrom vllm.model_executor.layers.quantization.utils.quant_utils import (\n GroupShape,\n group_broadcast,\n)\nfrom vllm.model_executor.layers.quantization.utils.w8a8_utils import (\n CUTLASS_BLOCK_FP8_SUPPORTED,\n)\nfrom vllm.model_executor.parameter import (\n BlockQuantScaleParameter,\n ChannelQuantScaleParameter,\n PerTensorScaleParameter,\n)\nfrom vllm.platforms import current_platform\nfrom vllm.triton_utils import tl, triton\nfrom vllm.utils.deep_gemm import (\n fp8_gemm_nt,\n is_deep_gemm_e8m0_used,\n is_deep_gemm_supported,\n should_use_deepgemm_for_fp8_linear,\n transform_sf_into_required_layout,\n)\nfrom vllm.utils.torch_utils import direct_register_custom_op\n\nlogger = init_logger(__name__)\n\n\ndef is_fp8(x: torch.dtype | torch.Tensor) -> bool:\n if isinstance(x, torch.Tensor):\n x = x.dtype\n return x == torch.float8_e4m3fn or x == torch.float8_e4m3fnuz\n\n\n# We need to pass in the is_hopper flag as argument because the function\n# current_platform.is_device_capability() is not supported by Torch compiler.\ndef cutlass_scaled_mm(\n A: torch.Tensor,\n B: torch.Tensor,\n As: torch.Tensor,\n Bs: torch.Tensor,\n block_size: list[int],\n output_dtype: torch.dtype = torch.float16,\n) -> torch.Tensor:\n return ops.cutlass_scaled_mm(\n A,\n B.T,\n out_dtype=output_dtype,\n scale_a=As,\n scale_b=Bs.T,\n )\n\n\n# TODO we should be able to change the type of block_size to GroupShape\n# after we resolve GroupShape compilation issue\n# https://github.com/vllm-project/vllm/issues/25270\ndef _w8a8_triton_block_scaled_mm_func(\n qx: torch.Tensor,\n weight: torch.Tensor,\n x_scale: torch.Tensor,\n weight_scale: torch.Tensor,\n block_size: list[int],\n output_dtype: torch.dtype,\n) -> torch.Tensor:\n return w8a8_triton_block_scaled_mm(\n qx, weight, x_scale, weight_scale, block_size, output_dtype\n )\n\n\ndef _w8a8_triton_block_scaled_mm_fake(\n qx: torch.Tensor,\n weight: torch.Tensor,\n x_scale: torch.Tensor,\n weight_scale: torch.Tensor,\n block_size: list[int],\n output_dtype: torch.dtype,\n) -> torch.Tensor:\n return torch.empty(\n (qx.size(0), weight.size(0)), dtype=output_dtype, device=qx.device\n )\n\n\ndirect_register_custom_op(\n \"w8a8_triton_block_scaled_mm_func\",\n _w8a8_triton_block_scaled_mm_func,\n fake_impl=_w8a8_triton_block_scaled_mm_fake,\n)\n\n\ndef _padded_cutlass(\n qx: torch.Tensor,\n weight: torch.Tensor,\n x_scale: torch.Tensor,\n weight_scale: torch.Tensor,\n block_size: list[int],\n output_dtype: torch.dtype,\n) -> torch.Tensor:\n pad_multiple = 4\n dim = qx.shape[0]\n padded = (\n dim if dim % pad_multiple == 0 else dim + pad_multiple - (dim % pad_multiple)\n )\n\n has_pad = padded > dim\n\n if has_pad:\n padded_shape = [padded, *qx.shape[1:]]\n padded_qx = torch.zeros(padded_shape, device=qx.device, dtype=qx.dtype)\n padded_qx[0 : qx.shape[0], ...].copy_(qx)\n\n padded_x_scale_shape = [*x_scale.shape[1:], padded]\n padded_x_scale = torch.ones(\n padded_x_scale_shape, device=x_scale.device, dtype=x_scale.dtype\n ).permute(-1, -2)\n padded_x_scale[0 : x_scale.shape[0], ...].copy_(x_scale)\n\n output = cutlass_scaled_mm(\n padded_qx, weight, padded_x_scale, weight_scale, block_size, output_dtype\n )\n return output[0 : qx.shape[0], ...]\n else:\n return cutlass_scaled_mm(\n qx, weight, x_scale, weight_scale, block_size, output_dtype\n )\n\n\ndef _padded_cutlass_fake(\n qx: torch.Tensor,\n weight: torch.Tensor,\n x_scale: torch.Tensor,\n weight_scale: torch.Tensor,\n block_size: list[int],\n output_dtype: torch.dtype,\n) -> torch.Tensor:\n return torch.empty(\n (qx.size(0), weight.size(0)), dtype=output_dtype, device=qx.device\n )\n\n\ndirect_register_custom_op(\n \"padded_cutlass\",\n _padded_cutlass,\n fake_impl=_padded_cutlass_fake,\n)\n\n\ndef _fp8_gemm_nt_op(\n q_input: torch.Tensor,\n input_scale: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n output: torch.Tensor,\n use_deep_gemm_e8m0: bool,\n) -> None:\n fp8_gemm_nt(\n (q_input, input_scale),\n (weight, weight_scale),\n output,\n is_deep_gemm_e8m0_used=use_deep_gemm_e8m0,\n )\n\n\ndef _fp8_gemm_nt_op_fake(\n q_input: torch.Tensor,\n input_scale: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n output: torch.Tensor,\n use_deep_gemm_e8m0: bool,\n) -> None:\n return None\n\n\ndirect_register_custom_op(\n \"fp8_gemm_nt_op\",\n _fp8_gemm_nt_op,\n mutates_args=[\"output\"],\n fake_impl=_fp8_gemm_nt_op_fake,\n)\n\n\n# TODO fix ROCm->Triton custom path:\n# https://github.com/vllm-project/vllm/issues/14397\nclass W8A8BlockFp8LinearOp:\n \"\"\"\n This class executes a Blocked FP8 linear layer using cutlass if supported\n and torch.scaled_mm otherwise.\n \"\"\"\n\n def __init__(\n self,\n weight_group_shape: GroupShape,\n act_quant_group_shape: GroupShape,\n cutlass_block_fp8_supported: bool = CUTLASS_BLOCK_FP8_SUPPORTED,\n use_aiter_and_is_supported: bool = False,\n ):\n self.weight_group_shape = weight_group_shape\n self.act_quant_group_shape = act_quant_group_shape\n self.is_deep_gemm_supported = is_deep_gemm_supported()\n self.is_hopper = current_platform.is_device_capability(90)\n self.use_deep_gemm_e8m0 = is_deep_gemm_e8m0_used()\n\n # Get the correct blockscale mul and input quant operations.\n # We can't use _dispatch_w8a8_blockscale_op to figure out if we want\n # to use deepgemm because we don't know the shape of weights (and\n # whether deepgemm supports it) at the init time.\n self.w8a8_blockscale_op, self.input_quant_op = (\n self._dispatch_w8a8_blockscale_op(\n cutlass_block_fp8_supported, use_aiter_and_is_supported\n )\n )\n self.deepgemm_input_quant_op = (\n QuantFP8(\n False,\n self.act_quant_group_shape,\n column_major_scales=True,\n use_ue8m0=self.use_deep_gemm_e8m0,\n )\n if self.is_deep_gemm_supported\n else None\n )\n\n def apply(\n self,\n input: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n input_scale: torch.Tensor | None = None,\n bias: torch.Tensor | None = None,\n ) -> torch.Tensor:\n assert input_scale is None\n # View input as 2D matrix for fp8 methods\n input_2d = input.view(-1, input.shape[-1])\n output_shape = [*input.shape[:-1], weight.shape[0]]\n output_dtype = input.dtype\n\n if should_use_deepgemm_for_fp8_linear(\n output_dtype, weight, self.is_deep_gemm_supported\n ):\n output = self._run_deepgemm(input_2d, weight, weight_scale)\n else:\n output = self.w8a8_blockscale_op(\n input_2d, weight, weight_scale, input_scale\n )\n\n if bias is not None:\n output = output + bias\n return output.to(dtype=input.dtype).view(*output_shape)\n\n def _run_deepgemm(\n self,\n input_2d: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n ) -> torch.Tensor:\n assert self.deepgemm_input_quant_op is not None\n q_input, input_scale = self.deepgemm_input_quant_op(input_2d)\n output = torch.empty(\n (q_input.shape[0], weight.shape[0]),\n dtype=torch.bfloat16,\n device=q_input.device,\n )\n torch.ops.vllm.fp8_gemm_nt_op(\n q_input, input_scale, weight, weight_scale, output, self.use_deep_gemm_e8m0\n )\n return output\n\n def _run_cutlass(\n self,\n input_2d: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n input_scale: torch.Tensor | None = None,\n ) -> torch.Tensor:\n assert input_scale is None\n assert self.input_quant_op is not None\n q_input, input_scale = self.input_quant_op(input_2d)\n if self.is_hopper:\n return torch.ops.vllm.padded_cutlass(\n q_input,\n weight,\n input_scale,\n weight_scale,\n list(self.weight_group_shape),\n input_2d.dtype,\n )\n else:\n return cutlass_scaled_mm(\n q_input,\n weight,\n input_scale,\n weight_scale,\n list(self.weight_group_shape),\n input_2d.dtype,\n )\n\n def _run_aiter(\n self,\n input_2d: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n input_scale: torch.Tensor | None = None,\n ) -> torch.Tensor:\n assert self.act_quant_group_shape == GroupShape(1, 128)\n\n n, k = weight.shape\n\n use_triton = (\n not current_platform.is_fp8_fnuz()\n and rocm_aiter_ops.is_triton_gemm_w8a8_tuned(n, k)\n )\n\n if use_triton:\n gemm_a8w8_blockscale_op = rocm_aiter_ops.triton_gemm_a8w8_blockscale\n else:\n gemm_a8w8_blockscale_op = rocm_aiter_ops.gemm_a8w8_blockscale\n\n if input_scale is not None:\n q_input = input_2d\n # MI350 case uses triton kernel\n elif use_triton:\n q_input, input_scale = per_token_group_quant_fp8(\n input_2d,\n self.act_quant_group_shape.col,\n column_major_scales=False,\n use_ue8m0=False,\n )\n # MI300 uses tuned AITER ASM/C++ kernel\n else:\n q_input, input_scale = rocm_aiter_ops.group_fp8_quant(input_2d)\n\n return gemm_a8w8_blockscale_op(\n q_input,\n weight,\n input_scale,\n weight_scale,\n list(self.weight_group_shape),\n output_dtype=input_2d.dtype,\n )\n\n def _run_triton(\n self,\n input_2d: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n input_scale: torch.Tensor | None = None,\n ) -> torch.Tensor:\n assert input_scale is None\n assert self.input_quant_op is not None\n q_input, input_scale = self.input_quant_op(input_2d)\n return torch.ops.vllm.w8a8_triton_block_scaled_mm_func(\n q_input,\n weight,\n input_scale,\n weight_scale,\n list(self.weight_group_shape),\n input_2d.dtype,\n )\n\n def _dispatch_w8a8_blockscale_op(\n self,\n use_cutlass: bool,\n use_aiter_and_is_supported: bool,\n ) -> tuple[\n Callable[\n [\n torch.Tensor,\n torch.Tensor,\n torch.Tensor,\n torch.Tensor | None,\n ],\n torch.Tensor,\n ],\n QuantFP8 | None,\n ]:\n if use_cutlass:\n return self._run_cutlass, (\n QuantFP8(\n False,\n self.act_quant_group_shape,\n column_major_scales=True,\n use_ue8m0=False,\n )\n )\n if use_aiter_and_is_supported:\n return self._run_aiter, None\n return self._run_triton, (\n QuantFP8(\n False,\n self.act_quant_group_shape,\n column_major_scales=False,\n use_ue8m0=False,\n )\n )\n\n\ndef input_to_float8(\n x: torch.Tensor, dtype: torch.dtype | None = None\n) -> tuple[torch.Tensor, torch.Tensor]:\n \"\"\"This function quantizes input values to float8 values \"\n \"with tensor-wise quantization.\"\"\"\n dtype = current_platform.fp8_dtype() if dtype is None else dtype\n finfo = torch.finfo(dtype)\n min_val, max_val = x.aminmax()\n amax = torch.maximum(min_val.abs(), max_val.abs()).clamp(min=1e-12)\n scale = finfo.max / amax\n x_scl_sat = (x * scale).clamp(min=finfo.min, max=finfo.max)\n return x_scl_sat.to(dtype).contiguous(), scale.float().reciprocal()\n\n\ndef block_quant_to_tensor_quant(\n x_q_block: torch.Tensor,\n x_s: torch.Tensor,\n) -> tuple[torch.Tensor, torch.Tensor]:\n \"\"\"This function converts block-wise quantization to tensor-wise\n quantization. The inputs are block-wise quantization tensor `x_q_block`,\n block-wise quantization scale and the block size.\n The outputs are tensor-wise quantization tensor and tensor-wise\n quantization scale. Note only float8 is supported for now.\n \"\"\"\n x_dq_block = group_broadcast(x_q_block, x_s)\n x_q_tensor, scale = input_to_float8(x_dq_block, dtype=x_q_block.dtype)\n return x_q_tensor, scale\n\n\n@triton.jit\ndef _per_token_group_quant_fp8(\n # Pointers to inputs and output\n y_ptr,\n y_q_ptr,\n y_s_ptr,\n group_size,\n # Num columns of y\n y_num_columns,\n y_row_stride,\n # Avoid to divide zero\n eps,\n # Information for float8\n fp8_min,\n fp8_max,\n use_ue8m0: tl.constexpr,\n # Meta-parameters\n BLOCK: tl.constexpr,\n):\n \"\"\"A Triton-accelerated function to perform per-token-group\n quantization on a tensor.\n This function converts the tensor values into float8 values.\n \"\"\"\n groups_per_row = y_num_columns // group_size\n\n # Map the program id to the row of X and Y it should compute.\n g_id = tl.program_id(0)\n row = g_id // groups_per_row\n row_g_id = g_id % groups_per_row\n\n # Ensure offset calculations use int64 to prevent overflow\n y_ptr_offset = (row.to(tl.int64) * y_row_stride) + (\n row_g_id.to(tl.int64) * group_size\n )\n y_ptr += y_ptr_offset\n\n y_q_ptr_offset = g_id.to(tl.int64) * group_size\n y_q_ptr += y_q_ptr_offset\n y_s_ptr += g_id\n\n cols = tl.arange(0, BLOCK) # N <= BLOCK\n mask = cols < group_size\n\n y = tl.load(y_ptr + cols, mask=mask, other=0.0).to(tl.float32)\n # Quant\n _absmax = tl.maximum(tl.max(tl.abs(y)), eps)\n scale_raw = _absmax / fp8_max\n y_s = tl.math.exp2(tl.ceil(tl.log2(scale_raw))) if use_ue8m0 else scale_raw\n y_q = tl.clamp(y / y_s, fp8_min, fp8_max).to(y_q_ptr.dtype.element_ty)\n\n tl.store(y_q_ptr + cols, y_q, mask=mask)\n tl.store(y_s_ptr, y_s)\n\n\n@triton.jit\ndef _silu_mul_per_token_group_quant_fp8_colmajor(\n y_ptr, # [M, N]\n y_q_ptr, # [M, N // 2]\n y_s_ptr, # [M, (N // 2) // GROUP_SIZE]\n M, # num tokens\n N, # intermediate size\n # Stride\n y_s_col_stride: tl.int64,\n # Information for float8\n eps,\n fp8_min,\n fp8_max,\n use_ue8m0: tl.constexpr,\n # Meta-parameters\n GROUP_SIZE: tl.constexpr,\n BLOCK_M: tl.constexpr,\n BLOCK_N: tl.constexpr,\n):\n # TODO(varun) : Add expert_ids so we may early-exit no-op thread blocks.\n \"\"\"\n Each thread block (BLOCK_N) computes [BLOCK_M, GROUP_SIZE] act-mul outputs. Then\n the thread block quantizes the [BLOCK_M, GROUP_SIZE] block of values and fills\n the outputs tensors at the right positions.\n \"\"\"\n\n pid_m = tl.program_id(0)\n pid_n = tl.program_id(1)\n N_2 = N // 2\n\n m_offset = pid_m * BLOCK_M\n n_offset = pid_n * BLOCK_N\n if m_offset >= M:\n return\n\n offs_n = tl.arange(0, BLOCK_N).to(tl.int64)\n offs_m = tl.arange(0, BLOCK_M).to(tl.int64)\n\n base_y_ptr = y_ptr + m_offset * N + n_offset\n\n act_in_ptrs = base_y_ptr + offs_m[:, None] * N + offs_n[None, :]\n\n act_in = tl.load(act_in_ptrs)\n mul_in = tl.load(act_in_ptrs + N_2)\n\n # silu & mul\n act_in = act_in.to(tl.float32)\n one_f32 = tl.cast(1, tl.float32)\n silu_out = (act_in / (one_f32 + tl.exp(-act_in))).to(y_ptr.dtype.element_ty)\n y = (silu_out * mul_in).to(tl.float32)\n\n # quant\n _absmax = tl.maximum(tl.max(tl.abs(y), axis=1), eps)\n scale_raw = _absmax / fp8_max\n y_s = tl.math.exp2(tl.ceil(tl.log2(scale_raw))) if use_ue8m0 else scale_raw\n y_s = tl.reshape(y_s, (BLOCK_M, 1))\n y_q = tl.clamp(y / y_s, fp8_min, fp8_max).to(y_q_ptr.dtype.element_ty)\n\n # store y_q\n base_y_q_ptr = y_q_ptr + m_offset * N_2 + n_offset\n y_q_ptrs = base_y_q_ptr + offs_m[:, None] * N_2 + offs_n[None, :]\n tl.store(y_q_ptrs, y_q)\n\n # store y_s\n group_id = n_offset // GROUP_SIZE\n base_y_s_ptr = y_s_ptr + group_id * y_s_col_stride + m_offset\n y_s_ptrs = base_y_s_ptr + offs_m\n y_s = tl.reshape(y_s, (BLOCK_M,))\n tl.store(y_s_ptrs, y_s)\n\n\ndef silu_mul_per_token_group_quant_fp8_colmajor(\n input: torch.Tensor, # [M, N]\n output: torch.Tensor | None = None, # [M, N // 2]\n use_ue8m0: bool | None = None,\n eps: float = 1e-10,\n):\n \"\"\"\n silu+mul + block-fp8 quant with group size 128.\n \"\"\"\n GROUP_SIZE = 128\n assert input.ndim == 2\n if output is not None:\n assert output.ndim == 2\n assert input.size(0) % GROUP_SIZE == 0\n assert input.size(1) % (GROUP_SIZE * 2) == 0\n\n if use_ue8m0 is None:\n use_ue8m0 = is_deep_gemm_e8m0_used()\n\n M, N = input.size()\n N_2 = N // 2\n\n if output is None:\n output = torch.empty((M, N_2), dtype=torch.float8_e4m3fn, device=input.device)\n\n output_scales = torch.empty(\n ((N_2 // GROUP_SIZE), M), dtype=torch.float32, device=input.device\n ).transpose(0, 1)\n\n BLOCK_M = 8\n BLOCK_N = GROUP_SIZE\n assert M % BLOCK_M == 0\n assert N_2 % BLOCK_N == 0\n\n finfo = torch.finfo(torch.float8_e4m3fn)\n fp8_min = finfo.min\n fp8_max = finfo.max\n\n # Force even division so we can avoid edgecases within the kernel.\n assert M % BLOCK_M == 0\n assert N_2 % BLOCK_N == 0\n grid = (M // BLOCK_M, N_2 // BLOCK_N)\n\n _silu_mul_per_token_group_quant_fp8_colmajor[grid](\n input,\n output,\n output_scales,\n M,\n N,\n output_scales.stride(-1),\n eps,\n fp8_min,\n fp8_max,\n use_ue8m0,\n GROUP_SIZE,\n BLOCK_M,\n BLOCK_N,\n )\n\n return output, output_scales\n\n\n@triton.jit\ndef _per_token_group_quant_fp8_colmajor(\n # Pointers to inputs and output\n y_ptr,\n y_q_ptr,\n y_s_ptr,\n group_size,\n # Num columns of y\n y_num_columns,\n y_row_stride,\n # Stride from one column to the next of y_s\n y_s_col_stride,\n # Avoid to divide zero\n eps,\n # Information for float8\n fp8_min,\n fp8_max,\n use_ue8m0: tl.constexpr,\n # Meta-parameters\n BLOCK: tl.constexpr,\n):\n \"\"\"A Triton-accelerated function to perform per-token-group\n quantization on a tensor.\n This function converts the tensor values into float8 values.\n \"\"\"\n groups_per_row = y_num_columns // group_size\n\n # Map the program id to the row of X and Y it should compute.\n g_id = tl.program_id(0)\n row = g_id // groups_per_row\n row_g_id = g_id % groups_per_row\n\n # Ensure offset calculations use int64 to prevent overflow\n y_ptr_offset = (row.to(tl.int64) * y_row_stride) + (\n row_g_id.to(tl.int64) * group_size\n )\n y_ptr += y_ptr_offset\n\n y_q_ptr_offset = g_id.to(tl.int64) * group_size\n y_q_ptr += y_q_ptr_offset\n\n # Convert g_id the flattened block coordinate to 2D so we can index\n # into the output y_scales matrix\n blocks_per_row = y_num_columns // group_size\n scale_col = g_id % blocks_per_row\n scale_row = g_id // blocks_per_row\n # Ensure offset calculation uses int64 for y_s_ptr\n y_s_ptr_offset = (scale_col.to(tl.int64) * y_s_col_stride) + scale_row.to(tl.int64)\n y_s_ptr += y_s_ptr_offset\n\n cols = tl.arange(0, BLOCK) # group_size <= BLOCK\n mask = cols < group_size\n\n y = tl.load(y_ptr + cols, mask=mask, other=0.0).to(tl.float32)\n # Quant\n _absmax = tl.maximum(tl.max(tl.abs(y)), eps)\n scale_raw = _absmax / fp8_max\n y_s = tl.math.exp2(tl.ceil(tl.log2(scale_raw))) if use_ue8m0 else scale_raw\n y_q = tl.clamp(y / y_s, fp8_min, fp8_max).to(y_q_ptr.dtype.element_ty)\n\n tl.store(y_q_ptr + cols, y_q, mask=mask)\n tl.store(y_s_ptr, y_s)\n\n\ndef per_token_group_quant_fp8(\n x: torch.Tensor,\n group_size: int,\n eps: float = 1e-10,\n dtype: torch.dtype | None = None,\n column_major_scales: bool = False,\n out_q: torch.Tensor | None = None,\n use_ue8m0: bool | None = None,\n) -> tuple[torch.Tensor, torch.Tensor]:\n \"\"\"Function to perform per-token-group quantization on an input tensor `x`.\n It converts the tensor values into signed float8 values and returns the\n quantized tensor along with the scaling factor used for quantization.\n Args:\n x: The input tensor with ndim >= 2.\n group_size: The group size used for quantization.\n eps: The minimum to avoid dividing zero.\n dtype: The dype of output tensor. Note that only `torch.float8_e4m3fn`\n is supported for now.\n column_major_scales: Outputs scales in column major.\n out_q: Optional output tensor. If not provided, function will create.\n Returns:\n tuple[torch.Tensor, torch.Tensor]: The quantized tensor and the\n scaling factor.\n \"\"\"\n if use_ue8m0 is None:\n use_ue8m0 = is_deep_gemm_e8m0_used()\n dtype = current_platform.fp8_dtype() if dtype is None else dtype\n assert x.shape[-1] % group_size == 0, (\n f\"the last dimension of `x` {x.shape[-1]} must be divisible \"\n f\"by `group_size` {group_size}\"\n )\n assert x.stride(-1) == 1, \"`x` groups must be contiguous\"\n\n finfo = torch.finfo(dtype)\n fp8_min = finfo.min\n fp8_max = finfo.max\n\n assert out_q is None or out_q.shape == x.shape\n x_q = out_q\n if x_q is None:\n x_q = torch.empty_like(x, device=x.device, dtype=dtype)\n\n # Allocate the scale tensor in either row- or column-major format.\n if column_major_scales:\n shape = (x.shape[-1] // group_size,) + x.shape[:-1]\n x_s = torch.empty(shape, device=x.device, dtype=torch.float32).permute(-1, -2)\n else:\n shape = x.shape[:-1] + (x.shape[-1] // group_size,)\n x_s = torch.empty(shape, device=x.device, dtype=torch.float32)\n\n # prefer CUDA kernel if available\n # TODO(bnell): this causes some fp8 moe test to fail.\n if current_platform.is_cuda() and x.is_contiguous():\n torch.ops._C.per_token_group_fp8_quant(\n x, x_q, x_s, group_size, eps, fp8_min, fp8_max, use_ue8m0\n )\n return x_q, x_s\n\n # TRITON FALLBACK\n M = x.numel() // group_size\n N = group_size\n BLOCK = triton.next_power_of_2(N)\n # heuristics for number of warps\n num_warps = min(max(BLOCK // 256, 1), 8)\n num_stages = 1\n if column_major_scales:\n _per_token_group_quant_fp8_colmajor[(M,)](\n x,\n x_q,\n x_s,\n group_size,\n x.shape[1],\n x.stride(0),\n x_s.stride(1),\n eps,\n fp8_min=fp8_min,\n fp8_max=fp8_max,\n use_ue8m0=use_ue8m0,\n BLOCK=BLOCK,\n num_warps=num_warps,\n num_stages=num_stages,\n )\n else:\n _per_token_group_quant_fp8[(M,)](\n x,\n x_q,\n x_s,\n group_size,\n x.shape[1],\n x.stride(0),\n eps,\n fp8_min=fp8_min,\n fp8_max=fp8_max,\n use_ue8m0=use_ue8m0,\n BLOCK=BLOCK,\n num_warps=num_warps,\n num_stages=num_stages,\n )\n\n return x_q, x_s\n\n\n@triton.jit\ndef _w8a8_triton_block_scaled_mm(\n # Pointers to inputs and output\n A,\n B,\n C,\n As,\n Bs,\n # Shape for matmul\n M,\n N,\n K,\n # Block size for block-wise quantization\n group_n,\n group_k,\n # Stride for inputs and output\n stride_am,\n stride_ak,\n stride_bk,\n stride_bn,\n stride_cm,\n stride_cn,\n stride_As_m,\n stride_As_k,\n stride_Bs_k,\n stride_Bs_n,\n # Meta-parameters\n BLOCK_SIZE_M: tl.constexpr,\n BLOCK_SIZE_N: tl.constexpr,\n BLOCK_SIZE_K: tl.constexpr,\n GROUP_SIZE_M: tl.constexpr,\n):\n \"\"\"Triton-accelerated function used to perform linear operations (dot\n product) on input tensors `A` and `B` with block-wise quantization, and\n store the result in output tensor `C`.\n \"\"\"\n\n pid = tl.program_id(axis=0)\n num_pid_m = tl.cdiv(M, BLOCK_SIZE_M)\n num_pid_n = tl.cdiv(N, BLOCK_SIZE_N)\n num_pid_in_group = GROUP_SIZE_M * num_pid_n\n group_id = pid // num_pid_in_group\n first_pid_m = group_id * GROUP_SIZE_M\n group_size_m = min(num_pid_m - first_pid_m, GROUP_SIZE_M)\n pid_m = first_pid_m + (pid % group_size_m)\n pid_n = (pid % num_pid_in_group) // group_size_m\n\n offs_am = (pid_m * BLOCK_SIZE_M + tl.arange(0, BLOCK_SIZE_M)) % M\n offs_bn = (pid_n * BLOCK_SIZE_N + tl.arange(0, BLOCK_SIZE_N)) % N\n offs_k = tl.arange(0, BLOCK_SIZE_K)\n a_ptrs = A + (offs_am[:, None] * stride_am + offs_k[None, :] * stride_ak)\n b_ptrs = B + (offs_k[:, None] * stride_bk + offs_bn[None, :] * stride_bn)\n\n As_ptrs = As + offs_am * stride_As_m\n offs_bsn = offs_bn // group_n\n Bs_ptrs = Bs + offs_bsn * stride_Bs_n\n\n accumulator = tl.zeros((BLOCK_SIZE_M, BLOCK_SIZE_N), dtype=tl.float32)\n for k in range(0, tl.cdiv(K, BLOCK_SIZE_K)):\n a = tl.load(a_ptrs, mask=offs_k[None, :] < K - k * BLOCK_SIZE_K, other=0.0)\n b = tl.load(b_ptrs, mask=offs_k[:, None] < K - k * BLOCK_SIZE_K, other=0.0)\n\n k_start = k * BLOCK_SIZE_K\n offs_ks = k_start // group_k\n a_s = tl.load(As_ptrs + offs_ks * stride_As_k)\n b_s = tl.load(Bs_ptrs + offs_ks * stride_Bs_k)\n\n accumulator += tl.dot(a, b) * a_s[:, None] * b_s[None, :]\n a_ptrs += BLOCK_SIZE_K * stride_ak\n b_ptrs += BLOCK_SIZE_K * stride_bk\n\n if C.dtype.element_ty == tl.bfloat16:\n c = accumulator.to(tl.bfloat16)\n elif C.dtype.element_ty == tl.float16:\n c = accumulator.to(tl.float16)\n else:\n c = accumulator.to(tl.float32)\n\n offs_cm = pid_m * BLOCK_SIZE_M + tl.arange(0, BLOCK_SIZE_M)\n offs_cn = pid_n * BLOCK_SIZE_N + tl.arange(0, BLOCK_SIZE_N)\n c_ptrs = C + stride_cm * offs_cm[:, None] + stride_cn * offs_cn[None, :]\n c_mask = (offs_cm[:, None] < M) & (offs_cn[None, :] < N)\n tl.store(c_ptrs, c, mask=c_mask)\n\n\n@functools.lru_cache\ndef get_w8a8_block_fp8_configs(\n N: int, K: int, block_n: int, block_k: int\n) -> dict[int, Any] | None:\n \"\"\"\n Return optimized configurations for the w8a8 block fp8 kernel.\n The return value will be a dictionary that maps an irregular grid of\n batch sizes to configurations of the w8a8 block fp8 kernel. To evaluate the\n kernel on a given batch size bs, the closest batch size in the grid should\n be picked and the associated configuration chosen to invoke the kernel.\n \"\"\"\n\n # First look up if an optimized configuration is available in the configs\n # directory\n device_name = current_platform.get_device_name().replace(\" \", \"_\")\n json_file_name = f\"N={N},K={K},device_name={device_name},dtype=fp8_w8a8,block_shape=[{block_n},{block_k}].json\" # noqa: E501\n\n config_file_path = os.path.join(\n os.path.dirname(os.path.realpath(__file__)), \"configs\", json_file_name\n )\n if os.path.exists(config_file_path):\n with open(config_file_path) as f:\n logger.info(\n \"Using configuration from %s for W8A8 Block FP8 kernel.\",\n config_file_path,\n )\n # If a configuration has been found, return it\n return {int(key): val for key, val in json.load(f).items()}\n\n # If no optimized configuration is available, we will use the default\n # configuration\n logger.warning(\n \"Using default W8A8 Block FP8 kernel config. Performance might \"\n \"be sub-optimal! Config file not found at %s\",\n config_file_path,\n )\n return None\n\n\ndef w8a8_triton_block_scaled_mm(\n A: torch.Tensor,\n B: torch.Tensor,\n As: torch.Tensor,\n Bs: torch.Tensor,\n block_size: list[int],\n output_dtype: torch.dtype = torch.float16,\n) -> torch.Tensor:\n \"\"\"This function performs matrix multiplication with block-wise\n quantization.\n It takes two input tensors `A` and `B` with scales `As` and `Bs`.\n The output is returned in the specified `output_dtype`.\n Args:\n A: The input tensor, e.g., activation.\n B: The input tensor, e.g., weight.\n As: The per-token-group quantization scale for `A`.\n Bs: The per-block quantization scale for `B`.\n block_size: The block size for per-block quantization. It should\n be 2-dim, e.g., [128, 128].\n output_dytpe: The dtype of the returned tensor.\n Returns:\n torch.Tensor: The result of matmul.\n \"\"\"\n assert len(block_size) == 2\n block_n, block_k = block_size[0], block_size[1]\n\n assert A.shape[-1] == B.shape[-1]\n assert A.shape[:-1] == As.shape[:-1] and A.is_contiguous()\n assert triton.cdiv(A.shape[-1], block_k) == As.shape[-1]\n M = A.numel() // A.shape[-1]\n\n assert B.ndim == 2 and Bs.ndim == 2\n N, K = B.shape\n assert triton.cdiv(N, block_n) == Bs.shape[0]\n assert triton.cdiv(K, block_k) == Bs.shape[1]\n\n C_shape = A.shape[:-1] + (N,)\n C = A.new_empty(C_shape, dtype=output_dtype)\n\n configs = get_w8a8_block_fp8_configs(N, K, block_size[0], block_size[1])\n if configs:\n # Get the optimal config if there is one\n config = configs[min(configs.keys(), key=lambda x: abs(x - M))]\n else:\n # Default config\n # Block-wise quant: BLOCK_SIZE_N must be divisible by block_size[0]\n # BLOCK_SIZE_K must be divisible by block_size[1]\n config = {\n \"BLOCK_SIZE_M\": 64,\n \"BLOCK_SIZE_N\": block_size[0],\n \"BLOCK_SIZE_K\": block_size[1],\n \"GROUP_SIZE_M\": 32,\n \"num_warps\": 4,\n \"num_stages\": 2,\n }\n\n def grid(META):\n return (\n triton.cdiv(M, META[\"BLOCK_SIZE_M\"]) * triton.cdiv(N, META[\"BLOCK_SIZE_N\"]),\n )\n\n _w8a8_triton_block_scaled_mm[grid](\n A,\n B,\n C,\n As,\n Bs,\n M,\n N,\n K,\n block_n,\n block_k,\n A.stride(-2),\n A.stride(-1),\n B.stride(1),\n B.stride(0),\n C.stride(-2),\n C.stride(-1),\n As.stride(-2),\n As.stride(-1),\n Bs.stride(1),\n Bs.stride(0),\n **config,\n )\n\n return C\n\n\ndef requant_weight_ue8m0_inplace(\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n block_size: Sequence[int] = (128, 128),\n) -> None:\n \"\"\"Re-quantise *weight* so that its per-block scaling factors are in the\n UE8M0 (power-of-two) format expected by the new DeepGEMM kernels inplace.\n\n Args:\n weight: Block-quantised weight tensor stored in `torch.float8_e4m3fn`.\n Expected shape `(..., M, K)`.\n weight_scale: Corresponding per-block scale tensor (`torch.float32`)\n with shape `(..., M // block_size[0], K // block_size[1])`.\n block_size: 2-element iterable `[block_m, block_k]` describing the\n block quantisation granularity.\n \"\"\"\n if weight.numel() == 0:\n return\n\n if weight.dtype != torch.float8_e4m3fn:\n raise ValueError(\n f\"Expected *weight* to be torch.float8_e4m3fn, got {weight.dtype} instead.\"\n )\n\n from vllm.utils.deep_gemm import per_block_cast_to_fp8\n\n block_m, block_k = int(block_size[0]), int(block_size[1])\n\n # Flatten leading dimensions so we can iterate over the last two dims.\n leading_shape = weight.shape[:-2]\n if len(leading_shape) == 0:\n w_view = weight.unsqueeze(0)\n s_view = weight_scale.unsqueeze(0)\n else:\n w_view = weight.reshape(-1, weight.shape[-2], weight.shape[-1])\n s_view = weight_scale.reshape(-1, *weight_scale.shape[-2:])\n\n num_mats = w_view.size(0)\n for idx in range(num_mats):\n w_q = w_view[idx]\n s_old = s_view[idx]\n\n # De-quantise with the *old* scaling factors (float32).\n m_cur, k_cur = w_q.shape\n s_float = s_old.to(torch.float32)\n # Expand scales along rows and cols by block size, then crop.\n s_exp_r = torch.repeat_interleave(s_float, block_m, dim=0)\n s_exp = torch.repeat_interleave(s_exp_r, block_k, dim=1)\n s_exp = s_exp[:m_cur, :k_cur]\n w_dq = w_q.to(torch.float32) * s_exp\n # Re-quantise using power-of-two scaling (UE8M0).\n w_requant, s_requant = per_block_cast_to_fp8(\n w_dq, [block_m, block_k], use_ue8m0=True\n )\n\n # Write back the results in-place.\n w_q.copy_(w_requant)\n s_old.copy_(s_requant)\n\n\ndef deepgemm_post_process_fp8_weight_block(\n wq: torch.Tensor, ws: torch.Tensor, quant_block_shape: tuple[int], use_e8m0: bool\n) -> tuple[torch.Tensor, torch.Tensor]:\n assert wq.dtype == torch.float8_e4m3fn, (\n \"Expected quantized tensor dtype \"\n f\"to be torch.float8_e4m3fn, got {wq.dtype} instead.\"\n )\n assert ws.dtype == torch.float32, (\n f\"Expected tensor scales dtype to be torch.float32, got {ws.dtype} instead\"\n )\n\n if use_e8m0:\n requant_weight_ue8m0_inplace(wq, ws, block_size=quant_block_shape)\n\n original_ndim = wq.ndim\n if wq.ndim == 2:\n assert ws.ndim == 2\n wq = wq.unsqueeze(0)\n ws = ws.unsqueeze(0)\n\n # From https://github.com/deepseek-ai/DeepGEMM/blob/c9f8b34dcdacc20aa746b786f983492c51072870/csrc/utils/layout.hpp#L46\n recipe = (1, 128, 128)\n\n # Ref : https://github.com/deepseek-ai/DeepGEMM/blob/c9f8b34dcdacc20aa746b786f983492c51072870/csrc/apis/gemm.hpp\n # DeepGemm uses the `transform_sf_into_required_layout` function to\n # represent scales in the correct format.\n dg_ws = transform_sf_into_required_layout(\n sf=ws,\n mn=wq.size(1),\n k=wq.size(2),\n recipe=recipe,\n num_groups=wq.size(0),\n # is the scale factors for A in (Refers to the argument A in A @ B).\n # Weights are B.\n is_sfa=False,\n )\n\n if original_ndim == 2:\n wq = wq.squeeze(0)\n dg_ws = dg_ws.squeeze(0)\n\n return wq, dg_ws\n\n\ndef _maybe_pad_fp8_weight(weight: torch.Tensor) -> torch.Tensor:\n \"\"\"Pad the weight tensor. This is an optimization on ROCm platform, which\n can benefit from tensors located far enough from one another in memory\"\"\"\n if (\n envs.VLLM_ROCM_FP8_PADDING\n and current_platform.is_rocm()\n and weight.stride(-1) == 1\n and (weight.stride(-2) * weight.element_size()) % 512 == 0\n ):\n num_pad = 256 // weight.element_size()\n import torch.nn.functional as F\n\n weight = F.pad(weight, (0, num_pad), \"constant\", 0)[..., :-num_pad]\n torch.cuda.empty_cache()\n return weight\n\n\ndef validate_fp8_block_shape(\n layer: torch.nn.Module,\n input_size: int,\n output_size: int,\n input_size_per_partition: int,\n output_partition_sizes: list[int],\n block_size: list[int],\n) -> None:\n \"\"\"Validate block quantization shapes for tensor parallelism.\"\"\"\n from vllm.distributed import get_tensor_model_parallel_world_size\n\n tp_size = getattr(layer, \"tp_size\", get_tensor_model_parallel_world_size())\n block_n, block_k = block_size[0], block_size[1]\n\n # Required by row parallel\n if (\n tp_size > 1\n and input_size // input_size_per_partition == tp_size\n and input_size_per_partition % block_k != 0\n ):\n raise ValueError(\n f\"Weight input_size_per_partition = {input_size_per_partition} \"\n f\"is not divisible by weight quantization block_k = {block_k}.\"\n )\n\n # Required by column parallel or enabling merged weights\n is_tp_split = tp_size > 1 and output_size // sum(output_partition_sizes) == tp_size\n is_merged_gemm = len(output_partition_sizes) > 1\n if is_tp_split or is_merged_gemm:\n sizes_to_check = output_partition_sizes\n if not is_tp_split and is_merged_gemm:\n # In case of merged matrices, we allow the last\n # matrix to not be a multiple of block size\n sizes_to_check = output_partition_sizes[:-1]\n for output_partition_size in sizes_to_check:\n if output_partition_size % block_n != 0:\n raise ValueError(\n f\"Weight output_partition_size = \"\n f\"{output_partition_size} is not divisible by \"\n f\"weight quantization block_n = {block_n}.\"\n )\n\n\ndef create_fp8_weight_parameter(\n output_size_per_partition: int,\n input_size_per_partition: int,\n weight_loader: Callable | None,\n) -> torch.nn.Parameter:\n \"\"\"Create FP8 weight parameter.\"\"\"\n from vllm.model_executor.parameter import ModelWeightParameter\n\n return ModelWeightParameter(\n data=torch.empty(\n output_size_per_partition,\n input_size_per_partition,\n dtype=torch.float8_e4m3fn,\n ),\n input_dim=1,\n output_dim=0,\n weight_loader=weight_loader,\n )\n\n\ndef create_fp8_scale_parameter(\n parameter_type: torch.nn.Parameter,\n output_partition_sizes: list[int],\n input_size_per_partition: int,\n block_size: list[int] | None,\n weight_loader: Callable | None,\n) -> torch.nn.Parameter:\n \"\"\"Create scale parameter based on quantization strategy.\"\"\"\n if parameter_type == ChannelQuantScaleParameter:\n scale = parameter_type(\n data=torch.empty((sum(output_partition_sizes), 1), dtype=torch.float32),\n output_dim=0,\n weight_loader=weight_loader,\n )\n elif parameter_type == BlockQuantScaleParameter:\n assert block_size is not None\n block_n, block_k = block_size[0], block_size[1]\n output_size_per_partition = sum(output_partition_sizes)\n scale = parameter_type(\n data=torch.empty(\n (output_size_per_partition + block_n - 1) // block_n,\n (input_size_per_partition + block_k - 1) // block_k,\n dtype=torch.float32,\n ),\n input_dim=1,\n output_dim=0,\n weight_loader=weight_loader,\n )\n elif parameter_type == PerTensorScaleParameter:\n scale = parameter_type(\n data=torch.empty(len(output_partition_sizes), dtype=torch.float32),\n weight_loader=weight_loader,\n )\n else:\n raise ValueError(f\"Unknown parameter type: {parameter_type}\")\n\n scale[:] = torch.finfo(torch.float32).min\n return scale\n\n\ndef create_fp8_input_scale(\n output_partition_sizes: list[int], weight_loader: Callable | None\n) -> torch.nn.Parameter:\n \"\"\"Create input scale parameter for static activation quantization.\"\"\"\n from vllm.model_executor.parameter import PerTensorScaleParameter\n\n scale = PerTensorScaleParameter(\n data=torch.empty(len(output_partition_sizes), dtype=torch.float32),\n weight_loader=weight_loader,\n )\n scale[:] = torch.finfo(torch.float32).min\n return scale\n\n\ndef process_fp8_weight_tensor_strategy(\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n logical_widths: list[int],\n input_scale: torch.Tensor | None = None,\n) -> tuple[torch.Tensor, torch.Tensor, torch.Tensor | None]:\n \"\"\"Process weights for tensor-wise quantization strategy.\"\"\"\n from vllm.model_executor.layers.quantization.utils.w8a8_utils import (\n normalize_e4m3fn_to_e4m3fnuz,\n requantize_with_max_scale,\n )\n\n if current_platform.is_fp8_fnuz():\n weight, weight_scale, input_scale = normalize_e4m3fn_to_e4m3fnuz(\n weight=weight, weight_scale=weight_scale, input_scale=input_scale\n )\n\n # Requantize with max scale\n weight_scale, weight = requantize_with_max_scale(\n weight=weight,\n weight_scale=weight_scale,\n logical_widths=logical_widths,\n )\n\n weight = _maybe_pad_fp8_weight(weight)\n return weight, weight_scale, input_scale\n\n\ndef process_fp8_weight_channel_strategy(\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n input_scale: torch.Tensor | None = None,\n) -> tuple[torch.Tensor, torch.Tensor, torch.Tensor | None]:\n \"\"\"Process weights for channel-wise quantization strategy.\"\"\"\n from vllm.model_executor.layers.quantization.utils.w8a8_utils import (\n normalize_e4m3fn_to_e4m3fnuz,\n )\n\n if current_platform.is_fp8_fnuz():\n weight, weight_scale, input_scale = normalize_e4m3fn_to_e4m3fnuz(\n weight=weight, weight_scale=weight_scale, input_scale=input_scale\n )\n\n return weight, weight_scale, input_scale\n\n\ndef process_fp8_weight_block_strategy(\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n) -> tuple[torch.Tensor, torch.Tensor]:\n \"\"\"Process weights for block-wise quantization strategy.\"\"\"\n from vllm.model_executor.layers.quantization.utils.w8a8_utils import (\n normalize_e4m3fn_to_e4m3fnuz,\n )\n\n if current_platform.is_fp8_fnuz():\n weight, weight_scale, _ = normalize_e4m3fn_to_e4m3fnuz(\n weight=weight, weight_scale=weight_scale\n )\n\n weight = _maybe_pad_fp8_weight(weight)\n return weight, weight_scale\n\n\ndef maybe_post_process_fp8_weight_block(layer: torch.nn.Module):\n assert layer.weight_block_size is not None\n\n from vllm.utils.deep_gemm import (\n is_deep_gemm_e8m0_used,\n should_use_deepgemm_for_fp8_linear,\n )\n\n # On Blackwell or Hopper, if E8M0 for DeepGemm is used, we need to\n # requantize the weight and input to the specific scale\n # at the same time.\n should_use_deepgemm = should_use_deepgemm_for_fp8_linear(\n layer.orig_dtype, layer.weight\n )\n if should_use_deepgemm:\n dg_weight, dg_weight_scale = deepgemm_post_process_fp8_weight_block(\n wq=layer.weight.data,\n ws=layer.weight_scale.data,\n quant_block_shape=tuple(layer.weight_block_size),\n use_e8m0=is_deep_gemm_e8m0_used(),\n )\n layer.weight = torch.nn.Parameter(dg_weight, requires_grad=False)\n layer.weight_scale = torch.nn.Parameter(dg_weight_scale, requires_grad=False)\n\n\ndef expert_weight_is_col_major(x: torch.Tensor) -> bool:\n assert x.dim() == 3\n b, m, n = x.shape\n return x.stride(0) == m * n and x.stride(1) == 1 and x.stride(2) == m\n"},"diff":{"kind":"string","value":"--- vllm/model_executor/layers/quantization/utils/fp8_utils.py\n+++ vllm/model_executor/layers/quantization/utils/fp8_utils.py\n@@ -490,6 +490,139 @@\n \n tl.store(y_q_ptr + cols, y_q, mask=mask)\n tl.store(y_s_ptr, y_s)\n+\n+\n+@triton.jit\n+def _silu_mul_per_token_group_quant_fp8_colmajor(\n+ y_ptr, # [M, N]\n+ y_q_ptr, # [M, N // 2]\n+ y_s_ptr, # [M, (N // 2) // GROUP_SIZE]\n+ M, # num tokens\n+ N, # intermediate size\n+ # Stride\n+ y_s_col_stride: tl.int64,\n+ # Information for float8\n+ eps,\n+ fp8_min,\n+ fp8_max,\n+ use_ue8m0: tl.constexpr,\n+ # Meta-parameters\n+ GROUP_SIZE: tl.constexpr,\n+ BLOCK_M: tl.constexpr,\n+ BLOCK_N: tl.constexpr,\n+):\n+ # TODO(varun) : Add expert_ids so we may early-exit no-op thread blocks.\n+ \"\"\"\n+ Each thread block (BLOCK_N) computes [BLOCK_M, GROUP_SIZE] act-mul outputs. Then\n+ the thread block quantizes the [BLOCK_M, GROUP_SIZE] block of values and fills\n+ the outputs tensors at the right positions.\n+ \"\"\"\n+\n+ pid_m = tl.program_id(0)\n+ pid_n = tl.program_id(1)\n+ N_2 = N // 2\n+\n+ m_offset = pid_m * BLOCK_M\n+ n_offset = pid_n * BLOCK_N\n+ if m_offset >= M:\n+ return\n+\n+ offs_n = tl.arange(0, BLOCK_N).to(tl.int64)\n+ offs_m = tl.arange(0, BLOCK_M).to(tl.int64)\n+\n+ base_y_ptr = y_ptr + m_offset * N + n_offset\n+\n+ act_in_ptrs = base_y_ptr + offs_m[:, None] * N + offs_n[None, :]\n+\n+ act_in = tl.load(act_in_ptrs)\n+ mul_in = tl.load(act_in_ptrs + N_2)\n+\n+ # silu & mul\n+ act_in = act_in.to(tl.float32)\n+ one_f32 = tl.cast(1, tl.float32)\n+ silu_out = (act_in / (one_f32 + tl.exp(-act_in))).to(y_ptr.dtype.element_ty)\n+ y = (silu_out * mul_in).to(tl.float32)\n+\n+ # quant\n+ _absmax = tl.maximum(tl.max(tl.abs(y), axis=1), eps)\n+ scale_raw = _absmax / fp8_max\n+ y_s = tl.math.exp2(tl.ceil(tl.log2(scale_raw))) if use_ue8m0 else scale_raw\n+ y_s = tl.reshape(y_s, (BLOCK_M, 1))\n+ y_q = tl.clamp(y / y_s, fp8_min, fp8_max).to(y_q_ptr.dtype.element_ty)\n+\n+ # store y_q\n+ base_y_q_ptr = y_q_ptr + m_offset * N_2 + n_offset\n+ y_q_ptrs = base_y_q_ptr + offs_m[:, None] * N_2 + offs_n[None, :]\n+ tl.store(y_q_ptrs, y_q)\n+\n+ # store y_s\n+ group_id = n_offset // GROUP_SIZE\n+ base_y_s_ptr = y_s_ptr + group_id * y_s_col_stride + m_offset\n+ y_s_ptrs = base_y_s_ptr + offs_m\n+ y_s = tl.reshape(y_s, (BLOCK_M,))\n+ tl.store(y_s_ptrs, y_s)\n+\n+\n+def silu_mul_per_token_group_quant_fp8_colmajor(\n+ input: torch.Tensor, # [M, N]\n+ output: torch.Tensor | None = None, # [M, N // 2]\n+ use_ue8m0: bool | None = None,\n+ eps: float = 1e-10,\n+):\n+ \"\"\"\n+ silu+mul + block-fp8 quant with group size 128.\n+ \"\"\"\n+ GROUP_SIZE = 128\n+ assert input.ndim == 2\n+ if output is not None:\n+ assert output.ndim == 2\n+ assert input.size(0) % GROUP_SIZE == 0\n+ assert input.size(1) % (GROUP_SIZE * 2) == 0\n+\n+ if use_ue8m0 is None:\n+ use_ue8m0 = is_deep_gemm_e8m0_used()\n+\n+ M, N = input.size()\n+ N_2 = N // 2\n+\n+ if output is None:\n+ output = torch.empty((M, N_2), dtype=torch.float8_e4m3fn, device=input.device)\n+\n+ output_scales = torch.empty(\n+ ((N_2 // GROUP_SIZE), M), dtype=torch.float32, device=input.device\n+ ).transpose(0, 1)\n+\n+ BLOCK_M = 8\n+ BLOCK_N = GROUP_SIZE\n+ assert M % BLOCK_M == 0\n+ assert N_2 % BLOCK_N == 0\n+\n+ finfo = torch.finfo(torch.float8_e4m3fn)\n+ fp8_min = finfo.min\n+ fp8_max = finfo.max\n+\n+ # Force even division so we can avoid edgecases within the kernel.\n+ assert M % BLOCK_M == 0\n+ assert N_2 % BLOCK_N == 0\n+ grid = (M // BLOCK_M, N_2 // BLOCK_N)\n+\n+ _silu_mul_per_token_group_quant_fp8_colmajor[grid](\n+ input,\n+ output,\n+ output_scales,\n+ M,\n+ N,\n+ output_scales.stride(-1),\n+ eps,\n+ fp8_min,\n+ fp8_max,\n+ use_ue8m0,\n+ GROUP_SIZE,\n+ BLOCK_M,\n+ BLOCK_N,\n+ )\n+\n+ return output, output_scales\n \n \n @triton.jit"},"lines_added":{"kind":"number","value":133,"string":"133"},"lines_removed":{"kind":"number","value":0,"string":"0"},"files_in_commit":{"kind":"number","value":2,"string":"2"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this triton kernel file from vllm (vllm/model_executor/layers/quantization/utils/fp8_utils.py).\n\nGoal: [Performance][DP/EP] Add silu_mul_per_token_group_quant_fp8_colmajor kernel\nTarget hardware: unspecified\nTarget models: unspecified\n\nCurrent file:\n```python\n# SPDX-License-Identifier: Apache-2.0\n# SPDX-FileCopyrightText: Copyright contributors to the vLLM project\n\n# Adapted from https://github.com/sgl-project/sglang/pull/2575\nimport functools\nimport json\nimport os\nfrom collections.abc import Callable, Sequence\nfrom typing import Any\n\nimport torch\n\nimport vllm.envs as envs\nfrom vllm import _custom_ops as ops\nfrom vllm._aiter_ops import rocm_aiter_ops\nfrom vllm.logger import init_logger\nfrom vllm.model_executor.layers.quantization.input_quant_fp8 import QuantFP8\nfrom vllm.model_executor.layers.quantization.utils.quant_utils import (\n GroupShape,\n group_broadcast,\n)\nfrom vllm.model_executor.layers.quantization.utils.w8a8_utils import (\n CUTLASS_BLOCK_FP8_SUPPORTED,\n)\nfrom vllm.model_executor.parameter import (\n BlockQuantScaleParameter,\n ChannelQuantScaleParameter,\n PerTensorScaleParameter,\n)\nfrom vllm.platforms import current_platform\nfrom vllm.triton_utils import tl, triton\nfrom vllm.utils.deep_gemm import (\n fp8_gemm_nt,\n is_deep_gemm_e8m0_used,\n is_deep_gemm_supported,\n should_use_deepgemm_for_fp8_linear,\n transform_sf_into_required_layout,\n)\nfrom vllm.utils.torch_utils import direct_register_custom_op\n\nlogger = init_logger(__name__)\n\n\ndef is_fp8(x: torch.dtype | torch.Tensor) -> bool:\n if isinstance(x, torch.Tensor):\n x = x.dtype\n return x == torch.float8_e4m3fn or x == torch.float8_e4m3fnuz\n\n\n# We need to pass in the is_hopper flag as argument because the function\n# current_platform.is_device_capability() is not supported by Torch compiler.\ndef cutlass_scaled_mm(\n A: torch.Tensor,\n B: torch.Tensor,\n As: torch.Tensor,\n Bs: torch.Tensor,\n block_size: list[int],\n output_dtype: torch.dtype = torch.float16,\n) -> torch.Tensor:\n return ops.cutlass_scaled_mm(\n A,\n B.T,\n out_dtype=output_dtype,\n scale_a=As,\n scale_b=Bs.T,\n )\n\n\n# TODO we should be able to change the type of block_size to GroupShape\n# after we resolve GroupShape compilation issue\n# https://github.com/vllm-project/vllm/issues/25270\ndef _w8a8_triton_block_scaled_mm_func(\n qx: torch.Tensor,\n weight: torch.Tensor,\n x_scale: torch.Tensor,\n weight_scale: torch.Tensor,\n block_size: list[int],\n output_dtype: torch.dtype,\n) -> torch.Tensor:\n return w8a8_triton_block_scaled_mm(\n qx, weight, x_scale, weight_scale, block_size, output_dtype\n )\n\n\ndef _w8a8_triton_block_scaled_mm_fake(\n qx: torch.Tensor,\n weight: torch.Tensor,\n x_scale: torch.Tensor,\n weight_scale: torch.Tensor,\n block_size: list[int],\n output_dtype: torch.dtype,\n) -> torch.Tensor:\n return torch.empty(\n (qx.size(0), weight.size(0)), dtype=output_dtype, device=qx.device\n )\n\n\ndirect_register_custom_op(\n \"w8a8_triton_block_scaled_mm_func\",\n _w8a8_triton_block_scaled_mm_func,\n fake_impl=_w8a8_triton_block_scaled_mm_fake,\n)\n\n\ndef _padded_cutlass(\n qx: torch.Tensor,\n weight: torch.Tensor,\n x_scale: torch.Tensor,\n weight_scale: torch.Tensor,\n block_size: list[int],\n output_dtype: torch.dtype,\n) -> torch.Tensor:\n pad_multiple = 4\n dim = qx.shape[0]\n padded = (\n dim if dim % pad_multiple == 0 else dim + pad_multiple - (dim % pad_multiple)\n )\n\n has_pad = padded > dim\n\n if has_pad:\n padded_shape = [padded, *qx.shape[1:]]\n padded_qx = torch.zeros(padded_shape, device=qx.device, dtype=qx.dtype)\n padded_qx[0 : qx.shape[0], ...].copy_(qx)\n\n padded_x_scale_shape = [*x_scale.shape[1:], padded]\n padded_x_scale = torch.ones(\n padded_x_scale_shape, device=x_scale.device, dtype=x_scale.dtype\n ).permute(-1, -2)\n padded_x_scale[0 : x_scale.shape[0], ...].copy_(x_scale)\n\n output = cutlass_scaled_mm(\n padded_qx, weight, padded_x_scale, weight_scale, block_size, output_dtype\n )\n return output[0 : qx.shape[0], ...]\n else:\n return cutlass_scaled_mm(\n qx, weight, x_scale, weight_scale, block_size, output_dtype\n )\n\n\ndef _padded_cutlass_fake(\n qx: torch.Tensor,\n weight: torch.Tensor,\n x_scale: torch.Tensor,\n weight_scale: torch.Tensor,\n block_size: list[int],\n output_dtype: torch.dtype,\n) -> torch.Tensor:\n return torch.empty(\n (qx.size(0), weight.size(0)), dtype=output_dtype, device=qx.device\n )\n\n\ndirect_register_custom_op(\n \"padded_cutlass\",\n _padded_cutlass,\n fake_impl=_padded_cutlass_fake,\n)\n\n\ndef _fp8_gemm_nt_op(\n q_input: torch.Tensor,\n input_scale: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n output: torch.Tensor,\n use_deep_gemm_e8m0: bool,\n) -> None:\n fp8_gemm_nt(\n (q_input, input_scale),\n (weight, weight_scale),\n output,\n is_deep_gemm_e8m0_used=use_deep_gemm_e8m0,\n )\n\n\ndef _fp8_gemm_nt_op_fake(\n q_input: torch.Tensor,\n input_scale: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n output: torch.Tensor,\n use_deep_gemm_e8m0: bool,\n) -> None:\n return None\n\n\ndirect_register_custom_op(\n \"fp8_gemm_nt_op\",\n _fp8_gemm_nt_op,\n mutates_args=[\"output\"],\n fake_impl=_fp8_gemm_nt_op_fake,\n)\n\n\n# TODO fix ROCm->Triton custom path:\n# https://github.com/vllm-project/vllm/issues/14397\nclass W8A8BlockFp8LinearOp:\n \"\"\"\n This class executes a Blocked FP8 linear layer using cutlass if supported\n and torch.scaled_mm otherwise.\n \"\"\"\n\n def __init__(\n self,\n weight_group_shape: GroupShape,\n act_quant_group_shape: GroupShape,\n cutlass_block_fp8_supported: bool = CUTLASS_BLOCK_FP8_SUPPORTED,\n use_aiter_and_is_supported: bool = False,\n ):\n self.weight_group_shape = weight_group_shape\n self.act_quant_group_shape = act_quant_group_shape\n self.is_deep_gemm_supported = is_deep_gemm_supported()\n self.is_hopper = current_platform.is_device_capability(90)\n self.use_deep_gemm_e8m0 = is_deep_gemm_e8m0_used()\n\n # Get the correct blockscale mul and input quant operations.\n # We can't use _dispatch_w8a8_blockscale_op to figure out if we want\n # to use deepgemm because we don't know the shape of weights (and\n # whether deepgemm supports it) at the init time.\n self.w8a8_blockscale_op, self.input_quant_op = (\n self._dispatch_w8a8_blockscale_op(\n cutlass_block_fp8_supported, use_aiter_and_is_supported\n )\n )\n self.deepgemm_input_quant_op = (\n QuantFP8(\n False,\n self.act_quant_group_shape,\n column_major_scales=True,\n use_ue8m0=self.use_deep_gemm_e8m0,\n )\n if self.is_deep_gemm_supported\n else None\n )\n\n def apply(\n self,\n input: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n input_scale: torch.Tensor | None = None,\n bias: torch.Tensor | None = None,\n ) -> torch.Tensor:\n assert input_scale is None\n # View input as 2D matrix for fp8 methods\n input_2d = input.view(-1, input.shape[-1])\n output_shape = [*input.shape[:-1], weight.shape[0]]\n output_dtype = input.dtype\n\n if should_use_deepgemm_for_fp8_linear(\n output_dtype, weight, self.is_deep_gemm_supported\n ):\n output = self._run_deepgemm(input_2d, weight, weight_scale)\n else:\n output = self.w8a8_blockscale_op(\n input_2d, weight, weight_scale, input_scale\n )\n\n if bias is not None:\n output = output + bias\n return output.to(dtype=input.dtype).view(*output_shape)\n\n def _run_deepgemm(\n self,\n input_2d: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n ) -> torch.Tensor:\n assert self.deepgemm_input_quant_op is not None\n q_input, input_scale = self.deepgemm_input_quant_op(input_2d)\n output = torch.empty(\n (q_input.shape[0], weight.shape[0]),\n dtype=torch.bfloat16,\n device=q_input.device,\n )\n torch.ops.vllm.fp8_gemm_nt_op(\n q_input, input_scale, weight, weight_scale, output, self.use_deep_gemm_e8m0\n )\n return output\n\n def _run_cutlass(\n self,\n input_2d: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n input_scale: torch.Tensor | None = None,\n ) -> torch.Tensor:\n assert input_scale is None\n assert self.input_quant_op is not None\n q_input, input_scale = self.input_quant_op(input_2d)\n if self.is_hopper:\n return torch.ops.vllm.padded_cutlass(\n q_input,\n weight,\n input_scale,\n weight_scale,\n list(self.weight_group_shape),\n input_2d.dtype,\n )\n else:\n return cutlass_scaled_mm(\n q_input,\n weight,\n input_scale,\n weight_scale,\n list(self.weight_group_shape),\n input_2d.dtype,\n )\n\n def _run_aiter(\n self,\n input_2d: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n input_scale: torch.Tensor | None = None,\n ) -> torch.Tensor:\n assert self.act_quant_group_shape == GroupShape(1, 128)\n\n n, k = weight.shape\n\n use_triton = (\n not current_platform.is_fp8_fnuz()\n and rocm_aiter_ops.is_triton_gemm_w8a8_tuned(n, k)\n )\n\n if use_triton:\n gemm_a8w8_blockscale_op = rocm_aiter_ops.triton_gemm_a8w8_blockscale\n else:\n gemm_a8w8_blockscale_op = rocm_aiter_ops.gemm_a8w8_blockscale\n\n if input_scale is not None:\n q_input = input_2d\n # MI350 case uses triton kernel\n elif use_triton:\n q_input, input_scale = per_token_group_quant_fp8(\n input_2d,\n self.act_quant_group_shape.col,\n column_major_scales=False,\n use_ue8m0=False,\n )\n # MI300 uses tuned AITER ASM/C++ kernel\n else:\n q_input, input_scale = rocm_aiter_ops.group_fp8_quant(input_2d)\n\n return gemm_a8w8_blockscale_op(\n q_input,\n weight,\n input_scale,\n weight_scale,\n list(self.weight_group_shape),\n output_dtype=input_2d.dtype,\n )\n\n def _run_triton(\n self,\n input_2d: torch.Tensor,\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n input_scale: torch.Tensor | None = None,\n ) -> torch.Tensor:\n assert input_scale is None\n assert self.input_quant_op is not None\n q_input, input_scale = self.input_quant_op(input_2d)\n return torch.ops.vllm.w8a8_triton_block_scaled_mm_func(\n q_input,\n weight,\n input_scale,\n weight_scale,\n list(self.weight_group_shape),\n input_2d.dtype,\n )\n\n def _dispatch_w8a8_blockscale_op(\n self,\n use_cutlass: bool,\n use_aiter_and_is_supported: bool,\n ) -> tuple[\n Callable[\n [\n torch.Tensor,\n torch.Tensor,\n torch.Tensor,\n torch.Tensor | None,\n ],\n torch.Tensor,\n ],\n QuantFP8 | None,\n ]:\n if use_cutlass:\n return self._run_cutlass, (\n QuantFP8(\n False,\n self.act_quant_group_shape,\n column_major_scales=True,\n use_ue8m0=False,\n )\n )\n if use_aiter_and_is_supported:\n return self._run_aiter, None\n return self._run_triton, (\n QuantFP8(\n False,\n self.act_quant_group_shape,\n column_major_scales=False,\n use_ue8m0=False,\n )\n )\n\n\ndef input_to_float8(\n x: torch.Tensor, dtype: torch.dtype | None = None\n) -> tuple[torch.Tensor, torch.Tensor]:\n \"\"\"This function quantizes input values to float8 values \"\n \"with tensor-wise quantization.\"\"\"\n dtype = current_platform.fp8_dtype() if dtype is None else dtype\n finfo = torch.finfo(dtype)\n min_val, max_val = x.aminmax()\n amax = torch.maximum(min_val.abs(), max_val.abs()).clamp(min=1e-12)\n scale = finfo.max / amax\n x_scl_sat = (x * scale).clamp(min=finfo.min, max=finfo.max)\n return x_scl_sat.to(dtype).contiguous(), scale.float().reciprocal()\n\n\ndef block_quant_to_tensor_quant(\n x_q_block: torch.Tensor,\n x_s: torch.Tensor,\n) -> tuple[torch.Tensor, torch.Tensor]:\n \"\"\"This function converts block-wise quantization to tensor-wise\n quantization. The inputs are block-wise quantization tensor `x_q_block`,\n block-wise quantization scale and the block size.\n The outputs are tensor-wise quantization tensor and tensor-wise\n quantization scale. Note only float8 is supported for now.\n \"\"\"\n x_dq_block = group_broadcast(x_q_block, x_s)\n x_q_tensor, scale = input_to_float8(x_dq_block, dtype=x_q_block.dtype)\n return x_q_tensor, scale\n\n\n@triton.jit\ndef _per_token_group_quant_fp8(\n # Pointers to inputs and output\n y_ptr,\n y_q_ptr,\n y_s_ptr,\n group_size,\n # Num columns of y\n y_num_columns,\n y_row_stride,\n # Avoid to divide zero\n eps,\n # Information for float8\n fp8_min,\n fp8_max,\n use_ue8m0: tl.constexpr,\n # Meta-parameters\n BLOCK: tl.constexpr,\n):\n \"\"\"A Triton-accelerated function to perform per-token-group\n quantization on a tensor.\n This function converts the tensor values into float8 values.\n \"\"\"\n groups_per_row = y_num_columns // group_size\n\n # Map the program id to the row of X and Y it should compute.\n g_id = tl.program_id(0)\n row = g_id // groups_per_row\n row_g_id = g_id % groups_per_row\n\n # Ensure offset calculations use int64 to prevent overflow\n y_ptr_offset = (row.to(tl.int64) * y_row_stride) + (\n row_g_id.to(tl.int64) * group_size\n )\n y_ptr += y_ptr_offset\n\n y_q_ptr_offset = g_id.to(tl.int64) * group_size\n y_q_ptr += y_q_ptr_offset\n y_s_ptr += g_id\n\n cols = tl.arange(0, BLOCK) # N <= BLOCK\n mask = cols < group_size\n\n y = tl.load(y_ptr + cols, mask=mask, other=0.0).to(tl.float32)\n # Quant\n _absmax = tl.maximum(tl.max(tl.abs(y)), eps)\n scale_raw = _absmax / fp8_max\n y_s = tl.math.exp2(tl.ceil(tl.log2(scale_raw))) if use_ue8m0 else scale_raw\n y_q = tl.clamp(y / y_s, fp8_min, fp8_max).to(y_q_ptr.dtype.element_ty)\n\n tl.store(y_q_ptr + cols, y_q, mask=mask)\n tl.store(y_s_ptr, y_s)\n\n\n@triton.jit\ndef _per_token_group_quant_fp8_colmajor(\n # Pointers to inputs and output\n y_ptr,\n y_q_ptr,\n y_s_ptr,\n group_size,\n # Num columns of y\n y_num_columns,\n y_row_stride,\n # Stride from one column to the next of y_s\n y_s_col_stride,\n # Avoid to divide zero\n eps,\n # Information for float8\n fp8_min,\n fp8_max,\n use_ue8m0: tl.constexpr,\n # Meta-parameters\n BLOCK: tl.constexpr,\n):\n \"\"\"A Triton-accelerated function to perform per-token-group\n quantization on a tensor.\n This function converts the tensor values into float8 values.\n \"\"\"\n groups_per_row = y_num_columns // group_size\n\n # Map the program id to the row of X and Y it should compute.\n g_id = tl.program_id(0)\n row = g_id // groups_per_row\n row_g_id = g_id % groups_per_row\n\n # Ensure offset calculations use int64 to prevent overflow\n y_ptr_offset = (row.to(tl.int64) * y_row_stride) + (\n row_g_id.to(tl.int64) * group_size\n )\n y_ptr += y_ptr_offset\n\n y_q_ptr_offset = g_id.to(tl.int64) * group_size\n y_q_ptr += y_q_ptr_offset\n\n # Convert g_id the flattened block coordinate to 2D so we can index\n # into the output y_scales matrix\n blocks_per_row = y_num_columns // group_size\n scale_col = g_id % blocks_per_row\n scale_row = g_id // blocks_per_row\n # Ensure offset calculation uses int64 for y_s_ptr\n y_s_ptr_offset = (scale_col.to(tl.int64) * y_s_col_stride) + scale_row.to(tl.int64)\n y_s_ptr += y_s_ptr_offset\n\n cols = tl.arange(0, BLOCK) # group_size <= BLOCK\n mask = cols < group_size\n\n y = tl.load(y_ptr + cols, mask=mask, other=0.0).to(tl.float32)\n # Quant\n _absmax = tl.maximum(tl.max(tl.abs(y)), eps)\n scale_raw = _absmax / fp8_max\n y_s = tl.math.exp2(tl.ceil(tl.log2(scale_raw))) if use_ue8m0 else scale_raw\n y_q = tl.clamp(y / y_s, fp8_min, fp8_max).to(y_q_ptr.dtype.element_ty)\n\n tl.store(y_q_ptr + cols, y_q, mask=mask)\n tl.store(y_s_ptr, y_s)\n\n\ndef per_token_group_quant_fp8(\n x: torch.Tensor,\n group_size: int,\n eps: float = 1e-10,\n dtype: torch.dtype | None = None,\n column_major_scales: bool = False,\n out_q: torch.Tensor | None = None,\n use_ue8m0: bool | None = None,\n) -> tuple[torch.Tensor, torch.Tensor]:\n \"\"\"Function to perform per-token-group quantization on an input tensor `x`.\n It converts the tensor values into signed float8 values and returns the\n quantized tensor along with the scaling factor used for quantization.\n Args:\n x: The input tensor with ndim >= 2.\n group_size: The group size used for quantization.\n eps: The minimum to avoid dividing zero.\n dtype: The dype of output tensor. Note that only `torch.float8_e4m3fn`\n is supported for now.\n column_major_scales: Outputs scales in column major.\n out_q: Optional output tensor. If not provided, function will create.\n Returns:\n tuple[torch.Tensor, torch.Tensor]: The quantized tensor and the\n scaling factor.\n \"\"\"\n if use_ue8m0 is None:\n use_ue8m0 = is_deep_gemm_e8m0_used()\n dtype = current_platform.fp8_dtype() if dtype is None else dtype\n assert x.shape[-1] % group_size == 0, (\n f\"the last dimension of `x` {x.shape[-1]} must be divisible \"\n f\"by `group_size` {group_size}\"\n )\n assert x.stride(-1) == 1, \"`x` groups must be contiguous\"\n\n finfo = torch.finfo(dtype)\n fp8_min = finfo.min\n fp8_max = finfo.max\n\n assert out_q is None or out_q.shape == x.shape\n x_q = out_q\n if x_q is None:\n x_q = torch.empty_like(x, device=x.device, dtype=dtype)\n\n # Allocate the scale tensor in either row- or column-major format.\n if column_major_scales:\n shape = (x.shape[-1] // group_size,) + x.shape[:-1]\n x_s = torch.empty(shape, device=x.device, dtype=torch.float32).permute(-1, -2)\n else:\n shape = x.shape[:-1] + (x.shape[-1] // group_size,)\n x_s = torch.empty(shape, device=x.device, dtype=torch.float32)\n\n # prefer CUDA kernel if available\n # TODO(bnell): this causes some fp8 moe test to fail.\n if current_platform.is_cuda() and x.is_contiguous():\n torch.ops._C.per_token_group_fp8_quant(\n x, x_q, x_s, group_size, eps, fp8_min, fp8_max, use_ue8m0\n )\n return x_q, x_s\n\n # TRITON FALLBACK\n M = x.numel() // group_size\n N = group_size\n BLOCK = triton.next_power_of_2(N)\n # heuristics for number of warps\n num_warps = min(max(BLOCK // 256, 1), 8)\n num_stages = 1\n if column_major_scales:\n _per_token_group_quant_fp8_colmajor[(M,)](\n x,\n x_q,\n x_s,\n group_size,\n x.shape[1],\n x.stride(0),\n x_s.stride(1),\n eps,\n fp8_min=fp8_min,\n fp8_max=fp8_max,\n use_ue8m0=use_ue8m0,\n BLOCK=BLOCK,\n num_warps=num_warps,\n num_stages=num_stages,\n )\n else:\n _per_token_group_quant_fp8[(M,)](\n x,\n x_q,\n x_s,\n group_size,\n x.shape[1],\n x.stride(0),\n eps,\n fp8_min=fp8_min,\n fp8_max=fp8_max,\n use_ue8m0=use_ue8m0,\n BLOCK=BLOCK,\n num_warps=num_warps,\n num_stages=num_stages,\n )\n\n return x_q, x_s\n\n\n@triton.jit\ndef _w8a8_triton_block_scaled_mm(\n # Pointers to inputs and output\n A,\n B,\n C,\n As,\n Bs,\n # Shape for matmul\n M,\n N,\n K,\n # Block size for block-wise quantization\n group_n,\n group_k,\n # Stride for inputs and output\n stride_am,\n stride_ak,\n stride_bk,\n stride_bn,\n stride_cm,\n stride_cn,\n stride_As_m,\n stride_As_k,\n stride_Bs_k,\n stride_Bs_n,\n # Meta-parameters\n BLOCK_SIZE_M: tl.constexpr,\n BLOCK_SIZE_N: tl.constexpr,\n BLOCK_SIZE_K: tl.constexpr,\n GROUP_SIZE_M: tl.constexpr,\n):\n \"\"\"Triton-accelerated function used to perform linear operations (dot\n product) on input tensors `A` and `B` with block-wise quantization, and\n store the result in output tensor `C`.\n \"\"\"\n\n pid = tl.program_id(axis=0)\n num_pid_m = tl.cdiv(M, BLOCK_SIZE_M)\n num_pid_n = tl.cdiv(N, BLOCK_SIZE_N)\n num_pid_in_group = GROUP_SIZE_M * num_pid_n\n group_id = pid // num_pid_in_group\n first_pid_m = group_id * GROUP_SIZE_M\n group_size_m = min(num_pid_m - first_pid_m, GROUP_SIZE_M)\n pid_m = first_pid_m + (pid % group_size_m)\n pid_n = (pid % num_pid_in_group) // group_size_m\n\n offs_am = (pid_m * BLOCK_SIZE_M + tl.arange(0, BLOCK_SIZE_M)) % M\n offs_bn = (pid_n * BLOCK_SIZE_N + tl.arange(0, BLOCK_SIZE_N)) % N\n offs_k = tl.arange(0, BLOCK_SIZE_K)\n a_ptrs = A + (offs_am[:, None] * stride_am + offs_k[None, :] * stride_ak)\n b_ptrs = B + (offs_k[:, None] * stride_bk + offs_bn[None, :] * stride_bn)\n\n As_ptrs = As + offs_am * stride_As_m\n offs_bsn = offs_bn // group_n\n Bs_ptrs = Bs + offs_bsn * stride_Bs_n\n\n accumulator = tl.zeros((BLOCK_SIZE_M, BLOCK_SIZE_N), dtype=tl.float32)\n for k in range(0, tl.cdiv(K, BLOCK_SIZE_K)):\n a = tl.load(a_ptrs, mask=offs_k[None, :] < K - k * BLOCK_SIZE_K, other=0.0)\n b = tl.load(b_ptrs, mask=offs_k[:, None] < K - k * BLOCK_SIZE_K, other=0.0)\n\n k_start = k * BLOCK_SIZE_K\n offs_ks = k_start // group_k\n a_s = tl.load(As_ptrs + offs_ks * stride_As_k)\n b_s = tl.load(Bs_ptrs + offs_ks * stride_Bs_k)\n\n accumulator += tl.dot(a, b) * a_s[:, None] * b_s[None, :]\n a_ptrs += BLOCK_SIZE_K * stride_ak\n b_ptrs += BLOCK_SIZE_K * stride_bk\n\n if C.dtype.element_ty == tl.bfloat16:\n c = accumulator.to(tl.bfloat16)\n elif C.dtype.element_ty == tl.float16:\n c = accumulator.to(tl.float16)\n else:\n c = accumulator.to(tl.float32)\n\n offs_cm = pid_m * BLOCK_SIZE_M + tl.arange(0, BLOCK_SIZE_M)\n offs_cn = pid_n * BLOCK_SIZE_N + tl.arange(0, BLOCK_SIZE_N)\n c_ptrs = C + stride_cm * offs_cm[:, None] + stride_cn * offs_cn[None, :]\n c_mask = (offs_cm[:, None] < M) & (offs_cn[None, :] < N)\n tl.store(c_ptrs, c, mask=c_mask)\n\n\n@functools.lru_cache\ndef get_w8a8_block_fp8_configs(\n N: int, K: int, block_n: int, block_k: int\n) -> dict[int, Any] | None:\n \"\"\"\n Return optimized configurations for the w8a8 block fp8 kernel.\n The return value will be a dictionary that maps an irregular grid of\n batch sizes to configurations of the w8a8 block fp8 kernel. To evaluate the\n kernel on a given batch size bs, the closest batch size in the grid should\n be picked and the associated configuration chosen to invoke the kernel.\n \"\"\"\n\n # First look up if an optimized configuration is available in the configs\n # directory\n device_name = current_platform.get_device_name().replace(\" \", \"_\")\n json_file_name = f\"N={N},K={K},device_name={device_name},dtype=fp8_w8a8,block_shape=[{block_n},{block_k}].json\" # noqa: E501\n\n config_file_path = os.path.join(\n os.path.dirname(os.path.realpath(__file__)), \"configs\", json_file_name\n )\n if os.path.exists(config_file_path):\n with open(config_file_path) as f:\n logger.info(\n \"Using configuration from %s for W8A8 Block FP8 kernel.\",\n config_file_path,\n )\n # If a configuration has been found, return it\n return {int(key): val for key, val in json.load(f).items()}\n\n # If no optimized configuration is available, we will use the default\n # configuration\n logger.warning(\n \"Using default W8A8 Block FP8 kernel config. Performance might \"\n \"be sub-optimal! Config file not found at %s\",\n config_file_path,\n )\n return None\n\n\ndef w8a8_triton_block_scaled_mm(\n A: torch.Tensor,\n B: torch.Tensor,\n As: torch.Tensor,\n Bs: torch.Tensor,\n block_size: list[int],\n output_dtype: torch.dtype = torch.float16,\n) -> torch.Tensor:\n \"\"\"This function performs matrix multiplication with block-wise\n quantization.\n It takes two input tensors `A` and `B` with scales `As` and `Bs`.\n The output is returned in the specified `output_dtype`.\n Args:\n A: The input tensor, e.g., activation.\n B: The input tensor, e.g., weight.\n As: The per-token-group quantization scale for `A`.\n Bs: The per-block quantization scale for `B`.\n block_size: The block size for per-block quantization. It should\n be 2-dim, e.g., [128, 128].\n output_dytpe: The dtype of the returned tensor.\n Returns:\n torch.Tensor: The result of matmul.\n \"\"\"\n assert len(block_size) == 2\n block_n, block_k = block_size[0], block_size[1]\n\n assert A.shape[-1] == B.shape[-1]\n assert A.shape[:-1] == As.shape[:-1] and A.is_contiguous()\n assert triton.cdiv(A.shape[-1], block_k) == As.shape[-1]\n M = A.numel() // A.shape[-1]\n\n assert B.ndim == 2 and Bs.ndim == 2\n N, K = B.shape\n assert triton.cdiv(N, block_n) == Bs.shape[0]\n assert triton.cdiv(K, block_k) == Bs.shape[1]\n\n C_shape = A.shape[:-1] + (N,)\n C = A.new_empty(C_shape, dtype=output_dtype)\n\n configs = get_w8a8_block_fp8_configs(N, K, block_size[0], block_size[1])\n if configs:\n # Get the optimal config if there is one\n config = configs[min(configs.keys(), key=lambda x: abs(x - M))]\n else:\n # Default config\n # Block-wise quant: BLOCK_SIZE_N must be divisible by block_size[0]\n # BLOCK_SIZE_K must be divisible by block_size[1]\n config = {\n \"BLOCK_SIZE_M\": 64,\n \"BLOCK_SIZE_N\": block_size[0],\n \"BLOCK_SIZE_K\": block_size[1],\n \"GROUP_SIZE_M\": 32,\n \"num_warps\": 4,\n \"num_stages\": 2,\n }\n\n def grid(META):\n return (\n triton.cdiv(M, META[\"BLOCK_SIZE_M\"]) * triton.cdiv(N, META[\"BLOCK_SIZE_N\"]),\n )\n\n _w8a8_triton_block_scaled_mm[grid](\n A,\n B,\n C,\n As,\n Bs,\n M,\n N,\n K,\n block_n,\n block_k,\n A.stride(-2),\n A.stride(-1),\n B.stride(1),\n B.stride(0),\n C.stride(-2),\n C.stride(-1),\n As.stride(-2),\n As.stride(-1),\n Bs.stride(1),\n Bs.stride(0),\n **config,\n )\n\n return C\n\n\ndef requant_weight_ue8m0_inplace(\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n block_size: Sequence[int] = (128, 128),\n) -> None:\n \"\"\"Re-quantise *weight* so that its per-block scaling factors are in the\n UE8M0 (power-of-two) format expected by the new DeepGEMM kernels inplace.\n\n Args:\n weight: Block-quantised weight tensor stored in `torch.float8_e4m3fn`.\n Expected shape `(..., M, K)`.\n weight_scale: Corresponding per-block scale tensor (`torch.float32`)\n with shape `(..., M // block_size[0], K // block_size[1])`.\n block_size: 2-element iterable `[block_m, block_k]` describing the\n block quantisation granularity.\n \"\"\"\n if weight.numel() == 0:\n return\n\n if weight.dtype != torch.float8_e4m3fn:\n raise ValueError(\n f\"Expected *weight* to be torch.float8_e4m3fn, got {weight.dtype} instead.\"\n )\n\n from vllm.utils.deep_gemm import per_block_cast_to_fp8\n\n block_m, block_k = int(block_size[0]), int(block_size[1])\n\n # Flatten leading dimensions so we can iterate over the last two dims.\n leading_shape = weight.shape[:-2]\n if len(leading_shape) == 0:\n w_view = weight.unsqueeze(0)\n s_view = weight_scale.unsqueeze(0)\n else:\n w_view = weight.reshape(-1, weight.shape[-2], weight.shape[-1])\n s_view = weight_scale.reshape(-1, *weight_scale.shape[-2:])\n\n num_mats = w_view.size(0)\n for idx in range(num_mats):\n w_q = w_view[idx]\n s_old = s_view[idx]\n\n # De-quantise with the *old* scaling factors (float32).\n m_cur, k_cur = w_q.shape\n s_float = s_old.to(torch.float32)\n # Expand scales along rows and cols by block size, then crop.\n s_exp_r = torch.repeat_interleave(s_float, block_m, dim=0)\n s_exp = torch.repeat_interleave(s_exp_r, block_k, dim=1)\n s_exp = s_exp[:m_cur, :k_cur]\n w_dq = w_q.to(torch.float32) * s_exp\n # Re-quantise using power-of-two scaling (UE8M0).\n w_requant, s_requant = per_block_cast_to_fp8(\n w_dq, [block_m, block_k], use_ue8m0=True\n )\n\n # Write back the results in-place.\n w_q.copy_(w_requant)\n s_old.copy_(s_requant)\n\n\ndef deepgemm_post_process_fp8_weight_block(\n wq: torch.Tensor, ws: torch.Tensor, quant_block_shape: tuple[int], use_e8m0: bool\n) -> tuple[torch.Tensor, torch.Tensor]:\n assert wq.dtype == torch.float8_e4m3fn, (\n \"Expected quantized tensor dtype \"\n f\"to be torch.float8_e4m3fn, got {wq.dtype} instead.\"\n )\n assert ws.dtype == torch.float32, (\n f\"Expected tensor scales dtype to be torch.float32, got {ws.dtype} instead\"\n )\n\n if use_e8m0:\n requant_weight_ue8m0_inplace(wq, ws, block_size=quant_block_shape)\n\n original_ndim = wq.ndim\n if wq.ndim == 2:\n assert ws.ndim == 2\n wq = wq.unsqueeze(0)\n ws = ws.unsqueeze(0)\n\n # From https://github.com/deepseek-ai/DeepGEMM/blob/c9f8b34dcdacc20aa746b786f983492c51072870/csrc/utils/layout.hpp#L46\n recipe = (1, 128, 128)\n\n # Ref : https://github.com/deepseek-ai/DeepGEMM/blob/c9f8b34dcdacc20aa746b786f983492c51072870/csrc/apis/gemm.hpp\n # DeepGemm uses the `transform_sf_into_required_layout` function to\n # represent scales in the correct format.\n dg_ws = transform_sf_into_required_layout(\n sf=ws,\n mn=wq.size(1),\n k=wq.size(2),\n recipe=recipe,\n num_groups=wq.size(0),\n # is the scale factors for A in (Refers to the argument A in A @ B).\n # Weights are B.\n is_sfa=False,\n )\n\n if original_ndim == 2:\n wq = wq.squeeze(0)\n dg_ws = dg_ws.squeeze(0)\n\n return wq, dg_ws\n\n\ndef _maybe_pad_fp8_weight(weight: torch.Tensor) -> torch.Tensor:\n \"\"\"Pad the weight tensor. This is an optimization on ROCm platform, which\n can benefit from tensors located far enough from one another in memory\"\"\"\n if (\n envs.VLLM_ROCM_FP8_PADDING\n and current_platform.is_rocm()\n and weight.stride(-1) == 1\n and (weight.stride(-2) * weight.element_size()) % 512 == 0\n ):\n num_pad = 256 // weight.element_size()\n import torch.nn.functional as F\n\n weight = F.pad(weight, (0, num_pad), \"constant\", 0)[..., :-num_pad]\n torch.cuda.empty_cache()\n return weight\n\n\ndef validate_fp8_block_shape(\n layer: torch.nn.Module,\n input_size: int,\n output_size: int,\n input_size_per_partition: int,\n output_partition_sizes: list[int],\n block_size: list[int],\n) -> None:\n \"\"\"Validate block quantization shapes for tensor parallelism.\"\"\"\n from vllm.distributed import get_tensor_model_parallel_world_size\n\n tp_size = getattr(layer, \"tp_size\", get_tensor_model_parallel_world_size())\n block_n, block_k = block_size[0], block_size[1]\n\n # Required by row parallel\n if (\n tp_size > 1\n and input_size // input_size_per_partition == tp_size\n and input_size_per_partition % block_k != 0\n ):\n raise ValueError(\n f\"Weight input_size_per_partition = {input_size_per_partition} \"\n f\"is not divisible by weight quantization block_k = {block_k}.\"\n )\n\n # Required by column parallel or enabling merged weights\n is_tp_split = tp_size > 1 and output_size // sum(output_partition_sizes) == tp_size\n is_merged_gemm = len(output_partition_sizes) > 1\n if is_tp_split or is_merged_gemm:\n sizes_to_check = output_partition_sizes\n if not is_tp_split and is_merged_gemm:\n # In case of merged matrices, we allow the last\n # matrix to not be a multiple of block size\n sizes_to_check = output_partition_sizes[:-1]\n for output_partition_size in sizes_to_check:\n if output_partition_size % block_n != 0:\n raise ValueError(\n f\"Weight output_partition_size = \"\n f\"{output_partition_size} is not divisible by \"\n f\"weight quantization block_n = {block_n}.\"\n )\n\n\ndef create_fp8_weight_parameter(\n output_size_per_partition: int,\n input_size_per_partition: int,\n weight_loader: Callable | None,\n) -> torch.nn.Parameter:\n \"\"\"Create FP8 weight parameter.\"\"\"\n from vllm.model_executor.parameter import ModelWeightParameter\n\n return ModelWeightParameter(\n data=torch.empty(\n output_size_per_partition,\n input_size_per_partition,\n dtype=torch.float8_e4m3fn,\n ),\n input_dim=1,\n output_dim=0,\n weight_loader=weight_loader,\n )\n\n\ndef create_fp8_scale_parameter(\n parameter_type: torch.nn.Parameter,\n output_partition_sizes: list[int],\n input_size_per_partition: int,\n block_size: list[int] | None,\n weight_loader: Callable | None,\n) -> torch.nn.Parameter:\n \"\"\"Create scale parameter based on quantization strategy.\"\"\"\n if parameter_type == ChannelQuantScaleParameter:\n scale = parameter_type(\n data=torch.empty((sum(output_partition_sizes), 1), dtype=torch.float32),\n output_dim=0,\n weight_loader=weight_loader,\n )\n elif parameter_type == BlockQuantScaleParameter:\n assert block_size is not None\n block_n, block_k = block_size[0], block_size[1]\n output_size_per_partition = sum(output_partition_sizes)\n scale = parameter_type(\n data=torch.empty(\n (output_size_per_partition + block_n - 1) // block_n,\n (input_size_per_partition + block_k - 1) // block_k,\n dtype=torch.float32,\n ),\n input_dim=1,\n output_dim=0,\n weight_loader=weight_loader,\n )\n elif parameter_type == PerTensorScaleParameter:\n scale = parameter_type(\n data=torch.empty(len(output_partition_sizes), dtype=torch.float32),\n weight_loader=weight_loader,\n )\n else:\n raise ValueError(f\"Unknown parameter type: {parameter_type}\")\n\n scale[:] = torch.finfo(torch.float32).min\n return scale\n\n\ndef create_fp8_input_scale(\n output_partition_sizes: list[int], weight_loader: Callable | None\n) -> torch.nn.Parameter:\n \"\"\"Create input scale parameter for static activation quantization.\"\"\"\n from vllm.model_executor.parameter import PerTensorScaleParameter\n\n scale = PerTensorScaleParameter(\n data=torch.empty(len(output_partition_sizes), dtype=torch.float32),\n weight_loader=weight_loader,\n )\n scale[:] = torch.finfo(torch.float32).min\n return scale\n\n\ndef process_fp8_weight_tensor_strategy(\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n logical_widths: list[int],\n input_scale: torch.Tensor | None = None,\n) -> tuple[torch.Tensor, torch.Tensor, torch.Tensor | None]:\n \"\"\"Process weights for tensor-wise quantization strategy.\"\"\"\n from vllm.model_executor.layers.quantization.utils.w8a8_utils import (\n normalize_e4m3fn_to_e4m3fnuz,\n requantize_with_max_scale,\n )\n\n if current_platform.is_fp8_fnuz():\n weight, weight_scale, input_scale = normalize_e4m3fn_to_e4m3fnuz(\n weight=weight, weight_scale=weight_scale, input_scale=input_scale\n )\n\n # Requantize with max scale\n weight_scale, weight = requantize_with_max_scale(\n weight=weight,\n weight_scale=weight_scale,\n logical_widths=logical_widths,\n )\n\n weight = _maybe_pad_fp8_weight(weight)\n return weight, weight_scale, input_scale\n\n\ndef process_fp8_weight_channel_strategy(\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n input_scale: torch.Tensor | None = None,\n) -> tuple[torch.Tensor, torch.Tensor, torch.Tensor | None]:\n \"\"\"Process weights for channel-wise quantization strategy.\"\"\"\n from vllm.model_executor.layers.quantization.utils.w8a8_utils import (\n normalize_e4m3fn_to_e4m3fnuz,\n )\n\n if current_platform.is_fp8_fnuz():\n weight, weight_scale, input_scale = normalize_e4m3fn_to_e4m3fnuz(\n weight=weight, weight_scale=weight_scale, input_scale=input_scale\n )\n\n return weight, weight_scale, input_scale\n\n\ndef process_fp8_weight_block_strategy(\n weight: torch.Tensor,\n weight_scale: torch.Tensor,\n) -> tuple[torch.Tensor, torch.Tensor]:\n \"\"\"Process weights for block-wise quantization strategy.\"\"\"\n from vllm.model_executor.layers.quantization.utils.w8a8_utils import (\n normalize_e4m3fn_to_e4m3fnuz,\n )\n\n if current_platform.is_fp8_fnuz():\n weight, weight_scale, _ = normalize_e4m3fn_to_e4m3fnuz(\n weight=weight, weight_scale=weight_scale\n )\n\n weight = _maybe_pad_fp8_weight(weight)\n return weight, weight_scale\n\n\ndef maybe_post_process_fp8_weight_block(layer: torch.nn.Module):\n assert layer.weight_block_size is not None\n\n from vllm.utils.deep_gemm import (\n is_deep_gemm_e8m0_used,\n should_use_deepgemm_for_fp8_linear,\n )\n\n # On Blackwell or Hopper, if E8M0 for DeepGemm is used, we need to\n # requantize the weight and input to the specific scale\n # at the same time.\n should_use_deepgemm = should_use_deepgemm_for_fp8_linear(\n layer.orig_dtype, layer.weight\n )\n if should_use_deepgemm:\n dg_weight, dg_weight_scale = deepgemm_post_process_fp8_weight_block(\n wq=layer.weight.data,\n ws=layer.weight_scale.data,\n quant_block_shape=tuple(layer.weight_block_size),\n use_e8m0=is_deep_gemm_e8m0_used(),\n )\n layer.weight = torch.nn.Parameter(dg_weight, requires_grad=False)\n layer.weight_scale = torch.nn.Parameter(dg_weight_scale, requires_grad=False)\n\n\ndef expert_weight_is_col_major(x: torch.Tensor) -> bool:\n assert x.dim() == 3\n b, m, n = x.shape\n return x.stride(0) == m * n and x.stride(1) == 1 and x.stride(2) == m\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## Purpose\nWith DeepEPHighThroughput all2all backend and EP, the \"act_mul + fp8 quant\" operation in deep_gemm_moe.py is expensive and almost as expensive as the FP8 gemms surrounding the operation. This PR,\n1. Adds a fused silu_mul_quant kernels to fuse the operations together.\n2. Another minor optimization is to rearrange the `_resize_cache` function so the CPU can run ahead of the GPU.\n\n## Traces\n`main`\n<img width=\"1009\" height=\"201\" alt=\"MAIN-\" src=\"https://github.com/user-attachments/assets/c5a629d4-8a8f-4710-a6d7-37ccf984f7ca\" />\n\n`PR`\n<img width=\"1123\" height=\"194\" alt=\"PR-\" src=\"https://github.com/user-attachments/assets/3b16453b-6159-41dd-aa2d-348d31774a6b\" />\n\n\n- The traces cannot be compared 1:1 as we don't know how many tokens reached the Rank. But they operation times can be compared relative to the deepgemm times. \n- Note that the PR has a much smaller block relative to the prior DeepGEMM call\n- Note that the bubble before the first DeepGEMM call is smaller in the PR. This is due to the rearrangement of the `_resize_cache` operations. This helps the CPU to run ahead and have the `_resize_cache` operations overlap with GPU operations.\n\n## Benchmarks\n\n### Microbenchmarks\nPlease find micro-benchmark results [here](https://docs.google.com/spreadsheets/d/1MEYa9ijI1s1tCocLOYxat3MiTVpZZwBrlIHVGKTEU3M/edit?usp=sharing)\nTLDR; Performance is better with the new kernel\n\n### E2E benchmarks\ncommand: \n `VLLM_ALL2ALL_BACKEND=\"deepep_high_throughput\" vllm serve Qwen/Qwen3-30B-A3B-FP8 --data-parallel-size 2 --enable-expert-parallel --no-enable-prefix-caching --port 9010`\nbench command (prefill):\n`vllm bench serve --model Qwen/Qwen3-30B-A3B-FP8 --dataset-name random --num-prompts 256 --random-input-len 4096 --random-output-len 1 --ignore-eos --port 9010 --backend vllm`\n\n`PR`\n```\n============ Serving Benchmark Result ============\nSuccessful requests: 256 \nFailed requests: 0 \nBenchmark duration (s): 11.94 \nTotal input tokens: 1048576 \nTotal generated tokens: 256 \nRequest throughput (req/s): 21.44 \nOutput token throughput (tok/s): 21.44 \nPeak output token throughput (tok/s): 24.00 \nPeak concurrent requests: 256.00 \nTotal Token throughput (tok/s): 87827.95 \n---------------Time to First Token----------------\nMean TTFT (ms): 6265.72 \nMedian TTFT (ms): 6263.23 \nP99 TTFT (ms): 11851.38 \n-----Time per Output Token (excl. 1st token)------\nMean TPOT (ms): 0.00 \nMedian TPOT (ms): 0.00 \nP99 TPOT (ms): 0.00 \n---------------Inter-token Latency----------------\nMean ITL (ms): 0.00 \nMedian ITL (ms): 0.00 \nP99 ITL (ms): 0.00 \n==================================================\n```\n`main`\n```\n============ Serving Benchmark Result ============\nSuccessful requests: 256 \nFailed requests: 0 \nBenchmark duration (s): 13.10 \nTotal input tokens: 1048576 \nTotal generated tokens: 256 \nRequest throughput (req/s): 19.55 \nOutput token throughput (tok/s): 19.55 \nPeak output token throughput (tok/s): 24.00 \nPeak concurrent requests: 256.00 \nTotal Token throughput (tok/s): 80087.70 \n---------------Time to First Token----------------\nMean TTFT (ms): 6743.63 \nMedian TTFT (ms): 6742.18 \nP99 TTFT (ms): 12842.97 \n-----Time per Output Token (excl. 1st token)------\nMean TPOT (ms): 0.00 \nMedian TPOT (ms): 0.00 \nP99 TPOT (ms): 0.00 \n---------------Inter-token Latency----------------\nMean ITL (ms): 0.00 \nMedian ITL (ms): 0.00 \nP99 ITL (ms): 0.00 \n==================================================\n```\n\n## Test Plan\ncommand:\n `VLLM_ALL2ALL_BACKEND=\"deepep_high_throughput\" vllm serve Qwen/Qwen3-30B-A3B-FP8 --data-parallel-size 2 --enable-expert-parallel --no-enable-prefix-caching --port 9010`\n\nlm-eval command:\n`lm_eval --model local-completions --tasks gsm8k --model_args model=Qwen/Qwen3-30B-A3B-FP8,base_url=http://localhost:9010/v1/completions,num_concurrent=30,max_retries=3 --limit 100`\n\n## Test Result\n`PR`\n```\n|Tasks|Version| Filter |n-shot| Metric | |Value| |Stderr|\n|-----|------:|----------------|-----:|-----------|---|----:|---|-----:|\n|gsm8k| 3|flexible-extract| 5|exact_match|↑ | 0.88|± |0.0327|\n| | |strict-match | 5|exact_match|↑ | 0.93|± |0.0256|\n```\n`main`\n```\n|Tasks|Version| Filter |n-shot| Metric | |Value| |Stderr|\n|-----|------:|----------------|-----:|-----------|---|----:|---|-----:|\n|gsm8k| 3|flexible-extract| 5|exact_match|↑ | 0.87|± |0.0338|\n| | |strict-match | 5|exact_match|↑ | 0.91|± |0.0288|\n```\n"},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}}],"truncated":false,"partial":false},"paginationData":{"pageIndex":3,"numItemsPerPage":100,"numTotalItems":1365,"offset":300,"length":100}},"jwt":"eyJhbGciOiJFZERTQSIsImtpZCI6IjVHZDBvd0g5MTM2eDZjc1FvbE1zcktNWUZoRVFoUm5PVVVybEpjOUhaUEEifQ.eyJyZWFkIjp0cnVlLCJwZXJtaXNzaW9ucyI6eyJyZXBvLmNvbnRlbnQucmVhZCI6dHJ1ZX0sInJlcG9JZHMiOlsiNmFkYjE3ZGJmZDFkOTk5NTg0YWY2M2I5Il0sImlhdCI6MTc5NDE0MTkwOCwianRpIjoiNjdkNzM2OTItNGRiYi00ZGU1LWJiZjEtZThmYmFkNWFiZmQ0Iiwic3ViIjoiL2RhdGFzZXRzL2d1eWNodWsva2VybmVsLW9wdC1ybCIsImV4cCI6MTc5NDE0NTUwOCwiaXNzIjoiaHR0cHM6Ly9odWdnaW5nZmFjZS5jbyJ9._H1kka0yb2_vFDrh5HF3g67EzgWwGTTWMiNAnh-8NJdwaXIW-_gT3yqgbOqgrRR_uqv2EALg_Sb9HPhgvswEAg","displayUrls":true,"splitSizeSummaries":[{"config":"kernel_commits","split":"train","numRows":1365,"numBytesParquet":42213599},{"config":"kernel_commits","split":"test","numRows":152,"numBytesParquet":5808547},{"config":"tuned_configs","split":"train","numRows":17561,"numBytesParquet":24732360},{"config":"tuned_configs","split":"test","numRows":1726,"numBytesParquet":2111842}]},"discussionsStats":{"closed":0,"open":0,"total":0},"fullWidth":true,"hasGatedAccess":true,"hasFullAccess":true,"isEmbedded":false,"savedQueries":{"community":[],"user":[]}}">
repo stringclasses 3
values | commit stringlengths 40 40 | date stringdate 2023-04-02 02:30:17-0500 2026-10-18 07:42:16-0500 | pr_number int64 20 61.9k ⌀ | pr_url stringlengths 44 53 ⌀ | title stringlengths 8 263 | message stringlengths 8 8k | path stringlengths 10 155 | language stringclasses 4
values | license stringclasses 4
values | before_code stringlengths 160 118k | after_code stringlengths 340 120k | diff stringlengths 149 51k | lines_added int64 0 729 | lines_removed int64 0 488 | files_in_commit int64 1 10 | models_mentioned listlengths 0 4 | hardware_mentioned listlengths 0 16 | speedup_claims listlengths 0 10 | prompt stringlengths 569 119k | pr_body stringlengths 0 24k | gains stringlengths 2 197k | kernel_speedup float64 0.78 150 ⌀ | e2e_speedup float64 0.76 136 ⌀ |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
vllm | 580864d81eb03d9fb1383e1782636ff6a9425fa2 | 2026-03-09T17:50:36+01:00 | 34,917 | https://github.com/vllm-project/vllm/pull/34917 | [Attention][Perf][Kernel] Replace torch.cat with vectorized CUDA kernel MLA query concat - DeepSeek-V3.2 (#34917) | [Attention][Perf][Kernel] Replace torch.cat with vectorized CUDA kernel MLA query concat - DeepSeek-V3.2 (#34917)
Signed-off-by: LopezCastroRoberto <rocastro@redhat.com>
Signed-off-by: Roberto L. Castro <38211239+LopezCastroRoberto@users.noreply.github.com> | csrc/cache.h | cpp | Apache-2.0 | #pragma once
#include <torch/all.h>
#include <c10/util/Optional.h>
#include <map>
#include <vector>
void swap_blocks(torch::Tensor& src, torch::Tensor& dst,
int64_t block_size_in_bytes,
const torch::Tensor& block_mapping);
void reshape_and_cache(torch::Tensor& key, torch::Tensor& v... | #pragma once
#include <torch/all.h>
#include <c10/util/Optional.h>
#include <map>
#include <vector>
void swap_blocks(torch::Tensor& src, torch::Tensor& dst,
int64_t block_size_in_bytes,
const torch::Tensor& block_mapping);
void reshape_and_cache(torch::Tensor& key, torch::Tensor& v... | --- csrc/cache.h
+++ csrc/cache.h
@@ -74,6 +74,12 @@
int64_t quant_block_size, // quantization block size
const std::string& scale_fmt);
+// Concatenate query nope and rope for MLA/DSA attention
+void concat_mla_q(
+ torch::Tensor& ql_nope, // [num_tokens, num_heads, nope_dim]
+ torch::Tensor& q_... | 6 | 0 | 5 | [
"deepseek"
] | [] | [] | Optimize this cpp kernel file from vllm (csrc/cache.h).
Goal: [Attention][Perf][Kernel] Replace torch.cat with vectorized CUDA kernel MLA query concat - DeepSeek-V3.2
Target hardware: unspecified
Target models: deepseek
Current file:
```cpp
#pragma once
#include <torch/all.h>
#include <c10/util/Optional.h>
#include... | PR #35105 needs to be merged first
## Perf eval on B300
Speedup improves with the number of tokens, peaking at `~11.8×` w.r.t. `torch.cat`.
```
--- Non-contiguous nope inputs (transposed BMM output) ---
concat_mla_q-transposed:
num_tokens torch.cat (Latency (us)) concat_mla_q (v8) (Latency (us))
1 8.0... | [{"scope": "kernel", "hardware": "B300", "model": "DeepSeek-V3.2", "shape": "transposed BMM output", "batch_size": 8, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 5.05539, "optimized": 1.892126, "stated_speedup": null, "speedup": 2.6718}, {"scope": "kernel", "hardware": "B300", "model": "De... | 8.2664 | 1.0454 |
vllm | 580864d81eb03d9fb1383e1782636ff6a9425fa2 | 2026-03-09T17:50:36+01:00 | 34,917 | https://github.com/vllm-project/vllm/pull/34917 | [Attention][Perf][Kernel] Replace torch.cat with vectorized CUDA kernel MLA query concat - DeepSeek-V3.2 (#34917) | [Attention][Perf][Kernel] Replace torch.cat with vectorized CUDA kernel MLA query concat - DeepSeek-V3.2 (#34917)
Signed-off-by: LopezCastroRoberto <rocastro@redhat.com>
Signed-off-by: Roberto L. Castro <38211239+LopezCastroRoberto@users.noreply.github.com> | csrc/cache_kernels.cu | cuda | Apache-2.0 | #include <torch/all.h>
#include <ATen/cuda/CUDAContext.h>
#include <c10/cuda/CUDAGuard.h>
#include <c10/cuda/CUDAException.h>
#include <c10/util/Optional.h>
#include "cuda_utils.h"
#include "cuda_compat.h"
#include "dispatch_utils.h"
#include "quantization/vectorization_utils.cuh"
#ifdef USE_ROCM
#include "quantiza... | #include <torch/all.h>
#include <ATen/cuda/CUDAContext.h>
#include <c10/cuda/CUDAGuard.h>
#include <c10/cuda/CUDAException.h>
#include <c10/util/Optional.h>
#include "cuda_utils.h"
#include "cuda_compat.h"
#include "dispatch_utils.h"
#include "quantization/vectorization_utils.cuh"
#include "concat_mla_q.cuh"
#ifdef U... | --- csrc/cache_kernels.cu
+++ csrc/cache_kernels.cu
@@ -8,6 +8,7 @@
#include "cuda_compat.h"
#include "dispatch_utils.h"
#include "quantization/vectorization_utils.cuh"
+#include "concat_mla_q.cuh"
#ifdef USE_ROCM
#include "quantization/w8a8/fp8/amd/quant_utils.cuh"
@@ -1358,3 +1359,43 @@
CALL_CP_GATHER_I... | 41 | 0 | 5 | [
"deepseek"
] | [] | [] | Optimize this cuda kernel file from vllm (csrc/cache_kernels.cu).
Goal: [Attention][Perf][Kernel] Replace torch.cat with vectorized CUDA kernel MLA query concat - DeepSeek-V3.2
Target hardware: unspecified
Target models: deepseek
Current file:
```cuda
#include <torch/all.h>
#include <ATen/cuda/CUDAContext.h>
#include... | PR #35105 needs to be merged first
## Perf eval on B300
Speedup improves with the number of tokens, peaking at `~11.8×` w.r.t. `torch.cat`.
```
--- Non-contiguous nope inputs (transposed BMM output) ---
concat_mla_q-transposed:
num_tokens torch.cat (Latency (us)) concat_mla_q (v8) (Latency (us))
1 8.0... | [{"scope": "kernel", "hardware": "B300", "model": "DeepSeek-V3.2", "shape": "transposed BMM output", "batch_size": 8, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 5.05539, "optimized": 1.892126, "stated_speedup": null, "speedup": 2.6718}, {"scope": "kernel", "hardware": "B300", "model": "De... | 8.2664 | 1.0454 |
vllm | 580864d81eb03d9fb1383e1782636ff6a9425fa2 | 2026-03-09T17:50:36+01:00 | 34,917 | https://github.com/vllm-project/vllm/pull/34917 | [Attention][Perf][Kernel] Replace torch.cat with vectorized CUDA kernel MLA query concat - DeepSeek-V3.2 (#34917) | [Attention][Perf][Kernel] Replace torch.cat with vectorized CUDA kernel MLA query concat - DeepSeek-V3.2 (#34917)
Signed-off-by: LopezCastroRoberto <rocastro@redhat.com>
Signed-off-by: Roberto L. Castro <38211239+LopezCastroRoberto@users.noreply.github.com> | csrc/cuda_vec_utils.cuh | cuda | Apache-2.0 | // SPDX-License-Identifier: Apache-2.0
// SPDX-FileCopyrightText: Copyright contributors to the vLLM project
#pragma once
#include <c10/util/BFloat16.h>
#include <c10/util/Half.h>
#include <cassert>
#ifdef USE_ROCM
#include <hip/hip_runtime.h>
#else
#include <cuda_bf16.h>
#include <cuda_fp16.h>
#include <cud... | // SPDX-License-Identifier: Apache-2.0
// SPDX-FileCopyrightText: Copyright contributors to the vLLM project
#pragma once
#include <c10/util/BFloat16.h>
#include <c10/util/Half.h>
#include <cassert>
#ifdef USE_ROCM
#include <hip/hip_runtime.h>
#else
#include <cuda_bf16.h>
#include <cuda_fp16.h>
#include <cud... | --- csrc/cuda_vec_utils.cuh
+++ csrc/cuda_vec_utils.cuh
@@ -196,7 +196,6 @@
return val;
#else
assert(false && "ld256_cs requires SM100+ with CUDA 12.9+");
- return {};
#endif
}
@@ -211,23 +210,51 @@
#endif
}
-// 32-bit cache-streaming (.cs) load / store — SM100+ only.
+// 32-bit load / store.
+__device... | 38 | 11 | 5 | [
"deepseek"
] | [] | [] | Optimize this cuda kernel file from vllm (csrc/cuda_vec_utils.cuh).
Goal: [Attention][Perf][Kernel] Replace torch.cat with vectorized CUDA kernel MLA query concat - DeepSeek-V3.2
Target hardware: unspecified
Target models: deepseek
Current file:
```cuda
// SPDX-License-Identifier: Apache-2.0
// SPDX-FileCopyrightText... | PR #35105 needs to be merged first
## Perf eval on B300
Speedup improves with the number of tokens, peaking at `~11.8×` w.r.t. `torch.cat`.
```
--- Non-contiguous nope inputs (transposed BMM output) ---
concat_mla_q-transposed:
num_tokens torch.cat (Latency (us)) concat_mla_q (v8) (Latency (us))
1 8.0... | [{"scope": "kernel", "hardware": "B300", "model": "DeepSeek-V3.2", "shape": "transposed BMM output", "batch_size": 8, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 5.05539, "optimized": 1.892126, "stated_speedup": null, "speedup": 2.6718}, {"scope": "kernel", "hardware": "B300", "model": "De... | 8.2664 | 1.0454 |
vllm | 580864d81eb03d9fb1383e1782636ff6a9425fa2 | 2026-03-09T17:50:36+01:00 | 34,917 | https://github.com/vllm-project/vllm/pull/34917 | [Attention][Perf][Kernel] Replace torch.cat with vectorized CUDA kernel MLA query concat - DeepSeek-V3.2 (#34917) | [Attention][Perf][Kernel] Replace torch.cat with vectorized CUDA kernel MLA query concat - DeepSeek-V3.2 (#34917)
Signed-off-by: LopezCastroRoberto <rocastro@redhat.com>
Signed-off-by: Roberto L. Castro <38211239+LopezCastroRoberto@users.noreply.github.com> | csrc/torch_bindings.cpp | cpp | Apache-2.0 | #include "cache.h"
#include "cuda_utils.h"
#include "ops.h"
#include "core/registration.h"
#include <torch/library.h>
#include <torch/version.h>
// Note on op signatures:
// The X_meta signatures are for the meta functions corresponding to op X.
// They must be kept in sync with the signature for X. Generally, only
/... | #include "cache.h"
#include "cuda_utils.h"
#include "ops.h"
#include "core/registration.h"
#include <torch/library.h>
#include <torch/version.h>
// Note on op signatures:
// The X_meta signatures are for the meta functions corresponding to op X.
// They must be kept in sync with the signature for X. Generally, only
/... | --- csrc/torch_bindings.cpp
+++ csrc/torch_bindings.cpp
@@ -803,6 +803,10 @@
&indexer_k_quant_and_cache);
cache_ops.def(
+ "concat_mla_q(Tensor ql_nope, Tensor q_pe, Tensor! q_out) -> ()");
+ cache_ops.impl("concat_mla_q", torch::kCUDA, &concat_mla_q);
+
+ cache_ops.def(
"cp_gather_... | 4 | 0 | 5 | [
"deepseek"
] | [] | [] | Optimize this cpp kernel file from vllm (csrc/torch_bindings.cpp).
Goal: [Attention][Perf][Kernel] Replace torch.cat with vectorized CUDA kernel MLA query concat - DeepSeek-V3.2
Target hardware: unspecified
Target models: deepseek
Current file:
```cpp
#include "cache.h"
#include "cuda_utils.h"
#include "ops.h"
#inclu... | PR #35105 needs to be merged first
## Perf eval on B300
Speedup improves with the number of tokens, peaking at `~11.8×` w.r.t. `torch.cat`.
```
--- Non-contiguous nope inputs (transposed BMM output) ---
concat_mla_q-transposed:
num_tokens torch.cat (Latency (us)) concat_mla_q (v8) (Latency (us))
1 8.0... | [{"scope": "kernel", "hardware": "B300", "model": "DeepSeek-V3.2", "shape": "transposed BMM output", "batch_size": 8, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 5.05539, "optimized": 1.892126, "stated_speedup": null, "speedup": 2.6718}, {"scope": "kernel", "hardware": "B300", "model": "De... | 8.2664 | 1.0454 |
vllm | 2b28b9b269e18cfe42c7e945d1da8d1c40989efa | 2026-03-09T17:46:57+01:00 | 35,290 | https://github.com/vllm-project/vllm/pull/35290 | [Attention][Perf] Optimize cp_gather_and_upconvert_fp8_kv_cache - DeepSeek-v3.2 (#35290) | [Attention][Perf] Optimize cp_gather_and_upconvert_fp8_kv_cache - DeepSeek-v3.2 (#35290)
Signed-off-by: LopezCastroRoberto <rocastro@redhat.com>
Co-authored-by: Claude <noreply@anthropic.com> | csrc/cache_kernels.cu | cuda | Apache-2.0 | #include <torch/all.h>
#include <ATen/cuda/CUDAContext.h>
#include <c10/cuda/CUDAGuard.h>
#include <c10/cuda/CUDAException.h>
#include <c10/util/Optional.h>
#include "cuda_utils.h"
#include "cuda_compat.h"
#include "dispatch_utils.h"
#include "quantization/vectorization_utils.cuh"
#ifdef USE_ROCM
#include "quantiza... | #include <torch/all.h>
#include <ATen/cuda/CUDAContext.h>
#include <c10/cuda/CUDAGuard.h>
#include <c10/cuda/CUDAException.h>
#include <c10/util/Optional.h>
#include "cuda_utils.h"
#include "cuda_compat.h"
#include "dispatch_utils.h"
#include "quantization/vectorization_utils.cuh"
#ifdef USE_ROCM
#include "quantiza... | --- csrc/cache_kernels.cu
+++ csrc/cache_kernels.cu
@@ -995,75 +995,67 @@
// Similar to cp_gather_cache but specifically for FP8->BF16 conversion
__global__ void cp_gather_and_upconvert_fp8_kv_cache(
const uint8_t* __restrict__ src_cache, // [NUM_BLOCKS, BLOCK_SIZE, 656]
- __nv_bfloat16* __restrict__ dst, ... | 70 | 77 | 1 | [
"deepseek"
] | [] | [] | Optimize this cuda kernel file from vllm (csrc/cache_kernels.cu).
Goal: [Attention][Perf] Optimize cp_gather_and_upconvert_fp8_kv_cache - DeepSeek-v3.2
Target hardware: unspecified
Target models: deepseek
Current file:
```cuda
#include <torch/all.h>
#include <ATen/cuda/CUDAContext.h>
#include <c10/cuda/CUDAGuard.h>
#... | ```
======================================================================
CP_GATHER_AND_UPCONVERT_FP8_KV_CACHE BENCHMARKS
======================================================================
Cache entry: 656 bytes (512 FP8 + 16 scales + 128 RoPE)
Output row: 576 BF16 = 1152 bytes
Per token: 1808 bytes (read + wri... | [{"scope": "kernel", "hardware": null, "model": null, "shape": "cache_entry=656_bytes,output_row=1152_bytes,block_size=64", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 123.42836, "optimized": 3.763423, "stated_speedup": null, "speedup": 32.7968}, {"scope": "kernel", "hardw... | 12.45 | 1.4499 |
vllm | 8e7820131ee8d0295e6a533d745f6ca8085baec9 | 2026-03-04T20:56:49-08:00 | 35,890 | https://github.com/vllm-project/vllm/pull/35890 | [Perf] Use dummy M for weight prepacking on x86 (#35890) | [Perf] Use dummy M for weight prepacking on x86 (#35890)
Signed-off-by: Li, Tianmu <tianmu.li@intel.com> | csrc/cpu/dnnl_helper.cpp | cpp | Apache-2.0 | #include <list>
#include <optional>
#include "common/memory_desc.hpp"
#include "common/memory.hpp"
#include "cpu/utils.hpp"
#include "cpu/dnnl_helper.h"
static dnnl::engine& default_engine() {
static dnnl::engine engine(dnnl::engine::kind::cpu, 0);
return engine;
}
static dnnl::stream& default_stream() {
stat... | #include <list>
#include <optional>
#include "common/memory_desc.hpp"
#include "common/memory.hpp"
#include "cpu/utils.hpp"
#include "cpu/dnnl_helper.h"
static dnnl::engine& default_engine() {
static dnnl::engine engine(dnnl::engine::kind::cpu, 0);
return engine;
}
static dnnl::stream& default_stream() {
stat... | --- csrc/cpu/dnnl_helper.cpp
+++ csrc/cpu/dnnl_helper.cpp
@@ -237,13 +237,10 @@
};
dnnl::memory::desc original_b_md({b_k_size_, b_n_size_}, b_type_,
{b_k_stride_, b_n_stride_});
-#ifdef __aarch64__
+
// dummy M size for prepacking weights
// Prepacking weights improves pe... | 12 | 17 | 1 | [] | [
"CPU"
] | [] | Optimize this cpp kernel file from vllm (csrc/cpu/dnnl_helper.cpp).
Goal: [Perf] Use dummy M for weight prepacking on x86
Target hardware: CPU
Target models: unspecified
Current file:
```cpp
#include <list>
#include <optional>
#include "common/memory_desc.hpp"
#include "common/memory.hpp"
#include "cpu/utils.hpp"
#... | ## Purpose
On x86 systems without AMX, onednn weight prepacking without known M dimension results in ab layout instead of optimized blocked layouts. The PR uses existing dummy M method for ARM platforms to ensure proper weight prepacking.
## Test Plan
Platform: 2S EPYC 9755, DDR5-6400
Server:
```
export VLLM_CPU_KVCACH... | [] | null | null |
vllm | 7faba503c403bc8c562888df3a841b6df104d042 | 2026-03-04T20:47:17+02:00 | 35,397 | https://github.com/vllm-project/vllm/pull/35397 | [Kernel][Mamba] Optimize Mamba2 SSD prefill Triton kernels (#35397) | [Kernel][Mamba] Optimize Mamba2 SSD prefill Triton kernels (#35397)
Signed-off-by: Tomer Asida <57313761+tomeras91@users.noreply.github.com> | vllm/model_executor/layers/mamba/ops/mamba_ssm.py | triton | Apache-2.0 | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# Copyright (c) 2024, Tri Dao, Albert Gu.
# Adapted from https://github.com/state-spaces/mamba/blob/v2.2.4/mamba_ssm/ops/triton/selective_state_update.py
import torch
from packaging import version
from vllm imp... | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# Copyright (c) 2024, Tri Dao, Albert Gu.
# Adapted from https://github.com/state-spaces/mamba/blob/v2.2.4/mamba_ssm/ops/triton/selective_state_update.py
import torch
from packaging import version
from vllm imp... | --- vllm/model_executor/layers/mamba/ops/mamba_ssm.py
+++ vllm/model_executor/layers/mamba/ops/mamba_ssm.py
@@ -8,6 +8,7 @@
from packaging import version
from vllm import _custom_ops as ops
+from vllm.model_executor.layers.mamba.ops.triton_helpers import fast_exp
from vllm.triton_utils import HAS_TRITON, tl, trito... | 3 | 2 | 5 | [
"mamba"
] | [] | [] | Optimize this triton kernel file from vllm (vllm/model_executor/layers/mamba/ops/mamba_ssm.py).
Goal: [Kernel][Mamba] Optimize Mamba2 SSD prefill Triton kernels
Target hardware: unspecified
Target models: mamba
Current file:
```python
# SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contribut... | ## Purpose
Optimize Mamba2 SSD prefill Triton kernels through three changes, and clean up dead code.
### 1. Extended autotune search space
Added new Triton configs to `_chunk_scan_fwd_kernel`, `_chunk_state_fwd_kernel`, and `_chunk_cumsum_fwd_kernel`, covering:
- Higher warp counts (num_warps=8) for better memory lat... | [{"scope": "e2e", "hardware": "B200", "model": "nvidia/NVIDIA-Nemotron-3-Nano-30B-A3B-BF16", "shape": "ISL=50000,OSL=2048", "batch_size": 64, "metric": "Total token throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 55461, "optimized": 55941, "stated_speedup": null, "speedup": 1.0087}, {"scope": "e2e",... | 1.0778 | 1.0091 |
vllm | 7faba503c403bc8c562888df3a841b6df104d042 | 2026-03-04T20:47:17+02:00 | 35,397 | https://github.com/vllm-project/vllm/pull/35397 | [Kernel][Mamba] Optimize Mamba2 SSD prefill Triton kernels (#35397) | [Kernel][Mamba] Optimize Mamba2 SSD prefill Triton kernels (#35397)
Signed-off-by: Tomer Asida <57313761+tomeras91@users.noreply.github.com> | vllm/model_executor/layers/mamba/ops/ssd_chunk_scan.py | triton | Apache-2.0 | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# Copyright (c) 2024, Tri Dao, Albert Gu.
# Adapted from https://github.com/state-spaces/mamba/blob/v2.2.4/mamba_ssm/ops/triton/ssd_chunk_scan.py
# ruff: noqa: E501,SIM102
from packaging import version
from vl... | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# Copyright (c) 2024, Tri Dao, Albert Gu.
# Adapted from https://github.com/state-spaces/mamba/blob/v2.2.4/mamba_ssm/ops/triton/ssd_chunk_scan.py
# ruff: noqa: E501,SIM102
from packaging import version
from vl... | --- vllm/model_executor/layers/mamba/ops/ssd_chunk_scan.py
+++ vllm/model_executor/layers/mamba/ops/ssd_chunk_scan.py
@@ -8,6 +8,7 @@
from packaging import version
+from vllm.model_executor.layers.mamba.ops.triton_helpers import fast_exp
from vllm.triton_utils import tl, triton
TRITON_22 = version.parse(triton... | 73 | 2 | 5 | [
"mamba"
] | [] | [] | Optimize this triton kernel file from vllm (vllm/model_executor/layers/mamba/ops/ssd_chunk_scan.py).
Goal: [Kernel][Mamba] Optimize Mamba2 SSD prefill Triton kernels
Target hardware: unspecified
Target models: mamba
Current file:
```python
# SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright cont... | ## Purpose
Optimize Mamba2 SSD prefill Triton kernels through three changes, and clean up dead code.
### 1. Extended autotune search space
Added new Triton configs to `_chunk_scan_fwd_kernel`, `_chunk_state_fwd_kernel`, and `_chunk_cumsum_fwd_kernel`, covering:
- Higher warp counts (num_warps=8) for better memory lat... | [{"scope": "e2e", "hardware": "B200", "model": "nvidia/NVIDIA-Nemotron-3-Nano-30B-A3B-BF16", "shape": "ISL=50000,OSL=2048", "batch_size": 64, "metric": "Total token throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 55461, "optimized": 55941, "stated_speedup": null, "speedup": 1.0087}, {"scope": "e2e",... | 1.0778 | 1.0091 |
vllm | 7faba503c403bc8c562888df3a841b6df104d042 | 2026-03-04T20:47:17+02:00 | 35,397 | https://github.com/vllm-project/vllm/pull/35397 | [Kernel][Mamba] Optimize Mamba2 SSD prefill Triton kernels (#35397) | [Kernel][Mamba] Optimize Mamba2 SSD prefill Triton kernels (#35397)
Signed-off-by: Tomer Asida <57313761+tomeras91@users.noreply.github.com> | vllm/model_executor/layers/mamba/ops/ssd_chunk_state.py | triton | Apache-2.0 | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# Copyright (c) 2024, Tri Dao, Albert Gu.
# Adapted from https://github.com/state-spaces/mamba/blob/v2.2.4/mamba_ssm/ops/triton/ssd_chunk_state.py
# ruff: noqa: E501
import torch
from vllm.triton_utils import ... | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# Copyright (c) 2024, Tri Dao, Albert Gu.
# Adapted from https://github.com/state-spaces/mamba/blob/v2.2.4/mamba_ssm/ops/triton/ssd_chunk_state.py
# ruff: noqa: E501
import torch
from vllm.model_executor.layer... | --- vllm/model_executor/layers/mamba/ops/ssd_chunk_state.py
+++ vllm/model_executor/layers/mamba/ops/ssd_chunk_state.py
@@ -8,6 +8,7 @@
import torch
+from vllm.model_executor.layers.mamba.ops.triton_helpers import fast_exp
from vllm.triton_utils import tl, triton
from .mamba_ssm import softplus
@@ -116,6 +117,... | 30 | 319 | 5 | [
"mamba"
] | [] | [] | Optimize this triton kernel file from vllm (vllm/model_executor/layers/mamba/ops/ssd_chunk_state.py).
Goal: [Kernel][Mamba] Optimize Mamba2 SSD prefill Triton kernels
Target hardware: unspecified
Target models: mamba
Current file:
```python
# SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright con... | ## Purpose
Optimize Mamba2 SSD prefill Triton kernels through three changes, and clean up dead code.
### 1. Extended autotune search space
Added new Triton configs to `_chunk_scan_fwd_kernel`, `_chunk_state_fwd_kernel`, and `_chunk_cumsum_fwd_kernel`, covering:
- Higher warp counts (num_warps=8) for better memory lat... | [{"scope": "e2e", "hardware": "B200", "model": "nvidia/NVIDIA-Nemotron-3-Nano-30B-A3B-BF16", "shape": "ISL=50000,OSL=2048", "batch_size": 64, "metric": "Total token throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 55461, "optimized": 55941, "stated_speedup": null, "speedup": 1.0087}, {"scope": "e2e",... | 1.0778 | 1.0091 |
vllm | 7faba503c403bc8c562888df3a841b6df104d042 | 2026-03-04T20:47:17+02:00 | 35,397 | https://github.com/vllm-project/vllm/pull/35397 | [Kernel][Mamba] Optimize Mamba2 SSD prefill Triton kernels (#35397) | [Kernel][Mamba] Optimize Mamba2 SSD prefill Triton kernels (#35397)
Signed-off-by: Tomer Asida <57313761+tomeras91@users.noreply.github.com> | vllm/model_executor/layers/mamba/ops/ssd_state_passing.py | triton | Apache-2.0 | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# Copyright (c) 2024, Tri Dao, Albert Gu.
# Adapted from https://github.com/state-spaces/mamba/blob/v2.2.4/mamba_ssm/ops/triton/ssd_state_passing.py
# ruff: noqa: E501
import torch
from vllm.triton_utils impor... | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# Copyright (c) 2024, Tri Dao, Albert Gu.
# Adapted from https://github.com/state-spaces/mamba/blob/v2.2.4/mamba_ssm/ops/triton/ssd_state_passing.py
# ruff: noqa: E501
import torch
from vllm.model_executor.lay... | --- vllm/model_executor/layers/mamba/ops/ssd_state_passing.py
+++ vllm/model_executor/layers/mamba/ops/ssd_state_passing.py
@@ -8,6 +8,7 @@
import torch
+from vllm.model_executor.layers.mamba.ops.triton_helpers import fast_exp
from vllm.triton_utils import tl, triton
@@ -29,12 +30,9 @@
out_ptr,
dA_c... | 29 | 40 | 5 | [
"mamba"
] | [] | [] | Optimize this triton kernel file from vllm (vllm/model_executor/layers/mamba/ops/ssd_state_passing.py).
Goal: [Kernel][Mamba] Optimize Mamba2 SSD prefill Triton kernels
Target hardware: unspecified
Target models: mamba
Current file:
```python
# SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright c... | ## Purpose
Optimize Mamba2 SSD prefill Triton kernels through three changes, and clean up dead code.
### 1. Extended autotune search space
Added new Triton configs to `_chunk_scan_fwd_kernel`, `_chunk_state_fwd_kernel`, and `_chunk_cumsum_fwd_kernel`, covering:
- Higher warp counts (num_warps=8) for better memory lat... | [{"scope": "e2e", "hardware": "B200", "model": "nvidia/NVIDIA-Nemotron-3-Nano-30B-A3B-BF16", "shape": "ISL=50000,OSL=2048", "batch_size": 64, "metric": "Total token throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 55461, "optimized": 55941, "stated_speedup": null, "speedup": 1.0087}, {"scope": "e2e",... | 1.0778 | 1.0091 |
vllm | 16d2ad1d384e8b3d89434ae60508b26d0ce6ac99 | 2026-03-04T17:49:47+08:00 | 30,681 | https://github.com/vllm-project/vllm/pull/30681 | [Hardware] Replace `torch.cuda.empty_cache` with `torch.accelerator.empty_cache` (#30681) | [Hardware] Replace `torch.cuda.empty_cache` with `torch.accelerator.empty_cache` (#30681)
Signed-off-by: Kunshang Ji <kunshang.ji@intel.com>
Signed-off-by: Kunshang Ji <jikunshang95@gmail.com>
Co-authored-by: Harry Mellor <19981378+hmellor@users.noreply.github.com> | vllm/model_executor/layers/quantization/utils/fp8_utils.py | triton | Apache-2.0 | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# Adapted from https://github.com/sgl-project/sglang/pull/2575
import functools
import json
import os
from collections.abc import Callable, Sequence
from typing import Any
import torch
import vllm.envs as envs
... | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# Adapted from https://github.com/sgl-project/sglang/pull/2575
import functools
import json
import os
from collections.abc import Callable, Sequence
from typing import Any
import torch
import vllm.envs as envs
... | --- vllm/model_executor/layers/quantization/utils/fp8_utils.py
+++ vllm/model_executor/layers/quantization/utils/fp8_utils.py
@@ -1407,7 +1407,7 @@
import torch.nn.functional as F
weight = F.pad(weight, (0, num_pad), "constant", 0)[..., :-num_pad]
- torch.cuda.empty_cache()
+ torch.acc... | 1 | 1 | 3 | [] | [] | [] | Optimize this triton kernel file from vllm (vllm/model_executor/layers/quantization/utils/fp8_utils.py).
Goal: [Hardware] Replace `torch.cuda.empty_cache` with `torch.accelerator.empty_cache`
Target hardware: unspecified
Target models: unspecified
Current file:
```python
# SPDX-License-Identifier: Apache-2.0
# SPDX-F... | <!-- markdownlint-disable -->
## Purpose
vLLM is a framework support multi hardware backend. while there are some torch.cuda hard call. this is unfriendly to non-cuda compatible device. fortunately, there is a new set of `torch.accelerator` API which can dispatch based on platform.
I will try to create a series of PR ... | [] | null | null |
vllm | 38c498b8e3aaec95049f384edfc56ca12cbe1839 | 2026-02-27T02:51:28+02:00 | 35,121 | https://github.com/vllm-project/vllm/pull/35121 | [Performance] Cublas Bf16 Gate with Fp32 Output (#35121) | [Performance] Cublas Bf16 Gate with Fp32 Output (#35121)
Signed-off-by: Roi Koren <roik@nvidia.com> | csrc/moe/moe_ops.h | cpp | Apache-2.0 | #pragma once
#include <torch/all.h>
void topk_softmax(torch::Tensor& topk_weights, torch::Tensor& topk_indices,
torch::Tensor& token_expert_indices,
torch::Tensor& gating_output, bool renormalize,
std::optional<torch::Tensor> bias);
void topk_sigmoid(torch::Tenso... | #pragma once
#include <torch/all.h>
void topk_softmax(torch::Tensor& topk_weights, torch::Tensor& topk_indices,
torch::Tensor& token_expert_indices,
torch::Tensor& gating_output, bool renormalize,
std::optional<torch::Tensor> bias);
void topk_sigmoid(torch::Tenso... | --- csrc/moe/moe_ops.h
+++ csrc/moe/moe_ops.h
@@ -58,6 +58,10 @@
torch::Tensor& output_tensor);
#ifndef USE_ROCM
+// cuBLAS bf16 x bf16 -> fp32 router GEMM (fallback for non-SM90 / batch > 16)
+torch::Tensor router_gemm_bf16_fp32(torch::Tensor const& input,
+ tor... | 4 | 0 | 3 | [] | [] | [] | Optimize this cpp kernel file from vllm (csrc/moe/moe_ops.h).
Goal: [Performance] Cublas Bf16 Gate with Fp32 Output
Target hardware: unspecified
Target models: unspecified
Current file:
```cpp
#pragma once
#include <torch/all.h>
void topk_softmax(torch::Tensor& topk_weights, torch::Tensor& topk_indices,
... | ## Purpose
Introduces `GateLinear`, a specialized MoE gate linear layer with three-tier GEMM dispatch for router logits:
1. **Tier 1 — DSV3 specialized kernel** (SM90+, batch ≤ 16, supported dims): highest throughput for small batches
2. **Tier 2 — cuBLAS bf16×bf16→fp32** (SM90+, bf16 weights, fp32 out_dtype): fp32-a... | [{"scope": "kernel", "hardware": "H100", "model": "DeepSeek-V3", "shape": "hidden=7168,experts=256", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 18.5, "optimized": 11.8, "stated_speedup": null, "speedup": 1.5678}, {"scope": "kernel", "hardware": "H100", "model": "DeepSeek-... | 1.5339 | null |
vllm | 38c498b8e3aaec95049f384edfc56ca12cbe1839 | 2026-02-27T02:51:28+02:00 | 35,121 | https://github.com/vllm-project/vllm/pull/35121 | [Performance] Cublas Bf16 Gate with Fp32 Output (#35121) | [Performance] Cublas Bf16 Gate with Fp32 Output (#35121)
Signed-off-by: Roi Koren <roik@nvidia.com> | csrc/moe/torch_bindings.cpp | cpp | Apache-2.0 | #include "core/registration.h"
#include "moe_ops.h"
TORCH_LIBRARY_EXPAND(TORCH_EXTENSION_NAME, m) {
// Apply topk softmax to the gating outputs.
m.def(
"topk_softmax(Tensor! topk_weights, Tensor! topk_indices, Tensor! "
"token_expert_indices, Tensor gating_output, bool renormalize, Tensor? "
"bia... | #include "core/registration.h"
#include "moe_ops.h"
TORCH_LIBRARY_EXPAND(TORCH_EXTENSION_NAME, m) {
// Apply topk softmax to the gating outputs.
m.def(
"topk_softmax(Tensor! topk_weights, Tensor! topk_indices, Tensor! "
"token_expert_indices, Tensor gating_output, bool renormalize, Tensor? "
"bia... | --- csrc/moe/torch_bindings.cpp
+++ csrc/moe/torch_bindings.cpp
@@ -125,6 +125,10 @@
"Tensor)");
m.impl("grouped_topk", torch::kCUDA, &grouped_topk);
+ // cuBLAS bf16 x bf16 -> fp32 router GEMM (fallback for non-SM90 / batch > 16)
+ m.def("router_gemm_bf16_fp32(Tensor input, Tensor weight) -> Tensor");
+ ... | 4 | 0 | 3 | [] | [] | [] | Optimize this cpp kernel file from vllm (csrc/moe/torch_bindings.cpp).
Goal: [Performance] Cublas Bf16 Gate with Fp32 Output
Target hardware: unspecified
Target models: unspecified
Current file:
```cpp
#include "core/registration.h"
#include "moe_ops.h"
TORCH_LIBRARY_EXPAND(TORCH_EXTENSION_NAME, m) {
// Apply topk... | ## Purpose
Introduces `GateLinear`, a specialized MoE gate linear layer with three-tier GEMM dispatch for router logits:
1. **Tier 1 — DSV3 specialized kernel** (SM90+, batch ≤ 16, supported dims): highest throughput for small batches
2. **Tier 2 — cuBLAS bf16×bf16→fp32** (SM90+, bf16 weights, fp32 out_dtype): fp32-a... | [{"scope": "kernel", "hardware": "H100", "model": "DeepSeek-V3", "shape": "hidden=7168,experts=256", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 18.5, "optimized": 11.8, "stated_speedup": null, "speedup": 1.5678}, {"scope": "kernel", "hardware": "H100", "model": "DeepSeek-... | 1.5339 | null |
vllm | 98217b09f9ce22429ce35badfa1d50e1f4fe4137 | 2026-02-26T22:29:01+01:00 | 35,422 | https://github.com/vllm-project/vllm/pull/35422 | [Performance] Extract KV cache update op from flashinfer forward (#35422) | [Performance] Extract KV cache update op from flashinfer forward (#35422)
Signed-off-by: ElizaWszola <ewszola@redhat.com> | vllm/v1/attention/backends/flashinfer.py | triton | Apache-2.0 | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
"""Attention layer with FlashInfer."""
from dataclasses import dataclass
from typing import ClassVar
import numpy as np
import torch
from flashinfer import (
BatchDecodeWithPagedKVCacheWrapper,
BatchPref... | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
"""Attention layer with FlashInfer."""
from dataclasses import dataclass
from typing import ClassVar
import numpy as np
import torch
from flashinfer import (
BatchDecodeWithPagedKVCacheWrapper,
BatchPref... | --- vllm/v1/attention/backends/flashinfer.py
+++ vllm/v1/attention/backends/flashinfer.py
@@ -380,6 +380,8 @@
if capability is not None and capability.major == 10:
return "HND"
return None
+
+ forward_includes_kv_cache_update: bool = False
@dataclass
@@ -1330,32 +1332,15 @@
... | 38 | 26 | 1 | [] | [] | [] | Optimize this triton kernel file from vllm (vllm/v1/attention/backends/flashinfer.py).
Goal: [Performance] Extract KV cache update op from flashinfer forward
Target hardware: unspecified
Target models: unspecified
Current file:
```python
# SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contri... | Extract KV cache update op from flashinfer similar to https://github.com/vllm-project/vllm/pull/25954
This PR is a part of https://github.com/vllm-project/vllm/issues/32335
#### Eval (`Qwen/Qwen3-30B-A3B-FP8`):
main:
|Tasks|Version| Filter |n-shot| Metric | |Value | |Stderr|
|-----|------:|-------------... | [] | null | null |
vllm | cd4367366814f1d1404e263e621a2b15c117eaf6 | 2026-02-25T14:25:24+08:00 | 34,424 | https://github.com/vllm-project/vllm/pull/34424 | [Perf] Optimize FP8 gemm of sm120. (#34424) | [Perf] Optimize FP8 gemm of sm120. (#34424)
Signed-off-by: wenshuai <wenshuai@xiaomi.com> | csrc/quantization/w8a8/cutlass/c3x/scaled_mm_sm120_fp8_dispatch.cuh | cuda | Apache-2.0 | #pragma once
#include "scaled_mm.cuh"
#include "cutlass_gemm_caller.cuh"
/**
* This file defines Gemm kernel configurations for SM120 (fp8) based on the
* Gemm shape.
*/
namespace vllm {
using c3x::cutlass_gemm_caller;
template <typename InType, typename OutType,
template <typename, typename, typename... | #pragma once
#include "scaled_mm.cuh"
#include "cutlass_gemm_caller.cuh"
/**
* This file defines Gemm kernel configurations for SM120 (fp8) based on the
* Gemm shape.
*/
namespace vllm {
using c3x::cutlass_gemm_caller;
// Custom wrapper to allow specifying EpilogueTile for small M
template <typename ElementAB_,... | --- csrc/quantization/w8a8/cutlass/c3x/scaled_mm_sm120_fp8_dispatch.cuh
+++ csrc/quantization/w8a8/cutlass/c3x/scaled_mm_sm120_fp8_dispatch.cuh
@@ -11,6 +11,68 @@
namespace vllm {
using c3x::cutlass_gemm_caller;
+
+// Custom wrapper to allow specifying EpilogueTile for small M
+template <typename ElementAB_, typena... | 132 | 0 | 1 | [] | [
"SM120"
] | [] | Optimize this cuda kernel file from vllm (csrc/quantization/w8a8/cutlass/c3x/scaled_mm_sm120_fp8_dispatch.cuh).
Goal: [Perf] Optimize FP8 gemm of sm120.
Target hardware: SM120
Target models: unspecified
Current file:
```cuda
#pragma once
#include "scaled_mm.cuh"
#include "cutlass_gemm_caller.cuh"
/**
* This file d... | ## Purpose
Optimize FP8 gemm of sm120 at any input shape.
## Test Plan
benchmarks/kernels# python3 bench_fp8_gemm.py
run bench_fp8_gemm.py and compare the results with the patch or not.
## Test Result
**the current restut without the patch**
```
root@de-22309-vllm-0-15-1-5090-0211172246-79ccd9bbf9-6jfzz:/vllm/benchma... | [] | null | null |
vllm | 34ce0ffd1f3c7b5e2bcc6073dd1525f266133755 | 2026-02-24T20:55:39+05:30 | 34,434 | https://github.com/vllm-project/vllm/pull/34434 | [CPU][Perf] Accelerate Attention head for s390x using vector intrinsics (#34434) | [CPU][Perf] Accelerate Attention head for s390x using vector intrinsics (#34434)
Signed-off-by: Rehan Khan <Rehan.Khan7@ibm.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com> | csrc/cpu/cpu_attn.cpp | cpp | Apache-2.0 | #include "cpu_attn_dispatch_generated.h"
torch::Tensor get_scheduler_metadata(
const int64_t num_req, const int64_t num_heads_q,
const int64_t num_heads_kv, const int64_t head_dim,
const torch::Tensor& seq_lens, at::ScalarType dtype,
const torch::Tensor& query_start_loc, const bool casual,
const in... | #include "cpu_attn_dispatch_generated.h"
torch::Tensor get_scheduler_metadata(
const int64_t num_req, const int64_t num_heads_q,
const int64_t num_heads_kv, const int64_t head_dim,
const torch::Tensor& seq_lens, at::ScalarType dtype,
const torch::Tensor& query_start_loc, const bool casual,
const in... | --- csrc/cpu/cpu_attn.cpp
+++ csrc/cpu/cpu_attn.cpp
@@ -16,6 +16,8 @@
isa = cpu_attention::ISA::VEC16;
} else if (isa_hint == "neon") {
isa = cpu_attention::ISA::NEON;
+ } else if (isa_hint == "vxe") {
+ isa = cpu_attention::ISA::VXE;
} else {
TORCH_CHECK(false, "Unsupported CPU attention ISA h... | 4 | 0 | 4 | [] | [
"CPU"
] | [] | Optimize this cpp kernel file from vllm (csrc/cpu/cpu_attn.cpp).
Goal: [CPU][Perf] Accelerate Attention head for s390x using vector intrinsics
Target hardware: CPU
Target models: unspecified
Current file:
```cpp
#include "cpu_attn_dispatch_generated.h"
torch::Tensor get_scheduler_metadata(
const int64_t num_req,... | ## Purpose
Accelerate paged attention GEMMs (QK, PV) on s390x with vector intrinsics
This PR accelerates `cpu_attention_with_kv_cache `on s390x by introducing VXE (Vector Extension Facility) optimized GEMM kernels for both QK and PV attention phases. The vectorized implementation significantly improves token generation... | [] | null | null |
vllm | 34ce0ffd1f3c7b5e2bcc6073dd1525f266133755 | 2026-02-24T20:55:39+05:30 | 34,434 | https://github.com/vllm-project/vllm/pull/34434 | [CPU][Perf] Accelerate Attention head for s390x using vector intrinsics (#34434) | [CPU][Perf] Accelerate Attention head for s390x using vector intrinsics (#34434)
Signed-off-by: Rehan Khan <Rehan.Khan7@ibm.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com> | csrc/cpu/cpu_attn_impl.hpp | cpp | Apache-2.0 | #ifndef CPU_ATTN_HPP
#define CPU_ATTN_HPP
#include <type_traits>
#include <cstddef>
#if defined(__APPLE__)
#include <sys/sysctl.h>
#endif
#include "cpu/cpu_arch_macros.h"
#include "cpu/utils.hpp"
namespace cpu_attention {
enum class ISA { AMX, VEC, VEC16, NEON };
template <ISA isa, typename scalar_t, int64_t hea... | #ifndef CPU_ATTN_HPP
#define CPU_ATTN_HPP
#include <type_traits>
#include <cstddef>
#if defined(__APPLE__)
#include <sys/sysctl.h>
#endif
#include "cpu/cpu_arch_macros.h"
#include "cpu/utils.hpp"
namespace cpu_attention {
enum class ISA { AMX, VEC, VEC16, NEON, VXE };
template <ISA isa, typename scalar_t, int64_... | --- csrc/cpu/cpu_attn_impl.hpp
+++ csrc/cpu/cpu_attn_impl.hpp
@@ -12,7 +12,7 @@
#include "cpu/utils.hpp"
namespace cpu_attention {
-enum class ISA { AMX, VEC, VEC16, NEON };
+enum class ISA { AMX, VEC, VEC16, NEON, VXE };
template <ISA isa, typename scalar_t, int64_t head_dim>
class AttentionImpl {}; | 1 | 1 | 4 | [] | [
"CPU"
] | [] | Optimize this cpp kernel file from vllm (csrc/cpu/cpu_attn_impl.hpp).
Goal: [CPU][Perf] Accelerate Attention head for s390x using vector intrinsics
Target hardware: CPU
Target models: unspecified
Current file:
```cpp
#ifndef CPU_ATTN_HPP
#define CPU_ATTN_HPP
#include <type_traits>
#include <cstddef>
#if defined(__A... | ## Purpose
Accelerate paged attention GEMMs (QK, PV) on s390x with vector intrinsics
This PR accelerates `cpu_attention_with_kv_cache `on s390x by introducing VXE (Vector Extension Facility) optimized GEMM kernels for both QK and PV attention phases. The vectorized implementation significantly improves token generation... | [] | null | null |
vllm | 22a97e66134a26c74b9dae73d9446c4e32718269 | 2026-02-23T19:01:28-05:00 | 34,846 | https://github.com/vllm-project/vllm/pull/34846 | [Perf] Improve default triton fused moe configs (#34846) | [Perf] Improve default triton fused moe configs (#34846)
Signed-off-by: mgoin <mgoin64@gmail.com>
Co-authored-by: Robert Shaw <114415538+robertgshaw2-redhat@users.noreply.github.com> | vllm/model_executor/layers/fused_moe/fused_moe.py | triton | Apache-2.0 | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
"""Fused MoE Triton kernels."""
import functools
import json
import os
from collections.abc import Callable
from typing import Any
import torch
import vllm.envs as envs
import vllm.model_executor.layers.fused_m... | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
"""Fused MoE Triton kernels."""
import functools
import json
import os
from collections.abc import Callable
from typing import Any
import torch
import vllm.envs as envs
import vllm.model_executor.layers.fused_m... | --- vllm/model_executor/layers/fused_moe/fused_moe.py
+++ vllm/model_executor/layers/fused_moe/fused_moe.py
@@ -1233,28 +1233,31 @@
block_shape: list[int] | None = None,
) -> dict[str, int]:
if vllm_is_batch_invariant():
- config = {
+ return {
"BLOCK_SIZE_M": 64,
"BLO... | 56 | 22 | 1 | [] | [] | [] | Optimize this triton kernel file from vllm (vllm/model_executor/layers/fused_moe/fused_moe.py).
Goal: [Perf] Improve default triton fused moe configs
Target hardware: unspecified
Target models: unspecified
Current file:
```python
# SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors t... | <!-- markdownlint-disable -->
## Purpose
Improve the default Triton fused MoE kernel configs when no tuned config file is available. The old defaults were chosen without much consideration: `BLOCK_SIZE_K=32` matched <1% of tuned configs, `num_warps`/`num_stages` were never set, and there was no batch-size awareness. ... | [{"scope": "kernel", "hardware": "H100", "model": "Mixtral", "shape": "E=8,N=7168,K=4096,topk=2", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 267.13, "optimized": 251.48, "stated_speedup": 0.94, "speedup": 1.0622}, {"scope": "kernel", "hardware": "H100", "model": "Mixtral"... | 0.99 | null |
vllm | 8435b2e0492525b2ae7361b7f0081febb483bb34 | 2026-02-23T09:02:26-05:00 | 34,302 | https://github.com/vllm-project/vllm/pull/34302 | [ModelBash][DSV3] Add TRTLLM DSV3 Router GEMM kernel (6% B1 Speedup) (#34302) | [ModelBash][DSV3] Add TRTLLM DSV3 Router GEMM kernel (6% B1 Speedup) (#34302)
Signed-off-by: Robert Shaw <robshaw@redhat.com>
Co-authored-by: Robert Shaw <robshaw@redhat.com> | csrc/moe/moe_ops.h | cpp | Apache-2.0 | #pragma once
#include <torch/all.h>
void topk_softmax(torch::Tensor& topk_weights, torch::Tensor& topk_indices,
torch::Tensor& token_expert_indices,
torch::Tensor& gating_output, bool renormalize,
std::optional<torch::Tensor> bias);
void topk_sigmoid(torch::Tenso... | #pragma once
#include <torch/all.h>
void topk_softmax(torch::Tensor& topk_weights, torch::Tensor& topk_indices,
torch::Tensor& token_expert_indices,
torch::Tensor& gating_output, bool renormalize,
std::optional<torch::Tensor> bias);
void topk_sigmoid(torch::Tenso... | --- csrc/moe/moe_ops.h
+++ csrc/moe/moe_ops.h
@@ -56,3 +56,14 @@
void shuffle_rows(const torch::Tensor& input_tensor,
const torch::Tensor& dst2src_map,
torch::Tensor& output_tensor);
+
+#ifndef USE_ROCM
+// DeepSeek V3 optimized router GEMM kernel for SM90+
+// Computes output = m... | 11 | 0 | 2 | [
"deepseek"
] | [] | [] | Optimize this cpp kernel file from vllm (csrc/moe/moe_ops.h).
Goal: [ModelBash][DSV3] Add TRTLLM DSV3 Router GEMM kernel (6% B1 Speedup)
Target hardware: unspecified
Target models: deepseek
Current file:
```cpp
#pragma once
#include <torch/all.h>
void topk_softmax(torch::Tensor& topk_weights, torch::Tensor& topk_in... | Port the optimized router GEMM kernel from sglang's sgl-kernel for DeepSeek V3 MoE models. This kernel is specifically optimized for small batch sizes (1-16 tokens) common in decode phase. The kernel is originally adapted from TRTLLM.
- original PR: https://github.com/sgl-project/sglang/pull/7627/changes
Key features:... | [{"scope": "e2e", "hardware": null, "model": "DeepSeek-V3", "shape": "hidden_dim=7168,num_experts=256/384", "batch_size": 1, "metric": "output token throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 109.58, "optimized": 115.65, "stated_speedup": null, "speedup": 1.0554}, {"scope": "e2e", "hardware": n... | 1.06 | 1.0554 |
vllm | 8435b2e0492525b2ae7361b7f0081febb483bb34 | 2026-02-23T09:02:26-05:00 | 34,302 | https://github.com/vllm-project/vllm/pull/34302 | [ModelBash][DSV3] Add TRTLLM DSV3 Router GEMM kernel (6% B1 Speedup) (#34302) | [ModelBash][DSV3] Add TRTLLM DSV3 Router GEMM kernel (6% B1 Speedup) (#34302)
Signed-off-by: Robert Shaw <robshaw@redhat.com>
Co-authored-by: Robert Shaw <robshaw@redhat.com> | csrc/moe/torch_bindings.cpp | cpp | Apache-2.0 | #include "core/registration.h"
#include "moe_ops.h"
TORCH_LIBRARY_EXPAND(TORCH_EXTENSION_NAME, m) {
// Apply topk softmax to the gating outputs.
m.def(
"topk_softmax(Tensor! topk_weights, Tensor! topk_indices, Tensor! "
"token_expert_indices, Tensor gating_output, bool renormalize, Tensor? "
"bia... | #include "core/registration.h"
#include "moe_ops.h"
TORCH_LIBRARY_EXPAND(TORCH_EXTENSION_NAME, m) {
// Apply topk softmax to the gating outputs.
m.def(
"topk_softmax(Tensor! topk_weights, Tensor! topk_indices, Tensor! "
"token_expert_indices, Tensor gating_output, bool renormalize, Tensor? "
"bia... | --- csrc/moe/torch_bindings.cpp
+++ csrc/moe/torch_bindings.cpp
@@ -124,6 +124,10 @@
"routed_scaling_factor, Tensor bias, int scoring_func) -> (Tensor, "
"Tensor)");
m.impl("grouped_topk", torch::kCUDA, &grouped_topk);
+
+ // DeepSeek V3 optimized router GEMM for SM90+
+ m.def("dsv3_router_gemm(Tenso... | 4 | 0 | 2 | [
"deepseek"
] | [] | [] | Optimize this cpp kernel file from vllm (csrc/moe/torch_bindings.cpp).
Goal: [ModelBash][DSV3] Add TRTLLM DSV3 Router GEMM kernel (6% B1 Speedup)
Target hardware: unspecified
Target models: deepseek
Current file:
```cpp
#include "core/registration.h"
#include "moe_ops.h"
TORCH_LIBRARY_EXPAND(TORCH_EXTENSION_NAME, m)... | Port the optimized router GEMM kernel from sglang's sgl-kernel for DeepSeek V3 MoE models. This kernel is specifically optimized for small batch sizes (1-16 tokens) common in decode phase. The kernel is originally adapted from TRTLLM.
- original PR: https://github.com/sgl-project/sglang/pull/7627/changes
Key features:... | [{"scope": "e2e", "hardware": null, "model": "DeepSeek-V3", "shape": "hidden_dim=7168,num_experts=256/384", "batch_size": 1, "metric": "output token throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 109.58, "optimized": 115.65, "stated_speedup": null, "speedup": 1.0554}, {"scope": "e2e", "hardware": n... | 1.06 | 1.0554 |
vllm | 2aab2bb54366c5a26add1b07f107b86f7fe28ff5 | 2026-02-20T20:32:05-08:00 | 34,541 | https://github.com/vllm-project/vllm/pull/34541 | [ROCM] Optimize ROCM_AITER_FA spec decode eagle performance (#34541) | [ROCM] Optimize ROCM_AITER_FA spec decode eagle performance (#34541)
Signed-off-by: jennyyyyzhen <yzhen@hmc.edu> | vllm/v1/attention/backends/rocm_aiter_fa.py | triton | Apache-2.0 | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
"""Attention layer with AiterFlashAttention."""
from dataclasses import dataclass
from typing import ClassVar
import torch
from vllm._aiter_ops import rocm_aiter_ops
from vllm.config import VllmConfig, get_laye... | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
"""Attention layer with AiterFlashAttention."""
from dataclasses import dataclass
from typing import ClassVar
import torch
from vllm._aiter_ops import rocm_aiter_ops
from vllm.config import VllmConfig, get_laye... | --- vllm/v1/attention/backends/rocm_aiter_fa.py
+++ vllm/v1/attention/backends/rocm_aiter_fa.py
@@ -396,8 +396,7 @@
class AiterFlashAttentionMetadataBuilder(
AttentionMetadataBuilder[AiterFlashAttentionMetadata]
):
- _cudagraph_support = AttentionCGSupport.UNIFORM_SINGLE_TOKEN_DECODE
- reorder_batch_thresh... | 50 | 2 | 1 | [] | [
"ROCM"
] | [] | Optimize this triton kernel file from vllm (vllm/v1/attention/backends/rocm_aiter_fa.py).
Goal: [ROCM] Optimize ROCM_AITER_FA spec decode eagle performance
Target hardware: ROCM
Target models: unspecified
Current file:
```python
# SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to... | ## Purpose
This PR has dependency on #32877, which fixes accuracy issue of rocm aiter fa.
**Changes:**
- Change cudagraph_support to UNIFORM_BATCH to support decode cudagraph when num_speculative_tokens >0
- Override build_for_drafting and remove cpu-gpu sync, so cudagraph can also work for draft model.
**Trace**
Be... | [] | null | null |
vllm | b1c4f0b26548d36fca304b298957e4791eafa09b | 2026-02-20T01:34:45-08:00 | 34,206 | https://github.com/vllm-project/vllm/pull/34206 | [Kernel] Optimize grouped topk kernel (#34206) | [Kernel] Optimize grouped topk kernel (#34206)
Signed-off-by: Xin Yang <xyangx@amazon.com> | csrc/moe/grouped_topk_kernels.cu | cuda | Apache-2.0 | /*
* Adapted from
* https://github.com/NVIDIA/TensorRT-LLM/blob/v0.21.0/cpp/tensorrt_llm/kernels/noAuxTcKernels.cu
* Copyright (c) 2025, The vLLM team.
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION &
* AFFILIATES. All rights reserved. SPDX-License-Identifier: Apache-2.0
*
* Licensed under ... | /*
* Adapted from
* https://github.com/NVIDIA/TensorRT-LLM/blob/v1.3.0rc2/cpp/tensorrt_llm/kernels/noAuxTcKernels.cu
* Copyright (c) 2025, The vLLM team.
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION &
* AFFILIATES. All rights reserved. SPDX-License-Identifier: Apache-2.0
*
* Licensed unde... | --- csrc/moe/grouped_topk_kernels.cu
+++ csrc/moe/grouped_topk_kernels.cu
@@ -1,6 +1,6 @@
/*
* Adapted from
- * https://github.com/NVIDIA/TensorRT-LLM/blob/v0.21.0/cpp/tensorrt_llm/kernels/noAuxTcKernels.cu
+ * https://github.com/NVIDIA/TensorRT-LLM/blob/v1.3.0rc2/cpp/tensorrt_llm/kernels/noAuxTcKernels.cu
* Copyr... | 375 | 96 | 1 | [] | [] | [] | Optimize this cuda kernel file from vllm (csrc/moe/grouped_topk_kernels.cu).
Goal: [Kernel] Optimize grouped topk kernel
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Adapted from
* https://github.com/NVIDIA/TensorRT-LLM/blob/v0.21.0/cpp/tensorrt_llm/kernels/noAuxTcKernels.cu
*... | ## Purpose
This PR add grouped topk kernel optimized for small expert count (num_experts<=512 for single group, or num_experts<=256 for multi group), which covers DeepSeek (num_experts=256, n_group=8), Kimi-K2.5 (num_experts=384, n_group=1), Nemotron (num_experts=512, n_group=1) etc.
For large expert count, fall back... | [{"scope": "kernel", "hardware": "H200", "model": "DeepSeek-R1", "shape": "num_experts=256, n_group=8", "batch_size": null, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 7, "optimized": 4, "stated_speedup": null, "speedup": 1.75}, {"scope": "e2e", "hardware": null, "model": "DeepSeek-R1", "s... | 1.75 | 1.0156 |
vllm | 6874638bc443ae99ee900072e0bb039fa5f7f0e7 | 2026-02-18T10:42:36-05:00 | 34,758 | https://github.com/vllm-project/vllm/pull/34758 | [Model Bash] DeepSeek R1 BF16 Min Latency QKV A GEMM (0.5% E2E Speedup) (#34758) | [Model Bash] DeepSeek R1 BF16 Min Latency QKV A GEMM (0.5% E2E Speedup) (#34758)
Signed-off-by: Robert Shaw <robshaw@redhat.com>
Co-authored-by: Robert Shaw <robshaw@redhat.com> | csrc/ops.h | cpp | Apache-2.0 | #pragma once
#include <optional>
#include <torch/library.h>
#include <tuple>
#include "core/scalar_type.hpp"
#include <vector>
torch::Tensor weak_ref_tensor(torch::Tensor& tensor) {
// Ensure tensor is on CUDA
if (!tensor.is_cuda()) {
throw std::runtime_error("Tensor must be on CUDA device");
}
// Get ... | #pragma once
#include <optional>
#include <torch/library.h>
#include <tuple>
#include "core/scalar_type.hpp"
#include <vector>
torch::Tensor weak_ref_tensor(torch::Tensor& tensor) {
// Ensure tensor is on CUDA
if (!tensor.is_cuda()) {
throw std::runtime_error("Tensor must be on CUDA device");
}
// Get ... | --- csrc/ops.h
+++ csrc/ops.h
@@ -410,3 +410,8 @@
int64_t quant_level, bool cast_bf2half = false);
int64_t qr_max_size();
#endif
+
+#ifndef USE_ROCM
+void dsv3_fused_a_gemm(torch::Tensor& output, torch::Tensor const& mat_a,
+ torch::Tensor const& mat_b);
+#endif | 5 | 0 | 3 | [
"deepseek"
] | [] | [] | Optimize this cpp kernel file from vllm (csrc/ops.h).
Goal: [Model Bash] DeepSeek R1 BF16 Min Latency QKV A GEMM (0.5% E2E Speedup)
Target hardware: unspecified
Target models: deepseek
Current file:
```cpp
#pragma once
#include <optional>
#include <torch/library.h>
#include <tuple>
#include "core/scalar_type.hpp"
... | ## Purpose
- add min latency bf16 qkv_a_gemm
- adapted from sgl: * https://github.com/sgl-project/sglang/blob/main/sgl-kernel/csrc/gemm/dsv3_fused_a_gemm.cu, which adapted from trtllm
- disappointing E2E win, but sets up using PDL to overlap with AR in future PR
## Test Plan
- lm eval
```bash
local-completions ({'mod... | [] | null | null |
vllm | 6874638bc443ae99ee900072e0bb039fa5f7f0e7 | 2026-02-18T10:42:36-05:00 | 34,758 | https://github.com/vllm-project/vllm/pull/34758 | [Model Bash] DeepSeek R1 BF16 Min Latency QKV A GEMM (0.5% E2E Speedup) (#34758) | [Model Bash] DeepSeek R1 BF16 Min Latency QKV A GEMM (0.5% E2E Speedup) (#34758)
Signed-off-by: Robert Shaw <robshaw@redhat.com>
Co-authored-by: Robert Shaw <robshaw@redhat.com> | csrc/torch_bindings.cpp | cpp | Apache-2.0 | #include "cache.h"
#include "cuda_utils.h"
#include "ops.h"
#include "core/registration.h"
#include <torch/library.h>
#include <torch/version.h>
// Note on op signatures:
// The X_meta signatures are for the meta functions corresponding to op X.
// They must be kept in sync with the signature for X. Generally, only
/... | #include "cache.h"
#include "cuda_utils.h"
#include "ops.h"
#include "core/registration.h"
#include <torch/library.h>
#include <torch/version.h>
// Note on op signatures:
// The X_meta signatures are for the meta functions corresponding to op X.
// They must be kept in sync with the signature for X. Generally, only
/... | --- csrc/torch_bindings.cpp
+++ csrc/torch_bindings.cpp
@@ -239,6 +239,11 @@
// Quantization ops
#ifndef USE_ROCM
+ // DeepSeek V3 fused A GEMM (SM 9.0+, bf16 only, 1-16 tokens).
+ ops.def(
+ "dsv3_fused_a_gemm(Tensor! output, Tensor mat_a, Tensor mat_b) -> ()");
+ ops.impl("dsv3_fused_a_gemm", torch::kCU... | 5 | 0 | 3 | [
"deepseek"
] | [] | [] | Optimize this cpp kernel file from vllm (csrc/torch_bindings.cpp).
Goal: [Model Bash] DeepSeek R1 BF16 Min Latency QKV A GEMM (0.5% E2E Speedup)
Target hardware: unspecified
Target models: deepseek
Current file:
```cpp
#include "cache.h"
#include "cuda_utils.h"
#include "ops.h"
#include "core/registration.h"
#includ... | ## Purpose
- add min latency bf16 qkv_a_gemm
- adapted from sgl: * https://github.com/sgl-project/sglang/blob/main/sgl-kernel/csrc/gemm/dsv3_fused_a_gemm.cu, which adapted from trtllm
- disappointing E2E win, but sets up using PDL to overlap with AR in future PR
## Test Plan
- lm eval
```bash
local-completions ({'mod... | [] | null | null |
vllm | b68fd899d1317259d61d8bbaf79dcb2749d17634 | 2026-02-17T09:58:49+08:00 | 34,507 | https://github.com/vllm-project/vllm/pull/34507 | [Bugfix] Fix fused MoE int32 overflow in stride*offset without perf regression (#34507) | [Bugfix] Fix fused MoE int32 overflow in stride*offset without perf regression (#34507)
Signed-off-by: haosdent <haosdent@gmail.com>
Co-authored-by: Michael Goin <mgoin64@gmail.com> | vllm/model_executor/layers/fused_moe/fused_moe.py | triton | Apache-2.0 | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
"""Fused MoE Triton kernels."""
import functools
import json
import os
from collections.abc import Callable
from typing import Any
import torch
import vllm.envs as envs
import vllm.model_executor.layers.fused_m... | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
"""Fused MoE Triton kernels."""
import functools
import json
import os
from collections.abc import Callable
from typing import Any
import torch
import vllm.envs as envs
import vllm.model_executor.layers.fused_m... | --- vllm/model_executor/layers/fused_moe/fused_moe.py
+++ vllm/model_executor/layers/fused_moe/fused_moe.py
@@ -175,7 +175,8 @@
if pid_m * BLOCK_SIZE_M >= num_tokens_post_padded:
return
offs_token_id = pid_m * BLOCK_SIZE_M + tl.arange(0, BLOCK_SIZE_M).to(tl.int64)
- offs_token = tl.load(sorted_tok... | 5 | 1 | 1 | [] | [] | [] | Optimize this triton kernel file from vllm (vllm/model_executor/layers/fused_moe/fused_moe.py).
Goal: [Bugfix] Fix fused MoE int32 overflow in stride*offset without perf regression
Target hardware: unspecified
Target models: unspecified
Current file:
```python
# SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrigh... | ## Purpose
Fixes #34413
PR #34279 annotated all stride parameters as tl.int64 to fix an int32 overflow crash, but this caused ~60x perf regression on small GPUs (e.g. NVIDIA GB10) due to register pressure. PR #34530 reverted that fix.
This patch prevents the overflow with minimal register impact by casting offs_toke... | [] | null | null |
vllm | afdce12c89555ce7b7bd4f3215b5d844de0a32ed | 2026-02-10T16:29:52+01:00 | 33,680 | https://github.com/vllm-project/vllm/pull/33680 | [Perf][Kernel] Add faster topKperRow decode kernel for DeepSeek-V3.2 sparse attention (#33680) | [Perf][Kernel] Add faster topKperRow decode kernel for DeepSeek-V3.2 sparse attention (#33680)
Signed-off-by: LopezCastroRoberto <rocastro@redhat.com>
Signed-off-by: Roberto L. Castro <38211239+LopezCastroRoberto@users.noreply.github.com>
Co-authored-by: Claude Sonnet 4.5 <noreply@anthropic.com> | csrc/ops.h | cpp | Apache-2.0 | #pragma once
#include <optional>
#include <torch/library.h>
#include <tuple>
#include "core/scalar_type.hpp"
#include <vector>
torch::Tensor weak_ref_tensor(torch::Tensor& tensor) {
// Ensure tensor is on CUDA
if (!tensor.is_cuda()) {
throw std::runtime_error("Tensor must be on CUDA device");
}
// Get ... | #pragma once
#include <optional>
#include <torch/library.h>
#include <tuple>
#include "core/scalar_type.hpp"
#include <vector>
torch::Tensor weak_ref_tensor(torch::Tensor& tensor) {
// Ensure tensor is on CUDA
if (!tensor.is_cuda()) {
throw std::runtime_error("Tensor must be on CUDA device");
}
// Get ... | --- csrc/ops.h
+++ csrc/ops.h
@@ -114,6 +114,10 @@
int64_t numRows, int64_t stride0, int64_t stride1,
int64_t topK);
+void large_context_topk(const torch::Tensor& score, torch::Tensor& indices,
+ const torch::Tensor& lengths,
+ ... | 4 | 0 | 5 | [
"deepseek"
] | [] | [] | Optimize this cpp kernel file from vllm (csrc/ops.h).
Goal: [Perf][Kernel] Add faster topKperRow decode kernel for DeepSeek-V3.2 sparse attention
Target hardware: unspecified
Target models: deepseek
Current file:
```cpp
#pragma once
#include <optional>
#include <torch/library.h>
#include <tuple>
#include "core/scal... | ## Summary
This PR adds an optimized top-k per-row decode kernel for DeepSeek-V3.2 sparse attention (K = 2048). The new kernel replaces vLLM’s native `top_k_per_row_decode` in the decode path for long-context inference. It uses a 5-pass radix selection algorithm optimized for large-K workloads and long sequence lengths... | [{"scope": "e2e", "hardware": "NVIDIA B200", "model": "nvidia/DeepSeek-V3.2-NVFP4", "shape": "input-len=131072,output-len=2048", "batch_size": 1, "metric": "Output token throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 63.95, "optimized": 68.29, "stated_speedup": null, "speedup": 1.0679}, {"scope": "... | null | 1.0685 |
vllm | afdce12c89555ce7b7bd4f3215b5d844de0a32ed | 2026-02-10T16:29:52+01:00 | 33,680 | https://github.com/vllm-project/vllm/pull/33680 | [Perf][Kernel] Add faster topKperRow decode kernel for DeepSeek-V3.2 sparse attention (#33680) | [Perf][Kernel] Add faster topKperRow decode kernel for DeepSeek-V3.2 sparse attention (#33680)
Signed-off-by: LopezCastroRoberto <rocastro@redhat.com>
Signed-off-by: Roberto L. Castro <38211239+LopezCastroRoberto@users.noreply.github.com>
Co-authored-by: Claude Sonnet 4.5 <noreply@anthropic.com> | csrc/torch_bindings.cpp | cpp | Apache-2.0 | #include "cache.h"
#include "cuda_utils.h"
#include "ops.h"
#include "core/registration.h"
#include <torch/library.h>
#include <torch/version.h>
// Note on op signatures:
// The X_meta signatures are for the meta functions corresponding to op X.
// They must be kept in sync with the signature for X. Generally, only
/... | #include "cache.h"
#include "cuda_utils.h"
#include "ops.h"
#include "core/registration.h"
#include <torch/library.h>
#include <torch/version.h>
// Note on op signatures:
// The X_meta signatures are for the meta functions corresponding to op X.
// They must be kept in sync with the signature for X. Generally, only
/... | --- csrc/torch_bindings.cpp
+++ csrc/torch_bindings.cpp
@@ -189,6 +189,12 @@
"Tensor seq_lens, Tensor! indices, "
"int numRows, int stride0, int stride1, int topK) -> ()");
ops.impl("top_k_per_row_decode", torch::kCUDA, &top_k_per_row_decode);
+
+ ops.def(
+ "large_context_topk(Tensor score, Tens... | 6 | 0 | 5 | [
"deepseek"
] | [] | [] | Optimize this cpp kernel file from vllm (csrc/torch_bindings.cpp).
Goal: [Perf][Kernel] Add faster topKperRow decode kernel for DeepSeek-V3.2 sparse attention
Target hardware: unspecified
Target models: deepseek
Current file:
```cpp
#include "cache.h"
#include "cuda_utils.h"
#include "ops.h"
#include "core/registrati... | ## Summary
This PR adds an optimized top-k per-row decode kernel for DeepSeek-V3.2 sparse attention (K = 2048). The new kernel replaces vLLM’s native `top_k_per_row_decode` in the decode path for long-context inference. It uses a 5-pass radix selection algorithm optimized for large-K workloads and long sequence lengths... | [{"scope": "e2e", "hardware": "NVIDIA B200", "model": "nvidia/DeepSeek-V3.2-NVFP4", "shape": "input-len=131072,output-len=2048", "batch_size": 1, "metric": "Output token throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 63.95, "optimized": 68.29, "stated_speedup": null, "speedup": 1.0679}, {"scope": "... | null | 1.0685 |
vllm | 179ae7da8f48f76b0db4dc3e331153b24a36a96a | 2026-02-09T00:13:24+08:00 | 33,771 | https://github.com/vllm-project/vllm/pull/33771 | [Revert] Fix performance regression for GLM-4.7-GPTQ decode and MTP acceptance rate (#33771) | [Revert] Fix performance regression for GLM-4.7-GPTQ decode and MTP acceptance rate (#33771)
Signed-off-by: aabbccddwasd <aabbccddwasd@qq.com> | vllm/v1/attention/backends/flashinfer.py | triton | Apache-2.0 | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
"""Attention layer with FlashInfer."""
from dataclasses import dataclass
from typing import ClassVar
import numpy as np
import torch
from flashinfer import (
BatchDecodeWithPagedKVCacheWrapper,
BatchPref... | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
"""Attention layer with FlashInfer."""
from dataclasses import dataclass
from typing import ClassVar
import numpy as np
import torch
from flashinfer import (
BatchDecodeWithPagedKVCacheWrapper,
BatchPref... | --- vllm/v1/attention/backends/flashinfer.py
+++ vllm/v1/attention/backends/flashinfer.py
@@ -919,9 +919,7 @@
# Guard access to seq_lens_cpu, which may not always be needed
# and can be expensive to retrieve in async mode.
needs_seq_lens_cpu = self.use_dcp or use_cascade or not is_only_trtllm... | 1 | 3 | 1 | [
"glm"
] | [] | [] | Optimize this triton kernel file from vllm (vllm/v1/attention/backends/flashinfer.py).
Goal: [Revert] Fix performance regression for GLM-4.7-GPTQ decode and MTP acceptance rate
Target hardware: unspecified
Target models: glm
Current file:
```python
# SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyr... | ## Purpose
Fix performance regressions introduced by two recent commits:
- `e0327c9db` (#31773) - Decode performance regression
~~- `654a71fc3` (#32805) - MTP (Multi-Token Prediction) acceptance rate regression~~
**Affected Model:** GLM-4.7-GPTQ-INT4-INT8MIX
- Model body: int4/int8 mixed quantization
- MT... | [{"scope": "e2e", "hardware": "4\u00d7RTX PRO 6000 BLACKWELL", "model": "GLM-4.7-GPTQ-INT4-INT8MIX", "shape": "MTP module in BF16", "batch_size": null, "metric": "throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 77, "optimized": 95, "stated_speedup": null, "speedup": 1.2338}] | null | 1.2338 |
vllm | ed17f54c8bccc2f1a19f83f65b36d837698b8792 | 2026-02-07T05:33:11-08:00 | 33,493 | https://github.com/vllm-project/vllm/pull/33493 | Perf tuning and expansion of cases covered for wvSplitKrc (#33493) | Perf tuning and expansion of cases covered for wvSplitKrc (#33493)
Signed-off-by: Hashem Hashemi <hashem.hashemi@amd.com> | csrc/rocm/skinny_gemms.cu | cuda | Apache-2.0 | #include <torch/all.h>
#include <ATen/cuda/CUDAContext.h>
#include <c10/cuda/CUDAGuard.h>
#include <cuda_runtime.h>
#include <cuda_fp16.h>
#include <cuda_bf16.h>
#include <stdexcept>
#include <algorithm>
#include "../cuda_compat.h"
#include "dispatch_utils.h"
#include "quantization/w8a8/fp8/common.cuh"
// TODO(rasm... | #include <torch/all.h>
#include <ATen/cuda/CUDAContext.h>
#include <c10/cuda/CUDAGuard.h>
#include <cuda_runtime.h>
#include <cuda_fp16.h>
#include <cuda_bf16.h>
#include <stdexcept>
#include <algorithm>
#include "../cuda_compat.h"
#include "dispatch_utils.h"
#include "quantization/w8a8/fp8/common.cuh"
// TODO(rasm... | --- csrc/rocm/skinny_gemms.cu
+++ csrc/rocm/skinny_gemms.cu
@@ -1365,13 +1365,12 @@
return out_c;
}
-#if defined(__gfx950__) // TODO: Add NAVI support
- // This version targets big A[] cases, where it is much larger than LDS
- // capacity
+// This version targets cases skinny where CUs are not filled
+// Wave-... | 144 | 185 | 2 | [] | [
"ROCM"
] | [] | Optimize this cuda kernel file from vllm (csrc/rocm/skinny_gemms.cu).
Goal: Perf tuning and expansion of cases covered for wvSplitKrc
Target hardware: ROCM
Target models: unspecified
Current file:
```cuda
#include <torch/all.h>
#include <ATen/cuda/CUDAContext.h>
#include <c10/cuda/CUDAGuard.h>
#include <cuda_runtime... | <!-- markdownlint-disable -->
mi355 measurements before and after changes:
m, n, K , bfor(us), aftr (us)
128, 16, 2880, 4.55, 4.56
640, 16, 2880, 4.80, 4.83
128, 32, 2880, 3.91, **3.21**
640, 32, 2880, 4.13, 4.05
128, 64, 2880, 4.42, **3.23**
640, 64, 2880, 4.88, **4.43**
128, 128, 2880, 4.51, **3.98**
640, 128, ... | [] | null | null |
vllm | 1363e3d6d5659b58376fa5284afc2c8be548cc9d | 2026-02-06T07:01:48Z | 32,263 | https://github.com/vllm-project/vllm/pull/32263 | [cpu][performance] CPU Paged Attention NEON BFMMLA BF16 Implementation (#32263) | [cpu][performance] CPU Paged Attention NEON BFMMLA BF16 Implementation (#32263)
Signed-off-by: Gassan <gassan.salama@arm.com> | csrc/cpu/cpu_attn_impl.hpp | cpp | Apache-2.0 | #ifndef CPU_ATTN_HPP
#define CPU_ATTN_HPP
#include <type_traits>
#include <cstddef>
#if defined(__APPLE__)
#include <sys/sysctl.h>
#endif
#include "cpu/cpu_arch_macros.h"
#include "cpu/utils.hpp"
namespace cpu_attention {
enum class ISA { AMX, VEC, VEC16, NEON };
template <ISA isa, typename scalar_t, int64_t hea... | #ifndef CPU_ATTN_HPP
#define CPU_ATTN_HPP
#include <type_traits>
#include <cstddef>
#if defined(__APPLE__)
#include <sys/sysctl.h>
#endif
#include "cpu/cpu_arch_macros.h"
#include "cpu/utils.hpp"
namespace cpu_attention {
enum class ISA { AMX, VEC, VEC16, NEON };
template <ISA isa, typename scalar_t, int64_t hea... | --- csrc/cpu/cpu_attn_impl.hpp
+++ csrc/cpu/cpu_attn_impl.hpp
@@ -1107,7 +1107,8 @@
if (sliding_window_left != -1) {
pos = std::max(pos, curr_token_pos - sliding_window_left);
}
- return pos;
+ // Clamp to tile end to avoid OOB when window starts past the tile
+ ... | 2 | 1 | 3 | [] | [
"CPU"
] | [] | Optimize this cpp kernel file from vllm (csrc/cpu/cpu_attn_impl.hpp).
Goal: [cpu][performance] CPU Paged Attention NEON BFMMLA BF16 Implementation
Target hardware: CPU
Target models: unspecified
Current file:
```cpp
#ifndef CPU_ATTN_HPP
#define CPU_ATTN_HPP
#include <type_traits>
#include <cstddef>
#if defined(__AP... | <!-- markdownlint-disable -->
## Purpose
CPU Paged Attention NEON BFMMLA BF16 Implementation
Co-authored-by: GitHub Copilot
## Test Results
Using: https://github.com/vllm-project/vllm/pull/31720 Benchmark Suite,
Against Current NEON Implementation:
**Prefill: 2.32x
Decode: 2.07x**
cc. @aditew01 @fadara01
| [{"scope": "kernel", "hardware": null, "model": null, "shape": null, "batch_size": null, "metric": "performance", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 2.32, "speedup": 2.32}, {"scope": "kernel", "hardware": null, "model": null, "shape": null, "batch_size": null,... | 2.195 | null |
vllm | 1363e3d6d5659b58376fa5284afc2c8be548cc9d | 2026-02-06T07:01:48Z | 32,263 | https://github.com/vllm-project/vllm/pull/32263 | [cpu][performance] CPU Paged Attention NEON BFMMLA BF16 Implementation (#32263) | [cpu][performance] CPU Paged Attention NEON BFMMLA BF16 Implementation (#32263)
Signed-off-by: Gassan <gassan.salama@arm.com> | csrc/cpu/cpu_attn_neon.hpp | cpp | Apache-2.0 | #ifndef CPU_ATTN_NEON_HPP
#define CPU_ATTN_NEON_HPP
#include "cpu_attn_impl.hpp"
#include <arm_neon.h>
#include <type_traits>
namespace cpu_attention {
namespace {
#define BLOCK_SIZE_ALIGNMENT 32
#define HEAD_SIZE_ALIGNMENT 32
#define MAX_Q_HEAD_NUM_PER_ITER 16
// These do not use vectorized class for loading / con... | #ifndef CPU_ATTN_NEON_HPP
#define CPU_ATTN_NEON_HPP
#include "cpu_attn_impl.hpp"
#include <arm_neon.h>
#include <type_traits>
#ifdef ARM_BF16_SUPPORT
#include "cpu_attn_neon_bfmmla.hpp"
#endif
namespace cpu_attention {
namespace {
#define BLOCK_SIZE_ALIGNMENT 32
#define HEAD_SIZE_ALIGNMENT 32
#define MAX_Q_HEAD_NU... | --- csrc/cpu/cpu_attn_neon.hpp
+++ csrc/cpu/cpu_attn_neon.hpp
@@ -4,6 +4,9 @@
#include "cpu_attn_impl.hpp"
#include <arm_neon.h>
#include <type_traits>
+#ifdef ARM_BF16_SUPPORT
+ #include "cpu_attn_neon_bfmmla.hpp"
+#endif
namespace cpu_attention {
namespace {
@@ -57,7 +60,7 @@
#endif
}
-// Mx8, with 1 <= M... | 17 | 2 | 3 | [] | [
"CPU"
] | [] | Optimize this cpp kernel file from vllm (csrc/cpu/cpu_attn_neon.hpp).
Goal: [cpu][performance] CPU Paged Attention NEON BFMMLA BF16 Implementation
Target hardware: CPU
Target models: unspecified
Current file:
```cpp
#ifndef CPU_ATTN_NEON_HPP
#define CPU_ATTN_NEON_HPP
#include "cpu_attn_impl.hpp"
#include <arm_neon.h... | <!-- markdownlint-disable -->
## Purpose
CPU Paged Attention NEON BFMMLA BF16 Implementation
Co-authored-by: GitHub Copilot
## Test Results
Using: https://github.com/vllm-project/vllm/pull/31720 Benchmark Suite,
Against Current NEON Implementation:
**Prefill: 2.32x
Decode: 2.07x**
cc. @aditew01 @fadara01
| [{"scope": "kernel", "hardware": null, "model": null, "shape": null, "batch_size": null, "metric": "performance", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 2.32, "speedup": 2.32}, {"scope": "kernel", "hardware": null, "model": null, "shape": null, "batch_size": null,... | 2.195 | null |
vllm | d5c4800112c12bbcd4955858ef1b415c16ae16e7 | 2026-02-05T14:16:02-08:00 | 33,527 | https://github.com/vllm-project/vllm/pull/33527 | Adds padding and perf improvements to wvSplitK_fp8 (#33527) | Adds padding and perf improvements to wvSplitK_fp8 (#33527)
Signed-off-by: Hashem Hashemi <hashem.hashemi@amd.com> | csrc/rocm/skinny_gemms.cu | cuda | Apache-2.0 | #include <torch/all.h>
#include <ATen/cuda/CUDAContext.h>
#include <c10/cuda/CUDAGuard.h>
#include <cuda_runtime.h>
#include <cuda_fp16.h>
#include <cuda_bf16.h>
#include <stdexcept>
#include <algorithm>
#include "../cuda_compat.h"
#include "dispatch_utils.h"
#include "quantization/w8a8/fp8/common.cuh"
// TODO(rasm... | #include <torch/all.h>
#include <ATen/cuda/CUDAContext.h>
#include <c10/cuda/CUDAGuard.h>
#include <cuda_runtime.h>
#include <cuda_fp16.h>
#include <cuda_bf16.h>
#include <stdexcept>
#include <algorithm>
#include "../cuda_compat.h"
#include "dispatch_utils.h"
#include "quantization/w8a8/fp8/common.cuh"
// TODO(rasm... | --- csrc/rocm/skinny_gemms.cu
+++ csrc/rocm/skinny_gemms.cu
@@ -1899,8 +1899,9 @@
template <typename scalar_t, typename fp8_t, int THRDS, int YTILE, int WvPrGrp,
int A_CHUNK, int UNRL, int N>
__global__ void __launch_bounds__(WvPrGrp* THRDS)
- wvSplitKQ_hf_sml_(const int K, const int Kp, const int M, co... | 129 | 177 | 2 | [] | [
"ROCM"
] | [] | Optimize this cuda kernel file from vllm (csrc/rocm/skinny_gemms.cu).
Goal: Adds padding and perf improvements to wvSplitK_fp8
Target hardware: ROCM
Target models: unspecified
Current file:
```cuda
#include <torch/all.h>
#include <ATen/cuda/CUDAContext.h>
#include <c10/cuda/CUDAGuard.h>
#include <cuda_runtime.h>
#in... | Adds activation padding support to wvSplitKQ. Additionally improves bias and dpp reduce perf. Expands test scenarios.
## Purpose
## Test Plan
## Test Result
---
<details>
<summary> Essential Elements of an Effective PR Description Checklist </summary>
- [ ] The purpose of the PR, such as "Fix some issue (link exis... | [] | null | null |
vllm | 824058076c56164a3772a5f5829bd9662507e5a3 | 2026-02-04T15:20:52+04:00 | 33,291 | https://github.com/vllm-project/vllm/pull/33291 | [PERF] Change GDN Attention State Layout from [N, HV, K, V] to [N, HV, V, K] (#33291) | [PERF] Change GDN Attention State Layout from [N, HV, K, V] to [N, HV, V, K] (#33291)
Signed-off-by: Vadim Gimpelson <vadim.gimpelson@gmail.com> | vllm/model_executor/layers/fla/ops/chunk_delta_h.py | triton | Apache-2.0 | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# SPDX-FileCopyrightText: Songlin Yang, Yu Zhang
#
# This file contains code copied from the flash-linear-attention project.
# The original source code was licensed under the MIT license and included
# the followi... | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# SPDX-FileCopyrightText: Songlin Yang, Yu Zhang
#
# This file contains code copied from the flash-linear-attention project.
# The original source code was licensed under the MIT license and included
# the followi... | --- vllm/model_executor/layers/fla/ops/chunk_delta_h.py
+++ vllm/model_executor/layers/fla/ops/chunk_delta_h.py
@@ -81,70 +81,70 @@
NT = tl.cdiv(T, BT)
boh = i_n * NT
- # [BK, BV]
- b_h1 = tl.zeros([64, BV], dtype=tl.float32)
+ # [BV, BK]
+ b_h1 = tl.zeros([BV, 64], dtype=tl.float32)
... | 35 | 35 | 6 | [] | [] | [] | Optimize this triton kernel file from vllm (vllm/model_executor/layers/fla/ops/chunk_delta_h.py).
Goal: [PERF] Change GDN Attention State Layout from [N, HV, K, V] to [N, HV, V, K]
Target hardware: unspecified
Target models: unspecified
Current file:
```python
# SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrigh... | ## Summary
This PR changes the recurrent state memory layout in GDN (Gated Delta Net) attention from `[N, HV, K, V]` to `[N, HV, V, K]` for improved memory access patterns and throughput.
Behind speedup, also allows to use FI's GDN kernels
## Performance Results
**Model**: `nvidia/Qwen3-Next-80B-A3B-Instruct-NVFP4`... | [{"scope": "e2e", "hardware": null, "model": "nvidia/Qwen3-Next-80B-A3B-Instruct-NVFP4", "shape": null, "batch_size": 1, "metric": "throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 199.58, "optimized": 201.37, "stated_speedup": null, "speedup": 1.009}, {"scope": "e2e", "hardware": null, "model": "nvi... | null | 1.009 |
vllm | 824058076c56164a3772a5f5829bd9662507e5a3 | 2026-02-04T15:20:52+04:00 | 33,291 | https://github.com/vllm-project/vllm/pull/33291 | [PERF] Change GDN Attention State Layout from [N, HV, K, V] to [N, HV, V, K] (#33291) | [PERF] Change GDN Attention State Layout from [N, HV, K, V] to [N, HV, V, K] (#33291)
Signed-off-by: Vadim Gimpelson <vadim.gimpelson@gmail.com> | vllm/model_executor/layers/fla/ops/chunk_o.py | triton | Apache-2.0 | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# SPDX-FileCopyrightText: Songlin Yang, Yu Zhang
#
# This file contains code copied from the flash-linear-attention project.
# The original source code was licensed under the MIT license and included
# the followi... | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# SPDX-FileCopyrightText: Songlin Yang, Yu Zhang
#
# This file contains code copied from the flash-linear-attention project.
# The original source code was licensed under the MIT license and included
# the followi... | --- vllm/model_executor/layers/fla/ops/chunk_o.py
+++ vllm/model_executor/layers/fla/ops/chunk_o.py
@@ -85,7 +85,7 @@
k += (bos * Hg + i_h // (H // Hg)) * K
v += (bos * H + i_h) * V
o += (bos * H + i_h) * V
- h += (i_tg * H + i_h).to(tl.int64) * K * V
+ h += (i_tg * H + i_h).to(tl.int64) * V * K
... | 4 | 4 | 6 | [] | [] | [] | Optimize this triton kernel file from vllm (vllm/model_executor/layers/fla/ops/chunk_o.py).
Goal: [PERF] Change GDN Attention State Layout from [N, HV, K, V] to [N, HV, V, K]
Target hardware: unspecified
Target models: unspecified
Current file:
```python
# SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText:... | ## Summary
This PR changes the recurrent state memory layout in GDN (Gated Delta Net) attention from `[N, HV, K, V]` to `[N, HV, V, K]` for improved memory access patterns and throughput.
Behind speedup, also allows to use FI's GDN kernels
## Performance Results
**Model**: `nvidia/Qwen3-Next-80B-A3B-Instruct-NVFP4`... | [{"scope": "e2e", "hardware": null, "model": "nvidia/Qwen3-Next-80B-A3B-Instruct-NVFP4", "shape": null, "batch_size": 1, "metric": "throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 199.58, "optimized": 201.37, "stated_speedup": null, "speedup": 1.009}, {"scope": "e2e", "hardware": null, "model": "nvi... | null | 1.009 |
vllm | 824058076c56164a3772a5f5829bd9662507e5a3 | 2026-02-04T15:20:52+04:00 | 33,291 | https://github.com/vllm-project/vllm/pull/33291 | [PERF] Change GDN Attention State Layout from [N, HV, K, V] to [N, HV, V, K] (#33291) | [PERF] Change GDN Attention State Layout from [N, HV, K, V] to [N, HV, V, K] (#33291)
Signed-off-by: Vadim Gimpelson <vadim.gimpelson@gmail.com> | vllm/model_executor/layers/fla/ops/fused_recurrent.py | triton | Apache-2.0 | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# SPDX-FileCopyrightText: Songlin Yang, Yu Zhang
#
# This file contains code copied from the flash-linear-attention project.
# The original source code was licensed under the MIT license and included
# the followi... | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# SPDX-FileCopyrightText: Songlin Yang, Yu Zhang
#
# This file contains code copied from the flash-linear-attention project.
# The original source code was licensed under the MIT license and included
# the followi... | --- vllm/model_executor/layers/fla/ops/fused_recurrent.py
+++ vllm/model_executor/layers/fla/ops/fused_recurrent.py
@@ -97,9 +97,9 @@
mask_k = o_k < K
mask_v = o_v < V
- mask_h = mask_k[:, None] & mask_v[None, :]
-
- b_h = tl.zeros([BK, BV], dtype=tl.float32)
+ mask_h = mask_v[:, None] & mask_k[Non... | 17 | 17 | 6 | [] | [] | [] | Optimize this triton kernel file from vllm (vllm/model_executor/layers/fla/ops/fused_recurrent.py).
Goal: [PERF] Change GDN Attention State Layout from [N, HV, K, V] to [N, HV, V, K]
Target hardware: unspecified
Target models: unspecified
Current file:
```python
# SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyri... | ## Summary
This PR changes the recurrent state memory layout in GDN (Gated Delta Net) attention from `[N, HV, K, V]` to `[N, HV, V, K]` for improved memory access patterns and throughput.
Behind speedup, also allows to use FI's GDN kernels
## Performance Results
**Model**: `nvidia/Qwen3-Next-80B-A3B-Instruct-NVFP4`... | [{"scope": "e2e", "hardware": null, "model": "nvidia/Qwen3-Next-80B-A3B-Instruct-NVFP4", "shape": null, "batch_size": 1, "metric": "throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 199.58, "optimized": 201.37, "stated_speedup": null, "speedup": 1.009}, {"scope": "e2e", "hardware": null, "model": "nvi... | null | 1.009 |
vllm | 824058076c56164a3772a5f5829bd9662507e5a3 | 2026-02-04T15:20:52+04:00 | 33,291 | https://github.com/vllm-project/vllm/pull/33291 | [PERF] Change GDN Attention State Layout from [N, HV, K, V] to [N, HV, V, K] (#33291) | [PERF] Change GDN Attention State Layout from [N, HV, K, V] to [N, HV, V, K] (#33291)
Signed-off-by: Vadim Gimpelson <vadim.gimpelson@gmail.com> | vllm/model_executor/layers/fla/ops/kda.py | triton | Apache-2.0 | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# SPDX-FileCopyrightText: Songlin Yang, Yu Zhang
#
# This file contains code copied from the flash-linear-attention project.
# The original source code was licensed under the MIT license and included
# the followi... | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# SPDX-FileCopyrightText: Songlin Yang, Yu Zhang
#
# This file contains code copied from the flash-linear-attention project.
# The original source code was licensed under the MIT license and included
# the followi... | --- vllm/model_executor/layers/fla/ops/kda.py
+++ vllm/model_executor/layers/fla/ops/kda.py
@@ -55,7 +55,7 @@
if inplace_final_state:
final_state = initial_state
else:
- final_state = q.new_empty(T, HV, K, V, dtype=initial_state.dtype)
+ final_state = q.new_empty(T, HV, V, K, dtype=init... | 1 | 1 | 6 | [] | [] | [] | Optimize this triton kernel file from vllm (vllm/model_executor/layers/fla/ops/kda.py).
Goal: [PERF] Change GDN Attention State Layout from [N, HV, K, V] to [N, HV, V, K]
Target hardware: unspecified
Target models: unspecified
Current file:
```python
# SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Cop... | ## Summary
This PR changes the recurrent state memory layout in GDN (Gated Delta Net) attention from `[N, HV, K, V]` to `[N, HV, V, K]` for improved memory access patterns and throughput.
Behind speedup, also allows to use FI's GDN kernels
## Performance Results
**Model**: `nvidia/Qwen3-Next-80B-A3B-Instruct-NVFP4`... | [{"scope": "e2e", "hardware": null, "model": "nvidia/Qwen3-Next-80B-A3B-Instruct-NVFP4", "shape": null, "batch_size": 1, "metric": "throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 199.58, "optimized": 201.37, "stated_speedup": null, "speedup": 1.009}, {"scope": "e2e", "hardware": null, "model": "nvi... | null | 1.009 |
vllm | e69c990c216c623b1de22f055926602a336f9352 | 2026-02-03T04:17:56Z | 30,329 | https://github.com/vllm-project/vllm/pull/30329 | [Feature][CPU Backend]: Optimize ARM vectorization backend (#30329) | [Feature][CPU Backend]: Optimize ARM vectorization backend (#30329)
Signed-off-by: Radu Salavat <radu.salavat@arm.com> | csrc/cpu/cpu_attn_impl.hpp | cpp | Apache-2.0 | #ifndef CPU_ATTN_HPP
#define CPU_ATTN_HPP
#include <type_traits>
#include <cstddef>
#if defined(__APPLE__)
#include <sys/sysctl.h>
#endif
#include "cpu/cpu_arch_macros.h"
#include "cpu/utils.hpp"
namespace cpu_attention {
enum class ISA { AMX, VEC, VEC16, NEON };
template <ISA isa, typename scalar_t, int64_t hea... | #ifndef CPU_ATTN_HPP
#define CPU_ATTN_HPP
#include <type_traits>
#include <cstddef>
#if defined(__APPLE__)
#include <sys/sysctl.h>
#endif
#include "cpu/cpu_arch_macros.h"
#include "cpu/utils.hpp"
namespace cpu_attention {
enum class ISA { AMX, VEC, VEC16, NEON };
template <ISA isa, typename scalar_t, int64_t hea... | --- csrc/cpu/cpu_attn_impl.hpp
+++ csrc/cpu/cpu_attn_impl.hpp
@@ -816,14 +816,10 @@
using vec_t = vec_op::FP32Vec16;
};
-// ARM only supports BF16 with ARMv8.6-A extension
-#if (defined(__aarch64__) && !defined(ARM_BF16_SUPPORT))
-#else
template <>
struct VecTypeTrait<c10::BFloat16> {
using vec_t = vec_op::B... | 0 | 11 | 5 | [] | [
"CPU"
] | [] | Optimize this cpp kernel file from vllm (csrc/cpu/cpu_attn_impl.hpp).
Goal: [Feature][CPU Backend]: Optimize ARM vectorization backend
Target hardware: CPU
Target models: unspecified
Current file:
```cpp
#ifndef CPU_ATTN_HPP
#define CPU_ATTN_HPP
#include <type_traits>
#include <cstddef>
#if defined(__APPLE__)
#in... | ## Purpose
Implement vectorised backed based on `at::vec::Vectorized` for ARM, introduce highlevel FP32/FP16/BF16 vector wrappers and add new shared based class `VectorizedRegWrapper` capable of scaling with dtypes.
- Implement ARM vectorisation based on `at::vec::Vectorized<T>` for `float`, `c10::Half` and `c10::BFlo... | [] | null | null |
vllm | e69c990c216c623b1de22f055926602a336f9352 | 2026-02-03T04:17:56Z | 30,329 | https://github.com/vllm-project/vllm/pull/30329 | [Feature][CPU Backend]: Optimize ARM vectorization backend (#30329) | [Feature][CPU Backend]: Optimize ARM vectorization backend (#30329)
Signed-off-by: Radu Salavat <radu.salavat@arm.com> | csrc/cpu/dnnl_kernels.cpp | cpp | Apache-2.0 | #include "cpu_types.hpp"
#include "dnnl_helper.h"
namespace {
template <typename scalar_t>
struct KernelVecType {
using load_vec_type = void;
using cvt_vec_type = void;
};
template <>
struct KernelVecType<float> {
using load_vec_type = vec_op::FP32Vec16;
using cvt_vec_type = vec_op::FP32Vec16;
};
#if !define... | #include "cpu_types.hpp"
#include "dnnl_helper.h"
namespace {
template <typename scalar_t>
struct KernelVecType {
using load_vec_type = void;
using cvt_vec_type = void;
};
template <>
struct KernelVecType<float> {
using load_vec_type = vec_op::FP32Vec16;
using cvt_vec_type = vec_op::FP32Vec16;
};
template <>... | --- csrc/cpu/dnnl_kernels.cpp
+++ csrc/cpu/dnnl_kernels.cpp
@@ -14,13 +14,11 @@
using cvt_vec_type = vec_op::FP32Vec16;
};
-#if !defined(__aarch64__) || defined(ARM_BF16_SUPPORT)
template <>
struct KernelVecType<c10::BFloat16> {
using load_vec_type = vec_op::BF16Vec16;
using cvt_vec_type = vec_op::FP32Vec... | 0 | 2 | 5 | [] | [
"CPU"
] | [] | Optimize this cpp kernel file from vllm (csrc/cpu/dnnl_kernels.cpp).
Goal: [Feature][CPU Backend]: Optimize ARM vectorization backend
Target hardware: CPU
Target models: unspecified
Current file:
```cpp
#include "cpu_types.hpp"
#include "dnnl_helper.h"
namespace {
template <typename scalar_t>
struct KernelVecType {
... | ## Purpose
Implement vectorised backed based on `at::vec::Vectorized` for ARM, introduce highlevel FP32/FP16/BF16 vector wrappers and add new shared based class `VectorizedRegWrapper` capable of scaling with dtypes.
- Implement ARM vectorisation based on `at::vec::Vectorized<T>` for `float`, `c10::Half` and `c10::BFlo... | [] | null | null |
vllm | e69c990c216c623b1de22f055926602a336f9352 | 2026-02-03T04:17:56Z | 30,329 | https://github.com/vllm-project/vllm/pull/30329 | [Feature][CPU Backend]: Optimize ARM vectorization backend (#30329) | [Feature][CPU Backend]: Optimize ARM vectorization backend (#30329)
Signed-off-by: Radu Salavat <radu.salavat@arm.com> | csrc/cpu/mla_decode.cpp | cpp | Apache-2.0 | #include "cpu_types.hpp"
#include <float.h>
namespace {
template <typename scalar_t>
struct KernelVecType {
using qk_load_vec_type = void;
using qk_vec_type = void;
using v_load_vec_type = void;
};
template <>
struct KernelVecType<float> {
using qk_load_vec_type = vec_op::FP32Vec16;
using qk_vec_type = vec_... | #include "cpu_types.hpp"
#include <float.h>
namespace {
template <typename scalar_t>
struct KernelVecType {
using qk_load_vec_type = void;
using qk_vec_type = void;
using v_load_vec_type = void;
};
template <>
struct KernelVecType<float> {
using qk_load_vec_type = vec_op::FP32Vec16;
using qk_vec_type = vec_... | --- csrc/cpu/mla_decode.cpp
+++ csrc/cpu/mla_decode.cpp
@@ -38,9 +38,7 @@
using qk_vec_type = vec_op::BF16Vec32;
using v_load_vec_type = vec_op::BF16Vec16;
};
-#elif defined(__aarch64__) && !defined(ARM_BF16_SUPPORT)
-// pass
-#else
+#elif defined(__aarch64__)
template <>
struct KernelVecType<c10::BFloat16> {
... | 1 | 3 | 5 | [] | [
"CPU"
] | [] | Optimize this cpp kernel file from vllm (csrc/cpu/mla_decode.cpp).
Goal: [Feature][CPU Backend]: Optimize ARM vectorization backend
Target hardware: CPU
Target models: unspecified
Current file:
```cpp
#include "cpu_types.hpp"
#include <float.h>
namespace {
template <typename scalar_t>
struct KernelVecType {
using ... | ## Purpose
Implement vectorised backed based on `at::vec::Vectorized` for ARM, introduce highlevel FP32/FP16/BF16 vector wrappers and add new shared based class `VectorizedRegWrapper` capable of scaling with dtypes.
- Implement ARM vectorisation based on `at::vec::Vectorized<T>` for `float`, `c10::Half` and `c10::BFlo... | [] | null | null |
vllm | e69c990c216c623b1de22f055926602a336f9352 | 2026-02-03T04:17:56Z | 30,329 | https://github.com/vllm-project/vllm/pull/30329 | [Feature][CPU Backend]: Optimize ARM vectorization backend (#30329) | [Feature][CPU Backend]: Optimize ARM vectorization backend (#30329)
Signed-off-by: Radu Salavat <radu.salavat@arm.com> | csrc/cpu/utils.hpp | cpp | Apache-2.0 | #ifndef UTILS_HPP
#define UTILS_HPP
#include <atomic>
#include <unistd.h>
#include <ATen/cpu/Utils.h>
#include "cpu/cpu_types.hpp"
namespace cpu_utils {
enum class ISA { AMX, VEC };
inline ISA get_isa(const std::string& isa) {
if (isa == "amx") {
return ISA::AMX;
} else if (isa == "vec") {
return ISA::V... | #ifndef UTILS_HPP
#define UTILS_HPP
#include <atomic>
#include <unistd.h>
#include <ATen/cpu/Utils.h>
#include "cpu/cpu_types.hpp"
namespace cpu_utils {
enum class ISA { AMX, VEC };
inline ISA get_isa(const std::string& isa) {
if (isa == "amx") {
return ISA::AMX;
} else if (isa == "vec") {
return ISA::V... | --- csrc/cpu/utils.hpp
+++ csrc/cpu/utils.hpp
@@ -30,12 +30,10 @@
using vec_t = vec_op::FP32Vec16;
};
-#if !defined(__aarch64__) || defined(ARM_BF16_SUPPORT)
template <>
struct VecTypeTrait<c10::BFloat16> {
using vec_t = vec_op::BF16Vec16;
};
-#endif
#if !defined(__powerpc__)
template <> | 0 | 2 | 5 | [] | [
"CPU"
] | [] | Optimize this cpp kernel file from vllm (csrc/cpu/utils.hpp).
Goal: [Feature][CPU Backend]: Optimize ARM vectorization backend
Target hardware: CPU
Target models: unspecified
Current file:
```cpp
#ifndef UTILS_HPP
#define UTILS_HPP
#include <atomic>
#include <unistd.h>
#include <ATen/cpu/Utils.h>
#include "cpu/cpu_... | ## Purpose
Implement vectorised backed based on `at::vec::Vectorized` for ARM, introduce highlevel FP32/FP16/BF16 vector wrappers and add new shared based class `VectorizedRegWrapper` capable of scaling with dtypes.
- Implement ARM vectorisation based on `at::vec::Vectorized<T>` for `float`, `c10::Half` and `c10::BFlo... | [] | null | null |
vllm | c4e744dbd41f23ee7fd554a86cc1bf516082552d | 2026-01-28T13:15:24-05:00 | 32,892 | https://github.com/vllm-project/vllm/pull/32892 | [Perf] Optimize `moe_permute` for CUTLASS FP8 (#32892) | [Perf] Optimize `moe_permute` for CUTLASS FP8 (#32892)
Signed-off-by: yewentao256 <zhyanwentao@126.com> | csrc/moe/moe_permute_unpermute_op.cu | cuda | Apache-2.0 | #include <c10/core/ScalarType.h>
#include <torch/all.h>
#include <ATen/cuda/CUDAContext.h>
#include "permute_unpermute_kernels/moe_permute_unpermute_kernel.h"
#include "permute_unpermute_kernels/dispatch.h"
#include "core/registration.h"
// moe_permute kernels require at least CUDA 12.0
#if defined(CUDA_VERSION) && (C... | #include <c10/core/ScalarType.h>
#include <torch/all.h>
#include <ATen/cuda/CUDAContext.h>
#include "permute_unpermute_kernels/moe_permute_unpermute_kernel.h"
#include "permute_unpermute_kernels/dispatch.h"
#include "core/registration.h"
// moe_permute kernels require at least CUDA 12.0
#if defined(CUDA_VERSION) && (C... | --- csrc/moe/moe_permute_unpermute_op.cu
+++ csrc/moe/moe_permute_unpermute_op.cu
@@ -73,25 +73,40 @@
get_ptr<int64_t>(expert_first_token_offset), n_token, n_expert,
n_local_expert, topk, sorter, get_ptr<int>(sort_workspace), stream);
+ // DeepGEMM: use getMIndices kernel to compute
+ // 1) align_expe... | 24 | 9 | 2 | [] | [] | [] | Optimize this cuda kernel file from vllm (csrc/moe/moe_permute_unpermute_op.cu).
Goal: [Perf] Optimize `moe_permute` for CUTLASS FP8
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
#include <c10/core/ScalarType.h>
#include <torch/all.h>
#include <ATen/cuda/CUDAContext.h>
#include "permut... | ## Purpose
Optimize `moe_permute` kernel using `aligned_expert_first_token_offset`
- Reduce calculation
- Reduce shared memory usage
## Test
### Acc
```bash
tests/kernels/moe/test_moe_permute_unpermute.py ........................... [ 6%]
.............................................................................. | [{"scope": "kernel", "hardware": null, "model": "deepseek-ai/DeepSeek-V2-lite", "shape": null, "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 22.46, "optimized": 15.8, "stated_speedup": 1.4215, "speedup": 1.4215}, {"scope": "kernel", "hardware": null, "model": "deepseek-ai/De... | 1.5096 | null |
vllm | c4e744dbd41f23ee7fd554a86cc1bf516082552d | 2026-01-28T13:15:24-05:00 | 32,892 | https://github.com/vllm-project/vllm/pull/32892 | [Perf] Optimize `moe_permute` for CUTLASS FP8 (#32892) | [Perf] Optimize `moe_permute` for CUTLASS FP8 (#32892)
Signed-off-by: yewentao256 <zhyanwentao@126.com> | csrc/moe/permute_unpermute_kernels/moe_permute_unpermute_kernel.h | cpp | Apache-2.0 | #pragma once
// reference from tensorrt_llm moe kernel implementation archive in
// https://github.com/BBuf/tensorrt-llm-moe/tree/master
#include <c10/core/ScalarType.h>
#include <torch/all.h>
#include "dispatch.h"
#include <cub/cub.cuh>
#include <cub/device/device_radix_sort.cuh>
#include <cub/util_type.cuh>
#include... | #pragma once
// reference from tensorrt_llm moe kernel implementation archive in
// https://github.com/BBuf/tensorrt-llm-moe/tree/master
#include <c10/core/ScalarType.h>
#include <torch/all.h>
#include "dispatch.h"
#include <cub/cub.cuh>
#include <cub/device/device_radix_sort.cuh>
#include <cub/util_type.cuh>
#include... | --- csrc/moe/permute_unpermute_kernels/moe_permute_unpermute_kernel.h
+++ csrc/moe/permute_unpermute_kernels/moe_permute_unpermute_kernel.h
@@ -60,7 +60,8 @@
T const* unpermuted_input, T* permuted_output, int* sorted_experts,
int const* expanded_dest_row_to_expanded_source_row,
int* expanded_source_row_t... | 2 | 1 | 2 | [] | [] | [] | Optimize this cpp kernel file from vllm (csrc/moe/permute_unpermute_kernels/moe_permute_unpermute_kernel.h).
Goal: [Perf] Optimize `moe_permute` for CUTLASS FP8
Target hardware: unspecified
Target models: unspecified
Current file:
```cpp
#pragma once
// reference from tensorrt_llm moe kernel implementation archive in... | ## Purpose
Optimize `moe_permute` kernel using `aligned_expert_first_token_offset`
- Reduce calculation
- Reduce shared memory usage
## Test
### Acc
```bash
tests/kernels/moe/test_moe_permute_unpermute.py ........................... [ 6%]
.............................................................................. | [{"scope": "kernel", "hardware": null, "model": "deepseek-ai/DeepSeek-V2-lite", "shape": null, "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 22.46, "optimized": 15.8, "stated_speedup": 1.4215, "speedup": 1.4215}, {"scope": "kernel", "hardware": null, "model": "deepseek-ai/De... | 1.5096 | null |
vllm | 3a6d5cbefd97a3dee07ba1756d8b5a9052801403 | 2026-01-27T17:24:41-05:00 | 33,102 | https://github.com/vllm-project/vllm/pull/33102 | [Perf] Optimize dcp allocate tensor (#33102) | [Perf] Optimize dcp allocate tensor (#33102)
Signed-off-by: yewentao256 <zhyanwentao@126.com> | vllm/v1/attention/ops/common.py | triton | Apache-2.0 | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
import torch
from vllm.distributed.parallel_state import GroupCoordinator
from vllm.triton_utils import tl, triton
@triton.jit
def _correct_attn_cp_out_kernel(
outputs_ptr,
new_output_ptr,
lses_ptr,... | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
import torch
from vllm.distributed.parallel_state import GroupCoordinator
from vllm.triton_utils import tl, triton
@triton.jit
def _correct_attn_cp_out_kernel(
outputs_ptr,
new_output_ptr,
lses_ptr,... | --- vllm/v1/attention/ops/common.py
+++ vllm/v1/attention/ops/common.py
@@ -195,14 +195,10 @@
if ctx is None:
ctx = CPTritonContext()
- lses = torch.empty(
- (cp_group.world_size,) + cp_attn_lse.shape,
- dtype=cp_attn_lse.dtype,
- device=cp_attn_lse.device,
- )
-
cp_attn_... | 3 | 7 | 1 | [] | [] | [] | Optimize this triton kernel file from vllm (vllm/v1/attention/ops/common.py).
Goal: [Perf] Optimize dcp allocate tensor
Target hardware: unspecified
Target models: unspecified
Current file:
```python
# SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
import torc... | ## Purpose
There is no need to allocate an additional tensor for view_as, we can optimize through that.
| [] | null | null |
vllm | f4a0921c9c1194abf0a5e53218cfe5fb110eedac | 2026-01-26T15:56:54+02:00 | 32,873 | https://github.com/vllm-project/vllm/pull/32873 | [Performance] Tune Mamba selective scan kernel for B200 (#32873) | [Performance] Tune Mamba selective scan kernel for B200 (#32873)
Signed-off-by: Daniel Serebrenik <daserebrenik@nvidia.com>
Co-authored-by: Robert Shaw <114415538+robertgshaw2-redhat@users.noreply.github.com> | vllm/model_executor/layers/mamba/ops/mamba_ssm.py | triton | Apache-2.0 | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# Copyright (c) 2024, Tri Dao, Albert Gu.
# Adapted from https://github.com/state-spaces/mamba/blob/v2.2.4/mamba_ssm/ops/triton/selective_state_update.py
import torch
from packaging import version
from vllm imp... | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# Copyright (c) 2024, Tri Dao, Albert Gu.
# Adapted from https://github.com/state-spaces/mamba/blob/v2.2.4/mamba_ssm/ops/triton/selective_state_update.py
import torch
from packaging import version
from vllm imp... | --- vllm/model_executor/layers/mamba/ops/mamba_ssm.py
+++ vllm/model_executor/layers/mamba/ops/mamba_ssm.py
@@ -286,6 +286,7 @@
out=None,
num_accepted_tokens=None,
cu_seqlens=None,
+ is_blackwell=False,
):
"""
Argument:
@@ -391,17 +392,26 @@
if dst_state_batch_indices is not None
... | 21 | 11 | 2 | [
"mamba"
] | [
"B200"
] | [] | Optimize this triton kernel file from vllm (vllm/model_executor/layers/mamba/ops/mamba_ssm.py).
Goal: [Performance] Tune Mamba selective scan kernel for B200
Target hardware: B200
Target models: mamba
Current file:
```python
# SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the... | ## Purpose
Tune config of `selective_state_update` for **Nemotron Nano NVFP4** on **B200 (TP1)**.
## Test Plan
Compare vLLM performance (Nano NVFP4, B200, TP1) with main branch and this branch/PR.
## Test Result
Server command:
```
export VLLM_USE_FLASHINFER_MOE_FP4=1
export VLLM_FLASHINFER_MOE_BACKEND=throughput
... | [] | null | null |
vllm | d08b356ee08dc8e0b0dd052ed7bef5245e21d7af | 2026-01-22T12:47:04-08:00 | 32,619 | https://github.com/vllm-project/vllm/pull/32619 | [Perf] Create TMA-aligned input scale tensor for DeepGemm on Hopper (#32619) | [Perf] Create TMA-aligned input scale tensor for DeepGemm on Hopper (#32619)
Signed-off-by: Xin Yang <xyangx@amazon.com> | vllm/model_executor/layers/quantization/utils/fp8_utils.py | triton | Apache-2.0 | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# Adapted from https://github.com/sgl-project/sglang/pull/2575
import functools
import json
import os
from collections.abc import Callable, Sequence
from typing import Any
import torch
import vllm.envs as envs
... | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# Adapted from https://github.com/sgl-project/sglang/pull/2575
import functools
import json
import os
from collections.abc import Callable, Sequence
from typing import Any
import torch
import vllm.envs as envs
... | --- vllm/model_executor/layers/quantization/utils/fp8_utils.py
+++ vllm/model_executor/layers/quantization/utils/fp8_utils.py
@@ -35,6 +35,7 @@
from vllm.utils.deep_gemm import (
DeepGemmQuantScaleFMT,
fp8_gemm_nt,
+ get_tma_aligned_size,
is_deep_gemm_e8m0_used,
is_deep_gemm_supported,
shou... | 23 | 3 | 2 | [] | [
"HOPPER"
] | [] | Optimize this triton kernel file from vllm (vllm/model_executor/layers/quantization/utils/fp8_utils.py).
Goal: [Perf] Create TMA-aligned input scale tensor for DeepGemm on Hopper
Target hardware: HOPPER
Target models: unspecified
Current file:
```python
# SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: ... | ## Purpose
This PR is to create TMA-aligned input scale tensor for DeepGemm on Hopper.
I noticed on H200 `deep_gemm::transpose_fp32` was launched before `deep_gemm::sm90_fp8_gemm_1d2d_impl` every time, because deepgemm requires input scale tensor to be column major TMA-aligned layout on Hopper, see [here](https://git... | [{"scope": "e2e", "hardware": null, "model": "DeepSeek-R1-0528", "shape": null, "batch_size": 8, "metric": "output token throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 449.4, "optimized": 464.59, "stated_speedup": 1.03, "speedup": 1.0338}] | null | 1.0338 |
vllm | 744ef30484169694ef4aaba9420a03ed5b861b66 | 2026-01-22T18:55:23Z | 32,792 | https://github.com/vllm-project/vllm/pull/32792 | [CPU Backend] [Perf] Accelerate tensor-parallel/data-parallel inference across NUMA domains on Arm (#32792) | [CPU Backend] [Perf] Accelerate tensor-parallel/data-parallel inference across NUMA domains on Arm (#32792)
Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com> | csrc/cpu/cpu_types_arm.hpp | cpp | Apache-2.0 | #include <arm_neon.h>
#include <torch/all.h>
#include <cmath>
#if defined(__APPLE__)
#include "omp.h"
#endif
namespace vec_op {
#ifdef ARM_BF16_SUPPORT
#define VLLM_DISPATCH_CASE_FLOATING_TYPES(...) \
AT_DISPATCH_CASE(at::ScalarType::Float, __VA_ARGS__) \
AT_DISPATCH_CASE(at::ScalarType::Half, __... | #include <arm_neon.h>
#include <torch/all.h>
#include <cmath>
#if defined(__APPLE__)
#include "omp.h"
#endif
namespace vec_op {
#ifdef ARM_BF16_SUPPORT
#define VLLM_DISPATCH_CASE_FLOATING_TYPES(...) \
AT_DISPATCH_CASE(at::ScalarType::Float, __VA_ARGS__) \
AT_DISPATCH_CASE(at::ScalarType::Half, __... | --- csrc/cpu/cpu_types_arm.hpp
+++ csrc/cpu/cpu_types_arm.hpp
@@ -80,8 +80,10 @@
reg.val[1] = vld1q_f16(reinterpret_cast<const __fp16*>(ptr) + 8);
}
+ // ASIMD does not support non-temporal loads
+ explicit FP16Vec16(bool, const void* ptr) : FP16Vec16(ptr) {}
+
explicit FP16Vec16(const FP32Vec16& vec);
-... | 99 | 1 | 3 | [] | [
"CPU"
] | [] | Optimize this cpp kernel file from vllm (csrc/cpu/cpu_types_arm.hpp).
Goal: [CPU Backend] [Perf] Accelerate tensor-parallel/data-parallel inference across NUMA domains on Arm
Target hardware: CPU
Target models: unspecified
Current file:
```cpp
#include <arm_neon.h>
#include <torch/all.h>
#include <cmath>
#if defined... | [CPU Backend] [Perf] Accelerate tensor-parallel/data-parallel inference across NUMA domains on Arm
Fixes: #32786
## Purpose
This PR addresses #32786 by enabling vLLM's custom shared memory communicator for Arm, in favor of torch.distributed which has very high synchronization costs. It also enables auto thread bindi... | [{"scope": "e2e", "hardware": "c8g.metal.48xlarge", "model": "llama3.2-3b-Instruct", "shape": "tp=2, 2 NUMAs", "batch_size": null, "metric": "throughput", "unit": "%", "higher_is_better": true, "baseline": 100, "optimized": 196.3, "stated_speedup": null, "speedup": 1.963}, {"scope": "e2e", "hardware": "c8g.metal.48xlar... | null | 2 |
vllm | 744ef30484169694ef4aaba9420a03ed5b861b66 | 2026-01-22T18:55:23Z | 32,792 | https://github.com/vllm-project/vllm/pull/32792 | [CPU Backend] [Perf] Accelerate tensor-parallel/data-parallel inference across NUMA domains on Arm (#32792) | [CPU Backend] [Perf] Accelerate tensor-parallel/data-parallel inference across NUMA domains on Arm (#32792)
Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com> | csrc/cpu/shm.cpp | cpp | Apache-2.0 | #include "cpu/cpu_types.hpp"
#include <fcntl.h>
#include <sys/mman.h>
#include <sys/stat.h>
#include <unistd.h>
namespace {
#define MAX_SHM_RANK_NUM 8
#define PER_THREAD_SHM_BUFFER_BYTES (4 * 1024 * 1024)
static_assert(PER_THREAD_SHM_BUFFER_BYTES % 2 == 0);
#define PER_THREAD_SHM_BUFFER_OFFSET (PER_THREAD_SHM_BUFFER_... | #include "cpu/cpu_types.hpp"
#include <fcntl.h>
#include <sys/mman.h>
#include <sys/stat.h>
#include <unistd.h>
#ifdef __aarch64__
#include <atomic>
#endif
namespace {
#define MAX_SHM_RANK_NUM 8
#define PER_THREAD_SHM_BUFFER_BYTES (4 * 1024 * 1024)
static_assert(PER_THREAD_SHM_BUFFER_BYTES % 2 == 0);
#define PER_T... | --- csrc/cpu/shm.cpp
+++ csrc/cpu/shm.cpp
@@ -4,6 +4,10 @@
#include <sys/mman.h>
#include <sys/stat.h>
#include <unistd.h>
+
+#ifdef __aarch64__
+ #include <atomic>
+#endif
namespace {
#define MAX_SHM_RANK_NUM 8
@@ -34,8 +38,17 @@
};
struct ThreadSHMContext {
+#ifdef __aarch64__
+ // memory model is weaker... | 51 | 3 | 3 | [] | [
"CPU"
] | [] | Optimize this cpp kernel file from vllm (csrc/cpu/shm.cpp).
Goal: [CPU Backend] [Perf] Accelerate tensor-parallel/data-parallel inference across NUMA domains on Arm
Target hardware: CPU
Target models: unspecified
Current file:
```cpp
#include "cpu/cpu_types.hpp"
#include <fcntl.h>
#include <sys/mman.h>
#include <sys... | [CPU Backend] [Perf] Accelerate tensor-parallel/data-parallel inference across NUMA domains on Arm
Fixes: #32786
## Purpose
This PR addresses #32786 by enabling vLLM's custom shared memory communicator for Arm, in favor of torch.distributed which has very high synchronization costs. It also enables auto thread bindi... | [{"scope": "e2e", "hardware": "c8g.metal.48xlarge", "model": "llama3.2-3b-Instruct", "shape": "tp=2, 2 NUMAs", "batch_size": null, "metric": "throughput", "unit": "%", "higher_is_better": true, "baseline": 100, "optimized": 196.3, "stated_speedup": null, "speedup": 1.963}, {"scope": "e2e", "hardware": "c8g.metal.48xlar... | null | 2 |
vllm | 744ef30484169694ef4aaba9420a03ed5b861b66 | 2026-01-22T18:55:23Z | 32,792 | https://github.com/vllm-project/vllm/pull/32792 | [CPU Backend] [Perf] Accelerate tensor-parallel/data-parallel inference across NUMA domains on Arm (#32792) | [CPU Backend] [Perf] Accelerate tensor-parallel/data-parallel inference across NUMA domains on Arm (#32792)
Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com> | csrc/cpu/torch_bindings.cpp | cpp | Apache-2.0 | #include "cache.h"
#include "ops.h"
#include "core/registration.h"
#include <torch/library.h>
std::string init_cpu_threads_env(const std::string& cpu_ids);
void release_dnnl_matmul_handler(int64_t handler);
int64_t create_onednn_scaled_mm_handler(const torch::Tensor& b,
const... | #include "cache.h"
#include "ops.h"
#include "core/registration.h"
#include <torch/library.h>
std::string init_cpu_threads_env(const std::string& cpu_ids);
void release_dnnl_matmul_handler(int64_t handler);
int64_t create_onednn_scaled_mm_handler(const torch::Tensor& b,
const... | --- csrc/cpu/torch_bindings.cpp
+++ csrc/cpu/torch_bindings.cpp
@@ -230,7 +230,7 @@
#endif
// SHM CCL
-#ifdef __AVX512F__
+#if defined(__AVX512F__) || defined(__aarch64__)
ops.def("init_shm_manager(str name, int group_size, int rank) -> int",
&init_shm_manager);
ops.def("join_shm_manager(int handle... | 2 | 2 | 3 | [] | [
"CPU"
] | [] | Optimize this cpp kernel file from vllm (csrc/cpu/torch_bindings.cpp).
Goal: [CPU Backend] [Perf] Accelerate tensor-parallel/data-parallel inference across NUMA domains on Arm
Target hardware: CPU
Target models: unspecified
Current file:
```cpp
#include "cache.h"
#include "ops.h"
#include "core/registration.h"
#incl... | [CPU Backend] [Perf] Accelerate tensor-parallel/data-parallel inference across NUMA domains on Arm
Fixes: #32786
## Purpose
This PR addresses #32786 by enabling vLLM's custom shared memory communicator for Arm, in favor of torch.distributed which has very high synchronization costs. It also enables auto thread bindi... | [{"scope": "e2e", "hardware": "c8g.metal.48xlarge", "model": "llama3.2-3b-Instruct", "shape": "tp=2, 2 NUMAs", "batch_size": null, "metric": "throughput", "unit": "%", "higher_is_better": true, "baseline": 100, "optimized": 196.3, "stated_speedup": null, "speedup": 1.963}, {"scope": "e2e", "hardware": "c8g.metal.48xlar... | null | 2 |
vllm | 6c97b9b9b6337d021615ed74f9cf836b65c446d7 | 2026-01-20T11:34:39-05:00 | 32,273 | https://github.com/vllm-project/vllm/pull/32273 | [Perf] Only clone when needed for `moe_permute` (#32273) | [Perf] Only clone when needed for `moe_permute` (#32273)
Signed-off-by: yewentao256 <zhyanwentao@126.com> | csrc/moe/moe_permute_unpermute_op.cu | cuda | Apache-2.0 | #include <c10/core/ScalarType.h>
#include <torch/all.h>
#include <ATen/cuda/CUDAContext.h>
#include "permute_unpermute_kernels/moe_permute_unpermute_kernel.h"
#include "permute_unpermute_kernels/dispatch.h"
#include "core/registration.h"
// moe_permute kernels require at least CUDA 12.0
#if defined(CUDA_VERSION) && (C... | #include <c10/core/ScalarType.h>
#include <torch/all.h>
#include <ATen/cuda/CUDAContext.h>
#include "permute_unpermute_kernels/moe_permute_unpermute_kernel.h"
#include "permute_unpermute_kernels/dispatch.h"
#include "core/registration.h"
// moe_permute kernels require at least CUDA 12.0
#if defined(CUDA_VERSION) && (C... | --- csrc/moe/moe_permute_unpermute_op.cu
+++ csrc/moe/moe_permute_unpermute_op.cu
@@ -42,7 +42,7 @@
auto sort_workspace = torch::empty(
{sorter_size},
torch::dtype(torch::kInt8).device(torch::kCUDA).requires_grad(false));
- auto copy_topk_ids = topk_ids.clone(); // copy topk_ids for preprocess
+ tor... | 4 | 3 | 3 | [] | [] | [] | Optimize this cuda kernel file from vllm (csrc/moe/moe_permute_unpermute_op.cu).
Goal: [Perf] Only clone when needed for `moe_permute`
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
#include <c10/core/ScalarType.h>
#include <torch/all.h>
#include <ATen/cuda/CUDAContext.h>
#include "perm... | ## Purpose
Part of the https://github.com/vllm-project/vllm/issues/31755
Only clone when needed
## Test
`export MODEL="zai-org/GLM-4.7-FP8"`
`vllm serve $MODEL -tp 8 --port 9256 --enable-expert-parallel --max_num_seqs 128 `
`lm_eval --model local-completions --model_args "base_url=http://127.0.0.1:9256/v1/completi... | [] | null | null |
vllm | 6c97b9b9b6337d021615ed74f9cf836b65c446d7 | 2026-01-20T11:34:39-05:00 | 32,273 | https://github.com/vllm-project/vllm/pull/32273 | [Perf] Only clone when needed for `moe_permute` (#32273) | [Perf] Only clone when needed for `moe_permute` (#32273)
Signed-off-by: yewentao256 <zhyanwentao@126.com> | csrc/moe/permute_unpermute_kernels/moe_permute_unpermute_kernel.cu | cuda | Apache-2.0 |
#include "moe_permute_unpermute_kernel.h"
// moe_permute kernels require at least CUDA 12.0
#if defined(CUDA_VERSION) && (CUDA_VERSION >= 12000)
// CubKeyValueSorter definition begin
CubKeyValueSorter::CubKeyValueSorter()
: num_experts_(0), num_bits_(sizeof(int) * 8) {}
int CubKeyValueSorter::expertsToBits(int ... |
#include "moe_permute_unpermute_kernel.h"
// moe_permute kernels require at least CUDA 12.0
#if defined(CUDA_VERSION) && (CUDA_VERSION >= 12000)
// CubKeyValueSorter definition begin
CubKeyValueSorter::CubKeyValueSorter()
: num_experts_(0), num_bits_(sizeof(int) * 8) {}
int CubKeyValueSorter::expertsToBits(int ... | --- csrc/moe/permute_unpermute_kernels/moe_permute_unpermute_kernel.cu
+++ csrc/moe/permute_unpermute_kernels/moe_permute_unpermute_kernel.cu
@@ -109,7 +109,7 @@
sorted_indices, total_indices, num_experts, expert_first_token_offset);
}
-void sortAndScanExpert(int* expert_for_source_row, const int* source_rows... | 1 | 1 | 3 | [] | [] | [] | Optimize this cuda kernel file from vllm (csrc/moe/permute_unpermute_kernels/moe_permute_unpermute_kernel.cu).
Goal: [Perf] Only clone when needed for `moe_permute`
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
#include "moe_permute_unpermute_kernel.h"
// moe_permute kernels require ... | ## Purpose
Part of the https://github.com/vllm-project/vllm/issues/31755
Only clone when needed
## Test
`export MODEL="zai-org/GLM-4.7-FP8"`
`vllm serve $MODEL -tp 8 --port 9256 --enable-expert-parallel --max_num_seqs 128 `
`lm_eval --model local-completions --model_args "base_url=http://127.0.0.1:9256/v1/completi... | [] | null | null |
vllm | 6c97b9b9b6337d021615ed74f9cf836b65c446d7 | 2026-01-20T11:34:39-05:00 | 32,273 | https://github.com/vllm-project/vllm/pull/32273 | [Perf] Only clone when needed for `moe_permute` (#32273) | [Perf] Only clone when needed for `moe_permute` (#32273)
Signed-off-by: yewentao256 <zhyanwentao@126.com> | csrc/moe/permute_unpermute_kernels/moe_permute_unpermute_kernel.h | cpp | Apache-2.0 | #pragma once
// reference from tensorrt_llm moe kernel implementation archive in
// https://github.com/BBuf/tensorrt-llm-moe/tree/master
#include <c10/core/ScalarType.h>
#include <torch/all.h>
#include "dispatch.h"
#include <cub/cub.cuh>
#include <cub/device/device_radix_sort.cuh>
#include <cub/util_type.cuh>
#include... | #pragma once
// reference from tensorrt_llm moe kernel implementation archive in
// https://github.com/BBuf/tensorrt-llm-moe/tree/master
#include <c10/core/ScalarType.h>
#include <torch/all.h>
#include "dispatch.h"
#include <cub/cub.cuh>
#include <cub/device/device_radix_sort.cuh>
#include <cub/util_type.cuh>
#include... | --- csrc/moe/permute_unpermute_kernels/moe_permute_unpermute_kernel.h
+++ csrc/moe/permute_unpermute_kernels/moe_permute_unpermute_kernel.h
@@ -48,7 +48,7 @@
int64_t* expert_first_token_offset,
cudaStream_t stream);
-void sortAndScanExpert(int* e... | 1 | 1 | 3 | [] | [] | [] | Optimize this cpp kernel file from vllm (csrc/moe/permute_unpermute_kernels/moe_permute_unpermute_kernel.h).
Goal: [Perf] Only clone when needed for `moe_permute`
Target hardware: unspecified
Target models: unspecified
Current file:
```cpp
#pragma once
// reference from tensorrt_llm moe kernel implementation archive ... | ## Purpose
Part of the https://github.com/vllm-project/vllm/issues/31755
Only clone when needed
## Test
`export MODEL="zai-org/GLM-4.7-FP8"`
`vllm serve $MODEL -tp 8 --port 9256 --enable-expert-parallel --max_num_seqs 128 `
`lm_eval --model local-completions --model_args "base_url=http://127.0.0.1:9256/v1/completi... | [] | null | null |
vllm | 8cc26acd8b77c8af12d2fbf1f5bd38d09861928c | 2026-01-18T12:19:59+08:00 | 32,403 | https://github.com/vllm-project/vllm/pull/32403 | [Performance] Improve Triton prefill attention kernel's performance (#32403) | [Performance] Improve Triton prefill attention kernel's performance (#32403)
Signed-off-by: Isotr0py <mozf@mail2.sysu.edu.cn> | vllm/v1/attention/ops/triton_prefill_attention.py | triton | Apache-2.0 | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# Adapted from
# https://github.com/sgl-project/sglang/blob/97cb762bb65ebf05025eb342de03c184660427a3/python/sglang/srt/layers/attention/triton_ops/prefill_attention.py
# Changes:
# - Add support for sliding windo... | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# Adapted from
# https://github.com/sgl-project/sglang/blob/97cb762bb65ebf05025eb342de03c184660427a3/python/sglang/srt/layers/attention/triton_ops/prefill_attention.py
# Changes:
# - Add support for sliding windo... | --- vllm/v1/attention/ops/triton_prefill_attention.py
+++ vllm/v1/attention/ops/triton_prefill_attention.py
@@ -30,6 +30,7 @@
from vllm.platforms import current_platform
from vllm.triton_utils import tl, triton
+from vllm.utils.math_utils import RCP_LN2
@triton.jit
@@ -110,15 +111,7 @@
end_n_limit = block... | 27 | 46 | 1 | [] | [] | [] | Optimize this triton kernel file from vllm (vllm/v1/attention/ops/triton_prefill_attention.py).
Goal: [Performance] Improve Triton prefill attention kernel's performance
Target hardware: unspecified
Target models: unspecified
Current file:
```python
# SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copy... | <!-- markdownlint-disable -->
## Purpose
Refine prefill attention kernel with FA2 implementation based on https://github.com/ModelTC/LightLLM/blob/2fbd2b8a7b180570129bd539bb34cbe0a5dbb22a/lightllm/common/basemodel/triton_kernel/att/prefill_att/context_flashattention_nopad.py#L287-L288
- In previous implementation, we ... | [{"scope": "e2e", "hardware": null, "model": null, "shape": "Input_len=2048", "batch_size": 8, "metric": "throughput", "unit": "requests/s", "higher_is_better": true, "baseline": 33.9996, "optimized": 34.969, "stated_speedup": null, "speedup": 1.0285}, {"scope": "e2e", "hardware": null, "model": null, "shape": "Input_l... | null | 1.0201 |
vllm | 7a1030431ade33439902f5b0cf7ff4a69c0fc033 | 2026-01-16T09:45:04-08:00 | 29,843 | https://github.com/vllm-project/vllm/pull/29843 | Atomics Reduce Counting Optimization for SplitK Skinny GEMMs. (#29843) | Atomics Reduce Counting Optimization for SplitK Skinny GEMMs. (#29843)
Signed-off-by: Hashem Hashemi <hashem.hashemi@amd.com> | csrc/rocm/ops.h | cpp | Apache-2.0 | #pragma once
#include <torch/all.h>
torch::Tensor LLMM1(at::Tensor& in_a, at::Tensor& in_b,
const int64_t rows_per_block);
torch::Tensor wvSplitK(const at::Tensor& in_a, const at::Tensor& in_b,
const std::optional<at::Tensor>& in_bias,
const int64_t C... | #pragma once
#include <torch/all.h>
torch::Tensor LLMM1(at::Tensor& in_a, at::Tensor& in_b,
const int64_t rows_per_block);
torch::Tensor wvSplitK(const at::Tensor& in_a, const at::Tensor& in_b,
const std::optional<at::Tensor>& in_bias,
const int64_t C... | --- csrc/rocm/ops.h
+++ csrc/rocm/ops.h
@@ -8,6 +8,10 @@
torch::Tensor wvSplitK(const at::Tensor& in_a, const at::Tensor& in_b,
const std::optional<at::Tensor>& in_bias,
const int64_t CuCount);
+
+torch::Tensor wvSplitKrc(const at::Tensor& in_a, const at::Tensor& in_b,
+... | 4 | 0 | 4 | [] | [
"ROCM"
] | [] | Optimize this cpp kernel file from vllm (csrc/rocm/ops.h).
Goal: Atomics Reduce Counting Optimization for SplitK Skinny GEMMs.
Target hardware: ROCM
Target models: unspecified
Current file:
```cpp
#pragma once
#include <torch/all.h>
torch::Tensor LLMM1(at::Tensor& in_a, at::Tensor& in_b,
const i... | ## Purpose
Optimize N=16-128 M=128,640 range and K=2880 cases -- targeting decode GEMMs observed in low concurrency gpt-oss. After more testing can be expanded to all GEMMs where N=16-128 and **(M/16)*(K/512)** is less than SIMD count.
## Test Plan
## Test Result
---
<details>
<summary> Essential Elements of an Effe... | [] | null | null |
vllm | 7a1030431ade33439902f5b0cf7ff4a69c0fc033 | 2026-01-16T09:45:04-08:00 | 29,843 | https://github.com/vllm-project/vllm/pull/29843 | Atomics Reduce Counting Optimization for SplitK Skinny GEMMs. (#29843) | Atomics Reduce Counting Optimization for SplitK Skinny GEMMs. (#29843)
Signed-off-by: Hashem Hashemi <hashem.hashemi@amd.com> | csrc/rocm/skinny_gemms.cu | cuda | Apache-2.0 | #include <torch/all.h>
#include <ATen/cuda/CUDAContext.h>
#include <c10/cuda/CUDAGuard.h>
#include <cuda_runtime.h>
#include <cuda_fp16.h>
#include <cuda_bf16.h>
#include <stdexcept>
#include <algorithm>
#include "../cuda_compat.h"
#include "dispatch_utils.h"
#include "quantization/w8a8/fp8/common.cuh"
#if defined(... | #include <torch/all.h>
#include <ATen/cuda/CUDAContext.h>
#include <c10/cuda/CUDAGuard.h>
#include <cuda_runtime.h>
#include <cuda_fp16.h>
#include <cuda_bf16.h>
#include <stdexcept>
#include <algorithm>
#include "../cuda_compat.h"
#include "dispatch_utils.h"
#include "quantization/w8a8/fp8/common.cuh"
#if defined(... | --- csrc/rocm/skinny_gemms.cu
+++ csrc/rocm/skinny_gemms.cu
@@ -287,6 +287,11 @@
V0 += (s.x + s.y); \
}
+// To avoid LLVM silently upcasting to double
+__device__ inline unsigned int min__(uint32_t a, uint32_t b) {
+ return min(a, b);
+}
+
#if defined(_... | 545 | 9 | 4 | [] | [
"ROCM"
] | [] | Optimize this cuda kernel file from vllm (csrc/rocm/skinny_gemms.cu).
Goal: Atomics Reduce Counting Optimization for SplitK Skinny GEMMs.
Target hardware: ROCM
Target models: unspecified
Current file:
```cuda
#include <torch/all.h>
#include <ATen/cuda/CUDAContext.h>
#include <c10/cuda/CUDAGuard.h>
#include <cuda_run... | ## Purpose
Optimize N=16-128 M=128,640 range and K=2880 cases -- targeting decode GEMMs observed in low concurrency gpt-oss. After more testing can be expanded to all GEMMs where N=16-128 and **(M/16)*(K/512)** is less than SIMD count.
## Test Plan
## Test Result
---
<details>
<summary> Essential Elements of an Effe... | [] | null | null |
vllm | 7a1030431ade33439902f5b0cf7ff4a69c0fc033 | 2026-01-16T09:45:04-08:00 | 29,843 | https://github.com/vllm-project/vllm/pull/29843 | Atomics Reduce Counting Optimization for SplitK Skinny GEMMs. (#29843) | Atomics Reduce Counting Optimization for SplitK Skinny GEMMs. (#29843)
Signed-off-by: Hashem Hashemi <hashem.hashemi@amd.com> | csrc/rocm/torch_bindings.cpp | cpp | Apache-2.0 | #include "core/registration.h"
#include "rocm/ops.h"
// Note on op signatures:
// The X_meta signatures are for the meta functions corresponding to op X.
// They must be kept in sync with the signature for X. Generally, only
// functions that return Tensors require a meta function.
//
// See the following links for de... | #include "core/registration.h"
#include "rocm/ops.h"
// Note on op signatures:
// The X_meta signatures are for the meta functions corresponding to op X.
// They must be kept in sync with the signature for X. Generally, only
// functions that return Tensors require a meta function.
//
// See the following links for de... | --- csrc/rocm/torch_bindings.cpp
+++ csrc/rocm/torch_bindings.cpp
@@ -25,6 +25,12 @@
"wvSplitK(Tensor in_a, Tensor in_b, Tensor? in_bias, int CuCount) -> "
"Tensor");
rocm_ops.impl("wvSplitK", torch::kCUDA, &wvSplitK);
+
+ // Custom gemm op for skinny matrix-matrix multiplication
+ rocm_ops.def(
+ ... | 6 | 0 | 4 | [] | [
"ROCM"
] | [] | Optimize this cpp kernel file from vllm (csrc/rocm/torch_bindings.cpp).
Goal: Atomics Reduce Counting Optimization for SplitK Skinny GEMMs.
Target hardware: ROCM
Target models: unspecified
Current file:
```cpp
#include "core/registration.h"
#include "rocm/ops.h"
// Note on op signatures:
// The X_meta signatures are... | ## Purpose
Optimize N=16-128 M=128,640 range and K=2880 cases -- targeting decode GEMMs observed in low concurrency gpt-oss. After more testing can be expanded to all GEMMs where N=16-128 and **(M/16)*(K/512)** is less than SIMD count.
## Test Plan
## Test Result
---
<details>
<summary> Essential Elements of an Effe... | [] | null | null |
vllm | 130d6c9514856cb5a152329f0382d60ff6e8d97e | 2026-01-15T23:29:53+08:00 | 29,887 | https://github.com/vllm-project/vllm/pull/29887 | [ROCm][Perf] Enable shuffle kv cache layout and assembly paged attention kernel for `AiterFlashAttentionBackend` (#29887) | [ROCm][Perf] Enable shuffle kv cache layout and assembly paged attention kernel for `AiterFlashAttentionBackend` (#29887)
Signed-off-by: ganyi <ygan@amd.com> | vllm/v1/attention/backends/rocm_aiter_fa.py | triton | Apache-2.0 | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
"""Attention layer with AiterFlashAttention."""
from dataclasses import dataclass
from typing import ClassVar
import torch
from vllm.attention.layer import Attention
from vllm.config import VllmConfig, get_laye... | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
"""Attention layer with AiterFlashAttention."""
from dataclasses import dataclass
from typing import ClassVar
import torch
from vllm._aiter_ops import rocm_aiter_ops
from vllm.attention.layer import Attention
f... | --- vllm/v1/attention/backends/rocm_aiter_fa.py
+++ vllm/v1/attention/backends/rocm_aiter_fa.py
@@ -7,6 +7,7 @@
import torch
+from vllm._aiter_ops import rocm_aiter_ops
from vllm.attention.layer import Attention
from vllm.config import VllmConfig, get_layers_from_vllm_config
from vllm.logger import init_logger
... | 302 | 87 | 1 | [] | [
"ROCM"
] | [] | Optimize this triton kernel file from vllm (vllm/v1/attention/backends/rocm_aiter_fa.py).
Goal: [ROCm][Perf] Enable shuffle kv cache layout and assembly paged attention kernel for `AiterFlashAttentionBackend`
Target hardware: ROCM
Target models: unspecified
Current file:
```python
# SPDX-License-Identifier: Apache-2.... |
## Purpose
This PR add assembly paged attention kernel in aiter to `AiterFlashAttentionBackend`. We verify this implementation on `Qwen3-30B-A3B-FP8` Mi308 and observed at least about 20% thoughput gain and obvious latency reduction on tpot.
This PR add this flag `USING_SHUFFLE_LAYOUT` to control whether to enable as... | [{"scope": "e2e", "hardware": "Mi308", "model": "Qwen3-30B-A3B-FP8", "shape": null, "batch_size": 200, "metric": "Request throughput", "unit": "req/s", "higher_is_better": true, "baseline": 2.1, "optimized": 2.51, "stated_speedup": null, "speedup": 1.1952}, {"scope": "e2e", "hardware": "Mi308", "model": "Qwen3-30B-A3B-... | null | 1.1952 |
vllm | f28125d87b6a5976a1584267077d4f0287ce6ce2 | 2026-01-13T13:58:18-05:00 | 32,058 | https://github.com/vllm-project/vllm/pull/32058 | [Perf] Optimize grouped topk kernel, 1.2%~2% E2E Throughput improvement (#32058) | [Perf] Optimize grouped topk kernel, 1.2%~2% E2E Throughput improvement (#32058)
Signed-off-by: yewentao256 <zhyanwentao@126.com> | csrc/moe/grouped_topk_kernels.cu | cuda | Apache-2.0 | /*
* Adapted from
* https://github.com/NVIDIA/TensorRT-LLM/blob/v0.21.0/cpp/tensorrt_llm/kernels/noAuxTcKernels.cu
* Copyright (c) 2025, The vLLM team.
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION &
* AFFILIATES. All rights reserved. SPDX-License-Identifier: Apache-2.0
*
* Licensed under ... | /*
* Adapted from
* https://github.com/NVIDIA/TensorRT-LLM/blob/v0.21.0/cpp/tensorrt_llm/kernels/noAuxTcKernels.cu
* Copyright (c) 2025, The vLLM team.
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION &
* AFFILIATES. All rights reserved. SPDX-License-Identifier: Apache-2.0
*
* Licensed under ... | --- csrc/moe/grouped_topk_kernels.cu
+++ csrc/moe/grouped_topk_kernels.cu
@@ -31,8 +31,6 @@
constexpr unsigned FULL_WARP_MASK = 0xffffffff;
constexpr int32_t WARP_SIZE = 32;
-constexpr int32_t BLOCK_SIZE = 512;
-constexpr int32_t NUM_WARPS_PER_BLOCK = BLOCK_SIZE / WARP_SIZE;
namespace warp_topk {
@@ -63,14 +61... | 193 | 295 | 1 | [] | [] | [] | Optimize this cuda kernel file from vllm (csrc/moe/grouped_topk_kernels.cu).
Goal: [Perf] Optimize grouped topk kernel, 1.2%~2% E2E Throughput improvement
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Adapted from
* https://github.com/NVIDIA/TensorRT-LLM/blob/v0.21.0/cpp/tensorr... | ## Purpose
Part of the https://github.com/vllm-project/vllm/issues/31755
Here we combine the two kernels together, reducing global write and read
## Test
## Test
`export MODEL="zai-org/GLM-4.7-FP8"`
`vllm serve $MODEL -tp 8 --port 9256 --enable-expert-parallel --max_num_seqs 128`
### Acc
`lm_eval --model loca... | [] | null | null |
vllm | b8bf5c45bbbb1249bd1656557603da71e9d4c3b9 | 2026-01-10T19:13:44+01:00 | 31,984 | https://github.com/vllm-project/vllm/pull/31984 | [Kernel] Optimize Sliding Window Attention in 3D Triton Kernel (#31984) | [Kernel] Optimize Sliding Window Attention in 3D Triton Kernel (#31984)
Signed-off-by: Jan van Lunteren <jvl@zurich.ibm.com> | vllm/v1/attention/ops/triton_unified_attention.py | triton | Apache-2.0 | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# Authors:
# - Burkhard Ringlein <ngl@zurich.ibm.com>
# - Jan van Lunteren <jvl@zurich.ibm.com>
# - Chih-Chieh Yang <chih.chieh.yang@ibm.com>
# - Thomas Parnell <tpa@zurich.ibm.com>
import torch
from vllm.l... | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# Authors:
# - Burkhard Ringlein <ngl@zurich.ibm.com>
# - Jan van Lunteren <jvl@zurich.ibm.com>
# - Chih-Chieh Yang <chih.chieh.yang@ibm.com>
# - Thomas Parnell <tpa@zurich.ibm.com>
import torch
from vllm.l... | --- vllm/v1/attention/ops/triton_unified_attention.py
+++ vllm/v1/attention/ops/triton_unified_attention.py
@@ -545,10 +545,33 @@
# this prefix can be skipped)
num_tiles = cdiv_fn(max_seq_prefix_len, TILE_SIZE)
- # iterate through tiles within current segment
+ # ---- Sliding-window tile pruning -----... | 26 | 3 | 1 | [] | [] | [] | Optimize this triton kernel file from vllm (vllm/v1/attention/ops/triton_unified_attention.py).
Goal: [Kernel] Optimize Sliding Window Attention in 3D Triton Kernel
Target hardware: unspecified
Target models: unspecified
Current file:
```python
# SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright... | ## Purpose
This pull request improves the efficiency of sliding window attention in the 3D kernel by applying the same optimization used in the 2D kernel. It ensures that only tiles within the defined window are processed, resulting in better performance and reduced computational overhead.
## Performance
The followin... | [{"scope": "e2e", "hardware": "NVIDIA H100", "model": "openai/gpt-oss-20b", "shape": "input-len=500, output-len=6400; output-len=12800", "batch_size": 1, "metric": "latency", "unit": null, "higher_is_better": false, "baseline": null, "optimized": null, "stated_speedup": 1.03, "speedup": 1.03}, {"scope": "e2e", "hardwar... | null | 1.035 |
vllm | 308feab33f3b386a6701cc5b28337bc04fe13a9b | 2026-01-09T14:13:43-05:00 | 31,830 | https://github.com/vllm-project/vllm/pull/31830 | [Perf] Optimize cutlass moe problem size calculation, 5.3% E2E Throughput improvement, 2.2% TTFT improvement (#31830) | [Perf] Optimize cutlass moe problem size calculation, 5.3% E2E Throughput improvement, 2.2% TTFT improvement (#31830)
Signed-off-by: yewentao256 <zhyanwentao@126.com>
Signed-off-by: Wentao Ye <44945378+yewentao256@users.noreply.github.com>
Co-authored-by: Luka Govedič <ProExpertProg@users.noreply.github.com> | csrc/ops.h | cpp | Apache-2.0 | #pragma once
#include <optional>
#include <torch/library.h>
#include "core/scalar_type.hpp"
#include <vector>
torch::Tensor weak_ref_tensor(torch::Tensor& tensor) {
// Ensure tensor is on CUDA
if (!tensor.is_cuda()) {
throw std::runtime_error("Tensor must be on CUDA device");
}
// Get the raw data poin... | #pragma once
#include <optional>
#include <torch/library.h>
#include "core/scalar_type.hpp"
#include <vector>
torch::Tensor weak_ref_tensor(torch::Tensor& tensor) {
// Ensure tensor is on CUDA
if (!tensor.is_cuda()) {
throw std::runtime_error("Tensor must be on CUDA device");
}
// Get the raw data poin... | --- csrc/ops.h
+++ csrc/ops.h
@@ -265,6 +265,11 @@
const int64_t k, const std::optional<torch::Tensor>& blockscale_offsets,
std::optional<bool> force_swap_ab = std::nullopt);
+void get_cutlass_moe_mm_problem_sizes_from_expert_offsets(
+ const torch::Tensor& expert_first_token_offset,
+ torch::Tensor& ... | 5 | 0 | 5 | [] | [] | [] | Optimize this cpp kernel file from vllm (csrc/ops.h).
Goal: [Perf] Optimize cutlass moe problem size calculation, 5.3% E2E Throughput improvement, 2.2% TTFT improvement
Target hardware: unspecified
Target models: unspecified
Current file:
```cpp
#pragma once
#include <optional>
#include <torch/library.h>
#include "... | ## Purpose
Part of the https://github.com/vllm-project/vllm/issues/31755
Here we add a kernel for faster calculation of problem size
## Test
`export MODEL="zai-org/GLM-4.7-FP8"`
`vllm serve $MODEL -tp 8 --port 9256 --enable-expert-parallel --max_num_seqs 128`
### Acc
`lm_eval --model local-completions --model_... | [] | null | null |
vllm | 308feab33f3b386a6701cc5b28337bc04fe13a9b | 2026-01-09T14:13:43-05:00 | 31,830 | https://github.com/vllm-project/vllm/pull/31830 | [Perf] Optimize cutlass moe problem size calculation, 5.3% E2E Throughput improvement, 2.2% TTFT improvement (#31830) | [Perf] Optimize cutlass moe problem size calculation, 5.3% E2E Throughput improvement, 2.2% TTFT improvement (#31830)
Signed-off-by: yewentao256 <zhyanwentao@126.com>
Signed-off-by: Wentao Ye <44945378+yewentao256@users.noreply.github.com>
Co-authored-by: Luka Govedič <ProExpertProg@users.noreply.github.com> | csrc/quantization/w8a8/cutlass/moe/moe_data.cu | cuda | Apache-2.0 | #include <cudaTypedefs.h>
#include <c10/cuda/CUDAGuard.h>
#include <torch/all.h>
#include <iostream>
constexpr uint64_t THREADS_PER_EXPERT = 512;
// threshold must match the dispatch logic in run_cutlass_moe_mm_sm90()
constexpr int SWAP_AB_THRESHOLD = 64;
template <bool SWAP_AB>
__global__ void compute_problem_size... | #include <cudaTypedefs.h>
#include <c10/cuda/CUDAGuard.h>
#include <torch/all.h>
#include "dispatch_utils.h"
#include <iostream>
constexpr uint64_t THREADS_PER_EXPERT = 512;
// threshold must match the dispatch logic in run_cutlass_moe_mm_sm90()
constexpr int SWAP_AB_THRESHOLD = 64;
template <bool SWAP_AB>
__globa... | --- csrc/quantization/w8a8/cutlass/moe/moe_data.cu
+++ csrc/quantization/w8a8/cutlass/moe/moe_data.cu
@@ -2,6 +2,8 @@
#include <c10/cuda/CUDAGuard.h>
#include <torch/all.h>
+
+#include "dispatch_utils.h"
#include <iostream>
@@ -114,22 +116,17 @@
const bool swap_ab) {
... | 97 | 13 | 5 | [] | [] | [] | Optimize this cuda kernel file from vllm (csrc/quantization/w8a8/cutlass/moe/moe_data.cu).
Goal: [Perf] Optimize cutlass moe problem size calculation, 5.3% E2E Throughput improvement, 2.2% TTFT improvement
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
#include <cudaTypedefs.h>
#includ... | ## Purpose
Part of the https://github.com/vllm-project/vllm/issues/31755
Here we add a kernel for faster calculation of problem size
## Test
`export MODEL="zai-org/GLM-4.7-FP8"`
`vllm serve $MODEL -tp 8 --port 9256 --enable-expert-parallel --max_num_seqs 128`
### Acc
`lm_eval --model local-completions --model_... | [] | null | null |
vllm | 308feab33f3b386a6701cc5b28337bc04fe13a9b | 2026-01-09T14:13:43-05:00 | 31,830 | https://github.com/vllm-project/vllm/pull/31830 | [Perf] Optimize cutlass moe problem size calculation, 5.3% E2E Throughput improvement, 2.2% TTFT improvement (#31830) | [Perf] Optimize cutlass moe problem size calculation, 5.3% E2E Throughput improvement, 2.2% TTFT improvement (#31830)
Signed-off-by: yewentao256 <zhyanwentao@126.com>
Signed-off-by: Wentao Ye <44945378+yewentao256@users.noreply.github.com>
Co-authored-by: Luka Govedič <ProExpertProg@users.noreply.github.com> | csrc/quantization/w8a8/cutlass/scaled_mm_entry.cu | cuda | Apache-2.0 | #include <cudaTypedefs.h>
#include <c10/cuda/CUDAGuard.h>
#include <torch/all.h>
#include "cutlass_extensions/common.hpp"
void cutlass_scaled_mm_sm75(torch::Tensor& c, torch::Tensor const& a,
torch::Tensor const& b,
torch::Tensor const& a_scales,
... | #include <cudaTypedefs.h>
#include <c10/cuda/CUDAGuard.h>
#include <torch/all.h>
#include "cutlass_extensions/common.hpp"
void cutlass_scaled_mm_sm75(torch::Tensor& c, torch::Tensor const& a,
torch::Tensor const& b,
torch::Tensor const& a_scales,
... | --- csrc/quantization/w8a8/cutlass/scaled_mm_entry.cu
+++ csrc/quantization/w8a8/cutlass/scaled_mm_entry.cu
@@ -83,6 +83,11 @@
const int64_t k, const std::optional<torch::Tensor>& blockscale_offsets,
std::optional<bool> force_swap_ab = std::nullopt);
+void get_cutlass_moe_mm_problem_sizes_from_expert_offset... | 24 | 0 | 5 | [] | [] | [] | Optimize this cuda kernel file from vllm (csrc/quantization/w8a8/cutlass/scaled_mm_entry.cu).
Goal: [Perf] Optimize cutlass moe problem size calculation, 5.3% E2E Throughput improvement, 2.2% TTFT improvement
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
#include <cudaTypedefs.h>
#inc... | ## Purpose
Part of the https://github.com/vllm-project/vllm/issues/31755
Here we add a kernel for faster calculation of problem size
## Test
`export MODEL="zai-org/GLM-4.7-FP8"`
`vllm serve $MODEL -tp 8 --port 9256 --enable-expert-parallel --max_num_seqs 128`
### Acc
`lm_eval --model local-completions --model_... | [] | null | null |
vllm | 308feab33f3b386a6701cc5b28337bc04fe13a9b | 2026-01-09T14:13:43-05:00 | 31,830 | https://github.com/vllm-project/vllm/pull/31830 | [Perf] Optimize cutlass moe problem size calculation, 5.3% E2E Throughput improvement, 2.2% TTFT improvement (#31830) | [Perf] Optimize cutlass moe problem size calculation, 5.3% E2E Throughput improvement, 2.2% TTFT improvement (#31830)
Signed-off-by: yewentao256 <zhyanwentao@126.com>
Signed-off-by: Wentao Ye <44945378+yewentao256@users.noreply.github.com>
Co-authored-by: Luka Govedič <ProExpertProg@users.noreply.github.com> | csrc/torch_bindings.cpp | cpp | Apache-2.0 | #include "cache.h"
#include "cuda_utils.h"
#include "ops.h"
#include "core/registration.h"
#include <torch/library.h>
#include <torch/version.h>
// Note on op signatures:
// The X_meta signatures are for the meta functions corresponding to op X.
// They must be kept in sync with the signature for X. Generally, only
/... | #include "cache.h"
#include "cuda_utils.h"
#include "ops.h"
#include "core/registration.h"
#include <torch/library.h>
#include <torch/version.h>
// Note on op signatures:
// The X_meta signatures are for the meta functions corresponding to op X.
// They must be kept in sync with the signature for X. Generally, only
/... | --- csrc/torch_bindings.cpp
+++ csrc/torch_bindings.cpp
@@ -487,6 +487,17 @@
ops.impl("get_cutlass_moe_mm_problem_sizes", torch::kCUDA,
&get_cutlass_moe_mm_problem_sizes);
+ // compute per-expert problem sizes from expert_first_token_offset
+ // produced by vLLM's moe_permute kernel
+ ops.def(
+ ... | 11 | 0 | 5 | [] | [] | [] | Optimize this cpp kernel file from vllm (csrc/torch_bindings.cpp).
Goal: [Perf] Optimize cutlass moe problem size calculation, 5.3% E2E Throughput improvement, 2.2% TTFT improvement
Target hardware: unspecified
Target models: unspecified
Current file:
```cpp
#include "cache.h"
#include "cuda_utils.h"
#include "ops.h"... | ## Purpose
Part of the https://github.com/vllm-project/vllm/issues/31755
Here we add a kernel for faster calculation of problem size
## Test
`export MODEL="zai-org/GLM-4.7-FP8"`
`vllm serve $MODEL -tp 8 --port 9256 --enable-expert-parallel --max_num_seqs 128`
### Acc
`lm_eval --model local-completions --model_... | [] | null | null |
vllm | 34cd32fe302f63270ac90c3ac8ec68b561aac3d7 | 2026-01-09T09:40:33-05:00 | 31,832 | https://github.com/vllm-project/vllm/pull/31832 | [Perf][Kernel] Fused SiLU+Mul+Quant kernel for NVFP4 cutlass_moe (#31832) | [Perf][Kernel] Fused SiLU+Mul+Quant kernel for NVFP4 cutlass_moe (#31832)
Signed-off-by: mgoin <mgoin64@gmail.com>
Signed-off-by: Michael Goin <mgoin64@gmail.com> | csrc/ops.h | cpp | Apache-2.0 | #pragma once
#include <optional>
#include <torch/library.h>
#include "core/scalar_type.hpp"
#include <vector>
torch::Tensor weak_ref_tensor(torch::Tensor& tensor) {
// Ensure tensor is on CUDA
if (!tensor.is_cuda()) {
throw std::runtime_error("Tensor must be on CUDA device");
}
// Get the raw data poin... | #pragma once
#include <optional>
#include <torch/library.h>
#include "core/scalar_type.hpp"
#include <vector>
torch::Tensor weak_ref_tensor(torch::Tensor& tensor) {
// Ensure tensor is on CUDA
if (!tensor.is_cuda()) {
throw std::runtime_error("Tensor must be on CUDA device");
}
// Get the raw data poin... | --- csrc/ops.h
+++ csrc/ops.h
@@ -301,6 +301,12 @@
torch::Tensor const& input_offset_by_experts,
torch::Tensor const& output_scale_offset_by_experts);
+void silu_and_mul_scaled_fp4_experts_quant(
+ torch::Tensor& output, torch::Tensor& output_scale,
+ torch::Tensor const& input, torch::Tensor const& i... | 6 | 0 | 7 | [] | [] | [] | Optimize this cpp kernel file from vllm (csrc/ops.h).
Goal: [Perf][Kernel] Fused SiLU+Mul+Quant kernel for NVFP4 cutlass_moe
Target hardware: unspecified
Target models: unspecified
Current file:
```cpp
#pragma once
#include <optional>
#include <torch/library.h>
#include "core/scalar_type.hpp"
#include <vector>
to... | ## Purpose
We can easily fuse the silu_and_mul operation into the nvfp4 quantization operation for moe, which we already do for dense nvfp4 as of https://github.com/vllm-project/vllm/pull/23671. This PR just generalizes some utils to expose the same functionality for expert quantization. This seems to improve latency ... | [{"scope": "e2e", "hardware": null, "model": "nvidia/Qwen3-30B-A3B-NVFP4", "shape": "input-len=100,output-len=100", "batch_size": 8, "metric": "benchmark duration", "unit": "s", "higher_is_better": false, "baseline": 0.8, "optimized": 0.78, "stated_speedup": null, "speedup": 1.0256}, {"scope": "e2e", "hardware": null, ... | null | 1.0256 |
vllm | 34cd32fe302f63270ac90c3ac8ec68b561aac3d7 | 2026-01-09T09:40:33-05:00 | 31,832 | https://github.com/vllm-project/vllm/pull/31832 | [Perf][Kernel] Fused SiLU+Mul+Quant kernel for NVFP4 cutlass_moe (#31832) | [Perf][Kernel] Fused SiLU+Mul+Quant kernel for NVFP4 cutlass_moe (#31832)
Signed-off-by: mgoin <mgoin64@gmail.com>
Signed-off-by: Michael Goin <mgoin64@gmail.com> | csrc/quantization/fp4/activation_nvfp4_quant_fusion_kernels.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless requi... | /*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless requi... | --- csrc/quantization/fp4/activation_nvfp4_quant_fusion_kernels.cu
+++ csrc/quantization/fp4/activation_nvfp4_quant_fusion_kernels.cu
@@ -30,37 +30,6 @@
#include "nvfp4_utils.cuh"
namespace vllm {
-
-// silu in float32
-__device__ __forceinline__ float silu(float x) {
- return __fdividef(x, (1.f + __expf(-x)));
-}... | 0 | 31 | 7 | [] | [] | [] | Optimize this cuda kernel file from vllm (csrc/quantization/fp4/activation_nvfp4_quant_fusion_kernels.cu).
Goal: [Perf][Kernel] Fused SiLU+Mul+Quant kernel for NVFP4 cutlass_moe
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights rese... | ## Purpose
We can easily fuse the silu_and_mul operation into the nvfp4 quantization operation for moe, which we already do for dense nvfp4 as of https://github.com/vllm-project/vllm/pull/23671. This PR just generalizes some utils to expose the same functionality for expert quantization. This seems to improve latency ... | [{"scope": "e2e", "hardware": null, "model": "nvidia/Qwen3-30B-A3B-NVFP4", "shape": "input-len=100,output-len=100", "batch_size": 8, "metric": "benchmark duration", "unit": "s", "higher_is_better": false, "baseline": 0.8, "optimized": 0.78, "stated_speedup": null, "speedup": 1.0256}, {"scope": "e2e", "hardware": null, ... | null | 1.0256 |
vllm | 34cd32fe302f63270ac90c3ac8ec68b561aac3d7 | 2026-01-09T09:40:33-05:00 | 31,832 | https://github.com/vllm-project/vllm/pull/31832 | [Perf][Kernel] Fused SiLU+Mul+Quant kernel for NVFP4 cutlass_moe (#31832) | [Perf][Kernel] Fused SiLU+Mul+Quant kernel for NVFP4 cutlass_moe (#31832)
Signed-off-by: mgoin <mgoin64@gmail.com>
Signed-off-by: Michael Goin <mgoin64@gmail.com> | csrc/quantization/fp4/nvfp4_experts_quant.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless requi... | /*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless requi... | --- csrc/quantization/fp4/nvfp4_experts_quant.cu
+++ csrc/quantization/fp4/nvfp4_experts_quant.cu
@@ -31,8 +31,12 @@
namespace vllm {
+// NVFP4 quantization kernel for experts (low-latency path).
+// When FUSE_SILU_MUL=true, expects input with gate||up layout and fuses
+// SiLU(gate)*up before quantization.
// Us... | 137 | 58 | 7 | [] | [] | [] | Optimize this cuda kernel file from vllm (csrc/quantization/fp4/nvfp4_experts_quant.cu).
Goal: [Perf][Kernel] Fused SiLU+Mul+Quant kernel for NVFP4 cutlass_moe
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*
* Licens... | ## Purpose
We can easily fuse the silu_and_mul operation into the nvfp4 quantization operation for moe, which we already do for dense nvfp4 as of https://github.com/vllm-project/vllm/pull/23671. This PR just generalizes some utils to expose the same functionality for expert quantization. This seems to improve latency ... | [{"scope": "e2e", "hardware": null, "model": "nvidia/Qwen3-30B-A3B-NVFP4", "shape": "input-len=100,output-len=100", "batch_size": 8, "metric": "benchmark duration", "unit": "s", "higher_is_better": false, "baseline": 0.8, "optimized": 0.78, "stated_speedup": null, "speedup": 1.0256}, {"scope": "e2e", "hardware": null, ... | null | 1.0256 |
vllm | 34cd32fe302f63270ac90c3ac8ec68b561aac3d7 | 2026-01-09T09:40:33-05:00 | 31,832 | https://github.com/vllm-project/vllm/pull/31832 | [Perf][Kernel] Fused SiLU+Mul+Quant kernel for NVFP4 cutlass_moe (#31832) | [Perf][Kernel] Fused SiLU+Mul+Quant kernel for NVFP4 cutlass_moe (#31832)
Signed-off-by: mgoin <mgoin64@gmail.com>
Signed-off-by: Michael Goin <mgoin64@gmail.com> | csrc/quantization/fp4/nvfp4_quant_entry.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless requi... | /*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless requi... | --- csrc/quantization/fp4/nvfp4_quant_entry.cu
+++ csrc/quantization/fp4/nvfp4_quant_entry.cu
@@ -41,6 +41,15 @@
torch::Tensor& input_sf);
#endif
+#if (defined(ENABLE_NVFP4_SM100) && ENABLE_NVFP4_SM100) || \
+ (defined(ENABLE_NVFP4_SM120) && ENABLE_NVFP4_SM120)
+void silu_and... | 24 | 0 | 7 | [] | [] | [] | Optimize this cuda kernel file from vllm (csrc/quantization/fp4/nvfp4_quant_entry.cu).
Goal: [Perf][Kernel] Fused SiLU+Mul+Quant kernel for NVFP4 cutlass_moe
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed... | ## Purpose
We can easily fuse the silu_and_mul operation into the nvfp4 quantization operation for moe, which we already do for dense nvfp4 as of https://github.com/vllm-project/vllm/pull/23671. This PR just generalizes some utils to expose the same functionality for expert quantization. This seems to improve latency ... | [{"scope": "e2e", "hardware": null, "model": "nvidia/Qwen3-30B-A3B-NVFP4", "shape": "input-len=100,output-len=100", "batch_size": 8, "metric": "benchmark duration", "unit": "s", "higher_is_better": false, "baseline": 0.8, "optimized": 0.78, "stated_speedup": null, "speedup": 1.0256}, {"scope": "e2e", "hardware": null, ... | null | 1.0256 |
vllm | 34cd32fe302f63270ac90c3ac8ec68b561aac3d7 | 2026-01-09T09:40:33-05:00 | 31,832 | https://github.com/vllm-project/vllm/pull/31832 | [Perf][Kernel] Fused SiLU+Mul+Quant kernel for NVFP4 cutlass_moe (#31832) | [Perf][Kernel] Fused SiLU+Mul+Quant kernel for NVFP4 cutlass_moe (#31832)
Signed-off-by: mgoin <mgoin64@gmail.com>
Signed-off-by: Michael Goin <mgoin64@gmail.com> | csrc/quantization/fp4/nvfp4_utils.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless requi... | /*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless requi... | --- csrc/quantization/fp4/nvfp4_utils.cuh
+++ csrc/quantization/fp4/nvfp4_utils.cuh
@@ -239,4 +239,34 @@
return e2m1Vec;
}
+// silu in float32
+__device__ __forceinline__ float silu(float x) {
+ return __fdividef(x, (1.f + __expf(-x)));
+}
+
+__device__ __forceinline__ float2 silu2(float2 x) {
+ return make_flo... | 30 | 0 | 7 | [] | [] | [] | Optimize this cuda kernel file from vllm (csrc/quantization/fp4/nvfp4_utils.cuh).
Goal: [Perf][Kernel] Fused SiLU+Mul+Quant kernel for NVFP4 cutlass_moe
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed unde... | ## Purpose
We can easily fuse the silu_and_mul operation into the nvfp4 quantization operation for moe, which we already do for dense nvfp4 as of https://github.com/vllm-project/vllm/pull/23671. This PR just generalizes some utils to expose the same functionality for expert quantization. This seems to improve latency ... | [{"scope": "e2e", "hardware": null, "model": "nvidia/Qwen3-30B-A3B-NVFP4", "shape": "input-len=100,output-len=100", "batch_size": 8, "metric": "benchmark duration", "unit": "s", "higher_is_better": false, "baseline": 0.8, "optimized": 0.78, "stated_speedup": null, "speedup": 1.0256}, {"scope": "e2e", "hardware": null, ... | null | 1.0256 |
vllm | 34cd32fe302f63270ac90c3ac8ec68b561aac3d7 | 2026-01-09T09:40:33-05:00 | 31,832 | https://github.com/vllm-project/vllm/pull/31832 | [Perf][Kernel] Fused SiLU+Mul+Quant kernel for NVFP4 cutlass_moe (#31832) | [Perf][Kernel] Fused SiLU+Mul+Quant kernel for NVFP4 cutlass_moe (#31832)
Signed-off-by: mgoin <mgoin64@gmail.com>
Signed-off-by: Michael Goin <mgoin64@gmail.com> | csrc/torch_bindings.cpp | cpp | Apache-2.0 | #include "cache.h"
#include "cuda_utils.h"
#include "ops.h"
#include "core/registration.h"
#include <torch/library.h>
#include <torch/version.h>
// Note on op signatures:
// The X_meta signatures are for the meta functions corresponding to op X.
// They must be kept in sync with the signature for X. Generally, only
/... | #include "cache.h"
#include "cuda_utils.h"
#include "ops.h"
#include "core/registration.h"
#include <torch/library.h>
#include <torch/version.h>
// Note on op signatures:
// The X_meta signatures are for the meta functions corresponding to op X.
// They must be kept in sync with the signature for X. Generally, only
/... | --- csrc/torch_bindings.cpp
+++ csrc/torch_bindings.cpp
@@ -558,6 +558,15 @@
"Tensor output_scale_offset_by_experts) -> ()");
ops.impl("scaled_fp4_experts_quant", torch::kCUDA, &scaled_fp4_experts_quant);
+ // Fused SiLU+Mul+NVFP4 experts quantization.
+ ops.def(
+ "silu_and_mul_scaled_fp4_experts_qu... | 9 | 0 | 7 | [] | [] | [] | Optimize this cpp kernel file from vllm (csrc/torch_bindings.cpp).
Goal: [Perf][Kernel] Fused SiLU+Mul+Quant kernel for NVFP4 cutlass_moe
Target hardware: unspecified
Target models: unspecified
Current file:
```cpp
#include "cache.h"
#include "cuda_utils.h"
#include "ops.h"
#include "core/registration.h"
#include <t... | ## Purpose
We can easily fuse the silu_and_mul operation into the nvfp4 quantization operation for moe, which we already do for dense nvfp4 as of https://github.com/vllm-project/vllm/pull/23671. This PR just generalizes some utils to expose the same functionality for expert quantization. This seems to improve latency ... | [{"scope": "e2e", "hardware": null, "model": "nvidia/Qwen3-30B-A3B-NVFP4", "shape": "input-len=100,output-len=100", "batch_size": 8, "metric": "benchmark duration", "unit": "s", "higher_is_better": false, "baseline": 0.8, "optimized": 0.78, "stated_speedup": null, "speedup": 1.0256}, {"scope": "e2e", "hardware": null, ... | null | 1.0256 |
vllm | 1a19e9cd87b6bb091fc9c530e6446601db52b58e | 2026-01-09T12:28:02+01:00 | 31,380 | https://github.com/vllm-project/vllm/pull/31380 | [Bugfix][ROCm]Fix Qwen3-Next-80B-A3B-Thinking inference and optimize non-standard block size (544) support under rocm_atten (#31380) | [Bugfix][ROCm]Fix Qwen3-Next-80B-A3B-Thinking inference and optimize non-standard block size (544) support under rocm_atten (#31380)
Signed-off-by: vllmellm <vllm.ellm@embeddedllm.com> | vllm/attention/ops/chunked_prefill_paged_decode.py | triton | Apache-2.0 | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# Authors:
# - Burkhard Ringlein <ngl@zurich.ibm.com>
# - Jan van Lunteren <jvl@zurich.ibm.com>
# - Chih-Chieh Yang <chih.chieh.yang@ibm.com>
# - Thomas Parnell <tpa@zurich.ibm.com>
import torch
from vllm i... | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# Authors:
# - Burkhard Ringlein <ngl@zurich.ibm.com>
# - Jan van Lunteren <jvl@zurich.ibm.com>
# - Chih-Chieh Yang <chih.chieh.yang@ibm.com>
# - Thomas Parnell <tpa@zurich.ibm.com>
import torch
from vllm i... | --- vllm/attention/ops/chunked_prefill_paged_decode.py
+++ vllm/attention/ops/chunked_prefill_paged_decode.py
@@ -46,6 +46,7 @@
output_stride_0: tl.int64, # int
output_stride_1: tl.int64, # int, should be equal to head_size
BLOCK_SIZE: tl.constexpr, # int
+ PHYSICAL_BLOCK_SIZE: tl.constexpr, # int... | 85 | 30 | 4 | [
"qwen"
] | [
"ROCM"
] | [] | Optimize this triton kernel file from vllm (vllm/attention/ops/chunked_prefill_paged_decode.py).
Goal: [Bugfix][ROCm]Fix Qwen3-Next-80B-A3B-Thinking inference and optimize non-standard block size (544) support under rocm_atten
Target hardware: ROCM
Target models: qwen
Current file:
```python
# SPDX-License-Identifier... | ## Purpose
Fixes #26473
This PR refactors the rocm_attn backend kernels to support models with non-power-of-2 block sizes, specifically the Qwen/Qwen3-Next-80B-A3B-Thinking model.
The core of this update is a Dynamic Dispatching Mechanism:Standard Path ($2^n$): For models with power-of-2 block sizes (16, 32, 64, 128... | [] | null | null |
vllm | 1a19e9cd87b6bb091fc9c530e6446601db52b58e | 2026-01-09T12:28:02+01:00 | 31,380 | https://github.com/vllm-project/vllm/pull/31380 | [Bugfix][ROCm]Fix Qwen3-Next-80B-A3B-Thinking inference and optimize non-standard block size (544) support under rocm_atten (#31380) | [Bugfix][ROCm]Fix Qwen3-Next-80B-A3B-Thinking inference and optimize non-standard block size (544) support under rocm_atten (#31380)
Signed-off-by: vllmellm <vllm.ellm@embeddedllm.com> | vllm/attention/ops/prefix_prefill.py | triton | Apache-2.0 | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# The kernels in this file are adapted from LightLLM's context_attention_fwd:
# https://github.com/ModelTC/lightllm/blob/main/lightllm/models/llama/triton_kernel/context_flashattention_nopad.py
import torch
fro... | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# The kernels in this file are adapted from LightLLM's context_attention_fwd:
# https://github.com/ModelTC/lightllm/blob/main/lightllm/models/llama/triton_kernel/context_flashattention_nopad.py
import torch
fro... | --- vllm/attention/ops/prefix_prefill.py
+++ vllm/attention/ops/prefix_prefill.py
@@ -79,6 +79,7 @@
BLOCK_DMODEL: tl.constexpr,
BLOCK_DMODEL_PADDED: tl.constexpr,
BLOCK_SIZE: tl.constexpr,
+ PHYSICAL_BLOCK_SIZE: tl.constexpr,
BLOCK_N: tl.constexpr,
SLIDING_WINDOW: tl.constexpr,
num_unro... | 81 | 33 | 4 | [
"qwen"
] | [
"ROCM"
] | [] | Optimize this triton kernel file from vllm (vllm/attention/ops/prefix_prefill.py).
Goal: [Bugfix][ROCm]Fix Qwen3-Next-80B-A3B-Thinking inference and optimize non-standard block size (544) support under rocm_atten
Target hardware: ROCM
Target models: qwen
Current file:
```python
# SPDX-License-Identifier: Apache-2.0
#... | ## Purpose
Fixes #26473
This PR refactors the rocm_attn backend kernels to support models with non-power-of-2 block sizes, specifically the Qwen/Qwen3-Next-80B-A3B-Thinking model.
The core of this update is a Dynamic Dispatching Mechanism:Standard Path ($2^n$): For models with power-of-2 block sizes (16, 32, 64, 128... | [] | null | null |
vllm | 1a19e9cd87b6bb091fc9c530e6446601db52b58e | 2026-01-09T12:28:02+01:00 | 31,380 | https://github.com/vllm-project/vllm/pull/31380 | [Bugfix][ROCm]Fix Qwen3-Next-80B-A3B-Thinking inference and optimize non-standard block size (544) support under rocm_atten (#31380) | [Bugfix][ROCm]Fix Qwen3-Next-80B-A3B-Thinking inference and optimize non-standard block size (544) support under rocm_atten (#31380)
Signed-off-by: vllmellm <vllm.ellm@embeddedllm.com> | vllm/attention/ops/triton_reshape_and_cache_flash.py | triton | Apache-2.0 | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
import torch
from vllm.platforms import current_platform
from vllm.triton_utils import tl, triton
@triton.jit
def reshape_and_cache_kernel_flash(
key_ptr, # [num_tokens, num_heads, head_size]
value_pt... | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
import torch
from vllm.platforms import current_platform
from vllm.triton_utils import tl, triton
@triton.jit
def reshape_and_cache_kernel_flash(
key_ptr, # [num_tokens, num_heads, head_size]
value_pt... | --- vllm/attention/ops/triton_reshape_and_cache_flash.py
+++ vllm/attention/ops/triton_reshape_and_cache_flash.py
@@ -20,10 +20,15 @@
key_stride: tl.int64,
value_stride: tl.int64,
block_stride: tl.int64,
+ head_stride: tl.int64,
+ dim_stride_k: tl.int64,
+ dim_stride_v: tl.int64,
page_strid... | 52 | 12 | 4 | [
"qwen"
] | [
"ROCM"
] | [] | Optimize this triton kernel file from vllm (vllm/attention/ops/triton_reshape_and_cache_flash.py).
Goal: [Bugfix][ROCm]Fix Qwen3-Next-80B-A3B-Thinking inference and optimize non-standard block size (544) support under rocm_atten
Target hardware: ROCM
Target models: qwen
Current file:
```python
# SPDX-License-Identifi... | ## Purpose
Fixes #26473
This PR refactors the rocm_attn backend kernels to support models with non-power-of-2 block sizes, specifically the Qwen/Qwen3-Next-80B-A3B-Thinking model.
The core of this update is a Dynamic Dispatching Mechanism:Standard Path ($2^n$): For models with power-of-2 block sizes (16, 32, 64, 128... | [] | null | null |
vllm | f347ac6c346f8e84a75ec975618c5aa79c1b9db5 | 2026-01-07T13:31:26-05:00 | 31,837 | https://github.com/vllm-project/vllm/pull/31837 | [Perf] Fuse stride preparation for NVFP4 cutlass_moe (#31837) | [Perf] Fuse stride preparation for NVFP4 cutlass_moe (#31837)
Signed-off-by: mgoin <mgoin64@gmail.com> | csrc/quantization/fp4/nvfp4_blockwise_moe_kernel.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless requi... | /*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless requi... | --- csrc/quantization/fp4/nvfp4_blockwise_moe_kernel.cu
+++ csrc/quantization/fp4/nvfp4_blockwise_moe_kernel.cu
@@ -62,7 +62,9 @@
ElementSF* a_scales_base_as_int, ElementSF* b_scales_base_as_int,
ElementAccumulator* alphas_base_as_int, const int32_t* expert_offsets,
const int32_t* sf_offsets, const int32... | 30 | 18 | 1 | [] | [] | [] | Optimize this cuda kernel file from vllm (csrc/quantization/fp4/nvfp4_blockwise_moe_kernel.cu).
Goal: [Perf] Fuse stride preparation for NVFP4 cutlass_moe
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed un... | ## Purpose
When profiling another PR, I noticed that there were always 3 `vectorized_elementwise_kernel` kernels when calling the `ops.cutlass_fp4_moe_mm` function and found these `torch::full` constructors. The kernel `__get_group_gemm_starts` already runs once per-expert to set up pointers. We can add stride initial... | [{"scope": "e2e", "hardware": null, "model": "nvidia/Qwen3-30B-A3B-NVFP4", "shape": "input-len=100,output-len=100", "batch_size": 8, "metric": "Request throughput", "unit": "req/s", "higher_is_better": true, "baseline": 10.25, "optimized": 10.79, "stated_speedup": null, "speedup": 1.0527}, {"scope": "e2e", "hardware": ... | null | 1.0256 |
vllm | cc6dafaef2bc6b0a3ea0d80efc93985fce6bc8b9 | 2026-01-07T07:53:54-08:00 | 29,213 | https://github.com/vllm-project/vllm/pull/29213 | [Perf][Kernels] Enable FlashInfer DeepGEMM swapAB on SM90 (for W8A8 Linear Op) (#29213) | [Perf][Kernels] Enable FlashInfer DeepGEMM swapAB on SM90 (for W8A8 Linear Op) (#29213)
Signed-off-by: Kate Cheng <yunhsuanc@nvidia.com>
Signed-off-by: Jhao-Ting Chen <jhaotingc@nvidia.com>
Co-authored-by: Jhao-Ting Chen <jhaotingc@nvidia.com> | vllm/model_executor/layers/quantization/utils/fp8_utils.py | triton | Apache-2.0 | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# Adapted from https://github.com/sgl-project/sglang/pull/2575
import functools
import json
import os
from collections.abc import Callable, Sequence
from typing import Any
import torch
import vllm.envs as envs
... | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# Adapted from https://github.com/sgl-project/sglang/pull/2575
import functools
import json
import os
from collections.abc import Callable, Sequence
from typing import Any
import torch
import vllm.envs as envs
... | --- vllm/model_executor/layers/quantization/utils/fp8_utils.py
+++ vllm/model_executor/layers/quantization/utils/fp8_utils.py
@@ -38,6 +38,11 @@
should_use_deepgemm_for_fp8_linear,
transform_sf_into_required_layout,
)
+from vllm.utils.flashinfer import (
+ flashinfer_fp8_blockscale_gemm,
+ is_flashinfe... | 143 | 1 | 1 | [] | [
"SM90"
] | [] | Optimize this triton kernel file from vllm (vllm/model_executor/layers/quantization/utils/fp8_utils.py).
Goal: [Perf][Kernels] Enable FlashInfer DeepGEMM swapAB on SM90 (for W8A8 Linear Op)
Target hardware: SM90
Target models: unspecified
Current file:
```python
# SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyri... | ### **Purpose**
Per https://github.com/vllm-project/vllm/issues/28427, https://github.com/vllm-project/vllm/issues/28316, TRTLLM has `fp8_gemm_kernel_swapAB` kernel for blockscale FP8 gemm in linear layer. This PR https://github.com/vllm-project/vllm/pull/29213 (and FlashInfer PR https://github.com/flashinfer-ai/flash... | [{"scope": "e2e", "hardware": "H200", "model": "DeepSeek-V3.1", "shape": null, "batch_size": 4, "metric": "output token throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 314.7, "optimized": 350.57, "stated_speedup": null, "speedup": 1.114}, {"scope": "e2e", "hardware": "H200", "model": "DeepSeek-V3.1"... | 1.1457 | 1.06 |
vllm | 22dffca9822987f0e912bfd9635e94bbdd05def3 | 2026-01-06T21:32:46+04:00 | 31,722 | https://github.com/vllm-project/vllm/pull/31722 | [PERF] Speed-up of GDN attention decode part (Qwen3-Next) (#31722) | [PERF] Speed-up of GDN attention decode part (Qwen3-Next) (#31722)
Signed-off-by: Vadim Gimpelson <vadim.gimpelson@gmail.com> | vllm/model_executor/layers/fla/ops/fused_recurrent.py | triton | Apache-2.0 | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# SPDX-FileCopyrightText: Songlin Yang, Yu Zhang
#
# This file contains code copied from the flash-linear-attention project.
# The original source code was licensed under the MIT license and included
# the followi... | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# SPDX-FileCopyrightText: Songlin Yang, Yu Zhang
#
# This file contains code copied from the flash-linear-attention project.
# The original source code was licensed under the MIT license and included
# the followi... | --- vllm/model_executor/layers/fla/ops/fused_recurrent.py
+++ vllm/model_executor/layers/fla/ops/fused_recurrent.py
@@ -189,7 +189,7 @@
B, T, H, K, V = *k.shape, v.shape[-1]
HV = v.shape[2]
N = B if cu_seqlens is None else len(cu_seqlens) - 1
- BK, BV = triton.next_power_of_2(K), min(triton.next_power... | 1 | 1 | 1 | [
"qwen"
] | [] | [] | Optimize this triton kernel file from vllm (vllm/model_executor/layers/fla/ops/fused_recurrent.py).
Goal: [PERF] Speed-up of GDN attention decode part (Qwen3-Next)
Target hardware: unspecified
Target models: qwen
Current file:
```python
# SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contrib... | Speed Up GDN Attention (Decode) - `fused_recurrent_gated_delta_rule_fwd`
# Benchmarks
## H200 — `fused_recurrent_gated_delta_rule_fwd` with shapes from Qwen3-Next
### Before
| Batch Size | TP=4 (μs) | TP=2 (μs) |
|-----------:|----------:|----------:|
| 32 | 19.87 ± 0.08 | 30.14 ± 0.02 |
| 128 | 52.06 ± 0.02 | 9... | [{"scope": "kernel", "hardware": "H200", "model": "Qwen3-Next", "shape": "TP=4", "batch_size": 32, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 19.87, "optimized": 13.6, "stated_speedup": null, "speedup": 1.461}, {"scope": "kernel", "hardware": "H200", "model": "Qwen3-Next", "shape": "TP=2"... | 1.5423 | 1.168 |
vllm | 7cd288a4b3f45f3524134b9915c35accd668c2f0 | 2025-12-24T19:17:49+05:30 | 30,800 | https://github.com/vllm-project/vllm/pull/30800 | [PERF] Add interleaved memory allocation to NUMA module (#30800) | [PERF] Add interleaved memory allocation to NUMA module (#30800) | csrc/cpu/utils.cpp | cpp | Apache-2.0 | #ifndef VLLM_NUMA_DISABLED
#include <numa.h>
#include <unistd.h>
#include <string>
#include <sched.h>
#endif
#if __GLIBC__ == 2 && __GLIBC_MINOR__ < 30
#include <unistd.h>
#include <sys/syscall.h>
#define gettid() syscall(SYS_gettid)
#endif
#include "cpu/utils.hpp"
#ifdef VLLM_NUMA_DISABLED
std::string ... | #ifndef VLLM_NUMA_DISABLED
#include <numa.h>
#include <unistd.h>
#include <string>
#include <sched.h>
#endif
#if __GLIBC__ == 2 && __GLIBC_MINOR__ < 30
#include <unistd.h>
#include <sys/syscall.h>
#define gettid() syscall(SYS_gettid)
#endif
#include "cpu/utils.hpp"
#ifdef VLLM_NUMA_DISABLED
std::string ... | --- csrc/cpu/utils.cpp
+++ csrc/cpu/utils.cpp
@@ -24,6 +24,8 @@
#ifndef VLLM_NUMA_DISABLED
std::string init_cpu_threads_env(const std::string& cpu_ids) {
bitmask* omp_cpu_mask = numa_parse_cpustring_all(cpu_ids.c_str());
+ TORCH_CHECK(omp_cpu_mask != nullptr,
+ "Failed to parse CPU string: " + cpu_id... | 38 | 13 | 1 | [] | [
"CPU"
] | [] | Optimize this cpp kernel file from vllm (csrc/cpu/utils.cpp).
Goal: [PERF] Add interleaved memory allocation to NUMA module
Target hardware: CPU
Target models: unspecified
Current file:
```cpp
#ifndef VLLM_NUMA_DISABLED
#include <numa.h>
#include <unistd.h>
#include <string>
#include <sched.h>
#endif
#if __GL... | ## Purpose
This PR adds support for interleaved memory allocation when the system is configured with more than one NUMA node. Enabling interleaved allocation helps distribute memory traffic across nodes more evenly, which is particularly beneficial for memory-bound workloads.
In summary, this PR:
- Introduces NUMA-awar... | [{"scope": "e2e", "hardware": "AMD EPYC", "model": null, "shape": null, "batch_size": 96, "metric": "throughput", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.3, "speedup": 1.3}] | null | 1.3 |
vllm | 06d490282f2bab6922137eb5230be9df5ebbe9c4 | 2025-12-21T12:41:57-05:00 | 30,897 | https://github.com/vllm-project/vllm/pull/30897 | [NVFP4][Perf] Tune NVFP4 input quant kernel for small batch size (#30897) | [NVFP4][Perf] Tune NVFP4 input quant kernel for small batch size (#30897)
Signed-off-by: mgoin <mgoin64@gmail.com> | csrc/quantization/fp4/activation_nvfp4_quant_fusion_kernels.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless requi... | /*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless requi... | --- csrc/quantization/fp4/activation_nvfp4_quant_fusion_kernels.cu
+++ csrc/quantization/fp4/activation_nvfp4_quant_fusion_kernels.cu
@@ -74,6 +74,9 @@
static_assert(sizeof(PackedVec) == sizeof(Type) * CVT_FP4_ELTS_PER_THREAD,
"Vec size is not matched.");
+ // Precompute SF layout parameter (cons... | 4 | 1 | 4 | [] | [] | [] | Optimize this cuda kernel file from vllm (csrc/quantization/fp4/activation_nvfp4_quant_fusion_kernels.cu).
Goal: [NVFP4][Perf] Tune NVFP4 input quant kernel for small batch size
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights rese... | ## Purpose
We discovered that the nvfp4 input quant operation was severely bottlenecking performance for dense models at small batch sizes. While investigating the flashinfer impl, I noticed that there is logic to [increase the grid size for small M](https://github.com/flashinfer-ai/flashinfer/blob/f0592411a3478d0548d... | [{"scope": "e2e", "hardware": null, "model": "Qwen3-8B-NVFP4", "shape": null, "batch_size": 1, "metric": "throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 220, "optimized": 276, "stated_speedup": 1.25, "speedup": 1.2545}, {"scope": "e2e", "hardware": null, "model": "Qwen3-30B-A3B-NVFP4", "shape": nul... | null | 1.1564 |
vllm | 06d490282f2bab6922137eb5230be9df5ebbe9c4 | 2025-12-21T12:41:57-05:00 | 30,897 | https://github.com/vllm-project/vllm/pull/30897 | [NVFP4][Perf] Tune NVFP4 input quant kernel for small batch size (#30897) | [NVFP4][Perf] Tune NVFP4 input quant kernel for small batch size (#30897)
Signed-off-by: mgoin <mgoin64@gmail.com> | csrc/quantization/fp4/nvfp4_experts_quant.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless requi... | /*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless requi... | --- csrc/quantization/fp4/nvfp4_experts_quant.cu
+++ csrc/quantization/fp4/nvfp4_experts_quant.cu
@@ -25,6 +25,7 @@
#include <cuda_fp8.h>
#include "dispatch_utils.h"
+#include "cuda_utils.h"
#include "nvfp4_utils.cuh"
#include "launch_bounds_utils.h"
@@ -43,6 +44,9 @@
(CVT_FP4_SF_VEC_SIZE / CVT_FP4_ELTS_... | 14 | 17 | 4 | [] | [] | [] | Optimize this cuda kernel file from vllm (csrc/quantization/fp4/nvfp4_experts_quant.cu).
Goal: [NVFP4][Perf] Tune NVFP4 input quant kernel for small batch size
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*
* Licens... | ## Purpose
We discovered that the nvfp4 input quant operation was severely bottlenecking performance for dense models at small batch sizes. While investigating the flashinfer impl, I noticed that there is logic to [increase the grid size for small M](https://github.com/flashinfer-ai/flashinfer/blob/f0592411a3478d0548d... | [{"scope": "e2e", "hardware": null, "model": "Qwen3-8B-NVFP4", "shape": null, "batch_size": 1, "metric": "throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 220, "optimized": 276, "stated_speedup": 1.25, "speedup": 1.2545}, {"scope": "e2e", "hardware": null, "model": "Qwen3-30B-A3B-NVFP4", "shape": nul... | null | 1.1564 |
vllm | 06d490282f2bab6922137eb5230be9df5ebbe9c4 | 2025-12-21T12:41:57-05:00 | 30,897 | https://github.com/vllm-project/vllm/pull/30897 | [NVFP4][Perf] Tune NVFP4 input quant kernel for small batch size (#30897) | [NVFP4][Perf] Tune NVFP4 input quant kernel for small batch size (#30897)
Signed-off-by: mgoin <mgoin64@gmail.com> | csrc/quantization/fp4/nvfp4_quant_kernels.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless requi... | /*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless requi... | --- csrc/quantization/fp4/nvfp4_quant_kernels.cu
+++ csrc/quantization/fp4/nvfp4_quant_kernels.cu
@@ -38,6 +38,12 @@
return (x + y - 1) / y * y;
}
+// Compute effective rows for grid configuration with swizzled SF layouts.
+inline int computeEffectiveRows(int m) {
+ constexpr int ROW_TILE = 128;
+ return round_... | 20 | 42 | 4 | [] | [] | [] | Optimize this cuda kernel file from vllm (csrc/quantization/fp4/nvfp4_quant_kernels.cu).
Goal: [NVFP4][Perf] Tune NVFP4 input quant kernel for small batch size
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*
* Licens... | ## Purpose
We discovered that the nvfp4 input quant operation was severely bottlenecking performance for dense models at small batch sizes. While investigating the flashinfer impl, I noticed that there is logic to [increase the grid size for small M](https://github.com/flashinfer-ai/flashinfer/blob/f0592411a3478d0548d... | [{"scope": "e2e", "hardware": null, "model": "Qwen3-8B-NVFP4", "shape": null, "batch_size": 1, "metric": "throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 220, "optimized": 276, "stated_speedup": 1.25, "speedup": 1.2545}, {"scope": "e2e", "hardware": null, "model": "Qwen3-30B-A3B-NVFP4", "shape": nul... | null | 1.1564 |
vllm | 06d490282f2bab6922137eb5230be9df5ebbe9c4 | 2025-12-21T12:41:57-05:00 | 30,897 | https://github.com/vllm-project/vllm/pull/30897 | [NVFP4][Perf] Tune NVFP4 input quant kernel for small batch size (#30897) | [NVFP4][Perf] Tune NVFP4 input quant kernel for small batch size (#30897)
Signed-off-by: mgoin <mgoin64@gmail.com> | csrc/quantization/fp4/nvfp4_utils.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless requi... | /*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless requi... | --- csrc/quantization/fp4/nvfp4_utils.cuh
+++ csrc/quantization/fp4/nvfp4_utils.cuh
@@ -128,51 +128,42 @@
return b;
}
+// Compute SF output offset for swizzled tensor core layout.
+// SF layout: [numMTiles, numKTiles, 32, 4, 4]
+// Caller must precompute: numKTiles = (numCols + 63) / 64
template <class SFType, i... | 29 | 38 | 4 | [] | [] | [] | Optimize this cuda kernel file from vllm (csrc/quantization/fp4/nvfp4_utils.cuh).
Goal: [NVFP4][Perf] Tune NVFP4 input quant kernel for small batch size
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed unde... | ## Purpose
We discovered that the nvfp4 input quant operation was severely bottlenecking performance for dense models at small batch sizes. While investigating the flashinfer impl, I noticed that there is logic to [increase the grid size for small M](https://github.com/flashinfer-ai/flashinfer/blob/f0592411a3478d0548d... | [{"scope": "e2e", "hardware": null, "model": "Qwen3-8B-NVFP4", "shape": null, "batch_size": 1, "metric": "throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 220, "optimized": 276, "stated_speedup": 1.25, "speedup": 1.2545}, {"scope": "e2e", "hardware": null, "model": "Qwen3-30B-A3B-NVFP4", "shape": nul... | null | 1.1564 |
vllm | 0a1ab1e565fce5070bc1c1b1f3374537e437550c | 2025-12-16T17:56:02-05:00 | 29,512 | https://github.com/vllm-project/vllm/pull/29512 | [Perf][Kernels] Vectorize `csrc/activations_kernels.cu` (#29512) | [Perf][Kernels] Vectorize `csrc/activations_kernels.cu` (#29512)
Signed-off-by: mgoin <mgoin64@gmail.com> | csrc/activation_kernels.cu | cuda | Apache-2.0 | #include <ATen/cuda/CUDAContext.h>
#include <torch/all.h>
#include <c10/cuda/CUDAGuard.h>
#include <cmath>
#include "cuda_compat.h"
#include "dispatch_utils.h"
namespace vllm {
template <typename scalar_t, scalar_t (*ACT_FN)(const scalar_t&),
bool act_first>
__device__ __forceinline__ scalar_t compute(con... | #include <ATen/cuda/CUDAContext.h>
#include <torch/all.h>
#include <c10/cuda/CUDAGuard.h>
#include <cmath>
#include "cuda_compat.h"
#include "dispatch_utils.h"
namespace vllm {
template <typename scalar_t, scalar_t (*ACT_FN)(const scalar_t&),
bool act_first>
__device__ __forceinline__ scalar_t compute(con... | --- csrc/activation_kernels.cu
+++ csrc/activation_kernels.cu
@@ -15,19 +15,61 @@
const scalar_t& y) {
return act_first ? ACT_FN(x) * y : x * ACT_FN(y);
}
+
+// Check if all pointers are 16-byte aligned for int4 vectorized access
+__device__ __forceinline__ bool is_16byt... | 176 | 38 | 1 | [] | [] | [] | Optimize this cuda kernel file from vllm (csrc/activation_kernels.cu).
Goal: [Perf][Kernels] Vectorize `csrc/activations_kernels.cu`
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
#include <ATen/cuda/CUDAContext.h>
#include <torch/all.h>
#include <c10/cuda/CUDAGuard.h>
#include <cmath>... | <!-- markdownlint-disable -->
## Purpose
We have been using `silu_and_mul`, `swigluoai_and_mul`, etc as unvectorized kernels for essentially all of the fused moe methods, so there are free gains to be had there, especially for large batch sizes. This PR expands all of them to 128 bit vectorized loads.
## Traces
```... | [] | null | null |
vllm | 6e78ed6ba7f3671f866766f93c6d3571e5bf504d | 2025-12-13T16:12:53-05:00 | 29,903 | https://github.com/vllm-project/vllm/pull/29903 | [Logs] Optimize startup logs 4 (#29903) | [Logs] Optimize startup logs 4 (#29903)
Signed-off-by: yewentao256 <zhyanwentao@126.com>
Signed-off-by: Wentao Ye <44945378+yewentao256@users.noreply.github.com>
Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com> | vllm/model_executor/layers/fused_moe/fused_moe.py | triton | Apache-2.0 | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
"""Fused MoE Triton kernels."""
import functools
import json
import os
from collections.abc import Callable
from typing import Any
import torch
import torch.nn.functional as F
import vllm.envs as envs
import vl... | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
"""Fused MoE Triton kernels."""
import functools
import json
import os
from collections.abc import Callable
from typing import Any
import torch
import torch.nn.functional as F
import vllm.envs as envs
import vl... | --- vllm/model_executor/layers/fused_moe/fused_moe.py
+++ vllm/model_executor/layers/fused_moe/fused_moe.py
@@ -885,12 +885,11 @@
# If no optimized configuration is available, we will use the default
# configuration
- logger.warning(
- (
- "Using default MoE config. Performance might be... | 5 | 6 | 2 | [] | [] | [] | Optimize this triton kernel file from vllm (vllm/model_executor/layers/fused_moe/fused_moe.py).
Goal: [Logs] Optimize startup logs 4
Target hardware: unspecified
Target models: unspecified
Current file:
```python
# SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM projec... | ## Purpose
Example:
```bash
(Worker_TP5_EP5 pid=626382) INFO 12-02 09:01:00 [backends.py:216] Directly load the compiled graph(s) for dynamic shape from the cache, took 7.017 s
(Worker_TP2_EP2 pid=626379) INFO 12-02 09:01:01 [backends.py:216] Directly load the compiled graph(s) for dynamic shape from the cache, took... | [] | null | null |
vllm | c817b1415121cf88178af1e4e78f651d802df4da | 2025-12-11T17:28:34-05:00 | 30,494 | https://github.com/vllm-project/vllm/pull/30494 | [Perf] Optimize deepgemm experts initialization, 3.9% TTFT improvement (#30494) | [Perf] Optimize deepgemm experts initialization, 3.9% TTFT improvement (#30494)
Signed-off-by: yewentao256 <zhyanwentao@126.com>
Co-authored-by: li-jinpeng <3332126450@qq.com>
Co-authored-by: youkaichao <youkaichao@gmail.com> | vllm/model_executor/layers/fused_moe/deep_gemm_utils.py | triton | Apache-2.0 | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
"""
Taken from https://github.com/ModelTC/LightLLM/blob/8ed97c74c18f11505b048b1ba00ba5c0cef8bff6/lightllm/common/fused_moe/deepep_scatter_gather.py
and updated to fit vllm needs and terminology.
"""
import torch
... | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
"""
Taken from https://github.com/ModelTC/LightLLM/blob/8ed97c74c18f11505b048b1ba00ba5c0cef8bff6/lightllm/common/fused_moe/deepep_scatter_gather.py
and updated to fit vllm needs and terminology.
"""
import torch
... | --- vllm/model_executor/layers/fused_moe/deep_gemm_utils.py
+++ vllm/model_executor/layers/fused_moe/deep_gemm_utils.py
@@ -84,10 +84,16 @@
m_indices_start_ptr = m_indices + cur_expert_start
off_expert = tl.arange(0, BLOCK_E)
+ # any rows in the per-expert aligned region that do not correspond to
+ # ... | 18 | 7 | 1 | [] | [] | [] | Optimize this triton kernel file from vllm (vllm/model_executor/layers/fused_moe/deep_gemm_utils.py).
Goal: [Perf] Optimize deepgemm experts initialization, 3.9% TTFT improvement
Target hardware: unspecified
Target models: unspecified
Current file:
```python
# SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightT... | ## Purpose
Thanks for the context from @youkaichao !
Co-author: @li-jinpeng
DeepGEMM uses negative values in m_indices (here expert_ids) to mark completely invalid / padded blocks that should be skipped. We always initialize expert_ids to -1 so any row that is not explicitly written by the scatter kernel will be tr... | [] | null | null |
vllm | 0ee6416f678de761f827f4bd387b36f0cbc43a0a | 2025-12-08T19:44:01-05:00 | 30,159 | https://github.com/vllm-project/vllm/pull/30159 | [Perf] Optimize `group_topk` kernel, 1.9% Throughput improvement, 2.1% TPOT improvemnt (#30159) | [Perf] Optimize `group_topk` kernel, 1.9% Throughput improvement, 2.1% TPOT improvemnt (#30159)
Signed-off-by: yewentao256 <zhyanwentao@126.com> | csrc/moe/grouped_topk_kernels.cu | cuda | Apache-2.0 | /*
* Adapted from
* https://github.com/NVIDIA/TensorRT-LLM/blob/v0.21.0/cpp/tensorrt_llm/kernels/noAuxTcKernels.cu
* Copyright (c) 2025, The vLLM team.
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION &
* AFFILIATES. All rights reserved. SPDX-License-Identifier: Apache-2.0
*
* Licensed under ... | /*
* Adapted from
* https://github.com/NVIDIA/TensorRT-LLM/blob/v0.21.0/cpp/tensorrt_llm/kernels/noAuxTcKernels.cu
* Copyright (c) 2025, The vLLM team.
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION &
* AFFILIATES. All rights reserved. SPDX-License-Identifier: Apache-2.0
*
* Licensed under ... | --- csrc/moe/grouped_topk_kernels.cu
+++ csrc/moe/grouped_topk_kernels.cu
@@ -444,23 +444,27 @@
return cuda_cast<T, float>(sigmoid_accurate(f));
}
-template <typename T>
+template <ScoringFunc SF, typename T>
+__device__ inline T apply_scoring(T val) {
+ if constexpr (SF == SCORING_SIGMOID) {
+ return apply_s... | 128 | 47 | 1 | [] | [] | [] | Optimize this cuda kernel file from vllm (csrc/moe/grouped_topk_kernels.cu).
Goal: [Perf] Optimize `group_topk` kernel, 1.9% Throughput improvement, 2.1% TPOT improvemnt
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Adapted from
* https://github.com/NVIDIA/TensorRT-LLM/blob/v0.2... | ## Purpose
We are trying to optimize the GLMv4.6 model, this kernel takes a lot of time and we try to reduce this first.
This optimization could be also used for other models like V3.2 etc.
Optimize the kernel, mainly:
1. Use template for the scoring function
2. unroll some usual ngroup
## Test
`export MODEL="zai-... | [] | null | null |
vllm | af0444bf40b7db2f3fb9fe1508d25ceba24cac87 | 2025-12-07T17:38:04+01:00 | 27,883 | https://github.com/vllm-project/vllm/pull/27883 | [Performance] Fused blockwise quant RMS norm (#27883) | [Performance] Fused blockwise quant RMS norm (#27883)
Signed-off-by: ElizaWszola <ewszola@redhat.com>
Signed-off-by: yewentao256 <zhyanwentao@126.com>
Co-authored-by: yewentao256 <zhyanwentao@126.com> | csrc/dispatch_utils.h | cpp | Apache-2.0 | /*
* Adapted from
* https://github.com/pytorch/pytorch/blob/v2.0.1/aten/src/ATen/Dispatch.h
*/
#pragma once
#include <torch/all.h>
// Need a special dispatch case macro since we will nest the FP8 dispatch.
// Instead of the usual 'scalar_t', this names the dispatched type 'fp8_t'.
#define AT_DISPATCH_FP8_CASE(enum... | /*
* Adapted from
* https://github.com/pytorch/pytorch/blob/v2.0.1/aten/src/ATen/Dispatch.h
*/
#pragma once
#include <torch/all.h>
// Need a special dispatch case macro since we will nest the FP8 dispatch.
// Instead of the usual 'scalar_t', this names the dispatched type 'fp8_t'.
#define AT_DISPATCH_FP8_CASE(enum... | --- csrc/dispatch_utils.h
+++ csrc/dispatch_utils.h
@@ -118,6 +118,24 @@
} \
}
+#define VLLM_DISPATCH_BOOL(expr, const_expr, ...) \
+ if (expr) { \
+ constexpr bool const_expr = true; \
+ __VA_ARGS__(); ... | 18 | 0 | 7 | [] | [] | [] | Optimize this cpp kernel file from vllm (csrc/dispatch_utils.h).
Goal: [Performance] Fused blockwise quant RMS norm
Target hardware: unspecified
Target models: unspecified
Current file:
```cpp
/*
* Adapted from
* https://github.com/pytorch/pytorch/blob/v2.0.1/aten/src/ATen/Dispatch.h
*/
#pragma once
#include <tor... | CUDA kernel and fusion code for Fused Groupwise FP8-Quantized RMS Norm. This code allows to fuse RMS Norm + FP8 Quantization of the RMS Norm's output when `enable_fusion==True`.
### Testing:
#### Test fused op
```pytest tests/kernels/core/test_fused_quant_layernorm.py```
#### Test fusion
```pytest tests/compile/test... | [{"scope": "kernel", "hardware": "H100", "model": null, "shape": "N=1,D=1024,R=True,DT=torch.bfloat16,GS=[1,64]", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 36.2, "optimized": 24.7, "stated_speedup": null, "speedup": 1.4656}, {"scope": "kernel", "hardware": "H100", "model... | 1.4685 | 1.0064 |
vllm | af0444bf40b7db2f3fb9fe1508d25ceba24cac87 | 2025-12-07T17:38:04+01:00 | 27,883 | https://github.com/vllm-project/vllm/pull/27883 | [Performance] Fused blockwise quant RMS norm (#27883) | [Performance] Fused blockwise quant RMS norm (#27883)
Signed-off-by: ElizaWszola <ewszola@redhat.com>
Signed-off-by: yewentao256 <zhyanwentao@126.com>
Co-authored-by: yewentao256 <zhyanwentao@126.com> | csrc/ops.h | cpp | Apache-2.0 | #pragma once
#include <optional>
#include <torch/library.h>
#include "core/scalar_type.hpp"
#include <vector>
torch::Tensor weak_ref_tensor(torch::Tensor& tensor) {
// Ensure tensor is on CUDA
if (!tensor.is_cuda()) {
throw std::runtime_error("Tensor must be on CUDA device");
}
// Get the raw data poin... | #pragma once
#include <optional>
#include <torch/library.h>
#include "core/scalar_type.hpp"
#include <vector>
torch::Tensor weak_ref_tensor(torch::Tensor& tensor) {
// Ensure tensor is on CUDA
if (!tensor.is_cuda()) {
throw std::runtime_error("Tensor must be on CUDA device");
}
// Get the raw data poin... | --- csrc/ops.h
+++ csrc/ops.h
@@ -128,6 +128,13 @@
std::optional<torch::Tensor> scale_ub,
std::optional<torch::Tensor> residual);
+void rms_norm_per_block_quant(torch::Tensor& out, torch::Tensor const& input,
+ ... | 7 | 0 | 7 | [] | [] | [] | Optimize this cpp kernel file from vllm (csrc/ops.h).
Goal: [Performance] Fused blockwise quant RMS norm
Target hardware: unspecified
Target models: unspecified
Current file:
```cpp
#pragma once
#include <optional>
#include <torch/library.h>
#include "core/scalar_type.hpp"
#include <vector>
torch::Tensor weak_ref... | CUDA kernel and fusion code for Fused Groupwise FP8-Quantized RMS Norm. This code allows to fuse RMS Norm + FP8 Quantization of the RMS Norm's output when `enable_fusion==True`.
### Testing:
#### Test fused op
```pytest tests/kernels/core/test_fused_quant_layernorm.py```
#### Test fusion
```pytest tests/compile/test... | [{"scope": "kernel", "hardware": "H100", "model": null, "shape": "N=1,D=1024,R=True,DT=torch.bfloat16,GS=[1,64]", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 36.2, "optimized": 24.7, "stated_speedup": null, "speedup": 1.4656}, {"scope": "kernel", "hardware": "H100", "model... | 1.4685 | 1.0064 |
vllm | af0444bf40b7db2f3fb9fe1508d25ceba24cac87 | 2025-12-07T17:38:04+01:00 | 27,883 | https://github.com/vllm-project/vllm/pull/27883 | [Performance] Fused blockwise quant RMS norm (#27883) | [Performance] Fused blockwise quant RMS norm (#27883)
Signed-off-by: ElizaWszola <ewszola@redhat.com>
Signed-off-by: yewentao256 <zhyanwentao@126.com>
Co-authored-by: yewentao256 <zhyanwentao@126.com> | csrc/quantization/fused_kernels/fused_layernorm_dynamic_per_token_quant.cu | cuda | Apache-2.0 |
#include <ATen/cuda/CUDAContext.h>
#include <c10/cuda/CUDAGuard.h>
#include "../../dispatch_utils.h"
#include "layernorm_utils.cuh"
#include "quant_conversions.cuh"
namespace vllm {
template <typename scalar_t, typename scalar_out_t, bool has_residual = false>
__device__ void rms_norm_dynamic_per_token_quant_vec(
... |
#include <ATen/cuda/CUDAContext.h>
#include <c10/cuda/CUDAGuard.h>
#include "../../dispatch_utils.h"
#include "layernorm_utils.cuh"
#include "quant_conversions.cuh"
namespace vllm {
template <typename scalar_t, typename scalar_out_t, bool has_residual = false>
__device__ void rms_norm_dynamic_per_token_quant_vec(
... | --- csrc/quantization/fused_kernels/fused_layernorm_dynamic_per_token_quant.cu
+++ csrc/quantization/fused_kernels/fused_layernorm_dynamic_per_token_quant.cu
@@ -31,14 +31,15 @@
// RMS Norm + Quant
if constexpr (std::is_same_v<scalar_out_t, int8_t>) {
+ token_scale = 1.0f / token_scale;
vllm::vectorized... | 126 | 22 | 7 | [] | [] | [] | Optimize this cuda kernel file from vllm (csrc/quantization/fused_kernels/fused_layernorm_dynamic_per_token_quant.cu).
Goal: [Performance] Fused blockwise quant RMS norm
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
#include <ATen/cuda/CUDAContext.h>
#include <c10/cuda/CUDAGuard.h>
#... | CUDA kernel and fusion code for Fused Groupwise FP8-Quantized RMS Norm. This code allows to fuse RMS Norm + FP8 Quantization of the RMS Norm's output when `enable_fusion==True`.
### Testing:
#### Test fused op
```pytest tests/kernels/core/test_fused_quant_layernorm.py```
#### Test fusion
```pytest tests/compile/test... | [{"scope": "kernel", "hardware": "H100", "model": null, "shape": "N=1,D=1024,R=True,DT=torch.bfloat16,GS=[1,64]", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 36.2, "optimized": 24.7, "stated_speedup": null, "speedup": 1.4656}, {"scope": "kernel", "hardware": "H100", "model... | 1.4685 | 1.0064 |
vllm | af0444bf40b7db2f3fb9fe1508d25ceba24cac87 | 2025-12-07T17:38:04+01:00 | 27,883 | https://github.com/vllm-project/vllm/pull/27883 | [Performance] Fused blockwise quant RMS norm (#27883) | [Performance] Fused blockwise quant RMS norm (#27883)
Signed-off-by: ElizaWszola <ewszola@redhat.com>
Signed-off-by: yewentao256 <zhyanwentao@126.com>
Co-authored-by: yewentao256 <zhyanwentao@126.com> | csrc/quantization/fused_kernels/layernorm_utils.cuh | cuda | Apache-2.0 | #pragma once
/**
* __device__ layernorm utilities.
*/
#include "quantization/vectorization.cuh"
#include "quantization/utils.cuh"
#include "quant_conversions.cuh"
#include "../../cub_helpers.h"
namespace vllm {
// has_residual must be true, if residual is not a nullptr
template <typename scalar_t, bool has_resid... | #pragma once
/**
* __device__ layernorm utilities.
*/
#include "quantization/vectorization.cuh"
#include "quantization/utils.cuh"
#include "quant_conversions.cuh"
#include "../../cub_helpers.h"
#include "../../cuda_compat.h"
namespace vllm {
// has_residual must be true, if residual is not a nullptr
template <ty... | --- csrc/quantization/fused_kernels/layernorm_utils.cuh
+++ csrc/quantization/fused_kernels/layernorm_utils.cuh
@@ -9,6 +9,7 @@
#include "quant_conversions.cuh"
#include "../../cub_helpers.h"
+#include "../../cuda_compat.h"
namespace vllm {
@@ -43,62 +44,150 @@
*rms = s_rms;
}
-template <typename scalar_... | 325 | 111 | 7 | [] | [] | [] | Optimize this cuda kernel file from vllm (csrc/quantization/fused_kernels/layernorm_utils.cuh).
Goal: [Performance] Fused blockwise quant RMS norm
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
#pragma once
/**
* __device__ layernorm utilities.
*/
#include "quantization/vectorizatio... | CUDA kernel and fusion code for Fused Groupwise FP8-Quantized RMS Norm. This code allows to fuse RMS Norm + FP8 Quantization of the RMS Norm's output when `enable_fusion==True`.
### Testing:
#### Test fused op
```pytest tests/kernels/core/test_fused_quant_layernorm.py```
#### Test fusion
```pytest tests/compile/test... | [{"scope": "kernel", "hardware": "H100", "model": null, "shape": "N=1,D=1024,R=True,DT=torch.bfloat16,GS=[1,64]", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 36.2, "optimized": 24.7, "stated_speedup": null, "speedup": 1.4656}, {"scope": "kernel", "hardware": "H100", "model... | 1.4685 | 1.0064 |
vllm | af0444bf40b7db2f3fb9fe1508d25ceba24cac87 | 2025-12-07T17:38:04+01:00 | 27,883 | https://github.com/vllm-project/vllm/pull/27883 | [Performance] Fused blockwise quant RMS norm (#27883) | [Performance] Fused blockwise quant RMS norm (#27883)
Signed-off-by: ElizaWszola <ewszola@redhat.com>
Signed-off-by: yewentao256 <zhyanwentao@126.com>
Co-authored-by: yewentao256 <zhyanwentao@126.com> | csrc/torch_bindings.cpp | cpp | Apache-2.0 | #include "cache.h"
#include "cuda_utils.h"
#include "ops.h"
#include "core/registration.h"
#include <torch/library.h>
#include <torch/version.h>
// Note on op signatures:
// The X_meta signatures are for the meta functions corresponding to op X.
// They must be kept in sync with the signature for X. Generally, only
/... | #include "cache.h"
#include "cuda_utils.h"
#include "ops.h"
#include "core/registration.h"
#include <torch/library.h>
#include <torch/version.h>
// Note on op signatures:
// The X_meta signatures are for the meta functions corresponding to op X.
// They must be kept in sync with the signature for X. Generally, only
/... | --- csrc/torch_bindings.cpp
+++ csrc/torch_bindings.cpp
@@ -214,6 +214,14 @@
"Tensor? scale_ub, Tensor!? residual) -> ()");
ops.impl("rms_norm_dynamic_per_token_quant", torch::kCUDA,
&rms_norm_dynamic_per_token_quant);
+
+ // Fused Layernorm + Block quant kernels
+ ops.def(
+ "rms_norm_per_... | 8 | 0 | 7 | [] | [] | [] | Optimize this cpp kernel file from vllm (csrc/torch_bindings.cpp).
Goal: [Performance] Fused blockwise quant RMS norm
Target hardware: unspecified
Target models: unspecified
Current file:
```cpp
#include "cache.h"
#include "cuda_utils.h"
#include "ops.h"
#include "core/registration.h"
#include <torch/library.h>
#inc... | CUDA kernel and fusion code for Fused Groupwise FP8-Quantized RMS Norm. This code allows to fuse RMS Norm + FP8 Quantization of the RMS Norm's output when `enable_fusion==True`.
### Testing:
#### Test fused op
```pytest tests/kernels/core/test_fused_quant_layernorm.py```
#### Test fusion
```pytest tests/compile/test... | [{"scope": "kernel", "hardware": "H100", "model": null, "shape": "N=1,D=1024,R=True,DT=torch.bfloat16,GS=[1,64]", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 36.2, "optimized": 24.7, "stated_speedup": null, "speedup": 1.4656}, {"scope": "kernel", "hardware": "H100", "model... | 1.4685 | 1.0064 |
vllm | af0444bf40b7db2f3fb9fe1508d25ceba24cac87 | 2025-12-07T17:38:04+01:00 | 27,883 | https://github.com/vllm-project/vllm/pull/27883 | [Performance] Fused blockwise quant RMS norm (#27883) | [Performance] Fused blockwise quant RMS norm (#27883)
Signed-off-by: ElizaWszola <ewszola@redhat.com>
Signed-off-by: yewentao256 <zhyanwentao@126.com>
Co-authored-by: yewentao256 <zhyanwentao@126.com> | vllm/model_executor/layers/quantization/utils/fp8_utils.py | triton | Apache-2.0 | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# Adapted from https://github.com/sgl-project/sglang/pull/2575
import functools
import json
import os
from collections.abc import Callable, Sequence
from typing import Any
import torch
import vllm.envs as envs
... | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# Adapted from https://github.com/sgl-project/sglang/pull/2575
import functools
import json
import os
from collections.abc import Callable, Sequence
from typing import Any
import torch
import vllm.envs as envs
... | --- vllm/model_executor/layers/quantization/utils/fp8_utils.py
+++ vllm/model_executor/layers/quantization/utils/fp8_utils.py
@@ -733,7 +733,7 @@
assert out_q is None or out_q.shape == x.shape
x_q = out_q
if x_q is None:
- x_q = torch.empty_like(x, device=x.device, dtype=dtype)
+ x_q = torc... | 1 | 1 | 7 | [] | [] | [] | Optimize this triton kernel file from vllm (vllm/model_executor/layers/quantization/utils/fp8_utils.py).
Goal: [Performance] Fused blockwise quant RMS norm
Target hardware: unspecified
Target models: unspecified
Current file:
```python
# SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contribu... | CUDA kernel and fusion code for Fused Groupwise FP8-Quantized RMS Norm. This code allows to fuse RMS Norm + FP8 Quantization of the RMS Norm's output when `enable_fusion==True`.
### Testing:
#### Test fused op
```pytest tests/kernels/core/test_fused_quant_layernorm.py```
#### Test fusion
```pytest tests/compile/test... | [{"scope": "kernel", "hardware": "H100", "model": null, "shape": "N=1,D=1024,R=True,DT=torch.bfloat16,GS=[1,64]", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 36.2, "optimized": 24.7, "stated_speedup": null, "speedup": 1.4656}, {"scope": "kernel", "hardware": "H100", "model... | 1.4685 | 1.0064 |
vllm | 541a2ef892720489f770569417bc1bc4436dbb21 | 2025-12-07T07:31:14-05:00 | 29,546 | https://github.com/vllm-project/vllm/pull/29546 | [Perf] Deepgemm fused layout kernel for activations, 4.3% throughput improvement, 10.7% TTFT improvement. (#29546) | [Perf] Deepgemm fused layout kernel for activations, 4.3% throughput improvement, 10.7% TTFT improvement. (#29546)
Signed-off-by: yewentao256 <zhyanwentao@126.com> | csrc/ops.h | cpp | Apache-2.0 | #pragma once
#include <optional>
#include <torch/library.h>
#include "core/scalar_type.hpp"
#include <vector>
torch::Tensor weak_ref_tensor(torch::Tensor& tensor) {
// Ensure tensor is on CUDA
if (!tensor.is_cuda()) {
throw std::runtime_error("Tensor must be on CUDA device");
}
// Get the raw data poin... | #pragma once
#include <optional>
#include <torch/library.h>
#include "core/scalar_type.hpp"
#include <vector>
torch::Tensor weak_ref_tensor(torch::Tensor& tensor) {
// Ensure tensor is on CUDA
if (!tensor.is_cuda()) {
throw std::runtime_error("Tensor must be on CUDA device");
}
// Get the raw data poin... | --- csrc/ops.h
+++ csrc/ops.h
@@ -299,6 +299,14 @@
torch::Tensor& output_q,
torch::Tensor& output_s, int64_t group_size,
double eps, double int8_min, double int8_max);
+
+// Fused activation quantisation + DeepGEMM-compat... | 8 | 0 | 5 | [] | [] | [] | Optimize this cpp kernel file from vllm (csrc/ops.h).
Goal: [Perf] Deepgemm fused layout kernel for activations, 4.3% throughput improvement, 10.7% TTFT improvement.
Target hardware: unspecified
Target models: unspecified
Current file:
```cpp
#pragma once
#include <optional>
#include <torch/library.h>
#include "cor... | ## Purpose
Fused layout transform with per token group quant to get performance
Namely, pack scales into a uint32 earlier and remove an additional kernel call
## Test
`vllm serve deepseek-ai/DeepSeek-V3.1 -tp 8 --enable-expert-parallel --port 9256 --enforce_eager`
### Acc
`lm_eval --model local-completions --mod... | [] | null | null |
vllm | 541a2ef892720489f770569417bc1bc4436dbb21 | 2025-12-07T07:31:14-05:00 | 29,546 | https://github.com/vllm-project/vllm/pull/29546 | [Perf] Deepgemm fused layout kernel for activations, 4.3% throughput improvement, 10.7% TTFT improvement. (#29546) | [Perf] Deepgemm fused layout kernel for activations, 4.3% throughput improvement, 10.7% TTFT improvement. (#29546)
Signed-off-by: yewentao256 <zhyanwentao@126.com> | csrc/quantization/w8a8/fp8/per_token_group_quant.cu | cuda | Apache-2.0 | #include <ATen/cuda/CUDAContext.h>
#include "quantization/w8a8/per_token_group_quant_8bit.h"
#include <cmath>
#include <cuda_fp8.h>
#include <torch/all.h>
#include "quantization/vectorization.cuh"
#include "quantization/vectorization_utils.cuh"
#include "dispatch_utils.h"
__device__ __forceinline__ float GroupRed... | #include <ATen/cuda/CUDAContext.h>
#include "quantization/w8a8/per_token_group_quant_8bit.h"
#include <cmath>
#include <cuda_fp8.h>
#include <torch/all.h>
#include "quantization/vectorization.cuh"
#include "quantization/vectorization_utils.cuh"
#include "dispatch_utils.h"
__device__ __forceinline__ float GroupRed... | --- csrc/quantization/w8a8/fp8/per_token_group_quant.cu
+++ csrc/quantization/w8a8/fp8/per_token_group_quant.cu
@@ -206,6 +206,191 @@
#undef LAUNCH_KERNEL
}
+template <typename T, typename DST_DTYPE>
+__global__ void per_token_group_quant_8bit_packed_kernel(
+ const T* __restrict__ input, void* __restrict__ outp... | 185 | 0 | 5 | [] | [] | [] | Optimize this cuda kernel file from vllm (csrc/quantization/w8a8/fp8/per_token_group_quant.cu).
Goal: [Perf] Deepgemm fused layout kernel for activations, 4.3% throughput improvement, 10.7% TTFT improvement.
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
#include <ATen/cuda/CUDAContext.... | ## Purpose
Fused layout transform with per token group quant to get performance
Namely, pack scales into a uint32 earlier and remove an additional kernel call
## Test
`vllm serve deepseek-ai/DeepSeek-V3.1 -tp 8 --enable-expert-parallel --port 9256 --enforce_eager`
### Acc
`lm_eval --model local-completions --mod... | [] | null | null |
vllm | 541a2ef892720489f770569417bc1bc4436dbb21 | 2025-12-07T07:31:14-05:00 | 29,546 | https://github.com/vllm-project/vllm/pull/29546 | [Perf] Deepgemm fused layout kernel for activations, 4.3% throughput improvement, 10.7% TTFT improvement. (#29546) | [Perf] Deepgemm fused layout kernel for activations, 4.3% throughput improvement, 10.7% TTFT improvement. (#29546)
Signed-off-by: yewentao256 <zhyanwentao@126.com> | csrc/torch_bindings.cpp | cpp | Apache-2.0 | #include "cache.h"
#include "cuda_utils.h"
#include "ops.h"
#include "core/registration.h"
#include <torch/library.h>
#include <torch/version.h>
// Note on op signatures:
// The X_meta signatures are for the meta functions corresponding to op X.
// They must be kept in sync with the signature for X. Generally, only
/... | #include "cache.h"
#include "cuda_utils.h"
#include "ops.h"
#include "core/registration.h"
#include <torch/library.h>
#include <torch/version.h>
// Note on op signatures:
// The X_meta signatures are for the meta functions corresponding to op X.
// They must be kept in sync with the signature for X. Generally, only
/... | --- csrc/torch_bindings.cpp
+++ csrc/torch_bindings.cpp
@@ -617,6 +617,15 @@
ops.impl("per_token_group_fp8_quant", torch::kCUDA,
&per_token_group_quant_fp8);
+ // Compute per-token-group 8-bit quantized tensor and UE8M0-packed,
+ // TMA-aligned scales for DeepGEMM.
+ ops.def(
+ "per_token_group... | 9 | 0 | 5 | [] | [] | [] | Optimize this cpp kernel file from vllm (csrc/torch_bindings.cpp).
Goal: [Perf] Deepgemm fused layout kernel for activations, 4.3% throughput improvement, 10.7% TTFT improvement.
Target hardware: unspecified
Target models: unspecified
Current file:
```cpp
#include "cache.h"
#include "cuda_utils.h"
#include "ops.h"
#i... | ## Purpose
Fused layout transform with per token group quant to get performance
Namely, pack scales into a uint32 earlier and remove an additional kernel call
## Test
`vllm serve deepseek-ai/DeepSeek-V3.1 -tp 8 --enable-expert-parallel --port 9256 --enforce_eager`
### Acc
`lm_eval --model local-completions --mod... | [] | null | null |
vllm | 541a2ef892720489f770569417bc1bc4436dbb21 | 2025-12-07T07:31:14-05:00 | 29,546 | https://github.com/vllm-project/vllm/pull/29546 | [Perf] Deepgemm fused layout kernel for activations, 4.3% throughput improvement, 10.7% TTFT improvement. (#29546) | [Perf] Deepgemm fused layout kernel for activations, 4.3% throughput improvement, 10.7% TTFT improvement. (#29546)
Signed-off-by: yewentao256 <zhyanwentao@126.com> | vllm/model_executor/layers/quantization/utils/fp8_utils.py | triton | Apache-2.0 | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# Adapted from https://github.com/sgl-project/sglang/pull/2575
import functools
import json
import os
from collections.abc import Callable, Sequence
from typing import Any
import torch
import vllm.envs as envs
... | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# Adapted from https://github.com/sgl-project/sglang/pull/2575
import functools
import json
import os
from collections.abc import Callable, Sequence
from typing import Any
import torch
import vllm.envs as envs
... | --- vllm/model_executor/layers/quantization/utils/fp8_utils.py
+++ vllm/model_executor/layers/quantization/utils/fp8_utils.py
@@ -269,7 +269,11 @@
weight_scale: torch.Tensor,
) -> torch.Tensor:
assert self.deepgemm_input_quant_op is not None
- q_input, input_scale = self.deepgemm_input_qua... | 79 | 1 | 5 | [] | [] | [] | Optimize this triton kernel file from vllm (vllm/model_executor/layers/quantization/utils/fp8_utils.py).
Goal: [Perf] Deepgemm fused layout kernel for activations, 4.3% throughput improvement, 10.7% TTFT improvement.
Target hardware: unspecified
Target models: unspecified
Current file:
```python
# SPDX-License-Identi... | ## Purpose
Fused layout transform with per token group quant to get performance
Namely, pack scales into a uint32 earlier and remove an additional kernel call
## Test
`vllm serve deepseek-ai/DeepSeek-V3.1 -tp 8 --enable-expert-parallel --port 9256 --enforce_eager`
### Acc
`lm_eval --model local-completions --mod... | [] | null | null |
vllm | 879ddb09c3b7b5a21f75e46ded148ce70f1c486e | 2025-12-07T17:58:47+08:00 | 29,642 | https://github.com/vllm-project/vllm/pull/29642 | [Kernel][MoE] optimize `moe_align_block_size` (#29642) | [Kernel][MoE] optimize `moe_align_block_size` (#29642)
Signed-off-by: Jinzhen Lin <jinzhen.ljz@antgroup.com>
Co-authored-by: Jee Jee Li <pandaleefree@gmail.com> | csrc/moe/moe_align_sum_kernels.cu | cuda | Apache-2.0 | #include <torch/all.h>
#include <ATen/cuda/CUDAContext.h>
#include <c10/cuda/CUDAGuard.h>
#include <cub/cub.cuh>
#include <ATen/ATen.h>
#include <ATen/cuda/Atomic.cuh>
#include "../cuda_compat.h"
#include "../dispatch_utils.h"
#include "core/math.hpp"
#define CEILDIV(x, y) (((x) + (y) - 1) / (y))
namespace vllm {
n... | #include <torch/all.h>
#include <ATen/cuda/CUDAContext.h>
#include <c10/cuda/CUDAGuard.h>
#include <cub/cub.cuh>
#include <ATen/ATen.h>
#include <ATen/cuda/Atomic.cuh>
#include "../cuda_compat.h"
#include "../dispatch_utils.h"
#include "core/math.hpp"
#define CEILDIV(x, y) (((x) + (y) - 1) / (y))
namespace vllm {
n... | --- csrc/moe/moe_align_sum_kernels.cu
+++ csrc/moe/moe_align_sum_kernels.cu
@@ -83,14 +83,22 @@
__global__ void moe_align_block_size_kernel(
const scalar_t* __restrict__ topk_ids,
int32_t* __restrict__ sorted_token_ids, int32_t* __restrict__ expert_ids,
- int32_t* __restrict__ total_tokens_post_pad, int32... | 117 | 57 | 6 | [] | [] | [] | Optimize this cuda kernel file from vllm (csrc/moe/moe_align_sum_kernels.cu).
Goal: [Kernel][MoE] optimize `moe_align_block_size`
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
#include <torch/all.h>
#include <ATen/cuda/CUDAContext.h>
#include <c10/cuda/CUDAGuard.h>
#include <cub/cub.cu... | ## Introduction
This PR optimize `moe_align_block_size` from three aspects:
1. For a small batch size, use the smallest possible value for `max_num_tokens_padded`.
2. In the CUDA Kernel, use additional thread or threadblock resources to fill `sorted_token_ids`. The previous CUDA Kernel used very few computational res... | [] | null | null |
vllm | 879ddb09c3b7b5a21f75e46ded148ce70f1c486e | 2025-12-07T17:58:47+08:00 | 29,642 | https://github.com/vllm-project/vllm/pull/29642 | [Kernel][MoE] optimize `moe_align_block_size` (#29642) | [Kernel][MoE] optimize `moe_align_block_size` (#29642)
Signed-off-by: Jinzhen Lin <jinzhen.ljz@antgroup.com>
Co-authored-by: Jee Jee Li <pandaleefree@gmail.com> | csrc/moe/moe_ops.h | cpp | Apache-2.0 | #pragma once
#include <torch/all.h>
void topk_softmax(torch::Tensor& topk_weights, torch::Tensor& topk_indices,
torch::Tensor& token_expert_indices,
torch::Tensor& gating_output, bool renormalize);
void moe_sum(torch::Tensor& input, torch::Tensor& output);
void moe_align_block_si... | #pragma once
#include <torch/all.h>
void topk_softmax(torch::Tensor& topk_weights, torch::Tensor& topk_indices,
torch::Tensor& token_expert_indices,
torch::Tensor& gating_output, bool renormalize);
void moe_sum(torch::Tensor& input, torch::Tensor& output);
void moe_align_block_si... | --- csrc/moe/moe_ops.h
+++ csrc/moe/moe_ops.h
@@ -11,7 +11,8 @@
void moe_align_block_size(torch::Tensor topk_ids, int64_t num_experts,
int64_t block_size, torch::Tensor sorted_token_ids,
torch::Tensor experts_ids,
- torch::Tensor num_tokens... | 2 | 1 | 6 | [] | [] | [] | Optimize this cpp kernel file from vllm (csrc/moe/moe_ops.h).
Goal: [Kernel][MoE] optimize `moe_align_block_size`
Target hardware: unspecified
Target models: unspecified
Current file:
```cpp
#pragma once
#include <torch/all.h>
void topk_softmax(torch::Tensor& topk_weights, torch::Tensor& topk_indices,
... | ## Introduction
This PR optimize `moe_align_block_size` from three aspects:
1. For a small batch size, use the smallest possible value for `max_num_tokens_padded`.
2. In the CUDA Kernel, use additional thread or threadblock resources to fill `sorted_token_ids`. The previous CUDA Kernel used very few computational res... | [] | null | null |
vllm | 879ddb09c3b7b5a21f75e46ded148ce70f1c486e | 2025-12-07T17:58:47+08:00 | 29,642 | https://github.com/vllm-project/vllm/pull/29642 | [Kernel][MoE] optimize `moe_align_block_size` (#29642) | [Kernel][MoE] optimize `moe_align_block_size` (#29642)
Signed-off-by: Jinzhen Lin <jinzhen.ljz@antgroup.com>
Co-authored-by: Jee Jee Li <pandaleefree@gmail.com> | csrc/moe/torch_bindings.cpp | cpp | Apache-2.0 | #include "core/registration.h"
#include "moe_ops.h"
TORCH_LIBRARY_EXPAND(TORCH_EXTENSION_NAME, m) {
// Apply topk softmax to the gating outputs.
m.def(
"topk_softmax(Tensor! topk_weights, Tensor! topk_indices, Tensor! "
"token_expert_indices, Tensor gating_output, bool renormalize) -> ()");
m.impl("t... | #include "core/registration.h"
#include "moe_ops.h"
TORCH_LIBRARY_EXPAND(TORCH_EXTENSION_NAME, m) {
// Apply topk softmax to the gating outputs.
m.def(
"topk_softmax(Tensor! topk_weights, Tensor! topk_indices, Tensor! "
"token_expert_indices, Tensor gating_output, bool renormalize) -> ()");
m.impl("t... | --- csrc/moe/torch_bindings.cpp
+++ csrc/moe/torch_bindings.cpp
@@ -19,7 +19,8 @@
"moe_align_block_size(Tensor topk_ids, int num_experts,"
" int block_size, Tensor! sorted_token_ids,"
" Tensor! experts_ids,"
- " Tensor! num_tokens_pos... | 2 | 1 | 6 | [] | [] | [] | Optimize this cpp kernel file from vllm (csrc/moe/torch_bindings.cpp).
Goal: [Kernel][MoE] optimize `moe_align_block_size`
Target hardware: unspecified
Target models: unspecified
Current file:
```cpp
#include "core/registration.h"
#include "moe_ops.h"
TORCH_LIBRARY_EXPAND(TORCH_EXTENSION_NAME, m) {
// Apply topk s... | ## Introduction
This PR optimize `moe_align_block_size` from three aspects:
1. For a small batch size, use the smallest possible value for `max_num_tokens_padded`.
2. In the CUDA Kernel, use additional thread or threadblock resources to fill `sorted_token_ids`. The previous CUDA Kernel used very few computational res... | [] | null | null |
vllm | 879ddb09c3b7b5a21f75e46ded148ce70f1c486e | 2025-12-07T17:58:47+08:00 | 29,642 | https://github.com/vllm-project/vllm/pull/29642 | [Kernel][MoE] optimize `moe_align_block_size` (#29642) | [Kernel][MoE] optimize `moe_align_block_size` (#29642)
Signed-off-by: Jinzhen Lin <jinzhen.ljz@antgroup.com>
Co-authored-by: Jee Jee Li <pandaleefree@gmail.com> | vllm/model_executor/layers/fused_moe/fused_moe.py | triton | Apache-2.0 | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
"""Fused MoE Triton kernels."""
import functools
import json
import os
from collections.abc import Callable
from typing import Any
import torch
import torch.nn.functional as F
import vllm.envs as envs
import vl... | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
"""Fused MoE Triton kernels."""
import functools
import json
import os
from collections.abc import Callable
from typing import Any
import torch
import torch.nn.functional as F
import vllm.envs as envs
import vl... | --- vllm/model_executor/layers/fused_moe/fused_moe.py
+++ vllm/model_executor/layers/fused_moe/fused_moe.py
@@ -1887,7 +1887,11 @@
)
sorted_token_ids, expert_ids, num_tokens_post_padded = moe_align_block_size(
- curr_topk_ids, config["BLOCK_SIZE_M"], global_num_experts, expert_map
+ ... | 8 | 1 | 6 | [] | [] | [] | Optimize this triton kernel file from vllm (vllm/model_executor/layers/fused_moe/fused_moe.py).
Goal: [Kernel][MoE] optimize `moe_align_block_size`
Target hardware: unspecified
Target models: unspecified
Current file:
```python
# SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to ... | ## Introduction
This PR optimize `moe_align_block_size` from three aspects:
1. For a small batch size, use the smallest possible value for `max_num_tokens_padded`.
2. In the CUDA Kernel, use additional thread or threadblock resources to fill `sorted_token_ids`. The previous CUDA Kernel used very few computational res... | [] | null | null |
vllm | 9843e332da56307597deb2739bb83b85c18c5dde | 2025-12-05T08:09:20-05:00 | 30,068 | https://github.com/vllm-project/vllm/pull/30068 | [CPU][Perf] Add fast vectorized exp impl from Arm Optimized Routines (#30068) | [CPU][Perf] Add fast vectorized exp impl from Arm Optimized Routines (#30068)
Signed-off-by: Ubuntu <ubuntu@ip-10-252-30-150.eu-west-1.compute.internal>
Signed-off-by: Elham Harirpoush <elham.harirpoush@arm.com>
Co-authored-by: Ubuntu <ubuntu@ip-10-252-30-150.eu-west-1.compute.internal> | csrc/cpu/cpu_attn_impl.hpp | cpp | Apache-2.0 | #ifndef CPU_ATTN_HPP
#define CPU_ATTN_HPP
#include <type_traits>
#include <cstddef>
#if defined(__APPLE__)
#include <sys/sysctl.h>
#endif
#include "cpu_types.hpp"
#include "scratchpad_manager.h"
#include "cpu_attn_macros.h"
#include "utils.hpp"
namespace cpu_attention {
enum class ISA { AMX, VEC, VEC16, NEON };
... | #ifndef CPU_ATTN_HPP
#define CPU_ATTN_HPP
#include <type_traits>
#include <cstddef>
#if defined(__APPLE__)
#include <sys/sysctl.h>
#endif
#include "cpu_types.hpp"
#include "scratchpad_manager.h"
#include "cpu_attn_macros.h"
#include "utils.hpp"
namespace cpu_attention {
enum class ISA { AMX, VEC, VEC16, NEON };
... | --- csrc/cpu/cpu_attn_impl.hpp
+++ csrc/cpu/cpu_attn_impl.hpp
@@ -1246,14 +1246,8 @@
// rescale sum and partial outputs
if (need_rescale) {
// compute rescale factor
-#ifdef DEFINE_FAST_EXP
- vec_op::FP32Vec16 rescale_factor_vec(rescale_factor);
- rescale_factor_vec = fast... | 0 | 13 | 2 | [] | [
"CPU"
] | [] | Optimize this cpp kernel file from vllm (csrc/cpu/cpu_attn_impl.hpp).
Goal: [CPU][Perf] Add fast vectorized exp impl from Arm Optimized Routines
Target hardware: CPU
Target models: unspecified
Current file:
```cpp
#ifndef CPU_ATTN_HPP
#define CPU_ATTN_HPP
#include <type_traits>
#include <cstddef>
#if defined(__APPL... | <!-- markdownlint-disable -->
## Purpose
This accelerates paged attention by 20% on Arm Neoverse-V2 for batch size = 64, query tokens = kv tokens = 512, q heads = 32, kv heads = 8, head size = 128, block size = 128
## Test Plan
@fadara01 will test in CI
## Test Result
---
<details>
<summary> Essential Elements of... | [{"scope": "kernel", "hardware": "Arm Neoverse-V2", "model": null, "shape": "q_heads=32,kv_heads=8,head_size=128,block_size=128", "batch_size": 64, "metric": "latency", "unit": null, "higher_is_better": false, "baseline": null, "optimized": null, "stated_speedup": 1.2, "speedup": 1.2}] | 1.2 | null |
vllm | 9843e332da56307597deb2739bb83b85c18c5dde | 2025-12-05T08:09:20-05:00 | 30,068 | https://github.com/vllm-project/vllm/pull/30068 | [CPU][Perf] Add fast vectorized exp impl from Arm Optimized Routines (#30068) | [CPU][Perf] Add fast vectorized exp impl from Arm Optimized Routines (#30068)
Signed-off-by: Ubuntu <ubuntu@ip-10-252-30-150.eu-west-1.compute.internal>
Signed-off-by: Elham Harirpoush <elham.harirpoush@arm.com>
Co-authored-by: Ubuntu <ubuntu@ip-10-252-30-150.eu-west-1.compute.internal> | csrc/cpu/cpu_attn_macros.h | cpp | Apache-2.0 | #ifndef CPU_ATTN_MACROS_H
#define CPU_ATTN_MACROS_H
// x86_64
#ifdef __x86_64__
#define FAST_SPINNING _mm_pause();
#ifdef __AVX512F__
#define DEFINE_FAST_EXP \
const __m512 vec_factorial_1 = _mm512_set1_ps(0.999999701f); \
const __m512... | #ifndef CPU_ATTN_MACROS_H
#define CPU_ATTN_MACROS_H
// x86_64
#ifdef __x86_64__
#define FAST_SPINNING _mm_pause();
#ifdef __AVX512F__
#define DEFINE_FAST_EXP \
const __m512 vec_factorial_1 = _mm512_set1_ps(0.999999701f); \
const __m512... | --- csrc/cpu/cpu_attn_macros.h
+++ csrc/cpu/cpu_attn_macros.h
@@ -60,4 +60,54 @@
#endif
+#ifdef __aarch64__
+ // Implementation copied from Arm Optimized Routines (expf AdvSIMD)
+ // https://github.com/ARM-software/optimized-routines/blob/master/math/aarch64/advsimd/expf.c
+ #include <limits>
+ #define DEFINE_... | 50 | 0 | 2 | [] | [
"CPU"
] | [] | Optimize this cpp kernel file from vllm (csrc/cpu/cpu_attn_macros.h).
Goal: [CPU][Perf] Add fast vectorized exp impl from Arm Optimized Routines
Target hardware: CPU
Target models: unspecified
Current file:
```cpp
#ifndef CPU_ATTN_MACROS_H
#define CPU_ATTN_MACROS_H
// x86_64
#ifdef __x86_64__
#define FAST_SPINNING... | <!-- markdownlint-disable -->
## Purpose
This accelerates paged attention by 20% on Arm Neoverse-V2 for batch size = 64, query tokens = kv tokens = 512, q heads = 32, kv heads = 8, head size = 128, block size = 128
## Test Plan
@fadara01 will test in CI
## Test Result
---
<details>
<summary> Essential Elements of... | [{"scope": "kernel", "hardware": "Arm Neoverse-V2", "model": null, "shape": "q_heads=32,kv_heads=8,head_size=128,block_size=128", "batch_size": 64, "metric": "latency", "unit": null, "higher_is_better": false, "baseline": null, "optimized": null, "stated_speedup": 1.2, "speedup": 1.2}] | 1.2 | null |
vllm | 19bee6d12d985c231b16374c99836376fc0c5706 | 2025-12-03T13:04:59-05:00 | 29,470 | https://github.com/vllm-project/vllm/pull/29470 | [Performance][DP/EP] Add silu_mul_per_token_group_quant_fp8_colmajor kernel (#29470) | [Performance][DP/EP] Add silu_mul_per_token_group_quant_fp8_colmajor kernel (#29470)
Signed-off-by: Varun Sundar Rabindranath <vsundarr@redhat.com>
Co-authored-by: Varun Sundar Rabindranath <vsundarr@redhat.com>
Co-authored-by: Tyler Michael Smith <tyler@neuralmagic.com> | vllm/model_executor/layers/quantization/utils/fp8_utils.py | triton | Apache-2.0 | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# Adapted from https://github.com/sgl-project/sglang/pull/2575
import functools
import json
import os
from collections.abc import Callable, Sequence
from typing import Any
import torch
import vllm.envs as envs
... | # SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
# Adapted from https://github.com/sgl-project/sglang/pull/2575
import functools
import json
import os
from collections.abc import Callable, Sequence
from typing import Any
import torch
import vllm.envs as envs
... | --- vllm/model_executor/layers/quantization/utils/fp8_utils.py
+++ vllm/model_executor/layers/quantization/utils/fp8_utils.py
@@ -490,6 +490,139 @@
tl.store(y_q_ptr + cols, y_q, mask=mask)
tl.store(y_s_ptr, y_s)
+
+
+@triton.jit
+def _silu_mul_per_token_group_quant_fp8_colmajor(
+ y_ptr, # [M, N]
+ y... | 133 | 0 | 2 | [] | [] | [] | Optimize this triton kernel file from vllm (vllm/model_executor/layers/quantization/utils/fp8_utils.py).
Goal: [Performance][DP/EP] Add silu_mul_per_token_group_quant_fp8_colmajor kernel
Target hardware: unspecified
Target models: unspecified
Current file:
```python
# SPDX-License-Identifier: Apache-2.0
# SPDX-FileCo... | ## Purpose
With DeepEPHighThroughput all2all backend and EP, the "act_mul + fp8 quant" operation in deep_gemm_moe.py is expensive and almost as expensive as the FP8 gemms surrounding the operation. This PR,
1. Adds a fused silu_mul_quant kernels to fuse the operations together.
2. Another minor optimization is to rearr... | [] | null | null |
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