repo_name stringlengths 1 62 | dataset stringclasses 1
value | lang stringclasses 11
values | pr_id int64 1 20.1k | owner stringlengths 2 34 | reviewer stringlengths 2 39 | diff_hunk stringlengths 15 262k | code_review_comment stringlengths 1 99.6k |
|---|---|---|---|---|---|---|---|
intel-xpu-backend-for-triton | github_2023 | others | 3,053 | intel | anmyachev | @@ -2,20 +2,26 @@ name: save
description: Save a directory to a cache based on a shared directory
inputs:
root:
- description:
+ description: Directory for cache
default: /cache
path:
description: Directory to save to a cache
required: true
dest:
description: Directory in cache
... | Why not something like that?
```suggestion
- name: Save ${{ inputs.path }} to cache
if: ${{ inputs.enabled == 'true' }}
``` |
intel-xpu-backend-for-triton | github_2023 | python | 3,041 | intel | anmyachev | @@ -24,3 +24,10 @@ def fresh_triton_cache():
except OSError:
# Ignore errors, such as PermissionError, on Windows
pass
+
+
+def pytest_configure(config):
+ worker_id = os.getenv("PYTEST_XDIST_WORKER")
+ # On Windows, use a dedicated Triton cache per pytest worker to avoid PermissionError.
+... | Could we create subfolders in default cache folder: `return os.path.join(get_home_dir(), ".triton", "cache")`? To simplify search. |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,950 | intel | etiotto | @@ -515,7 +515,10 @@ struct LoadOpConversion
const bool memoryRowMajor = (memoryLayoutInfo == "row_major");
DotOperandEncodingAttr dotLayout = getDotEncoding(tensorType).value();
- auto dotOrder = dotLayout.getThreadOrder();
+ // The getThreadOrder doesn't support Intel MMA layout. | We should fix `getThreadOrder` instead. |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,010 | intel | chengjunlu | @@ -83,35 +83,21 @@ Value addStringToModule(Location loc, RewriterBase &rewriter, StringRef key,
LLVM::LLVMFuncOp getSpirvPrintfDeclaration(RewriterBase &rewriter);
-static Value getStackPointer(PatternRewriter &rewriter,
- FunctionOpInterface funcOp) {
- auto mod = funcOp->getParentOf... | Can we remove this since it is same to the one in upstream Utility.h |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,000 | intel | chengjunlu | @@ -514,8 +516,11 @@ struct LoadOpConversion
"Only row_major or column_major is supported");
const bool memoryRowMajor = (memoryLayoutInfo == "row_major");
- DotOperandEncodingAttr dotLayout = getDotEncoding(tensorType).value();
- auto dotOrder = dotLayout.getThreadOrder();
+ auto dpasLayout... | We need get the order from the layout encoding instead of the parent layout for `#ttg.dot_op`.
Maybe we can use `encoding.getThreadOrder`. |
intel-xpu-backend-for-triton | github_2023 | python | 3,030 | intel | anmyachev | @@ -103,9 +103,7 @@ def parse_report(report_path: pathlib.Path, skiplist_dir: pathlib.Path) -> Repor
pass
stats.fixme += len(testsuite_fixme_tests)
- test_unskip = os.getenv('TEST_UNSKIP')
- if test_unskip not in ('true', 'false'): | Why don't you want to leave the check for valid variable values? |
intel-xpu-backend-for-triton | github_2023 | python | 3,011 | intel | whitneywhtsang | @@ -0,0 +1,333 @@
+# Copyright 2023-2024 SGLang Team
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable ... | can we add timing mechanism and result checking to ensure functional correctness? |
intel-xpu-backend-for-triton | github_2023 | others | 2,996 | intel | LiyangLingIntel | @@ -74,17 +74,41 @@ along the row (resp. col) dimension.
);
let extraClassDeclaration = extraDistributedDeclaration # [{
+ enum class OpIdx : unsigned {
+ Zero = 0u, // operand A
+ One = 1u, // operand B
+ Two = 2u // operand C
+ }; | How about using more meaningful enumeration names like `OperandA` or `OpA`? This would be consistant with the related function names like `getShapeA`. |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,951 | intel | etiotto | @@ -127,6 +127,8 @@ static Value getModuleWarpSize(RewriterBase &rewriter, Location loc) {
return i32_val(triton::gpu::TritonGPUDialect::getThreadsPerWarp(mod));
}
+Value mxfpScaleBf16(ConversionPatternRewriter &rewriter, Location loc, Value v, | This should be defined as a static function in `third_party/intel/lib/TritonIntelGPUToLLVM/UpcastMXFPToLLVM.cpp`, it is used only in that file. |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,951 | intel | etiotto | @@ -40,16 +48,16 @@ class DPASAnalysis {
Result canUseDPAS(FunctionOpInterface funcOp) const;
/// Given a DotOp operation, return its DPAS engine type.
- static DPASEngineType getDPASType(DotOp op);
+ static DPASEngineType getDPASType(Operation *op); | This could be a templated function where the template type may be only one of `DotOp`, `DotScaledOp` (enforced at template instantiation time). |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,951 | intel | etiotto | @@ -0,0 +1,68 @@
+#include "PatternTritonGPUOpToLLVM.h"
+
+#include "mlir/Conversion/LLVMCommon/Pattern.h"
+#include "mlir/IR/BuiltinOps.h"
+#include "mlir/IR/TypeUtilities.h"
+#include "mlir/IR/ValueRange.h"
+#include "mlir/Transforms/DialectConversion.h"
+#include "triton/Conversion/TritonGPUToLLVM/Utility.h"
+#inclu... | `mxfpScaleBf16` can be private to this class (or a static utility function defined in this file). |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,951 | intel | etiotto | @@ -287,36 +293,75 @@ class DecomposeScaledBlocked : public OpRewritePattern<tt::DotScaledOp> {
assert(opDesc.scale && "Expecting valid operand & scale");
unsigned opsPerChannel = dpasEnc.getOpsPerChannel();
- if (opDesc.elemType == tt::ScaleDotElemType::E2M1)
- opsPerChannel *= 2;
MLIRContex... | Remove else after return |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,951 | intel | whitneywhtsang | @@ -39,17 +47,24 @@ class DPASAnalysis {
/// (aka threads per warp) size.
Result canUseDPAS(FunctionOpInterface funcOp) const;
- /// Given a DotOp operation, return its DPAS engine type.
- static DPASEngineType getDPASType(DotOp op);
+ /// Given a 'DotOp' or 'ScaledDot' operation, return its DPAS engine t... | why need to turn off clang-format? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,951 | intel | whitneywhtsang | @@ -65,53 +73,110 @@ DPASAnalysis::canUseDPAS(FunctionOpInterface funcOp) const {
return (threadsPerWarp == minSGSize) ? Result::True : Result::False;
}
-DPASAnalysis::DPASEngineType DPASAnalysis::getDPASType(DotOp op) {
- // d = a * b + c
- auto aTy = cast<RankedTensorType>(op.getA().getType());
- auto bTy = ... | ?
```suggestion
return DPASAnalysis::getDPASType(dotOp);
``` |
intel-xpu-backend-for-triton | github_2023 | python | 2,995 | intel | pbchekin | @@ -142,12 +146,14 @@ def parse_target(self, tgt_prop) -> dict:
dev_prop['max_num_sub_groups'] = tgt_prop.get('max_num_sub_groups', None)
dev_prop['sub_group_sizes'] = tgt_prop.get('sub_group_sizes', None)
dev_prop['has_fp64'] = tgt_prop.get('has_fp64', None)
- if os.getenv("TRITON_INT... | Why do we need this? Looks like `ocloc query` prints the result to stdout, no need to delete anything. |
intel-xpu-backend-for-triton | github_2023 | python | 2,995 | intel | pbchekin | @@ -142,12 +146,20 @@ def parse_target(self, tgt_prop) -> dict:
dev_prop['max_num_sub_groups'] = tgt_prop.get('max_num_sub_groups', None)
dev_prop['sub_group_sizes'] = tgt_prop.get('sub_group_sizes', None)
dev_prop['has_fp64'] = tgt_prop.get('has_fp64', None)
- if os.getenv("TRITON_INT... | Nit:
```suggestion
if device_arch:
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,988 | intel | whitneywhtsang | @@ -1356,14 +1297,7 @@ struct AbsFOpConversion
ConversionPatternRewriter &rewriter,
Type elemTy, MultipleOperandsRange operands,
Location loc) const {
- // FIXME: Remove bitcast to and from i16 once SPIRV-LLVM... | Don't think SPIRV-LLVM-Translator added the support. |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,988 | intel | whitneywhtsang | @@ -1373,8 +1307,8 @@ struct AbsFOpConversion
auto maskAttr = rewriter.getIntegerAttr(elemTy, mask);
auto maskConst = rewriter.create<LLVM::ConstantOp>(loc, maskAttr);
Value res = and_(v, maskConst);
- if (llvm::isa<BFloat16Type>(orig_type))
- res = bitcast(res, orig_type);
+ if (l... | Assuming SPIRV-LLVM-Translator added the support, then we don't need to convert back, as we removed the original conversion at line 1363. |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,985 | intel | etiotto | @@ -33,14 +33,39 @@ void lowerDistributedToShared(
auto outOrd = mlir::cast<SharedEncodingAttr>(dstTy.getEncoding()).getOrder();
auto elemTy = typeConverter->convertType(srcTy.getElementType());
- auto smemBase = smemObj.getBase(); | This is now identical to the upstream implementation |
intel-xpu-backend-for-triton | github_2023 | others | 2,449 | intel | whitneywhtsang | @@ -336,10 +336,10 @@ module attributes {"triton_gpu.num-warps" = 4 : i32, "triton_gpu.threads-per-war
// CHECK-LABEL: llvm.func spir_kernelcc @test(
// CHECK-SAME: %[[VAL_0:.*]]: !llvm.ptr<3>,
// CHECK-SAME: %[[VAL_1:.*]]: vector<16xf32>) -> vector... | may need to rebase, the change to `get_sub_group_id` should be merged by now. |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,954 | intel | anmyachev | @@ -47,6 +47,12 @@ auto read_spirv(const std::string &filename) {
return read_file_as_bytes(filename);
}
+// Host output tensor buffers and indexes
+struct TensorBuffer { | Why not std::pair? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,954 | intel | anmyachev | @@ -369,36 +376,40 @@ at::Tensor launchKernel(sycl::queue stream, sycl::kernel kernel,
.wait_and_throw();
// Configure output tensor
- if (item.at("name").get<std::string>() == triton_args.out_tensor_name) {
- devout_idx = triton_args.dev_buffers.size() - 1;
- triton_arg... | When copying `torch::Tensor`, does it copy only the pointer to the tensor or the entire tensor? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,954 | intel | anmyachev | @@ -369,36 +376,40 @@ at::Tensor launchKernel(sycl::queue stream, sycl::kernel kernel,
.wait_and_throw();
// Configure output tensor
- if (item.at("name").get<std::string>() == triton_args.out_tensor_name) {
- devout_idx = triton_args.dev_buffers.size() - 1;
- triton_arg... | For consistency, it is better to use either only `tb` or only `host_outbuffers.back()`. |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,954 | intel | anmyachev | @@ -369,36 +376,40 @@ at::Tensor launchKernel(sycl::queue stream, sycl::kernel kernel,
.wait_and_throw();
// Configure output tensor
- if (item.at("name").get<std::string>() == triton_args.out_tensor_name) {
- devout_idx = triton_args.dev_buffers.size() - 1;
- triton_arg... | Why isn't this exception thrown anymore? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,954 | intel | anmyachev | @@ -369,36 +376,40 @@ at::Tensor launchKernel(sycl::queue stream, sycl::kernel kernel,
.wait_and_throw();
// Configure output tensor
- if (item.at("name").get<std::string>() == triton_args.out_tensor_name) {
- devout_idx = triton_args.dev_buffers.size() - 1;
- triton_arg... | ?
```suggestion
for (const auto &item : triton_args.host_outbuffers) {
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,700 | intel | chengjunlu | @@ -95,9 +96,23 @@ LogicalResult UpcastMXFPOp::inferReturnTypes(
if (typeEncoded == ScaleDotElemType::E2M1) {
auto oldEncoding = cast<DotOperandEncodingAttr>(encoding);
- auto newVEncoding = DotOperandEncodingAttr::get(
- ctx, oldEncoding.getOpIdx(), oldEncoding.getParent(),
- oldEncoding.get... | `opsPerChannel` is defined by the HW DPAS instruction.
I think we should align the `opsPerChannel` to the result scalar type of the `UpcastMXFPOp` instead of double the size.
fp16/bf16 -> `opsPerChannel=2`
Otherwise there might be ambiguous in the lowering of `UpcastMXFPOp`. |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,700 | intel | chengjunlu | @@ -0,0 +1,83 @@
+#include "PatternTritonGPUOpToLLVM.h"
+
+#include "mlir/Conversion/LLVMCommon/Pattern.h"
+#include "mlir/IR/BuiltinOps.h"
+#include "mlir/IR/TypeUtilities.h"
+#include "mlir/IR/ValueRange.h"
+#include "mlir/Transforms/DialectConversion.h"
+#include "triton/Conversion/TritonGPUToLLVM/Utility.h"
+#inclu... | The better we need to make sure the layout are expected of the `DotOp` with the `DPAS` as parent and the layout conversion from the source operand to the dest operand are supported as well. |
intel-xpu-backend-for-triton | github_2023 | others | 2,942 | intel | pbchekin | @@ -45,6 +45,13 @@ jobs:
- name: Build Triton
run: |
cd ${{ env.NEW_WORKSPACE }}
+
+ cmd /c '"C:\Program Files\Microsoft Visual Studio\2022\Community\VC\Auxiliary\Build\vcvarsall.bat" x64 && set' | ForEach-Object {
+ if ($_ -match '^(.*?)=(.*)$') {
+ [En... | This should also work (and simpler).
```suggestion
Invoke-BatchFile "C:\Program Files\Microsoft Visual Studio\2022\Community\VC\Auxiliary\Build\vcvarsall.bat"
``` |
intel-xpu-backend-for-triton | github_2023 | others | 2,959 | intel | pbchekin | @@ -288,6 +293,24 @@ run_benchmark_attention() {
python $TRITON_PROJ/benchmarks/triton_kernels_benchmark/flash_attention_fwd_benchmark.py
}
+run_benchmarks() {
+ cd $TRITON_PROJ/benchmarks
+ python setup.py install
+ for file in $TRITON_PROJ/benchmarks/triton_kernels_benchmark/*.py; do
+ if ! [ -f "$file"... | Does this look simpler?
```suggestion
python $file
``` |
intel-xpu-backend-for-triton | github_2023 | others | 2,959 | intel | pbchekin | @@ -288,6 +293,24 @@ run_benchmark_attention() {
python $TRITON_PROJ/benchmarks/triton_kernels_benchmark/flash_attention_fwd_benchmark.py
}
+run_benchmarks() {
+ cd $TRITON_PROJ/benchmarks
+ python setup.py install
+ for file in $TRITON_PROJ/benchmarks/triton_kernels_benchmark/*.py; do
+ if ! [ -f "$file"... | Why this check is needed? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,934 | intel | whitneywhtsang | @@ -154,6 +154,18 @@ class LoadStorePrefetchOpConversion
matchAndRewrite(OpType op, typename OpType::Adaptor adaptor,
ConversionPatternRewriter &rewriter) const override {
auto ptrType = cast<PointerType>(op.getPtr().getType());
+ // scalar load/store
+ if (!isa<RankedTensorType>(ptrTyp... | can be replaced with `llvm_unreachable` |
intel-xpu-backend-for-triton | github_2023 | others | 2,900 | intel | whitneywhtsang | @@ -13,6 +13,9 @@ target_link_libraries(triton-opt PRIVATE
TritonTransforms
TritonGPUTransforms
TritonNvidiaGPUTransforms
+ TritonIntelLLVMIR
+ TritonIntelGPUIR
+ TritonIntelGPUTransforms | They were removed intentionally in https://github.com/intel/intel-xpu-backend-for-triton/pull/2874.
```suggestion
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,900 | intel | etiotto | @@ -1,7 +1,7 @@
/// Trimmed down clone of llvm opt to be able to test triton custom llvm ir
/// passes.
#include "lib/Target/LLVMIR/LLVMPasses.h"
-#include "third_party/intel/lib/LLVMIR/LLVMPasses.h"
+#include "third_party/intel/lib/Target/LLVMIR/LLVMPasses.h" | I wonder if we really need to add this to this (common) makefile, it wasn't required for the PostProcessing library. |
intel-xpu-backend-for-triton | github_2023 | others | 2,900 | intel | etiotto | @@ -9,7 +9,6 @@ add_triton_plugin(TritonXPU
LINK_LIBS
MLIRGPUToLLVMSPV
- PostProcessLLVMIR | I don't understand the reason we need to remove this from the intel 3rd party makefile. |
intel-xpu-backend-for-triton | github_2023 | others | 2,900 | intel | etiotto | @@ -1,8 +1,12 @@
add_subdirectory(Dialect)
-add_mlir_translation_library(PostProcessLLVMIR
+add_triton_library(TritonIntelLLVMIR | What is the reason for not using `add_mlir_translation_library` and instead using `add_triton_library` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,048 | intel | anmyachev | @@ -1573,11 +1573,11 @@ void init_triton_ir(py::module &&m) {
if (haveDiagnostics) {
context->printOpOnDiagnostic(true);
context->printStackTraceOnDiagnostic(true);
- context->getDiagEngine().registerHandler([](Diagnostic &diag) {
- llvm::outs(... | @whitneywhtsang could we revert this change? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,910 | intel | whitneywhtsang | @@ -236,69 +232,118 @@ class DecomposeScaledBlocked : public OpRewritePattern<tt::DotScaledOp> {
if (!supportsTypes(aElemType) || !supportsTypes(bElemType))
return rewriter.notifyMatchFailure(scaledDotOp, "NYI: mxfp6 operand");
- MLIRContext *ctx = scaledDotOp.getContext();
- auto mod = scaledDotOp-... | ```suggestion
template <unsigned opIdx>
``` |
intel-xpu-backend-for-triton | github_2023 | others | 2,759 | intel | anmyachev | @@ -129,6 +129,7 @@ build_llvm() {
cd $LLVM_PROJ_BUILD
cmake -G Ninja ../llvm \
-DLLVM_ENABLE_DUMP=1 \
+ -DLLVM_ENABLE_RTTI=ON \ | Why? |
intel-xpu-backend-for-triton | github_2023 | others | 2,759 | intel | anmyachev | @@ -38,10 +44,10 @@ set(SYCL_FUNCTIONS_INCLUDE_DIR "${CMAKE_CURRENT_SOURCE_DIR}/../../third_party/in
set(TARGET_NAME SPIRVRunner)
add_executable(${TARGET_NAME} ${TARGET_NAME}.cpp)
target_include_directories(${TARGET_NAME} PRIVATE
- "${ONEAPI_ROOT}/compiler/latest/include" ${SYCL_FUNCTIONS_INCLUDE_DIR} ${JSON_INCL... | I suppose this increases the number of dependencies in the form of shared libraries? It is advisable to move away from this, since those to whom we report binaries already have a hard time setting up the environment. |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,759 | intel | alexbaden | @@ -0,0 +1,20 @@
+#ifndef LLVM_PARSER_H
+#define LLVM_PARSER_H
+
+#include "llvm/Support/CommandLine.h"
+
+class command_line_parser {
+public:
+ struct options {
+ std::string output_tensor; | I recommend putting the default values (where appropriate) in the struct, instantiating the struct first, and then reading the default values for the command line options out of the struct (e.g. `llvm::cl::init(ops.enable_profiling)`). I have not tried this with llvm but it should be possible - this was std practice wi... |
intel-xpu-backend-for-triton | github_2023 | others | 2,915 | intel | anmyachev | @@ -28,7 +28,9 @@ function(add_triton_ut)
gmock
${__LIBS})
- target_compile_options(${__NAME} PRIVATE -fno-rtti)
+ if(NOT MSVC)
+ target_compile_options(${__NAME} PRIVATE -fno-rtti) | Should we use `/GR-` (IIUC it's analogue for `-fno-rtti`) for MSVC? |
intel-xpu-backend-for-triton | github_2023 | others | 2,915 | intel | anmyachev | @@ -70,7 +70,6 @@ else()
set(CMAKE_EXE_LINKER_FLAGS_TRITONRELBUILDWITHASSERTS "/debug:fastlink /INCREMENTAL")
set(CMAKE_MODULE_LINKER_FLAGS_TRITONRELBUILDWITHASSERTS "/debug:fastlink /INCREMENTAL")
set(CMAKE_SHARED_LINKER_FLAGS_TRITONRELBUILDWITHASSERTS "/debug:fastlink /INCREMENTAL")
- set(CMAKE_STATIC_LINKE... | why? |
intel-xpu-backend-for-triton | github_2023 | others | 2,881 | intel | pbchekin | @@ -1,5 +1,5 @@
[build-system]
-requires = ["setuptools>=40.8.0", "wheel", "cmake>=3.18", "ninja>=1.11.1"]
+requires = ["setuptools>=60.8.0", "wheel", "cmake>=3.18", "ninja>=1.11.1"] | It's more reasonable to have `setuptools>=65.6.1` which has #3690: Fixed logging errors: 'underlying buffer has been detached' (issue #1631) (https://github.com/pypa/setuptools/blob/main/NEWS.rst#v6561). |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,775 | intel | arunjose696 | @@ -0,0 +1,57 @@
+#include "LLVMPasses.h"
+#include "llvm/Analysis/TargetTransformInfo.h"
+#include "llvm/Analysis/ValueTracking.h"
+#include "llvm/IR/Dominators.h"
+#include "llvm/IR/Instructions.h"
+
+using namespace llvm;
+
+static bool processPhiNode(PHINode *PhiNode, BasicBlock &BB) {
+ if (!any_of(PhiNode->incom... | ```suggestion
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,775 | intel | arunjose696 | @@ -0,0 +1,57 @@
+#include "LLVMPasses.h"
+#include "llvm/Analysis/TargetTransformInfo.h"
+#include "llvm/Analysis/ValueTracking.h"
+#include "llvm/IR/Dominators.h"
+#include "llvm/IR/Instructions.h"
+
+using namespace llvm;
+
+static bool processPhiNode(PHINode *PhiNode, BasicBlock &BB) {
+ if (!any_of(PhiNode->incom... | ```suggestion
Changed |= processPhiNode(PhiNode, I);
```
I think passing instruction as argument can avoid iterating again in processPhiNode |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,775 | intel | arunjose696 | @@ -0,0 +1,57 @@
+#include "LLVMPasses.h"
+#include "llvm/Analysis/TargetTransformInfo.h"
+#include "llvm/Analysis/ValueTracking.h"
+#include "llvm/IR/Dominators.h"
+#include "llvm/IR/Instructions.h"
+
+using namespace llvm;
+
+static bool processPhiNode(PHINode *PhiNode, BasicBlock &BB) {
+ if (!any_of(PhiNode->incom... | I am unclear why do we decide to not freeze the operands if one of the incoming value is Null?
|
intel-xpu-backend-for-triton | github_2023 | cpp | 2,775 | intel | arunjose696 | @@ -0,0 +1,57 @@
+#include "LLVMPasses.h"
+#include "llvm/Analysis/TargetTransformInfo.h"
+#include "llvm/Analysis/ValueTracking.h"
+#include "llvm/IR/Dominators.h"
+#include "llvm/IR/Instructions.h"
+
+using namespace llvm;
+
+static bool processPhiNode(PHINode *PhiNode, BasicBlock &BB) {
+ if (!any_of(PhiNode->incom... | instruction as argument instead of basicblock
```suggestion
static bool processPhiNode(PHINode *PhiNode, Instruction &I) {
if (!any_of(PhiNode->incoming_values(), [](Use &U) {
if (Constant *C = dyn_cast<Constant>(&U)) {
return C->isNullValue();
}
return false;
})) {
... |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,775 | intel | victor-eds | @@ -0,0 +1,56 @@
+#include "LLVMPasses.h"
+#include "llvm/Analysis/TargetTransformInfo.h"
+#include "llvm/Analysis/ValueTracking.h"
+#include "llvm/IR/Dominators.h"
+#include "llvm/IR/Instructions.h"
+
+using namespace llvm;
+
+static bool processBasicBlock(BasicBlock &BB, PHINode *PhiNode) {
+ if (!any_of(PhiNode->in... | ```suggestion
for (PHINode &PhiNode : BB.phis()) {
Changed |= processBasicBlock(BB, &PhiNode);
}
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,775 | intel | victor-eds | @@ -0,0 +1,56 @@
+#include "LLVMPasses.h"
+#include "llvm/Analysis/TargetTransformInfo.h"
+#include "llvm/Analysis/ValueTracking.h"
+#include "llvm/IR/Dominators.h"
+#include "llvm/IR/Instructions.h"
+
+using namespace llvm;
+
+static bool processBasicBlock(BasicBlock &BB, PHINode *PhiNode) {
+ if (!any_of(PhiNode->in... | ```suggestion
if (!any_of(PhiNode->incoming_values(), [](Use &U) {
Constant *C = dyn_cast<Constant>(&U));
return C && C->isNullValue();
})) {
return false;
}
```
More readable? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,775 | intel | victor-eds | @@ -0,0 +1,56 @@
+#include "LLVMPasses.h"
+#include "llvm/Analysis/TargetTransformInfo.h"
+#include "llvm/Analysis/ValueTracking.h"
+#include "llvm/IR/Dominators.h"
+#include "llvm/IR/Instructions.h"
+
+using namespace llvm;
+
+static bool processBasicBlock(BasicBlock &BB, PHINode *PhiNode) {
+ if (!any_of(PhiNode->in... | Wouldn't it be better to iterate on `PhiNode`'s uses? |
intel-xpu-backend-for-triton | github_2023 | python | 2,775 | intel | victor-eds | @@ -0,0 +1,84 @@
+# flake8: noqa: F821, F841
+import torch
+import pytest
+
+import triton
+import triton.language as tl
+
+aten = torch.ops.aten
+
+
+def patch_kernel(template, to_replace):
+ kernel = triton.JITFunction(template.fn)
+ for key, value in to_replace.items():
+ kernel.src = kernel.src.replace... | ```suggestion
outputs_float_div = "tl.store(out_ptr0 + (x0), tmp4, xmask)\n tl.store(out_ptr3 + (x0), tmp4, xmask)" if float_div else ""
outputs_floor = "\n tl.store(out_ptr1 + (x0), tmp5, xmask)\n tl.store(out_ptr4 + (x0), tmp5, xmask)" if floor else ""
outputs_trunc = "\n tl.store(out_ptr2 ... |
intel-xpu-backend-for-triton | github_2023 | others | 2,775 | intel | etiotto | @@ -0,0 +1,6 @@
+add_triton_library(TritonIntelLLVMIR | It would be neat if we could keep all LLVMIR passes into a folder. The passes in `third_party/intel/lib/Target/LLVMIR/CMakeLists.txt` are LLVMIR passes that we run on the LLVM IR produced by `opt`. Here you will want to run the new pass *before* calling LLVM's `opt` but we could rename the library `PostProcessLLVMIR` t... |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,775 | intel | whitneywhtsang | @@ -0,0 +1,50 @@
+#include "LLVMPasses.h"
+#include "llvm/Analysis/TargetTransformInfo.h"
+#include "llvm/Analysis/ValueTracking.h"
+#include "llvm/IR/Dominators.h"
+#include "llvm/IR/Instructions.h"
+
+using namespace llvm;
+
+static bool processPhiNode(BasicBlock &BB, PHINode *PhiNode) {
+ if (!any_of(PhiNode->incom... | `!any_of` could be replaced with `none_of`? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,775 | intel | whitneywhtsang | @@ -0,0 +1,50 @@
+#include "LLVMPasses.h"
+#include "llvm/Analysis/TargetTransformInfo.h"
+#include "llvm/Analysis/ValueTracking.h"
+#include "llvm/IR/Dominators.h"
+#include "llvm/IR/Instructions.h"
+
+using namespace llvm;
+
+static bool processPhiNode(BasicBlock &BB, PHINode *PhiNode) { | instead of passing `BB`, could we get `BB` from `PhiNode->getParent()`? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,893 | intel | victor-eds | @@ -107,6 +108,77 @@ Value TargetInfo::programId(RewriterBase &rewriter, Location loc,
return rewriter.create<arith::IndexCastOp>(loc, i32_ty, blockId);
}
+namespace {
+
+template <typename GroupOp>
+Value createSPIRVGroupOp(RewriterBase &rewriter, Location loc, Type resultTy,
+ Value acc,... | ```suggestion
template <typename OpTy>
struct spirv_group_op {};
template <>
struct spirv_group_op<arith::AddFOp> {
using type = spirv::GroupNonUniformFAddOp;
};
// ...
template <typename OpTy>
using spirv_group_op_ty = spirv_group_op<OpTy>::type;
// ----
Value warpReduce =
TypeSwitch<mlir::Oper... |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,893 | intel | victor-eds | @@ -134,28 +206,22 @@ bool TargetInfo::warpReduce(RewriterBase &rewriter, Location loc,
reduceOp->getOperand(1) != block.getArgument(1))
return false;
- auto reduceKind =
- llvm::TypeSwitch<mlir::Operation *, std::optional<TritonGEN::ReduceKind>>(
- reduceOp)
- .Case<arith::AddFOp,... | ```suggestion
auto supportedOp = isa<arith::AddFOp, arith::AddIOp, arith::MulFOp, arith::MulIOp,
arith::MaxNumFOp, arith::MinNumFOp, arith::AndIOp, arith::OrIOp,
arith::XOrIOp>(reduceOp);
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,893 | intel | victor-eds | @@ -585,17 +586,25 @@ class ReduceOpConversion : public ConvertTritonGPUOpToLLVMPattern<ReduceOp> {
using AllReduceOperation = mlir::gpu::AllReduceOperation;
AllReduceOperation redKind;
if (isa<arith::AddFOp>(combine)) | ```cpp
TypeSwitch<Operation *>(combine)
.Case<arith::AddFOp, arith::MaxNumFOp>([&](auto combine) {
rewriter.replaceOpWithNewOp<spirv_group_op_ty<decltype(combine)>>(
combine, typeConverter->convertType(combine.getType(0)), spirv::Scope::Subgroup,
spirv::GroupOperation::Reduce, adaptor.get... |
intel-xpu-backend-for-triton | github_2023 | python | 2,867 | intel | chengjunlu | @@ -172,6 +173,9 @@ def get_sycl_queue(self):
import torch
return torch.xpu.current_stream().sycl_queue
+ def wait(self):
+ self.wait_on_sycl_queue(self.get_sycl_queue()) | Can we use the `torch.xpu.current_stream().wait()`?
It is easy for us to decouple the SYCL runtime in triton to torch. |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,804 | intel | victor-eds | @@ -381,6 +381,32 @@ SmallVector<unsigned> DpasEncodingAttr::getContigPerThread() {
"be smaller than the threads required per row.");
}
+DpasEncodingAttr::DPASCapability
+DpasEncodingAttr::getDPASCapability(ModuleOp mod) {
+ assert(mod && "expected a valid module");
+ if (!mod->hasAttrO... | ```suggestion
assert(elemType.isIntOrFloat() && "unsupported type for DpasEncodingAttr");
```
Better? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,804 | intel | whitneywhtsang | @@ -381,6 +381,32 @@ SmallVector<unsigned> DpasEncodingAttr::getContigPerThread() {
"be smaller than the threads required per row.");
}
+DpasEncodingAttr::DPASCapability
+DpasEncodingAttr::getDPASCapability(ModuleOp mod) {
+ assert(mod && "expected a valid module");
+ if (!mod->hasAttrO... | ```suggestion
if (auto minSGSizeAttr = mod->getAttrOfType<IntegerAttr>(
triton::gpu::intel::TritonIntelGPUDialect::getMinSGSizeAttrName())) {
unsigned minSGSize = minSGSizeAttr.getInt();
assert(minSGSize == 8 || minSGSize == 16 && "unsupported minSGSize");
return DPASCapability(minSGS... |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,804 | intel | whitneywhtsang | @@ -163,7 +127,15 @@ class BlockedToDPAS : public OpRewritePattern<tt::DotOp> {
dpasCap.executionSize, opsPerChan, warpsPerTile, repCluster,
threadsPerWarp);
- if (dpasCap.executionSize == 16 /* PVC */) {
+ if (dpasCap.isPVC() || dpasCap.isFalconShore()) { | Why do we care if it is PVC or FalconShore? I think is better to rely on execution size. |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,804 | intel | whitneywhtsang | @@ -219,6 +191,181 @@ class BlockedToDPAS : public OpRewritePattern<tt::DotOp> {
}
};
+class DecomposeScaledBlocked : public OpRewritePattern<tt::DotScaledOp> {
+ const ttg::intel::DPASAnalysis &dpasAnalysis;
+ using TensorValue = TypedValue<RankedTensorType>;
+
+public:
+ DecomposeScaledBlocked(MLIRContext *c... | I was trying to compare with `lib/Dialect/TritonGPU/Transforms/AccelerateMatmul.cpp`, but noticed that it is quite different, is that expected? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,804 | intel | victor-eds | @@ -114,17 +115,36 @@ LogicalResult UpcastMXFPOp::inferReturnTypes(
retTy = RankedTensorType::get(xShape, FloatType::getBF16(ctx));
} else {
auto oldEncoding = cast<DotOperandEncodingAttr>(encoding);
- auto newVEncoding = DotOperandEncodingAttr::get(
- ctx, oldEncoding.getOpIdx(), oldEn... | Can we define this inside the if statement below? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,804 | intel | victor-eds | @@ -3,6 +3,10 @@
#include "triton/Dialect/TritonGPU/IR/Attributes.h"
+namespace mlir {
+class ModuleOp;
+} | I'd bet we don't need this |
intel-xpu-backend-for-triton | github_2023 | others | 2,804 | intel | victor-eds | @@ -91,7 +90,30 @@ along the row (resp. col) dimension.
return true;
}
- SmallVector<unsigned> getContigPerThread();
+ SmallVector<unsigned> getContigPerThread() const;
+
+ struct DPASCapability {
+ DPASCapability(unsigned minSGSize) : executionSize(minSGSize) {} | ```suggestion
explicit DPASCapability(unsigned minSGSize) : executionSize(minSGSize) {}
``` |
intel-xpu-backend-for-triton | github_2023 | others | 2,856 | intel | whitneywhtsang | @@ -382,4 +382,35 @@ module attributes {"triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 16
}) : (tensor<32x128xf32, #blocked>) -> tensor<32xf32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>
tt.return
}
+
+ // CHECK: @issue_2762
+ tt.func public @issue_2762(%arg0: !tt.ptr<f32> {tt.divisibili... | There is room of simplification of the lit test. |
intel-xpu-backend-for-triton | github_2023 | others | 2,856 | intel | whitneywhtsang | @@ -382,4 +382,30 @@ module attributes {"triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 16
}) : (tensor<32x128xf32, #blocked>) -> tensor<32xf32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>
tt.return
}
+
+ // CHECK: @issue_2762
+ tt.func public @issue_2762(%arg0: !tt.ptr<f32> {tt.divisibili... | ```suggestion
// CHECK: ttg.convert_layout [[LOAD_RES]] : tensor<1x32x128xf32, [[BLOCKED_LAYOUT1]]> -> tensor<1x32x128xf32, [[BLOCKED_LAYOUT2]]>
``` |
intel-xpu-backend-for-triton | github_2023 | others | 2,847 | intel | pbchekin | @@ -90,11 +90,7 @@ endif()
# Compiler flags
include_directories(${CMAKE_CURRENT_SOURCE_DIR}/include)
if(NOT MSVC)
- if(NOT WIN32)
- set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -D__STDC_FORMAT_MACROS -fPIC")
- else()
- set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -D__STDC_FORMAT_MACROS -Wno-deprecated") | May be this is to support building with llvm on windows? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,786 | intel | etiotto | @@ -50,6 +50,46 @@ buildSubGroupTransposeRegisterBases(int32_t registerSize, int32_t laneSize) {
return bases;
}
+// Return a vector such as:
+// [[0, 1], [0, 2], [0, 4], ..., [0, laneSize / 2], [1, 0], ...,
+// [registerSize / (laneSize * 2), 0]],
+// i.e., mapping registers to lanes till laneSize and performing... | int -> int32_t (consistency) |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,833 | intel | pbchekin | @@ -117,15 +117,8 @@ getValuesFromBlockPointerStruct(Value blockPointerStruct,
blockPointerStruct.getLoc(), blockPointerStruct, rewriter);
assert(elems.size() == 7 &&
"unexpected number of values unpacked from a block pointer");
- BlockPointerValues values{
- .base = elems[6],
- .baseWidt... | This is not readable and maintainable as the previous code. |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,833 | intel | victor-eds | @@ -117,15 +117,13 @@ getValuesFromBlockPointerStruct(Value blockPointerStruct,
blockPointerStruct.getLoc(), blockPointerStruct, rewriter);
assert(elems.size() == 7 &&
"unexpected number of values unpacked from a block pointer");
- BlockPointerValues values{
- .base = elems[6],
- .baseWid... | ```suggestion
BlockPointerValues values{/*base=*/elems[6],
```
And same for other rows. `clang-tidy` likes that better. |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,770 | intel | chengjunlu | @@ -116,12 +116,9 @@ struct FuncOpConversion : public ConvertOpToLLVMPattern<triton::FuncOp> {
newFuncOp.setLinkage(LLVM::Linkage::External);
}
- NamedAttrList attrs;
- attrs.append(TritonGEN::TritonGENDialect::getMaxWorkGroupSizeAttrName(),
- rewriter.getI32ArrayAttr({threadsPerWarp... | I am not sure either the `max_work_group_size` or `reqd_work_group_size` is used in IGC. Only the `reqd_sub_group_size` does matter. |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,770 | intel | whitneywhtsang | @@ -36,6 +36,7 @@ class TritonGENDialectLLVMIRTranslationInterface
NamedAttribute attribute,
LLVM::ModuleTranslation &moduleTranslation) const final {
StringRef attrName = attribute.getName().getValue();
+ // Unsupported attribute name: skip. | remove? |
intel-xpu-backend-for-triton | github_2023 | others | 2,799 | intel | whitneywhtsang | @@ -360,3 +360,38 @@ module attributes {"triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 2 :
tt.return %0 : tensor<128xi32, #sliced1>
}
}
+
+// -----
+
+#blocked = #triton_gpu.blocked<{sizePerThread = [2, 1], threadsPerWarp = [16, 1], warpsPerCTA = [1, 1], order = [0, 1]}>
+#blocked1 = #triton_gpu.blo... | ```suggestion
// CHECK: %{{.*}} = llvm.call spir_funccc @_Z17sub_group_shuffleDhj(%[[VAL_1]]
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,799 | intel | whitneywhtsang | @@ -636,19 +655,41 @@ struct ConvertLayoutOpUsingLinearLayoutsConversion
rewriter.replaceOp(op, result);
}
- SmallVector<Value>
- performSubGroupShuffle(Location loc, ArrayRef<Value> inVals,
- int32_t subGroupSize,
- ConversionPatternRewriter &rewriter) const ... | ```suggestion
// 2. Elements held by a work-item are contiguous rows in the abstract
``` |
intel-xpu-backend-for-triton | github_2023 | others | 2,799 | intel | etiotto | @@ -360,3 +360,38 @@ module attributes {"triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 2 :
tt.return %0 : tensor<128xi32, #sliced1>
}
}
+
+// -----
+
+#blocked = #triton_gpu.blocked<{sizePerThread = [2, 1], threadsPerWarp = [16, 1], warpsPerCTA = [1, 1], order = [0, 1]}>
+#blocked1 = #triton_gpu.blo... | ah would be nice if CHECK-COUNT could work with more than one line (so we could check that a pattern involving more than one line repeats a specified number of times). AFAIK this is not possible though. |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,799 | intel | etiotto | @@ -71,6 +71,29 @@ buildSubGroupShuffleRegisterBases(int32_t registerSize, int32_t laneSize) {
return bases;
}
+// Return a vector such as:
+// [[1, 0], [2, 0], [4, 0], ..., [registerSize / laneSize, 0], [0, 1], ...,
+// [0, laneSize/2]]
+// i.e., mapping registers to registers till registerSize / laneSize (all
+... | [NIT]: int -> int32_t (consistency with surrounding code) |
intel-xpu-backend-for-triton | github_2023 | python | 2,820 | intel | pbchekin | @@ -778,7 +771,6 @@ def get_install_requires():
long_description="",
packages=get_packages(),
entry_points=get_entry_points(),
- install_requires=get_install_requires(), | We use `packaging` in `third_party/intel/backend/driver.py`, so we should either keep the install dependencies for our fork, or get rid of `packaging` in our code. |
intel-xpu-backend-for-triton | github_2023 | python | 2,776 | intel | victor-eds | @@ -1102,7 +1102,11 @@ def kernel(X, Y, OUT, OUT_REF, BLOCK: tl.constexpr):
if is_xpu():
# use cpu result as reference, see https://github.com/llvm/llvm-project/issues/88222
- out_ref = torch.div(x.cpu().to(torch.float64), y.cpu().to(torch.float64)).to(torch.float32).to(device=device)
+ if... | I see. Would it make sense to create a separate test for XPU to avoid computing `out_ref` in the first place in the device? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,776 | intel | etiotto | @@ -1420,6 +1420,33 @@ struct MulhiUIOpConversion
const TargetInfoBase &targetInfo;
};
+struct PreciseSqrtOpConversion
+ : ElementwiseOpConversionBase<PreciseSqrtOp, PreciseSqrtOpConversion> {
+ using Base =
+ ElementwiseOpConversionBase<PreciseSqrtOp, PreciseSqrtOpConversion>;
+ using Base::Base;
+ us... | auto? what is the type ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,785 | intel | whitneywhtsang | @@ -204,12 +204,27 @@ SmallVector<unsigned> getUniqueContigPerThread(Attribute layout,
}
return ret;
}
-
-SmallVector<unsigned> getShapePerCTATile(Attribute layout,
- ArrayRef<int64_t> tensorShape) {
+SmallVector<unsigned> getShapePerCTATile(Attribute layout) {
if (auto... | Please create an issue to track this. |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,732 | intel | victor-eds | @@ -68,6 +68,10 @@ struct ConvertTritonGPUToLLVM
: public triton::gpu::intel::impl::ConvertTritonIntelGPUToLLVMBase<
ConvertTritonGPUToLLVM> {
using ConvertTritonIntelGPUToLLVMBase::ConvertTritonIntelGPUToLLVMBase;
+ ConvertTritonGPUToLLVM() = default;
+ ConvertTritonGPUToLLVM(bool advancedPath) {
... | ```suggestion
ConvertTritonGPUToLLVM(bool advancedPath)
: advancedPath(advancedPath) {}
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,732 | intel | etiotto | @@ -180,14 +180,8 @@ struct AddSPIRVEnvPattern : public mlir::OpRewritePattern<ModuleOp> {
/// block pointers or not.
class TritonGPUToLLVMPipelineManager {
public:
- TritonGPUToLLVMPipelineManager(ModuleOp &mod, MLIRContext *ctx)
- : mod(mod), ctx(ctx),
- isAdvancedPathEnabled(
- mod->hasAtt... | When `advance == true` please assert that the module has the attributes for 2D load/stores and the attribute indication the dpas instruction is available. |
intel-xpu-backend-for-triton | github_2023 | python | 2,732 | intel | whitneywhtsang | @@ -56,6 +56,7 @@ class XPUOptions:
backend_name: str = 'intel'
sanitize_overflow: bool = False
generate_native_code: bool = False
+ advanced_path: bool = False | let's put it in alphabetical order. |
intel-xpu-backend-for-triton | github_2023 | python | 2,732 | intel | whitneywhtsang | @@ -214,6 +214,7 @@ def forward(q, k, v, causal, sm_scale):
num_warps=num_warps, #
num_stages=num_stages, #
grf_mode='large', #
+ advanced_path=True, # | Let's not enable it in this PR until we disable features like fast math by default? |
intel-xpu-backend-for-triton | github_2023 | python | 2,732 | intel | whitneywhtsang | @@ -232,8 +233,9 @@ def make_ttgir(mod, metadata, opt, properties):
pm = ir.pass_manager(mod.context)
pm.enable_debug()
- if (properties["has_subgroup_2d_block_io"] and properties["has_subgroup_matrix_multiply_accumulate"]
- and os.getenv("TRITON_INTEL_ADVANCED_PATH", "0") == "... | Do we need to worry that with this change, we need different source code for different platforms? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,766 | intel | jopperm | @@ -341,38 +341,44 @@ LinearLayout combineCtaCgaWithShape(LinearLayout ctaLayout,
} // anonymous namespace
+// clang-format off
// The layout example repeat_count=8, systolic_depth=8,
// execution_size=16 and operands_per_chan=2 for warp size 32.
// For A operand:
-// systolic depth = 8
-//<--... | I think it must be
```suggestion
// Lane: {{0,1}, {0,2}, {0,4}, {0,8}, {1,0}}
```
to match the illustration above. |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,766 | intel | whitneywhtsang | @@ -3217,6 +3213,10 @@ std::string getDistributedLayoutStr(RankedTensorType tensorType,
int64_t tensorSize = product(tensorType.getShape());
std::vector<std::string> elementMapping(tensorSize);
std::vector<std::string> threadMapping;
+ unsigned threadsPerWarp = ll->getInDimSize(kLane); | Merging in https://github.com/intel/intel-xpu-backend-for-triton/pull/2783. |
intel-xpu-backend-for-triton | github_2023 | others | 2,478 | intel | victor-eds | @@ -8,34 +8,46 @@ endif()
include(ExternalProject)
-set(CMAKE_CXX_STANDARD 17)
-
set(CMAKE_INCLUDE_CURRENT_DIR ON)
project(triton)
include(CTest)
-if(NOT WIN32)
- list(APPEND CMAKE_MODULE_PATH "${CMAKE_CURRENT_SOURCE_DIR}/cmake")
-endif()
-
-
+list(APPEND CMAKE_MODULE_PATH "${CMAKE_CURRENT_SOURCE_DIR}/cmak... | Why different options? |
intel-xpu-backend-for-triton | github_2023 | others | 2,478 | intel | victor-eds | @@ -53,7 +65,15 @@ endif()
# Compiler flags
include_directories(${CMAKE_CURRENT_SOURCE_DIR}/include)
-set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -D__STDC_FORMAT_MACROS -fPIC -std=gnu++17")
+if(NOT MSVC)
+ if(NOT WIN32)
+ set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -D__STDC_FORMAT_MACROS -fPIC -std=gnu++17")
+ else(... | Wouldn't the `-std=*` be set by the `CMAKE_CXX_STANDARD`? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,478 | intel | victor-eds | @@ -16,10 +16,11 @@
#include "triton/Dialect/TritonGPU/IR/Dialect.h"
#include "triton/Dialect/TritonNvidiaGPU/IR/Dialect.h"
-// Below headers will allow registration to ROCm passes | Keep comment. Also, why do we need to drop AMD support? |
intel-xpu-backend-for-triton | github_2023 | python | 2,478 | intel | anmyachev | @@ -2734,9 +2734,10 @@ def test_reduce_layouts(M, N, src_layout, axis, epilogue_kind, dtype_str, reduce
}}) {{axis = {axis} : i32}} : (tensor<{M}x{N}x{ty}, #src>) -> tensor<{rdims_1d}x{ty}, #{GPU_DIALECT}.slice<{{dim = {axis}, parent = #src}}>>
""" + epilogue
- with tempfile.NamedTemporaryFile(mode='... | Why is it necessary only in this case? |
intel-xpu-backend-for-triton | github_2023 | python | 2,478 | intel | anmyachev | @@ -2600,7 +2600,7 @@ def test_scan_layouts(M, N, src_layout, axis, device):
}}
"""
- with tempfile.NamedTemporaryFile(mode='w', suffix='.ttgir') as f:
+ with tempfile.NamedTemporaryFile(mode='w', suffix='.ttgir', delete=False) as f: | Why is `delete=False` option used? |
intel-xpu-backend-for-triton | github_2023 | python | 2,478 | intel | anmyachev | @@ -140,6 +140,8 @@ def test_print(func: str, data_type: str, device: str):
func != "print_multiple_args" and func != "device_print_multiple_args" and \
func != "device_print_pointer" and func != "device_print_scalar":
assert_close(y, x)
+ if torch.cuda.is_available():
+ torch.cuda.sy... | I don't think it's necessary since there is synchronization on 148 line.
```suggestion
``` |
intel-xpu-backend-for-triton | github_2023 | python | 2,478 | intel | anmyachev | @@ -15,7 +15,7 @@ def triton_():
@pytest.mark.skipif(not torch.cuda.is_available(), reason="requires cuda")
def test_reproducer():
- tmpdir = ".tmp"
+ tmpdir = os.path.abspath(".tmp") | Why? |
intel-xpu-backend-for-triton | github_2023 | python | 2,478 | intel | anmyachev | @@ -154,7 +155,8 @@ def kernel():
try:
inner = e.value.__cause__
outer = e.value
- assert "/core.py" in '\n'.join(traceback.format_tb(inner.__traceback__)), "error should point inside core.py"
+ target = "\\core.py" if platform.system() == 'Windows' else "/core.py"
+ assert t... | Maybe use `os.path.sep`? It will be easier to upstream. |
intel-xpu-backend-for-triton | github_2023 | python | 2,478 | intel | anmyachev | @@ -176,8 +176,9 @@ def triton_key():
contents += [hashlib.sha256(f.read()).hexdigest()]
# backend
- libtriton_hash = hashlib.sha256()
- with open(os.path.join(TRITON_PATH, "_C/libtriton.so"), "rb") as f:
+ libtriton_hash = hashlib.sha1() | Why did you change the algorithm? |
intel-xpu-backend-for-triton | github_2023 | python | 2,478 | intel | anmyachev | @@ -176,8 +176,9 @@ def triton_key():
contents += [hashlib.sha256(f.read()).hexdigest()]
# backend
- libtriton_hash = hashlib.sha256()
- with open(os.path.join(TRITON_PATH, "_C/libtriton.so"), "rb") as f:
+ libtriton_hash = hashlib.sha1()
+ ext = "so" if os.name != "nt" else "pyd" | ?
```suggestion
ext = sysconfig.get_config_var('EXT_SUFFIX')
``` |
intel-xpu-backend-for-triton | github_2023 | python | 2,478 | intel | anmyachev | @@ -104,7 +108,8 @@ def include_dir(self) -> list[str]:
def compile_module_from_src(src, name):
key = hashlib.sha256(src.encode("utf-8")).hexdigest()
cache = get_cache_manager(key)
- cache_path = cache.get_file(f"{name}.so")
+ file_name = name + (".pyd" if os.name == "nt" else ".so") | ?
```suggestion
file_name = f"{name}{sysconfig.get_config_var('EXT_SUFFIX')}"
``` |
intel-xpu-backend-for-triton | github_2023 | python | 2,478 | intel | anmyachev | @@ -53,7 +53,7 @@ def test_print(func_type: str, data_type: str, device: str):
assert proc.stderr == b''
return
- outs = [line for line in proc.stdout.decode("UTF-8").split("\n") if line]
+ outs = [line for line in proc.stdout.decode("UTF-8").replace('\r', '').split("\n") if line] | ?
```suggestion
outs = [line for line in proc.stdout.decode("UTF-8").splitlines() if line]
``` |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.