repo_name stringlengths 1 62 | dataset stringclasses 1
value | lang stringclasses 11
values | pr_id int64 1 20.1k | owner stringlengths 2 34 | reviewer stringlengths 2 39 | diff_hunk stringlengths 15 262k | code_review_comment stringlengths 1 99.6k |
|---|---|---|---|---|---|---|---|
intel-xpu-backend-for-triton | github_2023 | python | 2,478 | intel | anmyachev | @@ -25,13 +25,17 @@ def __init__(self, target: GPUTarget) -> None:
@staticmethod
def _path_to_binary(binary: str):
+ binary += ".exe" if os.name == "nt" else "" | ?
```suggestion
binary += sysconfig.get_config_var("EXE") or ""
``` |
intel-xpu-backend-for-triton | github_2023 | c | 2,478 | intel | anmyachev | @@ -137,7 +137,15 @@ static PyObject *loadBinary(PyObject *self, PyObject *args) {
const size_t binary_size = PyBytes_Size(py_bytes);
uint8_t *binary_ptr = (uint8_t *)PyBytes_AsString(py_bytes);
- const auto ctx = sycl_device.get_platform().ext_oneapi_get_default_context();
+ auto platform = sycl_device.get_p... | Looks like a development-friendly code. Will it stay that way? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,478 | intel | anmyachev | @@ -3,6 +3,7 @@
#include <memory>
#include <optional>
+#include <string> | In the upstream: https://github.com/triton-lang/triton/commit/d1958329c9c531d33b4933e9bfcdbc4b15ab4ed0 |
intel-xpu-backend-for-triton | github_2023 | python | 2,478 | intel | anmyachev | @@ -280,18 +320,18 @@ def download_and_copy(name, src_path, dst_path, variable, version, url_func):
return
base_dir = os.path.dirname(__file__)
system = platform.system()
- try:
- arch = {"x86_64": "64", "arm64": "aarch64", "aarch64": "aarch64"}[platform.machine()]
- except KeyError:
- ... | In the upstream: https://github.com/triton-lang/triton/commit/bce48c82f3a8586e2f35b51d1afbcfe72a3fbbcd |
intel-xpu-backend-for-triton | github_2023 | others | 2,478 | intel | anmyachev | @@ -79,6 +79,7 @@ mlir_check_all_link_libraries(triton-lsp)
add_llvm_executable(triton-llvm-opt
+ PARTIAL_SOURCES_INTENDED | On line 85 it is already used, is that enough?
```suggestion
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,478 | intel | anmyachev | @@ -44,6 +44,16 @@ void dumpMatrix(uint64_t *m, int numRows, int numCols) {
}
}
+static inline uint32_t countTrailingZeros(uint32_t x) {
+#ifdef _MSC_VER
+ unsigned long index;
+ _BitScanForward(&index, x); | In the upstream: https://github.com/triton-lang/triton/commit/9d424e02ed4db695cc58baf939ec75ed0f0bc5b1 |
intel-xpu-backend-for-triton | github_2023 | python | 2,478 | intel | anmyachev | @@ -103,6 +103,49 @@ def copy_externals():
]
+def find_vswhere():
+ program_files = os.environ.get("ProgramFiles(x86)", "C:\\Program Files (x86)")
+ vswhere_path = Path(program_files) / "Microsoft Visual Studio" / "Installer" / "vswhere.exe"
+ if vswhere_path.exists():
+ return vswhere_path... | A safer option.
?
```suggestion
command = ["call", vcvarsall_path, arch, "&&", "set"]
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,478 | intel | anmyachev | @@ -4,21 +4,26 @@
namespace py = pybind11;
+#define EXPAND(x) x | Have you tried using `/Zc:preprocessor` or `/experimental:preprocessor` options to avoid using this workaround for MSVC compiler? Ref: https://stackoverflow.com/a/5134656/21672583 |
intel-xpu-backend-for-triton | github_2023 | others | 2,478 | intel | whitneywhtsang | @@ -53,7 +65,15 @@ endif()
# Compiler flags
include_directories(${CMAKE_CURRENT_SOURCE_DIR}/include)
-set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -D__STDC_FORMAT_MACROS -fPIC -std=gnu++17")
+if(NOT MSVC)
+ if(NOT WIN32)
+ set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -D__STDC_FORMAT_MACROS -fPIC") | Why `-std=gnu++17` is removed? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,478 | intel | anmyachev | @@ -4,6 +4,8 @@
#include <stdlib.h>
#if defined(_MSC_VER)
+#include <xmmintrin.h> // For _mm_prefetch
+#define __builtin_prefetch(addr) _mm_prefetch(reinterpret_cast<const char *>(addr), _MM_HINT_T0) | There is no longer a need to have it because all built-in use is under this `#if defined(__GNUC__)` guard. Fixed in https://github.com/triton-lang/triton/pull/4416. |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,478 | intel | etiotto | @@ -17,9 +17,11 @@
#include "triton/Dialect/TritonNvidiaGPU/IR/Dialect.h"
// Below headers will allow registration to ROCm passes
+#ifndef WIN32 | Remove the ifndef, ideally, we should be able to compile these header files |
intel-xpu-backend-for-triton | github_2023 | python | 2,478 | intel | etiotto | @@ -167,7 +210,7 @@ def get_json_package_info():
def get_llvm_package_info():
system = platform.system()
try:
- arch = {"x86_64": "x64", "arm64": "arm64", "aarch64": "arm64"}[platform.machine()]
+ arch = {"x86_64": "x64", "AMD64": "64", "arm64": "arm64", "aarch64": "arm64"}[platform.machine()] | Why do we need to add "AMD64" ? |
intel-xpu-backend-for-triton | github_2023 | python | 2,478 | intel | etiotto | @@ -430,9 +483,8 @@ def build_extension(self, ext):
build_args = ["--config", cfg]
if platform.system() == "Windows":
+ cmake_args += ["-DCMAKE_BUILD_TYPE=" + cfg]
cmake_args += [f"-DCMAKE_RUNTIME_OUTPUT_DIRECTORY_{cfg.upper()}={extdir}"]
- if sys.maxsize > 2**32: | So the upstream code already has some windows support ? Why do we need to change this code ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,478 | intel | etiotto | @@ -14,55 +15,46 @@ enum class MemSemantic { ACQUIRE_RELEASE, ACQUIRE, RELEASE, RELAXED };
enum class RMWOp { ADD, FADD, AND, OR, XOR, XCHG, MAX, MIN, UMIN, UMAX };
std::map<MemSemantic, int> mem_semantic_map = {
- {MemSemantic::ACQUIRE_RELEASE, __ATOMIC_ACQ_REL},
- {MemSemantic::ACQUIRE, __ATOMIC_ACQUIRE},
-... | Why is this changer required ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,478 | intel | etiotto | @@ -75,6 +75,7 @@ inline void registerTritonDialects(mlir::DialectRegistry ®istry) {
mlir::triton::registerConvertTritonGENToLLVM();
mlir::triton::registerTritonGENToLLVMPasses();
+#ifndef WIN32 | I am guessing on windows these AMD passes do not compile and that is the reason they are #ifdef out ?
|
intel-xpu-backend-for-triton | github_2023 | others | 2,478 | intel | victor-eds | @@ -8,34 +8,46 @@ endif()
include(ExternalProject)
-set(CMAKE_CXX_STANDARD 17)
-
set(CMAKE_INCLUDE_CURRENT_DIR ON)
project(triton)
include(CTest)
-if(NOT WIN32)
- list(APPEND CMAKE_MODULE_PATH "${CMAKE_CURRENT_SOURCE_DIR}/cmake")
-endif()
-
-
+list(APPEND CMAKE_MODULE_PATH "${CMAKE_CURRENT_SOURCE_DIR}/cmak... | Why did we need C++ 20 in Windows? |
intel-xpu-backend-for-triton | github_2023 | python | 2,478 | intel | victor-eds | @@ -103,6 +103,49 @@ def copy_externals():
]
+def find_vswhere():
+ program_files = os.environ.get("ProgramFiles(x86)", "C:\\Program Files (x86)")
+ vswhere_path = Path(program_files) / "Microsoft Visual Studio" / "Installer" / "vswhere.exe"
+ if vswhere_path.exists():
+ return vswhere_path... | So we do not support VS installed in a different path? |
intel-xpu-backend-for-triton | github_2023 | python | 2,478 | intel | victor-eds | @@ -401,6 +444,12 @@ def get_proton_cmake_args(self):
def build_extension(self, ext):
lit_dir = shutil.which('lit')
ninja_dir = shutil.which('ninja')
+ if platform.system() == "Windows":
+ vs_path = find_visual_studio(["[17.0,18.0)", "[16.0,17.0)"])
+ env = set_env_va... | Do we wanna keep this print? |
intel-xpu-backend-for-triton | github_2023 | others | 2,478 | intel | anmyachev | @@ -57,6 +60,10 @@ cuobjdump
nvdisasm
ptxas
+cuobjdump.exe
+nvdisasm.exe
+ptxas.exe
+ | This is not needed since `dst_path` as not having the file extension when we call `download_and_copy`.
```suggestion
``` |
intel-xpu-backend-for-triton | github_2023 | python | 2,478 | intel | anmyachev | @@ -153,7 +153,7 @@ def triton_key():
# backend
libtriton_hash = hashlib.sha256()
ext = sysconfig.get_config_var("EXT_SUFFIX").split(".")[-1]
- with open(os.path.join(TRITON_PATH, f"_C/libtriton.{ext}"), "rb") as f:
+ with open(os.path.join(TRITON_PATH, "_C", f"libtriton.{ext}"), "rb") as f: | ```suggestion
with open(os.path.join(TRITON_PATH, f"_C/libtriton.{ext}"), "rb") as f:
``` |
intel-xpu-backend-for-triton | github_2023 | python | 2,478 | intel | anmyachev | @@ -369,6 +374,12 @@ def make_cubin(src, metadata, opt, capability):
cubin = f.read()
if os.path.exists(fbin):
os.remove(fbin)
+
+ if os.path.exists(fsrc.name):
+ os.remove(fsrc.name)
+ if os.path.exists(flog.name):
+ os.remove(flog.name... | This has been moved to `352` line, can be deleted. |
intel-xpu-backend-for-triton | github_2023 | python | 2,478 | intel | anmyachev | @@ -103,6 +103,49 @@ def copy_externals():
]
+def find_vswhere():
+ program_files = os.environ.get("ProgramFiles(x86)", "C:\\Program Files (x86)")
+ vswhere_path = Path(program_files) / "Microsoft Visual Studio" / "Installer" / "vswhere.exe"
+ if vswhere_path.exists():
+ return vswhere_path... | Could we reuse code from `CLFinder.py`? |
intel-xpu-backend-for-triton | github_2023 | python | 2,478 | intel | anmyachev | @@ -431,6 +483,7 @@ def build_extension(self, ext):
cmake_args += [f"-DCMAKE_BUILD_TYPE={cfg}"]
if platform.system() == "Windows":
+ cmake_args += ["-DCMAKE_BUILD_TYPE=" + cfg] | Already in `484` line.
```suggestion
``` |
intel-xpu-backend-for-triton | github_2023 | python | 2,478 | intel | anmyachev | @@ -103,6 +103,49 @@ def copy_externals():
]
+def find_vswhere():
+ program_files = os.environ.get("ProgramFiles(x86)", "C:\\Program Files (x86)")
+ vswhere_path = Path(program_files) / "Microsoft Visual Studio" / "Installer" / "vswhere.exe"
+ if vswhere_path.exists():
+ return vswhere_path... | For me it works only if I specify `-products`:
`"C:\Program Files (x86)\Microsoft Visual Studio\Installer\vswhere.exe" -version "[17.0,18.0)" -products Microsoft.VisualStudio.Product.BuildTools -requires Microsoft.VisualStudio.Component.VC.Tools.x86.x64 -property installationPath -prerelease`
@gshimansky do you kno... |
intel-xpu-backend-for-triton | github_2023 | c | 2,478 | intel | anmyachev | @@ -161,6 +170,27 @@ typedef CUresult (*cuTensorMapEncodeTiled_t)(
CUtensorMapSwizzle swizzle, CUtensorMapL2promotion l2Promotion,
CUtensorMapFloatOOBfill oobFill);
+#ifdef WIN32
+#define defineGetFunctionHandle(name, symbolName) \
+ static symbolName##_t name() { ... | Should we explicitly clear any existing error on Windows as well?
```suggestion
} \
/* Clear any existing error */ \
SetLastError(NO_ERROR); ... |
intel-xpu-backend-for-triton | github_2023 | python | 2,478 | intel | anmyachev | @@ -231,13 +232,17 @@ def __init__(self, target: GPUTarget) -> None:
@staticmethod
def _path_to_binary(binary: str):
+ binary += sysconfig.get_config_var("EXE") | Done in https://github.com/intel/intel-xpu-backend-for-triton/commit/94684d326723b67b146f23f342623ea058a32098 |
intel-xpu-backend-for-triton | github_2023 | c | 2,478 | intel | anmyachev | @@ -1,8 +1,17 @@
#include "cuda.h"
+#ifdef WIN32
+#define WIN32_LEAN_AND_MEAN
+#define NOMINMAX
+#include <windows.h>
+#else
#include <dlfcn.h>
+#endif
#include <stdbool.h>
#define PY_SSIZE_T_CLEAN
#include <Python.h>
+#ifndef WIN32
+#include <stdatomic.h>
+#endif | This is no longer necessary.
```suggestion
``` |
intel-xpu-backend-for-triton | github_2023 | python | 2,478 | intel | anmyachev | @@ -372,6 +372,7 @@ def make_cubin(src, metadata, opt, capability):
cubin = f.read()
if os.path.exists(fbin):
os.remove(fbin)
+ | ```suggestion
``` |
intel-xpu-backend-for-triton | github_2023 | c | 2,478 | intel | anmyachev | @@ -194,8 +194,18 @@ static PyObject *loadBinary(PyObject *self, PyObject *args) {
const size_t binary_size = PyBytes_Size(py_bytes);
uint8_t *binary_ptr = (uint8_t *)PyBytes_AsString(py_bytes);
- const auto ctx =
- sycl_device.get_platform().ext_oneapi_get_default_context(); | Could we make this available on Windows using `set SYCL_ENABLE_DEFAULT_CONTEXTS=1`: https://github.com/intel/llvm/blob/7dd09d9effd6a56d2c0c7abca38b21baa4d77fc8/sycl/doc/EnvironmentVariables.md?plain=1#L22? |
intel-xpu-backend-for-triton | github_2023 | c | 2,478 | intel | etiotto | @@ -194,8 +194,18 @@ static PyObject *loadBinary(PyObject *self, PyObject *args) {
const size_t binary_size = PyBytes_Size(py_bytes);
uint8_t *binary_ptr = (uint8_t *)PyBytes_AsString(py_bytes);
- const auto ctx =
- sycl_device.get_platform().ext_oneapi_get_default_context();
+ auto platform = ... | This is iffy. If the exception is thrown `ctx` will be uninitialized when used at line 212. Is there another API to use on Windows to get the context ? |
intel-xpu-backend-for-triton | github_2023 | python | 2,478 | intel | anmyachev | @@ -401,6 +444,11 @@ def get_proton_cmake_args(self):
def build_extension(self, ext):
lit_dir = shutil.which('lit')
ninja_dir = shutil.which('ninja')
+ if platform.system() == "Windows":
+ vs_path = find_visual_studio(["[17.0,18.0)", "[16.0,17.0)"])
+ env = set_env_va... | It's probably a good idea to define `initialize_visual_studio_env` as in `CLFinder.py` file here as well.
```suggestion
if not vs_path:
raise EnvironmentError("Visual Studio 2019 or 2022 not found.")
env = set_env_vars(vs_path)
``` |
intel-xpu-backend-for-triton | github_2023 | python | 2,478 | intel | anmyachev | @@ -0,0 +1,55 @@
+import os
+import subprocess
+from pathlib import Path
+
+
+def find_vswhere():
+ program_files = os.environ.get("ProgramFiles(x86)", "C:\\Program Files (x86)")
+ vswhere_path = Path(program_files) / "Microsoft Visual Studio" / "Installer" / "vswhere.exe"
+ if vswhere_path.exists():
+ ... | At this point `vcvarsall.bat` has not yet been called? This will only happen when calling `set_env_vars` function IIUC. |
intel-xpu-backend-for-triton | github_2023 | others | 2,478 | intel | anmyachev | @@ -49,10 +50,21 @@ endif()
# used conditionally in this file and by lit tests
# Customized release build type with assertions: TritonRelBuildWithAsserts
-set(CMAKE_C_FLAGS_TRITONRELBUILDWITHASSERTS "-O2 -g")
-set(CMAKE_CXX_FLAGS_TRITONRELBUILDWITHASSERTS "-O2 -g")
-set(CMAKE_C_FLAGS_TRITONBUILDWITHO1 "-O1")
-set(C... | @gshimansky these flags are for debug build, aren't?
```suggestion
set(CMAKE_C_FLAGS_TRITONRELBUILDWITHASSERTS "/Zi /RTC1 /bigobj /Zc:preprocessor")
set(CMAKE_CXX_FLAGS_TRITONRELBUILDWITHASSERTS "/Zi /RTC1 /bigobj /Zc:preprocessor")
``` |
intel-xpu-backend-for-triton | github_2023 | others | 2,756 | intel | mfrancepillois | @@ -314,46 +314,97 @@ def TritonGEN_Matrix2DBlockPrefetchOp : TritonGEN_Op<"2Dblockprefetch">,
let hasVerifier = 1;
}
-def TritonGEN_SIMDBlockReadOp: TritonGEN_Op<"simdblockread">,
- Results<(outs FixedVectorOf<[AnyTypeOf<[AnyI8, AnyI16, AnyI32, AnyI64]>]>:$res)>,
- Arguments<(ins
- Arg<LLVM_AnyPointer, "", ... | Nit: Perhaps you could mention that the subgroup size is 128 in this example. |
intel-xpu-backend-for-triton | github_2023 | python | 2,744 | intel | pbchekin | @@ -103,6 +103,49 @@ def copy_externals():
]
+def find_vswhere():
+ program_files = os.environ.get("ProgramFiles(x86)", "C:\\Program Files (x86)")
+ vswhere_path = Path(program_files) / "Microsoft Visual Studio" / "Installer" / "vswhere.exe"
+ if vswhere_path.exists():
+ return vswhere_path... | The case when vs_path is None is not handled. |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,760 | intel | victor-eds | @@ -148,6 +148,12 @@ struct CoalescePass
if (op->getNumResults() == 0 && op->getNumRegions() == 0)
return true;
+ // Operations that do not consume a block pointer aren't interesting.
+ if (llvm::none_of(op->getOperandTypes(), [](Type resType) {
+ return tt::isTensorPointerType(resType);
+ ... | ```suggestion
// Operations that do not consume a block pointer aren't interesting.
if (llvm::none_of(op->getOperandTypes(), tt::isTensorPointerType))
return true;
```
NIT |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,760 | intel | victor-eds | @@ -367,8 +373,7 @@ struct CoalescePass
});
LLVM_DEBUG({
- DBGS() << "\nlayoutMap:"
- << "\n";
+ DBGS() << "\nlayoutMap:" << "\n"; | ```suggestion
DBGS() << "\nlayoutMap:\n";
```
NIT |
intel-xpu-backend-for-triton | github_2023 | c | 2,742 | intel | alexbaden | @@ -194,8 +194,18 @@ static PyObject *loadBinary(PyObject *self, PyObject *args) {
const size_t binary_size = PyBytes_Size(py_bytes);
uint8_t *binary_ptr = (uint8_t *)PyBytes_AsString(py_bytes);
- const auto ctx =
- sycl_device.get_platform().ext_oneapi_get_default_context();
+ auto platform = ... | We already have exceptions in this code block - but I suppose I might feel better if this was in a free function that had compile time definitions for windows (where we need the exception handling) and linux (where we don't).
Also, how can the code properly run with no valid context? What if a valid context is thro... |
intel-xpu-backend-for-triton | github_2023 | python | 2,717 | intel | anmyachev | @@ -128,6 +128,7 @@ def forward(ctx, a, b, c, acc_dtype=None):
[512, 32768, 8192],
[1024, 28672, 8192],
[3072, 4096, 3072],
+ [4096, 4096, 4096], | Adding a new combination breaks the CI and seems a bit out of topic for this pull request. Maybe we should move this change to a separate pull request? |
intel-xpu-backend-for-triton | github_2023 | python | 2,681 | intel | etiotto | @@ -266,9 +268,12 @@ def compile(src, target=None, options=None):
# when the source is an IR file, don't apply the passes related to this stage. This makes it easier to write IR level tests.
if ir_source:
first_stage += 1
- context = ir.context()
- ir.load_dialects(context)
- backend.load_di... | This is different from upstream code:
The "else" part is missing.... perhaps it belongs to a more recent upstream commit than the one we are trying to merge ?
Also, would adding the else part eliminate the need to add l... |
intel-xpu-backend-for-triton | github_2023 | python | 2,681 | intel | whitneywhtsang | @@ -107,28 +91,44 @@ def parse_options(self):
class IRSource:
- def __init__(self, path):
+ def __init__(self, path, context):
self.path = path
path = Path(path)
self.ext = path.suffix[1:]
self.src = path.read_text()
- match = re.search(prototype_pattern[self.ext], ... | Why DPAS layout requires additional dialects while MMA layout doesn't? |
intel-xpu-backend-for-triton | github_2023 | python | 2,505 | intel | anmyachev | @@ -131,20 +131,15 @@ def test_print(func: str, data_type: str, device: str):
else:
assert f"Unknown kernel: {func}"
- if device == "xpu":
- # FIXME: remove trigger to get output from kernel
- repr(x)
- repr(y)
+ # Wait until driver complete all the jobs for the device_print, ... | Is it necessary to move this? |
intel-xpu-backend-for-triton | github_2023 | others | 2,505 | intel | anmyachev | @@ -1,9 +0,0 @@
-# https://github.com/intel/intel-xpu-backend-for-triton/issues/800
-test/unit/language/test_subprocess.py::test_print[device_print-float16]
-test/unit/language/test_subprocess.py::test_print[device_print-float32]
-test/unit/language/test_subprocess.py::test_print[device_print-float64]
-test/unit/langua... | To make sure it works, you need to run corresponding workflow separately. |
intel-xpu-backend-for-triton | github_2023 | others | 2,683 | intel | FMarno | @@ -1045,7 +1045,6 @@ module attributes {"triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 4 :
// -----
module attributes {"triton_gpu.target" = "xpu", "triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 4 : i32} {
- // CHECK: llvm.func spir_funccc @_Z7barrierj(i32) attributes {convergent, no_unwind,... | should there be a replacement function declaration? |
intel-xpu-backend-for-triton | github_2023 | python | 2,609 | intel | pbchekin | @@ -28,146 +29,147 @@ def test_profile():
pathlib.Path("test.hatchet").unlink()
-def test_profile_decorator():
- f = tempfile.NamedTemporaryFile(delete=True)
- name = f.name.split(".")[0]
+def test_profile_decorator(tmp_path):
+ temp_file = tmp_path / "test_profile_decorator.hatchet"
- @proton.pr... | Do we need this unlink? The whole `tmp_path` should be deleted on exit. |
intel-xpu-backend-for-triton | github_2023 | others | 2,614 | intel | pbchekin | @@ -121,7 +125,7 @@ jobs:
python ../../scripts/build_report.py $REPORTS/softmax-performance.csv $REPORTS/softmax-xetla-report.csv --benchmark softmax --compiler xetla --param_cols "N" --tflops_col XeTLA-TFlops --hbm_col "XeTLA-GB/s" --tag $TAG
- name: Run Triton GEMM kernel benchmark
- if: ${... | `contains(inputs.skip_benchmarks, 'gemm_benchmark.py')` returns true if the skip list contains `gemm_benchmark.py_default` or `gemm_benchmark.py_advanced`. Is it expected? |
intel-xpu-backend-for-triton | github_2023 | others | 2,614 | intel | pbchekin | @@ -112,7 +116,7 @@ jobs:
python setup.py install
- name: Run Triton Softmax kernel benchmark
- if: ${{ steps.install.outcome == 'success' && !cancelled() }}
+ if: ${{ steps.install.outcome == 'success' && !cancelled() && !contains(fromJson(inputs.skip_benchmarks), 'fused_softmax.py') ... | Note that `inputs` are null when the workflow is triggered by cron. You probably need something like this:
```suggestion
if: ${{ steps.install.outcome == 'success' && !cancelled() && !contains(fromJson(inputs.skip_benchmarks || '[]'), 'fused_softmax.py') }}
``` |
intel-xpu-backend-for-triton | github_2023 | others | 2,614 | intel | pbchekin | @@ -24,6 +24,10 @@ on:
description: Run name
type: string
default: "Triton benchmarks"
+ skip_benchmarks:
+ description: List of benchmarks to skip | Let's make it clear it need to be a valid JSON list?
```suggestion
description: JSON list of benchmarks to skip
``` |
intel-xpu-backend-for-triton | github_2023 | others | 2,614 | intel | pbchekin | @@ -24,6 +24,10 @@ on:
description: Run name
type: string
default: "Triton benchmarks"
+ skip_benchmarks:
+ description: List of benchmarks to skip
+ type: string
+ default: "" | ```suggestion
default: "[]"
``` |
intel-xpu-backend-for-triton | github_2023 | others | 2,614 | intel | pbchekin | @@ -132,7 +136,7 @@ jobs:
python ../../scripts/build_report.py $REPORTS/matmul-performance-base.csv $REPORTS/gemm-xetla-report.csv --benchmark gemm --compiler xetla --param_cols "B,M,K,N" --tflops_col XeTLA-TFlops --hbm_col "XeTLA-GB/s" --tag $TAG
- name: Run Triton GEMM kernel benchmark - default p... | ```suggestion
if: ${{ steps.install.outcome == 'success' && !cancelled() && !contains(fromJson(inputs.skip_benchmarks || '[]'), 'gemm_benchmark.py_default') }}
``` |
intel-xpu-backend-for-triton | github_2023 | others | 2,631 | intel | etiotto | @@ -365,4 +365,46 @@ tt.func @test(%arg0: tensor<32x32xf32, #mma>) -> tensor<32xf32, #triton_gpu.slic
"mlir::triton::gpu::TritonGPUDialect"];
}
+def TritonIntelGPUOptimizeElementwiseParallelism
+ : Pass<"tritonintelgpu-optimize-elementwise-parallelism", "mlir::ModuleOp"> {
+ let summa... | "is not too high according to some heuristics" -> "is heuristically estimated to be sufficiently low" |
intel-xpu-backend-for-triton | github_2023 | others | 2,631 | intel | etiotto | @@ -0,0 +1,67 @@
+// RUN: triton-opt %s --split-input-file -tritonintelgpu-optimize-elementwise-parallelism | FileCheck %s
+
+#blocked = #triton_gpu.blocked<{sizePerThread = [1, 16], threadsPerWarp = [16, 1], warpsPerCTA = [1, 1], order = [0, 1]}>
+#blocked1 = #triton_gpu.blocked<{sizePerThread = [16, 1], threadsPerWar... | [nit]: Call it ATTR_0, ATTR_1 like in the first test. Same for other tests. |
intel-xpu-backend-for-triton | github_2023 | others | 2,631 | intel | etiotto | @@ -0,0 +1,67 @@
+// RUN: triton-opt %s --split-input-file -tritonintelgpu-optimize-elementwise-parallelism | FileCheck %s
+
+#blocked = #triton_gpu.blocked<{sizePerThread = [1, 16], threadsPerWarp = [16, 1], warpsPerCTA = [1, 1], order = [0, 1]}>
+#blocked1 = #triton_gpu.blocked<{sizePerThread = [16, 1], threadsPerWar... | The original code and the transformed code both contain 1 convert layout operation. What makes the transformed code "cheaper" ? |
intel-xpu-backend-for-triton | github_2023 | others | 2,628 | intel | whitneywhtsang | @@ -204,22 +204,7 @@ module attributes {"triton_gpu.num-warps" = 1 : i32, "triton_gpu.threads-per-war
%c0_i32 = arith.constant 0 : i32
%c32_i64 = arith.constant 32 : i64
%21 = tt.make_tensor_ptr %arg0, [%c64_i64, %c64_i64], [%c1_i64, %col_stride], [%c0_i32, %c0_i32] {order = array<i32: 0, 1>} : <te... | Should we check that there is no llvm.shufflevector? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,628 | intel | etiotto | @@ -621,13 +621,8 @@ struct LoadOpConversion
std::swap(tileHeight, tileWidth);
- // We can decompose the matrix returned by transposed large 2d load
- // when threads per warp < column size. Otherwise we have to load one
- // operand per inst.
- // Note: the tileHeight and numOperandsPer2... | Should add the reason (an explanation) for doing so. |
intel-xpu-backend-for-triton | github_2023 | others | 2,628 | intel | etiotto | @@ -193,58 +193,46 @@ module attributes {"triton_gpu.num-warps" = 8 : i32, "triton_gpu.threads-per-war
// -----
+// CHECK: llvm.func spir_funccc @_Z51intel_sub_group_2d_block_read_transpose_32b_16r8x1cPU3AS1viiiDv2_iPj(!llvm.ptr<1> {llvm.nonnull, llvm.readonly}, i32, i32, i32, vector<2xi32>, !llvm.ptr {llvm.nonnul... | Note: these are the changes that matter. The rest of the changes are white space differences. |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,628 | intel | etiotto | @@ -34,6 +34,7 @@ inline const std::set<std::string> CACHE_INVALIDATING_ENV_VARS = {
"TRITON_INTEL_ADVANCED_PATH",
"TRITON_INTEL_AGGRESSIVE_DPAS_REUSE",
"TRITON_INTEL_DO_NOT_SINK_INSTR_ACROSS_RGN",
+ "TRITON_INTEL_DISABLE_LARGE_BLOCK_SIZE_IO_FOR_TRANS_DOT_B", | Remove |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,640 | intel | jopperm | @@ -0,0 +1,16 @@
+#ifndef TRITON_INTEL_ANALYSIS_MEMBAR_H
+#define TRITON_INTEL_ANALYSIS_MEMBAR_H
+
+namespace mlir {
+class Operation;
+namespace intel {
+/// Intel-specific callback to filter operations that need no barriers between
+/// each other.
+///
+/// This is useful as the granularity to check whether barriers... | "Filter" could be ambiguous here (I needed to think about it for a moment), maybe say explicitly something like "return true if no barriers are needed between lhsOp and rhsOp". |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,640 | intel | jopperm | @@ -0,0 +1,58 @@
+#include "intel/include/Analysis/Membar.h"
+
+#include "intel/include/Analysis/Utility.h"
+
+namespace mlir::intel {
+namespace {
+triton::gpu::ConvertLayoutOp dynCastToSubGroupTranspose(Operation *op) {
+ auto convertLayout = dyn_cast<triton::gpu::ConvertLayoutOp>(op);
+ if (!convertLayout)
+ re... | Can you explain, what does "overlap" mean in this context? I presume not "at the same time", otherwise I'd expect to look of different `allocation.offset`s. |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,640 | intel | chengjunlu | @@ -0,0 +1,58 @@
+#include "intel/include/Analysis/Membar.h"
+
+#include "intel/include/Analysis/Utility.h"
+
+namespace mlir::intel {
+namespace {
+triton::gpu::ConvertLayoutOp dynCastToSubGroupTranspose(Operation *op) {
+ auto convertLayout = dyn_cast<triton::gpu::ConvertLayoutOp>(op);
+ if (!convertLayout)
+ re... | Should we check the overlapping instead of the `offset`? Cause of different transposing may require different size of scratch space. |
intel-xpu-backend-for-triton | github_2023 | others | 2,652 | intel | anmyachev | @@ -6,6 +6,7 @@
This is the development repository of Intel® XPU Backend for Triton\*, a new [Triton](https://github.com/triton-lang/triton/) backend for Intel GPUs. Intel® XPU Backend for Triton\* is a out of tree backend module for [Triton](https://github.com/triton-lang/triton/blob/main/CONTRIBUTING.md) used to p... | @whitneywhtsang merge conflict |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,648 | intel | anmyachev | @@ -513,15 +516,17 @@ struct ConvertLayoutOpUsingLinearLayoutsConversion
}
// TODO(jlebar): Implement me.
return failure();
- } else if (llvm::is_contained(dims, str_attr("register"))) {
+ } else if (llvm::is_contained(dims, kRegister) ||
+ dstLayout.getInDimSize(kRegister) !=
+... | I'm just wondering (because I also looked at this issue) if this is the main change that fixes the issue related to `resize` for XPU? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,605 | intel | chengjunlu | @@ -238,6 +241,7 @@ class Allocation {
size_t sharedMemorySize = 0;
friend class triton::AllocationAnalysis;
+ friend class triton::intel::AllocationAnalysis; | The change of adding `intel` namespace in a public header enlarge the divergence of the code upstream and downstream.
Can we improve this? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,605 | intel | etiotto | @@ -0,0 +1,596 @@
+#include "intel/include/Analysis/Allocation.h"
+
+#include <algorithm>
+#include <limits>
+#include <numeric>
+
+#include "mlir/Analysis/DataFlowFramework.h"
+#include "mlir/Analysis/Liveness.h"
+#include "mlir/Analysis/SliceAnalysis.h"
+#include "mlir/Dialect/Tensor/IR/Tensor.h"
+#include "mlir/Supp... | Remove this one |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,605 | intel | etiotto | @@ -0,0 +1,596 @@
+#include "intel/include/Analysis/Allocation.h"
+
+#include <algorithm>
+#include <limits>
+#include <numeric>
+
+#include "mlir/Analysis/DataFlowFramework.h"
+#include "mlir/Analysis/Liveness.h"
+#include "mlir/Analysis/SliceAnalysis.h"
+#include "mlir/Dialect/Tensor/IR/Tensor.h"
+#include "mlir/Supp... | Remove |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,605 | intel | etiotto | @@ -0,0 +1,596 @@
+#include "intel/include/Analysis/Allocation.h"
+
+#include <algorithm>
+#include <limits>
+#include <numeric>
+
+#include "mlir/Analysis/DataFlowFramework.h"
+#include "mlir/Analysis/Liveness.h"
+#include "mlir/Analysis/SliceAnalysis.h"
+#include "mlir/Dialect/Tensor/IR/Tensor.h"
+#include "mlir/Supp... | Unused? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,605 | intel | etiotto | @@ -0,0 +1,596 @@
+#include "intel/include/Analysis/Allocation.h"
+
+#include <algorithm>
+#include <limits>
+#include <numeric>
+
+#include "mlir/Analysis/DataFlowFramework.h"
+#include "mlir/Analysis/Liveness.h"
+#include "mlir/Analysis/SliceAnalysis.h"
+#include "mlir/Dialect/Tensor/IR/Tensor.h"
+#include "mlir/Supp... | Unused? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,605 | intel | etiotto | @@ -0,0 +1,596 @@
+#include "intel/include/Analysis/Allocation.h"
+
+#include <algorithm>
+#include <limits>
+#include <numeric>
+
+#include "mlir/Analysis/DataFlowFramework.h"
+#include "mlir/Analysis/Liveness.h"
+#include "mlir/Analysis/SliceAnalysis.h"
+#include "mlir/Dialect/Tensor/IR/Tensor.h"
+#include "mlir/Supp... | Unused? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,605 | intel | etiotto | @@ -0,0 +1,596 @@
+#include "intel/include/Analysis/Allocation.h"
+
+#include <algorithm>
+#include <limits>
+#include <numeric>
+
+#include "mlir/Analysis/DataFlowFramework.h"
+#include "mlir/Analysis/Liveness.h"
+#include "mlir/Analysis/SliceAnalysis.h"
+#include "mlir/Dialect/Tensor/IR/Tensor.h"
+#include "mlir/Supp... | This should be a DPAS layout right ? OR are you just copying the original file first and do further modification later ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,627 | intel | whitneywhtsang | @@ -37,7 +37,8 @@ inline const std::set<std::string> CACHE_INVALIDATING_ENV_VARS = {
"TRITON_INTEL_ENABLE_FIRST_LOAD_TO_SLM",
"TRITON_INTEL_ENABLE_INSTR_SCHED",
"TRITON_INTEL_ENABLE_POST_PROCESS_LLIR",
- "TRITON_INTEL_REDUCE_TRANSPOSE"
+ "TRITON_INTEL_REDUCE_TRANSPOSE",
+ "TRITON_INTEL_AGGRESSIV... | alphabetical order? |
intel-xpu-backend-for-triton | github_2023 | python | 2,608 | intel | etiotto | @@ -23,7 +23,7 @@ def quiet():
sys.stdout, sys.stderr = old_stdout, old_stderr
-def _build(name, src, srcdir, library_dirs, include_dirs, libraries):
+def _build(name, src, srcdir, library_dirs, include_dirs, libraries, extra_compile_args=[]): | This change in common file should be upstreamed. Can you open an issue so you can do that separately please ? |
intel-xpu-backend-for-triton | github_2023 | python | 2,608 | intel | pbchekin | @@ -14,36 +14,35 @@
from packaging.specifiers import SpecifierSet
-def find_sycl(include_dir: list[str]) -> tuple[list[str], list[str]]:
+def find_sycl(include_dir: list[str]) -> tuple[list[str], str]: | Since libsycl location can be None:
```suggestion
def find_sycl(include_dir: list[str]) -> tuple[list[str], Optional[str]]:
``` |
intel-xpu-backend-for-triton | github_2023 | python | 2,608 | intel | pbchekin | @@ -97,6 +102,11 @@ def include_dir(self) -> list[str]:
self._compute_compilation_options_lazy
return self._include_dir
+ @cached_property
+ def libsycl_dir(self) -> list[str]: | ```suggestion
def libsycl_dir(self) -> Optional[str]:
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,620 | intel | etiotto | @@ -722,9 +722,10 @@ MatchTargetSizePass::getSubOpSize(RankedTensorType type,
if (isa<ttgi::WarpEncodingAttr>(layout)) {
// 32 = 2 * 16(subgroupSize) which is for large load/store
// max 2d block prefetch width is 16 for 32-bit datatype
- subSize[1] = std::min(sizeInBits == 32 ? 16L : 32L, shape... | ```suggestion
subSize[0] = std::min(32LL, shape[0]);
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,620 | intel | etiotto | @@ -722,9 +722,10 @@ MatchTargetSizePass::getSubOpSize(RankedTensorType type,
if (isa<ttgi::WarpEncodingAttr>(layout)) {
// 32 = 2 * 16(subgroupSize) which is for large load/store
// max 2d block prefetch width is 16 for 32-bit datatype
- subSize[1] = std::min(sizeInBits == 32 ? 16L : 32L, shape... | ```suggestion
subSize[1] = std::min(sizeInBits == 32 ? 16LL : 32LL),
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,623 | intel | whitneywhtsang | @@ -1459,7 +1449,8 @@ struct AtomicRMWOpConversion
// emit unsupported feature error.
if (valueElemNBits == 16) {
op.emitWarning(
- "'tt.atomic_rmw' op fp16 datatype is not supported in the target "
+ "'tt.atomic_rmw' op fp16 datatype is not supported in the "
+ "... | undo or combine with the next line? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,623 | intel | whitneywhtsang | @@ -1561,10 +1552,10 @@ struct AtomicRMWOpConversion
rmwVal = bitcast(rmwVal, valueElemTy);
- // Align pointer by 4 bytes by zeroing lower address bits. Atomically read
- // a vector of two fp16 values as a single i32. The second lowest bit is
- // extracted to later be used as an index to extract the... | I am fine with this change, but curious why? it is needed for clang-format, why it didn't fail before? |
intel-xpu-backend-for-triton | github_2023 | others | 2,591 | intel | sommerlukas | @@ -50,3 +50,20 @@ tt.func @fn(%arg0: tensor<1xf32, #sliced0>) -> (tensor<32x1xf32, #blocked0>){
tt.return %b : tensor<32x1xf32, #blocked0>
}
} // end module
+
+// -----
+
+// CHECK-LABEL: tt.func @reduce(
+// CHECK-SAME: %[[ARG0:.*]]: tensor<2x1x16xf32>,
+// CHECK-SAME: %[[ARG1:... | What do we return after the canonicalization? The result of the two `reshape` operations?
If so, we should also check for that in the test. |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,591 | intel | sommerlukas | @@ -495,6 +495,55 @@ LogicalResult ReduceOp::verifyRegions() {
return verifyRegionsImpl<ReduceReturnOp>(*this);
}
+namespace {
+/// Replace reduction operations with equivalent reshape operations.
+///
+/// This pattern replaces reductions whose input tensor size is 1 in the
+/// reduction dimension:
+/// ```mlir... | ```suggestion
/// : (tensor<S0x...x SN-1 x 1 x SN+1x...>, ...) -> tensor<S0x...x SN-1 x SN+1x...>
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,591 | intel | sommerlukas | @@ -495,6 +495,55 @@ LogicalResult ReduceOp::verifyRegions() {
return verifyRegionsImpl<ReduceReturnOp>(*this);
}
+namespace {
+/// Replace reduction operations with equivalent reshape operations.
+///
+/// This pattern replaces reductions whose input tensor size is 1 in the
+/// reduction dimension:
+/// ```mlir... | ```suggestion
/// : tensor<S0x...x SN-1 x 1 x SN+1x...> -> tensor<S0x...x SN-1 x SN+1x...>
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,517 | intel | anmyachev | @@ -299,6 +299,11 @@ SmallVector<unsigned> getOrder(Attribute layout) {
}
if (auto dotLayout = dyn_cast<DotOperandEncodingAttr>(layout)) {
auto rank = getWarpsPerCTA(dotLayout.getParent()).size();
+ if (dyn_cast<intel::DpasEncodingAttr>(dotLayout.getParent())) { | @whitneywhtsang this is the only change needed to fix `lit` tests. In the new code, the swap occurs conditionally (`if (opIdx == 1)`), which apparently did not work for dpas so I returned unconditional swap. |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,517 | intel | chengjunlu | @@ -293,13 +304,12 @@ SmallVector<unsigned> getOrder(Attribute layout) {
}
if (auto dotLayout = dyn_cast<DotOperandEncodingAttr>(layout)) {
auto rank = getWarpsPerCTA(dotLayout.getParent()).size();
- SmallVector<unsigned> order(rank);
- if (isa<AMDMfmaEncodingAttr>(dotLayout.getParent())) {
- retu... | I didn't make a clear review at the first time. If the original code changes is only made for AMD, then we can keep all those DotOp register layout order unchanged. |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,598 | intel | victor-eds | @@ -187,10 +42,11 @@ class ModuleAxisInfoAnalysis : public CallGraph<AxisInfoMapT> {
}
}
- AxisInfo *getAxisInfo(Value value) {
+ AxisInfo *getAxisInfo(Value value) const {
auto funcOp =
value.getParentRegion()->getParentOfType<FunctionOpInterface>();
- auto *axisInfoMap = getFuncData(funcO... | Can we remove `const` and not `const_cast`? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,598 | intel | victor-eds | @@ -201,9 +57,9 @@ class ModuleAxisInfoAnalysis : public CallGraph<AxisInfoMapT> {
return &(it->second);
}
- unsigned getPtrContiguity(Value ptr);
- unsigned getPtrAlignment(Value ptr);
- unsigned getMaskAlignment(Value mask);
+ unsigned getPtrContiguity(Value ptr) const;
+ unsigned getPtrAlignment(Value... | Same as above |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,598 | intel | chengjunlu | @@ -1,169 +1,24 @@
#ifndef TRITON_INTEL_ANALYSIS_AXISINFO_H
#define TRITON_INTEL_ANALYSIS_AXISINFO_H
-#include "mlir/Analysis/DataFlow/SparseAnalysis.h"
-#include "llvm/Support/raw_ostream.h"
-
-#include "mlir/Support/LLVM.h"
-#include "triton/Analysis/Utility.h"
-#include "triton/Dialect/Triton/IR/Dialect.h"
-#inc... | Remove comment-out code. |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,518 | intel | etiotto | @@ -157,65 +186,99 @@ unsigned DpasEncodingAttr::getTotalElemsPerThread(ArrayRef<int64_t> shape,
}
SmallVector<unsigned> DpasEncodingAttr::getCTASplitNum() const {
- SmallVector<unsigned> res{1, 1};
+ size_t rank = getWarpsPerCTA().size();
+ SmallVector<unsigned> res(rank, 1);
return res;
}
SmallVector<un... | ```suggestion
}
if (opIdx == 1) {
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,518 | intel | etiotto | @@ -157,65 +186,99 @@ unsigned DpasEncodingAttr::getTotalElemsPerThread(ArrayRef<int64_t> shape,
}
SmallVector<unsigned> DpasEncodingAttr::getCTASplitNum() const {
- SmallVector<unsigned> res{1, 1};
+ size_t rank = getWarpsPerCTA().size();
+ SmallVector<unsigned> res(rank, 1);
return res;
}
SmallVector<un... | ```suggestion
}
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,518 | intel | etiotto | @@ -157,65 +186,99 @@ unsigned DpasEncodingAttr::getTotalElemsPerThread(ArrayRef<int64_t> shape,
}
SmallVector<unsigned> DpasEncodingAttr::getCTASplitNum() const {
- SmallVector<unsigned> res{1, 1};
+ size_t rank = getWarpsPerCTA().size();
+ SmallVector<unsigned> res(rank, 1);
return res;
}
SmallVector<un... | ```suggestion
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,518 | intel | etiotto | @@ -157,65 +186,99 @@ unsigned DpasEncodingAttr::getTotalElemsPerThread(ArrayRef<int64_t> shape,
}
SmallVector<unsigned> DpasEncodingAttr::getCTASplitNum() const {
- SmallVector<unsigned> res{1, 1};
+ size_t rank = getWarpsPerCTA().size();
+ SmallVector<unsigned> res(rank, 1);
return res;
}
SmallVector<un... | ```suggestion
size_t rank = shape.size();
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,518 | intel | etiotto | @@ -224,33 +287,47 @@ SmallVector<unsigned> DpasEncodingAttr::getWarpsPerCTA() const {
}
SmallVector<unsigned> DpasEncodingAttr::getThreadsPerWarp() const {
+ size_t rank = getWarpsPerCTA().size();
+ SmallVector<unsigned> res(rank, 1);
auto executionSize = getExecutionSize();
auto subGroupSize = getSubGroup... | ```suggestion
return (rank == 2)
? {parentShapePerCTATile[0], shapeA[1]}
: {parentShapePerCTATile[0], parentShapePerCTATile[rank - 2], shapeA[rank - 1]};
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,518 | intel | etiotto | @@ -224,33 +287,47 @@ SmallVector<unsigned> DpasEncodingAttr::getWarpsPerCTA() const {
}
SmallVector<unsigned> DpasEncodingAttr::getThreadsPerWarp() const {
+ size_t rank = getWarpsPerCTA().size();
+ SmallVector<unsigned> res(rank, 1);
auto executionSize = getExecutionSize();
auto subGroupSize = getSubGroup... | Rank here should be 2 or 3 correct? Please add an assertion. |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,518 | intel | etiotto | @@ -224,33 +287,47 @@ SmallVector<unsigned> DpasEncodingAttr::getWarpsPerCTA() const {
}
SmallVector<unsigned> DpasEncodingAttr::getThreadsPerWarp() const {
+ size_t rank = getWarpsPerCTA().size();
+ SmallVector<unsigned> res(rank, 1);
auto executionSize = getExecutionSize();
auto subGroupSize = getSubGroup... | ```suggestion
}
if (opIdx == 1) {
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,518 | intel | etiotto | @@ -224,33 +287,47 @@ SmallVector<unsigned> DpasEncodingAttr::getWarpsPerCTA() const {
}
SmallVector<unsigned> DpasEncodingAttr::getThreadsPerWarp() const {
+ size_t rank = getWarpsPerCTA().size();
+ SmallVector<unsigned> res(rank, 1);
auto executionSize = getExecutionSize();
auto subGroupSize = getSubGroup... | ```suggestion
return (rank == 2)
? {shapeB[0], parentShapePerCTATile[1]}
: {parentShapePerCTATile[0], shapeB[rank - 2], parentShapePerCTATile[rank - 1]};
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,518 | intel | etiotto | @@ -224,33 +287,47 @@ SmallVector<unsigned> DpasEncodingAttr::getWarpsPerCTA() const {
}
SmallVector<unsigned> DpasEncodingAttr::getThreadsPerWarp() const {
+ size_t rank = getWarpsPerCTA().size();
+ SmallVector<unsigned> res(rank, 1);
auto executionSize = getExecutionSize();
auto subGroupSize = getSubGroup... | ```suggestion
}
llvm_unreachable("DotOperandEncodingAttr opIdx must be 0 or 1");
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,518 | intel | etiotto | @@ -267,8 +344,7 @@ DpasEncodingAttr::getSizePerThreadForOperands(unsigned opIdx) const {
"be smaller than the threads required per row.");
}
unsigned rowsPerWarp = mlir::ceil<unsigned>(subGroupSize, packedColNum);
- auto repCluster = getRepCluster();
- return {shapeA[0] ... | ```suggestion
}
if (opIdx == 1) {
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,518 | intel | etiotto | @@ -293,20 +368,31 @@ SmallVector<unsigned> DpasEncodingAttr::getElemsPerThreadForOperands(
SmallVector<unsigned> sizePerThread = getSizePerThreadForOperands(opIdx);
SmallVector<int64_t> repetitions = getDPASRepetitions(shape, opIdx);
- return {static_cast<unsigned>(sizePerThread[0] * repetitions[0]),
- ... | ```suggestion
if (threadsPerWarp > instShapeC[1]) {
return contigPerThread;
}
if (threadsPerWarp == instShapeC[1]) {
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,518 | intel | etiotto | @@ -110,17 +110,23 @@ struct ConvertLayoutOpConversion
return multiDimOffset;
}
if (auto dpasLayout = dyn_cast<DpasEncodingAttr>(layout)) {
- assert(rank == 2);
+ assert(rank == 2 || rank == 3); | Add assert message please |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,518 | intel | etiotto | @@ -259,12 +283,14 @@ getLoadMatrixFn(MemDescType descTy, const SharedMemoryObject &smemObj,
auto sharedLayout = cast<SharedEncodingAttr>(descTy.getEncoding());
ArrayRef<unsigned> order = sharedLayout.getOrder();
+ unsigned rank = order.size(); | ```suggestion
size_t rank = order.size();
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,518 | intel | etiotto | @@ -272,10 +279,17 @@ emitOffsetForDotOpLayout(const DotOperandEncodingAttr &dotLayout,
unsigned packedElemColIndex =
(packedElemId % numColsPerLaneForPackedValue) *
numColsPerPackedValue;
- offsets.push_back({repRowIndex + repClusterRowIndex +
- ... | assert that rank == 2 |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,518 | intel | etiotto | @@ -175,15 +177,19 @@ emitOffsetForDpasLayoutPerCTA(const DpasEncodingAttr &dpasLayout,
for (unsigned elemId = 0; elemId < elemNumberPerRep; ++elemId) {
// Follows the C++ order for the dpas layout.
SmallVector<unsigned> repOffset = {
- (repId / repCluster[1]) * instShapeC[0],
- (re... | assert that rank == 2 |
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