repo_name stringlengths 1 62 | dataset stringclasses 1
value | lang stringclasses 11
values | pr_id int64 1 20.1k | owner stringlengths 2 34 | reviewer stringlengths 2 39 | diff_hunk stringlengths 15 262k | code_review_comment stringlengths 1 99.6k |
|---|---|---|---|---|---|---|---|
intel-xpu-backend-for-triton | github_2023 | cpp | 1,859 | intel | whitneywhtsang | @@ -387,9 +387,59 @@ createBlock2DReadWithAddressPayloadUpdate(TritonGEN::Matrix2DBlockLoadOp op,
attrs);
};
+ auto createBlock2DReadGenISA = [&](Value ptr,
+ TritonGEN::Matrix2DBlockLoadOp op) {
+ assert(isa<LLVM::LLVMPointerType>(ptr.ge... | not used.
```suggestion
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,859 | intel | whitneywhtsang | @@ -387,9 +387,59 @@ createBlock2DReadWithAddressPayloadUpdate(TritonGEN::Matrix2DBlockLoadOp op,
attrs);
};
+ auto createBlock2DReadGenISA = [&](Value ptr,
+ TritonGEN::Matrix2DBlockLoadOp op) {
+ assert(isa<LLVM::LLVMPointerType>(ptr.ge... | [optional]
```suggestion
auto vecType = dyn_cast<VectorType>(resType);
assert(vecType && vecType.getShape().size() == 1 && "Expecting a 1D vector");
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,859 | intel | whitneywhtsang | @@ -387,9 +387,59 @@ createBlock2DReadWithAddressPayloadUpdate(TritonGEN::Matrix2DBlockLoadOp op,
attrs);
};
+ auto createBlock2DReadGenISA = [&](Value ptr,
+ TritonGEN::Matrix2DBlockLoadOp op) {
+ assert(isa<LLVM::LLVMPointerType>(ptr.ge... | I would inline all these variables, as there is no extra info convey with them, and they are not used more than once. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,835 | intel | etiotto | @@ -164,7 +164,160 @@ LogicalResult TritonGEN::MatrixDPASOp::verify() {
// gen.2Dblockload
//===----------------------------------------------------------------------===//
+static LogicalResult
+verify2DBlockLoadHWRestriction(TritonGEN::Matrix2DBlockLoadOp op) {
+ VectorType resTy = op.getRes().getType();
+ unsig... | I rather have this early exit (when both transpose and transform are true). |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,835 | intel | etiotto | @@ -164,7 +164,160 @@ LogicalResult TritonGEN::MatrixDPASOp::verify() {
// gen.2Dblockload
//===----------------------------------------------------------------------===//
+static LogicalResult
+verify2DBlockLoadHWRestriction(TritonGEN::Matrix2DBlockLoadOp op) {
+ VectorType resTy = op.getRes().getType();
+ unsig... | assert(op.getVnniTransform() && !op.getTranspose() && ...) |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,811 | intel | LiyangLingIntel | @@ -425,54 +426,59 @@ class TritonIntelGPURewriteTensorPointerPass
"Expecting LoadOp/StoreOp ptr in rewritedInfo");
auto info = rewritedInfo[ptr];
- // Load/store with tensor pointers implicitly will check the bound while
- // accessing memory, so we should set `mask` and `other` (according to ... | ```suggestion
"Expecting StoreOp ptr in rewritedInfo");
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,811 | intel | LiyangLingIntel | @@ -425,54 +426,59 @@ class TritonIntelGPURewriteTensorPointerPass
"Expecting LoadOp/StoreOp ptr in rewritedInfo"); | ```suggestion
"Expecting LoadOp ptr in rewritedInfo");
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,811 | intel | whitneywhtsang | @@ -666,36 +672,36 @@ class TritonIntelGPURewriteTensorPointerPass
Operation *rewriteOp(Operation *op, std::stack<Operation *> &eraser) {
OpBuilder builder(op);
- // Rewrite `make_tensor_ptr` and `advance` and make a tensor of pointers
- // Rewriting functions return the next operation to visit, if ther... | would something like below works?
```
return TypeSwitch<Operation *, Operation *>(op)
.Case<tt::MakeTensorPtrOp, tt::AdvanceOp, ...>([&](auto op) {
return rewriteOp(builder, op, eraser);
}
...
``` |
intel-xpu-backend-for-triton | github_2023 | python | 1,805 | intel | chengjunlu | @@ -102,11 +93,13 @@ def extract_kernels(funcs):
times = torch.tensor([sum([k.duration for k in ks]) * 1e-3 for ks in kernels], dtype=torch.float)
if quantiles is not None:
ret = torch.quantile(times, torch.tensor(quantiles, dtype=torch.float)).tolist()
+ # calculate average time exclude max a... | Is it better to align the samples for the std and cv to the avg?
Then all the statistics are based on the same set of the samples. |
intel-xpu-backend-for-triton | github_2023 | python | 1,805 | intel | etiotto | @@ -53,17 +53,8 @@ def do_bench(fn, warmup=25, rep=100, grad_to_none=None, quantiles=None, fast_flu
# Estimate the runtime of the function
start_event = torch.xpu.Event(enable_timing=True)
end_event = torch.xpu.Event(enable_timing=True)
- start_event.record() | I'd like to understand the reason you are changing this code. What is the motivation/rationale ? |
intel-xpu-backend-for-triton | github_2023 | python | 1,805 | intel | etiotto | @@ -7,100 +7,15 @@
"""
-# %% | What is the reason to remove the comments ? |
intel-xpu-backend-for-triton | github_2023 | python | 1,805 | intel | etiotto | @@ -102,11 +93,13 @@ def extract_kernels(funcs):
times = torch.tensor([sum([k.duration for k in ks]) * 1e-3 for ks in kernels], dtype=torch.float)
if quantiles is not None:
ret = torch.quantile(times, torch.tensor(quantiles, dtype=torch.float)).tolist()
+ # calculate average time exclude max a... | why are we using the average rather than the mean ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,805 | intel | whitneywhtsang | @@ -385,8 +385,97 @@ createBlock2DReadWithAddressPayloadUpdate(TritonGEN::Matrix2DBlockLoadOp op,
attrs);
};
+ auto createBlock2DReadGenIsa = [&](Value ptr,
+ TritonGEN::Matrix2DBlockLoadOp op) {
+ assert(isa<LLVM::LLVMPointerType>(ptr.ge... | Can we do this in a separate PR with lit test? |
intel-xpu-backend-for-triton | github_2023 | python | 1,805 | intel | whitneywhtsang | @@ -64,6 +64,7 @@ def do_bench(fn, warmup=25, rep=100, grad_to_none=None, quantiles=None, fast_flu
# compute number of warmup and repeat
n_warmup = max(warmup, int(warmup / estimate_ms))
n_repeat = max(rep, int(rep / estimate_ms))
+ | ```suggestion
``` |
intel-xpu-backend-for-triton | github_2023 | python | 1,805 | intel | whitneywhtsang | @@ -102,10 +103,17 @@ def extract_kernels(funcs):
times = torch.tensor([sum([k.duration for k in ks]) * 1e-3 for ks in kernels], dtype=torch.float)
if quantiles is not None:
ret = torch.quantile(times, torch.tensor(quantiles, dtype=torch.float)).tolist()
- # add coefficient of the variance.
- ... | ```suggestion
if (times.numel() > 2):
# exclude max and min times
times = torch.sort(times).values[1:-1]
std = torch.std(times)
mean = torch.mean(times)
cv = std / mean
``` |
intel-xpu-backend-for-triton | github_2023 | python | 1,799 | intel | whitneywhtsang | @@ -351,7 +351,6 @@ def matmul(a, b):
[1, 512, 32768, 8192], #
[1, 1024, 16384, 8192], #
[1, 1024, 28672, 8192], #
- [1, 3072, 4096, 3072], # | Let's not remove until we have streamk working for Triton, or else we are not checking if it works. Let's add a FIXME to remind ourselves here. |
intel-xpu-backend-for-triton | github_2023 | python | 1,799 | intel | LiyangLingIntel | @@ -388,15 +387,14 @@ def benchmark(B, M, N, K, provider):
quantiles = [0.5, 0.0, 1.0]
if provider == 'onednn':
- ms, min_ms, max_ms, mean, cv = benchmark_suit.do_bench(lambda: torch.matmul(a, b), warmup=100, rep=100,
- quantiles=quantiles... | How much impact the `fast_flush` has on the performance data? |
intel-xpu-backend-for-triton | github_2023 | others | 1,345 | intel | pbchekin | @@ -4,6 +4,10 @@ run-name: ${{ inputs.run_name }}
on:
workflow_dispatch:
inputs:
+ enable_unskip:
+ description: Ignore all pytest.skip, disable as default | Nit:
```suggestion
description: Ignore pytest.skip
``` |
intel-xpu-backend-for-triton | github_2023 | others | 1,345 | intel | pbchekin | @@ -34,10 +34,10 @@ pytest() {
mkdir -p "$CURRENT_SKIPLIST_DIR"
# skip comments in the skiplist
sed -e '/^#/d' "$TRITON_TEST_SKIPLIST_DIR/$TRITON_TEST_SUITE.txt" > "$CURRENT_SKIPLIST_DIR/$TRITON_TEST_SUITE.txt"
- pytest_extra_args+=(
- "--deselect-from-file=$CURRENT_SKIPLIST... | ```suggestion
if [[ $TEST_UNSKIP = false ]]; then
pytest_extra_args+=(
"--deselect-from-file=$CURRENT_SKIPLIST_DIR/$TRITON_TEST_SUITE.txt"
"--select-fail-on-missing"
)
fi
``` |
intel-xpu-backend-for-triton | github_2023 | others | 1,345 | intel | pbchekin | @@ -34,10 +34,12 @@ pytest() {
mkdir -p "$CURRENT_SKIPLIST_DIR"
# skip comments in the skiplist
sed -e '/^#/d' "$TRITON_TEST_SKIPLIST_DIR/$TRITON_TEST_SUITE.txt" > "$CURRENT_SKIPLIST_DIR/$TRITON_TEST_SUITE.txt"
- pytest_extra_args+=(
- "--deselect-from-file=$CURRENT_SKIPLIST... | ```suggestion
"--deselect-from-file=$CURRENT_SKIPLIST_DIR/$TRITON_TEST_SUITE.txt"
``` |
intel-xpu-backend-for-triton | github_2023 | others | 1,345 | intel | pbchekin | @@ -34,10 +34,14 @@ pytest() {
mkdir -p "$CURRENT_SKIPLIST_DIR"
# skip comments in the skiplist
sed -e '/^#/d' "$TRITON_TEST_SKIPLIST_DIR/$TRITON_TEST_SUITE.txt" > "$CURRENT_SKIPLIST_DIR/$TRITON_TEST_SUITE.txt"
- pytest_extra_args+=(
- "--deselect-from-file=$CURRENT_SKIPLIST... | IMHO timeout 15s is not enough for some tests. Also have you tested that pytest-timeout works well with pytest-xdist? I had several weird errors using them both and also see https://github.com/pytest-dev/pytest-xdist/issues/220. Potentially for this mode (TEST_UNSKIP) you need to disable xdist and run tests sequentiall... |
intel-xpu-backend-for-triton | github_2023 | others | 1,345 | intel | pbchekin | @@ -114,3 +119,4 @@ jobs:
ignore_errors: ${{ inputs.ignore_errors || false }}
skip_list: ${{ inputs.skip_list }}
run_name: ${{ inputs.run_name }}
+ enable_unskip: ${{ (github.event_name == 'workflow_dispatch' && inputs.enable_unskip) || false }} | Nit: i think this can be simpler:
```suggestion
enable_unskip: ${{ inputs.enable_unskip || false }}
``` |
intel-xpu-backend-for-triton | github_2023 | python | 1,345 | intel | pbchekin | @@ -76,9 +76,25 @@ def parse_report(report_path: pathlib.Path) -> ReportStats:
except FileNotFoundError:
pass
stats.fixme += len(testsuite_fixme_tests)
- deselected = get_deselected(report_path)
- stats.skipped += deselected
- stats.total += deselected
+
+ test_unskip = os.get... | Nit:
```suggestion
if test_unskip not in ("true", "false"):
``` |
intel-xpu-backend-for-triton | github_2023 | python | 1,345 | intel | pbchekin | @@ -76,9 +76,25 @@ def parse_report(report_path: pathlib.Path) -> ReportStats:
except FileNotFoundError:
pass
stats.fixme += len(testsuite_fixme_tests)
- deselected = get_deselected(report_path)
- stats.skipped += deselected
- stats.total += deselected
+
+ test_unskip = os.get... | Please use the same logic as in `get_deselected`. |
intel-xpu-backend-for-triton | github_2023 | python | 1,345 | intel | pbchekin | @@ -76,9 +76,25 @@ def parse_report(report_path: pathlib.Path) -> ReportStats:
except FileNotFoundError:
pass
stats.fixme += len(testsuite_fixme_tests)
- deselected = get_deselected(report_path)
- stats.skipped += deselected
- stats.total += deselected
+
+ test_unskip = os.get... | Please do not hardcode the name of the file here. Instead, you can use a convention for example if `{name}-coredump.txt` exists then you can use it to adjust `skipped` and `total`. Move the processing to a function similar to `get_deselected`. |
intel-xpu-backend-for-triton | github_2023 | others | 1,345 | intel | pbchekin | @@ -34,10 +34,20 @@ pytest() {
mkdir -p "$CURRENT_SKIPLIST_DIR"
# skip comments in the skiplist
sed -e '/^#/d' "$TRITON_TEST_SKIPLIST_DIR/$TRITON_TEST_SUITE.txt" > "$CURRENT_SKIPLIST_DIR/$TRITON_TEST_SUITE.txt"
- pytest_extra_args+=(
- "--deselect-from-file=$CURRENT_SKIPLIST... | Please do not hard code test suite. |
intel-xpu-backend-for-triton | github_2023 | others | 1,345 | intel | pbchekin | @@ -0,0 +1,28 @@
+#!/bin/bash
+# set -x
+# Generate a .txt recording all cases that cause coredump
+
+SCRIPTS_DIR="$( cd -- "$( dirname -- "${BASH_SOURCE[0]}" )" &> /dev/null && pwd )"
+cd $SCRIPTS_DIR/../python/test/unit
+
+TRITON_TEST_SKIPLIST_DIR="${TRITON_TEST_SKIPLIST_DIR:-$SCRIPTS_DIR/skiplist/default}"
+COREDUMP... | I don't like the idea to restart pytest after test crash, `pytest-xdist` automatically handles this, see https://pytest-xdist.readthedocs.io/en/stable/crash.html. The `pre-run.sh` script basically runs all core tests, then you run them again in the workflow, that is a waste of time and compute resources. Potentially yo... |
intel-xpu-backend-for-triton | github_2023 | others | 1,345 | intel | pbchekin | @@ -200,7 +205,7 @@ jobs:
source ./scripts/pytest-utils.sh
cd python/test/unit
TRITON_TEST_SUITE=language \
- pytest -vvv -n 8 --device xpu language/ --ignore=language/test_line_info.py --ignore=language/test_subprocess.py
+ pytest -vvv -n 8 --max-worker-restart=50... | Move `--max-worker-restart=500` to `pytest-utils.sh` to the same place where you have `--timeout=500`. |
intel-xpu-backend-for-triton | github_2023 | others | 1,345 | intel | pbchekin | @@ -141,13 +146,15 @@ run_core_tests() {
echo "****** Running Triton Core tests ******"
echo "***************************************************"
CORE_TEST_DIR=$TRITON_PROJ/python/test/unit
+
if [ ! -d "${CORE_TEST_DIR}" ]; then
echo "Not found '${CORE_TEST_DIR}'. Build Triton please" ; ex... | Move `--max-worker-restart=500` to `pytest-utils.sh` to the same place where you have `--timeout=500`. |
intel-xpu-backend-for-triton | github_2023 | others | 1,345 | intel | pbchekin | @@ -34,10 +34,14 @@ pytest() {
mkdir -p "$CURRENT_SKIPLIST_DIR"
# skip comments in the skiplist
sed -e '/^#/d' "$TRITON_TEST_SKIPLIST_DIR/$TRITON_TEST_SUITE.txt" > "$CURRENT_SKIPLIST_DIR/$TRITON_TEST_SUITE.txt"
- pytest_extra_args+=(
- "--deselect-from-file=$CURRENT_SKIPLIST... | ```suggestion
pytest_extra_args+=(
"--timeout=500"
"--max-worker-restart=500"
)
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,636 | intel | victor-eds | @@ -846,6 +846,14 @@ struct TritonRaiseBlockPointer
return failure();
}
+ // As masks are incompatible with block pointer load/store ops
+ // Masks must be handled before the operation can be rewritten.
+ // This will be done in a future PR (Issue #1784).
+ // In the meantime, operations with ... | `success()` or `failure()`? |
intel-xpu-backend-for-triton | github_2023 | others | 1,761 | intel | whitneywhtsang | @@ -0,0 +1,38 @@
+// RUN: triton-opt %s -split-input-file --intel-decompose-unsupported-conversions | FileCheck %s
+
+#dpas = #triton_intel_gpu.dpas<{repeatCount = 8, systolicDepth = 8, executionSize = 16, opsPerChan = 2, threadsPerWarp = 16, warpsPerCTA = [32, 1], repCluster = [1, 2], A = [8, 16], B = [16, 32], C = [8... | ```suggestion
module attributes {"triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 32 : i32, "triton_gpu.threads-per-warp" = 16 : i32, triton_intel_gpu.min_sg_size = 16 : i32, triton_intel_gpu.support_dpas, triton_intel_gpu.support_sg_2d_block} {
``` |
intel-xpu-backend-for-triton | github_2023 | others | 1,761 | intel | whitneywhtsang | @@ -0,0 +1,38 @@
+// RUN: triton-opt %s -split-input-file --intel-decompose-unsupported-conversions | FileCheck %s
+
+#dpas = #triton_intel_gpu.dpas<{repeatCount = 8, systolicDepth = 8, executionSize = 16, opsPerChan = 2, threadsPerWarp = 16, warpsPerCTA = [32, 1], repCluster = [1, 2], A = [8, 16], B = [16, 32], C = [8... | Please add comment in the test case on why you don't expect local_alloc/load in this case. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,761 | intel | whitneywhtsang | @@ -133,12 +138,10 @@ struct DecomposeUnsupportedConversions
srcBlocked.getOrder(), srcBlocked.getCTALayout(),
srcType.getElementType()),
sharedMemorySpace);
- auto tmp = builder.create<triton::gpu::ConvertLayoutOp>(
+ auto tmp = builder.create<triton::gpu::L... | Please upstream this changes. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,761 | intel | etiotto | @@ -84,29 +86,32 @@ struct DecomposeUnsupportedConversions
}
});
/* -------------------------------- */
- // Replace `mma -> dot_op` with `mma -> blocked -> dot_op`
+ // Replace `dpas -> dot_op` with `dpas -> shared -> dot_op` | Why not doing the same as NVidia and go to blocked layout which is later on converted to shared layout and then to dot layout. I think your motivation is to just avoid the intermediate step of converting from a dpas layout to blocked layout, which makes sense at first sight.
My concern is that deviating from the w... |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,761 | intel | whitneywhtsang | @@ -84,23 +86,24 @@ struct DecomposeUnsupportedConversions
}
});
/* -------------------------------- */
- // Replace `mma -> dot_op` with `mma -> blocked -> dot_op`
+ // Replace `dpas -> dot_op` with `dpas -> shared -> dot_op` | ```suggestion
// Replace `dpas -> dot_op` with `dpas -> blocked -> dot_op`
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,570 | intel | FMarno | @@ -24,6 +24,59 @@ namespace {
constexpr unsigned offsetBitwidth = 32;
constexpr unsigned shapeAndStridesBitwidth = 64;
+std::optional<int64_t> getIntAttr(const OpFoldResult ofr) {
+ if (ofr.is<Attribute>() && isa<IntegerAttr>(ofr.get<Attribute>()))
+ return dyn_cast<IntegerAttr>(ofr.get<Attribute>()).getInt(); | ```suggestion
return cast<IntegerAttr>(ofr.get<Attribute>()).getInt();
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,570 | intel | FMarno | @@ -24,6 +24,59 @@ namespace {
constexpr unsigned offsetBitwidth = 32;
constexpr unsigned shapeAndStridesBitwidth = 64;
+std::optional<int64_t> getIntAttr(const OpFoldResult ofr) {
+ if (ofr.is<Attribute>() && isa<IntegerAttr>(ofr.get<Attribute>()))
+ return dyn_cast<IntegerAttr>(ofr.get<Attribute>()).getInt();... | ```suggestion
auto val = cast<Value>(results[0]);
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,570 | intel | FMarno | @@ -24,6 +24,59 @@ namespace {
constexpr unsigned offsetBitwidth = 32;
constexpr unsigned shapeAndStridesBitwidth = 64;
+std::optional<int64_t> getIntAttr(const OpFoldResult ofr) {
+ if (ofr.is<Attribute>() && isa<IntegerAttr>(ofr.get<Attribute>()))
+ return dyn_cast<IntegerAttr>(ofr.get<Attribute>()).getInt();... | ```suggestion
return getIntAttr(constOp.getValue());
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,570 | intel | FMarno | @@ -24,6 +24,59 @@ namespace {
constexpr unsigned offsetBitwidth = 32;
constexpr unsigned shapeAndStridesBitwidth = 64;
+std::optional<int64_t> getIntAttr(const OpFoldResult ofr) {
+ if (ofr.is<Attribute>() && isa<IntegerAttr>(ofr.get<Attribute>()))
+ return dyn_cast<IntegerAttr>(ofr.get<Attribute>()).getInt();... | ```suggestion
return intVal.has_value() && intVal.value() == 0;
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,570 | intel | FMarno | @@ -69,9 +122,13 @@ struct PtrState {
// When PtrState describes a non-block pointer, shape field indicates how
// address wraps around. As a result, a constant 0 indicates no wrap around
// (i.e. modulo) for the dimension.
- if (auto intOp = shape[dim].getDefiningOp<arith::ConstantIntOp>()) {
- ... | is `results` used? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,570 | intel | FMarno | @@ -69,9 +122,13 @@ struct PtrState {
// When PtrState describes a non-block pointer, shape field indicates how
// address wraps around. As a result, a constant 0 indicates no wrap around
// (i.e. modulo) for the dimension.
- if (auto intOp = shape[dim].getDefiningOp<arith::ConstantIntOp>()) {
- ... | ```suggestion
return !hasConstZero(shape[dim]);
```
double check that one please! |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,570 | intel | FMarno | @@ -112,11 +169,72 @@ struct PtrState {
sizes.push_back(lhsState.sizes[i]);
}
+ // AddPtr where both lhs and rhs containing modulo operators not supported
+ if (lhsState.hasModulo() && rhsState.hasModulo()) {
+ op->emitRemark(
+ "TritonRaiseBlockPointer: do not support adding two point... | ```suggestion
assert(!(lhsState.hasModulo() || rhsState.hasModulo()) || (lhsState.getRank() <= 2) && "description");
```
NIT: The conditional is only for debug code |
intel-xpu-backend-for-triton | github_2023 | others | 1,570 | intel | FMarno | @@ -236,3 +236,144 @@ tt.func @test_addptr_broadcast_rank_3(%arg0 : !tt.ptr<f32>) -> tensor<128x2x128x
%3 = tt.load %2 : tensor<128x2x128x!tt.ptr<f32>>
tt.return %3 : tensor<128x2x128xf32>
}
+
+
+// CHECK: tt.func public @wrap_side_by_side_masked([[PARAM_0_:%.+]]: !tt.ptr<f32>, [[PARAM_1_:%.+]]: !tt.ptr<... | Maybe the constant declaration should be check-dag since the order is not important? |
intel-xpu-backend-for-triton | github_2023 | others | 1,570 | intel | FMarno | @@ -236,3 +236,144 @@ tt.func @test_addptr_broadcast_rank_3(%arg0 : !tt.ptr<f32>) -> tensor<128x2x128x
%3 = tt.load %2 : tensor<128x2x128x!tt.ptr<f32>>
tt.return %3 : tensor<128x2x128xf32>
}
+
+
+// CHECK: tt.func public @wrap_side_by_side_masked([[PARAM_0_:%.+]]: !tt.ptr<f32>, [[PARAM_1_:%.+]]: !tt.ptr<... | ```suggestion
%c0_i32 = arith.constant 0 : i32
%c1_i32 = arith.constant 1 : i32
%c2_i32 = arith.constant 2 : i32
%c4_i32 = arith.constant 4 : i32
%cst_0 = arith.constant dense<2> : tensor<4x1xi32>
%cst_1 = arith.constant dense<6> : tensor<4xi32>
%cst_2 = arith.constant dense<2> : tens... |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,570 | intel | victor-eds | @@ -24,6 +24,59 @@ namespace {
constexpr unsigned offsetBitwidth = 32;
constexpr unsigned shapeAndStridesBitwidth = 64;
+std::optional<int64_t> getIntAttr(const OpFoldResult ofr) {
+ if (ofr.is<Attribute>() && isa<IntegerAttr>(ofr.get<Attribute>()))
+ return dyn_cast<IntegerAttr>(ofr.get<Attribute>()).getInt();... | Can we asssert on `op` having exactly 1 result? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,570 | intel | victor-eds | @@ -24,6 +24,59 @@ namespace {
constexpr unsigned offsetBitwidth = 32;
constexpr unsigned shapeAndStridesBitwidth = 64;
+std::optional<int64_t> getIntAttr(const OpFoldResult ofr) {
+ if (ofr.is<Attribute>() && isa<IntegerAttr>(ofr.get<Attribute>()))
+ return dyn_cast<IntegerAttr>(ofr.get<Attribute>()).getInt();... | ```suggestion
if (results.empty()) {
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,570 | intel | victor-eds | @@ -24,6 +24,59 @@ namespace {
constexpr unsigned offsetBitwidth = 32;
constexpr unsigned shapeAndStridesBitwidth = 64;
+std::optional<int64_t> getIntAttr(const OpFoldResult ofr) {
+ if (ofr.is<Attribute>() && isa<IntegerAttr>(ofr.get<Attribute>()))
+ return dyn_cast<IntegerAttr>(ofr.get<Attribute>()).getInt();... | Are we actually getting any constant value after this point? I'd expect this to be folded if result is `arith.constant` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,570 | intel | victor-eds | @@ -24,6 +24,59 @@ namespace {
constexpr unsigned offsetBitwidth = 32;
constexpr unsigned shapeAndStridesBitwidth = 64;
+std::optional<int64_t> getIntAttr(const OpFoldResult ofr) { | ```suggestion
std::optional<int64_t> getIntAttr(OpFoldResult ofr) {
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,570 | intel | victor-eds | @@ -24,6 +24,59 @@ namespace {
constexpr unsigned offsetBitwidth = 32;
constexpr unsigned shapeAndStridesBitwidth = 64;
+std::optional<int64_t> getIntAttr(const OpFoldResult ofr) {
+ if (ofr.is<Attribute>() && isa<IntegerAttr>(ofr.get<Attribute>()))
+ return dyn_cast<IntegerAttr>(ofr.get<Attribute>()).getInt();... | ```suggestion
bool hasConstZero(Value val) {
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,570 | intel | victor-eds | @@ -112,11 +169,72 @@ struct PtrState {
sizes.push_back(lhsState.sizes[i]);
}
+ // AddPtr where both lhs and rhs containing modulo operators not supported
+ if (lhsState.hasModulo() && rhsState.hasModulo()) {
+ op->emitRemark(
+ "TritonRaiseBlockPointer: do not support adding two point... | This will work if both have modulo, right? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,570 | intel | victor-eds | @@ -112,11 +169,72 @@ struct PtrState {
sizes.push_back(lhsState.sizes[i]);
}
+ // AddPtr where both lhs and rhs containing modulo operators not supported
+ if (lhsState.hasModulo() && rhsState.hasModulo()) {
+ op->emitRemark(
+ "TritonRaiseBlockPointer: do not support adding two point... | Does this correspond with "skipping"? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,570 | intel | victor-eds | @@ -112,11 +169,72 @@ struct PtrState {
sizes.push_back(lhsState.sizes[i]);
}
+ // AddPtr where both lhs and rhs containing modulo operators not supported
+ if (lhsState.hasModulo() && rhsState.hasModulo()) {
+ op->emitRemark(
+ "TritonRaiseBlockPointer: do not support adding two point... | Can we have this out of the loop as this will only happen in the first iteration and break out of the loop? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,570 | intel | victor-eds | @@ -377,6 +510,82 @@ struct TritonRaiseBlockPointer
IRMapping ptrMap;
};
+template <typename OpTy, typename = std::enable_if_t<llvm::is_one_of<
+ OpTy, arith::RemSIOp, arith::RemUIOp>::value>>
+LogicalResult TritonRaiseBlockPointer::visitAddPointerRemOperand(
+ OpTy remOp, PtrState ... | NIT: `failed(...)` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,570 | intel | victor-eds | @@ -377,6 +510,82 @@ struct TritonRaiseBlockPointer
IRMapping ptrMap;
};
+template <typename OpTy, typename = std::enable_if_t<llvm::is_one_of<
+ OpTy, arith::RemSIOp, arith::RemUIOp>::value>>
+LogicalResult TritonRaiseBlockPointer::visitAddPointerRemOperand(
+ OpTy remOp, PtrState ... | NIT: `failed(...)` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,570 | intel | victor-eds | @@ -377,6 +510,82 @@ struct TritonRaiseBlockPointer
IRMapping ptrMap;
};
+template <typename OpTy, typename = std::enable_if_t<llvm::is_one_of<
+ OpTy, arith::RemSIOp, arith::RemUIOp>::value>>
+LogicalResult TritonRaiseBlockPointer::visitAddPointerRemOperand(
+ OpTy remOp, PtrState ... | I would not worry much about this case, as I guess the canonicalizer should simplify this beforehand, but cool to check |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,570 | intel | victor-eds | @@ -377,6 +510,82 @@ struct TritonRaiseBlockPointer
IRMapping ptrMap;
};
+template <typename OpTy, typename = std::enable_if_t<llvm::is_one_of<
+ OpTy, arith::RemSIOp, arith::RemUIOp>::value>>
+LogicalResult TritonRaiseBlockPointer::visitAddPointerRemOperand(
+ OpTy remOp, PtrState ... | If this can cause issues, can we maybe change the order in an earlier pass? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,570 | intel | victor-eds | @@ -377,6 +510,82 @@ struct TritonRaiseBlockPointer
IRMapping ptrMap;
};
+template <typename OpTy, typename = std::enable_if_t<llvm::is_one_of<
+ OpTy, arith::RemSIOp, arith::RemUIOp>::value>>
+LogicalResult TritonRaiseBlockPointer::visitAddPointerRemOperand(
+ OpTy remOp, PtrState ... | Format |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,570 | intel | victor-eds | @@ -112,11 +169,72 @@ struct PtrState {
sizes.push_back(lhsState.sizes[i]);
}
+ // AddPtr where both lhs and rhs containing modulo operators not supported
+ if (lhsState.hasModulo() && rhsState.hasModulo()) {
+ op->emitRemark(
+ "TritonRaiseBlockPointer: do not support adding two point... | Format |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,570 | intel | etiotto | @@ -377,6 +478,81 @@ struct TritonRaiseBlockPointer
IRMapping ptrMap;
};
+template <typename OpTy, typename = std::enable_if_t<llvm::is_one_of<
+ OpTy, arith::RemSIOp, arith::RemUIOp>::value>>
+LogicalResult TritonRaiseBlockPointer::visitAddPointerRemOperand(
+ OpTy remOp, PtrState ... | Change to switch stmt |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,570 | intel | whitneywhtsang | @@ -113,11 +155,55 @@ struct PtrState {
sizes.push_back(lhsState.sizes[i]);
}
+ // AddPtr where both lhs and rhs containing modulo operators not supported
+ if (lhsState.hasModulo() && rhsState.hasModulo()) {
+ op->emitRemark(
+ "TritonRaiseBlockPointer: do not support adding two point... | Please update the comment if it is no longer the case. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,746 | intel | chengjunlu | @@ -397,31 +497,68 @@ std::optional<LinearLayout> DPAStoLinearLayout(ArrayRef<int64_t> shape,
const SmallVector<unsigned> warpsPerCTA = dpas.getWarpsPerCTA();
int threadsPerWarp = triton::gpu::getWarpSize(dpas);
+ unsigned opsPerChannel = dpas.getOpsPerChannel();
auto repCluster = dpas.getRepCluster();
- S... | I think the logic should be different for A, B and C on the warp dimension.
The A operands are duplicated on row dimension and B operands are duplicated on column dimension.
In another word, some warp hop should be 0 stride for A and B. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,746 | intel | etiotto | @@ -379,11 +479,11 @@ DPASLaneBasesC(int repeatCount, int executionSize, int threadsPerWarp) {
return laneBases;
}
-std::optional<LinearLayout> DPAStoLinearLayout(ArrayRef<int64_t> shape,
- Attribute layout) {
+std::optional<LinearLayout>
+DPAStoLinearLayout(ArrayRef<... | assert opIdx <3 on function entry |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,746 | intel | etiotto | @@ -397,33 +497,82 @@ std::optional<LinearLayout> DPAStoLinearLayout(ArrayRef<int64_t> shape,
const SmallVector<unsigned> warpsPerCTA = dpas.getWarpsPerCTA();
int threadsPerWarp = triton::gpu::getWarpSize(dpas);
+ unsigned opsPerChannel = dpas.getOpsPerChannel();
auto repCluster = dpas.getRepCluster();
- S... | For simplicity I would place these 2 lines before the `if` (is true that both aren't needed unless opIdx == 2 but I think is fine). |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,746 | intel | etiotto | @@ -397,33 +497,82 @@ std::optional<LinearLayout> DPAStoLinearLayout(ArrayRef<int64_t> shape,
const SmallVector<unsigned> warpsPerCTA = dpas.getWarpsPerCTA();
int threadsPerWarp = triton::gpu::getWarpSize(dpas);
+ unsigned opsPerChannel = dpas.getOpsPerChannel();
auto repCluster = dpas.getRepCluster();
- S... | [nit]: Initialize KDim to zero (its value is overwritten in all possible code path the if stmt can take) |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,746 | intel | etiotto | @@ -336,7 +336,109 @@ LinearLayout combineCtaCgaWithShape(LinearLayout ctaLayout,
// The layout example repeat_count=8, systolic_depth=8,
// execution_size=16 and operands_per_chan=2 for warp size 32.
-// DPASInst layout of C operand:
+// For A operand:
+// systolic depth = 8
+//<-----------------... | [nit]: opc *= 2 for the step |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,746 | intel | etiotto | @@ -336,7 +336,109 @@ LinearLayout combineCtaCgaWithShape(LinearLayout ctaLayout,
// The layout example repeat_count=8, systolic_depth=8,
// execution_size=16 and operands_per_chan=2 for warp size 32.
-// DPASInst layout of C operand:
+// For A operand:
+// systolic depth = 8
+//<-----------------... | [nit]: warp *= 2 for the step |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,746 | intel | etiotto | @@ -336,7 +336,109 @@ LinearLayout combineCtaCgaWithShape(LinearLayout ctaLayout,
// The layout example repeat_count=8, systolic_depth=8,
// execution_size=16 and operands_per_chan=2 for warp size 32.
-// DPASInst layout of C operand:
+// For A operand:
+// systolic depth = 8
+//<-----------------... | [nit]: remove empty line |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,746 | intel | etiotto | @@ -336,7 +336,109 @@ LinearLayout combineCtaCgaWithShape(LinearLayout ctaLayout,
// The layout example repeat_count=8, systolic_depth=8,
// execution_size=16 and operands_per_chan=2 for warp size 32.
-// DPASInst layout of C operand:
+// For A operand:
+// systolic depth = 8
+//<-----------------... | Can we use SmallVector ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,669 | intel | FMarno | @@ -774,6 +775,11 @@ void MatchTargetSizePass::transformDotOp(tt::DotOp dot) {
subDotC = b.create<tt::DotOp>(loc, subDotA, subDotB, subDotC,
dot.getInputPrecisionAttr(),
dot.getMaxNumImpreciseAccAttr());
+ // hack for attentio... | Why can this not be enabled by default?
I believe at this time we are trying to remove the hacks and do things properly |
intel-xpu-backend-for-triton | github_2023 | others | 1,669 | intel | FMarno | @@ -243,4 +243,19 @@ def TritonIntelGPUMatchTargetSize : Pass<"tritonintelgpu-match-target-size", "ml
"mlir::triton::gpu::intel::TritonIntelGPUDialect"];
}
+def TritonIntelGPUScheduleLoad : Pass<"tritonintelgpu-schedule-load", "mlir::ModuleOp"> {
+ let summary = "naive ra-aware instr sch... | what is RA? |
intel-xpu-backend-for-triton | github_2023 | others | 1,669 | intel | FMarno | @@ -243,4 +243,19 @@ def TritonIntelGPUMatchTargetSize : Pass<"tritonintelgpu-match-target-size", "ml
"mlir::triton::gpu::intel::TritonIntelGPUDialect"];
}
+def TritonIntelGPUScheduleLoad : Pass<"tritonintelgpu-schedule-load", "mlir::ModuleOp"> {
+ let summary = "naive ra-aware instr sch... | Can we try to be more general that just FlashAttention. Maybe mention the features of the workloads that this optimizes? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,669 | intel | FMarno | @@ -0,0 +1,133 @@
+//===- ScheduleLoad.cpp ----------------------------------------------*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===-----... | The use of the function is confusing since it has side effects (modifying `visited`) and returns another value. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,669 | intel | FMarno | @@ -0,0 +1,133 @@
+//===- ScheduleLoad.cpp ----------------------------------------------*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===-----... | Please detail the goals of the scheduler |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,669 | intel | FMarno | @@ -0,0 +1,133 @@
+//===- ScheduleLoad.cpp ----------------------------------------------*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===-----... | I don't think this change fits in here with the scheduling changes |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,669 | intel | FMarno | @@ -0,0 +1,133 @@
+//===- ScheduleLoad.cpp ----------------------------------------------*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===-----... | you're assigning a negative to an unsigned, maybe use `int` or `int64_t` instead? I believe the return type of `IntegerAttr::getInt` is `int64_t`. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,669 | intel | FMarno | @@ -0,0 +1,133 @@
+//===- ScheduleLoad.cpp ----------------------------------------------*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===-----... | why 4? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,669 | intel | FMarno | @@ -0,0 +1,133 @@
+//===- ScheduleLoad.cpp ----------------------------------------------*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===-----... | ```suggestion
if (visited.contains(val))
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,669 | intel | FMarno | @@ -0,0 +1,133 @@
+//===- ScheduleLoad.cpp ----------------------------------------------*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===-----... | ```suggestion
if (!visited.contains(base)) {
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,669 | intel | FMarno | @@ -0,0 +1,133 @@
+//===- ScheduleLoad.cpp ----------------------------------------------*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===-----... | ```suggestion
unsigned opIdx) {
```
This default makes the code less readable by adding extra information to remember without saving much typing |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,669 | intel | FMarno | @@ -0,0 +1,133 @@
+//===- ScheduleLoad.cpp ----------------------------------------------*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===-----... | Why are we visiting without doing anything for `currGroup == 0`? it would be good to add a code comment for that |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,669 | intel | FMarno | @@ -0,0 +1,133 @@
+//===- ScheduleLoad.cpp ----------------------------------------------*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===-----... | If I understand the code correctly, you are grouping instances of `DotOp` with the same value for `schedule-group`. Why not use something like an [`IndexedMap`](https://llvm.org/docs/ProgrammersManual.html#llvm-adt-indexedmap-h) or a [`DenseMap`](https://llvm.org/docs/ProgrammersManual.html#llvm-adt-densemap-h)? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,669 | intel | whitneywhtsang | @@ -0,0 +1,143 @@
+//===- ScheduleLoad.cpp ----------------------------------------------*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===-----... | remove |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,669 | intel | whitneywhtsang | @@ -0,0 +1,143 @@
+//===- ScheduleLoad.cpp ----------------------------------------------*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===-----... | what happen if the attribute is not present? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,669 | intel | FMarno | @@ -0,0 +1,143 @@
+//===- ScheduleLoad.cpp ----------------------------------------------*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===-----... | I'm not sure this is working as intended since `numGroups` will be `0` and it was previously `4`. |
intel-xpu-backend-for-triton | github_2023 | others | 1,392 | intel | YarShev | @@ -0,0 +1,29 @@
+# Developer Guide
+
+This short guide covers creating a basic development environment, installing needed dependencies, and best practices for building and running Triton on different Intel platforms. | ```suggestion
This short guide covers creating a basic development environment, installing needed dependencies, and
best practices for building and running Triton on different Intel platforms.
```
To not have long lines I would break these and all below. |
intel-xpu-backend-for-triton | github_2023 | others | 1,392 | intel | YarShev | @@ -0,0 +1,29 @@
+# Developer Guide
+
+This short guide covers creating a basic development environment, installing needed dependencies, and best practices for building and running Triton on different Intel platforms.
+
+## Dependencies
+
+The primary software dependency is oneAPI. The best way to get oneAPI for PyTo... | ```suggestion
The LTS, Production, and Rolling Stable release streams are supported. Some performance optimizations may not be available with the LTS driver package. For development, we recommend rolling stable.
``` |
intel-xpu-backend-for-triton | github_2023 | others | 1,392 | intel | vlad-penkin | @@ -0,0 +1,29 @@
+# Developer Guide | I suggest to add a section dedicated to the python base envs and offer two alternatives:
- virtualenv
- conda
For conda the recommended setup is `conda create -n xpu -c conda-forge python=3.10 gh jq` and then do pip install if needed for everything else. |
intel-xpu-backend-for-triton | github_2023 | others | 1,392 | intel | vlad-penkin | @@ -0,0 +1,29 @@
+# Developer Guide
+
+This short guide covers creating a basic development environment, installing needed dependencies, and best practices for building and running Triton on different Intel platforms.
+
+## Dependencies
+
+The primary software dependency is oneAPI. The best way to get oneAPI for PyTorc... | 1) I suggest to provide the recommendation on the packaging option. My preference is offline installer - it's much more easier to maintain, delete from the system. Offline installer will also allow you to have multiple installs on the same machine (PTDB and Regular oneAPI Base Kit).
2) Lets add recommended env activ... |
intel-xpu-backend-for-triton | github_2023 | others | 1,392 | intel | vlad-penkin | @@ -0,0 +1,29 @@
+# Developer Guide
+
+This short guide covers creating a basic development environment, installing needed dependencies, and best practices for building and running Triton on different Intel platforms.
+
+## Dependencies
+
+The primary software dependency is oneAPI. The best way to get oneAPI for PyTorc... | conda-forge binaries are usually up-to-date and a viable option to - `conda -c conda-forge install gh` |
intel-xpu-backend-for-triton | github_2023 | others | 1,392 | intel | YarShev | @@ -0,0 +1,31 @@
+# Developer Guide
+
+This short guide covers creating a basic development environment, installing needed dependencies, and best practices for building and running Triton on different Intel platforms.
+
+## Dependencies
+
+The primary software dependency is oneAPI. The best way to get oneAPI for PyTorc... | Why are we missing "Step 1: Install Intel Data Center GPU Drivers"? |
intel-xpu-backend-for-triton | github_2023 | others | 1,711 | intel | whitneywhtsang | @@ -324,6 +324,10 @@ jobs:
- name: Run triton gemm kernel benchmark
run: |
cd benchmarks/triton_kernels_benchmark
+ # Dry run to validate no functionality regression for splitk and streamk in defaul path | ```suggestion
# Dry run to validate no functionality regression for splitk and streamk in default path
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | victor-eds | @@ -58,6 +58,39 @@ namespace {
/// Import the GPU Ops to TritonGEN Patterns.
#include "GPUToTritonGEN.cpp.inc"
+struct GPUSubgroupReduceOpLowering
+ : public ConvertOpToLLVMPattern<mlir::gpu::SubgroupReduceOp> {
+ using ConvertOpToLLVMPattern<
+ mlir::gpu::SubgroupReduceOp>::ConvertOpToLLVMPattern;
+ Logi... | ```suggestion
LogicalResult
matchAndRewrite(mlir::gpu::SubgroupReduceOp op, OpAdaptor adaptor,
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | victor-eds | @@ -58,6 +58,39 @@ namespace {
/// Import the GPU Ops to TritonGEN Patterns.
#include "GPUToTritonGEN.cpp.inc"
+struct GPUSubgroupReduceOpLowering
+ : public ConvertOpToLLVMPattern<mlir::gpu::SubgroupReduceOp> {
+ using ConvertOpToLLVMPattern<
+ mlir::gpu::SubgroupReduceOp>::ConvertOpToLLVMPattern;
+ Logi... | Are we expecting non-uniform reductions? SPIR-V supports non-uniform reductions, so we could lower to those if needed here. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | victor-eds | @@ -58,6 +58,39 @@ namespace {
/// Import the GPU Ops to TritonGEN Patterns.
#include "GPUToTritonGEN.cpp.inc"
+struct GPUSubgroupReduceOpLowering
+ : public ConvertOpToLLVMPattern<mlir::gpu::SubgroupReduceOp> {
+ using ConvertOpToLLVMPattern<
+ mlir::gpu::SubgroupReduceOp>::ConvertOpToLLVMPattern;
+ Logi... | Can we have this in a function on its own and covering all of the possible values? We may run into other reductions. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | victor-eds | @@ -58,6 +58,39 @@ namespace {
/// Import the GPU Ops to TritonGEN Patterns.
#include "GPUToTritonGEN.cpp.inc"
+struct GPUSubgroupReduceOpLowering
+ : public ConvertOpToLLVMPattern<mlir::gpu::SubgroupReduceOp> {
+ using ConvertOpToLLVMPattern<
+ mlir::gpu::SubgroupReduceOp>::ConvertOpToLLVMPattern;
+ Logi... | Shouldn't we use subgroup size here instead of 32? I understand using a number different than subgroup size will lead to using `WaveAll` and that might give better performance, but that is not what `gpu.subgroup_reduce` represents. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | victor-eds | @@ -92,8 +92,13 @@ struct ConvertTritonGPUToLLVM
int numCTAs = triton::gpu::TritonGPUDialect::getNumCTAs(mod);
int threadsPerWarp = triton::gpu::TritonGPUDialect::getThreadsPerWarp(mod);
- // Allocate shared memory and set barrier
- if (!pipelineManager.skipSharedMemoryAllocation()) {
+ // fixed 0 ... | ```suggestion
Builder builder(context);
mod->setAttr(
"triton_gpu.shared",
builder.getI32IntegerAttr(0));
```
Why do we need this anyway? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | victor-eds | @@ -189,6 +195,17 @@ class LoadStorePrefetchOpConversion
getVectorType(cast<RankedTensorType>(op.getResult().getType()),
isDword ? i32_ty : i16_ty);
bool vnni = (idx == 1) && dataSize < 32;
+ // fixed f16 for now | Why? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | victor-eds | @@ -170,16 +173,19 @@ class LoadStorePrefetchOpConversion
return truncatedShape;
};
- Value surfaceW = calculateSurface(ptrOp.getShape()[1], true);
- Value surfaceH = calculateSurface(ptrOp.getShape()[0], false);
- Value surfaceP = calculateSurface(ptrOp.getStrides()[0], true);
+ Value surface... | I see at the beginning of the function we're asserting the op is 2D. Should we fail conversion instead? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | victor-eds | @@ -198,7 +215,14 @@ class LoadStorePrefetchOpConversion
return failure();
}
rewriter.replaceOp(op, bitcast(load, resType));
- } else if constexpr (std::is_same_v<OpType, PrefetchOp>) {
+ } else if constexpr (std::is_same_v<OpType, ttgi::PrefetchOp>) {
+ if (ptrOp.getOrder()[0] == 0) {... | Use `std::swap` |
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