repo_name stringlengths 1 62 | dataset stringclasses 1
value | lang stringclasses 11
values | pr_id int64 1 20.1k | owner stringlengths 2 34 | reviewer stringlengths 2 39 | diff_hunk stringlengths 15 262k | code_review_comment stringlengths 1 99.6k |
|---|---|---|---|---|---|---|---|
intel-xpu-backend-for-triton | github_2023 | cpp | 877 | intel | etiotto | @@ -0,0 +1,89 @@
+#pragma once | Add copyright |
intel-xpu-backend-for-triton | github_2023 | cpp | 877 | intel | etiotto | @@ -0,0 +1,102 @@
+#include "softmax.h" | Add copyright |
intel-xpu-backend-for-triton | github_2023 | others | 877 | intel | pbchekin | @@ -0,0 +1,3 @@
+[submodule "benchmark/third_party/xetla"] | Please don't use submodules. Instead consider using an external repository in the same way as we currently use llvm, e2e benchmarks, and so on. |
intel-xpu-backend-for-triton | github_2023 | others | 877 | intel | pbchekin | @@ -0,0 +1,121 @@
+name: Triton-benchmarks
+
+on:
+ workflow_dispatch:
+ inputs:
+ runner_label:
+ description: Runner label, keep empty for default
+ type: string
+ default: ""
+ pull_request:
+ branches:
+ - llvm-target
+ push:
+ branches:
+ - llvm-target | Do you want to remove this before merging? Running manually is fine, you can also run it daily/nightly if you want but running for each commit is too much IMHO. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,062 | intel | etiotto | @@ -95,21 +95,15 @@ LogicalResult TritonGEN::MatrixDPASOp::verify() {
return this->emitOpError("the dimension for 1st operand (C) and "
"result (D) should match repeat count");
+ constexpr unsigned SD = 8;
+ if (BTy.getNumElements() != SD)
+ return this->emitOpError(
+ "... | suggest: "the dimension for the 3rd operand (B) should match the systolic depth of 8" |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,062 | intel | etiotto | @@ -121,31 +115,31 @@ LogicalResult TritonGEN::MatrixDPASOp::verify() {
switch (precision) {
case TritonGEN::PrecisionType::TF32:
+ if (ATy.getNumElements() != getRc() / 2)
+ return this->emitOpError("the dimension for 2nd operand (A) should match " | suggest: the dimension for the 2nd operand (A) should be equal to half of the repeat count |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,062 | intel | etiotto | @@ -121,31 +115,31 @@ LogicalResult TritonGEN::MatrixDPASOp::verify() {
switch (precision) {
case TritonGEN::PrecisionType::TF32:
+ if (ATy.getNumElements() != getRc() / 2)
+ return this->emitOpError("the dimension for 2nd operand (A) should match "
+ "half the repeat count... | suggest: "when precision type is tf32" -> "when the precision type is tf32" |
intel-xpu-backend-for-triton | github_2023 | python | 1,054 | intel | pbchekin | @@ -602,6 +602,7 @@ def get_install_requires():
"numpy",
"pytest",
"scipy>=1.7.1",
+ "pytest-capturewarnings-ng @ git+https://github.com/kwasd/pytest-capturewarnings-ng.git@v1.1#egg=src/pytest_capturewarnings_ng" | This file is from upstream, it is better to keep it as is. Instead, install this additional dependency directly in the workflow (build-test.yml) like you do in test-triton.sh. |
intel-xpu-backend-for-triton | github_2023 | python | 1,064 | intel | whitneywhtsang | @@ -233,7 +233,9 @@ def matmul(a, b):
# Note: the torch.matmul and Triton implementations uses different
# algorithms so we need to adjust tolerance.
-if torch.allclose(triton_output, torch_output, atol=1e-4, rtol=1e-3):
+allclose = torch.allclose(triton_output, torch_output, atol=1e-4, rtol=1e-3)
+assert allclose,... | ```suggestion
if torch.allclose(triton_output, torch_output, atol=1e-4, rtol=1e-3):
print("✅ Triton and Torch match")
else:
exit("❌ Triton and Torch differ")
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,064 | intel | whitneywhtsang | @@ -153,6 +153,14 @@ class MatchTargetSizePass
canonicalize();
LLVM_DEBUG(llvm::dbgs() << "Module after canonicalization:\n"
<< m << "\n\n");
+
+ // by default, tritongpu are lowered to simt mode(threads-per-warp=16)
+ // instead of simd mode(threads-per-warp=1) | ```suggestion
// By default, tritongpu are lowered to simt mode (threads-per-warp=16)
// instead of simd mode (threads-per-warp=1).
``` |
intel-xpu-backend-for-triton | github_2023 | others | 1,029 | intel | etiotto | @@ -511,6 +704,66 @@ module attributes {"triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 1 :
// -----
+#blocked0 = #triton_gpu.blocked<{sizePerThread = [1, 4], threadsPerWarp = [8, 2], warpsPerCTA = [1, 1], order = [1, 0], CTAsPerCGA = [1, 1], CTASplitNum = [1, 1], CTAOrder = [1, 0]}>
+#shared0 = #triton_... | Instead of using #mma0 (and similar names) use #dpas as that term is more meaningful for Intel |
intel-xpu-backend-for-triton | github_2023 | others | 1,012 | intel | whitneywhtsang | @@ -219,13 +219,17 @@ def TritonIntelGPUPrefetchBlock : Pass<"tritonintelgpu-prefetch-block", "mlir::M
let constructor = "mlir::triton::gpu::intel::createPrefetchBlockPass()";
let dependentDialects = ["mlir::triton::TritonDialect",
+ "mlir::triton::TritonGEN::TritonGENDialect",
... | optional: `num-stages` could be a better name as it is used to determine the prefetch distance for other backends. |
intel-xpu-backend-for-triton | github_2023 | others | 1,012 | intel | whitneywhtsang | @@ -219,13 +219,17 @@ def TritonIntelGPUPrefetchBlock : Pass<"tritonintelgpu-prefetch-block", "mlir::M
let constructor = "mlir::triton::gpu::intel::createPrefetchBlockPass()";
let dependentDialects = ["mlir::triton::TritonDialect",
+ "mlir::triton::TritonGEN::TritonGENDialect",
... | can we default to false until we test it? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,012 | intel | Dewei-Wang-sh | @@ -360,6 +361,19 @@ void PrefetchBlockPass::injectPrefetchOpsInPreheader(
prefetchPtrs.push_back(currPtr);
}
+
+ // FIXME: try to use a named barrier to increase performance.
+ if (injectSplitBarriers) { | at stages before convert-tritongpu-to-llvm, we can make it target independent.
an alternative would be to generate gpu.barrier/ttgi.barrier and lower it to split-barrier in convert-tritongpu-to-llvm.
|
intel-xpu-backend-for-triton | github_2023 | cpp | 1,041 | intel | etiotto | @@ -218,14 +218,49 @@ static LLVM::CallOp createGenISADPAS(TritonGEN::MatrixDPASOp op,
return rewriter.create<LLVM::CallOp>(loc, funcOp, args);
}
+static bool isOCLAvailable(TritonGEN::Matrix2DBlockLoadOp op) { | isOCLAvailable -> isOCLAPIAvailable |
intel-xpu-backend-for-triton | github_2023 | python | 1,030 | intel | pbchekin | @@ -8,12 +8,17 @@
from triton.backends.driver import DriverBase
dirname = os.getenv("ZE_PATH", default="/usr/local")
-oneapi_root = os.getenv("ONEAPI_ROOT", default="/opt/intel/oneapi")
-include_dir = [
- os.path.join(dirname, "include"),
- os.path.join(oneapi_root, "compiler/latest/include"),
- os.path.jo... | Is it used? |
intel-xpu-backend-for-triton | github_2023 | others | 1,030 | intel | pbchekin | @@ -0,0 +1,127 @@
+name: Conda Basekit build and test
+
+on:
+ workflow_dispatch:
+ schedule:
+ - cron: "5 2 * * *"
+
+permissions: read-all
+
+env:
+ BACKEND: XPU | Not used, not required. |
intel-xpu-backend-for-triton | github_2023 | others | 1,030 | intel | pbchekin | @@ -0,0 +1,127 @@
+name: Conda Basekit build and test
+
+on:
+ workflow_dispatch:
+ schedule:
+ - cron: "5 2 * * *"
+
+permissions: read-all
+
+env:
+ BACKEND: XPU
+ TRITON_DISABLE_LINE_INFO: 1
+ GH_TOKEN: ${{ github.token }} | Is it required on the top level? It can be set for a specific step only. |
intel-xpu-backend-for-triton | github_2023 | cpp | 835 | intel | etiotto | @@ -318,42 +320,72 @@ struct ReduceOpConversion
Value zero = i32_val(0);
auto mod = op.getOperation()->getParentOfType<ModuleOp>();
+ unsigned threadsPerWarp =
+ triton::gpu::TritonGPUDialect::getThreadsPerWarp(mod);
+ assert(threadsPerWarp > 1 &&
+ "threadsPerWarp must be larger than... | Instead of hard coding 3 (for local memory) can we introduce an enum in the `TritonIntelGPU` dialect (TritonIntelGPUDialect.h) and use the enumerator. For example:
```
enum TritonIntelGPUMemorySpace {
kFunction = 0, // Workitem address space
kCrossWorkgroup = 1, // Global memory
kUniformCons... |
intel-xpu-backend-for-triton | github_2023 | cpp | 835 | intel | etiotto | @@ -318,42 +320,72 @@ struct ReduceOpConversion
Value zero = i32_val(0);
auto mod = op.getOperation()->getParentOfType<ModuleOp>();
+ unsigned threadsPerWarp =
+ triton::gpu::TritonGPUDialect::getThreadsPerWarp(mod);
+ assert(threadsPerWarp > 1 &&
+ "threadsPerWarp must be larger than... | Use enumerator instead of "3". |
intel-xpu-backend-for-triton | github_2023 | python | 835 | intel | etiotto | @@ -2007,7 +2008,8 @@ def kernel(X, Z, BLOCK: tl.constexpr):
z_ref = numpy_op(x).astype(getattr(np, z_dtype_str))
# triton result
z_tri = to_triton(numpy_random((1, ), dtype_str=z_dtype_str, rs=rs), device=device, dst_type=z_tri_dtype_str)
- kernel[(1, )](x_tri, z_tri, BLOCK=shape, num_ctas=num_ct... | The interpreter does not understand the `threads_per_warp` argument. |
intel-xpu-backend-for-triton | github_2023 | python | 835 | intel | ienkovich | @@ -1958,7 +1958,8 @@ def get_reduced_dtype(dtype_str, op):
'sum',
] for dtype in dtypes_with_bfloat16 for shape in [32, 64, 128, 512]])
@pytest.mark.parametrize("num_ctas", num_ctas_list)
-def test_reduce1d(op, dtype_str, shape, num_ctas, device):
+@pytest.mark.parametrize("multi_threads", [(64, 16), (4, 32)] i... | Pytest parameters support tuples, so `"num_warps, threads_per_warp"` would be clearer than `"multi_threads"`. |
intel-xpu-backend-for-triton | github_2023 | python | 835 | intel | etiotto | @@ -1958,7 +1958,8 @@ def get_reduced_dtype(dtype_str, op):
'sum',
] for dtype in dtypes_with_bfloat16 for shape in [32, 64, 128, 512]])
@pytest.mark.parametrize("num_ctas", num_ctas_list)
-def test_reduce1d(op, dtype_str, shape, num_ctas, device):
+@pytest.mark.parametrize("num_warps, threads_per_warp", [(64, 1... | change all instances of 32 to THREADS_PER_WARP. |
intel-xpu-backend-for-triton | github_2023 | python | 835 | intel | etiotto | @@ -2061,7 +2066,8 @@ def kernel(X, Z, BLOCK: tl.constexpr):
"op, dtype_str, shape, axis, keep_dims", reduce_configs1 + reduce_configs2 + reduce_configs3 + invalid_config +
negative_config + keep_dims_2d_configs + keep_dims_3d_configs)
@pytest.mark.parametrize("num_ctas", num_ctas_list)
-def test_reduce(op, ... | change all instances of 32 to THREADS_PER_WARP. |
intel-xpu-backend-for-triton | github_2023 | others | 835 | intel | etiotto | @@ -0,0 +1,54 @@
+// RUN: triton-opt %s -split-input-file --intel-allocate-shared-memory --convert-triton-intel-gpu-to-llvm | FileCheck %s --implicit-check-not=llvm.inline_asm
+
+#blocked = #triton_gpu.blocked<{sizePerThread = [1], threadsPerWarp = [32], warpsPerCTA = [64], order = [0], CTAsPerCGA = [1], CTASplitNum =... | Add:
// COM: Tests reduction when threads_per_warp < num_warps. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,035 | intel | whitneywhtsang | @@ -1,10 +1,12 @@
#pragma once
-#include "third_party/intel/include/Dialect/TritonGEN/IR/TritonGENDialect.h"
-#include "third_party/nvidia/include/Dialect/NVGPU/IR/Dialect.h"
-
+#include "intel/include/Dialect/TritonGEN/IR/TritonGENDialect.h"
+#include "intel/include/Dialect/TritonIntelGPU/IR/Dialect.h"
+#include "int... | why change nvidia include? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,035 | intel | whitneywhtsang | @@ -2,11 +2,17 @@
#include "mlir/IR/TypeUtilities.h"
#include "mlir/Support/LogicalResult.h"
#include "mlir/Transforms/GreedyPatternRewriteDriver.h"
+
+#include "intel/include/Dialect/TritonIntelGPU/IR/Dialect.h"
+#include "intel/include/Dialect/TritonIntelGPU/Transforms/Passes.h"
+#include "intel/include/Dialect/Tr... | ```suggestion
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,035 | intel | whitneywhtsang | @@ -1,12 +1,12 @@
#include "Schedule.h"
#include "include/triton/Dialect/TritonGPU/Transforms/Utility.h"
+#include "intel/include/Dialect/TritonIntelGPU/IR/Dialect.h"
#include "mlir/Dialect/SCF/Transforms/Transforms.h"
#include "mlir/IR/TypeUtilities.h"
#include "mlir/Interfaces/SideEffectInterfaces.h"
#include "... | ```suggestion
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,035 | intel | whitneywhtsang | @@ -37,24 +37,25 @@
/// tt.advance %prefetch_ptr
//===----------------------------------------------------------------------===//
-#include "llvm/ADT/SmallVector.h"
-#include "llvm/Support/Debug.h"
-
#include "mlir/Dialect/SCF/IR/SCF.h"
#include "mlir/IR/BuiltinAttributes.h"
#include "mlir/IR/PatternMatch.h"... | ```suggestion
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,035 | intel | whitneywhtsang | @@ -7,14 +7,17 @@
#include "mlir/Pass/PassManager.h"
#include "mlir/Support/LogicalResult.h"
#include "mlir/Transforms/GreedyPatternRewriteDriver.h"
+
+#include "intel/include/Dialect/TritonIntelGPU/IR/Dialect.h" | ```suggestion
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,035 | intel | whitneywhtsang | @@ -1,8 +1,18 @@
-#include "intel/include/TritonIntelGPUToLLVM/Passes.h"
+// #include "mlir/Pass/Pass.h" | ```suggestion
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,035 | intel | whitneywhtsang | @@ -1,8 +1,18 @@
-#include "intel/include/TritonIntelGPUToLLVM/Passes.h"
+// #include "mlir/Pass/Pass.h"
#include "mlir/Pass/PassManager.h"
+#include "passes.h"
+
+#include "intel/include/Dialect/TritonGEN/IR/TritonGENDialect.h"
+#include "intel/include/Dialect/TritonIntelGPU/IR/Dialect.h"
+#include "intel/include/Dia... | ```suggestion
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,035 | intel | whitneywhtsang | @@ -4,12 +4,15 @@
#include "mlir/IR/DialectImplementation.h"
#include "mlir/IR/OpImplementation.h"
+
+#include "intel/include/Dialect/TritonIntelGPU/IR/Dialect.h" | Maybe this can be removed? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,021 | intel | whitneywhtsang | @@ -41,7 +37,7 @@ bool isDivisible(Value value, unsigned divisor) {
if (value.getParentBlock()->isEntryBlock() && isa<BlockArgument>(value)) {
BlockArgument blockArg = cast<BlockArgument>(value);
Operation *parentOp = blockArg.getOwner()->getParentOp();
- if (auto funcOp = dyn_cast<tt::FuncOp>(parentOp)... | why this change? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,021 | intel | whitneywhtsang | @@ -320,14 +316,14 @@ struct RewritedInfo {
// very fragile and to solve we should expose convert Ptr of tensor to a
// structure contains all values and not only offsets.
class TritonIntelGPURewriteTensorPointerPass
- : public impl::TritonIntelGPURewriteTensorPointerBase<
+ : public triton::gpu::intel::impl::... | ```suggestion
: public ttgi::impl::TritonIntelGPURewriteTensorPointerBase<
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,021 | intel | whitneywhtsang | @@ -320,14 +316,14 @@ struct RewritedInfo {
// very fragile and to solve we should expose convert Ptr of tensor to a
// structure contains all values and not only offsets.
class TritonIntelGPURewriteTensorPointerPass
- : public impl::TritonIntelGPURewriteTensorPointerBase<
+ : public triton::gpu::intel::impl::... | ```suggestion
using ttgi::impl::TritonIntelGPURewriteTensorPointerBase<
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,021 | intel | whitneywhtsang | @@ -23,16 +11,24 @@ namespace ttg = mlir::triton::gpu;
namespace ttgi = mlir::triton::gpu::intel;
namespace mlir { | ```suggestion
namespace mlir::triton::gpu::intel {
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,021 | intel | whitneywhtsang | @@ -13,27 +13,21 @@
#include "intel/include/Dialect/TritonGEN/IR/TritonGENDialect.h"
-namespace mlir {
-namespace triton {
-namespace gpu {
-namespace intel {
+namespace mlir ::triton ::gpu::intel { | ```suggestion
namespace mlir::triton::gpu::intel {
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,021 | intel | whitneywhtsang | @@ -1177,8 +1172,9 @@ void hoistConvert(ModuleOp module) {
}
class TritonIntelGPURemoveLayoutConversionsPass
- : public impl::TritonIntelGPURemoveLayoutConversionsBase<
- TritonIntelGPURemoveLayoutConversionsPass> {
+ : public triton::gpu::intel::impl:: | ```suggestion
: public intel::impl::
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,024 | intel | whitneywhtsang | @@ -1,7 +1,9 @@
#pragma once
#include "third_party/nvidia/include/Dialect/NVGPU/IR/Dialect.h"
+
+#include "intel/include/Dialect/TritonGEN/IR/TritonGENDialect.h" | Why is it not "third_party/intel/..." for us? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,022 | intel | etiotto | @@ -264,82 +264,60 @@ emitOffsetForSliceLayout(const SliceEncodingAttr &sliceLayout,
// Get offsets / indices for any layout
// -----------------------------------------------------------------------
-static SmallVector<Value> emitCTAOffsetForLayout(Location loc,
- Re... | I think prefixing with `mlir::triton::` would be more clear. |
intel-xpu-backend-for-triton | github_2023 | others | 977 | intel | Dewei-Wang-sh | @@ -168,6 +168,14 @@ run_tutorial_tests() {
run_tutorial_test "06-fused-attention"
run_tutorial_test "07-extern-functions"
run_tutorial_test "08-grouped-gemm"
+ # Run block-pointer geem tutorial | ```suggestion
# Run block-pointer gemm tutorial
``` |
intel-xpu-backend-for-triton | github_2023 | others | 977 | intel | Dewei-Wang-sh | @@ -177,6 +177,14 @@ jobs:
python3 06-fused-attention.py
python3 07-extern-functions.py
python3 08-grouped-gemm.py
+ # Run block-pointer geem tutorial | ```suggestion
# Run block-pointer gemm tutorial
``` |
intel-xpu-backend-for-triton | github_2023 | python | 977 | intel | Dewei-Wang-sh | @@ -181,15 +187,14 @@ def matmul_kernel_with_block_pointers(
# See above `Advance a Block Pointer` section for details.
a_block_ptr = tl.advance(a_block_ptr, (0, BLOCK_SIZE_K))
b_block_ptr = tl.advance(b_block_ptr, (BLOCK_SIZE_K, 0))
- c = accumulator.to(tl.float16) | we can just comment it out for future use
the background here is that we use f32 to have a 1:1 comparison with Ben's opencl code. |
intel-xpu-backend-for-triton | github_2023 | python | 977 | intel | etiotto | @@ -131,7 +131,9 @@ def make_ttgir(mod, metadata, opt, device_arch):
pm.enable_debug()
if os.environ.get("TRITON_INTEL_ENABLE_BLOCK_PTR", ""):
passes.ttir.add_convert_to_ttgpuir_warp(pm, opt.num_warps)
- passes.ttgpuir.add_prefetch_block(pm)
+ # guard prefetch genera... | why <= ? should be greater than. |
intel-xpu-backend-for-triton | github_2023 | others | 977 | intel | etiotto | @@ -177,6 +177,14 @@ jobs:
python3 06-fused-attention.py
python3 07-extern-functions.py
python3 08-grouped-gemm.py
+ # Run block-pointer gemm tutorial
+ TRITON_INTEL_ENABLE_BLOCK_PTR=1 \
+ IGC_VISAOptions=" -TotalGRFNum 256 -enableBCR -nolocalra -printregusage... | I do not think we should add a test in CI that uses these IGC options. This test is to check that the test runs correctly with default options. |
intel-xpu-backend-for-triton | github_2023 | others | 977 | intel | etiotto | @@ -169,6 +169,8 @@ run_tutorial_tests() {
run_tutorial_test "07-extern-functions"
run_tutorial_test "08-grouped-gemm"
run_tutorial_test "09-experimental-block-pointer"
+ export TRITON_INTEL_ENABLE_BLOCK_PTR=1
+ run_tutorial_test "09-experimental-block-pointer"
} | Should undef the env variable at the end. |
intel-xpu-backend-for-triton | github_2023 | python | 977 | intel | etiotto | @@ -108,7 +109,8 @@ def make_ttir(mod, metadata, opt):
pm = ir.pass_manager(mod.context)
pm.enable_debug()
passes.common.add_inliner(pm)
- passes.ttir.add_rewrite_tensor_pointer(pm)
+ if os.environ.get("TRITON_INTEL_ENABLE_BLOCK_PTR", "0") == "0": | Can we make it more readable via something like this:
```
enableBlockPtrSupport = os.environ.get("TRITON_INTEL_ENABLE_BLOCK_PTR", "0") != "0";
if not enableBlockPtrSupport :
passes.ttir.add_rewrite_tensor_pointer(pm)
``` |
intel-xpu-backend-for-triton | github_2023 | python | 977 | intel | etiotto | @@ -123,6 +125,18 @@ def make_ttgir(mod, metadata, opt, device_arch):
# TTIR -> TTGIR
pm = ir.pass_manager(mod.context)
pm.enable_debug()
+ if os.environ.get("TRITON_INTEL_ENABLE_BLOCK_PTR", "0") == "1": | see comment at line 112 |
intel-xpu-backend-for-triton | github_2023 | python | 977 | intel | etiotto | @@ -123,6 +125,18 @@ def make_ttgir(mod, metadata, opt, device_arch):
# TTIR -> TTGIR
pm = ir.pass_manager(mod.context)
pm.enable_debug()
+ if os.environ.get("TRITON_INTEL_ENABLE_BLOCK_PTR", "0") == "1":
+ intel.passes.ttir.add_convert_to_ttgpuir_warp(pm, opt.num_warps)
+ ... | typo: available |
intel-xpu-backend-for-triton | github_2023 | python | 977 | intel | etiotto | @@ -123,6 +125,18 @@ def make_ttgir(mod, metadata, opt, device_arch):
# TTIR -> TTGIR
pm = ir.pass_manager(mod.context)
pm.enable_debug()
+ if os.environ.get("TRITON_INTEL_ENABLE_BLOCK_PTR", "0") == "1":
+ intel.passes.ttir.add_convert_to_ttgpuir_warp(pm, opt.num_warps)
+ ... | Add a FIXME here to use a better way to check whether IGC support prefetch instructions once available. |
intel-xpu-backend-for-triton | github_2023 | python | 977 | intel | etiotto | @@ -151,8 +165,10 @@ def make_llir(src, metadata, options, device_arch):
num_warp_groups = src.get_int_attr("triton_gpu.num-warp-groups-per-cta")
if num_warp_groups is not None:
metadata["num_warps"] *= num_warp_groups
- threads_per_warp = ir.ttgpuir.get_threads_per_warp(src)
- ... | I don't like we have to do this because the threads_per_warp attribute for the module should be left unchanged by any transformations. The user can specify the number of threads_per_warp in the kernel invocation command.
Please open an issue so we can fix it and add a FIXME here. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,016 | intel | etiotto | @@ -151,6 +122,45 @@ struct LocalLoadOpConversion
}
return failure();
}
+
+private:
+ LogicalResult
+ lowerSharedToDistributed(triton::gpu::LocalLoadOp op,
+ triton::gpu::LocalLoadOpAdaptor adaptor,
+ const LLVMTypeConverter *typeConverter,
+ ... | This is a temp. step because the `emitIndices` takes a targetInfo which suggests we should be able to use it to specialize the common function and then drop the intel specific copy of that function ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,011 | intel | whitneywhtsang | @@ -26,9 +26,11 @@
#define DBGS() (llvm::dbgs() << "[" DEBUG_TYPE "]: ")
#define LDBG(X) LLVM_DEBUG(DBGS() << X << "\n")
+using namespace mlir;
+namespace tt = mlir::triton;
+namespace ttg = mlir::triton::gpu;
namespace ttgi = mlir::triton::gpu::intel;
-namespace mlir::triton::gpu { | Can we keep the original change, as it is easier to compare with `lib/Dialect/TritonGPU/Transforms/RemoveLayoutConversions.cpp`?
Can we upstream the suggested changes on `lib/Dialect/TritonGPU/Transforms/RemoveLayoutConversions.cpp` to the OpenAI repo? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,011 | intel | victor-eds | @@ -261,8 +261,13 @@ class TritonIntelGPUAccelerateMatmulPass
}
};
-std::unique_ptr<Pass>
-mlir::triton::gpu::intel::createTritonIntelGPUAccelerateMatmulPass(
- ttgi::DeviceArch arch) {
- return std::make_unique<TritonIntelGPUAccelerateMatmulPass>(arch);
+std::unique_ptr<Pass> mlir::createTritonIntelGPUAccele... | This can also be autogenerated if you replace
```c++
#define GEN_PASS_CLASSES
#include "triton/Dialect/TritonIntelGPU/Transforms/Passes.h.inc"
```
with
```c++
#define GEN_PASS_DEF_PASSNAME
#include "triton/Dialect/TritonIntelGPU/Transforms/Passes.h.inc"
```
In fact, the approach used above (`GEN_PASS_CLASSE... |
intel-xpu-backend-for-triton | github_2023 | others | 1,006 | intel | victor-eds | @@ -159,6 +159,40 @@ def TritonGEN_BarrierOp : TritonGEN_Op<"barrier"> {
let assemblyFormat = "attr-dict";
}
+def TritonGEN_SplitBarrierSignalOp : TritonGEN_Op<"split_barrier_signal">,
+ Arguments<(ins TritonGEN_MemFence:$mem_fence, TritonGEN_MemScope:$mem_scope)> { | I was asked to use `let arguments` and `let results` instead of this syntax in an upstream PR |
intel-xpu-backend-for-triton | github_2023 | others | 1,006 | intel | victor-eds | @@ -159,6 +159,40 @@ def TritonGEN_BarrierOp : TritonGEN_Op<"barrier"> {
let assemblyFormat = "attr-dict";
}
+def TritonGEN_SplitBarrierSignalOp : TritonGEN_Op<"split_barrier_signal">,
+ Arguments<(ins TritonGEN_MemFence:$mem_fence, TritonGEN_MemScope:$mem_scope)> {
+ let summary = "Split barrier signal";
+ st... | Can we avoid using `{` and `}` in format? This can be easily mistaken with `attr-dict`. We can keep this as is and address in a further PR for all ops. |
intel-xpu-backend-for-triton | github_2023 | others | 1,006 | intel | victor-eds | @@ -159,6 +159,40 @@ def TritonGEN_BarrierOp : TritonGEN_Op<"barrier"> {
let assemblyFormat = "attr-dict";
}
+def TritonGEN_SplitBarrierSignalOp : TritonGEN_Op<"split_barrier_signal">,
+ Arguments<(ins TritonGEN_MemFence:$mem_fence, TritonGEN_MemScope:$mem_scope)> {
+ let summary = "Split barrier signal";
+ st... | Really minor, but can we just make this documentation point to `split_barrier_signal`? We're duplicating here. |
intel-xpu-backend-for-triton | github_2023 | others | 1,006 | intel | victor-eds | @@ -159,6 +159,40 @@ def TritonGEN_BarrierOp : TritonGEN_Op<"barrier"> {
let assemblyFormat = "attr-dict";
}
+def TritonGEN_SplitBarrierSignalOp : TritonGEN_Op<"split_barrier_signal">,
+ Arguments<(ins TritonGEN_MemFence:$mem_fence, TritonGEN_MemScope:$mem_scope)> {
+ let summary = "Split barrier signal";
+ st... | Same as above |
intel-xpu-backend-for-triton | github_2023 | others | 1,006 | intel | victor-eds | @@ -159,6 +159,40 @@ def TritonGEN_BarrierOp : TritonGEN_Op<"barrier"> {
let assemblyFormat = "attr-dict";
}
+def TritonGEN_SplitBarrierSignalOp : TritonGEN_Op<"split_barrier_signal">,
+ Arguments<(ins TritonGEN_MemFence:$mem_fence, TritonGEN_MemScope:$mem_scope)> {
+ let summary = "Split barrier signal";
+ st... | Also for future: we took this from other dialect definition, but we should use `let description` instead of `string baseDescription`. We can address in further PR for all ops. |
intel-xpu-backend-for-triton | github_2023 | others | 1,006 | intel | victor-eds | @@ -159,6 +159,40 @@ def TritonGEN_BarrierOp : TritonGEN_Op<"barrier"> {
let assemblyFormat = "attr-dict";
}
+def TritonGEN_SplitBarrierSignalOp : TritonGEN_Op<"split_barrier_signal">,
+ Arguments<(ins TritonGEN_MemFence:$mem_fence, TritonGEN_MemScope:$mem_scope)> {
+ let summary = "Split barrier signal";
+ st... | Can we also document:
- What happens if a thread waits before signal (UB AFAIK)
- What happens if signal and wait arguments differ (AFAIK: `fence` takes intersection of both and `scope` takes narrower, i.e., more restrictive)
- What happens if values of `fence` and `scope` differ between work-items (AFAIK that's not... |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,006 | intel | victor-eds | @@ -629,6 +629,61 @@ struct TritonGENBarrierLowering
}
};
+struct TritonGENSplitBarrier {
+protected:
+ template <typename OpType>
+ void replaceWithCall(OpType op, ConversionPatternRewriter &rewriter) const {
+ static_assert(
+ std::is_same<OpType, TritonGEN::SplitBarrierSignalOp>::value ||
+ ... | ```suggestion
auto funcName = std::is_same<OpType, TritonGEN::SplitBarrierSignalOp>(op)
? "_Z31intel_work_group_barrier_arriveii"
: "_Z29intel_work_group_barrier_waitii";
```
`constexpr` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,006 | intel | victor-eds | @@ -629,6 +629,61 @@ struct TritonGENBarrierLowering
}
};
+struct TritonGENSplitBarrier {
+protected:
+ template <typename OpType>
+ void replaceWithCall(OpType op, ConversionPatternRewriter &rewriter) const {
+ static_assert(
+ std::is_same<OpType, TritonGEN::SplitBarrierSignalOp>::value ||
+ ... | Use `replaceOpWithNewOp` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,006 | intel | victor-eds | @@ -629,6 +629,61 @@ struct TritonGENBarrierLowering
}
};
+struct TritonGENSplitBarrier {
+protected:
+ template <typename OpType>
+ void replaceWithCall(OpType op, ConversionPatternRewriter &rewriter) const {
+ static_assert(
+ std::is_same<OpType, TritonGEN::SplitBarrierSignalOp>::value ||
+ ... | NIT: If we pass function name here as an argument, we can avoid making above a template, thus generating lees code. |
intel-xpu-backend-for-triton | github_2023 | others | 972 | intel | etiotto | @@ -5,6 +5,8 @@ add_triton_library(TritonIntelGPUTransforms
PrefetchBlock.cpp
RemoveLayoutConversions.cpp
RewriteTensorPointer.cpp
+ Pipeliner/MatmulLoopPipeline.cpp | should add in alphabetical order |
intel-xpu-backend-for-triton | github_2023 | others | 972 | intel | etiotto | @@ -246,4 +246,34 @@ def TritonIntelGPUMatchTargetSize : Pass<"tritonintelgpu-match-target-size", "ml
"mlir::triton::gpu::intel::TritonIntelGPUDialect"];
}
+def TritonIntelGPUPipeline : Pass<"tritonintelgpu-pipeline", "mlir::ModuleOp"> {
+ let summary = "Intel GPU pipeline";
+
+ let des... | Description needs some polishing. |
intel-xpu-backend-for-triton | github_2023 | cpp | 972 | intel | etiotto | @@ -19,43 +19,43 @@ void init_triton_intel_passes_ttgpuir(py::module &&m) {
using namespace mlir::triton::gpu;
// Device arch
- py::enum_<mlir::triton::gpu::intel::DeviceArch>(m, "DEVICE_ARCH", | given we have a using declaration at line 19 ... we should make use of it. |
intel-xpu-backend-for-triton | github_2023 | others | 972 | intel | etiotto | @@ -246,4 +246,34 @@ def TritonIntelGPUMatchTargetSize : Pass<"tritonintelgpu-match-target-size", "ml
"mlir::triton::gpu::intel::TritonIntelGPUDialect"];
}
+def TritonIntelGPUPipeline : Pass<"tritonintelgpu-pipeline", "mlir::ModuleOp"> {
+ let summary = "Intel GPU pipeline";
+
+ let des... | The unit test (`loop-pipeline.mlir`) uses 3 stages, should we use the same for the default (3 rather then 2)) ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 972 | intel | etiotto | @@ -37,6 +37,12 @@ std::unique_ptr<Pass> createTritonIntelGPURewriteTensorPointerPass(
std::unique_ptr<Pass> createPrefetchBlockPass();
std::unique_ptr<Pass> createMatchTargetSizePass();
+
+std::unique_ptr<Pass>
+createTritonIntelGPUPipelinePass(int numStages = 2, | test/TritonIntelGPU/loop-pipeline.mlir uses 3 stages (should we init this to 3) ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 972 | intel | etiotto | @@ -0,0 +1,77 @@
+#include "Schedule.h"
+#include "mlir/Dialect/SCF/Transforms/Transforms.h"
+#include "mlir/IR/IRMapping.h"
+#include "mlir/IR/TypeUtilities.h"
+#include "mlir/Transforms/GreedyPatternRewriteDriver.h"
+#include "triton/Dialect/TritonGPU/IR/Dialect.h"
+#include "triton/Dialect/TritonIntelGPU/IR/Dialect.... | There is no pipeline expander in the PR. Need to adjust the comment. |
intel-xpu-backend-for-triton | github_2023 | cpp | 972 | intel | etiotto | @@ -0,0 +1,77 @@
+#include "Schedule.h"
+#include "mlir/Dialect/SCF/Transforms/Transforms.h"
+#include "mlir/IR/IRMapping.h"
+#include "mlir/IR/TypeUtilities.h"
+#include "mlir/Transforms/GreedyPatternRewriteDriver.h"
+#include "triton/Dialect/TritonGPU/IR/Dialect.h"
+#include "triton/Dialect/TritonIntelGPU/IR/Dialect.... | The upstream pass has a `preCondition` static function which also check whether the candidate loop contains nested loops. If it does it is not pipelined. I think we should do the same. |
intel-xpu-backend-for-triton | github_2023 | cpp | 972 | intel | etiotto | @@ -0,0 +1,330 @@
+#include "Schedule.h"
+#include "mlir/Dialect/SCF/Transforms/Transforms.h"
+#include "mlir/Dialect/Tensor/IR/Tensor.h"
+#include "mlir/IR/IRMapping.h"
+#include "mlir/IR/TypeUtilities.h"
+#include "mlir/Interfaces/SideEffectInterfaces.h"
+#include "triton/Analysis/AxisInfo.h"
+#include "triton/Analys... | This function is not easy to understand due to the nesting. Refactor to improve readability. |
intel-xpu-backend-for-triton | github_2023 | cpp | 972 | intel | etiotto | @@ -0,0 +1,330 @@
+#include "Schedule.h"
+#include "mlir/Dialect/SCF/Transforms/Transforms.h"
+#include "mlir/Dialect/Tensor/IR/Tensor.h"
+#include "mlir/IR/IRMapping.h"
+#include "mlir/IR/TypeUtilities.h"
+#include "mlir/Interfaces/SideEffectInterfaces.h"
+#include "triton/Analysis/AxisInfo.h"
+#include "triton/Analys... | ```suggestion
if (ttg::DotOperandEncodingAttr attr =
allTransitiveUsesHaveDotEncoding(loadOp.getResult()))
return LoadDotOperand(loadOp, attr);
return std::nullopt;
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 972 | intel | etiotto | @@ -0,0 +1,330 @@
+#include "Schedule.h"
+#include "mlir/Dialect/SCF/Transforms/Transforms.h"
+#include "mlir/Dialect/Tensor/IR/Tensor.h"
+#include "mlir/IR/IRMapping.h"
+#include "mlir/IR/TypeUtilities.h"
+#include "mlir/Interfaces/SideEffectInterfaces.h"
+#include "triton/Analysis/AxisInfo.h"
+#include "triton/Analys... | Add: ` assert(!newOperands.empty() && "Expecting at least one operand");` |
intel-xpu-backend-for-triton | github_2023 | cpp | 972 | intel | etiotto | @@ -0,0 +1,330 @@
+#include "Schedule.h"
+#include "mlir/Dialect/SCF/Transforms/Transforms.h"
+#include "mlir/Dialect/Tensor/IR/Tensor.h"
+#include "mlir/IR/IRMapping.h"
+#include "mlir/IR/TypeUtilities.h"
+#include "mlir/Interfaces/SideEffectInterfaces.h"
+#include "triton/Analysis/AxisInfo.h"
+#include "triton/Analys... | numStages is not used because numBuffers isn't used. Remove. |
intel-xpu-backend-for-triton | github_2023 | cpp | 972 | intel | etiotto | @@ -0,0 +1,330 @@
+#include "Schedule.h"
+#include "mlir/Dialect/SCF/Transforms/Transforms.h"
+#include "mlir/Dialect/Tensor/IR/Tensor.h"
+#include "mlir/IR/IRMapping.h"
+#include "mlir/IR/TypeUtilities.h"
+#include "mlir/Interfaces/SideEffectInterfaces.h"
+#include "triton/Analysis/AxisInfo.h"
+#include "triton/Analys... | We can avoid populating a vector of this struct datatype as a intermediate step. Refactoring |
intel-xpu-backend-for-triton | github_2023 | cpp | 972 | intel | etiotto | @@ -0,0 +1,330 @@
+#include "Schedule.h"
+#include "mlir/Dialect/SCF/Transforms/Transforms.h"
+#include "mlir/Dialect/Tensor/IR/Tensor.h"
+#include "mlir/IR/IRMapping.h"
+#include "mlir/IR/TypeUtilities.h"
+#include "mlir/Interfaces/SideEffectInterfaces.h"
+#include "triton/Analysis/AxisInfo.h"
+#include "triton/Analys... | This is redundant, both branches return true. Refactoring. |
intel-xpu-backend-for-triton | github_2023 | cpp | 972 | intel | etiotto | @@ -0,0 +1,330 @@
+#include "Schedule.h"
+#include "mlir/Dialect/SCF/Transforms/Transforms.h"
+#include "mlir/Dialect/Tensor/IR/Tensor.h"
+#include "mlir/IR/IRMapping.h"
+#include "mlir/IR/TypeUtilities.h"
+#include "mlir/Interfaces/SideEffectInterfaces.h"
+#include "triton/Analysis/AxisInfo.h"
+#include "triton/Analys... | ```suggestion
if (isa<RankedTensorType>(maskType))
mask = rewriter.create<tt::SplatOp>(loc, maskType, pred);
return currentMask ? rewriter.create<arith::AndIOp>(loc, mask, currentMask)
: mask
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 972 | intel | etiotto | @@ -0,0 +1,330 @@
+#include "Schedule.h"
+#include "mlir/Dialect/SCF/Transforms/Transforms.h"
+#include "mlir/Dialect/Tensor/IR/Tensor.h"
+#include "mlir/IR/IRMapping.h"
+#include "mlir/IR/TypeUtilities.h"
+#include "mlir/Interfaces/SideEffectInterfaces.h"
+#include "triton/Analysis/AxisInfo.h"
+#include "triton/Analys... | Factor this out into a lambda function. |
intel-xpu-backend-for-triton | github_2023 | others | 972 | intel | whitneywhtsang | @@ -101,6 +101,36 @@ def TritonIntelGPUDistributeToWarps
"mlir::gpu::GPUDialect"];
}
+def TritonIntelGPUPipeline : Pass<"tritonintelgpu-pipeline", "mlir::ModuleOp"> {
+ let summary = "Pipeline loops";
+
+ let description = [{
+ Apply software pipelinining to loops containing expensiv... | What kinds of tt.dot is considered as expensive, and what kinds are not? |
intel-xpu-backend-for-triton | github_2023 | others | 972 | intel | whitneywhtsang | @@ -101,6 +101,36 @@ def TritonIntelGPUDistributeToWarps
"mlir::gpu::GPUDialect"];
}
+def TritonIntelGPUPipeline : Pass<"tritonintelgpu-pipeline", "mlir::ModuleOp"> {
+ let summary = "Pipeline loops";
+
+ let description = [{
+ Apply software pipelinining to loops containing expensiv... | From experiments, prefetch distance of 3 is better for GEMM. |
intel-xpu-backend-for-triton | github_2023 | cpp | 972 | intel | etiotto | @@ -0,0 +1,323 @@
+#include "Schedule.h"
+#include "include/triton/Dialect/TritonGPU/Transforms/Utility.h"
+#include "mlir/Dialect/SCF/Transforms/Transforms.h"
+#include "mlir/IR/TypeUtilities.h"
+#include "mlir/Interfaces/SideEffectInterfaces.h"
+#include "triton/Analysis/AxisInfo.h"
+#include "triton/Dialect/Triton/I... | remove |
intel-xpu-backend-for-triton | github_2023 | others | 972 | intel | whitneywhtsang | @@ -0,0 +1,134 @@
+// RUN: triton-opt %s -split-input-file -tritonintelgpu-pipeline="num-stages=3 device-architecture=PVC" | FileCheck %s | ```suggestion
// RUN: triton-opt %s -tritonintelgpu-pipeline="num-stages=3 device-architecture=PVC" | FileCheck %s
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 972 | intel | whitneywhtsang | @@ -0,0 +1,300 @@
+#include "Schedule.h"
+#include "include/triton/Dialect/TritonGPU/Transforms/Utility.h"
+#include "mlir/Dialect/SCF/Transforms/Transforms.h"
+#include "mlir/IR/TypeUtilities.h"
+#include "mlir/Interfaces/SideEffectInterfaces.h"
+#include "triton/Analysis/AxisInfo.h"
+#include "triton/Dialect/Triton/I... | What's `needTrans` for? |
intel-xpu-backend-for-triton | github_2023 | cpp | 998 | intel | ienkovich | @@ -437,7 +436,8 @@ struct ConvertLayoutOpConversion
Value localOffset = linearize(rewriter, loc, localCoord, smemShape);
Value ptr = gep(elemPtrTy, llvmElemTy, smemBase, localOffset);
- outVals.push_back(load_dsmem(ptr, remoteCTAId, llvmElemTy));
+ llvm_unreachable("Unhandled load_dsm... | Does this mean you can completely remove `lowerDistToDistWithDistSmem` from our backend? |
intel-xpu-backend-for-triton | github_2023 | cpp | 998 | intel | etiotto | @@ -437,7 +436,8 @@ struct ConvertLayoutOpConversion
Value localOffset = linearize(rewriter, loc, localCoord, smemShape);
Value ptr = gep(elemPtrTy, llvmElemTy, smemBase, localOffset);
- outVals.push_back(load_dsmem(ptr, remoteCTAId, llvmElemTy));
+ llvm_unreachable("Unhandled load_dsm... | remove |
intel-xpu-backend-for-triton | github_2023 | cpp | 998 | intel | etiotto | @@ -446,8 +446,7 @@ struct ConvertLayoutOpConversion
}
// Cluster barrier | adjust or remove comment |
intel-xpu-backend-for-triton | github_2023 | others | 959 | intel | etiotto | @@ -0,0 +1,45 @@
+// RUN: triton-opt %s -split-input-file --intel-allocate-shared-memory --convert-triton-intel-gpu-to-llvm | FileCheck %s --implicit-check-not=llvm.inline_asm
+
+// CHECK: llvm.func spir_funccc @llvm.genx.GenISA.LSC2DBlockRead.v8i32(i64, i32, i32, i32, i32, i32, i32, i32, i32, i32, i1, i1, i32) -> vect... | Can you simplify the test by:
- remove attribute noinline
- remove `{tt.divisibility = 16 : i32}`
|
intel-xpu-backend-for-triton | github_2023 | others | 959 | intel | etiotto | @@ -0,0 +1,45 @@
+// RUN: triton-opt %s -split-input-file --intel-allocate-shared-memory --convert-triton-intel-gpu-to-llvm | FileCheck %s --implicit-check-not=llvm.inline_asm
+
+// CHECK: llvm.func spir_funccc @llvm.genx.GenISA.LSC2DBlockRead.v8i32(i64, i32, i32, i32, i32, i32, i32, i32, i32, i32, i1, i1, i32) -> vect... | Add more CHECKS to ensure that the lowered loads feed a dpas instruction. |
intel-xpu-backend-for-triton | github_2023 | others | 959 | intel | etiotto | @@ -1,4 +1,7 @@
// RUN: triton-opt %s -tritonintelgpu-rewrite-tensor-pointer | FileCheck %s
+// FIXME
+// XFAIL: * | Why is this failing ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 959 | intel | etiotto | @@ -141,6 +143,170 @@ struct LoadOpConversion
: ConvertTritonGPUOpToLLVMPattern<triton::LoadOp>(converter, benefit),
LoadStoreConversionBase(axisAnalysisPass) {}
+ std::tuple<Value, Value, Value, Value, Value, Value, Value>
+ getValuesFromBlockPointerStruct(Value blockPointer,
+ ... | ```suggestion
auto tensorType = cast<RankedTensorType>(resultType);
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 959 | intel | etiotto | @@ -141,6 +143,170 @@ struct LoadOpConversion
: ConvertTritonGPUOpToLLVMPattern<triton::LoadOp>(converter, benefit),
LoadStoreConversionBase(axisAnalysisPass) {}
+ std::tuple<Value, Value, Value, Value, Value, Value, Value>
+ getValuesFromBlockPointerStruct(Value blockPointer,
+ ... | [nit]: resultTy -> resultType (for consistency, next line uses 'Type' instead of 'Ty') |
intel-xpu-backend-for-triton | github_2023 | cpp | 959 | intel | etiotto | @@ -141,6 +143,170 @@ struct LoadOpConversion
: ConvertTritonGPUOpToLLVMPattern<triton::LoadOp>(converter, benefit),
LoadStoreConversionBase(axisAnalysisPass) {}
+ std::tuple<Value, Value, Value, Value, Value, Value, Value>
+ getValuesFromBlockPointerStruct(Value blockPointer,
+ ... | Please declare and initialize this variable on line 222. Is good practice to initialize the variable right away when possible. |
intel-xpu-backend-for-triton | github_2023 | cpp | 959 | intel | etiotto | @@ -141,6 +143,170 @@ struct LoadOpConversion
: ConvertTritonGPUOpToLLVMPattern<triton::LoadOp>(converter, benefit),
LoadStoreConversionBase(axisAnalysisPass) {}
+ std::tuple<Value, Value, Value, Value, Value, Value, Value>
+ getValuesFromBlockPointerStruct(Value blockPointer,
+ ... | ```suggestion
Value offsetX = (opIdx == 0)
? i32_val(k * elemsPerInstr[1])
: add(mul(outerDimWarpId, i32_val(elemsPerInstr[opIdx])),
i32_val(outer * outerDimWarpNum * elemsPerInstr[opIdx]));
Value offsetY ... |
intel-xpu-backend-for-triton | github_2023 | others | 959 | intel | Dewei-Wang-sh | @@ -0,0 +1,45 @@
+// RUN: triton-opt %s -split-input-file --intel-allocate-shared-memory --convert-triton-intel-gpu-to-llvm | FileCheck %s --implicit-check-not=llvm.inline_asm
+
+// CHECK: llvm.func spir_funccc @llvm.genx.GenISA.LSC2DBlockRead.v8i32(i64, i32, i32, i32, i32, i32, i32, i32, i32, i32, i1, i1, i32) -> vect... | in the other path, we split the tt.load lowering into several stages(distribute-to-warps, match-target-size, convert-to-llvm), each checks its own functionality.
in this case - wrapping all the logic into "loadStoreOpToLLVM“, would be better to have other checks instead of only the final llvm intrinsics.
|
intel-xpu-backend-for-triton | github_2023 | others | 959 | intel | Dewei-Wang-sh | @@ -0,0 +1,45 @@
+// RUN: triton-opt %s -split-input-file --intel-allocate-shared-memory --convert-triton-intel-gpu-to-llvm | FileCheck %s --implicit-check-not=llvm.inline_asm | will it work if we remove the --intel-allocate-shared-memory? |
intel-xpu-backend-for-triton | github_2023 | others | 959 | intel | chengjunlu | @@ -1,4 +1,7 @@
// RUN: triton-opt %s -tritonintelgpu-rewrite-tensor-pointer | FileCheck %s
+// FIXME | I don't think this LIT test changes is required for lowering code change.
This test is only for the Intel rewrite tensor pointer pass.
Please double confirm. |
intel-xpu-backend-for-triton | github_2023 | cpp | 959 | intel | whitneywhtsang | @@ -141,6 +143,164 @@ struct LoadOpConversion
: ConvertTritonGPUOpToLLVMPattern<triton::LoadOp>(converter, benefit),
LoadStoreConversionBase(axisAnalysisPass) {}
+ std::tuple<Value, Value, Value, Value, Value, Value, Value>
+ getValuesFromBlockPointerStruct(Value blockPointer,
+ ... | ```suggestion
int64_t numRepK = numReps[opIdx == 0];
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 959 | intel | whitneywhtsang | @@ -141,6 +143,164 @@ struct LoadOpConversion
: ConvertTritonGPUOpToLLVMPattern<triton::LoadOp>(converter, benefit),
LoadStoreConversionBase(axisAnalysisPass) {}
+ std::tuple<Value, Value, Value, Value, Value, Value, Value>
+ getValuesFromBlockPointerStruct(Value blockPointer,
+ ... | ```suggestion
opIdx == 0 || eltTy.getIntOrFloatBitWidth() == 32 ? /*A vnni=false*/ 0
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 959 | intel | whitneywhtsang | @@ -154,9 +314,10 @@ struct LoadOpConversion
Value other = op.getOther();
// adaptor values
- assert(!isTensorPointerType(ptr.getType()) &&
- "Cannot convert load with a tensor pointer into LLVM; "
- "this case should be transformed to normal load before lowering");
+ if (isTensorP... | ```suggestion
if (isTensorPointerType(ptr.getType()))
return rewriteTensorPointerLoad(op, adaptor, rewriter);
``` |
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