repo_name stringlengths 1 62 | dataset stringclasses 1
value | lang stringclasses 11
values | pr_id int64 1 20.1k | owner stringlengths 2 34 | reviewer stringlengths 2 39 | diff_hunk stringlengths 15 262k | code_review_comment stringlengths 1 99.6k |
|---|---|---|---|---|---|---|---|
intel-xpu-backend-for-triton | github_2023 | others | 1,148 | intel | etiotto | @@ -1,4 +1,4 @@
-// RUN: triton-opt %s -split-input-file -tritonintelgpu-pipeline="num-stages=3 device-architecture=PVC" | FileCheck %s
+// RUN: triton-opt %s -split-input-file -tritonintelgpu-pipeline="num-stages=3" | FileCheck %s | I think is best to not rely on the default target architecture in lit tests and add the `triton_gpu.target` attribute to the module |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,148 | intel | etiotto | @@ -260,4 +261,18 @@ LLVM::CallOp createSPIRVBuiltinCall(Location loc,
return call;
}
+DeviceArch getDeviceArch(Operation *module) {
+ assert(module->hasAttr(triton::AttrTargetName)); | add msg to assert `(assert(cond && "msg")` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,148 | intel | etiotto | @@ -260,4 +261,18 @@ LLVM::CallOp createSPIRVBuiltinCall(Location loc,
return call;
}
+DeviceArch getDeviceArch(Operation *module) {
+ assert(module->hasAttr(triton::AttrTargetName));
+ StringAttr archAttr =
+ cast<StringAttr>(module->getAttr(triton::AttrTargetName));
+
+ if (archAttr == "xpu:DEVICE_ARCH.... | I would use a switch statement here |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,148 | intel | sommerlukas | @@ -118,12 +116,13 @@ class BlockedToDPAS : public mlir::RewritePattern {
isa<DpasEncodingAttr>(oldRetType.getEncoding()))
return failure();
+ ModuleOp mod = op->getParentOfType<mlir::ModuleOp>(); | How expensive is getting the parent module here?
I wonder whether we should keep the device archicture parameter on the pattern and retrieve the target architecture from the module before `patterns.add<::BlockedToDPAS>(context, deviceArch);`. This way, we only have to retrieve the parent module and information once,... |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,148 | intel | chengjunlu | @@ -260,4 +261,16 @@ LLVM::CallOp createSPIRVBuiltinCall(Location loc,
return call;
}
+DeviceArch getDeviceArch(Operation *module) {
+ assert(module->hasAttr(triton::AttrTargetName) && | For the backward combability, return UNKNOWN device arch if there is no triton::AttrTargetName attribute. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,148 | intel | whitneywhtsang | @@ -260,4 +261,16 @@ LLVM::CallOp createSPIRVBuiltinCall(Location loc,
return call;
}
+DeviceArch getDeviceArch(Operation *module) {
+ assert(module->hasAttr(triton::AttrTargetName) &&
+ "Expected a target attribute on the module operation");
+ StringAttr archAttr =
+ cast<StringAttr>(module->getAt... | `xpu:PVC` is used in some existing lit tests, can we make them consistent.
Do you think `xpu:DEVICE_ARCH.PVC` or `xpu:PVC` is better? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,168 | intel | Dewei-Wang-sh | @@ -1045,7 +1045,10 @@ LogicalResult DotOperandEncodingAttr::verify(
}
if (auto parentAttr = mlir::dyn_cast<intel::WarpEncodingAttr>(parent)) {
- // FIXME: verify for the expected kWidth values.
+ if (kWidth != 0)
+ return emitError()
+ << "triton_gpu.dot_op kWidth parameter is not suppor... | actually I used this bit for attn, not 0.
we can just leave this as is, any necessity to add this verfiy? |
intel-xpu-backend-for-triton | github_2023 | others | 1,150 | intel | sommerlukas | @@ -26,19 +26,19 @@ def TritonGEN_Dialect : Dialect {
/// Get the name of the attribute used to annotate max work group size
/// required for kernels.
static constexpr ::llvm::StringLiteral getMaxWorkGroupSizeAttrName() {
- return ::llvm::StringLiteral("gen.max_work_group_size");
+ return ::llv... | I wonder whether it would be cleaner to create a proper TritonGEN dialect attribute for these (e.g., [here](https://github.com/intel/intel-xpu-backend-for-triton/blob/llvm-target/third_party/intel/include/Dialect/TritonGEN/IR/TritonGENAttrDefs.td)), instead of just an attribute with a fixed name. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,150 | intel | sommerlukas | @@ -0,0 +1,83 @@
+//===-TritonGENToLLVMIRTranslation.cpp - TritonGEN Dialect to LLVM IR -----===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---... | IIUC, it is never checked whether the `NamedAttribute`'s name actually matches one of the pre-defined names that we want to handle here.
Is `amendOperation` only called with named attributes with the `triton_gen` prefix or would it be called with any named attribute?
Even if it's only called with attributes with... |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,137 | intel | Dewei-Wang-sh | @@ -265,9 +265,18 @@ createGenISA2DBlockRead(TritonGEN::Matrix2DBlockLoadOp op,
auto moduleOp = rewriter.getBlock()->getParent()->getParentOfType<ModuleOp>();
Value ptr = op.getPtr();
- Value baseWidth = op.getBaseWidth();
- Value baseHeight = op.getBaseHeight();
- Value basePitch = op.getBasePitch();
+ Val... | we should extract this as a function and reused |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,137 | intel | whitneywhtsang | @@ -257,17 +266,27 @@ createGenISA2DBlockRead(TritonGEN::Matrix2DBlockLoadOp op,
op.getY(), i32_val(1));
SmallVector<Type> argTypes{ptr_ty(context, 1), i32_ty, i32_ty, i32_ty,
vecType};
- SmallVector<Value> args{op.getPtr(), op.getBaseWidth(), op.getBaseHeight(),
- ... | Why do we need to modify OCL 2D block load arguments, but not 2D block prefetch? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,131 | intel | chengjunlu | @@ -294,7 +294,9 @@ struct LoadOpConversion
getIntAttr(i1_ty,
(isOperandA || eltTy.getIntOrFloatBitWidth() == 32)
? /*A vnni=false*/ 0
- : /*B vnni=true*/ 1));
+ : /*B vnni=true*/ 1),
+ Triton... | Can we create a simple builder that use the `DEFAULT` cache control attribute to build the Gen Op. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,131 | intel | etiotto | @@ -280,21 +280,15 @@ struct LoadOpConversion
i32_val(1)),
/*x*/ trunc(i32_ty, offsetX),
/*y*/ trunc(i32_ty, offsetY),
- /*elem_size_in_bits*/
- getIntAttr(i32_ty, eltTy.getIntOrFloatBitWidth()),
- /*tile_width*/
- getIntAttr(i32_ty,... | Just pass: ` !isOperandA && eltTy.getIntOrFloatBitWidth() != 32` |
intel-xpu-backend-for-triton | github_2023 | others | 739 | intel | etiotto | @@ -89,10 +89,10 @@ def TTIG_ExtractOp : TTIG_Op<"extract", [Pure]> {
- taking the 3rd subtensor (as indicated by the index) counting in
column-major order
}];
- let arguments = (ins TT_TensorOrTensorPtr:$operand, I32Attr:$index);
+ let arguments = (ins TT_TensorOrTensorPtr:$base, I32Attr:$index); | ok change it |
intel-xpu-backend-for-triton | github_2023 | cpp | 739 | intel | etiotto | @@ -911,7 +911,7 @@ MakeTensorPtrOp getMakeTensorPtrOp(Value v) {
if (auto forOp = dyn_cast<scf::ForOp>(argOwner))
return getMakeTensorPtrOp(
forOp.getOperand(argNum + forOp.getNumControlOperands() - 1));
- if (auto funcOp = dyn_cast<FuncOp>(argOwner)) {
+ if (auto funcOp = dyn_cast<FunctionOpInterfa... | Does this match what is upstream ? If not I would leave it as is to make merging easier. |
intel-xpu-backend-for-triton | github_2023 | cpp | 739 | intel | etiotto | @@ -17,12 +18,29 @@ TritonGPUToLLVMTypeConverter::TritonGPUToLLVMTypeConverter(
MLIRContext *ctx, LowerToLLVMOptions &option,
const DataLayoutAnalysis *analysis)
: LLVMTypeConverter(ctx, option, analysis) {
- addConversion([&](triton::PointerType type) -> std::optional<Type> {
- return convertTritonP... | Changing upstream file is to be avoided because it will make getting our implementation into the OpenAI github repository difficult. Is there a way to avoid it? |
intel-xpu-backend-for-triton | github_2023 | cpp | 739 | intel | etiotto | @@ -201,6 +203,12 @@ struct ConvertTritonGPUToLLVM
void runOnOperation() override {
MLIRContext *context = &getContext();
ModuleOp mod = getOperation();
+ auto enableBlockPtr =
+ mlir::triton::tools::getBoolEnv("INTEL_ENABLE_BLOCK_PTR");
+ // fixme: set subgroupSize 16 for now | Use FIXME (uppercase so we can grep more easily - other files use the uppercase form) |
intel-xpu-backend-for-triton | github_2023 | cpp | 739 | intel | etiotto | @@ -210,10 +218,12 @@ struct ConvertTritonGPUToLLVM
int numCTAs = triton::gpu::TritonGPUDialect::getNumCTAs(mod);
int threadsPerWarp = triton::gpu::TritonGPUDialect::getThreadsPerWarp(mod);
- // Allocate shared memory and set barrier
- ModuleAllocation allocation(mod);
- ModuleMembarAnalysis membar... | We have to consider the case the kernel doesn't use blocked pointers (or doesn't contain a dot operation). IMO the way to do this is to have an analysis that identifies kernels that (a) use `tt.dot` and (b) use blocked pointers and only in that case avoid allocating shared memory ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 739 | intel | etiotto | @@ -201,6 +203,12 @@ struct ConvertTritonGPUToLLVM
void runOnOperation() override {
MLIRContext *context = &getContext();
ModuleOp mod = getOperation();
+ auto enableBlockPtr = | So the conversion pipeline need to be different for kernels that do use blocked pointers and kernels that do not. I think we can wrap the logic in a `ConversionPipeline` class responsible for creating the actual pipeline. That class can have a member function that analyzes the kernel to determine whether it uses bloc... |
intel-xpu-backend-for-triton | github_2023 | cpp | 739 | intel | etiotto | @@ -147,7 +147,7 @@ LogicalResult GlueOp::verify() {
LogicalResult ExtractOp::verify() {
Type resultType = getRes().getType();
- Type operandType = getOperand().getType();
+ Type operandType = getBase().getType(); | Done in separate PR (https://github.com/intel/intel-xpu-backend-for-triton/pull/918) |
intel-xpu-backend-for-triton | github_2023 | cpp | 739 | intel | etiotto | @@ -17,6 +17,7 @@
#include "intel/include/GPUToTritonGEN/GPUToTritonGENPass.h"
#include "intel/include/TritonGENToLLVM/TritonGENToLLVMPass.h"
+#include "intel/include/TritonIntelGPUToLLVM/Passes.h" | I am going to introduce a pipeline manager class to factor out the pipeline customizations in that class. The PR is https://github.com/intel/intel-xpu-backend-for-triton/pull/939 |
intel-xpu-backend-for-triton | github_2023 | cpp | 739 | intel | etiotto | @@ -44,6 +44,7 @@ inline const std::set<std::string> ENV_VARS = {
"TRITON_ENABLE_LLVM_DEBUG",
"USE_TTGIR_LOC",
"TRITON_INTEL_EMULATE_FP16_ATOMICS",
+ "INTEL_ENABLE_BLOCK_PTR", | Added this in PR https://github.com/intel/intel-xpu-backend-for-triton/pull/939 |
intel-xpu-backend-for-triton | github_2023 | others | 739 | intel | etiotto | @@ -1,26 +1,28 @@
add_triton_library(TritonIntelGPUToLLVM | Note: reorder in alphabetical order and added TypeConverter.cpp |
intel-xpu-backend-for-triton | github_2023 | others | 739 | intel | whitneywhtsang | @@ -0,0 +1,94 @@
+// RUN: TRITON_INTEL_ENABLE_BLOCK_PTR=1 triton-opt %s -split-input-file --convert-triton-intel-gpu-to-llvm | FileCheck %s | Don't need `-split-input-file` as there is nothing to split. |
intel-xpu-backend-for-triton | github_2023 | cpp | 739 | intel | whitneywhtsang | @@ -0,0 +1,404 @@
+#include "PatternTritonGPUOpToLLVM.h"
+#include "triton/Analysis/Utility.h"
+
+#include "triton/Dialect/Triton/IR/Dialect.h"
+#include "triton/Dialect/TritonGEN/IR/TritonGENDialect.h"
+
+using namespace mlir;
+using namespace mlir::triton;
+using namespace mlir::triton::gpu::intel;
+
+namespace {
+
+... | ```suggestion
Value idx0 = i32_val(0);
Value idx1 = i32_val(1);
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 739 | intel | whitneywhtsang | @@ -0,0 +1,404 @@
+#include "PatternTritonGPUOpToLLVM.h"
+#include "triton/Analysis/Utility.h"
+
+#include "triton/Dialect/Triton/IR/Dialect.h"
+#include "triton/Dialect/TritonGEN/IR/TritonGENDialect.h"
+
+using namespace mlir;
+using namespace mlir::triton;
+using namespace mlir::triton::gpu::intel;
+
+namespace {
+
+... | ```suggestion
Value idx0 = i32_val(0);
Value idx1 = i32_val(1);
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 739 | intel | whitneywhtsang | @@ -0,0 +1,404 @@
+#include "PatternTritonGPUOpToLLVM.h"
+#include "triton/Analysis/Utility.h"
+
+#include "triton/Dialect/Triton/IR/Dialect.h"
+#include "triton/Dialect/TritonGEN/IR/TritonGENDialect.h"
+
+using namespace mlir;
+using namespace mlir::triton;
+using namespace mlir::triton::gpu::intel;
+
+namespace {
+
+... | ```suggestion
Value bytes = i32_val(tensorType.getElementType().getIntOrFloatBitWidth() / 8);
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 739 | intel | whitneywhtsang | @@ -0,0 +1,404 @@
+#include "PatternTritonGPUOpToLLVM.h"
+#include "triton/Analysis/Utility.h"
+
+#include "triton/Dialect/Triton/IR/Dialect.h"
+#include "triton/Dialect/TritonGEN/IR/TritonGENDialect.h"
+
+using namespace mlir;
+using namespace mlir::triton;
+using namespace mlir::triton::gpu::intel;
+
+namespace {
+
+... | ```suggestion
Value one = i32_val(1);
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 739 | intel | whitneywhtsang | @@ -0,0 +1,404 @@
+#include "PatternTritonGPUOpToLLVM.h"
+#include "triton/Analysis/Utility.h"
+
+#include "triton/Dialect/Triton/IR/Dialect.h"
+#include "triton/Dialect/TritonGEN/IR/TritonGENDialect.h"
+
+using namespace mlir;
+using namespace mlir::triton;
+using namespace mlir::triton::gpu::intel;
+
+namespace {
+
+... | ```suggestion
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 739 | intel | whitneywhtsang | @@ -0,0 +1,404 @@
+#include "PatternTritonGPUOpToLLVM.h"
+#include "triton/Analysis/Utility.h"
+
+#include "triton/Dialect/Triton/IR/Dialect.h"
+#include "triton/Dialect/TritonGEN/IR/TritonGENDialect.h"
+
+using namespace mlir;
+using namespace mlir::triton;
+using namespace mlir::triton::gpu::intel;
+
+namespace {
+
+... | ```suggestion
return vec_ty(elemType, num);
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 739 | intel | whitneywhtsang | @@ -0,0 +1,404 @@
+#include "PatternTritonGPUOpToLLVM.h"
+#include "triton/Analysis/Utility.h"
+
+#include "triton/Dialect/Triton/IR/Dialect.h"
+#include "triton/Dialect/TritonGEN/IR/TritonGENDialect.h"
+
+using namespace mlir;
+using namespace mlir::triton;
+using namespace mlir::triton::gpu::intel;
+
+namespace {
+
+... | ```suggestion
VectorType v2i32 = vec_ty(i32Type, 2);
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 739 | intel | whitneywhtsang | @@ -0,0 +1,404 @@
+#include "PatternTritonGPUOpToLLVM.h"
+#include "triton/Analysis/Utility.h"
+
+#include "triton/Dialect/Triton/IR/Dialect.h"
+#include "triton/Dialect/TritonGEN/IR/TritonGENDialect.h"
+
+using namespace mlir;
+using namespace mlir::triton;
+using namespace mlir::triton::gpu::intel;
+
+namespace {
+
+... | ```suggestion
Value payLoad = undef(v2i32);
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 739 | intel | whitneywhtsang | @@ -0,0 +1,404 @@
+#include "PatternTritonGPUOpToLLVM.h"
+#include "triton/Analysis/Utility.h"
+
+#include "triton/Dialect/Triton/IR/Dialect.h"
+#include "triton/Dialect/TritonGEN/IR/TritonGENDialect.h"
+
+using namespace mlir;
+using namespace mlir::triton;
+using namespace mlir::triton::gpu::intel;
+
+namespace {
+
+... | ```suggestion
insert_element(payLoad, offsetX, idx0);
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 739 | intel | whitneywhtsang | @@ -0,0 +1,404 @@
+#include "PatternTritonGPUOpToLLVM.h"
+#include "triton/Analysis/Utility.h"
+
+#include "triton/Dialect/Triton/IR/Dialect.h"
+#include "triton/Dialect/TritonGEN/IR/TritonGENDialect.h"
+
+using namespace mlir;
+using namespace mlir::triton;
+using namespace mlir::triton::gpu::intel;
+
+namespace {
+
+... | ```suggestion
insert_element(payLoad, offsetY, idx1);
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 739 | intel | whitneywhtsang | @@ -0,0 +1,404 @@
+#include "PatternTritonGPUOpToLLVM.h"
+#include "triton/Analysis/Utility.h"
+
+#include "triton/Dialect/Triton/IR/Dialect.h"
+#include "triton/Dialect/TritonGEN/IR/TritonGENDialect.h"
+
+using namespace mlir;
+using namespace mlir::triton;
+using namespace mlir::triton::gpu::intel;
+
+namespace {
+
+... | ```suggestion
Value idx = i32_val(!i);
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 739 | intel | whitneywhtsang | @@ -0,0 +1,404 @@
+#include "PatternTritonGPUOpToLLVM.h"
+#include "triton/Analysis/Utility.h"
+
+#include "triton/Dialect/Triton/IR/Dialect.h"
+#include "triton/Dialect/TritonGEN/IR/TritonGENDialect.h"
+
+using namespace mlir;
+using namespace mlir::triton;
+using namespace mlir::triton::gpu::intel;
+
+namespace {
+
+... | ```suggestion
Value oldOffset = extract_element(ptr, idx);
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 739 | intel | whitneywhtsang | @@ -0,0 +1,404 @@
+#include "PatternTritonGPUOpToLLVM.h"
+#include "triton/Analysis/Utility.h"
+
+#include "triton/Dialect/Triton/IR/Dialect.h"
+#include "triton/Dialect/TritonGEN/IR/TritonGENDialect.h"
+
+using namespace mlir;
+using namespace mlir::triton;
+using namespace mlir::triton::gpu::intel;
+
+namespace {
+
+... | ```suggestion
add(i32Type, oldOffset, offset);
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 739 | intel | whitneywhtsang | @@ -0,0 +1,404 @@
+#include "PatternTritonGPUOpToLLVM.h"
+#include "triton/Analysis/Utility.h"
+
+#include "triton/Dialect/Triton/IR/Dialect.h"
+#include "triton/Dialect/TritonGEN/IR/TritonGENDialect.h"
+
+using namespace mlir;
+using namespace mlir::triton;
+using namespace mlir::triton::gpu::intel;
+
+namespace {
+
+... | ```suggestion
for (size_t i = 0; i < offsets.size(); ++i) {
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 739 | intel | whitneywhtsang | @@ -0,0 +1,404 @@
+#include "PatternTritonGPUOpToLLVM.h"
+#include "triton/Analysis/Utility.h"
+
+#include "triton/Dialect/Triton/IR/Dialect.h"
+#include "triton/Dialect/TritonGEN/IR/TritonGENDialect.h"
+
+using namespace mlir;
+using namespace mlir::triton;
+using namespace mlir::triton::gpu::intel;
+
+namespace {
+
+... | ```suggestion
ptr = insert_element(ptr, newOffset, idx);
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 739 | intel | whitneywhtsang | @@ -0,0 +1,366 @@
+#include "PatternTritonGPUOpToLLVM.h"
+#include "triton/Analysis/Utility.h"
+
+#include "triton/Dialect/Triton/IR/Dialect.h"
+#include "triton/Dialect/TritonGEN/IR/TritonGENDialect.h"
+
+using namespace mlir;
+using namespace mlir::triton;
+using namespace mlir::triton::gpu::intel;
+
+namespace {
+
+... | ```suggestion
vnni = idxAttr.getInt() == 1;
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 739 | intel | whitneywhtsang | @@ -0,0 +1,366 @@
+#include "PatternTritonGPUOpToLLVM.h"
+#include "triton/Analysis/Utility.h"
+
+#include "triton/Dialect/Triton/IR/Dialect.h"
+#include "triton/Dialect/TritonGEN/IR/TritonGENDialect.h"
+
+using namespace mlir;
+using namespace mlir::triton;
+using namespace mlir::triton::gpu::intel;
+
+namespace {
+
+... | Why it cannot be lowered by:
```
LogicalResult
ConstantOpLowering::matchAndRewrite(arith::ConstantOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter) const {
return LLVM::detail::oneToOneRewrite(op, LLVM::ConstantOp::getOperationName(),
... |
intel-xpu-backend-for-triton | github_2023 | others | 739 | intel | whitneywhtsang | @@ -0,0 +1,94 @@
+// RUN: TRITON_INTEL_ENABLE_BLOCK_PTR=1 triton-opt %s --convert-triton-intel-gpu-to-llvm | FileCheck %s
+
+module attributes {"triton_gpu.compute-capability" = 90 : i32, "triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 32 : i32, triton_gpu.shared = 0 : i32, "triton_gpu.threads-per-warp" = 1 :... | can we check the argument of the prefetch operation? |
intel-xpu-backend-for-triton | github_2023 | cpp | 739 | intel | whitneywhtsang | @@ -0,0 +1,324 @@
+#include "PatternTritonGPUOpToLLVM.h"
+#include "triton/Analysis/Utility.h"
+
+#include "triton/Dialect/Triton/IR/Dialect.h"
+#include "triton/Dialect/TritonGEN/IR/TritonGENDialect.h"
+
+using namespace mlir;
+using namespace mlir::triton;
+using namespace mlir::triton::gpu::intel;
+
+namespace {
+
+... | llvm_unreachable? |
intel-xpu-backend-for-triton | github_2023 | cpp | 739 | intel | etiotto | @@ -307,38 +307,6 @@ class ExtractOpConversion : public ConvertTritonGPUOpToLLVMPattern<ExtractOp> {
}
};
-// FIXME: support it in upstream constantOpLowering
-class ArithConstantOpLowering | We decided during code review to remove it: https://github.com/intel/intel-xpu-backend-for-triton/pull/739#discussion_r1578681887
How is it needed ? Can you post a PR with a test to exercise the pattern ? |
intel-xpu-backend-for-triton | github_2023 | python | 1,136 | intel | ESI-SYD | @@ -16,6 +16,8 @@
import xetla_benchmark
import xetla_benchmark.xetla_kernel as xetla_kernel
+becnmark_suit = xetla_benchmark # triton.testing | `becnmark_suit` -> `benchmark_suit` |
intel-xpu-backend-for-triton | github_2023 | python | 1,136 | intel | etiotto | @@ -130,16 +113,23 @@ def benchmark(M, N, provider):
x = torch.randn(M, N, device='xpu', dtype=torch.bfloat16)
quantiles = [0.5, 0.2, 0.8]
if provider == 'torch-native':
- ms, min_ms, max_ms = triton.testing.do_bench(lambda: torch.softmax(x, axis=-1), quantiles=quantiles, warmup=10,
+ ms, m... | @chengjunlu why can't we use the same `do_bench` as Triton uses to compute the benchmark timing ?
What is the difference between `triton.testing.do_bench` and `benchmark_suit.do_bench`. Note that the former now uses event profiling `torch.xpu.Event` now. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,136 | intel | etiotto | @@ -92,7 +92,8 @@ sycl::event softmax_forward(void *input, void *output, sycl::queue &queue) {
// sycl::info::event_profiling::command_start>()) /
// (1000.0f * 1000.0f * 1000.f);
- // printf("M: %d, Data_type_in: %d, Bandwidth: GB/S: %f \n", mat_m,
+ // printf("M: %d,... | @chengjunlu why do we keep commented out lines? |
intel-xpu-backend-for-triton | github_2023 | python | 1,147 | intel | etiotto | @@ -170,11 +170,15 @@ def is_xpu():
return triton.runtime.driver.active.get_current_target().backend == "xpu"
+def get_xpu_autotune_config(): | Hmmm... so the idea is to use a different set of ` triton.Config` here ? Why the configurations used by NVidia aren't good ? |
intel-xpu-backend-for-triton | github_2023 | python | 1,146 | intel | whitneywhtsang | @@ -501,7 +502,7 @@ def backward(ctx, do):
o, do, #
delta, #
BATCH, N_HEAD, N_CTX, #
- BLOCK_M=PRE_BLOCK, HEAD_DIM=ctx.HEAD_DIM #
+ BLOCK_M=PRE_BLOCK, HEAD_DIM=ctx.HEAD_DIM, # | ```suggestion
BLOCK_M=PRE_BLOCK, HEAD_DIM=ctx.HEAD_DIM #
``` |
intel-xpu-backend-for-triton | github_2023 | python | 1,146 | intel | whitneywhtsang | @@ -514,7 +515,8 @@ def backward(ctx, do):
BLK_SLICE_FACTOR=BLK_SLICE_FACTOR, #
HEAD_DIM=ctx.HEAD_DIM, #
num_warps=NUM_WARPS, #
- num_stages=NUM_STAGES #
+ num_stages=NUM_STAGES, #
+ threads_per_warp=16, # | ```suggestion
threads_per_warp=16 #
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,142 | intel | etiotto | @@ -424,6 +424,9 @@ struct LoadOpConversion
other_ = v;
}
}
+ } else { | Nothing wrong with the change but I think this is more readable. Because `_other` will never be undefined, suggest:
```
Value other_ = other ? undef(retTy)
: rewriter.create<LLVM::ConstantOp>(loc, retTy,
... |
intel-xpu-backend-for-triton | github_2023 | c | 900 | intel | etiotto | @@ -0,0 +1,63 @@
+#include <sycl/sycl.hpp> | Please add copyright |
intel-xpu-backend-for-triton | github_2023 | c | 900 | intel | etiotto | @@ -0,0 +1,63 @@
+#include <sycl/sycl.hpp>
+
+#define NPY_NO_DEPRECATED_API NPY_1_7_API_VERSION
+#include <Python.h>
+#include <numpy/arrayobject.h>
+
+static PyObject *parseDeviceArch(PyObject *self, PyObject *args) {
+ uint64_t dev_arch;
+ if (!PyArg_ParseTuple(args, "K", &dev_arch))
+ return NULL;
+
+ sycl::ex... | ```suggestion
if (PyObject *m = PyModule_Create(&ModuleDef)) {
PyModule_AddFunctions(m, ModuleMethods);
return m;
}
return NULL;
``` |
intel-xpu-backend-for-triton | github_2023 | c | 900 | intel | etiotto | @@ -0,0 +1,63 @@
+#include <sycl/sycl.hpp>
+
+#define NPY_NO_DEPRECATED_API NPY_1_7_API_VERSION
+#include <Python.h>
+#include <numpy/arrayobject.h>
+
+static PyObject *parseDeviceArch(PyObject *self, PyObject *args) {
+ uint64_t dev_arch;
+ if (!PyArg_ParseTuple(args, "K", &dev_arch))
+ return NULL;
+
+ sycl::ex... | add newline after function |
intel-xpu-backend-for-triton | github_2023 | c | 900 | intel | alexbaden | @@ -0,0 +1,63 @@
+#include <sycl/sycl.hpp>
+
+#define NPY_NO_DEPRECATED_API NPY_1_7_API_VERSION
+#include <Python.h>
+#include <numpy/arrayobject.h>
+
+static PyObject *parseDeviceArch(PyObject *self, PyObject *args) {
+ uint64_t dev_arch;
+ if (!PyArg_ParseTuple(args, "K", &dev_arch))
+ return NULL;
+
+ sycl::ex... | Can you explain how the logic here works? My expectation would be that the following line (`dev_arch == 0`) would always be false - but if it were true, meaning "UNKNOWN" key did not exist in `device_archs` object, why would we build and return that null object? |
intel-xpu-backend-for-triton | github_2023 | python | 900 | intel | chengjunlu | @@ -70,10 +68,16 @@ def supports_target(target: tuple):
def __init__(self, target: tuple) -> None:
super().__init__(target)
assert isinstance(target[1], dict)
+ dirname = os.path.dirname(os.path.realpath(__file__))
+ mod = compile_module_from_src(Path(os.path.join(dirname, "arch_par... | Please keep the `self.capability` as same as the one of the CUDA.
We can use the hardcode value to make it work correctly with Intel for now. Like: `80`. We are going to deprecate this fields. |
intel-xpu-backend-for-triton | github_2023 | python | 900 | intel | chengjunlu | @@ -131,7 +136,7 @@ def make_ttgir(mod, metadata, opt, capability):
intel.passes.ttnvgpuir.add_plan_cta(pm, cluster_info)
passes.ttgpuir.add_remove_layout_conversions(pm)
passes.ttgpuir.add_optimize_thread_locality(pm)
- intel.passes.ttgpuir.add_accelerate_matmul(pm, intel.passes.ttgpu... | We can add a new parameter to the make_ttgir for Intel device architecture. Keep the `capability` as same as to the CUDA. It is easy for us to remove it later. |
intel-xpu-backend-for-triton | github_2023 | c | 900 | intel | chengjunlu | @@ -118,12 +104,12 @@ static PyObject *getDeviceProperties(PyObject *self, PyObject *args) {
delete[] pMemoryProperties;
- return Py_BuildValue(
- "{s:i, s:i, s:i, s:i, s:i, s:i, s:i, s:O}", "max_shared_mem",
- max_shared_mem, "multiprocessor_count", multiprocessor_count,
- "sm_clock_rate", sm_cl... | Is there any reason to change the `s:O` to `s:N` for the subgroup_sizes?
Keep it as the old one if no impact. |
intel-xpu-backend-for-triton | github_2023 | python | 900 | intel | chengjunlu | @@ -70,10 +68,17 @@ def supports_target(target: tuple):
def __init__(self, target: tuple) -> None:
super().__init__(target)
assert isinstance(target[1], dict)
+ dirname = os.path.dirname(os.path.realpath(__file__))
+ mod = compile_module_from_src(Path(os.path.join(dirname, "arch_par... | Can we simply use the `self.device_arch = self.properteis["device_arch"]`?
And the arch_parser.c always return UNKNOWN device arch if anything goes wrong.
If anything is not expected, we just use the conservative optimization. |
intel-xpu-backend-for-triton | github_2023 | others | 776 | intel | etiotto | @@ -14,35 +14,98 @@ class TTIG_Op<string mnemonic, list<Trait> traits = []> :
Op<TritonIntelGPU_Dialect, mnemonic, traits>;
def TTIG_AllocOp : TTIG_Op<"alloc", [MemoryEffects<[MemAlloc]>]> {
- let summary = "Memory allocation operation";
-
+ let summary = "Memory allocation";
let description = [{
The ... | Fixed. I renamed the operation from `GlueOp` to `ConcatOp` for consistency with MLIR.
I am also adding a verification function for this operator and lit tests for both valid and invalid usage. |
intel-xpu-backend-for-triton | github_2023 | others | 776 | intel | etiotto | @@ -14,35 +14,98 @@ class TTIG_Op<string mnemonic, list<Trait> traits = []> :
Op<TritonIntelGPU_Dialect, mnemonic, traits>;
def TTIG_AllocOp : TTIG_Op<"alloc", [MemoryEffects<[MemAlloc]>]> {
- let summary = "Memory allocation operation";
-
+ let summary = "Memory allocation";
let description = [{
The ... | Changed the way we print the index to conform to MLIR precedent.
|
intel-xpu-backend-for-triton | github_2023 | others | 776 | intel | etiotto | @@ -123,4 +125,55 @@ def TritonIntelGPUPrefetchBlock : Pass<"tritonintelgpu-prefetch-block", "mlir::M
];
}
+def TritonIntelGPUMatchTargetSize : Pass<"tritonintelgpu-match-target-size", "mlir::ModuleOp"> {
+ let summary = "Split tensor operations to match target architecture";
+
+ let description = [{
+ This ... | fixed |
intel-xpu-backend-for-triton | github_2023 | others | 776 | intel | etiotto | @@ -123,4 +125,55 @@ def TritonIntelGPUPrefetchBlock : Pass<"tritonintelgpu-prefetch-block", "mlir::M
];
}
+def TritonIntelGPUMatchTargetSize : Pass<"tritonintelgpu-match-target-size", "mlir::ModuleOp"> {
+ let summary = "Split tensor operations to match target architecture";
+
+ let description = [{
+ This ... | added |
intel-xpu-backend-for-triton | github_2023 | cpp | 776 | intel | etiotto | @@ -0,0 +1,608 @@
+//===----- MatchTargetSize.cpp -------------------------------------- -----===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | rewrote comment |
intel-xpu-backend-for-triton | github_2023 | others | 776 | intel | etiotto | @@ -1,111 +1,114 @@
+//===- TritonIntelGPUOps.td - TritonIntelGPU op defs -------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===... | > the "dim" operand may not be applicative to "match-target-size" for example, glue/concat 8x16xf16, 8x16xf16, this can happen in a row or in a column, both make sense. so, it's not concat along a dim, it's more of glue operands at a block granularity.
Not sure I understand the comment here. Let's assume we have 2 ... |
intel-xpu-backend-for-triton | github_2023 | others | 776 | intel | whitneywhtsang | @@ -123,4 +125,56 @@ def TritonIntelGPUPrefetchBlock : Pass<"tritonintelgpu-prefetch-block", "mlir::M
];
}
+def TritonIntelGPUMatchTargetSize : Pass<"tritonintelgpu-match-target-size", "mlir::ModuleOp"> {
+ let summary = "Split tensor operations to match target architecture";
+
+ let description = [{
+ This ... | ```suggestion
Assuming that the native 'dot' shape supported by the target architecture is <8x16x16> and
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 776 | intel | whitneywhtsang | @@ -0,0 +1,607 @@
+//===----- MatchTargetSize.cpp -------------------------------------- -----===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | This is a general canonicalizing pattern, don't think it needs to be in this transformation. |
intel-xpu-backend-for-triton | github_2023 | cpp | 776 | intel | whitneywhtsang | @@ -0,0 +1,607 @@
+//===----- MatchTargetSize.cpp -------------------------------------- -----===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | canonicalization can be defined on the operation by `let hasCanonicalizer = 1;` or `let hasCanonicalizeMethod = 1;` |
intel-xpu-backend-for-triton | github_2023 | cpp | 776 | intel | whitneywhtsang | @@ -0,0 +1,607 @@
+//===----- MatchTargetSize.cpp -------------------------------------- -----===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | https://llvm.org/docs/CodingStandards.html#prefer-preincrement
```suggestion
++idx;
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 776 | intel | whitneywhtsang | @@ -0,0 +1,607 @@
+//===----- MatchTargetSize.cpp -------------------------------------- -----===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | Can we add an example? |
intel-xpu-backend-for-triton | github_2023 | cpp | 776 | intel | whitneywhtsang | @@ -0,0 +1,607 @@
+//===----- MatchTargetSize.cpp -------------------------------------- -----===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | Why would targetDotShape hasValue in the beginning of initTargetDotShape? |
intel-xpu-backend-for-triton | github_2023 | cpp | 776 | intel | whitneywhtsang | @@ -0,0 +1,607 @@
+//===----- MatchTargetSize.cpp -------------------------------------- -----===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | Please make the FIXME clearer. |
intel-xpu-backend-for-triton | github_2023 | cpp | 776 | intel | etiotto | @@ -149,7 +149,7 @@ LogicalResult GlueOp::verify() {
LogicalResult ExtractOp::verify() {
Type resultType = getRes().getType();
- Type operandType = getBase().getType();
+ Type operandType = getOperand().getType(); | right I changed the .td file as well |
intel-xpu-backend-for-triton | github_2023 | cpp | 776 | intel | etiotto | @@ -0,0 +1,626 @@
+//===----- MatchTargetSize.cpp -------------------------------------- -----===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | This simplification already exists upstream:
```
//===----------------------------------------------------------------------===//
// RemSIOp
//===----------------------------------------------------------------------===//
OpFoldResult arith::RemSIOp::fold(FoldAdaptor adaptor) {
// remsi (x, 1) -> 0.
if (ma... |
intel-xpu-backend-for-triton | github_2023 | cpp | 776 | intel | whitneywhtsang | @@ -0,0 +1,605 @@
+//===- MatchTargetSize.cpp ----------------------------------------------*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | please fix formatted example, and change ttig to triton_intel_gpu. |
intel-xpu-backend-for-triton | github_2023 | cpp | 776 | intel | whitneywhtsang | @@ -0,0 +1,605 @@
+//===- MatchTargetSize.cpp ----------------------------------------------*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | IIUC, if `%extract` is hoisted out of the loop by e.g., LICM, then the folder of extract operation should be able to fold to the same code, right?
Should we rely on pipeline like that instead of simplifying in this pass? |
intel-xpu-backend-for-triton | github_2023 | others | 1,120 | intel | etiotto | @@ -1517,3 +1517,15 @@ module attributes {"triton_gpu.target" = "xpu:PVC", "triton_gpu.num-ctas" = 1 :
tt.return
}
}
+
+// -----
+
+#blocked0 = #triton_gpu.blocked<{sizePerThread = [1], threadsPerWarp = [32], warpsPerCTA = [4], order = [0], CTAsPerCGA = [1], CTASplitNum = [1], CTAOrder = [0]}>
+module attribut... | add newline |
intel-xpu-backend-for-triton | github_2023 | others | 1,119 | intel | whitneywhtsang | @@ -185,8 +185,10 @@ build_ipex() {
if [ "$BUILD_PINNED" = true ]; then
git fetch --all | Given that it is not needed as you specified in the description, I would just remove it.
```suggestion
``` |
intel-xpu-backend-for-triton | github_2023 | others | 1,094 | intel | alexbaden | @@ -113,11 +113,14 @@ if [ "$BUILD_PINNED" = false ]; then
fi
if [ "$BUILD_FROM_SOURCE" = false ]; then
- TEMP_DIR=`mktemp -d`
- cd $TEMP_DIR
- gh run download $(gh run list -w "Triton wheels" -R intel/intel-xpu-backend-for-triton --json databaseId,conclusion | jq -r '[.[] | select(.conclusion=="success")][0].da... | Is there a workaround for older versions of `gh` which don't have `--pattern`? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,074 | intel | victor-eds | @@ -634,6 +634,30 @@ inline void storeDistributedToShared(Value src, ArrayRef<Value> inVals,
}
}
+
+inline LLVM::LLVMFuncOp lookupOrCreateSPIRVFn(Operation *symbolTable, StringRef name,
+ ArrayRef<Type> paramTypes,
+ Type resultType) {
+ ... | I like this code (ofc, I wrote it :stuck_out_tongue_closed_eyes:). Just two comments:
- Can we move the function definitions to `Utility.cpp`?
- Can we make [this](https://github.com/intel/intel-xpu-backend-for-triton/blob/63114efe1d8d91cc6c454c4be98a44e1c726eb62/third_party/intel/lib/GPUToTritonGEN/OpToFuncCallLower... |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,074 | intel | victor-eds | @@ -1284,36 +1284,40 @@ struct FpToFpOpConversion
static Value convertBf16ToFp32(Location loc,
ConversionPatternRewriter &rewriter,
const Value &v) {
- auto as_int16 = bitcast(v, i16_ty);
- auto as_int32 = zext(i32_ty, as_int16);
- auto shi... | ```suggestion
constexpr StringLiteral name = "_Z32intel_convert_bfloat16_as_ushortf";
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,074 | intel | victor-eds | @@ -1284,36 +1284,40 @@ struct FpToFpOpConversion
static Value convertBf16ToFp32(Location loc,
ConversionPatternRewriter &rewriter,
const Value &v) {
- auto as_int16 = bitcast(v, i16_ty);
- auto as_int32 = zext(i32_ty, as_int16);
- auto shi... | ```suggestion
constexpr StringLiteral name = "_Z31intel_convert_as_bfloat16_floatt";
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,074 | intel | victor-eds | @@ -1284,36 +1284,40 @@ struct FpToFpOpConversion
static Value convertBf16ToFp32(Location loc,
ConversionPatternRewriter &rewriter,
const Value &v) {
- auto as_int16 = bitcast(v, i16_ty);
- auto as_int32 = zext(i32_ty, as_int16);
- auto shi... | ```suggestion
Value call = intel::createSPIRVBuiltinCall(loc, rewriter, ext_func, v);
return call;
```
NIT |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,074 | intel | victor-eds | @@ -1284,36 +1284,40 @@ struct FpToFpOpConversion
static Value convertBf16ToFp32(Location loc,
ConversionPatternRewriter &rewriter,
const Value &v) {
- auto as_int16 = bitcast(v, i16_ty);
- auto as_int32 = zext(i32_ty, as_int16);
- auto shi... | ```suggestion
Value call = intel::createSPIRVBuiltinCall(loc, rewriter, trunc_func, v);
return call;
```
NIT |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,074 | intel | whitneywhtsang | @@ -13,6 +13,8 @@
#include "mlir/Dialect/GPU/IR/GPUDialect.h"
#include "mlir/Dialect/LLVMIR/LLVMDialect.h"
#include "mlir/IR/Builders.h"
+#include "mlir/IR/SymbolTable.h"
+#include "third_party/intel/include/Dialect/TritonIntelGPU/Transforms/Utility.h" | ```suggestion
#include "intel/include/Dialect/TritonIntelGPU/Transforms/Utility.h"
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,088 | intel | chengjunlu | @@ -271,7 +271,7 @@ DotOp::inferReturnTypes(MLIRContext *context, std::optional<Location> location,
auto retEnc = accTy.getEncoding();
if (aEnc) {
assert(bEnc);
- Dialect &dialect = retEnc.getDialect();
+ Dialect &dialect = aEnc.getDialect(); | Not to change it back. We should PR this changes to upstream.
Here we want the public code to dispatch the validation check to the external dialect such as TritonIntelDialect.
Only the result layout encoding is defined in the external dialect.
|
intel-xpu-backend-for-triton | github_2023 | python | 1,088 | intel | chengjunlu | @@ -90,23 +90,23 @@ def test_print(func: str, data_type: str):
x = torch.arange(0, N, dtype=torch.int32, device='xpu').to(getattr(torch, data_type))
y = torch.zeros((N, ), dtype=x.dtype, device="xpu")
if func == "device_print":
- kernel_device_print[(1, )](x, y, num_warps=num_warps, BLOCK=N, threa... | Does the tests support different threads_per_warp size now? `get_current_target_warp_size()`? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,088 | intel | chengjunlu | @@ -295,11 +295,7 @@ LogicalResult DotOp::verify() {
// Verify that the encodings are valid.
if (!aEncoding || !bEncoding)
return emitError("mismatching encoding between A and B operands");
-
- // type is the same as the accumulator
- auto accTy = getOperand(2).getType().cast<RankedTensorType>();
- auto r... | The same. We want the code to dispatching the validation to the external dialect. |
intel-xpu-backend-for-triton | github_2023 | others | 1,086 | intel | whitneywhtsang | @@ -132,3 +132,104 @@ module attributes {"triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 4 :
tt.return
}
}
+
+// -----
+
+// COM: Test that loads for a tt.dot operation are prefetched when the loaded value feeds the tt.dor operation directly. | ```suggestion
// COM: Test that loads for a tt.dot operation are prefetched when the loaded value feeds the tt.dot operation directly.
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,086 | intel | whitneywhtsang | @@ -71,10 +74,20 @@ static ttg::DotOperandEncodingAttr getDotEncodingFromUser(Operation *user) {
/// same dot operand encoding, return the encoding. Otherwise return nullptr.
static ttg::DotOperandEncodingAttr allTransitiveUsesHaveDotEncoding(Value val) {
ttg::DotOperandEncodingAttr attr{nullptr};
+ LLVM_DEBUG(ll... | ```suggestion
ttg::DotOperandEncodingAttr dotAttr;
if (isa<triton::DotOp>(user)) {
auto tensorType = cast<RankedTensorType>(val.getType());
dotAttr = dyn_cast<ttg::DotOperandEncodingAttr>(tensorType.getEncoding());
} else {
dotAttr = getDotEncodingFromUser(user);
}
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,061 | intel | whitneywhtsang | @@ -164,13 +164,11 @@ struct CoalescePass : public TritonGPUCoalesceBase<CoalescePass> {
Value ptr = getMemAccessPtr(curr);
if (!ptr)
return;
- // We only convert `tensor<tt.ptr<>>` or `tt.ptr<tensor<>>` load/store
- bool isPtrTensor = false, isTensorPointer = false;
+ // We only c... | Should we upstream this change? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,065 | intel | whitneywhtsang | @@ -310,8 +310,8 @@ Value loadOperand(ConversionPatternRewriter &rewriter, Location loc,
SmallVector<Value> multiDimWarpId =
mlir::LLVM::delinearize(rewriter, loc, warpId, warpsPerCTA, order);
- double ceilRes =
- ceil(static_cast<double>(shapePerCTA[opIdx]) / elemsPerInstr[opIdx]);
+ unsigned ceilRe... | Similar to https://github.com/intel/intel-xpu-backend-for-triton/pull/833. |
intel-xpu-backend-for-triton | github_2023 | others | 877 | intel | pbchekin | @@ -0,0 +1,17 @@
+#!/bin/bash
+set -e
+
+if [ ! -v BASE ]; then
+ echo "**** BASE is not given *****"
+ BASE=$(cd $(dirname "$0")/../../.. && pwd)
+ echo "**** Default BASE is set to $BASE ****"
+fi
+
+XETLA_PROJ=$BASE/ipex-extension-example
+if [ ! -d "$XETLA_PROJ" ]; then
+ cd $BASE
+ git clone https://github.co... | This repository has a submodule in intel-innersource, this will not work without proper credentials. |
intel-xpu-backend-for-triton | github_2023 | cpp | 877 | intel | etiotto | @@ -0,0 +1,94 @@
+#pragma once
+#include <sycl.hpp>
+
+class mat0_96x2048x2048_bf16 {
+public:
+ static constexpr size_t mat_n = 2048;
+ static constexpr size_t mat_m = 2048 * 96;
+ static constexpr size_t wg_n = mat_n;
+ static constexpr size_t wg_m = 4;
+ static constexpr size_t sg_n = 512;
+ static constexpr s... | Please remove commented out code. |
intel-xpu-backend-for-triton | github_2023 | cpp | 877 | intel | etiotto | @@ -0,0 +1,94 @@
+#pragma once | Need to add copyright notice to all new files please. |
intel-xpu-backend-for-triton | github_2023 | python | 877 | intel | etiotto | @@ -0,0 +1,204 @@
+"""
+Fused Softmax
+=============
+
+In this tutorial, you will write a fused softmax operation that is significantly faster
+than PyTorch's native op for a particular class of matrices: those whose rows can fit in
+the GPU's SRAM.
+
+In doing so, you will learn about:
+
+* The benefits of kernel fus... | Update the comment to0 reflect the use of xeTLA |
intel-xpu-backend-for-triton | github_2023 | python | 877 | intel | etiotto | @@ -0,0 +1,204 @@
+"""
+Fused Softmax
+=============
+
+In this tutorial, you will write a fused softmax operation that is significantly faster
+than PyTorch's native op for a particular class of matrices: those whose rows can fit in
+the GPU's SRAM.
+
+In doing so, you will learn about:
+
+* The benefits of kernel fus... | ??? I think you should remove this text because is not really necessary and also the performance may change over time so stating anything about performance in a benchmark is going to be potentially incorrect |
intel-xpu-backend-for-triton | github_2023 | cpp | 877 | intel | etiotto | @@ -0,0 +1,94 @@
+#include "softmax.h"
+#include <ipex.h>
+#include <torch/extension.h>
+#include <vector>
+
+sycl::queue get_current_sycl_queue() {
+ // submit kernel
+ c10::impl::VirtualGuardImpl impl(at::DeviceType::XPU);
+ c10::Stream stream = impl.getStream(impl.getDevice());
+
+ return xpu::get_queue_from_str... | Remove commented out code. |
intel-xpu-backend-for-triton | github_2023 | cpp | 877 | intel | etiotto | @@ -0,0 +1,94 @@
+#include "softmax.h"
+#include <ipex.h>
+#include <torch/extension.h>
+#include <vector>
+
+sycl::queue get_current_sycl_queue() {
+ // submit kernel
+ c10::impl::VirtualGuardImpl impl(at::DeviceType::XPU);
+ c10::Stream stream = impl.getStream(impl.getDevice());
+
+ return xpu::get_queue_from_str... | Remove commented out code |
intel-xpu-backend-for-triton | github_2023 | others | 877 | intel | etiotto | @@ -0,0 +1,12 @@
+ | Remove empty lines |
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