repo_name stringlengths 1 62 | dataset stringclasses 1
value | lang stringclasses 11
values | pr_id int64 1 20.1k | owner stringlengths 2 34 | reviewer stringlengths 2 39 | diff_hunk stringlengths 15 262k | code_review_comment stringlengths 1 99.6k |
|---|---|---|---|---|---|---|---|
intel-xpu-backend-for-triton | github_2023 | cpp | 959 | intel | etiotto | @@ -67,15 +68,7 @@ bool shouldRemove(tt::MakeTensorPtrOp &op, ttgi::DeviceArch deviceArch) {
auto ptrType = cast<tt::PointerType>(op.getType());
auto tensorType = cast<RankedTensorType>(ptrType.getPointeeType());
- // Only keep the tensor pointer with the layout of DpasEncodingAttr
- if (!tensorType.getEncodi... | Using a common utility here and in `LoadStoreOpToLLVM.cpp` to avoid code duplication |
intel-xpu-backend-for-triton | github_2023 | cpp | 959 | intel | whitneywhtsang | @@ -38,8 +40,16 @@ DPASEngineType getDPASType(DotOp op);
// Infers the encoding of the source of op given the result encoding.
std::optional<Attribute> inferSrcEncoding(Operation *op, Attribute encoding);
+// Retuns true is the operation is an expensive load or store operation. | ```suggestion
// Retuns true if the operation is an expensive load or store operation.
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 959 | intel | whitneywhtsang | @@ -141,6 +142,181 @@ struct LoadOpConversion
: ConvertTritonGPUOpToLLVMPattern<triton::LoadOp>(converter, benefit),
LoadStoreConversionBase(axisAnalysisPass) {}
+ /// Holds the values related to a block pointer
+ // It includes the offset base for Y and X, base height and width, row and | ```suggestion
// It includes the offset base for X and Y, base height and width, row and
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 959 | intel | whitneywhtsang | @@ -141,6 +142,181 @@ struct LoadOpConversion
: ConvertTritonGPUOpToLLVMPattern<triton::LoadOp>(converter, benefit),
LoadStoreConversionBase(axisAnalysisPass) {}
+ /// Holds the values related to a block pointer
+ // It includes the offset base for Y and X, base height and width, row and
+ // col... | Can we define `bool isOperandA = (opIdx == 0)` and use that? |
intel-xpu-backend-for-triton | github_2023 | cpp | 959 | intel | whitneywhtsang | @@ -141,6 +142,181 @@ struct LoadOpConversion
: ConvertTritonGPUOpToLLVMPattern<triton::LoadOp>(converter, benefit),
LoadStoreConversionBase(axisAnalysisPass) {}
+ /// Holds the values related to a block pointer
+ // It includes the offset base for Y and X, base height and width, row and
+ // col... | is this a complete sentence? |
intel-xpu-backend-for-triton | github_2023 | cpp | 959 | intel | whitneywhtsang | @@ -141,6 +142,181 @@ struct LoadOpConversion
: ConvertTritonGPUOpToLLVMPattern<triton::LoadOp>(converter, benefit),
LoadStoreConversionBase(axisAnalysisPass) {}
+ /// Holds the values related to a block pointer
+ // It includes the offset base for Y and X, base height and width, row and
+ // col... | can we use Structured Bindings? |
intel-xpu-backend-for-triton | github_2023 | cpp | 959 | intel | whitneywhtsang | @@ -154,9 +330,9 @@ struct LoadOpConversion
Value other = op.getOther();
// adaptor values
- assert(!isTensorPointerType(ptr.getType()) &&
- "Cannot convert load with a tensor pointer into LLVM; "
- "this case should be transformed to normal load before lowering");
+ if (isTensorPo... | can we add back the assert here in case of unexpected tensor pointer which is not handled. |
intel-xpu-backend-for-triton | github_2023 | cpp | 959 | intel | whitneywhtsang | @@ -141,6 +142,181 @@ struct LoadOpConversion
: ConvertTritonGPUOpToLLVMPattern<triton::LoadOp>(converter, benefit),
LoadStoreConversionBase(axisAnalysisPass) {}
+ /// Holds the values related to a block pointer
+ // It includes the offset base for Y and X, base height and width, row and
+ // col... | Do we have issue to track creation of large 2d block load? |
intel-xpu-backend-for-triton | github_2023 | others | 958 | intel | chengjunlu | @@ -1,4 +1,137 @@
-// RUN: triton-opt %s -tritonintelgpu-rewrite-tensor-pointer | FileCheck %s
+// RUN: triton-opt %s -split-input-file -tritonintelgpu-rewrite-tensor-pointer | FileCheck %s
+
+// COM: Case1:
+// COM: Block Pointers satisfy 3 conditions will not be rewrited
+// COM: - has triton_intel_gpu.dpas layout a... | `is contiguous` -> `is row major` which is more precises. |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | chengjunlu | @@ -30,11 +30,14 @@ std::unique_ptr<Pass> createTritonIntelGPUDistributeToWarpsPass();
std::unique_ptr<Pass> createTritonIntelGPURemoveLayoutConversionsPass();
-std::unique_ptr<Pass> createTritonIntelGPURewriteTensorPointerPass();
+std::unique_ptr<Pass> createTritonIntelGPURewriteTensorPointerPass(
+ triton::gp... | Remove blank change. |
intel-xpu-backend-for-triton | github_2023 | others | 958 | intel | etiotto | @@ -151,16 +151,27 @@ def TritonIntelGPURemoveLayoutConversions : Pass<"tritonintelgpu-remove-layout-c
}
def TritonIntelGPURewriteTensorPointer : Pass<"tritonintelgpu-rewrite-tensor-pointer", "mlir::ModuleOp"> {
- let summary = "Rewrite load/stores with tensor pointers into legacy load/stores";
+ let summary = "R... | ```suggestion
let summary = "Rewrite load/store operations using tensor pointers that cannot be lowered to 2D Block Load/Store intrinsics";
``` |
intel-xpu-backend-for-triton | github_2023 | others | 958 | intel | etiotto | @@ -1,4 +1,145 @@
-// RUN: triton-opt %s -tritonintelgpu-rewrite-tensor-pointer | FileCheck %s
+// RUN: triton-opt %s -split-input-file -tritonintelgpu-rewrite-tensor-pointer=device-architecture=PVC | FileCheck %s
+
+// COM: Case1:
+// COM: Block Pointers satisfy 3 conditions will not be rewrited
+// COM: - has triton... | // COM: Check that operations using block pointers satisfying the following conditions are not rewritten:
// COM: - the block pointer has the "dot" layout attribute (with dpas parent layout)
// COM: - the block pointers is advanced in row major order: strides[order[0]] == 1
// COM: - the block pointer pitch is... |
intel-xpu-backend-for-triton | github_2023 | others | 958 | intel | etiotto | @@ -1,4 +1,145 @@
-// RUN: triton-opt %s -tritonintelgpu-rewrite-tensor-pointer | FileCheck %s
+// RUN: triton-opt %s -split-input-file -tritonintelgpu-rewrite-tensor-pointer=device-architecture=PVC | FileCheck %s
+
+// COM: Case1:
+// COM: Block Pointers satisfy 3 conditions will not be rewrited
+// COM: - has triton... | Typo: CHECK-LABEL |
intel-xpu-backend-for-triton | github_2023 | others | 958 | intel | etiotto | @@ -1,4 +1,145 @@
-// RUN: triton-opt %s -tritonintelgpu-rewrite-tensor-pointer | FileCheck %s
+// RUN: triton-opt %s -split-input-file -tritonintelgpu-rewrite-tensor-pointer=device-architecture=PVC | FileCheck %s
+
+// COM: Case1:
+// COM: Block Pointers satisfy 3 conditions will not be rewrited
+// COM: - has triton... | Remove `attributes {noinline = false}` is not necessary (same for the next test). |
intel-xpu-backend-for-triton | github_2023 | others | 958 | intel | etiotto | @@ -1,4 +1,145 @@
-// RUN: triton-opt %s -tritonintelgpu-rewrite-tensor-pointer | FileCheck %s
+// RUN: triton-opt %s -split-input-file -tritonintelgpu-rewrite-tensor-pointer=device-architecture=PVC | FileCheck %s
+
+// COM: Case1:
+// COM: Block Pointers satisfy 3 conditions will not be rewrited
+// COM: - has triton... | instead of `{{.*}}<(opIdx ...` I would use the actual attribute needed: `#triton_gpu.dot_op<op_idx ...` here, on the tt.dot operation and the tt.advance operations as well. |
intel-xpu-backend-for-triton | github_2023 | others | 958 | intel | etiotto | @@ -1,4 +1,145 @@
-// RUN: triton-opt %s -tritonintelgpu-rewrite-tensor-pointer | FileCheck %s
+// RUN: triton-opt %s -split-input-file -tritonintelgpu-rewrite-tensor-pointer=device-architecture=PVC | FileCheck %s
+
+// COM: Case1:
+// COM: Block Pointers satisfy 3 conditions will not be rewrited
+// COM: - has triton... | typo: CHECK_LABEL |
intel-xpu-backend-for-triton | github_2023 | others | 958 | intel | etiotto | @@ -1,4 +1,145 @@
-// RUN: triton-opt %s -tritonintelgpu-rewrite-tensor-pointer | FileCheck %s
+// RUN: triton-opt %s -split-input-file -tritonintelgpu-rewrite-tensor-pointer=device-architecture=PVC | FileCheck %s
+
+// COM: Case1:
+// COM: Block Pointers satisfy 3 conditions will not be rewrited
+// COM: - has triton... | // COM: Check that operations using tensor pointers satisfying the following conditions are rewritten to use a legacy pointer:
// COM: - pointers have no divisibility attribute |
intel-xpu-backend-for-triton | github_2023 | others | 958 | intel | etiotto | @@ -1,4 +1,145 @@
-// RUN: triton-opt %s -tritonintelgpu-rewrite-tensor-pointer | FileCheck %s
+// RUN: triton-opt %s -split-input-file -tritonintelgpu-rewrite-tensor-pointer=device-architecture=PVC | FileCheck %s
+
+// COM: Case1:
+// COM: Block Pointers satisfy 3 conditions will not be rewrited
+// COM: - has triton... | // COM: Check that operations using block pointers without a layout attribute are rewritten to use a legacy pointer. |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | whitneywhtsang | @@ -17,13 +19,153 @@
using namespace mlir;
namespace tt = mlir::triton;
+namespace ttg = mlir::triton::gpu;
namespace ttgi = mlir::triton::gpu::intel;
#define GEN_PASS_CLASSES
#include "triton/Dialect/TritonIntelGPU/Transforms/Passes.h.inc"
namespace {
+bool isDivisible(Value v, unsigned divisor) {
+ if ... | Why v is divisible by divisor when it's first operand is divisible by divisor? |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | whitneywhtsang | @@ -17,13 +19,153 @@
using namespace mlir;
namespace tt = mlir::triton;
+namespace ttg = mlir::triton::gpu;
namespace ttgi = mlir::triton::gpu::intel;
#define GEN_PASS_CLASSES
#include "triton/Dialect/TritonIntelGPU/Transforms/Passes.h.inc"
namespace {
+bool isDivisible(Value v, unsigned divisor) {
+ if ... | this block is never entered, as v is either in entry block or not, and when it is in entry block, it is either a block argument or not, which are all covered in earlier blocks. |
intel-xpu-backend-for-triton | github_2023 | others | 958 | intel | etiotto | @@ -151,16 +151,27 @@ def TritonIntelGPURemoveLayoutConversions : Pass<"tritonintelgpu-remove-layout-c
}
def TritonIntelGPURewriteTensorPointer : Pass<"tritonintelgpu-rewrite-tensor-pointer", "mlir::ModuleOp"> {
- let summary = "Rewrite load/stores with tensor pointers into legacy load/stores";
+ let summary = "R... | ```suggestion
This pass determines whether a load/store operation can be lowered to 2D Block Load/Store intrinsic. If it cannot, it replaces the the load/store operation with a legacy pointer and removes the Triton operations that are used to create and advance the block pointer (that is `tt.make_tensor_tr` and `t... |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | whitneywhtsang | @@ -17,13 +19,153 @@
using namespace mlir;
namespace tt = mlir::triton;
+namespace ttg = mlir::triton::gpu;
namespace ttgi = mlir::triton::gpu::intel;
#define GEN_PASS_CLASSES
#include "triton/Dialect/TritonIntelGPU/Transforms/Passes.h.inc"
namespace {
+bool isDivisible(Value v, unsigned divisor) {
+ if ... | ```suggestion
for (auto &yieldOp : forOp.getOps<scf::YieldOp>()) {
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | whitneywhtsang | @@ -17,13 +19,153 @@
using namespace mlir;
namespace tt = mlir::triton;
+namespace ttg = mlir::triton::gpu;
namespace ttgi = mlir::triton::gpu::intel;
#define GEN_PASS_CLASSES
#include "triton/Dialect/TritonIntelGPU/Transforms/Passes.h.inc"
namespace {
+bool isDivisible(Value v, unsigned divisor) {
+ if ... | ```suggestion
auto yieldArg = yieldOp->getOperand(iterArgIdx);
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | whitneywhtsang | @@ -17,13 +19,153 @@
using namespace mlir;
namespace tt = mlir::triton;
+namespace ttg = mlir::triton::gpu;
namespace ttgi = mlir::triton::gpu::intel;
#define GEN_PASS_CLASSES
#include "triton/Dialect/TritonIntelGPU/Transforms/Passes.h.inc"
namespace {
+bool isDivisible(Value v, unsigned divisor) {
+ if ... | Please add a description of this function. |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | etiotto | @@ -247,15 +449,19 @@ class TritonIntelGPURewriteTensorPointerPass
// Save information
rewritedInfo[op.getResult()] =
RewritedInfo(op.getBase(), op.getShape(), op.getStrides(), i64Offsets,
- tensorType.getShape());
+ tensorType.getShape(), tensorType.getEncodin... | [nit]: Remove unnecessary braces { } |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | etiotto | @@ -281,8 +487,11 @@ class TritonIntelGPURewriteTensorPointerPass
}
Operation *rewriteLoadStoreOp(OpBuilder &builder, Operation *op,
- std::stack<Operation *> &eraser) {
+ std::stack<Operation *> &eraser,
+ const DenseS... | Add message to assert, like: assert(cond && ""); |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | whitneywhtsang | @@ -17,13 +18,148 @@
using namespace mlir;
namespace tt = mlir::triton;
+namespace ttg = mlir::triton::gpu;
namespace ttgi = mlir::triton::gpu::intel;
#define GEN_PASS_CLASSES
#include "triton/Dialect/TritonIntelGPU/Transforms/Passes.h.inc"
namespace {
+bool isDivisible(Value v, unsigned divisor) {
+ if ... | Why is this always the case? |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | whitneywhtsang | @@ -560,11 +830,12 @@ class TritonIntelGPURewriteTensorPointerPass
// `tt.make_tensor_ptr`, `tt.advance`, `tt.load`, `tt.store`,
// `scf.for` (tensor pointer usages may be in a loop fashion)
std::stack<Operation *> eraser;
- visitOperation(getOperation(), eraser);
+ visitOperation(getOperation(), e... | Do you think having `valueToRemove` as private member field is cleaner than passing through functions? |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | chengjunlu | @@ -17,13 +18,147 @@
using namespace mlir;
namespace tt = mlir::triton;
+namespace ttg = mlir::triton::gpu;
namespace ttgi = mlir::triton::gpu::intel;
#define GEN_PASS_CLASSES
#include "triton/Dialect/TritonIntelGPU/Transforms/Passes.h.inc"
namespace {
+bool isDivisible(Value v, unsigned divisor) {
+ if ... | Remove the `llvm::report_fatal_error`.
For any cases we couldn't make sure it is suitable for the 2D load HW, we just fallback it to the legacy pointer athematic computation. |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | chengjunlu | @@ -17,22 +18,86 @@
using namespace mlir;
namespace tt = mlir::triton;
+namespace ttg = mlir::triton::gpu;
namespace ttgi = mlir::triton::gpu::intel;
#define GEN_PASS_CLASSES
#include "triton/Dialect/TritonIntelGPU/Transforms/Passes.h.inc"
namespace {
-/// An additional struct to record the meta informati... | We still need to check whether it is contiguous on the fast changing dim. |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | chengjunlu | @@ -17,22 +18,86 @@
using namespace mlir;
namespace tt = mlir::triton;
+namespace ttg = mlir::triton::gpu;
namespace ttgi = mlir::triton::gpu::intel;
#define GEN_PASS_CLASSES
#include "triton/Dialect/TritonIntelGPU/Transforms/Passes.h.inc"
namespace {
-/// An additional struct to record the meta informati... | Return true earlier for the non-PVC arch. Only PVC has the 2D load/store |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | etiotto | @@ -17,22 +18,86 @@
using namespace mlir;
namespace tt = mlir::triton;
+namespace ttg = mlir::triton::gpu;
namespace ttgi = mlir::triton::gpu::intel;
#define GEN_PASS_CLASSES
#include "triton/Dialect/TritonIntelGPU/Transforms/Passes.h.inc"
namespace {
-/// An additional struct to record the meta informati... | If the dynamic cast fails you cannot use attr in the next line. |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | etiotto | @@ -17,22 +18,86 @@
using namespace mlir;
namespace tt = mlir::triton;
+namespace ttg = mlir::triton::gpu;
namespace ttgi = mlir::triton::gpu::intel;
#define GEN_PASS_CLASSES
#include "triton/Dialect/TritonIntelGPU/Transforms/Passes.h.inc"
namespace {
-/// An additional struct to record the meta informati... | ```suggestion
return isDivisible(op->getOperand(0), divisor);
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | etiotto | @@ -17,22 +18,86 @@
using namespace mlir;
namespace tt = mlir::triton;
+namespace ttg = mlir::triton::gpu;
namespace ttgi = mlir::triton::gpu::intel;
#define GEN_PASS_CLASSES
#include "triton/Dialect/TritonIntelGPU/Transforms/Passes.h.inc"
namespace {
-/// An additional struct to record the meta informati... | ```suggestion
}
return false;
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | etiotto | @@ -17,22 +18,86 @@
using namespace mlir;
namespace tt = mlir::triton;
+namespace ttg = mlir::triton::gpu;
namespace ttgi = mlir::triton::gpu::intel;
#define GEN_PASS_CLASSES
#include "triton/Dialect/TritonIntelGPU/Transforms/Passes.h.inc"
namespace {
-/// An additional struct to record the meta informati... | ```suggestion
return (strideInt.getInt() != 1);
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | etiotto | @@ -301,9 +427,15 @@ class TritonIntelGPURewriteTensorPointerPass
if (auto loadOp = dyn_cast<tt::LoadOp>(op)) {
assert(!loadOp.getMask() && !loadOp.getOther());
boundaryCheck = loadOp.getBoundaryCheck();
+ if (auto valueType =
+ dyn_cast<RankedTensorType>(loadOp.getResult().getType(... | if is not a tt.LoadOp it must be a tt.StoreOp (there is an assert earlier). You can change the `else if` to an `else`. |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | etiotto | @@ -301,9 +427,15 @@ class TritonIntelGPURewriteTensorPointerPass
if (auto loadOp = dyn_cast<tt::LoadOp>(op)) {
assert(!loadOp.getMask() && !loadOp.getOther()); | Add msg to assert (`assert(cond && msg)`) |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | etiotto | @@ -282,14 +409,13 @@ class TritonIntelGPURewriteTensorPointerPass
Operation *rewriteLoadStoreOp(OpBuilder &builder, Operation *op,
std::stack<Operation *> &eraser) {
- assert(isa<tt::LoadOp>(op) || isa<tt::StoreOp>(op));
-
- // We only have to rewrite load/stores with tensor... | Add msg to assert (assert(cond && msg)) |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | etiotto | @@ -301,9 +427,15 @@ class TritonIntelGPURewriteTensorPointerPass
if (auto loadOp = dyn_cast<tt::LoadOp>(op)) {
assert(!loadOp.getMask() && !loadOp.getOther());
boundaryCheck = loadOp.getBoundaryCheck();
+ if (auto valueType =
+ dyn_cast<RankedTensorType>(loadOp.getResult().getType(... | Add msg to assert (assert(cond && msg)) |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | etiotto | @@ -548,6 +701,41 @@ class TritonIntelGPURewriteTensorPointerPass
}
void runOnOperation() override {
+ ModuleOp mod = getOperation();
+
+ auto checkAndMarkToRemove = [this](Value val) {
+ if (!tt::isTensorPointerType(val.getType()))
+ return;
+ tt::MakeTensorPtrOp makeTensorPtrOp = getMak... | ```suggestion
} else if (isa<tt::AdvanceOp>(op) || isa<tt::LoadOp>(op)) {
checkAndMarkToRemove(op->getOperand(0));
}
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | whitneywhtsang | @@ -17,22 +18,88 @@
using namespace mlir;
namespace tt = mlir::triton;
+namespace ttg = mlir::triton::gpu;
namespace ttgi = mlir::triton::gpu::intel;
#define GEN_PASS_CLASSES
#include "triton/Dialect/TritonIntelGPU/Transforms/Passes.h.inc"
namespace {
-/// An additional struct to record the meta informati... | remove, because we already checked. |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | whitneywhtsang | @@ -68,16 +136,63 @@ struct RewritedInfo {
cachedOffsetWithRange.clear();
}
+ void setEncoding(Attribute newLayout) { layout = newLayout; }
+
+ // Creates a tensor with the values [0, tensorShape[axis]) + offsets[axis]
+ // broadcasted to N dimensions along axis (i.e. so that
+ // result[.., <axis'th dim>... | ```suggestion
// [0,1,2]
// layouts[3] = layout, containing axes [0,1,2,3]
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | whitneywhtsang | @@ -68,16 +136,63 @@ struct RewritedInfo {
cachedOffsetWithRange.clear();
}
+ void setEncoding(Attribute newLayout) { layout = newLayout; }
+
+ // Creates a tensor with the values [0, tensorShape[axis]) + offsets[axis]
+ // broadcasted to N dimensions along axis (i.e. so that
+ // result[.., <axis'th dim>... | ```suggestion
for (int64_t k = rank - 2; k >= 0; --k) {
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | whitneywhtsang | @@ -68,16 +136,63 @@ struct RewritedInfo {
cachedOffsetWithRange.clear();
}
+ void setEncoding(Attribute newLayout) { layout = newLayout; }
+
+ // Creates a tensor with the values [0, tensorShape[axis]) + offsets[axis]
+ // broadcasted to N dimensions along axis (i.e. so that
+ // result[.., <axis'th dim>... | ```suggestion
--axisToRemove;
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | whitneywhtsang | @@ -68,16 +136,63 @@ struct RewritedInfo {
cachedOffsetWithRange.clear();
}
+ void setEncoding(Attribute newLayout) { layout = newLayout; }
+
+ // Creates a tensor with the values [0, tensorShape[axis]) + offsets[axis]
+ // broadcasted to N dimensions along axis (i.e. so that
+ // result[.., <axis'th dim>... | ```suggestion
--axisToRemove;
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | whitneywhtsang | @@ -205,21 +323,30 @@ struct RewritedInfo {
class TritonIntelGPURewriteTensorPointerPass
: public TritonIntelGPURewriteTensorPointerBase<
TritonIntelGPURewriteTensorPointerPass> {
+
+public:
+ TritonIntelGPURewriteTensorPointerPass() = default; | remove? |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | etiotto | @@ -17,22 +18,87 @@
using namespace mlir;
namespace tt = mlir::triton;
+namespace ttg = mlir::triton::gpu;
namespace ttgi = mlir::triton::gpu::intel;
#define GEN_PASS_CLASSES
#include "triton/Dialect/TritonIntelGPU/Transforms/Passes.h.inc"
namespace {
-/// An additional struct to record the meta informati... | We should use the form cast<type>(value) instead of this older style. |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | etiotto | @@ -17,22 +18,87 @@
using namespace mlir;
namespace tt = mlir::triton;
+namespace ttg = mlir::triton::gpu;
namespace ttgi = mlir::triton::gpu::intel;
#define GEN_PASS_CLASSES
#include "triton/Dialect/TritonIntelGPU/Transforms/Passes.h.inc"
namespace {
-/// An additional struct to record the meta informati... | [nit]:
```suggestion
if (!dpasLayout)
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | etiotto | @@ -17,22 +18,87 @@
using namespace mlir;
namespace tt = mlir::triton;
+namespace ttg = mlir::triton::gpu;
namespace ttgi = mlir::triton::gpu::intel;
#define GEN_PASS_CLASSES
#include "triton/Dialect/TritonIntelGPU/Transforms/Passes.h.inc"
namespace {
-/// An additional struct to record the meta informati... | Can we use the static type here? |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | etiotto | @@ -205,21 +323,29 @@ struct RewritedInfo {
class TritonIntelGPURewriteTensorPointerPass
: public TritonIntelGPURewriteTensorPointerBase<
TritonIntelGPURewriteTensorPointerPass> {
+
+public:
+ TritonIntelGPURewriteTensorPointerPass(ttgi::DeviceArch arch) {
+ this->deviceArch = arch;
+ }
+
private... | Move the private "section" to the end of this class and move all the public member function into the same section. |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | etiotto | @@ -17,22 +18,87 @@
using namespace mlir;
namespace tt = mlir::triton;
+namespace ttg = mlir::triton::gpu;
namespace ttgi = mlir::triton::gpu::intel;
#define GEN_PASS_CLASSES
#include "triton/Dialect/TritonIntelGPU/Transforms/Passes.h.inc"
namespace {
-/// An additional struct to record the meta informati... | Add documentation to the function. |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | etiotto | @@ -17,22 +18,87 @@
using namespace mlir;
namespace tt = mlir::triton;
+namespace ttg = mlir::triton::gpu;
namespace ttgi = mlir::triton::gpu::intel;
#define GEN_PASS_CLASSES
#include "triton/Dialect/TritonIntelGPU/Transforms/Passes.h.inc"
namespace {
-/// An additional struct to record the meta informati... | Add documentation to the function. |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | etiotto | @@ -45,11 +111,12 @@ struct RewritedInfo {
RewritedInfo(Value base, const SmallVector<Value> &shape,
const SmallVector<Value> &strides,
const SmallVector<Value> &offsets,
- const ArrayRef<int64_t> &tensorShape)
+ const ArrayRef<int64_t> &tensorShape, Attrib... | at line 124 and 126: declare member functions that do not modify the object state (e.g. getOffset/getOffsets) as "const" pls. |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | etiotto | @@ -548,6 +720,39 @@ class TritonIntelGPURewriteTensorPointerPass
}
void runOnOperation() override {
+ ModuleOp mod = getOperation();
+
+ auto checkAndMarkToRemove = [this](Value val) {
+ if (!tt::isTensorPointerType(val.getType()))
+ return;
+ tt::MakeTensorPtrOp makeTensorPtrOp = getMak... | Change to a forall loop |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | etiotto | @@ -548,6 +720,39 @@ class TritonIntelGPURewriteTensorPointerPass
}
void runOnOperation() override {
+ ModuleOp mod = getOperation();
+
+ auto checkAndMarkToRemove = [this](Value val) {
+ if (!tt::isTensorPointerType(val.getType()))
+ return;
+ tt::MakeTensorPtrOp makeTensorPtrOp = getMak... | Change to a forall loop |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | etiotto | @@ -548,6 +720,39 @@ class TritonIntelGPURewriteTensorPointerPass
}
void runOnOperation() override {
+ ModuleOp mod = getOperation();
+
+ auto checkAndMarkToRemove = [this](Value val) {
+ if (!tt::isTensorPointerType(val.getType()))
+ return;
+ tt::MakeTensorPtrOp makeTensorPtrOp = getMak... | ```suggestion
if (tt::isTensorPointerType(val.getType())) {
tt::MakeTensorPtrOp makeTensorPtrOp = getMakeTensorPtrOp(val);
if (shouldRemove(makeTensorPtrOp, this->deviceArch))
valueToRemove.insert(val);
}
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 958 | intel | etiotto | @@ -548,6 +720,39 @@ class TritonIntelGPURewriteTensorPointerPass
}
void runOnOperation() override {
+ ModuleOp mod = getOperation();
+
+ auto checkAndMarkToRemove = [this](Value val) { | This lambda doesn't remove the tensor pointer, it just marks it for removal. Use a more precise name. |
intel-xpu-backend-for-triton | github_2023 | cpp | 865 | intel | chengjunlu | @@ -83,9 +83,6 @@ void LoadOp::build(OpBuilder &builder, OperationState &state, Value ptr,
padding.has_value()
? PaddingOptionAttr::get(builder.getContext(), padding.value())
: PaddingOptionAttr();
- LoadOp::build(builder, state, ptr, mask, other, | Revert this. |
intel-xpu-backend-for-triton | github_2023 | cpp | 865 | intel | chengjunlu | @@ -44,6 +44,10 @@ void init_triton_intel_passes_ttgpuir(py::module &&m) {
m.def("add_allocate_shared_memory", [](mlir::PassManager &pm) {
pm.addPass(createIntelAllocateSharedMemoryPass());
});
+ m.def("add_materialize_block_pointer", [](mlir::PassManager &self) {
+ self.addPass(mlir::triton::gpu::intel:... | Let's add the GPU arch options. Only the PVC has the 2D memory accessing |
intel-xpu-backend-for-triton | github_2023 | cpp | 865 | intel | chengjunlu | @@ -0,0 +1,186 @@
+#include "mlir/Dialect/Tensor/IR/Tensor.h"
+#include "triton/Analysis/Utility.h"
+#include "triton/Dialect/TritonGPU/IR/Dialect.h"
+#include "triton/Dialect/TritonGPU/Transforms/Utility.h"
+#include "triton/Dialect/TritonIntelGPU/IR/Dialect.h"
+#include "triton/Dialect/TritonIntelGPU/Transforms/Passe... | We need to pop the load op with multiple block pointer by make_tensor_ptr. |
intel-xpu-backend-for-triton | github_2023 | others | 865 | intel | chengjunlu | @@ -123,4 +123,24 @@ def TritonIntelGPUPrefetchBlock : Pass<"tritonintelgpu-prefetch-block", "mlir::M
];
}
+def TritonIntelGPUMaterializeBlockPointer : Pass<"tritonintelgpu-materialize-block-pointer", "mlir::ModuleOp"> {
+ let summary = "Intel GPU materialize block pointer";
+
+ let description = [{
+ }];
+
+ ... | Clean the unused options. |
intel-xpu-backend-for-triton | github_2023 | cpp | 865 | intel | chengjunlu | @@ -179,17 +179,24 @@ unsigned DpasEncodingAttr::getTotalElemsPerThreadForOperands(
int warpsPerCTAM = getWarpsPerCTA()[0];
int warpsPerCTAN = getWarpsPerCTA()[1];
auto rep = getDPASRepetitions(shapePerCTA, opIdx);
- auto threadsPerWar = getSubGroupSize();
+ auto threadsPerWarp = getSubGroupSize();
if (op... | This change is not need so far. Let me double check. |
intel-xpu-backend-for-triton | github_2023 | cpp | 970 | intel | victor-eds | @@ -1329,44 +1329,22 @@ struct FpToFpOpConversion
ConversionPatternRewriter &rewriter,
const Value &v, const RoundingMode rounding) {
MLIRContext *ctx = rewriter.getContext();
- auto moduleOp =
- rewriter.getBlock()->getParent()->getPare... | ```suggestion
llvm_unreachable("Unsupported rounding mode");
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 970 | intel | victor-eds | @@ -1329,44 +1329,22 @@ struct FpToFpOpConversion
ConversionPatternRewriter &rewriter,
const Value &v, const RoundingMode rounding) {
MLIRContext *ctx = rewriter.getContext();
- auto moduleOp =
- rewriter.getBlock()->getParent()->getPare... | Can we extract this to a function like [`convertArithRoundingModeToLLVM`](https://github.com/llvm/llvm-project/blob/03b1a0c2a72dd24943642ef15e6c046d982643c2/mlir/lib/Conversion/ArithCommon/AttrToLLVMConverter.cpp#L53)? |
intel-xpu-backend-for-triton | github_2023 | cpp | 970 | intel | victor-eds | @@ -1329,44 +1329,22 @@ struct FpToFpOpConversion
ConversionPatternRewriter &rewriter,
const Value &v, const RoundingMode rounding) {
MLIRContext *ctx = rewriter.getContext();
- auto moduleOp =
- rewriter.getBlock()->getParent()->getPare... | Why not create the LLVM op right away not going through `arith`? ([see](https://mlir.llvm.org/docs/Dialects/LLVM/#llvmintrexperimentalconstrainedfptrunc-llvmconstrainedfptruncintr)). I developed both as I though you would use the `arith` one for other purpouses. |
intel-xpu-backend-for-triton | github_2023 | cpp | 970 | intel | etiotto | @@ -1350,23 +1346,34 @@ struct FpToFpOpConversion
llvm_unreachable("");
}
- Operation *funcOp = moduleOp.lookupSymbol(funcName);
- if (!funcOp) {
- auto funcType =
- LLVM::LLVMFunctionType::get(f16_ty, {f32_ty}, /*isVarArg*/ false);
- ConversionPatternRewriter::InsertionGuard guar... | Remove dead code |
intel-xpu-backend-for-triton | github_2023 | cpp | 970 | intel | victor-eds | @@ -1325,48 +1326,36 @@ struct FpToFpOpConversion
return truncated;
}
- static Value convertFp32ToFp16(Location loc,
- ConversionPatternRewriter &rewriter,
- const Value &v, const RoundingMode rounding) {
- MLIRContext *ctx = rewriter.getCont... | ```suggestion
return rewriter.create<LLVM::ConstrainedFPTruncIntr>(loc, f16_ty, v,
LLVM::RoundingModeAttr::get(
ctx, convertTritonRoundingModeToLLVM(rounding)),
arith::getLLVMDefaultFPExceptionBehavior(*... |
intel-xpu-backend-for-triton | github_2023 | cpp | 966 | intel | whitneywhtsang | @@ -0,0 +1,25 @@
+//===- TypeConverter.h - TritonIntelGPUToLLVM Type Converter ----*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---... | ```suggestion
#endif // TRITON_CONVERSION_TRITONINTELGPUTOLLVM_TYPECONVERTER_H
``` |
intel-xpu-backend-for-triton | github_2023 | python | 963 | intel | etiotto | @@ -458,8 +458,8 @@ def backward(ctx, do):
CAUSAL=ctx.causal, #
MMA_V3=MMA_V3, #
num_warps=8, # | Question: given we reduce the threads_per_warp in half (from the default (32) to 16), should we double the number of warps ? |
intel-xpu-backend-for-triton | github_2023 | others | 941 | intel | chengjunlu | @@ -185,4 +185,28 @@ def TritonIntelGPUMatchTargetSize : Pass<"tritonintelgpu-match-target-size", "ml
"mlir::triton::gpu::intel::TritonIntelGPUDialect"];
}
+def TritonIntelGPURewriteTensorPointer : Pass</*cli-arg*/"tritonintelgpu-rewrite-tensor-pointer", /*Op*/"mlir::ModuleOp"> {
+ let s... | Change the comments for the things you made to support 2D load for now. |
intel-xpu-backend-for-triton | github_2023 | others | 941 | intel | etiotto | @@ -185,4 +185,29 @@ def TritonIntelGPUMatchTargetSize : Pass<"tritonintelgpu-match-target-size", "ml
"mlir::triton::gpu::intel::TritonIntelGPUDialect"];
}
+def TritonIntelGPURewriteTensorPointer : Pass</*cli-arg*/"tritonintelgpu-rewrite-tensor-pointer", /*Op*/"mlir::ModuleOp"> { | I do not think the comment `/*cli_arg*/` and `/*Op*/` add much info to the operation, I would remove them. |
intel-xpu-backend-for-triton | github_2023 | others | 941 | intel | etiotto | @@ -0,0 +1,45 @@
+// RUN: triton-opt %s -split-input-file --intel-allocate-shared-memory --convert-triton-intel-gpu-to-llvm | FileCheck %s | Do we need ` --intel-allocate-shared-memory` to test the new pass. It would be better to do not add a dependency on that pass in a lit test designed to test only one transformation. Can you please remove it? |
intel-xpu-backend-for-triton | github_2023 | others | 941 | intel | etiotto | @@ -0,0 +1,45 @@
+// RUN: triton-opt %s -split-input-file --intel-allocate-shared-memory --convert-triton-intel-gpu-to-llvm | FileCheck %s
+
+// CHECK: llvm.func spir_funccc @llvm.genx.GenISA.LSC2DBlockRead.v8i32(i64, i32, i32, i32, i32, i32, i32, i32, i32, i32, i1, i1, i32) -> vector<8xi32>
+// CHECK: llvm.func spir_f... | Given every argument is `{{.*}}` is not possible to determine the 2D block load is for one load etc... Rewrite the CHECKS to provide more context. |
intel-xpu-backend-for-triton | github_2023 | others | 941 | intel | etiotto | @@ -0,0 +1,45 @@
+// RUN: triton-opt %s -split-input-file --intel-allocate-shared-memory --convert-triton-intel-gpu-to-llvm | FileCheck %s
+
+// CHECK: llvm.func spir_funccc @llvm.genx.GenISA.LSC2DBlockRead.v8i32(i64, i32, i32, i32, i32, i32, i32, i32, i32, i32, i1, i1, i32) -> vector<8xi32>
+// CHECK: llvm.func spir_f... | use #dpas not #mma |
intel-xpu-backend-for-triton | github_2023 | others | 941 | intel | etiotto | @@ -0,0 +1,45 @@
+// RUN: triton-opt %s -split-input-file --intel-allocate-shared-memory --convert-triton-intel-gpu-to-llvm | FileCheck %s
+
+// CHECK: llvm.func spir_funccc @llvm.genx.GenISA.LSC2DBlockRead.v8i32(i64, i32, i32, i32, i32, i32, i32, i32, i32, i32, i1, i1, i32) -> vector<8xi32>
+// CHECK: llvm.func spir_f... | Can we simplify the test by removing `{tt.divisibility = 16 : i32}` ? and `attributes {noinline = false}`. The goal of a good lit test is to be as small as possible (and still test that the pass works as designed). |
intel-xpu-backend-for-triton | github_2023 | others | 941 | intel | etiotto | @@ -0,0 +1,105 @@
+// RUN: triton-opt %s -split-input-file --tritonintelgpu-rewrite-tensor-pointer=device-architecture=PVC | FileCheck %s
+
+// CHECK: #[[$BLOCKED:.+]] = #triton_gpu.blocked<{sizePerThread = [1, 1], threadsPerWarp = [1, 16], warpsPerCTA = [4, 16], order = [1, 0]}> | Add a `//COM: ...` to all the new tests to explain what are the objectives of the test (what does it test?) |
intel-xpu-backend-for-triton | github_2023 | others | 941 | intel | etiotto | @@ -0,0 +1,105 @@
+// RUN: triton-opt %s -split-input-file --tritonintelgpu-rewrite-tensor-pointer=device-architecture=PVC | FileCheck %s
+
+// CHECK: #[[$BLOCKED:.+]] = #triton_gpu.blocked<{sizePerThread = [1, 1], threadsPerWarp = [1, 16], warpsPerCTA = [4, 16], order = [1, 0]}>
+// CHECK: #[[$MMA:.+]] = #triton_intel... | #mma -> #dpas |
intel-xpu-backend-for-triton | github_2023 | others | 941 | intel | etiotto | @@ -0,0 +1,105 @@
+// RUN: triton-opt %s -split-input-file --tritonintelgpu-rewrite-tensor-pointer=device-architecture=PVC | FileCheck %s
+
+// CHECK: #[[$BLOCKED:.+]] = #triton_gpu.blocked<{sizePerThread = [1, 1], threadsPerWarp = [1, 16], warpsPerCTA = [4, 16], order = [1, 0]}>
+// CHECK: #[[$MMA:.+]] = #triton_intel... | This is the key part of this test right ? To test that the 2 `tt.load` are preserved ? |
intel-xpu-backend-for-triton | github_2023 | others | 941 | intel | etiotto | @@ -0,0 +1,105 @@
+// RUN: triton-opt %s -split-input-file --tritonintelgpu-rewrite-tensor-pointer=device-architecture=PVC | FileCheck %s
+
+// CHECK: #[[$BLOCKED:.+]] = #triton_gpu.blocked<{sizePerThread = [1, 1], threadsPerWarp = [1, 16], warpsPerCTA = [4, 16], order = [1, 0]}>
+// CHECK: #[[$MMA:.+]] = #triton_intel... | Are all of this `CHECKS` really necessary ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 941 | intel | etiotto | @@ -141,6 +142,182 @@ struct LoadOpConversion
: ConvertTritonGPUOpToLLVMPattern<triton::LoadOp>(converter, benefit),
LoadStoreConversionBase(axisAnalysisPass) {}
+ std::tuple<Value, Value, Value, Value, Value, Value, Value>
+ getValuesFromBlockPointerStruct(Value blockPointer,
+ ... | Add a comment to indicate what this member function does. With an example. |
intel-xpu-backend-for-triton | github_2023 | cpp | 941 | intel | etiotto | @@ -141,6 +142,182 @@ struct LoadOpConversion
: ConvertTritonGPUOpToLLVMPattern<triton::LoadOp>(converter, benefit),
LoadStoreConversionBase(axisAnalysisPass) {}
+ std::tuple<Value, Value, Value, Value, Value, Value, Value>
+ getValuesFromBlockPointerStruct(Value blockPointer,
+ ... | Use the static type instead of `auto`. |
intel-xpu-backend-for-triton | github_2023 | cpp | 941 | intel | etiotto | @@ -141,6 +142,182 @@ struct LoadOpConversion
: ConvertTritonGPUOpToLLVMPattern<triton::LoadOp>(converter, benefit),
LoadStoreConversionBase(axisAnalysisPass) {}
+ std::tuple<Value, Value, Value, Value, Value, Value, Value>
+ getValuesFromBlockPointerStruct(Value blockPointer,
+ ... | Given that the caller checks that the `ptr` argument of the load is a pointer to tensor, the result should of the load should be a tensor. So can you assert here (instead of an if...) |
intel-xpu-backend-for-triton | github_2023 | cpp | 941 | intel | etiotto | @@ -141,6 +142,182 @@ struct LoadOpConversion
: ConvertTritonGPUOpToLLVMPattern<triton::LoadOp>(converter, benefit),
LoadStoreConversionBase(axisAnalysisPass) {}
+ std::tuple<Value, Value, Value, Value, Value, Value, Value>
+ getValuesFromBlockPointerStruct(Value blockPointer,
+ ... | Is better to avoid large nested regions in the code (helps readability). Can you early return if the tensor does not have `dot` layout ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 941 | intel | etiotto | @@ -141,6 +142,182 @@ struct LoadOpConversion
: ConvertTritonGPUOpToLLVMPattern<triton::LoadOp>(converter, benefit),
LoadStoreConversionBase(axisAnalysisPass) {}
+ std::tuple<Value, Value, Value, Value, Value, Value, Value>
+ getValuesFromBlockPointerStruct(Value blockPointer,
+ ... | This block of code is too large. Need to simplify/refactor this code. |
intel-xpu-backend-for-triton | github_2023 | cpp | 941 | intel | etiotto | @@ -141,6 +142,182 @@ struct LoadOpConversion
: ConvertTritonGPUOpToLLVMPattern<triton::LoadOp>(converter, benefit),
LoadStoreConversionBase(axisAnalysisPass) {}
+ std::tuple<Value, Value, Value, Value, Value, Value, Value>
+ getValuesFromBlockPointerStruct(Value blockPointer,
+ ... | Can you try to factor out this code segment into a lambda so that you can pass the shape of either operand A or operand B and reuse the same code (the lambda) for both operands.
Does this work?
```
auto getLoad2DType = [&](SmallVectorImpl<unsigned> &shape, IntegerType packedType){
elemsPerInstr = {shape[0], sh... |
intel-xpu-backend-for-triton | github_2023 | others | 941 | intel | etiotto | @@ -1,4 +1,7 @@
// RUN: triton-opt %s -tritonintelgpu-rewrite-tensor-pointer | FileCheck %s
+// FIXME
+// XFAIL: * | Why does this fail? |
intel-xpu-backend-for-triton | github_2023 | cpp | 941 | intel | chengjunlu | @@ -66,20 +136,66 @@ struct RewritedInfo {
cachedOffsetWithRange.clear();
}
+ void setEncoding(Attribute newLayout) { layout = newLayout; }
+
+ // Creates a tensor with the values [0, tensorShape[axis]) + offsets[axis]
+ // broadcasted to N dimensions along axis (i.e. so that
+ // result[.., <axis'th dim>... | Please add the changes for the supporting run this pass on TTIR. |
intel-xpu-backend-for-triton | github_2023 | cpp | 941 | intel | chengjunlu | @@ -7,21 +7,90 @@
//===----------------------------------------------------------------------===//
#include "mlir/Dialect/ControlFlow/IR/ControlFlowOps.h"
+#include "mlir/IR/ValueRange.h"
#include "mlir/Pass/Pass.h"
#include "triton/Analysis/Utility.h"
+#include "triton/Dialect/Triton/IR/Dialect.h"
#include "tri... | Please use the `strides[order[0]]` for general supporting the Triton multi-dimensional representation. |
intel-xpu-backend-for-triton | github_2023 | cpp | 941 | intel | chengjunlu | @@ -7,21 +7,90 @@
//===----------------------------------------------------------------------===//
#include "mlir/Dialect/ControlFlow/IR/ControlFlowOps.h"
+#include "mlir/IR/ValueRange.h"
#include "mlir/Pass/Pass.h"
#include "triton/Analysis/Utility.h"
+#include "triton/Dialect/Triton/IR/Dialect.h"
#include "tri... | Please file a issue to track the supporting on the column major B matrix which is required for the flash attention. |
intel-xpu-backend-for-triton | github_2023 | cpp | 941 | intel | chengjunlu | @@ -542,14 +709,64 @@ class TritonIntelGPURewriteTensorPointerPass
// Rewrite and recursively visit
for (auto &nestedOp : blockCopy) {
- if (auto newOp = rewriteOp(nestedOp, eraser))
- visitOperation(newOp, eraser);
+ if (auto newOp = rewriteOp(nestedOp, eraser, valueToR... | We can re-align the changes here. I made different changes to support partial rewrite tensor pointer. |
intel-xpu-backend-for-triton | github_2023 | cpp | 962 | intel | etiotto | @@ -614,7 +612,8 @@ struct AtomicRMWOpConversion
Block *endBlock = nullptr;
// TODO: check device capabilities to avoid unnecessary emulation or
// emit unsupported feature error.
- if (valueElemNBits == 16 && emulateFp16Atomics) {
+ if (valueElemNBits == 16) {
+ op.emitOpError("us... | "fp16 datatype is not supported in the target HW, software emulation is an experimental feature (use at own risk)" |
intel-xpu-backend-for-triton | github_2023 | python | 906 | intel | etiotto | @@ -4816,6 +4816,15 @@ def test_convert2d(M, N, src_layout, interm_layout, dst_layout, dtype, device):
# skip even if scratch buffer equal to lds_size, because real scratch buffer is typically larger due to padding
if scratch_shape[0] * scratch_shape[1] * int32_size >= lds_size:
pytest.sk... | enclose in try/except construct like for AMD ? |
intel-xpu-backend-for-triton | github_2023 | python | 906 | intel | etiotto | @@ -4816,6 +4816,15 @@ def test_convert2d(M, N, src_layout, interm_layout, dst_layout, dtype, device):
# skip even if scratch buffer equal to lds_size, because real scratch buffer is typically larger due to padding
if scratch_shape[0] * scratch_shape[1] * int32_size >= lds_size:
pytest.sk... | lds_size -> shared_mem_size |
intel-xpu-backend-for-triton | github_2023 | python | 906 | intel | etiotto | @@ -4816,6 +4816,15 @@ def test_convert2d(M, N, src_layout, interm_layout, dst_layout, dtype, device):
# skip even if scratch buffer equal to lds_size, because real scratch buffer is typically larger due to padding
if scratch_shape[0] * scratch_shape[1] * int32_size >= lds_size:
pytest.sk... | Does 0 hard code the first device available? What about getting the current device with `triton.runtime.driver.active.get_current_device()` |
intel-xpu-backend-for-triton | github_2023 | python | 906 | intel | whitneywhtsang | @@ -4804,18 +4804,29 @@ def test_convert2d(M, N, src_layout, interm_layout, dst_layout, dtype, device):
pytest.xfail("Out of bound access when maxPhase > 1")
if str(src_layout) == str(dst_layout):
pytest.xfail("Do not convert same layout")
- if is_hip():
+ if is_hip() or is_xpu():
... | can we use `scratch_shape` calculated at line 4809? |
intel-xpu-backend-for-triton | github_2023 | python | 906 | intel | whitneywhtsang | @@ -4804,18 +4804,29 @@ def test_convert2d(M, N, src_layout, interm_layout, dst_layout, dtype, device):
pytest.xfail("Out of bound access when maxPhase > 1")
if str(src_layout) == str(dst_layout):
pytest.xfail("Do not convert same layout")
- if is_hip():
+ if is_hip() or is_xpu():
... | I assume there is nothing we can do about that, so not a failure we should count toward pass rate calculation, let's change it to `xfail`.
```suggestion
pytest.xfail("Scratch buffer is too large")
``` |
intel-xpu-backend-for-triton | github_2023 | python | 906 | intel | whitneywhtsang | @@ -4804,18 +4804,29 @@ def test_convert2d(M, N, src_layout, interm_layout, dst_layout, dtype, device):
pytest.xfail("Out of bound access when maxPhase > 1")
if str(src_layout) == str(dst_layout):
pytest.xfail("Do not convert same layout")
- if is_hip():
+ if is_hip() or is_xpu():
... | can we common code for hip and xpu, and only specialize lds_size/shared_mem_size? |
intel-xpu-backend-for-triton | github_2023 | python | 906 | intel | whitneywhtsang | @@ -4839,6 +4839,16 @@ def test_convert2d(M, N, src_layout, interm_layout, dst_layout, dtype, device):
# skip even if scratch buffer equal to lds_size, because real scratch buffer is typically larger due to padding
if scratch_shape[0] * scratch_shape[1] * int32_size >= lds_size:
pytest.sk... | Do you think we can common with is_hip code now that `compute_scratch_buffer_shape` always work for our use case? |
intel-xpu-backend-for-triton | github_2023 | cpp | 939 | intel | Dewei-Wang-sh | @@ -0,0 +1,248 @@
+//===- TritonGENDialect.h - MLIR TritonGEN dialect --------------*- C++ -*-===// | copy typo |
intel-xpu-backend-for-triton | github_2023 | cpp | 939 | intel | whitneywhtsang | @@ -190,20 +192,21 @@ struct ConvertTritonGPUToLLVM
int threadsPerWarp = triton::gpu::TritonGPUDialect::getThreadsPerWarp(mod);
// Allocate shared memory and set barrier
- ModuleAllocation allocation(mod);
- ModuleMembarAnalysis membarPass(&allocation);
- membarPass.run();
+ if (!pipelineManager... | To avoid copying the whole FuncOpConversion class, could we keep `funcPatterns.add<FuncOpConversion>(typeConverter, numWarps, /*benefit=*/1);` here? |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.