repo_name stringlengths 1 62 | dataset stringclasses 1
value | lang stringclasses 11
values | pr_id int64 1 20.1k | owner stringlengths 2 34 | reviewer stringlengths 2 39 | diff_hunk stringlengths 15 262k | code_review_comment stringlengths 1 99.6k |
|---|---|---|---|---|---|---|---|
intel-xpu-backend-for-triton | github_2023 | cpp | 1,249 | intel | victor-eds | @@ -30,45 +26,67 @@
#include "mlir/Target/LLVMIR/TypeToLLVM.h"
#include "llvm/ADT/TypeSwitch.h"
+#include "llvm/IR/Attributes.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/Support/ErrorHandling.h"
-#include <string>
-#include <type_traits>
#include "triton/Conversion/TritonGPUToLLVM/Utility.h"
#include "t... | ```suggestion
static intel::AttributeList
getAttrList(const intel::AttrBuilder &funcAttrBuilder, ArrayRef<NamedAttrList> paramAttrs = std::nullopt) {
intel::AttributeList attrs;
attrs.addFnAttrs(funcAttrBuilder);
if (!paramAttrs.empty())
attrs.addParamAttributes(paramAttrs.value());
return attrs;
}
... |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,249 | intel | victor-eds | @@ -30,45 +26,67 @@
#include "mlir/Target/LLVMIR/TypeToLLVM.h"
#include "llvm/ADT/TypeSwitch.h"
+#include "llvm/IR/Attributes.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/Support/ErrorHandling.h"
-#include <string>
-#include <type_traits>
#include "triton/Conversion/TritonGPUToLLVM/Utility.h"
#include "t... | Maybe we can:
```
for (auto pair = llvm::enumerate(attrs.getParamAttributes())) {
auto &[idx, attrList] = pair;
for (NamedAttribute attr : attrList)
funcOp.setArgAttr(idx, attr.getName(), attr.getValue());
}
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,249 | intel | victor-eds | @@ -379,14 +421,21 @@ createBlock2DReadWithAddressPayloadUpdate(TritonGEN::Matrix2DBlockLoadOp op,
assert(isa<LLVM::LLVMPointerType>(ptr.getType()) &&
"Expecting a pointer type");
SmallVector<Type> argTypes{ptr.getType(), i32_ty};
+
+ // Function and parameters attributes.
+ intel::AttrBuild... | ```suggestion
intel::AttrBuilder funcAttrBuilder(*ctx);
intel::AttrBuilder paramAttrBuilder(*ctx);
```
Readability |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,249 | intel | victor-eds | @@ -403,8 +452,17 @@ createBlock2DReadWithAddressPayloadUpdate(TritonGEN::Matrix2DBlockLoadOp op,
Value zero = i32_val(0);
SmallVector<Type> argTypes{ptr.getType(), i32_ty, i32_ty, i32_ty};
SmallVector<Value> args{ptr, zero, zero, zero};
+
+ // Function and parameters attributes.
+ intel::AttrBuild... | ```suggestion
intel::AttrBuilder funcAttrBuilder(*ctx);
intel::AttrBuilder paramAttrBuilder(*ctx);
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,249 | intel | victor-eds | @@ -379,14 +421,21 @@ createBlock2DReadWithAddressPayloadUpdate(TritonGEN::Matrix2DBlockLoadOp op,
assert(isa<LLVM::LLVMPointerType>(ptr.getType()) &&
"Expecting a pointer type");
SmallVector<Type> argTypes{ptr.getType(), i32_ty};
+
+ // Function and parameters attributes.
+ intel::AttrBuild... | Can we use `std::vector<NamedAttrList, 1>` instead? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,249 | intel | victor-eds | @@ -403,8 +452,17 @@ createBlock2DReadWithAddressPayloadUpdate(TritonGEN::Matrix2DBlockLoadOp op,
Value zero = i32_val(0);
SmallVector<Type> argTypes{ptr.getType(), i32_ty, i32_ty, i32_ty};
SmallVector<Value> args{ptr, zero, zero, zero};
+
+ // Function and parameters attributes.
+ intel::AttrBuild... |
Can we use std::vector<NamedAttrList, 1> instead?
|
intel-xpu-backend-for-triton | github_2023 | cpp | 1,249 | intel | whitneywhtsang | @@ -0,0 +1,218 @@
+//===- Attributes.h - Construct MLIR attributes -----------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | usually this follow the path. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,249 | intel | whitneywhtsang | @@ -30,45 +26,62 @@
#include "mlir/Target/LLVMIR/TypeToLLVM.h"
#include "llvm/ADT/TypeSwitch.h"
+#include "llvm/IR/Attributes.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/Support/ErrorHandling.h"
-#include <string>
-#include <type_traits>
#include "triton/Conversion/TritonGPUToLLVM/Utility.h"
#include "t... | ```suggestion
for (auto [idx, attrList] : llvm::enumerate(attrs.getParamAttributes())) {
``` |
intel-xpu-backend-for-triton | github_2023 | python | 1,211 | intel | Dewei-Wang-sh | @@ -177,12 +176,12 @@ def matmul_kernel_with_block_pointers(
a = tl.load(a_block_ptr, boundary_check=(0, 1))
b = tl.load(b_block_ptr, boundary_check=(0, 1))
# We accumulate along the K dimension.
- accumulator += tl.dot(a, b)
+ accumulator += tl.dot(a, b, out_dtype=accu_dtype)
... | caution: normally we may want accumulator to be fp32, and c to be the same with a/b type like bf16/fp16/tf32 |
intel-xpu-backend-for-triton | github_2023 | python | 1,211 | intel | Dewei-Wang-sh | @@ -243,7 +245,12 @@ def matmul(a, b, res_dtype):
# Note: the torch.matmul and Triton implementations uses different
# algorithms so we need to adjust tolerance.
- rtol = 1e-2 if dtype == torch.bfloat16 else 1e-3
+ rtol = 1e-3
+ if dtype == torch.bfloat16:
+ rtol = 1e-2
+ if res_dtype == ... | how about acc use f32 and then use f16 to store back? |
intel-xpu-backend-for-triton | github_2023 | python | 1,211 | intel | whitneywhtsang | @@ -223,10 +222,16 @@ def matmul(a, b, res_dtype):
torch.manual_seed(0)
for dtype, res_dtype in [(torch.float16, torch.float32), (torch.bfloat16, torch.float32), (torch.int8, torch.int32),
- (torch.float32, torch.float32)]:
+ (torch.float32, torch.float32), (torch.flo... | Why are we generating random integer values for float16? |
intel-xpu-backend-for-triton | github_2023 | others | 1,242 | intel | FMarno | @@ -17,7 +17,7 @@ include "intel/include/Dialect/TritonGEN/IR/TritonGENDialect.td"
include "intel/include/Dialect/TritonGEN/IR/TritonGENAttrDefs.td"
include "mlir/IR/OpBase.td"
include "mlir/IR/EnumAttr.td"
-include "mlir/Dialect/LLVMIR/LLVMOpBase.td"
+include "mlir/Dialect/LLVMIR/LLVMTypes.td" | you say `LLVMTypes.td` is the narrower file, but it includes `LLVMOpBase.td` itself
https://github.com/llvm/llvm-project/blob/d999ce0302f06d250f6d496b56a5a5f2dc331e61/mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.td#L12 |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,200 | intel | victor-eds | @@ -513,6 +513,58 @@ void LayoutPropagation::rewriteRegion(Region ®ion) {
} else if (auto assertOp = dyn_cast<AssertOp>(&op)) {
rewriteAssertOp(assertOp);
} else {
+ if (auto storeOp = dyn_cast<StoreOp>(&op)) {
+ // If storeOp is a pointer to a tensor, we try to found out if th... | ```suggestion
// If storeOp is a pointer to a tensor, we try to find out if the
// data has initially a DPAS encoding and forward it to the StoreOp
// to enable 2D block store.
```
NIT |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,200 | intel | victor-eds | @@ -513,6 +513,58 @@ void LayoutPropagation::rewriteRegion(Region ®ion) {
} else if (auto assertOp = dyn_cast<AssertOp>(&op)) {
rewriteAssertOp(assertOp);
} else {
+ if (auto storeOp = dyn_cast<StoreOp>(&op)) {
+ // If storeOp is a pointer to a tensor, we try to found out if th... | ```suggestion
auto convertOp = storeOp.getValue().getDefiningOp<ConvertLayoutOp>();
```
NIT |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,200 | intel | victor-eds | @@ -513,6 +513,58 @@ void LayoutPropagation::rewriteRegion(Region ®ion) {
} else if (auto assertOp = dyn_cast<AssertOp>(&op)) {
rewriteAssertOp(assertOp);
} else {
+ if (auto storeOp = dyn_cast<StoreOp>(&op)) {
+ // If storeOp is a pointer to a tensor, we try to found out if th... | ```suggestion
auto makeTensorPtrOp = storeOp->getOperand(0).getDefiningOp<MakeTensorPtrOp>();
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,200 | intel | victor-eds | @@ -513,6 +513,58 @@ void LayoutPropagation::rewriteRegion(Region ®ion) {
} else if (auto assertOp = dyn_cast<AssertOp>(&op)) {
rewriteAssertOp(assertOp);
} else {
+ if (auto storeOp = dyn_cast<StoreOp>(&op)) {
+ // If storeOp is a pointer to a tensor, we try to found out if th... | ```suggestion
RankedTensorType convertOpSrcType = convertOp.getSrc().getType();
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,200 | intel | victor-eds | @@ -513,6 +513,58 @@ void LayoutPropagation::rewriteRegion(Region ®ion) {
} else if (auto assertOp = dyn_cast<AssertOp>(&op)) {
rewriteAssertOp(assertOp);
} else {
+ if (auto storeOp = dyn_cast<StoreOp>(&op)) {
+ // If storeOp is a pointer to a tensor, we try to found out if th... | Would this work if `converOp` has more users? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,200 | intel | victor-eds | @@ -513,6 +513,60 @@ void LayoutPropagation::rewriteRegion(Region ®ion) {
} else if (auto assertOp = dyn_cast<AssertOp>(&op)) {
rewriteAssertOp(assertOp);
} else {
+ if (auto storeOp = dyn_cast<StoreOp>(&op)) {
+ // If storeOp is a pointer to a tensor, we try to find out if the... | If `makeTensorPtrOp` is used by a different operation, this would lead to errors. Can we:
1. Create a new `MakeTensorPtrOp` with new type
2. Replace `storeOp` argument with newly created op
3. Remove `makeTensorPtrOp` if it's no longer used |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,200 | intel | whitneywhtsang | @@ -513,6 +513,58 @@ void LayoutPropagation::rewriteRegion(Region ®ion) {
} else if (auto assertOp = dyn_cast<AssertOp>(&op)) {
rewriteAssertOp(assertOp);
} else {
+ if (auto storeOp = dyn_cast<StoreOp>(&op)) { | Can we create a rewriteStoreOp function? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,200 | intel | whitneywhtsang | @@ -513,6 +513,58 @@ void LayoutPropagation::rewriteRegion(Region ®ion) {
} else if (auto assertOp = dyn_cast<AssertOp>(&op)) {
rewriteAssertOp(assertOp);
} else {
+ if (auto storeOp = dyn_cast<StoreOp>(&op)) {
+ // If storeOp is a pointer to a tensor, we try to find out if the... | Once rewriteStoreOp function is created, can we early return instead of created big code nesting? https://llvm.org/docs/CodingStandards.html#use-early-exits-and-continue-to-simplify-code |
intel-xpu-backend-for-triton | github_2023 | others | 1,200 | intel | etiotto | @@ -0,0 +1,63 @@
+// RUN: triton-opt %s -split-input-file -tritonintelgpu-remove-layout-conversions 2>&1 | FileCheck %s | We have a lit test `backward_combine_dpas_dot_layout.mlir`, can you add this test in that file ?
Or even better enhance the existing test in that file. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,200 | intel | etiotto | @@ -785,6 +793,66 @@ void LayoutPropagation::rewriteAssertOp(AssertOp assertOp) {
assertOp->setOperand(0, newOperand);
}
+bool LayoutPropagation::rewriteStoreOp(StoreOp storeOp) {
+ // If storeOp is a pointer to a tensor, we try to find out if the
+ // data has initially a DPAS encoding and forward it to the St... | [nit]: Use Value not auto here |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,200 | intel | etiotto | @@ -785,6 +793,66 @@ void LayoutPropagation::rewriteAssertOp(AssertOp assertOp) {
assertOp->setOperand(0, newOperand);
}
+bool LayoutPropagation::rewriteStoreOp(StoreOp storeOp) {
+ // If storeOp is a pointer to a tensor, we try to find out if the
+ // data has initially a DPAS encoding and forward it to the St... | Use early exit here:
```
if (isa<ttgi::DpasEncodingAttr>(tensorType.getEncoding()))
return false;
```
|
intel-xpu-backend-for-triton | github_2023 | others | 1,200 | intel | whitneywhtsang | @@ -72,3 +73,151 @@ module attributes {"triton_gpu.num-warps" = 4 : i32, "triton_gpu.threads-per-war
tt.return
}
}
+
+
+// -----
+
+// COM: Case 1: | ```suggestion
// COM: Case 2:
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,223 | intel | victor-eds | @@ -40,6 +41,13 @@ enum TritonGENMemorySpace {
kGeneric = 4 // OpenCL Generic memory
};
+/// Get the subgroup size from the target.
+inline int getSubgroupSize(Operation *op) {
+ spirv::TargetEnvAttr attr = spirv::lookupTargetEnv(op);
+ assert(attr && "Expecting valid target env attribute");
+ return ... | Would failing the conversion make sense instead of asserting here? Also, can we move this to a `.cpp` file to make this header smaller? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,223 | intel | victor-eds | @@ -75,7 +75,26 @@ template <typename Op> static LogicalResult verifyInput(Op op) {
//===----------------------------------------------------------------------===//
LogicalResult TritonGEN::SubGroupReduceOp::verify() {
- // TODO: Add verification for SubGroupReduceOp.
+ Type ty = getValue().getType();
+ switch (... | Can we list the rest of cases instead of having `default` here? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,223 | intel | victor-eds | @@ -75,7 +76,40 @@ template <typename Op> static LogicalResult verifyInput(Op op) {
//===----------------------------------------------------------------------===//
LogicalResult TritonGEN::SubGroupReduceOp::verify() {
- // TODO: Add verification for SubGroupReduceOp.
+ spirv::TargetEnvAttr attr = spirv::lookupTa... | ```suggestion
if (!isa<IntegerType>(ty))
return this->emitOpError("expecting integer type for integer reduction");
break;
``` |
intel-xpu-backend-for-triton | github_2023 | others | 1,230 | intel | whitneywhtsang | @@ -1,28 +1,19 @@
-<div align="center">
- <img src="https://cdn.openai.com/triton/assets/triton-logo.png" alt="Triton logo" width="88" height="100">
-</div>
-
[](https://github.com/int... | ```suggestion
This is the development repository of Intel® XPU Backend for Triton\*, a new [Triton](https://github.com/triton-lang/triton/) backend for Intel GPUs. Intel® XPU Backend for Triton\* is a out of tree backend module for [Triton](https://github.com/triton-lang/triton/blob/main/CONTRIBUTING.md) used to provi... |
intel-xpu-backend-for-triton | github_2023 | others | 1,230 | intel | whitneywhtsang | @@ -176,12 +165,121 @@ For detailed instructions on how to debug Triton's frontend, please refer to thi
- `MLIR_ENABLE_TIMING` dumps the timing information for each MLIR pass.
- `LLVM_ENABLE_TIMING` dumps the timing information for each LLVM pass.
+# Usage Guide
+
+## Code Modifications
+Intel® XPU Backend for Trit... | ```suggestion
This example is a modified version of [Vector Add](https://triton-lang.org/main/getting-started/tutorials/01-vector-add.html#vector-addition) triton kernel. Please refer to [Vector Add](https://triton-lang.org/main/getting-started/tutorials/01-vector-add.html#vector-addition) for detailed comments and il... |
intel-xpu-backend-for-triton | github_2023 | python | 1,202 | intel | victor-eds | @@ -0,0 +1,68 @@
+import torch
+import intel_extension_for_pytorch
+
+import triton
+import triton.language as tl
+
+
+@triton.jit
+def float_trunc_kernel(
+ x_ptr,
+ n_elements,
+ BLOCK_SIZE: tl.constexpr,
+ target_type: tl.constexpr,
+):
+ pid = tl.program_id(axis=0)
+ block_start = pid * BLOCK_SIZE... | ```suggestion
as_f32 += 1 # plus one ensures that there are no redundant conversions that can be removed
``` |
intel-xpu-backend-for-triton | github_2023 | others | 1,202 | intel | whitneywhtsang | @@ -186,6 +203,9 @@ run_tutorial_tests() {
}
test_triton() {
+ if [ "$TEST_MICRO_BENCHMARKS" = true ]; then | [nit] Can we run micro benchmarks before or after tutorial?
unit tests are fast, and should be run first, then ensure the compiler is in ok sharp. |
intel-xpu-backend-for-triton | github_2023 | others | 1,202 | intel | whitneywhtsang | @@ -49,7 +54,7 @@ for arg in "$@"; do
shift
;;
--help)
- echo "Example usage: ./test-triton.sh [--core | --tutorial | --unit | --venv | --reports | --warning-reports | --ignore-errors]"
+ echo "Example usage: ./test-triton.sh [--core | --tutorial | --unit | --venv | --reports | --warning-re... | [nit] can we have `--microbench` added with other options that select the test kind? |
intel-xpu-backend-for-triton | github_2023 | python | 1,225 | intel | FMarno | @@ -99,23 +99,23 @@
@triton.autotune(
configs=[
- triton.Config({'BLOCK_SIZE_M': 128, 'BLOCK_SIZE_N': 256, 'BLOCK_SIZE_K': 64, 'GROUP_SIZE_M': 4}, num_stages=4,
+ triton.Config({'BLOCK_SIZE_M': 128, 'BLOCK_SIZE_N': 256, 'BLOCK_SIZE_K': 64, 'GROUP_SIZE_M': 4}, num_stages=2, | if there point is to autotune `num_stages` maybe there should be a variety of options for `num_stages`? |
intel-xpu-backend-for-triton | github_2023 | python | 1,225 | intel | etiotto | @@ -99,23 +99,23 @@
@triton.autotune(
configs=[
- triton.Config({'BLOCK_SIZE_M': 128, 'BLOCK_SIZE_N': 256, 'BLOCK_SIZE_K': 64, 'GROUP_SIZE_M': 4}, num_stages=4,
+ triton.Config({'BLOCK_SIZE_M': 128, 'BLOCK_SIZE_N': 256, 'BLOCK_SIZE_K': 64, 'GROUP_SIZE_M': 4}, num_stages=2,
n... | What is the reason for changing num_stages to 2 for all the configurations? |
intel-xpu-backend-for-triton | github_2023 | python | 1,225 | intel | etiotto | @@ -79,7 +79,7 @@ def make_ttgir(mod, metadata, opt, device_arch):
# FIXME: Use a better way to check if prefetch instructions are supported once available.
# Prefetch instruction is not available in older drivers.
if Version(metadata["target"].arch['driver_version']) > Version("1... | what does False mean ? Can you use a descriptive name ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,228 | intel | victor-eds | @@ -278,11 +278,18 @@ struct DotOpMFMAConversionHelper {
int kpack = kWidth / kBase;
SmallVector<Value> results;
auto vecTy = vec_ty(type, kBase);
+ if (type.isBF16())
+ vecTy = vec_ty(i16_ty, kBase);
for (int k = 0; k < kpack; ++k) {
Value vec = undef(vecTy);
for (int elemId =... | What's with this comment? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,228 | intel | victor-eds | @@ -975,13 +975,16 @@ struct TritonSubGroupShuffleLowering
if (!orig_type.isInteger())
val = bitcast(val, int_ty(bits));
val = zext(i8_ty, val);
+ } else if (isa<BFloat16Type>(orig_type)) {
+ val = bitcast(val, i16_ty);
}
Value result = createSubGroupShuffle(rewriter, val, mask,... | ```suggestion
} else if (isa<BFloat16Type>(orig_type)) {
result = bitcast(result, orig_type);
}
``` |
intel-xpu-backend-for-triton | github_2023 | others | 1,087 | intel | etiotto | @@ -16,3 +16,33 @@ llvm.func spir_kernelcc @test_reqd_work_group_size() attributes {triton_gen.reqd
// CHECK-DAG: ![[REQD_SUB_GROUP_SIZE]] = !{i64 32}
// CHECK-DAG: ![[MAX_WORK_GROUP_SIZE]] = !{i64 128, i64 1, i64 1}
// CHECK-DAG: ![[REQD_WORK_GROUP_SIZE]] = !{i64 128, i64 1, i64 2}
+
+// -----
+
+llvm.func @foo(%ar... | Yes, we only need to place the attribute on a call operation but I like the idea.
Regarding the call, it should have only one cache control attribute, depending on whether the call is a load or store operation.
Same observation for llvm.load: only the cache control attribute pertaining to loads make sense (similar ... |
intel-xpu-backend-for-triton | github_2023 | others | 1,087 | intel | etiotto | @@ -1,5 +1,21 @@
// RUN: triton-opt -split-input-file -verify-diagnostics %s
+llvm.func @triton_gen.duplicated_cache_controls(%arg0: !llvm.ptr) {
+ // expected-error @+1 {{'triton_gen.decoration_cache_controls' cannot specify more than one cache control decoration of the same nature for the same cache level}}
+ %0... | In addition, we should diagnose this code as invalid because a store cache control is illegal on a load operation. |
intel-xpu-backend-for-triton | github_2023 | others | 1,214 | intel | victor-eds | @@ -237,6 +237,30 @@ def TritonGEN_NamedBarrierWaitOp : TritonGEN_Op<"named_barrier_wait">,
def IntegerOrFloatType : AnyTypeOf<[AnyInteger, AnyFloat]>;
+def TritonGEN_SubGroupReduceOp : TritonGEN_Op<"sub_group_reduce", [
+ TypesMatchWith<"result and value have the same type",
+ "res", "val... | ```suggestion
AllTypesMatch<["res", "value"]>]>,
```
`AllTypesMatch` is used for simple `==` comparison between types. `TypesMatchWith` receive a third argument so that a function can be applied to the types before comparison. As what we want is `==` comparison (`"$_self"` gets you just that), we can use the... |
intel-xpu-backend-for-triton | github_2023 | others | 1,214 | intel | victor-eds | @@ -237,6 +237,30 @@ def TritonGEN_NamedBarrierWaitOp : TritonGEN_Op<"named_barrier_wait">,
def IntegerOrFloatType : AnyTypeOf<[AnyInteger, AnyFloat]>;
+def TritonGEN_SubGroupReduceOp : TritonGEN_Op<"sub_group_reduce", [
+ TypesMatchWith<"result and value have the same type",
+ "res", "val... | ```suggestion
let description = [{
```
`description` is the field used to provide operations descriptions |
intel-xpu-backend-for-triton | github_2023 | others | 1,214 | intel | victor-eds | @@ -237,6 +237,30 @@ def TritonGEN_NamedBarrierWaitOp : TritonGEN_Op<"named_barrier_wait">,
def IntegerOrFloatType : AnyTypeOf<[AnyInteger, AnyFloat]>;
+def TritonGEN_SubGroupReduceOp : TritonGEN_Op<"sub_group_reduce", [
+ TypesMatchWith<"result and value have the same type",
+ "res", "val... | ```suggestion
The `triton_gen.sub_group_reduce` operation is invoked by all work items in a
``` |
intel-xpu-backend-for-triton | github_2023 | others | 1,214 | intel | victor-eds | @@ -237,6 +237,30 @@ def TritonGEN_NamedBarrierWaitOp : TritonGEN_Op<"named_barrier_wait">,
def IntegerOrFloatType : AnyTypeOf<[AnyInteger, AnyFloat]>;
+def TritonGEN_SubGroupReduceOp : TritonGEN_Op<"sub_group_reduce", [
+ TypesMatchWith<"result and value have the same type",
+ "res", "val... | ```suggestion
$kind $value `,` $size attr-dict `:` type($value)
```
Can we avoid `{...}`? I think it's more difficult to parse right next to the `attr-dict`. Also, `type($value) = type($res)`, we can just specify one. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,214 | intel | victor-eds | @@ -70,6 +70,15 @@ template <typename Op> static LogicalResult verifyInput(Op op) {
return success();
}
+//===----------------------------------------------------------------------===//
+// gen.sub_group_reduce
+//===----------------------------------------------------------------------===//
+
+LogicalResult Trit... | Should we then not generate this for now and add that comment in TableGen? |
intel-xpu-backend-for-triton | github_2023 | others | 1,214 | intel | victor-eds | @@ -16,7 +16,7 @@ def ConvertTritonGENToLLVM : Pass<"convert-tritongen-to-llvm"> {
let description = [{
This pass converts the TritonGEN dialect operations to LLVM dialect operations.
}];
- let dependentDialects = ["mlir::LLVM::LLVMDialect"];
+ let dependentDialects = ["mlir::LLVM::LLVMDialect", "mlir::spi... | I don't think we're creating SPIR-V operations, types or attributes, so SPIR-V would not be a dependent dialect. If we used `lookupTargetEnvOrGetDefault` instead of `lookupTargetEnv`, we would be creating a SPIR-V attribute, so we'd need this here, but we aren't. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,214 | intel | victor-eds | @@ -903,6 +912,52 @@ struct TritonGENNamedBarrierWaitLowering
}
};
+struct TritonSubGroupReduceLowering
+ : public ConvertOpToLLVMPattern<TritonGEN::SubGroupReduceOp> {
+ using ConvertOpToLLVMPattern<
+ TritonGEN::SubGroupReduceOp>::ConvertOpToLLVMPattern;
+
+ LogicalResult
+ matchAndRewrite(TritonGEN:... | ```suggestion
auto moduleOp = op->getParentOfType<ModuleOp>();
```
Would this work? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,214 | intel | victor-eds | @@ -903,6 +912,52 @@ struct TritonGENNamedBarrierWaitLowering
}
};
+struct TritonSubGroupReduceLowering
+ : public ConvertOpToLLVMPattern<TritonGEN::SubGroupReduceOp> {
+ using ConvertOpToLLVMPattern<
+ TritonGEN::SubGroupReduceOp>::ConvertOpToLLVMPattern;
+
+ LogicalResult
+ matchAndRewrite(TritonGEN:... | Can we set the call operation calling convention too? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,214 | intel | victor-eds | @@ -903,6 +912,52 @@ struct TritonGENNamedBarrierWaitLowering
}
};
+struct TritonSubGroupReduceLowering
+ : public ConvertOpToLLVMPattern<TritonGEN::SubGroupReduceOp> {
+ using ConvertOpToLLVMPattern<
+ TritonGEN::SubGroupReduceOp>::ConvertOpToLLVMPattern;
+
+ LogicalResult
+ matchAndRewrite(TritonGEN:... | I'm not sure I like the idea of creating an LLVM context and depending on translation in a conversion pass. I'd rather manually build `funcName`. I'm assuming the name to be as simple as: `llvm.genx.GenISA.[WaveAll|WaveClustered].[f16|f32|f64|i8|i16|i32|i64]`, right? I think a small function with a bit of logic would b... |
intel-xpu-backend-for-triton | github_2023 | others | 1,214 | intel | victor-eds | @@ -101,6 +101,151 @@ llvm.func @triton_gen.named_barrier(%barrier_id : i32, %thread_group_count : i32
// -----
+module attributes {
+ spirv.target_env = #spirv.target_env<#spirv.vce<v1.4, [Kernel, Addresses, GroupNonUniformShuffle, Int64], []>, #spirv.resource_limits<subgroup_size = 32>> | Can we use `triton_gpu.threads-per-warp` instead? This would avoid adding a dependency with SPIR-V dialect. |
intel-xpu-backend-for-triton | github_2023 | cpp | 992 | intel | whitneywhtsang | @@ -1033,7 +1033,9 @@ inline SmallVector<Value> emitCTAOffsetForLayout(Location loc,
triton::gpu::getShapePerCTA(CTASplitNum, shape);
// Delinearize clusterCTAId
- Value clusterCTAId = getClusterCTAId(rewriter, loc);
+ unsigned numCTAs = product<unsigned>(CTAsPerCGA);
+ Value clusterCTAId =
+ numCTA... | Why not keep the intel version of getClusterCTAId which return `i32_val(0)`? |
intel-xpu-backend-for-triton | github_2023 | cpp | 992 | intel | victor-eds | @@ -0,0 +1,225 @@
+//===- Utility.h - Code generation utilities ------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | I'd avoid that in a header file |
intel-xpu-backend-for-triton | github_2023 | cpp | 992 | intel | victor-eds | @@ -0,0 +1,225 @@
+//===- Utility.h - Code generation utilities ------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | We should revisit namespaces used here. `mlir::LLVM` corresponds to the LLVM dialect. Should we use `mlir::triton::intel` instead? |
intel-xpu-backend-for-triton | github_2023 | cpp | 992 | intel | victor-eds | @@ -0,0 +1,225 @@
+//===- Utility.h - Code generation utilities ------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | Use markdown for formatting |
intel-xpu-backend-for-triton | github_2023 | cpp | 992 | intel | victor-eds | @@ -0,0 +1,225 @@
+//===- Utility.h - Code generation utilities ------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | ```suggestion
assert(llvm::equal(ops, thenOps, ...) && "type mismatch found");
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 992 | intel | victor-eds | @@ -0,0 +1,225 @@
+//===- Utility.h - Code generation utilities ------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | ```suggestion
template <typename F>
Block &createPredicatedBlock(RewriterBase &rewriter, Location loc,
Value cond, ValueRange ops,
F thenOpsFn) {
```
Can we also have more specific names for `ops` and `thenOpsFn`? Maybe `branchBlockArgs` and `endBlockArg... |
intel-xpu-backend-for-triton | github_2023 | cpp | 992 | intel | victor-eds | @@ -0,0 +1,225 @@
+//===- Utility.h - Code generation utilities ------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | ```suggestion
template <typename F>
Block &createPredicatedBlock(RewriterBase &rewriter, Location loc,
Value cond, ThenOpsFn thenOpsFn) {
return createPredicatedBlock(rewriter, loc, cond, {}, thenOpsFn);
}
```
Same for argument names |
intel-xpu-backend-for-triton | github_2023 | cpp | 992 | intel | victor-eds | @@ -0,0 +1,225 @@
+//===- Utility.h - Code generation utilities ------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | ```suggestion
Value storeShared(RewriterBase &rewriter, Location loc, Value ptr,
Value val, Value pred);
Value loadShared(RewriterBase &rewriter, Location loc, Value ptr,
Type elemTy, Value pred);
Value shuffleXor(RewriterBase &rewriter, Location loc, Value val,
... |
intel-xpu-backend-for-triton | github_2023 | cpp | 992 | intel | victor-eds | @@ -0,0 +1,225 @@
+//===- Utility.h - Code generation utilities ------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | Can we move this to a `.cpp` file? |
intel-xpu-backend-for-triton | github_2023 | cpp | 992 | intel | victor-eds | @@ -0,0 +1,225 @@
+//===- Utility.h - Code generation utilities ------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | ```suggestion
if (mod->getAttrOfType<IntegerAttr>("triton_gpu.shared").getInt() == 0)
return rewriter.create<LLVM::PoisonOp>(funcOp.getLoc(), ptrTy);
```
Do we wanna emit a warning or similar on this case? Will we even generate useful code in this case? Would the input module be illformed in this case? |
intel-xpu-backend-for-triton | github_2023 | cpp | 992 | intel | victor-eds | @@ -0,0 +1,225 @@
+//===- Utility.h - Code generation utilities ------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | Can we move this to a .cpp file? |
intel-xpu-backend-for-triton | github_2023 | cpp | 992 | intel | victor-eds | @@ -0,0 +1,225 @@
+//===- Utility.h - Code generation utilities ------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | Can we replace `3` with `TritonGEN::TritonGENMemorySpace::kWorkgroup`? (I assume that's the one) |
intel-xpu-backend-for-triton | github_2023 | cpp | 992 | intel | victor-eds | @@ -0,0 +1,225 @@
+//===- Utility.h - Code generation utilities ------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | Question: Is `template` needed here? |
intel-xpu-backend-for-triton | github_2023 | cpp | 992 | intel | victor-eds | @@ -0,0 +1,225 @@
+//===- Utility.h - Code generation utilities ------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | ```suggestion
uint64_t offset = op->getAttrOfType<IntegerAttr>("allocation.offset").getUInt();
```
Also, `.cast<...>()` is deprecated ([see](https://mlir.llvm.org/deprecation/)). |
intel-xpu-backend-for-triton | github_2023 | cpp | 992 | intel | victor-eds | @@ -0,0 +1,225 @@
+//===- Utility.h - Code generation utilities ------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | Can we move to .cpp file? (same for other functions defined here) |
intel-xpu-backend-for-triton | github_2023 | cpp | 992 | intel | victor-eds | @@ -0,0 +1,225 @@
+//===- Utility.h - Code generation utilities ------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | ```suggestion
DpasEncodingAttr dpasLayout,
```
Same for other `Attribute` args |
intel-xpu-backend-for-triton | github_2023 | others | 992 | intel | victor-eds | @@ -526,6 +526,18 @@ For the Threads Per Warp and Values Per Thread level, the linear id distribution
InterfaceMethod<"Gets the number of contiguous elements per thread.",
"SmallVector<unsigned>",
"getContigPerThread">,
+
+ InterfaceMethod<"emit base index",
+ ... | Sidenote: you can provide a default implementation changing this to:
```suggestion
InterfaceMethod<"emit base index",
"SmallVector<Value>",
"emitBaseIndexWithinCTAForLayout",
(ins "Location":$loc,
"RewriterBase&":$rewriter,... |
intel-xpu-backend-for-triton | github_2023 | python | 1,207 | intel | whitneywhtsang | @@ -42,66 +43,88 @@ def naive_softmax(x):
@triton.autotune(
configs=[
- triton.Config({}, num_warps=32),
- triton.Config({}, num_warps=8),
- triton.Config({}, num_warps=4),
- triton.Config({}, num_warps=32),
- triton.Config({}, num_warps=8),
- triton.Config({}, num_warp... | ```suggestion
device = torch.xpu.current_device()
properties = driver.active.utils.get_device_properties(device)
MAX_WORK_GROUP_SIZE = properties["max_work_group_size"]
``` |
intel-xpu-backend-for-triton | github_2023 | python | 1,207 | intel | whitneywhtsang | @@ -42,66 +43,88 @@ def naive_softmax(x):
@triton.autotune(
configs=[
- triton.Config({}, num_warps=32),
- triton.Config({}, num_warps=8),
- triton.Config({}, num_warps=4),
- triton.Config({}, num_warps=32),
- triton.Config({}, num_warps=8),
- triton.Config({}, num_warp... | ```suggestion
"XeTLA",
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,155 | intel | whitneywhtsang | @@ -123,8 +123,13 @@ class LoadStorePrefetchOpConversion
unsigned dataSize = tensorType.getElementType().getIntOrFloatBitWidth();
unsigned blockWidth = tensorType.getShape()[1];
assert(blockWidth == 16 || blockWidth == 32 && "only support 16/32 block");
- unsigned vBlks = blockWidth == 32 ? 2 : 1;
- ... | For 8-bit data, vBlks == 2 is allowed. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,155 | intel | FMarno | @@ -593,7 +611,10 @@ void MatchTargetSizePass::transformDotOp(tt::DotOp dot) {
int64_t m = aShape[0];
int64_t n = bShape[1];
int64_t k = aShape[1];
- const auto &dotShape = nativeSizes.getDotShape();
+ auto dotShape = nativeSizes.getDotShape();
+ if (aType.getElementTypeBitWidth() == 8)
+ dotShape.k *= 2... | what is this bit about? |
intel-xpu-backend-for-triton | github_2023 | python | 1,155 | intel | etiotto | @@ -239,3 +243,21 @@ def matmul(a, b):
print("✅ Triton and Torch match")
else:
exit("❌ Triton and Torch differ")
+
+# Integer data
+for dtype in [torch.int8]: | I would prefer to extend the current implementation to add support for int8 (no duplication of code) |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,155 | intel | etiotto | @@ -121,11 +121,19 @@ class LoadStorePrefetchOpConversion
"only support 1d/2d load/store/prefetch for now");
unsigned dataSize = tensorType.getElementType().getIntOrFloatBitWidth();
- unsigned blockWidth = tensorType.getShape()[1];
- assert(blockWidth == 16 || blockWidth == 32 && "only support ... | add a msg to the assert |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,155 | intel | whitneywhtsang | @@ -121,11 +121,19 @@ class LoadStorePrefetchOpConversion
"only support 1d/2d load/store/prefetch for now");
unsigned dataSize = tensorType.getElementType().getIntOrFloatBitWidth();
- unsigned blockWidth = tensorType.getShape()[1];
- assert(blockWidth == 16 || blockWidth == 32 && "only support ... | should we use ceil to avoid getting zero?
```suggestion
vBlks = ceil(blockWidth, blockWidthUnit);
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,155 | intel | whitneywhtsang | @@ -121,11 +121,19 @@ class LoadStorePrefetchOpConversion
"only support 1d/2d load/store/prefetch for now");
unsigned dataSize = tensorType.getElementType().getIntOrFloatBitWidth();
- unsigned blockWidth = tensorType.getShape()[1];
- assert(blockWidth == 16 || blockWidth == 32 && "only support ... | should we add back the assert of `assert(blockWidth == 16 || blockWidth == 32...)` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,155 | intel | etiotto | @@ -206,6 +214,9 @@ class DotOpConversion : public ConvertTritonGPUOpToLLVMPattern<DotOp> {
return TritonGEN::PrecisionType::FP16;
else if (type == rewriter.getTF32Type())
return TritonGEN::PrecisionType::TF32;
+ else if (type == i8_ty)
+ // TODO: Assuming signed data; is that ok? | i8_ty is a signless data type. Using `TritonGEN::PrecisionType::S8` should be fine. You can remove the TODO. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,155 | intel | whitneywhtsang | @@ -206,6 +214,9 @@ class DotOpConversion : public ConvertTritonGPUOpToLLVMPattern<DotOp> {
return TritonGEN::PrecisionType::FP16;
else if (type == rewriter.getTF32Type())
return TritonGEN::PrecisionType::TF32;
+ else if (type == i8_ty)
+ // TODO: Assuming signed data; is that ok?
+... | ```suggestion
else if (type.isInteger(8)) {
if (type.cast<IntegerType>().isUnsigned())
return TritonGEN::PrecisionType::U8;
else
return TritonGEN::PrecisionType::S8;
}
``` |
intel-xpu-backend-for-triton | github_2023 | python | 1,155 | intel | Dewei-Wang-sh | @@ -224,11 +224,15 @@ def matmul(a, b):
# Still we can test our matrix multiplication with block pointers against a native torch implementation (i.e., cuBLAS).
torch.manual_seed(0)
+
+# Floating-point data
for dtype in [torch.float16, torch.bfloat16]:
a = torch.randn((512, 512), device='xpu', dtype=dtype)
... | do you have time to make the res_dtype the same as a/b_type after this pr? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,155 | intel | Dewei-Wang-sh | @@ -121,11 +121,19 @@ class LoadStorePrefetchOpConversion
"only support 1d/2d load/store/prefetch for now");
unsigned dataSize = tensorType.getElementType().getIntOrFloatBitWidth();
- unsigned blockWidth = tensorType.getShape()[1];
- assert(blockWidth == 16 || blockWidth == 32 && "only support ... | interesting that width unit is related to the height |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,155 | intel | whitneywhtsang | @@ -121,11 +121,22 @@ class LoadStorePrefetchOpConversion
"only support 1d/2d load/store/prefetch for now");
unsigned dataSize = tensorType.getElementType().getIntOrFloatBitWidth();
- unsigned blockWidth = tensorType.getShape()[1];
- assert(blockWidth == 16 || blockWidth == 32 && "only support ... | what's the difference between `llvm::divideCeil` and https://github.com/intel/intel-xpu-backend-for-triton/blob/llvm-target/include/triton/Dialect/Triton/IR/Utility.h#L30? the second is used in many places in Triton. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,155 | intel | whitneywhtsang | @@ -121,11 +121,22 @@ class LoadStorePrefetchOpConversion
"only support 1d/2d load/store/prefetch for now");
unsigned dataSize = tensorType.getElementType().getIntOrFloatBitWidth();
- unsigned blockWidth = tensorType.getShape()[1];
- assert(blockWidth == 16 || blockWidth == 32 && "only support ... | Can we use https://github.com/intel/intel-xpu-backend-for-triton/blob/llvm-target/include/triton/Dialect/Triton/IR/Utility.h#L30 here too? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,155 | intel | etiotto | @@ -82,16 +82,18 @@ class TargetArchNativeSizes {
};
TargetArchNativeSizes() = default;
- TargetArchNativeSizes(DotShape dotShape, unsigned loadStoreSize)
- : dotShape(dotShape), loadStoreSize(loadStoreSize) {}
- void setDotShape(DotShape shape) { dotShape = shape; }
+ void setDotShape(unsigned bitWid... | Document the map. The key is the bitwidth of .... |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,155 | intel | etiotto | @@ -453,14 +456,16 @@ MatchTargetSizePass::getSubOpSize(RankedTensorType type) const {
// Dot operation.
if (dotAttrs.count(layout)) {
- const auto &dotShape = nativeSizes.getDotShape();
- SmallVector<int64_t> nativeDotSize{dotShape.m, dotShape.n};
+ auto dotShape = nativeSizes.getDotShape(type.getElem... | auto -> DotShape. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,155 | intel | FMarno | @@ -453,14 +456,16 @@ MatchTargetSizePass::getSubOpSize(RankedTensorType type) const {
// Dot operation.
if (dotAttrs.count(layout)) {
- const auto &dotShape = nativeSizes.getDotShape();
- SmallVector<int64_t> nativeDotSize{dotShape.m, dotShape.n};
+ auto dotShape = nativeSizes.getDotShape(type.getElem... | since you always do the assert, maybe move it into the `getDotShape` method. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,155 | intel | FMarno | @@ -470,14 +475,31 @@ MatchTargetSizePass::getSubOpSize(RankedTensorType type) const {
subSize[0] = std::min(max, shape[0]);
} break;
case 2: {
- // 32 = 2 * 16(subgroupSize) which is for large load/store
- int64_t colLimit =
- (isa<ttgi::WarpEncodingAttr, ttg::DotOperandEncodingAttr>(layout)) ?... | I would suggest splitting the nested switch into another function. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,155 | intel | etiotto | @@ -81,23 +81,49 @@ class TargetArchNativeSizes {
unsigned k = 0;
};
+ struct BlockMemShape {
+ BlockMemShape() = default;
+ BlockMemShape(unsigned rowsA, unsigned columnsA, unsigned rowsB,
+ unsigned columnsB)
+ : rowsA(rowsA), columnsA(columnsA), rowsB(rowsB), columnsB(columns... | [nit]: rowsB is not explicitly compared to zero like the rest. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,155 | intel | etiotto | @@ -394,11 +420,21 @@ class ScfPattern : public OpRewritePattern<scf::ForOp> {
void MatchTargetSizePass::initNativeOperationSizes() {
// FIXME: sets the target dot shape natively supported by the target
// architecture using the target architecture information when available.
- // These value works for PVC.
- ... | [Suggestion]: remove the comments and the clang-format off. The `setDotShape` member function is in this file so is easy to find out what is the meaning of the variolous arguments. |
intel-xpu-backend-for-triton | github_2023 | others | 1,155 | intel | etiotto | @@ -167,3 +167,57 @@ tt.func public @simplify_scf_for(%arg0: tensor<16x8xf16>, %arg1: tensor<16x8xf16
}
tt.return
}
+
+// -----
+
+// COM: Test transformation for int8 datatype
+
+// CHECK-LABEL: @matmul_kernel_with_block_pointers
+#warp = #triton_intel_gpu.warp<{sizePerThread = [8, 32], threadsPerWarp = [1, 1],... | The CHECK makes it look that the 2 block pointers are redundant because the remaining parameters are not specified. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,155 | intel | etiotto | @@ -81,23 +81,49 @@ class TargetArchNativeSizes {
unsigned k = 0;
};
+ struct BlockMemShape {
+ BlockMemShape() = default;
+ BlockMemShape(unsigned rowsA, unsigned columnsA, unsigned rowsB,
+ unsigned columnsB)
+ : rowsA(rowsA), columnsA(columnsA), rowsB(rowsB), columnsB(columns... | Make them const so that they are initialized once in the constructor and then can just be read. |
intel-xpu-backend-for-triton | github_2023 | others | 1,155 | intel | etiotto | @@ -175,14 +175,16 @@ tt.func public @simplify_scf_for(%arg0: tensor<16x8xf16>, %arg1: tensor<16x8xf16
// CHECK-LABEL: @matmul_kernel_with_block_pointers
#warp = #triton_intel_gpu.warp<{sizePerThread = [8, 32], threadsPerWarp = [1, 1], order = [1, 0]}>
tt.func public @matmul_kernel_with_block_pointers(%arg0: !tt.ptr... | [nit]: to be consistent with other CHECKS in this file use this pattern:
```
[[C0:%.*]] = ....
```
|
intel-xpu-backend-for-triton | github_2023 | cpp | 1,155 | intel | victor-eds | @@ -121,11 +121,22 @@ class LoadStorePrefetchOpConversion
"only support 1d/2d load/store/prefetch for now");
unsigned dataSize = tensorType.getElementType().getIntOrFloatBitWidth();
- unsigned blockWidth = tensorType.getShape()[1];
- assert(blockWidth == 16 || blockWidth == 32 && "only support ... | ```suggestion
assert((blockWidth == 16 || blockWidth == 32 ||
blockWidth == 64) && "only support 16/32/64 block");
```
I think the current assert is incorrect |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,155 | intel | victor-eds | @@ -121,11 +121,22 @@ class LoadStorePrefetchOpConversion
"only support 1d/2d load/store/prefetch for now");
unsigned dataSize = tensorType.getElementType().getIntOrFloatBitWidth();
- unsigned blockWidth = tensorType.getShape()[1];
- assert(blockWidth == 16 || blockWidth == 32 && "only support ... | ```suggestion
assert((vBlks == 1 || vBlks == 2) && "only support 1 or 2 blocks");
```
same |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,204 | intel | etiotto | @@ -385,8 +385,9 @@ struct LoadOpConversion
Type unpackType = LLVM::getFixedVectorType(
typeConverter->convertType(eltTy), elemsPerLane);
- // pack scalar to i16 for operand A, to i32 for operand B.
- Type elemType = isOperandA ? i16_ty : i32_ty;
+ // pack scalar to i16 for operand A and when e... | ```suggestion
// pack scalars for operand A and B.
Type elemType = (isOperandA && eltTy != f32_ty) ? i16_ty : i32_ty;
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,195 | intel | etiotto | @@ -396,7 +396,7 @@ void init_triton_llvm(py::module &&m) {
ret::take_ownership);
m.def("set_spv_target_triple", [](llvm::Module *mod) {
- std::string triple = "spir64-unknown-unknown";
+ std::string triple = "spirv64v1.3-unknown-unknown"; | This limits the SPIRV features to version 1.3 so we will not get any 1.4 (and later) features.
IGC should backport the SPIRV 1.4 feature to the version of the translator it uses.
When that happens and is delivered in a driver, we can undo this change.
Need to add a FIXME here. |
intel-xpu-backend-for-triton | github_2023 | others | 1,187 | intel | whitneywhtsang | @@ -21,7 +21,7 @@ module attributes {"triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 4 :
// CHECK-DAG: [[ARG3_EXT:%.*]] = arith.extsi %arg3 : i32 to i64
// CHECK-DAG: [[ARG5_EXT:%.*]] = arith.extsi %arg5 : i32 to i64
// CHECK-DAG: [[ARG6_EXT:%.*]] = arith.extsi %arg6 : i32 to i64
- // CHE... | Why we no longer want to test that it is multiplying 32? |
intel-xpu-backend-for-triton | github_2023 | python | 1,139 | intel | whitneywhtsang | @@ -189,6 +189,8 @@ def get_cuda_autotune_config():
num_warps=2),
triton.Config({'BLOCK_SIZE_M': 32, 'BLOCK_SIZE_N': 64, 'BLOCK_SIZE_K': 32, 'GROUP_SIZE_M': 8}, num_stages=5,
num_warps=2),
+ triton.Config({'BLOCK_SIZE_M': 32, 'BLOCK_SIZE_N': 64, 'BLOCK_SIZE_... | Added `get_xpu_autotune_config` in https://github.com/intel/intel-xpu-backend-for-triton/pull/1147, we can add this config for xpu backend in that function. |
intel-xpu-backend-for-triton | github_2023 | python | 655 | intel | whitneywhtsang | @@ -3908,8 +3908,8 @@ def test_precise_math(expr_prec, expr_ref, num_ctas, device):
if is_hip():
pytest.skip("TODO test_precise_math (added by https://github.com/openai/triton/pull/3172) does not work on HIP")
- if is_xpu() and expr_prec == 'tl.math.div_rn(x,y)':
- pytest.skip("FIXME: Fails to... | ```suggestion
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,164 | intel | whitneywhtsang | @@ -164,6 +165,125 @@ struct LoadStoreConversionBase {
const triton::intel::TargetInfo &targetInfo;
};
+struct PrefetchOpConversion
+ : public ConvertTritonGPUOpToLLVMPattern<triton::gpu::intel::PrefetchOp>,
+ public LoadStoreConversionBase {
+ using ConvertTritonGPUOpToLLVMPattern<
+ triton::gpu::i... | nit: unreachable |
intel-xpu-backend-for-triton | github_2023 | others | 1,160 | intel | gshimansky | @@ -11,6 +12,14 @@ on:
description: Upload test reports
type: boolean
default: false
+ ignore_errors:
+ description: Ignore test errors
+ type: boolean
+ default: false
+ run_name:
+ description: Custom run name
+ type: string
+ default: "Bu... | It doesn't seem to be used anywhere in the workflow |
intel-xpu-backend-for-triton | github_2023 | others | 1,160 | intel | leshikus | @@ -31,6 +40,10 @@ jobs:
- spr
- cpu
steps:
+ - name: Print inputs | I like this, because github sometimes puts `null` for inputs |
intel-xpu-backend-for-triton | github_2023 | others | 1,148 | intel | etiotto | @@ -1,10 +1,10 @@
-// RUN: triton-opt %s -split-input-file --tritonintelgpu-accelerate-matmul=device-architecture=ATS | FileCheck %s
+// RUN: triton-opt %s -split-input-file --tritonintelgpu-accelerate-matmul | FileCheck %s
// CHECK-NOT: dpas
#blocked = #triton_gpu.blocked<{sizePerThread = [8, 4], threadsPerWarp = ... | "triton_gpu.compute-capability" is for NVidia and it doesn't make sense for other vendors. Can we remove it in all these tests ? |
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