repo_name stringlengths 1 62 | dataset stringclasses 1
value | lang stringclasses 11
values | pr_id int64 1 20.1k | owner stringlengths 2 34 | reviewer stringlengths 2 39 | diff_hunk stringlengths 15 262k | code_review_comment stringlengths 1 99.6k |
|---|---|---|---|---|---|---|---|
intel-xpu-backend-for-triton | github_2023 | c | 864 | intel | whitneywhtsang | @@ -56,18 +56,46 @@ static inline void gpuAssert(ze_result_t code, const char *file, int line) {
}
static PyObject *getDeviceProperties(PyObject *self, PyObject *args) {
- int device_id;
- if (!PyArg_ParseTuple(args, "i", &device_id))
+ uint64_t cap = 0;
+ if (!PyArg_ParseTuple(args, "K", &cap))
return N... | When does `cap == 0`? |
intel-xpu-backend-for-triton | github_2023 | c | 864 | intel | whitneywhtsang | @@ -56,18 +56,46 @@ static inline void gpuAssert(ze_result_t code, const char *file, int line) {
}
static PyObject *getDeviceProperties(PyObject *self, PyObject *args) {
- int device_id;
- if (!PyArg_ParseTuple(args, "i", &device_id))
+ uint64_t cap = 0;
+ if (!PyArg_ParseTuple(args, "K", &cap))
return N... | where do you get this line from `triton._C.libtriton.intel.passes.ttgpuir`? |
intel-xpu-backend-for-triton | github_2023 | python | 864 | intel | etiotto | @@ -40,7 +40,7 @@ def test_compile_in_subproc() -> None:
major, minor = torch.cuda.get_device_capability(0)
cc = major * 10 + minor
elif torch.xpu.is_available():
- cc = torch.xpu.get_device_capability(0)
+ cc = torch.xpu.device(torch.xpu.current_device()).sycl_device | Instead of `torch.xpu.current_device()` we should use `triton.runtime.driver.active.get_current_device()` like in `test_cache.py` |
intel-xpu-backend-for-triton | github_2023 | c | 864 | intel | etiotto | @@ -56,18 +56,61 @@ static inline void gpuAssert(ze_result_t code, const char *file, int line) {
}
static PyObject *getDeviceProperties(PyObject *self, PyObject *args) {
- int device_id;
- if (!PyArg_ParseTuple(args, "i", &device_id))
+ uint64_t cap = 0; | What is `cap`. What does it stand for? Please use a more descriptive name. |
intel-xpu-backend-for-triton | github_2023 | c | 864 | intel | etiotto | @@ -56,18 +56,61 @@ static inline void gpuAssert(ze_result_t code, const char *file, int line) {
}
static PyObject *getDeviceProperties(PyObject *self, PyObject *args) {
- int device_id;
- if (!PyArg_ParseTuple(args, "i", &device_id))
+ uint64_t cap = 0;
+ if (!PyArg_ParseTuple(args, "K", &cap))
return N... | How do you know you can safely cast `cap` to a pointer ? |
intel-xpu-backend-for-triton | github_2023 | c | 864 | intel | etiotto | @@ -209,32 +242,28 @@ static PyObject *loadBinary(PyObject *self, PyObject *args) {
const char *name;
int shared;
PyObject *py_bytes;
- int devId;
+ uint64_t *cap; | use a more descriptive variable name please. |
intel-xpu-backend-for-triton | github_2023 | python | 864 | intel | etiotto | @@ -49,27 +49,36 @@ def __new__(cls):
return cls.instance
def __init__(self):
+ if hasattr(self, "cache"):
+ return
dirname = os.path.dirname(os.path.realpath(__file__))
mod = compile_module_from_src(Path(os.path.join(dirname, "driver.c")).read_text(), "spirv_utils")
... | Use triton.runtime.driver.active.get_current_device() |
intel-xpu-backend-for-triton | github_2023 | cpp | 907 | intel | Dewei-Wang-sh | @@ -209,39 +216,52 @@ class ArithRemPattern : public OpRewritePattern<arith::RemSIOp> {
}
};
-/// Simplify SCF loops.
-/// before:
+/// Simplify SCF for loops.
+/// Before:
/// %glue = triton_intel_gpu.glue %a, %b : tensor<4x4xf32>, tensor<4x4xf32>
/// -> tensor<8x4xf32>
-/// scf.for %i = %lb to %ub... | ```suggestion
/// use %arg
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 907 | intel | Dewei-Wang-sh | @@ -209,39 +216,52 @@ class ArithRemPattern : public OpRewritePattern<arith::RemSIOp> {
}
};
-/// Simplify SCF loops.
-/// before:
+/// Simplify SCF for loops.
+/// Before:
/// %glue = triton_intel_gpu.glue %a, %b : tensor<4x4xf32>, tensor<4x4xf32>
/// -> tensor<8x4xf32>
-/// scf.for %i = %lb to %ub... | here "init.getDefiningOp" is used 3 times.
so keep the old way would be better. |
intel-xpu-backend-for-triton | github_2023 | cpp | 907 | intel | Dewei-Wang-sh | @@ -546,8 +638,10 @@ void MatchTargetSizePass::transformGenericOp(Operation *op) {
if (auto tensorType = dyn_cast<RankedTensorType>(type))
if (isa<tt::LoadOp>(op)) {
Attribute layout = tensorType.getEncoding();
- if (auto dotAttr = dyn_cast<ttg::DotOperandEncodingAttr>(layout)) | here we expect the tensorType must have an encoding,
so it will core dump when it's not, and we can easily get to the problem by trace.
however if we skip this, the error will go later, and need time to find the root cause. |
intel-xpu-backend-for-triton | github_2023 | others | 907 | intel | Dewei-Wang-sh | @@ -76,3 +76,92 @@ module {
tt.return
}
}
+
+// -----
+
+// COM: Test SCF canonicalization: ensure result of loop (containing simplification opportunities) can be
+// consumed by a extract operations. | thanks Ettore, your improvement make it complete and easy to understand the logic |
intel-xpu-backend-for-triton | github_2023 | cpp | 907 | intel | whitneywhtsang | @@ -216,39 +217,52 @@ class ArithRemPattern : public OpRewritePattern<arith::RemSIOp> {
}
};
-/// Simplify SCF loops.
-/// before:
+/// Simplify SCF for loops.
+/// Before:
/// %glue = triton_intel_gpu.glue %a, %b : tensor<4x4xf32>, tensor<4x4xf32>
/// -> tensor<8x4xf32>
-/// scf.for %i = %lb to %ub... | ```suggestion
if (!isa_and_nonnull<ttgi::GlueOp>(init.getDefiningOp())) {
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 907 | intel | whitneywhtsang | @@ -289,17 +305,18 @@ class ScfPattern : public OpRewritePattern<scf::ForOp> {
rewriter.create<scf::YieldOp>(yield.getLoc(), newValues);
rewriter.eraseOp(yield);
- // replace results
+ // Replace uses of the original loop results with the new loop results.
userIndexMap.clear();
idx = 0;
- ... | ```suggestion
if (!isa_and_nonnull<ttgi::GlueOp>(init.getDefiningOp())) {
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 907 | intel | whitneywhtsang | @@ -563,7 +620,6 @@ void MatchTargetSizePass::transformDotOp(tt::DotOp dot) {
dot->replaceAllUsesWith(
b.create<ttgi::GlueOp>(loc, dot.getType(), subCs)->getResults());
- dot->erase(); | is the removal of this line intentional? |
intel-xpu-backend-for-triton | github_2023 | others | 899 | intel | whitneywhtsang | @@ -1,4 +1,4 @@
-// RUN: triton-opt %s -split-input-file -tritonintelgpu-match-target-size | FileCheck %s
+// RUN: triton-opt %s -split-input-file -tritonintelgpu-match-target-size --verify-each | FileCheck %s | What does `verify-each` do, is it not enabled by default? |
intel-xpu-backend-for-triton | github_2023 | cpp | 899 | intel | Dewei-Wang-sh | @@ -104,21 +104,15 @@ class MatchTargetSizePass
MLIRContext *ctx = &getContext();
ModuleOp m = getOperation();
- // Collect `tt.dot` operations layouts.
+ // Collect the result layout of "interesting" `tt.dot` operations.
+ // A candidate 'tt.dot' operation yields a tensor(or pointer to tensor) wit... | ```suggestion
// A candidate 'tt.dot' operation yields a tensor with
```
for dot, it can only be tensor |
intel-xpu-backend-for-triton | github_2023 | cpp | 899 | intel | Dewei-Wang-sh | @@ -127,27 +121,33 @@ class MatchTargetSizePass
op->getResultTypes().end());
types.append(resultTypes);
- if (llvm::none_of(types, isTensorOrPtrToTensor))
+ if (llvm::none_of(types, [this](Type type) { return isCandidate(type); }))
return WalkResult::adva... | keep "recordRootSubSize" at the top level, would be easy to see when we decide the "root config"
whereas move it to transform, it's hard to notice.
|
intel-xpu-backend-for-triton | github_2023 | cpp | 899 | intel | Dewei-Wang-sh | @@ -158,6 +158,10 @@ class MatchTargetSizePass
/// architecture.
void initNativeOperationSizes();
+ /// Determine whether the given type is a tensor (or a pointer to a tensor)
+ /// that has a warp layout or a dot layout with a parent warp layout.
+ bool isCandidate(Type type) const; | another alternative would be "hasTensorTypewithLayout"
people can get its meaning from the name itself, while the "candidate" is kind of general, people have to have a second look.
trival thing though. |
intel-xpu-backend-for-triton | github_2023 | cpp | 899 | intel | Dewei-Wang-sh | @@ -599,8 +637,6 @@ void MatchTargetSizePass::transformGenericOp(Operation *op) {
if (numResults == 1)
op->replaceAllUsesWith(b.create<ttgi::GlueOp>(loc, type, subOps));
-
- op->erase(); | will this be done in the same pass but in another pr?
transform and cleanup code in the same time would be more efficient than relying on a separate dce pass. |
intel-xpu-backend-for-triton | github_2023 | others | 860 | intel | whitneywhtsang | @@ -9,4 +9,5 @@ add_triton_plugin(TritonXPU
LINK_LIBS
TritonIntelGPUToLLVM
TritonGENToLLVM
+ TritonIntelGPUTransforms | Please put them in alphabetical order. |
intel-xpu-backend-for-triton | github_2023 | others | 860 | intel | whitneywhtsang | @@ -1,3 +1,4 @@
add_subdirectory(GPUToTritonGEN)
add_subdirectory(TritonGENToLLVM)
add_subdirectory(TritonIntelGPUToLLVM)
+add_subdirectory(TritonIntelGPUTransforms) | Please put them in alphabetical order |
intel-xpu-backend-for-triton | github_2023 | cpp | 873 | intel | whitneywhtsang | @@ -1,7 +1,7 @@
#include "PatternTritonGPUOpToLLVM.h"
#include "Utility.h"
-#include "mlir/Dialect/LLVMIR/NVVMDialect.h"
-#include "triton/Analysis/Utility.h"
+// #include "mlir/Dialect/LLVMIR/NVVMDialect.h"
+// #include "triton/Analysis/Utility.h" | ```suggestion
``` |
intel-xpu-backend-for-triton | github_2023 | python | 868 | intel | etiotto | @@ -3125,12 +3106,22 @@ def kernel(X, stride_xm, stride_xk, Y, stride_yk, stride_yn, W, stride_wn, strid
else:
out_dtype = tl.float32
- pgm = kernel[(1, 1)](x_tri, x_tri.stride(0), x_tri.stride(1), y_tri, y_tri.stride(0), y_tri.stride(1), w_tri,
- w_tri.stride(0), w_tri.stride... | This is a temporary change. I think we should default to 16 thread per warp if the kernel contains a dot operation. |
intel-xpu-backend-for-triton | github_2023 | others | 855 | intel | whitneywhtsang | @@ -8,11 +8,14 @@ include "triton/Dialect/TritonGPU/IR/TritonGPUTypes.td"
include "triton/Dialect/TritonIntelGPU/IR/TritonIntelGPUAttrDefs.td"
include "triton/Dialect/TritonIntelGPU/IR/TritonIntelGPUDialect.td"
include "mlir/IR/OpBase.td"
+include "mlir/Interfaces/CastInterfaces.td" | How is the CastInterface used? |
intel-xpu-backend-for-triton | github_2023 | others | 855 | intel | whitneywhtsang | @@ -8,4 +8,5 @@ add_triton_library(TritonIntelGPUIR
LINK_LIBS PUBLIC
MLIRGPUDialect
+ MLIRCastInterfaces | How is the CastInterface used? |
intel-xpu-backend-for-triton | github_2023 | cpp | 855 | intel | whitneywhtsang | @@ -1,13 +1,170 @@
#include "mlir/IR/Builders.h"
+#include "mlir/Support/LLVM.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/TypeSwitch.h"
+
+#include "triton/Dialect/Triton/IR/Types.h"
#include "triton/Dialect/TritonIntelGPU/IR/Dialect.h"
#define GET_OP_CLASSES
#include "triton/Dialect/TritonIntelGPU/IR... | may work without this return? |
intel-xpu-backend-for-triton | github_2023 | cpp | 855 | intel | whitneywhtsang | @@ -1,13 +1,170 @@
#include "mlir/IR/Builders.h"
+#include "mlir/Support/LLVM.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/TypeSwitch.h"
+
+#include "triton/Dialect/Triton/IR/Types.h"
#include "triton/Dialect/TritonIntelGPU/IR/Dialect.h"
#define GET_OP_CLASSES
#include "triton/Dialect/TritonIntelGPU/IR... | may work without this return? |
intel-xpu-backend-for-triton | github_2023 | cpp | 855 | intel | whitneywhtsang | @@ -1,13 +1,170 @@
#include "mlir/IR/Builders.h"
+#include "mlir/Support/LLVM.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/TypeSwitch.h"
+
+#include "triton/Dialect/Triton/IR/Types.h"
#include "triton/Dialect/TritonIntelGPU/IR/Dialect.h"
#define GET_OP_CLASSES
#include "triton/Dialect/TritonIntelGPU/IR... | may work without this return? |
intel-xpu-backend-for-triton | github_2023 | cpp | 855 | intel | whitneywhtsang | @@ -1,13 +1,170 @@
#include "mlir/IR/Builders.h"
+#include "mlir/Support/LLVM.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/TypeSwitch.h"
+
+#include "triton/Dialect/Triton/IR/Types.h"
#include "triton/Dialect/TritonIntelGPU/IR/Dialect.h"
#define GET_OP_CLASSES
#include "triton/Dialect/TritonIntelGPU/IR... | may work without this return? |
intel-xpu-backend-for-triton | github_2023 | cpp | 855 | intel | whitneywhtsang | @@ -1,13 +1,170 @@
#include "mlir/IR/Builders.h"
+#include "mlir/Support/LLVM.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/TypeSwitch.h"
+
+#include "triton/Dialect/Triton/IR/Types.h"
#include "triton/Dialect/TritonIntelGPU/IR/Dialect.h"
#define GET_OP_CLASSES
#include "triton/Dialect/TritonIntelGPU/IR... | What is `sizes` for? |
intel-xpu-backend-for-triton | github_2023 | cpp | 855 | intel | whitneywhtsang | @@ -1,13 +1,170 @@
#include "mlir/IR/Builders.h"
+#include "mlir/Support/LLVM.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/TypeSwitch.h"
+
+#include "triton/Dialect/Triton/IR/Types.h"
#include "triton/Dialect/TritonIntelGPU/IR/Dialect.h"
#define GET_OP_CLASSES
#include "triton/Dialect/TritonIntelGPU/IR... | can we check that the sum of the sizes equals to the result at dim? |
intel-xpu-backend-for-triton | github_2023 | others | 855 | intel | Dewei-Wang-sh | @@ -33,6 +36,62 @@ def TTIG_AllocOp : TTIG_Op<"alloc", [MemoryEffects<[MemAlloc]>]> {
let results = (outs TT_Ptr:$result);
}
+def TTIG_ConcatOp : TTIG_Op<"concat", [Pure]> {
+ let summary = "Tensor concatenation operation";
+ let description = [{
+ The `concat` operation concatenates its input operands along... | as commented in the other pr,
if we want to concat a tensor along 1 dim, upstream has tensor.concat that works this way. |
intel-xpu-backend-for-triton | github_2023 | python | 856 | intel | whitneywhtsang | @@ -4842,6 +4842,11 @@ def test_convert2d(M, N, src_layout, interm_layout, dst_layout, dtype, device):
kernel = triton.compile(f.name, options={'threads_per_warp': THREADS_PER_WARP})
kernel[(1, 1, 1)](x.data_ptr(), z.data_ptr())
+ for i in range(M): | I prefer not to have these prints to avoid merge conflicts. |
intel-xpu-backend-for-triton | github_2023 | cpp | 854 | intel | whitneywhtsang | @@ -1,3 +1,11 @@
+//===----------------------------------------------------------------------===// | can we add the file name here? |
intel-xpu-backend-for-triton | github_2023 | cpp | 828 | intel | etiotto | @@ -76,9 +76,16 @@ static Value commonShflSync(Location loc, ConversionPatternRewriter &rewriter,
vec = insert_element(vecTy, vec, val1, i32_val(1));
return bitcast(vec, val.getType());
}
- Type type = val.getType();
- return rewriter.create<TritonGEN::SubGroupShuffleOp>(loc, type, val, i,
- ... | This handles the case of `i1` but shouldn't we do the same for any integer type with size < 8 ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 828 | intel | whitneywhtsang | @@ -76,9 +76,16 @@ static Value commonShflSync(Location loc, ConversionPatternRewriter &rewriter,
vec = insert_element(vecTy, vec, val1, i32_val(1));
return bitcast(vec, val.getType());
}
- Type type = val.getType();
- return rewriter.create<TritonGEN::SubGroupShuffleOp>(loc, type, val, i,
- ... | We should either
1. sink the zext and trunc to TritonGEN::SubGroupShuffleOp lowering; or
2. limit the input type allowed for TritonGEN::SubGroupShuffleOp |
intel-xpu-backend-for-triton | github_2023 | python | 845 | intel | whitneywhtsang | @@ -1033,8 +1033,8 @@ def kernel(X, Y, OUT, OUT_REF, BLOCK: tl.constexpr):
kernel[(1, )](x, y, out, out_ref, BLOCK=shape[0], num_ctas=num_ctas)
if is_xpu() and expr_prec == 'tl.math.div_rn(x,y)':
- np.testing.assert_allclose(to_numpy(out), to_numpy(out_ref), rtol=1e-6)
- pytest.skip("FIXME: Fa... | can we remove `and expr_prec == 'tl.math.div_rn(x,y)'` from the check? This will likely make sqrt_rn fail, if so, please open an issue to fix the sqrt_rn failure. |
intel-xpu-backend-for-triton | github_2023 | cpp | 834 | intel | etiotto | @@ -311,30 +311,28 @@ class TritonIntelGPUDistributeToWarpsPass
typeMap[op] = op.getSrc().getType().cast<RankedTensorType>();
});
+ Dialect *arithDialect = getContext().getLoadedDialect("arith");
+ Dialect *mathDialect = getContext().getLoadedDialect("math");
func.walk<WalkOrder::PreO... | You can change lines 331-333 of the `TypeSwitch` to:
```
if (isa<tt::LoadOp, tt::DotOp, tt::AdvanceOp>(
op) || op->getDialect() == arithDialect || ... )
distributeGenericOp(op); |
intel-xpu-backend-for-triton | github_2023 | others | 843 | intel | Dewei-Wang-sh | @@ -161,6 +161,41 @@ def TritonGEN_BarrierOp : TritonGEN_Op<"barrier"> {
let assemblyFormat = "attr-dict";
}
+def TritonGEN_NamedBarrierSignalOp : TritonGEN_Op<"named_barrier_signal">,
+ Arguments<(ins I32:$barrier_id, I32:$thread_group_count)> { | wondering, are these bound to be constant?
if that's the case, I32Attr would be more constrained
|
intel-xpu-backend-for-triton | github_2023 | others | 809 | intel | pbchekin | @@ -0,0 +1,4 @@
+# FIXME https://github.com/intel/intel-xpu-backend-for-triton/issues/806
+test_reduce_layouts
+# FIXME https://github.com/intel/intel-xpu-backend-for-triton/issues/807
+language/test_random.py | You exclude too much, why not individual tests? |
intel-xpu-backend-for-triton | github_2023 | others | 809 | intel | pbchekin | @@ -109,37 +99,23 @@ run_core_tests() {
fi
cd ${CORE_TEST_DIR}
- TRITON_DISABLE_LINE_INFO=1 python3 -m pytest -n 8 --verbose --device xpu language/ --ignore=language/test_line_info.py
- if [ $? -ne 0 ]; then
- echo "FAILED: return code $?" ; exit $?
+ exclude_list=/
+ if [ -n ../exclude_list ]; then | Typo?
```suggestion
if [ -f ../exclude_list ]; then
``` |
intel-xpu-backend-for-triton | github_2023 | others | 809 | intel | pbchekin | @@ -109,37 +99,23 @@ run_core_tests() {
fi
cd ${CORE_TEST_DIR}
- TRITON_DISABLE_LINE_INFO=1 python3 -m pytest -n 8 --verbose --device xpu language/ --ignore=language/test_line_info.py
- if [ $? -ne 0 ]; then
- echo "FAILED: return code $?" ; exit $?
+ exclude_list=/ | Have you tested that `pytest ... -k /` works when there is no exclude list? |
intel-xpu-backend-for-triton | github_2023 | others | 809 | intel | pbchekin | @@ -99,7 +99,16 @@ run_core_tests() {
fi
cd ${CORE_TEST_DIR}
- TRITON_DISABLE_LINE_INFO=1 python3 -m pytest -n 8 --verbose --device xpu language/ --ignore=language/test_line_info.py
+ exclude_list_k=
+ exclude_list=
+ if [ -f ../../../scripts/core_exclude_list ]; then
+ exclude_list_k=-k
+ exclude_lis... | Duplicate? |
intel-xpu-backend-for-triton | github_2023 | others | 809 | intel | pbchekin | @@ -131,6 +140,7 @@ run_tutorial_test() {
echo
echo "****** Running $1 test ******"
echo
+ | This change is not needed. |
intel-xpu-backend-for-triton | github_2023 | cpp | 529 | intel | etiotto | @@ -16,6 +16,8 @@ std::unique_ptr<Pass> createAccelerateMatmulPass(int computeCapability = 80);
std::unique_ptr<Pass> createPrefetchPass();
+std::unique_ptr<Pass> createTritonGPUDistributeToWarpsPass(); | We should move this pass to the transform passes of the TrtitonIntelGPU dialect. |
intel-xpu-backend-for-triton | github_2023 | others | 529 | intel | etiotto | @@ -188,6 +188,20 @@ def TTG_LocalDeallocOp : TTG_Op<"local_dealloc", [MemoryEffects<[MemFree<SharedM
let assemblyFormat = [{$ptr attr-dict `:` qualified(type($ptr))}];
}
+def TTG_AllocOp : TTG_Op<"alloc", [MemoryEffects<[MemAlloc]> // Allocate shared memory | Moving this to the `TritonIntelGPU` dialect. |
intel-xpu-backend-for-triton | github_2023 | others | 529 | intel | etiotto | @@ -51,6 +51,23 @@ def TritonGPUPrefetch : Pass<"tritongpu-prefetch", "mlir::ModuleOp"> {
"mlir::arith::ArithDialect"];
}
+def TritonGPUDistributeToWarps : Pass<"tritongpu-distribute-to-warps", "mlir::ModuleOp"> { | We should move this pass to the transform passes of the `TritonIntelGPU` dialect. |
intel-xpu-backend-for-triton | github_2023 | others | 529 | intel | whitneywhtsang | @@ -61,6 +61,35 @@ Right now, Triton implements two classes of layouts: shared, and distributed.
}];
}
+//===----------------------------------------------------------------------===//
+// Warp Encoding
+//===----------------------------------------------------------------------===//
+
+def WarpEncodingAttr : Tri... | Can this attribute be moved to TritonIntelGPUAttrDefs.td? |
intel-xpu-backend-for-triton | github_2023 | others | 529 | intel | whitneywhtsang | @@ -20,11 +20,12 @@ def TritonIntelGPUAccelerateMatmul
compatible with the Intel DPAS instruction requirements.
}];
- let constructor = "mlir::createTritonIntelGPUAccelerateMatmulPass()";
+ let constructor = "mlir::triton::gpu::intel::createTritonIntelGPUAccelerateMatmulPass()";
let dependentDialects =... | Why adding back TritonGPUDialect? |
intel-xpu-backend-for-triton | github_2023 | others | 529 | intel | whitneywhtsang | @@ -38,6 +39,64 @@ def TritonIntelGPUAccelerateMatmul
];
}
+def TritonIntelGPUDistributeToWarps
+ : Pass<"tritonintelgpu-distribute-to-warps", "mlir::ModuleOp"> {
+ let summary = "distribute the thread block workload to the warps";
+
+ let description = [{
+ Changes the tensor type and layout
+
+ For e... | can we define #warpC here as well? |
intel-xpu-backend-for-triton | github_2023 | others | 529 | intel | whitneywhtsang | @@ -38,6 +39,64 @@ def TritonIntelGPUAccelerateMatmul
];
}
+def TritonIntelGPUDistributeToWarps
+ : Pass<"tritonintelgpu-distribute-to-warps", "mlir::ModuleOp"> {
+ let summary = "distribute the thread block workload to the warps";
+
+ let description = [{
+ Changes the tensor type and layout
+
+ For e... | do we really need TritonGPUDialect here?
I think we need ArithDialect though |
intel-xpu-backend-for-triton | github_2023 | cpp | 529 | intel | whitneywhtsang | @@ -119,6 +119,9 @@ getThreadsPerWarpWithUniqueData(Attribute layout,
}
SmallVector<unsigned> getWarpsPerCTA(Attribute layout) {
+ if (auto dotLayout = layout.dyn_cast<DotOperandEncodingAttr>()) { | can we upstream this change? |
intel-xpu-backend-for-triton | github_2023 | cpp | 529 | intel | whitneywhtsang | @@ -32,96 +31,86 @@ namespace ttgi = mlir::triton::gpu::intel;
namespace {
-/// Add named attrs contained in \p dictAttrs to the given operation \p op.
-void addNamedAttrs(Operation *op, DictionaryAttr dictAttrs) {
- for (const NamedAttribute attr : dictAttrs.getValue())
- if (!op->hasAttr(attr.getName()))
- ... | https://llvm.org/docs/CodingStandards.html#use-auto-type-deduction-to-make-code-more-readable |
intel-xpu-backend-for-triton | github_2023 | cpp | 529 | intel | etiotto | @@ -205,21 +197,24 @@ void distributeArithConstantOp(arith::ConstantOp op) {
auto value = cast<DenseElementsAttr>(op.getValue()).resizeSplat(newType);
OpBuilder b(op);
auto newOp = b.create<arith::ConstantOp>(op.getLoc(), newType, value);
- addNamedAttrs(newOp, op->getAttrDictionary());
+
+ for (const NamedA... | fixed |
intel-xpu-backend-for-triton | github_2023 | others | 529 | intel | whitneywhtsang | @@ -49,9 +50,9 @@ def TritonIntelGPUDistributeToWarps
For example, given:
```mlir
- #blockedC = #triton_gpu.blocked<{sizePerThread = [64, 64], threadsPerWarp = [1, 1], warpsPerCTA = [2, 2], order = [1, 0], CTAsPerCGA = [1, 1], CTASplitNum = [1, 1], CTAOrder = [1, 0]}>
#blockedA = #triton_gpu.dot_op<... | probably cannot change the order there, as #blockedA reference #blockedC |
intel-xpu-backend-for-triton | github_2023 | cpp | 804 | intel | etiotto | @@ -161,29 +161,11 @@ SmallVector<unsigned> getSizePerThread(Attribute layout) {
}
SmallVector<unsigned> getContigPerThread(Attribute layout) {
- if (auto mmaLayout = layout.dyn_cast<NvidiaMmaEncodingAttr>()) {
- assert(mmaLayout.isVolta() || mmaLayout.isAmpere() || mmaLayout.isHopper());
- auto rank = trito... | Changing this function this way makes this function substantially different from upstream code (https://github.com/openai/triton/blob/main/lib/Dialect/TritonGPU/IR/Dialect.cpp) and will make it difficult to upstream our BE.
Can we use the `layout` information and add a `else if` to handle the case when layout is of... |
intel-xpu-backend-for-triton | github_2023 | others | 804 | intel | etiotto | @@ -480,6 +480,10 @@ For the Threads Per Warp and Values Per Thread level, the linear id distribution
"SmallVector<unsigned>",
"getShapePerCTATile",
(ins "ArrayRef<int64_t>":$tensorShape)>,
+
+ InterfaceMethod<"Gets the number of contiguous elements per... | If we want to add this interface we should do it upstream because we want to work toward reducing the difference with the common code. I am OK if we do it downstream first, but we also need to post a corresponding PR upstream. |
intel-xpu-backend-for-triton | github_2023 | cpp | 821 | intel | whitneywhtsang | @@ -2480,6 +2480,9 @@ void populateElementwiseOpToLLVMPatterns(
POPULATE_UNARY_OP(triton::PtrToIntOp, LLVM::PtrToIntOp)
#undef POPULATE_UNARY_OP
+ patterns.add<ElementwiseOpConversion<math::FmaOp, LLVM::FMAOp>>( | What is math::FmaOp lower to by default? |
intel-xpu-backend-for-triton | github_2023 | cpp | 818 | intel | whitneywhtsang | @@ -465,8 +382,6 @@ struct ConvertLayoutOpConversion
Attribute srcLayout = srcTy.getEncoding();
Attribute dstLayout = dstTy.getEncoding();
- if (shouldUseDistSmem(srcLayout, dstLayout)) | From looking at the implementation of `shouldUseDistSmem`, it doesn't always return false, its result depends on the use case. |
intel-xpu-backend-for-triton | github_2023 | cpp | 817 | intel | etiotto | @@ -63,6 +63,7 @@ struct OpToFuncCallLowering : public ConvertOpToLLVMPattern<SourceOp> {
LLVMFuncOp funcOp = appendOrGetFuncOp(funcName, funcType, op);
auto callOp =
rewriter.create<LLVM::CallOp>(op->getLoc(), funcOp, castedOperands);
+ callOp.setCConv(LLVM::cconv::CConv::SPIR_FUNC); | Good catch! |
intel-xpu-backend-for-triton | github_2023 | others | 769 | intel | pbchekin | @@ -49,3 +49,8 @@ RUN \
cd $HOME; \
/bin/sh l_BaseKit*.sh -a --silent --eula accept; \
rm l_BaseKit*.sh
+
+RUN \
+ wget https://repo.anaconda.com/miniconda/Miniconda3-latest-Linux-x86_64.sh; \
+ sh Miniconda3-latest-Linux-x86_64.sh -b | WORKDIR is not set, / is not writable by user runner. Also see this hadolint warning https://github.com/hadolint/hadolint/wiki/DL4001 (Either use wget or curl but not both).
```suggestion
RUN \
cd /tmp; \
curl -sSLO https://repo.anaconda.com/miniconda/Miniconda3-latest-Linux-x86_64.sh; \
sh Miniconda3-latest... |
intel-xpu-backend-for-triton | github_2023 | others | 769 | intel | pbchekin | @@ -39,13 +38,18 @@ RUN set -ex; \
rm -rf /var/lib/apt/lists/*
USER runner
+WORKDIR $HOME
+
SHELL ["/bin/bash", "-xec"]
COPY --from=installer /l_BaseKit*.sh $HOME/
# TODO: install only necessary components
-
RUN \
- cd $HOME; \
/bin/sh l_BaseKit*.sh -a --silent --eula accept; \
rm l_BaseKit*.sh
+... | Why do you keep `.sh` file in the image? |
intel-xpu-backend-for-triton | github_2023 | others | 769 | intel | pbchekin | @@ -36,16 +36,22 @@ RUN set -ex; \
\
gh \
; \
+ apt install -y --no-install-recommends --allow-downgrades --fix-missing libigc1=1.0.15136.24-775~22.04; \
rm -rf /var/lib/apt/lists/*
USER runner
+WORKDIR $HOME
+
SHELL ["/bin/bash", "-xec"]
COPY --from=installer /l_BaseKit*.sh $HOME/
... | ```suggestion
sh Miniconda3-latest-Linux-x86_64.sh -b; \
``` |
intel-xpu-backend-for-triton | github_2023 | python | 801 | intel | etiotto | @@ -49,15 +49,15 @@ def test_assert(func: str):
x = torch.arange(0, shape[0], dtype=torch.int32, device='xpu')
y = torch.zeros(shape, dtype=x.dtype, device="xpu")
if func == "device_assert":
- kernel_device_assert[(1, )](x, y, BLOCK=shape[0], threads_per_warp=32)
+ kernel_device_assert[(1, ... | The assert operation should work for any grid. Can you highlight what part of these tests are designed to work with num_warps==4 ? |
intel-xpu-backend-for-triton | github_2023 | others | 811 | intel | leshikus | @@ -98,7 +98,7 @@ jobs:
runs-on:
- glados
- spr
- - runner-0.0.7
+ - runner-0.0.11 | good catch, I've missed it |
intel-xpu-backend-for-triton | github_2023 | others | 811 | intel | leshikus | @@ -33,9 +33,12 @@ runs:
- name: Load IPEX wheels from a cache
id: ipex-cache
uses: ./.github/actions/load
+ env:
+ # Increase this value to reset cache
+ CACHE_NUMBER: "1" | I wonder if Gregory's action `install-wheels` can be used instead. There are two places already where it is used |
intel-xpu-backend-for-triton | github_2023 | cpp | 802 | intel | etiotto | @@ -158,6 +172,18 @@ static LLVM::CallOp createGenISADPAS(TritonGEN::MatrixDPASOp op,
if (bOrigTy != bTy)
b = rewriter.create<LLVM::BitcastOp>(loc, bTy, b);
+ if (precisionA != TritonGEN::PrecisionType::TF32) { | Add a FIXME: we will want to use the OpenCL API also for the remaining TF32 case. |
intel-xpu-backend-for-triton | github_2023 | cpp | 802 | intel | etiotto | @@ -67,6 +67,31 @@ static LLVM::CallOp createDeviceFunctionCall(
return callOp;
}
+static std::string getTypeMangling(Type ty) {
+ return TypeSwitch<Type, std::string>(ty)
+ .Case<VectorType>([&](auto ty) {
+ return "Dv" + std::to_string(ty.getNumElements()) + "_" +
+ getTypeMangling(ty... | Remove capturing for this and below |
intel-xpu-backend-for-triton | github_2023 | python | 796 | intel | whitneywhtsang | @@ -34,6 +34,13 @@ def test_print(func_type: str, data_type: str):
outs, _ = proc.communicate()
outs = [line for line in outs.decode("UTF-8").split("\n") if line]
+ if (func_type, data_type) == ('print', 'int32'): | These tests pass for me when only upgrading libigc1, do you know which component cause the failures? |
intel-xpu-backend-for-triton | github_2023 | others | 796 | intel | whitneywhtsang | @@ -165,7 +165,7 @@ jobs:
python3 05-layer-norm.py
python3 06-fused-attention.py
python3 07-extern-functions.py
- python3 08-grouped-gemm.py
+ python3 08-grouped-gemm.py || true | Please add a FIXME comment here |
intel-xpu-backend-for-triton | github_2023 | cpp | 799 | intel | whitneywhtsang | @@ -304,80 +310,50 @@ struct ReduceOpConversion
auto smemShape = helper.getScratchConfig();
unsigned elems = product<unsigned>(smemShape);
unsigned sizeInterWarps = helper.getInterWarpSizeWithUniqueData();
- assert(((sizeInterWarps - 1) & sizeInterWarps) == 0 &&
- "sizeInterWarps must be 2^m... | These changes were added intentionally in https://github.com/intel/intel-xpu-backend-for-triton/pull/697. |
intel-xpu-backend-for-triton | github_2023 | cpp | 697 | intel | whitneywhtsang | @@ -310,48 +310,75 @@ struct ReduceOpConversion
Location loc = op.getLoc();
Value threadId = getThreadId(rewriter, loc);
- Value warpSize = getModuleWarpSize(rewriter, loc);
- Value laneId = urem(threadId, warpSize);
Value zero = i32_val(0);
auto mod = op.getOperation()->getParentOfType<Mo... | how do we know sizeInterWarps is divisible by threadsPerWarp? |
intel-xpu-backend-for-triton | github_2023 | cpp | 780 | intel | ienkovich | @@ -339,6 +353,32 @@ emitBaseIndexForLayout(Location loc, RewriterBase &rewriter, Attribute layout,
return result;
}
+static SmallVector<SmallVector<unsigned>>
+emitOffsetForLayout(Attribute layout, RankedTensorType type) {
+ if (auto blockedLayout = layout.dyn_cast<BlockedEncodingAttr>())
+ return emitOffset... | Can we simplify this function by handling DPAS and Slice and then calling the common version of `emitOffsetForLayout` for the rest? |
intel-xpu-backend-for-triton | github_2023 | cpp | 780 | intel | ienkovich | @@ -339,6 +353,32 @@ emitBaseIndexForLayout(Location loc, RewriterBase &rewriter, Attribute layout,
return result;
}
+static SmallVector<SmallVector<unsigned>>
+emitOffsetForLayout(Attribute layout, RankedTensorType type) { | It looks like changes in this function for DPAS force us to copy a lot of other code. Can we try to handle it through the target info object? E. g. instead of `llvm_unreachable` common version might call `targetInfo.emitOffsetForTargetLayout` where we would process the DPAS layout. The default implementation would be a... |
intel-xpu-backend-for-triton | github_2023 | others | 775 | intel | etiotto | @@ -148,6 +128,14 @@ then
fi
build_llvm() {
+
+ # Clone the LLVM repository (with GENX dialect). | Just change this comment to: #Clone the genx branch from the Intel LLVM repository. |
intel-xpu-backend-for-triton | github_2023 | python | 637 | intel | chengjunlu | @@ -41,18 +41,32 @@ class XPUOptions:
optimize_epilogue: bool = False
enable_fp_fusion: bool = True
allow_fp8e4nv: bool = False
- max_num_imprecise_acc_default: bool = None
+ max_num_imprecise_acc_default: int = 0 # `max_num_imprecise_acc` only applies to fp8 -> fp32 dot on sm_90 for cuda
ext... | We don't need to add the device properties information to the compile options.
The compile options are exported as a tune-able properties for the user. And it would be used as hash key for caching.
Just simply remove those fields in options. |
intel-xpu-backend-for-triton | github_2023 | python | 637 | intel | chengjunlu | @@ -67,14 +81,21 @@ def supports_target(target: tuple):
def __init__(self, target: tuple) -> None:
super().__init__(target)
- self.capability = target[1]
- assert isinstance(self.capability, int)
+ assert isinstance(target[1], dict)
+ # TODO: Deprecate capability in XPU compi... | Please create an issue to track the deprecation on the capability. |
intel-xpu-backend-for-triton | github_2023 | python | 637 | intel | chengjunlu | @@ -67,14 +81,21 @@ def supports_target(target: tuple):
def __init__(self, target: tuple) -> None:
super().__init__(target)
- self.capability = target[1]
- assert isinstance(self.capability, int)
+ assert isinstance(target[1], dict)
+ # TODO: Deprecate capability in XPU compi... | We don't have to put the device capability to the compile option. |
intel-xpu-backend-for-triton | github_2023 | cpp | 637 | intel | whitneywhtsang | @@ -47,8 +47,6 @@ void init_triton_intel_passes_ttgpuir(py::module &&m) {
void init_triton_intel_passes_ttnvgpuir(py::module &&m) {
ADD_PASS_WRAPPER_1("add_plan_cta", mlir::createTritonNvidiaGPUPlanCTAPass,
mlir::triton::nvidia_gpu::ClusterInfo *);
- ADD_PASS_WRAPPER_0("add_fence_insertion", | We probably want to remove `init_triton_intel_passes_ttnvgpuir` completely, but wonder why you need to remove `add_fence_insertion` in this PR? |
intel-xpu-backend-for-triton | github_2023 | python | 637 | intel | whitneywhtsang | @@ -118,18 +135,12 @@ def make_ttgir(mod, metadata, opt, capability):
passes.ttgpuir.add_optimize_epilogue(pm)
passes.ttgpuir.add_optimize_dot_operands(pm)
passes.common.add_cse(pm)
- if capability // 10 >= 8:
- passes.ttgpuir.add_pipeline(pm, opt.num_stages, opt.num_war... | Either `capability // 10 >= 8` or `capability // 10 <= 8` should be true, so this change is changing the pipeline. |
intel-xpu-backend-for-triton | github_2023 | python | 637 | intel | whitneywhtsang | @@ -41,7 +41,7 @@ class XPUOptions:
optimize_epilogue: bool = False
enable_fp_fusion: bool = True
allow_fp8e4nv: bool = False
- max_num_imprecise_acc_default: bool = None
+ max_num_imprecise_acc_default: int = 0 # `max_num_imprecise_acc` only applies to fp8 -> fp32 dot on sm_90 for cuda | Are we using it on XPU? |
intel-xpu-backend-for-triton | github_2023 | others | 751 | intel | whitneywhtsang | @@ -173,3 +173,12 @@ llvm.func @triton_gen.2Dblockstore(%ptr : !llvm.ptr, %base_width : i32, %base_he
triton_gen.2Dblockstore %ptr, %base_width, %base_height, %base_pitch, %x, %y, %stored_val {elem_size_in_bits=32, tile_width=8, tile_height=8, v_blocks=1, transpose=false, vnni_transform=false} : (!llvm.ptr, i32, i32... | It is not lowered. |
intel-xpu-backend-for-triton | github_2023 | cpp | 751 | intel | chengjunlu | @@ -8,11 +8,86 @@
#include "mlir/IR/OpDefinition.h"
#include "triton/Dialect/TritonGEN/IR/TritonGENDialect.h"
-#include "llvm/ADT/TypeSwitch.h"
+#include "llvm/ADT/STLExtras.h"
using namespace mlir;
using namespace mlir::triton;
+//===----------------------------------------------------------------------===//... | Can we use a more flexible checking? The 2D block load/store is for general purpose. Just protect the user input fits the HW's limitation is simple. |
intel-xpu-backend-for-triton | github_2023 | cpp | 751 | intel | Dewei-Wang-sh | @@ -8,11 +8,86 @@
#include "mlir/IR/OpDefinition.h"
#include "triton/Dialect/TritonGEN/IR/TritonGENDialect.h"
-#include "llvm/ADT/TypeSwitch.h"
+#include "llvm/ADT/STLExtras.h"
using namespace mlir;
using namespace mlir::triton;
+//===----------------------------------------------------------------------===//... | mlir has "std::optional<int64_t> getConstantIntValue", we can use that alternatively. |
intel-xpu-backend-for-triton | github_2023 | others | 751 | intel | victor-eds | @@ -315,7 +315,7 @@ def TritonGEN_Matrix2DBlockStoreOp : TritonGEN_Op<"2Dblockstore">,
$ptr - the base address of the memory array
$base_width, $base_height, $base_pitch - the shape of the memory array
$x, $y, $tile_width, $tile_height - the starting offsets and shape of the submatrix to load
- $elem_... | ```suggestion
$elem_size_in_bits - 32 for f32, bf32; 16 for f16, int16, bf16; 8 for int8, etc...
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 751 | intel | victor-eds | @@ -321,9 +319,67 @@ createGenISA2DBlockWrite(TritonGEN::Matrix2DBlockStoreOp op,
y, elemSize, tileWidth, tileHeight,
vBlocks, useTranspose, vnniTransform, cache,
storeVal};
- auto callOp = rewriter.create<LLVM::CallOp>(loc,... | ```suggestion
constexpr StringLiteral funcName = "llvm.genx.GenISA.LSC2DBlockPrefetch.isVoid";
``` |
intel-xpu-backend-for-triton | github_2023 | others | 658 | intel | pbchekin | @@ -105,32 +95,33 @@ jobs:
- name: Run core tests
run: |
- conda run -n triton scripts/test-triton.sh --pytorch --ipex
-
- - name: Save conda cache
- if: ${{ steps.conda-cache.outputs.status == 'miss' }}
- uses: ./.github/actions/save
- with:
- path: ${{ ste... | What about using `actions/checkout` for this? |
intel-xpu-backend-for-triton | github_2023 | others | 757 | intel | pbchekin | @@ -75,25 +58,16 @@ jobs:
conda info
conda list -n triton
- - name: Build packages
- if: ${{ steps.packages-cache.outputs.status == 'miss' }}
- run: |
- conda run --no-capture-output -n triton ./scripts/compile-triton.sh --llvm
-
- - name: Save packages cache
- ... | As far as I understand, `pip install -e .` is not necessary if you do `pip install .[tests]`
```suggestion
conda run --no-capture-output -n triton pip install -vvv -e '.[tests]'
``` |
intel-xpu-backend-for-triton | github_2023 | others | 753 | intel | etiotto | @@ -1576,3 +1576,19 @@ module attributes {"triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 4 :
tt.return
}
}
+
+// ----- | Add new test to the gen version of this file |
intel-xpu-backend-for-triton | github_2023 | cpp | 746 | intel | whitneywhtsang | @@ -16,6 +16,7 @@ struct ReturnOpConversion
ConversionPatternRewriter &rewriter) const override {
auto funcOp = op->getParentOfType<LLVM::LLVMFuncOp>();
if (funcOp->hasAttr("nvvm.kernel")) {
+ llvm_unreachable("TODO"); | Can we be more specific of what is the TODO? |
intel-xpu-backend-for-triton | github_2023 | c | 738 | intel | whitneywhtsang | @@ -139,6 +139,10 @@ ze_module_handle_t create_module(ze_context_handle_t context,
ze_device_handle_t device,
uint32_t *binary_ptr, size_t binary_size) {
const char *build_flags = "";
+ // fixme: set it according to register usage by kernel analysi... | [nit]
```suggestion
// FIXME: set it according to register usage by kernel analysis
``` |
intel-xpu-backend-for-triton | github_2023 | c | 738 | intel | etiotto | @@ -139,6 +139,10 @@ ze_module_handle_t create_module(ze_context_handle_t context,
ze_device_handle_t device,
uint32_t *binary_ptr, size_t binary_size) {
const char *build_flags = "";
+ // fixme: set it according to register usage by kernel analysi... | We need user documentation for this new env. variable. |
intel-xpu-backend-for-triton | github_2023 | cpp | 747 | intel | etiotto | @@ -1,3 +1,11 @@
+//===- TargetInfo.cpp - Target dependent information ----------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---... | Remove also `#include "mlir/Dialect/LLVMIR/NVVMDialect.h"` |
intel-xpu-backend-for-triton | github_2023 | cpp | 747 | intel | etiotto | @@ -7,51 +15,14 @@
using namespace mlir;
namespace mlir::triton::intel {
-// Check if the reduction can use a redux op and return the kind.
-static std::optional<NVVM::ReduxKind> matchReduxKind(triton::ReduceOp op,
- int computeCapability) {
- if (computeCapabili... | computeCapability doesn't apply to intel GPU. Can we remove this function ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 747 | intel | etiotto | @@ -1,3 +1,11 @@
+//===- TargetInfo.h - Target dependent information ------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---... | Add some whitespace to follow the usual structure of header files. |
intel-xpu-backend-for-triton | github_2023 | cpp | 693 | intel | etiotto | @@ -0,0 +1,31 @@
+#ifndef TRITON_CONVERSION_TRITONGPU_TO_LLVM_TARGETINFOINTEL_H | Please add the copyright info. We should not have files without the proper copyright. |
intel-xpu-backend-for-triton | github_2023 | cpp | 693 | intel | etiotto | @@ -0,0 +1,177 @@
+#include "TargetInfo.h" | Please add the copyright info. We should not have files without the proper copyright. |
intel-xpu-backend-for-triton | github_2023 | cpp | 693 | intel | etiotto | @@ -0,0 +1,177 @@
+#include "TargetInfo.h"
+#include "Utility.h"
+#include "intel/include/TritonIntelGPUToLLVM/PTXAsmFormat.h"
+#include "mlir/Conversion/LLVMCommon/Pattern.h"
+#include "mlir/Dialect/LLVMIR/LLVMDialect.h"
+#include "mlir/Dialect/LLVMIR/NVVMDialect.h"
+
+using namespace mlir;
+namespace mlir::triton::in... | I fail to understand why we need this code, given that we aren't generating LLVM + NVVM (this is the Intel directory). |
intel-xpu-backend-for-triton | github_2023 | cpp | 734 | intel | Dewei-Wang-sh | @@ -84,6 +84,37 @@ struct GPUIndexIntrinsicOpLowering : public ConvertOpToLLVMPattern<Op> {
}
};
+template <typename SourceOp, typename TargetOp>
+class SingleDimLaunchConfigLowering : public ConvertOpToLLVMPattern<SourceOp> {
+private:
+ unsigned indexBitwidth;
+
+public:
+ explicit SingleDimLaunchConfigLoweri... | typo? |
intel-xpu-backend-for-triton | github_2023 | others | 734 | intel | victor-eds | @@ -127,6 +127,18 @@ def TritonGEN_GridDimZOp : TritonGEN_Op<"grid.dim.z", [NoMemoryEffect]> {
}];
}
+//===----------------------------------------------------------------------===//
+// Subgroup index
+//===----------------------------------------------------------------------===//
+
+def TritonGEN_SubgroupIdOp ... | ```suggestion
def TritonGEN_SubgroupIdOp : TritonGEN_Op<"subgroup.id", [Pure]> {
```
? |
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