repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor4bb/sky130_fd_sc_hs__nor4bb.functional.pp.v | 1,900 | module MODULE1 (
VAR12,
VAR7,
VAR10 ,
VAR4 ,
VAR5 ,
VAR15 ,
VAR3
);
input VAR12;
input VAR7;
output VAR10 ;
input VAR4 ;
input VAR5 ;
input VAR15 ;
input VAR3 ;
wire VAR3 VAR2 ;
wire VAR9 ;
wire VAR11;
nor VAR13 (VAR2 , VAR4, VAR5 );
and VAR8 (VAR9 , VAR2, VAR15, VAR3 );
VAR6 VAR1 (VAR11, VAR9, VAR12, VAR7);
buf VAR14 ... | apache-2.0 |
eSedano/vrudy | rtl/dpth_regfile.v | 3,103 | module MODULE1 (
input wire clk,
input wire [2:0] VAR4,
input wire [2:0] VAR3,
input wire VAR5,
input wire [VAR1] din,
output wire [VAR1] dout
);
reg [VAR1] VAR2 [2:0];
always @(posedge clk)
begin
if (VAR5 == 1'b1)
VAR2[VAR3] <= din;
end
assign dout = VAR2[VAR4];
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfxtp/sky130_fd_sc_hd__dfxtp_4.v | 2,128 | module MODULE1 (
VAR2 ,
VAR8 ,
VAR5 ,
VAR9,
VAR3,
VAR6 ,
VAR7
);
output VAR2 ;
input VAR8 ;
input VAR5 ;
input VAR9;
input VAR3;
input VAR6 ;
input VAR7 ;
VAR1 VAR4 (
.VAR2(VAR2),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR2 ,
VAR8,
VAR5
);
output VAR2 ... | apache-2.0 |
csail-csg/riscy-OOO | procs/asic/bluespec_verilog/RegUN.v | 1,836 | module MODULE1(VAR6, VAR5, VAR2, VAR3);
parameter VAR1 = 1;
input VAR6;
input VAR5;
input [VAR1 - 1 : 0] VAR2;
output [VAR1 - 1 : 0] VAR3;
reg [VAR1 - 1 : 0] VAR3;
VAR3 = {((VAR1 + 1)/2){2'b10}} ;
end
always@(posedge VAR6)
begin
if (VAR5)
VAR3 <= VAR4 VAR2;
end
endmodule | mit |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v2_0_ddr_phy_dqs_found_cal_hr.v | 51,675 | module MODULE1 #
(
parameter VAR80 = 100, parameter VAR108 = 2, parameter VAR67 = 5, parameter VAR37 = "0",
parameter VAR4 = 5, parameter VAR130 = "VAR104", parameter VAR59 = 1, parameter VAR49 = 3, parameter VAR105 = 8, parameter VAR132 = 8, parameter VAR50 = "VAR79", parameter VAR112 = "VAR147", parameter VAR120 = 3,... | bsd-2-clause |
bluespec/Flute | builds/RV32ACIMU_Flute_verilator/Verilog_RTL/mkRISCV_MBox.v | 22,494 | module MODULE1(VAR8,
VAR59,
VAR103,
VAR82,
VAR48,
VAR69,
VAR102,
VAR67,
VAR118,
VAR113,
VAR35,
VAR4,
VAR53,
VAR78,
valid,
word);
input VAR8;
input VAR59;
input [3 : 0] VAR103;
input VAR82;
output VAR48;
input VAR69;
output VAR102;
input VAR67;
output VAR118;
input VAR113;
input [2 : 0] VAR35;
input [31 : 0] VAR4;
input... | apache-2.0 |
rhalstea/cidr_15_fpga_join | probe_engine/verilog/search_list.v | 17,646 | module MODULE1 (
input clk,
input rst,
output VAR34,
input VAR47,
output VAR33,
input [63:0] VAR31,
input [63:0] VAR28,
input VAR40,
output VAR64,
output [47:0] VAR37,
output VAR44,
input VAR13,
input [63:0] VAR70,
input VAR68,
output VAR12,
output [47:0] VAR72,
output VAR50,
input VAR49,
input [63:0] VAR59,
output VAR... | bsd-3-clause |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/tx_multiplexer_32.v | 18,441 | module MODULE1
parameter VAR57 = 9'd32,
parameter VAR8 = 4'd12,
parameter VAR19 = 5, parameter VAR115 = "VAR73"
)
(
input VAR99,
input VAR61,
input [VAR8-1:0] VAR81, input [(VAR8*VAR12)-1:0] VAR110, input [(VAR8*VAR42)-1:0] VAR3, input [(VAR8*VAR57)-1:0] VAR116, output [VAR8-1:0] VAR15, output [VAR8-1:0] VAR117,
input ... | gpl-3.0 |
intelligenttoasters/CPC2.0 | FPGA/rtl/dma.v | 10,462 | module MODULE1 (
input wire VAR37, input wire VAR47,
input wire VAR16,
input wire [3:0] VAR9,
input wire [7:0] VAR35,
output reg [7:0] VAR53,
input wire VAR17,
input wire VAR52,
output wire VAR61,
input wire VAR58, output reg VAR26,
input wire VAR7,
output reg [31:0] VAR14,
output reg [15:0] VAR51,
input wire [15:0] VA... | gpl-3.0 |
vpereira/golden_unicorn | bin/fpga/miner253.v | 2,069 | module MODULE1 (clk, reset, VAR16, VAR9, VAR13, VAR3, VAR11);
parameter VAR4 = 32'd0;
parameter VAR20 = 32'd1;
parameter VAR2 = 32'd0;
input clk, reset;
input [255:0] VAR16;
input [95:0] VAR9;
output reg [31:0] VAR13, VAR11, VAR3;
reg [31:0] VAR19;
wire [255:0] VAR15;
wire [31:0] VAR6;
reg VAR5, VAR1, VAR8, VAR14;
VAR1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/fill/sky130_fd_sc_hdll__fill.pp.blackbox.v | 1,181 | module MODULE1 (
VAR4,
VAR2,
VAR3 ,
VAR1
);
input VAR4;
input VAR2;
input VAR3 ;
input VAR1 ;
endmodule | apache-2.0 |
google/CFU-Playground | proj/example_cfu_v/cfu.v | 2,122 | module MODULE1 (
input VAR7,
output VAR11,
input [9:0] VAR4,
input [31:0] VAR8,
input [31:0] VAR6,
output VAR5,
input VAR2,
output [31:0] VAR1,
input clk,
input reset
);
assign VAR5 = VAR7;
assign VAR11 = VAR2;
wire [31:0] VAR9;
assign VAR9[31:0] = VAR8[7:0] + VAR6[7:0] +
VAR8[15:8] + VAR6[15:8] +
VAR8[23:16] + VAR6[23... | apache-2.0 |
alonso193/proyecto1 | sintetizado/CMDblock.v | 264,059 | module \VAR72\MODULE6\VAR95=32 (VAR49, VAR90, VAR98, VAR121, VAR41, VAR81);
wire [8:0] 000;
wire [31:0] 001;
wire 002;
wire 003;
wire 004;
wire 005;
wire 006;
wire 007;
wire 008;
wire 009;
wire 010;
wire 011;
wire 012;
wire 013;
wire 014;
wire 015;
wire 016;
wire 017;
wire 018;
wire 019;
wire 020;
wire 021;
wire 022;
w... | gpl-3.0 |
vipinkmenon/scas | hw/fpga/source/memory_if/mig_7series_v1_8_ddr_calib_top.v | 82,384 | module MODULE1 #
(
parameter VAR178 = 100,
parameter VAR87 = 2, parameter VAR111 = 2500, parameter VAR54 = 3333, parameter VAR287 = 3, parameter VAR282 = "VAR338", parameter VAR19 = 8, parameter VAR376 = 4,
parameter VAR64 = 3,
parameter VAR75 = "VAR3", parameter VAR229 = 4'hc,
parameter VAR248 = 4'hf,
parameter VAR384... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/inv/sky130_fd_sc_ls__inv.functional.v | 1,225 | module MODULE1 (
VAR4,
VAR2
);
output VAR4;
input VAR2;
wire VAR1;
not VAR3 (VAR1, VAR2 );
buf VAR5 (VAR4 , VAR1 );
endmodule | apache-2.0 |
romovs/xula-lib-verilog | Clk.v | 4,991 | module MODULE1 (VAR30, VAR47, VAR18);
parameter VAR19 = 25;
parameter VAR45 = 3;
parameter real VAR36 = 12.0;
input VAR30;
output VAR47;
output VAR18;
localparam real VAR24 = 1000.0/VAR36;
VAR11
.VAR32(2.0), .VAR42(VAR45), .VAR6(VAR19), .VAR39("VAR7"), .VAR34(VAR24), .VAR16("VAR20"), .VAR23("1X"), .VAR1("VAR2"), .VAR10... | gpl-2.0 |
CospanDesign/nysa-tx1-pcie-platform | tx1_pcie/slave/wb_tx1_pcie/rtl/xilinx/pcie_7x_v1_11_0_pipe_drp.v | 38,892 | module MODULE1 #
(
parameter VAR91 = "VAR181", parameter VAR169 = "3.0", parameter VAR168 = "VAR34", parameter VAR103 = "VAR111", parameter VAR121 = "VAR126", parameter VAR94 = "VAR34", parameter VAR175 = "VAR126", parameter VAR187 = 0, parameter VAR206 = 0, parameter VAR144 = 2'd1, parameter VAR49 = 5'd21
)
(
input VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai.functional.pp.v | 2,184 | module MODULE1 (
VAR10 ,
VAR12,
VAR1,
VAR2 ,
VAR18 ,
VAR8,
VAR11,
VAR19 ,
VAR13
);
output VAR10 ;
input VAR12;
input VAR1;
input VAR2 ;
input VAR18 ;
input VAR8;
input VAR11;
input VAR19 ;
input VAR13 ;
wire VAR5 ;
wire VAR3 ;
wire VAR15 ;
wire VAR6;
nand VAR17 (VAR5 , VAR1, VAR12 );
or VAR4 (VAR3 , VAR18, VAR2 );
nand... | apache-2.0 |
sehugg/8bitworkshop | presets/verilog/tile_renderer.v | 4,184 | module MODULE2(clk, reset, VAR14, VAR3,
VAR2,
VAR29, VAR22, VAR8,
VAR5, VAR26);
input clk, reset;
input [8:0] VAR14;
input [8:0] VAR3;
output [3:0] VAR2;
parameter VAR20 = 272;
output reg [15:0] VAR29;
input [15:0] VAR22;
output reg VAR8;
output [10:0] VAR5;
input [7:0] VAR26;
reg [7:0] VAR13 = 8'h7e; reg [15:0] VAR24;... | gpl-3.0 |
ptracton/wb_soc_template | rtl/uart16550/rtl/verilog/uart_sync_flops.v | 5,617 | module MODULE1
(
VAR4,
VAR1,
VAR9,
VAR3,
VAR7,
VAR8
);
parameter VAR2 = 1;
parameter VAR5 = 1'b0;
input VAR4; input VAR1; input VAR9; input VAR3; input [VAR2-1:0] VAR7; output [VAR2-1:0] VAR8;
reg [VAR2-1:0] VAR8;
reg [VAR2-1:0] VAR6;
always @ (posedge VAR1 or posedge VAR4)
begin
if (VAR4)
VAR6 <= {VAR2{VAR5}};
end
els... | mit |
bangonkali/quartus-sockit | soc_system/synthesis/submodules/hps_sdram_p0_altdqdqs.v | 6,912 | module MODULE1 (
VAR74,
VAR59,
VAR33,
VAR76,
VAR72,
VAR10,
VAR8,
VAR47,
VAR29,
VAR17,
VAR79,
VAR4,
VAR73,
VAR78,
VAR31,
VAR16,
VAR91,
VAR65,
VAR37,
VAR21,
VAR82,
VAR67,
VAR92,
VAR90,
VAR58,
VAR35,
VAR77,
VAR9,
VAR66,
VAR81,
VAR87,
VAR32,
VAR7,
VAR5,
VAR48,
VAR20,
VAR22,
VAR83
);
input [7-1:0] VAR83;
input VAR74;
input ... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_4.functional.v | 1,746 | module MODULE1( VAR12, VAR1, VAR17, VAR23, VAR6 );
input VAR1, VAR23, VAR17;
output VAR6, VAR12;
wire VAR4;
and VAR21( VAR4, VAR1, VAR23 );
wire VAR8;
and VAR18( VAR8, VAR1, VAR17 );
wire VAR3;
and VAR10( VAR3, VAR23, VAR17 );
or VAR5( VAR6, VAR4, VAR8, VAR3 );
wire VAR2;
and VAR16( VAR2, VAR1, VAR23, VAR17 );
wire VAR... | apache-2.0 |
twlostow/dsi-shield | hdl/rtl/framebuffer/video_mixer.v | 6,423 | module MODULE1
(
input VAR22,
input VAR39,
input VAR61,
output VAR65,
input VAR14,
input [47:0] VAR41,
input VAR4,
output VAR13,
input VAR18,
input VAR40,
input VAR58,
input [47:0] VAR62,
input VAR12,
input VAR17,
input VAR63,
output VAR20,
output [47:0] VAR30,
output reg VAR37,
input VAR10,
output [7:0] VAR43,
input [... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp.symbol.v | 1,373 | module MODULE1 (
input VAR5 ,
output VAR6 ,
input VAR1 ,
input VAR9 ,
input VAR2
);
supply1 VAR7;
supply0 VAR4;
supply1 VAR8 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/lm32/rtl/lm32_decoder.v | 19,228 | module MODULE1 (
VAR104,
VAR137,
VAR45,
VAR115,
VAR1,
VAR29,
VAR18,
VAR168,
VAR14,
VAR27,
VAR34,
VAR80,
VAR101,
VAR136,
VAR147,
VAR67,
VAR107,
VAR86,
VAR2,
VAR161,
VAR66,
VAR46,
VAR146,
VAR26,
VAR24,
VAR135,
VAR59,
VAR92,
VAR132,
VAR36,
VAR105,
VAR133,
VAR82,
VAR155,
VAR44,
VAR21,
VAR3,
VAR88,
VAR94,
VAR134,
VAR103,
VA... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi.symbol.v | 1,468 | module MODULE1 (
input VAR6,
input VAR5,
input VAR7 ,
input VAR8 ,
output VAR3
);
supply1 VAR9;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
alexforencich/xfcp | lib/eth/example/DE2-115/fpga/rtl/hex_display.v | 2,063 | module MODULE1 #(
parameter VAR2 = 0
)
(
input wire [3:0] in,
input wire enable,
output wire [6:0] out
);
reg [6:0] VAR1;
always @* begin
VAR1 <= 7'b0000000;
if (enable) begin
case (in)
4'h0: VAR1 <= 7'b0111111;
4'h1: VAR1 <= 7'b0000110;
4'h2: VAR1 <= 7'b1011011;
4'h3: VAR1 <= 7'b1001111;
4'h4: VAR1 <= 7'b1100110;
4'h5... | mit |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_3L_032bits.v | 1,917 | module MODULE2 (
clk,
VAR27, VAR17, VAR14, VAR16, VAR19, VAR5, VAR11, VAR10,
sum,
);
input clk;
input [VAR23+0-1:0] VAR27, VAR17, VAR14, VAR16, VAR19, VAR5, VAR11, VAR10;
output [VAR23 :0] sum;
reg [VAR23 :0] sum;
wire [VAR23+3-1:0] VAR33;
wire [VAR23+2-1:0] VAR18, VAR20;
wire [VAR23+1-1:0] VAR6, VAR24, VAR28, VAR30;
r... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a2bb2oi/sky130_fd_sc_hd__a2bb2oi_4.v | 2,477 | module MODULE1 (
VAR9 ,
VAR4,
VAR3,
VAR5 ,
VAR10 ,
VAR7,
VAR2,
VAR1 ,
VAR8
);
output VAR9 ;
input VAR4;
input VAR3;
input VAR5 ;
input VAR10 ;
input VAR7;
input VAR2;
input VAR1 ;
input VAR8 ;
VAR6 VAR11 (
.VAR9(VAR9),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR8(VA... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/velocityControlHdl_Convert_Data_Type1_block1.v | 1,139 | module MODULE1
(
VAR2,
VAR3
);
input signed [35:0] VAR2; output signed [17:0] VAR3;
wire signed [17:0] VAR1;
assign VAR1 = VAR2[35:18];
assign VAR3 = VAR1;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfbbp/sky130_fd_sc_hdll__sdfbbp.functional.v | 2,312 | module MODULE1 (
VAR8 ,
VAR12 ,
VAR2 ,
VAR21 ,
VAR15 ,
VAR11 ,
VAR13 ,
VAR6
);
output VAR8 ;
output VAR12 ;
input VAR2 ;
input VAR21 ;
input VAR15 ;
input VAR11 ;
input VAR13 ;
input VAR6;
wire VAR10 ;
wire VAR19 ;
wire VAR20 ;
wire VAR16;
not VAR14 (VAR10 , VAR6 );
not VAR7 (VAR19 , VAR13 );
VAR1 VAR9 (VAR16, VAR2, VA... | apache-2.0 |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/system/synthesis/submodules/system_acl_iface_pll.v | 2,082 | module MODULE1(
input wire VAR36,
input wire rst,
output wire VAR8,
output wire VAR54
);
VAR46 #(
.VAR6("false"),
.VAR48("50.0 VAR64"),
.VAR40("VAR14"),
.VAR63(1),
.VAR18("100.000000 VAR64"),
.VAR42("0 VAR52"),
.VAR41(50),
.VAR50("0 VAR64"),
.VAR53("0 VAR52"),
.VAR55(50),
.VAR4("0 VAR64"),
.VAR38("0 VAR52"),
.VAR11(50)... | mit |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Mux4x1_8_0_1/RAT_Mux4x1_8_0_1_stub.v | 1,339 | module MODULE1(VAR6, VAR4, VAR3, VAR2, VAR1, VAR5)
;
input [7:0]VAR6;
input [7:0]VAR4;
input [7:0]VAR3;
input [7:0]VAR2;
input [1:0]VAR1;
output [7:0]VAR5;
endmodule | mit |
hanw/sonic-lite | hw/verilog/scramble/scrambler.v | 2,306 | module MODULE1 # (
parameter VAR4 = 512
)(
input clk,VAR1,VAR3,
input [VAR4-1:0] din, output reg [VAR4-1:0] dout
);
localparam VAR2 = 58'h3ffffffffffffff;
reg [57:0] VAR5 = VAR2;
wire [VAR4+58-1:0] VAR6;
assign VAR6 [57:0] = VAR5;
genvar VAR7;
generate
for (VAR7=58; VAR7<VAR4+58; VAR7=VAR7+1) begin : VAR8
assign VAR6[V... | mit |
nishtahir/arty-blaze | src/bd/system/ip/system_mig_7series_0_0/system_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_0_ddr_byte_group_io.v | 21,896 | module MODULE1 #(
parameter VAR118 = 12'b111111111111,
parameter VAR103 = 12'b000000000000,
parameter VAR165 = "VAR82",
parameter VAR144 = "VAR178",
parameter VAR174 = 4,
parameter VAR99 = "VAR62",
parameter VAR2 = 00,
parameter VAR168 = "VAR138",
parameter VAR28 = 1,
parameter real VAR41 = 2500.0,
parameter VAR130 = 1... | apache-2.0 |
gtaylormb/fpga_nes | hw/src/cmn/uart/uart_baud_clk.v | 2,419 | module MODULE1
parameter VAR2 = 50000000,
parameter VAR4 = 19200,
parameter VAR3 = 16
)
(
input wire clk,
input wire reset,
output wire VAR7
);
localparam [15:0] VAR5 = (VAR2 / VAR4) / VAR3;
reg [15:0] VAR6;
wire [15:0] VAR1;
always @(posedge clk, posedge reset)
begin
if (reset)
VAR6 <= 0;
end
else
VAR6 <= VAR1;
end
as... | bsd-2-clause |
bluespec/Flute | builds/RV32ACDFIMSU_Flute_iverilog/Verilog_RTL/mkFPR_RegFile.v | 7,048 | module MODULE1(VAR55,
VAR46,
VAR6,
VAR62,
VAR65,
VAR27,
VAR34,
VAR59,
VAR72,
VAR16,
VAR10,
VAR2,
VAR44,
VAR39,
VAR8,
VAR33,
VAR20);
input VAR55;
input VAR46;
input VAR6;
output VAR62;
input VAR65;
output VAR27;
input [4 : 0] VAR34;
output [63 : 0] VAR59;
input [4 : 0] VAR72;
output [63 : 0] VAR16;
input [4 : 0] VAR10;
... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_2.behavioral.v | 2,716 | module MODULE1( VAR1, VAR19, VAR5, VAR2 );
input VAR5, VAR19, VAR1;
output VAR2;
reg VAR14;
VAR7 VAR9(.VAR1(VAR1),.VAR19(VAR19),.VAR5(VAR5),.VAR2(VAR2),.VAR14(VAR14));
VAR7 VAR6(.VAR1(VAR1),.VAR19(VAR19),.VAR5(VAR5),.VAR2(VAR2),.VAR14(VAR14));
not VAR20(VAR22,VAR19);
not VAR4(VAR17,VAR1);
and VAR10(VAR3,VAR17,VAR22);
n... | apache-2.0 |
makestuff/swled | fifo/verilog/fifo-gen/fifo_wrapper_xilinx.v | 1,677 | module
MODULE1(
input wire VAR8,
output wire[7:0] VAR16,
input wire[7:0] VAR14,
input wire VAR17,
output wire VAR2,
output wire[7:0] VAR15,
output wire VAR3,
input wire VAR6
);
wire VAR11;
wire VAR5;
assign VAR2 = !VAR11;
assign VAR3 = !VAR5;
VAR9 VAR12(
.clk(VAR8),
.VAR13(VAR16),
.din(VAR14),
.VAR1(VAR17),
.VAR10(VAR1... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/ccx/rtl/cpx_dp_maca_l.v | 4,558 | module MODULE1(
VAR7, VAR8, VAR10,
VAR26, VAR11, VAR4,
VAR18, VAR6, VAR32, VAR28,
VAR30, VAR31
);
output [149:0] VAR7; output VAR8;
output VAR10;
input VAR26; input VAR11; input VAR4; input VAR18; input VAR6; input [149:0] VAR32; input VAR28;
input VAR30;
input VAR31;
wire VAR2;
wire [149:0] VAR22;
wire [149:0] VAR3, V... | gpl-2.0 |
monotone-RK/FACE | IEICE-Trans/bandwidth/PCIe/src/ip_pcie/source/PCIeGen2x8If128_gtp_cpllpd_ovrd.v | 4,122 | module MODULE1 (
input VAR2,
output VAR1,
output VAR4
);
reg [95:0] VAR5 = 96'hFFFFFFFFFFFFFFFFFFFFFFFF;
reg [127:0] VAR3 = 128'h000000000000000000000000000000FF;
always @(posedge VAR2)
begin
VAR5 <= {VAR5[94:0], 1'b0};
VAR3 <= {VAR3[126:0], 1'b0};
end
assign VAR1 = VAR5[95];
assign VAR4 = VAR3[127];
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkbuf/sky130_fd_sc_hs__clkbuf.pp.symbol.v | 1,229 | module MODULE1 (
input VAR4 ,
output VAR3 ,
input VAR1,
input VAR2
);
endmodule | apache-2.0 |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_timer/db/ip/niosii/niosii.v | 52,152 | module MODULE1 (
input wire VAR100, output wire [7:0] VAR53, input wire VAR275, input wire VAR183, output wire VAR262 );
wire VAR46; wire VAR180; wire VAR13; wire [31:0] VAR162; wire VAR225; wire VAR196; wire [17:0] VAR19; wire [3:0] VAR179; wire VAR185; wire VAR265; wire [31:0] VAR244; wire [31:0] VAR209; wire VAR235;... | mit |
UCR-CS179-SUMMER2014/NES_FPGA | source/NES_FPGA/nios_system_backup/video_character_buffer_with_dma_0.v | 13,401 | module MODULE1 (
clk,
reset,
VAR6,
VAR12,
VAR105,
VAR54,
VAR50,
VAR79,
VAR82,
VAR30,
VAR44,
VAR103,
VAR64,
VAR102,
VAR67,
VAR101,
VAR15,
VAR78,
VAR108,
VAR41,
VAR18,
VAR35,
VAR95
);
parameter VAR77 = 8;
parameter VAR68 = 0;
parameter VAR31 = 13;
parameter VAR90 = 8192;
parameter VAR75 = 640;
parameter VAR87 = 480;
inpu... | mit |
eda-globetrotter/MarcheProcessor | processor/spare/build1/piso.v | 7,359 | module MODULE1(VAR16, VAR11, VAR15, VAR18, VAR7, clk);
output VAR16;
output VAR11;
input [7:0] VAR15;
input clk;
input VAR7;
input VAR18;
reg VAR11; reg VAR16; reg VAR13; reg VAR10; reg VAR4; reg VAR12; reg VAR2; reg VAR5; reg VAR8;
reg VAR9; reg VAR20; reg VAR17; reg VAR19; reg VAR3; reg VAR14;
always @(~VAR7)
begin
V... | mit |
everskar2013/PentiumX | Hardware/Code/BTN_Anti_jitter.v | 1,306 | module MODULE1(
clk,
VAR3,
VAR1,
VAR2,
VAR4
);
input wire clk;
input wire [ 3: 0] VAR3;
input wire [ 7: 0] VAR1;
output reg [ 3: 0] VAR2 = 0;
output reg [ 7: 0] VAR4 = 0;
reg [31: 0] counter = 0;
always @(posedge clk) begin
if ( counter > 0 ) begin
if ( counter < 100000 )
counter <= counter+1;
end
else
begin
counter <=... | mit |
vvk/sysrek | rgb2hsv/rgb2hsv.v | 7,634 | module MODULE1(
input clk,
input VAR57,
input [7:0] VAR97,
input [7:0] VAR36,
input [7:0] VAR21,
input VAR16, input VAR14, input VAR45,
output [7:0] VAR29,
output [7:0] VAR13,
output [7:0] VAR96,
output VAR30, output VAR88, output VAR77
);
wire [7:0] VAR81;
wire [7:0] VAR61;
wire [7:0] VAR40;
wire [7:0] VAR7;
wire [7:0... | gpl-2.0 |
dhytxz/PolyPC | hardware/ip_repo/hapara_axis_id_generator_1.0/hdl/hapara_axis_id_generator_v1_0_M00_AXIS.v | 6,175 | module MODULE1 #
(
parameter integer VAR16 = 32
)
(
input wire VAR12,
output wire VAR11,
input wire [VAR16 - 1 : 0] VAR7,
input wire [VAR16 - 1 : 0] VAR27,
input wire [VAR16 - 1 : 0] VAR29,
input wire VAR8,
input wire VAR24,
output wire VAR3,
output wire [VAR16-1 : 0] VAR2,
output wire VAR14,
input wire VAR21
);
localp... | gpl-2.0 |
peteasa/parallella-fpga | AdiHDLLib/library/common/ad_iqcor.v | 5,012 | module MODULE1 (
clk,
valid,
VAR8,
VAR7,
VAR21,
VAR29,
VAR2,
VAR23,
VAR27);
parameter VAR12 = 0;
input clk;
input valid;
input [15:0] VAR8;
input [15:0] VAR7;
output VAR21;
output [15:0] VAR29;
input VAR2;
input [15:0] VAR23;
input [15:0] VAR27;
reg VAR22 = 'd0;
reg [15:0] VAR26 = 'd0;
reg [15:0] VAR6 = 'd0;
reg [33:0]... | lgpl-3.0 |
frisnit/fpga-noise | verilog/noise_generator.v | 1,319 | module MODULE1(clk,reset,VAR5);
parameter VAR3 = 32'b10101011101010111010101110101011; parameter VAR2 = 31'b0000000000000000000000001100010;
input clk;
input reset;
output VAR5;
reg [31:0] VAR1;
VAR4 VAR1 = VAR3;
always @(posedge clk)
begin
if(!reset)
begin
if(VAR1[31])
VAR1[31:1] <= VAR1[30:0]^VAR2;
end
else
VAR1[31:1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv3sd3/sky130_fd_sc_ls__clkdlyinv3sd3.blackbox.v | 1,323 | module MODULE1 (
VAR4,
VAR6
);
output VAR4;
input VAR6;
supply1 VAR3;
supply0 VAR2;
supply1 VAR1 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
sh-chris110/chris | FPGA/Math/Qsys/nios_design/synthesis/submodules/nios_design_timer_0.v | 4,992 | module MODULE1 (
address,
VAR19,
clk,
VAR5,
VAR4,
VAR10,
irq,
VAR6
)
;
output irq;
output [ 15: 0] VAR6;
input [ 2: 0] address;
input VAR19;
input clk;
input VAR5;
input VAR4;
input [ 15: 0] VAR10;
wire VAR18;
wire VAR20;
reg VAR8;
wire VAR15;
reg VAR17;
wire VAR12;
wire [ 24: 0] VAR9;
reg VAR21;
wire VAR3;
wire VAR14;... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_ground_hvc_wpad/sky130_fd_io__top_ground_hvc_wpad.pp.symbol.v | 1,778 | module MODULE1 (
inout VAR16 ,
inout VAR2 ,
inout VAR12 ,
inout VAR14 ,
inout VAR17 ,
inout VAR7 ,
inout VAR13 ,
inout VAR3,
inout VAR9 ,
inout VAR10 ,
inout VAR6 ,
inout VAR15 ,
inout VAR11 ,
inout VAR1 ,
inout VAR8 ,
inout VAR5 ,
inout VAR4
);
endmodule | apache-2.0 |
CospanDesign/nysa-artemis-pcie-platform | artemis_pcie/slave/wb_artemis_pcie_platform/rtl/pcie_ingress.v | 19,330 | module MODULE1 (
input clk,
input rst,
output reg VAR81,
input [31:0] VAR24,
input [3:0] VAR35,
input VAR98,
input VAR85,
output reg [31:0] VAR93,
output reg [31:0] VAR30,
output reg [31:0] VAR102,
output reg [31:0] VAR96,
output reg [31:0] VAR1,
output reg [31:0] VAR5,
output reg [31:0] VAR79,
output reg VAR64,
output... | mit |
jhol/butterflylogic | rtl/shifter.v | 2,747 | module MODULE1 #(
parameter integer VAR6 = 32
)(
input wire clk,
input wire rst,
input wire VAR17,
input wire VAR16,
input wire [VAR6-1:0] VAR4,
input wire VAR7,
output wire VAR5,
input wire [VAR6-1:0] VAR8,
output wire VAR20,
input wire VAR1,
output wire [VAR6-1:0] VAR9
);
localparam VAR3 = VAR11(VAR6);
wire VAR15;
as... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_gpio_ovtv2/sky130_fd_io__top_gpio_ovtv2.behavioral.v | 49,416 | module MODULE1 ( VAR61, VAR29, VAR84, VAR77, VAR70,
VAR82, VAR33, VAR88, VAR79, VAR34,
VAR55, VAR4, VAR87, VAR5, VAR28, VAR14, VAR18, VAR3, VAR35, VAR81,
VAR56, VAR36, VAR26, VAR66, VAR75, VAR80, VAR16, VAR24, VAR89, VAR25 );
input VAR75;
input VAR66;
input VAR81;
input VAR28;
input VAR14;
input VAR18;
input VAR3;
inpu... | apache-2.0 |
dtysky/FPGA-Imaging-Library | Connector/ColorRGB16toRGB24/srcs/ColorRGB16toRGB24.v | 1,394 | module MODULE1(
input[15 : 0] VAR2,
output[23 : 0] VAR1
);
assign VAR1[23 : 16] = {VAR2[15 : 11], VAR2[15 : 13]};
assign VAR1[15:8] = {VAR2[10 : 5], VAR2[10 : 9]};
assign VAR1[7:0] = {VAR2[4 : 0], VAR2[4 : 2]};
endmodule | lgpl-2.1 |
zambreno/RCL | sccCyGraph/verilog/cae_pers.v | 82,296 | module MODULE1 (
input VAR100,
input clk,
input VAR177,
input VAR32,
input VAR175,
input [1:0] VAR81,
input VAR1,
output VAR61,
output VAR165,
input [31:0] VAR229,
input [63:0] VAR233,
input VAR143,
output [17:0] VAR125,
output [15:0] VAR214,
output [63:0] VAR204,
output VAR55,
output VAR154,
output VAR98,
output VAR23... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_2.behavioral.pp.v | 3,372 | module MODULE1( VAR10, VAR8, VAR9, VAR4, VAR3, VAR6, VAR2, VAR11 );
input VAR3, VAR6, VAR4, VAR8, VAR9;
inout VAR2, VAR11;
output VAR10;
VAR1 VAR5(.VAR10(VAR10),.VAR8(VAR8),.VAR9(VAR9),.VAR4(VAR4),.VAR3(VAR3),.VAR6(VAR6),.VAR2(VAR2),.VAR11(VAR11));
VAR1 VAR7(.VAR10(VAR10),.VAR8(VAR8),.VAR9(VAR9),.VAR4(VAR4),.VAR3(VAR3)... | apache-2.0 |
liqimai/ZPC | PersonalComputer/Coprocessor0.v | 1,352 | module MODULE1(
input clk,
input[4:0] VAR5,
input[31:0] VAR4,
input VAR1,
input[31:0] VAR13,
input VAR7,
output VAR2,
output[31:0] VAR6,
output reg[31:0] VAR8
);
parameter VAR11 = 5'h0;
parameter VAR14 = 5'h1;
parameter VAR10 = 5'h2;
reg[31:0] VAR3;
reg[31:0] VAR9;
reg[31:0] VAR12; | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_2.behavioral.pp.v | 8,945 | module MODULE1( VAR86, VAR7, VAR34, VAR21, VAR3, VAR69, VAR8 );
input VAR86, VAR7, VAR21, VAR34;
inout VAR69, VAR8;
output VAR3;
reg VAR68;
VAR88 VAR52(.VAR86(VAR86),.VAR7(VAR7),.VAR34(VAR34),.VAR21(VAR21),.VAR3(VAR3),.VAR69(VAR69),.VAR8(VAR8),.VAR68(VAR68));
VAR88 VAR12(.VAR86(VAR86),.VAR7(VAR7),.VAR34(VAR34),.VAR21(V... | apache-2.0 |
sh-chris110/chris | FPGA/chris.system_ok/Qsys/soc_design/synthesis/submodules/soc_design_SystemID.v | 2,203 | module MODULE1 (
address,
VAR1,
VAR3,
VAR2
)
;
output [ 31: 0] VAR2;
input address;
input VAR1;
input VAR3;
wire [ 31: 0] VAR2;
assign VAR2 = address ? 1499934064 : 255;
endmodule | gpl-2.0 |
omicronns/studies-sys-rek | lab4/zlozony/ipcore_dir/sum_18_19/sum_18_19.v | 35,975 | module MODULE1 (
clk, VAR146, VAR270, VAR376, VAR55
);
input clk;
input VAR146;
input [17 : 0] VAR270;
input [18 : 0] VAR376;
output [19 : 0] VAR55;
wire \VAR108/VAR173 ;
wire \VAR108/VAR162 ;
wire \VAR108/VAR367 ;
wire \VAR108/VAR242 ;
wire \VAR108/VAR16 ;
wire \VAR108/VAR119 ;
wire \VAR108/VAR200 ;
wire \VAR108/VAR23... | mit |
rkrajnc/minimig-de1 | rtl/mor1kx/mor1kx_wb_mux_espresso.v | 1,561 | module MODULE1
(
VAR3,
clk, rst, VAR7, VAR8, VAR5, VAR4,
VAR2, VAR1, VAR6, VAR10
);
parameter VAR9 = 32;
input clk, rst;
input [VAR9-1:0] VAR7;
input [VAR9-1:0] VAR8;
input [VAR9-1:0] VAR5;
input [VAR9-1:0] VAR4;
input [VAR9-1:0] VAR2;
output [VAR9-1:0] VAR3;
input VAR1;
input VAR6;
input VAR10;
assign VAR3 = VAR6 ? VA... | gpl-3.0 |
htuNCSU/MmcCommunicationVerilog | DE2_115_MASTER/source_code/phyIniCommand1.v | 1,169 | module MODULE1
(
input [(VAR2-1):0] VAR1,
input [(VAR7-1):0] addr,
input VAR3, clk,
output [(VAR2-1):0] VAR4
);
reg [VAR2-1:0] VAR6[2**VAR7-1:0];
reg [VAR7-1:0] VAR5;
begin | gpl-3.0 |
ptracton/Picoblaze | library/wb_uart/raminfr.v | 6,129 | module MODULE1
(clk, VAR8, VAR2, VAR5, VAR1, VAR6);
parameter VAR3 = 4;
parameter VAR7 = 8;
parameter VAR4 = 16;
input clk;
input VAR8;
input [VAR3-1:0] VAR2;
input [VAR3-1:0] VAR5;
input [VAR7-1:0] VAR1;
output [VAR7-1:0] VAR6;
reg [VAR7-1:0] VAR9 [VAR4-1:0];
wire [VAR7-1:0] VAR6;
wire [VAR7-1:0] VAR1;
wire [VAR3-1:0]... | mit |
twlostow/dsi-shield | hdl/rtl/sysctl/sysctl_regs.v | 4,598 | module MODULE1
parameter VAR21 = 26,
parameter VAR24 = 1, parameter VAR17 = 2
)
(
input VAR15,
input VAR22,
input [31:0] VAR8,
input [31:0] VAR11,
output reg [31:0] VAR37,
input [3:0] VAR3,
input VAR28,
input VAR27,
input VAR20,
output VAR34,
output VAR12,
output VAR31,
output VAR10,
output [VAR21-1:0] VAR26,
output [V... | lgpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/spi_engine/spi_engine_offload/spi_engine_offload.v | 4,069 | module MODULE1 (
input VAR23,
input VAR21,
input [15:0] VAR11,
input VAR41,
input [7:0] VAR19,
input VAR14,
output VAR44,
input VAR2,
input VAR10,
input VAR36,
input VAR9,
output VAR26,
input VAR4,
output [15:0] VAR35,
output VAR42,
input VAR40,
output [7:0] VAR1,
input VAR31,
output VAR7,
input [7:0] VAR15,
input VAR3... | gpl-3.0 |
OpenSoCPlus/hight_crypto_core | rtl/HIGHT_CORE_TOP.v | 5,471 | module MODULE1(
VAR18 ,
clk ,
VAR10 ,
VAR33 ,
VAR20 ,
VAR19 ,
VAR29 ,
VAR2 ,
VAR17 ,
VAR24 ,
VAR25
);
input VAR18 ;
input clk ;
input VAR10 ;
input[127:0] VAR33 ;
input VAR20 ;
input VAR19 ;
input VAR29 ;
input[63:0] VAR2 ;
output VAR17 ;
output[63:0] VAR24 ;
output VAR25 ;
wire[31:0] VAR9 ;
wire[2:0] VAR31 ;
wire VAR7... | lgpl-2.1 |
BigEd/beeb816 | rtl/cpld_jnr.v | 1,361 | module MODULE1 (
input [15:0] VAR12,
input [1:0] VAR8,
input VAR1,
output VAR6,
output VAR11,
output VAR7,
output [11:0] VAR13
);
reg [11:0] VAR4;
assign VAR13 = VAR4;
assign VAR6 = (VAR9) ? (VAR12==VAR10) : 1'b0;
assign VAR11 = (VAR2)? (VAR12==VAR3) : (VAR12==VAR5);
assign VAR7 = (VAR12[15:4]==12'hFE4) || (VAR12[15:9]... | lgpl-2.1 |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_spigpioport.v | 5,835 | module MODULE1(
input VAR55,
input reset,
input VAR43,
output VAR62,
input VAR15,
input VAR54,
output VAR71,
input VAR39,
input VAR16,
output VAR74,
input VAR1,
input VAR52,
output VAR38,
input VAR36,
input VAR21,
input VAR32,
input VAR25,
input VAR66,
input VAR56,
input VAR24,
output VAR22,
output VAR48,
output VAR27,... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/inv/sky130_fd_sc_hd__inv_4.v | 1,995 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR4,
VAR3,
VAR2 ,
VAR7
);
output VAR1 ;
input VAR5 ;
input VAR4;
input VAR3;
input VAR2 ;
input VAR7 ;
VAR6 VAR8 (
.VAR1(VAR1),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR1,
VAR5
);
output VAR1;
input VAR5;
supply1 VAR4;
supply0 VAR3;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o2bb2ai/sky130_fd_sc_hdll__o2bb2ai.pp.blackbox.v | 1,416 | module MODULE1 (
VAR1 ,
VAR6,
VAR3,
VAR2 ,
VAR4 ,
VAR8,
VAR9,
VAR7 ,
VAR5
);
output VAR1 ;
input VAR6;
input VAR3;
input VAR2 ;
input VAR4 ;
input VAR8;
input VAR9;
input VAR7 ;
input VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfbbp/sky130_fd_sc_hs__dfbbp.symbol.v | 1,431 | module MODULE1 (
input VAR7 ,
output VAR5 ,
output VAR3 ,
input VAR6,
input VAR4 ,
input VAR1
);
supply1 VAR8;
supply0 VAR2;
endmodule | apache-2.0 |
jhennessy/parallella-hw-old | fpga/hdl/axi/axi_slave_rd.v | 12,737 | module MODULE1 (
VAR32, VAR28, VAR23, VAR107, VAR93, VAR66, VAR68,
VAR78, VAR47, VAR80,
VAR15, VAR104, VAR16,
VAR87,
VAR91, VAR82, reset, VAR83, VAR52, VAR62, VAR89, VAR75, VAR79,
VAR33, VAR76, VAR106, VAR39, VAR38,
VAR18, VAR51, VAR90,
VAR11, VAR14, VAR59,
VAR101
);
parameter VAR13 = 12; parameter VAR2 = 32; parameter... | gpl-3.0 |
ptracton/pmodacl2 | rtl/fifo4.v | 4,296 | module MODULE1(clk, rst, VAR12, din, VAR5, dout, VAR3, VAR8, VAR9);
parameter VAR1 = 8;
input clk, rst;
input VAR12;
input [VAR1:1] din;
input VAR5;
output [VAR1:1] dout;
input VAR3;
output VAR8, VAR9;
reg [VAR1:1] VAR13[0:3];
reg [1:0] VAR7=0;
reg [1:0] VAR2=0;
wire [1:0] VAR6;
wire [1:0] VAR10;
wire [1:0] VAR4;
wire ... | mit |
SymbiFlow/yosys-symbiflow-plugins | ql-qlf-plugin/qlf_k6n10f/ffs_map.v | 12,798 | module \VAR72 (VAR69, VAR60, VAR75);
input VAR69;
input VAR60;
output VAR75;
VAR16 VAR67 (.VAR75(VAR75), .VAR69(VAR69), .VAR60(VAR60), .VAR25(1'b1), .VAR73(1'b1), .VAR44(1'b1));
endmodule
module \VAR5 (VAR69, VAR60, VAR73, VAR75);
input VAR69;
input VAR60;
input VAR73;
output VAR75;
VAR16 VAR67 (.VAR75(VAR75), .VAR69(V... | isc |
audiocircuit/NCSU-Low-Power-RFID | rfid-verilog/tag/tx.v | 6,327 | module MODULE1 (reset, VAR8, VAR13,
VAR10, VAR21, VAR28, VAR12,
VAR6, VAR16, VAR15, VAR17);
input reset, VAR8, VAR13, VAR10, VAR21, VAR28;
input [1:0] VAR12;
output VAR6, VAR16, VAR15, VAR17;
reg VAR6;
wire VAR16;
reg VAR15, VAR7, VAR33, VAR17;
reg VAR22;
reg VAR26, VAR24, VAR27;
reg VAR29;
wire VAR34;
assign VAR34 = V... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/mux2/gf180mcu_fd_sc_mcu9t5v0__mux2_4.behavioral.pp.v | 1,686 | module MODULE1( VAR6, VAR8, VAR1, VAR5, VAR7, VAR4 );
input VAR5, VAR8, VAR1;
inout VAR7, VAR4;
output VAR6;
VAR3 VAR2(.VAR6(VAR6),.VAR8(VAR8),.VAR1(VAR1),.VAR5(VAR5),.VAR7(VAR7),.VAR4(VAR4));
VAR3 VAR9(.VAR6(VAR6),.VAR8(VAR8),.VAR1(VAR1),.VAR5(VAR5),.VAR7(VAR7),.VAR4(VAR4)); | apache-2.0 |
richard42/CoCo3FPGA | coco3vid.v | 113,741 | module MODULE1(
VAR110,
VAR89,
VAR120,
VAR38,
VAR123,
VAR93,
VAR35,
VAR112,
VAR107,
VAR111,
VAR70,
VAR12,
VAR55,
VAR117,
VAR99,
VAR96,
VAR45,
VAR109,
VAR49,
VAR7,
VAR103,
VAR51,
VAR28,
VAR74,
VAR16, VAR21,
VAR53,
VAR3,
VAR72
);
input VAR110;
input VAR89;
output [8:0] VAR120;
reg [8:0] VAR120;
output VAR38;
reg VAR38;
o... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor3b/sky130_fd_sc_hdll__nor3b_1.v | 2,270 | module MODULE1 (
VAR9 ,
VAR10 ,
VAR2 ,
VAR3 ,
VAR6,
VAR7,
VAR8 ,
VAR5
);
output VAR9 ;
input VAR10 ;
input VAR2 ;
input VAR3 ;
input VAR6;
input VAR7;
input VAR8 ;
input VAR5 ;
VAR1 VAR4 (
.VAR9(VAR9),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR5(VAR5)
);
endmodule
module MODULE... | apache-2.0 |
audiocircuit/NCSU-Low-Power-RFID | rfid-verilog/reader/rfid_reader_tx.v | 4,996 | module MODULE1 (
reset, clk, VAR26,
VAR21, VAR11, VAR29, VAR34,
VAR27, VAR37, VAR12, VAR2, VAR1,
VAR30, VAR17
);
input reset, clk, VAR34, VAR29;
output VAR26;
output VAR21, VAR11;
input [15:0] VAR27, VAR37, VAR12, VAR2, VAR1;
input [6:0] VAR30;
input [127:0] VAR17;
reg [2:0] VAR28;
parameter VAR4 = 3'd0;
parameter VAR3... | gpl-3.0 |
freecores/logicprobe | tst/boards/XESS-XST-3S1000/lfsr128.v | 1,803 | module MODULE1(clk, VAR11, VAR5, VAR3);
input clk;
input VAR11;
output [3:0] VAR5;
output VAR3;
wire reset;
reg [23:0] VAR8;
reg [31:0] VAR9;
reg [31:0] VAR2;
reg [31:0] VAR12;
reg [31:0] VAR10;
wire VAR13;
wire VAR7;
wire [127:0] VAR1;
assign reset = (VAR8 == 24'hFFFFFF) ? 0 : 1;
always @(posedge clk) begin
if (VAR11 ... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfstp/sky130_fd_sc_hs__dfstp.behavioral.v | 2,087 | module MODULE1 (
VAR17 ,
VAR12 ,
VAR9 ,
VAR11,
VAR15 ,
VAR7
);
input VAR17 ;
input VAR12 ;
output VAR9 ;
input VAR11;
input VAR15 ;
input VAR7 ;
wire VAR1 ;
wire VAR18 ;
reg VAR19 ;
wire VAR8 ;
wire VAR10;
wire VAR14 ;
wire VAR5 ;
wire VAR4 ;
wire VAR13 ;
not VAR16 (VAR18 , VAR10 );
VAR3 VAR2 (VAR1 , VAR8, VAR14, VAR18... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/diode/sky130_fd_sc_hdll__diode_8.v | 1,994 | module MODULE1 (
VAR4,
VAR5 ,
VAR6 ,
VAR7 ,
VAR1
);
input VAR4;
input VAR5 ;
input VAR6 ;
input VAR7 ;
input VAR1 ;
VAR2 VAR3 (
.VAR4(VAR4),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR4
);
input VAR4;
supply1 VAR5;
supply0 VAR6;
supply1 VAR7 ;
supply0 VAR1 ;
VAR2 VAR3 (
.VAR4(VA... | apache-2.0 |
danidim13/labo-digitales | Experimento4/MiniAlu.v | 6,580 | module MODULE1
(
input wire VAR54,
input wire VAR32,
output wire [7:0] VAR35
output wire VAR65,
output wire VAR26,
output wire VAR7,
output wire VAR41,
output wire VAR29
);
wire [15:0] VAR61,VAR47,VAR34;
reg VAR36,VAR3,VAR21,VAR24;
wire [27:0] VAR27;
wire [3:0] VAR46;
reg [15:0] VAR20;
wire [7:0] VAR28,VAR50,VAR43, VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh.blackbox.v | 1,390 | module MODULE1 (
VAR1,
VAR4
);
output VAR1;
input VAR4;
supply1 VAR3 ;
supply0 VAR6 ;
supply1 VAR7;
supply1 VAR5 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/verilog/ANN_dexp_64ns_64ns_64_18_full_dsp.v | 1,637 | module MODULE1
VAR2 = 9,
VAR17 = 18,
VAR13 = 64,
VAR1 = 64,
VAR5 = 64
)(
input wire clk,
input wire reset,
input wire VAR6,
input wire [VAR13-1:0] VAR19,
input wire [VAR1-1:0] VAR4,
output wire [VAR5-1:0] dout
);
wire VAR12;
wire VAR18;
wire VAR20;
wire [63:0] VAR11;
wire VAR7;
wire [63:0] VAR8;
reg [VAR1-1:0] VAR22;
V... | gpl-3.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/tq/butterfly1_16.v | 3,570 | module MODULE1(
enable,
VAR16,
VAR25,
VAR12,
VAR6,
VAR27,
VAR2,
VAR7,
VAR11,
VAR23,
VAR1,
VAR22,
VAR13,
VAR3,
VAR19,
VAR17,
VAR28,
o0,
o1,
o2,
o3,
o4,
o5,
o6,
o7,
VAR30 ,
VAR26 ,
o10,
o11,
o12,
o13,
o14,
o15
);
input enable;
input signed [16:0] VAR16;
input signed [16:0] VAR25;
input signed [16:0] VAR12;
input signed [... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x4_125/source/pcie_7x_v1_3_pipe_sync.v | 22,970 | module MODULE1 #
(
parameter VAR52 = "VAR51", parameter VAR66 = "VAR89", parameter VAR16 = "VAR23", parameter VAR85 = 0, parameter VAR26 = 0, parameter VAR61 = 1, parameter VAR68 = 3, parameter VAR12 = 0, parameter VAR55 = 0
)
(
input VAR19,
input VAR81,
input VAR36,
input VAR44,
input VAR35,
input VAR31,
input VAR63,
... | lgpl-3.0 |
silent-observer/RCPU | CPU/source/PS2_Controller/Altera_UP_PS2_Data_In.v | 6,452 | module MODULE1 (
clk,
reset,
VAR2,
VAR7,
VAR8,
VAR15,
VAR6,
VAR4,
VAR13 );
input clk;
input reset;
input VAR2;
input VAR7;
input VAR8;
input VAR15;
input VAR6;
output reg [7:0] VAR4;
output reg VAR13;
localparam VAR1 = 3'h0,
VAR11 = 3'h1,
VAR3 = 3'h2,
VAR10 = 3'h3,
VAR16 = 3'h4;
reg [3:0] VAR14;
reg [7:0] VAR5;
reg [2:... | mit |
aaiijmrtt/JUCSEsem2 | VeryLargeScaleIntegration/adder.v | 1,222 | module MODULE4(VAR9, VAR6, sum, VAR13);
input wire VAR9, VAR6;
output wire sum, VAR13;
assign sum = VAR9 ^ VAR6;
assign VAR13 = VAR9 & VAR6;
endmodule
module MODULE3(VAR9, VAR6, VAR10, sum, VAR13);
input wire VAR9, VAR6, VAR10;
output wire sum, VAR13;
assign sum = VAR9 ^ VAR6 ^ VAR10;
assign VAR13 = (VAR9 & VAR6) | (VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a41oi/sky130_fd_sc_hs__a41oi.behavioral.pp.v | 1,971 | module MODULE1 (
VAR15,
VAR14,
VAR1 ,
VAR8 ,
VAR5 ,
VAR2 ,
VAR4 ,
VAR7
);
input VAR15;
input VAR14;
output VAR1 ;
input VAR8 ;
input VAR5 ;
input VAR2 ;
input VAR4 ;
input VAR7 ;
wire VAR4 VAR12 ;
wire VAR3 ;
wire VAR10;
and VAR6 (VAR12 , VAR8, VAR5, VAR2, VAR4 );
nor VAR13 (VAR3 , VAR7, VAR12 );
VAR11 VAR9 (VAR10, VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o31a/sky130_fd_sc_ms__o31a.functional.v | 1,425 | module MODULE1 (
VAR3 ,
VAR8,
VAR4,
VAR1,
VAR7
);
output VAR3 ;
input VAR8;
input VAR4;
input VAR1;
input VAR7;
wire VAR6 ;
wire VAR2;
or VAR10 (VAR6 , VAR4, VAR8, VAR1 );
and VAR5 (VAR2, VAR6, VAR7 );
buf VAR9 (VAR3 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfbbn/sky130_fd_sc_ls__sdfbbn_2.v | 2,825 | module MODULE1 (
VAR13 ,
VAR4 ,
VAR12 ,
VAR8 ,
VAR7 ,
VAR3 ,
VAR1 ,
VAR11,
VAR14 ,
VAR9 ,
VAR6 ,
VAR2
);
output VAR13 ;
output VAR4 ;
input VAR12 ;
input VAR8 ;
input VAR7 ;
input VAR3 ;
input VAR1 ;
input VAR11;
input VAR14 ;
input VAR9 ;
input VAR6 ;
input VAR2 ;
VAR10 VAR5 (
.VAR13(VAR13),
.VAR4(VAR4),
.VAR12(VAR12)... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srsdfrtp/sky130_fd_sc_lp__srsdfrtp.symbol.v | 1,604 | module MODULE1 (
input VAR1 ,
output VAR5 ,
input VAR7,
input VAR3 ,
input VAR9 ,
input VAR12 ,
input VAR11
);
supply1 VAR6;
supply1 VAR2 ;
supply0 VAR4 ;
supply1 VAR8 ;
supply0 VAR10 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfrtp/sky130_fd_sc_ms__sdfrtp.functional.pp.v | 2,211 | module MODULE1 (
VAR11 ,
VAR20 ,
VAR9 ,
VAR8 ,
VAR19 ,
VAR4,
VAR13 ,
VAR3 ,
VAR5 ,
VAR12
);
output VAR11 ;
input VAR20 ;
input VAR9 ;
input VAR8 ;
input VAR19 ;
input VAR4;
input VAR13 ;
input VAR3 ;
input VAR5 ;
input VAR12 ;
wire VAR7 ;
wire VAR10 ;
wire VAR14;
not VAR16 (VAR10 , VAR4 );
VAR17 VAR2 (VAR14, VAR9, VAR8... | apache-2.0 |
trnewman/VT-USRP-daughterboard-drivers_python | gr-radar-mono/src/fpga/lib/dac_interface.v | 1,791 | module MODULE1(VAR9,VAR6,VAR4,VAR1,VAR13,VAR8,VAR14,VAR7);
input VAR9;
input VAR6;
input VAR4;
input VAR1;
input [13:0] VAR13;
input [13:0] VAR8;
output [13:0] VAR14;
output VAR7;
wire VAR15;
reg VAR12;
reg [13:0] VAR14;
VAR10 VAR2(.VAR3(VAR6),.VAR11(VAR9),.VAR5(VAR15));
always @(posedge VAR15)
VAR12 <= VAR9;
always @(... | gpl-3.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/alt_mem_ddrx_ecc_encoder_32_syn.v | 13,776 | module MODULE1 #
( parameter
VAR1 = 0
)
(
clk,
VAR8,
VAR4,
VAR5
) ;
input clk;
input VAR8;
input [31:0] VAR4;
output [38:0] VAR5;
wire [31:0] VAR7;
wire [17:0] VAR14;
wire [9:0] VAR18;
wire [4:0] VAR6;
wire [1:0] VAR9;
wire [0:0] VAR2;
wire [5:0] VAR13;
wire [37:0] VAR12;
wire [37:0] VAR16;
reg [37:0] VAR17;
wire [37:0... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_1.v | 2,583 | module MODULE2 (
VAR1 ,
VAR6 ,
VAR2 ,
VAR10 ,
VAR4 ,
VAR7,
VAR11 ,
VAR12 ,
VAR5 ,
VAR9
);
output VAR1 ;
input VAR6 ;
input VAR2 ;
input VAR10 ;
input VAR4 ;
input VAR7;
input VAR11 ;
input VAR12 ;
input VAR5 ;
input VAR9 ;
VAR8 VAR3 (
.VAR1(VAR1),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR1... | apache-2.0 |
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