repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_8.behavioral.pp.v | 1,174 | module MODULE1( VAR6, VAR7, VAR5, VAR4 );
input VAR6;
inout VAR5, VAR4;
output VAR7;
VAR1 VAR2(.VAR6(VAR6),.VAR7(VAR7),.VAR5(VAR5),.VAR4(VAR4));
VAR1 VAR3(.VAR6(VAR6),.VAR7(VAR7),.VAR5(VAR5),.VAR4(VAR4)); | apache-2.0 |
rbesenczi/real-time-traffic-analyzer | src/traffic_analyser_Vivado_2014_4/traffic_analyser_Vivaldo_2014_4.srcs/sources_1/bd/design_1/ip/design_1_auto_us_0/synth/design_1_auto_us_0.v | 10,216 | module MODULE1 (
VAR68,
VAR49,
VAR83,
VAR69,
VAR80,
VAR30,
VAR28,
VAR19,
VAR87,
VAR15,
VAR98,
VAR73,
VAR35,
VAR14,
VAR86,
VAR26,
VAR12,
VAR6,
VAR63,
VAR79,
VAR90,
VAR55,
VAR70,
VAR9,
VAR78,
VAR13,
VAR93,
VAR18,
VAR8,
VAR82,
VAR21,
VAR65,
VAR4,
VAR72,
VAR5,
VAR32,
VAR3,
VAR75
);
input wire VAR68;
input wire VAR49;
input... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o21ba/sky130_fd_sc_hd__o21ba_1.v | 2,316 | module MODULE2 (
VAR8 ,
VAR2 ,
VAR10 ,
VAR9,
VAR1,
VAR4,
VAR7 ,
VAR5
);
output VAR8 ;
input VAR2 ;
input VAR10 ;
input VAR9;
input VAR1;
input VAR4;
input VAR7 ;
input VAR5 ;
VAR6 VAR3 (
.VAR8(VAR8),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR5(VAR5)
);
endmodule
module MODULE2 ... | apache-2.0 |
alexforencich/verilog-ethernet | example/HTG9200/fpga_10g/rtl/si5341_i2c_init.v | 46,920 | module MODULE1 (
input wire clk,
input wire rst,
output wire [6:0] VAR2,
output wire VAR4,
output wire VAR10,
output wire VAR14,
output wire VAR9,
output wire VAR6,
output wire VAR12,
input wire VAR1,
output wire [7:0] VAR8,
output wire VAR16,
input wire VAR5,
output wire VAR11,
output wire VAR13,
input wire VAR7
);
lo... | mit |
leonardhsin/3220-Lab1 | EggTimer.v | 3,621 | module MODULE7(
input [7:0]VAR4,
input [2:0]VAR30,
input VAR2,
output [6:0]VAR27,
output [6:0]VAR14,
output [6:0]VAR20,
output [6:0]VAR13,
output [9:0]VAR7,
output [7:0]VAR28
);
reg [3:0] VAR33 = 0;
reg [3:0] VAR29 = 0;
reg [3:0] VAR11 = 0;
reg [3:0] VAR31 = 0;
reg [9:0] VAR8 = 10'b0000000000;
reg [0:0] VAR22 = 0; reg ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlxtn/sky130_fd_sc_hs__dlxtn.blackbox.v | 1,264 | module MODULE1 (
VAR2 ,
VAR5 ,
VAR1
);
output VAR2 ;
input VAR5 ;
input VAR1;
supply1 VAR4;
supply0 VAR3;
endmodule | apache-2.0 |
ffu/DSA-3.2.2 | usrp/fpga/toplevel/usrp_multi/usrp_multi.v | 14,962 | module MODULE1
(output VAR90,
input VAR45,
input VAR121,
input VAR11,
inout VAR63,
input VAR201,
input VAR81,
output VAR33,
output VAR91,
input wire [11:0] VAR26,
input wire [11:0] VAR118,
input wire [11:0] VAR70,
input wire [11:0] VAR133,
output wire [13:0] VAR149,
output wire [13:0] VAR188,
output wire VAR158,
output... | gpl-3.0 |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_sdram/rtl/wb_sdram.v | 9,529 | module MODULE1 (
input clk,
input rst,
input VAR45,
input VAR28,
input [3:0] VAR16,
input [31:0] VAR2,
input VAR1,
output reg VAR27,
output reg [31:0] VAR31,
input [31:0] VAR30,
output reg VAR47,
output VAR35,
output VAR29,
output VAR41,
output VAR32,
output VAR33,
output VAR17,
output [11:0] VAR18,
output [1:0] VAR58,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkdlybuf4s25/sky130_fd_sc_hd__clkdlybuf4s25.pp.symbol.v | 1,356 | module MODULE1 (
input VAR2 ,
output VAR1 ,
input VAR3 ,
input VAR4,
input VAR5,
input VAR6
);
endmodule | apache-2.0 |
alexforencich/verilog-ethernet | rtl/ptp_tag_insert.v | 3,146 | module MODULE1 #
(
parameter VAR5 = 64,
parameter VAR13 = VAR5/8,
parameter VAR23 = 16,
parameter VAR19 = 1,
parameter VAR21 = VAR23+VAR19
)
(
input wire clk,
input wire rst,
input wire [VAR5-1:0] VAR11,
input wire [VAR13-1:0] VAR17,
input wire VAR3,
output wire VAR18,
input wire VAR14,
input wire [VAR21-1:0] VAR20,
ou... | mit |
codustry/cuckoo | FPGA - Verilog HDL/t_keepPressing.v | 1,361 | module MODULE1;
reg VAR4;
reg VAR5;
wire VAR2;
VAR3 VAR1 (
.VAR2(VAR2),
.VAR4(VAR4),
.VAR5(VAR5)
); | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/buf/sky130_fd_sc_ms__buf.behavioral.pp.v | 1,746 | module MODULE1 (
VAR1 ,
VAR6 ,
VAR12,
VAR5,
VAR11 ,
VAR10
);
output VAR1 ;
input VAR6 ;
input VAR12;
input VAR5;
input VAR11 ;
input VAR10 ;
wire VAR2 ;
wire VAR3;
buf VAR7 (VAR2 , VAR6 );
VAR4 VAR9 (VAR3, VAR2, VAR12, VAR5);
buf VAR8 (VAR1 , VAR3 );
endmodule | apache-2.0 |
aj-michael/Digital-Systems | Lab6-Part2/BaudRateGeneratorI2C.v | 1,081 | module MODULE1(VAR5, VAR4, VAR3, VAR1, VAR2, VAR7);
input [19:0] VAR2;
input [29:0] VAR7;
input VAR1, VAR3, VAR5;
output reg VAR4;
reg [15:0] VAR6;
reg [15:0] counter;
always @(posedge VAR1 or posedge VAR3)
if (VAR3 == 1) begin VAR6 <= 1'b0; VAR4 <= 1'b1; end
else if(VAR5 == 0) begin VAR6 <= 1'b0; VAR4 <= 1'b1; end
els... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o22a/sky130_fd_sc_hd__o22a.blackbox.v | 1,356 | module MODULE1 (
VAR6 ,
VAR5,
VAR1,
VAR2,
VAR8
);
output VAR6 ;
input VAR5;
input VAR1;
input VAR2;
input VAR8;
supply1 VAR9;
supply0 VAR7;
supply1 VAR4 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and2b/sky130_fd_sc_hdll__and2b_4.v | 2,152 | module MODULE1 (
VAR6 ,
VAR8 ,
VAR9 ,
VAR5,
VAR7,
VAR4 ,
VAR3
);
output VAR6 ;
input VAR8 ;
input VAR9 ;
input VAR5;
input VAR7;
input VAR4 ;
input VAR3 ;
VAR1 VAR2 (
.VAR6(VAR6),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR6 ,
VAR8,
VAR9
);
output VAR6 ... | apache-2.0 |
nikhilghanathe/HLS-for-EMTF | verilog/sp_mux_8to1_sel4_7_1.v | 1,885 | module MODULE1 #(
parameter
VAR18 = 0,
VAR12 = 1,
VAR3 = 32,
VAR11 = 32,
VAR6 = 32,
VAR17 = 32,
VAR4 = 32,
VAR27 = 32,
VAR19 = 32,
VAR22 = 32,
VAR21 = 32,
VAR1 = 32
)(
input [6 : 0] VAR16,
input [6 : 0] VAR8,
input [6 : 0] VAR28,
input [6 : 0] VAR23,
input [6 : 0] VAR9,
input [6 : 0] VAR14,
input [6 : 0] VAR24,
input [... | apache-2.0 |
bluespec/Flute | builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkPTW.v | 35,242 | module MODULE1(VAR48,
VAR187,
VAR35,
VAR129,
VAR28,
VAR88,
VAR176,
VAR160,
VAR100,
VAR159,
VAR137,
VAR166,
VAR83,
VAR69,
VAR43,
VAR138,
VAR186,
VAR191,
VAR156,
VAR27);
parameter [2 : 0] VAR109 = 3'b0;
input VAR48;
input VAR187;
input [127 : 0] VAR35;
input VAR129;
output VAR28;
input VAR88;
output [131 : 0] VAR176;
out... | apache-2.0 |
ServerTech/neptune | code/control_matrix_core.v | 7,278 | module MODULE1(clk, rst, VAR4, VAR22, VAR8, VAR16, VAR17, VAR25, VAR11, VAR12, VAR13, VAR18, VAR21, VAR27, VAR5, VAR1, VAR10, VAR7, VAR15, VAR6, state);
parameter VAR28 = 'd16; parameter VAR20 = 'd3; parameter VAR24 = 'd16;
input wire clk , rst , VAR4 ; input wire VAR22 , VAR8 ;
input wire VAR16 , VAR17 , VAR25 , VAR11... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/tap/sky130_fd_sc_hd__tap.functional.v | 1,056 | module MODULE1 ();
endmodule | apache-2.0 |
GSejas/Aproximate-Arithmetic-Operators | add_approx_flow/integracion_fisica/front_end/db/SINGLE/Approx_adder_GDAN8M8P3_syn.v | 8,794 | module MODULE1 ( VAR70, VAR63, VAR35, VAR180 );
input [15:0] VAR63;
input [15:0] VAR35;
output [16:0] VAR180;
input VAR70;
wire VAR51, VAR12, VAR126, VAR218, VAR246, VAR240, VAR64, VAR20, VAR176, VAR3, VAR283, VAR55, VAR187, VAR214,
VAR82, VAR273, VAR255, VAR54, VAR108, VAR46, VAR143, VAR56, VAR247, VAR81, VAR61, VAR11... | apache-2.0 |
ShepardSiegel/ocpi | libsrc/hdl/bsv/SyncRegister.v | 5,001 | module MODULE1(
VAR20,
VAR12,
VAR3,
VAR19,
VAR14,
VAR15,
VAR21
);
parameter VAR10 = 1 ;
parameter VAR6 = { VAR10 {1'b0 }} ;
input VAR20 ;
input VAR12 ;
input VAR19 ;
input [VAR10 -1 : 0] VAR15 ;
output VAR14 ;
input VAR3 ;
output [VAR10 -1 : 0] VAR21 ;
wire VAR18 ;
reg [VAR10 -1 : 0] VAR13 ;
reg [VAR10 -1 : 0] VAR21 ;
... | lgpl-3.0 |
hj3938/FPGA-Imaging-Library | Generator/FrameController/HDL/FrameController.srcs/sources_1/new/FrameController.v | 4,704 | module MODULE1(
clk,
VAR16,
VAR9,
VAR11,
VAR4,
VAR1,
VAR13);
parameter VAR10 = 0;
parameter VAR3 = 0;
parameter VAR15 = 8;
parameter VAR14 = 320;
parameter VAR12 = 240;
parameter VAR5 = 17;
parameter VAR2 = 2;
parameter VAR6 = 0;
input clk;
input VAR16;
input VAR9;
input [VAR15 - 1 : 0] VAR11;
output VAR4;
output[VAR15... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/mux2i/sky130_fd_sc_hd__mux2i.functional.pp.v | 1,934 | module MODULE1 (
VAR15 ,
VAR12 ,
VAR2 ,
VAR14 ,
VAR8,
VAR11,
VAR13 ,
VAR5
);
output VAR15 ;
input VAR12 ;
input VAR2 ;
input VAR14 ;
input VAR8;
input VAR11;
input VAR13 ;
input VAR5 ;
wire VAR4;
wire VAR7;
VAR9 VAR10 (VAR4, VAR12, VAR2, VAR14 );
VAR1 VAR6 (VAR7, VAR4, VAR8, VAR11);
buf VAR3 (VAR15 , VAR7 );
endmodule | apache-2.0 |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/ip/Pmods/PmodNAV_v1_0/src/PmodNAV.v | 13,731 | module MODULE1
(VAR130,
VAR145,
VAR89,
VAR53,
VAR81,
VAR163,
VAR91,
VAR65,
VAR119,
VAR157,
VAR129,
VAR194,
VAR154,
VAR10,
VAR196,
VAR95,
VAR33,
VAR14,
VAR142,
VAR103,
VAR202,
VAR68,
VAR143,
VAR30,
VAR140,
VAR83,
VAR112,
VAR22,
VAR150,
VAR179,
VAR63,
VAR117,
VAR190,
VAR206,
VAR171,
VAR195,
VAR146,
VAR3,
VAR27,
VAR114,
V... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inv/sky130_fd_sc_hdll__inv_4.v | 2,011 | module MODULE2 (
VAR8 ,
VAR2 ,
VAR3,
VAR5,
VAR1 ,
VAR7
);
output VAR8 ;
input VAR2 ;
input VAR3;
input VAR5;
input VAR1 ;
input VAR7 ;
VAR4 VAR6 (
.VAR8(VAR8),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR8,
VAR2
);
output VAR8;
input VAR2;
supply1 VAR3;
supply0 VAR5;... | apache-2.0 |
CospanDesign/nysa-artemis-platform | artemis/slave/wb_artemis_ddr3/rtl/ddr3_dma.v | 5,591 | module MODULE1(
input clk,
input rst,
input VAR11,
input [63:0] VAR26,
input VAR64,
input VAR34,
output reg VAR54,
input [23:0] VAR27,
input VAR10,
output [1:0] VAR55,
input [1:0] VAR58,
output [23:0] VAR49,
input VAR38,
input [31:0] VAR22,
input VAR45,
input [63:0] VAR39,
input VAR18,
input VAR56,
output VAR24,
output... | gpl-2.0 |
CeesWolfs/ceespu | src/ceespu_alu.v | 2,648 | module MODULE1(
input VAR14,
input VAR13,
input [31:0] VAR12,
input [31:0] VAR2,
input VAR4,
input [3:0] VAR16,
output reg VAR10 = 0,
output reg [31:0] VAR6,
output reg [31:0] VAR9,
output reg VAR11,
output VAR5
);
always @* begin
VAR10 = 0;
VAR6 = VAR12 + VAR2 + VAR4;
case(VAR16)
default: begin
{VAR11, VAR9} = VAR12 +... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or4bb/sky130_fd_sc_hs__or4bb.pp.blackbox.v | 1,292 | module MODULE1 (
VAR6 ,
VAR7 ,
VAR2 ,
VAR4 ,
VAR5 ,
VAR1,
VAR3
);
output VAR6 ;
input VAR7 ;
input VAR2 ;
input VAR4 ;
input VAR5 ;
input VAR1;
input VAR3;
endmodule | apache-2.0 |
SymbiFlow/yosys-f4pga-plugins | ql-qlf-plugin/qlf_k6n10f/sram1024x18.v | 4,505 | module MODULE1 (
VAR10,
VAR11,
VAR1,
VAR19,
VAR3,
VAR16,
VAR2,
VAR13,
VAR4,
VAR17,
VAR21,
VAR8,
VAR25,
VAR9
);
input wire VAR10;
input wire VAR11;
input wire VAR1;
input wire [9:0] VAR19;
input wire [17:0] VAR3;
input wire [17:0] VAR16;
output reg [17:0] VAR2;
input wire VAR13;
input wire VAR4;
input wire VAR17;
input ... | apache-2.0 |
DeadWitcher/amber-de0-nano | hw/vlog/ethmac/eth_shiftreg.v | 6,615 | module MODULE1(VAR13, VAR3, VAR4, VAR5, VAR15, VAR7, VAR1, VAR11, VAR14,
VAR2, VAR12, VAR10, VAR8);
parameter VAR9=1;
input VAR13; input VAR3; input VAR4; input VAR5; input [4:0] VAR15; input [4:0] VAR7; input [15:0]VAR1; input VAR11; input [3:0] VAR14; input [1:0] VAR2;
output VAR12; output[15:0]VAR10; output VAR8;
re... | lgpl-2.1 |
anderson1008/PAB-NOC | RTL/loadTrack_v2.v | 1,391 | module MODULE1 (reset, clk, valid, VAR5, VAR15, VAR4, VAR2, VAR11);
input clk, reset,VAR15;
input [3:0] valid;
input [3:0] VAR5;
input [4*VAR13-1:0] VAR4; output [VAR1-1:0] VAR2;
output [4*VAR9-1:0] VAR11;
wire [VAR13-1:0] VAR3 [3:0];
genvar VAR14;
generate
for (VAR14=0; VAR14<4; VAR14= VAR14+1) begin : VAR10
assign VA... | gpl-2.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/ethmac/bench/verilog/wb_master32.v | 13,486 | module MODULE1
(
VAR7,
VAR1,
VAR47,
VAR49,
VAR61,
VAR39,
VAR53,
VAR46,
VAR2,
VAR64,
VAR43,
VAR29,
VAR58,
VAR56,
VAR24
);
input VAR7;
input VAR1;
input VAR11 VAR47;
output VAR11 VAR49;
input VAR61;
output VAR31 VAR39;
output VAR53;
input VAR13 VAR46;
output VAR13 VAR2;
input VAR64;
input VAR43;
output VAR60 VAR29;
outpu... | gpl-2.0 |
ServerTech/neptune | code/neptune_I_core.v | 10,615 | module MODULE1(clk, VAR41, VAR11, VAR59, VAR1, VAR78, VAR103, VAR28, VAR27, VAR5, VAR40, VAR127, VAR73, VAR132, VAR70, VAR33, VAR116);
parameter VAR134 = 'd16; parameter VAR104 = 'd8; parameter VAR98 = 'd3; parameter VAR17 = 'd8192; parameter VAR63 = 'd13; parameter VAR46 = 'd256; parameter VAR97 = 'd8; parameter VAR58... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/einvn/sky130_fd_sc_lp__einvn_m.v | 2,147 | module MODULE2 (
VAR4 ,
VAR3 ,
VAR2,
VAR9,
VAR1,
VAR7 ,
VAR6
);
output VAR4 ;
input VAR3 ;
input VAR2;
input VAR9;
input VAR1;
input VAR7 ;
input VAR6 ;
VAR8 VAR5 (
.VAR4(VAR4),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR4 ,
VAR3 ,
VAR2
);
output VAR4 ;... | apache-2.0 |
olgirard/openmsp430 | fpga/xilinx_avnet_lx9microbard/bench/verilog/ram_16x1k_dp.v | 2,894 | module MODULE1 (
VAR11,
VAR4,
VAR18,
VAR14,
VAR17,
VAR1,
VAR25,
VAR15,
VAR13,
VAR23,
VAR27,
VAR3
);
input VAR11;
input VAR4;
input [1 : 0] VAR18;
input [9 : 0] VAR14;
input [15 : 0] VAR17;
output [15 : 0] VAR1;
input VAR25;
input VAR15;
input [1 : 0] VAR13;
input [9 : 0] VAR23;
input [15 : 0] VAR27;
output [15 : 0] VAR... | bsd-3-clause |
YosysHQ/yosys | techlibs/xilinx/urams_map.v | 3,552 | module MODULE1 (...);
parameter VAR47 = 8;
localparam VAR20 = 72 / VAR47;
parameter VAR19 = 1;
parameter VAR36 = 1;
parameter VAR49 = "VAR11";
parameter VAR40 = 1;
parameter VAR51 = "VAR11";
input VAR44;
input VAR25;
input VAR21;
input VAR46;
input VAR41;
input VAR62;
input [VAR20-1:0] VAR39;
input [11:0] VAR28;
input ... | isc |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/and2/sky130_fd_sc_hvl__and2.pp.symbol.v | 1,267 | module MODULE1 (
input VAR1 ,
input VAR7 ,
output VAR6 ,
input VAR5 ,
input VAR2,
input VAR3,
input VAR4
);
endmodule | apache-2.0 |
twlostow/dsi-shield | hdl/rtl/hpdmc/spartan6/hpdmc_iddr32.v | 7,216 | module MODULE1 #(
parameter VAR8 = "VAR40",
parameter VAR17 = 1'b0,
parameter VAR26 = 1'b0,
parameter VAR5 = "VAR31"
) (
output [31:0] VAR43,
output [31:0] VAR23,
input VAR40,
input VAR11,
input VAR2,
input [31:0] VAR27,
input VAR13,
input VAR21
);
VAR18 #(
.VAR8(VAR8),
.VAR17(VAR17),
.VAR26(VAR26),
.VAR5(VAR5)
) VAR33... | lgpl-3.0 |
sabertazimi/hust-lab | verilog/labs/lab2/src/lab2_2_2_1_partA.v | 1,185 | module MODULE1(
input [3:0] VAR9,
output VAR14,
output [3:0] VAR15
);
wire flag;
wire [2:0] VAR3;
VAR13 VAR12 (.in(VAR9), .flag(flag));
VAR10 VAR1 (.VAR11(VAR9[2:0]), .VAR2(VAR3));
assign VAR14 = flag;
VAR4 VAR6 (.VAR7(VAR9[0]), .VAR5(VAR3[0]), .VAR16(flag), .VAR18(VAR15[0]));
VAR4 VAR19 (.VAR7(VAR9[1]), .VAR5(VAR3[1])... | mit |
phase4ground/DVB-receiver | modem/hdl/library/fir_filter/fir_filter_axi-lite.v | 12,888 | module MODULE1 #
(
parameter integer VAR34 = 16,
parameter integer VAR14 = 16,
parameter integer VAR75 = 16,
parameter integer VAR64 = 16,
parameter integer VAR29 = -2,
parameter integer VAR8 = 1,
parameter VAR62 = 4,
parameter VAR72 = 32,
parameter [0:0] VAR63 = 1'b0,
parameter [0:0] VAR41 = 0,
parameter VAR37 = VAR24... | gpl-3.0 |
CospanDesign/nysa-tx1-pcie-platform | tx1_pcie/slave/wb_tx1_pcie/rtl/wb_tx1_pcie.v | 15,836 | module MODULE1 #(
parameter VAR97 = 10,
parameter VAR84 = 6,
parameter VAR40 = 7
) (
input clk,
input rst,
input VAR17,
input VAR110,
input [3:0] VAR47,
input [31:0] VAR44,
input VAR108,
output reg VAR50,
output reg [31:0] VAR100,
input [31:0] VAR20,
output VAR14,
output VAR65,
output VAR38,
output VAR106,
input VAR114... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o22a/sky130_fd_sc_hdll__o22a_1.v | 2,355 | module MODULE1 (
VAR8 ,
VAR11 ,
VAR7 ,
VAR2 ,
VAR4 ,
VAR6,
VAR1,
VAR5 ,
VAR9
);
output VAR8 ;
input VAR11 ;
input VAR7 ;
input VAR2 ;
input VAR4 ;
input VAR6;
input VAR1;
input VAR5 ;
input VAR9 ;
VAR10 VAR3 (
.VAR8(VAR8),
.VAR11(VAR11),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand3b/sky130_fd_sc_ls__nand3b.behavioral.v | 1,497 | module MODULE1 (
VAR7 ,
VAR3,
VAR13 ,
VAR11
);
output VAR7 ;
input VAR3;
input VAR13 ;
input VAR11 ;
supply1 VAR1;
supply0 VAR10;
supply1 VAR2 ;
supply0 VAR5 ;
wire VAR8 ;
wire VAR12;
not VAR4 (VAR8 , VAR3 );
nand VAR6 (VAR12, VAR13, VAR8, VAR11 );
buf VAR9 (VAR7 , VAR12 );
endmodule | apache-2.0 |
Apo45ty/ArquiCourseCPUVerilog | VerilogSource/PreFabALU+RF+BS/ARM_ALU.v | 2,246 | module MODULE1(input wire [31:0] VAR2,VAR5,input wire[4:0] VAR7,input wire [3:0] VAR10,output wire [31:0] VAR8,output wire [3:0] VAR9, input wire VAR3,VAR11);
parameter VAR6 = 32'VAR1;
reg [31:0] buffer,VAR2,VAR5;
reg [3:0] VAR4;
always @(VAR2 or VAR5 or VAR7)
begin
VAR4=4'h0;
VAR2=VAR2;
VAR5=VAR5;
casez(VAR7)
5'b00000... | apache-2.0 |
petrmikheev/miksys | verilog/RAM512x16_2RW.v | 11,225 | module MODULE1 (
VAR4,
VAR30,
VAR65,
VAR23,
VAR63,
VAR36,
VAR46,
VAR5,
VAR26,
VAR1,
VAR50);
input [8:0] VAR4;
input [8:0] VAR30;
input [1:0] VAR65;
input [1:0] VAR23;
input VAR63;
input [15:0] VAR36;
input [15:0] VAR46;
input VAR5;
input VAR26;
output [15:0] VAR1;
output [15:0] VAR50;
tri1 [1:0] VAR65;
tri1 [1:0] VAR23... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfrtp/sky130_fd_sc_ms__dfrtp_1.v | 2,329 | module MODULE1 (
VAR3 ,
VAR6 ,
VAR10 ,
VAR7,
VAR1 ,
VAR4 ,
VAR9 ,
VAR8
);
output VAR3 ;
input VAR6 ;
input VAR10 ;
input VAR7;
input VAR1 ;
input VAR4 ;
input VAR9 ;
input VAR8 ;
VAR2 VAR5 (
.VAR3(VAR3),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR8(VAR8)
);
endmodule
module MODU... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a21oi/sky130_fd_sc_ls__a21oi.functional.v | 1,420 | module MODULE1 (
VAR1 ,
VAR4,
VAR9,
VAR8
);
output VAR1 ;
input VAR4;
input VAR9;
input VAR8;
wire VAR2 ;
wire VAR3;
and VAR6 (VAR2 , VAR4, VAR9 );
nor VAR7 (VAR3, VAR8, VAR2 );
buf VAR5 (VAR1 , VAR3 );
endmodule | apache-2.0 |
sh-chris110/chris | FPGA/chris.system.dma.ok/Qsys/soc_design/synthesis/soc_design.v | 46,909 | module MODULE1 (
output wire [12:0] VAR316, output wire [1:0] VAR317, output wire VAR309, output wire VAR263, output wire VAR57, inout wire [15:0] VAR341, output wire [1:0] VAR142, output wire VAR167, output wire VAR87, output wire VAR273, input wire VAR113, output wire VAR266, input wire VAR247, input wire VAR320, out... | gpl-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/cm_rom_final.v | 10,225 | module MODULE1 (
VAR56,
VAR40,
VAR59,
VAR19,
VAR37,
VAR24);
input VAR56;
input [8:0] VAR40;
input [8:0] VAR59;
input VAR19;
output [3:0] VAR37;
output [3:0] VAR24;
tri0 VAR56;
tri1 VAR19;
wire [3:0] VAR7;
wire [3:0] VAR12;
wire VAR18 = 1'h0;
wire [3:0] VAR52 = 4'h0;
wire [3:0] VAR24 = VAR7[3:0];
wire [3:0] VAR37 = VAR1... | mit |
jayant-sharma/uart | hdl/packet_gen.v | 8,368 | module MODULE1#(
parameter VAR24 = 8,
parameter VAR9 = 16,
parameter VAR19 = 31'h6000
)
(
input VAR15,
input VAR3,
input [VAR24-1:0] VAR18,
input VAR35,
input VAR13,
input VAR41,
input VAR33,
input [VAR24-1:0] VAR25,
input [7:0] VAR11,
output reg [VAR24-1:0] VAR14,
output wire VAR39,
output wire [VAR9-1:0] VAR37,
outpu... | unlicense |
FPGA1988/udp_ip_stack | Network/udp_ip_core/trunk/ic/lib/smic18.v | 413,500 | module MODULE1 (VAR2, VAR1, VAR3);
input VAR2 ;
input VAR1 ;
output VAR3 ;
and (VAR3, VAR2, VAR1); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor3b/sky130_fd_sc_hs__nor3b.behavioral.v | 1,916 | module MODULE1 (
VAR7 ,
VAR13 ,
VAR8 ,
VAR10 ,
VAR3,
VAR6
);
output VAR7 ;
input VAR13 ;
input VAR8 ;
input VAR10 ;
input VAR3;
input VAR6;
wire VAR9 ;
wire VAR4 ;
wire VAR12;
nor VAR2 (VAR9 , VAR13, VAR8 );
and VAR5 (VAR4 , VAR10, VAR9 );
VAR11 VAR1 (VAR12, VAR4, VAR3, VAR6);
buf VAR14 (VAR7 , VAR12 );
endmodule | apache-2.0 |
bgamari/timetag-fpga | sequencer.v | 2,960 | module MODULE1(
clk,
reset, VAR25,
out,
VAR4, VAR9, VAR26, VAR12
);
parameter VAR19 = 0;
input clk;
input reset;
input VAR25;
output out;
input VAR4;
input [15:0] VAR9;
inout [31:0] VAR26;
input VAR12;
reg out;
VAR16 out = 0;
reg [31:0] counter;
VAR16 counter = 32'h0;
wire [31:0] VAR2;
wire VAR13 = VAR2[0];
wire VAR20 ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o41a/sky130_fd_sc_hd__o41a.functional.pp.v | 2,047 | module MODULE1 (
VAR10 ,
VAR15 ,
VAR6 ,
VAR1 ,
VAR13 ,
VAR12 ,
VAR3,
VAR18,
VAR4 ,
VAR16
);
output VAR10 ;
input VAR15 ;
input VAR6 ;
input VAR1 ;
input VAR13 ;
input VAR12 ;
input VAR3;
input VAR18;
input VAR4 ;
input VAR16 ;
wire VAR7 ;
wire VAR17 ;
wire VAR8;
or VAR9 (VAR7 , VAR13, VAR1, VAR6, VAR15 );
and VAR5 (VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fah/sky130_fd_sc_hs__fah.functional.pp.v | 2,494 | module MODULE1 (
VAR18,
VAR16 ,
VAR11 ,
VAR24 ,
VAR5 ,
VAR10,
VAR4
);
output VAR18;
output VAR16 ;
input VAR11 ;
input VAR24 ;
input VAR5 ;
input VAR10;
input VAR4;
wire VAR15 ;
wire VAR8 ;
wire VAR22 ;
wire VAR9 ;
wire VAR6 ;
wire VAR3 ;
wire VAR12;
xor VAR7 (VAR15 , VAR11, VAR24, VAR5 );
VAR13 VAR20 (VAR8 , VAR15, VA... | apache-2.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/stream_encoder_ip_prj/stream_encoder_ip_prj.runs/mult_gen_1_synth_1/mult_gen_1_stub.v | 1,247 | module MODULE1(VAR2, VAR1, VAR3)
;
input [11:0]VAR2;
input [13:0]VAR1;
output [32:0]VAR3;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand3/sky130_fd_sc_hdll__nand3.behavioral.v | 1,395 | module MODULE1 (
VAR10,
VAR4,
VAR1,
VAR11
);
output VAR10;
input VAR4;
input VAR1;
input VAR11;
supply1 VAR3;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR8 ;
wire VAR9;
nand VAR6 (VAR9, VAR1, VAR4, VAR11 );
buf VAR7 (VAR10 , VAR9 );
endmodule | apache-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_sdd1/main.v | 28,854 | module MODULE1(
output [22:0] VAR157,
output VAR22,
input VAR222,
output VAR51,
input VAR251,
output [21:0] VAR157,
output VAR288,
output VAR74,
output VAR224,
output VAR87,
output VAR183,
input VAR31,
input VAR320,
input [23:0] VAR345,
input VAR100,
input VAR184,
input VAR277,
inout [7:0] VAR238,
input VAR62,
input VA... | gpl-2.0 |
jhol/butterflylogic | rtl/regs.v | 1,502 | module MODULE4 #(
parameter VAR3 = 1
)(
input wire clk,
input wire [VAR3-1:0] VAR5,
output reg [VAR3-1:0] VAR7
);
always @(posedge clk) VAR7 <= VAR5;
endmodule
module MODULE2 #(
parameter VAR3 = 1,
parameter VAR6 = 1
)(
input wire clk,
input wire reset,
input wire [VAR3-1:0] VAR8,
output wire [VAR3-1:0] VAR1
);
reg [(V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/inv/sky130_fd_sc_ms__inv.blackbox.v | 1,204 | module MODULE1 (
VAR2,
VAR6
);
output VAR2;
input VAR6;
supply1 VAR3;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
osrf/wandrr | firmware/motor_controller/fpga/menc_sincos.v | 1,142 | module MODULE1
(input VAR14,
input [13:0] VAR5,
input [10:0] VAR17,
input [7:0] VAR15,
output [31:0] VAR3,
output [31:0] VAR16);
wire VAR18;
VAR19 VAR11(.VAR14(VAR14), .en(1'b1), .rst(1'b0), .VAR13(~VAR18), .VAR4(VAR18));
wire [10:0] VAR21, VAR26;
VAR1 #(11) VAR27(.VAR14(VAR14), .VAR13(VAR5 + VAR17), .VAR4(VAR21));
VAR... | apache-2.0 |
chipsalliance/yosys-f4pga-plugins | ql-qlf-plugin/qlf_k6n10f/brams_map.v | 31,120 | module \VAR136 (VAR31, VAR130, VAR100, VAR145, VAR125, VAR38, VAR48, VAR63, VAR32, VAR70, VAR54, VAR23, VAR10, VAR27);
parameter VAR134 = 10;
parameter VAR41 = 36;
parameter VAR91 = 4;
parameter VAR108 = 4;
parameter VAR58 = 1;
parameter VAR129 = 1;
parameter [36863:0] VAR131 = 36864'VAR50;
input VAR70;
input VAR54;
in... | apache-2.0 |
gigglesninja/digital-system-design | Lab4/ipcore_dir/mult12x12.v | 8,059 | module MODULE1 (
VAR39, VAR33, VAR3
);
output [23 : 0] VAR39;
input [11 : 0] VAR33;
input [11 : 0] VAR3;
wire \VAR41/VAR20 ;
wire \VAR41/VAR62 ;
wire \VAR29/VAR46<34>VAR42 ;
wire \VAR29/VAR46<33>VAR42 ;
wire \VAR29/VAR46<32>VAR42 ;
wire \VAR29/VAR46<31>VAR42 ;
wire \VAR29/VAR46<30>VAR42 ;
wire \VAR29/VAR46<29>VAR42 ;
w... | gpl-2.0 |
SiLab-Bonn/monopix_daq | firmware/src/monopix_mio3.v | 19,093 | module MODULE1(
input wire VAR233,
output wire [7:0] VAR178,
input wire [1:0] VAR23,
output wire [1:0] VAR96,
input wire VAR101,
input wire VAR130,
input wire VAR131, output wire VAR37, output wire VAR166, output wire VAR14, output wire VAR157, output wire VAR71, output wire VAR83, output wire VAR85,
input wire VAR67,
... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inv/sky130_fd_sc_lp__inv.functional.v | 1,225 | module MODULE1 (
VAR4,
VAR2
);
output VAR4;
input VAR2;
wire VAR1;
not VAR5 (VAR1, VAR2 );
buf VAR3 (VAR4 , VAR1 );
endmodule | apache-2.0 |
m-labs/milkymist | cores/pfpu/rtl/pfpu_clz32.v | 1,891 | module MODULE1(
input [31:0] VAR5,
output [4:0] VAR3
);
assign VAR3[4] = VAR5[31:16] == 16'd0;
wire [15:0] VAR4 = VAR3[4] ? VAR5[15:0] : VAR5[31:16];
assign VAR3[3] = VAR4[15:8] == 8'd0;
wire [7:0] VAR1 = VAR3[3] ? VAR4[7:0] : VAR4[15:8];
assign VAR3[2] = VAR1[7:4] == 4'd0;
wire [3:0] VAR6 = VAR3[2] ? VAR1[3:0] : VAR1[... | lgpl-3.0 |
Tao-J/nexys3MIPSSoC | led_Dev_IO.v | 1,034 | module MODULE1(input clk,
input rst,
input VAR1,
input [31:0] VAR2,
output [1:0] VAR4,
output [7:0] VAR5,
output [21:0] VAR3
);
endmodule | gpl-3.0 |
DreamIP/GPStudio | support/process/norm/hdl/norm.v | 3,815 | module MODULE1(
VAR6,
VAR10,
VAR18,
VAR5,
VAR46,
VAR1,
VAR26,
VAR15,
VAR22,
VAR44,
VAR12,
VAR56,
VAR33
);
parameter VAR41 = 16;
parameter VAR58 = 16;
parameter VAR54 = 50000000;
localparam VAR30 = 8;
localparam VAR40 = 10;
input VAR6;
input VAR10;
input VAR18;
input VAR5;
input [VAR41-1:0] VAR46;
output VAR1;
output VA... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/velocityControlHdl_Complex_Multiply.v | 1,969 | module MODULE1
(
VAR11,
VAR8,
VAR6,
VAR3,
VAR12,
VAR2
);
input signed [17:0] VAR11; input signed [17:0] VAR8; input signed [17:0] VAR6; input signed [17:0] VAR3; output signed [35:0] VAR12; output signed [35:0] VAR2;
wire signed [35:0] VAR4; wire signed [35:0] VAR7; wire signed [35:0] VAR10; wire signed [35:0] VAR5; wi... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or3/sky130_fd_sc_hd__or3.symbol.v | 1,268 | module MODULE1 (
input VAR8,
input VAR4,
input VAR6,
output VAR1
);
supply1 VAR7;
supply0 VAR5;
supply1 VAR2 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeDE1SoC/Computer_System/synthesis/submodules/altera_up_edge_detection_pixel_info_shift_register.v | 5,149 | module MODULE1 (
VAR6,
VAR8,
VAR5,
VAR12,
VAR7);
parameter VAR2 = 3628;
input VAR6;
input VAR8;
input [1:0] VAR5;
output [1:0] VAR12;
output [1:0] VAR7;
wire [1:0] VAR10;
wire [1:0] VAR1;
wire [1:0] VAR7 = VAR10[1:0];
wire [1:0] VAR12 = VAR1[1:0];
VAR4 VAR14 (
.VAR6 (VAR6),
.VAR8 (VAR8),
.VAR5 (VAR5),
.VAR7 (VAR10),
.V... | mit |
elegabriel/myzju | junior1/CA/LAB/lab6/lab6_gxl_3120102146/code/exin.v | 2,679 | module MODULE1(VAR3,rst,VAR2,VAR1
);
input VAR3,rst;
input [31:0] VAR2;
output reg [7:0] VAR1;
always @(*)
begin
if (rst)
VAR1=8'd0;
end
else
case(VAR2[31:26])
6'b000000:
begin
case(VAR2[5:0])
6'b100000:
begin
VAR1=(|VAR2[15:11])?8'd1:8'h0; end
6'b100001:VAR1=8'd2; 6'b100010:VAR1=8'd3; 6'b100011:VAR1=8'd4; 6'b100100:VA... | gpl-2.0 |
omicronns/studies-sys-rek | de1-soc-template/Sdram_Control/Sdram_Control.v | 21,610 | module MODULE1 (
VAR47,
VAR128,
VAR70,
VAR85,
VAR68,
VAR55,
VAR49,
VAR109,
VAR26,
VAR88,
VAR63,
VAR41,
VAR60,
VAR120,
VAR97,
VAR106,
VAR75,
VAR92,
VAR39,
VAR10,
VAR40,
VAR105,
VAR90,
VAR119,
VAR67,
VAR82,
VAR73,
VAR83,
VAR112,
VAR27,
VAR94,
VAR124,
VAR45,
VAR32,
VAR96,
VAR78,
VAR31,
VAR59,
VAR38
);
input VAR47; input V... | mit |
monotone-RK/FACE | IEICE-Trans/8-way_2-tree/src/riffa/one_hot_mux.v | 4,779 | module MODULE1
parameter VAR5 = 2,
parameter VAR3 = VAR5*VAR8
)
(
input [VAR5-1:0] VAR7,
input [VAR3-1:0] VAR9,
output [VAR8-1:0] VAR10);
genvar VAR2;
wire [VAR8-1:0] VAR6[(1<<VAR5):1];
reg [VAR8-1:0] VAR1;
assign VAR10 = VAR1;
generate
for( VAR2 = 0 ; VAR2 < VAR5; VAR2 = VAR2 + 1 ) begin : VAR4
assign VAR6[(1<<VAR2)] ... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/analog/bw_clk/rtl/bw_clk_cclk_hdr_48x.v | 3,245 | module MODULE1 (
VAR15, VAR29, clk, VAR4,
VAR24, VAR18, VAR12, VAR26, VAR2, VAR22, VAR19, VAR17,
VAR28
);
input VAR24;
input VAR28;
input VAR18;
input VAR12;
input VAR26;
input VAR2;
input VAR22;
output VAR29;
output VAR15;
output clk;
input VAR19; input VAR17;
output VAR4;
wire VAR6;
wire VAR11;
wire VAR21;
wire VAR29... | gpl-2.0 |
bluespec/Flute | src_SSITH_P2/Verilog_RTL/mkTLB.v | 35,110 | module MODULE1(VAR1,
VAR6,
VAR115,
VAR150,
VAR149,
VAR101,
VAR193,
VAR126,
VAR164,
VAR168,
VAR34,
VAR122,
VAR136,
VAR154,
VAR83,
VAR130,
VAR118,
VAR112,
VAR87);
parameter [0 : 0] VAR106 = 1'b0;
parameter [2 : 0] VAR103 = 3'b0;
input VAR1;
input VAR6;
input [63 : 0] VAR115;
input [63 : 0] VAR150;
input VAR149;
input [1 ... | apache-2.0 |
luke-jr/ZtexBTCMiner | fpga/sha256_pipes2.v | 5,779 | module MODULE3 ( clk, VAR2, VAR3, out );
parameter VAR1 = 64;
input clk;
input [255:0] VAR2;
input [511:0] VAR3;
output [255:0] out;
localparam VAR14 = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32'h243185be, 32'h550c7dc3... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and2b/sky130_fd_sc_hdll__and2b.behavioral.v | 1,460 | module MODULE1 (
VAR10 ,
VAR7,
VAR6
);
output VAR10 ;
input VAR7;
input VAR6 ;
supply1 VAR8;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR9 ;
wire VAR12 ;
wire VAR4;
not VAR1 (VAR12 , VAR7 );
and VAR11 (VAR4, VAR12, VAR6 );
buf VAR5 (VAR10 , VAR4 );
endmodule | apache-2.0 |
bsteinsbo/DE1-SoC-Sound | cores/i2s/playback_fifo_bb.v | 6,586 | module MODULE1 (
VAR8,
VAR5,
VAR11,
VAR10,
VAR12,
VAR6,
VAR3,
VAR1,
VAR9,
VAR2,
VAR4,
VAR7);
input VAR8;
input [31:0] VAR5;
input VAR11;
input VAR10;
input VAR12;
input VAR6;
output [63:0] VAR3;
output VAR1;
output VAR9;
output VAR2;
output VAR4;
output [4:0] VAR7;
tri0 VAR8;
endmodule | lgpl-2.1 |
fallen/milkymist-mmu | cores/tmu2/rtl/tmu2_hdivops.v | 1,885 | module MODULE1(
input VAR2,
input VAR20,
output VAR4,
input VAR14,
output VAR12,
input signed [11:0] VAR10,
input signed [11:0] VAR5,
input signed [17:0] VAR15,
input signed [17:0] VAR16,
input signed [17:0] VAR6,
input signed [17:0] VAR7,
output reg VAR11,
input VAR13,
output reg signed [11:0] VAR18,
output reg signed... | lgpl-3.0 |
Kumikomi/openreroc_posturesensor | hardware/src/MPU_accel_controller.v | 12,859 | module MODULE1(
input clk,
input reset,
output reg [15:0] VAR36, output reg [15:0] VAR23, output reg [15:0] VAR2,
output VAR14, output VAR45, output VAR9, input VAR8, output reg VAR40
);
parameter VAR29 = 0,
VAR31 = 1,
VAR15 = 2,
VAR4 = 3,
VAR48 = 4,
VAR47 = 5,
VAR38 = 6,
VAR42 = 7,
VAR26 = 8,
VAR19 = 9,
VAR22 = 10,
VA... | bsd-3-clause |
saiedhk/WhirlpoolHashEngine | whirlpool_wcipher_mu_inverse.v | 3,315 | module MODULE1 (
output [0:511] VAR63,
input [7:0] VAR33, VAR17, VAR42, VAR19, VAR58, VAR18, VAR46, VAR35,
VAR6, VAR28, VAR36, VAR30, VAR24, VAR2, VAR65, VAR31,
VAR51, VAR32, VAR5, VAR50, VAR41, VAR52, VAR7, VAR10,
VAR22, VAR60, VAR27, VAR14, VAR11, VAR38, VAR37, VAR47,
VAR49, VAR13, VAR12, VAR26, VAR48, VAR44, VAR25, ... | mit |
trun/fpgaboy | src/gb/mmu.v | 3,461 | module MODULE1(
input wire VAR21,
input wire reset,
input wire [15:0] VAR17,
input wire [7:0] VAR24, output wire [7:0] VAR35, input wire VAR16,
input wire VAR25,
output wire [15:0] VAR27,
output wire [7:0] VAR30,
input wire [7:0] VAR2,
output wire VAR28,
output wire VAR15,
output wire VAR31,
output wire [15:0] VAR20,
o... | mit |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/proj_pointer_basic_hls_ip_integ/proj_pointer_basic_hls_ip_integ.srcs/sources_1/bd/design_1/ip/design_1_rst_ps7_0_50M_0/design_1_rst_ps7_0_50M_0_stub.v | 1,822 | module MODULE1(VAR8, VAR5, VAR2,
VAR4, VAR9, VAR10, VAR1, VAR3,
VAR7, VAR6)
;
input VAR8;
input VAR5;
input VAR2;
input VAR4;
input VAR9;
output VAR10;
output [0:0]VAR1;
output [0:0]VAR3;
output [0:0]VAR7;
output [0:0]VAR6;
endmodule | mit |
GSejas/Karatsuba_FPU | ASIC_FLOW/global_sources/KOA_c_2_ASIC.v | 7,597 | module MODULE1
(
input wire [VAR16-1:0] VAR28,
input wire [VAR16-1:0] VAR37,
output wire [2*VAR16-1:0] VAR9
);
wire [VAR16/2+1:0] VAR12;
wire [VAR16/2+1:0] VAR3;
wire [2*(VAR16/2)-1:0] VAR8;
wire [2*(VAR16/2+1)-1:0] VAR31;
wire [2*(VAR16/2+2)-1:0] VAR22;
wire [2*(VAR16/2+2)-1:0] VAR36;
wire [2*(VAR16/2+2)-1:0] VAR7;
wi... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | models/udp_dlatch_lp/sky130_fd_sc_hd__udp_dlatch_lp.symbol.v | 1,300 | module MODULE1 (
input VAR1 ,
output VAR3 ,
input VAR2
);
endmodule | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project.xpr/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_1/synth/design_1_auto_pc_1.v | 16,145 | module MODULE1 (
VAR54,
VAR15,
VAR50,
VAR91,
VAR40,
VAR44,
VAR27,
VAR34,
VAR38,
VAR92,
VAR95,
VAR86,
VAR48,
VAR19,
VAR87,
VAR73,
VAR108,
VAR58,
VAR80,
VAR66,
VAR109,
VAR25,
VAR39,
VAR78,
VAR74,
VAR5,
VAR102,
VAR45,
VAR59,
VAR85,
VAR31,
VAR29,
VAR77,
VAR65,
VAR103,
VAR90,
VAR100,
VAR1,
VAR10,
VAR101,
VAR37,
VAR20,
VAR98... | mit |
nliu96/openHMC_Altera | src/openhmc_8x_rf.v | 19,042 | module MODULE1 (
input wire clk,
input wire VAR66,
input wire[6:3] address,
output reg VAR16,
output reg VAR60,
input wire VAR14,
output reg[63:0] VAR38,
input wire VAR74,
input wire[63:0] VAR37,
input wire VAR4,
input wire VAR17,
input wire VAR13,
input wire VAR33,
input wire VAR9,
input wire[9:0] VAR34,
input wire[9:... | lgpl-3.0 |
FAST-Switch/fast | projects/SDTS/example/hw-src/ddr2/ddr2_bb.v | 3,234 | module MODULE1 (
VAR36,
VAR29,
VAR15,
VAR10,
VAR7,
VAR24,
VAR3,
VAR28,
VAR20,
VAR12,
VAR2,
VAR18,
VAR16,
VAR5,
VAR14,
VAR31,
VAR33,
VAR9,
VAR23,
VAR34,
VAR21,
VAR1,
VAR13,
VAR26,
VAR19,
VAR37,
VAR22,
VAR35,
VAR17,
VAR8,
VAR11,
VAR25,
VAR4,
VAR30,
VAR6,
VAR32,
VAR27);
input [23:0] VAR36;
input VAR29;
input VAR15;
input ... | apache-2.0 |
jameshegarty/rigel | misc/lt_float32_float32_bool.v | 19,521 | module MODULE1 (
VAR56, VAR232, VAR243, out
);
parameter VAR119="VAR148";
input wire VAR56;
input wire VAR232;
input [63 : 0] VAR243;
output [0:0] out;
wire clk;
assign clk=VAR56;
wire [31:0] VAR40;
wire [31:0] VAR18;
wire [0:0] VAR73;
assign VAR40 = VAR243[31:0];
assign VAR18 = VAR243[63:32];
assign out = VAR73;
wire ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2111a/sky130_fd_sc_lp__o2111a_0.v | 2,448 | module MODULE2 (
VAR11 ,
VAR8 ,
VAR6 ,
VAR9 ,
VAR5 ,
VAR2 ,
VAR7,
VAR10,
VAR1 ,
VAR12
);
output VAR11 ;
input VAR8 ;
input VAR6 ;
input VAR9 ;
input VAR5 ;
input VAR2 ;
input VAR7;
input VAR10;
input VAR1 ;
input VAR12 ;
VAR4 VAR3 (
.VAR11(VAR11),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR7(V... | apache-2.0 |
jeffkub/n64-cart-reader | old/hdl/n64_console_bridge/n64_console_ram.v | 7,494 | module MODULE1 (VAR83, VAR112, VAR54, VAR93, VAR4,
VAR9, VAR80, VAR61, VAR95, VAR107);
input wire [7:0] VAR83;
input wire [7:0] VAR112;
input wire [15:0] VAR54;
input wire VAR93;
input wire VAR4;
input wire VAR9;
input wire VAR80;
input wire VAR61;
input wire VAR95;
output wire [15:0] VAR107;
wire VAR79;
wire VAR108;
V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfbbp/sky130_fd_sc_hs__sdfbbp.functional.v | 2,455 | module MODULE1 (
VAR23 ,
VAR17 ,
VAR5 ,
VAR7 ,
VAR16 ,
VAR20 ,
VAR15 ,
VAR21,
VAR4 ,
VAR2
);
output VAR23 ;
output VAR17 ;
input VAR5 ;
input VAR7 ;
input VAR16 ;
input VAR20 ;
input VAR15 ;
input VAR21;
input VAR4 ;
input VAR2 ;
wire VAR22 ;
wire VAR14 ;
wire VAR13 ;
wire VAR6;
not VAR9 (VAR22 , VAR21 );
not VAR3 (VAR... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_misc/rtl/bw_io_misc_chunk3.v | 5,549 | module MODULE1(VAR19 ,VAR3 ,VAR38 ,
VAR1 ,VAR55 ,VAR2 ,VAR13 ,
VAR52 ,VAR5 ,clk ,VAR47 ,VAR42 ,VAR39 ,VAR11 ,VAR9 ,
VAR56 ,VAR4 ,VAR32 ,VAR30 ,VAR21 ,VAR51 ,VAR12 ,
VAR29 ,VAR40 ,VAR7 ,VAR50 ,VAR28 ,VAR36 ,VAR24 ,VAR33 ,VAR43 ,
VAR18 ,VAR46 ,VAR10 );
output [0:0] VAR55 ;
input [0:0] VAR1 ;
input [5:4] VAR56 ;
input [0:... | gpl-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/mc/mvd_can_mv_addr.v | 14,094 | module MODULE1(
VAR1 ,
VAR24 ,
VAR15 ,
VAR17 ,
VAR14 ,
VAR9 ,
VAR6 ,
VAR7 ,
VAR20 ,
VAR13
);
input [(VAR27)-1:0] VAR1 ; input [(VAR4)-1:0] VAR24 ; input [(VAR27)-1:0] VAR15 ; input [(VAR4)-1:0] VAR17 ;
input [ 6-1:0] VAR14 ;
input [ 6-1:0] VAR9 ;
input [ 7-1:0] VAR6 ;
input [ 7-1:0] VAR7 ;
output [ 8-1:0] VAR20 ;
outpu... | gpl-3.0 |
combinatorylogic/soc | backends/c2/hw/rtl/div1.v | 2,275 | module MODULE1(clk, rst, VAR15, VAR9,
VAR12, VAR7);
parameter VAR13 = 32;
localparam VAR18 = VAR13*2;
localparam VAR17 = VAR18 / 2;
input clk;
input rst;
input [VAR13 -1:0] VAR15;
input [VAR17 -1:0] VAR9;
output [VAR17 -1:0] VAR12;
output [VAR17 -1:0] VAR7;
reg [VAR17-1:0] VAR12;
reg [VAR17-1:0] VAR7;
function [VAR18:0... | mit |
Cognoscan/BoostDSP | verilog/src/signalGen/trigTable.v | 2,310 | module MODULE1 #(
parameter VAR7 = 12,
parameter VAR1 = 18
) (
input wire clk, input wire [VAR7-1:0] VAR14, output reg signed [VAR1-1:0] VAR4, output reg signed [VAR1-1:0] VAR8 );
localparam VAR12 = 2**(VAR7-2);
wire [VAR7-3:0] VAR9;
wire [VAR7-3:0] VAR10;
reg [VAR1-2:0] VAR11 [VAR12-1:0];
reg VAR13;
reg VAR2;
reg [VAR... | apache-2.0 |
chimeh/stopwatch_verilog | src/module_top.v | 4,301 | module MODULE1(
input VAR11, input VAR45, input VAR59, output [7:0] VAR55, output [7:0] VAR10);
wire VAR58;
wire VAR19;
wire VAR24;
wire VAR51;
wire VAR9;
wire VAR32;
wire VAR34;
wire [3:0] VAR27;
wire [3:0] VAR22;
wire [3:0] VAR8;
wire [3:0] VAR43;
wire [3:0] VAR56;
wire [3:0] VAR21;
wire [3:0] VAR36;
wire [3:0] VAR38... | unlicense |
maijohnson/comp3601_blue_15s2 | AudioController/BPM_lut.v | 8,967 | module MODULE1(VAR1, VAR2);
input [7:0] VAR1;
output [19:0] VAR2;
assign VAR2 =(VAR1 == 8'd1) ? 1000000 :
(VAR1 == 8'd2) ? 500000 :
(VAR1 == 8'd3) ? 333333 :
(VAR1 == 8'd4) ? 250000 :
(VAR1 == 8'd5) ? 200000 :
(VAR1 == 8'd6) ? 166667 :
(VAR1 == 8'd7) ? 142857 :
(VAR1 == 8'd8) ? 125000 :
(VAR1 == 8'd9) ? 111111 :
(VAR1 ... | mit |
KorotkiyEugene/Netmaker_vc_router_syn_quartus | NW_vc_status.v | 2,831 | module MODULE1 (VAR21,
VAR2,
VAR17,
VAR5,
VAR19,
VAR3,
VAR14);
parameter VAR13=5;
parameter VAR4=4;
parameter VAR1 = 0;
input VAR26 VAR21 [VAR13-1:0][VAR4-1:0];
input [VAR13-1:0] VAR2; input [VAR4-1:0] VAR5 [VAR13-1:0][VAR4-1:0]; input [VAR13-1:0][VAR4-1:0] VAR19; input [VAR13-1:0][VAR4-1:0] VAR3; output [VAR13-1:0][VA... | gpl-2.0 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.