repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/FPU_Interface/fpu/FPU_Interface2v1.v | 10,677 | module MODULE1 #(parameter VAR1 = 64, VAR35 = 11, VAR79 = 52, VAR30 = 55, VAR108 = 6)
(
input wire clk,
input wire rst,
input wire VAR19,
input wire VAR38,
input wire [2:0] VAR3,
input wire [1:0] VAR61,
input wire [VAR1-1:0] VAR20,
input wire [VAR1-1:0] VAR50,
input wire [1:0] VAR53,
output wire VAR9,
output wire VAR98... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a211oi/sky130_fd_sc_ms__a211oi.behavioral.v | 1,553 | module MODULE1 (
VAR5 ,
VAR8,
VAR9,
VAR11,
VAR1
);
output VAR5 ;
input VAR8;
input VAR9;
input VAR11;
input VAR1;
supply1 VAR2;
supply0 VAR14;
supply1 VAR6 ;
supply0 VAR10 ;
wire VAR4 ;
wire VAR3;
and VAR7 (VAR4 , VAR8, VAR9 );
nor VAR12 (VAR3, VAR4, VAR11, VAR1);
buf VAR13 (VAR5 , VAR3 );
endmodule | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_3L_019bits.v | 1,917 | module MODULE2 (
clk,
VAR24, VAR11, VAR10, VAR22, VAR9, VAR18, VAR31, VAR3,
sum,
);
input clk;
input [VAR8+0-1:0] VAR24, VAR11, VAR10, VAR22, VAR9, VAR18, VAR31, VAR3;
output [VAR8 :0] sum;
reg [VAR8 :0] sum;
wire [VAR8+3-1:0] VAR1;
wire [VAR8+2-1:0] VAR30, VAR4;
wire [VAR8+1-1:0] VAR15, VAR25, VAR27, VAR34;
reg [VAR8+... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/ha/sky130_fd_sc_lp__ha.behavioral.v | 1,511 | module MODULE1 (
VAR13,
VAR12 ,
VAR1 ,
VAR11
);
output VAR13;
output VAR12 ;
input VAR1 ;
input VAR11 ;
supply1 VAR8;
supply0 VAR14;
supply1 VAR4 ;
supply0 VAR10 ;
wire VAR5;
wire VAR2 ;
and VAR9 (VAR5, VAR1, VAR11 );
buf VAR7 (VAR13 , VAR5 );
xor VAR3 (VAR2 , VAR11, VAR1 );
buf VAR6 (VAR12 , VAR2 );
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_channel_tunnel_wormhole.v | 22,174 | module MODULE1
,parameter VAR85(VAR14)
,parameter VAR85(VAR134)
,parameter VAR85(VAR129)
,parameter VAR85(VAR69)
,parameter VAR85(VAR127)
,parameter VAR85(VAR41)
,parameter VAR85(VAR103)
,parameter VAR48 = VAR20(VAR73(VAR41+1),4)
,parameter VAR150 = 1
,localparam VAR1 = VAR56(VAR49)
)
(input VAR158
,input VAR130
,input... | bsd-3-clause |
hcabrera-/lancetfish | RTL/nic/des_nic/rtl/des_nic_output_control_unit.v | 7,639 | module MODULE1
(
input wire clk,
input wire reset,
input wire VAR18,
input wire VAR12,
output wire VAR17,
output wire [2:0] VAR22
);
localparam VAR8 = 2'b00;
localparam VAR15 = 2'b01;
localparam VAR9 = 2'b10;
localparam VAR1 = 1'b1;
localparam VAR4 = 1'b0;
localparam VAR20 = VAR13/5;
localparam VAR19 = VAR24(VAR20);
re... | gpl-3.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_gpio_0_1/zqynq_lab_1_design_axi_gpio_0_1_stub.v | 2,370 | module MODULE1(VAR15, VAR11, VAR3,
VAR1, VAR9, VAR18, VAR16, VAR7, VAR8,
VAR14, VAR20, VAR10, VAR6, VAR2, VAR4,
VAR13, VAR12, VAR19, VAR17, VAR5)
;
input VAR15;
input VAR11;
input [8:0]VAR3;
input VAR1;
output VAR9;
input [31:0]VAR18;
input [3:0]VAR16;
input VAR7;
output VAR8;
output [1:0]VAR14;
output VAR20;
input VAR... | mit |
TalentlessAlpaca/Automated_Vacuum_Cleaner | Timer_Counter/Timer_Peripheral.v | 1,963 | module MODULE1 (clk , rst , din , VAR5 , addr , rd , wr, dout );
input clk;
input rst;
input [15:0] din;
input VAR5;
input [3:0] addr;
input rd;
input wr;
output reg [15:0] dout;
reg [5:0] VAR3;
reg [31:0] VAR8;
reg [31:0] VAR4;
reg en=0;
wire VAR1;
wire VAR7;
always @(*) begin
case (addr)
4'h0:begin VAR3 = (VAR5 && wr... | mit |
cybero/Verilog | src/BRAM + checker/rtl/debouncer.v | 1,521 | module MODULE1(
input clk, input reset,
input VAR3,
output reg VAR2, output VAR1, output VAR4 );
reg VAR6; always @(posedge clk) VAR6 <= VAR3; reg VAR8; always @(posedge clk) VAR8 <= VAR6;
reg [7:0] VAR9;
wire VAR5 = (VAR2==VAR8);
wire VAR7 = &VAR9;
always @(posedge clk, posedge reset)
if(reset)begin
VAR9 <= 0;
VAR2 <=... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfstp/sky130_fd_sc_hvl__sdfstp.functional.v | 1,949 | module MODULE1 (
VAR10 ,
VAR8 ,
VAR5 ,
VAR7 ,
VAR2 ,
VAR6
);
output VAR10 ;
input VAR8 ;
input VAR5 ;
input VAR7 ;
input VAR2 ;
input VAR6;
wire VAR13 ;
wire VAR16 ;
wire VAR12;
not VAR14 (VAR16 , VAR6 );
VAR3 VAR4 (VAR12, VAR5, VAR7, VAR2 );
VAR15 VAR1 VAR9 (VAR13 , VAR12, VAR8, VAR16);
buf VAR11 (VAR10 , VAR13 );
end... | apache-2.0 |
rkrajnc/minimig-de1 | rtl/mor1kx/mor1kx_pic.v | 3,870 | module MODULE1
(
VAR19, VAR2, VAR26, VAR9,
clk, rst, VAR30, VAR21, VAR28, VAR17, VAR31
);
parameter VAR27="VAR15";
parameter VAR20 = 0;
input clk;
input rst;
input [31:0] VAR30;
output [31:0] VAR19;
output [31:0] VAR2;
input VAR21;
input VAR28;
input [15:0] VAR17;
input [31:0] VAR31;
output VAR26;
output [31:0] VAR9;
r... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_4.functional.v | 1,264 | module MODULE1( VAR3, VAR12, VAR11, VAR7 );
input VAR11, VAR3, VAR7;
output VAR12;
wire VAR8;
not VAR4( VAR8, VAR11 );
wire VAR9;
not VAR13( VAR9, VAR3 );
wire VAR6;
and VAR2( VAR6, VAR8, VAR9 );
wire VAR5;
not VAR1( VAR5, VAR7 );
or VAR10( VAR12, VAR6, VAR5 );
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_amphy/alt_mem_ddrx_addr_cmd_wrap.v | 50,227 | module MODULE1
VAR77 = 2,
VAR161 = 2, VAR147 = 16, VAR60 = 16, VAR166 = 12, VAR57 = 3, VAR109 = 1,
VAR173 = 3,
VAR12 = 2,
VAR10 = 2,
VAR127 = 8,
VAR49 = 4,
VAR103 = 4,
VAR141 = 1,
VAR69 = 2,
VAR42 = 5,
VAR168 = 5,
VAR27 = 5,
VAR160 = 4,
VAR175 = 4,
VAR179 = 1
)
(
VAR87,
VAR70,
VAR68,
VAR153,
VAR203,
VAR170,
VAR44,
VAR7... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2111ai/sky130_fd_sc_lp__o2111ai.pp.blackbox.v | 1,435 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR9 ,
VAR1 ,
VAR6 ,
VAR7 ,
VAR3,
VAR2,
VAR8 ,
VAR10
);
output VAR5 ;
input VAR4 ;
input VAR9 ;
input VAR1 ;
input VAR6 ;
input VAR7 ;
input VAR3;
input VAR2;
input VAR8 ;
input VAR10 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_2.v | 2,466 | module MODULE1 (
VAR4 ,
VAR6 ,
VAR8 ,
VAR3 ,
VAR9 ,
VAR1 ,
VAR11,
VAR12,
VAR7 ,
VAR5
);
output VAR4 ;
input VAR6 ;
input VAR8 ;
input VAR3 ;
input VAR9 ;
input VAR1 ;
input VAR11;
input VAR12;
input VAR7 ;
input VAR5 ;
VAR10 VAR2 (
.VAR4(VAR4),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR11(VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o32a/sky130_fd_sc_ms__o32a.symbol.v | 1,383 | module MODULE1 (
input VAR8,
input VAR6,
input VAR7,
input VAR2,
input VAR10,
output VAR9
);
supply1 VAR3;
supply0 VAR5;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o32ai/sky130_fd_sc_lp__o32ai_2.v | 2,441 | module MODULE1 (
VAR7 ,
VAR4 ,
VAR6 ,
VAR8 ,
VAR3 ,
VAR10 ,
VAR11,
VAR2,
VAR12 ,
VAR1
);
output VAR7 ;
input VAR4 ;
input VAR6 ;
input VAR8 ;
input VAR3 ;
input VAR10 ;
input VAR11;
input VAR2;
input VAR12 ;
input VAR1 ;
VAR5 VAR9 (
.VAR7(VAR7),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR11(... | apache-2.0 |
linuxbest/lzs | decode/rtl/verilog/decode_out.v | 1,418 | module MODULE1 (
VAR1, VAR6, VAR2,
clk, rst, VAR5, VAR7, VAR4
);
input clk,
rst;
input VAR5, VAR7;
input [7:0] VAR4;
output [15:0] VAR1;
output VAR6, VAR2;
reg [15:0] VAR1;
reg VAR2;
reg VAR6;
reg VAR3;
always @(posedge clk or posedge rst)
begin
if (rst)
VAR3 <= 1'b0;
end
else if (VAR5)
VAR3 <= VAR3 + 1'b1;
end
always ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfsbp/sky130_fd_sc_hvl__dfsbp.behavioral.v | 2,158 | module MODULE1 (
VAR8 ,
VAR1 ,
VAR12 ,
VAR2 ,
VAR14
);
output VAR8 ;
output VAR1 ;
input VAR12 ;
input VAR2 ;
input VAR14;
supply1 VAR18;
supply0 VAR19;
supply1 VAR5 ;
supply0 VAR16 ;
wire VAR6 ;
wire VAR7 ;
reg VAR17 ;
wire VAR20 ;
wire VAR10 ;
wire VAR4;
wire VAR3 ;
not VAR21 (VAR7 , VAR4 );
VAR9 VAR13 (VAR6 , VAR10,... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlxbn/sky130_fd_sc_lp__dlxbn.pp.blackbox.v | 1,362 | module MODULE1 (
VAR2 ,
VAR7 ,
VAR6 ,
VAR1,
VAR5 ,
VAR8 ,
VAR4 ,
VAR3
);
output VAR2 ;
output VAR7 ;
input VAR6 ;
input VAR1;
input VAR5 ;
input VAR8 ;
input VAR4 ;
input VAR3 ;
endmodule | apache-2.0 |
asicguy/gplgpu | hdl/ramdac_sp/cursor.v | 30,179 | module MODULE1
(
input VAR177,
input reset,
input VAR98,
input VAR168,
input VAR100,
input VAR165,
input VAR65,
input [7:0] VAR18,
input [7:0] VAR120,
input [7:0] VAR29,
input [7:0] VAR134,
input [7:0] VAR36,
input [7:0] VAR102,
input [7:0] VAR124,
input [7:0] VAR196,
input [7:0] VAR122,
input [7:0] VAR53,
input [7:0] ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/bufbuf/sky130_fd_sc_hs__bufbuf.functional.pp.v | 1,666 | module MODULE1 (
VAR8,
VAR4,
VAR3 ,
VAR1
);
input VAR8;
input VAR4;
output VAR3 ;
input VAR1 ;
wire VAR5 ;
wire VAR2;
buf VAR10 (VAR5 , VAR1 );
VAR6 VAR7 (VAR2, VAR5, VAR8, VAR4);
buf VAR9 (VAR3 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or4bb/sky130_fd_sc_hdll__or4bb.behavioral.v | 1,518 | module MODULE1 (
VAR5 ,
VAR11 ,
VAR2 ,
VAR12,
VAR14
);
output VAR5 ;
input VAR11 ;
input VAR2 ;
input VAR12;
input VAR14;
supply1 VAR6;
supply0 VAR13;
supply1 VAR8 ;
supply0 VAR4 ;
wire VAR10;
wire VAR7;
nand VAR3 (VAR10, VAR14, VAR12 );
or VAR1 (VAR7, VAR2, VAR11, VAR10);
buf VAR9 (VAR5 , VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlygate4sd1/sky130_fd_sc_ms__dlygate4sd1.functional.v | 1,309 | module MODULE1 (
VAR3,
VAR5
);
output VAR3;
input VAR5;
wire VAR1;
buf VAR2 (VAR1, VAR5 );
buf VAR4 (VAR3 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2111a/sky130_fd_sc_hs__o2111a.functional.pp.v | 1,975 | module MODULE1 (
VAR15,
VAR11,
VAR3 ,
VAR5 ,
VAR2 ,
VAR12 ,
VAR6 ,
VAR16
);
input VAR15;
input VAR11;
output VAR3 ;
input VAR5 ;
input VAR2 ;
input VAR12 ;
input VAR6 ;
input VAR16 ;
wire VAR6 VAR9 ;
wire VAR4 ;
wire VAR14;
or VAR10 (VAR9 , VAR2, VAR5 );
and VAR8 (VAR4 , VAR12, VAR6, VAR9, VAR16 );
VAR13 VAR1 (VAR14, V... | apache-2.0 |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/ui/mig_7series_v2_0_ui_rd_data.v | 19,378 | module MODULE1 #
(
parameter VAR94 = 100,
parameter VAR54 = 256,
parameter VAR47 = 5,
parameter VAR8 = "VAR71",
parameter VAR49 = 2 ,
parameter VAR22 = "VAR16"
)
(
VAR29, VAR20, VAR76, VAR5,
VAR85, VAR84, VAR73, VAR32,
rst, clk, VAR3, VAR59, VAR9, VAR24,
VAR83, VAR40, VAR34
);
input rst;
input clk;
output wire VAR29;
o... | bsd-2-clause |
FPGA1988/udp_ip_stack | Network/udp_ip_core/trunk/ic/digital/rtl/sys_aux_module/sys_led_module.v | 6,161 | module MODULE1(
VAR5 , VAR6 , VAR2 , VAR1 );
input VAR5 ; input VAR6 ; input [07:00] VAR2 ; output [07:00] VAR1 ;
reg [09:00] VAR3 ; wire VAR5 ;
wire VAR6 ;
wire [07:00] VAR2 ;
wire [07:00] VAR1 ;
always @(posedge VAR5 or negedge VAR6) begin : VAR4
if(!VAR6)
begin
VAR3 <= 'd0;
end
else
begin
VAR3 <= VAR3 + 1'b1;
end
en... | apache-2.0 |
timofonic/fpga_nes | hw/src/ppu/ppu_vga.v | 8,403 | module MODULE1
(
input wire VAR10, input wire VAR13, input wire [5:0] VAR32, output wire VAR5, output wire VAR26, output wire [2:0] VAR4, output wire [2:0] VAR23, output wire [1:0] VAR11, output wire [9:0] VAR20, output wire [9:0] VAR28, output wire [9:0] VAR36, output wire VAR25, output wire VAR9 );
localparam [9:0] V... | bsd-2-clause |
trivoldus28/pulsarch-verilog | design/sys/iop/scbuf/rtl/scbuf_sig_buf.v | 2,334 | module MODULE1 (
VAR12, VAR8,
VAR11, VAR1,
VAR10, VAR6,
VAR3, VAR2,
VAR7, VAR9,
VAR5, VAR4
);
output [623:0] VAR12;
output [63:0] VAR8;
output VAR11;
output VAR1;
output VAR10;
output VAR6;
input [623:0] VAR3;
input [63:0] VAR2;
input VAR7;
input VAR9;
input VAR5;
input VAR4;
assign VAR12[623:0] = VAR3[623:0];
assign V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor4b/sky130_fd_sc_hs__nor4b.functional.pp.v | 1,890 | module MODULE1 (
VAR11,
VAR9,
VAR15 ,
VAR2 ,
VAR6 ,
VAR3 ,
VAR14
);
input VAR11;
input VAR9;
output VAR15 ;
input VAR2 ;
input VAR6 ;
input VAR3 ;
input VAR14 ;
wire VAR14 VAR8 ;
wire VAR1 ;
wire VAR7;
not VAR10 (VAR8 , VAR14 );
nor VAR12 (VAR1 , VAR2, VAR6, VAR3, VAR8 );
VAR5 VAR13 (VAR7, VAR1, VAR11, VAR9);
buf VAR4 ... | apache-2.0 |
chiralhat/fpga-pulses-ice | ECP5/pulses2.v | 8,208 | module MODULE1(
input VAR38, input reset, input VAR35, input [7:0] VAR18,
input [15:0] VAR11,
input [15:0] VAR51,
input [15:0] VAR31,
input [31:0] VAR27,
input [31:0] VAR47,
input VAR15,
input [7:0] VAR43,
input [7:0] VAR12,
input [15:0] VAR39,
input VAR7,
input VAR19,
output VAR48, output VAR29, output VAR3 );
reg [31... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfstp/sky130_fd_sc_hvl__sdfstp.symbol.v | 1,502 | module MODULE1 (
input VAR1 ,
output VAR9 ,
input VAR7,
input VAR8 ,
input VAR5 ,
input VAR6
);
supply1 VAR3;
supply0 VAR10;
supply1 VAR4 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_4.functional.pp.v | 1,081 | module MODULE1( VAR2, VAR10, VAR11, VAR1, VAR3, VAR6, VAR8 );
input VAR11, VAR10, VAR2, VAR3, VAR6, VAR8;
output VAR1;
or VAR13( VAR5, VAR10, VAR2 );
VAR12( VAR14, 1'b0, 1'b0, VAR11, VAR5, VAR8 );
wire VAR7;
not VAR4( VAR7, VAR14 );
or VAR9( VAR1, VAR11, VAR7 );
endmodule | apache-2.0 |
asicguy/gplgpu | hdl/lucy_tc/de3d_tc_mem_if_addr.v | 5,323 | module MODULE1
(
input [8:0] VAR3,
input [8:0] VAR12,
input [8:0] VAR5,
input [8:0] VAR7,
input [8:0] VAR6,
input [8:0] VAR2,
input [8:0] VAR16,
input [8:0] VAR9,
input [2:0] VAR17,
input [2:0] VAR13,
input VAR4,
input [7:0] VAR11,
input [3:0] VAR10,
output reg [7:0] VAR15
);
wire VAR1 = VAR10[3];
wire VAR14 = VAR10[2]... | gpl-3.0 |
FAST-Switch/fast | lib/hardware/pipeline/UM_OPENFLOW/bv-288/lookup_9bit.v | 2,123 | module MODULE1(
clk,
reset,
VAR10,
VAR20,
VAR9,
addr,
VAR12,
VAR15,
VAR30,
VAR13,
VAR25,
VAR29
);
input clk;
input reset;
input VAR10;
input [35:0] VAR20;
input VAR9;
input [8:0] addr;
output reg VAR12;
output reg [35:0] VAR15;
input VAR30;
input [8:0] VAR13;
output wire VAR25;
output wire [35:0] VAR29;
wire VAR27;
reg... | apache-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/clock_generator.v | 8,152 | module MODULE1
( input VAR86,
output VAR14,
output VAR106,
output VAR47,
output VAR95,
output VAR58,
output VAR42,
input VAR2
);
wire [15:0] VAR8;
wire VAR78;
wire VAR85;
wire VAR61;
wire VAR25;
wire VAR7;
wire VAR65;
wire VAR35;
wire VAR9;
wire VAR3;
wire VAR15;
wire VAR83;
wire VAR57;
wire VAR34;
VAR37
.VAR48 ("VAR32... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a2111o/sky130_fd_sc_ls__a2111o.symbol.v | 1,393 | module MODULE1 (
input VAR1,
input VAR9,
input VAR2,
input VAR10,
input VAR4,
output VAR5
);
supply1 VAR3;
supply0 VAR7;
supply1 VAR8 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
ptracton/wb_soc_template | rtl/MOR1KX/rtl/verilog/mor1kx_ctrl_cappuccino.v | 52,678 | module MODULE1
parameter VAR228 = 32,
parameter VAR73 = {{(VAR228-13){1'b0}},
parameter VAR299 = "VAR220",
parameter VAR98 = "VAR220",
parameter VAR219 = "VAR220",
parameter VAR19 = "VAR109",
parameter VAR23 = 5,
parameter VAR202 = 9,
parameter VAR318 = 2,
parameter VAR217 = "VAR109",
parameter VAR155 = 6,
parameter VA... | mit |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_pwmgpioport.v | 3,325 | module MODULE1(
input VAR23,
input reset,
input VAR18,
input VAR22,
input VAR13,
input VAR12,
input VAR35,
output VAR15,
output VAR28,
output VAR5,
output VAR3,
output VAR31,
input VAR30,
output VAR19,
output VAR16,
output VAR25,
output VAR10,
output VAR29,
input VAR1,
output VAR32,
output VAR36,
output VAR34,
output V... | apache-2.0 |
VerticalResearchGroup/miaow | src/verilog/rtl/vgpr/reg_1024x32b_3r_1w.v | 2,306 | module MODULE1 (
VAR4, VAR5, VAR19,
VAR17, VAR8, VAR9, VAR13, VAR16, VAR11, clk
);
output [31:0] VAR4;
output [31:0] VAR5;
output [31:0] VAR19;
input [9:0] VAR17;
input [9:0] VAR8;
input [9:0] VAR9;
input [9:0] VAR13;
input [3:0] VAR16; input [31:0] VAR11;
input clk;
reg [31:0] VAR4;
reg [31:0] VAR5;
reg [31:0] VAR19;
... | bsd-3-clause |
olgirard/openmsp430 | fpga/OBSOLETE/altera_de1_board/rtl/verilog/OpenMSP430_fpga.v | 34,323 | module MODULE1
(
VAR146, VAR173, VAR38, VAR113, VAR57, VAR48, VAR117, VAR165, VAR200, VAR111, VAR161, VAR121, VAR151, VAR3, VAR213, VAR194, VAR15, VAR180, VAR157, VAR12, VAR69, VAR41, VAR2, VAR189, VAR184, VAR120, VAR34, VAR37, VAR144, VAR206, VAR80, VAR195, VAR181, VAR50, VAR104, VAR65, VAR109, VAR40, VAR219, VAR13, V... | bsd-3-clause |
marmolejo/zet | cores/vga/rtl/fml/vga_sequencer_fml.v | 5,617 | module MODULE1 (
input clk, input rst,
input VAR36,
input [9:0] VAR8,
input VAR3,
input [9:0] VAR29,
input VAR31,
input VAR39,
input VAR1,
input VAR2, input VAR15,
output [17:1] VAR25,
input [15:0] VAR40,
output VAR4,
input [5:0] VAR26,
input [5:0] VAR47,
input [4:0] VAR11,
input [6:0] VAR7,
input VAR38,
output VAR43,
... | gpl-3.0 |
markusC64/1541ultimate2 | fpga/nios_dut/nios_dut/nios_dut_bb.v | 1,902 | module MODULE1 (
VAR8,
VAR3,
VAR12,
VAR27,
VAR31,
VAR42,
VAR10,
VAR28,
VAR36,
VAR24,
VAR41,
VAR16,
VAR11,
VAR9,
VAR2,
VAR18,
VAR4,
VAR22,
VAR37,
VAR20,
VAR38,
VAR29,
VAR35,
VAR15,
VAR13,
VAR25,
VAR30,
VAR5,
VAR33,
VAR6,
VAR23,
VAR39,
VAR26,
VAR21,
VAR17,
VAR19,
VAR40,
VAR1,
VAR14,
VAR34,
VAR43,
VAR32,
VAR7);
input [31:... | gpl-3.0 |
jmesmon/trifles | verilog/hw5/p28_b.v | 2,145 | module MODULE2 #(parameter VAR13=8)
(output reg [VAR13:0] out,
input [VAR13-1:0] VAR10, VAR8, input VAR20, input [2:0]VAR29);
parameter [2:0]
VAR14 = 0,
VAR17 = 1,
VAR9 = 2,
VAR5 = 3,
VAR12 = 4,
VAR19 = 5,
VAR24 = 6,
VAR28 = 7;
always @(VAR10, VAR8, VAR29, VAR20)
case (VAR29)
VAR14: out <= VAR10 + VAR8 + VAR20;
VAR17: ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/einvp/sky130_fd_sc_ms__einvp_8.v | 2,130 | module MODULE2 (
VAR7 ,
VAR5 ,
VAR4 ,
VAR8,
VAR3,
VAR6 ,
VAR1
);
output VAR7 ;
input VAR5 ;
input VAR4 ;
input VAR8;
input VAR3;
input VAR6 ;
input VAR1 ;
VAR9 VAR2 (
.VAR7(VAR7),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR7 ,
VAR5 ,
VAR4
);
output VAR7... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/bufinv/sky130_fd_sc_ls__bufinv_8.v | 2,044 | module MODULE2 (
VAR5 ,
VAR4 ,
VAR3,
VAR8,
VAR6 ,
VAR1
);
output VAR5 ;
input VAR4 ;
input VAR3;
input VAR8;
input VAR6 ;
input VAR1 ;
VAR7 VAR2 (
.VAR5(VAR5),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR5,
VAR4
);
output VAR5;
input VAR4;
supply1 VAR3;
supply0 VAR8;... | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/lm32/rtl/lm32_shifter.v | 4,922 | module MODULE1 (
VAR18,
VAR21,
VAR5,
VAR3,
VAR9,
VAR22,
VAR4,
VAR24
);
input VAR18; input VAR21; input VAR5; input VAR3; input VAR9; input [VAR2] VAR22; input [VAR2] VAR4;
output [VAR2] VAR24; wire [VAR2] VAR24;
reg VAR17;
reg [VAR2] VAR6;
reg [VAR2] VAR8;
reg [VAR2] VAR10;
wire [VAR2] VAR7;
wire VAR13;
wire [VAR2] VAR... | lgpl-3.0 |
olgirard/openmsp430 | fpga/altera_de0_nano_soc/rtl/verilog/opengfx430/ogfx_if_lt24.v | 24,646 | module MODULE1 (
VAR7, VAR14,
VAR15, VAR53, VAR43, VAR49, VAR58, VAR75,
VAR39, VAR9,
VAR60,
VAR10, VAR50,
VAR55, VAR1, VAR71, VAR21, VAR80,
VAR69, VAR59,
VAR70, VAR61, VAR4, VAR51,
VAR62,
VAR2,
VAR18, VAR76 );
output VAR7; output VAR14;
output VAR15; output [15:0] VAR53; output VAR43; output VAR49; output VAR58; output... | bsd-3-clause |
JY-Kim/CA2016 | Sources/ALU_32bit.v | 2,060 | module MODULE1
(
input [31:0] VAR12,
input [31:0] VAR19,
input [3:0] VAR5,
output wire [31:0] VAR10,
output wire VAR6,
output wire VAR2
);
reg [31:0] VAR8;
wire [31:1] VAR20; wire VAR13; wire VAR17;
wire [31:0] VAR15;
assign VAR17 = 1'b0; assign VAR6 = !( |VAR10 ); assign VAR10 = VAR8;
VAR3 VAR16
(
.VAR12 ( VAR12[0] ),... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_16/bsg_mem/bsg_mem_1r1w_sync_mask_write_bit.v | 5,742 | if (VAR2 == VAR21 && VAR20 == VAR19) \
begin: VAR22 \
VAR37 VAR41 ( \
.VAR50 (VAR24) \
,.VAR12 (VAR56) \
,.VAR35 (~VAR6) \
,.VAR33 (VAR42) \
\
,.VAR17 (VAR27) \
,.VAR43 (VAR25) \
,.VAR30 (~VAR32) \
,.VAR39 (~VAR52) \
\
,.VAR55 (1'd0 ) \
,.VAR18(1'd0 ) \
,.VAR23 (3'd3 ) \
,.VAR54 (2'd1 ) \
,.VAR7 (1'b0 ) \
,.VAR40 (1'b0... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/xnor2/sky130_fd_sc_hs__xnor2.functional.pp.v | 1,725 | module MODULE1 (
VAR6,
VAR8,
VAR10 ,
VAR7 ,
VAR5
);
input VAR6;
input VAR8;
output VAR10 ;
input VAR7 ;
input VAR5 ;
wire VAR9 ;
wire VAR3;
xnor VAR4 (VAR9 , VAR7, VAR5 );
VAR11 VAR2 (VAR3, VAR9, VAR6, VAR8);
buf VAR1 (VAR10 , VAR3 );
endmodule | apache-2.0 |
Cognoscan/BoostLogic | verilog/src/decoders/GrayToBinary.v | 2,156 | module MODULE1 #(
parameter VAR7 = 32 )
(
input clk, input rst, input VAR5, input [VAR7-1:0] VAR2, output reg VAR4, output reg [VAR7-1:0] VAR3 );
parameter VAR6 = VAR9(VAR7);
reg [VAR7-1:0] VAR1 [VAR6-1:0];
integer VAR8;
always @(*) begin
VAR1[0] = VAR2 ^ (VAR2 >> (1 << (VAR6-1)));
for (VAR8=1; VAR8<VAR6; VAR8=VAR8+1) ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o211ai/sky130_fd_sc_ms__o211ai.blackbox.v | 1,368 | module MODULE1 (
VAR1 ,
VAR3,
VAR4,
VAR5,
VAR6
);
output VAR1 ;
input VAR3;
input VAR4;
input VAR5;
input VAR6;
supply1 VAR2;
supply0 VAR9;
supply1 VAR7 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor2/sky130_fd_sc_ms__nor2_4.v | 2,086 | module MODULE1 (
VAR8 ,
VAR9 ,
VAR3 ,
VAR6,
VAR2,
VAR5 ,
VAR4
);
output VAR8 ;
input VAR9 ;
input VAR3 ;
input VAR6;
input VAR2;
input VAR5 ;
input VAR4 ;
VAR1 VAR7 (
.VAR8(VAR8),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR8,
VAR9,
VAR3
);
output VAR8;
... | apache-2.0 |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/gcd_snickerdoodle/gcd_snickerdoodle.srcs/sources_1/bd/gcd_zynq_snick/ip/gcd_zynq_snick_auto_pc_0/synth/gcd_zynq_snick_auto_pc_0.v | 14,691 | module MODULE1 (
VAR112,
VAR62,
VAR49,
VAR77,
VAR113,
VAR76,
VAR2,
VAR47,
VAR32,
VAR72,
VAR23,
VAR57,
VAR111,
VAR46,
VAR78,
VAR87,
VAR81,
VAR89,
VAR56,
VAR54,
VAR106,
VAR66,
VAR69,
VAR90,
VAR36,
VAR70,
VAR65,
VAR73,
VAR52,
VAR31,
VAR107,
VAR85,
VAR103,
VAR109,
VAR110,
VAR99,
VAR14,
VAR86,
VAR45,
VAR94,
VAR83,
VAR33,
VA... | mit |
ZiCog/xoro | rtl/memory.v | 2,147 | module MODULE1 (
input VAR8,
input VAR17,
input VAR1,
input [3:0] VAR15,
input [31:0] VAR12,
input [15:0] VAR3,
output [31:0] VAR16,
output VAR10,
input clk,
input reset);
wire [31:0] VAR14;
wire [31:0] VAR5;
wire [3:0] VAR4;
wire VAR6;
reg [31:0] VAR2;
reg ready;
wire [13:0] addr;
reg [7:0] VAR13 [0:1024*10];
reg [7:0... | mit |
asicguy/gplgpu | hdl/mc_graph/mc_dat.v | 12,142 | module MODULE1
(
parameter VAR47 = 4
)
(
input VAR81,
input VAR32,
input [66:0] VAR13,
input VAR31,
input VAR54,
input [3:0] VAR46,
input [(VAR47*8)-1:0] VAR24,
input [(VAR47*8)-1:0] VAR35,
input [(VAR47*4)-1:0] VAR23,
input [(VAR47*8)-1:0] VAR2,
input [31:0] VAR19,
input [VAR47-1:0] VAR17,
input [VAR47-1:0] VAR49,
inp... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp.pp.blackbox.v | 1,367 | module MODULE1 (
VAR9 ,
VAR8 ,
VAR5 ,
VAR3 ,
VAR2 ,
VAR6,
VAR7,
VAR1 ,
VAR4
);
output VAR9 ;
input VAR8 ;
input VAR5 ;
input VAR3 ;
input VAR2 ;
input VAR6;
input VAR7;
input VAR1 ;
input VAR4 ;
endmodule | apache-2.0 |
alexforencich/xfcp | example/VCU118/fpga_gty/rtl/fpga_core.v | 16,767 | module MODULE1
(
input wire clk,
input wire rst,
input wire VAR217,
input wire VAR41,
input wire VAR242,
input wire VAR126,
input wire VAR152,
input wire [3:0] VAR83,
output wire [7:0] VAR122,
input wire VAR232,
output wire VAR17,
output wire VAR194,
input wire VAR134,
output wire VAR123,
output wire VAR226,
input wire... | mit |
niketancm/tsea26 | lab2-3/rtl/id_pipeline_logic.v | 9,282 | module MODULE1
(
input wire VAR11,
input wire VAR66,
input wire [VAR60-1:0] VAR69,
input wire [VAR96-1:0] VAR48,
input wire [VAR53-1:0] VAR42,
input wire [VAR75-1:0] VAR71,
input wire [VAR94-1:0] VAR34,
input wire [VAR1-1:0] VAR13,
input wire [VAR14-1:0] VAR88,
input wire [VAR39-1:0] VAR18,
input wire [VAR5-1:0] VAR52,... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand2/sky130_fd_sc_ms__nand2.pp.blackbox.v | 1,266 | module MODULE1 (
VAR6 ,
VAR5 ,
VAR7 ,
VAR1,
VAR4,
VAR2 ,
VAR3
);
output VAR6 ;
input VAR5 ;
input VAR7 ;
input VAR1;
input VAR4;
input VAR2 ;
input VAR3 ;
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_min/rtl/jbi_min_wrtrk.v | 8,605 | module MODULE1 (
VAR16, VAR26, VAR1,
VAR21, VAR15,
VAR33, VAR2,
clk, VAR9, VAR27, VAR23, VAR28, VAR8,
VAR13, VAR32, VAR10, VAR34, VAR14,
VAR19, VAR7, VAR24,
VAR18
);
input clk;
input VAR9;
input VAR27;
input VAR23;
input [127:64] VAR28;
input VAR8;
input VAR13;
input VAR32;
input VAR10;
input VAR34;
input VAR14;
input ... | gpl-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature_KOA/ecp/ks58.v | 5,506 | module MODULE1(VAR6, VAR2, VAR9);
input wire [57:0] VAR6;
input wire [57:0] VAR2;
output wire [114:0] VAR9;
wire [56:0] VAR4;
wire [56:0] VAR10;
wire [56:0] VAR12;
wire [28:0] VAR8;
wire [28:0] VAR3;
VAR7 VAR5(VAR6[28:0], VAR2[28:0], VAR10);
VAR7 VAR11(VAR6[57:29], VAR2[57:29], VAR4);
assign VAR8[28:0] = VAR6[57:29] ^ ... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/analog/bw_clk/rtl/bw_clk_gl_rstce_rtl.v | 26,053 | module MODULE1(VAR33 ,VAR76 ,VAR96 ,
VAR64 ,VAR35 ,VAR13 ,VAR19 ,VAR115 ,VAR179 ,
VAR125 ,VAR192 ,VAR133 ,VAR233 ,VAR90 ,
VAR1 ,VAR178 ,VAR162 ,
VAR237 ,VAR34 ,VAR92 ,VAR176 ,
VAR211 ,VAR66 ,VAR193 ,VAR226 ,
VAR50 ,VAR158 ,VAR197 ,VAR77
,VAR206 ,VAR153 ,VAR43 ,
VAR128 ,VAR80 ,VAR200 ,VAR97
,VAR137 ,VAR187 ,VAR149 ,VAR4... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | models/udp_dff_ps/sky130_fd_sc_ls__udp_dff_ps.symbol.v | 1,311 | module MODULE1 (
input VAR4 ,
output VAR2 ,
input VAR1,
input VAR3
);
endmodule | apache-2.0 |
dwaipayanBiswas/ECG-feature-extraction-using-DWT | level3arch.v | 13,036 | module MODULE1 (VAR78,VAR72,VAR56,VAR133,
VAR22,VAR26,VAR127,VAR5,VAR43,
VAR13,VAR146,VAR128,VAR45,
VAR147,VAR91,VAR37,VAR139,VAR126,VAR107,VAR40,VAR84,VAR59,VAR65,VAR20,VAR52,VAR74,VAR130,VAR28,VAR34,VAR102,VAR113,VAR95,VAR39,VAR51,VAR125,VAR61,VAR53,VAR62,VAR80,VAR90,VAR35,VAR68,VAR131,VAR99,VAR100,VAR114,VAR109,VAR7... | gpl-3.0 |
grindars/bfcore | Stack.v | 1,350 | module MODULE1 (
VAR6,
VAR2,
VAR8,
VAR4,
VAR11,
VAR3
);
parameter VAR9 = 11;
parameter VAR7 = 7;
parameter VAR5 = 1 << VAR7;
input VAR6;
input VAR2;
input VAR8;
input VAR4;
input [VAR9 - 1:0] VAR11;
output reg [VAR9 - 1:0] VAR3;
reg [VAR7 - 1:0] VAR1;
reg [VAR9 - 1:0] VAR10 [0:VAR5 - 1];
always @ (posedge VAR6)
if(VAR2... | gpl-3.0 |
hanw/sonic-lite | hw/verilog/si570/edge_detector.v | 1,476 | module MODULE1 (
VAR11,
VAR9,
VAR8,
VAR7,
VAR10,
VAR3,
VAR1
);
input VAR11;
input VAR9;
input VAR8;
output VAR7;
output VAR10;
output reg VAR3;
reg [1:0] VAR5;
always@(posedge VAR11 or negedge VAR9)
begin
if (!VAR9)
begin
VAR5 <= 0;
end
else
begin
VAR5 <= {VAR5[0],VAR8};
end
end
assign VAR7 = (VAR5 == 2'b01) ? 1'b1 : 1... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.cache/ip/2017.2/834a177d5547d0b3/zynq_design_1_system_ila_0_stub.v | 5,476 | module MODULE1(clk, VAR58, VAR2,
VAR25, VAR28, VAR36, VAR33,
VAR8, VAR55, VAR19, VAR59,
VAR52, VAR34, VAR6, VAR12,
VAR30, VAR24, VAR7, VAR15,
VAR47, VAR57, VAR56, VAR35,
VAR4, VAR18, VAR42, VAR29,
VAR39, VAR45, VAR48, VAR14,
VAR3, VAR20, VAR10, VAR1, VAR26,
VAR44, VAR54, VAR16, VAR32,
VAR17, VAR11, VAR43, VAR41,
VAR37,... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/dram/rtl/dram_addr_gen_lo.v | 13,316 | module MODULE1(
VAR9, VAR13, VAR14, VAR8, VAR7, VAR3, VAR17,
VAR2, VAR5, VAR1, VAR10, VAR16
);
input [39:4] VAR2;
input [8:0] VAR5;
input VAR1;
input VAR16;
input VAR10;
output VAR17;
output VAR9;
output VAR13;
output VAR14;
output [2:0] VAR8;
output [14:0] VAR7;
output [13:0] VAR3;
wire [14:0] VAR6;
wire [14:0] VAR4;
... | gpl-2.0 |
TWW12/lzw | final_project/lzw_compression/lzw_compression.ipdefs/axi_compression_1.0_0_0/src/output_fifo/output_fifo_stub.v | 1,392 | module MODULE1(clk, VAR1, din, VAR2, VAR3, dout, VAR4, VAR5)
;
input clk;
input VAR1;
input [11:0]din;
input VAR2;
input VAR3;
output [11:0]dout;
output VAR4;
output VAR5;
endmodule | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or2b/sky130_fd_sc_hs__or2b.behavioral.v | 1,815 | module MODULE1 (
VAR4 ,
VAR13 ,
VAR6 ,
VAR1,
VAR3
);
output VAR4 ;
input VAR13 ;
input VAR6 ;
input VAR1;
input VAR3;
wire VAR4 VAR12 ;
wire VAR7 ;
wire VAR11;
not VAR9 (VAR12 , VAR6 );
or VAR5 (VAR7 , VAR12, VAR13 );
VAR8 VAR2 (VAR11, VAR7, VAR1, VAR3);
buf VAR10 (VAR4 , VAR11 );
endmodule | apache-2.0 |
mballance/oc_wb_ip | rtl/wb_dma/rtl/verilog/wb_dma_ch_sel.v | 54,344 | module MODULE1(clk, rst,
VAR39, VAR315, VAR380,
VAR341, VAR165, VAR378, VAR260, VAR184, VAR358, VAR154, VAR220,
VAR307, VAR195, VAR327, VAR415, VAR202, VAR313, VAR123, VAR26,
VAR78, VAR32, VAR374, VAR84, VAR318, VAR300, VAR114, VAR388,
VAR258, VAR247, VAR234, VAR58, VAR267, VAR252, VAR12, VAR152,
VAR65, VAR142, VAR266,... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_isobufsrc/sky130_fd_sc_hd__lpflow_isobufsrc.blackbox.v | 1,377 | module MODULE1 (
VAR5 ,
VAR4,
VAR7
);
output VAR5 ;
input VAR4;
input VAR7 ;
supply1 VAR1;
supply0 VAR6;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
gr0bi42/BTCMiner | fpga/ztex_ufm1_15d3.v | 3,849 | module MODULE1 (VAR18, reset, VAR6, VAR37, VAR56, VAR10, VAR9, VAR43, VAR34, VAR15, read, write);
input VAR18, reset, VAR6, VAR37, VAR56, VAR10, VAR9, VAR43, VAR34, VAR15;
input [7:0] read;
output [7:0] write;
reg [3:0] VAR41, VAR70;
reg VAR8, VAR5, VAR29;
reg VAR39, VAR52, VAR68;
reg [4:0] VAR24;
reg [351:0] VAR51, VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfxbp/sky130_fd_sc_ms__sdfxbp.behavioral.pp.v | 2,509 | module MODULE1 (
VAR4 ,
VAR9 ,
VAR22 ,
VAR17 ,
VAR24 ,
VAR27 ,
VAR23,
VAR13,
VAR10 ,
VAR18
);
output VAR4 ;
output VAR9 ;
input VAR22 ;
input VAR17 ;
input VAR24 ;
input VAR27 ;
input VAR23;
input VAR13;
input VAR10 ;
input VAR18 ;
wire VAR1 ;
wire VAR19 ;
reg VAR7 ;
wire VAR12 ;
wire VAR6;
wire VAR21;
wire VAR2;
wire ... | apache-2.0 |
Murailab-arch/magukara | cores/crc/rtl/crc.v | 5,852 | module MODULE1 (
input VAR3,
input VAR4,
input VAR5,
input [7:0] VAR8,
input VAR10,
input VAR13,
output [31:0] VAR11,
output reg VAR14
);
reg [31:0] VAR2;
reg [3:0] VAR12;
function[31:0] VAR7;
input[7:0] VAR6;
input[31:0] VAR1;
reg[31:0] VAR9;
begin
VAR9[0]=VAR1[24]^VAR1[30]^VAR6[1]^VAR6[7];
VAR9[1]=VAR1[25]^VAR1[31]^V... | gpl-3.0 |
pradeep9676/pradeep_9676 | tausworthe.v | 1,657 | module MODULE1( VAR8, VAR9, VAR2, clk, reset, out, valid
);
input [31:0]VAR8;
input [31:0]VAR9;
input [31:0]VAR2;
input clk, reset;
output reg [31:0]out;
output reg valid;
reg [31:0]b1,VAR6,VAR7,VAR1,VAR4, VAR5, VAR3;
begin
begin | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a221oi/sky130_fd_sc_ls__a221oi.functional.v | 1,582 | module MODULE1 (
VAR1 ,
VAR9,
VAR4,
VAR13,
VAR2,
VAR5
);
output VAR1 ;
input VAR9;
input VAR4;
input VAR13;
input VAR2;
input VAR5;
wire VAR11 ;
wire VAR12 ;
wire VAR8;
and VAR6 (VAR11 , VAR13, VAR2 );
and VAR7 (VAR12 , VAR9, VAR4 );
nor VAR3 (VAR8, VAR11, VAR5, VAR12);
buf VAR10 (VAR1 , VAR8 );
endmodule | apache-2.0 |
monotone-RK/FACE | MCSoC-15/4-way_4-parallel/ise/ipcore_dir/dram/user_design/rtl/phy/mig_7series_v1_9_ddr_phy_ck_addr_cmd_delay.v | 8,853 | module MODULE1 #
(
parameter VAR18 = 100,
parameter VAR6 = 3636,
parameter VAR19 = 3,
parameter VAR30 = 3,
parameter VAR13 = "VAR23"
)
(
input clk,
input rst,
input VAR12,
output reg [VAR30-1:0] VAR21,
output reg VAR26,
output reg VAR16,
output reg VAR27,
output reg VAR20,
output VAR1
);
localparam VAR22 = 63;
localpar... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/output_queues/sram_rr_output_queues/src/oq_regs_eval_full.v | 6,823 | module MODULE1
parameter VAR12 = 13,
parameter VAR27 = 8,
parameter VAR40 = 2,
parameter VAR13 = 8,
parameter VAR15 = VAR41(VAR13),
parameter VAR23 = 11,
parameter VAR22 = VAR23-VAR41(VAR27),
parameter VAR24 = 2048/VAR27, parameter VAR48 = 60/VAR27 + 1,
parameter VAR18 = VAR41((2**VAR12)/VAR48)
)
(
input VAR28,
input [... | mit |
YurongYou/MIPS_CPU | regfile.v | 3,254 | module MODULE1(
input clk,
input rst,
input[VAR21-1:0] VAR49,
input[VAR46-1:0] VAR32,
input VAR12,
input VAR41,
input[VAR21-1:0] VAR28,
output reg[VAR46-1:0] VAR47,
input VAR7,
input[VAR21-1:0] VAR36,
output reg[VAR46-1:0] VAR42,
output[VAR46-1:0] VAR16,
output[VAR46-1:0] VAR11,
output[VAR46-1:0] VAR2,
output[VAR46-1:0... | mpl-2.0 |
AngelTerrones/MUSB | Hardware/musoc/musoc.v | 12,817 | module MODULE1#(
parameter VAR82 = "VAR109", parameter VAR37 = 1, parameter VAR45 = 1, parameter VAR19 = 1, parameter VAR28 = 50, parameter VAR65 = 12 )(
input clk,
input rst,
output VAR44,
inout [31:0] VAR14,
input VAR115,
output VAR8
);
wire [31:0] VAR113;
wire [3:0] VAR42;
wire VAR104;
wire VAR33;
wire VAR2;
wire [3... | mit |
amontefusco/gnuradio-amontefusco | gr-sounder/src/fpga/lib/sounder_ctrl.v | 2,886 | module MODULE1(VAR13,VAR5,VAR4,VAR6,VAR24,
VAR26,VAR21,VAR3,VAR30,
VAR1,VAR2,VAR14,
VAR29,VAR11,VAR19,VAR25);
input VAR13; input VAR5; input [6:0] VAR4; input [31:0] VAR6; input VAR24; output VAR26;
output VAR21;
output VAR3;
output VAR30;
output [4:0] VAR1;
output [13:0] VAR2;
output [15:0] VAR14;
output VAR29;
output... | gpl-3.0 |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_zbroji_0_0/hdl/verilog/zbroji_HLS_ZBROJI_PERIPH_BUS_if.v | 8,718 | module MODULE1
VAR52 = 6,
VAR9 = 32
)(
input wire VAR55,
input wire VAR47,
input wire [VAR52-1:0] VAR26,
input wire VAR15,
output wire VAR24,
input wire [VAR9-1:0] VAR27,
input wire [VAR9/8-1:0] VAR62,
input wire VAR8,
output wire VAR64,
output wire [1:0] VAR4,
output wire VAR3,
input wire VAR18,
input wire [VAR52-1:0]... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_16.behavioral.v | 1,121 | module MODULE1( VAR4, VAR3 );
input VAR4;
output VAR3;
VAR1 VAR5(.VAR4(VAR4),.VAR3(VAR3));
VAR1 VAR2(.VAR4(VAR4),.VAR3(VAR3)); | apache-2.0 |
horia141/bachelor-thesis | prj/xtra/common/RAMDP/RAMDP.v | 1,394 | module MODULE1(VAR7,reset,VAR4,VAR3,VAR2,VAR1,VAR6,VAR8);
parameter VAR9 = 8;
parameter VAR5 = 8;
input wire VAR7;
input wire reset;
input wire VAR4;
input wire [VAR9-1:0] VAR3;
input wire [VAR9-1:0] VAR2;
input wire [VAR5-1:0] VAR1;
output reg [VAR5-1:0] VAR6;
output reg [VAR5-1:0] VAR8;
reg [VAR5-1:0] VAR10[2**VAR9-1... | mit |
jeffkub/n64-cart-reader | old/fpga/soc_system/soc_system/synthesis/submodules/soc_system_jtag_master.v | 21,624 | module MODULE1 #(
parameter VAR13 = 0,
parameter VAR21 = 50000,
parameter VAR44 = 2
) (
input wire VAR11, input wire VAR7, output wire [31:0] VAR4, input wire [31:0] VAR18, output wire VAR19, output wire VAR3, output wire [31:0] VAR5, input wire VAR38, input wire VAR15, output wire [3:0] VAR42, output wire VAR48 );
wir... | mit |
alexforencich/xfcp | lib/eth/rtl/mii_phy_if.v | 3,717 | module MODULE1 #
(
parameter VAR18 = "VAR36",
parameter VAR28 = "VAR37"
)
(
input wire rst,
output wire VAR3,
output wire VAR9,
output wire [3:0] VAR13,
output wire VAR6,
output wire VAR10,
output wire VAR30,
output wire VAR5,
input wire [3:0] VAR11,
input wire VAR26,
input wire VAR22,
input wire VAR23,
input wire [3:0... | mit |
alexforencich/verilog-i2c | rtl/i2c_init.v | 17,852 | module MODULE1 (
input wire clk,
input wire rst,
output wire [6:0] VAR2,
output wire VAR6,
output wire VAR12,
output wire VAR8,
output wire VAR3,
output wire VAR7,
output wire VAR11,
input wire VAR4,
output wire [7:0] VAR15,
output wire VAR10,
input wire VAR1,
output wire VAR14,
output wire VAR5,
input wire VAR9
);
loc... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/scbuf/rtl/bw_clk_cl_scbuf_cmp.v | 2,163 | module MODULE1 (
VAR6, VAR10, VAR9, VAR8,
VAR12, VAR5, VAR11, VAR3, VAR13, VAR14, VAR7,
VAR4
);
input VAR12;
input VAR5;
input VAR11;
input VAR3;
input VAR13;
input VAR14;
output VAR6;
output VAR10;
output VAR9;
input VAR7;
input VAR4;
output VAR8;
VAR2 VAR1 (
.VAR6 (VAR6),
.VAR10 (VAR10),
.VAR9 (VAR9),
.VAR8 (VAR8),
.... | gpl-2.0 |
azonenberg/openfpga | hdl/xc2c-model/HandshakeSynchronizer.v | 6,040 | module MODULE1(
input wire VAR11,
input wire VAR17,
output reg VAR2 = 0,
output wire VAR9,
input wire VAR13,
output reg VAR4 = 0,
input wire VAR14
);
reg VAR1 = 0;
wire VAR16;
reg VAR3 = 0;
wire VAR7;
VAR8 VAR12
(.VAR15(VAR11), .din(VAR1), .VAR6(VAR13), .dout(VAR16));
VAR8 VAR18
(.VAR15(VAR13), .din(VAR3), .VAR6(VAR11)... | lgpl-2.1 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/video_sys/synthesis/submodules/altera_up_av_config_auto_init_ltm.v | 6,602 | module MODULE1 (
VAR3,
VAR2
);
input [ 4: 0] VAR3;
output [23: 0] VAR2;
reg [23: 0] VAR1;
assign VAR2 = {VAR1[13: 8], 2'h0,
VAR1[ 7: 0]};
always @(*)
begin
case (VAR3)
0 : VAR1 <= {6'h02, 8'h07};
1 : VAR1 <= {6'h03, 8'hDF};
2 : VAR1 <= {6'h04, 8'h17};
3 : VAR1 <= {6'h11, 8'h00};
4 : VAR1 <= {6'h12, 8'h5B};
5 : VAR1 <= ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a2bb2o/sky130_fd_sc_ms__a2bb2o.behavioral.v | 1,705 | module MODULE1 (
VAR14 ,
VAR1,
VAR11,
VAR9 ,
VAR4
);
output VAR14 ;
input VAR1;
input VAR11;
input VAR9 ;
input VAR4 ;
supply1 VAR3;
supply0 VAR12;
supply1 VAR6 ;
supply0 VAR2 ;
wire VAR15 ;
wire VAR8 ;
wire VAR13;
and VAR7 (VAR15 , VAR9, VAR4 );
nor VAR5 (VAR8 , VAR1, VAR11 );
or VAR16 (VAR13, VAR8, VAR15);
buf VAR10 ... | apache-2.0 |
hermesdragon/-ECE270-Codes | Xilinx_BoothMultiplier/Implementation 1/Booth_Multiplier_I.v | 2,177 | module MODULE1 (VAR2,
VAR6,
VAR9,
VAR4,
VAR7,
VAR11);
output reg [7:0] VAR2; output reg VAR11; input [3:0] VAR6, VAR9; input wire VAR4, VAR7;
reg [8:0] VAR8, VAR5, VAR3;
reg [2:0] VAR10;
reg VAR1;
always @(posedge VAR4 or posedge VAR7) begin if (VAR7) begin
VAR3 = {4'b0000, VAR9, 1'b0}; VAR10 = 3'b000; VAR11 = 1'b1; VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfrtp/sky130_fd_sc_hs__sdfrtp.behavioral.v | 2,768 | module MODULE1 (
VAR17,
VAR22 ,
VAR20 ,
VAR16 ,
VAR28 ,
VAR27 ,
VAR19 ,
VAR23
);
input VAR17;
input VAR22 ;
input VAR20 ;
output VAR16 ;
input VAR28 ;
input VAR27 ;
input VAR19 ;
input VAR23 ;
wire VAR13 ;
wire VAR6 ;
wire VAR3 ;
reg VAR29 ;
wire VAR14 ;
wire VAR24 ;
wire VAR9 ;
wire VAR15;
wire VAR7 ;
wire VAR4 ;
wire... | apache-2.0 |
CospanDesign/nysa-tx1-pcie-platform | tx1_pcie/slave/wb_tx1_pcie/rtl/host_interface/pcie_control.v | 28,234 | module MODULE1 (
input clk,
input rst,
input [7:0] VAR114,
input [4:0] VAR128,
input [2:0] VAR61,
input [31:0] VAR175,
input [31:0] VAR110,
input [31:0] VAR191,
input [31:0] VAR132,
input [31:0] VAR10,
input [31:0] VAR35,
input [31:0] VAR22,
input [31:0] VAR41,
input [1:0] VAR26,
input VAR85,
input VAR106,
input [31:0]... | mit |
mfkiwl/parallella-platform | hdl/mux4.v | 1,402 | module MODULE1(
out,
VAR5, VAR7, VAR3, VAR8, VAR6, VAR9, VAR2, VAR4
);
parameter VAR1=99;
input [VAR1-1:0] VAR5;
input [VAR1-1:0] VAR7;
input [VAR1-1:0] VAR3;
input [VAR1-1:0] VAR8;
input VAR6;
input VAR9;
input VAR2;
input VAR4;
output [VAR1-1:0] out;
assign out[VAR1-1:0] = ({(VAR1){VAR6}} & VAR5[VAR1-1:0] |
{(VAR1){V... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_2.functional.v | 1,585 | module MODULE1( VAR16, VAR17, VAR10, VAR13, VAR8 );
input VAR17, VAR16, VAR13, VAR8;
output VAR10;
wire VAR6;
not VAR5( VAR6, VAR17 );
wire VAR2;
not VAR14( VAR2, VAR13 );
wire VAR4;
not VAR12( VAR4, VAR8 );
wire VAR3;
and VAR11( VAR3, VAR6, VAR2, VAR4 );
wire VAR15;
not VAR9( VAR15, VAR16 );
wire VAR18;
and VAR1( VAR1... | apache-2.0 |
red0bear/CRCAHB | rtl/crc_parrallel.v | 3,995 | module MODULE1
parameter VAR8 = 8, parameter VAR7 = 8 )(
output [VAR8 - 1 : 0] VAR23,
input [VAR7 - 1 : 0] VAR22,
input [VAR8 - 1 : 0] VAR1,
input [VAR8 - 1 : 0] VAR9,
input [VAR8 - 1 : 0] VAR14
);
localparam VAR20 = {VAR8{1'b1}};
localparam VAR3 = {VAR8{1'b0}};
wire [VAR8 - 1 : 0] VAR17[0 : VAR7];
wire [VAR8 - 1 : 0] ... | gpl-3.0 |
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