repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfbbp/sky130_fd_sc_hs__dfbbp.blackbox.v | 1,399 | module MODULE1 (
VAR2 ,
VAR3 ,
VAR4 ,
VAR5 ,
VAR7 ,
VAR1
);
output VAR2 ;
output VAR3 ;
input VAR4 ;
input VAR5 ;
input VAR7 ;
input VAR1;
supply1 VAR6;
supply0 VAR8;
endmodule | apache-2.0 |
dekuNukem/FAP80 | FAP_modules/video_card/FPGA_code/src/pc_vga_8x16_80_FF.v | 6,983 | module MODULE1 (
input clk,
input [6:0] VAR73,
input [3:0] VAR48,
input [2:0] VAR13,
output wire VAR29
);
VAR30 VAR37 (
.VAR11(clk),
.VAR22(1'b1),
.VAR33(1'b0),
.VAR58({VAR73[6:1], ~VAR73[0], VAR48, ~VAR13}),
.VAR63(1'b0),
.VAR75(1'b0),
.VAR62(VAR29)
);
en... | mit |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/verilog/FIFO_image_filter_p_dst_data_stream_1_V.v | 3,017 | module MODULE2 (
clk,
VAR9,
VAR23,
VAR7,
VAR27);
parameter VAR6 = 32'd8;
parameter VAR8 = 32'd1;
parameter VAR21 = 32'd2;
input clk;
input [VAR6-1:0] VAR9;
input VAR23;
input [VAR8-1:0] VAR7;
output [VAR6-1:0] VAR27;
reg[VAR6-1:0] VAR1 [0:VAR21-1];
integer VAR19;
always @ (posedge clk)
begin
if (VAR23)
begin
for (VAR19... | gpl-3.0 |
mda-ut/SubZero | fpga/fpga_hw/top_level/SONAR/ShiftRegisterWEnableSixteenAsyncMuxedInput.v | 3,444 | module MODULE1(clk, VAR6, enable, select, VAR7, VAR5);
input clk;
input VAR6;
input enable;
input select;
input [15:0] VAR7;
output [15:0] VAR5;
wire [15:1]VAR3;
VAR21 VAR10(.VAR29(VAR7[1]), .VAR8(VAR5[0]), .sel(select), .VAR19(VAR3[1]) );
VAR21 VAR33(.VAR29(VAR7[2]), .VAR8(VAR5[1]), .sel(select), .VAR19(VAR3[2]) );
VA... | mit |
Huyuwei/tvm | vta/hardware/chisel/src/main/resources/verilog/VTAHostDPI.v | 2,761 | module MODULE1 #
( parameter VAR3 = 8,
parameter VAR9 = 32
)
(
input VAR2,
input reset,
output logic VAR16,
output logic VAR23,
output logic [VAR3-1:0] VAR8,
output logic [VAR9-1:0] VAR5,
input VAR17,
input VAR20,
input [VAR9-1:0] VAR1
);
import "VAR7-VAR12" function void MODULE1
(
output byte unsigned VAR21,
output by... | apache-2.0 |
drichmond/riffa | fpga/altera/de5/DE5QGen1x8If64/hdl/DE5QGen1x8If64.v | 18,179 | module MODULE1
parameter VAR124 = 8,
parameter VAR130 = 64,
parameter VAR156 = 256,
parameter VAR188 = 5
)
(
output [7:0] VAR35,
input VAR81,
input VAR158,
input [VAR124-1:0] VAR61,
output [VAR124-1:0] VAR59,
input VAR193
);
wire VAR13;
wire VAR176;
wire [3:0] VAR187;
wire [31:0] VAR65;
wire [52:0] VAR213;
wire [0:0] V... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o21ba/sky130_fd_sc_ms__o21ba_1.v | 2,316 | module MODULE1 (
VAR8 ,
VAR4 ,
VAR3 ,
VAR2,
VAR6,
VAR5,
VAR7 ,
VAR1
);
output VAR8 ;
input VAR4 ;
input VAR3 ;
input VAR2;
input VAR6;
input VAR5;
input VAR7 ;
input VAR1 ;
VAR10 VAR9 (
.VAR8(VAR8),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
V... | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/DE10-old/mmio_if/synthesis/submodules/mmio_if_pio_0.v | 2,130 | module MODULE1 (
address,
VAR1,
clk,
VAR9,
VAR4,
VAR5,
VAR3,
VAR2
)
;
output [ 7: 0] VAR3;
output [ 31: 0] VAR2;
input [ 1: 0] address;
input VAR1;
input clk;
input VAR9;
input VAR4;
input [ 31: 0] VAR5;
wire VAR8;
reg [ 7: 0] VAR6;
wire [ 7: 0] VAR3;
wire [ 7: 0] VAR7;
wire [ 31: 0] VAR2;
assign VAR8 = 1;
assign VAR7 ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a221oi/sky130_fd_sc_lp__a221oi_0.v | 2,457 | module MODULE2 (
VAR6 ,
VAR4 ,
VAR1 ,
VAR12 ,
VAR10 ,
VAR8 ,
VAR9,
VAR7,
VAR2 ,
VAR5
);
output VAR6 ;
input VAR4 ;
input VAR1 ;
input VAR12 ;
input VAR10 ;
input VAR8 ;
input VAR9;
input VAR7;
input VAR2 ;
input VAR5 ;
VAR11 VAR3 (
.VAR6(VAR6),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR12(VAR12),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR9(... | apache-2.0 |
nyaxt/dmix | nkmd/arch/nkmd_dai_t.v | 4,030 | module MODULE1;
reg clk;
parameter VAR16 = 20;
VAR15 clk = 0;
always #(VAR16/2) clk = ~clk;
reg rst;
reg [23:0] VAR12;
reg VAR18;
reg [31:0] VAR10;
wire [31:0] VAR7;
reg [31:0] VAR8;
reg VAR13;
VAR17 VAR5(
.clk(clk),
.rst(rst),
.VAR11(VAR12),
.VAR19(VAR18),
.VAR3(VAR10),
.VAR14(VAR7),
.VAR20(VAR8),
.VAR9(VAR13));
task ... | mit |
ShepardSiegel/ocpi | coregen/dram_k7_mig11/mig_7series_v1_1/example_design/rtl/traffic_gen/read_posted_fifo.v | 7,918 | module MODULE1 #
(
parameter VAR14 = 100,
parameter VAR30 = "VAR35",
parameter VAR4 = 4,
parameter VAR50 = 32,
parameter VAR18 = 6
)
(
input VAR38,
input VAR22,
output reg VAR40,
input VAR8,
input VAR39,
input VAR12,
input VAR19,
input [VAR50-1:0] VAR15,
input [VAR18-1:0] VAR6,
input [2:0] VAR46,
input [5:0] VAR21 ,
in... | lgpl-3.0 |
osresearch/vst | fpga/mpc4922.v | 1,146 | module MODULE1(
input clk,
input reset,
output VAR7,
output VAR11,
output VAR5,
input [11:0] VAR4,
input VAR3,
input VAR6,
output ready
);
parameter VAR9 = 1'b1; parameter VAR1 = 1'b1; parameter VAR2 = 1'b1;
reg [15:0] VAR8;
reg [4:0] VAR10;
assign ready = !reset && VAR10 == 0;
assign VAR7 = ready; assign VAR5 = VAR8[1... | gpl-2.0 |
ineganov/bare_system | wiz/vji.v | 7,168 | module MODULE1 (
VAR25,
VAR13,
VAR49,
VAR10,
VAR17,
VAR40,
VAR31,
VAR21,
VAR36,
VAR22,
VAR3,
VAR18,
VAR33);
input [2:0] VAR25;
input VAR13;
output [2:0] VAR49;
output VAR10;
output VAR17;
output VAR40;
output VAR31;
output VAR21;
output VAR36;
output VAR22;
output VAR3;
output VAR18;
output VAR33;
wire VAR15;
wire VAR9... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkdlybuf4s25/sky130_fd_sc_hd__clkdlybuf4s25.behavioral.v | 1,439 | module MODULE1 (
VAR4,
VAR3
);
output VAR4;
input VAR3;
supply1 VAR5;
supply0 VAR1;
supply1 VAR7 ;
supply0 VAR2 ;
wire VAR6;
buf VAR9 (VAR6, VAR3 );
buf VAR8 (VAR4 , VAR6 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21o/sky130_fd_sc_ms__a21o.blackbox.v | 1,326 | module MODULE1 (
VAR4 ,
VAR2,
VAR8,
VAR3
);
output VAR4 ;
input VAR2;
input VAR8;
input VAR3;
supply1 VAR1;
supply0 VAR5;
supply1 VAR6 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlrbn/sky130_fd_sc_hd__dlrbn.behavioral.pp.v | 2,608 | module MODULE1 (
VAR21 ,
VAR7 ,
VAR18,
VAR13 ,
VAR17 ,
VAR24 ,
VAR15 ,
VAR14 ,
VAR2
);
output VAR21 ;
output VAR7 ;
input VAR18;
input VAR13 ;
input VAR17 ;
input VAR24 ;
input VAR15 ;
input VAR14 ;
input VAR2 ;
wire VAR8 ;
wire VAR26 ;
reg VAR10 ;
wire VAR22 ;
wire VAR11 ;
wire VAR25 ;
wire VAR12;
wire VAR1 ;
wire VAR... | apache-2.0 |
ptracton/wb_soc_template | rtl/ZIP/rtl/memops.v | 6,537 | module MODULE1(VAR10, VAR35, VAR4, VAR21,
VAR2, VAR17, VAR3, VAR25,
VAR18, VAR38, VAR37, VAR15, VAR32,
VAR23, VAR8,
VAR29, VAR9,
VAR30, VAR7, VAR16, VAR36,
VAR22, VAR12, VAR33, VAR19);
parameter VAR1=30;
parameter [0:0] VAR26=1'b0,
VAR5=1'b0;
localparam VAR6=VAR1;
input wire VAR10, VAR35;
input wire VAR4, VAR21;
input ... | mit |
ShepardSiegel/ocpi | rtl/mkQABSMF.v | 57,977 | module MODULE1(VAR15,
VAR17,
VAR50,
VAR54,
VAR3,
VAR180,
VAR141,
VAR163,
VAR210,
VAR1,
VAR206,
VAR59,
VAR215,
VAR67,
VAR110,
VAR69,
VAR186,
VAR75,
VAR222,
VAR135,
VAR49);
input [15 : 0] VAR15;
input VAR17;
input VAR50;
input [39 : 0] VAR54;
input VAR3;
output VAR180;
input VAR141;
output [39 : 0] VAR163;
output VAR210;... | lgpl-3.0 |
vineeshvs/research | output_files/full_adder_sliced_with_modified_IOports.v | 1,110 | module MODULE1 (VAR10, b0, VAR8, VAR14, b1, VAR12, VAR3, VAR11, VAR15);
input VAR10;
input b0;
input VAR8;
output VAR9;
output VAR12;
output VAR3;
wire VAR2;
wire VAR24;
wire VAR9;
wire VAR21;
wire VAR5;
assign VAR4 = VAR2 | VAR24;
assign VAR3 = VAR9;
VAR1 VAR22 (
.VAR18(VAR10),
.VAR17(b0),
.VAR26(VAR20),
.VAR19(VAR2)
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and4/sky130_fd_sc_ls__and4.functional.v | 1,296 | module MODULE1 (
VAR6,
VAR7,
VAR3,
VAR2,
VAR8
);
output VAR6;
input VAR7;
input VAR3;
input VAR2;
input VAR8;
wire VAR5;
and VAR4 (VAR5, VAR7, VAR3, VAR2, VAR8 );
buf VAR1 (VAR6 , VAR5 );
endmodule | apache-2.0 |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/Source/IP/COUNTER/COUNTER_bb.v | 3,772 | module MODULE1 (
VAR2,
VAR1,
VAR4,
VAR3);
input VAR2;
input VAR1;
input VAR4;
output [13:0] VAR3;
endmodule | gpl-2.0 |
jotego/jt-sfg01 | hdl/jt-sfg01.v | 3,611 | module MODULE1(
input rst,
output [ 7:0] VAR5, input [ 7:0] VAR19,
input [15:0] addr, input clk, input VAR11, input VAR6, input VAR21, input VAR10, input VAR16,
output VAR14, output VAR9,
output VAR7,
output [15:0] VAR15,
output [15:0] VAR4
);
wire VAR17 = &addr[13:7];
wire VAR2 = ~(addr[6] & VAR17);
wire VAR3 = ~(addr... | gpl-3.0 |
DreamSourceLab/DSLogic-hdl | src/sdramc/mem_ctrl.v | 7,264 | module MODULE1 (
input VAR50,
input VAR83,
input VAR33,
output VAR76,
input [31:0] VAR31,
input [15:0] VAR70,
input VAR30,
output VAR92,
input [31:0] VAR17,
output VAR15,
output [15:0] VAR32,
output VAR95,
output [12:0] VAR8,
output [1:0] VAR91,
inout [15:0] VAR82,
output VAR67,
output VAR29,
output VAR20,
output VAR59... | gpl-2.0 |
Tabrizian/GuessNumber | main_for_FPGA.v | 3,138 | module MODULE1(VAR20,VAR1,VAR28,VAR24,VAR15,VAR12,VAR14,reset,VAR5,VAR25,VAR7,VAR22,VAR26,VAR23,VAR9);
input VAR26;
wire VAR19;
output reg VAR23;
reg[0:22] out;
always @(posedge VAR19 or posedge reset) begin
if(reset)
VAR23 = 0 ;
end
else
VAR23 = ~VAR23;
end
always @(posedge VAR26 or posedge reset) begin
if(reset)
out ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand4b/sky130_fd_sc_ms__nand4b.symbol.v | 1,329 | module MODULE1 (
input VAR2,
input VAR7 ,
input VAR4 ,
input VAR8 ,
output VAR1
);
supply1 VAR3;
supply0 VAR6;
supply1 VAR5 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/Aurora_MGT/Pcore/mgt_fifo1_v1_00_a/hdl/verilog/rx_stream.v | 3,578 | module MODULE1
(
VAR10,
VAR5,
VAR1,
VAR11,
VAR3,
VAR6,
VAR8,
VAR7,
VAR4
);
output [0:31] VAR10;
output VAR5;
input VAR1;
input [0:1] VAR11;
input [0:31] VAR3;
input [0:1] VAR6;
input [0:1] VAR8;
input [0:1] VAR7;
input VAR4;
reg VAR2;
always @(posedge VAR4)
if(!VAR1)
VAR2 <= VAR9 1'b0;
else if(VAR8 > 2'd0)
VAR2 <= VAR9... | bsd-2-clause |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/bd/system/ip/system_HLS_accel_0_0/hdl/verilog/HLS_accel_fmul_32ns_32ns_32_4_max_dsp.v | 1,991 | module MODULE1
VAR27 = 1,
VAR25 = 4,
VAR15 = 32,
VAR18 = 32,
VAR5 = 32
)(
input wire clk,
input wire reset,
input wire VAR14,
input wire [VAR15-1:0] VAR2,
input wire [VAR18-1:0] VAR20,
output wire [VAR5-1:0] dout
);
wire VAR4;
wire VAR19;
wire VAR16;
wire [31:0] VAR17;
wire VAR1;
wire [31:0] VAR7;
wire VAR12;
wire [31:... | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/FPU_Interface/fpaddsub_arch2/Add_Subt.v | 2,540 | module MODULE1
input wire clk,
input wire rst,
input wire VAR4, input wire VAR20,
input wire [VAR1-1:0] VAR23,
input wire [VAR1-1:0] VAR17,
output wire [VAR1-1:0] VAR24,
output wire VAR10
);
wire [VAR1-1:0] VAR2;
wire [VAR1:0] VAR13;
wire [VAR1-1:0] VAR11;
wire [VAR1-1:1] VAR15;
wire VAR16;
VAR8 #(.VAR5(VAR1)) VAR18 (
... | gpl-3.0 |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/pikachu_down_pixel/pikachu_down_pixel_stub.v | 1,329 | module MODULE1(VAR3, VAR2, VAR4, VAR1, VAR5)
;
input VAR3;
input [0:0]VAR2;
input [12:0]VAR4;
input [11:0]VAR1;
output [11:0]VAR5;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_0.v | 2,398 | module MODULE1 (
VAR2 ,
VAR10,
VAR11,
VAR3 ,
VAR4 ,
VAR6,
VAR8,
VAR1 ,
VAR9
);
output VAR2 ;
input VAR10;
input VAR11;
input VAR3 ;
input VAR4 ;
input VAR6;
input VAR8;
input VAR1 ;
input VAR9 ;
VAR7 VAR5 (
.VAR2(VAR2),
.VAR10(VAR10),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR9... | apache-2.0 |
pseudoincorrect/FPGA_MCU_wifi | FPGA/src/DPRAM_modules/fifo_DPRAM.v | 10,435 | module MODULE1(clk, rst, VAR32, din, VAR9, dout, VAR37,
VAR14, VAR36, VAR19, VAR5,
VAR25, VAR3, VAR27, VAR23,
VAR12);
parameter VAR16 = 8;
parameter VAR7 = 8;
parameter VAR21 = 32;
parameter VAR33 = 1 << VAR7;
input clk, rst, VAR32;
input VAR9;
input VAR37;
input [VAR16-1:0] din;
output VAR14, VAR19;
output VAR36, VAR5... | mit |
Mahalakshmi23/ElectronicLock | ElectronicLock.v | 8,109 | module MODULE1(
input [5:0] VAR6,
input [3:0] VAR20,
input clk,
output [3:0] VAR13,
output [6:0] VAR19,
output [7:0] VAR9
);
reg [7:0] VAR21=8'b00000000;
reg [3:0] VAR10 = 4'b1111;
reg [6:0] VAR24=7'b1111111;
reg [6:0] VAR23=7'b1111111;
reg [6:0] VAR3=7'b1111111;
reg [6:0] VAR4=7'b1111111;
reg [6:0] VAR5=7'b1111111;
re... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inv/sky130_fd_sc_lp__inv.functional.pp.v | 1,748 | module MODULE1 (
VAR8 ,
VAR10 ,
VAR2,
VAR9,
VAR12 ,
VAR1
);
output VAR8 ;
input VAR10 ;
input VAR2;
input VAR9;
input VAR12 ;
input VAR1 ;
wire VAR3 ;
wire VAR7;
not VAR6 (VAR3 , VAR10 );
VAR4 VAR5 (VAR7, VAR3, VAR2, VAR9);
buf VAR11 (VAR8 , VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a221o/sky130_fd_sc_ls__a221o.functional.v | 1,566 | module MODULE1 (
VAR12 ,
VAR7,
VAR2,
VAR10,
VAR3,
VAR6
);
output VAR12 ;
input VAR7;
input VAR2;
input VAR10;
input VAR3;
input VAR6;
wire VAR5 ;
wire VAR4 ;
wire VAR11;
and VAR8 (VAR5 , VAR10, VAR3 );
and VAR9 (VAR4 , VAR7, VAR2 );
or VAR13 (VAR11, VAR4, VAR5, VAR6);
buf VAR1 (VAR12 , VAR11 );
endmodule | apache-2.0 |
srjet/mips-verilog | cpu_eda.v | 8,712 | module MODULE3(
input [3:0] VAR27,
input [31:0] VAR42, VAR44,
output reg [31:0] out,
output VAR16 );
wire [31:0] VAR11;
wire [31:0] VAR45;
always @ begin
case(VAR18)
2'b00: VAR30 <= 4'b0010; 2'b01: VAR30 <= 4'b0110; 2'b10 :
begin
case (VAR20)
6'b100000: VAR30 <= 4'b0010;
6'b100010: VAR30 <= 4'b0110;
6'b100101: VAR30 <=... | gpl-2.0 |
asicguy/gplgpu | hdl/de/der_top.v | 18,144 | module MODULE1
(
input VAR22, input VAR49, input VAR111, input VAR70, input [31:0] VAR115, input [8:2] VAR108, input [8:2] VAR126, input VAR140, input [3:0] VAR92, input VAR21, input [15:0] VAR23, input [53:0] VAR52, input [4:0] VAR67, input VAR59, input VAR132, input VAR85, input VAR128, input VAR141, input VAR64, inp... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_ncio/rtl/jbi_ncio.v | 26,089 | module MODULE1 (
VAR141, VAR211, VAR185,
VAR136, VAR162, VAR114,
VAR197, VAR131, VAR202,
VAR84, VAR155, VAR167,
VAR39, VAR104, VAR159, VAR53,
VAR145, VAR106, VAR208, VAR61, VAR178,
VAR113, VAR125, VAR213,
VAR17, VAR49, VAR63,
clk, VAR93, VAR183, VAR2, VAR196, VAR90, VAR43, VAR75,
VAR77, VAR81, VAR34, VAR149,
VAR87, VAR... | gpl-2.0 |
tmolteno/TART | hardware/FPGA/tart_spi/verilog/spi/spi_master.v | 9,352 | module MODULE1
parameter VAR65 = VAR30-2,
parameter VAR57 = 8'hA7,
parameter VAR59 = 3) ( input VAR63,
input VAR27,
input VAR54,
input VAR32,
input VAR23,
input VAR28,
output reg VAR58 = 0,
output reg VAR61 = 0,
output reg VAR24 = 0,
input [VAR65:0] VAR49,
input [VAR1:0] VAR10,
output reg [7:0] VAR19,
input VAR47,
outp... | lgpl-3.0 |
UdayanSinha/Code_Blocks | Nios-2/Nios/practica4/mi_nios/synthesis/mi_nios.v | 42,684 | module MODULE1 (
input wire VAR84, output wire VAR75, output wire VAR226, output wire VAR243, input wire VAR104, output wire [7:0] VAR15, input wire VAR1, output wire [11:0] VAR240, output wire [1:0] VAR290, output wire VAR211, output wire VAR126, output wire VAR101, inout wire [15:0] VAR178, output wire [1:0] VAR252, ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor3b/sky130_fd_sc_hd__nor3b.functional.pp.v | 1,995 | module MODULE1 (
VAR7 ,
VAR4 ,
VAR14 ,
VAR2 ,
VAR8,
VAR9,
VAR15 ,
VAR12
);
output VAR7 ;
input VAR4 ;
input VAR14 ;
input VAR2 ;
input VAR8;
input VAR9;
input VAR15 ;
input VAR12 ;
wire VAR10 ;
wire VAR5 ;
wire VAR13;
nor VAR3 (VAR10 , VAR4, VAR14 );
and VAR1 (VAR5 , VAR2, VAR10 );
VAR6 VAR16 (VAR13, VAR5, VAR8, VAR9);... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_fpaddsub_arch2/integracion_fisica/front_end/db/SINGLE/FPU_Add_Subtract_Function_W32_EW8_SW23_SWR26_EWR5_FSM_Add_Subtract_syn.v | 6,146 | module MODULE1 ( clk, rst, VAR126, VAR27, VAR104,
VAR20, VAR170, VAR163, VAR35, VAR19,
VAR91, VAR14, VAR130, VAR77, VAR61, VAR185,
VAR146, VAR5, VAR48, VAR7, VAR179, VAR137,
VAR13, VAR112, VAR127, ready );
output [1:0] VAR179;
input clk, rst, VAR126, VAR27, VAR104, VAR20,
VAR170, VAR163;
output VAR35, VAR19, VAR91, VAR... | gpl-3.0 |
Triple-Z/COExperiment_Repo | Project_2_OC/ALUOnBoard/alu_display.v | 4,770 | module MODULE1(
input clk,
input VAR8,
input [1:0] VAR22,
output VAR11,
output VAR27,
output VAR5,
output VAR10,
output VAR13,
inout[15:0] VAR3,
output VAR19,
inout VAR24,
inout VAR18,
output VAR29,
output VAR16
);
reg [11:0] VAR28; reg [31:0] VAR4; reg [31:0] VAR1; wire [31:0] VAR26; alu VAR9(
.VAR28(VAR28),
.VAR4 (VA... | mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/acl_fp_modf_s5.v | 1,227 | module MODULE1 (
enable,
VAR7,
VAR2,
VAR8,
VAR3);
input enable;
input VAR7;
input [31:0] VAR2;
input [31:0] VAR8;
output [31:0] VAR3;
wire [31:0] VAR10;
wire [31:0] VAR3 = VAR10[31:0];
VAR4 VAR6 (
.en (enable),
.VAR1(1'b0),
.clk(VAR7),
.VAR5(VAR2),
.VAR11(VAR8),
.VAR9(VAR10));
endmodule | mit |
kactus2/ipxactexamplelib | tut.fi/cpu.logic/register_bank/1.0/register_bank.v | 3,245 | module MODULE1 #(
parameter VAR2 = 16, parameter VAR15 = 4, parameter VAR4 = 8 ) (
input VAR6, input VAR5,
input VAR1,
input [VAR2-1:0] VAR7,
input [VAR15-1:0] VAR12,
input [VAR15-1:0] VAR10,
input [VAR2-1:0] VAR13,
input VAR3,
input VAR11,
input [VAR2-1:0] VAR8,
output reg [VAR2-1:0] VAR14,
output reg [VAR2-1:0] VAR16... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai21/gf180mcu_fd_sc_mcu9t5v0__oai21_2.functional.pp.v | 1,290 | module MODULE1( VAR14, VAR5, VAR15, VAR10, VAR13, VAR9 );
input VAR10, VAR15, VAR14;
inout VAR13, VAR9;
output VAR5;
wire VAR7;
not VAR4( VAR7, VAR10 );
wire VAR3;
not VAR2( VAR3, VAR15 );
wire VAR12;
and VAR6( VAR12, VAR7, VAR3 );
wire VAR8;
not VAR11( VAR8, VAR14 );
or VAR1( VAR5, VAR12, VAR8 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or4b/sky130_fd_sc_lp__or4b_4.v | 2,291 | module MODULE1 (
VAR6 ,
VAR10 ,
VAR9 ,
VAR1 ,
VAR3 ,
VAR7,
VAR2,
VAR8 ,
VAR5
);
output VAR6 ;
input VAR10 ;
input VAR9 ;
input VAR1 ;
input VAR3 ;
input VAR7;
input VAR2;
input VAR8 ;
input VAR5 ;
VAR4 VAR11 (
.VAR6(VAR6),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a21boi/sky130_fd_sc_hs__a21boi.functional.v | 2,054 | module MODULE1 (
VAR13,
VAR12,
VAR8 ,
VAR16 ,
VAR3 ,
VAR5
);
input VAR13;
input VAR12;
output VAR8 ;
input VAR16 ;
input VAR3 ;
input VAR5;
wire VAR2 ;
wire VAR11 ;
wire VAR9 ;
wire VAR7;
not VAR6 (VAR2 , VAR5 );
and VAR14 (VAR11 , VAR16, VAR3 );
nor VAR1 (VAR9 , VAR2, VAR11 );
VAR10 VAR4 (VAR7, VAR9, VAR13, VAR12);
bu... | apache-2.0 |
titorgalaxy/Titor | rtl/verilog/core/Flow_Control.v | 5,388 | module MODULE1 (
VAR39,
VAR42,
VAR45,
VAR40,
VAR4,
VAR43,
VAR50,
VAR32,
VAR36,
VAR53,
VAR2,
VAR47,
VAR12,
VAR10,
VAR21,
VAR6,
VAR13,
interrupt,
VAR1
);
output reg [VAR24-1:0] VAR39;
output reg [VAR24-1:0] VAR42;
output reg [VAR24-1:0] VAR45;
output reg [VAR24-1:0] VAR40;
output reg [VAR24-1:0] VAR4;
output reg [VAR24-1... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/jtag_uart.v | 22,865 | module MODULE4 (
clk,
VAR4,
VAR18,
valid
)
;
input clk;
input [ 7: 0] VAR4;
input VAR18;
input valid;
reg [31:0] VAR68; VAR50 VAR68 =
always @(posedge clk) begin
if (valid && VAR18) begin
("%VAR19", ((VAR4 == 8'hd) ? 8'ha : VAR4));
VAR75 (VAR68);
end
end
endmodule
module MODULE7 (
clk,
VAR3,
VAR36,
VAR67,
VAR86,
VAR63,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/mux2/sky130_fd_sc_ls__mux2_2.v | 2,187 | module MODULE2 (
VAR7 ,
VAR4 ,
VAR10 ,
VAR6 ,
VAR3,
VAR9,
VAR1 ,
VAR5
);
output VAR7 ;
input VAR4 ;
input VAR10 ;
input VAR6 ;
input VAR3;
input VAR9;
input VAR1 ;
input VAR5 ;
VAR8 VAR2 (
.VAR7(VAR7),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR5(VAR5)
);
endmodule
module MODULE... | apache-2.0 |
SymbiFlow/prjuray | spec/slice.v | 14,557 | module MODULE3 #(
parameter [1023:0] VAR178 = "",
parameter [63:0] VAR161 = 64'h00C0FFEE,
parameter [63:0] VAR143 = 64'h00C0FFEE,
parameter [63:0] VAR173 = 64'h00C0FFEE,
parameter [63:0] VAR52 = 64'h00C0FFEE,
parameter [63:0] VAR22 = 64'h00C0FFEE,
parameter [63:0] VAR90 = 64'h00C0FFEE,
parameter [63:0] VAR120 = 64'h00C... | isc |
housq/lc3 | LC3_FSM.v | 6,222 | module MODULE1(
input clk,
input reset,
input VAR11,
input VAR4,
input [15:11] VAR7,
input VAR6,
input VAR9,
output reg[39:0] VAR3
);
wire [49:0] VAR5 [63:0];
reg [5:0] VAR2,VAR10;
reg [5:0] VAR8;
reg [2:0] VAR12;
reg VAR1;
assign VAR5[0 ] = 50'b00100100100000000000000000000000000000000000000000;
assign VAR5[1 ] = 50'b... | gpl-2.0 |
ProjectVault/orp | hardware/mselSoC/src/systems/geophyte/rtl/verilog/sdhc/rtl/verilog/ftl_logical.v | 19,531 | module MODULE1 (
input wire VAR28,
input wire VAR62,
output reg VAR85,
input wire VAR74,
output reg VAR91,
input wire VAR100,
input wire VAR63,
input wire [9:0] VAR3,
output reg VAR83,
output reg VAR90,
output reg VAR60, output reg [2:0] VAR66, output reg [15:0] VAR30, output reg [15:0] VAR76, output reg [41:0] VAR69, ... | apache-2.0 |
FPGA1988/udp_ip_stack | Network/udp_ip_core/trunk/ic/digital/rtl/eth_tri_mode/RMON/RMON_addr_gen.v | 11,354 | module MODULE1(
VAR19 ,
VAR1 ,
VAR6 ,
VAR13 ,
VAR14 ,VAR16 ,
VAR5 ,
VAR27 ,
VAR7 ,
VAR3 ,
VAR21
);
input VAR19 ;
input VAR1 ;
input [2:0] VAR6 ;
input [15:0] VAR13 ;
input VAR14 ;input [2:0] VAR16 ;
output VAR5 ;
output [4:0] VAR27 ;
output [15:0] VAR7 ;
input VAR3 ;
output VAR21 ;
parameter VAR4 =4'd0;
parameter VAR15... | apache-2.0 |
qeedquan/fpga | de2-115/up3/up3.v | 2,237 | module MODULE1
(
input wire clk,
input wire rst,
output reg [7:0] VAR12,
output reg [15:0] VAR17,
output wire [15:0] VAR11,
output reg [15:0] VAR4
);
localparam VAR18 = 0;
localparam VAR14 = 1;
localparam VAR27 = 2;
localparam VAR25 = 3;
localparam VAR28 = 4;
localparam VAR19 = 5;
localparam VAR13 = 6;
localparam VAR16... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_2.behavioral.pp.v | 1,174 | module MODULE1( VAR3, VAR5, VAR4, VAR1 );
input VAR3;
inout VAR4, VAR1;
output VAR5;
VAR7 VAR2(.VAR3(VAR3),.VAR5(VAR5),.VAR4(VAR4),.VAR1(VAR1));
VAR7 VAR6(.VAR3(VAR3),.VAR5(VAR5),.VAR4(VAR4),.VAR1(VAR1)); | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/xnor2/gf180mcu_fd_sc_mcu9t5v0__xnor2_2.behavioral.pp.v | 1,495 | module MODULE1( VAR3, VAR8, VAR5, VAR6, VAR2 );
input VAR8, VAR3;
inout VAR6, VAR2;
output VAR5;
VAR4 VAR1(.VAR3(VAR3),.VAR8(VAR8),.VAR5(VAR5),.VAR6(VAR6),.VAR2(VAR2));
VAR4 VAR7(.VAR3(VAR3),.VAR8(VAR8),.VAR5(VAR5),.VAR6(VAR6),.VAR2(VAR2)); | apache-2.0 |
alexforencich/verilog-ethernet | example/ADM_PCIE_9V3/fpga_10g/rtl/fpga.v | 21,029 | module MODULE1 (
input wire VAR235,
input wire VAR215,
output wire [1:0] VAR193,
output wire VAR180,
output wire [1:0] VAR102,
input wire [1:0] VAR131,
output wire VAR268,
output wire VAR52,
input wire VAR302,
input wire VAR70,
output wire VAR84,
output wire VAR66,
input wire VAR286,
input wire VAR57,
output wire VAR20... | mit |
GSejas/Karatsuba_FPU | FPGA_FLOW/Karat/MUL_FPU_FUNCIONAL_v1/MUL_FPU_FUNCIONAL_v1.srcs/sources_1/imports/rtl/KOA_FPGA.v | 8,889 | module MODULE1
(
input wire [VAR2-1:0] VAR20,
input wire [VAR2-1:0] VAR18,
output wire [2*VAR2-1:0] VAR17
);
wire [VAR2/2+1:0] VAR32;
wire [VAR2/2+1:0] VAR27;
wire [2*(VAR2/2)-1:0] VAR19;
wire [2*(VAR2/2+1)-1:0] VAR16;
wire [2*(VAR2/2+2)-1:0] VAR13;
wire [2*(VAR2/2+2)-1:0] VAR14;
wire [2*(VAR2/2+2)-1:0] VAR34;
wire [4*... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or3/sky130_fd_sc_lp__or3_2.v | 2,153 | module MODULE1 (
VAR7 ,
VAR6 ,
VAR1 ,
VAR4 ,
VAR8,
VAR10,
VAR3 ,
VAR9
);
output VAR7 ;
input VAR6 ;
input VAR1 ;
input VAR4 ;
input VAR8;
input VAR10;
input VAR3 ;
input VAR9 ;
VAR5 VAR2 (
.VAR7(VAR7),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR9(VAR9)
);
endmodule
module MODULE... | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_v6_gtx_x4_250/example_design/PIO.v | 5,966 | module MODULE1 #(
parameter VAR31 = 64,
parameter VAR22 = VAR31 / 8 )(
input VAR2,
input VAR7,
input VAR10,
input VAR19,
output [VAR31-1:0] VAR1,
output [VAR22-1:0] VAR13,
output VAR9,
output VAR32,
output VAR20,
input [VAR31-1:0] VAR12,
input [VAR22-1:0] VAR27,
input VAR17,
input VAR4,
output VAR24,
input [21:0] VAR15... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and3/sky130_fd_sc_ls__and3_2.v | 2,164 | module MODULE1 (
VAR9 ,
VAR2 ,
VAR7 ,
VAR6 ,
VAR1,
VAR8,
VAR4 ,
VAR3
);
output VAR9 ;
input VAR2 ;
input VAR7 ;
input VAR6 ;
input VAR1;
input VAR8;
input VAR4 ;
input VAR3 ;
VAR5 VAR10 (
.VAR9(VAR9),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR3(VAR3)
);
endmodule
module MODULE1 (... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o21ai/sky130_fd_sc_hd__o21ai.functional.pp.v | 2,010 | module MODULE1 (
VAR15 ,
VAR7 ,
VAR3 ,
VAR14 ,
VAR13,
VAR2,
VAR6 ,
VAR5
);
output VAR15 ;
input VAR7 ;
input VAR3 ;
input VAR14 ;
input VAR13;
input VAR2;
input VAR6 ;
input VAR5 ;
wire VAR4 ;
wire VAR1 ;
wire VAR8;
or VAR10 (VAR4 , VAR3, VAR7 );
nand VAR12 (VAR1 , VAR14, VAR4 );
VAR9 VAR11 (VAR8, VAR1, VAR13, VAR2);
b... | apache-2.0 |
google/myelin-acorn-electron-hardware | econet_from_scratch/cpld/econet.v | 16,520 | module MODULE1(
input wire VAR27, output reg VAR36 = 1'b1, input wire VAR1, input wire VAR38, output reg VAR37 = 1'b0, output wire VAR2, input wire VAR10, input wire VAR6,
input wire VAR16, output wire VAR4, output wire VAR44, input wire VAR9, output wire VAR25, output wire VAR26,
input wire VAR11,
input wire VAR22,
in... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfrbp/sky130_fd_sc_hdll__sdfrbp.blackbox.v | 1,493 | module MODULE1 (
VAR6 ,
VAR4 ,
VAR9 ,
VAR8 ,
VAR7 ,
VAR2 ,
VAR10
);
output VAR6 ;
output VAR4 ;
input VAR9 ;
input VAR8 ;
input VAR7 ;
input VAR2 ;
input VAR10;
supply1 VAR11;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
seyedmaysamlavasani/GorillaPP | apps/lib/floatingPoints/common/types_float_double.v | 14,189 | module MODULE1 (
VAR116,
VAR22,
VAR111,
VAR75,
VAR49,
VAR98,
VAR107,
VAR23,
VAR44,
VAR83,
VAR26,
VAR7,
VAR95,
VAR106,
VAR37,
VAR38,
VAR11
);
input VAR116;
input VAR22;
input VAR111;
output VAR75;
output VAR49;
input [63:0] VAR98;
input [63:0] VAR107;
input [63:0] VAR23;
input [31:0] VAR44;
output [63:0] VAR83;
output V... | bsd-3-clause |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/NIOS_SYSTEMV3/synthesis/submodules/NIOS_SYSTEMV3_tristate_bridge_ssram_pinSharer.v | 6,081 | module MODULE1 (
input wire VAR40, input wire VAR10, output wire request, input wire VAR8, output wire [0:0] VAR4, output wire [3:0] VAR35, output wire [0:0] VAR23, output wire [0:0] VAR43, output wire [31:0] VAR31, input wire [31:0] VAR5, output wire VAR19, output wire [20:0] VAR28, output wire [0:0] VAR42, output wir... | gpl-2.0 |
aquaxis/FPGAMAG18 | fmrv32im-artya7.madd33/fmrv32im-artya7.srcs/sources_1/bd/fmrv32im_artya7/ipshared/0208/src/fmrv32im_timer.v | 1,063 | module MODULE1
(
input VAR5,
input VAR4,
input VAR3,
input [3:0] VAR7,
input [31:0] VAR1,
output reg [31:0] VAR6,
output wire VAR2
);
reg [31:0] counter, VAR8;
always @(posedge VAR4) begin
if(!VAR5) begin
counter <= 0;
VAR8 <= 0;
end else begin
if(VAR3 & (VAR7 == 4'h0)) begin
counter <= VAR1;
end else begin
counter <= ... | mit |
alan4186/ParCNN | Hardware/v/softmax/normalize.v | 2,437 | module MODULE1(
input VAR17,
input reset,
input [(VAR8*VAR22)-1:0] VAR25,
output [(VAR20*VAR22)-1:0] VAR4
);
wire [VAR16:0] VAR7 [VAR22];
wire [VAR24:0] VAR18 [((VAR22)*2)-1];
reg [VAR24:0] VAR19 [VAR22];
genvar VAR14;
generate
for(VAR14 = 0; VAR14 < VAR22; VAR14=VAR14+1) begin : VAR23
assign VAR7[VAR14] = VAR25[(VAR8*... | mit |
FrankMuenzner/proxmark3 | fpga/lo_edge_detect.v | 2,137 | module MODULE1(
VAR23, VAR12, VAR4,
VAR1, VAR24, VAR22, VAR17, VAR21, VAR14,
VAR2, VAR9,
VAR8, VAR11, VAR20, VAR26,
VAR13, VAR3,
VAR7,
VAR5,
VAR10
);
input VAR23, VAR12, VAR4;
output VAR1, VAR24, VAR22, VAR17, VAR21, VAR14;
input [7:0] VAR2;
output VAR9;
input VAR20;
output VAR8, VAR11, VAR26;
input VAR13, VAR3;
output... | gpl-2.0 |
asicguy/gplgpu | hdl/altera_clk_synth/bt_ddr_io.v | 4,505 | module MODULE1 (
VAR2,
VAR18,
VAR9,
VAR14,
VAR5);
input VAR2;
input [0:0] VAR18;
input [0:0] VAR9;
input VAR14;
output [0:0] VAR5;
wire [0:0] VAR15;
wire [0:0] VAR5 = VAR15[0:0];
VAR6 VAR27 (
.VAR2 (VAR2),
.VAR18 (VAR18),
.VAR9 (VAR9),
.VAR14 (VAR14),
.VAR5 (VAR15),
.VAR13 (1'b0),
.VAR8 (1'b1),
.VAR7 (),
.VAR11 (1'b1),... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/einvn/sky130_fd_sc_hs__einvn.symbol.v | 1,299 | module MODULE1 (
input VAR4 ,
output VAR2 ,
input VAR1
);
supply1 VAR5;
supply0 VAR3;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/ebufn/sky130_fd_sc_ls__ebufn.behavioral.v | 1,312 | module MODULE1 (
VAR4 ,
VAR8 ,
VAR1
);
output VAR4 ;
input VAR8 ;
input VAR1;
supply1 VAR5;
supply0 VAR3;
supply1 VAR7 ;
supply0 VAR6 ;
bufif0 VAR2 (VAR4 , VAR8, VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o21a/sky130_fd_sc_hd__o21a.pp.symbol.v | 1,344 | module MODULE1 (
input VAR7 ,
input VAR1 ,
input VAR5 ,
output VAR2 ,
input VAR6 ,
input VAR8,
input VAR4,
input VAR3
);
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v5_mig34/mig_v3_4/user_design/rtl/ddr2_usr_wr.v | 13,347 | module MODULE1 #
(
parameter VAR20 = 2,
parameter VAR16 = 10,
parameter VAR69 = 0,
parameter VAR4 = 72,
parameter VAR2 = 144,
parameter VAR64 = 0,
parameter VAR5 = 14
)
(
input VAR3,
input VAR45,
input VAR22,
input VAR17,
input [VAR2-1:0] VAR37,
input [(VAR2/8)-1:0] VAR60,
input VAR51,
output VAR41,
output [(2*VAR4)-1:... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a222oi/sky130_fd_sc_ls__a222oi.pp.symbol.v | 1,427 | module MODULE1 (
input VAR10 ,
input VAR2 ,
input VAR6 ,
input VAR7 ,
input VAR4 ,
input VAR3 ,
output VAR1 ,
input VAR8 ,
input VAR5,
input VAR9,
input VAR11
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/buf/sky130_fd_sc_lp__buf.functional.v | 1,223 | module MODULE1 (
VAR4,
VAR1
);
output VAR4;
input VAR1;
wire VAR5;
buf VAR3 (VAR5, VAR1 );
buf VAR2 (VAR4 , VAR5 );
endmodule | apache-2.0 |
eda-globetrotter/MarcheProcessor | processor/spare/build2/alicia.v | 1,659 | module MODULE1();
reg VAR1;
reg VAR11;
reg VAR8;
reg VAR10;
reg VAR5;
reg [1:0] VAR4;
reg VAR3;
reg VAR9;
reg [0:7] VAR6;
reg [0:7] VAR2;
reg [0:7] VAR7;
begin | mit |
ptracton/wb_soc_template | rtl/MOR1KX/rtl/verilog/mor1kx_rf_espresso.v | 4,607 | module MODULE1
(
VAR40, VAR31,
clk, rst, VAR29, VAR37, VAR14, VAR19, VAR28,
VAR17
);
parameter VAR7 = 5;
parameter VAR35 = 32;
parameter VAR9 = 32;
input clk, rst;
input [VAR7-1:0] VAR29;
input [VAR7-1:0] VAR37;
input [VAR7-1:0] VAR14;
input VAR19;
input VAR28;
input [VAR9-1:0] VAR17;
output [VAR9-1:0] VAR40;
output [V... | mit |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_SEQ_SRAM_FF_210930.v | 73,272 | module MODULE1 (VAR3, VAR11, VAR14, VAR7);
output VAR3;
input VAR11, VAR14, VAR7;
reg VAR16;
wire VAR4, VAR12;
wire VAR10, VAR8, VAR1;
wire VAR13;
not (VAR10, VAR4);
not (VAR1, VAR14);
VAR9 (VAR13, VAR12, VAR10, VAR1);
VAR2 (VAR8, VAR16, VAR12, VAR10, VAR1, VAR13);
buf (VAR3, VAR8);
wire VAR6, VAR5, VAR15;
and (VAR6, V... | bsd-3-clause |
spesialstyrker/boula | src/axi2ocp.v | 14,014 | module MODULE1(
input wire clk,
input wire reset,
output reg VAR18,
input wire VAR8,
output reg VAR26,
input wire [VAR23 - 1:0] VAR45,
input wire [VAR44 - 1:0] VAR16,
input wire VAR27,
input wire VAR53,
output reg [VAR10 - 1:0] address,
output reg enable,
output reg [2:0] VAR2,
output reg VAR50,
output reg [9:0] VAR6,
... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_misc/rtl/bw_io_hstl_edgelogic.v | 6,131 | module MODULE1(
VAR35, VAR11, VAR60, VAR7, VAR46, VAR30,
VAR65, VAR52, VAR31,
VAR54, VAR20, VAR29, VAR9, VAR70, clk, VAR47, VAR27,
VAR3, VAR6, VAR24, VAR58
);
input VAR54;
input VAR20;
input VAR29;
input VAR9;
input VAR70;
input clk;
input VAR47;
input VAR27;
input VAR3;
input VAR6;
input [5:4] VAR24;
input VAR58;
outp... | gpl-2.0 |
bbrown1867/ObjectTracking | hw/common/delta_frame.v | 2,482 | module MODULE1 #(
parameter VAR10 = 10,
parameter VAR9 = 20,
parameter VAR17 = 5
)(
input wire clk,
input wire VAR8,
input wire VAR2,
input wire VAR13,
input wire [(VAR10-1):0] VAR11,
input wire [(VAR10-1):0] VAR7,
input wire [(VAR10-1):0] VAR1,
output wire [(VAR10-1):0] MODULE1
);
localparam VAR15 = VAR17 + VAR10;
gen... | mit |
fbalakirev/red-pitaya-notes | cores/gpio_trigger_master_v1_0/gpio_trigger_master.v | 1,595 | module MODULE1 #
(
parameter integer VAR20 = 8,
parameter integer VAR18 = 2,
parameter integer VAR1 = 6
)
(
input wire VAR16,
input wire VAR14,
inout wire [VAR20-1:0] VAR7,
input wire VAR22,
output wire VAR19
);
reg [VAR20-1:0] VAR21 [1:0];
reg VAR2, VAR11;
wire [VAR20-1:0] VAR4;
wire [VAR1-1:0] VAR9;
genvar VAR13;
gen... | mit |
keith-epidev/VHDL-lib | top/mono_radio/ip/fir_lp_800kHz_0/fir_lp_800kHz_stub.v | 1,499 | module MODULE1(VAR2, VAR1, VAR4, VAR5, VAR3, VAR6)
;
input VAR2;
input VAR1;
output VAR4;
input [31:0]VAR5;
output VAR3;
output [95:0]VAR6;
endmodule | gpl-2.0 |
google/xls | xls/uncore_rtl/ice40/uart_receiver.v | 9,731 | module MODULE1(
input wire clk,
input wire VAR17,
input wire VAR21,
input wire VAR3,
output wire VAR14,
output wire [7:0] VAR9,
output wire VAR16
);
parameter VAR11 = 1250;
localparam VAR5 = (VAR11 >> 2);
localparam VAR4 = VAR5-1;
localparam VAR12 = VAR2(VAR11 >> 1);
localparam
VAR24 = 'd0,
VAR18 = 'd1,
VAR32 = 'd2,
VA... | apache-2.0 |
ShepardSiegel/ocpi | scripts/auguste/BRAM2.v | 3,758 | module MODULE1(VAR6,
VAR20,
VAR19,
VAR17,
VAR22,
VAR14,
VAR11,
VAR3,
VAR10,
VAR21,
VAR12,
VAR16
);
parameter VAR18 = 0;
parameter VAR13 = 1;
parameter VAR9 = 1;
parameter VAR2 = 1;
input VAR6;
input VAR20;
input VAR19;
input [VAR13-1:0] VAR17;
input [VAR9-1:0] VAR22;
output [VAR9-1:0] VAR14;
input VAR11;
input VAR3;
in... | lgpl-3.0 |
esonghori/TinyGarbled | circuit_synthesis/aes/MixColumns.v | 1,299 | module MODULE2 (
output [7:0] VAR8,
input [7:0] VAR4
);
wire [7:0] VAR14;
assign VAR14 = VAR4 << 1;
assign VAR8 = VAR4[7]? VAR14 ^ 8'h1B : VAR14;
endmodule
module MODULE1(
VAR4,
VAR16);
input [127:0] VAR4;
output [127:0] VAR16;
generate
genvar VAR12;
for (VAR12 = 0; VAR12 < 4; VAR12 = VAR12 + 1) begin: VAR2
wire[7:0] V... | gpl-3.0 |
nikhilghanathe/HLS-for-EMTF | verilog/sp_mux_4to1_sel2_7_1.v | 1,201 | module MODULE1 #(
parameter
VAR4 = 0,
VAR1 = 1,
VAR3 = 32,
VAR15 = 32,
VAR8 = 32,
VAR5 = 32,
VAR9 = 32,
VAR16 = 32
)(
input [6 : 0] VAR2,
input [6 : 0] VAR14,
input [6 : 0] VAR13,
input [6 : 0] VAR6,
input [1 : 0] VAR12,
output [6 : 0] dout);
wire [1 : 0] sel;
wire [6 : 0] VAR10;
wire [6 : 0] VAR11;
wire [6 : 0] VAR7;
... | apache-2.0 |
CospanDesign/nysa-artemis-usb2-platform | artemis_usb2/slave/wb_artemis_pcie_platform/rtl/c/axi_basic_tx.v | 10,105 | module MODULE1 #(
parameter VAR12 = 128, parameter VAR44 = "VAR7", parameter VAR37 = "VAR36", parameter VAR41 = "VAR36", parameter VAR31 = 1,
parameter VAR10 = (VAR12 == 128) ? 2 : 1, parameter VAR30 = VAR12 / 8 ) (
input [VAR12-1:0] VAR47, input VAR19, output VAR1, input [VAR30-1:0] VAR25, input VAR13, input [3:0] VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor3b/sky130_fd_sc_hdll__nor3b_2.v | 2,270 | module MODULE2 (
VAR4 ,
VAR10 ,
VAR7 ,
VAR1 ,
VAR5,
VAR8,
VAR9 ,
VAR2
);
output VAR4 ;
input VAR10 ;
input VAR7 ;
input VAR1 ;
input VAR5;
input VAR8;
input VAR9 ;
input VAR2 ;
VAR6 VAR3 (
.VAR4(VAR4),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR2(VAR2)
);
endmodule
module MODULE... | apache-2.0 |
Siliciumer/DOS-Mario-FPGA | sources/new_block.v | 4,593 | module MODULE1(
input wire [5:0] VAR41,
input wire VAR36,
input wire VAR9,
input wire [9:0] VAR40,
input wire [8:0] VAR33,
output reg [5:0] VAR1,
output reg VAR11,
output reg VAR22
);
always @* begin
if(VAR41 == VAR28) begin
VAR22 = 1;
VAR1 = VAR3;
VAR11 = 1;
end
else if(((VAR40 % 40) < 20) && (VAR9 == 0)) begin
if(VAR... | mit |
zhaoyang10/mips-cpu | verilog/regm.v | 2,005 | module MODULE1(
input wire clk,
input wire [4:0] VAR5, VAR2,
output wire [31:0] VAR7, VAR1,
input wire VAR8,
input wire [4:0] VAR3,
input wire [31:0] VAR6);
reg [31:0] VAR4 [0:31];
reg [31:0] VAR7, VAR1; | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfxtp/sky130_fd_sc_hd__dfxtp.behavioral.v | 1,760 | module MODULE1 (
VAR2 ,
VAR14,
VAR15
);
output VAR2 ;
input VAR14;
input VAR15 ;
supply1 VAR10;
supply0 VAR7;
supply1 VAR13 ;
supply0 VAR3 ;
wire VAR4 ;
reg VAR12 ;
wire VAR1 ;
wire VAR9;
wire VAR11 ;
VAR6 VAR8 (VAR4 , VAR1, VAR9, VAR12, VAR10, VAR7);
assign VAR11 = ( VAR10 === 1'b1 );
buf VAR5 (VAR2 , VAR4 );
endmodul... | apache-2.0 |
yyang29/MIPS | design/mips_syscallUnit.v | 2,301 | module MODULE1 (
VAR5,
VAR2, VAR1, VAR6, VAR3, clk
);
output wire VAR5;
input [31:0] VAR2, VAR1;
input VAR6, VAR3, clk;
assign VAR5 = VAR3 && VAR6 && (VAR1 == VAR4);
always @(posedge clk)
if (VAR3 && VAR6)
case(VAR1)
end
endcase
endmodule | gpl-2.0 |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/system/synthesis/system.v | 45,553 | module MODULE1 (
input wire VAR13, output wire VAR256, output wire [14:0] VAR280, output wire [2:0] VAR205, output wire VAR81, output wire VAR64, output wire VAR15, output wire VAR26, output wire VAR160, output wire VAR171, output wire VAR30, output wire VAR240, inout wire [31:0] VAR31, inout wire [3:0] VAR218, inout w... | mit |
cagiurumescu/pmod_oled_s3e | src/milisecond_timer.v | 2,426 | module MODULE1 #(
parameter VAR6 = 50,
parameter VAR16 = 12
) (
input clk,
input reset,
input VAR11,
input [VAR16-1:0] VAR2,
output VAR5
);
localparam VAR1 = VAR14'h0;
localparam VAR10 = VAR14'h1;
localparam VAR17 = VAR14'h2;
localparam VAR3 = VAR8(VAR6);
reg [VAR14-1:0] VAR15;
reg [VAR16-1:0] VAR13;
reg [VAR16-1:0] VA... | gpl-2.0 |
GSejas/Karatsuba_FPU | ASIC_FLOW/global_sources/KOA_FPGA.v | 8,912 | module MODULE1
(
input wire [VAR8-1:0] VAR26,
input wire [VAR8-1:0] VAR17,
output wire [2*VAR8-1:0] VAR3
);
wire [VAR8/2+1:0] VAR25;
wire [VAR8/2+1:0] VAR24;
wire [2*(VAR8/2)-1:0] VAR31;
wire [2*(VAR8/2+1)-1:0] VAR19;
wire [2*(VAR8/2+2)-1:0] VAR12;
wire [2*(VAR8/2+2)-1:0] VAR13;
wire [2*(VAR8/2+2)-1:0] VAR1;
wire [4*(V... | gpl-3.0 |
h-j-13/MyNote | Programming language/Verilog/sync_FIFO/参考源码/fifo_backup.v | 3,973 | module MODULE1(VAR2,reset,read,write,VAR13,VAR19,VAR16,VAR11);
parameter VAR14 = 128; parameter VAR15 = 7; parameter VAR22 = 4; parameter VAR17 = 7'b1111111;
parameter
VAR1=7'b0000001,
VAR21=7'b1001111,
VAR9=7'b0010010,
VAR4=7'b0000110,
VAR10=7'b1001100,
VAR27=7'b0100100,
VAR24=7'b0100000,
VAR25=7'b0001101,
VAR8=7'b000... | gpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_ad9643_v1_00_a/hdl/verilog/axi_ad9643_pnmon.v | 9,158 | module MODULE1 (
VAR16,
VAR10,
VAR24,
VAR21,
VAR9);
input VAR16;
input [13:0] VAR10;
output VAR24;
output VAR21;
input VAR9;
reg VAR17 = 'd0;
reg [13:0] VAR6 = 'd0;
reg [13:0] VAR15 = 'd0;
reg [29:0] VAR18 = 'd0;
reg VAR12 = 'd0;
reg VAR20 = 'd0;
reg VAR22 = 'd0;
reg VAR4 = 'd0;
reg VAR21 = 'd0;
reg [ 6:0] VAR7 = 'd0;
... | mit |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.