repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
hakehuang/pycpld | ips/ip/led_capture/led_capture.v | 2,783 | module MODULE1(
VAR6,clk,VAR15,VAR1,VAR2
);
input VAR6;
input clk;
input VAR15;
output VAR1;
output[7:0] VAR2;
reg ready;
reg[31:0] counter;
reg[31:0] VAR4;
reg[31:0] VAR5;
reg[31:0] VAR9;
reg VAR13;
reg VAR11;
wire VAR7;
always @(posedge clk or negedge VAR15)begin
if(!VAR15) begin
counter <= 'h0;
end
else begin
counte... | mit |
wgml/sysrek | uart_echo/UART_Rx.v | 2,581 | module MODULE1(
input VAR2,
output reg [7:0] VAR16 = 8'b00000000,
input VAR4,
input VAR15,
input VAR13,
output reg VAR3 = 1'b0
);
parameter VAR5 = 1000000;
parameter VAR8 = 9600;
localparam VAR10 = 4;
localparam VAR18 = VAR5/(VAR8*VAR10*2);
reg [VAR6(VAR18)-1:0]VAR12 = 0;
reg VAR17;
reg VAR1 = 1'b0;
always @ (posedge V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/edfxbp/sky130_fd_sc_hd__edfxbp.blackbox.v | 1,378 | module MODULE1 (
VAR7 ,
VAR3,
VAR1,
VAR2 ,
VAR8
);
output VAR7 ;
output VAR3;
input VAR1;
input VAR2 ;
input VAR8 ;
supply1 VAR9;
supply0 VAR6;
supply1 VAR5 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
Digilent/vivado-library | ip/hls_gamma_correction_1_0/hdl/verilog/fifo_w8_d2_A.v | 2,971 | module MODULE1 (
clk,
VAR19,
VAR5,
VAR20,
VAR17);
parameter VAR11 = 32'd8;
parameter VAR2 = 32'd2;
parameter VAR13 = 32'd3;
input clk;
input [VAR11-1:0] VAR19;
input VAR5;
input [VAR2-1:0] VAR20;
output [VAR11-1:0] VAR17;
reg[VAR11-1:0] VAR12 [0:VAR13-1];
integer VAR15;
always @ (posedge clk)
begin
if (VAR5)
begin
for ... | mit |
azonenberg/yosys | techlibs/intel/common/m9k_bb.v | 3,074 | module MODULE1(VAR20, VAR2, VAR18, VAR14, VAR52, VAR24, VAR4, VAR35, VAR15,
VAR28, VAR54, VAR45, VAR40, VAR34, VAR16, VAR26, VAR25, VAR10,
VAR57, VAR8);
parameter VAR41 = "VAR9";
parameter VAR21 = "VAR9";
parameter VAR53 = "VAR12";
parameter VAR37 = "VAR12";
parameter VAR5 = "VAR1";
parameter VAR6 = "VAR1";
parameter V... | isc |
hcabrera-/lancetfish | RTL/router/rtl/outport_scheduler.v | 4,083 | module MODULE1 #(
parameter VAR10 = VAR2
)
(
input wire clk,
input wire reset,
input wire [3:0] VAR6,
input wire VAR21,
output wire [3:0] VAR20,
output wire [3:0] VAR25,
output wire VAR19
);
localparam VAR1 = 1'b0;
localparam VAR24 = 1'b1;
wire VAR11;
wire VAR18;
wire VAR3;
wire VAR14;
wire VAR17;
assign VAR17 = |VAR6;... | gpl-3.0 |
cliffordwolf/picorv32 | scripts/vivado/system.v | 2,834 | module MODULE1 (
input clk,
input VAR13,
output VAR16,
output reg [7:0] VAR20,
output reg VAR7
);
parameter VAR18 = 1;
parameter VAR10 = 4096;
wire VAR19;
wire VAR3;
reg VAR9;
wire [31:0] VAR14;
wire [31:0] VAR15;
wire [3:0] VAR5;
reg [31:0] VAR11;
wire VAR12;
wire VAR6;
wire [31:0] VAR8;
wire [31:0] VAR17;
wire [3:0] ... | isc |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o2111ai/sky130_fd_sc_ls__o2111ai.blackbox.v | 1,402 | module MODULE1 (
VAR3 ,
VAR4,
VAR1,
VAR9,
VAR5,
VAR7
);
output VAR3 ;
input VAR4;
input VAR1;
input VAR9;
input VAR5;
input VAR7;
supply1 VAR10;
supply0 VAR6;
supply1 VAR2 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
liuyenting/CA-Project | src/dcache_top.v | 5,786 | module MODULE1
(
VAR50,
VAR31,
VAR43,
VAR2,
VAR22,
VAR23,
VAR11,
VAR9,
VAR18,
VAR20,
VAR26,
VAR38,
VAR7,
VAR45
);
input VAR50;
input VAR31;
input [256-1:0] VAR43;
input VAR2;
output [256-1:0] VAR22;
output [32-1:0] VAR23;
output VAR11;
output VAR9;
input [32-1:0] VAR18;
input [32-1:0] VAR20;
input VAR26;
input VAR38;
o... | gpl-3.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_34.v | 25,372 | module MODULE1 (
clk,
reset,
VAR120,
VAR83,
VAR29,
VAR153,
VAR200
);
parameter VAR136 = 18;
parameter VAR202 = 34;
parameter VAR152 = 17;
localparam VAR170 = 41;
input clk;
input reset;
input VAR120;
input VAR83;
input [VAR136-1:0] VAR29; output VAR153;
output [VAR136-1:0] VAR200;
localparam VAR49 = 18; localparam VAR7... | mit |
lvd2/zxevo | fpga/current/z80/zbus.v | 1,356 | module MODULE1(
input VAR8,
input VAR1,
input VAR3,
input VAR10,
output VAR7,
output VAR4,
input VAR5,
input VAR9,
input VAR6,
output VAR2
);
assign VAR7 = VAR8 | VAR6;
assign VAR4 = VAR7 | VAR5;
assign VAR2 = ( (~(VAR4|VAR9)) & (~VAR1) ) | (~(VAR10|VAR8));
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/tapvpwrvgnd/sky130_fd_sc_hdll__tapvpwrvgnd.functional.v | 1,075 | module MODULE1 ();
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfrtn/sky130_fd_sc_hs__dfrtn.pp.symbol.v | 1,397 | module MODULE1 (
input VAR5 ,
output VAR6 ,
input VAR1,
input VAR3 ,
input VAR2 ,
input VAR4
);
endmodule | apache-2.0 |
rkrajnc/minimig-de1 | lib/vga/vga_monitor.v | 2,867 | module MODULE1 #(
parameter VAR18 = 1, parameter VAR4 = 4, parameter VAR20 = 4, parameter VAR17 = 4, parameter VAR12 = 8, parameter VAR10 = 3, parameter VAR7 = "VAR13", parameter VAR22 = 32, parameter VAR9 = "VAR3", parameter VAR8 = "" )(
input wire clk, input wire VAR21, input wire [ 7-1:0] VAR2, input wire VAR11, inp... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor4bb/sky130_fd_sc_ls__nor4bb.functional.pp.v | 1,998 | module MODULE1 (
VAR14 ,
VAR16 ,
VAR1 ,
VAR17 ,
VAR6 ,
VAR15,
VAR8,
VAR10 ,
VAR7
);
output VAR14 ;
input VAR16 ;
input VAR1 ;
input VAR17 ;
input VAR6 ;
input VAR15;
input VAR8;
input VAR10 ;
input VAR7 ;
wire VAR13 ;
wire VAR11 ;
wire VAR3;
nor VAR12 (VAR13 , VAR16, VAR1 );
and VAR5 (VAR11 , VAR13, VAR17, VAR6 );
VAR2... | apache-2.0 |
ueliem/literate-broccoli | last_row_routing.v | 1,694 | module MODULE1(
input [VAR6*VAR1*12-1:0] VAR12,
inout [VAR1-1:0] VAR4, VAR7,
inout [VAR1*VAR6-1:0] VAR2, VAR9
);
parameter VAR1 = 3;
parameter VAR6 = 5;
wire [VAR1-1:0] VAR11[VAR6-1:0];
genvar VAR3;
generate
for (VAR3 = 0; VAR3 < VAR6-1; VAR3 = VAR3 + 1) begin
localparam VAR5 = VAR3*VAR1*12;
localparam VAR10 = VAR3*VAR... | gpl-3.0 |
jotego/jt12 | hdl/deprecated/jt12_opram.v | 1,092 | module MODULE1
(
input [4:0] VAR1,
input [4:0] VAR3,
input clk,
input VAR5,
input [43:0] VAR4,
output reg [43:0] VAR6
);
reg [43:0] VAR2[31:0];
always @ (posedge clk) if(VAR5) begin
VAR6 <= VAR2[VAR3];
VAR2[VAR1] <= VAR4;
end
endmodule | gpl-3.0 |
peteasa/parallella-fpga | AdiHDLLib/library/prcfg/common/prcfg_top.v | 11,639 | module MODULE1(
clk,
VAR30,
VAR4,
VAR79,
VAR64,
VAR38,
VAR35,
VAR93,
VAR18,
VAR73,
VAR52,
VAR55,
VAR75,
VAR76,
VAR63,
VAR31,
VAR92,
VAR37,
VAR7,
VAR5,
VAR44,
VAR83,
VAR54,
VAR11,
VAR47,
VAR91,
VAR20,
VAR65,
VAR69,
VAR78,
VAR61,
VAR53,
VAR15,
VAR51,
VAR86,
VAR12,
VAR22,
VAR87,
VAR84,
VAR80,
VAR50,
VAR59,
VAR43,
VAR56,
V... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.blackbox.v | 1,311 | module MODULE1 (
VAR4,
VAR1 ,
VAR3 ,
VAR2
);
output VAR4;
input VAR1 ;
input VAR3 ;
input VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand2b/sky130_fd_sc_lp__nand2b_1.v | 2,147 | module MODULE2 (
VAR9 ,
VAR6 ,
VAR5 ,
VAR4,
VAR3,
VAR2 ,
VAR1
);
output VAR9 ;
input VAR6 ;
input VAR5 ;
input VAR4;
input VAR3;
input VAR2 ;
input VAR1 ;
VAR8 VAR7 (
.VAR9(VAR9),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR9 ,
VAR6,
VAR5
);
output VAR9 ... | apache-2.0 |
aj-michael/Digital-Systems | Pong/Phase4/UniversalCounter10bitsV5.v | 1,048 | module MODULE1(VAR9,VAR4, VAR10, VAR5,VAR8,VAR1,VAR2, VAR6, VAR11) ;
parameter VAR7 = 10;
input VAR8, VAR1, VAR6, VAR11;
input [VAR7-1:0] VAR9, VAR4, VAR10;
output reg [VAR7-1:0] VAR5;
output reg VAR2; reg [VAR7-1:0] VAR3;
always @ (posedge VAR11 or posedge VAR6)
if(VAR6==1) VAR5 <= VAR4;
else VAR5<=VAR3;
always@(VAR5 ... | mit |
origintfj/riscv | rv32i/rtl/merlin_rv32ic_expander.v | 10,018 | module MODULE1
(
input wire [15:0] VAR5,
output reg VAR1,
output reg VAR4,
output reg [31:0] VAR2
);
wire [1:0] VAR6;
wire [2:0] VAR3;
assign VAR6 = VAR5[1:0];
assign VAR3 = VAR5[15:13];
always @ (*) begin
VAR1 = 1'b1;
VAR4 = 1'b0;
VAR2 = 32'b0; case (VAR6)
2'b00 : begin
case (VAR3)
3'b000 : begin if (VAR5[12:2] == 11'... | apache-2.0 |
jairov4/accel-oil | solution_virtex5/syn/verilog/sample_iterator_get_offset.v | 10,394 | module MODULE1 (
VAR8,
VAR7,
VAR54,
VAR13,
VAR51,
VAR9,
VAR41,
VAR24,
VAR50,
VAR44,
VAR38,
VAR45,
VAR48,
VAR32,
VAR35,
VAR47,
VAR6,
VAR42,
VAR43,
VAR11,
VAR21
);
parameter VAR17 = 1'b1;
parameter VAR52 = 1'b0;
parameter VAR30 = 1'b0;
parameter VAR33 = 32'b1;
parameter VAR14 = 32'b110000;
parameter VAR20 = 32'b110111;
p... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21ai/sky130_fd_sc_lp__o21ai_m.v | 2,258 | module MODULE1 (
VAR5 ,
VAR3 ,
VAR7 ,
VAR2 ,
VAR6,
VAR1,
VAR9 ,
VAR10
);
output VAR5 ;
input VAR3 ;
input VAR7 ;
input VAR2 ;
input VAR6;
input VAR1;
input VAR9 ;
input VAR10 ;
VAR4 VAR8 (
.VAR5(VAR5),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR10(VAR10)
);
endmodule
module MODULE... | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project.xpr/project_1/project_1.ipdefs/ip_0/RecComp_cnn_lab_convolve_kernel_1_0/hdl/verilog/convolve_kernel_control_s_axi.v | 8,989 | module MODULE1
VAR7 = 4,
VAR29 = 32
)(
input wire VAR20,
input wire VAR41,
input wire VAR10,
input wire [VAR7-1:0] VAR43,
input wire VAR12,
output wire VAR21,
input wire [VAR29-1:0] VAR50,
input wire [VAR29/8-1:0] VAR46,
input wire VAR26,
output wire VAR52,
output wire [1:0] VAR48,
output wire VAR14,
input wire VAR39,
... | mit |
fbalakirev/red-pitaya-notes | cores/axis_delay_v1_0/axis_delay.v | 1,823 | module MODULE1 #
(
parameter integer VAR12 = 32,
parameter integer VAR4 = 32
)
(
input wire VAR19,
input wire VAR17,
input wire [VAR4-1:0] VAR10,
input wire [VAR4-1:0] VAR18,
output wire VAR13,
input wire [VAR12-1:0] VAR14,
input wire VAR16,
input wire VAR6,
output wire [VAR12-1:0] VAR20,
output wire VAR21,
output wire... | mit |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/wb_output_pins32.v | 1,949 | module MODULE1
(VAR6, VAR3, VAR2, VAR5,
VAR1, VAR7, VAR10, VAR9, VAR4,
VAR11);
input VAR6;
input VAR3;
input wire [31:0] VAR2;
output wire [31:0] VAR5;
input VAR1;
input wire [3:0] VAR7;
input VAR10;
output VAR9;
input VAR4;
output wire [31:0] VAR11;
reg [31:0] VAR8;
always @(posedge VAR3)
if(VAR6)
VAR8 <= 32'b0;
else
... | gpl-2.0 |
Digilent/vivado-library | ip/hls_contrast_stretch_1_0/hdl/verilog/CvtColor.v | 33,810 | module MODULE1 (
VAR156,
VAR95,
VAR72,
VAR48,
VAR118,
VAR166,
VAR188,
VAR31,
VAR183,
VAR66,
VAR76,
VAR125,
VAR74,
VAR142,
VAR99,
VAR50,
VAR70,
VAR122,
VAR51,
VAR3,
VAR141,
VAR101,
VAR116,
VAR1,
VAR39,
VAR89,
VAR6,
VAR167,
VAR11,
VAR185,
VAR191
);
parameter VAR24 = 4'd1;
parameter VAR20 = 4'd2;
parameter VAR128 = 4'd4;
... | mit |
yugr/primogen | src/primogen_bench.v | 1,041 | module MODULE1;
reg clk = 0;
wire rst;
reg VAR8 = 0;
reg [31:0] VAR2 = 0;
reg [31:0] VAR13 = 0;
reg VAR11 = 0;
wire [15:0] VAR12;
wire VAR7;
wire VAR5;
VAR3 VAR4(
.clk(clk),
.rst(rst));
VAR1 VAR9(
.clk(clk),
.VAR8(VAR8),
.rst(rst),
.VAR10(VAR12),
.ready(VAR7),
.VAR6(VAR5));
always clk = !clk;
always @(posedge clk)
VAR2... | mit |
Tao-J/nexys3MIPSSoC | gpu.v | 2,480 | module MODULE1(
input wire VAR30,
input wire VAR21,
input wire VAR17,
input wire VAR10,
input wire VAR12,
input wire [12:0] VAR42,
input wire [15:0] VAR3,
output wire [15:0] VAR43,
output wire [2:0] VAR37,
output wire [2:0] VAR33,
output wire [2:1] VAR41,
output wire VAR5,
output wire VAR22
);
reg [23:0] VAR18;
wire VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/muxb16to1/sky130_fd_sc_hdll__muxb16to1.behavioral.v | 2,046 | module MODULE1 (
VAR16,
VAR12,
VAR21
);
output VAR16;
input [15:0] VAR12;
input [15:0] VAR21;
supply1 VAR2;
supply0 VAR18;
supply1 VAR17 ;
supply0 VAR9 ;
bufif1 VAR5 (VAR16 , !VAR12[0], VAR21[0] );
bufif1 VAR23 (VAR16 , !VAR12[1], VAR21[1] );
bufif1 VAR8 (VAR16 , !VAR12[2], VAR21[2] );
bufif1 VAR4 (VAR16 , !VAR12[3], V... | apache-2.0 |
GLADICOS/AES128 | rtl/datapath.v | 14,917 | module MODULE1
(
output [31:0] VAR38,
output [31:0] VAR49,
output [31:0] VAR130,
output VAR24,
input [31:0] VAR72,
input [ 1:0] VAR85,
input [ 1:0] VAR149,
input [ 1:0] VAR94,
input [ 3:0] VAR86,
input [ 2:0] VAR134,
input [ 3:0] VAR97,
input [ 3:0] VAR83,
input [ 3:0] VAR60,
input [ 3:0] VAR137,
input [ 3:0] VAR40,
in... | lgpl-3.0 |
mammenx/synesthesia_moksha | wxp/dgn/syn/limbus/synthesis/submodules/limbus_cpu_jtag_debug_module_tck.v | 7,973 | module MODULE1 (
VAR13,
VAR34,
VAR1,
VAR23,
VAR19,
VAR18,
VAR33,
VAR27,
VAR35,
VAR4,
VAR31,
VAR9,
VAR10,
VAR32,
VAR14,
VAR39,
VAR40,
VAR22,
VAR6,
VAR29,
VAR2,
VAR37,
VAR30,
VAR24,
VAR8,
VAR5,
VAR16,
VAR17,
VAR28,
VAR26,
VAR25
)
;
output [ 1: 0] VAR16;
output VAR17;
output [ 37: 0] VAR28;
output VAR26;
output VAR25;
inp... | gpl-3.0 |
catompiler/fpgalibs | counter/counter.v | 1,367 | module MODULE1 #(parameter VAR2 = 1)
(input wire clk, input wire rst, input wire VAR9,
input wire VAR11, input wire [VAR2 - 1:0] VAR7,
input wire [VAR2 - 1:0] VAR10, input wire VAR1,
output wire [VAR2 - 1:0] out, output wire VAR8);
reg [VAR2 - 1:0] VAR5;
wire [VAR2:0] VAR6;
wire VAR3 = (VAR5 == VAR7) & VAR11;
wire VAR4... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/output_port_lookup/cam_router/src/unencoded_cam_lut_sm.v | 8,203 | module MODULE1
parameter VAR25 = 3,
parameter VAR34 = 16,
parameter VAR51 = VAR19(VAR34),
parameter VAR13 = 0, parameter VAR39 = {VAR25{1'b0}}, parameter VAR9 = {VAR41{1'b0}}, parameter VAR1 = {VAR41{1'b0}} )
( input VAR45,
input [VAR41-1:0] VAR52,
input [VAR41-1:0] VAR22,
output reg VAR3,
output reg VAR7,
output [VAR2... | mit |
google/skywater-pdk-libs-sky130_fd_io | cells/top_sio_macro/sky130_fd_io__top_sio_macro.behavioral.pp.v | 40,947 | module MODULE1 (
VAR32,
VAR65,
VAR52,
VAR10,
VAR22,
VAR9,
VAR4,
VAR61,
VAR41,
VAR55,
VAR28,
VAR8,
VAR14,
VAR16,
VAR15,
VAR51,
VAR23,
VAR59,
VAR39,
VAR37,
VAR34,
VAR40,
VAR7,
VAR58,
VAR5,
VAR18,
VAR54,
VAR26,
VAR43,
VAR70,
VAR30,
VAR53,
VAR49,
VAR20,
VAR63,
VAR69,
VAR74,
VAR47,
VAR72,
VAR24,
VAR13,
VAR50
);
wire VAR1;
w... | apache-2.0 |
yipenghuang0302/csee4840_14 | software/peripheral/synthesis/submodules/altera_pli_streaming.v | 2,260 | module MODULE1 (
clk,
VAR15,
VAR20,
VAR1,
VAR10,
VAR18,
VAR13,
VAR17,
VAR11
);
parameter VAR3 = 50000;
parameter VAR9 = 0;
input clk;
input VAR15;
output reg VAR20;
output reg [7 : 0] VAR1;
input VAR10;
input VAR18;
input [7 : 0] VAR13;
output reg VAR17;
output reg VAR11;
reg VAR16;
reg VAR2;
reg [7 : 0] VAR19;
always ... | mit |
cpulabs/mist1032sa | src/core/l1_data/l1_data_cache_hit_counter.v | 3,280 | module MODULE1(
input wire VAR6,
input wire VAR3,
input wire VAR9,
input wire VAR8,
output wire [6:0] VAR7
);
reg [99:0] VAR5;
always@(posedge VAR6 or negedge VAR3)begin
if(!VAR3)begin
VAR5 <= 100'h0;
end
else begin
if(VAR9)begin
VAR5 <= {VAR5[98:0], VAR8};
end
end
end
reg [3:0] VAR2[0:9]; reg [5:0] VAR1[0:1]; reg [6:0... | bsd-2-clause |
Elphel/x353 | compressor/color_proc353.v | 35,547 | module MODULE1 (clk, en, VAR172, VAR171, VAR37, VAR97, VAR134, VAR46, VAR58, VAR22, VAR121, VAR112, VAR107, VAR113, VAR67,
VAR131, VAR153, VAR66, VAR193, VAR105, VAR175, VAR150, VAR18, VAR62, do, VAR204, VAR24, VAR206, VAR183, VAR149, VAR4, VAR106, VAR76, VAR141, VAR195, VAR182, VAR194, VAR64 VAR38 VAR170
,VAR49
,VAR11... | gpl-3.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_xbar_0/ip_design_xbar_0_stub.v | 3,598 | module MODULE1(VAR13, VAR1, VAR20, VAR39,
VAR23, VAR5, VAR8, VAR16, VAR10, VAR6,
VAR29, VAR27, VAR14, VAR4, VAR15, VAR19,
VAR36, VAR11, VAR35, VAR18, VAR32, VAR9,
VAR7, VAR31, VAR22, VAR12, VAR25, VAR33,
VAR2, VAR38, VAR28, VAR26, VAR34, VAR40,
VAR24, VAR37, VAR3, VAR21, VAR30, VAR17)
;
input VAR13;
input VAR1;
input [... | mit |
kramble/FPGA-Litecoin-Miner | source/hashcore.v | 23,589 | module MODULE1 (VAR62, VAR93, VAR45, VAR61, VAR38, VAR129, VAR54, VAR2, VAR122, VAR96);
input VAR62;
input [255:0] VAR93;
input [255:0] VAR45;
input [127:0] VAR61;
input [31:0] VAR38;
input [3:0] VAR129; output [31:0] VAR54;
output [31:0] VAR2;
output VAR122; input VAR96;
reg VAR44 = 1'b1;
reg reset = 1'b1;
always @ (p... | gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_rd_cmd_fsm.v | 4,201 | module MODULE1 (
input wire clk ,
input wire reset ,
output wire VAR8 ,
input wire VAR3 ,
input wire [7:0] VAR17 ,
output wire VAR12 ,
input wire VAR16 ,
output wire VAR7 ,
input wire VAR9 ,
input wire VAR6 ,
output wire VAR1 ,
output wire VAR13
);
localparam VAR10 = 2'b00;
localparam VAR11 = 2'b01;
localparam VAR4 = 2... | gpl-3.0 |
finnball/igloo | projects/chip8/hdl/mem.v | 1,129 | module MODULE1(
input clk,
input VAR11,
input [VAR2 - 1 : 0] VAR3,
input [VAR10 - 1 : 0] VAR12,
input VAR7,
input [VAR2 - 1 : 0] VAR5,
output [VAR10 - 1 : 0] VAR4
);
parameter VAR2 = 8;
parameter VAR10 = 16;
localparam VAR14 = 1 << VAR2;
parameter VAR6 = 0;
parameter VAR8 = "";
parameter VAR13 = 80;
parameter VAR9 = ""... | gpl-3.0 |
drom/elastic | rtl/eb15_ctrl.v | 1,489 | module MODULE1 #(
parameter VAR11 = 5'b10100,
parameter VAR6 = 5'b11010,
parameter VAR13 = 5'b01000,
parameter VAR4 = 5'b11101,
parameter VAR9 = 5'b01001
) (
input VAR7,
output VAR8,
output VAR12,
input VAR3,
output VAR1, VAR14, sel,
input clk, VAR2
);
reg [4:0] state, VAR5;
always @(posedge clk or negedge VAR2)
if (~V... | mit |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x8_250/source/pcie_7x_v1_3_axi_basic_rx_null_gen.v | 15,913 | module MODULE1 # (
parameter VAR4 = 128, parameter VAR16 = 1,
parameter VAR7 = VAR4 / 8 ) (
input [VAR4-1:0] VAR3, input VAR9, input VAR6, input VAR24, input [21:0] VAR38,
output VAR20, output VAR26, output [VAR7-1:0] VAR15, output VAR25, output reg [4:0] VAR30,
input VAR36, input VAR10 );
localparam VAR13 = (VAR4 == 1... | lgpl-3.0 |
comododragon/SHA256_FPGA | Full/Verilog/sha256_stream.v | 2,414 | module MODULE1
(input clk,
input rst,
input [511:0] VAR11,
input VAR10,
input VAR3,
output VAR5,
output [255:0] VAR9,
output VAR2);
reg VAR13;
always @(posedge clk) begin
if (VAR3 & VAR5)
VAR13 <= VAR10;
if (rst) begin
VAR13 <= 1'b1;
end
end
VAR15 VAR4
(.clk (clk),
.VAR1 (~rst),
.VAR7(VAR3 & VAR13),
.VAR12(VAR3 & !VAR1... | mit |
lbl-cal/StanfordNoC | router/src/clib/c_prio_sel.v | 3,139 | module MODULE1
(VAR6, enable, select);
parameter VAR11 = 32;
parameter VAR4 = 16;
localparam VAR16 = VAR17(VAR4);
input [0:VAR11*VAR16-1] VAR6;
input [0:VAR11-1] enable;
output [0:VAR11-1] select;
wire [0:VAR11-1] select;
wire [0:VAR16*VAR11-1] VAR1;
VAR14
.VAR2(VAR11))
VAR15
(.VAR12(VAR6),
.VAR7(VAR1));
wire [0:(VAR16... | bsd-2-clause |
franmolinaca/papiGB | rtl/pGB.v | 6,672 | module MODULE1
(
input wire VAR92,
output wire [3:0] VAR94,
output wire [3:0] VAR8,
output wire [3:0] VAR12,
output wire VAR97,
output wire VAR37,
input wire [5:0] VAR4,
output wire VAR107,
output wire [15:0] VAR100,
output wire [15:0] VAR89,
input wire VAR59
);
wire [15:0] VAR123, VAR32;
wire [7:0] VAR14, VAR63;
wire ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and3/sky130_fd_sc_hdll__and3_2.v | 2,180 | module MODULE1 (
VAR2 ,
VAR5 ,
VAR7 ,
VAR8 ,
VAR10,
VAR9,
VAR1 ,
VAR3
);
output VAR2 ;
input VAR5 ;
input VAR7 ;
input VAR8 ;
input VAR10;
input VAR9;
input VAR1 ;
input VAR3 ;
VAR4 VAR6 (
.VAR2(VAR2),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR3(VAR3)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a31oi/sky130_fd_sc_lp__a31oi.behavioral.v | 1,544 | module MODULE1 (
VAR10 ,
VAR2,
VAR8,
VAR5,
VAR14
);
output VAR10 ;
input VAR2;
input VAR8;
input VAR5;
input VAR14;
supply1 VAR3;
supply0 VAR4;
supply1 VAR13 ;
supply0 VAR6 ;
wire VAR7 ;
wire VAR11;
and VAR9 (VAR7 , VAR5, VAR2, VAR8 );
nor VAR12 (VAR11, VAR14, VAR7 );
buf VAR1 (VAR10 , VAR11 );
endmodule | apache-2.0 |
MarcoVogt/basil | firmware/modules/utils/fx2_to_bus.v | 1,093 | module MODULE1
parameter VAR9 = 16 ) (
input wire [VAR9-1:0] VAR8,
input wire VAR5, input wire VAR6,
input wire VAR3, output wire [VAR9-1:0] VAR1,
output wire VAR2,
output wire VAR4,
output wire VAR7
);
assign VAR1 = VAR8 - 16'h4000;
assign VAR7 = ~VAR8[15] & VAR8[14];
reg VAR10;
always @ (posedge VAR3) begin
VAR10 <= ... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/diode/sky130_fd_sc_hd__diode.functional.v | 1,081 | module MODULE1 (
VAR1
);
input VAR1;
endmodule | apache-2.0 |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/imports/new/pwm.v | 1,105 | module MODULE1 (
input wire clk,
input wire reset,
input [31:0] VAR2,
input [9:0] VAR6,
output reg VAR4
);
wire [31:0] VAR3 = 100000000 / VAR2;
wire [31:0] VAR1 = VAR3 * VAR6 / 1024;
reg [31:0] VAR5;
always @(posedge clk, posedge reset) begin
if (reset) begin
VAR5 <= 0;
VAR4 <= 0;
end else if (VAR5 < VAR3) begin
VAR5 <... | gpl-3.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/mgt/rocketio_wrapper_tile_gt_frame_gen.v | 5,165 | module MODULE1 #
(
parameter VAR15 = 512
)
(
output reg [79:0] VAR11,
output reg [7:0] VAR13,
input wire VAR10,
input wire VAR14
);
wire VAR12;
wire [31:0] VAR7;
wire [63:0] VAR4;
wire [7:0] VAR3;
reg [8:0] VAR1;
reg [79:0] VAR5 [0:511];
reg [79:0] VAR2;
reg VAR8;
assign VAR7 = 32'h00000000;
assign VAR12 = 1'b0;
assign... | gpl-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/hrfp_1.0/hrfp_normalize.v | 8,112 | module MODULE1
(input wire clk,
input wire [VAR18:0] VAR14,
input wire [30:0] VAR2,
input wire [7:0] VAR12,
output reg [30:0] VAR1,
output reg [VAR18:0] VAR9);
reg [7:0] VAR10;
reg [2:0] VAR8;
reg [1:0] VAR16;
reg [1:0] VAR7;
reg VAR11;
wire VAR19 = (VAR2[30:25] == 6'b011111);
wire VAR4 = (VAR2[24:19] == 6'b111111);
wi... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o21bai/sky130_fd_sc_ms__o21bai_1.v | 2,329 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR6 ,
VAR9,
VAR8,
VAR10,
VAR4 ,
VAR7
);
output VAR3 ;
input VAR2 ;
input VAR6 ;
input VAR9;
input VAR8;
input VAR10;
input VAR4 ;
input VAR7 ;
VAR5 VAR1 (
.VAR3(VAR3),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR7(VAR7)
);
endmodule
module MODULE1 ... | apache-2.0 |
impedimentToProgress/ProbableCause | ddr2/cores/or1200/or1200_gmultp2_32x32.v | 4,258 | module MODULE1 ( VAR1, VAR4, VAR11, VAR13, VAR3 );
input [VAR5-1:0] VAR1;
input [VAR5-1:0] VAR4;
input VAR11;
input VAR13;
output [VAR2-1:0] VAR3;
reg [VAR2-1:0] VAR8;
reg [VAR2-1:0] VAR9;
integer VAR10;
integer VAR6;
always @(VAR1)
VAR10 = VAR1;
always @(VAR4)
VAR6 = VAR4;
always @(posedge VAR11 or VAR12 VAR13)
if (VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/xor3/sky130_fd_sc_hdll__xor3.functional.v | 1,318 | module MODULE1 (
VAR1,
VAR3,
VAR4,
VAR5
);
output VAR1;
input VAR3;
input VAR4;
input VAR5;
wire VAR2;
xor VAR7 (VAR2, VAR3, VAR4, VAR5 );
buf VAR6 (VAR1 , VAR2 );
endmodule | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_hdmi_16b_es_v1_00_a/hdl/verilog/cf_v2h.v | 11,519 | module MODULE1 (
VAR31,
VAR76,
VAR48,
VAR39,
VAR14,
VAR58,
VAR35,
VAR81,
VAR79,
VAR28,
VAR80,
VAR10,
VAR60,
VAR45,
VAR82,
VAR71,
VAR1,
VAR23,
VAR29,
VAR64,
VAR30,
VAR41,
VAR66);
input VAR31;
output [15:0] VAR76;
input VAR48;
output VAR39;
input VAR14;
input VAR58;
input [ 7:0] VAR35;
input [63:0] VAR81;
input VAR79;
ou... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ipshared/0001/hdl/led_controller_v1_0.v | 2,337 | module MODULE1 #
(
parameter integer VAR33 = 32,
parameter integer VAR43 = 4
)
(
output wire[7:0] VAR40,
input wire VAR18,
input wire VAR9,
input wire [VAR43-1 : 0] VAR17,
input wire [2 : 0] VAR42,
input wire VAR36,
output wire VAR10,
input wire [VAR33-1 : 0] VAR49,
input wire [(VAR33/8)-1 : 0] VAR25,
input wire VAR3,
... | mit |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_OA_SLVT_SS_210930.v | 242,236 | module MODULE1 (VAR6, VAR9, VAR13, VAR7, VAR2, VAR10);
output VAR6;
input VAR9, VAR13, VAR7, VAR2, VAR10;
wire VAR5, VAR4, VAR11;
wire VAR1, VAR3, VAR8;
wire VAR12;
not (VAR3, VAR10);
not (VAR1, VAR2);
not (VAR11, VAR7);
and (VAR8, VAR11, VAR1);
not (VAR4, VAR13);
not (VAR5, VAR9);
and (VAR12, VAR5, VAR4, VAR1);
or (VA... | bsd-3-clause |
praveendath92/DDR2_Interface_Xilinx_XUPV5 | source/ddr2_usr_rd.v | 11,769 | module MODULE1 #
(
parameter VAR6 = 8,
parameter VAR20 = 9,
parameter VAR81 = 144,
parameter VAR47 = 72,
parameter VAR33 = 0
)
(
input VAR55,
input VAR73,
input [(VAR20*VAR6)-1:0] VAR32,
input [(VAR20*VAR6)-1:0] VAR41,
input [VAR20-1:0] VAR59,
input [VAR20-1:0] VAR66,
output reg [1:0] VAR60,
output VAR71,
output reg [(... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/hold/gf180mcu_fd_sc_mcu9t5v0__hold.behavioral.pp.v | 1,083 | module MODULE1( VAR6, VAR3, VAR5 );
inout VAR3, VAR5;
inout VAR6;
VAR2 VAR1(.VAR6(VAR6),.VAR3(VAR3),.VAR5(VAR5));
VAR2 VAR4(.VAR6(VAR6),.VAR3(VAR3),.VAR5(VAR5)); | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_ad9361_v1_00_a/hdl/verilog/axi_ad9361_pnlb.v | 19,124 | module MODULE1 (
clk,
VAR15,
VAR21,
VAR43,
VAR19,
VAR36,
VAR12,
VAR52,
VAR46,
VAR4,
VAR23,
VAR60,
VAR3,
VAR78,
VAR11,
VAR70,
VAR34,
VAR55,
VAR27,
VAR41,
VAR57,
VAR80,
VAR45,
VAR2,
VAR24,
VAR82,
VAR73,
VAR29,
VAR76,
VAR35,
VAR13,
VAR74);
input clk;
input VAR15;
input [11:0] VAR21;
input [11:0] VAR43;
input [11:0] VAR19;... | mit |
ashwith/hdlroot | lib/clkgen/clk_div.v | 3,048 | module MODULE1(
input VAR2,
input VAR7,
input [3:0] VAR15,
output VAR9
);
parameter VAR8 = 19'b1010001011000010100;
parameter VAR1 = 19'b0101000101100001010;
parameter VAR5 = 19'b0010100010110000100;
parameter VAR17 = 19'b0001010001011000010;
parameter VAR13 = 19'b0000101000101100000;
parameter VAR16 = 19'b000001010001... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_lsbuf_lh_isowell_tap/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1.v | 2,464 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR5,
VAR6 ,
VAR7 ,
VAR4
);
output VAR3 ;
input VAR1 ;
input VAR5;
input VAR6 ;
input VAR7 ;
input VAR4 ;
VAR2 VAR8 (
.VAR3(VAR3),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR3,
VAR1
);
output VAR3;
input VAR1;
wire VAR5;
supply1 VAR6 ;... | apache-2.0 |
kkalavantavanich/SD2017 | spiCommMaster.v | 13,672 | /* VAR5 VAR48 VAR59 VAR120 VAR93 VAR71 VAR28.
* VAR104 VAR102 VAR46 use/VAR89/VAR66 in VAR1 VAR117 VAR85 this VAR60 VAR16 VAR72 VAR92 VAR80.
* VAR25: VAR30:
module MODULE1(
input VAR82, input enable, input reset, input VAR106, input VAR52,
output VAR94, output [3:0] VAR49, output [3:0] VAR54,
input VAR119, input [5:0] ... | mit |
CospanDesign/nysa-artemis-usb2-platform | artemis_usb2/slave/wb_artemis_pcie_platform/rtl/c/gtpa1_dual_wrapper.v | 16,236 | module MODULE1 #(
parameter VAR133 = 0, parameter VAR151 = 4,
parameter VAR104 = 4,
parameter VAR19 = 5,
parameter VAR122 = 5,
parameter VAR84 = 2,
parameter VAR54 = 2,
parameter VAR64 = 0 )
(
input [1:0] VAR125,
input [1:0] VAR44,
input [1:0] VAR113,
input [1:0] VAR74,
input VAR29,
input VAR154,
input VAR89,
input VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/muxb8to1/sky130_fd_sc_hdll__muxb8to1_4.v | 2,219 | module MODULE1 (
VAR9 ,
VAR7 ,
VAR5 ,
VAR1,
VAR2,
VAR4 ,
VAR8
);
output VAR9 ;
input [7:0] VAR7 ;
input [7:0] VAR5 ;
input VAR1;
input VAR2;
input VAR4 ;
input VAR8 ;
VAR6 VAR3 (
.VAR9(VAR9),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR9,
VAR7,
VAR5
);
o... | apache-2.0 |
CeesWolfs/ceespu | src/ceespu_compare.v | 1,048 | module MODULE1(
input [31:0] VAR1,
input [31:0] VAR2,
input [2:0] VAR5,
input VAR3,
output reg VAR4
);
always @* begin
case (VAR5)
0: VAR4 = (VAR1 == VAR2);
1: VAR4 = (VAR1 != VAR2);
2: VAR4 = (VAR1 > VAR2);
3: VAR4 = (VAR1 >= VAR2);
4: VAR4 = ((VAR1) > (VAR2));
5: VAR4 = ((VAR1) >= (VAR2));
6: VAR4 = VAR3;
7: VAR4 = 1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srsdfrtp/sky130_fd_sc_lp__srsdfrtp.functional.v | 2,661 | module MODULE1 (
VAR22 ,
VAR21 ,
VAR9 ,
VAR7 ,
VAR6 ,
VAR17,
VAR19
);
output VAR22 ;
input VAR21 ;
input VAR9 ;
input VAR7 ;
input VAR6 ;
input VAR17;
input VAR19;
supply1 VAR23;
supply1 VAR20 ;
supply0 VAR1 ;
supply1 VAR8 ;
supply0 VAR25 ;
wire VAR3 ;
wire VAR15 ;
wire VAR24 ;
wire VAR18;
not VAR10 (VAR3 , VAR17 );
VA... | apache-2.0 |
schelleg/pynq_tutorial | Pynq-Z1/vivado/pynq_tutorial/ip/arduino_io_switch_1.0/hdl/arduino_io_switch_v1_0_S_AXI.v | 22,772 | module MODULE1 #
(
parameter integer VAR109 = 32,
parameter integer VAR13 = 4
)
(
input [5:0] VAR82,
output [5:0] VAR119,
output [5:0] VAR105,
input [1:0] VAR85,
output [1:0] VAR39,
output [1:0] VAR48,
input [11:0] VAR124,
output [11:0] VAR25,
output [11:0] VAR120,
input VAR122,
output VAR66,
output VAR77,
input VAR9,
... | bsd-3-clause |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_fpga_nes/rtl/vram.v | 2,316 | module MODULE1(
input VAR14, input VAR11, input VAR8, input [10:0] VAR2, input [ 7:0] din, output [ 7:0] dout );
wire VAR7;
wire [7:0] VAR6;
VAR5 #(.VAR9(11),
.VAR10(8)) VAR1(
.clk(VAR14),
.VAR12(VAR7),
.VAR3(VAR2),
.VAR4(din),
.VAR13(VAR6)
);
assign VAR7 = (VAR11) ? ~VAR8 : 1'b0;
assign dout = (VAR11) ? VAR6 : 8'h00;
... | mit |
da-steve101/binary_connect_cifar | src/main/verilog/Queue_4096.v | 1,278 | module MODULE1
(
input VAR14,
input reset,
input [4095:0] VAR9,
input VAR5,
output VAR8,
output [4095:0] VAR11,
output VAR2,
input VAR7
);
wire VAR3;
wire VAR17;
wire VAR6;
wire VAR16;
wire [2047:0] VAR15;
wire [2047:0] VAR1;
wire [2047:0] VAR4;
wire [2047:0] VAR10;
assign VAR15 = VAR9[2047:0];
assign VAR1 = VAR9[4095:... | gpl-3.0 |
elegabriel/myzju | junior1/CA/pipeline3/code/alt_ctl.v | 1,681 | module MODULE1(VAR2,VAR1,VAR3
);
input [5:0] VAR2,VAR1;
output reg [4:0] VAR3;
always @*
begin
case(VAR2)
6'b000000 : begin case(VAR1) 6'b100000 : VAR3 = 0; 6'b100001 : VAR3 = 1; 6'b100010 : VAR3 = 2; 6'b100011 : VAR3 = 3; 6'b100100 : VAR3 = 4; 6'b100101 : VAR3 = 5; 6'b100110 : VAR3 = 6; 6'b100111 : VAR3 = 7; 6'b101010... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/buf/sky130_fd_sc_hs__buf_2.v | 1,866 | module MODULE2 (
VAR4 ,
VAR6 ,
VAR5,
VAR2
);
output VAR4 ;
input VAR6 ;
input VAR5;
input VAR2;
VAR3 VAR1 (
.VAR4(VAR4),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR4,
VAR6
);
output VAR4;
input VAR6;
supply1 VAR5;
supply0 VAR2;
VAR3 VAR1 (
.VAR4(VAR4),
.VAR6(VAR6)
);
endmodule | apache-2.0 |
stpr18/verilog-processor | alu.v | 4,482 | module MODULE2 (input [31:0] VAR12, VAR21, output [15:0] o1, o2, input VAR7, input [4:0] VAR16, output [15:0] VAR1, input en);
reg [15:0] flag;
wire [15:0] VAR3, VAR4;
wire VAR2, VAR17;
always @(VAR3) begin
flag <= VAR3;
end
always @(VAR4) begin
flag <= VAR4;
end
MODULE1 #(.VAR9(8), .VAR18(3)) VAR10(VAR12[15:0], VAR21[... | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2bb2a/sky130_fd_sc_lp__o2bb2a.pp.symbol.v | 1,383 | module MODULE1 (
input VAR5,
input VAR8,
input VAR1 ,
input VAR3 ,
output VAR6 ,
input VAR9 ,
input VAR7,
input VAR4,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o41a/sky130_fd_sc_hs__o41a.pp.blackbox.v | 1,347 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR8 ,
VAR7 ,
VAR6 ,
VAR5 ,
VAR1,
VAR3
);
output VAR2 ;
input VAR4 ;
input VAR8 ;
input VAR7 ;
input VAR6 ;
input VAR5 ;
input VAR1;
input VAR3;
endmodule | apache-2.0 |
maijohnson/comp3601_blue_15s2 | AudioController/tone_lut64.v | 3,081 | module MODULE1 (input [5:0] VAR14, output [13:0] VAR9);
parameter
VAR33= 14'd1000, VAR10 = 14'd11945,
VAR26 = 14'd11275,
VAR49 = 14'd10642,
VAR18 = 14'd10045,
VAR47 = 14'd9481,
VAR5 = 14'd8949,
VAR35 = 14'd8446,
VAR23 = 14'd7972,
VAR38 = 14'd7525,
VAR51 = 14'd7103,
VAR20 = 14'd6704,
VAR40 = 14'd6328,
VAR34 = 14'd5973,
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o21ai/sky130_fd_sc_ls__o21ai.behavioral.pp.v | 2,010 | module MODULE1 (
VAR14 ,
VAR9 ,
VAR2 ,
VAR5 ,
VAR10,
VAR6,
VAR7 ,
VAR3
);
output VAR14 ;
input VAR9 ;
input VAR2 ;
input VAR5 ;
input VAR10;
input VAR6;
input VAR7 ;
input VAR3 ;
wire VAR8 ;
wire VAR12 ;
wire VAR1;
or VAR13 (VAR8 , VAR2, VAR9 );
nand VAR15 (VAR12 , VAR5, VAR8 );
VAR16 VAR11 (VAR1, VAR12, VAR10, VAR6);
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o22ai/sky130_fd_sc_ms__o22ai.functional.pp.v | 2,159 | module MODULE1 (
VAR3 ,
VAR11 ,
VAR17 ,
VAR2 ,
VAR6 ,
VAR12,
VAR8,
VAR9 ,
VAR15
);
output VAR3 ;
input VAR11 ;
input VAR17 ;
input VAR2 ;
input VAR6 ;
input VAR12;
input VAR8;
input VAR9 ;
input VAR15 ;
wire VAR18 ;
wire VAR16 ;
wire VAR10 ;
wire VAR1;
nor VAR5 (VAR18 , VAR2, VAR6 );
nor VAR14 (VAR16 , VAR11, VAR17 );
... | apache-2.0 |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/system/synthesis/submodules/system_acl_iface_mm_interconnect_1.v | 17,534 | module MODULE1 (
input wire VAR34, input wire VAR45, input wire [29:0] VAR61, output wire VAR87, input wire [4:0] VAR76, input wire [31:0] VAR19, input wire VAR23, output wire [255:0] VAR56, output wire VAR78, input wire VAR100, input wire [255:0] VAR89, input wire VAR101, output wire [24:0] VAR24, output wire VAR67, o... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand3b/sky130_fd_sc_ms__nand3b.pp.blackbox.v | 1,320 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR1 ,
VAR6 ,
VAR7,
VAR8,
VAR5 ,
VAR3
);
output VAR4 ;
input VAR2 ;
input VAR1 ;
input VAR6 ;
input VAR7;
input VAR8;
input VAR5 ;
input VAR3 ;
endmodule | apache-2.0 |
qmn/riscv-invicta | hardware/src/datapath.v | 4,858 | module MODULE1 (
input clk,
input reset,
input VAR23,
output [31:0] VAR14,
output VAR9,
input VAR4,
output [31:0] VAR5,
output [31:0] VAR25,
output [3:0] VAR11,
output VAR2,
output VAR26,
input VAR12,
input [31:0] VAR17,
output [31:0] VAR8,
output VAR1,
output VAR16
);
reg [31:0] VAR7;
reg [31:0] VAR15;
wire [1:0] VAR6... | bsd-2-clause |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_2L_016bits.v | 1,917 | module MODULE2 (
clk,
VAR14, VAR32, VAR20, VAR26, VAR15, VAR13, VAR30, VAR19,
sum,
);
input clk;
input [VAR29+0-1:0] VAR14, VAR32, VAR20, VAR26, VAR15, VAR13, VAR30, VAR19;
output [VAR29 :0] sum;
reg [VAR29 :0] sum;
wire [VAR29+3-1:0] VAR9;
wire [VAR29+2-1:0] VAR27, VAR28;
wire [VAR29+1-1:0] VAR1, VAR7, VAR21, VAR8;
re... | mit |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/stream_encoder_ip_prj/stream_encoder_ip_prj.ip_user_files/ipstatic/axi_traffic_gen_v2_0_7/hdl/src/verilog/axi_traffic_gen_v2_0_slvram_v7.v | 8,328 | module MODULE1 #(
parameter VAR4 = "VAR12" ,
parameter VAR2 = 64 ,
parameter VAR17 = 1024 ,
parameter VAR8= 10 ,
parameter VAR11 = "VAR18"
) (
input VAR27 ,
input [VAR2/8-1:0] VAR29 ,
input [VAR8-1:0] VAR22 ,
input [VAR2-1:0] VAR9,
output [VAR2-1:0] VAR15,
input VAR26 ,
input [VAR2/8-1:0] VAR7 ,
input [VAR8-1:0] VAR24 ... | gpl-3.0 |
andrewandrepowell/axiplasma | hdl/projects/VC707/bd/mig_wrap/ip/mig_wrap_mig_7series_0_0/mig_wrap_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_write.v | 7,619 | module MODULE1 #
(
parameter integer VAR19 = 32,
parameter integer VAR27 = 32,
parameter integer VAR1 = 5,
parameter integer VAR16 = 3,
parameter VAR17 = 160'h0000f00C0000f0080000f0040000f000FFFFFFFF,
parameter VAR15 = 5'b11111
)
(
input wire clk ,
input wire reset ,
input wire VAR22 ,
input wire VAR13 ,
input wire [VA... | mit |
Jawanga/ece385lab8 | lab8_usb/usb_system/synthesis/submodules/usb_system_cpu_jtag_debug_module_sysclk.v | 7,058 | module MODULE1 (
clk,
VAR14,
VAR7,
VAR3,
VAR31,
VAR23,
VAR12,
VAR13,
VAR24,
VAR11,
VAR1,
VAR28,
VAR10,
VAR26,
VAR4,
VAR21,
VAR9,
VAR27,
VAR15
)
;
output [ 37: 0] VAR23;
output VAR12;
output VAR13;
output VAR24;
output VAR11;
output VAR1;
output VAR28;
output VAR10;
output VAR26;
output VAR4;
output VAR21;
output VAR9;
... | apache-2.0 |
asicguy/gplgpu | hdl/lucy_tc/de3d_tc_tag_val.v | 6,308 | module MODULE1
(
input VAR23,
input VAR7,
input VAR22,
input VAR27,
input VAR26,
input VAR29,
input VAR18,
input VAR13,
input VAR36,
input VAR1,
input VAR17,
input [4:0] VAR34,
input [4:0] VAR16,
input [4:0] VAR2,
input [4:0] VAR19,
input [4:0] VAR12,
input [4:0] VAR31,
input [4:0] VAR37,
input [4:0] VAR4,
output [1:0]... | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | source/hardware/nfc-substrate/tiger4_nfc_substrate-1.0.0/DCFIFO_64x16_DR.v | 2,758 | module MODULE1
(
input VAR16 ,
input VAR20 ,
input [63:0] VAR19 ,
input VAR15 ,
output VAR9 ,
input VAR6 ,
input VAR17 ,
output [63:0] VAR1 ,
input VAR12 ,
output VAR2
);
VAR13
VAR18
(
.VAR11 (VAR16 ),
.VAR5 (VAR20 ),
.din (VAR19 ),
.VAR7 (VAR15 ),
.VAR8 (VAR9 ),
.VAR14 (VAR6 ),
.VAR10 (VAR17 ),
.dout (VAR1 ),
.VAR4 (V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dlrtp/sky130_fd_sc_hvl__dlrtp.behavioral.v | 2,142 | module MODULE1 (
VAR19 ,
VAR1,
VAR14 ,
VAR11
);
output VAR19 ;
input VAR1;
input VAR14 ;
input VAR11 ;
supply1 VAR15;
supply0 VAR5;
supply1 VAR16 ;
supply0 VAR13 ;
wire VAR2 ;
reg VAR18 ;
wire VAR9 ;
wire VAR4 ;
wire VAR8 ;
wire VAR6 ;
wire VAR7;
wire VAR17 ;
not VAR12 (VAR2 , VAR7 );
VAR10 VAR3 (VAR17 , VAR4, VAR8, VA... | apache-2.0 |
Jawanga/ece385final | finalproject/synthesis/submodules/altera_dcfifo_synchronizer_bundle.v | 1,190 | module MODULE1(
clk,
VAR1,
din,
dout
);
parameter VAR7 = 1;
parameter VAR5 = 3;
input clk;
input VAR1;
input [VAR7-1:0] din;
output [VAR7-1:0] dout;
genvar VAR6;
generate
for (VAR6=0; VAR6<VAR7; VAR6=VAR6+1)
begin : sync
VAR2 #(.VAR3(VAR5))
VAR4 (
.clk(clk),
.VAR1(VAR1),
.din(din[VAR6]),
.dout(dout[VAR6])
);
end
endgen... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputiso1p/sky130_fd_sc_lp__inputiso1p.symbol.v | 1,385 | module MODULE1 (
input VAR1 ,
output VAR5 ,
input VAR2
);
supply1 VAR4;
supply0 VAR6;
supply1 VAR7 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x32/fifo_async_103x32_stub.v | 1,468 | module MODULE1(rst, VAR7, VAR4, din, VAR5, VAR6, dout, VAR3, VAR1, VAR2)
;
input rst;
input VAR7;
input VAR4;
input [102:0]din;
input VAR5;
input VAR6;
output [102:0]dout;
output VAR3;
output VAR1;
output VAR2;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/xnor2/sky130_fd_sc_hd__xnor2_2.v | 2,132 | module MODULE2 (
VAR1 ,
VAR8 ,
VAR4 ,
VAR2,
VAR3,
VAR7 ,
VAR6
);
output VAR1 ;
input VAR8 ;
input VAR4 ;
input VAR2;
input VAR3;
input VAR7 ;
input VAR6 ;
VAR9 VAR5 (
.VAR1(VAR1),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR1,
VAR8,
VAR4
);
output VAR1;
... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_16.behavioral.pp.v | 1,172 | module MODULE1( VAR4, VAR7, VAR2, VAR5 );
input VAR4;
inout VAR2, VAR5;
output VAR7;
VAR6 VAR1(.VAR4(VAR4),.VAR7(VAR7),.VAR2(VAR2),.VAR5(VAR5));
VAR6 VAR3(.VAR4(VAR4),.VAR7(VAR7),.VAR2(VAR2),.VAR5(VAR5)); | apache-2.0 |
silverfoxy/MIPS-Verilog | Single-Cycle/Core.v | 10,460 | module MODULE1(
input clk,
input VAR4,
input [2:0] VAR8,
output wire[7:0] VAR33
);
reg[31:0] VAR13;
wire[31:0] VAR19;
reg[5:0] VAR3;
wire[31:0] dout;
reg[3:0] wr;
reg[31:0] VAR29;
wire[31:0] VAR35;
wire[4:0] VAR21;
wire[31:0] VAR23;
wire[4:0] VAR20;
wire[31:0] VAR14;
reg VAR16;
wire[4:0] VAR34;
reg[3:0] VAR36;
reg VAR1... | mit |
jon-whit/4-bit_comp | verilog modules/fourbit_cpu.v | 2,086 | module MODULE1(clk, VAR13, VAR16, VAR10, VAR27, VAR8, enable, VAR15);
input clk, VAR13;
input [7:0] VAR16;
input [1:0] VAR10;
output [3:0] VAR27, enable;
output [6:0] VAR15;
output VAR8;
wire [3:0] VAR20, VAR25, VAR7, VAR3, VAR42, VAR39, VAR31, VAR28;
wire VAR23, VAR9, VAR38, VAR50, VAR26, VAR29, VAR33, VAR22;
wire [1:... | mit |
dhytxz/PolyPC | hardware/ip_repo/hapara_axis_id_dispatcher_1.0/hapara_axis_id_dispatcher_v1_0.v | 18,478 | module MODULE1 #
(
parameter integer VAR29 = 1,
parameter integer VAR59 = 32
)
(
input wire [VAR29-1: 0] VAR45,
input wire VAR68,
input wire VAR50,
output wire VAR23,
input wire [VAR59-1 : 0] VAR67,
input wire VAR2,
input wire VAR35,
input wire VAR71,
input wire VAR10,
output wire VAR54,
output wire [VAR59-1 : 0] VAR36... | gpl-2.0 |
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