repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
brandonpelfrey/ice40-nes | src/mod_vga_encoder.v | 4,963 | module MODULE1(
input VAR13,
input [7:0] VAR11,
input [7:0] VAR32,
input [7:0] VAR24,
output [7:0] VAR3,
output [7:0] VAR38,
output [7:0] VAR20,
output VAR14,
output VAR10,
output [9:0] VAR16,
output [9:0] VAR22,
output VAR27
);
reg VAR23, VAR4, VAR2;
reg VAR28, VAR39, VAR35;
reg VAR17 = 0;
reg [9:0] VAR29 = 0;
reg [9:... | mit |
jotego/jt51 | hdl/jt51_acc.v | 4,425 | module MODULE1(
input rst,
input clk,
input VAR37,
input VAR17,
input VAR10,
input VAR14,
input VAR49,
input VAR33,
input [1:0] VAR22,
input [2:0] VAR39,
input signed [13:0] VAR9,
input VAR30, input signed [11:0] VAR16,
output signed [15:0] VAR38,
output signed [15:0] VAR4,
output reg signed [15:0] VAR47, output reg si... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_inputiso0n/sky130_fd_sc_hd__lpflow_inputiso0n.behavioral.v | 1,423 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR8
);
output VAR2 ;
input VAR4 ;
input VAR8;
supply1 VAR6;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR5 ;
and VAR7 (VAR2 , VAR4, VAR8 );
endmodule | apache-2.0 |
SymbiFlow/yosys-f4pga-plugins | ql-qlf-plugin/qlf_k6n10f/brams_map.v | 18,832 | module \VAR53 (VAR93, VAR60, VAR104, VAR154, VAR11, VAR112, VAR13, VAR111, VAR106, VAR34, VAR1, VAR30, VAR102, VAR124);
parameter VAR84 = 10;
parameter VAR116 = 36;
parameter VAR120 = 4;
parameter VAR148 = 4;
parameter VAR50 = 1;
parameter VAR151 = 1;
parameter [36863:0] VAR77 = 36864'VAR39;
input VAR34;
input VAR1;
in... | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/example_design/rtl/phy/phy_dqs_iob.v | 13,365 | module MODULE1 #
(
parameter VAR81 = 100, parameter VAR23 = "VAR28", parameter VAR50 = 300.0, parameter VAR27 = "VAR125", parameter VAR72 = "VAR105", parameter VAR69 = "VAR85" )
(
input VAR29, input clk, input VAR39, input VAR100, input rst, input VAR22, input [4:0] VAR58, input [3:0] VAR78, input [3:0] VAR71, input [1... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/decap/sky130_fd_sc_lp__decap_8.v | 1,870 | module MODULE1 (
VAR2,
VAR6,
VAR4 ,
VAR5
);
input VAR2;
input VAR6;
input VAR4 ;
input VAR5 ;
VAR3 VAR1 (
.VAR2(VAR2),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR5(VAR5)
);
endmodule
module MODULE1 ();
supply1 VAR2;
supply0 VAR6;
supply1 VAR4 ;
supply0 VAR5 ;
VAR3 VAR1 ();
endmodule | apache-2.0 |
Jafet95/proy_3_grupo_2_sem_1_2016 | ROM_16x32.v | 31,239 | module MODULE1(
input wire clk,
input wire [11:0] addr,
output reg [15:0] VAR2
);
reg [11:0] VAR1;
always @(posedge clk)
VAR1 <= addr;
always @*
case (VAR1)
12'h000: VAR2 = 16'b0000000000000000; 12'h001: VAR2 = 16'b0000000000000000; 12'h002: VAR2 = 16'b0000000000000000; 12'h003: VAR2 = 16'b0000000000000000; 12'h004: VA... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_1.behavioral.v | 1,170 | module MODULE1( VAR6, VAR4, VAR5 );
input VAR6, VAR4;
output VAR5;
VAR3 VAR2(.VAR6(VAR6),.VAR4(VAR4),.VAR5(VAR5));
VAR3 VAR1(.VAR6(VAR6),.VAR4(VAR4),.VAR5(VAR5)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfsbp/sky130_fd_sc_ls__dfsbp.functional.v | 1,737 | module MODULE1 (
VAR7 ,
VAR3 ,
VAR8 ,
VAR13 ,
VAR9
);
output VAR7 ;
output VAR3 ;
input VAR8 ;
input VAR13 ;
input VAR9;
wire VAR10;
wire VAR1 ;
not VAR2 (VAR1 , VAR9 );
VAR6 VAR12 VAR11 (VAR10 , VAR13, VAR8, VAR1 );
buf VAR5 (VAR7 , VAR10 );
not VAR4 (VAR3 , VAR10 );
endmodule | apache-2.0 |
srjet/mips-verilog | cpu.v | 2,469 | module MODULE1 (
input clk,
output reg [31:0] addr,
output [31:0] VAR16,
output [1:0] VAR20,
output VAR12, VAR1, VAR2,
output [1:0] VAR7,
output [1:0] VAR24,
output VAR22, VAR10, VAR18,
output [4:0] VAR21,
output [31:0] VAR14,
output [31:0] VAR5, VAR15,
output [31:0] VAR9,
output [31:0] VAR19,
output [31:0] VAR4,
outpu... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a22o/sky130_fd_sc_hdll__a22o.functional.v | 1,519 | module MODULE1 (
VAR2 ,
VAR7,
VAR4,
VAR10,
VAR8
);
output VAR2 ;
input VAR7;
input VAR4;
input VAR10;
input VAR8;
wire VAR12 ;
wire VAR1 ;
wire VAR6;
and VAR11 (VAR12 , VAR10, VAR8 );
and VAR9 (VAR1 , VAR7, VAR4 );
or VAR3 (VAR6, VAR1, VAR12);
buf VAR5 (VAR2 , VAR6 );
endmodule | apache-2.0 |
gbraad/minimig-de1 | rtl/ctrl/qmem_bus.v | 9,870 | module MODULE1 #(
parameter VAR10 = 24, parameter VAR55 = 22, parameter VAR46 = 32, parameter VAR30 = VAR46/8 )(
input wire clk,
input wire rst,
output reg VAR75,
output reg VAR98,
output reg VAR136,
output reg VAR15,
input wire [VAR10-1:0] VAR139,
input wire VAR84,
input wire VAR110,
input wire [VAR30-1:0] VAR51,
inpu... | gpl-3.0 |
Mahdi89/eTeak | runtime/verilog/top.v | 1,792 | module MODULE1;
reg reset;
reg VAR2;
wire VAR1; | bsd-3-clause |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/channel.v | 21,253 | module MODULE1
parameter VAR19 = 128,
parameter VAR51 = 2, parameter VAR56 = VAR61((VAR19/32)+1)
)
(
input VAR40,
input VAR35,
input [2:0] VAR63, input [2:0] VAR4,
input [31:0] VAR62, input [VAR19-1:0] VAR53,
output VAR7, input VAR23, input VAR24, input VAR36,
output VAR22, input VAR54, input VAR58, input VAR10,
input ... | gpl-3.0 |
dhytxz/PolyPC | hardware/ip_repo/hapara_axis_id_generator_1.0/hdl/hapara_axis_id_generator_v1_0.v | 3,732 | module MODULE1 #
(
parameter integer VAR4 = 32,
parameter integer VAR12 = 4,
parameter integer VAR69 = 32
)
(
input wire VAR49,
input wire VAR29,
input wire [VAR12-1 : 0] VAR1,
input wire [2 : 0] VAR41,
input wire VAR23,
output wire VAR22,
input wire [VAR4-1 : 0] VAR9,
input wire [(VAR4/8)-1 : 0] VAR59,
input wire VAR5... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfsbp/sky130_fd_sc_lp__dfsbp.functional.v | 1,737 | module MODULE1 (
VAR1 ,
VAR11 ,
VAR12 ,
VAR10 ,
VAR13
);
output VAR1 ;
output VAR11 ;
input VAR12 ;
input VAR10 ;
input VAR13;
wire VAR7;
wire VAR8 ;
not VAR6 (VAR8 , VAR13 );
VAR2 VAR3 VAR5 (VAR7 , VAR10, VAR12, VAR8 );
buf VAR9 (VAR1 , VAR7 );
not VAR4 (VAR11 , VAR7 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_2.behavioral.v | 2,924 | module MODULE1( VAR12, VAR22, VAR5, VAR3 );
input VAR22, VAR12, VAR5;
output VAR3;
reg VAR6;
VAR21 VAR23(.VAR12(VAR12),.VAR22(VAR22),.VAR5(VAR5),.VAR3(VAR3),.VAR6(VAR6));
VAR21 VAR15(.VAR12(VAR12),.VAR22(VAR22),.VAR5(VAR5),.VAR3(VAR3),.VAR6(VAR6));
buf VAR2(VAR7,VAR5);
not VAR13(VAR9,VAR22);
and VAR10(VAR4,VAR5,VAR9);
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and4b/sky130_fd_sc_ls__and4b.blackbox.v | 1,320 | module MODULE1 (
VAR8 ,
VAR3,
VAR7 ,
VAR4 ,
VAR1
);
output VAR8 ;
input VAR3;
input VAR7 ;
input VAR4 ;
input VAR1 ;
supply1 VAR6;
supply0 VAR9;
supply1 VAR2 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux2i/sky130_fd_sc_lp__mux2i.symbol.v | 1,344 | module MODULE1 (
input VAR5,
input VAR3,
output VAR6 ,
input VAR7
);
supply1 VAR2;
supply0 VAR4;
supply1 VAR8 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
walkthetalk/fsref | ip/step_motor/src/include/single_step_motor.v | 15,539 | module MODULE1 #(
parameter integer VAR25 = 0,
parameter integer VAR19 = 16,
parameter integer VAR53 = 16,
parameter integer VAR71 = 9,
parameter integer VAR112 = 3,
parameter integer VAR74 = 0,
parameter integer VAR49 = 0,
parameter integer VAR4 = 4 )(
input wire clk,
input wire VAR101,
input wire VAR70,
input wire [V... | gpl-3.0 |
The7thPres/CFTP | CFTP_Sat/CFTP_Sat.srcs/sources_1/imports/Sources-On_Sat/Scrubber/Configuration_Scrubber.v | 4,504 | module MODULE1(
input VAR2,
output reg VAR11
);
wire VAR8;
wire VAR6;
wire VAR7;
wire [25:0] VAR1;
wire [4:0] VAR5;
wire[ 12:0] VAR15;
wire VAR10;
wire [6:0] VAR4;
wire [31:0] VAR13;
wire VAR12;
wire [31:0] VAR3;
wire VAR9;
reg [17:0] VAR14; | lgpl-3.0 |
mashanz/FinalProject | Code/fpga/spartan3a/top.v | 9,085 | module MODULE1( reset, VAR6, enable, VAR4, VAR9, VAR3, VAR5, VAR8, VAR7);
input reset, VAR6, enable;
output VAR7;
input [1:0]VAR4;
input [7:0]VAR3,VAR5;
input [7:0]VAR8;
output [7:0]VAR9;
reg [7:0]VAR9;
integer VAR1;
always@(VAR8,VAR3,VAR5)
begin
case(VAR8)
8'b00000000:
VAR9 = VAR3+VAR5;
8'b00000001: VAR9 = VAR3-VAR5;... | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/ipshared/ENCLab/NVMeHostController_v2_0_0/ba7abda2/src/pcie_tx_fifo.v | 10,955 | module MODULE1 # (
parameter VAR50 = 64,
parameter VAR80 = 128,
parameter VAR16 = 9
)
(
input VAR37,
input VAR36,
input VAR9,
input [9:4] VAR32,
input VAR17,
input [VAR50-1:0] VAR20,
output VAR33,
input VAR18,
input VAR6,
input VAR24,
output [VAR80-1:0] VAR7,
input VAR42,
input [9:4] VAR68,
output VAR46
);
localparam V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o311a/sky130_fd_sc_ls__o311a.behavioral.pp.v | 2,053 | module MODULE1 (
VAR7 ,
VAR3 ,
VAR4 ,
VAR9 ,
VAR14 ,
VAR15 ,
VAR6,
VAR10,
VAR2 ,
VAR1
);
output VAR7 ;
input VAR3 ;
input VAR4 ;
input VAR9 ;
input VAR14 ;
input VAR15 ;
input VAR6;
input VAR10;
input VAR2 ;
input VAR1 ;
wire VAR12 ;
wire VAR11 ;
wire VAR18;
or VAR8 (VAR12 , VAR4, VAR3, VAR9 );
and VAR13 (VAR11 , VAR12... | apache-2.0 |
INTI-CMNB/Lattuino_IP_Core | devices/ad_conv.v | 4,931 | module MODULE1
parameter VAR38=12,
parameter VAR27=1,
parameter VAR26=1)
(
input VAR32, input VAR43, input [0:0] VAR41, output [7:0] VAR16, input [7:0] VAR14, input VAR10, input VAR42, output VAR11, input VAR29, output VAR39, output VAR15, output VAR22, input VAR33);
localparam integer VAR17=VAR36(VAR38);
reg [VAR17-1:... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/diode/sky130_fd_sc_hvl__diode.symbol.v | 1,249 | module MODULE1 (
input VAR3
);
supply1 VAR1;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_pmod_tft/rtl/axi_pmod_tft.v | 18,504 | module MODULE1 #(
parameter VAR39 = 5,
parameter VAR114 = 32,
parameter VAR152 = (VAR114 / 8),
parameter VAR165 = 24,
parameter VAR166 = 1,
parameter VAR42 = 1,
parameter VAR57 = 480,
parameter VAR8 = 272,
parameter VAR46 = 10
)(
input clk,
input rst,
output VAR6,
output VAR27,
output VAR112,
output VAR139,
output VAR1... | mit |
hydai/Verilog-Practice | HardwareLab/Lab8/LCD_DISPLAY.v | 4,033 | module MODULE1(VAR4, VAR2, VAR14, VAR13, VAR1, VAR9, VAR8, VAR15, VAR5, VAR7, reset, clk);
input clk;
input reset;
input [255:0] VAR7;
output VAR4;
output VAR2;
output VAR14;
output VAR13;
output VAR1;
output VAR9;
output [7:0] VAR8;
output VAR5, VAR15;
reg [7:0] VAR8;
reg [1:0] VAR6;
reg [2:0] VAR16;
reg [2:0] VAR10;
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfrtn/sky130_fd_sc_ls__sdfrtn.blackbox.v | 1,440 | module MODULE1 (
VAR10 ,
VAR9 ,
VAR8 ,
VAR7 ,
VAR2 ,
VAR5
);
output VAR10 ;
input VAR9 ;
input VAR8 ;
input VAR7 ;
input VAR2 ;
input VAR5;
supply1 VAR6;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
GSejas/Karatsuba_FPU | ASIC_FLOW/Karatsuba_jorge/integracion_fisica/front_end/source/Sgf_Multiplication.v | 10,690 | module MODULE1
(
input wire clk,
input wire rst,
input wire VAR4,
input wire [VAR7-1:0] VAR9,
input wire [VAR7-1:0] VAR5,
output wire [2*VAR7-1:0] VAR25
);
wire [VAR7/2+1:0] VAR20;
wire [VAR7/2+1:0] VAR30;
wire [2*(VAR7/2)-1:0] VAR29;
wire [2*(VAR7/2+1)-1:0] VAR15;
wire [2*(VAR7/2+2)-1:0] VAR26;
wire [2*(VAR7/2+2)-1:0]... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/spu/rtl/spu_mactl.v | 55,523 | module MODULE1 (
VAR139,
VAR360,
VAR341,
VAR42,
VAR254,
VAR228,
VAR1,
VAR110,
VAR362,
VAR295,
VAR166,
VAR215,
VAR355,
VAR338,
VAR54,
VAR351,
VAR231,
VAR104,
VAR293,
VAR290,
VAR176,
VAR46,
VAR282,
VAR241,
VAR91,
VAR246,
VAR339,
VAR62,
VAR232,
VAR356,
VAR77,
VAR89,
VAR124,
VAR214,
VAR308,
VAR115,
VAR193,
VAR30,
VAR315,
V... | gpl-2.0 |
Daeno/DCLabExp3 | inout_port.v | 2,665 | module MODULE1(VAR7, clk, reset, VAR4, VAR13, VAR14, VAR12, VAR1, VAR15, VAR3);
input VAR7; input clk;
input reset;
input [23:0] VAR4;
output VAR13;
output VAR14;
output VAR12;
inout VAR1;
output VAR15;
output [5:0] VAR3;
reg VAR5; wire VAR16;
reg VAR2; wire VAR9;
wire VAR15;
reg VAR10;
reg VAR18;
reg VAR19;
assign VAR... | mit |
andrewandrepowell/kernel-on-chip | hdl/projects/Nexys4/bd/ip/bd_mig_7series_0_0/bd_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_0_arb_row_col.v | 18,940 | module MODULE1 #
(
parameter VAR93 = 100,
parameter VAR23 = "1T",
parameter VAR62 = 5,
parameter VAR12 = "VAR1",
parameter VAR86 = 4,
parameter VAR77 = 2,
parameter VAR32 = 37500, parameter VAR28 = 12500, parameter VAR71 = 6 )
(
VAR38, VAR82, VAR33, VAR42, VAR78, VAR100,
VAR34, VAR5, VAR57,
VAR41, VAR53, VAR22, VAR50, ... | mit |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/mig_7series_v1_8_rank_common.v | 20,487 | module MODULE1 #
(
parameter VAR13 = 100,
parameter VAR41 = "VAR20",
parameter VAR50 = 40,
parameter VAR32 = 4,
parameter VAR121 = 4,
parameter VAR47 = 2,
parameter VAR77 = 20,
parameter VAR36 = 2,
parameter VAR56 = 4,
parameter VAR95 = 39,
parameter VAR63 = 640000
)
(
VAR92, VAR28, VAR98, VAR72, VAR33,
VAR3, VAR5, VAR... | mit |
h-j-13/MyNote | Programming language/Verilog/sync_FIFO/Source_Code/FIFO_L1.v | 4,495 | module MODULE2(VAR10, rd, wr, rst, clk, VAR2, VAR12, VAR4);
input [7:0] VAR10;
input rd, wr, rst, clk;
output [7:0] VAR2;
output VAR12, VAR4;
wire [7:0] VAR2;
reg VAR3, VAR5;
reg [7:0] VAR14 [15:0];
reg [3:0] VAR9, VAR11;
assign VAR12 = VAR3;
assign VAR4 = VAR5;
assign VAR2 = VAR14[VAR9];
always@(posedge clk) begin
if(... | gpl-3.0 |
VitorCBSB/hw-verilog | C++/Verilog/circ_gen/memoria.v | 7,056 | module MODULE1 (
address,
VAR37,
VAR15,
VAR38,
VAR5);
input [15:0] address;
input VAR37;
input [7:0] VAR15;
input VAR38;
output [7:0] VAR5;
tri1 VAR37;
wire [7:0] VAR34;
wire [7:0] VAR5 = VAR34[7:0];
VAR47 VAR11 (
.VAR8 (address),
.VAR49 (VAR37),
.VAR33 (VAR15),
.VAR22 (VAR38),
.VAR55 (VAR34),
.VAR24 (1'b0),
.VAR35 (1'... | mit |
mshaklunov/mips_onemore | rtl/mips_div_stage.v | 1,334 | module MODULE1 #(
parameter VAR6=32,
parameter VAR8=4
)
(
input[VAR6-1:0] VAR2,
input[VAR6-1:0] VAR7,
input[VAR6-1:0] VAR11,
output[VAR6-1:0] VAR12,
output[VAR6-1:0] VAR1
);
wire[VAR6:0] VAR10[VAR6:0];
wire[(VAR6*2)-1:0] VAR4[VAR6:0];
wire[VAR6:0] VAR5;
assign VAR4[VAR6]={VAR11,VAR2[VAR6-1:0]};
assign VAR5={1'b0,VAR7[V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dff_p_pp_pg/sky130_fd_sc_hs__udp_dff_p_pp_pg.blackbox.v | 1,312 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR5 ,
VAR4,
VAR1
);
output VAR3 ;
input VAR2 ;
input VAR5 ;
input VAR4;
input VAR1;
endmodule | apache-2.0 |
twlostow/dsi-shield | hdl/rtl/dsi_core/dsi_packer.v | 6,329 | module MODULE1
(
VAR32,
VAR14);
parameter VAR27 = 4;
input [VAR27 * 8 - 1 : 0] VAR32;
output [VAR27 * 8 - 1 : 0] VAR14;
generate
genvar VAR7, VAR37;
for(VAR7=0;VAR7<8;VAR7=VAR7+1)
for(VAR37=0;VAR37<VAR27;VAR37=VAR37+1)
assign VAR14[8 * (VAR27-1-VAR37) + VAR7] = VAR32[8 * VAR37 + VAR7];
endgenerate
endmodule
module MODU... | lgpl-3.0 |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/submodules/niosII_system_sysid_qsys_0.v | 1,415 | module MODULE1 (
address,
VAR2,
VAR1,
VAR3
)
;
output [ 31: 0] VAR3;
input address;
input VAR2;
input VAR1;
wire [ 31: 0] VAR3;
assign VAR3 = address ? 1459998803 : 0;
endmodule | apache-2.0 |
shaform/ArkanoidOnVerilog | paddle_control.v | 1,095 | module MODULE1(
input VAR9, reset, enable, VAR6, VAR8,
input [4:0] VAR2,
input [5:0] VAR15,
input VAR14,
output reg [9:0] VAR3, VAR7
);
localparam VAR13 = 8;
localparam VAR10 = 320;
localparam VAR1 = 480;
localparam VAR12 = 160;
localparam VAR11 = 0;
reg [9:0] VAR5, VAR4;
always @
begin
if (enable && VAR6) begin
if (VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a2111o/sky130_fd_sc_hd__a2111o.pp.symbol.v | 1,400 | module MODULE1 (
input VAR8 ,
input VAR6 ,
input VAR4 ,
input VAR2 ,
input VAR5 ,
output VAR7 ,
input VAR1 ,
input VAR3,
input VAR10,
input VAR9
);
endmodule | apache-2.0 |
lvd2/ngs | fpga/obsolete/fpgaC_release/common/spi.v | 4,203 | module MODULE1(
VAR10,
VAR9, VAR8, VAR11, VAR3,
VAR4,
VAR7,
din, dout );
input VAR10;
output VAR9;
wire VAR9;
output VAR8;
input VAR11;
output reg VAR3;
input VAR4;
input VAR7;
input [7:0] din;
output reg [7:0] dout;
reg [4:0] counter;
wire VAR12;
reg [6:0] VAR1;
reg [7:0] VAR6;
wire VAR2;
reg VAR5;
begin
begin
begin
e... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a21o/sky130_fd_sc_hd__a21o.symbol.v | 1,341 | module MODULE1 (
input VAR6,
input VAR7,
input VAR8,
output VAR1
);
supply1 VAR4;
supply0 VAR5;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
CospanDesign/nysa-artemis-pcie-platform | artemis_pcie/slave/wb_artemis_pcie_platform/rtl/c/pcie_bram_top_s6.v | 5,421 | module MODULE1 #(
parameter VAR5 = 0,
parameter VAR25 = 31,
parameter VAR3 = 20,
parameter VAR29 = 1,
parameter VAR11 = 2,
parameter VAR19 = 1,
parameter VAR9 = 'h1FFF,
parameter VAR40 = 1,
parameter VAR23 = 2,
parameter VAR14 = 1
) (
input VAR15,
input VAR33,
input VAR6,
input [11:0] VAR41,
input [35:0] VAR35,
input V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a22o/sky130_fd_sc_ls__a22o.symbol.v | 1,363 | module MODULE1 (
input VAR6,
input VAR9,
input VAR1,
input VAR7,
output VAR2
);
supply1 VAR3;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
slongfield/StereoCensus | verilog/lib/ff.v | 1,062 | module MODULE1(clk, rst, VAR3, VAR1);
parameter VAR2 = 1;
input wire clk;
input wire rst;
input wire [VAR2-1:0] VAR3;
output reg [VAR2-1:0] VAR1;
always @(posedge clk) begin
VAR1 <= rst ? 0 : VAR3;
end
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/ha/sky130_fd_sc_ms__ha.blackbox.v | 1,264 | module MODULE1 (
VAR1,
VAR2 ,
VAR5 ,
VAR6
);
output VAR1;
output VAR2 ;
input VAR5 ;
input VAR6 ;
supply1 VAR8;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sedfxbp/sky130_fd_sc_hdll__sedfxbp.blackbox.v | 1,440 | module MODULE1 (
VAR6 ,
VAR10,
VAR8,
VAR5 ,
VAR2 ,
VAR11,
VAR1
);
output VAR6 ;
output VAR10;
input VAR8;
input VAR5 ;
input VAR2 ;
input VAR11;
input VAR1;
supply1 VAR7;
supply0 VAR4;
supply1 VAR9 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
jbelloncastro/amber_arm | hw/vlog/system/clocks_resets.v | 11,827 | module MODULE1 (
input VAR24,
input VAR14,
input VAR8,
input VAR90,
output VAR3,
output VAR79,
output VAR105
);
wire VAR5;
wire VAR49;
assign VAR3 = VAR49 || !VAR5;
localparam VAR45 = 25;
wire VAR103;
wire VAR53;
reg [VAR45-1:0] VAR39 ;
reg [VAR45-1:0] VAR101 ;
wire VAR30;
wire VAR62;
wire VAR6;
VAR104 # (
.VAR87 ( "VA... | lgpl-3.0 |
GLADICOS/SPACEWIRESYSTEMC | rtl/RTL_VB/rx_data_control_p.v | 3,784 | module MODULE1(
input VAR11,
input VAR22,
input VAR16,
input VAR23,
input VAR25,
input VAR24,
input VAR9,
input VAR27,
input VAR6,
input VAR21,
input VAR8,
input VAR18,
input VAR5,
input VAR2,
input VAR4,
input VAR13,
input VAR19,
input VAR7,
input VAR3,
input [5:0] VAR1,
output reg [8:0] VAR26,
output reg VAR20,
outpu... | gpl-3.0 |
omicronns/studies-sys-rek | lab3/serializer/src/deserializer.v | 2,090 | module MODULE1 #(
parameter VAR5 = 8
)(
input VAR8,
input rst,
input clk,
output [VAR5 - 1:0] VAR4,
output VAR7
);
localparam VAR6 = 2'b00;
localparam VAR2 = 2'b01;
localparam VAR10 = 2'b11;
localparam VAR11 = 2'b10;
reg [1:0] state = VAR6;
reg [7:0] VAR3 = 0;
reg [VAR5 - 1:0] VAR1 = 0;
reg VAR9 = 0;
assign VAR4 = VAR1... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_misc/bsg_mul_array.v | 2,674 | module MODULE1 #(parameter VAR29(VAR19), VAR7))
(
input VAR12
, input VAR31
, input VAR13
, input [VAR19-1:0] VAR15
, input [VAR19-1:0] VAR1
, output logic [(VAR19*2)-1:0] VAR4
);
logic [VAR19-1:0] VAR2 [VAR19-3:0];
logic [VAR19-1:0] VAR14 [VAR19-3:0];
logic [VAR19-1:0] VAR5 [VAR19-2:0];
logic VAR11 [VAR19-2:0];
logic ... | bsd-3-clause |
alexforencich/verilog-ethernet | rtl/arp_eth_tx.v | 13,405 | module MODULE1 #
(
parameter VAR9 = 8,
parameter VAR28 = (VAR9>8),
parameter VAR17 = (VAR9/8)
)
(
input wire clk,
input wire rst,
input wire VAR2,
output wire VAR31,
input wire [47:0] VAR19,
input wire [47:0] VAR30,
input wire [15:0] VAR13,
input wire [15:0] VAR1,
input wire [15:0] VAR23,
input wire [15:0] VAR20,
input... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_4.functional.v | 1,040 | module MODULE1( VAR2, VAR8, VAR1 );
input VAR1, VAR8;
output VAR2;
wire VAR5;
not VAR7( VAR5, VAR1 );
wire VAR3;
not VAR4( VAR3, VAR8 );
and VAR6( VAR2, VAR5, VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a221o/sky130_fd_sc_hs__a221o_2.v | 2,317 | module MODULE1 (
VAR2 ,
VAR10 ,
VAR5 ,
VAR4 ,
VAR1 ,
VAR3 ,
VAR6,
VAR8
);
output VAR2 ;
input VAR10 ;
input VAR5 ;
input VAR4 ;
input VAR1 ;
input VAR3 ;
input VAR6;
input VAR8;
VAR7 VAR9 (
.VAR2(VAR2),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR8(VAR8)
);
endmodule
module MODUL... | apache-2.0 |
kylemsguy/FPGA-Litecoin-Miner | experimental/CM1/uart.v | 1,570 | module MODULE1(
clk,
VAR3,
VAR8,
VAR11,
VAR2,
VAR20,
VAR18,
VAR1,
VAR21,
VAR4
);
parameter VAR19 = 25000000; parameter VAR13 = 9600; parameter VAR6 = 8;
input clk;
input VAR3;
output VAR8;
output [7:0] VAR11;
input [7:0] VAR2;
output VAR20;
input VAR18;
output VAR1;
output VAR21;
output VAR4;
VAR12 #(
.VAR19(VAR19),
.V... | gpl-3.0 |
asicguy/gplgpu | hdl/de_temp/der_smdisp_orig.v | 8,092 | module MODULE1
(
input VAR19,
input VAR51,
input VAR33,
input VAR37,
input VAR8,
input VAR44,
input VAR3,
input [3:0] VAR9,
input [3:0] VAR30,
input [3:0] VAR38,
input VAR4, input VAR7,
output reg VAR47,
output reg VAR5, output reg VAR32, output reg VAR20, output reg VAR14,
output reg VAR17,
output reg VAR46,
output re... | gpl-3.0 |
twlostow/dsi-shield | hdl/rtl/hpdmc/spartan6/hpdmc_iodelay.v | 1,971 | module MODULE1 #(
parameter VAR22 = 30,
parameter VAR4 = 2,
parameter VAR16 = "VAR5"
) (
input [VAR4-1:0] VAR11,
output [VAR4-1:0] VAR8,
input [VAR4-1:0] VAR20,
output [VAR4-1:0] VAR10,
input [VAR4-1:0] VAR7,
output [VAR4-1:0] VAR6,
input VAR19,
input VAR9,
input VAR15,
input VAR1,
input VAR14,
input VAR3,
input VAR17
... | lgpl-3.0 |
hydai/Verilog-Practice | HardwareLab/Upload/101062124_戴宏穎_Lab8/LCD_DISPLAY.v | 4,030 | module MODULE1(VAR4, VAR10, VAR8, VAR7, VAR9, VAR16, VAR5, VAR13, VAR6, VAR14, reset, clk);
input clk;
input reset;
input [255:0] VAR14;
output VAR4;
output VAR10;
output VAR8;
output VAR7;
output VAR9;
output VAR16;
output [7:0] VAR5;
output VAR6, VAR13;
reg [7:0] VAR5;
reg [1:0] VAR15;
reg [2:0] VAR11;
reg [2:0] VAR3... | mit |
miamiasheep/nctu-dlab-99 | hw/multiply.v | 1,322 | module MODULE3(
input VAR7, reset, VAR6,
input [7:0] VAR4, VAR11,
output [15:0] VAR17,
output VAR1
);
wire VAR14, VAR12, VAR2;
MODULE2 MODULE1(VAR7, reset, VAR6, VAR14, VAR1, VAR12, VAR2);
MODULE1 MODULE2(VAR7, reset, VAR4, VAR11, VAR12, VAR2, VAR17, VAR14);
endmodule
module MODULE2(
input VAR7, reset, VAR6, VAR14,
out... | gpl-3.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_1/syn/verilog/convolve_kernel.v | 23,476 | module MODULE1 (
VAR103,
VAR166,
VAR108,
VAR3,
VAR110,
VAR171,
VAR134,
VAR184,
VAR45,
VAR172,
VAR66,
VAR5,
VAR25,
VAR30,
VAR177,
VAR129,
VAR10,
VAR100,
VAR6,
VAR46,
VAR77,
VAR37,
VAR16,
VAR8,
VAR22,
VAR163,
VAR11,
VAR114,
VAR141,
VAR97,
VAR125,
VAR162,
VAR124,
VAR150,
VAR70,
VAR88,
VAR174,
VAR126,
VAR34,
VAR53,
interru... | mit |
zuloloxi/mecrisp-ice | hx1k/icestorm/j1a.v | 13,463 | module MODULE2(
output [1:0] VAR37,
input VAR52, VAR89, VAR100,
input [10:0] VAR158,
input VAR64, VAR107, VAR4,
input [10:0] VAR145,
input [1:0] VAR45, VAR124
);
parameter VAR51 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter VAR93 = 256'h0000000000000000000000000000000000000000000000... | bsd-3-clause |
queq/just-stuff | pov/TopFixed/Converter.v | 6,822 | module MODULE1(
input VAR1,
input VAR4,
input VAR9,
input [7:0] VAR14,
input [7:0] VAR12,
output reg [6:0] VAR2,
output reg VAR8
);
wire [9:0]VAR11;
reg VAR3;
reg VAR6;
reg VAR10;
reg VAR5;
reg VAR7;
reg VAR15;
reg VAR13;
assign VAR11 = {VAR13, VAR15^VAR13,VAR14};
always @begin
end
if (VAR14==8'h58)VAR10=1; else VAR10=... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o221a/sky130_fd_sc_ms__o221a.pp.blackbox.v | 1,428 | module MODULE1 (
VAR1 ,
VAR9 ,
VAR6 ,
VAR3 ,
VAR4 ,
VAR10 ,
VAR7,
VAR8,
VAR5 ,
VAR2
);
output VAR1 ;
input VAR9 ;
input VAR6 ;
input VAR3 ;
input VAR4 ;
input VAR10 ;
input VAR7;
input VAR8;
input VAR5 ;
input VAR2 ;
endmodule | apache-2.0 |
victor1994y/BipedRobot_byFPGA | Project_BipedRobot.srcs/sources_1/new/Sonic.v | 2,029 | module MODULE1(clk,VAR11,VAR2,VAR12,VAR1);
input clk,VAR11,VAR12;
output VAR2;
output wire [23:0] VAR1;
reg [23:0] VAR13;
reg [21:0] VAR5;
always @( posedge clk or negedge VAR11)
begin
if(!VAR11)
begin
VAR5<=0;
end
else if(VAR5==22'd3000000)
begin
VAR5<=0;
end
else
VAR5<=VAR5+1'b1;
end
assign VAR2=((VAR5>=22'd100)&(VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o311a/sky130_fd_sc_lp__o311a.behavioral.pp.v | 2,053 | module MODULE1 (
VAR10 ,
VAR9 ,
VAR6 ,
VAR4 ,
VAR12 ,
VAR17 ,
VAR2,
VAR5,
VAR3 ,
VAR8
);
output VAR10 ;
input VAR9 ;
input VAR6 ;
input VAR4 ;
input VAR12 ;
input VAR17 ;
input VAR2;
input VAR5;
input VAR3 ;
input VAR8 ;
wire VAR11 ;
wire VAR18 ;
wire VAR15;
or VAR13 (VAR11 , VAR6, VAR9, VAR4 );
and VAR16 (VAR18 , VAR1... | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie3_7x_0/source/pcie3_7x_0_pcie_bram_7vx.v | 10,483 | module MODULE1 #(
parameter VAR11 = "VAR84", parameter VAR75 = "VAR91", parameter VAR1 = "500 VAR16", parameter VAR9 = "16KB"
) (
input VAR93, input VAR36,
input [8:0] VAR28,
input [127:0] VAR25, input [15:0] VAR77, input VAR8, input VAR46,
output [127:0] VAR24, output [15:0] VAR40,
input [8:0] VAR21, input [8:0] VAR53... | gpl-3.0 |
azonenberg/yosys | techlibs/xilinx/brams_bb.v | 22,243 | module MODULE1 (
input VAR28,
input VAR184,
input VAR139,
input VAR111,
input VAR18,
input VAR58,
input VAR3,
input VAR72,
input VAR120,
input VAR33,
input [13:0] VAR143,
input [13:0] VAR151,
input [15:0] VAR42,
input [15:0] VAR83,
input [1:0] VAR105,
input [1:0] VAR137,
input [1:0] VAR148,
input [3:0] VAR5,
output [15... | isc |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/azpr_soc/io/gpio/rtl/gpio.v | 4,218 | module MODULE1 (
input wire clk, input wire reset,
input wire VAR24, input wire VAR22, input wire VAR1, input wire [VAR17] addr, input wire [VAR4] VAR26, output reg [VAR4] VAR9, output reg VAR11
);
wire [VAR2-1:0] VAR27; reg [VAR2-1:0] VAR5; reg [VAR2-1:0] VAR16; reg [VAR2-1:0] VAR13; integer VAR6;
assign VAR27 = VAR3;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o22ai/sky130_fd_sc_hdll__o22ai_1.v | 2,368 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR8 ,
VAR11 ,
VAR2 ,
VAR1,
VAR5,
VAR9 ,
VAR6
);
output VAR4 ;
input VAR3 ;
input VAR8 ;
input VAR11 ;
input VAR2 ;
input VAR1;
input VAR5;
input VAR9 ;
input VAR6 ;
VAR10 VAR7 (
.VAR4(VAR4),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR... | apache-2.0 |
CospanDesign/nysa-tx1-pcie-platform | tx1_pcie/slave/wb_tx1_pcie/rtl/host_interface/ingress_buffer_manager.v | 18,002 | module MODULE1 #(
parameter VAR9 = 12, parameter VAR54 = 9
)(
input clk,
input rst,
input VAR100, input [1:0] VAR60, output reg VAR83, output reg [1:0] VAR8,
input VAR65, input VAR20, input VAR72, output reg VAR86, output [7:0] VAR59, output [9:0] VAR101, output [11:0] VAR70, output reg VAR96, output VAR31,
input VAR32... | mit |
trevortheblack/NL16-BinaryCompression | build_tree.v | 2,507 | module MODULE1 (
input wire in,
output [15:0] reg out,
output [3:0] reg VAR9,
output reg VAR23,
output reg VAR1,
input wire VAR26,
input wire VAR5,
input wire VAR11
);
reg [15:0] VAR10;
reg [3:0] VAR13;
reg [4:0] VAR3;
reg [4:0] VAR7;
assign VAR23 = VAR21[0];
always @ (negedge VAR5 or posedge VAR26) begin
if (~VAR5) be... | apache-2.0 |
ffu/DSA-3.2.2 | usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v | 15,804 | module MODULE1
(output VAR215,
input VAR7,
input VAR39,
input VAR52,
inout VAR113,
input VAR238,
input VAR108,
output VAR104,
output VAR119,
input wire [11:0] VAR78,
input wire [11:0] VAR98,
input wire [11:0] VAR128,
input wire [11:0] VAR142,
output wire [13:0] VAR58,
output wire [13:0] VAR176,
output wire VAR227,
outp... | gpl-3.0 |
FAST-Switch/fast | projects/SDTS/example/hw-src/cdp/ddio_out.v | 4,664 | module MODULE1 (
VAR13,
VAR23,
VAR20,
VAR22,
VAR4);
input VAR13;
input [3:0] VAR23;
input [3:0] VAR20;
input VAR22;
output [3:0] VAR4;
tri0 VAR13;
wire [3:0] VAR5;
wire [3:0] VAR4 = VAR5[3:0];
VAR16 VAR6 (
.VAR22 (VAR22),
.VAR23 (VAR23),
.VAR13 (VAR13),
.VAR20 (VAR20),
.VAR4 (VAR5),
.VAR17 (1'b0),
.VAR1 (1'b1),
.VAR10 ... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_tiehi.v | 1,628 | if (VAR6 && (VAR4==VAR5)) \
begin: VAR13 \
VAR10 VAR11 (.VAR7); \
end
module MODULE1 #(parameter VAR9(VAR4)
, parameter VAR6=1
)
(output [VAR4-1:0] VAR7
);
begin :VAR15
assign VAR7 = { VAR4 {1'b1} };
end
VAR2 assert(VAR6==0) else ("## %VAR14 VAR12 VAR8 VAR1 VAR16 VAR3 VAR13");
end
endmodule | bsd-3-clause |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/vhls/set/solution/impl/verilog/set.v | 24,428 | module MODULE1 (
VAR238,
VAR78,
VAR27,
VAR116,
VAR177,
VAR155,
VAR352,
VAR299,
VAR125,
VAR300,
VAR154,
VAR74,
VAR165,
VAR319,
VAR321,
VAR317,
VAR73,
VAR189,
VAR127,
VAR17,
VAR330,
VAR344,
VAR29,
VAR54,
VAR59,
VAR287,
VAR38,
VAR247,
VAR146,
VAR239,
VAR120,
VAR18,
VAR11,
VAR235,
VAR341,
VAR206,
VAR211,
VAR15,
VAR176,
VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and2/sky130_fd_sc_hd__and2.pp.blackbox.v | 1,260 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR6 ,
VAR1,
VAR2,
VAR5 ,
VAR7
);
output VAR4 ;
input VAR3 ;
input VAR6 ;
input VAR1;
input VAR2;
input VAR5 ;
input VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand3b/sky130_fd_sc_hdll__nand3b.pp.blackbox.v | 1,328 | module MODULE1 (
VAR2 ,
VAR5 ,
VAR6 ,
VAR8 ,
VAR3,
VAR4,
VAR1 ,
VAR7
);
output VAR2 ;
input VAR5 ;
input VAR6 ;
input VAR8 ;
input VAR3;
input VAR4;
input VAR1 ;
input VAR7 ;
endmodule | apache-2.0 |
keith-epidev/VHDL-lib | top/lab_4/part_1/ip/mult_fft/mult_fft_stub.v | 1,162 | module MODULE1(VAR1, VAR2, VAR3, VAR4)
;
input VAR1;
input [27:0]VAR2;
input [27:0]VAR3;
output [55:0]VAR4;
endmodule | gpl-2.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig11/mig_7series_v1_1/user_design/rtl/controller/bank_cntrl.v | 25,718 | module MODULE1 #
(
parameter VAR47 = 100,
parameter VAR33 = "1T",
parameter VAR139 = 3,
parameter VAR112 = 2,
parameter VAR113 = "8",
parameter VAR126 = 12,
parameter VAR128 = 5,
parameter VAR71 = 8,
parameter VAR109 = "VAR19",
parameter VAR67 = "VAR48",
parameter VAR8 = 4,
parameter VAR84 = 4,
parameter VAR103 = 2,
pa... | lgpl-3.0 |
koyunbaba/ABLE_YU_training | filter/filter.srcs/sources_1/new/filter.v | 3,728 | module MODULE1
(
input clk,
input VAR15,
input [71:0] din,
input [53:0] VAR25,
input VAR7,
output [15:0] dout,
output VAR10
);
parameter VAR29 = 9; wire [8:0] VAR27 [8:0];
wire [5:0] VAR1 [8:0];
wire VAR28 [2:0]; genvar VAR5;
generate
for(VAR5 = 0; VAR5 < 9; VAR5 = VAR5 + 1) begin
assign VAR27[VAR5] = {1'b0, din[VAR5*8... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a21boi/sky130_fd_sc_ls__a21boi_4.v | 2,332 | module MODULE2 (
VAR8 ,
VAR4 ,
VAR5 ,
VAR7,
VAR10,
VAR2,
VAR3 ,
VAR9
);
output VAR8 ;
input VAR4 ;
input VAR5 ;
input VAR7;
input VAR10;
input VAR2;
input VAR3 ;
input VAR9 ;
VAR6 VAR1 (
.VAR8(VAR8),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR9(VAR9)
);
endmodule
module MODULE2 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o22a/sky130_fd_sc_lp__o22a.pp.blackbox.v | 1,385 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR7 ,
VAR8 ,
VAR1 ,
VAR4,
VAR3,
VAR9 ,
VAR6
);
output VAR5 ;
input VAR2 ;
input VAR7 ;
input VAR8 ;
input VAR1 ;
input VAR4;
input VAR3;
input VAR9 ;
input VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dff_nr_pp_pkg_sn/sky130_fd_sc_hs__udp_dff_nr_pp_pkg_sn.blackbox.v | 1,519 | module MODULE1 (
VAR8 ,
VAR2 ,
VAR3 ,
VAR5 ,
VAR9 ,
VAR6,
VAR4 ,
VAR1 ,
VAR7
);
output VAR8 ;
input VAR2 ;
input VAR3 ;
input VAR5 ;
input VAR9 ;
input VAR6;
input VAR4 ;
input VAR1 ;
input VAR7 ;
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/sync_gray.v | 4,180 | module MODULE1 (
input VAR1,
input VAR17,
input [VAR5-1:0] VAR4,
input VAR14,
input VAR15,
output [VAR5-1:0] VAR3
);
parameter VAR5 = 1;
parameter VAR9 = 1;
reg [VAR5-1:0] VAR7 = 'h0;
reg [VAR5-1:0] VAR2 = 'h0;
reg [VAR5-1:0] VAR13 = 'h0;
reg [VAR5-1:0] VAR11 = 'h0;
function [VAR5-1:0] VAR16;
input [VAR5-1:0] VAR10;
re... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfbbp/sky130_fd_sc_lp__sdfbbp.symbol.v | 1,572 | module MODULE1 (
input VAR3 ,
output VAR8 ,
output VAR1 ,
input VAR10,
input VAR5 ,
input VAR7 ,
input VAR6 ,
input VAR11
);
supply1 VAR2;
supply0 VAR4;
supply1 VAR12 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
lynxis/lpc_sniffer | ftdi.v | 1,537 | module MODULE1
(
input VAR8,
input [7:0] VAR9,
input VAR11,
input reset,
input VAR5,
output reg ready,
output reg [1:0] state,
output reg VAR2);
reg [9:0] VAR1;
reg VAR3;
reg [3:0] VAR4;
localparam VAR7 = 2'h0, VAR10 = 2'h1, VAR6 = 2'h2;
always @(negedge VAR8 or negedge reset) begin
if (~reset) begin
ready <= 0;
VAR3 <... | gpl-3.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_18.v | 15,469 | module MODULE3 (
clk,
reset,
VAR93,
VAR119,
VAR96,
VAR29,
VAR99
);
parameter VAR75 = 18;
parameter VAR11 = 18;
parameter VAR116 = 9;
localparam VAR52 = 24;
input clk;
input reset;
input VAR93;
input VAR119;
input [VAR75-1:0] VAR96; output VAR29;
output [VAR75-1:0] VAR99;
localparam VAR107 = 18; localparam VAR115 = 36; ... | mit |
benjaminfjones/fpga-tunes | src/analog_input.v | 1,117 | module MODULE1(
input clk,
input rst,
output [3:0] VAR6,
input VAR2,
input [9:0] VAR4,
input [3:0] VAR1,
output [9:0] out
);
assign VAR6 = 4'd0;
reg [9:0] VAR5, VAR3;
assign out = VAR3;
always @(*) begin
VAR5 = VAR3;
if (VAR2 && VAR1 == 4'd0) VAR5 = VAR4;
end
always @(posedge clk) begin
if (rst) begin
VAR3 <= 10'd0;
en... | gpl-3.0 |
patrick-samy/ace | lib/multiplexors.v | 1,434 | module MODULE2#(parameter VAR7 = 32)
(input VAR5,
input[VAR7 - 1:0] VAR9,
input[VAR7 - 1:0] VAR3,
output[VAR7 - 1:0] out);
wire VAR1;
wire[VAR7 - 1:0] VAR15;
wire[VAR7 - 1:0] VAR10;
genvar VAR13;
not (VAR1, VAR5);
generate
for (VAR13 = 0; VAR13 < 32; VAR13 = VAR13 + 1)
begin : VAR2
and (VAR15[VAR13], VAR1, VAR9[VAR13])... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlrbn/sky130_fd_sc_ls__dlrbn.functional.pp.v | 2,214 | module MODULE1 (
VAR11 ,
VAR10 ,
VAR13,
VAR15 ,
VAR6 ,
VAR2 ,
VAR7 ,
VAR14 ,
VAR18
);
output VAR11 ;
output VAR10 ;
input VAR13;
input VAR15 ;
input VAR6 ;
input VAR2 ;
input VAR7 ;
input VAR14 ;
input VAR18 ;
wire VAR16 ;
wire VAR3;
wire VAR17 ;
not VAR4 (VAR16 , VAR13 );
not VAR12 (VAR3, VAR6 );
VAR5 VAR19 VAR9 (VAR1... | apache-2.0 |
yipenghuang0302/csee4840_14 | software/peripheral/synthesis/ik_swift.v | 51,468 | module MODULE1 (
input wire VAR76, input wire VAR103, output wire [14:0] VAR147, output wire [2:0] VAR199, output wire VAR218, output wire VAR29, output wire VAR286, output wire VAR409, output wire VAR237, output wire VAR413, output wire VAR225, output wire VAR197, inout wire [31:0] VAR261, inout wire [3:0] VAR339, ino... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_axi_gpio_0_0/ip_design_axi_gpio_0_0_stub.v | 2,399 | module MODULE1(VAR10, VAR5, VAR14,
VAR6, VAR7, VAR2, VAR19, VAR17, VAR18,
VAR11, VAR12, VAR4, VAR21, VAR3, VAR20,
VAR8, VAR1, VAR16, VAR15, VAR22, VAR9, VAR13)
;
input VAR10;
input VAR5;
input [8:0]VAR14;
input VAR6;
output VAR7;
input [31:0]VAR2;
input [3:0]VAR19;
input VAR17;
output VAR18;
output [1:0]VAR11;
output V... | mit |
CospanDesign/sdio-device | rtl/cia/sdio_cia.v | 27,734 | module MODULE1 (
input clk, input rst,
output reg VAR54,
input VAR13,
input VAR91,
output reg VAR27,
input VAR33,
input VAR142,
input [17:0] VAR49,
input VAR114,
input [12:0] VAR7,
input [7:0] VAR31,
output [7:0] VAR131,
output reg VAR108,
output VAR9,
output [3:0] VAR17,
output [15:0] VAR127,
output VAR92,
output [3:0... | mit |
alexforencich/verilog-cam | rtl/cam_bram.v | 7,642 | module MODULE1 #(
parameter VAR36 = 64,
parameter VAR41 = 5,
parameter VAR4 = 9
)
(
input wire clk,
input wire rst,
input wire [VAR41-1:0] VAR21,
input wire [VAR36-1:0] VAR34,
input wire VAR38,
input wire VAR20,
output wire VAR19,
input wire [VAR36-1:0] VAR33,
output wire [2**VAR41-1:0] VAR28,
output wire [2**VAR41-1:0... | mit |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v | 1,147 | module MODULE1
VAR4 = 32,
VAR6 = 32,
VAR7 = 32,
VAR10 = 16, VAR1 = 32,
VAR3 = 8,
VAR8 = 1,
VAR9 = 8,
VAR2 = 1,
VAR5 = 1
) (
);
endmodule | gpl-3.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_101.v | 1,559 | module MODULE1 (
VAR7,
VAR3
);
input [31:0] VAR7;
output [31:0]
VAR3;
wire [31:0]
VAR11,
VAR8,
VAR13,
VAR12,
VAR10,
VAR1,
VAR14,
VAR2,
VAR9,
VAR6;
assign VAR11 = VAR7;
assign VAR1 = VAR11 << 4;
assign VAR14 = VAR13 - VAR1;
assign VAR8 = VAR11 << 8;
assign VAR13 = VAR11 + VAR8;
assign VAR6 = VAR9 << 2;
assign VAR9 = VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfrbp/sky130_fd_sc_ms__dfrbp.pp.symbol.v | 1,430 | module MODULE1 (
input VAR6 ,
output VAR3 ,
output VAR5 ,
input VAR8,
input VAR4 ,
input VAR2 ,
input VAR1 ,
input VAR9 ,
input VAR7
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/tapvgnd/sky130_fd_sc_hd__tapvgnd.behavioral.pp.v | 1,230 | module MODULE1 (
VAR3,
VAR4,
VAR1 ,
VAR2
);
input VAR3;
input VAR4;
input VAR1 ;
input VAR2 ;
endmodule | apache-2.0 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.