repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
Siliciumer/DOS-Mario-FPGA | sources/music.v | 18,909 | module MODULE1 (
input wire clk,
output reg VAR12
);
wire [7:0] VAR13;
wire [2:0] VAR9;
wire [3:0] VAR2;
reg [30:0] VAR6;
reg [8:0] VAR3;
reg [8:0] VAR11;
reg [7:0] VAR8;
MODULE3 MODULE2 (
.clk(clk),
.address(VAR6[30:22]),
.VAR2(VAR13)
);
MODULE2 MODULE1 (
.VAR5(VAR13[5:0]),
.VAR14(VAR9),
.VAR4(VAR2)
);
always @(posedg... | mit |
eda-globetrotter/PicenoDecoders | zhiyang_and_andrew/viterbidec.v | 5,176 | module MODULE1 (VAR22, VAR27, clk, reset);
output VAR22;
input [1:0] VAR27;
input clk;
input reset;
wire VAR22;
wire [1:0] VAR3,VAR7,VAR23,VAR13;
wire [1:0] VAR14,VAR29,VAR25,VAR4;
wire VAR21,VAR33,VAR6,VAR10;
wire [3:0] VAR18,VAR32,VAR17,VAR24;
wire [3:0] VAR30, VAR11, VAR12, VAR20;
VAR1 VAR26 (VAR27[0], VAR27[1],
VAR... | mit |
keith-epidev/VHDL-lib | top/lab_6/ip/clk_base/clk_base_stub.v | 1,130 | module MODULE1(VAR3, VAR2, VAR1)
;
input VAR3;
output VAR2;
output VAR1;
endmodule | gpl-2.0 |
olofk/oh | elink/hdl/etx_io.v | 8,016 | module MODULE1 (
VAR38, VAR2, VAR57, VAR69, VAR58,
VAR79, VAR11, VAR53, VAR59,
reset, VAR22, VAR30, VAR23, VAR73,
VAR4, VAR13, VAR49, VAR20, VAR72
);
parameter VAR25 = "VAR55";
parameter VAR32 = 104;
parameter VAR8 = 1; input reset; input VAR22; input VAR30;
output VAR38, VAR2; output VAR57, VAR69; output [7:0] VAR58, ... | gpl-3.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_xlconcat_0_1/synth/zqynq_lab_1_design_xlconcat_0_1.v | 4,597 | module MODULE1 (
VAR15,
VAR6,
dout
);
input wire [0 : 0] VAR15;
input wire [0 : 0] VAR6;
output wire [1 : 0] dout;
VAR4 #(
.VAR67(1),
.VAR1(1),
.VAR26(1),
.VAR3(1),
.VAR38(1),
.VAR24(1),
.VAR35(1),
.VAR17(1),
.VAR40(1),
.VAR28(1),
.VAR30(1),
.VAR11(1),
.VAR10(1),
.VAR36(1),
.VAR14(1),
.VAR43(1),
.VAR33(1),
.VAR51(1),
.... | mit |
Gifts/descrypt-ztex-bruteforcer | user_cores/des/src/crypt_shift_salt.v | 1,917 | module MODULE2(
input [31:0] VAR22,
input [31:0] VAR4,
input [67:0] VAR20,
output [67:0] VAR16,
input VAR6,
output [31:0] VAR13,
output [31:0] VAR14
);
wire [55:0] VAR3;
wire [47:0] VAR15;
VAR7 VAR19(VAR20[55:0], VAR3);
VAR8 VAR9({VAR20[67:56], VAR3}, VAR16, VAR6);
VAR10 VAR12(VAR3, VAR15);
VAR1 VAR18(
VAR22,
VAR4,
{VA... | gpl-3.0 |
ThotIP/async_fifo | src/vlog/sync_w2r.v | 1,269 | module MODULE1
parameter VAR2 = 4
)(
input wire VAR4,
input wire VAR3,
output reg [VAR2:0] VAR5,
input wire [VAR2:0] VAR6
);
reg [VAR2:0] VAR1;
always @(posedge VAR4 or negedge VAR3) begin
if (!VAR3)
{VAR5,VAR1} <= 0;
end
else
{VAR5,VAR1} <= {VAR1,VAR6};
end
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o41a/sky130_fd_sc_hd__o41a.pp.blackbox.v | 1,400 | module MODULE1 (
VAR9 ,
VAR6 ,
VAR5 ,
VAR8 ,
VAR3 ,
VAR10 ,
VAR7,
VAR1,
VAR2 ,
VAR4
);
output VAR9 ;
input VAR6 ;
input VAR5 ;
input VAR8 ;
input VAR3 ;
input VAR10 ;
input VAR7;
input VAR1;
input VAR2 ;
input VAR4 ;
endmodule | apache-2.0 |
bluespec/Flute | builds/AWSteria_Core_Flute_RV64_Linux/Verilog_RTL_PLATFORM_AWSF1/mkBranch_Predictor.v | 24,952 | module MODULE1(VAR43,
VAR136,
VAR42,
VAR63,
VAR52,
VAR13,
VAR112,
VAR121,
VAR56,
VAR29,
VAR105,
VAR31,
VAR115,
VAR14,
VAR59,
VAR57);
input VAR43;
input VAR136;
input VAR42;
output VAR63;
input [63 : 0] VAR52;
input VAR13;
output VAR112;
input VAR121;
input [31 : 0] VAR56;
output [63 : 0] VAR29;
input [63 : 0] VAR105;
i... | apache-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/vfabric_bypass_reg2.v | 1,878 | module MODULE1(VAR5, VAR2, VAR17,
VAR9,
VAR7, VAR6, VAR15,
VAR1, VAR10, VAR8,
VAR12, VAR13, VAR3,
VAR11, VAR16, VAR14);
parameter VAR4 = 32;
input VAR5;
input VAR2;
input [1:0] VAR17;
input [VAR4-1:0] VAR9;
input [VAR4-1:0] VAR7, VAR1;
input VAR6, VAR10;
output VAR15, VAR8;
output [VAR4-1:0] VAR12, VAR11;
output VAR13,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/diode/sky130_fd_sc_ls__diode.functional.pp.v | 1,200 | module MODULE1 (
VAR2,
VAR5 ,
VAR1 ,
VAR3 ,
VAR4
);
input VAR2;
input VAR5 ;
input VAR1 ;
input VAR3 ;
input VAR4 ;
endmodule | apache-2.0 |
merckhung/zet | cores/zet/rtl/zet_mux8_1.v | 1,258 | module MODULE1(sel, VAR4, VAR8, VAR1, VAR5, VAR6, VAR2, VAR3, VAR7, out);
input [2:0] sel;
input VAR4, VAR8, VAR1, VAR5, VAR6, VAR2, VAR3, VAR7;
output out;
reg out;
always @(sel or VAR4 or VAR8 or VAR1 or VAR5 or VAR6 or VAR2 or VAR3 or VAR7)
case(sel)
3'd0: out = VAR4;
3'd1: out = VAR8;
3'd2: out = VAR1;
3'd3: out = ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srsdfrtp/sky130_fd_sc_lp__srsdfrtp.pp.blackbox.v | 1,562 | module MODULE1 (
VAR8 ,
VAR2 ,
VAR10 ,
VAR6 ,
VAR3 ,
VAR7,
VAR1,
VAR12 ,
VAR9 ,
VAR4 ,
VAR5 ,
VAR11
);
output VAR8 ;
input VAR2 ;
input VAR10 ;
input VAR6 ;
input VAR3 ;
input VAR7;
input VAR1;
input VAR12 ;
input VAR9 ;
input VAR4 ;
input VAR5 ;
input VAR11 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_4.behavioral.v | 1,101 | module MODULE1( VAR3, VAR2 );
input VAR3;
output VAR2;
VAR5 VAR1(.VAR3(VAR3),.VAR2(VAR2));
VAR5 VAR4(.VAR3(VAR3),.VAR2(VAR2)); | apache-2.0 |
minosys-jp/FPGA | Zybo/vgagraph/vgagraph/HDL/vgagraph_ip_v1_0_M00_AXI.v | 22,448 | module MODULE1 #
(
parameter integer VAR63 = 28,
parameter integer VAR116 = 32'h40000000,
parameter integer VAR117 = 16,
parameter integer VAR64 = 1,
parameter integer VAR105 = 32,
parameter integer VAR3 = 32,
parameter integer VAR69 = 0,
parameter integer VAR129 = 0,
parameter integer VAR92 = 0,
parameter integer VAR8... | bsd-2-clause |
ShepardSiegel/ocpi | coregen/dram_k7_mig11/mig_7series_v1_1/user_design/rtl/phy/phy_dqs_found_cal.v | 10,743 | module MODULE1 #
(
parameter VAR35 = 100, parameter VAR39 = 2, parameter VAR14 = 5, parameter VAR28 = "0",
parameter VAR7 = 1, parameter VAR13 = 3, parameter VAR12 = 8, parameter VAR6 = 8 )
(
input clk,
input rst,
input VAR19,
input VAR9,
input VAR29,
input VAR21,
output reg VAR26,
output [5:0] VAR24,
output VAR22,
out... | lgpl-3.0 |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_3/hdl/verilog/feedforward_ddiv_64ns_64ns_64_31.v | 1,927 | module MODULE1
VAR1 = 7,
VAR12 = 31,
VAR22 = 64,
VAR9 = 64,
VAR16 = 64
)(
input wire clk,
input wire reset,
input wire VAR27,
input wire [VAR22-1:0] VAR10,
input wire [VAR9-1:0] VAR14,
output wire [VAR16-1:0] dout
);
wire VAR25;
wire VAR2;
wire VAR15;
wire [63:0] VAR7;
wire VAR20;
wire [63:0] VAR24;
wire VAR18;
wire [6... | gpl-3.0 |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/bg_low_1/bg_low_stub.v | 1,266 | module MODULE1(VAR4, VAR1, VAR2, VAR5, VAR3)
;
input VAR4;
input [0:0]VAR1;
input [10:0]VAR2;
input [11:0]VAR5;
output [11:0]VAR3;
endmodule | gpl-3.0 |
jobisoft/jTDC | modules/datalatch.v | 2,808 | module MODULE1 (VAR11,
VAR17,
VAR3,
VAR6);
parameter VAR10 = 32;
parameter VAR20 = 1;
parameter VAR18 = 0;
parameter VAR4 = 0;
parameter VAR5 = "VAR14";
input wire VAR11;
input wire VAR3;
input wire [VAR10-1:0] VAR17;
output reg [VAR10-1:0] VAR6;
wire VAR15;
wire VAR21;
wire [VAR10-1:0] VAR13;
generate
if (VAR20 == 1)
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/maj3/sky130_fd_sc_ms__maj3.pp.blackbox.v | 1,297 | module MODULE1 (
VAR7 ,
VAR8 ,
VAR5 ,
VAR3 ,
VAR2,
VAR6,
VAR4 ,
VAR1
);
output VAR7 ;
input VAR8 ;
input VAR5 ;
input VAR3 ;
input VAR2;
input VAR6;
input VAR4 ;
input VAR1 ;
endmodule | apache-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/phy_pd_top.v | 16,333 | module MODULE1 #
(
parameter VAR76 = 100, parameter VAR20 = 3, parameter VAR54 = 8, parameter VAR44 = 16, parameter VAR61 = "VAR34", parameter VAR16 = 8, parameter VAR65 = "VAR60", parameter VAR8 = "VAR50", parameter VAR53 = "VAR3" )
(
input clk,
input rst,
input VAR18, output VAR68, input VAR59, input VAR31, output re... | mit |
Jesus89/open-fpga-verilog-tutorial | tutorial/ICESTICK/T29-tristate/error2.v | 1,515 | module MODULE1 (
input wire clk, output wire [1:0] VAR3);
wire VAR2 = 1'b1;
reg VAR5;
always @(posedge clk)
VAR5 <= 1'b1;
reg VAR4;
always @(posedge clk)
VAR4 <= 1'b1;
assign VAR3[0] = (VAR2) ? VAR5 : 1'VAR1;
assign VAR3[1] = (VAR2) ? VAR4 : 1'VAR1;
endmodule | gpl-2.0 |
cmos3511/cmos_linux | python/pj/proj/rtl/LP/ChipTop.v | 4,153 | module MODULE1 (VAR2, VAR49, VAR4, VAR15, reset,
VAR16, VAR18, VAR43,
VAR54, VAR20, VAR9,
VAR25, VAR30, VAR46,
VAR13, VAR44, VAR50, VAR23
);
input [31:0] VAR4; output [31:0] VAR2; output VAR49; input VAR15; input reset;
input VAR16; input VAR18; input VAR43; input VAR13;
input VAR44;
wire VAR27;
input VAR54; input VAR2... | gpl-3.0 |
mossmann/unambiguous-encapsulation | code-search/verilog/icblbc/icblbc_top.v | 5,885 | module MODULE1 (
input wire VAR39,
input wire VAR44,
inout wire [7:0] VAR16,
input wire VAR21,
output wire VAR25,
input wire VAR69,
output wire [6:0] VAR29,
output wire [6:0] VAR18,
output wire [6:0] VAR10,
output wire [6:0] VAR42,
output wire [6:0] VAR72,
output wire [6:0] VAR60,
output wire [6:0] VAR45,
output wire [... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/einvp/sky130_fd_sc_hs__einvp.functional.v | 1,755 | module MODULE1 (
VAR9,
VAR4,
VAR8 ,
VAR1 ,
VAR2
);
input VAR9;
input VAR4;
output VAR8 ;
input VAR1 ;
input VAR2 ;
wire VAR3 ;
wire VAR6;
VAR11 VAR7 (VAR3 , VAR1, VAR9, VAR4 );
VAR11 VAR5 (VAR6, VAR2, VAR9, VAR4 );
notif1 VAR10 (VAR8 , VAR3, VAR6);
endmodule | apache-2.0 |
sharebrained/medusa | hdl/medusa_cape/gamma.v | 5,043 | module MODULE1 (
input [7:0] VAR2,
output reg [7:0] VAR1
);
always @(VAR2) begin
case(VAR2)
0: VAR1 = 0;
1: VAR1 = 1;
2: VAR1 = 1;
3: VAR1 = 1;
4: VAR1 = 1;
5: VAR1 = 1;
6: VAR1 = 1;
7: VAR1 = 1;
8: VAR1 = 1;
9: VAR1 = 1;
10: VAR1 = 1;
11: VAR1 = 1;
12: VAR1 = 1;
13: VAR1 = 1;
14: VAR1 = 1;
15: VAR1 = 1;
16: VAR1 = 1;
... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a32oi/sky130_fd_sc_ls__a32oi.blackbox.v | 1,434 | module MODULE1 (
VAR4 ,
VAR1,
VAR3,
VAR6,
VAR5,
VAR9
);
output VAR4 ;
input VAR1;
input VAR3;
input VAR6;
input VAR5;
input VAR9;
supply1 VAR7;
supply0 VAR8;
supply1 VAR10 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
The7thPres/CFTP | CFTP_Sat/CFTP_Sat.srcs/sources_1/imports/Sources-On_Sat/MIPS32/ALU.v | 13,592 | module MODULE1(
input VAR12,
input reset,
input VAR46,
input VAR69,
input [31:0] VAR41, VAR65,
input [4:0] VAR97,
input signed [4:0] VAR90,
output reg signed [31:0] VAR75,
output VAR19, output reg VAR104,
output VAR67, input [63:0] VAR40,
input VAR11,
output reg [63:0] VAR59,
output reg VAR117,
input VAR60,
input neg,
... | lgpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/db/GDA_St_N8_M4_P2_syn.v | 1,789 | module MODULE1 ( VAR36, VAR33, VAR6 );
input [7:0] VAR36;
input [7:0] VAR33;
output [8:0] VAR6;
wire VAR57, VAR54, VAR8, VAR19, VAR14, VAR10, VAR59, VAR3, VAR23, VAR48, VAR56, VAR18, VAR11, VAR31,
VAR12;
VAR66 VAR24 ( .VAR35(VAR33[4]), .VAR63(VAR36[4]), .VAR43(VAR57) );
VAR66 VAR13 ( .VAR35(VAR33[0]), .VAR63(VAR36[0]),... | gpl-3.0 |
queq/just-stuff | pov/TopFixed/control.v | 2,841 | module MODULE1 (clk, VAR10, VAR8, VAR4, VAR19, VAR3, new, reset, VAR17, VAR11, VAR1, VAR21, VAR14, VAR7, VAR18, VAR5, VAR12);
input clk;
input VAR11;
input VAR5;
input VAR8, VAR10;
input VAR4;
input VAR19;
input new;
input reset;
input VAR3;
output reg VAR17;
output reg VAR1;
output reg VAR21;
output reg VAR14;
output ... | mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/acl_fp_custom_reduced_normalize.v | 12,820 | module MODULE1(
VAR24, VAR14,
VAR2, VAR21, VAR49,
VAR47, VAR11, VAR28, VAR54,
enable,
VAR20, VAR4, VAR25);
parameter VAR37 = 1;
parameter VAR46 = 0;
parameter VAR43 = 1;
parameter VAR45 = 1;
parameter VAR18 = 1;
input VAR24, VAR14;
input VAR47, VAR11;
output VAR28, VAR54;
input enable;
input [27:0] VAR2;
input [8:0] VA... | mit |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/sync_bits.v | 3,327 | module MODULE1
(
input [VAR4-1:0] in,
input VAR5,
input VAR3,
output [VAR4-1:0] out
);
parameter VAR4 = 1;
parameter VAR1 = 1;
reg [VAR4-1:0] VAR6 = 'h0;
reg [VAR4-1:0] VAR2 = 'h0;
always @(posedge VAR3)
begin
if (VAR5 == 1'b0) begin
VAR6 <= 'b0;
VAR2 <= 'b0;
end else begin
VAR6 <= in;
VAR2 <= VAR6;
end
end
assign out ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_dff_pr_pp_pg_n/sky130_fd_sc_lp__udp_dff_pr_pp_pg_n.symbol.v | 1,478 | module MODULE1 (
input VAR3 ,
output VAR7 ,
input VAR6 ,
input VAR1 ,
input VAR2,
input VAR5 ,
input VAR4
);
endmodule | apache-2.0 |
sabertazimi/hust-lab | digitalLogic/design/clock_design/src/flow_led.v | 1,303 | module MODULE1
(
input VAR4,
input VAR3,
input VAR6,
output reg [(VAR2-1):0] VAR5
);
reg [31:0] VAR1;
reg VAR7; | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/bw_io_ddr_6sig_async.v | 10,347 | module MODULE1(VAR48 ,VAR73 ,VAR55 ,VAR74
,VAR45 ,VAR57 ,VAR15 ,VAR33 ,VAR76 ,VAR25 ,
VAR77 ,VAR75 ,VAR3 ,VAR58 ,VAR30 ,VAR35
,VAR36 ,VAR5 ,VAR42 ,VAR44 ,VAR38 ,
VAR53 ,VAR67 ,VAR9 ,VAR1 ,VAR4 ,VAR56 ,VAR32 ,VAR46 ,
VAR39 ,VAR60 ,VAR8 ,VAR64 ,
VAR79 ,VAR69 , VAR21, VAR78 ,VAR19 ,VAR54 ,
VAR34 ,VAR68 ,VAR2 ,VAR29 ,VAR43... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_inputiso0p/sky130_fd_sc_hd__lpflow_inputiso0p.behavioral.v | 1,495 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR8
);
output VAR3 ;
input VAR5 ;
input VAR8;
supply1 VAR1;
supply0 VAR7;
supply1 VAR4 ;
supply0 VAR10 ;
wire VAR2;
not VAR9 (VAR2, VAR8 );
and VAR6 (VAR3 , VAR5, VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and3b/sky130_fd_sc_hs__and3b.pp.symbol.v | 1,274 | module MODULE1 (
input VAR3 ,
input VAR6 ,
input VAR2 ,
output VAR4 ,
input VAR5,
input VAR1
);
endmodule | apache-2.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_light/spw_light/synthesis/submodules/spw_light_ctrl_in.v | 2,169 | module MODULE1 (
address,
VAR6,
clk,
VAR4,
VAR5,
VAR7,
VAR1,
VAR2
)
;
output [ 1: 0] VAR1;
output [ 31: 0] VAR2;
input [ 1: 0] address;
input VAR6;
input clk;
input VAR4;
input VAR5;
input [ 31: 0] VAR7;
wire VAR3;
reg [ 1: 0] VAR9;
wire [ 1: 0] VAR1;
wire [ 1: 0] VAR8;
wire [ 31: 0] VAR2;
assign VAR3 = 1;
assign VAR8 ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/tapvpwrvgnd/sky130_fd_sc_ms__tapvpwrvgnd_1.v | 1,928 | module MODULE2 (
VAR1,
VAR5,
VAR4 ,
VAR6
);
input VAR1;
input VAR5;
input VAR4 ;
input VAR6 ;
VAR2 VAR3 (
.VAR1(VAR1),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR6(VAR6)
);
endmodule
module MODULE2 ();
supply1 VAR1;
supply0 VAR5;
supply1 VAR4 ;
supply0 VAR6 ;
VAR2 VAR3 ();
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlrtp/sky130_fd_sc_ls__dlrtp.functional.v | 1,701 | module MODULE1 (
VAR1 ,
VAR10,
VAR5 ,
VAR8
);
output VAR1 ;
input VAR10;
input VAR5 ;
input VAR8 ;
wire VAR6;
wire VAR7;
not VAR9 (VAR6 , VAR10 );
VAR11 VAR2 VAR3 (VAR7 , VAR5, VAR8, VAR6 );
buf VAR4 (VAR1 , VAR7 );
endmodule | apache-2.0 |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/Clock/example_design/Clock_exdes.v | 5,991 | module MODULE1
parameter VAR31 = 100
)
( input VAR32,
input VAR20,
output [4:1] VAR30,
output [4:1] VAR22,
output VAR11
);
localparam VAR8 = 16;
localparam VAR10 = 4;
genvar VAR34;
wire VAR18 = !VAR11 || VAR20;
reg [VAR10:1] VAR24;
reg [VAR10:1] VAR6;
reg [VAR10:1] VAR12;
reg [VAR10:1] VAR28;
wire [VAR10:1] VAR13;
wire... | mit |
Kipsora/MIPS-CPU | source/machine/cpu/regfile/gpr-file.v | 2,308 | module MODULE1(
input wire VAR16,
input wire reset,
input wire VAR7,
input wire[VAR8] VAR15,
input wire[VAR10] VAR17,
input wire VAR1,
input wire[VAR8] VAR12,
output reg[VAR10] VAR2,
input wire VAR5,
input wire[VAR8] VAR4,
output reg[VAR10] VAR6
);
reg[VAR10] VAR14[0:VAR13 - 1];
always @ (posedge VAR16) begin
if (reset... | mit |
Apo45ty/ArquiCourseCPUVerilog | VerilogSource/ControlUnit+ALU/ARM_CU_ALU.v | 1,172 | module MODULE1;
wire VAR2, VAR23, VAR28, VAR4, VAR29, VAR8, VAR15, VAR22, VAR26, VAR32, VAR21, VAR5, VAR1;
wire [4:0] VAR17;
wire [3:0] VAR11;
reg [31:0] VAR27;
reg [3:0] VAR33;
reg VAR10 , VAR24 , VAR13 ;
VAR3 VAR25(VAR2, VAR23, VAR28, VAR4, VAR29, VAR8, VAR15, VAR22, VAR26, VAR32, VAR21, VAR5, VAR1,VAR17,VAR11,VAR10,... | apache-2.0 |
zuloloxi/mecrisp-ice | hx8k/icestorm/j1.v | 6,892 | module MODULE1(
input wire clk,
input wire VAR28,
output wire VAR40,
output wire VAR44,
output wire [15:0] VAR2,
output wire VAR34,
output wire [15:0] dout,
input wire [15:0] VAR15,
output wire [12:0] VAR12,
input wire [15:0] VAR18,
input wire VAR32
);
reg VAR7 = 0;
wire interrupt = VAR32 & VAR7;
reg [4:0] VAR47, VAR25... | bsd-3-clause |
Ricky-Gong/LegoCar | DE0-Nano/DE0Course/db/ip/NIOS_Sys/submodules/NIOS_Sys_pio_1.v | 1,897 | module MODULE1 (
address,
clk,
VAR2,
VAR5,
VAR6
)
;
output [ 31: 0] VAR6;
input [ 1: 0] address;
input clk;
input [ 3: 0] VAR2;
input VAR5;
wire VAR4;
wire [ 3: 0] VAR1;
wire [ 3: 0] VAR3;
reg [ 31: 0] VAR6;
assign VAR4 = 1;
assign VAR3 = {4 {(address == 0)}} & VAR1;
always @(posedge clk or negedge VAR5)
begin
if (VAR5... | gpl-2.0 |
SI-RISCV/e200_opensource | rtl/e203/core/e203_clkgate.v | 1,936 | module MODULE1 (
input VAR4,
input VAR2,
input VAR5,
output VAR3
);
reg VAR1;
always@(*)
if (!VAR4)
VAR1 = (VAR5 | VAR2);
assign VAR3 = VAR1 & VAR4;
endmodule | apache-2.0 |
MIPSfpga/schoolMIPS | src/sm_top.v | 1,961 | module MODULE1
(
input VAR16,
input VAR18,
input [ 3:0 ] VAR21,
input VAR24,
output clk,
input [ 4:0 ] VAR22,
output [31:0 ] VAR13
);
wire [ 3:0 ] VAR4;
wire enable;
wire [ 4:0 ] addr;
MODULE3 #(.VAR8(4)) VAR26(VAR16, VAR21, VAR4);
MODULE3 #(.VAR8(1)) VAR17(VAR16, VAR24, enable);
MODULE3 #(.VAR8(5)) VAR23(VAR16, VAR22,... | mit |
juan199/Lab_Digitales | exp4/Collaterals.v | 1,699 | module MODULE4 # (parameter VAR4=16)
(
input wire VAR14, VAR2,
input wire [VAR4-1:0] VAR8,
input wire VAR15,
output reg [VAR4-1:0] VAR16
);
always @(posedge VAR14 )
begin
if (VAR2)
VAR16 = VAR8;
end
else
begin
if (VAR15)
VAR16 = VAR16 + 1;
end
end
endmodule
module MODULE3 # ( parameter VAR4=8 )
(
input wire VAR14,
inpu... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp.blackbox.v | 1,381 | module MODULE1 (
VAR8 ,
VAR5,
VAR4,
VAR10 ,
VAR9,
VAR2
);
output VAR8 ;
output VAR5;
input VAR4;
input VAR10 ;
input VAR9;
input VAR2;
supply1 VAR3;
supply0 VAR6;
supply1 VAR1 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
tommythorn/yari | DE2-70/rtl/video.v | 7,732 | module MODULE1
(input VAR56
,input VAR69
,input [31:0] VAR14
,input VAR18
,output reg [29:0] VAR31
,output reg VAR12 = 0
,output reg [31:0] VAR58 = 0
,input VAR57
,output VAR19
,output reg [ 9:0] VAR22 = 0
,output reg [ 9:0] VAR55 = 0
,output reg [ 9:0] VAR43 = 0
,output reg VAR4 = 0
,output reg VAR66 = 0
,output reg V... | gpl-2.0 |
jrward/qdbreakout | rtl/vga.v | 1,347 | module MODULE1( input VAR2,
input VAR6,
output reg [9:0] VAR9,
output reg [9:0] VAR1,
output reg VAR5,
output reg VAR10 );
always @ (posedge VAR2 or negedge VAR6)
begin : VAR7
if (!VAR6) VAR9 <= 0;
end
else if (VAR9 <= 799) VAR9 <= VAR9 + 1'b1;
else VAR9 <= 0;
end
always @ (posedge VAR2 or negedge VAR6)
begin : VAR3
if... | gpl-2.0 |
olajep/oh | src/adi/hdl/library/common/ad_edge_detect.v | 2,655 | module MODULE1 #(
parameter VAR5 = 0) (
input clk,
input rst,
input in,
output reg out);
localparam VAR3 = 0;
localparam VAR4 = 1;
localparam VAR2 = 2;
reg VAR6 = 0;
reg VAR1 = 0;
always @(posedge clk) begin
if (rst == 1) begin
VAR6 <= 0;
VAR1 <= 0;
end else begin
VAR6 <= in;
VAR1 <= VAR6;
end
end
always @(posedge clk)... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a21bo/sky130_fd_sc_hd__a21bo.behavioral.pp.v | 2,043 | module MODULE1 (
VAR11 ,
VAR16 ,
VAR10 ,
VAR9,
VAR7,
VAR4,
VAR2 ,
VAR14
);
output VAR11 ;
input VAR16 ;
input VAR10 ;
input VAR9;
input VAR7;
input VAR4;
input VAR2 ;
input VAR14 ;
wire VAR15 ;
wire VAR1 ;
wire VAR8;
nand VAR13 (VAR15 , VAR10, VAR16 );
nand VAR6 (VAR1 , VAR9, VAR15 );
VAR3 VAR5 (VAR8, VAR1, VAR7, VAR4)... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/velocityControlHdl_Reset_Delay_block.v | 2,054 | module MODULE1
(
VAR3,
reset,
VAR11,
VAR8,
VAR4,
VAR6
);
input VAR3;
input reset;
input VAR11;
input VAR8;
input signed [31:0] VAR4; output signed [31:0] VAR6;
wire signed [31:0] VAR7; wire signed [31:0] VAR9; reg signed [31:0] VAR5; wire signed [31:0] VAR2; wire signed [31:0] VAR12;
assign VAR7 = 32'VAR10;
assign VAR9... | gpl-3.0 |
praveendath92/securePUF | source/ipcore_dependencies/emac_single_block.v | 13,529 | module MODULE1
(
VAR32,
VAR62,
VAR48,
VAR65,
VAR64,
VAR15,
VAR75,
VAR76,
VAR22,
VAR4,
VAR54,
VAR44,
VAR57,
VAR77,
VAR5,
VAR35,
VAR19,
VAR38,
VAR49,
VAR40,
VAR63,
VAR66,
VAR52,
VAR16,
VAR6,
VAR8,
VAR18,
VAR47,
VAR73,
VAR61,
VAR31,
VAR59 ,
VAR39
);
output VAR32;
input VAR62;
output [7:0] VAR48;
output VAR65;
output VAR64... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffnsnq/gf180mcu_fd_sc_mcu9t5v0__dffnsnq_4.behavioral.pp.v | 3,847 | module MODULE1( VAR15, VAR7, VAR2, VAR21, VAR13, VAR26 );
input VAR15, VAR7, VAR2;
inout VAR13, VAR26;
output VAR21;
reg VAR31;
VAR29 VAR1(.VAR15(VAR15),.VAR7(VAR7),.VAR2(VAR2),.VAR21(VAR21),.VAR13(VAR13),.VAR26(VAR26),.VAR31(VAR31));
VAR29 VAR23(.VAR15(VAR15),.VAR7(VAR7),.VAR2(VAR2),.VAR21(VAR21),.VAR13(VAR13),.VAR26(... | apache-2.0 |
rkrajnc/minimig-mist | rtl/minimig/denise_sprites.v | 9,241 | module MODULE1
(
input clk, input VAR10,
input reset, input VAR37,
input VAR24,
input VAR33,
input [8:1] VAR14, input [8:0] VAR25, input [15:0] VAR39, input [47:0] VAR4,
input VAR13, input [3:0] VAR31,
input [3:0] VAR42,
input [1:0] VAR2,
output [7:0] VAR41, output reg [7:0] VAR40 );
parameter VAR9 = 9'h140; parameter ... | gpl-3.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/Zynq_Book/hls/tut3A/matrix_mult_prj/solution2/syn/verilog/matrix_mult.v | 16,799 | module MODULE1 (
VAR40,
VAR8,
VAR60,
VAR62,
VAR12,
VAR83,
VAR91,
VAR20,
VAR68,
VAR32,
VAR15,
VAR63,
VAR72,
VAR37,
VAR30,
VAR33,
VAR29
);
parameter VAR5 = 8'd1;
parameter VAR2 = 8'd2;
parameter VAR64 = 8'd4;
parameter VAR47 = 8'd8;
parameter VAR41 = 8'd16;
parameter VAR79 = 8'd32;
parameter VAR88 = 8'd64;
parameter VAR1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfxbp/sky130_fd_sc_hs__dfxbp.behavioral.pp.v | 1,849 | module MODULE1 (
VAR2,
VAR13,
VAR15 ,
VAR6 ,
VAR14 ,
VAR10
);
input VAR2;
input VAR13;
output VAR15 ;
output VAR6 ;
input VAR14 ;
input VAR10 ;
wire VAR7 ;
reg VAR4 ;
wire VAR3 ;
wire VAR11;
wire VAR12 ;
VAR1 VAR5 (VAR7 , VAR3, VAR11, VAR4, VAR2, VAR13);
assign VAR12 = ( VAR2 === 1'b1 );
buf VAR8 (VAR15 , VAR7 );
not V... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/hold/gf180mcu_fd_sc_mcu7t5v0__hold.behavioral.pp.v | 1,083 | module MODULE1( VAR4, VAR5, VAR6 );
inout VAR5, VAR6;
inout VAR4;
VAR3 VAR2(.VAR4(VAR4),.VAR5(VAR5),.VAR6(VAR6));
VAR3 VAR1(.VAR4(VAR4),.VAR5(VAR5),.VAR6(VAR6)); | apache-2.0 |
zeldin/logic16_bitstream | src/logic_top.v | 3,072 | module MODULE1(
input VAR30,
input VAR37,
output VAR72,
output VAR13,
input VAR50,
input VAR69,
input VAR40,
output [7:0] VAR26,
output [7:0] VAR51,
output VAR36,
input VAR29,
input [15:0] VAR81
);
wire VAR22, VAR8, VAR52; wire VAR83, VAR60, VAR64;
wire VAR82; wire [15:0] VAR3;
VAR47 VAR20(.VAR5(VAR30), .VAR61(VAR60));... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and3b/sky130_fd_sc_hdll__and3b.behavioral.v | 1,485 | module MODULE1 (
VAR7 ,
VAR4,
VAR10 ,
VAR13
);
output VAR7 ;
input VAR4;
input VAR10 ;
input VAR13 ;
supply1 VAR8;
supply0 VAR11;
supply1 VAR9 ;
supply0 VAR3 ;
wire VAR1 ;
wire VAR2;
not VAR5 (VAR1 , VAR4 );
and VAR6 (VAR2, VAR13, VAR1, VAR10 );
buf VAR12 (VAR7 , VAR2 );
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_min/rtl/jbi_min_wrtrk_ptag_sum.v | 19,489 | module MODULE2(
VAR23,
VAR104
);
input [127:64] VAR104;
output [5:0] VAR23;
wire [5:0] VAR23;
wire VAR111;
wire VAR28;
wire VAR118;
wire VAR126;
wire VAR148;
wire VAR152;
wire VAR123;
wire VAR22;
wire VAR128;
wire VAR45;
wire VAR16;
wire VAR124;
wire VAR97;
wire VAR127;
wire VAR47;
wire VAR55;
wire VAR4;
wire VAR138;
w... | gpl-2.0 |
GustavoOS/ARMAria | src/ControlUnit/control.v | 2,053 | module MODULE1
parameter VAR7 = 32,
parameter VAR33 = 7,
parameter VAR6 = 16,
parameter VAR42 = 4,
parameter VAR21 = 12,
parameter VAR8 = 4
)(
input [VAR6 - 1 : 0] VAR27,
input VAR15, VAR35, VAR32,
input VAR13, VAR5, VAR26,
input VAR50, VAR45, reset, VAR9,
input VAR11,
input [1:0] VAR16,
output [(VAR21 - 1) : 0] VAR52,... | mit |
racerxdl/LVDS-7-to-1-Serializer | src/lvds_clockgen.v | 1,554 | module MODULE1(
input clk,
output VAR40,
output VAR38,
output VAR47,
output VAR2,
output VAR18
);
wire VAR42;
wire VAR33;
wire VAR20;
VAR7 #(.VAR1 ("15.625"),
.VAR23 ("0"),
.VAR14 (7),
.VAR36 (2))
VAR32 (
.VAR31 (clk),
.VAR21 (VAR20),
.VAR17 (1'b0),
.VAR13 (VAR33),
.VAR4 (VAR40),
.VAR44 (VAR38),
.VAR35 (),
.VAR45 (),
.... | mit |
pseudoincorrect/FPGA_MCU_wifi | FPGA/src/common/spi_master_32b.v | 6,974 | module MODULE1(VAR10, clk, VAR18, VAR5, VAR19, VAR2,
din, VAR12, VAR21, dout, VAR23, VAR16);
parameter VAR6 = 4'd0;
parameter VAR15 = 4'd1;
parameter VAR14 = 4'd2;
input VAR10, clk, VAR18, VAR5;
input [31:0] VAR19; input [1:0] VAR2; input din;
output reg VAR12;
output reg VAR21;
output reg dout;
output reg VAR23;
outpu... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dlyd/gf180mcu_fd_sc_mcu9t5v0__dlyd_4.behavioral.v | 1,098 | module MODULE1( VAR5, VAR3 );
input VAR5;
output VAR3;
VAR2 VAR1(.VAR5(VAR5),.VAR3(VAR3));
VAR2 VAR4(.VAR5(VAR5),.VAR3(VAR3)); | apache-2.0 |
ayushmaanbhav/cpu32bit | control.v | 1,199 | module MODULE1(input [5:0] VAR7,output VAR9,output VAR5,output VAR2,output VAR4,output VAR3,output VAR6,output VAR1,output VAR8);
reg VAR9,VAR5,VAR2,VAR1;
reg VAR8,VAR4,VAR3,VAR6;
always @ ( VAR7 )
begin
if(VAR7[5:0] == 6'b000000)
begin
VAR9 = 1'b0;
VAR5 = 1'b0;
VAR2 = 1'b0;
VAR4 = 1'b0;
VAR3 = 1'b1;
VAR6 = 1'b1;
VAR1 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/einvp/sky130_fd_sc_ms__einvp_4.v | 2,130 | module MODULE1 (
VAR9 ,
VAR2 ,
VAR4 ,
VAR3,
VAR6,
VAR1 ,
VAR5
);
output VAR9 ;
input VAR2 ;
input VAR4 ;
input VAR3;
input VAR6;
input VAR1 ;
input VAR5 ;
VAR8 VAR7 (
.VAR9(VAR9),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR9 ,
VAR2 ,
VAR4
);
output VAR9... | apache-2.0 |
Jawanga/ece385lab8 | lab8_usb/usb_system/synthesis/submodules/usb_system_cpu_jtag_debug_module_tck.v | 8,351 | module MODULE1 (
VAR5,
VAR20,
VAR30,
VAR36,
VAR38,
VAR37,
VAR7,
VAR21,
VAR13,
VAR39,
VAR24,
VAR4,
VAR1,
VAR40,
VAR29,
VAR19,
VAR27,
VAR12,
VAR14,
VAR11,
VAR33,
VAR31,
VAR18,
VAR10,
VAR26,
VAR34,
VAR23,
VAR28,
VAR22,
VAR2,
VAR17
)
;
output [ 1: 0] VAR23;
output VAR28;
output [ 37: 0] VAR22;
output VAR2;
output VAR17;
in... | apache-2.0 |
olgirard/openmsp430 | fpga/altera_de0_nano_soc/rtl/verilog/opengfx430/ogfx_reg.v | 69,127 | module MODULE1 (
VAR134,
VAR329, VAR307, VAR105,
VAR86, VAR83, VAR117, VAR384, VAR302, VAR298, VAR191, VAR331, VAR366, VAR312, VAR110, VAR362, VAR95,
VAR66, VAR275, VAR125, VAR85, VAR164, VAR143, VAR269,
VAR65,
VAR277,
VAR121, VAR216, VAR123, VAR108, VAR26,
VAR135, VAR72, VAR156, VAR213, VAR1
VAR250, VAR326, VAR129, VA... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o41ai/sky130_fd_sc_hs__o41ai.behavioral.v | 1,953 | module MODULE1 (
VAR3 ,
VAR16 ,
VAR5 ,
VAR14 ,
VAR11 ,
VAR10 ,
VAR7,
VAR2
);
output VAR3 ;
input VAR16 ;
input VAR5 ;
input VAR14 ;
input VAR11 ;
input VAR10 ;
input VAR7;
input VAR2;
wire VAR11 VAR9 ;
wire VAR6 ;
wire VAR12;
or VAR4 (VAR9 , VAR11, VAR14, VAR5, VAR16 );
nand VAR1 (VAR6 , VAR10, VAR9 );
VAR13 VAR8 (VAR1... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_12.behavioral.v | 1,113 | module MODULE1( VAR5, VAR1 );
input VAR5;
output VAR1;
VAR2 VAR4(.VAR5(VAR5),.VAR1(VAR1));
VAR2 VAR3(.VAR5(VAR5),.VAR1(VAR1)); | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/icgtn/gf180mcu_fd_sc_mcu9t5v0__icgtn_2.functional.pp.v | 1,081 | module MODULE1( VAR6, VAR7, VAR10, VAR4, VAR2, VAR3, VAR8 );
input VAR10, VAR7, VAR6, VAR2, VAR3, VAR8;
output VAR4;
or VAR5( VAR14, VAR7, VAR6 );
VAR9( VAR11, 1'b0, 1'b0, VAR10, VAR14, VAR8 );
wire VAR12;
not VAR1( VAR12, VAR11 );
or VAR13( VAR4, VAR10, VAR12 );
endmodule | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/ad_intp2_4.v | 4,283 | module MODULE1 (
clk,
VAR16,
VAR22,
VAR9,
VAR11,
VAR1);
input clk;
input [15:0] VAR16;
output [15:0] VAR22;
output [15:0] VAR9;
output [15:0] VAR11;
output [15:0] VAR1;
reg [15:0] VAR7 = 'd0;
reg [15:0] VAR21 = 'd0;
reg [15:0] VAR3 = 'd0;
reg [15:0] VAR10 = 'd0;
reg [15:0] VAR15 = 'd0;
reg [15:0] VAR14 = 'd0;
reg [15:0... | mit |
cpulabs/mist1032sa | src/core/execute/execute_load_store.v | 9,318 | module MODULE1(
input wire [4:0] VAR11,
input wire VAR10, input wire [31:0] VAR15,
input wire [31:0] VAR13,
input wire VAR19,
input wire [31:0] VAR7,
input wire [31:0] VAR33,
input wire [31:0] VAR6,
output wire VAR14,
output wire [31:0] VAR31,
output wire [31:0] VAR8,
output wire VAR16,
output wire [31:0] VAR28,
output... | bsd-2-clause |
fabianz66/cursos-tec | taller-digital/Lab1/sietesegmentos/siete_segmentos_principal.v | 1,658 | module MODULE1(
input wire VAR5,
input wire VAR12,
input wire VAR19,
input wire VAR10,
input wire VAR13,
input wire VAR18,
input wire VAR16,
input wire VAR4,
output VAR7,
output VAR9,
output VAR14,
output VAR2,
output VAR15,
output VAR11,
output VAR8,
output VAR17,
output VAR1,
output VAR3,
output VAR6
);
assign VAR17 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/einvp/sky130_fd_sc_hs__einvp.pp.symbol.v | 1,296 | module MODULE1 (
input VAR5 ,
output VAR3 ,
input VAR1 ,
input VAR2,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfbbp/sky130_fd_sc_ms__sdfbbp.behavioral.v | 3,323 | module MODULE1 (
VAR5 ,
VAR8 ,
VAR30 ,
VAR33 ,
VAR20 ,
VAR17 ,
VAR24 ,
VAR37
);
output VAR5 ;
output VAR8 ;
input VAR30 ;
input VAR33 ;
input VAR20 ;
input VAR17 ;
input VAR24 ;
input VAR37;
supply1 VAR29;
supply0 VAR25;
supply1 VAR2 ;
supply0 VAR6 ;
wire VAR4 ;
wire VAR34 ;
wire VAR21 ;
reg VAR22 ;
wire VAR13 ;
wire V... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/addf/gf180mcu_fd_sc_mcu9t5v0__addf_2.behavioral.pp.v | 3,162 | module MODULE1( VAR6, VAR9, VAR10, VAR4, VAR7, VAR1, VAR2 );
input VAR9, VAR4, VAR10;
inout VAR1, VAR2;
output VAR7, VAR6;
VAR3 VAR5(.VAR6(VAR6),.VAR9(VAR9),.VAR10(VAR10),.VAR4(VAR4),.VAR7(VAR7),.VAR1(VAR1),.VAR2(VAR2));
VAR3 VAR8(.VAR6(VAR6),.VAR9(VAR9),.VAR10(VAR10),.VAR4(VAR4),.VAR7(VAR7),.VAR1(VAR1),.VAR2(VAR2)); | apache-2.0 |
SymbiFlow/yosys-f4pga-plugins | ql-qlf-plugin/pp3/brams_map.v | 32,401 | module \VAR71 (
VAR108,
VAR136,
VAR140,
VAR103,
VAR45,
VAR164,
VAR60,
VAR88
);
parameter VAR107 = 9;
parameter VAR49 = 36;
parameter VAR15 = 4;
parameter VAR131 = 1;
parameter VAR95 = 1;
parameter [16383:0] VAR28 = 16384'VAR98;
input VAR108;
input VAR136;
input [VAR107-1:0] VAR140;
output [VAR49-1:0] VAR103;
input VAR4... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfxtp/sky130_fd_sc_hd__sdfxtp.functional.pp.v | 1,947 | module MODULE1 (
VAR16 ,
VAR11 ,
VAR2 ,
VAR4 ,
VAR5 ,
VAR12,
VAR1,
VAR14 ,
VAR3
);
output VAR16 ;
input VAR11 ;
input VAR2 ;
input VAR4 ;
input VAR5 ;
input VAR12;
input VAR1;
input VAR14 ;
input VAR3 ;
wire VAR10 ;
wire VAR7;
VAR6 VAR13 (VAR7, VAR2, VAR4, VAR5 );
VAR8 VAR17 VAR9 (VAR10 , VAR7, VAR11, , VAR12, VAR1);
b... | apache-2.0 |
eclay42/cs220-galois-aig-rewriting | adder16.v | 1,606 | module MODULE1 (VAR23,
VAR18,VAR39,VAR9,VAR45,VAR16,VAR3,VAR17,VAR40,VAR31,VAR60,VAR50,VAR38,VAR27,VAR28,VAR20,VAR24,
VAR2,VAR43,VAR19,VAR49,VAR46,VAR52,VAR34,VAR10,VAR56,VAR15,VAR1,VAR58,VAR53,VAR13,VAR25,VAR30,
b0,b1,VAR47,VAR59,VAR36,VAR11,VAR22,VAR12,VAR21,VAR5,b10,b11,VAR55,VAR7,VAR4,VAR44);
input VAR2,VAR43,VAR19... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50.pp.symbol.v | 1,356 | module MODULE1 (
input VAR6 ,
output VAR4 ,
input VAR1 ,
input VAR5,
input VAR3,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a211o/sky130_fd_sc_ms__a211o.functional.pp.v | 2,032 | module MODULE1 (
VAR16 ,
VAR10 ,
VAR13 ,
VAR9 ,
VAR17 ,
VAR14,
VAR11,
VAR15 ,
VAR12
);
output VAR16 ;
input VAR10 ;
input VAR13 ;
input VAR9 ;
input VAR17 ;
input VAR14;
input VAR11;
input VAR15 ;
input VAR12 ;
wire VAR8 ;
wire VAR4 ;
wire VAR3;
and VAR5 (VAR8 , VAR10, VAR13 );
or VAR2 (VAR4 , VAR8, VAR17, VAR9 );
VAR6... | apache-2.0 |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/Kintex7_160T_experimental/fpgaminer_top.v | 5,652 | module MODULE1 (
input VAR13,
input VAR11,
input VAR2,
output VAR7
);
wire VAR4;
wire VAR3;
VAR9 VAR8 (
.VAR10 (VAR13),
.VAR1 (VAR11),
.VAR12 (VAR4),
.VAR6 (VAR3)
);
reg VAR5 = 1'b0;
assign VAR4 = VAR5;
assign VAR3 = VAR5;
begin
begin
begin
begin
begin
end
begin | gpl-3.0 |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/wasca/synthesis/submodules/wasca_spi_sync.v | 1,839 | module MODULE1 (
address,
clk,
VAR2,
VAR3,
VAR6
)
;
output [ 31: 0] VAR6;
input [ 1: 0] address;
input clk;
input VAR2;
input VAR3;
wire VAR1;
wire VAR5;
wire VAR4;
reg [ 31: 0] VAR6;
assign VAR1 = 1;
assign VAR4 = {1 {(address == 0)}} & VAR5;
always @(posedge clk or negedge VAR3)
begin
if (VAR3 == 0)
VAR6 <= 0;
end
el... | gpl-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_2L_007bits.v | 1,917 | module MODULE2 (
clk,
VAR29, VAR11, VAR25, VAR9, VAR27, VAR33, VAR15, VAR28,
sum,
);
input clk;
input [VAR7+0-1:0] VAR29, VAR11, VAR25, VAR9, VAR27, VAR33, VAR15, VAR28;
output [VAR7 :0] sum;
reg [VAR7 :0] sum;
wire [VAR7+3-1:0] VAR14;
wire [VAR7+2-1:0] VAR1, VAR30;
wire [VAR7+1-1:0] VAR8, VAR2, VAR3, VAR12;
reg [VAR7+... | mit |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_033.v | 1,479 | module MODULE2 (
VAR9,
VAR6
);
input [31:0] VAR9;
output [31:0]
VAR6;
wire [31:0]
VAR3,
VAR1,
VAR8,
VAR7,
VAR5,
VAR12,
VAR4,
VAR13;
assign VAR3 = VAR9;
assign VAR4 = VAR5 - VAR12;
assign VAR7 = VAR8 << 1;
assign VAR5 = VAR3 + VAR7;
assign VAR12 = VAR3 << 4;
assign VAR13 = VAR4 << 1;
assign VAR1 = VAR3 << 9;
assign VAR8... | mit |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_44.v | 30,974 | module MODULE5 (
clk,
reset,
VAR142,
VAR172,
VAR21,
VAR154,
VAR237
);
parameter VAR165 = 18;
parameter VAR78 = 44;
parameter VAR66 = 22;
localparam VAR246 = 51;
input clk;
input reset;
input VAR142;
input VAR172;
input [VAR165-1:0] VAR21; output VAR154;
output [VAR165-1:0] VAR237;
localparam VAR192 = 18; localparam VAR... | mit |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/ipshared/ENCLab/Tiger4SharedKES_v1_0_0/8069a058/src/InterChannelSyndromeBuffer.v | 7,964 | module MODULE1
parameter VAR13 = 4,
parameter VAR40 = 2,
parameter VAR35 = 12,
parameter VAR22 = 27
)
(
VAR29 ,
VAR4 ,
VAR26 ,
VAR8 ,
VAR24 ,
VAR43 ,
VAR9 ,
VAR25 ,
VAR34 ,
VAR16 ,
VAR2 ,
VAR11 ,
VAR30
);
input VAR29 ;
input VAR4 ;
input [VAR13*VAR40 - 1:0] VAR26 ;
input [VAR13*VAR40 - 1:0] VAR8 ;
input [VAR13*VAR40*VA... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_1.behavioral.pp.v | 1,174 | module MODULE1( VAR5, VAR4, VAR7, VAR6 );
input VAR5;
inout VAR7, VAR6;
output VAR4;
VAR2 VAR3(.VAR5(VAR5),.VAR4(VAR4),.VAR7(VAR7),.VAR6(VAR6));
VAR2 VAR1(.VAR5(VAR5),.VAR4(VAR4),.VAR7(VAR7),.VAR6(VAR6)); | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_2L_048bits.v | 1,917 | module MODULE1 (
clk,
VAR30, VAR12, VAR27, VAR22, VAR24, VAR14, VAR5, VAR29,
sum,
);
input clk;
input [VAR31+0-1:0] VAR30, VAR12, VAR27, VAR22, VAR24, VAR14, VAR5, VAR29;
output [VAR31 :0] sum;
reg [VAR31 :0] sum;
wire [VAR31+3-1:0] VAR19;
wire [VAR31+2-1:0] VAR1, VAR3;
wire [VAR31+1-1:0] VAR34, VAR13, VAR21, VAR18;
re... | mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/vfabric_icmp.v | 3,532 | module MODULE1(VAR26, VAR15,
VAR24, VAR17, VAR25,
VAR6, VAR5, VAR9,
VAR22, VAR11, VAR21, VAR19);
parameter VAR10 = 32;
parameter VAR13 = 4;
parameter VAR18 = 64;
input VAR26, VAR15;
input [VAR10-1:0] VAR24;
input [VAR10-1:0] VAR6;
input VAR17, VAR5;
output VAR25, VAR9;
output reg VAR22;
output VAR11;
input VAR21;
input... | mit |
martinmiranda14/Digitales | Lab_6/new/hello_world.v | 23,395 | module MODULE2(
input clk,
input rst,
input [10:0]VAR50,
input [10:0]VAR31,
output VAR10,
output reg VAR27
);
localparam VAR49 = 2'd3; localparam VAR16 = 11'd422;
localparam VAR11 = 11'd348;
localparam VAR15 = 8'd5;
localparam VAR38 = 8'd8;
localparam VAR29 = 10; localparam VAR34 = 3; localparam VAR14 = ( VAR15 + 8'd1 ... | apache-2.0 |
fbelavenuto/msx1fpga | src/audio/jt51/jt51_phrom.v | 3,323 | module MODULE1
(
input [4:0] addr,
input clk,
output reg [45:0] VAR1
);
reg [45:0] VAR2[31:0];
begin | gpl-3.0 |
marqs85/de2-vd | rtl/seg7_ctrl.v | 1,390 | module MODULE1(
input [3:0] VAR1,
output [6:0] VAR2
);
always @(*)
case (VAR1)
4'h0: VAR2 = ~7'b0111111;
4'h1: VAR2 = ~7'b0000110;
4'h2: VAR2 = ~7'b1011011;
4'h3: VAR2 = ~7'b1001111;
4'h4: VAR2 = ~7'b1100110;
4'h5: VAR2 = ~7'b1101101;
4'h6: VAR2 = ~7'b1111101;
4'h7: VAR2 = ~7'b0000111;
4'h8: VAR2 = ~7'b1111111;
4'h9: V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/mux2/sky130_fd_sc_ms__mux2.behavioral.pp.v | 1,902 | module MODULE1 (
VAR3 ,
VAR14 ,
VAR12 ,
VAR11 ,
VAR7,
VAR1,
VAR2 ,
VAR6
);
output VAR3 ;
input VAR14 ;
input VAR12 ;
input VAR11 ;
input VAR7;
input VAR1;
input VAR2 ;
input VAR6 ;
wire VAR13 ;
wire VAR4;
VAR9 VAR8 (VAR13 , VAR14, VAR12, VAR11 );
VAR5 VAR15 (VAR4, VAR13, VAR7, VAR1);
buf VAR10 (VAR3 , VAR4 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_1.functional.v | 1,384 | module MODULE1( VAR19, VAR12, VAR20, VAR7, VAR6, VAR3, VAR9 );
input VAR9, VAR3, VAR19, VAR20, VAR12, VAR6;
output VAR7;
wire VAR5;
not VAR13( VAR5, VAR12 );
wire VAR4;
not VAR2( VAR4, VAR6 );
wire VAR17;
and VAR18( VAR17, VAR5, VAR4, VAR9 );
wire VAR10;
and VAR11( VAR10, VAR4, VAR3, VAR12 );
wire VAR8;
and VAR1( VAR8,... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a31oi/sky130_fd_sc_hdll__a31oi.pp.blackbox.v | 1,399 | module MODULE1 (
VAR2 ,
VAR8 ,
VAR4 ,
VAR5 ,
VAR1 ,
VAR6,
VAR9,
VAR7 ,
VAR3
);
output VAR2 ;
input VAR8 ;
input VAR4 ;
input VAR5 ;
input VAR1 ;
input VAR6;
input VAR9;
input VAR7 ;
input VAR3 ;
endmodule | apache-2.0 |
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