repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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gtaylormb/fpga_nes | hw/src/cpu/apu/apu_triangle.v | 5,531 | module MODULE1
(
input wire VAR1, input wire VAR41, input wire VAR28, input wire VAR37, input wire VAR29, input wire VAR39, input wire [1:0] VAR33, input wire [7:0] din, input wire VAR36, output wire [3:0] VAR38, output wire VAR19 );
reg [10:0] VAR15;
wire [10:0] VAR2;
wire VAR11;
always @(posedge VAR1)
begin
if (VAR41... | bsd-2-clause |
piranna/wasmachine | src/stack.v | 1,748 | module MODULE1
parameter VAR3 = 8, parameter VAR13 = 3 )
(
input clk,
input reset,
input [ 1:0] VAR9, input [VAR3-1:0] VAR11, output [VAR3-1:0] VAR8,
output reg [1:0] VAR5 = VAR6, output reg [1:0] VAR2 = VAR7 );
localparam VAR1 = (1 << VAR13+1) - 1;
reg [VAR3-1:0] MODULE1 [0:VAR1-1];
reg [ VAR13:0] VAR10 = 0;
assign VA... | gpl-3.0 |
Digilent/vivado-library | ip/hls_saturation_enhance_1_0/hdl/verilog/fifo_w16_d4_A.v | 2,977 | module MODULE2 (
clk,
VAR17,
VAR9,
VAR1,
VAR2);
parameter VAR20 = 32'd16;
parameter VAR8 = 32'd3;
parameter VAR22 = 32'd5;
input clk;
input [VAR20-1:0] VAR17;
input VAR9;
input [VAR8-1:0] VAR1;
output [VAR20-1:0] VAR2;
reg[VAR20-1:0] VAR25 [0:VAR22-1];
integer VAR11;
always @ (posedge clk)
begin
if (VAR9)
begin
for (VA... | mit |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy/ddr3_s4_uniphy_p0_iss_probe.v | 1,721 | module MODULE1 (
VAR33
);
parameter VAR22 = 1;
parameter VAR13 = "VAR15";
input [VAR22-1:0] VAR33;
VAR5 VAR21 (
.VAR31 (VAR33),
.VAR9 ()
,
.VAR27 (),
.VAR8 (),
.VAR20 (),
.VAR32 (),
.VAR19 (),
.VAR34 (),
.VAR12 (),
.VAR14 (),
.VAR26 (),
.VAR7 (),
.VAR3 (),
.VAR1 (),
.VAR2 (),
.VAR10 (),
.VAR24 (),
.VAR6 (),
.VAR25 ()
)... | lgpl-3.0 |
FPGA1988/udp_ip_stack | Network/udp_ip_core/trunk/ic/digital/rtl/eth_tri_mode/miim/eth_shiftreg.v | 6,843 | module MODULE1(VAR8, VAR14, VAR7, VAR13, VAR6, VAR11, VAR3, VAR10, VAR4,
VAR1, VAR15, VAR2, VAR5);
parameter VAR12=1;
input VAR8; input VAR14; input VAR7; input VAR13; input [4:0] VAR6; input [4:0] VAR11; input [15:0]VAR3; input VAR10; input [3:0] VAR4; input [1:0] VAR1;
output VAR15; output[15:0]VAR2; output VAR5;
reg... | apache-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/cores/wb_altera_ddr_wrapper/bench/ddr_ctrl_ip/alt_mem_ddrx_timing_param.v | 67,710 | module MODULE1 #
( parameter
VAR177 = 2,
VAR1 = "VAR148",
VAR159 = 3,
VAR113 = 5,
VAR124 = 4, VAR134 = 3, VAR52 = 4, VAR71 = 4, VAR154 = 6, VAR94 = 8, VAR121 = 13, VAR133 = 4, VAR37 = 4, VAR84 = 4, VAR171 = 4, VAR82 = 4, VAR55 = 5, VAR35 = 6, VAR10 = 3, VAR25 = 3, VAR186 = 10, VAR155 = 4, VAR80 = 16, VAR56 = 4, VAR57 =... | gpl-2.0 |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/wasca/synthesis/submodules/wasca_nios2_gen2_0.v | 5,661 | module MODULE1 (
input wire clk, input wire VAR23, output wire [27:0] VAR21, output wire [3:0] VAR9, output wire VAR17, input wire [31:0] VAR10, input wire VAR4, output wire VAR6, output wire [31:0] VAR25, output wire VAR14, output wire [24:0] VAR18, output wire VAR16, input wire [31:0] VAR26, input wire VAR15, input w... | gpl-2.0 |
krucios/Echo_module | src/servo_fsm.v | 3,544 | module MODULE1 #(parameter VAR10 = 1)(
input wire clk,
input wire VAR12,
input wire VAR14,
output reg[7:0] VAR9 = 8'h80,
input wire VAR1, input wire[7:0] VAR7, input wire[7:0] VAR2 );
reg[1:0] state = 0; reg[1:0] VAR4 = 0; parameter VAR11 = 2'b00;
parameter VAR5 = 2'b01;
parameter VAR13 = 2'b10;
parameter VAR8 = 2'b11;... | gpl-3.0 |
fpgasystems/Centaur | rtl/fthread/iolib/ReadConfigStruct.v | 3,993 | module MODULE1 #(parameter VAR8 = 2)
(
input wire clk,
input wire VAR20,
input wire VAR2,
input wire [57:0] VAR4,
input wire [31:0] VAR14,
output reg [57:0] VAR11,
output reg [8:0] VAR17,
output reg VAR23,
input wire VAR22,
input wire [8:0] VAR10,
input wire [511:0] VAR9,
input wire VAR1,
output wire [(VAR8<<9)-1:0] VA... | apache-2.0 |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/ipshared/xilinx.com/processing_system7_bfm_v2_0/e69044ca/hdl/processing_system7_bfm_v2_0_arb_wr.v | 3,932 | module MODULE1(
VAR24,
VAR8,
VAR11,
VAR15,
VAR4,
VAR20,
VAR9,
VAR21,
VAR1,
VAR27,
VAR2,
VAR14,
VAR29,
VAR22,
VAR23,
VAR26,
VAR12,
VAR7,
VAR6,
VAR16
);
input VAR24, VAR8;
input [VAR25-1:0] VAR11,VAR15;
input [VAR13-1:0] VAR9,VAR21;
input [VAR5-1:0] VAR1,VAR27;
input [VAR19:0] VAR2,VAR14;
input VAR4, VAR20, VAR16;
output... | mit |
jairov4/accel-oil | solution_spartan3/syn/verilog/sample_iterator_next.v | 21,326 | module MODULE1 (
VAR101,
VAR1,
VAR32,
VAR10,
VAR12,
VAR72,
VAR53,
VAR82,
VAR60,
VAR103,
VAR71,
VAR86,
VAR64,
VAR17,
VAR8,
VAR48,
VAR19,
VAR42,
VAR88,
VAR89,
VAR30,
VAR81,
VAR92,
VAR5,
VAR94,
VAR76,
VAR18,
VAR109,
VAR115,
VAR106,
VAR57,
VAR49,
VAR113,
VAR47,
VAR68,
VAR74,
VAR84,
VAR33
);
input VAR101;
input VAR1;
input ... | lgpl-3.0 |
cafe-alpha/wasca | fpga_firmware/wasca/synthesis/submodules/wasca_nios2_gen2_0_cpu_debug_slave_tck.v | 8,183 | module MODULE1 (
VAR22,
VAR9,
VAR18,
VAR1,
VAR4,
VAR28,
VAR20,
VAR27,
VAR35,
VAR31,
VAR12,
VAR40,
VAR23,
VAR17,
VAR15,
VAR6,
VAR24,
VAR2,
VAR19,
VAR21,
VAR13,
VAR3,
VAR37,
VAR5,
VAR16,
VAR7,
VAR26,
VAR29,
VAR39,
VAR34,
VAR25
)
;
output [ 1: 0] VAR26;
output VAR29;
output [ 37: 0] VAR39;
output VAR34;
output VAR25;
inpu... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor3b/sky130_fd_sc_ms__nor3b.blackbox.v | 1,331 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR3 ,
VAR6
);
output VAR1 ;
input VAR2 ;
input VAR3 ;
input VAR6;
supply1 VAR5;
supply0 VAR7;
supply1 VAR8 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axi_crossbar_v2_1/hdl/verilog/axi_crossbar_v2_1_addr_arbiter.v | 13,806 | module MODULE1 #
(
parameter VAR49 = "none",
parameter integer VAR41 = 1,
parameter integer VAR26 = 1,
parameter integer VAR11 = 1,
parameter integer VAR35 = 1,
parameter [VAR41*32-1:0] VAR69 = {VAR41{32'h00000000}}
)
(
input wire VAR5,
input wire VAR71,
input wire [VAR41*VAR35-1:0] VAR19,
input wire [VAR41*VAR11-1:0] ... | mit |
ShirmanXia/EE469SPRING16 | lab4/nios_system/synthesis/submodules/nios_system_load.v | 2,159 | module MODULE1 (
address,
VAR8,
clk,
VAR4,
VAR5,
VAR6,
VAR9,
VAR1
)
;
output VAR9;
output [ 31: 0] VAR1;
input [ 1: 0] address;
input VAR8;
input clk;
input VAR4;
input VAR5;
input [ 31: 0] VAR6;
wire VAR2;
reg VAR3;
wire VAR9;
wire VAR7;
wire [ 31: 0] VAR1;
assign VAR2 = 1;
assign VAR7 = {1 {(address == 0)}} & VAR3;
a... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o32a/sky130_fd_sc_hd__o32a.blackbox.v | 1,384 | module MODULE1 (
VAR8 ,
VAR7,
VAR10,
VAR6,
VAR3,
VAR4
);
output VAR8 ;
input VAR7;
input VAR10;
input VAR6;
input VAR3;
input VAR4;
supply1 VAR1;
supply0 VAR5;
supply1 VAR2 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlymetal6s2s/sky130_fd_sc_lp__dlymetal6s2s_1.v | 2,157 | module MODULE2 (
VAR6 ,
VAR1 ,
VAR3,
VAR2,
VAR7 ,
VAR4
);
output VAR6 ;
input VAR1 ;
input VAR3;
input VAR2;
input VAR7 ;
input VAR4 ;
VAR8 VAR5 (
.VAR6(VAR6),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR6,
VAR1
);
output VAR6;
input VAR1;
supply1 VAR3;
supply0 VAR2;... | apache-2.0 |
tmolteno/TART | hardware/FPGA/ddrmem/counter.v | 2,328 | module MODULE1 (
VAR3,
VAR4,
VAR7,
VAR2
);
parameter VAR1 = 200;
parameter VAR5 = 8;
input VAR3;
input VAR4;
input VAR7;
output VAR2;
reg [VAR5-1:0] MODULE1 = VAR1 - 1;
reg VAR6 = 0;
always @(posedge VAR3)
begin
if (VAR4)
begin
VAR6 <= 0;
MODULE1 <= VAR1 - 1;
end
else
begin
if (VAR7)
begin
MODULE1 <= VAR1 - 1;
VAR6 <= ... | lgpl-3.0 |
googleinterns/hw-fuzzing | third_party/aes_128/round.v | 2,640 | module MODULE1 (clk, VAR22, VAR6, VAR39);
input clk;
input [127:0] VAR22, VAR6;
output reg [127:0] VAR39;
wire [31:0] VAR27, VAR35, VAR1, VAR7,
VAR17, VAR4, VAR42, VAR11,
VAR29, VAR21, VAR36, VAR10,
VAR16, VAR40, VAR37, VAR23,
VAR26, VAR24, VAR33, VAR14,
VAR15, VAR18, VAR8, VAR20,
VAR31, VAR9, VAR3, VAR12;
assign {VAR3... | apache-2.0 |
liuyenting/CA-Project | src/EXMEM_Reg.v | 1,292 | module MODULE1 (
input clk,
input VAR16,
input VAR22,
input [2-1:0] VAR21,
output [2-1:0] VAR8,
input [2-1:0] VAR12,
output [2-1:0] VAR1,
input [32-1:0] VAR11,
output [32-1:0] VAR5,
input [32-1:0] VAR15,
output [32-1:0] VAR13,
input [5-1:0] VAR7,
output [5-1:0] VAR9
);
VAR19 #(.VAR17(2)) VAR3 (
.clk (clk),
.rst (~VAR16... | gpl-3.0 |
franmolinaca/papiGB | rtl/mmu.v | 10,126 | module MODULE1
(
input wire VAR26,
input wire VAR32,
input wire VAR85,
input wire [15:0] VAR57,
input wire VAR89,
input wire [7:0] VAR78,
output wire [7:0] VAR86,
output wire [7:0] VAR19,
input wire VAR18,
input wire [15:0] VAR43,
output wire [3:0] VAR72,
output wire VAR62,
output wire [7:0] VAR37,
input wire [7:0] VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor3/sky130_fd_sc_ms__nor3_2.v | 2,198 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR9 ,
VAR6 ,
VAR10,
VAR7,
VAR8 ,
VAR2
);
output VAR1 ;
input VAR3 ;
input VAR9 ;
input VAR6 ;
input VAR10;
input VAR7;
input VAR8 ;
input VAR2 ;
VAR5 VAR4 (
.VAR1(VAR1),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR2(VAR2)
);
endmodule
module MODULE... | apache-2.0 |
dnet/proxmark3 | fpga/min_max_tracker.v | 1,947 | module MODULE1(input clk, input [7:0] VAR6, input [7:0] VAR4,
output [7:0] VAR7, output [7:0] VAR2);
reg [7:0] VAR5 = 255;
reg [7:0] VAR3 = 0;
reg [7:0] VAR8 = 255;
reg [7:0] VAR1 = 0;
reg [1:0] state = 0;
always @(posedge clk)
begin
case (state)
0:
begin
if (VAR1 >= ({1'b0, VAR6} + VAR4))
state <= 2;
end
else if (VAR6... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and3/sky130_fd_sc_lp__and3.behavioral.pp.v | 1,810 | module MODULE1 (
VAR5 ,
VAR13 ,
VAR3 ,
VAR14 ,
VAR7,
VAR8,
VAR4 ,
VAR2
);
output VAR5 ;
input VAR13 ;
input VAR3 ;
input VAR14 ;
input VAR7;
input VAR8;
input VAR4 ;
input VAR2 ;
wire VAR12 ;
wire VAR11;
and VAR10 (VAR12 , VAR14, VAR13, VAR3 );
VAR6 VAR9 (VAR11, VAR12, VAR7, VAR8);
buf VAR1 (VAR5 , VAR11 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a211oi/sky130_fd_sc_ms__a211oi_2.v | 2,361 | module MODULE1 (
VAR2 ,
VAR9 ,
VAR6 ,
VAR5 ,
VAR3 ,
VAR10,
VAR7,
VAR4 ,
VAR8
);
output VAR2 ;
input VAR9 ;
input VAR6 ;
input VAR5 ;
input VAR3 ;
input VAR10;
input VAR7;
input VAR4 ;
input VAR8 ;
VAR11 VAR1 (
.VAR2(VAR2),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR... | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/hpdmc_ddr32/rtl/hpdmc_busif.v | 1,373 | module MODULE1 #(
parameter VAR4 = 26
) (
input VAR6,
input VAR7,
input [VAR4-1:0] VAR2,
input VAR5,
input VAR3,
output VAR9,
output VAR10,
output VAR11,
output [VAR4-3-1:0] VAR13,
input VAR8,
input VAR12
);
reg VAR1;
assign VAR10 = VAR5 & VAR1;
assign VAR11 = VAR3;
assign VAR13 = VAR2[VAR4-1:3];
assign VAR9 = VAR12;
a... | lgpl-3.0 |
DougFirErickson/parallella-hw | boards/archive/gen1.1/fpga/hdl/ewrapper_link_transmitter.v | 7,774 | module MODULE1(
VAR15, VAR37, VAR33,
reset, VAR50, VAR7, VAR28,
VAR55, VAR17, VAR16,
VAR12, VAR27, VAR13,
VAR44, VAR39, VAR8
);
input reset; input VAR50;
input VAR7;
input VAR28;
input VAR55;
input [1:0] VAR17;
input [3:0] VAR16;
input [31:0] VAR12;
input [31:0] VAR27;
input [31:0] VAR13;
input VAR44; input VAR39;
inpu... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfrtp_ov2/sky130_fd_sc_lp__sdfrtp_ov2.pp.blackbox.v | 1,421 | module MODULE1 (
VAR3 ,
VAR10 ,
VAR7 ,
VAR1 ,
VAR5 ,
VAR9,
VAR6 ,
VAR4 ,
VAR8 ,
VAR2
);
output VAR3 ;
input VAR10 ;
input VAR7 ;
input VAR1 ;
input VAR5 ;
input VAR9;
input VAR6 ;
input VAR4 ;
input VAR8 ;
input VAR2 ;
endmodule | apache-2.0 |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/new/seven_seg.v | 6,893 | module MODULE1(
input clk,
input signed [5:0] VAR6,
input signed [5:0] VAR8,
output reg [7:0] VAR4,
output reg [7:0] VAR7
);
reg [7:0] VAR5;
reg [7:0] VAR3;
reg [5:0] VAR2;
reg [5:0] VAR1; | mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_0.v | 61,932 | module MODULE1 (
input wire VAR156, input wire VAR311, input wire VAR213, input wire [29:0] VAR131, output wire VAR332, input wire [0:0] VAR29, input wire [3:0] VAR319, input wire VAR389, output wire [31:0] VAR244, output wire VAR337, input wire VAR339, input wire [31:0] VAR24, output wire [29:0] VAR175, output wire VA... | mit |
fpgaminer/sha1_collider | hdl/counter.v | 2,282 | module MODULE3 # (
parameter VAR9 = 1
) (
input clk,
input rst,
input [59:0] VAR3,
output reg [59:0] VAR13
);
genvar VAR16;
generate
for (VAR16 = 0; VAR16 < 15; VAR16=VAR16+1) begin : VAR10
reg [3:0] VAR11 = 4'd0;
wire [3:0] VAR8;
wire VAR12;
if (VAR16 == 0)
MODULE1 MODULE1 (.VAR1 (VAR11), .VAR5 (VAR9), .VAR14 (0), .VA... | gpl-3.0 |
Digilent/vivado-library | ip/hls_saturation_enhance_1_0/hdl/verilog/Loop_loop_height_ibs.v | 1,187 | module MODULE1 (
VAR6, VAR7, VAR4, clk);
parameter VAR3 = 8;
parameter VAR5 = 8;
parameter VAR1 = 256;
input[VAR5-1:0] VAR6;
input VAR7;
output reg[VAR3-1:0] VAR4;
input clk;
reg [VAR3-1:0] VAR2[0:VAR1-1];
begin
begin | mit |
jhennessy/parallella-hw-old | boards/archive/gen1.1/fpga/hdl/ewrapper_link_top.v | 12,050 | module MODULE1 (
VAR63, VAR30, VAR14,
VAR97, VAR108, VAR98,
VAR90, VAR62, VAR1,
VAR4, VAR87, VAR23, VAR50,
VAR34, VAR105, VAR37, VAR17, VAR99,
VAR88, VAR107, VAR36, VAR53,
reset, VAR64, VAR82, VAR109,
VAR96, VAR32, VAR68,
VAR29, VAR104, VAR19,
VAR101, VAR18, VAR28, VAR65,
VAR9, VAR60, VAR44, VAR56, VAR85,
VAR3, VAR22, ... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mesosync_io/src/bsg_mesosync_input.v | 12,821 | module MODULE1
, parameter VAR34(VAR33 )
, parameter VAR34(VAR104 )
, parameter VAR34(VAR8 )
, parameter VAR74 = VAR33 + VAR104
)
( input clk
, input reset
, input VAR13 VAR82
, input [VAR74-1:0] VAR83
, output logic [VAR74-1:0] VAR10
, output logic VAR17
, output VAR71
, output VAR94
, input VAR60
);
logic [1:0] VAR29... | bsd-3-clause |
freecores/orsoc_graphics_accelerator | rtl/verilog/gfx/gfx_wbm_read.v | 3,120 | module MODULE1 (VAR12, VAR13,
VAR5, VAR3, VAR15, VAR6, VAR1, VAR18, VAR2, VAR7, VAR9, VAR10, VAR17,
VAR11,
VAR4, VAR19, VAR14, VAR16);
input VAR12; input VAR13; output reg VAR5; output VAR3; output [ 2:0] VAR15; output [ 1:0] VAR6; output VAR1; output [31:0] VAR18; output reg [ 3:0] VAR2; input VAR7; input VAR9; input ... | gpl-3.0 |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_gen_reset.v | 5,210 | module MODULE1(
VAR13,
VAR20,
VAR43,
VAR19,
VAR29,
VAR2,
VAR31,
VAR39,
VAR34,
VAR17,
VAR35,
VAR28,
VAR40,
VAR14,
VAR24,
VAR15,
VAR6,
VAR26,
VAR5,
VAR27,
VAR42,
VAR30,
VAR22,
VAR12,
VAR37,
VAR21,
VAR36,
VAR11,
VAR18,
VAR25,
VAR23,
VAR45,
VAR33,
VAR1
);
input VAR13;
input VAR20;
input VAR19;
input VAR29;
input VAR2;
inpu... | mit |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/stream_encoder_ip_prj/stream_encoder_ip_prj.ip_user_files/ip/cdn_axi_bfm_0/hdl/src/verilog/cdn_axi_bfm_0.v | 7,463 | module MODULE1 (VAR30, VAR8,
VAR37, VAR29, VAR28,
VAR12,VAR1,VAR27,VAR4, VAR39);
parameter VAR3 = "MODULE1";
parameter VAR5 = 24;
parameter VAR34 = 8;
parameter VAR25 = 4;
parameter VAR19 = 8;
parameter VAR11 = 10;
parameter VAR40 = 8;
parameter VAR7 = 8;
parameter VAR38 = 1;
parameter VAR23 = 0;
input wire VAR30;
inpu... | gpl-3.0 |
PeterMagnusson/modexp | src/rtl/montprod.v | 17,258 | module MODULE1(
input wire clk,
input wire VAR28,
input wire VAR76,
output wire ready,
input [7 : 0] VAR68,
output wire [7 : 0] VAR88,
input wire [31 : 0] VAR12,
output wire [7 : 0] VAR59,
input wire [31 : 0] VAR10,
output wire [7 : 0] VAR57,
input wire [31 : 0] VAR42,
output wire [7 : 0] VAR8,
output wire [31 : 0] VAR... | bsd-2-clause |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature_KOA/FastMultiplier-master/CLA.v | 1,749 | module MODULE1(VAR5, VAR13, VAR9, VAR2, VAR6, VAR11, VAR8);parameter VAR14 = 4;
input wire [VAR14-1:0] VAR5;
input wire [VAR14-1:0] VAR13;
input wire VAR9;
output wire [VAR14-1:0] VAR2;
output wire VAR6;
output wire VAR11;
output wire VAR8;
wire VAR12 [VAR14-1:0];
wire VAR7 [VAR14-1:0];
wire VAR10 [VAR14-1:0];
wire VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/diode/sky130_fd_sc_ms__diode.functional.v | 1,081 | module MODULE1 (
VAR1
);
input VAR1;
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_dmac/src_fifo_inf.v | 4,201 | module MODULE1 (
input clk,
input VAR29,
input enable,
output VAR26,
input VAR27,
output VAR5,
input [VAR28-1:0] VAR20,
output [VAR28-1:0] VAR23,
input VAR31,
input en,
input [VAR16-1:0] din,
output reg VAR18,
input sync,
output VAR19,
input VAR3,
output VAR17,
output [VAR16-1:0] VAR22,
input VAR25,
output VAR24,
input... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hd__udp_dlatch_p_pp_pg_n.symbol.v | 1,438 | module MODULE1 (
input VAR5 ,
output VAR1 ,
input VAR3 ,
input VAR2,
input VAR6 ,
input VAR4
);
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/ffu/rtl/sparc_ffu_dp.v | 22,284 | module MODULE1 (
VAR80, VAR4, VAR110, VAR12, VAR79,
VAR119, VAR124, VAR48, VAR82,
VAR83, VAR146, VAR88,
VAR32, VAR24, VAR36,
VAR109,
VAR143, VAR31, VAR112, VAR71, VAR57, VAR26,
VAR68, VAR81, VAR44, VAR34,
VAR100, VAR132, VAR64, VAR89,
VAR135, VAR28,
VAR16, VAR11,
VAR19, VAR123,
VAR58, VAR134, VAR145,
VAR45, VAR67, VAR1... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/iso1n/sky130_fd_sc_lp__iso1n_lp.v | 2,202 | module MODULE2 (
VAR4 ,
VAR5 ,
VAR9,
VAR6 ,
VAR1 ,
VAR3 ,
VAR7
);
output VAR4 ;
input VAR5 ;
input VAR9;
input VAR6 ;
input VAR1 ;
input VAR3 ;
input VAR7 ;
VAR8 VAR2 (
.VAR4(VAR4),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR4 ,
VAR5 ,
VAR9
);
output VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/xor3/sky130_fd_sc_ls__xor3.functional.pp.v | 1,845 | module MODULE1 (
VAR7 ,
VAR8 ,
VAR12 ,
VAR1 ,
VAR4,
VAR3,
VAR14 ,
VAR2
);
output VAR7 ;
input VAR8 ;
input VAR12 ;
input VAR1 ;
input VAR4;
input VAR3;
input VAR14 ;
input VAR2 ;
wire VAR11 ;
wire VAR10;
xor VAR6 (VAR11 , VAR8, VAR12, VAR1 );
VAR9 VAR5 (VAR10, VAR11, VAR4, VAR3);
buf VAR13 (VAR7 , VAR10 );
endmodule | apache-2.0 |
alan4186/ParCNN | Hardware/v/window_wrapper.v | 1,782 | module MODULE1(
input VAR18,
input reset,
input [VAR10:0] VAR28,
input VAR6,
input VAR24,
input [VAR31:0] VAR29, input [VAR26:0] VAR32,
output [VAR15:0] VAR7
);
wire [VAR3:0] VAR2;
wire [VAR10:0] VAR1 [VAR17-1:0][VAR17-1:0];
VAR4 VAR11(
.VAR18(VAR18),
.reset(reset),
.VAR24(VAR24), .VAR6(VAR6), .VAR28(VAR28),
.VAR9(VAR2... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o21a/sky130_fd_sc_ls__o21a_4.v | 2,248 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR10 ,
VAR8 ,
VAR7,
VAR5,
VAR3 ,
VAR9
);
output VAR4 ;
input VAR1 ;
input VAR10 ;
input VAR8 ;
input VAR7;
input VAR5;
input VAR3 ;
input VAR9 ;
VAR6 VAR2 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR9(VAR9)
);
endmodule
module MODULE... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/cores/axis_pulse_height_analyzer_v1_0/src/axis_pulse_height_analyzer.v | 4,030 | module MODULE1 #
(
parameter integer VAR23 = 16,
parameter VAR26 = "VAR17",
parameter integer VAR3 = 16
)
(
input wire VAR33,
input wire VAR21,
input wire [VAR3-1:0] VAR32,
input wire [VAR23-1:0] VAR22,
input wire [VAR23-1:0] VAR12,
output wire VAR34,
input wire [VAR23-1:0] VAR4,
input wire VAR18,
input wire VAR5,
outp... | gpl-3.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project.xpr/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_xbar_1/synth/design_1_xbar_1.v | 19,339 | module MODULE1 (
VAR127,
VAR41,
VAR101,
VAR44,
VAR111,
VAR25,
VAR99,
VAR39,
VAR40,
VAR47,
VAR57,
VAR32,
VAR67,
VAR82,
VAR73,
VAR58,
VAR68,
VAR90,
VAR62,
VAR132,
VAR27,
VAR72,
VAR42,
VAR53,
VAR81,
VAR109,
VAR105,
VAR128,
VAR120,
VAR91,
VAR100,
VAR115,
VAR93,
VAR5,
VAR125,
VAR122,
VAR95,
VAR121,
VAR119,
VAR49
);
input wi... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o311ai/sky130_fd_sc_hs__o311ai_2.v | 2,308 | module MODULE1 (
VAR9 ,
VAR10 ,
VAR5 ,
VAR8 ,
VAR3 ,
VAR2 ,
VAR7,
VAR4
);
output VAR9 ;
input VAR10 ;
input VAR5 ;
input VAR8 ;
input VAR3 ;
input VAR2 ;
input VAR7;
input VAR4;
VAR1 VAR6 (
.VAR9(VAR9),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR4(VAR4)
);
endmodule
module MODUL... | apache-2.0 |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/acl_fp_acospi_s5.v | 1,188 | module MODULE1 (
enable,
VAR3,
VAR9,
VAR5);
input enable;
input VAR3;
input [31:0] VAR9;
output [31:0] VAR5;
wire [31:0] VAR7;
wire [31:0] VAR5 = VAR7[31:0];
VAR4 VAR8 (
.en (enable),
.VAR6(1'b0),
.clk(VAR3),
.VAR2(VAR9),
.VAR1(VAR7));
endmodule | mit |
alexforencich/xfcp | example/VCU108/fpga/rtl/fpga.v | 10,022 | module MODULE1 (
input wire VAR15,
input wire VAR103,
input wire reset,
input wire VAR122,
input wire VAR50,
input wire VAR67,
input wire VAR83,
input wire VAR166,
input wire [3:0] VAR29,
output wire [7:0] VAR101,
inout wire VAR87,
inout wire VAR91,
input wire VAR94,
input wire VAR180,
output wire VAR107,
output wire V... | mit |
somethingnew2-0/CS552-CPU | not_in_tarball/rf_single_cycle.v | 2,498 | module MODULE1(clk,VAR10,VAR5,VAR4,VAR15,VAR1,VAR12,VAR14,VAR8,VAR13,VAR9);
input clk;
input [3:0] VAR10, VAR5; input VAR1,VAR12; input [3:0] VAR14; input [15:0] VAR8; input VAR13; input VAR9;
output reg [15:0] VAR4,VAR15;
integer VAR2;
reg [15:0]VAR3[0:15];
reg [3:0] VAR11; reg [15:0] VAR7; reg VAR6;
begin | mit |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v2_0_ddr_mc_phy.v | 88,782 | module MODULE1
parameter VAR103 = 4'b1111,
parameter VAR480 = 4'b0000,
parameter VAR157 = 4'b0000,
parameter VAR237 = 4'b0000,
parameter VAR450 = 4'b0000,
parameter VAR11 = 4'hc,
parameter VAR427 = 4'hf,
parameter VAR305 = 4'hf,
parameter VAR93 = 4'hf,
parameter VAR147 = 4'hf,
parameter VAR204 = 0,
parameter VAR190 = "... | bsd-2-clause |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/median/ipi_proj/srcs/ip/xilinx_com_hls_image_filter_1_0/hdl/verilog/FIFO_image_filter_img_1_data_stream_1_V.v | 3,017 | module MODULE2 (
clk,
VAR8,
VAR21,
VAR25,
VAR5);
parameter VAR17 = 32'd8;
parameter VAR24 = 32'd1;
parameter VAR7 = 32'd2;
input clk;
input [VAR17-1:0] VAR8;
input VAR21;
input [VAR24-1:0] VAR25;
output [VAR17-1:0] VAR5;
reg[VAR17-1:0] VAR23 [0:VAR7-1];
integer VAR18;
always @ (posedge clk)
begin
if (VAR21)
begin
for (... | gpl-3.0 |
bluespec/Flute | builds/RV32ACDFIMSU_Flute_verilator/Verilog_RTL/mkFBox_Top.v | 5,329 | module MODULE1(VAR5,
VAR8,
VAR2,
VAR7,
VAR36,
VAR3,
VAR4,
VAR25,
VAR28,
VAR34,
VAR35,
VAR27,
VAR19,
VAR22,
VAR13,
valid,
VAR29,
VAR39);
input [3 : 0] VAR5;
input VAR8;
input VAR2;
input VAR7;
output VAR36;
input VAR3;
output VAR4;
input [6 : 0] VAR25;
input [6 : 0] VAR28;
input [2 : 0] VAR34;
input [4 : 0] VAR35;
input... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a41oi/sky130_fd_sc_hd__a41oi_1.v | 2,439 | module MODULE2 (
VAR1 ,
VAR2 ,
VAR6 ,
VAR10 ,
VAR12 ,
VAR8 ,
VAR9,
VAR4,
VAR11 ,
VAR5
);
output VAR1 ;
input VAR2 ;
input VAR6 ;
input VAR10 ;
input VAR12 ;
input VAR8 ;
input VAR9;
input VAR4;
input VAR11 ;
input VAR5 ;
VAR3 VAR7 (
.VAR1(VAR1),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR12(VAR12),
.VAR8(VAR8),
.VAR9... | apache-2.0 |
eda-globetrotter/MarcheProcessor | processor/spare/build2/jpdt.v | 49,254 | module MODULE1 (VAR7,VAR8,VAR10,VAR9,VAR26);
output [0:127] VAR26;
input [0:127] VAR7;
input [0:127] VAR8;
input [0:1] VAR10;
input [0:4] VAR9;
integer VAR21;
reg [0:127] VAR26;
reg [0:127] VAR23;
reg [0:15] VAR29;
reg [0:15] VAR19;
reg [0:15] VAR15;
reg [0:15] VAR17;
reg [0:15] VAR6;
reg [0:15] VAR30;
reg [0:15] VAR20... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or4bb/sky130_fd_sc_hd__or4bb.functional.v | 1,414 | module MODULE1 (
VAR10 ,
VAR7 ,
VAR5 ,
VAR1,
VAR3
);
output VAR10 ;
input VAR7 ;
input VAR5 ;
input VAR1;
input VAR3;
wire VAR6;
wire VAR9;
nand VAR8 (VAR6, VAR3, VAR1 );
or VAR4 (VAR9, VAR5, VAR7, VAR6);
buf VAR2 (VAR10 , VAR9 );
endmodule | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/Zynq_Book/hls/tut3A/matrix_mult_prj/solution4/syn/verilog/matrix_mult_mac_mcud.v | 1,807 | module MODULE2(
input clk,
input rst,
input VAR8,
input [8 - 1:0] VAR20,
input [8 - 1:0] VAR18,
input [16 - 1:0] VAR9,
output [16 - 1:0] dout);
wire signed [25 - 1:0] VAR16;
wire signed [18 - 1:0] VAR17;
wire signed [48 - 1:0] VAR5;
wire signed [43 - 1:0] VAR14;
wire signed [48 - 1:0] VAR12;
reg signed [43 - 1:0] VAR19... | mit |
PyLCARS/PythonUberHDL | myHDL_ComputerFundamentals/Counters/UpDown_Counter.v | 1,393 | module MODULE1 (
VAR1,
VAR2,
VAR4,
clk,
rst
);
input [0:0] VAR1;
output [4:0] VAR2;
wire [4:0] VAR2;
output VAR4;
reg VAR4;
input clk;
input rst;
reg [4:0] VAR5 = 8;
always @(posedge clk, negedge rst) begin: VAR3
if (rst) begin
VAR5 <= 8;
VAR4 <= 0;
end
else if ((((VAR5 / 17) == 1) && (rst == 0))) begin
VAR5 <= 8;
end
... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a222oi/sky130_fd_sc_ls__a222oi.symbol.v | 1,418 | module MODULE1 (
input VAR1,
input VAR10,
input VAR2,
input VAR3,
input VAR9,
input VAR7,
output VAR6
);
supply1 VAR5;
supply0 VAR11;
supply1 VAR4 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/iface/ip/uniphy_status/uniphy_status.v | 3,941 | module MODULE1
parameter VAR38=32,
parameter VAR18=2
)
(
input clk,
input VAR17,
input VAR30,
output [VAR38-1:0] VAR36,
input VAR16,
input VAR2,
input VAR4,
input VAR23,
input VAR3,
input VAR15,
input VAR22,
input VAR27,
input VAR33,
input VAR8,
input VAR32,
input VAR34,
input VAR21,
input VAR19,
input VAR37,
input VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o32a/sky130_fd_sc_ls__o32a_1.v | 2,428 | module MODULE1 (
VAR1 ,
VAR9 ,
VAR11 ,
VAR4 ,
VAR12 ,
VAR2 ,
VAR5,
VAR6,
VAR3 ,
VAR10
);
output VAR1 ;
input VAR9 ;
input VAR11 ;
input VAR4 ;
input VAR12 ;
input VAR2 ;
input VAR5;
input VAR6;
input VAR3 ;
input VAR10 ;
VAR8 VAR7 (
.VAR1(VAR1),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR12(VAR12),
.VAR2(VAR2),
.VAR5... | apache-2.0 |
ridecore/ridecore | src/fpga/src_manager.v | 1,329 | module MODULE1
(
input wire [VAR8-1:0] VAR10,
input wire VAR7,
input wire [VAR8-1:0] VAR5,
input wire [VAR13-1:0] VAR9,
input wire VAR1,
input wire [VAR8-1:0] VAR6,
input wire [VAR13-1:0] VAR17,
input wire VAR21,
input wire [VAR8-1:0] VAR20,
input wire [VAR13-1:0] VAR16,
input wire VAR12,
input wire [VAR8-1:0] VAR14,
i... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlrtn/sky130_fd_sc_hd__dlrtn_4.v | 2,358 | module MODULE1 (
VAR5 ,
VAR2,
VAR4 ,
VAR1 ,
VAR8 ,
VAR7 ,
VAR10 ,
VAR6
);
output VAR5 ;
input VAR2;
input VAR4 ;
input VAR1 ;
input VAR8 ;
input VAR7 ;
input VAR10 ;
input VAR6 ;
VAR9 VAR3 (
.VAR5(VAR5),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR6(VAR6)
);
endmodule
module MODU... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a221oi/sky130_fd_sc_ls__a221oi.behavioral.pp.v | 2,207 | module MODULE1 (
VAR18 ,
VAR1 ,
VAR9 ,
VAR10 ,
VAR17 ,
VAR20 ,
VAR4,
VAR13,
VAR6 ,
VAR11
);
output VAR18 ;
input VAR1 ;
input VAR9 ;
input VAR10 ;
input VAR17 ;
input VAR20 ;
input VAR4;
input VAR13;
input VAR6 ;
input VAR11 ;
wire VAR2 ;
wire VAR3 ;
wire VAR5 ;
wire VAR19;
and VAR16 (VAR2 , VAR10, VAR17 );
and VAR8 (V... | apache-2.0 |
ehliar/schematic_gui | mult.v | 1,271 | module MODULE1 #(parameter VAR2 = 1) (input wire clk,
input wire [VAR2:0] VAR4,VAR1,
output reg [VAR2:0] VAR3); | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a31oi/sky130_fd_sc_hd__a31oi.blackbox.v | 1,362 | module MODULE1 (
VAR9 ,
VAR1,
VAR6,
VAR8,
VAR7
);
output VAR9 ;
input VAR1;
input VAR6;
input VAR8;
input VAR7;
supply1 VAR2;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6T_CKINVDC_SRAM_TT_210930.v | 11,817 | module MODULE1 (VAR1, VAR2);
output VAR1;
input VAR2;
not (VAR1, VAR2); | bsd-3-clause |
markusC64/1541ultimate2 | fpga/nios/nios/synthesis/submodules/alt_mem_ddrx_rdata_path.v | 51,123 | module MODULE1
parameter
VAR272 = 8,
VAR154 = 2,
VAR59 = 3, VAR110 = 3,
VAR35 = 32,
VAR208 = 5,
VAR267 = 2,
VAR180 = 3,
VAR266 = 13,
VAR163 = 10,
VAR185 = 4, VAR50 = "VAR18", VAR252 = 2,
VAR36 = 3,
VAR103 = 2,
VAR159 = 1,
VAR39 = 8,
VAR32 = 3,
VAR244 = 1,
VAR269 = 1,
VAR140 = 1,
VAR72 = 5,
VAR201 = 2,
VAR31 = 9,
VAR30 ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sedfxbp/sky130_fd_sc_ms__sedfxbp_2.v | 2,564 | module MODULE1 (
VAR6 ,
VAR7 ,
VAR10 ,
VAR5 ,
VAR12 ,
VAR11 ,
VAR3 ,
VAR9,
VAR4,
VAR2 ,
VAR13
);
output VAR6 ;
output VAR7 ;
input VAR10 ;
input VAR5 ;
input VAR12 ;
input VAR11 ;
input VAR3 ;
input VAR9;
input VAR4;
input VAR2 ;
input VAR13 ;
VAR1 VAR8 (
.VAR6(VAR6),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR12(VAR... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/cmp/rtl/dram3_ddr3_rptr.v | 4,414 | module MODULE1(
VAR20, VAR33, VAR13,
VAR6, VAR4, VAR12,
VAR7, VAR3,
VAR16, VAR23,
VAR29, VAR10, VAR35,
VAR26, VAR22, VAR25,
VAR30, VAR34,
VAR1, VAR24, VAR14,
VAR18, VAR19, VAR5,
VAR36, VAR11, VAR31,
VAR2, VAR21, VAR9,
VAR27, VAR32, VAR28, VAR15,
VAR8, VAR17
);
output VAR20;
output [31:0] VAR33;
output [255:0] VAR13;
ou... | gpl-2.0 |
Feuerwerk/fpgaNES | master_reconfig/altera_pll_reconfig_core.v | 85,089 | module MODULE2
parameter VAR270 = 64,
parameter VAR13 = "VAR159 VAR262",
parameter VAR110 = 6,
parameter VAR228 = 32,
parameter VAR205 = 9,
parameter VAR25 = 32,
parameter VAR203 = 512
) (
input wire VAR75,
input wire VAR67,
output wire [VAR270-1:0] VAR257,
input wire [VAR270-1:0] VAR247,
output wire [31:0] VAR80,
outp... | gpl-3.0 |
ipburbank/Raster-Laser-Projector | src/Raster_Laser_Projector/synthesis/submodules/Raster_Laser_Projector_mm_interconnect_0.v | 15,025 | module MODULE1 (
input wire VAR68, input wire VAR5, input wire VAR40, input wire [31:0] VAR79, output wire VAR37, input wire VAR34, input wire [7:0] VAR60, output wire [18:0] VAR76, output wire VAR59, input wire [7:0] VAR39, output wire [7:0] VAR54, output wire VAR62, output wire VAR57 );
wire VAR42; wire [7:0] VAR58; ... | gpl-3.0 |
antmicro/yosys | techlibs/xilinx/xc6s_brams_map.v | 5,699 | module \VAR7 (VAR36, VAR77, VAR46, VAR68, VAR6, VAR55, VAR11, VAR61);
parameter VAR64 = 1;
parameter VAR25 = 1;
parameter [9215:0] VAR14 = 9216'VAR8;
input VAR36;
input VAR77;
input [7:0] VAR46;
output [35:0] VAR68;
input VAR6;
input [7:0] VAR55;
input [35:0] VAR11;
input [3:0] VAR61;
wire [12:0] VAR43 = {VAR46, 5'b0};... | isc |
cpulabs/gci-std-display | rtl/display_controller/gci_std_display_vram_interface.v | 6,784 | module MODULE1 #(
parameter VAR55 = 19
)(
input wire VAR28,
input wire VAR16,
input wire VAR19,
input wire VAR31,
output wire VAR26,
input wire VAR52,
input wire VAR8,
output wire VAR56,
input wire VAR49,
input wire [VAR55-1:0] VAR41,
input wire [31:0] VAR15,
output wire VAR58,
input wire VAR60,
output wire [31:0] VAR2... | bsd-2-clause |
Elphel/x393_sata | ahci/ahci_dma.v | 36,885 | module MODULE1 (
input VAR112, input VAR152,
input VAR29, input VAR103, input [31:4] VAR209, input VAR188, input [15:0] VAR100, input VAR48, input VAR25, input VAR155, input VAR174,
input [3:0] VAR186,
input [3:0] VAR199,
input VAR203,
input VAR84,
output reg VAR161, input [ 4:0] VAR219, input [ 1:0] VAR36, output reg ... | gpl-3.0 |
marmolejo/zet | cores/wb_abrg/wb_abrg_reg.v | 5,097 | module MODULE1 (
input VAR3,
input VAR12,
input [19:1] VAR25,
input [15:0] VAR29,
output [15:0] VAR8,
input [ 1:0] VAR26,
input VAR11,
input VAR10,
input VAR41,
input VAR42,
output VAR49,
input VAR38,
output reg [19:1] VAR16,
output reg [15:0] VAR47,
input [15:0] VAR2,
output reg [ 1:0] VAR31,
output reg VAR22,
output ... | gpl-3.0 |
Elphel/x353 | memctrl353/sdram_phase.v | 5,478 | module MODULE1 ( VAR13, VAR25, VAR12, VAR19, VAR16;
input VAR18;
input VAR2, VAR21, VAR1, VAR22;
output VAR3, VAR23, VAR11, VAR15;
output [ 1:0] VAR8;
wire VAR17 = VAR13;
reg [ 1:0] VAR8;
reg VAR3;
reg [1:0] VAR9;
reg VAR11;
reg VAR15;
reg VAR20, VAR6,VAR5,VAR7;
reg VAR4, VAR10, VAR24, VAR14;
always @ (negedge VAR19) b... | gpl-3.0 |
chriswynnyk/american-put-verilog | american_put_stratix/src/fp_compare_v1.v | 21,429 | module MODULE1
(
VAR76,
VAR5,
VAR67,
VAR84) ;
output VAR76;
input VAR5;
input [63:0] VAR67;
input [63:0] VAR84;
reg VAR23;
wire VAR78;
wire VAR4;
wire VAR14;
wire VAR49;
wire VAR34;
wire VAR52;
wire VAR51;
wire VAR35;
wire VAR87;
wire VAR73;
wire VAR33;
wire VAR55;
wire VAR13;
wire VAR22;
wire VAR81;
wire VAR15;
wire V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/edfxbp/sky130_fd_sc_hs__edfxbp.pp.symbol.v | 1,414 | module MODULE1 (
input VAR4 ,
output VAR6 ,
output VAR3 ,
input VAR5 ,
input VAR7 ,
input VAR1,
input VAR2
);
endmodule | apache-2.0 |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/Source/PEAKFINDER.v | 5,573 | module MODULE1 # (
parameter VAR7 = 7'd65)(
input VAR10,
input VAR34,
input VAR48,
input VAR22,
input VAR46,
input [59:0] VAR1,
input [49:0] VAR36,
input [13:0] VAR57,
input VAR51,
input VAR25,
output VAR47,
output [109:0] VAR58, VAR16, VAR42,
output [13:0] VAR38
);
wire VAR14, VAR50, VAR39;
assign VAR50 = VAR4 > VAR23... | gpl-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/settings_fifo_ctrl.v | 13,938 | module MODULE1
parameter VAR37 = 1, parameter VAR39 = 0, parameter VAR16 = 1, parameter VAR42 = 0 )
(
input VAR107, input reset, input VAR58,
input [63:0] VAR77,
input VAR10,
input [35:0] VAR95, input VAR103, output VAR110,
output [35:0] VAR53, output VAR45, input VAR6,
output VAR43, output [7:0] addr, output [31:0] VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlxbp/sky130_fd_sc_hs__dlxbp.behavioral.pp.v | 1,912 | module MODULE1 (
VAR10,
VAR9,
VAR13 ,
VAR5 ,
VAR12 ,
VAR15
);
input VAR10;
input VAR9;
output VAR13 ;
output VAR5 ;
input VAR12 ;
input VAR15;
wire VAR11 VAR1;
wire VAR11 VAR4 ;
reg VAR3 ;
wire VAR11 ;
wire VAR8 ;
VAR6 VAR14 (VAR11 , VAR4, VAR1, VAR3, VAR10, VAR9);
buf VAR2 (VAR13 , VAR11 );
not VAR7 (VAR5 , VAR11 );
a... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a32o/sky130_fd_sc_lp__a32o_0.v | 2,469 | module MODULE2 (
VAR5 ,
VAR7 ,
VAR1 ,
VAR8 ,
VAR12 ,
VAR10 ,
VAR11,
VAR3,
VAR2 ,
VAR4
);
output VAR5 ;
input VAR7 ;
input VAR1 ;
input VAR8 ;
input VAR12 ;
input VAR10 ;
input VAR11;
input VAR3;
input VAR2 ;
input VAR4 ;
VAR9 VAR6 (
.VAR5(VAR5),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR12(VAR12),
.VAR10(VAR10),
.VAR1... | apache-2.0 |
CMU-SAFARI/NOCulator | hring/hw/buffered/src/vcr_vc_alloc_mac.v | 6,395 | module MODULE1
(clk, reset, VAR24, VAR31, VAR16, VAR17,
VAR32, VAR23, VAR5, VAR30, VAR28);
parameter VAR29 = 2;
parameter VAR25 = 2;
localparam VAR22 = VAR29 * VAR25;
parameter VAR13 = 1;
localparam VAR20 = VAR22 * VAR13;
parameter VAR2 = 5;
localparam VAR7 = VAR18(VAR2);
parameter VAR33 = VAR3;
parameter VAR19 = VAR11... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor4b/sky130_fd_sc_hd__nor4b.blackbox.v | 1,322 | module MODULE1 (
VAR9 ,
VAR7 ,
VAR3 ,
VAR5 ,
VAR4
);
output VAR9 ;
input VAR7 ;
input VAR3 ;
input VAR5 ;
input VAR4;
supply1 VAR1;
supply0 VAR2;
supply1 VAR8 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp.behavioral.v | 2,771 | module MODULE1 (
VAR12,
VAR11 ,
VAR10,
VAR28
);
output VAR12;
input VAR11 ;
input VAR10;
input VAR28 ;
supply1 VAR26;
supply0 VAR13;
supply1 VAR6 ;
supply0 VAR7 ;
wire VAR21 ;
wire VAR17 ;
wire VAR27 ;
wire VAR4 ;
wire VAR20 ;
wire VAR14 ;
wire VAR1;
wire VAR25 ;
reg VAR9 ;
wire VAR3 ;
wire VAR19 ;
wire VAR22 ;
not VAR... | apache-2.0 |
mda-ut/SubZero | fpga/fpga_hw/top_level/DE0_Nano_SOPC/synthesis/submodules/SPI_3WIRE.v | 5,758 | module MODULE1(
clk,
VAR22,
VAR25,
VAR1,
VAR3,
VAR53,
VAR23,
VAR9,
VAR7,
VAR38,
VAR28,
VAR17,
VAR31,
VAR33,
VAR24
);
parameter VAR44 = 10;
parameter VAR34 = 1;
input clk;
input VAR22;
input VAR25;
output VAR1;
input [5:0] VAR3;
input VAR53; input [3:0] VAR23; input VAR9;
input [7:0] VAR7;
input [7:0] VAR38;
input [7:0]... | mit |
ultraembedded/riscv | core/riscv/riscv_mmu.v | 20,844 | module MODULE1
parameter VAR57 = 32'h80000000
,parameter VAR83 = 32'h8fffffff
,parameter VAR84 = 1
)
(
input VAR87
,input VAR14
,input [ 1:0] VAR107
,input VAR48
,input VAR94
,input VAR16
,input [ 31:0] VAR90
,input VAR11
,input VAR113
,input VAR74
,input [ 31:0] VAR114
,input [ 1:0] VAR63
,input VAR50
,input VAR52
,in... | bsd-3-clause |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/example_design/rtl/phy/phy_dq_iob.v | 23,052 | module MODULE1 #
(
parameter VAR58 = 100, parameter VAR141 = 5, parameter VAR47 = "VAR37", parameter VAR77 = "VAR113", parameter VAR166 = 300.0, parameter VAR178 = "VAR90", parameter VAR95 = "VAR113", parameter VAR18 = "VAR190" )
(
input VAR163,
input clk,
input rst,
input VAR105,
input VAR108,
input VAR80,
input [4:0]... | lgpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/up_fft.v | 9,160 | module MODULE1 (
clk,
rst,
VAR17,
VAR41,
VAR13,
VAR15,
VAR19,
VAR14,
VAR22,
VAR16,
VAR31,
VAR48,
VAR51,
VAR37,
VAR12);
parameter VAR38 = 32'h00040062;
parameter VAR36 = 0;
input clk;
output rst;
output VAR17;
output [31:0] VAR41;
output VAR13;
output [15:0] VAR15;
input [19:0] VAR19;
input VAR14;
input VAR22;
input VAR... | mit |
cafe-alpha/wascafe | v11/fpga_firmware/wasca/synthesis/submodules/altera_onchip_flash.v | 11,138 | module MODULE1 (
VAR24,
VAR22,
VAR54,
VAR9,
VAR1,
VAR108,
VAR47,
VAR18,
VAR78,
VAR55,
VAR34,
VAR39,
VAR37,
VAR52,
VAR99
);
parameter VAR94 = "VAR109 10";
parameter VAR88 = "VAR92";
parameter VAR33 = "VAR31";
parameter VAR72 = "VAR31";
parameter VAR86 = "VAR31";
parameter VAR75 = "";
parameter VAR66 = "08";
parameter VA... | gpl-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_3L_022bits.v | 1,917 | module MODULE2 (
clk,
VAR12, VAR8, VAR17, VAR15, VAR31, VAR4, VAR6, VAR34,
sum,
);
input clk;
input [VAR10+0-1:0] VAR12, VAR8, VAR17, VAR15, VAR31, VAR4, VAR6, VAR34;
output [VAR10 :0] sum;
reg [VAR10 :0] sum;
wire [VAR10+3-1:0] VAR20;
wire [VAR10+2-1:0] VAR18, VAR1;
wire [VAR10+1-1:0] VAR22, VAR23, VAR24, VAR33;
reg [... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv3sd3/sky130_fd_sc_ms__clkdlyinv3sd3.behavioral.pp.v | 1,867 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR9,
VAR11,
VAR5 ,
VAR12
);
output VAR4 ;
input VAR2 ;
input VAR9;
input VAR11;
input VAR5 ;
input VAR12 ;
wire VAR1 ;
wire VAR3;
not VAR10 (VAR1 , VAR2 );
VAR6 VAR8 (VAR3, VAR1, VAR9, VAR11);
buf VAR7 (VAR4 , VAR3 );
endmodule | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/rtl/Altera/bidirbuf.v | 20,002 | module MODULE1
(
VAR34,
VAR47,
VAR36,
VAR31) ;
input [15:0] VAR34;
inout [15:0] VAR47;
output [15:0] VAR36;
input [15:0] VAR31;
wire [15:0] VAR43;
wire [15:0] VAR27;
wire [15:0] VAR57;
wire [15:0] VAR50;
wire [15:0] VAR3;
VAR21 VAR32
(
.VAR51(VAR43[0:0]),
.VAR20(VAR27[0:0])
,
.VAR17(1'b0),
.VAR19(1'b0)
);
VAR32.VAR2 =... | gpl-3.0 |
TUM-LIS/faultify | software/host/davester_combinational_extractor/c432.v | 6,849 | module MODULE1 (VAR20,VAR201,VAR299,VAR289,VAR107,VAR286,VAR315,VAR19,VAR100,VAR223,
VAR331,VAR127,VAR116,VAR261,VAR174,VAR112,VAR157,VAR56,VAR243,VAR301,
VAR48,VAR182,VAR326,VAR142,VAR221,VAR143,VAR37,VAR105,VAR130,VAR8,
VAR178,VAR334,VAR68,VAR166,VAR247,VAR23,VAR307,VAR67,VAR169,VAR191,
VAR246,VAR254,VAR323);
input V... | gpl-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/acl_fp_custom_round_post_double.v | 7,151 | module MODULE1(
VAR14, VAR21, VAR15, VAR19, VAR25, VAR27, VAR8, VAR4,
VAR24, VAR18, VAR20, VAR32, enable);
parameter VAR11 = 1;
parameter VAR31 = 0;
parameter VAR33 = 1;
parameter VAR35 = 0;
parameter VAR22 = 1;
parameter VAR16 = 1;
input VAR14, VAR21;
input VAR20, VAR24;
output VAR32, VAR18;
input enable;
input [55:0]... | mit |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie_recv_fifo/pcie_recv_fifo_stub.v | 1,407 | module MODULE1(clk, VAR2, din, VAR5, VAR3, dout, VAR4, VAR1)
;
input clk;
input VAR2;
input [127:0]din;
input VAR5;
input VAR3;
output [127:0]dout;
output VAR4;
output VAR1;
endmodule | gpl-3.0 |
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