repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
davidkoltak/tawas-core | ip/rcn/rtl/rcn_ram.v | 1,455 | module MODULE1
(
input clk,
input rst,
input [68:0] VAR9,
output [68:0] VAR4
);
parameter VAR13 = 0;
wire VAR12;
wire wr;
wire [3:0] VAR8;
wire [23:0] addr;
wire [31:0] VAR11;
wire [31:0] VAR7;
VAR2 #(.VAR1(24'hFF0000), .VAR13(VAR13)) VAR2
(
.rst(rst),
.clk(clk),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR12(VAR12),
.wr(wr),
.VAR8(... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfxtp/sky130_fd_sc_lp__dfxtp_2.v | 2,128 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR5 ,
VAR4,
VAR8,
VAR7 ,
VAR1
);
output VAR6 ;
input VAR2 ;
input VAR5 ;
input VAR4;
input VAR8;
input VAR7 ;
input VAR1 ;
VAR3 VAR9 (
.VAR6(VAR6),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR6 ,
VAR2,
VAR5
);
output VAR6 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/bufinv/sky130_fd_sc_lp__bufinv_8.v | 2,044 | module MODULE2 (
VAR5 ,
VAR3 ,
VAR8,
VAR4,
VAR2 ,
VAR7
);
output VAR5 ;
input VAR3 ;
input VAR8;
input VAR4;
input VAR2 ;
input VAR7 ;
VAR1 VAR6 (
.VAR5(VAR5),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR5,
VAR3
);
output VAR5;
input VAR3;
supply1 VAR8;
supply0 VAR4;... | apache-2.0 |
ipburbank/Raster-Laser-Projector | src/Raster_Laser_Projector/synthesis/submodules/altera_up_video_clipper_counters.v | 6,438 | module MODULE1 (
clk,
reset,
VAR11,
VAR3,
VAR17,
VAR7,
VAR9,
VAR16
);
parameter VAR10 = 640; parameter VAR4 = 480; parameter VAR15 = 9; parameter VAR8 = 8;
parameter VAR2 = 0;
parameter VAR5 = 0;
parameter VAR14 = 0;
parameter VAR18 = 0;
input clk;
input reset;
input VAR11;
output VAR3;
output VAR17;
output VAR7;
outpu... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a221o/sky130_fd_sc_hd__a221o_2.v | 2,444 | module MODULE2 (
VAR6 ,
VAR8 ,
VAR2 ,
VAR11 ,
VAR10 ,
VAR3 ,
VAR9,
VAR12,
VAR4 ,
VAR7
);
output VAR6 ;
input VAR8 ;
input VAR2 ;
input VAR11 ;
input VAR10 ;
input VAR3 ;
input VAR9;
input VAR12;
input VAR4 ;
input VAR7 ;
VAR5 VAR1 (
.VAR6(VAR6),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR11(VAR11),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR9... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand3b/sky130_fd_sc_hs__nand3b.functional.v | 1,889 | module MODULE1 (
VAR13,
VAR2,
VAR12 ,
VAR10 ,
VAR14 ,
VAR4
);
input VAR13;
input VAR2;
output VAR12 ;
input VAR10 ;
input VAR14 ;
input VAR4 ;
wire VAR1 ;
wire VAR5 ;
wire VAR3;
not VAR8 (VAR1 , VAR10 );
nand VAR7 (VAR5 , VAR14, VAR1, VAR4 );
VAR11 VAR9 (VAR3, VAR5, VAR13, VAR2);
buf VAR6 (VAR12 , VAR3 );
endmodule | apache-2.0 |
mbuesch/pyprofibus | phy_fpga/main.v | 4,713 | module MODULE1 #(
parameter VAR84 = 0,
) (
input clk,
input VAR36,
input VAR69,
inout VAR28,
input VAR62,
input VAR11,
input VAR6,
output VAR57,
output VAR35,
output VAR26,
output VAR15,
output VAR67,
output VAR85,
output VAR17,
output VAR14,
);
wire VAR66;
wire VAR79;
wire VAR47;
wire VAR58;
wire VAR22;
wire VAR56;
wi... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1_1.v | 2,037 | module MODULE2 (
VAR4 ,
VAR2 ,
VAR6,
VAR5
);
output VAR4 ;
input VAR2 ;
input VAR6;
input VAR5;
VAR3 VAR1 (
.VAR4(VAR4),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR4,
VAR2
);
output VAR4;
input VAR2;
supply1 VAR6;
supply0 VAR5;
VAR3 VAR1 (
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule | apache-2.0 |
hightoon/Sora | FPGA/SISO/rtl/pcie_userapp_wrapper/pcie_dma_engine/rx_mem_data_fsm.v | 14,656 | module MODULE1(
input wire clk,
input wire rst,
output reg [127:0] VAR15,
output reg [1:0] VAR38, input wire [1:0] VAR37, output reg [2:0] VAR33,
output reg [27:6] VAR18,
output reg VAR7,
input wire VAR26,
input wire VAR30, input wire [27:6] VAR17,
input wire [10:0] VAR39,
input wire VAR10, input wire VAR13,
output reg... | bsd-2-clause |
KestrelComputer/kestrel | cores/MGIA/bench/verilog/T_uxa_mgia.v | 1,256 | module MODULE1;
reg VAR12;
reg VAR4;
reg [15:0] VAR10;
reg ack;
wire VAR7;
wire VAR9;
wire [2:0] VAR11;
wire [2:0] VAR6;
wire [2:1] VAR2;
VAR8 VAR3 (
.VAR12(VAR12),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR5(VAR10),
.VAR1(ack)
);
always begin
VAR12 <= ~VAR12;
VAR10 <= VAR10 ^ ... | mpl-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/fifo/packet_verifier32.v | 1,562 | module MODULE1
(input clk, input reset, input VAR17,
input [35:0] VAR3, input VAR6, output VAR7,
output [31:0] VAR9, output [31:0] VAR16, output [31:0] VAR10, output [31:0] VAR8);
wire [7:0] VAR4;
wire VAR19, VAR11, VAR1, VAR13;
VAR15 VAR5
(.clk(clk), .reset(reset), .VAR17(VAR17),
.VAR14(VAR3), .VAR21(VAR6), .VAR2(VAR7... | gpl-2.0 |
AngelTerrones/Antares | Hardware/verilog/antares_cloz.v | 6,829 | module MODULE1 (
input [31:0] VAR23,
output [5:0] VAR33,
output [5:0] VAR10
);
reg [5:0] VAR33;
reg [5:0] VAR10;
always @ begin
casez (VAR23)
32'VAR25 : VAR10 = 6'd0;
32'VAR21 : VAR10 = 6'd1;
32'VAR14 : VAR10 = 6'd2;
32'VAR11 : VAR10 = 6'd3;
32'VAR28 : VAR10 = 6'd4;
32'VAR34 : VAR10 = 6'd5;
32'VAR29 : VAR10 = 6'd6;
32'... | mit |
GLADICOS/SPACEWIRESYSTEMC | rtl/RTL_VB/fifo_tx.v | 5,073 | module MODULE1
parameter integer VAR13 = 9,
parameter integer VAR2 = 6
)
(
input VAR6, reset, VAR15, VAR17,
input [VAR13-1:0] VAR11,
output reg VAR7,VAR3,VAR12,
output [VAR13-1:0] VAR5,
output reg [VAR2-1:0] counter
);
reg [VAR2-1:0] VAR9;
reg [VAR2-1:0] VAR16;
reg [1:0] VAR10;
reg [1:0] VAR14;
reg [1:0] VAR1;
reg [1:0... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/ebufn/sky130_fd_sc_ls__ebufn_1.v | 2,148 | module MODULE2 (
VAR9 ,
VAR1 ,
VAR4,
VAR2,
VAR7,
VAR8 ,
VAR6
);
output VAR9 ;
input VAR1 ;
input VAR4;
input VAR2;
input VAR7;
input VAR8 ;
input VAR6 ;
VAR3 VAR5 (
.VAR9(VAR9),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR9 ,
VAR1 ,
VAR4
);
output VAR9 ;... | apache-2.0 |
alexforencich/hdg2000 | fpga/lib/axis/rtl/arbiter.v | 4,906 | module MODULE1 #
(
parameter VAR36 = 4,
parameter VAR28 = "VAR23",
parameter VAR4 = "VAR21",
parameter VAR18 = "VAR11"
)
(
input wire clk,
input wire rst,
input wire [VAR36-1:0] request,
input wire [VAR36-1:0] acknowledge,
output wire [VAR36-1:0] VAR31,
output wire VAR16,
output wire [VAR34(VAR36)-1:0] VAR2
);
reg [VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/buf/sky130_fd_sc_hd__buf.blackbox.v | 1,202 | module MODULE1 (
VAR4,
VAR2
);
output VAR4;
input VAR2;
supply1 VAR3;
supply0 VAR6;
supply1 VAR5 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
mlohstroh/bubble-pushers | cpu.v | 2,623 | module MODULE2(clk, rst);
input clk, rst;
wire [31:0] VAR15;
wire VAR10, VAR27, VAR20, VAR38, VAR5, VAR32, VAR29;
wire [1:0] VAR26;
wire [31:0] VAR23;
wire [5:0] VAR40, VAR7;
wire [31:0] VAR21, VAR17;
wire [4:0] VAR41, VAR24;
wire [31:0] VAR8;
wire [31:0] VAR14;
wire [31:0] VAR12;
wire [31:0] VAR4;
wire [31:0] VAR11;
w... | gpl-3.0 |
lerwys/bpm-sw-old-backup | hdl/modules/dbe_wishbone/wb_ethmac/eth_maccontrol.v | 11,621 | module MODULE1 (VAR53, VAR41, VAR28, VAR47, VAR39, VAR14, VAR9, VAR29,
VAR55, VAR24, VAR11, VAR54, VAR1, VAR31, VAR20, VAR32,
VAR42, VAR8, VAR36, VAR44, VAR26, VAR43,
VAR49, VAR51, VAR7, VAR23, VAR30, VAR38, VAR56, VAR2,
VAR52, VAR37, VAR35, VAR33, VAR46,
VAR5, VAR4, VAR25, VAR17, VAR22
);
parameter VAR6 = 1;
input VAR... | lgpl-3.0 |
HFoxtail/Mu80 | trunk/mu80.v | 4,596 | module MODULE1(
input wire VAR43,
output wire [3:0] VAR50,
output wire [4:0] VAR35,
output wire [5:0] VAR21,
output wire [4:0] VAR13,
output wire VAR4,
output wire VAR48
);
assign VAR50 = {VAR23, VAR34, VAR31};
wire [3:0] VAR23;
wire [15:0] address; wire VAR34;
wire VAR47; wire VAR51;
wire VAR53;
wire VAR31 = VAR47;
re... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dlatch_p_pp_pg/sky130_fd_sc_hs__udp_dlatch_p_pp_pg.blackbox.v | 1,337 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR5,
VAR3,
VAR4
);
output VAR2 ;
input VAR1 ;
input VAR5;
input VAR3;
input VAR4;
endmodule | apache-2.0 |
lvd2/ngs | fpga/current/dma/dma_mp3.v | 3,424 | module MODULE1
(
input wire clk,
input wire VAR21,
output wire [ 7:0] VAR34, output wire VAR8, input wire VAR24, input wire VAR2,
input wire [7:0] din, output reg [7:0] dout,
input wire VAR31, input wire VAR3, input wire [1:0] VAR35,
output reg [21:0] VAR11,
input wire [7:0] VAR22, output wire VAR29,
output reg VAR9,
i... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and2/sky130_fd_sc_hdll__and2.functional.v | 1,262 | module MODULE1 (
VAR2,
VAR3,
VAR4
);
output VAR2;
input VAR3;
input VAR4;
wire VAR1;
and VAR5 (VAR1, VAR3, VAR4 );
buf VAR6 (VAR2 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or4bb/sky130_fd_sc_hdll__or4bb.symbol.v | 1,335 | module MODULE1 (
input VAR3 ,
input VAR1 ,
input VAR6,
input VAR8,
output VAR5
);
supply1 VAR7;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfrbp/sky130_fd_sc_hd__sdfrbp.behavioral.v | 2,996 | module MODULE1 (
VAR25 ,
VAR32 ,
VAR2 ,
VAR12 ,
VAR3 ,
VAR14 ,
VAR16
);
output VAR25 ;
output VAR32 ;
input VAR2 ;
input VAR12 ;
input VAR3 ;
input VAR14 ;
input VAR16;
supply1 VAR23;
supply0 VAR5;
supply1 VAR10 ;
supply0 VAR21 ;
wire VAR30 ;
wire VAR28 ;
wire VAR4 ;
reg VAR6 ;
wire VAR9 ;
wire VAR22 ;
wire VAR8 ;
wire... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand2b/sky130_fd_sc_ls__nand2b.pp.blackbox.v | 1,293 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR3 ,
VAR7,
VAR5,
VAR6 ,
VAR1
);
output VAR4 ;
input VAR2 ;
input VAR3 ;
input VAR7;
input VAR5;
input VAR6 ;
input VAR1 ;
endmodule | apache-2.0 |
bangonkali/quartus-sockit | soc_system/synthesis/submodules/altera_avalon_st_bytes_to_packets.v | 7,305 | module MODULE1
parameter VAR2 = 0 )
(
input clk,
input VAR14,
input VAR8,
output reg VAR9,
output reg [7: 0] VAR19,
output reg [VAR16-1: 0] VAR5,
output reg VAR3,
output reg VAR10,
output reg VAR7,
input VAR11,
input [7: 0] VAR12
);
reg VAR6, VAR1, VAR21;
wire VAR15, VAR18, VAR4, VAR13, VAR17;
wire [7:0] VAR20;
assign ... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/led_controller/led_controller.srcs/sources_1/bd/led_controller_design/ip/led_controller_design_auto_pc_0/led_controller_design_auto_pc_0_stub.v | 4,469 | module MODULE1(VAR49, VAR25, VAR7, VAR10,
VAR52, VAR37, VAR45, VAR41, VAR23, VAR58,
VAR57, VAR35, VAR38, VAR53, VAR36, VAR26, VAR40,
VAR9, VAR21, VAR56, VAR46, VAR59, VAR18, VAR14,
VAR13, VAR51, VAR20, VAR32, VAR27, VAR29,
VAR47, VAR28, VAR55, VAR22, VAR3, VAR19, VAR54,
VAR17, VAR12, VAR11, VAR30, VAR44, VAR15,
VAR6, V... | mit |
monotone-RK/FACE | IEICE-Trans/data_compression/8-way_2-tree/src/ip_pcie/source/PCIeGen2x8If128_gtx_cpllpd_ovrd.v | 4,122 | module MODULE1 (
input VAR2,
output VAR5,
output VAR4
);
reg [95:0] VAR1 = 96'hFFFFFFFFFFFFFFFFFFFFFFFF;
reg [127:0] VAR3 = 128'h000000000000000000000000000000FF;
always @(posedge VAR2)
begin
VAR1 <= {VAR1[94:0], 1'b0};
VAR3 <= {VAR3[126:0], 1'b0};
end
assign VAR5 = VAR1[95];
assign VAR4 = VAR3[127];
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a221oi/sky130_fd_sc_ms__a221oi.blackbox.v | 1,403 | module MODULE1 (
VAR6 ,
VAR10,
VAR4,
VAR3,
VAR5,
VAR2
);
output VAR6 ;
input VAR10;
input VAR4;
input VAR3;
input VAR5;
input VAR2;
supply1 VAR1;
supply0 VAR9;
supply1 VAR8 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axilite_conv.v | 9,139 | module MODULE1 #
(
parameter VAR30 = "VAR41",
parameter integer VAR59 = 1,
parameter integer VAR25 = 32,
parameter integer VAR43 = 32,
parameter integer VAR19 = 1,
parameter integer VAR16 = 1,
parameter integer VAR18 = 1,
parameter integer VAR10 = 1
)
(
input wire VAR62,
input wire VAR72,
input wire [VAR59-1:0] VAR69,
... | gpl-3.0 |
bargei/NoC264 | NoC264_2x2/module_outport_encoder.v | 2,656 | module MODULE1(VAR2,
VAR1);
input [4 : 0] VAR2;
output [3 : 0] VAR1;
wire [3 : 0] VAR1;
assign VAR1 =
{ VAR2[0] || VAR2[1] ||
VAR2[2] ||
VAR2[3] ||
VAR2[4],
VAR2[0] ?
3'd0 :
(VAR2[1] ?
3'd1 :
(VAR2[2] ?
3'd2 :
(VAR2[3] ? 3'd3 : 3'd4))) } ;
endmodule | mit |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/pic.v | 7,508 | module MODULE1
(input VAR3, input VAR6, input VAR21, input VAR20,
input [2:0] VAR8,
input VAR14,
input [31:0] VAR12,
output reg [31:0] VAR15,
output reg VAR17,
output reg VAR23,
input [31:0] irq
);
reg [31:0] VAR5, VAR9, VAR11, VAR13; reg [31:0] VAR2, VAR24;
always @(posedge VAR3)
VAR2 <= irq;
always @(posedge VAR3)
VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or3b/sky130_fd_sc_lp__or3b.functional.pp.v | 1,951 | module MODULE1 (
VAR13 ,
VAR6 ,
VAR10 ,
VAR5 ,
VAR8,
VAR3,
VAR2 ,
VAR14
);
output VAR13 ;
input VAR6 ;
input VAR10 ;
input VAR5 ;
input VAR8;
input VAR3;
input VAR2 ;
input VAR14 ;
wire VAR15 ;
wire VAR7 ;
wire VAR1;
not VAR4 (VAR15 , VAR5 );
or VAR12 (VAR7 , VAR10, VAR6, VAR15 );
VAR9 VAR16 (VAR1, VAR7, VAR8, VAR3);
b... | apache-2.0 |
bluespec/Flute | builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkFPR_RegFile.v | 7,018 | module MODULE1(VAR58,
VAR61,
VAR52,
VAR40,
VAR76,
VAR45,
VAR21,
VAR7,
VAR13,
VAR50,
VAR2,
VAR30,
VAR29,
VAR66,
VAR68,
VAR62,
VAR46);
input VAR58;
input VAR61;
input VAR52;
output VAR40;
input VAR76;
output VAR45;
input [4 : 0] VAR21;
output [63 : 0] VAR7;
input [4 : 0] VAR13;
output [63 : 0] VAR50;
input [4 : 0] VAR2;
... | apache-2.0 |
toomij/DE2Labs | Lab3/lab3_part3.v | 2,150 | module MODULE2 (VAR6, VAR3, VAR7);
input [1:0] VAR6;
output [1:0] VAR3, VAR7;
assign VAR3 = VAR6;
wire VAR10;
MODULE3 VAR12(VAR6[1],VAR6[0],VAR7[0]);
endmodule
module MODULE3(VAR4, VAR11, VAR10);
input VAR4, VAR11;
output VAR10;
wire VAR16;
MODULE1 VAR15 (~VAR4, VAR11, VAR16);
MODULE1 VAR13 (VAR4, VAR16, VAR10);
endmod... | gpl-2.0 |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/Aurora_MGT/Pcore/mgt_fifo1_v1_00_a/hdl/verilog/channel_init_sm.v | 10,907 | module MODULE1
(
VAR26,
VAR37,
VAR29,
VAR38,
VAR3,
VAR1,
VAR8,
VAR6,
VAR27,
VAR22,
VAR47,
VAR40,
VAR42
);
input VAR26;
output VAR37;
input VAR29;
input [0:3] VAR38;
input VAR3;
output VAR1;
input VAR8;
input VAR6;
output VAR27;
output VAR22;
input VAR47;
output VAR40;
input VAR42;
reg VAR22;
reg VAR43;
reg [0:15] VAR20... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_isolatch_pp_pkg_sn/sky130_fd_sc_hs__udp_isolatch_pp_pkg_sn.symbol.v | 1,525 | module MODULE1 (
input VAR4 ,
output VAR6 ,
input VAR3 ,
input VAR7 ,
input VAR5,
input VAR1 ,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfstp/sky130_fd_sc_hd__sdfstp.functional.v | 1,938 | module MODULE1 (
VAR8 ,
VAR15 ,
VAR2 ,
VAR9 ,
VAR5 ,
VAR16
);
output VAR8 ;
input VAR15 ;
input VAR2 ;
input VAR9 ;
input VAR5 ;
input VAR16;
wire VAR14 ;
wire VAR7 ;
wire VAR6;
not VAR12 (VAR7 , VAR16 );
VAR3 VAR13 (VAR6, VAR2, VAR9, VAR5 );
VAR4 VAR11 VAR10 (VAR14 , VAR6, VAR15, VAR7);
buf VAR1 (VAR8 , VAR14 );
endmo... | apache-2.0 |
archlabo/Frix | fpga/de2-115/rtl/clock/clk_wiz_0_bb.v | 12,330 | module MODULE1 (
VAR2,
VAR1,
VAR4,
VAR3);
input VAR2;
output VAR1;
output VAR4;
output VAR3;
endmodule | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/tapvgnd/sky130_fd_sc_ms__tapvgnd.functional.pp.v | 1,230 | module MODULE1 (
VAR4,
VAR2,
VAR1 ,
VAR3
);
input VAR4;
input VAR2;
input VAR1 ;
input VAR3 ;
endmodule | apache-2.0 |
FAST-Switch/fast | lib/hardware/pipeline/IPE_IF_OPENFLOW/mac_core/altera_tse_rgmii_module.v | 8,713 | module MODULE1 ( VAR31,
VAR15,
VAR58,
VAR37,
VAR61,
VAR3,
VAR26,
VAR17,
VAR22,
VAR51,
VAR48,
VAR11,
VAR13,
VAR56,
VAR34,
VAR40,
VAR9,
VAR52,
VAR6,
VAR33,
VAR20,
VAR50,
VAR54
);
parameter VAR41 = 3;
output [ 3: 0] VAR56;
output [ 7: 0] VAR34;
output [ 3: 0] VAR40;
output VAR9;
output VAR52;
output VAR6;
output VAR33;
ou... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a211oi/sky130_fd_sc_ls__a211oi.symbol.v | 1,375 | module MODULE1 (
input VAR4,
input VAR7,
input VAR2,
input VAR1,
output VAR9
);
supply1 VAR8;
supply0 VAR6;
supply1 VAR3 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_hdmi_rx_v1_00_a/hdl/verilog/axi_hdmi_rx_core.v | 13,122 | module MODULE1 (
VAR37,
VAR44,
VAR53, VAR56, VAR22, VAR8, VAR52, VAR39, VAR19, VAR57, VAR50, VAR32, VAR16,
VAR14,
VAR65,
VAR36,
VAR12,
VAR33,
VAR38,
VAR58,
VAR27,
VAR26,
VAR11);
input VAR37;
input [15:0] VAR44;
output VAR53;
output VAR56;
output [15:0] VAR22;
output VAR8;
output VAR52;
output [15:0] VAR39;
output VAR19... | mit |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_10.v | 10,406 | module MODULE5 (
clk,
reset,
VAR5,
VAR23,
VAR28,
VAR2,
VAR63
);
parameter VAR48 = 18;
parameter VAR26 = 10;
parameter VAR61 = 5;
localparam VAR18 = 15;
input clk;
input reset;
input VAR5;
input VAR23;
input [VAR48-1:0] VAR28; output VAR2;
output [VAR48-1:0] VAR63;
localparam VAR64 = 18; localparam VAR1 = 36; localparam... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a41o/sky130_fd_sc_ms__a41o_2.v | 2,426 | module MODULE1 (
VAR2 ,
VAR8 ,
VAR4 ,
VAR7 ,
VAR11 ,
VAR5 ,
VAR12,
VAR10,
VAR9 ,
VAR3
);
output VAR2 ;
input VAR8 ;
input VAR4 ;
input VAR7 ;
input VAR11 ;
input VAR5 ;
input VAR12;
input VAR10;
input VAR9 ;
input VAR3 ;
VAR6 VAR1 (
.VAR2(VAR2),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR12(... | apache-2.0 |
thurday/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_LED_Clock.v | 3,587 | module MODULE2(VAR1, VAR6, VAR7);
input VAR1;
output VAR6;
input VAR7;
reg[9:0] VAR4;
reg[9:0] VAR2;
reg[9:0] VAR3;
reg VAR5;
assign VAR6 = VAR5;
always @(posedge VAR1 or posedge VAR7) begin
if (VAR7) begin
VAR4 <= 1'b0;
VAR2 <= 1'b0;
VAR3 <= 1'b0;
VAR5 <= 1'b0;
end
else begin
if (VAR3 < 448) begin
if (VAR2 < 1000) beg... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlrbn/sky130_fd_sc_ls__dlrbn.blackbox.v | 1,405 | module MODULE1 (
VAR2 ,
VAR3 ,
VAR6,
VAR8 ,
VAR1
);
output VAR2 ;
output VAR3 ;
input VAR6;
input VAR8 ;
input VAR1 ;
supply1 VAR4;
supply0 VAR5;
supply1 VAR7 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
CospanDesign/nysa-artemis-pcie-platform | artemis_pcie/slave/wb_artemis_pcie_platform/rtl/c/pcie_bram_s6.v | 5,968 | module MODULE1 #(
parameter VAR1 = 0, parameter VAR2 = 0 ) (
input VAR11, input VAR7,
input VAR15, input [11:0] VAR10, input [VAR2 - 1:0] VAR6,
input VAR13, input VAR14, input [11:0] VAR4,
output [VAR2 - 1:0] VAR8 );
localparam VAR5 = ((VAR2 == 4) ? 11 :
(VAR2 == 9) ? 10 :
(VAR2 == 18) ? 9 :
8
);
localparam VAR12 = ((V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand2b/sky130_fd_sc_ms__nand2b.behavioral.v | 1,452 | module MODULE1 (
VAR5 ,
VAR4,
VAR12
);
output VAR5 ;
input VAR4;
input VAR12 ;
supply1 VAR10;
supply0 VAR9;
supply1 VAR2 ;
supply0 VAR1 ;
wire VAR8 ;
wire VAR11;
not VAR7 (VAR8 , VAR12 );
or VAR3 (VAR11, VAR8, VAR4 );
buf VAR6 (VAR5 , VAR11 );
endmodule | apache-2.0 |
GSejas/Karatsuba_FPU | FPGA_FLOW/Proyectos Funcionales Francis Jeffrey/CORDICO/CORDICO.srcs/sources_1/imports/Floating-Point-Unit-master/Coprocesador_CORDIC_RTL/FPU_Interface_and_NaN/FPU_Interface.v | 7,979 | module MODULE1 #(parameter VAR102 = 64, VAR36 = 11, VAR84 = 52, VAR96 = 55, VAR43 = 6, VAR69=12)
(
input wire clk,
input wire rst,
input wire VAR26,
input wire VAR67,
input wire [2:0] VAR68,
input wire [1:0] VAR101,
input wire [VAR102-1:0] VAR65,
input wire [1:0] VAR79,
output wire VAR8,
output wire VAR47,
output wire ... | gpl-3.0 |
rkrajnc/minimig-de1 | rtl/or1200/or1200_spram_1024x32.v | 9,391 | module MODULE1(
VAR4, VAR17, VAR48,
clk, rst, VAR13, VAR24, VAR12, addr, VAR20, VAR18
);
parameter VAR54 = 10;
parameter VAR45 = 32;
input VAR4;
input [VAR15 - 1:0] VAR48;
output VAR17;
input clk; input rst; input VAR13; input VAR24; input VAR12; input [VAR54-1:0] addr; input [VAR45-1:0] VAR20; output [VAR45-1:0] VAR18... | gpl-3.0 |
The7thPres/CFTP | CFTP_Sat/CFTP_Sat.srcs/sources_1/imports/Sources-On_Sat/MIPS32/Hazard_Detection.v | 8,634 | module MODULE1(
input [7:0] VAR55,
input [4:0] VAR68,
input [4:0] VAR16,
input [4:0] VAR56,
input [4:0] VAR58,
input [4:0] VAR44,
input [4:0] VAR39,
input [4:0] VAR24,
input VAR36,
input VAR33,
input VAR15,
input VAR13,
input VAR45,
input VAR47, input VAR61,
input VAR23,
input VAR48, input VAR59,
input VAR31,
input VAR... | lgpl-3.0 |
GLADICOS/SPACEWIRESYSTEMC | rtl/RTL_VB/top_spw_ultra_light.v | 3,548 | module MODULE1(
input VAR11,
input VAR40,
input VAR35,
input VAR25,
input VAR49,
input VAR32,
input VAR10,
input VAR69,
input VAR45,
input [8:0] VAR66,
input VAR58,
input [7:0] VAR61,
input VAR28,
input VAR55,
output [8:0] VAR44,
output VAR12,
output [7:0] timeout,
output VAR68,
output VAR2,
output VAR43,
output VAR18,... | gpl-3.0 |
Gifts/descrypt-ztex-bruteforcer | user_cores/des/src/xor_48.v | 1,285 | module MODULE1(
input [47:0] VAR2,
input [59:0] VAR1,
output reg [47:0] VAR3,
input VAR4
);
wire [47:0] VAR5;
always @(posedge VAR4)
begin
VAR3 <= VAR5 ^ VAR1[47:0];
end
assign VAR5 = {(VAR2[47:36] & (~VAR1[59:48])) | (VAR1[59:48] & VAR2[23:12]), VAR2[35:24], (VAR2[23:12] & (~VAR1[59:48])) | (VAR1[59:48] & VAR2[47:36])... | gpl-3.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/rw_manager_ram_csr.v | 2,433 | module MODULE1 #(
parameter VAR8 = 32,
parameter VAR5 = 2,
parameter VAR23 = 4
) (
input VAR10,
input VAR4,
input VAR14,
input VAR9,
input VAR15,
input [(VAR8-1):0] VAR18,
input [(VAR5-1):0] VAR20,
input [(VAR5-1):0] VAR12,
output reg [(VAR8-1):0] VAR1,
output reg VAR24
);
localparam integer VAR11 = VAR8*VAR23;
reg [VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a22o/sky130_fd_sc_hd__a22o_1.v | 2,339 | module MODULE1 (
VAR3 ,
VAR4 ,
VAR2 ,
VAR7 ,
VAR9 ,
VAR10,
VAR6,
VAR11 ,
VAR5
);
output VAR3 ;
input VAR4 ;
input VAR2 ;
input VAR7 ;
input VAR9 ;
input VAR10;
input VAR6;
input VAR11 ;
input VAR5 ;
VAR1 VAR8 (
.VAR3(VAR3),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR11(VAR11),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o221a/sky130_fd_sc_ls__o221a.pp.blackbox.v | 1,428 | module MODULE1 (
VAR1 ,
VAR8 ,
VAR9 ,
VAR7 ,
VAR5 ,
VAR10 ,
VAR4,
VAR3,
VAR2 ,
VAR6
);
output VAR1 ;
input VAR8 ;
input VAR9 ;
input VAR7 ;
input VAR5 ;
input VAR10 ;
input VAR4;
input VAR3;
input VAR2 ;
input VAR6 ;
endmodule | apache-2.0 |
bluespec/Flute | builds/RV64ACIMU_Flute_verilator/Verilog_RTL/mkCSR_MIE.v | 3,367 | module MODULE1(VAR7,
VAR22,
VAR6,
VAR10,
VAR17,
VAR18,
VAR13,
VAR23);
input VAR7;
input VAR22;
input VAR6;
output [63 : 0] VAR10;
input [27 : 0] VAR17;
input [63 : 0] VAR18;
input VAR13;
output [63 : 0] VAR23;
wire [63 : 0] VAR23, VAR10;
reg [11 : 0] VAR4;
wire [11 : 0] VAR12;
wire VAR3;
wire VAR20,
VAR24,
VAR8,
VAR5;
... | apache-2.0 |
yahniukov/FIFO_Verilog | src/design/wr_memory.v | 1,370 | module MODULE1 ( VAR3, VAR10, VAR8, VAR4,
VAR9,
VAR5,
reset );
parameter VAR2 = 1;
parameter VAR6 = 3;
parameter VAR1 = 8;
input wire [VAR2 - 1 : 0] VAR3;
input wire [VAR6 - 1 : 0] VAR4;
input wire VAR10, VAR8;
input wire VAR5;
output reg [VAR1 - 1 : 0] VAR9;
input wire reset;
reg [VAR2 - 1 : 0] memory [VAR1 - 1 : 0];
... | apache-2.0 |
lneuhaus/pyrpl | pyrpl/fpga/rtl/red_pitaya_lpf_block.v | 3,610 | module MODULE1
parameter VAR9 = 4, parameter VAR17 = 14, parameter VAR15 = 10 )
(
input VAR5,
input VAR4 ,
input [VAR9:0] VAR6,
input VAR18,
input VAR16,
input signed [VAR17-1:0] VAR1,
output signed [VAR17-1:0] VAR8
);
(VAR14 < 2) ? 1 : \
(VAR14 < 4) ? 2 : \
(VAR14 < 8) ? 3 : \
(VAR14 < 16) ? 4 : \
(VAR14 < 32) ? 5 : \... | mit |
hakehuang/pycpld | ips/ip/spi_slave_b2b/spi_slave_act_h_b2b.v | 4,912 | module MODULE1(
clk,VAR17,VAR10,VAR2,VAR16,VAR23,VAR11
);
input clk;
input VAR23;
input VAR17,VAR10,VAR16;
output VAR2;
output VAR11;
reg VAR11;
reg[2:0] VAR3;
reg[2:0] VAR6;
reg[1:0] VAR15;
reg[2:0] VAR7;
reg[7:0] VAR21;
reg VAR4; reg [7:0] VAR8;
reg[7:0] VAR13;
reg [7:0] VAR14;
reg [7:0] VAR18;
reg [7:0] VAR19;
wire ... | mit |
eda-globetrotter/MarcheProcessor | processor/spare/build1/prog_counter2.v | 1,428 | module MODULE1 (VAR2,rst,clk);
output [0:31] VAR2;
input clk;
input rst;
reg [0:31] VAR2; reg [0:31] VAR1;
always @(posedge clk)
begin
if(rst)
begin
VAR2<=32'd0;
VAR1<=32'd0;
end
else
begin
VAR1<=VAR1+32'd4;
VAR2<=VAR1>>2;
end
end
endmodule | mit |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_data_fifo_v2_1/82d298e6/hdl/verilog/axi_data_fifo_v2_1_axic_srl_fifo.v | 8,226 | module MODULE1 #
(
parameter VAR9 = "none", parameter integer VAR24 = 1, parameter integer VAR19 = 33, parameter integer VAR6 = 2, parameter VAR18 = 1 )
(
input wire VAR21, input wire VAR38, input wire [VAR24-1:0] VAR27, input wire VAR14, output wire VAR12, output wire [VAR24-1:0] VAR10, output wire VAR29, input wire V... | mit |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | source/hardware/nfc-substrate/tiger4_nfc_substrate-1.0.0/AXI4CommandDriver.v | 4,073 | module MODULE1
(
parameter VAR13 = 32 ,
parameter VAR7 = 32
)
(
VAR20 ,
VAR19 ,
VAR23 ,
VAR12 ,
VAR8 ,
VAR15 ,
VAR3 ,
VAR10 ,
VAR14 ,
VAR2 ,
VAR21 ,
VAR22 ,
VAR18 ,
VAR17 ,
VAR6 ,
VAR16
);
input VAR20 ;
input VAR19 ;
output [VAR13 - 1:0] VAR23 ;
output [7:0] VAR12 ;
output [2:0] VAR8 ;
output [1:0] VAR15 ;
output [3:0]... | gpl-3.0 |
ychaim/FPGA-Litecoin-Miner | experimental/LX150-EIGHT-B/ltcminer_icarus.v | 11,669 | module MODULE1 (VAR107, VAR19, VAR41, VAR11, VAR50, VAR87, VAR102, VAR15, VAR1, VAR37);
function integer VAR64; input integer VAR103;
begin
VAR103 = VAR103-1;
for (VAR64=0; VAR103>0; VAR64=VAR64+1)
VAR103 = VAR103>>1;
end
endfunction
parameter VAR12 = VAR12;
parameter VAR12 = 50; VAR72
parameter VAR97 = VAR97; else
par... | gpl-3.0 |
siamumar/TinyGarbled | circuit_synthesis/rsa/modexp_1_N.v | 2,404 | module MODULE1
parameter VAR17 = 8, parameter VAR10 = VAR17 )
(
clk,
rst,
VAR26, VAR4, VAR8 );
input clk;
input rst;
input [VAR17-1:0] VAR26;
input [2*VAR17-1:0] VAR4;
output [VAR17-1:0] VAR8;
wire [VAR17-1:0] VAR20;
wire [VAR17-1:0] VAR13;
assign VAR20 = VAR4[VAR17-1:0];
assign VAR13 = VAR4[2*VAR17-1:VAR17];
reg VAR2;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlymetal6s2s/sky130_fd_sc_hd__dlymetal6s2s_1.v | 2,157 | module MODULE1 (
VAR1 ,
VAR7 ,
VAR5,
VAR3,
VAR8 ,
VAR6
);
output VAR1 ;
input VAR7 ;
input VAR5;
input VAR3;
input VAR8 ;
input VAR6 ;
VAR2 VAR4 (
.VAR1(VAR1),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR1,
VAR7
);
output VAR1;
input VAR7;
supply1 VAR5;
supply0 VAR3;... | apache-2.0 |
ShepardSiegel/ocpi | rtl/mkQABSMF3.v | 111,930 | module MODULE1(VAR217,
VAR246,
VAR53,
VAR243,
VAR16,
VAR59,
VAR409,
VAR400,
VAR347,
VAR332,
VAR364,
VAR398,
VAR13,
VAR235,
VAR313,
VAR83,
VAR125,
VAR65,
VAR185,
VAR357,
VAR20,
VAR405,
VAR287,
VAR250,
VAR367,
VAR369,
VAR350,
VAR253);
input [15 : 0] VAR217;
input [15 : 0] VAR246;
input VAR53;
input VAR243;
input [39 : 0]... | lgpl-3.0 |
rbarzic/arty-cm0-designstart | rtl/cmsdk_ahb_ram.v | 5,636 | module MODULE1(
VAR16, VAR25, VAR11,
VAR27, VAR8, VAR12, VAR3, VAR9, VAR5, VAR17, VAR19, VAR1
);
parameter VAR14 = 16; parameter VAR10 = 0;
parameter VAR2 = "";
input VAR27; input VAR8; input VAR12; input [VAR14-1:0] VAR3; input [1:0] VAR9; input [2:0] VAR5; input VAR17; input [31:0] VAR19; input VAR1; output VAR16; ou... | gpl-2.0 |
everskar2013/PentiumX | Hardware/Code/irq_arb.v | 7,710 | module MODULE1(
clk,
rst,
req,
VAR7
);
input clk;
input rst;
input [VAR5 - 1: 0]
req; output [VAR8 - 1: 0]
VAR7;
parameter VAR2 = VAR8'h0,
VAR4 = VAR8'h1,
VAR6 = VAR8'h2,
VAR1 = VAR8'h3;
reg [VAR8 - 1: 0] state = 0, VAR3 = 0;
assign VAR7 = state;
always@(posedge clk or posedge rst)
if(rst) state <= VAR2;
else state <= ... | mit |
hydai/Verilog-Practice | HardwareLab/Final/CAR_CTR.v | 1,387 | module MODULE1(
output reg VAR10,
output reg VAR6,
output reg VAR8,
output reg VAR12,
input VAR13,
input VAR11,
input clk,
input VAR7
);
parameter VAR5 = 2'b00;
parameter VAR9 = 2'b01;
parameter VAR1 = 2'b10;
parameter VAR4 = 2'b11;
parameter VAR2 = 1'b1;
parameter VAR3 = 1'b0;
always @(*) begin
if (VAR13 == VAR3 && VA... | mit |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_dwidth_converter_v2_1/hdl/verilog/axi_dwidth_converter_v2_1_b_downsizer.v | 10,782 | module MODULE1 #
(
parameter VAR19 = "none",
parameter integer VAR28 = 1
)
(
input wire VAR36,
input wire VAR3,
input wire VAR12,
input wire VAR2,
input wire [8-1:0] VAR33,
output wire VAR16,
input wire [VAR28-1:0] VAR22,
output wire [VAR28-1:0] VAR10,
output wire [2-1:0] VAR13,
output wire VAR15,
input wire VAR18,
inp... | gpl-3.0 |
Kipsora/MIPS-CPU | source/machine/cpu/stages/if-id-buffer.v | 1,195 | module MODULE1(
input wire VAR5,
input wire reset,
input wire[VAR6] VAR3,
input wire[VAR7] VAR1,
input wire[VAR10] VAR2,
output reg[VAR7] VAR4,
output reg[VAR10] VAR9
);
always @ (posedge VAR5) begin
if (reset == VAR11) begin
VAR4 <= 0; VAR9 <= 0; end else if (VAR3[1] == VAR11 && VAR3[2] == VAR8) begin
VAR4 <= 0; VAR9 ... | mit |
cpulabs/mist1032sa | src/core/execute/execute_shift.v | 13,834 | module MODULE1 #(
parameter VAR25 = 32
)(
input wire [2:0] VAR18,
input wire [VAR25-1:0] VAR17,
input wire [VAR25-1:0] VAR21,
output wire [VAR25-1:0] VAR11,
output wire VAR16,
output wire VAR13,
output wire VAR19,
output wire VAR24,
output wire VAR2
);
function [31:0] VAR6;
input [31:0] VAR20;
input [4:0] VAR26;
begin
... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s.functional.pp.v | 1,763 | module MODULE1 (
VAR8,
VAR2,
VAR4 ,
VAR10
);
input VAR8;
input VAR2;
output VAR4 ;
input VAR10 ;
wire VAR1 ;
wire VAR3;
buf VAR7 (VAR1 , VAR10 );
VAR5 VAR9 (VAR3, VAR1, VAR8, VAR2);
buf VAR6 (VAR4 , VAR3 );
endmodule | apache-2.0 |
borti4938/sd2snes | verilog/sd2snes_sdd1/main.v | 27,794 | module MODULE1(
output [22:0] VAR324,
output VAR31,
input VAR4,
output VAR190,
input VAR202,
output [21:0] VAR324,
output VAR333,
output VAR208,
output VAR56,
output VAR195,
output VAR301,
input VAR311,
input VAR213,
input [23:0] VAR368,
input VAR154,
input VAR374,
input VAR184,
inout [7:0] VAR218,
input VAR258,
input ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a31o/sky130_fd_sc_hs__a31o_4.v | 2,210 | module MODULE1 (
VAR4 ,
VAR7 ,
VAR1 ,
VAR6 ,
VAR3 ,
VAR9,
VAR8
);
output VAR4 ;
input VAR7 ;
input VAR1 ;
input VAR6 ;
input VAR3 ;
input VAR9;
input VAR8;
VAR5 VAR2 (
.VAR4(VAR4),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR4 ,
VAR7,
VAR1,
VAR6,
VAR3
);... | apache-2.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/ipshared/ENCLab/Tiger4NSC_v1_2_3/ff169405/src/FMCTop.v | 36,372 | module MODULE1
(
parameter VAR203 = 8 ,
parameter VAR51 = 64 ,
parameter VAR131 = 256 ,
parameter VAR280 = 2 ,
parameter VAR152 = 12 ,
parameter VAR346 = 9 ,
parameter VAR248 = 27 ,
parameter VAR204 = 15
)
(
VAR278 ,
VAR297 ,
VAR272 ,
VAR262 ,
VAR21 ,
VAR41 ,
VAR255 ,
VAR84 ,
VAR155 ,
VAR48 ,
VAR123 ,
VAR320 ,
VAR217 ,... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdlclkp/sky130_fd_sc_hs__sdlclkp.blackbox.v | 1,261 | module MODULE1 (
VAR1,
VAR3,
VAR4 ,
VAR2
);
output VAR1;
input VAR3;
input VAR4 ;
input VAR2 ;
supply1 VAR5;
supply0 VAR6;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/tapvgnd/sky130_fd_sc_hdll__tapvgnd.pp.symbol.v | 1,266 | module MODULE1 (
input VAR2 ,
input VAR4,
input VAR3,
input VAR1
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o31a/sky130_fd_sc_lp__o31a.behavioral.pp.v | 2,015 | module MODULE1 (
VAR8 ,
VAR7 ,
VAR10 ,
VAR1 ,
VAR13 ,
VAR12,
VAR9,
VAR11 ,
VAR2
);
output VAR8 ;
input VAR7 ;
input VAR10 ;
input VAR1 ;
input VAR13 ;
input VAR12;
input VAR9;
input VAR11 ;
input VAR2 ;
wire VAR4 ;
wire VAR15 ;
wire VAR16;
or VAR17 (VAR4 , VAR10, VAR7, VAR1 );
and VAR5 (VAR15 , VAR4, VAR13 );
VAR6 VAR1... | apache-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeDE1SoC/Computer_System/synthesis/submodules/altera_up_edge_detection_sobel_operator.v | 7,534 | module MODULE1 (
clk,
reset,
VAR18,
VAR22,
VAR19
);
parameter VAR30 = 640;
input clk;
input reset;
input [ 8: 0] VAR18;
input VAR22;
output [ 9: 0] VAR19;
wire [ 8: 0] VAR28[ 1: 0];
reg [ 8: 0] VAR5[ 2: 0];
reg [ 8: 0] VAR15[ 2: 0];
reg [ 8: 0] VAR25[ 2: 0];
reg [11: 0] VAR1[ 3: 0];
reg [11: 0] VAR16[ 1: 0];
reg [11: 0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlrtn/sky130_fd_sc_ms__dlrtn.functional.pp.v | 2,056 | module MODULE1 (
VAR6 ,
VAR13,
VAR9 ,
VAR14 ,
VAR5 ,
VAR15 ,
VAR17 ,
VAR11
);
output VAR6 ;
input VAR13;
input VAR9 ;
input VAR14 ;
input VAR5 ;
input VAR15 ;
input VAR17 ;
input VAR11 ;
wire VAR10 ;
wire VAR2;
wire VAR7 ;
not VAR4 (VAR10 , VAR13 );
not VAR3 (VAR2, VAR14 );
VAR8 VAR16 VAR1 (VAR7 , VAR9, VAR2, VAR10, , ... | apache-2.0 |
horia141/mv-parser | projects/LedPattern/LedPattern.v | 10,104 | module MODULE1;
wire [7:0] VAR1; | mit |
n8thenetninja/Cloud-Car | VeriLog/QuartusProjects/ServoController/i2cslave/trunk/model/i2c_master_byte_ctrl.v | 10,545 | module MODULE1 (
clk, rst, VAR25, VAR29, VAR22, VAR38, VAR33, read, write, VAR20, din,
VAR21, VAR13, dout, VAR26, VAR42, VAR11, VAR31, VAR34, VAR28, VAR1, VAR9 );
input clk; input rst; input VAR25; input VAR29;
input [15:0] VAR22;
input VAR38;
input VAR33;
input read;
input write;
input VAR20;
input [7:0] din;
output V... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/DE4_SOPC_burst_2.v | 25,700 | module MODULE1 (
clk,
VAR47,
VAR77,
VAR24,
VAR100,
VAR13,
VAR96,
VAR59,
VAR28
)
;
output [ 63: 0] VAR28;
input clk;
input [ 63: 0] VAR47;
input [ 8: 0] VAR77;
input VAR24;
input VAR100;
input [ 8: 0] VAR13;
input VAR96;
input VAR59;
reg [ 63: 0] VAR66 [511: 0];
wire [ 63: 0] VAR28;
reg [ 8: 0] VAR90;
always @(posedge c... | mit |
vad-rulezz/megabot | minsoc/rtl/verilog/xilinx_dcm.v | 9,071 | module MODULE1(
VAR59,
VAR25
);
parameter VAR14 = 2;
input VAR59;
output VAR25;
wire VAR40;
wire VAR33;
assign VAR40 = VAR59;
assign VAR25 = VAR33;
wire VAR57;
wire VAR54;
wire VAR63;
wire VAR28;
VAR72 VAR44 (
.VAR38(VAR40),
.VAR16(VAR57)
);
VAR35 VAR24 (
.VAR38(VAR54),
.VAR16(VAR63)
);
VAR35 VAR34 (
.VAR38(VAR28),
.VA... | gpl-2.0 |
thucoldwind/ucore_mips | CPU32/thinpad_top/thinpad_top.srcs/sources_1/new/id_ex.v | 6,365 | module MODULE1(
input wire clk,
input wire rst,
input wire[31:0] VAR56,
input wire VAR57,
input wire[31:0] VAR51,
input wire[31:0] VAR28,
input wire[4:0] VAR30,
input wire[31:0] VAR21,
input wire[2:0] VAR3,
input wire VAR40,
input wire[4:0] VAR58,
input wire VAR37,
input wire VAR13,
input wire[4:0] VAR35,
input wire VA... | unlicense |
yard2010/Arducar | Car/Modules/Video-and-Image-Processing-Design-Using-FPGAs-master/de1_ov7670/SRC/I2C/I2C_OV7670_Config.v | 8,694 | module MODULE1
(
input [7:0] VAR2,
output reg [15:0] VAR3
);
parameter VAR4 = 0; parameter VAR1 = 2; always@(*)
begin
case(VAR2)
VAR4 + 0 : VAR3 = {8'h0A, 8'h76}; VAR4 + 1 : VAR3 = {8'h0B, 8'h73}; VAR1 + 0 : VAR3 = 16'h3a00; VAR1 + 1 : VAR3 = 16'h40d0; VAR1 + 2 : VAR3 = 16'h1280; VAR1 + 3 : VAR3 = 16'h32b6; VAR1 + 4 : ... | apache-2.0 |
trivoldus28/pulsarch-verilog | verif/env/cmp/l1warm.v | 84,729 | module MODULE1();
reg [7:0] VAR7;
reg VAR26;
integer VAR8;
integer VAR16;
reg [32:0] VAR22 [511:0];
reg [32:0] VAR1 [511:0];
reg [32:0] VAR12 [511:0];
reg [32:0] VAR27 [511:0];
reg [32:0] VAR15 [511:0];
reg [32:0] VAR3 [511:0];
reg [32:0] VAR28 [511:0];
reg [32:0] VAR6 [511:0];
reg [32:0] VAR21 [511:0];
reg [32:0] VAR1... | gpl-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/synthesis/submodules/Video_System_Clock_Signals.v | 10,578 | module MODULE1 (
VAR96,
reset,
VAR95,
VAR87,
VAR26
);
input VAR96;
input reset;
output VAR95;
output VAR87;
output VAR26;
localparam VAR102 = 1;
localparam VAR70 = 1;
wire [ 2: 0] VAR9;
wire VAR38;
wire VAR33;
wire VAR77;
assign VAR26 = VAR38;
assign VAR87 = VAR9[0];
assign VAR77 = VAR9[1];
assign VAR95 = VAR9[2];
VAR6... | gpl-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/up_xfer_cntrl.v | 5,149 | module MODULE1 (
VAR1,
VAR17,
VAR13,
VAR16,
VAR15,
VAR10,
VAR12);
parameter VAR4 = 8;
localparam VAR8 = VAR4 - 1;
input VAR1;
input VAR17;
input [VAR8:0] VAR13;
output VAR16;
input VAR15;
input VAR10;
output [VAR8:0] VAR12;
reg VAR9 = 'd0;
reg VAR21 = 'd0;
reg VAR3 = 'd0;
reg [ 5:0] VAR6 = 'd0;
reg VAR16 = 'd0;
reg VAR... | gpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp2/fifo/fifo36_demux.v | 2,104 | module MODULE1
parameter VAR16 = 0)
(input clk, input reset, input VAR13,
input [35:0] VAR11, input VAR7, output VAR14,
output [35:0] VAR6, output VAR10, input VAR1,
output [35:0] VAR17, output VAR15, input VAR12);
localparam VAR4 = 0;
localparam VAR3 = 1;
localparam VAR8 = 2;
reg [1:0] state;
wire VAR2 = |( (VAR11 ^ V... | gpl-2.0 |
toyoshim/tvcl | sample/spartan-3-starterkit.v | 2,833 | module MODULE1(
VAR14,
VAR25,
VAR39,
VAR35,
VAR28,
VAR12,
VAR20,
VAR30,
VAR23,
VAR1,
VAR34,
VAR5,
VAR21,
VAR18,
VAR6,
VAR32,
VAR24,
VAR38,
VAR26,
VAR13,
VAR33,
VAR19,
VAR15,
VAR31,
VAR7,
VAR29,
VAR10,
VAR27,
VAR17,
VAR37,
VAR4,
VAR16,
VAR11,
VAR8,
VAR22,
VAR9,
VAR2,
VAR36,
VAR3);
input VAR14;
input VAR25;
output [17:0]... | bsd-3-clause |
545/Atari7800 | core/ag_6502/trunk/ag_6502/ag_6502.v | 8,530 | module MODULE2(input VAR93, output VAR70, output VAR162);
wire VAR149;
not(VAR70,VAR93);
or(VAR149,~VAR93, VAR70);
not(VAR162, VAR149);
endmodule
module MODULE5(input VAR146, input VAR93, output reg VAR70);
parameter VAR56 = 1; VAR98 VAR70 = 0;
integer VAR134 = 0;
always @(posedge VAR146) begin
if (VAR93 != VAR70) begi... | gpl-2.0 |
marmolejo/zet | cores/vga/rtl/fml/vga_lcd_fml.v | 14,788 | module MODULE1 #(
parameter VAR103 = 20 ) (
input clk, input rst,
input VAR92, input VAR102,
output reg [VAR103-1:0] VAR68,
output reg VAR1,
input VAR70,
input VAR123,
output [1:0] VAR114,
output [15:0] VAR104,
input [15:0] VAR33,
output reg VAR39,
output [VAR103-1:0] VAR31,
input [15:0] VAR80,
input VAR72,
input [3:0]... | gpl-3.0 |
tmolteno/TART | hardware/FPGA/fifo/afifo16.v | 1,178 | module MODULE1 (
VAR4,
VAR1,
VAR9,
VAR2,
VAR13,
VAR6,
VAR21,
VAR5,
VAR8
);
parameter VAR20 = 16;
input VAR4;
input VAR1;
input VAR9;
output [VAR20-1:0] VAR2;
input VAR13;
input VAR6;
input [VAR20-1:0] VAR21;
output VAR5;
output VAR8;
VAR11 #(VAR20,4,16) VAR19 (
.VAR16 (VAR1),
.VAR7 (VAR13),
.rst (VAR4),
.VAR12 (1'b0),
... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand2/sky130_fd_sc_hd__nand2_8.v | 2,097 | module MODULE1 (
VAR7 ,
VAR2 ,
VAR8 ,
VAR3,
VAR1,
VAR5 ,
VAR9
);
output VAR7 ;
input VAR2 ;
input VAR8 ;
input VAR3;
input VAR1;
input VAR5 ;
input VAR9 ;
VAR6 VAR4 (
.VAR7(VAR7),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR9(VAR9)
);
endmodule
module MODULE1 (
VAR7,
VAR2,
VAR8
);
output VAR7;
... | apache-2.0 |
hightoon/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/pcie_dma_engine/tag_generator.v | 2,875 | module MODULE1(
input clk,
input rst,
output reg VAR2,
input VAR5,
output [7:0] VAR1,
input [31:0] VAR4);
reg VAR3;
reg [4:0] VAR6;
always@(posedge clk) VAR3 <= rst;
always@(posedge clk)begin
if(VAR4[VAR6[4:0]])
VAR2 <= 1'b0;
end
else
VAR2 <= 1'b1;
end
assign VAR1[7:0] = {3'b000,VAR6[4:0]};
always@(posedge clk)begin
if... | bsd-2-clause |
UdayanSinha/Code_Blocks | Nios-2/Nios/practica4/mi_nios/synthesis/submodules/mi_nios_sdram.v | 24,338 | module MODULE1 (
clk,
rd,
VAR77,
wr,
VAR75,
VAR53,
VAR48,
VAR68,
VAR14,
VAR47
)
;
output VAR53;
output VAR48;
output VAR68;
output VAR14;
output [ 40: 0] VAR47;
input clk;
input rd;
input VAR77;
input wr;
input [ 40: 0] VAR75;
wire VAR53;
wire VAR48;
wire VAR68;
reg [ 1: 0] VAR37;
reg [ 40: 0] VAR50;
reg [ 40: 0] VAR55... | mit |
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