repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux2/sky130_fd_sc_lp__mux2_1.v | 2,187 | module MODULE2 (
VAR5 ,
VAR1 ,
VAR6 ,
VAR7 ,
VAR9,
VAR8,
VAR2 ,
VAR3
);
output VAR5 ;
input VAR1 ;
input VAR6 ;
input VAR7 ;
input VAR9;
input VAR8;
input VAR2 ;
input VAR3 ;
VAR10 VAR4 (
.VAR5(VAR5),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR3(VAR3)
);
endmodule
module MODULE2 (... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/xnor2/sky130_fd_sc_hd__xnor2.behavioral.v | 1,401 | module MODULE1 (
VAR5,
VAR6,
VAR7
);
output VAR5;
input VAR6;
input VAR7;
supply1 VAR2;
supply0 VAR8;
supply1 VAR10 ;
supply0 VAR4 ;
wire VAR9;
xnor VAR1 (VAR9, VAR6, VAR7 );
buf VAR3 (VAR5 , VAR9 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a211oi/sky130_fd_sc_hs__a211oi.functional.pp.v | 1,945 | module MODULE1 (
VAR7,
VAR11,
VAR6 ,
VAR15 ,
VAR4 ,
VAR5 ,
VAR9
);
input VAR7;
input VAR11;
output VAR6 ;
input VAR15 ;
input VAR4 ;
input VAR5 ;
input VAR9 ;
wire VAR9 VAR8 ;
wire VAR14 ;
wire VAR12;
and VAR3 (VAR8 , VAR15, VAR4 );
nor VAR13 (VAR14 , VAR8, VAR5, VAR9 );
VAR1 VAR10 (VAR12, VAR14, VAR7, VAR11);
buf VAR2... | apache-2.0 |
jhennessy/parallella-hw-old | fpga/hdl/elink/ewrapper_io_rx_slow.v | 7,723 | module MODULE1 (
VAR50, VAR10,
VAR15, VAR57, VAR54, VAR4, VAR49,
VAR11, VAR41
);
input VAR15; input VAR57;
input VAR54;
input VAR4;
input [8:0] VAR49;
input [8:0] VAR11;
input VAR41;
output VAR50; output [71:0] VAR10;
reg [3:0] VAR19;
reg VAR32;
reg [8:0] VAR37;
reg [8:0] VAR30;
reg [8:0] VAR25;
reg [8:0] VAR46;
reg [8... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o31ai/sky130_fd_sc_lp__o31ai_lp.v | 2,343 | module MODULE2 (
VAR8 ,
VAR9 ,
VAR3 ,
VAR4 ,
VAR7 ,
VAR1,
VAR10,
VAR5 ,
VAR11
);
output VAR8 ;
input VAR9 ;
input VAR3 ;
input VAR4 ;
input VAR7 ;
input VAR1;
input VAR10;
input VAR5 ;
input VAR11 ;
VAR2 VAR6 (
.VAR8(VAR8),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR5(VAR5),
.VA... | apache-2.0 |
fabianmcg/usbc_tcpc | src/probador_Rx.v | 1,311 | module MODULE1(VAR4, reset, VAR1, VAR16, VAR14, VAR9, VAR13, VAR11, VAR18,
VAR2, VAR8, VAR10, VAR17, VAR5, VAR12, VAR7, VAR6);
input wire [15:0] VAR17;
input wire [7:0] VAR6;
input wire [7:0] VAR7;
input wire [7:0] VAR5;
input wire VAR12;
output wire VAR4;
output reg reset;
output reg VAR1;
output reg [7:0] VAR16; outp... | mit |
pavel-demin/red-pitaya-notes | cores/axis_interpolator_v1_0/axis_interpolator.v | 2,156 | module MODULE1 #
(
parameter integer VAR19 = 32,
parameter integer VAR1 = 32
)
(
input wire VAR12,
input wire VAR8,
input wire [VAR1-1:0] VAR18,
output wire VAR16,
input wire [VAR19-1:0] VAR14,
input wire VAR3,
input wire VAR13,
output wire [VAR19-1:0] VAR10,
output wire VAR2
);
reg [VAR19-1:0] VAR11, VAR7;
reg [VAR1-1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfstp/sky130_fd_sc_ms__sdfstp_2.v | 2,511 | module MODULE2 (
VAR1 ,
VAR8 ,
VAR12 ,
VAR6 ,
VAR11 ,
VAR2,
VAR10 ,
VAR9 ,
VAR7 ,
VAR4
);
output VAR1 ;
input VAR8 ;
input VAR12 ;
input VAR6 ;
input VAR11 ;
input VAR2;
input VAR10 ;
input VAR9 ;
input VAR7 ;
input VAR4 ;
VAR3 VAR5 (
.VAR1(VAR1),
.VAR8(VAR8),
.VAR12(VAR12),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR2(VAR2),
.VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand3b/sky130_fd_sc_lp__nand3b_4.v | 2,229 | module MODULE1 (
VAR6 ,
VAR9 ,
VAR1 ,
VAR5 ,
VAR4,
VAR3,
VAR10 ,
VAR8
);
output VAR6 ;
input VAR9 ;
input VAR1 ;
input VAR5 ;
input VAR4;
input VAR3;
input VAR10 ;
input VAR8 ;
VAR2 VAR7 (
.VAR6(VAR6),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR8(VAR8)
);
endmodule
module MODULE... | apache-2.0 |
fallen/milkymist-mmu | cores/tmu2/rtl/tmu2_dpram.v | 1,313 | module MODULE1 #(
parameter VAR6 = 11,
parameter VAR9 = 32
) (
input VAR10,
input [VAR6-1:0] VAR1,
input VAR2,
output [VAR9-1:0] rd,
input [VAR6-1:0] VAR11,
input VAR7,
input [VAR9-1:0] VAR8
);
reg [VAR9-1:0] VAR4[0:(1 << VAR6)-1];
reg [VAR6-1:0] VAR3;
always @(posedge VAR10) begin
if(VAR2)
VAR3 <= VAR1;
if(VAR7)
VAR4[... | lgpl-3.0 |
Apo45ty/ArquiCourseCPUVerilog | VerilogSource/ControlUnit+ALU/controlunit.v | 3,077 | module MODULE1 (output reg VAR1, VAR6, VAR13, VAR9, VAR11, VAR23, VAR12, VAR18,VAR10,VAR16,VAR8,VAR3,VAR2,output reg[4:0] VAR15, output reg[3:0] VAR14, input VAR20, VAR19,VAR21, input [31:0] VAR24,input [3:0] VAR5);
reg [4:0] VAR7, VAR22;
task VAR17;
input [17:0] VAR4;
fork
{VAR14,VAR1, VAR6, VAR13, VAR9,VAR15, VAR11, ... | apache-2.0 |
kyzhai/NUNY | src/hardware/thesis_new_bb.v | 5,042 | module MODULE1 (
address,
VAR2,
VAR1);
input [11:0] address;
input VAR2;
output [11:0] VAR1;
tri1 VAR2;
endmodule | gpl-2.0 |
lynxis/lpc_sniffer | uart_tx.v | 1,588 | module MODULE1 #(parameter VAR5 = 12000000, VAR13 = 115200)
(
input VAR4,
input [7:0] VAR2,
input VAR10,
input reset,
output reg ready,
output reg VAR11,
output reg VAR3);
reg [9:0] VAR8;
localparam VAR7 = VAR5 / VAR13 / 2;
reg [24:0] VAR1;
reg VAR6;
reg state;
reg [3:0] VAR12;
localparam VAR14 = 1'h0, VAR9 = 1'h1;
alw... | gpl-3.0 |
iori-yja/ball_detector | divider_bb.v | 3,690 | module MODULE1 (
VAR5,
VAR1,
VAR2,
VAR3,
VAR4);
input VAR5;
input [4:0] VAR1;
input [10:0] VAR2;
output [10:0] VAR3;
output [4:0] VAR4;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a22o/sky130_fd_sc_hdll__a22o_4.v | 2,355 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR11 ,
VAR3 ,
VAR8 ,
VAR2,
VAR6,
VAR9 ,
VAR10
);
output VAR5 ;
input VAR1 ;
input VAR11 ;
input VAR3 ;
input VAR8 ;
input VAR2;
input VAR6;
input VAR9 ;
input VAR10 ;
VAR4 VAR7 (
.VAR5(VAR5),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR9(VAR9),
.VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor2/sky130_fd_sc_ls__nor2.symbol.v | 1,260 | module MODULE1 (
input VAR3,
input VAR4,
output VAR5
);
supply1 VAR6;
supply0 VAR7;
supply1 VAR1 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
GREO/gnuradio-git | gr-radar-mono/src/fpga/lib/radar_control.v | 5,043 | module MODULE1(VAR50,VAR35,VAR45,VAR7,VAR51,
VAR6,VAR12,VAR41,VAR25,VAR14,
VAR15,VAR17,VAR38,VAR30,VAR32);
input VAR50; input [6:0] VAR35; input [31:0] VAR45; input VAR7;
output VAR51;
output VAR6;
output VAR12;
output VAR41;
output VAR25;
output VAR14;
output [15:0] VAR15;
output [31:0] VAR17;
output [31:0] VAR38;
out... | gpl-3.0 |
Cognoscan/BoostDSP | verilog/src/smallFilters/SmallLpf.v | 1,561 | module MODULE1 #(
parameter VAR2 = 8, parameter VAR4 = 8 )
(
input clk, input rst, input en, input signed [VAR2-1:0] VAR1, output signed [VAR2-1:0] VAR3 );
reg signed [VAR2+VAR4-1:0] VAR5;
assign VAR3 = VAR5[VAR2+VAR4-1:VAR4];
always @(posedge clk) begin
if (rst) begin
VAR5 <= 'd0;
end
else if (en) begin
VAR5 <= VAR5 +... | apache-2.0 |
gigglesninja/digital-system-design | spi/spi_bonus.v | 3,804 | module MODULE1(clk, reset, din, dout, VAR12, VAR10, addr, VAR26, VAR21, VAR1);
input clk, reset, VAR12, VAR10;
input [7:0] din;
output [7:0] dout;
input [1:0] addr;
output VAR26; input VAR21; output VAR1;
reg [7:0] VAR9, VAR32, VAR15, dout;
reg VAR5, VAR20, VAR7, VAR30, VAR34, VAR24, VAR35, VAR2, VAR8, VAR14;
reg [6:0]... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv3sd2/sky130_fd_sc_ms__clkdlyinv3sd2.functional.pp.v | 1,867 | module MODULE1 (
VAR1 ,
VAR11 ,
VAR4,
VAR9,
VAR3 ,
VAR6
);
output VAR1 ;
input VAR11 ;
input VAR4;
input VAR9;
input VAR3 ;
input VAR6 ;
wire VAR7 ;
wire VAR5;
not VAR2 (VAR7 , VAR11 );
VAR8 VAR12 (VAR5, VAR7, VAR4, VAR9);
buf VAR10 (VAR1 , VAR5 );
endmodule | apache-2.0 |
jefg89/proyecto_final_prototipado | ProyectoFinal/SOC/synthesis/submodules/SoC_NIOS_jtag_debug_module_sysclk.v | 6,739 | module MODULE1 (
clk,
VAR19,
VAR1,
VAR28,
VAR27,
VAR23,
VAR18,
VAR11,
VAR3,
VAR22,
VAR9,
VAR8,
VAR5,
VAR15,
VAR25,
VAR16,
VAR26,
VAR2,
VAR30
)
;
output [ 37: 0] VAR23;
output VAR18;
output VAR11;
output VAR3;
output VAR22;
output VAR9;
output VAR8;
output VAR5;
output VAR15;
output VAR25;
output VAR16;
output VAR26;
ou... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/einvp/sky130_fd_sc_lp__einvp.behavioral.pp.v | 1,863 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR13 ,
VAR6,
VAR9,
VAR10 ,
VAR1
);
output VAR2 ;
input VAR4 ;
input VAR13 ;
input VAR6;
input VAR9;
input VAR10 ;
input VAR1 ;
wire VAR12 ;
wire VAR8;
VAR3 VAR7 (VAR12 , VAR4, VAR6, VAR9 );
VAR3 VAR5 (VAR8, VAR13, VAR6, VAR9 );
notif1 VAR11 (VAR2 , VAR12, VAR8);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand2b/sky130_fd_sc_lp__nand2b.functional.v | 1,356 | module MODULE1 (
VAR3 ,
VAR8,
VAR4
);
output VAR3 ;
input VAR8;
input VAR4 ;
wire VAR2 ;
wire VAR7;
not VAR6 (VAR2 , VAR4 );
or VAR5 (VAR7, VAR2, VAR8 );
buf VAR1 (VAR3 , VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and2b/sky130_fd_sc_ls__and2b.pp.blackbox.v | 1,287 | module MODULE1 (
VAR6 ,
VAR7 ,
VAR2 ,
VAR5,
VAR3,
VAR1 ,
VAR4
);
output VAR6 ;
input VAR7 ;
input VAR2 ;
input VAR5;
input VAR3;
input VAR1 ;
input VAR4 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_1.functional.pp.v | 2,125 | module MODULE1( VAR22, VAR11, VAR26, VAR23, VAR15, VAR12, VAR18, VAR6 );
input VAR12, VAR15, VAR11, VAR22, VAR23;
inout VAR18, VAR6;
output VAR26;
wire VAR9;
not VAR4( VAR9, VAR12 );
wire VAR7;
not VAR25( VAR7, VAR11 );
wire VAR27;
not VAR24( VAR27, VAR23 );
wire VAR8;
and VAR10( VAR8, VAR9, VAR7, VAR27 );
wire VAR21;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a221oi/sky130_fd_sc_hd__a221oi.pp.symbol.v | 1,409 | module MODULE1 (
input VAR2 ,
input VAR10 ,
input VAR1 ,
input VAR9 ,
input VAR6 ,
output VAR7 ,
input VAR3 ,
input VAR5,
input VAR8,
input VAR4
);
endmodule | apache-2.0 |
rafalmiel/fpga | tron/bigram_bb.v | 8,706 | module MODULE1 (
VAR2,
VAR7,
VAR8,
VAR5,
VAR6,
VAR10,
VAR9,
VAR4,
VAR3,
VAR1);
input [16:0] VAR2;
input [16:0] VAR7;
input [2:0] VAR8;
input [2:0] VAR5;
input VAR6;
input VAR10;
input VAR9;
input VAR4;
output [2:0] VAR3;
output [2:0] VAR1;
tri1 VAR6;
tri0 VAR9;
tri0 VAR4;
endmodule | gpl-2.0 |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/ip/hdl/verilog/ANN_fptrunc_64ns_32_1.v | 1,103 | module MODULE1
VAR7 = 4,
VAR14 = 1,
VAR9 = 64,
VAR8 = 32
)(
input wire [VAR9-1:0] VAR11,
output wire [VAR8-1:0] dout
);
wire VAR6;
wire [63:0] VAR12;
wire VAR4;
wire [31:0] VAR3;
VAR15 VAR16 (
.VAR2 ( VAR6 ),
.VAR10 ( VAR12 ),
.VAR5 ( VAR4 ),
.VAR1 ( VAR3 )
);
assign VAR6 = 1'b1;
assign VAR12 = VAR11==='VAR13 ? 'b0 : V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfxtp/sky130_fd_sc_hdll__sdfxtp.behavioral.pp.v | 2,390 | module MODULE1 (
VAR5 ,
VAR9 ,
VAR10 ,
VAR25 ,
VAR19 ,
VAR20,
VAR16,
VAR23 ,
VAR17
);
output VAR5 ;
input VAR9 ;
input VAR10 ;
input VAR25 ;
input VAR19 ;
input VAR20;
input VAR16;
input VAR23 ;
input VAR17 ;
wire VAR11 ;
wire VAR12 ;
reg VAR15 ;
wire VAR14 ;
wire VAR18;
wire VAR1;
wire VAR22;
wire VAR24 ;
wire VAR13 ;... | apache-2.0 |
ultraembedded/riscv | top_tcm_axi/src_v/tcm_mem_ram.v | 3,703 | module MODULE1
(
input VAR7
,input VAR8
,input [ 13:0] VAR11
,input [ 31:0] VAR10
,input [ 3:0] VAR9
,input VAR5
,input VAR6
,input [ 13:0] VAR14
,input [ 31:0] VAR4
,input [ 3:0] VAR2
,output [ 31:0] VAR12
,output [ 31:0] VAR3
);
reg [31:0] VAR15 [16383:0] ;
reg [31:0] VAR13;
reg [31:0] VAR1;
always @ (posedge VAR7)
b... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_io | cells/top_gpiov2/sky130_fd_io__top_gpiov2.behavioral.pp.v | 42,205 | module MODULE1 (VAR23, VAR71,VAR22,VAR57,
VAR59, VAR5, VAR68, VAR55, VAR24, VAR52, VAR49, VAR21, VAR44, VAR75,
VAR20, VAR15, VAR38, VAR7, VAR45, VAR46, VAR72, VAR1, VAR61,
VAR3, VAR26, VAR10, VAR32
,VAR51, VAR8, VAR37, VAR62, VAR17, VAR13, VAR74, VAR12,
VAR33, VAR19
);
input VAR26;
input VAR75;
input VAR68;
input VAR49... | apache-2.0 |
takeshineshiro/fpga_linear_128 | EmitOneCH.v | 2,006 | module MODULE1
(
input VAR2, input VAR7, input [7:0] VAR6, input [6:0] VAR4, output reg VAR8,
output reg VAR1
);
reg [6:0] VAR3;
reg [6:0] VAR5;
always @(posedge VAR2 or negedge VAR7)
begin
if(~VAR7) begin
VAR3 <= 7'd0;
VAR5 <= 8'd0;
VAR8 <= 1'b1;
VAR1 <= 1'b1;
end
else
begin
if(VAR5 < VAR6[6:0] ) begin
VAR5 <= VAR5 + ... | mit |
svofski/mahponk | src/analinput.v | 2,339 | module MODULE1(clk, VAR6, VAR15, VAR4, VAR13, VAR10, VAR16);
parameter VAR14 = 0;
parameter VAR9 = 0;
input clk;
output reg[9:0] VAR6;
output reg[9:0] VAR15;
input VAR4;
output reg VAR13;
output reg VAR10;
output VAR16;
parameter VAR2 = 0, VAR3 = 1, VAR11 = 2, VAR5 = 3;
reg [1:0] state;
reg [4:0] VAR8;
reg [11:0] VAR7;... | bsd-2-clause |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/cabac/cabac_bae_stage1.v | 10,741 | module MODULE1(
VAR9 ,
VAR13 ,
VAR2 ,
VAR10 ,
VAR4 ,
VAR8 ,
VAR7
);
input [5:0] VAR9 ;
input VAR13 ;
input VAR2 ;
output [31:0] VAR10 ;
output [35:0] VAR4 ;
output [15:0] VAR8 ;
output VAR7 ;
reg [31:0] VAR14 ;
always @* begin
case (VAR9)
6'd0: begin VAR14 = 32'h80b0d0f0 ; end
6'd1: begin VAR14 = 32'h80a7c5e3 ; end
6'd... | gpl-3.0 |
lokisz/openzcore | pippo-riscv/rtl/verilog/dsu_uartlite.v | 5,245 | module MODULE1(
clk, rst,
VAR41, VAR7,
VAR43,
VAR46, VAR26,
VAR5, VAR36,
VAR30, VAR8,
VAR1, VAR4,
VAR32,
VAR23,
VAR11,
VAR18,
VAR25
);
input clk;
input rst;
input VAR7;
output VAR41;
input [7:0] VAR43;
input VAR26;
input VAR36;
input VAR4;
input VAR8;
output [7:0] VAR46;
output [7:0] VAR5;
output [7:0] VAR30;
output [7... | gpl-2.0 |
Chapna/TTCache | src/set.v | 2,731 | module MODULE1 (enable, word, VAR4,
write, rst, VAR1, VAR2, VAR12,
VAR10, VAR8, VAR18,
VAR17, VAR20, ack);
parameter VAR14 = 4;
input enable;
input rst;
input [0:1] word;
input VAR4;
input write;
input rst;
input [0:4] VAR1;
input [0:15] VAR2;
input VAR12;
output reg VAR10;
output reg VAR8;
output reg [0:4] VAR18;
outp... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl.pp.blackbox.v | 1,452 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR5 ,
VAR7 ,
VAR4,
VAR3 ,
VAR6
);
output VAR2 ;
input VAR1 ;
input VAR5 ;
input VAR7 ;
input VAR4;
input VAR3 ;
input VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o311a/sky130_fd_sc_ls__o311a.symbol.v | 1,372 | module MODULE1 (
input VAR8,
input VAR9,
input VAR1,
input VAR10,
input VAR4,
output VAR3
);
supply1 VAR6;
supply0 VAR5;
supply1 VAR2 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
ShirmanXia/EE469SPRING16 | lab3/nios_system/synthesis/submodules/nios_system_load.v | 2,225 | module MODULE1 (
address,
VAR2,
clk,
VAR6,
VAR5,
VAR4,
VAR3,
VAR8
)
;
output VAR3;
output [ 31: 0] VAR8;
input [ 1: 0] address;
input VAR2;
input clk;
input VAR6;
input VAR5;
input [ 31: 0] VAR4;
wire VAR7;
reg VAR9;
wire VAR3;
wire VAR1;
wire [ 31: 0] VAR8;
assign VAR7 = 1;
assign VAR1 = {1 {(address == 0)}} & VAR9;
a... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/fpu/rtl/fpu_in_dp.v | 8,991 | module MODULE1 (
VAR59,
VAR29,
VAR57,
VAR36,
VAR48,
VAR4,
VAR28,
VAR21,
VAR2,
VAR44,
VAR51,
VAR8,
VAR12,
VAR15,
VAR31,
VAR6,
VAR10,
VAR42,
VAR32,
VAR52,
VAR18,
VAR58,
VAR5,
VAR60,
VAR40,
VAR14,
VAR50,
VAR55,
VAR3,
VAR33,
VAR11,
VAR7,
VAR27,
VAR45,
VAR30,
VAR23
);
input VAR59;
input [116:112] VAR29; input [79:72] VAR57;... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_ms__udp_dlatch_pr_pp_pg_n.blackbox.v | 1,464 | module MODULE1 (
VAR3 ,
VAR4 ,
VAR7 ,
VAR5 ,
VAR6,
VAR1 ,
VAR2
);
output VAR3 ;
input VAR4 ;
input VAR7 ;
input VAR5 ;
input VAR6;
input VAR1 ;
input VAR2 ;
endmodule | apache-2.0 |
curtiszimmerman/orp | hardware/mselSoC/src/systems/geophyte/rtl/verilog/sdhc/rtl/verilog/ftl_free_fifo.v | 2,813 | module MODULE1 (
input wire VAR1,
input wire VAR24,
input wire [9:0] VAR15,
input wire VAR25,
output wire [9:0] VAR4,
output reg VAR18,
input wire VAR13,
output wire VAR29
);
reg VAR30;
reg VAR26;
reg [9:0] VAR3;
reg [9:0] VAR10;
reg [9:0] VAR27;
reg VAR17;
wire [9:0] VAR20;
reg [3:0] state;
parameter [3:0] VAR28 = 'd0... | apache-2.0 |
kk4ead/stack16 | Datapath.v | 1,819 | module MODULE1 (clk, reset, addr, VAR20, read, write, irq, VAR2);
input clk, reset, irq;
inout [15:0] VAR20;
output [15:0] addr;
output read, write, VAR2;
reg [15:0] VAR18, VAR17;
reg [15:0] VAR4, VAR12, VAR13;
reg [7:0] VAR15;
wire [1:0] VAR9, VAR14, VAR6;
wire VAR19, VAR22, VAR8;
wire [5:0] VAR16;
wire [15:0] VAR1;
w... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/common/rtl/cluster_header.v | 3,612 | module MODULE1 (
VAR8, VAR12, VAR15, VAR14,
VAR19, VAR26, VAR16, VAR27, VAR5, VAR20, VAR3,
VAR22
);
input VAR19;
input VAR26;
input VAR16;
input VAR27;
input VAR5;
input VAR20;
output VAR8;
output VAR12;
output VAR15;
input VAR3; input VAR22;
output VAR14;
reg VAR8;
reg VAR12;
assign VAR15 = VAR19;
always @(negedge VAR... | gpl-2.0 |
megari/sd2snes | verilog/sd2snes/mcu_cmd.v | 15,884 | module MODULE1(
input clk,
input VAR54,
input VAR51,
input [7:0] VAR12,
input [7:0] VAR17,
output [2:0] VAR5,
output reg VAR64 = 0,
output VAR44,
output reg VAR58 = 0,
input VAR37,
output [7:0] VAR13,
input [7:0] VAR46,
output [7:0] VAR3,
input [31:0] VAR41,
input [2:0] VAR35,
output [23:0] VAR19,
output [23:0] VAR57,
... | gpl-2.0 |
glennchid/font5-firmware | src/verilog/synthesis/uart2_tx.v | 2,476 | module MODULE1 #(parameter VAR10 = 8, parameter real VAR3 = 9600) (
input reset,
input clk,
input VAR8,
input [VAR10-1:0] VAR15,
input VAR14,
output reg VAR1 = 1'b1,
output reg VAR17 = 1'b1
);
localparam VAR13 = VAR5(VAR6/VAR3);
localparam VAR11 = VAR5(VAR10+2);
localparam [VAR13-1:0] VAR12 = VAR6/VAR3;
reg [VAR10-1:0]... | gpl-3.0 |
hhuang25/uwaterloo_ece224 | Lab1/sysid.v | 1,392 | module MODULE1 (
address,
VAR2,
VAR1,
VAR3
)
;
output [ 31: 0] VAR3;
input address;
input VAR2;
input VAR1;
wire [ 31: 0] VAR3;
assign VAR3 = address ? 1379612281 : 0;
endmodule | mit |
MeshSr/onetswitch30 | ons30-app52-ref_ofshw/vivado/onets_7030_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/wildcard_lut_action.v | 10,413 | module MODULE1
parameter VAR57 = 32,
parameter VAR43 = 64,
parameter VAR38 = 16,
parameter VAR7 = 4,
parameter VAR59=0
)
( input VAR60,
input [VAR43-1:0] VAR55,
output reg VAR8,
output reg VAR48,
output reg [VAR57-1:0] VAR20,
output reg [VAR7-1:0] VAR85,
input VAR63,
input VAR32,
input [VAR7-1:0] VAR50,
output [VAR43-1... | lgpl-2.1 |
trivoldus28/pulsarch-verilog | design/sys/iop/ccx/rtl/cpx_fpbuf_p0.v | 1,301 | module MODULE1(
VAR1,
VAR2
);
input [7:0] VAR2;
output [7:0] VAR1;
assign VAR1[7:0] = ~VAR2[7:0];
endmodule | gpl-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeASIC/build/designware_divmod.v | 1,131 | module MODULE1(VAR15, reset, VAR5, VAR11, VAR2, VAR20);
parameter VAR13 = 16;
parameter VAR19 = 16;
parameter VAR24 = 0; parameter VAR22 = 1; parameter VAR4 = 2;
input VAR15, reset; input [VAR13-1:0] VAR5;
input [VAR19-1:0] VAR11;
output [VAR13-1:0] VAR2, VAR20;
wire VAR1;
VAR12 #(
.VAR18(VAR13),
.VAR16(VAR19),
.VAR17(... | mit |
AntonovAlexander/activecore | designs/rtl/ram/ram_dual_memsplit.v | 6,557 | module MODULE1
parameter VAR18="VAR5", VAR19="VAR15.VAR5", VAR13=32, VAR25=32, VAR39=1024, VAR30="VAR9", VAR16="VAR9"
)
(
input VAR1,
input VAR36,
input [0:0] VAR29,
input [0:0] VAR6,
input [31:0] VAR4,
input [3:0] VAR44,
input [31:0] VAR7,
output [0:0] VAR20,
output reg [0:0] VAR26,
output reg [31:0] VAR48,
input [0:0... | apache-2.0 |
ptracton/pmodacl2 | soc/xilinx/FDRE.v | 12,535 | primitive VAR8 (VAR44, VAR47, clk, VAR53, VAR35, VAR12, rst, VAR43, VAR26);
output VAR44; reg VAR44;
input VAR47, clk, VAR53, VAR35, VAR12, rst, VAR43, VAR26;
VAR41
? ? ? ? 1 0 ? ? : ? : 1;
? ? ? ? ? 1 ? ? : ? : 0;
? (??) ? 0 0 0 0 ? : ? : -;
? ? (??) ? ? ? ? ? : ? : -;
? ? ? (??) ? ? ? ? : ? : -;
0 (01) 0 1 0 0 0 ? : ... | mit |
ShepardSiegel/ocpi | coregen/dram_k7_mig11/mig_7series_v1_1/user_design/rtl/ecc/ecc_merge_enc.v | 5,839 | module MODULE1
parameter VAR15 = 100,
parameter VAR24 = 64,
parameter VAR13 = 72,
parameter VAR27 = 4,
parameter VAR11 = 1,
parameter VAR26 = 64,
parameter VAR20 = 72,
parameter VAR12 = 8,
parameter VAR19 = 4
)
(
VAR18, VAR17,
clk, rst, VAR22, VAR7, VAR25, VAR14, VAR8
);
input clk;
input rst;
input [2*VAR19*VAR24-1:0] ... | lgpl-3.0 |
spesialstyrker/boula | gen/PCIe/source/pcie_clocking_v6.v | 11,225 | module MODULE1 # (
parameter VAR118 = "VAR52",
parameter VAR73 = 8, parameter VAR120 = 4'h1, parameter VAR84 = 0, parameter VAR96 = 3
)
(
input wire VAR58,
input wire VAR112,
input wire VAR109,
input wire [1:0] VAR69,
output wire VAR17,
output wire VAR29,
output wire VAR72,
output wire VAR18,
output wire VAR22,
output ... | gpl-2.0 |
Gilberto-Lopez/Arquitectura-Computadoras | Memory.v | 1,226 | module MODULE1(
input wire [31:0] VAR5,
input wire clk,
input wire enable,
input wire VAR4,
input wire reset,
input wire [9:0] VAR2,
output reg [31:0] VAR6
);
reg [31:0] VAR1 [1023:0];
integer VAR3;
always @(posedge clk) begin
if (reset) begin
for(VAR3 = 0; VAR3 < 1024; VAR3 = VAR3 + 1) begin
VAR1[VAR3] = 32'h00000000;... | lgpl-3.0 |
TokiSeven/schoolMIPS | board/de0/de0_top.v | 5,435 | module MODULE1
(
input VAR21, input VAR72,
input [ 2:0] VAR34,
input [ 9:0] VAR65,
output [ 6:0] VAR47, output VAR64, output [ 6:0] VAR59, output VAR5, output [ 6:0] VAR10, output VAR27, output [ 6:0] VAR24, output VAR45,
output [ 9:0] VAR52,
output VAR54, input VAR29, output VAR23, input VAR60,
inout [15:0] VAR22, out... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/Detect_Change_To_One.v | 1,356 | module MODULE1
(
VAR8,
reset,
VAR1,
VAR6,
VAR3
);
input VAR8;
input reset;
input VAR1;
input VAR6;
output VAR3;
reg VAR5;
wire VAR7;
wire VAR2;
always @(posedge VAR8)
begin : VAR4
if (reset == 1'b1) begin
VAR5 <= 1'b0;
end
else if (VAR1) begin
VAR5 <= VAR6;
end
end
assign VAR7 = ~ VAR5;
assign VAR2 = VAR6 & VAR7;
assig... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_4.behavioral.v | 8,908 | module MODULE1( VAR18, VAR63, VAR32, VAR77, VAR89 );
input VAR77, VAR32, VAR18, VAR63;
output VAR89;
reg VAR12;
VAR6 VAR35(.VAR18(VAR18),.VAR63(VAR63),.VAR32(VAR32),.VAR77(VAR77),.VAR89(VAR89),.VAR12(VAR12));
VAR6 VAR27(.VAR18(VAR18),.VAR63(VAR63),.VAR32(VAR32),.VAR77(VAR77),.VAR89(VAR89),.VAR12(VAR12));
not VAR41(VAR2... | apache-2.0 |
jordens/redpid | verilog/red_pitaya_asg.v | 12,634 | module MODULE1
(
output [ 14-1: 0] VAR29 , output [ 14-1: 0] VAR45 , input VAR55 , input VAR15 , input VAR60 , input VAR81 , output VAR57 ,
input VAR59 , input VAR67 , input [ 32-1: 0] VAR56 , input [ 32-1: 0] VAR49 , input [ 4-1: 0] VAR52 , input VAR79 , input VAR43 , output [ 32-1: 0] VAR89 , output VAR2 , output VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlymetal6s2s/sky130_fd_sc_hd__dlymetal6s2s.symbol.v | 1,355 | module MODULE1 (
input VAR1,
output VAR2
);
supply1 VAR5;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfbbn/sky130_fd_sc_lp__dfbbn_2.v | 2,601 | module MODULE2 (
VAR6 ,
VAR5 ,
VAR9 ,
VAR10 ,
VAR4 ,
VAR12,
VAR3 ,
VAR8 ,
VAR11 ,
VAR7
);
output VAR6 ;
output VAR5 ;
input VAR9 ;
input VAR10 ;
input VAR4 ;
input VAR12;
input VAR3 ;
input VAR8 ;
input VAR11 ;
input VAR7 ;
VAR2 VAR1 (
.VAR6(VAR6),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR12(VAR12),
.V... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/ctu/rtl/ctu_dft_creg.v | 25,324 | module MODULE1 (
VAR102, VAR61, VAR56,
VAR228, VAR174, VAR27, VAR161, VAR135,
VAR105, VAR222, VAR152, VAR207, VAR53,
VAR187, VAR224, VAR48, VAR198,
VAR51, VAR22, VAR122,
VAR83, VAR86, VAR29,
VAR99, VAR101, VAR194, VAR12, VAR138,
VAR146, VAR159, VAR123
);
input VAR105;
input VAR222;
input VAR152;
input VAR207;
input VAR... | gpl-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/jump_ram_bb.v | 8,328 | module MODULE1 (
VAR7,
VAR3,
VAR5,
VAR4,
VAR1,
VAR6,
VAR2);
input [4:0] VAR7;
input [4:0] VAR3;
input VAR5;
input VAR4;
input VAR1;
output [15:0] VAR6;
output [15:0] VAR2;
tri1 VAR5;
tri1 VAR4;
tri1 VAR1;
endmodule | mit |
Jawanga/ece385lab8 | lab8_usb/usb_system/synthesis/submodules/usb_system_cpu_jtag_debug_module_wrapper.v | 10,271 | module MODULE1 (
VAR2,
VAR27,
clk,
VAR7,
VAR30,
VAR18,
VAR14,
VAR58,
VAR47,
VAR26,
VAR41,
VAR5,
VAR38,
VAR40,
VAR8,
VAR9,
VAR31,
VAR1,
VAR24,
VAR44,
VAR48,
VAR34,
VAR49,
VAR23,
VAR21,
VAR25,
VAR54,
VAR13,
VAR10,
VAR56,
VAR4,
VAR17,
VAR59,
VAR36,
VAR52,
VAR43
)
;
output [ 37: 0] VAR48;
output VAR34;
output VAR49;
output... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkdlybuf4s25/sky130_fd_sc_hd__clkdlybuf4s25.symbol.v | 1,356 | module MODULE1 (
input VAR3,
output VAR2
);
supply1 VAR4;
supply0 VAR1;
supply1 VAR6 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/buf/sky130_fd_sc_hvl__buf_16.v | 2,007 | module MODULE2 (
VAR2 ,
VAR5 ,
VAR7,
VAR3,
VAR8 ,
VAR4
);
output VAR2 ;
input VAR5 ;
input VAR7;
input VAR3;
input VAR8 ;
input VAR4 ;
VAR6 VAR1 (
.VAR2(VAR2),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR2,
VAR5
);
output VAR2;
input VAR5;
supply1 VAR7;
supply0 VAR3;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/isolatch/sky130_fd_sc_lp__isolatch.pp.symbol.v | 1,314 | module MODULE1 (
input VAR8 ,
output VAR7 ,
input VAR2,
input VAR5 ,
input VAR3 ,
input VAR1 ,
input VAR4 ,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a221oi/sky130_fd_sc_ls__a221oi.pp.blackbox.v | 1,436 | module MODULE1 (
VAR10 ,
VAR8 ,
VAR2 ,
VAR9 ,
VAR6 ,
VAR1 ,
VAR3,
VAR5,
VAR7 ,
VAR4
);
output VAR10 ;
input VAR8 ;
input VAR2 ;
input VAR9 ;
input VAR6 ;
input VAR1 ;
input VAR3;
input VAR5;
input VAR7 ;
input VAR4 ;
endmodule | apache-2.0 |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/Aurora_MGT/Pcore/mgt_fifo1_v1_00_a/hdl/verilog/global_logic.v | 5,252 | module MODULE1
(
VAR2,
VAR21,
VAR20,
VAR15,
VAR32,
VAR31,
VAR5,
VAR10,
VAR14,
VAR26,
VAR28,
VAR23,
VAR22,
VAR17,
VAR16,
VAR27,
VAR18,
VAR12,
VAR3,
VAR6
);
input VAR2;
output VAR21;
input [0:1] VAR15;
input VAR20;
input VAR32;
input VAR31;
input [0:3] VAR5;
input VAR10;
output VAR14;
output [0:3] VAR26;
output [0:3] VAR... | bsd-2-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_2.functional.v | 1,209 | module MODULE1( VAR6, VAR11, VAR8, VAR4 );
input VAR4, VAR8, VAR11;
output VAR6;
wire VAR1;
not VAR2( VAR1, VAR4 );
wire VAR3;
not VAR10( VAR3, VAR8 );
wire VAR5;
not VAR7( VAR5, VAR11 );
and VAR9( VAR6, VAR1, VAR3, VAR5 );
endmodule | apache-2.0 |
travisg/cpu | altera/top.DE1.v | 11,920 | module MODULE1
(
VAR6, VAR23, VAR19, VAR44, VAR25, VAR56, VAR52, VAR18, VAR32, VAR11, VAR1, VAR4, VAR27, VAR14, VAR13, VAR36, VAR53, VAR9, VAR57, VAR63, VAR49, VAR28, VAR45, VAR48, VAR54, VAR3, VAR64, VAR43, VAR34, VAR38, VAR2, VAR22, VAR62, VAR16, VAR10, VAR24, VAR17, VAR8, VAR59, VAR60, VAR51, VAR35, VAR21, VAR47, VA... | mit |
camsoupa/cc3000 | cc3000fpga/component/Actel/DirectCore/CoreAPB3/4.0.100/rtl/vlog/core_obfuscated/coreapb3_muxptob3.v | 5,424 | module
MODULE1
(
input
[
16
:
0
]
VAR17,
input
[
31
:
0
]
VAR43,
input
[
31
:
0
]
VAR12,
input
[
31
:
0
]
VAR41,
input
[
31
:
0
]
VAR40,
input
[
31
:
0
]
VAR5,
input
[
31
:
0
]
VAR9,
input
[
31
:
0
]
VAR28,
input
[
31
:
0
]
VAR25,
input
[
31
:
0
]
VAR2,
input
[
31
:
0
]
VAR18,
input
[
31
:
0
]
VAR24,
input
[
31
:
0
]
V... | mit |
htuNCSU/MmcCommunicationVerilog | DE2_115_MASTER/source_code/eth_shiftreg.v | 6,686 | module MODULE1(VAR8, VAR7, VAR2, VAR10, VAR3, VAR9, VAR13, VAR11, VAR14,
VAR5, VAR12, VAR4, VAR1);
input VAR8; input VAR7; input VAR2; input VAR10; input [4:0] VAR3; input [4:0] VAR9; input [15:0]VAR13; input VAR11; input [3:0] VAR14; input [1:0] VAR5;
output VAR12; output[15:0]VAR4; output VAR1;
reg [7:0] VAR6; reg [1... | gpl-3.0 |
queq/just-stuff | pov/TopFixed/Top_Show.v | 1,387 | module MODULE1(clk, VAR35, VAR6, VAR4, VAR10, VAR31, VAR27, VAR53, VAR21);
input clk;
input VAR35, VAR6;
input [76:0] VAR4;
output [6:0] VAR53;
output VAR10, VAR31, VAR27;
output VAR21;
wire [76:0] VAR52;
wire [6:0] VAR42;
wire [2:0] VAR47;
wire VAR48,VAR24, VAR3, VAR36, VAR13, VAR26, VAR15, VAR7, VAR29, VAR2, VAR16;
V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o2bb2a/sky130_fd_sc_hdll__o2bb2a.functional.pp.v | 2,193 | module MODULE1 (
VAR5 ,
VAR14,
VAR2,
VAR15 ,
VAR4 ,
VAR16,
VAR12,
VAR3 ,
VAR7
);
output VAR5 ;
input VAR14;
input VAR2;
input VAR15 ;
input VAR4 ;
input VAR16;
input VAR12;
input VAR3 ;
input VAR7 ;
wire VAR17 ;
wire VAR6 ;
wire VAR18 ;
wire VAR1;
nand VAR9 (VAR17 , VAR2, VAR14 );
or VAR8 (VAR6 , VAR4, VAR15 );
and VAR... | apache-2.0 |
myriadrf/A2300 | hdl/wca/WcaCicInterp.v | 2,697 | module MODULE1
(
input wire VAR16,
input wire reset,
input wire enable,
input wire VAR8,
input wire VAR1,
input wire [3:0] VAR14,
input wire [15:0] VAR7,
output wire [15:0] VAR12
);
reg [24+15:0] VAR13;
reg [24+15:0] VAR4;
reg [24+15:0] VAR9;
reg [24+15:0] VAR6;
reg [24+15:0] VAR15;
reg [24+15:0] VAR2;
reg [24+15:0] VA... | gpl-2.0 |
olgirard/openmsp430 | fpga/altera_de0_nano_soc/rtl/verilog/mega/ram_16x1302_dp.v | 11,752 | module MODULE1 (
VAR68,
VAR60,
VAR33,
VAR7,
VAR49,
VAR42,
VAR5,
VAR13,
VAR31,
VAR19,
VAR17,
VAR15,
VAR22,
VAR46);
input [10:0] VAR68;
input [10:0] VAR60;
input [1:0] VAR33;
input [1:0] VAR7;
input VAR49;
input VAR42;
input [15:0] VAR5;
input [15:0] VAR13;
input VAR31;
input VAR19;
input VAR17;
input VAR15;
output [15:0... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a22o/sky130_fd_sc_ms__a22o_1.v | 2,339 | module MODULE2 (
VAR6 ,
VAR11 ,
VAR2 ,
VAR9 ,
VAR1 ,
VAR7,
VAR4,
VAR8 ,
VAR5
);
output VAR6 ;
input VAR11 ;
input VAR2 ;
input VAR9 ;
input VAR1 ;
input VAR7;
input VAR4;
input VAR8 ;
input VAR5 ;
VAR10 VAR3 (
.VAR6(VAR6),
.VAR11(VAR11),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR... | apache-2.0 |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_sd_host/rtl/phy/sd_sd1_phy.v | 7,955 | module MODULE1 (
input clk,
input rst,
input VAR20,
output reg VAR22,
input VAR14,
output reg VAR1,
output reg VAR25,
input [11:0] VAR8,
input [7:0] VAR33,
output reg [7:0] VAR15,
inout [7:0] VAR31
);
localparam VAR27 = 4'h0;
localparam VAR19 = 4'h1;
localparam VAR12 = 4'h2;
localparam VAR28 = 4'h3;
localparam VAR7= 4'... | mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/acl_fp_add_sub_fast_double.v | 149,468 | module MODULE1
(
VAR8,
VAR14,
VAR5,
VAR11,
VAR12,
VAR3) ;
input VAR8;
input VAR14;
input VAR5;
input [54:0] VAR11;
input [5:0] VAR12;
output [54:0] VAR3;
tri0 VAR8;
tri1 VAR14;
tri0 VAR5;
reg [0:0] VAR6;
reg [54:0] VAR2;
wire [6:0] VAR9;
wire VAR7;
wire [31:0] VAR13;
wire [384:0] VAR1;
wire [5:0] VAR4;
wire [329:0] VAR... | mit |
peteasa/parallella-fpga | AdiHDLLib/library/common/up_tdd_cntrl.v | 16,538 | module MODULE1 (
clk,
rst,
VAR48,
VAR20,
VAR5,
VAR46,
VAR89,
VAR15,
VAR40,
VAR54,
VAR77,
VAR31,
VAR44,
VAR29,
VAR8,
VAR67,
VAR61,
VAR80,
VAR90,
VAR33,
VAR36,
VAR16,
VAR86,
VAR45,
VAR76,
VAR6,
VAR58,
VAR75,
VAR83,
VAR25,
VAR63,
VAR21,
VAR28,
VAR2,
VAR7,
VAR10,
VAR70,
VAR56,
VAR32,
VAR9,
VAR12,
VAR53,
VAR4,
VAR27);
local... | lgpl-3.0 |
katherinejlu/ece3400 | code dump/DE0_NANO.v | 5,612 | module MODULE1(
VAR13,
VAR22,
VAR39,
VAR7,
VAR1,
VAR4,
VAR34,
VAR32,
);
localparam VAR11 = 25000000; localparam VAR26 = 8'b11111111;
localparam VAR12 = 8'b0;
localparam VAR29 = 8'b11110011;
localparam VAR20 = 8'b10011011;
input VAR13;
output [7:0] VAR22;
input [1:0] VAR39;
input [3:0] VAR7;
inout [33:0] VAR1;
input [1:... | mit |
wgml/sysrek | skin_color_segm/mean_filter3x3.v | 3,394 | module MODULE1 #(
parameter [9:0] VAR3 = 83 )(
input clk,
input VAR28,
input rst,
input [7:0] VAR23,
input [7:0] VAR17,
input [7:0] VAR4,
input VAR36,
input VAR31,
input VAR13,
output [7:0] VAR8,
output [7:0] VAR16,
output [7:0] VAR11,
output VAR19,
output VAR2,
output VAR35
);
wire [10:0] VAR15;
reg [10:0] VAR27 [2:0]... | gpl-2.0 |
alonso193/proyecto1 | REG.v | 10,123 | module MODULE1(clk, VAR42, addr, VAR18, VAR1);
parameter VAR6 = 32;
parameter VAR21 = 5;
parameter VAR63 = 28;
input clk;
wire clk;
input VAR42;
wire VAR42;
input req;
wire req;
output ack;
reg ack;
input [VAR21-1: 0] addr;
wire addr;
input [VAR6-1: 0] VAR18;
wire VAR18;
output [VAR6-1: 0] VAR1;
reg VAR1;
output [15: 0... | gpl-3.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/acl_vector_to_stream_converter.v | 2,557 | module MODULE1(
VAR12, VAR14, VAR1, VAR5,
VAR13, VAR17, b1, VAR9, VAR11, VAR15,
VAR8, VAR6, VAR3, VAR7);
parameter VAR16 = 32;
input VAR12, VAR14, VAR1, VAR8, VAR3, VAR5;
input [VAR16-1:0] VAR13;
input [VAR16-1:0] b1;
input [VAR16-1:0] VAR17;
input [VAR16-1:0] VAR9;
output [VAR16-1:0] VAR11;
output [VAR16-1:0] VAR15;
o... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fill_diode/sky130_fd_sc_ms__fill_diode.behavioral.pp.v | 1,178 | module MODULE1 (
VAR2,
VAR4,
VAR1 ,
VAR3
);
input VAR2;
input VAR4;
input VAR1 ;
input VAR3 ;
endmodule | apache-2.0 |
GLADICOS/SPACEWIRESYSTEMC | rtl/DEBUG_VERILOG/write_axi_9bit.v | 1,724 | module MODULE1(
input VAR5,
input VAR2,
input VAR1,
input [8:0] VAR4,
output reg [8:0] VAR3
);
always@(posedge VAR2 or negedge VAR1 )
begin
if(!VAR1)
begin
VAR3 <= 9'd0;
end
else
begin
if(VAR5)
VAR3 <= VAR4;
end
else
VAR3 <= VAR3;
end
end
endmodule | gpl-3.0 |
intelligenttoasters/CPC2.0 | FPGA/rtl/Altera/ram2.v | 10,868 | module MODULE1 (
VAR36,
VAR57,
VAR49,
VAR29,
VAR15,
VAR50,
VAR7,
VAR48,
VAR59,
VAR24);
input [15:0] VAR36;
input [15:0] VAR57;
input VAR49;
input VAR29;
input [7:0] VAR15;
input [7:0] VAR50;
input VAR7;
input VAR48;
output [7:0] VAR59;
output [7:0] VAR24;
tri1 VAR49;
tri0 VAR7;
tri0 VAR48;
wire [7:0] VAR65;
wire [7:0] ... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nand2/gf180mcu_fd_sc_mcu9t5v0__nand2_4.functional.pp.v | 1,072 | module MODULE1( VAR7, VAR4, VAR9, VAR6, VAR2 );
input VAR9, VAR7;
inout VAR6, VAR2;
output VAR4;
wire VAR10;
not VAR3( VAR10, VAR9 );
wire VAR8;
not VAR5( VAR8, VAR7 );
or VAR1( VAR4, VAR10, VAR8 );
endmodule | apache-2.0 |
bigeagle/riffa | fpga/riffa_hdl/rotate.v | 3,074 | module MODULE1
parameter VAR10 = "VAR5",
parameter VAR3 = 4
)
(
input [VAR3-1:0] VAR7,
input [VAR6(VAR3)-1:0] VAR9,
output [VAR3-1:0] VAR12
);
wire [2*VAR3-1:0] VAR11;
wire [2*VAR3-1:0] VAR4;
wire [2*VAR3-1:0] VAR1;
wire [2*VAR3-1:0] VAR8;
assign VAR4 = {VAR7,VAR7};
assign VAR11 = {VAR7,VAR7};
assign VAR8 = VAR4 << VAR... | bsd-3-clause |
bigeagle/riffa | fpga/riffa_hdl/tx_data_pipeline.v | 7,297 | module MODULE1(
parameter VAR12 = 128,
parameter VAR21 = 1,
parameter VAR33 = 1,
parameter VAR2 = 256,
parameter VAR6 = 10,
parameter VAR9 = "VAR24"
)
(
input VAR18,
input VAR25,
input VAR23,
input [VAR12-1:0] VAR13,
input VAR27,
input [VAR3(VAR12/32)-1:0] VAR34,
input VAR31,
input [VAR3(VAR12/32)-1:0] VAR17,
output VA... | bsd-3-clause |
tmatsuya/milkymist-ml401 | cores/fmlbrg/rtl/fmlbrg_datamem.v | 3,184 | module MODULE1 #(
parameter VAR29 = 11
) (
input VAR39,
input [VAR29-1:0] VAR2,
input [7:0] VAR9,
input [63:0] VAR3,
output [63:0] do,
input [VAR29-1:0] VAR13,
output [63:0] VAR4
);
reg [7:0] VAR36[0:(1 << VAR29)-1];
reg [7:0] VAR24[0:(1 << VAR29)-1];
reg [7:0] VAR27[0:(1 << VAR29)-1];
reg [7:0] VAR15[0:(1 << VAR29)-1]... | lgpl-3.0 |
TalentlessAlpaca/Automated_Vacuum_Cleaner | j1_soc/hdl/Timer_Counter/Periph_int_clk_tst.v | 2,641 | module MODULE1;
reg clk;
reg rst;
reg VAR1;
reg [15:0] din;
reg VAR6;
reg [3:0] addr;
reg rd;
reg wr;
wire [15:0] dout;
VAR10 VAR3 (
.clk(clk),
.rst(rst),
.din(din),
.VAR6(VAR6),
.addr(addr),
.rd(rd),
.wr(wr),
.dout(dout)
);
parameter VAR8 = 20;
parameter real VAR7 = 0.5;
parameter VAR5 = 0;
reg [20:0] VAR9;
VAR2 VAR4;... | mit |
hydai/Verilog-Practice | HardwareLab/Upload/101062124_戴宏穎_Lab8/LCD_DISPLAY_CTRL.v | 5,441 | module MODULE1(VAR4, VAR7, VAR6, VAR5, reset, clk);
input clk;
input reset, VAR7, VAR6;
input [15:0] VAR5;
output [255:0] VAR4;
reg [255:0] VAR4, VAR2;
reg [4:0] counter, VAR12;
wire [255:0] VAR3, VAR10;
wire [255:0] VAR1, VAR9;
wire [255:0] VAR8, VAR11;
always @(negedge clk or negedge reset) begin
if (!reset) begin
VA... | mit |
origintfj/riscv | rv32i/rtl/merlin_rv32i_decoder.v | 16,394 | module MODULE1
(
input wire [31:0] VAR1,
output reg VAR12,
output reg VAR3,
output reg VAR9,
output reg VAR7,
output reg VAR27,
output reg VAR26,
output wire [1:0] VAR44,
output reg [VAR15] VAR24,
output reg VAR2,
output wire [4:0] VAR10,
output reg VAR40,
output wire [4:0] VAR16,
output reg VAR37,
output wire [4:0] VA... | apache-2.0 |
asicguy/gplgpu | hdl/altera_project/hb_pll/hb_pll_bb.v | 10,098 | module MODULE1 (
VAR5,
VAR3,
VAR7,
VAR2,
VAR6,
VAR4,
VAR1);
input VAR5;
input VAR3;
input VAR7;
output VAR2;
output VAR6;
output VAR4;
output VAR1;
endmodule | gpl-3.0 |
alexforencich/verilog-ethernet | rtl/rgmii_phy_if.v | 7,397 | module MODULE1 #
(
parameter VAR21 = "VAR32",
parameter VAR55 = "VAR54",
parameter VAR49 = "VAR45",
parameter VAR22 = "VAR56"
)
(
input wire clk,
input wire VAR19,
input wire rst,
output wire VAR15,
output wire VAR33,
output wire [7:0] VAR4,
output wire VAR42,
output wire VAR7,
output wire VAR14,
output wire VAR34,
out... | mit |
ZenoFuturista/fpga-shovel-and-pickaxe | verilog/sha_miner/pll.v | 17,177 | module MODULE1 (
input wire VAR5, input wire rst, output wire VAR2 );
VAR1 VAR3 (
.VAR5 (VAR5), .rst (rst), .VAR2 (VAR2), .VAR4 () );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/invkapwr/sky130_fd_sc_lp__invkapwr_1.v | 2,156 | module MODULE2 (
VAR5 ,
VAR6 ,
VAR8 ,
VAR1 ,
VAR4,
VAR2 ,
VAR3
);
output VAR5 ;
input VAR6 ;
input VAR8 ;
input VAR1 ;
input VAR4;
input VAR2 ;
input VAR3 ;
VAR9 VAR7 (
.VAR5(VAR5),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR5,
VAR6
);
output VAR5;
inpu... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/db/ACA_I_N16_Q4_syn.v | 5,703 | module MODULE1 ( VAR54, VAR123, VAR36 );
input [15:0] VAR54;
input [15:0] VAR123;
output [16:0] VAR36;
wire VAR22, VAR86, VAR162, VAR145, VAR109, VAR178, VAR183, VAR78, VAR69, VAR42, VAR12, VAR87, VAR147, VAR63,
VAR110, VAR113, VAR171, VAR90, VAR27, VAR157, VAR21, VAR127, VAR31, VAR117, VAR40, VAR94, VAR44, VAR17,
VAR7... | gpl-3.0 |
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