repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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kielfriedt/ece472 | lab4/mips_single.v | 3,199 | module MODULE1(clk, reset);
input clk, reset;
wire [31:0] VAR3;
wire [5:0] VAR39, VAR49;
wire [4:0] VAR43, VAR58, rd, VAR22;
wire [15:0] VAR14;
wire [31:0] VAR33, VAR46;
wire [25:0] VAR48;
assign VAR39 = VAR3[31:26];
assign VAR43 = VAR3[25:21];
assign VAR58 = VAR3[20:16];
assign rd = VAR3[15:11];
assign VAR22 = VAR3[10... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/tapvgnd/sky130_fd_sc_lp__tapvgnd_1.v | 1,938 | module MODULE2 (
VAR2,
VAR6,
VAR4 ,
VAR1
);
input VAR2;
input VAR6;
input VAR4 ;
input VAR1 ;
VAR3 VAR5 (
.VAR2(VAR2),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR1(VAR1)
);
endmodule
module MODULE2 ();
supply1 VAR2;
supply0 VAR6;
supply1 VAR4 ;
supply0 VAR1 ;
VAR3 VAR5 ();
endmodule | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_13.v | 12,311 | module MODULE2 (
clk,
reset,
VAR32,
VAR58,
VAR2,
VAR72,
VAR18
);
parameter VAR71 = 18;
parameter VAR77 = 13;
parameter VAR21 = 7;
localparam VAR43 = 18;
input clk;
input reset;
input VAR32;
input VAR58;
input [VAR71-1:0] VAR2; output VAR72;
output [VAR71-1:0] VAR18;
localparam VAR64 = 18; localparam VAR85 = 36; localpa... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/o21ai/sky130_fd_sc_hvl__o21ai_1.v | 2,269 | module MODULE1 (
VAR10 ,
VAR3 ,
VAR4 ,
VAR7 ,
VAR5,
VAR9,
VAR2 ,
VAR8
);
output VAR10 ;
input VAR3 ;
input VAR4 ;
input VAR7 ;
input VAR5;
input VAR9;
input VAR2 ;
input VAR8 ;
VAR1 VAR6 (
.VAR10(VAR10),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR8(VAR8)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a222oi/sky130_fd_sc_ls__a222oi_1.v | 2,542 | module MODULE2 (
VAR6 ,
VAR12 ,
VAR8 ,
VAR1 ,
VAR10 ,
VAR3 ,
VAR5 ,
VAR13,
VAR11,
VAR4 ,
VAR9
);
output VAR6 ;
input VAR12 ;
input VAR8 ;
input VAR1 ;
input VAR10 ;
input VAR3 ;
input VAR5 ;
input VAR13;
input VAR11;
input VAR4 ;
input VAR9 ;
VAR7 VAR2 (
.VAR6(VAR6),
.VAR12(VAR12),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR10(VAR1... | apache-2.0 |
ashish-17/alu_verilog | shifter.v | 2,078 | module MODULE1(
input[VAR9 - 1:0] VAR1,
input[VAR3 - 1:0] VAR6,
input[VAR10 - 1:0] VAR11,
input VAR4,
output[VAR9 - 1:0] VAR5);
reg[VAR9 - 1:0] VAR2;
reg[VAR9 - 1:0] VAR7;
reg[VAR9 - 1:0] VAR8; | gpl-3.0 |
efabless/openlane | designs/usb_cdc_core/src/usb_cdc_core.v | 32,916 | module MODULE1
(
input VAR52
,input VAR214
,input VAR201
,input [ 7:0] VAR92
,input VAR203
,input VAR227
,input VAR67
,input VAR28
,input [ 1:0] VAR44
,input VAR132
,input [ 7:0] VAR8
,input VAR53
,output [ 7:0] VAR71
,output VAR167
,output [ 1:0] VAR91
,output [ 1:0] VAR13
,output VAR255
,output VAR126
,output VAR81
,... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/cmp/rtl/dram1_ddr1_rptr.v | 4,414 | module MODULE1(
VAR33, VAR6, VAR12,
VAR31, VAR13, VAR36,
VAR20, VAR34,
VAR9, VAR17,
VAR19, VAR25, VAR11,
VAR27, VAR16, VAR2,
VAR7, VAR35,
VAR4, VAR30, VAR3,
VAR22, VAR5, VAR32,
VAR18, VAR29, VAR24,
VAR15, VAR21, VAR14,
VAR26, VAR10, VAR8, VAR23,
VAR1, VAR28
);
output VAR33;
output [31:0] VAR6;
output [255:0] VAR12;
out... | gpl-2.0 |
praveendath92/securePUF | ipcore_dir/CLOCK_TRNG.v | 4,001 | module MODULE1(VAR57,
VAR8,
VAR1,
VAR28,
VAR21);
input VAR57;
output VAR8;
output VAR1;
output VAR28;
output VAR21;
wire VAR60;
wire VAR45;
wire VAR75;
wire VAR64;
wire VAR5;
wire VAR11;
wire VAR46;
wire [4:0] VAR4;
wire [15:0] VAR31;
wire VAR6;
assign VAR46 = 0;
assign VAR4 = 5'b00000;
assign VAR31 = 16'b0000000000000... | gpl-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_dac_4d_2c_v1_00_a/hdl/verilog/cf_ddsx.v | 18,922 | module MODULE1 (
VAR66,
VAR74,
VAR93,
VAR13,
VAR70,
VAR2,
VAR123,
VAR19,
VAR29,
VAR49, VAR30, VAR65, VAR97, VAR98, VAR101, VAR12, VAR36, VAR42, VAR46, VAR117, VAR23,
VAR95,
VAR16);
input VAR66;
input VAR74;
output [15:0] VAR93;
output [15:0] VAR13;
output [15:0] VAR70;
output [15:0] VAR2;
output [15:0] VAR123;
output [... | mit |
asicguy/gplgpu | hdl/math/flt_int.v | 3,576 | module MODULE1
(
input clk,
input [31:0] VAR6,
output reg [31:0] VAR2
);
reg [22:0] VAR3;
reg [31:0] VAR4;
always @(posedge clk)
begin
VAR4 <= VAR6;
casex(VAR6[30:23])
8'b10000000:VAR3 <= 23'b10000000000000000000000;
8'b10000001:VAR3 <= 23'b11000000000000000000000;
8'b10000010:VAR3 <= 23'b11100000000000000000000;
8'b10... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and4/sky130_fd_sc_ls__and4.blackbox.v | 1,275 | module MODULE1 (
VAR7,
VAR3,
VAR4,
VAR1,
VAR5
);
output VAR7;
input VAR3;
input VAR4;
input VAR1;
input VAR5;
supply1 VAR2;
supply0 VAR9;
supply1 VAR6 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
peteg944/music-fpga | Experimental/RainbowMatrix and Partial Spectrum/OLED.v | 8,148 | module MODULE1(output VAR28,
output VAR4,
output VAR40,
output VAR31,
output VAR13,
output reset,
output VAR30,
input clk,
input rst,
input VAR6);
localparam VAR2 = 24;
localparam VAR34 = 24'd350;
localparam VAR52 = 24'h00FFFFFF;
reg VAR61, VAR57;
reg VAR25, VAR1;
reg VAR42, VAR26;
reg VAR38, VAR51;
reg [5:0] VAR58, VA... | mit |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/pixelq_op_v1_0/0d718de5/hdl/verilog/FIFO_pixelq_op_img_data_stream_0_V.v | 2,997 | module MODULE1 (
clk,
VAR8,
VAR14,
VAR1,
VAR15);
parameter VAR23 = 32'd8;
parameter VAR20 = 32'd1;
parameter VAR11 = 32'd2;
input clk;
input [VAR23-1:0] VAR8;
input VAR14;
input [VAR20-1:0] VAR1;
output [VAR23-1:0] VAR15;
reg[VAR23-1:0] VAR10 [0:VAR11-1];
integer VAR9;
always @ (posedge clk)
begin
if (VAR14)
begin
for ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi.blackbox.v | 1,463 | module MODULE1 (
VAR2 ,
VAR3,
VAR1,
VAR6 ,
VAR5
);
output VAR2 ;
input VAR3;
input VAR1;
input VAR6 ;
input VAR5 ;
supply1 VAR8;
supply0 VAR7;
supply1 VAR9 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
AloriumTechnology/XLR8Float | extras/rtl/xlr8_float/xlr8_float_add1.v | 5,201 | module MODULE1 (
input wire clk, input wire VAR1, input wire [0:0] en, input wire [31:0] VAR2, input wire [31:0] VAR5, output wire [31:0] VAR4 );
VAR3 VAR6 (
.clk (clk), .VAR1 (VAR1), .en (en), .VAR2 (VAR2), .VAR5 (VAR5), .VAR4 (VAR4) );
endmodule | gpl-3.0 |
cafe-alpha/wascafe | v12/fpga_firmware/wasca/synthesis/submodules/altera_up_rs232_counters.v | 5,450 | module MODULE1 (
clk,
reset,
VAR1,
VAR6,
VAR10,
VAR8
);
parameter VAR5 = 9; parameter VAR3 = 433;
parameter VAR4 = 216;
parameter VAR7 = 11;
input clk;
input reset;
input VAR1;
output reg VAR6;
output reg VAR10;
output reg VAR8;
reg [(VAR5-1):0] VAR2;
reg [ 3: 0] VAR9;
always @(posedge clk)
begin
if (reset)
VAR2 <= {VA... | gpl-2.0 |
asicguy/gplgpu | hdl/altera_rams/dpram_64x256.v | 9,649 | module MODULE1 (
VAR11,
VAR22,
VAR14,
VAR43,
VAR6,
VAR42,
VAR33);
input [7:0] VAR11;
input VAR22;
input [63:0] VAR14;
input [7:0] VAR43;
input [7:0] VAR6;
input VAR42;
output [63:0] VAR33;
wire [63:0] VAR21;
wire [63:0] VAR33 = VAR21[63:0];
VAR59 VAR48 (
.VAR31 (VAR42),
.VAR54 (VAR22),
.VAR11 (VAR11),
.VAR46 (VAR6),
.V... | gpl-3.0 |
rwarmstr/Vivado_IP | mdio_1to2/src/mdio_1to2.v | 1,804 | module MODULE1
(input wire VAR2,
input wire VAR4,
input wire VAR12,
output wire VAR1,
output wire VAR7,
output wire VAR3,
output wire VAR9,
input wire VAR5,
output wire VAR10,
output wire VAR11,
output wire VAR6,
input wire VAR8
);
assign VAR7 = VAR2;
assign VAR9 = VAR12;
assign VAR3 = VAR4;
assign VAR10 = VAR2;
assign... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlxbp/sky130_fd_sc_hd__dlxbp.functional.v | 1,640 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR8 ,
VAR10
);
output VAR3 ;
output VAR5 ;
input VAR8 ;
input VAR10;
wire VAR4;
VAR7 VAR6 VAR1 (VAR4 , VAR8, VAR10 );
buf VAR9 (VAR3 , VAR4 );
not VAR2 (VAR5 , VAR4 );
endmodule | apache-2.0 |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_abot/db/ip/niosii/submodules/niosii_onchip_memory2_0.v | 3,040 | module MODULE1 (
address,
VAR28,
VAR25,
clk,
VAR20,
reset,
VAR17,
write,
VAR40,
VAR32
)
;
parameter VAR5 = "VAR3:/VAR16/VAR42/VAR22/VAR9/VAR33/VAR27/VAR10/MODULE1.VAR11";
output [ 31: 0] VAR32;
input [ 13: 0] address;
input [ 3: 0] VAR28;
input VAR25;
input clk;
input VAR20;
input reset;
input VAR17;
input write;
input... | mit |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_jaxa/jaxa/synthesis/submodules/jaxa_creditCount.v | 1,850 | module MODULE1 (
address,
clk,
VAR5,
VAR4,
VAR1
)
;
output [ 31: 0] VAR1;
input [ 1: 0] address;
input clk;
input [ 5: 0] VAR5;
input VAR4;
wire VAR6;
wire [ 5: 0] VAR2;
wire [ 5: 0] VAR3;
reg [ 31: 0] VAR1;
assign VAR6 = 1;
assign VAR3 = {6 {(address == 0)}} & VAR2;
always @(posedge clk or negedge VAR4)
begin
if (VAR4... | gpl-3.0 |
archlabo/Frix | fpga/nexys4/rtl/system.v | 36,241 | module MODULE1 (
input wire VAR311,
input wire VAR113,
input wire VAR28,
input wire VAR247,
output wire VAR76,
output wire VAR74,
output wire VAR35,
output wire VAR286,
output wire VAR264,
output wire VAR234,
output wire VAR168,
inout wire [15:0] VAR43,
output wire [22:0] VAR62,
output wire VAR38,
output wire VAR219,
o... | bsd-2-clause |
eda-globetrotter/PicenoDecoders | zhiyang_and_andrew/bmu.v | 2,409 | module MODULE1 (VAR9, VAR7, VAR2, VAR3, VAR5, VAR8, VAR10, VAR4, VAR1, VAR6);
output [1:0] VAR2, VAR3, VAR5, VAR8, VAR10, VAR4, VAR1, VAR6;
input VAR9, VAR7;
reg [1:0] VAR2, VAR3, VAR5, VAR8, VAR10, VAR4, VAR1, VAR6;
always@ (VAR9 or VAR7)
begin
if (VAR9==0 && VAR7==0)
begin
VAR2 <= 2'd0; VAR3 <= 2'd2; VAR5 <= 2'd2; VA... | mit |
which0326/ca_project2 | code/EX_MEM.v | 1,058 | module MODULE1(input clk,
input reset,
input [1:0] VAR2,
input [1:0] VAR5,
input [31:0] VAR11,
input [4:0] VAR7,
input [31:0] VAR8,
input VAR4,
output reg VAR6,
output reg VAR10,
output reg[1:0] VAR1,
output reg[31:0] VAR9,
output reg[4:0] VAR3,
output reg[31:0] VAR12);
always@(posedge reset)begin
VAR6 = 0;
VAR10 = 0;
... | cc0-1.0 |
hoglet67/CoPro6502 | src/zet/tube/wb_tube.v | 4,391 | module MODULE1 #(
parameter VAR5 = 0 ) (
input clk,
input reset,
input VAR21,
input VAR10,
input VAR4,
output reg VAR3,
input VAR16,
input [2:0] VAR20,
input [1:0] VAR14,
input [15:0] VAR8,
output reg [15:0] VAR13,
output reg [2:0] VAR23,
inout [7:0] VAR11,
output reg VAR17, output reg VAR18, output reg VAR6 );
wire VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfxtp/sky130_fd_sc_hs__dfxtp.symbol.v | 1,278 | module MODULE1 (
input VAR3 ,
output VAR2 ,
input VAR4
);
supply1 VAR1;
supply0 VAR5;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_dff_pr/sky130_fd_sc_lp__udp_dff_pr.symbol.v | 1,317 | module MODULE1 (
input VAR2 ,
output VAR4 ,
input VAR3,
input VAR1
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfstp/sky130_fd_sc_hdll__sdfstp_2.v | 2,527 | module MODULE2 (
VAR6 ,
VAR12 ,
VAR5 ,
VAR10 ,
VAR11 ,
VAR9,
VAR4 ,
VAR2 ,
VAR3 ,
VAR1
);
output VAR6 ;
input VAR12 ;
input VAR5 ;
input VAR10 ;
input VAR11 ;
input VAR9;
input VAR4 ;
input VAR2 ;
input VAR3 ;
input VAR1 ;
VAR8 VAR7 (
.VAR6(VAR6),
.VAR12(VAR12),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR11(VAR11),
.VAR9(VAR9),
.... | apache-2.0 |
borti4938/sd2snes | verilog/sd2snes_sa1/msu_databuf.v | 9,172 | module MODULE1 (
VAR35,
VAR29,
VAR17,
VAR38,
VAR19,
VAR11);
input VAR35;
input [7:0] VAR29;
input [13:0] VAR17;
input [13:0] VAR38;
input VAR19;
output [7:0] VAR11;
tri1 VAR35;
tri0 VAR19;
wire [7:0] VAR41;
wire [7:0] VAR11 = VAR41[7:0];
VAR33 VAR44 (
.VAR21 (VAR38),
.VAR43 (VAR17),
.VAR34 (VAR35),
.VAR5 (VAR29),
.VAR1... | gpl-2.0 |
walkthetalk/fsref | ip/fsa/src/include/fsa_detect_header.v | 5,521 | module MODULE1 # (
parameter integer VAR8 = 12,
parameter integer VAR21 = 12
) (
input clk,
input VAR39,
input wire VAR37 ,
input wire VAR14 ,
input wire VAR24 ,
input wire VAR41 ,
input wire VAR20 ,
input wire VAR33 ,
input wire VAR1 ,
input wire VAR35 ,
input wire [VAR21-1:0] VAR44 ,
input wire [VAR21-1:0] VAR16 ,
in... | gpl-3.0 |
eda-globetrotter/MarcheProcessor | processor/syn/src/mult.v | 61,285 | module MODULE1 (VAR14,VAR28,VAR31,VAR22,VAR6);
output [0:127] VAR6;
input [0:127] VAR14;
input [0:127] VAR28;
input [0:1] VAR31;
input [0:4] VAR22;
integer VAR13;
reg [0:127] VAR6;
reg [0:127] VAR18;
reg [0:15] VAR11;
reg [0:15] VAR8;
reg [0:15] VAR5;
reg [0:15] VAR24;
reg [0:15] VAR9;
reg [0:15] VAR29;
reg [0:15] VAR3... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_2.behavioral.pp.v | 1,164 | module MODULE1( VAR7, VAR5, VAR6, VAR1 );
input VAR7;
inout VAR6, VAR1;
output VAR5;
VAR2 VAR3(.VAR7(VAR7),.VAR5(VAR5),.VAR6(VAR6),.VAR1(VAR1));
VAR2 VAR4(.VAR7(VAR7),.VAR5(VAR5),.VAR6(VAR6),.VAR1(VAR1)); | apache-2.0 |
ptracton/wb_dsp | rtl/wb_dsp_slave_registers.v | 6,341 | module MODULE1 (
VAR19, VAR9, VAR18, VAR11, VAR4,
VAR5, VAR13,
VAR3, VAR7, interrupt,
VAR1, VAR15, VAR8, VAR14, VAR21, VAR24, VAR6,
VAR17, VAR12, VAR2, VAR20
) ;
parameter VAR10 = 32;
parameter VAR22 = 8;
parameter VAR23 = 0;
input VAR1;
input VAR15;
input [VAR22-1:0] VAR8;
input [VAR10-1:0] VAR14;
input [3:0] VAR21;
i... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21a/sky130_fd_sc_hs__o21a.pp.symbol.v | 1,311 | module MODULE1 (
input VAR5 ,
input VAR1 ,
input VAR2 ,
output VAR6 ,
input VAR4,
input VAR3
);
endmodule | apache-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/acl_fp_div_s5.v | 58,740 | module MODULE1
(
VAR17,
VAR97,
VAR189,
VAR237,
VAR153,
VAR166) ;
input VAR17;
input VAR97;
input VAR189;
input [31:0] VAR237;
input [31:0] VAR153;
output [31:0] VAR166;
tri0 VAR17;
tri1 VAR97;
wire [8:0] VAR219;
reg VAR213;
reg VAR26;
reg VAR156;
reg VAR10;
reg VAR216;
reg VAR74;
reg VAR96;
reg VAR59;
reg VAR202;
reg V... | mit |
plindstroem/oh | elink/hdl/erx.v | 7,866 | module MODULE1 (
VAR28, VAR29, VAR54, VAR31,
VAR51, VAR34, VAR47, VAR15, VAR32,
VAR10, VAR23, VAR19, timeout, VAR50,
VAR52,
VAR4,VAR45, VAR30, VAR25, VAR26, VAR36,
VAR40, VAR37, VAR5, VAR27, VAR43,
VAR39, VAR2, VAR9, VAR33, VAR8,
VAR21
);
parameter VAR20 = 32;
parameter VAR41 = 32;
parameter VAR49 = 104;
parameter VAR4... | gpl-3.0 |
subailong/miaow | src/verilog/rtl/dispatcher/resource_update_buffer.v | 4,785 | module MODULE1
(
VAR11, VAR1,
VAR25,
clk, rst, VAR24, VAR6,
VAR13, VAR17
) ;
parameter VAR4 = 10;
parameter VAR23 = 3;
parameter VAR12 = 8;
input clk, rst;
input [VAR12-1:0] VAR24;
input [VAR12*(VAR4+1)-1 :0] VAR6;
input [VAR12*(VAR4)-1 :0] VAR13;
output [VAR12-1:0] VAR11;
input [VAR12-1:0] VAR17;
output [VAR4 :0] VAR1... | bsd-3-clause |
FAST-Switch/fast | projects/SDTS/example/hw-src/ddr2/alt_ddrx_input_if.v | 31,106 | module MODULE1
VAR94 = 7,
VAR3 = 64,
VAR69 = 0,
VAR115 = 0,
VAR167 = 0,
VAR113 = 4,
VAR134 = 5,
VAR117 = 2,
VAR186 = 2,
VAR55 = 9,
VAR162 = 64,
VAR112 = 33,
VAR174 = 6,
VAR180 = 4,
VAR110 = 4,
VAR160 = 16,
VAR88 = 12,
VAR65 = 3,
VAR56 = 2,
VAR141 = 2,
VAR121 = 8,
VAR19 = 1,
VAR61 = "VAR5",
VAR47 = 8,
VAR16 = 12,
VAR33 ... | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dly_ctrl.v | 23,402 | module MODULE1 #
(
parameter VAR37 = 100, parameter VAR7 = 64, parameter VAR25 = 3, parameter VAR86 = 8, parameter VAR45 = 1, parameter VAR44 = 5, parameter VAR29 = "VAR39", parameter VAR67 = "VAR81", parameter VAR84 = "VAR81", parameter VAR2 = "VAR87", parameter VAR33 = 4, parameter VAR8 = 4, parameter VAR78 = 0, para... | lgpl-3.0 |
trevortheblack/NewLondo16 | Verilog/decode.v | 2,787 | module MODULE1(VAR15,
VAR16, VAR6, VAR10,
VAR5, VAR3, logic, memory,
VAR11, VAR14, VAR8,
VAR1
);
input [15:0] VAR15;
output [3:0] VAR16, VAR6, VAR10;
output [4:0] VAR11; output [2:0] VAR14; output [2:0] VAR8;
output reg VAR5; output reg VAR3; output reg logic; output reg memory;
output [2:0] VAR1;
assign VAR16 = VAR15[... | mit |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_ic_ram.v | 5,609 | module MODULE1(
clk, rst,
VAR3, VAR4, VAR7,
addr, en, VAR5, VAR12, VAR1
);
parameter VAR11 = VAR17;
parameter VAR19 = VAR10;
input clk;
input rst;
input [VAR19-1:0] addr;
input en;
input [3:0] VAR5;
input [VAR11-1:0] VAR12;
output [VAR11-1:0] VAR1;
input VAR3;
input [VAR15 - 1:0] VAR7;
output VAR4;
assign VAR1 = {VAR11... | gpl-3.0 |
spesialstyrker/boula | gen/PCIe/example_design/PIO_TO_CTRL.v | 3,929 | module MODULE1 (
clk,
VAR6,
VAR3,
VAR2,
VAR5,
VAR1
);
input clk;
input VAR6;
input VAR3;
input VAR2;
input VAR5;
output VAR1;
reg VAR4;
reg VAR1;
always @ ( posedge clk or negedge VAR6 ) begin
if (!VAR6 ) begin
VAR4 <= 0;
end else begin
if (!VAR4 && VAR3)
VAR4 <= 1'b1;
end
else if (VAR2)
VAR4 <= 1'b0;
end
end
always @ ... | gpl-2.0 |
MCDELTAT/CSE311 | lab1_reverse/bi_directional_shift.v | 1,509 | module MODULE1(
input wire [7:0] din,
input wire [2:0] VAR4,
input wire VAR9, output wire [7:0] VAR8
);
wire [7:0] VAR12;
wire [7:0] VAR6;
wire [7:0] VAR2;
wire [7:0] VAR16;
VAR5 VAR3 (
.din (din),
.dout (VAR12)
);
VAR11 VAR13 (
.VAR15 (din),
.VAR14 (VAR12),
.select (VAR9),
.VAR17 (VAR16)
);
VAR1 VAR10 (
.din (VAR16),
... | mit |
olajep/oh | src/common/hdl/oh_dsync.v | 1,373 | module MODULE1 #(parameter VAR3 = 2, parameter VAR7 = 0 )
(
input clk, input VAR5, input din, output dout );
localparam VAR2 = VAR6;
generate
if(VAR2)
begin : VAR4
VAR1 VAR1 (.clk(clk),
.VAR5(VAR5),
.din(din),
.dout(dout));
end
else
begin : VAR4
reg [VAR3:0] VAR8;
always @ (posedge clk or negedge VAR5)
if(!VAR5)
VAR8[V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/diode/sky130_fd_sc_ls__diode.functional.v | 1,081 | module MODULE1 (
VAR1
);
input VAR1;
endmodule | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_dac_1c_2p_f_v1_00_a/hdl/verilog/cf_dac_1c_2p_f.v | 10,864 | module MODULE1 (
rst,
VAR69,
VAR75,
VAR11,
VAR79,
VAR46,
VAR63,
VAR27,
VAR28,
VAR8,
VAR38,
VAR10,
VAR59,
VAR24,
VAR37,
VAR64,
VAR25,
VAR72,
VAR4,
VAR43,
VAR87,
VAR17,
VAR61,
VAR77,
VAR2,
VAR80,
VAR76,
VAR36,
VAR14,
VAR1,
VAR3,
VAR58,
VAR68);
input rst;
input VAR69;
input VAR75;
output VAR11;
output VAR79;
output VAR46;... | mit |
YosysHQ/yosys | techlibs/intel/cycloneiv/cells_arith.v | 3,850 | module MODULE1(
module 80cycloneivalu (VAR3, VAR9, VAR17, VAR16, VAR1, VAR10, VAR4);
parameter VAR25 = 0;
parameter VAR27 = 0;
parameter VAR11 = 1;
parameter VAR31 = 1;
parameter VAR33 = 1;
input [VAR11-1:0] VAR3;
input [VAR31-1:0] VAR9;
output [VAR33-1:0] VAR1, VAR10;
input VAR17, VAR16;
output [VAR33:0] VAR4;
wire VA... | isc |
DougFirErickson/parallella-hw | boards/archive/gen1.1/fpga/hdl/ewrapper_io_tx_slow.v | 8,232 | module MODULE1 (
VAR13, VAR37, VAR43,
VAR34,
VAR41, VAR26, VAR1, VAR39, VAR51,
VAR59
);
input VAR41; input VAR26; input VAR1; input VAR39;
input VAR51;
input [71:0] VAR59;
output [8:0] VAR13;
output [8:0] VAR37;
output VAR43;
output VAR34;
reg [1:0] VAR7;
reg VAR70;
reg VAR46;
reg [8:0] VAR61;
reg [8:0] VAR22;
reg [71:... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and2/sky130_fd_sc_lp__and2_4.v | 2,086 | module MODULE2 (
VAR6 ,
VAR8 ,
VAR2 ,
VAR7,
VAR9,
VAR3 ,
VAR4
);
output VAR6 ;
input VAR8 ;
input VAR2 ;
input VAR7;
input VAR9;
input VAR3 ;
input VAR4 ;
VAR1 VAR5 (
.VAR6(VAR6),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR6,
VAR8,
VAR2
);
output VAR6;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputiso1p/sky130_fd_sc_lp__inputiso1p.behavioral.v | 1,367 | module MODULE1 (
VAR4 ,
VAR6 ,
VAR3
);
output VAR4 ;
input VAR6 ;
input VAR3;
supply1 VAR1;
supply0 VAR8;
supply1 VAR7 ;
supply0 VAR5 ;
or VAR2 (VAR4 , VAR6, VAR3 );
endmodule | apache-2.0 |
mithro/soft-utmi | hdl/third_party/XAPP1064-serdes-macros/Verilog_Source/Macros/serdes_n_to_1_ddr_s8_se.v | 8,834 | module MODULE1 (VAR31, VAR1, VAR52, reset, VAR44, VAR10, VAR24) ;
parameter integer VAR13 = 8 ; parameter integer VAR3 = 16 ;
input VAR31 ; input VAR1 ; input VAR52 ; input reset ; input VAR44 ; input [(VAR3*VAR13)-1:0] VAR10 ; output [VAR3-1:0] VAR24 ;
wire [VAR3:0] VAR36 ; wire [VAR3:0] VAR32 ; wire [VAR3:0] VAR18 ; ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o31ai/sky130_fd_sc_hdll__o31ai.pp.blackbox.v | 1,384 | module MODULE1 (
VAR8 ,
VAR6 ,
VAR5 ,
VAR3 ,
VAR1 ,
VAR7,
VAR2,
VAR9 ,
VAR4
);
output VAR8 ;
input VAR6 ;
input VAR5 ;
input VAR3 ;
input VAR1 ;
input VAR7;
input VAR2;
input VAR9 ;
input VAR4 ;
endmodule | apache-2.0 |
everskar2013/PentiumX | Hardware/Code/alu_correctHalf.v | 2,856 | module MODULE1(
VAR21,
VAR3,
VAR13,
VAR25,
VAR24,
VAR10,
VAR27
);
input wire [31: 0] VAR21, VAR3;
input wire [ 3: 0] VAR13;
input wire [ 4: 0] VAR25;
output reg [31: 0] VAR24;
output wire VAR10;
output wire VAR27;
wire [31: 0] VAR16, VAR9, VAR2, VAR5, VAR12, VAR14,
VAR18, VAR28, VAR4, VAR15, VAR6, VAR20, VAR8, VAR26, V... | mit |
hoglet67/CoPro6502 | src/ICAP_core.v | 17,073 | module MODULE1
(
input VAR35,
input [4:0] VAR63,
input VAR26,
input VAR34,
input [3:0] VAR6,
output [3:0] VAR48,
output [3:0] VAR27,
output VAR9,
);
reg [1:0] clk;
reg VAR52;
reg [15:0] VAR37;
reg VAR41;
reg VAR15;
wire [15:0] VAR49;
reg [15:0] VAR61;
reg [15:0] VAR18;
reg VAR66;
reg VAR51;
reg [3:0] VAR8 = 4'b0000;
r... | gpl-3.0 |
horia141/bachelor-thesis | prj/applications/RedRectangle/RedRectangle.v | 1,824 | module MODULE1(VAR23,VAR7,reset,VAR22,VAR32,VAR19,VAR37,VAR41);
input wire VAR23;
input wire VAR7;
input wire reset;
output wire VAR22;
output wire VAR32;
output wire VAR19;
output wire VAR37;
output wire VAR41;
wire [7:0] VAR20;
wire [11:0] VAR43;
wire [7:0] VAR24;
wire [19:0] VAR28;
wire [4095:0] VAR15;
wire [7:0] VA... | mit |
JakeMercer/mac | MAC/rtl/mac/mac_fifo/fifo/fifo.v | 5,070 | module MODULE1
parameter VAR7 = 8,
parameter VAR3 = 8,
parameter VAR5 = 12
)
(
input wire reset,
output reg VAR16,
input wire [VAR7-1:0] VAR11,
input wire VAR8,
input wire VAR6,
output reg [VAR5-1:0] VAR1,
input wire VAR13,
input wire [VAR5-1:0] VAR10,
output reg [VAR3-1:0] VAR12,
input wire VAR2,
input wire VAR4,
outp... | mit |
ShepardSiegel/ocpi | coregen/dram_v6_mig39_2/mig_39_2/example_design/rtl/phy/phy_data_io.v | 16,996 | module MODULE1 #
(
parameter VAR53 = 100, parameter VAR58 = 2, parameter VAR5 = 3000, parameter VAR52 = 8, parameter VAR15 = 9, parameter VAR76 = 72, parameter VAR71 = 9, parameter VAR64 = "VAR96",
parameter VAR17 = 5, parameter VAR61 = "VAR6", parameter VAR40 = 300.0, parameter VAR62 = "VAR6", parameter VAR74 = "VAR9"... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o211a/sky130_fd_sc_lp__o211a_2.v | 2,348 | module MODULE2 (
VAR4 ,
VAR8 ,
VAR9 ,
VAR3 ,
VAR10 ,
VAR1,
VAR7,
VAR11 ,
VAR6
);
output VAR4 ;
input VAR8 ;
input VAR9 ;
input VAR3 ;
input VAR10 ;
input VAR1;
input VAR7;
input VAR11 ;
input VAR6 ;
VAR2 VAR5 (
.VAR4(VAR4),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR11(VAR11),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/einvn/sky130_fd_sc_hdll__einvn_4.v | 2,166 | module MODULE1 (
VAR7 ,
VAR9 ,
VAR4,
VAR2,
VAR8,
VAR5 ,
VAR6
);
output VAR7 ;
input VAR9 ;
input VAR4;
input VAR2;
input VAR8;
input VAR5 ;
input VAR6 ;
VAR3 VAR1 (
.VAR7(VAR7),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR7 ,
VAR9 ,
VAR4
);
output VAR7 ;... | apache-2.0 |
bangonkali/quartus-sockit | soc_system/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v | 1,158 | module MODULE1
VAR9 = 32,
VAR10 = 32,
VAR3 = 32,
VAR8 = 16, VAR7 = 32,
VAR5 = 8,
VAR1 = 1,
VAR2 = 8,
VAR6 = 1,
VAR4 = 1
) (
);
endmodule | mit |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/cabac/cabac_binari_cu.v | 40,677 | module MODULE1(
clk ,
VAR97 ,
VAR86 ,
VAR134 ,
VAR35 ,
VAR113 ,
VAR135 ,
VAR31 ,
VAR161 ,
VAR87 ,
VAR45 ,
VAR185 ,
VAR52 ,
VAR58 ,
VAR47 ,
VAR186 ,
VAR64 ,
VAR102 ,
VAR80 ,
VAR112 ,
VAR88 ,
VAR203 ,
VAR123 ,
VAR99 ,
VAR118 ,
VAR110 ,
VAR90 ,
VAR66 ,
VAR81 ,
VAR142 ,
VAR69 ,
VAR98 ,
VAR36 ,
VAR39 ,
VAR23 ,
VAR63
);
inpu... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/util_pmod_fmeter/util_pmod_fmeter.v | 5,588 | module MODULE1 (
VAR68,
VAR4,
VAR11,
VAR54,
VAR34,
VAR31,
VAR2,
VAR21,
VAR49,
VAR17,
VAR40,
VAR52,
VAR41,
VAR6,
VAR66,
VAR25,
VAR18,
VAR67,
VAR61,
VAR14,
VAR24);
parameter VAR38 = 0;
input VAR68;
input VAR4;
input VAR11;
input VAR54;
input VAR34;
input [31:0] VAR31;
output VAR2;
input VAR21;
input [31:0] VAR49;
input [... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/to_send/ngnp_added_monitor/ngnp/src/tmp/yacc/yacc2.v | 6,643 | module MODULE1(VAR90,VAR9, VAR70,VAR31);
input VAR90;
input VAR9;
input VAR70;
output VAR31;
wire [31:0] VAR29,VAR65;
wire VAR18;
wire [1:0] VAR56;
wire [1:0] VAR36;
wire VAR33,VAR86;
wire [1:0] VAR102,VAR12;
wire [3:0] VAR78;
wire [1:0] VAR95;
wire [25:0] VAR27,VAR108;
wire [4:0] VAR94,VAR19;
wire [4:0] VAR97,VAR30,VA... | mit |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/rtl/cpu/mem_ctrl.v | 3,787 | module MODULE1 (
input wire VAR13,
input wire [VAR1] VAR3,
input wire [VAR6] VAR17,
input wire [VAR6] VAR12,
input wire [VAR6] VAR16,
output wire [VAR15] addr,
output reg VAR24,
output reg VAR18,
output wire [VAR6] VAR5,
output reg [VAR6] out ,
output reg VAR19
);
wire [VAR14] VAR23;
assign VAR5 = VAR17;
assign addr = ... | apache-2.0 |
camacazio/icestick_JSTK2_ORGB | source/PmodJSTK.v | 3,794 | module MODULE1(
VAR8,
VAR3,
VAR22,
VAR21,
VAR20,
VAR17,
VAR10,
VAR19,
VAR18
);
input VAR8; input VAR3; input VAR22; input [39:0] VAR21; input VAR20; output VAR17; output VAR10; output VAR19; output [39:0] VAR18;
wire VAR17;
wire VAR10;
wire VAR19;
wire [39:0] VAR18;
wire VAR1; wire [7:0] VAR16; wire [7:0] VAR4; wire VA... | gpl-3.0 |
Ricky-Gong/LegoCar | DE0-Nano/DE0Course/NIOS_Sys/synthesis/submodules/NIOS_Sys_epcs_flash_controller_0.v | 17,630 | module MODULE1 (
VAR42,
clk,
VAR20,
VAR6,
VAR56,
VAR30,
VAR39,
VAR62,
VAR47,
VAR73,
VAR70,
VAR72,
VAR28,
VAR80,
irq,
VAR57
)
;
output VAR47;
output VAR73;
output VAR70;
output [ 15: 0] VAR72;
output VAR28;
output VAR80;
output irq;
output VAR57;
input VAR42;
input clk;
input [ 15: 0] VAR20;
input VAR6;
input [ 2: 0] VA... | gpl-2.0 |
bluespec/Flute | builds/AWSteria_Core_Flute_RV64_Linux/Verilog_RTL_PLATFORM_VCU118/mkCSR_MIE.v | 5,874 | module MODULE1(VAR34,
VAR25,
VAR29,
VAR4,
VAR26,
VAR6,
VAR40,
VAR38,
VAR16,
VAR5,
VAR14,
VAR8,
VAR11);
input VAR34;
input VAR25;
input VAR29;
output [63 : 0] VAR4;
input [27 : 0] VAR26;
input [63 : 0] VAR6;
input VAR40;
output [63 : 0] VAR38;
output [63 : 0] VAR16;
input [27 : 0] VAR5;
input [63 : 0] VAR14;
input VAR8;... | apache-2.0 |
secworks/keywrap | src/rtl/keywrap_core.v | 5,805 | module MODULE1(
input wire clk,
input wire VAR14,
input wire VAR39,
input wire VAR31,
input wire VAR6,
output wire ready,
input wire [255 : 0] VAR1,
input wire VAR7,
input wire [63 : 0] VAR41,
output wire [63 : 0] VAR34,
input wire VAR25
);
localparam VAR43 = 0;
localparam VAR46 = 3'h0;
localparam VAR8 = 3'h1;
localpar... | bsd-2-clause |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_clkgen_v1_00_a/hdl/verilog/user_logic.v | 6,102 | module MODULE1 (
VAR16,
clk,
VAR6,
VAR18,
VAR12,
VAR24,
VAR23,
VAR4,
VAR3,
VAR10,
VAR25,
VAR5);
parameter VAR20 = 32;
parameter VAR13 = 32;
parameter VAR14 = 0;
input VAR16;
output clk;
input VAR6;
input VAR18;
input [31:0] VAR12;
input [ 3:0] VAR24;
input [31:0] VAR23;
input [31:0] VAR4;
output [31:0] VAR3;
output VAR... | mit |
donnaware/AGC | rtl/de0/modules/SPICmd1.v | 6,395 | module MODULE1(
input clk, input VAR22, input VAR26, input VAR12, output VAR19, input VAR21, input [7:0] VAR15, output reg [7:0] VAR29, output reg [4:0] VAR11, output [3:0] VAR13, output [3:0] VAR25, output VAR18, output VAR16, output VAR1, output reg VAR17, output reg VAR31, output reg VAR28, output VAR7, output VAR14... | gpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_dac_1c_2p_f_v1_00_a/hdl/verilog/cf_dac_if.v | 13,939 | module MODULE1 (
rst,
VAR114,
VAR113,
VAR26,
VAR107,
VAR103,
VAR52,
VAR13,
VAR82,
VAR88,
VAR66,
VAR38,
VAR93,
VAR83,
VAR106,
VAR1,
VAR21,
VAR30,
VAR96,
VAR55,
VAR67,
VAR63,
VAR71,
VAR89,
VAR24,
VAR17);
input rst;
input VAR114;
input VAR113;
output VAR26;
output VAR107;
output VAR103;
output VAR52;
output [13:0] VAR13;
... | mit |
deepakcu/maestro | fpga/DE4_Ethernet_0/src/ethernet_rx_buffer.v | 9,356 | module MODULE1 (
VAR27,
VAR37,
VAR46,
VAR21,
VAR18,
VAR36,
VAR16);
input VAR27;
input [31:0] VAR37;
input [9:0] VAR46;
input VAR21;
input [9:0] VAR18;
input VAR36;
output [31:0] VAR16;
tri1 VAR27;
tri1 VAR21;
tri0 VAR36;
wire [31:0] VAR30;
wire [31:0] VAR16 = VAR30[31:0];
VAR29 VAR40 (
.VAR38 (VAR18),
.VAR61 (VAR27),
.... | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/custom/power_trig.v | 4,113 | module MODULE1
parameter VAR8 = 24,
parameter VAR49 = 0
)
(
input VAR48, input reset, input VAR43, input enable,
input VAR46, input [7:0] VAR52, input [31:0] VAR36,
input [VAR8-1:0] VAR27,
input [VAR8-1:0] VAR45,
output [VAR8-1:0] VAR2,
output [VAR8-1:0] VAR39,
input [31:0] VAR28,
input VAR53, output VAR47,
output [31:... | gpl-2.0 |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_dwidth_converter_v2_1/d98fa611/hdl/verilog/axi_dwidth_converter_v2_1_axi4lite_downsizer.v | 14,619 | module MODULE1 #
(
parameter VAR3 = "none",
parameter integer VAR49 = 32,
parameter integer VAR42 = 1,
parameter integer VAR66 = 1
)
(
input wire VAR33,
input wire VAR8,
input wire [VAR49-1:0] VAR2,
input wire [3-1:0] VAR41,
input wire VAR27,
output wire VAR61,
input wire [64-1:0] VAR58,
input wire [64/8-1:0] VAR45,
in... | mit |
fabianz66/cursos-tec | taller-digital/Lab3/laboratorio3/Comparador.v | 1,130 | module MODULE1(VAR6, reset, VAR5, VAR2,
VAR7, VAR4, VAR3);
input VAR6, reset, VAR7;
input [3:0] VAR5, VAR2;
output VAR4, VAR3;
reg [3:0] VAR1;
assign VAR4 = (VAR5 == VAR1);
assign VAR3 = ~VAR4;
always @( posedge VAR6 or posedge reset)
begin
if(reset)
begin
VAR1 <= 4'b0;
end
else if (VAR7)
begin
VAR1 <= VAR2;
end
end
en... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv3sd3/sky130_fd_sc_ls__clkdlyinv3sd3.pp.blackbox.v | 1,344 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR6,
VAR3,
VAR2 ,
VAR4
);
output VAR1 ;
input VAR5 ;
input VAR6;
input VAR3;
input VAR2 ;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_mux_2to1_n/sky130_fd_sc_lp__udp_mux_2to1_n.symbol.v | 1,289 | module MODULE1 (
input VAR1,
input VAR4,
output VAR2 ,
input VAR3
);
endmodule | apache-2.0 |
freecores/altor32 | rtl/soc/soc_pif8.v | 7,516 | module MODULE1
(
input VAR40,
input VAR10,
output [7:0] VAR14,
output [31:0] VAR18,
input [31:0] VAR1,
output reg VAR20,
output reg VAR16,
output [7:0] VAR6,
output [31:0] VAR33,
input [31:0] VAR8,
output reg VAR35,
output reg VAR5,
output [7:0] VAR25,
output [31:0] VAR11,
input [31:0] VAR45,
output reg VAR13,
output r... | lgpl-3.0 |
cafe-alpha/wascafe | v12/fpga_firmware/wasca/synthesis/submodules/wasca_onchip_memory2_0.v | 2,887 | module MODULE1 (
address,
VAR6,
VAR9,
clk,
VAR2,
reset,
VAR11,
write,
VAR32,
VAR20
)
;
output [ 31: 0] VAR20;
input [ 11: 0] address;
input [ 3: 0] VAR6;
input VAR9;
input clk;
input VAR2;
input reset;
input VAR11;
input write;
input [ 31: 0] VAR32;
wire VAR19;
wire [ 31: 0] VAR20;
wire VAR14;
assign VAR14 = VAR9 & wri... | gpl-2.0 |
gigglesninja/digital-system-design | lab8_uart_tx/uart_tx.v | 4,087 | module MODULE1(clk, reset, VAR1, VAR14, din, dout, VAR18, addr);
input clk, reset, VAR1, VAR14;
input [7:0] din;
output [7:0] dout;
output VAR18; input [2:0] addr;
reg [7:0] VAR4, dout;
reg [9:0] VAR23;
reg VAR29, VAR16, VAR27, VAR9, VAR13;
reg VAR21, VAR33, VAR15, VAR5, VAR3, VAR24;
reg [3:0] VAR34, VAR10;
reg [1:0] V... | gpl-2.0 |
ejk43/rfnoc-neuralnet | rfnoc/fpga-src/noc_block_addsub.v | 4,610 | module MODULE1 #(
parameter VAR50 = 64'hADD0000000000000,
parameter VAR82 = 11) (
input VAR65, input VAR72,
input VAR73, input VAR98,
input [63:0] VAR53, input VAR9, input VAR41, output VAR71,
output [63:0] VAR91, output VAR1, output VAR38, input VAR6,
output [63:0] VAR81
);
localparam VAR2 = 10;
wire [63:0] VAR80, VAR... | gpl-3.0 |
olgirard/openmsp430 | core/synthesis/actel/src/omsp_watchdog.v | 7,615 | module MODULE1 (
VAR22, VAR2, VAR6, VAR19, VAR12,
VAR18, VAR3, VAR33, VAR1, VAR9, VAR27, VAR28, VAR29, VAR4, VAR31, VAR26, VAR15 );
output VAR22; output [15:0] VAR2; output VAR6; output VAR19; output VAR12;
input VAR18; input VAR3; input VAR33; input VAR1; input VAR9; input [7:0] VAR27; input [15:0] VAR28; input VAR29;... | bsd-3-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_1.behavioral.v | 1,178 | module MODULE1( VAR2, VAR5, VAR4 );
input VAR2, VAR5;
output VAR4;
VAR3 VAR6(.VAR2(VAR2),.VAR5(VAR5),.VAR4(VAR4));
VAR3 VAR1(.VAR2(VAR2),.VAR5(VAR5),.VAR4(VAR4)); | apache-2.0 |
glennchid/font5-firmware | src/verilog/synthesis/DSPCalcModule.v | 2,604 | module MODULE1(
input signed [20:0] VAR3,
input signed [16:0] VAR6,
input VAR9,
input clk,
input VAR18,
input VAR12,
output reg signed [14:0] VAR2,
input VAR4,
output reg VAR13,
output reg VAR8,
output reg VAR15
);
reg [7:0] VAR5;
reg signed [37:0] VAR1;
reg signed [14:0] VAR19;
reg signed [37:0] VAR7;
reg signed [20:0... | gpl-3.0 |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axi_dwidth_converter_v2_1/hdl/verilog/axi_dwidth_converter_v2_1_top.v | 52,187 | module MODULE1 #
(
parameter VAR68 = "VAR69",
parameter integer VAR79 = 0,
parameter integer VAR78 = 1,
parameter integer VAR70 = 0,
parameter integer VAR182 = 32,
parameter integer VAR117 = 32,
parameter integer VAR199 = 64,
parameter integer VAR17 = 1,
parameter integer VAR190 = 1,
parameter integer VAR65 = 0,
parame... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv3sd1/sky130_fd_sc_ls__clkdlyinv3sd1_1.v | 2,164 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR8,
VAR7,
VAR3 ,
VAR5
);
output VAR2 ;
input VAR4 ;
input VAR8;
input VAR7;
input VAR3 ;
input VAR5 ;
VAR6 VAR1 (
.VAR2(VAR2),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR2,
VAR4
);
output VAR2;
input VAR4;
supply1 VAR8;
supply0 VAR7;... | apache-2.0 |
CospanDesign/nysa-verilog | verilog/generic/adapter_block_fifo_2_axi_stream.v | 4,934 | module MODULE1 #(
parameter VAR18 = 24,
parameter VAR13 = VAR18 / 8,
parameter VAR2 = 0,
parameter VAR9 = 1
)(
input rst,
input VAR6,
output reg VAR10,
input [23:0] VAR15,
input [(VAR18 + 1) - 1:0] VAR14,
output VAR3,
input [3:0] VAR4,
input VAR19,
output [3:0] VAR21,
input VAR11,
output [VAR18 - 1:0] VAR12,
output VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/muxb4to1/sky130_fd_sc_hdll__muxb4to1.behavioral.v | 1,468 | module MODULE1 (
VAR4,
VAR3,
VAR11
);
output VAR4;
input [3:0] VAR3;
input [3:0] VAR11;
supply1 VAR6;
supply0 VAR7;
supply1 VAR9 ;
supply0 VAR1 ;
bufif1 VAR2 (VAR4 , !VAR3[0], VAR11[0] );
bufif1 VAR5 (VAR4 , !VAR3[1], VAR11[1] );
bufif1 VAR8 (VAR4 , !VAR3[2], VAR11[2] );
bufif1 VAR10 (VAR4 , !VAR3[3], VAR11[3] );
endmo... | apache-2.0 |
mda-ut/SubZero | fpga/fpga_hw/top_level/DE0_Nano_SOPC/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v | 7,553 | module MODULE1
parameter VAR40 = 8,
VAR37 = 8,
VAR27 = 0,
VAR5 = 0,
VAR42 = 1,
VAR2 = 0,
VAR45 = 1,
VAR28 = 2,
VAR21 = 2,
VAR34 = 1,
VAR35 = VAR40 / VAR37,
VAR18 = VAR13(VAR35)
)
(
input VAR31,
input VAR1,
input VAR7,
input VAR26,
output VAR20,
input VAR12,
input [VAR40 - 1 : 0] VAR44,
input [VAR42 - 1 : 0] VAR15,
inpu... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o22a/sky130_fd_sc_ls__o22a.functional.v | 1,511 | module MODULE1 (
VAR4 ,
VAR11,
VAR8,
VAR5,
VAR7
);
output VAR4 ;
input VAR11;
input VAR8;
input VAR5;
input VAR7;
wire VAR1 ;
wire VAR2 ;
wire VAR10;
or VAR3 (VAR1 , VAR8, VAR11 );
or VAR12 (VAR2 , VAR7, VAR5 );
and VAR6 (VAR10, VAR1, VAR2);
buf VAR9 (VAR4 , VAR10 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/xnor2/gf180mcu_fd_sc_mcu9t5v0__xnor2_2.behavioral.v | 1,429 | module MODULE1( VAR2, VAR5, VAR4 );
input VAR5, VAR2;
output VAR4;
VAR1 VAR6(.VAR2(VAR2),.VAR5(VAR5),.VAR4(VAR4));
VAR1 VAR3(.VAR2(VAR2),.VAR5(VAR5),.VAR4(VAR4)); | apache-2.0 |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/bd/system/ip/system_auto_us_0/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axi3_conv.v | 26,446 | module MODULE1 #
(
parameter VAR147 = "none",
parameter integer VAR61 = 1,
parameter integer VAR35 = 32,
parameter integer VAR73 = 32,
parameter integer VAR65 = 0,
parameter integer VAR80 = 1,
parameter integer VAR82 = 1,
parameter integer VAR13 = 1,
parameter integer VAR59 = 1,
parameter integer VAR3 = 1,
parameter in... | mit |
ammelto/FPGAdventure | Adventure/ECenterMaze.v | 3,630 | module MODULE1(VAR3, VAR2, VAR1, VAR6, VAR4);
input VAR3;
input [9:0]VAR2;
input [8:0]VAR1;
input [7:0]VAR4;
output [7:0]VAR6;
reg [7:0]VAR5;
always @(posedge VAR3) begin
if((VAR2 >= 0 && VAR2 <=63) && (
(VAR1 <= 39) ||
(VAR1 >= 120 && VAR1 <=199) ||
(VAR1 >= 280 && VAR1 <= 359) ||
(VAR1 >= 441) ) )
VAR5[7:0] <= VAR4;
... | mit |
AnAtomInTheUniverse/578_project_col_panic | final_verilog/src/clib/c_damq_ctrl.v | 17,600 | module MODULE1
(clk, reset, VAR7, VAR4, VAR12, VAR21, VAR13,
VAR3, VAR11, VAR20, VAR2, VAR18,
VAR15, VAR17, VAR5);
parameter VAR8 = 4;
parameter VAR16 = 8;
parameter VAR19 = 0;
parameter VAR6 = 0;
parameter VAR10 = 0;
parameter VAR22 = VAR1;
localparam VAR14 = VAR9(VAR16);
input clk;
input reset;
input VAR7;
input VAR4... | gpl-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/tmp/spree/tmp/reg_file_pipe.v | 3,674 | module MODULE1(clk,VAR8,
VAR54, VAR58, VAR50,
VAR22, VAR19, VAR24,
VAR48, VAR27, VAR31);
parameter VAR33=32;
parameter VAR60=32;
parameter VAR23=5;
input clk;
input VAR8;
input VAR50;
input VAR24;
input [VAR23-1:0] VAR54,VAR22,VAR48;
output [VAR33-1:0] VAR58, VAR19;
input [VAR33-1:0] VAR27;
input VAR31;
VAR7 VAR2(
.VAR... | mit |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_stepper/rtl/wb_stepper.v | 15,479 | module MODULE1 #(
parameter VAR60 = (32'd200) << 9
)(
input clk,
input rst,
input VAR81,
input VAR80,
input [3:0] VAR42,
input [31:0] VAR94,
input VAR58,
output reg VAR83,
output reg [31:0] VAR27,
input [31:0] VAR53,
output reg VAR50,
output VAR23,
output VAR52,
output VAR89,
output VAR24
);
localparam VAR92 = 32'h0000... | mit |
praveendath92/securePUF | source/system.v | 16,414 | module MODULE1 #(
parameter VAR26 = 1,
parameter VAR73 = 1,
parameter VAR58 = 17,
parameter VAR125 = 13,
parameter VAR4 = 1,
parameter VAR22 = 48'hAAAAAAAAAAAA
)(
input wire VAR98, input wire VAR80, input wire VAR139,
output wire [7:0] VAR137, output wire VAR93, output wire VAR24, output wire VAR65, input wire [7:0] VA... | gpl-2.0 |
Obijuan/open-fpga-verilog-tutorial | tutorial/ICESTICK/T18-notas/divider.v | 1,352 | module MODULE1(input wire VAR4, output wire VAR2);
parameter VAR7 = VAR6;
localparam VAR5 = VAR1(VAR7);
reg [VAR5-1:0] VAR3 = 0;
always @(posedge VAR4)
VAR3 <= (VAR3 == VAR7 - 1) ? 0 : VAR3 + 1;
assign VAR2 = VAR3[VAR5-1];
endmodule | gpl-2.0 |
AloriumTechnology/XLR8Pong | extras/rtl/xlr8_top.v | 25,838 | module MODULE1
(
input VAR113, input VAR189,
inout VAR71,
inout VAR141,
inout VAR116,VAR21,VAR70,VAR205,VAR39,VAR87, inout VAR131,VAR19,VAR67,VAR23,VAR178,VAR124,VAR106,VAR104, inout VAR130,VAR250,VAR216,VAR17,VAR249,VAR211, output VAR167,
inout [5:0] VAR256,
output VAR257, output VAR195, inout VAR182, inout VAR75, ino... | lgpl-3.0 |
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