repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
alexforencich/xfcp | lib/eth/rtl/xgmii_deinterleave.v | 2,123 | module MODULE1
(
input wire [72:0] VAR3,
output wire [63:0] VAR1,
output wire [7:0] VAR2
);
assign VAR1[7:0] = VAR3[7:0];
assign VAR2[0] = VAR3[8];
assign VAR1[15:8] = VAR3[16:9];
assign VAR2[1] = VAR3[17];
assign VAR1[23:16] = VAR3[25:18];
assign VAR2[2] = VAR3[26];
assign VAR1[31:24] = VAR3[34:27];
assign VAR2[3] = V... | mit |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/cascaded_integrator_comb/cascaded_integrator_comb_stub.v | 1,622 | module MODULE1(VAR5, VAR4, VAR1, VAR3, VAR2, VAR6)
;
input VAR5;
input [7:0]VAR4;
input VAR1;
output VAR3;
output [23:0]VAR2;
output VAR6;
endmodule | mit |
martinmiranda14/Digitales | Lab_6/driver_vga1.v | 2,306 | module MODULE1(VAR6, VAR8, VAR7,VAR13,VAR15);
input VAR6; output VAR8, VAR7;
output [9:0]VAR13;
output [9:0]VAR15;
parameter VAR5 = 10'd1360; parameter VAR2 = 10'd805;
parameter VAR14 = 10'd64; parameter VAR3 = 10'd104; parameter VAR16 = 10'd168;
parameter VAR1 = 10'd3; parameter VAR12 = 10'd4; parameter VAR11 = 10'd30... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and3b/sky130_fd_sc_hd__and3b_4.v | 2,218 | module MODULE2 (
VAR10 ,
VAR6 ,
VAR2 ,
VAR5 ,
VAR1,
VAR4,
VAR9 ,
VAR3
);
output VAR10 ;
input VAR6 ;
input VAR2 ;
input VAR5 ;
input VAR1;
input VAR4;
input VAR9 ;
input VAR3 ;
VAR8 VAR7 (
.VAR10(VAR10),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR3(VAR3)
);
endmodule
module MODULE... | apache-2.0 |
davidlee80/miaow | src/verilog/rtl/dispatcher/dispatcher.v | 23,655 | module MODULE1
(
VAR24,
VAR100, VAR90,
VAR56, VAR106,
VAR1, VAR82,
VAR99, VAR44,
VAR34, VAR23,
rst, VAR38, VAR8, VAR41, VAR79,
VAR72, VAR64, VAR91,
VAR25, VAR40, VAR4,
VAR3, VAR22, VAR111,
clk
) ;
parameter VAR51 = 8;
parameter VAR84 = 3;
parameter VAR104 = 6;
parameter VAR69 = 6;
parameter VAR78 = 40;
parameter VAR57 ... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o31ai/sky130_fd_sc_hs__o31ai.functional.pp.v | 1,928 | module MODULE1 (
VAR6,
VAR14,
VAR10 ,
VAR3 ,
VAR13 ,
VAR8 ,
VAR1
);
input VAR6;
input VAR14;
output VAR10 ;
input VAR3 ;
input VAR13 ;
input VAR8 ;
input VAR1 ;
wire VAR1 VAR2 ;
wire VAR9 ;
wire VAR11;
or VAR5 (VAR2 , VAR13, VAR3, VAR8 );
nand VAR12 (VAR9 , VAR1, VAR2 );
VAR4 VAR15 (VAR11, VAR9, VAR6, VAR14);
buf VAR7 ... | apache-2.0 |
skalldri/mips-verilog | fetch-decode/memory2.v | 3,070 | module MODULE1 (clk, addr, din, dout, VAR9, VAR2, VAR8, VAR4, enable);
parameter VAR1 = 1024;
parameter VAR5 = 32'h80020000;
input clk;
input [31:0] addr;
input [31:0] din;
input [2:0] VAR2;
input VAR8; input enable;
output reg VAR4;
output reg [31:0] dout;
output reg [31:0] VAR9;
reg [7:0] VAR13[0:VAR1];
reg [31:0] VA... | gpl-2.0 |
ShepardSiegel/ocpi | coregen/dram_v5_mig34/ddr2_idelay_ctrl_eco20100514.v | 3,857 | module MODULE1 #
(
parameter VAR10 = "VAR8"
)
(
input VAR13,
input VAR1,
output VAR3
);
wire VAR6;
wire VAR11;
VAR4 VAR5
(
.VAR2(VAR6),
.VAR12(VAR13),
.VAR7(VAR1)
);
VAR4 VAR9
(
.VAR2(VAR11),
.VAR12(VAR13),
.VAR7(VAR1)
);
assign VAR3 = VAR6 & VAR11;
endmodule | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfrtp/sky130_fd_sc_lp__sdfrtp.functional.pp.v | 2,211 | module MODULE1 (
VAR3 ,
VAR16 ,
VAR5 ,
VAR9 ,
VAR7 ,
VAR4,
VAR20 ,
VAR14 ,
VAR6 ,
VAR1
);
output VAR3 ;
input VAR16 ;
input VAR5 ;
input VAR9 ;
input VAR7 ;
input VAR4;
input VAR20 ;
input VAR14 ;
input VAR6 ;
input VAR1 ;
wire VAR10 ;
wire VAR17 ;
wire VAR12;
not VAR8 (VAR17 , VAR4 );
VAR11 VAR19 (VAR12, VAR5, VAR9, V... | apache-2.0 |
UA3MQJ/fpga-synth | modules/spi_slave.v | 1,815 | module MODULE1 #(parameter VAR3 = 8) (VAR17, VAR8, VAR14, VAR4, VAR1, VAR12);
input wire VAR17;
input wire VAR8, VAR1, VAR14;
output wire VAR4;
output wire [(VAR3-1):0] VAR12;
assign VAR4 = 0;
reg [2:0] VAR9; VAR10 VAR9 <= 3'd0;
always @(posedge VAR17) VAR9 <= {VAR9[1:0], VAR8};
wire VAR13 = (VAR9[2:1]==2'b01);
reg [2:... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffq/gf180mcu_fd_sc_mcu9t5v0__dffq_1.behavioral.pp.v | 2,179 | module MODULE1( VAR8, VAR13, VAR11, VAR2, VAR7 );
input VAR8, VAR13;
inout VAR2, VAR7;
output VAR11;
reg VAR1;
VAR10 VAR5(.VAR8(VAR8),.VAR13(VAR13),.VAR11(VAR11),.VAR2(VAR2),.VAR7(VAR7),.VAR1(VAR1));
VAR10 VAR12(.VAR8(VAR8),.VAR13(VAR13),.VAR11(VAR11),.VAR2(VAR2),.VAR7(VAR7),.VAR1(VAR1));
not VAR4(VAR9,VAR13);
buf VAR3... | apache-2.0 |
cliffordwolf/yosys | techlibs/sf2/cells_map.v | 1,745 | module \VAR6 (input VAR17, VAR30, VAR11, VAR2, output VAR24);
VAR4 VAR21 (.VAR17(VAR17), .VAR8(VAR30), .VAR20(VAR2), .VAR3(VAR11), .VAR28(1'b1), .VAR9(1'b1), .VAR27(1'b0), .VAR12(1'b0), .VAR24(VAR24));
endmodule
module \VAR15 (input VAR17, VAR30, VAR11, VAR2, output VAR24);
VAR4 VAR21 (.VAR17(VAR17), .VAR8(VAR30), .VAR... | isc |
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/dspengine_8to16.v | 5,950 | module MODULE1
parameter VAR51 = 9,
parameter VAR34 = 0)
(input clk, input reset, input VAR53,
input VAR10, input [7:0] VAR22, input [31:0] VAR24,
output VAR1,
output VAR37,
input VAR23,
output VAR46,
output VAR50,
output [VAR51-1:0] VAR52,
input [VAR51-1:0] VAR3,
output [35:0] VAR42,
input [35:0] VAR28
);
wire VAR40;
... | gpl-2.0 |
theapi/nand2tetris_fpga | hack/rtl/verilog/ascii.v | 13,531 | module MODULE1 (
input clk,
input VAR5,
input [7:0] VAR23,
output [7:0] MODULE1
);
reg [7:0] VAR19;
reg [1:0] VAR21 = 2'b00;
assign MODULE1 = VAR19;
reg VAR1 = 0;
reg VAR11 = 0;
reg [1:0] VAR9 = 2'b00;
wire VAR16;
reg [7:0] VAR8;
reg [7:0] VAR22 [2:0];
reg [1:0] VAR20 = 2'b00;
reg [1:0] VAR10 = 2'b00;
reg VAR17 = 0;
re... | mit |
rkrajnc/minimig-mist | rtl/minimig/paula_floppy_fifo.v | 2,015 | module MODULE1
(
input clk, input VAR3,
input reset, input [15:0] in, output reg [15:0] out, input rd, input wr, output reg VAR5, output VAR7, output [11:0] VAR4 );
reg [15:0] VAR1 [2047:0]; reg [11:0] VAR6; reg [11:0] VAR2; wire VAR8;
assign VAR4 = VAR6 - VAR2;
always @(posedge clk) begin
if (VAR3) begin
if (wr)
VAR1[... | gpl-3.0 |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/example_design/rtl/traffic_gen/mig_7series_v2_0_memc_flow_vcontrol.v | 15,757 | module MODULE1 #
(
parameter VAR56 = 100,
parameter VAR29 = 4,
parameter VAR1 = 32,
parameter VAR75 = 6,
parameter VAR32 = 4,
parameter VAR12 = "VAR30",
parameter VAR18 = "VAR72"
)
(
input VAR54,
input [9:0] VAR57,
input [3:0] VAR20,
input [5:0] VAR59,
input VAR13,
output reg VAR4,
input VAR66,
input [2:0] VAR60,
input... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfrtp/sky130_fd_sc_ms__dfrtp.blackbox.v | 1,337 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR8 ,
VAR5
);
output VAR3 ;
input VAR1 ;
input VAR8 ;
input VAR5;
supply1 VAR2;
supply0 VAR6;
supply1 VAR7 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy/ddr3_s4_uniphy_p0_write_datapath.v | 4,700 | module MODULE1(
VAR5,
VAR6,
VAR16,
VAR27,
VAR3,
VAR22,
VAR13,
VAR32,
VAR15,
VAR23,
VAR34,
VAR17
);
parameter VAR10 = "";
parameter VAR4 = "";
parameter VAR14 = "";
parameter VAR35 = "";
parameter VAR9 = "";
parameter VAR33 = "";
parameter VAR12 = "";
parameter VAR21 = "";
parameter VAR36 = "";
parameter VAR28 = "";
par... | lgpl-3.0 |
alexforencich/xfcp | lib/eth/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v | 25,903 | module MODULE1 (
input wire VAR195,
input wire VAR269,
output wire [1:0] VAR345,
output wire VAR405,
output wire [1:0] VAR93,
input wire [1:0] VAR188,
output wire VAR209,
output wire VAR390,
input wire VAR51,
input wire VAR131,
output wire VAR105,
output wire VAR387,
input wire VAR252,
input wire VAR94,
output wire VAR... | mit |
bluespec/Flute | builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkNear_Mem_IO_AXI4.v | 107,524 | module MODULE1(VAR163,
VAR21,
VAR251,
VAR43,
VAR97,
VAR205,
VAR201,
VAR27,
VAR8,
VAR143,
VAR261,
VAR255,
VAR50,
VAR40,
VAR109,
VAR175,
VAR120,
VAR313,
VAR190,
VAR282,
VAR208,
VAR276,
VAR214,
VAR310,
VAR210,
VAR226,
VAR58,
VAR89,
VAR112,
VAR213,
VAR215,
VAR64,
VAR245,
VAR123,
VAR52,
VAR164,
VAR150,
VAR273,
VAR189,
VAR26... | apache-2.0 |
yipenghuang0302/csee4840_14 | software/peripheral/synthesis/submodules/hps_sdram_p0_acv_ldc.v | 3,413 | module MODULE1
(
VAR41,
VAR13,
VAR34,
VAR1,
VAR10,
VAR14,
VAR9,
VAR33,
VAR39
);
parameter VAR26 = "";
parameter VAR20 = 0;
parameter VAR21 = "false";
parameter VAR2 = "false";
input VAR41;
input VAR13;
input VAR34;
input [VAR26-1:0] VAR1;
output VAR10;
output VAR14;
output VAR9;
output VAR33;
output VAR39;
wire VAR37;
... | mit |
monotone-RK/FACE | IEICE-Trans/16-way/src/ip_dram/ui/mig_7series_v2_3_ui_top.v | 14,966 | module MODULE1 #
(
parameter VAR54 = 100,
parameter VAR42 = 256,
parameter VAR64 = 32,
parameter VAR60 = 3,
parameter VAR2 = 12,
parameter VAR78 = 5,
parameter VAR24 = 5,
parameter VAR40 = "VAR12",
parameter VAR43 = "VAR12",
parameter VAR56 = "VAR77",
parameter VAR6 = 2,
parameter VAR19 = 4,
parameter VAR75 = "VAR14", ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o2bb2a/sky130_fd_sc_hdll__o2bb2a_4.v | 2,414 | module MODULE1 (
VAR7 ,
VAR10,
VAR1,
VAR5 ,
VAR4 ,
VAR8,
VAR3,
VAR6 ,
VAR2
);
output VAR7 ;
input VAR10;
input VAR1;
input VAR5 ;
input VAR4 ;
input VAR8;
input VAR3;
input VAR6 ;
input VAR2 ;
VAR11 VAR9 (
.VAR7(VAR7),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR2(VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o22a/sky130_fd_sc_lp__o22a_lp.v | 2,347 | module MODULE1 (
VAR9 ,
VAR2 ,
VAR10 ,
VAR11 ,
VAR4 ,
VAR5,
VAR7,
VAR8 ,
VAR3
);
output VAR9 ;
input VAR2 ;
input VAR10 ;
input VAR11 ;
input VAR4 ;
input VAR5;
input VAR7;
input VAR8 ;
input VAR3 ;
VAR1 VAR6 (
.VAR9(VAR9),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR8(VAR8),
.... | apache-2.0 |
efabless/openlane | designs/digital_pll_sky130_fd_sc_hd/src/digital_pll.v | 3,234 | module MODULE1 (reset, VAR16, VAR30, VAR25, VAR32, VAR1, VAR23, sel, VAR8, VAR11);
input reset; input VAR16; input VAR30; input [4:0] VAR23; input [2:0] sel; input VAR8; input [25:0] VAR11;
output VAR25; output [1:0] VAR32; output [3:0] VAR1;
wire [25:0] VAR21; wire [25:0] VAR24; wire [3:0] VAR15; wire VAR33; wire VAR2... | apache-2.0 |
borti4938/n64rgb | generalRGBmod/firmware/rtl/n64_vinfo_ext.v | 3,388 | module MODULE1(
VAR10,
VAR8,
VAR4,
VAR13,
VAR12
);
input VAR10;
input VAR8;
input [3:0] VAR4;
input [3:0] VAR13;
output [3:0] VAR12;
wire VAR14 = !VAR4[3] & VAR13[3];
wire VAR1 = VAR4[3] & !VAR13[3];
wire VAR11 = !VAR4[1] & VAR13[1];
wire VAR6 = VAR4[1] & !VAR13[1];
reg [1:0] VAR2 = 2'b00;
always @(posedge VAR10) begin... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor3/sky130_fd_sc_hs__nor3_1.v | 2,071 | module MODULE2 (
VAR3 ,
VAR8 ,
VAR4 ,
VAR2 ,
VAR1,
VAR6
);
output VAR3 ;
input VAR8 ;
input VAR4 ;
input VAR2 ;
input VAR1;
input VAR6;
VAR5 VAR7 (
.VAR3(VAR3),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR3,
VAR8,
VAR4,
VAR2
);
output VAR3;
input VAR8;
input VAR4;
in... | apache-2.0 |
ridecore/ridecore | src/fpga/uart.v | 9,487 | module MODULE5(VAR27, VAR35, VAR26, VAR45, VAR17, VAR40);
input wire VAR27, VAR35, VAR45;
input wire [7:0] VAR26;
output reg VAR17, VAR40;
reg [8:0] VAR1;
reg [11:0] VAR38;
reg [3:0] VAR9;
always @(posedge VAR27 or negedge VAR35) begin
if(~VAR35) begin
VAR17 <= 1'b1;
VAR40 <= 1'b1;
VAR1 <= 9'h1ff;
VAR38 <= 0;
VAR9 <= 0... | bsd-3-clause |
ShepardSiegel/ocpi | coregen/dram_v6_mig39_2/mig_39_2/user_design/rtl/controller/arb_row_col.v | 12,632 | module MODULE1 #
(
parameter VAR32 = 100,
parameter VAR26 = "1T",
parameter VAR62 = "VAR31",
parameter VAR71 = 4,
parameter VAR33 = 2,
parameter VAR75 = 2
)
(
VAR35, VAR69, VAR12, VAR48,
VAR10, VAR67, VAR55,
VAR20, VAR64, VAR21, VAR68, VAR4,
VAR53, VAR6, VAR63, VAR47,
clk, rst, VAR70, VAR74, VAR24, VAR77,
VAR9, VAR15
)... | lgpl-3.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/01BLUETOOTH/Version_02/02 verilog/RX/recepcion.v | 1,191 | module MODULE1(input VAR4,
output reg VAR6,
input VAR2,
input reset,
output reg [7:0] dout,
output VAR3);
VAR5 VAR1(.VAR2(VAR2), .VAR3(VAR3), .reset(reset)); | gpl-3.0 |
hitomi2500/wasca | fpga_firmware/wasca/synthesis/submodules/wasca_nios2_gen2_0_cpu_debug_slave_tck.v | 8,164 | module MODULE1 (
VAR26,
VAR35,
VAR34,
VAR24,
VAR39,
VAR4,
VAR30,
VAR9,
VAR38,
VAR23,
VAR29,
VAR3,
VAR28,
VAR8,
VAR27,
VAR32,
VAR7,
VAR25,
VAR22,
VAR18,
VAR36,
VAR11,
VAR2,
VAR5,
VAR37,
VAR16,
VAR17,
VAR19,
VAR33,
VAR14,
VAR20
)
;
output [ 1: 0] VAR17;
output VAR19;
output [ 37: 0] VAR33;
output VAR14;
output VAR20;
inp... | gpl-2.0 |
hly11/CollisionDetectionFPGA | hardware/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_3/synth/design_1_auto_pc_3.v | 15,723 | module MODULE1 (
VAR4,
VAR102,
VAR55,
VAR51,
VAR23,
VAR93,
VAR97,
VAR35,
VAR43,
VAR74,
VAR3,
VAR72,
VAR49,
VAR73,
VAR84,
VAR105,
VAR12,
VAR76,
VAR58,
VAR109,
VAR7,
VAR101,
VAR34,
VAR13,
VAR68,
VAR62,
VAR88,
VAR48,
VAR31,
VAR98,
VAR107,
VAR40,
VAR11,
VAR85,
VAR99,
VAR50,
VAR17,
VAR80,
VAR33,
VAR28,
VAR65,
VAR96,
VAR81,
... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/edk/pcores/ccx2mb_v1_00_a/hdl/verilog/pcx2mb_sm.v | 8,851 | module MODULE1 (
VAR26,
VAR40,
VAR45,
VAR24,
VAR34,
VAR35,
VAR22,
VAR9,
VAR1,
VAR19,
VAR39,
VAR31,
VAR3,
VAR25,
VAR42
);
parameter VAR27 = 5;
parameter VAR27 = 2;
parameter VAR11 = (((VAR8+VAR27)/VAR17)+1);
parameter VAR5 = (VAR17 * VAR11) -
(VAR8+VAR27+1);
parameter [2:0] VAR12 = VAR11 - 1;
parameter VAR13 = 0,
VAR36 ... | gpl-2.0 |
JakeMercer/mac | MAC/rtl/tx_sm.v | 7,722 | module MODULE1 #(
parameter VAR2 = 4'h0,
parameter VAR17 = 4'h1,
parameter VAR45 = 4'h2,
parameter VAR21 = 4'h3,
parameter VAR39 = 4'h4,
parameter VAR9 = 4'h5,
parameter VAR22 = 4'h6,
parameter VAR13 = 4'h7,
parameter VAR35 = 4'h8,
parameter VAR18 = 4'h9,
parameter VAR11 = 4'hA,
parameter VAR24 = 4'hB
)(
input wire res... | mit |
OpticalMeasurementsSystems/2DImageProcessing | src/axi_slave_impl.v | 14,276 | module MODULE1 #
(
parameter integer VAR8 = 16,
parameter integer VAR3 = 32,
parameter integer VAR29 = 10
)
(
input wire [1:0] VAR10, input wire [7 : 0] VAR17,
input wire [VAR3 -1 : 0] VAR13,
output reg [VAR3 -1 : 0] VAR41,
input wire VAR22,
input wire VAR15,
input wire [VAR29-1 : 0] VAR38,
input wire [2 : 0] VAR40,
in... | gpl-2.0 |
deepakcu/digital_design | flops/flop_async_rst.v | 1,712 | module MODULE1(
input clk,
input VAR2,
input din,
output reg VAR1
);
always@(posedge clk or posedge VAR2)
if(rst)
VAR1 <= 0;
else
VAR1 <= din;
endmodule | apache-2.0 |
SeanZarzycki/openSPARC-FPU | project/src/fpu_in_dp.v | 8,977 | module MODULE1 (
VAR31,
VAR3,
VAR29,
VAR33,
VAR51,
VAR23,
VAR24,
VAR59,
VAR13,
VAR18,
VAR46,
VAR37,
VAR61,
VAR21,
VAR32,
VAR19,
VAR25,
VAR8,
VAR45,
VAR27,
VAR44,
VAR2,
VAR43,
VAR22,
VAR6,
VAR17,
VAR5,
VAR38,
VAR7,
VAR57,
VAR36,
VAR35,
VAR41,
VAR56,
VAR34,
VAR1
);
input VAR31;
input [116:112] VAR3; input [79:72] VAR29; ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp.pp.symbol.v | 1,367 | module MODULE1 (
input VAR3 ,
output VAR2 ,
input VAR9 ,
input VAR7 ,
input VAR8,
input VAR5 ,
input VAR6,
input VAR4,
input VAR1
);
endmodule | apache-2.0 |
xuefei1/ElectronicEngineControl | db/ip/niosII_system/submodules/altera_up_rs232_in_deserializer.v | 8,150 | module MODULE1 (
clk,
reset,
VAR10,
VAR15,
VAR9,
VAR32,
VAR11
);
parameter VAR13 = 9; parameter VAR24 = 433;
parameter VAR5 = 216;
parameter VAR3 = 11; parameter VAR23 = 9;
input clk;
input reset;
input VAR10;
input VAR15;
output reg [ 7: 0] VAR9;
output VAR32;
output [VAR23: 0] VAR11;
wire VAR19;
wire VAR4;
wire VAR25... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o21a/sky130_fd_sc_ls__o21a.blackbox.v | 1,326 | module MODULE1 (
VAR1 ,
VAR4,
VAR7,
VAR8
);
output VAR1 ;
input VAR4;
input VAR7;
input VAR8;
supply1 VAR3;
supply0 VAR2;
supply1 VAR6 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/fa/sky130_fd_sc_hd__fa.blackbox.v | 1,293 | module MODULE1 (
VAR2,
VAR9 ,
VAR8 ,
VAR1 ,
VAR6
);
output VAR2;
output VAR9 ;
input VAR8 ;
input VAR1 ;
input VAR6 ;
supply1 VAR7;
supply0 VAR5;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_115.v | 1,531 | module MODULE2 (
VAR7,
VAR13
);
input [31:0] VAR7;
output [31:0]
VAR13;
wire [31:0]
VAR9,
VAR4,
VAR1,
VAR2,
VAR8,
VAR5,
VAR14,
VAR11,
VAR6;
assign VAR9 = VAR7;
assign VAR11 = VAR14 << 3;
assign VAR6 = VAR14 + VAR11;
assign VAR14 = VAR8 - VAR5;
assign VAR2 = VAR9 << 4;
assign VAR8 = VAR1 - VAR2;
assign VAR4 = VAR9 << 11... | mit |
csturton/wirepatch | system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v | 15,336 | module MODULE1(
VAR57,
VAR9,
VAR2,
VAR72,
VAR14,
VAR82,
VAR101,
VAR39,
VAR6
,
VAR68,
VAR17,
VAR64,
VAR44,
VAR34,
VAR37,
VAR59,
VAR56,
VAR77,
VAR78,
VAR13,
VAR67,
VAR74,
VAR69
,
VAR38,
VAR48,
VAR20,
VAR40,
VAR12,
VAR54,
VAR86,
VAR47,
VAR22,
VAR25
,
VAR51,
VAR95,
VAR52,
VAR93,
VAR76,
VAR73,
VAR21,
VAR4,
VAR16,
VAR87
,
VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/conb/sky130_fd_sc_hvl__conb.functional.pp.v | 1,900 | module MODULE1 (
VAR14 ,
VAR7 ,
VAR3,
VAR11,
VAR4 ,
VAR6
);
output VAR14 ;
output VAR7 ;
input VAR3;
input VAR11;
input VAR4 ;
input VAR6 ;
wire VAR12 ;
wire VAR8;
pullup VAR9 (VAR12 );
VAR1 VAR5 (VAR14 , VAR12, VAR3 );
pulldown VAR2 (VAR8);
VAR13 VAR10 (VAR7 , VAR8, VAR11);
endmodule | apache-2.0 |
KorotkiyEugene/LAG_sv_syn_quartus | LAG_route.v | 3,371 | function automatic bit VAR7;
input integer VAR11;
input integer VAR33;
bit valid;
begin
valid=1'b1;
if (VAR11==VAR20) begin
if (VAR33>=VAR8) valid=1'b0;
end
VAR7=valid;
end
endfunction
function automatic bit VAR24;
input VAR13 VAR22;
input VAR13 VAR28;
bit valid;
begin
valid=1'b1;
if (VAR22==VAR28) valid=1'b0;
if (((VA... | gpl-2.0 |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/submodules/niosII_system_nios2_qsys_0_jtag_debug_module_sysclk.v | 7,153 | module MODULE1 (
clk,
VAR33,
VAR27,
VAR12,
VAR7,
VAR14,
VAR25,
VAR13,
VAR10,
VAR2,
VAR5,
VAR23,
VAR21,
VAR22,
VAR18,
VAR26,
VAR29,
VAR30,
VAR31
)
;
output [ 37: 0] VAR14;
output VAR25;
output VAR13;
output VAR10;
output VAR2;
output VAR5;
output VAR23;
output VAR21;
output VAR22;
output VAR18;
output VAR26;
output VAR2... | apache-2.0 |
Digilent/vivado-library | ip/hls_contrast_stretch_1_0/hdl/verilog/hls_contrast_strehbi.v | 1,308 | module MODULE2(
input [8 - 1:0] VAR5,
input [22 - 1:0] VAR7,
input [30 - 1:0] VAR12,
output [32 - 1:0] dout);
wire signed [25 - 1:0] VAR3;
wire signed [18 - 1:0] VAR13;
wire signed [48 - 1:0] VAR9;
wire signed [43 - 1:0] VAR2;
wire signed [48 - 1:0] VAR14;
assign VAR3 = (VAR7);
assign VAR13 = (VAR5);
assign VAR9 = (VAR... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_1.behavioral.pp.v | 2,214 | module MODULE1( VAR2, VAR8, VAR6, VAR9, VAR4 );
input VAR2, VAR8;
inout VAR9, VAR4;
output VAR6;
reg VAR3;
VAR12 VAR13(.VAR2(VAR2),.VAR8(VAR8),.VAR6(VAR6),.VAR9(VAR9),.VAR4(VAR4),.VAR3(VAR3));
VAR12 VAR5(.VAR2(VAR2),.VAR8(VAR8),.VAR6(VAR6),.VAR9(VAR9),.VAR4(VAR4),.VAR3(VAR3));
not VAR1(VAR7,VAR8);
buf VAR10(VAR11,VAR8)... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a211o/sky130_fd_sc_hs__a211o.pp.symbol.v | 1,339 | module MODULE1 (
input VAR1 ,
input VAR2 ,
input VAR6 ,
input VAR5 ,
output VAR4 ,
input VAR3,
input VAR7
);
endmodule | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/FPU_Interface/cordic_Arch3/DECO_CORDIC_OP.v | 2,262 | module MODULE1 #(parameter VAR4 = 32)(
input wire [VAR4-1:0] VAR2,
input wire VAR5,
input wire [1:0] VAR3,
output reg VAR1,
output reg [VAR4-1:0] VAR6
);
always @(*) begin
if(VAR5 == 1'b0)
begin case (VAR3)
2'b00 : begin
VAR1 = 1'b0;
VAR6 = VAR2;
end
2'b01 : begin
VAR1 = 1'b1;
VAR6 = {~VAR2[VAR4-1],VAR2[VAR4-2:0]};
end... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfxtp/sky130_fd_sc_hs__dfxtp.functional.v | 1,529 | module MODULE1 (
VAR7,
VAR5,
VAR1 ,
VAR9 ,
VAR4
);
input VAR7;
input VAR5;
output VAR1 ;
input VAR9 ;
input VAR4 ;
wire VAR10;
VAR6 VAR2 VAR8 (VAR10 , VAR4, VAR9, VAR7, VAR5);
buf VAR3 (VAR1 , VAR10 );
endmodule | apache-2.0 |
tinkercnc/spi-fpga-driver | pluto_mix_firmware/spi_mix_main.v | 8,629 | module MODULE1(clk, VAR49, VAR4, VAR6, VAR73, VAR65, VAR19, VAR66, VAR51, dout, din, VAR61, VAR14, VAR44, VAR40, VAR60, VAR10, VAR36);
parameter VAR7=10;
parameter VAR25=11;
parameter VAR27=4;
parameter VAR45=14;
input clk;
input VAR49, VAR73, VAR4, VAR65;
output VAR6, VAR51 = 1'VAR32, VAR19;
output VAR66;
input [12:0]... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o2111a/sky130_fd_sc_ms__o2111a.functional.v | 1,492 | module MODULE1 (
VAR11 ,
VAR10,
VAR5,
VAR4,
VAR3,
VAR2
);
output VAR11 ;
input VAR10;
input VAR5;
input VAR4;
input VAR3;
input VAR2;
wire VAR1 ;
wire VAR8;
or VAR9 (VAR1 , VAR5, VAR10 );
and VAR7 (VAR8, VAR4, VAR3, VAR1, VAR2);
buf VAR6 (VAR11 , VAR8 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_3.behavioral.pp.v | 1,159 | module MODULE1( VAR4, VAR7, VAR1, VAR3 );
input VAR4;
inout VAR1, VAR3;
output VAR7;
VAR2 VAR5(.VAR4(VAR4),.VAR7(VAR7),.VAR1(VAR1),.VAR3(VAR3));
VAR2 VAR6(.VAR4(VAR4),.VAR7(VAR7),.VAR1(VAR1),.VAR3(VAR3)); | apache-2.0 |
hcabrera-/atto | rtl/crossbar.v | 1,384 | module MODULE1
(
input wire [47:0] VAR8,
input wire [47:0] VAR11,
input wire [47:0] VAR16,
input wire [1:0] VAR15,
input wire [1:0] VAR5,
input wire VAR7,
output wire [47:0] VAR19,
output wire [47:0] VAR1,
output wire [39:0] VAR12
);
wire [47:0] VAR10;
VAR20 VAR9(
.sel (VAR15[0]),
.VAR4 (VAR8),
.VAR14 (VAR11),
.VAR13 (... | gpl-3.0 |
lokisz/openzcore | pippo-0.9/rtl/verilog/lsu_reg2mem.v | 2,631 | module MODULE1(addr, VAR11, VAR7, VAR10);
parameter VAR5 = VAR4;
input [1:0] addr;
input [VAR8-1:0] VAR11;
input [VAR5-1:0] VAR7;
output [VAR5-1:0] VAR10;
reg [7:0] VAR12; reg [7:0] VAR9; reg [7:0] VAR3; reg [7:0] VAR13;
assign VAR10 = {VAR12, VAR9, VAR3, VAR13};
always @(VAR11 or addr or VAR7) begin
casex({VAR11, addr... | gpl-2.0 |
FPGA1988/udp_ip_stack | Network/udp_ip_core/trunk/ic/digital/rtl/eth_tri_mode/MAC_tx/CRC_gen.v | 7,274 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR4 ,
VAR13 ,
VAR7 ,
VAR11 ,
VAR14 ,
VAR6
);
input VAR3 ;
input VAR1 ;
input VAR4 ;
input [7:0] VAR13 ;
input VAR7 ;
input VAR11 ;
output [7:0] VAR6 ;
output VAR14 ;
reg [7:0] VAR6 ;
reg [31:0] VAR2;
reg VAR14;
reg [3:0] VAR9;
function[31:0] VAR5;
input[7:0] VAR12;
input[31:0] VAR8;
reg[... | apache-2.0 |
laanwj/yosys-ice-experiments | error/fail.v | 6,853 | module MODULE1(input clk,
output VAR32, input VAR34,
input VAR38
);
localparam VAR52 = 12;
wire VAR27, VAR19;
wire [7:0] VAR11;
wire [7:0] VAR61;
wire VAR42;
wire VAR21;
reg VAR72 = 1'b0;
VAR44 VAR24 (
.clk(clk),
.VAR38(VAR72),
.VAR70(VAR34),
.VAR63(VAR32),
.rd(VAR21),
.wr(VAR42),
.valid(VAR27),
.VAR71(VAR19),
.VAR23(V... | mit |
Fabeltranm/FPGA-Game-D1 | HW/RTL/01BLUETOOTH/Version_01/02 verilog/Recepción/recibo.v | 1,854 | module MODULE1 ( input clk,
input VAR10,
input reset,
input VAR5,
output VAR14,
output VAR6,
output reg[7:0]dout
);
wire VAR13;
VAR8 VAR3(.clk(clk), .VAR13(VAR13), .reset(reset));
reg[1:0]VAR11, VAR1;
parameter VAR2 =2'b00;
parameter VAR12 =2'b01;
reg VAR9;
reg VAR4 = 0;
reg[8:0]VAR15=9'b000000000;
reg[3:0]VAR7=4'b0000... | gpl-3.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_axi_bridge_0/ghrd_10as066n2_axi_bridge_0_bb.v | 6,634 | module MODULE1 #(
parameter VAR130 = 1,
parameter VAR51 = 1,
parameter VAR67 = 1,
parameter VAR47 = 1,
parameter VAR37 = 1,
parameter VAR46 = 1,
parameter VAR66 = 1,
parameter VAR99 = 1,
parameter VAR4 = 1,
parameter VAR135 = 1,
parameter VAR17 = 1,
parameter VAR81 = 1,
parameter VAR93 = 1,
parameter VAR131 = 1,
parame... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21bai/sky130_fd_sc_hs__o21bai.behavioral.v | 2,056 | module MODULE1 (
VAR15 ,
VAR16 ,
VAR2 ,
VAR12,
VAR3,
VAR5
);
output VAR15 ;
input VAR16 ;
input VAR2 ;
input VAR12;
input VAR3;
input VAR5;
wire VAR4 ;
wire VAR11 ;
wire VAR1 ;
wire VAR10;
not VAR8 (VAR4 , VAR12 );
or VAR9 (VAR11 , VAR2, VAR16 );
nand VAR7 (VAR1 , VAR4, VAR11 );
VAR6 VAR13 (VAR10, VAR1, VAR3, VAR5);
bu... | apache-2.0 |
KorotkiyEugene/Netmaker_vc_router_syn_quartus | NW_tree_arbiter.v | 3,536 | module MODULE1 (request, VAR15, VAR1, VAR13, clk, VAR22);
parameter VAR3=0;
parameter VAR5=20;
parameter VAR21=4;
parameter VAR8=VAR5/VAR21;
parameter VAR6 = 0;
input [VAR5-1:0] request;
input VAR4 VAR15 [VAR8-1:0][VAR21-1:0];
output [VAR5-1:0] VAR1;
input VAR13;
input clk, VAR22;
logic [VAR5-1:0] VAR12;
logic [VAR8-1:... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/mux2/sky130_fd_sc_hs__mux2_4.v | 2,060 | module MODULE1 (
VAR6 ,
VAR1 ,
VAR7 ,
VAR2 ,
VAR3,
VAR5
);
output VAR6 ;
input VAR1 ;
input VAR7 ;
input VAR2 ;
input VAR3;
input VAR5;
VAR8 VAR4 (
.VAR6(VAR6),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR6 ,
VAR1,
VAR7,
VAR2
);
output VAR6 ;
input VAR1;
input VAR7;
... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/FPU_Interface/cordic_Arch3/CORDIC_Arch3.v | 20,441 | module MODULE1 #(parameter VAR81 = 32, parameter VAR24 = 8, parameter VAR40 = 23, parameter VAR103=26, parameter VAR39 = 5)/*#(parameter VAR81 = 64, parameter VAR24 = 11, parameter VAR40 = 52, parameter VAR103 = 55, parameter VAR39 = 6) (
input wire clk, input wire rst, input wire VAR76, input wire VAR43, input wire VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfxtp/sky130_fd_sc_ms__dfxtp.symbol.v | 1,314 | module MODULE1 (
input VAR7 ,
output VAR2 ,
input VAR5
);
supply1 VAR1;
supply0 VAR4;
supply1 VAR6 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
rkrajnc/minimig-mist | rtl/minimig/denise_playfields.v | 3,103 | module MODULE1
(
input VAR6,
input [8:1] VAR10, input VAR4, input [2:0] VAR8, input [6:0] VAR1, output reg [2:1] VAR2, output reg [7:0] VAR9 );
wire VAR3; wire [2:0] VAR7; reg [7:0] VAR5;
assign VAR3 = VAR1[6];
assign VAR7 = VAR1[5:3];
always @
begin
if (VAR4) begin
if (VAR10[7] || VAR10[5] || VAR10[3] || VAR10[1]) VAR... | gpl-3.0 |
asicguy/gplgpu | hdl/altera_fifos/sfifo_112x256_la_bb.v | 6,049 | module MODULE1 (
VAR7,
VAR10,
VAR6,
VAR2,
VAR9,
VAR4,
VAR5,
VAR8,
VAR1,
VAR3);
input VAR7;
input VAR10;
input [111:0] VAR6;
input VAR2;
input VAR9;
output VAR4;
output VAR5;
output VAR8;
output [111:0] VAR1;
output [7:0] VAR3;
endmodule | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_jbus_common/rtl/bw_io_dtl_pad_adp.v | 18,446 | module MODULE1(VAR51 ,VAR50 ,VAR71 ,
VAR12 ,VAR66 ,VAR6 ,VAR27 ,VAR35 ,VAR41 ,clk ,VAR90 ,
VAR63 ,VAR26 ,VAR79 ,VAR80 ,
VAR74 ,VAR45 ,VAR49 ,VAR11 ,
VAR7 ,VAR48 ,VAR72 ,VAR34 ,VAR42 ,
VAR38 ,ref ,VAR86 ,VAR81 ,VAR33 ,VAR77 ,VAR9 ,VAR67 ,VAR23 ,
VAR88 ,VAR5 ,VAR40 ,VAR9 );
output [7:0] VAR50 ;
output [7:0] VAR67 ;
outpu... | gpl-2.0 |
P3Stor/P3Stor | pcie/app/BMD.v | 18,024 | module MODULE1 #
(
parameter VAR35 = 128,
parameter VAR104 = 4'b0010,
parameter VAR29 = 8'h14
)
(
VAR16,
VAR4,
VAR112,
en,
VAR126,
VAR8,
VAR117,
VAR96,
VAR30,
VAR44,
VAR86,
VAR53,
VAR108,
VAR3,
VAR32,
VAR18,
VAR102,
VAR37,
VAR67,
VAR114,
VAR9,
VAR124,
VAR113,
VAR40,
VAR25,
VAR98,
VAR95,
VAR91,
VAR88,
VAR45,
VAR58,
VAR7... | gpl-2.0 |
kyzhai/NUNY | src/hardware/zero_new2_bb.v | 5,018 | module MODULE1 (
address,
VAR1,
VAR2);
input [9:0] address;
input VAR1;
output [11:0] VAR2;
tri1 VAR1;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xnor2/sky130_fd_sc_lp__xnor2_lp.v | 2,140 | module MODULE1 (
VAR2 ,
VAR3 ,
VAR4 ,
VAR9,
VAR5,
VAR7 ,
VAR1
);
output VAR2 ;
input VAR3 ;
input VAR4 ;
input VAR9;
input VAR5;
input VAR7 ;
input VAR1 ;
VAR8 VAR6 (
.VAR2(VAR2),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR2,
VAR3,
VAR4
);
output VAR2;
... | apache-2.0 |
rbarzic/async_logic | async_lib/single_rail_2ph/arbitrer_r1_2ph/arbitrer_r1_2ph_original.v | 1,301 | module MODULE1(
VAR1, VAR28, VAR23, VAR16,
VAR25, VAR29, VAR13, VAR14, VAR15
);
input VAR25;
output VAR1;
input VAR29;
output VAR28;
output VAR23;
input VAR13;
output VAR16;
input VAR14;
input VAR15;
wire VAR7, VAR17;
wire VAR4, VAR20;
VAR27 VAR11 (.VAR8(VAR25),.VAR22(VAR13),.VAR2(VAR7));
VAR27 VAR26 (.VAR8(VAR29),.VAR... | gpl-2.0 |
FAST-Switch/fast | lib/hardware/pipeline/IPE_IF_OPENFLOW/sgmii_core.v | 17,604 | module MODULE1 (
VAR46,
VAR16,
VAR20,
VAR12,
VAR32,
VAR7,
VAR48,
VAR2,
VAR54,
VAR41,
VAR23,
VAR1,
VAR30,
VAR44,
VAR50,
VAR53,
VAR26,
VAR21,
VAR39,
VAR10,
VAR42,
VAR5,
VAR38,
VAR9,
VAR34,
VAR51,
VAR22,
VAR27,
VAR37,
VAR40,
VAR28,
VAR24,
VAR33,
VAR4,
VAR52,
VAR8,
address,
read,
VAR36,
write,
clk,
reset,
VAR43,
VAR13,
VAR... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/fpu/rtl/fpu_in2_gt_in1_frac.v | 11,758 | module MODULE1 (
VAR42,
VAR24,
VAR83,
VAR59,
VAR76,
VAR43,
VAR17,
VAR84
);
input [54:0] VAR42; input [54:0] VAR24; input VAR83; input VAR59; input VAR76;
output VAR43; output VAR17; output VAR84;
wire VAR11;
wire VAR30;
wire VAR26;
wire VAR54;
wire VAR53;
wire VAR48;
wire VAR10;
wire VAR13;
wire VAR23;
wire VAR75;
wire... | gpl-2.0 |
FAST-Switch/fast | projects/SDTS/example/hw-src/ddr2/alt_ddrx_timing_param.v | 68,993 | module MODULE1 #
( parameter
VAR177 = 0,
VAR217 = 0,
VAR66 = 0,
VAR157 = "VAR191",
VAR22 = 2, VAR121 = 8,
VAR125 = 4, VAR212 = 3, VAR124 = 4, VAR165 = 4, VAR220 = 6, VAR175 = 8, VAR45 = 13, VAR141 = 4, VAR201 = 4, VAR154 = 4, VAR30 = 4, VAR1 = 4, VAR90 = 5, VAR61 = 6, VAR123 = 16,
VAR187 = 4,
VAR41 = 10,
VAR117 = 4,
VA... | apache-2.0 |
HackLinux/CPU-Design | cpu/ICACHE.v | 2,264 | module MODULE1(VAR16, address, VAR4, read, VAR9, VAR2, VAR3, VAR17, VAR6, VAR14);
input VAR16;
input [31:0] address;
input [127:0] VAR2;
input [63:0] VAR17;
output [127:0] VAR4;
output [31:0] VAR9;
input read;
output VAR3;
output [63:0] VAR6;
output VAR14;
reg [127:0] MODULE1 [12'hFFF:0];
reg [31:0] VAR10 [12'hFFF:0];
... | bsd-2-clause |
jameshegarty/rigel | platform/axi/clk25_2_X.v | 7,021 | module MODULE1
( input VAR37,
output VAR38,
input VAR56
);
assign VAR76 = VAR37;
wire [15:0] VAR72;
wire VAR12;
wire VAR50;
wire VAR60;
wire VAR61;
wire VAR30;
wire VAR69;
wire VAR52;
wire VAR55;
wire VAR74;
wire VAR5;
wire VAR44;
wire VAR14;
wire VAR57;
wire VAR45;
wire VAR36;
wire VAR2;
wire VAR29;
localparam real VA... | mit |
lab11/M-ulator | platforms/HT_m3/hardware/ICE/hdl/header_decoder.v | 1,855 | module MODULE1(
input clk,
input rst,
input [7:0] VAR17,
input VAR14,
input VAR4,
output reg [7:0] VAR7,
output reg VAR5,
output reg VAR1,
output reg VAR11,
output reg VAR15,
input VAR13
);
parameter VAR8 = 0;
parameter VAR9 = 1;
parameter VAR12 = 2;
parameter VAR6 = 3;
reg [3:0] state, VAR3;
reg VAR10, VAR16, VAR2;
al... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o311ai/sky130_fd_sc_hd__o311ai.behavioral.pp.v | 2,065 | module MODULE1 (
VAR14 ,
VAR18 ,
VAR3 ,
VAR17 ,
VAR6 ,
VAR5 ,
VAR10,
VAR11,
VAR16 ,
VAR12
);
output VAR14 ;
input VAR18 ;
input VAR3 ;
input VAR17 ;
input VAR6 ;
input VAR5 ;
input VAR10;
input VAR11;
input VAR16 ;
input VAR12 ;
wire VAR13 ;
wire VAR1 ;
wire VAR8;
or VAR9 (VAR13 , VAR3, VAR18, VAR17 );
nand VAR7 (VAR1 ... | apache-2.0 |
DougFirErickson/parallella-hw | fpga/src/common/hdl/synchronizer.v | 1,584 | module MODULE1 (
out,
in, clk, reset
);
parameter VAR1 = 32;
input [VAR1-1:0] in;
input clk;
input reset;
output [VAR1-1:0] out;
reg [VAR1-1:0] VAR2;
reg [VAR1-1:0] out;
always @ (posedge clk or posedge reset)
if(reset)
begin
VAR2[VAR1-1:0] <= {(VAR1){1'b0}};
out[VAR1-1:0] <= {(VAR1){1'b0}};
end
else
begin
VAR2[VAR1-1:... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fill/sky130_fd_sc_ms__fill.functional.v | 1,110 | module MODULE1 ();
supply1 VAR2;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/16-way/src/riffa/tx_port_buffer_128.v | 7,918 | module MODULE1 #(
parameter VAR29 = 9'd128,
parameter VAR48 = 512,
parameter VAR25 = VAR44((2**VAR44(VAR48))+1),
parameter VAR23 = 2,
parameter VAR41 = 2,
parameter VAR18 = 3,
parameter VAR40 = 3,
parameter VAR32 = 1
)
(
input VAR20,
input VAR12,
input VAR16, input [1:0] VAR9, input VAR47,
input [VAR29-1:0] VAR15, inpu... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/invkapwr/sky130_fd_sc_lp__invkapwr.pp.symbol.v | 1,311 | module MODULE1 (
input VAR7 ,
output VAR2 ,
input VAR6,
input VAR3 ,
input VAR5 ,
input VAR4 ,
input VAR1
);
endmodule | apache-2.0 |
takeshineshiro/fpga_fibre_scan | HUCB2P0_150701/03_usb/usb_uart.v | 13,923 | module MODULE1#(
parameter VAR19 = 115200 , parameter VAR3 = 60 )
(
input VAR16 ,
input VAR52 ,
input VAR38 ,
input VAR27 ,
input VAR13 ,
input [7 : 0] VAR1 ,
output VAR4 ,
input VAR32 ,
output [7 : 0] VAR14 ,
output VAR40 ,
output VAR6 ,
input VAR18
);
localparam VAR49 = (VAR3 * 1000000)/VAR19;
reg [15: 0] VAR42 = VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_gpio_ovtv2/sky130_fd_io__top_gpio_ovtv2.pp.blackbox.v | 3,514 | module MODULE1 (
VAR34 ,
VAR4 ,
VAR19 ,
VAR21 ,
VAR15 ,
VAR40 ,
VAR13 ,
VAR10,
VAR23 ,
VAR39 ,
VAR17 ,
VAR6 ,
VAR35 ,
VAR16 ,
VAR38 ,
VAR11 ,
VAR25 ,
VAR18 ,
VAR31 ,
VAR32 ,
VAR14 ,
VAR2 ,
VAR28 ,
VAR9 ,
VAR8 ,
VAR24 ,
VAR20 ,
VAR29 ,
VAR3 ,
VAR12 ,
VAR27 ,
VAR5 ,
VAR7 ,
VAR30 ,
VAR26 ,
VAR22 ,
VAR36 ,
VAR1 ,
VAR33 ,
V... | apache-2.0 |
Franderg/Ascensor | fpgadisplay_controller.v | 1,587 | module MODULE1(
input clk,
input VAR12,
input VAR3,
input VAR4,
input VAR15,
output reg [6:0] VAR2,
output reg [3:0] VAR17,
output reg VAR9
);
reg [1:0] VAR7, VAR1;
parameter VAR14 = 2'b00, VAR6 = 2'b01, VAR10 = 2'b10, VAR13 = 2'b11;
VAR8 begin VAR7 = VAR14; end
wire VAR11;
wire VAR5;
wire VAR18;
VAR16 VAR19 (VAR11, VA... | gpl-3.0 |
ptracton/wb_soc_template | rtl/bus_matrix/soc_bus_matrix.v | 15,176 | module MODULE1
(input VAR67,
input VAR26,
input [31:0] VAR60,
input [31:0] VAR46,
input [3:0] VAR143,
input VAR182,
input VAR183,
input VAR5,
input [2:0] VAR39,
input [1:0] VAR3,
output [31:0] VAR142,
output VAR149,
output VAR168,
output VAR94,
input [31:0] VAR160,
input [31:0] VAR202,
input [3:0] VAR175,
input VAR196,... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/analog/bw_clk/rtl/flop_rptrs_xa0.v | 33,057 | module MODULE1(
VAR32, VAR11, VAR69, VAR10, VAR27,
VAR1, VAR4, VAR25, VAR48,
VAR79, VAR20, VAR72, VAR23, VAR41, VAR47,
VAR77, VAR49, VAR61, VAR63, VAR66, VAR59,
VAR13
);
output [25:0] VAR48; output VAR25; output VAR4; output VAR1; output VAR27; output VAR10; output VAR69; output VAR11; output [5:0] VAR32;
input VAR13; ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o32a/sky130_fd_sc_ls__o32a.blackbox.v | 1,384 | module MODULE1 (
VAR2 ,
VAR1,
VAR8,
VAR9,
VAR5,
VAR6
);
output VAR2 ;
input VAR1;
input VAR8;
input VAR9;
input VAR5;
input VAR6;
supply1 VAR3;
supply0 VAR10;
supply1 VAR4 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
Anirudh94/Connect4-FPGA | Connect4/player2.v | 6,214 | module MODULE1 (
address,
VAR13,
VAR30);
input [10:0] address;
input VAR13;
output [2:0] VAR30;
tri1 VAR13;
wire [2:0] VAR37;
wire [2:0] VAR30 = VAR37[2:0];
VAR33 VAR12 (
.VAR36 (address),
.VAR24 (VAR13),
.VAR28 (VAR37),
.VAR49 (1'b0),
.VAR27 (1'b0),
.VAR31 (1'b1),
.VAR5 (1'b0),
.VAR29 (1'b0),
.VAR35 (1'b1),
.VAR48 (1'... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21bo/sky130_fd_sc_hdll__a21bo.pp.symbol.v | 1,393 | module MODULE1 (
input VAR1 ,
input VAR6 ,
input VAR8,
output VAR3 ,
input VAR7 ,
input VAR2,
input VAR5,
input VAR4
);
endmodule | apache-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/board/dma_pcie_bridge/dma_pcie_bridge.v | 4,652 | module MODULE1
(
clk,
reset,
VAR28,
VAR22,
VAR26,
VAR37,
VAR6,
VAR15,
VAR10,
VAR19,
VAR40,
VAR30,
VAR21,
VAR14,
VAR3,
VAR20,
VAR4,
VAR12,
VAR31,
VAR42
);
parameter VAR41 = 256;
parameter VAR29 = 64;
parameter VAR18 = 6;
parameter VAR11 = 10;
parameter VAR13 = 30; parameter VAR17 = 0;
localparam VAR36 = VAR41 / 8;
local... | mit |
sarchar/uart_de0_nano | uart_divider.v | 1,553 | module MODULE1
(input VAR4,
input reset,
output reg VAR7,
output reg VAR1);
localparam VAR8 = VAR6(VAR9);
reg [(VAR8-1):0] counter;
always @(posedge VAR4 or posedge reset)
begin
if(reset) begin
counter <= 'b0;
VAR7 <= 'b0;
end else begin
if(counter == (VAR9 - 1)) begin
counter <= 'b0;
VAR7 <= ~VAR7;
end else
counter <=... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/tapvgnd/sky130_fd_sc_lp__tapvgnd.behavioral.v | 1,193 | module MODULE1 ();
supply1 VAR3;
supply0 VAR4;
supply1 VAR1 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and4bb/sky130_fd_sc_hs__and4bb.pp.symbol.v | 1,301 | module MODULE1 (
input VAR7 ,
input VAR3 ,
input VAR6 ,
input VAR5 ,
output VAR1 ,
input VAR4,
input VAR2
);
endmodule | apache-2.0 |
eda-globetrotter/MarcheProcessor | wwp/control.v | 5,034 | module MODULE1(VAR25,
VAR5, VAR27, VAR34,
VAR26, VAR12, VAR32,
VAR19, VAR4, VAR14, VAR10,
VAR9,
VAR11,
VAR15);
input [0:31] VAR25;
output [0:4] VAR5, VAR4, VAR14, VAR10;
output [0:2] VAR27, VAR19, VAR26;
output [0:1] VAR34;
output [0:20] VAR12;
output VAR9, VAR11;
output [0:15] VAR32;
output [0:31] VAR15;
reg [0:4] VAR... | mit |
scalable-networks/ext | uhd/fpga/usrp2/serdes/serdes_fc_rx.v | 1,904 | module MODULE1
parameter VAR6 = 320)
(input clk, input rst,
input [15:0] VAR1,
output reg VAR5,
output reg VAR8,
input VAR2);
reg [15:0] VAR7;
reg VAR4, VAR9;
always @(posedge clk)
if(rst)
begin
VAR4 <= 0;
VAR9 <= 0;
VAR7 <= 0;
end
else
begin
VAR4 <= 0;
VAR9 <= 0;
if(VAR7 == 0)
if(VAR1 < VAR3)
begin
VAR9 <= 1;
VAR7 <= ... | gpl-2.0 |
alan4186/ParCNN | DE2_115_CAMERA/Sdram_Control/Sdram_Control.v | 16,887 | module MODULE1 (
VAR100,
VAR77,
VAR95,
VAR117,
VAR69,
VAR131,
VAR136,
VAR75,
VAR112,
VAR118,
VAR82,
VAR52,
VAR70,
VAR138,
VAR22,
VAR23,
VAR135,
VAR12,
VAR51,
VAR49,
VAR26,
VAR127,
VAR86,
VAR84,
VAR42,
VAR108,
VAR16,
VAR19,
VAR103,
VAR124,
VAR140,
VAR114,
VAR4,
VAR79,
VAR25,
VAR6,
VAR48,
VAR91,
VAR60
);
input VAR100; in... | mit |
ElegantLin/My-CPU | Snake/Snake.srcs/sources_1/new/top_greedy_snake.v | 2,148 | module MODULE1
(
input clk,
input rst,
input VAR37,
input VAR18,
input VAR4,
input VAR45,
output VAR24,
output VAR14,
output [11:0]VAR17,
output [7:0]VAR44,
output [3:0]sel
);
wire VAR22;
wire VAR36;
wire VAR21;
wire VAR10;
wire [1:0]VAR20;
wire [9:0]VAR7;
wire [9:0]VAR9;
wire [5:0]VAR41;
wire [4:0]VAR35;
wire [5:0]VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/xor2/sky130_fd_sc_hdll__xor2_2.v | 2,133 | module MODULE2 (
VAR8 ,
VAR3 ,
VAR2 ,
VAR1,
VAR6,
VAR7 ,
VAR9
);
output VAR8 ;
input VAR3 ;
input VAR2 ;
input VAR1;
input VAR6;
input VAR7 ;
input VAR9 ;
VAR5 VAR4 (
.VAR8(VAR8),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR9(VAR9)
);
endmodule
module MODULE2 (
VAR8,
VAR3,
VAR2
);
output VAR8;
... | apache-2.0 |
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