repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
aquaxis/FPGAMAG18 | fmrv32im-artya7.nonos/fmrv32im-artya7.srcs/sources_1/bd/fmrv32im_artya7/hdl/fmrv32im_artya7.v | 16,169 | module MODULE2
(VAR26,
VAR32,
VAR1,
VAR113,
VAR202,
VAR53);
input VAR26;
input [31:0]VAR32;
output [31:0]VAR1;
output [31:0]VAR113;
input VAR202;
output VAR53;
wire VAR52;
wire [0:0]VAR43;
wire [31:0]VAR128;
wire [3:0]VAR8;
wire [2:0]VAR67;
wire VAR229;
wire VAR29;
wire [31:0]VAR206;
wire [3:0]VAR73;
wire [2:0]VAR173;
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/buf/sky130_fd_sc_lp__buf_lp.v | 2,001 | module MODULE1 (
VAR2 ,
VAR6 ,
VAR5,
VAR3,
VAR8 ,
VAR7
);
output VAR2 ;
input VAR6 ;
input VAR5;
input VAR3;
input VAR8 ;
input VAR7 ;
VAR4 VAR1 (
.VAR2(VAR2),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR2,
VAR6
);
output VAR2;
input VAR6;
supply1 VAR5;
supply0 VAR3;... | apache-2.0 |
alexforencich/hdg2000 | fpga/rtl/wb_mcb_8.v | 4,239 | module MODULE1
(
input wire clk,
input wire rst,
input wire [31:0] VAR1, input wire [7:0] VAR21, output wire [7:0] VAR4, input wire VAR27, input wire VAR8, output wire VAR22, input wire VAR16,
output wire VAR19,
output wire VAR3,
output wire [2:0] VAR18,
output wire [5:0] VAR38,
output wire [31:0] VAR5,
input wire VAR1... | mit |
kyzhai/NUNY | src/hardware/bg3_new.v | 6,392 | module MODULE1 (
address,
VAR2,
VAR42);
input [14:0] address;
input VAR2;
output [11:0] VAR42;
tri1 VAR2;
wire [11:0] VAR40;
wire [11:0] VAR42 = VAR40[11:0];
VAR19 VAR9 (
.VAR20 (address),
.VAR41 (VAR2),
.VAR14 (VAR40),
.VAR45 (1'b0),
.VAR37 (1'b0),
.VAR12 (1'b1),
.VAR46 (1'b0),
.VAR31 (1'b0),
.VAR36 (1'b1),
.VAR29 (1'... | gpl-2.0 |
combinatorylogic/soc | backends/c2/hw/nexys4ddr/vgatop640x480grey.v | 3,674 | module MODULE1(input clk,
input [19:0] VAR44,
input [7:0] VAR25,
output reg [7:0] VAR8,
input VAR21,
input VAR41,
input [19:0] VAR33,
output reg [7:0] VAR17);
reg [7:0] VAR3[0:153600-1];
always @(posedge clk)
begin
if (VAR21) begin
VAR3[VAR44] <= VAR25;
end else if (VAR41) begin
VAR8 <= VAR3[VAR44];
end
VAR17 <= VAR3[V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xnor2/sky130_fd_sc_lp__xnor2.blackbox.v | 1,274 | module MODULE1 (
VAR3,
VAR2,
VAR7
);
output VAR3;
input VAR2;
input VAR7;
supply1 VAR4;
supply0 VAR6;
supply1 VAR5 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
GSejas/Aproximate-Arithmetic-Operators | src_lib/addlib/GDA_St_N8_M8_P2.v | 2,265 | module MODULE1(
input [7:0] VAR53,
input [7:0] VAR26,
output [8:0] VAR43
);
wire [2:0] VAR2, VAR48, VAR22, VAR56, VAR12, VAR70, VAR3, VAR44;
wire VAR1,VAR6,VAR36,VAR25,VAR49,VAR40,VAR47,VAR63,VAR33,VAR55,VAR18,VAR65,VAR67,VAR13,VAR41,VAR8,VAR9,VAR45,VAR68,VAR16,VAR23;
wire VAR50,VAR59,VAR34,VAR62,VAR38,VAR61;
wire VAR2... | apache-2.0 |
ASP-SoC/ASP-SoC | libASP/grpPlatform/unitPlatformHps/synlayQuartus/ASP/Platform_bb.v | 5,305 | module MODULE1 (
VAR51,
VAR64,
VAR80,
VAR2,
VAR23,
VAR31,
VAR49,
VAR42,
VAR19,
VAR17,
VAR5,
VAR10,
VAR55,
VAR21,
VAR84,
VAR24,
VAR88,
VAR30,
VAR76,
VAR52,
VAR29,
VAR25,
VAR32,
VAR63,
VAR46,
VAR16,
VAR62,
VAR39,
VAR27,
VAR6,
VAR38,
VAR41,
VAR79,
VAR72,
VAR87,
VAR44,
VAR58,
VAR65,
VAR28,
VAR57,
VAR4,
VAR13,
VAR22,
VAR81,... | gpl-3.0 |
cafe-alpha/wascafe | v13/wasca_10m08sc_20191205_abus_divide/wasca/synthesis/submodules/wasca_altpll_0.v | 11,005 | module MODULE1
(
VAR3,
VAR4,
VAR2,
VAR1) ;
input VAR3;
input VAR4;
input [0:0] VAR2;
output [0:0] VAR1;
tri0 VAR3;
tri1 VAR4;
reg [0:0] VAR5;
reg [0:0] VAR8;
reg [0:0] VAR6;
wire VAR9;
wire VAR7;
wire VAR10; | gpl-2.0 |
sehugg/8bitworkshop | presets/verilog/sprite_rotation.v | 11,446 | module MODULE1(addr, VAR1);
input [7:0] addr;
output [7:0] VAR1;
reg [15:0] VAR2[0:255];
assign VAR1 = (addr[0]) ? VAR2[addr>>1][15:8] : VAR2[addr>>1][7:0];
begin
begin
end | gpl-3.0 |
DProvinciani/Arquitectura_TPF | Codigo_fuente/7-uart/rx.v | 3,990 | module MODULE1
parameter VAR8 = 8 , VAR1 = 16 )
(
input wire clk, reset, input wire MODULE1, VAR13, output reg VAR16, output wire [VAR8-1:0] dout );
localparam [1:0]
VAR15 = 2'b00,
VAR6 = 2'b01,
VAR11 = 2'b10,
VAR9 = 2'b11;
reg [1:0] VAR10, VAR7; reg [3:0] VAR12, VAR14; reg [2:0] VAR3, VAR4; reg [VAR8-1:0] VAR2, VAR5;
... | gpl-3.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeDE1SoC/CS_bak/synthesis/submodules/altera_up_avalon_reset_from_locked_signal.v | 3,921 | module MODULE1 (
VAR1,
reset
);
input VAR1;
output reset;
assign reset = ~VAR1;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a32o/sky130_fd_sc_lp__a32o.pp.symbol.v | 1,431 | module MODULE1 (
input VAR4 ,
input VAR10 ,
input VAR7 ,
input VAR3 ,
input VAR6 ,
output VAR1 ,
input VAR9 ,
input VAR5,
input VAR8,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and4b/sky130_fd_sc_ls__and4b_4.v | 2,300 | module MODULE2 (
VAR3 ,
VAR2 ,
VAR9 ,
VAR1 ,
VAR5 ,
VAR10,
VAR7,
VAR8 ,
VAR4
);
output VAR3 ;
input VAR2 ;
input VAR9 ;
input VAR1 ;
input VAR5 ;
input VAR10;
input VAR7;
input VAR8 ;
input VAR4 ;
VAR11 VAR6 (
.VAR3(VAR3),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR... | apache-2.0 |
tmeissner/cryptocores | tdes/rtl/verilog/tdes.v | 3,356 | module MODULE1
(
input VAR22, input VAR3, input VAR10, input [0:63] VAR9, input [0:63] VAR27, input [0:63] VAR19, input [0:63] VAR6, input VAR24, output [0:63] VAR14, output VAR11, output reg VAR28 );
reg VAR5;
reg [0:63] VAR15;
reg [0:63] VAR16;
reg [0:63] VAR17;
wire VAR1;
wire VAR26;
wire [0:63] VAR8;
wire [0:63] VA... | gpl-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_3L_024bits.v | 1,917 | module MODULE1 (
clk,
VAR9, VAR31, VAR10, VAR22, VAR20, VAR28, VAR32, VAR34,
sum,
);
input clk;
input [VAR5+0-1:0] VAR9, VAR31, VAR10, VAR22, VAR20, VAR28, VAR32, VAR34;
output [VAR5 :0] sum;
reg [VAR5 :0] sum;
wire [VAR5+3-1:0] VAR3;
wire [VAR5+2-1:0] VAR1, VAR17;
wire [VAR5+1-1:0] VAR14, VAR26, VAR25, VAR11;
reg [VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_isolatch_pp_pkg_s/sky130_fd_sc_hs__udp_isolatch_pp_pkg_s.blackbox.v | 1,484 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR6,
VAR3 ,
VAR4 ,
VAR5
);
output VAR2 ;
input VAR1 ;
input VAR6;
input VAR3 ;
input VAR4 ;
input VAR5 ;
endmodule | apache-2.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_light/spw_light/synthesis/submodules/spw_light_rxdata.v | 1,850 | module MODULE1 (
address,
clk,
VAR4,
VAR6,
VAR1
)
;
output [ 31: 0] VAR1;
input [ 1: 0] address;
input clk;
input [ 7: 0] VAR4;
input VAR6;
wire VAR2;
wire [ 7: 0] VAR3;
wire [ 7: 0] VAR5;
reg [ 31: 0] VAR1;
assign VAR2 = 1;
assign VAR5 = {8 {(address == 0)}} & VAR3;
always @(posedge clk or negedge VAR6)
begin
if (VAR6... | gpl-3.0 |
ShirmanXia/EE469SPRING16 | lab4/nios_system/synthesis/submodules/nios_system_LEDs.v | 2,167 | module MODULE1 (
address,
VAR5,
clk,
VAR2,
VAR7,
VAR9,
VAR1,
VAR4
)
;
output [ 9: 0] VAR1;
output [ 31: 0] VAR4;
input [ 1: 0] address;
input VAR5;
input clk;
input VAR2;
input VAR7;
input [ 31: 0] VAR9;
wire VAR3;
reg [ 9: 0] VAR8;
wire [ 9: 0] VAR1;
wire [ 9: 0] VAR6;
wire [ 31: 0] VAR4;
assign VAR3 = 1;
assign VAR6 ... | gpl-3.0 |
secworks/trng | src/rtl/wrappers/trng_avalanche_entropy.v | 4,298 | module MODULE1(
input wire clk,
input wire VAR14,
input wire VAR4,
);
VAR7 VAR13(
.clk(clk),
.VAR14(VAR14),
.enable(VAR8),
.VAR17(VAR4),
.VAR16(VAR15),
.VAR18(VAR3),
.VAR5(VAR2),
.VAR11(VAR1),
.VAR19(VAR12),
.VAR6(VAR10),
.VAR9()
);
always @ (posedge clk or negedge VAR14)
begin
if (!VAR14)
begin
end
else
begin
end
end
... | bsd-2-clause |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/multi_fft/multi_fft_stub.v | 1,166 | module MODULE1(VAR3, VAR4, VAR2, VAR1)
;
input VAR3;
input [28:0]VAR4;
input [28:0]VAR2;
output [57:0]VAR1;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlrtn/sky130_fd_sc_ls__dlrtn.behavioral.pp.v | 2,446 | module MODULE1 (
VAR15 ,
VAR7,
VAR12 ,
VAR4 ,
VAR6 ,
VAR16 ,
VAR13 ,
VAR19
);
output VAR15 ;
input VAR7;
input VAR12 ;
input VAR4 ;
input VAR6 ;
input VAR16 ;
input VAR13 ;
input VAR19 ;
wire VAR22 ;
wire VAR21 ;
reg VAR10 ;
wire VAR20 ;
wire VAR1 ;
wire VAR14 ;
wire VAR9;
wire VAR18 ;
wire VAR2 ;
wire VAR17 ;
wire VAR... | apache-2.0 |
eda-globetrotter/PicenoDecoders | extra_credit/syn/src/encoder.v | 1,631 | module MODULE1 (VAR1,VAR2);
output [14:0] VAR2;
input [10:0] VAR1;
assign VAR2[2]=VAR1[0];
assign VAR2[4]=VAR1[1];
assign VAR2[5]=VAR1[2];
assign VAR2[6]=VAR1[3];
assign VAR2[8]=VAR1[4];
assign VAR2[9]=VAR1[5];
assign VAR2[10]=VAR1[6];
assign VAR2[11]=VAR1[7];
assign VAR2[12]=VAR1[8];
assign VAR2[13]=VAR1[9];
assign VA... | mit |
olgirard/opengfx430 | core/bench/verilog/lt24Model.v | 9,361 | module MODULE1 (
VAR38, VAR25, VAR62, VAR68,
VAR43, VAR6, VAR23, VAR40, VAR18, VAR15, VAR11, VAR51, VAR55, VAR31, VAR60 );
output [15:0] VAR38; output VAR25; output VAR62; output VAR68;
input VAR43; input VAR6; input VAR23; input VAR40; input [15:0] VAR18; input VAR15; input VAR11; input VAR51; input VAR55; input VAR31... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a31o/sky130_fd_sc_ls__a31o.functional.pp.v | 2,026 | module MODULE1 (
VAR15 ,
VAR3 ,
VAR14 ,
VAR16 ,
VAR8 ,
VAR7,
VAR4,
VAR6 ,
VAR9
);
output VAR15 ;
input VAR3 ;
input VAR14 ;
input VAR16 ;
input VAR8 ;
input VAR7;
input VAR4;
input VAR6 ;
input VAR9 ;
wire VAR13 ;
wire VAR2 ;
wire VAR5;
and VAR17 (VAR13 , VAR16, VAR3, VAR14 );
or VAR12 (VAR2 , VAR13, VAR8 );
VAR10 VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/einvp/sky130_fd_sc_hs__einvp_1.v | 2,002 | module MODULE2 (
VAR6 ,
VAR3 ,
VAR5 ,
VAR1,
VAR4
);
input VAR6 ;
input VAR3 ;
output VAR5 ;
input VAR1;
input VAR4;
VAR7 VAR2 (
.VAR6(VAR6),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR6 ,
VAR3,
VAR5
);
input VAR6 ;
input VAR3;
output VAR5 ;
supply1 VAR1;
supply0 VAR4;
VAR7 VAR2 ... | apache-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/Command_FIFO.v | 13,412 | module MODULE1(
clk,
rst,
din,
VAR246,
VAR165,
dout,
VAR42,
VAR40,
valid
);
input clk;
input rst;
input [127 : 0] din;
input VAR246;
input VAR165;
output [127 : 0] dout;
output VAR42;
output VAR40;
output valid;
VAR285 #(
.VAR91(0),
.VAR321(0),
.VAR187(0),
.VAR169(0),
.VAR283(0),
.VAR88(0),
.VAR404(0),
.VAR6(32),
.VAR2... | gpl-2.0 |
takeshineshiro/fpga_linear_128 | IMG_TRI_BUFFER_bb.v | 6,651 | module MODULE1 (
VAR2,
VAR8,
VAR3,
VAR1,
VAR4,
VAR5,
VAR7,
VAR9,
VAR6);
input [7:0] VAR2;
input [10:0] VAR8;
input [10:0] VAR3;
input VAR1;
input [10:0] VAR4;
input VAR5;
input VAR7;
output [7:0] VAR9;
output [7:0] VAR6;
tri1 VAR7;
endmodule | mit |
twlostow/dsi-shield | hdl/rtl/hpdmc/spartan6/hpdmc_oddr16.v | 3,878 | module MODULE1 #(
parameter VAR17 = "VAR24",
parameter VAR2 = 1'b0,
parameter VAR26 = "VAR5"
) (
output [15:0] VAR10,
input VAR24,
input VAR19,
input VAR27,
input [15:0] VAR18,
input [15:0] VAR11,
input VAR4,
input VAR13
);
VAR7 #(
.VAR17(VAR17),
.VAR2(VAR2),
.VAR26(VAR26)
) VAR23 (
.VAR10(VAR10[0]),
.VAR24(VAR24),
.VA... | lgpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/HardFloat/source/mulAddRecFN.v | 21,730 | module
MODULE3#(
parameter VAR32 = 3, parameter VAR124 = 3, parameter VAR140 = 1
) (
VAR102,
VAR82,
VAR134,
VAR59,
VAR118,
VAR55,
VAR73,
VAR57,
VAR21,
VAR74,
VAR116,
VAR6,
VAR34
);
input [(VAR14 - 1):0] VAR102;
input [2:0] VAR82;
input [(VAR32 + VAR124):0] VAR134;
input [(VAR32 + VAR124):0] VAR59;
input [(VAR32 + VAR12... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tapvgnd/sky130_fd_sc_ls__tapvgnd.pp.symbol.v | 1,258 | module MODULE1 (
input VAR1 ,
input VAR3,
input VAR2,
input VAR4
);
endmodule | apache-2.0 |
Cognoscan/BoostLogic | verilog/src/transceivers/XcvrSpiSlave.v | 5,670 | module MODULE1 #(
parameter VAR15 = 4
)
(
input clk, input rst, input [7:0] VAR23, input write, input read, input VAR22, input VAR8, input VAR17, input VAR9, input VAR10, output VAR3, output VAR20, output VAR29, output VAR12, output VAR34, output VAR33, output VAR2, output [7:0] VAR21 );
wire [7:0] VAR18;
wire [7:0] VA... | apache-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_amphy/alt_mem_ddrx_ddr2_odt_gen.v | 17,986 | module MODULE1
VAR2 = 2,
VAR16 = 3,
VAR30 = 1,
VAR24 = 4
)
(
VAR9,
VAR6,
VAR11,
VAR4,
VAR18,
VAR22,
VAR8,
VAR13,
VAR20,
VAR12
);
localparam integer VAR35 = 2**VAR24; localparam VAR19 = 2;
localparam VAR31 = 2.5;
input VAR9;
input VAR6;
input [VAR24-1:0] VAR11;
input [VAR16-1:0] VAR4;
input [4:0] VAR18;
input [VAR30-1:0... | lgpl-3.0 |
borti4938/n64rgb | advancedRGBmod/firmware/rtl/ppu/vconv.v | 7,672 | module MODULE1(
VAR23,
VAR5,
VAR18,
VAR9,
VAR1,
VAR11,
VAR21
);
localparam VAR26 = 20;
input VAR23;
input VAR5;
input VAR18;
input VAR9;
input [VAR7] VAR1;
output reg VAR11 = 1'b0;
output [VAR7] VAR21;
wire [3:0] VAR25 = VAR1[VAR8];
wire unsigned [VAR14-1:0] VAR3 = VAR1[VAR13];
wire unsigned [VAR14-1:0] VAR24 = VAR1[VA... | gpl-3.0 |
diegovalverde/papiGB | rtl/sound_controller_modules/SoundControllerChannel2.v | 4,311 | module MODULE1 (
input wire VAR1, input wire VAR23,
input wire VAR16, input wire VAR13, input wire VAR20,
input wire [7:0] VAR2,
input wire [7:0] VAR26,
input wire [7:0] VAR5,
input wire [7:0] VAR18,
output reg [4:0] VAR21,
output wire VAR10
);
reg [5:0] VAR7;
reg [19:0] VAR12;
reg [1:0] VAR17;
reg VAR4;
reg VAR25;
reg... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv.blackbox.v | 1,315 | module MODULE1 (
VAR1,
VAR2
);
output VAR1;
input VAR2 ;
supply1 VAR4;
supply1 VAR3 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
pradeep9676/pradeep_9676 | lzd_4bit.v | 1,954 | module MODULE1( in, out, valid
);
input [3:0]in;
output reg [1:0]out;
output reg valid;
wire VAR6,VAR3, VAR4, VAR5; VAR7
begin out<=2'b00;
valid<=0;
end
VAR8 VAR2( .in(in[1:0]), .out(VAR4), .valid(VAR6)); VAR8 VAR1( .in(in[3:2]), .out(VAR5), .valid(VAR3));
always@(in,VAR6,VAR3,VAR4,VAR5) begin
if(VAR3==0&& VAR6==1)
beg... | mit |
bangonkali/quartus-sockit | soc_system/synthesis/submodules/alt_vipitc131_IS2Vid_statemachine.v | 9,039 | module MODULE1(
input wire rst,
input wire clk,
input wire VAR11,
input wire VAR2,
input wire VAR5,
input wire VAR13,
input wire [3:0] VAR6,
input wire VAR19,
input wire VAR27,
input wire VAR14,
input wire VAR22,
output wire [3:0] VAR12,
output wire [3:0] state
);
parameter VAR9 = 0;
parameter VAR4 = 0;
parameter [3:0]... | mit |
duttondj/DigitalDesignI-P2 | counter_9bit.v | 2,245 | module MODULE1 (enable, VAR1, clk, VAR2);
parameter VAR6 = 10; parameter VAR3 = 15;
input enable; input VAR1; input clk; output [8:0] VAR2; reg [8:0] VAR2;
reg [8:0] VAR5;
VAR4 VAR5 = 0;
always @(posedge clk or VAR1) begin
if (VAR1 == 1) begin
VAR5 = 9'b0;
VAR2 = #VAR6 VAR5;
end
else if (clk == 1) begin
if (enable == 1... | mit |
Triple-Z/COExperiment_Repo | Project_Assignment_OnBoard/ctrl.v | 10,825 | module MODULE1 (VAR50, VAR41, VAR22, VAR53, VAR21, VAR69, VAR10, VAR26, VAR7, VAR32, VAR33, VAR44, VAR65, VAR23, VAR68, VAR46);
input [31:0] VAR50;
output reg [3:0] VAR10;
output reg VAR41;
output reg VAR22;
output reg [1:0] VAR53;
output reg [1:0] VAR21;
output reg [1:0] VAR69;
output reg [1:0] VAR26;
output reg [1:0]... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/einvp/sky130_fd_sc_hvl__einvp.functional.v | 1,210 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR4
);
output VAR3 ;
input VAR2 ;
input VAR4;
notif1 VAR1 (VAR3 , VAR2, VAR4 );
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/controllerHdl_Encoder_To_Position_And_Velocity.v | 3,383 | module MODULE1
(
VAR14,
reset,
VAR5,
VAR1,
VAR9,
VAR4,
VAR3,
VAR6,
VAR8,
VAR10
);
input VAR14;
input reset;
input VAR5;
input VAR1;
input [15:0] VAR9; input signed [17:0] VAR4; output VAR3;
output signed [17:0] VAR6; output signed [17:0] VAR8; output signed [17:0] VAR10;
wire signed [17:0] VAR12; wire signed [17:0] VAR... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_misc/rtl/bw_io_misc_chunk2.v | 4,308 | module MODULE1(VAR39 ,VAR41 ,VAR20 ,VAR13 ,
VAR42 ,VAR27 ,VAR37 ,VAR23 ,VAR3 ,
VAR40 ,VAR22 ,VAR29 ,VAR1 ,VAR26 ,VAR33 ,VAR4 ,VAR35 ,VAR17 ,
VAR5 ,VAR19 ,VAR11 ,VAR47 ,VAR6 ,VAR14 ,VAR48 ,VAR36 ,
VAR18 ,clk ,VAR9 );
input [5:4] VAR40 ;
output VAR39 ;
output VAR13 ;
output VAR3 ;
output VAR26 ;
output VAR33 ;
input VAR4... | gpl-2.0 |
tmolteno/TART | hardware/FPGA/ddrmem/Xilinx/xc.v | 53,240 | module MODULE1(
VAR153,
clk,
VAR5,
VAR39,
address,
VAR97,
VAR222,
VAR177,
VAR183,
VAR95,
VAR186,
VAR209,
VAR144,
VAR43,
VAR6,
VAR105,
VAR192,
VAR143,
VAR3,
VAR136,
VAR138,
VAR139,
VAR70,
VAR171,
VAR33
);
input VAR153;
input clk;
input VAR5;
input VAR39;
input[21:0] address;
input[1:0] VAR97;
input[9:0] VAR222;
input[2:... | lgpl-3.0 |
migajv/mips_pipeline | verilog/pc.v | 1,113 | module MODULE1(
input clk,
output [31:0] MODULE1,
input VAR4,
input [31:0] VAR6);
reg VAR7 = 1'b0;
reg [31:0] VAR1 = 32'd0;
reg [31:0] VAR3 = 32'd0;
reg [31:0] VAR2 = 32'd0;
reg [31:0] VAR5 = 32'd0;
assign MODULE1 = VAR1;
always @(posedge clk) begin
if (VAR7)
end
VAR1 <= VAR5; else
VAR1 <= VAR1 + 4;
VAR3 <= VAR1;
VAR2 ... | gpl-3.0 |
asicguy/gplgpu | hdl/altera_project/de_pll/de_PLL_bb.v | 10,547 | module MODULE1 (
VAR1,
VAR2,
VAR3);
input VAR1;
input VAR2;
output VAR3;
endmodule | gpl-3.0 |
chriswynnyk/american-put-verilog | american_put_stratix/src/fp_mult_slow.v | 30,034 | module MODULE1
(
VAR32,
VAR43,
VAR53,
VAR47,
VAR58) ;
input VAR32;
input VAR43;
input [63:0] VAR53;
input [63:0] VAR47;
output [63:0] VAR58;
reg VAR23;
reg VAR64;
reg VAR12;
reg VAR16;
reg VAR21;
reg VAR22;
reg VAR44;
reg VAR20;
reg [12:0] VAR40;
reg [12:0] VAR39;
reg VAR18;
reg VAR42;
reg [11:0] VAR15;
reg [10:0] VAR2... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/decap/sky130_fd_sc_hs__decap_8.v | 1,745 | module MODULE1 (
VAR2,
VAR1
);
input VAR2;
input VAR1;
VAR3 VAR4 (
.VAR2(VAR2),
.VAR1(VAR1)
);
endmodule
module MODULE1 ();
supply1 VAR2;
supply0 VAR1;
VAR3 VAR4 ();
endmodule | apache-2.0 |
csail-csg/connectal | verilog/CONNECTNET2.v | 1,274 | module MODULE1(VAR1, VAR4, VAR2, VAR3);
output VAR1;
output VAR4;
input VAR2;
input VAR3;
assign VAR1 = VAR2;
assign VAR4 = VAR3;
endmodule | mit |
intelligenttoasters/CPC2.0 | FPGA/Quartus/DE10/HPS/synthesis/submodules/HPS_hps_0.v | 10,676 | module MODULE1 #(
parameter VAR31 = 0,
parameter VAR20 = 0
) (
output wire [66:0] VAR8, input wire [66:0] VAR23, input wire [66:0] VAR16, output wire VAR42, input wire [31:0] VAR34, output wire [31:0] VAR17, output wire [14:0] VAR14, output wire [2:0] VAR26, output wire VAR10, output wire VAR19, output wire VAR11, outp... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o221ai/sky130_fd_sc_hdll__o221ai.behavioral.pp.v | 2,234 | module MODULE1 (
VAR12 ,
VAR4 ,
VAR17 ,
VAR15 ,
VAR3 ,
VAR14 ,
VAR5,
VAR18,
VAR8 ,
VAR2
);
output VAR12 ;
input VAR4 ;
input VAR17 ;
input VAR15 ;
input VAR3 ;
input VAR14 ;
input VAR5;
input VAR18;
input VAR8 ;
input VAR2 ;
wire VAR10 ;
wire VAR6 ;
wire VAR11 ;
wire VAR9;
or VAR20 (VAR10 , VAR3, VAR15 );
or VAR16 (VAR... | apache-2.0 |
trivoldus28/pulsarch-verilog | verif/env/cmp/nc_inv_chk.v | 2,017 | module MODULE1 (
clk, VAR2, VAR6, VAR5, VAR3, VAR4, VAR1
);
input clk;
input VAR2;
input VAR6;
input [3:0] VAR5;
input VAR3;
input VAR4;
input [2:0] VAR1;
reg enable;
begin
end | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1.v | 2,519 | module MODULE2 (
VAR3 ,
VAR10 ,
VAR4 ,
VAR7 ,
VAR6 ,
VAR8,
VAR2 ,
VAR12 ,
VAR9 ,
VAR5
);
output VAR3 ;
input VAR10 ;
input VAR4 ;
input VAR7 ;
input VAR6 ;
input VAR8;
input VAR2 ;
input VAR12 ;
input VAR9 ;
input VAR5 ;
VAR1 VAR11 (
.VAR3(VAR3),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR2(... | apache-2.0 |
hydai/Verilog-Practice | DigitalDesign/101062124_hw4/fifo_ctr.v | 4,222 | module MODULE1 (
input wire clk,
input wire VAR6,
input wire VAR19,
input wire VAR22,
output reg VAR11,
output reg VAR13,
output reg VAR2,
output reg VAR8,
output reg VAR28,
output reg VAR7,
output reg VAR4,
output reg VAR12,
output reg [4:0] addr
);
parameter VAR27 = 32;
parameter delay = 1.5;
parameter VAR1 = 2'b00;
... | mit |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/pcieCore/example_design/PIO_EP_MEM_ACCESS.v | 11,627 | module MODULE1 #(
parameter VAR35 = 1
) (
clk,
VAR16,
VAR66, VAR13, VAR27,
VAR70, VAR7, VAR23, VAR44, VAR60
);
input clk;
input VAR16;
input [10:0] VAR66;
input [3:0] VAR13;
output [31:0] VAR27;
input [10:0] VAR70;
input [7:0] VAR7;
input [31:0] VAR23;
input VAR44;
output VAR60;
localparam VAR43 = 3'b000;
localparam VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/mux2/sky130_fd_sc_ms__mux2.pp.symbol.v | 1,325 | module MODULE1 (
input VAR1 ,
input VAR3 ,
output VAR5 ,
input VAR7 ,
input VAR4 ,
input VAR6,
input VAR8,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or4b/sky130_fd_sc_hdll__or4b_1.v | 2,307 | module MODULE2 (
VAR6 ,
VAR4 ,
VAR3 ,
VAR8 ,
VAR9 ,
VAR2,
VAR7,
VAR5 ,
VAR11
);
output VAR6 ;
input VAR4 ;
input VAR3 ;
input VAR8 ;
input VAR9 ;
input VAR2;
input VAR7;
input VAR5 ;
input VAR11 ;
VAR1 VAR10 (
.VAR6(VAR6),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR11... | apache-2.0 |
merckhung/zet | cores/zet/rtl/zet_muldiv.v | 3,121 | module MODULE1 (
input [31:0] VAR25, input [15:0] VAR2,
output [31:0] VAR14,
input [ 2:0] VAR28,
input VAR5,
output VAR3,
output VAR12,
input clk,
output VAR21
);
wire VAR16, VAR15, VAR9, VAR18;
wire [16:0] VAR31, VAR1;
wire [33:0] VAR13;
wire VAR10, VAR19, VAR24, VAR20;
wire [33:0] VAR29;
wire [16:0] VAR17;
wire [17:0... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfrtp/sky130_fd_sc_ls__dfrtp.pp.symbol.v | 1,402 | module MODULE1 (
input VAR8 ,
output VAR1 ,
input VAR7,
input VAR6 ,
input VAR3 ,
input VAR5 ,
input VAR2 ,
input VAR4
);
endmodule | apache-2.0 |
CospanDesign/sdio-device | rtl/cia/sdio_fbr.v | 4,835 | module MODULE1 #(
parameter VAR24 = 0,
parameter VAR12 = 4'h0,
parameter VAR37 = 4'h0,
parameter VAR30 = 1'b0,
parameter VAR25 = 0,
parameter VAR3 = 0,
parameter VAR16 = 0,
parameter VAR45 = 256
)(
input clk,
input rst,
output reg VAR22,
output reg [3:0] VAR31,
output reg [15:0] VAR2,
input VAR10,
input VAR41,
input [7... | mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/system/synthesis/submodules/system_acl_iface_hps_hps_io.v | 6,777 | module MODULE1 (
output wire [14:0] VAR42, output wire [2:0] VAR41, output wire VAR2, output wire VAR18, output wire VAR14, output wire VAR15, output wire VAR20, output wire VAR22, output wire VAR29, output wire VAR13, inout wire [31:0] VAR5, inout wire [3:0] VAR34, inout wire [3:0] VAR31, output wire VAR7, output wire... | mit |
kyzhai/NUNY | src/hardware/clock_pll/clock_pll_0002.v | 2,141 | module MODULE1(
input wire VAR28,
input wire rst,
output wire VAR12,
output wire VAR70,
output wire VAR58
);
VAR36 #(
.VAR68("false"),
.VAR6("50.0 VAR65"),
.VAR46("VAR9"),
.VAR55(2),
.VAR4("11.288659 VAR65"),
.VAR66("0 VAR51"),
.VAR37(50),
.VAR53("49.772727 VAR65"),
.VAR31("0 VAR51"),
.VAR13(50),
.VAR5("0 VAR65"),
.VAR... | gpl-2.0 |
drichmond/riffa | fpga/riffa_hdl/tx_port_monitor_128.v | 7,924 | module MODULE1 #(
parameter VAR13 = 9'd128,
parameter VAR12 = 512,
parameter VAR37 = (VAR12 - 4),
parameter VAR40 = VAR1((2**VAR1(VAR12))+1),
parameter VAR41 = 1
)
(
input VAR27,
input VAR28,
input [VAR13:0] VAR30, input VAR38, output VAR8,
output [VAR13-1:0] VAR6, output VAR15, input [VAR40-1:0] VAR36,
output VAR17, i... | bsd-3-clause |
TalentlessAlpaca/Automated_Vacuum_Cleaner | Position/position_j1_tst.v | 2,483 | module MODULE1;
reg clk;
reg rst;
reg VAR11;
wire VAR22;
wire VAR9;
wire [31:0] VAR27;
reg VAR3;
reg rd;
reg wr;
reg [4:0] addr;
reg [15:0] din;
wire [15:0] dout;
wire VAR6;
wire VAR29;
wire [31:0] VAR5;
wire VAR15;
wire VAR16;
wire VAR17;
wire [31:0] VAR26;
wire VAR12;
wire VAR13;
assign VAR13 = VAR6? VAR29 : VAR11;
V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfxtp/sky130_fd_sc_hs__dfxtp.behavioral.v | 1,704 | module MODULE1 (
VAR9 ,
VAR4 ,
VAR13 ,
VAR7,
VAR10
);
input VAR9 ;
input VAR4 ;
output VAR13 ;
input VAR7;
input VAR10;
wire VAR12 ;
reg VAR5 ;
wire VAR8 ;
wire VAR2;
wire VAR1 ;
VAR11 VAR6 (VAR12 , VAR8, VAR2, VAR5, VAR7, VAR10);
assign VAR1 = ( VAR7 === 1'b1 );
buf VAR3 (VAR13 , VAR12 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/edfxbp/sky130_fd_sc_ms__edfxbp.blackbox.v | 1,378 | module MODULE1 (
VAR6 ,
VAR3,
VAR1,
VAR9 ,
VAR2
);
output VAR6 ;
output VAR3;
input VAR1;
input VAR9 ;
input VAR2 ;
supply1 VAR7;
supply0 VAR4;
supply1 VAR8 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/video_sys/synthesis/submodules/video_sys_Video_RGB_Resampler.v | 7,563 | module MODULE1 (
clk,
reset,
VAR7,
VAR13,
VAR19,
VAR21,
VAR11,
VAR3,
VAR17,
VAR18,
VAR22,
VAR10,
VAR4,
VAR20
);
parameter VAR6 = 23;
parameter VAR1 = 15;
parameter VAR5 = 1;
parameter VAR2 = 0;
parameter VAR8 = 10'h3FF;
input clk;
input reset;
input [VAR6:0] VAR7;
input VAR13;
input VAR19;
input [VAR5:0] VAR21;
input V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/bufbuf/sky130_fd_sc_ls__bufbuf.functional.pp.v | 1,768 | module MODULE1 (
VAR6 ,
VAR4 ,
VAR2,
VAR7,
VAR9 ,
VAR10
);
output VAR6 ;
input VAR4 ;
input VAR2;
input VAR7;
input VAR9 ;
input VAR10 ;
wire VAR8 ;
wire VAR5;
buf VAR3 (VAR8 , VAR4 );
VAR1 VAR12 (VAR5, VAR8, VAR2, VAR7);
buf VAR11 (VAR6 , VAR5 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a21bo/sky130_fd_sc_hs__a21bo.behavioral.pp.v | 1,973 | module MODULE1 (
VAR10,
VAR5,
VAR14 ,
VAR1 ,
VAR12 ,
VAR13
);
input VAR10;
input VAR5;
output VAR14 ;
input VAR1 ;
input VAR12 ;
input VAR13;
wire VAR11 ;
wire VAR2 ;
wire VAR9;
nand VAR8 (VAR11 , VAR12, VAR1 );
nand VAR7 (VAR2 , VAR13, VAR11 );
VAR3 VAR6 (VAR9, VAR2, VAR10, VAR5);
buf VAR4 (VAR14 , VAR9 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a32o/sky130_fd_sc_hdll__a32o.pp.blackbox.v | 1,466 | module MODULE1 (
VAR9 ,
VAR3 ,
VAR1 ,
VAR10 ,
VAR7 ,
VAR8 ,
VAR4,
VAR5,
VAR2 ,
VAR6
);
output VAR9 ;
input VAR3 ;
input VAR1 ;
input VAR10 ;
input VAR7 ;
input VAR8 ;
input VAR4;
input VAR5;
input VAR2 ;
input VAR6 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/and4/gf180mcu_fd_sc_mcu9t5v0__and4_4.behavioral.v | 1,322 | module MODULE1( VAR4, VAR3, VAR1, VAR8, VAR6 );
input VAR1, VAR8, VAR3, VAR4;
output VAR6;
VAR2 VAR5(.VAR4(VAR4),.VAR3(VAR3),.VAR1(VAR1),.VAR8(VAR8),.VAR6(VAR6));
VAR2 VAR7(.VAR4(VAR4),.VAR3(VAR3),.VAR1(VAR1),.VAR8(VAR8),.VAR6(VAR6)); | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/cores/axis_bram_reader_v1_0/src/axis_bram_reader.v | 3,294 | module MODULE1 #
(
parameter integer VAR22 = 32,
parameter integer VAR17 = 32,
parameter integer VAR21 = 10,
parameter VAR10 = "VAR12"
)
(
input wire VAR25,
input wire VAR1,
input wire [VAR21-1:0] VAR27,
output wire [VAR21-1:0] VAR26,
input wire VAR13,
output wire [VAR22-1:0] VAR20,
output wire VAR15,
output wire VAR28... | gpl-3.0 |
ehab93/MIPS-Processor | CPU/cpu.v | 3,729 | module MODULE1(input clk,
output [31:0] VAR70, VAR67, VAR16);
reg [31:0] VAR46;
wire [31:0] VAR76, VAR51, VAR20;
wire VAR9, VAR2, VAR13, VAR47, VAR65, VAR36, VAR22;
wire VAR3, VAR78, VAR1, VAR72, VAR62, VAR40;
wire [31:0] VAR66, VAR70, VAR49, VAR54, VAR69, VAR48, VAR15;
wire [3:0] VAR43;
wire [2:0] VAR55;
wire [4:0] VA... | mit |
rkrajnc/minimig-mist | rtl/or1200/or1200_spram_128x32.v | 6,897 | module MODULE1(
VAR14, VAR20, VAR16,
clk, rst, VAR18, VAR12, VAR6, addr, VAR9, VAR11
);
parameter VAR19 = 7;
parameter VAR10 = 32;
input VAR14;
input [VAR7 - 1:0] VAR16;
output VAR20;
input clk; input rst; input VAR18; input VAR12; input VAR6; input [VAR19-1:0] addr; input [VAR10-1:0] VAR9; output [VAR10-1:0] VAR11;
VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or3/sky130_fd_sc_lp__or3.functional.pp.v | 1,801 | module MODULE1 (
VAR14 ,
VAR4 ,
VAR12 ,
VAR9 ,
VAR7,
VAR3,
VAR8 ,
VAR13
);
output VAR14 ;
input VAR4 ;
input VAR12 ;
input VAR9 ;
input VAR7;
input VAR3;
input VAR8 ;
input VAR13 ;
wire VAR2 ;
wire VAR1;
or VAR10 (VAR2 , VAR12, VAR4, VAR9 );
VAR5 VAR11 (VAR1, VAR2, VAR7, VAR3);
buf VAR6 (VAR14 , VAR1 );
endmodule | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_14.v | 12,581 | module MODULE1 (
clk,
reset,
VAR73,
VAR3,
VAR76,
VAR50,
VAR63
);
parameter VAR32 = 18;
parameter VAR29 = 14;
parameter VAR55 = 7;
localparam VAR67 = 19;
input clk;
input reset;
input VAR73;
input VAR3;
input [VAR32-1:0] VAR76; output VAR50;
output [VAR32-1:0] VAR63;
localparam VAR26 = 18; localparam VAR65 = 36; localpa... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/o22a/sky130_fd_sc_hvl__o22a.pp.symbol.v | 1,372 | module MODULE1 (
input VAR8 ,
input VAR6 ,
input VAR9 ,
input VAR3 ,
output VAR2 ,
input VAR7 ,
input VAR4,
input VAR5,
input VAR1
);
endmodule | apache-2.0 |
SymbiFlow/yosys | techlibs/intel_alm/common/megafunction_bb.v | 21,609 | module MODULE3
parameter VAR7 = "0 VAR230",
parameter VAR120 = "false",
parameter VAR204 = "VAR196",
parameter VAR132 = "VAR196",
parameter VAR211 = 1,
parameter VAR170 = "VAR78 VAR234",
parameter VAR34 = 4,
parameter VAR367 = 0,
parameter VAR205 = 0,
parameter VAR91 = "0 VAR230",
parameter VAR197 = "0 VAR230",
paramet... | isc |
antmicro/yosys | techlibs/xilinx/arith_map.v | 4,593 | module MODULE1(
module 80xilinxlcu (VAR43, VAR27, VAR21, VAR34);
parameter VAR16 = 2;
input [VAR16-1:0] VAR43, VAR27;
input VAR21;
output [VAR16-1:0] VAR34;
wire VAR12 = VAR16 <= 2;
genvar VAR23;
generate if (VAR7 == 4) begin
wire [VAR16-1:0] VAR41 = {VAR34, VAR21};
wire [VAR16-1:0] VAR24 = VAR43 & ~VAR27;
generate for... | isc |
theapi/nand2tetris_fpga | hack/rtl/verilog/ps2decoder.v | 1,729 | module MODULE1 (
input reset,
input VAR4,
input VAR1,
output VAR5,
output [7:0] VAR3
);
reg [7:0] VAR2;
reg [3:0] VAR6;
reg ready;
assign VAR3 = VAR2;
assign VAR5 = ready;
always @(negedge VAR4 or posedge reset) begin
if (reset) begin
VAR6 <= 4'b0;
VAR2 <= 8'b0;
end
else begin
case (VAR6)
4'd0: begin
VAR6 <= VAR6 + 1'b... | mit |
AngelTerrones/MUSB | Boards/xilinx_diligent_s3e/rtl/verilog/musoc/musoc.v | 12,817 | module MODULE1#(
parameter VAR80 = "VAR3", parameter VAR20 = 0, parameter VAR30 = 0, parameter VAR42 = 0, parameter VAR83 = 50, parameter VAR115 = 12 )(
input clk,
input rst,
output VAR34,
inout [31:0] VAR45,
input VAR28,
output VAR56
);
wire [31:0] VAR12;
wire [3:0] VAR88;
wire VAR127;
wire VAR60;
wire VAR61;
wire [31... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlclkp/sky130_fd_sc_ls__dlclkp.symbol.v | 1,276 | module MODULE1 (
input VAR3 ,
input VAR4,
output VAR6
);
supply1 VAR2;
supply0 VAR5;
supply1 VAR1 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/ip_compiler_for_pci_express-library/altpcie_pll_phy4_62p5.v | 18,281 | module MODULE1 (
VAR107,
VAR5,
VAR113,
VAR84,
VAR95,
VAR71);
input VAR107;
input VAR5;
output VAR113;
output VAR84;
output VAR95;
output VAR71;
tri0 VAR107;
wire [5:0] VAR76;
wire VAR66;
wire [0:0] VAR57 = 1'h0;
wire [2:2] VAR22 = VAR76[2:2];
wire [1:1] VAR49 = VAR76[1:1];
wire [0:0] VAR50 = VAR76[0:0];
wire VAR113 = V... | mit |
chiralhat/fpga-pulses-ice | HX8K/pulses.v | 7,970 | module MODULE1(
input VAR24, input clk, input [23:0] VAR2, input [15:0] VAR4,
input [15:0] VAR18,
input [15:0] VAR22,
input VAR17,
input VAR25,
input VAR3,
input [7:0] VAR7, output VAR21, output VAR15, output VAR11 );
reg [31:0] counter = 0; reg sync;
reg pulse;
reg VAR14;
reg VAR12 = 0;
reg VAR8 = 0;
parameter VAR26 =... | bsd-3-clause |
anguslin/RISC | HEXDisplay.v | 1,494 | module MODULE1(VAR2, VAR1);
input [3:0] VAR2;
output [6:0] VAR1;
reg [6:0] VAR1;
always @(*) begin
case(VAR2)
4'b0000: VAR1 = 7'b1000000; 4'b0001: VAR1 = 7'b1111001; 4'b0010: VAR1 = 7'b0100100; 4'b0011: VAR1 = 7'b0110000; 4'b0100: VAR1 = 7'b0011001; 4'b0101: VAR1 = 7'b0010010; 4'b0110: VAR1 = 7'b0000010; 4'b0111: VAR1 ... | mit |
jameshegarty/rigel | platform/camera/vsrc/serializer.v | 2,110 | module MODULE1
parameter VAR15 = 3,
localparam VAR16 = 1<<VAR1,
localparam VAR20 = 1<<VAR15)
(
input clk,
input VAR2,
input VAR13,
output reg VAR4,
input [VAR16-1:0] VAR11,
output VAR5,
input VAR3,
output [VAR20-1:0] VAR8
);
localparam VAR19 = VAR1-VAR15 ;
localparam VAR12 = (1<<VAR19)-1;
reg [VAR19-1:0] VAR17;
reg [VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o31ai/sky130_fd_sc_ls__o31ai.behavioral.v | 1,543 | module MODULE1 (
VAR2 ,
VAR5,
VAR1,
VAR8,
VAR12
);
output VAR2 ;
input VAR5;
input VAR1;
input VAR8;
input VAR12;
supply1 VAR3;
supply0 VAR4;
supply1 VAR11 ;
supply0 VAR6 ;
wire VAR10 ;
wire VAR13;
or VAR9 (VAR10 , VAR1, VAR5, VAR8 );
nand VAR14 (VAR13, VAR12, VAR10 );
buf VAR7 (VAR2 , VAR13 );
endmodule | apache-2.0 |
AngelTerrones/Antares | Hardware/verilog/antares_cpzero.v | 32,612 | module MODULE1 (
input clk,
input VAR94, input VAR33, input VAR108, input VAR34, input VAR54, input VAR81, input [4:0] VAR134, input [2:0] select, input [31:0] VAR115, input VAR119, input VAR17, output reg [31:0] VAR73, output VAR14, input [4:0] VAR107, input rst, input VAR48, input VAR136, input VAR30, input VAR89, in... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfsbp/sky130_fd_sc_hd__dfsbp.behavioral.v | 2,273 | module MODULE1 (
VAR5 ,
VAR18 ,
VAR15 ,
VAR1 ,
VAR21
);
output VAR5 ;
output VAR18 ;
input VAR15 ;
input VAR1 ;
input VAR21;
supply1 VAR8;
supply0 VAR13;
supply1 VAR16 ;
supply0 VAR4 ;
wire VAR3 ;
wire VAR17 ;
reg VAR11 ;
wire VAR6 ;
wire VAR14;
wire VAR20 ;
wire VAR22 ;
wire VAR2 ;
wire VAR12 ;
not VAR9 (VAR17 , VAR14... | apache-2.0 |
eda-globetrotter/MarcheProcessor | final/src/control.v | 6,056 | module MODULE1(VAR11,
VAR12, VAR17,
VAR34, VAR28, VAR6, VAR14,
VAR32, VAR9, VAR16, VAR31,
VAR24,
VAR23,
VAR25);
input [0:31] VAR11;
output [0:4] VAR12, VAR9, VAR16, VAR31;
output [0:2] VAR32;
output [0:1] VAR17;
output [0:20] VAR6;
output VAR34, VAR28;
output VAR24, VAR23;
output [0:15] VAR14;
output [0:127] VAR25;
reg... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_misc/rtl/bw_io_misc_rpt.v | 1,909 | module MODULE1(VAR12 ,VAR4 ,VAR5 ,VAR1 ,VAR15 ,VAR24 ,VAR19 ,VAR20 ,VAR23
,VAR14 ,VAR11 ,VAR3 ,VAR6 ,VAR8 );
output VAR4 ;
output VAR5 ;
output VAR1 ;
output VAR15 ;
output VAR24 ;
output VAR19 ;
output VAR8 ;
input VAR12 ;
input VAR20 ;
input VAR23 ;
input VAR14 ;
input VAR11 ;
input VAR3 ;
input VAR6 ;
VAR2 VAR18 (
.... | gpl-2.0 |
lfmunoz/vhdl | ip_blocks/axi_to_stellarip/vivado_prj/vivado_prj.srcs/sources_1/ip/axi_traffic_gen_0/axi_traffic_gen_v2_0/hdl/src/verilog/axi_traffic_gen_v2_0_cmdram.v | 7,277 | module MODULE1 #(
parameter VAR20 = "VAR3",
parameter VAR44 = "VAR31",
parameter VAR16 = "VAR31",
parameter VAR37 = "VAR31",
parameter VAR6 = "VAR31"
) (
input reset ,
input VAR51 ,
input VAR49 ,
input [15:0 ] VAR36 ,
input [15:0 ] VAR45 ,
input [15:0 ] VAR11 ,
input [127:0] VAR50 ,
output [127:0] VAR1 ,
input VAR35 ,
... | mit |
lvd2/ngs | fpga/current/common/mem512b.v | 1,333 | module MODULE1
(
input wire clk,
input wire VAR5,
input wire [8:0] VAR3,
output reg [7:0] VAR4,
input wire VAR1,
input wire [8:0] VAR6,
input wire [7:0] VAR2
);
reg [7:0] VAR7[0:511];
always @(posedge clk)
if( VAR5 )
VAR4 <= VAR7[VAR3];
always @(posedge clk)
if( VAR1 )
VAR7[VAR6] <= VAR2;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21o/sky130_fd_sc_hdll__a21o.functional.pp.v | 2,014 | module MODULE1 (
VAR15 ,
VAR1 ,
VAR14 ,
VAR8 ,
VAR16,
VAR4,
VAR13 ,
VAR11
);
output VAR15 ;
input VAR1 ;
input VAR14 ;
input VAR8 ;
input VAR16;
input VAR4;
input VAR13 ;
input VAR11 ;
wire VAR5 ;
wire VAR6 ;
wire VAR12;
and VAR10 (VAR5 , VAR1, VAR14 );
or VAR3 (VAR6 , VAR5, VAR8 );
VAR7 VAR9 (VAR12, VAR6, VAR16, VAR4)... | apache-2.0 |
fzyz999/5-stage-MIPS | datapath/alu.v | 1,256 | module MODULE2(
input signed [31:0] VAR6,
input [4:0] VAR15,
input VAR12,
output [31:0] out
);
assign out = (VAR12)? (VAR6>>VAR15):
(VAR6>>>VAR15);
endmodule
module MODULE1 (VAR9,VAR2,VAR7,VAR13,VAR20);
input [31:0] VAR9,VAR2;
input [3:0] VAR7;
output [31:0] VAR13;
output VAR20;
wire [31:0] VAR19,VAR11;
wire [31:0] VAR... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_2.functional.pp.v | 1,804 | module MODULE1( VAR18, VAR15, VAR14, VAR10, VAR2, VAR7, VAR23 );
input VAR2, VAR10, VAR15, VAR18;
inout VAR7, VAR23;
output VAR14;
wire VAR1;
not VAR9( VAR1, VAR2 );
wire VAR19;
not VAR5( VAR19, VAR15 );
wire VAR22;
and VAR3( VAR22, VAR1, VAR19 );
wire VAR13;
not VAR20( VAR13, VAR18 );
wire VAR17;
and VAR21( VAR17, VAR... | apache-2.0 |
m-labs/milkymist | cores/softusb/rtl/softusb_phy.v | 3,218 | module MODULE1(
input VAR35,
input VAR26,
output VAR29,
output VAR37,
input VAR46,
inout VAR36,
inout VAR34,
output VAR52,
output VAR5,
input VAR20,
inout VAR39,
inout VAR30,
output [1:0] VAR28,
output [1:0] VAR55,
input VAR10,
input [1:0] VAR2,
input [7:0] VAR51,
input VAR47,
output VAR14,
output reg VAR56,
input [1:0... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/fill/sky130_fd_sc_hdll__fill_4.v | 1,856 | module MODULE2 (
VAR1,
VAR6,
VAR3 ,
VAR4
);
input VAR1;
input VAR6;
input VAR3 ;
input VAR4 ;
VAR2 VAR5 (
.VAR1(VAR1),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR4(VAR4)
);
endmodule
module MODULE2 ();
supply1 VAR1;
supply0 VAR6;
supply1 VAR3 ;
supply0 VAR4 ;
VAR2 VAR5 ();
endmodule | apache-2.0 |
sergev/vak-opensource | hardware/vga512x256/rom8kx16.v | 1,811 | module MODULE1 (
input [12 : 0] addr,
input clk,
output [15 : 0] dout);
VAR7 #(.VAR19 (2'b00), .VAR18 (2'b00), .VAR6 ("VAR16"),
) VAR11 (.VAR8 (dout[1:0]), .VAR10 (addr), .VAR15 (clk),
.VAR1 (0), .VAR9 (1), .VAR20 (0), .VAR4 (0));
VAR7 #(.VAR19 (2'b00), .VAR18 (2'b00), .VAR6 ("VAR16"),
) VAR12 (.VAR8 (dout[3:2]), .VAR1... | apache-2.0 |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_INVBUF_SLVT_FF_210930.v | 14,942 | module MODULE1 (VAR2, VAR1);
output VAR2;
input VAR1;
buf (VAR2, VAR1); | bsd-3-clause |
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