repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
MarcoVogt/basil | firmware/modules/tlu/tlu_controller.v | 3,173 | module MODULE1
parameter VAR36 = 16'h0000,
parameter VAR26 = 16'h0000,
parameter VAR15 = 16,
parameter VAR11 = 8,
parameter VAR32 = 8,
parameter VAR22 = 17,
parameter VAR24 = 32
)
(
input wire VAR38,
input wire VAR16,
input wire [VAR15-1:0] VAR27,
inout wire [7:0] VAR13,
input wire VAR33,
input wire VAR3,
input wire VA... | bsd-3-clause |
kyzhai/NUNY | src/hardware/lab3/synthesis/submodules/lab3_master_0_p2b_adapter.v | 1,328 | module MODULE1 (
input clk,
input VAR4,
output reg VAR5,
input VAR1,
input [ 7: 0] VAR3,
input VAR2,
input VAR12,
input VAR10,
output reg VAR8,
output reg [ 7: 0] VAR9,
output reg VAR11,
output reg VAR7,
output reg [ 7: 0] VAR6
);
reg VAR13 = 0;
always @* begin
VAR5 = VAR10;
VAR8 = VAR1;
VAR9 = VAR3;
VAR11 = VAR2;
VAR7... | gpl-2.0 |
cpulabs/mist1032isa | src/primitive/altera/ram_256bit_16word/ram_256bit_16word.v | 9,570 | module MODULE1 (
VAR30,
VAR19,
VAR43,
VAR57,
VAR16,
VAR3,
VAR37);
input [31:0] VAR30;
input VAR19;
input [255:0] VAR43;
input [3:0] VAR57;
input [3:0] VAR16;
input VAR3;
output [255:0] VAR37;
tri1 [31:0] VAR30;
tri1 VAR19;
tri0 VAR3;
wire [255:0] VAR11;
wire [255:0] VAR37 = VAR11[255:0];
VAR38 VAR34 (
.VAR5 (VAR16),
.V... | bsd-2-clause |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/ecc/mig_7series_v2_0_ecc_gen.v | 7,915 | module MODULE1
parameter VAR18 = 72,
parameter VAR21 = 8,
parameter VAR7 = 64
)
(
VAR20
);
function integer VAR10 (input integer VAR9);
integer VAR4;
if (VAR9 == 1) VAR10 = 1;
else begin
VAR10 = 1;
for (VAR4=2; VAR4<=VAR9; VAR4=VAR4+1)
VAR10 = VAR10 * VAR4;
end
endfunction
function integer VAR14 (input integer VAR6, VA... | bsd-2-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.behavioral.v | 1,113 | module MODULE1( VAR5, VAR3 );
input VAR5;
output VAR3;
VAR1 VAR4(.VAR5(VAR5),.VAR3(VAR3));
VAR1 VAR2(.VAR5(VAR5),.VAR3(VAR3)); | apache-2.0 |
sabertazimi/hust-lab | architecture/design/fpga/src/IF_ID.v | 1,212 | module MODULE1
(
input clk,
input rst,
input en,
input [VAR3-1:0] VAR10,
input [VAR3-1:0] VAR9,
input VAR5,
output [VAR3-1:0] VAR4,
output [VAR3-1:0] VAR6,
output VAR7
);
wire VAR8 = rst && en;
register #(
.VAR3(VAR3)
) VAR1 (
.clk(clk),
.rst(VAR8),
.en(en),
.din(VAR10),
.dout(VAR4)
);
register #(
.VAR3(VAR3)
) VAR11 (... | mit |
deepakcu/maestro | fpga/DE4_Ethernet_0/float_mega/float_mult/float_mult.v | 25,512 | module MODULE1
(
VAR48,
VAR23,
VAR32,
VAR59,
VAR15) ;
input VAR48;
input [31:0] VAR23;
input [31:0] VAR32;
output VAR59;
output [31:0] VAR15;
reg VAR16;
reg VAR37;
reg VAR60;
reg VAR53;
reg VAR40;
reg VAR12;
reg VAR55;
reg VAR1;
reg [9:0] VAR22;
reg [9:0] VAR61;
reg VAR62;
reg VAR43;
reg [8:0] VAR35;
reg [7:0] VAR49;
r... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s.functional.v | 1,754 | module MODULE1 (
VAR5,
VAR2,
VAR10 ,
VAR9
);
input VAR5;
input VAR2;
output VAR10 ;
input VAR9 ;
wire VAR4 ;
wire VAR1;
buf VAR8 (VAR4 , VAR9 );
VAR6 VAR7 (VAR1, VAR4, VAR5, VAR2);
buf VAR3 (VAR10 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor4/sky130_fd_sc_hs__nor4_1.v | 2,148 | module MODULE2 (
VAR7 ,
VAR1 ,
VAR5 ,
VAR9 ,
VAR2 ,
VAR3,
VAR6
);
output VAR7 ;
input VAR1 ;
input VAR5 ;
input VAR9 ;
input VAR2 ;
input VAR3;
input VAR6;
VAR4 VAR8 (
.VAR7(VAR7),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR7,
VAR1,
VAR5,
VAR9,
VAR2
);
... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_sbox.v | 6,458 | module MODULE1
, parameter VAR3(VAR5 )
, parameter VAR24 = 0
, parameter VAR42 = 0
, parameter VAR27 = 1
)
(input VAR45
, input VAR59
, input VAR10
, input [VAR29-1:0] VAR64
, input [VAR29-1:0 ] VAR56
, input [VAR5-1:0] VAR37 [VAR29-1:0]
, output [VAR29-1:0 ] VAR22
, output [VAR29-1:0 ] VAR36
, output [VAR5-1:0] VAR6 [... | bsd-3-clause |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/hashing_clock_multiplier/hashing_clock_multiplier.v | 4,159 | module MODULE1
( input VAR6,
input VAR5,
output VAR4,
output VAR2
);
VAR1 VAR3
( .VAR6(VAR6),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o211ai/sky130_fd_sc_hd__o211ai.pp.blackbox.v | 1,397 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR4 ,
VAR9 ,
VAR8 ,
VAR6,
VAR7,
VAR2 ,
VAR3
);
output VAR1 ;
input VAR5 ;
input VAR4 ;
input VAR9 ;
input VAR8 ;
input VAR6;
input VAR7;
input VAR2 ;
input VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv3sd1/sky130_fd_sc_ls__clkdlyinv3sd1.behavioral.pp.v | 1,867 | module MODULE1 (
VAR8 ,
VAR3 ,
VAR5,
VAR4,
VAR10 ,
VAR6
);
output VAR8 ;
input VAR3 ;
input VAR5;
input VAR4;
input VAR10 ;
input VAR6 ;
wire VAR1 ;
wire VAR12;
not VAR11 (VAR1 , VAR3 );
VAR7 VAR2 (VAR12, VAR1, VAR5, VAR4);
buf VAR9 (VAR8 , VAR12 );
endmodule | apache-2.0 |
FelixWinterstein/LEAP-HLS | filtering_algorithm/wrappers/verilog/filtering_algorithm_top_wrapper.v | 46,110 | module MODULE1 (
input VAR472,
input VAR381,
input VAR260,
output VAR261,
output VAR382,
output VAR334,
input [399:0] VAR360,
input VAR98,
output VAR369,
output VAR187,
output [511:0] VAR115,
output [31:0] VAR193,
input VAR423,
output VAR376,
output [31:0] VAR22,
input VAR303,
input [511:0] VAR287,
output VAR479,
outpu... | bsd-3-clause |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_aw_channel.v | 3,891 | module MODULE1 #
(
parameter integer VAR18 = 4,
parameter integer VAR26 = 32
)
(
input wire clk ,
input wire reset ,
input wire [VAR18-1:0] VAR2 ,
input wire [VAR26-1:0] VAR7 ,
input wire [7:0] VAR6 ,
input wire [2:0] VAR25 ,
input wire [1:0] VAR28 ,
input wire VAR10 ,
output wire VAR17 ,
output wire VAR3 ,
output wire... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_dff_en.v | 4,897 | if (VAR5 && VAR12==VAR11 && (VAR6==VAR10)) \
begin: VAR2 \
VAR7 VAR9(.VAR3(VAR4) \
,.VAR19({ VAR12 { VAR16 } }) \
,.VAR1({ VAR12 {VAR18} }) \
,.VAR14(VAR17) \
); \
end
module MODULE1 #(VAR12="VAR8"
, VAR5=1
, VAR6=1
)
(input VAR18
,input [VAR12-1:0] VAR4
,input VAR16
,output [VAR12-1:0] VAR17
);
begin : VAR13
reg [VAR1... | bsd-3-clause |
kyzhai/NUNY | src/hardware/stage1.v | 6,372 | module MODULE1 (
address,
VAR46,
VAR12);
input [11:0] address;
input VAR46;
output [11:0] VAR12;
tri1 VAR46;
wire [11:0] VAR14;
wire [11:0] VAR12 = VAR14[11:0];
VAR9 VAR48 (
.VAR20 (address),
.VAR4 (VAR46),
.VAR24 (VAR14),
.VAR17 (1'b0),
.VAR3 (1'b0),
.VAR21 (1'b1),
.VAR25 (1'b0),
.VAR19 (1'b0),
.VAR43 (1'b1),
.VAR7 (1... | gpl-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/up_dac_channel.v | 10,908 | module MODULE1 (
VAR49,
VAR14,
VAR13,
VAR5,
VAR43,
VAR29,
VAR31,
VAR8,
VAR27,
VAR15,
VAR35,
VAR46,
VAR24,
VAR33,
VAR1,
VAR4,
VAR30,
VAR7,
VAR47,
VAR2,
VAR38,
VAR10,
VAR52,
VAR26,
VAR42,
VAR12,
VAR40,
VAR22,
VAR19,
VAR36,
VAR50,
VAR32,
VAR20,
VAR37);
parameter VAR45 = 4'h0;
input VAR49;
input VAR14;
output [ 3:0] VAR13;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlrtn/sky130_fd_sc_hs__dlrtn.symbol.v | 1,380 | module MODULE1 (
input VAR4 ,
output VAR6 ,
input VAR5,
input VAR2
);
supply1 VAR3;
supply0 VAR1;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkbuf/sky130_fd_sc_lp__clkbuf_1.v | 2,034 | module MODULE2 (
VAR5 ,
VAR6 ,
VAR7,
VAR3,
VAR8 ,
VAR2
);
output VAR5 ;
input VAR6 ;
input VAR7;
input VAR3;
input VAR8 ;
input VAR2 ;
VAR1 VAR4 (
.VAR5(VAR5),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR5,
VAR6
);
output VAR5;
input VAR6;
supply1 VAR7;
supply0 VAR3;... | apache-2.0 |
hakehuang/pycpld | ips/ip/uart8bit/my_uart_rx8to8.v | 3,776 | module MODULE1(
clk,
VAR1,
VAR3,
VAR12,
VAR14,
VAR2
);
input clk;
input VAR1;
input [2:0] VAR3;
input VAR12;
output [7:0] VAR14;
output VAR2;
parameter VAR16 = 13'd2604,
VAR5 = 13'd1301,
VAR8 = 13'd650,
VAR13 = 13'd433,
VAR17 = 13'd217,
VAR4 = 13'd97;
parameter VAR15 = 2'b01,
VAR11 = 2'b10;
reg [1:0] state;
reg VAR9, V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor4bb/sky130_fd_sc_hs__nor4bb.blackbox.v | 1,296 | module MODULE1 (
VAR5 ,
VAR7 ,
VAR4 ,
VAR2,
VAR6
);
output VAR5 ;
input VAR7 ;
input VAR4 ;
input VAR2;
input VAR6;
supply1 VAR3;
supply0 VAR1;
endmodule | apache-2.0 |
andrewandrepowell/kernel-on-chip | hdl/projects/Nexys4/bd/ip/bd_mig_7series_0_0/bd_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_0_ddr_carry_latch_or.v | 4,250 | module MODULE1 #
(
parameter VAR2 = "VAR7"
)
(
input wire VAR8,
input wire VAR6,
output wire VAR10
);
generate
if ( VAR2 == "VAR5" ) begin : VAR1
assign VAR10 = VAR8 | VAR6;
end else begin : VAR3
VAR12 VAR9
(
.VAR10(VAR10),
.VAR11(VAR8),
.VAR4(VAR6)
);
end
endgenerate
endmodule | mit |
sh-chris110/chris | FPGA/Math/Qsys/nios_design/synthesis/submodules/nios_design_nios2_gen2_0.v | 6,229 | module MODULE1 (
input wire clk, input wire VAR28, input wire VAR27, output wire [18:0] VAR23, output wire [3:0] VAR26, output wire VAR22, input wire [31:0] VAR5, input wire VAR19, output wire VAR2, output wire [31:0] VAR3, input wire VAR25, output wire VAR18, output wire [18:0] VAR16, output wire VAR11, input wire [31... | gpl-2.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_light/spw_light/synthesis/submodules/spw_light_hps_0.v | 7,255 | module MODULE1 #(
parameter VAR24 = 0,
parameter VAR2 = 1
) (
output wire VAR27, input wire VAR31, output wire [11:0] VAR25, output wire [29:0] VAR53, output wire [3:0] VAR38, output wire [2:0] VAR15, output wire [1:0] VAR35, output wire [1:0] VAR49, output wire [3:0] VAR3, output wire [2:0] VAR26, output wire VAR29, i... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busdriver/sky130_fd_sc_lp__busdriver.behavioral.v | 1,327 | module MODULE1 (
VAR3 ,
VAR6 ,
VAR7
);
output VAR3 ;
input VAR6 ;
input VAR7;
supply1 VAR8;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR5 ;
bufif0 VAR1 (VAR3 , VAR6, VAR7 );
endmodule | apache-2.0 |
ipburbank/Raster-Laser-Projector | src/Video_In/synthesis/submodules/Raster_Laser_Projector_Video_In_video_rgb_resampler_0.v | 5,750 | module MODULE1 (
clk,
reset,
VAR13,
VAR6,
VAR10,
VAR22,
VAR3,
VAR7,
VAR4,
VAR14,
VAR15,
VAR11,
VAR20,
VAR2
);
parameter VAR23 = 23;
parameter VAR17 = 7;
parameter VAR12 = 1;
parameter VAR19 = 0;
parameter VAR9 = 10'h3FF;
input clk;
input reset;
input [VAR23:0] VAR13;
input VAR6;
input VAR10;
input [VAR12:0] VAR22;
inpu... | gpl-3.0 |
chipsalliance/yosys-f4pga-plugins | ql-qlf-plugin/qlf_k6n10f/TDP18K_FIFO.v | 10,338 | module MODULE1 (
VAR18,
VAR4,
VAR48,
VAR19,
VAR57,
VAR67,
VAR5,
VAR60,
VAR38,
VAR72,
VAR52,
VAR16,
VAR56,
VAR22,
VAR29,
VAR58,
VAR34,
VAR70,
VAR44,
VAR69,
VAR39,
VAR27,
VAR2,
VAR30,
VAR53,
VAR33,
VAR43,
VAR20,
);
parameter VAR9 = 1'b0;
parameter VAR46 = 1'b0;
parameter VAR50 = 1'b0;
parameter VAR35 = 1'b0;
parameter VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o2bb2a/sky130_fd_sc_ms__o2bb2a.pp.blackbox.v | 1,400 | module MODULE1 (
VAR9 ,
VAR4,
VAR7,
VAR3 ,
VAR6 ,
VAR8,
VAR2,
VAR5 ,
VAR1
);
output VAR9 ;
input VAR4;
input VAR7;
input VAR3 ;
input VAR6 ;
input VAR8;
input VAR2;
input VAR5 ;
input VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlrtn/sky130_fd_sc_ms__dlrtn.functional.v | 1,806 | module MODULE1 (
VAR2 ,
VAR13,
VAR9 ,
VAR3
);
output VAR2 ;
input VAR13;
input VAR9 ;
input VAR3 ;
wire VAR10 ;
wire VAR8;
wire VAR1 ;
not VAR6 (VAR10 , VAR13 );
not VAR4 (VAR8, VAR3 );
VAR5 VAR11 VAR7 (VAR1 , VAR9, VAR8, VAR10);
buf VAR12 (VAR2 , VAR1 );
endmodule | apache-2.0 |
fabianz66/cursos-tec | taller-digital/Proyecto Final/CON SOLO NCO/tec-drums/sound_selector.v | 1,359 | module MODULE1(
input VAR8,
input VAR3,
input reset,
input[1:0] VAR1,
output reg [15:0] VAR6,
output reg [15:0] VAR5
);
reg [3:0] VAR2;
wire [3:0] VAR4;
wire [31:0] VAR7;
begin
begin
begin
end
begin
begin
begin
end
begin | mit |
jayant-sharma/uart | hdl/TOP_UART_ADC.v | 4,352 | module MODULE1(
input VAR27,
input VAR34,
input VAR7,
input VAR4,
inout VAR6,
inout VAR19
);
wire VAR21;
wire VAR29;
wire [VAR3-1:0] VAR2;
wire [VAR33-1:0] VAR15;
wire [VAR33-1:0] VAR35;
wire [VAR24-1:0] VAR28;
wire [VAR33-1:0] VAR9;
wire VAR8, VAR25;
wire VAR13, VAR1, VAR12, VAR18, VAR26;
wire [4:0] VAR32;
wire [6:0] ... | unlicense |
Cognoscan/BoostDSP | verilog/src/signalGen/sineTable.v | 1,995 | module MODULE1 #(
parameter VAR5 = 12,
parameter VAR4 = 18
) (
input wire clk, input wire [VAR5-1:0] VAR3, output reg signed [VAR4-1:0] VAR7 );
localparam VAR6 = 2**(VAR5-2);
wire [VAR5-3:0] VAR9;
reg [VAR4-2:0] MODULE1 [VAR6-1:0];
reg VAR8;
reg [VAR4-2:0] VAR2;
integer VAR1;
assign VAR9 = (VAR3[VAR5-2]) ? ~VAR3[VAR5-3... | apache-2.0 |
mammenx/synesthesia_moksha | wxp/dgn/rtl/altera/win_ram.v | 9,450 | module MODULE1 (
VAR16,
VAR23,
VAR39,
VAR46,
VAR58,
VAR30);
input VAR16;
input [31:0] VAR23;
input [6:0] VAR39;
input [6:0] VAR46;
input VAR58;
output [31:0] VAR30;
tri1 VAR16;
tri0 VAR58;
wire [31:0] VAR49;
wire [31:0] VAR30 = VAR49[31:0];
VAR66 VAR65 (
.VAR10 (VAR46),
.VAR52 (VAR16),
.VAR32 (VAR23),
.VAR12 (VAR58),
.... | gpl-3.0 |
asicguy/gplgpu | hdl/vga/clk_sel.v | 5,841 | module MODULE1
(
input VAR23,
input VAR14,
input VAR2,
input VAR10, input VAR21,
input VAR17, input VAR5,
output VAR3, output reg VAR8, output reg VAR4, output reg VAR12 );
reg [1:0] VAR7;
reg VAR13; reg [3:0] VAR1;
reg VAR11;
reg VAR18; reg VAR20; reg VAR19;
wire VAR22; wire VAR6 = VAR2;
wire VAR15;
wire VAR9;
wire [1... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/and4/gf180mcu_fd_sc_mcu9t5v0__and4_2.behavioral.v | 1,322 | module MODULE1( VAR6, VAR5, VAR2, VAR1, VAR4 );
input VAR6, VAR5, VAR2, VAR1;
output VAR4;
VAR3 VAR8(.VAR6(VAR6),.VAR5(VAR5),.VAR2(VAR2),.VAR1(VAR1),.VAR4(VAR4));
VAR3 VAR7(.VAR6(VAR6),.VAR5(VAR5),.VAR2(VAR2),.VAR1(VAR1),.VAR4(VAR4)); | apache-2.0 |
alexforencich/xfcp | lib/eth/rtl/axis_baser_tx_64.v | 29,486 | module MODULE1 #
(
parameter VAR15 = 64,
parameter VAR18 = (VAR15/8),
parameter VAR9 = 2,
parameter VAR21 = 1,
parameter VAR13 = 1,
parameter VAR12 = 64,
parameter VAR28 = 4'h6,
parameter VAR14 = 16'h6666,
parameter VAR1 = 0,
parameter VAR20 = 96,
parameter VAR3 = VAR1,
parameter VAR16 = 16,
parameter VAR24 = (VAR3 ? V... | mit |
intelligenttoasters/CPC2.0 | FPGA/Quartus/DE10/HPS/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v | 11,404 | module MODULE1(
VAR16,
VAR124,
VAR33,
VAR136,
VAR99,
VAR41,
VAR127,
VAR118,
VAR26,
VAR95,
VAR90,
VAR29,
VAR6,
VAR143,
VAR93,
VAR19,
VAR113,
VAR57,
VAR71,
VAR134,
VAR70,
VAR109,
VAR133,
VAR80,
VAR139,
VAR148,
VAR12,
VAR66,
VAR102,
VAR101,
VAR147,
VAR98,
VAR119,
VAR32,
VAR106,
VAR75,
VAR105,
VAR72,
VAR56,
VAR37,
VAR68,
V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and4b/sky130_fd_sc_ms__and4b_1.v | 2,300 | module MODULE2 (
VAR4 ,
VAR1 ,
VAR5 ,
VAR2 ,
VAR10 ,
VAR11,
VAR3,
VAR9 ,
VAR8
);
output VAR4 ;
input VAR1 ;
input VAR5 ;
input VAR2 ;
input VAR10 ;
input VAR11;
input VAR3;
input VAR9 ;
input VAR8 ;
VAR7 VAR6 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR9(VAR9),
.... | apache-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/system/synthesis/system.v | 41,841 | module MODULE1 (
input wire VAR93, input wire VAR64, output wire VAR231, output wire [14:0] VAR161, output wire [2:0] VAR19, output wire VAR166, output wire VAR120, output wire VAR31, output wire VAR113, output wire VAR4, output wire VAR61, output wire VAR57, output wire VAR138, inout wire [31:0] VAR131, inout wire [3:... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_1.behavioral.v | 1,093 | module MODULE1( VAR3, VAR4 );
input VAR3;
output VAR4;
VAR1 VAR5(.VAR3(VAR3),.VAR4(VAR4));
VAR1 VAR2(.VAR3(VAR3),.VAR4(VAR4)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/buf/sky130_fd_sc_ls__buf.symbol.v | 1,236 | module MODULE1 (
input VAR2,
output VAR6
);
supply1 VAR1;
supply0 VAR5;
supply1 VAR4 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
cr88192/bgbtech_bjx1core | bjx1c32b/DecOp4.v | 43,549 | module MODULE1(
clk,
VAR196,
VAR37,
VAR241,
VAR343,
VAR198,
VAR127,
VAR243,
VAR76,
VAR1
);
parameter VAR96 = 0; parameter VAR180 = 0; parameter VAR326 = 1;
input clk; input[47:0] VAR196; input[15:0] VAR37;
output[6:0] VAR241;
output[6:0] VAR343;
output[6:0] VAR198;
output[31:0] VAR127;
output[3:0] VAR243;
output[3:0] V... | mit |
FAST-Switch/fast | lib/hardware/pipeline/IPE_PPS_OPENFLOW/INGRESS/INGRESS.v | 2,251 | module MODULE1(
input clk,
input reset,
input VAR30,
input [133:0] VAR18,
input VAR21,
input VAR5,
output VAR22,
output VAR1,
output [133:0] VAR2,
input VAR23,
output VAR3,
output VAR6,
input VAR31,
input [133:0] VAR32,
input VAR12,
input VAR10,
output VAR16,
output VAR13,
output [133:0] VAR14,
output VAR27,
output VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfxbp/sky130_fd_sc_ls__sdfxbp_1.v | 2,443 | module MODULE2 (
VAR4 ,
VAR9 ,
VAR5 ,
VAR6 ,
VAR11 ,
VAR10 ,
VAR2,
VAR12,
VAR8 ,
VAR7
);
output VAR4 ;
output VAR9 ;
input VAR5 ;
input VAR6 ;
input VAR11 ;
input VAR10 ;
input VAR2;
input VAR12;
input VAR8 ;
input VAR7 ;
VAR1 VAR3 (
.VAR4(VAR4),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR10(VAR10),
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfbbn/sky130_fd_sc_lp__dfbbn.symbol.v | 1,485 | module MODULE1 (
input VAR7 ,
output VAR5 ,
output VAR4 ,
input VAR8,
input VAR3 ,
input VAR1
);
supply1 VAR6;
supply0 VAR2;
supply1 VAR9 ;
supply0 VAR10 ;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/example_design/rtl/controller/rank_common.v | 15,104 | module MODULE1 #
(
parameter VAR44 = 100,
parameter VAR12 = "VAR39",
parameter VAR76 = 40,
parameter VAR6 = 4,
parameter VAR75 = 2,
parameter VAR66 = 4,
parameter VAR79 = 39,
parameter VAR26 = 640000
)
(
VAR16, VAR72, VAR52, VAR46,
VAR81, VAR70, VAR53,
VAR69,
clk, rst, VAR77, VAR63, VAR31,
VAR67, VAR78, VAR40, VAR20,
V... | lgpl-3.0 |
cafe-alpha/wasca | v12/fpga_firmware/wasca/synthesis/submodules/altera_up_rs232_out_serializer.v | 6,267 | module MODULE1 (
clk,
reset,
VAR27,
VAR24,
VAR20,
VAR22
);
parameter VAR19 = 9; parameter VAR13 = 433;
parameter VAR17 = 216;
parameter VAR15 = 11; parameter VAR8 = 9;
input clk;
input reset;
input [VAR8: 0] VAR27;
input VAR24;
output reg [ 7: 0] VAR20;
output reg VAR22;
wire VAR9;
wire VAR21;
wire VAR23;
wire VAR16;
w... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a211o/sky130_fd_sc_hs__a211o.behavioral.v | 1,926 | module MODULE1 (
VAR8 ,
VAR6 ,
VAR2 ,
VAR15 ,
VAR9 ,
VAR11,
VAR13
);
output VAR8 ;
input VAR6 ;
input VAR2 ;
input VAR15 ;
input VAR9 ;
input VAR11;
input VAR13;
wire VAR9 VAR4 ;
wire VAR3 ;
wire VAR10;
and VAR14 (VAR4 , VAR6, VAR2 );
or VAR12 (VAR3 , VAR4, VAR9, VAR15 );
VAR1 VAR7 (VAR10, VAR3, VAR11, VAR13);
buf VAR5... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfbbn/sky130_fd_sc_ls__sdfbbn.behavioral.v | 3,407 | module MODULE1 (
VAR19 ,
VAR5 ,
VAR8 ,
VAR30 ,
VAR6 ,
VAR23 ,
VAR24 ,
VAR18
);
output VAR19 ;
output VAR5 ;
input VAR8 ;
input VAR30 ;
input VAR6 ;
input VAR23 ;
input VAR24 ;
input VAR18;
supply1 VAR33;
supply0 VAR38;
supply1 VAR16 ;
supply0 VAR11 ;
wire VAR3 ;
wire VAR2 ;
wire VAR17 ;
wire VAR29 ;
reg VAR26 ;
wire VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor4bb/sky130_fd_sc_hd__nor4bb_2.v | 2,325 | module MODULE2 (
VAR7 ,
VAR3 ,
VAR4 ,
VAR10 ,
VAR2 ,
VAR6,
VAR9,
VAR5 ,
VAR8
);
output VAR7 ;
input VAR3 ;
input VAR4 ;
input VAR10 ;
input VAR2 ;
input VAR6;
input VAR9;
input VAR5 ;
input VAR8 ;
VAR11 VAR1 (
.VAR7(VAR7),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR... | apache-2.0 |
dries007/Basys3 | VGA_text/VGA_text.srcs/sources_1/ip/FrameBuffer/FrameBuffer_stub.v | 1,492 | module MODULE1(VAR6, VAR4, VAR2, VAR11, VAR3, VAR1, VAR9, VAR8, VAR5, VAR7, VAR10)
;
input VAR6;
input VAR4;
input [0:0]VAR2;
input [13:0]VAR11;
input [7:0]VAR3;
output [7:0]VAR1;
input VAR9;
input [0:0]VAR8;
input [13:0]VAR5;
input [7:0]VAR7;
output [7:0]VAR10;
endmodule | mit |
alexforencich/verilog-axis | rtl/axis_fifo_adapter.v | 12,101 | module MODULE1 #
(
parameter VAR3 = 4096,
parameter VAR45 = 8,
parameter VAR44 = (VAR45>8),
parameter VAR12 = ((VAR45+7)/8),
parameter VAR23 = 8,
parameter VAR21 = (VAR23>8),
parameter VAR41 = ((VAR23+7)/8),
parameter VAR18 = 0,
parameter VAR30 = 8,
parameter VAR32 = 0,
parameter VAR22 = 8,
parameter VAR2 = 1,
paramete... | mit |
hanw/Open-Source-FPGA-Bitcoin-Miner | projects/X5000_ztexmerge/hdl/main_pll.v | 5,684 | module MODULE1
( input VAR1,
output VAR24
);
VAR8 VAR38
(.VAR11 (VAR12),
.VAR28 (VAR1));
wire VAR36;
wire VAR17;
wire [7:0] VAR20;
wire VAR37;
wire VAR21;
wire VAR41;
VAR14
.VAR19 (10),
.VAR29 (10),
.VAR46 ("VAR45"),
.VAR44 (10.0),
.VAR42 ("VAR35"),
.VAR4 ("VAR35"),
.VAR48 ("VAR31"),
.VAR10 (0),
.VAR30 ("VAR45"))
VAR15... | gpl-3.0 |
sorgelig/Apogee_MIST | scandoubler.v | 2,845 | module MODULE1
(
input VAR5,
input VAR21,
input VAR13,
input VAR23,
input [5:0] VAR10,
input [5:0] VAR27,
input [5:0] VAR9,
output reg VAR20,
output VAR12,
output reg [5:0] VAR11,
output reg [5:0] VAR19,
output reg [5:0] VAR2
);
assign VAR12 = VAR23;
reg VAR8, VAR4;
always @(negedge VAR5) begin
reg VAR28;
reg [7:0] VAR... | bsd-2-clause |
juan199/Lab_Digitales | exp3/adder.v | 1,387 | module MODULE1(
input wire VAR17,
input wire VAR2,
input wire VAR18,
output reg VAR11,
output reg VAR14
);
always @ (*)
{VAR14, VAR11} = VAR17 + VAR2 + VAR18;
endmodule
module MODULE2(
input wire [3:0] VAR6,
input wire [3:0] VAR12,
output wire [7:0] VAR1
);
wire VAR17 [11:0];
wire VAR2 [11:0];
wire VAR3 [11:0];
wire VA... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi.pp.symbol.v | 1,457 | module MODULE1 (
input VAR3,
input VAR2,
input VAR4 ,
input VAR9 ,
output VAR6 ,
input VAR7 ,
input VAR8,
input VAR5,
input VAR1
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/mux4/sky130_fd_sc_hvl__mux4.pp.blackbox.v | 1,380 | module MODULE1 (
VAR6 ,
VAR8 ,
VAR2 ,
VAR5 ,
VAR4 ,
VAR10 ,
VAR9 ,
VAR3,
VAR1,
VAR11 ,
VAR7
);
output VAR6 ;
input VAR8 ;
input VAR2 ;
input VAR5 ;
input VAR4 ;
input VAR10 ;
input VAR9 ;
input VAR3;
input VAR1;
input VAR11 ;
input VAR7 ;
endmodule | apache-2.0 |
spacemonkeydelivers/mor1kx | rtl/verilog/mor1kx_branch_predictor_gshare.v | 4,528 | module MODULE1
parameter VAR2 = 10,
parameter VAR21 = 32
)
(
input clk,
input rst,
output VAR11,
input VAR5, input VAR22, input VAR9, input VAR8, input VAR16, input VAR20,
input VAR7, input VAR1,
input [VAR21-1:0] VAR6
);
localparam [1:0]
VAR15 = 2'b00,
VAR13 = 2'b01,
VAR19 = 2'b10,
VAR14 = 2'b11;
localparam VAR10 = 2 ... | mpl-2.0 |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/radio_controller_v1_08_a/hdl/verilog/spi_clgen.v | 4,955 | module MODULE1 (VAR5, rst, VAR6, enable, VAR8, VAR7, VAR2, posedge, negedge);
parameter VAR3 = 1;
input VAR5; input rst; input enable; input VAR6; input VAR8; input VAR7; output VAR2; output posedge; output negedge;
reg VAR2;
reg posedge;
reg negedge;
reg VAR1; wire VAR9; wire VAR4;
assign VAR9 = VAR1 == {1{1'b0}};
ass... | bsd-2-clause |
johan92/yafpgatetris | tetris/rtl/string_rom.v | 6,572 | module MODULE1
parameter VAR31 = 16,
parameter VAR43 = "2.VAR42"
)
(
VAR54,
address,
VAR49);
input [VAR27-1:0] address;
input VAR54;
output [VAR31-1:0] VAR49;
tri1 VAR54;
wire [VAR31-1:0] VAR40;
wire [VAR31-1:0] VAR49 = VAR40[VAR31-1:0];
VAR36 VAR1 (
.VAR8 (address),
.VAR51 (VAR54),
.VAR45 (VAR40),
.VAR35 (1'b0),
.VAR3... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/velocityControlHdl_Reset_Delay_block1.v | 2,061 | module MODULE1
(
VAR1,
reset,
VAR10,
VAR8,
VAR12,
VAR11
);
input VAR1;
input reset;
input VAR10;
input VAR8;
input signed [31:0] VAR12; output signed [31:0] VAR11;
wire signed [31:0] VAR5; wire signed [31:0] VAR2; reg signed [31:0] VAR7; wire signed [31:0] VAR9; wire signed [31:0] VAR6;
assign VAR5 = 32'VAR3;
assign VA... | gpl-3.0 |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/NIOS_SYSTEMV3/synthesis/submodules/NIOS_SYSTEMV3_NIOS_CPU_mult_cell.v | 6,367 | module MODULE1 (
VAR6,
VAR33,
clk,
VAR31,
VAR28
)
;
output [ 31: 0] VAR28;
input [ 31: 0] VAR6;
input [ 31: 0] VAR33;
input clk;
input VAR31;
wire [ 31: 0] VAR28;
wire [ 31: 0] VAR39;
wire [ 15: 0] VAR56;
wire VAR51;
assign VAR51 = ~VAR31;
VAR24 VAR40
(
.VAR3 (VAR51),
.VAR43 (clk),
.VAR25 (VAR6[15 : 0]),
.VAR27 (VAR33[... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai33/gf180mcu_fd_sc_mcu9t5v0__oai33_2.behavioral.pp.v | 5,425 | module MODULE1( VAR10, VAR4, VAR1, VAR8, VAR12, VAR11, VAR9, VAR5, VAR6 );
input VAR9, VAR11, VAR12, VAR1, VAR4, VAR10;
inout VAR5, VAR6;
output VAR8;
VAR2 VAR3(.VAR10(VAR10),.VAR4(VAR4),.VAR1(VAR1),.VAR8(VAR8),.VAR12(VAR12),.VAR11(VAR11),.VAR9(VAR9),.VAR5(VAR5),.VAR6(VAR6));
VAR2 VAR7(.VAR10(VAR10),.VAR4(VAR4),.VAR1(V... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_2.behavioral.v | 3,431 | module MODULE1( VAR3, VAR1, VAR6, VAR2, VAR5, VAR8 );
input VAR6, VAR1, VAR3, VAR8, VAR5;
output VAR2;
VAR7 VAR4(.VAR3(VAR3),.VAR1(VAR1),.VAR6(VAR6),.VAR2(VAR2),.VAR5(VAR5),.VAR8(VAR8));
VAR7 VAR9(.VAR3(VAR3),.VAR1(VAR1),.VAR6(VAR6),.VAR2(VAR2),.VAR5(VAR5),.VAR8(VAR8)); | apache-2.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/IPRepo-1.0.0/Tiger4NSC/src/BCHEncoderControl.v | 7,677 | module MODULE1
(
parameter VAR2 = 32 ,
parameter VAR32 = 32 ,
parameter VAR15 = 16 ,
parameter VAR56 = 2
)
(
VAR8 ,
VAR49 ,
VAR35 ,
VAR13 ,
VAR36 ,
VAR17 ,
VAR19 ,
VAR29 ,
VAR12 ,
VAR26 ,
VAR62 ,
VAR60 ,
VAR42 ,
VAR48 ,
VAR40 ,
VAR27 ,
VAR6 ,
VAR64 ,
VAR20 ,
VAR46 ,
VAR54 ,
VAR11 ,
VAR18 ,
VAR4
);
input VAR8 ;
input VA... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_comm_link/bsg_assembler_in.v | 2,882 | module MODULE1 #(parameter VAR3(VAR30)
,parameter VAR3(VAR7)
,parameter VAR3(VAR15)
,parameter VAR14=(1 << (VAR7-1)))
(input clk
, input reset
, input VAR22
, input [VAR7-1:0] VAR21
, input [VAR30-1 :0] VAR26 [VAR7]
, output [VAR7-1:0] VAR5
, input [VAR12(0,VAR20(VAR7)-1):0] VAR23
, input [VAR12(0,VAR20(VAR15)-1):0] VA... | bsd-3-clause |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/rtl/mem/ram_core.v | 5,578 | module MODULE1 #(
parameter VAR5 = 32,
parameter VAR7 = 11
)(
input wire VAR15,
input wire VAR18,
input wire VAR14,
input wire VAR13,
input wire [VAR7-1:0] VAR9,
input wire [VAR7-1:0] VAR1,
input wire [VAR5-1:0] VAR2,
input wire [VAR5-1:0] VAR8,
output reg [VAR5-1:0] VAR10,
output reg [VAR5-1:0] VAR11
);
reg [VAR5-1:0]... | apache-2.0 |
nikhilghanathe/HLS-for-EMTF | verilog/sp_extend_sector.v | 26,902 | module MODULE1 (
VAR118,
VAR45,
VAR84,
VAR90,
VAR28,
VAR51,
VAR108,
VAR124,
VAR77,
VAR75,
VAR137,
VAR85,
VAR66,
VAR72,
VAR115,
VAR49,
VAR65,
VAR42,
VAR59,
VAR3,
VAR119,
VAR7,
VAR31,
VAR114,
VAR13,
VAR53,
VAR120,
VAR37,
VAR38,
VAR133,
VAR78,
VAR112,
VAR110,
VAR41,
VAR86,
VAR99,
VAR70,
VAR9,
VAR50,
VAR4,
VAR126
);
parame... | apache-2.0 |
alan4186/ssd_design | v/flash_ctrl.v | 14,122 | module MODULE1(
input clk, input rst,
output reg VAR21,
input [7:0] VAR43, output reg [7:0] VAR16, input [31:0] VAR37,
input VAR28, input VAR15, input VAR6, output VAR44, output reg VAR3, output reg VAR33, output VAR2,
output reg VAR20,
output reg VAR29,
output reg VAR8,
output reg VAR1,
output reg VAR17,
output reg VA... | mit |
asicguy/gplgpu | hdl/de/ded_mskgen.v | 15,316 | module MODULE1
(
input VAR74, VAR33, VAR63, VAR45, VAR10, input VAR42, input VAR9, VAR2, input [1:0] VAR77, input VAR62, input VAR21, input [VAR5-1:0] VAR1, input [31:0] VAR22, input [15:0] VAR40, input [6:0] VAR14, input VAR17, input [VAR5-1:0] VAR57, input VAR31, input VAR56, input VAR44, input [3:0] VAR18, input [6:... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or2b/sky130_fd_sc_hs__or2b.blackbox.v | 1,230 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR4
);
output VAR2 ;
input VAR1 ;
input VAR4;
supply1 VAR3;
supply0 VAR5;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o221a/sky130_fd_sc_hd__o221a.pp.symbol.v | 1,401 | module MODULE1 (
input VAR10 ,
input VAR1 ,
input VAR2 ,
input VAR6 ,
input VAR4 ,
output VAR5 ,
input VAR7 ,
input VAR9,
input VAR3,
input VAR8
);
endmodule | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_hdmi_tx_16b_v1_00_a/hdl/verilog/cf_hdmi_tx_16b.v | 12,578 | module MODULE1 (
VAR80,
VAR36,
VAR11,
VAR42,
VAR46,
VAR25,
VAR13,
VAR50,
VAR2,
VAR71,
VAR30,
VAR27,
VAR78,
VAR68,
VAR75,
VAR5,
VAR35,
VAR4,
VAR55,
VAR28,
VAR21,
VAR51,
VAR19,
VAR57);
input VAR80;
output VAR36;
output VAR11;
output VAR42;
output [15:0] VAR46;
input VAR25;
output VAR13;
input VAR50;
input VAR2;
input [ 7... | mit |
mrehkopf/sd2snes | verilog/sd2snes_base/cheat.v | 17,035 | module MODULE1(
input clk,
input [7:0] VAR9,
input [23:0] VAR14,
input [7:0] VAR61,
input VAR22,
input VAR76,
input VAR50,
input VAR6,
input VAR25,
input VAR37,
input VAR35,
input VAR15,
input VAR28,
input VAR47,
input VAR33,
input VAR55,
input VAR29,
input [2:0] VAR44,
input VAR51,
input [31:0] VAR5,
input VAR43,
outp... | gpl-2.0 |
SiLab-Bonn/basil | basil/firmware/modules/timestamp/timestamp.v | 1,728 | module MODULE1 #(
parameter VAR13 = 16'h0000,
parameter VAR11 = 16'h0000,
parameter VAR12 = 16,
parameter VAR19 = 4'b0001
) (
input wire VAR16,
input wire [VAR12-1:0] VAR7,
inout wire [7:0] VAR23,
input wire VAR28,
input wire VAR22,
input wire VAR20,
input wire VAR10,
input wire VAR5,
input wire [63:0] VAR2,
output wir... | bsd-3-clause |
YurongYou/MIPS_CPU | ID.v | 1,295 | module MODULE1 (
input rst,
input[VAR1-1:0] VAR12,
input[VAR10-1:0] VAR32,
output[VAR16-1:0] VAR8,
output[VAR16-1:0] VAR6,
output VAR23,
output VAR9,
output VAR15,
output VAR33,
output[VAR4-1:0] VAR31,
output[VAR29-1:0] VAR28,
output VAR21,
output VAR27,
output VAR20,
output VAR3,
output VAR25,
output[VAR16-1:0] VAR14,... | mpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlrtn/sky130_fd_sc_hdll__dlrtn.blackbox.v | 1,362 | module MODULE1 (
VAR7 ,
VAR1,
VAR6 ,
VAR2
);
output VAR7 ;
input VAR1;
input VAR6 ;
input VAR2 ;
supply1 VAR4;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
xuefei1/ElectronicEngineControl | db/ip/niosII_system/submodules/niosII_system_nios2_0_jtag_debug_module_wrapper.v | 10,416 | module MODULE1 (
VAR9,
VAR16,
clk,
VAR22,
VAR28,
VAR42,
VAR38,
VAR12,
VAR50,
VAR49,
VAR40,
VAR54,
VAR26,
VAR2,
VAR47,
VAR21,
VAR18,
VAR58,
VAR37,
VAR51,
VAR55,
VAR48,
VAR3,
VAR14,
VAR1,
VAR56,
VAR13,
VAR45,
VAR25,
VAR4,
VAR33,
VAR31,
VAR27,
VAR24,
VAR5,
VAR6
)
;
output [ 37: 0] VAR55;
output VAR48;
output VAR3;
output ... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi22/gf180mcu_fd_sc_mcu9t5v0__aoi22_4.behavioral.v | 2,309 | module MODULE1( VAR5, VAR1, VAR3, VAR2, VAR6 );
input VAR6, VAR2, VAR3, VAR5;
output VAR1;
VAR7 VAR4(.VAR5(VAR5),.VAR1(VAR1),.VAR3(VAR3),.VAR2(VAR2),.VAR6(VAR6));
VAR7 VAR8(.VAR5(VAR5),.VAR1(VAR1),.VAR3(VAR3),.VAR2(VAR2),.VAR6(VAR6)); | apache-2.0 |
kmod/processor | src/util.v | 6,601 | module MODULE2 #(parameter VAR3=18) (
input wire clk,
input wire [15:0] in,
output reg [7:0] VAR10,
output reg [3:0] VAR2
);
reg [VAR3-1:0] VAR5; always @(posedge clk) begin
VAR5 <= VAR5 + 1'b1;
end
wire [1:0] VAR12; assign VAR12 = VAR5[VAR3-1:VAR3-2];
reg [3:0] VAR15;
always @(*) begin
VAR2 = 4'b1111;
VAR2[VAR12] = 0;... | mit |
devinacker/sd2snes | verilog/sd2sneslite/main.v | 9,853 | module MODULE1(
input VAR100,
input [23:0] VAR107,
input VAR133,
input VAR26,
input VAR134,
inout [7:0] VAR34,
input VAR51,
input VAR61,
output VAR102,
output VAR111,
output VAR6,
input VAR21,
input [7:0] VAR80,
input VAR12,
input VAR97,
inout [15:0] VAR60,
output [22:0] VAR5,
output VAR47,
output VAR23,
output VAR40,
... | gpl-2.0 |
olgirard/openmsp430 | fpga/OBSOLETE/altera_de1_board/rtl/verilog/ram16x512.v | 7,047 | module MODULE1 (
address,
VAR43,
VAR17,
VAR46,
VAR9,
VAR18,
VAR36);
input [8:0] address;
input [1:0] VAR43;
input VAR17;
input VAR46;
input [15:0] VAR9;
input VAR18;
output [15:0] VAR36;
wire [15:0] VAR29;
wire [15:0] VAR36 = VAR29[15:0];
VAR22 VAR2 (
.VAR7 (VAR17),
.VAR39 (VAR18),
.VAR41 (VAR46),
.VAR8 (VAR43),
.VAR50... | bsd-3-clause |
asicguy/gplgpu | hdl/de/dex_alu.v | 15,652 | module MODULE1
(
input VAR88,
input VAR69,
input [4:0] VAR19,
input [15:0] VAR115,
input [15:0] VAR116,
input [15:0] VAR9,
input [15:0] VAR86,
input [4:0] VAR24,
input VAR62,
input VAR96,
input VAR110,
input VAR82,
input VAR71,
input VAR17,
input VAR103,
input VAR35,
input VAR75,
output [15:0] VAR65,
output [15:0] VAR6... | gpl-3.0 |
bigeagle/riffa | fpga/riffa_hdl/txr_engine_ultrascale.v | 23,927 | module MODULE3
parameter VAR30 = 128,
parameter VAR14 = 1,
parameter VAR34 = 1,
parameter VAR8 = 10,
parameter VAR40 = 256
)
(
input VAR155,
input VAR135,
input [VAR42-1:0] VAR59,
input VAR98,
output VAR164,
output VAR134,
output [VAR30-1:0] VAR71,
output [(VAR30/32)-1:0] VAR100,
output [VAR129-1:0] VAR69,
input VAR117... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfsbp/sky130_fd_sc_lp__dfsbp.behavioral.pp.v | 2,300 | module MODULE1 (
VAR22 ,
VAR8 ,
VAR14 ,
VAR17 ,
VAR10,
VAR9 ,
VAR1 ,
VAR3 ,
VAR19
);
output VAR22 ;
output VAR8 ;
input VAR14 ;
input VAR17 ;
input VAR10;
input VAR9 ;
input VAR1 ;
input VAR3 ;
input VAR19 ;
wire VAR15 ;
wire VAR18 ;
reg VAR13 ;
wire VAR4 ;
wire VAR20;
wire VAR12 ;
wire VAR11 ;
wire VAR21 ;
wire VAR6 ;... | apache-2.0 |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_AO_LVT_SS_210930.v | 231,277 | module MODULE1 (VAR3, VAR6, VAR10, VAR1, VAR4);
output VAR3;
input VAR6, VAR10, VAR1, VAR4;
wire VAR7, VAR9, VAR11;
wire VAR2, VAR5, VAR8;
not (VAR2, VAR4);
not (VAR11, VAR1);
not (VAR9, VAR10);
and (VAR5, VAR9, VAR11);
not (VAR7, VAR6);
and (VAR8, VAR7, VAR11);
or (VAR3, VAR8, VAR5, VAR2); | bsd-3-clause |
fabianz66/cursos-tec | taller-digital/Lab2/laboratorio2/clock_divider.v | 1,027 | module MODULE1(input clk, input rst, output reg VAR1);
reg [25:0] counter;
begin
begin
begin
end
begin | mit |
ptracton/Picoblaze | library/display/display.v | 3,038 | module MODULE1 (
VAR1, VAR4,
clk, VAR2, VAR6, VAR10, VAR7
) ;
input clk;
input [3:0] VAR2;
input [3:0] VAR6;
input [3:0] VAR10;
input [3:0] VAR7;
output [3:0] VAR1;
output [7:0] VAR4;
reg [3:0] VAR1 = 4'hF;
reg [7:0] VAR4 = 8'h00;
reg [31:0] VAR3 = 32'h00000000;
wire VAR9 = (VAR3 == 32'd100000);
always @(posedge clk)
i... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdlclkp/sky130_fd_sc_hd__sdlclkp.pp.symbol.v | 1,332 | module MODULE1 (
input VAR3 ,
input VAR2 ,
input VAR7,
output VAR6,
input VAR8 ,
input VAR1,
input VAR5,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand2b/sky130_fd_sc_lp__nand2b.behavioral.pp.v | 1,936 | module MODULE1 (
VAR13 ,
VAR1 ,
VAR3 ,
VAR9,
VAR2,
VAR6 ,
VAR10
);
output VAR13 ;
input VAR1 ;
input VAR3 ;
input VAR9;
input VAR2;
input VAR6 ;
input VAR10 ;
wire VAR15 ;
wire VAR14 ;
wire VAR5;
not VAR4 (VAR15 , VAR3 );
or VAR12 (VAR14 , VAR15, VAR1 );
VAR11 VAR7 (VAR5, VAR14, VAR9, VAR2);
buf VAR8 (VAR13 , VAR5 );
e... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand4/sky130_fd_sc_ms__nand4.behavioral.pp.v | 1,846 | module MODULE1 (
VAR12 ,
VAR7 ,
VAR4 ,
VAR1 ,
VAR11 ,
VAR8,
VAR2,
VAR13 ,
VAR9
);
output VAR12 ;
input VAR7 ;
input VAR4 ;
input VAR1 ;
input VAR11 ;
input VAR8;
input VAR2;
input VAR13 ;
input VAR9 ;
wire VAR3 ;
wire VAR15;
nand VAR14 (VAR3 , VAR11, VAR1, VAR4, VAR7 );
VAR5 VAR10 (VAR15, VAR3, VAR8, VAR2);
buf VAR6 (V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a31o/sky130_fd_sc_hd__a31o.pp.blackbox.v | 1,383 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR6 ,
VAR7 ,
VAR8 ,
VAR9,
VAR3,
VAR4 ,
VAR5
);
output VAR2 ;
input VAR1 ;
input VAR6 ;
input VAR7 ;
input VAR8 ;
input VAR9;
input VAR3;
input VAR4 ;
input VAR5 ;
endmodule | apache-2.0 |
petrmikheev/miksys | verilog/COMMAND_PAGE.v | 9,131 | module MODULE1 (
VAR26,
VAR12,
VAR30,
VAR4,
VAR44,
VAR7);
input VAR26;
input [15:0] VAR12;
input [7:0] VAR30;
input [8:0] VAR4;
input VAR44;
output [31:0] VAR7;
tri1 VAR26;
tri0 VAR44;
wire [31:0] VAR39;
wire [31:0] VAR7 = VAR39[31:0];
VAR22 VAR59 (
.VAR47 (VAR4),
.VAR23 (VAR26),
.VAR19 (VAR12),
.VAR16 (VAR44),
.VAR36 ... | gpl-3.0 |
DougFirErickson/parallella-hw | fpga/src/elink/hdl/erx_disty.v | 4,222 | module MODULE1 (
VAR26, VAR14, VAR15, VAR21, VAR4,
VAR6, VAR22, VAR16, VAR25, VAR17,
VAR5,
clk, VAR12, VAR7, VAR13, VAR10, VAR2,
VAR23, VAR9, VAR18, VAR11,
VAR19, VAR3, VAR8
);
parameter [11:0] VAR1 = 12'h810;
parameter VAR24 = 7;
parameter [31:0] VAR20 = 32'h3E000000;
input clk;
input VAR12;
input VAR7;
input VAR13;
i... | gpl-3.0 |
lkesteloot/alice | alice4/fpga/Alice4-DE0-Nano-SoC/Debouncer.v | 1,250 | module MODULE1 #(parameter VAR1=1'b0)
(
input wire VAR5,
input wire VAR2,
input wire VAR3,
output reg VAR6,
output reg VAR4
);
localparam VAR7 = 21;
reg [VAR7-1:0] counter;
always @(posedge VAR5 or negedge VAR2) begin
if (!VAR2) begin
VAR6 <= VAR1;
counter <= 1'b0;
VAR4 <= 1'b0;
end else begin
VAR4 <= 1'b0;
if (VAR3 ==... | apache-2.0 |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/controller/mig_7series_v2_0_arb_row_col.v | 18,940 | module MODULE1 #
(
parameter VAR32 = 100,
parameter VAR38 = "1T",
parameter VAR17 = 5,
parameter VAR80 = "VAR65",
parameter VAR72 = 4,
parameter VAR81 = 2,
parameter VAR97 = 37500, parameter VAR91 = 12500, parameter VAR52 = 6 )
(
VAR39, VAR40, VAR14, VAR27, VAR41, VAR85,
VAR12, VAR88, VAR20,
VAR67, VAR34, VAR4, VAR69, ... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.blackbox.v | 1,395 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR2 ,
VAR3,
VAR6 ,
VAR4
);
output VAR1 ;
input VAR5 ;
input VAR2 ;
input VAR3;
input VAR6 ;
input VAR4 ;
endmodule | apache-2.0 |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/wasca/synthesis/submodules/wasca_pio_0.v | 2,794 | module MODULE1 (
address,
VAR11,
clk,
VAR12,
VAR5,
VAR4,
VAR2,
VAR1
)
;
inout [ 3: 0] VAR2;
output [ 31: 0] VAR1;
input [ 1: 0] address;
input VAR11;
input clk;
input VAR12;
input VAR5;
input [ 31: 0] VAR4;
wire [ 3: 0] VAR2;
wire VAR8;
reg [ 3: 0] VAR6;
wire [ 3: 0] VAR9;
reg [ 3: 0] VAR10;
wire [ 3: 0] VAR7;
reg [ 31... | gpl-2.0 |
asicguy/gplgpu | hdl/ramdac_sp/cpu_int.v | 25,528 | module MODULE1
(
input VAR87,
input VAR88,
input [2:0] VAR121,
input VAR86,
input VAR19,
input [7:0] VAR14,
input [6:0] VAR13,
input [5:0] VAR136,
input [2:0] VAR8,
input [1:0] VAR109,
input [7:0] VAR54,
input VAR131,
input VAR108,
input VAR129,
input VAR35,
input VAR4,
input VAR21,
input VAR33,
input [7:0] VAR117,
inp... | gpl-3.0 |
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