repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
egyp7/mor1kx | rtl/verilog/mor1kx_immu.v | 14,295 | module MODULE1
parameter VAR32 = "VAR39",
parameter VAR88 = 32,
parameter VAR90 = 6,
parameter VAR34 = 1
)
(
input clk,
input rst,
input VAR87,
output VAR78,
input [VAR88-1:0] VAR16,
input [VAR88-1:0] VAR36,
output reg [VAR88-1:0] VAR72,
output reg VAR44,
input VAR62,
output reg VAR81,
output VAR89,
output reg VAR35,
i... | mpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.v | 2,336 | module MODULE1 (
VAR8 ,
VAR7,
VAR1,
VAR3 ,
VAR5 ,
VAR9,
VAR2
);
output VAR8 ;
input VAR7;
input VAR1;
input VAR3 ;
input VAR5 ;
input VAR9;
input VAR2;
VAR4 VAR6 (
.VAR8(VAR8),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR8 ,
VAR7,
VAR1,
VAR3 ,
VAR5
);
ou... | apache-2.0 |
tommythorn/yari | DE2-70/rtl/mega/video_pll.v | 14,531 | module MODULE1 (
VAR42,
VAR1);
input VAR42;
output VAR1;
wire [5:0] VAR18;
wire [0:0] VAR91 = 1'h0;
wire [0:0] VAR88 = VAR18[0:0];
wire VAR1 = VAR88;
wire VAR98 = VAR42;
wire [1:0] VAR61 = {VAR91, VAR98};
VAR20 VAR50 (
.VAR26 (VAR61),
.clk (VAR18),
.VAR37 (),
.VAR19 (1'b0),
.VAR9 (),
.VAR49 ({6{1'b1}}),
.VAR46 (),
.VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a41o/sky130_fd_sc_ls__a41o.functional.v | 1,462 | module MODULE1 (
VAR2 ,
VAR8,
VAR7,
VAR6,
VAR1,
VAR10
);
output VAR2 ;
input VAR8;
input VAR7;
input VAR6;
input VAR1;
input VAR10;
wire VAR4 ;
wire VAR5;
and VAR3 (VAR4 , VAR8, VAR7, VAR6, VAR1 );
or VAR11 (VAR5, VAR4, VAR10 );
buf VAR9 (VAR2 , VAR5 );
endmodule | apache-2.0 |
DreamSourceLab/DSLogic-hdl | src/i2c/serialInterface.v | 10,966 | module MODULE1 (VAR41, clk, VAR21, VAR32, VAR36, rst, VAR9, VAR34, VAR29, VAR43, VAR42);
input clk;
input [7:0]VAR21;
input rst;
input VAR9;
input VAR34;
input [1:0]VAR43;
output VAR41;
output [7:0]VAR32;
output [7:0]VAR36;
output VAR29;
output VAR42;
reg VAR41, VAR12;
wire clk;
wire [7:0]VAR21;
reg [7:0]VAR32, VAR40;
... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand4bb/sky130_fd_sc_hd__nand4bb.pp.blackbox.v | 1,357 | module MODULE1 (
VAR7 ,
VAR4 ,
VAR6 ,
VAR3 ,
VAR5 ,
VAR2,
VAR9,
VAR1 ,
VAR8
);
output VAR7 ;
input VAR4 ;
input VAR6 ;
input VAR3 ;
input VAR5 ;
input VAR2;
input VAR9;
input VAR1 ;
input VAR8 ;
endmodule | apache-2.0 |
onchipuis/mriscv_vivado | mriscv_vivado.srcs/sources_1/ip/ddr_axi/ddr_axi/user_design/rtl/phy/mig_7series_v4_0_poc_cc.v | 7,934 | module MODULE1 #
(parameter VAR14 = 100,
parameter VAR58 = 0,
parameter VAR19 = 2,
parameter VAR6 = 95,
parameter VAR33 = 8,
parameter VAR42 = 128,
parameter VAR55 = 2,
parameter VAR28 = 7)
(
VAR39, VAR61, VAR49, VAR40,
VAR43, clk, rst, VAR54, VAR34,
VAR5, VAR60, VAR48,
VAR23, VAR24, VAR41, VAR36,
VAR1, VAR22, VAR2, VA... | mit |
hoangt/NOCulator | hring/hw/buffered/src/c_wf_alloc_rep.v | 4,587 | module MODULE1
(clk, reset, VAR24, req, VAR3);
parameter VAR13 = 8;
parameter VAR35 = 0;
parameter VAR16 = VAR20;
localparam VAR33 = VAR23(VAR13);
input clk;
input reset;
input VAR24;
input [0:VAR13*VAR13-1] req;
output [0:VAR13*VAR13-1] VAR3;
wire [0:VAR13*VAR13-1] VAR3;
wire [0:VAR33-1] VAR14, VAR5;
VAR34
.VAR32(0),
... | mit |
ptracton/wb_soc_template | rtl/ZIP/rtl/dcache.v | 15,359 | module MODULE1(VAR15, VAR53, VAR42, VAR12,
VAR85, VAR79, VAR65, VAR84,
VAR44, VAR21, VAR51, VAR90, VAR43,VAR9,
VAR75, VAR26, VAR38, VAR1,
VAR7, VAR4, VAR77,
VAR61, VAR20, VAR47, VAR64);
parameter VAR17 = 8,
VAR52=32,
VAR49=5, VAR30=0,
VAR41=5; localparam VAR73 = 26;
localparam VAR24 = 22;
localparam VAR6= 15;
localpara... | mit |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtp_x8_125/source/pcie_blk_cf_err.v | 24,243 | module MODULE1
(
input wire clk,
input wire VAR71,
input VAR88,
input VAR11,
input VAR103,
input VAR129,
input VAR149,
input VAR108,
input VAR137,
input VAR28,
input [47:0] VAR96,
output VAR143,
input VAR31, input VAR29, input VAR25, input VAR91,
input VAR54,
input VAR169,
input VAR105, input VAR93, input VAR112,
input... | lgpl-3.0 |
donnaware/ZBC---The-Zero-Board-Computer | rtl/ver1/rtl/zbc.v | 33,681 | module MODULE1 (
input VAR157, input reset,
output [1:0] VAR235, input [1:0] VAR368, input [3:0] VAR184, input [1:0] VAR27,
output VAR273, output VAR84,
output [11:0] VAR53, inout [15:0] VAR154, output [ 1:0] VAR43, output VAR396, output VAR316, output VAR67, output VAR395, output VAR227, output VAR99,
output [ 3:0] VA... | gpl-3.0 |
bkboggy/MIPS | ALU_CONTROL.v | 1,368 | module MODULE1(input [5:0] VAR1, input [1:0] VAR2, output reg [2:0] select);
always @ *
begin
case (VAR2)
2'b00:
begin
select <= 3'b010; end
2'b01:
begin
select <= 3'b110; end
2'b10:
begin
case (VAR1)
6'b100000:
begin
select <= 3'b010; end
6'b100010:
begin
select <= 3'b110; end
6'b100100:
begin
select <= 3'b000; end
6'... | mit |
dailypips/miaow | src/verilog/rtl/issue/valid_entry.v | 1,651 | module MODULE1
(
VAR11,
clk, rst, VAR18, VAR10, VAR9,
VAR6, VAR4, VAR1,
VAR22, VAR7, VAR8, VAR3
);
input clk,rst;
input VAR18, VAR10, VAR9,
VAR6, VAR4, VAR1,
VAR22;
input [VAR20-1:0] VAR7, VAR8,
VAR3;
wire VAR25;
wire [VAR27-1:0] VAR5, VAR15,
VAR26,
VAR17;
output [VAR27-1:0] VAR11;
VAR2 VAR13(
.VAR19(VAR7),
.out(VAR5),... | bsd-3-clause |
richard42/CoCo3FPGA | FIFO_WRITE_bb.v | 6,185 | module MODULE1 (
VAR9,
VAR6,
VAR4,
VAR8,
VAR3,
VAR1,
VAR2,
VAR7,
VAR5);
input VAR9;
input [7:0] VAR6;
input VAR4;
input VAR8;
input VAR3;
input VAR1;
output [7:0] VAR2;
output VAR7;
output VAR5;
tri0 VAR9;
endmodule | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a2111oi/sky130_fd_sc_ms__a2111oi.blackbox.v | 1,402 | module MODULE1 (
VAR4 ,
VAR5,
VAR3,
VAR8,
VAR9,
VAR1
);
output VAR4 ;
input VAR5;
input VAR3;
input VAR8;
input VAR9;
input VAR1;
supply1 VAR6;
supply0 VAR10;
supply1 VAR2 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/mux2i/sky130_fd_sc_hdll__mux2i.pp.symbol.v | 1,355 | module MODULE1 (
input VAR2 ,
input VAR1 ,
output VAR6 ,
input VAR8 ,
input VAR4 ,
input VAR7,
input VAR3,
input VAR5
);
endmodule | apache-2.0 |
freecores/tiny_tate_bilinear_pairing | group_size_is_697_bits/rtl/tiny.v | 2,893 | module MODULE2(clk, reset, sel, addr, VAR5, VAR11, out, VAR26);
input clk, reset;
input sel;
input [5:0] addr;
input VAR5;
input [VAR25:0] VAR11;
output [VAR25:0] out;
output VAR26;
wire [5:0] VAR36;
wire [5:0] VAR14, VAR4;
wire [VAR25:0] VAR12;
wire VAR13, VAR1;
wire [VAR25:0] VAR32, VAR24;
wire [VAR25:0] VAR17, VAR20... | apache-2.0 |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_thesis_ANN_2_0/hdl/verilog/ANN_fptrunc_64ns_32_1.v | 1,103 | module MODULE1
VAR11 = 3,
VAR3 = 1,
VAR6 = 64,
VAR7 = 32
)(
input wire [VAR6-1:0] VAR9,
output wire [VAR7-1:0] dout
);
wire VAR12;
wire [63:0] VAR15;
wire VAR2;
wire [31:0] VAR10;
VAR8 VAR14 (
.VAR13 ( VAR12 ),
.VAR1 ( VAR15 ),
.VAR16 ( VAR2 ),
.VAR5 ( VAR10 )
);
assign VAR12 = 1'b1;
assign VAR15 = VAR9==='VAR4 ? 'b0 :... | gpl-3.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/mc/mc_chroma_ip_1p.v | 4,909 | module MODULE1 (
clk,
VAR23,
VAR5,
VAR18,
VAR29,
VAR30,
VAR24,
VAR15,
VAR17,
VAR22,
VAR6,
VAR13
);
input clk ;
input VAR23 ;
input VAR5 ;
input [2 :0] VAR18 ;
input [2 :0] VAR29 ;
input VAR30 ;
input [VAR12-1:0] VAR24 ;
input [VAR12-1:0] VAR15 ;
input [VAR12-1:0] VAR17 ;
input [VAR12-1:0] VAR22 ;
output VAR6;
output [V... | gpl-3.0 |
impedimentToProgress/ProbableCause | ddr2/cores/ram_wb/ram_wb.v | 6,155 | module MODULE1
(
VAR17, VAR48, VAR29, VAR44, VAR9, VAR6,
VAR71, VAR73,
VAR16, VAR54, VAR4, VAR34,
VAR66, VAR18, VAR40, VAR10, VAR27, VAR47,
VAR20, VAR19,
VAR52, VAR32, VAR64, VAR67,
VAR37, VAR65, VAR13, VAR55, VAR1, VAR60,
VAR43, VAR42,
VAR25, VAR28, VAR46, VAR39,
VAR58, VAR24
);
parameter VAR50 = 32;
parameter VAR35 =... | mit |
SI-RISCV/e200_opensource | rtl/e203/debug/sirv_debug_rom.v | 8,304 | module MODULE1(
input [7-1:2] VAR3,
output [32-1:0] VAR2
);
wire [31:0] VAR1 [0:28];
assign VAR2 = VAR1[VAR3];
assign VAR1[ 0][7 : 0] = 8'h6f;
assign VAR1[ 0][15: 8] = 8'h00;
assign VAR1[ 0][23:16] = 8'hc0;
assign VAR1[ 0][31:24] = 8'h03;
assign VAR1[ 1][7 : 0] = 8'h6f;
assign VAR1[ 1][15: 8] = 8'h00;
assign VAR1[ 1][2... | apache-2.0 |
aabdelfattah/alhaitham-hardware | DE2_115_CAMERA.v | 16,964 | module MODULE1(
VAR278,
VAR115,
VAR107,
VAR181,
VAR154,
VAR111,
VAR187,
VAR37,
VAR10,
VAR34,
VAR172,
VAR242,
VAR228,
VAR227,
VAR250,
VAR71,
VAR87,
VAR32,
VAR89,
VAR213,
VAR133,
VAR17,
VAR229,
VAR223,
VAR210,
VAR293,
VAR86,
VAR163,
VAR28,
VAR110,
VAR66,
VAR80,
VAR202,
VAR45,
VAR119,
VAR141,
VAR296,
VAR149,
VAR46,
VAR276... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/add_rm_hdr/add_rm_hdr.v | 3,575 | module MODULE1
parameter VAR26 = 64,
parameter VAR18=VAR26/8,
parameter VAR29 = 'hff,
parameter VAR6 = 0
)
(
VAR11,
VAR15,
VAR12,
VAR17,
VAR16,
VAR22,
VAR25,
VAR14,
VAR20,
VAR3,
VAR8,
VAR19,
VAR30,
VAR4,
VAR2,
VAR1,
reset,
clk
);
input [VAR26-1:0] VAR11;
input [VAR18-1:0] VAR15;
input VAR12;
output VAR17;
output [VAR26... | mit |
asicguy/gplgpu | hdl/altera_ddr3_128/alt_mem_ddrx_buffer.v | 3,835 | module MODULE1
parameter
VAR14 = 3,
VAR9 = 8
)
(
VAR59,
VAR36,
VAR24,
VAR58,
VAR50,
VAR42,
VAR35,
VAR11
);
localparam VAR32 = VAR37(VAR14);
input VAR59;
input VAR36;
input VAR24;
input [VAR14-1:0] VAR58;
input [VAR9-1:0] VAR50;
input VAR42;
input [VAR14-1:0] VAR35;
output [VAR9-1:0] VAR11;
wire VAR59;
wire VAR36;
wire ... | gpl-3.0 |
openfpga/xc3sprog | bscan_spi/bscan_s3a_spi_isf_ext.v | 1,276 | module MODULE1
(
output wire VAR44,
output wire VAR27,
output wire VAR4,
input VAR16
);
wire VAR9;
wire VAR25;
wire VAR24;
wire VAR21;
reg [47:0] VAR43;
reg [15:0] VAR32;
reg VAR17 = 0;
assign VAR44 = VAR24 ;
wire VAR28;
wire VAR10;
wire VAR22;
reg VAR41 = 0;
reg VAR15 = 0;
reg VAR5 = 0;
reg VAR6 = 0;
reg [13:0] VAR7;
... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/tapvgnd/sky130_fd_sc_ms__tapvgnd_1.v | 1,938 | module MODULE1 (
VAR3,
VAR6,
VAR5 ,
VAR2
);
input VAR3;
input VAR6;
input VAR5 ;
input VAR2 ;
VAR4 VAR1 (
.VAR3(VAR3),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR2(VAR2)
);
endmodule
module MODULE1 ();
supply1 VAR3;
supply0 VAR6;
supply1 VAR5 ;
supply0 VAR2 ;
VAR4 VAR1 ();
endmodule | apache-2.0 |
everskar2013/PentiumX | Hardware/Code/ctrl_withdualport.v | 16,718 | module MODULE1(
clk,
reset,
VAR43,
VAR22,
VAR36,
VAR31,
VAR73,
VAR47,
VAR48,
VAR59,
VAR63,
VAR65,
VAR61,
VAR4,
VAR9,
VAR13,
VAR72,
VAR35,
VAR1,
VAR5,
VAR53,
VAR70,
VAR44,
VAR40,
VAR67,
VAR27,
VAR37,
VAR30,
VAR18,
VAR64,
VAR45,
VAR55,
VAR68
);
input wire clk, reset;
input wire [31: 0] VAR43;
input wire VAR22, VAR36, VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/edfxtp/sky130_fd_sc_ls__edfxtp_1.v | 2,277 | module MODULE2 (
VAR6 ,
VAR7 ,
VAR9 ,
VAR4 ,
VAR10,
VAR5,
VAR3 ,
VAR2
);
output VAR6 ;
input VAR7 ;
input VAR9 ;
input VAR4 ;
input VAR10;
input VAR5;
input VAR3 ;
input VAR2 ;
VAR1 VAR8 (
.VAR6(VAR6),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR2(VAR2)
);
endmodule
module MODULE... | apache-2.0 |
elegabriel/myzju | junior1/CA/LAB/lab6/lab6_gxl_3120102146/code/IF_ID.v | 1,632 | module MODULE1(clk,rst,VAR4, VAR7, VAR1,
VAR6,VAR3, VAR5,VAR2,VAR8
);
input clk,rst,VAR7, VAR1;
input wire [31:0] VAR4,VAR6,VAR2;
output reg [31:0] VAR3,VAR5,VAR8;
always @(posedge clk or posedge rst)
begin
if(rst)
begin
VAR3 <= 4;
VAR5 <= 32'b100000;
VAR8<=0;
end
else if(VAR7 | VAR1)
begin
VAR3 <= VAR4;
VAR5 <= 32'b10... | gpl-2.0 |
kkalavantavanich/SD2017 | segMaster.v | 2,030 | /* VAR17 VAR26 VAR3 VAR31 VAR29 VAR28 VAR18.
* VAR8 VAR14 VAR12 use/VAR5/VAR15 in VAR4 VAR27 VAR21 this VAR10 VAR24 VAR6 VAR19 VAR20.
* VAR1: VAR2:
module MODULE1(
input clk,
input [15:0] VAR25,
input [3:0] VAR22, output [6:0] VAR23,
output [3:0] VAR16,
output VAR9
);
reg [2:0] VAR7 = 0;
wire [1:0] VAR30;
assign VAR30 ... | mit |
Obijuan/open-fpga-verilog-tutorial | tutorial/ICESTICK/T28-ram/buffer.v | 3,666 | module MODULE1 (input wire clk,
input wire VAR14,
output wire VAR17,
output wire [3:0] VAR9,
output reg VAR21);
parameter VAR16 = VAR29;
parameter VAR10 = "VAR28.VAR25";
parameter VAR24 = 4;
parameter VAR8 = 8;
reg VAR13 = 0;
always @(posedge clk)
VAR13 <= 1;
reg [VAR24-1: 0] addr = 0;
wire [VAR8-1: 0] VAR18;
wire [VAR... | gpl-2.0 |
nishtahir/arty-blaze | src/bd/system/ip/system_rst_mig_7series_0_83M_0/system_rst_mig_7series_0_83M_0_stub.v | 1,820 | module MODULE1(VAR2, VAR1, VAR10,
VAR4, VAR3, VAR8, VAR5, VAR9,
VAR7, VAR6)
;
input VAR2;
input VAR1;
input VAR10;
input VAR4;
input VAR3;
output VAR8;
output [0:0]VAR5;
output [0:0]VAR9;
output [0:0]VAR7;
output [0:0]VAR6;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/xnor2/sky130_fd_sc_hvl__xnor2_1.v | 2,140 | module MODULE1 (
VAR8 ,
VAR4 ,
VAR7 ,
VAR5,
VAR2,
VAR3 ,
VAR9
);
output VAR8 ;
input VAR4 ;
input VAR7 ;
input VAR5;
input VAR2;
input VAR3 ;
input VAR9 ;
VAR1 VAR6 (
.VAR8(VAR8),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR9(VAR9)
);
endmodule
module MODULE1 (
VAR8,
VAR4,
VAR7
);
output VAR8;
... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/efc/rtl/efc.v | 21,523 | module MODULE1 (
VAR157, VAR166, VAR151,
VAR46, VAR40,
VAR36, VAR154,
VAR35, VAR53,
VAR98, VAR165,
VAR49, VAR85,
VAR135, VAR13,
VAR150, VAR114,
VAR2, VAR108,
VAR39, VAR144,
VAR68, VAR99,
VAR171, VAR52,
VAR119, VAR100,
VAR132, VAR159,
VAR24, VAR9,
VAR6, VAR22,
VAR95, VAR59,
VAR169, VAR109,
VAR113, VAR83,
VAR77, VAR64,
V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o221ai/sky130_fd_sc_ms__o221ai.behavioral.pp.v | 2,212 | module MODULE1 (
VAR2 ,
VAR11 ,
VAR20 ,
VAR4 ,
VAR19 ,
VAR12 ,
VAR9,
VAR3,
VAR6 ,
VAR5
);
output VAR2 ;
input VAR11 ;
input VAR20 ;
input VAR4 ;
input VAR19 ;
input VAR12 ;
input VAR9;
input VAR3;
input VAR6 ;
input VAR5 ;
wire VAR14 ;
wire VAR15 ;
wire VAR10 ;
wire VAR17;
or VAR18 (VAR14 , VAR19, VAR4 );
or VAR7 (VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/invlp/sky130_fd_sc_lp__invlp.symbol.v | 1,258 | module MODULE1 (
input VAR4,
output VAR1
);
supply1 VAR3;
supply0 VAR6;
supply1 VAR5 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
davidkoltak/tawas-core | ip/tawas/rtl/tawas.v | 5,652 | module MODULE1
(
input clk,
input rst,
output VAR30,
output [23:0] VAR18,
input [31:0] VAR60,
output VAR44,
output VAR8,
output [31:0] VAR28,
output [3:0] VAR52,
output [31:0] dout,
input [31:0] din,
input [68:0] VAR65,
output [68:0] VAR10
);
parameter VAR22 = 0;
wire VAR57;
wire [4:0] VAR55;
wire [4:0] VAR11;
wire [4:... | mit |
MeshSr/onetswitch20 | ons20-app21-ref_switch/vivado/onets_7020_ref_switch/ip/ref_switch_core/src/core/eth_queue.v | 6,239 | module MODULE1
parameter VAR44 = 64,
parameter VAR31=VAR44/8,
parameter VAR30 = 0,
parameter VAR36 = 'hff,
parameter VAR40 = 0
)( input VAR4,
input VAR10,
input [31:0] VAR1,
input [31:0] VAR11,
output [31:0] VAR41,
output VAR26,
output [VAR44-1:0] VAR20,
output [VAR31-1:0] VAR21,
output VAR46,
input VAR23,
input [VAR44... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o32a/sky130_fd_sc_lp__o32a.pp.blackbox.v | 1,417 | module MODULE1 (
VAR6 ,
VAR9 ,
VAR1 ,
VAR3 ,
VAR2 ,
VAR4 ,
VAR8,
VAR10,
VAR7 ,
VAR5
);
output VAR6 ;
input VAR9 ;
input VAR1 ;
input VAR3 ;
input VAR2 ;
input VAR4 ;
input VAR8;
input VAR10;
input VAR7 ;
input VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/xor2/sky130_fd_sc_ls__xor2_4.v | 2,117 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR6 ,
VAR4,
VAR5,
VAR2 ,
VAR7
);
output VAR3 ;
input VAR1 ;
input VAR6 ;
input VAR4;
input VAR5;
input VAR2 ;
input VAR7 ;
VAR9 VAR8 (
.VAR3(VAR3),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR3,
VAR1,
VAR6
);
output VAR3;
... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/db/GeAr_N8_R2_P4_syn.v | 1,784 | module MODULE1 ( VAR9, VAR51, VAR38 );
input [7:0] VAR9;
input [7:0] VAR51;
output [8:0] VAR38;
wire VAR3, VAR6, VAR34, VAR20, VAR48,
VAR44, VAR45, VAR46, VAR17, VAR23, VAR1, VAR29;
VAR52 VAR10 ( .VAR19(VAR51[1]), .VAR33(VAR9[1]), .VAR36(VAR3), .VAR32(
VAR6), .VAR53(VAR38[1]) );
VAR52 VAR39 ( .VAR19(VAR51[2]), .VAR33(V... | gpl-3.0 |
tmolteno/TART | hardware/FPGA/tart_spi/verilog/correlator/ones_count.v | 6,638 | module MODULE1
parameter VAR42 = VAR28-1,
parameter VAR9 = 12, parameter VAR26 = 4,
parameter VAR32 = (2<<VAR26)-1,
parameter VAR14 = 3)
(
input VAR39, input rst,
input VAR29, input VAR4,
input VAR22,
input VAR25, input VAR40, output VAR15,
input [4:0] VAR6,
input [VAR42:0] VAR21,
output reg [VAR42:0] VAR18,
input enab... | lgpl-3.0 |
kevintownsend/inara-hdl-libraries | std_fifo/std_fifo.v | 2,291 | module MODULE1(rst, clk, VAR2, VAR10, VAR13, VAR5, VAR9, VAR11, VAR17, VAR3, VAR7);
parameter VAR16 = 8;
parameter VAR12 = 8;
parameter VAR14 = VAR1(VAR12-1);
parameter VAR8 = 1;
parameter VAR6 = 1;
input rst;
input clk;
input VAR2;
input VAR10;
input [VAR16-1:0] VAR13;
output [VAR16-1:0] VAR5;
output VAR9;
output VAR1... | apache-2.0 |
toomij/DE2Labs | Lab3/lab3_part4.v | 1,702 | module MODULE4 (VAR1, VAR5, VAR9, VAR6, VAR4);
input VAR1, VAR5;
output VAR9, VAR6, VAR4;
wire VAR1, VAR5;
MODULE1 VAR3 (VAR1, VAR5, VAR9);
MODULE2 VAR8 (VAR1, VAR5, VAR6);
MODULE3 VAR7 (VAR1, VAR5, VAR4);
endmodule
module MODULE3 (VAR1, VAR5, VAR2);
input VAR1, VAR5;
output reg VAR2;
always @ (negedge VAR5)
VAR2 = VAR... | gpl-2.0 |
bluespec/Flute | builds/RV64ACIMU_Flute_iverilog/Verilog_RTL/mkUART.v | 132,389 | module MODULE1(VAR187,
VAR308,
VAR54,
VAR1,
VAR196,
VAR285,
VAR99,
VAR22,
VAR92,
VAR229,
VAR217,
VAR43,
VAR173,
VAR200,
VAR171,
VAR90,
VAR135,
VAR250,
VAR314,
VAR356,
VAR145,
VAR189,
VAR115,
VAR4,
VAR208,
VAR10,
VAR346,
VAR85,
VAR61,
VAR97,
VAR335,
VAR57,
VAR337,
VAR159,
VAR350,
VAR222,
VAR94,
VAR150,
VAR278,
VAR152,
V... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/tmp/ucore/ucore.v | 27,541 | module MODULE1
(
VAR127,VAR35,
VAR226,VAR32,VAR277,VAR186,VAR214,
VAR349,VAR96,VAR44,VAR220,VAR90,
VAR68,VAR195,VAR276,VAR365,
VAR31,
VAR311
,
VAR309,VAR215,VAR262,
VAR157,VAR181,VAR245,
VAR45,VAR221,VAR164
);
input VAR127;
input VAR35;
output VAR226;
output VAR32;
output [31:0] VAR277;
input VAR186;
input [31:0] VAR21... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a2bb2o/sky130_fd_sc_ls__a2bb2o.behavioral.v | 1,705 | module MODULE1 (
VAR14 ,
VAR11,
VAR1,
VAR10 ,
VAR5
);
output VAR14 ;
input VAR11;
input VAR1;
input VAR10 ;
input VAR5 ;
supply1 VAR13;
supply0 VAR9;
supply1 VAR2 ;
supply0 VAR12 ;
wire VAR8 ;
wire VAR3 ;
wire VAR4;
and VAR6 (VAR8 , VAR10, VAR5 );
nor VAR7 (VAR3 , VAR11, VAR1 );
or VAR16 (VAR4, VAR3, VAR8);
buf VAR15 (... | apache-2.0 |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/system/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v | 9,229 | module MODULE1(
VAR31,
VAR108,
VAR93,
VAR19,
VAR99,
VAR55,
VAR70,
VAR38,
VAR37,
VAR118,
VAR104,
VAR30,
VAR60,
VAR84,
VAR73,
VAR39,
VAR117,
VAR33,
VAR89,
VAR9,
VAR48,
VAR18,
VAR61,
VAR32,
VAR109,
VAR16,
VAR77,
VAR86,
VAR64
);
parameter VAR45 = "";
parameter VAR97 = "";
parameter VAR126 = "";
parameter VAR24 = "";
parame... | mit |
alankarkotwal/lca-processor | USE THESE FILES PRAVEEN/register.v | 1,706 | module MODULE2(clk, out, in, write, reset);
output reg [15:0] out;
input [15:0] in;
input clk, write, reset;
always@(posedge clk) begin
if(reset==0) begin
out = 16'b0;
end
else if(write == 1'b0) begin
out = in;
end
end
endmodule
module MODULE1(clk, out, in, write, reset);
output reg [3:0] out;
input [3:0] in;
input clk... | gpl-2.0 |
kmod/bitcoin_mining | fpga/src/sha256.v | 7,703 | module MODULE1(
input wire [5:0] VAR16, output reg [31:0] VAR12
);
always @ begin
VAR20 = VAR5(VAR6[1], 7) ^ VAR5(VAR6[1], 18) ^ (VAR6[1] >> 3);
VAR3 = VAR5(VAR6[14], 17) ^ VAR5(VAR6[14], 19) ^ (VAR6[14] >> 10);
VAR4 = VAR6[0] + VAR20 + VAR6[9] + VAR3;
VAR13 = VAR5(VAR15[4], 6) ^ VAR5(VAR15[4], 11) ^ VAR5(VAR15[4], 25)... | gpl-2.0 |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/syn/verilog/tri_intersect_fmul_32ns_32ns_32_5_max_dsp.v | 1,940 | module MODULE1
VAR2 = 23,
VAR18 = 5,
VAR6 = 32,
VAR10 = 32,
VAR5 = 32
)(
input wire clk,
input wire reset,
input wire VAR14,
input wire [VAR6-1:0] VAR3,
input wire [VAR10-1:0] VAR22,
output wire [VAR5-1:0] dout
);
wire VAR26;
wire VAR23;
wire VAR9;
wire [31:0] VAR15;
wire VAR16;
wire [31:0] VAR17;
wire VAR7;
wire [31:0... | mit |
cpulabs/mist1032sa | src/core/microcode/microcode_context_load.v | 39,540 | module MODULE1(
input VAR14,
input VAR7,
input [31:0] VAR13,
output [31:0] VAR15,
input [72:0] VAR5,
input [72:0] VAR12
);
wire [73:0] VAR8;
wire [73:0] VAR3;
assign VAR8 = VAR4(VAR13<<1);
assign VAR3 = VAR4((VAR13<<1) + 32'h1);
assign VAR15 = VAR10;
assign VAR5 = VAR8[72:0];
assign VAR12 = VAR3[72:0];
function [73:0] ... | bsd-2-clause |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_SEQ_SLVT_FF_210930.v | 73,208 | module MODULE1 (VAR16, VAR6, VAR9, VAR13);
output VAR16;
input VAR6, VAR9, VAR13;
reg VAR10;
wire VAR2, VAR1;
wire VAR8, VAR5, VAR7;
wire VAR15;
not (VAR8, VAR2);
not (VAR7, VAR9);
VAR14 (VAR15, VAR1, VAR8, VAR7);
VAR3 (VAR5, VAR10, VAR1, VAR8, VAR7, VAR15);
buf (VAR16, VAR5);
wire VAR12, VAR4, VAR11;
and (VAR12, VAR6,... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or4/sky130_fd_sc_hd__or4_4.v | 2,231 | module MODULE1 (
VAR2 ,
VAR5 ,
VAR3 ,
VAR4 ,
VAR9 ,
VAR8,
VAR7,
VAR11 ,
VAR1
);
output VAR2 ;
input VAR5 ;
input VAR3 ;
input VAR4 ;
input VAR9 ;
input VAR8;
input VAR7;
input VAR11 ;
input VAR1 ;
VAR6 VAR10 (
.VAR2(VAR2),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/ebufn/sky130_fd_sc_lp__ebufn_4.v | 2,148 | module MODULE1 (
VAR9 ,
VAR4 ,
VAR7,
VAR5,
VAR3,
VAR6 ,
VAR2
);
output VAR9 ;
input VAR4 ;
input VAR7;
input VAR5;
input VAR3;
input VAR6 ;
input VAR2 ;
VAR1 VAR8 (
.VAR9(VAR9),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR9 ,
VAR4 ,
VAR7
);
output VAR9 ;... | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/wb_readback_mux.v | 2,124 | module MODULE1
(input VAR14,
input VAR20,
input VAR11,
input [15:0] VAR12,
output reg [31:0] VAR15,
output reg VAR3,
input [31:0] VAR9,
input [31:0] VAR6,
input [31:0] VAR17,
input [31:0] VAR19,
input [31:0] VAR5,
input [31:0] VAR8,
input [31:0] VAR7,
input [31:0] VAR4,
input [31:0] VAR2,
input [31:0] VAR16,
input [31:... | gpl-2.0 |
zatslogic/UDI_example | udi_pipelined/udi_top.v | 5,899 | module MODULE1 (
input [31:0] VAR58 , input VAR43 , input [31:0] VAR40 , input [31:0] VAR39 , input VAR16 , input VAR9 , input VAR61 , input VAR10 , input VAR8 , input VAR44 , input VAR34 , input VAR25 ,
output [31:0] VAR36 , output [4:0] VAR33 ,
output VAR12 , output VAR26 , output VAR60 , output VAR5 , input [VAR29-1... | gpl-3.0 |
travisg/cpu | rtl/cpu/stage4_memory.v | 2,248 | module MODULE1(
input VAR6,
input VAR4,
input [31:0] VAR11,
input VAR13,
input VAR9,
input VAR8,
input VAR7,
input [4:0] VAR3,
output VAR16,
output reg VAR10,
output reg [4:0] VAR2,
output reg [31:0] VAR5
);
reg [31:0] VAR1;
reg VAR14;
reg VAR15;
assign VAR16 = 0;
always @(posedge VAR6)
begin
if (VAR4) begin
VAR1 <= 0;... | mit |
MarcoVogt/basil | firmware/modules/seq_rec/seq_rec.v | 1,589 | module MODULE1
parameter VAR3 = 0,
parameter VAR20 = 0,
parameter VAR21 = 16,
parameter VAR5 = 8*1024,
parameter VAR9 = 8
)(
input wire VAR7,
input wire VAR1,
input wire [VAR21-1:0] VAR25,
inout wire [7:0] VAR24,
input wire VAR6,
input wire VAR12,
input wire VAR2,
input wire [VAR9-1:0] VAR19,
input wire VAR10
);
wire V... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv3sd1/sky130_fd_sc_ms__clkdlyinv3sd1_1.v | 2,164 | module MODULE2 (
VAR1 ,
VAR4 ,
VAR8,
VAR5,
VAR6 ,
VAR3
);
output VAR1 ;
input VAR4 ;
input VAR8;
input VAR5;
input VAR6 ;
input VAR3 ;
VAR7 VAR2 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR1,
VAR4
);
output VAR1;
input VAR4;
supply1 VAR8;
supply0 VAR5;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fa/sky130_fd_sc_ms__fa.pp.blackbox.v | 1,303 | module MODULE1 (
VAR2,
VAR5 ,
VAR3 ,
VAR4 ,
VAR6 ,
VAR8,
VAR9,
VAR7 ,
VAR1
);
output VAR2;
output VAR5 ;
input VAR3 ;
input VAR4 ;
input VAR6 ;
input VAR8;
input VAR9;
input VAR7 ;
input VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfxtp/sky130_fd_sc_ms__dfxtp.functional.v | 1,470 | module MODULE1 (
VAR7 ,
VAR5,
VAR4
);
output VAR7 ;
input VAR5;
input VAR4 ;
wire VAR1;
VAR2 VAR6 VAR8 (VAR1 , VAR4, VAR5 );
buf VAR3 (VAR7 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/tap/sky130_fd_sc_hd__tap.pp.symbol.v | 1,217 | module MODULE1 (
input VAR1 ,
input VAR4,
input VAR2,
input VAR3
);
endmodule | apache-2.0 |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/system/synthesis/submodules/acl_profiler.v | 4,692 | module MODULE2
(
VAR4,
VAR1,
enable,
VAR9,
VAR13,
VAR7,
VAR14
);
parameter VAR18=64;
parameter VAR6=32;
parameter VAR11=4;
parameter VAR12=VAR6 * VAR11;
parameter VAR2=64;
input VAR4;
input VAR1;
input enable;
input VAR9;
input [VAR11-1:0] VAR13;
input [VAR12-1:0] VAR7;
output [VAR2-1:0] VAR14;
wire [VAR11-2:0][VAR2-1:... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18.symbol.v | 1,356 | module MODULE1 (
input VAR3,
output VAR6
);
supply1 VAR1;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/ipi_proj/srcs/ip/xilinx_com_hls_image_filter_1_0/hdl/verilog/image_filter_mul_8ns_22ns_30_3.v | 1,411 | module MODULE2(clk, VAR10, VAR3, VAR1, VAR13);
input clk;
input VAR10;
input[8 - 1 : 0] VAR3; input[22 - 1 : 0] VAR1; output[30 - 1 : 0] VAR13;
reg [8 - 1 : 0] VAR14;
reg [22 - 1 : 0] VAR16;
wire [30 - 1 : 0] VAR5;
reg [30 - 1 : 0] VAR6;
assign VAR13 = VAR6;
assign VAR5 = VAR14 * VAR16;
always @ (posedge clk) begin
if ... | gpl-3.0 |
jmesmon/trifles | verilog/hw3/p18.v | 1,690 | module MODULE2(output VAR15, VAR4, input VAR12, VAR19, VAR13, clk);
wire [3:0]VAR26;
nand VAR20(VAR26[0], VAR19, VAR26[1], VAR26[3]),
VAR23(VAR26[1], VAR26[0], clk, VAR12),
VAR29(VAR26[2], VAR26[1], clk, VAR26[3]),
VAR7(VAR26[3], VAR13, VAR26[2], VAR12);
nand VAR33(VAR15, VAR26[1], VAR19, VAR4),
VAR18(VAR4, VAR26[2], V... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_4.behavioral.pp.v | 8,945 | module MODULE1( VAR13, VAR20, VAR58, VAR47, VAR79, VAR11, VAR45 );
input VAR13, VAR20, VAR47, VAR58;
inout VAR11, VAR45;
output VAR79;
reg VAR76;
VAR12 VAR88(.VAR13(VAR13),.VAR20(VAR20),.VAR58(VAR58),.VAR47(VAR47),.VAR79(VAR79),.VAR11(VAR11),.VAR45(VAR45),.VAR76(VAR76));
VAR12 VAR87(.VAR13(VAR13),.VAR20(VAR20),.VAR58(V... | apache-2.0 |
olajep/oh | src/elink/hdl/ecfg_if.v | 4,755 | module MODULE1 (
VAR56, VAR13, VAR43, VAR40, VAR6, VAR4,
VAR30, VAR16,
clk, VAR59, VAR38, VAR53, VAR51, VAR25, VAR1,
VAR12, VAR18
);
parameter VAR23 = 0; parameter VAR33 = 104;
parameter VAR41 = 32;
parameter VAR20 = 32;
parameter VAR42 = 12'h999;
input clk;
input VAR59;
input VAR38;
input [VAR33-1:0] VAR53;
output VAR... | mit |
ipburbank/Raster-Laser-Projector | src/Raster_Laser_Projector/synthesis/submodules/altera_reset_synchronizer.v | 3,473 | module MODULE1
parameter VAR2 = 1,
parameter VAR3 = 2
)
(
input VAR5 ,
input clk,
output VAR1
);
reg [VAR3-1:0] VAR4;
reg VAR6;
generate if (VAR2) begin
always @(posedge clk or posedge VAR5) begin
if (VAR5) begin
VAR4 <= {VAR3{1'b1}};
VAR6 <= 1'b1;
end
else begin
VAR4[VAR3-2:0] <= VAR4[VAR3-1:1];
VAR4[VAR3-1] <= 0;
VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_4.v | 2,398 | module MODULE2 (
VAR5 ,
VAR8,
VAR7,
VAR11 ,
VAR10 ,
VAR1,
VAR4,
VAR3 ,
VAR2
);
output VAR5 ;
input VAR8;
input VAR7;
input VAR11 ;
input VAR10 ;
input VAR1;
input VAR4;
input VAR3 ;
input VAR2 ;
VAR9 VAR6 (
.VAR5(VAR5),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR2... | apache-2.0 |
thucoldwind/ucore_mips | CPU32/thinpad_top/thinpad_top.srcs/sources_1/new/sram.v | 1,028 | module MODULE1(
input wire[21:0] VAR8,
input wire VAR4,
input wire VAR11,
input wire VAR9,
inout wire[31:0] VAR6
);
wire[21:0] addr = VAR8[21:0];
wire VAR1;
wire VAR2;
reg[31:0] VAR10[0:4195000];
reg[31:0] VAR12;
assign VAR6 = VAR12;
assign VAR1 = ~VAR9;
assign VAR2 = ~VAR4;
always @(*) begin
if (VAR2 == VAR7 || VAR1 =... | unlicense |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/dram_sstl_pad.v | 4,592 | module MODULE1(
VAR1, VAR13,
VAR9,
VAR25, VAR16, VAR23, VAR5, VAR26, VAR2,
VAR11, VAR4, VAR14, VAR3, VAR6, VAR20, VAR10
);
inout VAR9;
output VAR13; output VAR1;
input VAR10; input [8:1] VAR20; input [8:1] VAR6; input VAR3; input VAR14; input VAR4; input VAR11; input VAR2; input VAR26; input VAR5; input VAR23; input VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlrtp/sky130_fd_sc_ls__dlrtp.pp.symbol.v | 1,434 | module MODULE1 (
input VAR8 ,
output VAR6 ,
input VAR4,
input VAR3 ,
input VAR7 ,
input VAR2 ,
input VAR5 ,
input VAR1
);
endmodule | apache-2.0 |
545/Atari7800 | riot/riot.v | 5,252 | module MODULE1(VAR11, VAR12, VAR9, VAR6, VAR8, VAR22, VAR32, VAR34, VAR19, VAR16, VAR15, VAR13, VAR4, VAR2); input [6:0] VAR11;
input [7:0] VAR12;
output [7:0] VAR9;
input VAR6, VAR8, VAR22, VAR32, VAR34, VAR16;
output VAR19;
input [7:0] VAR15, VAR4;
output [7:0] VAR13, VAR2; reg [7:0] VAR9; reg [7:0] VAR26[127:0]; reg... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkbuf/sky130_fd_sc_ms__clkbuf.blackbox.v | 1,228 | module MODULE1 (
VAR6,
VAR5
);
output VAR6;
input VAR5;
supply1 VAR4;
supply0 VAR2;
supply1 VAR1 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o211ai/sky130_fd_sc_lp__o211ai.symbol.v | 1,375 | module MODULE1 (
input VAR1,
input VAR9,
input VAR8,
input VAR2,
output VAR3
);
supply1 VAR6;
supply0 VAR7;
supply1 VAR5 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfbbn/sky130_fd_sc_hs__sdfbbn.blackbox.v | 1,492 | module MODULE1 (
VAR8 ,
VAR7 ,
VAR10 ,
VAR1 ,
VAR6 ,
VAR2 ,
VAR3 ,
VAR4
);
output VAR8 ;
output VAR7 ;
input VAR10 ;
input VAR1 ;
input VAR6 ;
input VAR2 ;
input VAR3 ;
input VAR4;
supply1 VAR5;
supply0 VAR9;
endmodule | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/txc_engine_classic.v | 16,191 | parameter VAR7 = 1,
parameter VAR137 = 0,
parameter VAR58 = 64,
parameter VAR99 = 10,
parameter VAR29 = "VAR82")
( input VAR38,
input VAR61, output VAR134,
input [VAR64-1:0] VAR20,
input VAR43,
output [VAR100-1:0] VAR2,
output VAR101,
output VAR89,
output [VAR115(VAR100/32)-1:0] VAR37,
output VAR136,
output [VAR115(VAR... | gpl-3.0 |
fabianmcg/usbc_tcpc | src/rx.v | 4,158 | module MODULE1(VAR21,reset,VAR23,VAR15, VAR13, VAR26, VAR4, VAR27, VAR16, VAR2, VAR24,
VAR20,VAR22,VAR19, VAR14, address, VAR5);
localparam VAR3 = 4'b0000;
localparam VAR25 = 4'b0001;
localparam VAR18 = 4'b0010;
localparam VAR29 = 4'b0100;
localparam VAR28 = 4'b1000;
input wire VAR30;
input wire VAR21;
input wire reset... | mit |
ShepardSiegel/ocpi | coregen/temac_v6_v1_5/example_design/v6_emac_v1_5_locallink.v | 14,103 | module MODULE1
(
VAR40,
VAR38,
VAR68,
VAR104,
VAR20,
VAR14,
VAR35,
VAR54,
VAR43,
VAR86,
VAR66,
VAR7,
VAR102,
VAR19,
VAR28,
VAR55,
VAR101,
VAR69,
VAR9,
VAR95,
VAR25,
VAR33,
VAR83,
VAR29,
VAR59,
VAR58,
VAR15,
VAR27,
VAR80,
VAR71,
VAR57,
VAR13,
VAR44,
VAR51,
VAR78,
VAR96,
VAR37,
VAR1,
VAR74
);
output VAR40;
input VAR38;
i... | lgpl-3.0 |
ultraembedded/riscv | core/riscv/riscv_multiplier.v | 5,438 | module MODULE1
(
input VAR17
,input VAR22
,input VAR27
,input [ 31:0] VAR29
,input [ 31:0] VAR14
,input VAR3
,input [ 4:0] VAR13
,input [ 4:0] VAR20
,input [ 4:0] VAR4
,input [ 31:0] VAR6
,input [ 31:0] VAR23
,input VAR5
,output [ 31:0] VAR16
);
localparam VAR30 = 2;
reg [31:0] VAR9;
reg [31:0] VAR10;
reg [32:0] VAR15;... | bsd-3-clause |
DougFirErickson/parallella-hw | fpga/old/hdl/parallella-I/parallella.v | 37,253 | module MODULE1 (
VAR61, VAR158, VAR139, VAR108, VAR10, VAR239,
VAR76, VAR189, VAR247, VAR170, VAR7,
VAR95, VAR133, VAR204, VAR75,
VAR24, VAR223, VAR5, VAR167, VAR140,
VAR161, VAR210, VAR117, VAR62,
VAR244, VAR2, VAR80, VAR196, VAR82,
VAR205, VAR17, VAR84, VAR27, VAR219,
VAR69, VAR181, VAR56, VAR179, VAR53,
VAR147, VAR1... | gpl-3.0 |
ChrisPVille/RL02 | FPGA/ipcore_dir/dataFIFO.v | 13,710 | module MODULE1(
clk,
VAR334,
din,
VAR4,
VAR24,
dout,
VAR135,
VAR250,
VAR256
);
input clk;
input VAR334;
input [16 : 0] din;
input VAR4;
input VAR24;
output [16 : 0] dout;
output VAR135;
output VAR250;
output VAR256;
VAR7 #(
.VAR34(0),
.VAR361(0),
.VAR109(0),
.VAR310(0),
.VAR416(0),
.VAR264(0),
.VAR355(0),
.VAR379(32),
... | gpl-3.0 |
kyzhai/NUNY | src/hardware/ninja2.v | 6,363 | module MODULE1 (
address,
VAR39,
VAR38);
input [11:0] address;
input VAR39;
output [11:0] VAR38;
tri1 VAR39;
wire [11:0] VAR36;
wire [11:0] VAR38 = VAR36[11:0];
VAR2 VAR9 (
.VAR3 (address),
.VAR6 (VAR39),
.VAR26 (VAR36),
.VAR10 (1'b0),
.VAR47 (1'b0),
.VAR14 (1'b1),
.VAR8 (1'b0),
.VAR46 (1'b0),
.VAR30 (1'b1),
.VAR28 (1'... | gpl-2.0 |
sh-chris110/chris | FPGA/chris.convolution.ok/db/ip/soc_design/submodules/chris_pipelined.v | 7,808 | module MODULE1 (
input wire [7:0] VAR18, input wire VAR9, output wire [31:0] VAR29, input wire VAR25, input wire [31:0] VAR13, output wire VAR5, input wire VAR24, input wire VAR10, output wire VAR27, output wire [31:0] VAR22, output wire VAR20, input wire VAR3, input wire [31:0] VAR21, input wire VAR6, output wire VAR3... | gpl-2.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/rw_manager_data_broadcast.v | 2,289 | module MODULE1(
VAR14,
VAR3,
VAR6,
VAR2
);
parameter VAR16 = "";
parameter VAR17 = "";
parameter VAR20 = "";
parameter VAR8 = "";
localparam VAR5 = VAR16 * VAR17;
localparam VAR15 = 2 * VAR20;
input [VAR17 * VAR15 - 1 : 0] VAR14;
input [VAR15 - 1 : 0] VAR3;
output [VAR5 * VAR15 - 1 : 0] VAR6;
output [VAR8 * 2 * VAR20 -... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/Chart.v | 3,079 | module MODULE1
(
VAR8,
reset,
VAR7,
VAR3,
VAR9
);
input VAR8;
input reset;
input VAR7;
input [15:0] VAR3; output [15:0] VAR9;
parameter VAR6 = 0, VAR4 = 1;
reg [1:0] VAR11; reg [15:0] VAR5; reg [1:0] VAR13; reg [15:0] VAR10; reg [16:0] VAR1; reg signed [16:0] VAR2;
always @(posedge VAR8)
begin : VAR12
if (reset == 1'b1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/nor3/sky130_fd_sc_hvl__nor3.symbol.v | 1,312 | module MODULE1 (
input VAR5,
input VAR8,
input VAR4,
output VAR2
);
supply1 VAR7;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
MarcoVogt/basil | firmware/modules/seq_rec/seq_rec_core.v | 6,301 | module MODULE1
parameter VAR27 = 8*1024,
parameter VAR11 = 16,
parameter VAR5 = 8
)(
VAR30,
VAR10,
VAR29,
VAR8,
VAR6,
VAR28,
VAR17,
VAR3,
VAR2,
VAR13
);
localparam VAR14 = 0;
input wire VAR30;
input wire VAR10;
input wire [VAR11-1:0] VAR29;
input wire [7:0] VAR8;
input wire VAR6;
input wire VAR28;
output reg [7:0] VAR1... | bsd-3-clause |
alan4186/Hardware-CNN | Hardware/v/feature_map_buffer_ctrl.v | 1,364 | module MODULE1(
input VAR6,
input reset,
input VAR8,
input [VAR9:0] VAR3,
input [VAR2:0] VAR7,
output reg [VAR4:0] addr,
output reg VAR5
);
always@(posedge VAR6 or negedge reset) begin
if(reset == 1'b0)
addr <= VAR10'd0;
end
else if (VAR8)
if(VAR3[0]&VAR7[0])
addr <= addr + VAR10'd1;
else
addr <= addr;
else
addr <= VAR... | mit |
sabertazimi/hust-lab | architecture/design/fpga/src/lru_counter.v | 3,055 | module MODULE1
(
input clk,
input rst,
input en,
input VAR6,
input [VAR27-1:0] VAR7,
output [VAR27-1:0] VAR34
);
wire [VAR27-1:0] VAR32;
wire VAR29, VAR5, VAR23, VAR22, VAR35, VAR11, VAR31, VAR17;
wire [VAR27-1:0] VAR21, VAR28, VAR12, VAR15, VAR13, VAR30, VAR19, VAR18;
assign VAR32 = VAR6 ? VAR7 : VAR34;
assign VAR29 =... | mit |
kevintownsend/R3 | verilog/mac.v | 2,123 | module MODULE1(
input clk,
input reset,
input [9:0] VAR16,
input [63:0] VAR24,
input [63:0] VAR30,
input wr,
output VAR27,
output [63:0] dout,
input VAR8);
reg VAR5 [14:0];
reg [9:0] VAR18 [14:0];
reg VAR2 [11:0];
reg [9:0] VAR21 [11:0];
wire [63:0] VAR15;
wire [63:0] sum;
wire VAR1;
wire [63:0] VAR20, VAR19;
wire [9:0... | mit |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/new/SHD_top.v | 5,220 | module MODULE1 #(parameter VAR46 = 128) (
input VAR32,
input VAR71, output VAR22,
input VAR70,
output VAR67,
input VAR21,
input[31:0] VAR74,
input[30:0] VAR20,
input[VAR46 - 1:0] VAR14,
input VAR72,
output VAR1,
output VAR6,
output VAR2,
input VAR17,
output VAR68,
output[31:0] VAR69,
output[30:0] VAR37,
output[VAR46 - ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlxbp/sky130_fd_sc_ls__dlxbp.symbol.v | 1,364 | module MODULE1 (
input VAR4 ,
output VAR5 ,
output VAR7 ,
input VAR6
);
supply1 VAR8;
supply0 VAR2;
supply1 VAR1 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axi_data_fifo_v2_1/hdl/verilog/axi_data_fifo_v2_1_axic_reg_srl_fifo.v | 9,777 | module MODULE1 #
(
parameter VAR24 = "none", parameter integer VAR41 = 1, parameter integer VAR35 = 33, parameter integer VAR39 = 2, parameter VAR3 = 1 )
(
input wire VAR34, input wire VAR4, input wire [VAR41-1:0] VAR15, input wire VAR27, output wire VAR8, output wire [VAR41-1:0] VAR36, output wire VAR5, input wire VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfsbp/sky130_fd_sc_ls__dfsbp.behavioral.v | 2,273 | module MODULE1 (
VAR20 ,
VAR11 ,
VAR5 ,
VAR21 ,
VAR4
);
output VAR20 ;
output VAR11 ;
input VAR5 ;
input VAR21 ;
input VAR4;
supply1 VAR13;
supply0 VAR14;
supply1 VAR6 ;
supply0 VAR19 ;
wire VAR12 ;
wire VAR15 ;
reg VAR7 ;
wire VAR3 ;
wire VAR18;
wire VAR10 ;
wire VAR2 ;
wire VAR8 ;
wire VAR9 ;
not VAR1 (VAR15 , VAR18 ... | apache-2.0 |
alexforencich/xfcp | lib/eth/rtl/eth_mac_1g_rgmii.v | 6,989 | module MODULE1 #
(
parameter VAR63 = "VAR24",
parameter VAR42 = "VAR40",
parameter VAR13 = "VAR10",
parameter VAR54 = "VAR26",
parameter VAR23 = 1,
parameter VAR19 = 64
)
(
input wire VAR74,
input wire VAR36,
input wire VAR1,
output wire VAR56,
output wire VAR35,
output wire VAR32,
output wire VAR57,
input wire [7:0] V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/bushold/sky130_fd_sc_lp__bushold.pp.blackbox.v | 1,341 | module MODULE1 (
VAR4 ,
VAR1,
VAR3 ,
VAR6 ,
VAR5 ,
VAR2
);
inout VAR4 ;
input VAR1;
input VAR3 ;
input VAR6 ;
input VAR5 ;
input VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor2/sky130_fd_sc_ls__nor2_1.v | 2,086 | module MODULE2 (
VAR7 ,
VAR3 ,
VAR5 ,
VAR4,
VAR8,
VAR2 ,
VAR1
);
output VAR7 ;
input VAR3 ;
input VAR5 ;
input VAR4;
input VAR8;
input VAR2 ;
input VAR1 ;
VAR6 VAR9 (
.VAR7(VAR7),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR7,
VAR3,
VAR5
);
output VAR7;
... | apache-2.0 |
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