repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
peteasa/parallella-fpga | AdaptevaLib/elink-gold/fifo_mem.v | 1,513 | module MODULE1 (
VAR5,
VAR9, VAR4, VAR6, VAR2, VAR3
);
parameter VAR8 = 104;
parameter VAR10 = 2;
localparam VAR1 = 1<<VAR10;
input VAR9; input VAR4;
input [VAR8-1:0] VAR6;
input [VAR10-1:0] VAR2;
input [VAR10-1:0] VAR3;
output [VAR8-1:0] VAR5;
reg [VAR8-1:0] VAR7[VAR1-1:0];
always @(posedge VAR9)
if(VAR4)
VAR7[VAR2[VA... | lgpl-3.0 |
deepakcu/maestro | fpga/DE4_Ethernet_0/src/jtag_bus.v | 8,608 | module MODULE1
parameter VAR28 = 27,
parameter VAR45 = 32
)
(
input VAR23,
input VAR9,
input [VAR28-1:0] VAR48,
input [VAR45-1:0] VAR44,
output wire [VAR45-1:0] VAR10,
output reg VAR13,
output VAR49,
output VAR57, input VAR29,
output wire VAR4,
output [VAR28-1:0] VAR3,
output [VAR45-1:0] VAR8,
input wire [VAR45-1:0] VA... | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/sync_gray.v | 4,188 | module MODULE1 (
input VAR3,
input VAR6,
input [VAR17-1:0] VAR2,
input VAR5,
input VAR15,
output [VAR17-1:0] VAR1
);
parameter VAR17 = 1;
parameter VAR4 = 1;
reg [VAR17-1:0] VAR7 = 'h0;
reg [VAR17-1:0] VAR16 = 'h0;
reg [VAR17-1:0] VAR9 = 'h0;
reg [VAR17-1:0] VAR14 = 'h0;
function [VAR17-1:0] VAR10;
input [VAR17-1:0] VA... | mit |
erkyrath/linguist | samples/Verilog/ram.v | 2,498 | module MODULE1 (
input wire [31:0] addr, VAR8,
input wire VAR12,
input wire [1:0] VAR5,
output wire [31:0] VAR2,
input wire VAR1, reset
);
reg [7:0] VAR9 [VAR10-1:0];
always @(posedge VAR1) begin
if (reset) begin : rst
integer VAR4;
for (VAR4 = 0; VAR4 < VAR10; VAR4 = VAR4 + 1) begin
VAR9[VAR4] <= 0;
end
end
else if (V... | mit |
csturton/wirepatch | system/hardware/cores/bench/or1200_monitor.v | 56,555 | module MODULE1;
integer VAR2;
integer VAR7;
reg [23:0] ref;
integer VAR5;
integer VAR1;
integer VAR4;
integer VAR6;
integer VAR3;
begin
begin
begin
end
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor2b/sky130_fd_sc_hdll__nor2b_4.v | 2,189 | module MODULE2 (
VAR9 ,
VAR7 ,
VAR8 ,
VAR5,
VAR2,
VAR4 ,
VAR3
);
output VAR9 ;
input VAR7 ;
input VAR8 ;
input VAR5;
input VAR2;
input VAR4 ;
input VAR3 ;
VAR6 VAR1 (
.VAR9(VAR9),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR9 ,
VAR7 ,
VAR8
);
output VAR9... | apache-2.0 |
borti4938/sd2snes | verilog/sd2snes_base/address.v | 9,902 | module MODULE1(
input VAR29,
input [15:0] VAR6, input [2:0] VAR28, input [23:0] VAR35, input [7:0] VAR2, input VAR30, output [23:0] VAR17, output VAR3, output VAR13, output VAR15, output VAR19, input [23:0] VAR32,
input [23:0] VAR33,
output VAR39,
output VAR25,
output VAR44,
output VAR36,
input [14:0] VAR10,
output VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o32a/sky130_fd_sc_lp__o32a.behavioral.v | 1,635 | module MODULE1 (
VAR6 ,
VAR3,
VAR2,
VAR12,
VAR9,
VAR8
);
output VAR6 ;
input VAR3;
input VAR2;
input VAR12;
input VAR9;
input VAR8;
supply1 VAR11;
supply0 VAR7;
supply1 VAR1 ;
supply0 VAR15 ;
wire VAR5 ;
wire VAR17 ;
wire VAR10;
or VAR13 (VAR5 , VAR2, VAR3, VAR12 );
or VAR4 (VAR17 , VAR8, VAR9 );
and VAR14 (VAR10, VAR5... | apache-2.0 |
MarcoVogt/basil | firmware/modules/seq_gen/seq_gen.v | 1,533 | module MODULE1
parameter VAR11 = 16'h0000,
parameter VAR7 = 16'h0000,
parameter VAR24 = 16,
parameter VAR25 = 16384,
parameter VAR15 = 16
)(
input wire VAR16,
input wire VAR14,
input wire [VAR24-1:0] VAR22,
inout wire [7:0] VAR3,
input wire VAR2,
input wire VAR17,
input wire VAR19,
input wire VAR8,
output wire [VAR15-1... | bsd-3-clause |
JakeMercer/mac | station_management.v | 5,728 | module MODULE1
parameter VAR7 = 4'd0,
parameter VAR11 = 4'd1,
parameter VAR17 = 4'd2,
parameter VAR12 = 4'd3,
parameter VAR21 = 4'd4,
parameter VAR3 = 4'd5,
parameter VAR30 = 4'd6,
parameter VAR35 = 4'd7,
parameter VAR27 = 4'd8,
parameter VAR23 = 1'b0,
parameter VAR1 = 1'b1
)(
input wire reset,
input wire VAR18,
output... | mit |
zeruniverse/Single-cycle_CPU | ISE project/RegFile.v | 1,063 | module MODULE1 (clk, VAR2, VAR4, VAR5, VAR3, VAR6, VAR7, VAR8, VAR9, VAR10);
input clk,VAR7; input [4:0] VAR5, VAR2, VAR4, VAR3; input [31:0] VAR6; output wire [31:0] VAR8, VAR9, VAR10; reg [31:0] VAR1 [0:31];
assign VAR8=VAR1[VAR2];
assign VAR9=VAR1[VAR4];
assign VAR10=VAR1[VAR5];
always @(posedge clk) begin
if(VAR7) ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_refgen_new/sky130_fd_io__top_refgen_new.pp.symbol.v | 2,534 | module MODULE1 (
input VAR14 ,
inout VAR1 ,
inout VAR13 ,
input VAR10 ,
input VAR22,
input VAR21 ,
input VAR26 ,
input [2:0] VAR4 ,
input [1:0] VAR7 ,
input VAR9 ,
input VAR6 ,
inout VAR15 ,
inout VAR16 ,
inout VAR25 ,
inout VAR24 ,
inout VAR11 ,
inout VAR8 ,
inout VAR18 ,
output VAR12 ,
inout VAR5 ,
input VAR3 ,
outpu... | apache-2.0 |
trander1/Dual-Core-Processor | FinalProjectV3/Modules/arbiter_dualcore.v | 3,261 | module MODULE1(
VAR1, VAR4,
VAR2, VAR5, enable, reset, clk
);
output reg VAR1;
output reg VAR4;
input VAR2; input VAR5; input enable;
input reset;
input clk;
always @(reset) begin
if (reset) begin
end
end
always @*
begin
if(enable)
begin
case ({VAR2,VAR5})
2'b11: begin
VAR1 = VAR6;
VAR4 = VAR3;
end
2'b01: begin
VAR1 = ... | gpl-2.0 |
jacgoudsmit/P8X32A_Emulation | P8X32A_Pipistrello/src/cog_ram.v | 1,397 | module MODULE1
(
input clk,
input VAR6,
input VAR2,
input [8:0] VAR1,
input [31:0] VAR3,
output reg [31:0] VAR4
);
reg [31:0] VAR5 [511:0];
always @(posedge clk)
begin
if (VAR6 && VAR2)
VAR5[VAR1] <= VAR3;
if (VAR6)
VAR4 <= VAR5[VAR1];
end
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor2/sky130_fd_sc_hdll__nor2.behavioral.pp.v | 1,801 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR6 ,
VAR7,
VAR3,
VAR11 ,
VAR2
);
output VAR1 ;
input VAR4 ;
input VAR6 ;
input VAR7;
input VAR3;
input VAR11 ;
input VAR2 ;
wire VAR5 ;
wire VAR9;
nor VAR13 (VAR5 , VAR4, VAR6 );
VAR8 VAR10 (VAR9, VAR5, VAR7, VAR3);
buf VAR12 (VAR1 , VAR9 );
endmodule | apache-2.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_vdma_v6_2/hdl/src/verilog/axi_vdma_v6_2_axis_register_slice_v1_0_axis_register_slice.v | 8,941 | module MODULE1 #
(
parameter VAR55 = "VAR10",
parameter integer VAR26 = 32,
parameter integer VAR17 = 1,
parameter integer VAR5 = 1,
parameter integer VAR21 = 1,
parameter [31:0] VAR13 = 32'hFF,
parameter integer VAR46 = 0
)
(
input wire VAR23,
input wire VAR14,
input wire VAR25,
input wire VAR41,
output wire VAR43,
in... | gpl-3.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/fftTop.v | 4,484 | module MODULE1 (clk,reset,VAR25,VAR16,VAR6,VAR9,VAR19,
VAR29,VAR27,VAR23,VAR18,VAR28, VAR4
);
input clk;
input reset;
input VAR25;
input VAR16;
wire [31:0] VAR30;
output [31:0] VAR6;
input [31:0] VAR9;
output reg VAR19;
input [31:0] VAR29;
input VAR27;
input VAR23;
input [3:0] VAR18;
output VAR28;
output VAR4;
reg VAR8... | gpl-2.0 |
grindars/bfcore | UART.v | 1,463 | module MODULE1(
input VAR9,
input VAR8,
output VAR16,
input VAR14,
input [7:0] VAR12,
output [7:0] VAR1,
output reg VAR13,
input VAR6,
output VAR21,
input VAR24
);
parameter VAR2 = 50000000;
parameter VAR23 = 9600;
wire VAR5, VAR26;
VAR22 #(
.VAR17(VAR2 / (VAR23 * 4))
) VAR18 (
.clk(VAR9),
.rst(VAR8),
.VAR11(VAR14),
.V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor4bb/sky130_fd_sc_hdll__nor4bb.pp.blackbox.v | 1,359 | module MODULE1 (
VAR4 ,
VAR5 ,
VAR2 ,
VAR9 ,
VAR8 ,
VAR7,
VAR3,
VAR1 ,
VAR6
);
output VAR4 ;
input VAR5 ;
input VAR2 ;
input VAR9 ;
input VAR8 ;
input VAR7;
input VAR3;
input VAR1 ;
input VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o31a/sky130_fd_sc_hd__o31a.symbol.v | 1,346 | module MODULE1 (
input VAR6,
input VAR5,
input VAR8,
input VAR7,
output VAR9
);
supply1 VAR3;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlrtp/sky130_fd_sc_hd__dlrtp_4.v | 2,362 | module MODULE1 (
VAR2 ,
VAR7,
VAR8 ,
VAR3 ,
VAR9 ,
VAR5 ,
VAR6 ,
VAR10
);
output VAR2 ;
input VAR7;
input VAR8 ;
input VAR3 ;
input VAR9 ;
input VAR5 ;
input VAR6 ;
input VAR10 ;
VAR1 VAR4 (
.VAR2(VAR2),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR10(VAR10)
);
endmodule
module MODU... | apache-2.0 |
iAklis/teoca | EXPR8/MAIN.v | 5,833 | module MODULE3(
input VAR46,
input VAR39,
input rst,
output [31:0] VAR41
);
wire VAR15, VAR24, VAR27;
wire [31:0] VAR43;
MODULE6 VAR8 (
.clk(VAR46),
.VAR8(VAR39),
.VAR31(VAR15)
);
MODULE1 VAR47 (
.clk(VAR15),
.rst(rst),
.VAR43(VAR43),
.VAR49(VAR24),
.VAR19(VAR27)
);
assign VAR41 = VAR43;
endmodule
module MODULE4(
input... | mit |
rohit91/novena-sd-fpga | novena-sd.srcs/sources_1/ip/mig_v3_91_0/ddr3_if/user_design/rtl/mcb_controller/mcb_soft_calibration.v | 67,851 | module MODULE1 # (
parameter VAR130 = 10'd512, parameter VAR175 = "VAR279", parameter VAR18 = "VAR163", parameter VAR188 = 1'b0, parameter VAR58 = 1'b0, parameter VAR70 = 1'b1, parameter VAR100 = "VAR211"
)
(
input wire VAR153, input wire VAR244, output reg VAR206,
input wire VAR85, input wire VAR73,
input wire VAR61,
... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_2.functional.v | 1,728 | module MODULE1( VAR16, VAR6, VAR9, VAR20, VAR21, VAR22, VAR5 );
input VAR20, VAR9, VAR21, VAR16, VAR6, VAR5;
output VAR22;
not VAR2( VAR26, VAR21 );
wire VAR23;
not VAR18( VAR23, VAR9 );
wire VAR15;
not VAR12( VAR15, VAR16 );
wire VAR14;
and VAR13( VAR14, VAR23, VAR15 );
wire VAR3;
not VAR19( VAR3, VAR6 );
wire VAR4;
a... | apache-2.0 |
lab1-ufba/Genius | rom_dispv.v | 6,419 | module MODULE1 (
address,
VAR5,
VAR27);
input [5:0] address;
input VAR5;
output [5:0] VAR27;
tri1 VAR5;
wire [5:0] VAR42;
wire [5:0] VAR27 = VAR42[5:0];
VAR51 VAR37 (
.VAR34 (address),
.VAR50 (VAR5),
.VAR49 (VAR42),
.VAR44 (1'b0),
.VAR6 (1'b0),
.VAR23 (1'b1),
.VAR41 (1'b0),
.VAR15 (1'b0),
.VAR2 (1'b1),
.VAR25 (1'b1),
.... | gpl-3.0 |
ptracton/vscale_soc | rtl/wb_riscvscale/vscale_ctrl.v | 20,393 | module MODULE1(
input clk,
input reset,
input [VAR68-1:0] VAR40,
input VAR119,
input VAR91,
input VAR141,
input VAR105,
input VAR125,
input [VAR4-1:0] VAR44,
output reg [VAR33-1:0] VAR31,
output reg [VAR96-1:0] VAR72,
output VAR132,
output VAR63,
output reg [VAR109-1:0] VAR116,
output reg [VAR66-1:0] VAR9,
output reg [... | mit |
kimi-michael/Ring-NoC | build_verilog/mkEhr2BSV.v | 3,738 | module MODULE1(VAR18,
VAR12,
VAR19,
VAR22,
VAR23,
VAR14,
VAR9,
VAR1,
VAR4,
VAR15,
VAR10,
VAR13);
input VAR18;
input VAR12;
input [31 : 0] VAR19;
input VAR22;
output VAR23;
output [31 : 0] VAR14;
output VAR9;
input [31 : 0] VAR1;
input VAR4;
output VAR15;
output [31 : 0] VAR10;
output VAR13;
wire [31 : 0] VAR14, VAR10;
... | gpl-2.0 |
pradeep9676/pradeep_9676 | LZD_8bit.v | 1,685 | module MODULE1( in, out, valid
);
input [7:0]in;
output reg [2:0]out;
output reg valid;
wire VAR2,VAR1;
wire [1:0]VAR4, VAR3;
begin
begin
begin
end
begin
begin | mit |
Koheron/zynq-sdk | fpga/cores/redp_dac_v1_0/redp_dac.v | 1,700 | module MODULE1 #
(
)
(
input VAR17 ,
input VAR7 ,
input VAR25 ,
input VAR19 ,
output [ 14-1: 0] VAR12 , output VAR15 , output VAR8 , output VAR20 , output VAR13 ,
input [ 14-1: 0] VAR4 , input [ 14-1: 0] VAR10
);
reg VAR18 ;
reg [14-1: 0] VAR22 ;
reg [14-1: 0] VAR11 ;
always @(posedge VAR17) begin
VAR22 <= {VAR4[14-1],... | mit |
monotone-RK/FACE | MCSoC-15/16-way_2-parallel/ise/ipcore_dir/dram/user_design/rtl/controller/mig_7series_v1_9_arb_mux.v | 19,702 | module MODULE1 #
(
parameter VAR118 = 100,
parameter VAR62 = "VAR5",
parameter VAR64 = "1T",
parameter VAR67 = 11,
parameter VAR108 = 3,
parameter VAR122 = "8",
parameter VAR101 = 4,
parameter VAR57 = 5,
parameter VAR13 = 5,
parameter VAR60 = 31,
parameter VAR31 = 8,
parameter VAR86 = "VAR45",
parameter VAR52 = "VAR79"... | mit |
hanw/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/sha-256-functions.v | 1,662 | module MODULE5 (VAR2, VAR1);
input [31:0] VAR2;
output [31:0] VAR1;
assign VAR1 = {VAR2[1:0],VAR2[31:2]} ^ {VAR2[12:0],VAR2[31:13]} ^ {VAR2[21:0],VAR2[31:22]};
endmodule
module MODULE1 (VAR2, VAR1);
input [31:0] VAR2;
output [31:0] VAR1;
assign VAR1 = {VAR2[5:0],VAR2[31:6]} ^ {VAR2[10:0],VAR2[31:11]} ^ {VAR2[24:0],VAR2... | gpl-3.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/mc/mc_chroma_filter.v | 3,163 | module MODULE2(
VAR5,
VAR7,
VAR2,
VAR6,
VAR4,
VAR3,
out
);
input [2:0] VAR5,VAR7;
input [VAR12-1:0] VAR2;
input [VAR12-1:0] VAR6;
input [VAR12-1:0] VAR4;
input [VAR12-1:0] VAR3;
output[2*VAR12-1:0] out;
reg signed [2*VAR12-1:0] sum;
reg [VAR12-1: 0] VAR8; wire signed [2*VAR12-1:0] VAR10;
always @ begin
if (((sum+'d32) ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a31oi/sky130_fd_sc_hd__a31oi.behavioral.pp.v | 2,038 | module MODULE1 (
VAR13 ,
VAR16 ,
VAR14 ,
VAR12 ,
VAR7 ,
VAR3,
VAR4,
VAR5 ,
VAR8
);
output VAR13 ;
input VAR16 ;
input VAR14 ;
input VAR12 ;
input VAR7 ;
input VAR3;
input VAR4;
input VAR5 ;
input VAR8 ;
wire VAR9 ;
wire VAR2 ;
wire VAR15;
and VAR1 (VAR9 , VAR12, VAR16, VAR14 );
nor VAR11 (VAR2 , VAR7, VAR9 );
VAR6 VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/o21ai/sky130_fd_sc_hvl__o21ai.behavioral.v | 1,534 | module MODULE1 (
VAR3 ,
VAR12,
VAR8,
VAR5
);
output VAR3 ;
input VAR12;
input VAR8;
input VAR5;
supply1 VAR4;
supply0 VAR7;
supply1 VAR11 ;
supply0 VAR2 ;
wire VAR1 ;
wire VAR10;
or VAR13 (VAR1 , VAR8, VAR12 );
nand VAR9 (VAR10, VAR5, VAR1 );
buf VAR6 (VAR3 , VAR10 );
endmodule | apache-2.0 |
MForever78/CPUFly | src/Top.v | 4,428 | module MODULE1(clk, reset, VAR20, VAR46, VAR70, VAR6, VAR62, VAR81, VAR15, VAR71, VAR60, VAR23);
input clk;
input reset;
input VAR71;
input VAR60;
output [7: 0] VAR20;
output [3: 0] VAR46;
output [2: 0] VAR70, VAR6;
output [1: 0] VAR62;
output VAR81, VAR15;
output [7: 0] VAR23;
reg [5: 0] VAR1 = 0;
always @(posedge clk... | mit |
esonghori/TinyGarbled | circuit_synthesis/matrix_mult/matrix_mult_N_M_0.v | 1,275 | module MODULE1
parameter VAR21=3,
parameter VAR16=32
)
(
clk,
rst,
VAR2,
VAR10,
VAR3
);
input clk,rst;
input[VAR16*VAR21*VAR21-1:0] VAR2;
input[VAR16*VAR21*VAR21-1:0] VAR10;
output[VAR16*VAR21*VAR21-1:0] VAR3;
wire [VAR16-1:0] VAR11[VAR21-1:0][VAR21-1:0];
wire [VAR16-1:0] VAR4[VAR21-1:0][VAR21-1:0];
wire [VAR16-1:0] VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlxtn/sky130_fd_sc_hs__dlxtn.pp.blackbox.v | 1,262 | module MODULE1 (
VAR3 ,
VAR4 ,
VAR1,
VAR5 ,
VAR2
);
output VAR3 ;
input VAR4 ;
input VAR1;
input VAR5 ;
input VAR2 ;
endmodule | apache-2.0 |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_brams_v6.v | 8,451 | module MODULE1
parameter VAR1 = 0,
parameter VAR12 = 1,
parameter VAR7 = 1,
parameter VAR10 = 1,
parameter VAR3 = 1
)
(
input VAR6,
input VAR2,
input VAR9,
input [12:0] VAR11,
input [71:0] VAR4,
input VAR5,
input VAR16,
input [12:0] VAR13,
output [71:0] VAR15
);
localparam VAR14 = (VAR7 > 1) ? 1 : 0;
localparam [6:0] V... | lgpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp1/sdr_lib/adc_interface.v | 4,098 | module MODULE1
(input VAR47, input reset, input enable,
input wire [6:0] VAR41, input wire [31:0] VAR24, input VAR6,
input wire [11:0] VAR30, input wire [11:0] VAR33, input wire [11:0] VAR23, input wire [11:0] VAR53,
output wire [31:0] VAR38, output wire [31:0] VAR50, output wire [31:0] VAR22, output wire [31:0] VAR2,
... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_64.behavioral.pp.v | 1,089 | module MODULE1( VAR4, VAR2 );
inout VAR4, VAR2;
VAR5 VAR1(.VAR4(VAR4),.VAR2(VAR2));
VAR5 VAR3(.VAR4(VAR4),.VAR2(VAR2)); | apache-2.0 |
velizarefremov/MIPS | Part 2/Verilog Code/aluparam.v | 3,808 | module MODULE1
( output [VAR30-1:0] VAR3,
output [15:0] VAR36,
input [VAR30-1:0] VAR25,
input [VAR30-1:0] VAR27,
input [3:0] sel
);
wire [VAR30-1:0] VAR29;
wire [VAR30-1:0] VAR21;
wire [VAR30-1:0] VAR31;
wire [VAR30-1:0] VAR9;
wire [VAR30-1:0] VAR19;
wire [VAR30-2:0] VAR20; wire VAR24;
assign VAR29 = VAR25;
and(VAR36[0... | gpl-2.0 |
jobisoft/jTDC | implementations/jTDC_XC6SLX150_VFB6_Discriminator/jDisc.v | 22,705 | module MODULE1 (
inout wire [31:0] VAR100,
input wire [15:0] VAR1,
input wire VAR133,
input wire VAR165,
output wire VAR72,
input wire VAR201,
inout wire VAR85,
inout wire VAR160,
output wire [7:0] VAR173,
input wire [7:0] VAR15,
input wire [1:0] VAR43,
inout wire [73:0] VAR186,
input wire [3:0] VAR69,
output wire [3:0... | gpl-3.0 |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/system/synthesis/submodules/system_acl_iface_acl_kernel_interface.v | 60,109 | module MODULE1 (
input wire VAR57, input wire VAR76, output wire VAR244, output wire [31:0] VAR186, output wire VAR307, input wire [0:0] VAR118, input wire [31:0] VAR258, input wire [13:0] VAR10, input wire VAR246, input wire VAR225, input wire [3:0] VAR282, input wire VAR36, input wire VAR39, input wire [63:0] VAR239,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/tapvgnd2/sky130_fd_sc_lp__tapvgnd2.blackbox.v | 1,256 | module MODULE1 ();
supply1 VAR3;
supply0 VAR4;
supply1 VAR1 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature_KOA/ecp/ks30.v | 3,222 | module MODULE1(VAR4, VAR2, VAR12);
input wire [29:0] VAR4;
input wire [29:0] VAR2;
output wire [58:0] VAR12;
wire [28:0] VAR7;
wire [28:0] VAR1;
wire [28:0] VAR5;
wire [14:0] VAR8;
wire [14:0] VAR11;
VAR3 VAR9(VAR4[14:0], VAR2[14:0], VAR1);
VAR3 VAR10(VAR4[29:15], VAR2[29:15], VAR7);
assign VAR8[14:0] = VAR4[29:15] ^ V... | gpl-3.0 |
spesialstyrker/boula | gen/PCIe/example_design/PIO_64_TX_ENGINE.v | 9,695 | module MODULE1 #(
parameter VAR17 = 64,
parameter VAR16 = 1,
parameter VAR28 = VAR17 / 8
)(
input clk,
input VAR7,
input VAR14,
output reg [VAR17-1:0] VAR20,
output reg [VAR28-1:0] VAR8,
output reg VAR30,
output reg VAR24,
output VAR36,
input VAR9,
input VAR11,
output reg VAR29,
input [2:0] VAR31,
input VAR6,
input VAR... | gpl-2.0 |
KorotkiyEugene/Netmaker_vc_router_syn_quartus | NW_vc_free_pool.v | 4,728 | module MODULE1 (VAR4, valid,
VAR27, VAR19, VAR10, VAR21, VAR25, VAR2, clk, VAR38);
parameter VAR16 = 4; parameter VAR5 = 4;
parameter VAR29 = 0;
parameter VAR34 = 0;
input VAR24 VAR4;
input valid;
output VAR8 VAR27;
output VAR19;
input VAR10;
input [VAR16-1:0] VAR25;
output [VAR16-1:0] VAR21;
input [VAR16-1:0] VAR2;
in... | gpl-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/controllerHdl_Set_Acceleration.v | 4,881 | module MODULE1
(
VAR13,
reset,
VAR16,
VAR20,
VAR10,
VAR18
);
input VAR13;
input reset;
input VAR16;
input signed [17:0] VAR20; input signed [31:0] VAR10; output signed [17:0] VAR18;
wire signed [31:0] VAR12; wire VAR9;
wire VAR1;
wire VAR25;
wire VAR29;
wire VAR3;
wire VAR32;
reg VAR27;
wire VAR11;
wire VAR30;
wire VAR... | gpl-3.0 |
silent-observer/RCPU | CPU/source/RAM2.v | 1,525 | module MODULE1 (
input wire rst,
input wire clk,
input wire[VAR3-1:0] addr,
input wire[VAR12-1:0] VAR1,
input wire VAR2,
input wire VAR5,
output wire[VAR12-1:0] VAR6,
output reg ready);
parameter VAR3 = 16; parameter VAR12 = 16; parameter VAR7 = 1 << VAR3;
reg[VAR3-1:0] VAR11;
reg[VAR12-1:0] VAR8;
reg VAR4;
reg VAR13;
... | mit |
omicronns/studies-sys-rek | lab4/abc/src/sum/sum.v | 20,318 | module MODULE2 (
clk, VAR208, VAR103, VAR48, VAR27
);
input clk;
input VAR208;
input [11 : 0] VAR103;
input [11 : 0] VAR48;
output [12 : 0] VAR27;
wire \VAR104/VAR2 ;
wire \VAR104/VAR13 ;
wire \VAR104/VAR24 ;
wire \VAR104/VAR49 ;
wire \VAR104/VAR156 ;
wire \VAR104/VAR62 ;
wire \VAR104/VAR203 ;
wire \VAR104/VAR162 ;
wir... | mit |
TierraDelFuego/Open-Source-FPGA-Bitcoin-Miner | projects/X5000_ztexmerge/hdl/jtag_fifo.v | 2,393 | module MODULE1 (
input VAR10,
input [11:0] VAR16,
input VAR5, VAR39,
output [8:0] VAR27,
output VAR31, VAR9
);
wire VAR4, VAR14, VAR19, VAR8, VAR32, VAR15, VAR28, VAR2;
wire VAR21;
VAR30 # (.VAR6(1)) VAR18 (
.VAR22(VAR4),
.VAR11(VAR14),
.VAR26(VAR19),
.VAR1(),
.VAR13(VAR8),
.VAR24(VAR32),
.VAR35(VAR15),
.VAR37(VAR28),
... | gpl-3.0 |
rkrajnc/minimig-mist | rtl/or1200/or1200_spram_2048x32.v | 10,377 | module MODULE1(
VAR1, VAR5, VAR27,
clk, rst, VAR60, VAR31, VAR35, addr, VAR7, VAR63
);
parameter VAR4 = 11;
parameter VAR20 = 32;
input VAR1;
input [VAR49 - 1:0] VAR27;
output VAR5;
input clk; input rst; input VAR60; input VAR31; input VAR35; input [VAR4-1:0] addr; input [VAR20-1:0] VAR7; output [VAR20-1:0] VAR63;
assi... | gpl-3.0 |
firedom/combin-for-FPGA | src/encodeBcd10to4.v | 2,314 | module MODULE1(in, out);
input [0:8]in;
output [0:3]out;
wire VAR29, VAR3, VAR17, VAR10, VAR26, VAR16, VAR27, VAR11, VAR13, VAR20, VAR31, VAR7, VAR25, VAR4;
and
VAR19(VAR29, ~in[0], in[1], in[3], in[5], VAR4),
VAR14(VAR3, ~in[2], in[3], in[5], VAR4),
VAR1(VAR17, ~in[4], in[5], VAR4),
VAR21(VAR10, ~in[6], VAR4),
VAR5(VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfxbp/sky130_fd_sc_lp__dfxbp.behavioral.v | 1,893 | module MODULE1 (
VAR15 ,
VAR4,
VAR3,
VAR8
);
output VAR15 ;
output VAR4;
input VAR3;
input VAR8 ;
supply1 VAR2;
supply0 VAR1;
supply1 VAR13 ;
supply0 VAR14 ;
wire VAR5 ;
reg VAR7 ;
wire VAR6 ;
wire VAR16;
wire VAR12 ;
VAR10 VAR17 (VAR5 , VAR6, VAR16, VAR7, VAR2, VAR1);
assign VAR12 = ( VAR2 === 1'b1 );
buf VAR9 (VAR15 ... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/addh/gf180mcu_fd_sc_mcu9t5v0__addh_1.functional.v | 1,164 | module MODULE1( VAR4, VAR13, VAR5, VAR8 );
input VAR13, VAR5;
output VAR4, VAR8;
and VAR10( VAR4, VAR13, VAR5 );
wire VAR1;
not VAR7( VAR1, VAR5 );
wire VAR11;
and VAR6( VAR11, VAR1, VAR13 );
wire VAR2;
not VAR14( VAR2, VAR13 );
wire VAR12;
and VAR9( VAR12, VAR2, VAR5 );
or VAR3( VAR8, VAR11, VAR12 );
endmodule | apache-2.0 |
jacgoudsmit/P8X32A_Emulation | Altera/dig.v | 4,949 | module MODULE1
(
input VAR38,
output [7:0] VAR12,
input VAR4, input VAR24,
input [31:0] VAR31, output [31:0] VAR17, output [31:0] VAR26,
output [7:0] VAR27 );
parameter VAR39 = 0;
reg [31:0] VAR14;
always @(posedge VAR4)
if (VAR38)
VAR14 <= VAR14 + 1'b1;
reg VAR11;
always @(posedge VAR4 or negedge VAR38)
if (!VAR38)
VA... | gpl-3.0 |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_on_screen_display/rtl/axi_on_screen_display.v | 18,830 | module MODULE1 #(
parameter VAR113 = 12,
parameter VAR157 = 5,
parameter VAR75 = 32,
parameter VAR28 = (VAR75 / 8),
parameter VAR51 = 24,
parameter VAR112 = 1,
parameter VAR128 = 1,
parameter VAR104 = 480,
parameter VAR47 = 272,
parameter VAR63 = 9,
parameter VAR88 = 24,
parameter VAR114 = 24'hFFFFFF,
parameter VAR68 =... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/mux4/sky130_fd_sc_ms__mux4.behavioral.pp.v | 1,983 | module MODULE1 (
VAR10 ,
VAR7 ,
VAR13 ,
VAR5 ,
VAR18 ,
VAR14 ,
VAR4 ,
VAR2,
VAR11,
VAR16 ,
VAR1
);
output VAR10 ;
input VAR7 ;
input VAR13 ;
input VAR5 ;
input VAR18 ;
input VAR14 ;
input VAR4 ;
input VAR2;
input VAR11;
input VAR16 ;
input VAR1 ;
wire VAR3 ;
wire VAR6;
VAR15 VAR8 (VAR3 , VAR7, VAR13, VAR5, VAR18, VAR14... | apache-2.0 |
jeichenhofer/chuck-light | SoC/soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v | 11,404 | module MODULE1(
VAR67,
VAR21,
VAR74,
VAR103,
VAR49,
VAR27,
VAR125,
VAR46,
VAR48,
VAR139,
VAR87,
VAR43,
VAR88,
VAR31,
VAR101,
VAR82,
VAR52,
VAR64,
VAR156,
VAR17,
VAR19,
VAR133,
VAR140,
VAR59,
VAR14,
VAR120,
VAR91,
VAR62,
VAR137,
VAR3,
VAR81,
VAR89,
VAR127,
VAR117,
VAR154,
VAR144,
VAR115,
VAR50,
VAR85,
VAR129,
VAR112,
VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21ai/sky130_fd_sc_lp__o21ai_1.v | 2,261 | module MODULE1 (
VAR4 ,
VAR10 ,
VAR6 ,
VAR8 ,
VAR2,
VAR3,
VAR5 ,
VAR7
);
output VAR4 ;
input VAR10 ;
input VAR6 ;
input VAR8 ;
input VAR2;
input VAR3;
input VAR5 ;
input VAR7 ;
VAR1 VAR9 (
.VAR4(VAR4),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR7(VAR7)
);
endmodule
module MODULE... | apache-2.0 |
olofk/wb_streamer | bench/wb_reader.v | 2,004 | module MODULE1
parameter VAR8 = 32,
parameter VAR12 = 0)
(input wire VAR9,
input wire VAR17,
input wire [VAR10-1:0] VAR1,
input wire [VAR8-1:0] VAR11,
input wire [VAR8/8-1:0] VAR15,
input wire VAR7,
input wire [1:0] VAR39,
input wire [2:0] VAR41,
input wire VAR24,
input wire VAR22,
output wire VAR23,
output wire VAR40,... | lgpl-3.0 |
ckdur/mriscv_vivado_arty | mriscv_vivado.srcs/sources_1/imports/uart/uart.v | 3,541 | module MODULE1 #
(
parameter VAR17 = 8
)
(
input wire clk,
input wire rst,
input wire [VAR17-1:0] VAR12,
input wire VAR24,
output wire VAR4,
output wire [VAR17-1:0] VAR5,
output wire VAR11,
input wire VAR2,
input wire VAR19,
output wire VAR7,
output wire VAR1,
output wire VAR10,
output wire VAR13,
output wire VAR20,
in... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/ad_rst.v | 3,128 | module MODULE1 (
VAR1,
clk,
rst);
input VAR1;
input clk;
output rst;
reg VAR2 = 'd0;
reg rst = 'd0;
always @(posedge clk or posedge VAR1) begin
if (VAR1 == 1'b1) begin
VAR2 <= 1'd1;
rst <= 1'd1;
end else begin
VAR2 <= 1'b0;
rst <= VAR2;
end
end
endmodule | gpl-3.0 |
devinacker/sd2snes | verilog/sd2snes_cx4/main.v | 21,041 | module MODULE1(
input VAR226,
input [23:0] VAR97,
input VAR95,
input VAR229,
input VAR117,
inout [7:0] VAR283,
input VAR215,
input VAR69,
output VAR16,
output VAR268,
output VAR20,
input VAR67,
input [7:0] VAR107,
input VAR123,
input VAR155,
inout [15:0] VAR85,
output [22:0] VAR121,
output VAR157,
output VAR260,
output... | gpl-2.0 |
AntonovAlexander/activecore | designs/rtl/udm/hw/uart_tx.v | 2,028 | module MODULE1
parameter VAR16 = "VAR2"
)
(
input VAR17, VAR13,
input VAR8,
input [7:0] VAR15,
input VAR4,
input [28:0] VAR5,
output reg VAR1,
output reg VAR11
);
reg [7:0] VAR10;
reg [3:0] state;
reg [31:0] VAR6;
reg [2:0] VAR14;
localparam VAR3 = 8'h0;
localparam VAR9 = 8'h1;
localparam VAR12 = 8'h2;
localparam VAR7 ... | apache-2.0 |
dawsonjon/fpu | multiplier/multiplier.v | 6,419 | module MODULE1(
VAR23,
VAR9,
VAR8,
VAR20,
VAR35,
clk,
rst,
VAR10,
VAR7,
VAR18,
VAR34);
input clk;
input rst;
input [31:0] VAR23;
input VAR8;
output VAR18;
input [31:0] VAR9;
input VAR20;
output VAR34;
output [31:0] VAR10;
output VAR7;
input VAR35;
reg VAR39;
reg [31:0] VAR40;
reg VAR4;
reg VAR37;
reg [3:0] state;
param... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand4/sky130_fd_sc_hdll__nand4.functional.pp.v | 1,864 | module MODULE1 (
VAR12 ,
VAR6 ,
VAR13 ,
VAR8 ,
VAR2 ,
VAR11,
VAR3,
VAR14 ,
VAR7
);
output VAR12 ;
input VAR6 ;
input VAR13 ;
input VAR8 ;
input VAR2 ;
input VAR11;
input VAR3;
input VAR14 ;
input VAR7 ;
wire VAR9 ;
wire VAR10;
nand VAR4 (VAR9 , VAR2, VAR8, VAR13, VAR6 );
VAR15 VAR5 (VAR10, VAR9, VAR11, VAR3);
buf VAR1 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and4bb/sky130_fd_sc_lp__and4bb.functional.v | 1,416 | module MODULE1 (
VAR7 ,
VAR9,
VAR1,
VAR4 ,
VAR6
);
output VAR7 ;
input VAR9;
input VAR1;
input VAR4 ;
input VAR6 ;
wire VAR3 ;
wire VAR5;
nor VAR10 (VAR3 , VAR9, VAR1 );
and VAR8 (VAR5, VAR3, VAR4, VAR6 );
buf VAR2 (VAR7 , VAR5 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or4/sky130_fd_sc_ms__or4_2.v | 2,231 | module MODULE1 (
VAR11 ,
VAR9 ,
VAR1 ,
VAR8 ,
VAR6 ,
VAR10,
VAR7,
VAR2 ,
VAR3
);
output VAR11 ;
input VAR9 ;
input VAR1 ;
input VAR8 ;
input VAR6 ;
input VAR10;
input VAR7;
input VAR2 ;
input VAR3 ;
VAR5 VAR4 (
.VAR11(VAR11),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR2(VAR2),
.... | apache-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/cores/wb_altera_ddr_wrapper/rtl/verilog/wb_ddr_ctrl.v | 4,404 | module MODULE1 #(
parameter VAR8 = 25, parameter VAR43 = 3, parameter VAR20 = {3'd3, 3'd3, 3'd3} )
(
input VAR19,
input VAR9,
input [VAR43*32-1:0] VAR57,
input [VAR43-1:0] VAR3,
input [VAR43-1:0] VAR22,
input [VAR43*3-1:0] VAR51,
input [VAR43*2-1:0] VAR49,
input [VAR43-1:0] VAR5,
input [VAR43*4-1:0] VAR36,
input [VAR43... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkinv/sky130_fd_sc_lp__clkinv.pp.symbol.v | 1,264 | module MODULE1 (
input VAR5 ,
output VAR2 ,
input VAR3 ,
input VAR4,
input VAR1,
input VAR6
);
endmodule | apache-2.0 |
SergKolo/msudenver_eet_4020_verilog | proj1_traffic_fsm/traffic_fsm.v | 8,592 | module MODULE1(VAR14,VAR2,VAR20,VAR22,clk);
input clk;
input [4:0] VAR22;
output reg [4:0] VAR2;
output reg [4:0] VAR20;
output [6:0] VAR14;
reg [3:0] state;
parameter VAR1=0,VAR3=1,
VAR10=2,VAR17=3,
VAR18=4,VAR4=5,
VAR13=6,VAR19=7,
VAR8=8;
reg [3:0] VAR16;
wire [3:0] VAR5;
reg VAR11,VAR7,VAR15;
VAR21 VAR6(VAR5,VAR16,c... | mit |
P3Stor/P3Stor | pcie/app/BAR0.v | 41,760 | module MODULE1(
clk,
VAR106,
en,
VAR50,
VAR117,
VAR11,
VAR10,
VAR38,
VAR151,
VAR69,
VAR153,
VAR131,
VAR161,
VAR121,
VAR33,
VAR22,
VAR148,
VAR158,
VAR51,
VAR29,
VAR87,
VAR70,
VAR135,
VAR94,
VAR107,
VAR86,
VAR43,
VAR137,
VAR97,
VAR20,
VAR149,
VAR39,
VAR2,
VAR144,
VAR56,
VAR105,
VAR34,
VAR169,
VAR4,
VAR57,
VAR41,
VAR47,
V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_xres4v2/sky130_fd_io__top_xres4v2.behavioral.pp.v | 7,858 | module MODULE1 ( VAR13, VAR4, VAR25, VAR9,
VAR17, VAR37, VAR1, VAR18, VAR36, VAR6, VAR29, VAR26,
VAR30, VAR14, VAR35
,VAR42, VAR33, VAR34, VAR43,VAR38, VAR8, VAR3, VAR16, VAR15, VAR39
);
output VAR4;
inout VAR17;
inout VAR37;
inout VAR1;
input VAR30;
input VAR36;
input VAR6;
input VAR29;
input VAR26;
inout VAR14;
input... | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/ug871-design-files/Interface_Synthesis/lab3/array_io_prj/solution1/syn/verilog/array_io.v | 6,703 | module MODULE1 (
VAR17,
VAR5,
VAR16,
VAR3,
VAR20,
VAR15,
VAR27,
VAR40,
VAR7,
VAR42,
VAR28,
VAR29,
VAR14
);
parameter VAR41 = 4'd1;
parameter VAR21 = 4'd2;
parameter VAR1 = 4'd4;
parameter VAR33 = 4'd8;
input VAR17;
input VAR5;
input VAR16;
output VAR3;
output VAR20;
output VAR15;
output [4:0] VAR27;
output VAR40;
outpu... | mit |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/tq/premuat3_32.v | 6,886 | module MODULE1(
enable,
VAR10,
VAR36,
VAR3,
VAR37,
VAR12,
VAR32,
VAR35,
VAR13,
VAR9,
VAR19,
VAR21,
VAR25,
VAR22,
VAR20,
VAR26,
VAR6,
VAR24,
VAR34,
VAR39,
VAR14,
VAR1,
VAR38,
VAR33,
VAR28,
VAR8,
VAR11,
VAR15,
VAR2,
VAR16,
VAR27,
VAR31,
VAR29,
VAR18,
o0,
o1,
o2,
o3,
o4,
o5,
o6,
o7,
VAR17,
VAR23,
o10,
o11,
o12,
o13,
o14,
... | gpl-3.0 |
merckhung/zet | cores/vga/rtl/vga_cpu_mem_iface.v | 5,306 | module MODULE1 (
input VAR45,
input VAR3,
input [16:1] VAR11,
input [ 1:0] VAR20,
input VAR36,
input [15:0] VAR34,
output [15:0] VAR17,
input VAR13,
output VAR19,
output [17:1] VAR40,
output [ 1:0] VAR55,
output VAR8,
output [15:0] VAR50,
input [15:0] VAR56,
output VAR2,
input VAR42,
input VAR35,
input VAR39,
input [ 1... | gpl-3.0 |
bigeagle/riffa | fpga/riffa_hdl/tx_engine_ultrascale.v | 11,798 | module MODULE1
parameter VAR19 = 128,
parameter VAR67 = 1,
parameter VAR46 = 0,
parameter VAR64 = 64
)
(
input VAR59,
input VAR77,
input [VAR50-1:0] VAR34,
input VAR24,
output VAR63,
output VAR29,
output [VAR19-1:0] VAR62,
output [(VAR19/32)-1:0] VAR61,
output [VAR45-1:0] VAR66,
input VAR11,
input [VAR19-1:0] VAR41,
in... | bsd-3-clause |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/radio_controller_v1_07_a/hdl/verilog/radio_controller_TxTiming.v | 2,524 | module MODULE1
(
clk,
reset,
VAR9,
VAR3,
VAR2,
VAR16,
VAR4,
VAR12,
VAR11,
VAR6,
VAR5,
VAR1,
VAR10,
VAR14
);
input clk;
input reset;
input VAR9;
input [0:5] VAR3;
input [0:3] VAR2;
input [0:3] VAR16;
input [0:7] VAR4;
input [0:7] VAR12;
input [0:7] VAR11;
input [0:7] VAR6;
output VAR5;
output VAR14;
output VAR10;
output... | bsd-2-clause |
martinmiranda14/Digitales | Lab_6/project_5/project_5.srcs/sources_1/new/Amm.v | 1,559 | module MODULE1(
input [3:0] VAR2,
output reg [7:0] VAR1
);
always @(*) begin
case(VAR2)
4'd0: VAR1=8'b00000011;
4'd1: VAR1=8'b10011111;
4'd2: VAR1=8'b00100101;
4'd3: VAR1=8'b00001101;
4'd4: VAR1=8'b10011001;
4'd5: VAR1=8'b01001001;
4'd6: VAR1=8'b01000001;
4'd7: VAR1=8'b00011111;
4'd8: VAR1=8'b00000001;
4'd9: VAR1=8'b00... | apache-2.0 |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_seeed_tft/rtl/seeed_tft_command.v | 2,722 | module MODULE1 (
input rst,
input clk,
output [31:0] VAR1,
input VAR9,
input VAR6,
input [7:0] VAR4,
output reg [7:0] VAR15,
input VAR10,
input VAR11,
output reg VAR18,
output VAR5,
output reg VAR12,
output reg VAR16,
output reg [7:0] VAR2,
input [7:0] VAR13,
output reg VAR3
);
localparam VAR14 = 4'h0;
localparam VAR8 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inputiso1n/sky130_fd_sc_hdll__inputiso1n.symbol.v | 1,397 | module MODULE1 (
input VAR3 ,
output VAR4 ,
input VAR6
);
supply1 VAR7;
supply0 VAR2;
supply1 VAR1 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a222oi/sky130_fd_sc_hs__a222oi.behavioral.pp.v | 2,316 | module MODULE1 (
VAR18 ,
VAR14 ,
VAR4 ,
VAR17 ,
VAR15 ,
VAR6 ,
VAR11 ,
VAR19,
VAR1
);
output VAR18 ;
input VAR14 ;
input VAR4 ;
input VAR17 ;
input VAR15 ;
input VAR6 ;
input VAR11 ;
input VAR19;
input VAR1;
wire VAR15 VAR21 ;
wire VAR15 VAR9 ;
wire VAR15 VAR8 ;
wire VAR3 ;
wire VAR5;
nand VAR20 (VAR21 , VAR4, VAR14 );... | apache-2.0 |
Proxmark/proxmark3 | fpga/min_max_tracker.v | 1,988 | module MODULE1(input clk, input [7:0] VAR1, input [7:0] VAR7,
output [7:0] VAR5, output [7:0] VAR4);
reg [7:0] VAR2 = 255;
reg [7:0] VAR6 = 0;
reg [7:0] VAR8 = 255;
reg [7:0] VAR3 = 0;
reg [1:0] state = 0;
always @(posedge clk)
begin
case (state)
0: begin
if (VAR3 >= ({1'b0, VAR1} + VAR7))
state <= 2;
end
else if (VAR1... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/xor3/sky130_fd_sc_ms__xor3.functional.pp.v | 1,845 | module MODULE1 (
VAR8 ,
VAR7 ,
VAR14 ,
VAR1 ,
VAR3,
VAR11,
VAR12 ,
VAR9
);
output VAR8 ;
input VAR7 ;
input VAR14 ;
input VAR1 ;
input VAR3;
input VAR11;
input VAR12 ;
input VAR9 ;
wire VAR10 ;
wire VAR6;
xor VAR4 (VAR10 , VAR7, VAR14, VAR1 );
VAR2 VAR13 (VAR6, VAR10, VAR3, VAR11);
buf VAR5 (VAR8 , VAR6 );
endmodule | apache-2.0 |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/Source/IP/FIFO_SUM_IN_SQUARED/FIFO_SUM_IN_SQUARED_bb.v | 5,520 | module MODULE1 (
VAR6,
VAR5,
VAR7,
VAR8,
VAR1,
VAR2,
VAR3,
VAR4);
input VAR6;
input [25:0] VAR5;
input VAR7;
input VAR8;
input VAR1;
output VAR2;
output VAR3;
output [25:0] VAR4;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/probec_p/sky130_fd_sc_hdll__probec_p.functional.v | 1,277 | module MODULE1 (
VAR3,
VAR4
);
output VAR3;
input VAR4;
wire VAR2;
buf VAR1 (VAR2, VAR4 );
buf VAR5 (VAR3 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ls__udp_dff_nsr_pp_pg_n.symbol.v | 1,655 | module MODULE1 (
input VAR2 ,
output VAR8 ,
input VAR5 ,
input VAR7 ,
input VAR1 ,
input VAR4,
input VAR6 ,
input VAR3
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi22/gf180mcu_fd_sc_mcu9t5v0__aoi22_2.functional.pp.v | 1,804 | module MODULE1( VAR1, VAR8, VAR21, VAR11, VAR6, VAR5, VAR24 );
input VAR6, VAR11, VAR8, VAR1;
inout VAR5, VAR24;
output VAR21;
wire VAR16;
not VAR12( VAR16, VAR6 );
wire VAR7;
not VAR9( VAR7, VAR8 );
wire VAR19;
and VAR18( VAR19, VAR16, VAR7 );
wire VAR3;
not VAR14( VAR3, VAR1 );
wire VAR15;
and VAR10( VAR15, VAR16, VA... | apache-2.0 |
Digilent/vivado-library | ip/MotorFeedback_1.0/hdl/MotorFeedback_v1_0_S00_AXI.v | 16,352 | module MODULE1 #
(
parameter integer VAR7 = 32,
parameter integer VAR17 = 5
)
(
input wire VAR18,
input wire VAR61,
input wire VAR13,
input wire VAR2,
input wire [VAR17-1 : 0] VAR55,
input wire [2 : 0] VAR52,
input wire VAR60,
output wire VAR40,
input wire [VAR7-1 : 0] VAR47,
input wire [(VAR7/8)-1 : 0] VAR44,
input wi... | mit |
mammenx/synesthesia_moksha | wxp/dgn/rtl/altera/lpddr2_cntrlr/lpddr2_cntrlr/lpddr2_cntrlr_p0_acv_hard_memphy.v | 28,427 | module MODULE1 (
VAR190,
VAR130,
VAR36,
VAR110,
VAR164,
VAR8,
VAR206,
VAR136,
VAR69,
VAR52,
VAR67,
VAR241,
VAR231,
VAR227,
VAR170,
VAR127,
VAR185,
VAR38,
VAR200,
VAR42,
VAR101,
VAR162,
VAR48,
VAR184,
VAR5,
VAR39,
VAR175,
VAR55,
VAR94,
VAR237,
VAR22,
VAR57,
VAR197,
VAR96,
VAR156,
VAR254,
VAR132,
VAR117,
VAR177,
VAR160,
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a21bo/sky130_fd_sc_hs__a21bo_4.v | 2,191 | module MODULE2 (
VAR7 ,
VAR5 ,
VAR2 ,
VAR3,
VAR1,
VAR8
);
output VAR7 ;
input VAR5 ;
input VAR2 ;
input VAR3;
input VAR1;
input VAR8;
VAR4 VAR6 (
.VAR7(VAR7),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR7 ,
VAR5 ,
VAR2 ,
VAR3
);
output VAR7 ;
input VAR5 ;
input VAR2 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/invlp/sky130_fd_sc_lp__invlp.pp.blackbox.v | 1,245 | module MODULE1 (
VAR6 ,
VAR1 ,
VAR5,
VAR2,
VAR3 ,
VAR4
);
output VAR6 ;
input VAR1 ;
input VAR5;
input VAR2;
input VAR3 ;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | models/udp_dff_p_pp_pg_n/sky130_fd_sc_ms__udp_dff_p_pp_pg_n.blackbox.v | 1,395 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR5 ,
VAR2,
VAR6 ,
VAR4
);
output VAR3 ;
input VAR1 ;
input VAR5 ;
input VAR2;
input VAR6 ;
input VAR4 ;
endmodule | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_097.v | 1,555 | module MODULE1 (
VAR8,
VAR5
);
input [31:0] VAR8;
output [31:0]
VAR5;
wire [31:0]
VAR6,
VAR15,
VAR4,
VAR12,
VAR1,
VAR13,
VAR10,
VAR7,
VAR14,
VAR3;
assign VAR6 = VAR8;
assign VAR3 = VAR14 << 1;
assign VAR7 = VAR4 << 8;
assign VAR14 = VAR10 - VAR7;
assign VAR4 = VAR15 - VAR6;
assign VAR10 = VAR1 - VAR13;
assign VAR15 = V... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/reg_based_cam.v | 2,937 | module MODULE1 (
clk,rst,
VAR11,VAR14,VAR9,VAR3,
VAR17,VAR5
);
parameter VAR8 = 32;
parameter VAR1 = 4;
parameter VAR13 = (1<<VAR1);
input clk,rst;
input [VAR1-1:0] VAR11;
input [VAR8-1:0] VAR14,VAR9;
input VAR3;
input [VAR8-1:0] VAR17;
output [VAR13-1:0] VAR5;
wire [VAR13-1:0] VAR5;
wire [VAR13-1:0] VAR6;
reg [VAR13-1... | mit |
mashanz/FinalProject | Code/lib/alu_8bit.v | 9,149 | module MODULE1( reset, VAR1, enable, VAR6, VAR5, VAR7, VAR8, VAR9, VAR3);
input reset, VAR1, enable;
output VAR3;
input [1:0]VAR6;
input [7:0]VAR7,VAR8;
input [7:0]VAR9;
output [7:0]VAR5;
reg [7:0]VAR5;
integer VAR4;
always@(VAR9,VAR7,VAR8)
begin
case(VAR9)
8'b00000000:
begin
end
8'b00000001: VAR5 <= VAR7-VAR8;
8'b000... | gpl-3.0 |
archlabo/Frix | fpga/de2-115/rtl/soc.v | 5,402 | module MODULE1(
input wire VAR9,
input wire [3:0] VAR22,
output wire [12:0] VAR62,
output wire [1:0] VAR42,
output wire VAR19,
output wire VAR57,
output wire VAR59,
output wire VAR38,
inout wire [31:0] VAR45,
output wire [3:0] VAR34,
output wire VAR64,
output wire VAR58,
inout wire VAR32,
inout wire VAR11,
output wire ... | bsd-2-clause |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/example_project/ddr3_s4_uniphy_example/submodules/altera_reset_synchronizer.v | 3,475 | module MODULE1
parameter VAR6 = 1,
parameter VAR1 = 2
)
(
input VAR4 ,
input clk,
output VAR2
);
reg [VAR1-1:0] VAR3;
reg VAR5;
generate if (VAR6) begin
always @(posedge clk or posedge VAR4) begin
if (VAR4) begin
VAR3 <= {VAR1{1'b1}};
VAR5 <= 1'b1;
end
else begin
VAR3[VAR1-2:0] <= VAR3[VAR1-1:1];
VAR3[VAR1-1] <= 0;
VAR... | lgpl-3.0 |
tuura/workcraft | ci/import-circuit/hier_buck_control.v | 3,717 | module MODULE2 (VAR90, VAR47, VAR21, VAR35, VAR18, VAR32, VAR74);
input VAR90, VAR47, VAR21, VAR35, VAR32;
output VAR18, VAR74;
wire VAR9, VAR11;
MODULE4 MODULE1 (.VAR18(VAR18), .VAR74(VAR74), .VAR35(VAR35), .VAR32(VAR32), .VAR88(VAR11), .VAR47(VAR47), .VAR21(VAR21), .VAR67(VAR9));
MODULE5 MODULE2 (.VAR88(VAR11), .VAR6... | mit |
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