repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o211ai/sky130_fd_sc_hs__o211ai_4.v | 2,234 | module MODULE2 (
VAR6 ,
VAR8 ,
VAR9 ,
VAR1 ,
VAR7 ,
VAR5,
VAR3
);
output VAR6 ;
input VAR8 ;
input VAR9 ;
input VAR1 ;
input VAR7 ;
input VAR5;
input VAR3;
VAR4 VAR2 (
.VAR6(VAR6),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR6 ,
VAR8,
VAR9,
VAR1,
VAR7
);... | apache-2.0 |
marmolejo/zet | cores/fmlbrg/rtl/fmlbrg.v | 11,811 | module MODULE1 #(
parameter VAR36 = 23,
parameter VAR38 = 9 ) (
input VAR25,
input VAR52,
input [VAR36-1:1] VAR13,
input [2:0] VAR50,
input [15:0] VAR63,
output [15:0] VAR95,
input [1:0] VAR48,
input VAR100,
input VAR94,
input VAR65,
input VAR69,
output reg VAR44,
output reg [VAR36-1:0] VAR17,
output reg VAR96,
output ... | gpl-3.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/systems/or1200-generic/bench/verilog/wb_intercon.v | 9,871 | module MODULE1
(input VAR35,
input VAR21,
input [31:0] VAR42,
input [31:0] VAR50,
input [3:0] VAR127,
input VAR12,
input VAR138,
input VAR33,
input [2:0] VAR16,
input [1:0] VAR89,
output [31:0] VAR34,
output VAR125,
output VAR128,
output VAR114,
input [31:0] VAR36,
input [31:0] VAR106,
input [3:0] VAR3,
input VAR124,
i... | gpl-2.0 |
megari/sd2snes | verilog/sd2snes_obc1/main.v | 19,334 | module MODULE1(
input VAR62,
input [23:0] VAR212,
input VAR143,
input VAR174,
input VAR103,
inout [7:0] VAR70,
input VAR116,
input VAR36,
output VAR43,
output VAR24,
output VAR158,
input VAR282,
input [7:0] VAR99,
input VAR50,
input VAR286,
inout [15:0] VAR123,
output [22:0] VAR193,
output VAR241,
output VAR219,
output... | gpl-2.0 |
Triple-Z/COExperiment_Repo | Project_Assignment/datapath/alu.v | 1,100 | module MODULE1 (VAR4, VAR1, VAR5, VAR6, clk);
input [3:0] VAR4;
input [31:0] VAR1, VAR5;
input clk;
output reg [31:0] VAR6;
reg [63:0] VAR7;
reg [31:0] VAR3, VAR2; | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi.functional.pp.v | 2,245 | module MODULE1 (
VAR7 ,
VAR15,
VAR17,
VAR9 ,
VAR6 ,
VAR8,
VAR12,
VAR3 ,
VAR2
);
output VAR7 ;
input VAR15;
input VAR17;
input VAR9 ;
input VAR6 ;
input VAR8;
input VAR12;
input VAR3 ;
input VAR2 ;
wire VAR5 ;
wire VAR10 ;
wire VAR19 ;
wire VAR1;
and VAR4 (VAR5 , VAR9, VAR6 );
nor VAR16 (VAR10 , VAR15, VAR17 );
nor VAR1... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/cmp/rtl/dram_ddr_pad_rptr.v | 4,418 | module MODULE1(
VAR16, VAR34, VAR27,
VAR11, VAR5, VAR8,
VAR35, VAR12,
VAR36, VAR33,
VAR31, VAR30, VAR20,
VAR13, VAR23, VAR17,
VAR32, VAR14,
VAR1, VAR21, VAR6,
VAR7, VAR3, VAR10,
VAR29, VAR26, VAR18,
VAR25, VAR22, VAR24,
VAR4, VAR9, VAR2, VAR28,
VAR19, VAR15
);
output VAR16;
output [31:0] VAR34;
output [255:0] VAR27;
ou... | gpl-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_amphy/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v | 47,980 | module MODULE1 #
( parameter
VAR61 = 80,
VAR129 = 32,
VAR59 = 2,
VAR54 = 40,
VAR15 = 5,
VAR119 = 8,
VAR70 = 1,
VAR132 = 0,
VAR10 = 0,
VAR79 = 0,
VAR83 = 8,
VAR50 = 1,
VAR19 = 1,
VAR120 = 1,
VAR78 = 1,
VAR26 = 1,
VAR1 = 1,
VAR65 = 1,
VAR8 = 1,
VAR100 = 1,
VAR4 = 1,
VAR121 = 8,
VAR17 = 8,
VAR53 = 1,
VAR39 = 8
)
(
VAR76,
... | lgpl-3.0 |
binderclip/BCOpenMIPS | cpu-code/id_ex.v | 2,969 | module MODULE1 (
input wire clk,
input wire rst,
input wire[VAR36] VAR6,
input wire[VAR16] VAR1,
input wire[VAR29] VAR4,
input wire[VAR29] VAR41,
input wire[VAR21] VAR40,
input wire VAR7,
input wire[5:0] VAR8,
input wire VAR39,
input wire[VAR29] VAR31,
input wire VAR20,
input wire VAR22,
input wire[VAR29] VAR42,
input ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlygate4sd1/sky130_fd_sc_hdll__dlygate4sd1.functional.v | 1,317 | module MODULE1 (
VAR1,
VAR5
);
output VAR1;
input VAR5;
wire VAR2;
buf VAR3 (VAR2, VAR5 );
buf VAR4 (VAR1 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/inv/sky130_fd_sc_ms__inv_16.v | 2,001 | module MODULE2 (
VAR4 ,
VAR3 ,
VAR7,
VAR8,
VAR5 ,
VAR1
);
output VAR4 ;
input VAR3 ;
input VAR7;
input VAR8;
input VAR5 ;
input VAR1 ;
VAR2 VAR6 (
.VAR4(VAR4),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR4,
VAR3
);
output VAR4;
input VAR3;
supply1 VAR7;
supply0 VAR8;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfxbp/sky130_fd_sc_hd__dfxbp.pp.symbol.v | 1,336 | module MODULE1 (
input VAR6 ,
output VAR5 ,
output VAR4 ,
input VAR3 ,
input VAR1 ,
input VAR2,
input VAR7,
input VAR8
);
endmodule | apache-2.0 |
alexforencich/xfcp | lib/eth/example/DE5-Net/fpga/cores/phy.v | 14,610 | module MODULE1 (
input wire VAR65, output wire VAR75, output wire VAR79, output wire VAR50, input wire VAR72, output wire VAR58, output wire [3:0] VAR5, output wire [71:0] VAR63, input wire VAR23, output wire [71:0] VAR32, input wire VAR46, output wire [71:0] VAR2, input wire VAR62, output wire [71:0] VAR27, input wire... | mit |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_wbmux.v | 5,916 | module MODULE1(
clk, rst,
VAR11, VAR4,
VAR13, VAR3, VAR9, VAR2,
VAR7, VAR8, VAR1
);
parameter VAR5 = VAR6;
input clk;
input rst;
input VAR11;
input [VAR10-1:0] VAR4;
input [VAR5-1:0] VAR13;
input [VAR5-1:0] VAR3;
input [VAR5-1:0] VAR9;
input [VAR5-1:0] VAR2;
output [VAR5-1:0] VAR7;
output [VAR5-1:0] VAR8;
output VAR1;
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr_1.v | 2,290 | module MODULE2 (
VAR7 ,
VAR3 ,
VAR6 ,
VAR4 ,
VAR5,
VAR8 ,
VAR9
);
output VAR7 ;
input VAR3 ;
input VAR6 ;
input VAR4 ;
input VAR5;
input VAR8 ;
input VAR9 ;
VAR2 VAR1 (
.VAR7(VAR7),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR9(VAR9)
);
endmodule
module MODULE2 (
VAR7,
VAR3
);
output VAR7;
inpu... | apache-2.0 |
efabless/openlane | designs/aes_cipher/src/aes_rcon.v | 3,773 | module MODULE1(clk, VAR3, out);
input clk;
input VAR3;
output [31:0] out;
reg [31:0] out;
reg [3:0] VAR4;
wire [3:0] VAR2;
always @(posedge clk)
if(VAR3) out <= 32'h01000000;
else out <= VAR1(VAR2);
assign VAR2 = VAR4 + 4'h1;
always @(posedge clk)
if(VAR3) VAR4 <= 4'h0;
else VAR4 <= VAR2;
function [31:0] VAR1;
input [3... | apache-2.0 |
trivoldus28/pulsarch-verilog | verif/env/cmp/cmp_dram_mon.v | 5,776 | module MODULE1(
clk, VAR3, VAR12, VAR10,
VAR16, VAR1
);
input clk;
input [1:0] VAR3;
input [1:0] VAR12;
input [1:0] VAR10;
input [1:0] VAR16;
input VAR1;
reg[2:0] VAR11, VAR13, VAR14, VAR18, VAR7, VAR17, VAR9, VAR5;
reg VAR20, VAR15, VAR4, VAR8, VAR21, VAR19, VAR6, VAR2;
begin | gpl-2.0 |
TheMadSocrates/vercpu-project | rtl/core/ALU.v | 3,206 | module MODULE1 #(parameter VAR14=8) (
input wire [VAR14 - 1 : 0] VAR15,
input wire [VAR14 - 1 : 0] VAR12,
input wire [VAR2 - 1: 0] VAR16,
input wire [VAR4 - 1 : 0] VAR7,
output wire [VAR14 - 1 : 0] VAR17,
output wire [VAR4 - 1 : 0] VAR6
);
reg [VAR4 - 1 : 0] VAR5;
reg [VAR14 - 1 : 0] VAR3;
wire VAR1, VAR13, VAR9;
assig... | gpl-3.0 |
jeffkub/n64-cart-reader | old/n64cartridge/src/sdram/delay_gen150us.v | 2,574 | module MODULE1 (
VAR5,
VAR8, VAR7
);
input VAR7; input VAR8; output VAR5; wire VAR4;
VAR1 VAR3(
.VAR6 (VAR4),
.VAR7 (VAR7),
.VAR8 (VAR8));
VAR2 VAR9(
.VAR5 (VAR5),
.VAR7 (VAR4),
.VAR8 (VAR8));
endmodule | mit |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/engine_layer.v | 28,212 | module MODULE1
parameter VAR54=6,
parameter VAR71 = 1,
parameter VAR142 = 0,
parameter VAR8 = 64,
parameter VAR77="VAR102")
( input VAR139,
input VAR149, input VAR73, output VAR119,
output VAR27,
output VAR118,
output VAR70,
input [VAR20-1:0] VAR61,
input [VAR66-1:0] VAR132,
input VAR103,
input VAR93,
input [VAR156-1:0... | gpl-3.0 |
freecores/orsoc_graphics_accelerator | rtl/verilog/gfx/gfx_color.v | 3,295 | module MODULE2(VAR5, VAR7, VAR2,
VAR8, VAR6);
input [1:0] VAR5;
input [31:0] VAR7;
input [1:0] VAR2;
output [31:0] VAR8;
output [3:0] VAR6;
assign VAR6 = (VAR5 == 2'b00) && (VAR2 == 2'b00) ? 4'b1000 : (VAR5 == 2'b00) && (VAR2 == 2'b01) ? 4'b0100 : (VAR5 == 2'b00) && (VAR2 == 2'b10) ? 4'b0010 : (VAR5 == 2'b00) && (VAR2 ... | gpl-3.0 |
cpulabs/mist1032sa | src/core/decode/decode_function.v | 173,265 | module MODULE1(
input wire [31:0] VAR19,
output wire VAR27,
output wire VAR33,
output wire VAR1,
output wire VAR5,
output wire VAR12,
output wire VAR18,
output wire VAR30,
output wire VAR35,
output wire VAR10,
output wire VAR2,
output wire VAR16,
output wire VAR34,
output wire VAR23,
output wire [4:0] VAR22,
output wir... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or2/sky130_fd_sc_hdll__or2.functional.v | 1,252 | module MODULE1 (
VAR6,
VAR2,
VAR5
);
output VAR6;
input VAR2;
input VAR5;
wire VAR3;
or VAR1 (VAR3, VAR5, VAR2 );
buf VAR4 (VAR6 , VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o221ai/sky130_fd_sc_lp__o221ai.pp.blackbox.v | 1,436 | module MODULE1 (
VAR7 ,
VAR10 ,
VAR2 ,
VAR6 ,
VAR8 ,
VAR9 ,
VAR5,
VAR3,
VAR1 ,
VAR4
);
output VAR7 ;
input VAR10 ;
input VAR2 ;
input VAR6 ;
input VAR8 ;
input VAR9 ;
input VAR5;
input VAR3;
input VAR1 ;
input VAR4 ;
endmodule | apache-2.0 |
sh-chris110/chris | FPGA/chris.final/Qsys/soc_design/synthesis/submodules/soc_design_system_pll.v | 2,153 | module MODULE1(
input wire VAR62,
input wire rst,
output wire VAR1,
output wire VAR44,
output wire VAR16
);
VAR17 #(
.VAR50("false"),
.VAR31("50.0 VAR72"),
.VAR39("VAR9"),
.VAR23(2),
.VAR27("100.000000 VAR72"),
.VAR70("0 VAR30"),
.VAR36(50),
.VAR63("100.000000 VAR72"),
.VAR45("8250 VAR30"),
.VAR53(50),
.VAR65("0 VAR72"... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlygate4sd1/sky130_fd_sc_hs__dlygate4sd1.functional.v | 1,724 | module MODULE1 (
VAR9 ,
VAR10 ,
VAR8,
VAR7
);
output VAR9 ;
input VAR10 ;
input VAR8;
input VAR7;
wire VAR1 ;
wire VAR2;
buf VAR3 (VAR1 , VAR10 );
VAR6 VAR5 (VAR2, VAR1, VAR8, VAR7);
buf VAR4 (VAR9 , VAR2 );
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9467/axi_ad9467.v | 9,653 | module MODULE1(
VAR45,
VAR53,
VAR49,
VAR108,
VAR82,
VAR33,
VAR32,
VAR29,
VAR61,
VAR130,
VAR25,
VAR74,
VAR114,
VAR92,
VAR42,
VAR51,
VAR69,
VAR13,
VAR6,
VAR3,
VAR123,
VAR10,
VAR37,
VAR116,
VAR84,
VAR24,
VAR112,
VAR57,
VAR39,
VAR79,
VAR7,
VAR75);
parameter VAR86 = 0;
parameter VAR12 = 0;
parameter VAR18 = "VAR58";
input V... | gpl-3.0 |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Mux2x1_10_0_0/RAT_Mux2x1_10_0_0_stub.v | 1,280 | module MODULE1(VAR3, VAR1, VAR4, VAR2)
;
input [9:0]VAR3;
input [9:0]VAR1;
input VAR4;
output [9:0]VAR2;
endmodule | mit |
bluespec/Flute | src_bsc_lib_RTL/main.v | 3,637 | module MODULE1();
reg VAR2;
reg VAR4;
reg [31:0] VAR8;
reg VAR7;
reg VAR6;
reg VAR3;
reg VAR1;
reg [8*256:1] VAR5;
begin | apache-2.0 |
Anirudh94/Connect4-FPGA | Connect4/vga_adapter/vga_address_translator.v | 1,575 | module MODULE1(VAR6, VAR2, VAR1);
parameter VAR3 = "320x240";
input [((VAR3 == "320x240") ? (8) : (7)):0] VAR6;
input [((VAR3 == "320x240") ? (7) : (6)):0] VAR2;
output reg [((VAR3 == "320x240") ? (16) : (14)):0] VAR1;
wire [16:0] VAR5 = ({1'b0, VAR2, 8'd0} + {1'b0, VAR2, 6'd0} + {1'b0, VAR6});
wire [15:0] VAR4 = ({1'b... | mit |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/fetch/mem_bilo_db.v | 10,352 | module MODULE1 (
clk ,
VAR56 ,
VAR24 ,
VAR30 ,
VAR22 ,
VAR8 ,
VAR27 ,
VAR31 ,
VAR14 ,
VAR23
);
input clk ; input VAR56 ; input VAR24 ; input [1:0] VAR30 ; input [3:0] VAR22 ; input [4:0] VAR8 ; input [VAR55*16-1:0] VAR27 ; input VAR31 ; input [7:0] VAR14 ; output [VAR55*32-1:0] VAR23 ;
wire [VAR55*4-1:0] VAR10 ,
VAR26 ... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/velocityControlHdl_Rotor_Velocity_Control.v | 5,614 | module MODULE1
(
VAR17,
reset,
VAR29,
VAR3,
VAR19,
VAR48,
VAR40,
VAR4
);
input VAR17;
input reset;
input VAR29;
input VAR3;
input signed [17:0] VAR19; input signed [17:0] VAR48; input signed [17:0] VAR40; output signed [17:0] VAR4;
wire signed [35:0] VAR36; wire signed [35:0] VAR23; wire signed [17:0] VAR5; wire signed... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/and2/gf180mcu_fd_sc_mcu9t5v0__and2_4.behavioral.v | 1,178 | module MODULE1( VAR4, VAR5, VAR2 );
input VAR5, VAR4;
output VAR2;
VAR1 VAR3(.VAR4(VAR4),.VAR5(VAR5),.VAR2(VAR2));
VAR1 VAR6(.VAR4(VAR4),.VAR5(VAR5),.VAR2(VAR2)); | apache-2.0 |
zhaishaomin/ring_network-based-multicore- | communication_assist/arbiter_for_dcache.v | 5,068 | module MODULE1( clk,
rst,
VAR12,
VAR3,
VAR20,
VAR24,
VAR7,
VAR17,
VAR16,
VAR21,
VAR1,
VAR23,
VAR18,
VAR19,
VAR2,
VAR14,
VAR22
);
input clk;
input rst;
input VAR12;
input VAR3;
input [143:0] VAR20;
input VAR24;
input [67:0] VAR7;
input VAR17;
input [143:0] VAR16;
output [143:0] VAR21;
output VAR1;
output VAR23;
output V... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_common/rtl/bw_io_dtl_bscl2.v | 6,430 | module MODULE1(VAR57 ,VAR94 ,VAR76 ,VAR41 ,
VAR100 ,VAR56 ,VAR47 ,VAR60 ,VAR11 ,VAR8 ,
VAR91 ,VAR14 ,VAR97 ,VAR13 ,VAR107 ,VAR30 ,VAR22
);
output VAR56 ;
output VAR47 ;
output VAR91 ;
output VAR107 ;
input VAR57 ;
input VAR94 ;
input VAR76 ;
input VAR41 ;
input VAR100 ;
input VAR60 ;
input VAR11 ;
input VAR8 ;
input VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or2b/sky130_fd_sc_hd__or2b.functional.pp.v | 1,924 | module MODULE1 (
VAR8 ,
VAR6 ,
VAR14 ,
VAR3,
VAR10,
VAR4 ,
VAR2
);
output VAR8 ;
input VAR6 ;
input VAR14 ;
input VAR3;
input VAR10;
input VAR4 ;
input VAR2 ;
wire VAR15 ;
wire VAR7 ;
wire VAR1;
not VAR5 (VAR15 , VAR14 );
or VAR13 (VAR7 , VAR15, VAR6 );
VAR9 VAR12 (VAR1, VAR7, VAR3, VAR10);
buf VAR11 (VAR8 , VAR1 );
en... | apache-2.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_m00_regslice_0/synth/OpenSSD2_m00_regslice_0.v | 15,518 | module MODULE1 (
VAR30,
VAR14,
VAR17,
VAR1,
VAR112,
VAR38,
VAR111,
VAR27,
VAR84,
VAR19,
VAR31,
VAR22,
VAR37,
VAR40,
VAR109,
VAR107,
VAR71,
VAR42,
VAR89,
VAR60,
VAR90,
VAR29,
VAR78,
VAR51,
VAR72,
VAR88,
VAR68,
VAR5,
VAR58,
VAR10,
VAR74,
VAR48,
VAR13,
VAR25,
VAR103,
VAR91,
VAR28,
VAR102,
VAR110,
VAR83,
VAR101,
VAR92,
VAR... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/mig_v3_4/user_design/rtl/controller/rank_cntrl.v | 16,479 | module MODULE1 #
(
parameter VAR66 = 100,
parameter VAR60 = "8",
parameter VAR24 = 0,
parameter VAR33 = 4,
parameter VAR14 = 2,
parameter VAR58 = 5,
parameter VAR68 = 30,
parameter VAR72 = 8,
parameter VAR80 = 4,
parameter VAR42 = 4,
parameter VAR17 = 20,
parameter VAR1 = 16,
parameter VAR45 = 2,
parameter VAR55 = 4,
p... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o2111a/sky130_fd_sc_ms__o2111a.functional.pp.v | 2,074 | module MODULE1 (
VAR11 ,
VAR6 ,
VAR3 ,
VAR13 ,
VAR9 ,
VAR15 ,
VAR7,
VAR17,
VAR8 ,
VAR18
);
output VAR11 ;
input VAR6 ;
input VAR3 ;
input VAR13 ;
input VAR9 ;
input VAR15 ;
input VAR7;
input VAR17;
input VAR8 ;
input VAR18 ;
wire VAR12 ;
wire VAR14 ;
wire VAR16;
or VAR1 (VAR12 , VAR3, VAR6 );
and VAR5 (VAR14 , VAR13, V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_lp__udp_dff_nsr_pp_pg_n.blackbox.v | 1,628 | module MODULE1 (
VAR2 ,
VAR8 ,
VAR6 ,
VAR7 ,
VAR1 ,
VAR3,
VAR5 ,
VAR4
);
output VAR2 ;
input VAR8 ;
input VAR6 ;
input VAR7 ;
input VAR1 ;
input VAR3;
input VAR5 ;
input VAR4 ;
endmodule | apache-2.0 |
sabertazimi/hust-lab | verilog/labs/lab5/src/Moore_FSM.v | 2,977 | module MODULE1(
input clk,
input reset,
input [1:0] VAR6,
output reg VAR4
);
reg [2:0] state, VAR3;
parameter VAR1 = 0, VAR8 = 1, VAR7 = 2, b0 = 3, b1 = 4, VAR2 = 5, VAR5 = 6;
always @(posedge clk or posedge reset) begin
if (reset) begin
state <= VAR1;
end
else begin
state <= VAR3;
end
end
always @(VAR6 or state) begin... | mit |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/IPRepo-1.0.0/NVMeHostController/src/pcie_tans_if.v | 9,379 | module MODULE1 # (
parameter VAR84 = 128,
parameter VAR46 = 36
)
(
input VAR81,
input VAR6,
output VAR56,
output [VAR84-1:0] VAR78,
output [7:0] VAR106,
output VAR102,
output VAR37,
output [VAR84-1:0] VAR5,
output [7:0] VAR75,
output VAR103,
output VAR14,
output [VAR84-1:0] VAR73,
output [7:0] VAR67,
output VAR16,
outp... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2.behavioral.pp.v | 1,768 | module MODULE1 (
VAR6 ,
VAR7 ,
VAR9,
VAR10
);
output VAR6 ;
input VAR7 ;
input VAR9;
input VAR10;
wire VAR1 ;
wire VAR3;
not VAR5 (VAR1 , VAR7 );
VAR4 VAR8 (VAR3, VAR1, VAR9, VAR10);
buf VAR2 (VAR6 , VAR3 );
endmodule | apache-2.0 |
AngelTerrones/MUSB | Hardware/musb/musb_memwb_register.v | 2,453 | module MODULE1(
input clk, input rst, input [31:0] VAR13, input [31:0] VAR7, input [4:0] VAR8, input VAR9, input VAR2, input VAR4,
input VAR11, input VAR5, output reg [31:0] VAR1, output reg [31:0] VAR12, output reg [4:0] VAR6, output reg VAR10, output reg VAR3 );
always @(posedge clk) begin
VAR1 <= (rst) ? 31'b0 : ((V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or3b/sky130_fd_sc_ms__or3b.pp.symbol.v | 1,301 | module MODULE1 (
input VAR2 ,
input VAR5 ,
input VAR1 ,
output VAR8 ,
input VAR7 ,
input VAR6,
input VAR3,
input VAR4
);
endmodule | apache-2.0 |
ehab93/MIPS-Processor | lib/jump_addr.v | 1,055 | module MODULE1(
input [25:0] VAR3,
input [3:0] VAR2,
output[31:0] VAR1);
buf (VAR1[0 ] ,VAR3[0 ]);
buf (VAR1[1 ] ,VAR3[1 ]);
buf (VAR1[2 ] ,VAR3[2 ]);
buf (VAR1[3 ] ,VAR3[3 ]);
buf (VAR1[4 ] ,VAR3[4 ]);
buf (VAR1[5 ] ,VAR3[5 ]);
buf (VAR1[6 ] ,VAR3[6 ]);
buf (VAR1[7 ] ,VAR3[7 ]);
buf (VAR1[8 ] ,VAR3[8 ]);
buf (VAR1[9 ]... | mit |
ShepardSiegel/ocpi | libsrc/hdl/ocpi/xilinx_v5_v12_pcie_wrapper.v | 11,105 | module MODULE1
(
VAR32, VAR66, VAR52, VAR110,
VAR53, VAR100, VAR21, VAR63,
VAR71, VAR54, VAR16, VAR27,
VAR68, VAR106, VAR36,
VAR86, VAR31, VAR91,
VAR97, VAR69, VAR9, VAR99, VAR88,
VAR60, VAR103, VAR5, VAR80,
VAR11, VAR49, VAR25, VAR96,
VAR61, VAR46, VAR20, VAR55,
VAR26, VAR56, VAR90,
VAR79, VAR74,
VAR30, VAR47, VAR6,
V... | lgpl-3.0 |
makestuff/seven-seg | verilog/seven_seg.v | 2,900 | module
MODULE1#(
parameter
VAR10 = 18
)(
input wire VAR12,
input wire[15:0] VAR1,
input wire[3:0] VAR5,
output wire[7:0] VAR4,
output wire[3:0] VAR3
);
reg[VAR10-1:0] VAR8 = 0;
wire[VAR10-1:0] VAR11;
wire[1:0] VAR6;
wire[3:0] VAR2;
wire[6:0] VAR9;
wire VAR7;
always @(posedge VAR12)
VAR8 <= VAR11;
assign VAR11 = VAR8 + ... | gpl-3.0 |
freecores/raggedstone | source/pcidmux.v | 1,679 | module MODULE1 ( VAR6, VAR4, VAR15, VAR9, VAR1, VAR14, VAR5,
VAR12, VAR10, VAR2, VAR7, VAR16);
input VAR6;
input VAR4;
inout [31:0] VAR15;
output [31:0] VAR9;
input VAR1;
input VAR14;
input VAR5;
input VAR12;
input [15:0] VAR10;
output [15:0] VAR2;
input [31:0] VAR7;
output [31:0] VAR16;
wire [31:0] VAR13;
wire [31:0] ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/mux4/sky130_fd_sc_ms__mux4.blackbox.v | 1,339 | module MODULE1 (
VAR10 ,
VAR4,
VAR2,
VAR6,
VAR8,
VAR1,
VAR5
);
output VAR10 ;
input VAR4;
input VAR2;
input VAR6;
input VAR8;
input VAR1;
input VAR5;
supply1 VAR9;
supply0 VAR3;
supply1 VAR11 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
juan199/Lab_Digitales | exp1/MiniAlu.v | 3,520 | module MODULE1
(
input wire VAR5,
input wire VAR14,
output wire [7:0] VAR35
);
wire [15:0] VAR31,VAR41;
reg VAR3,VAR4;
wire [27:0] VAR23;
wire [3:0] VAR28;
reg [15:0] VAR39;
wire [7:0] VAR43,VAR37,VAR24;
wire [15:0] VAR9,VAR6,VAR30,VAR27;
VAR25 VAR29
(
.VAR40( VAR31 ),
.VAR15( VAR23 )
);
VAR21 VAR10
(
.VAR5( VAR5 ),
.V... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor2/sky130_fd_sc_hs__nor2_4.v | 1,959 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR5 ,
VAR1,
VAR6
);
output VAR3 ;
input VAR2 ;
input VAR5 ;
input VAR1;
input VAR6;
VAR7 VAR4 (
.VAR3(VAR3),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR3,
VAR2,
VAR5
);
output VAR3;
input VAR2;
input VAR5;
supply1 VAR1;
supply0 VAR6;
VAR7 VAR4 (
.... | apache-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_sa1/sa1_div.v | 4,503 | module MODULE1 (
VAR7,
VAR11,
VAR19,
VAR8,
VAR14);
input VAR7;
input [15:0] VAR11;
input [15:0] VAR19;
output [15:0] VAR8;
output [15:0] VAR14;
wire [15:0] VAR16;
wire [15:0] VAR17;
wire [15:0] VAR8 = VAR16[15:0];
wire [15:0] VAR14 = VAR17[15:0];
VAR22 VAR9 (
.VAR7 (VAR7),
.VAR11 (VAR11),
.VAR19 (VAR19),
.VAR8 (VAR16),... | gpl-2.0 |
cliffordwolf/yosys | techlibs/ice40/ff_map.v | 3,043 | module \VAR1 (input VAR45, VAR40, output VAR33); VAR13 VAR10 (.VAR45(VAR45), .VAR33(VAR33), .VAR40(VAR40)); wire VAR15 = 1; endmodule
module \VAR20 (input VAR45, VAR40, output VAR33); VAR46 VAR10 (.VAR45(VAR45), .VAR33(VAR33), .VAR40(VAR40)); wire VAR15 = 1; endmodule
module \VAR35 (input VAR45, VAR40, VAR5, output VAR... | isc |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_babasu/spw_babasu/synthesis/submodules/spw_babasu_AUTOSTART.v | 2,198 | module MODULE1 (
address,
VAR8,
clk,
VAR2,
VAR5,
VAR9,
VAR1,
VAR6
)
;
output VAR1;
output [ 31: 0] VAR6;
input [ 1: 0] address;
input VAR8;
input clk;
input VAR2;
input VAR5;
input [ 31: 0] VAR9;
wire VAR3;
reg VAR4;
wire VAR1;
wire VAR7;
wire [ 31: 0] VAR6;
assign VAR3 = 1;
assign VAR7 = {1 {(address == 0)}} & VAR4;
a... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlygate4s18/sky130_fd_sc_lp__dlygate4s18_1.v | 2,119 | module MODULE1 (
VAR3 ,
VAR8 ,
VAR6,
VAR7,
VAR1 ,
VAR5
);
output VAR3 ;
input VAR8 ;
input VAR6;
input VAR7;
input VAR1 ;
input VAR5 ;
VAR2 VAR4 (
.VAR3(VAR3),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR3,
VAR8
);
output VAR3;
input VAR8;
supply1 VAR6;
supply0 VAR7;... | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/8-way/src/ip_pcie/source/PCIeGen2x8If128_pipe_reset.v | 22,154 | module MODULE1 #
(
parameter VAR61 = "VAR23", parameter VAR39 = "VAR64",
parameter VAR7 = "VAR63", parameter VAR82 = "VAR4", parameter VAR50 = "VAR23", parameter VAR9 = 1, parameter VAR65 = 6'd63, parameter VAR86 = 1
)
(
input VAR73,
input VAR49,
input VAR2,
input VAR51,
input [VAR9-1:0] VAR15,
input [VAR9-1:0] VAR34,
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o21bai/sky130_fd_sc_ls__o21bai.functional.pp.v | 2,174 | module MODULE1 (
VAR5 ,
VAR9 ,
VAR10 ,
VAR13,
VAR2,
VAR14,
VAR15 ,
VAR1
);
output VAR5 ;
input VAR9 ;
input VAR10 ;
input VAR13;
input VAR2;
input VAR14;
input VAR15 ;
input VAR1 ;
wire VAR17 ;
wire VAR16 ;
wire VAR8 ;
wire VAR12;
not VAR7 (VAR17 , VAR13 );
or VAR4 (VAR16 , VAR10, VAR9 );
nand VAR11 (VAR8 , VAR17, VAR1... | apache-2.0 |
zeruniverse/pipelined_CPU | ISE project/ipcore_dir/mem_ins.v | 5,450 | module MODULE1(
VAR51,
VAR14);
input [5 : 0] VAR51;
output [31 : 0] VAR14;
VAR43 #(
.VAR2(6),
.VAR53("0"),
.VAR28(64),
.VAR18("VAR24"),
.VAR40(0),
.VAR29(0),
.VAR17(0),
.VAR15(0),
.VAR26(0),
.VAR31(0),
.VAR7(0),
.VAR41(0),
.VAR9(0),
.VAR21(0),
.VAR12(0),
.VAR42(0),
.VAR35(0),
.VAR36(0),
.VAR27(1),
.VAR49(0),
.VAR22(0),... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21bai/sky130_fd_sc_hs__o21bai_2.v | 2,202 | module MODULE2 (
VAR1 ,
VAR2 ,
VAR6 ,
VAR5,
VAR8,
VAR7
);
output VAR1 ;
input VAR2 ;
input VAR6 ;
input VAR5;
input VAR8;
input VAR7;
VAR4 VAR3 (
.VAR1(VAR1),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR1 ,
VAR2 ,
VAR6 ,
VAR5
);
output VAR1 ;
input VAR2 ;
input VAR6 ... | apache-2.0 |
mistryalok/Zedboard | learning/training/MSD/s07v2/vivado/project_2/project_2.srcs/sources_1/bd/design_1/ip/design_1_sample_generator_0_1/synth/design_1_sample_generator_0_1.v | 5,176 | module MODULE1 (
VAR18,
VAR10,
VAR4,
VAR22,
VAR13,
VAR2,
VAR11,
VAR16,
VAR17,
VAR20,
VAR15,
VAR9,
VAR14,
VAR21,
VAR8,
VAR1,
VAR12
);
input wire [7 : 0] VAR18;
input wire VAR10;
input wire VAR4;
output wire [31 : 0] VAR22;
output wire [3 : 0] VAR13;
output wire VAR2;
output wire VAR11;
input wire VAR16;
input wire VAR17... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfxbp/sky130_fd_sc_ms__dfxbp_2.v | 2,226 | module MODULE1 (
VAR2 ,
VAR10 ,
VAR8 ,
VAR4 ,
VAR3,
VAR6,
VAR1 ,
VAR7
);
output VAR2 ;
output VAR10 ;
input VAR8 ;
input VAR4 ;
input VAR3;
input VAR6;
input VAR1 ;
input VAR7 ;
VAR5 VAR9 (
.VAR2(VAR2),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR7(VAR7)
);
endmodule
module MODUL... | apache-2.0 |
andrewandrepowell/kernel-on-chip | hdl/projects/Nexys4/bd/ip/bd_clk_wiz_0_0/bd_clk_wiz_0_0_clk_wiz.v | 7,509 | module MODULE1
( output VAR69,
output VAR91,
output VAR51,
input VAR38,
input VAR78
);
wire VAR26;
wire VAR85;
VAR40 VAR48
(.VAR62 (VAR26),
.VAR30 (VAR78));
wire VAR58;
wire VAR55;
wire VAR49;
wire VAR68;
wire VAR52;
wire VAR15;
wire VAR25;
wire [15:0] VAR67;
wire VAR7;
wire VAR74;
wire VAR18;
wire VAR87;
wire VAR86;
w... | mit |
Franderg/Ascensor | acciones_to_bcd.v | 1,819 | module MODULE1(
input clk,
input rst,
input [1:0] VAR3, input [1:0] VAR2, input VAR7, output reg [3:0] VAR6,
output reg [3:0] VAR5,
output reg [3:0] VAR4,
output reg [3:0] VAR1
);
begin
begin
end
begin
end
begin
begin
end
begin
end
begin
begin
end
begin
end | gpl-3.0 |
markusC64/1541ultimate2 | fpga/nios_dut/nios_dut/synthesis/submodules/MM_to_ST_Adapter.v | 13,474 | module MODULE1 (
clk,
reset,
VAR30,
VAR13,
address,
VAR37,
VAR4,
VAR15,
VAR2,
VAR27,
VAR39,
VAR26,
VAR5,
VAR10
);
parameter VAR21 = 32; parameter VAR18 = 32;
parameter VAR7 = 32;
parameter VAR23 = 2; parameter VAR24 = 5;
parameter VAR29 = 2; parameter VAR6 = 1; parameter VAR17 = 1; parameter VAR36 = 0;
input clk;
input... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o32a/sky130_fd_sc_ls__o32a.functional.pp.v | 2,188 | module MODULE1 (
VAR2 ,
VAR13 ,
VAR14 ,
VAR8 ,
VAR16 ,
VAR11 ,
VAR19,
VAR20,
VAR18 ,
VAR1
);
output VAR2 ;
input VAR13 ;
input VAR14 ;
input VAR8 ;
input VAR16 ;
input VAR11 ;
input VAR19;
input VAR20;
input VAR18 ;
input VAR1 ;
wire VAR17 ;
wire VAR4 ;
wire VAR9 ;
wire VAR12;
or VAR6 (VAR17 , VAR14, VAR13, VAR8 );
or ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o2111a/sky130_fd_sc_hd__o2111a_1.v | 2,448 | module MODULE2 (
VAR12 ,
VAR6 ,
VAR7 ,
VAR2 ,
VAR1 ,
VAR11 ,
VAR10,
VAR4,
VAR8 ,
VAR3
);
output VAR12 ;
input VAR6 ;
input VAR7 ;
input VAR2 ;
input VAR1 ;
input VAR11 ;
input VAR10;
input VAR4;
input VAR8 ;
input VAR3 ;
VAR5 VAR9 (
.VAR12(VAR12),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR1... | apache-2.0 |
fallen/milkymist-mmu | cores/fmlarb/rtl/fmlarb_dack.v | 1,753 | module MODULE1(
input VAR3,
input VAR4,
input VAR2,
input VAR6,
input VAR8,
output VAR9,
output reg ack
);
wire read = VAR6 & ~VAR8;
wire write = VAR6 & VAR8;
reg VAR7;
reg VAR5;
reg VAR11;
always @(posedge VAR3) begin
if(VAR4) begin
VAR7 <= 1'b0;
VAR5 <= 1'b0;
VAR11 <= 1'b0;
end else begin
VAR7 <= read;
VAR5 <= VAR7;
... | lgpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_gpio_sysfs/zybo_petalinux_1.ip_user_files/ipstatic/axi_data_fifo_v2_1/hdl/verilog/axi_data_fifo_v2_1_axic_srl_fifo.v | 8,230 | module MODULE1 #
(
parameter VAR13 = "none", parameter integer VAR33 = 1, parameter integer VAR34 = 33, parameter integer VAR12 = 2, parameter VAR39 = 1 )
(
input wire VAR14, input wire VAR17, input wire [VAR33-1:0] VAR22, input wire VAR23, output wire VAR32, output wire [VAR33-1:0] VAR1, output wire VAR30, input wire ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfxbp/sky130_fd_sc_lp__dfxbp.behavioral.pp.v | 1,923 | module MODULE1 (
VAR5 ,
VAR12 ,
VAR10 ,
VAR1 ,
VAR9,
VAR14,
VAR6 ,
VAR16
);
output VAR5 ;
output VAR12 ;
input VAR10 ;
input VAR1 ;
input VAR9;
input VAR14;
input VAR6 ;
input VAR16 ;
wire VAR7 ;
reg VAR17 ;
wire VAR11 ;
wire VAR8;
wire VAR15 ;
VAR13 VAR4 (VAR7 , VAR11, VAR8, VAR17, VAR9, VAR14);
assign VAR15 = ( VAR9 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/tapvgnd2/sky130_fd_sc_lp__tapvgnd2.behavioral.v | 1,200 | module MODULE1 ();
supply1 VAR2;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
f3zz3h/Embedded-Co-Design | ts7300_top_restored/ethernet/eth_rxstatem.v | 7,541 | module MODULE1 (VAR12, VAR15, VAR21, VAR20, VAR9, VAR24, VAR10, VAR13,
VAR5, VAR7, VAR4, VAR23, VAR17, VAR19,
VAR3
);
parameter VAR8 = 1;
input VAR12;
input VAR15;
input VAR21;
input VAR20;
input VAR9;
input VAR10;
input VAR24;
input VAR13;
input VAR5;
input VAR7;
output [1:0] VAR4;
output VAR23;
output VAR3;
output VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or4bb/sky130_fd_sc_lp__or4bb.symbol.v | 1,327 | module MODULE1 (
input VAR4 ,
input VAR6 ,
input VAR8,
input VAR5,
output VAR2
);
supply1 VAR1;
supply0 VAR7;
supply1 VAR3 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o22ai/sky130_fd_sc_hd__o22ai.pp.symbol.v | 1,376 | module MODULE1 (
input VAR3 ,
input VAR8 ,
input VAR7 ,
input VAR9 ,
output VAR4 ,
input VAR1 ,
input VAR6,
input VAR5,
input VAR2
);
endmodule | apache-2.0 |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/bd/system/ip/system_auto_pc_0/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_incr_cmd.v | 4,483 | module MODULE1 #
(
parameter integer VAR5 = 32
)
(
input wire clk ,
input wire reset ,
input wire [VAR5-1:0] VAR11 ,
input wire [7:0] VAR17 ,
input wire [2:0] VAR7 ,
input wire VAR10 ,
output wire [VAR5-1:0] VAR14 ,
input wire VAR8 ,
output reg VAR1
);
reg VAR16;
reg [11:0] VAR12;
reg [8:0] VAR15;
reg VAR2;
wire [3:0] ... | mit |
sigilance/tera-computer | src/pc.v | 1,236 | module MODULE2 (VAR9, VAR13, VAR7, VAR2);
input [7:0] VAR13; input VAR7, VAR2;
output reg [7:0] VAR9;
always @ (posedge VAR7) if (VAR2) VAR9 <= 8'b0; else VAR9 <= VAR13; endmodule
module MODULE1 (VAR11, VAR12, VAR4, VAR7, VAR2);
output [7:0] VAR11;
input [7:0] VAR12;
input VAR4, VAR7, VAR2;
wire [7:0] VAR6, VAR1;
MODUL... | mit |
walkthetalk/fsref | ip/fscpu/src/include/DISCHARGE_ctl.v | 3,913 | module MODULE1 #
(
parameter integer VAR13 = 0,
parameter integer VAR15 = 16,
parameter integer VAR23 = 16,
parameter integer VAR9 = 32
) (
input wire clk,
input wire VAR3,
output wire VAR10,
output wire VAR5,
input wire [VAR15-1:0] VAR17, input wire [VAR15-1:0] VAR16,
input wire [VAR15-1:0] VAR12,
input wire [VAR9-1:0... | gpl-3.0 |
tloinuy/opencpi-opencv | opencpi/hdl/apps/mkOCApp-noADC-6w.v | 22,601 | module MODULE1(VAR243,
VAR44,
VAR144,
VAR274,
VAR117,
VAR137,
VAR195,
VAR221,
VAR68,
VAR224,
VAR200,
VAR108,
VAR20,
VAR160,
VAR184,
VAR125,
VAR102,
VAR2,
VAR179,
VAR131,
VAR36,
VAR279,
VAR143,
VAR49,
VAR114,
VAR138,
VAR217,
VAR123,
VAR61,
VAR215,
VAR86,
VAR87,
VAR147,
VAR234,
VAR263,
VAR229,
VAR99,
VAR40,
VAR92,
VAR223... | gpl-2.0 |
yanhongwang/ColorImage | ColorCorrection/ColorCorrection.v | 2,698 | module MODULE1
(
input[ VAR14 - 1 : 0 ]VAR7,
input[ VAR14 - 1 : 0 ]VAR9,
input[ VAR14 - 1 : 0 ]VAR1,
output wire[ VAR14 - 1 : 0 ]VAR12,
output wire[ VAR14 - 1 : 0 ]VAR13,
output wire[ VAR14 - 1 : 0 ]VAR6
);
reg[ VAR14 : 0 ]VAR5;
reg[ VAR14 : 0 ]VAR23;
reg[ VAR14 : 0 ]VAR11;
always@( VAR7 or VAR9 or VAR1 )
begin
VAR5 = ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or2b/sky130_fd_sc_hdll__or2b.pp.symbol.v | 1,292 | module MODULE1 (
input VAR1 ,
input VAR4 ,
output VAR7 ,
input VAR3 ,
input VAR5,
input VAR2,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a22o/sky130_fd_sc_lp__a22o.pp.blackbox.v | 1,385 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR6 ,
VAR9 ,
VAR7 ,
VAR5,
VAR2,
VAR4 ,
VAR8
);
output VAR3 ;
input VAR1 ;
input VAR6 ;
input VAR9 ;
input VAR7 ;
input VAR5;
input VAR2;
input VAR4 ;
input VAR8 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux4/sky130_fd_sc_lp__mux4.behavioral.pp.v | 1,983 | module MODULE1 (
VAR18 ,
VAR11 ,
VAR5 ,
VAR16 ,
VAR1 ,
VAR7 ,
VAR10 ,
VAR12,
VAR9,
VAR17 ,
VAR2
);
output VAR18 ;
input VAR11 ;
input VAR5 ;
input VAR16 ;
input VAR1 ;
input VAR7 ;
input VAR10 ;
input VAR12;
input VAR9;
input VAR17 ;
input VAR2 ;
wire VAR4 ;
wire VAR6;
VAR8 VAR3 (VAR4 , VAR11, VAR5, VAR16, VAR1, VAR7, ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor2/sky130_fd_sc_hs__nor2.functional.v | 1,672 | module MODULE1 (
VAR3,
VAR10,
VAR2 ,
VAR7 ,
VAR8
);
input VAR3;
input VAR10;
output VAR2 ;
input VAR7 ;
input VAR8 ;
wire VAR5 ;
wire VAR9;
nor VAR4 (VAR5 , VAR7, VAR8 );
VAR11 VAR1 (VAR9, VAR5, VAR3, VAR10);
buf VAR6 (VAR2 , VAR9 );
endmodule | apache-2.0 |
zatslogic/UDI_example | udi/udi_top.v | 5,088 | module MODULE1 (
input [31:0] VAR31 , input VAR45 , input [31:0] VAR29 , input [31:0] VAR49 , input VAR30 , input VAR47 , input VAR41 , input VAR51 , input VAR9 , input VAR21 , input VAR14 , input VAR46 ,
output [31:0] VAR42 , output [4:0] VAR11 ,
output VAR23 , output VAR39 , output VAR10 , output VAR7 , input [VAR3-1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfrtp/sky130_fd_sc_ls__sdfrtp.symbol.v | 1,510 | module MODULE1 (
input VAR5 ,
output VAR6 ,
input VAR9,
input VAR4 ,
input VAR10 ,
input VAR8
);
supply1 VAR1;
supply0 VAR3;
supply1 VAR2 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/bd/system/ip/system_auto_us_1/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s.v | 25,773 | module MODULE1 #(
parameter VAR117 = 0,
parameter integer VAR73 = 4,
parameter integer VAR176 = 30,
parameter integer VAR74 = 32,
parameter integer VAR103 = 1,
parameter integer VAR14 = 1
)
(
input wire VAR154 ,
input wire VAR216 ,
input wire [VAR73-1:0] VAR46 ,
input wire [VAR176-1:0] VAR86 ,
input wire [((VAR117 == 1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlrtp/sky130_fd_sc_ls__dlrtp_1.v | 2,362 | module MODULE2 (
VAR6 ,
VAR2,
VAR4 ,
VAR5 ,
VAR1 ,
VAR3 ,
VAR7 ,
VAR10
);
output VAR6 ;
input VAR2;
input VAR4 ;
input VAR5 ;
input VAR1 ;
input VAR3 ;
input VAR7 ;
input VAR10 ;
VAR8 VAR9 (
.VAR6(VAR6),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR10(VAR10)
);
endmodule
module MODU... | apache-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/acl_fp_sqrt_double.v | 121,064 | module MODULE1
(
VAR68,
VAR185,
VAR87,
VAR118,
VAR116) ;
input VAR68;
input VAR185;
input VAR87;
input [54:0] VAR118;
output [53:0] VAR116;
tri0 VAR68;
tri1 VAR185;
tri0 VAR87;
reg [1:0] VAR179;
reg [51:0] VAR36;
reg [51:0] VAR242;
reg [51:0] VAR108;
reg [51:0] VAR199;
reg [51:0] VAR127;
reg [51:0] VAR24;
reg [51:0] VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a31o/sky130_fd_sc_ms__a31o_2.v | 2,337 | module MODULE2 (
VAR10 ,
VAR3 ,
VAR8 ,
VAR5 ,
VAR4 ,
VAR9,
VAR6,
VAR2 ,
VAR1
);
output VAR10 ;
input VAR3 ;
input VAR8 ;
input VAR5 ;
input VAR4 ;
input VAR9;
input VAR6;
input VAR2 ;
input VAR1 ;
VAR11 VAR7 (
.VAR10(VAR10),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/edk/pcores/aurora_201_pcore_v1_00_a/hdl/verilog/aurora_201_global_logic.v | 5,142 | module MODULE1
(
VAR8,
VAR1,
VAR18,
VAR26,
VAR13,
VAR12,
VAR17,
VAR9,
VAR31,
VAR29,
VAR25,
VAR22,
VAR4,
VAR20,
VAR15,
VAR28,
VAR24,
VAR32,
VAR10,
VAR2
);
input VAR8;
output VAR1;
input VAR26;
input VAR18;
input VAR13;
input VAR12;
input [0:1] VAR17;
input VAR9;
output VAR31;
output [0:1] VAR29;
output [0:1] VAR25;
outp... | gpl-2.0 |
CospanDesign/nysa-sdio-device | rtl/cia/sdio_cis.v | 1,840 | module MODULE1 (
input clk,
input rst
input VAR10,
input VAR3,
output VAR12,
output VAR5,
input VAR1,
input VAR11,
input [17:0] VAR7,
input VAR8,
input [17:0] VAR2,
input [7:0] VAR4,
output [7:0] VAR6,
output VAR9
);
endmodule | mit |
rakeshkadamati/MIPS-32-Bit-Verilog | registerfile.v | 2,693 | module MODULE1(VAR4,VAR5,VAR1,VAR7,VAR3,VAR8,VAR2,clk);
input VAR4; input [4:0] VAR5; input [4:0] VAR1; input [4:0] VAR8; input [31:0] VAR2; output [31:0] VAR7; output [31:0] VAR3;
input clk;
reg [31:0] VAR6 [31:0];
begin | mit |
rurume/openrisc_vision_hardware | ISE/uart_rfifo.v | 11,183 | module MODULE1 (clk,
VAR3, VAR28, VAR11,
VAR21, VAR14, VAR38,
VAR12,
VAR39,
VAR41,
VAR30
);
parameter VAR17 = VAR42;
parameter VAR7 = VAR29;
parameter VAR5 = VAR37;
parameter VAR44 = VAR36;
input clk;
input VAR3;
input VAR21;
input VAR14;
input [VAR17-1:0] VAR28;
input VAR41;
input VAR30;
output [VAR17-1:0] VAR11;
outp... | gpl-2.0 |
wendlers/lattice-logic-sniffer | logic/clkdiv.v | 1,749 | module MODULE1(
input rst,
input VAR3,
input [15:0] VAR1,
output VAR5
);
reg VAR2 = 1'b0;
reg [15:0] VAR4 = 16'h0;
always @(posedge VAR3) begin
if(rst) begin
VAR2 = 1'b0;
VAR4 = 16'h0;
end
else begin
VAR4 = VAR4 + 1;
if(VAR4 == VAR1) begin
VAR4 = 16'h0;
VAR2 = ~VAR2;
end
end
end
assign VAR5 = VAR2;
endmodule | mit |
jmesmon/trifles | verilog/hw3/ff.v | 1,351 | module MODULE2(output VAR29, VAR24, input VAR21, VAR12);
nand VAR22(VAR29, VAR21, VAR24),
VAR17(VAR24, VAR12, VAR29);
endmodule
module MODULE1(output VAR29, VAR24, input VAR26, VAR3);
nor VAR2(VAR29, VAR3, VAR24),
VAR25(VAR24, VAR26, VAR29);
endmodule
module MODULE3(output VAR29, VAR24, input VAR6, clk);
wire VAR10, VA... | gpl-3.0 |
impedimentToProgress/ProbableCause | ddr2/cores/or1200/or1200_tpram_32x32.v | 11,602 | module MODULE1(
VAR10, VAR104, VAR41, VAR86, VAR77, VAR58, VAR126, VAR114,
VAR53, VAR16, VAR54, VAR131, VAR129, VAR15, VAR62, VAR40
);
parameter VAR27 = 5;
parameter VAR65 = 32;
input VAR10; input VAR104; input VAR41; input VAR86; input VAR77; input [VAR27-1:0] VAR58; input [VAR65-1:0] VAR126; output [VAR65-1:0] VAR114... | mit |
CospanDesign/nysa-tx1-pcie-platform | tx1_pcie/host_interface/tx1_pcie_host_interface.v | 20,424 | module MODULE1 (
input clk,
input rst,
input VAR118,
input VAR133,
input VAR41,
input VAR141,
input VAR40,
output VAR67,
output VAR166,
input [31:0] VAR105,
input [31:0] VAR34,
input VAR4,
input VAR160,
input VAR22,
output VAR140,
output [31:0] VAR128,
output VAR5,
input VAR43,
output VAR135,
input [23:0] VAR187,
outpu... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a311o/sky130_fd_sc_lp__a311o.behavioral.pp.v | 2,064 | module MODULE1 (
VAR9 ,
VAR15 ,
VAR18 ,
VAR1 ,
VAR4 ,
VAR7 ,
VAR3,
VAR16,
VAR13 ,
VAR12
);
output VAR9 ;
input VAR15 ;
input VAR18 ;
input VAR1 ;
input VAR4 ;
input VAR7 ;
input VAR3;
input VAR16;
input VAR13 ;
input VAR12 ;
wire VAR10 ;
wire VAR14 ;
wire VAR8;
and VAR2 (VAR10 , VAR1, VAR15, VAR18 );
or VAR11 (VAR14 , ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a2111o/sky130_fd_sc_hs__a2111o_2.v | 2,321 | module MODULE2 (
VAR2 ,
VAR8 ,
VAR10 ,
VAR7 ,
VAR9 ,
VAR5 ,
VAR3,
VAR4
);
output VAR2 ;
input VAR8 ;
input VAR10 ;
input VAR7 ;
input VAR9 ;
input VAR5 ;
input VAR3;
input VAR4;
VAR6 VAR1 (
.VAR2(VAR2),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR4(VAR4)
);
endmodule
module MODUL... | apache-2.0 |
curtiszimmerman/orp | hardware/mselSoC/src/systems/geophyte/rtl/verilog/crypto_aes/rtl/verilog/aes_core.v | 9,088 | module MODULE1 (
input clk,
input VAR39,
input [255:0] VAR60,
input [127:0] VAR13,
input [1:0] VAR22,
input VAR6,
output reg [127:0] VAR34,
output reg VAR31
);
localparam VAR67 = 0;
localparam VAR12 = 1;
localparam VAR10 = 2;
localparam VAR38 = 0;
localparam VAR32 = 1;
reg VAR58;
reg [1:0] fsm, VAR69;
reg [3:0] VAR54, ... | apache-2.0 |
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