repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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google/skywater-pdk-libs-sky130_fd_sc_ls | cells/xnor3/sky130_fd_sc_ls__xnor3_2.v | 2,184 | module MODULE2 (
VAR8 ,
VAR9 ,
VAR7 ,
VAR10 ,
VAR3,
VAR2,
VAR4 ,
VAR5
);
output VAR8 ;
input VAR9 ;
input VAR7 ;
input VAR10 ;
input VAR3;
input VAR2;
input VAR4 ;
input VAR5 ;
VAR6 VAR1 (
.VAR8(VAR8),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR5(VAR5)
);
endmodule
module MODULE... | apache-2.0 |
puroh/Procesador_monociclo | controlALU.v | 1,186 | module MODULE1(
input [1:0] VAR1,
input [5:0] VAR3,
input clk,
output reg [2:0]VAR2
);
always @(*)
begin
if (VAR1==2'b00)
begin
VAR2= 3'b010;
end
else if (VAR1==2'b01)
begin
VAR2= 3'b110;
end
else
begin
case (VAR3)
6'b100000:VAR2= 3'b010;
6'b100010:VAR2= 3'b110;
6'b100100:VAR2= 3'b000;
6'b100101:VAR2= 3'b001;
6'b101010... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/velocityControlHdl_Maintain_Range_block1.v | 1,116 | module MODULE1
(
VAR1,
VAR2
);
input signed [35:0] VAR1; output signed [17:0] VAR2;
wire signed [17:0] VAR3;
assign VAR3 = VAR1[35:18];
assign VAR2 = VAR3;
endmodule | gpl-3.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/video_sys/synthesis/submodules/altera_up_av_config_auto_init_ob_audio.v | 6,858 | module MODULE1 (
VAR4,
VAR8
);
parameter VAR1 = 9'h01A;
parameter VAR2 = 9'h01A;
parameter VAR10 = 9'h07B;
parameter VAR11 = 9'h07B;
parameter VAR12 = 9'h0F8;
parameter VAR13 = 9'h006;
parameter VAR7 = 9'h000;
parameter VAR5 = 9'h001;
parameter VAR3 = 9'h002;
parameter VAR9 = 9'h001;
input [ 5: 0] VAR4;
output [26: 0] ... | gpl-2.0 |
DougFirErickson/parallella-hw | fpga/src/elink/hdl/erx.v | 16,328 | module MODULE1 (
VAR26, VAR104, VAR83, VAR61, VAR49,
VAR110, VAR32, VAR91, VAR42,
VAR63, VAR45, VAR12, VAR109,
VAR74, VAR43, VAR65, VAR101, VAR22,
VAR54, VAR29, VAR41, VAR15,
VAR105,
reset, VAR72, VAR28, VAR95, VAR14,
VAR16, VAR48, VAR35, VAR118, VAR11, VAR82,
VAR18, VAR51, VAR100, VAR17, VAR102, VAR88,
VAR87, VAR113, ... | gpl-3.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_3L_007bits.v | 1,917 | module MODULE1 (
clk,
VAR28, VAR14, VAR12, VAR4, VAR19, VAR24, VAR34, VAR23,
sum,
);
input clk;
input [VAR5+0-1:0] VAR28, VAR14, VAR12, VAR4, VAR19, VAR24, VAR34, VAR23;
output [VAR5 :0] sum;
reg [VAR5 :0] sum;
wire [VAR5+3-1:0] VAR20;
wire [VAR5+2-1:0] VAR25, VAR2;
wire [VAR5+1-1:0] VAR22, VAR13, VAR26, VAR15;
reg [VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a41oi/sky130_fd_sc_hd__a41oi.symbol.v | 1,389 | module MODULE1 (
input VAR5,
input VAR7,
input VAR9,
input VAR3,
input VAR1,
output VAR10
);
supply1 VAR4;
supply0 VAR6;
supply1 VAR8 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
rkrajnc/minimig-de1 | rtl/minimig/CIA8520.v | 30,633 | module MODULE3
(
input clk, input VAR56, input rd, input wr, input reset, input [3:0] VAR5, input [7:0] VAR42, output [7:0] VAR36, input VAR78, input VAR13, output irq, input [7:2] VAR8, output [1:0] VAR52, output VAR84, inout VAR96, inout VAR91, input VAR99, input VAR2,
input [1:0] VAR97,
input [7:0] VAR19,
output [7:... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o21ba/sky130_fd_sc_ls__o21ba.behavioral.v | 1,563 | module MODULE1 (
VAR8 ,
VAR2 ,
VAR6 ,
VAR12
);
output VAR8 ;
input VAR2 ;
input VAR6 ;
input VAR12;
supply1 VAR11;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR13 ;
wire VAR10 ;
wire VAR9;
nor VAR5 (VAR10 , VAR2, VAR6 );
nor VAR4 (VAR9, VAR12, VAR10 );
buf VAR7 (VAR8 , VAR9 );
endmodule | apache-2.0 |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/bd/tutorial/ip/tutorial_auto_pc_0/synth/tutorial_auto_pc_0.v | 15,727 | module MODULE1 (
VAR3,
VAR96,
VAR80,
VAR5,
VAR72,
VAR33,
VAR20,
VAR103,
VAR14,
VAR15,
VAR79,
VAR28,
VAR91,
VAR98,
VAR25,
VAR50,
VAR82,
VAR11,
VAR86,
VAR76,
VAR34,
VAR31,
VAR83,
VAR81,
VAR6,
VAR39,
VAR58,
VAR90,
VAR66,
VAR108,
VAR110,
VAR85,
VAR77,
VAR29,
VAR32,
VAR71,
VAR18,
VAR8,
VAR75,
VAR70,
VAR60,
VAR41,
VAR97,
VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a2111o/sky130_fd_sc_hd__a2111o.symbol.v | 1,393 | module MODULE1 (
input VAR1,
input VAR9,
input VAR5,
input VAR2,
input VAR3,
output VAR7
);
supply1 VAR6;
supply0 VAR4;
supply1 VAR8 ;
supply0 VAR10 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a2111oi/sky130_fd_sc_hd__a2111oi.pp.symbol.v | 1,408 | module MODULE1 (
input VAR4 ,
input VAR9 ,
input VAR8 ,
input VAR5 ,
input VAR3 ,
output VAR7 ,
input VAR1 ,
input VAR2,
input VAR10,
input VAR6
);
endmodule | apache-2.0 |
timvideos/HDMI2USB-jahanzeb-firmware | hdl/misc/calc_res.v | 2,841 | module MODULE1(
input wire VAR6,
input wire clk,
input VAR13,
input VAR16,
input VAR7,
output reg [15:0] VAR14,
output reg [15:0] VAR4
);
reg [15:0] VAR2,VAR5,VAR1;
reg VAR9,VAR10,VAR8;
wire VAR12;
wire VAR15;
wire VAR11;
assign VAR12 = ((VAR10 ^ VAR16) & VAR16);
assign VAR15 = ((VAR9 ^ VAR7) & VAR7);
assign VAR11 = ((... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/nor3/sky130_fd_sc_hvl__nor3.behavioral.v | 1,409 | module MODULE1 (
VAR8,
VAR11,
VAR7,
VAR9
);
output VAR8;
input VAR11;
input VAR7;
input VAR9;
supply1 VAR1;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR10 ;
wire VAR6;
nor VAR2 (VAR6, VAR9, VAR11, VAR7 );
buf VAR4 (VAR8 , VAR6 );
endmodule | apache-2.0 |
strigeus/fpganes | src/hw_led.v | 1,886 | module MODULE1(input clk,
input [31:0] VAR1,
input [7:0] enable,
output reg [7:0] VAR4,
output reg [7:0] VAR5);
reg [2:0] state;
reg [3:0] VAR3;
reg [16:0] VAR2;
always @(posedge clk) begin
VAR2 <= VAR2 + 1;
if (VAR2 == 20000) begin
VAR2 <= 0;
state <= state + 1;
end
case (state)
0: begin VAR5 <= enable[0] ? 8'b1111111... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tap/sky130_fd_sc_ls__tap.behavioral.pp.v | 1,189 | module MODULE1 (
VAR4,
VAR2,
VAR1 ,
VAR3
);
input VAR4;
input VAR2;
input VAR1 ;
input VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a31oi/sky130_fd_sc_ls__a31oi.functional.pp.v | 2,038 | module MODULE1 (
VAR13 ,
VAR17 ,
VAR8 ,
VAR9 ,
VAR7 ,
VAR11,
VAR10,
VAR16 ,
VAR3
);
output VAR13 ;
input VAR17 ;
input VAR8 ;
input VAR9 ;
input VAR7 ;
input VAR11;
input VAR10;
input VAR16 ;
input VAR3 ;
wire VAR1 ;
wire VAR2 ;
wire VAR12;
and VAR4 (VAR1 , VAR9, VAR17, VAR8 );
nor VAR14 (VAR2 , VAR7, VAR1 );
VAR6 VAR5... | apache-2.0 |
cheehieu/qm-fir-digital-filter-core | ISAAC/qmfir_documentation/jasons_v/FIR0QM.v | 4,742 | module MODULE1(
VAR18, VAR33, VAR24, VAR14, VAR8, VAR4, VAR31, VAR7,
VAR30, VAR2,
clk, rst, VAR12, VAR6, VAR5, VAR20, VAR22, VAR1, VAR16,
VAR35, VAR15, VAR23
);
parameter VAR29 = 8;
parameter VAR10 = 16;
input clk;
input rst;
input [6:0] VAR12;
input [6:0] VAR6;
input [6:0] VAR5;
input [6:0] VAR20;
input VAR22;
input V... | gpl-2.0 |
babykiss4ever/MipsCPU | CPU/sccu_dataflow.v | 4,410 | module MODULE1(VAR22, VAR7, VAR21, VAR12, VAR3, VAR1, VAR41, VAR4, VAR13, VAR33, VAR47, VAR16, VAR36, VAR44, VAR11);
input [5:0] VAR22, VAR7;
input VAR21;
output VAR1, VAR41, VAR4,VAR33, VAR47, VAR36, VAR44, VAR12, VAR3, VAR11;
output [3:0] VAR13;
output [1:0] VAR16;
wire VAR18 = ~|VAR22;
wire VAR17 = VAR18 & VAR7[5] &... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlrtp/sky130_fd_sc_ms__dlrtp.blackbox.v | 1,366 | module MODULE1 (
VAR3 ,
VAR8,
VAR5 ,
VAR4
);
output VAR3 ;
input VAR8;
input VAR5 ;
input VAR4 ;
supply1 VAR6;
supply0 VAR1;
supply1 VAR2 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_xbar_1/synth/OpenSSD2_xbar_1.v | 19,514 | module MODULE1 (
VAR88,
VAR29,
VAR57,
VAR36,
VAR9,
VAR83,
VAR11,
VAR53,
VAR49,
VAR99,
VAR4,
VAR125,
VAR71,
VAR122,
VAR32,
VAR1,
VAR40,
VAR82,
VAR96,
VAR118,
VAR70,
VAR103,
VAR92,
VAR47,
VAR126,
VAR79,
VAR68,
VAR129,
VAR61,
VAR25,
VAR20,
VAR21,
VAR59,
VAR60,
VAR19,
VAR48,
VAR8,
VAR78,
VAR41,
VAR33,
VAR38,
VAR121,
VAR37,... | gpl-3.0 |
MForever78/CPUFly | src/Keyboard_dev.v | 2,127 | module MODULE1(clk, reset, VAR4, VAR3, VAR1, VAR5);
input clk;
input reset;
input VAR4;
input VAR3;
output reg VAR5;
output reg [7: 0] VAR1;
reg [3:0] counter;
reg [3:0] VAR2; | mit |
bbrown1867/ObjectTracking | hw/kalman_filter/kalman_filter.v | 11,757 | module MODULE1(
input VAR39,
input VAR84,
input VAR9,
output [8:0] VAR106,
output [17:0] VAR70,
input [3:0] VAR24,
input [17:0] VAR30,
output [7:0] VAR202,
output VAR87,
output VAR134,
output [7:0] VAR113,
output VAR102,
output [7:0] VAR77,
output VAR163,
output VAR143,
output VAR40,
inout VAR57,
input VAR157,
input [7... | mit |
himansurathi/labCourseWork | VLSI lab/VLSI codes/trafficLightController.v | 1,830 | module MODULE1 (
input wire clk ,
input wire VAR2 ,
output reg [5:0] VAR11
);
reg [2:0] state;
reg [3:0] VAR1;
parameter VAR10 = 3'b000, VAR9 =3'b001, VAR6 = 3'b010, VAR7 = 3'b011, VAR4 = 3'b100, VAR5 = 3'b101;
parameter VAR8 = 4'b0101, VAR3 = 4'b0001; always @(posedge clk or posedge VAR2)
begin
if (VAR2 == 1)
begin
st... | mit |
thinkoco/de1_soc_opencl | de10_standard_sharedonly_vga/ip/TERASIC_IRM/irda_receive_terasic.v | 10,127 | module MODULE1(
VAR5, VAR20,
VAR6, VAR11,
VAR2, VAR19 );
parameter VAR16 = 2'b00; parameter VAR15 = 2'b01; parameter VAR12 = 2'b10;
parameter VAR13 = 262143; parameter VAR21 = 230000; parameter VAR22 = 210000; parameter VAR23 = 41500; parameter VAR8 = 20000;
input VAR5; input VAR20; input VAR6; input VAR11;
output VAR2... | apache-2.0 |
jmassucco17/full_mips | processor/SingleCycleDatapath/Alu.v | 1,727 | module MODULE2(input[31:0] VAR1,
input[31:0] VAR3,
input[3:0] VAR7,
output reg[31:0] VAR2,
output VAR6);
always @(VAR1, VAR3, VAR7)
case (VAR7)
0: VAR2 = VAR1 + VAR3;
1: VAR2 = VAR1 - VAR3;
2: VAR2 = VAR1 & VAR3;
3: VAR2 = VAR1 | VAR3;
4: VAR2 = VAR1 ~| VAR3;
5: VAR2 = VAR1 ^ VAR3;
6: VAR2 = VAR1 << VAR3;
7: VAR2 = VAR... | mit |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_103.v | 1,503 | module MODULE2 (
VAR3,
VAR10
);
input [31:0] VAR3;
output [31:0]
VAR10;
wire [31:0]
VAR13,
VAR14,
VAR6,
VAR11,
VAR7,
VAR9,
VAR8,
VAR2,
VAR5;
assign VAR13 = VAR3;
assign VAR2 = VAR7 << 1;
assign VAR6 = VAR14 - VAR13;
assign VAR14 = VAR13 << 8;
assign VAR11 = VAR13 << 2;
assign VAR7 = VAR13 + VAR11;
assign VAR9 = VAR6 <<... | mit |
jotego/jt51 | syn/xilinx/contra_snd/hdl/sd2_dac.v | 4,963 | module MODULE1 (
input clk, input [15:0] VAR28, input [15:0] VAR2, output reg VAR8=0, output reg VAR34=0 );
localparam VAR23 = 16;
localparam VAR38 = 2;
localparam VAR1 = 4;
localparam VAR41 = 2;
localparam VAR15 = 5;
wire [VAR23+2+0 -1:0] VAR33, VAR18;
reg [VAR23+2+0 -1:0] VAR20=0, VAR13=0;
wire [VAR23+VAR41+2-1:0] VA... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/analog/bw_tsr/rtl/bw_tsr.v | 1,558 | module MODULE1 (
VAR5,
VAR7,
clk,
VAR8,
VAR4,
dout,
VAR6,
VAR3,
VAR2,
VAR1);
input VAR5;
input [9:1] VAR7;
input clk;
input VAR8;
input [7:0] VAR4;
input VAR1;
output [7:0] dout;
output [1:0] VAR6;
output [7:0] VAR3;
output VAR2;
endmodule | gpl-2.0 |
jotego/jt51 | syn/xilinx/contra_snd/hdl/bus_manager.v | 1,977 | module MODULE1 #(parameter VAR16=10)(
input [7:0] VAR5,
input [7:0] VAR21,
input [7:0] VAR3,
input VAR18,
input [7:0] VAR22,
output VAR13,
output reg [7:0] VAR6,
input [15:0]addr,
input VAR14,
input VAR7,
output reg VAR15,
output reg VAR10
);
wire VAR24 = addr[15];
parameter VAR19 = 16'h6000;
parameter VAR12 = VAR19+(2... | gpl-3.0 |
jakubfi/mera400f | src/mem_elwro_sram.v | 1,695 | module MODULE1(
input clk,
input reset,
output VAR13,
output VAR11, VAR24, VAR6,
output [17:0] VAR8,
inout [15:0] VAR18,
input [0:3] VAR7,
input [0:15] VAR29,
output [0:15] VAR16,
input [0:15] VAR12,
input VAR5, VAR30, VAR9,
output VAR4
);
wire [0:7] VAR26 = { VAR12[12:15], VAR12[0:3] };
wire [0:7] VAR14 = { VAR29[11:1... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/buf/sky130_fd_sc_hs__buf_1.v | 1,866 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR4,
VAR2
);
output VAR5 ;
input VAR6 ;
input VAR4;
input VAR2;
VAR3 VAR1 (
.VAR5(VAR5),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR5,
VAR6
);
output VAR5;
input VAR6;
supply1 VAR4;
supply0 VAR2;
VAR3 VAR1 (
.VAR5(VAR5),
.VAR6(VAR6)
);
endmodule | apache-2.0 |
yyang29/MIPS | design/mips_mem.v | 17,427 | module MODULE1(VAR20,VAR2,VAR14,VAR23,VAR37,VAR21,VAR15,
VAR16,VAR7,VAR51,VAR41,VAR42,VAR3,VAR39,
VAR9,clk);
parameter
VAR13 = 32'h10000000,
VAR8 = 'h40000,
VAR56 = VAR8 * 4,
VAR33 = VAR13 + VAR56,
VAR44 = VAR13 >> 2,
VAR25 = VAR44 + VAR8,
VAR31 = 32'h00400000,
VAR22 = 'h10000,
VAR18 = VAR22 * 4,
VAR53 = VAR31 + VAR18,... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv3sd3/sky130_fd_sc_ls__clkdlyinv3sd3.symbol.v | 1,357 | module MODULE1 (
input VAR5,
output VAR2
);
supply1 VAR6;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
eda-globetrotter/MarcheProcessor | processor/syn/src/datamem.v | 2,477 | module MODULE1 (VAR3,VAR2,VAR4,clk,VAR1);
output [0:127] VAR3;
input [0:127] VAR2;
input [0:31] VAR4;
input clk;
input [0:1] VAR1;
reg [0:31] VAR3;
reg [0:127] MODULE1 [0:255];
begin
begin
begin
begin
begin
begin | mit |
timvideos/HDMI2USB-jahanzeb-firmware | hdl/hdmi/phsaligner.v | 8,897 | module MODULE1 # (
parameter VAR11 = 3, parameter VAR23 = 7, parameter VAR14 = 12 )
(
input wire rst,
input wire clk,
input wire [9:0] VAR24, output reg VAR15,
output reg VAR26,
output reg VAR1 );
parameter VAR13 = 10'b1101010100;
parameter VAR6 = 10'b0010101011;
parameter VAR29 = 10'b0101010100;
parameter VAR30 = 10'b... | bsd-2-clause |
danbone/core | risc_core_ref.v | 8,798 | module MODULE1 (
input clk,
input VAR67,
output [31:0] VAR20,
input [31:0] VAR41,
output [31:0] VAR65,
output VAR60,
output [31:0] VAR43,
input [31:0] VAR48
);
localparam VAR29 = 6'h00;
localparam VAR61 = 6'h01;
localparam VAR44 = 6'h02;
localparam VAR2 = 6'h03;
localparam VAR68 = 6'h04;
localparam VAR51 = 6'h05;
local... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_cache/bsg_cache_non_blocking_tag_mem.v | 5,319 | module MODULE1
import VAR14::*;
, parameter VAR49(VAR30)
, parameter VAR49(VAR25)
, parameter VAR49(VAR55)
, parameter VAR4=VAR46(VAR30)
, parameter VAR21=VAR46(VAR27)
, parameter VAR52=0
, parameter VAR45=
)
(
input VAR38
, input VAR56
, input VAR17
, input [VAR45-1:0] VAR22
, output logic [VAR30-1:0] VAR13
, output l... | bsd-3-clause |
AngelTerrones/ADA | rtl/ada_idex_stage.v | 6,065 | module MODULE1(
input clk, input rst, input [4:0] VAR32, input [31:0] VAR17, input [31:0] VAR1, input [31:0] VAR15, input VAR11, input VAR22, input VAR25, input VAR33, input VAR24, input VAR6, input [4:0] VAR8, input VAR20, input VAR35, input [31:0] VAR19, input VAR23, input VAR31, input VAR28, input VAR4, input VAR21,... | mit |
FPGA1988/udp_ip_stack | Network/udp_ip_core/trunk/ic/digital/rtl/eth_tri_mode/MAC_tx/MAC_tx_FF.v | 26,442 | module MODULE1 (
VAR25 ,
VAR91 ,
VAR2 ,
VAR33 ,
VAR90 ,
VAR61 ,
VAR51 ,
VAR93 ,
VAR99 ,
VAR79 ,
VAR37 ,
VAR21 ,
VAR71 ,
VAR53 ,
VAR65 ,
VAR6 ,
VAR70 ,
VAR87 ,
VAR55 ,
VAR105 ,
VAR38
);
input VAR25 ;
input VAR91 ;
input VAR2 ;
output [7:0] VAR33 ;
input VAR90 ;
input VAR61 ;
input VAR51 ;
output VAR93 ;
output VAR99 ;
o... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand3/sky130_fd_sc_ms__nand3.blackbox.v | 1,260 | module MODULE1 (
VAR1,
VAR3,
VAR5,
VAR6
);
output VAR1;
input VAR3;
input VAR5;
input VAR6;
supply1 VAR4;
supply0 VAR7;
supply1 VAR2 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_086.v | 1,438 | module MODULE2 (
VAR3,
VAR6
);
input [31:0] VAR3;
output [31:0]
VAR6;
wire [31:0]
VAR11,
VAR10,
VAR12,
VAR8,
VAR1,
VAR2,
VAR7;
assign VAR11 = VAR3;
assign VAR8 = VAR11 << 14;
assign VAR1 = VAR12 + VAR8;
assign VAR7 = VAR1 + VAR2;
assign VAR10 = VAR11 << 2;
assign VAR12 = VAR11 + VAR10;
assign VAR2 = VAR12 << 4;
assign ... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/projects/fmcadc4/common/fmcadc4_spi.v | 3,760 | module MODULE1 (
VAR4,
VAR2,
VAR1,
VAR16,
VAR13);
input [ 2:0] VAR4;
input VAR2;
input VAR1;
output VAR16;
inout VAR13;
reg [ 5:0] VAR15 = 'd0;
reg VAR12 = 'd0;
reg VAR5 = 'd0;
wire VAR9;
wire VAR8;
assign VAR9 = & VAR4;
assign VAR8 = VAR5 & ~VAR9;
always @(posedge VAR2 or posedge VAR9) begin
if (VAR9 == 1'b1) begin
VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inputiso0n/sky130_fd_sc_hdll__inputiso0n.symbol.v | 1,401 | module MODULE1 (
input VAR5 ,
output VAR3 ,
input VAR7
);
supply1 VAR4;
supply0 VAR2;
supply1 VAR6 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/decap/sky130_fd_sc_hvl__decap.functional.pp.v | 1,176 | module MODULE1 (
VAR1,
VAR4,
VAR2 ,
VAR3
);
input VAR1;
input VAR4;
input VAR2 ;
input VAR3 ;
endmodule | apache-2.0 |
borti4938/sd2snes | verilog/sd2snes_sa1/sd_dma.v | 3,981 | module MODULE1(
input [3:0] VAR8,
inout VAR9,
input VAR12,
input VAR6,
output VAR3,
output VAR17,
output VAR19,
output [7:0] VAR10,
input VAR5,
input [10:0] VAR13,
input [10:0] VAR7,
input VAR2,
input VAR20,
output [10:0] VAR18,
output [2:0] VAR1
);
reg [10:0] VAR15;
reg [10:0] VAR11;
reg VAR4;
always @(posedge VAR12) ... | gpl-2.0 |
jas0n1ee/THU-DSD | FB/pio_sw.v | 1,778 | module MODULE1 (
address,
clk,
VAR1,
VAR6,
VAR3
)
;
output [ 31: 0] VAR3;
input [ 1: 0] address;
input clk;
input [ 17: 0] VAR1;
input VAR6;
wire VAR5;
wire [ 17: 0] VAR2;
wire [ 17: 0] VAR4;
reg [ 31: 0] VAR3;
assign VAR5 = 1;
assign VAR4 = {18 {(address == 0)}} & VAR2;
always @(posedge clk or negedge VAR6)
begin
if (... | mit |
mlarouche/sd2snes | verilog/sd2snes_obc1/main.v | 17,681 | module MODULE1(
input VAR265,
input [23:0] VAR192,
input VAR121,
input VAR243,
input VAR203,
inout [7:0] VAR211,
input VAR60,
input VAR163,
output VAR156,
output VAR229,
output VAR261,
input VAR258,
input [7:0] VAR138,
input VAR184,
input VAR55,
inout [15:0] VAR63,
output [22:0] VAR204,
output VAR158,
output VAR31,
out... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffq/gf180mcu_fd_sc_mcu9t5v0__dffq_4.behavioral.pp.v | 2,179 | module MODULE1( VAR12, VAR4, VAR11, VAR6, VAR2 );
input VAR12, VAR4;
inout VAR6, VAR2;
output VAR11;
reg VAR8;
VAR5 VAR3(.VAR12(VAR12),.VAR4(VAR4),.VAR11(VAR11),.VAR6(VAR6),.VAR2(VAR2),.VAR8(VAR8));
VAR5 VAR13(.VAR12(VAR12),.VAR4(VAR4),.VAR11(VAR11),.VAR6(VAR6),.VAR2(VAR2),.VAR8(VAR8));
not VAR1(VAR7,VAR4);
buf VAR9(VA... | apache-2.0 |
sachitkuhar/amba_ahb | fifo.v | 1,254 | module MODULE1( VAR7, VAR5, VAR3);
input VAR5;
output VAR7;
input VAR3;
wire [3:0] VAR3;
wire VAR5;
reg VAR7;
reg [3:0] VAR2 [0:9];
int VAR8 = 0;
int VAR1 = 0;
int VAR4;
int VAR6;
begin
begin
begin
begin
begin
end
begin
begin
begin
begin
begin | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2bb2a/sky130_fd_sc_lp__o2bb2a.behavioral.v | 1,658 | module MODULE1 (
VAR1 ,
VAR6,
VAR4,
VAR9 ,
VAR10
);
output VAR1 ;
input VAR6;
input VAR4;
input VAR9 ;
input VAR10 ;
supply1 VAR8;
supply0 VAR15;
supply1 VAR5 ;
supply0 VAR16 ;
wire VAR14 ;
wire VAR13 ;
wire VAR7;
nand VAR12 (VAR14 , VAR4, VAR6 );
or VAR11 (VAR13 , VAR10, VAR9 );
and VAR3 (VAR7, VAR14, VAR13);
buf VAR2... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfstp/sky130_fd_sc_hdll__sdfstp.functional.pp.v | 2,185 | module MODULE1 (
VAR1 ,
VAR6 ,
VAR15 ,
VAR7 ,
VAR12 ,
VAR20,
VAR11 ,
VAR8 ,
VAR2 ,
VAR4
);
output VAR1 ;
input VAR6 ;
input VAR15 ;
input VAR7 ;
input VAR12 ;
input VAR20;
input VAR11 ;
input VAR8 ;
input VAR2 ;
input VAR4 ;
wire VAR18 ;
wire VAR9 ;
wire VAR13;
not VAR16 (VAR9 , VAR20 );
VAR3 VAR17 (VAR13, VAR15, VAR7,... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlygate4sd2/sky130_fd_sc_hs__dlygate4sd2.pp.blackbox.v | 1,256 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR1,
VAR4
);
output VAR3 ;
input VAR2 ;
input VAR1;
input VAR4;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor4/sky130_fd_sc_lp__nor4_m.v | 2,272 | module MODULE2 (
VAR3 ,
VAR11 ,
VAR1 ,
VAR8 ,
VAR4 ,
VAR9,
VAR5,
VAR7 ,
VAR2
);
output VAR3 ;
input VAR11 ;
input VAR1 ;
input VAR8 ;
input VAR4 ;
input VAR9;
input VAR5;
input VAR7 ;
input VAR2 ;
VAR10 VAR6 (
.VAR3(VAR3),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR... | apache-2.0 |
alan4186/Hardware-CNN | Hardware/fm_ram_1024w.v | 9,219 | module MODULE1 (
VAR25,
VAR31,
VAR49,
VAR5,
VAR38,
VAR3);
input VAR25;
input [23:0] VAR31;
input [9:0] VAR49;
input [9:0] VAR5;
input VAR38;
output [23:0] VAR3;
tri1 VAR25;
tri0 VAR38;
wire [23:0] VAR59;
wire [23:0] VAR3 = VAR59[23:0];
VAR20 VAR32 (
.VAR61 (VAR5),
.VAR39 (VAR49),
.VAR34 (VAR25),
.VAR15 (VAR31),
.VAR18 ... | mit |
parallella/oh | parallella/hdl/parallella_base.v | 14,163 | module MODULE1(
VAR71, VAR49, VAR85, VAR86, VAR93,
VAR97, VAR25, VAR43, VAR131, VAR76,
VAR92, VAR101, VAR128, VAR47, VAR9,
VAR37, VAR90, VAR14, VAR116,
VAR111, VAR130, VAR19, VAR5, VAR35,
VAR120, VAR113, VAR54, VAR55,
VAR102, VAR115, VAR23, VAR124,
VAR24, VAR48, VAR21, VAR74,
VAR119, VAR108, VAR56, VAR46, VAR75, VAR123... | mit |
asicguy/gplgpu | hdl/vga/addr_dec_gen.v | 24,279 | module MODULE1
(
input VAR32,
input VAR19,
input VAR84,
input VAR86,
input VAR111,
input VAR90,
input VAR92,
input VAR73,
input VAR102,
input [22:0] VAR69,
input VAR16, input [3:0] VAR45,
input VAR54,
input VAR97, input VAR43,
input VAR29,
input VAR21,
input VAR105, input [31:0] VAR64,
input [31:0] VAR78,
input [7:0] V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fahcon/sky130_fd_sc_lp__fahcon.behavioral.v | 1,829 | module MODULE1 (
VAR2,
VAR4 ,
VAR15 ,
VAR10 ,
VAR7
);
output VAR2;
output VAR4 ;
input VAR15 ;
input VAR10 ;
input VAR7 ;
supply1 VAR19;
supply0 VAR13;
supply1 VAR1 ;
supply0 VAR9 ;
wire VAR12 ;
wire VAR8 ;
wire VAR21 ;
wire VAR11 ;
wire VAR5;
xor VAR20 (VAR12 , VAR15, VAR10, VAR7 );
buf VAR6 (VAR4 , VAR12 );
nor VAR14... | apache-2.0 |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.ip_user_files/ipstatic/axi_crossbar_v2_1/hdl/verilog/axi_crossbar_v2_1_decerr_slave.v | 9,276 | module MODULE1 #
(
parameter integer VAR33 = 1,
parameter integer VAR13 = 32,
parameter integer VAR36 = 1,
parameter integer VAR38 = 1,
parameter integer VAR48 = 0,
parameter integer VAR8 = 2'b11
)
(
input wire VAR11,
input wire VAR4,
input wire [(VAR33-1):0] VAR26,
input wire VAR14,
output wire VAR6,
input wire VAR5,
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlrtn/sky130_fd_sc_ls__dlrtn_4.v | 2,358 | module MODULE2 (
VAR1 ,
VAR4,
VAR5 ,
VAR8 ,
VAR3 ,
VAR2 ,
VAR10 ,
VAR6
);
output VAR1 ;
input VAR4;
input VAR5 ;
input VAR8 ;
input VAR3 ;
input VAR2 ;
input VAR10 ;
input VAR6 ;
VAR7 VAR9 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR6(VAR6)
);
endmodule
module MODU... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_isolatch_pp_pkg_sn/sky130_fd_sc_hs__udp_isolatch_pp_pkg_sn.blackbox.v | 1,550 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR4 ,
VAR7,
VAR1 ,
VAR2 ,
VAR6
);
output VAR3 ;
input VAR5 ;
input VAR4 ;
input VAR7;
input VAR1 ;
input VAR2 ;
input VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or2b/sky130_fd_sc_hs__or2b_4.v | 2,000 | module MODULE1 (
VAR7 ,
VAR2 ,
VAR1 ,
VAR6,
VAR3
);
output VAR7 ;
input VAR2 ;
input VAR1 ;
input VAR6;
input VAR3;
VAR4 VAR5 (
.VAR7(VAR7),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR7 ,
VAR2 ,
VAR1
);
output VAR7 ;
input VAR2 ;
input VAR1;
supply1 VAR6;
supply0 VAR3;
VAR4 VAR5... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand4/sky130_fd_sc_lp__nand4.behavioral.v | 1,408 | module MODULE1 (
VAR8,
VAR9,
VAR3,
VAR1,
VAR7
);
output VAR8;
input VAR9;
input VAR3;
input VAR1;
input VAR7;
supply1 VAR12;
supply0 VAR11;
supply1 VAR4 ;
supply0 VAR5 ;
wire VAR6;
nand VAR2 (VAR6, VAR7, VAR1, VAR3, VAR9 );
buf VAR10 (VAR8 , VAR6 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21boi/sky130_fd_sc_ms__a21boi.behavioral.pp.v | 2,172 | module MODULE1 (
VAR14 ,
VAR7 ,
VAR2 ,
VAR11,
VAR18,
VAR15,
VAR10 ,
VAR3
);
output VAR14 ;
input VAR7 ;
input VAR2 ;
input VAR11;
input VAR18;
input VAR15;
input VAR10 ;
input VAR3 ;
wire VAR12 ;
wire VAR6 ;
wire VAR1 ;
wire VAR5;
not VAR8 (VAR12 , VAR11 );
and VAR17 (VAR6 , VAR7, VAR2 );
nor VAR13 (VAR1 , VAR12, VAR6 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4.v | 2,479 | module MODULE1 (
VAR3 ,
VAR4,
VAR6,
VAR2 ,
VAR7 ,
VAR1,
VAR8,
VAR10 ,
VAR5
);
output VAR3 ;
input VAR4;
input VAR6;
input VAR2 ;
input VAR7 ;
input VAR1;
input VAR8;
input VAR10 ;
input VAR5 ;
VAR11 VAR9 (
.VAR3(VAR3),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR5(VA... | apache-2.0 |
TalentlessAlpaca/Automated_Vacuum_Cleaner | Ultrasonico/peripheral_ult.v | 1,797 | module MODULE1(
input clk,
input rst,
input [15:0] din, input VAR7, input [3:0] addr, input rd, input wr, input VAR3,
output reg [15:0] dout );
reg [1:0] VAR2; wire [15:0] VAR5 ;
wire VAR1 ;
reg enable ;
always @(*) begin case (addr)
4'h0: VAR2 = (VAR7 && wr) ? 4'b0001 : 4'b000 ;
4'h2: VAR2 = (VAR7 && rd) ? 4'b0010 : 4... | mit |
fallen/milkymist-mmu | cores/minimac2/rtl/minimac2_sync.v | 2,185 | module MODULE1(
input VAR21,
input VAR20,
input VAR24,
input [1:0] VAR25,
output [1:0] VAR16,
output reg [10:0] VAR17,
output reg [10:0] VAR19,
input VAR8,
output VAR14,
input [10:0] VAR6,
output [1:0] VAR26,
input [1:0] VAR4,
input [10:0] VAR5,
input [10:0] VAR13,
output VAR7,
input VAR30,
output reg [10:0] VAR10
);
V... | lgpl-3.0 |
ShirmanXia/EE469SPRING16 | lab3/nios_system/synthesis/submodules/nios_system_nios2_qsys_0_cpu_debug_slave_tck.v | 8,631 | module MODULE1 (
VAR37,
VAR29,
VAR14,
VAR24,
VAR6,
VAR26,
VAR32,
VAR34,
VAR21,
VAR12,
VAR25,
VAR38,
VAR13,
VAR39,
VAR27,
VAR22,
VAR20,
VAR4,
VAR15,
VAR40,
VAR16,
VAR8,
VAR31,
VAR5,
VAR35,
VAR19,
VAR17,
VAR36,
VAR23,
VAR33,
VAR3
)
;
output [ 1: 0] VAR17;
output VAR36;
output [ 37: 0] VAR23;
output VAR33;
output VAR3;
in... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_2.functional.pp.v | 1,751 | module MODULE1( VAR12, VAR2, VAR22, VAR3, VAR1, VAR21, VAR9, VAR16, VAR25 );
input VAR3, VAR22, VAR12, VAR1, VAR2, VAR9, VAR16, VAR25;
output VAR21;
not VAR28( VAR19, VAR1 );
wire VAR23;
not VAR17( VAR23, VAR22 );
wire VAR4;
not VAR8( VAR4, VAR12 );
wire VAR10;
and VAR13( VAR10, VAR23, VAR4 );
wire VAR24;
not VAR27( VA... | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ipshared/55c0/hdl/axi_register_slice_v2_1_vl_rfs.v | 42,081 | module MODULE1 #
(
parameter VAR9 = 2 )
(
input wire clk, input wire [VAR9-1:0] VAR15, input wire VAR23, input wire VAR35, output wire VAR41 );
localparam integer VAR31 = 2**VAR9;
reg [VAR31-1:0] VAR1 = {VAR31{1'b0}};
always @(posedge clk)
if (VAR23)
VAR1 <= {VAR1[VAR31-2:0], VAR35};
assign VAR41 = VAR1[VAR15];
endmodu... | mit |
antmicro/yosys | techlibs/intel/common/m9k_bb.v | 3,076 | module MODULE1(VAR41, VAR11, VAR1, VAR55, VAR40, VAR29, VAR50, VAR39, VAR45,
VAR57, VAR28, VAR26, VAR30, VAR12, VAR48, VAR37, VAR35, VAR20,
VAR10, VAR15);
parameter VAR46 = "VAR23";
parameter VAR34 = "VAR23";
parameter VAR21 = "VAR19";
parameter VAR44 = "VAR19";
parameter VAR53 = "VAR2";
parameter VAR54 = "VAR2";
param... | isc |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/system/synthesis/submodules/system_acl_iface_hps.v | 16,175 | module MODULE1 #(
parameter VAR81 = 0,
parameter VAR84 = 0
) (
output wire VAR22, input wire VAR44, output wire [11:0] VAR15, output wire [20:0] VAR85, output wire [3:0] VAR13, output wire [2:0] VAR86, output wire [1:0] VAR28, output wire [1:0] VAR69, output wire [3:0] VAR33, output wire [2:0] VAR91, output wire VAR87,... | mit |
Willster419/ELEC3725_vivado_projects | assignment_5/controller.v | 12,071 | module MODULE1(VAR1, clk, VAR10, VAR12, VAR22, VAR19, VAR20, VAR9);
input [31:0] VAR1;
input clk;
output [31:0] VAR19;
output [31:0] VAR20;
output [31:0] VAR9;
output [2:0] VAR22;
output VAR12;
output VAR10;
reg VAR8;
reg [2:0] VAR3;
reg VAR5;
wire [31:0] VAR14; wire [31:0] VAR21; wire [4:0] VAR11; wire [4:0] VAR6;
wir... | gpl-3.0 |
CospanDesign/python | game/panda/panda_path/example_project/rtl/top.v | 14,942 | module MODULE1 (
output VAR219,
output VAR157,
output VAR184,
output VAR177,
input clk,
input VAR128,
input VAR166,
input VAR50,
output VAR80,
output VAR256,
output [11:0] VAR148,
output VAR249,
output VAR23,
input [1:0] VAR227,
inout [15:0] VAR30,
input VAR124,
output [1:0] VAR132,
output [1:0] VAR194,
input rst,
outp... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and3b/sky130_fd_sc_hdll__and3b.symbol.v | 1,315 | module MODULE1 (
input VAR5,
input VAR1 ,
input VAR6 ,
output VAR2
);
supply1 VAR3;
supply0 VAR8;
supply1 VAR7 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
cpulabs/mist1032sa | src/core/scheduler2/scheduler2_free_search_64to2.v | 51,851 | module MODULE1(
input wire VAR120,
input wire VAR29,
input wire VAR6,
input wire VAR60,
input wire VAR18,
input wire VAR93,
input wire VAR45,
input wire VAR25,
input wire VAR59,
input wire VAR89,
input wire VAR64,
input wire VAR43,
input wire VAR150,
input wire VAR77,
input wire VAR8,
input wire VAR144,
input wire VAR9... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdlclkp/sky130_fd_sc_hdll__sdlclkp.pp.symbol.v | 1,340 | module MODULE1 (
input VAR6 ,
input VAR4 ,
input VAR1,
output VAR5,
input VAR3 ,
input VAR2,
input VAR8,
input VAR7
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a222oi/sky130_fd_sc_hs__a222oi.functional.v | 2,307 | module MODULE1 (
VAR9 ,
VAR19 ,
VAR4 ,
VAR6 ,
VAR3 ,
VAR18 ,
VAR5 ,
VAR15,
VAR11
);
output VAR9 ;
input VAR19 ;
input VAR4 ;
input VAR6 ;
input VAR3 ;
input VAR18 ;
input VAR5 ;
input VAR15;
input VAR11;
wire VAR3 VAR13 ;
wire VAR3 VAR21 ;
wire VAR3 VAR12 ;
wire VAR8 ;
wire VAR10;
nand VAR1 (VAR13 , VAR4, VAR19 );
nand... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_mem/bsg_mem_1r1w_sync_mask_write_bit.v | 3,261 | if (VAR11 == VAR39 && VAR2 == VAR41) \
begin: VAR25 \
VAR23 VAR22 \
( \
.VAR16 (VAR8 ) \
,.VAR15 (VAR29) \
,.VAR6(~VAR5 ) \
,.VAR38 (VAR17) \
\
,.VAR43(VAR8 ) \
,.VAR35(~VAR12) \
,.VAR33(~VAR28) \
,.VAR13 (VAR36) \
,.VAR19 (VAR44) \
); \
end
module MODULE1 #(parameter VAR10(VAR2)
, parameter VAR10(VAR11)
, parameter VA... | bsd-3-clause |
jameshegarty/rigel | generators/hardfloat/source/recFNToFN.v | 3,465 | module
MODULE1#(parameter VAR6 = 3, parameter VAR3 = 3) (
input [(VAR6 + VAR3):0] in,
output [(VAR6 + VAR3 - 1):0] out
);
localparam [VAR6:0] VAR5 = (1<<(VAR6 - 1)) + 2;
localparam VAR9 = VAR16(VAR3);
wire VAR12, VAR4, VAR10, VAR8;
wire signed [(VAR6 + 1):0] VAR13;
wire [VAR3:0] VAR15;
VAR14#(VAR6, VAR3)
VAR14(in, VAR1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlrtn/sky130_fd_sc_ms__dlrtn.behavioral.pp.v | 2,446 | module MODULE1 (
VAR11 ,
VAR2,
VAR13 ,
VAR4 ,
VAR20 ,
VAR1 ,
VAR17 ,
VAR18
);
output VAR11 ;
input VAR2;
input VAR13 ;
input VAR4 ;
input VAR20 ;
input VAR1 ;
input VAR17 ;
input VAR18 ;
wire VAR7 ;
wire VAR9 ;
reg VAR3 ;
wire VAR6 ;
wire VAR12 ;
wire VAR5 ;
wire VAR10;
wire VAR21 ;
wire VAR24 ;
wire VAR19 ;
wire VAR15... | apache-2.0 |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_rx.v | 8,247 | module MODULE1 #(
parameter VAR15 = 128, parameter VAR29 = "VAR8", parameter VAR2 = "VAR28", parameter VAR22 = "VAR28", parameter VAR14 = 1,
parameter VAR24 = (VAR15 == 128) ? 2 : 1, parameter VAR6 = VAR15 / 8 ) (
output [VAR15-1:0] VAR30, output VAR23, input VAR1, output [VAR6-1:0] VAR33, output VAR34, output [21:0] V... | lgpl-3.0 |
niketancm/tsea26 | lab2-3/rtl/register_file.v | 1,499 | module MODULE1
parameter VAR8 = VAR19)
(
input wire VAR4,
input wire VAR12,
input wire [VAR8-1:0] VAR11,
input wire [VAR7-1:0] VAR3,
input wire [VAR8-1:0] VAR23,
input wire [VAR8-1:0] VAR6,
input wire VAR9,
output reg [VAR8-1:0] VAR5,
output reg [VAR8-1:0] VAR15
);
reg [VAR8-1:0] VAR10 [31:0];
wire [VAR8-1:0] VAR14;
wi... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_power_lvc_wpad/sky130_fd_io__top_power_lvc_wpad.behavioral.v | 1,157 | module MODULE1 ( VAR11, VAR21, VAR19
);
inout VAR11;
inout VAR21;
inout VAR19;
supply0 VAR6;
supply0 VAR14;
supply1 VAR16;
supply1 VAR4;
supply1 VAR7;
supply0 VAR3;
supply1 VAR5;
supply1 VAR15;
supply1 VAR13;
supply1 VAR1;
supply1 VAR20;
supply1 VAR9;
supply1 VAR10;
supply1 VAR18;
supply1 VAR12;
supply0 VAR17;
supply0 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand2/sky130_fd_sc_hd__nand2.behavioral.pp.v | 1,792 | module MODULE1 (
VAR8 ,
VAR10 ,
VAR4 ,
VAR13,
VAR6,
VAR12 ,
VAR5
);
output VAR8 ;
input VAR10 ;
input VAR4 ;
input VAR13;
input VAR6;
input VAR12 ;
input VAR5 ;
wire VAR9 ;
wire VAR1;
nand VAR11 (VAR9 , VAR4, VAR10 );
VAR2 VAR3 (VAR1, VAR9, VAR13, VAR6);
buf VAR7 (VAR8 , VAR1 );
endmodule | apache-2.0 |
lokisz/openzcore | pippo-riscv/rtl/verilog/reg_2r1w_generic.v | 7,198 | module MODULE1(
clk,
rst,
VAR33,
VAR37,
VAR40,
VAR1,
VAR46,
VAR42,
VAR35,
VAR19,
VAR26
);
parameter VAR43 = VAR49;
input clk;
input rst;
input VAR33;
input VAR1;
input VAR23;
input [4:0] VAR37;
input [4:0] VAR46;
input [4:0] VAR24;
output [VAR43-1:0] VAR40;
output [VAR43-1:0] VAR42;
output [VAR43-1:0] VAR18;
input VAR3... | gpl-2.0 |
AmeerAbdelhadi/Switched-Multiported-RAM | mpram_reg.v | 4,941 | module MODULE1
localparam VAR1 = VAR15(VAR4); integer VAR13;
reg [VAR2-1:0] VAR12 [0:VAR4-1]; VAR17
if (VAR6)
for (VAR13=0; VAR13<VAR4; VAR13=VAR13+1) VAR12[VAR13] = {VAR2{1'b0}};
else
if (VAR10 != "")
always @(posedge clk) begin
for (VAR13=1; VAR13<=VAR7; VAR13=VAR13+1)
if (VAR3[VAR13-1])
end
if (VAR11) VAR12[VAR5[VAR... | bsd-3-clause |
kramble/FPGA-Litecoin-Miner | experimental/LX150-EIGHT-B/salsa_piped.v | 8,193 | module MODULE2 (clk, VAR166, VAR62, VAR163, VAR86, VAR70, VAR167, VAR118);
input clk;
input VAR166;
input [511:0]VAR62;
input [511:0]VAR163;
output [511:0]VAR86;
output [511:0]VAR70; output [511:0]VAR167; output [9:0]VAR118;
wire [511:0]VAR3; wire [511:0]VAR169;
wire [511:0]VAR154; reg [511:0]VAR180;
wire [9:0]addr; re... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o21ai/sky130_fd_sc_ms__o21ai.behavioral.pp.v | 2,010 | module MODULE1 (
VAR12 ,
VAR4 ,
VAR7 ,
VAR16 ,
VAR10,
VAR9,
VAR8 ,
VAR6
);
output VAR12 ;
input VAR4 ;
input VAR7 ;
input VAR16 ;
input VAR10;
input VAR9;
input VAR8 ;
input VAR6 ;
wire VAR14 ;
wire VAR15 ;
wire VAR11;
or VAR3 (VAR14 , VAR7, VAR4 );
nand VAR1 (VAR15 , VAR16, VAR14 );
VAR2 VAR13 (VAR11, VAR15, VAR10, VA... | apache-2.0 |
eda-globetrotter/MarcheProcessor | processor/spare/build1/alicia.v | 1,658 | module MODULE1();
reg VAR3;
reg VAR5;
reg VAR2;
reg VAR4;
reg VAR6;
reg [1:0] VAR10;
reg VAR1;
reg VAR8;
reg [0:7] VAR11;
reg [0:7] VAR7;
reg [0:7] VAR9;
begin | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or4b/sky130_fd_sc_ls__or4b.pp.symbol.v | 1,318 | module MODULE1 (
input VAR7 ,
input VAR9 ,
input VAR5 ,
input VAR1 ,
output VAR3 ,
input VAR8 ,
input VAR4,
input VAR2,
input VAR6
);
endmodule | apache-2.0 |
jbelloncastro/amber_arm | hw/vlog/ethmac/eth_macstatus.v | 12,259 | module MODULE1(
VAR44, VAR31, VAR35, VAR24, VAR36, VAR28,
VAR7, VAR12, VAR1, VAR47, VAR37, VAR33, VAR49,
VAR52, VAR23, VAR6, VAR19,
VAR20, VAR21, VAR3, VAR14, VAR27, VAR18,
VAR29, VAR34, VAR11, VAR26, VAR16, VAR54, VAR55,
VAR25, VAR56, VAR42, VAR46, VAR48, VAR10, VAR8,
VAR41, VAR17, VAR30, VAR38, VAR2, VAR39, VAR51,
VA... | lgpl-3.0 |
P3Stor/P3Stor | DDR3/clk_wiz_v3_6.v | 7,163 | module MODULE1
( input VAR4,
output VAR59,
output VAR79,
output VAR83
);
VAR33 VAR44
(.VAR42 (VAR11),
.VAR27 (VAR4));
wire [15:0] VAR45;
wire VAR43;
wire VAR66;
wire VAR77;
wire VAR64;
wire VAR13;
wire VAR54;
wire VAR81;
wire VAR56;
wire VAR35;
wire VAR22;
wire VAR52;
wire VAR18;
wire VAR30;
wire VAR8;
wire VAR71;
wire... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a21oi/sky130_fd_sc_hs__a21oi.pp.symbol.v | 1,319 | module MODULE1 (
input VAR6 ,
input VAR1 ,
input VAR5 ,
output VAR2 ,
input VAR4,
input VAR3
);
endmodule | apache-2.0 |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/Source/main.v | 23,631 | module MODULE1(
input VAR5,
input [17:0] VAR233,
input [3:0] VAR69,
output [17:0] VAR13,
output [8:0] VAR8,
output [6:0] VAR32, VAR115, VAR205, VAR175, VAR118, VAR248, VAR120, VAR185,
inout [31:0] VAR38, VAR150,
output VAR148, output VAR7, output VAR244, output VAR101, output VAR20, inout [7:0] VAR157,
inout [31:0] VAR... | gpl-2.0 |
ak-fau/fpga-cyclone_iv | bemicro/alt_rom_bb.v | 5,053 | module MODULE1 (
address,
VAR2,
VAR1);
input [11:0] address;
input VAR2;
output [31:0] VAR1;
tri1 VAR2;
endmodule | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkinvlp/sky130_fd_sc_lp__clkinvlp.functional.pp.v | 1,796 | module MODULE1 (
VAR4 ,
VAR12 ,
VAR5,
VAR11,
VAR7 ,
VAR3
);
output VAR4 ;
input VAR12 ;
input VAR5;
input VAR11;
input VAR7 ;
input VAR3 ;
wire VAR6 ;
wire VAR9;
not VAR1 (VAR6 , VAR12 );
VAR2 VAR8 (VAR9, VAR6, VAR5, VAR11);
buf VAR10 (VAR4 , VAR9 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a31o/sky130_fd_sc_lp__a31o.symbol.v | 1,361 | module MODULE1 (
input VAR8,
input VAR2,
input VAR3,
input VAR6,
output VAR7
);
supply1 VAR1;
supply0 VAR9;
supply1 VAR4 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
asicguy/gplgpu | hdl/math/flt_add_sub.v | 7,597 | module MODULE1
(
input clk,
input VAR10,
input [31:0] VAR35,
input [31:0] VAR54,
output reg [31:0] VAR27
);
reg [24:0] VAR29; reg [24:0] VAR24; reg VAR51;
reg [7:0] VAR57; reg [24:0] VAR21; reg [24:0] VAR28; reg [24:0] VAR52; reg VAR53; reg [24:0] VAR40; reg [31:0] VAR22;
reg [31:0] VAR38;
reg VAR47;
reg VAR16;
reg VAR... | gpl-3.0 |
parallella/oh | common/hdl/oh_mux7.v | 1,203 | module MODULE1 #(parameter VAR6 = 1 ) (
input VAR3,
input VAR10,
input VAR11,
input VAR15,
input VAR1,
input VAR5,
input VAR4,
input [VAR6-1:0] VAR8,
input [VAR6-1:0] VAR2,
input [VAR6-1:0] VAR7,
input [VAR6-1:0] VAR14,
input [VAR6-1:0] VAR9,
input [VAR6-1:0] VAR12,
input [VAR6-1:0] VAR13,
output [VAR6-1:0] out );
assi... | mit |
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