repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
Elphel/x393_sata | ahci/axi_hp_abort.v | 6,097 | module MODULE1(
input VAR37,
input VAR40, input VAR16,
output VAR28, output reg VAR35,
input VAR31, input VAR38, input [ 5:0] VAR32,
input [3:0] VAR25,
input VAR6,
input VAR8,
output VAR22,
output reg [ 5:0] VAR1,
input VAR9,
input VAR2,
input [ 3:0] VAR20,
input VAR13,
input VAR19,
output VAR41,
output VAR45,
input [ ... | gpl-3.0 |
zhelnio/ahb_lite_eic | src/mfp_ahb_lite_eic.v | 3,211 | module MODULE1
(
input VAR13,
input VAR34,
input [ 31 : 0 ] VAR22,
input [ 2 : 0 ] VAR20,
input VAR24, input [ 3 : 0 ] VAR7, input VAR36,
input [ 2 : 0 ] VAR30,
input [ 1 : 0 ] VAR28,
input [ 31 : 0 ] VAR5,
input VAR35,
output reg [ 31 : 0 ] VAR26,
output VAR29,
output VAR2,
input VAR40,
input [ VAR4-1 : 0 ] VAR19,
out... | mit |
nikhilghanathe/HLS-for-EMTF | verilog/sp_mux_16to1_sel4_7_1.v | 2,926 | module MODULE1 #(
parameter
VAR29 = 0,
VAR50 = 1,
VAR40 = 32,
VAR36 = 32,
VAR14 = 32,
VAR9 = 32,
VAR20 = 32,
VAR1 = 32,
VAR25 = 32,
VAR34 = 32,
VAR27 = 32,
VAR15 = 32,
VAR52 = 32,
VAR39 = 32,
VAR30 = 32,
VAR44 = 32,
VAR46 = 32,
VAR7 = 32,
VAR17 = 32,
VAR10 = 32
)(
input [6 : 0] VAR23,
input [6 : 0] VAR8,
input [6 : 0] ... | apache-2.0 |
lvd2/zxevo | unsupported/solegstar/fpga/current/mem/atm_pager.v | 5,792 | module MODULE1(
input wire VAR7,
input wire VAR36,
input wire VAR3,
input wire VAR21,
input wire [15:0] VAR17,
input wire [ 7:0] VAR31,
input wire VAR27,VAR13,VAR24,
input wire VAR26,
input wire VAR33, input wire [ 5:0] VAR4, input wire VAR1, input wire VAR16,
input wire VAR29,
input wire VAR18,
input wire VAR15,
outpu... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfbbp/sky130_fd_sc_ls__sdfbbp.functional.v | 2,286 | module MODULE1 (
VAR4 ,
VAR21 ,
VAR6 ,
VAR11 ,
VAR17 ,
VAR7 ,
VAR9 ,
VAR19
);
output VAR4 ;
output VAR21 ;
input VAR6 ;
input VAR11 ;
input VAR17 ;
input VAR7 ;
input VAR9 ;
input VAR19;
wire VAR12 ;
wire VAR15 ;
wire VAR1 ;
wire VAR5;
not VAR14 (VAR12 , VAR19 );
not VAR13 (VAR15 , VAR9 );
VAR16 VAR8 (VAR5, VAR6, VAR11... | apache-2.0 |
nyaxt/dmix | resample_pipeline.v | 6,310 | module MODULE1
parameter VAR63 = 8,
parameter VAR25 = 3,
parameter VAR36 = 5
)(
input wire clk,
input wire rst,
input wire [(VAR63-1):0] VAR29,
input wire [(VAR36*VAR63-1):0] VAR37,
input wire [(VAR63-1):0] VAR28,
input wire [(24*VAR63-1):0] VAR68,
output wire [(VAR63-1):0] VAR38,
input wire [(VAR63-1):0] VAR60,
output... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/and2/gf180mcu_fd_sc_mcu9t5v0__and2_2.behavioral.v | 1,178 | module MODULE1( VAR2, VAR3, VAR1 );
input VAR2, VAR3;
output VAR1;
VAR6 VAR4(.VAR2(VAR2),.VAR3(VAR3),.VAR1(VAR1));
VAR6 VAR5(.VAR2(VAR2),.VAR3(VAR3),.VAR1(VAR1)); | apache-2.0 |
AngelTerrones/MUSB | Boards/xilinx_diligent_s3/bench/verilog/IS61LV25616AL.v | 2,279 | module MODULE1 (VAR2, VAR7, VAR4, VAR16, VAR10, VAR19, VAR14);
parameter VAR11 = 16;
parameter VAR18 = 262143;
parameter VAR15 = 18;
parameter VAR17 = 2;
parameter VAR5 = 2;
parameter VAR12 = 10,
VAR1 = 3,
VAR8 = 5;
parameter VAR12 = 12,
VAR1 = 5,
VAR8 = 6;
input VAR4, VAR16, VAR10, VAR19, VAR14;
input [(VAR15 - 1) : 0... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2/d5e322d2745b1271/zqynq_lab_1_design_axi_bram_ctrl_0_0_stub.v | 4,104 | module MODULE1(VAR40, VAR38, VAR47,
VAR50, VAR29, VAR31, VAR5, VAR30, VAR4,
VAR1, VAR44, VAR15, VAR16, VAR49, VAR39,
VAR48, VAR24, VAR34, VAR21, VAR42, VAR46, VAR36,
VAR11, VAR26, VAR28, VAR10, VAR32, VAR8,
VAR17, VAR18, VAR45, VAR6, VAR2, VAR37, VAR33,
VAR7, VAR3, VAR25, VAR41, VAR19, VAR14, VAR22,
VAR43, VAR35, VAR12... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a211o/sky130_fd_sc_hs__a211o_4.v | 2,221 | module MODULE1 (
VAR7 ,
VAR9 ,
VAR4 ,
VAR5 ,
VAR8 ,
VAR3,
VAR1
);
output VAR7 ;
input VAR9 ;
input VAR4 ;
input VAR5 ;
input VAR8 ;
input VAR3;
input VAR1;
VAR6 VAR2 (
.VAR7(VAR7),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR7 ,
VAR9,
VAR4,
VAR5,
VAR8
);... | apache-2.0 |
tmolteno/TART | hardware/FPGA/tart_spi/verilog/correlator/bank_switch.v | 4,004 | module MODULE1
parameter VAR10 = VAR20-1,
parameter VAR13 = 4,
parameter VAR16 = VAR13-1,
parameter VAR23 = 3)
(
input VAR8, input VAR11,
input VAR15, input VAR19,
input VAR22,
input [VAR10:0] VAR14, input VAR4, output VAR6, output VAR21 );
reg VAR5 = 1'b0, VAR1 = 1'b0;
reg VAR3 = 0, VAR18 = 0; reg VAR7 = 1'b0;
assign ... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/isobufsrc/sky130_fd_sc_hdll__isobufsrc_8.v | 2,258 | module MODULE2 (
VAR6 ,
VAR7,
VAR2 ,
VAR3 ,
VAR4 ,
VAR8 ,
VAR9
);
output VAR6 ;
input VAR7;
input VAR2 ;
input VAR3 ;
input VAR4 ;
input VAR8 ;
input VAR9 ;
VAR1 VAR5 (
.VAR6(VAR6),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR9(VAR9)
);
endmodule
module MODULE2 (
VAR6 ,
VAR7,
VAR2
);
output VAR... | apache-2.0 |
ultraembedded/riscv | top_tcm_axi/src_v/dport_mux.v | 6,844 | module MODULE1
parameter VAR2 = 0
)
(
input VAR25
,input VAR32
,input [ 31:0] VAR47
,input [ 31:0] VAR9
,input VAR35
,input [ 3:0] VAR41
,input VAR21
,input [ 10:0] VAR28
,input VAR27
,input VAR49
,input VAR44
,input [ 31:0] VAR24
,input VAR48
,input VAR22
,input VAR29
,input [ 10:0] VAR1
,input [ 31:0] VAR34
,input VA... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlymetal6s4s/sky130_fd_sc_lp__dlymetal6s4s.behavioral.v | 1,441 | module MODULE1 (
VAR3,
VAR5
);
output VAR3;
input VAR5;
supply1 VAR6;
supply0 VAR9;
supply1 VAR1 ;
supply0 VAR8 ;
wire VAR2;
buf VAR4 (VAR2, VAR5 );
buf VAR7 (VAR3 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o22ai/sky130_fd_sc_ms__o22ai.blackbox.v | 1,364 | module MODULE1 (
VAR5 ,
VAR4,
VAR1,
VAR3,
VAR8
);
output VAR5 ;
input VAR4;
input VAR1;
input VAR3;
input VAR8;
supply1 VAR2;
supply0 VAR7;
supply1 VAR9 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/mux4/sky130_fd_sc_hs__mux4.blackbox.v | 1,303 | module MODULE1 (
VAR8 ,
VAR7,
VAR3,
VAR6,
VAR5,
VAR1,
VAR4
);
output VAR8 ;
input VAR7;
input VAR3;
input VAR6;
input VAR5;
input VAR1;
input VAR4;
supply1 VAR9;
supply0 VAR2;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlygate4sd3/sky130_fd_sc_hs__dlygate4sd3.pp.blackbox.v | 1,256 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR3,
VAR1
);
output VAR2 ;
input VAR4 ;
input VAR3;
input VAR1;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffnsnq/gf180mcu_fd_sc_mcu9t5v0__dffnsnq_4.behavioral.v | 3,781 | module MODULE1( VAR9, VAR17, VAR30, VAR27 );
input VAR9, VAR17, VAR30;
output VAR27;
reg VAR22;
VAR29 VAR26(.VAR9(VAR9),.VAR17(VAR17),.VAR30(VAR30),.VAR27(VAR27),.VAR22(VAR22));
VAR29 VAR24(.VAR9(VAR9),.VAR17(VAR17),.VAR30(VAR30),.VAR27(VAR27),.VAR22(VAR22));
not VAR15(VAR8,VAR17);
and VAR19(VAR20,VAR30,VAR8);
and VAR3... | apache-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_gsu/ipcore_dir/gsu_umult.v | 6,162 | module MODULE2 (
VAR34, VAR3, VAR24
);
output [15 : 0] VAR34;
input [7 : 0] VAR3;
input [7 : 0] VAR24;
wire \VAR37/VAR7 ;
wire \VAR46/VAR4<35>VAR22 ;
wire \VAR46/VAR4<34>VAR22 ;
wire \VAR46/VAR4<33>VAR22 ;
wire \VAR46/VAR4<32>VAR22 ;
wire \VAR46/VAR4<31>VAR22 ;
wire \VAR46/VAR4<30>VAR22 ;
wire \VAR46/VAR4<29>VAR22 ;
wi... | gpl-2.0 |
onchipuis/mriscv_vivado | mriscv_vivado.srcs/sources_1/ip/ddr2/ddr2/example_design/rtl/traffic_gen/mig_7series_v4_0_tg_status.v | 4,748 | module MODULE1 #(
parameter VAR7 = 100,
parameter VAR6 = 32
)
(
input VAR8 ,
input VAR13 ,
input VAR9,
input VAR4 ,
input [VAR6-1:0] VAR17,
input [VAR6-1:0] VAR14 ,
input [31:0] VAR3 ,
input [5:0] VAR10 ,
input VAR1 ,
input VAR11,
input VAR12,
output reg [64 + (2*VAR6 - 1):0] VAR5,
output VAR15
);
reg VAR2;
reg VAR16;
... | mit |
cfangmeier/VFPIX-telescope-Code | DAQ_Firmware/src/misc_ip/lshift.v | 4,295 | module MODULE1 (
VAR9,
VAR5,
VAR2,
VAR3,
VAR15);
input wire [31:0] VAR9;
input wire [4:0] VAR5;
output wire VAR2;
output wire [31:0] VAR3;
output wire VAR15;
VAR13 VAR11 (
.VAR9 (VAR9),
.VAR1 (1'h0),
.VAR5 (VAR5),
.VAR2 (VAR2),
.VAR3 (VAR3),
.VAR15 (VAR15)
,
.VAR17 (),
.VAR16 (),
.VAR6 ()
);
VAR11.VAR10 = "VAR8",
VAR1... | gpl-2.0 |
petrmikheev/miksys | verilog/CHARMAP_bb.v | 4,992 | module MODULE1 (
address,
VAR1,
VAR2);
input [8:0] address;
input VAR1;
output [17:0] VAR2;
tri1 VAR1;
endmodule | gpl-3.0 |
subailong/miaow | src/verilog/rtl/issue/busy_gpr_table.v | 13,057 | module MODULE1
(
VAR20, VAR105,
VAR51, VAR60,
VAR108, VAR28,
clk, rst, VAR43, VAR86, VAR68,
VAR17, VAR7, VAR38,
VAR82, VAR18, VAR93,
VAR40, VAR31, VAR14, VAR92,
VAR53, VAR100, VAR64,
VAR15, VAR61,
VAR65, VAR57,
VAR56, VAR41,
VAR70, VAR63
);
input clk,rst;
input VAR43, VAR86;
input [VAR39-1:0] VAR68, VAR17, VAR7;
input ... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srdlrtp/sky130_fd_sc_lp__srdlrtp.pp.symbol.v | 1,415 | module MODULE1 (
input VAR2 ,
output VAR10 ,
input VAR9,
input VAR3 ,
input VAR5,
input VAR6 ,
input VAR8 ,
input VAR4 ,
input VAR7 ,
input VAR1
);
endmodule | apache-2.0 |
drichmond/riffa | fpga/xilinx/adm7V3/riffa_wrapper_adm7V3.v | 35,526 | module MODULE1
parameter VAR25 = 128,
parameter VAR241 = 256,
parameter VAR324 = 5,
parameter VAR192 = "7V30")
( input VAR43,
input VAR74,
input [VAR25-1:0] VAR98,
input [(VAR25/32)-1:0] VAR274,
input [VAR156-1:0] VAR202,
output VAR321,
input VAR47,
input VAR79,
input [VAR25-1:0] VAR266,
input [(VAR25/32)-1:0] VAR117,
... | bsd-3-clause |
anderson1008/NOCulator | hring/hw/buffered/src/vcr_op_ctrl_mac.v | 28,221 | module MODULE1
(clk, reset, VAR138, VAR57, VAR28, VAR44,
VAR49, VAR141, VAR16, VAR122,
VAR95, VAR13, VAR1, VAR52);
parameter VAR133 = 8;
parameter VAR130 = 4;
parameter VAR134 = 2;
parameter VAR78 = 2;
localparam VAR24 = VAR134 * VAR78;
parameter VAR92 = 1;
localparam VAR73 = VAR24 * VAR92;
localparam VAR140 = VAR91(VA... | mit |
khldragon/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_DDR_8TO1_16CHAN_RX.v | 15,573 | module MODULE1
(
input VAR118,
input VAR72,
input VAR97,
input VAR31,
input [4:0] VAR86,
input [4:0] VAR64,
input VAR122,
input VAR71,
input VAR120,
output [39:0] VAR21,
output [5:0] VAR33,
output [5:0] VAR109,
output [5:0] VAR132,
output [5:0] VAR92,
output [5:0] VAR131,
output [5:0] VAR66,
output VAR62
);
wire [4:0] ... | bsd-2-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/sdffsnq/gf180mcu_fd_sc_mcu9t5v0__sdffsnq_4.functional.v | 1,734 | module MODULE1( VAR21, VAR7, VAR5, VAR22, VAR20, VAR9, VAR10 );
input VAR22, VAR5, VAR21, VAR20, VAR7, VAR10;
output VAR9;
not VAR1( VAR11, VAR20 );
wire VAR2;
not VAR12( VAR2, VAR5 );
wire VAR19;
not VAR3( VAR19, VAR21 );
wire VAR15;
and VAR25( VAR15, VAR2, VAR19 );
wire VAR13;
not VAR18( VAR13, VAR7 );
wire VAR8;
and... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlrbp/sky130_fd_sc_hs__dlrbp.behavioral.v | 2,383 | module MODULE1 (
VAR11,
VAR3 ,
VAR19 ,
VAR22 ,
VAR12 ,
VAR13 ,
VAR15
);
input VAR11;
input VAR3 ;
input VAR19 ;
output VAR22 ;
output VAR12 ;
input VAR13 ;
input VAR15 ;
wire VAR21 ;
reg VAR4 ;
wire VAR17 ;
wire VAR18 ;
wire VAR2 ;
wire VAR5;
wire VAR1 ;
wire VAR16 ;
wire VAR7 ;
wire VAR8 ;
not VAR6 (VAR21 , VAR5 );
VA... | apache-2.0 |
FAST-Switch/fast | lib/hardware/pipeline/UM_OPENFLOW/user_mux.v | 8,613 | module MODULE1(
input clk,
input VAR3,
input VAR45,
input [133:0] VAR32,
input VAR16,
input VAR4,
output VAR5,
input VAR27,
input [133:0] VAR8,
input VAR22,
input VAR13,
output VAR21,
output reg VAR19,
output reg [133:0] VAR30,
output reg VAR44,
output VAR42,
input VAR47
);
reg VAR25;
wire [133:0] VAR31;
wire [7:0] VAR... | apache-2.0 |
csturton/wirepatch | system/hardware/cores/ddr2/ddr2_idelay_ctrl.v | 3,559 | module MODULE1 #
(
parameter VAR9 = "VAR3"
)
(
input VAR5,
input VAR2,
output VAR10
);
VAR4 VAR1
(
.VAR7(VAR10),
.VAR8(VAR5),
.VAR6(VAR2)
);
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/mux4/sky130_fd_sc_hs__mux4_2.v | 2,317 | module MODULE1 (
VAR5 ,
VAR3 ,
VAR4 ,
VAR11 ,
VAR9 ,
VAR2 ,
VAR8 ,
VAR1,
VAR10
);
output VAR5 ;
input VAR3 ;
input VAR4 ;
input VAR11 ;
input VAR9 ;
input VAR2 ;
input VAR8 ;
input VAR1;
input VAR10;
VAR7 VAR6 (
.VAR5(VAR5),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR1(VAR1),
.V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/a21o/sky130_fd_sc_hvl__a21o.functional.v | 1,410 | module MODULE1 (
VAR5 ,
VAR2,
VAR4,
VAR7
);
output VAR5 ;
input VAR2;
input VAR4;
input VAR7;
wire VAR6 ;
wire VAR1;
and VAR3 (VAR6 , VAR2, VAR4 );
or VAR9 (VAR1, VAR6, VAR7 );
buf VAR8 (VAR5 , VAR1 );
endmodule | apache-2.0 |
ruishihan/R7-with-notes | src/rtl/AXI2SREG.v | 5,284 | module MODULE1
(
clk,
rst,
en,
VAR10,
din,
dout,
addr,
VAR22,
VAR23,
async,
VAR14,
VAR31,
VAR27,
VAR19,
VAR26,
VAR28,
VAR18,
VAR17,
VAR3,
VAR16,
VAR8,
VAR20,
VAR11,
VAR13,
VAR2,
VAR4,
VAR12,
VAR29,
VAR9,
VAR30,
VAR7
);
parameter VAR25 = VAR1;
input clk,rst,en,VAR10;
input [31:0]din;
input [17:0]addr;
output reg VAR22,... | apache-2.0 |
AmeerAbdelhadi/2D-Binary-Content-Addressable-Memory-BCAM | bcam_str.v | 14,873 | module MODULE1
localparam VAR21 = VAR3(VAR17); localparam VAR12 = VAR17 / VAR15; localparam VAR37 = VAR3(VAR12); localparam VAR56 = VAR3(VAR15);
wire [VAR37-1:0] VAR49 = VAR1[VAR21-1:VAR56];
wire [VAR56-1:0] VAR33 = VAR1[VAR56-1:0 ];
reg [VAR15-1:0] VAR44;
always @
for (VAR19=0;VAR19<VAR15;VAR19=VAR19+1)
VAR32[VAR51*VA... | bsd-3-clause |
zeruniverse/Single-cycle_CPU | ISE project/ipcore_dir/Data_Mem.v | 5,515 | module MODULE1(
VAR29,
VAR9,
clk,
VAR46,
VAR30);
input [5 : 0] VAR29;
input [31 : 0] VAR9;
input clk;
input VAR46;
output [31 : 0] VAR30;
VAR25 #(
.VAR41(6),
.VAR27("0"),
.VAR52(64),
.VAR51("VAR36"),
.VAR56(1),
.VAR35(1),
.VAR16(0),
.VAR38(0),
.VAR42(0),
.VAR2(0),
.VAR6(0),
.VAR26(0),
.VAR21(0),
.VAR45(0),
.VAR22(0),
.... | gpl-3.0 |
Apo45ty/ArquiCourseCPUVerilog | VerilogSource/ControlUnit+ALU/controlunit2.v | 3,754 | module MODULE1 (output reg VAR5, VAR24, VAR2, VAR22, VAR19, VAR4, VAR14, VAR13,VAR17,VAR10,VAR12,VAR3,VAR16,output reg[4:0] VAR21, output reg[3:0] VAR9, input VAR11, VAR8,VAR20, input [31:0] VAR7,input [3:0] VAR18);
reg [4:0] VAR1, VAR23;
task VAR6;
input [17:0] VAR15;
fork
{VAR9,VAR5, VAR24, VAR2, VAR22,VAR21, VAR19, ... | apache-2.0 |
mistryalok/Zedboard | learning/training/MSD/s07v2/vivado/project_2/project_2.srcs/sources_1/ipshared/Alok/sample_generator_v1_0/085ecca4/hdl/sample_generator_v1_0_M_AXIS.v | 3,056 | module MODULE1 #
(
parameter integer VAR3 = 32,
parameter integer VAR6 = 32
)
(
input wire [7:0] VAR11,
input wire VAR8,
input wire VAR5,
input wire VAR10,
output wire VAR12,
output wire [VAR3-1 : 0] VAR15,
output wire [(VAR3/8)-1 : 0] VAR1,
output wire VAR13,
input wire VAR4
);
reg [VAR3-1 : 0] VAR9;
assign VAR15 = VA... | gpl-3.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/acl_fp_call_sqrtf.v | 1,320 | module MODULE1(VAR1, VAR7, VAR5, VAR3, VAR6);
input VAR1;
input VAR7;
output VAR5;
input [31:0] VAR3;
output [31:0] VAR6;
VAR2( .VAR1(VAR1), .VAR4(VAR3), .VAR6(VAR6));
reg [15:0] delay;
always@(posedge VAR1)
begin
delay[0] <= VAR7;
delay[15:1] <= delay[14:0];
end
assign VAR5 = delay[15];
endmodule | mit |
andrewandrepowell/axiplasma | hdl/projects/Nexys4/bd/mig_wrap/ip/mig_wrap_proc_sys_reset_0_0/mig_wrap_proc_sys_reset_0_0_stub.v | 1,882 | module MODULE1(VAR5, VAR8, VAR1,
VAR4, VAR9, VAR10, VAR3, VAR7,
VAR6, VAR2)
;
input VAR5;
input VAR8;
input VAR1;
input VAR4;
input VAR9;
output VAR10;
output [0:0]VAR3;
output [0:0]VAR7;
output [0:0]VAR6;
output [0:0]VAR2;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlxtn/sky130_fd_sc_hd__dlxtn.pp.symbol.v | 1,341 | module MODULE1 (
input VAR3 ,
output VAR5 ,
input VAR1,
input VAR4 ,
input VAR2 ,
input VAR6 ,
input VAR7
);
endmodule | apache-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/db/ip/video_sys/submodules/altera_reset_synchronizer.v | 3,482 | module MODULE1
parameter VAR6 = 1,
parameter VAR5 = 2
)
(
input VAR1 ,
input clk,
output VAR4
);
reg [VAR5-1:0] VAR3;
reg VAR2;
generate if (VAR6) begin
always @(posedge clk or posedge VAR1) begin
if (VAR1) begin
VAR3 <= {VAR5{1'b1}};
VAR2 <= 1'b1;
end
else begin
VAR3[VAR5-2:0] <= VAR3[VAR5-1:1];
VAR3[VAR5-1] <= 0;
VAR... | gpl-2.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/DE10/hyper_dbuf.v | 12,395 | module MODULE1
(
VAR33,
VAR3,
VAR11,
VAR38) ;
input [7:0] VAR33;
inout [7:0] VAR3;
output [7:0] VAR11;
input [7:0] VAR38;
wire [7:0] VAR20;
wire [7:0] VAR26;
wire [7:0] VAR12;
wire [7:0] VAR24;
wire [7:0] VAR7;
VAR13 VAR16
(
.VAR2(VAR20[0:0]),
.VAR19(VAR26[0:0])
,
.VAR31(1'b0),
.VAR30(1'b0)
);
VAR16.VAR15 = "false",
V... | gpl-3.0 |
hoangt/NOCulator | hring/hw/buffered/src/tc_node_ctrl_mac.v | 12,574 | module MODULE1
(clk, reset, VAR44, VAR27, VAR1, VAR7, VAR59, VAR69,
VAR20, VAR30, VAR73, VAR48, VAR64, VAR15,
VAR26, VAR16, VAR67);
parameter VAR56 = 10;
parameter VAR84 = 6;
localparam VAR53 = VAR56 + VAR84;
parameter VAR13 = 2;
parameter VAR25 = 32;
localparam VAR36 = VAR53;
localparam VAR83 = VAR25;
parameter VAR62 ... | mit |
everskar2013/PentiumX | Hardware/Code/Mem_I_D.v | 4,002 | module MODULE1 (
VAR19,
VAR7,
VAR4,
VAR22,
VAR20,
VAR5,
VAR13,
clk,
VAR11
);
input wire [31: 0] VAR19;
input wire [31: 0] VAR7;
input wire VAR4;
input wire VAR22;
output reg [31: 0] VAR5;
output VAR13;
input clk;
input wire VAR11;
input wire [3: 0] VAR20;
wire [1:0] VAR17;
wire [12:0] VAR9;
wire VAR15;
wire [ 3: 0] VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkbuf/sky130_fd_sc_lp__clkbuf.pp.symbol.v | 1,262 | module MODULE1 (
input VAR2 ,
output VAR4 ,
input VAR3 ,
input VAR5,
input VAR6,
input VAR1
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfrtn/sky130_fd_sc_hdll__sdfrtn.functional.pp.v | 2,372 | module MODULE1 (
VAR3 ,
VAR20 ,
VAR2 ,
VAR6 ,
VAR15 ,
VAR1,
VAR4 ,
VAR12 ,
VAR19 ,
VAR7
);
output VAR3 ;
input VAR20 ;
input VAR2 ;
input VAR6 ;
input VAR15 ;
input VAR1;
input VAR4 ;
input VAR12 ;
input VAR19 ;
input VAR7 ;
wire VAR10 ;
wire VAR21 ;
wire VAR8 ;
wire VAR13;
not VAR22 (VAR21 , VAR1 );
not VAR11 (VAR8 , ... | apache-2.0 |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/bd/system/ip/system_auto_pc_1/axi_infrastructure_v1_1/hdl/verilog/axi_infrastructure_v1_1_vector2axi.v | 11,984 | module MODULE1 #
(
parameter integer VAR57 = 0,
parameter integer VAR59 = 4,
parameter integer VAR127 = 32,
parameter integer VAR112 = 32,
parameter integer VAR16 = 0,
parameter integer VAR104 = 0,
parameter integer VAR7 = 1,
parameter integer VAR88 = 1,
parameter integer VAR117 = 1,
parameter integer VAR43 = 1,
parame... | mit |
FAST-Switch/fast | lib/hardware/pipeline/IPE_IF_OPENFLOW/mac_sgmii/altera_tse_false_path_marker.v | 2,529 | module MODULE1
parameter VAR1 = 1
)
(
input reset,
input clk,
input [VAR1 - 1 : 0] VAR4,
output [VAR1 - 1 : 0] VAR2
);
reg [VAR1 - 1 : 0] VAR3;
assign VAR2 = VAR3;
always @(posedge clk or posedge reset)
begin
if (reset)
begin
VAR3 <= {VAR1{1'b0}};
end
else
begin
VAR3 <= VAR4;
end
end
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig11/mig_7series_v1_1/user_design/rtl/controller/arb_mux.v | 18,282 | module MODULE1 #
(
parameter VAR64 = 100,
parameter VAR27 = "1T",
parameter VAR98 = 11,
parameter VAR86 = 3,
parameter VAR50 = "8",
parameter VAR104 = 4,
parameter VAR1 = 5,
parameter VAR90 = 31,
parameter VAR63 = 8,
parameter VAR36 = "VAR52",
parameter VAR53 = "VAR81",
parameter VAR55 = "VAR81",
parameter VAR46 = 4,
p... | lgpl-3.0 |
camsoupa/cc3000 | cc3000fpga/component/work/cc3000fpga_MSS/MSS_CCC_0/cc3000fpga_MSS_tmp_MSS_CCC_0_MSS_CCC.v | 2,890 | module MODULE1(
VAR61,
VAR44,
VAR64,
VAR28,
VAR26,
VAR7,
VAR23,
VAR54,
VAR63,
VAR48,
VAR49,
VAR62,
VAR38,
VAR13,
VAR2,
VAR11,
VAR67,
VAR3,
VAR16,
VAR52,
VAR29,
VAR12,
VAR15,
VAR60,
VAR10,
VAR39,
VAR40,
VAR24,
VAR14
);
input VAR61;
input VAR44;
input VAR64;
input VAR28;
input VAR26;
input VAR7;
input VAR23;
input VAR54;... | mit |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeZynq/build/AXI4LiteToRFBridgeZCUVerilog.v | 16,837 | module MODULE1 #
(
parameter integer VAR23 = 40,
parameter integer VAR4 = 64
)
(
output wire [VAR23-1 : 0] VAR10,
output wire [VAR23-1 : 0] VAR18,
output wire VAR30,
output wire [VAR4-1 : 0] VAR8,
input wire [VAR4-1 : 0] VAR28,
input wire VAR42,
input wire VAR33,
input wire [VAR23-1 : 0] VAR7,
input wire [2 : 0] VAR19,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlygate4sd3/sky130_fd_sc_hdll__dlygate4sd3.behavioral.v | 1,413 | module MODULE1 (
VAR3,
VAR8
);
output VAR3;
input VAR8;
supply1 VAR4;
supply0 VAR1;
supply1 VAR5 ;
supply0 VAR9 ;
wire VAR6;
buf VAR2 (VAR6, VAR8 );
buf VAR7 (VAR3 , VAR6 );
endmodule | apache-2.0 |
Anirudh94/Connect4-FPGA | Connect4/Gameover.v | 6,224 | module MODULE1 (
address,
VAR38,
VAR8);
input [11:0] address;
input VAR38;
output [2:0] VAR8;
tri1 VAR38;
wire [2:0] VAR24;
wire [2:0] VAR8 = VAR24[2:0];
VAR29 VAR3 (
.VAR49 (address),
.VAR35 (VAR38),
.VAR30 (VAR24),
.VAR17 (1'b0),
.VAR6 (1'b0),
.VAR36 (1'b1),
.VAR27 (1'b0),
.VAR16 (1'b0),
.VAR1 (1'b1),
.VAR21 (1'b1),
... | mit |
scalable-networks/ext | uhd/fpga/usrp1/sdr_lib/hb/mac.v | 1,804 | module MODULE1 (input VAR5, input reset, input enable, input VAR1,
input signed [15:0] VAR9, input signed [15:0] VAR8,
input [7:0] VAR3, output [15:0] VAR7 );
reg signed [30:0] VAR6;
reg signed [39:0] VAR4;
reg signed [15:0] VAR2;
reg VAR10;
always @(posedge VAR5)
VAR10 <= enable;
always @(posedge VAR5)
if(reset | VAR1... | gpl-2.0 |
andrewandrepowell/kernel-on-chip | hdl/projects/Nexys4/bd/ip/bd_proc_sys_reset_0_0/bd_proc_sys_reset_0_0_stub.v | 1,779 | module MODULE1(VAR9, VAR10, VAR1,
VAR5, VAR2, VAR6, VAR7, VAR8,
VAR4, VAR3)
;
input VAR9;
input VAR10;
input VAR1;
input VAR5;
input VAR2;
output VAR6;
output [0:0]VAR7;
output [0:0]VAR8;
output [0:0]VAR4;
output [0:0]VAR3;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkbuf/sky130_fd_sc_ls__clkbuf.behavioral.pp.v | 1,772 | module MODULE1 (
VAR11 ,
VAR3 ,
VAR10,
VAR5,
VAR8 ,
VAR9
);
output VAR11 ;
input VAR3 ;
input VAR10;
input VAR5;
input VAR8 ;
input VAR9 ;
wire VAR12 ;
wire VAR6;
buf VAR7 (VAR12 , VAR3 );
VAR4 VAR1 (VAR6, VAR12, VAR10, VAR5);
buf VAR2 (VAR11 , VAR6 );
endmodule | apache-2.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_gpio_sysfs/zybo_petalinux_1.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr_4.v | 6,817 | module MODULE1(
VAR38,
VAR27,
VAR41,
VAR5,
VAR1,
VAR35,
VAR33,
VAR14,
VAR12,
VAR17,
VAR29,
VAR8,
VAR11,
VAR2,
VAR39,
VAR37,
VAR23,
VAR20,
VAR26,
VAR34,
VAR19,
VAR4,
VAR6,
VAR21,
VAR22,
VAR28,
VAR9,
VAR16,
VAR15,
VAR7,
VAR32,
VAR31
);
input VAR38, VAR27;
input [VAR24-1:0] VAR41,VAR5,VAR1,VAR35;
input [VAR36-1:0] VAR29,V... | gpl-3.0 |
csturton/wirepatch | system/hardware/cores/fabric/ovl_ported/redundant/ovl_change.v | 1,960 | module MODULE1 (VAR15, reset, enable, VAR8, VAR20, VAR25);
parameter VAR17 = VAR14;
parameter VAR21 = 1;
parameter VAR5 = 1;
parameter VAR19 = VAR3;
parameter VAR1 = VAR11;
parameter VAR4 = VAR6;
parameter VAR2 = VAR23;
parameter VAR10 = VAR13;
parameter VAR16 = VAR9;
parameter VAR18 = VAR22;
input VAR15, reset, enable... | mit |
olajep/oh | src/aes/hdl/aes_256.v | 4,474 | module MODULE3 (clk, state, VAR85, out);
input clk;
input [127:0] state;
input [255:0] VAR85;
output [127:0] out;
reg [127:0] VAR60;
reg [255:0] VAR91, VAR7, VAR61;
wire [127:0] VAR46, VAR62, VAR4, VAR26, VAR49, VAR32, VAR11, VAR84,
VAR75, VAR37, VAR25, VAR72, VAR93;
wire [255:0] VAR20, VAR33, VAR9, VAR35, VAR38, VAR43... | mit |
balanx/laotzu | RTL/asyn_fifo_write.v | 4,117 | module MODULE1 #(
parameter VAR13 = 6,
parameter [VAR13:0] VAR8 = 44,
parameter [VAR13:0] VAR2 = 0,
parameter [VAR13:0] VAR1 = 7
) (
input wire VAR14 ,
input wire VAR18 ,
input wire VAR10 ,
input wire [VAR13:0] VAR6 ,
output reg [VAR13-1:0] VAR17 ,
output reg [VAR13:0] VAR15 ,
output VAR11 ,
output reg VAR5 ,
output re... | apache-2.0 |
lbl-cal/StanfordNoC | router/verif/router/packet_source.v | 28,167 | module MODULE1
(clk, reset, VAR23, VAR106, VAR115, VAR75, VAR56, VAR77);
parameter VAR59 = 0;
parameter VAR93 = 1000;
parameter VAR78 = 25;
parameter VAR127 = 32;
parameter VAR183 = 0;
parameter VAR81 = VAR73;
parameter VAR7 = 32;
parameter VAR171 = 2;
parameter VAR139 = 2;
localparam VAR107 = VAR114(VAR139);
localpara... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdlclkp/sky130_fd_sc_ls__sdlclkp.blackbox.v | 1,297 | module MODULE1 (
VAR4,
VAR1 ,
VAR5,
VAR3
);
output VAR4;
input VAR1 ;
input VAR5;
input VAR3 ;
supply1 VAR8;
supply0 VAR7;
supply1 VAR6 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/dram/rtl/dram_dctl.v | 16,087 | module MODULE1 (
VAR34, VAR92, VAR14, VAR100,
VAR63, VAR72, VAR19, VAR138,
VAR67, VAR78, VAR94, VAR55,
VAR98, VAR101, VAR60, VAR13,
VAR26, VAR56, VAR69, VAR33, VAR66,
VAR109, VAR129, VAR79,
VAR97, VAR75, VAR25,
VAR20, VAR30, VAR50, VAR90,
VAR11, VAR105, VAR62, VAR137,
VAR130, VAR82, VAR32,
VAR54, VAR58, VAR65,
VAR36, V... | gpl-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/controllerHdl_MATLAB_Function_block1.v | 1,091 | module MODULE1
(
VAR1,
VAR2
);
input [17:0] VAR1; output [8:0] VAR2;
assign VAR2 = VAR1[8:0];
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/fa/sky130_fd_sc_hd__fa.pp.symbol.v | 1,286 | module MODULE1 (
input VAR7 ,
input VAR4 ,
input VAR9 ,
output VAR2,
output VAR3 ,
input VAR1 ,
input VAR8,
input VAR5,
input VAR6
);
endmodule | apache-2.0 |
EmbeddedANT/XILINX_Spartan3AN-StarterKit | Spartan3AN_PicoBlaze_LCD/PicoBlaze_OutReg.v | 2,063 | module MODULE1
(
clk,
reset,
VAR5,
VAR6,
VAR1,
VAR4);
input wire clk;
input wire reset;
input wire [7:0] VAR5;
input wire VAR6;
input wire [7:0] VAR1;
output reg [7:0] VAR4;
reg VAR3=1;
always @ (*)
begin
if (VAR6 == 1)
begin
case (VAR5)
VAR2: VAR3 = 1;
default: VAR3 = 0;
endcase
end
else
VAR3=0;
end
always @ (posedge ... | gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/FPU_Interface/fpaddsub_arch2/exp_operation.v | 2,069 | module MODULE1
input wire clk, input wire rst, input wire VAR22,
input wire VAR7,
input wire [VAR31-1:0] VAR20,
input wire [VAR31-1:0] VAR24,
input wire VAR6,
output wire [VAR31-1:0] VAR19,
output wire VAR21,
output wire VAR2
);
wire VAR4;
wire VAR26;
wire [VAR31:0] VAR16;
VAR5 #(.VAR14(VAR31)) VAR30(
.VAR25 (VAR6),
.V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/buf/sky130_fd_sc_ms__buf.pp.blackbox.v | 1,223 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR3,
VAR4,
VAR5 ,
VAR6
);
output VAR2 ;
input VAR1 ;
input VAR3;
input VAR4;
input VAR5 ;
input VAR6 ;
endmodule | apache-2.0 |
olofk/oh | elink/hdl/erx_timer.v | 1,647 | module MODULE1 (
timeout,
clk, reset, VAR11, VAR7, VAR6
);
parameter VAR5 = 32;
parameter VAR8 = 32;
input clk;
input reset;
input [1:0] VAR11; input VAR7;
input VAR6;
output timeout;
reg [31:0] VAR10;
reg VAR1;
wire VAR2;
wire VAR9;
VAR3 #(.VAR5(1)) sync(
.out (VAR9),
.in (VAR6),
.clk (clk),
.reset (reset)
);
assign V... | gpl-3.0 |
glennchid/font5-firmware | src/verilog/synthesis/ADC_block.v | 7,095 | module MODULE1(
input VAR23,
input VAR16,
input rst,
input VAR29,
input [1:0] VAR35,
input [6:0] VAR42,
input [5:0] VAR6,
input VAR3,
input VAR26,
input VAR10,
output VAR33,
output [5:0] VAR2, output [5:0] VAR34, output [6:0] VAR39, output reg VAR38, output [6:0] VAR36, output [6:0] VAR40, output [6:0] VAR19, output [5... | gpl-3.0 |
golfit/QcmCapBoardMain | CapBoardDecoderMain.v | 5,677 | module MODULE1(clk,VAR4,VAR8,VAR7,VAR2,VAR6,VAR1,VAR5,VAR3,VAR9);
input clk; reg [2:0] VAR10; input [5:0] VAR4;
input VAR8,VAR7;
input [6:0] VAR2,VAR6;
output [7:0] VAR1, VAR5;
output [3:0] VAR3, VAR9; | mit |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/hostController/speedCtrlMux.v | 3,631 | module MODULE1 (VAR7, VAR6, VAR4, VAR1, VAR3, VAR2, VAR5);
input VAR7;
input VAR6;
input VAR4;
input VAR1;
input VAR3;
output VAR2;
output VAR5;
wire VAR7;
wire VAR6;
wire VAR4;
wire VAR1;
wire VAR3;
reg VAR2;
reg VAR5;
always @(VAR7 or VAR6 or VAR4 or VAR1 or VAR3)
begin
if (VAR3 == 1'b1)
begin
VAR2 <= VAR4;
VAR5 <= V... | gpl-3.0 |
nyaxt/dmix | dmix_t.v | 4,373 | module MODULE1;
reg rst;
reg VAR6;
parameter VAR4 = 40; VAR9 VAR15(.rst(rst), .VAR10(VAR6));
task VAR12;
input wire VAR11;
begin
VAR6 = VAR11;
endtask
task VAR3;
begin
if(VAR6) begin
VAR12(0);
VAR12(0);
VAR12(0);
VAR12(1);
VAR12(0);
VAR12(1);
VAR12(1);
VAR12(1);
end else begin
VAR12(1);
VAR12(1);
VAR12(1);
VAR12(0);
VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor2/sky130_fd_sc_hs__nor2_1.v | 1,959 | module MODULE1 (
VAR1 ,
VAR6 ,
VAR4 ,
VAR3,
VAR7
);
output VAR1 ;
input VAR6 ;
input VAR4 ;
input VAR3;
input VAR7;
VAR2 VAR5 (
.VAR1(VAR1),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR1,
VAR6,
VAR4
);
output VAR1;
input VAR6;
input VAR4;
supply1 VAR3;
supply0 VAR7;
VAR2 VAR5 (
.... | apache-2.0 |
briburrell/amica | device/scrypt_bitstream/bk.03.02.14/salsaengine.v | 20,388 | module MODULE1 (VAR43, reset, din, dout, VAR73, VAR57, VAR67, VAR23 );
input VAR43;
input reset; input VAR73;
input VAR57; output VAR67;
output reg VAR23 = 1'b0;
parameter VAR2 = 8; input [VAR2-1:0] din;
output [VAR2-1:0] dout;
parameter VAR60 = 12;
parameter VAR18 = 16;
function integer VAR24; input integer VAR64;
beg... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlxbn/sky130_fd_sc_hs__dlxbn.behavioral.pp.v | 2,032 | module MODULE1 (
VAR6 ,
VAR4 ,
VAR1 ,
VAR10 ,
VAR3 ,
VAR2
);
input VAR6 ;
input VAR4 ;
output VAR1 ;
output VAR10 ;
input VAR3 ;
input VAR2;
wire VAR12 ;
wire VAR9 ;
wire VAR14;
wire VAR13 ;
reg VAR11 ;
wire VAR8 ;
wire 1 ;
not VAR5 (VAR12 , VAR14 );
VAR17 VAR15 (VAR9 , VAR13, VAR12, VAR11, VAR6, VAR4);
assign VAR8 = (... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or2b/sky130_fd_sc_ls__or2b_1.v | 2,127 | module MODULE2 (
VAR6 ,
VAR2 ,
VAR8 ,
VAR9,
VAR5,
VAR1 ,
VAR4
);
output VAR6 ;
input VAR2 ;
input VAR8 ;
input VAR9;
input VAR5;
input VAR1 ;
input VAR4 ;
VAR7 VAR3 (
.VAR6(VAR6),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR6 ,
VAR2 ,
VAR8
);
output VAR6... | apache-2.0 |
vvk/sysrek | skin_color_segm/opening3x3.v | 1,594 | module MODULE1#(
parameter [9:0] VAR13 = 83 )(
input clk,
input VAR8,
input rst,
input VAR19,
input VAR23,
input VAR1,
input VAR18,
output VAR9,
output VAR14,
output VAR7,
output VAR4
);
wire VAR22;
wire VAR24;
wire VAR12;
wire VAR3;
VAR21 #
(
.VAR13(VAR13)
)
VAR17
(
.clk(clk),
.VAR8(1'b1),
.rst(1'b0),
.VAR19(VAR19),
.... | gpl-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/system/synthesis/submodules/system_mm_interconnect_1.v | 16,432 | module MODULE1 (
input wire VAR40, input wire VAR51, input wire [29:0] VAR49, output wire VAR1, input wire [0:0] VAR91, input wire [7:0] VAR36, input wire VAR25, output wire [63:0] VAR70, output wire VAR14, input wire VAR24, input wire [63:0] VAR92, input wire VAR81, output wire [3:0] VAR29, output wire VAR71, output w... | mit |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/mig_v3_4/user_design/rtl/ui/ui_top.v | 13,216 | module MODULE1 #
(
parameter VAR68 = 100,
parameter VAR14 = 256,
parameter VAR52 = 32,
parameter VAR28 = 3,
parameter VAR20 = 12,
parameter VAR43 = 5,
parameter VAR33 = "VAR16",
parameter VAR37 = "VAR16",
parameter VAR21 = "VAR7",
parameter VAR3 = 4,
parameter VAR69 = 2,
parameter VAR19 = 16
)
(
VAR8, VAR13, VAR70, VAR... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21bo/sky130_fd_sc_lp__a21bo_lp.v | 2,326 | module MODULE1 (
VAR4 ,
VAR6 ,
VAR3 ,
VAR2,
VAR9,
VAR10,
VAR5 ,
VAR1
);
output VAR4 ;
input VAR6 ;
input VAR3 ;
input VAR2;
input VAR9;
input VAR10;
input VAR5 ;
input VAR1 ;
VAR8 VAR7 (
.VAR4(VAR4),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR1(VAR1)
);
endmodule
module MODULE1 ... | apache-2.0 |
yipenghuang0302/csee4840_14 | software/peripheral/db/ip/ik_swift/submodules/ik_swift_hps_0.v | 28,530 | module MODULE1 #(
parameter VAR48 = 2,
parameter VAR57 = 2
) (
output wire VAR87, input wire VAR4, input wire [7:0] VAR11, input wire [31:0] VAR74, input wire [3:0] VAR63, input wire [2:0] VAR174, input wire [1:0] VAR69, input wire [1:0] VAR127, input wire [3:0] VAR31, input wire [2:0] VAR88, input wire VAR6, output wi... | mit |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/ip/hdl/verilog/FIFO_image_filter_src1_cols_V.v | 2,983 | module MODULE1 (
clk,
VAR19,
VAR21,
VAR24,
VAR8);
parameter VAR16 = 32'd12;
parameter VAR18 = 32'd2;
parameter VAR22 = 32'd3;
input clk;
input [VAR16-1:0] VAR19;
input VAR21;
input [VAR18-1:0] VAR24;
output [VAR16-1:0] VAR8;
reg[VAR16-1:0] VAR20 [0:VAR22-1];
integer VAR23;
always @ (posedge clk)
begin
if (VAR21)
begin
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/diode/sky130_fd_sc_ms__diode.pp.blackbox.v | 1,226 | module MODULE1 (
VAR4,
VAR3 ,
VAR1 ,
VAR5 ,
VAR2
);
input VAR4;
input VAR3 ;
input VAR1 ;
input VAR5 ;
input VAR2 ;
endmodule | apache-2.0 |
ccckmit/wd | db/joc/verilog/Not.v | 3,360 | module MODULE1(input in, output out);
nand VAR49(out, in, in);
}
VAR18 VAR46 {
VAR31 VAR59, VAR27;
VAR44 out;
VAR51:
MODULE1(in=VAR59, out=VAR22);
MODULE1(in=VAR27, out=VAR35);
VAR16(VAR59=VAR22, VAR27=VAR35, out=out);
}
VAR18 VAR30 {
VAR31 VAR59, VAR27;
VAR44 out;
VAR51:
VAR16 (VAR59=VAR59, VAR27=VAR27, out= VAR62);
V... | mpl-2.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/IPRepo-1.0.0/NVMeHostController4L/src/pcie_fc_cntl.v | 13,544 | module MODULE1
(
input VAR7,
input VAR47,
input [11:0] VAR15,
input [7:0] VAR4,
input [11:0] VAR19,
input [7:0] VAR38,
input [11:0] VAR49,
input [7:0] VAR41,
output [2:0] VAR51,
input VAR30,
output VAR16,
input [5:0] VAR53,
output VAR48,
output VAR33,
output VAR35
);
parameter VAR32 = 32;
parameter VAR24 = 8;
parameter... | gpl-3.0 |
monotone-RK/FACE | MCSoC-15/8-way/ise/ipcore_dir/dram/example_design/rtl/traffic_gen/mig_7series_v1_9_tg_status.v | 4,748 | module MODULE1 #(
parameter VAR17 = 100,
parameter VAR1 = 32
)
(
input VAR10 ,
input VAR14 ,
input VAR11,
input VAR5 ,
input [VAR1-1:0] VAR16,
input [VAR1-1:0] VAR7 ,
input [31:0] VAR8 ,
input [5:0] VAR15 ,
input VAR6 ,
input VAR9,
input VAR4,
output reg [64 + (2*VAR1 - 1):0] VAR13,
output VAR3
);
reg VAR2;
reg VAR12;
... | mit |
aquaxis/synverll | lib/axi_master_single/aq_axi_master32_single.v | 10,658 | module MODULE1(
input VAR59,
input VAR18,
output [0:0] VAR34,
output [31:0] VAR6,
output [7:0] VAR38,
output [2:0] VAR15,
output [1:0] VAR9,
output VAR76,
output [3:0] VAR44,
output [2:0] VAR68,
output [3:0] VAR10,
output [0:0] VAR29,
output VAR82,
input VAR84,
output [31:0] VAR27,
output [3:0] VAR63,
output VAR51,
out... | mit |
qmn/riscv-invicta | hardware/src/arbiter.v | 4,537 | module MODULE1 (
input clk,
input reset,
output [31:0] VAR18,
output VAR11,
input [31:0] VAR2,
input VAR9,
output VAR1,
input [31:0] VAR14,
input [31:0] VAR24,
input [3:0] VAR20,
input VAR19,
input VAR6,
output VAR13,
output reg [31:0] VAR10,
output [3:0] VAR15,
output VAR12,
output reg VAR4,
input [31:0] VAR16,
output... | bsd-2-clause |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/system/synthesis/submodules/system_acl_iface_acl_kernel_interface.v | 60,109 | module MODULE1 (
input wire VAR312, input wire VAR291, output wire VAR238, output wire [31:0] VAR362, output wire VAR239, input wire [0:0] VAR306, input wire [31:0] VAR29, input wire [13:0] VAR284, input wire VAR117, input wire VAR278, input wire [3:0] VAR67, input wire VAR359, input wire VAR202, input wire [63:0] VAR3... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfrtn/sky130_fd_sc_hs__dfrtn.pp.blackbox.v | 1,336 | module MODULE1 (
VAR3,
VAR2 ,
VAR4 ,
VAR5 ,
VAR6 ,
VAR1
);
input VAR3;
input VAR2 ;
input VAR4 ;
output VAR5 ;
input VAR6 ;
input VAR1 ;
endmodule | apache-2.0 |
CospanDesign/nysa-tx1-pcie-platform | tx1_pcie/host_interface/ppfifo_pcie_host_interface.v | 16,657 | module MODULE1(
input rst,
input clk,
input VAR28,
input VAR27,
output VAR46,
output reg VAR29,
output reg [31:0] VAR58,
output reg [31:0] VAR57,
output reg [31:0] VAR22,
output reg [27:0] VAR38,
output reg VAR10,
input VAR35,
input [31:0] VAR48,
input [31:0] VAR25,
input [31:0] VAR55,
input [27:0] VAR39,
input VAR47,
... | mit |
cornell-zhang/datuner | designs/quartus/processor/lab5iram1B.v | 2,337 | module MODULE1(VAR3, VAR6, VAR5, VAR1);
input VAR3;
input VAR6;
input [7:0] VAR5;
output [15:0] VAR1;
reg [15:0] VAR2[0:127];
wire [6:0] VAR4;
integer VAR7;
assign VAR4 = VAR5[7:1];
assign VAR1 = VAR2[VAR4];
always @(posedge VAR3) begin
if(VAR6) begin
VAR2[0] <= 16'b1111000000000001; VAR2[1] <= 16'b0101000101111111; VA... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlrtp/sky130_fd_sc_hs__dlrtp.pp.symbol.v | 1,395 | module MODULE1 (
input VAR6 ,
output VAR5 ,
input VAR4,
input VAR3 ,
input VAR2 ,
input VAR1
);
endmodule | apache-2.0 |
fpgasystems/caribou | hw/src/regex/rem_rangematch.v | 2,116 | module MODULE1
(
clk,
rst,
VAR8,
VAR6,
VAR9,
VAR7,
VAR5,
VAR2,
VAR3,
VAR4
);
input clk;
input rst;
input VAR8;
input [7:0] VAR6;
input [7:0] VAR9;
input [1:0] VAR7;
input VAR5;
input [7:0] VAR2;
input VAR3;
output VAR4;
reg VAR12;
reg [7:0] VAR11;
reg [7:0] VAR10;
reg VAR1;
assign VAR4 = VAR12;
always @(posedge clk)
be... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor4bb/sky130_fd_sc_ls__nor4bb.symbol.v | 1,333 | module MODULE1 (
input VAR1 ,
input VAR2 ,
input VAR9,
input VAR5,
output VAR6
);
supply1 VAR8;
supply0 VAR7;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkbuf/sky130_fd_sc_hs__clkbuf.behavioral.v | 1,664 | module MODULE1 (
VAR8 ,
VAR5 ,
VAR10,
VAR1
);
output VAR8 ;
input VAR5 ;
input VAR10;
input VAR1;
wire VAR2 ;
wire VAR6;
buf VAR7 (VAR2 , VAR5 );
VAR9 VAR4 (VAR6, VAR2, VAR10, VAR1);
buf VAR3 (VAR8 , VAR6 );
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/fft_v5_4k_strm_nat/xfft_v7_1_bb.v | 2,019 | module MODULE1 (
VAR1, VAR11, VAR4, VAR14, VAR3, clk, VAR12, VAR6, VAR7, VAR10, VAR8, VAR13, VAR5, VAR9, VAR2, VAR15, VAR16
);
output VAR1;
input VAR11;
input VAR4;
output VAR14;
output VAR3;
input clk;
output VAR12;
input VAR6;
input VAR7;
output VAR10;
input [15 : 0] VAR8;
output [15 : 0] VAR13;
output [11 : 0] VAR5;... | lgpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature_KOA/ecp/ks29.v | 3,218 | module MODULE1(VAR8, VAR9, VAR6);
input wire [28:0] VAR8;
input wire [28:0] VAR9;
output wire [56:0] VAR6;
wire [26:0] VAR1;
wire [28:0] VAR5;
wire [28:0] VAR2;
wire [14:0] VAR4;
wire [14:0] VAR13;
VAR7 VAR12(VAR8[14:0], VAR9[14:0], VAR5);
VAR10 VAR3(VAR8[28:15], VAR9[28:15], VAR1);
assign VAR4[13:0] = VAR8[28:15] ^ VA... | gpl-3.0 |
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