repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/controller/mig_7series_v2_0_arb_mux.v | 19,765 | module MODULE1 #
(
parameter VAR52 = 100,
parameter VAR46 = "VAR20",
parameter VAR30 = "1T",
parameter VAR12 = 11,
parameter VAR82 = 3,
parameter VAR69 = "8",
parameter VAR99 = 4,
parameter VAR120 = 5,
parameter VAR41 = 5,
parameter VAR17 = 31,
parameter VAR62 = 8,
parameter VAR32 = "VAR13",
parameter VAR97 = "VAR95", ... | bsd-2-clause |
cafe-alpha/wascafe | v12/fpga_firmware/wasca/synthesis/submodules/wasca_nios2_gen2_0.v | 5,661 | module MODULE1 (
input wire clk, input wire VAR14, output wire [26:0] VAR19, output wire [3:0] VAR15, output wire VAR8, input wire [31:0] VAR16, input wire VAR9, output wire VAR13, output wire [31:0] VAR10, output wire VAR4, output wire [26:0] VAR26, output wire VAR12, input wire [31:0] VAR11, input wire VAR7, input wi... | gpl-2.0 |
borti4938/n64rgb | advancedRGBmod/firmware/rtl/ppu/n64_vinfo_ext.v | 3,215 | module MODULE1(
VAR5,
VAR13,
VAR8,
VAR4,
VAR11,
VAR6
);
input VAR5;
input VAR13;
input VAR8;
input [3:0] VAR4;
input [3:0] VAR11;
output [1:0] VAR6;
wire VAR14 = !VAR4[3] & VAR11[3];
wire VAR12 = VAR4[3] & !VAR11[3];
wire VAR2 = !VAR4[1] & VAR11[1];
wire VAR7 = VAR4[1] & !VAR11[1];
reg VAR9 = 1'b0; reg VAR3 = 1'b1;
alw... | gpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_dmac_v1_00_a/hdl/verilog/request_generator.v | 3,791 | module MODULE1 (
input VAR4,
input VAR1,
output [VAR2-1:0] VAR7,
input [VAR2-1:0] VAR3,
input VAR9,
output reg VAR18,
input [VAR11:0] VAR6,
input enable,
input VAR8,
output VAR15
);
parameter VAR2 = 3;
parameter VAR12 = 3;
parameter VAR5 = 7;
parameter VAR16 = 24;
localparam VAR11 = VAR16 - VAR5;
reg [VAR11-1:0] VAR13 ... | mit |
peteg944/music-fpga | Experimental/RainbowMatrix and Partial Spectrum/ADAU1761Top.v | 3,957 | module MODULE1(
input clk,
input VAR2,
input VAR17,
input VAR1,
input VAR20,
output VAR19,
output VAR15,
output VAR6,
output VAR16,
output VAR26,
inout VAR9,
input [3:0] VAR31,
output [2:0] VAR12,
output [2:0] VAR30,
output [3:0] VAR29,
output VAR27,
output VAR10,
output VAR7,
output VAR21,
output VAR22,
output VAR4,
i... | mit |
TierraDelFuego/Open-Source-FPGA-Bitcoin-Miner | projects/LX150_comm_tweaks/hdl/fpgaminer_top.v | 5,072 | module MODULE1 (
input VAR39
);
localparam VAR18 = 100;
localparam VAR37 = 200;
localparam VAR2 = 50;
localparam VAR8 = 200;
wire VAR50;
VAR5 VAR58 ( .VAR59 (VAR39), .VAR21 (VAR50));
reg [255:0] VAR19 = 0;
reg [95:0] VAR54 = 0;
reg [31:0] VAR31 = 32'd253, VAR56 = 32'd0;
wire VAR17;
wire VAR43, VAR25, VAR30;
VAR57 # (
.... | gpl-3.0 |
theapi/de0-nano | uart_buffered/async.v | 7,540 | module MODULE2(
input clk,
input VAR46,
input [7:0] VAR26,
output VAR33,
output VAR23
);
parameter VAR44 = 50000000; parameter VAR18 = 115200;
generate
if(VAR44<VAR18*8 && (VAR44 % VAR18!=0)) MODULE4 VAR12("VAR11 VAR35 with VAR42 VAR18 VAR28");
endgenerate
wire VAR13 = 1'b1; else
wire VAR13;
MODULE3 #(VAR44, VAR18) VAR... | mit |
Siliciumer/DOS-Mario-FPGA | sources/player.v | 3,414 | module MODULE1
VAR14 = 40,
VAR26 = 80
)
(
input wire [9:0] VAR9,
input wire [8:0] VAR24,
input wire VAR10,
input wire VAR18,
input wire VAR5,
input wire [9:0] VAR4,
input wire VAR8,
input wire [9:0] VAR2,
input wire VAR12,
input wire VAR7,
input wire rst,
input wire clk,
input wire [23:0] VAR20,
input wire [23:0] VAR13... | mit |
ptracton/vscale_soc | rtl/uart16550-1.5.4/rtl/verilog/uart_wb.v | 9,369 | module MODULE1 (clk, VAR5,
VAR7, VAR9, VAR1, VAR22, VAR8,
VAR21, VAR15, VAR20, VAR2, VAR11, VAR6, VAR3,
VAR17, VAR18 );
input clk;
input VAR5;
input VAR7;
input VAR9;
input VAR1;
input [3:0] VAR3;
input [2:0] VAR8;
input [7:0] VAR15; output [7:0] VAR20;
reg [7:0] VAR20;
wire [7:0] VAR15;
reg [7:0] VAR14;
output [2:0] V... | mit |
marqs85/ossc | rtl/lpm_mult_4_sl.v | 4,662 | module MODULE1 (
VAR10,
VAR5,
VAR2,
VAR6);
input VAR10;
input [7:0] VAR5;
input [7:0] VAR2;
output [7:0] VAR6;
wire [7:0] VAR1;
wire [7:0] VAR6 = VAR1[7:0];
VAR4 VAR3 (
.VAR10 (VAR10),
.VAR5 (VAR5),
.VAR2 (VAR2),
.VAR6 (VAR1),
.VAR18 (1'b0),
.VAR7 (1'b1),
.VAR13 (1'b0),
.sum (1'b0));
VAR3.VAR20 = "VAR14=9",
VAR3.VAR15... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21oi/sky130_fd_sc_hdll__a21oi_4.v | 2,277 | module MODULE1 (
VAR8 ,
VAR9 ,
VAR7 ,
VAR2 ,
VAR3,
VAR4,
VAR10 ,
VAR1
);
output VAR8 ;
input VAR9 ;
input VAR7 ;
input VAR2 ;
input VAR3;
input VAR4;
input VAR10 ;
input VAR1 ;
VAR5 VAR6 (
.VAR8(VAR8),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR1(VAR1)
);
endmodule
module MODULE... | apache-2.0 |
alexforencich/xfcp | lib/eth/example/ExaNIC_X25/fpga_10g/rtl/fpga.v | 11,697 | module MODULE1 (
output wire [1:0] VAR35,
output wire [1:0] VAR83,
output wire [1:0] VAR218,
input wire VAR176,
input wire VAR183,
output wire VAR203,
output wire VAR24,
input wire VAR205,
input wire VAR16,
output wire VAR70,
output wire VAR226,
input wire VAR51,
input wire VAR148,
output wire VAR61,
output wire VAR130... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/diode/sky130_fd_sc_hdll__diode.functional.v | 1,089 | module MODULE1 (
VAR1
);
input VAR1;
endmodule | apache-2.0 |
jotego/jt51 | syn/xilinx/ym09/hdl/pll.v | 2,730 | module MODULE1(VAR51,
VAR6,
VAR31,
VAR29,
VAR13);
input VAR51;
output VAR6;
output VAR31;
output VAR29;
output VAR13;
wire VAR32;
wire VAR4;
wire VAR9;
wire VAR48;
wire VAR52;
assign VAR52 = 0;
assign VAR31 = VAR9;
assign VAR29 = VAR32;
VAR39 VAR17 (.VAR47(VAR4),
.VAR3(VAR6));
VAR34 VAR57 (.VAR47(VAR51),
.VAR3(VAR9));
... | gpl-3.0 |
jakubfi/mera400f | src/rzrp.v | 1,057 | module MODULE1(
input VAR10,
input VAR4, input irq, input VAR11, input VAR1, input VAR3, input VAR5, input VAR2, output VAR8, output VAR6, output VAR9, output VAR7 );
assign VAR6 = VAR8 & VAR4;
always @ (posedge VAR10, posedge irq) begin
if (irq) VAR8 <= 1'b1;
end
else if (VAR3) VAR8 <= 1'b0;
else if (VAR1) case ({VAR1... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkbuf/sky130_fd_sc_lp__clkbuf_16.v | 2,040 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR4,
VAR8,
VAR7 ,
VAR5
);
output VAR1 ;
input VAR2 ;
input VAR4;
input VAR8;
input VAR7 ;
input VAR5 ;
VAR6 VAR3 (
.VAR1(VAR1),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR1,
VAR2
);
output VAR1;
input VAR2;
supply1 VAR4;
supply0 VAR8;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a211oi/sky130_fd_sc_hs__a211oi_4.v | 2,234 | module MODULE2 (
VAR8 ,
VAR4 ,
VAR1 ,
VAR3 ,
VAR9 ,
VAR2,
VAR7
);
output VAR8 ;
input VAR4 ;
input VAR1 ;
input VAR3 ;
input VAR9 ;
input VAR2;
input VAR7;
VAR6 VAR5 (
.VAR8(VAR8),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR8 ,
VAR4,
VAR1,
VAR3,
VAR9
);... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv.functional.v | 1,274 | module MODULE1 (
VAR3,
VAR2
);
output VAR3;
input VAR2;
buf VAR1 (VAR3 , VAR2 );
endmodule | apache-2.0 |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_uart/niosii/synthesis/submodules/niosii_nios2_gen2_0.v | 5,770 | module MODULE1 (
input wire clk, input wire VAR21, input wire VAR3, output wire [17:0] VAR9, output wire [3:0] VAR14, output wire VAR4, input wire [31:0] VAR13, input wire VAR12, output wire VAR6, output wire [31:0] VAR10, output wire VAR8, output wire [17:0] VAR22, output wire VAR20, input wire [31:0] VAR25, input wir... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and4/sky130_fd_sc_ls__and4.functional.pp.v | 1,837 | module MODULE1 (
VAR14 ,
VAR4 ,
VAR2 ,
VAR15 ,
VAR7 ,
VAR8,
VAR11,
VAR3 ,
VAR9
);
output VAR14 ;
input VAR4 ;
input VAR2 ;
input VAR15 ;
input VAR7 ;
input VAR8;
input VAR11;
input VAR3 ;
input VAR9 ;
wire VAR1 ;
wire VAR13;
and VAR10 (VAR1 , VAR4, VAR2, VAR15, VAR7 );
VAR5 VAR12 (VAR13, VAR1, VAR8, VAR11);
buf VAR6 (V... | apache-2.0 |
borti4938/sd2snes | verilog/sd2snes_sdd1/dac.v | 7,269 | module MODULE1(
input VAR2,
input VAR1,
input VAR25,
input[10:0] VAR11,
input[7:0] VAR47,
input[7:0] VAR39,
input VAR15,
input [2:0] VAR38,
input [8:0] VAR54,
input VAR46,
input reset,
input VAR36,
output VAR18,
output VAR45,
output VAR58,
output VAR33,
output VAR28
);
reg[8:0] VAR31;
reg[8:0] VAR52;
wire[8:0] VAR57 = ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkmux2/sky130_fd_sc_hdll__clkmux2_2.v | 2,223 | module MODULE1 (
VAR8 ,
VAR5 ,
VAR3 ,
VAR4 ,
VAR9,
VAR1,
VAR6 ,
VAR2
);
output VAR8 ;
input VAR5 ;
input VAR3 ;
input VAR4 ;
input VAR9;
input VAR1;
input VAR6 ;
input VAR2 ;
VAR7 VAR10 (
.VAR8(VAR8),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR2(VAR2)
);
endmodule
module MODULE1 (... | apache-2.0 |
cpulabs/mist1032sa | src/lib/mist1032sa_arbiter_matching_queue.v | 2,000 | module MODULE1 #(
parameter VAR7 = 8,
parameter VAR5 = 3,
parameter VAR13 = 1
)(
input wire VAR11,
input wire VAR3,
input wire VAR16,
input wire VAR2,
input wire [VAR13-1:0] VAR17,
output wire VAR20,
input wire VAR19,
output wire VAR15,
output wire [VAR13-1:0] VAR14,
output wire VAR8
);
wire VAR18;
wire VAR4;
wire [VAR... | bsd-2-clause |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/acl_fp_custom_mul_hc_core.v | 24,602 | module MODULE1 #(
parameter integer VAR116 = 1 )
(
input logic VAR110,
input logic VAR125,
input logic VAR2,
input logic VAR1,
output logic VAR3,
output logic VAR15,
input logic enable,
input logic [31:0] VAR40,
input logic [31:0] VAR91,
output logic [31:0] VAR24
);
struct packed
{
logic VAR16, VAR94;
logic [7:0] VAR58... | mit |
masc-ucsc/cmpe220fall16 | rtl/l2cache_pipe.v | 89,016 | module MODULE1(
input clk
,input reset
,input VAR297
,output VAR169
,input VAR228 VAR326
,output VAR250
,input VAR162
,output VAR29 VAR130
,input VAR372
,output VAR336
,input VAR65 VAR332
,input VAR156
,output VAR154
,input VAR263 VAR257
,output VAR107
,input VAR145
,output VAR83 VAR16
,input VAR28
,output VAR255
,inpu... | apache-2.0 |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/bd/system/ip/system_xbar_1/synth/system_xbar_1.v | 20,018 | module MODULE1 (
VAR61,
VAR83,
VAR80,
VAR41,
VAR100,
VAR102,
VAR55,
VAR92,
VAR38,
VAR34,
VAR40,
VAR98,
VAR131,
VAR29,
VAR30,
VAR88,
VAR31,
VAR6,
VAR65,
VAR15,
VAR8,
VAR108,
VAR39,
VAR10,
VAR9,
VAR53,
VAR3,
VAR43,
VAR101,
VAR126,
VAR35,
VAR107,
VAR36,
VAR73,
VAR14,
VAR32,
VAR99,
VAR16,
VAR45,
VAR17,
VAR111,
VAR11,
VAR89... | mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/vfabric_fdiv.v | 2,793 | module MODULE1(VAR7, VAR28,
VAR6, VAR15, VAR23,
VAR22, VAR14, VAR26,
VAR8, VAR30, VAR12);
parameter VAR34 = 32;
parameter VAR21 = 14;
parameter VAR20 = 64;
input VAR7, VAR28;
input [VAR34-1:0] VAR6;
input [VAR34-1:0] VAR22;
input VAR15, VAR14;
output VAR23, VAR26;
output [VAR34-1:0] VAR8;
output VAR30;
input VAR12;
reg... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a22o/sky130_fd_sc_ls__a22o.blackbox.v | 1,356 | module MODULE1 (
VAR8 ,
VAR9,
VAR1,
VAR6,
VAR4
);
output VAR8 ;
input VAR9;
input VAR1;
input VAR6;
input VAR4;
supply1 VAR3;
supply0 VAR5;
supply1 VAR2 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a211oi/sky130_fd_sc_lp__a211oi.behavioral.pp.v | 2,044 | module MODULE1 (
VAR13 ,
VAR16 ,
VAR2 ,
VAR15 ,
VAR6 ,
VAR4,
VAR3,
VAR14 ,
VAR10
);
output VAR13 ;
input VAR16 ;
input VAR2 ;
input VAR15 ;
input VAR6 ;
input VAR4;
input VAR3;
input VAR14 ;
input VAR10 ;
wire VAR7 ;
wire VAR8 ;
wire VAR12;
and VAR5 (VAR7 , VAR16, VAR2 );
nor VAR11 (VAR8 , VAR7, VAR15, VAR6 );
VAR1 VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlygate4sd1/sky130_fd_sc_hdll__dlygate4sd1.pp.blackbox.v | 1,317 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR2,
VAR6,
VAR1 ,
VAR3
);
output VAR5 ;
input VAR4 ;
input VAR2;
input VAR6;
input VAR1 ;
input VAR3 ;
endmodule | apache-2.0 |
vvk/sysrek | rgb2hsv/ipcore_dir/sub12.v | 18,820 | module MODULE2 (
clk, VAR61, VAR59, VAR166, VAR47
);
input clk;
input VAR61;
input [11 : 0] VAR59;
input [11 : 0] VAR166;
output [11 : 0] VAR47;
wire \VAR186/VAR196 ;
wire \VAR186/VAR26 ;
wire \VAR186/VAR110 ;
wire \VAR186/VAR68 ;
wire \VAR186/VAR208 ;
wire \VAR186/VAR174 ;
wire \VAR186/VAR63 ;
wire \VAR186/VAR112 ;
wi... | gpl-2.0 |
8l/kestrel | 2/nexys2/uxa/ps2io/M_uxa_ps2.v | 2,362 | module MODULE1(
output VAR17,
output VAR37,
input VAR22,
input VAR38,
input VAR29,
input VAR18,
output VAR15,
input VAR30,
input VAR32,
input [9:8] VAR26,
output [15:0] VAR39
);
wire VAR27;
wire VAR35;
wire VAR7;
wire VAR10;
wire [7:0] VAR23;
wire VAR45;
wire VAR43 = (VAR18 | VAR10);
VAR48 VAR46 (
.VAR29(VAR29),
.VAR18... | apache-2.0 |
cliffordwolf/yosys | techlibs/xilinx/abc9_model.v | 1,497 | module \VAR2 (output VAR5, input VAR3, VAR1, VAR6, VAR8, VAR4, VAR7);
assign VAR5 = VAR7 ? (VAR4 ? VAR8 : VAR6)
: (VAR4 ? VAR1 : VAR3); | isc |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv3sd3/sky130_fd_sc_ms__clkdlyinv3sd3_1.v | 2,164 | module MODULE2 (
VAR2 ,
VAR5 ,
VAR6,
VAR4,
VAR8 ,
VAR1
);
output VAR2 ;
input VAR5 ;
input VAR6;
input VAR4;
input VAR8 ;
input VAR1 ;
VAR7 VAR3 (
.VAR2(VAR2),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR2,
VAR5
);
output VAR2;
input VAR5;
supply1 VAR6;
supply0 VAR4;... | apache-2.0 |
colinww/spi-core-generator | templates/spi_map_template.v | 3,363 | module MODULE1(
VAR13, VAR12, VAR8, VAR3, VAR4,
VAR14);
input VAR13;
input VAR12;
input [7:0] VAR8;
input VAR3;
input [2:0] VAR4;
inout [7:0] VAR14;
reg [7:0] VAR2;
wire VAR7 = VAR13 && VAR12;
reg [7:0] VAR10;
reg VAR6;
reg VAR5;
reg [7:0] VAR1;
always @( posedge VAR3 or negedge VAR7 ) begin : VAR11
if ( !VAR7 ) begin
... | gpl-3.0 |
natsutan/NPU | fpga_implement/npu8/npu8.ip_user_files/ip/mul8_8/mul8_8_stub.v | 1,246 | module MODULE1(VAR4, VAR2, VAR3, VAR1)
;
input VAR4;
input [7:0]VAR2;
input [7:0]VAR3;
output [15:0]VAR1;
endmodule | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlrbp/sky130_fd_sc_lp__dlrbp_2.v | 2,474 | module MODULE2 (
VAR4 ,
VAR7 ,
VAR5,
VAR9 ,
VAR2 ,
VAR6 ,
VAR8 ,
VAR1 ,
VAR3
);
output VAR4 ;
output VAR7 ;
input VAR5;
input VAR9 ;
input VAR2 ;
input VAR6 ;
input VAR8 ;
input VAR1 ;
input VAR3 ;
VAR10 VAR11 (
.VAR4(VAR4),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR... | apache-2.0 |
keith-epidev/VHDL-lib | top/lab_4/part_1/ip/fft/fft_stub.v | 2,397 | module MODULE1(VAR5, VAR6, VAR17, VAR12, VAR7, VAR1, VAR13, VAR19, VAR3, VAR11, VAR18, VAR2, VAR14, VAR16, VAR15, VAR10, VAR8, VAR4, VAR9)
;
input VAR5;
input [7:0]VAR6;
input VAR17;
output VAR12;
input [31:0]VAR7;
input VAR1;
output VAR13;
input VAR19;
output [63:0]VAR3;
output [15:0]VAR11;
output VAR18;
input VAR2;
o... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a22o/sky130_fd_sc_hs__a22o.behavioral.pp.v | 2,052 | module MODULE1 (
VAR11,
VAR2,
VAR4 ,
VAR15 ,
VAR6 ,
VAR9 ,
VAR16
);
input VAR11;
input VAR2;
output VAR4 ;
input VAR15 ;
input VAR6 ;
input VAR9 ;
input VAR16 ;
wire VAR16 VAR5 ;
wire VAR16 VAR14 ;
wire VAR1 ;
wire VAR10;
and VAR7 (VAR5 , VAR9, VAR16 );
and VAR8 (VAR14 , VAR15, VAR6 );
or VAR3 (VAR1 , VAR14, VAR5 );
VA... | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/data_compression/8-way_2-tree/src/ip_pcie/source/PCIeGen2x8If128_gt_rx_valid_filter_7x.v | 9,181 | module MODULE1 #(
parameter VAR15 = 28,
parameter VAR21 = 1
)
(
output [1:0] VAR44,
output [15:0] VAR24,
output VAR7,
output VAR35,
output [ 2:0] VAR25,
output VAR23,
input [1:0] VAR32,
input [15:0] VAR3,
input VAR18,
input VAR29,
input [ 2:0] VAR45,
input VAR9,
input VAR6,
input VAR37,
input VAR28,
input VAR27
);
loca... | mit |
crespum/N64-controller-FPGA | n64_readcmd_rx.v | 1,598 | module MODULE1(input wire VAR16,
input wire din,
input wire enable,
output reg [31:0] VAR5,
output wire VAR13);
wire [6:0] VAR17;
VAR15 #(.VAR4(7), .VAR9(7'b1111111))
VAR8 (
.clk(VAR16),
.enable(enable),
.VAR7(din),
.VAR6(VAR17)
);
wire [32:0] VAR3;
VAR15 #(.VAR4(33), .VAR9(33'b0))
VAR1 (
.clk(~VAR17[6]),
.enable(enabl... | gpl-3.0 |
Elphel/x393_sata | device/oob_dev.v | 18,131 | module MODULE1 #(
parameter VAR5 = 4,
parameter VAR39 = 2, parameter VAR14 = 2, parameter VAR50 = 'h28, parameter VAR53 = 'h80 )
(
input wire clk,
input wire rst,
input wire VAR2,
input wire VAR18,
input wire VAR37,
input wire VAR31,
output reg VAR25,
output reg VAR13,
output reg VAR26,
output wire VAR42,
input wire VA... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig11/mig_7series_v1_1/user_design/rtl/phy/byte_lane.v | 24,334 | module MODULE1 #(
parameter VAR67 = "VAR28", parameter VAR283 = "VAR259",
parameter VAR128 = 12'b111111111111,
parameter VAR282 = 12'b000000000000,
parameter VAR205 = "VAR30",
parameter VAR10 = "VAR297",
parameter VAR257 = 1,
parameter VAR251 = 1,
parameter VAR227 = "VAR153",
parameter VAR248 = "VAR30",
parameter VAR17... | lgpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_ready_to_credit_flow_converter.v | 2,100 | module MODULE1 #( parameter VAR16(VAR23 )
, parameter VAR16(VAR10 )
, parameter VAR6 = 1
, parameter VAR15 =
)
( input VAR4
, input VAR24
, input VAR7
, output VAR1
, output VAR18
, input VAR22
);
localparam VAR12 = VAR3(VAR6);
logic [VAR12-1:0] VAR9,VAR13;
logic [VAR15-1:0] VAR11;
assign VAR1 = (VAR11!=0);
assign VAR1... | bsd-3-clause |
Canaan-Creative/MM | verilog/superkdf9/components/uart_core/txcver_fifo.v | 4,276 | module MODULE1 (VAR19, VAR15, VAR30, VAR1, VAR18, VAR9, VAR13, VAR32,
VAR11, VAR10);
input [7:0] VAR19;
input VAR15;
input VAR30;
input VAR1;
input VAR18;
output [7:0] VAR9;
output VAR13;
output VAR32;
output VAR11;
output VAR10;
parameter VAR2 = VAR21;
generate
if (VAR2 == "VAR26" || VAR2 == "VAR25") begin
VAR20 #(.VA... | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and4bb/sky130_fd_sc_hdll__and4bb_1.v | 2,339 | module MODULE1 (
VAR9 ,
VAR4 ,
VAR7 ,
VAR3 ,
VAR11 ,
VAR2,
VAR5,
VAR10 ,
VAR1
);
output VAR9 ;
input VAR4 ;
input VAR7 ;
input VAR3 ;
input VAR11 ;
input VAR2;
input VAR5;
input VAR10 ;
input VAR1 ;
VAR6 VAR8 (
.VAR9(VAR9),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR11(VAR11),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR10(VAR10),
.... | apache-2.0 |
rfotino/consolite-hardware | src/pixel_writer.v | 3,615 | module MODULE1
(
input clk,
input VAR19,
output reg VAR21,
output VAR10,
input VAR11,
input [7:0] VAR18,
input [7:0] VAR15,
input [7:0] VAR6,
output reg VAR12,
output wire [2:0] VAR20,
output reg [5:0] VAR9,
output reg [29:0] VAR14,
input VAR13,
input VAR4,
output reg VAR8,
output reg [3:0] VAR3,
output reg [31:0] VAR2... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sedfxbp/sky130_fd_sc_ls__sedfxbp.behavioral.pp.v | 2,768 | module MODULE1 (
VAR17 ,
VAR27 ,
VAR10 ,
VAR12 ,
VAR16 ,
VAR3 ,
VAR25 ,
VAR13,
VAR5,
VAR31 ,
VAR15
);
output VAR17 ;
output VAR27 ;
input VAR10 ;
input VAR12 ;
input VAR16 ;
input VAR3 ;
input VAR25 ;
input VAR13;
input VAR5;
input VAR31 ;
input VAR15 ;
wire VAR30 ;
reg VAR8 ;
wire VAR19 ;
wire VAR14 ;
wire VAR29;
wire... | apache-2.0 |
super5516/ICLAB-hw4 | lzc_t.v | 1,750 | module MODULE1;
parameter VAR3 = 10;
parameter delay = 1;
reg clk, VAR7, VAR9, VAR5;
reg [VAR23-1:0] VAR6;
wire VAR24;
wire [8:0] VAR19;
reg VAR25;
reg [8*128-1:0] VAR10, VAR15, VAR13;
reg [VAR23+1:0] VAR26[0:30000];
reg [8:0] VAR17[0:30000];
integer VAR22, VAR4, VAR27;
VAR14 #(
.VAR12(VAR23),
.word(VAR20))
VAR18 (
.VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_dff_nr_pp_pkg_s/sky130_fd_sc_lp__udp_dff_nr_pp_pkg_s.blackbox.v | 1,463 | module MODULE1 (
VAR8 ,
VAR6 ,
VAR3 ,
VAR5 ,
VAR1,
VAR7 ,
VAR4 ,
VAR2
);
output VAR8 ;
input VAR6 ;
input VAR3 ;
input VAR5 ;
input VAR1;
input VAR7 ;
input VAR4 ;
input VAR2 ;
endmodule | apache-2.0 |
drichmond/riffa | fpga/xilinx/NetFPGA/riffa_wrapper_NetFPGA.v | 35,513 | module MODULE1
parameter VAR146 = 128,
parameter VAR73 = 256,
parameter VAR59 = 5,
parameter VAR213 = "7V30")
( input VAR61,
input VAR279,
input [VAR146-1:0] VAR99,
input [(VAR146/32)-1:0] VAR180,
input [VAR106-1:0] VAR189,
output VAR1,
input VAR194,
input VAR311,
input [VAR146-1:0] VAR251,
input [(VAR146/32)-1:0] VAR3... | bsd-3-clause |
ShepardSiegel/ocpi | coregen/temac_axi_v5_2/example_design/axi_ipif/slave_attachment.v | 23,835 | module MODULE1
parameter VAR111 = 2,
parameter VAR137 = 16,
parameter [0:32*2*VAR111-1]VAR30 =
{2*VAR111
{32'h00000000}},
parameter [0:8*VAR111-1] VAR132 =
{VAR111{8'd4}},
parameter VAR3 = 32,
parameter VAR40 = 32,
parameter [31:0] VAR58 = 'h000001FF,
parameter VAR106 = 0,
parameter VAR108 = 16,
parameter VAR129 = "VAR... | lgpl-3.0 |
markusC64/1541ultimate2 | fpga/nios/nios/synthesis/submodules/alt_mem_ddrx_arbiter.v | 52,523 | module MODULE1 #
( parameter
VAR126 = 4,
VAR95 = 4,
VAR105 = "VAR90",
VAR162 = 0,
VAR112 = 0,
VAR14 = 1,
VAR56 = 1,
VAR72 = 3,
VAR116 = 13,
VAR92 = 10,
VAR91 = 10,
VAR160 = 10,
VAR161 = 4,
VAR11 = 2,
VAR139 = 1
)
(
VAR68,
VAR140,
VAR177,
VAR45,
VAR47,
VAR184,
VAR39,
VAR120,
VAR36,
VAR149,
VAR64,
VAR106,
VAR83,
VAR74,
V... | gpl-3.0 |
jtillma3/fpga_tutorial | projects/project2/src/serial_rx.v | 2,454 | module MODULE1 #(
parameter VAR23 = 50
)(
input clk,
input rst,
input VAR15,
output [7:0] VAR11,
output VAR6
);
parameter VAR19 = VAR2(VAR23);
localparam VAR20 = 2;
localparam VAR4 = 2'd0,
VAR18 = 2'd1,
VAR21 = 2'd2,
VAR22 = 2'd3;
reg [VAR19-1:0] VAR8, VAR5;
reg [2:0] VAR1, VAR7;
reg [7:0] VAR12, VAR9;
reg VAR14, VAR10... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/isolatch/sky130_fd_sc_lp__isolatch.pp.blackbox.v | 1,345 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR6,
VAR3 ,
VAR8 ,
VAR4 ,
VAR2 ,
VAR7
);
output VAR5 ;
input VAR1 ;
input VAR6;
input VAR3 ;
input VAR8 ;
input VAR4 ;
input VAR2 ;
input VAR7 ;
endmodule | apache-2.0 |
liqimai/ZPC | PersonalComputer/Adder16.v | 1,351 | module MODULE1(
input [15:0] VAR11,
input [15:0] VAR3,
input VAR8,
output [3:0] VAR15,
output [3:0] VAR1,
output [15:0] sum,
output VAR19,
output VAR10,
output VAR18,
output VAR12,
output VAR4
);
wire[15:0] VAR6,VAR20;
wire[4:0] VAR14;
wire[3:0] VAR9,VAR17,VAR21,VAR23,VAR24;
VAR25 VAR25(VAR6,VAR20,VAR15,VAR1);
VAR7 VAR... | gpl-2.0 |
itpcc/FPGA-IA-Journy-game | verilog/bulletPosition-26.v | 3,092 | module MODULE1(
input clk,
input VAR5,
input wire [9:0] VAR6,
input wire [8:0] VAR10,
input wire [9:0] VAR4,
input wire [8:0] VAR11,
input wire [1:0] VAR1,
input VAR3,
input VAR15,
input wire [4:0] VAR7,
input wire [4:0] VAR16,
input reset,
output reg VAR8,
output reg VAR2,
output reg [9:0] VAR14,
output reg [8:0] VAR1... | mit |
pemsac/ANN_project | ANN_project.ip_user_files/ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_aw_channel.v | 3,891 | module MODULE1 #
(
parameter integer VAR13 = 4,
parameter integer VAR26 = 32
)
(
input wire clk ,
input wire reset ,
input wire [VAR13-1:0] VAR28 ,
input wire [VAR26-1:0] VAR30 ,
input wire [7:0] VAR22 ,
input wire [2:0] VAR18 ,
input wire [1:0] VAR5 ,
input wire VAR10 ,
output wire VAR15 ,
output wire VAR17 ,
output w... | gpl-3.0 |
eda-globetrotter/MarcheProcessor | final/src/tosynth Folder/alu_shift.v | 95,820 | module MODULE1 (VAR2,VAR3,VAR1,VAR4,VAR6);
output [0:127] VAR6;
input [0:127] VAR2;
input [0:127] VAR3;
input [0:1] VAR1;
input [0:4] VAR4;
parameter VAR5 = 128'hffffffffffffffffffffffffffffffff;
reg [0:127] VAR6;
integer VAR9;
integer VAR7;
integer VAR8;
always @(VAR2 or VAR3 or VAR1 or VAR4)
begin
case(VAR4)
begin
ca... | mit |
OpticalMeasurementsSystems/2DImageProcessing | src/clock_divider.v | 1,328 | module MODULE1 #
(
parameter VAR1 = 2
)
(
input wire reset,
input wire VAR2,
output wire VAR4
);
reg[7:0] counter;
reg VAR3;
assign VAR4 = VAR1 == 1 ? VAR2 & reset : VAR3;
always @(posedge VAR2)
begin
if(~reset)
begin
counter <= 0;
VAR3 <= 0;
end
else
begin
if(counter == VAR1 - 1)
begin
VAR3 <= ~VAR3;
counter <= 1;
end... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor3/sky130_fd_sc_ms__nor3.behavioral.v | 1,405 | module MODULE1 (
VAR8,
VAR1,
VAR10,
VAR2
);
output VAR8;
input VAR1;
input VAR10;
input VAR2;
supply1 VAR7;
supply0 VAR11;
supply1 VAR5 ;
supply0 VAR6 ;
wire VAR3;
nor VAR4 (VAR3, VAR2, VAR1, VAR10 );
buf VAR9 (VAR8 , VAR3 );
endmodule | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/new/SHD_PE.v | 2,175 | module MODULE1 #(parameter VAR28 = 128) (
input clk,
input rst,
input[VAR28 - 1:0] VAR16,
input[VAR28 - 1:0] VAR18,
input VAR23,
output VAR4,
input VAR20,
input VAR25,
output[7:0] VAR3,
output VAR15
);
reg[VAR28 - 1:0] VAR9, VAR6;
reg VAR1;
always@(posedge clk) begin
if(rst) begin
VAR1 <= 1'b0;
VAR9 <= 0;
VAR6 <= 0;
en... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/addh/gf180mcu_fd_sc_mcu9t5v0__addh_1.behavioral.v | 1,502 | module MODULE1( VAR3, VAR2, VAR7, VAR5 );
input VAR2, VAR7;
output VAR3, VAR5;
VAR4 VAR6(.VAR3(VAR3),.VAR2(VAR2),.VAR7(VAR7),.VAR5(VAR5));
VAR4 VAR1(.VAR3(VAR3),.VAR2(VAR2),.VAR7(VAR7),.VAR5(VAR5)); | apache-2.0 |
UA3MQJ/fpga-synth | modules/lin2exp.v | 3,546 | module MODULE1(VAR10, VAR1);
input wire [6:0] VAR10;
output wire [31:0] VAR1;
wire [31:0] VAR4 = 7540 - ({VAR10,8'b0}+{VAR10,6'b0}+{VAR10,5'b0}+{VAR10,3'b0}+{VAR10,2'b0});
wire [31:0] VAR5 = 6637 - ({VAR10,8'b0}-{VAR10,5'b0}+{VAR10,3'b0}+{VAR10,1'b0});
wire [31:0] VAR9 = 5317 - ({VAR10,7'b0}+{VAR10,4'b0}+{VAR10,1'b0}+V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xnor2/sky130_fd_sc_lp__xnor2.pp.symbol.v | 1,304 | module MODULE1 (
input VAR7 ,
input VAR1 ,
output VAR5 ,
input VAR3 ,
input VAR6,
input VAR2,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr_1.v | 2,290 | module MODULE2 (
VAR1 ,
VAR2 ,
VAR5 ,
VAR8 ,
VAR6,
VAR3 ,
VAR4
);
output VAR1 ;
input VAR2 ;
input VAR5 ;
input VAR8 ;
input VAR6;
input VAR3 ;
input VAR4 ;
VAR7 VAR9 (
.VAR1(VAR1),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR1,
VAR2
);
output VAR1;
inpu... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21a/sky130_fd_sc_hs__o21a.symbol.v | 1,305 | module MODULE1 (
input VAR2,
input VAR1,
input VAR4,
output VAR5
);
supply1 VAR6;
supply0 VAR3;
endmodule | apache-2.0 |
davidkoltak/tawas-core | ip/tawas/rtl/tawas_rcn_master.v | 1,569 | module MODULE1
(
input rst,
input clk,
input [68:0] VAR6,
output [68:0] VAR9,
input VAR13,
input [4:0] VAR11,
output VAR7,
input wr,
input [3:0] VAR8,
input [23:0] addr,
input [31:0] VAR3,
output VAR12,
output VAR14,
output [4:0] VAR4,
output [3:0] VAR15,
output [23:0] VAR16,
output [31:0] VAR1
);
parameter VAR2 = 0;
r... | mit |
DougFirErickson/parallella-hw | fpga/old/e_mmu/hdl/e_mmu.v | 6,064 | module MODULE1 (
VAR12, VAR42, VAR4, VAR3,
VAR15, VAR40, VAR2,
VAR19,
clk, VAR10, VAR1, VAR6, VAR33, VAR43,
VAR13, VAR41, VAR29,
VAR5, VAR38, VAR31,
VAR34
);
parameter VAR28 = 32; parameter VAR21 = 32; parameter VAR8 = 12; parameter VAR30 = 64; parameter VAR27 = VAR30-VAR21+VAR8; parameter VAR37 = 1<<VAR8;
input clk;
i... | gpl-3.0 |
Jawanga/ece385final | usb_system/synthesis/submodules/altera_avalon_dc_fifo.v | 26,090 | module MODULE1(
VAR85,
VAR17,
VAR93,
VAR73,
VAR44,
VAR33,
VAR68,
VAR21,
VAR54,
VAR11,
VAR94,
VAR2,
VAR36,
VAR61,
VAR14,
VAR82,
VAR96,
VAR77,
VAR103,
VAR58,
VAR34,
VAR3,
VAR48,
VAR106,
VAR70,
VAR80,
VAR35,
VAR29,
VAR19,
VAR9,
VAR16,
VAR84,
VAR53,
VAR7,
VAR83
);
parameter VAR22 = 1;
parameter VAR41 = 8;
parameter VAR24 =... | apache-2.0 |
SymbiFlow/prjuray | spec/slice_carry.v | 16,976 | module MODULE4 #(
parameter [1023:0] VAR21 = "",
parameter [1023:0] VAR75 = "",
parameter [63:0] VAR100 = 64'h00C0FFEE,
parameter [63:0] VAR198 = 64'h00C0FFEE,
parameter [63:0] VAR90 = 64'h00C0FFEE,
parameter [63:0] VAR66 = 64'h00C0FFEE,
parameter [63:0] VAR87 = 64'h00C0FFEE,
parameter [63:0] VAR72 = 64'h00C0FFEE,
para... | isc |
hoang26/processor_verilog | 5_control.v | 1,182 | module MODULE1(
input [5:0] VAR6,
input clk,
output reg VAR3,
output reg VAR2,
output reg VAR9,
output reg VAR7,
output reg VAR4,
output reg VAR10,
output reg VAR5,
output reg VAR8,
output reg [1:0] VAR1
);
always@(posedge clk)
begin
{VAR3, VAR5, VAR4, VAR8, VAR7, VAR10, VAR9, VAR2, VAR1} = 10'b0000000000;
if (VAR6 == ... | gpl-2.0 |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/acl_fp_add.v | 130,366 | module MODULE1
(
VAR5,
VAR13,
VAR8,
VAR4,
VAR9,
VAR14) ;
input VAR5;
input VAR13;
input VAR8;
input [25:0] VAR4;
input [4:0] VAR9;
output [25:0] VAR14;
tri0 VAR5;
tri1 VAR13;
tri0 VAR8;
reg [0:0] VAR11;
reg [25:0] VAR10;
wire [5:0] VAR6;
wire VAR1;
wire [15:0] VAR12;
wire [155:0] VAR3;
wire [4:0] VAR2;
wire [129:0] VAR... | mit |
anguslin/RISC | register.v | 1,397 | module MODULE1(clk, VAR18, VAR4, write, VAR9, VAR14, VAR10, VAR6, VAR8, VAR17 ,VAR2 ,VAR19 ,VAR1, VAR5, VAR16);
parameter VAR11= 1;
input clk, VAR18, VAR4, write;
input [2:0] VAR9;
input [15:0] VAR14, VAR10, VAR6, VAR8, VAR17 ,VAR2 ,VAR19 ,VAR1;
output [15:0] VAR5, VAR16;
reg [15:0] VAR3;
always @(*) begin
case(VAR9)
3... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_1.behavioral.v | 2,148 | module MODULE1( VAR9, VAR4, VAR1 );
input VAR9, VAR4;
output VAR1;
reg VAR11;
VAR3 VAR2(.VAR9(VAR9),.VAR4(VAR4),.VAR1(VAR1),.VAR11(VAR11));
VAR3 VAR8(.VAR9(VAR9),.VAR4(VAR4),.VAR1(VAR1),.VAR11(VAR11));
not VAR7(VAR6,VAR4);
buf VAR5(VAR10,VAR4); | apache-2.0 |
Vadman97/ImageAES | des/DES/encrypt.v | 3,207 | module MODULE1(
VAR5,
VAR13,
VAR14,
VAR11,
clk,
reset,
enable,
ack
);
input [7:0][7:0] VAR5;
input [7:0][7:0] VAR13;
output [7:0][7:0] VAR14;
input clk, reset, enable, ack;
output VAR11;
reg [63:0] VAR17, VAR9, VAR2;
reg [5:0] state;
reg [55:0] VAR16;
reg [63:0] VAR10;
integer VAR1[55:0] = {57, 49, 41, 33, 25, 17, 9, 1... | gpl-3.0 |
CospanDesign/nysa-verilog | verilog/generic/video_to_block_fifo.v | 2,623 | module MODULE1 #(
parameter VAR28 = 9
)(
input clk,
input rst,
input VAR19,
input VAR7,
input VAR30,
input [7:0] VAR21,
input [7:0] VAR31,
input [7:0] VAR9,
input VAR12,
input VAR26,
output VAR15,
input VAR13,
input VAR20,
output [24:0] VAR36,
output [23:0] VAR25
);
wire VAR3;
reg VAR33;
wire [23:0] VAR14;
reg VAR34;
r... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/lsbuf/sky130_fd_sc_lp__lsbuf.blackbox.v | 1,264 | module MODULE1 (
VAR2,
VAR6
);
output VAR2;
input VAR6;
supply1 VAR3;
supply1 VAR7 ;
supply0 VAR8 ;
supply1 VAR5;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
rkrajnc/minimig-mist | rtl/minimig/denise_collision.v | 4,954 | module MODULE1
(
input clk, input VAR6,
input reset, input VAR15, input [8:1] VAR4, input [15:0] VAR12, output [15:0] VAR1, input VAR8, input [7:0] VAR7, input [7:0] VAR13
);
parameter VAR21 = 9'h098;
parameter VAR5 = 9'h10e;
parameter VAR16 = 9'h00e;
reg [15:0] VAR20; reg [15:0] VAR3; reg [14:0] VAR17; wire [3:0] VAR1... | gpl-3.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/fme/fme_cost.v | 23,218 | module MODULE1 (
clk ,
VAR51 ,
VAR22 ,
VAR136 ,
VAR38 ,
VAR111 ,
VAR134 ,
VAR18 ,
VAR39 ,
VAR29 ,
VAR58 ,
VAR53 ,
VAR124 ,
VAR160 ,
VAR93 ,
VAR15 ,
VAR32 ,
VAR122 ,
VAR24 ,
VAR125 ,
VAR72 ,
VAR21 ,
VAR5 ,
VAR140 ,
VAR105
);
parameter VAR71 = VAR28 + 10;
input [1-1:0] clk ; input [1-1:0] VAR51 ; input [6-1 :0] VAR22 ; i... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/xnor2/sky130_fd_sc_hvl__xnor2.behavioral.v | 1,405 | module MODULE1 (
VAR2,
VAR1,
VAR7
);
output VAR2;
input VAR1;
input VAR7;
supply1 VAR6;
supply0 VAR5;
supply1 VAR8 ;
supply0 VAR10 ;
wire VAR4;
xnor VAR3 (VAR4, VAR1, VAR7 );
buf VAR9 (VAR2 , VAR4 );
endmodule | apache-2.0 |
alexforencich/hdg2000 | fpga/lib/axis/rtl/axis_stat_counter.v | 11,736 | module MODULE1 #
(
parameter VAR61 = 64,
parameter VAR48 = (VAR61/8),
parameter VAR8 = 1,
parameter VAR51 = 16,
parameter VAR20 = 1,
parameter VAR21 = 32,
parameter VAR1 = 1,
parameter VAR9 = 32,
parameter VAR12 = 1,
parameter VAR28 = 32
)
(
input wire clk,
input wire rst,
input wire [VAR48-1:0] VAR19,
input wire VAR30... | mit |
martinmiranda14/Digitales | Lab_6/new/Calculadora_monitor.v | 8,567 | module MODULE1(
input VAR33,
input reset,
input [63:0] VAR22,
input VAR50,
input [7:0] VAR14,
input [2:0] VAR17,
input [2:0] VAR6,
input VAR29,
output reg [63:0] VAR3,
output wire [3:0] VAR4,
output [1:0] VAR46,
output reg VAR7,
output [15:0] VAR31,
output reg VAR56
);
localparam VAR32=2'b00; localparam VAR25=2'b01;
lo... | apache-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/systems/neek/backend/rtl/verilog/ddr_ctrl_ip/ddr_ctrl_ip.v | 31,218 | module MODULE1 (
VAR61,
VAR4,
VAR53,
VAR19,
VAR27,
VAR106,
VAR22,
VAR42,
VAR52,
VAR70,
VAR44,
VAR18,
VAR84,
VAR37,
VAR20,
VAR85,
VAR16,
VAR14,
VAR100,
VAR32,
VAR96,
VAR9,
VAR5,
VAR50,
VAR89,
VAR31,
VAR81,
VAR63,
VAR72,
VAR13,
VAR47,
VAR71,
VAR62);
input [22:0] VAR61;
input VAR4;
input VAR53;
input VAR19;
input [31:0] V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfrtn/sky130_fd_sc_hs__dfrtn.functional.pp.v | 1,921 | module MODULE1 (
VAR14 ,
VAR5 ,
VAR13 ,
VAR4 ,
VAR7 ,
VAR6
);
input VAR14 ;
input VAR5 ;
output VAR13 ;
input VAR4 ;
input VAR7 ;
input VAR6;
wire VAR11 ;
wire VAR9 ;
wire VAR8;
not VAR12 (VAR9 , VAR6 );
not VAR3 (VAR8, VAR4 );
VAR1 VAR15 VAR2 (VAR11 , VAR7, VAR8, VAR9, VAR14, VAR5);
buf VAR10 (VAR13 , VAR11 );
endmodu... | apache-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/acl_fp_atan_s5.v | 1,182 | module MODULE1 (
enable,
VAR5,
VAR2,
VAR8);
input enable;
input VAR5;
input [31:0] VAR2;
output [31:0] VAR8;
wire [31:0] VAR6;
wire [31:0] VAR8 = VAR6[31:0];
VAR9 VAR3 (
.en (enable),
.VAR7(1'b0),
.clk(VAR5),
.VAR1(VAR2),
.VAR4(VAR6));
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfrtp/sky130_fd_sc_hd__sdfrtp.pp.blackbox.v | 1,474 | module MODULE1 (
VAR2 ,
VAR7 ,
VAR6 ,
VAR1 ,
VAR9 ,
VAR8,
VAR3 ,
VAR4 ,
VAR5 ,
VAR10
);
output VAR2 ;
input VAR7 ;
input VAR6 ;
input VAR1 ;
input VAR9 ;
input VAR8;
input VAR3 ;
input VAR4 ;
input VAR5 ;
input VAR10 ;
endmodule | apache-2.0 |
asicguy/gplgpu | stim/avalon_fast_model.v | 15,543 | parameter VAR98 = 10;
parameter VAR100 = VAR98+1;
parameter VAR39 = 32'h100000;
parameter VAR12 = 27;
parameter VAR50 = 23;
parameter VAR47 = 1;
module MODULE2
(
VAR112,
VAR9,
VAR76,
VAR41,
VAR6,
VAR86,
VAR24,
VAR38,
VAR3,
VAR108,
VAR71,
VAR25,
VAR92,
VAR91,
VAR79,
VAR8,
VAR20,
VAR44,
VAR61,
VAR45,
VAR52,
VAR110,
VAR81... | gpl-3.0 |
zeldin/iceGDROM | fpga/source/avr/avr109tx.v | 1,554 | module MODULE1 (
input rst,
input clk,
input[7:0] VAR10,
input VAR6,
output VAR9,
output VAR8
);
parameter VAR14 = 1000000;
parameter VAR16 = 19200;
function integer VAR12;
input integer VAR1;
begin
VAR1 = VAR1-1;
for (VAR12=0; VAR1>0; VAR12=VAR12+1)
VAR1 = VAR1>>1;
end
endfunction
localparam VAR18 = (VAR14 / VAR16);
l... | gpl-3.0 |
jmahler/mips-cpu | control.v | 1,263 | module MODULE1(
input wire [5:0] VAR5,
output reg VAR4, VAR8,
output reg [1:0] VAR1,
output reg VAR11, VAR9, VAR6,
output reg VAR10, VAR7, VAR2,
output reg VAR3);
always @(*) begin
VAR1[1:0] <= 2'b10;
VAR2 <= 1'b0;
VAR4 <= 1'b0;
VAR8 <= 1'b0;
VAR11 <= 1'b0;
VAR6 <= 1'b0;
VAR9 <= 1'b0;
VAR10 <= 1'b1;
VAR7 <= 1'b1;
VAR3 ... | gpl-3.0 |
makestuff/comm-fpga | epp/verilog/comm_fpga_epp.v | 5,939 | module
MODULE1(
input wire VAR25, input wire VAR24, output reg VAR29,
inout wire[7:0] VAR4, input wire VAR3, input wire VAR11, input wire VAR16, output wire VAR1,
output wire[6:0] VAR20,
output reg[7:0] VAR28, output reg VAR31, input wire VAR34,
input wire[7:0] VAR5, input wire VAR33, output reg VAR14 );
localparam[2:0... | gpl-3.0 |
tofuman/nand-proz | Prozessor/RegisterBank.v | 1,544 | module MODULE1 (VAR14, VAR3, VAR12, VAR13, VAR9, VAR2, VAR10, enable);
input wire [2:0] VAR14, VAR3, VAR12, VAR2;
output wire [7:0] VAR13, VAR9;
input wire [2:0] VAR10;
input wire enable;
reg [7:0] VAR6,VAR4,VAR8,VAR7,VAR11,VAR5,VAR1,VAR15;
always @ (posedge enable) begin
if (VAR10[0]) begin
case(VAR14)
0 : VAR13 = VAR... | gpl-2.0 |
bluespec/Flute | builds/AWSteria_Core_Flute_RV64_Linux/Verilog_RTL_PLATFORM_AWSF1/mkAXI4_Deburster_A.v | 48,689 | module MODULE1(VAR99,
VAR89,
VAR35,
VAR12,
VAR225,
VAR118,
VAR22,
VAR204,
VAR226,
VAR17,
VAR206,
VAR176,
VAR81,
VAR139,
VAR188,
VAR61,
VAR5,
VAR82,
VAR198,
VAR155,
VAR277,
VAR137,
VAR262,
VAR240,
VAR221,
VAR87,
VAR245,
VAR165,
VAR73,
VAR75,
VAR266,
VAR149,
VAR128,
VAR113,
VAR66,
VAR135,
VAR158,
VAR195,
VAR138,
VAR116,
... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_cam_1r1w_tag_array.v | 2,509 | module MODULE1
, parameter VAR41(VAR20)
, parameter VAR14 = 0
, parameter VAR34 = VAR2(VAR20,1)
)
(input VAR36
, input VAR6
, input [VAR34-1:0] VAR12
, input VAR28
, input [VAR26-1:0] VAR24
, output logic [VAR34-1:0] VAR23
, input VAR39
, input [VAR26-1:0] VAR19
, output logic [VAR34-1:0] VAR43
);
logic [VAR34-1:0][VAR... | bsd-3-clause |
SymbiFlow/yosys-f4pga-plugins | ql-qlf-plugin/qlf_k6n10f/ufifo_ctl.v | 19,645 | module MODULE1 (
VAR50,
VAR57,
VAR38,
VAR46,
sync,
VAR63,
VAR69,
VAR68,
VAR70,
VAR4,
VAR27,
VAR10,
VAR79,
VAR76,
VAR12,
VAR62
);
parameter VAR15 = 11;
parameter VAR72 = 3'd2;
localparam VAR20 = VAR15 + 1;
output wire [VAR15 - 1:0] VAR50;
output wire [VAR15 - 1:0] VAR57;
output wire [7:0] VAR38;
output wire VAR46;
input... | apache-2.0 |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/Source/IP/FIFO_DETECTION_TIME/FIFO_DETECTION_TIME_bb.v | 5,470 | module MODULE1 (
VAR3,
VAR7,
VAR2,
VAR5,
VAR1,
VAR4,
VAR8,
VAR6);
input VAR3;
input [13:0] VAR7;
input VAR2;
input VAR5;
input VAR1;
output VAR4;
output VAR8;
output [13:0] VAR6;
endmodule | gpl-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/master_0/altera_avalon_st_packets_to_bytes/altera_avalon_st_packets_to_bytes.v | 9,555 | module MODULE1
parameter VAR10 = 0)
(
input clk,
input VAR3,
output reg VAR6,
input VAR8,
input [7: 0] VAR15,
input [VAR23-1: 0] VAR12,
input VAR17,
input VAR25,
input VAR22,
output reg VAR14,
output reg [7: 0] VAR16
);
localparam VAR2 = VAR23/7;
reg VAR7, VAR13, VAR1;
reg VAR18, VAR4, VAR11;
reg [VAR23:0] VAR19;
reg [... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlrtp/sky130_fd_sc_hd__dlrtp_1.v | 2,362 | module MODULE1 (
VAR6 ,
VAR4,
VAR2 ,
VAR8 ,
VAR10 ,
VAR1 ,
VAR7 ,
VAR5
);
output VAR6 ;
input VAR4;
input VAR2 ;
input VAR8 ;
input VAR10 ;
input VAR1 ;
input VAR7 ;
input VAR5 ;
VAR3 VAR9 (
.VAR6(VAR6),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR5(VAR5)
);
endmodule
module MODU... | apache-2.0 |
OpenSoCPlus/hight_crypto_core | rtl/RF.v | 7,110 | module MODULE1(
VAR16 ,
VAR19 ,
VAR6 ,
VAR11 ,
VAR10
);
input VAR16 ;
input[31:0] VAR19 ;
input[63:0] VAR6 ;
input VAR11 ;
output[63:0] VAR10 ;
wire[63:0] VAR12 ;
wire[7:0] VAR7 ;
wire[7:0] VAR9 ;
wire[7:0] VAR13 ;
wire[7:0] VAR1 ;
wire[7:0] VAR17 ;
wire[7:0] VAR3 ;
wire[7:0] VAR18 ;
wire[7:0] VAR14 ;
wire[7:0] VAR5 ;
... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlymetal6s2s/sky130_fd_sc_lp__dlymetal6s2s.symbol.v | 1,355 | module MODULE1 (
input VAR6,
output VAR3
);
supply1 VAR4;
supply0 VAR5;
supply1 VAR2 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
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