(\n k_smem, &kv_smem_offset_w, paged_kv, (iter + 1) * 16 * NUM_WARPS_KV * NUM_FRAGS_KV,\n kv_offset, chunk_size);\n cp_async::commit_group();\n cp_async::wait_group<1>();\n block.sync();\n\n // compute sfm*v\n compute_sfm_v<NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV, swizzle_mode_kv, DTypeQ, DTypeKV>(\n variant, &v_smem, &v_smem_offset_r, s_frag, o_frag, d);\n\n block.sync();\n page_produce_kv<true, NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_D, NUM_FRAGS_KV>(\n v_smem, &kv_smem_offset_w, paged_kv, (iter + 1) * 16 * NUM_WARPS_KV * NUM_FRAGS_KV,\n kv_offset, chunk_size);\n cp_async::commit_group();\n }\n cp_async::wait_group<0>();\n block.sync();\n\n // threadblock synchronization\n threadblock_sync_mdo_states<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_Q, NUM_FRAGS_D, DTypeQKAccum>(\n variant, o_frag, (float*)smem, m, d, warp_idx, lane_idx);\n\n // normalize d\n normalize_d<NUM_FRAGS_Q, NUM_FRAGS_D>(variant, o_frag, m, d);\n\n const uint32_t num_kv_chunks = (kv_len_safe + kv_chunk_size - 1) / kv_chunk_size;\n\n // write_back\n write_o_reg_gmem<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_Q, NUM_FRAGS_D>(\n o_frag, &qo_smem, o_ptr_base, qo_packed_idx_base, qo_len,\n /*o_stride_n=*/\n partition_kv ? num_qo_heads * head_dim * num_kv_chunks : num_qo_heads * head_dim,\n /*o_stride_h=*/head_dim, group_size);\n\n // write lse\n if constexpr (variant.use_softmax) {\n if (lse != nullptr) {\n if (get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>() == 0) {\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n uint32_t q, r;\n group_size.divmod(qo_packed_idx_base + lane_idx / 4 + j * 8 + fq * 16, q, r);\n const uint32_t qo_head_idx = kv_head_idx * group_size + r;\n const uint32_t qo_idx = q;\n if (qo_idx < qo_upper_bound) {\n if (partition_kv) {\n lse[(o_indptr[request_idx] + qo_idx * num_kv_chunks + kv_tile_idx) *\n num_qo_heads +\n qo_head_idx] = math::ptx_log2(d[fq][j]) + float(m[fq][j]);\n } else {\n lse[(o_indptr[request_idx] + qo_idx) * num_qo_heads + qo_head_idx] =\n math::ptx_log2(d[fq][j]) + float(m[fq][j]);\n }\n }\n }\n }\n }\n }\n }\n#if (__CUDA_ARCH__ < 800)\n }\n#endif\n}\n\ntemplate <uint32_t CTA_TILE_Q, uint32_t HEAD_DIM, PosEncodingMode POS_ENCODING_MODE,\n bool ALLOW_FP16_QK_REDUCTION, MaskMode MASK_MODE, typename AttentionVariant>\ncudaError_t BatchPrefillWithRaggedKVCacheDispatched(typename AttentionVariant::ParamsT params,\n typename AttentionVariant::DTypeO* tmp_v,\n float* tmp_s, cudaStream_t stream) {\n using DTypeQ = typename AttentionVariant::DTypeQ;\n using DTypeKV = typename AttentionVariant::DTypeKV;\n const uint32_t padded_batch_size = params.padded_batch_size;\n const uint32_t num_qo_heads = params.num_qo_heads;\n const uint32_t num_kv_heads = params.num_kv_heads;\n const uint_fastdiv group_size_fastdiv(num_qo_heads / num_kv_heads);\n const uint32_t total_num_rows = params.total_num_rows;\n constexpr uint32_t NUM_FRAGS_Q = get_num_frags_q(CTA_TILE_Q);\n constexpr uint32_t NUM_WARPS_Q = get_num_warps_q(CTA_TILE_Q);\n constexpr uint32_t NUM_WARPS_KV = get_num_warps_kv(CTA_TILE_Q);\n\n if (padded_batch_size == 0) {\n // No request, skip\n // this won't happen in CUDAGraph mode because we fixed the padded_batch_size\n return cudaSuccess;\n }\n\n dim3 nblks(padded_batch_size, 1, num_kv_heads);\n dim3 nthrs(32, NUM_WARPS_Q, NUM_WARPS_KV);\n constexpr uint32_t NUM_FRAGS_D = HEAD_DIM / 16;\n using DTypeQKAccum =\n typename std::conditional<ALLOW_FP16_QK_REDUCTION && std::is_same_v<DTypeQ, half>, half,\n float>::type;\n\n int dev_id = 0;\n FLASHINFER_CUDA_CALL(cudaGetDevice(&dev_id));\n int max_smem_per_sm = 0;\n FLASHINFER_CUDA_CALL(cudaDeviceGetAttribute(&max_smem_per_sm,\n cudaDevAttrMaxSharedMemoryPerMultiprocessor, dev_id));\n // we expect each sm execute two threadblocks\n // TODO(Zihao): fix the following computation\n const int num_ctas_per_sm = max_smem_per_sm > (16 * HEAD_DIM * sizeof(DTypeQ) * 16) ? 2 : 1;\n const int max_smem_per_threadblock = max_smem_per_sm / num_ctas_per_sm;\n\n const uint32_t max_num_frags_kv_reg =\n (HEAD_DIM >= 128 && NUM_FRAGS_Q == 2 && POS_ENCODING_MODE == PosEncodingMode::kRoPELlama &&\n !ALLOW_FP16_QK_REDUCTION)\n ? 2\n : (8 / NUM_FRAGS_Q);\n // TODO(Zihao): fix the following computation\n const uint32_t max_num_frags_kv_smem =\n (max_smem_per_threadblock / (16 * HEAD_DIM * sizeof(DTypeQ)) - NUM_FRAGS_Q * NUM_WARPS_Q) /\n (2 * NUM_WARPS_KV);\n\n DISPATCH_NUM_FRAGS_KV(min(max_num_frags_kv_smem, max_num_frags_kv_reg), NUM_FRAGS_KV, {\n if constexpr (is_invalid_configuration<POS_ENCODING_MODE, DTypeKV, DTypeQKAccum>(\n NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV, NUM_WARPS_Q, NUM_WARPS_KV)) {\n // Invalid configuration, skip\n std::ostringstream err_msg;\n err_msg << \"FlashInfer Internal Error: Invalid configuration : NUM_FRAGS_Q=\" << NUM_FRAGS_Q\n << \" NUM_FRAGS_D=\" << NUM_FRAGS_D << \" NUM_FRAGS_KV=\" << NUM_FRAGS_KV\n << \" NUM_WARPS_Q=\" << NUM_WARPS_Q << \" NUM_WARPS_KV=\" << NUM_WARPS_KV\n << \" please create an issue (https://github.com/flashinfer-ai/flashinfer/issues)\"\n \" and report the issue to the developers.\";\n throw std::invalid_argument(err_msg.str());\n } else {\n // TODO(Zihao): fix the following computation\n uint32_t smem_size = (NUM_FRAGS_Q * NUM_WARPS_Q * sizeof(DTypeQ) +\n NUM_FRAGS_KV * NUM_WARPS_KV * 2 * sizeof(DTypeQ)) *\n 16 * HEAD_DIM;\n auto kernel =\n BatchPrefillWithRaggedKVCacheKernel<MASK_MODE, POS_ENCODING_MODE, NUM_FRAGS_Q,\n NUM_FRAGS_D, NUM_FRAGS_KV, NUM_WARPS_Q, NUM_WARPS_KV,\n DTypeQKAccum, AttentionVariant>;\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n if (tmp_v == nullptr) {\n // do not partition kv\n params.partition_kv = false;\n void* args[] = {(void*)&group_size_fastdiv, (void*)¶ms};\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n } else {\n // partition kv\n params.partition_kv = true;\n auto o = params.o;\n auto lse = params.lse;\n params.o = tmp_v;\n params.lse = tmp_s;\n void* args[] = {(void*)&group_size_fastdiv, (void*)¶ms};\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n if constexpr (AttentionVariant::use_softmax) {\n FLASHINFER_CUDA_CALL(VariableLengthMergeStates(tmp_v, tmp_s, params.merge_indptr, o, lse,\n total_num_rows, num_qo_heads, HEAD_DIM,\n stream));\n } else {\n FLASHINFER_CUDA_CALL(VariableLengthAttentionSum(\n tmp_v, params.merge_indptr, o, total_num_rows, num_qo_heads, HEAD_DIM, stream));\n }\n }\n }\n });\n return cudaSuccess;\n}\n\ntemplate <uint32_t CTA_TILE_Q, uint32_t HEAD_DIM, PosEncodingMode POS_ENCODING_MODE,\n bool ALLOW_FP16_QK_REDUCTION, MaskMode MASK_MODE, typename AttentionVariant>\ncudaError_t BatchPrefillWithPagedKVCacheDispatched(typename AttentionVariant::ParamsT params,\n typename AttentionVariant::DTypeO* tmp_v,\n float* tmp_s, cudaStream_t stream) {\n using DTypeQ = typename AttentionVariant::DTypeQ;\n using DTypeKV = typename AttentionVariant::DTypeKV;\n const uint32_t padded_batch_size = params.padded_batch_size;\n const uint32_t num_qo_heads = params.num_qo_heads;\n const uint32_t num_kv_heads = params.paged_kv.num_heads;\n const uint_fastdiv group_size_fastdiv(num_qo_heads / num_kv_heads);\n const uint32_t total_num_rows = params.total_num_rows;\n constexpr uint32_t NUM_FRAGS_Q = get_num_frags_q(CTA_TILE_Q);\n constexpr uint32_t NUM_WARPS_Q = get_num_warps_q(CTA_TILE_Q);\n constexpr uint32_t NUM_WARPS_KV = get_num_warps_kv(CTA_TILE_Q);\n\n if (padded_batch_size == 0) {\n // No request, skip\n // this won't happen in CUDAGraph mode because we fixed the padded_batch_size\n return cudaSuccess;\n }\n\n dim3 nblks(padded_batch_size, 1, num_kv_heads);\n dim3 nthrs(32, NUM_WARPS_Q, NUM_WARPS_KV);\n\n constexpr uint32_t NUM_FRAGS_D = HEAD_DIM / 16;\n using DTypeQKAccum =\n typename std::conditional<ALLOW_FP16_QK_REDUCTION && std::is_same_v<DTypeQ, half>, half,\n float>::type;\n\n int dev_id = 0;\n FLASHINFER_CUDA_CALL(cudaGetDevice(&dev_id));\n int max_smem_per_sm = 0;\n FLASHINFER_CUDA_CALL(cudaDeviceGetAttribute(&max_smem_per_sm,\n cudaDevAttrMaxSharedMemoryPerMultiprocessor, dev_id));\n // we expect each sm execute two threadblocks\n // TODO(Zihao): fix the following computation\n const int num_ctas_per_sm = max_smem_per_sm > (16 * HEAD_DIM * sizeof(DTypeQ) * 16) ? 2 : 1;\n const int max_smem_per_threadblock = max_smem_per_sm / num_ctas_per_sm;\n\n const uint32_t max_num_frags_kv_reg =\n (HEAD_DIM >= 128 && NUM_FRAGS_Q == 2 && POS_ENCODING_MODE == PosEncodingMode::kRoPELlama &&\n !ALLOW_FP16_QK_REDUCTION)\n ? 2\n : (8 / NUM_FRAGS_Q);\n // TODO(Zihao): fix the following computation\n const uint32_t max_num_frags_kv_smem =\n (max_smem_per_threadblock / (16 * HEAD_DIM * sizeof(DTypeQ)) - NUM_FRAGS_Q * NUM_WARPS_Q) /\n (2 * NUM_WARPS_KV);\n\n DISPATCH_NUM_FRAGS_KV(min(max_num_frags_kv_smem, max_num_frags_kv_reg), NUM_FRAGS_KV, {\n if constexpr (is_invalid_configuration<POS_ENCODING_MODE, DTypeKV, DTypeQKAccum>(\n NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV, NUM_WARPS_Q, NUM_WARPS_KV)) {\n // Invalid configuration, skip\n std::ostringstream err_msg;\n err_msg << \"FlashInfer Internal Error: Invalid configuration : NUM_FRAGS_Q=\" << NUM_FRAGS_Q\n << \" NUM_FRAGS_D=\" << NUM_FRAGS_D << \" NUM_FRAGS_KV=\" << NUM_FRAGS_KV\n << \" NUM_WARPS_Q=\" << NUM_WARPS_Q << \" NUM_WARPS_KV=\" << NUM_WARPS_KV\n << \" please create an issue (https://github.com/flashinfer-ai/flashinfer/issues)\"\n \" and report the issue to the developers.\";\n throw std::invalid_argument(err_msg.str());\n } else {\n // TODO(Zihao): fix the following computation\n uint32_t smem_size = (NUM_FRAGS_Q * NUM_WARPS_Q * sizeof(DTypeQ) +\n NUM_FRAGS_KV * NUM_WARPS_KV * 2 * sizeof(DTypeQ)) *\n 16 * HEAD_DIM;\n auto kernel =\n BatchPrefillWithPagedKVCacheKernel<MASK_MODE, POS_ENCODING_MODE, NUM_FRAGS_Q, NUM_FRAGS_D,\n NUM_FRAGS_KV, NUM_WARPS_Q, NUM_WARPS_KV, DTypeQKAccum,\n AttentionVariant>;\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n if (tmp_v == nullptr) {\n // do not partition kv\n params.partition_kv = false;\n void* args[] = {(void*)&group_size_fastdiv, (void*)¶ms};\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n } else {\n params.partition_kv = true;\n auto o = params.o;\n auto lse = params.lse;\n params.o = tmp_v;\n params.lse = tmp_s;\n void* args[] = {(void*)&group_size_fastdiv, (void*)¶ms};\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n if constexpr (AttentionVariant::use_softmax) {\n FLASHINFER_CUDA_CALL(VariableLengthMergeStates(tmp_v, tmp_s, params.merge_indptr, o, lse,\n total_num_rows, num_qo_heads, HEAD_DIM,\n stream));\n } else {\n FLASHINFER_CUDA_CALL(VariableLengthAttentionSum(\n tmp_v, params.merge_indptr, o, total_num_rows, num_qo_heads, HEAD_DIM, stream));\n }\n }\n }\n });\n return cudaSuccess;\n}\n\n} // namespace flashinfer\n\n#endif // FLASHINFER_PREFILL_CUH_\n"},"after_code":{"kind":"string","value":"/*\n * Copyright (c) 2023 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_PREFILL_CUH_\n#define FLASHINFER_PREFILL_CUH_\n#include <cooperative_groups.h>\n#include <cuda_bf16.h>\n#include <cuda_fp16.h>\n#include <cuda_fp8.h>\n#include <cuda_runtime.h>\n\n#include \"../cp_async.cuh\"\n#include \"../fastdiv.cuh\"\n#include \"../frag_layout_swizzle.cuh\"\n#include \"../layout.cuh\"\n#include \"../math.cuh\"\n#include \"../mma.cuh\"\n#include \"../page.cuh\"\n#include \"../permuted_smem.cuh\"\n#include \"../pos_enc.cuh\"\n#include \"../utils.cuh\"\n#include \"cascade.cuh\"\n#include \"mask.cuh\"\n#include \"variants.cuh\"\n\nnamespace flashinfer {\n\nnamespace cg = cooperative_groups;\nusing cp_async::SharedMemFillMode;\nusing mma::MMAMode;\n\nconstexpr uint32_t WARP_SIZE = 32;\n\nconstexpr uint32_t get_num_warps_q(const uint32_t cta_tile_q) {\n if (cta_tile_q > 16) {\n return 4;\n } else {\n return 1;\n }\n}\n\nconstexpr uint32_t get_num_warps_kv(const uint32_t cta_tile_kv) {\n return 4 / get_num_warps_q(cta_tile_kv);\n}\n\nconstexpr uint32_t get_num_frags_q(const uint32_t cta_tile_q) {\n if (cta_tile_q > 64) {\n return 2;\n } else {\n return 1;\n }\n}\n\nnamespace {\n\ntemplate <PosEncodingMode POS_ENCODING_MODE, typename DTypeKV, typename DTypeQKAccum>\nconstexpr bool is_invalid_configuration(uint32_t NUM_FRAGS_Q, uint32_t NUM_FRAGS_D,\n uint32_t NUM_FRAGS_KV, uint32_t NUM_WARPS_Q,\n uint32_t NUM_WARPS_KV) {\n return ((NUM_FRAGS_D < 4) || (NUM_FRAGS_D == 4 && NUM_FRAGS_KV % 2 == 1) ||\n (NUM_FRAGS_D > 4 && NUM_FRAGS_D % (2 * NUM_WARPS_Q) != 0) ||\n (NUM_FRAGS_Q * (8 * NUM_FRAGS_D + 2 * sizeof(DTypeQKAccum) * NUM_FRAGS_KV) >= 256) ||\n (sizeof(DTypeKV) == 1 && NUM_FRAGS_KV * 2 % NUM_WARPS_Q != 0) ||\n (sizeof(DTypeKV) == 1 && POS_ENCODING_MODE == PosEncodingMode::kRoPELlama));\n}\n\ntemplate <uint32_t NUM_WARPS_Q, uint32_t NUM_WARPS_KV>\n__device__ __forceinline__ uint32_t get_warp_idx_q() {\n if constexpr (NUM_WARPS_Q == 1) {\n return 0;\n } else {\n return threadIdx.y;\n }\n}\n\ntemplate <uint32_t NUM_WARPS_Q, uint32_t NUM_WARPS_KV>\n__device__ __forceinline__ uint32_t get_warp_idx_kv() {\n if constexpr (NUM_WARPS_KV == 1) {\n return 0;\n } else {\n return threadIdx.z;\n }\n}\n\ntemplate <uint32_t NUM_WARPS_Q, uint32_t NUM_WARPS_KV>\n__device__ __forceinline__ uint32_t get_warp_idx() {\n return get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>() * NUM_WARPS_Q +\n get_warp_idx_q<NUM_WARPS_Q, NUM_WARPS_KV>();\n}\n\n/*!\n * \\brief Apply Llama style rotary embedding to two 16x16 fragments.\n * \\tparam T The data type of the input fragments.\n * \\param x_first_half First fragment x[offset:offset+16, j*16:(j+1)*16]\n * \\param x_second_half Second fragment x[offset:offset*16, j*16+d/2:(j+1)*16+d/2]\n * \\param rope_freq Rope frequency\n * \\param offset The offset of the first row in both fragments.\n * \\note The sin/cos computation is slow, especially for A100 GPUs which has low\n * non tensor-ops flops, will optimize in the future.\n */\ntemplate <typename T>\n__device__ __forceinline__ void k_frag_apply_llama_rope(T* x_first_half, T* x_second_half,\n const float* rope_freq,\n const uint32_t kv_offset) {\n static_assert(sizeof(T) == 2);\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n float cos, sin, tmp;\n // 0 1 | 2 3\n // ---------\n // 4 5 | 6 7\n uint32_t i = reg_id / 4, j = (reg_id % 4) / 2;\n __sincosf(float(kv_offset + 8 * i) * rope_freq[2 * j + reg_id % 2], &sin, &cos);\n tmp = x_first_half[reg_id];\n x_first_half[reg_id] = (tmp * cos - (float)x_second_half[reg_id] * sin);\n x_second_half[reg_id] = ((float)x_second_half[reg_id] * cos + tmp * sin);\n }\n}\n\ntemplate <typename T>\n__device__ __forceinline__ void q_frag_apply_llama_rope(T* x_first_half, T* x_second_half,\n const float* rope_freq,\n const uint32_t qo_packed_offset,\n const uint_fastdiv group_size) {\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n float cos, sin, tmp;\n // 0 1 | 4 5\n // ---------\n // 2 3 | 6 7\n uint32_t i = ((reg_id % 4) / 2), j = (reg_id / 4);\n __sincosf(float((qo_packed_offset + 8 * i) / group_size) * rope_freq[2 * j + reg_id % 2], &sin,\n &cos);\n tmp = x_first_half[reg_id];\n x_first_half[reg_id] = (tmp * cos - (float)x_second_half[reg_id] * sin);\n x_second_half[reg_id] = ((float)x_second_half[reg_id] * cos + tmp * sin);\n }\n}\n\ntemplate <typename T, typename IdType>\n__device__ __forceinline__ void q_frag_apply_llama_rope_with_pos(T* x_first_half, T* x_second_half,\n const float* rope_freq,\n const uint32_t qo_packed_offset,\n const uint_fastdiv group_size,\n const IdType* q_offset) {\n float pos[2] = {static_cast<float>(q_offset[qo_packed_offset / group_size]),\n static_cast<float>(q_offset[(qo_packed_offset + 8) / group_size])};\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n float cos, sin, tmp;\n // 0 1 | 4 5\n // ---------\n // 2 3 | 6 7\n uint32_t i = ((reg_id % 4) / 2), j = (reg_id / 4);\n __sincosf(pos[i] * rope_freq[2 * j + reg_id % 2], &sin, &cos);\n tmp = x_first_half[reg_id];\n x_first_half[reg_id] = (tmp * cos - (float)x_second_half[reg_id] * sin);\n x_second_half[reg_id] = ((float)x_second_half[reg_id] * cos + tmp * sin);\n }\n}\n\n/*!\n * \\brief Produce k/v fragments from global memory to shared memory.\n * \\tparam fill_mode The fill mode of the shared memory.\n * \\tparam NUM_FRAGS_D The number of fragments in y dimension.\n * \\tparam NUM_FRAGS_KV The number of fragments in z dimension.\n * \\tparam num_warps The number of warps in the threadblock.\n * \\tparam T The data type of the input tensor.\n * \\param smem The shared memory to store kv fragments.\n * \\param gptr The global memory pointer.\n * \\param kv_idx_base The base kv index.\n * \\param kv_len The length of kv tensor.\n */\ntemplate <SharedMemFillMode fill_mode, uint32_t NUM_WARPS_Q, uint32_t NUM_WARPS_KV,\n uint32_t NUM_FRAGS_D, uint32_t NUM_FRAGS_KV, SwizzleMode swizzle_mode, typename T>\n__device__ __forceinline__ void produce_kv(smem_t<swizzle_mode> smem, uint32_t* smem_offset,\n T** gptr, const uint32_t kv_stride_n,\n const uint32_t kv_idx_base, const uint32_t kv_len) {\n // NOTE(Zihao): for fp8, this function doesn't work for head_dim = 64 at the moment\n constexpr uint32_t head_dim = NUM_FRAGS_D * 16;\n constexpr uint32_t num_warps = NUM_WARPS_Q * NUM_WARPS_KV;\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<T>();\n const uint32_t warp_idx = get_warp_idx<NUM_WARPS_Q, NUM_WARPS_KV>(), lane_idx = threadIdx.x;\n\n if constexpr (swizzle_mode == SwizzleMode::k128B) {\n uint32_t kv_idx = kv_idx_base + warp_idx * 4 + lane_idx / 8;\n // NOTE(Zihao): NUM_FRAGS_KV * 4 / NUM_WARPS_Q = NUM_WARPS_KV * NUM_FRAGS_KV * 4 / num_warps\n static_assert(NUM_FRAGS_KV * 4 % NUM_WARPS_Q == 0);\n#pragma unroll\n for (uint32_t i = 0; i < NUM_FRAGS_KV * 4 / NUM_WARPS_Q; ++i) {\n#pragma unroll\n for (uint32_t j = 0; j < NUM_FRAGS_D / (8 / sizeof(T)); ++j) {\n smem.load_128b_async<fill_mode>(*smem_offset, *gptr, kv_idx < kv_len);\n *smem_offset = smem.template advance_offset_by_column<8>(*smem_offset, j);\n *gptr += 8 * num_elems_per_128b<T>();\n }\n kv_idx += num_warps * 4;\n *smem_offset =\n smem.template advance_offset_by_row<num_warps * 4, channel_size_128b_kv>(*smem_offset) -\n sizeof(T) * NUM_FRAGS_D;\n *gptr += num_warps * 4 * kv_stride_n - sizeof(T) * NUM_FRAGS_D * num_elems_per_128b<T>();\n }\n *smem_offset -= NUM_WARPS_KV * NUM_FRAGS_KV * 16 * channel_size_128b_kv;\n } else {\n uint32_t kv_idx = kv_idx_base + warp_idx * 8 + lane_idx / 4;\n // NOTE(Zihao): NUM_FRAGS_KV * 2 / NUM_WARPS_Q = NUM_WARPS_KV * NUM_FRAGS_KV * 2 / num_warps\n static_assert(NUM_FRAGS_KV * 2 % NUM_WARPS_Q == 0);\n#pragma unroll\n for (uint32_t i = 0; i < NUM_FRAGS_KV * 2 / NUM_WARPS_Q; ++i) {\n smem.load_128b_async<fill_mode>(*smem_offset, *gptr, kv_idx < kv_len);\n *smem_offset =\n smem.template advance_offset_by_row<num_warps * 8, channel_size_128b_kv>(*smem_offset);\n kv_idx += num_warps * 8;\n *gptr += num_warps * 8 * kv_stride_n;\n }\n *smem_offset -= NUM_WARPS_KV * NUM_FRAGS_KV * 16 * channel_size_128b_kv;\n }\n}\n\ntemplate <bool produce_v, uint32_t NUM_WARPS_Q, uint32_t NUM_WARPS_KV, uint32_t NUM_FRAGS_D,\n uint32_t NUM_FRAGS_KV, SwizzleMode swizzle_mode, typename DType, typename IdType>\n__device__ __forceinline__ void page_produce_kv(smem_t<swizzle_mode> smem, uint32_t* smem_offset,\n const paged_kv_t<DType, IdType>& paged_kv,\n const uint32_t kv_idx_base, const size_t* kv_offset,\n const uint32_t kv_len) {\n // NOTE(Zihao): for fp8, this function doesn't work for head_dim = 64 at the moment\n constexpr SharedMemFillMode fill_mode =\n produce_v ? SharedMemFillMode::kFillZero : SharedMemFillMode::kNoFill;\n constexpr uint32_t head_dim = NUM_FRAGS_D * 16;\n constexpr uint32_t num_warps = NUM_WARPS_Q * NUM_WARPS_KV;\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<DType>();\n const uint32_t warp_idx = get_warp_idx<NUM_WARPS_Q, NUM_WARPS_KV>(), lane_idx = threadIdx.x;\n if constexpr (swizzle_mode == SwizzleMode::k128B) {\n uint32_t kv_idx = kv_idx_base + warp_idx * 4 + lane_idx / 8;\n // NOTE(Zihao): NUM_FRAGS_KV * 4 / NUM_WARPS_Q = NUM_WARPS_KV * NUM_FRAGS_KV * 4 / num_warps\n static_assert(NUM_FRAGS_KV * 4 % NUM_WARPS_Q == 0);\n#pragma unroll\n for (uint32_t i = 0; i < NUM_FRAGS_KV * 4 / NUM_WARPS_Q; ++i) {\n DType* gptr = produce_v ? paged_kv.v_data + kv_offset[i] : paged_kv.k_data + kv_offset[i];\n#pragma unroll\n for (uint32_t j = 0; j < NUM_FRAGS_D / (8 / sizeof(DType)); ++j) {\n smem.load_128b_async<fill_mode>(*smem_offset, gptr, kv_idx < kv_len);\n *smem_offset = smem.template advance_offset_by_column<8>(*smem_offset, j);\n gptr += 8 * num_elems_per_128b<DType>();\n }\n kv_idx += num_warps * 4;\n *smem_offset =\n smem.template advance_offset_by_row<num_warps * 4, channel_size_128b_kv>(*smem_offset) -\n sizeof(DType) * NUM_FRAGS_D;\n }\n *smem_offset -= NUM_WARPS_KV * NUM_FRAGS_KV * 16 * channel_size_128b_kv;\n } else {\n uint32_t kv_idx = kv_idx_base + warp_idx * 8 + lane_idx / 4;\n // NOTE(Zihao): NUM_FRAGS_KV * 2 / NUM_WARPS_Q = NUM_WARPS_KV * NUM_FRAGS_KV * 2 / num_warps\n static_assert(NUM_FRAGS_KV * 2 % NUM_WARPS_Q == 0);\n#pragma unroll\n for (uint32_t i = 0; i < NUM_FRAGS_KV * 2 / NUM_WARPS_Q; ++i) {\n DType* gptr = produce_v ? paged_kv.v_data + kv_offset[i] : paged_kv.k_data + kv_offset[i];\n smem.load_128b_async<fill_mode>(*smem_offset, gptr, kv_idx < kv_len);\n kv_idx += num_warps * 8;\n *smem_offset =\n smem.template advance_offset_by_row<num_warps * 8, channel_size_128b_kv>(*smem_offset);\n }\n *smem_offset -= NUM_WARPS_KV * NUM_FRAGS_KV * 16 * channel_size_128b_kv;\n }\n}\n\ntemplate <uint32_t NUM_FRAGS_D>\n__device__ __forceinline__ void init_rope_freq(float (*rope_freq)[4],\n const float log2_rope_rcp_scale,\n const float log2_rope_rcp_theta) {\n constexpr uint32_t head_dim = NUM_FRAGS_D * 16;\n const uint32_t lane_idx = threadIdx.x;\n#pragma unroll\n for (uint32_t fd = 0; fd < NUM_FRAGS_D / 2; ++fd) {\n#pragma unroll\n for (uint32_t j = 0; j < 4; ++j) {\n rope_freq[fd][j] = math::ptx_exp2(\n log2_rope_rcp_scale +\n log2_rope_rcp_theta *\n float(2 * ((fd * 16 + (j / 2) * 8 + (lane_idx % 4) * 2 + (j % 2)) % (head_dim / 2))) /\n float(head_dim));\n }\n }\n}\n\ntemplate <uint32_t NUM_FRAGS_Q, uint32_t NUM_FRAGS_D, typename DTypeQKAccum,\n typename AttentionVariant>\n__device__ __forceinline__ void init_states(AttentionVariant variant,\n float (*o_frag)[NUM_FRAGS_D][8], DTypeQKAccum (*m)[2],\n float (*d)[2]) {\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t fd = 0; fd < NUM_FRAGS_D; ++fd) {\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n o_frag[fq][fd][reg_id] = 0.f;\n }\n }\n }\n\n if constexpr (variant.use_softmax) {\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n m[fq][j] = DTypeQKAccum(-math::inf);\n d[fq][j] = 1.f;\n }\n }\n }\n}\n\ntemplate <uint32_t NUM_WARPS_Q, uint32_t NUM_WARPS_KV, uint32_t NUM_FRAGS_Q, uint32_t NUM_FRAGS_D,\n SwizzleMode swizzle_mode, typename DTypeQ>\n__device__ __forceinline__ void load_q_global_smem(uint32_t packed_offset,\n const uint32_t qo_upper_bound,\n DTypeQ* q_ptr_base, const uint32_t q_stride_n,\n const uint32_t q_stride_h,\n const uint_fastdiv group_size,\n smem_t<swizzle_mode>* q_smem) {\n constexpr uint32_t head_dim = NUM_FRAGS_D * 16;\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n const uint32_t lane_idx = threadIdx.x, warp_idx_x = get_warp_idx_q<NUM_WARPS_Q, NUM_WARPS_KV>();\n\n if (get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>() == 0) {\n uint32_t q_smem_offset_w = q_smem->get_permuted_offset<channel_size_128b_q>(\n warp_idx_x * NUM_FRAGS_Q * 16 + lane_idx / 8, lane_idx % 8);\n\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t j = 0; j < 4; ++j) {\n uint32_t q, r;\n group_size.divmod(packed_offset + lane_idx / 8 + fq * 16 + j * 4, q, r);\n const uint32_t q_idx = q;\n DTypeQ* q_ptr = q_ptr_base + q * q_stride_n + r * q_stride_h;\n#pragma unroll\n for (uint32_t fdo = 0; fdo < NUM_FRAGS_D / 4; ++fdo) {\n // load q fragment from gmem to smem\n q_smem->load_128b_async<SharedMemFillMode::kNoFill>(q_smem_offset_w, q_ptr,\n q_idx < qo_upper_bound);\n q_smem_offset_w = q_smem->template advance_offset_by_column<8>(q_smem_offset_w, fdo);\n q_ptr += 8 * num_elems_per_128b<DTypeQ>();\n }\n q_smem_offset_w =\n q_smem->template advance_offset_by_row<4, channel_size_128b_q>(q_smem_offset_w) -\n 2 * NUM_FRAGS_D;\n }\n }\n }\n}\n\ntemplate <uint32_t NUM_WARPS_Q, uint32_t NUM_WARPS_KV, uint32_t NUM_FRAGS_Q, uint32_t NUM_FRAGS_D,\n SwizzleMode swizzle_mode, typename DTypeQ>\n__device__ __forceinline__ void q_smem_inplace_apply_rotary(\n const uint32_t q_packed_idx, const uint32_t qo_len, const uint32_t kv_len,\n const uint_fastdiv group_size, smem_t<swizzle_mode>* q_smem, uint32_t* q_smem_offset_r,\n float (*rope_freq)[4]) {\n if (get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>() == 0) {\n constexpr uint32_t head_dim = NUM_FRAGS_D * 16;\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n const uint32_t lane_idx = threadIdx.x;\n uint32_t q_frag_local[2][4];\n static_assert(NUM_FRAGS_D % 4 == 0, \"NUM_FRAGS_D must be a multiple of 4\");\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n uint32_t q_smem_offset_r_first_half = *q_smem_offset_r;\n#pragma unroll\n for (uint32_t fdi = 0; fdi < NUM_FRAGS_D / 2; ++fdi) {\n q_smem->ldmatrix_m8n8x4(q_smem_offset_r_first_half, q_frag_local[0]);\n uint32_t q_smem_offset_r_last_half =\n q_smem->template advance_offset_by_column<NUM_FRAGS_D>(q_smem_offset_r_first_half, 0);\n q_smem->ldmatrix_m8n8x4(q_smem_offset_r_last_half, q_frag_local[1]);\n q_frag_apply_llama_rope<DTypeQ>(\n (DTypeQ*)q_frag_local[0], (DTypeQ*)q_frag_local[1], rope_freq[fdi],\n q_packed_idx + kv_len * group_size - qo_len * group_size + fq * 16 + lane_idx / 4,\n group_size);\n q_smem->stmatrix_m8n8x4(q_smem_offset_r_last_half, q_frag_local[1]);\n q_smem->stmatrix_m8n8x4(q_smem_offset_r_first_half, q_frag_local[0]);\n q_smem_offset_r_first_half =\n q_smem->template advance_offset_by_column<2>(q_smem_offset_r_first_half, fdi);\n }\n *q_smem_offset_r += 16 * channel_size_128b_q;\n }\n *q_smem_offset_r -= NUM_FRAGS_Q * 16 * channel_size_128b_q;\n }\n}\n\ntemplate <uint32_t NUM_WARPS_Q, uint32_t NUM_WARPS_KV, uint32_t NUM_FRAGS_Q, uint32_t NUM_FRAGS_D,\n SwizzleMode swizzle_mode, typename DTypeQ, typename IdType>\n__device__ __forceinline__ void q_smem_inplace_apply_rotary_with_pos(\n const uint32_t q_packed_idx_base, const IdType* q_offset, smem_t<swizzle_mode>* q_smem,\n const uint_fastdiv group_size, uint32_t* q_smem_offset_r, float (*rope_freq)[4]) {\n if (get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>() == 0) {\n constexpr uint32_t head_dim = NUM_FRAGS_D * 16;\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n const uint32_t lane_idx = threadIdx.x;\n uint32_t q_frag_local[2][4];\n static_assert(NUM_FRAGS_D % 4 == 0, \"NUM_FRAGS_D must be a multiple of 4\");\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n uint32_t q_smem_offset_r_first_half = *q_smem_offset_r;\n#pragma unroll\n for (uint32_t fdi = 0; fdi < NUM_FRAGS_D / 2; ++fdi) {\n q_smem->ldmatrix_m8n8x4(q_smem_offset_r_first_half, q_frag_local[0]);\n uint32_t q_smem_offset_r_last_half =\n q_smem->template advance_offset_by_column<NUM_FRAGS_D>(q_smem_offset_r_first_half, 0);\n q_smem->ldmatrix_m8n8x4(q_smem_offset_r_last_half, q_frag_local[1]);\n q_frag_apply_llama_rope_with_pos<DTypeQ>(\n (DTypeQ*)q_frag_local[0], (DTypeQ*)q_frag_local[1], rope_freq[fdi],\n q_packed_idx_base + fq * 16 + lane_idx / 4, group_size, q_offset);\n q_smem->stmatrix_m8n8x4(q_smem_offset_r_last_half, q_frag_local[1]);\n q_smem->stmatrix_m8n8x4(q_smem_offset_r_first_half, q_frag_local[0]);\n q_smem_offset_r_first_half =\n q_smem->template advance_offset_by_column<2>(q_smem_offset_r_first_half, fdi);\n }\n *q_smem_offset_r += 16 * channel_size_128b_q;\n }\n *q_smem_offset_r -= NUM_FRAGS_Q * 16 * channel_size_128b_q;\n }\n}\n\ntemplate <uint32_t NUM_WARPS_Q, uint32_t NUM_WARPS_KV, uint32_t NUM_FRAGS_Q, uint32_t NUM_FRAGS_D,\n SwizzleMode swizzle_mode, typename AttentionVariant>\n__device__ __forceinline__ void q_smem_inplace_transform(\n const typename AttentionVariant::ParamsT& params, AttentionVariant variant,\n smem_t<swizzle_mode>* q_smem) {\n using DTypeQ = typename AttentionVariant::DTypeQ;\n const uint32_t warp_idx = get_warp_idx<NUM_WARPS_Q, NUM_WARPS_KV>(), lane_idx = threadIdx.x;\n constexpr uint32_t head_dim = NUM_FRAGS_D * 16;\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n constexpr uint32_t num_warps = NUM_WARPS_Q * NUM_WARPS_KV;\n#pragma unroll\n for (uint32_t i = 0; i < NUM_FRAGS_Q * head_dim / (NUM_WARPS_KV * 16); ++i) {\n vec_t<DTypeQ, 8> tmp;\n tmp.load((DTypeQ*)(q_smem->base) + (i * num_warps + warp_idx) * 256 + lane_idx * 8);\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n tmp[reg_id] = variant.QueryTransform(params, tmp[reg_id]);\n }\n tmp.store((DTypeQ*)(q_smem->base) + (i * num_warps + warp_idx) * 256 + lane_idx * 8);\n }\n}\n\ntemplate <uint32_t NUM_WARPS_Q, uint32_t NUM_WARPS_KV, uint32_t NUM_FRAGS_D, uint32_t NUM_FRAGS_KV,\n SwizzleMode swizzle_mode, typename DTypeKV>\n__device__ __forceinline__ void k_smem_inplace_apply_rotary(const uint32_t kv_idx_base,\n smem_t<swizzle_mode>* k_smem,\n uint32_t* k_smem_offset_r,\n float (*rope_freq)[4]) {\n static_assert(sizeof(DTypeKV) == 2);\n constexpr uint32_t head_dim = NUM_FRAGS_D * 16;\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<DTypeKV>();\n uint32_t k_frag_local[2][4];\n const uint32_t lane_idx = threadIdx.x;\n if constexpr (NUM_FRAGS_D == 4 && NUM_WARPS_Q == 4) {\n static_assert(NUM_WARPS_KV == 1);\n const uint32_t warp_idx = get_warp_idx_q<NUM_WARPS_Q, NUM_WARPS_KV>();\n // horizontal-axis: y\n // horizontal-axis: y\n // vertical-axis: z\n // | 1-16 | 16-32 | 32-48 | 48-64 |\n // | 1-16 | warp_idx=0 | warp_idx=1 | warp_idx=0 | warp_idx=1 |\n // | 16-32 | warp_idx=2 | warp_idx=3 | warp_idx=2 | warp_idx=3 |\n static_assert(NUM_FRAGS_KV % 2 == 0,\n \"when NUM_FRAGS_D == 4, NUM_FRAGS_KV must be a multiple of 2\");\n uint32_t kv_idx = kv_idx_base + (warp_idx / 2) * 16 + lane_idx / 4;\n *k_smem_offset_r =\n (*k_smem_offset_r ^ (0x2 * (warp_idx % 2))) + (warp_idx / 2) * 16 * channel_size_128b_kv;\n#pragma unroll\n for (uint32_t i = 0; i < NUM_FRAGS_KV / 2; ++i) {\n // uint32_t fkv = warp_idx / 2 + i * 2;\n uint32_t k_smem_offset_r_first_half = *k_smem_offset_r;\n uint32_t fdi = (warp_idx % 2);\n k_smem->ldmatrix_m8n8x4(k_smem_offset_r_first_half, k_frag_local[0]);\n uint32_t k_smem_offset_r_last_half =\n k_smem->template advance_offset_by_column<4>(k_smem_offset_r_first_half, 0);\n k_smem->ldmatrix_m8n8x4(k_smem_offset_r_last_half, k_frag_local[1]);\n k_frag_apply_llama_rope<DTypeKV>((DTypeKV*)k_frag_local[0], (DTypeKV*)k_frag_local[1],\n rope_freq[fdi], kv_idx);\n k_smem->stmatrix_m8n8x4(k_smem_offset_r_last_half, k_frag_local[1]);\n k_smem->stmatrix_m8n8x4(k_smem_offset_r_first_half, k_frag_local[0]);\n *k_smem_offset_r += 32 * channel_size_128b_kv;\n kv_idx += 32;\n }\n *k_smem_offset_r = (*k_smem_offset_r ^ (0x2 * (warp_idx % 2))) -\n ((warp_idx / 2) + NUM_FRAGS_KV) * 16 * channel_size_128b_kv;\n } else {\n const uint32_t warp_idx_x = get_warp_idx_q<NUM_WARPS_Q, NUM_WARPS_KV>(),\n warp_idx_z = get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>();\n static_assert(NUM_FRAGS_D % (2 * NUM_WARPS_Q) == 0);\n // horizontal axis: y\n // vertical axis: z\n // | (warp_idx_z, warp_idx_x) | 1-16 | 16-32 | 32-48 | 48-64 | ...\n // | 1-16*NUM_FRAGS_KV | (0, 0) | (0, 1) | (0, 2) | (0, 3) | ...\n // | 16*NUM_FRAGS_KV-32*NUM_FRAGS_KV | (1, 0) | (1, 1) | (1, 2) | (1, 3) | ...\n // ...\n uint32_t kv_idx = kv_idx_base + (warp_idx_z * NUM_FRAGS_KV * 16) + lane_idx / 4;\n *k_smem_offset_r = *k_smem_offset_r ^ (0x2 * warp_idx_x);\n#pragma unroll\n for (uint32_t i = 0; i < NUM_FRAGS_KV; ++i) {\n uint32_t k_smem_offset_r_first_half = *k_smem_offset_r;\n#pragma unroll\n for (uint32_t j = 0; j < NUM_FRAGS_D / (2 * NUM_WARPS_Q); ++j) {\n uint32_t fdi = warp_idx_x + j * NUM_WARPS_Q;\n k_smem->ldmatrix_m8n8x4(k_smem_offset_r_first_half, k_frag_local[0]);\n uint32_t k_smem_offset_r_last_half =\n k_smem->template advance_offset_by_column<NUM_FRAGS_D>(k_smem_offset_r_first_half, 0);\n k_smem->ldmatrix_m8n8x4(k_smem_offset_r_last_half, k_frag_local[1]);\n k_frag_apply_llama_rope<DTypeKV>((DTypeKV*)k_frag_local[0], (DTypeKV*)k_frag_local[1],\n rope_freq[fdi], kv_idx);\n k_smem->stmatrix_m8n8x4(k_smem_offset_r_last_half, k_frag_local[1]);\n k_smem->stmatrix_m8n8x4(k_smem_offset_r_first_half, k_frag_local[0]);\n k_smem_offset_r_first_half = k_smem->template advance_offset_by_column<2 * NUM_WARPS_Q>(\n k_smem_offset_r_first_half, fdi);\n }\n *k_smem_offset_r += 16 * channel_size_128b_kv;\n kv_idx += 16;\n }\n *k_smem_offset_r =\n (*k_smem_offset_r ^ (0x2 * warp_idx_x)) - NUM_FRAGS_KV * 16 * channel_size_128b_kv;\n }\n}\n\ntemplate <uint32_t NUM_FRAGS_Q, uint32_t NUM_FRAGS_D, uint32_t NUM_FRAGS_KV,\n SwizzleMode swizzle_mode_q, SwizzleMode swizzle_mode_kv, typename DTypeQ,\n typename DTypeKV, typename DTypeQKAccum>\n__device__ __forceinline__ void compute_qk(smem_t<swizzle_mode_q>* q_smem,\n uint32_t* q_smem_offset_r,\n smem_t<swizzle_mode_kv>* k_smem,\n uint32_t* k_smem_offset_r,\n DTypeQKAccum (*s_frag)[NUM_FRAGS_KV][8]) {\n constexpr uint32_t head_dim = NUM_FRAGS_D * 16;\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<DTypeKV>();\n uint32_t a_frag[NUM_FRAGS_Q][4], b_frag[4];\n // compute q*k^T\n#pragma unroll\n for (uint32_t fd = 0; fd < NUM_FRAGS_D; ++fd) {\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n q_smem->ldmatrix_m8n8x4(*q_smem_offset_r, a_frag[fq]);\n *q_smem_offset_r =\n q_smem->template advance_offset_by_row<16, channel_size_128b_q>(*q_smem_offset_r);\n }\n\n *q_smem_offset_r = q_smem->template advance_offset_by_column<2>(*q_smem_offset_r, fd) -\n NUM_FRAGS_Q * 16 * channel_size_128b_q;\n\n#pragma unroll\n for (uint32_t fkv = 0; fkv < NUM_FRAGS_KV; ++fkv) {\n if constexpr (sizeof(DTypeKV) == 1) {\n uint32_t b_frag_f8[2];\n if (fd % 2 == 0) {\n k_smem->ldmatrix_m8n8x4_left_half(*k_smem_offset_r, b_frag_f8);\n } else {\n k_smem->ldmatrix_m8n8x4_right_half(*k_smem_offset_r, b_frag_f8);\n }\n b_frag_f8[0] = frag_layout_swizzle_16b_to_8b(b_frag_f8[0]);\n b_frag_f8[1] = frag_layout_swizzle_16b_to_8b(b_frag_f8[1]);\n vec_cast<DTypeQ, DTypeKV>::cast<8>((DTypeQ*)b_frag, (DTypeKV*)b_frag_f8);\n } else {\n k_smem->ldmatrix_m8n8x4(*k_smem_offset_r, b_frag);\n }\n *k_smem_offset_r =\n k_smem->template advance_offset_by_row<16, channel_size_128b_kv>(*k_smem_offset_r);\n\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n if constexpr (std::is_same_v<DTypeQKAccum, float>) {\n if (fd == 0) {\n mma::mma_sync_m16n16k16_row_col_f16f16f32<DTypeQ, MMAMode::kInit>(s_frag[fq][fkv],\n a_frag[fq], b_frag);\n } else {\n mma::mma_sync_m16n16k16_row_col_f16f16f32<DTypeQ>(s_frag[fq][fkv], a_frag[fq], b_frag);\n }\n } else if (std::is_same_v<DTypeQKAccum, half>) {\n if (fd == 0) {\n mma::mma_sync_m16n16k16_row_col_f16f16f16<MMAMode::kInit>((uint32_t*)s_frag[fq][fkv],\n a_frag[fq], b_frag);\n } else {\n mma::mma_sync_m16n16k16_row_col_f16f16f16((uint32_t*)s_frag[fq][fkv], a_frag[fq],\n b_frag);\n }\n }\n }\n }\n if constexpr (sizeof(DTypeKV) == 1) {\n if (fd % 2 == 1) {\n *k_smem_offset_r = k_smem->template advance_offset_by_column<2>(*k_smem_offset_r, fd / 2);\n }\n *k_smem_offset_r -= NUM_FRAGS_KV * 16 * channel_size_128b_kv;\n } else {\n *k_smem_offset_r = k_smem->template advance_offset_by_column<2>(*k_smem_offset_r, fd) -\n NUM_FRAGS_KV * 16 * channel_size_128b_kv;\n }\n }\n *q_smem_offset_r -= NUM_FRAGS_D * 2;\n *k_smem_offset_r -= NUM_FRAGS_D * sizeof(DTypeKV);\n}\n\ntemplate <uint32_t NUM_FRAGS_Q, uint32_t NUM_FRAGS_D, uint32_t NUM_FRAGS_KV,\n typename AttentionVariant, typename DTypeQKAccum>\n__device__ __forceinline__ void logits_transform(const typename AttentionVariant::ParamsT& params,\n AttentionVariant variant, const uint32_t batch_idx,\n const uint32_t qo_packed_idx_base,\n const uint32_t kv_idx_base, const uint32_t qo_len,\n const uint32_t kv_len,\n const uint_fastdiv group_size,\n DTypeQKAccum (*s_frag)[NUM_FRAGS_KV][8]) {\n const uint32_t lane_idx = threadIdx.x, kv_head_idx = blockIdx.z;\n uint32_t q[NUM_FRAGS_Q][2], r[NUM_FRAGS_Q][2];\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n group_size.divmod(qo_packed_idx_base + fq * 16 + lane_idx / 4 + 8 * j, q[fq][j], r[fq][j]);\n }\n }\n\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t fkv = 0; fkv < NUM_FRAGS_KV; ++fkv) {\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n const uint32_t q_idx = q[fq][(reg_id % 4) / 2], kv_idx = kv_idx_base + fkv * 16 +\n 2 * (lane_idx % 4) +\n 8 * (reg_id / 4) + reg_id % 2;\n const uint32_t qo_head_idx = kv_head_idx * group_size + r[fq][(reg_id % 4) / 2];\n s_frag[fq][fkv][reg_id] = variant.LogitsTransform(\n params, s_frag[fq][fkv][reg_id], batch_idx, q_idx, kv_idx, qo_head_idx, kv_head_idx);\n }\n }\n }\n}\n\ntemplate <MaskMode MASK_MODE, uint32_t NUM_FRAGS_Q, uint32_t NUM_FRAGS_D, uint32_t NUM_FRAGS_KV,\n typename AttentionVariant, typename DTypeQKAccum>\n__device__ __forceinline__ void logits_mask(const typename AttentionVariant::ParamsT& params,\n AttentionVariant variant, const uint32_t batch_idx,\n const uint32_t qo_packed_idx_base,\n const uint32_t kv_idx_base, const uint32_t qo_len,\n const uint32_t kv_len, const uint32_t chunk_end,\n const uint_fastdiv group_size,\n DTypeQKAccum (*s_frag)[NUM_FRAGS_KV][8]) {\n const uint32_t lane_idx = threadIdx.x, kv_head_idx = blockIdx.z;\n uint32_t q[NUM_FRAGS_Q][2], r[NUM_FRAGS_Q][2];\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n group_size.divmod(qo_packed_idx_base + fq * 16 + lane_idx / 4 + 8 * j, q[fq][j], r[fq][j]);\n }\n }\n\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t fkv = 0; fkv < NUM_FRAGS_KV; ++fkv) {\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n const uint32_t q_idx = q[fq][(reg_id % 4) / 2], kv_idx = kv_idx_base + fkv * 16 +\n 2 * (lane_idx % 4) +\n 8 * (reg_id / 4) + reg_id % 2;\n const uint32_t qo_head_idx = kv_head_idx * group_size + r[fq][(reg_id % 4) / 2];\n const bool mask =\n (!(MASK_MODE == MaskMode::kCausal\n ? (kv_idx + qo_len > kv_len + q_idx || (kv_idx >= chunk_end))\n : kv_idx >= chunk_end)) &&\n variant.LogitsMask(params, batch_idx, q_idx, kv_idx, qo_head_idx, kv_head_idx);\n s_frag[fq][fkv][reg_id] =\n (mask) ? s_frag[fq][fkv][reg_id]\n : (variant.use_softmax ? DTypeQKAccum(-math::inf) : DTypeQKAccum(0.f));\n }\n }\n }\n}\n\ntemplate <uint32_t NUM_FRAGS_Q, uint32_t NUM_FRAGS_D, uint32_t NUM_FRAGS_KV, typename DTypeQKAccum,\n typename AttentionVariant>\n__device__ __forceinline__ void update_mdo_states(AttentionVariant variant,\n DTypeQKAccum (*s_frag)[NUM_FRAGS_KV][8],\n float (*o_frag)[NUM_FRAGS_D][8],\n DTypeQKAccum (*m)[2], float (*d)[2]) {\n if constexpr (variant.use_softmax) {\n if constexpr (std::is_same_v<DTypeQKAccum, float>) {\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n float m_prev = m[fq][j];\n#pragma unroll\n for (uint32_t fkv = 0; fkv < NUM_FRAGS_KV; ++fkv) {\n float m_local = max(max(s_frag[fq][fkv][j * 2 + 0], s_frag[fq][fkv][j * 2 + 1]),\n max(s_frag[fq][fkv][j * 2 + 4], s_frag[fq][fkv][j * 2 + 5]));\n m[fq][j] = max(m[fq][j], m_local);\n }\n m[fq][j] = max(m[fq][j], math::shfl_xor_sync(m[fq][j], 0x2));\n m[fq][j] = max(m[fq][j], math::shfl_xor_sync(m[fq][j], 0x1));\n\n float o_scale = math::ptx_exp2(m_prev - m[fq][j]);\n d[fq][j] *= o_scale;\n#pragma unroll\n for (uint32_t fd = 0; fd < NUM_FRAGS_D; ++fd) {\n o_frag[fq][fd][j * 2 + 0] *= o_scale;\n o_frag[fq][fd][j * 2 + 1] *= o_scale;\n o_frag[fq][fd][j * 2 + 4] *= o_scale;\n o_frag[fq][fd][j * 2 + 5] *= o_scale;\n }\n#pragma unroll\n for (uint32_t fkv = 0; fkv < NUM_FRAGS_KV; ++fkv) {\n s_frag[fq][fkv][j * 2 + 0] = math::ptx_exp2(s_frag[fq][fkv][j * 2 + 0] - m[fq][j]);\n s_frag[fq][fkv][j * 2 + 1] = math::ptx_exp2(s_frag[fq][fkv][j * 2 + 1] - m[fq][j]);\n s_frag[fq][fkv][j * 2 + 4] = math::ptx_exp2(s_frag[fq][fkv][j * 2 + 4] - m[fq][j]);\n s_frag[fq][fkv][j * 2 + 5] = math::ptx_exp2(s_frag[fq][fkv][j * 2 + 5] - m[fq][j]);\n }\n }\n }\n } else if constexpr (std::is_same_v<DTypeQKAccum, half>) {\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n half m_prev[2];\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n m_prev[j] = m[fq][j];\n#pragma unroll\n for (uint32_t fkv = 0; fkv < NUM_FRAGS_KV; ++fkv) {\n half2 m_local =\n __hmax2(*(half2*)&s_frag[fq][fkv][j * 2], *(half2*)&s_frag[fq][fkv][j * 2 + 4]);\n m[fq][j] = __hmax(m[fq][j], __hmax(m_local.x, m_local.y));\n }\n }\n *(half2*)&m[fq] = __hmax2(*(half2*)&m[fq], math::shfl_xor_sync(*(half2*)&m[fq], 0x2));\n *(half2*)&m[fq] = __hmax2(*(half2*)&m[fq], math::shfl_xor_sync(*(half2*)&m[fq], 0x1));\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n float o_scale = math::ptx_exp2(float(m_prev[j] - m[fq][j]));\n d[fq][j] *= o_scale;\n#pragma unroll\n for (uint32_t fd = 0; fd < NUM_FRAGS_D; ++fd) {\n o_frag[fq][fd][j * 2 + 0] *= o_scale;\n o_frag[fq][fd][j * 2 + 1] *= o_scale;\n o_frag[fq][fd][j * 2 + 4] *= o_scale;\n o_frag[fq][fd][j * 2 + 5] *= o_scale;\n }\n half2 m2 = make_half2(m[fq][j], m[fq][j]);\n#pragma unroll\n for (uint32_t fkv = 0; fkv < NUM_FRAGS_KV; ++fkv) {\n *(half2*)&s_frag[fq][fkv][j * 2] =\n math::ptx_exp2(*(half2*)&s_frag[fq][fkv][j * 2] - m2);\n *(half2*)&s_frag[fq][fkv][j * 2 + 4] =\n math::ptx_exp2(*(half2*)&s_frag[fq][fkv][j * 2 + 4] - m2);\n }\n }\n }\n }\n }\n}\n\ntemplate <uint32_t NUM_FRAGS_Q, uint32_t NUM_FRAGS_D, uint32_t NUM_FRAGS_KV,\n SwizzleMode swizzle_mode, typename DTypeQ, typename DTypeKV, typename DTypeQKAccum,\n typename AttentionVariant>\n__device__ __forceinline__ void compute_sfm_v(AttentionVariant variant,\n smem_t<swizzle_mode>* v_smem,\n uint32_t* v_smem_offset_r,\n DTypeQKAccum (*s_frag)[NUM_FRAGS_KV][8],\n float (*o_frag)[NUM_FRAGS_D][8], float (*d)[2]) {\n constexpr uint32_t head_dim = NUM_FRAGS_D * 16;\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<DTypeKV>();\n\n DTypeQ s_frag_f16[NUM_FRAGS_Q][NUM_FRAGS_KV][8];\n if constexpr (std::is_same_v<DTypeQKAccum, float>) {\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t fkv = 0; fkv < NUM_FRAGS_KV; ++fkv) {\n vec_cast<DTypeQ, float>::cast<8>(s_frag_f16[fq][fkv], s_frag[fq][fkv]);\n }\n }\n }\n\n if constexpr (variant.use_softmax) {\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t fkv = 0; fkv < NUM_FRAGS_KV; ++fkv) {\n if constexpr (std::is_same_v<DTypeQKAccum, float>) {\n mma::rowsum_f16f16f32(d[fq], s_frag_f16[fq][fkv]);\n } else {\n mma::rowsum_f16f16f32(d[fq], s_frag[fq][fkv]);\n }\n }\n }\n }\n\n#pragma unroll\n for (uint32_t fkv = 0; fkv < NUM_FRAGS_KV; ++fkv) {\n#pragma unroll\n for (uint32_t fd = 0; fd < NUM_FRAGS_D; ++fd) {\n uint32_t b_frag[4];\n if constexpr (sizeof(DTypeKV) == 1) {\n uint32_t b_frag_f8[2];\n if (fd % 2 == 0) {\n v_smem->ldmatrix_m8n8x4_trans_left_half(*v_smem_offset_r, b_frag_f8);\n } else {\n v_smem->ldmatrix_m8n8x4_trans_right_half(*v_smem_offset_r, b_frag_f8);\n }\n b_frag_f8[0] = frag_layout_swizzle_16b_to_8b_trans(b_frag_f8[0]);\n b_frag_f8[1] = frag_layout_swizzle_16b_to_8b_trans(b_frag_f8[1]);\n vec_cast<DTypeQ, DTypeKV>::cast<8>((DTypeQ*)b_frag, (DTypeKV*)b_frag_f8);\n swap(b_frag[1], b_frag[2]);\n } else {\n v_smem->ldmatrix_m8n8x4_trans(*v_smem_offset_r, b_frag);\n }\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n if constexpr (std::is_same_v<DTypeQKAccum, float>) {\n mma::mma_sync_m16n16k16_row_col_f16f16f32<DTypeQ>(\n o_frag[fq][fd], (uint32_t*)(s_frag_f16[fq][fkv]), b_frag);\n } else {\n mma::mma_sync_m16n16k16_row_col_f16f16f32<DTypeQ>(o_frag[fq][fd],\n (uint32_t*)s_frag[fq][fkv], b_frag);\n }\n }\n if constexpr (sizeof(DTypeKV) == 1) {\n if (fd % 2 == 1) {\n *v_smem_offset_r = v_smem->template advance_offset_by_column<2>(*v_smem_offset_r, fd / 2);\n }\n } else {\n *v_smem_offset_r = v_smem->template advance_offset_by_column<2>(*v_smem_offset_r, fd);\n }\n }\n *v_smem_offset_r =\n v_smem->template advance_offset_by_row<16, channel_size_128b_kv>(*v_smem_offset_r) -\n sizeof(DTypeKV) * NUM_FRAGS_D;\n }\n *v_smem_offset_r -= 16 * NUM_FRAGS_KV * channel_size_128b_kv;\n}\n\ntemplate <uint32_t NUM_FRAGS_Q, uint32_t NUM_FRAGS_D, typename DTypeQKAccum,\n typename AttentionVariant>\n__device__ __forceinline__ void normalize_d(AttentionVariant variant,\n float (*o_frag)[NUM_FRAGS_D][8], DTypeQKAccum (*m)[2],\n float (*d)[2]) {\n if constexpr (variant.use_softmax) {\n float d_rcp[NUM_FRAGS_Q][2];\n // compute reciprocal of d\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n d_rcp[fq][j] = (m[fq][j] != DTypeQKAccum(-math::inf)) ? math::ptx_rcp(d[fq][j]) : 0.f;\n }\n }\n\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t fd = 0; fd < NUM_FRAGS_D; ++fd) {\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n o_frag[fq][fd][reg_id] = o_frag[fq][fd][reg_id] * d_rcp[fq][(reg_id % 4) / 2];\n }\n }\n }\n }\n}\n\n/*!\n * \\brief Synchronize the states of the MDO kernel across the threadblock along threadIdx.z.\n */\ntemplate <uint32_t NUM_WARPS_Q, uint32_t NUM_WARPS_KV, uint32_t NUM_FRAGS_Q, uint32_t NUM_FRAGS_D,\n typename DTypeQKAccum, typename AttentionVariant>\n__device__ __forceinline__ void threadblock_sync_mdo_states(\n AttentionVariant variant, float (*o_frag)[NUM_FRAGS_D][8], float* smem_workspace,\n DTypeQKAccum (*m)[2], float (*d)[2], const uint32_t warp_idx, const uint32_t lane_idx) {\n // only necessary when blockDim.z > 1\n if constexpr (NUM_WARPS_KV > 1) {\n float2* smem_md = (float2*)(smem_workspace + NUM_FRAGS_Q * NUM_FRAGS_D * NUM_WARPS_Q *\n NUM_WARPS_KV * WARP_SIZE * 8);\n // o: [num_warps, NUM_FRAGS_Q, NUM_FRAGS_D, WARP_SIZE(32), 8]\n // md: [num_warps, NUM_FRAGS_Q, 2, WARP_SIZE(32), 2 (m/d)]\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t fd = 0; fd < NUM_FRAGS_D; ++fd) {\n vec_t<float, 8>::memcpy(\n smem_workspace +\n (((warp_idx * NUM_FRAGS_Q + fq) * NUM_FRAGS_D + fd) * WARP_SIZE + lane_idx) * 8,\n o_frag[fq][fd]);\n }\n }\n\n if constexpr (variant.use_softmax) {\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n smem_md[((warp_idx * NUM_FRAGS_Q + fq) * 2 + j) * WARP_SIZE + lane_idx] =\n make_float2(float(m[fq][j]), d[fq][j]);\n }\n }\n\n // synchronize m,d first\n __syncthreads();\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n float o_scale[2][NUM_WARPS_KV];\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n float m_new = -math::inf, d_new = 1.f;\n#pragma unroll\n for (uint32_t i = 0; i < NUM_WARPS_KV; ++i) {\n float2 md = smem_md[(((i * NUM_WARPS_Q + get_warp_idx_q<NUM_WARPS_Q, NUM_WARPS_KV>()) *\n NUM_FRAGS_Q +\n fq) *\n 2 +\n j) *\n WARP_SIZE +\n lane_idx];\n float m_prev = m_new, d_prev = d_new;\n m_new = max(m_new, md.x);\n d_new = d_prev * math::ptx_exp2(m_prev - m_new) + md.y * math::ptx_exp2(md.x - m_new);\n }\n\n#pragma unroll\n for (uint32_t i = 0; i < NUM_WARPS_KV; ++i) {\n float2 md = smem_md[(((i * NUM_WARPS_Q + get_warp_idx_q<NUM_WARPS_Q, NUM_WARPS_KV>()) *\n NUM_FRAGS_Q +\n fq) *\n 2 +\n j) *\n WARP_SIZE +\n lane_idx];\n float mi = md.x;\n o_scale[j][i] = math::ptx_exp2(float(mi - m_new));\n }\n m[fq][j] = DTypeQKAccum(m_new);\n d[fq][j] = d_new;\n }\n\n#pragma unroll\n for (uint32_t fd = 0; fd < NUM_FRAGS_D; ++fd) {\n vec_t<float, 8> o_new;\n o_new.fill(0.f);\n#pragma unroll\n for (uint32_t i = 0; i < NUM_WARPS_KV; ++i) {\n vec_t<float, 8> oi;\n oi.load(\n smem_workspace +\n ((((i * NUM_WARPS_Q + get_warp_idx_q<NUM_WARPS_Q, NUM_WARPS_KV>()) * NUM_FRAGS_Q +\n fq) *\n NUM_FRAGS_D +\n fd) *\n WARP_SIZE +\n lane_idx) *\n 8);\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n o_new[reg_id] += oi[reg_id] * o_scale[(reg_id % 4) / 2][i];\n }\n }\n o_new.store(o_frag[fq][fd]);\n }\n }\n } else {\n // synchronize m,d first\n __syncthreads();\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t fd = 0; fd < NUM_FRAGS_D; ++fd) {\n vec_t<float, 8> o_new;\n o_new.fill(0.f);\n#pragma unroll\n for (uint32_t i = 0; i < NUM_WARPS_KV; ++i) {\n vec_t<float, 8> oi;\n oi.load(\n smem_workspace +\n ((((i * NUM_WARPS_Q + get_warp_idx_q<NUM_WARPS_Q, NUM_WARPS_KV>()) * NUM_FRAGS_Q +\n fq) *\n NUM_FRAGS_D +\n fd) *\n WARP_SIZE +\n lane_idx) *\n 8);\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n o_new[reg_id] += oi[reg_id];\n }\n }\n o_new.store(o_frag[fq][fd]);\n }\n }\n }\n }\n}\n\ntemplate <uint32_t NUM_WARPS_Q, uint32_t NUM_WARPS_KV, uint32_t NUM_FRAGS_Q, uint32_t NUM_FRAGS_D,\n SwizzleMode swizzle_mode, typename DTypeO>\n__device__ __forceinline__ void write_o_reg_gmem(\n float (*o_frag)[NUM_FRAGS_D][8], smem_t<swizzle_mode>* o_smem, DTypeO* o_ptr_base,\n const uint32_t o_packed_idx_base, const uint32_t qo_upper_bound, const uint32_t o_stride_n,\n const uint32_t o_stride_h, const uint_fastdiv group_size) {\n constexpr uint32_t head_dim = NUM_FRAGS_D * 16;\n constexpr uint32_t channel_size_128b_out = head_dim / num_elems_per_128b<DTypeO>();\n const uint32_t warp_idx_x = get_warp_idx_q<NUM_WARPS_Q, NUM_WARPS_KV>();\n const uint32_t lane_idx = threadIdx.x;\n\n if (get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>() == 0) {\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t fd = 0; fd < NUM_FRAGS_D; ++fd) {\n uint32_t o_frag_f16[4];\n vec_cast<DTypeO, float>::cast<8>((DTypeO*)o_frag_f16, o_frag[fq][fd]);\n#ifdef FLASHINFER_STMATRIX_M8N8X4_ENABLED\n uint32_t o_smem_offset_w = o_smem->get_permuted_offset<channel_size_128b_out>(\n (warp_idx_x * NUM_FRAGS_Q + fq) * 16 + lane_idx % 16, fd * 2 + lane_idx / 16);\n o_smem->stmatrix_m8n8x4(o_smem_offset_w, o_frag_f16);\n#else\n uint32_t o_smem_offset_w = o_smem->get_permuted_offset<channel_size_128b_out>(\n (warp_idx_x * NUM_FRAGS_Q + fq) * 16 + lane_idx / 4, fd * 2);\n ((uint32_t*)(o_smem->base + o_smem_offset_w))[lane_idx % 4] = o_frag_f16[0];\n ((uint32_t*)(o_smem->base + o_smem_offset_w + 8 * channel_size_128b_out))[lane_idx % 4] =\n o_frag_f16[1];\n ((uint32_t*)(o_smem->base + (o_smem_offset_w ^ 0x1)))[lane_idx % 4] = o_frag_f16[2];\n ((uint32_t*)(o_smem->base + (o_smem_offset_w ^ 0x1) +\n 8 * channel_size_128b_out))[lane_idx % 4] = o_frag_f16[3];\n#endif\n }\n }\n\n uint32_t o_smem_offset_w = o_smem->get_permuted_offset<channel_size_128b_out>(\n warp_idx_x * NUM_FRAGS_Q * 16 + lane_idx / 8, lane_idx % 8);\n\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t j = 0; j < 4; ++j) {\n uint32_t q, r;\n group_size.divmod(o_packed_idx_base + lane_idx / 8 + fq * 16 + j * 4, q, r);\n const uint32_t o_idx = q;\n DTypeO* o_ptr = o_ptr_base + q * o_stride_n + r * o_stride_h;\n#pragma unroll\n for (uint32_t fdo = 0; fdo < NUM_FRAGS_D / 4; ++fdo) {\n if (o_idx < qo_upper_bound) {\n o_smem->store_128b(o_smem_offset_w, o_ptr);\n }\n o_ptr += 8 * num_elems_per_128b<DTypeO>();\n o_smem_offset_w = o_smem->template advance_offset_by_column<8>(o_smem_offset_w, fdo);\n }\n o_smem_offset_w =\n o_smem->template advance_offset_by_row<4, channel_size_128b_out>(o_smem_offset_w) -\n 2 * NUM_FRAGS_D;\n }\n }\n }\n}\n\n} // namespace\n\n/*!\n * \\brief FlashAttention prefill CUDA kernel for a single request.\n * \\tparam partition_kv Whether to split kv_len into chunks.\n * \\tparam mask_mode The mask mode used in the attention operation.\n * \\tparam POS_ENCODING_MODE The positional encoding mode.\n * \\tparam NUM_FRAGS_Q The number of fragments in x dimension.\n * \\tparam NUM_FRAGS_D The number of fragments in y dimension.\n * \\tparam NUM_FRAGS_KV The number of fragments in z dimension.\n * \\tparam num_warps The number of warps in the threadblock.\n * \\tparam DTypeQ The data type of the query tensor.\n * \\tparam DTypeKV The data type of the key/value tensor.\n * \\tparam DTypeO The data type of the output tensor.\n * \\param q The query tensor.\n * \\param k The key tensor.\n * \\param v The value tensor.\n * \\param o The output tensor.\n * \\param tmp The temporary buffer (used when partition_kv is true).\n * \\param lse The logsumexp value.\n * \\param log2_rope_rcp_scale log2(1/(rope_scale)), where rope_scale is the scaling\n * factor used in RoPE interpolation.\n * \\param log2_rope_rcp_theta log2(1/(rope_theta)), where rope_theta is the theta\n * used in RoPE.\n */\ntemplate <MaskMode MASK_MODE, PosEncodingMode POS_ENCODING_MODE, uint32_t NUM_FRAGS_Q,\n uint32_t NUM_FRAGS_D, uint32_t NUM_FRAGS_KV, uint32_t NUM_WARPS_Q, uint32_t NUM_WARPS_KV,\n typename DTypeQKAccum, typename AttentionVariant>\n__global__\n__launch_bounds__(NUM_WARPS_Q* NUM_WARPS_KV* WARP_SIZE) void SinglePrefillWithKVCacheKernel(\n const uint_fastdiv group_size,\n const __grid_constant__ typename AttentionVariant::ParamsT params) {\n using DTypeQ = typename AttentionVariant::DTypeQ;\n#if (__CUDA_ARCH__ < 800)\n if constexpr (std::is_same_v<DTypeQ, nv_bfloat16>) {\n FLASHINFER_RUNTIME_ASSERT(\"Prefill kernels do not support bf16 on sm75.\");\n } else {\n#endif\n using DTypeKV = typename AttentionVariant::DTypeKV;\n using DTypeO = typename AttentionVariant::DTypeO;\n DTypeQ* q = params.q;\n DTypeKV* k = params.k;\n DTypeKV* v = params.v;\n DTypeO* o = params.o;\n float* lse = params.lse;\n const uint32_t qo_len = params.qo_len;\n const uint32_t kv_len = params.kv_len;\n const bool partition_kv = params.partition_kv;\n const uint32_t q_stride_n = params.q_stride_n;\n const uint32_t q_stride_h = params.q_stride_h;\n const uint32_t kv_stride_n = params.kv_stride_n;\n const uint32_t kv_stride_h = params.kv_stride_h;\n const int32_t maybe_window_left = params.window_left;\n\n static_assert(sizeof(DTypeQ) == 2);\n static_assert(sizeof(DTypeO) == 2);\n const uint32_t lane_idx = threadIdx.x, warp_idx = get_warp_idx<NUM_WARPS_Q, NUM_WARPS_KV>();\n const uint32_t bx = blockIdx.x, chunk_idx = blockIdx.y, kv_head_idx = blockIdx.z;\n const uint32_t num_kv_heads = gridDim.z, num_qo_heads = num_kv_heads * group_size;\n constexpr uint32_t num_rows_per_cta = NUM_FRAGS_Q * NUM_WARPS_Q * 16;\n const tensor_info_t qkv_info(qo_len, kv_len, num_qo_heads, num_kv_heads, q_stride_n, q_stride_h,\n kv_stride_n, kv_stride_h, /*head_dim=*/NUM_FRAGS_D * 16);\n\n const uint32_t num_chunks = gridDim.y;\n const uint32_t max_chunk_size = partition_kv ? ceil_div(kv_len, num_chunks) : kv_len;\n const uint32_t chunk_start = partition_kv ? chunk_idx * max_chunk_size : 0;\n const uint32_t chunk_end =\n partition_kv ? min((chunk_idx + 1) * max_chunk_size, kv_len) : kv_len;\n const uint32_t chunk_size = chunk_end - chunk_start;\n\n auto block = cg::this_thread_block();\n extern __shared__ uint8_t smem[];\n AttentionVariant variant(params, /*batch_idx=*/0, smem);\n const uint32_t window_left = variant.window_left;\n\n constexpr uint32_t head_dim = NUM_FRAGS_D * 16;\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<DTypeKV>();\n constexpr uint32_t channel_size_128b_out = head_dim / num_elems_per_128b<DTypeO>();\n\n DTypeQKAccum s_frag[NUM_FRAGS_Q][NUM_FRAGS_KV][8];\n float o_frag[NUM_FRAGS_Q][NUM_FRAGS_D][8];\n DTypeQKAccum m[NUM_FRAGS_Q][2];\n float d[NUM_FRAGS_Q][2];\n float rope_freq[NUM_FRAGS_D / 2][4];\n if constexpr (POS_ENCODING_MODE == PosEncodingMode::kRoPELlama) {\n const float log2_rope_rcp_scale = params.log2_rope_rcp_scale;\n const float log2_rope_rcp_theta = params.log2_rope_rcp_theta;\n init_rope_freq<NUM_FRAGS_D>(rope_freq, log2_rope_rcp_scale, log2_rope_rcp_theta);\n }\n init_states<NUM_FRAGS_Q, NUM_FRAGS_D>(variant, o_frag, m, d);\n\n // cooperative fetch q fragment from gmem to reg\n const uint32_t qo_packed_idx_base =\n (bx * NUM_WARPS_Q + get_warp_idx_q<NUM_WARPS_Q, NUM_WARPS_KV>()) * NUM_FRAGS_Q * 16;\n constexpr SwizzleMode swizzle_mode_q = SwizzleMode::k128B;\n smem_t<swizzle_mode_q> qo_smem(smem);\n DTypeQ* q_ptr_base =\n q + qkv_info.get_q_elem_offset(0, kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeQ>());\n DTypeO* o_ptr_base =\n partition_kv\n ? o + chunk_idx * num_qo_heads * head_dim +\n qkv_info.get_o_elem_offset(0, kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeO>())\n : o + qkv_info.get_o_elem_offset(0, kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeO>());\n\n uint32_t q_smem_offset_r = qo_smem.get_permuted_offset<channel_size_128b_q>(\n get_warp_idx_q<NUM_WARPS_Q, NUM_WARPS_KV>() * NUM_FRAGS_Q * 16 + lane_idx % 16,\n lane_idx / 16);\n\n load_q_global_smem<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_Q, NUM_FRAGS_D>(\n qo_packed_idx_base, qo_len, q_ptr_base, q_stride_n, q_stride_h, group_size, &qo_smem);\n\n cp_async::commit_group();\n cp_async::wait_group<0>();\n block.sync();\n\n if constexpr (POS_ENCODING_MODE == PosEncodingMode::kRoPELlama) {\n q_smem_inplace_apply_rotary<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_Q, NUM_FRAGS_D,\n swizzle_mode_q, DTypeQ>(\n qo_packed_idx_base, qo_len, kv_len, group_size, &qo_smem, &q_smem_offset_r, rope_freq);\n block.sync();\n }\n q_smem_inplace_transform<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_Q, NUM_FRAGS_D, swizzle_mode_q>(\n params, variant, &qo_smem);\n\n constexpr SwizzleMode swizzle_mode_kv =\n (sizeof(DTypeKV) == 1 && head_dim == 64) ? SwizzleMode::k64B : SwizzleMode::k128B;\n constexpr uint32_t kv_frag_rows = swizzle_mode_kv == SwizzleMode::k128B ? 4 : 8;\n constexpr uint32_t kv_frag_cols = swizzle_mode_kv == SwizzleMode::k128B ? 8 : 4;\n smem_t<swizzle_mode_kv> k_smem(smem +\n (NUM_WARPS_Q * NUM_FRAGS_Q * sizeof(DTypeQ)) * 16 * head_dim),\n v_smem(smem + (NUM_WARPS_Q * NUM_FRAGS_Q * sizeof(DTypeQ) +\n NUM_WARPS_KV * NUM_FRAGS_KV * sizeof(DTypeKV)) *\n 16 * head_dim);\n\n const uint32_t num_iterations = ceil_div(\n MASK_MODE == MaskMode::kCausal\n ? min(chunk_size,\n sub_if_greater_or_zero(\n kv_len - qo_len + ((bx + 1) * num_rows_per_cta) / group_size, chunk_start))\n : chunk_size,\n 16 * NUM_WARPS_KV * NUM_FRAGS_KV);\n\n const uint32_t window_iteration =\n ceil_div(sub_if_greater_or_zero(kv_len + (bx + 1) * num_rows_per_cta,\n qo_len + window_left + chunk_start),\n (16 * NUM_WARPS_KV * NUM_FRAGS_KV));\n\n const uint32_t mask_iteration =\n (MASK_MODE == MaskMode::kCausal\n ? min(chunk_size,\n sub_if_greater_or_zero(kv_len + (bx * num_rows_per_cta) / group_size - qo_len,\n chunk_start))\n : chunk_size) /\n (16 * NUM_WARPS_KV * NUM_FRAGS_KV);\n\n DTypeKV* k_ptr =\n k + qkv_info.get_kv_elem_offset(\n chunk_start + warp_idx * kv_frag_rows + lane_idx / kv_frag_cols, kv_head_idx,\n (lane_idx % kv_frag_cols) * num_elems_per_128b<DTypeKV>());\n DTypeKV* v_ptr =\n v + qkv_info.get_kv_elem_offset(\n chunk_start + warp_idx * kv_frag_rows + lane_idx / kv_frag_cols, kv_head_idx,\n (lane_idx % kv_frag_cols) * num_elems_per_128b<DTypeKV>());\n\n uint32_t k_smem_offset_r = k_smem.get_permuted_offset<channel_size_128b_kv>(\n get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>() * NUM_FRAGS_KV * 16 +\n 8 * (lane_idx / 16) + lane_idx % 8,\n (lane_idx % 16) / 8),\n v_smem_offset_r = v_smem.get_permuted_offset<channel_size_128b_kv>(\n get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>() * NUM_FRAGS_KV * 16 + lane_idx % 16,\n lane_idx / 16),\n kv_smem_offset_w = k_smem.get_permuted_offset<channel_size_128b_kv>(\n warp_idx * kv_frag_rows + lane_idx / kv_frag_cols, lane_idx % kv_frag_cols);\n produce_kv<SharedMemFillMode::kNoFill, NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_D, NUM_FRAGS_KV>(\n k_smem, &kv_smem_offset_w, &k_ptr, kv_stride_n, 0, chunk_size);\n cp_async::commit_group();\n produce_kv<SharedMemFillMode::kFillZero, NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_D, NUM_FRAGS_KV>(\n v_smem, &kv_smem_offset_w, &v_ptr, kv_stride_n, 0, chunk_size);\n cp_async::commit_group();\n\n#pragma unroll 1\n for (uint32_t iter = 0; iter < num_iterations; ++iter) {\n cp_async::wait_group<1>();\n block.sync();\n\n if constexpr (POS_ENCODING_MODE == PosEncodingMode::kRoPELlama) {\n k_smem_inplace_apply_rotary<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_D, NUM_FRAGS_KV,\n swizzle_mode_kv, DTypeKV>(\n chunk_start + iter * 16 * NUM_WARPS_KV * NUM_FRAGS_KV, &k_smem, &k_smem_offset_r,\n rope_freq);\n block.sync();\n }\n\n // compute attention score\n compute_qk<NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV, swizzle_mode_q, swizzle_mode_kv, DTypeQ,\n DTypeKV>(&qo_smem, &q_smem_offset_r, &k_smem, &k_smem_offset_r, s_frag);\n\n logits_transform<NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV>(\n params, variant, /*batch_idx=*/0, qo_packed_idx_base,\n chunk_start + (iter * NUM_WARPS_KV + get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>()) *\n NUM_FRAGS_KV * 16,\n qo_len, kv_len, group_size, s_frag);\n\n // apply mask\n if (MASK_MODE == MaskMode::kCustom || (iter >= mask_iteration || iter < window_iteration)) {\n logits_mask<MASK_MODE, NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV>(\n params, variant, /*batch_idx=*/0, qo_packed_idx_base,\n chunk_start + (iter * NUM_WARPS_KV + get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>()) *\n NUM_FRAGS_KV * 16,\n qo_len, kv_len, chunk_end, group_size, s_frag);\n }\n\n // compute m,d states in online softmax\n update_mdo_states<NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV>(variant, s_frag, o_frag, m, d);\n\n block.sync();\n produce_kv<SharedMemFillMode::kNoFill, NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_D, NUM_FRAGS_KV>(\n k_smem, &kv_smem_offset_w, &k_ptr, kv_stride_n,\n (iter + 1) * 16 * NUM_WARPS_KV * NUM_FRAGS_KV, chunk_size);\n cp_async::commit_group();\n cp_async::wait_group<1>();\n block.sync();\n\n // compute sfm*v\n compute_sfm_v<NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV, swizzle_mode_kv, DTypeQ, DTypeKV>(\n variant, &v_smem, &v_smem_offset_r, s_frag, o_frag, d);\n\n block.sync();\n produce_kv<SharedMemFillMode::kFillZero, NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_D,\n NUM_FRAGS_KV>(v_smem, &kv_smem_offset_w, &v_ptr, kv_stride_n,\n (iter + 1) * 16 * NUM_WARPS_KV * NUM_FRAGS_KV, chunk_size);\n cp_async::commit_group();\n }\n cp_async::wait_group<0>();\n block.sync();\n\n // threadblock synchronization\n threadblock_sync_mdo_states<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_Q, NUM_FRAGS_D, DTypeQKAccum>(\n variant, o_frag, (float*)smem, m, d, warp_idx, lane_idx);\n\n // normalize d\n normalize_d<NUM_FRAGS_Q, NUM_FRAGS_D>(variant, o_frag, m, d);\n\n // write back\n write_o_reg_gmem<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_Q, NUM_FRAGS_D>(\n o_frag, &qo_smem, o_ptr_base, qo_packed_idx_base, qo_len,\n /*o_stride_n=*/\n partition_kv ? num_qo_heads * head_dim * num_chunks : num_qo_heads * head_dim,\n /*o_stride_h=*/head_dim, group_size);\n\n // write lse\n if constexpr (variant.use_softmax) {\n if (lse != nullptr || partition_kv) {\n if (get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>() == 0) {\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n uint32_t q, r;\n group_size.divmod(qo_packed_idx_base + lane_idx / 4 + j * 8 + fq * 16, q, r);\n const uint32_t qo_head_idx = kv_head_idx * group_size + r;\n const uint32_t qo_idx = q;\n if (qo_idx < qo_len) {\n if (partition_kv) {\n lse[(qo_idx * num_chunks + chunk_idx) * num_qo_heads + qo_head_idx] =\n math::ptx_log2(d[fq][j]) + float(m[fq][j]);\n } else {\n lse[qo_idx * num_qo_heads + qo_head_idx] =\n math::ptx_log2(d[fq][j]) + float(m[fq][j]);\n }\n }\n }\n }\n }\n }\n }\n#if (__CUDA_ARCH__ < 800)\n }\n#endif\n}\n\ntemplate <uint32_t HEAD_DIM, PosEncodingMode POS_ENCODING_MODE, bool ALLOW_FP16_QK_REDUCTION,\n MaskMode MASK_MODE, typename AttentionVariant>\ncudaError_t SinglePrefillWithKVCacheDispatched(typename AttentionVariant::ParamsT params,\n typename AttentionVariant::DTypeO* tmp,\n cudaStream_t stream) {\n using DTypeQ = typename AttentionVariant::DTypeQ;\n using DTypeKV = typename AttentionVariant::DTypeKV;\n using DTypeO = typename AttentionVariant::DTypeO;\n const uint32_t num_qo_heads = params.num_qo_heads;\n const uint32_t num_kv_heads = params.num_kv_heads;\n const uint32_t qo_len = params.qo_len;\n const uint32_t kv_len = params.kv_len;\n if (kv_len < qo_len && MASK_MODE == MaskMode::kCausal) {\n std::ostringstream err_msg;\n err_msg << \"When mask_mode is set to MaskMode::kCausal, kv_len must be greater than or equal \"\n \"to qo_len, got kv_len\"\n << kv_len << \" and qo_len \" << qo_len;\n throw std::invalid_argument(err_msg.str());\n }\n\n const uint32_t group_size = num_qo_heads / num_kv_heads;\n const uint_fastdiv group_size_fastdiv(group_size);\n constexpr uint32_t NUM_FRAGS_D = HEAD_DIM / 16;\n uint32_t cta_tile_q = 0;\n int64_t unpacked_qo_len = qo_len * group_size;\n if (unpacked_qo_len > 64 && HEAD_DIM < 256) {\n cta_tile_q = 128;\n } else {\n auto compute_capacity = GetCudaComputeCapability();\n if (compute_capacity.first >= 8) {\n // Ampere or newer\n if (unpacked_qo_len > 16) {\n // avg_packed_qo_len <= 64\n cta_tile_q = 64;\n } else {\n // avg_packed_qo_len <= 16\n cta_tile_q = 16;\n }\n } else {\n // NOTE(Zihao): not enough shared memory on Turing for 1x4 warp layout\n cta_tile_q = 64;\n }\n }\n\n DISPATCH_CTA_TILE_Q(cta_tile_q, CTA_TILE_Q, {\n constexpr uint32_t NUM_WARPS_Q = get_num_warps_q(CTA_TILE_Q);\n constexpr uint32_t NUM_WARPS_KV = get_num_warps_kv(CTA_TILE_Q);\n constexpr uint32_t NUM_FRAGS_Q = get_num_frags_q(CTA_TILE_Q);\n\n using DTypeQKAccum =\n typename std::conditional<ALLOW_FP16_QK_REDUCTION && std::is_same_v<DTypeQ, half>, half,\n float>::type;\n\n int dev_id = 0;\n FLASHINFER_CUDA_CALL(cudaGetDevice(&dev_id));\n int max_smem_per_sm = 0;\n FLASHINFER_CUDA_CALL(cudaDeviceGetAttribute(\n &max_smem_per_sm, cudaDevAttrMaxSharedMemoryPerMultiprocessor, dev_id));\n // we expect each sm execute two threadblocks\n // TODO(Zihao): fix the following computation\n const int num_ctas_per_sm = max_smem_per_sm > (16 * HEAD_DIM * sizeof(DTypeQ) * 16) ? 2 : 1;\n const int max_smem_per_threadblock = max_smem_per_sm / num_ctas_per_sm;\n\n const uint32_t max_num_frags_kv_reg =\n (HEAD_DIM >= 128 && NUM_FRAGS_Q == 2 && POS_ENCODING_MODE == PosEncodingMode::kRoPELlama &&\n !ALLOW_FP16_QK_REDUCTION)\n ? 2\n : (8 / NUM_FRAGS_Q);\n // TODO(Zihao): fix the following computation\n const uint32_t max_num_frags_kv_smem =\n (max_smem_per_threadblock / (16 * HEAD_DIM * sizeof(DTypeQ)) - NUM_FRAGS_Q * NUM_WARPS_Q) /\n (2 * NUM_WARPS_KV);\n\n // control NUM_FRAGS_KV for maximum warp occupancy\n DISPATCH_NUM_FRAGS_KV(min(max_num_frags_kv_smem, max_num_frags_kv_reg), NUM_FRAGS_KV, {\n if constexpr (is_invalid_configuration<POS_ENCODING_MODE, DTypeKV, DTypeQKAccum>(\n NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV, NUM_WARPS_Q, NUM_WARPS_KV)) {\n // Invalid configuration, skip\n std::ostringstream err_msg;\n err_msg << \"FlashInfer Internal Error: Invalid configuration : NUM_FRAGS_Q=\" << NUM_FRAGS_Q\n << \" NUM_FRAGS_D=\" << NUM_FRAGS_D << \" NUM_FRAGS_KV=\" << NUM_FRAGS_KV\n << \" NUM_WARPS_Q=\" << NUM_WARPS_Q << \" NUM_WARPS_KV=\" << NUM_WARPS_KV\n << \" please create an issue (https://github.com/flashinfer-ai/flashinfer/issues)\"\n \" and report the issue to the developers.\";\n throw std::invalid_argument(err_msg.str());\n } else {\n constexpr uint32_t num_threads = (NUM_WARPS_Q * NUM_WARPS_KV) * WARP_SIZE;\n constexpr uint32_t num_rows_per_cta = NUM_FRAGS_Q * NUM_WARPS_Q * 16;\n auto kernel = SinglePrefillWithKVCacheKernel<MASK_MODE, POS_ENCODING_MODE, NUM_FRAGS_Q,\n NUM_FRAGS_D, NUM_FRAGS_KV, NUM_WARPS_Q,\n NUM_WARPS_KV, DTypeQKAccum, AttentionVariant>;\n // TODO(Zihao): fix the following computation\n uint32_t smem_size = (NUM_FRAGS_Q * NUM_WARPS_Q * sizeof(DTypeQ) +\n NUM_FRAGS_KV * NUM_WARPS_KV * 2 * sizeof(DTypeQ)) *\n 16 * HEAD_DIM;\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n int num_blocks_per_sm = 0;\n int num_sm = 0;\n FLASHINFER_CUDA_CALL(\n cudaDeviceGetAttribute(&num_sm, cudaDevAttrMultiProcessorCount, dev_id));\n FLASHINFER_CUDA_CALL(cudaOccupancyMaxActiveBlocksPerMultiprocessor(\n &num_blocks_per_sm, kernel, num_threads, smem_size));\n uint32_t max_num_kv_chunks =\n (num_blocks_per_sm * num_sm) /\n (num_kv_heads * ceil_div(qo_len * group_size, num_rows_per_cta));\n uint32_t num_chunks;\n if (max_num_kv_chunks > 0) {\n uint32_t chunk_size = max(ceil_div(kv_len, max_num_kv_chunks), 256);\n num_chunks = ceil_div(kv_len, chunk_size);\n } else {\n num_chunks = 0;\n }\n\n if (num_chunks <= 1 || tmp == nullptr) {\n // Enough parallelism, do not split-kv\n params.partition_kv = false;\n void* args[] = {(void*)&group_size_fastdiv, (void*)¶ms};\n dim3 nblks(ceil_div(qo_len * group_size, num_rows_per_cta), 1, num_kv_heads);\n dim3 nthrs(32, NUM_WARPS_Q, NUM_WARPS_KV);\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n } else {\n // Use cooperative groups to increase occupancy\n params.partition_kv = true;\n float* tmp_lse = (float*)(tmp + num_chunks * qo_len * num_qo_heads * HEAD_DIM);\n auto o = params.o;\n auto lse = params.lse;\n params.o = tmp;\n params.lse = tmp_lse;\n void* args[] = {(void*)&group_size_fastdiv, (void*)¶ms};\n dim3 nblks(ceil_div(qo_len * group_size, num_rows_per_cta), num_chunks, num_kv_heads);\n dim3 nthrs(32, NUM_WARPS_Q, NUM_WARPS_KV);\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n if constexpr (AttentionVariant::use_softmax) {\n FLASHINFER_CUDA_CALL(MergeStates(tmp, tmp_lse, o, lse, num_chunks, qo_len, num_qo_heads,\n HEAD_DIM, stream));\n } else {\n FLASHINFER_CUDA_CALL(\n AttentionSum(tmp, o, num_chunks, qo_len, num_qo_heads, HEAD_DIM, stream));\n }\n }\n }\n })\n });\n return cudaSuccess;\n}\n\ntemplate <MaskMode MASK_MODE, PosEncodingMode POS_ENCODING_MODE, uint32_t NUM_FRAGS_Q,\n uint32_t NUM_FRAGS_D, uint32_t NUM_FRAGS_KV, uint32_t NUM_WARPS_Q, uint32_t NUM_WARPS_KV,\n typename DTypeQKAccum, typename AttentionVariant>\n__global__\n__launch_bounds__(NUM_WARPS_Q* NUM_WARPS_KV* WARP_SIZE) void BatchPrefillWithRaggedKVCacheKernel(\n const uint_fastdiv group_size,\n const __grid_constant__ typename AttentionVariant::ParamsT params) {\n using DTypeQ = typename AttentionVariant::DTypeQ;\n#if (__CUDA_ARCH__ < 800)\n if constexpr (std::is_same_v<DTypeQ, nv_bfloat16>) {\n FLASHINFER_RUNTIME_ASSERT(\"Prefill kernels do not support bf16 on sm75.\");\n } else {\n#endif\n using DTypeKV = typename AttentionVariant::DTypeKV;\n using DTypeO = typename AttentionVariant::DTypeO;\n using IdType = typename AttentionVariant::IdType;\n DTypeQ* q = params.q;\n IdType* request_indices = params.request_indices;\n IdType* qo_tile_indices = params.qo_tile_indices;\n IdType* kv_tile_indices = params.kv_tile_indices;\n IdType* q_indptr = params.q_indptr;\n IdType* kv_indptr = params.kv_indptr;\n DTypeKV* k = params.k;\n DTypeKV* v = params.v;\n IdType* q_offset = params.q_offset;\n IdType* k_rope_pos_offset = params.k_rope_pos_offset;\n IdType* o_indptr = params.o_indptr;\n DTypeO* o = params.o;\n float* lse = params.lse;\n bool* block_valid_mask = params.block_valid_mask;\n const bool partition_kv = params.partition_kv;\n const uint32_t q_stride_n = params.q_stride_n;\n const uint32_t q_stride_h = params.q_stride_h;\n const uint32_t kv_stride_n = params.kv_stride_n;\n const uint32_t kv_stride_h = params.kv_stride_h;\n const int32_t maybe_window_left = params.window_left;\n\n static_assert(sizeof(DTypeQ) == 2);\n static_assert(sizeof(DTypeO) == 2);\n constexpr uint32_t head_dim = NUM_FRAGS_D * 16;\n const uint32_t kv_chunk_size = *(params.kv_chunk_size_ptr);\n\n auto block = cg::this_thread_block();\n const uint32_t bx = blockIdx.x, lane_idx = threadIdx.x,\n warp_idx = get_warp_idx<NUM_WARPS_Q, NUM_WARPS_KV>(), kv_head_idx = blockIdx.z;\n if (block_valid_mask && !block_valid_mask[bx]) {\n return;\n }\n const uint32_t num_kv_heads = gridDim.z, num_qo_heads = group_size * num_kv_heads;\n const uint32_t request_idx = request_indices[bx], qo_tile_idx = qo_tile_indices[bx],\n kv_tile_idx = kv_tile_indices[bx];\n constexpr uint32_t num_rows_per_cta = NUM_FRAGS_Q * NUM_WARPS_Q * 16;\n extern __shared__ uint8_t smem[];\n AttentionVariant variant(params, /*batch_idx=*/request_idx, smem);\n const uint32_t qo_len = variant.qo_len, kv_len = variant.kv_len,\n window_left = variant.window_left;\n const uint32_t kv_len_safe = kv_len > 0 ? kv_len : 1;\n const uint32_t max_chunk_size = partition_kv ? kv_chunk_size : kv_len;\n const uint32_t chunk_start = partition_kv ? kv_tile_idx * max_chunk_size : 0;\n const uint32_t chunk_end =\n partition_kv ? min((kv_tile_idx + 1) * max_chunk_size, kv_len) : kv_len;\n const uint32_t chunk_size = chunk_end - chunk_start;\n const tensor_info_t qkv_info(qo_len, kv_len, num_qo_heads, num_kv_heads, q_stride_n, q_stride_h,\n kv_stride_n, kv_stride_h, /*head_dim=*/NUM_FRAGS_D * 16);\n const uint32_t qo_upper_bound =\n min(qo_len, ceil_div((qo_tile_idx + 1) * num_rows_per_cta, group_size));\n\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<DTypeKV>();\n constexpr uint32_t channel_size_128b_out = head_dim / num_elems_per_128b<DTypeO>();\n\n DTypeQKAccum s_frag[NUM_FRAGS_Q][NUM_FRAGS_KV][8];\n float o_frag[NUM_FRAGS_Q][NUM_FRAGS_D][8];\n DTypeQKAccum m[NUM_FRAGS_Q][2];\n float d[NUM_FRAGS_Q][2];\n float rope_freq[NUM_FRAGS_D / 2][4];\n\n if constexpr (POS_ENCODING_MODE == PosEncodingMode::kRoPELlama) {\n const float log2_rope_rcp_scale = params.log2_rope_rcp_scale;\n const float log2_rope_rcp_theta = params.log2_rope_rcp_theta;\n init_rope_freq<NUM_FRAGS_D>(rope_freq, log2_rope_rcp_scale, log2_rope_rcp_theta);\n }\n init_states<NUM_FRAGS_Q, NUM_FRAGS_D>(variant, o_frag, m, d);\n\n const uint32_t qo_packed_idx_base =\n (qo_tile_idx * NUM_WARPS_Q + get_warp_idx_q<NUM_WARPS_Q, NUM_WARPS_KV>()) * NUM_FRAGS_Q *\n 16;\n constexpr SwizzleMode swizzle_mode_q = SwizzleMode::k128B;\n smem_t<swizzle_mode_q> qo_smem(smem);\n\n DTypeQ* q_ptr_base =\n q + qkv_info.get_q_elem_offset(q_indptr[request_idx], kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeQ>());\n\n DTypeO* o_ptr_base =\n partition_kv\n ? o + kv_tile_idx * num_qo_heads * head_dim +\n qkv_info.get_o_elem_offset(o_indptr[request_idx], kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeO>())\n : o + qkv_info.get_o_elem_offset(o_indptr[request_idx], kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeO>());\n\n uint32_t q_smem_offset_r = qo_smem.get_permuted_offset<channel_size_128b_q>(\n get_warp_idx_q<NUM_WARPS_Q, NUM_WARPS_KV>() * NUM_FRAGS_Q * 16 + lane_idx % 16,\n lane_idx / 16);\n\n load_q_global_smem<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_Q, NUM_FRAGS_D>(\n qo_packed_idx_base, qo_upper_bound, q_ptr_base, q_stride_n, q_stride_h, group_size,\n &qo_smem);\n\n cp_async::commit_group();\n cp_async::wait_group<0>();\n block.sync();\n\n if constexpr (POS_ENCODING_MODE == PosEncodingMode::kRoPELlama) {\n if (!q_offset) {\n q_smem_inplace_apply_rotary<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_Q, NUM_FRAGS_D,\n swizzle_mode_q, DTypeQ>(\n qo_packed_idx_base, qo_len, kv_len, group_size, &qo_smem, &q_smem_offset_r, rope_freq);\n } else {\n q_smem_inplace_apply_rotary_with_pos<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_Q, NUM_FRAGS_D,\n swizzle_mode_q, DTypeQ>(\n qo_packed_idx_base, q_offset + q_indptr[request_idx], &qo_smem, group_size,\n &q_smem_offset_r, rope_freq);\n }\n block.sync();\n }\n q_smem_inplace_transform<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_Q, NUM_FRAGS_D, swizzle_mode_q>(\n params, variant, &qo_smem);\n\n const uint32_t num_iterations = ceil_div(\n (MASK_MODE == MaskMode::kCausal\n ? min(chunk_size,\n sub_if_greater_or_zero(\n kv_len - qo_len + ((qo_tile_idx + 1) * num_rows_per_cta) / group_size,\n chunk_start))\n : chunk_size),\n 16 * NUM_WARPS_KV * NUM_FRAGS_KV);\n\n const uint32_t window_iteration =\n ceil_div(sub_if_greater_or_zero(kv_len + (qo_tile_idx + 1) * num_rows_per_cta,\n qo_len + window_left + chunk_start),\n (16 * NUM_WARPS_KV * NUM_FRAGS_KV));\n\n const uint32_t mask_iteration =\n (MASK_MODE == MaskMode::kCausal\n ? min(chunk_size, sub_if_greater_or_zero(\n kv_len + (qo_tile_idx * num_rows_per_cta) / group_size - qo_len,\n chunk_start))\n : chunk_size) /\n (16 * NUM_WARPS_KV * NUM_FRAGS_KV);\n\n constexpr SwizzleMode swizzle_mode_kv =\n (sizeof(DTypeKV) == 1 && head_dim == 64) ? SwizzleMode::k64B : SwizzleMode::k128B;\n constexpr uint32_t kv_frag_rows = swizzle_mode_kv == SwizzleMode::k128B ? 4 : 8;\n constexpr uint32_t kv_frag_cols = swizzle_mode_kv == SwizzleMode::k128B ? 8 : 4;\n smem_t<swizzle_mode_kv> k_smem(smem +\n (NUM_WARPS_Q * NUM_FRAGS_Q * sizeof(DTypeQ)) * 16 * head_dim),\n v_smem(smem + (NUM_WARPS_Q * NUM_FRAGS_Q * sizeof(DTypeQ) +\n NUM_WARPS_KV * NUM_FRAGS_KV * sizeof(DTypeKV)) *\n 16 * head_dim);\n\n uint32_t k_smem_offset_r = k_smem.get_permuted_offset<channel_size_128b_kv>(\n get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>() * NUM_FRAGS_KV * 16 +\n 8 * (lane_idx / 16) + lane_idx % 8,\n (lane_idx % 16) / 8),\n v_smem_offset_r = v_smem.get_permuted_offset<channel_size_128b_kv>(\n get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>() * NUM_FRAGS_KV * 16 + lane_idx % 16,\n lane_idx / 16),\n kv_smem_offset_w = k_smem.get_permuted_offset<channel_size_128b_kv>(\n warp_idx * kv_frag_rows + lane_idx / kv_frag_cols, lane_idx % kv_frag_cols);\n\n DTypeKV* k_ptr =\n k + qkv_info.get_kv_elem_offset(kv_indptr[request_idx] + chunk_start +\n warp_idx * kv_frag_rows + lane_idx / kv_frag_cols,\n kv_head_idx,\n (lane_idx % kv_frag_cols) * num_elems_per_128b<DTypeKV>());\n DTypeKV* v_ptr =\n v + qkv_info.get_kv_elem_offset(kv_indptr[request_idx] + chunk_start +\n warp_idx * kv_frag_rows + lane_idx / kv_frag_cols,\n kv_head_idx,\n (lane_idx % kv_frag_cols) * num_elems_per_128b<DTypeKV>());\n\n produce_kv<SharedMemFillMode::kNoFill, NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_D, NUM_FRAGS_KV>(\n k_smem, &kv_smem_offset_w, &k_ptr, kv_stride_n, 0, chunk_size);\n cp_async::commit_group();\n produce_kv<SharedMemFillMode::kFillZero, NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_D, NUM_FRAGS_KV>(\n v_smem, &kv_smem_offset_w, &v_ptr, kv_stride_n, 0, chunk_size);\n cp_async::commit_group();\n\n#pragma unroll 1\n for (uint32_t iter = 0; iter < num_iterations; ++iter) {\n cp_async::wait_group<1>();\n block.sync();\n\n if constexpr (POS_ENCODING_MODE == PosEncodingMode::kRoPELlama) {\n k_smem_inplace_apply_rotary<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_D, NUM_FRAGS_KV,\n swizzle_mode_kv, DTypeKV>(\n (k_rope_pos_offset == nullptr ? 0 : k_rope_pos_offset[request_idx]) + chunk_start +\n iter * 16 * NUM_WARPS_KV * NUM_FRAGS_KV,\n &k_smem, &k_smem_offset_r, rope_freq);\n block.sync();\n }\n\n // compute attention score\n compute_qk<NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV, swizzle_mode_q, swizzle_mode_kv, DTypeQ,\n DTypeKV>(&qo_smem, &q_smem_offset_r, &k_smem, &k_smem_offset_r, s_frag);\n\n logits_transform<NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV>(\n params, variant, /*batch_idx=*/request_idx, qo_packed_idx_base,\n chunk_start + (iter * NUM_WARPS_KV + get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>()) *\n NUM_FRAGS_KV * 16,\n qo_len, kv_len, group_size, s_frag);\n\n // apply mask\n if (MASK_MODE == MaskMode::kCustom || (iter >= mask_iteration || iter < window_iteration)) {\n logits_mask<MASK_MODE, NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV>(\n params, variant, /*batch_idx=*/request_idx, qo_packed_idx_base,\n chunk_start + (iter * NUM_WARPS_KV + get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>()) *\n NUM_FRAGS_KV * 16,\n qo_len, kv_len, chunk_end, group_size, s_frag);\n }\n\n // compute m,d states in online softmax\n update_mdo_states<NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV>(variant, s_frag, o_frag, m, d);\n\n block.sync();\n produce_kv<SharedMemFillMode::kNoFill, NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_D, NUM_FRAGS_KV>(\n k_smem, &kv_smem_offset_w, &k_ptr, kv_stride_n,\n (iter + 1) * 16 * NUM_WARPS_KV * NUM_FRAGS_KV, chunk_size);\n cp_async::commit_group();\n cp_async::wait_group<1>();\n block.sync();\n\n // compute sfm*v\n compute_sfm_v<NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV, swizzle_mode_kv, DTypeQ, DTypeKV>(\n variant, &v_smem, &v_smem_offset_r, s_frag, o_frag, d);\n\n block.sync();\n produce_kv<SharedMemFillMode::kFillZero, NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_D,\n NUM_FRAGS_KV>(v_smem, &kv_smem_offset_w, &v_ptr, kv_stride_n,\n (iter + 1) * 16 * NUM_WARPS_KV * NUM_FRAGS_KV, chunk_size);\n cp_async::commit_group();\n }\n cp_async::wait_group<0>();\n block.sync();\n\n // threadblock synchronization\n threadblock_sync_mdo_states<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_Q, NUM_FRAGS_D, DTypeQKAccum>(\n variant, o_frag, (float*)smem, m, d, warp_idx, lane_idx);\n\n // normalize d\n normalize_d<NUM_FRAGS_Q, NUM_FRAGS_D>(variant, o_frag, m, d);\n\n const uint32_t num_kv_chunks = (kv_len_safe + kv_chunk_size - 1) / kv_chunk_size;\n\n // write back\n write_o_reg_gmem<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_Q, NUM_FRAGS_D>(\n o_frag, &qo_smem, o_ptr_base, qo_packed_idx_base, qo_len,\n /*o_stride_n=*/\n partition_kv ? num_qo_heads * head_dim * num_kv_chunks : num_qo_heads * head_dim,\n /*o_stride_h=*/head_dim, group_size);\n\n // write lse\n if constexpr (variant.use_softmax) {\n if (lse != nullptr) {\n if (get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>() == 0) {\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n uint32_t q, r;\n group_size.divmod(qo_packed_idx_base + lane_idx / 4 + j * 8 + fq * 16, q, r);\n const uint32_t qo_head_idx = kv_head_idx * group_size + r;\n const uint32_t qo_idx = q;\n if (qo_idx < qo_len) {\n if (partition_kv) {\n lse[(o_indptr[request_idx] + qo_idx * num_kv_chunks + kv_tile_idx) *\n num_qo_heads +\n qo_head_idx] = math::ptx_log2(d[fq][j]) + float(m[fq][j]);\n } else {\n lse[(o_indptr[request_idx] + qo_idx) * num_qo_heads + qo_head_idx] =\n math::ptx_log2(d[fq][j]) + float(m[fq][j]);\n }\n }\n }\n }\n }\n }\n }\n#if (__CUDA_ARCH__ < 800)\n }\n#endif\n}\n\ntemplate <MaskMode MASK_MODE, PosEncodingMode POS_ENCODING_MODE, uint32_t NUM_FRAGS_Q,\n uint32_t NUM_FRAGS_D, uint32_t NUM_FRAGS_KV, uint32_t NUM_WARPS_Q, uint32_t NUM_WARPS_KV,\n typename DTypeQKAccum, typename AttentionVariant>\n__global__\n__launch_bounds__(NUM_WARPS_Q* NUM_WARPS_KV* WARP_SIZE) void BatchPrefillWithPagedKVCacheKernel(\n const uint_fastdiv group_size,\n const __grid_constant__ typename AttentionVariant::ParamsT params) {\n using DTypeQ = typename AttentionVariant::DTypeQ;\n#if (__CUDA_ARCH__ < 800)\n if constexpr (std::is_same_v<DTypeQ, nv_bfloat16>) {\n FLASHINFER_RUNTIME_ASSERT(\"Prefill kernels do not support bf16 on sm75.\");\n } else {\n#endif\n using DTypeKV = typename AttentionVariant::DTypeKV;\n using DTypeO = typename AttentionVariant::DTypeO;\n using IdType = typename AttentionVariant::IdType;\n IdType* request_indices = params.request_indices;\n IdType* qo_tile_indices = params.qo_tile_indices;\n IdType* kv_tile_indices = params.kv_tile_indices;\n DTypeQ* q = params.q;\n IdType* q_indptr = params.q_indptr;\n IdType* q_offset = params.q_offset;\n IdType* o_indptr = params.o_indptr;\n DTypeO* o = params.o;\n float* lse = params.lse;\n bool* block_valid_mask = params.block_valid_mask;\n const paged_kv_t<DTypeKV, IdType>& paged_kv = params.paged_kv;\n const bool partition_kv = params.partition_kv;\n const int32_t maybe_window_left = params.window_left;\n\n static_assert(sizeof(DTypeQ) == 2);\n static_assert(sizeof(DTypeO) == 2);\n auto block = cg::this_thread_block();\n const uint32_t kv_chunk_size = *(params.kv_chunk_size_ptr);\n\n const uint32_t bx = blockIdx.x, lane_idx = threadIdx.x,\n warp_idx = get_warp_idx<NUM_WARPS_Q, NUM_WARPS_KV>(), kv_head_idx = blockIdx.z;\n if (block_valid_mask && !block_valid_mask[bx]) {\n return;\n }\n const uint32_t num_kv_heads = gridDim.z, num_qo_heads = num_kv_heads * group_size;\n\n const uint32_t request_idx = request_indices[bx], qo_tile_idx = qo_tile_indices[bx],\n kv_tile_idx = kv_tile_indices[bx];\n constexpr uint32_t num_rows_per_cta = NUM_FRAGS_Q * NUM_WARPS_Q * 16;\n extern __shared__ uint8_t smem[];\n AttentionVariant variant(params, /*batch_idx=*/request_idx, smem);\n const uint32_t qo_len = variant.qo_len, kv_len = variant.kv_len,\n window_left = variant.window_left;\n const uint32_t kv_len_safe = kv_len > 0 ? kv_len : 1;\n const uint32_t max_chunk_size = partition_kv ? kv_chunk_size : kv_len;\n const uint32_t chunk_start = partition_kv ? kv_tile_idx * max_chunk_size : 0;\n const uint32_t chunk_end =\n partition_kv ? min((kv_tile_idx + 1) * max_chunk_size, kv_len) : kv_len;\n const uint32_t chunk_size = chunk_end - chunk_start;\n const uint32_t qo_upper_bound =\n min(qo_len, ceil_div((qo_tile_idx + 1) * num_rows_per_cta, group_size));\n\n constexpr uint32_t head_dim = NUM_FRAGS_D * 16;\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<DTypeKV>();\n constexpr uint32_t channel_size_128b_out = head_dim / num_elems_per_128b<DTypeO>();\n\n DTypeQKAccum s_frag[NUM_FRAGS_Q][NUM_FRAGS_KV][8];\n float o_frag[NUM_FRAGS_Q][NUM_FRAGS_D][8];\n DTypeQKAccum m[NUM_FRAGS_Q][2];\n float d[NUM_FRAGS_Q][2];\n float rope_freq[NUM_FRAGS_D / 2][4];\n\n if constexpr (POS_ENCODING_MODE == PosEncodingMode::kRoPELlama) {\n const float log2_rope_rcp_scale = params.log2_rope_rcp_scale;\n const float log2_rope_rcp_theta = params.log2_rope_rcp_theta;\n init_rope_freq<NUM_FRAGS_D>(rope_freq, log2_rope_rcp_scale, log2_rope_rcp_theta);\n }\n init_states<NUM_FRAGS_Q, NUM_FRAGS_D>(variant, o_frag, m, d);\n\n const uint32_t qo_packed_idx_base =\n (qo_tile_idx * NUM_WARPS_Q + get_warp_idx_q<NUM_WARPS_Q, NUM_WARPS_KV>()) * NUM_FRAGS_Q *\n 16;\n const uint32_t q_stride_n = params.q_stride_n, q_stride_h = params.q_stride_h;\n constexpr SwizzleMode swizzle_mode_q = SwizzleMode::k128B;\n smem_t<swizzle_mode_q> qo_smem(smem);\n DTypeQ* q_ptr_base = q + get_elem_offset_impl(q_indptr[request_idx], kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeQ>(),\n q_stride_n, q_stride_h);\n DTypeO* o_ptr_base =\n partition_kv ? o + kv_tile_idx * num_qo_heads * head_dim +\n get_elem_offset_impl(o_indptr[request_idx], kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeO>(),\n num_qo_heads * head_dim, head_dim)\n : o + get_elem_offset_impl(o_indptr[request_idx], kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeO>(),\n num_qo_heads * head_dim, head_dim);\n uint32_t q_smem_offset_r = qo_smem.get_permuted_offset<channel_size_128b_q>(\n get_warp_idx_q<NUM_WARPS_Q, NUM_WARPS_KV>() * NUM_FRAGS_Q * 16 + lane_idx % 16,\n lane_idx / 16);\n\n load_q_global_smem<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_Q, NUM_FRAGS_D>(\n qo_packed_idx_base, qo_upper_bound, q_ptr_base, q_stride_n, q_stride_h, group_size,\n &qo_smem);\n\n cp_async::commit_group();\n cp_async::wait_group<0>();\n block.sync();\n\n if constexpr (POS_ENCODING_MODE == PosEncodingMode::kRoPELlama) {\n if (q_offset == nullptr) {\n q_smem_inplace_apply_rotary<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_Q, NUM_FRAGS_D,\n swizzle_mode_q, DTypeQ>(\n qo_packed_idx_base, qo_len, kv_len, group_size, &qo_smem, &q_smem_offset_r, rope_freq);\n } else {\n q_smem_inplace_apply_rotary_with_pos<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_Q, NUM_FRAGS_D,\n swizzle_mode_q, DTypeQ>(\n qo_packed_idx_base, q_offset + q_indptr[request_idx], &qo_smem, group_size,\n &q_smem_offset_r, rope_freq);\n }\n block.sync();\n }\n q_smem_inplace_transform<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_Q, NUM_FRAGS_D, swizzle_mode_q>(\n params, variant, &qo_smem);\n\n constexpr SwizzleMode swizzle_mode_kv =\n (sizeof(DTypeKV) == 1 && head_dim == 64) ? SwizzleMode::k64B : SwizzleMode::k128B;\n constexpr uint32_t kv_frag_rows = swizzle_mode_kv == SwizzleMode::k128B ? 4 : 8;\n constexpr uint32_t kv_frag_cols = swizzle_mode_kv == SwizzleMode::k128B ? 8 : 4;\n smem_t<swizzle_mode_kv> k_smem(smem +\n (NUM_WARPS_Q * NUM_FRAGS_Q * sizeof(DTypeQ)) * 16 * head_dim),\n v_smem(smem + (NUM_WARPS_Q * NUM_FRAGS_Q * sizeof(DTypeQ) +\n NUM_WARPS_KV * NUM_FRAGS_KV * sizeof(DTypeKV)) *\n 16 * head_dim);\n size_t kv_offset[NUM_FRAGS_KV * (swizzle_mode_kv == SwizzleMode::k128B ? 4 : 2) / NUM_WARPS_Q];\n\n uint32_t k_smem_offset_r = k_smem.get_permuted_offset<channel_size_128b_kv>(\n get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>() * NUM_FRAGS_KV * 16 +\n 8 * (lane_idx / 16) + lane_idx % 8,\n (lane_idx % 16) / 8),\n v_smem_offset_r = v_smem.get_permuted_offset<channel_size_128b_kv>(\n get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>() * NUM_FRAGS_KV * 16 + lane_idx % 16,\n lane_idx / 16),\n kv_smem_offset_w = k_smem.get_permuted_offset<channel_size_128b_kv>(\n warp_idx * kv_frag_rows + lane_idx / kv_frag_cols, lane_idx % kv_frag_cols);\n const IdType last_indptr = paged_kv.indptr[paged_kv.batch_size];\n\n uint32_t packed_page_iter_base =\n paged_kv.indptr[request_idx] * paged_kv.page_size + chunk_start;\n#pragma unroll\n for (uint32_t i = 0;\n i < NUM_FRAGS_KV * (swizzle_mode_kv == SwizzleMode::k128B ? 4 : 2) / NUM_WARPS_Q; ++i) {\n uint32_t page_iter, entry_idx;\n paged_kv.page_size.divmod(packed_page_iter_base + warp_idx * kv_frag_rows +\n lane_idx / kv_frag_cols +\n kv_frag_rows * NUM_WARPS_Q * NUM_WARPS_KV * i,\n page_iter, entry_idx);\n kv_offset[i] = paged_kv.protective_get_kv_offset(\n page_iter, kv_head_idx, entry_idx,\n (lane_idx % kv_frag_cols) * num_elems_per_128b<DTypeKV>(), last_indptr);\n }\n page_produce_kv<false, NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_D, NUM_FRAGS_KV>(\n k_smem, &kv_smem_offset_w, paged_kv, 0, kv_offset, chunk_size);\n cp_async::commit_group();\n page_produce_kv<true, NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_D, NUM_FRAGS_KV>(\n v_smem, &kv_smem_offset_w, paged_kv, 0, kv_offset, chunk_size);\n cp_async::commit_group();\n\n const uint32_t num_iterations = ceil_div(\n (MASK_MODE == MaskMode::kCausal\n ? min(chunk_size,\n sub_if_greater_or_zero(\n kv_len - qo_len + ((qo_tile_idx + 1) * num_rows_per_cta) / group_size,\n chunk_start))\n : chunk_size),\n 16 * NUM_WARPS_KV * NUM_FRAGS_KV);\n\n const uint32_t window_iteration =\n ceil_div(sub_if_greater_or_zero(kv_len + (qo_tile_idx + 1) * num_rows_per_cta,\n qo_len + window_left + chunk_start),\n (16 * NUM_WARPS_KV * NUM_FRAGS_KV));\n\n const uint32_t mask_iteration =\n (MASK_MODE == MaskMode::kCausal\n ? min(chunk_size, sub_if_greater_or_zero(\n kv_len + (qo_tile_idx * num_rows_per_cta) / group_size - qo_len,\n chunk_start))\n : chunk_size) /\n (16 * NUM_WARPS_KV * NUM_FRAGS_KV);\n\n#pragma unroll 1\n for (uint32_t iter = 0; iter < num_iterations; ++iter) {\n packed_page_iter_base += 16 * NUM_WARPS_KV * NUM_FRAGS_KV;\n#pragma unroll\n for (uint32_t i = 0;\n i < NUM_FRAGS_KV * (swizzle_mode_kv == SwizzleMode::k128B ? 4 : 2) / NUM_WARPS_Q; ++i) {\n uint32_t page_iter, entry_idx;\n paged_kv.page_size.divmod(packed_page_iter_base + warp_idx * kv_frag_rows +\n lane_idx / kv_frag_cols +\n kv_frag_rows * NUM_WARPS_Q * NUM_WARPS_KV * i,\n page_iter, entry_idx);\n kv_offset[i] = paged_kv.protective_get_kv_offset(\n page_iter, kv_head_idx, entry_idx,\n (lane_idx % kv_frag_cols) * num_elems_per_128b<DTypeKV>(), last_indptr);\n }\n cp_async::wait_group<1>();\n block.sync();\n\n if constexpr (POS_ENCODING_MODE == PosEncodingMode::kRoPELlama) {\n k_smem_inplace_apply_rotary<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_D, NUM_FRAGS_KV,\n swizzle_mode_kv, DTypeKV>(\n (paged_kv.rope_pos_offset == nullptr ? 0 : paged_kv.rope_pos_offset[request_idx]) +\n chunk_start + iter * 16 * NUM_WARPS_KV * NUM_FRAGS_KV,\n &k_smem, &k_smem_offset_r, rope_freq);\n block.sync();\n }\n\n // compute attention score\n compute_qk<NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV, swizzle_mode_q, swizzle_mode_kv, DTypeQ,\n DTypeKV>(&qo_smem, &q_smem_offset_r, &k_smem, &k_smem_offset_r, s_frag);\n\n logits_transform<NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV>(\n params, variant, /*batch_idx=*/request_idx, qo_packed_idx_base,\n chunk_start + (iter * NUM_WARPS_KV + get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>()) *\n NUM_FRAGS_KV * 16,\n qo_len, kv_len, group_size, s_frag);\n\n // apply mask\n if (MASK_MODE == MaskMode::kCustom || (iter >= mask_iteration || iter < window_iteration)) {\n logits_mask<MASK_MODE, NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV>(\n params, variant, /*batch_idx=*/request_idx, qo_packed_idx_base,\n chunk_start + (iter * NUM_WARPS_KV + get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>()) *\n NUM_FRAGS_KV * 16,\n qo_len, kv_len, chunk_end, group_size, s_frag);\n }\n\n // compute m,d states in online softmax\n update_mdo_states<NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV>(variant, s_frag, o_frag, m, d);\n\n block.sync();\n page_produce_kv<false, NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_D, NUM_FRAGS_KV>(\n k_smem, &kv_smem_offset_w, paged_kv, (iter + 1) * 16 * NUM_WARPS_KV * NUM_FRAGS_KV,\n kv_offset, chunk_size);\n cp_async::commit_group();\n cp_async::wait_group<1>();\n block.sync();\n\n // compute sfm*v\n compute_sfm_v<NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV, swizzle_mode_kv, DTypeQ, DTypeKV>(\n variant, &v_smem, &v_smem_offset_r, s_frag, o_frag, d);\n\n block.sync();\n page_produce_kv<true, NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_D, NUM_FRAGS_KV>(\n v_smem, &kv_smem_offset_w, paged_kv, (iter + 1) * 16 * NUM_WARPS_KV * NUM_FRAGS_KV,\n kv_offset, chunk_size);\n cp_async::commit_group();\n }\n cp_async::wait_group<0>();\n block.sync();\n\n // threadblock synchronization\n threadblock_sync_mdo_states<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_Q, NUM_FRAGS_D, DTypeQKAccum>(\n variant, o_frag, (float*)smem, m, d, warp_idx, lane_idx);\n\n // normalize d\n normalize_d<NUM_FRAGS_Q, NUM_FRAGS_D>(variant, o_frag, m, d);\n\n const uint32_t num_kv_chunks = (kv_len_safe + kv_chunk_size - 1) / kv_chunk_size;\n\n // write_back\n write_o_reg_gmem<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_Q, NUM_FRAGS_D>(\n o_frag, &qo_smem, o_ptr_base, qo_packed_idx_base, qo_len,\n /*o_stride_n=*/\n partition_kv ? num_qo_heads * head_dim * num_kv_chunks : num_qo_heads * head_dim,\n /*o_stride_h=*/head_dim, group_size);\n\n // write lse\n if constexpr (variant.use_softmax) {\n if (lse != nullptr) {\n if (get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>() == 0) {\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n uint32_t q, r;\n group_size.divmod(qo_packed_idx_base + lane_idx / 4 + j * 8 + fq * 16, q, r);\n const uint32_t qo_head_idx = kv_head_idx * group_size + r;\n const uint32_t qo_idx = q;\n if (qo_idx < qo_upper_bound) {\n if (partition_kv) {\n lse[(o_indptr[request_idx] + qo_idx * num_kv_chunks + kv_tile_idx) *\n num_qo_heads +\n qo_head_idx] = math::ptx_log2(d[fq][j]) + float(m[fq][j]);\n } else {\n lse[(o_indptr[request_idx] + qo_idx) * num_qo_heads + qo_head_idx] =\n math::ptx_log2(d[fq][j]) + float(m[fq][j]);\n }\n }\n }\n }\n }\n }\n }\n#if (__CUDA_ARCH__ < 800)\n }\n#endif\n}\n\ntemplate <uint32_t CTA_TILE_Q, uint32_t HEAD_DIM, PosEncodingMode POS_ENCODING_MODE,\n bool ALLOW_FP16_QK_REDUCTION, MaskMode MASK_MODE, typename AttentionVariant>\ncudaError_t BatchPrefillWithRaggedKVCacheDispatched(typename AttentionVariant::ParamsT params,\n typename AttentionVariant::DTypeO* tmp_v,\n float* tmp_s, cudaStream_t stream) {\n using DTypeQ = typename AttentionVariant::DTypeQ;\n using DTypeKV = typename AttentionVariant::DTypeKV;\n const uint32_t padded_batch_size = params.padded_batch_size;\n const uint32_t num_qo_heads = params.num_qo_heads;\n const uint32_t num_kv_heads = params.num_kv_heads;\n const uint_fastdiv group_size_fastdiv(num_qo_heads / num_kv_heads);\n const uint32_t total_num_rows = params.total_num_rows;\n constexpr uint32_t NUM_FRAGS_Q = get_num_frags_q(CTA_TILE_Q);\n constexpr uint32_t NUM_WARPS_Q = get_num_warps_q(CTA_TILE_Q);\n constexpr uint32_t NUM_WARPS_KV = get_num_warps_kv(CTA_TILE_Q);\n\n if (padded_batch_size == 0) {\n // No request, skip\n // this won't happen in CUDAGraph mode because we fixed the padded_batch_size\n return cudaSuccess;\n }\n\n dim3 nblks(padded_batch_size, 1, num_kv_heads);\n dim3 nthrs(32, NUM_WARPS_Q, NUM_WARPS_KV);\n constexpr uint32_t NUM_FRAGS_D = HEAD_DIM / 16;\n using DTypeQKAccum =\n typename std::conditional<ALLOW_FP16_QK_REDUCTION && std::is_same_v<DTypeQ, half>, half,\n float>::type;\n\n int dev_id = 0;\n FLASHINFER_CUDA_CALL(cudaGetDevice(&dev_id));\n int max_smem_per_sm = 0;\n FLASHINFER_CUDA_CALL(cudaDeviceGetAttribute(&max_smem_per_sm,\n cudaDevAttrMaxSharedMemoryPerMultiprocessor, dev_id));\n // we expect each sm execute two threadblocks\n // TODO(Zihao): fix the following computation\n const int num_ctas_per_sm = max_smem_per_sm > (16 * HEAD_DIM * sizeof(DTypeQ) * 16) ? 2 : 1;\n const int max_smem_per_threadblock = max_smem_per_sm / num_ctas_per_sm;\n\n const uint32_t max_num_frags_kv_reg =\n (HEAD_DIM >= 128 && NUM_FRAGS_Q == 2 && POS_ENCODING_MODE == PosEncodingMode::kRoPELlama &&\n !ALLOW_FP16_QK_REDUCTION)\n ? 2\n : (8 / NUM_FRAGS_Q);\n // TODO(Zihao): fix the following computation\n const uint32_t max_num_frags_kv_smem =\n (max_smem_per_threadblock / (16 * HEAD_DIM * sizeof(DTypeQ)) - NUM_FRAGS_Q * NUM_WARPS_Q) /\n (2 * NUM_WARPS_KV);\n\n DISPATCH_NUM_FRAGS_KV(min(max_num_frags_kv_smem, max_num_frags_kv_reg), NUM_FRAGS_KV, {\n if constexpr (is_invalid_configuration<POS_ENCODING_MODE, DTypeKV, DTypeQKAccum>(\n NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV, NUM_WARPS_Q, NUM_WARPS_KV)) {\n // Invalid configuration, skip\n std::ostringstream err_msg;\n err_msg << \"FlashInfer Internal Error: Invalid configuration : NUM_FRAGS_Q=\" << NUM_FRAGS_Q\n << \" NUM_FRAGS_D=\" << NUM_FRAGS_D << \" NUM_FRAGS_KV=\" << NUM_FRAGS_KV\n << \" NUM_WARPS_Q=\" << NUM_WARPS_Q << \" NUM_WARPS_KV=\" << NUM_WARPS_KV\n << \" please create an issue (https://github.com/flashinfer-ai/flashinfer/issues)\"\n \" and report the issue to the developers.\";\n throw std::invalid_argument(err_msg.str());\n } else {\n // TODO(Zihao): fix the following computation\n uint32_t smem_size = (NUM_FRAGS_Q * NUM_WARPS_Q * sizeof(DTypeQ) +\n NUM_FRAGS_KV * NUM_WARPS_KV * 2 * sizeof(DTypeQ)) *\n 16 * HEAD_DIM;\n auto kernel =\n BatchPrefillWithRaggedKVCacheKernel<MASK_MODE, POS_ENCODING_MODE, NUM_FRAGS_Q,\n NUM_FRAGS_D, NUM_FRAGS_KV, NUM_WARPS_Q, NUM_WARPS_KV,\n DTypeQKAccum, AttentionVariant>;\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n if (tmp_v == nullptr) {\n // do not partition kv\n params.partition_kv = false;\n void* args[] = {(void*)&group_size_fastdiv, (void*)¶ms};\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n } else {\n // partition kv\n params.partition_kv = true;\n auto o = params.o;\n auto lse = params.lse;\n params.o = tmp_v;\n params.lse = tmp_s;\n void* args[] = {(void*)&group_size_fastdiv, (void*)¶ms};\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n if constexpr (AttentionVariant::use_softmax) {\n FLASHINFER_CUDA_CALL(VariableLengthMergeStates(tmp_v, tmp_s, params.merge_indptr, o, lse,\n total_num_rows, num_qo_heads, HEAD_DIM,\n stream));\n } else {\n FLASHINFER_CUDA_CALL(VariableLengthAttentionSum(\n tmp_v, params.merge_indptr, o, total_num_rows, num_qo_heads, HEAD_DIM, stream));\n }\n }\n }\n });\n return cudaSuccess;\n}\n\ntemplate <uint32_t CTA_TILE_Q, uint32_t HEAD_DIM, PosEncodingMode POS_ENCODING_MODE,\n bool ALLOW_FP16_QK_REDUCTION, MaskMode MASK_MODE, typename AttentionVariant>\ncudaError_t BatchPrefillWithPagedKVCacheDispatched(typename AttentionVariant::ParamsT params,\n typename AttentionVariant::DTypeO* tmp_v,\n float* tmp_s, cudaStream_t stream) {\n using DTypeQ = typename AttentionVariant::DTypeQ;\n using DTypeKV = typename AttentionVariant::DTypeKV;\n const uint32_t padded_batch_size = params.padded_batch_size;\n const uint32_t num_qo_heads = params.num_qo_heads;\n const uint32_t num_kv_heads = params.paged_kv.num_heads;\n const uint_fastdiv group_size_fastdiv(num_qo_heads / num_kv_heads);\n const uint32_t total_num_rows = params.total_num_rows;\n constexpr uint32_t NUM_FRAGS_Q = get_num_frags_q(CTA_TILE_Q);\n constexpr uint32_t NUM_WARPS_Q = get_num_warps_q(CTA_TILE_Q);\n constexpr uint32_t NUM_WARPS_KV = get_num_warps_kv(CTA_TILE_Q);\n\n if (padded_batch_size == 0) {\n // No request, skip\n // this won't happen in CUDAGraph mode because we fixed the padded_batch_size\n return cudaSuccess;\n }\n\n dim3 nblks(padded_batch_size, 1, num_kv_heads);\n dim3 nthrs(32, NUM_WARPS_Q, NUM_WARPS_KV);\n\n constexpr uint32_t NUM_FRAGS_D = HEAD_DIM / 16;\n using DTypeQKAccum =\n typename std::conditional<ALLOW_FP16_QK_REDUCTION && std::is_same_v<DTypeQ, half>, half,\n float>::type;\n\n int dev_id = 0;\n FLASHINFER_CUDA_CALL(cudaGetDevice(&dev_id));\n int max_smem_per_sm = 0;\n FLASHINFER_CUDA_CALL(cudaDeviceGetAttribute(&max_smem_per_sm,\n cudaDevAttrMaxSharedMemoryPerMultiprocessor, dev_id));\n // we expect each sm execute two threadblocks\n // TODO(Zihao): fix the following computation\n const int num_ctas_per_sm = max_smem_per_sm > (16 * HEAD_DIM * sizeof(DTypeQ) * 16) ? 2 : 1;\n const int max_smem_per_threadblock = max_smem_per_sm / num_ctas_per_sm;\n\n const uint32_t max_num_frags_kv_reg =\n (HEAD_DIM >= 128 && NUM_FRAGS_Q == 2 && POS_ENCODING_MODE == PosEncodingMode::kRoPELlama &&\n !ALLOW_FP16_QK_REDUCTION)\n ? 2\n : (8 / NUM_FRAGS_Q);\n // TODO(Zihao): fix the following computation\n const uint32_t max_num_frags_kv_smem =\n (max_smem_per_threadblock / (16 * HEAD_DIM * sizeof(DTypeQ)) - NUM_FRAGS_Q * NUM_WARPS_Q) /\n (2 * NUM_WARPS_KV);\n\n DISPATCH_NUM_FRAGS_KV(min(max_num_frags_kv_smem, max_num_frags_kv_reg), NUM_FRAGS_KV, {\n if constexpr (is_invalid_configuration<POS_ENCODING_MODE, DTypeKV, DTypeQKAccum>(\n NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV, NUM_WARPS_Q, NUM_WARPS_KV)) {\n // Invalid configuration, skip\n std::ostringstream err_msg;\n err_msg << \"FlashInfer Internal Error: Invalid configuration : NUM_FRAGS_Q=\" << NUM_FRAGS_Q\n << \" NUM_FRAGS_D=\" << NUM_FRAGS_D << \" NUM_FRAGS_KV=\" << NUM_FRAGS_KV\n << \" NUM_WARPS_Q=\" << NUM_WARPS_Q << \" NUM_WARPS_KV=\" << NUM_WARPS_KV\n << \" please create an issue (https://github.com/flashinfer-ai/flashinfer/issues)\"\n \" and report the issue to the developers.\";\n throw std::invalid_argument(err_msg.str());\n } else {\n // TODO(Zihao): fix the following computation\n uint32_t smem_size = (NUM_FRAGS_Q * NUM_WARPS_Q * sizeof(DTypeQ) +\n NUM_FRAGS_KV * NUM_WARPS_KV * 2 * sizeof(DTypeQ)) *\n 16 * HEAD_DIM;\n auto kernel =\n BatchPrefillWithPagedKVCacheKernel<MASK_MODE, POS_ENCODING_MODE, NUM_FRAGS_Q, NUM_FRAGS_D,\n NUM_FRAGS_KV, NUM_WARPS_Q, NUM_WARPS_KV, DTypeQKAccum,\n AttentionVariant>;\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n if (tmp_v == nullptr) {\n // do not partition kv\n params.partition_kv = false;\n void* args[] = {(void*)&group_size_fastdiv, (void*)¶ms};\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n } else {\n params.partition_kv = true;\n auto o = params.o;\n auto lse = params.lse;\n params.o = tmp_v;\n params.lse = tmp_s;\n void* args[] = {(void*)&group_size_fastdiv, (void*)¶ms};\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n if constexpr (AttentionVariant::use_softmax) {\n FLASHINFER_CUDA_CALL(VariableLengthMergeStates(tmp_v, tmp_s, params.merge_indptr, o, lse,\n total_num_rows, num_qo_heads, HEAD_DIM,\n stream));\n } else {\n FLASHINFER_CUDA_CALL(VariableLengthAttentionSum(\n tmp_v, params.merge_indptr, o, total_num_rows, num_qo_heads, HEAD_DIM, stream));\n }\n }\n }\n });\n return cudaSuccess;\n}\n\n} // namespace flashinfer\n\n#endif // FLASHINFER_PREFILL_CUH_\n"},"diff":{"kind":"string","value":"--- include/flashinfer/attention/prefill.cuh\n+++ include/flashinfer/attention/prefill.cuh\n@@ -623,18 +623,25 @@\n const uint_fastdiv group_size,\n DTypeQKAccum (*s_frag)[NUM_FRAGS_KV][8]) {\n const uint32_t lane_idx = threadIdx.x, kv_head_idx = blockIdx.z;\n+ uint32_t q[NUM_FRAGS_Q][2], r[NUM_FRAGS_Q][2];\n #pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n #pragma unroll\n+ for (uint32_t j = 0; j < 2; ++j) {\n+ group_size.divmod(qo_packed_idx_base + fq * 16 + lane_idx / 4 + 8 * j, q[fq][j], r[fq][j]);\n+ }\n+ }\n+\n+#pragma unroll\n+ for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n+#pragma unroll\n for (uint32_t fkv = 0; fkv < NUM_FRAGS_KV; ++fkv) {\n #pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n- uint32_t q, r;\n- group_size.divmod(qo_packed_idx_base + fq * 16 + lane_idx / 4 + 8 * ((reg_id % 4) / 2), q,\n- r);\n- const uint32_t q_idx = q, kv_idx = kv_idx_base + fkv * 16 + 2 * (lane_idx % 4) +\n- 8 * (reg_id / 4) + reg_id % 2;\n- const uint32_t qo_head_idx = kv_head_idx * group_size + r;\n+ const uint32_t q_idx = q[fq][(reg_id % 4) / 2], kv_idx = kv_idx_base + fkv * 16 +\n+ 2 * (lane_idx % 4) +\n+ 8 * (reg_id / 4) + reg_id % 2;\n+ const uint32_t qo_head_idx = kv_head_idx * group_size + r[fq][(reg_id % 4) / 2];\n s_frag[fq][fkv][reg_id] = variant.LogitsTransform(\n params, s_frag[fq][fkv][reg_id], batch_idx, q_idx, kv_idx, qo_head_idx, kv_head_idx);\n }\n@@ -652,18 +659,25 @@\n const uint_fastdiv group_size,\n DTypeQKAccum (*s_frag)[NUM_FRAGS_KV][8]) {\n const uint32_t lane_idx = threadIdx.x, kv_head_idx = blockIdx.z;\n+ uint32_t q[NUM_FRAGS_Q][2], r[NUM_FRAGS_Q][2];\n #pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n #pragma unroll\n+ for (uint32_t j = 0; j < 2; ++j) {\n+ group_size.divmod(qo_packed_idx_base + fq * 16 + lane_idx / 4 + 8 * j, q[fq][j], r[fq][j]);\n+ }\n+ }\n+\n+#pragma unroll\n+ for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n+#pragma unroll\n for (uint32_t fkv = 0; fkv < NUM_FRAGS_KV; ++fkv) {\n #pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n- uint32_t q, r;\n- group_size.divmod(qo_packed_idx_base + fq * 16 + lane_idx / 4 + 8 * ((reg_id % 4) / 2), q,\n- r);\n- const uint32_t q_idx = q, kv_idx = kv_idx_base + fkv * 16 + 2 * (lane_idx % 4) +\n- 8 * (reg_id / 4) + reg_id % 2;\n- const uint32_t qo_head_idx = kv_head_idx * group_size + r;\n+ const uint32_t q_idx = q[fq][(reg_id % 4) / 2], kv_idx = kv_idx_base + fkv * 16 +\n+ 2 * (lane_idx % 4) +\n+ 8 * (reg_id / 4) + reg_id % 2;\n+ const uint32_t qo_head_idx = kv_head_idx * group_size + r[fq][(reg_id % 4) / 2];\n const bool mask =\n (!(MASK_MODE == MaskMode::kCausal\n ? (kv_idx + qo_len > kv_len + q_idx || (kv_idx >= chunk_end))"},"lines_added":{"kind":"number","value":26,"string":"26"},"lines_removed":{"kind":"number","value":12,"string":"12"},"files_in_commit":{"kind":"number","value":1,"string":"1"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["A100"],"string":"[\n \"A100\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/prefill.cuh).\n\nGoal: perf: fix prefill kernel performance degradation (step 1)\nTarget hardware: A100\nTarget models: unspecified\n\nCurrent file:\n```cuda\n/*\n * Copyright (c) 2023 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_PREFILL_CUH_\n#define FLASHINFER_PREFILL_CUH_\n#include <cooperative_groups.h>\n#include <cuda_bf16.h>\n#include <cuda_fp16.h>\n#include <cuda_fp8.h>\n#include <cuda_runtime.h>\n\n#include \"../cp_async.cuh\"\n#include \"../fastdiv.cuh\"\n#include \"../frag_layout_swizzle.cuh\"\n#include \"../layout.cuh\"\n#include \"../math.cuh\"\n#include \"../mma.cuh\"\n#include \"../page.cuh\"\n#include \"../permuted_smem.cuh\"\n#include \"../pos_enc.cuh\"\n#include \"../utils.cuh\"\n#include \"cascade.cuh\"\n#include \"mask.cuh\"\n#include \"variants.cuh\"\n\nnamespace flashinfer {\n\nnamespace cg = cooperative_groups;\nusing cp_async::SharedMemFillMode;\nusing mma::MMAMode;\n\nconstexpr uint32_t WARP_SIZE = 32;\n\nconstexpr uint32_t get_num_warps_q(const uint32_t cta_tile_q) {\n if (cta_tile_q > 16) {\n return 4;\n } else {\n return 1;\n }\n}\n\nconstexpr uint32_t get_num_warps_kv(const uint32_t cta_tile_kv) {\n return 4 / get_num_warps_q(cta_tile_kv);\n}\n\nconstexpr uint32_t get_num_frags_q(const uint32_t cta_tile_q) {\n if (cta_tile_q > 64) {\n return 2;\n } else {\n return 1;\n }\n}\n\nnamespace {\n\ntemplate <PosEncodingMode POS_ENCODING_MODE, typename DTypeKV, typename DTypeQKAccum>\nconstexpr bool is_invalid_configuration(uint32_t NUM_FRAGS_Q, uint32_t NUM_FRAGS_D,\n uint32_t NUM_FRAGS_KV, uint32_t NUM_WARPS_Q,\n uint32_t NUM_WARPS_KV) {\n return ((NUM_FRAGS_D < 4) || (NUM_FRAGS_D == 4 && NUM_FRAGS_KV % 2 == 1) ||\n (NUM_FRAGS_D > 4 && NUM_FRAGS_D % (2 * NUM_WARPS_Q) != 0) ||\n (NUM_FRAGS_Q * (8 * NUM_FRAGS_D + 2 * sizeof(DTypeQKAccum) * NUM_FRAGS_KV) >= 256) ||\n (sizeof(DTypeKV) == 1 && NUM_FRAGS_KV * 2 % NUM_WARPS_Q != 0) ||\n (sizeof(DTypeKV) == 1 && POS_ENCODING_MODE == PosEncodingMode::kRoPELlama));\n}\n\ntemplate <uint32_t NUM_WARPS_Q, uint32_t NUM_WARPS_KV>\n__device__ __forceinline__ uint32_t get_warp_idx_q() {\n if constexpr (NUM_WARPS_Q == 1) {\n return 0;\n } else {\n return threadIdx.y;\n }\n}\n\ntemplate <uint32_t NUM_WARPS_Q, uint32_t NUM_WARPS_KV>\n__device__ __forceinline__ uint32_t get_warp_idx_kv() {\n if constexpr (NUM_WARPS_KV == 1) {\n return 0;\n } else {\n return threadIdx.z;\n }\n}\n\ntemplate <uint32_t NUM_WARPS_Q, uint32_t NUM_WARPS_KV>\n__device__ __forceinline__ uint32_t get_warp_idx() {\n return get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>() * NUM_WARPS_Q +\n get_warp_idx_q<NUM_WARPS_Q, NUM_WARPS_KV>();\n}\n\n/*!\n * \\brief Apply Llama style rotary embedding to two 16x16 fragments.\n * \\tparam T The data type of the input fragments.\n * \\param x_first_half First fragment x[offset:offset+16, j*16:(j+1)*16]\n * \\param x_second_half Second fragment x[offset:offset*16, j*16+d/2:(j+1)*16+d/2]\n * \\param rope_freq Rope frequency\n * \\param offset The offset of the first row in both fragments.\n * \\note The sin/cos computation is slow, especially for A100 GPUs which has low\n * non tensor-ops flops, will optimize in the future.\n */\ntemplate <typename T>\n__device__ __forceinline__ void k_frag_apply_llama_rope(T* x_first_half, T* x_second_half,\n const float* rope_freq,\n const uint32_t kv_offset) {\n static_assert(sizeof(T) == 2);\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n float cos, sin, tmp;\n // 0 1 | 2 3\n // ---------\n // 4 5 | 6 7\n uint32_t i = reg_id / 4, j = (reg_id % 4) / 2;\n __sincosf(float(kv_offset + 8 * i) * rope_freq[2 * j + reg_id % 2], &sin, &cos);\n tmp = x_first_half[reg_id];\n x_first_half[reg_id] = (tmp * cos - (float)x_second_half[reg_id] * sin);\n x_second_half[reg_id] = ((float)x_second_half[reg_id] * cos + tmp * sin);\n }\n}\n\ntemplate <typename T>\n__device__ __forceinline__ void q_frag_apply_llama_rope(T* x_first_half, T* x_second_half,\n const float* rope_freq,\n const uint32_t qo_packed_offset,\n const uint_fastdiv group_size) {\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n float cos, sin, tmp;\n // 0 1 | 4 5\n // ---------\n // 2 3 | 6 7\n uint32_t i = ((reg_id % 4) / 2), j = (reg_id / 4);\n __sincosf(float((qo_packed_offset + 8 * i) / group_size) * rope_freq[2 * j + reg_id % 2], &sin,\n &cos);\n tmp = x_first_half[reg_id];\n x_first_half[reg_id] = (tmp * cos - (float)x_second_half[reg_id] * sin);\n x_second_half[reg_id] = ((float)x_second_half[reg_id] * cos + tmp * sin);\n }\n}\n\ntemplate <typename T, typename IdType>\n__device__ __forceinline__ void q_frag_apply_llama_rope_with_pos(T* x_first_half, T* x_second_half,\n const float* rope_freq,\n const uint32_t qo_packed_offset,\n const uint_fastdiv group_size,\n const IdType* q_offset) {\n float pos[2] = {static_cast<float>(q_offset[qo_packed_offset / group_size]),\n static_cast<float>(q_offset[(qo_packed_offset + 8) / group_size])};\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n float cos, sin, tmp;\n // 0 1 | 4 5\n // ---------\n // 2 3 | 6 7\n uint32_t i = ((reg_id % 4) / 2), j = (reg_id / 4);\n __sincosf(pos[i] * rope_freq[2 * j + reg_id % 2], &sin, &cos);\n tmp = x_first_half[reg_id];\n x_first_half[reg_id] = (tmp * cos - (float)x_second_half[reg_id] * sin);\n x_second_half[reg_id] = ((float)x_second_half[reg_id] * cos + tmp * sin);\n }\n}\n\n/*!\n * \\brief Produce k/v fragments from global memory to shared memory.\n * \\tparam fill_mode The fill mode of the shared memory.\n * \\tparam NUM_FRAGS_D The number of fragments in y dimension.\n * \\tparam NUM_FRAGS_KV The number of fragments in z dimension.\n * \\tparam num_warps The number of warps in the threadblock.\n * \\tparam T The data type of the input tensor.\n * \\param smem The shared memory to store kv fragments.\n * \\param gptr The global memory pointer.\n * \\param kv_idx_base The base kv index.\n * \\param kv_len The length of kv tensor.\n */\ntemplate <SharedMemFillMode fill_mode, uint32_t NUM_WARPS_Q, uint32_t NUM_WARPS_KV,\n uint32_t NUM_FRAGS_D, uint32_t NUM_FRAGS_KV, SwizzleMode swizzle_mode, typename T>\n__device__ __forceinline__ void produce_kv(smem_t<swizzle_mode> smem, uint32_t* smem_offset,\n T** gptr, const uint32_t kv_stride_n,\n const uint32_t kv_idx_base, const uint32_t kv_len) {\n // NOTE(Zihao): for fp8, this function doesn't work for head_dim = 64 at the moment\n constexpr uint32_t head_dim = NUM_FRAGS_D * 16;\n constexpr uint32_t num_warps = NUM_WARPS_Q * NUM_WARPS_KV;\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<T>();\n const uint32_t warp_idx = get_warp_idx<NUM_WARPS_Q, NUM_WARPS_KV>(), lane_idx = threadIdx.x;\n\n if constexpr (swizzle_mode == SwizzleMode::k128B) {\n uint32_t kv_idx = kv_idx_base + warp_idx * 4 + lane_idx / 8;\n // NOTE(Zihao): NUM_FRAGS_KV * 4 / NUM_WARPS_Q = NUM_WARPS_KV * NUM_FRAGS_KV * 4 / num_warps\n static_assert(NUM_FRAGS_KV * 4 % NUM_WARPS_Q == 0);\n#pragma unroll\n for (uint32_t i = 0; i < NUM_FRAGS_KV * 4 / NUM_WARPS_Q; ++i) {\n#pragma unroll\n for (uint32_t j = 0; j < NUM_FRAGS_D / (8 / sizeof(T)); ++j) {\n smem.load_128b_async<fill_mode>(*smem_offset, *gptr, kv_idx < kv_len);\n *smem_offset = smem.template advance_offset_by_column<8>(*smem_offset, j);\n *gptr += 8 * num_elems_per_128b<T>();\n }\n kv_idx += num_warps * 4;\n *smem_offset =\n smem.template advance_offset_by_row<num_warps * 4, channel_size_128b_kv>(*smem_offset) -\n sizeof(T) * NUM_FRAGS_D;\n *gptr += num_warps * 4 * kv_stride_n - sizeof(T) * NUM_FRAGS_D * num_elems_per_128b<T>();\n }\n *smem_offset -= NUM_WARPS_KV * NUM_FRAGS_KV * 16 * channel_size_128b_kv;\n } else {\n uint32_t kv_idx = kv_idx_base + warp_idx * 8 + lane_idx / 4;\n // NOTE(Zihao): NUM_FRAGS_KV * 2 / NUM_WARPS_Q = NUM_WARPS_KV * NUM_FRAGS_KV * 2 / num_warps\n static_assert(NUM_FRAGS_KV * 2 % NUM_WARPS_Q == 0);\n#pragma unroll\n for (uint32_t i = 0; i < NUM_FRAGS_KV * 2 / NUM_WARPS_Q; ++i) {\n smem.load_128b_async<fill_mode>(*smem_offset, *gptr, kv_idx < kv_len);\n *smem_offset =\n smem.template advance_offset_by_row<num_warps * 8, channel_size_128b_kv>(*smem_offset);\n kv_idx += num_warps * 8;\n *gptr += num_warps * 8 * kv_stride_n;\n }\n *smem_offset -= NUM_WARPS_KV * NUM_FRAGS_KV * 16 * channel_size_128b_kv;\n }\n}\n\ntemplate <bool produce_v, uint32_t NUM_WARPS_Q, uint32_t NUM_WARPS_KV, uint32_t NUM_FRAGS_D,\n uint32_t NUM_FRAGS_KV, SwizzleMode swizzle_mode, typename DType, typename IdType>\n__device__ __forceinline__ void page_produce_kv(smem_t<swizzle_mode> smem, uint32_t* smem_offset,\n const paged_kv_t<DType, IdType>& paged_kv,\n const uint32_t kv_idx_base, const size_t* kv_offset,\n const uint32_t kv_len) {\n // NOTE(Zihao): for fp8, this function doesn't work for head_dim = 64 at the moment\n constexpr SharedMemFillMode fill_mode =\n produce_v ? SharedMemFillMode::kFillZero : SharedMemFillMode::kNoFill;\n constexpr uint32_t head_dim = NUM_FRAGS_D * 16;\n constexpr uint32_t num_warps = NUM_WARPS_Q * NUM_WARPS_KV;\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<DType>();\n const uint32_t warp_idx = get_warp_idx<NUM_WARPS_Q, NUM_WARPS_KV>(), lane_idx = threadIdx.x;\n if constexpr (swizzle_mode == SwizzleMode::k128B) {\n uint32_t kv_idx = kv_idx_base + warp_idx * 4 + lane_idx / 8;\n // NOTE(Zihao): NUM_FRAGS_KV * 4 / NUM_WARPS_Q = NUM_WARPS_KV * NUM_FRAGS_KV * 4 / num_warps\n static_assert(NUM_FRAGS_KV * 4 % NUM_WARPS_Q == 0);\n#pragma unroll\n for (uint32_t i = 0; i < NUM_FRAGS_KV * 4 / NUM_WARPS_Q; ++i) {\n DType* gptr = produce_v ? paged_kv.v_data + kv_offset[i] : paged_kv.k_data + kv_offset[i];\n#pragma unroll\n for (uint32_t j = 0; j < NUM_FRAGS_D / (8 / sizeof(DType)); ++j) {\n smem.load_128b_async<fill_mode>(*smem_offset, gptr, kv_idx < kv_len);\n *smem_offset = smem.template advance_offset_by_column<8>(*smem_offset, j);\n gptr += 8 * num_elems_per_128b<DType>();\n }\n kv_idx += num_warps * 4;\n *smem_offset =\n smem.template advance_offset_by_row<num_warps * 4, channel_size_128b_kv>(*smem_offset) -\n sizeof(DType) * NUM_FRAGS_D;\n }\n *smem_offset -= NUM_WARPS_KV * NUM_FRAGS_KV * 16 * channel_size_128b_kv;\n } else {\n uint32_t kv_idx = kv_idx_base + warp_idx * 8 + lane_idx / 4;\n // NOTE(Zihao): NUM_FRAGS_KV * 2 / NUM_WARPS_Q = NUM_WARPS_KV * NUM_FRAGS_KV * 2 / num_warps\n static_assert(NUM_FRAGS_KV * 2 % NUM_WARPS_Q == 0);\n#pragma unroll\n for (uint32_t i = 0; i < NUM_FRAGS_KV * 2 / NUM_WARPS_Q; ++i) {\n DType* gptr = produce_v ? paged_kv.v_data + kv_offset[i] : paged_kv.k_data + kv_offset[i];\n smem.load_128b_async<fill_mode>(*smem_offset, gptr, kv_idx < kv_len);\n kv_idx += num_warps * 8;\n *smem_offset =\n smem.template advance_offset_by_row<num_warps * 8, channel_size_128b_kv>(*smem_offset);\n }\n *smem_offset -= NUM_WARPS_KV * NUM_FRAGS_KV * 16 * channel_size_128b_kv;\n }\n}\n\ntemplate <uint32_t NUM_FRAGS_D>\n__device__ __forceinline__ void init_rope_freq(float (*rope_freq)[4],\n const float log2_rope_rcp_scale,\n const float log2_rope_rcp_theta) {\n constexpr uint32_t head_dim = NUM_FRAGS_D * 16;\n const uint32_t lane_idx = threadIdx.x;\n#pragma unroll\n for (uint32_t fd = 0; fd < NUM_FRAGS_D / 2; ++fd) {\n#pragma unroll\n for (uint32_t j = 0; j < 4; ++j) {\n rope_freq[fd][j] = math::ptx_exp2(\n log2_rope_rcp_scale +\n log2_rope_rcp_theta *\n float(2 * ((fd * 16 + (j / 2) * 8 + (lane_idx % 4) * 2 + (j % 2)) % (head_dim / 2))) /\n float(head_dim));\n }\n }\n}\n\ntemplate <uint32_t NUM_FRAGS_Q, uint32_t NUM_FRAGS_D, typename DTypeQKAccum,\n typename AttentionVariant>\n__device__ __forceinline__ void init_states(AttentionVariant variant,\n float (*o_frag)[NUM_FRAGS_D][8], DTypeQKAccum (*m)[2],\n float (*d)[2]) {\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t fd = 0; fd < NUM_FRAGS_D; ++fd) {\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n o_frag[fq][fd][reg_id] = 0.f;\n }\n }\n }\n\n if constexpr (variant.use_softmax) {\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n m[fq][j] = DTypeQKAccum(-math::inf);\n d[fq][j] = 1.f;\n }\n }\n }\n}\n\ntemplate <uint32_t NUM_WARPS_Q, uint32_t NUM_WARPS_KV, uint32_t NUM_FRAGS_Q, uint32_t NUM_FRAGS_D,\n SwizzleMode swizzle_mode, typename DTypeQ>\n__device__ __forceinline__ void load_q_global_smem(uint32_t packed_offset,\n const uint32_t qo_upper_bound,\n DTypeQ* q_ptr_base, const uint32_t q_stride_n,\n const uint32_t q_stride_h,\n const uint_fastdiv group_size,\n smem_t<swizzle_mode>* q_smem) {\n constexpr uint32_t head_dim = NUM_FRAGS_D * 16;\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n const uint32_t lane_idx = threadIdx.x, warp_idx_x = get_warp_idx_q<NUM_WARPS_Q, NUM_WARPS_KV>();\n\n if (get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>() == 0) {\n uint32_t q_smem_offset_w = q_smem->get_permuted_offset<channel_size_128b_q>(\n warp_idx_x * NUM_FRAGS_Q * 16 + lane_idx / 8, lane_idx % 8);\n\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t j = 0; j < 4; ++j) {\n uint32_t q, r;\n group_size.divmod(packed_offset + lane_idx / 8 + fq * 16 + j * 4, q, r);\n const uint32_t q_idx = q;\n DTypeQ* q_ptr = q_ptr_base + q * q_stride_n + r * q_stride_h;\n#pragma unroll\n for (uint32_t fdo = 0; fdo < NUM_FRAGS_D / 4; ++fdo) {\n // load q fragment from gmem to smem\n q_smem->load_128b_async<SharedMemFillMode::kNoFill>(q_smem_offset_w, q_ptr,\n q_idx < qo_upper_bound);\n q_smem_offset_w = q_smem->template advance_offset_by_column<8>(q_smem_offset_w, fdo);\n q_ptr += 8 * num_elems_per_128b<DTypeQ>();\n }\n q_smem_offset_w =\n q_smem->template advance_offset_by_row<4, channel_size_128b_q>(q_smem_offset_w) -\n 2 * NUM_FRAGS_D;\n }\n }\n }\n}\n\ntemplate <uint32_t NUM_WARPS_Q, uint32_t NUM_WARPS_KV, uint32_t NUM_FRAGS_Q, uint32_t NUM_FRAGS_D,\n SwizzleMode swizzle_mode, typename DTypeQ>\n__device__ __forceinline__ void q_smem_inplace_apply_rotary(\n const uint32_t q_packed_idx, const uint32_t qo_len, const uint32_t kv_len,\n const uint_fastdiv group_size, smem_t<swizzle_mode>* q_smem, uint32_t* q_smem_offset_r,\n float (*rope_freq)[4]) {\n if (get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>() == 0) {\n constexpr uint32_t head_dim = NUM_FRAGS_D * 16;\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n const uint32_t lane_idx = threadIdx.x;\n uint32_t q_frag_local[2][4];\n static_assert(NUM_FRAGS_D % 4 == 0, \"NUM_FRAGS_D must be a multiple of 4\");\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n uint32_t q_smem_offset_r_first_half = *q_smem_offset_r;\n#pragma unroll\n for (uint32_t fdi = 0; fdi < NUM_FRAGS_D / 2; ++fdi) {\n q_smem->ldmatrix_m8n8x4(q_smem_offset_r_first_half, q_frag_local[0]);\n uint32_t q_smem_offset_r_last_half =\n q_smem->template advance_offset_by_column<NUM_FRAGS_D>(q_smem_offset_r_first_half, 0);\n q_smem->ldmatrix_m8n8x4(q_smem_offset_r_last_half, q_frag_local[1]);\n q_frag_apply_llama_rope<DTypeQ>(\n (DTypeQ*)q_frag_local[0], (DTypeQ*)q_frag_local[1], rope_freq[fdi],\n q_packed_idx + kv_len * group_size - qo_len * group_size + fq * 16 + lane_idx / 4,\n group_size);\n q_smem->stmatrix_m8n8x4(q_smem_offset_r_last_half, q_frag_local[1]);\n q_smem->stmatrix_m8n8x4(q_smem_offset_r_first_half, q_frag_local[0]);\n q_smem_offset_r_first_half =\n q_smem->template advance_offset_by_column<2>(q_smem_offset_r_first_half, fdi);\n }\n *q_smem_offset_r += 16 * channel_size_128b_q;\n }\n *q_smem_offset_r -= NUM_FRAGS_Q * 16 * channel_size_128b_q;\n }\n}\n\ntemplate <uint32_t NUM_WARPS_Q, uint32_t NUM_WARPS_KV, uint32_t NUM_FRAGS_Q, uint32_t NUM_FRAGS_D,\n SwizzleMode swizzle_mode, typename DTypeQ, typename IdType>\n__device__ __forceinline__ void q_smem_inplace_apply_rotary_with_pos(\n const uint32_t q_packed_idx_base, const IdType* q_offset, smem_t<swizzle_mode>* q_smem,\n const uint_fastdiv group_size, uint32_t* q_smem_offset_r, float (*rope_freq)[4]) {\n if (get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>() == 0) {\n constexpr uint32_t head_dim = NUM_FRAGS_D * 16;\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n const uint32_t lane_idx = threadIdx.x;\n uint32_t q_frag_local[2][4];\n static_assert(NUM_FRAGS_D % 4 == 0, \"NUM_FRAGS_D must be a multiple of 4\");\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n uint32_t q_smem_offset_r_first_half = *q_smem_offset_r;\n#pragma unroll\n for (uint32_t fdi = 0; fdi < NUM_FRAGS_D / 2; ++fdi) {\n q_smem->ldmatrix_m8n8x4(q_smem_offset_r_first_half, q_frag_local[0]);\n uint32_t q_smem_offset_r_last_half =\n q_smem->template advance_offset_by_column<NUM_FRAGS_D>(q_smem_offset_r_first_half, 0);\n q_smem->ldmatrix_m8n8x4(q_smem_offset_r_last_half, q_frag_local[1]);\n q_frag_apply_llama_rope_with_pos<DTypeQ>(\n (DTypeQ*)q_frag_local[0], (DTypeQ*)q_frag_local[1], rope_freq[fdi],\n q_packed_idx_base + fq * 16 + lane_idx / 4, group_size, q_offset);\n q_smem->stmatrix_m8n8x4(q_smem_offset_r_last_half, q_frag_local[1]);\n q_smem->stmatrix_m8n8x4(q_smem_offset_r_first_half, q_frag_local[0]);\n q_smem_offset_r_first_half =\n q_smem->template advance_offset_by_column<2>(q_smem_offset_r_first_half, fdi);\n }\n *q_smem_offset_r += 16 * channel_size_128b_q;\n }\n *q_smem_offset_r -= NUM_FRAGS_Q * 16 * channel_size_128b_q;\n }\n}\n\ntemplate <uint32_t NUM_WARPS_Q, uint32_t NUM_WARPS_KV, uint32_t NUM_FRAGS_Q, uint32_t NUM_FRAGS_D,\n SwizzleMode swizzle_mode, typename AttentionVariant>\n__device__ __forceinline__ void q_smem_inplace_transform(\n const typename AttentionVariant::ParamsT& params, AttentionVariant variant,\n smem_t<swizzle_mode>* q_smem) {\n using DTypeQ = typename AttentionVariant::DTypeQ;\n const uint32_t warp_idx = get_warp_idx<NUM_WARPS_Q, NUM_WARPS_KV>(), lane_idx = threadIdx.x;\n constexpr uint32_t head_dim = NUM_FRAGS_D * 16;\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n constexpr uint32_t num_warps = NUM_WARPS_Q * NUM_WARPS_KV;\n#pragma unroll\n for (uint32_t i = 0; i < NUM_FRAGS_Q * head_dim / (NUM_WARPS_KV * 16); ++i) {\n vec_t<DTypeQ, 8> tmp;\n tmp.load((DTypeQ*)(q_smem->base) + (i * num_warps + warp_idx) * 256 + lane_idx * 8);\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n tmp[reg_id] = variant.QueryTransform(params, tmp[reg_id]);\n }\n tmp.store((DTypeQ*)(q_smem->base) + (i * num_warps + warp_idx) * 256 + lane_idx * 8);\n }\n}\n\ntemplate <uint32_t NUM_WARPS_Q, uint32_t NUM_WARPS_KV, uint32_t NUM_FRAGS_D, uint32_t NUM_FRAGS_KV,\n SwizzleMode swizzle_mode, typename DTypeKV>\n__device__ __forceinline__ void k_smem_inplace_apply_rotary(const uint32_t kv_idx_base,\n smem_t<swizzle_mode>* k_smem,\n uint32_t* k_smem_offset_r,\n float (*rope_freq)[4]) {\n static_assert(sizeof(DTypeKV) == 2);\n constexpr uint32_t head_dim = NUM_FRAGS_D * 16;\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<DTypeKV>();\n uint32_t k_frag_local[2][4];\n const uint32_t lane_idx = threadIdx.x;\n if constexpr (NUM_FRAGS_D == 4 && NUM_WARPS_Q == 4) {\n static_assert(NUM_WARPS_KV == 1);\n const uint32_t warp_idx = get_warp_idx_q<NUM_WARPS_Q, NUM_WARPS_KV>();\n // horizontal-axis: y\n // horizontal-axis: y\n // vertical-axis: z\n // | 1-16 | 16-32 | 32-48 | 48-64 |\n // | 1-16 | warp_idx=0 | warp_idx=1 | warp_idx=0 | warp_idx=1 |\n // | 16-32 | warp_idx=2 | warp_idx=3 | warp_idx=2 | warp_idx=3 |\n static_assert(NUM_FRAGS_KV % 2 == 0,\n \"when NUM_FRAGS_D == 4, NUM_FRAGS_KV must be a multiple of 2\");\n uint32_t kv_idx = kv_idx_base + (warp_idx / 2) * 16 + lane_idx / 4;\n *k_smem_offset_r =\n (*k_smem_offset_r ^ (0x2 * (warp_idx % 2))) + (warp_idx / 2) * 16 * channel_size_128b_kv;\n#pragma unroll\n for (uint32_t i = 0; i < NUM_FRAGS_KV / 2; ++i) {\n // uint32_t fkv = warp_idx / 2 + i * 2;\n uint32_t k_smem_offset_r_first_half = *k_smem_offset_r;\n uint32_t fdi = (warp_idx % 2);\n k_smem->ldmatrix_m8n8x4(k_smem_offset_r_first_half, k_frag_local[0]);\n uint32_t k_smem_offset_r_last_half =\n k_smem->template advance_offset_by_column<4>(k_smem_offset_r_first_half, 0);\n k_smem->ldmatrix_m8n8x4(k_smem_offset_r_last_half, k_frag_local[1]);\n k_frag_apply_llama_rope<DTypeKV>((DTypeKV*)k_frag_local[0], (DTypeKV*)k_frag_local[1],\n rope_freq[fdi], kv_idx);\n k_smem->stmatrix_m8n8x4(k_smem_offset_r_last_half, k_frag_local[1]);\n k_smem->stmatrix_m8n8x4(k_smem_offset_r_first_half, k_frag_local[0]);\n *k_smem_offset_r += 32 * channel_size_128b_kv;\n kv_idx += 32;\n }\n *k_smem_offset_r = (*k_smem_offset_r ^ (0x2 * (warp_idx % 2))) -\n ((warp_idx / 2) + NUM_FRAGS_KV) * 16 * channel_size_128b_kv;\n } else {\n const uint32_t warp_idx_x = get_warp_idx_q<NUM_WARPS_Q, NUM_WARPS_KV>(),\n warp_idx_z = get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>();\n static_assert(NUM_FRAGS_D % (2 * NUM_WARPS_Q) == 0);\n // horizontal axis: y\n // vertical axis: z\n // | (warp_idx_z, warp_idx_x) | 1-16 | 16-32 | 32-48 | 48-64 | ...\n // | 1-16*NUM_FRAGS_KV | (0, 0) | (0, 1) | (0, 2) | (0, 3) | ...\n // | 16*NUM_FRAGS_KV-32*NUM_FRAGS_KV | (1, 0) | (1, 1) | (1, 2) | (1, 3) | ...\n // ...\n uint32_t kv_idx = kv_idx_base + (warp_idx_z * NUM_FRAGS_KV * 16) + lane_idx / 4;\n *k_smem_offset_r = *k_smem_offset_r ^ (0x2 * warp_idx_x);\n#pragma unroll\n for (uint32_t i = 0; i < NUM_FRAGS_KV; ++i) {\n uint32_t k_smem_offset_r_first_half = *k_smem_offset_r;\n#pragma unroll\n for (uint32_t j = 0; j < NUM_FRAGS_D / (2 * NUM_WARPS_Q); ++j) {\n uint32_t fdi = warp_idx_x + j * NUM_WARPS_Q;\n k_smem->ldmatrix_m8n8x4(k_smem_offset_r_first_half, k_frag_local[0]);\n uint32_t k_smem_offset_r_last_half =\n k_smem->template advance_offset_by_column<NUM_FRAGS_D>(k_smem_offset_r_first_half, 0);\n k_smem->ldmatrix_m8n8x4(k_smem_offset_r_last_half, k_frag_local[1]);\n k_frag_apply_llama_rope<DTypeKV>((DTypeKV*)k_frag_local[0], (DTypeKV*)k_frag_local[1],\n rope_freq[fdi], kv_idx);\n k_smem->stmatrix_m8n8x4(k_smem_offset_r_last_half, k_frag_local[1]);\n k_smem->stmatrix_m8n8x4(k_smem_offset_r_first_half, k_frag_local[0]);\n k_smem_offset_r_first_half = k_smem->template advance_offset_by_column<2 * NUM_WARPS_Q>(\n k_smem_offset_r_first_half, fdi);\n }\n *k_smem_offset_r += 16 * channel_size_128b_kv;\n kv_idx += 16;\n }\n *k_smem_offset_r =\n (*k_smem_offset_r ^ (0x2 * warp_idx_x)) - NUM_FRAGS_KV * 16 * channel_size_128b_kv;\n }\n}\n\ntemplate <uint32_t NUM_FRAGS_Q, uint32_t NUM_FRAGS_D, uint32_t NUM_FRAGS_KV,\n SwizzleMode swizzle_mode_q, SwizzleMode swizzle_mode_kv, typename DTypeQ,\n typename DTypeKV, typename DTypeQKAccum>\n__device__ __forceinline__ void compute_qk(smem_t<swizzle_mode_q>* q_smem,\n uint32_t* q_smem_offset_r,\n smem_t<swizzle_mode_kv>* k_smem,\n uint32_t* k_smem_offset_r,\n DTypeQKAccum (*s_frag)[NUM_FRAGS_KV][8]) {\n constexpr uint32_t head_dim = NUM_FRAGS_D * 16;\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<DTypeKV>();\n uint32_t a_frag[NUM_FRAGS_Q][4], b_frag[4];\n // compute q*k^T\n#pragma unroll\n for (uint32_t fd = 0; fd < NUM_FRAGS_D; ++fd) {\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n q_smem->ldmatrix_m8n8x4(*q_smem_offset_r, a_frag[fq]);\n *q_smem_offset_r =\n q_smem->template advance_offset_by_row<16, channel_size_128b_q>(*q_smem_offset_r);\n }\n\n *q_smem_offset_r = q_smem->template advance_offset_by_column<2>(*q_smem_offset_r, fd) -\n NUM_FRAGS_Q * 16 * channel_size_128b_q;\n\n#pragma unroll\n for (uint32_t fkv = 0; fkv < NUM_FRAGS_KV; ++fkv) {\n if constexpr (sizeof(DTypeKV) == 1) {\n uint32_t b_frag_f8[2];\n if (fd % 2 == 0) {\n k_smem->ldmatrix_m8n8x4_left_half(*k_smem_offset_r, b_frag_f8);\n } else {\n k_smem->ldmatrix_m8n8x4_right_half(*k_smem_offset_r, b_frag_f8);\n }\n b_frag_f8[0] = frag_layout_swizzle_16b_to_8b(b_frag_f8[0]);\n b_frag_f8[1] = frag_layout_swizzle_16b_to_8b(b_frag_f8[1]);\n vec_cast<DTypeQ, DTypeKV>::cast<8>((DTypeQ*)b_frag, (DTypeKV*)b_frag_f8);\n } else {\n k_smem->ldmatrix_m8n8x4(*k_smem_offset_r, b_frag);\n }\n *k_smem_offset_r =\n k_smem->template advance_offset_by_row<16, channel_size_128b_kv>(*k_smem_offset_r);\n\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n if constexpr (std::is_same_v<DTypeQKAccum, float>) {\n if (fd == 0) {\n mma::mma_sync_m16n16k16_row_col_f16f16f32<DTypeQ, MMAMode::kInit>(s_frag[fq][fkv],\n a_frag[fq], b_frag);\n } else {\n mma::mma_sync_m16n16k16_row_col_f16f16f32<DTypeQ>(s_frag[fq][fkv], a_frag[fq], b_frag);\n }\n } else if (std::is_same_v<DTypeQKAccum, half>) {\n if (fd == 0) {\n mma::mma_sync_m16n16k16_row_col_f16f16f16<MMAMode::kInit>((uint32_t*)s_frag[fq][fkv],\n a_frag[fq], b_frag);\n } else {\n mma::mma_sync_m16n16k16_row_col_f16f16f16((uint32_t*)s_frag[fq][fkv], a_frag[fq],\n b_frag);\n }\n }\n }\n }\n if constexpr (sizeof(DTypeKV) == 1) {\n if (fd % 2 == 1) {\n *k_smem_offset_r = k_smem->template advance_offset_by_column<2>(*k_smem_offset_r, fd / 2);\n }\n *k_smem_offset_r -= NUM_FRAGS_KV * 16 * channel_size_128b_kv;\n } else {\n *k_smem_offset_r = k_smem->template advance_offset_by_column<2>(*k_smem_offset_r, fd) -\n NUM_FRAGS_KV * 16 * channel_size_128b_kv;\n }\n }\n *q_smem_offset_r -= NUM_FRAGS_D * 2;\n *k_smem_offset_r -= NUM_FRAGS_D * sizeof(DTypeKV);\n}\n\ntemplate <uint32_t NUM_FRAGS_Q, uint32_t NUM_FRAGS_D, uint32_t NUM_FRAGS_KV,\n typename AttentionVariant, typename DTypeQKAccum>\n__device__ __forceinline__ void logits_transform(const typename AttentionVariant::ParamsT& params,\n AttentionVariant variant, const uint32_t batch_idx,\n const uint32_t qo_packed_idx_base,\n const uint32_t kv_idx_base, const uint32_t qo_len,\n const uint32_t kv_len,\n const uint_fastdiv group_size,\n DTypeQKAccum (*s_frag)[NUM_FRAGS_KV][8]) {\n const uint32_t lane_idx = threadIdx.x, kv_head_idx = blockIdx.z;\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t fkv = 0; fkv < NUM_FRAGS_KV; ++fkv) {\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n uint32_t q, r;\n group_size.divmod(qo_packed_idx_base + fq * 16 + lane_idx / 4 + 8 * ((reg_id % 4) / 2), q,\n r);\n const uint32_t q_idx = q, kv_idx = kv_idx_base + fkv * 16 + 2 * (lane_idx % 4) +\n 8 * (reg_id / 4) + reg_id % 2;\n const uint32_t qo_head_idx = kv_head_idx * group_size + r;\n s_frag[fq][fkv][reg_id] = variant.LogitsTransform(\n params, s_frag[fq][fkv][reg_id], batch_idx, q_idx, kv_idx, qo_head_idx, kv_head_idx);\n }\n }\n }\n}\n\ntemplate <MaskMode MASK_MODE, uint32_t NUM_FRAGS_Q, uint32_t NUM_FRAGS_D, uint32_t NUM_FRAGS_KV,\n typename AttentionVariant, typename DTypeQKAccum>\n__device__ __forceinline__ void logits_mask(const typename AttentionVariant::ParamsT& params,\n AttentionVariant variant, const uint32_t batch_idx,\n const uint32_t qo_packed_idx_base,\n const uint32_t kv_idx_base, const uint32_t qo_len,\n const uint32_t kv_len, const uint32_t chunk_end,\n const uint_fastdiv group_size,\n DTypeQKAccum (*s_frag)[NUM_FRAGS_KV][8]) {\n const uint32_t lane_idx = threadIdx.x, kv_head_idx = blockIdx.z;\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t fkv = 0; fkv < NUM_FRAGS_KV; ++fkv) {\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n uint32_t q, r;\n group_size.divmod(qo_packed_idx_base + fq * 16 + lane_idx / 4 + 8 * ((reg_id % 4) / 2), q,\n r);\n const uint32_t q_idx = q, kv_idx = kv_idx_base + fkv * 16 + 2 * (lane_idx % 4) +\n 8 * (reg_id / 4) + reg_id % 2;\n const uint32_t qo_head_idx = kv_head_idx * group_size + r;\n const bool mask =\n (!(MASK_MODE == MaskMode::kCausal\n ? (kv_idx + qo_len > kv_len + q_idx || (kv_idx >= chunk_end))\n : kv_idx >= chunk_end)) &&\n variant.LogitsMask(params, batch_idx, q_idx, kv_idx, qo_head_idx, kv_head_idx);\n s_frag[fq][fkv][reg_id] =\n (mask) ? s_frag[fq][fkv][reg_id]\n : (variant.use_softmax ? DTypeQKAccum(-math::inf) : DTypeQKAccum(0.f));\n }\n }\n }\n}\n\ntemplate <uint32_t NUM_FRAGS_Q, uint32_t NUM_FRAGS_D, uint32_t NUM_FRAGS_KV, typename DTypeQKAccum,\n typename AttentionVariant>\n__device__ __forceinline__ void update_mdo_states(AttentionVariant variant,\n DTypeQKAccum (*s_frag)[NUM_FRAGS_KV][8],\n float (*o_frag)[NUM_FRAGS_D][8],\n DTypeQKAccum (*m)[2], float (*d)[2]) {\n if constexpr (variant.use_softmax) {\n if constexpr (std::is_same_v<DTypeQKAccum, float>) {\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n float m_prev = m[fq][j];\n#pragma unroll\n for (uint32_t fkv = 0; fkv < NUM_FRAGS_KV; ++fkv) {\n float m_local = max(max(s_frag[fq][fkv][j * 2 + 0], s_frag[fq][fkv][j * 2 + 1]),\n max(s_frag[fq][fkv][j * 2 + 4], s_frag[fq][fkv][j * 2 + 5]));\n m[fq][j] = max(m[fq][j], m_local);\n }\n m[fq][j] = max(m[fq][j], math::shfl_xor_sync(m[fq][j], 0x2));\n m[fq][j] = max(m[fq][j], math::shfl_xor_sync(m[fq][j], 0x1));\n\n float o_scale = math::ptx_exp2(m_prev - m[fq][j]);\n d[fq][j] *= o_scale;\n#pragma unroll\n for (uint32_t fd = 0; fd < NUM_FRAGS_D; ++fd) {\n o_frag[fq][fd][j * 2 + 0] *= o_scale;\n o_frag[fq][fd][j * 2 + 1] *= o_scale;\n o_frag[fq][fd][j * 2 + 4] *= o_scale;\n o_frag[fq][fd][j * 2 + 5] *= o_scale;\n }\n#pragma unroll\n for (uint32_t fkv = 0; fkv < NUM_FRAGS_KV; ++fkv) {\n s_frag[fq][fkv][j * 2 + 0] = math::ptx_exp2(s_frag[fq][fkv][j * 2 + 0] - m[fq][j]);\n s_frag[fq][fkv][j * 2 + 1] = math::ptx_exp2(s_frag[fq][fkv][j * 2 + 1] - m[fq][j]);\n s_frag[fq][fkv][j * 2 + 4] = math::ptx_exp2(s_frag[fq][fkv][j * 2 + 4] - m[fq][j]);\n s_frag[fq][fkv][j * 2 + 5] = math::ptx_exp2(s_frag[fq][fkv][j * 2 + 5] - m[fq][j]);\n }\n }\n }\n } else if constexpr (std::is_same_v<DTypeQKAccum, half>) {\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n half m_prev[2];\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n m_prev[j] = m[fq][j];\n#pragma unroll\n for (uint32_t fkv = 0; fkv < NUM_FRAGS_KV; ++fkv) {\n half2 m_local =\n __hmax2(*(half2*)&s_frag[fq][fkv][j * 2], *(half2*)&s_frag[fq][fkv][j * 2 + 4]);\n m[fq][j] = __hmax(m[fq][j], __hmax(m_local.x, m_local.y));\n }\n }\n *(half2*)&m[fq] = __hmax2(*(half2*)&m[fq], math::shfl_xor_sync(*(half2*)&m[fq], 0x2));\n *(half2*)&m[fq] = __hmax2(*(half2*)&m[fq], math::shfl_xor_sync(*(half2*)&m[fq], 0x1));\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n float o_scale = math::ptx_exp2(float(m_prev[j] - m[fq][j]));\n d[fq][j] *= o_scale;\n#pragma unroll\n for (uint32_t fd = 0; fd < NUM_FRAGS_D; ++fd) {\n o_frag[fq][fd][j * 2 + 0] *= o_scale;\n o_frag[fq][fd][j * 2 + 1] *= o_scale;\n o_frag[fq][fd][j * 2 + 4] *= o_scale;\n o_frag[fq][fd][j * 2 + 5] *= o_scale;\n }\n half2 m2 = make_half2(m[fq][j], m[fq][j]);\n#pragma unroll\n for (uint32_t fkv = 0; fkv < NUM_FRAGS_KV; ++fkv) {\n *(half2*)&s_frag[fq][fkv][j * 2] =\n math::ptx_exp2(*(half2*)&s_frag[fq][fkv][j * 2] - m2);\n *(half2*)&s_frag[fq][fkv][j * 2 + 4] =\n math::ptx_exp2(*(half2*)&s_frag[fq][fkv][j * 2 + 4] - m2);\n }\n }\n }\n }\n }\n}\n\ntemplate <uint32_t NUM_FRAGS_Q, uint32_t NUM_FRAGS_D, uint32_t NUM_FRAGS_KV,\n SwizzleMode swizzle_mode, typename DTypeQ, typename DTypeKV, typename DTypeQKAccum,\n typename AttentionVariant>\n__device__ __forceinline__ void compute_sfm_v(AttentionVariant variant,\n smem_t<swizzle_mode>* v_smem,\n uint32_t* v_smem_offset_r,\n DTypeQKAccum (*s_frag)[NUM_FRAGS_KV][8],\n float (*o_frag)[NUM_FRAGS_D][8], float (*d)[2]) {\n constexpr uint32_t head_dim = NUM_FRAGS_D * 16;\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<DTypeKV>();\n\n DTypeQ s_frag_f16[NUM_FRAGS_Q][NUM_FRAGS_KV][8];\n if constexpr (std::is_same_v<DTypeQKAccum, float>) {\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t fkv = 0; fkv < NUM_FRAGS_KV; ++fkv) {\n vec_cast<DTypeQ, float>::cast<8>(s_frag_f16[fq][fkv], s_frag[fq][fkv]);\n }\n }\n }\n\n if constexpr (variant.use_softmax) {\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t fkv = 0; fkv < NUM_FRAGS_KV; ++fkv) {\n if constexpr (std::is_same_v<DTypeQKAccum, float>) {\n mma::rowsum_f16f16f32(d[fq], s_frag_f16[fq][fkv]);\n } else {\n mma::rowsum_f16f16f32(d[fq], s_frag[fq][fkv]);\n }\n }\n }\n }\n\n#pragma unroll\n for (uint32_t fkv = 0; fkv < NUM_FRAGS_KV; ++fkv) {\n#pragma unroll\n for (uint32_t fd = 0; fd < NUM_FRAGS_D; ++fd) {\n uint32_t b_frag[4];\n if constexpr (sizeof(DTypeKV) == 1) {\n uint32_t b_frag_f8[2];\n if (fd % 2 == 0) {\n v_smem->ldmatrix_m8n8x4_trans_left_half(*v_smem_offset_r, b_frag_f8);\n } else {\n v_smem->ldmatrix_m8n8x4_trans_right_half(*v_smem_offset_r, b_frag_f8);\n }\n b_frag_f8[0] = frag_layout_swizzle_16b_to_8b_trans(b_frag_f8[0]);\n b_frag_f8[1] = frag_layout_swizzle_16b_to_8b_trans(b_frag_f8[1]);\n vec_cast<DTypeQ, DTypeKV>::cast<8>((DTypeQ*)b_frag, (DTypeKV*)b_frag_f8);\n swap(b_frag[1], b_frag[2]);\n } else {\n v_smem->ldmatrix_m8n8x4_trans(*v_smem_offset_r, b_frag);\n }\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n if constexpr (std::is_same_v<DTypeQKAccum, float>) {\n mma::mma_sync_m16n16k16_row_col_f16f16f32<DTypeQ>(\n o_frag[fq][fd], (uint32_t*)(s_frag_f16[fq][fkv]), b_frag);\n } else {\n mma::mma_sync_m16n16k16_row_col_f16f16f32<DTypeQ>(o_frag[fq][fd],\n (uint32_t*)s_frag[fq][fkv], b_frag);\n }\n }\n if constexpr (sizeof(DTypeKV) == 1) {\n if (fd % 2 == 1) {\n *v_smem_offset_r = v_smem->template advance_offset_by_column<2>(*v_smem_offset_r, fd / 2);\n }\n } else {\n *v_smem_offset_r = v_smem->template advance_offset_by_column<2>(*v_smem_offset_r, fd);\n }\n }\n *v_smem_offset_r =\n v_smem->template advance_offset_by_row<16, channel_size_128b_kv>(*v_smem_offset_r) -\n sizeof(DTypeKV) * NUM_FRAGS_D;\n }\n *v_smem_offset_r -= 16 * NUM_FRAGS_KV * channel_size_128b_kv;\n}\n\ntemplate <uint32_t NUM_FRAGS_Q, uint32_t NUM_FRAGS_D, typename DTypeQKAccum,\n typename AttentionVariant>\n__device__ __forceinline__ void normalize_d(AttentionVariant variant,\n float (*o_frag)[NUM_FRAGS_D][8], DTypeQKAccum (*m)[2],\n float (*d)[2]) {\n if constexpr (variant.use_softmax) {\n float d_rcp[NUM_FRAGS_Q][2];\n // compute reciprocal of d\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n d_rcp[fq][j] = (m[fq][j] != DTypeQKAccum(-math::inf)) ? math::ptx_rcp(d[fq][j]) : 0.f;\n }\n }\n\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t fd = 0; fd < NUM_FRAGS_D; ++fd) {\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n o_frag[fq][fd][reg_id] = o_frag[fq][fd][reg_id] * d_rcp[fq][(reg_id % 4) / 2];\n }\n }\n }\n }\n}\n\n/*!\n * \\brief Synchronize the states of the MDO kernel across the threadblock along threadIdx.z.\n */\ntemplate <uint32_t NUM_WARPS_Q, uint32_t NUM_WARPS_KV, uint32_t NUM_FRAGS_Q, uint32_t NUM_FRAGS_D,\n typename DTypeQKAccum, typename AttentionVariant>\n__device__ __forceinline__ void threadblock_sync_mdo_states(\n AttentionVariant variant, float (*o_frag)[NUM_FRAGS_D][8], float* smem_workspace,\n DTypeQKAccum (*m)[2], float (*d)[2], const uint32_t warp_idx, const uint32_t lane_idx) {\n // only necessary when blockDim.z > 1\n if constexpr (NUM_WARPS_KV > 1) {\n float2* smem_md = (float2*)(smem_workspace + NUM_FRAGS_Q * NUM_FRAGS_D * NUM_WARPS_Q *\n NUM_WARPS_KV * WARP_SIZE * 8);\n // o: [num_warps, NUM_FRAGS_Q, NUM_FRAGS_D, WARP_SIZE(32), 8]\n // md: [num_warps, NUM_FRAGS_Q, 2, WARP_SIZE(32), 2 (m/d)]\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t fd = 0; fd < NUM_FRAGS_D; ++fd) {\n vec_t<float, 8>::memcpy(\n smem_workspace +\n (((warp_idx * NUM_FRAGS_Q + fq) * NUM_FRAGS_D + fd) * WARP_SIZE + lane_idx) * 8,\n o_frag[fq][fd]);\n }\n }\n\n if constexpr (variant.use_softmax) {\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n smem_md[((warp_idx * NUM_FRAGS_Q + fq) * 2 + j) * WARP_SIZE + lane_idx] =\n make_float2(float(m[fq][j]), d[fq][j]);\n }\n }\n\n // synchronize m,d first\n __syncthreads();\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n float o_scale[2][NUM_WARPS_KV];\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n float m_new = -math::inf, d_new = 1.f;\n#pragma unroll\n for (uint32_t i = 0; i < NUM_WARPS_KV; ++i) {\n float2 md = smem_md[(((i * NUM_WARPS_Q + get_warp_idx_q<NUM_WARPS_Q, NUM_WARPS_KV>()) *\n NUM_FRAGS_Q +\n fq) *\n 2 +\n j) *\n WARP_SIZE +\n lane_idx];\n float m_prev = m_new, d_prev = d_new;\n m_new = max(m_new, md.x);\n d_new = d_prev * math::ptx_exp2(m_prev - m_new) + md.y * math::ptx_exp2(md.x - m_new);\n }\n\n#pragma unroll\n for (uint32_t i = 0; i < NUM_WARPS_KV; ++i) {\n float2 md = smem_md[(((i * NUM_WARPS_Q + get_warp_idx_q<NUM_WARPS_Q, NUM_WARPS_KV>()) *\n NUM_FRAGS_Q +\n fq) *\n 2 +\n j) *\n WARP_SIZE +\n lane_idx];\n float mi = md.x;\n o_scale[j][i] = math::ptx_exp2(float(mi - m_new));\n }\n m[fq][j] = DTypeQKAccum(m_new);\n d[fq][j] = d_new;\n }\n\n#pragma unroll\n for (uint32_t fd = 0; fd < NUM_FRAGS_D; ++fd) {\n vec_t<float, 8> o_new;\n o_new.fill(0.f);\n#pragma unroll\n for (uint32_t i = 0; i < NUM_WARPS_KV; ++i) {\n vec_t<float, 8> oi;\n oi.load(\n smem_workspace +\n ((((i * NUM_WARPS_Q + get_warp_idx_q<NUM_WARPS_Q, NUM_WARPS_KV>()) * NUM_FRAGS_Q +\n fq) *\n NUM_FRAGS_D +\n fd) *\n WARP_SIZE +\n lane_idx) *\n 8);\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n o_new[reg_id] += oi[reg_id] * o_scale[(reg_id % 4) / 2][i];\n }\n }\n o_new.store(o_frag[fq][fd]);\n }\n }\n } else {\n // synchronize m,d first\n __syncthreads();\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t fd = 0; fd < NUM_FRAGS_D; ++fd) {\n vec_t<float, 8> o_new;\n o_new.fill(0.f);\n#pragma unroll\n for (uint32_t i = 0; i < NUM_WARPS_KV; ++i) {\n vec_t<float, 8> oi;\n oi.load(\n smem_workspace +\n ((((i * NUM_WARPS_Q + get_warp_idx_q<NUM_WARPS_Q, NUM_WARPS_KV>()) * NUM_FRAGS_Q +\n fq) *\n NUM_FRAGS_D +\n fd) *\n WARP_SIZE +\n lane_idx) *\n 8);\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n o_new[reg_id] += oi[reg_id];\n }\n }\n o_new.store(o_frag[fq][fd]);\n }\n }\n }\n }\n}\n\ntemplate <uint32_t NUM_WARPS_Q, uint32_t NUM_WARPS_KV, uint32_t NUM_FRAGS_Q, uint32_t NUM_FRAGS_D,\n SwizzleMode swizzle_mode, typename DTypeO>\n__device__ __forceinline__ void write_o_reg_gmem(\n float (*o_frag)[NUM_FRAGS_D][8], smem_t<swizzle_mode>* o_smem, DTypeO* o_ptr_base,\n const uint32_t o_packed_idx_base, const uint32_t qo_upper_bound, const uint32_t o_stride_n,\n const uint32_t o_stride_h, const uint_fastdiv group_size) {\n constexpr uint32_t head_dim = NUM_FRAGS_D * 16;\n constexpr uint32_t channel_size_128b_out = head_dim / num_elems_per_128b<DTypeO>();\n const uint32_t warp_idx_x = get_warp_idx_q<NUM_WARPS_Q, NUM_WARPS_KV>();\n const uint32_t lane_idx = threadIdx.x;\n\n if (get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>() == 0) {\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t fd = 0; fd < NUM_FRAGS_D; ++fd) {\n uint32_t o_frag_f16[4];\n vec_cast<DTypeO, float>::cast<8>((DTypeO*)o_frag_f16, o_frag[fq][fd]);\n#ifdef FLASHINFER_STMATRIX_M8N8X4_ENABLED\n uint32_t o_smem_offset_w = o_smem->get_permuted_offset<channel_size_128b_out>(\n (warp_idx_x * NUM_FRAGS_Q + fq) * 16 + lane_idx % 16, fd * 2 + lane_idx / 16);\n o_smem->stmatrix_m8n8x4(o_smem_offset_w, o_frag_f16);\n#else\n uint32_t o_smem_offset_w = o_smem->get_permuted_offset<channel_size_128b_out>(\n (warp_idx_x * NUM_FRAGS_Q + fq) * 16 + lane_idx / 4, fd * 2);\n ((uint32_t*)(o_smem->base + o_smem_offset_w))[lane_idx % 4] = o_frag_f16[0];\n ((uint32_t*)(o_smem->base + o_smem_offset_w + 8 * channel_size_128b_out))[lane_idx % 4] =\n o_frag_f16[1];\n ((uint32_t*)(o_smem->base + (o_smem_offset_w ^ 0x1)))[lane_idx % 4] = o_frag_f16[2];\n ((uint32_t*)(o_smem->base + (o_smem_offset_w ^ 0x1) +\n 8 * channel_size_128b_out))[lane_idx % 4] = o_frag_f16[3];\n#endif\n }\n }\n\n uint32_t o_smem_offset_w = o_smem->get_permuted_offset<channel_size_128b_out>(\n warp_idx_x * NUM_FRAGS_Q * 16 + lane_idx / 8, lane_idx % 8);\n\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t j = 0; j < 4; ++j) {\n uint32_t q, r;\n group_size.divmod(o_packed_idx_base + lane_idx / 8 + fq * 16 + j * 4, q, r);\n const uint32_t o_idx = q;\n DTypeO* o_ptr = o_ptr_base + q * o_stride_n + r * o_stride_h;\n#pragma unroll\n for (uint32_t fdo = 0; fdo < NUM_FRAGS_D / 4; ++fdo) {\n if (o_idx < qo_upper_bound) {\n o_smem->store_128b(o_smem_offset_w, o_ptr);\n }\n o_ptr += 8 * num_elems_per_128b<DTypeO>();\n o_smem_offset_w = o_smem->template advance_offset_by_column<8>(o_smem_offset_w, fdo);\n }\n o_smem_offset_w =\n o_smem->template advance_offset_by_row<4, channel_size_128b_out>(o_smem_offset_w) -\n 2 * NUM_FRAGS_D;\n }\n }\n }\n}\n\n} // namespace\n\n/*!\n * \\brief FlashAttention prefill CUDA kernel for a single request.\n * \\tparam partition_kv Whether to split kv_len into chunks.\n * \\tparam mask_mode The mask mode used in the attention operation.\n * \\tparam POS_ENCODING_MODE The positional encoding mode.\n * \\tparam NUM_FRAGS_Q The number of fragments in x dimension.\n * \\tparam NUM_FRAGS_D The number of fragments in y dimension.\n * \\tparam NUM_FRAGS_KV The number of fragments in z dimension.\n * \\tparam num_warps The number of warps in the threadblock.\n * \\tparam DTypeQ The data type of the query tensor.\n * \\tparam DTypeKV The data type of the key/value tensor.\n * \\tparam DTypeO The data type of the output tensor.\n * \\param q The query tensor.\n * \\param k The key tensor.\n * \\param v The value tensor.\n * \\param o The output tensor.\n * \\param tmp The temporary buffer (used when partition_kv is true).\n * \\param lse The logsumexp value.\n * \\param log2_rope_rcp_scale log2(1/(rope_scale)), where rope_scale is the scaling\n * factor used in RoPE interpolation.\n * \\param log2_rope_rcp_theta log2(1/(rope_theta)), where rope_theta is the theta\n * used in RoPE.\n */\ntemplate <MaskMode MASK_MODE, PosEncodingMode POS_ENCODING_MODE, uint32_t NUM_FRAGS_Q,\n uint32_t NUM_FRAGS_D, uint32_t NUM_FRAGS_KV, uint32_t NUM_WARPS_Q, uint32_t NUM_WARPS_KV,\n typename DTypeQKAccum, typename AttentionVariant>\n__global__\n__launch_bounds__(NUM_WARPS_Q* NUM_WARPS_KV* WARP_SIZE) void SinglePrefillWithKVCacheKernel(\n const uint_fastdiv group_size,\n const __grid_constant__ typename AttentionVariant::ParamsT params) {\n using DTypeQ = typename AttentionVariant::DTypeQ;\n#if (__CUDA_ARCH__ < 800)\n if constexpr (std::is_same_v<DTypeQ, nv_bfloat16>) {\n FLASHINFER_RUNTIME_ASSERT(\"Prefill kernels do not support bf16 on sm75.\");\n } else {\n#endif\n using DTypeKV = typename AttentionVariant::DTypeKV;\n using DTypeO = typename AttentionVariant::DTypeO;\n DTypeQ* q = params.q;\n DTypeKV* k = params.k;\n DTypeKV* v = params.v;\n DTypeO* o = params.o;\n float* lse = params.lse;\n const uint32_t qo_len = params.qo_len;\n const uint32_t kv_len = params.kv_len;\n const bool partition_kv = params.partition_kv;\n const uint32_t q_stride_n = params.q_stride_n;\n const uint32_t q_stride_h = params.q_stride_h;\n const uint32_t kv_stride_n = params.kv_stride_n;\n const uint32_t kv_stride_h = params.kv_stride_h;\n const int32_t maybe_window_left = params.window_left;\n\n static_assert(sizeof(DTypeQ) == 2);\n static_assert(sizeof(DTypeO) == 2);\n const uint32_t lane_idx = threadIdx.x, warp_idx = get_warp_idx<NUM_WARPS_Q, NUM_WARPS_KV>();\n const uint32_t bx = blockIdx.x, chunk_idx = blockIdx.y, kv_head_idx = blockIdx.z;\n const uint32_t num_kv_heads = gridDim.z, num_qo_heads = num_kv_heads * group_size;\n constexpr uint32_t num_rows_per_cta = NUM_FRAGS_Q * NUM_WARPS_Q * 16;\n const tensor_info_t qkv_info(qo_len, kv_len, num_qo_heads, num_kv_heads, q_stride_n, q_stride_h,\n kv_stride_n, kv_stride_h, /*head_dim=*/NUM_FRAGS_D * 16);\n\n const uint32_t num_chunks = gridDim.y;\n const uint32_t max_chunk_size = partition_kv ? ceil_div(kv_len, num_chunks) : kv_len;\n const uint32_t chunk_start = partition_kv ? chunk_idx * max_chunk_size : 0;\n const uint32_t chunk_end =\n partition_kv ? min((chunk_idx + 1) * max_chunk_size, kv_len) : kv_len;\n const uint32_t chunk_size = chunk_end - chunk_start;\n\n auto block = cg::this_thread_block();\n extern __shared__ uint8_t smem[];\n AttentionVariant variant(params, /*batch_idx=*/0, smem);\n const uint32_t window_left = variant.window_left;\n\n constexpr uint32_t head_dim = NUM_FRAGS_D * 16;\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<DTypeKV>();\n constexpr uint32_t channel_size_128b_out = head_dim / num_elems_per_128b<DTypeO>();\n\n DTypeQKAccum s_frag[NUM_FRAGS_Q][NUM_FRAGS_KV][8];\n float o_frag[NUM_FRAGS_Q][NUM_FRAGS_D][8];\n DTypeQKAccum m[NUM_FRAGS_Q][2];\n float d[NUM_FRAGS_Q][2];\n float rope_freq[NUM_FRAGS_D / 2][4];\n if constexpr (POS_ENCODING_MODE == PosEncodingMode::kRoPELlama) {\n const float log2_rope_rcp_scale = params.log2_rope_rcp_scale;\n const float log2_rope_rcp_theta = params.log2_rope_rcp_theta;\n init_rope_freq<NUM_FRAGS_D>(rope_freq, log2_rope_rcp_scale, log2_rope_rcp_theta);\n }\n init_states<NUM_FRAGS_Q, NUM_FRAGS_D>(variant, o_frag, m, d);\n\n // cooperative fetch q fragment from gmem to reg\n const uint32_t qo_packed_idx_base =\n (bx * NUM_WARPS_Q + get_warp_idx_q<NUM_WARPS_Q, NUM_WARPS_KV>()) * NUM_FRAGS_Q * 16;\n constexpr SwizzleMode swizzle_mode_q = SwizzleMode::k128B;\n smem_t<swizzle_mode_q> qo_smem(smem);\n DTypeQ* q_ptr_base =\n q + qkv_info.get_q_elem_offset(0, kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeQ>());\n DTypeO* o_ptr_base =\n partition_kv\n ? o + chunk_idx * num_qo_heads * head_dim +\n qkv_info.get_o_elem_offset(0, kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeO>())\n : o + qkv_info.get_o_elem_offset(0, kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeO>());\n\n uint32_t q_smem_offset_r = qo_smem.get_permuted_offset<channel_size_128b_q>(\n get_warp_idx_q<NUM_WARPS_Q, NUM_WARPS_KV>() * NUM_FRAGS_Q * 16 + lane_idx % 16,\n lane_idx / 16);\n\n load_q_global_smem<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_Q, NUM_FRAGS_D>(\n qo_packed_idx_base, qo_len, q_ptr_base, q_stride_n, q_stride_h, group_size, &qo_smem);\n\n cp_async::commit_group();\n cp_async::wait_group<0>();\n block.sync();\n\n if constexpr (POS_ENCODING_MODE == PosEncodingMode::kRoPELlama) {\n q_smem_inplace_apply_rotary<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_Q, NUM_FRAGS_D,\n swizzle_mode_q, DTypeQ>(\n qo_packed_idx_base, qo_len, kv_len, group_size, &qo_smem, &q_smem_offset_r, rope_freq);\n block.sync();\n }\n q_smem_inplace_transform<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_Q, NUM_FRAGS_D, swizzle_mode_q>(\n params, variant, &qo_smem);\n\n constexpr SwizzleMode swizzle_mode_kv =\n (sizeof(DTypeKV) == 1 && head_dim == 64) ? SwizzleMode::k64B : SwizzleMode::k128B;\n constexpr uint32_t kv_frag_rows = swizzle_mode_kv == SwizzleMode::k128B ? 4 : 8;\n constexpr uint32_t kv_frag_cols = swizzle_mode_kv == SwizzleMode::k128B ? 8 : 4;\n smem_t<swizzle_mode_kv> k_smem(smem +\n (NUM_WARPS_Q * NUM_FRAGS_Q * sizeof(DTypeQ)) * 16 * head_dim),\n v_smem(smem + (NUM_WARPS_Q * NUM_FRAGS_Q * sizeof(DTypeQ) +\n NUM_WARPS_KV * NUM_FRAGS_KV * sizeof(DTypeKV)) *\n 16 * head_dim);\n\n const uint32_t num_iterations = ceil_div(\n MASK_MODE == MaskMode::kCausal\n ? min(chunk_size,\n sub_if_greater_or_zero(\n kv_len - qo_len + ((bx + 1) * num_rows_per_cta) / group_size, chunk_start))\n : chunk_size,\n 16 * NUM_WARPS_KV * NUM_FRAGS_KV);\n\n const uint32_t window_iteration =\n ceil_div(sub_if_greater_or_zero(kv_len + (bx + 1) * num_rows_per_cta,\n qo_len + window_left + chunk_start),\n (16 * NUM_WARPS_KV * NUM_FRAGS_KV));\n\n const uint32_t mask_iteration =\n (MASK_MODE == MaskMode::kCausal\n ? min(chunk_size,\n sub_if_greater_or_zero(kv_len + (bx * num_rows_per_cta) / group_size - qo_len,\n chunk_start))\n : chunk_size) /\n (16 * NUM_WARPS_KV * NUM_FRAGS_KV);\n\n DTypeKV* k_ptr =\n k + qkv_info.get_kv_elem_offset(\n chunk_start + warp_idx * kv_frag_rows + lane_idx / kv_frag_cols, kv_head_idx,\n (lane_idx % kv_frag_cols) * num_elems_per_128b<DTypeKV>());\n DTypeKV* v_ptr =\n v + qkv_info.get_kv_elem_offset(\n chunk_start + warp_idx * kv_frag_rows + lane_idx / kv_frag_cols, kv_head_idx,\n (lane_idx % kv_frag_cols) * num_elems_per_128b<DTypeKV>());\n\n uint32_t k_smem_offset_r = k_smem.get_permuted_offset<channel_size_128b_kv>(\n get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>() * NUM_FRAGS_KV * 16 +\n 8 * (lane_idx / 16) + lane_idx % 8,\n (lane_idx % 16) / 8),\n v_smem_offset_r = v_smem.get_permuted_offset<channel_size_128b_kv>(\n get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>() * NUM_FRAGS_KV * 16 + lane_idx % 16,\n lane_idx / 16),\n kv_smem_offset_w = k_smem.get_permuted_offset<channel_size_128b_kv>(\n warp_idx * kv_frag_rows + lane_idx / kv_frag_cols, lane_idx % kv_frag_cols);\n produce_kv<SharedMemFillMode::kNoFill, NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_D, NUM_FRAGS_KV>(\n k_smem, &kv_smem_offset_w, &k_ptr, kv_stride_n, 0, chunk_size);\n cp_async::commit_group();\n produce_kv<SharedMemFillMode::kFillZero, NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_D, NUM_FRAGS_KV>(\n v_smem, &kv_smem_offset_w, &v_ptr, kv_stride_n, 0, chunk_size);\n cp_async::commit_group();\n\n#pragma unroll 1\n for (uint32_t iter = 0; iter < num_iterations; ++iter) {\n cp_async::wait_group<1>();\n block.sync();\n\n if constexpr (POS_ENCODING_MODE == PosEncodingMode::kRoPELlama) {\n k_smem_inplace_apply_rotary<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_D, NUM_FRAGS_KV,\n swizzle_mode_kv, DTypeKV>(\n chunk_start + iter * 16 * NUM_WARPS_KV * NUM_FRAGS_KV, &k_smem, &k_smem_offset_r,\n rope_freq);\n block.sync();\n }\n\n // compute attention score\n compute_qk<NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV, swizzle_mode_q, swizzle_mode_kv, DTypeQ,\n DTypeKV>(&qo_smem, &q_smem_offset_r, &k_smem, &k_smem_offset_r, s_frag);\n\n logits_transform<NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV>(\n params, variant, /*batch_idx=*/0, qo_packed_idx_base,\n chunk_start + (iter * NUM_WARPS_KV + get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>()) *\n NUM_FRAGS_KV * 16,\n qo_len, kv_len, group_size, s_frag);\n\n // apply mask\n if (MASK_MODE == MaskMode::kCustom || (iter >= mask_iteration || iter < window_iteration)) {\n logits_mask<MASK_MODE, NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV>(\n params, variant, /*batch_idx=*/0, qo_packed_idx_base,\n chunk_start + (iter * NUM_WARPS_KV + get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>()) *\n NUM_FRAGS_KV * 16,\n qo_len, kv_len, chunk_end, group_size, s_frag);\n }\n\n // compute m,d states in online softmax\n update_mdo_states<NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV>(variant, s_frag, o_frag, m, d);\n\n block.sync();\n produce_kv<SharedMemFillMode::kNoFill, NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_D, NUM_FRAGS_KV>(\n k_smem, &kv_smem_offset_w, &k_ptr, kv_stride_n,\n (iter + 1) * 16 * NUM_WARPS_KV * NUM_FRAGS_KV, chunk_size);\n cp_async::commit_group();\n cp_async::wait_group<1>();\n block.sync();\n\n // compute sfm*v\n compute_sfm_v<NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV, swizzle_mode_kv, DTypeQ, DTypeKV>(\n variant, &v_smem, &v_smem_offset_r, s_frag, o_frag, d);\n\n block.sync();\n produce_kv<SharedMemFillMode::kFillZero, NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_D,\n NUM_FRAGS_KV>(v_smem, &kv_smem_offset_w, &v_ptr, kv_stride_n,\n (iter + 1) * 16 * NUM_WARPS_KV * NUM_FRAGS_KV, chunk_size);\n cp_async::commit_group();\n }\n cp_async::wait_group<0>();\n block.sync();\n\n // threadblock synchronization\n threadblock_sync_mdo_states<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_Q, NUM_FRAGS_D, DTypeQKAccum>(\n variant, o_frag, (float*)smem, m, d, warp_idx, lane_idx);\n\n // normalize d\n normalize_d<NUM_FRAGS_Q, NUM_FRAGS_D>(variant, o_frag, m, d);\n\n // write back\n write_o_reg_gmem<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_Q, NUM_FRAGS_D>(\n o_frag, &qo_smem, o_ptr_base, qo_packed_idx_base, qo_len,\n /*o_stride_n=*/\n partition_kv ? num_qo_heads * head_dim * num_chunks : num_qo_heads * head_dim,\n /*o_stride_h=*/head_dim, group_size);\n\n // write lse\n if constexpr (variant.use_softmax) {\n if (lse != nullptr || partition_kv) {\n if (get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>() == 0) {\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n uint32_t q, r;\n group_size.divmod(qo_packed_idx_base + lane_idx / 4 + j * 8 + fq * 16, q, r);\n const uint32_t qo_head_idx = kv_head_idx * group_size + r;\n const uint32_t qo_idx = q;\n if (qo_idx < qo_len) {\n if (partition_kv) {\n lse[(qo_idx * num_chunks + chunk_idx) * num_qo_heads + qo_head_idx] =\n math::ptx_log2(d[fq][j]) + float(m[fq][j]);\n } else {\n lse[qo_idx * num_qo_heads + qo_head_idx] =\n math::ptx_log2(d[fq][j]) + float(m[fq][j]);\n }\n }\n }\n }\n }\n }\n }\n#if (__CUDA_ARCH__ < 800)\n }\n#endif\n}\n\ntemplate <uint32_t HEAD_DIM, PosEncodingMode POS_ENCODING_MODE, bool ALLOW_FP16_QK_REDUCTION,\n MaskMode MASK_MODE, typename AttentionVariant>\ncudaError_t SinglePrefillWithKVCacheDispatched(typename AttentionVariant::ParamsT params,\n typename AttentionVariant::DTypeO* tmp,\n cudaStream_t stream) {\n using DTypeQ = typename AttentionVariant::DTypeQ;\n using DTypeKV = typename AttentionVariant::DTypeKV;\n using DTypeO = typename AttentionVariant::DTypeO;\n const uint32_t num_qo_heads = params.num_qo_heads;\n const uint32_t num_kv_heads = params.num_kv_heads;\n const uint32_t qo_len = params.qo_len;\n const uint32_t kv_len = params.kv_len;\n if (kv_len < qo_len && MASK_MODE == MaskMode::kCausal) {\n std::ostringstream err_msg;\n err_msg << \"When mask_mode is set to MaskMode::kCausal, kv_len must be greater than or equal \"\n \"to qo_len, got kv_len\"\n << kv_len << \" and qo_len \" << qo_len;\n throw std::invalid_argument(err_msg.str());\n }\n\n const uint32_t group_size = num_qo_heads / num_kv_heads;\n const uint_fastdiv group_size_fastdiv(group_size);\n constexpr uint32_t NUM_FRAGS_D = HEAD_DIM / 16;\n uint32_t cta_tile_q = 0;\n int64_t unpacked_qo_len = qo_len * group_size;\n if (unpacked_qo_len > 64 && HEAD_DIM < 256) {\n cta_tile_q = 128;\n } else {\n auto compute_capacity = GetCudaComputeCapability();\n if (compute_capacity.first >= 8) {\n // Ampere or newer\n if (unpacked_qo_len > 16) {\n // avg_packed_qo_len <= 64\n cta_tile_q = 64;\n } else {\n // avg_packed_qo_len <= 16\n cta_tile_q = 16;\n }\n } else {\n // NOTE(Zihao): not enough shared memory on Turing for 1x4 warp layout\n cta_tile_q = 64;\n }\n }\n\n DISPATCH_CTA_TILE_Q(cta_tile_q, CTA_TILE_Q, {\n constexpr uint32_t NUM_WARPS_Q = get_num_warps_q(CTA_TILE_Q);\n constexpr uint32_t NUM_WARPS_KV = get_num_warps_kv(CTA_TILE_Q);\n constexpr uint32_t NUM_FRAGS_Q = get_num_frags_q(CTA_TILE_Q);\n\n using DTypeQKAccum =\n typename std::conditional<ALLOW_FP16_QK_REDUCTION && std::is_same_v<DTypeQ, half>, half,\n float>::type;\n\n int dev_id = 0;\n FLASHINFER_CUDA_CALL(cudaGetDevice(&dev_id));\n int max_smem_per_sm = 0;\n FLASHINFER_CUDA_CALL(cudaDeviceGetAttribute(\n &max_smem_per_sm, cudaDevAttrMaxSharedMemoryPerMultiprocessor, dev_id));\n // we expect each sm execute two threadblocks\n // TODO(Zihao): fix the following computation\n const int num_ctas_per_sm = max_smem_per_sm > (16 * HEAD_DIM * sizeof(DTypeQ) * 16) ? 2 : 1;\n const int max_smem_per_threadblock = max_smem_per_sm / num_ctas_per_sm;\n\n const uint32_t max_num_frags_kv_reg =\n (HEAD_DIM >= 128 && NUM_FRAGS_Q == 2 && POS_ENCODING_MODE == PosEncodingMode::kRoPELlama &&\n !ALLOW_FP16_QK_REDUCTION)\n ? 2\n : (8 / NUM_FRAGS_Q);\n // TODO(Zihao): fix the following computation\n const uint32_t max_num_frags_kv_smem =\n (max_smem_per_threadblock / (16 * HEAD_DIM * sizeof(DTypeQ)) - NUM_FRAGS_Q * NUM_WARPS_Q) /\n (2 * NUM_WARPS_KV);\n\n // control NUM_FRAGS_KV for maximum warp occupancy\n DISPATCH_NUM_FRAGS_KV(min(max_num_frags_kv_smem, max_num_frags_kv_reg), NUM_FRAGS_KV, {\n if constexpr (is_invalid_configuration<POS_ENCODING_MODE, DTypeKV, DTypeQKAccum>(\n NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV, NUM_WARPS_Q, NUM_WARPS_KV)) {\n // Invalid configuration, skip\n std::ostringstream err_msg;\n err_msg << \"FlashInfer Internal Error: Invalid configuration : NUM_FRAGS_Q=\" << NUM_FRAGS_Q\n << \" NUM_FRAGS_D=\" << NUM_FRAGS_D << \" NUM_FRAGS_KV=\" << NUM_FRAGS_KV\n << \" NUM_WARPS_Q=\" << NUM_WARPS_Q << \" NUM_WARPS_KV=\" << NUM_WARPS_KV\n << \" please create an issue (https://github.com/flashinfer-ai/flashinfer/issues)\"\n \" and report the issue to the developers.\";\n throw std::invalid_argument(err_msg.str());\n } else {\n constexpr uint32_t num_threads = (NUM_WARPS_Q * NUM_WARPS_KV) * WARP_SIZE;\n constexpr uint32_t num_rows_per_cta = NUM_FRAGS_Q * NUM_WARPS_Q * 16;\n auto kernel = SinglePrefillWithKVCacheKernel<MASK_MODE, POS_ENCODING_MODE, NUM_FRAGS_Q,\n NUM_FRAGS_D, NUM_FRAGS_KV, NUM_WARPS_Q,\n NUM_WARPS_KV, DTypeQKAccum, AttentionVariant>;\n // TODO(Zihao): fix the following computation\n uint32_t smem_size = (NUM_FRAGS_Q * NUM_WARPS_Q * sizeof(DTypeQ) +\n NUM_FRAGS_KV * NUM_WARPS_KV * 2 * sizeof(DTypeQ)) *\n 16 * HEAD_DIM;\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n int num_blocks_per_sm = 0;\n int num_sm = 0;\n FLASHINFER_CUDA_CALL(\n cudaDeviceGetAttribute(&num_sm, cudaDevAttrMultiProcessorCount, dev_id));\n FLASHINFER_CUDA_CALL(cudaOccupancyMaxActiveBlocksPerMultiprocessor(\n &num_blocks_per_sm, kernel, num_threads, smem_size));\n uint32_t max_num_kv_chunks =\n (num_blocks_per_sm * num_sm) /\n (num_kv_heads * ceil_div(qo_len * group_size, num_rows_per_cta));\n uint32_t num_chunks;\n if (max_num_kv_chunks > 0) {\n uint32_t chunk_size = max(ceil_div(kv_len, max_num_kv_chunks), 256);\n num_chunks = ceil_div(kv_len, chunk_size);\n } else {\n num_chunks = 0;\n }\n\n if (num_chunks <= 1 || tmp == nullptr) {\n // Enough parallelism, do not split-kv\n params.partition_kv = false;\n void* args[] = {(void*)&group_size_fastdiv, (void*)¶ms};\n dim3 nblks(ceil_div(qo_len * group_size, num_rows_per_cta), 1, num_kv_heads);\n dim3 nthrs(32, NUM_WARPS_Q, NUM_WARPS_KV);\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n } else {\n // Use cooperative groups to increase occupancy\n params.partition_kv = true;\n float* tmp_lse = (float*)(tmp + num_chunks * qo_len * num_qo_heads * HEAD_DIM);\n auto o = params.o;\n auto lse = params.lse;\n params.o = tmp;\n params.lse = tmp_lse;\n void* args[] = {(void*)&group_size_fastdiv, (void*)¶ms};\n dim3 nblks(ceil_div(qo_len * group_size, num_rows_per_cta), num_chunks, num_kv_heads);\n dim3 nthrs(32, NUM_WARPS_Q, NUM_WARPS_KV);\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n if constexpr (AttentionVariant::use_softmax) {\n FLASHINFER_CUDA_CALL(MergeStates(tmp, tmp_lse, o, lse, num_chunks, qo_len, num_qo_heads,\n HEAD_DIM, stream));\n } else {\n FLASHINFER_CUDA_CALL(\n AttentionSum(tmp, o, num_chunks, qo_len, num_qo_heads, HEAD_DIM, stream));\n }\n }\n }\n })\n });\n return cudaSuccess;\n}\n\ntemplate <MaskMode MASK_MODE, PosEncodingMode POS_ENCODING_MODE, uint32_t NUM_FRAGS_Q,\n uint32_t NUM_FRAGS_D, uint32_t NUM_FRAGS_KV, uint32_t NUM_WARPS_Q, uint32_t NUM_WARPS_KV,\n typename DTypeQKAccum, typename AttentionVariant>\n__global__\n__launch_bounds__(NUM_WARPS_Q* NUM_WARPS_KV* WARP_SIZE) void BatchPrefillWithRaggedKVCacheKernel(\n const uint_fastdiv group_size,\n const __grid_constant__ typename AttentionVariant::ParamsT params) {\n using DTypeQ = typename AttentionVariant::DTypeQ;\n#if (__CUDA_ARCH__ < 800)\n if constexpr (std::is_same_v<DTypeQ, nv_bfloat16>) {\n FLASHINFER_RUNTIME_ASSERT(\"Prefill kernels do not support bf16 on sm75.\");\n } else {\n#endif\n using DTypeKV = typename AttentionVariant::DTypeKV;\n using DTypeO = typename AttentionVariant::DTypeO;\n using IdType = typename AttentionVariant::IdType;\n DTypeQ* q = params.q;\n IdType* request_indices = params.request_indices;\n IdType* qo_tile_indices = params.qo_tile_indices;\n IdType* kv_tile_indices = params.kv_tile_indices;\n IdType* q_indptr = params.q_indptr;\n IdType* kv_indptr = params.kv_indptr;\n DTypeKV* k = params.k;\n DTypeKV* v = params.v;\n IdType* q_offset = params.q_offset;\n IdType* k_rope_pos_offset = params.k_rope_pos_offset;\n IdType* o_indptr = params.o_indptr;\n DTypeO* o = params.o;\n float* lse = params.lse;\n bool* block_valid_mask = params.block_valid_mask;\n const bool partition_kv = params.partition_kv;\n const uint32_t q_stride_n = params.q_stride_n;\n const uint32_t q_stride_h = params.q_stride_h;\n const uint32_t kv_stride_n = params.kv_stride_n;\n const uint32_t kv_stride_h = params.kv_stride_h;\n const int32_t maybe_window_left = params.window_left;\n\n static_assert(sizeof(DTypeQ) == 2);\n static_assert(sizeof(DTypeO) == 2);\n constexpr uint32_t head_dim = NUM_FRAGS_D * 16;\n const uint32_t kv_chunk_size = *(params.kv_chunk_size_ptr);\n\n auto block = cg::this_thread_block();\n const uint32_t bx = blockIdx.x, lane_idx = threadIdx.x,\n warp_idx = get_warp_idx<NUM_WARPS_Q, NUM_WARPS_KV>(), kv_head_idx = blockIdx.z;\n if (block_valid_mask && !block_valid_mask[bx]) {\n return;\n }\n const uint32_t num_kv_heads = gridDim.z, num_qo_heads = group_size * num_kv_heads;\n const uint32_t request_idx = request_indices[bx], qo_tile_idx = qo_tile_indices[bx],\n kv_tile_idx = kv_tile_indices[bx];\n constexpr uint32_t num_rows_per_cta = NUM_FRAGS_Q * NUM_WARPS_Q * 16;\n extern __shared__ uint8_t smem[];\n AttentionVariant variant(params, /*batch_idx=*/request_idx, smem);\n const uint32_t qo_len = variant.qo_len, kv_len = variant.kv_len,\n window_left = variant.window_left;\n const uint32_t kv_len_safe = kv_len > 0 ? kv_len : 1;\n const uint32_t max_chunk_size = partition_kv ? kv_chunk_size : kv_len;\n const uint32_t chunk_start = partition_kv ? kv_tile_idx * max_chunk_size : 0;\n const uint32_t chunk_end =\n partition_kv ? min((kv_tile_idx + 1) * max_chunk_size, kv_len) : kv_len;\n const uint32_t chunk_size = chunk_end - chunk_start;\n const tensor_info_t qkv_info(qo_len, kv_len, num_qo_heads, num_kv_heads, q_stride_n, q_stride_h,\n kv_stride_n, kv_stride_h, /*head_dim=*/NUM_FRAGS_D * 16);\n const uint32_t qo_upper_bound =\n min(qo_len, ceil_div((qo_tile_idx + 1) * num_rows_per_cta, group_size));\n\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<DTypeKV>();\n constexpr uint32_t channel_size_128b_out = head_dim / num_elems_per_128b<DTypeO>();\n\n DTypeQKAccum s_frag[NUM_FRAGS_Q][NUM_FRAGS_KV][8];\n float o_frag[NUM_FRAGS_Q][NUM_FRAGS_D][8];\n DTypeQKAccum m[NUM_FRAGS_Q][2];\n float d[NUM_FRAGS_Q][2];\n float rope_freq[NUM_FRAGS_D / 2][4];\n\n if constexpr (POS_ENCODING_MODE == PosEncodingMode::kRoPELlama) {\n const float log2_rope_rcp_scale = params.log2_rope_rcp_scale;\n const float log2_rope_rcp_theta = params.log2_rope_rcp_theta;\n init_rope_freq<NUM_FRAGS_D>(rope_freq, log2_rope_rcp_scale, log2_rope_rcp_theta);\n }\n init_states<NUM_FRAGS_Q, NUM_FRAGS_D>(variant, o_frag, m, d);\n\n const uint32_t qo_packed_idx_base =\n (qo_tile_idx * NUM_WARPS_Q + get_warp_idx_q<NUM_WARPS_Q, NUM_WARPS_KV>()) * NUM_FRAGS_Q *\n 16;\n constexpr SwizzleMode swizzle_mode_q = SwizzleMode::k128B;\n smem_t<swizzle_mode_q> qo_smem(smem);\n\n DTypeQ* q_ptr_base =\n q + qkv_info.get_q_elem_offset(q_indptr[request_idx], kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeQ>());\n\n DTypeO* o_ptr_base =\n partition_kv\n ? o + kv_tile_idx * num_qo_heads * head_dim +\n qkv_info.get_o_elem_offset(o_indptr[request_idx], kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeO>())\n : o + qkv_info.get_o_elem_offset(o_indptr[request_idx], kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeO>());\n\n uint32_t q_smem_offset_r = qo_smem.get_permuted_offset<channel_size_128b_q>(\n get_warp_idx_q<NUM_WARPS_Q, NUM_WARPS_KV>() * NUM_FRAGS_Q * 16 + lane_idx % 16,\n lane_idx / 16);\n\n load_q_global_smem<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_Q, NUM_FRAGS_D>(\n qo_packed_idx_base, qo_upper_bound, q_ptr_base, q_stride_n, q_stride_h, group_size,\n &qo_smem);\n\n cp_async::commit_group();\n cp_async::wait_group<0>();\n block.sync();\n\n if constexpr (POS_ENCODING_MODE == PosEncodingMode::kRoPELlama) {\n if (!q_offset) {\n q_smem_inplace_apply_rotary<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_Q, NUM_FRAGS_D,\n swizzle_mode_q, DTypeQ>(\n qo_packed_idx_base, qo_len, kv_len, group_size, &qo_smem, &q_smem_offset_r, rope_freq);\n } else {\n q_smem_inplace_apply_rotary_with_pos<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_Q, NUM_FRAGS_D,\n swizzle_mode_q, DTypeQ>(\n qo_packed_idx_base, q_offset + q_indptr[request_idx], &qo_smem, group_size,\n &q_smem_offset_r, rope_freq);\n }\n block.sync();\n }\n q_smem_inplace_transform<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_Q, NUM_FRAGS_D, swizzle_mode_q>(\n params, variant, &qo_smem);\n\n const uint32_t num_iterations = ceil_div(\n (MASK_MODE == MaskMode::kCausal\n ? min(chunk_size,\n sub_if_greater_or_zero(\n kv_len - qo_len + ((qo_tile_idx + 1) * num_rows_per_cta) / group_size,\n chunk_start))\n : chunk_size),\n 16 * NUM_WARPS_KV * NUM_FRAGS_KV);\n\n const uint32_t window_iteration =\n ceil_div(sub_if_greater_or_zero(kv_len + (qo_tile_idx + 1) * num_rows_per_cta,\n qo_len + window_left + chunk_start),\n (16 * NUM_WARPS_KV * NUM_FRAGS_KV));\n\n const uint32_t mask_iteration =\n (MASK_MODE == MaskMode::kCausal\n ? min(chunk_size, sub_if_greater_or_zero(\n kv_len + (qo_tile_idx * num_rows_per_cta) / group_size - qo_len,\n chunk_start))\n : chunk_size) /\n (16 * NUM_WARPS_KV * NUM_FRAGS_KV);\n\n constexpr SwizzleMode swizzle_mode_kv =\n (sizeof(DTypeKV) == 1 && head_dim == 64) ? SwizzleMode::k64B : SwizzleMode::k128B;\n constexpr uint32_t kv_frag_rows = swizzle_mode_kv == SwizzleMode::k128B ? 4 : 8;\n constexpr uint32_t kv_frag_cols = swizzle_mode_kv == SwizzleMode::k128B ? 8 : 4;\n smem_t<swizzle_mode_kv> k_smem(smem +\n (NUM_WARPS_Q * NUM_FRAGS_Q * sizeof(DTypeQ)) * 16 * head_dim),\n v_smem(smem + (NUM_WARPS_Q * NUM_FRAGS_Q * sizeof(DTypeQ) +\n NUM_WARPS_KV * NUM_FRAGS_KV * sizeof(DTypeKV)) *\n 16 * head_dim);\n\n uint32_t k_smem_offset_r = k_smem.get_permuted_offset<channel_size_128b_kv>(\n get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>() * NUM_FRAGS_KV * 16 +\n 8 * (lane_idx / 16) + lane_idx % 8,\n (lane_idx % 16) / 8),\n v_smem_offset_r = v_smem.get_permuted_offset<channel_size_128b_kv>(\n get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>() * NUM_FRAGS_KV * 16 + lane_idx % 16,\n lane_idx / 16),\n kv_smem_offset_w = k_smem.get_permuted_offset<channel_size_128b_kv>(\n warp_idx * kv_frag_rows + lane_idx / kv_frag_cols, lane_idx % kv_frag_cols);\n\n DTypeKV* k_ptr =\n k + qkv_info.get_kv_elem_offset(kv_indptr[request_idx] + chunk_start +\n warp_idx * kv_frag_rows + lane_idx / kv_frag_cols,\n kv_head_idx,\n (lane_idx % kv_frag_cols) * num_elems_per_128b<DTypeKV>());\n DTypeKV* v_ptr =\n v + qkv_info.get_kv_elem_offset(kv_indptr[request_idx] + chunk_start +\n warp_idx * kv_frag_rows + lane_idx / kv_frag_cols,\n kv_head_idx,\n (lane_idx % kv_frag_cols) * num_elems_per_128b<DTypeKV>());\n\n produce_kv<SharedMemFillMode::kNoFill, NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_D, NUM_FRAGS_KV>(\n k_smem, &kv_smem_offset_w, &k_ptr, kv_stride_n, 0, chunk_size);\n cp_async::commit_group();\n produce_kv<SharedMemFillMode::kFillZero, NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_D, NUM_FRAGS_KV>(\n v_smem, &kv_smem_offset_w, &v_ptr, kv_stride_n, 0, chunk_size);\n cp_async::commit_group();\n\n#pragma unroll 1\n for (uint32_t iter = 0; iter < num_iterations; ++iter) {\n cp_async::wait_group<1>();\n block.sync();\n\n if constexpr (POS_ENCODING_MODE == PosEncodingMode::kRoPELlama) {\n k_smem_inplace_apply_rotary<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_D, NUM_FRAGS_KV,\n swizzle_mode_kv, DTypeKV>(\n (k_rope_pos_offset == nullptr ? 0 : k_rope_pos_offset[request_idx]) + chunk_start +\n iter * 16 * NUM_WARPS_KV * NUM_FRAGS_KV,\n &k_smem, &k_smem_offset_r, rope_freq);\n block.sync();\n }\n\n // compute attention score\n compute_qk<NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV, swizzle_mode_q, swizzle_mode_kv, DTypeQ,\n DTypeKV>(&qo_smem, &q_smem_offset_r, &k_smem, &k_smem_offset_r, s_frag);\n\n logits_transform<NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV>(\n params, variant, /*batch_idx=*/request_idx, qo_packed_idx_base,\n chunk_start + (iter * NUM_WARPS_KV + get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>()) *\n NUM_FRAGS_KV * 16,\n qo_len, kv_len, group_size, s_frag);\n\n // apply mask\n if (MASK_MODE == MaskMode::kCustom || (iter >= mask_iteration || iter < window_iteration)) {\n logits_mask<MASK_MODE, NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV>(\n params, variant, /*batch_idx=*/request_idx, qo_packed_idx_base,\n chunk_start + (iter * NUM_WARPS_KV + get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>()) *\n NUM_FRAGS_KV * 16,\n qo_len, kv_len, chunk_end, group_size, s_frag);\n }\n\n // compute m,d states in online softmax\n update_mdo_states<NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV>(variant, s_frag, o_frag, m, d);\n\n block.sync();\n produce_kv<SharedMemFillMode::kNoFill, NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_D, NUM_FRAGS_KV>(\n k_smem, &kv_smem_offset_w, &k_ptr, kv_stride_n,\n (iter + 1) * 16 * NUM_WARPS_KV * NUM_FRAGS_KV, chunk_size);\n cp_async::commit_group();\n cp_async::wait_group<1>();\n block.sync();\n\n // compute sfm*v\n compute_sfm_v<NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV, swizzle_mode_kv, DTypeQ, DTypeKV>(\n variant, &v_smem, &v_smem_offset_r, s_frag, o_frag, d);\n\n block.sync();\n produce_kv<SharedMemFillMode::kFillZero, NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_D,\n NUM_FRAGS_KV>(v_smem, &kv_smem_offset_w, &v_ptr, kv_stride_n,\n (iter + 1) * 16 * NUM_WARPS_KV * NUM_FRAGS_KV, chunk_size);\n cp_async::commit_group();\n }\n cp_async::wait_group<0>();\n block.sync();\n\n // threadblock synchronization\n threadblock_sync_mdo_states<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_Q, NUM_FRAGS_D, DTypeQKAccum>(\n variant, o_frag, (float*)smem, m, d, warp_idx, lane_idx);\n\n // normalize d\n normalize_d<NUM_FRAGS_Q, NUM_FRAGS_D>(variant, o_frag, m, d);\n\n const uint32_t num_kv_chunks = (kv_len_safe + kv_chunk_size - 1) / kv_chunk_size;\n\n // write back\n write_o_reg_gmem<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_Q, NUM_FRAGS_D>(\n o_frag, &qo_smem, o_ptr_base, qo_packed_idx_base, qo_len,\n /*o_stride_n=*/\n partition_kv ? num_qo_heads * head_dim * num_kv_chunks : num_qo_heads * head_dim,\n /*o_stride_h=*/head_dim, group_size);\n\n // write lse\n if constexpr (variant.use_softmax) {\n if (lse != nullptr) {\n if (get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>() == 0) {\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n uint32_t q, r;\n group_size.divmod(qo_packed_idx_base + lane_idx / 4 + j * 8 + fq * 16, q, r);\n const uint32_t qo_head_idx = kv_head_idx * group_size + r;\n const uint32_t qo_idx = q;\n if (qo_idx < qo_len) {\n if (partition_kv) {\n lse[(o_indptr[request_idx] + qo_idx * num_kv_chunks + kv_tile_idx) *\n num_qo_heads +\n qo_head_idx] = math::ptx_log2(d[fq][j]) + float(m[fq][j]);\n } else {\n lse[(o_indptr[request_idx] + qo_idx) * num_qo_heads + qo_head_idx] =\n math::ptx_log2(d[fq][j]) + float(m[fq][j]);\n }\n }\n }\n }\n }\n }\n }\n#if (__CUDA_ARCH__ < 800)\n }\n#endif\n}\n\ntemplate <MaskMode MASK_MODE, PosEncodingMode POS_ENCODING_MODE, uint32_t NUM_FRAGS_Q,\n uint32_t NUM_FRAGS_D, uint32_t NUM_FRAGS_KV, uint32_t NUM_WARPS_Q, uint32_t NUM_WARPS_KV,\n typename DTypeQKAccum, typename AttentionVariant>\n__global__\n__launch_bounds__(NUM_WARPS_Q* NUM_WARPS_KV* WARP_SIZE) void BatchPrefillWithPagedKVCacheKernel(\n const uint_fastdiv group_size,\n const __grid_constant__ typename AttentionVariant::ParamsT params) {\n using DTypeQ = typename AttentionVariant::DTypeQ;\n#if (__CUDA_ARCH__ < 800)\n if constexpr (std::is_same_v<DTypeQ, nv_bfloat16>) {\n FLASHINFER_RUNTIME_ASSERT(\"Prefill kernels do not support bf16 on sm75.\");\n } else {\n#endif\n using DTypeKV = typename AttentionVariant::DTypeKV;\n using DTypeO = typename AttentionVariant::DTypeO;\n using IdType = typename AttentionVariant::IdType;\n IdType* request_indices = params.request_indices;\n IdType* qo_tile_indices = params.qo_tile_indices;\n IdType* kv_tile_indices = params.kv_tile_indices;\n DTypeQ* q = params.q;\n IdType* q_indptr = params.q_indptr;\n IdType* q_offset = params.q_offset;\n IdType* o_indptr = params.o_indptr;\n DTypeO* o = params.o;\n float* lse = params.lse;\n bool* block_valid_mask = params.block_valid_mask;\n const paged_kv_t<DTypeKV, IdType>& paged_kv = params.paged_kv;\n const bool partition_kv = params.partition_kv;\n const int32_t maybe_window_left = params.window_left;\n\n static_assert(sizeof(DTypeQ) == 2);\n static_assert(sizeof(DTypeO) == 2);\n auto block = cg::this_thread_block();\n const uint32_t kv_chunk_size = *(params.kv_chunk_size_ptr);\n\n const uint32_t bx = blockIdx.x, lane_idx = threadIdx.x,\n warp_idx = get_warp_idx<NUM_WARPS_Q, NUM_WARPS_KV>(), kv_head_idx = blockIdx.z;\n if (block_valid_mask && !block_valid_mask[bx]) {\n return;\n }\n const uint32_t num_kv_heads = gridDim.z, num_qo_heads = num_kv_heads * group_size;\n\n const uint32_t request_idx = request_indices[bx], qo_tile_idx = qo_tile_indices[bx],\n kv_tile_idx = kv_tile_indices[bx];\n constexpr uint32_t num_rows_per_cta = NUM_FRAGS_Q * NUM_WARPS_Q * 16;\n extern __shared__ uint8_t smem[];\n AttentionVariant variant(params, /*batch_idx=*/request_idx, smem);\n const uint32_t qo_len = variant.qo_len, kv_len = variant.kv_len,\n window_left = variant.window_left;\n const uint32_t kv_len_safe = kv_len > 0 ? kv_len : 1;\n const uint32_t max_chunk_size = partition_kv ? kv_chunk_size : kv_len;\n const uint32_t chunk_start = partition_kv ? kv_tile_idx * max_chunk_size : 0;\n const uint32_t chunk_end =\n partition_kv ? min((kv_tile_idx + 1) * max_chunk_size, kv_len) : kv_len;\n const uint32_t chunk_size = chunk_end - chunk_start;\n const uint32_t qo_upper_bound =\n min(qo_len, ceil_div((qo_tile_idx + 1) * num_rows_per_cta, group_size));\n\n constexpr uint32_t head_dim = NUM_FRAGS_D * 16;\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<DTypeKV>();\n constexpr uint32_t channel_size_128b_out = head_dim / num_elems_per_128b<DTypeO>();\n\n DTypeQKAccum s_frag[NUM_FRAGS_Q][NUM_FRAGS_KV][8];\n float o_frag[NUM_FRAGS_Q][NUM_FRAGS_D][8];\n DTypeQKAccum m[NUM_FRAGS_Q][2];\n float d[NUM_FRAGS_Q][2];\n float rope_freq[NUM_FRAGS_D / 2][4];\n\n if constexpr (POS_ENCODING_MODE == PosEncodingMode::kRoPELlama) {\n const float log2_rope_rcp_scale = params.log2_rope_rcp_scale;\n const float log2_rope_rcp_theta = params.log2_rope_rcp_theta;\n init_rope_freq<NUM_FRAGS_D>(rope_freq, log2_rope_rcp_scale, log2_rope_rcp_theta);\n }\n init_states<NUM_FRAGS_Q, NUM_FRAGS_D>(variant, o_frag, m, d);\n\n const uint32_t qo_packed_idx_base =\n (qo_tile_idx * NUM_WARPS_Q + get_warp_idx_q<NUM_WARPS_Q, NUM_WARPS_KV>()) * NUM_FRAGS_Q *\n 16;\n const uint32_t q_stride_n = params.q_stride_n, q_stride_h = params.q_stride_h;\n constexpr SwizzleMode swizzle_mode_q = SwizzleMode::k128B;\n smem_t<swizzle_mode_q> qo_smem(smem);\n DTypeQ* q_ptr_base = q + get_elem_offset_impl(q_indptr[request_idx], kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeQ>(),\n q_stride_n, q_stride_h);\n DTypeO* o_ptr_base =\n partition_kv ? o + kv_tile_idx * num_qo_heads * head_dim +\n get_elem_offset_impl(o_indptr[request_idx], kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeO>(),\n num_qo_heads * head_dim, head_dim)\n : o + get_elem_offset_impl(o_indptr[request_idx], kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeO>(),\n num_qo_heads * head_dim, head_dim);\n uint32_t q_smem_offset_r = qo_smem.get_permuted_offset<channel_size_128b_q>(\n get_warp_idx_q<NUM_WARPS_Q, NUM_WARPS_KV>() * NUM_FRAGS_Q * 16 + lane_idx % 16,\n lane_idx / 16);\n\n load_q_global_smem<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_Q, NUM_FRAGS_D>(\n qo_packed_idx_base, qo_upper_bound, q_ptr_base, q_stride_n, q_stride_h, group_size,\n &qo_smem);\n\n cp_async::commit_group();\n cp_async::wait_group<0>();\n block.sync();\n\n if constexpr (POS_ENCODING_MODE == PosEncodingMode::kRoPELlama) {\n if (q_offset == nullptr) {\n q_smem_inplace_apply_rotary<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_Q, NUM_FRAGS_D,\n swizzle_mode_q, DTypeQ>(\n qo_packed_idx_base, qo_len, kv_len, group_size, &qo_smem, &q_smem_offset_r, rope_freq);\n } else {\n q_smem_inplace_apply_rotary_with_pos<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_Q, NUM_FRAGS_D,\n swizzle_mode_q, DTypeQ>(\n qo_packed_idx_base, q_offset + q_indptr[request_idx], &qo_smem, group_size,\n &q_smem_offset_r, rope_freq);\n }\n block.sync();\n }\n q_smem_inplace_transform<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_Q, NUM_FRAGS_D, swizzle_mode_q>(\n params, variant, &qo_smem);\n\n constexpr SwizzleMode swizzle_mode_kv =\n (sizeof(DTypeKV) == 1 && head_dim == 64) ? SwizzleMode::k64B : SwizzleMode::k128B;\n constexpr uint32_t kv_frag_rows = swizzle_mode_kv == SwizzleMode::k128B ? 4 : 8;\n constexpr uint32_t kv_frag_cols = swizzle_mode_kv == SwizzleMode::k128B ? 8 : 4;\n smem_t<swizzle_mode_kv> k_smem(smem +\n (NUM_WARPS_Q * NUM_FRAGS_Q * sizeof(DTypeQ)) * 16 * head_dim),\n v_smem(smem + (NUM_WARPS_Q * NUM_FRAGS_Q * sizeof(DTypeQ) +\n NUM_WARPS_KV * NUM_FRAGS_KV * sizeof(DTypeKV)) *\n 16 * head_dim);\n size_t kv_offset[NUM_FRAGS_KV * (swizzle_mode_kv == SwizzleMode::k128B ? 4 : 2) / NUM_WARPS_Q];\n\n uint32_t k_smem_offset_r = k_smem.get_permuted_offset<channel_size_128b_kv>(\n get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>() * NUM_FRAGS_KV * 16 +\n 8 * (lane_idx / 16) + lane_idx % 8,\n (lane_idx % 16) / 8),\n v_smem_offset_r = v_smem.get_permuted_offset<channel_size_128b_kv>(\n get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>() * NUM_FRAGS_KV * 16 + lane_idx % 16,\n lane_idx / 16),\n kv_smem_offset_w = k_smem.get_permuted_offset<channel_size_128b_kv>(\n warp_idx * kv_frag_rows + lane_idx / kv_frag_cols, lane_idx % kv_frag_cols);\n const IdType last_indptr = paged_kv.indptr[paged_kv.batch_size];\n\n uint32_t packed_page_iter_base =\n paged_kv.indptr[request_idx] * paged_kv.page_size + chunk_start;\n#pragma unroll\n for (uint32_t i = 0;\n i < NUM_FRAGS_KV * (swizzle_mode_kv == SwizzleMode::k128B ? 4 : 2) / NUM_WARPS_Q; ++i) {\n uint32_t page_iter, entry_idx;\n paged_kv.page_size.divmod(packed_page_iter_base + warp_idx * kv_frag_rows +\n lane_idx / kv_frag_cols +\n kv_frag_rows * NUM_WARPS_Q * NUM_WARPS_KV * i,\n page_iter, entry_idx);\n kv_offset[i] = paged_kv.protective_get_kv_offset(\n page_iter, kv_head_idx, entry_idx,\n (lane_idx % kv_frag_cols) * num_elems_per_128b<DTypeKV>(), last_indptr);\n }\n page_produce_kv<false, NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_D, NUM_FRAGS_KV>(\n k_smem, &kv_smem_offset_w, paged_kv, 0, kv_offset, chunk_size);\n cp_async::commit_group();\n page_produce_kv<true, NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_D, NUM_FRAGS_KV>(\n v_smem, &kv_smem_offset_w, paged_kv, 0, kv_offset, chunk_size);\n cp_async::commit_group();\n\n const uint32_t num_iterations = ceil_div(\n (MASK_MODE == MaskMode::kCausal\n ? min(chunk_size,\n sub_if_greater_or_zero(\n kv_len - qo_len + ((qo_tile_idx + 1) * num_rows_per_cta) / group_size,\n chunk_start))\n : chunk_size),\n 16 * NUM_WARPS_KV * NUM_FRAGS_KV);\n\n const uint32_t window_iteration =\n ceil_div(sub_if_greater_or_zero(kv_len + (qo_tile_idx + 1) * num_rows_per_cta,\n qo_len + window_left + chunk_start),\n (16 * NUM_WARPS_KV * NUM_FRAGS_KV));\n\n const uint32_t mask_iteration =\n (MASK_MODE == MaskMode::kCausal\n ? min(chunk_size, sub_if_greater_or_zero(\n kv_len + (qo_tile_idx * num_rows_per_cta) / group_size - qo_len,\n chunk_start))\n : chunk_size) /\n (16 * NUM_WARPS_KV * NUM_FRAGS_KV);\n\n#pragma unroll 1\n for (uint32_t iter = 0; iter < num_iterations; ++iter) {\n packed_page_iter_base += 16 * NUM_WARPS_KV * NUM_FRAGS_KV;\n#pragma unroll\n for (uint32_t i = 0;\n i < NUM_FRAGS_KV * (swizzle_mode_kv == SwizzleMode::k128B ? 4 : 2) / NUM_WARPS_Q; ++i) {\n uint32_t page_iter, entry_idx;\n paged_kv.page_size.divmod(packed_page_iter_base + warp_idx * kv_frag_rows +\n lane_idx / kv_frag_cols +\n kv_frag_rows * NUM_WARPS_Q * NUM_WARPS_KV * i,\n page_iter, entry_idx);\n kv_offset[i] = paged_kv.protective_get_kv_offset(\n page_iter, kv_head_idx, entry_idx,\n (lane_idx % kv_frag_cols) * num_elems_per_128b<DTypeKV>(), last_indptr);\n }\n cp_async::wait_group<1>();\n block.sync();\n\n if constexpr (POS_ENCODING_MODE == PosEncodingMode::kRoPELlama) {\n k_smem_inplace_apply_rotary<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_D, NUM_FRAGS_KV,\n swizzle_mode_kv, DTypeKV>(\n (paged_kv.rope_pos_offset == nullptr ? 0 : paged_kv.rope_pos_offset[request_idx]) +\n chunk_start + iter * 16 * NUM_WARPS_KV * NUM_FRAGS_KV,\n &k_smem, &k_smem_offset_r, rope_freq);\n block.sync();\n }\n\n // compute attention score\n compute_qk<NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV, swizzle_mode_q, swizzle_mode_kv, DTypeQ,\n DTypeKV>(&qo_smem, &q_smem_offset_r, &k_smem, &k_smem_offset_r, s_frag);\n\n logits_transform<NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV>(\n params, variant, /*batch_idx=*/request_idx, qo_packed_idx_base,\n chunk_start + (iter * NUM_WARPS_KV + get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>()) *\n NUM_FRAGS_KV * 16,\n qo_len, kv_len, group_size, s_frag);\n\n // apply mask\n if (MASK_MODE == MaskMode::kCustom || (iter >= mask_iteration || iter < window_iteration)) {\n logits_mask<MASK_MODE, NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV>(\n params, variant, /*batch_idx=*/request_idx, qo_packed_idx_base,\n chunk_start + (iter * NUM_WARPS_KV + get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>()) *\n NUM_FRAGS_KV * 16,\n qo_len, kv_len, chunk_end, group_size, s_frag);\n }\n\n // compute m,d states in online softmax\n update_mdo_states<NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV>(variant, s_frag, o_frag, m, d);\n\n block.sync();\n page_produce_kv<false, NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_D, NUM_FRAGS_KV>(\n k_smem, &kv_smem_offset_w, paged_kv, (iter + 1) * 16 * NUM_WARPS_KV * NUM_FRAGS_KV,\n kv_offset, chunk_size);\n cp_async::commit_group();\n cp_async::wait_group<1>();\n block.sync();\n\n // compute sfm*v\n compute_sfm_v<NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV, swizzle_mode_kv, DTypeQ, DTypeKV>(\n variant, &v_smem, &v_smem_offset_r, s_frag, o_frag, d);\n\n block.sync();\n page_produce_kv<true, NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_D, NUM_FRAGS_KV>(\n v_smem, &kv_smem_offset_w, paged_kv, (iter + 1) * 16 * NUM_WARPS_KV * NUM_FRAGS_KV,\n kv_offset, chunk_size);\n cp_async::commit_group();\n }\n cp_async::wait_group<0>();\n block.sync();\n\n // threadblock synchronization\n threadblock_sync_mdo_states<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_Q, NUM_FRAGS_D, DTypeQKAccum>(\n variant, o_frag, (float*)smem, m, d, warp_idx, lane_idx);\n\n // normalize d\n normalize_d<NUM_FRAGS_Q, NUM_FRAGS_D>(variant, o_frag, m, d);\n\n const uint32_t num_kv_chunks = (kv_len_safe + kv_chunk_size - 1) / kv_chunk_size;\n\n // write_back\n write_o_reg_gmem<NUM_WARPS_Q, NUM_WARPS_KV, NUM_FRAGS_Q, NUM_FRAGS_D>(\n o_frag, &qo_smem, o_ptr_base, qo_packed_idx_base, qo_len,\n /*o_stride_n=*/\n partition_kv ? num_qo_heads * head_dim * num_kv_chunks : num_qo_heads * head_dim,\n /*o_stride_h=*/head_dim, group_size);\n\n // write lse\n if constexpr (variant.use_softmax) {\n if (lse != nullptr) {\n if (get_warp_idx_kv<NUM_WARPS_Q, NUM_WARPS_KV>() == 0) {\n#pragma unroll\n for (uint32_t fq = 0; fq < NUM_FRAGS_Q; ++fq) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n uint32_t q, r;\n group_size.divmod(qo_packed_idx_base + lane_idx / 4 + j * 8 + fq * 16, q, r);\n const uint32_t qo_head_idx = kv_head_idx * group_size + r;\n const uint32_t qo_idx = q;\n if (qo_idx < qo_upper_bound) {\n if (partition_kv) {\n lse[(o_indptr[request_idx] + qo_idx * num_kv_chunks + kv_tile_idx) *\n num_qo_heads +\n qo_head_idx] = math::ptx_log2(d[fq][j]) + float(m[fq][j]);\n } else {\n lse[(o_indptr[request_idx] + qo_idx) * num_qo_heads + qo_head_idx] =\n math::ptx_log2(d[fq][j]) + float(m[fq][j]);\n }\n }\n }\n }\n }\n }\n }\n#if (__CUDA_ARCH__ < 800)\n }\n#endif\n}\n\ntemplate <uint32_t CTA_TILE_Q, uint32_t HEAD_DIM, PosEncodingMode POS_ENCODING_MODE,\n bool ALLOW_FP16_QK_REDUCTION, MaskMode MASK_MODE, typename AttentionVariant>\ncudaError_t BatchPrefillWithRaggedKVCacheDispatched(typename AttentionVariant::ParamsT params,\n typename AttentionVariant::DTypeO* tmp_v,\n float* tmp_s, cudaStream_t stream) {\n using DTypeQ = typename AttentionVariant::DTypeQ;\n using DTypeKV = typename AttentionVariant::DTypeKV;\n const uint32_t padded_batch_size = params.padded_batch_size;\n const uint32_t num_qo_heads = params.num_qo_heads;\n const uint32_t num_kv_heads = params.num_kv_heads;\n const uint_fastdiv group_size_fastdiv(num_qo_heads / num_kv_heads);\n const uint32_t total_num_rows = params.total_num_rows;\n constexpr uint32_t NUM_FRAGS_Q = get_num_frags_q(CTA_TILE_Q);\n constexpr uint32_t NUM_WARPS_Q = get_num_warps_q(CTA_TILE_Q);\n constexpr uint32_t NUM_WARPS_KV = get_num_warps_kv(CTA_TILE_Q);\n\n if (padded_batch_size == 0) {\n // No request, skip\n // this won't happen in CUDAGraph mode because we fixed the padded_batch_size\n return cudaSuccess;\n }\n\n dim3 nblks(padded_batch_size, 1, num_kv_heads);\n dim3 nthrs(32, NUM_WARPS_Q, NUM_WARPS_KV);\n constexpr uint32_t NUM_FRAGS_D = HEAD_DIM / 16;\n using DTypeQKAccum =\n typename std::conditional<ALLOW_FP16_QK_REDUCTION && std::is_same_v<DTypeQ, half>, half,\n float>::type;\n\n int dev_id = 0;\n FLASHINFER_CUDA_CALL(cudaGetDevice(&dev_id));\n int max_smem_per_sm = 0;\n FLASHINFER_CUDA_CALL(cudaDeviceGetAttribute(&max_smem_per_sm,\n cudaDevAttrMaxSharedMemoryPerMultiprocessor, dev_id));\n // we expect each sm execute two threadblocks\n // TODO(Zihao): fix the following computation\n const int num_ctas_per_sm = max_smem_per_sm > (16 * HEAD_DIM * sizeof(DTypeQ) * 16) ? 2 : 1;\n const int max_smem_per_threadblock = max_smem_per_sm / num_ctas_per_sm;\n\n const uint32_t max_num_frags_kv_reg =\n (HEAD_DIM >= 128 && NUM_FRAGS_Q == 2 && POS_ENCODING_MODE == PosEncodingMode::kRoPELlama &&\n !ALLOW_FP16_QK_REDUCTION)\n ? 2\n : (8 / NUM_FRAGS_Q);\n // TODO(Zihao): fix the following computation\n const uint32_t max_num_frags_kv_smem =\n (max_smem_per_threadblock / (16 * HEAD_DIM * sizeof(DTypeQ)) - NUM_FRAGS_Q * NUM_WARPS_Q) /\n (2 * NUM_WARPS_KV);\n\n DISPATCH_NUM_FRAGS_KV(min(max_num_frags_kv_smem, max_num_frags_kv_reg), NUM_FRAGS_KV, {\n if constexpr (is_invalid_configuration<POS_ENCODING_MODE, DTypeKV, DTypeQKAccum>(\n NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV, NUM_WARPS_Q, NUM_WARPS_KV)) {\n // Invalid configuration, skip\n std::ostringstream err_msg;\n err_msg << \"FlashInfer Internal Error: Invalid configuration : NUM_FRAGS_Q=\" << NUM_FRAGS_Q\n << \" NUM_FRAGS_D=\" << NUM_FRAGS_D << \" NUM_FRAGS_KV=\" << NUM_FRAGS_KV\n << \" NUM_WARPS_Q=\" << NUM_WARPS_Q << \" NUM_WARPS_KV=\" << NUM_WARPS_KV\n << \" please create an issue (https://github.com/flashinfer-ai/flashinfer/issues)\"\n \" and report the issue to the developers.\";\n throw std::invalid_argument(err_msg.str());\n } else {\n // TODO(Zihao): fix the following computation\n uint32_t smem_size = (NUM_FRAGS_Q * NUM_WARPS_Q * sizeof(DTypeQ) +\n NUM_FRAGS_KV * NUM_WARPS_KV * 2 * sizeof(DTypeQ)) *\n 16 * HEAD_DIM;\n auto kernel =\n BatchPrefillWithRaggedKVCacheKernel<MASK_MODE, POS_ENCODING_MODE, NUM_FRAGS_Q,\n NUM_FRAGS_D, NUM_FRAGS_KV, NUM_WARPS_Q, NUM_WARPS_KV,\n DTypeQKAccum, AttentionVariant>;\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n if (tmp_v == nullptr) {\n // do not partition kv\n params.partition_kv = false;\n void* args[] = {(void*)&group_size_fastdiv, (void*)¶ms};\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n } else {\n // partition kv\n params.partition_kv = true;\n auto o = params.o;\n auto lse = params.lse;\n params.o = tmp_v;\n params.lse = tmp_s;\n void* args[] = {(void*)&group_size_fastdiv, (void*)¶ms};\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n if constexpr (AttentionVariant::use_softmax) {\n FLASHINFER_CUDA_CALL(VariableLengthMergeStates(tmp_v, tmp_s, params.merge_indptr, o, lse,\n total_num_rows, num_qo_heads, HEAD_DIM,\n stream));\n } else {\n FLASHINFER_CUDA_CALL(VariableLengthAttentionSum(\n tmp_v, params.merge_indptr, o, total_num_rows, num_qo_heads, HEAD_DIM, stream));\n }\n }\n }\n });\n return cudaSuccess;\n}\n\ntemplate <uint32_t CTA_TILE_Q, uint32_t HEAD_DIM, PosEncodingMode POS_ENCODING_MODE,\n bool ALLOW_FP16_QK_REDUCTION, MaskMode MASK_MODE, typename AttentionVariant>\ncudaError_t BatchPrefillWithPagedKVCacheDispatched(typename AttentionVariant::ParamsT params,\n typename AttentionVariant::DTypeO* tmp_v,\n float* tmp_s, cudaStream_t stream) {\n using DTypeQ = typename AttentionVariant::DTypeQ;\n using DTypeKV = typename AttentionVariant::DTypeKV;\n const uint32_t padded_batch_size = params.padded_batch_size;\n const uint32_t num_qo_heads = params.num_qo_heads;\n const uint32_t num_kv_heads = params.paged_kv.num_heads;\n const uint_fastdiv group_size_fastdiv(num_qo_heads / num_kv_heads);\n const uint32_t total_num_rows = params.total_num_rows;\n constexpr uint32_t NUM_FRAGS_Q = get_num_frags_q(CTA_TILE_Q);\n constexpr uint32_t NUM_WARPS_Q = get_num_warps_q(CTA_TILE_Q);\n constexpr uint32_t NUM_WARPS_KV = get_num_warps_kv(CTA_TILE_Q);\n\n if (padded_batch_size == 0) {\n // No request, skip\n // this won't happen in CUDAGraph mode because we fixed the padded_batch_size\n return cudaSuccess;\n }\n\n dim3 nblks(padded_batch_size, 1, num_kv_heads);\n dim3 nthrs(32, NUM_WARPS_Q, NUM_WARPS_KV);\n\n constexpr uint32_t NUM_FRAGS_D = HEAD_DIM / 16;\n using DTypeQKAccum =\n typename std::conditional<ALLOW_FP16_QK_REDUCTION && std::is_same_v<DTypeQ, half>, half,\n float>::type;\n\n int dev_id = 0;\n FLASHINFER_CUDA_CALL(cudaGetDevice(&dev_id));\n int max_smem_per_sm = 0;\n FLASHINFER_CUDA_CALL(cudaDeviceGetAttribute(&max_smem_per_sm,\n cudaDevAttrMaxSharedMemoryPerMultiprocessor, dev_id));\n // we expect each sm execute two threadblocks\n // TODO(Zihao): fix the following computation\n const int num_ctas_per_sm = max_smem_per_sm > (16 * HEAD_DIM * sizeof(DTypeQ) * 16) ? 2 : 1;\n const int max_smem_per_threadblock = max_smem_per_sm / num_ctas_per_sm;\n\n const uint32_t max_num_frags_kv_reg =\n (HEAD_DIM >= 128 && NUM_FRAGS_Q == 2 && POS_ENCODING_MODE == PosEncodingMode::kRoPELlama &&\n !ALLOW_FP16_QK_REDUCTION)\n ? 2\n : (8 / NUM_FRAGS_Q);\n // TODO(Zihao): fix the following computation\n const uint32_t max_num_frags_kv_smem =\n (max_smem_per_threadblock / (16 * HEAD_DIM * sizeof(DTypeQ)) - NUM_FRAGS_Q * NUM_WARPS_Q) /\n (2 * NUM_WARPS_KV);\n\n DISPATCH_NUM_FRAGS_KV(min(max_num_frags_kv_smem, max_num_frags_kv_reg), NUM_FRAGS_KV, {\n if constexpr (is_invalid_configuration<POS_ENCODING_MODE, DTypeKV, DTypeQKAccum>(\n NUM_FRAGS_Q, NUM_FRAGS_D, NUM_FRAGS_KV, NUM_WARPS_Q, NUM_WARPS_KV)) {\n // Invalid configuration, skip\n std::ostringstream err_msg;\n err_msg << \"FlashInfer Internal Error: Invalid configuration : NUM_FRAGS_Q=\" << NUM_FRAGS_Q\n << \" NUM_FRAGS_D=\" << NUM_FRAGS_D << \" NUM_FRAGS_KV=\" << NUM_FRAGS_KV\n << \" NUM_WARPS_Q=\" << NUM_WARPS_Q << \" NUM_WARPS_KV=\" << NUM_WARPS_KV\n << \" please create an issue (https://github.com/flashinfer-ai/flashinfer/issues)\"\n \" and report the issue to the developers.\";\n throw std::invalid_argument(err_msg.str());\n } else {\n // TODO(Zihao): fix the following computation\n uint32_t smem_size = (NUM_FRAGS_Q * NUM_WARPS_Q * sizeof(DTypeQ) +\n NUM_FRAGS_KV * NUM_WARPS_KV * 2 * sizeof(DTypeQ)) *\n 16 * HEAD_DIM;\n auto kernel =\n BatchPrefillWithPagedKVCacheKernel<MASK_MODE, POS_ENCODING_MODE, NUM_FRAGS_Q, NUM_FRAGS_D,\n NUM_FRAGS_KV, NUM_WARPS_Q, NUM_WARPS_KV, DTypeQKAccum,\n AttentionVariant>;\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n if (tmp_v == nullptr) {\n // do not partition kv\n params.partition_kv = false;\n void* args[] = {(void*)&group_size_fastdiv, (void*)¶ms};\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n } else {\n params.partition_kv = true;\n auto o = params.o;\n auto lse = params.lse;\n params.o = tmp_v;\n params.lse = tmp_s;\n void* args[] = {(void*)&group_size_fastdiv, (void*)¶ms};\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n if constexpr (AttentionVariant::use_softmax) {\n FLASHINFER_CUDA_CALL(VariableLengthMergeStates(tmp_v, tmp_s, params.merge_indptr, o, lse,\n total_num_rows, num_qo_heads, HEAD_DIM,\n stream));\n } else {\n FLASHINFER_CUDA_CALL(VariableLengthAttentionSum(\n tmp_v, params.merge_indptr, o, total_num_rows, num_qo_heads, HEAD_DIM, stream));\n }\n }\n }\n });\n return cudaSuccess;\n}\n\n} // namespace flashinfer\n\n#endif // FLASHINFER_PREFILL_CUH_\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"The prefill attention kernel performance has degraded significantly in recent releases (since v0.1.2), especially on A100 when `causal=True`, this is mainly because we add new attention variants (which increases register usage thus incurs register spilling) and move some parameters from compile-time to runtime.\n\nThis PR alleviates the issue by caching some of the variables regarding GQA group size.\nIn the next PR, we will support another mode `kv_head_major` in addition to `qo_head_major`, to further accelerate GQA prefill with query size >= 64.\n\ncc @AKKamath\n"},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1293,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"2043ca2181d1e9119a1fb8b86a739c245be5b536"},"date":{"kind":"string","value":"2024-11-09T10:32:14+08:00"},"pr_number":{"kind":"number","value":592,"string":"592"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/592"},"title":{"kind":"string","value":"perf: reduce the read and write of shared memory in the FusedAddRMSNormKernel (#592)"},"message":{"kind":"string","value":"perf: reduce the read and write of shared memory in the FusedAddRMSNormKernel (#592)\n\nUse `vec_t<float, VEC_SIZE> x_vec` to reduce the number of read and\r\nwrite operations to shared memory."},"path":{"kind":"string","value":"include/flashinfer/norm.cuh"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * Copyright (c) 2024 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_NORM_CUH_\n#define FLASHINFER_NORM_CUH_\n\n#include <numeric>\n\n#include \"flashinfer/utils.cuh\"\n#include \"math.cuh\"\n#include \"utils.cuh\"\n#include \"vec_dtypes.cuh\"\n\nnamespace flashinfer {\n\nnamespace norm {\n\ntemplate <uint32_t VEC_SIZE, typename T>\n__global__ void RMSNormKernel(T* __restrict__ input, T* __restrict__ weight, T* __restrict__ output,\n const uint32_t d, float eps) {\n const uint32_t bx = blockIdx.x;\n const uint32_t tx = threadIdx.x, ty = threadIdx.y;\n constexpr uint32_t warp_size = 32;\n const uint32_t num_warps = blockDim.y;\n // NOTE(Zihao): it's guaranteed that num_warps should be smaller than 32\n const uint32_t thread_id = tx + ty * warp_size;\n const uint32_t num_threads = num_warps * warp_size;\n const uint32_t rounds = ceil_div(d, VEC_SIZE * num_threads);\n extern __shared__ float smem[];\n\n float sum_sq = 0.f;\n\n for (uint32_t i = 0; i < rounds; i++) {\n vec_t<T, VEC_SIZE> input_vec;\n input_vec.fill(0.f);\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n input_vec.load(input + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; j++) {\n sum_sq += float(input_vec[j]) * float(input_vec[j]);\n }\n }\n\n // first, warp reduce sum\n#pragma unroll\n for (uint32_t offset = warp_size / 2; offset > 0; offset /= 2) {\n sum_sq += math::shfl_xor_sync(sum_sq, offset);\n }\n\n smem[ty] = sum_sq;\n __syncthreads();\n // then, cross warp reduce sum using only the first warp\n if (ty == 0) {\n sum_sq = (tx < num_warps) ? smem[tx] : 0.f;\n#pragma unroll\n for (uint32_t offset = warp_size / 2; offset > 0; offset /= 2) {\n sum_sq += math::shfl_xor_sync(sum_sq, offset);\n }\n smem[0] = sum_sq;\n }\n __syncthreads();\n\n float rms_rcp = math::rsqrt(smem[0] / float(d) + eps);\n\n for (uint32_t i = 0; i < rounds; i++) {\n vec_t<T, VEC_SIZE> input_vec;\n vec_t<T, VEC_SIZE> weight_vec;\n vec_t<T, VEC_SIZE> output_vec;\n input_vec.fill(0.f);\n weight_vec.fill(0.f);\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n input_vec.load(input + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n weight_vec.load(weight + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; j++) {\n output_vec[j] = float(input_vec[j]) * rms_rcp * float(weight_vec[j]);\n }\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n output_vec.store(output + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n }\n}\n\ntemplate <typename T>\ncudaError_t RMSNorm(T* input, T* weight, T* output, uint32_t batch_size, uint32_t d,\n float eps = 1e-5, cudaStream_t stream = 0) {\n const uint32_t vec_size = std::gcd(16 / sizeof(T), d);\n\n const uint32_t block_size = std::min<uint32_t>(1024, d / vec_size);\n const uint32_t num_warps = ceil_div(block_size, 32);\n dim3 nblks(batch_size);\n dim3 nthrs(32, num_warps);\n const uint32_t smem_size = num_warps * sizeof(float);\n void* args[] = {&input, &weight, &output, &d, &eps};\n\n DISPATCH_ALIGNED_VEC_SIZE(vec_size, VEC_SIZE, {\n auto kernel = RMSNormKernel<VEC_SIZE, T>;\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n });\n return cudaSuccess;\n}\n\ntemplate <uint32_t VEC_SIZE, typename T>\n__global__ void FusedAddRMSNormKernel(T* __restrict__ input, T* __restrict__ residual,\n T* __restrict__ weight, const uint32_t d, float eps) {\n const uint32_t bx = blockIdx.x;\n const uint32_t tx = threadIdx.x, ty = threadIdx.y;\n constexpr uint32_t warp_size = 32;\n const uint32_t num_warps = blockDim.y;\n const uint32_t thread_id = tx + ty * warp_size;\n const uint32_t num_threads = num_warps * warp_size;\n const uint32_t rounds = ceil_div(d, VEC_SIZE * num_threads);\n extern __shared__ float smem[];\n\n float sum_sq = 0.f;\n\n for (uint32_t i = 0; i < rounds; i++) {\n vec_t<T, VEC_SIZE> input_vec;\n input_vec.fill(0.f);\n vec_t<T, VEC_SIZE> residual_vec;\n residual_vec.fill(0.f);\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n input_vec.load(input + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n residual_vec.load(residual + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; j++) {\n float x = float(input_vec[j]);\n x += float(residual_vec[j]);\n sum_sq += x * x;\n residual_vec[j] = (T)x;\n smem[num_warps + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE + j] = x;\n }\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n residual_vec.store(residual + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n }\n\n // first, warp reduce sum\n#pragma unroll\n for (uint32_t offset = warp_size / 2; offset > 0; offset /= 2) {\n sum_sq += math::shfl_xor_sync(sum_sq, offset);\n }\n\n smem[ty] = sum_sq;\n __syncthreads();\n // then, cross warp reduce sum using only the first warp\n if (ty == 0) {\n sum_sq = (tx < num_warps) ? smem[tx] : 0.f;\n#pragma unroll\n for (uint32_t offset = warp_size / 2; offset > 0; offset /= 2) {\n sum_sq += math::shfl_xor_sync(sum_sq, offset);\n }\n smem[0] = sum_sq;\n }\n __syncthreads();\n\n float rms_rcp = math::rsqrt(smem[0] / float(d) + eps);\n\n for (uint32_t i = 0; i < rounds; i++) {\n vec_t<T, VEC_SIZE> input_vec;\n vec_t<T, VEC_SIZE> weight_vec;\n input_vec.fill(0.f);\n weight_vec.fill(0.f);\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n weight_vec.load(weight + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; j++) {\n float x = smem[num_warps + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE + j];\n input_vec[j] = x * rms_rcp * float(weight_vec[j]);\n }\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n input_vec.store(input + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n }\n}\n\ntemplate <typename T>\ncudaError_t FusedAddRMSNorm(T* input, T* residual, T* weight, uint32_t batch_size, uint32_t d,\n float eps = 1e-5, cudaStream_t stream = 0) {\n const uint32_t vec_size = std::gcd(16 / sizeof(T), d);\n\n const uint32_t block_size = std::min<uint32_t>(1024, d / vec_size);\n const uint32_t num_warps = ceil_div(block_size, 32);\n dim3 nblks(batch_size);\n dim3 nthrs(32, num_warps);\n const uint32_t smem_size = (num_warps + d) * sizeof(float);\n void* args[] = {&input, &residual, &weight, &d, &eps};\n\n DISPATCH_ALIGNED_VEC_SIZE(vec_size, VEC_SIZE, {\n auto kernel = FusedAddRMSNormKernel<VEC_SIZE, T>;\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n });\n\n return cudaSuccess;\n}\n\ntemplate <uint32_t VEC_SIZE, typename T>\n__global__ void GemmaRMSNormKernel(T* __restrict__ input, T* __restrict__ weight,\n T* __restrict__ output, const uint32_t d, float eps) {\n const uint32_t bx = blockIdx.x;\n const uint32_t tx = threadIdx.x, ty = threadIdx.y;\n constexpr uint32_t warp_size = 32;\n const uint32_t num_warps = blockDim.y;\n const uint32_t thread_id = tx + ty * warp_size;\n const uint32_t num_threads = num_warps * warp_size;\n const uint32_t rounds = ceil_div(d, VEC_SIZE * num_threads);\n extern __shared__ float smem[];\n\n float sum_sq = 0.f;\n\n for (uint32_t i = 0; i < rounds; i++) {\n vec_t<T, VEC_SIZE> input_vec;\n input_vec.fill(0.f);\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n input_vec.load(input + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; j++) {\n sum_sq += float(input_vec[j]) * float(input_vec[j]);\n }\n }\n\n // first, warp reduce sum\n#pragma unroll\n for (uint32_t offset = warp_size / 2; offset > 0; offset /= 2) {\n sum_sq += math::shfl_xor_sync(sum_sq, offset);\n }\n\n smem[ty] = sum_sq;\n __syncthreads();\n // then, cross warp reduce sum using only the first warp\n if (ty == 0) {\n sum_sq = (tx < num_warps) ? smem[tx] : 0.f;\n#pragma unroll\n for (uint32_t offset = warp_size / 2; offset > 0; offset /= 2) {\n sum_sq += math::shfl_xor_sync(sum_sq, offset);\n }\n smem[0] = sum_sq;\n }\n __syncthreads();\n\n float rms_rcp = math::rsqrt(smem[0] / (float(d) + eps));\n\n for (uint32_t i = 0; i < rounds; i++) {\n vec_t<T, VEC_SIZE> input_vec;\n vec_t<T, VEC_SIZE> weight_vec;\n vec_t<T, VEC_SIZE> output_vec;\n input_vec.fill(0.f);\n weight_vec.fill(0.f);\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n input_vec.load(input + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n weight_vec.load(weight + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; j++) {\n output_vec[j] = float(input_vec[j]) * rms_rcp * (1.0f + float(weight_vec[j]));\n }\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n output_vec.store(output + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n }\n}\n\ntemplate <typename T>\ncudaError_t GemmaRMSNorm(T* input, T* weight, T* output, uint32_t batch_size, uint32_t d,\n float eps = 1e-5, cudaStream_t stream = 0) {\n const uint32_t vec_size = std::gcd(16 / sizeof(T), d);\n\n const uint32_t block_size = std::min<uint32_t>(1024, d / vec_size);\n const uint32_t num_warps = ceil_div(block_size, 32);\n dim3 nblks(batch_size);\n dim3 nthrs(32, num_warps);\n const uint32_t smem_size = num_warps * sizeof(float);\n void* args[] = {&input, &weight, &output, &d, &eps};\n\n DISPATCH_ALIGNED_VEC_SIZE(vec_size, VEC_SIZE, {\n auto kernel = GemmaRMSNormKernel<VEC_SIZE, T>;\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n });\n return cudaSuccess;\n}\n\ntemplate <uint32_t VEC_SIZE, typename T>\n__global__ void GemmaFusedAddRMSNormKernel(T* __restrict__ input, T* __restrict__ residual,\n T* __restrict__ weight, const uint32_t d, float eps) {\n const uint32_t bx = blockIdx.x;\n const uint32_t tx = threadIdx.x, ty = threadIdx.y;\n constexpr uint32_t warp_size = 32;\n const uint32_t num_warps = blockDim.y;\n const uint32_t thread_id = tx + ty * warp_size;\n const uint32_t num_threads = num_warps * warp_size;\n const uint32_t rounds = ceil_div(d, VEC_SIZE * num_threads);\n extern __shared__ float smem[];\n\n float sum_sq = 0.f;\n\n for (uint32_t i = 0; i < rounds; i++) {\n vec_t<T, VEC_SIZE> input_vec;\n input_vec.fill(0.f);\n vec_t<T, VEC_SIZE> residual_vec;\n residual_vec.fill(0.f);\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n input_vec.load(input + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n residual_vec.load(residual + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; j++) {\n float x = float(input_vec[j]);\n x += float(residual_vec[j]);\n sum_sq += x * x;\n residual_vec[j] = (T)x;\n }\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n residual_vec.store(residual + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n }\n\n // first, warp reduce sum\n#pragma unroll\n for (uint32_t offset = warp_size / 2; offset > 0; offset /= 2) {\n sum_sq += math::shfl_xor_sync(sum_sq, offset);\n }\n\n smem[ty] = sum_sq;\n __syncthreads();\n // then, cross warp reduce sum using only the first warp\n if (ty == 0) {\n sum_sq = (tx < num_warps) ? smem[tx] : 0.f;\n#pragma unroll\n for (uint32_t offset = warp_size / 2; offset > 0; offset /= 2) {\n sum_sq += math::shfl_xor_sync(sum_sq, offset);\n }\n smem[0] = sum_sq;\n }\n __syncthreads();\n\n float rms_rcp = math::rsqrt(smem[0] / (float(d) + eps));\n\n for (uint32_t i = 0; i < rounds; i++) {\n vec_t<T, VEC_SIZE> input_vec;\n vec_t<T, VEC_SIZE> weight_vec;\n vec_t<T, VEC_SIZE> residual_vec;\n input_vec.fill(0.f);\n weight_vec.fill(0.f);\n residual_vec.fill(0.f);\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n weight_vec.load(weight + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n residual_vec.load(residual + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; j++) {\n input_vec[j] = float(residual_vec[j]) * rms_rcp * (1.0f + float(weight_vec[j]));\n }\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n input_vec.store(input + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n }\n}\n\ntemplate <typename T>\ncudaError_t GemmaFusedAddRMSNorm(T* input, T* residual, T* weight, uint32_t batch_size, uint32_t d,\n float eps = 1e-5, cudaStream_t stream = 0) {\n const uint32_t vec_size = std::gcd(16 / sizeof(T), d);\n\n const uint32_t block_size = std::min<uint32_t>(1024, d / vec_size);\n const uint32_t num_warps = ceil_div(block_size, 32);\n dim3 nblks(batch_size);\n dim3 nthrs(32, num_warps);\n const uint32_t smem_size = num_warps * sizeof(float);\n void* args[] = {&input, &residual, &weight, &d, &eps};\n\n DISPATCH_ALIGNED_VEC_SIZE(vec_size, VEC_SIZE, {\n auto kernel = GemmaFusedAddRMSNormKernel<VEC_SIZE, T>;\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n });\n\n return cudaSuccess;\n}\n\n} // namespace norm\n\n} // namespace flashinfer\n\n#endif // FLASHINFER_NORM_CUH_\n"},"after_code":{"kind":"string","value":"/*\n * Copyright (c) 2024 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_NORM_CUH_\n#define FLASHINFER_NORM_CUH_\n\n#include <numeric>\n\n#include \"flashinfer/utils.cuh\"\n#include \"math.cuh\"\n#include \"utils.cuh\"\n#include \"vec_dtypes.cuh\"\n\nnamespace flashinfer {\n\nnamespace norm {\n\ntemplate <uint32_t VEC_SIZE, typename T>\n__global__ void RMSNormKernel(T* __restrict__ input, T* __restrict__ weight, T* __restrict__ output,\n const uint32_t d, float eps) {\n const uint32_t bx = blockIdx.x;\n const uint32_t tx = threadIdx.x, ty = threadIdx.y;\n constexpr uint32_t warp_size = 32;\n const uint32_t num_warps = blockDim.y;\n // NOTE(Zihao): it's guaranteed that num_warps should be smaller than 32\n const uint32_t thread_id = tx + ty * warp_size;\n const uint32_t num_threads = num_warps * warp_size;\n const uint32_t rounds = ceil_div(d, VEC_SIZE * num_threads);\n extern __shared__ float smem[];\n\n float sum_sq = 0.f;\n\n for (uint32_t i = 0; i < rounds; i++) {\n vec_t<T, VEC_SIZE> input_vec;\n input_vec.fill(0.f);\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n input_vec.load(input + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; j++) {\n sum_sq += float(input_vec[j]) * float(input_vec[j]);\n }\n }\n\n // first, warp reduce sum\n#pragma unroll\n for (uint32_t offset = warp_size / 2; offset > 0; offset /= 2) {\n sum_sq += math::shfl_xor_sync(sum_sq, offset);\n }\n\n smem[ty] = sum_sq;\n __syncthreads();\n // then, cross warp reduce sum using only the first warp\n if (ty == 0) {\n sum_sq = (tx < num_warps) ? smem[tx] : 0.f;\n#pragma unroll\n for (uint32_t offset = warp_size / 2; offset > 0; offset /= 2) {\n sum_sq += math::shfl_xor_sync(sum_sq, offset);\n }\n smem[0] = sum_sq;\n }\n __syncthreads();\n\n float rms_rcp = math::rsqrt(smem[0] / float(d) + eps);\n\n for (uint32_t i = 0; i < rounds; i++) {\n vec_t<T, VEC_SIZE> input_vec;\n vec_t<T, VEC_SIZE> weight_vec;\n vec_t<T, VEC_SIZE> output_vec;\n input_vec.fill(0.f);\n weight_vec.fill(0.f);\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n input_vec.load(input + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n weight_vec.load(weight + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; j++) {\n output_vec[j] = float(input_vec[j]) * rms_rcp * float(weight_vec[j]);\n }\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n output_vec.store(output + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n }\n}\n\ntemplate <typename T>\ncudaError_t RMSNorm(T* input, T* weight, T* output, uint32_t batch_size, uint32_t d,\n float eps = 1e-5, cudaStream_t stream = 0) {\n const uint32_t vec_size = std::gcd(16 / sizeof(T), d);\n\n const uint32_t block_size = std::min<uint32_t>(1024, d / vec_size);\n const uint32_t num_warps = ceil_div(block_size, 32);\n dim3 nblks(batch_size);\n dim3 nthrs(32, num_warps);\n const uint32_t smem_size = num_warps * sizeof(float);\n void* args[] = {&input, &weight, &output, &d, &eps};\n\n DISPATCH_ALIGNED_VEC_SIZE(vec_size, VEC_SIZE, {\n auto kernel = RMSNormKernel<VEC_SIZE, T>;\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n });\n return cudaSuccess;\n}\n\ntemplate <uint32_t VEC_SIZE, typename T>\n__global__ void FusedAddRMSNormKernel(T* __restrict__ input, T* __restrict__ residual,\n T* __restrict__ weight, const uint32_t d, float eps) {\n const uint32_t bx = blockIdx.x;\n const uint32_t tx = threadIdx.x, ty = threadIdx.y;\n constexpr uint32_t warp_size = 32;\n const uint32_t num_warps = blockDim.y;\n const uint32_t thread_id = tx + ty * warp_size;\n const uint32_t num_threads = num_warps * warp_size;\n const uint32_t rounds = ceil_div(d, VEC_SIZE * num_threads);\n extern __shared__ float smem[];\n\n float sum_sq = 0.f;\n\n for (uint32_t i = 0; i < rounds; i++) {\n vec_t<T, VEC_SIZE> input_vec;\n input_vec.fill(0.f);\n vec_t<T, VEC_SIZE> residual_vec;\n residual_vec.fill(0.f);\n vec_t<float, VEC_SIZE> x_vec;\n x_vec.fill(0.f);\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n input_vec.load(input + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n residual_vec.load(residual + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; j++) {\n float x = float(input_vec[j]);\n x += float(residual_vec[j]);\n sum_sq += x * x;\n residual_vec[j] = (T)x;\n x_vec[j] = x;\n }\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n residual_vec.store(residual + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n x_vec.store(smem + num_warps + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n }\n\n // first, warp reduce sum\n#pragma unroll\n for (uint32_t offset = warp_size / 2; offset > 0; offset /= 2) {\n sum_sq += math::shfl_xor_sync(sum_sq, offset);\n }\n\n smem[ty] = sum_sq;\n __syncthreads();\n // then, cross warp reduce sum using only the first warp\n if (ty == 0) {\n sum_sq = (tx < num_warps) ? smem[tx] : 0.f;\n#pragma unroll\n for (uint32_t offset = warp_size / 2; offset > 0; offset /= 2) {\n sum_sq += math::shfl_xor_sync(sum_sq, offset);\n }\n smem[0] = sum_sq;\n }\n __syncthreads();\n\n float rms_rcp = math::rsqrt(smem[0] / float(d) + eps);\n\n for (uint32_t i = 0; i < rounds; i++) {\n vec_t<T, VEC_SIZE> input_vec;\n vec_t<T, VEC_SIZE> weight_vec;\n vec_t<float, VEC_SIZE> x_vec;\n input_vec.fill(0.f);\n weight_vec.fill(0.f);\n x_vec.fill(0.f);\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n weight_vec.load(weight + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n x_vec.load(smem + num_warps + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; j++) {\n input_vec[j] = x_vec[j] * rms_rcp * float(weight_vec[j]);\n }\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n input_vec.store(input + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n }\n}\n\ntemplate <typename T>\ncudaError_t FusedAddRMSNorm(T* input, T* residual, T* weight, uint32_t batch_size, uint32_t d,\n float eps = 1e-5, cudaStream_t stream = 0) {\n const uint32_t vec_size = std::gcd(16 / sizeof(T), d);\n\n const uint32_t block_size = std::min<uint32_t>(1024, d / vec_size);\n const uint32_t num_warps = ceil_div(block_size, 32);\n dim3 nblks(batch_size);\n dim3 nthrs(32, num_warps);\n const uint32_t smem_size = (num_warps + d) * sizeof(float);\n void* args[] = {&input, &residual, &weight, &d, &eps};\n\n DISPATCH_ALIGNED_VEC_SIZE(vec_size, VEC_SIZE, {\n auto kernel = FusedAddRMSNormKernel<VEC_SIZE, T>;\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n });\n\n return cudaSuccess;\n}\n\ntemplate <uint32_t VEC_SIZE, typename T>\n__global__ void GemmaRMSNormKernel(T* __restrict__ input, T* __restrict__ weight,\n T* __restrict__ output, const uint32_t d, float eps) {\n const uint32_t bx = blockIdx.x;\n const uint32_t tx = threadIdx.x, ty = threadIdx.y;\n constexpr uint32_t warp_size = 32;\n const uint32_t num_warps = blockDim.y;\n const uint32_t thread_id = tx + ty * warp_size;\n const uint32_t num_threads = num_warps * warp_size;\n const uint32_t rounds = ceil_div(d, VEC_SIZE * num_threads);\n extern __shared__ float smem[];\n\n float sum_sq = 0.f;\n\n for (uint32_t i = 0; i < rounds; i++) {\n vec_t<T, VEC_SIZE> input_vec;\n input_vec.fill(0.f);\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n input_vec.load(input + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; j++) {\n sum_sq += float(input_vec[j]) * float(input_vec[j]);\n }\n }\n\n // first, warp reduce sum\n#pragma unroll\n for (uint32_t offset = warp_size / 2; offset > 0; offset /= 2) {\n sum_sq += math::shfl_xor_sync(sum_sq, offset);\n }\n\n smem[ty] = sum_sq;\n __syncthreads();\n // then, cross warp reduce sum using only the first warp\n if (ty == 0) {\n sum_sq = (tx < num_warps) ? smem[tx] : 0.f;\n#pragma unroll\n for (uint32_t offset = warp_size / 2; offset > 0; offset /= 2) {\n sum_sq += math::shfl_xor_sync(sum_sq, offset);\n }\n smem[0] = sum_sq;\n }\n __syncthreads();\n\n float rms_rcp = math::rsqrt(smem[0] / (float(d) + eps));\n\n for (uint32_t i = 0; i < rounds; i++) {\n vec_t<T, VEC_SIZE> input_vec;\n vec_t<T, VEC_SIZE> weight_vec;\n vec_t<T, VEC_SIZE> output_vec;\n input_vec.fill(0.f);\n weight_vec.fill(0.f);\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n input_vec.load(input + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n weight_vec.load(weight + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; j++) {\n output_vec[j] = float(input_vec[j]) * rms_rcp * (1.0f + float(weight_vec[j]));\n }\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n output_vec.store(output + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n }\n}\n\ntemplate <typename T>\ncudaError_t GemmaRMSNorm(T* input, T* weight, T* output, uint32_t batch_size, uint32_t d,\n float eps = 1e-5, cudaStream_t stream = 0) {\n const uint32_t vec_size = std::gcd(16 / sizeof(T), d);\n\n const uint32_t block_size = std::min<uint32_t>(1024, d / vec_size);\n const uint32_t num_warps = ceil_div(block_size, 32);\n dim3 nblks(batch_size);\n dim3 nthrs(32, num_warps);\n const uint32_t smem_size = num_warps * sizeof(float);\n void* args[] = {&input, &weight, &output, &d, &eps};\n\n DISPATCH_ALIGNED_VEC_SIZE(vec_size, VEC_SIZE, {\n auto kernel = GemmaRMSNormKernel<VEC_SIZE, T>;\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n });\n return cudaSuccess;\n}\n\ntemplate <uint32_t VEC_SIZE, typename T>\n__global__ void GemmaFusedAddRMSNormKernel(T* __restrict__ input, T* __restrict__ residual,\n T* __restrict__ weight, const uint32_t d, float eps) {\n const uint32_t bx = blockIdx.x;\n const uint32_t tx = threadIdx.x, ty = threadIdx.y;\n constexpr uint32_t warp_size = 32;\n const uint32_t num_warps = blockDim.y;\n const uint32_t thread_id = tx + ty * warp_size;\n const uint32_t num_threads = num_warps * warp_size;\n const uint32_t rounds = ceil_div(d, VEC_SIZE * num_threads);\n extern __shared__ float smem[];\n\n float sum_sq = 0.f;\n\n for (uint32_t i = 0; i < rounds; i++) {\n vec_t<T, VEC_SIZE> input_vec;\n input_vec.fill(0.f);\n vec_t<T, VEC_SIZE> residual_vec;\n residual_vec.fill(0.f);\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n input_vec.load(input + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n residual_vec.load(residual + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; j++) {\n float x = float(input_vec[j]);\n x += float(residual_vec[j]);\n sum_sq += x * x;\n residual_vec[j] = (T)x;\n }\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n residual_vec.store(residual + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n }\n\n // first, warp reduce sum\n#pragma unroll\n for (uint32_t offset = warp_size / 2; offset > 0; offset /= 2) {\n sum_sq += math::shfl_xor_sync(sum_sq, offset);\n }\n\n smem[ty] = sum_sq;\n __syncthreads();\n // then, cross warp reduce sum using only the first warp\n if (ty == 0) {\n sum_sq = (tx < num_warps) ? smem[tx] : 0.f;\n#pragma unroll\n for (uint32_t offset = warp_size / 2; offset > 0; offset /= 2) {\n sum_sq += math::shfl_xor_sync(sum_sq, offset);\n }\n smem[0] = sum_sq;\n }\n __syncthreads();\n\n float rms_rcp = math::rsqrt(smem[0] / (float(d) + eps));\n\n for (uint32_t i = 0; i < rounds; i++) {\n vec_t<T, VEC_SIZE> input_vec;\n vec_t<T, VEC_SIZE> weight_vec;\n vec_t<T, VEC_SIZE> residual_vec;\n input_vec.fill(0.f);\n weight_vec.fill(0.f);\n residual_vec.fill(0.f);\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n weight_vec.load(weight + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n residual_vec.load(residual + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; j++) {\n input_vec[j] = float(residual_vec[j]) * rms_rcp * (1.0f + float(weight_vec[j]));\n }\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n input_vec.store(input + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n }\n}\n\ntemplate <typename T>\ncudaError_t GemmaFusedAddRMSNorm(T* input, T* residual, T* weight, uint32_t batch_size, uint32_t d,\n float eps = 1e-5, cudaStream_t stream = 0) {\n const uint32_t vec_size = std::gcd(16 / sizeof(T), d);\n\n const uint32_t block_size = std::min<uint32_t>(1024, d / vec_size);\n const uint32_t num_warps = ceil_div(block_size, 32);\n dim3 nblks(batch_size);\n dim3 nthrs(32, num_warps);\n const uint32_t smem_size = num_warps * sizeof(float);\n void* args[] = {&input, &residual, &weight, &d, &eps};\n\n DISPATCH_ALIGNED_VEC_SIZE(vec_size, VEC_SIZE, {\n auto kernel = GemmaFusedAddRMSNormKernel<VEC_SIZE, T>;\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n });\n\n return cudaSuccess;\n}\n\n} // namespace norm\n\n} // namespace flashinfer\n\n#endif // FLASHINFER_NORM_CUH_\n"},"diff":{"kind":"string","value":"--- include/flashinfer/norm.cuh\n+++ include/flashinfer/norm.cuh\n@@ -133,6 +133,8 @@\n input_vec.fill(0.f);\n vec_t<T, VEC_SIZE> residual_vec;\n residual_vec.fill(0.f);\n+ vec_t<float, VEC_SIZE> x_vec;\n+ x_vec.fill(0.f);\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n input_vec.load(input + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n residual_vec.load(residual + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n@@ -143,10 +145,11 @@\n x += float(residual_vec[j]);\n sum_sq += x * x;\n residual_vec[j] = (T)x;\n- smem[num_warps + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE + j] = x;\n+ x_vec[j] = x;\n }\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n residual_vec.store(residual + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n+ x_vec.store(smem + num_warps + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n }\n \n@@ -174,15 +177,17 @@\n for (uint32_t i = 0; i < rounds; i++) {\n vec_t<T, VEC_SIZE> input_vec;\n vec_t<T, VEC_SIZE> weight_vec;\n+ vec_t<float, VEC_SIZE> x_vec;\n input_vec.fill(0.f);\n weight_vec.fill(0.f);\n+ x_vec.fill(0.f);\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n weight_vec.load(weight + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n- }\n-#pragma unroll\n- for (uint32_t j = 0; j < VEC_SIZE; j++) {\n- float x = smem[num_warps + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE + j];\n- input_vec[j] = x * rms_rcp * float(weight_vec[j]);\n+ x_vec.load(smem + num_warps + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n+ }\n+#pragma unroll\n+ for (uint32_t j = 0; j < VEC_SIZE; j++) {\n+ input_vec[j] = x_vec[j] * rms_rcp * float(weight_vec[j]);\n }\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n input_vec.store(input + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);"},"lines_added":{"kind":"number","value":11,"string":"11"},"lines_removed":{"kind":"number","value":6,"string":"6"},"files_in_commit":{"kind":"number","value":1,"string":"1"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (include/flashinfer/norm.cuh).\n\nGoal: perf: reduce the read and write of shared memory in the FusedAddRMSNormKernel\nTarget hardware: unspecified\nTarget models: unspecified\n\nCurrent file:\n```cuda\n/*\n * Copyright (c) 2024 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_NORM_CUH_\n#define FLASHINFER_NORM_CUH_\n\n#include <numeric>\n\n#include \"flashinfer/utils.cuh\"\n#include \"math.cuh\"\n#include \"utils.cuh\"\n#include \"vec_dtypes.cuh\"\n\nnamespace flashinfer {\n\nnamespace norm {\n\ntemplate <uint32_t VEC_SIZE, typename T>\n__global__ void RMSNormKernel(T* __restrict__ input, T* __restrict__ weight, T* __restrict__ output,\n const uint32_t d, float eps) {\n const uint32_t bx = blockIdx.x;\n const uint32_t tx = threadIdx.x, ty = threadIdx.y;\n constexpr uint32_t warp_size = 32;\n const uint32_t num_warps = blockDim.y;\n // NOTE(Zihao): it's guaranteed that num_warps should be smaller than 32\n const uint32_t thread_id = tx + ty * warp_size;\n const uint32_t num_threads = num_warps * warp_size;\n const uint32_t rounds = ceil_div(d, VEC_SIZE * num_threads);\n extern __shared__ float smem[];\n\n float sum_sq = 0.f;\n\n for (uint32_t i = 0; i < rounds; i++) {\n vec_t<T, VEC_SIZE> input_vec;\n input_vec.fill(0.f);\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n input_vec.load(input + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; j++) {\n sum_sq += float(input_vec[j]) * float(input_vec[j]);\n }\n }\n\n // first, warp reduce sum\n#pragma unroll\n for (uint32_t offset = warp_size / 2; offset > 0; offset /= 2) {\n sum_sq += math::shfl_xor_sync(sum_sq, offset);\n }\n\n smem[ty] = sum_sq;\n __syncthreads();\n // then, cross warp reduce sum using only the first warp\n if (ty == 0) {\n sum_sq = (tx < num_warps) ? smem[tx] : 0.f;\n#pragma unroll\n for (uint32_t offset = warp_size / 2; offset > 0; offset /= 2) {\n sum_sq += math::shfl_xor_sync(sum_sq, offset);\n }\n smem[0] = sum_sq;\n }\n __syncthreads();\n\n float rms_rcp = math::rsqrt(smem[0] / float(d) + eps);\n\n for (uint32_t i = 0; i < rounds; i++) {\n vec_t<T, VEC_SIZE> input_vec;\n vec_t<T, VEC_SIZE> weight_vec;\n vec_t<T, VEC_SIZE> output_vec;\n input_vec.fill(0.f);\n weight_vec.fill(0.f);\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n input_vec.load(input + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n weight_vec.load(weight + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; j++) {\n output_vec[j] = float(input_vec[j]) * rms_rcp * float(weight_vec[j]);\n }\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n output_vec.store(output + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n }\n}\n\ntemplate <typename T>\ncudaError_t RMSNorm(T* input, T* weight, T* output, uint32_t batch_size, uint32_t d,\n float eps = 1e-5, cudaStream_t stream = 0) {\n const uint32_t vec_size = std::gcd(16 / sizeof(T), d);\n\n const uint32_t block_size = std::min<uint32_t>(1024, d / vec_size);\n const uint32_t num_warps = ceil_div(block_size, 32);\n dim3 nblks(batch_size);\n dim3 nthrs(32, num_warps);\n const uint32_t smem_size = num_warps * sizeof(float);\n void* args[] = {&input, &weight, &output, &d, &eps};\n\n DISPATCH_ALIGNED_VEC_SIZE(vec_size, VEC_SIZE, {\n auto kernel = RMSNormKernel<VEC_SIZE, T>;\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n });\n return cudaSuccess;\n}\n\ntemplate <uint32_t VEC_SIZE, typename T>\n__global__ void FusedAddRMSNormKernel(T* __restrict__ input, T* __restrict__ residual,\n T* __restrict__ weight, const uint32_t d, float eps) {\n const uint32_t bx = blockIdx.x;\n const uint32_t tx = threadIdx.x, ty = threadIdx.y;\n constexpr uint32_t warp_size = 32;\n const uint32_t num_warps = blockDim.y;\n const uint32_t thread_id = tx + ty * warp_size;\n const uint32_t num_threads = num_warps * warp_size;\n const uint32_t rounds = ceil_div(d, VEC_SIZE * num_threads);\n extern __shared__ float smem[];\n\n float sum_sq = 0.f;\n\n for (uint32_t i = 0; i < rounds; i++) {\n vec_t<T, VEC_SIZE> input_vec;\n input_vec.fill(0.f);\n vec_t<T, VEC_SIZE> residual_vec;\n residual_vec.fill(0.f);\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n input_vec.load(input + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n residual_vec.load(residual + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; j++) {\n float x = float(input_vec[j]);\n x += float(residual_vec[j]);\n sum_sq += x * x;\n residual_vec[j] = (T)x;\n smem[num_warps + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE + j] = x;\n }\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n residual_vec.store(residual + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n }\n\n // first, warp reduce sum\n#pragma unroll\n for (uint32_t offset = warp_size / 2; offset > 0; offset /= 2) {\n sum_sq += math::shfl_xor_sync(sum_sq, offset);\n }\n\n smem[ty] = sum_sq;\n __syncthreads();\n // then, cross warp reduce sum using only the first warp\n if (ty == 0) {\n sum_sq = (tx < num_warps) ? smem[tx] : 0.f;\n#pragma unroll\n for (uint32_t offset = warp_size / 2; offset > 0; offset /= 2) {\n sum_sq += math::shfl_xor_sync(sum_sq, offset);\n }\n smem[0] = sum_sq;\n }\n __syncthreads();\n\n float rms_rcp = math::rsqrt(smem[0] / float(d) + eps);\n\n for (uint32_t i = 0; i < rounds; i++) {\n vec_t<T, VEC_SIZE> input_vec;\n vec_t<T, VEC_SIZE> weight_vec;\n input_vec.fill(0.f);\n weight_vec.fill(0.f);\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n weight_vec.load(weight + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; j++) {\n float x = smem[num_warps + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE + j];\n input_vec[j] = x * rms_rcp * float(weight_vec[j]);\n }\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n input_vec.store(input + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n }\n}\n\ntemplate <typename T>\ncudaError_t FusedAddRMSNorm(T* input, T* residual, T* weight, uint32_t batch_size, uint32_t d,\n float eps = 1e-5, cudaStream_t stream = 0) {\n const uint32_t vec_size = std::gcd(16 / sizeof(T), d);\n\n const uint32_t block_size = std::min<uint32_t>(1024, d / vec_size);\n const uint32_t num_warps = ceil_div(block_size, 32);\n dim3 nblks(batch_size);\n dim3 nthrs(32, num_warps);\n const uint32_t smem_size = (num_warps + d) * sizeof(float);\n void* args[] = {&input, &residual, &weight, &d, &eps};\n\n DISPATCH_ALIGNED_VEC_SIZE(vec_size, VEC_SIZE, {\n auto kernel = FusedAddRMSNormKernel<VEC_SIZE, T>;\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n });\n\n return cudaSuccess;\n}\n\ntemplate <uint32_t VEC_SIZE, typename T>\n__global__ void GemmaRMSNormKernel(T* __restrict__ input, T* __restrict__ weight,\n T* __restrict__ output, const uint32_t d, float eps) {\n const uint32_t bx = blockIdx.x;\n const uint32_t tx = threadIdx.x, ty = threadIdx.y;\n constexpr uint32_t warp_size = 32;\n const uint32_t num_warps = blockDim.y;\n const uint32_t thread_id = tx + ty * warp_size;\n const uint32_t num_threads = num_warps * warp_size;\n const uint32_t rounds = ceil_div(d, VEC_SIZE * num_threads);\n extern __shared__ float smem[];\n\n float sum_sq = 0.f;\n\n for (uint32_t i = 0; i < rounds; i++) {\n vec_t<T, VEC_SIZE> input_vec;\n input_vec.fill(0.f);\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n input_vec.load(input + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; j++) {\n sum_sq += float(input_vec[j]) * float(input_vec[j]);\n }\n }\n\n // first, warp reduce sum\n#pragma unroll\n for (uint32_t offset = warp_size / 2; offset > 0; offset /= 2) {\n sum_sq += math::shfl_xor_sync(sum_sq, offset);\n }\n\n smem[ty] = sum_sq;\n __syncthreads();\n // then, cross warp reduce sum using only the first warp\n if (ty == 0) {\n sum_sq = (tx < num_warps) ? smem[tx] : 0.f;\n#pragma unroll\n for (uint32_t offset = warp_size / 2; offset > 0; offset /= 2) {\n sum_sq += math::shfl_xor_sync(sum_sq, offset);\n }\n smem[0] = sum_sq;\n }\n __syncthreads();\n\n float rms_rcp = math::rsqrt(smem[0] / (float(d) + eps));\n\n for (uint32_t i = 0; i < rounds; i++) {\n vec_t<T, VEC_SIZE> input_vec;\n vec_t<T, VEC_SIZE> weight_vec;\n vec_t<T, VEC_SIZE> output_vec;\n input_vec.fill(0.f);\n weight_vec.fill(0.f);\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n input_vec.load(input + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n weight_vec.load(weight + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; j++) {\n output_vec[j] = float(input_vec[j]) * rms_rcp * (1.0f + float(weight_vec[j]));\n }\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n output_vec.store(output + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n }\n}\n\ntemplate <typename T>\ncudaError_t GemmaRMSNorm(T* input, T* weight, T* output, uint32_t batch_size, uint32_t d,\n float eps = 1e-5, cudaStream_t stream = 0) {\n const uint32_t vec_size = std::gcd(16 / sizeof(T), d);\n\n const uint32_t block_size = std::min<uint32_t>(1024, d / vec_size);\n const uint32_t num_warps = ceil_div(block_size, 32);\n dim3 nblks(batch_size);\n dim3 nthrs(32, num_warps);\n const uint32_t smem_size = num_warps * sizeof(float);\n void* args[] = {&input, &weight, &output, &d, &eps};\n\n DISPATCH_ALIGNED_VEC_SIZE(vec_size, VEC_SIZE, {\n auto kernel = GemmaRMSNormKernel<VEC_SIZE, T>;\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n });\n return cudaSuccess;\n}\n\ntemplate <uint32_t VEC_SIZE, typename T>\n__global__ void GemmaFusedAddRMSNormKernel(T* __restrict__ input, T* __restrict__ residual,\n T* __restrict__ weight, const uint32_t d, float eps) {\n const uint32_t bx = blockIdx.x;\n const uint32_t tx = threadIdx.x, ty = threadIdx.y;\n constexpr uint32_t warp_size = 32;\n const uint32_t num_warps = blockDim.y;\n const uint32_t thread_id = tx + ty * warp_size;\n const uint32_t num_threads = num_warps * warp_size;\n const uint32_t rounds = ceil_div(d, VEC_SIZE * num_threads);\n extern __shared__ float smem[];\n\n float sum_sq = 0.f;\n\n for (uint32_t i = 0; i < rounds; i++) {\n vec_t<T, VEC_SIZE> input_vec;\n input_vec.fill(0.f);\n vec_t<T, VEC_SIZE> residual_vec;\n residual_vec.fill(0.f);\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n input_vec.load(input + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n residual_vec.load(residual + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; j++) {\n float x = float(input_vec[j]);\n x += float(residual_vec[j]);\n sum_sq += x * x;\n residual_vec[j] = (T)x;\n }\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n residual_vec.store(residual + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n }\n\n // first, warp reduce sum\n#pragma unroll\n for (uint32_t offset = warp_size / 2; offset > 0; offset /= 2) {\n sum_sq += math::shfl_xor_sync(sum_sq, offset);\n }\n\n smem[ty] = sum_sq;\n __syncthreads();\n // then, cross warp reduce sum using only the first warp\n if (ty == 0) {\n sum_sq = (tx < num_warps) ? smem[tx] : 0.f;\n#pragma unroll\n for (uint32_t offset = warp_size / 2; offset > 0; offset /= 2) {\n sum_sq += math::shfl_xor_sync(sum_sq, offset);\n }\n smem[0] = sum_sq;\n }\n __syncthreads();\n\n float rms_rcp = math::rsqrt(smem[0] / (float(d) + eps));\n\n for (uint32_t i = 0; i < rounds; i++) {\n vec_t<T, VEC_SIZE> input_vec;\n vec_t<T, VEC_SIZE> weight_vec;\n vec_t<T, VEC_SIZE> residual_vec;\n input_vec.fill(0.f);\n weight_vec.fill(0.f);\n residual_vec.fill(0.f);\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n weight_vec.load(weight + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n residual_vec.load(residual + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; j++) {\n input_vec[j] = float(residual_vec[j]) * rms_rcp * (1.0f + float(weight_vec[j]));\n }\n if ((i * num_threads + thread_id) * VEC_SIZE < d) {\n input_vec.store(input + bx * d + i * num_threads * VEC_SIZE + thread_id * VEC_SIZE);\n }\n }\n}\n\ntemplate <typename T>\ncudaError_t GemmaFusedAddRMSNorm(T* input, T* residual, T* weight, uint32_t batch_size, uint32_t d,\n float eps = 1e-5, cudaStream_t stream = 0) {\n const uint32_t vec_size = std::gcd(16 / sizeof(T), d);\n\n const uint32_t block_size = std::min<uint32_t>(1024, d / vec_size);\n const uint32_t num_warps = ceil_div(block_size, 32);\n dim3 nblks(batch_size);\n dim3 nthrs(32, num_warps);\n const uint32_t smem_size = num_warps * sizeof(float);\n void* args[] = {&input, &residual, &weight, &d, &eps};\n\n DISPATCH_ALIGNED_VEC_SIZE(vec_size, VEC_SIZE, {\n auto kernel = GemmaFusedAddRMSNormKernel<VEC_SIZE, T>;\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n });\n\n return cudaSuccess;\n}\n\n} // namespace norm\n\n} // namespace flashinfer\n\n#endif // FLASHINFER_NORM_CUH_\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"Use `vec_t<float, VEC_SIZE> x_vec` to reduce the number of read and write operations to shared memory.\n"},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1294,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"e15f7c984bc4152c0b65cfec916ace37c98668cd"},"date":{"kind":"string","value":"2024-11-06T14:02:19-08:00"},"pr_number":{"kind":"number","value":588,"string":"588"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/588"},"title":{"kind":"string","value":"perf: fix the performance issue of `append_paged_kv_cache` (#588)"},"message":{"kind":"string","value":"perf: fix the performance issue of `append_paged_kv_cache` (#588)\n\nThe performance of `append_paged_kv_cache` is terrible for small batch\r\nsize, which is a known issue that we haven't fixed for a long time, this\r\nPR fixes it. This PR also adds support for non-contiguous append\r\nkeys/values (which could be sliced from fused qkv matrix).\r\n\r\nWe first call a triton kernel to convert `append_indptr` to\r\n`batch_indices` and `positions` (which is similar to [CSR2COO\r\nconversion](https://docs.nvidia.com/cuda/cusparse/#cusparse-t-csr2coo)\r\nin sparse matrix). After the conversion, we can use element parallelism\r\ninstead of batch parallelism.\r\n\r\nIt's also worth trying using triton for the second\r\n`AppendPagedKVCacheKernel` kernel, I think the performance should be\r\nfine. I'll leave it for future work.\r\n\r\nSome todo items:\r\n1. add torch.compile support.\r\n\r\nAfter this PR (reference number can be found at #583 ):\r\n```bash\r\nmodel: l1b seqlens: [1, 1, 1, 1, 1, 1, 1, 1] single_layer: 0.006ms all_layers: 0.094ms throughput: 5.563GB/s\r\nmodel: l1b seqlens: [4993, 1, 1, 1, 1, 1, 1, 1] single_layer: 0.014ms all_layers: 0.216ms throughput: 1514.280GB/s\r\nmodel: l1b seqlens: [5000] single_layer: 0.014ms all_layers: 0.216ms throughput: 1517.017GB/s\r\nmodel: l1b seqlens: [625, 625, 625, 625, 625, 625, 625, 625] single_layer: 0.014ms all_layers: 0.217ms throughput: 1510.863GB/s\r\n---\r\nmodel: l3b seqlens: [1, 1, 1, 1, 1, 1, 1, 1] single_layer: 0.006ms all_layers: 0.165ms throughput: 11.123GB/s\r\nmodel: l3b seqlens: [4993, 1, 1, 1, 1, 1, 1, 1] single_layer: 0.021ms all_layers: 0.580ms throughput: 1975.732GB/s\r\nmodel: l3b seqlens: [5000] single_layer: 0.021ms all_layers: 0.586ms throughput: 1958.078GB/s\r\nmodel: l3b seqlens: [625, 625, 625, 625, 625, 625, 625, 625] single_layer: 0.021ms all_layers: 0.581ms throughput: 1973.174GB/s\r\n---\r\nmodel: l8b seqlens: [1, 1, 1, 1, 1, 1, 1, 1] single_layer: 0.006ms all_layers: 0.185ms throughput: 11.321GB/s\r\nmodel: l8b seqlens: [4993, 1, 1, 1, 1, 1, 1, 1] single_layer: 0.021ms all_layers: 0.661ms throughput: 1982.815GB/s\r\nmodel: l8b seqlens: [5000] single_layer: 0.021ms all_layers: 0.662ms throughput: 1980.227GB/s\r\nmodel: l8b seqlens: [625, 625, 625, 625, 625, 625, 625, 625] single_layer: 0.021ms all_layers: 0.667ms throughput: 1964.861GB/s\r\n---\r\nmodel: l70b-tp8 seqlens: [1, 1, 1, 1, 1, 1, 1, 1] single_layer: 0.006ms all_layers: 0.457ms throughput: 1.434GB/s\r\nmodel: l70b-tp8 seqlens: [4993, 1, 1, 1, 1, 1, 1, 1] single_layer: 0.009ms all_layers: 0.710ms throughput: 576.866GB/s\r\nmodel: l70b-tp8 seqlens: [5000] single_layer: 0.009ms all_layers: 0.685ms throughput: 598.366GB/s\r\nmodel: l70b-tp8 seqlens: [625, 625, 625, 625, 625, 625, 625, 625] single_layer: 0.009ms all_layers: 0.690ms throughput: 593.453GB/s\r\n```\r\n\r\ncc @abcdabcd987"},"path":{"kind":"string","value":"include/flashinfer/page.cuh"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * Copyright (c) 2023 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_PAGE_CUH_\n#define FLASHINFER_PAGE_CUH_\n\n#include <vector>\n\n#include \"fastdiv.cuh\"\n#include \"layout.cuh\"\n#include \"utils.cuh\"\n#include \"vec_dtypes.cuh\"\n\nnamespace flashinfer {\n\n/*!\n * \\brief Paged key-value cache\n * \\tparam layout The layout of last 3 dimensions in KV-Cache.\n * \\tparam DType The data type of the key-value cache\n * \\tparam IdType The index data type of the kv-cache\n */\ntemplate <typename DType, typename IdType>\nstruct paged_kv_t {\n uint_fastdiv page_size;\n uint32_t num_heads;\n uint32_t head_dim;\n uint32_t batch_size;\n uint32_t stride_page;\n uint32_t stride_n;\n uint32_t stride_h;\n\n // Internal layout:\n // [max_num_pages, num_heads, page_size, head_dim] if layout == HND\n // [max_num_pages, page_size, num_heads, head_dim] if layout == NHD\n DType* k_data;\n DType* v_data;\n IdType* indices;\n\n // [batch_size + 1] The page indptr array, with the first element 0, the last element nnz_pages\n IdType* indptr;\n // [batch_size] The offset of the last page for each request in the batch\n IdType* last_page_len;\n // [batch_size] The start position of each request in the batch.\n IdType* rope_pos_offset;\n\n /*!\n * \\brief Construct an empty paged key-value cache\n */\n __host__ __device__ __forceinline__ paged_kv_t()\n : num_heads(0),\n page_size(0),\n head_dim(0),\n batch_size(0),\n stride_page(0),\n stride_n(0),\n stride_h(0),\n k_data(nullptr),\n v_data(nullptr),\n indices(nullptr),\n indptr(nullptr),\n last_page_len(nullptr),\n rope_pos_offset(nullptr) {}\n\n /*!\n * \\brief Construct a paged key-value cache\n * \\param num_heads The number of heads\n * \\param page_size The size of each page\n * \\param head_dim The dimension of each head\n * \\param batch_size The batch size\n * \\param layout The layout of last 3 dimensions in KV-Cache.\n * \\param k_data The start pointer of key cache, k_cache should be contiguous\n * \\param v_data The start pointer of value cache, v_cache should be contiguous\n * \\param indices The page indices array\n * \\param indptr The page indptr array\n * \\param last_page_len The offset of the last page for each request in the batch\n * \\param rope_pos_offset The start position of each request in the batch.\n */\n __host__ __forceinline__ paged_kv_t(uint32_t num_heads, uint32_t page_size, uint32_t head_dim,\n uint32_t batch_size, QKVLayout layout, DType* k_data,\n DType* v_data, IdType* indices, IdType* indptr,\n IdType* last_page_len, IdType* rope_pos_offset = nullptr)\n : num_heads(num_heads),\n page_size(page_size),\n head_dim(head_dim),\n batch_size(batch_size),\n indices(indices),\n indptr(indptr),\n last_page_len(last_page_len),\n rope_pos_offset(rope_pos_offset) {\n stride_page = num_heads * page_size * head_dim;\n this->k_data = k_data;\n this->v_data = v_data;\n stride_n = layout == QKVLayout::kHND ? head_dim : num_heads * head_dim;\n stride_h = layout == QKVLayout::kHND ? page_size * head_dim : head_dim;\n }\n\n /*!\n * \\brief Construct a paged key-value cache with custom kv-cache strides\n * \\param num_heads The number of heads\n * \\param page_size The size of each page\n * \\param head_dim The dimension of each head\n * \\param batch_size The batch size\n * \\param layout The layout of last 3 dimensions in KV-Cache.\n * \\param k_data The start pointer of key cache, k_cache doesn't have to be contiguous\n * \\param v_data The start pointer of value cache, v_cache doesn't have to be contiguous\n * \\param kv_strides custom strides of each dimensions of k_data and v_data\n * \\param indices The page indices array\n * \\param indptr The page indptr array\n * \\param last_page_len The offset of the last page for each request in the batch\n * \\param rope_pos_offset The start position of each request in the batch.\n */\n __host__ __forceinline__ paged_kv_t(uint32_t num_heads, uint32_t page_size, uint32_t head_dim,\n uint32_t batch_size, QKVLayout layout, DType* k_data,\n DType* v_data, const int64_t* kv_strides, IdType* indices,\n IdType* indptr, IdType* last_page_len,\n IdType* rope_pos_offset = nullptr)\n : num_heads(num_heads),\n page_size(page_size),\n head_dim(head_dim),\n batch_size(batch_size),\n indices(indices),\n indptr(indptr),\n last_page_len(last_page_len),\n rope_pos_offset(rope_pos_offset) {\n stride_page = kv_strides[0];\n this->k_data = k_data;\n this->v_data = v_data;\n stride_n = layout == QKVLayout::kHND ? kv_strides[2] : kv_strides[1];\n stride_h = layout == QKVLayout::kHND ? kv_strides[1] : kv_strides[2];\n }\n\n __host__ __device__ __forceinline__ uint32_t get_length(uint32_t batch_idx) const {\n if (indptr[batch_idx + 1] == indptr[batch_idx]) {\n return 0;\n }\n return (indptr[batch_idx + 1] - indptr[batch_idx] - 1) * page_size + last_page_len[batch_idx];\n }\n\n /*!\n * \\brief Compute the offset of element in the allocated buffer.\n * \\param page_idx The page index\n * \\param head_idx The head index\n * \\param entry_idx The page entry index\n * \\param feat_idx The feature index\n */\n __host__ __device__ __forceinline__ size_t get_elem_offset(size_t page_idx, size_t head_idx,\n size_t entry_idx,\n size_t feat_idx) const {\n return page_idx * stride_page + head_idx * stride_h + entry_idx * stride_n + feat_idx;\n }\n\n /*!\n * \\brief Compute the offset of element inside the page.\n * \\param head_idx The head index\n * \\param entry_idx The page entry index\n * \\param feat_idx The feature index\n */\n __host__ __device__ __forceinline__ size_t get_elem_offset_in_page(size_t head_idx,\n size_t entry_idx,\n size_t feat_idx) const {\n return head_idx * stride_h + entry_idx * stride_n + feat_idx;\n }\n\n __device__ __forceinline__ DType* get_k_ptr(IdType page_iter, uint32_t head_idx,\n uint32_t entry_idx, uint32_t feat_idx) const {\n return k_data + get_elem_offset(__ldg(indices + page_iter), head_idx, entry_idx, feat_idx);\n }\n\n __device__ __forceinline__ size_t protective_get_kv_offset(IdType page_iter, uint32_t head_idx,\n uint32_t entry_idx, uint32_t feat_idx,\n IdType last_indptr) const {\n if (page_iter < last_indptr) {\n return get_elem_offset(__ldg(indices + page_iter), head_idx, entry_idx, feat_idx);\n } else {\n return 0;\n }\n }\n\n __device__ __forceinline__ DType* protective_get_k_ptr(IdType page_iter, uint32_t head_idx,\n uint32_t entry_idx, uint32_t feat_idx,\n IdType last_indptr) const {\n return k_data + protective_get_kv_offset(page_iter, head_idx, entry_idx, feat_idx, last_indptr);\n }\n\n __device__ __forceinline__ DType* get_v_ptr(IdType page_iter, uint32_t head_idx,\n uint32_t entry_idx, uint32_t feat_idx) const {\n return v_data + get_elem_offset(__ldg(indices + page_iter), head_idx, entry_idx, feat_idx);\n }\n\n __device__ __forceinline__ DType* protective_get_v_ptr(IdType page_iter, uint32_t head_idx,\n uint32_t entry_idx, uint32_t feat_idx,\n IdType last_indptr) const {\n return v_data + protective_get_kv_offset(page_iter, head_idx, entry_idx, feat_idx, last_indptr);\n }\n};\n\n/*!\n * \\brief CUDA kernel to append new keys/values to the paged key-value cache in the decode phase\n * \\tparam head_dim The dimension of each head\n * \\tparam vec_size The vector size used in the kernel\n * \\tparam DType The data type of the key-value cache\n * \\tparam IdType The index data type of the kv-cache\n * \\param paged_kv The paged key-value cache\n * \\param key The key to be appended\n * \\param value The value to be appended\n */\ntemplate <uint32_t head_dim, uint32_t vec_size, typename DType, typename IdType>\n__global__ void AppendPagedKVCacheDecodeKernel(paged_kv_t<DType, IdType> paged_kv,\n DType* __restrict__ key, DType* __restrict__ value) {\n uint32_t tx = threadIdx.x, ty = threadIdx.y;\n uint32_t num_heads = paged_kv.num_heads;\n uint32_t batch_idx = blockIdx.x;\n uint32_t head_idx = ty;\n\n uint32_t seq_len =\n (paged_kv.indptr[batch_idx + 1] - paged_kv.indptr[batch_idx] - 1) * paged_kv.page_size +\n paged_kv.last_page_len[batch_idx];\n\n uint32_t page_iter = paged_kv.indptr[batch_idx] + (seq_len - 1) / paged_kv.page_size;\n uint32_t entry_idx = (seq_len - 1) % paged_kv.page_size;\n\n DType* k_ptr = paged_kv.get_k_ptr(page_iter, head_idx, entry_idx, tx * vec_size);\n DType* v_ptr = paged_kv.get_v_ptr(page_iter, head_idx, entry_idx, tx * vec_size);\n vec_t<DType, vec_size>::memcpy(\n k_ptr, key + (batch_idx * num_heads + head_idx) * head_dim + tx * vec_size);\n\n vec_t<DType, vec_size>::memcpy(\n v_ptr, value + (batch_idx * num_heads + head_idx) * head_dim + tx * vec_size);\n}\n\n/*!\n * \\brief CUDA kernel to append new keys/values to the paged key-value cache in the prefill phase\n * \\tparam head_dim The dimension of each head\n * \\tparam vec_size The vector size used in the kernel\n * \\tparam DType The data type of the key-value cache\n * \\tparam IdType The index data type of the kv-cache\n * \\param paged_kv The paged key-value cache\n * \\param key The key to be appended\n * \\param value The value to be appended\n * \\param append_indptr The indptr array of the appended ragged tensor\n */\ntemplate <uint32_t head_dim, uint32_t vec_size, typename DType, typename IdType>\n__global__ void AppendPagedKVCachePrefillKernel(paged_kv_t<DType, IdType> paged_kv,\n DType* __restrict__ key, DType* __restrict__ value,\n IdType* __restrict__ append_indptr) {\n uint32_t tx = threadIdx.x, ty = threadIdx.y;\n uint32_t num_heads = paged_kv.num_heads;\n uint32_t batch_idx = blockIdx.x;\n uint32_t head_idx = ty;\n\n uint32_t seq_len =\n (paged_kv.indptr[batch_idx + 1] - paged_kv.indptr[batch_idx] - 1) * paged_kv.page_size +\n paged_kv.last_page_len[batch_idx];\n uint32_t append_seq_len = append_indptr[batch_idx + 1] - append_indptr[batch_idx];\n uint32_t append_start = seq_len - append_seq_len;\n\n#pragma unroll 2\n for (uint32_t j = 0; j < append_seq_len; ++j) {\n uint32_t page_seq_idx = j + append_start;\n uint32_t page_iter = paged_kv.indptr[batch_idx] + page_seq_idx / paged_kv.page_size;\n uint32_t entry_idx = page_seq_idx % paged_kv.page_size;\n\n DType* k_ptr = paged_kv.get_k_ptr(page_iter, head_idx, entry_idx, tx * vec_size);\n DType* v_ptr = paged_kv.get_v_ptr(page_iter, head_idx, entry_idx, tx * vec_size);\n vec_t<DType, vec_size>::memcpy(\n k_ptr,\n key + ((append_indptr[batch_idx] + j) * num_heads + head_idx) * head_dim + tx * vec_size);\n\n vec_t<DType, vec_size>::memcpy(\n v_ptr,\n value + ((append_indptr[batch_idx] + j) * num_heads + head_idx) * head_dim + tx * vec_size);\n }\n}\n\n/*!\n * \\brief Append new keys/values to the paged key-value cache in the decode phase\n * \\tparam DType The data type of the key-value cache\n * \\tparam IdType The index data type of the kv-cache\n * \\param paged_kv The paged key-value cache\n * \\param key The key to be appended\n * \\param value The value to be appended\n * \\param stream The CUDA stream to execute kernels.\n * \\return status Indicates whether CUDA calls are successful\n */\ntemplate <typename DType, typename IdType>\ncudaError_t AppendPagedKVCacheDecode(paged_kv_t<DType, IdType> paged_kv, DType* key, DType* value,\n cudaStream_t stream = nullptr) {\n uint32_t head_dim = paged_kv.head_dim;\n uint32_t batch_size = paged_kv.batch_size;\n uint32_t num_heads = paged_kv.num_heads;\n DISPATCH_HEAD_DIM(head_dim, HEAD_DIM, {\n constexpr uint32_t vec_size = std::max(16 / sizeof(DType), HEAD_DIM / 32);\n uint32_t bdx = HEAD_DIM / vec_size;\n uint32_t bdy = num_heads;\n // NOTE(Zihao): could be slow for small batch size, will optimize later\n dim3 nblks(batch_size);\n dim3 nthrs(bdx, bdy);\n auto kernel = AppendPagedKVCacheDecodeKernel<HEAD_DIM, vec_size, DType, IdType>;\n void* args[] = {(void*)&paged_kv, (void*)&key, (void*)&value};\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)kernel, nblks, nthrs, args, 0, stream));\n });\n return cudaSuccess;\n}\n\n/*!\n * \\brief Append new keys/values to the paged key-value cache\n * \\tparam layout The layout of last 3 dimension in KV-Cache\n * \\tparam DType The data type of the key-value cache\n * \\tparam IdType The index data type of the kv-cache\n * \\param paged_kv The paged key-value cache\n * \\param key The key to be appended\n * \\param value The value to be appended\n * \\param append_indptr The indptr array of the appended ragged tensor\n * \\param stream The CUDA stream to execute kernels.\n * \\return status Indicates whether CUDA calls are successful\n */\ntemplate <typename DType, typename IdType>\ncudaError_t AppendPagedKVCache(paged_kv_t<DType, IdType> paged_kv, DType* key, DType* value,\n IdType* append_indptr, cudaStream_t stream = nullptr) {\n uint32_t head_dim = paged_kv.head_dim;\n uint32_t batch_size = paged_kv.batch_size;\n uint32_t num_heads = paged_kv.num_heads;\n DISPATCH_HEAD_DIM(head_dim, HEAD_DIM, {\n constexpr uint32_t vec_size = std::max(16 / sizeof(DType), HEAD_DIM / 32);\n uint32_t bdx = HEAD_DIM / vec_size;\n uint32_t bdy = num_heads;\n // NOTE(Zihao): could be slow for small batch size, will optimize later\n dim3 nblks(batch_size);\n dim3 nthrs(bdx, bdy);\n auto kernel = AppendPagedKVCachePrefillKernel<HEAD_DIM, vec_size, DType, IdType>;\n void* args[] = {(void*)&paged_kv, (void*)&key, (void*)&value, (void*)&append_indptr};\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)kernel, nblks, nthrs, args, 0, stream));\n });\n return cudaSuccess;\n}\n\ntemplate <typename DType, typename IdType>\nstruct paged_kv_mla_t {\n uint_fastdiv page_size;\n uint32_t head_dim_ckv;\n uint32_t head_dim_kpe;\n uint32_t batch_size;\n uint32_t stride_page_ckv;\n uint32_t stride_page_kpe;\n uint32_t stride_n_ckv;\n uint32_t stride_n_kpe;\n\n // Internal layout:\n // [max_num_pages, page_size, head_dim]\n DType* ckv_data;\n DType* kpe_data;\n IdType* indices;\n\n // [batch_size + 1] The page indptr array, with the first element 0, the last element nnz_pages\n IdType* indptr;\n // [batch_size] The offset of the last page for each request in the batch\n IdType* last_page_len;\n // [batch_size] The start position of each request in the batch.\n IdType* rope_pos_offset;\n\n /*!\n * \\brief Construct an empty paged key-value cache\n */\n __host__ __device__ __forceinline__ paged_kv_mla_t()\n : head_dim_ckv(0),\n head_dim_kpe(0),\n batch_size(0),\n stride_page_ckv(0),\n stride_page_kpe(0),\n stride_n_ckv(0),\n stride_n_kpe(0),\n ckv_data(nullptr),\n kpe_data(nullptr),\n indices(nullptr),\n indptr(nullptr),\n last_page_len(nullptr),\n rope_pos_offset(nullptr) {}\n\n /*!\n * \\brief Construct a paged mla kv cache\n * \\param page_size The size of each page\n * \\param head_dim_compressed_kv The dimension of compressed-kv\n * \\param head_dim_kpe The dimension of k-pe\n * \\param batch_size The batch size\n * \\param compressed_kv_data The start pointer of compressed-kv cache, cache should be contiguous\n * \\param kpe_data The start pointer of k-pe cache, cache should be contiguous\n * \\param indices The page indices array\n * \\param indptr The page indptr array\n * \\param last_page_len The offset of the last page for each request in the batch\n * \\param rope_pos_offset The start position of each request in the batch.\n */\n __host__ __forceinline__ paged_kv_mla_t(uint32_t page_size, uint32_t head_dim_compressed_kv,\n uint32_t head_dim_kpe, uint32_t batch_size,\n DType* compressed_kv_data, DType* kpe_data,\n IdType* indices, IdType* indptr, IdType* last_page_len,\n IdType* rope_pos_offset = nullptr)\n : page_size(page_size),\n head_dim_ckv(head_dim_compressed_kv),\n head_dim_kpe(head_dim_kpe),\n batch_size(batch_size),\n ckv_data(compressed_kv_data),\n kpe_data(kpe_data),\n indices(indices),\n indptr(indptr),\n last_page_len(last_page_len),\n rope_pos_offset(rope_pos_offset) {\n stride_page_ckv = page_size * head_dim_ckv;\n stride_n_ckv = head_dim_ckv;\n stride_page_kpe = page_size * head_dim_kpe;\n stride_n_kpe = head_dim_kpe;\n }\n\n /*!\n * \\brief Construct a paged key-value cache with custom kv-cache strides\n * \\param page_size The size of each page\n * \\param head_dim_compressed_kv The dimension of compressed-kv\n * \\param head_dim_kpe The dimension of k-pe\n * \\param batch_size The batch size\n * \\param compressed_kv_data The start pointer of compressed-kv cache, cache should be contiguous\n * \\param compressed_kv_strides custom strides of each dimensions of compressed-kv cache\n * \\param kpe_data The start pointer of k-pe cache, cache should be contiguous\n * \\param kpe_strides custom strides of each dimensions of k-pe cache\n * \\param indices The page indices array\n * \\param indptr The page indptr array\n * \\param last_page_len The offset of the last page for each request in the batch\n * \\param rope_pos_offset The start position of each request in the batch.\n */\n __host__ __forceinline__ paged_kv_mla_t(uint32_t page_size, uint32_t head_dim_compressed_kv,\n uint32_t head_dim_kpe, uint32_t batch_size,\n DType* compressed_kv_data,\n const int64_t* compressed_kv_strides, DType* kpe_data,\n const int64_t* kpe_strides, IdType* indices,\n IdType* indptr, IdType* last_page_len,\n IdType* rope_pos_offset = nullptr)\n : page_size(page_size),\n head_dim_ckv(head_dim_compressed_kv),\n head_dim_kpe(head_dim_kpe),\n batch_size(batch_size),\n ckv_data(compressed_kv_data),\n kpe_data(kpe_data),\n indices(indices),\n indptr(indptr),\n last_page_len(last_page_len),\n rope_pos_offset(rope_pos_offset) {\n stride_page_ckv = compressed_kv_strides[0];\n stride_n_ckv = compressed_kv_strides[1];\n stride_page_kpe = kpe_strides[0];\n stride_n_kpe = kpe_strides[1];\n }\n\n __host__ __device__ __forceinline__ uint32_t get_length(uint32_t batch_idx) const {\n if (indptr[batch_idx + 1] == indptr[batch_idx]) {\n return 0;\n }\n return (indptr[batch_idx + 1] - indptr[batch_idx] - 1) * page_size + last_page_len[batch_idx];\n }\n\n __host__ __device__ __forceinline__ size_t get_elem_offset_ckv(size_t page_idx, size_t entry_idx,\n size_t feat_idx) const {\n return page_idx * stride_page_ckv + entry_idx * stride_n_ckv + feat_idx;\n }\n\n __device__ __forceinline__ size_t protective_get_offset_ckv(IdType page_iter, uint32_t entry_idx,\n uint32_t feat_idx,\n IdType last_indptr) const {\n if (page_iter < last_indptr) {\n return get_elem_offset_ckv(__ldg(indices + page_iter), entry_idx, feat_idx);\n } else {\n return 0;\n }\n }\n\n __host__ __device__ __forceinline__ size_t get_elem_offset_kpe(size_t page_idx, size_t entry_idx,\n size_t feat_idx) const {\n return page_idx * stride_page_kpe + entry_idx * stride_n_kpe + feat_idx;\n }\n\n __device__ __forceinline__ size_t protective_get_offset_kpe(IdType page_iter, uint32_t entry_idx,\n uint32_t feat_idx,\n IdType last_indptr) const {\n if (page_iter < last_indptr) {\n return get_elem_offset_kpe(__ldg(indices + page_iter), entry_idx, feat_idx);\n } else {\n return 0;\n }\n }\n};\n\n} // namespace flashinfer\n\n#endif // FLAHSINFER_PAGE_CUH_\n"},"after_code":{"kind":"string","value":"/*\n * Copyright (c) 2023 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_PAGE_CUH_\n#define FLASHINFER_PAGE_CUH_\n\n#include <vector>\n\n#include \"fastdiv.cuh\"\n#include \"layout.cuh\"\n#include \"utils.cuh\"\n#include \"vec_dtypes.cuh\"\n\nnamespace flashinfer {\n\n/*!\n * \\brief Paged key-value cache\n * \\tparam layout The layout of last 3 dimensions in KV-Cache.\n * \\tparam DType The data type of the key-value cache\n * \\tparam IdType The index data type of the kv-cache\n */\ntemplate <typename DType, typename IdType>\nstruct paged_kv_t {\n uint_fastdiv page_size;\n uint32_t num_heads;\n uint32_t head_dim;\n uint32_t batch_size;\n uint32_t stride_page;\n uint32_t stride_n;\n uint32_t stride_h;\n\n // Internal layout:\n // [max_num_pages, num_heads, page_size, head_dim] if layout == HND\n // [max_num_pages, page_size, num_heads, head_dim] if layout == NHD\n DType* k_data;\n DType* v_data;\n IdType* indices;\n\n // [batch_size + 1] The page indptr array, with the first element 0, the last element nnz_pages\n IdType* indptr;\n // [batch_size] The offset of the last page for each request in the batch\n IdType* last_page_len;\n // [batch_size] The start position of each request in the batch.\n IdType* rope_pos_offset;\n\n /*!\n * \\brief Construct an empty paged key-value cache\n */\n __host__ __device__ __forceinline__ paged_kv_t()\n : num_heads(0),\n page_size(0),\n head_dim(0),\n batch_size(0),\n stride_page(0),\n stride_n(0),\n stride_h(0),\n k_data(nullptr),\n v_data(nullptr),\n indices(nullptr),\n indptr(nullptr),\n last_page_len(nullptr),\n rope_pos_offset(nullptr) {}\n\n /*!\n * \\brief Construct a paged key-value cache\n * \\param num_heads The number of heads\n * \\param page_size The size of each page\n * \\param head_dim The dimension of each head\n * \\param batch_size The batch size\n * \\param layout The layout of last 3 dimensions in KV-Cache.\n * \\param k_data The start pointer of key cache, k_cache should be contiguous\n * \\param v_data The start pointer of value cache, v_cache should be contiguous\n * \\param indices The page indices array\n * \\param indptr The page indptr array\n * \\param last_page_len The offset of the last page for each request in the batch\n * \\param rope_pos_offset The start position of each request in the batch.\n */\n __host__ __forceinline__ paged_kv_t(uint32_t num_heads, uint32_t page_size, uint32_t head_dim,\n uint32_t batch_size, QKVLayout layout, DType* k_data,\n DType* v_data, IdType* indices, IdType* indptr,\n IdType* last_page_len, IdType* rope_pos_offset = nullptr)\n : num_heads(num_heads),\n page_size(page_size),\n head_dim(head_dim),\n batch_size(batch_size),\n indices(indices),\n indptr(indptr),\n last_page_len(last_page_len),\n rope_pos_offset(rope_pos_offset) {\n stride_page = num_heads * page_size * head_dim;\n this->k_data = k_data;\n this->v_data = v_data;\n stride_n = layout == QKVLayout::kHND ? head_dim : num_heads * head_dim;\n stride_h = layout == QKVLayout::kHND ? page_size * head_dim : head_dim;\n }\n\n /*!\n * \\brief Construct a paged key-value cache with custom kv-cache strides\n * \\param num_heads The number of heads\n * \\param page_size The size of each page\n * \\param head_dim The dimension of each head\n * \\param batch_size The batch size\n * \\param layout The layout of last 3 dimensions in KV-Cache.\n * \\param k_data The start pointer of key cache, k_cache doesn't have to be contiguous\n * \\param v_data The start pointer of value cache, v_cache doesn't have to be contiguous\n * \\param kv_strides custom strides of each dimensions of k_data and v_data\n * \\param indices The page indices array\n * \\param indptr The page indptr array\n * \\param last_page_len The offset of the last page for each request in the batch\n * \\param rope_pos_offset The start position of each request in the batch.\n */\n __host__ __forceinline__ paged_kv_t(uint32_t num_heads, uint32_t page_size, uint32_t head_dim,\n uint32_t batch_size, QKVLayout layout, DType* k_data,\n DType* v_data, const int64_t* kv_strides, IdType* indices,\n IdType* indptr, IdType* last_page_len,\n IdType* rope_pos_offset = nullptr)\n : num_heads(num_heads),\n page_size(page_size),\n head_dim(head_dim),\n batch_size(batch_size),\n indices(indices),\n indptr(indptr),\n last_page_len(last_page_len),\n rope_pos_offset(rope_pos_offset) {\n stride_page = kv_strides[0];\n this->k_data = k_data;\n this->v_data = v_data;\n stride_n = layout == QKVLayout::kHND ? kv_strides[2] : kv_strides[1];\n stride_h = layout == QKVLayout::kHND ? kv_strides[1] : kv_strides[2];\n }\n\n __host__ __device__ __forceinline__ uint32_t get_length(uint32_t batch_idx) const {\n if (indptr[batch_idx + 1] == indptr[batch_idx]) {\n return 0;\n }\n return (indptr[batch_idx + 1] - indptr[batch_idx] - 1) * page_size + last_page_len[batch_idx];\n }\n\n /*!\n * \\brief Compute the offset of element in the allocated buffer.\n * \\param page_idx The page index\n * \\param head_idx The head index\n * \\param entry_idx The page entry index\n * \\param feat_idx The feature index\n */\n __host__ __device__ __forceinline__ size_t get_elem_offset(size_t page_idx, size_t head_idx,\n size_t entry_idx,\n size_t feat_idx) const {\n return page_idx * stride_page + head_idx * stride_h + entry_idx * stride_n + feat_idx;\n }\n\n /*!\n * \\brief Compute the offset of element inside the page.\n * \\param head_idx The head index\n * \\param entry_idx The page entry index\n * \\param feat_idx The feature index\n */\n __host__ __device__ __forceinline__ size_t get_elem_offset_in_page(size_t head_idx,\n size_t entry_idx,\n size_t feat_idx) const {\n return head_idx * stride_h + entry_idx * stride_n + feat_idx;\n }\n\n __device__ __forceinline__ DType* get_k_ptr(IdType page_iter, uint32_t head_idx,\n uint32_t entry_idx, uint32_t feat_idx) const {\n return k_data + get_elem_offset(__ldg(indices + page_iter), head_idx, entry_idx, feat_idx);\n }\n\n __device__ __forceinline__ size_t protective_get_kv_offset(IdType page_iter, uint32_t head_idx,\n uint32_t entry_idx, uint32_t feat_idx,\n IdType last_indptr) const {\n if (page_iter < last_indptr) {\n return get_elem_offset(__ldg(indices + page_iter), head_idx, entry_idx, feat_idx);\n } else {\n return 0;\n }\n }\n\n __device__ __forceinline__ DType* protective_get_k_ptr(IdType page_iter, uint32_t head_idx,\n uint32_t entry_idx, uint32_t feat_idx,\n IdType last_indptr) const {\n return k_data + protective_get_kv_offset(page_iter, head_idx, entry_idx, feat_idx, last_indptr);\n }\n\n __device__ __forceinline__ DType* get_v_ptr(IdType page_iter, uint32_t head_idx,\n uint32_t entry_idx, uint32_t feat_idx) const {\n return v_data + get_elem_offset(__ldg(indices + page_iter), head_idx, entry_idx, feat_idx);\n }\n\n __device__ __forceinline__ DType* protective_get_v_ptr(IdType page_iter, uint32_t head_idx,\n uint32_t entry_idx, uint32_t feat_idx,\n IdType last_indptr) const {\n return v_data + protective_get_kv_offset(page_iter, head_idx, entry_idx, feat_idx, last_indptr);\n }\n};\n\n/*!\n * \\brief CUDA kernel to append new keys/values to the paged key-value cache in the decode phase\n * \\tparam head_dim The dimension of each head\n * \\tparam vec_size The vector size used in the kernel\n * \\tparam DType The data type of the key-value cache\n * \\tparam IdType The index data type of the kv-cache\n * \\param paged_kv The paged key-value cache\n * \\param key The key to be appended\n * \\param value The value to be appended\n */\ntemplate <uint32_t head_dim, uint32_t vec_size, typename DType, typename IdType>\n__global__ void AppendPagedKVCacheDecodeKernel(paged_kv_t<DType, IdType> paged_kv,\n DType* __restrict__ key, DType* __restrict__ value) {\n uint32_t tx = threadIdx.x, ty = threadIdx.y;\n uint32_t num_heads = paged_kv.num_heads;\n uint32_t batch_idx = blockIdx.x;\n uint32_t head_idx = ty;\n\n uint32_t seq_len =\n (paged_kv.indptr[batch_idx + 1] - paged_kv.indptr[batch_idx] - 1) * paged_kv.page_size +\n paged_kv.last_page_len[batch_idx];\n\n uint32_t page_iter = paged_kv.indptr[batch_idx] + (seq_len - 1) / paged_kv.page_size;\n uint32_t entry_idx = (seq_len - 1) % paged_kv.page_size;\n\n DType* k_ptr = paged_kv.get_k_ptr(page_iter, head_idx, entry_idx, tx * vec_size);\n DType* v_ptr = paged_kv.get_v_ptr(page_iter, head_idx, entry_idx, tx * vec_size);\n vec_t<DType, vec_size>::memcpy(\n k_ptr, key + (batch_idx * num_heads + head_idx) * head_dim + tx * vec_size);\n\n vec_t<DType, vec_size>::memcpy(\n v_ptr, value + (batch_idx * num_heads + head_idx) * head_dim + tx * vec_size);\n}\n\n/*!\n * \\brief CUDA kernel to append new keys/values to the paged key-value cache in the prefill phase\n * \\tparam head_dim The dimension of each head\n * \\tparam vec_size The vector size used in the kernel\n * \\tparam DType The data type of the key-value cache\n * \\tparam IdType The index data type of the kv-cache\n * \\param paged_kv The paged key-value cache\n * \\param key The key to be appended\n * \\param value The value to be appended\n * \\param batch_indices The batch indices of elements to be appended\n * \\param positions The positions of elements to be appended\n */\ntemplate <uint32_t head_dim, uint32_t vec_size, typename DType, typename IdType>\n__global__ void AppendPagedKVCacheKernel(paged_kv_t<DType, IdType> paged_kv,\n DType* __restrict__ append_key,\n DType* __restrict__ append_value,\n IdType* __restrict__ batch_indices,\n IdType* __restrict__ positions, uint32_t nnz,\n size_t append_k_stride_n, size_t append_k_stride_h,\n size_t append_v_stride_n, size_t append_v_stride_h) {\n uint32_t tx = threadIdx.x, ty = threadIdx.y;\n uint32_t num_heads = paged_kv.num_heads;\n uint32_t head_idx = ty;\n uint32_t cta_id = blockIdx.x;\n uint32_t num_ctas = gridDim.x;\n\n#pragma unroll 4\n for (uint32_t i = cta_id; i < nnz; i += num_ctas) {\n uint32_t page_iter, entry_idx;\n paged_kv.page_size.divmod(paged_kv.indptr[batch_indices[i]] * paged_kv.page_size + positions[i],\n page_iter, entry_idx);\n DType* k_ptr = paged_kv.get_k_ptr(page_iter, head_idx, entry_idx, tx * vec_size);\n DType* v_ptr = paged_kv.get_v_ptr(page_iter, head_idx, entry_idx, tx * vec_size);\n vec_t<DType, vec_size>::memcpy(\n k_ptr, append_key + i * append_k_stride_n + head_idx * append_k_stride_h + tx * vec_size);\n vec_t<DType, vec_size>::memcpy(\n v_ptr, append_value + i * append_v_stride_n + head_idx * append_v_stride_h + tx * vec_size);\n }\n}\n\n/*!\n * \\brief Append new keys/values to the paged key-value cache in the decode phase\n * \\tparam DType The data type of the key-value cache\n * \\tparam IdType The index data type of the kv-cache\n * \\param paged_kv The paged key-value cache\n * \\param key The key to be appended\n * \\param value The value to be appended\n * \\param stream The CUDA stream to execute kernels.\n * \\return status Indicates whether CUDA calls are successful\n */\ntemplate <typename DType, typename IdType>\ncudaError_t AppendPagedKVCacheDecode(paged_kv_t<DType, IdType> paged_kv, DType* key, DType* value,\n cudaStream_t stream = nullptr) {\n uint32_t head_dim = paged_kv.head_dim;\n uint32_t batch_size = paged_kv.batch_size;\n uint32_t num_heads = paged_kv.num_heads;\n DISPATCH_HEAD_DIM(head_dim, HEAD_DIM, {\n constexpr uint32_t vec_size = std::max(16 / sizeof(DType), HEAD_DIM / 32);\n uint32_t bdx = HEAD_DIM / vec_size;\n uint32_t bdy = num_heads;\n // NOTE(Zihao): could be slow for small batch size, will optimize later\n dim3 nblks(batch_size);\n dim3 nthrs(bdx, bdy);\n auto kernel = AppendPagedKVCacheDecodeKernel<HEAD_DIM, vec_size, DType, IdType>;\n void* args[] = {(void*)&paged_kv, (void*)&key, (void*)&value};\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)kernel, nblks, nthrs, args, 0, stream));\n });\n return cudaSuccess;\n}\n\n/*!\n * \\brief Append new keys/values to the paged key-value cache\n * \\tparam layout The layout of last 3 dimension in KV-Cache\n * \\tparam DType The data type of the key-value cache\n * \\tparam IdType The index data type of the kv-cache\n * \\param paged_kv The paged key-value cache\n * \\param key The key to be appended\n * \\param value The value to be appended\n * \\param append_indptr The indptr array of the appended ragged tensor\n * \\param stream The CUDA stream to execute kernels.\n * \\return status Indicates whether CUDA calls are successful\n */\ntemplate <typename DType, typename IdType>\ncudaError_t AppendPagedKVCache(paged_kv_t<DType, IdType> paged_kv, DType* append_key,\n DType* append_value, IdType* batch_indices, IdType* positions,\n uint32_t nnz, size_t append_k_stride_n, size_t append_k_stride_h,\n size_t append_v_stride_n, size_t append_v_stride_h,\n cudaStream_t stream = nullptr) {\n uint32_t head_dim = paged_kv.head_dim;\n uint32_t num_heads = paged_kv.num_heads;\n int dev_id = 0;\n int num_sms = 0;\n int num_blocks_per_sm = 0;\n FLASHINFER_CUDA_CALL(cudaGetDevice(&dev_id));\n FLASHINFER_CUDA_CALL(cudaDeviceGetAttribute(&num_sms, cudaDevAttrMultiProcessorCount, dev_id));\n\n DISPATCH_HEAD_DIM(head_dim, HEAD_DIM, {\n constexpr uint32_t vec_size = std::max(16 / sizeof(DType), HEAD_DIM / 32);\n uint32_t bdx = HEAD_DIM / vec_size;\n uint32_t bdy = num_heads;\n uint32_t num_threads = bdx * bdy;\n uint32_t smem_size = 0;\n auto kernel = AppendPagedKVCacheKernel<HEAD_DIM, vec_size, DType, IdType>;\n FLASHINFER_CUDA_CALL(cudaOccupancyMaxActiveBlocksPerMultiprocessor(&num_blocks_per_sm, kernel,\n num_threads, smem_size));\n num_blocks_per_sm = min(num_blocks_per_sm, ceil_div(int(nnz), num_sms));\n dim3 nblks(num_blocks_per_sm * num_sms);\n dim3 nthrs(bdx, bdy);\n\n void* args[] = {(void*)&paged_kv, (void*)&append_key, (void*)&append_value,\n (void*)&batch_indices, (void*)&positions, (void*)&nnz,\n (void*)&append_k_stride_n, (void*)&append_k_stride_h, (void*)&append_v_stride_n,\n (void*)&append_v_stride_h};\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)kernel, nblks, nthrs, args, 0, stream));\n });\n return cudaSuccess;\n}\n\ntemplate <typename DType, typename IdType>\nstruct paged_kv_mla_t {\n uint_fastdiv page_size;\n uint32_t head_dim_ckv;\n uint32_t head_dim_kpe;\n uint32_t batch_size;\n uint32_t stride_page_ckv;\n uint32_t stride_page_kpe;\n uint32_t stride_n_ckv;\n uint32_t stride_n_kpe;\n\n // Internal layout:\n // [max_num_pages, page_size, head_dim]\n DType* ckv_data;\n DType* kpe_data;\n IdType* indices;\n\n // [batch_size + 1] The page indptr array, with the first element 0, the last element nnz_pages\n IdType* indptr;\n // [batch_size] The offset of the last page for each request in the batch\n IdType* last_page_len;\n // [batch_size] The start position of each request in the batch.\n IdType* rope_pos_offset;\n\n /*!\n * \\brief Construct an empty paged key-value cache\n */\n __host__ __device__ __forceinline__ paged_kv_mla_t()\n : head_dim_ckv(0),\n head_dim_kpe(0),\n batch_size(0),\n stride_page_ckv(0),\n stride_page_kpe(0),\n stride_n_ckv(0),\n stride_n_kpe(0),\n ckv_data(nullptr),\n kpe_data(nullptr),\n indices(nullptr),\n indptr(nullptr),\n last_page_len(nullptr),\n rope_pos_offset(nullptr) {}\n\n /*!\n * \\brief Construct a paged mla kv cache\n * \\param page_size The size of each page\n * \\param head_dim_compressed_kv The dimension of compressed-kv\n * \\param head_dim_kpe The dimension of k-pe\n * \\param batch_size The batch size\n * \\param compressed_kv_data The start pointer of compressed-kv cache, cache should be contiguous\n * \\param kpe_data The start pointer of k-pe cache, cache should be contiguous\n * \\param indices The page indices array\n * \\param indptr The page indptr array\n * \\param last_page_len The offset of the last page for each request in the batch\n * \\param rope_pos_offset The start position of each request in the batch.\n */\n __host__ __forceinline__ paged_kv_mla_t(uint32_t page_size, uint32_t head_dim_compressed_kv,\n uint32_t head_dim_kpe, uint32_t batch_size,\n DType* compressed_kv_data, DType* kpe_data,\n IdType* indices, IdType* indptr, IdType* last_page_len,\n IdType* rope_pos_offset = nullptr)\n : page_size(page_size),\n head_dim_ckv(head_dim_compressed_kv),\n head_dim_kpe(head_dim_kpe),\n batch_size(batch_size),\n ckv_data(compressed_kv_data),\n kpe_data(kpe_data),\n indices(indices),\n indptr(indptr),\n last_page_len(last_page_len),\n rope_pos_offset(rope_pos_offset) {\n stride_page_ckv = page_size * head_dim_ckv;\n stride_n_ckv = head_dim_ckv;\n stride_page_kpe = page_size * head_dim_kpe;\n stride_n_kpe = head_dim_kpe;\n }\n\n /*!\n * \\brief Construct a paged key-value cache with custom kv-cache strides\n * \\param page_size The size of each page\n * \\param head_dim_compressed_kv The dimension of compressed-kv\n * \\param head_dim_kpe The dimension of k-pe\n * \\param batch_size The batch size\n * \\param compressed_kv_data The start pointer of compressed-kv cache, cache should be contiguous\n * \\param compressed_kv_strides custom strides of each dimensions of compressed-kv cache\n * \\param kpe_data The start pointer of k-pe cache, cache should be contiguous\n * \\param kpe_strides custom strides of each dimensions of k-pe cache\n * \\param indices The page indices array\n * \\param indptr The page indptr array\n * \\param last_page_len The offset of the last page for each request in the batch\n * \\param rope_pos_offset The start position of each request in the batch.\n */\n __host__ __forceinline__ paged_kv_mla_t(uint32_t page_size, uint32_t head_dim_compressed_kv,\n uint32_t head_dim_kpe, uint32_t batch_size,\n DType* compressed_kv_data,\n const int64_t* compressed_kv_strides, DType* kpe_data,\n const int64_t* kpe_strides, IdType* indices,\n IdType* indptr, IdType* last_page_len,\n IdType* rope_pos_offset = nullptr)\n : page_size(page_size),\n head_dim_ckv(head_dim_compressed_kv),\n head_dim_kpe(head_dim_kpe),\n batch_size(batch_size),\n ckv_data(compressed_kv_data),\n kpe_data(kpe_data),\n indices(indices),\n indptr(indptr),\n last_page_len(last_page_len),\n rope_pos_offset(rope_pos_offset) {\n stride_page_ckv = compressed_kv_strides[0];\n stride_n_ckv = compressed_kv_strides[1];\n stride_page_kpe = kpe_strides[0];\n stride_n_kpe = kpe_strides[1];\n }\n\n __host__ __device__ __forceinline__ uint32_t get_length(uint32_t batch_idx) const {\n if (indptr[batch_idx + 1] == indptr[batch_idx]) {\n return 0;\n }\n return (indptr[batch_idx + 1] - indptr[batch_idx] - 1) * page_size + last_page_len[batch_idx];\n }\n\n __host__ __device__ __forceinline__ size_t get_elem_offset_ckv(size_t page_idx, size_t entry_idx,\n size_t feat_idx) const {\n return page_idx * stride_page_ckv + entry_idx * stride_n_ckv + feat_idx;\n }\n\n __device__ __forceinline__ size_t protective_get_offset_ckv(IdType page_iter, uint32_t entry_idx,\n uint32_t feat_idx,\n IdType last_indptr) const {\n if (page_iter < last_indptr) {\n return get_elem_offset_ckv(__ldg(indices + page_iter), entry_idx, feat_idx);\n } else {\n return 0;\n }\n }\n\n __host__ __device__ __forceinline__ size_t get_elem_offset_kpe(size_t page_idx, size_t entry_idx,\n size_t feat_idx) const {\n return page_idx * stride_page_kpe + entry_idx * stride_n_kpe + feat_idx;\n }\n\n __device__ __forceinline__ size_t protective_get_offset_kpe(IdType page_iter, uint32_t entry_idx,\n uint32_t feat_idx,\n IdType last_indptr) const {\n if (page_iter < last_indptr) {\n return get_elem_offset_kpe(__ldg(indices + page_iter), entry_idx, feat_idx);\n } else {\n return 0;\n }\n }\n};\n\n} // namespace flashinfer\n\n#endif // FLAHSINFER_PAGE_CUH_\n"},"diff":{"kind":"string","value":"--- include/flashinfer/page.cuh\n+++ include/flashinfer/page.cuh\n@@ -249,38 +249,34 @@\n * \\param paged_kv The paged key-value cache\n * \\param key The key to be appended\n * \\param value The value to be appended\n- * \\param append_indptr The indptr array of the appended ragged tensor\n+ * \\param batch_indices The batch indices of elements to be appended\n+ * \\param positions The positions of elements to be appended\n */\n template <uint32_t head_dim, uint32_t vec_size, typename DType, typename IdType>\n-__global__ void AppendPagedKVCachePrefillKernel(paged_kv_t<DType, IdType> paged_kv,\n- DType* __restrict__ key, DType* __restrict__ value,\n- IdType* __restrict__ append_indptr) {\n+__global__ void AppendPagedKVCacheKernel(paged_kv_t<DType, IdType> paged_kv,\n+ DType* __restrict__ append_key,\n+ DType* __restrict__ append_value,\n+ IdType* __restrict__ batch_indices,\n+ IdType* __restrict__ positions, uint32_t nnz,\n+ size_t append_k_stride_n, size_t append_k_stride_h,\n+ size_t append_v_stride_n, size_t append_v_stride_h) {\n uint32_t tx = threadIdx.x, ty = threadIdx.y;\n uint32_t num_heads = paged_kv.num_heads;\n- uint32_t batch_idx = blockIdx.x;\n uint32_t head_idx = ty;\n-\n- uint32_t seq_len =\n- (paged_kv.indptr[batch_idx + 1] - paged_kv.indptr[batch_idx] - 1) * paged_kv.page_size +\n- paged_kv.last_page_len[batch_idx];\n- uint32_t append_seq_len = append_indptr[batch_idx + 1] - append_indptr[batch_idx];\n- uint32_t append_start = seq_len - append_seq_len;\n-\n-#pragma unroll 2\n- for (uint32_t j = 0; j < append_seq_len; ++j) {\n- uint32_t page_seq_idx = j + append_start;\n- uint32_t page_iter = paged_kv.indptr[batch_idx] + page_seq_idx / paged_kv.page_size;\n- uint32_t entry_idx = page_seq_idx % paged_kv.page_size;\n-\n+ uint32_t cta_id = blockIdx.x;\n+ uint32_t num_ctas = gridDim.x;\n+\n+#pragma unroll 4\n+ for (uint32_t i = cta_id; i < nnz; i += num_ctas) {\n+ uint32_t page_iter, entry_idx;\n+ paged_kv.page_size.divmod(paged_kv.indptr[batch_indices[i]] * paged_kv.page_size + positions[i],\n+ page_iter, entry_idx);\n DType* k_ptr = paged_kv.get_k_ptr(page_iter, head_idx, entry_idx, tx * vec_size);\n DType* v_ptr = paged_kv.get_v_ptr(page_iter, head_idx, entry_idx, tx * vec_size);\n vec_t<DType, vec_size>::memcpy(\n- k_ptr,\n- key + ((append_indptr[batch_idx] + j) * num_heads + head_idx) * head_dim + tx * vec_size);\n-\n+ k_ptr, append_key + i * append_k_stride_n + head_idx * append_k_stride_h + tx * vec_size);\n vec_t<DType, vec_size>::memcpy(\n- v_ptr,\n- value + ((append_indptr[batch_idx] + j) * num_heads + head_idx) * head_dim + tx * vec_size);\n+ v_ptr, append_value + i * append_v_stride_n + head_idx * append_v_stride_h + tx * vec_size);\n }\n }\n \n@@ -327,20 +323,36 @@\n * \\return status Indicates whether CUDA calls are successful\n */\n template <typename DType, typename IdType>\n-cudaError_t AppendPagedKVCache(paged_kv_t<DType, IdType> paged_kv, DType* key, DType* value,\n- IdType* append_indptr, cudaStream_t stream = nullptr) {\n+cudaError_t AppendPagedKVCache(paged_kv_t<DType, IdType> paged_kv, DType* append_key,\n+ DType* append_value, IdType* batch_indices, IdType* positions,\n+ uint32_t nnz, size_t append_k_stride_n, size_t append_k_stride_h,\n+ size_t append_v_stride_n, size_t append_v_stride_h,\n+ cudaStream_t stream = nullptr) {\n uint32_t head_dim = paged_kv.head_dim;\n- uint32_t batch_size = paged_kv.batch_size;\n uint32_t num_heads = paged_kv.num_heads;\n+ int dev_id = 0;\n+ int num_sms = 0;\n+ int num_blocks_per_sm = 0;\n+ FLASHINFER_CUDA_CALL(cudaGetDevice(&dev_id));\n+ FLASHINFER_CUDA_CALL(cudaDeviceGetAttribute(&num_sms, cudaDevAttrMultiProcessorCount, dev_id));\n+\n DISPATCH_HEAD_DIM(head_dim, HEAD_DIM, {\n constexpr uint32_t vec_size = std::max(16 / sizeof(DType), HEAD_DIM / 32);\n uint32_t bdx = HEAD_DIM / vec_size;\n uint32_t bdy = num_heads;\n- // NOTE(Zihao): could be slow for small batch size, will optimize later\n- dim3 nblks(batch_size);\n+ uint32_t num_threads = bdx * bdy;\n+ uint32_t smem_size = 0;\n+ auto kernel = AppendPagedKVCacheKernel<HEAD_DIM, vec_size, DType, IdType>;\n+ FLASHINFER_CUDA_CALL(cudaOccupancyMaxActiveBlocksPerMultiprocessor(&num_blocks_per_sm, kernel,\n+ num_threads, smem_size));\n+ num_blocks_per_sm = min(num_blocks_per_sm, ceil_div(int(nnz), num_sms));\n+ dim3 nblks(num_blocks_per_sm * num_sms);\n dim3 nthrs(bdx, bdy);\n- auto kernel = AppendPagedKVCachePrefillKernel<HEAD_DIM, vec_size, DType, IdType>;\n- void* args[] = {(void*)&paged_kv, (void*)&key, (void*)&value, (void*)&append_indptr};\n+\n+ void* args[] = {(void*)&paged_kv, (void*)&append_key, (void*)&append_value,\n+ (void*)&batch_indices, (void*)&positions, (void*)&nnz,\n+ (void*)&append_k_stride_n, (void*)&append_k_stride_h, (void*)&append_v_stride_n,\n+ (void*)&append_v_stride_h};\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)kernel, nblks, nthrs, args, 0, stream));\n });\n return cudaSuccess;"},"lines_added":{"kind":"number","value":42,"string":"42"},"lines_removed":{"kind":"number","value":30,"string":"30"},"files_in_commit":{"kind":"number","value":1,"string":"1"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (include/flashinfer/page.cuh).\n\nGoal: perf: fix the performance issue of `append_paged_kv_cache`\nTarget hardware: unspecified\nTarget models: unspecified\n\nCurrent file:\n```cuda\n/*\n * Copyright (c) 2023 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_PAGE_CUH_\n#define FLASHINFER_PAGE_CUH_\n\n#include <vector>\n\n#include \"fastdiv.cuh\"\n#include \"layout.cuh\"\n#include \"utils.cuh\"\n#include \"vec_dtypes.cuh\"\n\nnamespace flashinfer {\n\n/*!\n * \\brief Paged key-value cache\n * \\tparam layout The layout of last 3 dimensions in KV-Cache.\n * \\tparam DType The data type of the key-value cache\n * \\tparam IdType The index data type of the kv-cache\n */\ntemplate <typename DType, typename IdType>\nstruct paged_kv_t {\n uint_fastdiv page_size;\n uint32_t num_heads;\n uint32_t head_dim;\n uint32_t batch_size;\n uint32_t stride_page;\n uint32_t stride_n;\n uint32_t stride_h;\n\n // Internal layout:\n // [max_num_pages, num_heads, page_size, head_dim] if layout == HND\n // [max_num_pages, page_size, num_heads, head_dim] if layout == NHD\n DType* k_data;\n DType* v_data;\n IdType* indices;\n\n // [batch_size + 1] The page indptr array, with the first element 0, the last element nnz_pages\n IdType* indptr;\n // [batch_size] The offset of the last page for each request in the batch\n IdType* last_page_len;\n // [batch_size] The start position of each request in the batch.\n IdType* rope_pos_offset;\n\n /*!\n * \\brief Construct an empty paged key-value cache\n */\n __host__ __device__ __forceinline__ paged_kv_t()\n : num_heads(0),\n page_size(0),\n head_dim(0),\n batch_size(0),\n stride_page(0),\n stride_n(0),\n stride_h(0),\n k_data(nullptr),\n v_data(nullptr),\n indices(nullptr),\n indptr(nullptr),\n last_page_len(nullptr),\n rope_pos_offset(nullptr) {}\n\n /*!\n * \\brief Construct a paged key-value cache\n * \\param num_heads The number of heads\n * \\param page_size The size of each page\n * \\param head_dim The dimension of each head\n * \\param batch_size The batch size\n * \\param layout The layout of last 3 dimensions in KV-Cache.\n * \\param k_data The start pointer of key cache, k_cache should be contiguous\n * \\param v_data The start pointer of value cache, v_cache should be contiguous\n * \\param indices The page indices array\n * \\param indptr The page indptr array\n * \\param last_page_len The offset of the last page for each request in the batch\n * \\param rope_pos_offset The start position of each request in the batch.\n */\n __host__ __forceinline__ paged_kv_t(uint32_t num_heads, uint32_t page_size, uint32_t head_dim,\n uint32_t batch_size, QKVLayout layout, DType* k_data,\n DType* v_data, IdType* indices, IdType* indptr,\n IdType* last_page_len, IdType* rope_pos_offset = nullptr)\n : num_heads(num_heads),\n page_size(page_size),\n head_dim(head_dim),\n batch_size(batch_size),\n indices(indices),\n indptr(indptr),\n last_page_len(last_page_len),\n rope_pos_offset(rope_pos_offset) {\n stride_page = num_heads * page_size * head_dim;\n this->k_data = k_data;\n this->v_data = v_data;\n stride_n = layout == QKVLayout::kHND ? head_dim : num_heads * head_dim;\n stride_h = layout == QKVLayout::kHND ? page_size * head_dim : head_dim;\n }\n\n /*!\n * \\brief Construct a paged key-value cache with custom kv-cache strides\n * \\param num_heads The number of heads\n * \\param page_size The size of each page\n * \\param head_dim The dimension of each head\n * \\param batch_size The batch size\n * \\param layout The layout of last 3 dimensions in KV-Cache.\n * \\param k_data The start pointer of key cache, k_cache doesn't have to be contiguous\n * \\param v_data The start pointer of value cache, v_cache doesn't have to be contiguous\n * \\param kv_strides custom strides of each dimensions of k_data and v_data\n * \\param indices The page indices array\n * \\param indptr The page indptr array\n * \\param last_page_len The offset of the last page for each request in the batch\n * \\param rope_pos_offset The start position of each request in the batch.\n */\n __host__ __forceinline__ paged_kv_t(uint32_t num_heads, uint32_t page_size, uint32_t head_dim,\n uint32_t batch_size, QKVLayout layout, DType* k_data,\n DType* v_data, const int64_t* kv_strides, IdType* indices,\n IdType* indptr, IdType* last_page_len,\n IdType* rope_pos_offset = nullptr)\n : num_heads(num_heads),\n page_size(page_size),\n head_dim(head_dim),\n batch_size(batch_size),\n indices(indices),\n indptr(indptr),\n last_page_len(last_page_len),\n rope_pos_offset(rope_pos_offset) {\n stride_page = kv_strides[0];\n this->k_data = k_data;\n this->v_data = v_data;\n stride_n = layout == QKVLayout::kHND ? kv_strides[2] : kv_strides[1];\n stride_h = layout == QKVLayout::kHND ? kv_strides[1] : kv_strides[2];\n }\n\n __host__ __device__ __forceinline__ uint32_t get_length(uint32_t batch_idx) const {\n if (indptr[batch_idx + 1] == indptr[batch_idx]) {\n return 0;\n }\n return (indptr[batch_idx + 1] - indptr[batch_idx] - 1) * page_size + last_page_len[batch_idx];\n }\n\n /*!\n * \\brief Compute the offset of element in the allocated buffer.\n * \\param page_idx The page index\n * \\param head_idx The head index\n * \\param entry_idx The page entry index\n * \\param feat_idx The feature index\n */\n __host__ __device__ __forceinline__ size_t get_elem_offset(size_t page_idx, size_t head_idx,\n size_t entry_idx,\n size_t feat_idx) const {\n return page_idx * stride_page + head_idx * stride_h + entry_idx * stride_n + feat_idx;\n }\n\n /*!\n * \\brief Compute the offset of element inside the page.\n * \\param head_idx The head index\n * \\param entry_idx The page entry index\n * \\param feat_idx The feature index\n */\n __host__ __device__ __forceinline__ size_t get_elem_offset_in_page(size_t head_idx,\n size_t entry_idx,\n size_t feat_idx) const {\n return head_idx * stride_h + entry_idx * stride_n + feat_idx;\n }\n\n __device__ __forceinline__ DType* get_k_ptr(IdType page_iter, uint32_t head_idx,\n uint32_t entry_idx, uint32_t feat_idx) const {\n return k_data + get_elem_offset(__ldg(indices + page_iter), head_idx, entry_idx, feat_idx);\n }\n\n __device__ __forceinline__ size_t protective_get_kv_offset(IdType page_iter, uint32_t head_idx,\n uint32_t entry_idx, uint32_t feat_idx,\n IdType last_indptr) const {\n if (page_iter < last_indptr) {\n return get_elem_offset(__ldg(indices + page_iter), head_idx, entry_idx, feat_idx);\n } else {\n return 0;\n }\n }\n\n __device__ __forceinline__ DType* protective_get_k_ptr(IdType page_iter, uint32_t head_idx,\n uint32_t entry_idx, uint32_t feat_idx,\n IdType last_indptr) const {\n return k_data + protective_get_kv_offset(page_iter, head_idx, entry_idx, feat_idx, last_indptr);\n }\n\n __device__ __forceinline__ DType* get_v_ptr(IdType page_iter, uint32_t head_idx,\n uint32_t entry_idx, uint32_t feat_idx) const {\n return v_data + get_elem_offset(__ldg(indices + page_iter), head_idx, entry_idx, feat_idx);\n }\n\n __device__ __forceinline__ DType* protective_get_v_ptr(IdType page_iter, uint32_t head_idx,\n uint32_t entry_idx, uint32_t feat_idx,\n IdType last_indptr) const {\n return v_data + protective_get_kv_offset(page_iter, head_idx, entry_idx, feat_idx, last_indptr);\n }\n};\n\n/*!\n * \\brief CUDA kernel to append new keys/values to the paged key-value cache in the decode phase\n * \\tparam head_dim The dimension of each head\n * \\tparam vec_size The vector size used in the kernel\n * \\tparam DType The data type of the key-value cache\n * \\tparam IdType The index data type of the kv-cache\n * \\param paged_kv The paged key-value cache\n * \\param key The key to be appended\n * \\param value The value to be appended\n */\ntemplate <uint32_t head_dim, uint32_t vec_size, typename DType, typename IdType>\n__global__ void AppendPagedKVCacheDecodeKernel(paged_kv_t<DType, IdType> paged_kv,\n DType* __restrict__ key, DType* __restrict__ value) {\n uint32_t tx = threadIdx.x, ty = threadIdx.y;\n uint32_t num_heads = paged_kv.num_heads;\n uint32_t batch_idx = blockIdx.x;\n uint32_t head_idx = ty;\n\n uint32_t seq_len =\n (paged_kv.indptr[batch_idx + 1] - paged_kv.indptr[batch_idx] - 1) * paged_kv.page_size +\n paged_kv.last_page_len[batch_idx];\n\n uint32_t page_iter = paged_kv.indptr[batch_idx] + (seq_len - 1) / paged_kv.page_size;\n uint32_t entry_idx = (seq_len - 1) % paged_kv.page_size;\n\n DType* k_ptr = paged_kv.get_k_ptr(page_iter, head_idx, entry_idx, tx * vec_size);\n DType* v_ptr = paged_kv.get_v_ptr(page_iter, head_idx, entry_idx, tx * vec_size);\n vec_t<DType, vec_size>::memcpy(\n k_ptr, key + (batch_idx * num_heads + head_idx) * head_dim + tx * vec_size);\n\n vec_t<DType, vec_size>::memcpy(\n v_ptr, value + (batch_idx * num_heads + head_idx) * head_dim + tx * vec_size);\n}\n\n/*!\n * \\brief CUDA kernel to append new keys/values to the paged key-value cache in the prefill phase\n * \\tparam head_dim The dimension of each head\n * \\tparam vec_size The vector size used in the kernel\n * \\tparam DType The data type of the key-value cache\n * \\tparam IdType The index data type of the kv-cache\n * \\param paged_kv The paged key-value cache\n * \\param key The key to be appended\n * \\param value The value to be appended\n * \\param append_indptr The indptr array of the appended ragged tensor\n */\ntemplate <uint32_t head_dim, uint32_t vec_size, typename DType, typename IdType>\n__global__ void AppendPagedKVCachePrefillKernel(paged_kv_t<DType, IdType> paged_kv,\n DType* __restrict__ key, DType* __restrict__ value,\n IdType* __restrict__ append_indptr) {\n uint32_t tx = threadIdx.x, ty = threadIdx.y;\n uint32_t num_heads = paged_kv.num_heads;\n uint32_t batch_idx = blockIdx.x;\n uint32_t head_idx = ty;\n\n uint32_t seq_len =\n (paged_kv.indptr[batch_idx + 1] - paged_kv.indptr[batch_idx] - 1) * paged_kv.page_size +\n paged_kv.last_page_len[batch_idx];\n uint32_t append_seq_len = append_indptr[batch_idx + 1] - append_indptr[batch_idx];\n uint32_t append_start = seq_len - append_seq_len;\n\n#pragma unroll 2\n for (uint32_t j = 0; j < append_seq_len; ++j) {\n uint32_t page_seq_idx = j + append_start;\n uint32_t page_iter = paged_kv.indptr[batch_idx] + page_seq_idx / paged_kv.page_size;\n uint32_t entry_idx = page_seq_idx % paged_kv.page_size;\n\n DType* k_ptr = paged_kv.get_k_ptr(page_iter, head_idx, entry_idx, tx * vec_size);\n DType* v_ptr = paged_kv.get_v_ptr(page_iter, head_idx, entry_idx, tx * vec_size);\n vec_t<DType, vec_size>::memcpy(\n k_ptr,\n key + ((append_indptr[batch_idx] + j) * num_heads + head_idx) * head_dim + tx * vec_size);\n\n vec_t<DType, vec_size>::memcpy(\n v_ptr,\n value + ((append_indptr[batch_idx] + j) * num_heads + head_idx) * head_dim + tx * vec_size);\n }\n}\n\n/*!\n * \\brief Append new keys/values to the paged key-value cache in the decode phase\n * \\tparam DType The data type of the key-value cache\n * \\tparam IdType The index data type of the kv-cache\n * \\param paged_kv The paged key-value cache\n * \\param key The key to be appended\n * \\param value The value to be appended\n * \\param stream The CUDA stream to execute kernels.\n * \\return status Indicates whether CUDA calls are successful\n */\ntemplate <typename DType, typename IdType>\ncudaError_t AppendPagedKVCacheDecode(paged_kv_t<DType, IdType> paged_kv, DType* key, DType* value,\n cudaStream_t stream = nullptr) {\n uint32_t head_dim = paged_kv.head_dim;\n uint32_t batch_size = paged_kv.batch_size;\n uint32_t num_heads = paged_kv.num_heads;\n DISPATCH_HEAD_DIM(head_dim, HEAD_DIM, {\n constexpr uint32_t vec_size = std::max(16 / sizeof(DType), HEAD_DIM / 32);\n uint32_t bdx = HEAD_DIM / vec_size;\n uint32_t bdy = num_heads;\n // NOTE(Zihao): could be slow for small batch size, will optimize later\n dim3 nblks(batch_size);\n dim3 nthrs(bdx, bdy);\n auto kernel = AppendPagedKVCacheDecodeKernel<HEAD_DIM, vec_size, DType, IdType>;\n void* args[] = {(void*)&paged_kv, (void*)&key, (void*)&value};\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)kernel, nblks, nthrs, args, 0, stream));\n });\n return cudaSuccess;\n}\n\n/*!\n * \\brief Append new keys/values to the paged key-value cache\n * \\tparam layout The layout of last 3 dimension in KV-Cache\n * \\tparam DType The data type of the key-value cache\n * \\tparam IdType The index data type of the kv-cache\n * \\param paged_kv The paged key-value cache\n * \\param key The key to be appended\n * \\param value The value to be appended\n * \\param append_indptr The indptr array of the appended ragged tensor\n * \\param stream The CUDA stream to execute kernels.\n * \\return status Indicates whether CUDA calls are successful\n */\ntemplate <typename DType, typename IdType>\ncudaError_t AppendPagedKVCache(paged_kv_t<DType, IdType> paged_kv, DType* key, DType* value,\n IdType* append_indptr, cudaStream_t stream = nullptr) {\n uint32_t head_dim = paged_kv.head_dim;\n uint32_t batch_size = paged_kv.batch_size;\n uint32_t num_heads = paged_kv.num_heads;\n DISPATCH_HEAD_DIM(head_dim, HEAD_DIM, {\n constexpr uint32_t vec_size = std::max(16 / sizeof(DType), HEAD_DIM / 32);\n uint32_t bdx = HEAD_DIM / vec_size;\n uint32_t bdy = num_heads;\n // NOTE(Zihao): could be slow for small batch size, will optimize later\n dim3 nblks(batch_size);\n dim3 nthrs(bdx, bdy);\n auto kernel = AppendPagedKVCachePrefillKernel<HEAD_DIM, vec_size, DType, IdType>;\n void* args[] = {(void*)&paged_kv, (void*)&key, (void*)&value, (void*)&append_indptr};\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)kernel, nblks, nthrs, args, 0, stream));\n });\n return cudaSuccess;\n}\n\ntemplate <typename DType, typename IdType>\nstruct paged_kv_mla_t {\n uint_fastdiv page_size;\n uint32_t head_dim_ckv;\n uint32_t head_dim_kpe;\n uint32_t batch_size;\n uint32_t stride_page_ckv;\n uint32_t stride_page_kpe;\n uint32_t stride_n_ckv;\n uint32_t stride_n_kpe;\n\n // Internal layout:\n // [max_num_pages, page_size, head_dim]\n DType* ckv_data;\n DType* kpe_data;\n IdType* indices;\n\n // [batch_size + 1] The page indptr array, with the first element 0, the last element nnz_pages\n IdType* indptr;\n // [batch_size] The offset of the last page for each request in the batch\n IdType* last_page_len;\n // [batch_size] The start position of each request in the batch.\n IdType* rope_pos_offset;\n\n /*!\n * \\brief Construct an empty paged key-value cache\n */\n __host__ __device__ __forceinline__ paged_kv_mla_t()\n : head_dim_ckv(0),\n head_dim_kpe(0),\n batch_size(0),\n stride_page_ckv(0),\n stride_page_kpe(0),\n stride_n_ckv(0),\n stride_n_kpe(0),\n ckv_data(nullptr),\n kpe_data(nullptr),\n indices(nullptr),\n indptr(nullptr),\n last_page_len(nullptr),\n rope_pos_offset(nullptr) {}\n\n /*!\n * \\brief Construct a paged mla kv cache\n * \\param page_size The size of each page\n * \\param head_dim_compressed_kv The dimension of compressed-kv\n * \\param head_dim_kpe The dimension of k-pe\n * \\param batch_size The batch size\n * \\param compressed_kv_data The start pointer of compressed-kv cache, cache should be contiguous\n * \\param kpe_data The start pointer of k-pe cache, cache should be contiguous\n * \\param indices The page indices array\n * \\param indptr The page indptr array\n * \\param last_page_len The offset of the last page for each request in the batch\n * \\param rope_pos_offset The start position of each request in the batch.\n */\n __host__ __forceinline__ paged_kv_mla_t(uint32_t page_size, uint32_t head_dim_compressed_kv,\n uint32_t head_dim_kpe, uint32_t batch_size,\n DType* compressed_kv_data, DType* kpe_data,\n IdType* indices, IdType* indptr, IdType* last_page_len,\n IdType* rope_pos_offset = nullptr)\n : page_size(page_size),\n head_dim_ckv(head_dim_compressed_kv),\n head_dim_kpe(head_dim_kpe),\n batch_size(batch_size),\n ckv_data(compressed_kv_data),\n kpe_data(kpe_data),\n indices(indices),\n indptr(indptr),\n last_page_len(last_page_len),\n rope_pos_offset(rope_pos_offset) {\n stride_page_ckv = page_size * head_dim_ckv;\n stride_n_ckv = head_dim_ckv;\n stride_page_kpe = page_size * head_dim_kpe;\n stride_n_kpe = head_dim_kpe;\n }\n\n /*!\n * \\brief Construct a paged key-value cache with custom kv-cache strides\n * \\param page_size The size of each page\n * \\param head_dim_compressed_kv The dimension of compressed-kv\n * \\param head_dim_kpe The dimension of k-pe\n * \\param batch_size The batch size\n * \\param compressed_kv_data The start pointer of compressed-kv cache, cache should be contiguous\n * \\param compressed_kv_strides custom strides of each dimensions of compressed-kv cache\n * \\param kpe_data The start pointer of k-pe cache, cache should be contiguous\n * \\param kpe_strides custom strides of each dimensions of k-pe cache\n * \\param indices The page indices array\n * \\param indptr The page indptr array\n * \\param last_page_len The offset of the last page for each request in the batch\n * \\param rope_pos_offset The start position of each request in the batch.\n */\n __host__ __forceinline__ paged_kv_mla_t(uint32_t page_size, uint32_t head_dim_compressed_kv,\n uint32_t head_dim_kpe, uint32_t batch_size,\n DType* compressed_kv_data,\n const int64_t* compressed_kv_strides, DType* kpe_data,\n const int64_t* kpe_strides, IdType* indices,\n IdType* indptr, IdType* last_page_len,\n IdType* rope_pos_offset = nullptr)\n : page_size(page_size),\n head_dim_ckv(head_dim_compressed_kv),\n head_dim_kpe(head_dim_kpe),\n batch_size(batch_size),\n ckv_data(compressed_kv_data),\n kpe_data(kpe_data),\n indices(indices),\n indptr(indptr),\n last_page_len(last_page_len),\n rope_pos_offset(rope_pos_offset) {\n stride_page_ckv = compressed_kv_strides[0];\n stride_n_ckv = compressed_kv_strides[1];\n stride_page_kpe = kpe_strides[0];\n stride_n_kpe = kpe_strides[1];\n }\n\n __host__ __device__ __forceinline__ uint32_t get_length(uint32_t batch_idx) const {\n if (indptr[batch_idx + 1] == indptr[batch_idx]) {\n return 0;\n }\n return (indptr[batch_idx + 1] - indptr[batch_idx] - 1) * page_size + last_page_len[batch_idx];\n }\n\n __host__ __device__ __forceinline__ size_t get_elem_offset_ckv(size_t page_idx, size_t entry_idx,\n size_t feat_idx) const {\n return page_idx * stride_page_ckv + entry_idx * stride_n_ckv + feat_idx;\n }\n\n __device__ __forceinline__ size_t protective_get_offset_ckv(IdType page_iter, uint32_t entry_idx,\n uint32_t feat_idx,\n IdType last_indptr) const {\n if (page_iter < last_indptr) {\n return get_elem_offset_ckv(__ldg(indices + page_iter), entry_idx, feat_idx);\n } else {\n return 0;\n }\n }\n\n __host__ __device__ __forceinline__ size_t get_elem_offset_kpe(size_t page_idx, size_t entry_idx,\n size_t feat_idx) const {\n return page_idx * stride_page_kpe + entry_idx * stride_n_kpe + feat_idx;\n }\n\n __device__ __forceinline__ size_t protective_get_offset_kpe(IdType page_iter, uint32_t entry_idx,\n uint32_t feat_idx,\n IdType last_indptr) const {\n if (page_iter < last_indptr) {\n return get_elem_offset_kpe(__ldg(indices + page_iter), entry_idx, feat_idx);\n } else {\n return 0;\n }\n }\n};\n\n} // namespace flashinfer\n\n#endif // FLAHSINFER_PAGE_CUH_\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"The performance of `append_paged_kv_cache` is terrible for small batch size, which is a known issue that we haven't fixed for a long time, this PR fixes it. This PR also adds support for non-contiguous append keys/values (which could be sliced from fused qkv matrix).\n\nWe first call a triton kernel to convert `append_indptr` to `batch_indices` and `positions` (which is similar to [CSR2COO conversion](https://docs.nvidia.com/cuda/cusparse/#cusparse-t-csr2coo) in sparse matrix). After the conversion, we can use element parallelism instead of batch parallelism.\n\nIt's also worth trying using triton for the second `AppendPagedKVCacheKernel` kernel, I think the performance should be fine. I'll leave it for future work.\n\nSome todo items:\n1. add torch.compile support.\n\nAfter this PR (reference number can be found at #583 ):\n```bash\nmodel: l1b seqlens: [1, 1, 1, 1, 1, 1, 1, 1] single_layer: 0.006ms all_layers: 0.094ms throughput: 5.563GB/s\nmodel: l1b seqlens: [4993, 1, 1, 1, 1, 1, 1, 1] single_layer: 0.014ms all_layers: 0.216ms throughput: 1514.280GB/s\nmodel: l1b seqlens: [5000] single_layer: 0.014ms all_layers: 0.216ms throughput: 1517.017GB/s\nmodel: l1b seqlens: [625, 625, 625, 625, 625, 625, 625, 625] single_layer: 0.014ms all_layers: 0.217ms throughput: 1510.863GB/s\n---\nmodel: l3b seqlens: [1, 1, 1, 1, 1, 1, 1, 1] single_layer: 0.006ms all_layers: 0.165ms throughput: 11.123GB/s\nmodel: l3b seqlens: [4993, 1, 1, 1, 1, 1, 1, 1] single_layer: 0.021ms all_layers: 0.580ms throughput: 1975.732GB/s\nmodel: l3b seqlens: [5000] single_layer: 0.021ms all_layers: 0.586ms throughput: 1958.078GB/s\nmodel: l3b seqlens: [625, 625, 625, 625, 625, 625, 625, 625] single_layer: 0.021ms all_layers: 0.581ms throughput: 1973.174GB/s\n---\nmodel: l8b seqlens: [1, 1, 1, 1, 1, 1, 1, 1] single_layer: 0.006ms all_layers: 0.185ms throughput: 11.321GB/s\nmodel: l8b seqlens: [4993, 1, 1, 1, 1, 1, 1, 1] single_layer: 0.021ms all_layers: 0.661ms throughput: 1982.815GB/s\nmodel: l8b seqlens: [5000] single_layer: 0.021ms all_layers: 0.662ms throughput: 1980.227GB/s\nmodel: l8b seqlens: [625, 625, 625, 625, 625, 625, 625, 625] single_layer: 0.021ms all_layers: 0.667ms throughput: 1964.861GB/s\n---\nmodel: l70b-tp8 seqlens: [1, 1, 1, 1, 1, 1, 1, 1] single_layer: 0.006ms all_layers: 0.457ms throughput: 1.434GB/s\nmodel: l70b-tp8 seqlens: [4993, 1, 1, 1, 1, 1, 1, 1] single_layer: 0.009ms all_layers: 0.710ms throughput: 576.866GB/s\nmodel: l70b-tp8 seqlens: [5000] single_layer: 0.009ms all_layers: 0.685ms throughput: 598.366GB/s\nmodel: l70b-tp8 seqlens: [625, 625, 625, 625, 625, 625, 625, 625] single_layer: 0.009ms all_layers: 0.690ms throughput: 593.453GB/s\n```\n\ncc @abcdabcd987 \n\n"},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1295,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"be6bf5bb26f1f1b3edf094d903544600c574ee09"},"date":{"kind":"string","value":"2024-08-21T12:08:36-07:00"},"pr_number":{"kind":"number","value":459,"string":"459"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/459"},"title":{"kind":"string","value":"perf: use persistent kernel for merging attention states (#459)"},"message":{"kind":"string","value":"perf: use persistent kernel for merging attention states (#459)\n\nAs observed by @MasterJH5574 , there are cases where our\r\n`VariableLengthMergeStatesKernel` launches a lot of CTAs (>=10k) while\r\nmost of the CTAs only work on small number of merges, this PR fixes the\r\nissue by using a persistent kernel.\r\n\r\nThere is still load imbalance issue, and I plan to resolve it inside\r\nscheduler. I'll leave it for later PRs."},"path":{"kind":"string","value":"include/flashinfer/attention/cascade.cuh"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*!\n * Copyright (c) 2023 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_CASCADE_CUH_\n#define FLASHINFER_CASCADE_CUH_\n\n#include <cooperative_groups.h>\n\n#include \"../cp_async.cuh\"\n#include \"../math.cuh\"\n#include \"../utils.cuh\"\n#include \"state.cuh\"\n\nnamespace flashinfer {\n\nnamespace cg = cooperative_groups;\nusing cp_async::PrefetchMode;\nusing cp_async::SharedMemFillMode;\n\n/*!\n * \\brief The CUDA kernel that merges the self-attention state of two index sets A and B.\n * \\tparam vec_size The vector size used in the kernel.\n * \\tparam DTypeIn The data type of v_a and v_b.\n * \\tparam DTypeOut The data type of v_merged.\n * \\param v_a The partial v of index set A. (n, h, d)\n * \\param s_a The logsumexp value of index set A. (n, h)\n * \\param v_b The partial v of index set B. (n, h, d)\n * \\param s_b The logsumexp value of index set B. (n, h)\n * \\param v_merged The merged v of index set A union B. (n, h, d)\n * \\param s_merged The merged logsumexp value of index set A union B. (n, h)\n * \\param num_heads The number of heads of v_a and v_b.\n * \\param head_dim The dimension of each head.\n * \\note Both s_a and s_b are logsumexp values with base 2.\n */\ntemplate <uint32_t vec_size, typename DTypeIn, typename DTypeOut>\n__global__ void MergeStateKernel(DTypeIn* __restrict__ v_a, float* __restrict__ s_a,\n DTypeIn* __restrict__ v_b, float* __restrict__ s_b,\n DTypeOut* __restrict__ v_merged, float* __restrict__ s_merged,\n uint32_t num_heads, uint32_t head_dim) {\n uint32_t tx = threadIdx.x, ty = threadIdx.y;\n uint32_t pos = blockIdx.x;\n uint32_t head_idx = ty;\n\n float s_a_val = s_a[pos * num_heads + head_idx];\n float s_b_val = s_b[pos * num_heads + head_idx];\n float s_max = max(s_a_val, s_b_val);\n s_a_val = math::ptx_exp2(s_a_val - s_max);\n s_b_val = math::ptx_exp2(s_b_val - s_max);\n float a_scale = s_a_val / (s_a_val + s_b_val);\n float b_scale = s_b_val / (s_a_val + s_b_val);\n vec_t<float, vec_size> v_a_vec, v_b_vec, v_merged_vec;\n v_a_vec.cast_load(v_a + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n v_b_vec.cast_load(v_b + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n#pragma unroll\n for (uint32_t i = 0; i < vec_size; ++i) {\n v_merged_vec[i] = a_scale * v_a_vec[i] + b_scale * v_b_vec[i];\n }\n v_merged_vec.cast_store(v_merged + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n if (s_merged != nullptr) {\n s_merged[pos * num_heads + head_idx] = math::ptx_log2(s_a_val + s_b_val) + s_max;\n }\n}\n\n/*!\n * \\brief The CUDA kernel that merges the self-attention state with another state in-place.\n * \\tparam vec_size The vector size used in the kernel.\n * \\tparam DType The data type of v and v_other.\n * \\param v The partial v to be updated in-place. (n, h, d)\n * \\param s The logsumexp value to be updated in-place. (n, h)\n * \\param v_other The other v to be merged. (n, h, d)\n * \\param s_other The other logsumexp value to be merged. (n, h)\n * \\param mask Optional mask of whether to merge given sequences or not. (n)\n * \\param num_heads The number of heads of v and v_other.\n * \\param head_dim The dimension of each head.\n * \\note Both s and s_other are logsumexp values with base 2.\n */\ntemplate <uint32_t vec_size, typename DType>\n__global__ void MergeStateInPlaceKernel(DType* __restrict__ v, float* __restrict__ s,\n DType* __restrict__ v_other, float* __restrict__ s_other,\n uint8_t* __restrict__ mask, uint32_t num_heads,\n uint32_t head_dim) {\n uint32_t pos = blockIdx.x;\n\n if (mask != nullptr && mask[pos] == 0) return;\n\n uint32_t tx = threadIdx.x, ty = threadIdx.y;\n uint32_t head_idx = ty;\n\n float s_val = s[pos * num_heads + head_idx];\n float s_other_val = s_other[pos * num_heads + head_idx];\n float s_max = max(s_val, s_other_val);\n s_val = math::ptx_exp2(s_val - s_max);\n s_other_val = math::ptx_exp2(s_other_val - s_max);\n float scale = s_val / (s_val + s_other_val);\n float other_scale = s_other_val / (s_val + s_other_val);\n vec_t<float, vec_size> v_vec, v_other_vec;\n v_vec.cast_load(v + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n v_other_vec.cast_load(v_other + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n#pragma unroll\n for (uint32_t i = 0; i < vec_size; ++i) {\n v_vec[i] = scale * v_vec[i] + other_scale * v_other_vec[i];\n }\n v_vec.cast_store(v + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n if (s != nullptr) {\n s[pos * num_heads + head_idx] = math::ptx_log2(s_val + s_other_val) + s_max;\n }\n}\n\ntemplate <uint32_t bdx, uint32_t bdy, uint32_t vec_size, typename DTypeIn>\n__device__ __forceinline__ void threadblock_sync_state(state_t<vec_size>& st, DTypeIn* v_smem,\n float* s_smem) {\n const uint32_t tx = threadIdx.x, ty = threadIdx.y;\n constexpr uint32_t head_dim = vec_size * bdx;\n st.o.cast_store(v_smem + ty * head_dim + tx * vec_size);\n s_smem[ty] = st.get_lse();\n st.init();\n __syncthreads();\n\n#pragma unroll\n for (uint32_t iter = 0; iter < bdy; ++iter) {\n float s = s_smem[iter];\n vec_t<float, vec_size> v;\n v.cast_load(v_smem + iter * head_dim + tx * vec_size);\n st.merge(v, s, 1);\n }\n}\n\n/*!\n * \\brief The CUDA kernel that merges self-attention states of a list of index sets.\n * \\param vec_size The vector size used in the kernel.\n * \\tparam DTypeIn The data type of v.\n * \\tparam DTypeOut The data type of v_merged.\n * \\param v The partial v of index sets. (n, num_index_sets, h, d)\n * \\param s The logsumexp value of index sets. (n, num_index_sets, h)\n * \\param v_merged The merged v of index sets union. (n, h, d)\n * \\param s_merged The merged logsumexp value of index sets union. (n, h)\n * \\param num_heads The number of heads of v.\n * \\param head_dim The dimension of each head.\n * \\note s are logsumexp values with base 2.\n */\ntemplate <uint32_t vec_size, typename DTypeIn, typename DTypeOut>\n__global__ void MergeStatesKernel(DTypeIn* __restrict__ V, float* __restrict__ S,\n DTypeOut* __restrict__ v_merged, float* __restrict__ s_merged,\n uint32_t num_index_sets, uint32_t num_heads, uint32_t head_dim) {\n uint32_t tx = threadIdx.x, ty = threadIdx.y;\n uint32_t pos = blockIdx.x;\n uint32_t head_idx = ty;\n\n if (num_index_sets == 0) {\n vec_t<DTypeOut, vec_size> v;\n v.fill(DTypeOut(0));\n v.store(v_merged + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n if (s_merged != nullptr) {\n s_merged[pos * num_heads + head_idx] = -5e4;\n }\n return;\n }\n\n if (num_index_sets == 1) {\n vec_t<DTypeOut, vec_size> v;\n v.cast_load(V + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n v.store(v_merged + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n if (s_merged != nullptr) {\n s_merged[pos * num_heads + head_idx] = S[pos * num_heads + head_idx];\n }\n return;\n }\n\n vec_t<float, vec_size> v_merged_vec;\n state_t<vec_size> st;\n v_merged_vec.fill(0.f);\n#pragma unroll 2\n for (uint32_t iter = 0; iter < num_index_sets; ++iter) {\n float s = S[(pos * num_index_sets + iter) * num_heads + head_idx];\n vec_t<float, vec_size> v;\n v.cast_load(V + ((pos * num_index_sets + iter) * num_heads + head_idx) * head_dim +\n tx * vec_size);\n st.merge(v, s, 1);\n }\n\n st.normalize();\n st.o.cast_store(v_merged + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n if (s_merged != nullptr) {\n s_merged[pos * num_heads + head_idx] = st.get_lse();\n }\n}\n\n/*!\n * \\brief The CUDA kernel that merges self-attention states of a list of index sets,\n * accelerated for larget number of index sets.\n * \\tparam vec_size The vector size used in the kernel.\n * \\tparam bdx The blockDim.x used in the kernel.\n * \\tparam bdy The blockDim.y used in the kernel.\n * \\tparam num_smem_stages The number of stages of shared memory used in the kernel.\n * \\tparam DTypeIn The data type of v.\n * \\tparam DTypeOut The data type of v_merged.\n * \\param V The partial v of index sets. (n, num_index_sets, h, d)\n * \\param S The logsumexp value of index sets. (n, num_index_sets, h)\n * \\param v_merged The merged v of index sets union. (n, h, d)\n * \\param s_merged The merged logsumexp value of index sets union. (n, h)\n * \\param num_heads The number of heads of v.\n * \\param head_dim The dimension of each head.\n * \\note s are logsumexp values with base 2.\n */\ntemplate <uint32_t vec_size, uint32_t bdx, uint32_t bdy, uint32_t num_smem_stages, typename DTypeIn,\n typename DTypeOut>\n__global__ void MergeStatesLargeNumIndexSetsKernel(DTypeIn* __restrict__ V, float* __restrict__ S,\n DTypeOut* __restrict__ v_merged,\n float* __restrict__ s_merged,\n uint32_t num_index_sets, uint32_t num_heads) {\n uint32_t tx = threadIdx.x, ty = threadIdx.y;\n uint32_t pos = blockIdx.x;\n uint32_t head_idx = blockIdx.y;\n state_t<vec_size> st;\n constexpr uint32_t vec_bits = sizeof(DTypeIn) * vec_size * 8;\n constexpr uint32_t head_dim = vec_size * bdx;\n\n extern __shared__ uint8_t smem[];\n DTypeIn* v_smem = (DTypeIn*)smem;\n float* s_smem = (float*)(smem + num_smem_stages * bdy * head_dim * sizeof(DTypeIn));\n\n#pragma unroll\n for (uint32_t iter = 0; iter < num_smem_stages; ++iter) {\n cp_async::pred_load<vec_bits, PrefetchMode::kPrefetch, SharedMemFillMode::kNoFill>(\n v_smem + (iter * bdy + ty) * head_dim + tx * vec_size,\n V + ((pos * num_index_sets + (iter * bdy + ty)) * num_heads + head_idx) * head_dim +\n tx * vec_size,\n (iter * bdy + ty) < num_index_sets);\n cp_async::commit_group();\n }\n#pragma unroll 4\n for (uint32_t iter = 0; iter < ceil_div(num_index_sets, bdy); ++iter) {\n if (iter % bdx == 0) {\n s_smem[ty * bdx + tx] =\n iter * bdy + (ty * bdx + tx) < num_index_sets\n ? S[(pos * num_index_sets + (iter * bdy + ty * bdx + tx)) * num_heads + head_idx]\n : 0.f;\n __syncthreads();\n }\n cp_async::wait_group<num_smem_stages - 1>();\n __syncthreads();\n vec_t<float, vec_size> v;\n v.cast_load(v_smem + ((iter % num_smem_stages) * bdy + ty) * head_dim + tx * vec_size);\n if (iter * bdy + ty < num_index_sets) {\n float s = s_smem[(iter % bdx) * bdy + ty];\n st.merge(v, s, 1);\n }\n __syncthreads();\n cp_async::pred_load<vec_bits, PrefetchMode::kPrefetch, SharedMemFillMode::kNoFill>(\n v_smem + ((iter % num_smem_stages) * bdy + ty) * head_dim + tx * vec_size,\n V +\n ((pos * num_index_sets + ((iter + num_smem_stages) * bdy + ty)) * num_heads +\n head_idx) *\n head_dim +\n tx * vec_size,\n (iter + num_smem_stages) * bdy + ty < num_index_sets);\n cp_async::commit_group();\n }\n cp_async::wait_group<0>();\n __syncthreads();\n\n st.normalize();\n threadblock_sync_state<bdx, bdy, vec_size>(st, v_smem, s_smem);\n st.normalize();\n\n st.o.cast_store(v_merged + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n if (s_merged != nullptr) {\n s_merged[pos * num_heads + head_idx] = st.get_lse();\n }\n}\n\n/*!\n * \\brief The CUDA kernel to merge self-attention states of multiple index sets, the number of index\n * sets at each position might vary.\n * \\tparam vec_size The vector size used in the kernel.\n * \\tparam bdx The blockDim.x used in the kernel.\n * \\tparam bdy The blockDim.y used in the kernel.\n * \\tparam num_smem_stages The number of stages of shared memory used in the kernel.\n * \\tparam DTypeIn The data type of v.\n * \\tparam DTypeOut The data type of v_merged.\n * \\param V The partial v of index sets. (nnz, h, d)\n * \\param S The logsumexp value of index sets. (nnz, h)\n * \\param indptr The start offsets of each position in the variable length array.\n * \\param v_merged The merged v of index sets union. (n, h, d)\n * \\param s_merged The merged logsumexp value of index sets union. (n, h)\n * \\param num_heads The number of heads of v.\n * \\param head_dim The dimension of each head.\n * \\note s are logsumexp values with base 2.\n */\ntemplate <uint32_t vec_size, uint32_t bdx, uint32_t bdy, uint32_t num_smem_stages, typename DTypeIn,\n typename DTypeOut, typename IdType>\n__global__ void VariableLengthMergeStatesKernel(DTypeIn* __restrict__ V, float* __restrict__ S,\n IdType* indptr, DTypeOut* __restrict__ v_merged,\n float* __restrict__ s_merged, uint32_t num_heads) {\n uint32_t tx = threadIdx.x, ty = threadIdx.y;\n uint32_t pos = blockIdx.x;\n uint32_t head_idx = blockIdx.y;\n state_t<vec_size> st;\n constexpr uint32_t vec_bits = sizeof(DTypeIn) * vec_size * 8;\n constexpr uint32_t head_dim = vec_size * bdx;\n\n extern __shared__ uint8_t smem[];\n DTypeIn* v_smem = (DTypeIn*)smem;\n float* s_smem = (float*)(smem + num_smem_stages * bdy * head_dim * sizeof(DTypeIn));\n const uint32_t num_index_sets = indptr[pos + 1] - indptr[pos];\n\n if (num_index_sets == 0) {\n vec_t<DTypeOut, vec_size> v;\n v.fill(DTypeOut(0));\n v.store(v_merged + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n if (s_merged != nullptr) {\n s_merged[pos * num_heads + head_idx] = -5e4;\n }\n return;\n }\n\n if (num_index_sets == 1) {\n vec_t<DTypeOut, vec_size> v;\n v.cast_load(V + (indptr[pos] * num_heads + head_idx) * head_dim + tx * vec_size);\n v.store(v_merged + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n if (s_merged != nullptr) {\n s_merged[pos * num_heads + head_idx] = S[indptr[pos] * num_heads + head_idx];\n }\n }\n\n#pragma unroll\n for (uint32_t iter = 0; iter < num_smem_stages; ++iter) {\n cp_async::pred_load<vec_bits, PrefetchMode::kPrefetch, SharedMemFillMode::kNoFill>(\n v_smem + (iter * bdy + ty) * head_dim + tx * vec_size,\n V + ((indptr[pos] + (iter * bdy + ty)) * num_heads + head_idx) * head_dim + tx * vec_size,\n (iter * bdy + ty) < num_index_sets);\n cp_async::commit_group();\n }\n#pragma unroll 4\n for (uint32_t iter = 0; iter < ceil_div(num_index_sets, bdy); ++iter) {\n if (iter % bdx == 0) {\n s_smem[ty * bdx + tx] =\n iter * bdy + (ty * bdx + tx) < num_index_sets\n ? S[(indptr[pos] + (iter * bdy + ty * bdx + tx)) * num_heads + head_idx]\n : 0.f;\n __syncthreads();\n }\n cp_async::wait_group<num_smem_stages - 1>();\n __syncthreads();\n vec_t<float, vec_size> v;\n v.cast_load(v_smem + ((iter % num_smem_stages) * bdy + ty) * head_dim + tx * vec_size);\n if (iter * bdy + ty < num_index_sets) {\n float s = s_smem[(iter % bdx) * bdy + ty];\n st.merge(v, s, 1);\n }\n __syncthreads();\n cp_async::pred_load<vec_bits, PrefetchMode::kPrefetch, SharedMemFillMode::kNoFill>(\n v_smem + ((iter % num_smem_stages) * bdy + ty) * head_dim + tx * vec_size,\n V +\n ((indptr[pos] + ((iter + num_smem_stages) * bdy + ty)) * num_heads + head_idx) *\n head_dim +\n tx * vec_size,\n (iter + num_smem_stages) * bdy + ty < num_index_sets);\n cp_async::commit_group();\n }\n cp_async::wait_group<0>();\n __syncthreads();\n\n st.normalize();\n threadblock_sync_state<bdx, bdy, vec_size>(st, v_smem, s_smem);\n st.normalize();\n\n st.o.cast_store(v_merged + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n if (s_merged != nullptr) {\n s_merged[pos * num_heads + head_idx] = st.get_lse();\n }\n}\n\n/*!\n * \\brief Merge the self-attention state of two index sets A and B.\n * \\tparam DTypeIn The data type of v_a and v_b.\n * \\tparam DTypeOut The data type of v_merged.\n * \\param v_a The partial v of index set A (n, h, d)\n * \\param s_a The logsumexp value of index set A. (n, h)\n * \\param v_b The partial v of index set B. (n, h, d)\n * \\param s_b The logsumexp value of index set B. (n, h)\n * \\param v_merged The merged v of index set A union B. (n, h, d)\n * \\param s_merged The merged logsumexp value of index set A union B. (n, h)\n * \\param seq_len The sequence length.\n * \\param num_heads The number of heads of v_a and v_b.\n * \\param head_dim The dimension of each head.\n * \\param stream The CUDA stream to execute the kernel.\n * \\return status Indicates whether CUDA calls are successful\n * \\note Both s_a and s_b are logsumexp values with base 2.\n */\ntemplate <typename DTypeIn, typename DTypeOut>\ncudaError_t MergeState(DTypeIn* v_a, float* s_a, DTypeIn* v_b, float* s_b, DTypeOut* v_merged,\n float* s_merged, uint32_t seq_len, uint32_t num_heads, uint32_t head_dim,\n cudaStream_t stream = nullptr) {\n DISPATCH_HEAD_DIM(head_dim, HEAD_DIM, {\n constexpr uint32_t vec_size = std::max(16U / sizeof(DTypeIn), HEAD_DIM / 32U);\n uint32_t bdx = HEAD_DIM / vec_size;\n uint32_t bdy = num_heads;\n dim3 nblks(seq_len);\n dim3 nthrs(bdx, bdy);\n auto kernel = MergeStateKernel<vec_size, DTypeIn, DTypeOut>;\n void* args[] = {&v_a, &s_a, &v_b, &s_b, &v_merged, &s_merged, &num_heads, &head_dim};\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)kernel, nblks, nthrs, args, 0, stream));\n });\n return cudaSuccess;\n}\n\n/*!\n * \\brief Merge the self-attention state with another state in place.\n * \\tparam DType The data type of v and v_other.\n * \\param v The partial v to be updated in-place. (n, h, d)\n * \\param s The logsumexp value to be updated in-place. (n, h)\n * \\param v_other The other v to be merged. (n, h, d)\n * \\param s_other The other logsumexp value to be merged. (n, h)\n * \\param seq_len The sequence length.\n * \\param num_heads The number of heads of v and v_other.\n * \\param head_dim The dimension of each head.\n * \\param mask Optional mask of whether to merge given sequences or not. (n)\n * \\param stream The CUDA stream to execute the kernel.\n * \\return status Indicates whether CUDA calls are successful\n * \\note Both s and s_other are logsumexp values with base 2.\n */\ntemplate <typename DType>\ncudaError_t MergeStateInPlace(DType* v, float* s, DType* v_other, float* s_other, uint32_t seq_len,\n uint32_t num_heads, uint32_t head_dim, uint8_t* mask = nullptr,\n cudaStream_t stream = nullptr) {\n DISPATCH_HEAD_DIM(head_dim, HEAD_DIM, {\n constexpr uint32_t vec_size = std::max(16U / sizeof(DType), HEAD_DIM / 32U);\n uint32_t bdx = HEAD_DIM / vec_size;\n uint32_t bdy = num_heads;\n dim3 nblks(seq_len);\n dim3 nthrs(bdx, bdy);\n auto kernel = MergeStateInPlaceKernel<vec_size, DType>;\n void* args[] = {&v, &s, &v_other, &s_other, &mask, &num_heads, &head_dim};\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)kernel, nblks, nthrs, args, 0, stream));\n });\n return cudaSuccess;\n}\n\n/*!\n * \\brief Merge self-attention states of a list of index sets.\n * \\tparam DTypeIn The data type of v.\n * \\tparam DTypeOut The data type of v_merged.\n * \\param v The partial v of index sets. (n, num_index_sets, h, d)\n * \\param s The logsumexp value of index sets. (n, num_index_sets, h)\n * \\param v_merged The merged v of index sets union. (n, h, d)\n * \\param s_merged The merged logsumexp value of index sets union. (n, h)\n * \\param num_index_sets The number of index sets.\n * \\param seq_len The sequence length.\n * \\param num_heads The number of heads of v.\n * \\param head_dim The dimension of each head.\n * \\param stream The CUDA stream to execute the kernel.\n * \\return status Indicates whether CUDA calls are successful\n * \\note s are logsumexp values with base 2.\n */\ntemplate <typename DTypeIn, typename DTypeOut>\ncudaError_t MergeStates(DTypeIn* v, float* s, DTypeOut* v_merged, float* s_merged,\n uint32_t num_index_sets, uint32_t seq_len, uint32_t num_heads,\n uint32_t head_dim, cudaStream_t stream = nullptr) {\n DISPATCH_HEAD_DIM(head_dim, HEAD_DIM, {\n constexpr uint32_t vec_size = std::max(16U / sizeof(DTypeIn), HEAD_DIM / 32U);\n constexpr uint32_t bdx = HEAD_DIM / vec_size;\n if (num_index_sets >= seq_len) {\n constexpr uint32_t num_threads = 128;\n constexpr uint32_t bdy = num_threads / bdx;\n dim3 nblks(seq_len, num_heads);\n dim3 nthrs(bdx, bdy);\n constexpr uint32_t num_smem_stages = 4;\n auto kernel = MergeStatesLargeNumIndexSetsKernel<vec_size, bdx, bdy, num_smem_stages, DTypeIn,\n DTypeOut>;\n void* args[] = {&v, &s, &v_merged, &s_merged, &num_index_sets, &num_heads};\n uint32_t smem_size =\n num_smem_stages * bdy * head_dim * sizeof(DTypeIn) + num_threads * sizeof(float);\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n } else {\n uint32_t bdy = num_heads;\n dim3 nblks(seq_len);\n dim3 nthrs(bdx, bdy);\n auto kernel = MergeStatesKernel<vec_size, DTypeIn, DTypeOut>;\n void* args[] = {&v, &s, &v_merged, &s_merged, &num_index_sets, &num_heads, &head_dim};\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)kernel, nblks, nthrs, args, 0, stream));\n }\n });\n return cudaSuccess;\n}\n\ntemplate <typename DTypeIn, typename DTypeOut, typename IdType>\ncudaError_t VariableLengthMergeStates(DTypeIn* v, float* s, IdType* indptr, DTypeOut* v_merged,\n float* s_merged, uint32_t seq_len, uint32_t num_heads,\n uint32_t head_dim, cudaStream_t stream = nullptr) {\n DISPATCH_HEAD_DIM(head_dim, HEAD_DIM, {\n constexpr uint32_t vec_size = std::max(16U / sizeof(DTypeIn), HEAD_DIM / 32U);\n constexpr uint32_t bdx = HEAD_DIM / vec_size;\n constexpr uint32_t num_threads = 128;\n constexpr uint32_t bdy = num_threads / bdx;\n dim3 nblks(seq_len, num_heads);\n dim3 nthrs(bdx, bdy);\n constexpr uint32_t num_smem_stages = 4;\n auto kernel = VariableLengthMergeStatesKernel<vec_size, bdx, bdy, num_smem_stages, DTypeIn,\n DTypeOut, IdType>;\n void* args[] = {&v, &s, &indptr, &v_merged, &s_merged, &num_heads};\n uint32_t smem_size =\n num_smem_stages * bdy * head_dim * sizeof(DTypeIn) + num_threads * sizeof(float);\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n });\n return cudaSuccess;\n}\n\n} // namespace flashinfer\n\n#endif // FLASHINFER_CASCADE_CUH_\n"},"after_code":{"kind":"string","value":"/*!\n * Copyright (c) 2023 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_CASCADE_CUH_\n#define FLASHINFER_CASCADE_CUH_\n\n#include <cooperative_groups.h>\n\n#include \"../cp_async.cuh\"\n#include \"../math.cuh\"\n#include \"../utils.cuh\"\n#include \"state.cuh\"\n\nnamespace flashinfer {\n\nnamespace cg = cooperative_groups;\nusing cp_async::PrefetchMode;\nusing cp_async::SharedMemFillMode;\n\n/*!\n * \\brief The CUDA kernel that merges the self-attention state of two index sets A and B.\n * \\tparam vec_size The vector size used in the kernel.\n * \\tparam DTypeIn The data type of v_a and v_b.\n * \\tparam DTypeOut The data type of v_merged.\n * \\param v_a The partial v of index set A. (n, h, d)\n * \\param s_a The logsumexp value of index set A. (n, h)\n * \\param v_b The partial v of index set B. (n, h, d)\n * \\param s_b The logsumexp value of index set B. (n, h)\n * \\param v_merged The merged v of index set A union B. (n, h, d)\n * \\param s_merged The merged logsumexp value of index set A union B. (n, h)\n * \\param num_heads The number of heads of v_a and v_b.\n * \\param head_dim The dimension of each head.\n * \\note Both s_a and s_b are logsumexp values with base 2.\n */\ntemplate <uint32_t vec_size, typename DTypeIn, typename DTypeOut>\n__global__ void MergeStateKernel(DTypeIn* __restrict__ v_a, float* __restrict__ s_a,\n DTypeIn* __restrict__ v_b, float* __restrict__ s_b,\n DTypeOut* __restrict__ v_merged, float* __restrict__ s_merged,\n uint32_t num_heads, uint32_t head_dim) {\n uint32_t tx = threadIdx.x, ty = threadIdx.y;\n uint32_t pos = blockIdx.x;\n uint32_t head_idx = ty;\n\n float s_a_val = s_a[pos * num_heads + head_idx];\n float s_b_val = s_b[pos * num_heads + head_idx];\n float s_max = max(s_a_val, s_b_val);\n s_a_val = math::ptx_exp2(s_a_val - s_max);\n s_b_val = math::ptx_exp2(s_b_val - s_max);\n float a_scale = s_a_val / (s_a_val + s_b_val);\n float b_scale = s_b_val / (s_a_val + s_b_val);\n vec_t<float, vec_size> v_a_vec, v_b_vec, v_merged_vec;\n v_a_vec.cast_load(v_a + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n v_b_vec.cast_load(v_b + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n#pragma unroll\n for (uint32_t i = 0; i < vec_size; ++i) {\n v_merged_vec[i] = a_scale * v_a_vec[i] + b_scale * v_b_vec[i];\n }\n v_merged_vec.cast_store(v_merged + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n if (s_merged != nullptr) {\n s_merged[pos * num_heads + head_idx] = math::ptx_log2(s_a_val + s_b_val) + s_max;\n }\n}\n\n/*!\n * \\brief The CUDA kernel that merges the self-attention state with another state in-place.\n * \\tparam vec_size The vector size used in the kernel.\n * \\tparam DType The data type of v and v_other.\n * \\param v The partial v to be updated in-place. (n, h, d)\n * \\param s The logsumexp value to be updated in-place. (n, h)\n * \\param v_other The other v to be merged. (n, h, d)\n * \\param s_other The other logsumexp value to be merged. (n, h)\n * \\param mask Optional mask of whether to merge given sequences or not. (n)\n * \\param num_heads The number of heads of v and v_other.\n * \\param head_dim The dimension of each head.\n * \\note Both s and s_other are logsumexp values with base 2.\n */\ntemplate <uint32_t vec_size, typename DType>\n__global__ void MergeStateInPlaceKernel(DType* __restrict__ v, float* __restrict__ s,\n DType* __restrict__ v_other, float* __restrict__ s_other,\n uint8_t* __restrict__ mask, uint32_t num_heads,\n uint32_t head_dim) {\n uint32_t pos = blockIdx.x;\n\n if (mask != nullptr && mask[pos] == 0) return;\n\n uint32_t tx = threadIdx.x, ty = threadIdx.y;\n uint32_t head_idx = ty;\n\n float s_val = s[pos * num_heads + head_idx];\n float s_other_val = s_other[pos * num_heads + head_idx];\n float s_max = max(s_val, s_other_val);\n s_val = math::ptx_exp2(s_val - s_max);\n s_other_val = math::ptx_exp2(s_other_val - s_max);\n float scale = s_val / (s_val + s_other_val);\n float other_scale = s_other_val / (s_val + s_other_val);\n vec_t<float, vec_size> v_vec, v_other_vec;\n v_vec.cast_load(v + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n v_other_vec.cast_load(v_other + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n#pragma unroll\n for (uint32_t i = 0; i < vec_size; ++i) {\n v_vec[i] = scale * v_vec[i] + other_scale * v_other_vec[i];\n }\n v_vec.cast_store(v + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n if (s != nullptr) {\n s[pos * num_heads + head_idx] = math::ptx_log2(s_val + s_other_val) + s_max;\n }\n}\n\ntemplate <uint32_t bdx, uint32_t bdy, uint32_t vec_size, typename DTypeIn>\n__device__ __forceinline__ void threadblock_sync_state(state_t<vec_size>& st, DTypeIn* v_smem,\n float* s_smem) {\n const uint32_t tx = threadIdx.x, ty = threadIdx.y;\n constexpr uint32_t head_dim = vec_size * bdx;\n st.o.cast_store(v_smem + ty * head_dim + tx * vec_size);\n s_smem[ty] = st.get_lse();\n st.init();\n __syncthreads();\n\n#pragma unroll\n for (uint32_t iter = 0; iter < bdy; ++iter) {\n float s = s_smem[iter];\n vec_t<float, vec_size> v;\n v.cast_load(v_smem + iter * head_dim + tx * vec_size);\n st.merge(v, s, 1);\n }\n}\n\n/*!\n * \\brief The CUDA kernel that merges self-attention states of a list of index sets.\n * \\param vec_size The vector size used in the kernel.\n * \\tparam DTypeIn The data type of v.\n * \\tparam DTypeOut The data type of v_merged.\n * \\param v The partial v of index sets. (n, num_index_sets, h, d)\n * \\param s The logsumexp value of index sets. (n, num_index_sets, h)\n * \\param v_merged The merged v of index sets union. (n, h, d)\n * \\param s_merged The merged logsumexp value of index sets union. (n, h)\n * \\param num_heads The number of heads of v.\n * \\param head_dim The dimension of each head.\n * \\note s are logsumexp values with base 2.\n */\ntemplate <uint32_t vec_size, typename DTypeIn, typename DTypeOut>\n__global__ void MergeStatesKernel(DTypeIn* __restrict__ V, float* __restrict__ S,\n DTypeOut* __restrict__ v_merged, float* __restrict__ s_merged,\n uint32_t num_index_sets, uint32_t num_heads, uint32_t head_dim) {\n uint32_t tx = threadIdx.x, ty = threadIdx.y;\n uint32_t pos = blockIdx.x;\n uint32_t head_idx = ty;\n\n if (num_index_sets == 0) {\n vec_t<DTypeOut, vec_size> v;\n v.fill(DTypeOut(0));\n v.store(v_merged + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n if (s_merged != nullptr) {\n s_merged[pos * num_heads + head_idx] = -5e4;\n }\n return;\n }\n\n if (num_index_sets == 1) {\n vec_t<DTypeOut, vec_size> v;\n v.cast_load(V + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n v.store(v_merged + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n if (s_merged != nullptr) {\n s_merged[pos * num_heads + head_idx] = S[pos * num_heads + head_idx];\n }\n return;\n }\n\n vec_t<float, vec_size> v_merged_vec;\n state_t<vec_size> st;\n v_merged_vec.fill(0.f);\n#pragma unroll 2\n for (uint32_t iter = 0; iter < num_index_sets; ++iter) {\n float s = S[(pos * num_index_sets + iter) * num_heads + head_idx];\n vec_t<float, vec_size> v;\n v.cast_load(V + ((pos * num_index_sets + iter) * num_heads + head_idx) * head_dim +\n tx * vec_size);\n st.merge(v, s, 1);\n }\n\n st.normalize();\n st.o.cast_store(v_merged + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n if (s_merged != nullptr) {\n s_merged[pos * num_heads + head_idx] = st.get_lse();\n }\n}\n\n/*!\n * \\brief The CUDA kernel that merges self-attention states of a list of index sets,\n * accelerated for larget number of index sets.\n * \\tparam vec_size The vector size used in the kernel.\n * \\tparam bdx The blockDim.x used in the kernel.\n * \\tparam bdy The blockDim.y used in the kernel.\n * \\tparam num_smem_stages The number of stages of shared memory used in the kernel.\n * \\tparam DTypeIn The data type of v.\n * \\tparam DTypeOut The data type of v_merged.\n * \\param V The partial v of index sets. (n, num_index_sets, h, d)\n * \\param S The logsumexp value of index sets. (n, num_index_sets, h)\n * \\param v_merged The merged v of index sets union. (n, h, d)\n * \\param s_merged The merged logsumexp value of index sets union. (n, h)\n * \\param num_heads The number of heads of v.\n * \\param head_dim The dimension of each head.\n * \\note s are logsumexp values with base 2.\n */\ntemplate <uint32_t vec_size, uint32_t bdx, uint32_t bdy, uint32_t num_smem_stages, typename DTypeIn,\n typename DTypeOut>\n__global__ void MergeStatesLargeNumIndexSetsKernel(DTypeIn* __restrict__ V, float* __restrict__ S,\n DTypeOut* __restrict__ v_merged,\n float* __restrict__ s_merged,\n uint32_t num_index_sets, uint32_t num_heads) {\n uint32_t tx = threadIdx.x, ty = threadIdx.y;\n uint32_t pos = blockIdx.x;\n uint32_t head_idx = blockIdx.y;\n state_t<vec_size> st;\n constexpr uint32_t vec_bits = sizeof(DTypeIn) * vec_size * 8;\n constexpr uint32_t head_dim = vec_size * bdx;\n\n extern __shared__ uint8_t smem[];\n DTypeIn* v_smem = (DTypeIn*)smem;\n float* s_smem = (float*)(smem + num_smem_stages * bdy * head_dim * sizeof(DTypeIn));\n\n#pragma unroll\n for (uint32_t iter = 0; iter < num_smem_stages; ++iter) {\n cp_async::pred_load<vec_bits, PrefetchMode::kPrefetch, SharedMemFillMode::kNoFill>(\n v_smem + (iter * bdy + ty) * head_dim + tx * vec_size,\n V + ((pos * num_index_sets + (iter * bdy + ty)) * num_heads + head_idx) * head_dim +\n tx * vec_size,\n (iter * bdy + ty) < num_index_sets);\n cp_async::commit_group();\n }\n#pragma unroll 4\n for (uint32_t iter = 0; iter < ceil_div(num_index_sets, bdy); ++iter) {\n if (iter % bdx == 0) {\n s_smem[ty * bdx + tx] =\n iter * bdy + (ty * bdx + tx) < num_index_sets\n ? S[(pos * num_index_sets + (iter * bdy + ty * bdx + tx)) * num_heads + head_idx]\n : 0.f;\n __syncthreads();\n }\n cp_async::wait_group<num_smem_stages - 1>();\n __syncthreads();\n vec_t<float, vec_size> v;\n v.cast_load(v_smem + ((iter % num_smem_stages) * bdy + ty) * head_dim + tx * vec_size);\n if (iter * bdy + ty < num_index_sets) {\n float s = s_smem[(iter % bdx) * bdy + ty];\n st.merge(v, s, 1);\n }\n __syncthreads();\n cp_async::pred_load<vec_bits, PrefetchMode::kPrefetch, SharedMemFillMode::kNoFill>(\n v_smem + ((iter % num_smem_stages) * bdy + ty) * head_dim + tx * vec_size,\n V +\n ((pos * num_index_sets + ((iter + num_smem_stages) * bdy + ty)) * num_heads +\n head_idx) *\n head_dim +\n tx * vec_size,\n (iter + num_smem_stages) * bdy + ty < num_index_sets);\n cp_async::commit_group();\n }\n cp_async::wait_group<0>();\n __syncthreads();\n\n st.normalize();\n threadblock_sync_state<bdx, bdy, vec_size>(st, v_smem, s_smem);\n st.normalize();\n\n st.o.cast_store(v_merged + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n if (s_merged != nullptr) {\n s_merged[pos * num_heads + head_idx] = st.get_lse();\n }\n}\n\n/*!\n * \\brief The CUDA kernel to merge self-attention states of multiple index sets, the number of index\n * sets at each position might vary.\n * \\tparam vec_size The vector size used in the kernel.\n * \\tparam bdx The blockDim.x used in the kernel.\n * \\tparam bdy The blockDim.y used in the kernel.\n * \\tparam num_smem_stages The number of stages of shared memory used in the kernel.\n * \\tparam DTypeIn The data type of v.\n * \\tparam DTypeOut The data type of v_merged.\n * \\param V The partial v of index sets. (nnz, h, d)\n * \\param S The logsumexp value of index sets. (nnz, h)\n * \\param indptr The start offsets of each position in the variable length array.\n * \\param v_merged The merged v of index sets union. (n, h, d)\n * \\param s_merged The merged logsumexp value of index sets union. (n, h)\n * \\param num_heads The number of heads of v.\n * \\param head_dim The dimension of each head.\n * \\note s are logsumexp values with base 2.\n */\ntemplate <uint32_t vec_size, uint32_t bdx, uint32_t bdy, uint32_t num_smem_stages, typename DTypeIn,\n typename DTypeOut, typename IdType>\n__global__ void PersistentVariableLengthMergeStatesKernel(DTypeIn* __restrict__ V,\n float* __restrict__ S, IdType* indptr,\n DTypeOut* __restrict__ v_merged,\n float* __restrict__ s_merged,\n uint32_t seq_len, uint32_t num_heads) {\n uint32_t tx = threadIdx.x, ty = threadIdx.y;\n uint32_t cta_id = blockIdx.x;\n uint32_t num_ctas = gridDim.x;\n uint32_t num_iters = ceil_div(seq_len * num_heads, num_ctas);\n constexpr uint32_t vec_bits = sizeof(DTypeIn) * vec_size * 8;\n constexpr uint32_t head_dim = vec_size * bdx;\n extern __shared__ uint8_t smem[];\n DTypeIn* v_smem = (DTypeIn*)smem;\n float* s_smem = (float*)(smem + num_smem_stages * bdy * head_dim * sizeof(DTypeIn));\n\n#pragma unroll 1\n for (uint32_t i = cta_id; i < seq_len * num_heads; i += num_ctas) {\n uint32_t pos = i / num_heads;\n uint32_t head_idx = i % num_heads;\n state_t<vec_size> st;\n const uint32_t num_index_sets = indptr[pos + 1] - indptr[pos];\n\n if (num_index_sets == 0) {\n vec_t<DTypeOut, vec_size> v;\n v.fill(DTypeOut(0));\n v.store(v_merged + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n if (s_merged != nullptr) {\n s_merged[pos * num_heads + head_idx] = -5e4;\n }\n continue;\n }\n\n if (num_index_sets == 1) {\n vec_t<DTypeOut, vec_size> v;\n v.cast_load(V + (indptr[pos] * num_heads + head_idx) * head_dim + tx * vec_size);\n v.store(v_merged + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n if (s_merged != nullptr) {\n s_merged[pos * num_heads + head_idx] = S[indptr[pos] * num_heads + head_idx];\n }\n continue;\n }\n\n#pragma unroll\n for (uint32_t iter = 0; iter < num_smem_stages; ++iter) {\n cp_async::pred_load<vec_bits, PrefetchMode::kPrefetch, SharedMemFillMode::kNoFill>(\n v_smem + (iter * bdy + ty) * head_dim + tx * vec_size,\n V + ((indptr[pos] + (iter * bdy + ty)) * num_heads + head_idx) * head_dim + tx * vec_size,\n (iter * bdy + ty) < num_index_sets);\n cp_async::commit_group();\n }\n#pragma unroll 4\n for (uint32_t iter = 0; iter < ceil_div(num_index_sets, bdy); ++iter) {\n if (iter % bdx == 0) {\n s_smem[ty * bdx + tx] =\n iter * bdy + (ty * bdx + tx) < num_index_sets\n ? S[(indptr[pos] + (iter * bdy + ty * bdx + tx)) * num_heads + head_idx]\n : 0.f;\n __syncthreads();\n }\n cp_async::wait_group<num_smem_stages - 1>();\n __syncthreads();\n vec_t<float, vec_size> v;\n v.cast_load(v_smem + ((iter % num_smem_stages) * bdy + ty) * head_dim + tx * vec_size);\n if (iter * bdy + ty < num_index_sets) {\n float s = s_smem[(iter % bdx) * bdy + ty];\n st.merge(v, s, 1);\n }\n __syncthreads();\n cp_async::pred_load<vec_bits, PrefetchMode::kPrefetch, SharedMemFillMode::kNoFill>(\n v_smem + ((iter % num_smem_stages) * bdy + ty) * head_dim + tx * vec_size,\n V +\n ((indptr[pos] + ((iter + num_smem_stages) * bdy + ty)) * num_heads + head_idx) *\n head_dim +\n tx * vec_size,\n (iter + num_smem_stages) * bdy + ty < num_index_sets);\n cp_async::commit_group();\n }\n cp_async::wait_group<0>();\n __syncthreads();\n\n st.normalize();\n threadblock_sync_state<bdx, bdy, vec_size>(st, v_smem, s_smem);\n st.normalize();\n\n st.o.cast_store(v_merged + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n if (s_merged != nullptr) {\n s_merged[pos * num_heads + head_idx] = st.get_lse();\n }\n }\n}\n\n/*!\n * \\brief Merge the self-attention state of two index sets A and B.\n * \\tparam DTypeIn The data type of v_a and v_b.\n * \\tparam DTypeOut The data type of v_merged.\n * \\param v_a The partial v of index set A (n, h, d)\n * \\param s_a The logsumexp value of index set A. (n, h)\n * \\param v_b The partial v of index set B. (n, h, d)\n * \\param s_b The logsumexp value of index set B. (n, h)\n * \\param v_merged The merged v of index set A union B. (n, h, d)\n * \\param s_merged The merged logsumexp value of index set A union B. (n, h)\n * \\param seq_len The sequence length.\n * \\param num_heads The number of heads of v_a and v_b.\n * \\param head_dim The dimension of each head.\n * \\param stream The CUDA stream to execute the kernel.\n * \\return status Indicates whether CUDA calls are successful\n * \\note Both s_a and s_b are logsumexp values with base 2.\n */\ntemplate <typename DTypeIn, typename DTypeOut>\ncudaError_t MergeState(DTypeIn* v_a, float* s_a, DTypeIn* v_b, float* s_b, DTypeOut* v_merged,\n float* s_merged, uint32_t seq_len, uint32_t num_heads, uint32_t head_dim,\n cudaStream_t stream = nullptr) {\n DISPATCH_HEAD_DIM(head_dim, HEAD_DIM, {\n constexpr uint32_t vec_size = std::max(16U / sizeof(DTypeIn), HEAD_DIM / 32U);\n uint32_t bdx = HEAD_DIM / vec_size;\n uint32_t bdy = num_heads;\n dim3 nblks(seq_len);\n dim3 nthrs(bdx, bdy);\n auto kernel = MergeStateKernel<vec_size, DTypeIn, DTypeOut>;\n void* args[] = {&v_a, &s_a, &v_b, &s_b, &v_merged, &s_merged, &num_heads, &head_dim};\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)kernel, nblks, nthrs, args, 0, stream));\n });\n return cudaSuccess;\n}\n\n/*!\n * \\brief Merge the self-attention state with another state in place.\n * \\tparam DType The data type of v and v_other.\n * \\param v The partial v to be updated in-place. (n, h, d)\n * \\param s The logsumexp value to be updated in-place. (n, h)\n * \\param v_other The other v to be merged. (n, h, d)\n * \\param s_other The other logsumexp value to be merged. (n, h)\n * \\param seq_len The sequence length.\n * \\param num_heads The number of heads of v and v_other.\n * \\param head_dim The dimension of each head.\n * \\param mask Optional mask of whether to merge given sequences or not. (n)\n * \\param stream The CUDA stream to execute the kernel.\n * \\return status Indicates whether CUDA calls are successful\n * \\note Both s and s_other are logsumexp values with base 2.\n */\ntemplate <typename DType>\ncudaError_t MergeStateInPlace(DType* v, float* s, DType* v_other, float* s_other, uint32_t seq_len,\n uint32_t num_heads, uint32_t head_dim, uint8_t* mask = nullptr,\n cudaStream_t stream = nullptr) {\n DISPATCH_HEAD_DIM(head_dim, HEAD_DIM, {\n constexpr uint32_t vec_size = std::max(16U / sizeof(DType), HEAD_DIM / 32U);\n uint32_t bdx = HEAD_DIM / vec_size;\n uint32_t bdy = num_heads;\n dim3 nblks(seq_len);\n dim3 nthrs(bdx, bdy);\n auto kernel = MergeStateInPlaceKernel<vec_size, DType>;\n void* args[] = {&v, &s, &v_other, &s_other, &mask, &num_heads, &head_dim};\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)kernel, nblks, nthrs, args, 0, stream));\n });\n return cudaSuccess;\n}\n\n/*!\n * \\brief Merge self-attention states of a list of index sets.\n * \\tparam DTypeIn The data type of v.\n * \\tparam DTypeOut The data type of v_merged.\n * \\param v The partial v of index sets. (n, num_index_sets, h, d)\n * \\param s The logsumexp value of index sets. (n, num_index_sets, h)\n * \\param v_merged The merged v of index sets union. (n, h, d)\n * \\param s_merged The merged logsumexp value of index sets union. (n, h)\n * \\param num_index_sets The number of index sets.\n * \\param seq_len The sequence length.\n * \\param num_heads The number of heads of v.\n * \\param head_dim The dimension of each head.\n * \\param stream The CUDA stream to execute the kernel.\n * \\return status Indicates whether CUDA calls are successful\n * \\note s are logsumexp values with base 2.\n */\ntemplate <typename DTypeIn, typename DTypeOut>\ncudaError_t MergeStates(DTypeIn* v, float* s, DTypeOut* v_merged, float* s_merged,\n uint32_t num_index_sets, uint32_t seq_len, uint32_t num_heads,\n uint32_t head_dim, cudaStream_t stream = nullptr) {\n DISPATCH_HEAD_DIM(head_dim, HEAD_DIM, {\n constexpr uint32_t vec_size = std::max(16U / sizeof(DTypeIn), HEAD_DIM / 32U);\n constexpr uint32_t bdx = HEAD_DIM / vec_size;\n if (num_index_sets >= seq_len) {\n constexpr uint32_t num_threads = 128;\n constexpr uint32_t bdy = num_threads / bdx;\n dim3 nblks(seq_len, num_heads);\n dim3 nthrs(bdx, bdy);\n constexpr uint32_t num_smem_stages = 4;\n auto kernel = MergeStatesLargeNumIndexSetsKernel<vec_size, bdx, bdy, num_smem_stages, DTypeIn,\n DTypeOut>;\n void* args[] = {&v, &s, &v_merged, &s_merged, &num_index_sets, &num_heads};\n uint32_t smem_size =\n num_smem_stages * bdy * head_dim * sizeof(DTypeIn) + num_threads * sizeof(float);\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n } else {\n uint32_t bdy = num_heads;\n dim3 nblks(seq_len);\n dim3 nthrs(bdx, bdy);\n auto kernel = MergeStatesKernel<vec_size, DTypeIn, DTypeOut>;\n void* args[] = {&v, &s, &v_merged, &s_merged, &num_index_sets, &num_heads, &head_dim};\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)kernel, nblks, nthrs, args, 0, stream));\n }\n });\n return cudaSuccess;\n}\n\ntemplate <typename DTypeIn, typename DTypeOut, typename IdType>\ncudaError_t VariableLengthMergeStates(DTypeIn* v, float* s, IdType* indptr, DTypeOut* v_merged,\n float* s_merged, uint32_t seq_len, uint32_t num_heads,\n uint32_t head_dim, cudaStream_t stream = nullptr) {\n int dev_id = 0;\n int num_sms = 0;\n int num_blocks_per_sm = 0;\n FLASHINFER_CUDA_CALL(cudaGetDevice(&dev_id));\n FLASHINFER_CUDA_CALL(cudaDeviceGetAttribute(&num_sms, cudaDevAttrMultiProcessorCount, dev_id));\n\n DISPATCH_HEAD_DIM(head_dim, HEAD_DIM, {\n constexpr uint32_t vec_size = std::max(16U / sizeof(DTypeIn), HEAD_DIM / 32U);\n constexpr uint32_t bdx = HEAD_DIM / vec_size;\n constexpr uint32_t num_threads = 128;\n constexpr uint32_t bdy = num_threads / bdx;\n constexpr uint32_t num_smem_stages = 4;\n uint32_t smem_size =\n num_smem_stages * bdy * head_dim * sizeof(DTypeIn) + num_threads * sizeof(float);\n auto kernel = PersistentVariableLengthMergeStatesKernel<vec_size, bdx, bdy, num_smem_stages,\n DTypeIn, DTypeOut, IdType>;\n FLASHINFER_CUDA_CALL(cudaOccupancyMaxActiveBlocksPerMultiprocessor(&num_blocks_per_sm, kernel,\n num_threads, smem_size));\n num_blocks_per_sm = min(num_blocks_per_sm, ceil_div(seq_len * num_heads, num_sms));\n\n dim3 nblks(num_sms * num_blocks_per_sm);\n dim3 nthrs(bdx, bdy);\n void* args[] = {&v, &s, &indptr, &v_merged, &s_merged, &seq_len, &num_heads};\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n });\n return cudaSuccess;\n}\n\n} // namespace flashinfer\n\n#endif // FLASHINFER_CASCADE_CUH_\n"},"diff":{"kind":"string","value":"--- include/flashinfer/attention/cascade.cuh\n+++ include/flashinfer/attention/cascade.cuh\n@@ -301,85 +301,94 @@\n */\n template <uint32_t vec_size, uint32_t bdx, uint32_t bdy, uint32_t num_smem_stages, typename DTypeIn,\n typename DTypeOut, typename IdType>\n-__global__ void VariableLengthMergeStatesKernel(DTypeIn* __restrict__ V, float* __restrict__ S,\n- IdType* indptr, DTypeOut* __restrict__ v_merged,\n- float* __restrict__ s_merged, uint32_t num_heads) {\n+__global__ void PersistentVariableLengthMergeStatesKernel(DTypeIn* __restrict__ V,\n+ float* __restrict__ S, IdType* indptr,\n+ DTypeOut* __restrict__ v_merged,\n+ float* __restrict__ s_merged,\n+ uint32_t seq_len, uint32_t num_heads) {\n uint32_t tx = threadIdx.x, ty = threadIdx.y;\n- uint32_t pos = blockIdx.x;\n- uint32_t head_idx = blockIdx.y;\n- state_t<vec_size> st;\n+ uint32_t cta_id = blockIdx.x;\n+ uint32_t num_ctas = gridDim.x;\n+ uint32_t num_iters = ceil_div(seq_len * num_heads, num_ctas);\n constexpr uint32_t vec_bits = sizeof(DTypeIn) * vec_size * 8;\n constexpr uint32_t head_dim = vec_size * bdx;\n-\n extern __shared__ uint8_t smem[];\n DTypeIn* v_smem = (DTypeIn*)smem;\n float* s_smem = (float*)(smem + num_smem_stages * bdy * head_dim * sizeof(DTypeIn));\n- const uint32_t num_index_sets = indptr[pos + 1] - indptr[pos];\n-\n- if (num_index_sets == 0) {\n- vec_t<DTypeOut, vec_size> v;\n- v.fill(DTypeOut(0));\n- v.store(v_merged + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n+\n+#pragma unroll 1\n+ for (uint32_t i = cta_id; i < seq_len * num_heads; i += num_ctas) {\n+ uint32_t pos = i / num_heads;\n+ uint32_t head_idx = i % num_heads;\n+ state_t<vec_size> st;\n+ const uint32_t num_index_sets = indptr[pos + 1] - indptr[pos];\n+\n+ if (num_index_sets == 0) {\n+ vec_t<DTypeOut, vec_size> v;\n+ v.fill(DTypeOut(0));\n+ v.store(v_merged + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n+ if (s_merged != nullptr) {\n+ s_merged[pos * num_heads + head_idx] = -5e4;\n+ }\n+ continue;\n+ }\n+\n+ if (num_index_sets == 1) {\n+ vec_t<DTypeOut, vec_size> v;\n+ v.cast_load(V + (indptr[pos] * num_heads + head_idx) * head_dim + tx * vec_size);\n+ v.store(v_merged + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n+ if (s_merged != nullptr) {\n+ s_merged[pos * num_heads + head_idx] = S[indptr[pos] * num_heads + head_idx];\n+ }\n+ continue;\n+ }\n+\n+#pragma unroll\n+ for (uint32_t iter = 0; iter < num_smem_stages; ++iter) {\n+ cp_async::pred_load<vec_bits, PrefetchMode::kPrefetch, SharedMemFillMode::kNoFill>(\n+ v_smem + (iter * bdy + ty) * head_dim + tx * vec_size,\n+ V + ((indptr[pos] + (iter * bdy + ty)) * num_heads + head_idx) * head_dim + tx * vec_size,\n+ (iter * bdy + ty) < num_index_sets);\n+ cp_async::commit_group();\n+ }\n+#pragma unroll 4\n+ for (uint32_t iter = 0; iter < ceil_div(num_index_sets, bdy); ++iter) {\n+ if (iter % bdx == 0) {\n+ s_smem[ty * bdx + tx] =\n+ iter * bdy + (ty * bdx + tx) < num_index_sets\n+ ? S[(indptr[pos] + (iter * bdy + ty * bdx + tx)) * num_heads + head_idx]\n+ : 0.f;\n+ __syncthreads();\n+ }\n+ cp_async::wait_group<num_smem_stages - 1>();\n+ __syncthreads();\n+ vec_t<float, vec_size> v;\n+ v.cast_load(v_smem + ((iter % num_smem_stages) * bdy + ty) * head_dim + tx * vec_size);\n+ if (iter * bdy + ty < num_index_sets) {\n+ float s = s_smem[(iter % bdx) * bdy + ty];\n+ st.merge(v, s, 1);\n+ }\n+ __syncthreads();\n+ cp_async::pred_load<vec_bits, PrefetchMode::kPrefetch, SharedMemFillMode::kNoFill>(\n+ v_smem + ((iter % num_smem_stages) * bdy + ty) * head_dim + tx * vec_size,\n+ V +\n+ ((indptr[pos] + ((iter + num_smem_stages) * bdy + ty)) * num_heads + head_idx) *\n+ head_dim +\n+ tx * vec_size,\n+ (iter + num_smem_stages) * bdy + ty < num_index_sets);\n+ cp_async::commit_group();\n+ }\n+ cp_async::wait_group<0>();\n+ __syncthreads();\n+\n+ st.normalize();\n+ threadblock_sync_state<bdx, bdy, vec_size>(st, v_smem, s_smem);\n+ st.normalize();\n+\n+ st.o.cast_store(v_merged + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n if (s_merged != nullptr) {\n- s_merged[pos * num_heads + head_idx] = -5e4;\n- }\n- return;\n- }\n-\n- if (num_index_sets == 1) {\n- vec_t<DTypeOut, vec_size> v;\n- v.cast_load(V + (indptr[pos] * num_heads + head_idx) * head_dim + tx * vec_size);\n- v.store(v_merged + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n- if (s_merged != nullptr) {\n- s_merged[pos * num_heads + head_idx] = S[indptr[pos] * num_heads + head_idx];\n- }\n- }\n-\n-#pragma unroll\n- for (uint32_t iter = 0; iter < num_smem_stages; ++iter) {\n- cp_async::pred_load<vec_bits, PrefetchMode::kPrefetch, SharedMemFillMode::kNoFill>(\n- v_smem + (iter * bdy + ty) * head_dim + tx * vec_size,\n- V + ((indptr[pos] + (iter * bdy + ty)) * num_heads + head_idx) * head_dim + tx * vec_size,\n- (iter * bdy + ty) < num_index_sets);\n- cp_async::commit_group();\n- }\n-#pragma unroll 4\n- for (uint32_t iter = 0; iter < ceil_div(num_index_sets, bdy); ++iter) {\n- if (iter % bdx == 0) {\n- s_smem[ty * bdx + tx] =\n- iter * bdy + (ty * bdx + tx) < num_index_sets\n- ? S[(indptr[pos] + (iter * bdy + ty * bdx + tx)) * num_heads + head_idx]\n- : 0.f;\n- __syncthreads();\n- }\n- cp_async::wait_group<num_smem_stages - 1>();\n- __syncthreads();\n- vec_t<float, vec_size> v;\n- v.cast_load(v_smem + ((iter % num_smem_stages) * bdy + ty) * head_dim + tx * vec_size);\n- if (iter * bdy + ty < num_index_sets) {\n- float s = s_smem[(iter % bdx) * bdy + ty];\n- st.merge(v, s, 1);\n- }\n- __syncthreads();\n- cp_async::pred_load<vec_bits, PrefetchMode::kPrefetch, SharedMemFillMode::kNoFill>(\n- v_smem + ((iter % num_smem_stages) * bdy + ty) * head_dim + tx * vec_size,\n- V +\n- ((indptr[pos] + ((iter + num_smem_stages) * bdy + ty)) * num_heads + head_idx) *\n- head_dim +\n- tx * vec_size,\n- (iter + num_smem_stages) * bdy + ty < num_index_sets);\n- cp_async::commit_group();\n- }\n- cp_async::wait_group<0>();\n- __syncthreads();\n-\n- st.normalize();\n- threadblock_sync_state<bdx, bdy, vec_size>(st, v_smem, s_smem);\n- st.normalize();\n-\n- st.o.cast_store(v_merged + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n- if (s_merged != nullptr) {\n- s_merged[pos * num_heads + head_idx] = st.get_lse();\n+ s_merged[pos * num_heads + head_idx] = st.get_lse();\n+ }\n }\n }\n \n@@ -502,19 +511,29 @@\n cudaError_t VariableLengthMergeStates(DTypeIn* v, float* s, IdType* indptr, DTypeOut* v_merged,\n float* s_merged, uint32_t seq_len, uint32_t num_heads,\n uint32_t head_dim, cudaStream_t stream = nullptr) {\n+ int dev_id = 0;\n+ int num_sms = 0;\n+ int num_blocks_per_sm = 0;\n+ FLASHINFER_CUDA_CALL(cudaGetDevice(&dev_id));\n+ FLASHINFER_CUDA_CALL(cudaDeviceGetAttribute(&num_sms, cudaDevAttrMultiProcessorCount, dev_id));\n+\n DISPATCH_HEAD_DIM(head_dim, HEAD_DIM, {\n constexpr uint32_t vec_size = std::max(16U / sizeof(DTypeIn), HEAD_DIM / 32U);\n constexpr uint32_t bdx = HEAD_DIM / vec_size;\n constexpr uint32_t num_threads = 128;\n constexpr uint32_t bdy = num_threads / bdx;\n- dim3 nblks(seq_len, num_heads);\n- dim3 nthrs(bdx, bdy);\n constexpr uint32_t num_smem_stages = 4;\n- auto kernel = VariableLengthMergeStatesKernel<vec_size, bdx, bdy, num_smem_stages, DTypeIn,\n- DTypeOut, IdType>;\n- void* args[] = {&v, &s, &indptr, &v_merged, &s_merged, &num_heads};\n uint32_t smem_size =\n num_smem_stages * bdy * head_dim * sizeof(DTypeIn) + num_threads * sizeof(float);\n+ auto kernel = PersistentVariableLengthMergeStatesKernel<vec_size, bdx, bdy, num_smem_stages,\n+ DTypeIn, DTypeOut, IdType>;\n+ FLASHINFER_CUDA_CALL(cudaOccupancyMaxActiveBlocksPerMultiprocessor(&num_blocks_per_sm, kernel,\n+ num_threads, smem_size));\n+ num_blocks_per_sm = min(num_blocks_per_sm, ceil_div(seq_len * num_heads, num_sms));\n+\n+ dim3 nblks(num_sms * num_blocks_per_sm);\n+ dim3 nthrs(bdx, bdy);\n+ void* args[] = {&v, &s, &indptr, &v_merged, &s_merged, &seq_len, &num_heads};\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));"},"lines_added":{"kind":"number","value":96,"string":"96"},"lines_removed":{"kind":"number","value":77,"string":"77"},"files_in_commit":{"kind":"number","value":1,"string":"1"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/cascade.cuh).\n\nGoal: perf: use persistent kernel for merging attention states\nTarget hardware: unspecified\nTarget models: unspecified\n\nCurrent file:\n```cuda\n/*!\n * Copyright (c) 2023 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_CASCADE_CUH_\n#define FLASHINFER_CASCADE_CUH_\n\n#include <cooperative_groups.h>\n\n#include \"../cp_async.cuh\"\n#include \"../math.cuh\"\n#include \"../utils.cuh\"\n#include \"state.cuh\"\n\nnamespace flashinfer {\n\nnamespace cg = cooperative_groups;\nusing cp_async::PrefetchMode;\nusing cp_async::SharedMemFillMode;\n\n/*!\n * \\brief The CUDA kernel that merges the self-attention state of two index sets A and B.\n * \\tparam vec_size The vector size used in the kernel.\n * \\tparam DTypeIn The data type of v_a and v_b.\n * \\tparam DTypeOut The data type of v_merged.\n * \\param v_a The partial v of index set A. (n, h, d)\n * \\param s_a The logsumexp value of index set A. (n, h)\n * \\param v_b The partial v of index set B. (n, h, d)\n * \\param s_b The logsumexp value of index set B. (n, h)\n * \\param v_merged The merged v of index set A union B. (n, h, d)\n * \\param s_merged The merged logsumexp value of index set A union B. (n, h)\n * \\param num_heads The number of heads of v_a and v_b.\n * \\param head_dim The dimension of each head.\n * \\note Both s_a and s_b are logsumexp values with base 2.\n */\ntemplate <uint32_t vec_size, typename DTypeIn, typename DTypeOut>\n__global__ void MergeStateKernel(DTypeIn* __restrict__ v_a, float* __restrict__ s_a,\n DTypeIn* __restrict__ v_b, float* __restrict__ s_b,\n DTypeOut* __restrict__ v_merged, float* __restrict__ s_merged,\n uint32_t num_heads, uint32_t head_dim) {\n uint32_t tx = threadIdx.x, ty = threadIdx.y;\n uint32_t pos = blockIdx.x;\n uint32_t head_idx = ty;\n\n float s_a_val = s_a[pos * num_heads + head_idx];\n float s_b_val = s_b[pos * num_heads + head_idx];\n float s_max = max(s_a_val, s_b_val);\n s_a_val = math::ptx_exp2(s_a_val - s_max);\n s_b_val = math::ptx_exp2(s_b_val - s_max);\n float a_scale = s_a_val / (s_a_val + s_b_val);\n float b_scale = s_b_val / (s_a_val + s_b_val);\n vec_t<float, vec_size> v_a_vec, v_b_vec, v_merged_vec;\n v_a_vec.cast_load(v_a + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n v_b_vec.cast_load(v_b + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n#pragma unroll\n for (uint32_t i = 0; i < vec_size; ++i) {\n v_merged_vec[i] = a_scale * v_a_vec[i] + b_scale * v_b_vec[i];\n }\n v_merged_vec.cast_store(v_merged + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n if (s_merged != nullptr) {\n s_merged[pos * num_heads + head_idx] = math::ptx_log2(s_a_val + s_b_val) + s_max;\n }\n}\n\n/*!\n * \\brief The CUDA kernel that merges the self-attention state with another state in-place.\n * \\tparam vec_size The vector size used in the kernel.\n * \\tparam DType The data type of v and v_other.\n * \\param v The partial v to be updated in-place. (n, h, d)\n * \\param s The logsumexp value to be updated in-place. (n, h)\n * \\param v_other The other v to be merged. (n, h, d)\n * \\param s_other The other logsumexp value to be merged. (n, h)\n * \\param mask Optional mask of whether to merge given sequences or not. (n)\n * \\param num_heads The number of heads of v and v_other.\n * \\param head_dim The dimension of each head.\n * \\note Both s and s_other are logsumexp values with base 2.\n */\ntemplate <uint32_t vec_size, typename DType>\n__global__ void MergeStateInPlaceKernel(DType* __restrict__ v, float* __restrict__ s,\n DType* __restrict__ v_other, float* __restrict__ s_other,\n uint8_t* __restrict__ mask, uint32_t num_heads,\n uint32_t head_dim) {\n uint32_t pos = blockIdx.x;\n\n if (mask != nullptr && mask[pos] == 0) return;\n\n uint32_t tx = threadIdx.x, ty = threadIdx.y;\n uint32_t head_idx = ty;\n\n float s_val = s[pos * num_heads + head_idx];\n float s_other_val = s_other[pos * num_heads + head_idx];\n float s_max = max(s_val, s_other_val);\n s_val = math::ptx_exp2(s_val - s_max);\n s_other_val = math::ptx_exp2(s_other_val - s_max);\n float scale = s_val / (s_val + s_other_val);\n float other_scale = s_other_val / (s_val + s_other_val);\n vec_t<float, vec_size> v_vec, v_other_vec;\n v_vec.cast_load(v + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n v_other_vec.cast_load(v_other + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n#pragma unroll\n for (uint32_t i = 0; i < vec_size; ++i) {\n v_vec[i] = scale * v_vec[i] + other_scale * v_other_vec[i];\n }\n v_vec.cast_store(v + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n if (s != nullptr) {\n s[pos * num_heads + head_idx] = math::ptx_log2(s_val + s_other_val) + s_max;\n }\n}\n\ntemplate <uint32_t bdx, uint32_t bdy, uint32_t vec_size, typename DTypeIn>\n__device__ __forceinline__ void threadblock_sync_state(state_t<vec_size>& st, DTypeIn* v_smem,\n float* s_smem) {\n const uint32_t tx = threadIdx.x, ty = threadIdx.y;\n constexpr uint32_t head_dim = vec_size * bdx;\n st.o.cast_store(v_smem + ty * head_dim + tx * vec_size);\n s_smem[ty] = st.get_lse();\n st.init();\n __syncthreads();\n\n#pragma unroll\n for (uint32_t iter = 0; iter < bdy; ++iter) {\n float s = s_smem[iter];\n vec_t<float, vec_size> v;\n v.cast_load(v_smem + iter * head_dim + tx * vec_size);\n st.merge(v, s, 1);\n }\n}\n\n/*!\n * \\brief The CUDA kernel that merges self-attention states of a list of index sets.\n * \\param vec_size The vector size used in the kernel.\n * \\tparam DTypeIn The data type of v.\n * \\tparam DTypeOut The data type of v_merged.\n * \\param v The partial v of index sets. (n, num_index_sets, h, d)\n * \\param s The logsumexp value of index sets. (n, num_index_sets, h)\n * \\param v_merged The merged v of index sets union. (n, h, d)\n * \\param s_merged The merged logsumexp value of index sets union. (n, h)\n * \\param num_heads The number of heads of v.\n * \\param head_dim The dimension of each head.\n * \\note s are logsumexp values with base 2.\n */\ntemplate <uint32_t vec_size, typename DTypeIn, typename DTypeOut>\n__global__ void MergeStatesKernel(DTypeIn* __restrict__ V, float* __restrict__ S,\n DTypeOut* __restrict__ v_merged, float* __restrict__ s_merged,\n uint32_t num_index_sets, uint32_t num_heads, uint32_t head_dim) {\n uint32_t tx = threadIdx.x, ty = threadIdx.y;\n uint32_t pos = blockIdx.x;\n uint32_t head_idx = ty;\n\n if (num_index_sets == 0) {\n vec_t<DTypeOut, vec_size> v;\n v.fill(DTypeOut(0));\n v.store(v_merged + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n if (s_merged != nullptr) {\n s_merged[pos * num_heads + head_idx] = -5e4;\n }\n return;\n }\n\n if (num_index_sets == 1) {\n vec_t<DTypeOut, vec_size> v;\n v.cast_load(V + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n v.store(v_merged + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n if (s_merged != nullptr) {\n s_merged[pos * num_heads + head_idx] = S[pos * num_heads + head_idx];\n }\n return;\n }\n\n vec_t<float, vec_size> v_merged_vec;\n state_t<vec_size> st;\n v_merged_vec.fill(0.f);\n#pragma unroll 2\n for (uint32_t iter = 0; iter < num_index_sets; ++iter) {\n float s = S[(pos * num_index_sets + iter) * num_heads + head_idx];\n vec_t<float, vec_size> v;\n v.cast_load(V + ((pos * num_index_sets + iter) * num_heads + head_idx) * head_dim +\n tx * vec_size);\n st.merge(v, s, 1);\n }\n\n st.normalize();\n st.o.cast_store(v_merged + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n if (s_merged != nullptr) {\n s_merged[pos * num_heads + head_idx] = st.get_lse();\n }\n}\n\n/*!\n * \\brief The CUDA kernel that merges self-attention states of a list of index sets,\n * accelerated for larget number of index sets.\n * \\tparam vec_size The vector size used in the kernel.\n * \\tparam bdx The blockDim.x used in the kernel.\n * \\tparam bdy The blockDim.y used in the kernel.\n * \\tparam num_smem_stages The number of stages of shared memory used in the kernel.\n * \\tparam DTypeIn The data type of v.\n * \\tparam DTypeOut The data type of v_merged.\n * \\param V The partial v of index sets. (n, num_index_sets, h, d)\n * \\param S The logsumexp value of index sets. (n, num_index_sets, h)\n * \\param v_merged The merged v of index sets union. (n, h, d)\n * \\param s_merged The merged logsumexp value of index sets union. (n, h)\n * \\param num_heads The number of heads of v.\n * \\param head_dim The dimension of each head.\n * \\note s are logsumexp values with base 2.\n */\ntemplate <uint32_t vec_size, uint32_t bdx, uint32_t bdy, uint32_t num_smem_stages, typename DTypeIn,\n typename DTypeOut>\n__global__ void MergeStatesLargeNumIndexSetsKernel(DTypeIn* __restrict__ V, float* __restrict__ S,\n DTypeOut* __restrict__ v_merged,\n float* __restrict__ s_merged,\n uint32_t num_index_sets, uint32_t num_heads) {\n uint32_t tx = threadIdx.x, ty = threadIdx.y;\n uint32_t pos = blockIdx.x;\n uint32_t head_idx = blockIdx.y;\n state_t<vec_size> st;\n constexpr uint32_t vec_bits = sizeof(DTypeIn) * vec_size * 8;\n constexpr uint32_t head_dim = vec_size * bdx;\n\n extern __shared__ uint8_t smem[];\n DTypeIn* v_smem = (DTypeIn*)smem;\n float* s_smem = (float*)(smem + num_smem_stages * bdy * head_dim * sizeof(DTypeIn));\n\n#pragma unroll\n for (uint32_t iter = 0; iter < num_smem_stages; ++iter) {\n cp_async::pred_load<vec_bits, PrefetchMode::kPrefetch, SharedMemFillMode::kNoFill>(\n v_smem + (iter * bdy + ty) * head_dim + tx * vec_size,\n V + ((pos * num_index_sets + (iter * bdy + ty)) * num_heads + head_idx) * head_dim +\n tx * vec_size,\n (iter * bdy + ty) < num_index_sets);\n cp_async::commit_group();\n }\n#pragma unroll 4\n for (uint32_t iter = 0; iter < ceil_div(num_index_sets, bdy); ++iter) {\n if (iter % bdx == 0) {\n s_smem[ty * bdx + tx] =\n iter * bdy + (ty * bdx + tx) < num_index_sets\n ? S[(pos * num_index_sets + (iter * bdy + ty * bdx + tx)) * num_heads + head_idx]\n : 0.f;\n __syncthreads();\n }\n cp_async::wait_group<num_smem_stages - 1>();\n __syncthreads();\n vec_t<float, vec_size> v;\n v.cast_load(v_smem + ((iter % num_smem_stages) * bdy + ty) * head_dim + tx * vec_size);\n if (iter * bdy + ty < num_index_sets) {\n float s = s_smem[(iter % bdx) * bdy + ty];\n st.merge(v, s, 1);\n }\n __syncthreads();\n cp_async::pred_load<vec_bits, PrefetchMode::kPrefetch, SharedMemFillMode::kNoFill>(\n v_smem + ((iter % num_smem_stages) * bdy + ty) * head_dim + tx * vec_size,\n V +\n ((pos * num_index_sets + ((iter + num_smem_stages) * bdy + ty)) * num_heads +\n head_idx) *\n head_dim +\n tx * vec_size,\n (iter + num_smem_stages) * bdy + ty < num_index_sets);\n cp_async::commit_group();\n }\n cp_async::wait_group<0>();\n __syncthreads();\n\n st.normalize();\n threadblock_sync_state<bdx, bdy, vec_size>(st, v_smem, s_smem);\n st.normalize();\n\n st.o.cast_store(v_merged + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n if (s_merged != nullptr) {\n s_merged[pos * num_heads + head_idx] = st.get_lse();\n }\n}\n\n/*!\n * \\brief The CUDA kernel to merge self-attention states of multiple index sets, the number of index\n * sets at each position might vary.\n * \\tparam vec_size The vector size used in the kernel.\n * \\tparam bdx The blockDim.x used in the kernel.\n * \\tparam bdy The blockDim.y used in the kernel.\n * \\tparam num_smem_stages The number of stages of shared memory used in the kernel.\n * \\tparam DTypeIn The data type of v.\n * \\tparam DTypeOut The data type of v_merged.\n * \\param V The partial v of index sets. (nnz, h, d)\n * \\param S The logsumexp value of index sets. (nnz, h)\n * \\param indptr The start offsets of each position in the variable length array.\n * \\param v_merged The merged v of index sets union. (n, h, d)\n * \\param s_merged The merged logsumexp value of index sets union. (n, h)\n * \\param num_heads The number of heads of v.\n * \\param head_dim The dimension of each head.\n * \\note s are logsumexp values with base 2.\n */\ntemplate <uint32_t vec_size, uint32_t bdx, uint32_t bdy, uint32_t num_smem_stages, typename DTypeIn,\n typename DTypeOut, typename IdType>\n__global__ void VariableLengthMergeStatesKernel(DTypeIn* __restrict__ V, float* __restrict__ S,\n IdType* indptr, DTypeOut* __restrict__ v_merged,\n float* __restrict__ s_merged, uint32_t num_heads) {\n uint32_t tx = threadIdx.x, ty = threadIdx.y;\n uint32_t pos = blockIdx.x;\n uint32_t head_idx = blockIdx.y;\n state_t<vec_size> st;\n constexpr uint32_t vec_bits = sizeof(DTypeIn) * vec_size * 8;\n constexpr uint32_t head_dim = vec_size * bdx;\n\n extern __shared__ uint8_t smem[];\n DTypeIn* v_smem = (DTypeIn*)smem;\n float* s_smem = (float*)(smem + num_smem_stages * bdy * head_dim * sizeof(DTypeIn));\n const uint32_t num_index_sets = indptr[pos + 1] - indptr[pos];\n\n if (num_index_sets == 0) {\n vec_t<DTypeOut, vec_size> v;\n v.fill(DTypeOut(0));\n v.store(v_merged + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n if (s_merged != nullptr) {\n s_merged[pos * num_heads + head_idx] = -5e4;\n }\n return;\n }\n\n if (num_index_sets == 1) {\n vec_t<DTypeOut, vec_size> v;\n v.cast_load(V + (indptr[pos] * num_heads + head_idx) * head_dim + tx * vec_size);\n v.store(v_merged + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n if (s_merged != nullptr) {\n s_merged[pos * num_heads + head_idx] = S[indptr[pos] * num_heads + head_idx];\n }\n }\n\n#pragma unroll\n for (uint32_t iter = 0; iter < num_smem_stages; ++iter) {\n cp_async::pred_load<vec_bits, PrefetchMode::kPrefetch, SharedMemFillMode::kNoFill>(\n v_smem + (iter * bdy + ty) * head_dim + tx * vec_size,\n V + ((indptr[pos] + (iter * bdy + ty)) * num_heads + head_idx) * head_dim + tx * vec_size,\n (iter * bdy + ty) < num_index_sets);\n cp_async::commit_group();\n }\n#pragma unroll 4\n for (uint32_t iter = 0; iter < ceil_div(num_index_sets, bdy); ++iter) {\n if (iter % bdx == 0) {\n s_smem[ty * bdx + tx] =\n iter * bdy + (ty * bdx + tx) < num_index_sets\n ? S[(indptr[pos] + (iter * bdy + ty * bdx + tx)) * num_heads + head_idx]\n : 0.f;\n __syncthreads();\n }\n cp_async::wait_group<num_smem_stages - 1>();\n __syncthreads();\n vec_t<float, vec_size> v;\n v.cast_load(v_smem + ((iter % num_smem_stages) * bdy + ty) * head_dim + tx * vec_size);\n if (iter * bdy + ty < num_index_sets) {\n float s = s_smem[(iter % bdx) * bdy + ty];\n st.merge(v, s, 1);\n }\n __syncthreads();\n cp_async::pred_load<vec_bits, PrefetchMode::kPrefetch, SharedMemFillMode::kNoFill>(\n v_smem + ((iter % num_smem_stages) * bdy + ty) * head_dim + tx * vec_size,\n V +\n ((indptr[pos] + ((iter + num_smem_stages) * bdy + ty)) * num_heads + head_idx) *\n head_dim +\n tx * vec_size,\n (iter + num_smem_stages) * bdy + ty < num_index_sets);\n cp_async::commit_group();\n }\n cp_async::wait_group<0>();\n __syncthreads();\n\n st.normalize();\n threadblock_sync_state<bdx, bdy, vec_size>(st, v_smem, s_smem);\n st.normalize();\n\n st.o.cast_store(v_merged + (pos * num_heads + head_idx) * head_dim + tx * vec_size);\n if (s_merged != nullptr) {\n s_merged[pos * num_heads + head_idx] = st.get_lse();\n }\n}\n\n/*!\n * \\brief Merge the self-attention state of two index sets A and B.\n * \\tparam DTypeIn The data type of v_a and v_b.\n * \\tparam DTypeOut The data type of v_merged.\n * \\param v_a The partial v of index set A (n, h, d)\n * \\param s_a The logsumexp value of index set A. (n, h)\n * \\param v_b The partial v of index set B. (n, h, d)\n * \\param s_b The logsumexp value of index set B. (n, h)\n * \\param v_merged The merged v of index set A union B. (n, h, d)\n * \\param s_merged The merged logsumexp value of index set A union B. (n, h)\n * \\param seq_len The sequence length.\n * \\param num_heads The number of heads of v_a and v_b.\n * \\param head_dim The dimension of each head.\n * \\param stream The CUDA stream to execute the kernel.\n * \\return status Indicates whether CUDA calls are successful\n * \\note Both s_a and s_b are logsumexp values with base 2.\n */\ntemplate <typename DTypeIn, typename DTypeOut>\ncudaError_t MergeState(DTypeIn* v_a, float* s_a, DTypeIn* v_b, float* s_b, DTypeOut* v_merged,\n float* s_merged, uint32_t seq_len, uint32_t num_heads, uint32_t head_dim,\n cudaStream_t stream = nullptr) {\n DISPATCH_HEAD_DIM(head_dim, HEAD_DIM, {\n constexpr uint32_t vec_size = std::max(16U / sizeof(DTypeIn), HEAD_DIM / 32U);\n uint32_t bdx = HEAD_DIM / vec_size;\n uint32_t bdy = num_heads;\n dim3 nblks(seq_len);\n dim3 nthrs(bdx, bdy);\n auto kernel = MergeStateKernel<vec_size, DTypeIn, DTypeOut>;\n void* args[] = {&v_a, &s_a, &v_b, &s_b, &v_merged, &s_merged, &num_heads, &head_dim};\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)kernel, nblks, nthrs, args, 0, stream));\n });\n return cudaSuccess;\n}\n\n/*!\n * \\brief Merge the self-attention state with another state in place.\n * \\tparam DType The data type of v and v_other.\n * \\param v The partial v to be updated in-place. (n, h, d)\n * \\param s The logsumexp value to be updated in-place. (n, h)\n * \\param v_other The other v to be merged. (n, h, d)\n * \\param s_other The other logsumexp value to be merged. (n, h)\n * \\param seq_len The sequence length.\n * \\param num_heads The number of heads of v and v_other.\n * \\param head_dim The dimension of each head.\n * \\param mask Optional mask of whether to merge given sequences or not. (n)\n * \\param stream The CUDA stream to execute the kernel.\n * \\return status Indicates whether CUDA calls are successful\n * \\note Both s and s_other are logsumexp values with base 2.\n */\ntemplate <typename DType>\ncudaError_t MergeStateInPlace(DType* v, float* s, DType* v_other, float* s_other, uint32_t seq_len,\n uint32_t num_heads, uint32_t head_dim, uint8_t* mask = nullptr,\n cudaStream_t stream = nullptr) {\n DISPATCH_HEAD_DIM(head_dim, HEAD_DIM, {\n constexpr uint32_t vec_size = std::max(16U / sizeof(DType), HEAD_DIM / 32U);\n uint32_t bdx = HEAD_DIM / vec_size;\n uint32_t bdy = num_heads;\n dim3 nblks(seq_len);\n dim3 nthrs(bdx, bdy);\n auto kernel = MergeStateInPlaceKernel<vec_size, DType>;\n void* args[] = {&v, &s, &v_other, &s_other, &mask, &num_heads, &head_dim};\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)kernel, nblks, nthrs, args, 0, stream));\n });\n return cudaSuccess;\n}\n\n/*!\n * \\brief Merge self-attention states of a list of index sets.\n * \\tparam DTypeIn The data type of v.\n * \\tparam DTypeOut The data type of v_merged.\n * \\param v The partial v of index sets. (n, num_index_sets, h, d)\n * \\param s The logsumexp value of index sets. (n, num_index_sets, h)\n * \\param v_merged The merged v of index sets union. (n, h, d)\n * \\param s_merged The merged logsumexp value of index sets union. (n, h)\n * \\param num_index_sets The number of index sets.\n * \\param seq_len The sequence length.\n * \\param num_heads The number of heads of v.\n * \\param head_dim The dimension of each head.\n * \\param stream The CUDA stream to execute the kernel.\n * \\return status Indicates whether CUDA calls are successful\n * \\note s are logsumexp values with base 2.\n */\ntemplate <typename DTypeIn, typename DTypeOut>\ncudaError_t MergeStates(DTypeIn* v, float* s, DTypeOut* v_merged, float* s_merged,\n uint32_t num_index_sets, uint32_t seq_len, uint32_t num_heads,\n uint32_t head_dim, cudaStream_t stream = nullptr) {\n DISPATCH_HEAD_DIM(head_dim, HEAD_DIM, {\n constexpr uint32_t vec_size = std::max(16U / sizeof(DTypeIn), HEAD_DIM / 32U);\n constexpr uint32_t bdx = HEAD_DIM / vec_size;\n if (num_index_sets >= seq_len) {\n constexpr uint32_t num_threads = 128;\n constexpr uint32_t bdy = num_threads / bdx;\n dim3 nblks(seq_len, num_heads);\n dim3 nthrs(bdx, bdy);\n constexpr uint32_t num_smem_stages = 4;\n auto kernel = MergeStatesLargeNumIndexSetsKernel<vec_size, bdx, bdy, num_smem_stages, DTypeIn,\n DTypeOut>;\n void* args[] = {&v, &s, &v_merged, &s_merged, &num_index_sets, &num_heads};\n uint32_t smem_size =\n num_smem_stages * bdy * head_dim * sizeof(DTypeIn) + num_threads * sizeof(float);\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n } else {\n uint32_t bdy = num_heads;\n dim3 nblks(seq_len);\n dim3 nthrs(bdx, bdy);\n auto kernel = MergeStatesKernel<vec_size, DTypeIn, DTypeOut>;\n void* args[] = {&v, &s, &v_merged, &s_merged, &num_index_sets, &num_heads, &head_dim};\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)kernel, nblks, nthrs, args, 0, stream));\n }\n });\n return cudaSuccess;\n}\n\ntemplate <typename DTypeIn, typename DTypeOut, typename IdType>\ncudaError_t VariableLengthMergeStates(DTypeIn* v, float* s, IdType* indptr, DTypeOut* v_merged,\n float* s_merged, uint32_t seq_len, uint32_t num_heads,\n uint32_t head_dim, cudaStream_t stream = nullptr) {\n DISPATCH_HEAD_DIM(head_dim, HEAD_DIM, {\n constexpr uint32_t vec_size = std::max(16U / sizeof(DTypeIn), HEAD_DIM / 32U);\n constexpr uint32_t bdx = HEAD_DIM / vec_size;\n constexpr uint32_t num_threads = 128;\n constexpr uint32_t bdy = num_threads / bdx;\n dim3 nblks(seq_len, num_heads);\n dim3 nthrs(bdx, bdy);\n constexpr uint32_t num_smem_stages = 4;\n auto kernel = VariableLengthMergeStatesKernel<vec_size, bdx, bdy, num_smem_stages, DTypeIn,\n DTypeOut, IdType>;\n void* args[] = {&v, &s, &indptr, &v_merged, &s_merged, &num_heads};\n uint32_t smem_size =\n num_smem_stages * bdy * head_dim * sizeof(DTypeIn) + num_threads * sizeof(float);\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n });\n return cudaSuccess;\n}\n\n} // namespace flashinfer\n\n#endif // FLASHINFER_CASCADE_CUH_\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"As observed by @MasterJH5574 , there are cases where our `VariableLengthMergeStatesKernel` launches a lot of CTAs (>=10k) while most of the CTAs only work on small number of merges, this PR fixes the issue by using a persistent kernel.\n\nThere is still load imbalance issue, and I plan to resolve it inside scheduler. I'll leave it for later PRs.\n"},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1296,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"7c397cbd81d4fa5da8aef9f105576dbe67f6c22b"},"date":{"kind":"string","value":"2024-08-20T23:03:22-07:00"},"pr_number":{"kind":"number","value":458,"string":"458"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/458"},"title":{"kind":"string","value":"perf: slight optimization on fragment layout swizzle (#458)"},"message":{"kind":"string","value":"perf: slight optimization on fragment layout swizzle (#458)\n\nfuse two byte perm into one."},"path":{"kind":"string","value":"include/flashinfer/frag_layout_swizzle.cuh"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * Copyright (c) 2024 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_FRAG_LAYOUT_SWIZZLE_CUH_\n#define FLASHINFER_FRAG_LAYOUT_SWIZZLE_CUH_\n\n#include <cuda_runtime.h>\n\n#include <cstdint>\n\n__device__ __forceinline__ uint32_t frag_layout_swizzle_16b_to_8b(uint32_t x) {\n uint32_t tmp = __shfl_xor_sync(0xffffffff, x, 0x1);\n x = __byte_perm(x, tmp, ((threadIdx.x & 0x1) == 0) ? 0x5410 : 0x3276);\n tmp = __shfl_xor_sync(0xffffffff, x, 0x2);\n x = __byte_perm(x, tmp, ((threadIdx.x & 0x2) == 0) ? 0x5410 : 0x3276);\n return x;\n}\n\n__device__ __forceinline__ uint32_t frag_layout_swizzle_16b_to_8b_trans(uint32_t x) {\n x = __byte_perm(x, x, 0x3120);\n uint32_t tmp = __shfl_xor_sync(0xffffffff, x, 0x4);\n x = __byte_perm(x, tmp, ((threadIdx.x & 0x4) == 0) ? 0x5410 : 0x3276);\n tmp = __shfl_xor_sync(0xffffffff, x, 0x8);\n x = __byte_perm(x, tmp, ((threadIdx.x & 0x8) == 0) ? 0x5410 : 0x3276);\n tmp = __shfl_xor_sync(0xffffffff, x, 0x10);\n x = __byte_perm(x, tmp, ((threadIdx.x & 0x10) == 0) ? 0x5410 : 0x3276);\n return x;\n}\n\n#endif // FLASHINFER_FRAG_LAYOUT_SWIZZLE_CUH_\n"},"after_code":{"kind":"string","value":"/*\n * Copyright (c) 2024 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_FRAG_LAYOUT_SWIZZLE_CUH_\n#define FLASHINFER_FRAG_LAYOUT_SWIZZLE_CUH_\n\n#include <cuda_runtime.h>\n\n#include <cstdint>\n\n__device__ __forceinline__ uint32_t frag_layout_swizzle_16b_to_8b(uint32_t x) {\n uint32_t tmp = __shfl_xor_sync(0xffffffff, x, 0x1);\n x = __byte_perm(x, tmp, ((threadIdx.x & 0x1) == 0) ? 0x5410 : 0x3276);\n tmp = __shfl_xor_sync(0xffffffff, x, 0x2);\n x = __byte_perm(x, tmp, ((threadIdx.x & 0x2) == 0) ? 0x5410 : 0x3276);\n return x;\n}\n\n__device__ __forceinline__ uint32_t frag_layout_swizzle_16b_to_8b_trans(uint32_t x) {\n uint32_t tmp = __shfl_xor_sync(0xffffffff, x, 0x4);\n x = __byte_perm(x, tmp, ((threadIdx.x & 0x4) == 0) ? 0x6420 : 0x3175);\n tmp = __shfl_xor_sync(0xffffffff, x, 0x8);\n x = __byte_perm(x, tmp, ((threadIdx.x & 0x8) == 0) ? 0x5410 : 0x3276);\n tmp = __shfl_xor_sync(0xffffffff, x, 0x10);\n x = __byte_perm(x, tmp, ((threadIdx.x & 0x10) == 0) ? 0x5410 : 0x3276);\n return x;\n}\n\n#endif // FLASHINFER_FRAG_LAYOUT_SWIZZLE_CUH_\n"},"diff":{"kind":"string","value":"--- include/flashinfer/frag_layout_swizzle.cuh\n+++ include/flashinfer/frag_layout_swizzle.cuh\n@@ -29,9 +29,8 @@\n }\n \n __device__ __forceinline__ uint32_t frag_layout_swizzle_16b_to_8b_trans(uint32_t x) {\n- x = __byte_perm(x, x, 0x3120);\n uint32_t tmp = __shfl_xor_sync(0xffffffff, x, 0x4);\n- x = __byte_perm(x, tmp, ((threadIdx.x & 0x4) == 0) ? 0x5410 : 0x3276);\n+ x = __byte_perm(x, tmp, ((threadIdx.x & 0x4) == 0) ? 0x6420 : 0x3175);\n tmp = __shfl_xor_sync(0xffffffff, x, 0x8);\n x = __byte_perm(x, tmp, ((threadIdx.x & 0x8) == 0) ? 0x5410 : 0x3276);\n tmp = __shfl_xor_sync(0xffffffff, x, 0x10);"},"lines_added":{"kind":"number","value":1,"string":"1"},"lines_removed":{"kind":"number","value":2,"string":"2"},"files_in_commit":{"kind":"number","value":2,"string":"2"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (include/flashinfer/frag_layout_swizzle.cuh).\n\nGoal: perf: slight optimization on fragment layout swizzle\nTarget hardware: unspecified\nTarget models: unspecified\n\nCurrent file:\n```cuda\n/*\n * Copyright (c) 2024 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_FRAG_LAYOUT_SWIZZLE_CUH_\n#define FLASHINFER_FRAG_LAYOUT_SWIZZLE_CUH_\n\n#include <cuda_runtime.h>\n\n#include <cstdint>\n\n__device__ __forceinline__ uint32_t frag_layout_swizzle_16b_to_8b(uint32_t x) {\n uint32_t tmp = __shfl_xor_sync(0xffffffff, x, 0x1);\n x = __byte_perm(x, tmp, ((threadIdx.x & 0x1) == 0) ? 0x5410 : 0x3276);\n tmp = __shfl_xor_sync(0xffffffff, x, 0x2);\n x = __byte_perm(x, tmp, ((threadIdx.x & 0x2) == 0) ? 0x5410 : 0x3276);\n return x;\n}\n\n__device__ __forceinline__ uint32_t frag_layout_swizzle_16b_to_8b_trans(uint32_t x) {\n x = __byte_perm(x, x, 0x3120);\n uint32_t tmp = __shfl_xor_sync(0xffffffff, x, 0x4);\n x = __byte_perm(x, tmp, ((threadIdx.x & 0x4) == 0) ? 0x5410 : 0x3276);\n tmp = __shfl_xor_sync(0xffffffff, x, 0x8);\n x = __byte_perm(x, tmp, ((threadIdx.x & 0x8) == 0) ? 0x5410 : 0x3276);\n tmp = __shfl_xor_sync(0xffffffff, x, 0x10);\n x = __byte_perm(x, tmp, ((threadIdx.x & 0x10) == 0) ? 0x5410 : 0x3276);\n return x;\n}\n\n#endif // FLASHINFER_FRAG_LAYOUT_SWIZZLE_CUH_\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"fuse two byte perm into one.\n"},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1297,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"7c397cbd81d4fa5da8aef9f105576dbe67f6c22b"},"date":{"kind":"string","value":"2024-08-20T23:03:22-07:00"},"pr_number":{"kind":"number","value":458,"string":"458"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/458"},"title":{"kind":"string","value":"perf: slight optimization on fragment layout swizzle (#458)"},"message":{"kind":"string","value":"perf: slight optimization on fragment layout swizzle (#458)\n\nfuse two byte perm into one."},"path":{"kind":"string","value":"include/flashinfer/vec_dtypes.cuh"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * Copyright (c) 2023 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef VEC_DTYPES_CUH_\n#define VEC_DTYPES_CUH_\n\n#include <cuda_bf16.h>\n#include <cuda_fp16.h>\n#include <cuda_fp8.h>\n#include <cuda_runtime.h>\n\n#include <type_traits>\n\nnamespace flashinfer {\n\n#if (!defined(__CUDA_ARCH__) || (__CUDA_ARCH__ >= 900))\n#define FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n#endif\n\n#define FLASHINFER_INLINE inline __attribute__((always_inline)) __device__\n\n/******************* vec_t type cast *******************/\n\ntemplate <typename dst_t, typename src_t>\nstruct vec_cast {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(dst_t* dst, const src_t* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size; ++i) {\n dst[i] = (dst_t)src[i];\n }\n }\n};\n\ntemplate <>\nstruct vec_cast<float, half> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(float* dst, const half* src) {\n if constexpr (vec_size == 1) {\n dst[0] = (float)src[0];\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n ((float2*)dst)[i] = __half22float2(((half2*)src)[i]);\n }\n }\n }\n};\n\ntemplate <>\nstruct vec_cast<half, float> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(half* dst, const float* src) {\n if constexpr (vec_size == 1) {\n dst[0] = __float2half(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n ((half2*)dst)[i] = __float22half2_rn(((float2*)src)[i]);\n }\n }\n }\n};\n\ntemplate <typename T>\nconstexpr FLASHINFER_INLINE int get_exponent_bits() {\n if constexpr (std::is_same<T, __nv_fp8_e4m3>::value) {\n return 4;\n } else if constexpr (std::is_same<T, __nv_fp8_e5m2>::value) {\n return 5;\n } else if constexpr (std::is_same<T, half>::value) {\n return 5;\n } else if constexpr (std::is_same<T, nv_bfloat16>::value) {\n return 8;\n }\n}\n\ntemplate <typename T>\nconstexpr FLASHINFER_INLINE int get_mantissa_bits() {\n if constexpr (std::is_same<T, __nv_fp8_e4m3>::value) {\n return 3;\n } else if constexpr (std::is_same<T, __nv_fp8_e5m2>::value) {\n return 2;\n } else if constexpr (std::is_same<T, half>::value) {\n return 11;\n } else if constexpr (std::is_same<T, nv_bfloat16>::value) {\n return 7;\n }\n}\n\n/*!\n * \\brief Fallback to software fast dequant implementation if hardware dequantization is not\n * available.\n * \\note Inspired by Marlin's fast dequantization, but here we don't have to permute\n * weights order.\n * \\ref\n * https://github.com/vllm-project/vllm/blob/6dffa4b0a6120159ef2fe44d695a46817aff65bc/csrc/quantization/fp8/fp8_marlin.cu#L120\n */\ntemplate <typename fp8_dtype, typename fp16_dtype>\n__device__ void fast_dequant_f8f16x4(uint32_t* input, uint2* output) {\n uint32_t q = *input;\n if constexpr (std::is_same<fp8_dtype, __nv_fp8_e5m2>::value &&\n std::is_same<fp16_dtype, half>::value) {\n output->x = __byte_perm(0U, q, 0x5140);\n output->y = __byte_perm(0U, q, 0x7362);\n } else {\n constexpr int FP8_EXPONENT = get_exponent_bits<fp8_dtype>();\n constexpr int FP8_MANTISSA = get_mantissa_bits<fp8_dtype>();\n constexpr int FP16_EXPONENT = get_exponent_bits<fp16_dtype>();\n\n constexpr int RIGHT_SHIFT = FP16_EXPONENT - FP8_EXPONENT;\n // Calculate MASK for extracting mantissa and exponent\n constexpr int MASK1 = 0x80000000;\n constexpr int MASK2 = MASK1 >> (FP8_EXPONENT + FP8_MANTISSA);\n constexpr int MASK3 = MASK2 & 0x7fffffff;\n constexpr int MASK = MASK3 | (MASK3 >> 16);\n // Final MASK value: 0x7F007F00\n q = __byte_perm(q, q, 0x1302);\n\n // Extract and shift FP8 values to FP16 format\n uint32_t Out1 = (q & 0x80008000) | ((q & MASK) >> RIGHT_SHIFT);\n uint32_t Out2 = ((q << 8) & 0x80008000) | (((q << 8) & MASK) >> RIGHT_SHIFT);\n\n constexpr int BIAS_OFFSET = (1 << (FP16_EXPONENT - 1)) - (1 << (FP8_EXPONENT - 1));\n // Construct and apply exponent bias\n if constexpr (std::is_same<fp16_dtype, half>::value) {\n const half2 bias_reg = __float2half2_rn(float(1 << BIAS_OFFSET));\n\n // Convert to half2 and apply bias\n *(half2*)&(output->x) = __hmul2(*reinterpret_cast<const half2*>(&Out1), bias_reg);\n *(half2*)&(output->y) = __hmul2(*reinterpret_cast<const half2*>(&Out2), bias_reg);\n } else {\n constexpr uint32_t BIAS = (BIAS_OFFSET + 127) << 23;\n const nv_bfloat162 bias_reg = __float2bfloat162_rn(*reinterpret_cast<const float*>(&BIAS));\n // Convert to bfloat162 and apply bias\n *(nv_bfloat162*)&(output->x) =\n __hmul2(*reinterpret_cast<const nv_bfloat162*>(&Out1), bias_reg);\n *(nv_bfloat162*)&(output->y) =\n __hmul2(*reinterpret_cast<const nv_bfloat162*>(&Out2), bias_reg);\n }\n }\n}\n\ntemplate <>\nstruct vec_cast<nv_bfloat16, __nv_fp8_e4m3> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(nv_bfloat16* dst, const __nv_fp8_e4m3* src) {\n if constexpr (vec_size == 1) {\n dst[0] = nv_bfloat16(src[0]);\n } else if constexpr (vec_size == 2) {\n dst[0] = nv_bfloat16(src[0]);\n dst[1] = nv_bfloat16(src[1]);\n } else {\n static_assert(vec_size % 4 == 0, \"vec_size must be a multiple of 4\");\n#pragma unroll\n for (uint32_t i = 0; i < vec_size / 4; ++i) {\n fast_dequant_f8f16x4<__nv_fp8_e4m3, nv_bfloat16>((uint32_t*)&src[i * 4],\n (uint2*)&dst[i * 4]);\n }\n }\n }\n};\n\ntemplate <>\nstruct vec_cast<nv_bfloat16, __nv_fp8_e5m2> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(nv_bfloat16* dst, const __nv_fp8_e5m2* src) {\n if constexpr (vec_size == 1) {\n dst[0] = nv_bfloat16(src[0]);\n } else if constexpr (vec_size == 2) {\n dst[0] = nv_bfloat16(src[0]);\n dst[1] = nv_bfloat16(src[1]);\n } else {\n static_assert(vec_size % 4 == 0, \"vec_size must be a multiple of 4\");\n#pragma unroll\n for (uint32_t i = 0; i < vec_size / 4; ++i) {\n fast_dequant_f8f16x4<__nv_fp8_e5m2, nv_bfloat16>((uint32_t*)&src[i * 4],\n (uint2*)&dst[i * 4]);\n }\n }\n }\n};\n\ntemplate <>\nstruct vec_cast<__nv_fp8_e4m3, half> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(__nv_fp8_e4m3* dst, const half* src) {\n#ifdef FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n if constexpr (vec_size == 1) {\n dst[0] = __nv_fp8_e4m3(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint16_t y;\n uint32_t x = *(uint32_t*)&src[i * 2];\n asm volatile(\"cvt.rn.satfinite.e4m3x2.f16x2 %0, %1;\" : \"=h\"(y) : \"r\"(x));\n *(uint16_t*)&dst[i * 2] = y;\n }\n }\n#else\n#pragma unroll\n for (size_t i = 0; i < vec_size; ++i) {\n dst[i] = __nv_fp8_e4m3(src[i]);\n }\n#endif // FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n }\n};\n\ntemplate <>\nstruct vec_cast<__nv_fp8_e5m2, half> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(__nv_fp8_e5m2* dst, const half* src) {\n#ifdef FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n if constexpr (vec_size == 1) {\n dst[0] = __nv_fp8_e5m2(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint16_t y;\n uint32_t x = *(uint32_t*)&src[i * 2];\n asm volatile(\"cvt.rn.satfinite.e5m2x2.f16x2 %0, %1;\" : \"=h\"(y) : \"r\"(x));\n *(uint16_t*)&dst[i * 2] = y;\n }\n }\n#else\n#pragma unroll\n for (size_t i = 0; i < vec_size; ++i) {\n dst[i] = __nv_fp8_e5m2(src[i]);\n }\n#endif // FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n }\n};\n\ntemplate <>\nstruct vec_cast<half, __nv_fp8_e4m3> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(half* dst, const __nv_fp8_e4m3* src) {\n#ifdef FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n if constexpr (vec_size == 1) {\n dst[0] = half(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint32_t y;\n uint16_t x = *(uint16_t*)&src[i * 2];\n asm volatile(\"cvt.rn.f16x2.e4m3x2 %0, %1;\" : \"=r\"(y) : \"h\"(x));\n *(uint32_t*)&dst[i * 2] = y;\n }\n }\n#else\n if constexpr (vec_size == 1) {\n dst[0] = half(src[0]);\n } else if constexpr (vec_size == 2) {\n dst[0] = half(src[0]);\n dst[1] = half(src[1]);\n } else {\n static_assert(vec_size % 4 == 0, \"vec_size must be a multiple of 4\");\n#pragma unroll\n for (uint32_t i = 0; i < vec_size / 4; ++i) {\n fast_dequant_f8f16x4<__nv_fp8_e4m3, half>((uint32_t*)&src[i * 4], (uint2*)&dst[i * 4]);\n }\n }\n#endif // FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n }\n};\n\ntemplate <>\nstruct vec_cast<half, __nv_fp8_e5m2> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(half* dst, const __nv_fp8_e5m2* src) {\n#ifdef FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n if constexpr (vec_size == 1) {\n dst[0] = half(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint32_t y;\n uint16_t x = *(uint16_t*)&src[i * 2];\n asm volatile(\"cvt.rn.f16x2.e5m2x2 %0, %1;\" : \"=r\"(y) : \"h\"(x));\n *(uint32_t*)&dst[i * 2] = y;\n }\n }\n#else\n if constexpr (vec_size == 1) {\n dst[0] = half(src[0]);\n } else if constexpr (vec_size == 2) {\n dst[0] = half(src[0]);\n dst[1] = half(src[1]);\n } else {\n static_assert(vec_size % 4 == 0, \"vec_size must be a multiple of 4\");\n#pragma unroll\n for (uint32_t i = 0; i < vec_size / 4; ++i) {\n fast_dequant_f8f16x4<__nv_fp8_e5m2, half>((uint32_t*)&src[i * 4], (uint2*)&dst[i * 4]);\n }\n }\n#endif // FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n }\n};\n\ntemplate <>\nstruct vec_cast<float, nv_bfloat16> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(float* dst, const nv_bfloat16* src) {\n if constexpr (vec_size == 1) {\n dst[0] = (float)src[0];\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n ((float2*)dst)[i] = __bfloat1622float2(((nv_bfloat162*)src)[i]);\n }\n }\n }\n};\n\ntemplate <>\nstruct vec_cast<nv_bfloat16, float> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(nv_bfloat16* dst, const float* src) {\n if constexpr (vec_size == 1) {\n dst[0] = nv_bfloat16(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n ((nv_bfloat162*)dst)[i] = __float22bfloat162_rn(((float2*)src)[i]);\n }\n }\n }\n};\n\ntemplate <typename float_t, size_t vec_size>\nstruct vec_t {\n FLASHINFER_INLINE float_t& operator[](size_t i);\n FLASHINFER_INLINE const float_t& operator[](size_t i) const;\n FLASHINFER_INLINE void fill(float_t val);\n FLASHINFER_INLINE void load(const float_t* ptr);\n FLASHINFER_INLINE void store(float_t* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src);\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr);\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const;\n FLASHINFER_INLINE static void memcpy(float_t* dst, const float_t* src);\n FLASHINFER_INLINE float_t* ptr();\n};\n\ntemplate <typename src_float_t, typename tgt_float_t, size_t vec_size>\nFLASHINFER_INLINE void cast_from_impl(vec_t<tgt_float_t, vec_size>& dst,\n const vec_t<src_float_t, vec_size>& src) {\n vec_cast<tgt_float_t, src_float_t>::cast<vec_size>(\n dst.ptr(), const_cast<vec_t<src_float_t, vec_size>*>(&src)->ptr());\n}\n\ntemplate <typename src_float_t, typename tgt_float_t, size_t vec_size>\nFLASHINFER_INLINE void cast_load_impl(vec_t<tgt_float_t, vec_size>& dst,\n const src_float_t* src_ptr) {\n if constexpr (std::is_same<src_float_t, tgt_float_t>::value) {\n dst.load(src_ptr);\n } else {\n vec_t<src_float_t, vec_size> tmp;\n tmp.load(src_ptr);\n dst.cast_from(tmp);\n }\n}\n\ntemplate <typename src_float_t, typename tgt_float_t, size_t vec_size>\nFLASHINFER_INLINE void cast_store_impl(tgt_float_t* dst_ptr,\n const vec_t<src_float_t, vec_size>& src) {\n if constexpr (std::is_same<src_float_t, tgt_float_t>::value) {\n src.store(dst_ptr);\n } else {\n vec_t<tgt_float_t, vec_size> tmp;\n tmp.cast_from(src);\n tmp.store(dst_ptr);\n }\n}\n\n/******************* vec_t<__nv_fp8_e4m3> *******************/\n\n// __nv_fp8_e4m3 x 1\ntemplate <>\nstruct vec_t<__nv_fp8_e4m3, 1> {\n __nv_fp8_e4m3 data;\n\n FLASHINFER_INLINE __nv_fp8_e4m3& operator[](size_t i) { return ((__nv_fp8_e4m3*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e4m3& operator[](size_t i) const {\n return ((const __nv_fp8_e4m3*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e4m3* ptr() { return reinterpret_cast<__nv_fp8_e4m3*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e4m3 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e4m3* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e4m3* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 1>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e4m3* dst, const __nv_fp8_e4m3* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 1>::fill(__nv_fp8_e4m3 val) { data = val; }\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 1>::load(const __nv_fp8_e4m3* ptr) { data = *ptr; }\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 1>::store(__nv_fp8_e4m3* ptr) const { *ptr = data; }\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 1>::memcpy(__nv_fp8_e4m3* dst,\n const __nv_fp8_e4m3* src) {\n *dst = *src;\n}\n\n// __nv_fp8_e4m3 x 2\ntemplate <>\nstruct vec_t<__nv_fp8_e4m3, 2> {\n __nv_fp8x2_e4m3 data;\n\n FLASHINFER_INLINE __nv_fp8_e4m3& operator[](size_t i) { return ((__nv_fp8_e4m3*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e4m3& operator[](size_t i) const {\n return ((const __nv_fp8_e4m3*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e4m3* ptr() { return reinterpret_cast<__nv_fp8_e4m3*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e4m3 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e4m3* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e4m3* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 2>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e4m3* dst, const __nv_fp8_e4m3* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 2>::fill(__nv_fp8_e4m3 val) {\n data.__x = (__nv_fp8x2_storage_t(val.__x) << 8) | __nv_fp8x2_storage_t(val.__x);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 2>::load(const __nv_fp8_e4m3* ptr) {\n data = *((__nv_fp8x2_e4m3*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 2>::store(__nv_fp8_e4m3* ptr) const {\n *((__nv_fp8x2_e4m3*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 2>::memcpy(__nv_fp8_e4m3* dst,\n const __nv_fp8_e4m3* src) {\n *((__nv_fp8x2_e4m3*)dst) = *((__nv_fp8x2_e4m3*)src);\n}\n\n// __nv_fp8_e4m3 x 4\n\ntemplate <>\nstruct vec_t<__nv_fp8_e4m3, 4> {\n __nv_fp8x4_e4m3 data;\n\n FLASHINFER_INLINE __nv_fp8_e4m3& operator[](size_t i) { return ((__nv_fp8_e4m3*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e4m3& operator[](size_t i) const {\n return ((const __nv_fp8_e4m3*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e4m3* ptr() { return reinterpret_cast<__nv_fp8_e4m3*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e4m3 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e4m3* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e4m3* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 4>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e4m3* dst, const __nv_fp8_e4m3* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 4>::fill(__nv_fp8_e4m3 val) {\n data.__x = (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 4>::load(const __nv_fp8_e4m3* ptr) {\n data = *((__nv_fp8x4_e4m3*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 4>::store(__nv_fp8_e4m3* ptr) const {\n *((__nv_fp8x4_e4m3*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 4>::memcpy(__nv_fp8_e4m3* dst,\n const __nv_fp8_e4m3* src) {\n *((__nv_fp8x4_e4m3*)dst) = *((__nv_fp8x4_e4m3*)src);\n}\n\n// __nv_fp8_e4m3 x 8\n\ntemplate <>\nstruct vec_t<__nv_fp8_e4m3, 8> {\n uint2 data;\n\n FLASHINFER_INLINE __nv_fp8_e4m3& operator[](size_t i) { return ((__nv_fp8_e4m3*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e4m3& operator[](size_t i) const {\n return ((const __nv_fp8_e4m3*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e4m3* ptr() { return reinterpret_cast<__nv_fp8_e4m3*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e4m3 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e4m3* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e4m3* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 8>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e4m3* dst, const __nv_fp8_e4m3* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 8>::fill(__nv_fp8_e4m3 val) {\n ((__nv_fp8x4_e4m3*)(&data.x))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e4m3*)(&data.y))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 8>::load(const __nv_fp8_e4m3* ptr) {\n data = *((uint2*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 8>::store(__nv_fp8_e4m3* ptr) const {\n *((uint2*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 8>::memcpy(__nv_fp8_e4m3* dst,\n const __nv_fp8_e4m3* src) {\n *((uint2*)dst) = *((uint2*)src);\n}\n\n// __nv_fp8_e4m3 x 16 or more\ntemplate <size_t vec_size>\nstruct vec_t<__nv_fp8_e4m3, vec_size> {\n uint4 data[vec_size / 16];\n\n FLASHINFER_INLINE __nv_fp8_e4m3& operator[](size_t i) { return ((__nv_fp8_e4m3*)data)[i]; }\n FLASHINFER_INLINE const __nv_fp8_e4m3& operator[](size_t i) const {\n return ((const __nv_fp8_e4m3*)data)[i];\n }\n FLASHINFER_INLINE __nv_fp8_e4m3* ptr() { return reinterpret_cast<__nv_fp8_e4m3*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e4m3 val) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((__nv_fp8x4_e4m3*)(&(data[i].x)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e4m3*)(&(data[i].y)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e4m3*)(&(data[i].z)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e4m3*)(&(data[i].w)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n }\n }\n FLASHINFER_INLINE void load(const __nv_fp8_e4m3* ptr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i] = ((uint4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(__nv_fp8_e4m3* ptr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((uint4*)ptr)[i] = data[i];\n }\n }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e4m3* dst, const __nv_fp8_e4m3* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((uint4*)dst)[i] = ((uint4*)src)[i];\n }\n }\n};\n\n/******************* vec_t<__nv_fp8_e5m2> *******************/\n\n// __nv_fp8_e5m2 x 1\ntemplate <>\nstruct vec_t<__nv_fp8_e5m2, 1> {\n __nv_fp8_e5m2 data;\n\n FLASHINFER_INLINE __nv_fp8_e5m2& operator[](size_t i) { return ((__nv_fp8_e5m2*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e5m2& operator[](size_t i) const {\n return ((const __nv_fp8_e5m2*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e5m2* ptr() { return reinterpret_cast<__nv_fp8_e5m2*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e5m2 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e5m2* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e5m2* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 1>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e5m2* dst, const __nv_fp8_e5m2* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 1>::fill(__nv_fp8_e5m2 val) { data = val; }\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 1>::load(const __nv_fp8_e5m2* ptr) { data = *ptr; }\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 1>::store(__nv_fp8_e5m2* ptr) const { *ptr = data; }\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 1>::memcpy(__nv_fp8_e5m2* dst,\n const __nv_fp8_e5m2* src) {\n *dst = *src;\n}\n\n// __nv_fp8_e5m2 x 2\ntemplate <>\nstruct vec_t<__nv_fp8_e5m2, 2> {\n __nv_fp8x2_e5m2 data;\n\n FLASHINFER_INLINE __nv_fp8_e5m2& operator[](size_t i) { return ((__nv_fp8_e5m2*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e5m2& operator[](size_t i) const {\n return ((const __nv_fp8_e5m2*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e5m2* ptr() { return reinterpret_cast<__nv_fp8_e5m2*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e5m2 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e5m2* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e5m2* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 2>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e5m2* dst, const __nv_fp8_e5m2* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 2>::fill(__nv_fp8_e5m2 val) {\n data.__x = (__nv_fp8x2_storage_t(val.__x) << 8) | __nv_fp8x2_storage_t(val.__x);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 2>::load(const __nv_fp8_e5m2* ptr) {\n data = *((__nv_fp8x2_e5m2*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 2>::store(__nv_fp8_e5m2* ptr) const {\n *((__nv_fp8x2_e5m2*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 2>::memcpy(__nv_fp8_e5m2* dst,\n const __nv_fp8_e5m2* src) {\n *((__nv_fp8x2_e5m2*)dst) = *((__nv_fp8x2_e5m2*)src);\n}\n\n// __nv_fp8_e5m2 x 4\n\ntemplate <>\nstruct vec_t<__nv_fp8_e5m2, 4> {\n __nv_fp8x4_e5m2 data;\n\n FLASHINFER_INLINE __nv_fp8_e5m2& operator[](size_t i) { return ((__nv_fp8_e5m2*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e5m2& operator[](size_t i) const {\n return ((const __nv_fp8_e5m2*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e5m2* ptr() { return reinterpret_cast<__nv_fp8_e5m2*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e5m2 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e5m2* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e5m2* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 4>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e5m2* dst, const __nv_fp8_e5m2* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 4>::fill(__nv_fp8_e5m2 val) {\n data.__x = (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 4>::load(const __nv_fp8_e5m2* ptr) {\n data = *((__nv_fp8x4_e5m2*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 4>::store(__nv_fp8_e5m2* ptr) const {\n *((__nv_fp8x4_e5m2*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 4>::memcpy(__nv_fp8_e5m2* dst,\n const __nv_fp8_e5m2* src) {\n *((__nv_fp8x4_e5m2*)dst) = *((__nv_fp8x4_e5m2*)src);\n}\n\n// __nv_fp8_e5m2 x 8\n\ntemplate <>\nstruct vec_t<__nv_fp8_e5m2, 8> {\n uint2 data;\n\n FLASHINFER_INLINE __nv_fp8_e5m2& operator[](size_t i) { return ((__nv_fp8_e5m2*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e5m2& operator[](size_t i) const {\n return ((const __nv_fp8_e5m2*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e5m2* ptr() { return reinterpret_cast<__nv_fp8_e5m2*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e5m2 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e5m2* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e5m2* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 8>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e5m2* dst, const __nv_fp8_e5m2* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 8>::fill(__nv_fp8_e5m2 val) {\n ((__nv_fp8x4_e5m2*)(&data.x))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e5m2*)(&data.y))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 8>::load(const __nv_fp8_e5m2* ptr) {\n data = *((uint2*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 8>::store(__nv_fp8_e5m2* ptr) const {\n *((uint2*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 8>::memcpy(__nv_fp8_e5m2* dst,\n const __nv_fp8_e5m2* src) {\n *((uint2*)dst) = *((uint2*)src);\n}\n\n// __nv_fp8_e5m2 x 16 or more\n\ntemplate <size_t vec_size>\nstruct vec_t<__nv_fp8_e5m2, vec_size> {\n uint4 data[vec_size / 16];\n\n FLASHINFER_INLINE __nv_fp8_e5m2& operator[](size_t i) { return ((__nv_fp8_e5m2*)data)[i]; }\n FLASHINFER_INLINE const __nv_fp8_e5m2& operator[](size_t i) const {\n return ((const __nv_fp8_e5m2*)data)[i];\n }\n FLASHINFER_INLINE __nv_fp8_e5m2* ptr() { return reinterpret_cast<__nv_fp8_e5m2*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e5m2 val) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((__nv_fp8x4_e5m2*)(&(data[i].x)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e5m2*)(&(data[i].y)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e5m2*)(&(data[i].z)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e5m2*)(&(data[i].w)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n }\n }\n FLASHINFER_INLINE void load(const __nv_fp8_e5m2* ptr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i] = ((uint4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(__nv_fp8_e5m2* ptr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((uint4*)ptr)[i] = data[i];\n }\n }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e5m2* dst, const __nv_fp8_e5m2* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((uint4*)dst)[i] = ((uint4*)src)[i];\n }\n }\n};\n\n/******************* vec_t<half> *******************/\n\n// half x 1\ntemplate <>\nstruct vec_t<half, 1> {\n half data;\n\n FLASHINFER_INLINE half& operator[](size_t i) { return ((half*)(&data))[i]; }\n FLASHINFER_INLINE const half& operator[](size_t i) const { return ((const half*)(&data))[i]; }\n FLASHINFER_INLINE half* ptr() { return reinterpret_cast<half*>(&data); }\n FLASHINFER_INLINE void fill(half val);\n FLASHINFER_INLINE void load(const half* ptr);\n FLASHINFER_INLINE void store(half* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 1>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(half* dst, const half* src);\n};\n\nFLASHINFER_INLINE void vec_t<half, 1>::fill(half val) { data = val; }\n\nFLASHINFER_INLINE void vec_t<half, 1>::load(const half* ptr) { data = *ptr; }\n\nFLASHINFER_INLINE void vec_t<half, 1>::store(half* ptr) const { *ptr = data; }\n\nFLASHINFER_INLINE void vec_t<half, 1>::memcpy(half* dst, const half* src) { *dst = *src; }\n\n// half x 2\ntemplate <>\nstruct vec_t<half, 2> {\n half2 data;\n\n FLASHINFER_INLINE half& operator[](size_t i) { return ((half*)(&data))[i]; }\n FLASHINFER_INLINE const half& operator[](size_t i) const { return ((const half*)(&data))[i]; }\n FLASHINFER_INLINE half* ptr() { return reinterpret_cast<half*>(&data); }\n FLASHINFER_INLINE void fill(half val);\n FLASHINFER_INLINE void load(const half* ptr);\n FLASHINFER_INLINE void store(half* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 2>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(half* dst, const half* src);\n};\n\nFLASHINFER_INLINE void vec_t<half, 2>::fill(half val) { data = make_half2(val, val); }\n\nFLASHINFER_INLINE void vec_t<half, 2>::load(const half* ptr) { data = *((half2*)ptr); }\n\nFLASHINFER_INLINE void vec_t<half, 2>::store(half* ptr) const { *((half2*)ptr) = data; }\n\nFLASHINFER_INLINE void vec_t<half, 2>::memcpy(half* dst, const half* src) {\n *((half2*)dst) = *((half2*)src);\n}\n\n// half x 4\n\ntemplate <>\nstruct vec_t<half, 4> {\n uint2 data;\n\n FLASHINFER_INLINE half& operator[](size_t i) { return ((half*)(&data))[i]; }\n FLASHINFER_INLINE const half& operator[](size_t i) const { return ((const half*)(&data))[i]; }\n FLASHINFER_INLINE half* ptr() { return reinterpret_cast<half*>(&data); }\n FLASHINFER_INLINE void fill(half val);\n FLASHINFER_INLINE void load(const half* ptr);\n FLASHINFER_INLINE void store(half* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 4>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(half* dst, const half* src);\n};\n\nFLASHINFER_INLINE void vec_t<half, 4>::fill(half val) {\n *(half2*)(&data.x) = make_half2(val, val);\n *(half2*)(&data.y) = make_half2(val, val);\n}\n\nFLASHINFER_INLINE void vec_t<half, 4>::load(const half* ptr) { data = *((uint2*)ptr); }\n\nFLASHINFER_INLINE void vec_t<half, 4>::store(half* ptr) const { *((uint2*)ptr) = data; }\n\nFLASHINFER_INLINE void vec_t<half, 4>::memcpy(half* dst, const half* src) {\n *((uint2*)dst) = *((uint2*)src);\n}\n\n// half x 8 or more\n\ntemplate <size_t vec_size>\nstruct vec_t<half, vec_size> {\n uint4 data[vec_size / 8];\n FLASHINFER_INLINE half& operator[](size_t i) { return ((half*)data)[i]; }\n FLASHINFER_INLINE const half& operator[](size_t i) const { return ((const half*)data)[i]; }\n FLASHINFER_INLINE half* ptr() { return reinterpret_cast<half*>(&data); }\n FLASHINFER_INLINE void fill(half val) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n *(half2*)(&(data[i].x)) = make_half2(val, val);\n *(half2*)(&(data[i].y)) = make_half2(val, val);\n *(half2*)(&(data[i].z)) = make_half2(val, val);\n *(half2*)(&(data[i].w)) = make_half2(val, val);\n }\n }\n FLASHINFER_INLINE void load(const half* ptr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n data[i] = ((uint4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(half* ptr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n ((uint4*)ptr)[i] = data[i];\n }\n }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(half* dst, const half* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n ((uint4*)dst)[i] = ((uint4*)src)[i];\n }\n }\n};\n\n/******************* vec_t<nv_bfloat16> *******************/\n\n// nv_bfloat16 x 1\ntemplate <>\nstruct vec_t<nv_bfloat16, 1> {\n nv_bfloat16 data;\n FLASHINFER_INLINE nv_bfloat16& operator[](size_t i) { return ((nv_bfloat16*)(&data))[i]; }\n FLASHINFER_INLINE const nv_bfloat16& operator[](size_t i) const {\n return ((const nv_bfloat16*)(&data))[i];\n }\n FLASHINFER_INLINE nv_bfloat16* ptr() { return reinterpret_cast<nv_bfloat16*>(&data); }\n FLASHINFER_INLINE void fill(nv_bfloat16 val);\n FLASHINFER_INLINE void load(const nv_bfloat16* ptr);\n FLASHINFER_INLINE void store(nv_bfloat16* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 1>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(nv_bfloat16* dst, const nv_bfloat16* src);\n};\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 1>::fill(nv_bfloat16 val) { data = val; }\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 1>::load(const nv_bfloat16* ptr) { data = *ptr; }\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 1>::store(nv_bfloat16* ptr) const { *ptr = data; }\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 1>::memcpy(nv_bfloat16* dst, const nv_bfloat16* src) {\n *dst = *src;\n}\n\n// nv_bfloat16 x 2\ntemplate <>\nstruct vec_t<nv_bfloat16, 2> {\n nv_bfloat162 data;\n\n FLASHINFER_INLINE nv_bfloat16& operator[](size_t i) { return ((nv_bfloat16*)(&data))[i]; }\n FLASHINFER_INLINE const nv_bfloat16& operator[](size_t i) const {\n return ((const nv_bfloat16*)(&data))[i];\n }\n FLASHINFER_INLINE nv_bfloat16* ptr() { return reinterpret_cast<nv_bfloat16*>(&data); }\n FLASHINFER_INLINE void fill(nv_bfloat16 val);\n FLASHINFER_INLINE void load(const nv_bfloat16* ptr);\n FLASHINFER_INLINE void store(nv_bfloat16* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 2>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(nv_bfloat16* dst, const nv_bfloat16* src);\n};\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 2>::fill(nv_bfloat16 val) {\n data = make_bfloat162(val, val);\n}\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 2>::load(const nv_bfloat16* ptr) {\n data = *((nv_bfloat162*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 2>::store(nv_bfloat16* ptr) const {\n *((nv_bfloat162*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 2>::memcpy(nv_bfloat16* dst, const nv_bfloat16* src) {\n *((nv_bfloat162*)dst) = *((nv_bfloat162*)src);\n}\n\n// nv_bfloat16 x 4\n\ntemplate <>\nstruct vec_t<nv_bfloat16, 4> {\n uint2 data;\n\n FLASHINFER_INLINE nv_bfloat16& operator[](size_t i) { return ((nv_bfloat16*)(&data))[i]; }\n FLASHINFER_INLINE const nv_bfloat16& operator[](size_t i) const {\n return ((const nv_bfloat16*)(&data))[i];\n }\n FLASHINFER_INLINE nv_bfloat16* ptr() { return reinterpret_cast<nv_bfloat16*>(&data); }\n FLASHINFER_INLINE void fill(nv_bfloat16 val);\n FLASHINFER_INLINE void load(const nv_bfloat16* ptr);\n FLASHINFER_INLINE void store(nv_bfloat16* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 4>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(nv_bfloat16* dst, const nv_bfloat16* src);\n};\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 4>::fill(nv_bfloat16 val) {\n *(nv_bfloat162*)(&data.x) = make_bfloat162(val, val);\n *(nv_bfloat162*)(&data.y) = make_bfloat162(val, val);\n}\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 4>::load(const nv_bfloat16* ptr) {\n data = *((uint2*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 4>::store(nv_bfloat16* ptr) const {\n *((uint2*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 4>::memcpy(nv_bfloat16* dst, const nv_bfloat16* src) {\n *((uint2*)dst) = *((uint2*)src);\n}\n\n// nv_bfloat16 x 8 or more\n\ntemplate <size_t vec_size>\nstruct vec_t<nv_bfloat16, vec_size> {\n uint4 data[vec_size / 8];\n\n FLASHINFER_INLINE nv_bfloat16& operator[](size_t i) { return ((nv_bfloat16*)data)[i]; }\n FLASHINFER_INLINE const nv_bfloat16& operator[](size_t i) const {\n return ((const nv_bfloat16*)data)[i];\n }\n FLASHINFER_INLINE nv_bfloat16* ptr() { return reinterpret_cast<nv_bfloat16*>(&data); }\n FLASHINFER_INLINE void fill(nv_bfloat16 val) {\n#pragma unoll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n *(nv_bfloat162*)(&(data[i].x)) = make_bfloat162(val, val);\n *(nv_bfloat162*)(&(data[i].y)) = make_bfloat162(val, val);\n *(nv_bfloat162*)(&(data[i].z)) = make_bfloat162(val, val);\n *(nv_bfloat162*)(&(data[i].w)) = make_bfloat162(val, val);\n }\n }\n FLASHINFER_INLINE void load(const nv_bfloat16* ptr) {\n#pragma unoll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n data[i] = ((uint4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(nv_bfloat16* ptr) const {\n#pragma unoll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n ((uint4*)ptr)[i] = data[i];\n }\n }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(nv_bfloat16* dst, const nv_bfloat16* src) {\n#pragma unoll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n ((uint4*)dst)[i] = ((uint4*)src)[i];\n }\n }\n};\n\n/******************* vec_t<float> *******************/\n\n// float x 1\n\ntemplate <>\nstruct vec_t<float, 1> {\n float data;\n\n FLASHINFER_INLINE float& operator[](size_t i) { return ((float*)(&data))[i]; }\n FLASHINFER_INLINE const float& operator[](size_t i) const { return ((const float*)(&data))[i]; }\n FLASHINFER_INLINE float* ptr() { return reinterpret_cast<float*>(&data); }\n FLASHINFER_INLINE void fill(float val);\n FLASHINFER_INLINE void load(const float* ptr);\n FLASHINFER_INLINE void store(float* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 1>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(float* dst, const float* src);\n};\n\nFLASHINFER_INLINE void vec_t<float, 1>::fill(float val) { data = val; }\n\nFLASHINFER_INLINE void vec_t<float, 1>::load(const float* ptr) { data = *ptr; }\n\nFLASHINFER_INLINE void vec_t<float, 1>::store(float* ptr) const { *ptr = data; }\n\nFLASHINFER_INLINE void vec_t<float, 1>::memcpy(float* dst, const float* src) { *dst = *src; }\n\n// float x 2\n\ntemplate <>\nstruct vec_t<float, 2> {\n float2 data;\n\n FLASHINFER_INLINE float& operator[](size_t i) { return ((float*)(&data))[i]; }\n FLASHINFER_INLINE const float& operator[](size_t i) const { return ((const float*)(&data))[i]; }\n FLASHINFER_INLINE float* ptr() { return reinterpret_cast<float*>(&data); }\n FLASHINFER_INLINE void fill(float val);\n FLASHINFER_INLINE void load(const float* ptr);\n FLASHINFER_INLINE void store(float* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 2>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(float* dst, const float* src);\n};\n\nFLASHINFER_INLINE void vec_t<float, 2>::fill(float val) { data = make_float2(val, val); }\n\nFLASHINFER_INLINE void vec_t<float, 2>::load(const float* ptr) { data = *((float2*)ptr); }\n\nFLASHINFER_INLINE void vec_t<float, 2>::store(float* ptr) const { *((float2*)ptr) = data; }\n\nFLASHINFER_INLINE void vec_t<float, 2>::memcpy(float* dst, const float* src) {\n *((float2*)dst) = *((float2*)src);\n}\n\n// float x 4 or more\ntemplate <size_t vec_size>\nstruct vec_t<float, vec_size> {\n float4 data[vec_size / 4];\n\n FLASHINFER_INLINE float& operator[](size_t i) { return ((float*)(data))[i]; }\n FLASHINFER_INLINE const float& operator[](size_t i) const { return ((const float*)(data))[i]; }\n FLASHINFER_INLINE float* ptr() { return reinterpret_cast<float*>(&data); }\n FLASHINFER_INLINE void fill(float val) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 4; ++i) {\n data[i] = make_float4(val, val, val, val);\n }\n }\n FLASHINFER_INLINE void load(const float* ptr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 4; ++i) {\n data[i] = ((float4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(float* ptr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 4; ++i) {\n ((float4*)ptr)[i] = data[i];\n }\n }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(float* dst, const float* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 4; ++i) {\n ((float4*)dst)[i] = ((float4*)src)[i];\n }\n }\n};\n\n} // namespace flashinfer\n\n#endif // VEC_DTYPES_CUH_\n"},"after_code":{"kind":"string","value":"/*\n * Copyright (c) 2023 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef VEC_DTYPES_CUH_\n#define VEC_DTYPES_CUH_\n\n#include <cuda_bf16.h>\n#include <cuda_fp16.h>\n#include <cuda_fp8.h>\n#include <cuda_runtime.h>\n\n#include <type_traits>\n\nnamespace flashinfer {\n\n#if (!defined(__CUDA_ARCH__) || (__CUDA_ARCH__ >= 900))\n#define FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n#endif\n\n#define FLASHINFER_INLINE inline __attribute__((always_inline)) __device__\n\n/******************* vec_t type cast *******************/\n\ntemplate <typename dst_t, typename src_t>\nstruct vec_cast {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(dst_t* dst, const src_t* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size; ++i) {\n dst[i] = (dst_t)src[i];\n }\n }\n};\n\ntemplate <>\nstruct vec_cast<float, half> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(float* dst, const half* src) {\n if constexpr (vec_size == 1) {\n dst[0] = (float)src[0];\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n ((float2*)dst)[i] = __half22float2(((half2*)src)[i]);\n }\n }\n }\n};\n\ntemplate <>\nstruct vec_cast<half, float> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(half* dst, const float* src) {\n if constexpr (vec_size == 1) {\n dst[0] = __float2half(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n ((half2*)dst)[i] = __float22half2_rn(((float2*)src)[i]);\n }\n }\n }\n};\n\ntemplate <typename T>\nconstexpr FLASHINFER_INLINE int get_exponent_bits() {\n if constexpr (std::is_same<T, __nv_fp8_e4m3>::value) {\n return 4;\n } else if constexpr (std::is_same<T, __nv_fp8_e5m2>::value) {\n return 5;\n } else if constexpr (std::is_same<T, half>::value) {\n return 5;\n } else if constexpr (std::is_same<T, nv_bfloat16>::value) {\n return 8;\n }\n}\n\ntemplate <typename T>\nconstexpr FLASHINFER_INLINE int get_mantissa_bits() {\n if constexpr (std::is_same<T, __nv_fp8_e4m3>::value) {\n return 3;\n } else if constexpr (std::is_same<T, __nv_fp8_e5m2>::value) {\n return 2;\n } else if constexpr (std::is_same<T, half>::value) {\n return 11;\n } else if constexpr (std::is_same<T, nv_bfloat16>::value) {\n return 7;\n }\n}\n\n/*!\n * \\brief Fallback to software fast dequant implementation if hardware dequantization is not\n * available.\n * \\note Inspired by Marlin's fast dequantization, but here we don't have to permute\n * weights order.\n * \\ref\n * https://github.com/vllm-project/vllm/blob/6dffa4b0a6120159ef2fe44d695a46817aff65bc/csrc/quantization/fp8/fp8_marlin.cu#L120\n */\ntemplate <typename fp8_dtype, typename fp16_dtype>\n__device__ void fast_dequant_f8f16x4(uint32_t* input, uint2* output) {\n uint32_t q = *input;\n if constexpr (std::is_same<fp8_dtype, __nv_fp8_e5m2>::value &&\n std::is_same<fp16_dtype, half>::value) {\n output->x = __byte_perm(0U, q, 0x5140);\n output->y = __byte_perm(0U, q, 0x7362);\n } else {\n constexpr int FP8_EXPONENT = get_exponent_bits<fp8_dtype>();\n constexpr int FP8_MANTISSA = get_mantissa_bits<fp8_dtype>();\n constexpr int FP16_EXPONENT = get_exponent_bits<fp16_dtype>();\n\n constexpr int RIGHT_SHIFT = FP16_EXPONENT - FP8_EXPONENT;\n // Calculate MASK for extracting mantissa and exponent\n constexpr int MASK1 = 0x80000000;\n constexpr int MASK2 = MASK1 >> (FP8_EXPONENT + FP8_MANTISSA);\n constexpr int MASK3 = MASK2 & 0x7fffffff;\n constexpr int MASK = MASK3 | (MASK3 >> 16);\n q = __byte_perm(q, q, 0x1302);\n\n // Extract and shift FP8 values to FP16 format\n uint32_t Out1 = (q & 0x80008000) | ((q & MASK) >> RIGHT_SHIFT);\n uint32_t Out2 = ((q << 8) & 0x80008000) | (((q << 8) & MASK) >> RIGHT_SHIFT);\n\n constexpr int BIAS_OFFSET = (1 << (FP16_EXPONENT - 1)) - (1 << (FP8_EXPONENT - 1));\n // Construct and apply exponent bias\n if constexpr (std::is_same<fp16_dtype, half>::value) {\n const half2 bias_reg = __float2half2_rn(float(1 << BIAS_OFFSET));\n\n // Convert to half2 and apply bias\n *(half2*)&(output->x) = __hmul2(*reinterpret_cast<const half2*>(&Out1), bias_reg);\n *(half2*)&(output->y) = __hmul2(*reinterpret_cast<const half2*>(&Out2), bias_reg);\n } else {\n constexpr uint32_t BIAS = (BIAS_OFFSET + 127) << 23;\n const nv_bfloat162 bias_reg = __float2bfloat162_rn(*reinterpret_cast<const float*>(&BIAS));\n // Convert to bfloat162 and apply bias\n *(nv_bfloat162*)&(output->x) =\n __hmul2(*reinterpret_cast<const nv_bfloat162*>(&Out1), bias_reg);\n *(nv_bfloat162*)&(output->y) =\n __hmul2(*reinterpret_cast<const nv_bfloat162*>(&Out2), bias_reg);\n }\n }\n}\n\ntemplate <>\nstruct vec_cast<nv_bfloat16, __nv_fp8_e4m3> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(nv_bfloat16* dst, const __nv_fp8_e4m3* src) {\n if constexpr (vec_size == 1) {\n dst[0] = nv_bfloat16(src[0]);\n } else if constexpr (vec_size == 2) {\n dst[0] = nv_bfloat16(src[0]);\n dst[1] = nv_bfloat16(src[1]);\n } else {\n static_assert(vec_size % 4 == 0, \"vec_size must be a multiple of 4\");\n#pragma unroll\n for (uint32_t i = 0; i < vec_size / 4; ++i) {\n fast_dequant_f8f16x4<__nv_fp8_e4m3, nv_bfloat16>((uint32_t*)&src[i * 4],\n (uint2*)&dst[i * 4]);\n }\n }\n }\n};\n\ntemplate <>\nstruct vec_cast<nv_bfloat16, __nv_fp8_e5m2> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(nv_bfloat16* dst, const __nv_fp8_e5m2* src) {\n if constexpr (vec_size == 1) {\n dst[0] = nv_bfloat16(src[0]);\n } else if constexpr (vec_size == 2) {\n dst[0] = nv_bfloat16(src[0]);\n dst[1] = nv_bfloat16(src[1]);\n } else {\n static_assert(vec_size % 4 == 0, \"vec_size must be a multiple of 4\");\n#pragma unroll\n for (uint32_t i = 0; i < vec_size / 4; ++i) {\n fast_dequant_f8f16x4<__nv_fp8_e5m2, nv_bfloat16>((uint32_t*)&src[i * 4],\n (uint2*)&dst[i * 4]);\n }\n }\n }\n};\n\ntemplate <>\nstruct vec_cast<__nv_fp8_e4m3, half> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(__nv_fp8_e4m3* dst, const half* src) {\n#ifdef FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n if constexpr (vec_size == 1) {\n dst[0] = __nv_fp8_e4m3(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint16_t y;\n uint32_t x = *(uint32_t*)&src[i * 2];\n asm volatile(\"cvt.rn.satfinite.e4m3x2.f16x2 %0, %1;\" : \"=h\"(y) : \"r\"(x));\n *(uint16_t*)&dst[i * 2] = y;\n }\n }\n#else\n#pragma unroll\n for (size_t i = 0; i < vec_size; ++i) {\n dst[i] = __nv_fp8_e4m3(src[i]);\n }\n#endif // FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n }\n};\n\ntemplate <>\nstruct vec_cast<__nv_fp8_e5m2, half> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(__nv_fp8_e5m2* dst, const half* src) {\n#ifdef FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n if constexpr (vec_size == 1) {\n dst[0] = __nv_fp8_e5m2(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint16_t y;\n uint32_t x = *(uint32_t*)&src[i * 2];\n asm volatile(\"cvt.rn.satfinite.e5m2x2.f16x2 %0, %1;\" : \"=h\"(y) : \"r\"(x));\n *(uint16_t*)&dst[i * 2] = y;\n }\n }\n#else\n#pragma unroll\n for (size_t i = 0; i < vec_size; ++i) {\n dst[i] = __nv_fp8_e5m2(src[i]);\n }\n#endif // FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n }\n};\n\ntemplate <>\nstruct vec_cast<half, __nv_fp8_e4m3> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(half* dst, const __nv_fp8_e4m3* src) {\n#ifdef FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n if constexpr (vec_size == 1) {\n dst[0] = half(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint32_t y;\n uint16_t x = *(uint16_t*)&src[i * 2];\n asm volatile(\"cvt.rn.f16x2.e4m3x2 %0, %1;\" : \"=r\"(y) : \"h\"(x));\n *(uint32_t*)&dst[i * 2] = y;\n }\n }\n#else\n if constexpr (vec_size == 1) {\n dst[0] = half(src[0]);\n } else if constexpr (vec_size == 2) {\n dst[0] = half(src[0]);\n dst[1] = half(src[1]);\n } else {\n static_assert(vec_size % 4 == 0, \"vec_size must be a multiple of 4\");\n#pragma unroll\n for (uint32_t i = 0; i < vec_size / 4; ++i) {\n fast_dequant_f8f16x4<__nv_fp8_e4m3, half>((uint32_t*)&src[i * 4], (uint2*)&dst[i * 4]);\n }\n }\n#endif // FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n }\n};\n\ntemplate <>\nstruct vec_cast<half, __nv_fp8_e5m2> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(half* dst, const __nv_fp8_e5m2* src) {\n#ifdef FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n if constexpr (vec_size == 1) {\n dst[0] = half(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint32_t y;\n uint16_t x = *(uint16_t*)&src[i * 2];\n asm volatile(\"cvt.rn.f16x2.e5m2x2 %0, %1;\" : \"=r\"(y) : \"h\"(x));\n *(uint32_t*)&dst[i * 2] = y;\n }\n }\n#else\n if constexpr (vec_size == 1) {\n dst[0] = half(src[0]);\n } else if constexpr (vec_size == 2) {\n dst[0] = half(src[0]);\n dst[1] = half(src[1]);\n } else {\n static_assert(vec_size % 4 == 0, \"vec_size must be a multiple of 4\");\n#pragma unroll\n for (uint32_t i = 0; i < vec_size / 4; ++i) {\n fast_dequant_f8f16x4<__nv_fp8_e5m2, half>((uint32_t*)&src[i * 4], (uint2*)&dst[i * 4]);\n }\n }\n#endif // FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n }\n};\n\ntemplate <>\nstruct vec_cast<float, nv_bfloat16> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(float* dst, const nv_bfloat16* src) {\n if constexpr (vec_size == 1) {\n dst[0] = (float)src[0];\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n ((float2*)dst)[i] = __bfloat1622float2(((nv_bfloat162*)src)[i]);\n }\n }\n }\n};\n\ntemplate <>\nstruct vec_cast<nv_bfloat16, float> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(nv_bfloat16* dst, const float* src) {\n if constexpr (vec_size == 1) {\n dst[0] = nv_bfloat16(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n ((nv_bfloat162*)dst)[i] = __float22bfloat162_rn(((float2*)src)[i]);\n }\n }\n }\n};\n\ntemplate <typename float_t, size_t vec_size>\nstruct vec_t {\n FLASHINFER_INLINE float_t& operator[](size_t i);\n FLASHINFER_INLINE const float_t& operator[](size_t i) const;\n FLASHINFER_INLINE void fill(float_t val);\n FLASHINFER_INLINE void load(const float_t* ptr);\n FLASHINFER_INLINE void store(float_t* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src);\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr);\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const;\n FLASHINFER_INLINE static void memcpy(float_t* dst, const float_t* src);\n FLASHINFER_INLINE float_t* ptr();\n};\n\ntemplate <typename src_float_t, typename tgt_float_t, size_t vec_size>\nFLASHINFER_INLINE void cast_from_impl(vec_t<tgt_float_t, vec_size>& dst,\n const vec_t<src_float_t, vec_size>& src) {\n vec_cast<tgt_float_t, src_float_t>::cast<vec_size>(\n dst.ptr(), const_cast<vec_t<src_float_t, vec_size>*>(&src)->ptr());\n}\n\ntemplate <typename src_float_t, typename tgt_float_t, size_t vec_size>\nFLASHINFER_INLINE void cast_load_impl(vec_t<tgt_float_t, vec_size>& dst,\n const src_float_t* src_ptr) {\n if constexpr (std::is_same<src_float_t, tgt_float_t>::value) {\n dst.load(src_ptr);\n } else {\n vec_t<src_float_t, vec_size> tmp;\n tmp.load(src_ptr);\n dst.cast_from(tmp);\n }\n}\n\ntemplate <typename src_float_t, typename tgt_float_t, size_t vec_size>\nFLASHINFER_INLINE void cast_store_impl(tgt_float_t* dst_ptr,\n const vec_t<src_float_t, vec_size>& src) {\n if constexpr (std::is_same<src_float_t, tgt_float_t>::value) {\n src.store(dst_ptr);\n } else {\n vec_t<tgt_float_t, vec_size> tmp;\n tmp.cast_from(src);\n tmp.store(dst_ptr);\n }\n}\n\n/******************* vec_t<__nv_fp8_e4m3> *******************/\n\n// __nv_fp8_e4m3 x 1\ntemplate <>\nstruct vec_t<__nv_fp8_e4m3, 1> {\n __nv_fp8_e4m3 data;\n\n FLASHINFER_INLINE __nv_fp8_e4m3& operator[](size_t i) { return ((__nv_fp8_e4m3*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e4m3& operator[](size_t i) const {\n return ((const __nv_fp8_e4m3*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e4m3* ptr() { return reinterpret_cast<__nv_fp8_e4m3*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e4m3 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e4m3* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e4m3* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 1>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e4m3* dst, const __nv_fp8_e4m3* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 1>::fill(__nv_fp8_e4m3 val) { data = val; }\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 1>::load(const __nv_fp8_e4m3* ptr) { data = *ptr; }\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 1>::store(__nv_fp8_e4m3* ptr) const { *ptr = data; }\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 1>::memcpy(__nv_fp8_e4m3* dst,\n const __nv_fp8_e4m3* src) {\n *dst = *src;\n}\n\n// __nv_fp8_e4m3 x 2\ntemplate <>\nstruct vec_t<__nv_fp8_e4m3, 2> {\n __nv_fp8x2_e4m3 data;\n\n FLASHINFER_INLINE __nv_fp8_e4m3& operator[](size_t i) { return ((__nv_fp8_e4m3*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e4m3& operator[](size_t i) const {\n return ((const __nv_fp8_e4m3*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e4m3* ptr() { return reinterpret_cast<__nv_fp8_e4m3*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e4m3 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e4m3* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e4m3* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 2>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e4m3* dst, const __nv_fp8_e4m3* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 2>::fill(__nv_fp8_e4m3 val) {\n data.__x = (__nv_fp8x2_storage_t(val.__x) << 8) | __nv_fp8x2_storage_t(val.__x);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 2>::load(const __nv_fp8_e4m3* ptr) {\n data = *((__nv_fp8x2_e4m3*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 2>::store(__nv_fp8_e4m3* ptr) const {\n *((__nv_fp8x2_e4m3*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 2>::memcpy(__nv_fp8_e4m3* dst,\n const __nv_fp8_e4m3* src) {\n *((__nv_fp8x2_e4m3*)dst) = *((__nv_fp8x2_e4m3*)src);\n}\n\n// __nv_fp8_e4m3 x 4\n\ntemplate <>\nstruct vec_t<__nv_fp8_e4m3, 4> {\n __nv_fp8x4_e4m3 data;\n\n FLASHINFER_INLINE __nv_fp8_e4m3& operator[](size_t i) { return ((__nv_fp8_e4m3*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e4m3& operator[](size_t i) const {\n return ((const __nv_fp8_e4m3*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e4m3* ptr() { return reinterpret_cast<__nv_fp8_e4m3*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e4m3 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e4m3* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e4m3* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 4>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e4m3* dst, const __nv_fp8_e4m3* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 4>::fill(__nv_fp8_e4m3 val) {\n data.__x = (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 4>::load(const __nv_fp8_e4m3* ptr) {\n data = *((__nv_fp8x4_e4m3*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 4>::store(__nv_fp8_e4m3* ptr) const {\n *((__nv_fp8x4_e4m3*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 4>::memcpy(__nv_fp8_e4m3* dst,\n const __nv_fp8_e4m3* src) {\n *((__nv_fp8x4_e4m3*)dst) = *((__nv_fp8x4_e4m3*)src);\n}\n\n// __nv_fp8_e4m3 x 8\n\ntemplate <>\nstruct vec_t<__nv_fp8_e4m3, 8> {\n uint2 data;\n\n FLASHINFER_INLINE __nv_fp8_e4m3& operator[](size_t i) { return ((__nv_fp8_e4m3*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e4m3& operator[](size_t i) const {\n return ((const __nv_fp8_e4m3*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e4m3* ptr() { return reinterpret_cast<__nv_fp8_e4m3*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e4m3 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e4m3* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e4m3* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 8>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e4m3* dst, const __nv_fp8_e4m3* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 8>::fill(__nv_fp8_e4m3 val) {\n ((__nv_fp8x4_e4m3*)(&data.x))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e4m3*)(&data.y))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 8>::load(const __nv_fp8_e4m3* ptr) {\n data = *((uint2*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 8>::store(__nv_fp8_e4m3* ptr) const {\n *((uint2*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 8>::memcpy(__nv_fp8_e4m3* dst,\n const __nv_fp8_e4m3* src) {\n *((uint2*)dst) = *((uint2*)src);\n}\n\n// __nv_fp8_e4m3 x 16 or more\ntemplate <size_t vec_size>\nstruct vec_t<__nv_fp8_e4m3, vec_size> {\n uint4 data[vec_size / 16];\n\n FLASHINFER_INLINE __nv_fp8_e4m3& operator[](size_t i) { return ((__nv_fp8_e4m3*)data)[i]; }\n FLASHINFER_INLINE const __nv_fp8_e4m3& operator[](size_t i) const {\n return ((const __nv_fp8_e4m3*)data)[i];\n }\n FLASHINFER_INLINE __nv_fp8_e4m3* ptr() { return reinterpret_cast<__nv_fp8_e4m3*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e4m3 val) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((__nv_fp8x4_e4m3*)(&(data[i].x)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e4m3*)(&(data[i].y)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e4m3*)(&(data[i].z)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e4m3*)(&(data[i].w)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n }\n }\n FLASHINFER_INLINE void load(const __nv_fp8_e4m3* ptr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i] = ((uint4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(__nv_fp8_e4m3* ptr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((uint4*)ptr)[i] = data[i];\n }\n }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e4m3* dst, const __nv_fp8_e4m3* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((uint4*)dst)[i] = ((uint4*)src)[i];\n }\n }\n};\n\n/******************* vec_t<__nv_fp8_e5m2> *******************/\n\n// __nv_fp8_e5m2 x 1\ntemplate <>\nstruct vec_t<__nv_fp8_e5m2, 1> {\n __nv_fp8_e5m2 data;\n\n FLASHINFER_INLINE __nv_fp8_e5m2& operator[](size_t i) { return ((__nv_fp8_e5m2*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e5m2& operator[](size_t i) const {\n return ((const __nv_fp8_e5m2*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e5m2* ptr() { return reinterpret_cast<__nv_fp8_e5m2*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e5m2 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e5m2* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e5m2* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 1>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e5m2* dst, const __nv_fp8_e5m2* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 1>::fill(__nv_fp8_e5m2 val) { data = val; }\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 1>::load(const __nv_fp8_e5m2* ptr) { data = *ptr; }\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 1>::store(__nv_fp8_e5m2* ptr) const { *ptr = data; }\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 1>::memcpy(__nv_fp8_e5m2* dst,\n const __nv_fp8_e5m2* src) {\n *dst = *src;\n}\n\n// __nv_fp8_e5m2 x 2\ntemplate <>\nstruct vec_t<__nv_fp8_e5m2, 2> {\n __nv_fp8x2_e5m2 data;\n\n FLASHINFER_INLINE __nv_fp8_e5m2& operator[](size_t i) { return ((__nv_fp8_e5m2*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e5m2& operator[](size_t i) const {\n return ((const __nv_fp8_e5m2*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e5m2* ptr() { return reinterpret_cast<__nv_fp8_e5m2*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e5m2 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e5m2* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e5m2* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 2>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e5m2* dst, const __nv_fp8_e5m2* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 2>::fill(__nv_fp8_e5m2 val) {\n data.__x = (__nv_fp8x2_storage_t(val.__x) << 8) | __nv_fp8x2_storage_t(val.__x);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 2>::load(const __nv_fp8_e5m2* ptr) {\n data = *((__nv_fp8x2_e5m2*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 2>::store(__nv_fp8_e5m2* ptr) const {\n *((__nv_fp8x2_e5m2*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 2>::memcpy(__nv_fp8_e5m2* dst,\n const __nv_fp8_e5m2* src) {\n *((__nv_fp8x2_e5m2*)dst) = *((__nv_fp8x2_e5m2*)src);\n}\n\n// __nv_fp8_e5m2 x 4\n\ntemplate <>\nstruct vec_t<__nv_fp8_e5m2, 4> {\n __nv_fp8x4_e5m2 data;\n\n FLASHINFER_INLINE __nv_fp8_e5m2& operator[](size_t i) { return ((__nv_fp8_e5m2*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e5m2& operator[](size_t i) const {\n return ((const __nv_fp8_e5m2*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e5m2* ptr() { return reinterpret_cast<__nv_fp8_e5m2*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e5m2 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e5m2* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e5m2* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 4>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e5m2* dst, const __nv_fp8_e5m2* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 4>::fill(__nv_fp8_e5m2 val) {\n data.__x = (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 4>::load(const __nv_fp8_e5m2* ptr) {\n data = *((__nv_fp8x4_e5m2*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 4>::store(__nv_fp8_e5m2* ptr) const {\n *((__nv_fp8x4_e5m2*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 4>::memcpy(__nv_fp8_e5m2* dst,\n const __nv_fp8_e5m2* src) {\n *((__nv_fp8x4_e5m2*)dst) = *((__nv_fp8x4_e5m2*)src);\n}\n\n// __nv_fp8_e5m2 x 8\n\ntemplate <>\nstruct vec_t<__nv_fp8_e5m2, 8> {\n uint2 data;\n\n FLASHINFER_INLINE __nv_fp8_e5m2& operator[](size_t i) { return ((__nv_fp8_e5m2*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e5m2& operator[](size_t i) const {\n return ((const __nv_fp8_e5m2*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e5m2* ptr() { return reinterpret_cast<__nv_fp8_e5m2*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e5m2 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e5m2* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e5m2* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 8>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e5m2* dst, const __nv_fp8_e5m2* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 8>::fill(__nv_fp8_e5m2 val) {\n ((__nv_fp8x4_e5m2*)(&data.x))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e5m2*)(&data.y))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 8>::load(const __nv_fp8_e5m2* ptr) {\n data = *((uint2*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 8>::store(__nv_fp8_e5m2* ptr) const {\n *((uint2*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 8>::memcpy(__nv_fp8_e5m2* dst,\n const __nv_fp8_e5m2* src) {\n *((uint2*)dst) = *((uint2*)src);\n}\n\n// __nv_fp8_e5m2 x 16 or more\n\ntemplate <size_t vec_size>\nstruct vec_t<__nv_fp8_e5m2, vec_size> {\n uint4 data[vec_size / 16];\n\n FLASHINFER_INLINE __nv_fp8_e5m2& operator[](size_t i) { return ((__nv_fp8_e5m2*)data)[i]; }\n FLASHINFER_INLINE const __nv_fp8_e5m2& operator[](size_t i) const {\n return ((const __nv_fp8_e5m2*)data)[i];\n }\n FLASHINFER_INLINE __nv_fp8_e5m2* ptr() { return reinterpret_cast<__nv_fp8_e5m2*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e5m2 val) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((__nv_fp8x4_e5m2*)(&(data[i].x)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e5m2*)(&(data[i].y)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e5m2*)(&(data[i].z)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e5m2*)(&(data[i].w)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n }\n }\n FLASHINFER_INLINE void load(const __nv_fp8_e5m2* ptr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i] = ((uint4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(__nv_fp8_e5m2* ptr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((uint4*)ptr)[i] = data[i];\n }\n }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e5m2* dst, const __nv_fp8_e5m2* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((uint4*)dst)[i] = ((uint4*)src)[i];\n }\n }\n};\n\n/******************* vec_t<half> *******************/\n\n// half x 1\ntemplate <>\nstruct vec_t<half, 1> {\n half data;\n\n FLASHINFER_INLINE half& operator[](size_t i) { return ((half*)(&data))[i]; }\n FLASHINFER_INLINE const half& operator[](size_t i) const { return ((const half*)(&data))[i]; }\n FLASHINFER_INLINE half* ptr() { return reinterpret_cast<half*>(&data); }\n FLASHINFER_INLINE void fill(half val);\n FLASHINFER_INLINE void load(const half* ptr);\n FLASHINFER_INLINE void store(half* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 1>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(half* dst, const half* src);\n};\n\nFLASHINFER_INLINE void vec_t<half, 1>::fill(half val) { data = val; }\n\nFLASHINFER_INLINE void vec_t<half, 1>::load(const half* ptr) { data = *ptr; }\n\nFLASHINFER_INLINE void vec_t<half, 1>::store(half* ptr) const { *ptr = data; }\n\nFLASHINFER_INLINE void vec_t<half, 1>::memcpy(half* dst, const half* src) { *dst = *src; }\n\n// half x 2\ntemplate <>\nstruct vec_t<half, 2> {\n half2 data;\n\n FLASHINFER_INLINE half& operator[](size_t i) { return ((half*)(&data))[i]; }\n FLASHINFER_INLINE const half& operator[](size_t i) const { return ((const half*)(&data))[i]; }\n FLASHINFER_INLINE half* ptr() { return reinterpret_cast<half*>(&data); }\n FLASHINFER_INLINE void fill(half val);\n FLASHINFER_INLINE void load(const half* ptr);\n FLASHINFER_INLINE void store(half* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 2>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(half* dst, const half* src);\n};\n\nFLASHINFER_INLINE void vec_t<half, 2>::fill(half val) { data = make_half2(val, val); }\n\nFLASHINFER_INLINE void vec_t<half, 2>::load(const half* ptr) { data = *((half2*)ptr); }\n\nFLASHINFER_INLINE void vec_t<half, 2>::store(half* ptr) const { *((half2*)ptr) = data; }\n\nFLASHINFER_INLINE void vec_t<half, 2>::memcpy(half* dst, const half* src) {\n *((half2*)dst) = *((half2*)src);\n}\n\n// half x 4\n\ntemplate <>\nstruct vec_t<half, 4> {\n uint2 data;\n\n FLASHINFER_INLINE half& operator[](size_t i) { return ((half*)(&data))[i]; }\n FLASHINFER_INLINE const half& operator[](size_t i) const { return ((const half*)(&data))[i]; }\n FLASHINFER_INLINE half* ptr() { return reinterpret_cast<half*>(&data); }\n FLASHINFER_INLINE void fill(half val);\n FLASHINFER_INLINE void load(const half* ptr);\n FLASHINFER_INLINE void store(half* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 4>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(half* dst, const half* src);\n};\n\nFLASHINFER_INLINE void vec_t<half, 4>::fill(half val) {\n *(half2*)(&data.x) = make_half2(val, val);\n *(half2*)(&data.y) = make_half2(val, val);\n}\n\nFLASHINFER_INLINE void vec_t<half, 4>::load(const half* ptr) { data = *((uint2*)ptr); }\n\nFLASHINFER_INLINE void vec_t<half, 4>::store(half* ptr) const { *((uint2*)ptr) = data; }\n\nFLASHINFER_INLINE void vec_t<half, 4>::memcpy(half* dst, const half* src) {\n *((uint2*)dst) = *((uint2*)src);\n}\n\n// half x 8 or more\n\ntemplate <size_t vec_size>\nstruct vec_t<half, vec_size> {\n uint4 data[vec_size / 8];\n FLASHINFER_INLINE half& operator[](size_t i) { return ((half*)data)[i]; }\n FLASHINFER_INLINE const half& operator[](size_t i) const { return ((const half*)data)[i]; }\n FLASHINFER_INLINE half* ptr() { return reinterpret_cast<half*>(&data); }\n FLASHINFER_INLINE void fill(half val) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n *(half2*)(&(data[i].x)) = make_half2(val, val);\n *(half2*)(&(data[i].y)) = make_half2(val, val);\n *(half2*)(&(data[i].z)) = make_half2(val, val);\n *(half2*)(&(data[i].w)) = make_half2(val, val);\n }\n }\n FLASHINFER_INLINE void load(const half* ptr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n data[i] = ((uint4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(half* ptr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n ((uint4*)ptr)[i] = data[i];\n }\n }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(half* dst, const half* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n ((uint4*)dst)[i] = ((uint4*)src)[i];\n }\n }\n};\n\n/******************* vec_t<nv_bfloat16> *******************/\n\n// nv_bfloat16 x 1\ntemplate <>\nstruct vec_t<nv_bfloat16, 1> {\n nv_bfloat16 data;\n FLASHINFER_INLINE nv_bfloat16& operator[](size_t i) { return ((nv_bfloat16*)(&data))[i]; }\n FLASHINFER_INLINE const nv_bfloat16& operator[](size_t i) const {\n return ((const nv_bfloat16*)(&data))[i];\n }\n FLASHINFER_INLINE nv_bfloat16* ptr() { return reinterpret_cast<nv_bfloat16*>(&data); }\n FLASHINFER_INLINE void fill(nv_bfloat16 val);\n FLASHINFER_INLINE void load(const nv_bfloat16* ptr);\n FLASHINFER_INLINE void store(nv_bfloat16* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 1>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(nv_bfloat16* dst, const nv_bfloat16* src);\n};\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 1>::fill(nv_bfloat16 val) { data = val; }\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 1>::load(const nv_bfloat16* ptr) { data = *ptr; }\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 1>::store(nv_bfloat16* ptr) const { *ptr = data; }\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 1>::memcpy(nv_bfloat16* dst, const nv_bfloat16* src) {\n *dst = *src;\n}\n\n// nv_bfloat16 x 2\ntemplate <>\nstruct vec_t<nv_bfloat16, 2> {\n nv_bfloat162 data;\n\n FLASHINFER_INLINE nv_bfloat16& operator[](size_t i) { return ((nv_bfloat16*)(&data))[i]; }\n FLASHINFER_INLINE const nv_bfloat16& operator[](size_t i) const {\n return ((const nv_bfloat16*)(&data))[i];\n }\n FLASHINFER_INLINE nv_bfloat16* ptr() { return reinterpret_cast<nv_bfloat16*>(&data); }\n FLASHINFER_INLINE void fill(nv_bfloat16 val);\n FLASHINFER_INLINE void load(const nv_bfloat16* ptr);\n FLASHINFER_INLINE void store(nv_bfloat16* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 2>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(nv_bfloat16* dst, const nv_bfloat16* src);\n};\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 2>::fill(nv_bfloat16 val) {\n data = make_bfloat162(val, val);\n}\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 2>::load(const nv_bfloat16* ptr) {\n data = *((nv_bfloat162*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 2>::store(nv_bfloat16* ptr) const {\n *((nv_bfloat162*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 2>::memcpy(nv_bfloat16* dst, const nv_bfloat16* src) {\n *((nv_bfloat162*)dst) = *((nv_bfloat162*)src);\n}\n\n// nv_bfloat16 x 4\n\ntemplate <>\nstruct vec_t<nv_bfloat16, 4> {\n uint2 data;\n\n FLASHINFER_INLINE nv_bfloat16& operator[](size_t i) { return ((nv_bfloat16*)(&data))[i]; }\n FLASHINFER_INLINE const nv_bfloat16& operator[](size_t i) const {\n return ((const nv_bfloat16*)(&data))[i];\n }\n FLASHINFER_INLINE nv_bfloat16* ptr() { return reinterpret_cast<nv_bfloat16*>(&data); }\n FLASHINFER_INLINE void fill(nv_bfloat16 val);\n FLASHINFER_INLINE void load(const nv_bfloat16* ptr);\n FLASHINFER_INLINE void store(nv_bfloat16* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 4>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(nv_bfloat16* dst, const nv_bfloat16* src);\n};\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 4>::fill(nv_bfloat16 val) {\n *(nv_bfloat162*)(&data.x) = make_bfloat162(val, val);\n *(nv_bfloat162*)(&data.y) = make_bfloat162(val, val);\n}\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 4>::load(const nv_bfloat16* ptr) {\n data = *((uint2*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 4>::store(nv_bfloat16* ptr) const {\n *((uint2*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 4>::memcpy(nv_bfloat16* dst, const nv_bfloat16* src) {\n *((uint2*)dst) = *((uint2*)src);\n}\n\n// nv_bfloat16 x 8 or more\n\ntemplate <size_t vec_size>\nstruct vec_t<nv_bfloat16, vec_size> {\n uint4 data[vec_size / 8];\n\n FLASHINFER_INLINE nv_bfloat16& operator[](size_t i) { return ((nv_bfloat16*)data)[i]; }\n FLASHINFER_INLINE const nv_bfloat16& operator[](size_t i) const {\n return ((const nv_bfloat16*)data)[i];\n }\n FLASHINFER_INLINE nv_bfloat16* ptr() { return reinterpret_cast<nv_bfloat16*>(&data); }\n FLASHINFER_INLINE void fill(nv_bfloat16 val) {\n#pragma unoll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n *(nv_bfloat162*)(&(data[i].x)) = make_bfloat162(val, val);\n *(nv_bfloat162*)(&(data[i].y)) = make_bfloat162(val, val);\n *(nv_bfloat162*)(&(data[i].z)) = make_bfloat162(val, val);\n *(nv_bfloat162*)(&(data[i].w)) = make_bfloat162(val, val);\n }\n }\n FLASHINFER_INLINE void load(const nv_bfloat16* ptr) {\n#pragma unoll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n data[i] = ((uint4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(nv_bfloat16* ptr) const {\n#pragma unoll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n ((uint4*)ptr)[i] = data[i];\n }\n }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(nv_bfloat16* dst, const nv_bfloat16* src) {\n#pragma unoll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n ((uint4*)dst)[i] = ((uint4*)src)[i];\n }\n }\n};\n\n/******************* vec_t<float> *******************/\n\n// float x 1\n\ntemplate <>\nstruct vec_t<float, 1> {\n float data;\n\n FLASHINFER_INLINE float& operator[](size_t i) { return ((float*)(&data))[i]; }\n FLASHINFER_INLINE const float& operator[](size_t i) const { return ((const float*)(&data))[i]; }\n FLASHINFER_INLINE float* ptr() { return reinterpret_cast<float*>(&data); }\n FLASHINFER_INLINE void fill(float val);\n FLASHINFER_INLINE void load(const float* ptr);\n FLASHINFER_INLINE void store(float* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 1>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(float* dst, const float* src);\n};\n\nFLASHINFER_INLINE void vec_t<float, 1>::fill(float val) { data = val; }\n\nFLASHINFER_INLINE void vec_t<float, 1>::load(const float* ptr) { data = *ptr; }\n\nFLASHINFER_INLINE void vec_t<float, 1>::store(float* ptr) const { *ptr = data; }\n\nFLASHINFER_INLINE void vec_t<float, 1>::memcpy(float* dst, const float* src) { *dst = *src; }\n\n// float x 2\n\ntemplate <>\nstruct vec_t<float, 2> {\n float2 data;\n\n FLASHINFER_INLINE float& operator[](size_t i) { return ((float*)(&data))[i]; }\n FLASHINFER_INLINE const float& operator[](size_t i) const { return ((const float*)(&data))[i]; }\n FLASHINFER_INLINE float* ptr() { return reinterpret_cast<float*>(&data); }\n FLASHINFER_INLINE void fill(float val);\n FLASHINFER_INLINE void load(const float* ptr);\n FLASHINFER_INLINE void store(float* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 2>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(float* dst, const float* src);\n};\n\nFLASHINFER_INLINE void vec_t<float, 2>::fill(float val) { data = make_float2(val, val); }\n\nFLASHINFER_INLINE void vec_t<float, 2>::load(const float* ptr) { data = *((float2*)ptr); }\n\nFLASHINFER_INLINE void vec_t<float, 2>::store(float* ptr) const { *((float2*)ptr) = data; }\n\nFLASHINFER_INLINE void vec_t<float, 2>::memcpy(float* dst, const float* src) {\n *((float2*)dst) = *((float2*)src);\n}\n\n// float x 4 or more\ntemplate <size_t vec_size>\nstruct vec_t<float, vec_size> {\n float4 data[vec_size / 4];\n\n FLASHINFER_INLINE float& operator[](size_t i) { return ((float*)(data))[i]; }\n FLASHINFER_INLINE const float& operator[](size_t i) const { return ((const float*)(data))[i]; }\n FLASHINFER_INLINE float* ptr() { return reinterpret_cast<float*>(&data); }\n FLASHINFER_INLINE void fill(float val) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 4; ++i) {\n data[i] = make_float4(val, val, val, val);\n }\n }\n FLASHINFER_INLINE void load(const float* ptr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 4; ++i) {\n data[i] = ((float4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(float* ptr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 4; ++i) {\n ((float4*)ptr)[i] = data[i];\n }\n }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(float* dst, const float* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 4; ++i) {\n ((float4*)dst)[i] = ((float4*)src)[i];\n }\n }\n};\n\n} // namespace flashinfer\n\n#endif // VEC_DTYPES_CUH_\n"},"diff":{"kind":"string","value":"--- include/flashinfer/vec_dtypes.cuh\n+++ include/flashinfer/vec_dtypes.cuh\n@@ -126,7 +126,6 @@\n constexpr int MASK2 = MASK1 >> (FP8_EXPONENT + FP8_MANTISSA);\n constexpr int MASK3 = MASK2 & 0x7fffffff;\n constexpr int MASK = MASK3 | (MASK3 >> 16);\n- // Final MASK value: 0x7F007F00\n q = __byte_perm(q, q, 0x1302);\n \n // Extract and shift FP8 values to FP16 format"},"lines_added":{"kind":"number","value":0,"string":"0"},"lines_removed":{"kind":"number","value":1,"string":"1"},"files_in_commit":{"kind":"number","value":2,"string":"2"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (include/flashinfer/vec_dtypes.cuh).\n\nGoal: perf: slight optimization on fragment layout swizzle\nTarget hardware: unspecified\nTarget models: unspecified\n\nCurrent file:\n```cuda\n/*\n * Copyright (c) 2023 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef VEC_DTYPES_CUH_\n#define VEC_DTYPES_CUH_\n\n#include <cuda_bf16.h>\n#include <cuda_fp16.h>\n#include <cuda_fp8.h>\n#include <cuda_runtime.h>\n\n#include <type_traits>\n\nnamespace flashinfer {\n\n#if (!defined(__CUDA_ARCH__) || (__CUDA_ARCH__ >= 900))\n#define FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n#endif\n\n#define FLASHINFER_INLINE inline __attribute__((always_inline)) __device__\n\n/******************* vec_t type cast *******************/\n\ntemplate <typename dst_t, typename src_t>\nstruct vec_cast {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(dst_t* dst, const src_t* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size; ++i) {\n dst[i] = (dst_t)src[i];\n }\n }\n};\n\ntemplate <>\nstruct vec_cast<float, half> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(float* dst, const half* src) {\n if constexpr (vec_size == 1) {\n dst[0] = (float)src[0];\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n ((float2*)dst)[i] = __half22float2(((half2*)src)[i]);\n }\n }\n }\n};\n\ntemplate <>\nstruct vec_cast<half, float> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(half* dst, const float* src) {\n if constexpr (vec_size == 1) {\n dst[0] = __float2half(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n ((half2*)dst)[i] = __float22half2_rn(((float2*)src)[i]);\n }\n }\n }\n};\n\ntemplate <typename T>\nconstexpr FLASHINFER_INLINE int get_exponent_bits() {\n if constexpr (std::is_same<T, __nv_fp8_e4m3>::value) {\n return 4;\n } else if constexpr (std::is_same<T, __nv_fp8_e5m2>::value) {\n return 5;\n } else if constexpr (std::is_same<T, half>::value) {\n return 5;\n } else if constexpr (std::is_same<T, nv_bfloat16>::value) {\n return 8;\n }\n}\n\ntemplate <typename T>\nconstexpr FLASHINFER_INLINE int get_mantissa_bits() {\n if constexpr (std::is_same<T, __nv_fp8_e4m3>::value) {\n return 3;\n } else if constexpr (std::is_same<T, __nv_fp8_e5m2>::value) {\n return 2;\n } else if constexpr (std::is_same<T, half>::value) {\n return 11;\n } else if constexpr (std::is_same<T, nv_bfloat16>::value) {\n return 7;\n }\n}\n\n/*!\n * \\brief Fallback to software fast dequant implementation if hardware dequantization is not\n * available.\n * \\note Inspired by Marlin's fast dequantization, but here we don't have to permute\n * weights order.\n * \\ref\n * https://github.com/vllm-project/vllm/blob/6dffa4b0a6120159ef2fe44d695a46817aff65bc/csrc/quantization/fp8/fp8_marlin.cu#L120\n */\ntemplate <typename fp8_dtype, typename fp16_dtype>\n__device__ void fast_dequant_f8f16x4(uint32_t* input, uint2* output) {\n uint32_t q = *input;\n if constexpr (std::is_same<fp8_dtype, __nv_fp8_e5m2>::value &&\n std::is_same<fp16_dtype, half>::value) {\n output->x = __byte_perm(0U, q, 0x5140);\n output->y = __byte_perm(0U, q, 0x7362);\n } else {\n constexpr int FP8_EXPONENT = get_exponent_bits<fp8_dtype>();\n constexpr int FP8_MANTISSA = get_mantissa_bits<fp8_dtype>();\n constexpr int FP16_EXPONENT = get_exponent_bits<fp16_dtype>();\n\n constexpr int RIGHT_SHIFT = FP16_EXPONENT - FP8_EXPONENT;\n // Calculate MASK for extracting mantissa and exponent\n constexpr int MASK1 = 0x80000000;\n constexpr int MASK2 = MASK1 >> (FP8_EXPONENT + FP8_MANTISSA);\n constexpr int MASK3 = MASK2 & 0x7fffffff;\n constexpr int MASK = MASK3 | (MASK3 >> 16);\n // Final MASK value: 0x7F007F00\n q = __byte_perm(q, q, 0x1302);\n\n // Extract and shift FP8 values to FP16 format\n uint32_t Out1 = (q & 0x80008000) | ((q & MASK) >> RIGHT_SHIFT);\n uint32_t Out2 = ((q << 8) & 0x80008000) | (((q << 8) & MASK) >> RIGHT_SHIFT);\n\n constexpr int BIAS_OFFSET = (1 << (FP16_EXPONENT - 1)) - (1 << (FP8_EXPONENT - 1));\n // Construct and apply exponent bias\n if constexpr (std::is_same<fp16_dtype, half>::value) {\n const half2 bias_reg = __float2half2_rn(float(1 << BIAS_OFFSET));\n\n // Convert to half2 and apply bias\n *(half2*)&(output->x) = __hmul2(*reinterpret_cast<const half2*>(&Out1), bias_reg);\n *(half2*)&(output->y) = __hmul2(*reinterpret_cast<const half2*>(&Out2), bias_reg);\n } else {\n constexpr uint32_t BIAS = (BIAS_OFFSET + 127) << 23;\n const nv_bfloat162 bias_reg = __float2bfloat162_rn(*reinterpret_cast<const float*>(&BIAS));\n // Convert to bfloat162 and apply bias\n *(nv_bfloat162*)&(output->x) =\n __hmul2(*reinterpret_cast<const nv_bfloat162*>(&Out1), bias_reg);\n *(nv_bfloat162*)&(output->y) =\n __hmul2(*reinterpret_cast<const nv_bfloat162*>(&Out2), bias_reg);\n }\n }\n}\n\ntemplate <>\nstruct vec_cast<nv_bfloat16, __nv_fp8_e4m3> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(nv_bfloat16* dst, const __nv_fp8_e4m3* src) {\n if constexpr (vec_size == 1) {\n dst[0] = nv_bfloat16(src[0]);\n } else if constexpr (vec_size == 2) {\n dst[0] = nv_bfloat16(src[0]);\n dst[1] = nv_bfloat16(src[1]);\n } else {\n static_assert(vec_size % 4 == 0, \"vec_size must be a multiple of 4\");\n#pragma unroll\n for (uint32_t i = 0; i < vec_size / 4; ++i) {\n fast_dequant_f8f16x4<__nv_fp8_e4m3, nv_bfloat16>((uint32_t*)&src[i * 4],\n (uint2*)&dst[i * 4]);\n }\n }\n }\n};\n\ntemplate <>\nstruct vec_cast<nv_bfloat16, __nv_fp8_e5m2> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(nv_bfloat16* dst, const __nv_fp8_e5m2* src) {\n if constexpr (vec_size == 1) {\n dst[0] = nv_bfloat16(src[0]);\n } else if constexpr (vec_size == 2) {\n dst[0] = nv_bfloat16(src[0]);\n dst[1] = nv_bfloat16(src[1]);\n } else {\n static_assert(vec_size % 4 == 0, \"vec_size must be a multiple of 4\");\n#pragma unroll\n for (uint32_t i = 0; i < vec_size / 4; ++i) {\n fast_dequant_f8f16x4<__nv_fp8_e5m2, nv_bfloat16>((uint32_t*)&src[i * 4],\n (uint2*)&dst[i * 4]);\n }\n }\n }\n};\n\ntemplate <>\nstruct vec_cast<__nv_fp8_e4m3, half> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(__nv_fp8_e4m3* dst, const half* src) {\n#ifdef FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n if constexpr (vec_size == 1) {\n dst[0] = __nv_fp8_e4m3(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint16_t y;\n uint32_t x = *(uint32_t*)&src[i * 2];\n asm volatile(\"cvt.rn.satfinite.e4m3x2.f16x2 %0, %1;\" : \"=h\"(y) : \"r\"(x));\n *(uint16_t*)&dst[i * 2] = y;\n }\n }\n#else\n#pragma unroll\n for (size_t i = 0; i < vec_size; ++i) {\n dst[i] = __nv_fp8_e4m3(src[i]);\n }\n#endif // FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n }\n};\n\ntemplate <>\nstruct vec_cast<__nv_fp8_e5m2, half> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(__nv_fp8_e5m2* dst, const half* src) {\n#ifdef FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n if constexpr (vec_size == 1) {\n dst[0] = __nv_fp8_e5m2(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint16_t y;\n uint32_t x = *(uint32_t*)&src[i * 2];\n asm volatile(\"cvt.rn.satfinite.e5m2x2.f16x2 %0, %1;\" : \"=h\"(y) : \"r\"(x));\n *(uint16_t*)&dst[i * 2] = y;\n }\n }\n#else\n#pragma unroll\n for (size_t i = 0; i < vec_size; ++i) {\n dst[i] = __nv_fp8_e5m2(src[i]);\n }\n#endif // FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n }\n};\n\ntemplate <>\nstruct vec_cast<half, __nv_fp8_e4m3> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(half* dst, const __nv_fp8_e4m3* src) {\n#ifdef FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n if constexpr (vec_size == 1) {\n dst[0] = half(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint32_t y;\n uint16_t x = *(uint16_t*)&src[i * 2];\n asm volatile(\"cvt.rn.f16x2.e4m3x2 %0, %1;\" : \"=r\"(y) : \"h\"(x));\n *(uint32_t*)&dst[i * 2] = y;\n }\n }\n#else\n if constexpr (vec_size == 1) {\n dst[0] = half(src[0]);\n } else if constexpr (vec_size == 2) {\n dst[0] = half(src[0]);\n dst[1] = half(src[1]);\n } else {\n static_assert(vec_size % 4 == 0, \"vec_size must be a multiple of 4\");\n#pragma unroll\n for (uint32_t i = 0; i < vec_size / 4; ++i) {\n fast_dequant_f8f16x4<__nv_fp8_e4m3, half>((uint32_t*)&src[i * 4], (uint2*)&dst[i * 4]);\n }\n }\n#endif // FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n }\n};\n\ntemplate <>\nstruct vec_cast<half, __nv_fp8_e5m2> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(half* dst, const __nv_fp8_e5m2* src) {\n#ifdef FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n if constexpr (vec_size == 1) {\n dst[0] = half(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint32_t y;\n uint16_t x = *(uint16_t*)&src[i * 2];\n asm volatile(\"cvt.rn.f16x2.e5m2x2 %0, %1;\" : \"=r\"(y) : \"h\"(x));\n *(uint32_t*)&dst[i * 2] = y;\n }\n }\n#else\n if constexpr (vec_size == 1) {\n dst[0] = half(src[0]);\n } else if constexpr (vec_size == 2) {\n dst[0] = half(src[0]);\n dst[1] = half(src[1]);\n } else {\n static_assert(vec_size % 4 == 0, \"vec_size must be a multiple of 4\");\n#pragma unroll\n for (uint32_t i = 0; i < vec_size / 4; ++i) {\n fast_dequant_f8f16x4<__nv_fp8_e5m2, half>((uint32_t*)&src[i * 4], (uint2*)&dst[i * 4]);\n }\n }\n#endif // FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n }\n};\n\ntemplate <>\nstruct vec_cast<float, nv_bfloat16> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(float* dst, const nv_bfloat16* src) {\n if constexpr (vec_size == 1) {\n dst[0] = (float)src[0];\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n ((float2*)dst)[i] = __bfloat1622float2(((nv_bfloat162*)src)[i]);\n }\n }\n }\n};\n\ntemplate <>\nstruct vec_cast<nv_bfloat16, float> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(nv_bfloat16* dst, const float* src) {\n if constexpr (vec_size == 1) {\n dst[0] = nv_bfloat16(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n ((nv_bfloat162*)dst)[i] = __float22bfloat162_rn(((float2*)src)[i]);\n }\n }\n }\n};\n\ntemplate <typename float_t, size_t vec_size>\nstruct vec_t {\n FLASHINFER_INLINE float_t& operator[](size_t i);\n FLASHINFER_INLINE const float_t& operator[](size_t i) const;\n FLASHINFER_INLINE void fill(float_t val);\n FLASHINFER_INLINE void load(const float_t* ptr);\n FLASHINFER_INLINE void store(float_t* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src);\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr);\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const;\n FLASHINFER_INLINE static void memcpy(float_t* dst, const float_t* src);\n FLASHINFER_INLINE float_t* ptr();\n};\n\ntemplate <typename src_float_t, typename tgt_float_t, size_t vec_size>\nFLASHINFER_INLINE void cast_from_impl(vec_t<tgt_float_t, vec_size>& dst,\n const vec_t<src_float_t, vec_size>& src) {\n vec_cast<tgt_float_t, src_float_t>::cast<vec_size>(\n dst.ptr(), const_cast<vec_t<src_float_t, vec_size>*>(&src)->ptr());\n}\n\ntemplate <typename src_float_t, typename tgt_float_t, size_t vec_size>\nFLASHINFER_INLINE void cast_load_impl(vec_t<tgt_float_t, vec_size>& dst,\n const src_float_t* src_ptr) {\n if constexpr (std::is_same<src_float_t, tgt_float_t>::value) {\n dst.load(src_ptr);\n } else {\n vec_t<src_float_t, vec_size> tmp;\n tmp.load(src_ptr);\n dst.cast_from(tmp);\n }\n}\n\ntemplate <typename src_float_t, typename tgt_float_t, size_t vec_size>\nFLASHINFER_INLINE void cast_store_impl(tgt_float_t* dst_ptr,\n const vec_t<src_float_t, vec_size>& src) {\n if constexpr (std::is_same<src_float_t, tgt_float_t>::value) {\n src.store(dst_ptr);\n } else {\n vec_t<tgt_float_t, vec_size> tmp;\n tmp.cast_from(src);\n tmp.store(dst_ptr);\n }\n}\n\n/******************* vec_t<__nv_fp8_e4m3> *******************/\n\n// __nv_fp8_e4m3 x 1\ntemplate <>\nstruct vec_t<__nv_fp8_e4m3, 1> {\n __nv_fp8_e4m3 data;\n\n FLASHINFER_INLINE __nv_fp8_e4m3& operator[](size_t i) { return ((__nv_fp8_e4m3*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e4m3& operator[](size_t i) const {\n return ((const __nv_fp8_e4m3*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e4m3* ptr() { return reinterpret_cast<__nv_fp8_e4m3*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e4m3 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e4m3* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e4m3* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 1>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e4m3* dst, const __nv_fp8_e4m3* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 1>::fill(__nv_fp8_e4m3 val) { data = val; }\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 1>::load(const __nv_fp8_e4m3* ptr) { data = *ptr; }\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 1>::store(__nv_fp8_e4m3* ptr) const { *ptr = data; }\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 1>::memcpy(__nv_fp8_e4m3* dst,\n const __nv_fp8_e4m3* src) {\n *dst = *src;\n}\n\n// __nv_fp8_e4m3 x 2\ntemplate <>\nstruct vec_t<__nv_fp8_e4m3, 2> {\n __nv_fp8x2_e4m3 data;\n\n FLASHINFER_INLINE __nv_fp8_e4m3& operator[](size_t i) { return ((__nv_fp8_e4m3*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e4m3& operator[](size_t i) const {\n return ((const __nv_fp8_e4m3*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e4m3* ptr() { return reinterpret_cast<__nv_fp8_e4m3*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e4m3 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e4m3* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e4m3* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 2>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e4m3* dst, const __nv_fp8_e4m3* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 2>::fill(__nv_fp8_e4m3 val) {\n data.__x = (__nv_fp8x2_storage_t(val.__x) << 8) | __nv_fp8x2_storage_t(val.__x);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 2>::load(const __nv_fp8_e4m3* ptr) {\n data = *((__nv_fp8x2_e4m3*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 2>::store(__nv_fp8_e4m3* ptr) const {\n *((__nv_fp8x2_e4m3*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 2>::memcpy(__nv_fp8_e4m3* dst,\n const __nv_fp8_e4m3* src) {\n *((__nv_fp8x2_e4m3*)dst) = *((__nv_fp8x2_e4m3*)src);\n}\n\n// __nv_fp8_e4m3 x 4\n\ntemplate <>\nstruct vec_t<__nv_fp8_e4m3, 4> {\n __nv_fp8x4_e4m3 data;\n\n FLASHINFER_INLINE __nv_fp8_e4m3& operator[](size_t i) { return ((__nv_fp8_e4m3*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e4m3& operator[](size_t i) const {\n return ((const __nv_fp8_e4m3*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e4m3* ptr() { return reinterpret_cast<__nv_fp8_e4m3*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e4m3 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e4m3* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e4m3* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 4>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e4m3* dst, const __nv_fp8_e4m3* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 4>::fill(__nv_fp8_e4m3 val) {\n data.__x = (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 4>::load(const __nv_fp8_e4m3* ptr) {\n data = *((__nv_fp8x4_e4m3*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 4>::store(__nv_fp8_e4m3* ptr) const {\n *((__nv_fp8x4_e4m3*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 4>::memcpy(__nv_fp8_e4m3* dst,\n const __nv_fp8_e4m3* src) {\n *((__nv_fp8x4_e4m3*)dst) = *((__nv_fp8x4_e4m3*)src);\n}\n\n// __nv_fp8_e4m3 x 8\n\ntemplate <>\nstruct vec_t<__nv_fp8_e4m3, 8> {\n uint2 data;\n\n FLASHINFER_INLINE __nv_fp8_e4m3& operator[](size_t i) { return ((__nv_fp8_e4m3*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e4m3& operator[](size_t i) const {\n return ((const __nv_fp8_e4m3*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e4m3* ptr() { return reinterpret_cast<__nv_fp8_e4m3*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e4m3 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e4m3* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e4m3* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 8>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e4m3* dst, const __nv_fp8_e4m3* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 8>::fill(__nv_fp8_e4m3 val) {\n ((__nv_fp8x4_e4m3*)(&data.x))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e4m3*)(&data.y))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 8>::load(const __nv_fp8_e4m3* ptr) {\n data = *((uint2*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 8>::store(__nv_fp8_e4m3* ptr) const {\n *((uint2*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 8>::memcpy(__nv_fp8_e4m3* dst,\n const __nv_fp8_e4m3* src) {\n *((uint2*)dst) = *((uint2*)src);\n}\n\n// __nv_fp8_e4m3 x 16 or more\ntemplate <size_t vec_size>\nstruct vec_t<__nv_fp8_e4m3, vec_size> {\n uint4 data[vec_size / 16];\n\n FLASHINFER_INLINE __nv_fp8_e4m3& operator[](size_t i) { return ((__nv_fp8_e4m3*)data)[i]; }\n FLASHINFER_INLINE const __nv_fp8_e4m3& operator[](size_t i) const {\n return ((const __nv_fp8_e4m3*)data)[i];\n }\n FLASHINFER_INLINE __nv_fp8_e4m3* ptr() { return reinterpret_cast<__nv_fp8_e4m3*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e4m3 val) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((__nv_fp8x4_e4m3*)(&(data[i].x)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e4m3*)(&(data[i].y)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e4m3*)(&(data[i].z)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e4m3*)(&(data[i].w)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n }\n }\n FLASHINFER_INLINE void load(const __nv_fp8_e4m3* ptr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i] = ((uint4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(__nv_fp8_e4m3* ptr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((uint4*)ptr)[i] = data[i];\n }\n }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e4m3* dst, const __nv_fp8_e4m3* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((uint4*)dst)[i] = ((uint4*)src)[i];\n }\n }\n};\n\n/******************* vec_t<__nv_fp8_e5m2> *******************/\n\n// __nv_fp8_e5m2 x 1\ntemplate <>\nstruct vec_t<__nv_fp8_e5m2, 1> {\n __nv_fp8_e5m2 data;\n\n FLASHINFER_INLINE __nv_fp8_e5m2& operator[](size_t i) { return ((__nv_fp8_e5m2*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e5m2& operator[](size_t i) const {\n return ((const __nv_fp8_e5m2*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e5m2* ptr() { return reinterpret_cast<__nv_fp8_e5m2*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e5m2 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e5m2* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e5m2* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 1>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e5m2* dst, const __nv_fp8_e5m2* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 1>::fill(__nv_fp8_e5m2 val) { data = val; }\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 1>::load(const __nv_fp8_e5m2* ptr) { data = *ptr; }\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 1>::store(__nv_fp8_e5m2* ptr) const { *ptr = data; }\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 1>::memcpy(__nv_fp8_e5m2* dst,\n const __nv_fp8_e5m2* src) {\n *dst = *src;\n}\n\n// __nv_fp8_e5m2 x 2\ntemplate <>\nstruct vec_t<__nv_fp8_e5m2, 2> {\n __nv_fp8x2_e5m2 data;\n\n FLASHINFER_INLINE __nv_fp8_e5m2& operator[](size_t i) { return ((__nv_fp8_e5m2*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e5m2& operator[](size_t i) const {\n return ((const __nv_fp8_e5m2*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e5m2* ptr() { return reinterpret_cast<__nv_fp8_e5m2*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e5m2 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e5m2* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e5m2* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 2>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e5m2* dst, const __nv_fp8_e5m2* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 2>::fill(__nv_fp8_e5m2 val) {\n data.__x = (__nv_fp8x2_storage_t(val.__x) << 8) | __nv_fp8x2_storage_t(val.__x);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 2>::load(const __nv_fp8_e5m2* ptr) {\n data = *((__nv_fp8x2_e5m2*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 2>::store(__nv_fp8_e5m2* ptr) const {\n *((__nv_fp8x2_e5m2*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 2>::memcpy(__nv_fp8_e5m2* dst,\n const __nv_fp8_e5m2* src) {\n *((__nv_fp8x2_e5m2*)dst) = *((__nv_fp8x2_e5m2*)src);\n}\n\n// __nv_fp8_e5m2 x 4\n\ntemplate <>\nstruct vec_t<__nv_fp8_e5m2, 4> {\n __nv_fp8x4_e5m2 data;\n\n FLASHINFER_INLINE __nv_fp8_e5m2& operator[](size_t i) { return ((__nv_fp8_e5m2*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e5m2& operator[](size_t i) const {\n return ((const __nv_fp8_e5m2*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e5m2* ptr() { return reinterpret_cast<__nv_fp8_e5m2*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e5m2 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e5m2* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e5m2* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 4>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e5m2* dst, const __nv_fp8_e5m2* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 4>::fill(__nv_fp8_e5m2 val) {\n data.__x = (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 4>::load(const __nv_fp8_e5m2* ptr) {\n data = *((__nv_fp8x4_e5m2*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 4>::store(__nv_fp8_e5m2* ptr) const {\n *((__nv_fp8x4_e5m2*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 4>::memcpy(__nv_fp8_e5m2* dst,\n const __nv_fp8_e5m2* src) {\n *((__nv_fp8x4_e5m2*)dst) = *((__nv_fp8x4_e5m2*)src);\n}\n\n// __nv_fp8_e5m2 x 8\n\ntemplate <>\nstruct vec_t<__nv_fp8_e5m2, 8> {\n uint2 data;\n\n FLASHINFER_INLINE __nv_fp8_e5m2& operator[](size_t i) { return ((__nv_fp8_e5m2*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e5m2& operator[](size_t i) const {\n return ((const __nv_fp8_e5m2*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e5m2* ptr() { return reinterpret_cast<__nv_fp8_e5m2*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e5m2 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e5m2* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e5m2* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 8>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e5m2* dst, const __nv_fp8_e5m2* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 8>::fill(__nv_fp8_e5m2 val) {\n ((__nv_fp8x4_e5m2*)(&data.x))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e5m2*)(&data.y))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 8>::load(const __nv_fp8_e5m2* ptr) {\n data = *((uint2*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 8>::store(__nv_fp8_e5m2* ptr) const {\n *((uint2*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 8>::memcpy(__nv_fp8_e5m2* dst,\n const __nv_fp8_e5m2* src) {\n *((uint2*)dst) = *((uint2*)src);\n}\n\n// __nv_fp8_e5m2 x 16 or more\n\ntemplate <size_t vec_size>\nstruct vec_t<__nv_fp8_e5m2, vec_size> {\n uint4 data[vec_size / 16];\n\n FLASHINFER_INLINE __nv_fp8_e5m2& operator[](size_t i) { return ((__nv_fp8_e5m2*)data)[i]; }\n FLASHINFER_INLINE const __nv_fp8_e5m2& operator[](size_t i) const {\n return ((const __nv_fp8_e5m2*)data)[i];\n }\n FLASHINFER_INLINE __nv_fp8_e5m2* ptr() { return reinterpret_cast<__nv_fp8_e5m2*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e5m2 val) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((__nv_fp8x4_e5m2*)(&(data[i].x)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e5m2*)(&(data[i].y)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e5m2*)(&(data[i].z)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e5m2*)(&(data[i].w)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n }\n }\n FLASHINFER_INLINE void load(const __nv_fp8_e5m2* ptr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i] = ((uint4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(__nv_fp8_e5m2* ptr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((uint4*)ptr)[i] = data[i];\n }\n }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e5m2* dst, const __nv_fp8_e5m2* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((uint4*)dst)[i] = ((uint4*)src)[i];\n }\n }\n};\n\n/******************* vec_t<half> *******************/\n\n// half x 1\ntemplate <>\nstruct vec_t<half, 1> {\n half data;\n\n FLASHINFER_INLINE half& operator[](size_t i) { return ((half*)(&data))[i]; }\n FLASHINFER_INLINE const half& operator[](size_t i) const { return ((const half*)(&data))[i]; }\n FLASHINFER_INLINE half* ptr() { return reinterpret_cast<half*>(&data); }\n FLASHINFER_INLINE void fill(half val);\n FLASHINFER_INLINE void load(const half* ptr);\n FLASHINFER_INLINE void store(half* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 1>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(half* dst, const half* src);\n};\n\nFLASHINFER_INLINE void vec_t<half, 1>::fill(half val) { data = val; }\n\nFLASHINFER_INLINE void vec_t<half, 1>::load(const half* ptr) { data = *ptr; }\n\nFLASHINFER_INLINE void vec_t<half, 1>::store(half* ptr) const { *ptr = data; }\n\nFLASHINFER_INLINE void vec_t<half, 1>::memcpy(half* dst, const half* src) { *dst = *src; }\n\n// half x 2\ntemplate <>\nstruct vec_t<half, 2> {\n half2 data;\n\n FLASHINFER_INLINE half& operator[](size_t i) { return ((half*)(&data))[i]; }\n FLASHINFER_INLINE const half& operator[](size_t i) const { return ((const half*)(&data))[i]; }\n FLASHINFER_INLINE half* ptr() { return reinterpret_cast<half*>(&data); }\n FLASHINFER_INLINE void fill(half val);\n FLASHINFER_INLINE void load(const half* ptr);\n FLASHINFER_INLINE void store(half* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 2>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(half* dst, const half* src);\n};\n\nFLASHINFER_INLINE void vec_t<half, 2>::fill(half val) { data = make_half2(val, val); }\n\nFLASHINFER_INLINE void vec_t<half, 2>::load(const half* ptr) { data = *((half2*)ptr); }\n\nFLASHINFER_INLINE void vec_t<half, 2>::store(half* ptr) const { *((half2*)ptr) = data; }\n\nFLASHINFER_INLINE void vec_t<half, 2>::memcpy(half* dst, const half* src) {\n *((half2*)dst) = *((half2*)src);\n}\n\n// half x 4\n\ntemplate <>\nstruct vec_t<half, 4> {\n uint2 data;\n\n FLASHINFER_INLINE half& operator[](size_t i) { return ((half*)(&data))[i]; }\n FLASHINFER_INLINE const half& operator[](size_t i) const { return ((const half*)(&data))[i]; }\n FLASHINFER_INLINE half* ptr() { return reinterpret_cast<half*>(&data); }\n FLASHINFER_INLINE void fill(half val);\n FLASHINFER_INLINE void load(const half* ptr);\n FLASHINFER_INLINE void store(half* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 4>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(half* dst, const half* src);\n};\n\nFLASHINFER_INLINE void vec_t<half, 4>::fill(half val) {\n *(half2*)(&data.x) = make_half2(val, val);\n *(half2*)(&data.y) = make_half2(val, val);\n}\n\nFLASHINFER_INLINE void vec_t<half, 4>::load(const half* ptr) { data = *((uint2*)ptr); }\n\nFLASHINFER_INLINE void vec_t<half, 4>::store(half* ptr) const { *((uint2*)ptr) = data; }\n\nFLASHINFER_INLINE void vec_t<half, 4>::memcpy(half* dst, const half* src) {\n *((uint2*)dst) = *((uint2*)src);\n}\n\n// half x 8 or more\n\ntemplate <size_t vec_size>\nstruct vec_t<half, vec_size> {\n uint4 data[vec_size / 8];\n FLASHINFER_INLINE half& operator[](size_t i) { return ((half*)data)[i]; }\n FLASHINFER_INLINE const half& operator[](size_t i) const { return ((const half*)data)[i]; }\n FLASHINFER_INLINE half* ptr() { return reinterpret_cast<half*>(&data); }\n FLASHINFER_INLINE void fill(half val) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n *(half2*)(&(data[i].x)) = make_half2(val, val);\n *(half2*)(&(data[i].y)) = make_half2(val, val);\n *(half2*)(&(data[i].z)) = make_half2(val, val);\n *(half2*)(&(data[i].w)) = make_half2(val, val);\n }\n }\n FLASHINFER_INLINE void load(const half* ptr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n data[i] = ((uint4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(half* ptr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n ((uint4*)ptr)[i] = data[i];\n }\n }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(half* dst, const half* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n ((uint4*)dst)[i] = ((uint4*)src)[i];\n }\n }\n};\n\n/******************* vec_t<nv_bfloat16> *******************/\n\n// nv_bfloat16 x 1\ntemplate <>\nstruct vec_t<nv_bfloat16, 1> {\n nv_bfloat16 data;\n FLASHINFER_INLINE nv_bfloat16& operator[](size_t i) { return ((nv_bfloat16*)(&data))[i]; }\n FLASHINFER_INLINE const nv_bfloat16& operator[](size_t i) const {\n return ((const nv_bfloat16*)(&data))[i];\n }\n FLASHINFER_INLINE nv_bfloat16* ptr() { return reinterpret_cast<nv_bfloat16*>(&data); }\n FLASHINFER_INLINE void fill(nv_bfloat16 val);\n FLASHINFER_INLINE void load(const nv_bfloat16* ptr);\n FLASHINFER_INLINE void store(nv_bfloat16* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 1>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(nv_bfloat16* dst, const nv_bfloat16* src);\n};\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 1>::fill(nv_bfloat16 val) { data = val; }\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 1>::load(const nv_bfloat16* ptr) { data = *ptr; }\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 1>::store(nv_bfloat16* ptr) const { *ptr = data; }\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 1>::memcpy(nv_bfloat16* dst, const nv_bfloat16* src) {\n *dst = *src;\n}\n\n// nv_bfloat16 x 2\ntemplate <>\nstruct vec_t<nv_bfloat16, 2> {\n nv_bfloat162 data;\n\n FLASHINFER_INLINE nv_bfloat16& operator[](size_t i) { return ((nv_bfloat16*)(&data))[i]; }\n FLASHINFER_INLINE const nv_bfloat16& operator[](size_t i) const {\n return ((const nv_bfloat16*)(&data))[i];\n }\n FLASHINFER_INLINE nv_bfloat16* ptr() { return reinterpret_cast<nv_bfloat16*>(&data); }\n FLASHINFER_INLINE void fill(nv_bfloat16 val);\n FLASHINFER_INLINE void load(const nv_bfloat16* ptr);\n FLASHINFER_INLINE void store(nv_bfloat16* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 2>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(nv_bfloat16* dst, const nv_bfloat16* src);\n};\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 2>::fill(nv_bfloat16 val) {\n data = make_bfloat162(val, val);\n}\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 2>::load(const nv_bfloat16* ptr) {\n data = *((nv_bfloat162*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 2>::store(nv_bfloat16* ptr) const {\n *((nv_bfloat162*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 2>::memcpy(nv_bfloat16* dst, const nv_bfloat16* src) {\n *((nv_bfloat162*)dst) = *((nv_bfloat162*)src);\n}\n\n// nv_bfloat16 x 4\n\ntemplate <>\nstruct vec_t<nv_bfloat16, 4> {\n uint2 data;\n\n FLASHINFER_INLINE nv_bfloat16& operator[](size_t i) { return ((nv_bfloat16*)(&data))[i]; }\n FLASHINFER_INLINE const nv_bfloat16& operator[](size_t i) const {\n return ((const nv_bfloat16*)(&data))[i];\n }\n FLASHINFER_INLINE nv_bfloat16* ptr() { return reinterpret_cast<nv_bfloat16*>(&data); }\n FLASHINFER_INLINE void fill(nv_bfloat16 val);\n FLASHINFER_INLINE void load(const nv_bfloat16* ptr);\n FLASHINFER_INLINE void store(nv_bfloat16* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 4>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(nv_bfloat16* dst, const nv_bfloat16* src);\n};\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 4>::fill(nv_bfloat16 val) {\n *(nv_bfloat162*)(&data.x) = make_bfloat162(val, val);\n *(nv_bfloat162*)(&data.y) = make_bfloat162(val, val);\n}\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 4>::load(const nv_bfloat16* ptr) {\n data = *((uint2*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 4>::store(nv_bfloat16* ptr) const {\n *((uint2*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 4>::memcpy(nv_bfloat16* dst, const nv_bfloat16* src) {\n *((uint2*)dst) = *((uint2*)src);\n}\n\n// nv_bfloat16 x 8 or more\n\ntemplate <size_t vec_size>\nstruct vec_t<nv_bfloat16, vec_size> {\n uint4 data[vec_size / 8];\n\n FLASHINFER_INLINE nv_bfloat16& operator[](size_t i) { return ((nv_bfloat16*)data)[i]; }\n FLASHINFER_INLINE const nv_bfloat16& operator[](size_t i) const {\n return ((const nv_bfloat16*)data)[i];\n }\n FLASHINFER_INLINE nv_bfloat16* ptr() { return reinterpret_cast<nv_bfloat16*>(&data); }\n FLASHINFER_INLINE void fill(nv_bfloat16 val) {\n#pragma unoll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n *(nv_bfloat162*)(&(data[i].x)) = make_bfloat162(val, val);\n *(nv_bfloat162*)(&(data[i].y)) = make_bfloat162(val, val);\n *(nv_bfloat162*)(&(data[i].z)) = make_bfloat162(val, val);\n *(nv_bfloat162*)(&(data[i].w)) = make_bfloat162(val, val);\n }\n }\n FLASHINFER_INLINE void load(const nv_bfloat16* ptr) {\n#pragma unoll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n data[i] = ((uint4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(nv_bfloat16* ptr) const {\n#pragma unoll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n ((uint4*)ptr)[i] = data[i];\n }\n }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(nv_bfloat16* dst, const nv_bfloat16* src) {\n#pragma unoll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n ((uint4*)dst)[i] = ((uint4*)src)[i];\n }\n }\n};\n\n/******************* vec_t<float> *******************/\n\n// float x 1\n\ntemplate <>\nstruct vec_t<float, 1> {\n float data;\n\n FLASHINFER_INLINE float& operator[](size_t i) { return ((float*)(&data))[i]; }\n FLASHINFER_INLINE const float& operator[](size_t i) const { return ((const float*)(&data))[i]; }\n FLASHINFER_INLINE float* ptr() { return reinterpret_cast<float*>(&data); }\n FLASHINFER_INLINE void fill(float val);\n FLASHINFER_INLINE void load(const float* ptr);\n FLASHINFER_INLINE void store(float* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 1>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(float* dst, const float* src);\n};\n\nFLASHINFER_INLINE void vec_t<float, 1>::fill(float val) { data = val; }\n\nFLASHINFER_INLINE void vec_t<float, 1>::load(const float* ptr) { data = *ptr; }\n\nFLASHINFER_INLINE void vec_t<float, 1>::store(float* ptr) const { *ptr = data; }\n\nFLASHINFER_INLINE void vec_t<float, 1>::memcpy(float* dst, const float* src) { *dst = *src; }\n\n// float x 2\n\ntemplate <>\nstruct vec_t<float, 2> {\n float2 data;\n\n FLASHINFER_INLINE float& operator[](size_t i) { return ((float*)(&data))[i]; }\n FLASHINFER_INLINE const float& operator[](size_t i) const { return ((const float*)(&data))[i]; }\n FLASHINFER_INLINE float* ptr() { return reinterpret_cast<float*>(&data); }\n FLASHINFER_INLINE void fill(float val);\n FLASHINFER_INLINE void load(const float* ptr);\n FLASHINFER_INLINE void store(float* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 2>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(float* dst, const float* src);\n};\n\nFLASHINFER_INLINE void vec_t<float, 2>::fill(float val) { data = make_float2(val, val); }\n\nFLASHINFER_INLINE void vec_t<float, 2>::load(const float* ptr) { data = *((float2*)ptr); }\n\nFLASHINFER_INLINE void vec_t<float, 2>::store(float* ptr) const { *((float2*)ptr) = data; }\n\nFLASHINFER_INLINE void vec_t<float, 2>::memcpy(float* dst, const float* src) {\n *((float2*)dst) = *((float2*)src);\n}\n\n// float x 4 or more\ntemplate <size_t vec_size>\nstruct vec_t<float, vec_size> {\n float4 data[vec_size / 4];\n\n FLASHINFER_INLINE float& operator[](size_t i) { return ((float*)(data))[i]; }\n FLASHINFER_INLINE const float& operator[](size_t i) const { return ((const float*)(data))[i]; }\n FLASHINFER_INLINE float* ptr() { return reinterpret_cast<float*>(&data); }\n FLASHINFER_INLINE void fill(float val) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 4; ++i) {\n data[i] = make_float4(val, val, val, val);\n }\n }\n FLASHINFER_INLINE void load(const float* ptr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 4; ++i) {\n data[i] = ((float4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(float* ptr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 4; ++i) {\n ((float4*)ptr)[i] = data[i];\n }\n }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(float* dst, const float* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 4; ++i) {\n ((float4*)dst)[i] = ((float4*)src)[i];\n }\n }\n};\n\n} // namespace flashinfer\n\n#endif // VEC_DTYPES_CUH_\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"fuse two byte perm into one.\n"},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1298,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"0d618712faff20a84bbd513d02ac01e16be19306"},"date":{"kind":"string","value":"2024-08-17T23:26:02-07:00"},"pr_number":{"kind":"number","value":453,"string":"453"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/453"},"title":{"kind":"string","value":"perf: slight optimization on f16->f8 fragment layout swizzling (#453)"},"message":{"kind":"string","value":"perf: slight optimization on f16->f8 fragment layout swizzling (#453)\n\nswap after dequantize."},"path":{"kind":"string","value":"include/flashinfer/attention/prefill.cuh"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * Copyright (c) 2023 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_PREFILL_CUH_\n#define FLASHINFER_PREFILL_CUH_\n#include <cooperative_groups.h>\n#include <cuda_bf16.h>\n#include <cuda_fp16.h>\n#ifdef FLASHINFER_ENABLE_FP8\n#include <cuda_fp8.h>\n#endif\n#include <cuda_runtime.h>\n\n#include \"../cp_async.cuh\"\n#include \"../fastdiv.cuh\"\n#include \"../frag_layout_swizzle.cuh\"\n#include \"../layout.cuh\"\n#include \"../math.cuh\"\n#include \"../mma.cuh\"\n#include \"../page.cuh\"\n#include \"../permuted_smem.cuh\"\n#include \"../pos_enc.cuh\"\n#include \"../utils.cuh\"\n#include \"cascade.cuh\"\n#include \"logits_post_hook.cuh\"\n#include \"mask.cuh\"\n#include \"warp_layout.cuh\"\n\nnamespace flashinfer {\n\nnamespace cg = cooperative_groups;\nusing cp_async::SharedMemFillMode;\nusing mma::MMAMode;\n\nconstexpr uint32_t warp_size = 32;\n\nnamespace {\n\ntemplate <PosEncodingMode pos_encoding_mode, typename DTypeKV, typename DTypeQKAccum>\nconstexpr bool is_invalid_configuration(uint32_t num_frags_x, uint32_t num_frags_y,\n uint32_t num_frags_z, uint32_t num_warps_x,\n uint32_t num_warps_z) {\n return ((num_frags_y < 4) || (num_frags_y == 4 && num_frags_z % 2 == 1) ||\n (num_frags_y > 4 && num_frags_y % (2 * num_warps_x) != 0) ||\n (num_frags_x * (8 * num_frags_y + 2 * sizeof(DTypeQKAccum) * num_frags_z) >= 256) ||\n (sizeof(DTypeKV) == 1 && num_frags_z * 2 % num_warps_x != 0) ||\n (sizeof(DTypeKV) == 1 && pos_encoding_mode == PosEncodingMode::kRoPELlama));\n}\n\ntemplate <uint32_t num_warps_x, uint32_t num_warps_z>\n__device__ __forceinline__ uint32_t get_warp_idx_x() {\n if constexpr (num_warps_x == 1) {\n return 0;\n } else {\n return threadIdx.y;\n }\n}\n\ntemplate <uint32_t num_warps_x, uint32_t num_warps_z>\n__device__ __forceinline__ uint32_t get_warp_idx_z() {\n if constexpr (num_warps_z == 1) {\n return 0;\n } else {\n return threadIdx.z;\n }\n}\n\ntemplate <uint32_t num_warps_x, uint32_t num_warps_z>\n__device__ __forceinline__ uint32_t get_warp_idx() {\n return get_warp_idx_z<num_warps_x, num_warps_z>() * num_warps_x +\n get_warp_idx_x<num_warps_x, num_warps_z>();\n}\n\n/*!\n * \\brief Apply Llama style rotary embedding to two 16x16 fragments.\n * \\tparam T The data type of the input fragments.\n * \\param x_first_half First fragment x[offset:offset+16, j*16:(j+1)*16]\n * \\param x_second_half Second fragment x[offset:offset*16, j*16+d/2:(j+1)*16+d/2]\n * \\param rope_freq Rope frequency\n * \\param offset The offset of the first row in both fragments.\n * \\param scale A scale factor applied to the result (used to multiply sm_scale).\n * \\note The sin/cos computation is slow, especially for A100 GPUs which has low\n * non tensor-ops flops, will optimize in the future.\n */\ntemplate <typename T>\n__device__ __forceinline__ void k_frag_apply_llama_rope(T* x_first_half, T* x_second_half,\n const float* rope_freq,\n const uint32_t kv_offset,\n float scale = 1.f) {\n static_assert(sizeof(T) == 2);\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n float cos, sin, tmp;\n // 0 1 | 2 3\n // ---------\n // 4 5 | 6 7\n uint32_t i = reg_id / 4, j = (reg_id % 4) / 2;\n __sincosf(float(kv_offset + 8 * i) * rope_freq[2 * j + reg_id % 2], &sin, &cos);\n tmp = x_first_half[reg_id];\n x_first_half[reg_id] = (tmp * cos - (float)x_second_half[reg_id] * sin) * scale;\n x_second_half[reg_id] = ((float)x_second_half[reg_id] * cos + tmp * sin) * scale;\n }\n}\n\ntemplate <typename T>\n__device__ __forceinline__ void q_frag_apply_llama_rope(T* x_first_half, T* x_second_half,\n const float* rope_freq,\n const uint32_t qo_packed_offset,\n const uint_fastdiv group_size,\n float scale = 1.f) {\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n float cos, sin, tmp;\n // 0 1 | 4 5\n // ---------\n // 2 3 | 6 7\n uint32_t i = ((reg_id % 4) / 2), j = (reg_id / 4);\n __sincosf(float((qo_packed_offset + 8 * i) / group_size) * rope_freq[2 * j + reg_id % 2], &sin,\n &cos);\n tmp = x_first_half[reg_id];\n x_first_half[reg_id] = (tmp * cos - (float)x_second_half[reg_id] * sin) * scale;\n x_second_half[reg_id] = ((float)x_second_half[reg_id] * cos + tmp * sin) * scale;\n }\n}\n\ntemplate <typename T, typename IdType>\n__device__ __forceinline__ void q_frag_apply_llama_rope_with_pos(\n T* x_first_half, T* x_second_half, const float* rope_freq, const uint32_t qo_packed_offset,\n const uint_fastdiv group_size, const IdType* q_offset, float scale = 1.f) {\n float pos[2] = {static_cast<float>(q_offset[qo_packed_offset / group_size]),\n static_cast<float>(q_offset[(qo_packed_offset + 8) / group_size])};\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n float cos, sin, tmp;\n // 0 1 | 4 5\n // ---------\n // 2 3 | 6 7\n uint32_t i = ((reg_id % 4) / 2), j = (reg_id / 4);\n __sincosf(pos[i] * rope_freq[2 * j + reg_id % 2], &sin, &cos);\n tmp = x_first_half[reg_id];\n x_first_half[reg_id] = (tmp * cos - (float)x_second_half[reg_id] * sin) * scale;\n x_second_half[reg_id] = ((float)x_second_half[reg_id] * cos + tmp * sin) * scale;\n }\n}\n\n/*!\n * \\brief Produce k/v fragments from global memory to shared memory.\n * \\tparam fill_mode The fill mode of the shared memory.\n * \\tparam num_frags_y The number of fragments in y dimension.\n * \\tparam num_frags_z The number of fragments in z dimension.\n * \\tparam num_warps The number of warps in the threadblock.\n * \\tparam T The data type of the input tensor.\n * \\param smem The shared memory to store kv fragments.\n * \\param gptr The global memory pointer.\n * \\param qkv_info The tensor info of the input tensor.\n * \\param kv_idx_base The base kv index.\n * \\param kv_len The length of kv tensor.\n */\ntemplate <SharedMemFillMode fill_mode, uint32_t num_warps_x, uint32_t num_warps_z,\n uint32_t num_frags_y, uint32_t num_frags_z, SwizzleMode swizzle_mode, typename T>\n__device__ __forceinline__ void produce_kv(smem_t<swizzle_mode> smem, uint32_t* smem_offset,\n T** gptr, const uint32_t kv_stride_n,\n const uint32_t kv_idx_base, const uint32_t kv_len) {\n // NOTE(Zihao): for fp8, this function doesn't work for head_dim = 64 at the moment\n constexpr uint32_t head_dim = num_frags_y * 16;\n constexpr uint32_t num_warps = num_warps_x * num_warps_z;\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<T>();\n const uint32_t warp_idx = get_warp_idx<num_warps_x, num_warps_z>(), lane_idx = threadIdx.x;\n\n if constexpr (swizzle_mode == SwizzleMode::k128B) {\n uint32_t kv_idx = kv_idx_base + warp_idx * 4 + lane_idx / 8;\n // NOTE(Zihao): num_frags_z * 4 / num_warps_x = num_warps_z * num_frags_z * 4 / num_warps\n static_assert(num_frags_z * 4 % num_warps_x == 0);\n#pragma unroll\n for (uint32_t i = 0; i < num_frags_z * 4 / num_warps_x; ++i) {\n#pragma unroll\n for (uint32_t j = 0; j < num_frags_y / (8 / sizeof(T)); ++j) {\n smem.load_128b_async<fill_mode>(*smem_offset, *gptr, kv_idx < kv_len);\n *smem_offset = smem.template advance_offset_by_column<8>(*smem_offset, j);\n *gptr += 8 * num_elems_per_128b<T>();\n }\n kv_idx += num_warps * 4;\n *smem_offset =\n smem.template advance_offset_by_row<num_warps * 4, channel_size_128b_kv>(*smem_offset) -\n sizeof(T) * num_frags_y;\n *gptr += num_warps * 4 * kv_stride_n - sizeof(T) * num_frags_y * num_elems_per_128b<T>();\n }\n *smem_offset -= num_warps_z * num_frags_z * 16 * channel_size_128b_kv;\n } else {\n uint32_t kv_idx = kv_idx_base + warp_idx * 8 + lane_idx / 4;\n // NOTE(Zihao): num_frags_z * 2 / num_warps_x = num_warps_z * num_frags_z * 2 / num_warps\n static_assert(num_frags_z * 2 % num_warps_x == 0);\n#pragma unroll\n for (uint32_t i = 0; i < num_frags_z * 2 / num_warps_x; ++i) {\n smem.load_128b_async<fill_mode>(*smem_offset, *gptr, kv_idx < kv_len);\n *smem_offset =\n smem.template advance_offset_by_row<num_warps * 8, channel_size_128b_kv>(*smem_offset);\n kv_idx += num_warps * 8;\n *gptr += num_warps * 8 * kv_stride_n;\n }\n *smem_offset -= num_warps_z * num_frags_z * 16 * channel_size_128b_kv;\n }\n}\n\ntemplate <bool produce_v, uint32_t num_warps_x, uint32_t num_warps_z, uint32_t num_frags_y,\n uint32_t num_frags_z, PageStorage page_storage, SwizzleMode swizzle_mode, typename DType,\n typename IdType>\n__device__ __forceinline__ void page_produce_kv(smem_t<swizzle_mode> smem, uint32_t* smem_offset,\n paged_kv_t<page_storage, DType, IdType>& paged_kv,\n const uint32_t kv_idx_base, const size_t* kv_offset,\n const uint32_t kv_len) {\n // NOTE(Zihao): for fp8, this function doesn't work for head_dim = 64 at the moment\n constexpr SharedMemFillMode fill_mode =\n produce_v ? SharedMemFillMode::kFillZero : SharedMemFillMode::kNoFill;\n constexpr uint32_t head_dim = num_frags_y * 16;\n constexpr uint32_t num_warps = num_warps_x * num_warps_z;\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<DType>();\n const uint32_t warp_idx = get_warp_idx<num_warps_x, num_warps_z>(), lane_idx = threadIdx.x;\n if constexpr (swizzle_mode == SwizzleMode::k128B) {\n uint32_t kv_idx = kv_idx_base + warp_idx * 4 + lane_idx / 8;\n // NOTE(Zihao): num_frags_z * 4 / num_warps_x = num_warps_z * num_frags_z * 4 / num_warps\n static_assert(num_frags_z * 4 % num_warps_x == 0);\n#pragma unroll\n for (uint32_t i = 0; i < num_frags_z * 4 / num_warps_x; ++i) {\n DType* gptr = produce_v ? paged_kv.v_data + kv_offset[i] : paged_kv.k_data + kv_offset[i];\n#pragma unroll\n for (uint32_t j = 0; j < num_frags_y / (8 / sizeof(DType)); ++j) {\n smem.load_128b_async<fill_mode>(*smem_offset, gptr, kv_idx < kv_len);\n *smem_offset = smem.template advance_offset_by_column<8>(*smem_offset, j);\n gptr += 8 * num_elems_per_128b<DType>();\n }\n kv_idx += num_warps * 4;\n *smem_offset =\n smem.template advance_offset_by_row<num_warps * 4, channel_size_128b_kv>(*smem_offset) -\n sizeof(DType) * num_frags_y;\n }\n *smem_offset -= num_warps_z * num_frags_z * 16 * channel_size_128b_kv;\n } else {\n uint32_t kv_idx = kv_idx_base + warp_idx * 8 + lane_idx / 4;\n // NOTE(Zihao): num_frags_z * 2 / num_warps_x = num_warps_z * num_frags_z * 2 / num_warps\n static_assert(num_frags_z * 2 % num_warps_x == 0);\n#pragma unroll\n for (uint32_t i = 0; i < num_frags_z * 2 / num_warps_x; ++i) {\n DType* gptr = produce_v ? paged_kv.v_data + kv_offset[i] : paged_kv.k_data + kv_offset[i];\n smem.load_128b_async<fill_mode>(*smem_offset, gptr, kv_idx < kv_len);\n kv_idx += num_warps * 8;\n *smem_offset =\n smem.template advance_offset_by_row<num_warps * 8, channel_size_128b_kv>(*smem_offset);\n }\n *smem_offset -= num_warps_z * num_frags_z * 16 * channel_size_128b_kv;\n }\n}\n\ntemplate <uint32_t num_frags_y>\n__device__ __forceinline__ void init_rope_freq(float (*rope_freq)[4],\n const float log2_rope_rcp_scale,\n const float log2_rope_rcp_theta) {\n constexpr uint32_t head_dim = num_frags_y * 16;\n const uint32_t lane_idx = threadIdx.x;\n#pragma unroll\n for (uint32_t fy = 0; fy < num_frags_y / 2; ++fy) {\n#pragma unroll\n for (uint32_t j = 0; j < 4; ++j) {\n rope_freq[fy][j] = math::ptx_exp2(\n log2_rope_rcp_scale +\n log2_rope_rcp_theta *\n float(2 * ((fy * 16 + (j / 2) * 8 + (lane_idx % 4) * 2 + (j % 2)) % (head_dim / 2))) /\n float(head_dim));\n }\n }\n}\n\ntemplate <uint32_t num_frags_x, uint32_t num_frags_y, typename DTypeQKAccum>\n__device__ __forceinline__ void init_states(float (*o_frag)[num_frags_y][8], DTypeQKAccum (*m)[2],\n float (*d)[2]) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t fy = 0; fy < num_frags_y; ++fy) {\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n o_frag[fx][fy][reg_id] = 0.f;\n }\n }\n }\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n m[fx][j] = DTypeQKAccum(-5e4);\n d[fx][j] = 1.f;\n }\n }\n}\n\ntemplate <uint32_t num_warps_x, uint32_t num_warps_z, uint32_t num_frags_x, uint32_t num_frags_y,\n SwizzleMode swizzle_mode, typename DTypeQ>\n__device__ __forceinline__ void load_q_global_smem(uint32_t packed_offset,\n const uint32_t qo_upper_bound,\n DTypeQ* q_ptr_base, const uint32_t q_stride_n,\n const uint32_t q_stride_h,\n const uint_fastdiv group_size,\n smem_t<swizzle_mode>* q_smem) {\n constexpr uint32_t head_dim = num_frags_y * 16;\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n const uint32_t lane_idx = threadIdx.x, warp_idx_x = get_warp_idx_x<num_warps_x, num_warps_z>();\n\n if (get_warp_idx_z<num_warps_x, num_warps_z>() == 0) {\n uint32_t q_smem_offset_w = q_smem->get_permuted_offset<channel_size_128b_q>(\n warp_idx_x * num_frags_x * 16 + lane_idx / 8, lane_idx % 8);\n\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t j = 0; j < 4; ++j) {\n uint32_t q, r;\n group_size.divmod(packed_offset + lane_idx / 8 + fx * 16 + j * 4, q, r);\n const uint32_t q_idx = q;\n DTypeQ* q_ptr = q_ptr_base + q * q_stride_n + r * q_stride_h;\n#pragma unroll\n for (uint32_t fyo = 0; fyo < num_frags_y / 4; ++fyo) {\n // load q fragment from gmem to smem\n q_smem->load_128b_async<SharedMemFillMode::kNoFill>(q_smem_offset_w, q_ptr,\n q_idx < qo_upper_bound);\n q_smem_offset_w = q_smem->template advance_offset_by_column<8>(q_smem_offset_w, fyo);\n q_ptr += 8 * num_elems_per_128b<DTypeQ>();\n }\n q_smem_offset_w =\n q_smem->template advance_offset_by_row<4, channel_size_128b_q>(q_smem_offset_w) -\n 2 * num_frags_y;\n }\n }\n }\n}\n\ntemplate <uint32_t num_warps_x, uint32_t num_warps_z, uint32_t num_frags_x, uint32_t num_frags_y,\n SwizzleMode swizzle_mode, typename DTypeQ>\n__device__ __forceinline__ void q_smem_inplace_apply_rotary_multiply_sm_scale(\n const uint32_t q_packed_idx, const uint32_t qo_len, const uint32_t kv_len,\n const uint_fastdiv group_size, smem_t<swizzle_mode>* q_smem, uint32_t* q_smem_offset_r,\n float (*rope_freq)[4], const float sm_scale) {\n if (get_warp_idx_z<num_warps_x, num_warps_z>() == 0) {\n constexpr uint32_t head_dim = num_frags_y * 16;\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n const uint32_t lane_idx = threadIdx.x;\n uint32_t q_frag_local[2][4];\n static_assert(num_frags_y % 4 == 0, \"num_frags_y must be a multiple of 4\");\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n uint32_t q_smem_offset_r_first_half = *q_smem_offset_r;\n#pragma unroll\n for (uint32_t fyi = 0; fyi < num_frags_y / 2; ++fyi) {\n q_smem->ldmatrix_m8n8x4(q_smem_offset_r_first_half, q_frag_local[0]);\n uint32_t q_smem_offset_r_last_half =\n q_smem->template advance_offset_by_column<num_frags_y>(q_smem_offset_r_first_half, 0);\n q_smem->ldmatrix_m8n8x4(q_smem_offset_r_last_half, q_frag_local[1]);\n q_frag_apply_llama_rope<DTypeQ>(\n (DTypeQ*)q_frag_local[0], (DTypeQ*)q_frag_local[1], rope_freq[fyi],\n q_packed_idx + kv_len * group_size - qo_len * group_size + fx * 16 + lane_idx / 4,\n group_size, sm_scale);\n q_smem->stmatrix_m8n8x4(q_smem_offset_r_last_half, q_frag_local[1]);\n q_smem->stmatrix_m8n8x4(q_smem_offset_r_first_half, q_frag_local[0]);\n q_smem_offset_r_first_half =\n q_smem->template advance_offset_by_column<2>(q_smem_offset_r_first_half, fyi);\n }\n *q_smem_offset_r += 16 * channel_size_128b_q;\n }\n *q_smem_offset_r -= num_frags_x * 16 * channel_size_128b_q;\n }\n}\n\ntemplate <uint32_t num_warps_x, uint32_t num_warps_z, uint32_t num_frags_x, uint32_t num_frags_y,\n SwizzleMode swizzle_mode, typename DTypeQ, typename IdType>\n__device__ __forceinline__ void q_smem_inplace_apply_rotary_with_pos_multiply_sm_scale(\n const uint32_t q_packed_idx_base, const IdType* q_offset, smem_t<swizzle_mode>* q_smem,\n const uint_fastdiv group_size, uint32_t* q_smem_offset_r, float (*rope_freq)[4],\n const float sm_scale) {\n if (get_warp_idx_z<num_warps_x, num_warps_z>() == 0) {\n constexpr uint32_t head_dim = num_frags_y * 16;\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n const uint32_t lane_idx = threadIdx.x;\n uint32_t q_frag_local[2][4];\n static_assert(num_frags_y % 4 == 0, \"num_frags_y must be a multiple of 4\");\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n uint32_t q_smem_offset_r_first_half = *q_smem_offset_r;\n#pragma unroll\n for (uint32_t fyi = 0; fyi < num_frags_y / 2; ++fyi) {\n q_smem->ldmatrix_m8n8x4(q_smem_offset_r_first_half, q_frag_local[0]);\n uint32_t q_smem_offset_r_last_half =\n q_smem->template advance_offset_by_column<num_frags_y>(q_smem_offset_r_first_half, 0);\n q_smem->ldmatrix_m8n8x4(q_smem_offset_r_last_half, q_frag_local[1]);\n q_frag_apply_llama_rope_with_pos<DTypeQ>(\n (DTypeQ*)q_frag_local[0], (DTypeQ*)q_frag_local[1], rope_freq[fyi],\n q_packed_idx_base + fx * 16 + lane_idx / 4, group_size, q_offset, sm_scale);\n q_smem->stmatrix_m8n8x4(q_smem_offset_r_last_half, q_frag_local[1]);\n q_smem->stmatrix_m8n8x4(q_smem_offset_r_first_half, q_frag_local[0]);\n q_smem_offset_r_first_half =\n q_smem->template advance_offset_by_column<2>(q_smem_offset_r_first_half, fyi);\n }\n *q_smem_offset_r += 16 * channel_size_128b_q;\n }\n *q_smem_offset_r -= num_frags_x * 16 * channel_size_128b_q;\n }\n}\n\ntemplate <uint32_t num_warps_x, uint32_t num_warps_z, uint32_t num_frags_x, uint32_t num_frags_y,\n SwizzleMode swizzle_mode, typename DTypeQ>\n__device__ __forceinline__ void q_smem_inplace_multiply_sm_scale(smem_t<swizzle_mode>* q_smem,\n const float sm_scale) {\n const uint32_t warp_idx = get_warp_idx<num_warps_x, num_warps_z>(), lane_idx = threadIdx.x;\n constexpr uint32_t head_dim = num_frags_y * 16;\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n constexpr uint32_t num_warps = num_warps_x * num_warps_z;\n#pragma unroll\n for (uint32_t i = 0; i < num_frags_x * head_dim / (num_warps_z * 16); ++i) {\n vec_t<DTypeQ, 8> tmp;\n tmp.load((DTypeQ*)(q_smem->base) + (i * num_warps + warp_idx) * 256 + lane_idx * 8);\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n tmp[reg_id] *= sm_scale;\n }\n tmp.store((DTypeQ*)(q_smem->base) + (i * num_warps + warp_idx) * 256 + lane_idx * 8);\n }\n}\n\ntemplate <uint32_t num_warps_x, uint32_t num_warps_z, uint32_t num_frags_y, uint32_t num_frags_z,\n SwizzleMode swizzle_mode, typename DTypeKV>\n__device__ __forceinline__ void k_smem_inplace_apply_rotary(const uint32_t kv_idx_base,\n smem_t<swizzle_mode>* k_smem,\n uint32_t* k_smem_offset_r,\n float (*rope_freq)[4]) {\n static_assert(sizeof(DTypeKV) == 2);\n constexpr uint32_t head_dim = num_frags_y * 16;\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<DTypeKV>();\n uint32_t k_frag_local[2][4];\n const uint32_t lane_idx = threadIdx.x;\n if constexpr (num_frags_y == 4 && num_warps_x == 4) {\n static_assert(num_warps_z == 1);\n const uint32_t warp_idx = get_warp_idx_x<num_warps_x, num_warps_z>();\n // horizontal-axis: y\n // horizontal-axis: y\n // vertical-axis: z\n // | 1-16 | 16-32 | 32-48 | 48-64 |\n // | 1-16 | warp_idx=0 | warp_idx=1 | warp_idx=0 | warp_idx=1 |\n // | 16-32 | warp_idx=2 | warp_idx=3 | warp_idx=2 | warp_idx=3 |\n static_assert(num_frags_z % 2 == 0,\n \"when num_frags_y == 4, num_frags_z must be a multiple of 2\");\n uint32_t kv_idx = kv_idx_base + (warp_idx / 2) * 16 + lane_idx / 4;\n *k_smem_offset_r =\n (*k_smem_offset_r ^ (0x2 * (warp_idx % 2))) + (warp_idx / 2) * 16 * channel_size_128b_kv;\n#pragma unroll\n for (uint32_t i = 0; i < num_frags_z / 2; ++i) {\n // uint32_t fz = warp_idx / 2 + i * 2;\n uint32_t k_smem_offset_r_first_half = *k_smem_offset_r;\n uint32_t fyi = (warp_idx % 2);\n k_smem->ldmatrix_m8n8x4(k_smem_offset_r_first_half, k_frag_local[0]);\n uint32_t k_smem_offset_r_last_half =\n k_smem->template advance_offset_by_column<4>(k_smem_offset_r_first_half, 0);\n k_smem->ldmatrix_m8n8x4(k_smem_offset_r_last_half, k_frag_local[1]);\n k_frag_apply_llama_rope<DTypeKV>((DTypeKV*)k_frag_local[0], (DTypeKV*)k_frag_local[1],\n rope_freq[fyi], kv_idx);\n k_smem->stmatrix_m8n8x4(k_smem_offset_r_last_half, k_frag_local[1]);\n k_smem->stmatrix_m8n8x4(k_smem_offset_r_first_half, k_frag_local[0]);\n *k_smem_offset_r += 32 * channel_size_128b_kv;\n kv_idx += 32;\n }\n *k_smem_offset_r = (*k_smem_offset_r ^ (0x2 * (warp_idx % 2))) -\n ((warp_idx / 2) + num_frags_z) * 16 * channel_size_128b_kv;\n } else {\n const uint32_t warp_idx_x = get_warp_idx_x<num_warps_x, num_warps_z>(),\n warp_idx_z = get_warp_idx_z<num_warps_x, num_warps_z>();\n static_assert(num_frags_y % (2 * num_warps_x) == 0);\n // horizontal axis: y\n // vertical axis: z\n // | (warp_idx_z, warp_idx_x) | 1-16 | 16-32 | 32-48 | 48-64 | ...\n // | 1-16*num_frags_z | (0, 0) | (0, 1) | (0, 2) | (0, 3) | ...\n // | 16*num_frags_z-32*num_frags_z | (1, 0) | (1, 1) | (1, 2) | (1, 3) | ...\n // ...\n uint32_t kv_idx = kv_idx_base + (warp_idx_z * num_frags_z * 16) + lane_idx / 4;\n *k_smem_offset_r = *k_smem_offset_r ^ (0x2 * warp_idx_x);\n#pragma unroll\n for (uint32_t i = 0; i < num_frags_z; ++i) {\n uint32_t k_smem_offset_r_first_half = *k_smem_offset_r;\n#pragma unroll\n for (uint32_t j = 0; j < num_frags_y / (2 * num_warps_x); ++j) {\n uint32_t fyi = warp_idx_x + j * num_warps_x;\n k_smem->ldmatrix_m8n8x4(k_smem_offset_r_first_half, k_frag_local[0]);\n uint32_t k_smem_offset_r_last_half =\n k_smem->template advance_offset_by_column<num_frags_y>(k_smem_offset_r_first_half, 0);\n k_smem->ldmatrix_m8n8x4(k_smem_offset_r_last_half, k_frag_local[1]);\n k_frag_apply_llama_rope<DTypeKV>((DTypeKV*)k_frag_local[0], (DTypeKV*)k_frag_local[1],\n rope_freq[fyi], kv_idx);\n k_smem->stmatrix_m8n8x4(k_smem_offset_r_last_half, k_frag_local[1]);\n k_smem->stmatrix_m8n8x4(k_smem_offset_r_first_half, k_frag_local[0]);\n k_smem_offset_r_first_half = k_smem->template advance_offset_by_column<2 * num_warps_x>(\n k_smem_offset_r_first_half, fyi);\n }\n *k_smem_offset_r += 16 * channel_size_128b_kv;\n kv_idx += 16;\n }\n *k_smem_offset_r =\n (*k_smem_offset_r ^ (0x2 * warp_idx_x)) - num_frags_z * 16 * channel_size_128b_kv;\n }\n}\n\ntemplate <LogitsPostHook logits_post_hook, uint32_t num_frags_x, uint32_t num_frags_y,\n uint32_t num_frags_z, SwizzleMode swizzle_mode_q, SwizzleMode swizzle_mode_kv,\n typename DTypeQ, typename DTypeKV, typename DTypeQKAccum>\n__device__ __forceinline__ void compute_qk(\n smem_t<swizzle_mode_q>* q_smem, uint32_t* q_smem_offset_r, smem_t<swizzle_mode_kv>* k_smem,\n uint32_t* k_smem_offset_r, DTypeQKAccum (*s_frag)[num_frags_z][8], const float soft_cap) {\n constexpr uint32_t head_dim = num_frags_y * 16;\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<DTypeKV>();\n uint32_t a_frag[num_frags_x][4], b_frag[4];\n // compute q*k^T\n#pragma unroll\n for (uint32_t fy = 0; fy < num_frags_y; ++fy) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n q_smem->ldmatrix_m8n8x4(*q_smem_offset_r, a_frag[fx]);\n *q_smem_offset_r =\n q_smem->template advance_offset_by_row<16, channel_size_128b_q>(*q_smem_offset_r);\n }\n\n *q_smem_offset_r = q_smem->template advance_offset_by_column<2>(*q_smem_offset_r, fy) -\n num_frags_x * 16 * channel_size_128b_q;\n\n#pragma unroll\n for (uint32_t fz = 0; fz < num_frags_z; ++fz) {\n if constexpr (sizeof(DTypeKV) == 1) {\n uint32_t b_frag_f8[2];\n if (fy % 2 == 0) {\n k_smem->ldmatrix_m8n8x4_left_half(*k_smem_offset_r, b_frag_f8);\n } else {\n k_smem->ldmatrix_m8n8x4_right_half(*k_smem_offset_r, b_frag_f8);\n }\n b_frag_f8[0] = frag_layout_swizzle_16b_to_8b(b_frag_f8[0]);\n b_frag_f8[1] = frag_layout_swizzle_16b_to_8b(b_frag_f8[1]);\n vec_cast<DTypeQ, DTypeKV>::cast<8>((DTypeQ*)b_frag, (DTypeKV*)b_frag_f8);\n } else {\n k_smem->ldmatrix_m8n8x4(*k_smem_offset_r, b_frag);\n }\n *k_smem_offset_r =\n k_smem->template advance_offset_by_row<16, channel_size_128b_kv>(*k_smem_offset_r);\n\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n if constexpr (std::is_same<DTypeQKAccum, float>::value) {\n if (fy == 0) {\n mma::mma_sync_m16n16k16_row_col_f16f16f32<DTypeQ, MMAMode::kInit>(s_frag[fx][fz],\n a_frag[fx], b_frag);\n } else {\n mma::mma_sync_m16n16k16_row_col_f16f16f32<DTypeQ>(s_frag[fx][fz], a_frag[fx], b_frag);\n }\n } else if (std::is_same<DTypeQKAccum, half>::value) {\n if (fy == 0) {\n mma::mma_sync_m16n16k16_row_col_f16f16f16<MMAMode::kInit>((uint32_t*)s_frag[fx][fz],\n a_frag[fx], b_frag);\n } else {\n mma::mma_sync_m16n16k16_row_col_f16f16f16((uint32_t*)s_frag[fx][fz], a_frag[fx],\n b_frag);\n }\n }\n }\n }\n if constexpr (sizeof(DTypeKV) == 1) {\n if (fy % 2 == 1) {\n *k_smem_offset_r = k_smem->template advance_offset_by_column<2>(*k_smem_offset_r, fy / 2);\n }\n *k_smem_offset_r -= num_frags_z * 16 * channel_size_128b_kv;\n } else {\n *k_smem_offset_r = k_smem->template advance_offset_by_column<2>(*k_smem_offset_r, fy) -\n num_frags_z * 16 * channel_size_128b_kv;\n }\n }\n *q_smem_offset_r -= num_frags_y * 2;\n *k_smem_offset_r -= num_frags_y * sizeof(DTypeKV);\n\n if constexpr (std::is_same<DTypeQKAccum, float>::value) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t fz = 0; fz < num_frags_z; ++fz) {\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n s_frag[fx][fz][reg_id] =\n apply_logits_post_hook<logits_post_hook>(s_frag[fx][fz][reg_id], soft_cap);\n }\n }\n }\n } else {\n static_assert(std::is_same<DTypeQKAccum, half>::value);\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t fz = 0; fz < num_frags_z; ++fz) {\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 4; ++reg_id) {\n *(half2*)(&s_frag[fx][fz][reg_id * 2]) = apply_logits_post_hook<logits_post_hook>(\n *(half2*)(&s_frag[fx][fz][reg_id * 2]), soft_cap);\n }\n }\n }\n }\n}\n\ntemplate <uint32_t num_frags_x, uint32_t num_frags_z, typename T>\n__device__ __forceinline__ void apply_alibi_bias(const uint32_t qo_packed_idx_base,\n const uint32_t kv_idx_base, const int32_t q_offset,\n const uint_fastdiv group_size,\n float (*alibi_slope)[2],\n T (*s_frag)[num_frags_z][8]) {\n const int32_t lane_idx = threadIdx.x;\n#pragma unroll\n for (int32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (int32_t fz = 0; fz < num_frags_z; ++fz) {\n#pragma unroll\n for (int32_t reg_id = 0; reg_id < 8; ++reg_id) {\n const int32_t q_idx =\n (qo_packed_idx_base + fx * 16 + lane_idx / 4 + 8 * ((reg_id % 4) / 2)) /\n group_size,\n kv_idx = kv_idx_base + fz * 16 + 2 * (lane_idx % 4) + 8 * (reg_id / 4) +\n reg_id % 2;\n s_frag[fx][fz][reg_id] +=\n T(alibi_slope[fx][(reg_id % 4) / 2]) * T(kv_idx - q_idx - q_offset);\n }\n }\n }\n}\n\ntemplate <MaskMode mask_mode, uint32_t num_frags_x, uint32_t num_frags_y, uint32_t num_frags_z,\n typename DTypeQKAccum>\n__device__ __forceinline__ void mask_s(const uint32_t qo_packed_idx_base,\n const uint32_t kv_idx_base, const uint32_t qo_len,\n const uint32_t kv_len, const uint32_t window_left,\n const uint32_t chunk_end, const uint_fastdiv group_size,\n uint8_t* custom_mask,\n DTypeQKAccum (*s_frag)[num_frags_z][8]) {\n const uint32_t lane_idx = threadIdx.x;\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t fz = 0; fz < num_frags_z; ++fz) {\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n const uint32_t q_idx =\n (qo_packed_idx_base + fx * 16 + lane_idx / 4 + 8 * ((reg_id % 4) / 2)) /\n group_size,\n kv_idx = kv_idx_base + fz * 16 + 2 * (lane_idx % 4) + 8 * (reg_id / 4) +\n reg_id % 2;\n const bool out_of_boundary =\n (mask_mode == MaskMode::kCausal\n ? (kv_idx + qo_len > kv_len + q_idx || (kv_idx >= chunk_end) ||\n kv_idx + qo_len + window_left < kv_len + q_idx)\n : kv_idx >= chunk_end || kv_idx + qo_len + window_left < kv_len + q_idx);\n s_frag[fx][fz][reg_id] =\n (out_of_boundary ||\n (mask_mode == MaskMode::kCustom && q_idx < qo_len &&\n !((custom_mask[(q_idx * kv_len + kv_idx) / 8] >> ((q_idx * kv_len + kv_idx) % 8)) &\n 1)))\n ? DTypeQKAccum(-5e4)\n : s_frag[fx][fz][reg_id];\n }\n }\n }\n}\n\ntemplate <uint32_t num_frags_x, uint32_t num_frags_y, uint32_t num_frags_z, typename DTypeQKAccum>\n__device__ __forceinline__ void update_mdo_states(DTypeQKAccum (*s_frag)[num_frags_z][8],\n float (*o_frag)[num_frags_y][8],\n DTypeQKAccum (*m)[2], float (*d)[2]) {\n if constexpr (std::is_same<DTypeQKAccum, float>::value) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n float m_prev = m[fx][j];\n#pragma unroll\n for (uint32_t fz = 0; fz < num_frags_z; ++fz) {\n float m_local = max(max(s_frag[fx][fz][j * 2 + 0], s_frag[fx][fz][j * 2 + 1]),\n max(s_frag[fx][fz][j * 2 + 4], s_frag[fx][fz][j * 2 + 5]));\n m[fx][j] = max(m[fx][j], m_local);\n }\n m[fx][j] = max(m[fx][j], math::shfl_xor_sync(m[fx][j], 0x2));\n m[fx][j] = max(m[fx][j], math::shfl_xor_sync(m[fx][j], 0x1));\n\n float o_scale = math::ptx_exp2(m_prev - m[fx][j]);\n d[fx][j] *= o_scale;\n#pragma unroll\n for (uint32_t fy = 0; fy < num_frags_y; ++fy) {\n o_frag[fx][fy][j * 2 + 0] *= o_scale;\n o_frag[fx][fy][j * 2 + 1] *= o_scale;\n o_frag[fx][fy][j * 2 + 4] *= o_scale;\n o_frag[fx][fy][j * 2 + 5] *= o_scale;\n }\n#pragma unroll\n for (uint32_t fz = 0; fz < num_frags_z; ++fz) {\n s_frag[fx][fz][j * 2 + 0] = math::ptx_exp2(s_frag[fx][fz][j * 2 + 0] - m[fx][j]);\n s_frag[fx][fz][j * 2 + 1] = math::ptx_exp2(s_frag[fx][fz][j * 2 + 1] - m[fx][j]);\n s_frag[fx][fz][j * 2 + 4] = math::ptx_exp2(s_frag[fx][fz][j * 2 + 4] - m[fx][j]);\n s_frag[fx][fz][j * 2 + 5] = math::ptx_exp2(s_frag[fx][fz][j * 2 + 5] - m[fx][j]);\n }\n }\n }\n } else if constexpr (std::is_same<DTypeQKAccum, half>::value) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n half m_prev[2];\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n m_prev[j] = m[fx][j];\n#pragma unroll\n for (uint32_t fz = 0; fz < num_frags_z; ++fz) {\n half2 m_local =\n __hmax2(*(half2*)&s_frag[fx][fz][j * 2], *(half2*)&s_frag[fx][fz][j * 2 + 4]);\n m[fx][j] = __hmax(m[fx][j], __hmax(m_local.x, m_local.y));\n }\n }\n *(half2*)&m[fx] = __hmax2(*(half2*)&m[fx], math::shfl_xor_sync(*(half2*)&m[fx], 0x2));\n *(half2*)&m[fx] = __hmax2(*(half2*)&m[fx], math::shfl_xor_sync(*(half2*)&m[fx], 0x1));\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n float o_scale = math::ptx_exp2(float(m_prev[j] - m[fx][j]));\n d[fx][j] *= o_scale;\n#pragma unroll\n for (uint32_t fy = 0; fy < num_frags_y; ++fy) {\n o_frag[fx][fy][j * 2 + 0] *= o_scale;\n o_frag[fx][fy][j * 2 + 1] *= o_scale;\n o_frag[fx][fy][j * 2 + 4] *= o_scale;\n o_frag[fx][fy][j * 2 + 5] *= o_scale;\n }\n half2 m2 = make_half2(m[fx][j], m[fx][j]);\n#pragma unroll\n for (uint32_t fz = 0; fz < num_frags_z; ++fz) {\n *(half2*)&s_frag[fx][fz][j * 2] = math::ptx_exp2(*(half2*)&s_frag[fx][fz][j * 2] - m2);\n *(half2*)&s_frag[fx][fz][j * 2 + 4] =\n math::ptx_exp2(*(half2*)&s_frag[fx][fz][j * 2 + 4] - m2);\n }\n }\n }\n }\n}\n\ntemplate <uint32_t num_frags_x, uint32_t num_frags_y, uint32_t num_frags_z,\n SwizzleMode swizzle_mode, typename DTypeQ, typename DTypeKV, typename DTypeQKAccum>\n__device__ __forceinline__ void compute_sfm_v(smem_t<swizzle_mode>* v_smem,\n uint32_t* v_smem_offset_r,\n DTypeQKAccum (*s_frag)[num_frags_z][8],\n float (*o_frag)[num_frags_y][8], float (*d)[2]) {\n constexpr uint32_t head_dim = num_frags_y * 16;\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<DTypeKV>();\n\n DTypeQ s_frag_f16[num_frags_x][num_frags_z][8];\n if constexpr (std::is_same<DTypeQKAccum, float>::value) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t fz = 0; fz < num_frags_z; ++fz) {\n vec_cast<DTypeQ, float>::cast<8>(s_frag_f16[fx][fz], s_frag[fx][fz]);\n }\n }\n }\n\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t fz = 0; fz < num_frags_z; ++fz) {\n if constexpr (std::is_same<DTypeQKAccum, float>::value) {\n mma::rowsum_f16f16f32(d[fx], s_frag_f16[fx][fz]);\n } else {\n mma::rowsum_f16f16f32(d[fx], s_frag[fx][fz]);\n }\n }\n }\n\n#pragma unroll\n for (uint32_t fz = 0; fz < num_frags_z; ++fz) {\n#pragma unroll\n for (uint32_t fy = 0; fy < num_frags_y; ++fy) {\n uint32_t b_frag[4];\n if constexpr (sizeof(DTypeKV) == 1) {\n uint32_t b_frag_f8[2];\n if (fy % 2 == 0) {\n v_smem->ldmatrix_m8n8x4_trans_left_half(*v_smem_offset_r, b_frag_f8);\n } else {\n v_smem->ldmatrix_m8n8x4_trans_right_half(*v_smem_offset_r, b_frag_f8);\n }\n b_frag_f8[0] = frag_layout_swizzle_16b_to_8b_trans(b_frag_f8[0]);\n b_frag_f8[1] = frag_layout_swizzle_16b_to_8b_trans(b_frag_f8[1]);\n bfly_exch(b_frag_f8[0], b_frag_f8[1]);\n vec_cast<DTypeQ, DTypeKV>::cast<8>((DTypeQ*)b_frag, (DTypeKV*)b_frag_f8);\n } else {\n v_smem->ldmatrix_m8n8x4_trans(*v_smem_offset_r, b_frag);\n }\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n if constexpr (std::is_same<DTypeQKAccum, float>::value) {\n mma::mma_sync_m16n16k16_row_col_f16f16f32<DTypeQ>(\n o_frag[fx][fy], (uint32_t*)(s_frag_f16[fx][fz]), b_frag);\n } else {\n mma::mma_sync_m16n16k16_row_col_f16f16f32<DTypeQ>(o_frag[fx][fy],\n (uint32_t*)s_frag[fx][fz], b_frag);\n }\n }\n if constexpr (sizeof(DTypeKV) == 1) {\n if (fy % 2 == 1) {\n *v_smem_offset_r = v_smem->template advance_offset_by_column<2>(*v_smem_offset_r, fy / 2);\n }\n } else {\n *v_smem_offset_r = v_smem->template advance_offset_by_column<2>(*v_smem_offset_r, fy);\n }\n }\n *v_smem_offset_r =\n v_smem->template advance_offset_by_row<16, channel_size_128b_kv>(*v_smem_offset_r) -\n sizeof(DTypeKV) * num_frags_y;\n }\n *v_smem_offset_r -= 16 * num_frags_z * channel_size_128b_kv;\n}\n\ntemplate <uint32_t num_frags_x, uint32_t num_frags_y, typename DTypeQKAccum>\n__device__ __forceinline__ void normalize_d(float (*o_frag)[num_frags_y][8], DTypeQKAccum (*m)[2],\n float (*d)[2]) {\n float d_rcp[num_frags_x][2];\n // compute reciprocal of d\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n d_rcp[fx][j] = (m[fx][j] != DTypeQKAccum(-5e4)) ? math::ptx_rcp(d[fx][j]) : 0.f;\n }\n }\n\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t fy = 0; fy < num_frags_y; ++fy) {\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n o_frag[fx][fy][reg_id] = o_frag[fx][fy][reg_id] * d_rcp[fx][(reg_id % 4) / 2];\n }\n }\n }\n}\n\n/*!\n * \\brief Synchronize the states of the MDO kernel across the threadblock along threadIdx.z.\n */\ntemplate <uint32_t num_warps_x, uint32_t num_warps_z, uint32_t num_frags_x, uint32_t num_frags_y,\n typename DTypeQKAccum>\n__device__ __forceinline__ void threadblock_sync_mdo_states(float (*o_frag)[num_frags_y][8],\n float* smem_workspace,\n DTypeQKAccum (*m)[2], float (*d)[2],\n const uint32_t warp_idx,\n const uint32_t lane_idx) {\n // only necessary when blockDim.z > 1\n if constexpr (num_warps_z > 1) {\n float2* smem_md = (float2*)(smem_workspace + num_frags_x * num_frags_y * num_warps_x *\n num_warps_z * warp_size * 8);\n // o: [num_warps, num_frags_x, num_frags_y, warp_size(32), 8]\n // md: [num_warps, num_frags_x, 2, warp_size(32), 2 (m/d)]\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t fy = 0; fy < num_frags_y; ++fy) {\n vec_t<float, 8>::memcpy(\n smem_workspace +\n (((warp_idx * num_frags_x + fx) * num_frags_y + fy) * warp_size + lane_idx) * 8,\n o_frag[fx][fy]);\n }\n }\n\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n smem_md[((warp_idx * num_frags_x + fx) * 2 + j) * warp_size + lane_idx] =\n make_float2(float(m[fx][j]), d[fx][j]);\n }\n }\n\n // synchronize m,d first\n __syncthreads();\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n float o_scale[2][num_warps_z];\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n float m_new = -5e4, d_new = 1.f;\n#pragma unroll\n for (uint32_t i = 0; i < num_warps_z; ++i) {\n float2 md = smem_md[(((i * num_warps_x + get_warp_idx_x<num_warps_x, num_warps_z>()) *\n num_frags_x +\n fx) *\n 2 +\n j) *\n warp_size +\n lane_idx];\n float m_prev = m_new, d_prev = d_new;\n m_new = max(m_new, md.x);\n d_new = d_prev * math::ptx_exp2(m_prev - m_new) + md.y * math::ptx_exp2(md.x - m_new);\n }\n\n#pragma unroll\n for (uint32_t i = 0; i < num_warps_z; ++i) {\n float2 md = smem_md[(((i * num_warps_x + get_warp_idx_x<num_warps_x, num_warps_z>()) *\n num_frags_x +\n fx) *\n 2 +\n j) *\n warp_size +\n lane_idx];\n float mi = md.x;\n o_scale[j][i] = math::ptx_exp2(float(mi - m_new));\n }\n m[fx][j] = DTypeQKAccum(m_new);\n d[fx][j] = d_new;\n }\n\n#pragma unroll\n for (uint32_t fy = 0; fy < num_frags_y; ++fy) {\n vec_t<float, 8> o_new;\n o_new.fill(0.f);\n#pragma unroll\n for (uint32_t i = 0; i < num_warps_z; ++i) {\n vec_t<float, 8> oi;\n oi.load(smem_workspace +\n ((((i * num_warps_x + get_warp_idx_x<num_warps_x, num_warps_z>()) * num_frags_x +\n fx) *\n num_frags_y +\n fy) *\n warp_size +\n lane_idx) *\n 8);\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n o_new[reg_id] += oi[reg_id] * o_scale[(reg_id % 4) / 2][i];\n }\n }\n o_new.store(o_frag[fx][fy]);\n }\n }\n }\n}\n\ntemplate <uint32_t num_warps_x, uint32_t num_warps_z, uint32_t num_frags_x, uint32_t num_frags_y,\n SwizzleMode swizzle_mode, typename DTypeOut>\n__device__ __forceinline__ void write_o_reg_gmem(\n float (*o_frag)[num_frags_y][8], smem_t<swizzle_mode>* o_smem, DTypeOut* o_ptr_base,\n const uint32_t o_packed_idx_base, const uint32_t qo_upper_bound, const uint32_t o_stride_n,\n const uint32_t o_stride_h, const uint_fastdiv group_size) {\n constexpr uint32_t head_dim = num_frags_y * 16;\n constexpr uint32_t channel_size_128b_out = head_dim / num_elems_per_128b<DTypeOut>();\n const uint32_t warp_idx_x = get_warp_idx_x<num_warps_x, num_warps_z>();\n const uint32_t lane_idx = threadIdx.x;\n\n if (get_warp_idx_z<num_warps_x, num_warps_z>() == 0) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t fy = 0; fy < num_frags_y; ++fy) {\n uint32_t o_frag_f16[4];\n vec_cast<DTypeOut, float>::cast<8>((DTypeOut*)o_frag_f16, o_frag[fx][fy]);\n#ifdef FLASHINFER_STMATRIX_M8N8X4_ENABLED\n uint32_t o_smem_offset_w = o_smem->get_permuted_offset<channel_size_128b_out>(\n (warp_idx_x * num_frags_x + fx) * 16 + lane_idx % 16, fy * 2 + lane_idx / 16);\n o_smem->stmatrix_m8n8x4(o_smem_offset_w, o_frag_f16);\n#else\n uint32_t o_smem_offset_w = o_smem->get_permuted_offset<channel_size_128b_out>(\n (warp_idx_x * num_frags_x + fx) * 16 + lane_idx / 4, fy * 2);\n ((uint32_t*)(o_smem->base + o_smem_offset_w))[lane_idx % 4] = o_frag_f16[0];\n ((uint32_t*)(o_smem->base + o_smem_offset_w + 8 * channel_size_128b_out))[lane_idx % 4] =\n o_frag_f16[1];\n ((uint32_t*)(o_smem->base + (o_smem_offset_w ^ 0x1)))[lane_idx % 4] = o_frag_f16[2];\n ((uint32_t*)(o_smem->base + (o_smem_offset_w ^ 0x1) +\n 8 * channel_size_128b_out))[lane_idx % 4] = o_frag_f16[3];\n#endif\n }\n }\n\n uint32_t o_smem_offset_w = o_smem->get_permuted_offset<channel_size_128b_out>(\n warp_idx_x * num_frags_x * 16 + lane_idx / 8, lane_idx % 8);\n\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t j = 0; j < 4; ++j) {\n uint32_t q, r;\n group_size.divmod(o_packed_idx_base + lane_idx / 8 + fx * 16 + j * 4, q, r);\n const uint32_t o_idx = q;\n DTypeOut* o_ptr = o_ptr_base + q * o_stride_n + r * o_stride_h;\n#pragma unroll\n for (uint32_t fyo = 0; fyo < num_frags_y / 4; ++fyo) {\n if (o_idx < qo_upper_bound) {\n o_smem->store_128b(o_smem_offset_w, o_ptr);\n }\n o_ptr += 8 * num_elems_per_128b<DTypeOut>();\n o_smem_offset_w = o_smem->template advance_offset_by_column<8>(o_smem_offset_w, fyo);\n }\n o_smem_offset_w =\n o_smem->template advance_offset_by_row<4, channel_size_128b_out>(o_smem_offset_w) -\n 2 * num_frags_y;\n }\n }\n }\n}\n\n} // namespace\n\n/*!\n * \\brief FlashAttention prefill CUDA kernel for a single request.\n * \\tparam partition_kv Whether to split kv_len into chunks.\n * \\tparam mask_mode The mask mode used in the attention operation.\n * \\tparam pos_encoding_mode The positional encoding mode.\n * \\tparam num_frags_x The number of fragments in x dimension.\n * \\tparam num_frags_y The number of fragments in y dimension.\n * \\tparam num_frags_z The number of fragments in z dimension.\n * \\tparam num_warps The number of warps in the threadblock.\n * \\tparam DTypeQ The data type of the query tensor.\n * \\tparam DTypeKV The data type of the key/value tensor.\n * \\tparam DTypeOut The data type of the output tensor.\n * \\param q The query tensor.\n * \\param k The key tensor.\n * \\param v The value tensor.\n * \\param o The output tensor.\n * \\param tmp The temporary buffer (used when partition_kv is true).\n * \\param lse The logsumexp value.\n * \\param qkv_info The tensor info of the input tensor.\n * \\param sm_scale The scale factor applied to the softmax score.\n * \\param log2_rope_rcp_scale log2(1/(rope_scale)), where rope_scale is the scaling\n * factor used in RoPE interpolation.\n * \\param log2_rope_rcp_theta log2(1/(rope_theta)), where rope_theta is the theta\n * used in RoPE.\n */\ntemplate <LogitsPostHook logits_post_hook, MaskMode mask_mode, PosEncodingMode pos_encoding_mode,\n uint32_t num_frags_x, uint32_t num_frags_y, uint32_t num_frags_z, uint32_t num_warps_x,\n uint32_t num_warps_z, typename DTypeQ, typename DTypeKV, typename DTypeQKAccum,\n typename DTypeOut>\n__global__\n__launch_bounds__(num_warps_x* num_warps_z* warp_size) void SinglePrefillWithKVCacheKernel(\n DTypeQ* __restrict__ q, DTypeKV* __restrict__ k, DTypeKV* __restrict__ v,\n uint8_t* __restrict__ custom_mask, DTypeOut* __restrict__ o, float* __restrict__ lse,\n const uint32_t qo_len, const uint32_t kv_len, const bool partition_kv,\n const uint_fastdiv group_size, const uint32_t q_stride_n, const uint32_t q_stride_h,\n const uint32_t kv_stride_n, const uint32_t kv_stride_h, const int32_t maybe_window_left,\n const float logits_soft_cap, float sm_scale, const float log2_rope_rcp_scale,\n const float log2_rope_rcp_theta) {\n static_assert(sizeof(DTypeQ) == 2);\n static_assert(sizeof(DTypeOut) == 2);\n sm_scale *=\n (logits_post_hook == LogitsPostHook::kNone ? math::log2e : math::ptx_rcp(logits_soft_cap));\n const uint32_t lane_idx = threadIdx.x, warp_idx = get_warp_idx<num_warps_x, num_warps_z>();\n const uint32_t bx = blockIdx.x, chunk_idx = blockIdx.y, kv_head_idx = blockIdx.z;\n const uint32_t num_kv_heads = gridDim.z, num_qo_heads = num_kv_heads * group_size;\n constexpr uint32_t num_rows_per_cta = num_frags_x * num_warps_x * 16;\n const tensor_info_t qkv_info(qo_len, kv_len, num_qo_heads, num_kv_heads, q_stride_n, q_stride_h,\n kv_stride_n, kv_stride_h, /*head_dim=*/num_frags_y * 16);\n float alibi_slopes[num_frags_x][2];\n\n const uint32_t num_chunks = gridDim.y;\n const uint32_t max_chunk_size = partition_kv ? ceil_div(kv_len, num_chunks) : kv_len;\n const uint32_t chunk_start = partition_kv ? chunk_idx * max_chunk_size : 0;\n const uint32_t chunk_end = partition_kv ? min((chunk_idx + 1) * max_chunk_size, kv_len) : kv_len;\n const uint32_t chunk_size = chunk_end - chunk_start;\n\n auto block = cg::this_thread_block();\n const uint32_t window_left = (maybe_window_left >= 0) ? maybe_window_left : kv_len;\n\n constexpr uint32_t head_dim = num_frags_y * 16;\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<DTypeKV>();\n constexpr uint32_t channel_size_128b_out = head_dim / num_elems_per_128b<DTypeOut>();\n\n extern __shared__ uint8_t smem[];\n\n DTypeQKAccum s_frag[num_frags_x][num_frags_z][8];\n float o_frag[num_frags_x][num_frags_y][8];\n DTypeQKAccum m[num_frags_x][2];\n float d[num_frags_x][2];\n float rope_freq[num_frags_y / 2][4];\n if constexpr (pos_encoding_mode == PosEncodingMode::kRoPELlama) {\n init_rope_freq<num_frags_y>(rope_freq, log2_rope_rcp_scale, log2_rope_rcp_theta);\n }\n init_states<num_frags_x, num_frags_y>(o_frag, m, d);\n\n // cooperative fetch q fragment from gmem to reg\n const uint32_t qo_packed_idx_base =\n (bx * num_warps_x + get_warp_idx_x<num_warps_x, num_warps_z>()) * num_frags_x * 16;\n constexpr SwizzleMode swizzle_mode_q = SwizzleMode::k128B;\n smem_t<swizzle_mode_q> qo_smem(smem);\n DTypeQ* q_ptr_base =\n q + qkv_info.get_q_elem_offset(0, kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeQ>());\n DTypeOut* o_ptr_base =\n partition_kv\n ? o + chunk_idx * num_qo_heads * head_dim +\n qkv_info.get_o_elem_offset(0, kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeOut>())\n : o + qkv_info.get_o_elem_offset(0, kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeOut>());\n uint32_t q_smem_offset_r = qo_smem.get_permuted_offset<channel_size_128b_q>(\n get_warp_idx_x<num_warps_x, num_warps_z>() * num_frags_x * 16 + lane_idx % 16, lane_idx / 16);\n\n load_q_global_smem<num_warps_x, num_warps_z, num_frags_x, num_frags_y>(\n qo_packed_idx_base, qo_len, q_ptr_base, q_stride_n, q_stride_h, group_size, &qo_smem);\n\n cp_async::commit_group();\n cp_async::wait_group<0>();\n block.sync();\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kRoPELlama) {\n q_smem_inplace_apply_rotary_multiply_sm_scale<num_warps_x, num_warps_z, num_frags_x,\n num_frags_y, swizzle_mode_q, DTypeQ>(\n qo_packed_idx_base, qo_len, kv_len, group_size, &qo_smem, &q_smem_offset_r, rope_freq,\n sm_scale);\n } else {\n q_smem_inplace_multiply_sm_scale<num_warps_x, num_warps_z, num_frags_x, num_frags_y,\n swizzle_mode_q, DTypeQ>(&qo_smem, sm_scale);\n }\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kALiBi) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n const uint32_t qo_head_idx =\n kv_head_idx * group_size +\n (qo_packed_idx_base + lane_idx / 4 + j * 8 + fx * 16) % group_size;\n alibi_slopes[fx][j] = get_alibi_slope(qo_head_idx, num_qo_heads) * math::log2e;\n }\n }\n }\n\n constexpr SwizzleMode swizzle_mode_kv =\n (sizeof(DTypeKV) == 1 && head_dim == 64) ? SwizzleMode::k64B : SwizzleMode::k128B;\n constexpr uint32_t kv_frag_rows = swizzle_mode_kv == SwizzleMode::k128B ? 4 : 8;\n constexpr uint32_t kv_frag_cols = swizzle_mode_kv == SwizzleMode::k128B ? 8 : 4;\n smem_t<swizzle_mode_kv> k_smem(smem +\n (num_warps_x * num_frags_x * sizeof(DTypeQ)) * 16 * head_dim),\n v_smem(smem + (num_warps_x * num_frags_x * sizeof(DTypeQ) +\n num_warps_z * num_frags_z * sizeof(DTypeKV)) *\n 16 * head_dim);\n\n const uint32_t num_iterations = ceil_div(\n mask_mode == MaskMode::kCausal\n ? min(chunk_size,\n sub_if_greater_or_zero(kv_len - qo_len + ((bx + 1) * num_rows_per_cta) / group_size,\n chunk_start))\n : chunk_size,\n 16 * num_warps_z * num_frags_z);\n\n const uint32_t window_iteration =\n ceil_div(sub_if_greater_or_zero(kv_len + (bx + 1) * num_rows_per_cta,\n qo_len + window_left + chunk_start),\n (16 * num_warps_z * num_frags_z));\n\n const uint32_t mask_iteration =\n (mask_mode == MaskMode::kCausal\n ? min(chunk_size,\n sub_if_greater_or_zero(kv_len + (bx * num_rows_per_cta) / group_size - qo_len,\n chunk_start))\n : chunk_size) /\n (16 * num_warps_z * num_frags_z);\n\n DTypeKV* k_ptr = k + qkv_info.get_kv_elem_offset(\n chunk_start + warp_idx * kv_frag_rows + lane_idx / kv_frag_cols,\n kv_head_idx, (lane_idx % kv_frag_cols) * num_elems_per_128b<DTypeKV>());\n DTypeKV* v_ptr = v + qkv_info.get_kv_elem_offset(\n chunk_start + warp_idx * kv_frag_rows + lane_idx / kv_frag_cols,\n kv_head_idx, (lane_idx % kv_frag_cols) * num_elems_per_128b<DTypeKV>());\n uint32_t k_smem_offset_r = k_smem.get_permuted_offset<channel_size_128b_kv>(\n get_warp_idx_z<num_warps_x, num_warps_z>() * num_frags_z * 16 + 8 * (lane_idx / 16) +\n lane_idx % 8,\n (lane_idx % 16) / 8),\n v_smem_offset_r = v_smem.get_permuted_offset<channel_size_128b_kv>(\n get_warp_idx_z<num_warps_x, num_warps_z>() * num_frags_z * 16 + lane_idx % 16,\n lane_idx / 16),\n kv_smem_offset_w = k_smem.get_permuted_offset<channel_size_128b_kv>(\n warp_idx * kv_frag_rows + lane_idx / kv_frag_cols, lane_idx % kv_frag_cols);\n produce_kv<SharedMemFillMode::kNoFill, num_warps_x, num_warps_z, num_frags_y, num_frags_z>(\n k_smem, &kv_smem_offset_w, &k_ptr, kv_stride_n, 0, chunk_size);\n cp_async::commit_group();\n produce_kv<SharedMemFillMode::kFillZero, num_warps_x, num_warps_z, num_frags_y, num_frags_z>(\n v_smem, &kv_smem_offset_w, &v_ptr, kv_stride_n, 0, chunk_size);\n cp_async::commit_group();\n\n#pragma unroll 1\n for (uint32_t iter = 0; iter < num_iterations; ++iter) {\n cp_async::wait_group<1>();\n block.sync();\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kRoPELlama) {\n k_smem_inplace_apply_rotary<num_warps_x, num_warps_z, num_frags_y, num_frags_z,\n swizzle_mode_kv, DTypeKV>(\n chunk_start + iter * 16 * num_warps_z * num_frags_z, &k_smem, &k_smem_offset_r,\n rope_freq);\n block.sync();\n }\n\n // compute attention score\n compute_qk<logits_post_hook, num_frags_x, num_frags_y, num_frags_z, swizzle_mode_q,\n swizzle_mode_kv, DTypeQ, DTypeKV>(&qo_smem, &q_smem_offset_r, &k_smem,\n &k_smem_offset_r, s_frag, logits_soft_cap);\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kALiBi) {\n apply_alibi_bias<num_frags_x, num_frags_z>(\n qo_packed_idx_base,\n chunk_start +\n (iter * num_warps_z + get_warp_idx_z<num_warps_x, num_warps_z>()) * num_frags_z * 16,\n int(kv_len) - int(qo_len), group_size, alibi_slopes, s_frag);\n }\n // apply mask\n if constexpr (mask_mode == MaskMode::kCustom) {\n mask_s<mask_mode, num_frags_x, num_frags_y, num_frags_z>(\n qo_packed_idx_base,\n chunk_start +\n (iter * num_warps_z + get_warp_idx_z<num_warps_x, num_warps_z>()) * num_frags_z * 16,\n qo_len, kv_len, window_left, chunk_end, group_size, custom_mask, s_frag);\n } else {\n if (iter >= mask_iteration || iter < window_iteration) {\n mask_s<mask_mode, num_frags_x, num_frags_y, num_frags_z>(\n qo_packed_idx_base,\n chunk_start + (iter * num_warps_z + get_warp_idx_z<num_warps_x, num_warps_z>()) *\n num_frags_z * 16,\n qo_len, kv_len, window_left, chunk_end, group_size, nullptr, s_frag);\n }\n }\n\n // compute m,d states in online softmax\n update_mdo_states<num_frags_x, num_frags_y, num_frags_z>(s_frag, o_frag, m, d);\n\n block.sync();\n produce_kv<SharedMemFillMode::kNoFill, num_warps_x, num_warps_z, num_frags_y, num_frags_z>(\n k_smem, &kv_smem_offset_w, &k_ptr, kv_stride_n, (iter + 1) * 16 * num_warps_z * num_frags_z,\n chunk_size);\n cp_async::commit_group();\n cp_async::wait_group<1>();\n block.sync();\n\n // compute sfm*v\n compute_sfm_v<num_frags_x, num_frags_y, num_frags_z, swizzle_mode_kv, DTypeQ, DTypeKV>(\n &v_smem, &v_smem_offset_r, s_frag, o_frag, d);\n\n block.sync();\n produce_kv<SharedMemFillMode::kFillZero, num_warps_x, num_warps_z, num_frags_y, num_frags_z>(\n v_smem, &kv_smem_offset_w, &v_ptr, kv_stride_n, (iter + 1) * 16 * num_warps_z * num_frags_z,\n chunk_size);\n cp_async::commit_group();\n }\n cp_async::wait_group<0>();\n block.sync();\n\n // threadblock synchronization\n threadblock_sync_mdo_states<num_warps_x, num_warps_z, num_frags_x, num_frags_y, DTypeQKAccum>(\n o_frag, (float*)smem, m, d, warp_idx, lane_idx);\n\n // normalize d\n normalize_d<num_frags_x, num_frags_y>(o_frag, m, d);\n\n // write back\n write_o_reg_gmem<num_warps_x, num_warps_z, num_frags_x, num_frags_y>(\n o_frag, &qo_smem, o_ptr_base, qo_packed_idx_base, qo_len,\n /*o_stride_n=*/partition_kv ? num_qo_heads * head_dim * num_chunks : num_qo_heads * head_dim,\n /*o_stride_h=*/head_dim, group_size);\n\n // write lse\n if (lse != nullptr || partition_kv) {\n if (get_warp_idx_z<num_warps_x, num_warps_z>() == 0) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n uint32_t q, r;\n group_size.divmod(qo_packed_idx_base + lane_idx / 4 + j * 8 + fx * 16, q, r);\n const uint32_t qo_head_idx = kv_head_idx * group_size + r;\n const uint32_t qo_idx = q;\n if (qo_idx < qo_len) {\n if (partition_kv) {\n lse[(qo_idx * num_chunks + chunk_idx) * num_qo_heads + qo_head_idx] =\n math::ptx_log2(d[fx][j]) + float(m[fx][j]);\n } else {\n lse[qo_idx * num_qo_heads + qo_head_idx] = math::ptx_log2(d[fx][j]) + float(m[fx][j]);\n }\n }\n }\n }\n }\n }\n}\n\ntemplate <LogitsPostHook logits_post_hook, MaskMode mask_mode, PosEncodingMode pos_encoding_mode,\n uint32_t num_frags_x, uint32_t num_frags_y, uint32_t num_frags_z, uint32_t num_warps_x,\n uint32_t num_warps_z, typename DTypeQ, typename DTypeKV, typename DTypeQKAccum,\n typename DTypeOut, typename IdType>\n__global__\n__launch_bounds__(num_warps_x* num_warps_z* warp_size) void BatchPrefillWithRaggedKVCacheKernel(\n DTypeQ* __restrict__ q, IdType* __restrict__ request_indices,\n IdType* __restrict__ q_tile_indices, IdType* __restrict__ kv_tile_indices,\n IdType* __restrict__ q_indptr, DTypeKV* __restrict__ k, DTypeKV* __restrict__ v,\n IdType* __restrict__ kv_indptr, uint8_t* __restrict__ custom_mask,\n IdType* __restrict__ qk_indptr, IdType* __restrict__ q_offset,\n IdType* __restrict__ k_rope_pos_offset, IdType* __restrict__ o_indptr, DTypeOut* __restrict__ o,\n float* __restrict__ lse, bool* __restrict__ block_valid_mask,\n IdType* __restrict__ kv_chunk_size_ptr, const bool partition_kv, const uint_fastdiv group_size,\n const uint32_t q_stride_n, const uint32_t q_stride_h, const uint32_t kv_stride_n,\n const uint32_t kv_stride_h, const int32_t maybe_window_left, const float logits_soft_cap,\n float sm_scale, const float log2_rope_rcp_scale, const float log2_rope_rcp_theta) {\n static_assert(sizeof(DTypeQ) == 2);\n static_assert(sizeof(DTypeOut) == 2);\n sm_scale *=\n (logits_post_hook == LogitsPostHook::kNone ? math::log2e : math::ptx_rcp(logits_soft_cap));\n constexpr uint32_t head_dim = num_frags_y * 16;\n const uint32_t kv_chunk_size = *kv_chunk_size_ptr;\n\n auto block = cg::this_thread_block();\n const uint32_t bx = blockIdx.x, lane_idx = threadIdx.x,\n warp_idx = get_warp_idx<num_warps_x, num_warps_z>(), kv_head_idx = blockIdx.z;\n if (block_valid_mask && !block_valid_mask[bx]) {\n return;\n }\n const uint32_t num_kv_heads = gridDim.z, num_qo_heads = group_size * num_kv_heads;\n const uint32_t request_idx = request_indices[bx], qo_tile_idx = q_tile_indices[bx],\n kv_tile_idx = kv_tile_indices[bx];\n constexpr uint32_t num_rows_per_cta = num_frags_x * num_warps_x * 16;\n const uint32_t qo_len = q_indptr[request_idx + 1] - q_indptr[request_idx],\n kv_len = kv_indptr[request_idx + 1] - kv_indptr[request_idx];\n const uint32_t kv_len_safe = kv_len > 0 ? kv_len : 1;\n const uint32_t window_left = (maybe_window_left >= 0) ? maybe_window_left : kv_len;\n const uint32_t max_chunk_size = partition_kv ? kv_chunk_size : kv_len;\n const uint32_t chunk_start = partition_kv ? kv_tile_idx * max_chunk_size : 0;\n const uint32_t chunk_end =\n partition_kv ? min((kv_tile_idx + 1) * max_chunk_size, kv_len) : kv_len;\n const uint32_t chunk_size = chunk_end - chunk_start;\n const tensor_info_t qkv_info(qo_len, kv_len, num_qo_heads, num_kv_heads, q_stride_n, q_stride_h,\n kv_stride_n, kv_stride_h, /*head_dim=*/num_frags_y * 16);\n float alibi_slopes[num_frags_x][2];\n const uint32_t qo_upper_bound =\n min(qo_len, ceil_div((qo_tile_idx + 1) * num_rows_per_cta, group_size));\n\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<DTypeKV>();\n constexpr uint32_t channel_size_128b_out = head_dim / num_elems_per_128b<DTypeOut>();\n\n extern __shared__ uint8_t smem[];\n\n DTypeQKAccum s_frag[num_frags_x][num_frags_z][8];\n float o_frag[num_frags_x][num_frags_y][8];\n DTypeQKAccum m[num_frags_x][2];\n float d[num_frags_x][2];\n float rope_freq[num_frags_y / 2][4];\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kRoPELlama) {\n init_rope_freq<num_frags_y>(rope_freq, log2_rope_rcp_scale, log2_rope_rcp_theta);\n }\n init_states<num_frags_x, num_frags_y>(o_frag, m, d);\n\n const uint32_t qo_packed_idx_base =\n (qo_tile_idx * num_warps_x + get_warp_idx_x<num_warps_x, num_warps_z>()) * num_frags_x * 16;\n constexpr SwizzleMode swizzle_mode_q = SwizzleMode::k128B;\n smem_t<swizzle_mode_q> qo_smem(smem);\n\n DTypeQ* q_ptr_base =\n q + qkv_info.get_q_elem_offset(q_indptr[request_idx], kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeQ>());\n\n DTypeOut* o_ptr_base =\n partition_kv\n ? o + kv_tile_idx * num_qo_heads * head_dim +\n qkv_info.get_o_elem_offset(o_indptr[request_idx], kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeOut>())\n : o + qkv_info.get_o_elem_offset(o_indptr[request_idx], kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeOut>());\n\n uint32_t q_smem_offset_r = qo_smem.get_permuted_offset<channel_size_128b_q>(\n get_warp_idx_x<num_warps_x, num_warps_z>() * num_frags_x * 16 + lane_idx % 16, lane_idx / 16);\n\n load_q_global_smem<num_warps_x, num_warps_z, num_frags_x, num_frags_y>(\n qo_packed_idx_base, qo_upper_bound, q_ptr_base, q_stride_n, q_stride_h, group_size, &qo_smem);\n\n cp_async::commit_group();\n cp_async::wait_group<0>();\n block.sync();\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kRoPELlama) {\n if (!q_offset) {\n q_smem_inplace_apply_rotary_multiply_sm_scale<num_warps_x, num_warps_z, num_frags_x,\n num_frags_y, swizzle_mode_q, DTypeQ>(\n qo_packed_idx_base, qo_len, kv_len, group_size, &qo_smem, &q_smem_offset_r, rope_freq,\n sm_scale);\n } else {\n q_smem_inplace_apply_rotary_with_pos_multiply_sm_scale<num_warps_x, num_warps_z, num_frags_x,\n num_frags_y, swizzle_mode_q, DTypeQ>(\n qo_packed_idx_base, q_offset + q_indptr[request_idx], &qo_smem, group_size,\n &q_smem_offset_r, rope_freq, sm_scale);\n }\n } else {\n q_smem_inplace_multiply_sm_scale<num_warps_x, num_warps_z, num_frags_x, num_frags_y,\n swizzle_mode_q, DTypeQ>(&qo_smem, sm_scale);\n }\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kALiBi) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n const uint32_t qo_head_idx =\n kv_head_idx * group_size +\n (qo_packed_idx_base + lane_idx / 4 + j * 8 + fx * 16) % group_size;\n alibi_slopes[fx][j] = get_alibi_slope(qo_head_idx, num_qo_heads) * math::log2e;\n }\n }\n }\n\n const uint32_t num_iterations =\n ceil_div((mask_mode == MaskMode::kCausal\n ? min(chunk_size,\n sub_if_greater_or_zero(\n kv_len - qo_len + ((qo_tile_idx + 1) * num_rows_per_cta) / group_size,\n chunk_start))\n : chunk_size),\n 16 * num_warps_z * num_frags_z);\n\n const uint32_t window_iteration =\n ceil_div(sub_if_greater_or_zero(kv_len + (bx + 1) * num_rows_per_cta,\n qo_len + window_left + chunk_start),\n (16 * num_warps_z * num_frags_z));\n\n const uint32_t mask_iteration =\n (mask_mode == MaskMode::kCausal\n ? min(chunk_size,\n sub_if_greater_or_zero(\n kv_len + (qo_tile_idx * num_rows_per_cta) / group_size - qo_len, chunk_start))\n : chunk_size) /\n (16 * num_warps_z * num_frags_z);\n\n constexpr SwizzleMode swizzle_mode_kv =\n (sizeof(DTypeKV) == 1 && head_dim == 64) ? SwizzleMode::k64B : SwizzleMode::k128B;\n constexpr uint32_t kv_frag_rows = swizzle_mode_kv == SwizzleMode::k128B ? 4 : 8;\n constexpr uint32_t kv_frag_cols = swizzle_mode_kv == SwizzleMode::k128B ? 8 : 4;\n smem_t<swizzle_mode_kv> k_smem(smem +\n (num_warps_x * num_frags_x * sizeof(DTypeQ)) * 16 * head_dim),\n v_smem(smem + (num_warps_x * num_frags_x * sizeof(DTypeQ) +\n num_warps_z * num_frags_z * sizeof(DTypeKV)) *\n 16 * head_dim);\n\n uint32_t k_smem_offset_r = k_smem.get_permuted_offset<channel_size_128b_kv>(\n get_warp_idx_z<num_warps_x, num_warps_z>() * num_frags_z * 16 + 8 * (lane_idx / 16) +\n lane_idx % 8,\n (lane_idx % 16) / 8),\n v_smem_offset_r = v_smem.get_permuted_offset<channel_size_128b_kv>(\n get_warp_idx_z<num_warps_x, num_warps_z>() * num_frags_z * 16 + lane_idx % 16,\n lane_idx / 16),\n kv_smem_offset_w = k_smem.get_permuted_offset<channel_size_128b_kv>(\n warp_idx * kv_frag_rows + lane_idx / kv_frag_cols, lane_idx % kv_frag_cols);\n\n DTypeKV* k_ptr = k + qkv_info.get_kv_elem_offset(\n kv_indptr[request_idx] + chunk_start + warp_idx * kv_frag_rows +\n lane_idx / kv_frag_cols,\n kv_head_idx, (lane_idx % kv_frag_cols) * num_elems_per_128b<DTypeKV>());\n DTypeKV* v_ptr = v + qkv_info.get_kv_elem_offset(\n kv_indptr[request_idx] + chunk_start + warp_idx * kv_frag_rows +\n lane_idx / kv_frag_cols,\n kv_head_idx, (lane_idx % kv_frag_cols) * num_elems_per_128b<DTypeKV>());\n\n produce_kv<SharedMemFillMode::kNoFill, num_warps_x, num_warps_z, num_frags_y, num_frags_z>(\n k_smem, &kv_smem_offset_w, &k_ptr, kv_stride_n, 0, chunk_size);\n cp_async::commit_group();\n produce_kv<SharedMemFillMode::kFillZero, num_warps_x, num_warps_z, num_frags_y, num_frags_z>(\n v_smem, &kv_smem_offset_w, &v_ptr, kv_stride_n, 0, chunk_size);\n cp_async::commit_group();\n\n#pragma unroll 1\n for (uint32_t iter = 0; iter < num_iterations; ++iter) {\n cp_async::wait_group<1>();\n block.sync();\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kRoPELlama) {\n k_smem_inplace_apply_rotary<num_warps_x, num_warps_z, num_frags_y, num_frags_z,\n swizzle_mode_kv, DTypeKV>(\n (k_rope_pos_offset == nullptr ? 0 : k_rope_pos_offset[request_idx]) + chunk_start +\n iter * 16 * num_warps_z * num_frags_z,\n &k_smem, &k_smem_offset_r, rope_freq);\n block.sync();\n }\n\n // compute attention score\n compute_qk<logits_post_hook, num_frags_x, num_frags_y, num_frags_z, swizzle_mode_q,\n swizzle_mode_kv, DTypeQ, DTypeKV>(&qo_smem, &q_smem_offset_r, &k_smem,\n &k_smem_offset_r, s_frag, logits_soft_cap);\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kALiBi) {\n // TODO(Zihao): handle the case that q_offset is specified\n apply_alibi_bias<num_frags_x, num_frags_z>(\n qo_packed_idx_base,\n chunk_start +\n (iter * num_warps_z + get_warp_idx_z<num_warps_x, num_warps_z>()) * num_frags_z * 16,\n int(kv_len) - int(qo_len), group_size, alibi_slopes, s_frag);\n }\n // apply mask\n if constexpr (mask_mode == MaskMode::kCustom) {\n mask_s<mask_mode, num_frags_x, num_frags_y, num_frags_z>(\n qo_packed_idx_base,\n chunk_start +\n (iter * num_warps_z + get_warp_idx_z<num_warps_x, num_warps_z>()) * num_frags_z * 16,\n qo_len, kv_len, window_left, chunk_end, group_size, custom_mask + qk_indptr[request_idx],\n s_frag);\n } else {\n if (iter >= mask_iteration || iter < window_iteration) {\n mask_s<mask_mode, num_frags_x, num_frags_y, num_frags_z>(\n qo_packed_idx_base,\n chunk_start + (iter * num_warps_z + get_warp_idx_z<num_warps_x, num_warps_z>()) *\n num_frags_z * 16,\n qo_len, kv_len, window_left, chunk_end, group_size, nullptr, s_frag);\n }\n }\n\n // compute m,d states in online softmax\n update_mdo_states<num_frags_x, num_frags_y, num_frags_z>(s_frag, o_frag, m, d);\n\n block.sync();\n produce_kv<SharedMemFillMode::kNoFill, num_warps_x, num_warps_z, num_frags_y, num_frags_z>(\n k_smem, &kv_smem_offset_w, &k_ptr, kv_stride_n, (iter + 1) * 16 * num_warps_z * num_frags_z,\n chunk_size);\n cp_async::commit_group();\n cp_async::wait_group<1>();\n block.sync();\n\n // compute sfm*v\n compute_sfm_v<num_frags_x, num_frags_y, num_frags_z, swizzle_mode_kv, DTypeQ, DTypeKV>(\n &v_smem, &v_smem_offset_r, s_frag, o_frag, d);\n\n block.sync();\n produce_kv<SharedMemFillMode::kFillZero, num_warps_x, num_warps_z, num_frags_y, num_frags_z>(\n v_smem, &kv_smem_offset_w, &v_ptr, kv_stride_n, (iter + 1) * 16 * num_warps_z * num_frags_z,\n chunk_size);\n cp_async::commit_group();\n }\n cp_async::wait_group<0>();\n block.sync();\n\n // threadblock synchronization\n threadblock_sync_mdo_states<num_warps_x, num_warps_z, num_frags_x, num_frags_y, DTypeQKAccum>(\n o_frag, (float*)smem, m, d, warp_idx, lane_idx);\n\n // normalize d\n normalize_d<num_frags_x, num_frags_y>(o_frag, m, d);\n\n const uint32_t num_kv_chunks = (kv_len_safe + kv_chunk_size - 1) / kv_chunk_size;\n\n // write back\n write_o_reg_gmem<num_warps_x, num_warps_z, num_frags_x, num_frags_y>(\n o_frag, &qo_smem, o_ptr_base, qo_packed_idx_base, qo_len,\n /*o_stride_n=*/\n partition_kv ? num_qo_heads * head_dim * num_kv_chunks : num_qo_heads * head_dim,\n /*o_stride_h=*/head_dim, group_size);\n\n // write lse\n if (lse != nullptr) {\n if (get_warp_idx_z<num_warps_x, num_warps_z>() == 0) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n uint32_t q, r;\n group_size.divmod(qo_packed_idx_base + lane_idx / 4 + j * 8 + fx * 16, q, r);\n const uint32_t qo_head_idx = kv_head_idx * group_size + r;\n const uint32_t qo_idx = q;\n if (qo_idx < qo_len) {\n if (partition_kv) {\n lse[(o_indptr[request_idx] + qo_idx * num_kv_chunks + kv_tile_idx) * num_qo_heads +\n qo_head_idx] = math::ptx_log2(d[fx][j]) + float(m[fx][j]);\n } else {\n lse[(o_indptr[request_idx] + qo_idx) * num_qo_heads + qo_head_idx] =\n math::ptx_log2(d[fx][j]) + float(m[fx][j]);\n }\n }\n }\n }\n }\n }\n}\n\ntemplate <LogitsPostHook logits_post_hook, MaskMode mask_mode, PosEncodingMode pos_encoding_mode,\n uint32_t num_frags_x, uint32_t num_frags_y, uint32_t num_frags_z, uint32_t num_warps_x,\n uint32_t num_warps_z, PageStorage page_storage, typename DTypeQ, typename DTypeKV,\n typename DTypeQKAccum, typename DTypeOut, typename IdType>\n__global__\n__launch_bounds__(num_warps_x* num_warps_z* warp_size) void BatchPrefillWithPagedKVCacheKernel(\n IdType* __restrict__ request_indices, IdType* __restrict__ q_tile_indices,\n IdType* __restrict__ kv_tile_indices, DTypeQ* __restrict__ q,\n paged_kv_t<page_storage, DTypeKV, IdType> paged_kv, IdType* __restrict__ q_indptr,\n uint8_t* __restrict__ custom_mask, IdType* __restrict__ qk_indptr,\n IdType* __restrict__ q_offset, IdType* __restrict__ o_indptr, DTypeOut* __restrict__ o,\n float* __restrict__ lse, bool* __restrict__ block_valid_mask,\n IdType* __restrict__ kv_chunk_size_ptr, const bool partition_kv, const uint_fastdiv group_size,\n int32_t maybe_window_left, const float logits_soft_cap, float sm_scale,\n const float log2_rope_rcp_scale, const float log2_rope_rcp_theta) {\n static_assert(sizeof(DTypeQ) == 2);\n static_assert(sizeof(DTypeOut) == 2);\n sm_scale *=\n (logits_post_hook == LogitsPostHook::kNone ? math::log2e : math::ptx_rcp(logits_soft_cap));\n auto block = cg::this_thread_block();\n const uint32_t kv_chunk_size = *kv_chunk_size_ptr;\n\n const uint32_t bx = blockIdx.x, lane_idx = threadIdx.x,\n warp_idx = get_warp_idx<num_warps_x, num_warps_z>(), kv_head_idx = blockIdx.z;\n if (block_valid_mask && !block_valid_mask[bx]) {\n return;\n }\n const uint32_t num_kv_heads = gridDim.z, num_qo_heads = num_kv_heads * group_size;\n float alibi_slopes[num_frags_x][2];\n\n const uint32_t request_idx = request_indices[bx], qo_tile_idx = q_tile_indices[bx],\n kv_tile_idx = kv_tile_indices[bx];\n constexpr uint32_t num_rows_per_cta = num_frags_x * num_warps_x * 16;\n const uint32_t qo_len = q_indptr[request_idx + 1] - q_indptr[request_idx],\n kv_len = (paged_kv.indptr[request_idx + 1] != paged_kv.indptr[request_idx])\n ? (paged_kv.indptr[request_idx + 1] - paged_kv.indptr[request_idx] -\n 1) * paged_kv.page_size +\n paged_kv.last_page_len[request_idx]\n : 0;\n const uint32_t kv_len_safe = kv_len > 0 ? kv_len : 1;\n const uint32_t window_left = (maybe_window_left >= 0) ? maybe_window_left : kv_len;\n const uint32_t max_chunk_size = partition_kv ? kv_chunk_size : kv_len;\n const uint32_t chunk_start = partition_kv ? kv_tile_idx * max_chunk_size : 0;\n const uint32_t chunk_end =\n partition_kv ? min((kv_tile_idx + 1) * max_chunk_size, kv_len) : kv_len;\n const uint32_t chunk_size = chunk_end - chunk_start;\n const uint32_t qo_upper_bound =\n min(qo_len, ceil_div((qo_tile_idx + 1) * num_rows_per_cta, group_size));\n\n constexpr uint32_t head_dim = num_frags_y * 16;\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<DTypeKV>();\n constexpr uint32_t channel_size_128b_out = head_dim / num_elems_per_128b<DTypeOut>();\n\n extern __shared__ uint8_t smem[];\n\n DTypeQKAccum s_frag[num_frags_x][num_frags_z][8];\n float o_frag[num_frags_x][num_frags_y][8];\n DTypeQKAccum m[num_frags_x][2];\n float d[num_frags_x][2];\n float rope_freq[num_frags_y / 2][4];\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kRoPELlama) {\n init_rope_freq<num_frags_y>(rope_freq, log2_rope_rcp_scale, log2_rope_rcp_theta);\n }\n init_states<num_frags_x, num_frags_y>(o_frag, m, d);\n\n const uint32_t qo_packed_idx_base =\n (qo_tile_idx * num_warps_x + get_warp_idx_x<num_warps_x, num_warps_z>()) * num_frags_x * 16;\n const uint32_t q_stride_n = num_qo_heads * head_dim, q_stride_h = head_dim;\n constexpr SwizzleMode swizzle_mode_q = SwizzleMode::k128B;\n smem_t<swizzle_mode_q> qo_smem(smem);\n DTypeQ* q_ptr_base = q + get_elem_offset_impl(q_indptr[request_idx], kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeQ>(),\n q_stride_n, q_stride_h);\n DTypeOut* o_ptr_base =\n partition_kv ? o + kv_tile_idx * num_qo_heads * head_dim +\n get_elem_offset_impl(o_indptr[request_idx], kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeOut>(),\n num_qo_heads * head_dim, head_dim)\n : o + get_elem_offset_impl(o_indptr[request_idx], kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeOut>(),\n num_qo_heads * head_dim, head_dim);\n uint32_t q_smem_offset_r = qo_smem.get_permuted_offset<channel_size_128b_q>(\n get_warp_idx_x<num_warps_x, num_warps_z>() * num_frags_x * 16 + lane_idx % 16, lane_idx / 16);\n\n load_q_global_smem<num_warps_x, num_warps_z, num_frags_x, num_frags_y>(\n qo_packed_idx_base, qo_upper_bound, q_ptr_base, q_stride_n, q_stride_h, group_size, &qo_smem);\n\n cp_async::commit_group();\n cp_async::wait_group<0>();\n block.sync();\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kRoPELlama) {\n if (q_offset == nullptr) {\n q_smem_inplace_apply_rotary_multiply_sm_scale<num_warps_x, num_warps_z, num_frags_x,\n num_frags_y, swizzle_mode_q, DTypeQ>(\n qo_packed_idx_base, qo_len, kv_len, group_size, &qo_smem, &q_smem_offset_r, rope_freq,\n sm_scale);\n } else {\n q_smem_inplace_apply_rotary_with_pos_multiply_sm_scale<num_warps_x, num_warps_z, num_frags_x,\n num_frags_y, swizzle_mode_q, DTypeQ>(\n qo_packed_idx_base, q_offset + q_indptr[request_idx], &qo_smem, group_size,\n &q_smem_offset_r, rope_freq, sm_scale);\n }\n } else {\n q_smem_inplace_multiply_sm_scale<num_warps_x, num_warps_z, num_frags_x, num_frags_y,\n swizzle_mode_q, DTypeQ>(&qo_smem, sm_scale);\n }\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kALiBi) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n const uint32_t qo_head_idx =\n kv_head_idx * group_size +\n (qo_packed_idx_base + lane_idx / 4 + j * 8 + fx * 16) % group_size;\n alibi_slopes[fx][j] = get_alibi_slope(qo_head_idx, num_qo_heads) * math::log2e;\n }\n }\n }\n\n constexpr SwizzleMode swizzle_mode_kv =\n (sizeof(DTypeKV) == 1 && head_dim == 64) ? SwizzleMode::k64B : SwizzleMode::k128B;\n constexpr uint32_t kv_frag_rows = swizzle_mode_kv == SwizzleMode::k128B ? 4 : 8;\n constexpr uint32_t kv_frag_cols = swizzle_mode_kv == SwizzleMode::k128B ? 8 : 4;\n smem_t<swizzle_mode_kv> k_smem(smem +\n (num_warps_x * num_frags_x * sizeof(DTypeQ)) * 16 * head_dim),\n v_smem(smem + (num_warps_x * num_frags_x * sizeof(DTypeQ) +\n num_warps_z * num_frags_z * sizeof(DTypeKV)) *\n 16 * head_dim);\n size_t kv_offset[num_frags_z * (swizzle_mode_kv == SwizzleMode::k128B ? 4 : 2) / num_warps_x];\n\n uint32_t k_smem_offset_r = k_smem.get_permuted_offset<channel_size_128b_kv>(\n get_warp_idx_z<num_warps_x, num_warps_z>() * num_frags_z * 16 + 8 * (lane_idx / 16) +\n lane_idx % 8,\n (lane_idx % 16) / 8),\n v_smem_offset_r = v_smem.get_permuted_offset<channel_size_128b_kv>(\n get_warp_idx_z<num_warps_x, num_warps_z>() * num_frags_z * 16 + lane_idx % 16,\n lane_idx / 16),\n kv_smem_offset_w = k_smem.get_permuted_offset<channel_size_128b_kv>(\n warp_idx * kv_frag_rows + lane_idx / kv_frag_cols, lane_idx % kv_frag_cols);\n const IdType last_indptr = paged_kv.indptr[paged_kv.batch_size];\n\n uint32_t packed_page_iter_base = paged_kv.indptr[request_idx] * paged_kv.page_size + chunk_start;\n#pragma unroll\n for (uint32_t i = 0;\n i < num_frags_z * (swizzle_mode_kv == SwizzleMode::k128B ? 4 : 2) / num_warps_x; ++i) {\n uint32_t page_iter, entry_idx;\n paged_kv.page_size.divmod(packed_page_iter_base + warp_idx * kv_frag_rows +\n lane_idx / kv_frag_cols +\n kv_frag_rows * num_warps_x * num_warps_z * i,\n page_iter, entry_idx);\n kv_offset[i] =\n page_iter < last_indptr\n ? paged_kv.get_elem_offset(__ldg(paged_kv.indices + page_iter), kv_head_idx, entry_idx,\n (lane_idx % kv_frag_cols) * num_elems_per_128b<DTypeKV>())\n : 0;\n }\n page_produce_kv<false, num_warps_x, num_warps_z, num_frags_y, num_frags_z>(\n k_smem, &kv_smem_offset_w, paged_kv, 0, kv_offset, chunk_size);\n cp_async::commit_group();\n page_produce_kv<true, num_warps_x, num_warps_z, num_frags_y, num_frags_z>(\n v_smem, &kv_smem_offset_w, paged_kv, 0, kv_offset, chunk_size);\n cp_async::commit_group();\n\n const uint32_t num_iterations =\n ceil_div((mask_mode == MaskMode::kCausal\n ? min(chunk_size,\n sub_if_greater_or_zero(\n kv_len - qo_len + ((qo_tile_idx + 1) * num_rows_per_cta) / group_size,\n chunk_start))\n : chunk_size),\n 16 * num_warps_z * num_frags_z);\n\n const uint32_t window_iteration =\n ceil_div(sub_if_greater_or_zero(kv_len + (bx + 1) * num_rows_per_cta,\n qo_len + window_left + chunk_start),\n (16 * num_warps_z * num_frags_z));\n\n const uint32_t mask_iteration =\n (mask_mode == MaskMode::kCausal\n ? min(chunk_size,\n sub_if_greater_or_zero(\n kv_len + (qo_tile_idx * num_rows_per_cta) / group_size - qo_len, chunk_start))\n : chunk_size) /\n (16 * num_warps_z * num_frags_z);\n\n#pragma unroll 1\n for (uint32_t iter = 0; iter < num_iterations; ++iter) {\n packed_page_iter_base += 16 * num_warps_z * num_frags_z;\n#pragma unroll\n for (uint32_t i = 0;\n i < num_frags_z * (swizzle_mode_kv == SwizzleMode::k128B ? 4 : 2) / num_warps_x; ++i) {\n uint32_t page_iter, entry_idx;\n paged_kv.page_size.divmod(packed_page_iter_base + warp_idx * kv_frag_rows +\n lane_idx / kv_frag_cols +\n kv_frag_rows * num_warps_x * num_warps_z * i,\n page_iter, entry_idx);\n kv_offset[i] = page_iter < last_indptr\n ? paged_kv.get_elem_offset(\n __ldg(paged_kv.indices + page_iter), kv_head_idx, entry_idx,\n (lane_idx % kv_frag_cols) * num_elems_per_128b<DTypeKV>())\n : 0;\n }\n cp_async::wait_group<1>();\n block.sync();\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kRoPELlama) {\n k_smem_inplace_apply_rotary<num_warps_x, num_warps_z, num_frags_y, num_frags_z,\n swizzle_mode_kv, DTypeKV>(\n (paged_kv.rope_pos_offset == nullptr ? 0 : paged_kv.rope_pos_offset[request_idx]) +\n chunk_start + iter * 16 * num_warps_z * num_frags_z,\n &k_smem, &k_smem_offset_r, rope_freq);\n block.sync();\n }\n\n // compute attention score\n compute_qk<logits_post_hook, num_frags_x, num_frags_y, num_frags_z, swizzle_mode_q,\n swizzle_mode_kv, DTypeQ, DTypeKV>(&qo_smem, &q_smem_offset_r, &k_smem,\n &k_smem_offset_r, s_frag, logits_soft_cap);\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kALiBi) {\n // TODO(Zihao): handle the case that q_offset is specified\n apply_alibi_bias<num_frags_x, num_frags_z>(\n qo_packed_idx_base,\n chunk_start +\n (iter * num_warps_z + get_warp_idx_z<num_warps_x, num_warps_z>()) * num_frags_z * 16,\n int(kv_len) - int(qo_len), group_size, alibi_slopes, s_frag);\n }\n // apply mask\n if constexpr (mask_mode == MaskMode::kCustom) {\n mask_s<mask_mode, num_frags_x, num_frags_y, num_frags_z>(\n qo_packed_idx_base,\n chunk_start +\n (iter * num_warps_z + get_warp_idx_z<num_warps_x, num_warps_z>()) * num_frags_z * 16,\n qo_len, kv_len, window_left, chunk_end, group_size, custom_mask + qk_indptr[request_idx],\n s_frag);\n } else {\n if (iter >= mask_iteration || iter < window_iteration) {\n mask_s<mask_mode, num_frags_x, num_frags_y, num_frags_z>(\n qo_packed_idx_base,\n chunk_start + (iter * num_warps_z + get_warp_idx_z<num_warps_x, num_warps_z>()) *\n num_frags_z * 16,\n qo_len, kv_len, window_left, chunk_end, group_size, nullptr, s_frag);\n }\n }\n\n // compute m,d states in online softmax\n update_mdo_states<num_frags_x, num_frags_y, num_frags_z>(s_frag, o_frag, m, d);\n\n block.sync();\n page_produce_kv<false, num_warps_x, num_warps_z, num_frags_y, num_frags_z>(\n k_smem, &kv_smem_offset_w, paged_kv, (iter + 1) * 16 * num_warps_z * num_frags_z, kv_offset,\n chunk_size);\n cp_async::commit_group();\n cp_async::wait_group<1>();\n block.sync();\n\n // compute sfm*v\n compute_sfm_v<num_frags_x, num_frags_y, num_frags_z, swizzle_mode_kv, DTypeQ, DTypeKV>(\n &v_smem, &v_smem_offset_r, s_frag, o_frag, d);\n\n block.sync();\n page_produce_kv<true, num_warps_x, num_warps_z, num_frags_y, num_frags_z>(\n v_smem, &kv_smem_offset_w, paged_kv, (iter + 1) * 16 * num_warps_z * num_frags_z, kv_offset,\n chunk_size);\n cp_async::commit_group();\n }\n cp_async::wait_group<0>();\n block.sync();\n\n // threadblock synchronization\n threadblock_sync_mdo_states<num_warps_x, num_warps_z, num_frags_x, num_frags_y, DTypeQKAccum>(\n o_frag, (float*)smem, m, d, warp_idx, lane_idx);\n\n // normalize d\n normalize_d<num_frags_x, num_frags_y>(o_frag, m, d);\n\n const uint32_t num_kv_chunks = (kv_len_safe + kv_chunk_size - 1) / kv_chunk_size;\n\n // write_back\n write_o_reg_gmem<num_warps_x, num_warps_z, num_frags_x, num_frags_y>(\n o_frag, &qo_smem, o_ptr_base, qo_packed_idx_base, qo_len,\n /*o_stride_n=*/\n partition_kv ? num_qo_heads * head_dim * num_kv_chunks : num_qo_heads * head_dim,\n /*o_stride_h=*/head_dim, group_size);\n\n // write lse\n if (lse != nullptr) {\n if (get_warp_idx_z<num_warps_x, num_warps_z>() == 0) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n uint32_t q, r;\n group_size.divmod(qo_packed_idx_base + lane_idx / 4 + j * 8 + fx * 16, q, r);\n const uint32_t qo_head_idx = kv_head_idx * group_size + r;\n const uint32_t qo_idx = q;\n if (qo_idx < qo_upper_bound) {\n if (partition_kv) {\n lse[(o_indptr[request_idx] + qo_idx * num_kv_chunks + kv_tile_idx) * num_qo_heads +\n qo_head_idx] = math::ptx_log2(d[fx][j]) + float(m[fx][j]);\n } else {\n lse[(o_indptr[request_idx] + qo_idx) * num_qo_heads + qo_head_idx] =\n math::ptx_log2(d[fx][j]) + float(m[fx][j]);\n }\n }\n }\n }\n }\n }\n}\n\ntemplate <uint32_t HEAD_DIM, LogitsPostHook LOGITS_POST_HOOK, PosEncodingMode pos_encoding_mode,\n bool ALLOW_FP16_QK_REDUCTION, MaskMode MASK_MODE, typename DTypeQ, typename DTypeKV,\n typename DTypeOut>\ncudaError_t SinglePrefillWithKVCacheDispatched(\n DTypeQ* q, DTypeKV* k, DTypeKV* v, uint8_t* custom_mask, DTypeOut* o, DTypeOut* tmp, float* lse,\n uint32_t num_qo_heads, uint32_t num_kv_heads, uint32_t qo_len, uint32_t kv_len,\n uint32_t q_stride_n, uint32_t q_stride_h, uint32_t kv_stride_n, uint32_t kv_stride_h,\n int32_t window_left, float logits_soft_cap, float sm_scale, float rope_scale, float rope_theta,\n cudaStream_t stream) {\n const float log2_rope_rcp_scale = -std::log2f(rope_scale);\n const float log2_rope_rcp_theta = -std::log2f(rope_theta);\n if (kv_len < qo_len && MASK_MODE == MaskMode::kCausal) {\n std::ostringstream err_msg;\n err_msg << \"When mask_mode is set to MaskMode::kCausal, kv_len must be greater than or equal \"\n \"to qo_len, got kv_len\"\n << kv_len << \" and qo_len \" << qo_len;\n throw std::invalid_argument(err_msg.str());\n }\n\n const uint32_t group_size = num_qo_heads / num_kv_heads;\n const uint_fastdiv group_size_fastdiv(group_size);\n constexpr uint32_t num_frags_y = HEAD_DIM / 16;\n WarpLayout warp_layout;\n int64_t unpacked_qo_len = qo_len * group_size;\n if (unpacked_qo_len > 64 && HEAD_DIM < 256) {\n warp_layout = WarpLayout::k4x1x2;\n } else {\n if (unpacked_qo_len > 16) {\n warp_layout = WarpLayout::k4x1x1;\n } else {\n warp_layout = WarpLayout::k1x4x1;\n }\n }\n\n DISPATCH_WARP_LAYOUT(warp_layout, WARP_LAYOUT, {\n constexpr uint32_t num_frags_x = get_num_frags_x<WARP_LAYOUT>();\n using DTypeQKAccum =\n typename std::conditional<ALLOW_FP16_QK_REDUCTION && std::is_same<DTypeQ, half>::value,\n half, float>::type;\n\n int dev_id = 0;\n FLASHINFER_CUDA_CALL(cudaGetDevice(&dev_id));\n int max_smem_per_sm = 0;\n FLASHINFER_CUDA_CALL(cudaDeviceGetAttribute(\n &max_smem_per_sm, cudaDevAttrMaxSharedMemoryPerMultiprocessor, dev_id));\n // we expect each sm execute two threadblocks\n // TODO(Zihao): fix the following computation\n const int num_ctas_per_sm = max_smem_per_sm > (16 * HEAD_DIM * sizeof(DTypeQ) * 16) ? 2 : 1;\n const int max_smem_per_threadblock = max_smem_per_sm / num_ctas_per_sm;\n\n constexpr uint32_t num_warps_x = get_num_warps_x<WARP_LAYOUT>();\n constexpr uint32_t num_warps_z = get_num_warps_z<WARP_LAYOUT>();\n const uint32_t max_num_frags_z_reg =\n (HEAD_DIM >= 128 && num_frags_x == 2 && pos_encoding_mode == PosEncodingMode::kRoPELlama &&\n !ALLOW_FP16_QK_REDUCTION)\n ? 2\n : (8 / num_frags_x);\n // TODO(Zihao): fix the following computation\n const uint32_t max_num_frags_z_smem =\n (max_smem_per_threadblock / (16 * HEAD_DIM * sizeof(DTypeQ)) - num_frags_x * num_warps_x) /\n (2 * num_warps_z);\n\n // control num_frags_z for maximum warp occupancy\n DISPATCH_NUM_FRAGS_Z(min(max_num_frags_z_smem, max_num_frags_z_reg), num_frags_z, {\n if constexpr (is_invalid_configuration<pos_encoding_mode, DTypeKV, DTypeQKAccum>(\n num_frags_x, num_frags_y, num_frags_z, num_warps_x, num_warps_z)) {\n // Invalid configuration, skip\n std::ostringstream err_msg;\n err_msg << \"FlashInfer Internal Error: Invalid configuration : num_frags_x=\" << num_frags_x\n << \" num_frags_y=\" << num_frags_y << \" num_frags_z=\" << num_frags_z\n << \" num_warps_x=\" << num_warps_x << \" num_warps_z=\" << num_warps_z\n << \" please create an issue (https://github.com/flashinfer-ai/flashinfer/issues)\"\n \" and report the issue to the developers.\";\n throw std::invalid_argument(err_msg.str());\n } else {\n constexpr uint32_t num_threads = (num_warps_x * num_warps_z) * warp_size;\n constexpr uint32_t num_rows_per_cta = num_frags_x * num_warps_x * 16;\n auto kernel =\n SinglePrefillWithKVCacheKernel<LOGITS_POST_HOOK, MASK_MODE, pos_encoding_mode,\n num_frags_x, num_frags_y, num_frags_z, num_warps_x,\n num_warps_z, DTypeQ, DTypeKV, DTypeQKAccum, DTypeOut>;\n // TODO(Zihao): fix the following computation\n uint32_t smem_size = (num_frags_x * num_warps_x * sizeof(DTypeQ) +\n num_frags_z * num_warps_z * 2 * sizeof(DTypeQ)) *\n 16 * HEAD_DIM;\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n int num_blocks_per_sm = 0;\n int num_sm = 0;\n FLASHINFER_CUDA_CALL(\n cudaDeviceGetAttribute(&num_sm, cudaDevAttrMultiProcessorCount, dev_id));\n FLASHINFER_CUDA_CALL(cudaOccupancyMaxActiveBlocksPerMultiprocessor(\n &num_blocks_per_sm, kernel, num_threads, smem_size));\n uint32_t max_num_kv_chunks =\n (num_blocks_per_sm * num_sm) /\n (num_kv_heads * ceil_div(qo_len * group_size, num_rows_per_cta));\n uint32_t num_chunks;\n if (max_num_kv_chunks > 0) {\n uint32_t chunk_size = max(ceil_div(kv_len, max_num_kv_chunks), 256);\n num_chunks = ceil_div(kv_len, chunk_size);\n } else {\n num_chunks = 0;\n }\n\n if (num_chunks <= 1 || tmp == nullptr) {\n // Enough parallelism, do not split-kv\n bool partition_kv = false;\n void* args[] = {(void*)&q,\n (void*)&k,\n (void*)&v,\n (void*)&custom_mask,\n (void*)&o,\n (void*)&lse,\n (void*)&qo_len,\n (void*)&kv_len,\n (void*)&partition_kv,\n (void*)&group_size_fastdiv,\n (void*)&q_stride_n,\n (void*)&q_stride_h,\n (void*)&kv_stride_n,\n (void*)&kv_stride_h,\n (void*)&window_left,\n (void*)&logits_soft_cap,\n (void*)&sm_scale,\n (void*)&log2_rope_rcp_scale,\n (void*)&log2_rope_rcp_theta};\n dim3 nblks(ceil_div(qo_len * group_size, num_rows_per_cta), 1, num_kv_heads);\n dim3 nthrs(32, num_warps_x, num_warps_z);\n\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n } else {\n // Use cooperative groups to increase occupancy\n bool partition_kv = true;\n float* tmp_lse = (float*)(tmp + num_chunks * qo_len * num_qo_heads * HEAD_DIM);\n void* args[] = {(void*)&q,\n (void*)&k,\n (void*)&v,\n (void*)&custom_mask,\n (void*)&tmp,\n (void*)&tmp_lse,\n (void*)&qo_len,\n (void*)&kv_len,\n (void*)&partition_kv,\n (void*)&group_size_fastdiv,\n (void*)&q_stride_n,\n (void*)&q_stride_h,\n (void*)&kv_stride_n,\n (void*)&kv_stride_h,\n (void*)&window_left,\n (void*)&logits_soft_cap,\n (void*)&sm_scale,\n (void*)&log2_rope_rcp_scale,\n (void*)&log2_rope_rcp_theta};\n dim3 nblks(ceil_div(qo_len * group_size, num_rows_per_cta), num_chunks, num_kv_heads);\n dim3 nthrs(32, num_warps_x, num_warps_z);\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n FLASHINFER_CUDA_CALL(MergeStates(tmp, tmp_lse, o, lse, num_chunks, qo_len, num_qo_heads,\n HEAD_DIM, stream));\n }\n }\n })\n });\n return cudaSuccess;\n}\n\ntemplate <WarpLayout WARP_LAYOUT, uint32_t HEAD_DIM, LogitsPostHook LOGITS_POST_HOOK,\n PosEncodingMode pos_encoding_mode, bool ALLOW_FP16_QK_REDUCTION, MaskMode MASK_MODE,\n typename DTypeQ, typename DTypeKV, typename DTypeOut, typename IdType>\ncudaError_t BatchPrefillWithRaggedKVCacheDispatched(\n DTypeQ* q, IdType* request_indices, IdType* q_tile_indices, IdType* kv_tile_indices,\n IdType* q_indptr, DTypeKV* k, DTypeKV* v, IdType* kv_indptr, uint8_t* custom_mask,\n IdType* qk_indptr, IdType* q_offset, IdType* k_rope_pos_offset, IdType* o_indptr, DTypeOut* o,\n DTypeOut* tmp_v, float* tmp_s, float* lse, IdType* merge_indptr, bool* block_valid_mask,\n IdType* kv_chunk_size_ptr, uint32_t total_num_rows, uint32_t num_qo_heads,\n uint32_t padded_batch_size, uint32_t num_kv_heads, uint32_t q_stride_n, uint32_t q_stride_h,\n uint32_t kv_stride_n, uint32_t kv_stride_h, int32_t window_left, float logits_soft_cap,\n float sm_scale, float rope_scale, float rope_theta, cudaStream_t stream = nullptr) {\n const float log2_rope_rcp_scale = -std::log2f(rope_scale);\n const float log2_rope_rcp_theta = -std::log2f(rope_theta);\n constexpr uint32_t num_frags_x = get_num_frags_x<WARP_LAYOUT>();\n constexpr uint32_t num_warps_x = get_num_warps_x<WARP_LAYOUT>();\n constexpr uint32_t num_warps_z = get_num_warps_z<WARP_LAYOUT>();\n const uint32_t group_size = num_qo_heads / num_kv_heads;\n const uint_fastdiv group_size_fastdiv(group_size);\n\n if (padded_batch_size == 0) {\n // No request, skip\n // this won't happen in CUDAGraph mode because we fixed the padded_batch_size\n return cudaSuccess;\n }\n\n dim3 nblks(padded_batch_size, 1, num_kv_heads);\n dim3 nthrs(32, num_warps_x, num_warps_z);\n constexpr uint32_t num_frags_y = HEAD_DIM / 16;\n using DTypeQKAccum =\n typename std::conditional<ALLOW_FP16_QK_REDUCTION && std::is_same<DTypeQ, half>::value, half,\n float>::type;\n\n int dev_id = 0;\n FLASHINFER_CUDA_CALL(cudaGetDevice(&dev_id));\n int max_smem_per_sm = 0;\n FLASHINFER_CUDA_CALL(cudaDeviceGetAttribute(&max_smem_per_sm,\n cudaDevAttrMaxSharedMemoryPerMultiprocessor, dev_id));\n // we expect each sm execute two threadblocks\n // TODO(Zihao): fix the following computation\n const int num_ctas_per_sm = max_smem_per_sm > (16 * HEAD_DIM * sizeof(DTypeQ) * 16) ? 2 : 1;\n const int max_smem_per_threadblock = max_smem_per_sm / num_ctas_per_sm;\n\n const uint32_t max_num_frags_z_reg =\n (HEAD_DIM >= 128 && num_frags_x == 2 && pos_encoding_mode == PosEncodingMode::kRoPELlama &&\n !ALLOW_FP16_QK_REDUCTION)\n ? 2\n : (8 / num_frags_x);\n // TODO(Zihao): fix the following computation\n const uint32_t max_num_frags_z_smem =\n (max_smem_per_threadblock / (16 * HEAD_DIM * sizeof(DTypeQ)) - num_frags_x * num_warps_x) /\n (2 * num_warps_z);\n\n DISPATCH_NUM_FRAGS_Z(min(max_num_frags_z_smem, max_num_frags_z_reg), num_frags_z, {\n if constexpr (is_invalid_configuration<pos_encoding_mode, DTypeKV, DTypeQKAccum>(\n num_frags_x, num_frags_y, num_frags_z, num_warps_x, num_warps_z)) {\n // Invalid configuration, skip\n std::ostringstream err_msg;\n err_msg << \"FlashInfer Internal Error: Invalid configuration : num_frags_x=\" << num_frags_x\n << \" num_frags_y=\" << num_frags_y << \" num_frags_z=\" << num_frags_z\n << \" num_warps_x=\" << num_warps_x << \" num_warps_z=\" << num_warps_z\n << \" please create an issue (https://github.com/flashinfer-ai/flashinfer/issues)\"\n \" and report the issue to the developers.\";\n throw std::invalid_argument(err_msg.str());\n } else {\n // TODO(Zihao): fix the following computation\n uint32_t smem_size = (num_frags_x * num_warps_x * sizeof(DTypeQ) +\n num_frags_z * num_warps_z * 2 * sizeof(DTypeQ)) *\n 16 * HEAD_DIM;\n auto kernel = BatchPrefillWithRaggedKVCacheKernel<\n LOGITS_POST_HOOK, MASK_MODE, pos_encoding_mode, num_frags_x, num_frags_y, num_frags_z,\n num_warps_x, num_warps_z, DTypeQ, DTypeKV, DTypeQKAccum, DTypeOut, IdType>;\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n if (tmp_v == nullptr) {\n // do not partition kv\n bool partition_kv = false;\n\n void* args[] = {(void*)&q,\n (void*)&request_indices,\n (void*)&q_tile_indices,\n (void*)&kv_tile_indices,\n (void*)&q_indptr,\n (void*)&k,\n (void*)&v,\n (void*)&kv_indptr,\n (void*)&custom_mask,\n (void*)&qk_indptr,\n (void*)&q_offset,\n (void*)&k_rope_pos_offset,\n (void*)&o_indptr,\n (void*)&o,\n (void*)&lse,\n (void*)&block_valid_mask,\n (void*)&kv_chunk_size_ptr,\n (void*)&partition_kv,\n (void*)&group_size_fastdiv,\n (void*)&q_stride_n,\n (void*)&q_stride_h,\n (void*)&kv_stride_n,\n (void*)&kv_stride_h,\n (void*)&window_left,\n (void*)&logits_soft_cap,\n (void*)&sm_scale,\n (void*)&log2_rope_rcp_scale,\n (void*)&log2_rope_rcp_theta};\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n } else {\n // partition kv\n bool partition_kv = true;\n void* args[] = {(void*)&q,\n (void*)&request_indices,\n (void*)&q_tile_indices,\n (void*)&kv_tile_indices,\n (void*)&q_indptr,\n (void*)&k,\n (void*)&v,\n (void*)&kv_indptr,\n (void*)&custom_mask,\n (void*)&qk_indptr,\n (void*)&q_offset,\n (void*)&k_rope_pos_offset,\n (void*)&o_indptr,\n (void*)&tmp_v,\n (void*)&tmp_s,\n (void*)&block_valid_mask,\n (void*)&kv_chunk_size_ptr,\n (void*)&partition_kv,\n (void*)&group_size_fastdiv,\n (void*)&q_stride_n,\n (void*)&q_stride_h,\n (void*)&kv_stride_n,\n (void*)&kv_stride_h,\n (void*)&window_left,\n (void*)&logits_soft_cap,\n (void*)&sm_scale,\n (void*)&log2_rope_rcp_scale,\n (void*)&log2_rope_rcp_theta};\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n FLASHINFER_CUDA_CALL(VariableLengthMergeStates(\n tmp_v, tmp_s, merge_indptr, o, lse, total_num_rows, num_qo_heads, HEAD_DIM, stream));\n }\n }\n });\n return cudaSuccess;\n}\n\ntemplate <PageStorage page_storage, WarpLayout WARP_LAYOUT, uint32_t HEAD_DIM,\n LogitsPostHook LOGITS_POST_HOOK, PosEncodingMode pos_encoding_mode,\n bool ALLOW_FP16_QK_REDUCTION, MaskMode MASK_MODE, typename DTypeQ, typename DTypeKV,\n typename DTypeOut, typename IdType>\ncudaError_t BatchPrefillWithPagedKVCacheDispatched(\n DTypeQ* q, IdType* request_indices, IdType* q_tile_indices, IdType* kv_tile_indices,\n IdType* q_indptr, IdType* q_offset, paged_kv_t<page_storage, DTypeKV, IdType> paged_kv,\n uint8_t* custom_mask, IdType* qk_indptr, IdType* o_indptr, DTypeOut* o, DTypeOut* tmp_v,\n float* tmp_s, float* lse, IdType* merge_indptr, bool* block_valid_mask,\n IdType* kv_chunk_size_ptr, uint32_t total_num_rows, uint32_t num_qo_heads,\n uint32_t padded_batch_size, int32_t window_left, float logits_soft_cap, float sm_scale,\n float rope_scale, float rope_theta, cudaStream_t stream) {\n const float log2_rope_rcp_scale = -std::log2f(rope_scale);\n const float log2_rope_rcp_theta = -std::log2f(rope_theta);\n constexpr uint32_t num_frags_x = get_num_frags_x<WARP_LAYOUT>();\n constexpr uint32_t num_warps_x = get_num_warps_x<WARP_LAYOUT>();\n constexpr uint32_t num_warps_z = get_num_warps_z<WARP_LAYOUT>();\n const uint32_t num_kv_heads = paged_kv.num_heads;\n const uint32_t group_size = num_qo_heads / num_kv_heads;\n const uint_fastdiv group_size_fastdiv(group_size);\n\n if (padded_batch_size == 0) {\n // No request, skip\n // this won't happen in CUDAGraph mode because we fixed the padded_batch_size\n return cudaSuccess;\n }\n\n dim3 nblks(padded_batch_size, 1, num_kv_heads);\n dim3 nthrs(32, num_warps_x, num_warps_z);\n\n constexpr uint32_t num_frags_y = HEAD_DIM / 16;\n using DTypeQKAccum =\n typename std::conditional<ALLOW_FP16_QK_REDUCTION && std::is_same<DTypeQ, half>::value, half,\n float>::type;\n\n int dev_id = 0;\n FLASHINFER_CUDA_CALL(cudaGetDevice(&dev_id));\n int max_smem_per_sm = 0;\n FLASHINFER_CUDA_CALL(cudaDeviceGetAttribute(&max_smem_per_sm,\n cudaDevAttrMaxSharedMemoryPerMultiprocessor, dev_id));\n // we expect each sm execute two threadblocks\n // TODO(Zihao): fix the following computation\n const int num_ctas_per_sm = max_smem_per_sm > (16 * HEAD_DIM * sizeof(DTypeQ) * 16) ? 2 : 1;\n const int max_smem_per_threadblock = max_smem_per_sm / num_ctas_per_sm;\n\n const uint32_t max_num_frags_z_reg =\n (HEAD_DIM >= 128 && num_frags_x == 2 && pos_encoding_mode == PosEncodingMode::kRoPELlama &&\n !ALLOW_FP16_QK_REDUCTION)\n ? 2\n : (8 / num_frags_x);\n // TODO(Zihao): fix the following computation\n const uint32_t max_num_frags_z_smem =\n (max_smem_per_threadblock / (16 * HEAD_DIM * sizeof(DTypeQ)) - num_frags_x * num_warps_x) /\n (2 * num_warps_z);\n\n DISPATCH_NUM_FRAGS_Z(min(max_num_frags_z_smem, max_num_frags_z_reg), num_frags_z, {\n if constexpr (is_invalid_configuration<pos_encoding_mode, DTypeKV, DTypeQKAccum>(\n num_frags_x, num_frags_y, num_frags_z, num_warps_x, num_warps_z)) {\n // Invalid configuration, skip\n std::ostringstream err_msg;\n err_msg << \"FlashInfer Internal Error: Invalid configuration : num_frags_x=\" << num_frags_x\n << \" num_frags_y=\" << num_frags_y << \" num_frags_z=\" << num_frags_z\n << \" num_warps_x=\" << num_warps_x << \" num_warps_z=\" << num_warps_z\n << \" please create an issue (https://github.com/flashinfer-ai/flashinfer/issues)\"\n \" and report the issue to the developers.\";\n throw std::invalid_argument(err_msg.str());\n } else {\n // TODO(Zihao): fix the following computation\n uint32_t smem_size = (num_frags_x * num_warps_x * sizeof(DTypeQ) +\n num_frags_z * num_warps_z * 2 * sizeof(DTypeQ)) *\n 16 * HEAD_DIM;\n auto kernel = BatchPrefillWithPagedKVCacheKernel<\n LOGITS_POST_HOOK, MASK_MODE, pos_encoding_mode, num_frags_x, num_frags_y, num_frags_z,\n num_warps_x, num_warps_z, page_storage, DTypeQ, DTypeKV, DTypeQKAccum, DTypeOut, IdType>;\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n if (tmp_v == nullptr) {\n // do not partition kv\n bool partition_kv = false;\n void* args[] = {(void*)&request_indices,\n (void*)&q_tile_indices,\n (void*)&kv_tile_indices,\n (void*)&q,\n (void*)&paged_kv,\n (void*)&q_indptr,\n (void*)&custom_mask,\n (void*)&qk_indptr,\n (void*)&q_offset,\n (void*)&o_indptr,\n (void*)&o,\n (void*)&lse,\n (void*)&block_valid_mask,\n (void*)&kv_chunk_size_ptr,\n (void*)&partition_kv,\n (void*)&group_size_fastdiv,\n (void*)&window_left,\n (void*)&logits_soft_cap,\n (void*)&sm_scale,\n (void*)&log2_rope_rcp_scale,\n (void*)&log2_rope_rcp_theta};\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n } else {\n bool partition_kv = true;\n void* args[] = {(void*)&request_indices,\n (void*)&q_tile_indices,\n (void*)&kv_tile_indices,\n (void*)&q,\n (void*)&paged_kv,\n (void*)&q_indptr,\n (void*)&custom_mask,\n (void*)&qk_indptr,\n (void*)&q_offset,\n (void*)&o_indptr,\n (void*)&tmp_v,\n (void*)&tmp_s,\n (void*)&block_valid_mask,\n (void*)&kv_chunk_size_ptr,\n (void*)&partition_kv,\n (void*)&group_size_fastdiv,\n (void*)&window_left,\n (void*)&logits_soft_cap,\n (void*)&sm_scale,\n (void*)&log2_rope_rcp_scale,\n (void*)&log2_rope_rcp_theta};\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n FLASHINFER_CUDA_CALL(VariableLengthMergeStates(\n tmp_v, tmp_s, merge_indptr, o, lse, total_num_rows, num_qo_heads, HEAD_DIM, stream));\n }\n }\n });\n return cudaSuccess;\n}\n\n} // namespace flashinfer\n\n#endif // FLASHINFER_PREFILL_CUH_\n"},"after_code":{"kind":"string","value":"/*\n * Copyright (c) 2023 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_PREFILL_CUH_\n#define FLASHINFER_PREFILL_CUH_\n#include <cooperative_groups.h>\n#include <cuda_bf16.h>\n#include <cuda_fp16.h>\n#ifdef FLASHINFER_ENABLE_FP8\n#include <cuda_fp8.h>\n#endif\n#include <cuda_runtime.h>\n\n#include \"../cp_async.cuh\"\n#include \"../fastdiv.cuh\"\n#include \"../frag_layout_swizzle.cuh\"\n#include \"../layout.cuh\"\n#include \"../math.cuh\"\n#include \"../mma.cuh\"\n#include \"../page.cuh\"\n#include \"../permuted_smem.cuh\"\n#include \"../pos_enc.cuh\"\n#include \"../utils.cuh\"\n#include \"cascade.cuh\"\n#include \"logits_post_hook.cuh\"\n#include \"mask.cuh\"\n#include \"warp_layout.cuh\"\n\nnamespace flashinfer {\n\nnamespace cg = cooperative_groups;\nusing cp_async::SharedMemFillMode;\nusing mma::MMAMode;\n\nconstexpr uint32_t warp_size = 32;\n\nnamespace {\n\ntemplate <PosEncodingMode pos_encoding_mode, typename DTypeKV, typename DTypeQKAccum>\nconstexpr bool is_invalid_configuration(uint32_t num_frags_x, uint32_t num_frags_y,\n uint32_t num_frags_z, uint32_t num_warps_x,\n uint32_t num_warps_z) {\n return ((num_frags_y < 4) || (num_frags_y == 4 && num_frags_z % 2 == 1) ||\n (num_frags_y > 4 && num_frags_y % (2 * num_warps_x) != 0) ||\n (num_frags_x * (8 * num_frags_y + 2 * sizeof(DTypeQKAccum) * num_frags_z) >= 256) ||\n (sizeof(DTypeKV) == 1 && num_frags_z * 2 % num_warps_x != 0) ||\n (sizeof(DTypeKV) == 1 && pos_encoding_mode == PosEncodingMode::kRoPELlama));\n}\n\ntemplate <uint32_t num_warps_x, uint32_t num_warps_z>\n__device__ __forceinline__ uint32_t get_warp_idx_x() {\n if constexpr (num_warps_x == 1) {\n return 0;\n } else {\n return threadIdx.y;\n }\n}\n\ntemplate <uint32_t num_warps_x, uint32_t num_warps_z>\n__device__ __forceinline__ uint32_t get_warp_idx_z() {\n if constexpr (num_warps_z == 1) {\n return 0;\n } else {\n return threadIdx.z;\n }\n}\n\ntemplate <uint32_t num_warps_x, uint32_t num_warps_z>\n__device__ __forceinline__ uint32_t get_warp_idx() {\n return get_warp_idx_z<num_warps_x, num_warps_z>() * num_warps_x +\n get_warp_idx_x<num_warps_x, num_warps_z>();\n}\n\n/*!\n * \\brief Apply Llama style rotary embedding to two 16x16 fragments.\n * \\tparam T The data type of the input fragments.\n * \\param x_first_half First fragment x[offset:offset+16, j*16:(j+1)*16]\n * \\param x_second_half Second fragment x[offset:offset*16, j*16+d/2:(j+1)*16+d/2]\n * \\param rope_freq Rope frequency\n * \\param offset The offset of the first row in both fragments.\n * \\param scale A scale factor applied to the result (used to multiply sm_scale).\n * \\note The sin/cos computation is slow, especially for A100 GPUs which has low\n * non tensor-ops flops, will optimize in the future.\n */\ntemplate <typename T>\n__device__ __forceinline__ void k_frag_apply_llama_rope(T* x_first_half, T* x_second_half,\n const float* rope_freq,\n const uint32_t kv_offset,\n float scale = 1.f) {\n static_assert(sizeof(T) == 2);\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n float cos, sin, tmp;\n // 0 1 | 2 3\n // ---------\n // 4 5 | 6 7\n uint32_t i = reg_id / 4, j = (reg_id % 4) / 2;\n __sincosf(float(kv_offset + 8 * i) * rope_freq[2 * j + reg_id % 2], &sin, &cos);\n tmp = x_first_half[reg_id];\n x_first_half[reg_id] = (tmp * cos - (float)x_second_half[reg_id] * sin) * scale;\n x_second_half[reg_id] = ((float)x_second_half[reg_id] * cos + tmp * sin) * scale;\n }\n}\n\ntemplate <typename T>\n__device__ __forceinline__ void q_frag_apply_llama_rope(T* x_first_half, T* x_second_half,\n const float* rope_freq,\n const uint32_t qo_packed_offset,\n const uint_fastdiv group_size,\n float scale = 1.f) {\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n float cos, sin, tmp;\n // 0 1 | 4 5\n // ---------\n // 2 3 | 6 7\n uint32_t i = ((reg_id % 4) / 2), j = (reg_id / 4);\n __sincosf(float((qo_packed_offset + 8 * i) / group_size) * rope_freq[2 * j + reg_id % 2], &sin,\n &cos);\n tmp = x_first_half[reg_id];\n x_first_half[reg_id] = (tmp * cos - (float)x_second_half[reg_id] * sin) * scale;\n x_second_half[reg_id] = ((float)x_second_half[reg_id] * cos + tmp * sin) * scale;\n }\n}\n\ntemplate <typename T, typename IdType>\n__device__ __forceinline__ void q_frag_apply_llama_rope_with_pos(\n T* x_first_half, T* x_second_half, const float* rope_freq, const uint32_t qo_packed_offset,\n const uint_fastdiv group_size, const IdType* q_offset, float scale = 1.f) {\n float pos[2] = {static_cast<float>(q_offset[qo_packed_offset / group_size]),\n static_cast<float>(q_offset[(qo_packed_offset + 8) / group_size])};\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n float cos, sin, tmp;\n // 0 1 | 4 5\n // ---------\n // 2 3 | 6 7\n uint32_t i = ((reg_id % 4) / 2), j = (reg_id / 4);\n __sincosf(pos[i] * rope_freq[2 * j + reg_id % 2], &sin, &cos);\n tmp = x_first_half[reg_id];\n x_first_half[reg_id] = (tmp * cos - (float)x_second_half[reg_id] * sin) * scale;\n x_second_half[reg_id] = ((float)x_second_half[reg_id] * cos + tmp * sin) * scale;\n }\n}\n\n/*!\n * \\brief Produce k/v fragments from global memory to shared memory.\n * \\tparam fill_mode The fill mode of the shared memory.\n * \\tparam num_frags_y The number of fragments in y dimension.\n * \\tparam num_frags_z The number of fragments in z dimension.\n * \\tparam num_warps The number of warps in the threadblock.\n * \\tparam T The data type of the input tensor.\n * \\param smem The shared memory to store kv fragments.\n * \\param gptr The global memory pointer.\n * \\param qkv_info The tensor info of the input tensor.\n * \\param kv_idx_base The base kv index.\n * \\param kv_len The length of kv tensor.\n */\ntemplate <SharedMemFillMode fill_mode, uint32_t num_warps_x, uint32_t num_warps_z,\n uint32_t num_frags_y, uint32_t num_frags_z, SwizzleMode swizzle_mode, typename T>\n__device__ __forceinline__ void produce_kv(smem_t<swizzle_mode> smem, uint32_t* smem_offset,\n T** gptr, const uint32_t kv_stride_n,\n const uint32_t kv_idx_base, const uint32_t kv_len) {\n // NOTE(Zihao): for fp8, this function doesn't work for head_dim = 64 at the moment\n constexpr uint32_t head_dim = num_frags_y * 16;\n constexpr uint32_t num_warps = num_warps_x * num_warps_z;\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<T>();\n const uint32_t warp_idx = get_warp_idx<num_warps_x, num_warps_z>(), lane_idx = threadIdx.x;\n\n if constexpr (swizzle_mode == SwizzleMode::k128B) {\n uint32_t kv_idx = kv_idx_base + warp_idx * 4 + lane_idx / 8;\n // NOTE(Zihao): num_frags_z * 4 / num_warps_x = num_warps_z * num_frags_z * 4 / num_warps\n static_assert(num_frags_z * 4 % num_warps_x == 0);\n#pragma unroll\n for (uint32_t i = 0; i < num_frags_z * 4 / num_warps_x; ++i) {\n#pragma unroll\n for (uint32_t j = 0; j < num_frags_y / (8 / sizeof(T)); ++j) {\n smem.load_128b_async<fill_mode>(*smem_offset, *gptr, kv_idx < kv_len);\n *smem_offset = smem.template advance_offset_by_column<8>(*smem_offset, j);\n *gptr += 8 * num_elems_per_128b<T>();\n }\n kv_idx += num_warps * 4;\n *smem_offset =\n smem.template advance_offset_by_row<num_warps * 4, channel_size_128b_kv>(*smem_offset) -\n sizeof(T) * num_frags_y;\n *gptr += num_warps * 4 * kv_stride_n - sizeof(T) * num_frags_y * num_elems_per_128b<T>();\n }\n *smem_offset -= num_warps_z * num_frags_z * 16 * channel_size_128b_kv;\n } else {\n uint32_t kv_idx = kv_idx_base + warp_idx * 8 + lane_idx / 4;\n // NOTE(Zihao): num_frags_z * 2 / num_warps_x = num_warps_z * num_frags_z * 2 / num_warps\n static_assert(num_frags_z * 2 % num_warps_x == 0);\n#pragma unroll\n for (uint32_t i = 0; i < num_frags_z * 2 / num_warps_x; ++i) {\n smem.load_128b_async<fill_mode>(*smem_offset, *gptr, kv_idx < kv_len);\n *smem_offset =\n smem.template advance_offset_by_row<num_warps * 8, channel_size_128b_kv>(*smem_offset);\n kv_idx += num_warps * 8;\n *gptr += num_warps * 8 * kv_stride_n;\n }\n *smem_offset -= num_warps_z * num_frags_z * 16 * channel_size_128b_kv;\n }\n}\n\ntemplate <bool produce_v, uint32_t num_warps_x, uint32_t num_warps_z, uint32_t num_frags_y,\n uint32_t num_frags_z, PageStorage page_storage, SwizzleMode swizzle_mode, typename DType,\n typename IdType>\n__device__ __forceinline__ void page_produce_kv(smem_t<swizzle_mode> smem, uint32_t* smem_offset,\n paged_kv_t<page_storage, DType, IdType>& paged_kv,\n const uint32_t kv_idx_base, const size_t* kv_offset,\n const uint32_t kv_len) {\n // NOTE(Zihao): for fp8, this function doesn't work for head_dim = 64 at the moment\n constexpr SharedMemFillMode fill_mode =\n produce_v ? SharedMemFillMode::kFillZero : SharedMemFillMode::kNoFill;\n constexpr uint32_t head_dim = num_frags_y * 16;\n constexpr uint32_t num_warps = num_warps_x * num_warps_z;\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<DType>();\n const uint32_t warp_idx = get_warp_idx<num_warps_x, num_warps_z>(), lane_idx = threadIdx.x;\n if constexpr (swizzle_mode == SwizzleMode::k128B) {\n uint32_t kv_idx = kv_idx_base + warp_idx * 4 + lane_idx / 8;\n // NOTE(Zihao): num_frags_z * 4 / num_warps_x = num_warps_z * num_frags_z * 4 / num_warps\n static_assert(num_frags_z * 4 % num_warps_x == 0);\n#pragma unroll\n for (uint32_t i = 0; i < num_frags_z * 4 / num_warps_x; ++i) {\n DType* gptr = produce_v ? paged_kv.v_data + kv_offset[i] : paged_kv.k_data + kv_offset[i];\n#pragma unroll\n for (uint32_t j = 0; j < num_frags_y / (8 / sizeof(DType)); ++j) {\n smem.load_128b_async<fill_mode>(*smem_offset, gptr, kv_idx < kv_len);\n *smem_offset = smem.template advance_offset_by_column<8>(*smem_offset, j);\n gptr += 8 * num_elems_per_128b<DType>();\n }\n kv_idx += num_warps * 4;\n *smem_offset =\n smem.template advance_offset_by_row<num_warps * 4, channel_size_128b_kv>(*smem_offset) -\n sizeof(DType) * num_frags_y;\n }\n *smem_offset -= num_warps_z * num_frags_z * 16 * channel_size_128b_kv;\n } else {\n uint32_t kv_idx = kv_idx_base + warp_idx * 8 + lane_idx / 4;\n // NOTE(Zihao): num_frags_z * 2 / num_warps_x = num_warps_z * num_frags_z * 2 / num_warps\n static_assert(num_frags_z * 2 % num_warps_x == 0);\n#pragma unroll\n for (uint32_t i = 0; i < num_frags_z * 2 / num_warps_x; ++i) {\n DType* gptr = produce_v ? paged_kv.v_data + kv_offset[i] : paged_kv.k_data + kv_offset[i];\n smem.load_128b_async<fill_mode>(*smem_offset, gptr, kv_idx < kv_len);\n kv_idx += num_warps * 8;\n *smem_offset =\n smem.template advance_offset_by_row<num_warps * 8, channel_size_128b_kv>(*smem_offset);\n }\n *smem_offset -= num_warps_z * num_frags_z * 16 * channel_size_128b_kv;\n }\n}\n\ntemplate <uint32_t num_frags_y>\n__device__ __forceinline__ void init_rope_freq(float (*rope_freq)[4],\n const float log2_rope_rcp_scale,\n const float log2_rope_rcp_theta) {\n constexpr uint32_t head_dim = num_frags_y * 16;\n const uint32_t lane_idx = threadIdx.x;\n#pragma unroll\n for (uint32_t fy = 0; fy < num_frags_y / 2; ++fy) {\n#pragma unroll\n for (uint32_t j = 0; j < 4; ++j) {\n rope_freq[fy][j] = math::ptx_exp2(\n log2_rope_rcp_scale +\n log2_rope_rcp_theta *\n float(2 * ((fy * 16 + (j / 2) * 8 + (lane_idx % 4) * 2 + (j % 2)) % (head_dim / 2))) /\n float(head_dim));\n }\n }\n}\n\ntemplate <uint32_t num_frags_x, uint32_t num_frags_y, typename DTypeQKAccum>\n__device__ __forceinline__ void init_states(float (*o_frag)[num_frags_y][8], DTypeQKAccum (*m)[2],\n float (*d)[2]) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t fy = 0; fy < num_frags_y; ++fy) {\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n o_frag[fx][fy][reg_id] = 0.f;\n }\n }\n }\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n m[fx][j] = DTypeQKAccum(-5e4);\n d[fx][j] = 1.f;\n }\n }\n}\n\ntemplate <uint32_t num_warps_x, uint32_t num_warps_z, uint32_t num_frags_x, uint32_t num_frags_y,\n SwizzleMode swizzle_mode, typename DTypeQ>\n__device__ __forceinline__ void load_q_global_smem(uint32_t packed_offset,\n const uint32_t qo_upper_bound,\n DTypeQ* q_ptr_base, const uint32_t q_stride_n,\n const uint32_t q_stride_h,\n const uint_fastdiv group_size,\n smem_t<swizzle_mode>* q_smem) {\n constexpr uint32_t head_dim = num_frags_y * 16;\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n const uint32_t lane_idx = threadIdx.x, warp_idx_x = get_warp_idx_x<num_warps_x, num_warps_z>();\n\n if (get_warp_idx_z<num_warps_x, num_warps_z>() == 0) {\n uint32_t q_smem_offset_w = q_smem->get_permuted_offset<channel_size_128b_q>(\n warp_idx_x * num_frags_x * 16 + lane_idx / 8, lane_idx % 8);\n\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t j = 0; j < 4; ++j) {\n uint32_t q, r;\n group_size.divmod(packed_offset + lane_idx / 8 + fx * 16 + j * 4, q, r);\n const uint32_t q_idx = q;\n DTypeQ* q_ptr = q_ptr_base + q * q_stride_n + r * q_stride_h;\n#pragma unroll\n for (uint32_t fyo = 0; fyo < num_frags_y / 4; ++fyo) {\n // load q fragment from gmem to smem\n q_smem->load_128b_async<SharedMemFillMode::kNoFill>(q_smem_offset_w, q_ptr,\n q_idx < qo_upper_bound);\n q_smem_offset_w = q_smem->template advance_offset_by_column<8>(q_smem_offset_w, fyo);\n q_ptr += 8 * num_elems_per_128b<DTypeQ>();\n }\n q_smem_offset_w =\n q_smem->template advance_offset_by_row<4, channel_size_128b_q>(q_smem_offset_w) -\n 2 * num_frags_y;\n }\n }\n }\n}\n\ntemplate <uint32_t num_warps_x, uint32_t num_warps_z, uint32_t num_frags_x, uint32_t num_frags_y,\n SwizzleMode swizzle_mode, typename DTypeQ>\n__device__ __forceinline__ void q_smem_inplace_apply_rotary_multiply_sm_scale(\n const uint32_t q_packed_idx, const uint32_t qo_len, const uint32_t kv_len,\n const uint_fastdiv group_size, smem_t<swizzle_mode>* q_smem, uint32_t* q_smem_offset_r,\n float (*rope_freq)[4], const float sm_scale) {\n if (get_warp_idx_z<num_warps_x, num_warps_z>() == 0) {\n constexpr uint32_t head_dim = num_frags_y * 16;\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n const uint32_t lane_idx = threadIdx.x;\n uint32_t q_frag_local[2][4];\n static_assert(num_frags_y % 4 == 0, \"num_frags_y must be a multiple of 4\");\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n uint32_t q_smem_offset_r_first_half = *q_smem_offset_r;\n#pragma unroll\n for (uint32_t fyi = 0; fyi < num_frags_y / 2; ++fyi) {\n q_smem->ldmatrix_m8n8x4(q_smem_offset_r_first_half, q_frag_local[0]);\n uint32_t q_smem_offset_r_last_half =\n q_smem->template advance_offset_by_column<num_frags_y>(q_smem_offset_r_first_half, 0);\n q_smem->ldmatrix_m8n8x4(q_smem_offset_r_last_half, q_frag_local[1]);\n q_frag_apply_llama_rope<DTypeQ>(\n (DTypeQ*)q_frag_local[0], (DTypeQ*)q_frag_local[1], rope_freq[fyi],\n q_packed_idx + kv_len * group_size - qo_len * group_size + fx * 16 + lane_idx / 4,\n group_size, sm_scale);\n q_smem->stmatrix_m8n8x4(q_smem_offset_r_last_half, q_frag_local[1]);\n q_smem->stmatrix_m8n8x4(q_smem_offset_r_first_half, q_frag_local[0]);\n q_smem_offset_r_first_half =\n q_smem->template advance_offset_by_column<2>(q_smem_offset_r_first_half, fyi);\n }\n *q_smem_offset_r += 16 * channel_size_128b_q;\n }\n *q_smem_offset_r -= num_frags_x * 16 * channel_size_128b_q;\n }\n}\n\ntemplate <uint32_t num_warps_x, uint32_t num_warps_z, uint32_t num_frags_x, uint32_t num_frags_y,\n SwizzleMode swizzle_mode, typename DTypeQ, typename IdType>\n__device__ __forceinline__ void q_smem_inplace_apply_rotary_with_pos_multiply_sm_scale(\n const uint32_t q_packed_idx_base, const IdType* q_offset, smem_t<swizzle_mode>* q_smem,\n const uint_fastdiv group_size, uint32_t* q_smem_offset_r, float (*rope_freq)[4],\n const float sm_scale) {\n if (get_warp_idx_z<num_warps_x, num_warps_z>() == 0) {\n constexpr uint32_t head_dim = num_frags_y * 16;\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n const uint32_t lane_idx = threadIdx.x;\n uint32_t q_frag_local[2][4];\n static_assert(num_frags_y % 4 == 0, \"num_frags_y must be a multiple of 4\");\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n uint32_t q_smem_offset_r_first_half = *q_smem_offset_r;\n#pragma unroll\n for (uint32_t fyi = 0; fyi < num_frags_y / 2; ++fyi) {\n q_smem->ldmatrix_m8n8x4(q_smem_offset_r_first_half, q_frag_local[0]);\n uint32_t q_smem_offset_r_last_half =\n q_smem->template advance_offset_by_column<num_frags_y>(q_smem_offset_r_first_half, 0);\n q_smem->ldmatrix_m8n8x4(q_smem_offset_r_last_half, q_frag_local[1]);\n q_frag_apply_llama_rope_with_pos<DTypeQ>(\n (DTypeQ*)q_frag_local[0], (DTypeQ*)q_frag_local[1], rope_freq[fyi],\n q_packed_idx_base + fx * 16 + lane_idx / 4, group_size, q_offset, sm_scale);\n q_smem->stmatrix_m8n8x4(q_smem_offset_r_last_half, q_frag_local[1]);\n q_smem->stmatrix_m8n8x4(q_smem_offset_r_first_half, q_frag_local[0]);\n q_smem_offset_r_first_half =\n q_smem->template advance_offset_by_column<2>(q_smem_offset_r_first_half, fyi);\n }\n *q_smem_offset_r += 16 * channel_size_128b_q;\n }\n *q_smem_offset_r -= num_frags_x * 16 * channel_size_128b_q;\n }\n}\n\ntemplate <uint32_t num_warps_x, uint32_t num_warps_z, uint32_t num_frags_x, uint32_t num_frags_y,\n SwizzleMode swizzle_mode, typename DTypeQ>\n__device__ __forceinline__ void q_smem_inplace_multiply_sm_scale(smem_t<swizzle_mode>* q_smem,\n const float sm_scale) {\n const uint32_t warp_idx = get_warp_idx<num_warps_x, num_warps_z>(), lane_idx = threadIdx.x;\n constexpr uint32_t head_dim = num_frags_y * 16;\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n constexpr uint32_t num_warps = num_warps_x * num_warps_z;\n#pragma unroll\n for (uint32_t i = 0; i < num_frags_x * head_dim / (num_warps_z * 16); ++i) {\n vec_t<DTypeQ, 8> tmp;\n tmp.load((DTypeQ*)(q_smem->base) + (i * num_warps + warp_idx) * 256 + lane_idx * 8);\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n tmp[reg_id] *= sm_scale;\n }\n tmp.store((DTypeQ*)(q_smem->base) + (i * num_warps + warp_idx) * 256 + lane_idx * 8);\n }\n}\n\ntemplate <uint32_t num_warps_x, uint32_t num_warps_z, uint32_t num_frags_y, uint32_t num_frags_z,\n SwizzleMode swizzle_mode, typename DTypeKV>\n__device__ __forceinline__ void k_smem_inplace_apply_rotary(const uint32_t kv_idx_base,\n smem_t<swizzle_mode>* k_smem,\n uint32_t* k_smem_offset_r,\n float (*rope_freq)[4]) {\n static_assert(sizeof(DTypeKV) == 2);\n constexpr uint32_t head_dim = num_frags_y * 16;\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<DTypeKV>();\n uint32_t k_frag_local[2][4];\n const uint32_t lane_idx = threadIdx.x;\n if constexpr (num_frags_y == 4 && num_warps_x == 4) {\n static_assert(num_warps_z == 1);\n const uint32_t warp_idx = get_warp_idx_x<num_warps_x, num_warps_z>();\n // horizontal-axis: y\n // horizontal-axis: y\n // vertical-axis: z\n // | 1-16 | 16-32 | 32-48 | 48-64 |\n // | 1-16 | warp_idx=0 | warp_idx=1 | warp_idx=0 | warp_idx=1 |\n // | 16-32 | warp_idx=2 | warp_idx=3 | warp_idx=2 | warp_idx=3 |\n static_assert(num_frags_z % 2 == 0,\n \"when num_frags_y == 4, num_frags_z must be a multiple of 2\");\n uint32_t kv_idx = kv_idx_base + (warp_idx / 2) * 16 + lane_idx / 4;\n *k_smem_offset_r =\n (*k_smem_offset_r ^ (0x2 * (warp_idx % 2))) + (warp_idx / 2) * 16 * channel_size_128b_kv;\n#pragma unroll\n for (uint32_t i = 0; i < num_frags_z / 2; ++i) {\n // uint32_t fz = warp_idx / 2 + i * 2;\n uint32_t k_smem_offset_r_first_half = *k_smem_offset_r;\n uint32_t fyi = (warp_idx % 2);\n k_smem->ldmatrix_m8n8x4(k_smem_offset_r_first_half, k_frag_local[0]);\n uint32_t k_smem_offset_r_last_half =\n k_smem->template advance_offset_by_column<4>(k_smem_offset_r_first_half, 0);\n k_smem->ldmatrix_m8n8x4(k_smem_offset_r_last_half, k_frag_local[1]);\n k_frag_apply_llama_rope<DTypeKV>((DTypeKV*)k_frag_local[0], (DTypeKV*)k_frag_local[1],\n rope_freq[fyi], kv_idx);\n k_smem->stmatrix_m8n8x4(k_smem_offset_r_last_half, k_frag_local[1]);\n k_smem->stmatrix_m8n8x4(k_smem_offset_r_first_half, k_frag_local[0]);\n *k_smem_offset_r += 32 * channel_size_128b_kv;\n kv_idx += 32;\n }\n *k_smem_offset_r = (*k_smem_offset_r ^ (0x2 * (warp_idx % 2))) -\n ((warp_idx / 2) + num_frags_z) * 16 * channel_size_128b_kv;\n } else {\n const uint32_t warp_idx_x = get_warp_idx_x<num_warps_x, num_warps_z>(),\n warp_idx_z = get_warp_idx_z<num_warps_x, num_warps_z>();\n static_assert(num_frags_y % (2 * num_warps_x) == 0);\n // horizontal axis: y\n // vertical axis: z\n // | (warp_idx_z, warp_idx_x) | 1-16 | 16-32 | 32-48 | 48-64 | ...\n // | 1-16*num_frags_z | (0, 0) | (0, 1) | (0, 2) | (0, 3) | ...\n // | 16*num_frags_z-32*num_frags_z | (1, 0) | (1, 1) | (1, 2) | (1, 3) | ...\n // ...\n uint32_t kv_idx = kv_idx_base + (warp_idx_z * num_frags_z * 16) + lane_idx / 4;\n *k_smem_offset_r = *k_smem_offset_r ^ (0x2 * warp_idx_x);\n#pragma unroll\n for (uint32_t i = 0; i < num_frags_z; ++i) {\n uint32_t k_smem_offset_r_first_half = *k_smem_offset_r;\n#pragma unroll\n for (uint32_t j = 0; j < num_frags_y / (2 * num_warps_x); ++j) {\n uint32_t fyi = warp_idx_x + j * num_warps_x;\n k_smem->ldmatrix_m8n8x4(k_smem_offset_r_first_half, k_frag_local[0]);\n uint32_t k_smem_offset_r_last_half =\n k_smem->template advance_offset_by_column<num_frags_y>(k_smem_offset_r_first_half, 0);\n k_smem->ldmatrix_m8n8x4(k_smem_offset_r_last_half, k_frag_local[1]);\n k_frag_apply_llama_rope<DTypeKV>((DTypeKV*)k_frag_local[0], (DTypeKV*)k_frag_local[1],\n rope_freq[fyi], kv_idx);\n k_smem->stmatrix_m8n8x4(k_smem_offset_r_last_half, k_frag_local[1]);\n k_smem->stmatrix_m8n8x4(k_smem_offset_r_first_half, k_frag_local[0]);\n k_smem_offset_r_first_half = k_smem->template advance_offset_by_column<2 * num_warps_x>(\n k_smem_offset_r_first_half, fyi);\n }\n *k_smem_offset_r += 16 * channel_size_128b_kv;\n kv_idx += 16;\n }\n *k_smem_offset_r =\n (*k_smem_offset_r ^ (0x2 * warp_idx_x)) - num_frags_z * 16 * channel_size_128b_kv;\n }\n}\n\ntemplate <LogitsPostHook logits_post_hook, uint32_t num_frags_x, uint32_t num_frags_y,\n uint32_t num_frags_z, SwizzleMode swizzle_mode_q, SwizzleMode swizzle_mode_kv,\n typename DTypeQ, typename DTypeKV, typename DTypeQKAccum>\n__device__ __forceinline__ void compute_qk(\n smem_t<swizzle_mode_q>* q_smem, uint32_t* q_smem_offset_r, smem_t<swizzle_mode_kv>* k_smem,\n uint32_t* k_smem_offset_r, DTypeQKAccum (*s_frag)[num_frags_z][8], const float soft_cap) {\n constexpr uint32_t head_dim = num_frags_y * 16;\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<DTypeKV>();\n uint32_t a_frag[num_frags_x][4], b_frag[4];\n // compute q*k^T\n#pragma unroll\n for (uint32_t fy = 0; fy < num_frags_y; ++fy) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n q_smem->ldmatrix_m8n8x4(*q_smem_offset_r, a_frag[fx]);\n *q_smem_offset_r =\n q_smem->template advance_offset_by_row<16, channel_size_128b_q>(*q_smem_offset_r);\n }\n\n *q_smem_offset_r = q_smem->template advance_offset_by_column<2>(*q_smem_offset_r, fy) -\n num_frags_x * 16 * channel_size_128b_q;\n\n#pragma unroll\n for (uint32_t fz = 0; fz < num_frags_z; ++fz) {\n if constexpr (sizeof(DTypeKV) == 1) {\n uint32_t b_frag_f8[2];\n if (fy % 2 == 0) {\n k_smem->ldmatrix_m8n8x4_left_half(*k_smem_offset_r, b_frag_f8);\n } else {\n k_smem->ldmatrix_m8n8x4_right_half(*k_smem_offset_r, b_frag_f8);\n }\n b_frag_f8[0] = frag_layout_swizzle_16b_to_8b(b_frag_f8[0]);\n b_frag_f8[1] = frag_layout_swizzle_16b_to_8b(b_frag_f8[1]);\n vec_cast<DTypeQ, DTypeKV>::cast<8>((DTypeQ*)b_frag, (DTypeKV*)b_frag_f8);\n } else {\n k_smem->ldmatrix_m8n8x4(*k_smem_offset_r, b_frag);\n }\n *k_smem_offset_r =\n k_smem->template advance_offset_by_row<16, channel_size_128b_kv>(*k_smem_offset_r);\n\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n if constexpr (std::is_same<DTypeQKAccum, float>::value) {\n if (fy == 0) {\n mma::mma_sync_m16n16k16_row_col_f16f16f32<DTypeQ, MMAMode::kInit>(s_frag[fx][fz],\n a_frag[fx], b_frag);\n } else {\n mma::mma_sync_m16n16k16_row_col_f16f16f32<DTypeQ>(s_frag[fx][fz], a_frag[fx], b_frag);\n }\n } else if (std::is_same<DTypeQKAccum, half>::value) {\n if (fy == 0) {\n mma::mma_sync_m16n16k16_row_col_f16f16f16<MMAMode::kInit>((uint32_t*)s_frag[fx][fz],\n a_frag[fx], b_frag);\n } else {\n mma::mma_sync_m16n16k16_row_col_f16f16f16((uint32_t*)s_frag[fx][fz], a_frag[fx],\n b_frag);\n }\n }\n }\n }\n if constexpr (sizeof(DTypeKV) == 1) {\n if (fy % 2 == 1) {\n *k_smem_offset_r = k_smem->template advance_offset_by_column<2>(*k_smem_offset_r, fy / 2);\n }\n *k_smem_offset_r -= num_frags_z * 16 * channel_size_128b_kv;\n } else {\n *k_smem_offset_r = k_smem->template advance_offset_by_column<2>(*k_smem_offset_r, fy) -\n num_frags_z * 16 * channel_size_128b_kv;\n }\n }\n *q_smem_offset_r -= num_frags_y * 2;\n *k_smem_offset_r -= num_frags_y * sizeof(DTypeKV);\n\n if constexpr (std::is_same<DTypeQKAccum, float>::value) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t fz = 0; fz < num_frags_z; ++fz) {\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n s_frag[fx][fz][reg_id] =\n apply_logits_post_hook<logits_post_hook>(s_frag[fx][fz][reg_id], soft_cap);\n }\n }\n }\n } else {\n static_assert(std::is_same<DTypeQKAccum, half>::value);\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t fz = 0; fz < num_frags_z; ++fz) {\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 4; ++reg_id) {\n *(half2*)(&s_frag[fx][fz][reg_id * 2]) = apply_logits_post_hook<logits_post_hook>(\n *(half2*)(&s_frag[fx][fz][reg_id * 2]), soft_cap);\n }\n }\n }\n }\n}\n\ntemplate <uint32_t num_frags_x, uint32_t num_frags_z, typename T>\n__device__ __forceinline__ void apply_alibi_bias(const uint32_t qo_packed_idx_base,\n const uint32_t kv_idx_base, const int32_t q_offset,\n const uint_fastdiv group_size,\n float (*alibi_slope)[2],\n T (*s_frag)[num_frags_z][8]) {\n const int32_t lane_idx = threadIdx.x;\n#pragma unroll\n for (int32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (int32_t fz = 0; fz < num_frags_z; ++fz) {\n#pragma unroll\n for (int32_t reg_id = 0; reg_id < 8; ++reg_id) {\n const int32_t q_idx =\n (qo_packed_idx_base + fx * 16 + lane_idx / 4 + 8 * ((reg_id % 4) / 2)) /\n group_size,\n kv_idx = kv_idx_base + fz * 16 + 2 * (lane_idx % 4) + 8 * (reg_id / 4) +\n reg_id % 2;\n s_frag[fx][fz][reg_id] +=\n T(alibi_slope[fx][(reg_id % 4) / 2]) * T(kv_idx - q_idx - q_offset);\n }\n }\n }\n}\n\ntemplate <MaskMode mask_mode, uint32_t num_frags_x, uint32_t num_frags_y, uint32_t num_frags_z,\n typename DTypeQKAccum>\n__device__ __forceinline__ void mask_s(const uint32_t qo_packed_idx_base,\n const uint32_t kv_idx_base, const uint32_t qo_len,\n const uint32_t kv_len, const uint32_t window_left,\n const uint32_t chunk_end, const uint_fastdiv group_size,\n uint8_t* custom_mask,\n DTypeQKAccum (*s_frag)[num_frags_z][8]) {\n const uint32_t lane_idx = threadIdx.x;\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t fz = 0; fz < num_frags_z; ++fz) {\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n const uint32_t q_idx =\n (qo_packed_idx_base + fx * 16 + lane_idx / 4 + 8 * ((reg_id % 4) / 2)) /\n group_size,\n kv_idx = kv_idx_base + fz * 16 + 2 * (lane_idx % 4) + 8 * (reg_id / 4) +\n reg_id % 2;\n const bool out_of_boundary =\n (mask_mode == MaskMode::kCausal\n ? (kv_idx + qo_len > kv_len + q_idx || (kv_idx >= chunk_end) ||\n kv_idx + qo_len + window_left < kv_len + q_idx)\n : kv_idx >= chunk_end || kv_idx + qo_len + window_left < kv_len + q_idx);\n s_frag[fx][fz][reg_id] =\n (out_of_boundary ||\n (mask_mode == MaskMode::kCustom && q_idx < qo_len &&\n !((custom_mask[(q_idx * kv_len + kv_idx) / 8] >> ((q_idx * kv_len + kv_idx) % 8)) &\n 1)))\n ? DTypeQKAccum(-5e4)\n : s_frag[fx][fz][reg_id];\n }\n }\n }\n}\n\ntemplate <uint32_t num_frags_x, uint32_t num_frags_y, uint32_t num_frags_z, typename DTypeQKAccum>\n__device__ __forceinline__ void update_mdo_states(DTypeQKAccum (*s_frag)[num_frags_z][8],\n float (*o_frag)[num_frags_y][8],\n DTypeQKAccum (*m)[2], float (*d)[2]) {\n if constexpr (std::is_same<DTypeQKAccum, float>::value) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n float m_prev = m[fx][j];\n#pragma unroll\n for (uint32_t fz = 0; fz < num_frags_z; ++fz) {\n float m_local = max(max(s_frag[fx][fz][j * 2 + 0], s_frag[fx][fz][j * 2 + 1]),\n max(s_frag[fx][fz][j * 2 + 4], s_frag[fx][fz][j * 2 + 5]));\n m[fx][j] = max(m[fx][j], m_local);\n }\n m[fx][j] = max(m[fx][j], math::shfl_xor_sync(m[fx][j], 0x2));\n m[fx][j] = max(m[fx][j], math::shfl_xor_sync(m[fx][j], 0x1));\n\n float o_scale = math::ptx_exp2(m_prev - m[fx][j]);\n d[fx][j] *= o_scale;\n#pragma unroll\n for (uint32_t fy = 0; fy < num_frags_y; ++fy) {\n o_frag[fx][fy][j * 2 + 0] *= o_scale;\n o_frag[fx][fy][j * 2 + 1] *= o_scale;\n o_frag[fx][fy][j * 2 + 4] *= o_scale;\n o_frag[fx][fy][j * 2 + 5] *= o_scale;\n }\n#pragma unroll\n for (uint32_t fz = 0; fz < num_frags_z; ++fz) {\n s_frag[fx][fz][j * 2 + 0] = math::ptx_exp2(s_frag[fx][fz][j * 2 + 0] - m[fx][j]);\n s_frag[fx][fz][j * 2 + 1] = math::ptx_exp2(s_frag[fx][fz][j * 2 + 1] - m[fx][j]);\n s_frag[fx][fz][j * 2 + 4] = math::ptx_exp2(s_frag[fx][fz][j * 2 + 4] - m[fx][j]);\n s_frag[fx][fz][j * 2 + 5] = math::ptx_exp2(s_frag[fx][fz][j * 2 + 5] - m[fx][j]);\n }\n }\n }\n } else if constexpr (std::is_same<DTypeQKAccum, half>::value) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n half m_prev[2];\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n m_prev[j] = m[fx][j];\n#pragma unroll\n for (uint32_t fz = 0; fz < num_frags_z; ++fz) {\n half2 m_local =\n __hmax2(*(half2*)&s_frag[fx][fz][j * 2], *(half2*)&s_frag[fx][fz][j * 2 + 4]);\n m[fx][j] = __hmax(m[fx][j], __hmax(m_local.x, m_local.y));\n }\n }\n *(half2*)&m[fx] = __hmax2(*(half2*)&m[fx], math::shfl_xor_sync(*(half2*)&m[fx], 0x2));\n *(half2*)&m[fx] = __hmax2(*(half2*)&m[fx], math::shfl_xor_sync(*(half2*)&m[fx], 0x1));\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n float o_scale = math::ptx_exp2(float(m_prev[j] - m[fx][j]));\n d[fx][j] *= o_scale;\n#pragma unroll\n for (uint32_t fy = 0; fy < num_frags_y; ++fy) {\n o_frag[fx][fy][j * 2 + 0] *= o_scale;\n o_frag[fx][fy][j * 2 + 1] *= o_scale;\n o_frag[fx][fy][j * 2 + 4] *= o_scale;\n o_frag[fx][fy][j * 2 + 5] *= o_scale;\n }\n half2 m2 = make_half2(m[fx][j], m[fx][j]);\n#pragma unroll\n for (uint32_t fz = 0; fz < num_frags_z; ++fz) {\n *(half2*)&s_frag[fx][fz][j * 2] = math::ptx_exp2(*(half2*)&s_frag[fx][fz][j * 2] - m2);\n *(half2*)&s_frag[fx][fz][j * 2 + 4] =\n math::ptx_exp2(*(half2*)&s_frag[fx][fz][j * 2 + 4] - m2);\n }\n }\n }\n }\n}\n\ntemplate <uint32_t num_frags_x, uint32_t num_frags_y, uint32_t num_frags_z,\n SwizzleMode swizzle_mode, typename DTypeQ, typename DTypeKV, typename DTypeQKAccum>\n__device__ __forceinline__ void compute_sfm_v(smem_t<swizzle_mode>* v_smem,\n uint32_t* v_smem_offset_r,\n DTypeQKAccum (*s_frag)[num_frags_z][8],\n float (*o_frag)[num_frags_y][8], float (*d)[2]) {\n constexpr uint32_t head_dim = num_frags_y * 16;\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<DTypeKV>();\n\n DTypeQ s_frag_f16[num_frags_x][num_frags_z][8];\n if constexpr (std::is_same<DTypeQKAccum, float>::value) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t fz = 0; fz < num_frags_z; ++fz) {\n vec_cast<DTypeQ, float>::cast<8>(s_frag_f16[fx][fz], s_frag[fx][fz]);\n }\n }\n }\n\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t fz = 0; fz < num_frags_z; ++fz) {\n if constexpr (std::is_same<DTypeQKAccum, float>::value) {\n mma::rowsum_f16f16f32(d[fx], s_frag_f16[fx][fz]);\n } else {\n mma::rowsum_f16f16f32(d[fx], s_frag[fx][fz]);\n }\n }\n }\n\n#pragma unroll\n for (uint32_t fz = 0; fz < num_frags_z; ++fz) {\n#pragma unroll\n for (uint32_t fy = 0; fy < num_frags_y; ++fy) {\n uint32_t b_frag[4];\n if constexpr (sizeof(DTypeKV) == 1) {\n uint32_t b_frag_f8[2];\n if (fy % 2 == 0) {\n v_smem->ldmatrix_m8n8x4_trans_left_half(*v_smem_offset_r, b_frag_f8);\n } else {\n v_smem->ldmatrix_m8n8x4_trans_right_half(*v_smem_offset_r, b_frag_f8);\n }\n b_frag_f8[0] = frag_layout_swizzle_16b_to_8b_trans(b_frag_f8[0]);\n b_frag_f8[1] = frag_layout_swizzle_16b_to_8b_trans(b_frag_f8[1]);\n vec_cast<DTypeQ, DTypeKV>::cast<8>((DTypeQ*)b_frag, (DTypeKV*)b_frag_f8);\n swap(b_frag[1], b_frag[2]);\n } else {\n v_smem->ldmatrix_m8n8x4_trans(*v_smem_offset_r, b_frag);\n }\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n if constexpr (std::is_same<DTypeQKAccum, float>::value) {\n mma::mma_sync_m16n16k16_row_col_f16f16f32<DTypeQ>(\n o_frag[fx][fy], (uint32_t*)(s_frag_f16[fx][fz]), b_frag);\n } else {\n mma::mma_sync_m16n16k16_row_col_f16f16f32<DTypeQ>(o_frag[fx][fy],\n (uint32_t*)s_frag[fx][fz], b_frag);\n }\n }\n if constexpr (sizeof(DTypeKV) == 1) {\n if (fy % 2 == 1) {\n *v_smem_offset_r = v_smem->template advance_offset_by_column<2>(*v_smem_offset_r, fy / 2);\n }\n } else {\n *v_smem_offset_r = v_smem->template advance_offset_by_column<2>(*v_smem_offset_r, fy);\n }\n }\n *v_smem_offset_r =\n v_smem->template advance_offset_by_row<16, channel_size_128b_kv>(*v_smem_offset_r) -\n sizeof(DTypeKV) * num_frags_y;\n }\n *v_smem_offset_r -= 16 * num_frags_z * channel_size_128b_kv;\n}\n\ntemplate <uint32_t num_frags_x, uint32_t num_frags_y, typename DTypeQKAccum>\n__device__ __forceinline__ void normalize_d(float (*o_frag)[num_frags_y][8], DTypeQKAccum (*m)[2],\n float (*d)[2]) {\n float d_rcp[num_frags_x][2];\n // compute reciprocal of d\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n d_rcp[fx][j] = (m[fx][j] != DTypeQKAccum(-5e4)) ? math::ptx_rcp(d[fx][j]) : 0.f;\n }\n }\n\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t fy = 0; fy < num_frags_y; ++fy) {\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n o_frag[fx][fy][reg_id] = o_frag[fx][fy][reg_id] * d_rcp[fx][(reg_id % 4) / 2];\n }\n }\n }\n}\n\n/*!\n * \\brief Synchronize the states of the MDO kernel across the threadblock along threadIdx.z.\n */\ntemplate <uint32_t num_warps_x, uint32_t num_warps_z, uint32_t num_frags_x, uint32_t num_frags_y,\n typename DTypeQKAccum>\n__device__ __forceinline__ void threadblock_sync_mdo_states(float (*o_frag)[num_frags_y][8],\n float* smem_workspace,\n DTypeQKAccum (*m)[2], float (*d)[2],\n const uint32_t warp_idx,\n const uint32_t lane_idx) {\n // only necessary when blockDim.z > 1\n if constexpr (num_warps_z > 1) {\n float2* smem_md = (float2*)(smem_workspace + num_frags_x * num_frags_y * num_warps_x *\n num_warps_z * warp_size * 8);\n // o: [num_warps, num_frags_x, num_frags_y, warp_size(32), 8]\n // md: [num_warps, num_frags_x, 2, warp_size(32), 2 (m/d)]\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t fy = 0; fy < num_frags_y; ++fy) {\n vec_t<float, 8>::memcpy(\n smem_workspace +\n (((warp_idx * num_frags_x + fx) * num_frags_y + fy) * warp_size + lane_idx) * 8,\n o_frag[fx][fy]);\n }\n }\n\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n smem_md[((warp_idx * num_frags_x + fx) * 2 + j) * warp_size + lane_idx] =\n make_float2(float(m[fx][j]), d[fx][j]);\n }\n }\n\n // synchronize m,d first\n __syncthreads();\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n float o_scale[2][num_warps_z];\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n float m_new = -5e4, d_new = 1.f;\n#pragma unroll\n for (uint32_t i = 0; i < num_warps_z; ++i) {\n float2 md = smem_md[(((i * num_warps_x + get_warp_idx_x<num_warps_x, num_warps_z>()) *\n num_frags_x +\n fx) *\n 2 +\n j) *\n warp_size +\n lane_idx];\n float m_prev = m_new, d_prev = d_new;\n m_new = max(m_new, md.x);\n d_new = d_prev * math::ptx_exp2(m_prev - m_new) + md.y * math::ptx_exp2(md.x - m_new);\n }\n\n#pragma unroll\n for (uint32_t i = 0; i < num_warps_z; ++i) {\n float2 md = smem_md[(((i * num_warps_x + get_warp_idx_x<num_warps_x, num_warps_z>()) *\n num_frags_x +\n fx) *\n 2 +\n j) *\n warp_size +\n lane_idx];\n float mi = md.x;\n o_scale[j][i] = math::ptx_exp2(float(mi - m_new));\n }\n m[fx][j] = DTypeQKAccum(m_new);\n d[fx][j] = d_new;\n }\n\n#pragma unroll\n for (uint32_t fy = 0; fy < num_frags_y; ++fy) {\n vec_t<float, 8> o_new;\n o_new.fill(0.f);\n#pragma unroll\n for (uint32_t i = 0; i < num_warps_z; ++i) {\n vec_t<float, 8> oi;\n oi.load(smem_workspace +\n ((((i * num_warps_x + get_warp_idx_x<num_warps_x, num_warps_z>()) * num_frags_x +\n fx) *\n num_frags_y +\n fy) *\n warp_size +\n lane_idx) *\n 8);\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n o_new[reg_id] += oi[reg_id] * o_scale[(reg_id % 4) / 2][i];\n }\n }\n o_new.store(o_frag[fx][fy]);\n }\n }\n }\n}\n\ntemplate <uint32_t num_warps_x, uint32_t num_warps_z, uint32_t num_frags_x, uint32_t num_frags_y,\n SwizzleMode swizzle_mode, typename DTypeOut>\n__device__ __forceinline__ void write_o_reg_gmem(\n float (*o_frag)[num_frags_y][8], smem_t<swizzle_mode>* o_smem, DTypeOut* o_ptr_base,\n const uint32_t o_packed_idx_base, const uint32_t qo_upper_bound, const uint32_t o_stride_n,\n const uint32_t o_stride_h, const uint_fastdiv group_size) {\n constexpr uint32_t head_dim = num_frags_y * 16;\n constexpr uint32_t channel_size_128b_out = head_dim / num_elems_per_128b<DTypeOut>();\n const uint32_t warp_idx_x = get_warp_idx_x<num_warps_x, num_warps_z>();\n const uint32_t lane_idx = threadIdx.x;\n\n if (get_warp_idx_z<num_warps_x, num_warps_z>() == 0) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t fy = 0; fy < num_frags_y; ++fy) {\n uint32_t o_frag_f16[4];\n vec_cast<DTypeOut, float>::cast<8>((DTypeOut*)o_frag_f16, o_frag[fx][fy]);\n#ifdef FLASHINFER_STMATRIX_M8N8X4_ENABLED\n uint32_t o_smem_offset_w = o_smem->get_permuted_offset<channel_size_128b_out>(\n (warp_idx_x * num_frags_x + fx) * 16 + lane_idx % 16, fy * 2 + lane_idx / 16);\n o_smem->stmatrix_m8n8x4(o_smem_offset_w, o_frag_f16);\n#else\n uint32_t o_smem_offset_w = o_smem->get_permuted_offset<channel_size_128b_out>(\n (warp_idx_x * num_frags_x + fx) * 16 + lane_idx / 4, fy * 2);\n ((uint32_t*)(o_smem->base + o_smem_offset_w))[lane_idx % 4] = o_frag_f16[0];\n ((uint32_t*)(o_smem->base + o_smem_offset_w + 8 * channel_size_128b_out))[lane_idx % 4] =\n o_frag_f16[1];\n ((uint32_t*)(o_smem->base + (o_smem_offset_w ^ 0x1)))[lane_idx % 4] = o_frag_f16[2];\n ((uint32_t*)(o_smem->base + (o_smem_offset_w ^ 0x1) +\n 8 * channel_size_128b_out))[lane_idx % 4] = o_frag_f16[3];\n#endif\n }\n }\n\n uint32_t o_smem_offset_w = o_smem->get_permuted_offset<channel_size_128b_out>(\n warp_idx_x * num_frags_x * 16 + lane_idx / 8, lane_idx % 8);\n\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t j = 0; j < 4; ++j) {\n uint32_t q, r;\n group_size.divmod(o_packed_idx_base + lane_idx / 8 + fx * 16 + j * 4, q, r);\n const uint32_t o_idx = q;\n DTypeOut* o_ptr = o_ptr_base + q * o_stride_n + r * o_stride_h;\n#pragma unroll\n for (uint32_t fyo = 0; fyo < num_frags_y / 4; ++fyo) {\n if (o_idx < qo_upper_bound) {\n o_smem->store_128b(o_smem_offset_w, o_ptr);\n }\n o_ptr += 8 * num_elems_per_128b<DTypeOut>();\n o_smem_offset_w = o_smem->template advance_offset_by_column<8>(o_smem_offset_w, fyo);\n }\n o_smem_offset_w =\n o_smem->template advance_offset_by_row<4, channel_size_128b_out>(o_smem_offset_w) -\n 2 * num_frags_y;\n }\n }\n }\n}\n\n} // namespace\n\n/*!\n * \\brief FlashAttention prefill CUDA kernel for a single request.\n * \\tparam partition_kv Whether to split kv_len into chunks.\n * \\tparam mask_mode The mask mode used in the attention operation.\n * \\tparam pos_encoding_mode The positional encoding mode.\n * \\tparam num_frags_x The number of fragments in x dimension.\n * \\tparam num_frags_y The number of fragments in y dimension.\n * \\tparam num_frags_z The number of fragments in z dimension.\n * \\tparam num_warps The number of warps in the threadblock.\n * \\tparam DTypeQ The data type of the query tensor.\n * \\tparam DTypeKV The data type of the key/value tensor.\n * \\tparam DTypeOut The data type of the output tensor.\n * \\param q The query tensor.\n * \\param k The key tensor.\n * \\param v The value tensor.\n * \\param o The output tensor.\n * \\param tmp The temporary buffer (used when partition_kv is true).\n * \\param lse The logsumexp value.\n * \\param qkv_info The tensor info of the input tensor.\n * \\param sm_scale The scale factor applied to the softmax score.\n * \\param log2_rope_rcp_scale log2(1/(rope_scale)), where rope_scale is the scaling\n * factor used in RoPE interpolation.\n * \\param log2_rope_rcp_theta log2(1/(rope_theta)), where rope_theta is the theta\n * used in RoPE.\n */\ntemplate <LogitsPostHook logits_post_hook, MaskMode mask_mode, PosEncodingMode pos_encoding_mode,\n uint32_t num_frags_x, uint32_t num_frags_y, uint32_t num_frags_z, uint32_t num_warps_x,\n uint32_t num_warps_z, typename DTypeQ, typename DTypeKV, typename DTypeQKAccum,\n typename DTypeOut>\n__global__\n__launch_bounds__(num_warps_x* num_warps_z* warp_size) void SinglePrefillWithKVCacheKernel(\n DTypeQ* __restrict__ q, DTypeKV* __restrict__ k, DTypeKV* __restrict__ v,\n uint8_t* __restrict__ custom_mask, DTypeOut* __restrict__ o, float* __restrict__ lse,\n const uint32_t qo_len, const uint32_t kv_len, const bool partition_kv,\n const uint_fastdiv group_size, const uint32_t q_stride_n, const uint32_t q_stride_h,\n const uint32_t kv_stride_n, const uint32_t kv_stride_h, const int32_t maybe_window_left,\n const float logits_soft_cap, float sm_scale, const float log2_rope_rcp_scale,\n const float log2_rope_rcp_theta) {\n static_assert(sizeof(DTypeQ) == 2);\n static_assert(sizeof(DTypeOut) == 2);\n sm_scale *=\n (logits_post_hook == LogitsPostHook::kNone ? math::log2e : math::ptx_rcp(logits_soft_cap));\n const uint32_t lane_idx = threadIdx.x, warp_idx = get_warp_idx<num_warps_x, num_warps_z>();\n const uint32_t bx = blockIdx.x, chunk_idx = blockIdx.y, kv_head_idx = blockIdx.z;\n const uint32_t num_kv_heads = gridDim.z, num_qo_heads = num_kv_heads * group_size;\n constexpr uint32_t num_rows_per_cta = num_frags_x * num_warps_x * 16;\n const tensor_info_t qkv_info(qo_len, kv_len, num_qo_heads, num_kv_heads, q_stride_n, q_stride_h,\n kv_stride_n, kv_stride_h, /*head_dim=*/num_frags_y * 16);\n float alibi_slopes[num_frags_x][2];\n\n const uint32_t num_chunks = gridDim.y;\n const uint32_t max_chunk_size = partition_kv ? ceil_div(kv_len, num_chunks) : kv_len;\n const uint32_t chunk_start = partition_kv ? chunk_idx * max_chunk_size : 0;\n const uint32_t chunk_end = partition_kv ? min((chunk_idx + 1) * max_chunk_size, kv_len) : kv_len;\n const uint32_t chunk_size = chunk_end - chunk_start;\n\n auto block = cg::this_thread_block();\n const uint32_t window_left = (maybe_window_left >= 0) ? maybe_window_left : kv_len;\n\n constexpr uint32_t head_dim = num_frags_y * 16;\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<DTypeKV>();\n constexpr uint32_t channel_size_128b_out = head_dim / num_elems_per_128b<DTypeOut>();\n\n extern __shared__ uint8_t smem[];\n\n DTypeQKAccum s_frag[num_frags_x][num_frags_z][8];\n float o_frag[num_frags_x][num_frags_y][8];\n DTypeQKAccum m[num_frags_x][2];\n float d[num_frags_x][2];\n float rope_freq[num_frags_y / 2][4];\n if constexpr (pos_encoding_mode == PosEncodingMode::kRoPELlama) {\n init_rope_freq<num_frags_y>(rope_freq, log2_rope_rcp_scale, log2_rope_rcp_theta);\n }\n init_states<num_frags_x, num_frags_y>(o_frag, m, d);\n\n // cooperative fetch q fragment from gmem to reg\n const uint32_t qo_packed_idx_base =\n (bx * num_warps_x + get_warp_idx_x<num_warps_x, num_warps_z>()) * num_frags_x * 16;\n constexpr SwizzleMode swizzle_mode_q = SwizzleMode::k128B;\n smem_t<swizzle_mode_q> qo_smem(smem);\n DTypeQ* q_ptr_base =\n q + qkv_info.get_q_elem_offset(0, kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeQ>());\n DTypeOut* o_ptr_base =\n partition_kv\n ? o + chunk_idx * num_qo_heads * head_dim +\n qkv_info.get_o_elem_offset(0, kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeOut>())\n : o + qkv_info.get_o_elem_offset(0, kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeOut>());\n uint32_t q_smem_offset_r = qo_smem.get_permuted_offset<channel_size_128b_q>(\n get_warp_idx_x<num_warps_x, num_warps_z>() * num_frags_x * 16 + lane_idx % 16, lane_idx / 16);\n\n load_q_global_smem<num_warps_x, num_warps_z, num_frags_x, num_frags_y>(\n qo_packed_idx_base, qo_len, q_ptr_base, q_stride_n, q_stride_h, group_size, &qo_smem);\n\n cp_async::commit_group();\n cp_async::wait_group<0>();\n block.sync();\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kRoPELlama) {\n q_smem_inplace_apply_rotary_multiply_sm_scale<num_warps_x, num_warps_z, num_frags_x,\n num_frags_y, swizzle_mode_q, DTypeQ>(\n qo_packed_idx_base, qo_len, kv_len, group_size, &qo_smem, &q_smem_offset_r, rope_freq,\n sm_scale);\n } else {\n q_smem_inplace_multiply_sm_scale<num_warps_x, num_warps_z, num_frags_x, num_frags_y,\n swizzle_mode_q, DTypeQ>(&qo_smem, sm_scale);\n }\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kALiBi) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n const uint32_t qo_head_idx =\n kv_head_idx * group_size +\n (qo_packed_idx_base + lane_idx / 4 + j * 8 + fx * 16) % group_size;\n alibi_slopes[fx][j] = get_alibi_slope(qo_head_idx, num_qo_heads) * math::log2e;\n }\n }\n }\n\n constexpr SwizzleMode swizzle_mode_kv =\n (sizeof(DTypeKV) == 1 && head_dim == 64) ? SwizzleMode::k64B : SwizzleMode::k128B;\n constexpr uint32_t kv_frag_rows = swizzle_mode_kv == SwizzleMode::k128B ? 4 : 8;\n constexpr uint32_t kv_frag_cols = swizzle_mode_kv == SwizzleMode::k128B ? 8 : 4;\n smem_t<swizzle_mode_kv> k_smem(smem +\n (num_warps_x * num_frags_x * sizeof(DTypeQ)) * 16 * head_dim),\n v_smem(smem + (num_warps_x * num_frags_x * sizeof(DTypeQ) +\n num_warps_z * num_frags_z * sizeof(DTypeKV)) *\n 16 * head_dim);\n\n const uint32_t num_iterations = ceil_div(\n mask_mode == MaskMode::kCausal\n ? min(chunk_size,\n sub_if_greater_or_zero(kv_len - qo_len + ((bx + 1) * num_rows_per_cta) / group_size,\n chunk_start))\n : chunk_size,\n 16 * num_warps_z * num_frags_z);\n\n const uint32_t window_iteration =\n ceil_div(sub_if_greater_or_zero(kv_len + (bx + 1) * num_rows_per_cta,\n qo_len + window_left + chunk_start),\n (16 * num_warps_z * num_frags_z));\n\n const uint32_t mask_iteration =\n (mask_mode == MaskMode::kCausal\n ? min(chunk_size,\n sub_if_greater_or_zero(kv_len + (bx * num_rows_per_cta) / group_size - qo_len,\n chunk_start))\n : chunk_size) /\n (16 * num_warps_z * num_frags_z);\n\n DTypeKV* k_ptr = k + qkv_info.get_kv_elem_offset(\n chunk_start + warp_idx * kv_frag_rows + lane_idx / kv_frag_cols,\n kv_head_idx, (lane_idx % kv_frag_cols) * num_elems_per_128b<DTypeKV>());\n DTypeKV* v_ptr = v + qkv_info.get_kv_elem_offset(\n chunk_start + warp_idx * kv_frag_rows + lane_idx / kv_frag_cols,\n kv_head_idx, (lane_idx % kv_frag_cols) * num_elems_per_128b<DTypeKV>());\n uint32_t k_smem_offset_r = k_smem.get_permuted_offset<channel_size_128b_kv>(\n get_warp_idx_z<num_warps_x, num_warps_z>() * num_frags_z * 16 + 8 * (lane_idx / 16) +\n lane_idx % 8,\n (lane_idx % 16) / 8),\n v_smem_offset_r = v_smem.get_permuted_offset<channel_size_128b_kv>(\n get_warp_idx_z<num_warps_x, num_warps_z>() * num_frags_z * 16 + lane_idx % 16,\n lane_idx / 16),\n kv_smem_offset_w = k_smem.get_permuted_offset<channel_size_128b_kv>(\n warp_idx * kv_frag_rows + lane_idx / kv_frag_cols, lane_idx % kv_frag_cols);\n produce_kv<SharedMemFillMode::kNoFill, num_warps_x, num_warps_z, num_frags_y, num_frags_z>(\n k_smem, &kv_smem_offset_w, &k_ptr, kv_stride_n, 0, chunk_size);\n cp_async::commit_group();\n produce_kv<SharedMemFillMode::kFillZero, num_warps_x, num_warps_z, num_frags_y, num_frags_z>(\n v_smem, &kv_smem_offset_w, &v_ptr, kv_stride_n, 0, chunk_size);\n cp_async::commit_group();\n\n#pragma unroll 1\n for (uint32_t iter = 0; iter < num_iterations; ++iter) {\n cp_async::wait_group<1>();\n block.sync();\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kRoPELlama) {\n k_smem_inplace_apply_rotary<num_warps_x, num_warps_z, num_frags_y, num_frags_z,\n swizzle_mode_kv, DTypeKV>(\n chunk_start + iter * 16 * num_warps_z * num_frags_z, &k_smem, &k_smem_offset_r,\n rope_freq);\n block.sync();\n }\n\n // compute attention score\n compute_qk<logits_post_hook, num_frags_x, num_frags_y, num_frags_z, swizzle_mode_q,\n swizzle_mode_kv, DTypeQ, DTypeKV>(&qo_smem, &q_smem_offset_r, &k_smem,\n &k_smem_offset_r, s_frag, logits_soft_cap);\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kALiBi) {\n apply_alibi_bias<num_frags_x, num_frags_z>(\n qo_packed_idx_base,\n chunk_start +\n (iter * num_warps_z + get_warp_idx_z<num_warps_x, num_warps_z>()) * num_frags_z * 16,\n int(kv_len) - int(qo_len), group_size, alibi_slopes, s_frag);\n }\n // apply mask\n if constexpr (mask_mode == MaskMode::kCustom) {\n mask_s<mask_mode, num_frags_x, num_frags_y, num_frags_z>(\n qo_packed_idx_base,\n chunk_start +\n (iter * num_warps_z + get_warp_idx_z<num_warps_x, num_warps_z>()) * num_frags_z * 16,\n qo_len, kv_len, window_left, chunk_end, group_size, custom_mask, s_frag);\n } else {\n if (iter >= mask_iteration || iter < window_iteration) {\n mask_s<mask_mode, num_frags_x, num_frags_y, num_frags_z>(\n qo_packed_idx_base,\n chunk_start + (iter * num_warps_z + get_warp_idx_z<num_warps_x, num_warps_z>()) *\n num_frags_z * 16,\n qo_len, kv_len, window_left, chunk_end, group_size, nullptr, s_frag);\n }\n }\n\n // compute m,d states in online softmax\n update_mdo_states<num_frags_x, num_frags_y, num_frags_z>(s_frag, o_frag, m, d);\n\n block.sync();\n produce_kv<SharedMemFillMode::kNoFill, num_warps_x, num_warps_z, num_frags_y, num_frags_z>(\n k_smem, &kv_smem_offset_w, &k_ptr, kv_stride_n, (iter + 1) * 16 * num_warps_z * num_frags_z,\n chunk_size);\n cp_async::commit_group();\n cp_async::wait_group<1>();\n block.sync();\n\n // compute sfm*v\n compute_sfm_v<num_frags_x, num_frags_y, num_frags_z, swizzle_mode_kv, DTypeQ, DTypeKV>(\n &v_smem, &v_smem_offset_r, s_frag, o_frag, d);\n\n block.sync();\n produce_kv<SharedMemFillMode::kFillZero, num_warps_x, num_warps_z, num_frags_y, num_frags_z>(\n v_smem, &kv_smem_offset_w, &v_ptr, kv_stride_n, (iter + 1) * 16 * num_warps_z * num_frags_z,\n chunk_size);\n cp_async::commit_group();\n }\n cp_async::wait_group<0>();\n block.sync();\n\n // threadblock synchronization\n threadblock_sync_mdo_states<num_warps_x, num_warps_z, num_frags_x, num_frags_y, DTypeQKAccum>(\n o_frag, (float*)smem, m, d, warp_idx, lane_idx);\n\n // normalize d\n normalize_d<num_frags_x, num_frags_y>(o_frag, m, d);\n\n // write back\n write_o_reg_gmem<num_warps_x, num_warps_z, num_frags_x, num_frags_y>(\n o_frag, &qo_smem, o_ptr_base, qo_packed_idx_base, qo_len,\n /*o_stride_n=*/partition_kv ? num_qo_heads * head_dim * num_chunks : num_qo_heads * head_dim,\n /*o_stride_h=*/head_dim, group_size);\n\n // write lse\n if (lse != nullptr || partition_kv) {\n if (get_warp_idx_z<num_warps_x, num_warps_z>() == 0) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n uint32_t q, r;\n group_size.divmod(qo_packed_idx_base + lane_idx / 4 + j * 8 + fx * 16, q, r);\n const uint32_t qo_head_idx = kv_head_idx * group_size + r;\n const uint32_t qo_idx = q;\n if (qo_idx < qo_len) {\n if (partition_kv) {\n lse[(qo_idx * num_chunks + chunk_idx) * num_qo_heads + qo_head_idx] =\n math::ptx_log2(d[fx][j]) + float(m[fx][j]);\n } else {\n lse[qo_idx * num_qo_heads + qo_head_idx] = math::ptx_log2(d[fx][j]) + float(m[fx][j]);\n }\n }\n }\n }\n }\n }\n}\n\ntemplate <LogitsPostHook logits_post_hook, MaskMode mask_mode, PosEncodingMode pos_encoding_mode,\n uint32_t num_frags_x, uint32_t num_frags_y, uint32_t num_frags_z, uint32_t num_warps_x,\n uint32_t num_warps_z, typename DTypeQ, typename DTypeKV, typename DTypeQKAccum,\n typename DTypeOut, typename IdType>\n__global__\n__launch_bounds__(num_warps_x* num_warps_z* warp_size) void BatchPrefillWithRaggedKVCacheKernel(\n DTypeQ* __restrict__ q, IdType* __restrict__ request_indices,\n IdType* __restrict__ q_tile_indices, IdType* __restrict__ kv_tile_indices,\n IdType* __restrict__ q_indptr, DTypeKV* __restrict__ k, DTypeKV* __restrict__ v,\n IdType* __restrict__ kv_indptr, uint8_t* __restrict__ custom_mask,\n IdType* __restrict__ qk_indptr, IdType* __restrict__ q_offset,\n IdType* __restrict__ k_rope_pos_offset, IdType* __restrict__ o_indptr, DTypeOut* __restrict__ o,\n float* __restrict__ lse, bool* __restrict__ block_valid_mask,\n IdType* __restrict__ kv_chunk_size_ptr, const bool partition_kv, const uint_fastdiv group_size,\n const uint32_t q_stride_n, const uint32_t q_stride_h, const uint32_t kv_stride_n,\n const uint32_t kv_stride_h, const int32_t maybe_window_left, const float logits_soft_cap,\n float sm_scale, const float log2_rope_rcp_scale, const float log2_rope_rcp_theta) {\n static_assert(sizeof(DTypeQ) == 2);\n static_assert(sizeof(DTypeOut) == 2);\n sm_scale *=\n (logits_post_hook == LogitsPostHook::kNone ? math::log2e : math::ptx_rcp(logits_soft_cap));\n constexpr uint32_t head_dim = num_frags_y * 16;\n const uint32_t kv_chunk_size = *kv_chunk_size_ptr;\n\n auto block = cg::this_thread_block();\n const uint32_t bx = blockIdx.x, lane_idx = threadIdx.x,\n warp_idx = get_warp_idx<num_warps_x, num_warps_z>(), kv_head_idx = blockIdx.z;\n if (block_valid_mask && !block_valid_mask[bx]) {\n return;\n }\n const uint32_t num_kv_heads = gridDim.z, num_qo_heads = group_size * num_kv_heads;\n const uint32_t request_idx = request_indices[bx], qo_tile_idx = q_tile_indices[bx],\n kv_tile_idx = kv_tile_indices[bx];\n constexpr uint32_t num_rows_per_cta = num_frags_x * num_warps_x * 16;\n const uint32_t qo_len = q_indptr[request_idx + 1] - q_indptr[request_idx],\n kv_len = kv_indptr[request_idx + 1] - kv_indptr[request_idx];\n const uint32_t kv_len_safe = kv_len > 0 ? kv_len : 1;\n const uint32_t window_left = (maybe_window_left >= 0) ? maybe_window_left : kv_len;\n const uint32_t max_chunk_size = partition_kv ? kv_chunk_size : kv_len;\n const uint32_t chunk_start = partition_kv ? kv_tile_idx * max_chunk_size : 0;\n const uint32_t chunk_end =\n partition_kv ? min((kv_tile_idx + 1) * max_chunk_size, kv_len) : kv_len;\n const uint32_t chunk_size = chunk_end - chunk_start;\n const tensor_info_t qkv_info(qo_len, kv_len, num_qo_heads, num_kv_heads, q_stride_n, q_stride_h,\n kv_stride_n, kv_stride_h, /*head_dim=*/num_frags_y * 16);\n float alibi_slopes[num_frags_x][2];\n const uint32_t qo_upper_bound =\n min(qo_len, ceil_div((qo_tile_idx + 1) * num_rows_per_cta, group_size));\n\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<DTypeKV>();\n constexpr uint32_t channel_size_128b_out = head_dim / num_elems_per_128b<DTypeOut>();\n\n extern __shared__ uint8_t smem[];\n\n DTypeQKAccum s_frag[num_frags_x][num_frags_z][8];\n float o_frag[num_frags_x][num_frags_y][8];\n DTypeQKAccum m[num_frags_x][2];\n float d[num_frags_x][2];\n float rope_freq[num_frags_y / 2][4];\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kRoPELlama) {\n init_rope_freq<num_frags_y>(rope_freq, log2_rope_rcp_scale, log2_rope_rcp_theta);\n }\n init_states<num_frags_x, num_frags_y>(o_frag, m, d);\n\n const uint32_t qo_packed_idx_base =\n (qo_tile_idx * num_warps_x + get_warp_idx_x<num_warps_x, num_warps_z>()) * num_frags_x * 16;\n constexpr SwizzleMode swizzle_mode_q = SwizzleMode::k128B;\n smem_t<swizzle_mode_q> qo_smem(smem);\n\n DTypeQ* q_ptr_base =\n q + qkv_info.get_q_elem_offset(q_indptr[request_idx], kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeQ>());\n\n DTypeOut* o_ptr_base =\n partition_kv\n ? o + kv_tile_idx * num_qo_heads * head_dim +\n qkv_info.get_o_elem_offset(o_indptr[request_idx], kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeOut>())\n : o + qkv_info.get_o_elem_offset(o_indptr[request_idx], kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeOut>());\n\n uint32_t q_smem_offset_r = qo_smem.get_permuted_offset<channel_size_128b_q>(\n get_warp_idx_x<num_warps_x, num_warps_z>() * num_frags_x * 16 + lane_idx % 16, lane_idx / 16);\n\n load_q_global_smem<num_warps_x, num_warps_z, num_frags_x, num_frags_y>(\n qo_packed_idx_base, qo_upper_bound, q_ptr_base, q_stride_n, q_stride_h, group_size, &qo_smem);\n\n cp_async::commit_group();\n cp_async::wait_group<0>();\n block.sync();\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kRoPELlama) {\n if (!q_offset) {\n q_smem_inplace_apply_rotary_multiply_sm_scale<num_warps_x, num_warps_z, num_frags_x,\n num_frags_y, swizzle_mode_q, DTypeQ>(\n qo_packed_idx_base, qo_len, kv_len, group_size, &qo_smem, &q_smem_offset_r, rope_freq,\n sm_scale);\n } else {\n q_smem_inplace_apply_rotary_with_pos_multiply_sm_scale<num_warps_x, num_warps_z, num_frags_x,\n num_frags_y, swizzle_mode_q, DTypeQ>(\n qo_packed_idx_base, q_offset + q_indptr[request_idx], &qo_smem, group_size,\n &q_smem_offset_r, rope_freq, sm_scale);\n }\n } else {\n q_smem_inplace_multiply_sm_scale<num_warps_x, num_warps_z, num_frags_x, num_frags_y,\n swizzle_mode_q, DTypeQ>(&qo_smem, sm_scale);\n }\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kALiBi) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n const uint32_t qo_head_idx =\n kv_head_idx * group_size +\n (qo_packed_idx_base + lane_idx / 4 + j * 8 + fx * 16) % group_size;\n alibi_slopes[fx][j] = get_alibi_slope(qo_head_idx, num_qo_heads) * math::log2e;\n }\n }\n }\n\n const uint32_t num_iterations =\n ceil_div((mask_mode == MaskMode::kCausal\n ? min(chunk_size,\n sub_if_greater_or_zero(\n kv_len - qo_len + ((qo_tile_idx + 1) * num_rows_per_cta) / group_size,\n chunk_start))\n : chunk_size),\n 16 * num_warps_z * num_frags_z);\n\n const uint32_t window_iteration =\n ceil_div(sub_if_greater_or_zero(kv_len + (bx + 1) * num_rows_per_cta,\n qo_len + window_left + chunk_start),\n (16 * num_warps_z * num_frags_z));\n\n const uint32_t mask_iteration =\n (mask_mode == MaskMode::kCausal\n ? min(chunk_size,\n sub_if_greater_or_zero(\n kv_len + (qo_tile_idx * num_rows_per_cta) / group_size - qo_len, chunk_start))\n : chunk_size) /\n (16 * num_warps_z * num_frags_z);\n\n constexpr SwizzleMode swizzle_mode_kv =\n (sizeof(DTypeKV) == 1 && head_dim == 64) ? SwizzleMode::k64B : SwizzleMode::k128B;\n constexpr uint32_t kv_frag_rows = swizzle_mode_kv == SwizzleMode::k128B ? 4 : 8;\n constexpr uint32_t kv_frag_cols = swizzle_mode_kv == SwizzleMode::k128B ? 8 : 4;\n smem_t<swizzle_mode_kv> k_smem(smem +\n (num_warps_x * num_frags_x * sizeof(DTypeQ)) * 16 * head_dim),\n v_smem(smem + (num_warps_x * num_frags_x * sizeof(DTypeQ) +\n num_warps_z * num_frags_z * sizeof(DTypeKV)) *\n 16 * head_dim);\n\n uint32_t k_smem_offset_r = k_smem.get_permuted_offset<channel_size_128b_kv>(\n get_warp_idx_z<num_warps_x, num_warps_z>() * num_frags_z * 16 + 8 * (lane_idx / 16) +\n lane_idx % 8,\n (lane_idx % 16) / 8),\n v_smem_offset_r = v_smem.get_permuted_offset<channel_size_128b_kv>(\n get_warp_idx_z<num_warps_x, num_warps_z>() * num_frags_z * 16 + lane_idx % 16,\n lane_idx / 16),\n kv_smem_offset_w = k_smem.get_permuted_offset<channel_size_128b_kv>(\n warp_idx * kv_frag_rows + lane_idx / kv_frag_cols, lane_idx % kv_frag_cols);\n\n DTypeKV* k_ptr = k + qkv_info.get_kv_elem_offset(\n kv_indptr[request_idx] + chunk_start + warp_idx * kv_frag_rows +\n lane_idx / kv_frag_cols,\n kv_head_idx, (lane_idx % kv_frag_cols) * num_elems_per_128b<DTypeKV>());\n DTypeKV* v_ptr = v + qkv_info.get_kv_elem_offset(\n kv_indptr[request_idx] + chunk_start + warp_idx * kv_frag_rows +\n lane_idx / kv_frag_cols,\n kv_head_idx, (lane_idx % kv_frag_cols) * num_elems_per_128b<DTypeKV>());\n\n produce_kv<SharedMemFillMode::kNoFill, num_warps_x, num_warps_z, num_frags_y, num_frags_z>(\n k_smem, &kv_smem_offset_w, &k_ptr, kv_stride_n, 0, chunk_size);\n cp_async::commit_group();\n produce_kv<SharedMemFillMode::kFillZero, num_warps_x, num_warps_z, num_frags_y, num_frags_z>(\n v_smem, &kv_smem_offset_w, &v_ptr, kv_stride_n, 0, chunk_size);\n cp_async::commit_group();\n\n#pragma unroll 1\n for (uint32_t iter = 0; iter < num_iterations; ++iter) {\n cp_async::wait_group<1>();\n block.sync();\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kRoPELlama) {\n k_smem_inplace_apply_rotary<num_warps_x, num_warps_z, num_frags_y, num_frags_z,\n swizzle_mode_kv, DTypeKV>(\n (k_rope_pos_offset == nullptr ? 0 : k_rope_pos_offset[request_idx]) + chunk_start +\n iter * 16 * num_warps_z * num_frags_z,\n &k_smem, &k_smem_offset_r, rope_freq);\n block.sync();\n }\n\n // compute attention score\n compute_qk<logits_post_hook, num_frags_x, num_frags_y, num_frags_z, swizzle_mode_q,\n swizzle_mode_kv, DTypeQ, DTypeKV>(&qo_smem, &q_smem_offset_r, &k_smem,\n &k_smem_offset_r, s_frag, logits_soft_cap);\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kALiBi) {\n // TODO(Zihao): handle the case that q_offset is specified\n apply_alibi_bias<num_frags_x, num_frags_z>(\n qo_packed_idx_base,\n chunk_start +\n (iter * num_warps_z + get_warp_idx_z<num_warps_x, num_warps_z>()) * num_frags_z * 16,\n int(kv_len) - int(qo_len), group_size, alibi_slopes, s_frag);\n }\n // apply mask\n if constexpr (mask_mode == MaskMode::kCustom) {\n mask_s<mask_mode, num_frags_x, num_frags_y, num_frags_z>(\n qo_packed_idx_base,\n chunk_start +\n (iter * num_warps_z + get_warp_idx_z<num_warps_x, num_warps_z>()) * num_frags_z * 16,\n qo_len, kv_len, window_left, chunk_end, group_size, custom_mask + qk_indptr[request_idx],\n s_frag);\n } else {\n if (iter >= mask_iteration || iter < window_iteration) {\n mask_s<mask_mode, num_frags_x, num_frags_y, num_frags_z>(\n qo_packed_idx_base,\n chunk_start + (iter * num_warps_z + get_warp_idx_z<num_warps_x, num_warps_z>()) *\n num_frags_z * 16,\n qo_len, kv_len, window_left, chunk_end, group_size, nullptr, s_frag);\n }\n }\n\n // compute m,d states in online softmax\n update_mdo_states<num_frags_x, num_frags_y, num_frags_z>(s_frag, o_frag, m, d);\n\n block.sync();\n produce_kv<SharedMemFillMode::kNoFill, num_warps_x, num_warps_z, num_frags_y, num_frags_z>(\n k_smem, &kv_smem_offset_w, &k_ptr, kv_stride_n, (iter + 1) * 16 * num_warps_z * num_frags_z,\n chunk_size);\n cp_async::commit_group();\n cp_async::wait_group<1>();\n block.sync();\n\n // compute sfm*v\n compute_sfm_v<num_frags_x, num_frags_y, num_frags_z, swizzle_mode_kv, DTypeQ, DTypeKV>(\n &v_smem, &v_smem_offset_r, s_frag, o_frag, d);\n\n block.sync();\n produce_kv<SharedMemFillMode::kFillZero, num_warps_x, num_warps_z, num_frags_y, num_frags_z>(\n v_smem, &kv_smem_offset_w, &v_ptr, kv_stride_n, (iter + 1) * 16 * num_warps_z * num_frags_z,\n chunk_size);\n cp_async::commit_group();\n }\n cp_async::wait_group<0>();\n block.sync();\n\n // threadblock synchronization\n threadblock_sync_mdo_states<num_warps_x, num_warps_z, num_frags_x, num_frags_y, DTypeQKAccum>(\n o_frag, (float*)smem, m, d, warp_idx, lane_idx);\n\n // normalize d\n normalize_d<num_frags_x, num_frags_y>(o_frag, m, d);\n\n const uint32_t num_kv_chunks = (kv_len_safe + kv_chunk_size - 1) / kv_chunk_size;\n\n // write back\n write_o_reg_gmem<num_warps_x, num_warps_z, num_frags_x, num_frags_y>(\n o_frag, &qo_smem, o_ptr_base, qo_packed_idx_base, qo_len,\n /*o_stride_n=*/\n partition_kv ? num_qo_heads * head_dim * num_kv_chunks : num_qo_heads * head_dim,\n /*o_stride_h=*/head_dim, group_size);\n\n // write lse\n if (lse != nullptr) {\n if (get_warp_idx_z<num_warps_x, num_warps_z>() == 0) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n uint32_t q, r;\n group_size.divmod(qo_packed_idx_base + lane_idx / 4 + j * 8 + fx * 16, q, r);\n const uint32_t qo_head_idx = kv_head_idx * group_size + r;\n const uint32_t qo_idx = q;\n if (qo_idx < qo_len) {\n if (partition_kv) {\n lse[(o_indptr[request_idx] + qo_idx * num_kv_chunks + kv_tile_idx) * num_qo_heads +\n qo_head_idx] = math::ptx_log2(d[fx][j]) + float(m[fx][j]);\n } else {\n lse[(o_indptr[request_idx] + qo_idx) * num_qo_heads + qo_head_idx] =\n math::ptx_log2(d[fx][j]) + float(m[fx][j]);\n }\n }\n }\n }\n }\n }\n}\n\ntemplate <LogitsPostHook logits_post_hook, MaskMode mask_mode, PosEncodingMode pos_encoding_mode,\n uint32_t num_frags_x, uint32_t num_frags_y, uint32_t num_frags_z, uint32_t num_warps_x,\n uint32_t num_warps_z, PageStorage page_storage, typename DTypeQ, typename DTypeKV,\n typename DTypeQKAccum, typename DTypeOut, typename IdType>\n__global__\n__launch_bounds__(num_warps_x* num_warps_z* warp_size) void BatchPrefillWithPagedKVCacheKernel(\n IdType* __restrict__ request_indices, IdType* __restrict__ q_tile_indices,\n IdType* __restrict__ kv_tile_indices, DTypeQ* __restrict__ q,\n paged_kv_t<page_storage, DTypeKV, IdType> paged_kv, IdType* __restrict__ q_indptr,\n uint8_t* __restrict__ custom_mask, IdType* __restrict__ qk_indptr,\n IdType* __restrict__ q_offset, IdType* __restrict__ o_indptr, DTypeOut* __restrict__ o,\n float* __restrict__ lse, bool* __restrict__ block_valid_mask,\n IdType* __restrict__ kv_chunk_size_ptr, const bool partition_kv, const uint_fastdiv group_size,\n int32_t maybe_window_left, const float logits_soft_cap, float sm_scale,\n const float log2_rope_rcp_scale, const float log2_rope_rcp_theta) {\n static_assert(sizeof(DTypeQ) == 2);\n static_assert(sizeof(DTypeOut) == 2);\n sm_scale *=\n (logits_post_hook == LogitsPostHook::kNone ? math::log2e : math::ptx_rcp(logits_soft_cap));\n auto block = cg::this_thread_block();\n const uint32_t kv_chunk_size = *kv_chunk_size_ptr;\n\n const uint32_t bx = blockIdx.x, lane_idx = threadIdx.x,\n warp_idx = get_warp_idx<num_warps_x, num_warps_z>(), kv_head_idx = blockIdx.z;\n if (block_valid_mask && !block_valid_mask[bx]) {\n return;\n }\n const uint32_t num_kv_heads = gridDim.z, num_qo_heads = num_kv_heads * group_size;\n float alibi_slopes[num_frags_x][2];\n\n const uint32_t request_idx = request_indices[bx], qo_tile_idx = q_tile_indices[bx],\n kv_tile_idx = kv_tile_indices[bx];\n constexpr uint32_t num_rows_per_cta = num_frags_x * num_warps_x * 16;\n const uint32_t qo_len = q_indptr[request_idx + 1] - q_indptr[request_idx],\n kv_len = (paged_kv.indptr[request_idx + 1] != paged_kv.indptr[request_idx])\n ? (paged_kv.indptr[request_idx + 1] - paged_kv.indptr[request_idx] -\n 1) * paged_kv.page_size +\n paged_kv.last_page_len[request_idx]\n : 0;\n const uint32_t kv_len_safe = kv_len > 0 ? kv_len : 1;\n const uint32_t window_left = (maybe_window_left >= 0) ? maybe_window_left : kv_len;\n const uint32_t max_chunk_size = partition_kv ? kv_chunk_size : kv_len;\n const uint32_t chunk_start = partition_kv ? kv_tile_idx * max_chunk_size : 0;\n const uint32_t chunk_end =\n partition_kv ? min((kv_tile_idx + 1) * max_chunk_size, kv_len) : kv_len;\n const uint32_t chunk_size = chunk_end - chunk_start;\n const uint32_t qo_upper_bound =\n min(qo_len, ceil_div((qo_tile_idx + 1) * num_rows_per_cta, group_size));\n\n constexpr uint32_t head_dim = num_frags_y * 16;\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<DTypeKV>();\n constexpr uint32_t channel_size_128b_out = head_dim / num_elems_per_128b<DTypeOut>();\n\n extern __shared__ uint8_t smem[];\n\n DTypeQKAccum s_frag[num_frags_x][num_frags_z][8];\n float o_frag[num_frags_x][num_frags_y][8];\n DTypeQKAccum m[num_frags_x][2];\n float d[num_frags_x][2];\n float rope_freq[num_frags_y / 2][4];\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kRoPELlama) {\n init_rope_freq<num_frags_y>(rope_freq, log2_rope_rcp_scale, log2_rope_rcp_theta);\n }\n init_states<num_frags_x, num_frags_y>(o_frag, m, d);\n\n const uint32_t qo_packed_idx_base =\n (qo_tile_idx * num_warps_x + get_warp_idx_x<num_warps_x, num_warps_z>()) * num_frags_x * 16;\n const uint32_t q_stride_n = num_qo_heads * head_dim, q_stride_h = head_dim;\n constexpr SwizzleMode swizzle_mode_q = SwizzleMode::k128B;\n smem_t<swizzle_mode_q> qo_smem(smem);\n DTypeQ* q_ptr_base = q + get_elem_offset_impl(q_indptr[request_idx], kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeQ>(),\n q_stride_n, q_stride_h);\n DTypeOut* o_ptr_base =\n partition_kv ? o + kv_tile_idx * num_qo_heads * head_dim +\n get_elem_offset_impl(o_indptr[request_idx], kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeOut>(),\n num_qo_heads * head_dim, head_dim)\n : o + get_elem_offset_impl(o_indptr[request_idx], kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeOut>(),\n num_qo_heads * head_dim, head_dim);\n uint32_t q_smem_offset_r = qo_smem.get_permuted_offset<channel_size_128b_q>(\n get_warp_idx_x<num_warps_x, num_warps_z>() * num_frags_x * 16 + lane_idx % 16, lane_idx / 16);\n\n load_q_global_smem<num_warps_x, num_warps_z, num_frags_x, num_frags_y>(\n qo_packed_idx_base, qo_upper_bound, q_ptr_base, q_stride_n, q_stride_h, group_size, &qo_smem);\n\n cp_async::commit_group();\n cp_async::wait_group<0>();\n block.sync();\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kRoPELlama) {\n if (q_offset == nullptr) {\n q_smem_inplace_apply_rotary_multiply_sm_scale<num_warps_x, num_warps_z, num_frags_x,\n num_frags_y, swizzle_mode_q, DTypeQ>(\n qo_packed_idx_base, qo_len, kv_len, group_size, &qo_smem, &q_smem_offset_r, rope_freq,\n sm_scale);\n } else {\n q_smem_inplace_apply_rotary_with_pos_multiply_sm_scale<num_warps_x, num_warps_z, num_frags_x,\n num_frags_y, swizzle_mode_q, DTypeQ>(\n qo_packed_idx_base, q_offset + q_indptr[request_idx], &qo_smem, group_size,\n &q_smem_offset_r, rope_freq, sm_scale);\n }\n } else {\n q_smem_inplace_multiply_sm_scale<num_warps_x, num_warps_z, num_frags_x, num_frags_y,\n swizzle_mode_q, DTypeQ>(&qo_smem, sm_scale);\n }\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kALiBi) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n const uint32_t qo_head_idx =\n kv_head_idx * group_size +\n (qo_packed_idx_base + lane_idx / 4 + j * 8 + fx * 16) % group_size;\n alibi_slopes[fx][j] = get_alibi_slope(qo_head_idx, num_qo_heads) * math::log2e;\n }\n }\n }\n\n constexpr SwizzleMode swizzle_mode_kv =\n (sizeof(DTypeKV) == 1 && head_dim == 64) ? SwizzleMode::k64B : SwizzleMode::k128B;\n constexpr uint32_t kv_frag_rows = swizzle_mode_kv == SwizzleMode::k128B ? 4 : 8;\n constexpr uint32_t kv_frag_cols = swizzle_mode_kv == SwizzleMode::k128B ? 8 : 4;\n smem_t<swizzle_mode_kv> k_smem(smem +\n (num_warps_x * num_frags_x * sizeof(DTypeQ)) * 16 * head_dim),\n v_smem(smem + (num_warps_x * num_frags_x * sizeof(DTypeQ) +\n num_warps_z * num_frags_z * sizeof(DTypeKV)) *\n 16 * head_dim);\n size_t kv_offset[num_frags_z * (swizzle_mode_kv == SwizzleMode::k128B ? 4 : 2) / num_warps_x];\n\n uint32_t k_smem_offset_r = k_smem.get_permuted_offset<channel_size_128b_kv>(\n get_warp_idx_z<num_warps_x, num_warps_z>() * num_frags_z * 16 + 8 * (lane_idx / 16) +\n lane_idx % 8,\n (lane_idx % 16) / 8),\n v_smem_offset_r = v_smem.get_permuted_offset<channel_size_128b_kv>(\n get_warp_idx_z<num_warps_x, num_warps_z>() * num_frags_z * 16 + lane_idx % 16,\n lane_idx / 16),\n kv_smem_offset_w = k_smem.get_permuted_offset<channel_size_128b_kv>(\n warp_idx * kv_frag_rows + lane_idx / kv_frag_cols, lane_idx % kv_frag_cols);\n const IdType last_indptr = paged_kv.indptr[paged_kv.batch_size];\n\n uint32_t packed_page_iter_base = paged_kv.indptr[request_idx] * paged_kv.page_size + chunk_start;\n#pragma unroll\n for (uint32_t i = 0;\n i < num_frags_z * (swizzle_mode_kv == SwizzleMode::k128B ? 4 : 2) / num_warps_x; ++i) {\n uint32_t page_iter, entry_idx;\n paged_kv.page_size.divmod(packed_page_iter_base + warp_idx * kv_frag_rows +\n lane_idx / kv_frag_cols +\n kv_frag_rows * num_warps_x * num_warps_z * i,\n page_iter, entry_idx);\n kv_offset[i] =\n page_iter < last_indptr\n ? paged_kv.get_elem_offset(__ldg(paged_kv.indices + page_iter), kv_head_idx, entry_idx,\n (lane_idx % kv_frag_cols) * num_elems_per_128b<DTypeKV>())\n : 0;\n }\n page_produce_kv<false, num_warps_x, num_warps_z, num_frags_y, num_frags_z>(\n k_smem, &kv_smem_offset_w, paged_kv, 0, kv_offset, chunk_size);\n cp_async::commit_group();\n page_produce_kv<true, num_warps_x, num_warps_z, num_frags_y, num_frags_z>(\n v_smem, &kv_smem_offset_w, paged_kv, 0, kv_offset, chunk_size);\n cp_async::commit_group();\n\n const uint32_t num_iterations =\n ceil_div((mask_mode == MaskMode::kCausal\n ? min(chunk_size,\n sub_if_greater_or_zero(\n kv_len - qo_len + ((qo_tile_idx + 1) * num_rows_per_cta) / group_size,\n chunk_start))\n : chunk_size),\n 16 * num_warps_z * num_frags_z);\n\n const uint32_t window_iteration =\n ceil_div(sub_if_greater_or_zero(kv_len + (bx + 1) * num_rows_per_cta,\n qo_len + window_left + chunk_start),\n (16 * num_warps_z * num_frags_z));\n\n const uint32_t mask_iteration =\n (mask_mode == MaskMode::kCausal\n ? min(chunk_size,\n sub_if_greater_or_zero(\n kv_len + (qo_tile_idx * num_rows_per_cta) / group_size - qo_len, chunk_start))\n : chunk_size) /\n (16 * num_warps_z * num_frags_z);\n\n#pragma unroll 1\n for (uint32_t iter = 0; iter < num_iterations; ++iter) {\n packed_page_iter_base += 16 * num_warps_z * num_frags_z;\n#pragma unroll\n for (uint32_t i = 0;\n i < num_frags_z * (swizzle_mode_kv == SwizzleMode::k128B ? 4 : 2) / num_warps_x; ++i) {\n uint32_t page_iter, entry_idx;\n paged_kv.page_size.divmod(packed_page_iter_base + warp_idx * kv_frag_rows +\n lane_idx / kv_frag_cols +\n kv_frag_rows * num_warps_x * num_warps_z * i,\n page_iter, entry_idx);\n kv_offset[i] = page_iter < last_indptr\n ? paged_kv.get_elem_offset(\n __ldg(paged_kv.indices + page_iter), kv_head_idx, entry_idx,\n (lane_idx % kv_frag_cols) * num_elems_per_128b<DTypeKV>())\n : 0;\n }\n cp_async::wait_group<1>();\n block.sync();\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kRoPELlama) {\n k_smem_inplace_apply_rotary<num_warps_x, num_warps_z, num_frags_y, num_frags_z,\n swizzle_mode_kv, DTypeKV>(\n (paged_kv.rope_pos_offset == nullptr ? 0 : paged_kv.rope_pos_offset[request_idx]) +\n chunk_start + iter * 16 * num_warps_z * num_frags_z,\n &k_smem, &k_smem_offset_r, rope_freq);\n block.sync();\n }\n\n // compute attention score\n compute_qk<logits_post_hook, num_frags_x, num_frags_y, num_frags_z, swizzle_mode_q,\n swizzle_mode_kv, DTypeQ, DTypeKV>(&qo_smem, &q_smem_offset_r, &k_smem,\n &k_smem_offset_r, s_frag, logits_soft_cap);\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kALiBi) {\n // TODO(Zihao): handle the case that q_offset is specified\n apply_alibi_bias<num_frags_x, num_frags_z>(\n qo_packed_idx_base,\n chunk_start +\n (iter * num_warps_z + get_warp_idx_z<num_warps_x, num_warps_z>()) * num_frags_z * 16,\n int(kv_len) - int(qo_len), group_size, alibi_slopes, s_frag);\n }\n // apply mask\n if constexpr (mask_mode == MaskMode::kCustom) {\n mask_s<mask_mode, num_frags_x, num_frags_y, num_frags_z>(\n qo_packed_idx_base,\n chunk_start +\n (iter * num_warps_z + get_warp_idx_z<num_warps_x, num_warps_z>()) * num_frags_z * 16,\n qo_len, kv_len, window_left, chunk_end, group_size, custom_mask + qk_indptr[request_idx],\n s_frag);\n } else {\n if (iter >= mask_iteration || iter < window_iteration) {\n mask_s<mask_mode, num_frags_x, num_frags_y, num_frags_z>(\n qo_packed_idx_base,\n chunk_start + (iter * num_warps_z + get_warp_idx_z<num_warps_x, num_warps_z>()) *\n num_frags_z * 16,\n qo_len, kv_len, window_left, chunk_end, group_size, nullptr, s_frag);\n }\n }\n\n // compute m,d states in online softmax\n update_mdo_states<num_frags_x, num_frags_y, num_frags_z>(s_frag, o_frag, m, d);\n\n block.sync();\n page_produce_kv<false, num_warps_x, num_warps_z, num_frags_y, num_frags_z>(\n k_smem, &kv_smem_offset_w, paged_kv, (iter + 1) * 16 * num_warps_z * num_frags_z, kv_offset,\n chunk_size);\n cp_async::commit_group();\n cp_async::wait_group<1>();\n block.sync();\n\n // compute sfm*v\n compute_sfm_v<num_frags_x, num_frags_y, num_frags_z, swizzle_mode_kv, DTypeQ, DTypeKV>(\n &v_smem, &v_smem_offset_r, s_frag, o_frag, d);\n\n block.sync();\n page_produce_kv<true, num_warps_x, num_warps_z, num_frags_y, num_frags_z>(\n v_smem, &kv_smem_offset_w, paged_kv, (iter + 1) * 16 * num_warps_z * num_frags_z, kv_offset,\n chunk_size);\n cp_async::commit_group();\n }\n cp_async::wait_group<0>();\n block.sync();\n\n // threadblock synchronization\n threadblock_sync_mdo_states<num_warps_x, num_warps_z, num_frags_x, num_frags_y, DTypeQKAccum>(\n o_frag, (float*)smem, m, d, warp_idx, lane_idx);\n\n // normalize d\n normalize_d<num_frags_x, num_frags_y>(o_frag, m, d);\n\n const uint32_t num_kv_chunks = (kv_len_safe + kv_chunk_size - 1) / kv_chunk_size;\n\n // write_back\n write_o_reg_gmem<num_warps_x, num_warps_z, num_frags_x, num_frags_y>(\n o_frag, &qo_smem, o_ptr_base, qo_packed_idx_base, qo_len,\n /*o_stride_n=*/\n partition_kv ? num_qo_heads * head_dim * num_kv_chunks : num_qo_heads * head_dim,\n /*o_stride_h=*/head_dim, group_size);\n\n // write lse\n if (lse != nullptr) {\n if (get_warp_idx_z<num_warps_x, num_warps_z>() == 0) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n uint32_t q, r;\n group_size.divmod(qo_packed_idx_base + lane_idx / 4 + j * 8 + fx * 16, q, r);\n const uint32_t qo_head_idx = kv_head_idx * group_size + r;\n const uint32_t qo_idx = q;\n if (qo_idx < qo_upper_bound) {\n if (partition_kv) {\n lse[(o_indptr[request_idx] + qo_idx * num_kv_chunks + kv_tile_idx) * num_qo_heads +\n qo_head_idx] = math::ptx_log2(d[fx][j]) + float(m[fx][j]);\n } else {\n lse[(o_indptr[request_idx] + qo_idx) * num_qo_heads + qo_head_idx] =\n math::ptx_log2(d[fx][j]) + float(m[fx][j]);\n }\n }\n }\n }\n }\n }\n}\n\ntemplate <uint32_t HEAD_DIM, LogitsPostHook LOGITS_POST_HOOK, PosEncodingMode pos_encoding_mode,\n bool ALLOW_FP16_QK_REDUCTION, MaskMode MASK_MODE, typename DTypeQ, typename DTypeKV,\n typename DTypeOut>\ncudaError_t SinglePrefillWithKVCacheDispatched(\n DTypeQ* q, DTypeKV* k, DTypeKV* v, uint8_t* custom_mask, DTypeOut* o, DTypeOut* tmp, float* lse,\n uint32_t num_qo_heads, uint32_t num_kv_heads, uint32_t qo_len, uint32_t kv_len,\n uint32_t q_stride_n, uint32_t q_stride_h, uint32_t kv_stride_n, uint32_t kv_stride_h,\n int32_t window_left, float logits_soft_cap, float sm_scale, float rope_scale, float rope_theta,\n cudaStream_t stream) {\n const float log2_rope_rcp_scale = -std::log2f(rope_scale);\n const float log2_rope_rcp_theta = -std::log2f(rope_theta);\n if (kv_len < qo_len && MASK_MODE == MaskMode::kCausal) {\n std::ostringstream err_msg;\n err_msg << \"When mask_mode is set to MaskMode::kCausal, kv_len must be greater than or equal \"\n \"to qo_len, got kv_len\"\n << kv_len << \" and qo_len \" << qo_len;\n throw std::invalid_argument(err_msg.str());\n }\n\n const uint32_t group_size = num_qo_heads / num_kv_heads;\n const uint_fastdiv group_size_fastdiv(group_size);\n constexpr uint32_t num_frags_y = HEAD_DIM / 16;\n WarpLayout warp_layout;\n int64_t unpacked_qo_len = qo_len * group_size;\n if (unpacked_qo_len > 64 && HEAD_DIM < 256) {\n warp_layout = WarpLayout::k4x1x2;\n } else {\n if (unpacked_qo_len > 16) {\n warp_layout = WarpLayout::k4x1x1;\n } else {\n warp_layout = WarpLayout::k1x4x1;\n }\n }\n\n DISPATCH_WARP_LAYOUT(warp_layout, WARP_LAYOUT, {\n constexpr uint32_t num_frags_x = get_num_frags_x<WARP_LAYOUT>();\n using DTypeQKAccum =\n typename std::conditional<ALLOW_FP16_QK_REDUCTION && std::is_same<DTypeQ, half>::value,\n half, float>::type;\n\n int dev_id = 0;\n FLASHINFER_CUDA_CALL(cudaGetDevice(&dev_id));\n int max_smem_per_sm = 0;\n FLASHINFER_CUDA_CALL(cudaDeviceGetAttribute(\n &max_smem_per_sm, cudaDevAttrMaxSharedMemoryPerMultiprocessor, dev_id));\n // we expect each sm execute two threadblocks\n // TODO(Zihao): fix the following computation\n const int num_ctas_per_sm = max_smem_per_sm > (16 * HEAD_DIM * sizeof(DTypeQ) * 16) ? 2 : 1;\n const int max_smem_per_threadblock = max_smem_per_sm / num_ctas_per_sm;\n\n constexpr uint32_t num_warps_x = get_num_warps_x<WARP_LAYOUT>();\n constexpr uint32_t num_warps_z = get_num_warps_z<WARP_LAYOUT>();\n const uint32_t max_num_frags_z_reg =\n (HEAD_DIM >= 128 && num_frags_x == 2 && pos_encoding_mode == PosEncodingMode::kRoPELlama &&\n !ALLOW_FP16_QK_REDUCTION)\n ? 2\n : (8 / num_frags_x);\n // TODO(Zihao): fix the following computation\n const uint32_t max_num_frags_z_smem =\n (max_smem_per_threadblock / (16 * HEAD_DIM * sizeof(DTypeQ)) - num_frags_x * num_warps_x) /\n (2 * num_warps_z);\n\n // control num_frags_z for maximum warp occupancy\n DISPATCH_NUM_FRAGS_Z(min(max_num_frags_z_smem, max_num_frags_z_reg), num_frags_z, {\n if constexpr (is_invalid_configuration<pos_encoding_mode, DTypeKV, DTypeQKAccum>(\n num_frags_x, num_frags_y, num_frags_z, num_warps_x, num_warps_z)) {\n // Invalid configuration, skip\n std::ostringstream err_msg;\n err_msg << \"FlashInfer Internal Error: Invalid configuration : num_frags_x=\" << num_frags_x\n << \" num_frags_y=\" << num_frags_y << \" num_frags_z=\" << num_frags_z\n << \" num_warps_x=\" << num_warps_x << \" num_warps_z=\" << num_warps_z\n << \" please create an issue (https://github.com/flashinfer-ai/flashinfer/issues)\"\n \" and report the issue to the developers.\";\n throw std::invalid_argument(err_msg.str());\n } else {\n constexpr uint32_t num_threads = (num_warps_x * num_warps_z) * warp_size;\n constexpr uint32_t num_rows_per_cta = num_frags_x * num_warps_x * 16;\n auto kernel =\n SinglePrefillWithKVCacheKernel<LOGITS_POST_HOOK, MASK_MODE, pos_encoding_mode,\n num_frags_x, num_frags_y, num_frags_z, num_warps_x,\n num_warps_z, DTypeQ, DTypeKV, DTypeQKAccum, DTypeOut>;\n // TODO(Zihao): fix the following computation\n uint32_t smem_size = (num_frags_x * num_warps_x * sizeof(DTypeQ) +\n num_frags_z * num_warps_z * 2 * sizeof(DTypeQ)) *\n 16 * HEAD_DIM;\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n int num_blocks_per_sm = 0;\n int num_sm = 0;\n FLASHINFER_CUDA_CALL(\n cudaDeviceGetAttribute(&num_sm, cudaDevAttrMultiProcessorCount, dev_id));\n FLASHINFER_CUDA_CALL(cudaOccupancyMaxActiveBlocksPerMultiprocessor(\n &num_blocks_per_sm, kernel, num_threads, smem_size));\n uint32_t max_num_kv_chunks =\n (num_blocks_per_sm * num_sm) /\n (num_kv_heads * ceil_div(qo_len * group_size, num_rows_per_cta));\n uint32_t num_chunks;\n if (max_num_kv_chunks > 0) {\n uint32_t chunk_size = max(ceil_div(kv_len, max_num_kv_chunks), 256);\n num_chunks = ceil_div(kv_len, chunk_size);\n } else {\n num_chunks = 0;\n }\n\n if (num_chunks <= 1 || tmp == nullptr) {\n // Enough parallelism, do not split-kv\n bool partition_kv = false;\n void* args[] = {(void*)&q,\n (void*)&k,\n (void*)&v,\n (void*)&custom_mask,\n (void*)&o,\n (void*)&lse,\n (void*)&qo_len,\n (void*)&kv_len,\n (void*)&partition_kv,\n (void*)&group_size_fastdiv,\n (void*)&q_stride_n,\n (void*)&q_stride_h,\n (void*)&kv_stride_n,\n (void*)&kv_stride_h,\n (void*)&window_left,\n (void*)&logits_soft_cap,\n (void*)&sm_scale,\n (void*)&log2_rope_rcp_scale,\n (void*)&log2_rope_rcp_theta};\n dim3 nblks(ceil_div(qo_len * group_size, num_rows_per_cta), 1, num_kv_heads);\n dim3 nthrs(32, num_warps_x, num_warps_z);\n\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n } else {\n // Use cooperative groups to increase occupancy\n bool partition_kv = true;\n float* tmp_lse = (float*)(tmp + num_chunks * qo_len * num_qo_heads * HEAD_DIM);\n void* args[] = {(void*)&q,\n (void*)&k,\n (void*)&v,\n (void*)&custom_mask,\n (void*)&tmp,\n (void*)&tmp_lse,\n (void*)&qo_len,\n (void*)&kv_len,\n (void*)&partition_kv,\n (void*)&group_size_fastdiv,\n (void*)&q_stride_n,\n (void*)&q_stride_h,\n (void*)&kv_stride_n,\n (void*)&kv_stride_h,\n (void*)&window_left,\n (void*)&logits_soft_cap,\n (void*)&sm_scale,\n (void*)&log2_rope_rcp_scale,\n (void*)&log2_rope_rcp_theta};\n dim3 nblks(ceil_div(qo_len * group_size, num_rows_per_cta), num_chunks, num_kv_heads);\n dim3 nthrs(32, num_warps_x, num_warps_z);\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n FLASHINFER_CUDA_CALL(MergeStates(tmp, tmp_lse, o, lse, num_chunks, qo_len, num_qo_heads,\n HEAD_DIM, stream));\n }\n }\n })\n });\n return cudaSuccess;\n}\n\ntemplate <WarpLayout WARP_LAYOUT, uint32_t HEAD_DIM, LogitsPostHook LOGITS_POST_HOOK,\n PosEncodingMode pos_encoding_mode, bool ALLOW_FP16_QK_REDUCTION, MaskMode MASK_MODE,\n typename DTypeQ, typename DTypeKV, typename DTypeOut, typename IdType>\ncudaError_t BatchPrefillWithRaggedKVCacheDispatched(\n DTypeQ* q, IdType* request_indices, IdType* q_tile_indices, IdType* kv_tile_indices,\n IdType* q_indptr, DTypeKV* k, DTypeKV* v, IdType* kv_indptr, uint8_t* custom_mask,\n IdType* qk_indptr, IdType* q_offset, IdType* k_rope_pos_offset, IdType* o_indptr, DTypeOut* o,\n DTypeOut* tmp_v, float* tmp_s, float* lse, IdType* merge_indptr, bool* block_valid_mask,\n IdType* kv_chunk_size_ptr, uint32_t total_num_rows, uint32_t num_qo_heads,\n uint32_t padded_batch_size, uint32_t num_kv_heads, uint32_t q_stride_n, uint32_t q_stride_h,\n uint32_t kv_stride_n, uint32_t kv_stride_h, int32_t window_left, float logits_soft_cap,\n float sm_scale, float rope_scale, float rope_theta, cudaStream_t stream = nullptr) {\n const float log2_rope_rcp_scale = -std::log2f(rope_scale);\n const float log2_rope_rcp_theta = -std::log2f(rope_theta);\n constexpr uint32_t num_frags_x = get_num_frags_x<WARP_LAYOUT>();\n constexpr uint32_t num_warps_x = get_num_warps_x<WARP_LAYOUT>();\n constexpr uint32_t num_warps_z = get_num_warps_z<WARP_LAYOUT>();\n const uint32_t group_size = num_qo_heads / num_kv_heads;\n const uint_fastdiv group_size_fastdiv(group_size);\n\n if (padded_batch_size == 0) {\n // No request, skip\n // this won't happen in CUDAGraph mode because we fixed the padded_batch_size\n return cudaSuccess;\n }\n\n dim3 nblks(padded_batch_size, 1, num_kv_heads);\n dim3 nthrs(32, num_warps_x, num_warps_z);\n constexpr uint32_t num_frags_y = HEAD_DIM / 16;\n using DTypeQKAccum =\n typename std::conditional<ALLOW_FP16_QK_REDUCTION && std::is_same<DTypeQ, half>::value, half,\n float>::type;\n\n int dev_id = 0;\n FLASHINFER_CUDA_CALL(cudaGetDevice(&dev_id));\n int max_smem_per_sm = 0;\n FLASHINFER_CUDA_CALL(cudaDeviceGetAttribute(&max_smem_per_sm,\n cudaDevAttrMaxSharedMemoryPerMultiprocessor, dev_id));\n // we expect each sm execute two threadblocks\n // TODO(Zihao): fix the following computation\n const int num_ctas_per_sm = max_smem_per_sm > (16 * HEAD_DIM * sizeof(DTypeQ) * 16) ? 2 : 1;\n const int max_smem_per_threadblock = max_smem_per_sm / num_ctas_per_sm;\n\n const uint32_t max_num_frags_z_reg =\n (HEAD_DIM >= 128 && num_frags_x == 2 && pos_encoding_mode == PosEncodingMode::kRoPELlama &&\n !ALLOW_FP16_QK_REDUCTION)\n ? 2\n : (8 / num_frags_x);\n // TODO(Zihao): fix the following computation\n const uint32_t max_num_frags_z_smem =\n (max_smem_per_threadblock / (16 * HEAD_DIM * sizeof(DTypeQ)) - num_frags_x * num_warps_x) /\n (2 * num_warps_z);\n\n DISPATCH_NUM_FRAGS_Z(min(max_num_frags_z_smem, max_num_frags_z_reg), num_frags_z, {\n if constexpr (is_invalid_configuration<pos_encoding_mode, DTypeKV, DTypeQKAccum>(\n num_frags_x, num_frags_y, num_frags_z, num_warps_x, num_warps_z)) {\n // Invalid configuration, skip\n std::ostringstream err_msg;\n err_msg << \"FlashInfer Internal Error: Invalid configuration : num_frags_x=\" << num_frags_x\n << \" num_frags_y=\" << num_frags_y << \" num_frags_z=\" << num_frags_z\n << \" num_warps_x=\" << num_warps_x << \" num_warps_z=\" << num_warps_z\n << \" please create an issue (https://github.com/flashinfer-ai/flashinfer/issues)\"\n \" and report the issue to the developers.\";\n throw std::invalid_argument(err_msg.str());\n } else {\n // TODO(Zihao): fix the following computation\n uint32_t smem_size = (num_frags_x * num_warps_x * sizeof(DTypeQ) +\n num_frags_z * num_warps_z * 2 * sizeof(DTypeQ)) *\n 16 * HEAD_DIM;\n auto kernel = BatchPrefillWithRaggedKVCacheKernel<\n LOGITS_POST_HOOK, MASK_MODE, pos_encoding_mode, num_frags_x, num_frags_y, num_frags_z,\n num_warps_x, num_warps_z, DTypeQ, DTypeKV, DTypeQKAccum, DTypeOut, IdType>;\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n if (tmp_v == nullptr) {\n // do not partition kv\n bool partition_kv = false;\n\n void* args[] = {(void*)&q,\n (void*)&request_indices,\n (void*)&q_tile_indices,\n (void*)&kv_tile_indices,\n (void*)&q_indptr,\n (void*)&k,\n (void*)&v,\n (void*)&kv_indptr,\n (void*)&custom_mask,\n (void*)&qk_indptr,\n (void*)&q_offset,\n (void*)&k_rope_pos_offset,\n (void*)&o_indptr,\n (void*)&o,\n (void*)&lse,\n (void*)&block_valid_mask,\n (void*)&kv_chunk_size_ptr,\n (void*)&partition_kv,\n (void*)&group_size_fastdiv,\n (void*)&q_stride_n,\n (void*)&q_stride_h,\n (void*)&kv_stride_n,\n (void*)&kv_stride_h,\n (void*)&window_left,\n (void*)&logits_soft_cap,\n (void*)&sm_scale,\n (void*)&log2_rope_rcp_scale,\n (void*)&log2_rope_rcp_theta};\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n } else {\n // partition kv\n bool partition_kv = true;\n void* args[] = {(void*)&q,\n (void*)&request_indices,\n (void*)&q_tile_indices,\n (void*)&kv_tile_indices,\n (void*)&q_indptr,\n (void*)&k,\n (void*)&v,\n (void*)&kv_indptr,\n (void*)&custom_mask,\n (void*)&qk_indptr,\n (void*)&q_offset,\n (void*)&k_rope_pos_offset,\n (void*)&o_indptr,\n (void*)&tmp_v,\n (void*)&tmp_s,\n (void*)&block_valid_mask,\n (void*)&kv_chunk_size_ptr,\n (void*)&partition_kv,\n (void*)&group_size_fastdiv,\n (void*)&q_stride_n,\n (void*)&q_stride_h,\n (void*)&kv_stride_n,\n (void*)&kv_stride_h,\n (void*)&window_left,\n (void*)&logits_soft_cap,\n (void*)&sm_scale,\n (void*)&log2_rope_rcp_scale,\n (void*)&log2_rope_rcp_theta};\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n FLASHINFER_CUDA_CALL(VariableLengthMergeStates(\n tmp_v, tmp_s, merge_indptr, o, lse, total_num_rows, num_qo_heads, HEAD_DIM, stream));\n }\n }\n });\n return cudaSuccess;\n}\n\ntemplate <PageStorage page_storage, WarpLayout WARP_LAYOUT, uint32_t HEAD_DIM,\n LogitsPostHook LOGITS_POST_HOOK, PosEncodingMode pos_encoding_mode,\n bool ALLOW_FP16_QK_REDUCTION, MaskMode MASK_MODE, typename DTypeQ, typename DTypeKV,\n typename DTypeOut, typename IdType>\ncudaError_t BatchPrefillWithPagedKVCacheDispatched(\n DTypeQ* q, IdType* request_indices, IdType* q_tile_indices, IdType* kv_tile_indices,\n IdType* q_indptr, IdType* q_offset, paged_kv_t<page_storage, DTypeKV, IdType> paged_kv,\n uint8_t* custom_mask, IdType* qk_indptr, IdType* o_indptr, DTypeOut* o, DTypeOut* tmp_v,\n float* tmp_s, float* lse, IdType* merge_indptr, bool* block_valid_mask,\n IdType* kv_chunk_size_ptr, uint32_t total_num_rows, uint32_t num_qo_heads,\n uint32_t padded_batch_size, int32_t window_left, float logits_soft_cap, float sm_scale,\n float rope_scale, float rope_theta, cudaStream_t stream) {\n const float log2_rope_rcp_scale = -std::log2f(rope_scale);\n const float log2_rope_rcp_theta = -std::log2f(rope_theta);\n constexpr uint32_t num_frags_x = get_num_frags_x<WARP_LAYOUT>();\n constexpr uint32_t num_warps_x = get_num_warps_x<WARP_LAYOUT>();\n constexpr uint32_t num_warps_z = get_num_warps_z<WARP_LAYOUT>();\n const uint32_t num_kv_heads = paged_kv.num_heads;\n const uint32_t group_size = num_qo_heads / num_kv_heads;\n const uint_fastdiv group_size_fastdiv(group_size);\n\n if (padded_batch_size == 0) {\n // No request, skip\n // this won't happen in CUDAGraph mode because we fixed the padded_batch_size\n return cudaSuccess;\n }\n\n dim3 nblks(padded_batch_size, 1, num_kv_heads);\n dim3 nthrs(32, num_warps_x, num_warps_z);\n\n constexpr uint32_t num_frags_y = HEAD_DIM / 16;\n using DTypeQKAccum =\n typename std::conditional<ALLOW_FP16_QK_REDUCTION && std::is_same<DTypeQ, half>::value, half,\n float>::type;\n\n int dev_id = 0;\n FLASHINFER_CUDA_CALL(cudaGetDevice(&dev_id));\n int max_smem_per_sm = 0;\n FLASHINFER_CUDA_CALL(cudaDeviceGetAttribute(&max_smem_per_sm,\n cudaDevAttrMaxSharedMemoryPerMultiprocessor, dev_id));\n // we expect each sm execute two threadblocks\n // TODO(Zihao): fix the following computation\n const int num_ctas_per_sm = max_smem_per_sm > (16 * HEAD_DIM * sizeof(DTypeQ) * 16) ? 2 : 1;\n const int max_smem_per_threadblock = max_smem_per_sm / num_ctas_per_sm;\n\n const uint32_t max_num_frags_z_reg =\n (HEAD_DIM >= 128 && num_frags_x == 2 && pos_encoding_mode == PosEncodingMode::kRoPELlama &&\n !ALLOW_FP16_QK_REDUCTION)\n ? 2\n : (8 / num_frags_x);\n // TODO(Zihao): fix the following computation\n const uint32_t max_num_frags_z_smem =\n (max_smem_per_threadblock / (16 * HEAD_DIM * sizeof(DTypeQ)) - num_frags_x * num_warps_x) /\n (2 * num_warps_z);\n\n DISPATCH_NUM_FRAGS_Z(min(max_num_frags_z_smem, max_num_frags_z_reg), num_frags_z, {\n if constexpr (is_invalid_configuration<pos_encoding_mode, DTypeKV, DTypeQKAccum>(\n num_frags_x, num_frags_y, num_frags_z, num_warps_x, num_warps_z)) {\n // Invalid configuration, skip\n std::ostringstream err_msg;\n err_msg << \"FlashInfer Internal Error: Invalid configuration : num_frags_x=\" << num_frags_x\n << \" num_frags_y=\" << num_frags_y << \" num_frags_z=\" << num_frags_z\n << \" num_warps_x=\" << num_warps_x << \" num_warps_z=\" << num_warps_z\n << \" please create an issue (https://github.com/flashinfer-ai/flashinfer/issues)\"\n \" and report the issue to the developers.\";\n throw std::invalid_argument(err_msg.str());\n } else {\n // TODO(Zihao): fix the following computation\n uint32_t smem_size = (num_frags_x * num_warps_x * sizeof(DTypeQ) +\n num_frags_z * num_warps_z * 2 * sizeof(DTypeQ)) *\n 16 * HEAD_DIM;\n auto kernel = BatchPrefillWithPagedKVCacheKernel<\n LOGITS_POST_HOOK, MASK_MODE, pos_encoding_mode, num_frags_x, num_frags_y, num_frags_z,\n num_warps_x, num_warps_z, page_storage, DTypeQ, DTypeKV, DTypeQKAccum, DTypeOut, IdType>;\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n if (tmp_v == nullptr) {\n // do not partition kv\n bool partition_kv = false;\n void* args[] = {(void*)&request_indices,\n (void*)&q_tile_indices,\n (void*)&kv_tile_indices,\n (void*)&q,\n (void*)&paged_kv,\n (void*)&q_indptr,\n (void*)&custom_mask,\n (void*)&qk_indptr,\n (void*)&q_offset,\n (void*)&o_indptr,\n (void*)&o,\n (void*)&lse,\n (void*)&block_valid_mask,\n (void*)&kv_chunk_size_ptr,\n (void*)&partition_kv,\n (void*)&group_size_fastdiv,\n (void*)&window_left,\n (void*)&logits_soft_cap,\n (void*)&sm_scale,\n (void*)&log2_rope_rcp_scale,\n (void*)&log2_rope_rcp_theta};\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n } else {\n bool partition_kv = true;\n void* args[] = {(void*)&request_indices,\n (void*)&q_tile_indices,\n (void*)&kv_tile_indices,\n (void*)&q,\n (void*)&paged_kv,\n (void*)&q_indptr,\n (void*)&custom_mask,\n (void*)&qk_indptr,\n (void*)&q_offset,\n (void*)&o_indptr,\n (void*)&tmp_v,\n (void*)&tmp_s,\n (void*)&block_valid_mask,\n (void*)&kv_chunk_size_ptr,\n (void*)&partition_kv,\n (void*)&group_size_fastdiv,\n (void*)&window_left,\n (void*)&logits_soft_cap,\n (void*)&sm_scale,\n (void*)&log2_rope_rcp_scale,\n (void*)&log2_rope_rcp_theta};\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n FLASHINFER_CUDA_CALL(VariableLengthMergeStates(\n tmp_v, tmp_s, merge_indptr, o, lse, total_num_rows, num_qo_heads, HEAD_DIM, stream));\n }\n }\n });\n return cudaSuccess;\n}\n\n} // namespace flashinfer\n\n#endif // FLASHINFER_PREFILL_CUH_\n"},"diff":{"kind":"string","value":"--- include/flashinfer/attention/prefill.cuh\n+++ include/flashinfer/attention/prefill.cuh\n@@ -802,8 +802,8 @@\n }\n b_frag_f8[0] = frag_layout_swizzle_16b_to_8b_trans(b_frag_f8[0]);\n b_frag_f8[1] = frag_layout_swizzle_16b_to_8b_trans(b_frag_f8[1]);\n- bfly_exch(b_frag_f8[0], b_frag_f8[1]);\n vec_cast<DTypeQ, DTypeKV>::cast<8>((DTypeQ*)b_frag, (DTypeKV*)b_frag_f8);\n+ swap(b_frag[1], b_frag[2]);\n } else {\n v_smem->ldmatrix_m8n8x4_trans(*v_smem_offset_r, b_frag);\n }"},"lines_added":{"kind":"number","value":1,"string":"1"},"lines_removed":{"kind":"number","value":1,"string":"1"},"files_in_commit":{"kind":"number","value":3,"string":"3"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/prefill.cuh).\n\nGoal: perf: slight optimization on f16->f8 fragment layout swizzling\nTarget hardware: unspecified\nTarget models: unspecified\n\nCurrent file:\n```cuda\n/*\n * Copyright (c) 2023 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_PREFILL_CUH_\n#define FLASHINFER_PREFILL_CUH_\n#include <cooperative_groups.h>\n#include <cuda_bf16.h>\n#include <cuda_fp16.h>\n#ifdef FLASHINFER_ENABLE_FP8\n#include <cuda_fp8.h>\n#endif\n#include <cuda_runtime.h>\n\n#include \"../cp_async.cuh\"\n#include \"../fastdiv.cuh\"\n#include \"../frag_layout_swizzle.cuh\"\n#include \"../layout.cuh\"\n#include \"../math.cuh\"\n#include \"../mma.cuh\"\n#include \"../page.cuh\"\n#include \"../permuted_smem.cuh\"\n#include \"../pos_enc.cuh\"\n#include \"../utils.cuh\"\n#include \"cascade.cuh\"\n#include \"logits_post_hook.cuh\"\n#include \"mask.cuh\"\n#include \"warp_layout.cuh\"\n\nnamespace flashinfer {\n\nnamespace cg = cooperative_groups;\nusing cp_async::SharedMemFillMode;\nusing mma::MMAMode;\n\nconstexpr uint32_t warp_size = 32;\n\nnamespace {\n\ntemplate <PosEncodingMode pos_encoding_mode, typename DTypeKV, typename DTypeQKAccum>\nconstexpr bool is_invalid_configuration(uint32_t num_frags_x, uint32_t num_frags_y,\n uint32_t num_frags_z, uint32_t num_warps_x,\n uint32_t num_warps_z) {\n return ((num_frags_y < 4) || (num_frags_y == 4 && num_frags_z % 2 == 1) ||\n (num_frags_y > 4 && num_frags_y % (2 * num_warps_x) != 0) ||\n (num_frags_x * (8 * num_frags_y + 2 * sizeof(DTypeQKAccum) * num_frags_z) >= 256) ||\n (sizeof(DTypeKV) == 1 && num_frags_z * 2 % num_warps_x != 0) ||\n (sizeof(DTypeKV) == 1 && pos_encoding_mode == PosEncodingMode::kRoPELlama));\n}\n\ntemplate <uint32_t num_warps_x, uint32_t num_warps_z>\n__device__ __forceinline__ uint32_t get_warp_idx_x() {\n if constexpr (num_warps_x == 1) {\n return 0;\n } else {\n return threadIdx.y;\n }\n}\n\ntemplate <uint32_t num_warps_x, uint32_t num_warps_z>\n__device__ __forceinline__ uint32_t get_warp_idx_z() {\n if constexpr (num_warps_z == 1) {\n return 0;\n } else {\n return threadIdx.z;\n }\n}\n\ntemplate <uint32_t num_warps_x, uint32_t num_warps_z>\n__device__ __forceinline__ uint32_t get_warp_idx() {\n return get_warp_idx_z<num_warps_x, num_warps_z>() * num_warps_x +\n get_warp_idx_x<num_warps_x, num_warps_z>();\n}\n\n/*!\n * \\brief Apply Llama style rotary embedding to two 16x16 fragments.\n * \\tparam T The data type of the input fragments.\n * \\param x_first_half First fragment x[offset:offset+16, j*16:(j+1)*16]\n * \\param x_second_half Second fragment x[offset:offset*16, j*16+d/2:(j+1)*16+d/2]\n * \\param rope_freq Rope frequency\n * \\param offset The offset of the first row in both fragments.\n * \\param scale A scale factor applied to the result (used to multiply sm_scale).\n * \\note The sin/cos computation is slow, especially for A100 GPUs which has low\n * non tensor-ops flops, will optimize in the future.\n */\ntemplate <typename T>\n__device__ __forceinline__ void k_frag_apply_llama_rope(T* x_first_half, T* x_second_half,\n const float* rope_freq,\n const uint32_t kv_offset,\n float scale = 1.f) {\n static_assert(sizeof(T) == 2);\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n float cos, sin, tmp;\n // 0 1 | 2 3\n // ---------\n // 4 5 | 6 7\n uint32_t i = reg_id / 4, j = (reg_id % 4) / 2;\n __sincosf(float(kv_offset + 8 * i) * rope_freq[2 * j + reg_id % 2], &sin, &cos);\n tmp = x_first_half[reg_id];\n x_first_half[reg_id] = (tmp * cos - (float)x_second_half[reg_id] * sin) * scale;\n x_second_half[reg_id] = ((float)x_second_half[reg_id] * cos + tmp * sin) * scale;\n }\n}\n\ntemplate <typename T>\n__device__ __forceinline__ void q_frag_apply_llama_rope(T* x_first_half, T* x_second_half,\n const float* rope_freq,\n const uint32_t qo_packed_offset,\n const uint_fastdiv group_size,\n float scale = 1.f) {\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n float cos, sin, tmp;\n // 0 1 | 4 5\n // ---------\n // 2 3 | 6 7\n uint32_t i = ((reg_id % 4) / 2), j = (reg_id / 4);\n __sincosf(float((qo_packed_offset + 8 * i) / group_size) * rope_freq[2 * j + reg_id % 2], &sin,\n &cos);\n tmp = x_first_half[reg_id];\n x_first_half[reg_id] = (tmp * cos - (float)x_second_half[reg_id] * sin) * scale;\n x_second_half[reg_id] = ((float)x_second_half[reg_id] * cos + tmp * sin) * scale;\n }\n}\n\ntemplate <typename T, typename IdType>\n__device__ __forceinline__ void q_frag_apply_llama_rope_with_pos(\n T* x_first_half, T* x_second_half, const float* rope_freq, const uint32_t qo_packed_offset,\n const uint_fastdiv group_size, const IdType* q_offset, float scale = 1.f) {\n float pos[2] = {static_cast<float>(q_offset[qo_packed_offset / group_size]),\n static_cast<float>(q_offset[(qo_packed_offset + 8) / group_size])};\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n float cos, sin, tmp;\n // 0 1 | 4 5\n // ---------\n // 2 3 | 6 7\n uint32_t i = ((reg_id % 4) / 2), j = (reg_id / 4);\n __sincosf(pos[i] * rope_freq[2 * j + reg_id % 2], &sin, &cos);\n tmp = x_first_half[reg_id];\n x_first_half[reg_id] = (tmp * cos - (float)x_second_half[reg_id] * sin) * scale;\n x_second_half[reg_id] = ((float)x_second_half[reg_id] * cos + tmp * sin) * scale;\n }\n}\n\n/*!\n * \\brief Produce k/v fragments from global memory to shared memory.\n * \\tparam fill_mode The fill mode of the shared memory.\n * \\tparam num_frags_y The number of fragments in y dimension.\n * \\tparam num_frags_z The number of fragments in z dimension.\n * \\tparam num_warps The number of warps in the threadblock.\n * \\tparam T The data type of the input tensor.\n * \\param smem The shared memory to store kv fragments.\n * \\param gptr The global memory pointer.\n * \\param qkv_info The tensor info of the input tensor.\n * \\param kv_idx_base The base kv index.\n * \\param kv_len The length of kv tensor.\n */\ntemplate <SharedMemFillMode fill_mode, uint32_t num_warps_x, uint32_t num_warps_z,\n uint32_t num_frags_y, uint32_t num_frags_z, SwizzleMode swizzle_mode, typename T>\n__device__ __forceinline__ void produce_kv(smem_t<swizzle_mode> smem, uint32_t* smem_offset,\n T** gptr, const uint32_t kv_stride_n,\n const uint32_t kv_idx_base, const uint32_t kv_len) {\n // NOTE(Zihao): for fp8, this function doesn't work for head_dim = 64 at the moment\n constexpr uint32_t head_dim = num_frags_y * 16;\n constexpr uint32_t num_warps = num_warps_x * num_warps_z;\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<T>();\n const uint32_t warp_idx = get_warp_idx<num_warps_x, num_warps_z>(), lane_idx = threadIdx.x;\n\n if constexpr (swizzle_mode == SwizzleMode::k128B) {\n uint32_t kv_idx = kv_idx_base + warp_idx * 4 + lane_idx / 8;\n // NOTE(Zihao): num_frags_z * 4 / num_warps_x = num_warps_z * num_frags_z * 4 / num_warps\n static_assert(num_frags_z * 4 % num_warps_x == 0);\n#pragma unroll\n for (uint32_t i = 0; i < num_frags_z * 4 / num_warps_x; ++i) {\n#pragma unroll\n for (uint32_t j = 0; j < num_frags_y / (8 / sizeof(T)); ++j) {\n smem.load_128b_async<fill_mode>(*smem_offset, *gptr, kv_idx < kv_len);\n *smem_offset = smem.template advance_offset_by_column<8>(*smem_offset, j);\n *gptr += 8 * num_elems_per_128b<T>();\n }\n kv_idx += num_warps * 4;\n *smem_offset =\n smem.template advance_offset_by_row<num_warps * 4, channel_size_128b_kv>(*smem_offset) -\n sizeof(T) * num_frags_y;\n *gptr += num_warps * 4 * kv_stride_n - sizeof(T) * num_frags_y * num_elems_per_128b<T>();\n }\n *smem_offset -= num_warps_z * num_frags_z * 16 * channel_size_128b_kv;\n } else {\n uint32_t kv_idx = kv_idx_base + warp_idx * 8 + lane_idx / 4;\n // NOTE(Zihao): num_frags_z * 2 / num_warps_x = num_warps_z * num_frags_z * 2 / num_warps\n static_assert(num_frags_z * 2 % num_warps_x == 0);\n#pragma unroll\n for (uint32_t i = 0; i < num_frags_z * 2 / num_warps_x; ++i) {\n smem.load_128b_async<fill_mode>(*smem_offset, *gptr, kv_idx < kv_len);\n *smem_offset =\n smem.template advance_offset_by_row<num_warps * 8, channel_size_128b_kv>(*smem_offset);\n kv_idx += num_warps * 8;\n *gptr += num_warps * 8 * kv_stride_n;\n }\n *smem_offset -= num_warps_z * num_frags_z * 16 * channel_size_128b_kv;\n }\n}\n\ntemplate <bool produce_v, uint32_t num_warps_x, uint32_t num_warps_z, uint32_t num_frags_y,\n uint32_t num_frags_z, PageStorage page_storage, SwizzleMode swizzle_mode, typename DType,\n typename IdType>\n__device__ __forceinline__ void page_produce_kv(smem_t<swizzle_mode> smem, uint32_t* smem_offset,\n paged_kv_t<page_storage, DType, IdType>& paged_kv,\n const uint32_t kv_idx_base, const size_t* kv_offset,\n const uint32_t kv_len) {\n // NOTE(Zihao): for fp8, this function doesn't work for head_dim = 64 at the moment\n constexpr SharedMemFillMode fill_mode =\n produce_v ? SharedMemFillMode::kFillZero : SharedMemFillMode::kNoFill;\n constexpr uint32_t head_dim = num_frags_y * 16;\n constexpr uint32_t num_warps = num_warps_x * num_warps_z;\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<DType>();\n const uint32_t warp_idx = get_warp_idx<num_warps_x, num_warps_z>(), lane_idx = threadIdx.x;\n if constexpr (swizzle_mode == SwizzleMode::k128B) {\n uint32_t kv_idx = kv_idx_base + warp_idx * 4 + lane_idx / 8;\n // NOTE(Zihao): num_frags_z * 4 / num_warps_x = num_warps_z * num_frags_z * 4 / num_warps\n static_assert(num_frags_z * 4 % num_warps_x == 0);\n#pragma unroll\n for (uint32_t i = 0; i < num_frags_z * 4 / num_warps_x; ++i) {\n DType* gptr = produce_v ? paged_kv.v_data + kv_offset[i] : paged_kv.k_data + kv_offset[i];\n#pragma unroll\n for (uint32_t j = 0; j < num_frags_y / (8 / sizeof(DType)); ++j) {\n smem.load_128b_async<fill_mode>(*smem_offset, gptr, kv_idx < kv_len);\n *smem_offset = smem.template advance_offset_by_column<8>(*smem_offset, j);\n gptr += 8 * num_elems_per_128b<DType>();\n }\n kv_idx += num_warps * 4;\n *smem_offset =\n smem.template advance_offset_by_row<num_warps * 4, channel_size_128b_kv>(*smem_offset) -\n sizeof(DType) * num_frags_y;\n }\n *smem_offset -= num_warps_z * num_frags_z * 16 * channel_size_128b_kv;\n } else {\n uint32_t kv_idx = kv_idx_base + warp_idx * 8 + lane_idx / 4;\n // NOTE(Zihao): num_frags_z * 2 / num_warps_x = num_warps_z * num_frags_z * 2 / num_warps\n static_assert(num_frags_z * 2 % num_warps_x == 0);\n#pragma unroll\n for (uint32_t i = 0; i < num_frags_z * 2 / num_warps_x; ++i) {\n DType* gptr = produce_v ? paged_kv.v_data + kv_offset[i] : paged_kv.k_data + kv_offset[i];\n smem.load_128b_async<fill_mode>(*smem_offset, gptr, kv_idx < kv_len);\n kv_idx += num_warps * 8;\n *smem_offset =\n smem.template advance_offset_by_row<num_warps * 8, channel_size_128b_kv>(*smem_offset);\n }\n *smem_offset -= num_warps_z * num_frags_z * 16 * channel_size_128b_kv;\n }\n}\n\ntemplate <uint32_t num_frags_y>\n__device__ __forceinline__ void init_rope_freq(float (*rope_freq)[4],\n const float log2_rope_rcp_scale,\n const float log2_rope_rcp_theta) {\n constexpr uint32_t head_dim = num_frags_y * 16;\n const uint32_t lane_idx = threadIdx.x;\n#pragma unroll\n for (uint32_t fy = 0; fy < num_frags_y / 2; ++fy) {\n#pragma unroll\n for (uint32_t j = 0; j < 4; ++j) {\n rope_freq[fy][j] = math::ptx_exp2(\n log2_rope_rcp_scale +\n log2_rope_rcp_theta *\n float(2 * ((fy * 16 + (j / 2) * 8 + (lane_idx % 4) * 2 + (j % 2)) % (head_dim / 2))) /\n float(head_dim));\n }\n }\n}\n\ntemplate <uint32_t num_frags_x, uint32_t num_frags_y, typename DTypeQKAccum>\n__device__ __forceinline__ void init_states(float (*o_frag)[num_frags_y][8], DTypeQKAccum (*m)[2],\n float (*d)[2]) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t fy = 0; fy < num_frags_y; ++fy) {\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n o_frag[fx][fy][reg_id] = 0.f;\n }\n }\n }\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n m[fx][j] = DTypeQKAccum(-5e4);\n d[fx][j] = 1.f;\n }\n }\n}\n\ntemplate <uint32_t num_warps_x, uint32_t num_warps_z, uint32_t num_frags_x, uint32_t num_frags_y,\n SwizzleMode swizzle_mode, typename DTypeQ>\n__device__ __forceinline__ void load_q_global_smem(uint32_t packed_offset,\n const uint32_t qo_upper_bound,\n DTypeQ* q_ptr_base, const uint32_t q_stride_n,\n const uint32_t q_stride_h,\n const uint_fastdiv group_size,\n smem_t<swizzle_mode>* q_smem) {\n constexpr uint32_t head_dim = num_frags_y * 16;\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n const uint32_t lane_idx = threadIdx.x, warp_idx_x = get_warp_idx_x<num_warps_x, num_warps_z>();\n\n if (get_warp_idx_z<num_warps_x, num_warps_z>() == 0) {\n uint32_t q_smem_offset_w = q_smem->get_permuted_offset<channel_size_128b_q>(\n warp_idx_x * num_frags_x * 16 + lane_idx / 8, lane_idx % 8);\n\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t j = 0; j < 4; ++j) {\n uint32_t q, r;\n group_size.divmod(packed_offset + lane_idx / 8 + fx * 16 + j * 4, q, r);\n const uint32_t q_idx = q;\n DTypeQ* q_ptr = q_ptr_base + q * q_stride_n + r * q_stride_h;\n#pragma unroll\n for (uint32_t fyo = 0; fyo < num_frags_y / 4; ++fyo) {\n // load q fragment from gmem to smem\n q_smem->load_128b_async<SharedMemFillMode::kNoFill>(q_smem_offset_w, q_ptr,\n q_idx < qo_upper_bound);\n q_smem_offset_w = q_smem->template advance_offset_by_column<8>(q_smem_offset_w, fyo);\n q_ptr += 8 * num_elems_per_128b<DTypeQ>();\n }\n q_smem_offset_w =\n q_smem->template advance_offset_by_row<4, channel_size_128b_q>(q_smem_offset_w) -\n 2 * num_frags_y;\n }\n }\n }\n}\n\ntemplate <uint32_t num_warps_x, uint32_t num_warps_z, uint32_t num_frags_x, uint32_t num_frags_y,\n SwizzleMode swizzle_mode, typename DTypeQ>\n__device__ __forceinline__ void q_smem_inplace_apply_rotary_multiply_sm_scale(\n const uint32_t q_packed_idx, const uint32_t qo_len, const uint32_t kv_len,\n const uint_fastdiv group_size, smem_t<swizzle_mode>* q_smem, uint32_t* q_smem_offset_r,\n float (*rope_freq)[4], const float sm_scale) {\n if (get_warp_idx_z<num_warps_x, num_warps_z>() == 0) {\n constexpr uint32_t head_dim = num_frags_y * 16;\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n const uint32_t lane_idx = threadIdx.x;\n uint32_t q_frag_local[2][4];\n static_assert(num_frags_y % 4 == 0, \"num_frags_y must be a multiple of 4\");\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n uint32_t q_smem_offset_r_first_half = *q_smem_offset_r;\n#pragma unroll\n for (uint32_t fyi = 0; fyi < num_frags_y / 2; ++fyi) {\n q_smem->ldmatrix_m8n8x4(q_smem_offset_r_first_half, q_frag_local[0]);\n uint32_t q_smem_offset_r_last_half =\n q_smem->template advance_offset_by_column<num_frags_y>(q_smem_offset_r_first_half, 0);\n q_smem->ldmatrix_m8n8x4(q_smem_offset_r_last_half, q_frag_local[1]);\n q_frag_apply_llama_rope<DTypeQ>(\n (DTypeQ*)q_frag_local[0], (DTypeQ*)q_frag_local[1], rope_freq[fyi],\n q_packed_idx + kv_len * group_size - qo_len * group_size + fx * 16 + lane_idx / 4,\n group_size, sm_scale);\n q_smem->stmatrix_m8n8x4(q_smem_offset_r_last_half, q_frag_local[1]);\n q_smem->stmatrix_m8n8x4(q_smem_offset_r_first_half, q_frag_local[0]);\n q_smem_offset_r_first_half =\n q_smem->template advance_offset_by_column<2>(q_smem_offset_r_first_half, fyi);\n }\n *q_smem_offset_r += 16 * channel_size_128b_q;\n }\n *q_smem_offset_r -= num_frags_x * 16 * channel_size_128b_q;\n }\n}\n\ntemplate <uint32_t num_warps_x, uint32_t num_warps_z, uint32_t num_frags_x, uint32_t num_frags_y,\n SwizzleMode swizzle_mode, typename DTypeQ, typename IdType>\n__device__ __forceinline__ void q_smem_inplace_apply_rotary_with_pos_multiply_sm_scale(\n const uint32_t q_packed_idx_base, const IdType* q_offset, smem_t<swizzle_mode>* q_smem,\n const uint_fastdiv group_size, uint32_t* q_smem_offset_r, float (*rope_freq)[4],\n const float sm_scale) {\n if (get_warp_idx_z<num_warps_x, num_warps_z>() == 0) {\n constexpr uint32_t head_dim = num_frags_y * 16;\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n const uint32_t lane_idx = threadIdx.x;\n uint32_t q_frag_local[2][4];\n static_assert(num_frags_y % 4 == 0, \"num_frags_y must be a multiple of 4\");\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n uint32_t q_smem_offset_r_first_half = *q_smem_offset_r;\n#pragma unroll\n for (uint32_t fyi = 0; fyi < num_frags_y / 2; ++fyi) {\n q_smem->ldmatrix_m8n8x4(q_smem_offset_r_first_half, q_frag_local[0]);\n uint32_t q_smem_offset_r_last_half =\n q_smem->template advance_offset_by_column<num_frags_y>(q_smem_offset_r_first_half, 0);\n q_smem->ldmatrix_m8n8x4(q_smem_offset_r_last_half, q_frag_local[1]);\n q_frag_apply_llama_rope_with_pos<DTypeQ>(\n (DTypeQ*)q_frag_local[0], (DTypeQ*)q_frag_local[1], rope_freq[fyi],\n q_packed_idx_base + fx * 16 + lane_idx / 4, group_size, q_offset, sm_scale);\n q_smem->stmatrix_m8n8x4(q_smem_offset_r_last_half, q_frag_local[1]);\n q_smem->stmatrix_m8n8x4(q_smem_offset_r_first_half, q_frag_local[0]);\n q_smem_offset_r_first_half =\n q_smem->template advance_offset_by_column<2>(q_smem_offset_r_first_half, fyi);\n }\n *q_smem_offset_r += 16 * channel_size_128b_q;\n }\n *q_smem_offset_r -= num_frags_x * 16 * channel_size_128b_q;\n }\n}\n\ntemplate <uint32_t num_warps_x, uint32_t num_warps_z, uint32_t num_frags_x, uint32_t num_frags_y,\n SwizzleMode swizzle_mode, typename DTypeQ>\n__device__ __forceinline__ void q_smem_inplace_multiply_sm_scale(smem_t<swizzle_mode>* q_smem,\n const float sm_scale) {\n const uint32_t warp_idx = get_warp_idx<num_warps_x, num_warps_z>(), lane_idx = threadIdx.x;\n constexpr uint32_t head_dim = num_frags_y * 16;\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n constexpr uint32_t num_warps = num_warps_x * num_warps_z;\n#pragma unroll\n for (uint32_t i = 0; i < num_frags_x * head_dim / (num_warps_z * 16); ++i) {\n vec_t<DTypeQ, 8> tmp;\n tmp.load((DTypeQ*)(q_smem->base) + (i * num_warps + warp_idx) * 256 + lane_idx * 8);\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n tmp[reg_id] *= sm_scale;\n }\n tmp.store((DTypeQ*)(q_smem->base) + (i * num_warps + warp_idx) * 256 + lane_idx * 8);\n }\n}\n\ntemplate <uint32_t num_warps_x, uint32_t num_warps_z, uint32_t num_frags_y, uint32_t num_frags_z,\n SwizzleMode swizzle_mode, typename DTypeKV>\n__device__ __forceinline__ void k_smem_inplace_apply_rotary(const uint32_t kv_idx_base,\n smem_t<swizzle_mode>* k_smem,\n uint32_t* k_smem_offset_r,\n float (*rope_freq)[4]) {\n static_assert(sizeof(DTypeKV) == 2);\n constexpr uint32_t head_dim = num_frags_y * 16;\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<DTypeKV>();\n uint32_t k_frag_local[2][4];\n const uint32_t lane_idx = threadIdx.x;\n if constexpr (num_frags_y == 4 && num_warps_x == 4) {\n static_assert(num_warps_z == 1);\n const uint32_t warp_idx = get_warp_idx_x<num_warps_x, num_warps_z>();\n // horizontal-axis: y\n // horizontal-axis: y\n // vertical-axis: z\n // | 1-16 | 16-32 | 32-48 | 48-64 |\n // | 1-16 | warp_idx=0 | warp_idx=1 | warp_idx=0 | warp_idx=1 |\n // | 16-32 | warp_idx=2 | warp_idx=3 | warp_idx=2 | warp_idx=3 |\n static_assert(num_frags_z % 2 == 0,\n \"when num_frags_y == 4, num_frags_z must be a multiple of 2\");\n uint32_t kv_idx = kv_idx_base + (warp_idx / 2) * 16 + lane_idx / 4;\n *k_smem_offset_r =\n (*k_smem_offset_r ^ (0x2 * (warp_idx % 2))) + (warp_idx / 2) * 16 * channel_size_128b_kv;\n#pragma unroll\n for (uint32_t i = 0; i < num_frags_z / 2; ++i) {\n // uint32_t fz = warp_idx / 2 + i * 2;\n uint32_t k_smem_offset_r_first_half = *k_smem_offset_r;\n uint32_t fyi = (warp_idx % 2);\n k_smem->ldmatrix_m8n8x4(k_smem_offset_r_first_half, k_frag_local[0]);\n uint32_t k_smem_offset_r_last_half =\n k_smem->template advance_offset_by_column<4>(k_smem_offset_r_first_half, 0);\n k_smem->ldmatrix_m8n8x4(k_smem_offset_r_last_half, k_frag_local[1]);\n k_frag_apply_llama_rope<DTypeKV>((DTypeKV*)k_frag_local[0], (DTypeKV*)k_frag_local[1],\n rope_freq[fyi], kv_idx);\n k_smem->stmatrix_m8n8x4(k_smem_offset_r_last_half, k_frag_local[1]);\n k_smem->stmatrix_m8n8x4(k_smem_offset_r_first_half, k_frag_local[0]);\n *k_smem_offset_r += 32 * channel_size_128b_kv;\n kv_idx += 32;\n }\n *k_smem_offset_r = (*k_smem_offset_r ^ (0x2 * (warp_idx % 2))) -\n ((warp_idx / 2) + num_frags_z) * 16 * channel_size_128b_kv;\n } else {\n const uint32_t warp_idx_x = get_warp_idx_x<num_warps_x, num_warps_z>(),\n warp_idx_z = get_warp_idx_z<num_warps_x, num_warps_z>();\n static_assert(num_frags_y % (2 * num_warps_x) == 0);\n // horizontal axis: y\n // vertical axis: z\n // | (warp_idx_z, warp_idx_x) | 1-16 | 16-32 | 32-48 | 48-64 | ...\n // | 1-16*num_frags_z | (0, 0) | (0, 1) | (0, 2) | (0, 3) | ...\n // | 16*num_frags_z-32*num_frags_z | (1, 0) | (1, 1) | (1, 2) | (1, 3) | ...\n // ...\n uint32_t kv_idx = kv_idx_base + (warp_idx_z * num_frags_z * 16) + lane_idx / 4;\n *k_smem_offset_r = *k_smem_offset_r ^ (0x2 * warp_idx_x);\n#pragma unroll\n for (uint32_t i = 0; i < num_frags_z; ++i) {\n uint32_t k_smem_offset_r_first_half = *k_smem_offset_r;\n#pragma unroll\n for (uint32_t j = 0; j < num_frags_y / (2 * num_warps_x); ++j) {\n uint32_t fyi = warp_idx_x + j * num_warps_x;\n k_smem->ldmatrix_m8n8x4(k_smem_offset_r_first_half, k_frag_local[0]);\n uint32_t k_smem_offset_r_last_half =\n k_smem->template advance_offset_by_column<num_frags_y>(k_smem_offset_r_first_half, 0);\n k_smem->ldmatrix_m8n8x4(k_smem_offset_r_last_half, k_frag_local[1]);\n k_frag_apply_llama_rope<DTypeKV>((DTypeKV*)k_frag_local[0], (DTypeKV*)k_frag_local[1],\n rope_freq[fyi], kv_idx);\n k_smem->stmatrix_m8n8x4(k_smem_offset_r_last_half, k_frag_local[1]);\n k_smem->stmatrix_m8n8x4(k_smem_offset_r_first_half, k_frag_local[0]);\n k_smem_offset_r_first_half = k_smem->template advance_offset_by_column<2 * num_warps_x>(\n k_smem_offset_r_first_half, fyi);\n }\n *k_smem_offset_r += 16 * channel_size_128b_kv;\n kv_idx += 16;\n }\n *k_smem_offset_r =\n (*k_smem_offset_r ^ (0x2 * warp_idx_x)) - num_frags_z * 16 * channel_size_128b_kv;\n }\n}\n\ntemplate <LogitsPostHook logits_post_hook, uint32_t num_frags_x, uint32_t num_frags_y,\n uint32_t num_frags_z, SwizzleMode swizzle_mode_q, SwizzleMode swizzle_mode_kv,\n typename DTypeQ, typename DTypeKV, typename DTypeQKAccum>\n__device__ __forceinline__ void compute_qk(\n smem_t<swizzle_mode_q>* q_smem, uint32_t* q_smem_offset_r, smem_t<swizzle_mode_kv>* k_smem,\n uint32_t* k_smem_offset_r, DTypeQKAccum (*s_frag)[num_frags_z][8], const float soft_cap) {\n constexpr uint32_t head_dim = num_frags_y * 16;\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<DTypeKV>();\n uint32_t a_frag[num_frags_x][4], b_frag[4];\n // compute q*k^T\n#pragma unroll\n for (uint32_t fy = 0; fy < num_frags_y; ++fy) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n q_smem->ldmatrix_m8n8x4(*q_smem_offset_r, a_frag[fx]);\n *q_smem_offset_r =\n q_smem->template advance_offset_by_row<16, channel_size_128b_q>(*q_smem_offset_r);\n }\n\n *q_smem_offset_r = q_smem->template advance_offset_by_column<2>(*q_smem_offset_r, fy) -\n num_frags_x * 16 * channel_size_128b_q;\n\n#pragma unroll\n for (uint32_t fz = 0; fz < num_frags_z; ++fz) {\n if constexpr (sizeof(DTypeKV) == 1) {\n uint32_t b_frag_f8[2];\n if (fy % 2 == 0) {\n k_smem->ldmatrix_m8n8x4_left_half(*k_smem_offset_r, b_frag_f8);\n } else {\n k_smem->ldmatrix_m8n8x4_right_half(*k_smem_offset_r, b_frag_f8);\n }\n b_frag_f8[0] = frag_layout_swizzle_16b_to_8b(b_frag_f8[0]);\n b_frag_f8[1] = frag_layout_swizzle_16b_to_8b(b_frag_f8[1]);\n vec_cast<DTypeQ, DTypeKV>::cast<8>((DTypeQ*)b_frag, (DTypeKV*)b_frag_f8);\n } else {\n k_smem->ldmatrix_m8n8x4(*k_smem_offset_r, b_frag);\n }\n *k_smem_offset_r =\n k_smem->template advance_offset_by_row<16, channel_size_128b_kv>(*k_smem_offset_r);\n\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n if constexpr (std::is_same<DTypeQKAccum, float>::value) {\n if (fy == 0) {\n mma::mma_sync_m16n16k16_row_col_f16f16f32<DTypeQ, MMAMode::kInit>(s_frag[fx][fz],\n a_frag[fx], b_frag);\n } else {\n mma::mma_sync_m16n16k16_row_col_f16f16f32<DTypeQ>(s_frag[fx][fz], a_frag[fx], b_frag);\n }\n } else if (std::is_same<DTypeQKAccum, half>::value) {\n if (fy == 0) {\n mma::mma_sync_m16n16k16_row_col_f16f16f16<MMAMode::kInit>((uint32_t*)s_frag[fx][fz],\n a_frag[fx], b_frag);\n } else {\n mma::mma_sync_m16n16k16_row_col_f16f16f16((uint32_t*)s_frag[fx][fz], a_frag[fx],\n b_frag);\n }\n }\n }\n }\n if constexpr (sizeof(DTypeKV) == 1) {\n if (fy % 2 == 1) {\n *k_smem_offset_r = k_smem->template advance_offset_by_column<2>(*k_smem_offset_r, fy / 2);\n }\n *k_smem_offset_r -= num_frags_z * 16 * channel_size_128b_kv;\n } else {\n *k_smem_offset_r = k_smem->template advance_offset_by_column<2>(*k_smem_offset_r, fy) -\n num_frags_z * 16 * channel_size_128b_kv;\n }\n }\n *q_smem_offset_r -= num_frags_y * 2;\n *k_smem_offset_r -= num_frags_y * sizeof(DTypeKV);\n\n if constexpr (std::is_same<DTypeQKAccum, float>::value) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t fz = 0; fz < num_frags_z; ++fz) {\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n s_frag[fx][fz][reg_id] =\n apply_logits_post_hook<logits_post_hook>(s_frag[fx][fz][reg_id], soft_cap);\n }\n }\n }\n } else {\n static_assert(std::is_same<DTypeQKAccum, half>::value);\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t fz = 0; fz < num_frags_z; ++fz) {\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 4; ++reg_id) {\n *(half2*)(&s_frag[fx][fz][reg_id * 2]) = apply_logits_post_hook<logits_post_hook>(\n *(half2*)(&s_frag[fx][fz][reg_id * 2]), soft_cap);\n }\n }\n }\n }\n}\n\ntemplate <uint32_t num_frags_x, uint32_t num_frags_z, typename T>\n__device__ __forceinline__ void apply_alibi_bias(const uint32_t qo_packed_idx_base,\n const uint32_t kv_idx_base, const int32_t q_offset,\n const uint_fastdiv group_size,\n float (*alibi_slope)[2],\n T (*s_frag)[num_frags_z][8]) {\n const int32_t lane_idx = threadIdx.x;\n#pragma unroll\n for (int32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (int32_t fz = 0; fz < num_frags_z; ++fz) {\n#pragma unroll\n for (int32_t reg_id = 0; reg_id < 8; ++reg_id) {\n const int32_t q_idx =\n (qo_packed_idx_base + fx * 16 + lane_idx / 4 + 8 * ((reg_id % 4) / 2)) /\n group_size,\n kv_idx = kv_idx_base + fz * 16 + 2 * (lane_idx % 4) + 8 * (reg_id / 4) +\n reg_id % 2;\n s_frag[fx][fz][reg_id] +=\n T(alibi_slope[fx][(reg_id % 4) / 2]) * T(kv_idx - q_idx - q_offset);\n }\n }\n }\n}\n\ntemplate <MaskMode mask_mode, uint32_t num_frags_x, uint32_t num_frags_y, uint32_t num_frags_z,\n typename DTypeQKAccum>\n__device__ __forceinline__ void mask_s(const uint32_t qo_packed_idx_base,\n const uint32_t kv_idx_base, const uint32_t qo_len,\n const uint32_t kv_len, const uint32_t window_left,\n const uint32_t chunk_end, const uint_fastdiv group_size,\n uint8_t* custom_mask,\n DTypeQKAccum (*s_frag)[num_frags_z][8]) {\n const uint32_t lane_idx = threadIdx.x;\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t fz = 0; fz < num_frags_z; ++fz) {\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n const uint32_t q_idx =\n (qo_packed_idx_base + fx * 16 + lane_idx / 4 + 8 * ((reg_id % 4) / 2)) /\n group_size,\n kv_idx = kv_idx_base + fz * 16 + 2 * (lane_idx % 4) + 8 * (reg_id / 4) +\n reg_id % 2;\n const bool out_of_boundary =\n (mask_mode == MaskMode::kCausal\n ? (kv_idx + qo_len > kv_len + q_idx || (kv_idx >= chunk_end) ||\n kv_idx + qo_len + window_left < kv_len + q_idx)\n : kv_idx >= chunk_end || kv_idx + qo_len + window_left < kv_len + q_idx);\n s_frag[fx][fz][reg_id] =\n (out_of_boundary ||\n (mask_mode == MaskMode::kCustom && q_idx < qo_len &&\n !((custom_mask[(q_idx * kv_len + kv_idx) / 8] >> ((q_idx * kv_len + kv_idx) % 8)) &\n 1)))\n ? DTypeQKAccum(-5e4)\n : s_frag[fx][fz][reg_id];\n }\n }\n }\n}\n\ntemplate <uint32_t num_frags_x, uint32_t num_frags_y, uint32_t num_frags_z, typename DTypeQKAccum>\n__device__ __forceinline__ void update_mdo_states(DTypeQKAccum (*s_frag)[num_frags_z][8],\n float (*o_frag)[num_frags_y][8],\n DTypeQKAccum (*m)[2], float (*d)[2]) {\n if constexpr (std::is_same<DTypeQKAccum, float>::value) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n float m_prev = m[fx][j];\n#pragma unroll\n for (uint32_t fz = 0; fz < num_frags_z; ++fz) {\n float m_local = max(max(s_frag[fx][fz][j * 2 + 0], s_frag[fx][fz][j * 2 + 1]),\n max(s_frag[fx][fz][j * 2 + 4], s_frag[fx][fz][j * 2 + 5]));\n m[fx][j] = max(m[fx][j], m_local);\n }\n m[fx][j] = max(m[fx][j], math::shfl_xor_sync(m[fx][j], 0x2));\n m[fx][j] = max(m[fx][j], math::shfl_xor_sync(m[fx][j], 0x1));\n\n float o_scale = math::ptx_exp2(m_prev - m[fx][j]);\n d[fx][j] *= o_scale;\n#pragma unroll\n for (uint32_t fy = 0; fy < num_frags_y; ++fy) {\n o_frag[fx][fy][j * 2 + 0] *= o_scale;\n o_frag[fx][fy][j * 2 + 1] *= o_scale;\n o_frag[fx][fy][j * 2 + 4] *= o_scale;\n o_frag[fx][fy][j * 2 + 5] *= o_scale;\n }\n#pragma unroll\n for (uint32_t fz = 0; fz < num_frags_z; ++fz) {\n s_frag[fx][fz][j * 2 + 0] = math::ptx_exp2(s_frag[fx][fz][j * 2 + 0] - m[fx][j]);\n s_frag[fx][fz][j * 2 + 1] = math::ptx_exp2(s_frag[fx][fz][j * 2 + 1] - m[fx][j]);\n s_frag[fx][fz][j * 2 + 4] = math::ptx_exp2(s_frag[fx][fz][j * 2 + 4] - m[fx][j]);\n s_frag[fx][fz][j * 2 + 5] = math::ptx_exp2(s_frag[fx][fz][j * 2 + 5] - m[fx][j]);\n }\n }\n }\n } else if constexpr (std::is_same<DTypeQKAccum, half>::value) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n half m_prev[2];\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n m_prev[j] = m[fx][j];\n#pragma unroll\n for (uint32_t fz = 0; fz < num_frags_z; ++fz) {\n half2 m_local =\n __hmax2(*(half2*)&s_frag[fx][fz][j * 2], *(half2*)&s_frag[fx][fz][j * 2 + 4]);\n m[fx][j] = __hmax(m[fx][j], __hmax(m_local.x, m_local.y));\n }\n }\n *(half2*)&m[fx] = __hmax2(*(half2*)&m[fx], math::shfl_xor_sync(*(half2*)&m[fx], 0x2));\n *(half2*)&m[fx] = __hmax2(*(half2*)&m[fx], math::shfl_xor_sync(*(half2*)&m[fx], 0x1));\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n float o_scale = math::ptx_exp2(float(m_prev[j] - m[fx][j]));\n d[fx][j] *= o_scale;\n#pragma unroll\n for (uint32_t fy = 0; fy < num_frags_y; ++fy) {\n o_frag[fx][fy][j * 2 + 0] *= o_scale;\n o_frag[fx][fy][j * 2 + 1] *= o_scale;\n o_frag[fx][fy][j * 2 + 4] *= o_scale;\n o_frag[fx][fy][j * 2 + 5] *= o_scale;\n }\n half2 m2 = make_half2(m[fx][j], m[fx][j]);\n#pragma unroll\n for (uint32_t fz = 0; fz < num_frags_z; ++fz) {\n *(half2*)&s_frag[fx][fz][j * 2] = math::ptx_exp2(*(half2*)&s_frag[fx][fz][j * 2] - m2);\n *(half2*)&s_frag[fx][fz][j * 2 + 4] =\n math::ptx_exp2(*(half2*)&s_frag[fx][fz][j * 2 + 4] - m2);\n }\n }\n }\n }\n}\n\ntemplate <uint32_t num_frags_x, uint32_t num_frags_y, uint32_t num_frags_z,\n SwizzleMode swizzle_mode, typename DTypeQ, typename DTypeKV, typename DTypeQKAccum>\n__device__ __forceinline__ void compute_sfm_v(smem_t<swizzle_mode>* v_smem,\n uint32_t* v_smem_offset_r,\n DTypeQKAccum (*s_frag)[num_frags_z][8],\n float (*o_frag)[num_frags_y][8], float (*d)[2]) {\n constexpr uint32_t head_dim = num_frags_y * 16;\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<DTypeKV>();\n\n DTypeQ s_frag_f16[num_frags_x][num_frags_z][8];\n if constexpr (std::is_same<DTypeQKAccum, float>::value) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t fz = 0; fz < num_frags_z; ++fz) {\n vec_cast<DTypeQ, float>::cast<8>(s_frag_f16[fx][fz], s_frag[fx][fz]);\n }\n }\n }\n\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t fz = 0; fz < num_frags_z; ++fz) {\n if constexpr (std::is_same<DTypeQKAccum, float>::value) {\n mma::rowsum_f16f16f32(d[fx], s_frag_f16[fx][fz]);\n } else {\n mma::rowsum_f16f16f32(d[fx], s_frag[fx][fz]);\n }\n }\n }\n\n#pragma unroll\n for (uint32_t fz = 0; fz < num_frags_z; ++fz) {\n#pragma unroll\n for (uint32_t fy = 0; fy < num_frags_y; ++fy) {\n uint32_t b_frag[4];\n if constexpr (sizeof(DTypeKV) == 1) {\n uint32_t b_frag_f8[2];\n if (fy % 2 == 0) {\n v_smem->ldmatrix_m8n8x4_trans_left_half(*v_smem_offset_r, b_frag_f8);\n } else {\n v_smem->ldmatrix_m8n8x4_trans_right_half(*v_smem_offset_r, b_frag_f8);\n }\n b_frag_f8[0] = frag_layout_swizzle_16b_to_8b_trans(b_frag_f8[0]);\n b_frag_f8[1] = frag_layout_swizzle_16b_to_8b_trans(b_frag_f8[1]);\n bfly_exch(b_frag_f8[0], b_frag_f8[1]);\n vec_cast<DTypeQ, DTypeKV>::cast<8>((DTypeQ*)b_frag, (DTypeKV*)b_frag_f8);\n } else {\n v_smem->ldmatrix_m8n8x4_trans(*v_smem_offset_r, b_frag);\n }\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n if constexpr (std::is_same<DTypeQKAccum, float>::value) {\n mma::mma_sync_m16n16k16_row_col_f16f16f32<DTypeQ>(\n o_frag[fx][fy], (uint32_t*)(s_frag_f16[fx][fz]), b_frag);\n } else {\n mma::mma_sync_m16n16k16_row_col_f16f16f32<DTypeQ>(o_frag[fx][fy],\n (uint32_t*)s_frag[fx][fz], b_frag);\n }\n }\n if constexpr (sizeof(DTypeKV) == 1) {\n if (fy % 2 == 1) {\n *v_smem_offset_r = v_smem->template advance_offset_by_column<2>(*v_smem_offset_r, fy / 2);\n }\n } else {\n *v_smem_offset_r = v_smem->template advance_offset_by_column<2>(*v_smem_offset_r, fy);\n }\n }\n *v_smem_offset_r =\n v_smem->template advance_offset_by_row<16, channel_size_128b_kv>(*v_smem_offset_r) -\n sizeof(DTypeKV) * num_frags_y;\n }\n *v_smem_offset_r -= 16 * num_frags_z * channel_size_128b_kv;\n}\n\ntemplate <uint32_t num_frags_x, uint32_t num_frags_y, typename DTypeQKAccum>\n__device__ __forceinline__ void normalize_d(float (*o_frag)[num_frags_y][8], DTypeQKAccum (*m)[2],\n float (*d)[2]) {\n float d_rcp[num_frags_x][2];\n // compute reciprocal of d\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n d_rcp[fx][j] = (m[fx][j] != DTypeQKAccum(-5e4)) ? math::ptx_rcp(d[fx][j]) : 0.f;\n }\n }\n\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t fy = 0; fy < num_frags_y; ++fy) {\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n o_frag[fx][fy][reg_id] = o_frag[fx][fy][reg_id] * d_rcp[fx][(reg_id % 4) / 2];\n }\n }\n }\n}\n\n/*!\n * \\brief Synchronize the states of the MDO kernel across the threadblock along threadIdx.z.\n */\ntemplate <uint32_t num_warps_x, uint32_t num_warps_z, uint32_t num_frags_x, uint32_t num_frags_y,\n typename DTypeQKAccum>\n__device__ __forceinline__ void threadblock_sync_mdo_states(float (*o_frag)[num_frags_y][8],\n float* smem_workspace,\n DTypeQKAccum (*m)[2], float (*d)[2],\n const uint32_t warp_idx,\n const uint32_t lane_idx) {\n // only necessary when blockDim.z > 1\n if constexpr (num_warps_z > 1) {\n float2* smem_md = (float2*)(smem_workspace + num_frags_x * num_frags_y * num_warps_x *\n num_warps_z * warp_size * 8);\n // o: [num_warps, num_frags_x, num_frags_y, warp_size(32), 8]\n // md: [num_warps, num_frags_x, 2, warp_size(32), 2 (m/d)]\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t fy = 0; fy < num_frags_y; ++fy) {\n vec_t<float, 8>::memcpy(\n smem_workspace +\n (((warp_idx * num_frags_x + fx) * num_frags_y + fy) * warp_size + lane_idx) * 8,\n o_frag[fx][fy]);\n }\n }\n\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n smem_md[((warp_idx * num_frags_x + fx) * 2 + j) * warp_size + lane_idx] =\n make_float2(float(m[fx][j]), d[fx][j]);\n }\n }\n\n // synchronize m,d first\n __syncthreads();\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n float o_scale[2][num_warps_z];\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n float m_new = -5e4, d_new = 1.f;\n#pragma unroll\n for (uint32_t i = 0; i < num_warps_z; ++i) {\n float2 md = smem_md[(((i * num_warps_x + get_warp_idx_x<num_warps_x, num_warps_z>()) *\n num_frags_x +\n fx) *\n 2 +\n j) *\n warp_size +\n lane_idx];\n float m_prev = m_new, d_prev = d_new;\n m_new = max(m_new, md.x);\n d_new = d_prev * math::ptx_exp2(m_prev - m_new) + md.y * math::ptx_exp2(md.x - m_new);\n }\n\n#pragma unroll\n for (uint32_t i = 0; i < num_warps_z; ++i) {\n float2 md = smem_md[(((i * num_warps_x + get_warp_idx_x<num_warps_x, num_warps_z>()) *\n num_frags_x +\n fx) *\n 2 +\n j) *\n warp_size +\n lane_idx];\n float mi = md.x;\n o_scale[j][i] = math::ptx_exp2(float(mi - m_new));\n }\n m[fx][j] = DTypeQKAccum(m_new);\n d[fx][j] = d_new;\n }\n\n#pragma unroll\n for (uint32_t fy = 0; fy < num_frags_y; ++fy) {\n vec_t<float, 8> o_new;\n o_new.fill(0.f);\n#pragma unroll\n for (uint32_t i = 0; i < num_warps_z; ++i) {\n vec_t<float, 8> oi;\n oi.load(smem_workspace +\n ((((i * num_warps_x + get_warp_idx_x<num_warps_x, num_warps_z>()) * num_frags_x +\n fx) *\n num_frags_y +\n fy) *\n warp_size +\n lane_idx) *\n 8);\n#pragma unroll\n for (uint32_t reg_id = 0; reg_id < 8; ++reg_id) {\n o_new[reg_id] += oi[reg_id] * o_scale[(reg_id % 4) / 2][i];\n }\n }\n o_new.store(o_frag[fx][fy]);\n }\n }\n }\n}\n\ntemplate <uint32_t num_warps_x, uint32_t num_warps_z, uint32_t num_frags_x, uint32_t num_frags_y,\n SwizzleMode swizzle_mode, typename DTypeOut>\n__device__ __forceinline__ void write_o_reg_gmem(\n float (*o_frag)[num_frags_y][8], smem_t<swizzle_mode>* o_smem, DTypeOut* o_ptr_base,\n const uint32_t o_packed_idx_base, const uint32_t qo_upper_bound, const uint32_t o_stride_n,\n const uint32_t o_stride_h, const uint_fastdiv group_size) {\n constexpr uint32_t head_dim = num_frags_y * 16;\n constexpr uint32_t channel_size_128b_out = head_dim / num_elems_per_128b<DTypeOut>();\n const uint32_t warp_idx_x = get_warp_idx_x<num_warps_x, num_warps_z>();\n const uint32_t lane_idx = threadIdx.x;\n\n if (get_warp_idx_z<num_warps_x, num_warps_z>() == 0) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t fy = 0; fy < num_frags_y; ++fy) {\n uint32_t o_frag_f16[4];\n vec_cast<DTypeOut, float>::cast<8>((DTypeOut*)o_frag_f16, o_frag[fx][fy]);\n#ifdef FLASHINFER_STMATRIX_M8N8X4_ENABLED\n uint32_t o_smem_offset_w = o_smem->get_permuted_offset<channel_size_128b_out>(\n (warp_idx_x * num_frags_x + fx) * 16 + lane_idx % 16, fy * 2 + lane_idx / 16);\n o_smem->stmatrix_m8n8x4(o_smem_offset_w, o_frag_f16);\n#else\n uint32_t o_smem_offset_w = o_smem->get_permuted_offset<channel_size_128b_out>(\n (warp_idx_x * num_frags_x + fx) * 16 + lane_idx / 4, fy * 2);\n ((uint32_t*)(o_smem->base + o_smem_offset_w))[lane_idx % 4] = o_frag_f16[0];\n ((uint32_t*)(o_smem->base + o_smem_offset_w + 8 * channel_size_128b_out))[lane_idx % 4] =\n o_frag_f16[1];\n ((uint32_t*)(o_smem->base + (o_smem_offset_w ^ 0x1)))[lane_idx % 4] = o_frag_f16[2];\n ((uint32_t*)(o_smem->base + (o_smem_offset_w ^ 0x1) +\n 8 * channel_size_128b_out))[lane_idx % 4] = o_frag_f16[3];\n#endif\n }\n }\n\n uint32_t o_smem_offset_w = o_smem->get_permuted_offset<channel_size_128b_out>(\n warp_idx_x * num_frags_x * 16 + lane_idx / 8, lane_idx % 8);\n\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t j = 0; j < 4; ++j) {\n uint32_t q, r;\n group_size.divmod(o_packed_idx_base + lane_idx / 8 + fx * 16 + j * 4, q, r);\n const uint32_t o_idx = q;\n DTypeOut* o_ptr = o_ptr_base + q * o_stride_n + r * o_stride_h;\n#pragma unroll\n for (uint32_t fyo = 0; fyo < num_frags_y / 4; ++fyo) {\n if (o_idx < qo_upper_bound) {\n o_smem->store_128b(o_smem_offset_w, o_ptr);\n }\n o_ptr += 8 * num_elems_per_128b<DTypeOut>();\n o_smem_offset_w = o_smem->template advance_offset_by_column<8>(o_smem_offset_w, fyo);\n }\n o_smem_offset_w =\n o_smem->template advance_offset_by_row<4, channel_size_128b_out>(o_smem_offset_w) -\n 2 * num_frags_y;\n }\n }\n }\n}\n\n} // namespace\n\n/*!\n * \\brief FlashAttention prefill CUDA kernel for a single request.\n * \\tparam partition_kv Whether to split kv_len into chunks.\n * \\tparam mask_mode The mask mode used in the attention operation.\n * \\tparam pos_encoding_mode The positional encoding mode.\n * \\tparam num_frags_x The number of fragments in x dimension.\n * \\tparam num_frags_y The number of fragments in y dimension.\n * \\tparam num_frags_z The number of fragments in z dimension.\n * \\tparam num_warps The number of warps in the threadblock.\n * \\tparam DTypeQ The data type of the query tensor.\n * \\tparam DTypeKV The data type of the key/value tensor.\n * \\tparam DTypeOut The data type of the output tensor.\n * \\param q The query tensor.\n * \\param k The key tensor.\n * \\param v The value tensor.\n * \\param o The output tensor.\n * \\param tmp The temporary buffer (used when partition_kv is true).\n * \\param lse The logsumexp value.\n * \\param qkv_info The tensor info of the input tensor.\n * \\param sm_scale The scale factor applied to the softmax score.\n * \\param log2_rope_rcp_scale log2(1/(rope_scale)), where rope_scale is the scaling\n * factor used in RoPE interpolation.\n * \\param log2_rope_rcp_theta log2(1/(rope_theta)), where rope_theta is the theta\n * used in RoPE.\n */\ntemplate <LogitsPostHook logits_post_hook, MaskMode mask_mode, PosEncodingMode pos_encoding_mode,\n uint32_t num_frags_x, uint32_t num_frags_y, uint32_t num_frags_z, uint32_t num_warps_x,\n uint32_t num_warps_z, typename DTypeQ, typename DTypeKV, typename DTypeQKAccum,\n typename DTypeOut>\n__global__\n__launch_bounds__(num_warps_x* num_warps_z* warp_size) void SinglePrefillWithKVCacheKernel(\n DTypeQ* __restrict__ q, DTypeKV* __restrict__ k, DTypeKV* __restrict__ v,\n uint8_t* __restrict__ custom_mask, DTypeOut* __restrict__ o, float* __restrict__ lse,\n const uint32_t qo_len, const uint32_t kv_len, const bool partition_kv,\n const uint_fastdiv group_size, const uint32_t q_stride_n, const uint32_t q_stride_h,\n const uint32_t kv_stride_n, const uint32_t kv_stride_h, const int32_t maybe_window_left,\n const float logits_soft_cap, float sm_scale, const float log2_rope_rcp_scale,\n const float log2_rope_rcp_theta) {\n static_assert(sizeof(DTypeQ) == 2);\n static_assert(sizeof(DTypeOut) == 2);\n sm_scale *=\n (logits_post_hook == LogitsPostHook::kNone ? math::log2e : math::ptx_rcp(logits_soft_cap));\n const uint32_t lane_idx = threadIdx.x, warp_idx = get_warp_idx<num_warps_x, num_warps_z>();\n const uint32_t bx = blockIdx.x, chunk_idx = blockIdx.y, kv_head_idx = blockIdx.z;\n const uint32_t num_kv_heads = gridDim.z, num_qo_heads = num_kv_heads * group_size;\n constexpr uint32_t num_rows_per_cta = num_frags_x * num_warps_x * 16;\n const tensor_info_t qkv_info(qo_len, kv_len, num_qo_heads, num_kv_heads, q_stride_n, q_stride_h,\n kv_stride_n, kv_stride_h, /*head_dim=*/num_frags_y * 16);\n float alibi_slopes[num_frags_x][2];\n\n const uint32_t num_chunks = gridDim.y;\n const uint32_t max_chunk_size = partition_kv ? ceil_div(kv_len, num_chunks) : kv_len;\n const uint32_t chunk_start = partition_kv ? chunk_idx * max_chunk_size : 0;\n const uint32_t chunk_end = partition_kv ? min((chunk_idx + 1) * max_chunk_size, kv_len) : kv_len;\n const uint32_t chunk_size = chunk_end - chunk_start;\n\n auto block = cg::this_thread_block();\n const uint32_t window_left = (maybe_window_left >= 0) ? maybe_window_left : kv_len;\n\n constexpr uint32_t head_dim = num_frags_y * 16;\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<DTypeKV>();\n constexpr uint32_t channel_size_128b_out = head_dim / num_elems_per_128b<DTypeOut>();\n\n extern __shared__ uint8_t smem[];\n\n DTypeQKAccum s_frag[num_frags_x][num_frags_z][8];\n float o_frag[num_frags_x][num_frags_y][8];\n DTypeQKAccum m[num_frags_x][2];\n float d[num_frags_x][2];\n float rope_freq[num_frags_y / 2][4];\n if constexpr (pos_encoding_mode == PosEncodingMode::kRoPELlama) {\n init_rope_freq<num_frags_y>(rope_freq, log2_rope_rcp_scale, log2_rope_rcp_theta);\n }\n init_states<num_frags_x, num_frags_y>(o_frag, m, d);\n\n // cooperative fetch q fragment from gmem to reg\n const uint32_t qo_packed_idx_base =\n (bx * num_warps_x + get_warp_idx_x<num_warps_x, num_warps_z>()) * num_frags_x * 16;\n constexpr SwizzleMode swizzle_mode_q = SwizzleMode::k128B;\n smem_t<swizzle_mode_q> qo_smem(smem);\n DTypeQ* q_ptr_base =\n q + qkv_info.get_q_elem_offset(0, kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeQ>());\n DTypeOut* o_ptr_base =\n partition_kv\n ? o + chunk_idx * num_qo_heads * head_dim +\n qkv_info.get_o_elem_offset(0, kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeOut>())\n : o + qkv_info.get_o_elem_offset(0, kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeOut>());\n uint32_t q_smem_offset_r = qo_smem.get_permuted_offset<channel_size_128b_q>(\n get_warp_idx_x<num_warps_x, num_warps_z>() * num_frags_x * 16 + lane_idx % 16, lane_idx / 16);\n\n load_q_global_smem<num_warps_x, num_warps_z, num_frags_x, num_frags_y>(\n qo_packed_idx_base, qo_len, q_ptr_base, q_stride_n, q_stride_h, group_size, &qo_smem);\n\n cp_async::commit_group();\n cp_async::wait_group<0>();\n block.sync();\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kRoPELlama) {\n q_smem_inplace_apply_rotary_multiply_sm_scale<num_warps_x, num_warps_z, num_frags_x,\n num_frags_y, swizzle_mode_q, DTypeQ>(\n qo_packed_idx_base, qo_len, kv_len, group_size, &qo_smem, &q_smem_offset_r, rope_freq,\n sm_scale);\n } else {\n q_smem_inplace_multiply_sm_scale<num_warps_x, num_warps_z, num_frags_x, num_frags_y,\n swizzle_mode_q, DTypeQ>(&qo_smem, sm_scale);\n }\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kALiBi) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n const uint32_t qo_head_idx =\n kv_head_idx * group_size +\n (qo_packed_idx_base + lane_idx / 4 + j * 8 + fx * 16) % group_size;\n alibi_slopes[fx][j] = get_alibi_slope(qo_head_idx, num_qo_heads) * math::log2e;\n }\n }\n }\n\n constexpr SwizzleMode swizzle_mode_kv =\n (sizeof(DTypeKV) == 1 && head_dim == 64) ? SwizzleMode::k64B : SwizzleMode::k128B;\n constexpr uint32_t kv_frag_rows = swizzle_mode_kv == SwizzleMode::k128B ? 4 : 8;\n constexpr uint32_t kv_frag_cols = swizzle_mode_kv == SwizzleMode::k128B ? 8 : 4;\n smem_t<swizzle_mode_kv> k_smem(smem +\n (num_warps_x * num_frags_x * sizeof(DTypeQ)) * 16 * head_dim),\n v_smem(smem + (num_warps_x * num_frags_x * sizeof(DTypeQ) +\n num_warps_z * num_frags_z * sizeof(DTypeKV)) *\n 16 * head_dim);\n\n const uint32_t num_iterations = ceil_div(\n mask_mode == MaskMode::kCausal\n ? min(chunk_size,\n sub_if_greater_or_zero(kv_len - qo_len + ((bx + 1) * num_rows_per_cta) / group_size,\n chunk_start))\n : chunk_size,\n 16 * num_warps_z * num_frags_z);\n\n const uint32_t window_iteration =\n ceil_div(sub_if_greater_or_zero(kv_len + (bx + 1) * num_rows_per_cta,\n qo_len + window_left + chunk_start),\n (16 * num_warps_z * num_frags_z));\n\n const uint32_t mask_iteration =\n (mask_mode == MaskMode::kCausal\n ? min(chunk_size,\n sub_if_greater_or_zero(kv_len + (bx * num_rows_per_cta) / group_size - qo_len,\n chunk_start))\n : chunk_size) /\n (16 * num_warps_z * num_frags_z);\n\n DTypeKV* k_ptr = k + qkv_info.get_kv_elem_offset(\n chunk_start + warp_idx * kv_frag_rows + lane_idx / kv_frag_cols,\n kv_head_idx, (lane_idx % kv_frag_cols) * num_elems_per_128b<DTypeKV>());\n DTypeKV* v_ptr = v + qkv_info.get_kv_elem_offset(\n chunk_start + warp_idx * kv_frag_rows + lane_idx / kv_frag_cols,\n kv_head_idx, (lane_idx % kv_frag_cols) * num_elems_per_128b<DTypeKV>());\n uint32_t k_smem_offset_r = k_smem.get_permuted_offset<channel_size_128b_kv>(\n get_warp_idx_z<num_warps_x, num_warps_z>() * num_frags_z * 16 + 8 * (lane_idx / 16) +\n lane_idx % 8,\n (lane_idx % 16) / 8),\n v_smem_offset_r = v_smem.get_permuted_offset<channel_size_128b_kv>(\n get_warp_idx_z<num_warps_x, num_warps_z>() * num_frags_z * 16 + lane_idx % 16,\n lane_idx / 16),\n kv_smem_offset_w = k_smem.get_permuted_offset<channel_size_128b_kv>(\n warp_idx * kv_frag_rows + lane_idx / kv_frag_cols, lane_idx % kv_frag_cols);\n produce_kv<SharedMemFillMode::kNoFill, num_warps_x, num_warps_z, num_frags_y, num_frags_z>(\n k_smem, &kv_smem_offset_w, &k_ptr, kv_stride_n, 0, chunk_size);\n cp_async::commit_group();\n produce_kv<SharedMemFillMode::kFillZero, num_warps_x, num_warps_z, num_frags_y, num_frags_z>(\n v_smem, &kv_smem_offset_w, &v_ptr, kv_stride_n, 0, chunk_size);\n cp_async::commit_group();\n\n#pragma unroll 1\n for (uint32_t iter = 0; iter < num_iterations; ++iter) {\n cp_async::wait_group<1>();\n block.sync();\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kRoPELlama) {\n k_smem_inplace_apply_rotary<num_warps_x, num_warps_z, num_frags_y, num_frags_z,\n swizzle_mode_kv, DTypeKV>(\n chunk_start + iter * 16 * num_warps_z * num_frags_z, &k_smem, &k_smem_offset_r,\n rope_freq);\n block.sync();\n }\n\n // compute attention score\n compute_qk<logits_post_hook, num_frags_x, num_frags_y, num_frags_z, swizzle_mode_q,\n swizzle_mode_kv, DTypeQ, DTypeKV>(&qo_smem, &q_smem_offset_r, &k_smem,\n &k_smem_offset_r, s_frag, logits_soft_cap);\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kALiBi) {\n apply_alibi_bias<num_frags_x, num_frags_z>(\n qo_packed_idx_base,\n chunk_start +\n (iter * num_warps_z + get_warp_idx_z<num_warps_x, num_warps_z>()) * num_frags_z * 16,\n int(kv_len) - int(qo_len), group_size, alibi_slopes, s_frag);\n }\n // apply mask\n if constexpr (mask_mode == MaskMode::kCustom) {\n mask_s<mask_mode, num_frags_x, num_frags_y, num_frags_z>(\n qo_packed_idx_base,\n chunk_start +\n (iter * num_warps_z + get_warp_idx_z<num_warps_x, num_warps_z>()) * num_frags_z * 16,\n qo_len, kv_len, window_left, chunk_end, group_size, custom_mask, s_frag);\n } else {\n if (iter >= mask_iteration || iter < window_iteration) {\n mask_s<mask_mode, num_frags_x, num_frags_y, num_frags_z>(\n qo_packed_idx_base,\n chunk_start + (iter * num_warps_z + get_warp_idx_z<num_warps_x, num_warps_z>()) *\n num_frags_z * 16,\n qo_len, kv_len, window_left, chunk_end, group_size, nullptr, s_frag);\n }\n }\n\n // compute m,d states in online softmax\n update_mdo_states<num_frags_x, num_frags_y, num_frags_z>(s_frag, o_frag, m, d);\n\n block.sync();\n produce_kv<SharedMemFillMode::kNoFill, num_warps_x, num_warps_z, num_frags_y, num_frags_z>(\n k_smem, &kv_smem_offset_w, &k_ptr, kv_stride_n, (iter + 1) * 16 * num_warps_z * num_frags_z,\n chunk_size);\n cp_async::commit_group();\n cp_async::wait_group<1>();\n block.sync();\n\n // compute sfm*v\n compute_sfm_v<num_frags_x, num_frags_y, num_frags_z, swizzle_mode_kv, DTypeQ, DTypeKV>(\n &v_smem, &v_smem_offset_r, s_frag, o_frag, d);\n\n block.sync();\n produce_kv<SharedMemFillMode::kFillZero, num_warps_x, num_warps_z, num_frags_y, num_frags_z>(\n v_smem, &kv_smem_offset_w, &v_ptr, kv_stride_n, (iter + 1) * 16 * num_warps_z * num_frags_z,\n chunk_size);\n cp_async::commit_group();\n }\n cp_async::wait_group<0>();\n block.sync();\n\n // threadblock synchronization\n threadblock_sync_mdo_states<num_warps_x, num_warps_z, num_frags_x, num_frags_y, DTypeQKAccum>(\n o_frag, (float*)smem, m, d, warp_idx, lane_idx);\n\n // normalize d\n normalize_d<num_frags_x, num_frags_y>(o_frag, m, d);\n\n // write back\n write_o_reg_gmem<num_warps_x, num_warps_z, num_frags_x, num_frags_y>(\n o_frag, &qo_smem, o_ptr_base, qo_packed_idx_base, qo_len,\n /*o_stride_n=*/partition_kv ? num_qo_heads * head_dim * num_chunks : num_qo_heads * head_dim,\n /*o_stride_h=*/head_dim, group_size);\n\n // write lse\n if (lse != nullptr || partition_kv) {\n if (get_warp_idx_z<num_warps_x, num_warps_z>() == 0) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n uint32_t q, r;\n group_size.divmod(qo_packed_idx_base + lane_idx / 4 + j * 8 + fx * 16, q, r);\n const uint32_t qo_head_idx = kv_head_idx * group_size + r;\n const uint32_t qo_idx = q;\n if (qo_idx < qo_len) {\n if (partition_kv) {\n lse[(qo_idx * num_chunks + chunk_idx) * num_qo_heads + qo_head_idx] =\n math::ptx_log2(d[fx][j]) + float(m[fx][j]);\n } else {\n lse[qo_idx * num_qo_heads + qo_head_idx] = math::ptx_log2(d[fx][j]) + float(m[fx][j]);\n }\n }\n }\n }\n }\n }\n}\n\ntemplate <LogitsPostHook logits_post_hook, MaskMode mask_mode, PosEncodingMode pos_encoding_mode,\n uint32_t num_frags_x, uint32_t num_frags_y, uint32_t num_frags_z, uint32_t num_warps_x,\n uint32_t num_warps_z, typename DTypeQ, typename DTypeKV, typename DTypeQKAccum,\n typename DTypeOut, typename IdType>\n__global__\n__launch_bounds__(num_warps_x* num_warps_z* warp_size) void BatchPrefillWithRaggedKVCacheKernel(\n DTypeQ* __restrict__ q, IdType* __restrict__ request_indices,\n IdType* __restrict__ q_tile_indices, IdType* __restrict__ kv_tile_indices,\n IdType* __restrict__ q_indptr, DTypeKV* __restrict__ k, DTypeKV* __restrict__ v,\n IdType* __restrict__ kv_indptr, uint8_t* __restrict__ custom_mask,\n IdType* __restrict__ qk_indptr, IdType* __restrict__ q_offset,\n IdType* __restrict__ k_rope_pos_offset, IdType* __restrict__ o_indptr, DTypeOut* __restrict__ o,\n float* __restrict__ lse, bool* __restrict__ block_valid_mask,\n IdType* __restrict__ kv_chunk_size_ptr, const bool partition_kv, const uint_fastdiv group_size,\n const uint32_t q_stride_n, const uint32_t q_stride_h, const uint32_t kv_stride_n,\n const uint32_t kv_stride_h, const int32_t maybe_window_left, const float logits_soft_cap,\n float sm_scale, const float log2_rope_rcp_scale, const float log2_rope_rcp_theta) {\n static_assert(sizeof(DTypeQ) == 2);\n static_assert(sizeof(DTypeOut) == 2);\n sm_scale *=\n (logits_post_hook == LogitsPostHook::kNone ? math::log2e : math::ptx_rcp(logits_soft_cap));\n constexpr uint32_t head_dim = num_frags_y * 16;\n const uint32_t kv_chunk_size = *kv_chunk_size_ptr;\n\n auto block = cg::this_thread_block();\n const uint32_t bx = blockIdx.x, lane_idx = threadIdx.x,\n warp_idx = get_warp_idx<num_warps_x, num_warps_z>(), kv_head_idx = blockIdx.z;\n if (block_valid_mask && !block_valid_mask[bx]) {\n return;\n }\n const uint32_t num_kv_heads = gridDim.z, num_qo_heads = group_size * num_kv_heads;\n const uint32_t request_idx = request_indices[bx], qo_tile_idx = q_tile_indices[bx],\n kv_tile_idx = kv_tile_indices[bx];\n constexpr uint32_t num_rows_per_cta = num_frags_x * num_warps_x * 16;\n const uint32_t qo_len = q_indptr[request_idx + 1] - q_indptr[request_idx],\n kv_len = kv_indptr[request_idx + 1] - kv_indptr[request_idx];\n const uint32_t kv_len_safe = kv_len > 0 ? kv_len : 1;\n const uint32_t window_left = (maybe_window_left >= 0) ? maybe_window_left : kv_len;\n const uint32_t max_chunk_size = partition_kv ? kv_chunk_size : kv_len;\n const uint32_t chunk_start = partition_kv ? kv_tile_idx * max_chunk_size : 0;\n const uint32_t chunk_end =\n partition_kv ? min((kv_tile_idx + 1) * max_chunk_size, kv_len) : kv_len;\n const uint32_t chunk_size = chunk_end - chunk_start;\n const tensor_info_t qkv_info(qo_len, kv_len, num_qo_heads, num_kv_heads, q_stride_n, q_stride_h,\n kv_stride_n, kv_stride_h, /*head_dim=*/num_frags_y * 16);\n float alibi_slopes[num_frags_x][2];\n const uint32_t qo_upper_bound =\n min(qo_len, ceil_div((qo_tile_idx + 1) * num_rows_per_cta, group_size));\n\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<DTypeKV>();\n constexpr uint32_t channel_size_128b_out = head_dim / num_elems_per_128b<DTypeOut>();\n\n extern __shared__ uint8_t smem[];\n\n DTypeQKAccum s_frag[num_frags_x][num_frags_z][8];\n float o_frag[num_frags_x][num_frags_y][8];\n DTypeQKAccum m[num_frags_x][2];\n float d[num_frags_x][2];\n float rope_freq[num_frags_y / 2][4];\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kRoPELlama) {\n init_rope_freq<num_frags_y>(rope_freq, log2_rope_rcp_scale, log2_rope_rcp_theta);\n }\n init_states<num_frags_x, num_frags_y>(o_frag, m, d);\n\n const uint32_t qo_packed_idx_base =\n (qo_tile_idx * num_warps_x + get_warp_idx_x<num_warps_x, num_warps_z>()) * num_frags_x * 16;\n constexpr SwizzleMode swizzle_mode_q = SwizzleMode::k128B;\n smem_t<swizzle_mode_q> qo_smem(smem);\n\n DTypeQ* q_ptr_base =\n q + qkv_info.get_q_elem_offset(q_indptr[request_idx], kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeQ>());\n\n DTypeOut* o_ptr_base =\n partition_kv\n ? o + kv_tile_idx * num_qo_heads * head_dim +\n qkv_info.get_o_elem_offset(o_indptr[request_idx], kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeOut>())\n : o + qkv_info.get_o_elem_offset(o_indptr[request_idx], kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeOut>());\n\n uint32_t q_smem_offset_r = qo_smem.get_permuted_offset<channel_size_128b_q>(\n get_warp_idx_x<num_warps_x, num_warps_z>() * num_frags_x * 16 + lane_idx % 16, lane_idx / 16);\n\n load_q_global_smem<num_warps_x, num_warps_z, num_frags_x, num_frags_y>(\n qo_packed_idx_base, qo_upper_bound, q_ptr_base, q_stride_n, q_stride_h, group_size, &qo_smem);\n\n cp_async::commit_group();\n cp_async::wait_group<0>();\n block.sync();\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kRoPELlama) {\n if (!q_offset) {\n q_smem_inplace_apply_rotary_multiply_sm_scale<num_warps_x, num_warps_z, num_frags_x,\n num_frags_y, swizzle_mode_q, DTypeQ>(\n qo_packed_idx_base, qo_len, kv_len, group_size, &qo_smem, &q_smem_offset_r, rope_freq,\n sm_scale);\n } else {\n q_smem_inplace_apply_rotary_with_pos_multiply_sm_scale<num_warps_x, num_warps_z, num_frags_x,\n num_frags_y, swizzle_mode_q, DTypeQ>(\n qo_packed_idx_base, q_offset + q_indptr[request_idx], &qo_smem, group_size,\n &q_smem_offset_r, rope_freq, sm_scale);\n }\n } else {\n q_smem_inplace_multiply_sm_scale<num_warps_x, num_warps_z, num_frags_x, num_frags_y,\n swizzle_mode_q, DTypeQ>(&qo_smem, sm_scale);\n }\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kALiBi) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n const uint32_t qo_head_idx =\n kv_head_idx * group_size +\n (qo_packed_idx_base + lane_idx / 4 + j * 8 + fx * 16) % group_size;\n alibi_slopes[fx][j] = get_alibi_slope(qo_head_idx, num_qo_heads) * math::log2e;\n }\n }\n }\n\n const uint32_t num_iterations =\n ceil_div((mask_mode == MaskMode::kCausal\n ? min(chunk_size,\n sub_if_greater_or_zero(\n kv_len - qo_len + ((qo_tile_idx + 1) * num_rows_per_cta) / group_size,\n chunk_start))\n : chunk_size),\n 16 * num_warps_z * num_frags_z);\n\n const uint32_t window_iteration =\n ceil_div(sub_if_greater_or_zero(kv_len + (bx + 1) * num_rows_per_cta,\n qo_len + window_left + chunk_start),\n (16 * num_warps_z * num_frags_z));\n\n const uint32_t mask_iteration =\n (mask_mode == MaskMode::kCausal\n ? min(chunk_size,\n sub_if_greater_or_zero(\n kv_len + (qo_tile_idx * num_rows_per_cta) / group_size - qo_len, chunk_start))\n : chunk_size) /\n (16 * num_warps_z * num_frags_z);\n\n constexpr SwizzleMode swizzle_mode_kv =\n (sizeof(DTypeKV) == 1 && head_dim == 64) ? SwizzleMode::k64B : SwizzleMode::k128B;\n constexpr uint32_t kv_frag_rows = swizzle_mode_kv == SwizzleMode::k128B ? 4 : 8;\n constexpr uint32_t kv_frag_cols = swizzle_mode_kv == SwizzleMode::k128B ? 8 : 4;\n smem_t<swizzle_mode_kv> k_smem(smem +\n (num_warps_x * num_frags_x * sizeof(DTypeQ)) * 16 * head_dim),\n v_smem(smem + (num_warps_x * num_frags_x * sizeof(DTypeQ) +\n num_warps_z * num_frags_z * sizeof(DTypeKV)) *\n 16 * head_dim);\n\n uint32_t k_smem_offset_r = k_smem.get_permuted_offset<channel_size_128b_kv>(\n get_warp_idx_z<num_warps_x, num_warps_z>() * num_frags_z * 16 + 8 * (lane_idx / 16) +\n lane_idx % 8,\n (lane_idx % 16) / 8),\n v_smem_offset_r = v_smem.get_permuted_offset<channel_size_128b_kv>(\n get_warp_idx_z<num_warps_x, num_warps_z>() * num_frags_z * 16 + lane_idx % 16,\n lane_idx / 16),\n kv_smem_offset_w = k_smem.get_permuted_offset<channel_size_128b_kv>(\n warp_idx * kv_frag_rows + lane_idx / kv_frag_cols, lane_idx % kv_frag_cols);\n\n DTypeKV* k_ptr = k + qkv_info.get_kv_elem_offset(\n kv_indptr[request_idx] + chunk_start + warp_idx * kv_frag_rows +\n lane_idx / kv_frag_cols,\n kv_head_idx, (lane_idx % kv_frag_cols) * num_elems_per_128b<DTypeKV>());\n DTypeKV* v_ptr = v + qkv_info.get_kv_elem_offset(\n kv_indptr[request_idx] + chunk_start + warp_idx * kv_frag_rows +\n lane_idx / kv_frag_cols,\n kv_head_idx, (lane_idx % kv_frag_cols) * num_elems_per_128b<DTypeKV>());\n\n produce_kv<SharedMemFillMode::kNoFill, num_warps_x, num_warps_z, num_frags_y, num_frags_z>(\n k_smem, &kv_smem_offset_w, &k_ptr, kv_stride_n, 0, chunk_size);\n cp_async::commit_group();\n produce_kv<SharedMemFillMode::kFillZero, num_warps_x, num_warps_z, num_frags_y, num_frags_z>(\n v_smem, &kv_smem_offset_w, &v_ptr, kv_stride_n, 0, chunk_size);\n cp_async::commit_group();\n\n#pragma unroll 1\n for (uint32_t iter = 0; iter < num_iterations; ++iter) {\n cp_async::wait_group<1>();\n block.sync();\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kRoPELlama) {\n k_smem_inplace_apply_rotary<num_warps_x, num_warps_z, num_frags_y, num_frags_z,\n swizzle_mode_kv, DTypeKV>(\n (k_rope_pos_offset == nullptr ? 0 : k_rope_pos_offset[request_idx]) + chunk_start +\n iter * 16 * num_warps_z * num_frags_z,\n &k_smem, &k_smem_offset_r, rope_freq);\n block.sync();\n }\n\n // compute attention score\n compute_qk<logits_post_hook, num_frags_x, num_frags_y, num_frags_z, swizzle_mode_q,\n swizzle_mode_kv, DTypeQ, DTypeKV>(&qo_smem, &q_smem_offset_r, &k_smem,\n &k_smem_offset_r, s_frag, logits_soft_cap);\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kALiBi) {\n // TODO(Zihao): handle the case that q_offset is specified\n apply_alibi_bias<num_frags_x, num_frags_z>(\n qo_packed_idx_base,\n chunk_start +\n (iter * num_warps_z + get_warp_idx_z<num_warps_x, num_warps_z>()) * num_frags_z * 16,\n int(kv_len) - int(qo_len), group_size, alibi_slopes, s_frag);\n }\n // apply mask\n if constexpr (mask_mode == MaskMode::kCustom) {\n mask_s<mask_mode, num_frags_x, num_frags_y, num_frags_z>(\n qo_packed_idx_base,\n chunk_start +\n (iter * num_warps_z + get_warp_idx_z<num_warps_x, num_warps_z>()) * num_frags_z * 16,\n qo_len, kv_len, window_left, chunk_end, group_size, custom_mask + qk_indptr[request_idx],\n s_frag);\n } else {\n if (iter >= mask_iteration || iter < window_iteration) {\n mask_s<mask_mode, num_frags_x, num_frags_y, num_frags_z>(\n qo_packed_idx_base,\n chunk_start + (iter * num_warps_z + get_warp_idx_z<num_warps_x, num_warps_z>()) *\n num_frags_z * 16,\n qo_len, kv_len, window_left, chunk_end, group_size, nullptr, s_frag);\n }\n }\n\n // compute m,d states in online softmax\n update_mdo_states<num_frags_x, num_frags_y, num_frags_z>(s_frag, o_frag, m, d);\n\n block.sync();\n produce_kv<SharedMemFillMode::kNoFill, num_warps_x, num_warps_z, num_frags_y, num_frags_z>(\n k_smem, &kv_smem_offset_w, &k_ptr, kv_stride_n, (iter + 1) * 16 * num_warps_z * num_frags_z,\n chunk_size);\n cp_async::commit_group();\n cp_async::wait_group<1>();\n block.sync();\n\n // compute sfm*v\n compute_sfm_v<num_frags_x, num_frags_y, num_frags_z, swizzle_mode_kv, DTypeQ, DTypeKV>(\n &v_smem, &v_smem_offset_r, s_frag, o_frag, d);\n\n block.sync();\n produce_kv<SharedMemFillMode::kFillZero, num_warps_x, num_warps_z, num_frags_y, num_frags_z>(\n v_smem, &kv_smem_offset_w, &v_ptr, kv_stride_n, (iter + 1) * 16 * num_warps_z * num_frags_z,\n chunk_size);\n cp_async::commit_group();\n }\n cp_async::wait_group<0>();\n block.sync();\n\n // threadblock synchronization\n threadblock_sync_mdo_states<num_warps_x, num_warps_z, num_frags_x, num_frags_y, DTypeQKAccum>(\n o_frag, (float*)smem, m, d, warp_idx, lane_idx);\n\n // normalize d\n normalize_d<num_frags_x, num_frags_y>(o_frag, m, d);\n\n const uint32_t num_kv_chunks = (kv_len_safe + kv_chunk_size - 1) / kv_chunk_size;\n\n // write back\n write_o_reg_gmem<num_warps_x, num_warps_z, num_frags_x, num_frags_y>(\n o_frag, &qo_smem, o_ptr_base, qo_packed_idx_base, qo_len,\n /*o_stride_n=*/\n partition_kv ? num_qo_heads * head_dim * num_kv_chunks : num_qo_heads * head_dim,\n /*o_stride_h=*/head_dim, group_size);\n\n // write lse\n if (lse != nullptr) {\n if (get_warp_idx_z<num_warps_x, num_warps_z>() == 0) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n uint32_t q, r;\n group_size.divmod(qo_packed_idx_base + lane_idx / 4 + j * 8 + fx * 16, q, r);\n const uint32_t qo_head_idx = kv_head_idx * group_size + r;\n const uint32_t qo_idx = q;\n if (qo_idx < qo_len) {\n if (partition_kv) {\n lse[(o_indptr[request_idx] + qo_idx * num_kv_chunks + kv_tile_idx) * num_qo_heads +\n qo_head_idx] = math::ptx_log2(d[fx][j]) + float(m[fx][j]);\n } else {\n lse[(o_indptr[request_idx] + qo_idx) * num_qo_heads + qo_head_idx] =\n math::ptx_log2(d[fx][j]) + float(m[fx][j]);\n }\n }\n }\n }\n }\n }\n}\n\ntemplate <LogitsPostHook logits_post_hook, MaskMode mask_mode, PosEncodingMode pos_encoding_mode,\n uint32_t num_frags_x, uint32_t num_frags_y, uint32_t num_frags_z, uint32_t num_warps_x,\n uint32_t num_warps_z, PageStorage page_storage, typename DTypeQ, typename DTypeKV,\n typename DTypeQKAccum, typename DTypeOut, typename IdType>\n__global__\n__launch_bounds__(num_warps_x* num_warps_z* warp_size) void BatchPrefillWithPagedKVCacheKernel(\n IdType* __restrict__ request_indices, IdType* __restrict__ q_tile_indices,\n IdType* __restrict__ kv_tile_indices, DTypeQ* __restrict__ q,\n paged_kv_t<page_storage, DTypeKV, IdType> paged_kv, IdType* __restrict__ q_indptr,\n uint8_t* __restrict__ custom_mask, IdType* __restrict__ qk_indptr,\n IdType* __restrict__ q_offset, IdType* __restrict__ o_indptr, DTypeOut* __restrict__ o,\n float* __restrict__ lse, bool* __restrict__ block_valid_mask,\n IdType* __restrict__ kv_chunk_size_ptr, const bool partition_kv, const uint_fastdiv group_size,\n int32_t maybe_window_left, const float logits_soft_cap, float sm_scale,\n const float log2_rope_rcp_scale, const float log2_rope_rcp_theta) {\n static_assert(sizeof(DTypeQ) == 2);\n static_assert(sizeof(DTypeOut) == 2);\n sm_scale *=\n (logits_post_hook == LogitsPostHook::kNone ? math::log2e : math::ptx_rcp(logits_soft_cap));\n auto block = cg::this_thread_block();\n const uint32_t kv_chunk_size = *kv_chunk_size_ptr;\n\n const uint32_t bx = blockIdx.x, lane_idx = threadIdx.x,\n warp_idx = get_warp_idx<num_warps_x, num_warps_z>(), kv_head_idx = blockIdx.z;\n if (block_valid_mask && !block_valid_mask[bx]) {\n return;\n }\n const uint32_t num_kv_heads = gridDim.z, num_qo_heads = num_kv_heads * group_size;\n float alibi_slopes[num_frags_x][2];\n\n const uint32_t request_idx = request_indices[bx], qo_tile_idx = q_tile_indices[bx],\n kv_tile_idx = kv_tile_indices[bx];\n constexpr uint32_t num_rows_per_cta = num_frags_x * num_warps_x * 16;\n const uint32_t qo_len = q_indptr[request_idx + 1] - q_indptr[request_idx],\n kv_len = (paged_kv.indptr[request_idx + 1] != paged_kv.indptr[request_idx])\n ? (paged_kv.indptr[request_idx + 1] - paged_kv.indptr[request_idx] -\n 1) * paged_kv.page_size +\n paged_kv.last_page_len[request_idx]\n : 0;\n const uint32_t kv_len_safe = kv_len > 0 ? kv_len : 1;\n const uint32_t window_left = (maybe_window_left >= 0) ? maybe_window_left : kv_len;\n const uint32_t max_chunk_size = partition_kv ? kv_chunk_size : kv_len;\n const uint32_t chunk_start = partition_kv ? kv_tile_idx * max_chunk_size : 0;\n const uint32_t chunk_end =\n partition_kv ? min((kv_tile_idx + 1) * max_chunk_size, kv_len) : kv_len;\n const uint32_t chunk_size = chunk_end - chunk_start;\n const uint32_t qo_upper_bound =\n min(qo_len, ceil_div((qo_tile_idx + 1) * num_rows_per_cta, group_size));\n\n constexpr uint32_t head_dim = num_frags_y * 16;\n constexpr uint32_t channel_size_128b_q = head_dim / num_elems_per_128b<DTypeQ>();\n constexpr uint32_t channel_size_128b_kv = head_dim / num_elems_per_128b<DTypeKV>();\n constexpr uint32_t channel_size_128b_out = head_dim / num_elems_per_128b<DTypeOut>();\n\n extern __shared__ uint8_t smem[];\n\n DTypeQKAccum s_frag[num_frags_x][num_frags_z][8];\n float o_frag[num_frags_x][num_frags_y][8];\n DTypeQKAccum m[num_frags_x][2];\n float d[num_frags_x][2];\n float rope_freq[num_frags_y / 2][4];\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kRoPELlama) {\n init_rope_freq<num_frags_y>(rope_freq, log2_rope_rcp_scale, log2_rope_rcp_theta);\n }\n init_states<num_frags_x, num_frags_y>(o_frag, m, d);\n\n const uint32_t qo_packed_idx_base =\n (qo_tile_idx * num_warps_x + get_warp_idx_x<num_warps_x, num_warps_z>()) * num_frags_x * 16;\n const uint32_t q_stride_n = num_qo_heads * head_dim, q_stride_h = head_dim;\n constexpr SwizzleMode swizzle_mode_q = SwizzleMode::k128B;\n smem_t<swizzle_mode_q> qo_smem(smem);\n DTypeQ* q_ptr_base = q + get_elem_offset_impl(q_indptr[request_idx], kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeQ>(),\n q_stride_n, q_stride_h);\n DTypeOut* o_ptr_base =\n partition_kv ? o + kv_tile_idx * num_qo_heads * head_dim +\n get_elem_offset_impl(o_indptr[request_idx], kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeOut>(),\n num_qo_heads * head_dim, head_dim)\n : o + get_elem_offset_impl(o_indptr[request_idx], kv_head_idx * group_size,\n (lane_idx % 8) * num_elems_per_128b<DTypeOut>(),\n num_qo_heads * head_dim, head_dim);\n uint32_t q_smem_offset_r = qo_smem.get_permuted_offset<channel_size_128b_q>(\n get_warp_idx_x<num_warps_x, num_warps_z>() * num_frags_x * 16 + lane_idx % 16, lane_idx / 16);\n\n load_q_global_smem<num_warps_x, num_warps_z, num_frags_x, num_frags_y>(\n qo_packed_idx_base, qo_upper_bound, q_ptr_base, q_stride_n, q_stride_h, group_size, &qo_smem);\n\n cp_async::commit_group();\n cp_async::wait_group<0>();\n block.sync();\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kRoPELlama) {\n if (q_offset == nullptr) {\n q_smem_inplace_apply_rotary_multiply_sm_scale<num_warps_x, num_warps_z, num_frags_x,\n num_frags_y, swizzle_mode_q, DTypeQ>(\n qo_packed_idx_base, qo_len, kv_len, group_size, &qo_smem, &q_smem_offset_r, rope_freq,\n sm_scale);\n } else {\n q_smem_inplace_apply_rotary_with_pos_multiply_sm_scale<num_warps_x, num_warps_z, num_frags_x,\n num_frags_y, swizzle_mode_q, DTypeQ>(\n qo_packed_idx_base, q_offset + q_indptr[request_idx], &qo_smem, group_size,\n &q_smem_offset_r, rope_freq, sm_scale);\n }\n } else {\n q_smem_inplace_multiply_sm_scale<num_warps_x, num_warps_z, num_frags_x, num_frags_y,\n swizzle_mode_q, DTypeQ>(&qo_smem, sm_scale);\n }\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kALiBi) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n const uint32_t qo_head_idx =\n kv_head_idx * group_size +\n (qo_packed_idx_base + lane_idx / 4 + j * 8 + fx * 16) % group_size;\n alibi_slopes[fx][j] = get_alibi_slope(qo_head_idx, num_qo_heads) * math::log2e;\n }\n }\n }\n\n constexpr SwizzleMode swizzle_mode_kv =\n (sizeof(DTypeKV) == 1 && head_dim == 64) ? SwizzleMode::k64B : SwizzleMode::k128B;\n constexpr uint32_t kv_frag_rows = swizzle_mode_kv == SwizzleMode::k128B ? 4 : 8;\n constexpr uint32_t kv_frag_cols = swizzle_mode_kv == SwizzleMode::k128B ? 8 : 4;\n smem_t<swizzle_mode_kv> k_smem(smem +\n (num_warps_x * num_frags_x * sizeof(DTypeQ)) * 16 * head_dim),\n v_smem(smem + (num_warps_x * num_frags_x * sizeof(DTypeQ) +\n num_warps_z * num_frags_z * sizeof(DTypeKV)) *\n 16 * head_dim);\n size_t kv_offset[num_frags_z * (swizzle_mode_kv == SwizzleMode::k128B ? 4 : 2) / num_warps_x];\n\n uint32_t k_smem_offset_r = k_smem.get_permuted_offset<channel_size_128b_kv>(\n get_warp_idx_z<num_warps_x, num_warps_z>() * num_frags_z * 16 + 8 * (lane_idx / 16) +\n lane_idx % 8,\n (lane_idx % 16) / 8),\n v_smem_offset_r = v_smem.get_permuted_offset<channel_size_128b_kv>(\n get_warp_idx_z<num_warps_x, num_warps_z>() * num_frags_z * 16 + lane_idx % 16,\n lane_idx / 16),\n kv_smem_offset_w = k_smem.get_permuted_offset<channel_size_128b_kv>(\n warp_idx * kv_frag_rows + lane_idx / kv_frag_cols, lane_idx % kv_frag_cols);\n const IdType last_indptr = paged_kv.indptr[paged_kv.batch_size];\n\n uint32_t packed_page_iter_base = paged_kv.indptr[request_idx] * paged_kv.page_size + chunk_start;\n#pragma unroll\n for (uint32_t i = 0;\n i < num_frags_z * (swizzle_mode_kv == SwizzleMode::k128B ? 4 : 2) / num_warps_x; ++i) {\n uint32_t page_iter, entry_idx;\n paged_kv.page_size.divmod(packed_page_iter_base + warp_idx * kv_frag_rows +\n lane_idx / kv_frag_cols +\n kv_frag_rows * num_warps_x * num_warps_z * i,\n page_iter, entry_idx);\n kv_offset[i] =\n page_iter < last_indptr\n ? paged_kv.get_elem_offset(__ldg(paged_kv.indices + page_iter), kv_head_idx, entry_idx,\n (lane_idx % kv_frag_cols) * num_elems_per_128b<DTypeKV>())\n : 0;\n }\n page_produce_kv<false, num_warps_x, num_warps_z, num_frags_y, num_frags_z>(\n k_smem, &kv_smem_offset_w, paged_kv, 0, kv_offset, chunk_size);\n cp_async::commit_group();\n page_produce_kv<true, num_warps_x, num_warps_z, num_frags_y, num_frags_z>(\n v_smem, &kv_smem_offset_w, paged_kv, 0, kv_offset, chunk_size);\n cp_async::commit_group();\n\n const uint32_t num_iterations =\n ceil_div((mask_mode == MaskMode::kCausal\n ? min(chunk_size,\n sub_if_greater_or_zero(\n kv_len - qo_len + ((qo_tile_idx + 1) * num_rows_per_cta) / group_size,\n chunk_start))\n : chunk_size),\n 16 * num_warps_z * num_frags_z);\n\n const uint32_t window_iteration =\n ceil_div(sub_if_greater_or_zero(kv_len + (bx + 1) * num_rows_per_cta,\n qo_len + window_left + chunk_start),\n (16 * num_warps_z * num_frags_z));\n\n const uint32_t mask_iteration =\n (mask_mode == MaskMode::kCausal\n ? min(chunk_size,\n sub_if_greater_or_zero(\n kv_len + (qo_tile_idx * num_rows_per_cta) / group_size - qo_len, chunk_start))\n : chunk_size) /\n (16 * num_warps_z * num_frags_z);\n\n#pragma unroll 1\n for (uint32_t iter = 0; iter < num_iterations; ++iter) {\n packed_page_iter_base += 16 * num_warps_z * num_frags_z;\n#pragma unroll\n for (uint32_t i = 0;\n i < num_frags_z * (swizzle_mode_kv == SwizzleMode::k128B ? 4 : 2) / num_warps_x; ++i) {\n uint32_t page_iter, entry_idx;\n paged_kv.page_size.divmod(packed_page_iter_base + warp_idx * kv_frag_rows +\n lane_idx / kv_frag_cols +\n kv_frag_rows * num_warps_x * num_warps_z * i,\n page_iter, entry_idx);\n kv_offset[i] = page_iter < last_indptr\n ? paged_kv.get_elem_offset(\n __ldg(paged_kv.indices + page_iter), kv_head_idx, entry_idx,\n (lane_idx % kv_frag_cols) * num_elems_per_128b<DTypeKV>())\n : 0;\n }\n cp_async::wait_group<1>();\n block.sync();\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kRoPELlama) {\n k_smem_inplace_apply_rotary<num_warps_x, num_warps_z, num_frags_y, num_frags_z,\n swizzle_mode_kv, DTypeKV>(\n (paged_kv.rope_pos_offset == nullptr ? 0 : paged_kv.rope_pos_offset[request_idx]) +\n chunk_start + iter * 16 * num_warps_z * num_frags_z,\n &k_smem, &k_smem_offset_r, rope_freq);\n block.sync();\n }\n\n // compute attention score\n compute_qk<logits_post_hook, num_frags_x, num_frags_y, num_frags_z, swizzle_mode_q,\n swizzle_mode_kv, DTypeQ, DTypeKV>(&qo_smem, &q_smem_offset_r, &k_smem,\n &k_smem_offset_r, s_frag, logits_soft_cap);\n\n if constexpr (pos_encoding_mode == PosEncodingMode::kALiBi) {\n // TODO(Zihao): handle the case that q_offset is specified\n apply_alibi_bias<num_frags_x, num_frags_z>(\n qo_packed_idx_base,\n chunk_start +\n (iter * num_warps_z + get_warp_idx_z<num_warps_x, num_warps_z>()) * num_frags_z * 16,\n int(kv_len) - int(qo_len), group_size, alibi_slopes, s_frag);\n }\n // apply mask\n if constexpr (mask_mode == MaskMode::kCustom) {\n mask_s<mask_mode, num_frags_x, num_frags_y, num_frags_z>(\n qo_packed_idx_base,\n chunk_start +\n (iter * num_warps_z + get_warp_idx_z<num_warps_x, num_warps_z>()) * num_frags_z * 16,\n qo_len, kv_len, window_left, chunk_end, group_size, custom_mask + qk_indptr[request_idx],\n s_frag);\n } else {\n if (iter >= mask_iteration || iter < window_iteration) {\n mask_s<mask_mode, num_frags_x, num_frags_y, num_frags_z>(\n qo_packed_idx_base,\n chunk_start + (iter * num_warps_z + get_warp_idx_z<num_warps_x, num_warps_z>()) *\n num_frags_z * 16,\n qo_len, kv_len, window_left, chunk_end, group_size, nullptr, s_frag);\n }\n }\n\n // compute m,d states in online softmax\n update_mdo_states<num_frags_x, num_frags_y, num_frags_z>(s_frag, o_frag, m, d);\n\n block.sync();\n page_produce_kv<false, num_warps_x, num_warps_z, num_frags_y, num_frags_z>(\n k_smem, &kv_smem_offset_w, paged_kv, (iter + 1) * 16 * num_warps_z * num_frags_z, kv_offset,\n chunk_size);\n cp_async::commit_group();\n cp_async::wait_group<1>();\n block.sync();\n\n // compute sfm*v\n compute_sfm_v<num_frags_x, num_frags_y, num_frags_z, swizzle_mode_kv, DTypeQ, DTypeKV>(\n &v_smem, &v_smem_offset_r, s_frag, o_frag, d);\n\n block.sync();\n page_produce_kv<true, num_warps_x, num_warps_z, num_frags_y, num_frags_z>(\n v_smem, &kv_smem_offset_w, paged_kv, (iter + 1) * 16 * num_warps_z * num_frags_z, kv_offset,\n chunk_size);\n cp_async::commit_group();\n }\n cp_async::wait_group<0>();\n block.sync();\n\n // threadblock synchronization\n threadblock_sync_mdo_states<num_warps_x, num_warps_z, num_frags_x, num_frags_y, DTypeQKAccum>(\n o_frag, (float*)smem, m, d, warp_idx, lane_idx);\n\n // normalize d\n normalize_d<num_frags_x, num_frags_y>(o_frag, m, d);\n\n const uint32_t num_kv_chunks = (kv_len_safe + kv_chunk_size - 1) / kv_chunk_size;\n\n // write_back\n write_o_reg_gmem<num_warps_x, num_warps_z, num_frags_x, num_frags_y>(\n o_frag, &qo_smem, o_ptr_base, qo_packed_idx_base, qo_len,\n /*o_stride_n=*/\n partition_kv ? num_qo_heads * head_dim * num_kv_chunks : num_qo_heads * head_dim,\n /*o_stride_h=*/head_dim, group_size);\n\n // write lse\n if (lse != nullptr) {\n if (get_warp_idx_z<num_warps_x, num_warps_z>() == 0) {\n#pragma unroll\n for (uint32_t fx = 0; fx < num_frags_x; ++fx) {\n#pragma unroll\n for (uint32_t j = 0; j < 2; ++j) {\n uint32_t q, r;\n group_size.divmod(qo_packed_idx_base + lane_idx / 4 + j * 8 + fx * 16, q, r);\n const uint32_t qo_head_idx = kv_head_idx * group_size + r;\n const uint32_t qo_idx = q;\n if (qo_idx < qo_upper_bound) {\n if (partition_kv) {\n lse[(o_indptr[request_idx] + qo_idx * num_kv_chunks + kv_tile_idx) * num_qo_heads +\n qo_head_idx] = math::ptx_log2(d[fx][j]) + float(m[fx][j]);\n } else {\n lse[(o_indptr[request_idx] + qo_idx) * num_qo_heads + qo_head_idx] =\n math::ptx_log2(d[fx][j]) + float(m[fx][j]);\n }\n }\n }\n }\n }\n }\n}\n\ntemplate <uint32_t HEAD_DIM, LogitsPostHook LOGITS_POST_HOOK, PosEncodingMode pos_encoding_mode,\n bool ALLOW_FP16_QK_REDUCTION, MaskMode MASK_MODE, typename DTypeQ, typename DTypeKV,\n typename DTypeOut>\ncudaError_t SinglePrefillWithKVCacheDispatched(\n DTypeQ* q, DTypeKV* k, DTypeKV* v, uint8_t* custom_mask, DTypeOut* o, DTypeOut* tmp, float* lse,\n uint32_t num_qo_heads, uint32_t num_kv_heads, uint32_t qo_len, uint32_t kv_len,\n uint32_t q_stride_n, uint32_t q_stride_h, uint32_t kv_stride_n, uint32_t kv_stride_h,\n int32_t window_left, float logits_soft_cap, float sm_scale, float rope_scale, float rope_theta,\n cudaStream_t stream) {\n const float log2_rope_rcp_scale = -std::log2f(rope_scale);\n const float log2_rope_rcp_theta = -std::log2f(rope_theta);\n if (kv_len < qo_len && MASK_MODE == MaskMode::kCausal) {\n std::ostringstream err_msg;\n err_msg << \"When mask_mode is set to MaskMode::kCausal, kv_len must be greater than or equal \"\n \"to qo_len, got kv_len\"\n << kv_len << \" and qo_len \" << qo_len;\n throw std::invalid_argument(err_msg.str());\n }\n\n const uint32_t group_size = num_qo_heads / num_kv_heads;\n const uint_fastdiv group_size_fastdiv(group_size);\n constexpr uint32_t num_frags_y = HEAD_DIM / 16;\n WarpLayout warp_layout;\n int64_t unpacked_qo_len = qo_len * group_size;\n if (unpacked_qo_len > 64 && HEAD_DIM < 256) {\n warp_layout = WarpLayout::k4x1x2;\n } else {\n if (unpacked_qo_len > 16) {\n warp_layout = WarpLayout::k4x1x1;\n } else {\n warp_layout = WarpLayout::k1x4x1;\n }\n }\n\n DISPATCH_WARP_LAYOUT(warp_layout, WARP_LAYOUT, {\n constexpr uint32_t num_frags_x = get_num_frags_x<WARP_LAYOUT>();\n using DTypeQKAccum =\n typename std::conditional<ALLOW_FP16_QK_REDUCTION && std::is_same<DTypeQ, half>::value,\n half, float>::type;\n\n int dev_id = 0;\n FLASHINFER_CUDA_CALL(cudaGetDevice(&dev_id));\n int max_smem_per_sm = 0;\n FLASHINFER_CUDA_CALL(cudaDeviceGetAttribute(\n &max_smem_per_sm, cudaDevAttrMaxSharedMemoryPerMultiprocessor, dev_id));\n // we expect each sm execute two threadblocks\n // TODO(Zihao): fix the following computation\n const int num_ctas_per_sm = max_smem_per_sm > (16 * HEAD_DIM * sizeof(DTypeQ) * 16) ? 2 : 1;\n const int max_smem_per_threadblock = max_smem_per_sm / num_ctas_per_sm;\n\n constexpr uint32_t num_warps_x = get_num_warps_x<WARP_LAYOUT>();\n constexpr uint32_t num_warps_z = get_num_warps_z<WARP_LAYOUT>();\n const uint32_t max_num_frags_z_reg =\n (HEAD_DIM >= 128 && num_frags_x == 2 && pos_encoding_mode == PosEncodingMode::kRoPELlama &&\n !ALLOW_FP16_QK_REDUCTION)\n ? 2\n : (8 / num_frags_x);\n // TODO(Zihao): fix the following computation\n const uint32_t max_num_frags_z_smem =\n (max_smem_per_threadblock / (16 * HEAD_DIM * sizeof(DTypeQ)) - num_frags_x * num_warps_x) /\n (2 * num_warps_z);\n\n // control num_frags_z for maximum warp occupancy\n DISPATCH_NUM_FRAGS_Z(min(max_num_frags_z_smem, max_num_frags_z_reg), num_frags_z, {\n if constexpr (is_invalid_configuration<pos_encoding_mode, DTypeKV, DTypeQKAccum>(\n num_frags_x, num_frags_y, num_frags_z, num_warps_x, num_warps_z)) {\n // Invalid configuration, skip\n std::ostringstream err_msg;\n err_msg << \"FlashInfer Internal Error: Invalid configuration : num_frags_x=\" << num_frags_x\n << \" num_frags_y=\" << num_frags_y << \" num_frags_z=\" << num_frags_z\n << \" num_warps_x=\" << num_warps_x << \" num_warps_z=\" << num_warps_z\n << \" please create an issue (https://github.com/flashinfer-ai/flashinfer/issues)\"\n \" and report the issue to the developers.\";\n throw std::invalid_argument(err_msg.str());\n } else {\n constexpr uint32_t num_threads = (num_warps_x * num_warps_z) * warp_size;\n constexpr uint32_t num_rows_per_cta = num_frags_x * num_warps_x * 16;\n auto kernel =\n SinglePrefillWithKVCacheKernel<LOGITS_POST_HOOK, MASK_MODE, pos_encoding_mode,\n num_frags_x, num_frags_y, num_frags_z, num_warps_x,\n num_warps_z, DTypeQ, DTypeKV, DTypeQKAccum, DTypeOut>;\n // TODO(Zihao): fix the following computation\n uint32_t smem_size = (num_frags_x * num_warps_x * sizeof(DTypeQ) +\n num_frags_z * num_warps_z * 2 * sizeof(DTypeQ)) *\n 16 * HEAD_DIM;\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n int num_blocks_per_sm = 0;\n int num_sm = 0;\n FLASHINFER_CUDA_CALL(\n cudaDeviceGetAttribute(&num_sm, cudaDevAttrMultiProcessorCount, dev_id));\n FLASHINFER_CUDA_CALL(cudaOccupancyMaxActiveBlocksPerMultiprocessor(\n &num_blocks_per_sm, kernel, num_threads, smem_size));\n uint32_t max_num_kv_chunks =\n (num_blocks_per_sm * num_sm) /\n (num_kv_heads * ceil_div(qo_len * group_size, num_rows_per_cta));\n uint32_t num_chunks;\n if (max_num_kv_chunks > 0) {\n uint32_t chunk_size = max(ceil_div(kv_len, max_num_kv_chunks), 256);\n num_chunks = ceil_div(kv_len, chunk_size);\n } else {\n num_chunks = 0;\n }\n\n if (num_chunks <= 1 || tmp == nullptr) {\n // Enough parallelism, do not split-kv\n bool partition_kv = false;\n void* args[] = {(void*)&q,\n (void*)&k,\n (void*)&v,\n (void*)&custom_mask,\n (void*)&o,\n (void*)&lse,\n (void*)&qo_len,\n (void*)&kv_len,\n (void*)&partition_kv,\n (void*)&group_size_fastdiv,\n (void*)&q_stride_n,\n (void*)&q_stride_h,\n (void*)&kv_stride_n,\n (void*)&kv_stride_h,\n (void*)&window_left,\n (void*)&logits_soft_cap,\n (void*)&sm_scale,\n (void*)&log2_rope_rcp_scale,\n (void*)&log2_rope_rcp_theta};\n dim3 nblks(ceil_div(qo_len * group_size, num_rows_per_cta), 1, num_kv_heads);\n dim3 nthrs(32, num_warps_x, num_warps_z);\n\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n } else {\n // Use cooperative groups to increase occupancy\n bool partition_kv = true;\n float* tmp_lse = (float*)(tmp + num_chunks * qo_len * num_qo_heads * HEAD_DIM);\n void* args[] = {(void*)&q,\n (void*)&k,\n (void*)&v,\n (void*)&custom_mask,\n (void*)&tmp,\n (void*)&tmp_lse,\n (void*)&qo_len,\n (void*)&kv_len,\n (void*)&partition_kv,\n (void*)&group_size_fastdiv,\n (void*)&q_stride_n,\n (void*)&q_stride_h,\n (void*)&kv_stride_n,\n (void*)&kv_stride_h,\n (void*)&window_left,\n (void*)&logits_soft_cap,\n (void*)&sm_scale,\n (void*)&log2_rope_rcp_scale,\n (void*)&log2_rope_rcp_theta};\n dim3 nblks(ceil_div(qo_len * group_size, num_rows_per_cta), num_chunks, num_kv_heads);\n dim3 nthrs(32, num_warps_x, num_warps_z);\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n FLASHINFER_CUDA_CALL(MergeStates(tmp, tmp_lse, o, lse, num_chunks, qo_len, num_qo_heads,\n HEAD_DIM, stream));\n }\n }\n })\n });\n return cudaSuccess;\n}\n\ntemplate <WarpLayout WARP_LAYOUT, uint32_t HEAD_DIM, LogitsPostHook LOGITS_POST_HOOK,\n PosEncodingMode pos_encoding_mode, bool ALLOW_FP16_QK_REDUCTION, MaskMode MASK_MODE,\n typename DTypeQ, typename DTypeKV, typename DTypeOut, typename IdType>\ncudaError_t BatchPrefillWithRaggedKVCacheDispatched(\n DTypeQ* q, IdType* request_indices, IdType* q_tile_indices, IdType* kv_tile_indices,\n IdType* q_indptr, DTypeKV* k, DTypeKV* v, IdType* kv_indptr, uint8_t* custom_mask,\n IdType* qk_indptr, IdType* q_offset, IdType* k_rope_pos_offset, IdType* o_indptr, DTypeOut* o,\n DTypeOut* tmp_v, float* tmp_s, float* lse, IdType* merge_indptr, bool* block_valid_mask,\n IdType* kv_chunk_size_ptr, uint32_t total_num_rows, uint32_t num_qo_heads,\n uint32_t padded_batch_size, uint32_t num_kv_heads, uint32_t q_stride_n, uint32_t q_stride_h,\n uint32_t kv_stride_n, uint32_t kv_stride_h, int32_t window_left, float logits_soft_cap,\n float sm_scale, float rope_scale, float rope_theta, cudaStream_t stream = nullptr) {\n const float log2_rope_rcp_scale = -std::log2f(rope_scale);\n const float log2_rope_rcp_theta = -std::log2f(rope_theta);\n constexpr uint32_t num_frags_x = get_num_frags_x<WARP_LAYOUT>();\n constexpr uint32_t num_warps_x = get_num_warps_x<WARP_LAYOUT>();\n constexpr uint32_t num_warps_z = get_num_warps_z<WARP_LAYOUT>();\n const uint32_t group_size = num_qo_heads / num_kv_heads;\n const uint_fastdiv group_size_fastdiv(group_size);\n\n if (padded_batch_size == 0) {\n // No request, skip\n // this won't happen in CUDAGraph mode because we fixed the padded_batch_size\n return cudaSuccess;\n }\n\n dim3 nblks(padded_batch_size, 1, num_kv_heads);\n dim3 nthrs(32, num_warps_x, num_warps_z);\n constexpr uint32_t num_frags_y = HEAD_DIM / 16;\n using DTypeQKAccum =\n typename std::conditional<ALLOW_FP16_QK_REDUCTION && std::is_same<DTypeQ, half>::value, half,\n float>::type;\n\n int dev_id = 0;\n FLASHINFER_CUDA_CALL(cudaGetDevice(&dev_id));\n int max_smem_per_sm = 0;\n FLASHINFER_CUDA_CALL(cudaDeviceGetAttribute(&max_smem_per_sm,\n cudaDevAttrMaxSharedMemoryPerMultiprocessor, dev_id));\n // we expect each sm execute two threadblocks\n // TODO(Zihao): fix the following computation\n const int num_ctas_per_sm = max_smem_per_sm > (16 * HEAD_DIM * sizeof(DTypeQ) * 16) ? 2 : 1;\n const int max_smem_per_threadblock = max_smem_per_sm / num_ctas_per_sm;\n\n const uint32_t max_num_frags_z_reg =\n (HEAD_DIM >= 128 && num_frags_x == 2 && pos_encoding_mode == PosEncodingMode::kRoPELlama &&\n !ALLOW_FP16_QK_REDUCTION)\n ? 2\n : (8 / num_frags_x);\n // TODO(Zihao): fix the following computation\n const uint32_t max_num_frags_z_smem =\n (max_smem_per_threadblock / (16 * HEAD_DIM * sizeof(DTypeQ)) - num_frags_x * num_warps_x) /\n (2 * num_warps_z);\n\n DISPATCH_NUM_FRAGS_Z(min(max_num_frags_z_smem, max_num_frags_z_reg), num_frags_z, {\n if constexpr (is_invalid_configuration<pos_encoding_mode, DTypeKV, DTypeQKAccum>(\n num_frags_x, num_frags_y, num_frags_z, num_warps_x, num_warps_z)) {\n // Invalid configuration, skip\n std::ostringstream err_msg;\n err_msg << \"FlashInfer Internal Error: Invalid configuration : num_frags_x=\" << num_frags_x\n << \" num_frags_y=\" << num_frags_y << \" num_frags_z=\" << num_frags_z\n << \" num_warps_x=\" << num_warps_x << \" num_warps_z=\" << num_warps_z\n << \" please create an issue (https://github.com/flashinfer-ai/flashinfer/issues)\"\n \" and report the issue to the developers.\";\n throw std::invalid_argument(err_msg.str());\n } else {\n // TODO(Zihao): fix the following computation\n uint32_t smem_size = (num_frags_x * num_warps_x * sizeof(DTypeQ) +\n num_frags_z * num_warps_z * 2 * sizeof(DTypeQ)) *\n 16 * HEAD_DIM;\n auto kernel = BatchPrefillWithRaggedKVCacheKernel<\n LOGITS_POST_HOOK, MASK_MODE, pos_encoding_mode, num_frags_x, num_frags_y, num_frags_z,\n num_warps_x, num_warps_z, DTypeQ, DTypeKV, DTypeQKAccum, DTypeOut, IdType>;\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n if (tmp_v == nullptr) {\n // do not partition kv\n bool partition_kv = false;\n\n void* args[] = {(void*)&q,\n (void*)&request_indices,\n (void*)&q_tile_indices,\n (void*)&kv_tile_indices,\n (void*)&q_indptr,\n (void*)&k,\n (void*)&v,\n (void*)&kv_indptr,\n (void*)&custom_mask,\n (void*)&qk_indptr,\n (void*)&q_offset,\n (void*)&k_rope_pos_offset,\n (void*)&o_indptr,\n (void*)&o,\n (void*)&lse,\n (void*)&block_valid_mask,\n (void*)&kv_chunk_size_ptr,\n (void*)&partition_kv,\n (void*)&group_size_fastdiv,\n (void*)&q_stride_n,\n (void*)&q_stride_h,\n (void*)&kv_stride_n,\n (void*)&kv_stride_h,\n (void*)&window_left,\n (void*)&logits_soft_cap,\n (void*)&sm_scale,\n (void*)&log2_rope_rcp_scale,\n (void*)&log2_rope_rcp_theta};\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n } else {\n // partition kv\n bool partition_kv = true;\n void* args[] = {(void*)&q,\n (void*)&request_indices,\n (void*)&q_tile_indices,\n (void*)&kv_tile_indices,\n (void*)&q_indptr,\n (void*)&k,\n (void*)&v,\n (void*)&kv_indptr,\n (void*)&custom_mask,\n (void*)&qk_indptr,\n (void*)&q_offset,\n (void*)&k_rope_pos_offset,\n (void*)&o_indptr,\n (void*)&tmp_v,\n (void*)&tmp_s,\n (void*)&block_valid_mask,\n (void*)&kv_chunk_size_ptr,\n (void*)&partition_kv,\n (void*)&group_size_fastdiv,\n (void*)&q_stride_n,\n (void*)&q_stride_h,\n (void*)&kv_stride_n,\n (void*)&kv_stride_h,\n (void*)&window_left,\n (void*)&logits_soft_cap,\n (void*)&sm_scale,\n (void*)&log2_rope_rcp_scale,\n (void*)&log2_rope_rcp_theta};\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n FLASHINFER_CUDA_CALL(VariableLengthMergeStates(\n tmp_v, tmp_s, merge_indptr, o, lse, total_num_rows, num_qo_heads, HEAD_DIM, stream));\n }\n }\n });\n return cudaSuccess;\n}\n\ntemplate <PageStorage page_storage, WarpLayout WARP_LAYOUT, uint32_t HEAD_DIM,\n LogitsPostHook LOGITS_POST_HOOK, PosEncodingMode pos_encoding_mode,\n bool ALLOW_FP16_QK_REDUCTION, MaskMode MASK_MODE, typename DTypeQ, typename DTypeKV,\n typename DTypeOut, typename IdType>\ncudaError_t BatchPrefillWithPagedKVCacheDispatched(\n DTypeQ* q, IdType* request_indices, IdType* q_tile_indices, IdType* kv_tile_indices,\n IdType* q_indptr, IdType* q_offset, paged_kv_t<page_storage, DTypeKV, IdType> paged_kv,\n uint8_t* custom_mask, IdType* qk_indptr, IdType* o_indptr, DTypeOut* o, DTypeOut* tmp_v,\n float* tmp_s, float* lse, IdType* merge_indptr, bool* block_valid_mask,\n IdType* kv_chunk_size_ptr, uint32_t total_num_rows, uint32_t num_qo_heads,\n uint32_t padded_batch_size, int32_t window_left, float logits_soft_cap, float sm_scale,\n float rope_scale, float rope_theta, cudaStream_t stream) {\n const float log2_rope_rcp_scale = -std::log2f(rope_scale);\n const float log2_rope_rcp_theta = -std::log2f(rope_theta);\n constexpr uint32_t num_frags_x = get_num_frags_x<WARP_LAYOUT>();\n constexpr uint32_t num_warps_x = get_num_warps_x<WARP_LAYOUT>();\n constexpr uint32_t num_warps_z = get_num_warps_z<WARP_LAYOUT>();\n const uint32_t num_kv_heads = paged_kv.num_heads;\n const uint32_t group_size = num_qo_heads / num_kv_heads;\n const uint_fastdiv group_size_fastdiv(group_size);\n\n if (padded_batch_size == 0) {\n // No request, skip\n // this won't happen in CUDAGraph mode because we fixed the padded_batch_size\n return cudaSuccess;\n }\n\n dim3 nblks(padded_batch_size, 1, num_kv_heads);\n dim3 nthrs(32, num_warps_x, num_warps_z);\n\n constexpr uint32_t num_frags_y = HEAD_DIM / 16;\n using DTypeQKAccum =\n typename std::conditional<ALLOW_FP16_QK_REDUCTION && std::is_same<DTypeQ, half>::value, half,\n float>::type;\n\n int dev_id = 0;\n FLASHINFER_CUDA_CALL(cudaGetDevice(&dev_id));\n int max_smem_per_sm = 0;\n FLASHINFER_CUDA_CALL(cudaDeviceGetAttribute(&max_smem_per_sm,\n cudaDevAttrMaxSharedMemoryPerMultiprocessor, dev_id));\n // we expect each sm execute two threadblocks\n // TODO(Zihao): fix the following computation\n const int num_ctas_per_sm = max_smem_per_sm > (16 * HEAD_DIM * sizeof(DTypeQ) * 16) ? 2 : 1;\n const int max_smem_per_threadblock = max_smem_per_sm / num_ctas_per_sm;\n\n const uint32_t max_num_frags_z_reg =\n (HEAD_DIM >= 128 && num_frags_x == 2 && pos_encoding_mode == PosEncodingMode::kRoPELlama &&\n !ALLOW_FP16_QK_REDUCTION)\n ? 2\n : (8 / num_frags_x);\n // TODO(Zihao): fix the following computation\n const uint32_t max_num_frags_z_smem =\n (max_smem_per_threadblock / (16 * HEAD_DIM * sizeof(DTypeQ)) - num_frags_x * num_warps_x) /\n (2 * num_warps_z);\n\n DISPATCH_NUM_FRAGS_Z(min(max_num_frags_z_smem, max_num_frags_z_reg), num_frags_z, {\n if constexpr (is_invalid_configuration<pos_encoding_mode, DTypeKV, DTypeQKAccum>(\n num_frags_x, num_frags_y, num_frags_z, num_warps_x, num_warps_z)) {\n // Invalid configuration, skip\n std::ostringstream err_msg;\n err_msg << \"FlashInfer Internal Error: Invalid configuration : num_frags_x=\" << num_frags_x\n << \" num_frags_y=\" << num_frags_y << \" num_frags_z=\" << num_frags_z\n << \" num_warps_x=\" << num_warps_x << \" num_warps_z=\" << num_warps_z\n << \" please create an issue (https://github.com/flashinfer-ai/flashinfer/issues)\"\n \" and report the issue to the developers.\";\n throw std::invalid_argument(err_msg.str());\n } else {\n // TODO(Zihao): fix the following computation\n uint32_t smem_size = (num_frags_x * num_warps_x * sizeof(DTypeQ) +\n num_frags_z * num_warps_z * 2 * sizeof(DTypeQ)) *\n 16 * HEAD_DIM;\n auto kernel = BatchPrefillWithPagedKVCacheKernel<\n LOGITS_POST_HOOK, MASK_MODE, pos_encoding_mode, num_frags_x, num_frags_y, num_frags_z,\n num_warps_x, num_warps_z, page_storage, DTypeQ, DTypeKV, DTypeQKAccum, DTypeOut, IdType>;\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n if (tmp_v == nullptr) {\n // do not partition kv\n bool partition_kv = false;\n void* args[] = {(void*)&request_indices,\n (void*)&q_tile_indices,\n (void*)&kv_tile_indices,\n (void*)&q,\n (void*)&paged_kv,\n (void*)&q_indptr,\n (void*)&custom_mask,\n (void*)&qk_indptr,\n (void*)&q_offset,\n (void*)&o_indptr,\n (void*)&o,\n (void*)&lse,\n (void*)&block_valid_mask,\n (void*)&kv_chunk_size_ptr,\n (void*)&partition_kv,\n (void*)&group_size_fastdiv,\n (void*)&window_left,\n (void*)&logits_soft_cap,\n (void*)&sm_scale,\n (void*)&log2_rope_rcp_scale,\n (void*)&log2_rope_rcp_theta};\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n } else {\n bool partition_kv = true;\n void* args[] = {(void*)&request_indices,\n (void*)&q_tile_indices,\n (void*)&kv_tile_indices,\n (void*)&q,\n (void*)&paged_kv,\n (void*)&q_indptr,\n (void*)&custom_mask,\n (void*)&qk_indptr,\n (void*)&q_offset,\n (void*)&o_indptr,\n (void*)&tmp_v,\n (void*)&tmp_s,\n (void*)&block_valid_mask,\n (void*)&kv_chunk_size_ptr,\n (void*)&partition_kv,\n (void*)&group_size_fastdiv,\n (void*)&window_left,\n (void*)&logits_soft_cap,\n (void*)&sm_scale,\n (void*)&log2_rope_rcp_scale,\n (void*)&log2_rope_rcp_theta};\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n FLASHINFER_CUDA_CALL(VariableLengthMergeStates(\n tmp_v, tmp_s, merge_indptr, o, lse, total_num_rows, num_qo_heads, HEAD_DIM, stream));\n }\n }\n });\n return cudaSuccess;\n}\n\n} // namespace flashinfer\n\n#endif // FLASHINFER_PREFILL_CUH_\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"swap after dequantize.\n"},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1299,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"0d618712faff20a84bbd513d02ac01e16be19306"},"date":{"kind":"string","value":"2024-08-17T23:26:02-07:00"},"pr_number":{"kind":"number","value":453,"string":"453"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/453"},"title":{"kind":"string","value":"perf: slight optimization on f16->f8 fragment layout swizzling (#453)"},"message":{"kind":"string","value":"perf: slight optimization on f16->f8 fragment layout swizzling (#453)\n\nswap after dequantize."},"path":{"kind":"string","value":"include/flashinfer/frag_layout_swizzle.cuh"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * Copyright (c) 2024 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_FRAG_LAYOUT_SWIZZLE_CUH_\n#define FLASHINFER_FRAG_LAYOUT_SWIZZLE_CUH_\n\n#include <cuda_runtime.h>\n\n#include <cstdint>\n\n__device__ __forceinline__ uint32_t frag_layout_swizzle_16b_to_8b(uint32_t x) {\n uint32_t tmp = __shfl_xor_sync(0xffffffff, x, 0x1);\n x = __byte_perm(x, tmp, ((threadIdx.x & 0x1) == 0) ? 0x5410 : 0x3276);\n tmp = __shfl_xor_sync(0xffffffff, x, 0x2);\n x = __byte_perm(x, tmp, ((threadIdx.x & 0x2) == 0) ? 0x5410 : 0x3276);\n return x;\n}\n\n__device__ __forceinline__ uint32_t frag_layout_swizzle_16b_to_8b_trans(uint32_t x) {\n x = __byte_perm(x, x, 0x3120);\n uint32_t tmp = __shfl_xor_sync(0xffffffff, x, 0x4);\n x = __byte_perm(x, tmp, ((threadIdx.x & 0x4) == 0) ? 0x5410 : 0x3276);\n tmp = __shfl_xor_sync(0xffffffff, x, 0x8);\n x = __byte_perm(x, tmp, ((threadIdx.x & 0x8) == 0) ? 0x5410 : 0x3276);\n tmp = __shfl_xor_sync(0xffffffff, x, 0x10);\n x = __byte_perm(x, tmp, ((threadIdx.x & 0x10) == 0) ? 0x5410 : 0x3276);\n return x;\n}\n\n__device__ __forceinline__ void bfly_exch(uint32_t& a, uint32_t& b) {\n uint32_t tmp = __byte_perm(a, b, 0x5410);\n uint32_t tmp2 = __byte_perm(a, b, 0x7632);\n a = tmp;\n b = tmp2;\n}\n\n#endif // FLASHINFER_FRAG_LAYOUT_SWIZZLE_CUH_\n"},"after_code":{"kind":"string","value":"/*\n * Copyright (c) 2024 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_FRAG_LAYOUT_SWIZZLE_CUH_\n#define FLASHINFER_FRAG_LAYOUT_SWIZZLE_CUH_\n\n#include <cuda_runtime.h>\n\n#include <cstdint>\n\n__device__ __forceinline__ uint32_t frag_layout_swizzle_16b_to_8b(uint32_t x) {\n uint32_t tmp = __shfl_xor_sync(0xffffffff, x, 0x1);\n x = __byte_perm(x, tmp, ((threadIdx.x & 0x1) == 0) ? 0x5410 : 0x3276);\n tmp = __shfl_xor_sync(0xffffffff, x, 0x2);\n x = __byte_perm(x, tmp, ((threadIdx.x & 0x2) == 0) ? 0x5410 : 0x3276);\n return x;\n}\n\n__device__ __forceinline__ uint32_t frag_layout_swizzle_16b_to_8b_trans(uint32_t x) {\n x = __byte_perm(x, x, 0x3120);\n uint32_t tmp = __shfl_xor_sync(0xffffffff, x, 0x4);\n x = __byte_perm(x, tmp, ((threadIdx.x & 0x4) == 0) ? 0x5410 : 0x3276);\n tmp = __shfl_xor_sync(0xffffffff, x, 0x8);\n x = __byte_perm(x, tmp, ((threadIdx.x & 0x8) == 0) ? 0x5410 : 0x3276);\n tmp = __shfl_xor_sync(0xffffffff, x, 0x10);\n x = __byte_perm(x, tmp, ((threadIdx.x & 0x10) == 0) ? 0x5410 : 0x3276);\n return x;\n}\n\n#endif // FLASHINFER_FRAG_LAYOUT_SWIZZLE_CUH_\n"},"diff":{"kind":"string","value":"--- include/flashinfer/frag_layout_swizzle.cuh\n+++ include/flashinfer/frag_layout_swizzle.cuh\n@@ -39,11 +39,4 @@\n return x;\n }\n \n-__device__ __forceinline__ void bfly_exch(uint32_t& a, uint32_t& b) {\n- uint32_t tmp = __byte_perm(a, b, 0x5410);\n- uint32_t tmp2 = __byte_perm(a, b, 0x7632);\n- a = tmp;\n- b = tmp2;\n-}\n-\n #endif // FLASHINFER_FRAG_LAYOUT_SWIZZLE_CUH_"},"lines_added":{"kind":"number","value":0,"string":"0"},"lines_removed":{"kind":"number","value":7,"string":"7"},"files_in_commit":{"kind":"number","value":3,"string":"3"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (include/flashinfer/frag_layout_swizzle.cuh).\n\nGoal: perf: slight optimization on f16->f8 fragment layout swizzling\nTarget hardware: unspecified\nTarget models: unspecified\n\nCurrent file:\n```cuda\n/*\n * Copyright (c) 2024 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_FRAG_LAYOUT_SWIZZLE_CUH_\n#define FLASHINFER_FRAG_LAYOUT_SWIZZLE_CUH_\n\n#include <cuda_runtime.h>\n\n#include <cstdint>\n\n__device__ __forceinline__ uint32_t frag_layout_swizzle_16b_to_8b(uint32_t x) {\n uint32_t tmp = __shfl_xor_sync(0xffffffff, x, 0x1);\n x = __byte_perm(x, tmp, ((threadIdx.x & 0x1) == 0) ? 0x5410 : 0x3276);\n tmp = __shfl_xor_sync(0xffffffff, x, 0x2);\n x = __byte_perm(x, tmp, ((threadIdx.x & 0x2) == 0) ? 0x5410 : 0x3276);\n return x;\n}\n\n__device__ __forceinline__ uint32_t frag_layout_swizzle_16b_to_8b_trans(uint32_t x) {\n x = __byte_perm(x, x, 0x3120);\n uint32_t tmp = __shfl_xor_sync(0xffffffff, x, 0x4);\n x = __byte_perm(x, tmp, ((threadIdx.x & 0x4) == 0) ? 0x5410 : 0x3276);\n tmp = __shfl_xor_sync(0xffffffff, x, 0x8);\n x = __byte_perm(x, tmp, ((threadIdx.x & 0x8) == 0) ? 0x5410 : 0x3276);\n tmp = __shfl_xor_sync(0xffffffff, x, 0x10);\n x = __byte_perm(x, tmp, ((threadIdx.x & 0x10) == 0) ? 0x5410 : 0x3276);\n return x;\n}\n\n__device__ __forceinline__ void bfly_exch(uint32_t& a, uint32_t& b) {\n uint32_t tmp = __byte_perm(a, b, 0x5410);\n uint32_t tmp2 = __byte_perm(a, b, 0x7632);\n a = tmp;\n b = tmp2;\n}\n\n#endif // FLASHINFER_FRAG_LAYOUT_SWIZZLE_CUH_\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"swap after dequantize.\n"},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}}],"truncated":false,"partial":false},"paginationData":{"pageIndex":12,"numItemsPerPage":100,"numTotalItems":1365,"offset":1200,"length":100}},"jwt":"eyJhbGciOiJFZERTQSIsImtpZCI6IjVHZDBvd0g5MTM2eDZjc1FvbE1zcktNWUZoRVFoUm5PVVVybEpjOUhaUEEifQ.eyJyZWFkIjp0cnVlLCJwZXJtaXNzaW9ucyI6eyJyZXBvLmNvbnRlbnQucmVhZCI6dHJ1ZX0sInJlcG9JZHMiOlsiNmFkYjE3ZGJmZDFkOTk5NTg0YWY2M2I5Il0sImlhdCI6MTc5NDE1MDk4NSwianRpIjoiZWM4MDdjNmYtOWU1MC00MTMzLThhYzAtOThkMWE3OTYyMzhjIiwic3ViIjoiL2RhdGFzZXRzL2d1eWNodWsva2VybmVsLW9wdC1ybCIsImV4cCI6MTc5NDE1NDU4NSwiaXNzIjoiaHR0cHM6Ly9odWdnaW5nZmFjZS5jbyJ9.ox4IccH9I01KDh2N508X-Qn2iipceVZaUK-7phIdDBPiNX8s5WxKt2jeStLGK21jY7rSKEKUdCTyUB8esNsrDg","displayUrls":true,"splitSizeSummaries":[{"config":"kernel_commits","split":"train","numRows":1365,"numBytesParquet":42213599},{"config":"kernel_commits","split":"test","numRows":152,"numBytesParquet":5808547},{"config":"tuned_configs","split":"train","numRows":17561,"numBytesParquet":24732360},{"config":"tuned_configs","split":"test","numRows":1726,"numBytesParquet":2111842}]},"discussionsStats":{"closed":0,"open":0,"total":0},"fullWidth":true,"hasGatedAccess":true,"hasFullAccess":true,"isEmbedded":false,"savedQueries":{"community":[],"user":[]}}">
repo stringclasses 3
values | commit stringlengths 40 40 | date stringdate 2023-04-02 02:30:17-0500 2026-10-18 07:42:16-0500 | pr_number int64 20 61.9k ⌀ | pr_url stringlengths 44 53 ⌀ | title stringlengths 8 263 | message stringlengths 8 8k | path stringlengths 10 155 | language stringclasses 4
values | license stringclasses 4
values | before_code stringlengths 160 118k | after_code stringlengths 340 120k | diff stringlengths 149 51k | lines_added int64 0 729 | lines_removed int64 0 488 | files_in_commit int64 1 10 | models_mentioned listlengths 0 4 | hardware_mentioned listlengths 0 16 | speedup_claims listlengths 0 10 | prompt stringlengths 569 119k | pr_body stringlengths 0 24k | gains stringlengths 2 197k | kernel_speedup float64 0.78 150 ⌀ | e2e_speedup float64 0.76 136 ⌀ |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
flashinfer | 4aed50cfa663708fab3931b2d5fcab6adc5e1f55 | 2025-11-16T17:40:45-05:00 | 2,095 | https://github.com/flashinfer-ai/flashinfer/pull/2095 | perf: enable pdl for cutlass fp4 gemm (#2095) | perf: enable pdl for cutlass fp4 gemm (#2095)
<!-- .github/pull_request_template.md -->
## 📌 Description
The `enablePDL` flag is set to false, this PR turned them on.
Set to true for both because sm_100 and sm_120 should have support of
pdl.
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull R... | include/flashinfer/gemm/fp4_gemm_template_sm100.h | cpp | Apache-2.0 | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- include/flashinfer/gemm/fp4_gemm_template_sm100.h
+++ include/flashinfer/gemm/fp4_gemm_template_sm100.h
@@ -273,7 +273,7 @@
std::string(cutlassGetStatusString(initStatus)); \
throw std::runtime_error("[FP4 gemm Runner] " + errMsg); ... | 1 | 1 | 2 | [] | [
"SM100",
"SM120"
] | [] | Optimize this cpp kernel file from flashinfer (include/flashinfer/gemm/fp4_gemm_template_sm100.h).
Goal: perf: enable pdl for cutlass fp4 gemm
Target hardware: SM100, SM120
Target models: unspecified
Current file:
```cpp
/*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the... | <!-- .github/pull_request_template.md -->
## 📌 Description
The `enablePDL` flag is set to false, this PR turned them on.
Set to true for both because sm_100 and sm_120 should have support of pdl.
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull Request Checklist
Thank you for contributing to... | [] | null | null |
flashinfer | 4aed50cfa663708fab3931b2d5fcab6adc5e1f55 | 2025-11-16T17:40:45-05:00 | 2,095 | https://github.com/flashinfer-ai/flashinfer/pull/2095 | perf: enable pdl for cutlass fp4 gemm (#2095) | perf: enable pdl for cutlass fp4 gemm (#2095)
<!-- .github/pull_request_template.md -->
## 📌 Description
The `enablePDL` flag is set to false, this PR turned them on.
Set to true for both because sm_100 and sm_120 should have support of
pdl.
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull R... | include/flashinfer/gemm/fp4_gemm_template_sm120.h | cpp | Apache-2.0 | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- include/flashinfer/gemm/fp4_gemm_template_sm120.h
+++ include/flashinfer/gemm/fp4_gemm_template_sm120.h
@@ -257,7 +257,7 @@
std::string(cutlass::cutlassGetStatusString(initStatus)); \
throw std::runtime_error("[FP4 gemm Runner] " + errMsg); ... | 1 | 1 | 2 | [] | [
"SM100",
"SM120"
] | [] | Optimize this cpp kernel file from flashinfer (include/flashinfer/gemm/fp4_gemm_template_sm120.h).
Goal: perf: enable pdl for cutlass fp4 gemm
Target hardware: SM100, SM120
Target models: unspecified
Current file:
```cpp
/*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the... | <!-- .github/pull_request_template.md -->
## 📌 Description
The `enablePDL` flag is set to false, this PR turned them on.
Set to true for both because sm_100 and sm_120 should have support of pdl.
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull Request Checklist
Thank you for contributing to... | [] | null | null |
flashinfer | cce4952fdd41b353325e11d99e1fc0b0737961ff | 2025-11-14T22:43:40+01:00 | 2,092 | https://github.com/flashinfer-ai/flashinfer/pull/2092 | perf: TRT-LLM Gen finalize kernel optimization (#2092) | perf: TRT-LLM Gen finalize kernel optimization (#2092)
<!-- .github/pull_request_template.md -->
## 📌 Description
- Small optimization for TRT-LLM Gen MoE finalize kernel
TopK=8, NumExperts=128, HiddenSize=4096
| BS | Baseline, us | Optimized, us | Speed-up |
| ------------- | ------------- | ------------- | ----... | csrc/trtllm_fused_moe_dev_kernel.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/trtllm_fused_moe_dev_kernel.cu
+++ csrc/trtllm_fused_moe_dev_kernel.cu
@@ -672,11 +672,128 @@
// Final kernel to unpermute and scale
// This kernel unpermutes the original data, does the k-way reduction and performs the final skip
// connection.
+/////////////////////////////////////////////////////////////... | 172 | 23 | 2 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (csrc/trtllm_fused_moe_dev_kernel.cu).
Goal: perf: TRT-LLM Gen finalize kernel optimization
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apa... | <!-- .github/pull_request_template.md -->
## 📌 Description
- Small optimization for TRT-LLM Gen MoE finalize kernel
TopK=8, NumExperts=128, HiddenSize=4096
| BS | Baseline, us | Optimized, us | Speed-up |
| ------------- | ------------- | ------------- | ------------- |
| 256 | 11 | 6 | 1.83 |
| 512 | 12 | 7 ... | [] | null | null |
flashinfer | cce4952fdd41b353325e11d99e1fc0b0737961ff | 2025-11-14T22:43:40+01:00 | 2,092 | https://github.com/flashinfer-ai/flashinfer/pull/2092 | perf: TRT-LLM Gen finalize kernel optimization (#2092) | perf: TRT-LLM Gen finalize kernel optimization (#2092)
<!-- .github/pull_request_template.md -->
## 📌 Description
- Small optimization for TRT-LLM Gen MoE finalize kernel
TopK=8, NumExperts=128, HiddenSize=4096
| BS | Baseline, us | Optimized, us | Speed-up |
| ------------- | ------------- | ------------- | ----... | include/flashinfer/trtllm/fused_moe/DevKernel.h | cpp | Apache-2.0 | /*
* Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- include/flashinfer/trtllm/fused_moe/DevKernel.h
+++ include/flashinfer/trtllm/fused_moe/DevKernel.h
@@ -116,27 +116,36 @@
FLASHINFER_WARN("Unsupported dtypeElt"); \
}
-#define LAUNCH_EXPW(data, kernel, numBlocks, numThreads, smemSize, stream) ... | 32 | 22 | 2 | [] | [] | [] | Optimize this cpp kernel file from flashinfer (include/flashinfer/trtllm/fused_moe/DevKernel.h).
Goal: perf: TRT-LLM Gen finalize kernel optimization
Target hardware: unspecified
Target models: unspecified
Current file:
```cpp
/*
* Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved.
*
* Licensed und... | <!-- .github/pull_request_template.md -->
## 📌 Description
- Small optimization for TRT-LLM Gen MoE finalize kernel
TopK=8, NumExperts=128, HiddenSize=4096
| BS | Baseline, us | Optimized, us | Speed-up |
| ------------- | ------------- | ------------- | ------------- |
| 256 | 11 | 6 | 1.83 |
| 512 | 12 | 7 ... | [] | null | null |
flashinfer | ba011d15ed44d32c9c226fd1d66746707233729c | 2025-11-08T07:14:05+01:00 | 2,063 | https://github.com/flashinfer-ai/flashinfer/pull/2063 | perf: TRT-LLM MoE Block-FP8 activation optimization (#2063) | perf: TRT-LLM MoE Block-FP8 activation optimization (#2063)
<!-- .github/pull_request_template.md -->
## 📌 Description
- Small optimization to the activation kernel for block-FP8 MoE for
large batch size.
| BS | Baseline, us | Optimized, us |
| ------------- | ------------- | ------------- |
| 1 | 2.4 | 2.1 |
| ... | csrc/trtllm_fused_moe_dev_kernel.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/trtllm_fused_moe_dev_kernel.cu
+++ csrc/trtllm_fused_moe_dev_kernel.cu
@@ -19,6 +19,7 @@
#include <cutlass/numeric_conversion.h>
#include <cutlass/numeric_types.h>
+#include <algorithm>
#include <cub/cub.cuh>
#include <cuda/functional>
#include <cuda/std/functional>
@@ -26,6 +27,7 @@
#include "flashi... | 233 | 52 | 2 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (csrc/trtllm_fused_moe_dev_kernel.cu).
Goal: perf: TRT-LLM MoE Block-FP8 activation optimization
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under th... | <!-- .github/pull_request_template.md -->
## 📌 Description
- Small optimization to the activation kernel for block-FP8 MoE for large batch size.
| BS | Baseline, us | Optimized, us |
| ------------- | ------------- | ------------- |
| 1 | 2.4 | 2.1 |
| 32 | 3.5 | 2.6 |
| 256 | 21.7 | 8.7 |
| 1024 | 84.4 | 2... | [] | null | null |
flashinfer | ba011d15ed44d32c9c226fd1d66746707233729c | 2025-11-08T07:14:05+01:00 | 2,063 | https://github.com/flashinfer-ai/flashinfer/pull/2063 | perf: TRT-LLM MoE Block-FP8 activation optimization (#2063) | perf: TRT-LLM MoE Block-FP8 activation optimization (#2063)
<!-- .github/pull_request_template.md -->
## 📌 Description
- Small optimization to the activation kernel for block-FP8 MoE for
large batch size.
| BS | Baseline, us | Optimized, us |
| ------------- | ------------- | ------------- |
| 1 | 2.4 | 2.1 |
| ... | include/flashinfer/trtllm/fused_moe/DevKernel.h | cpp | Apache-2.0 | /*
* Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- include/flashinfer/trtllm/fused_moe/DevKernel.h
+++ include/flashinfer/trtllm/fused_moe/DevKernel.h
@@ -90,6 +90,32 @@
FLASHINFER_WARN("Unsupported dtypeElt"); \
}
+#define LAUNCH_NUM_TOKENS_PER_CTA(data, type, numTokensPerCta, kernel, numBlocks, numTh... | 28 | 1 | 2 | [] | [] | [] | Optimize this cpp kernel file from flashinfer (include/flashinfer/trtllm/fused_moe/DevKernel.h).
Goal: perf: TRT-LLM MoE Block-FP8 activation optimization
Target hardware: unspecified
Target models: unspecified
Current file:
```cpp
/*
* Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved.
*
* License... | <!-- .github/pull_request_template.md -->
## 📌 Description
- Small optimization to the activation kernel for block-FP8 MoE for large batch size.
| BS | Baseline, us | Optimized, us |
| ------------- | ------------- | ------------- |
| 1 | 2.4 | 2.1 |
| 32 | 3.5 | 2.6 |
| 256 | 21.7 | 8.7 |
| 1024 | 84.4 | 2... | [] | null | null |
flashinfer | f588d96af1d27bd8714b63e40ccc2955d92a5593 | 2025-11-07T11:50:59-08:00 | 2,058 | https://github.com/flashinfer-ai/flashinfer/pull/2058 | perf: Optimize helper max/minmax function in sampling.cuh (#2058) | perf: Optimize helper max/minmax function in sampling.cuh (#2058)
<!-- .github/pull_request_template.md -->
## 📌 Description
Apply optimizations similar to #2044 to max/min functions.
<!-- What does this PR do? Briefly describe the changes and why they’re
needed. -->
## 🔍 Related Issues
<!-- Link any related is... | include/flashinfer/sampling.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/sampling.cuh
+++ include/flashinfer/sampling.cuh
@@ -249,27 +249,31 @@
TempStorage& temp_storage) {
const uint32_t tx = threadIdx.x;
vec_t<float, VEC_SIZE> in_data_vec;
- float max_val = -cuda::std::numeric_limits<float>::... | 28 | 23 | 1 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/sampling.cuh).
Goal: perf: Optimize helper max/minmax function in sampling.cuh
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version ... | <!-- .github/pull_request_template.md -->
## 📌 Description
Apply optimizations similar to #2044 to max/min functions.
`top_p_renorm_probs`, `top_k_renorm_probs`, and `top_k_mask_logits` see 14%, 7%, and 19% speedups on B200 (logs from `bench_sampling.py`: [bench_sampling_before.txt](https://github.com/user-attachme... | [{"scope": "kernel", "hardware": "B200", "model": null, "shape": null, "batch_size": null, "metric": "latency", "unit": null, "higher_is_better": false, "baseline": null, "optimized": null, "stated_speedup": 1.14, "speedup": 1.14}, {"scope": "kernel", "hardware": "B200", "model": null, "shape": null, "batch_size": null... | 1.14 | null |
flashinfer | adcc5dd41037bbd77a68800b15f5e0235c2975ac | 2025-11-06T16:58:30-08:00 | 2,044 | https://github.com/flashinfer-ai/flashinfer/pull/2044 | perf: improve sampling/mask/softmax performance (part 1/2) (#2044) | perf: improve sampling/mask/softmax performance (part 1/2) (#2044)
<!-- .github/pull_request_template.md -->
## 📌 Description
This is the first part of the performance improvement PR for
sampling/mask/softmax operator, in this PR, we defer the cross thread
reduction till the end of the loop (similar to how FA2 hand... | include/flashinfer/sampling.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/sampling.cuh
+++ include/flashinfer/sampling.cuh
@@ -333,6 +333,7 @@
float running_max = -cuda::std::numeric_limits<float>::infinity();
float running_denominator = 0.0f;
+ float threadlocal_running_denominator = 0.0f;
#if (__CUDACC_VER_MAJOR__ >= 12 && defined(__CUDA_ARCH__) && (__CUD... | 161 | 148 | 1 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/sampling.cuh).
Goal: perf: improve sampling/mask/softmax performance (part 1/2)
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version... | <!-- .github/pull_request_template.md -->
## 📌 Description
This is the first part of the performance improvement PR for sampling/mask/softmax operator, in this PR, we defer the cross thread reduction till the end of the loop (similar to how FA2 handles denominator) to reduce the number of shuffling and thread sync i... | [] | null | null |
flashinfer | 2580610b46ba5fa45532256ca77730acba2f5a03 | 2025-11-04T22:07:19-08:00 | 2,025 | https://github.com/flashinfer-ai/flashinfer/pull/2025 | perf: Speed up fp4 quantization for small batch with swizzling for cutlass MoE (#2025) | perf: Speed up fp4 quantization for small batch with swizzling for cutlass MoE (#2025)
<!-- .github/pull_request_template.md -->
## 📌 Description
Performance optimization for `fp4_quantize()` function. The performance
issue was raised in issues #1734 and #2021
Observed behavior was slow performance when `is_sf_swi... | csrc/nv_internal/cpp/kernels/quantization.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/nv_internal/cpp/kernels/quantization.cu
+++ csrc/nv_internal/cpp/kernels/quantization.cu
@@ -71,6 +71,21 @@
////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////... | 21 | 3 | 2 | [] | [] | [
"10×"
] | Optimize this cuda kernel file from flashinfer (csrc/nv_internal/cpp/kernels/quantization.cu).
Goal: perf: Speed up fp4 quantization for small batch with swizzling for cutlass MoE
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All righ... | <!-- .github/pull_request_template.md -->
## 📌 Description
Performance optimization for `fp4_quantize()` function. The performance issue was raised in issues #1734 and #2021
Observed behavior was slow performance when `is_sf_swizzled_layout=True` (as opposed to False). Root cause of the issue was
* Excessive Padd... | [{"scope": "kernel", "hardware": null, "model": null, "shape": "N=5120", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 71.52, "optimized": 3.456, "stated_speedup": null, "speedup": 20.6944}, {"scope": "kernel", "hardware": null, "model": null, "shape": "N=5120", "batch_size"... | 1.68 | null |
flashinfer | 2580610b46ba5fa45532256ca77730acba2f5a03 | 2025-11-04T22:07:19-08:00 | 2,025 | https://github.com/flashinfer-ai/flashinfer/pull/2025 | perf: Speed up fp4 quantization for small batch with swizzling for cutlass MoE (#2025) | perf: Speed up fp4 quantization for small batch with swizzling for cutlass MoE (#2025)
<!-- .github/pull_request_template.md -->
## 📌 Description
Performance optimization for `fp4_quantize()` function. The performance
issue was raised in issues #1734 and #2021
Observed behavior was slow performance when `is_sf_swi... | csrc/nv_internal/tensorrt_llm/kernels/quantization.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/nv_internal/tensorrt_llm/kernels/quantization.cuh
+++ csrc/nv_internal/tensorrt_llm/kernels/quantization.cuh
@@ -778,56 +778,86 @@
int numColThreadsForSf = numColsForSf / ELTS_PER_THREAD;
asm volatile("griddepcontrol.wait;");
+
// Input tensor batch/row/col loops.
+ // Optimization: Iterate over ac... | 74 | 44 | 2 | [] | [] | [
"10×"
] | Optimize this cuda kernel file from flashinfer (csrc/nv_internal/tensorrt_llm/kernels/quantization.cuh).
Goal: perf: Speed up fp4 quantization for small batch with swizzling for cutlass MoE
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2019-2023, NVIDIA CORPORATION.... | <!-- .github/pull_request_template.md -->
## 📌 Description
Performance optimization for `fp4_quantize()` function. The performance issue was raised in issues #1734 and #2021
Observed behavior was slow performance when `is_sf_swizzled_layout=True` (as opposed to False). Root cause of the issue was
* Excessive Padd... | [{"scope": "kernel", "hardware": null, "model": null, "shape": "N=5120", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 71.52, "optimized": 3.456, "stated_speedup": null, "speedup": 20.6944}, {"scope": "kernel", "hardware": null, "model": null, "shape": "N=5120", "batch_size"... | 1.68 | null |
flashinfer | bb6b62089a13db0a6b90887d68b161bbc1b5fc8e | 2025-10-28T23:47:25-07:00 | 1,980 | https://github.com/flashinfer-ai/flashinfer/pull/1980 | feat: autotune tile_tokens_dim in trtllm-gen MOE (#1980) | feat: autotune tile_tokens_dim in trtllm-gen MOE (#1980)
<!-- .github/pull_request_template.md -->
## 📌 Description
- Update the autotune logic in trtllm-gen moe. Instead of using a fixed
`tile_tokens_dim`, tune in a range of
`[max(8,tile_token_dim/2), tile_token_dim, min(128, tile_token_dim*2),
min(128, tile_token_... | csrc/trtllm_fused_moe_kernel_launcher.cu | cuda | Apache-2.0 | /*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distribut... | /*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distribut... | --- csrc/trtllm_fused_moe_kernel_launcher.cu
+++ csrc/trtllm_fused_moe_kernel_launcher.cu
@@ -18,6 +18,8 @@
#include <algorithm>
#include <cmath>
#include <iostream>
+#include <set>
+#include <unordered_map>
#include <vector>
#include "flashinfer/trtllm/batched_gemm/trtllmGen_bmm_export/GemmGatedActOptions.h"
@@... | 230 | 94 | 3 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (csrc/trtllm_fused_moe_kernel_launcher.cu).
Goal: feat: autotune tile_tokens_dim in trtllm-gen MOE
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this ... | <!-- .github/pull_request_template.md -->
## 📌 Description
- Update the autotune logic in trtllm-gen moe. Instead of using a fixed `tile_tokens_dim`, tune in a range of
`[max(8,tile_token_dim/2), tile_token_dim, min(128, tile_token_dim*2), min(128, tile_token_dim*4)]`
- Add FP8 MOE autotune logic, initial PR https:/... | [] | null | null |
flashinfer | ed1d8c1461d8cf85bd6d1c2f46eb4fbf4b14aa1a | 2025-09-19T17:13:55+08:00 | 1,685 | https://github.com/flashinfer-ai/flashinfer/pull/1685 | perf: Port the separate reduce kernel mode from trtllm. (#1685) | perf: Port the separate reduce kernel mode from trtllm. (#1685)
<!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re
needed. -->
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull Request Checklist
Thank you for con... | include/flashinfer/trtllm/common/cudaUtils.h | cpp | Apache-2.0 | /*
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights
* reserved. SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the Lic... | /*
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights
* reserved. SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the Lic... | --- include/flashinfer/trtllm/common/cudaUtils.h
+++ include/flashinfer/trtllm/common/cudaUtils.h
@@ -22,6 +22,7 @@
// #include "tensorrt_llm/common/logger.h"
// #include "tensorrt_llm/common/tllmException.h"
+#include <c10/util/Exception.h>
#include <cublasLt.h>
#include <cublas_v2.h>
#include <cuda.h>
@@ -31,1... | 4 | 1 | 5 | [] | [] | [] | Optimize this cpp kernel file from flashinfer (include/flashinfer/trtllm/common/cudaUtils.h).
Goal: perf: Port the separate reduce kernel mode from trtllm.
Target hardware: unspecified
Target models: unspecified
Current file:
```cpp
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES... | <!-- .github/pull_request_template.md -->
## 📌 Description
This also updated the kernels which fixed mha perf regression and fp8 sink attention accuracy issue.
<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull... | [] | null | null |
flashinfer | ed1d8c1461d8cf85bd6d1c2f46eb4fbf4b14aa1a | 2025-09-19T17:13:55+08:00 | 1,685 | https://github.com/flashinfer-ai/flashinfer/pull/1685 | perf: Port the separate reduce kernel mode from trtllm. (#1685) | perf: Port the separate reduce kernel mode from trtllm. (#1685)
<!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re
needed. -->
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull Request Checklist
Thank you for con... | include/flashinfer/trtllm/fmha/fmhaKernels.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless r... | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless r... | --- include/flashinfer/trtllm/fmha/fmhaKernels.cuh
+++ include/flashinfer/trtllm/fmha/fmhaKernels.cuh
@@ -28,6 +28,7 @@
#include "../common.h"
#include "cuda_runtime_api.h"
#include "flashInferMetaInfo.h"
+#include "fmhaReduction.h"
#include "fmhaRunnerParams.h"
#include "kernelParams.h"
#include "lse.cuh"
@@ -25... | 9 | 0 | 5 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/trtllm/fmha/fmhaKernels.cuh).
Goal: perf: Port the separate reduce kernel mode from trtllm.
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Lic... | <!-- .github/pull_request_template.md -->
## 📌 Description
This also updated the kernels which fixed mha perf regression and fp8 sink attention accuracy issue.
<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull... | [] | null | null |
flashinfer | ed1d8c1461d8cf85bd6d1c2f46eb4fbf4b14aa1a | 2025-09-19T17:13:55+08:00 | 1,685 | https://github.com/flashinfer-ai/flashinfer/pull/1685 | perf: Port the separate reduce kernel mode from trtllm. (#1685) | perf: Port the separate reduce kernel mode from trtllm. (#1685)
<!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re
needed. -->
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull Request Checklist
Thank you for con... | include/flashinfer/trtllm/fmha/fmhaRunnerParams.h | cpp | Apache-2.0 | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- include/flashinfer/trtllm/fmha/fmhaRunnerParams.h
+++ include/flashinfer/trtllm/fmha/fmhaRunnerParams.h
@@ -134,10 +134,14 @@
////////////////////////////////////////////////////////////////////////////////////////////////////
enum class MultiCtasKvMode {
- // No multiCtasKvMode.
+ // Disable the multiCtasKvM... | 6 | 1 | 5 | [] | [] | [] | Optimize this cpp kernel file from flashinfer (include/flashinfer/trtllm/fmha/fmhaRunnerParams.h).
Goal: perf: Port the separate reduce kernel mode from trtllm.
Target hardware: unspecified
Target models: unspecified
Current file:
```cpp
/*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* L... | <!-- .github/pull_request_template.md -->
## 📌 Description
This also updated the kernels which fixed mha perf regression and fp8 sink attention accuracy issue.
<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull... | [] | null | null |
flashinfer | 67c7e889605106778aac5cdd6d7feee0fccfc86f | 2025-09-15T20:01:07-04:00 | 1,681 | https://github.com/flashinfer-ai/flashinfer/pull/1681 | perf: improve performance of cutlass fmha (#1681) | perf: improve performance of cutlass fmha (#1681)
<!-- .github/pull_request_template.md -->
## 📌 Description
1. fix the bug in `get_unmasked_trip_count` calculation in causal
attention
2. add skip correction rescale optimization in FA4.
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull Reques... | include/flashinfer/attention/blackwell/collective/fmha_fusion.hpp | cpp | BSD-3-Clause | /***************************************************************************************************
* Copyright (c) 2024 - 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
*
* Redistribution and use in source and binary forms, with or without
* modification, are p... | /***************************************************************************************************
* Copyright (c) 2024 - 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
*
* Redistribution and use in source and binary forms, with or without
* modification, are p... | --- include/flashinfer/attention/blackwell/collective/fmha_fusion.hpp
+++ include/flashinfer/attention/blackwell/collective/fmha_fusion.hpp
@@ -121,7 +121,8 @@
template <class BlkCoord, class TileShape, class ProblemSize>
CUTLASS_DEVICE int get_masked_trip_count(BlkCoord const& blk_coord, TileShape const& tile_sh... | 2 | 1 | 2 | [] | [
"BLACKWELL"
] | [] | Optimize this cpp kernel file from flashinfer (include/flashinfer/attention/blackwell/collective/fmha_fusion.hpp).
Goal: perf: improve performance of cutlass fmha
Target hardware: BLACKWELL
Target models: unspecified
Current file:
```cpp
/*******************************************************************************... | <!-- .github/pull_request_template.md -->
## 📌 Description
1. fix the bug in `get_unmasked_trip_count` calculation in causal attention
2. add skip correction rescale optimization in FA4.
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull Request Checklist
Thank you for contributing to FlashInf... | [] | null | null |
flashinfer | 67c7e889605106778aac5cdd6d7feee0fccfc86f | 2025-09-15T20:01:07-04:00 | 1,681 | https://github.com/flashinfer-ai/flashinfer/pull/1681 | perf: improve performance of cutlass fmha (#1681) | perf: improve performance of cutlass fmha (#1681)
<!-- .github/pull_request_template.md -->
## 📌 Description
1. fix the bug in `get_unmasked_trip_count` calculation in causal
attention
2. add skip correction rescale optimization in FA4.
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull Reques... | include/flashinfer/attention/blackwell/collective/sm100_fmha_fwd_mainloop_tma_warpspecialized.hpp | cpp | BSD-3-Clause | /***************************************************************************************************
* Copyright (c) 2024 - 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
*
* Redistribution and use in source and binary forms, with or without
* modification, are p... | /***************************************************************************************************
* Copyright (c) 2024 - 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
*
* Redistribution and use in source and binary forms, with or without
* modification, are p... | --- include/flashinfer/attention/blackwell/collective/sm100_fmha_fwd_mainloop_tma_warpspecialized.hpp
+++ include/flashinfer/attention/blackwell/collective/sm100_fmha_fwd_mainloop_tma_warpspecialized.hpp
@@ -961,10 +961,13 @@
// e^(scale * (old_max - new_max)
float scale = ::exp2f(params.scale_softmax_log... | 8 | 2 | 2 | [] | [
"BLACKWELL"
] | [] | Optimize this cpp kernel file from flashinfer (include/flashinfer/attention/blackwell/collective/sm100_fmha_fwd_mainloop_tma_warpspecialized.hpp).
Goal: perf: improve performance of cutlass fmha
Target hardware: BLACKWELL
Target models: unspecified
Current file:
```cpp
/***********************************************... | <!-- .github/pull_request_template.md -->
## 📌 Description
1. fix the bug in `get_unmasked_trip_count` calculation in causal attention
2. add skip correction rescale optimization in FA4.
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull Request Checklist
Thank you for contributing to FlashInf... | [] | null | null |
flashinfer | 73bc88ec1210a73bf2bd67316ca221b4f677de3c | 2025-09-09T19:38:03+08:00 | 1,660 | https://github.com/flashinfer-ai/flashinfer/pull/1660 | Speedup MLARopeQuantize by 20-35% (#1660) | Speedup MLARopeQuantize by 20-35% (#1660)
<!-- .github/pull_request_template.md -->
## 📌 Description
baseline
```
num_tokens FlashInfer
0 1.0 0.002714
1 2.0 0.003126
2 4.0 0.003328
3 8.0 0.003328
4 16.0 0.003530
5 32.0 0.004144
6 64... | include/flashinfer/pos_enc.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/pos_enc.cuh
+++ include/flashinfer/pos_enc.cuh
@@ -370,7 +370,7 @@
// 2. if not interleave
// - cos = cos_cache[pos_id][(tx * vec_size) % (rot_dim // 2)]
// - sin = sin_cache[pos_id][(rot_dim // 2) + (tx * vec_size) % (rot_dim // 2)]
- if (tx * vec_size < rotary_dim) {
+ if... | 2 | 2 | 1 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/pos_enc.cuh).
Goal: Speedup MLARopeQuantize by 20-35%
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* y... |
<!-- .github/pull_request_template.md -->
## 📌 Description
baseline
```
num_tokens FlashInfer
0 1.0 0.002714
1 2.0 0.003126
2 4.0 0.003328
3 8.0 0.003328
4 16.0 0.003530
5 32.0 0.004144
6 64.0 0.005430
7 128.0 0.007837
... | [] | null | null |
flashinfer | 375a26b6550578799a739d91c3470cd1727f35a4 | 2025-09-05T03:48:15-04:00 | 1,548 | https://github.com/flashinfer-ai/flashinfer/pull/1548 | Enable SplitK and fix autotuner for trtllm fp4 fused moe (#1548) | Enable SplitK and fix autotuner for trtllm fp4 fused moe (#1548)
Enable splitK for trtllm-gen fused moe.
Make autotuner for trtllm-gen fp4 fused moe more robust.
Add autotuner for trtllm-gen fused moe test.
<!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the ... | csrc/trtllm_batched_gemm_runner.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/trtllm_batched_gemm_runner.cu
+++ csrc/trtllm_batched_gemm_runner.cu
@@ -104,13 +104,6 @@
tileSize == mOptions.tileSize &&
options.mUseShuffledMatrixA == mOptions.useShuffledMatrixA &&
options.mLayoutA == mOptions.weightLayout) {
- // FIXME: Disable split-k for swiglu for now.
-... | 0 | 7 | 4 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (csrc/trtllm_batched_gemm_runner.cu).
Goal: Enable SplitK and fix autotuner for trtllm fp4 fused moe
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed unde... | Enable splitK for trtllm-gen fused moe.
Make autotuner for trtllm-gen fp4 fused moe more robust.
Add autotuner for trtllm-gen fused moe test.
<!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->
## 🔍 Related Issues
<!-- Li... | [] | null | null |
flashinfer | 375a26b6550578799a739d91c3470cd1727f35a4 | 2025-09-05T03:48:15-04:00 | 1,548 | https://github.com/flashinfer-ai/flashinfer/pull/1548 | Enable SplitK and fix autotuner for trtllm fp4 fused moe (#1548) | Enable SplitK and fix autotuner for trtllm fp4 fused moe (#1548)
Enable splitK for trtllm-gen fused moe.
Make autotuner for trtllm-gen fp4 fused moe more robust.
Add autotuner for trtllm-gen fused moe test.
<!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the ... | include/flashinfer/trtllm/batched_gemm/trtllmGen_bmm_export/GemmOptions.h | cpp | Apache-2.0 | /*
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION &
* AFFILIATES. All rights reserved. SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the Lic... | /*
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION &
* AFFILIATES. All rights reserved. SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the Lic... | --- include/flashinfer/trtllm/batched_gemm/trtllmGen_bmm_export/GemmOptions.h
+++ include/flashinfer/trtllm/batched_gemm/trtllmGen_bmm_export/GemmOptions.h
@@ -1085,22 +1085,34 @@
")");
}
+ // Number of iterations in K dimension after padding.
+ // Note the perCtaK in each CTA in the splitK... | 28 | 11 | 4 | [] | [] | [] | Optimize this cpp kernel file from flashinfer (include/flashinfer/trtllm/batched_gemm/trtllmGen_bmm_export/GemmOptions.h).
Goal: Enable SplitK and fix autotuner for trtllm fp4 fused moe
Target hardware: unspecified
Target models: unspecified
Current file:
```cpp
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 N... | Enable splitK for trtllm-gen fused moe.
Make autotuner for trtllm-gen fp4 fused moe more robust.
Add autotuner for trtllm-gen fused moe test.
<!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->
## 🔍 Related Issues
<!-- Li... | [] | null | null |
flashinfer | da937d73c6dd59419bf6beaf7e5c5c0f1d0d0d93 | 2025-09-03T04:32:32+08:00 | 1,615 | https://github.com/flashinfer-ai/flashinfer/pull/1615 | perf: Fix the tactic sorting in TrtllmGenBatchedGemmRunner::getValidConfigIndices (#1615) | perf: Fix the tactic sorting in TrtllmGenBatchedGemmRunner::getValidConfigIndices (#1615) | csrc/trtllm_batched_gemm_runner.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/trtllm_batched_gemm_runner.cu
+++ csrc/trtllm_batched_gemm_runner.cu
@@ -24,6 +24,7 @@
#include "flashinfer/trtllm/batched_gemm/trtllmGen_bmm_export/Enums.h"
#include "flashinfer/trtllm/batched_gemm/trtllmGen_bmm_export/trtllm/gen/DtypeDecl.h"
#include "flashinfer/trtllm/common.h"
+#include "tensorrt_llm/co... | 45 | 52 | 2 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (csrc/trtllm_batched_gemm_runner.cu).
Goal: perf: Fix the tactic sorting in TrtllmGenBatchedGemmRunner::getValidConfigIndices
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights rese... | <!-- .github/pull_request_template.md -->
## 📌 Description
The tactic sorting in `TrtllmGenBatchedGemmRunner::getValidConfigIndices` may not be as expected because different criteria are applied in different sorting function calls. This PR fixes the issue by applying these criteria in the same sorting function call.... | [] | null | null |
flashinfer | da937d73c6dd59419bf6beaf7e5c5c0f1d0d0d93 | 2025-09-03T04:32:32+08:00 | 1,615 | https://github.com/flashinfer-ai/flashinfer/pull/1615 | perf: Fix the tactic sorting in TrtllmGenBatchedGemmRunner::getValidConfigIndices (#1615) | perf: Fix the tactic sorting in TrtllmGenBatchedGemmRunner::getValidConfigIndices (#1615) | include/flashinfer/trtllm/batched_gemm/trtllmGen_bmm_export/BatchedGemmInterface.h | cpp | Apache-2.0 | /*
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION &
* AFFILIATES. All rights reserved. SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the Lic... | /*
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION &
* AFFILIATES. All rights reserved. SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the Lic... | --- include/flashinfer/trtllm/batched_gemm/trtllmGen_bmm_export/BatchedGemmInterface.h
+++ include/flashinfer/trtllm/batched_gemm/trtllmGen_bmm_export/BatchedGemmInterface.h
@@ -522,13 +522,14 @@
// Returns true if the configuration of the cubin can be executed for the given params.
bool isValidConfig(BatchedGemm... | 4 | 3 | 2 | [] | [] | [] | Optimize this cpp kernel file from flashinfer (include/flashinfer/trtllm/batched_gemm/trtllmGen_bmm_export/BatchedGemmInterface.h).
Goal: perf: Fix the tactic sorting in TrtllmGenBatchedGemmRunner::getValidConfigIndices
Target hardware: unspecified
Target models: unspecified
Current file:
```cpp
/*
* SPDX-FileCopyri... | <!-- .github/pull_request_template.md -->
## 📌 Description
The tactic sorting in `TrtllmGenBatchedGemmRunner::getValidConfigIndices` may not be as expected because different criteria are applied in different sorting function calls. This PR fixes the issue by applying these criteria in the same sorting function call.... | [] | null | null |
flashinfer | eab0de466deea57771f152e5ee6969d744ddfcf7 | 2025-08-30T02:11:12+08:00 | 1,607 | https://github.com/flashinfer-ai/flashinfer/pull/1607 | [cute dsl] optimize cute dsl make_ptr perf (#1607) | [cute dsl] optimize cute dsl make_ptr perf (#1607) | flashinfer/cute_dsl/blockscaled_gemm.py | cute_dsl | BSD-3-Clause | # Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Identifier: BSD-3-Clause
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# 1. Redistributions of source code must retain the abov... | # Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Identifier: BSD-3-Clause
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# 1. Redistributions of source code must retain the abov... | --- flashinfer/cute_dsl/blockscaled_gemm.py
+++ flashinfer/cute_dsl/blockscaled_gemm.py
@@ -40,7 +40,8 @@
import functools
from cutlass._mlir import ir
from cutlass.cute.nvgpu import cpasync, tcgen05
-from cutlass.cute.runtime import from_dlpack, make_ptr
+from cutlass.cute.runtime import from_dlpack
+
from cutlass... | 3 | 2 | 2 | [] | [] | [] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/cute_dsl/blockscaled_gemm.py).
Goal: [cute dsl] optimize cute dsl make_ptr perf
Target hardware: unspecified
Target models: unspecified
Current file:
```python
# Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Ident... | <!-- .github/pull_request_template.md -->
## 📌 Description
Optimize make_ptr performance for cute_dsl as a workaround. Will remove the WAR after CuTeDSL release the optimization.
Performance: 20us+ => 1.4us
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull Request Checklist
Thank you for con... | [{"scope": "kernel", "hardware": null, "model": null, "shape": null, "batch_size": null, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 20, "optimized": 1.4, "stated_speedup": null, "speedup": 14.2857}] | 14.2857 | null |
flashinfer | eab0de466deea57771f152e5ee6969d744ddfcf7 | 2025-08-30T02:11:12+08:00 | 1,607 | https://github.com/flashinfer-ai/flashinfer/pull/1607 | [cute dsl] optimize cute dsl make_ptr perf (#1607) | [cute dsl] optimize cute dsl make_ptr perf (#1607) | flashinfer/cute_dsl/utils.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/cute_dsl/utils.py
+++ flashinfer/cute_dsl/utils.py
@@ -14,10 +14,16 @@
limitations under the License.
"""
+import ctypes
+import functools
+import importlib.util
+from typing import Union
+
import cutlass
+import cutlass._mlir.dialects.cute as _cute_ir
import torch
-import importlib.util
-import fu... | 156 | 2 | 2 | [] | [] | [] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/cute_dsl/utils.py).
Goal: [cute dsl] optimize cute dsl make_ptr perf
Target hardware: unspecified
Target models: unspecified
Current file:
```python
"""
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License")... | <!-- .github/pull_request_template.md -->
## 📌 Description
Optimize make_ptr performance for cute_dsl as a workaround. Will remove the WAR after CuTeDSL release the optimization.
Performance: 20us+ => 1.4us
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull Request Checklist
Thank you for con... | [{"scope": "kernel", "hardware": null, "model": null, "shape": null, "batch_size": null, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 20, "optimized": 1.4, "stated_speedup": null, "speedup": 14.2857}] | 14.2857 | null |
flashinfer | 8ce1b089088e89f89fae7778d689ebc313477717 | 2025-08-27T00:48:06-07:00 | 1,573 | https://github.com/flashinfer-ai/flashinfer/pull/1573 | update trtllm-gen fp4 autotuner and routing (#1573) | update trtllm-gen fp4 autotuner and routing (#1573)
<!-- .github/pull_request_template.md -->
## 📌 Description
- remove `.to(torch.bfloat16)` which causes illegal memory access when
using deepseek v3 routing.
- handle the case when `routing_logits` is `None` to support
`trtllm_fp4_block_scale_routed_moe`
- fix the ... | csrc/trtllm_fused_moe_routing_llama4.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2022-2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2022-2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/trtllm_fused_moe_routing_llama4.cu
+++ csrc/trtllm_fused_moe_routing_llama4.cu
@@ -449,7 +449,7 @@
} else {
// Reset the global histograms.
CHECK_CUDA_ERROR(cudaMemsetAsync(data.mPtrExpertCounts, 0,
- static_cast<size_t>(2 * NumThreads) * sizeof(int32_t)... | 1 | 1 | 3 | [
"deepseek",
"llama"
] | [] | [] | Optimize this cuda kernel file from flashinfer (csrc/trtllm_fused_moe_routing_llama4.cu).
Goal: update trtllm-gen fp4 autotuner and routing
Target hardware: unspecified
Target models: deepseek, llama
Current file:
```cuda
/*
* Copyright (c) 2022-2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under th... | <!-- .github/pull_request_template.md -->
## 📌 Description
- remove `.to(torch.bfloat16)` which causes illegal memory access when using deepseek v3 routing.
- handle the case when `routing_logits` is `None` to support `trtllm_fp4_block_scale_routed_moe`
- fix the `invalid argument` error in llama and renormalize rou... | [] | null | null |
flashinfer | 8ce1b089088e89f89fae7778d689ebc313477717 | 2025-08-27T00:48:06-07:00 | 1,573 | https://github.com/flashinfer-ai/flashinfer/pull/1573 | update trtllm-gen fp4 autotuner and routing (#1573) | update trtllm-gen fp4 autotuner and routing (#1573)
<!-- .github/pull_request_template.md -->
## 📌 Description
- remove `.to(torch.bfloat16)` which causes illegal memory access when
using deepseek v3 routing.
- handle the case when `routing_logits` is `None` to support
`trtllm_fp4_block_scale_routed_moe`
- fix the ... | csrc/trtllm_fused_moe_routing_renormalize.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2022-2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2022-2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/trtllm_fused_moe_routing_renormalize.cu
+++ csrc/trtllm_fused_moe_routing_renormalize.cu
@@ -278,7 +278,7 @@
} else {
// Reset the global histograms.
CHECK_CUDA_ERROR(cudaMemsetAsync(data.mPtrExpertCounts, 0,
- static_cast<size_t>(2 * NumThreads) * sizeo... | 1 | 1 | 3 | [
"deepseek",
"llama"
] | [] | [] | Optimize this cuda kernel file from flashinfer (csrc/trtllm_fused_moe_routing_renormalize.cu).
Goal: update trtllm-gen fp4 autotuner and routing
Target hardware: unspecified
Target models: deepseek, llama
Current file:
```cuda
/*
* Copyright (c) 2022-2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed und... | <!-- .github/pull_request_template.md -->
## 📌 Description
- remove `.to(torch.bfloat16)` which causes illegal memory access when using deepseek v3 routing.
- handle the case when `routing_logits` is `None` to support `trtllm_fp4_block_scale_routed_moe`
- fix the `invalid argument` error in llama and renormalize rou... | [] | null | null |
flashinfer | e2448aa6e3d268c0b4451d17d8cb5c1804ca1fb7 | 2025-08-22T11:46:52-07:00 | 1,547 | https://github.com/flashinfer-ai/flashinfer/pull/1547 | perf: replace cudaGetDeviceProperties with cudaDeviceGetAttribute (#1547) | perf: replace cudaGetDeviceProperties with cudaDeviceGetAttribute (#1547)
<!-- .github/pull_request_template.md -->
## 📌 Description
This change replaces the use of cudaGetDeviceProperties with
cudaDeviceGetAttribute when querying the number of GPU Streaming
Multiprocessors. Rather than retrieving the entire device... | csrc/cudnn_sdpa_kernel_launcher.cu | cuda | Apache-2.0 | /*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distribut... | /*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distribut... | --- csrc/cudnn_sdpa_kernel_launcher.cu
+++ csrc/cudnn_sdpa_kernel_launcher.cu
@@ -973,10 +973,10 @@
CU_FUNC_ATTRIBUTE_NON_PORTABLE_CLUSTER_SIZE_ALLOWED, 1));
}
- // Get number of SMs perf GPU
- cudaDeviceProp prop;
- cudaGetDeviceProperties(&prop, 0);
- sm_count =... | 4 | 4 | 3 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (csrc/cudnn_sdpa_kernel_launcher.cu).
Goal: perf: replace cudaGetDeviceProperties with cudaDeviceGetAttribute
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may no... | <!-- .github/pull_request_template.md -->
## 📌 Description
This change replaces the use of cudaGetDeviceProperties with cudaDeviceGetAttribute when querying the number of GPU Streaming Multiprocessors. Rather than retrieving the entire device properties, the updated approach directly fetches only the needed attribut... | [] | null | null |
flashinfer | e2448aa6e3d268c0b4451d17d8cb5c1804ca1fb7 | 2025-08-22T11:46:52-07:00 | 1,547 | https://github.com/flashinfer-ai/flashinfer/pull/1547 | perf: replace cudaGetDeviceProperties with cudaDeviceGetAttribute (#1547) | perf: replace cudaGetDeviceProperties with cudaDeviceGetAttribute (#1547)
<!-- .github/pull_request_template.md -->
## 📌 Description
This change replaces the use of cudaGetDeviceProperties with
cudaDeviceGetAttribute when querying the number of GPU Streaming
Multiprocessors. Rather than retrieving the entire device... | include/flashinfer/comm/trtllm_allreduce_fusion.cuh | cuda | Apache-2.0 | #include <cooperative_groups.h>
#include <cuda.h>
#include <cuda_bf16.h>
#include <cuda_fp16.h>
#if CUDA_VERSION >= 120800
#include <cuda_fp4.h>
#endif
#include <cuda/std/optional>
#include <tuple>
#include <type_traits>
#include "../exception.h"
#include "../fp4_layout.cuh"
#include "../logging.h"
#include "../util... | #include <cooperative_groups.h>
#include <cuda.h>
#include <cuda_bf16.h>
#include <cuda_fp16.h>
#if CUDA_VERSION >= 120800
#include <cuda_fp4.h>
#endif
#include <cuda/std/optional>
#include <tuple>
#include <type_traits>
#include "../exception.h"
#include "../fp4_layout.cuh"
#include "../logging.h"
#include "../util... | --- include/flashinfer/comm/trtllm_allreduce_fusion.cuh
+++ include/flashinfer/comm/trtllm_allreduce_fusion.cuh
@@ -1292,9 +1292,8 @@
if (sm_count == 0) {
int device_id;
FLASHINFER_CUDA_CALL(cudaGetDevice(&device_id));
- cudaDeviceProp device_prop;
- cudaGetDeviceProperties(&device_prop, device_id);
... | 2 | 3 | 3 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/comm/trtllm_allreduce_fusion.cuh).
Goal: perf: replace cudaGetDeviceProperties with cudaDeviceGetAttribute
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
#include <cooperative_groups.h>
#include <cuda.h>
#include <cuda_b... | <!-- .github/pull_request_template.md -->
## 📌 Description
This change replaces the use of cudaGetDeviceProperties with cudaDeviceGetAttribute when querying the number of GPU Streaming Multiprocessors. Rather than retrieving the entire device properties, the updated approach directly fetches only the needed attribut... | [] | null | null |
flashinfer | e2448aa6e3d268c0b4451d17d8cb5c1804ca1fb7 | 2025-08-22T11:46:52-07:00 | 1,547 | https://github.com/flashinfer-ai/flashinfer/pull/1547 | perf: replace cudaGetDeviceProperties with cudaDeviceGetAttribute (#1547) | perf: replace cudaGetDeviceProperties with cudaDeviceGetAttribute (#1547)
<!-- .github/pull_request_template.md -->
## 📌 Description
This change replaces the use of cudaGetDeviceProperties with
cudaDeviceGetAttribute when querying the number of GPU Streaming
Multiprocessors. Rather than retrieving the entire device... | include/flashinfer/comm/trtllm_moe_allreduce_fusion.cuh | cuda | Apache-2.0 | #include <cooperative_groups.h>
#include <cuda.h>
#include <cuda_bf16.h>
#include <cuda_fp16.h>
#if CUDA_VERSION >= 120800
#include <cuda_fp4.h>
#endif
#include <cuda/std/optional>
#include <tuple>
#include <type_traits>
#include "../exception.h"
#include "../fp4_layout.cuh"
#include "../logging.h"
#include "../util... | #include <cooperative_groups.h>
#include <cuda.h>
#include <cuda_bf16.h>
#include <cuda_fp16.h>
#if CUDA_VERSION >= 120800
#include <cuda_fp4.h>
#endif
#include <cuda/std/optional>
#include <tuple>
#include <type_traits>
#include "../exception.h"
#include "../fp4_layout.cuh"
#include "../logging.h"
#include "../util... | --- include/flashinfer/comm/trtllm_moe_allreduce_fusion.cuh
+++ include/flashinfer/comm/trtllm_moe_allreduce_fusion.cuh
@@ -919,9 +919,7 @@
auto status = cudaGetDevice(&device_id);
FLASHINFER_CHECK(status == cudaSuccess, "cudaGetDevice failed with error code " +
... | 1 | 3 | 3 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/comm/trtllm_moe_allreduce_fusion.cuh).
Goal: perf: replace cudaGetDeviceProperties with cudaDeviceGetAttribute
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
#include <cooperative_groups.h>
#include <cuda.h>
#include <cu... | <!-- .github/pull_request_template.md -->
## 📌 Description
This change replaces the use of cudaGetDeviceProperties with cudaDeviceGetAttribute when querying the number of GPU Streaming Multiprocessors. Rather than retrieving the entire device properties, the updated approach directly fetches only the needed attribut... | [] | null | null |
flashinfer | 6518ce42a8a3d4d32c2262b638c63049c02a3d62 | 2025-08-16T22:30:37-07:00 | 1,491 | https://github.com/flashinfer-ai/flashinfer/pull/1491 | perf: support scale_a/scale_b instead of combined scale in cutlass bmm_fp8 (#1491) | perf: support scale_a/scale_b instead of combined scale in cutlass bmm_fp8 (#1491)
Previous cutlass implementation require combine of scale_a/scale_b in
the python, so extra aten kernel is used which may cost 1us. Now we
support separate alpha_a and alpha_b in epilog, to avoid this extra aten
kernel.
<!-- .github/pul... | csrc/fp8_gemm_cutlass.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/fp8_gemm_cutlass.cu
+++ csrc/fp8_gemm_cutlass.cu
@@ -59,8 +59,8 @@
template <typename T>
void runGemm(at::Tensor& out, at::Tensor const& mat1, at::Tensor const& mat2,
- at::Tensor const& scale, int64_t m, int64_t n, int64_t k, int64_t b,
- CutlassGemmConfig const& gemmConfig, at::Te... | 17 | 11 | 5 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (csrc/fp8_gemm_cutlass.cu).
Goal: perf: support scale_a/scale_b instead of combined scale in cutlass bmm_fp8
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licen... | Previous cutlass implementation require combine of scale_a/scale_b in the python, so extra aten kernel is used which may cost 1us. Now we support separate alpha_a and alpha_b in epilog, to avoid this extra aten kernel.
<!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly des... | [] | null | null |
flashinfer | 6518ce42a8a3d4d32c2262b638c63049c02a3d62 | 2025-08-16T22:30:37-07:00 | 1,491 | https://github.com/flashinfer-ai/flashinfer/pull/1491 | perf: support scale_a/scale_b instead of combined scale in cutlass bmm_fp8 (#1491) | perf: support scale_a/scale_b instead of combined scale in cutlass bmm_fp8 (#1491)
Previous cutlass implementation require combine of scale_a/scale_b in
the python, so extra aten kernel is used which may cost 1us. Now we
support separate alpha_a and alpha_b in epilog, to avoid this extra aten
kernel.
<!-- .github/pul... | include/flashinfer/gemm/fp8_gemm_cutlass.h | cpp | Apache-2.0 | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- include/flashinfer/gemm/fp8_gemm_cutlass.h
+++ include/flashinfer/gemm/fp8_gemm_cutlass.h
@@ -31,9 +31,10 @@
CutlassFp8GemmRunnerInterface() = default;
virtual ~CutlassFp8GemmRunnerInterface() = default;
- virtual void gemm(__nv_fp8_e4m3 const* A, __nv_fp8_e4m3 const* B, float const* alpha, void* D,
- ... | 7 | 6 | 5 | [] | [] | [] | Optimize this cpp kernel file from flashinfer (include/flashinfer/gemm/fp8_gemm_cutlass.h).
Goal: perf: support scale_a/scale_b instead of combined scale in cutlass bmm_fp8
Target hardware: unspecified
Target models: unspecified
Current file:
```cpp
/*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reser... | Previous cutlass implementation require combine of scale_a/scale_b in the python, so extra aten kernel is used which may cost 1us. Now we support separate alpha_a and alpha_b in epilog, to avoid this extra aten kernel.
<!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly des... | [] | null | null |
flashinfer | 6518ce42a8a3d4d32c2262b638c63049c02a3d62 | 2025-08-16T22:30:37-07:00 | 1,491 | https://github.com/flashinfer-ai/flashinfer/pull/1491 | perf: support scale_a/scale_b instead of combined scale in cutlass bmm_fp8 (#1491) | perf: support scale_a/scale_b instead of combined scale in cutlass bmm_fp8 (#1491)
Previous cutlass implementation require combine of scale_a/scale_b in
the python, so extra aten kernel is used which may cost 1us. Now we
support separate alpha_a and alpha_b in epilog, to avoid this extra aten
kernel.
<!-- .github/pul... | include/flashinfer/gemm/fp8_gemm_cutlass_template.h | cpp | Apache-2.0 | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- include/flashinfer/gemm/fp8_gemm_cutlass_template.h
+++ include/flashinfer/gemm/fp8_gemm_cutlass_template.h
@@ -50,43 +50,44 @@
template <typename T, typename arch, int32_t CTA_M_, int32_t CTA_N_, int32_t CTA_K_,
typename ClusterShape_, typename XSM_>
size_t genericFp8GemmKernelLauncherSm100(__nv_fp8_e... | 41 | 38 | 5 | [] | [] | [] | Optimize this cpp kernel file from flashinfer (include/flashinfer/gemm/fp8_gemm_cutlass_template.h).
Goal: perf: support scale_a/scale_b instead of combined scale in cutlass bmm_fp8
Target hardware: unspecified
Target models: unspecified
Current file:
```cpp
/*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rig... | Previous cutlass implementation require combine of scale_a/scale_b in the python, so extra aten kernel is used which may cost 1us. Now we support separate alpha_a and alpha_b in epilog, to avoid this extra aten kernel.
<!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly des... | [] | null | null |
flashinfer | 6518ce42a8a3d4d32c2262b638c63049c02a3d62 | 2025-08-16T22:30:37-07:00 | 1,491 | https://github.com/flashinfer-ai/flashinfer/pull/1491 | perf: support scale_a/scale_b instead of combined scale in cutlass bmm_fp8 (#1491) | perf: support scale_a/scale_b instead of combined scale in cutlass bmm_fp8 (#1491)
Previous cutlass implementation require combine of scale_a/scale_b in
the python, so extra aten kernel is used which may cost 1us. Now we
support separate alpha_a and alpha_b in epilog, to avoid this extra aten
kernel.
<!-- .github/pul... | include/flashinfer/gemm/fp8_gemm_template_sm100.h | cpp | Apache-2.0 | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- include/flashinfer/gemm/fp8_gemm_template_sm100.h
+++ include/flashinfer/gemm/fp8_gemm_template_sm100.h
@@ -23,9 +23,12 @@
#include "cutlass/arch/arch.h"
#include "cutlass/cutlass.h"
#include "cutlass/epilogue/collective/collective_builder.hpp"
+#include "cutlass/epilogue/fusion/sm90_visitor_load_tma_warpspecial... | 32 | 11 | 5 | [] | [] | [] | Optimize this cpp kernel file from flashinfer (include/flashinfer/gemm/fp8_gemm_template_sm100.h).
Goal: perf: support scale_a/scale_b instead of combined scale in cutlass bmm_fp8
Target hardware: unspecified
Target models: unspecified
Current file:
```cpp
/*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All right... | Previous cutlass implementation require combine of scale_a/scale_b in the python, so extra aten kernel is used which may cost 1us. Now we support separate alpha_a and alpha_b in epilog, to avoid this extra aten kernel.
<!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly des... | [] | null | null |
flashinfer | cba02c4e9858eba08d26f97436e8fb42870492ef | 2025-08-14T16:11:59+08:00 | 1,483 | https://github.com/flashinfer-ai/flashinfer/pull/1483 | perf: add fast path to TopPRenormProbKernel for top_p >= 1.0, significantly boosting SGLang workloads (#1483) | perf: add fast path to TopPRenormProbKernel for top_p >= 1.0, significantly boosting SGLang workloads (#1483)
<!-- .github/pull_request_template.md -->
## 📌 Description
### Summary
When deploying **DeepSeek-R1** with **DP+EP+MTP** in SGLang and sending
requests with `temperature > 0.0`, we observed a **\~15% perfor... | include/flashinfer/sampling.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/sampling.cuh
+++ include/flashinfer/sampling.cuh
@@ -1539,6 +1539,7 @@
struct {
float max_val;
float min_val;
+ float row_sum;
union {
struct {
float values[2];
@@ -1565,9 +1566,61 @@
uint8_t smem_renorm[];
auto& temp_storage =
reinterpret_cas... | 55 | 2 | 1 | [
"deepseek"
] | [] | [
"200×"
] | Optimize this cuda kernel file from flashinfer (include/flashinfer/sampling.cuh).
Goal: perf: add fast path to TopPRenormProbKernel for top_p >= 1.0, significantly boosting SGLang workloads
Target hardware: unspecified
Target models: deepseek
Current file:
```cuda
/*
* Copyright (c) 2024 by FlashInfer team.
*
* Li... | <!-- .github/pull_request_template.md -->
## 📌 Description
### Summary
When deploying **DeepSeek-R1** with **DP+EP+MTP** in SGLang and sending requests with `temperature > 0.0`, we observed a **\~15% performance degradation**.
Profiling revealed that `TopPRenormProbKernel` took about **13 ms**, whereas disabling MTP... | [{"scope": "kernel", "hardware": null, "model": null, "shape": null, "batch_size": null, "metric": "latency", "unit": null, "higher_is_better": false, "baseline": null, "optimized": null, "stated_speedup": 200, "speedup": 200.0}, {"scope": "kernel", "hardware": null, "model": "DeepSeek-R1", "shape": null, "batch_size":... | 100.575 | null |
flashinfer | 7e98d8b94ae626aaebf2f5e25d115bc30c2229f2 | 2025-08-12T12:46:20-07:00 | 1,473 | https://github.com/flashinfer-ai/flashinfer/pull/1473 | perf: add 1x4x1 cluster shape for fp8 bmm M<16 cases (#1473) | perf: add 1x4x1 cluster shape for fp8 bmm M<16 cases (#1473) | include/flashinfer/gemm/fp8_gemm_cutlass_template.h | cpp | Apache-2.0 | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- include/flashinfer/gemm/fp8_gemm_cutlass_template.h
+++ include/flashinfer/gemm/fp8_gemm_cutlass_template.h
@@ -83,6 +83,11 @@
_2SM>(A, B, alpha, D, m, n, k, b, gemmConfig,
workspacePtr, workspaceBytes, stream);
... | 7 | 3 | 1 | [] | [] | [] | Optimize this cpp kernel file from flashinfer (include/flashinfer/gemm/fp8_gemm_cutlass_template.h).
Goal: perf: add 1x4x1 cluster shape for fp8 bmm M<16 cases
Target hardware: unspecified
Target models: unspecified
Current file:
```cpp
/*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Li... | there is perf gain in M<16 cases when we use the 1x4x1 cluster shape.
<!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull Request Checklist
Thank you f... | [] | null | null |
flashinfer | 43e08e9b0fa58b4d51998ce20ca439771c8ac200 | 2025-07-25T04:21:27-07:00 | 1,321 | https://github.com/flashinfer-ai/flashinfer/pull/1321 | comm: Optimizations for TRTLLM MNNVL Allreduce (#1321) | comm: Optimizations for TRTLLM MNNVL Allreduce (#1321)
<!-- .github/pull_request_template.md -->
## 📌 Description
This PR introduces a series of optimizations to the
trtllm_mnnvl_allreduce. These optimizations are also added by
[https://github.com/NVIDIA/TensorRT-LLM/pull/5934](https://github.com/NVIDIA/TensorRT-LL... | csrc/trtllm_mnnvl_allreduce.cu | cuda | Apache-2.0 | #include "flashinfer/comm/trtllm_mnnvl_allreduce.cuh"
#include "pytorch_extension_utils.h"
using namespace flashinfer::trtllm_mnnvl_allreduce;
#define DISPATCH_FLOATING_TYPES_FOR_MNNVL_ALLREDUCE(scalar_type, c_type, ...) \
[&] { ... | #include "flashinfer/comm/trtllm_mnnvl_allreduce.cuh"
#include "pytorch_extension_utils.h"
using namespace flashinfer::trtllm_mnnvl_allreduce;
#define DISPATCH_FLOATING_TYPES_FOR_MNNVL_ALLREDUCE(scalar_type, c_type, ...) \
[&] { ... | --- csrc/trtllm_mnnvl_allreduce.cu
+++ csrc/trtllm_mnnvl_allreduce.cu
@@ -37,6 +37,8 @@
int64_t token_dim = in.size(1);
// Validate input parameters
+ TORCH_CHECK(token_dim % (sizeof(float2) / sizeof(c_type)) == 0,
+ "token_dim must be divisible by ", sizeof(float2) / sizeof(c_type));
... | 2 | 0 | 4 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (csrc/trtllm_mnnvl_allreduce.cu).
Goal: comm: Optimizations for TRTLLM MNNVL Allreduce
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
#include "flashinfer/comm/trtllm_mnnvl_allreduce.cuh"
#include "pytorch_extension_utils.h"
using namespac... | <!-- .github/pull_request_template.md -->
## 📌 Description
This PR introduces a series of optimizations to the trtllm_mnnvl_allreduce. These optimizations are also added by [https://github.com/NVIDIA/TensorRT-LLM/pull/5934](https://github.com/NVIDIA/TensorRT-LLM/pull/5934) and [https://github.com/NVIDIA/TensorRT-LLM... | [] | null | null |
flashinfer | 43e08e9b0fa58b4d51998ce20ca439771c8ac200 | 2025-07-25T04:21:27-07:00 | 1,321 | https://github.com/flashinfer-ai/flashinfer/pull/1321 | comm: Optimizations for TRTLLM MNNVL Allreduce (#1321) | comm: Optimizations for TRTLLM MNNVL Allreduce (#1321)
<!-- .github/pull_request_template.md -->
## 📌 Description
This PR introduces a series of optimizations to the
trtllm_mnnvl_allreduce. These optimizations are also added by
[https://github.com/NVIDIA/TensorRT-LLM/pull/5934](https://github.com/NVIDIA/TensorRT-LL... | include/flashinfer/comm/trtllm_mnnvl_allreduce.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- include/flashinfer/comm/trtllm_mnnvl_allreduce.cuh
+++ include/flashinfer/comm/trtllm_mnnvl_allreduce.cuh
@@ -63,6 +63,8 @@
__device__ bool isNegZero(__nv_bfloat16 val) { return isNegZero(__bfloat162float(val)); }
+__device__ bool isNegZero(__nv_half val) { return isNegZero(__half2float(val)); }
+
template <t... | 149 | 82 | 4 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/comm/trtllm_mnnvl_allreduce.cuh).
Goal: comm: Optimizations for TRTLLM MNNVL Allreduce
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved.
*
* License... | <!-- .github/pull_request_template.md -->
## 📌 Description
This PR introduces a series of optimizations to the trtllm_mnnvl_allreduce. These optimizations are also added by [https://github.com/NVIDIA/TensorRT-LLM/pull/5934](https://github.com/NVIDIA/TensorRT-LLM/pull/5934) and [https://github.com/NVIDIA/TensorRT-LLM... | [] | null | null |
flashinfer | 3f99f1867051924d6a7347df1fc1d2e50f7fd0e2 | 2025-07-21T23:20:55-07:00 | 1,298 | https://github.com/flashinfer-ai/flashinfer/pull/1298 | perfix: use lightweight API to query device property (#1298) | perfix: use lightweight API to query device property (#1298)
<!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re
needed. -->
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull Request Checklist
Thank you for contri... | csrc/trtllm_fused_moe_kernel_launcher.cu | cuda | Apache-2.0 | /*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distribut... | /*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distribut... | --- csrc/trtllm_fused_moe_kernel_launcher.cu
+++ csrc/trtllm_fused_moe_kernel_launcher.cu
@@ -56,11 +56,17 @@
bool const use_routing_scales_on_input, int64_t const tile_tokens_dim,
int64_t const routing_method_type) {
auto device = hidden_states.device();
- cudaDeviceProp prop;
- cudaGetDeviceProperties(... | 33 | 15 | 1 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (csrc/trtllm_fused_moe_kernel_launcher.cu).
Goal: perfix: use lightweight API to query device property
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use t... | <!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull Request Checklist
Thank you for contributing to FlashInfer! Before we review your pull request, plea... | [] | null | null |
flashinfer | 40db3fadfd5f361882dcd4cc797bd8867b7893a2 | 2025-06-30T15:10:25-07:00 | 1,200 | https://github.com/flashinfer-ai/flashinfer/pull/1200 | [feat] optimize persistent batch attention perf. (#1200) | [feat] optimize persistent batch attention perf. (#1200)
<!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re
needed. -->
This is a follow-up PR on
https://github.com/flashinfer-ai/flashinfer/pull/1137, optimizing
scheduling balance & red... | csrc/batch_attention.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/batch_attention.cu
+++ csrc/batch_attention.cu
@@ -68,7 +68,8 @@
at::Tensor v_cache, at::Tensor kv_indices, at::Tensor o,
std::optional<at::Tensor> maybe_lse, int64_t mask_mode_code,
int64_t layout_code, int64_t num_qo_heads... | 3 | 1 | 9 | [] | [
"H200"
] | [
"2x"
] | Optimize this cuda kernel file from flashinfer (csrc/batch_attention.cu).
Goal: [feat] optimize persistent batch attention perf.
Target hardware: H200
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* ... | <!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->
This is a follow-up PR on https://github.com/flashinfer-ai/flashinfer/pull/1137, optimizing scheduling balance & reduction overhead, and achieving 2x speedup. Optimization in... | [{"scope": "kernel", "hardware": "H200", "model": null, "shape": "head_dim=128, num_qo_heads=28, num_kv_heads=4, page_size=1", "batch_size": null, "metric": "performance", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 2.0, "speedup": 2.0}] | 2 | null |
flashinfer | 40db3fadfd5f361882dcd4cc797bd8867b7893a2 | 2025-06-30T15:10:25-07:00 | 1,200 | https://github.com/flashinfer-ai/flashinfer/pull/1200 | [feat] optimize persistent batch attention perf. (#1200) | [feat] optimize persistent batch attention perf. (#1200)
<!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re
needed. -->
This is a follow-up PR on
https://github.com/flashinfer-ai/flashinfer/pull/1137, optimizing
scheduling balance & red... | csrc/batch_attention_jit_pybind.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/batch_attention_jit_pybind.cu
+++ csrc/batch_attention_jit_pybind.cu
@@ -28,7 +28,8 @@
at::Tensor v_cache, at::Tensor kv_indices, at::Tensor o,
std::optional<at::Tensor> maybe_lse, int64_t mask_mode_code,
int64_t layout_code... | 2 | 1 | 9 | [] | [
"H200"
] | [
"2x"
] | Optimize this cuda kernel file from flashinfer (csrc/batch_attention_jit_pybind.cu).
Goal: [feat] optimize persistent batch attention perf.
Target hardware: H200
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "Lic... | <!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->
This is a follow-up PR on https://github.com/flashinfer-ai/flashinfer/pull/1137, optimizing scheduling balance & reduction overhead, and achieving 2x speedup. Optimization in... | [{"scope": "kernel", "hardware": "H200", "model": null, "shape": "head_dim=128, num_qo_heads=28, num_kv_heads=4, page_size=1", "batch_size": null, "metric": "performance", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 2.0, "speedup": 2.0}] | 2 | null |
flashinfer | 40db3fadfd5f361882dcd4cc797bd8867b7893a2 | 2025-06-30T15:10:25-07:00 | 1,200 | https://github.com/flashinfer-ai/flashinfer/pull/1200 | [feat] optimize persistent batch attention perf. (#1200) | [feat] optimize persistent batch attention perf. (#1200)
<!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re
needed. -->
This is a follow-up PR on
https://github.com/flashinfer-ai/flashinfer/pull/1137, optimizing
scheduling balance & red... | include/flashinfer/attention/cascade.cuh | cuda | Apache-2.0 | /*!
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or... | /*!
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or... | --- include/flashinfer/attention/cascade.cuh
+++ include/flashinfer/attention/cascade.cuh
@@ -125,6 +125,25 @@
s_smem[ty] = st.get_lse();
st.init();
__syncthreads();
+
+#pragma unroll
+ for (uint32_t iter = 0; iter < bdy; ++iter) {
+ float s = s_smem[iter];
+ vec_t<float, vec_size> v;
+ v.cast_load(v... | 19 | 0 | 9 | [] | [
"H200"
] | [
"2x"
] | Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/cascade.cuh).
Goal: [feat] optimize persistent batch attention perf.
Target hardware: H200
Target models: unspecified
Current file:
```cuda
/*!
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (t... | <!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->
This is a follow-up PR on https://github.com/flashinfer-ai/flashinfer/pull/1137, optimizing scheduling balance & reduction overhead, and achieving 2x speedup. Optimization in... | [{"scope": "kernel", "hardware": "H200", "model": null, "shape": "head_dim=128, num_qo_heads=28, num_kv_heads=4, page_size=1", "batch_size": null, "metric": "performance", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 2.0, "speedup": 2.0}] | 2 | null |
flashinfer | 40db3fadfd5f361882dcd4cc797bd8867b7893a2 | 2025-06-30T15:10:25-07:00 | 1,200 | https://github.com/flashinfer-ai/flashinfer/pull/1200 | [feat] optimize persistent batch attention perf. (#1200) | [feat] optimize persistent batch attention perf. (#1200)
<!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re
needed. -->
This is a follow-up PR on
https://github.com/flashinfer-ai/flashinfer/pull/1137, optimizing
scheduling balance & red... | include/flashinfer/attention/persistent.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/attention/persistent.cuh
+++ include/flashinfer/attention/persistent.cuh
@@ -144,7 +144,8 @@
using Params = Params_;
static __device__ __forceinline__ void Run(const Params& params,
- typename KTraits::SharedStorage* smem_storage) {
+ ... | 77 | 49 | 9 | [] | [
"H200"
] | [
"2x"
] | Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/persistent.cuh).
Goal: [feat] optimize persistent batch attention perf.
Target hardware: H200
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 ... | <!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->
This is a follow-up PR on https://github.com/flashinfer-ai/flashinfer/pull/1137, optimizing scheduling balance & reduction overhead, and achieving 2x speedup. Optimization in... | [{"scope": "kernel", "hardware": "H200", "model": null, "shape": "head_dim=128, num_qo_heads=28, num_kv_heads=4, page_size=1", "batch_size": null, "metric": "performance", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 2.0, "speedup": 2.0}] | 2 | null |
flashinfer | 40db3fadfd5f361882dcd4cc797bd8867b7893a2 | 2025-06-30T15:10:25-07:00 | 1,200 | https://github.com/flashinfer-ai/flashinfer/pull/1200 | [feat] optimize persistent batch attention perf. (#1200) | [feat] optimize persistent batch attention perf. (#1200)
<!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re
needed. -->
This is a follow-up PR on
https://github.com/flashinfer-ai/flashinfer/pull/1137, optimizing
scheduling balance & red... | include/flashinfer/attention/persistent_template.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/attention/persistent_template.cuh
+++ include/flashinfer/attention/persistent_template.cuh
@@ -30,8 +30,11 @@
enum class PersistentProfileEventType {
kRunner1 = 0U,
kRunner2 = 1U,
- kRunner3 = 2U,
- kRunner4 = 3U,
+ kReduction = 2U,
+};
+
+struct ProfilerClosure {
+ PROFILER_CLOSURE_PA... | 22 | 11 | 9 | [] | [
"H200"
] | [
"2x"
] | Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/persistent_template.cuh).
Goal: [feat] optimize persistent batch attention perf.
Target hardware: H200
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Ver... | <!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->
This is a follow-up PR on https://github.com/flashinfer-ai/flashinfer/pull/1137, optimizing scheduling balance & reduction overhead, and achieving 2x speedup. Optimization in... | [{"scope": "kernel", "hardware": "H200", "model": null, "shape": "head_dim=128, num_qo_heads=28, num_kv_heads=4, page_size=1", "batch_size": null, "metric": "performance", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 2.0, "speedup": 2.0}] | 2 | null |
flashinfer | 40db3fadfd5f361882dcd4cc797bd8867b7893a2 | 2025-06-30T15:10:25-07:00 | 1,200 | https://github.com/flashinfer-ai/flashinfer/pull/1200 | [feat] optimize persistent batch attention perf. (#1200) | [feat] optimize persistent batch attention perf. (#1200)
<!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re
needed. -->
This is a follow-up PR on
https://github.com/flashinfer-ai/flashinfer/pull/1137, optimizing
scheduling balance & red... | include/flashinfer/attention/scheduler.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/attention/scheduler.cuh
+++ include/flashinfer/attention/scheduler.cuh
@@ -1120,7 +1120,6 @@
int packed_qo_len = qo_len * gqa_group_size;
int kv_len = kv_len_arr_h[i];
- // TODO(Zihao): add more stages
if (packed_qo_len > CTA_TILE_Q_SIZES[1]) {
idx_qo_kv_len_vec[0].push... | 28 | 15 | 9 | [] | [
"H200"
] | [
"2x"
] | Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/scheduler.cuh).
Goal: [feat] optimize persistent batch attention perf.
Target hardware: H200
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (... | <!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->
This is a follow-up PR on https://github.com/flashinfer-ai/flashinfer/pull/1137, optimizing scheduling balance & reduction overhead, and achieving 2x speedup. Optimization in... | [{"scope": "kernel", "hardware": "H200", "model": null, "shape": "head_dim=128, num_qo_heads=28, num_kv_heads=4, page_size=1", "batch_size": null, "metric": "performance", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 2.0, "speedup": 2.0}] | 2 | null |
flashinfer | 40db3fadfd5f361882dcd4cc797bd8867b7893a2 | 2025-06-30T15:10:25-07:00 | 1,200 | https://github.com/flashinfer-ai/flashinfer/pull/1200 | [feat] optimize persistent batch attention perf. (#1200) | [feat] optimize persistent batch attention perf. (#1200)
<!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re
needed. -->
This is a follow-up PR on
https://github.com/flashinfer-ai/flashinfer/pull/1137, optimizing
scheduling balance & red... | include/flashinfer/profiler.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/profiler.cuh
+++ include/flashinfer/profiler.cuh
@@ -68,20 +68,23 @@
#ifdef FLASHINFER_ENABLE_PROFILER
#define PROFILER_CLOSURE_PARAMS_DECL \
+ ProfilerEntry entry; \
uint64_t* profiler_write_ptr; \
uint32_t profiler_write_stride; \
uint32_t profiler_entry_tag_... | 18 | 13 | 9 | [] | [
"H200"
] | [
"2x"
] | Optimize this cuda kernel file from flashinfer (include/flashinfer/profiler.cuh).
Goal: [feat] optimize persistent batch attention perf.
Target hardware: H200
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "Licens... | <!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->
This is a follow-up PR on https://github.com/flashinfer-ai/flashinfer/pull/1137, optimizing scheduling balance & reduction overhead, and achieving 2x speedup. Optimization in... | [{"scope": "kernel", "hardware": "H200", "model": null, "shape": "head_dim=128, num_qo_heads=28, num_kv_heads=4, page_size=1", "batch_size": null, "metric": "performance", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 2.0, "speedup": 2.0}] | 2 | null |
flashinfer | 4d92f008831aac4ef7adec1159d5b6d80c1f7831 | 2025-05-22T23:38:35-07:00 | 1,086 | https://github.com/flashinfer-ai/flashinfer/pull/1086 | perf: accelerate blackwell grouped gemm (#1086) | perf: accelerate blackwell grouped gemm (#1086) | csrc/group_gemm_groupwise_sm100.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/group_gemm_groupwise_sm100.cu
+++ csrc/group_gemm_groupwise_sm100.cu
@@ -19,6 +19,19 @@
#include "pytorch_extension_utils.h"
using namespace flashinfer;
+
+#define DISPATCH_MMA_SM(mma_sm, MMA_SM, ...) \
+ [&]() -> bool { \
+ if (mma_sm == 1) { \
+ ... | 33 | 18 | 4 | [] | [
"BLACKWELL"
] | [] | Optimize this cuda kernel file from flashinfer (csrc/group_gemm_groupwise_sm100.cu).
Goal: perf: accelerate blackwell grouped gemm
Target hardware: BLACKWELL
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License... | <!-- .github/pull_request_template.md -->
## 📌 Description
This PR reduce the grouped gemm overhead outside kernel itself:
1. remove the multiple of 4 check, and add notice in the documentation (the multiple ensurance should be guaranteed when we prepare these inputs, in an outer moe module).
2. use pdl for prepare a... | [] | null | null |
flashinfer | 4d92f008831aac4ef7adec1159d5b6d80c1f7831 | 2025-05-22T23:38:35-07:00 | 1,086 | https://github.com/flashinfer-ai/flashinfer/pull/1086 | perf: accelerate blackwell grouped gemm (#1086) | perf: accelerate blackwell grouped gemm (#1086) | csrc/group_gemm_sm100_pybind.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/group_gemm_sm100_pybind.cu
+++ csrc/group_gemm_sm100_pybind.cu
@@ -20,7 +20,7 @@
at::Tensor B, at::Tensor SFA, at::Tensor SFB,
at::Tensor C, at::Tensor m_indptr, int64_t n, int64_t k,
... | 1 | 1 | 4 | [] | [
"BLACKWELL"
] | [] | Optimize this cuda kernel file from flashinfer (csrc/group_gemm_sm100_pybind.cu).
Goal: perf: accelerate blackwell grouped gemm
Target hardware: BLACKWELL
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");... | <!-- .github/pull_request_template.md -->
## 📌 Description
This PR reduce the grouped gemm overhead outside kernel itself:
1. remove the multiple of 4 check, and add notice in the documentation (the multiple ensurance should be guaranteed when we prepare these inputs, in an outer moe module).
2. use pdl for prepare a... | [] | null | null |
flashinfer | 4d92f008831aac4ef7adec1159d5b6d80c1f7831 | 2025-05-22T23:38:35-07:00 | 1,086 | https://github.com/flashinfer-ai/flashinfer/pull/1086 | perf: accelerate blackwell grouped gemm (#1086) | perf: accelerate blackwell grouped gemm (#1086) | include/flashinfer/gemm/group_gemm_groupwise_sm100.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/gemm/group_gemm_groupwise_sm100.cuh
+++ include/flashinfer/gemm/group_gemm_groupwise_sm100.cuh
@@ -47,16 +47,20 @@
stride_C[i] = cutlass::make_cute_packed_stride(StrideC{}, {m, n, 1});
layout_SFA[i] = ScaleConfig::tile_atom_to_shape_SFA(make_shape(m_indptr[batch_size], n, k, 1));
layout_... | 46 | 18 | 4 | [] | [
"BLACKWELL"
] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/gemm/group_gemm_groupwise_sm100.cuh).
Goal: perf: accelerate blackwell grouped gemm
Target hardware: BLACKWELL
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Versi... | <!-- .github/pull_request_template.md -->
## 📌 Description
This PR reduce the grouped gemm overhead outside kernel itself:
1. remove the multiple of 4 check, and add notice in the documentation (the multiple ensurance should be guaranteed when we prepare these inputs, in an outer moe module).
2. use pdl for prepare a... | [] | null | null |
flashinfer | d7a9234263ef9a60161abc7419795fc8f101f451 | 2025-03-31T17:27:39-04:00 | 991 | https://github.com/flashinfer-ai/flashinfer/pull/991 | perf: prefetch page indices for mla kernel (#991) | perf: prefetch page indices for mla kernel (#991)
Followup of https://github.com/flashinfer-ai/flashinfer/pull/952
cc @abcdabcd987
## Before this PR
```
Config: batch_size=64, seq_len=1024, num_heads=64
Memory bandwidth: 1509.87 GB/s
FLOPs: 163.25 TFLOPs
Config: batch_size=64, seq_len=1024, num_heads=128
Memory ban... | include/flashinfer/attention/mla.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/attention/mla.cuh
+++ include/flashinfer/attention/mla.cuh
@@ -629,7 +629,7 @@
typename KTraits::IdType* merge_partial_stride, typename KTraits::DTypeO* partial_o,
float* partial_lse, typename KTraits::DTypeO* final_o, float* final_lse,
const uint32_t o_stride_n, const uint32_t o_s... | 1 | 1 | 2 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/mla.cuh).
Goal: perf: prefetch page indices for mla kernel
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "... | Followup of https://github.com/flashinfer-ai/flashinfer/pull/952
cc @abcdabcd987
## Before this PR
```
Config: batch_size=64, seq_len=1024, num_heads=64
Memory bandwidth: 1509.87 GB/s
FLOPs: 163.25 TFLOPs
Config: batch_size=64, seq_len=1024, num_heads=128
Memory bandwidth: 1766.19 GB/s
FLOPs: 345.46 TFLOPs
Config: b... | [{"scope": "kernel", "hardware": null, "model": null, "shape": "batch_size=64,seq_len=1024,num_heads=64", "batch_size": 64, "metric": "memory bandwidth", "unit": "GB/s", "higher_is_better": true, "baseline": 1509.87, "optimized": 1596.98, "stated_speedup": null, "speedup": 1.0577}, {"scope": "kernel", "hardware": null,... | 1.0053 | null |
flashinfer | d7a9234263ef9a60161abc7419795fc8f101f451 | 2025-03-31T17:27:39-04:00 | 991 | https://github.com/flashinfer-ai/flashinfer/pull/991 | perf: prefetch page indices for mla kernel (#991) | perf: prefetch page indices for mla kernel (#991)
Followup of https://github.com/flashinfer-ai/flashinfer/pull/952
cc @abcdabcd987
## Before this PR
```
Config: batch_size=64, seq_len=1024, num_heads=64
Memory bandwidth: 1509.87 GB/s
FLOPs: 163.25 TFLOPs
Config: batch_size=64, seq_len=1024, num_heads=128
Memory ban... | include/flashinfer/attention/mla_hopper.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/attention/mla_hopper.cuh
+++ include/flashinfer/attention/mla_hopper.cuh
@@ -170,20 +170,47 @@
}
}
+template <typename KTraits>
+__device__ __forceinline__ void prefetch_offset(
+ const uint32_t packed_block_iter_base, const uint32_t packed_kv_bound,
+ const uint32_t ckv_stride_page, ... | 57 | 24 | 2 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/mla_hopper.cuh).
Goal: perf: prefetch page indices for mla kernel
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0... | Followup of https://github.com/flashinfer-ai/flashinfer/pull/952
cc @abcdabcd987
## Before this PR
```
Config: batch_size=64, seq_len=1024, num_heads=64
Memory bandwidth: 1509.87 GB/s
FLOPs: 163.25 TFLOPs
Config: batch_size=64, seq_len=1024, num_heads=128
Memory bandwidth: 1766.19 GB/s
FLOPs: 345.46 TFLOPs
Config: b... | [{"scope": "kernel", "hardware": null, "model": null, "shape": "batch_size=64,seq_len=1024,num_heads=64", "batch_size": 64, "metric": "memory bandwidth", "unit": "GB/s", "higher_is_better": true, "baseline": 1509.87, "optimized": 1596.98, "stated_speedup": null, "speedup": 1.0577}, {"scope": "kernel", "hardware": null,... | 1.0053 | null |
flashinfer | 60d37b741f88f11159e7eec35e2261aa668dc2a4 | 2025-03-28T21:34:14-07:00 | 952 | https://github.com/flashinfer-ai/flashinfer/pull/952 | perf: Use 2WG pipeline design for MLA implementation on Hopper (#952) | perf: Use 2WG pipeline design for MLA implementation on Hopper (#952)
This PR implements #892 .
Per benchmark, 2WG pipeline (FlashMLA's implementation) is faster than
our current 3WG pipeline design on Hopper. While it remains
investigation where the gap comes from, we should implements the 2WG
(and 4WG in the future... | include/flashinfer/attention/mla_hopper.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/attention/mla_hopper.cuh
+++ include/flashinfer/attention/mla_hopper.cuh
@@ -44,7 +44,7 @@
kSplitK = 8U,
};
-enum class NamedBarriers { kBarrierQ = 1, kBarrierO = 2, kConsumerSync = 3 };
+enum class NamedBarriers { kOScaleReady = 1U, kBarrierO = 2U, kMDReady = 3U };
__device__ __forceinl... | 251 | 306 | 1 | [] | [
"HOPPER"
] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/mla_hopper.cuh).
Goal: perf: Use 2WG pipeline design for MLA implementation on Hopper
Target hardware: HOPPER
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache Licen... | This PR implements #892 .
Per benchmark, 2WG pipeline (FlashMLA's implementation) is faster than our current 3WG pipeline design on Hopper. While it remains investigation where the gap comes from, we should implements the 2WG (and 4WG in the future) pipeline in FlashInfer to make sure our implementation not getting wo... | [{"scope": "kernel", "hardware": null, "model": null, "shape": "seq_len=1024,num_heads=64", "batch_size": 64, "metric": "memory bandwidth", "unit": "GB/s", "higher_is_better": true, "baseline": 1547.23, "optimized": 1509.87, "stated_speedup": null, "speedup": 0.9759}, {"scope": "kernel", "hardware": null, "model": null... | 1.1521 | null |
flashinfer | e19cb7bafbd7c426e0d563c30418cbe4a02230c6 | 2025-03-27T02:04:55-07:00 | 974 | https://github.com/flashinfer-ai/flashinfer/pull/974 | perf: dual pivot top-p/top-k renorm (#974) | perf: dual pivot top-p/top-k renorm (#974)
Uses one more pivot and a fixed Block Threads of 1024 in the
sampling.renorm kernels. Benchmark and comparisons can be found
[here](https://docs.google.com/spreadsheets/d/15Qxh7fRxO2HiYaSxpyZs7sWQKoJ-8gscQFTG3rW_hZI/edit?usp=sharing).
---------
Co-authored-by: Zihao Ye <exp... | include/flashinfer/sampling.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/sampling.cuh
+++ include/flashinfer/sampling.cuh
@@ -943,9 +943,15 @@
float max_val;
float min_val;
union {
- float value;
- int count;
- ValueCount<float> pair;
+ struct {
+ float values[2];
+ };
+ struct {
+ int counts[2];
+ };
+ ... | 102 | 43 | 1 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/sampling.cuh).
Goal: perf: dual pivot top-p/top-k renorm
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
... | Uses one more pivot and a fixed Block Threads of 1024 in the sampling.renorm kernels. Benchmark and comparisons can be found [here](https://docs.google.com/spreadsheets/d/15Qxh7fRxO2HiYaSxpyZs7sWQKoJ-8gscQFTG3rW_hZI/edit?usp=sharing).
| [] | null | null |
flashinfer | e3853ddcab052582fca689646bdaad6dbd0d29b6 | 2025-03-09T18:12:32-04:00 | 925 | https://github.com/flashinfer-ai/flashinfer/pull/925 | perf: use max probability instead of 1 as upper bound in top-p/k sampling (#925) | perf: use max probability instead of 1 as upper bound in top-p/k sampling (#925)
Reduce maximum number of iterations. | include/flashinfer/sampling.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/sampling.cuh
+++ include/flashinfer/sampling.cuh
@@ -25,6 +25,7 @@
#include <cub/block/block_scan.cuh>
#include <cuda/std/limits>
#include <numeric>
+#include <tuple>
#include "math.cuh"
#include "utils.cuh"
@@ -97,10 +98,10 @@
struct {
int32_t sampled_id;
int32_t last_valid_i... | 106 | 103 | 1 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/sampling.cuh).
Goal: perf: use max probability instead of 1 as upper bound in top-p/k sampling
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache L... | Reduce maximum number of iterations.
| [] | null | null |
flashinfer | 0ed1ce8377d06747c2e9c6b39012f63ef5fad9ef | 2025-02-27T00:55:29-05:00 | 901 | https://github.com/flashinfer-ai/flashinfer/pull/901 | perf: tweak the pipeline design of mla kernel (#901) | perf: tweak the pipeline design of mla kernel (#901)
1. defer barrier sync for `p_smem`
2. change unroll number from 1 to 2
We found there are still significant overhead for synchronizing two
consumers in qk stage. Use only one warpgroup for qk can resolve the
issue. | include/flashinfer/attention/mla_hopper.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/attention/mla_hopper.cuh
+++ include/flashinfer/attention/mla_hopper.cuh
@@ -275,6 +275,7 @@
template <typename KTraits>
__device__ __forceinline__ void compute_mla_pv(typename KTraits::SharedStorage* smem_storage,
const uint32_t stage_idx, float*... | 2 | 2 | 1 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/mla_hopper.cuh).
Goal: perf: tweak the pipeline design of mla kernel
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version ... | 1. defer barrier sync for `p_smem`
2. change unroll number from 1 to 2
We found there are still significant overhead for synchronizing two consumers in qk stage. Use only one warpgroup for qk can resolve the issue.
| [] | null | null |
flashinfer | e4a68e4a84626a5e823bbec31a80f8194047d8d9 | 2025-02-26T23:00:22-05:00 | 900 | https://github.com/flashinfer-ai/flashinfer/pull/900 | perf: use f16 as split-k partial output data type (#900) | perf: use f16 as split-k partial output data type (#900)
We use f32 as split-k partial output data type, mainly for accuracy
concern.
However, the official FlashMLA implementation uses 16-bit partial data
type, so I guess 16bit split-k is enough for production.
This PR changes flashinfer mla implementation's intermedi... | csrc/batch_mla_run.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/batch_mla_run.cu
+++ csrc/batch_mla_run.cu
@@ -95,7 +95,7 @@
params.final_lse =
maybe_lse.has_value() ? static_cast<float*>(maybe_lse->data_ptr()) : nullptr;
params.partial_o =
- GetPtrFromBaseOffset<float>(float_buffer_ptr, plan_info.partial_o_offset);
+ Ge... | 1 | 1 | 6 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (csrc/batch_mla_run.cu).
Goal: perf: use f16 as split-k partial output data type
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License"... | We use f32 as split-k partial output data type, mainly for accuracy concern.
However, the official FlashMLA implementation uses 16-bit partial data type, so I guess 16bit split-k is enough for production.
This PR changes flashinfer mla implementation's intermediate data type to 16bit.
This is the third piece (4 in tot... | [] | null | null |
flashinfer | e4a68e4a84626a5e823bbec31a80f8194047d8d9 | 2025-02-26T23:00:22-05:00 | 900 | https://github.com/flashinfer-ai/flashinfer/pull/900 | perf: use f16 as split-k partial output data type (#900) | perf: use f16 as split-k partial output data type (#900)
We use f32 as split-k partial output data type, mainly for accuracy
concern.
However, the official FlashMLA implementation uses 16-bit partial data
type, so I guess 16bit split-k is enough for production.
This PR changes flashinfer mla implementation's intermedi... | csrc/batch_mla_sm90_run.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/batch_mla_sm90_run.cu
+++ csrc/batch_mla_sm90_run.cu
@@ -96,7 +96,7 @@
params.final_lse =
maybe_lse.has_value() ? static_cast<float*>(maybe_lse->data_ptr()) : nullptr;
params.partial_o =
- GetPtrFromBaseOffset<float>(float_buffer_ptr, plan_info.partial_o_offset);
+ ... | 1 | 1 | 6 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (csrc/batch_mla_sm90_run.cu).
Goal: perf: use f16 as split-k partial output data type
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "Lic... | We use f32 as split-k partial output data type, mainly for accuracy concern.
However, the official FlashMLA implementation uses 16-bit partial data type, so I guess 16bit split-k is enough for production.
This PR changes flashinfer mla implementation's intermediate data type to 16bit.
This is the third piece (4 in tot... | [] | null | null |
flashinfer | e4a68e4a84626a5e823bbec31a80f8194047d8d9 | 2025-02-26T23:00:22-05:00 | 900 | https://github.com/flashinfer-ai/flashinfer/pull/900 | perf: use f16 as split-k partial output data type (#900) | perf: use f16 as split-k partial output data type (#900)
We use f32 as split-k partial output data type, mainly for accuracy
concern.
However, the official FlashMLA implementation uses 16-bit partial data
type, so I guess 16bit split-k is enough for production.
This PR changes flashinfer mla implementation's intermedi... | include/flashinfer/attention/mla.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/attention/mla.cuh
+++ include/flashinfer/attention/mla.cuh
@@ -620,9 +620,9 @@
typename KTraits::IdType* merge_packed_offset_end,
typename KTraits::IdType* merge_partial_packed_offset_start,
typename KTraits::IdType* merge_partial_packed_offset_end,
- typename KTraits::IdType* m... | 50 | 48 | 6 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/mla.cuh).
Goal: perf: use f16 as split-k partial output data type
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0... | We use f32 as split-k partial output data type, mainly for accuracy concern.
However, the official FlashMLA implementation uses 16-bit partial data type, so I guess 16bit split-k is enough for production.
This PR changes flashinfer mla implementation's intermediate data type to 16bit.
This is the third piece (4 in tot... | [] | null | null |
flashinfer | e4a68e4a84626a5e823bbec31a80f8194047d8d9 | 2025-02-26T23:00:22-05:00 | 900 | https://github.com/flashinfer-ai/flashinfer/pull/900 | perf: use f16 as split-k partial output data type (#900) | perf: use f16 as split-k partial output data type (#900)
We use f32 as split-k partial output data type, mainly for accuracy
concern.
However, the official FlashMLA implementation uses 16-bit partial data
type, so I guess 16bit split-k is enough for production.
This PR changes flashinfer mla implementation's intermedi... | include/flashinfer/attention/mla_hopper.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/attention/mla_hopper.cuh
+++ include/flashinfer/attention/mla_hopper.cuh
@@ -441,11 +441,14 @@
}
template <typename KTraits>
-__device__ __forceinline__ void write_o(
- typename KTraits::SharedStorage* smem_storage, const uint32_t stage_counter,
- typename KTraits::DTypeO* final_o, floa... | 53 | 48 | 6 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/mla_hopper.cuh).
Goal: perf: use f16 as split-k partial output data type
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Vers... | We use f32 as split-k partial output data type, mainly for accuracy concern.
However, the official FlashMLA implementation uses 16-bit partial data type, so I guess 16bit split-k is enough for production.
This PR changes flashinfer mla implementation's intermediate data type to 16bit.
This is the third piece (4 in tot... | [] | null | null |
flashinfer | e4a68e4a84626a5e823bbec31a80f8194047d8d9 | 2025-02-26T23:00:22-05:00 | 900 | https://github.com/flashinfer-ai/flashinfer/pull/900 | perf: use f16 as split-k partial output data type (#900) | perf: use f16 as split-k partial output data type (#900)
We use f32 as split-k partial output data type, mainly for accuracy
concern.
However, the official FlashMLA implementation uses 16-bit partial data
type, so I guess 16bit split-k is enough for production.
This PR changes flashinfer mla implementation's intermedi... | include/flashinfer/attention/mla_params.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/attention/mla_params.cuh
+++ include/flashinfer/attention/mla_params.cuh
@@ -32,7 +32,7 @@
DTypeQ* q_pe;
DTypeKV* ckv;
DTypeKV* kpe;
- float* partial_o;
+ DTypeO* partial_o;
float* partial_lse;
DTypeO* final_o;
float* final_lse; | 1 | 1 | 6 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/mla_params.cuh).
Goal: perf: use f16 as split-k partial output data type
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Vers... | We use f32 as split-k partial output data type, mainly for accuracy concern.
However, the official FlashMLA implementation uses 16-bit partial data type, so I guess 16bit split-k is enough for production.
This PR changes flashinfer mla implementation's intermediate data type to 16bit.
This is the third piece (4 in tot... | [] | null | null |
flashinfer | e4a68e4a84626a5e823bbec31a80f8194047d8d9 | 2025-02-26T23:00:22-05:00 | 900 | https://github.com/flashinfer-ai/flashinfer/pull/900 | perf: use f16 as split-k partial output data type (#900) | perf: use f16 as split-k partial output data type (#900)
We use f32 as split-k partial output data type, mainly for accuracy
concern.
However, the official FlashMLA implementation uses 16-bit partial data
type, so I guess 16bit split-k is enough for production.
This PR changes flashinfer mla implementation's intermedi... | include/flashinfer/attention/scheduler.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/attention/scheduler.cuh
+++ include/flashinfer/attention/scheduler.cuh
@@ -1104,7 +1104,21 @@
total_kv_lens += effective_kv_len;
}
}
- int kv_len_limit = ceil_div(std::max(ceil_div(total_kv_lens, num_clusters), 1L), 256L) * 256L;
+
+ auto f = [](int x) {
+ if (x <= 8) {
+ ... | 17 | 2 | 6 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/scheduler.cuh).
Goal: perf: use f16 as split-k partial output data type
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Versi... | We use f32 as split-k partial output data type, mainly for accuracy concern.
However, the official FlashMLA implementation uses 16-bit partial data type, so I guess 16bit split-k is enough for production.
This PR changes flashinfer mla implementation's intermediate data type to 16bit.
This is the third piece (4 in tot... | [] | null | null |
flashinfer | 1e330b712c23315d76d9f1692a0a225623666d1a | 2025-02-25T20:32:04-05:00 | 898 | https://github.com/flashinfer-ai/flashinfer/pull/898 | perf: fix MLA split-k performance bug (#898) | perf: fix MLA split-k performance bug (#898)
As observed in #892 , we found flashinfer mla's second stage of split-k
is very slow (when batch size is small), this is because our scheduler
only uses one CTA for the second stage of split-k.
This PR fixes the issue. | csrc/batch_mla_run.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/batch_mla_run.cu
+++ csrc/batch_mla_run.cu
@@ -85,8 +85,12 @@
int_buffer_ptr, plan_info.merge_packed_offset_start_offset);
params.merge_packed_offset_end =
GetPtrFromBaseOffset<IdType>(int_buffer_ptr, plan_info.merge_packed_offset_end_offset);
- params.merge_indptr =
-... | 6 | 2 | 6 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (csrc/batch_mla_run.cu).
Goal: perf: fix MLA split-k performance bug
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you ma... | As observed in #892 , we found flashinfer mla's second stage of split-k is very slow (when batch size is small), this is because our scheduler only uses one CTA for the second stage of split-k.
This PR fixes the issue.
| [] | null | null |
flashinfer | 1e330b712c23315d76d9f1692a0a225623666d1a | 2025-02-25T20:32:04-05:00 | 898 | https://github.com/flashinfer-ai/flashinfer/pull/898 | perf: fix MLA split-k performance bug (#898) | perf: fix MLA split-k performance bug (#898)
As observed in #892 , we found flashinfer mla's second stage of split-k
is very slow (when batch size is small), this is because our scheduler
only uses one CTA for the second stage of split-k.
This PR fixes the issue. | csrc/batch_mla_sm90_run.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/batch_mla_sm90_run.cu
+++ csrc/batch_mla_sm90_run.cu
@@ -86,8 +86,12 @@
int_buffer_ptr, plan_info.merge_packed_offset_start_offset);
params.merge_packed_offset_end =
GetPtrFromBaseOffset<IdType>(int_buffer_ptr, plan_info.merge_packed_offset_end_offset);
- params.merge_... | 6 | 2 | 6 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (csrc/batch_mla_sm90_run.cu).
Goal: perf: fix MLA split-k performance bug
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* y... | As observed in #892 , we found flashinfer mla's second stage of split-k is very slow (when batch size is small), this is because our scheduler only uses one CTA for the second stage of split-k.
This PR fixes the issue.
| [] | null | null |
flashinfer | 1e330b712c23315d76d9f1692a0a225623666d1a | 2025-02-25T20:32:04-05:00 | 898 | https://github.com/flashinfer-ai/flashinfer/pull/898 | perf: fix MLA split-k performance bug (#898) | perf: fix MLA split-k performance bug (#898)
As observed in #892 , we found flashinfer mla's second stage of split-k
is very slow (when batch size is small), this is because our scheduler
only uses one CTA for the second stage of split-k.
This PR fixes the issue. | include/flashinfer/attention/mla.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/attention/mla.cuh
+++ include/flashinfer/attention/mla.cuh
@@ -615,28 +615,27 @@
}
template <typename KTraits>
-__device__ void DevicePersistentMergeStates(typename KTraits::IdType* merge_packed_offset_start,
- typename KTraits::IdType* merge_packed_... | 22 | 22 | 6 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/mla.cuh).
Goal: perf: fix MLA split-k performance bug
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "Licen... | As observed in #892 , we found flashinfer mla's second stage of split-k is very slow (when batch size is small), this is because our scheduler only uses one CTA for the second stage of split-k.
This PR fixes the issue.
| [] | null | null |
flashinfer | 1e330b712c23315d76d9f1692a0a225623666d1a | 2025-02-25T20:32:04-05:00 | 898 | https://github.com/flashinfer-ai/flashinfer/pull/898 | perf: fix MLA split-k performance bug (#898) | perf: fix MLA split-k performance bug (#898)
As observed in #892 , we found flashinfer mla's second stage of split-k
is very slow (when batch size is small), this is because our scheduler
only uses one CTA for the second stage of split-k.
This PR fixes the issue. | include/flashinfer/attention/mla_hopper.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/attention/mla_hopper.cuh
+++ include/flashinfer/attention/mla_hopper.cuh
@@ -838,10 +838,11 @@
__syncthreads();
// the second stage, merge partial outputs
- DevicePersistentMergeStates<KTraits>(params.merge_packed_offset_start,
- params.merge_packed_... | 5 | 4 | 6 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/mla_hopper.cuh).
Goal: perf: fix MLA split-k performance bug
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the... | As observed in #892 , we found flashinfer mla's second stage of split-k is very slow (when batch size is small), this is because our scheduler only uses one CTA for the second stage of split-k.
This PR fixes the issue.
| [] | null | null |
flashinfer | 1e330b712c23315d76d9f1692a0a225623666d1a | 2025-02-25T20:32:04-05:00 | 898 | https://github.com/flashinfer-ai/flashinfer/pull/898 | perf: fix MLA split-k performance bug (#898) | perf: fix MLA split-k performance bug (#898)
As observed in #892 , we found flashinfer mla's second stage of split-k
is very slow (when batch size is small), this is because our scheduler
only uses one CTA for the second stage of split-k.
This PR fixes the issue. | include/flashinfer/attention/mla_params.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/attention/mla_params.cuh
+++ include/flashinfer/attention/mla_params.cuh
@@ -42,7 +42,9 @@
IdType* partial_indptr;
IdType* merge_packed_offset_start;
IdType* merge_packed_offset_end;
- IdType* merge_indptr;
+ IdType* merge_partial_packed_offset_start;
+ IdType* merge_partial_packed_of... | 3 | 1 | 6 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/mla_params.cuh).
Goal: perf: fix MLA split-k performance bug
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the... | As observed in #892 , we found flashinfer mla's second stage of split-k is very slow (when batch size is small), this is because our scheduler only uses one CTA for the second stage of split-k.
This PR fixes the issue.
| [] | null | null |
flashinfer | 1e330b712c23315d76d9f1692a0a225623666d1a | 2025-02-25T20:32:04-05:00 | 898 | https://github.com/flashinfer-ai/flashinfer/pull/898 | perf: fix MLA split-k performance bug (#898) | perf: fix MLA split-k performance bug (#898)
As observed in #892 , we found flashinfer mla's second stage of split-k
is very slow (when batch size is small), this is because our scheduler
only uses one CTA for the second stage of split-k.
This PR fixes the issue. | include/flashinfer/attention/scheduler.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/attention/scheduler.cuh
+++ include/flashinfer/attention/scheduler.cuh
@@ -989,7 +989,9 @@
int64_t partial_indptr_offset;
int64_t merge_packed_offset_start_offset;
int64_t merge_packed_offset_end_offset;
- int64_t merge_indptr_offset;
+ int64_t merge_partial_packed_offset_start_offset;... | 83 | 36 | 6 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/scheduler.cuh).
Goal: perf: fix MLA split-k performance bug
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the ... | As observed in #892 , we found flashinfer mla's second stage of split-k is very slow (when batch size is small), this is because our scheduler only uses one CTA for the second stage of split-k.
This PR fixes the issue.
| [] | null | null |
flashinfer | 56e56ea4e22fc7cf5ca3b41f8143e8847eb5f3fa | 2025-02-24T12:41:10-05:00 | 896 | https://github.com/flashinfer-ai/flashinfer/pull/896 | perf: tweak register amount for producer/consumer in MLA template (#896) | perf: tweak register amount for producer/consumer in MLA template (#896)
56, 224 is faster. | include/flashinfer/attention/mla_hopper.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/attention/mla_hopper.cuh
+++ include/flashinfer/attention/mla_hopper.cuh
@@ -626,7 +626,7 @@
if (warp_group_idx == 0) {
// producer
- cutlass::arch::warpgroup_reg_dealloc<72>();
+ cutlass::arch::warpgroup_reg_dealloc<56>();
const uint32_t warp_idx_in_warpgroup = __shfl_sync(0... | 2 | 2 | 1 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/mla_hopper.cuh).
Goal: perf: tweak register amount for producer/consumer in MLA template
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apac... | 56, 224 is faster.
| [] | null | null |
flashinfer | 341ae09ecd33c441de6060ef51c5f369ec020694 | 2025-02-24T03:01:09-05:00 | 894 | https://github.com/flashinfer-ai/flashinfer/pull/894 | perf: fix the performance of stage stage of split-k (#894) | perf: fix the performance of stage stage of split-k (#894)
As pointed in
https://github.com/flashinfer-ai/flashinfer/issues/892#issuecomment-2677596676
The second stage of split-k seems to have a huge overhead. This PR is
the first second in addressing these issues, by changing the vector size
from 4 to 8. | include/flashinfer/attention/mla.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/attention/mla.cuh
+++ include/flashinfer/attention/mla.cuh
@@ -623,7 +623,7 @@
const uint32_t o_stride_n, const uint32_t o_stride_h,
const uint32_t cluster_tile_q,
... | 2 | 2 | 1 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/mla.cuh).
Goal: perf: fix the performance of stage stage of split-k
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2... | As pointed in https://github.com/flashinfer-ai/flashinfer/issues/892#issuecomment-2677596676 The second stage of split-k seems to have a huge overhead. This PR is the first attempt in addressing these issues, by changing the vector size from 4 to 8.
| [] | null | null |
flashinfer | 2b24293bc7dd6536596a0fc06ebc1ddc490a113a | 2025-02-23T06:37:57-05:00 | 887 | https://github.com/flashinfer-ai/flashinfer/pull/887 | perf: FlashAttention-3 style MLA PageAttention (#887) | perf: FlashAttention-3 style MLA PageAttention (#887)
This PR is the followup of #804 , we implemented a FlashAttention-3
version of warp specialization pattern (splitting on head-dimension) in
#804 for faster attention on Hopper GPUs. Compared to the previous
version (in FA2 style), this PR did the following changes:... | csrc/batch_mla_run.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/batch_mla_run.cu
+++ csrc/batch_mla_run.cu
@@ -13,7 +13,7 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
-#include <flashinfer/attention/mla_fa2.cuh>
+#include <flashinfer/attention/mla.cuh>
#include <flashinfer/attention/scheduler.cuh>
#inc... | 1 | 1 | 5 | [] | [
"H100",
"HOPPER"
] | [] | Optimize this cuda kernel file from flashinfer (csrc/batch_mla_run.cu).
Goal: perf: FlashAttention-3 style MLA PageAttention
Target hardware: H100, HOPPER
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");... | This PR is the followup of #804 , we implemented a FlashAttention-3 version of warp specialization pattern (splitting on head-dimension) in #804 for faster attention on Hopper GPUs. Compared to the previous version (in FA2 style), this PR did the following changes:
1. use one warpgroup for producer, two warpgroup for... | [{"scope": "kernel", "hardware": "H100 SXM3", "model": null, "shape": "seq_len=1024,num_heads=64", "batch_size": 64, "metric": "memory bandwidth", "unit": "GB/s", "higher_is_better": true, "baseline": 1067.74, "optimized": 1305.4, "stated_speedup": null, "speedup": 1.2226}, {"scope": "kernel", "hardware": "H100 SXM3", ... | 1.2979 | null |
flashinfer | 2b24293bc7dd6536596a0fc06ebc1ddc490a113a | 2025-02-23T06:37:57-05:00 | 887 | https://github.com/flashinfer-ai/flashinfer/pull/887 | perf: FlashAttention-3 style MLA PageAttention (#887) | perf: FlashAttention-3 style MLA PageAttention (#887)
This PR is the followup of #804 , we implemented a FlashAttention-3
version of warp specialization pattern (splitting on head-dimension) in
#804 for faster attention on Hopper GPUs. Compared to the previous
version (in FA2 style), this PR did the following changes:... | include/flashinfer/attention/hopper/epilogue.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2024, Jay Shah, Ganesh Bikshandi, Ying Zhang, Vijay Thakkar, Pradeep Ramani, Tri
* Dao. Licensed under the BSD 3-Clause.
*
* Modified by the FlashInfer team.
*/
#ifndef FLASHINFER_ATTENTION_HOPPER_EPILOGUE_CUH_
#define FLASHINFER_ATTENTION_HOPPER_EPILOGUE_CUH_
#include <cutlass/cutlass.h>
#inc... | /*
* Copyright (c) 2024, Jay Shah, Ganesh Bikshandi, Ying Zhang, Vijay Thakkar, Pradeep Ramani, Tri
* Dao. Licensed under the BSD 3-Clause.
*
* Modified by the FlashInfer team.
*/
#ifndef FLASHINFER_ATTENTION_HOPPER_EPILOGUE_CUH_
#define FLASHINFER_ATTENTION_HOPPER_EPILOGUE_CUH_
#include <cutlass/cutlass.h>
#inc... | --- include/flashinfer/attention/hopper/epilogue.cuh
+++ include/flashinfer/attention/hopper/epilogue.cuh
@@ -160,13 +160,13 @@
auto smem_thr_copy_O = smem_tiled_copy_O.get_thread_slice(thread_idx);
Tensor tOrO_out = convert_type<DTypeO>(tOrO);
- Tensor taccOrO = smem_thr_copy_O.retile_S(tOrO_out); // (... | 13 | 13 | 5 | [] | [
"H100",
"HOPPER"
] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/hopper/epilogue.cuh).
Goal: perf: FlashAttention-3 style MLA PageAttention
Target hardware: H100, HOPPER
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2024, Jay Shah, Ganesh Bikshandi, Ying Zhang, Vijay Thakkar, Pradee... | This PR is the followup of #804 , we implemented a FlashAttention-3 version of warp specialization pattern (splitting on head-dimension) in #804 for faster attention on Hopper GPUs. Compared to the previous version (in FA2 style), this PR did the following changes:
1. use one warpgroup for producer, two warpgroup for... | [{"scope": "kernel", "hardware": "H100 SXM3", "model": null, "shape": "seq_len=1024,num_heads=64", "batch_size": 64, "metric": "memory bandwidth", "unit": "GB/s", "higher_is_better": true, "baseline": 1067.74, "optimized": 1305.4, "stated_speedup": null, "speedup": 1.2226}, {"scope": "kernel", "hardware": "H100 SXM3", ... | 1.2979 | null |
flashinfer | 41a4f5618179f0366ef814951efac6d5a2f967b3 | 2025-02-17T07:30:20-08:00 | 863 | https://github.com/flashinfer-ai/flashinfer/pull/863 | perf: dynamic split-k for MLA (#863) | perf: dynamic split-k for MLA (#863)
#804 didn't implement split-k, which might result in performance
degradation if concurrency is not large enough. This PR fixes issue.
We implemented the v2 scheduler and write-through optimization mentioned
in [our paper](https://arxiv.org/pdf/2501.01005) (section 3.3 and
appendix... | csrc/batch_mla_run.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/batch_mla_run.cu
+++ csrc/batch_mla_run.cu
@@ -71,6 +71,8 @@
params.q_indptr = GetPtrFromBaseOffset<IdType>(int_buffer_ptr, plan_info.q_indptr_offset);
params.kv_indptr = GetPtrFromBaseOffset<IdType>(int_buffer_ptr, plan_info.kv_indptr_offset);
+ params.partial_indptr =
+ ... | 8 | 0 | 5 | [] | [
"H100"
] | [] | Optimize this cuda kernel file from flashinfer (csrc/batch_mla_run.cu).
Goal: perf: dynamic split-k for MLA
Target hardware: H100
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this ... | #804 didn't implement split-k, which might result in performance degradation if concurrency is not large enough. This PR fixes issue.
We implemented the v2 scheduler and write-through optimization mentioned in [our paper](https://arxiv.org/pdf/2501.01005) (section 3.3 and appendix in D.2) for load-balancing.
In an ea... | [{"scope": "kernel", "hardware": "H100", "model": null, "shape": "seq_len=1024,num_heads=16", "batch_size": 1, "metric": "memory bandwidth", "unit": "GB/s", "higher_is_better": true, "baseline": 15.46, "optimized": 22.33, "stated_speedup": null, "speedup": 1.4444}, {"scope": "kernel", "hardware": "H100", "model": null,... | 2.7115 | null |
flashinfer | 41a4f5618179f0366ef814951efac6d5a2f967b3 | 2025-02-17T07:30:20-08:00 | 863 | https://github.com/flashinfer-ai/flashinfer/pull/863 | perf: dynamic split-k for MLA (#863) | perf: dynamic split-k for MLA (#863)
#804 didn't implement split-k, which might result in performance
degradation if concurrency is not large enough. This PR fixes issue.
We implemented the v2 scheduler and write-through optimization mentioned
in [our paper](https://arxiv.org/pdf/2501.01005) (section 3.3 and
appendix... | include/flashinfer/attention/cascade.cuh | cuda | Apache-2.0 | /*!
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or... | /*!
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or... | --- include/flashinfer/attention/cascade.cuh
+++ include/flashinfer/attention/cascade.cuh
@@ -16,8 +16,6 @@
#ifndef FLASHINFER_CASCADE_CUH_
#define FLASHINFER_CASCADE_CUH_
-#include <cooperative_groups.h>
-
#include "../cp_async.cuh"
#include "../math.cuh"
#include "../utils.cuh"
@@ -25,7 +23,6 @@
namespace f... | 2 | 5 | 5 | [] | [
"H100"
] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/cascade.cuh).
Goal: perf: dynamic split-k for MLA
Target hardware: H100
Target models: unspecified
Current file:
```cuda
/*!
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* y... | #804 didn't implement split-k, which might result in performance degradation if concurrency is not large enough. This PR fixes issue.
We implemented the v2 scheduler and write-through optimization mentioned in [our paper](https://arxiv.org/pdf/2501.01005) (section 3.3 and appendix in D.2) for load-balancing.
In an ea... | [{"scope": "kernel", "hardware": "H100", "model": null, "shape": "seq_len=1024,num_heads=16", "batch_size": 1, "metric": "memory bandwidth", "unit": "GB/s", "higher_is_better": true, "baseline": 15.46, "optimized": 22.33, "stated_speedup": null, "speedup": 1.4444}, {"scope": "kernel", "hardware": "H100", "model": null,... | 2.7115 | null |
flashinfer | 41a4f5618179f0366ef814951efac6d5a2f967b3 | 2025-02-17T07:30:20-08:00 | 863 | https://github.com/flashinfer-ai/flashinfer/pull/863 | perf: dynamic split-k for MLA (#863) | perf: dynamic split-k for MLA (#863)
#804 didn't implement split-k, which might result in performance
degradation if concurrency is not large enough. This PR fixes issue.
We implemented the v2 scheduler and write-through optimization mentioned
in [our paper](https://arxiv.org/pdf/2501.01005) (section 3.3 and
appendix... | include/flashinfer/attention/mla_fa2.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/attention/mla_fa2.cuh
+++ include/flashinfer/attention/mla_fa2.cuh
@@ -15,6 +15,8 @@
*/
#ifndef FLASHINFER_MLA_FA2_CUH_
#define FLASHINFER_MLA_FA2_CUH_
+#include <cooperative_groups.h>
+
#include <cstdint>
#include <sstream>
@@ -90,7 +92,6 @@
static constexpr uint32_t UPCAST_STRIDE_KPE... | 110 | 22 | 5 | [] | [
"H100"
] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/mla_fa2.cuh).
Goal: perf: dynamic split-k for MLA
Target hardware: H100
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* yo... | #804 didn't implement split-k, which might result in performance degradation if concurrency is not large enough. This PR fixes issue.
We implemented the v2 scheduler and write-through optimization mentioned in [our paper](https://arxiv.org/pdf/2501.01005) (section 3.3 and appendix in D.2) for load-balancing.
In an ea... | [{"scope": "kernel", "hardware": "H100", "model": null, "shape": "seq_len=1024,num_heads=16", "batch_size": 1, "metric": "memory bandwidth", "unit": "GB/s", "higher_is_better": true, "baseline": 15.46, "optimized": 22.33, "stated_speedup": null, "speedup": 1.4444}, {"scope": "kernel", "hardware": "H100", "model": null,... | 2.7115 | null |
flashinfer | 41a4f5618179f0366ef814951efac6d5a2f967b3 | 2025-02-17T07:30:20-08:00 | 863 | https://github.com/flashinfer-ai/flashinfer/pull/863 | perf: dynamic split-k for MLA (#863) | perf: dynamic split-k for MLA (#863)
#804 didn't implement split-k, which might result in performance
degradation if concurrency is not large enough. This PR fixes issue.
We implemented the v2 scheduler and write-through optimization mentioned
in [our paper](https://arxiv.org/pdf/2501.01005) (section 3.3 and
appendix... | include/flashinfer/attention/mla_params.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/attention/mla_params.cuh
+++ include/flashinfer/attention/mla_params.cuh
@@ -39,6 +39,10 @@
IdType* q_indptr;
IdType* kv_indptr;
+ IdType* partial_indptr;
+ IdType* merge_packed_offset_start;
+ IdType* merge_packed_offset_end;
+ IdType* merge_indptr;
IdType* kv_indices;
IdType* ... | 4 | 0 | 5 | [] | [
"H100"
] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/mla_params.cuh).
Goal: perf: dynamic split-k for MLA
Target hardware: H100
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
*... | #804 didn't implement split-k, which might result in performance degradation if concurrency is not large enough. This PR fixes issue.
We implemented the v2 scheduler and write-through optimization mentioned in [our paper](https://arxiv.org/pdf/2501.01005) (section 3.3 and appendix in D.2) for load-balancing.
In an ea... | [{"scope": "kernel", "hardware": "H100", "model": null, "shape": "seq_len=1024,num_heads=16", "batch_size": 1, "metric": "memory bandwidth", "unit": "GB/s", "higher_is_better": true, "baseline": 15.46, "optimized": 22.33, "stated_speedup": null, "speedup": 1.4444}, {"scope": "kernel", "hardware": "H100", "model": null,... | 2.7115 | null |
flashinfer | 41a4f5618179f0366ef814951efac6d5a2f967b3 | 2025-02-17T07:30:20-08:00 | 863 | https://github.com/flashinfer-ai/flashinfer/pull/863 | perf: dynamic split-k for MLA (#863) | perf: dynamic split-k for MLA (#863)
#804 didn't implement split-k, which might result in performance
degradation if concurrency is not large enough. This PR fixes issue.
We implemented the v2 scheduler and write-through optimization mentioned
in [our paper](https://arxiv.org/pdf/2501.01005) (section 3.3 and
appendix... | include/flashinfer/attention/scheduler.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/attention/scheduler.cuh
+++ include/flashinfer/attention/scheduler.cuh
@@ -44,10 +44,10 @@
__global__ void BatchDecodeWithPagedKVCacheKernelMLA(Params params);
template <uint32_t HEAD_DIM_CKV, uint32_t HEAD_DIM_KPE, uint32_t QO_TILE_LEN, typename DTypeKV>
-std::tuple<uint32_t, uint32_t, uint3... | 145 | 49 | 5 | [] | [
"H100"
] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/scheduler.cuh).
Goal: perf: dynamic split-k for MLA
Target hardware: H100
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* ... | #804 didn't implement split-k, which might result in performance degradation if concurrency is not large enough. This PR fixes issue.
We implemented the v2 scheduler and write-through optimization mentioned in [our paper](https://arxiv.org/pdf/2501.01005) (section 3.3 and appendix in D.2) for load-balancing.
In an ea... | [{"scope": "kernel", "hardware": "H100", "model": null, "shape": "seq_len=1024,num_heads=16", "batch_size": 1, "metric": "memory bandwidth", "unit": "GB/s", "higher_is_better": true, "baseline": 15.46, "optimized": 22.33, "stated_speedup": null, "speedup": 1.4444}, {"scope": "kernel", "hardware": "H100", "model": null,... | 2.7115 | null |
flashinfer | 88e3dee17cc64a61eb6b5a45ef79742a5599ef7a | 2025-02-15T01:45:14+08:00 | 844 | https://github.com/flashinfer-ai/flashinfer/pull/844 | perf: MLA decode kernel implemented by CuTe targeted to SM80 (#844) | perf: MLA decode kernel implemented by CuTe targeted to SM80 (#844)
Hi @yzh119 , this is a follow up of #766, an interesting idea came to my
mind today, can't help to change few lines to verify this idea.
We can use asymmetric warp config to solve the register file size limit
issue, the solution is simply to use 8 war... | include/flashinfer/attention/scheduler.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/attention/scheduler.cuh
+++ include/flashinfer/attention/scheduler.cuh
@@ -42,6 +42,13 @@
uint32_t bdy, uint32_t bdz, uint32_t tile_size_qo_heads, typename AttentionVariant,
typename Params>
__global__ void BatchDecodeWithPagedKVCacheKernelMLA(Params params);
+
+template <u... | 65 | 0 | 3 | [] | [
"SM80"
] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/scheduler.cuh).
Goal: perf: MLA decode kernel implemented by CuTe targeted to SM80
Target hardware: SM80
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, V... | Hi @yzh119 , this is a follow up of #766, an interesting idea came to my mind today, can't help to change few lines to verify this idea.
We can use asymmetric warp config to solve the register file size limit issue, the solution is simply to use 8 warps for the output mma stage, and keep other parts unchanged, because... | [] | null | null |
flashinfer | 106e6fc24a80ee2aa534dfd29274bb67091dce65 | 2025-02-12T00:02:18-05:00 | 804 | https://github.com/flashinfer-ai/flashinfer/pull/804 | perf: memory efficient deepseek mla fused page-attention kernel (#804) | perf: memory efficient deepseek mla fused page-attention kernel (#804)
**Description:**
This PR implements a memory efficient fused Deepseek MLA PageAttention
kernel for decode, prefill, and chunked prefill operations.
MLA computation after matrix absorption can be described as a
(multi-query attention) MQA kern... | include/flashinfer/attention/heap.h | cpp | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/attention/heap.h
+++ include/flashinfer/attention/heap.h
@@ -27,12 +27,12 @@
* \brief Heap data structure for (index, value) pairs
* \note minimal element on top
*/
-class CTACostHeap {
+class MinHeap {
public:
// first: index, second: cost
using Element = std::pair<int, float>;
-... | 4 | 2 | 7 | [
"deepseek"
] | [
"A100",
"H100"
] | [] | Optimize this cpp kernel file from flashinfer (include/flashinfer/attention/heap.h).
Goal: perf: memory efficient deepseek mla fused page-attention kernel
Target hardware: A100, H100
Target models: deepseek
Current file:
```cpp
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Vers... | **Description:**
This PR implements a memory efficient fused Deepseek MLA PageAttention kernel for decode, prefill, and chunked prefill operations.
MLA computation after matrix absorption can be described as a (multi-query attention) MQA kernel, with same K/V cache and special head dimensions: `head_dim_qk=576, head_d... | [] | null | null |
flashinfer | 106e6fc24a80ee2aa534dfd29274bb67091dce65 | 2025-02-12T00:02:18-05:00 | 804 | https://github.com/flashinfer-ai/flashinfer/pull/804 | perf: memory efficient deepseek mla fused page-attention kernel (#804) | perf: memory efficient deepseek mla fused page-attention kernel (#804)
**Description:**
This PR implements a memory efficient fused Deepseek MLA PageAttention
kernel for decode, prefill, and chunked prefill operations.
MLA computation after matrix absorption can be described as a
(multi-query attention) MQA kern... | include/flashinfer/attention/prefill.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/attention/prefill.cuh
+++ include/flashinfer/attention/prefill.cuh
@@ -102,10 +102,10 @@
static constexpr uint32_t NUM_WARPS = NUM_WARPS_Q * NUM_WARPS_KV;
static constexpr uint32_t HEAD_DIM_QK = NUM_MMA_D_QK * 16;
static constexpr uint32_t HEAD_DIM_VO = NUM_MMA_D_VO * 16;
- static const... | 80 | 81 | 7 | [
"deepseek"
] | [
"A100",
"H100"
] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/prefill.cuh).
Goal: perf: memory efficient deepseek mla fused page-attention kernel
Target hardware: A100, H100
Target models: deepseek
Current file:
```cuda
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache Licens... | **Description:**
This PR implements a memory efficient fused Deepseek MLA PageAttention kernel for decode, prefill, and chunked prefill operations.
MLA computation after matrix absorption can be described as a (multi-query attention) MQA kernel, with same K/V cache and special head dimensions: `head_dim_qk=576, head_d... | [] | null | null |
flashinfer | 106e6fc24a80ee2aa534dfd29274bb67091dce65 | 2025-02-12T00:02:18-05:00 | 804 | https://github.com/flashinfer-ai/flashinfer/pull/804 | perf: memory efficient deepseek mla fused page-attention kernel (#804) | perf: memory efficient deepseek mla fused page-attention kernel (#804)
**Description:**
This PR implements a memory efficient fused Deepseek MLA PageAttention
kernel for decode, prefill, and chunked prefill operations.
MLA computation after matrix absorption can be described as a
(multi-query attention) MQA kern... | include/flashinfer/attention/scheduler.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/attention/scheduler.cuh
+++ include/flashinfer/attention/scheduler.cuh
@@ -17,6 +17,7 @@
#define FLASHINFER_ATTENTION_SCHEDULER_CUH_
#include <cuda_runtime_api.h>
+#include <driver_types.h>
#include <algorithm>
#include <cstddef>
@@ -702,9 +703,7 @@
return cudaSuccess;
}
-inline flo... | 195 | 10 | 7 | [
"deepseek"
] | [
"A100",
"H100"
] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/scheduler.cuh).
Goal: perf: memory efficient deepseek mla fused page-attention kernel
Target hardware: A100, H100
Target models: deepseek
Current file:
```cuda
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache Lice... | **Description:**
This PR implements a memory efficient fused Deepseek MLA PageAttention kernel for decode, prefill, and chunked prefill operations.
MLA computation after matrix absorption can be described as a (multi-query attention) MQA kernel, with same K/V cache and special head dimensions: `head_dim_qk=576, head_d... | [] | null | null |
flashinfer | 106e6fc24a80ee2aa534dfd29274bb67091dce65 | 2025-02-12T00:02:18-05:00 | 804 | https://github.com/flashinfer-ai/flashinfer/pull/804 | perf: memory efficient deepseek mla fused page-attention kernel (#804) | perf: memory efficient deepseek mla fused page-attention kernel (#804)
**Description:**
This PR implements a memory efficient fused Deepseek MLA PageAttention
kernel for decode, prefill, and chunked prefill operations.
MLA computation after matrix absorption can be described as a
(multi-query attention) MQA kern... | include/flashinfer/attention/variant_helper.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/attention/variant_helper.cuh
+++ include/flashinfer/attention/variant_helper.cuh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2024 by FlashInfer team.
+ * Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except i... | 2 | 1 | 7 | [
"deepseek"
] | [
"A100",
"H100"
] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/variant_helper.cuh).
Goal: perf: memory efficient deepseek mla fused page-attention kernel
Target hardware: A100, H100
Target models: deepseek
Current file:
```cuda
/*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache... | **Description:**
This PR implements a memory efficient fused Deepseek MLA PageAttention kernel for decode, prefill, and chunked prefill operations.
MLA computation after matrix absorption can be described as a (multi-query attention) MQA kernel, with same K/V cache and special head dimensions: `head_dim_qk=576, head_d... | [] | null | null |
flashinfer | fc037728a9abaafdc0cedb1559c8844e4b59b264 | 2025-02-04T00:20:55-05:00 | 776 | https://github.com/flashinfer-ai/flashinfer/pull/776 | perf: refactor fa2 prefill template (#776) | perf: refactor fa2 prefill template (#776)
This PR refactors the FA2-based prefill template, including the
following changes:
1. Using KernelTraits for all constexpr and data types.
2. Using SharedStorage class for a clean interface shared memory
management.
3. Unlock `CTA_TILE_Q=32`.
We also tried `CTA_TILE_Q... | include/flashinfer/attention/scheduler.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/attention/scheduler.cuh
+++ include/flashinfer/attention/scheduler.cuh
@@ -418,27 +418,6 @@
return cudaSuccess;
}
-inline uint32_t DetermineCtaTileQ(int64_t avg_packed_qo_len, uint32_t head_dim) {
- if (avg_packed_qo_len > 64 && head_dim < 256) {
- return 128;
- } else {
- auto comp... | 2 | 23 | 4 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/scheduler.cuh).
Goal: perf: refactor fa2 prefill template
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "L... | This PR refactors the FA2-based prefill template, including the following changes:
1. Using KernelTraits for all constexpr and data types.
2. Using SharedStorage class for a clean interface shared memory management.
3. Unlock `CTA_TILE_Q=32`.
We also tried `CTA_TILE_Q=8`, the half-mma optimization for GQA decoding wit... | [] | null | null |
flashinfer | fc037728a9abaafdc0cedb1559c8844e4b59b264 | 2025-02-04T00:20:55-05:00 | 776 | https://github.com/flashinfer-ai/flashinfer/pull/776 | perf: refactor fa2 prefill template (#776) | perf: refactor fa2 prefill template (#776)
This PR refactors the FA2-based prefill template, including the
following changes:
1. Using KernelTraits for all constexpr and data types.
2. Using SharedStorage class for a clean interface shared memory
management.
3. Unlock `CTA_TILE_Q=32`.
We also tried `CTA_TILE_Q... | include/flashinfer/mma.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/mma.cuh
+++ include/flashinfer/mma.cuh
@@ -480,7 +480,7 @@
* \brief Use mma instructions to compute rowsum.
*/
template <typename DType>
-__device__ __forceinline__ void rowsum_f8f8f32(float* d, DType* s) {
+__device__ __forceinline__ void m16k32_rowsum_f8f8f32(float* d, DType* s) {
stati... | 2 | 2 | 4 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/mma.cuh).
Goal: perf: refactor fa2 prefill template
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you... | This PR refactors the FA2-based prefill template, including the following changes:
1. Using KernelTraits for all constexpr and data types.
2. Using SharedStorage class for a clean interface shared memory management.
3. Unlock `CTA_TILE_Q=32`.
We also tried `CTA_TILE_Q=8`, the half-mma optimization for GQA decoding wit... | [] | null | null |
flashinfer | fc037728a9abaafdc0cedb1559c8844e4b59b264 | 2025-02-04T00:20:55-05:00 | 776 | https://github.com/flashinfer-ai/flashinfer/pull/776 | perf: refactor fa2 prefill template (#776) | perf: refactor fa2 prefill template (#776)
This PR refactors the FA2-based prefill template, including the
following changes:
1. Using KernelTraits for all constexpr and data types.
2. Using SharedStorage class for a clean interface shared memory
management.
3. Unlock `CTA_TILE_Q=32`.
We also tried `CTA_TILE_Q... | include/flashinfer/utils.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/utils.cuh
+++ include/flashinfer/utils.cuh
@@ -108,6 +108,11 @@
__VA_ARGS__ \
break; \
} \
+ case 32: { ... | 29 | 0 | 4 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/utils.cuh).
Goal: perf: refactor fa2 prefill template
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* y... | This PR refactors the FA2-based prefill template, including the following changes:
1. Using KernelTraits for all constexpr and data types.
2. Using SharedStorage class for a clean interface shared memory management.
3. Unlock `CTA_TILE_Q=32`.
We also tried `CTA_TILE_Q=8`, the half-mma optimization for GQA decoding wit... | [] | null | null |
flashinfer | 989dbfa65f28939575d4f2c15ed71bb09c030287 | 2025-01-03T23:31:22-08:00 | 714 | https://github.com/flashinfer-ai/flashinfer/pull/714 | perf: fix the iteration bound of SWA in FA2 prefill template (#714) | perf: fix the iteration bound of SWA in FA2 prefill template (#714)
We forgot to divide the packed row index by group_size when computing
the sliding window iteration bound, making it larger than its actual
value, and slows down the execution.
Thank @Ying1123 for spotting this bug. | include/flashinfer/attention/prefill.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/attention/prefill.cuh
+++ include/flashinfer/attention/prefill.cuh
@@ -1226,7 +1226,7 @@
16 * NUM_WARPS_KV * NUM_MMA_KV);
const uint32_t window_iteration =
- ceil_div(sub_if_greater_or_zero(kv_len + (bx + 1) * num_rows_per_cta,
+ ceil_div(sub_if_greater_or_zero(kv_le... | 3 | 3 | 1 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/prefill.cuh).
Goal: perf: fix the iteration bound of SWA in FA2 prefill template
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache Licen... | We forgot to divide the packed row index by group_size when computing the sliding window iteration bound, making it larger than its actual value, and slows down the execution.
Thank @Ying1123 for spotting this bug.
| [] | null | null |
flashinfer | db8f04d30989f57acef3fbde41cbd3ce373727f1 | 2024-12-22T16:39:35-08:00 | 690 | https://github.com/flashinfer-ai/flashinfer/pull/690 | hotfix: accelerate plan speed of fa3 template (#690) | hotfix: accelerate plan speed of fa3 template (#690)
The fa3 template's plan speed is very slow because we overestimate the
workspace size that needs to be transferred from CPU to GPU, this PR
fixes the issue.
cc @nandor @zhyncs | csrc/aot_extension_utils.h | cpp | Apache-2.0 | /*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/aot_extension_utils.h
+++ csrc/aot_extension_utils.h
@@ -30,17 +30,6 @@
#define DISPATCH_mask_mode(expr, const_expr, ...) \
_DISPATCH_SWITCH("mask_mode", expr, _DISPATCH_CASES_mask_mode(const_expr, __VA_ARGS__))
-#define DISPATCH_BOOL(expr, const_expr, ...) \
- [&]() -> bool { ... | 0 | 11 | 10 | [] | [
"CPU"
] | [] | Optimize this cpp kernel file from flashinfer (csrc/aot_extension_utils.h).
Goal: hotfix: accelerate plan speed of fa3 template
Target hardware: CPU
Target models: unspecified
Current file:
```cpp
/*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you... | The fa3 template's plan speed is very slow because we overestimate the workspace size that needs to be transferred from CPU to GPU, this PR fixes the issue.
cc @nandor @zhyncs
| [] | null | null |
flashinfer | db8f04d30989f57acef3fbde41cbd3ce373727f1 | 2024-12-22T16:39:35-08:00 | 690 | https://github.com/flashinfer-ai/flashinfer/pull/690 | hotfix: accelerate plan speed of fa3 template (#690) | hotfix: accelerate plan speed of fa3 template (#690)
The fa3 template's plan speed is very slow because we overestimate the
workspace size that needs to be transferred from CPU to GPU, this PR
fixes the issue.
cc @nandor @zhyncs | csrc/batch_prefill_sm90.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/batch_prefill_sm90.cu
+++ csrc/batch_prefill_sm90.cu
@@ -29,14 +29,14 @@
namespace flashinfer {
template <uint32_t HEAD_DIM, MaskMode MASK_MODE, bool LEFT_SLINDING_WINDOW,
- typename AttentionVariant, typename DTypeQ, typename DTypeKV, typename DTypeO,
- typename IdType>
+ bool S... | 39 | 31 | 10 | [] | [
"CPU"
] | [] | Optimize this cuda kernel file from flashinfer (csrc/batch_prefill_sm90.cu).
Goal: hotfix: accelerate plan speed of fa3 template
Target hardware: CPU
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* y... | The fa3 template's plan speed is very slow because we overestimate the workspace size that needs to be transferred from CPU to GPU, this PR fixes the issue.
cc @nandor @zhyncs
| [] | null | null |
flashinfer | db8f04d30989f57acef3fbde41cbd3ce373727f1 | 2024-12-22T16:39:35-08:00 | 690 | https://github.com/flashinfer-ai/flashinfer/pull/690 | hotfix: accelerate plan speed of fa3 template (#690) | hotfix: accelerate plan speed of fa3 template (#690)
The fa3 template's plan speed is very slow because we overestimate the
workspace size that needs to be transferred from CPU to GPU, this PR
fixes the issue.
cc @nandor @zhyncs | csrc/flashinfer_ops_sm90.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/flashinfer_ops_sm90.cu
+++ csrc/flashinfer_ops_sm90.cu
@@ -33,9 +33,9 @@
std::vector<int64_t> BatchPrefillWithKVCacheSM90Plan(
unsigned int head_dim, bool causal, at::Tensor float_workspace_buffer,
at::Tensor int_workspace_buffer, at::Tensor page_locked_int_workspace_buffer,
- at::Tensor qo_indpt... | 3 | 3 | 10 | [] | [
"CPU"
] | [] | Optimize this cuda kernel file from flashinfer (csrc/flashinfer_ops_sm90.cu).
Goal: hotfix: accelerate plan speed of fa3 template
Target hardware: CPU
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* ... | The fa3 template's plan speed is very slow because we overestimate the workspace size that needs to be transferred from CPU to GPU, this PR fixes the issue.
cc @nandor @zhyncs
| [] | null | null |
flashinfer | db8f04d30989f57acef3fbde41cbd3ce373727f1 | 2024-12-22T16:39:35-08:00 | 690 | https://github.com/flashinfer-ai/flashinfer/pull/690 | hotfix: accelerate plan speed of fa3 template (#690) | hotfix: accelerate plan speed of fa3 template (#690)
The fa3 template's plan speed is very slow because we overestimate the
workspace size that needs to be transferred from CPU to GPU, this PR
fixes the issue.
cc @nandor @zhyncs | csrc/pytorch_extension_utils.h | cpp | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/pytorch_extension_utils.h
+++ csrc/pytorch_extension_utils.h
@@ -189,6 +189,17 @@
return __VA_ARGS__(); \
}
+#define DISPATCH_BOOL(expr, const_expr, ...) \
+ [&]() -> bool { \
+ if (expr) { \
+ constexpr bool cons... | 11 | 0 | 10 | [] | [
"CPU"
] | [] | Optimize this cpp kernel file from flashinfer (csrc/pytorch_extension_utils.h).
Goal: hotfix: accelerate plan speed of fa3 template
Target hardware: CPU
Target models: unspecified
Current file:
```cpp
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
*... | The fa3 template's plan speed is very slow because we overestimate the workspace size that needs to be transferred from CPU to GPU, this PR fixes the issue.
cc @nandor @zhyncs
| [] | null | null |
flashinfer | db8f04d30989f57acef3fbde41cbd3ce373727f1 | 2024-12-22T16:39:35-08:00 | 690 | https://github.com/flashinfer-ai/flashinfer/pull/690 | hotfix: accelerate plan speed of fa3 template (#690) | hotfix: accelerate plan speed of fa3 template (#690)
The fa3 template's plan speed is very slow because we overestimate the
workspace size that needs to be transferred from CPU to GPU, this PR
fixes the issue.
cc @nandor @zhyncs | include/flashinfer/attention/hopper/prefill_sm90.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2024, Jay Shah, Ganesh Bikshandi, Ying Zhang, Vijay Thakkar, Pradeep Ramani, Tri
* Dao. Licensed under the BSD 3-Clause.
*
* Modified by the FlashInfer team.
*/
#ifndef FLASHINFER_ATTENTION_HOPPER_PREFILL_SM90_CUH_
#define FLASHINFER_ATTENTION_HOPPER_PREFILL_SM90_CUH_
#include <cuda_device_runt... | /*
* Copyright (c) 2024, Jay Shah, Ganesh Bikshandi, Ying Zhang, Vijay Thakkar, Pradeep Ramani, Tri
* Dao. Licensed under the BSD 3-Clause.
*
* Modified by the FlashInfer team.
*/
#ifndef FLASHINFER_ATTENTION_HOPPER_PREFILL_SM90_CUH_
#define FLASHINFER_ATTENTION_HOPPER_PREFILL_SM90_CUH_
#include <cuda_device_runt... | --- include/flashinfer/attention/hopper/prefill_sm90.cuh
+++ include/flashinfer/attention/hopper/prefill_sm90.cuh
@@ -291,7 +291,8 @@
return cudaSuccess;
}
-template <typename KernelTraits, bool LEFT_SLINDING_WINDOW, bool CAUSAL, typename IdType>
+template <typename KernelTraits, bool LEFT_SLINDING_WINDOW, bool C... | 25 | 17 | 10 | [] | [
"CPU",
"HOPPER"
] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/hopper/prefill_sm90.cuh).
Goal: hotfix: accelerate plan speed of fa3 template
Target hardware: CPU, HOPPER
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2024, Jay Shah, Ganesh Bikshandi, Ying Zhang, Vijay Thakkar, Prad... | The fa3 template's plan speed is very slow because we overestimate the workspace size that needs to be transferred from CPU to GPU, this PR fixes the issue.
cc @nandor @zhyncs
| [] | null | null |
flashinfer | db8f04d30989f57acef3fbde41cbd3ce373727f1 | 2024-12-22T16:39:35-08:00 | 690 | https://github.com/flashinfer-ai/flashinfer/pull/690 | hotfix: accelerate plan speed of fa3 template (#690) | hotfix: accelerate plan speed of fa3 template (#690)
The fa3 template's plan speed is very slow because we overestimate the
workspace size that needs to be transferred from CPU to GPU, this PR
fixes the issue.
cc @nandor @zhyncs | include/flashinfer/attention/hopper/tile_scheduler.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2024, Jay Shah, Ganesh Bikshandi, Ying Zhang, Vijay Thakkar, Pradeep Ramani, Tri
* Dao. Licensed under the BSD 3-Clause.
*
* Modified by the FlashInfer team.
*/
#ifndef FLASHINFER_ATTENTION_HOPPER_TILE_SCHEDULER_CUH_
#define FLASHINFER_ATTENTION_HOPPER_TILE_SCHEDULER_CUH_
#include "cutlass/arch... | /*
* Copyright (c) 2024, Jay Shah, Ganesh Bikshandi, Ying Zhang, Vijay Thakkar, Pradeep Ramani, Tri
* Dao. Licensed under the BSD 3-Clause.
*
* Modified by the FlashInfer team.
*/
#ifndef FLASHINFER_ATTENTION_HOPPER_TILE_SCHEDULER_CUH_
#define FLASHINFER_ATTENTION_HOPPER_TILE_SCHEDULER_CUH_
#include "cutlass/arch... | --- include/flashinfer/attention/hopper/tile_scheduler.cuh
+++ include/flashinfer/attention/hopper/tile_scheduler.cuh
@@ -78,13 +78,14 @@
};
template <typename IdType>
-struct BatchPrefillTileScheduler {
+struct BatchPrefillPersistentTileScheduler {
public:
// Host side kernel arguments
struct Arguments {
... | 116 | 6 | 10 | [] | [
"CPU",
"HOPPER"
] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/hopper/tile_scheduler.cuh).
Goal: hotfix: accelerate plan speed of fa3 template
Target hardware: CPU, HOPPER
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2024, Jay Shah, Ganesh Bikshandi, Ying Zhang, Vijay Thakkar, Pr... | The fa3 template's plan speed is very slow because we overestimate the workspace size that needs to be transferred from CPU to GPU, this PR fixes the issue.
cc @nandor @zhyncs
| [] | null | null |
flashinfer | db8f04d30989f57acef3fbde41cbd3ce373727f1 | 2024-12-22T16:39:35-08:00 | 690 | https://github.com/flashinfer-ai/flashinfer/pull/690 | hotfix: accelerate plan speed of fa3 template (#690) | hotfix: accelerate plan speed of fa3 template (#690)
The fa3 template's plan speed is very slow because we overestimate the
workspace size that needs to be transferred from CPU to GPU, this PR
fixes the issue.
cc @nandor @zhyncs | include/flashinfer/attention/scheduler.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/attention/scheduler.cuh
+++ include/flashinfer/attention/scheduler.cuh
@@ -742,6 +742,7 @@
int64_t kv_len_offset;
int64_t head_indices_offset;
int64_t work_indptr_offset;
+ bool same_schedule_for_all_heads;
PrefillPlanSM90Info()
: qo_tile_indices_offset(0),
@@ -750,17 +751,2... | 29 | 16 | 10 | [] | [
"CPU"
] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/scheduler.cuh).
Goal: hotfix: accelerate plan speed of fa3 template
Target hardware: CPU
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the ... | The fa3 template's plan speed is very slow because we overestimate the workspace size that needs to be transferred from CPU to GPU, this PR fixes the issue.
cc @nandor @zhyncs
| [] | null | null |
flashinfer | 553ace5eb91fc07681fa9edf8b6c09827a72617a | 2024-12-04T02:27:50-08:00 | 644 | https://github.com/flashinfer-ai/flashinfer/pull/644 | perf: reduce total_num_tiles_q by one (#644) | perf: reduce total_num_tiles_q by one (#644)
The bound can be reduced by one to slightly decrease workspace memory
usage. | include/flashinfer/attention/scheduler.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/attention/scheduler.cuh
+++ include/flashinfer/attention/scheduler.cuh
@@ -483,7 +483,7 @@
// number of rows and the batch size. The sum of qo lengths rounded
// up to cta_tile_q will not exceed this number derived from the total
// number of rows.
- total_num_tiles_q = ceil_di... | 1 | 1 | 1 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/scheduler.cuh).
Goal: perf: reduce total_num_tiles_q by one
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the ... | The bound can be reduced by one to slightly decrease workspace memory usage.
| [] | null | null |
flashinfer | ff05155581f5e085b573f803aed398434859e22f | 2024-11-14T07:46:16Z | 609 | https://github.com/flashinfer-ai/flashinfer/pull/609 | perf: improve parallelism in RoPE with pos_ids (#609) | perf: improve parallelism in RoPE with pos_ids (#609)
The previous kernel was not parallelised sufficiently well for low batch
sizes. Similarly to the regular rotary kernel, now all qo/kv heads are
split across separate blocks.
In decode mode, the pos_ids kernel is now faster. | include/flashinfer/pos_enc.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/pos_enc.cuh
+++ include/flashinfer/pos_enc.cuh
@@ -229,65 +229,61 @@
float smooth_b, float rope_rcp_scale, float rope_rcp_theta) {
// NOTE: q and q_rope may be the same ptr, so do k and k_rope
uint32_t bx = blockIdx.x, tx = threadIdx.x, ty = threadIdx.y;
- const uint32_t bdy = blockDi... | 49 | 53 | 1 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/pos_enc.cuh).
Goal: perf: improve parallelism in RoPE with pos_ids
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "Li... | The previous kernel was not parallelised sufficiently well for low batch sizes. Similarly to the regular rotary kernel, now all qo/kv heads are split across separate blocks.
In decode mode, the pos_ids kernel is now faster.
| [] | null | null |
flashinfer | 595cf602e73688d2f96f8cf1aad7cb2fce689d41 | 2024-11-10T16:24:18-08:00 | 602 | https://github.com/flashinfer-ai/flashinfer/pull/602 | perf: fix prefill kernel performance degradation (step 1) (#602) | perf: fix prefill kernel performance degradation (step 1) (#602)
The prefill attention kernel performance has degraded significantly in
recent releases (since v0.1.2), especially on A100 when `causal=True`,
this is mainly because we add new attention variants (which increases
register usage thus incurs register spi... | include/flashinfer/attention/prefill.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/attention/prefill.cuh
+++ include/flashinfer/attention/prefill.cuh
@@ -623,18 +623,25 @@
const uint_fastdiv group_size,
DTypeQKAccum (*s_frag)[NUM_FRAGS_KV][8]) {
const uint32_t lane_idx = threa... | 26 | 12 | 1 | [] | [
"A100"
] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/prefill.cuh).
Goal: perf: fix prefill kernel performance degradation (step 1)
Target hardware: A100
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Versio... | The prefill attention kernel performance has degraded significantly in recent releases (since v0.1.2), especially on A100 when `causal=True`, this is mainly because we add new attention variants (which increases register usage thus incurs register spilling) and move some parameters from compile-time to runtime.
This P... | [] | null | null |
flashinfer | 2043ca2181d1e9119a1fb8b86a739c245be5b536 | 2024-11-09T10:32:14+08:00 | 592 | https://github.com/flashinfer-ai/flashinfer/pull/592 | perf: reduce the read and write of shared memory in the FusedAddRMSNormKernel (#592) | perf: reduce the read and write of shared memory in the FusedAddRMSNormKernel (#592)
Use `vec_t<float, VEC_SIZE> x_vec` to reduce the number of read and
write operations to shared memory. | include/flashinfer/norm.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/norm.cuh
+++ include/flashinfer/norm.cuh
@@ -133,6 +133,8 @@
input_vec.fill(0.f);
vec_t<T, VEC_SIZE> residual_vec;
residual_vec.fill(0.f);
+ vec_t<float, VEC_SIZE> x_vec;
+ x_vec.fill(0.f);
if ((i * num_threads + thread_id) * VEC_SIZE < d) {
input_vec.load(input +... | 11 | 6 | 1 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/norm.cuh).
Goal: perf: reduce the read and write of shared memory in the FusedAddRMSNormKernel
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache L... | Use `vec_t<float, VEC_SIZE> x_vec` to reduce the number of read and write operations to shared memory.
| [] | null | null |
flashinfer | e15f7c984bc4152c0b65cfec916ace37c98668cd | 2024-11-06T14:02:19-08:00 | 588 | https://github.com/flashinfer-ai/flashinfer/pull/588 | perf: fix the performance issue of `append_paged_kv_cache` (#588) | perf: fix the performance issue of `append_paged_kv_cache` (#588)
The performance of `append_paged_kv_cache` is terrible for small batch
size, which is a known issue that we haven't fixed for a long time, this
PR fixes it. This PR also adds support for non-contiguous append
keys/values (which could be sliced from f... | include/flashinfer/page.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/page.cuh
+++ include/flashinfer/page.cuh
@@ -249,38 +249,34 @@
* \param paged_kv The paged key-value cache
* \param key The key to be appended
* \param value The value to be appended
- * \param append_indptr The indptr array of the appended ragged tensor
+ * \param batch_indices The batch i... | 42 | 30 | 1 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/page.cuh).
Goal: perf: fix the performance issue of `append_paged_kv_cache`
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0... | The performance of `append_paged_kv_cache` is terrible for small batch size, which is a known issue that we haven't fixed for a long time, this PR fixes it. This PR also adds support for non-contiguous append keys/values (which could be sliced from fused qkv matrix).
We first call a triton kernel to convert `append_in... | [] | null | null |
flashinfer | be6bf5bb26f1f1b3edf094d903544600c574ee09 | 2024-08-21T12:08:36-07:00 | 459 | https://github.com/flashinfer-ai/flashinfer/pull/459 | perf: use persistent kernel for merging attention states (#459) | perf: use persistent kernel for merging attention states (#459)
As observed by @MasterJH5574 , there are cases where our
`VariableLengthMergeStatesKernel` launches a lot of CTAs (>=10k) while
most of the CTAs only work on small number of merges, this PR fixes the
issue by using a persistent kernel.
There is stil... | include/flashinfer/attention/cascade.cuh | cuda | Apache-2.0 | /*!
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or... | /*!
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or... | --- include/flashinfer/attention/cascade.cuh
+++ include/flashinfer/attention/cascade.cuh
@@ -301,85 +301,94 @@
*/
template <uint32_t vec_size, uint32_t bdx, uint32_t bdy, uint32_t num_smem_stages, typename DTypeIn,
typename DTypeOut, typename IdType>
-__global__ void VariableLengthMergeStatesKernel(DType... | 96 | 77 | 1 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/cascade.cuh).
Goal: perf: use persistent kernel for merging attention states
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*!
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License,... | As observed by @MasterJH5574 , there are cases where our `VariableLengthMergeStatesKernel` launches a lot of CTAs (>=10k) while most of the CTAs only work on small number of merges, this PR fixes the issue by using a persistent kernel.
There is still load imbalance issue, and I plan to resolve it inside scheduler. I'l... | [] | null | null |
flashinfer | 7c397cbd81d4fa5da8aef9f105576dbe67f6c22b | 2024-08-20T23:03:22-07:00 | 458 | https://github.com/flashinfer-ai/flashinfer/pull/458 | perf: slight optimization on fragment layout swizzle (#458) | perf: slight optimization on fragment layout swizzle (#458)
fuse two byte perm into one. | include/flashinfer/frag_layout_swizzle.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/frag_layout_swizzle.cuh
+++ include/flashinfer/frag_layout_swizzle.cuh
@@ -29,9 +29,8 @@
}
__device__ __forceinline__ uint32_t frag_layout_swizzle_16b_to_8b_trans(uint32_t x) {
- x = __byte_perm(x, x, 0x3120);
uint32_t tmp = __shfl_xor_sync(0xffffffff, x, 0x4);
- x = __byte_perm(x, tmp, ... | 1 | 2 | 2 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/frag_layout_swizzle.cuh).
Goal: perf: slight optimization on fragment layout swizzle
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Ve... | fuse two byte perm into one.
| [] | null | null |
flashinfer | 7c397cbd81d4fa5da8aef9f105576dbe67f6c22b | 2024-08-20T23:03:22-07:00 | 458 | https://github.com/flashinfer-ai/flashinfer/pull/458 | perf: slight optimization on fragment layout swizzle (#458) | perf: slight optimization on fragment layout swizzle (#458)
fuse two byte perm into one. | include/flashinfer/vec_dtypes.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/vec_dtypes.cuh
+++ include/flashinfer/vec_dtypes.cuh
@@ -126,7 +126,6 @@
constexpr int MASK2 = MASK1 >> (FP8_EXPONENT + FP8_MANTISSA);
constexpr int MASK3 = MASK2 & 0x7fffffff;
constexpr int MASK = MASK3 | (MASK3 >> 16);
- // Final MASK value: 0x7F007F00
q = __byte_perm(q, ... | 0 | 1 | 2 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/vec_dtypes.cuh).
Goal: perf: slight optimization on fragment layout swizzle
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0... | fuse two byte perm into one.
| [] | null | null |
flashinfer | 0d618712faff20a84bbd513d02ac01e16be19306 | 2024-08-17T23:26:02-07:00 | 453 | https://github.com/flashinfer-ai/flashinfer/pull/453 | perf: slight optimization on f16->f8 fragment layout swizzling (#453) | perf: slight optimization on f16->f8 fragment layout swizzling (#453)
swap after dequantize. | include/flashinfer/attention/prefill.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/attention/prefill.cuh
+++ include/flashinfer/attention/prefill.cuh
@@ -802,8 +802,8 @@
}
b_frag_f8[0] = frag_layout_swizzle_16b_to_8b_trans(b_frag_f8[0]);
b_frag_f8[1] = frag_layout_swizzle_16b_to_8b_trans(b_frag_f8[1]);
- bfly_exch(b_frag_f8[0], b_frag_f8[1]);
... | 1 | 1 | 3 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/prefill.cuh).
Goal: perf: slight optimization on f16->f8 fragment layout swizzling
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache Lic... | swap after dequantize.
| [] | null | null |
flashinfer | 0d618712faff20a84bbd513d02ac01e16be19306 | 2024-08-17T23:26:02-07:00 | 453 | https://github.com/flashinfer-ai/flashinfer/pull/453 | perf: slight optimization on f16->f8 fragment layout swizzling (#453) | perf: slight optimization on f16->f8 fragment layout swizzling (#453)
swap after dequantize. | include/flashinfer/frag_layout_swizzle.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/frag_layout_swizzle.cuh
+++ include/flashinfer/frag_layout_swizzle.cuh
@@ -39,11 +39,4 @@
return x;
}
-__device__ __forceinline__ void bfly_exch(uint32_t& a, uint32_t& b) {
- uint32_t tmp = __byte_perm(a, b, 0x5410);
- uint32_t tmp2 = __byte_perm(a, b, 0x7632);
- a = tmp;
- b = tmp2;
-}... | 0 | 7 | 3 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/frag_layout_swizzle.cuh).
Goal: perf: slight optimization on f16->f8 fragment layout swizzling
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache L... | swap after dequantize.
| [] | null | null |
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