>, \\\n ScaleMode>(inputs, hopper_inputs, sm_count_, \\\n workspace_size); \\\n } \\\n break\n\n#define DISPATCH_MIXED_DTYPE_MOE_SMALL_K_TILE(ENUM_NAME, TILE_M, TILE_N, TILE_K) \\\n case tkc::CutlassTileConfigSM90::ENUM_NAME: \\\n if constexpr (Sm90Wfp4Afp8Mode == Sm90Wfp4Afp8ScaleMode::kHummingPreMmaE8M0) { \\\n sm90_dispatch_moe_mixed_dtype_gemm_small_k_only< \\\n T, WeightType, GemmOutputType, EpilogueTag, \\\n Shape<Int<TILE_M>, Int<TILE_N>, Int<TILE_K>>, ScaleMode>(inputs, hopper_inputs, \\\n sm_count_, workspace_size); \\\n } else { \\\n TLLM_THROW(\"Single-warpgroup small-K tile is only valid for Humming pre-MMA scale.\"); \\\n } \\\n break\n\n switch (inputs.gemm_config.tile_config_sm90) {\n DISPATCH_MIXED_DTYPE_MOE_TILE(CtaShape64x16x128B, 64, 16, 128);\n DISPATCH_MIXED_DTYPE_MOE_TILE(CtaShape64x16x256B, 64, 16, 256);\n DISPATCH_MIXED_DTYPE_MOE_TILE(CtaShape64x16x512B, 64, 16, 512);\n DISPATCH_MIXED_DTYPE_MOE_TILE(CtaShape64x32x128B, 64, 32, 128);\n DISPATCH_MIXED_DTYPE_MOE_TILE(CtaShape64x32x256B, 64, 32, 256);\n DISPATCH_MIXED_DTYPE_MOE_TILE(CtaShape64x32x512B, 64, 32, 512);\n DISPATCH_MIXED_DTYPE_MOE_TILE(CtaShape64x64x128B, 64, 64, 128);\n DISPATCH_MIXED_DTYPE_MOE_TILE(CtaShape64x64x256B, 64, 64, 256);\n DISPATCH_MIXED_DTYPE_MOE_TILE(CtaShape64x64x512B, 64, 64, 512);\n DISPATCH_MIXED_DTYPE_MOE_TILE(CtaShape64x128x128B, 64, 128, 128);\n DISPATCH_MIXED_DTYPE_MOE_TILE(CtaShape64x128x256B, 64, 128, 256);\n DISPATCH_MIXED_DTYPE_MOE_TILE(CtaShape64x128x512B, 64, 128, 512);\n DISPATCH_MIXED_DTYPE_MOE_SMALL_K_TILE(CtaShape128x8x128B, 128, 8, 128);\n DISPATCH_MIXED_DTYPE_MOE_TILE_WITH_SMALL_K(CtaShape128x16x128B, 128, 16, 128);\n DISPATCH_MIXED_DTYPE_MOE_TILE(CtaShape128x16x256B, 128, 16, 256);\n DISPATCH_MIXED_DTYPE_MOE_TILE(CtaShape128x16x512B, 128, 16, 512);\n DISPATCH_MIXED_DTYPE_MOE_TILE_WITH_SMALL_K(CtaShape128x32x128B, 128, 32, 128);\n DISPATCH_MIXED_DTYPE_MOE_TILE(CtaShape128x32x256B, 128, 32, 256);\n DISPATCH_MIXED_DTYPE_MOE_TILE(CtaShape128x32x512B, 128, 32, 512);\n DISPATCH_MIXED_DTYPE_MOE_SMALL_K_TILE(CtaShape128x40x128B, 128, 40, 128);\n DISPATCH_MIXED_DTYPE_MOE_TILE(CtaShape128x64x128B, 128, 64, 128);\n DISPATCH_MIXED_DTYPE_MOE_TILE(CtaShape128x64x256B, 128, 64, 256);\n DISPATCH_MIXED_DTYPE_MOE_TILE(CtaShape128x64x512B, 128, 64, 512);\n DISPATCH_MIXED_DTYPE_MOE_TILE(CtaShape128x128x128B, 128, 128, 128);\n DISPATCH_MIXED_DTYPE_MOE_TILE(CtaShape128x128x256B, 128, 128, 256);\n DISPATCH_MIXED_DTYPE_MOE_TILE(CtaShape128x128x512B, 128, 128, 512);\n DISPATCH_MIXED_DTYPE_MOE_TILE(CtaShape128x256x128B, 128, 256, 128);\n DISPATCH_MIXED_DTYPE_MOE_TILE(CtaShape128x256x256B, 128, 256, 256);\n DISPATCH_MIXED_DTYPE_MOE_TILE(CtaShape256x128x128B, 256, 128, 128);\n DISPATCH_MIXED_DTYPE_MOE_TILE(CtaShape256x128x256B, 256, 128, 256);\n DISPATCH_MIXED_DTYPE_MOE_TILE(CtaShape256x256x128B, 256, 256, 128);\n case tkc::CutlassTileConfigSM90::Undefined:\n TLLM_THROW(\n \"[Mixed dtype MoE GEMM][sm90_dispatch_moe_mixed_dtype_gemm_to_cutlass] gemm config \"\n \"undefined.\");\n break;\n case tkc::CutlassTileConfigSM90::ChooseWithHeuristic:\n TLLM_THROW(\n \"[Mixed dtype MoE GEMM][sm90_dispatch_moe_mixed_dtype_gemm_to_cutlass] gemm config \"\n \"should have already \"\n \"been set by \"\n \"heuristic.\");\n break;\n default:\n TLLM_THROW(\n \"[Mixed dtype MoE GEMM][sm90_dispatch_moe_mixed_dtype_gemm_to_cutlass] Config is invalid \"\n \"for mixed type \"\n \"GEMM.\");\n break;\n }\n\n#undef DISPATCH_MIXED_DTYPE_MOE_TILE\n#undef DISPATCH_MIXED_DTYPE_MOE_TILE_WITH_SMALL_K\n#undef DISPATCH_MIXED_DTYPE_MOE_SMALL_K_TILE\n}\n\ntemplate <typename T, typename WeightType, typename OutputType,\n Sm90Wfp4Afp8ScaleMode Sm90Wfp4Afp8Mode = Sm90Wfp4Afp8ScaleMode::kDisabled>\nsize_t calcMaxWorkspaceSizeTmaWarpSpecializedMixedInput(int num_experts, int sm_count_) {\n size_t count = 0;\n#if defined(ENABLE_FP4)\n constexpr int Ktile = (std::is_same_v<WeightType, Fp4Type>) ? 256 : 512;\n#else\n constexpr int Ktile = 512;\n#endif\n using _Ktile = Int<Ktile>;\n static constexpr auto ScaleMode =\n Sm90Wfp4Afp8Mode == Sm90Wfp4Afp8ScaleMode::kHummingPreMmaE8M0\n ? cutlass::gemm::collective::MixedInputScaleMode::kPreMmaE8M0\n : cutlass::gemm::collective::MixedInputScaleMode::kPostMma;\n\n#ifdef COMPILE_HOPPER_TMA_GROUPED_GEMMS\n GroupedGemmInput<T, WeightType, OutputType, OutputType> inputs{};\n inputs.num_experts = num_experts;\n sm90_generic_mixed_moe_gemm_kernelLauncher<\n T, WeightType, OutputType, tensorrt_llm::cutlass_extensions::EpilogueOpDefault,\n Shape<_128, _64, _Ktile>, Shape<_1, _1, _1>,\n cutlass::gemm::KernelTmaWarpSpecializedCooperative,\n cutlass::epilogue::TmaWarpSpecializedCooperative,\n cutlass::WeightOnlyQuantOp::FINEGRAINED_SCALE_ONLY, ScaleMode>(\n inputs, TmaWarpSpecializedGroupedGemmInput{}, sm_count_, &count);\n#endif\n return count;\n}\n\n} // namespace tensorrt_llm::kernels::cutlass_kernels_oss\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## 📌 Description\n\nThis PR improves the SM90 CUTLASS mixed-input MoE backend in two areas.\n\nFirst, it expands the MXFP4×FP8 Humming single-warpgroup tactic set with the\n`(128, 64, 128)` shape for both PrefillAll and RollingRefill. The N64 shape is\nregistered alongside the existing N8/N16/N32/N40 shapes, routed through the\nsmall-K dispatch, and configured for two CTAs per SM, matching its shared-memory\noccupancy limit. PrefillAll is eligible for `K <= 384`, while RollingRefill\ncovers `K > 384`.\n\nSecond, it extends the existing work-map builder, which already constructs the\nA and B TMA descriptors, to also construct output-D descriptors before the\npersistent grouped GEMM is launched:\n\n- Allocate one prebuilt output descriptor per local expert.\n- Select the corresponding D descriptor for the initial expert and whenever\n the scheduler moves to another expert, instead of rebuilding its address,\n dimensions, and strides in the GEMM kernel.\n- Remove mutable output descriptors from the epilogue shared-memory and\n per-SM descriptor workspace when the prebuilt path is enabled.\n\nAt SM90 module-generation time, the prebuilt-D variant is selected internally\nonly if JIT is enabled and the current CUDA device reports 78 SMs, covering the\nintended H20 and H20-3e configurations. Devices reporting other SM counts,\nincluding H100 and H200, generate the generic mutable-D variant. The 78-SM\nvariant uses a distinct JIT module name to avoid a cache collision with the\ngeneric SM90 module. Single-warpgroup small-K kernels are excluded from\nprebuilt-D and retain their existing direct-store epilogue.\n\nOn 78-SM devices, this compile-time switch applies to regular,\nnon-single-warpgroup SM90 mixed-input grouped GEMMs instantiated by this\nlauncher. The H20 evaluation below combines protocol-matched NCU sweeps of\nthe MXFP4×FP8 Humming, INT4×FP8, and MXFP4×BF16 path families. The N64\ntactic expansion is Humming-specific, while the prebuilt-D optimization is\nshared by all three regular mixed-input paths on the selected H20 route.\n\n## Performance\n\n### H20 DSV4-Pro TPEP benchmark\n\nThe formal H20 NCU evaluation covers all three regular SM90 mixed-input path\nfamilies reached by this launcher:\n\n- MXFP4 weights with FP8 activations (Humming).\n- INT4 weights with internally quantized FP8 activations (W4A8), using BF16\n output in the performance sweep.\n- MXFP4 weights with BF16 activations (W4A16).\n\nEach path covers all 36 DeepSeek-V4-Pro TPEP cases (`TP1/EP8`, `TP2/EP4`,\n`TP4/EP2`, and `TP8/EP1`) at batch sizes 8 through 2048, for 108 logical cases\nin total.\n\n- Metric: NCU `gpu__time_duration.sum`; CUDA Event and host timings are\n excluded.\n- NCU 2026.1.1, application replay, cache-control `none`, clock-control\n `none`. This preserves the cache state established by the builder for the\n immediately following GEMM.\n- Each revision/case contains 50 fused calls; the first two are discarded,\n leaving 48 paired samples.\n- `FC1 total = FC1 builder + FC1 GEMM`.\n- `FC2 total = FC2 builder + FC2 GEMM`.\n- `FC1+FC2 total` includes both builders and both GEMMs.\n- Per-case speedup is baseline median divided by candidate median; aggregate\n values are geometric means.\n\n<img width=\"4096\" height=\"2920\" alt=\"dsv4_sm90_all_mixed_paths_pr_de701865_vs_main_39b484f1_ncu_speedup_percent_h20\" src=\"https://github.com/user-attachments/assets/5e1ccd1c-e40a-456c-99ea-18a33829155c\" />\n\n\n| H20 path | Cases | FC1 total | FC2 total | FC1+FC2 total | Equivalent latency reduction |\n|---|---:|---:|---:|---:|---:|\n| MXFP4×FP8 Humming | 36 | 1.0064x | 1.0923x | **1.0470x** | **4.493%** |\n| INT4×FP8 | 36 | 1.0211x | 1.0857x | **1.0515x** | **4.895%** |\n| MXFP4×BF16 | 36 | 1.0014x | 1.0277x | **1.0123x** | **1.212%** |\n| All three paths | 108 | 1.0096x | 1.0681x | **1.0368x** | **3.547%** |\n\n| H20 FC1+FC2 total | TP1/EP8 | TP2/EP4 | TP4/EP2 | TP8/EP1 |\n|---|---:|---:|---:|---:|\n| MXFP4×FP8 Humming | 1.0050x | 1.0045x | 1.0366x | 1.1484x |\n| INT4×FP8 | 1.0218x | 1.0205x | 1.0292x | 1.1390x |\n| MXFP4×BF16 | 1.0008x | 1.0018x | 1.0012x | 1.0460x |\n\nAll 36 Humming cases improved. The best Humming case was TP8/EP1 BS512:\n`1416.928 us -> 1214.624 us` (`1.1666x`, 14.278% lower latency). The aggregate\nbuilder slowdown from constructing D descriptors is included in every result.\n\nAll 36 INT4×FP8 cases improved. Its best FC1+FC2 case was TP8/EP1\nBS128: `1413.136 us -> 1214.352 us` (`1.1637x`, 14.067% lower latency).\n\nFor MXFP4×BF16, 29 of 36 cases improved. Its best FC1+FC2 case was TP8/EP1\nBS128: `1704.464 us -> 1612.848 us` (`1.0568x`, 5.375% lower latency).\nThe largest of the seven remaining regressions was TP2/EP4 BS2048:\n`11563.584 us -> 11577.600 us` (`0.9988x`, 0.121% higher latency).\n\n#### Observed TP-dominant FC2 trend\n\nIn the DSV4 matrix, FC2's reduction K is the local intermediate size: 3072,\n1536, 768, and 384 for TP1 through TP8. With the fixed `64x16x128` tactic,\nthat corresponds to 24, 12, 6, and 3 mainloop K tiles per output tile. A likely\nexplanation for the observed trend is that a smaller K does not reduce the\namount of output data, but makes each output tile reach the epilogue after\nfewer mainloop iterations. This leaves less mainloop work over which to\namortize the fixed-cost mutable-D descriptor update, its warp synchronization,\nand descriptor fence release at an expert (`L_idx`) transition. TP-dominant\nconfigurations also have more local experts, which may increase expert\ntransitions and partial-tile fragmentation for the same routed-token count.\n\nThe FC2 builder-plus-GEMM geometric means show the same trend across all three\npaths:\n\n| H20 FC2 total | TP1/EP8<br>K=3072 | TP2/EP4<br>K=1536 | TP4/EP2<br>K=768 | TP8/EP1<br>K=384 |\n|---|---:|---:|---:|---:|\n| MXFP4×FP8 Humming | 1.0019x | 1.0007x | 1.0874x | **1.3055x** |\n| INT4×FP8 | 1.0225x | 1.0201x | 1.0435x | **1.2763x** |\n| MXFP4×BF16 | 1.0005x | 1.0028x | 1.0012x | **1.1105x** |\n\nThe cross-path trend is consistent with prebuilding D being most valuable when\nshort FC2 mainloops have less work over which to amortize online descriptor\nmaintenance. Because TP changes both reduction K and the local expert count,\nthis sweep does not isolate their individual contributions. The prebuilt path\nstill performs the required descriptor acquire and TMA stores; it removes the\nmutable descriptor rewrite, that update's warp synchronization, and fence\nrelease from the GEMM critical path.\n\nPrebuilding D adds work to the builder: the builder-only aggregate was\n`0.9835x` for MXFP4×FP8 Humming, `0.9805x` for INT4×FP8, and `0.9793x` for\nMXFP4×BF16. That cost is included in every FC1, FC2, and combined result\nabove.\n\nThe Humming sweep selected the same default Pingpong `64x16x128` structural\ntactic in baseline and candidate; N64 was selected in `0/72` case/stage pairs.\nThe other two paths were forced to that same structural tactic (absolute FC1\nand FC2 profile IDs `0` and `116`), and the strict parser verified matching\nkernel families and structural tactics for all 144 baseline-versus-candidate\nFC1/FC2 stage comparisons. The N64 tactics are Humming-only and do not change\nthe tactic space of the other paths. The performance gains above are therefore\nnot attributed to the new N64 tactic.\n\n## 🔍 Related Issues\n\nN/A\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request,\nplease make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used\n my preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed\n any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see the\n> [pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Existing tests cover the affected paths; this PR does not add a test-only\n file.\n- [x] Relevant SM90 mixed-input correctness tests are passing.\n\nValidation included:\n\n- Exact SM90a JIT builds and fresh-process loads for both routes: H20 used\n `fused_moe_90_h20_prebuilt_d`, while H200 used the generic `fused_moe_90`\n module without the prebuilt-D define.\n- A single no-build H20 run explicitly recorded candidate source matching\n `de701865`, the `fused_moe_90_h20_prebuilt_d` module, the prebuilt-D compile\n define, and the loaded `.so` SHA256; all 26 selected tests passed. These comprise seven\n Humming `use_autotune=False` cases, 13 W4A16\n correctness/coverage/activation cases, and six W4A8 cases covering BF16 and\n FP16 correctness, autotuning, and the exact packed-workspace size.\n- The Humming no-build A/B sweep over all 36 DeepSeek-V4-Pro TPEP cases\n produced bit-identical BF16 outputs from bit-identical deterministic inputs.\n- The Humming and other-path performance sweeps produced 216 complete NCU\n reports. Every report passed the exact 200-launch ordered-slot check; all\n 144 baseline-versus-candidate FC1/FC2 stage comparisons in the other-path\n sweep used the same structural tactic.\n- During N64 bring-up on H20, forcing N64 PrefillAll for both FC1 and FC2 at K\n values 128, 256, and 384 produced bit-identical complete MoE outputs to N40\n PrefillAll (`max_abs = 0`).\n- `pre-commit run -a` passed.\n\n## Reviewer Notes\n\n- This PR contains three commits so the N64 tactic expansion, prebuilt-D\n optimization, and H20-only device gate remain independently reviewable.\n- The H20 selection is internal to the SM90 JIT generator and does not add a\n public API argument. H100 and H200 continue to use the generic module.\n- Each path's 36-case DSV4 matrix holds the structural tactic constant between\n baseline and candidate. The reported gains therefore are not attributed to\n the new N64 tactic.\n- The prebuilt path stores one read-only D descriptor per expert and shares it\n between consumer warpgroups.\n- The H20 performance validation covers Humming plus both other regular SM90\n mixed-input path families reached by this launcher.\n- Non-prebuilt kernels retain their mutable descriptor initialization and\n update path. Single-warpgroup kernels retain their direct-store epilogue.\n- The builder overhead and main-kernel gains are both included in the reported\n fused-call totals.\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n* **New Features**\n * Added support for additional SM90 mixed-precision MoE and grouped GEMM configurations using 128×64 tiles.\n * Expanded compatibility with larger tile widths in single-warpgroup execution paths.\n * Added optimized output descriptor handling for supported H20 and H20-3e systems.\n\n* **Performance Improvements**\n * Improved scheduling and execution efficiency for supported H20 MoE workloads.\n * Added optimized kernel configurations for FP8 activation and FP4 weight operations.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"e2e\", \"hardware\": \"H20\", \"model\": \"DeepSeek-V4-Pro\", \"shape\": null, \"batch_size\": 512, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 1416.928, \"optimized\": 1214.624, \"stated_speedup\": 1.1666, \"speedup\": 1.1666}, {\"scope\": \"e2e\", \"hardware\": \"H20\", \"model\": \"DeepSeek-V4-Pro\", \"shape\": null, \"batch_size\": 128, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 1413.136, \"optimized\": 1214.352, \"stated_speedup\": 1.1637, \"speedup\": 1.1637}, {\"scope\": \"e2e\", \"hardware\": \"H20\", \"model\": \"DeepSeek-V4-Pro\", \"shape\": null, \"batch_size\": 128, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 1704.464, \"optimized\": 1612.848, \"stated_speedup\": 1.0568, \"speedup\": 1.0568}, {\"scope\": \"e2e\", \"hardware\": \"H20\", \"model\": \"DeepSeek-V4-Pro\", \"shape\": \"TP=8,EP=1\", \"batch_size\": 2048, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 11563.584, \"optimized\": 11577.6, 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\"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.0368, \"speedup\": 1.0368}, {\"scope\": \"e2e\", \"hardware\": \"H20\", \"model\": \"DeepSeek-V4-Pro\", \"shape\": \"TP=8,EP=1\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.1484, \"speedup\": 1.1484}, {\"scope\": \"e2e\", \"hardware\": \"H20\", \"model\": \"DeepSeek-V4-Pro\", \"shape\": \"TP=8,EP=1\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.139, \"speedup\": 1.139}, {\"scope\": \"e2e\", \"hardware\": \"H20\", \"model\": \"DeepSeek-V4-Pro\", \"shape\": \"TP=8,EP=1\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.046, \"speedup\": 1.046}, {\"scope\": \"e2e\", \"hardware\": \"H20\", \"model\": \"DeepSeek-V4-Pro\", \"shape\": \"TP=8,EP=1,K=384\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.3055, \"speedup\": 1.3055}, {\"scope\": \"e2e\", \"hardware\": \"H20\", \"model\": \"DeepSeek-V4-Pro\", \"shape\": \"TP=8,EP=1,K=384\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.2763, \"speedup\": 1.2763}, {\"scope\": \"e2e\", \"hardware\": \"H20\", \"model\": \"DeepSeek-V4-Pro\", \"shape\": \"TP=8,EP=1,K=384\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.1105, \"speedup\": 1.1105}, {\"scope\": \"e2e\", \"hardware\": \"H20\", \"model\": \"DeepSeek-V4-Pro\", \"shape\": null, \"batch_size\": null, \"metric\": \"builder slowdown\", \"unit\": null, \"higher_is_better\": false, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 0.9835, \"speedup\": 0.9835}, {\"scope\": \"e2e\", \"hardware\": \"H20\", \"model\": \"DeepSeek-V4-Pro\", \"shape\": null, \"batch_size\": null, \"metric\": \"builder slowdown\", \"unit\": null, \"higher_is_better\": false, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 0.9805, \"speedup\": 0.9805}, {\"scope\": \"e2e\", \"hardware\": \"H20\", \"model\": \"DeepSeek-V4-Pro\", \"shape\": null, \"batch_size\": null, \"metric\": \"builder slowdown\", \"unit\": null, \"higher_is_better\": false, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 0.9793, \"speedup\": 0.9793}]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"number","value":1.0515,"string":"1.0515"}}},{"rowIdx":1061,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"75038cdf67a5ba577ef4b329badc301f185c5a95"},"date":{"kind":"string","value":"2026-09-10T02:48:58+09:00"},"pr_number":{"kind":"number","value":4997,"string":"4,997"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/4997"},"title":{"kind":"string","value":"perf(attention): Refresh DSL_FMHA cubins (#4997)"},"message":{"kind":"string","value":"perf(attention): Refresh DSL_FMHA cubins (#4997)\n\n<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\n<!-- What does this PR do? Briefly describe the changes and why they’re\nneeded. -->\n\n+ Refresh DSL_FMHA cubins\n+ Minimal change to source code to keep backward compatibility (unlike\ncubin builder, FlashInfer needs to ensure JIT source compatibility with\nmultiple `nvidia-cutlass-dsl` versions).\n\n### Performance on B300\n\nBase shape: B=2, H=16, D=128 data:\n- Internal compiler scheduling decision might have caused regression in\nsome shapes, but overall there is a consistent latency improvement over\nthe Blackwell Ultra horizon:\n\n| S | Causal | QK/V | `main` median (ms) | Refresh median (ms) | Refresh\nlatency delta | Refresh speedup |\n\n|---:|:------:|:------|-------------------:|--------------------:|----------------------:|----------------:|\n| 2048 | True | BF16/BF16 | 0.064800 | 0.060704 | -6.32% | 1.0675x |\n| 2048 | True | BF16/FP8 | 0.059040 | 0.055952 | -5.23% | 1.0552x |\n| 2048 | True | FP8/FP8 | 0.053393 | 0.049728 | -6.86% | 1.0737x |\n| 2048 | False | BF16/BF16 | 0.070321 | 0.065408 | -6.99% | 1.0751x |\n| 2048 | False | BF16/FP8 | 0.061056 | 0.058912 | -3.51% | 1.0364x |\n| 2048 | False | FP8/FP8 | 0.049504 | 0.049729 | +0.45% | 0.9955x |\n| 16384 | True | BF16/BF16 | 1.386919 | 1.383943 | -0.21% | 1.0022x |\n| 16384 | True | BF16/FP8 | 1.114918 | 1.170806 | +5.01% | 0.9523x |\n| 16384 | True | FP8/FP8 | 1.050949 | 1.038149 | -1.22% | 1.0123x |\n| 16384 | False | BF16/BF16 | 2.621342 | 2.425229 | -7.48% | 1.0809x |\n| 16384 | False | BF16/FP8 | 2.146891 | 2.001659 | -6.76% | 1.0726x |\n| 16384 | False | FP8/FP8 | 1.764121 | 1.729594 | -1.96% | 1.0200x |\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\nN/A\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the\npre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n## 🔬 Experimental Track\n\n<!-- Only for PRs submitted under the experimental policy\n(CONTRIBUTING.md → \"Experimental APIs and Backends\").\n Leave this section untouched for normal PRs. -->\n\n- [ ] This PR is **experimental**: it adds or changes code under\n`flashinfer/experimental/` and/or an `@flashinfer_experimental_api`.\nTracking issue: #\n- [ ] The tracking issue names an owner, the reason for the experimental\npath, and a graduation plan with a target release.\n- [ ] Core changes are limited to a thin entry point (signature, shared\nvalidation, feature-gate check, backend selection, handoff).\n- [ ] Tests live in `tests/experimental/` and were validated on the\nintended hardware; a runnable example is included.\n- [ ] Nothing is registered in `flashinfer/aot.py`, and no experimental\nbackend is reachable from `backend=\"auto\"` without\n`FLASHINFER_ALLOW_EXPERIMENTAL_AUTO_BACKENDS=1`. (Calling an\n`@flashinfer_experimental_api` or naming a backend explicitly is itself\nthe opt-in and needs no environment variable.)\n- [ ] **Test scope declared below.** The experimental CI lane runs\nexactly these targets, so keep them as narrow as the change allows.\n\n<!-- Required for experimental PRs. Replace the commented lines below\nwith your targets.\nDo not delete the fence or change its `experimental-tests` tag — the\nexperimental-track\nwatcher reads it verbatim to decide which targets to ask CI for. -->\n\n```experimental-tests\n# One target per line: a directory or a file. (A pytest ::selector is not\n# supported -- the sharding runner cannot consume one.) Must be under\n# tests/experimental/ and must exist. Delete these comment lines and add yours, e.g.\n#\n# tests/experimental/test_my_backend.py\n# tests/experimental/my_backend/\n#\n# Declaring the whole tree (tests/experimental/) is allowed but means every\n# experimental PR pays for every other feature's tests, in every matrix cell.\n```\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc.\n-->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n- **Bug Fixes**\n- Updated the CuTe DSL fused multi-head attention backend for\ncompatibility with the latest kernel interface.\n- Improved softmax-scaling behavior for skip-softmax and low-precision\nattention modes.\n- Added configurable rescaling thresholds for standard and block-scaled\nattention paths.\n- Refreshed backend artifacts and checksums across supported GPU and CPU\narchitectures.\n- **Documentation**\n- Clarified CuTe DSL attention backend coverage, including ALiBi and\nmodular prefill behavior.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->"},"path":{"kind":"string","value":"flashinfer/attention/cute_dsl/fmha.py"},"language":{"kind":"string","value":"cute_dsl"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"# Copyright (c) 2026 by FlashInfer team.\n#\n# Licensed under the Apache License, Version 2.0 (the \"License\");\n# you may not use this file except in compliance with the License.\n# You may obtain a copy of the License at\n#\n# http://www.apache.org/licenses/LICENSE-2.0\n#\n# Unless required by applicable law or agreed to in writing, software\n# distributed under the License is distributed on an \"AS IS\" BASIS,\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n# See the License for the specific language governing permissions and\n# limitations under the License.\n\"\"\"\nCuTe DSL FMHA Kernel Loader (Cubin Distribution)\n=================================================\n\nLoads pre-compiled FMHA kernel .so artifacts via ExternalBinaryModule.\nThe .so files are compiled offline from the proprietary DSL kernel source\nand distributed through the cubin_publishing pipeline.\n\nRuntime flow:\n 1. get_artifact() downloads .so from artifactory (or local cache)\n 2. ExternalBinaryModule loads .so and extracts callable kernel\n 3. cute_dsl_fmha_ragged_prefill() wraps the kernel with a PyTorch-friendly API\n\"\"\"\n\nimport functools\nimport logging\nimport math\nimport os\nfrom typing import Optional\n\nimport cutlass\nimport cutlass.cute as cute\nimport torch\nfrom cuda.bindings import driver as cuda_driver\nfrom cutlass.cute.runtime import from_dlpack\nfrom cutlass.cute.typing import Float32, Int32\n\nlogger = logging.getLogger(\"flashinfer.attention.cute_dsl.fmha\")\n\n\n# =============================================================================\n# Artifact configuration\n# =============================================================================\n\nfrom flashinfer.artifacts import ArtifactPath\n\nDSL_FMHA_ARTIFACT_PATH = ArtifactPath.DSL_FMHA\n\nfrom flashinfer.artifacts import _get_host_cpu_arch as _get_cpu_arch\n\n\ndef _get_gpu_arch(device: torch.device) -> str:\n \"\"\"Get the GPU architecture string for *device* (e.g. 'sm_100a').\n\n Uses the same normalization as CompilationContext to match the arch\n subdirectory names used by the cubin publishing pipeline.\n \"\"\"\n major, minor = torch.cuda.get_device_capability(device)\n from flashinfer.compilation_context import CompilationContext\n\n _, minor_str = CompilationContext._normalize_cuda_arch(major, minor)\n return f\"sm_{major}{minor_str}\"\n\n\n# Cache: arch -> {variant_name: sha256} parsed from downloaded checksums.txt\n_checksums_cache: dict[str, dict[str, str]] = {}\n\n\ndef _get_checksums(gpu_arch: str) -> dict[str, str]:\n \"\"\"Download and parse checksums.txt for the given arch.\n\n The checksums.txt is generated by compile_dsl_fmha.py and published\n alongside the .so files at <artifact_path>/<arch>/checksums.txt.\n Format per line: \"sha256 filename.so\"\n \"\"\"\n if gpu_arch in _checksums_cache:\n return _checksums_cache[gpu_arch]\n\n from flashinfer.jit.cubin_loader import download_file, safe_urljoin\n from flashinfer.jit.cubin_loader import FLASHINFER_CUBINS_REPOSITORY\n from flashinfer.jit.env import FLASHINFER_CUBIN_DIR\n\n cpu_arch = _get_cpu_arch()\n checksums_rel = os.path.join(\n DSL_FMHA_ARTIFACT_PATH, cpu_arch, gpu_arch, \"checksums.txt\"\n )\n local_path = FLASHINFER_CUBIN_DIR / checksums_rel\n\n if not local_path.exists():\n os.makedirs(local_path.parent, exist_ok=True)\n uri = safe_urljoin(FLASHINFER_CUBINS_REPOSITORY, checksums_rel)\n logger.info(f\"Fetching checksums for {gpu_arch} from {uri}\")\n download_file(uri, str(local_path))\n\n checksums = {}\n with open(local_path) as f:\n for line in f:\n line = line.strip()\n if not line:\n continue\n sha256, filename = line.split(None, 1)\n variant_name = filename.rsplit(\".\", 1)[0] # strip .so extension\n checksums[variant_name] = sha256\n\n _checksums_cache[gpu_arch] = checksums\n return checksums\n\n\ndef _dtype_to_str(dtype: torch.dtype) -> str:\n \"\"\"Convert torch dtype to short string matching compile_cute_dsl_fmha.py naming.\"\"\"\n return {\n torch.float16: \"fp16\",\n torch.bfloat16: \"bf16\",\n torch.float8_e4m3fn: \"e4m3\",\n }[dtype]\n\n\ndef _get_variant_name(\n qk_dtype: torch.dtype,\n pv_dtype: torch.dtype,\n out_dtype: torch.dtype,\n head_dim: int,\n is_causal: bool,\n is_persistent: bool = True,\n varlen: bool = False,\n with_lse: bool = False,\n enable_tvm_ffi: bool = False,\n enable_skip_softmax: bool = False,\n enable_sink: bool = False,\n use_pdl: bool = False,\n) -> str:\n \"\"\"Generate the variant name matching compile_cute_dsl_fmha.py naming convention.\"\"\"\n qk_str = _dtype_to_str(qk_dtype)\n pv_str = _dtype_to_str(pv_dtype)\n out_str = _dtype_to_str(out_dtype)\n # Include all three dtypes for partially quantized kernels. Preserve the\n # compact legacy names when QK and PV use the same dtype.\n dtype_str = (\n f\"{qk_str}_{pv_str}_{out_str}\"\n if qk_dtype != pv_dtype\n else f\"{qk_str}_{out_str}\"\n if qk_dtype != out_dtype\n else qk_str\n )\n causal_str = \"causal\" if is_causal else \"nocausal\"\n persist_str = \"persistent\" if is_persistent else \"nonpersistent\"\n varlen_str = \"_varlen\" if varlen else \"\"\n lse_str = \"_lse\" if with_lse else \"\"\n skip_str = \"_skipsm\" if enable_skip_softmax else \"\"\n sink_str = \"_sink\" if enable_sink else \"\"\n pdl_str = \"_pdl\" if use_pdl else \"\"\n ffi_str = \"_tvmffi\" if enable_tvm_ffi else \"\"\n return f\"cute_dsl_fmha_{dtype_str}_h{head_dim}_{causal_str}_{persist_str}{varlen_str}{lse_str}{skip_str}{sink_str}{pdl_str}{ffi_str}\"\n\n\n# =============================================================================\n# Loading: ExternalBinaryModule path\n# =============================================================================\n\n\ndef _load_from_artifact(variant_name: str, gpu_arch: str, enable_tvm_ffi: bool = False):\n \"\"\"Download .so from artifactory and load via ExternalBinaryModule.\n\n This is the production path used when cubins are published.\n\n Parameters\n ----------\n variant_name : str\n The kernel variant name (matches function_prefix used during export).\n gpu_arch : str\n GPU architecture string (e.g. 'sm_100a').\n enable_tvm_ffi : bool\n If False (default), load with CuTe native ABI.\n If True, load with TVM-FFI ABI (TODO: compile-side support pending).\n \"\"\"\n from flashinfer.jit.cubin_loader import get_artifact\n from flashinfer.jit.env import FLASHINFER_CUBIN_DIR\n\n so_filename = f\"{variant_name}.so\"\n cpu_arch = _get_cpu_arch()\n artifact_path = os.path.join(\n DSL_FMHA_ARTIFACT_PATH, cpu_arch, gpu_arch, so_filename\n )\n\n checksums = _get_checksums(gpu_arch)\n sha256 = checksums.get(variant_name, \"\")\n if not sha256:\n raise RuntimeError(\n f\"No checksum found for DSL FMHA variant '{variant_name}' on {gpu_arch}. \"\n f\"Available variants: {list(checksums.keys())}\"\n )\n\n # get_artifact downloads to FLASHINFER_CUBIN_DIR / artifact_path and verifies sha256\n data = get_artifact(artifact_path, sha256)\n if not data:\n raise RuntimeError(f\"Failed to download DSL FMHA artifact: {artifact_path}\")\n\n local_path = FLASHINFER_CUBIN_DIR / artifact_path\n module = cute.runtime.load_module(str(local_path), enable_tvm_ffi=enable_tvm_ffi)\n return getattr(module, variant_name)\n\n\ndef _load_from_local(variant_name: str, local_dir: str, enable_tvm_ffi: bool = False):\n \"\"\"Load .so or .o from a local directory (for development/testing).\n\n Set FLASHINFER_DSL_FMHA_LOCAL_DIR to use this path.\n\n Parameters\n ----------\n variant_name : str\n The kernel variant name (matches function_prefix used during export).\n local_dir : str\n Directory containing the compiled .so/.o files.\n enable_tvm_ffi : bool\n If False (default), load with CuTe native ABI.\n If True, load with TVM-FFI ABI (TODO: compile-side support pending).\n \"\"\"\n # Try .so first, then .o\n so_path = os.path.join(local_dir, f\"{variant_name}.so\")\n o_path = os.path.join(local_dir, f\"{variant_name}.o\")\n if os.path.exists(so_path):\n load_path = so_path\n elif os.path.exists(o_path):\n load_path = o_path\n else:\n raise FileNotFoundError(\n f\"DSL FMHA .so/.o not found at {local_dir}/{variant_name}.[so|o]. \"\n f\"Run compile_cute_dsl_fmha.py to generate it.\"\n )\n\n module = cute.runtime.load_module(load_path, enable_tvm_ffi=enable_tvm_ffi)\n return getattr(module, variant_name)\n\n\n@functools.cache\ndef get_cute_dsl_fmha_kernel(\n gpu_arch: str,\n qk_dtype: torch.dtype,\n pv_dtype: torch.dtype,\n out_dtype: torch.dtype,\n head_dim: int,\n is_causal: bool,\n is_persistent: bool = True,\n enable_tvm_ffi: bool = False,\n varlen: bool = False,\n with_lse: bool = False,\n enable_skip_softmax: bool = False,\n enable_sink: bool = False,\n use_pdl: bool = False,\n):\n \"\"\"Get a compiled DSL FMHA kernel function.\n\n Checks local directory first (FLASHINFER_DSL_FMHA_LOCAL_DIR env var),\n then falls back to artifact download.\n\n Parameters\n ----------\n gpu_arch : str\n GPU architecture string (e.g. 'sm_100a'), used both for selecting the\n correct artifact and as part of the cache key.\n qk_dtype : torch.dtype\n Query/key data type (torch.float16, torch.bfloat16, or\n torch.float8_e4m3fn).\n pv_dtype : torch.dtype\n Value data type (torch.float16, torch.bfloat16, or\n torch.float8_e4m3fn).\n out_dtype : torch.dtype\n Output data type. Same as qk_dtype for non-mixed precision.\n head_dim : int\n Head dimension (e.g., 64, 128, 192). Note: 192 only supports FP8.\n is_causal : bool\n Whether to use causal masking.\n is_persistent : bool\n Whether to use persistent kernel mode.\n enable_tvm_ffi : bool\n If False (default), load with CuTe native ABI — kernel accepts\n cute Pointer/Tensor args (same calling convention as JIT mode).\n If True, load with TVM-FFI ABI — Pointer args accept data_ptr(),\n Tensor args accept torch.Tensor directly, stream uses env stream.\n enable_skip_softmax : bool\n If True, load kernel compiled with skip-softmax support.\n\n Returns\n -------\n callable\n The compiled kernel function.\n \"\"\"\n variant_name = _get_variant_name(\n qk_dtype,\n pv_dtype,\n out_dtype,\n head_dim,\n is_causal,\n is_persistent,\n varlen=varlen,\n with_lse=with_lse,\n enable_tvm_ffi=enable_tvm_ffi,\n enable_skip_softmax=enable_skip_softmax,\n enable_sink=enable_sink,\n use_pdl=use_pdl,\n )\n\n # Check for local .so directory (development mode)\n local_dir = os.environ.get(\"FLASHINFER_DSL_FMHA_LOCAL_DIR\")\n if local_dir:\n logger.info(\n f\"Loading DSL FMHA kernel from local dir: {local_dir} (tvm_ffi={enable_tvm_ffi})\"\n )\n return _load_from_local(variant_name, local_dir, enable_tvm_ffi=enable_tvm_ffi)\n\n # Production path: download from artifactory\n logger.info(\n f\"Loading DSL FMHA kernel variant: {variant_name} (tvm_ffi={enable_tvm_ffi})\"\n )\n return _load_from_artifact(variant_name, gpu_arch, enable_tvm_ffi=enable_tvm_ffi)\n\n\n# =============================================================================\n# PyTorch API wrapper\n# =============================================================================\n\n\ndef cute_dsl_fmha_ragged_prefill(\n q: torch.Tensor,\n k: torch.Tensor,\n v: torch.Tensor,\n o: torch.Tensor,\n qo_indptr: torch.Tensor,\n kv_indptr: torch.Tensor,\n is_causal: bool = False,\n sm_scale: Optional[float] = None,\n window_left: int = -1,\n window_right: int = -1,\n lse: Optional[torch.Tensor] = None,\n attention_sinks: Optional[torch.Tensor] = None,\n scale_q: float = 1.0,\n scale_k: float = 1.0,\n scale_v: float = 1.0,\n scale_o: float = 1.0,\n enable_tvm_ffi: bool = True,\n max_qo_len: Optional[int] = None,\n max_kv_len: Optional[int] = None,\n kernel_fn=None,\n skip_softmax_threshold_scale_factor: Optional[float] = None,\n enable_pdl: bool = False,\n) -> None:\n \"\"\"Run DSL FMHA prefill kernel on ragged (variable-length) tensors.\n\n Note: The DSL FMHA kernel only supports per-tensor scalar scales, not\n per-head scale tensors.\n\n Parameters\n ----------\n q : torch.Tensor\n Query tensor, shape (total_q_tokens, H_q, D).\n k : torch.Tensor\n Key tensor, shape (total_kv_tokens, H_k, D).\n v : torch.Tensor\n Value tensor, shape (total_kv_tokens, H_k, D_v).\n o : torch.Tensor\n Output tensor, shape (total_q_tokens, H_q, D_v). Modified in-place.\n Must be 32-byte aligned (kernel uses 256-bit store instructions).\n qo_indptr : torch.Tensor\n Cumulative sequence lengths for Q/O, shape (batch_size + 1,).\n Same as cum_seqlen_q in DSL FMHA kernel.\n kv_indptr : torch.Tensor\n Cumulative sequence lengths for K/V, shape (batch_size + 1,).\n Same as cum_seqlen_k in DSL FMHA kernel.\n is_causal : bool\n Whether to apply causal masking.\n sm_scale : float, optional\n Softmax scale factor. Defaults to 1/sqrt(D).\n window_left : int\n Left sliding window size. -1 means no window.\n window_right : int\n Right sliding window size. -1 means no window. 0 for causal.\n lse : torch.Tensor, optional\n Log-sum-exp output tensor. None to skip.\n attention_sinks : torch.Tensor, optional\n Attention sink tensor, shape (H_q,) Float32. None to disable.\n scale_q : float\n Per-tensor scale for query (FP8 calibration). Default 1.0.\n scale_k : float\n Per-tensor scale for key (FP8 calibration). Default 1.0.\n scale_v : float\n Per-tensor scale for value (FP8 calibration). Default 1.0.\n scale_o : float\n Per-tensor scale for output (FP8 calibration). Default 1.0.\n enable_tvm_ffi : bool\n If True, use TVM-FFI ABI (pass data_ptr() for Pointer args, torch.Tensor\n for Tensor args, no explicit stream). Default False (CuTe native ABI).\n max_qo_len : int, optional\n Maximum query sequence length. Computed from qo_indptr if not provided.\n Pass this from plan() to avoid D2H copy during CUDA graph capture.\n max_kv_len : int, optional\n Maximum KV sequence length. Computed from kv_indptr if not provided.\n skip_softmax_threshold_scale_factor : float, optional\n Threshold scale factor for skip-softmax sparsity (https://arxiv.org/abs/2512.12087).\n The actual threshold = scale_factor / max_kv_len, then converted to log2 domain.\n None or 0 disables skip-softmax.\n \"\"\"\n total_q, H_q, D = q.shape\n total_kv, H_k, _ = k.shape\n D_v = v.shape[-1]\n\n batch_size = len(qo_indptr) - 1\n\n use_skip_softmax = (\n skip_softmax_threshold_scale_factor is not None\n and skip_softmax_threshold_scale_factor > 0\n )\n\n if kernel_fn is None:\n gpu_arch = _get_gpu_arch(q.device)\n # Q and K feed the same GEMM operand dtype: neither the prebuilt\n # artifacts nor the JIT compile (single qk_dtype) support q != k.\n if q.dtype != k.dtype:\n raise ValueError(\n f\"cute-dsl FMHA requires q.dtype == k.dtype, got {q.dtype} and {k.dtype}\"\n )\n try:\n if window_left != -1 or window_right != -1:\n # The exported artifact matrix has no window axis: every\n # prebuilt variant is traced with window_size_left=None (and\n # window_size_right present only for causal), so a windowed\n # call into one fails the FFI signature check. The causal\n # artifact lookup would falsely succeed here — force JIT.\n raise RuntimeError(\"windowed DSL FMHA variants are not exported\")\n kernel_fn = get_cute_dsl_fmha_kernel(\n gpu_arch,\n q.dtype,\n v.dtype,\n o.dtype,\n D,\n is_causal,\n is_persistent=False, # varlen always uses non-persistent\n varlen=True,\n enable_tvm_ffi=enable_tvm_ffi,\n with_lse=lse is not None,\n enable_skip_softmax=use_skip_softmax,\n enable_sink=attention_sinks is not None,\n use_pdl=enable_pdl,\n )\n except (RuntimeError, FileNotFoundError) as e:\n # Cubin variant not available / repo unreachable.\n # JIT-compile the trtllm kernel instead.\n logger.info(f\"DSL FMHA cubin unavailable ({e}); JIT-compiling the kernel.\")\n from flashinfer.cute_dsl.attention.fmha.compile import (\n compile_cute_dsl_fmha_kernel,\n )\n\n kernel_fn = compile_cute_dsl_fmha_kernel(\n q.dtype,\n v.dtype,\n o.dtype,\n H_q,\n H_k,\n D,\n D_v,\n is_causal,\n lse is not None,\n attention_sinks is not None,\n use_skip_softmax,\n enable_pdl,\n q.device,\n has_window_left=window_left != -1,\n has_window_right=is_causal or window_right != -1,\n )\n # JIT kernels are compiled with --enable-tvm-ffi; the CuTe-native branch\n # would not accept them.\n enable_tvm_ffi = True\n\n # Compute scale factors\n if sm_scale is None:\n sm_scale = 1.0 / math.sqrt(D)\n log2_e = math.log2(math.exp(1.0))\n scale_softmax = scale_q * scale_k * sm_scale\n scale_softmax_log2 = scale_softmax * log2_e\n scale_output = scale_v / scale_o\n\n # Max seq lengths for problem_size (prefer pre-computed values for CUDA graph compat)\n if max_qo_len is None:\n max_s_q = int((qo_indptr.cpu()[1:] - qo_indptr.cpu()[:-1]).max().item())\n else:\n max_s_q = max_qo_len\n if max_kv_len is None:\n max_s_k = int((kv_indptr.cpu()[1:] - kv_indptr.cpu()[:-1]).max().item())\n else:\n max_s_k = max_kv_len\n\n # problem_size: (B, max_s_q, s_lse, max_s_k, H_q, H_k, D, D_v)\n s_lse = total_q # for variable length, s_lse = total tokens\n problem_size = (batch_size, max_s_q, s_lse, max_s_k, H_q, H_k, D, D_v)\n\n # Skip-softmax threshold (convert scale_factor to log2 domain)\n skip_threshold_log2 = None\n if use_skip_softmax:\n threshold = skip_softmax_threshold_scale_factor / max_s_k\n skip_threshold_log2 = Float32(math.log2(threshold))\n\n # Window sizes\n ws_left = None if window_left == -1 else Int32(window_left)\n ws_right = None if window_right == -1 else Int32(window_right)\n if is_causal and ws_right is None:\n ws_right = Int32(0)\n\n # Reshape to 5D matching kernel docstring:\n # q/o: (b=1, total, h_k, h_r, d/dv)\n # k/v: (b=1, total, h_k, 1, d/dv)\n h_r = H_q // H_k\n q_5d = q.view(1, total_q, H_k, h_r, D)\n k_5d = k.view(1, total_kv, H_k, 1, D)\n v_5d = v.view(1, total_kv, H_k, 1, D_v)\n assert o.data_ptr() % 32 == 0, (\n \"o must be 32-byte aligned (kernel uses 256-bit store instructions)\"\n )\n o_5d = o.view(1, total_q, H_k, h_r, D_v)\n # LSE: (1, total_q, h_k, h_r) — 4D row-major.\n lse_4d = lse.view(1, total_q, H_k, h_r) if lse is not None else None\n\n if enable_tvm_ffi:\n # TVM-FFI: pass torch.Tensor directly, no explicit stream (env stream).\n kernel_fn(\n q_5d,\n k_5d,\n v_5d,\n o_5d,\n problem_size,\n qo_indptr.to(torch.int32), # cum_seqlen_q\n kv_indptr.to(torch.int32), # cum_seqlen_k\n lse_4d,\n attention_sinks,\n Float32(scale_softmax_log2),\n Float32(scale_softmax),\n Float32(scale_output),\n skip_threshold_log2,\n ws_left,\n ws_right,\n None, # skip_softmax_count\n None, # total_softmax_count\n enable_pdl,\n )\n else:\n # CuTe native ABI: convert to cute tensors and pass with explicit stream.\n is_fp8_qk = q.dtype == torch.float8_e4m3fn\n is_fp8_pv = v.dtype == torch.float8_e4m3fn\n is_fp8_out = o.dtype == torch.float8_e4m3fn\n if is_fp8_qk:\n q_cute = from_dlpack(\n q_5d.view(torch.int8), assumed_align=16\n ).mark_layout_dynamic(leading_dim=4)\n q_cute.element_type = cutlass.Float8E4M3FN\n k_cute = from_dlpack(\n k_5d.view(torch.int8), assumed_align=16\n ).mark_layout_dynamic(leading_dim=4)\n k_cute.element_type = cutlass.Float8E4M3FN\n else:\n q_cute = from_dlpack(q_5d, assumed_align=16).mark_layout_dynamic(\n leading_dim=4\n )\n k_cute = from_dlpack(k_5d, assumed_align=16).mark_layout_dynamic(\n leading_dim=4\n )\n if is_fp8_pv:\n v_cute = from_dlpack(\n v_5d.view(torch.int8), assumed_align=16\n ).mark_layout_dynamic(leading_dim=4)\n v_cute.element_type = cutlass.Float8E4M3FN\n else:\n v_cute = from_dlpack(v_5d, assumed_align=16).mark_layout_dynamic(\n leading_dim=4\n )\n if is_fp8_out:\n o_cute = from_dlpack(\n o_5d.view(torch.int8), assumed_align=32\n ).mark_layout_dynamic(leading_dim=4)\n o_cute.element_type = cutlass.Float8E4M3FN\n else:\n o_cute = from_dlpack(o_5d, assumed_align=32).mark_layout_dynamic(\n leading_dim=4\n )\n\n cum_seqlen_q_cute = from_dlpack(\n qo_indptr.to(torch.int32), assumed_align=16\n ).mark_layout_dynamic(leading_dim=0)\n cum_seqlen_k_cute = from_dlpack(\n kv_indptr.to(torch.int32), assumed_align=16\n ).mark_layout_dynamic(leading_dim=0)\n\n lse_cute = None\n if lse_4d is not None:\n lse_cute = from_dlpack(lse_4d, assumed_align=16).mark_layout_dynamic(\n leading_dim=3\n )\n\n sink_cute = None\n if attention_sinks is not None:\n sink_cute = from_dlpack(\n attention_sinks, assumed_align=16\n ).mark_layout_dynamic(leading_dim=0)\n\n stream = cuda_driver.CUstream(torch.cuda.current_stream().cuda_stream)\n\n kernel_fn(\n q_cute,\n k_cute,\n v_cute,\n o_cute,\n problem_size,\n cum_seqlen_q_cute,\n cum_seqlen_k_cute,\n lse_cute,\n sink_cute,\n Float32(scale_softmax_log2),\n Float32(scale_softmax),\n Float32(scale_output),\n skip_threshold_log2,\n ws_left,\n ws_right,\n None, # skip_softmax_count\n None, # total_softmax_count\n stream,\n enable_pdl,\n )\n"},"after_code":{"kind":"string","value":"# Copyright (c) 2026 by FlashInfer team.\n#\n# Licensed under the Apache License, Version 2.0 (the \"License\");\n# you may not use this file except in compliance with the License.\n# You may obtain a copy of the License at\n#\n# http://www.apache.org/licenses/LICENSE-2.0\n#\n# Unless required by applicable law or agreed to in writing, software\n# distributed under the License is distributed on an \"AS IS\" BASIS,\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n# See the License for the specific language governing permissions and\n# limitations under the License.\n\"\"\"\nCuTe DSL FMHA Kernel Loader (Cubin Distribution)\n=================================================\n\nLoads pre-compiled FMHA kernel .so artifacts via ExternalBinaryModule.\nThe .so files are compiled offline from the proprietary DSL kernel source\nand distributed through the cubin_publishing pipeline.\n\nRuntime flow:\n 1. get_artifact() downloads .so from artifactory (or local cache)\n 2. ExternalBinaryModule loads .so and extracts callable kernel\n 3. cute_dsl_fmha_ragged_prefill() wraps the kernel with a PyTorch-friendly API\n\"\"\"\n\nimport functools\nimport logging\nimport math\nimport os\nfrom typing import Optional\n\nimport cutlass\nimport cutlass.cute as cute\nimport torch\nfrom cuda.bindings import driver as cuda_driver\nfrom cutlass.cute.runtime import from_dlpack\nfrom cutlass.cute.typing import Float32, Int32\n\nlogger = logging.getLogger(\"flashinfer.attention.cute_dsl.fmha\")\n\n\n# =============================================================================\n# Artifact configuration\n# =============================================================================\n\nfrom flashinfer.artifacts import ArtifactPath\n\nDSL_FMHA_ARTIFACT_PATH = ArtifactPath.DSL_FMHA\n\nfrom flashinfer.artifacts import _get_host_cpu_arch as _get_cpu_arch\n\n\ndef _get_gpu_arch(device: torch.device) -> str:\n \"\"\"Get the GPU architecture string for *device* (e.g. 'sm_100a').\n\n Uses the same normalization as CompilationContext to match the arch\n subdirectory names used by the cubin publishing pipeline.\n \"\"\"\n major, minor = torch.cuda.get_device_capability(device)\n from flashinfer.compilation_context import CompilationContext\n\n _, minor_str = CompilationContext._normalize_cuda_arch(major, minor)\n return f\"sm_{major}{minor_str}\"\n\n\n# Cache: arch -> {variant_name: sha256} parsed from downloaded checksums.txt\n_checksums_cache: dict[str, dict[str, str]] = {}\n\n\ndef _get_checksums(gpu_arch: str) -> dict[str, str]:\n \"\"\"Download and parse checksums.txt for the given arch.\n\n The checksums.txt is generated by compile_dsl_fmha.py and published\n alongside the .so files at <artifact_path>/<arch>/checksums.txt.\n Format per line: \"sha256 filename.so\"\n \"\"\"\n if gpu_arch in _checksums_cache:\n return _checksums_cache[gpu_arch]\n\n from flashinfer.jit.cubin_loader import download_file, safe_urljoin\n from flashinfer.jit.cubin_loader import FLASHINFER_CUBINS_REPOSITORY\n from flashinfer.jit.env import FLASHINFER_CUBIN_DIR\n\n cpu_arch = _get_cpu_arch()\n checksums_rel = os.path.join(\n DSL_FMHA_ARTIFACT_PATH, cpu_arch, gpu_arch, \"checksums.txt\"\n )\n local_path = FLASHINFER_CUBIN_DIR / checksums_rel\n\n if not local_path.exists():\n os.makedirs(local_path.parent, exist_ok=True)\n uri = safe_urljoin(FLASHINFER_CUBINS_REPOSITORY, checksums_rel)\n logger.info(f\"Fetching checksums for {gpu_arch} from {uri}\")\n download_file(uri, str(local_path))\n\n checksums = {}\n with open(local_path) as f:\n for line in f:\n line = line.strip()\n if not line:\n continue\n sha256, filename = line.split(None, 1)\n variant_name = filename.rsplit(\".\", 1)[0] # strip .so extension\n checksums[variant_name] = sha256\n\n _checksums_cache[gpu_arch] = checksums\n return checksums\n\n\ndef _dtype_to_str(dtype: torch.dtype) -> str:\n \"\"\"Convert torch dtype to short string matching compile_cute_dsl_fmha.py naming.\"\"\"\n return {\n torch.float16: \"fp16\",\n torch.bfloat16: \"bf16\",\n torch.float8_e4m3fn: \"e4m3\",\n }[dtype]\n\n\ndef _get_variant_name(\n qk_dtype: torch.dtype,\n pv_dtype: torch.dtype,\n out_dtype: torch.dtype,\n head_dim: int,\n is_causal: bool,\n is_persistent: bool = True,\n varlen: bool = False,\n with_lse: bool = False,\n enable_tvm_ffi: bool = False,\n enable_skip_softmax: bool = False,\n enable_sink: bool = False,\n use_pdl: bool = False,\n) -> str:\n \"\"\"Generate the variant name matching compile_cute_dsl_fmha.py naming convention.\"\"\"\n qk_str = _dtype_to_str(qk_dtype)\n pv_str = _dtype_to_str(pv_dtype)\n out_str = _dtype_to_str(out_dtype)\n # Include all three dtypes for partially quantized kernels. Preserve the\n # compact legacy names when QK and PV use the same dtype.\n dtype_str = (\n f\"{qk_str}_{pv_str}_{out_str}\"\n if qk_dtype != pv_dtype\n else f\"{qk_str}_{out_str}\"\n if qk_dtype != out_dtype\n else qk_str\n )\n causal_str = \"causal\" if is_causal else \"nocausal\"\n persist_str = \"persistent\" if is_persistent else \"nonpersistent\"\n varlen_str = \"_varlen\" if varlen else \"\"\n lse_str = \"_lse\" if with_lse else \"\"\n skip_str = \"_skipsm\" if enable_skip_softmax else \"\"\n sink_str = \"_sink\" if enable_sink else \"\"\n pdl_str = \"_pdl\" if use_pdl else \"\"\n ffi_str = \"_tvmffi\" if enable_tvm_ffi else \"\"\n return f\"cute_dsl_fmha_{dtype_str}_h{head_dim}_{causal_str}_{persist_str}{varlen_str}{lse_str}{skip_str}{sink_str}{pdl_str}{ffi_str}\"\n\n\n# =============================================================================\n# Loading: ExternalBinaryModule path\n# =============================================================================\n\n\ndef _load_from_artifact(variant_name: str, gpu_arch: str, enable_tvm_ffi: bool = False):\n \"\"\"Download .so from artifactory and load via ExternalBinaryModule.\n\n This is the production path used when cubins are published.\n\n Parameters\n ----------\n variant_name : str\n The kernel variant name (matches function_prefix used during export).\n gpu_arch : str\n GPU architecture string (e.g. 'sm_100a').\n enable_tvm_ffi : bool\n If False (default), load with CuTe native ABI.\n If True, load with TVM-FFI ABI (TODO: compile-side support pending).\n \"\"\"\n from flashinfer.jit.cubin_loader import get_artifact\n from flashinfer.jit.env import FLASHINFER_CUBIN_DIR\n\n so_filename = f\"{variant_name}.so\"\n cpu_arch = _get_cpu_arch()\n artifact_path = os.path.join(\n DSL_FMHA_ARTIFACT_PATH, cpu_arch, gpu_arch, so_filename\n )\n\n checksums = _get_checksums(gpu_arch)\n sha256 = checksums.get(variant_name, \"\")\n if not sha256:\n raise RuntimeError(\n f\"No checksum found for DSL FMHA variant '{variant_name}' on {gpu_arch}. \"\n f\"Available variants: {list(checksums.keys())}\"\n )\n\n # get_artifact downloads to FLASHINFER_CUBIN_DIR / artifact_path and verifies sha256\n data = get_artifact(artifact_path, sha256)\n if not data:\n raise RuntimeError(f\"Failed to download DSL FMHA artifact: {artifact_path}\")\n\n local_path = FLASHINFER_CUBIN_DIR / artifact_path\n module = cute.runtime.load_module(str(local_path), enable_tvm_ffi=enable_tvm_ffi)\n return getattr(module, variant_name)\n\n\ndef _load_from_local(variant_name: str, local_dir: str, enable_tvm_ffi: bool = False):\n \"\"\"Load .so or .o from a local directory (for development/testing).\n\n Set FLASHINFER_DSL_FMHA_LOCAL_DIR to use this path.\n\n Parameters\n ----------\n variant_name : str\n The kernel variant name (matches function_prefix used during export).\n local_dir : str\n Directory containing the compiled .so/.o files.\n enable_tvm_ffi : bool\n If False (default), load with CuTe native ABI.\n If True, load with TVM-FFI ABI (TODO: compile-side support pending).\n \"\"\"\n # Try .so first, then .o\n so_path = os.path.join(local_dir, f\"{variant_name}.so\")\n o_path = os.path.join(local_dir, f\"{variant_name}.o\")\n if os.path.exists(so_path):\n load_path = so_path\n elif os.path.exists(o_path):\n load_path = o_path\n else:\n raise FileNotFoundError(\n f\"DSL FMHA .so/.o not found at {local_dir}/{variant_name}.[so|o]. \"\n f\"Run compile_cute_dsl_fmha.py to generate it.\"\n )\n\n module = cute.runtime.load_module(load_path, enable_tvm_ffi=enable_tvm_ffi)\n return getattr(module, variant_name)\n\n\n@functools.cache\ndef get_cute_dsl_fmha_kernel(\n gpu_arch: str,\n qk_dtype: torch.dtype,\n pv_dtype: torch.dtype,\n out_dtype: torch.dtype,\n head_dim: int,\n is_causal: bool,\n is_persistent: bool = True,\n enable_tvm_ffi: bool = False,\n varlen: bool = False,\n with_lse: bool = False,\n enable_skip_softmax: bool = False,\n enable_sink: bool = False,\n use_pdl: bool = False,\n):\n \"\"\"Get a compiled DSL FMHA kernel function.\n\n Checks local directory first (FLASHINFER_DSL_FMHA_LOCAL_DIR env var),\n then falls back to artifact download.\n\n Parameters\n ----------\n gpu_arch : str\n GPU architecture string (e.g. 'sm_100a'), used both for selecting the\n correct artifact and as part of the cache key.\n qk_dtype : torch.dtype\n Query/key data type (torch.float16, torch.bfloat16, or\n torch.float8_e4m3fn).\n pv_dtype : torch.dtype\n Value data type (torch.float16, torch.bfloat16, or\n torch.float8_e4m3fn).\n out_dtype : torch.dtype\n Output data type. Same as qk_dtype for non-mixed precision.\n head_dim : int\n Head dimension (e.g., 64, 128, 192). Note: 192 only supports FP8.\n is_causal : bool\n Whether to use causal masking.\n is_persistent : bool\n Whether to use persistent kernel mode.\n enable_tvm_ffi : bool\n If False (default), load with CuTe native ABI — kernel accepts\n cute Pointer/Tensor args (same calling convention as JIT mode).\n If True, load with TVM-FFI ABI — Pointer args accept data_ptr(),\n Tensor args accept torch.Tensor directly, stream uses env stream.\n enable_skip_softmax : bool\n If True, load kernel compiled with skip-softmax support.\n\n Returns\n -------\n callable\n The compiled kernel function.\n \"\"\"\n variant_name = _get_variant_name(\n qk_dtype,\n pv_dtype,\n out_dtype,\n head_dim,\n is_causal,\n is_persistent,\n varlen=varlen,\n with_lse=with_lse,\n enable_tvm_ffi=enable_tvm_ffi,\n enable_skip_softmax=enable_skip_softmax,\n enable_sink=enable_sink,\n use_pdl=use_pdl,\n )\n\n # Check for local .so directory (development mode)\n local_dir = os.environ.get(\"FLASHINFER_DSL_FMHA_LOCAL_DIR\")\n if local_dir:\n logger.info(\n f\"Loading DSL FMHA kernel from local dir: {local_dir} (tvm_ffi={enable_tvm_ffi})\"\n )\n return _load_from_local(variant_name, local_dir, enable_tvm_ffi=enable_tvm_ffi)\n\n # Production path: download from artifactory\n logger.info(\n f\"Loading DSL FMHA kernel variant: {variant_name} (tvm_ffi={enable_tvm_ffi})\"\n )\n return _load_from_artifact(variant_name, gpu_arch, enable_tvm_ffi=enable_tvm_ffi)\n\n\n# =============================================================================\n# PyTorch API wrapper\n# =============================================================================\n\n\ndef cute_dsl_fmha_ragged_prefill(\n q: torch.Tensor,\n k: torch.Tensor,\n v: torch.Tensor,\n o: torch.Tensor,\n qo_indptr: torch.Tensor,\n kv_indptr: torch.Tensor,\n is_causal: bool = False,\n sm_scale: Optional[float] = None,\n window_left: int = -1,\n window_right: int = -1,\n lse: Optional[torch.Tensor] = None,\n attention_sinks: Optional[torch.Tensor] = None,\n scale_q: float = 1.0,\n scale_k: float = 1.0,\n scale_v: float = 1.0,\n scale_o: float = 1.0,\n enable_tvm_ffi: bool = True,\n max_qo_len: Optional[int] = None,\n max_kv_len: Optional[int] = None,\n kernel_fn=None,\n skip_softmax_threshold_scale_factor: Optional[float] = None,\n enable_pdl: bool = False,\n) -> None:\n \"\"\"Run DSL FMHA prefill kernel on ragged (variable-length) tensors.\n\n Note: The DSL FMHA kernel only supports per-tensor scalar scales, not\n per-head scale tensors.\n\n Parameters\n ----------\n q : torch.Tensor\n Query tensor, shape (total_q_tokens, H_q, D).\n k : torch.Tensor\n Key tensor, shape (total_kv_tokens, H_k, D).\n v : torch.Tensor\n Value tensor, shape (total_kv_tokens, H_k, D_v).\n o : torch.Tensor\n Output tensor, shape (total_q_tokens, H_q, D_v). Modified in-place.\n Must be 32-byte aligned (kernel uses 256-bit store instructions).\n qo_indptr : torch.Tensor\n Cumulative sequence lengths for Q/O, shape (batch_size + 1,).\n Same as cum_seqlen_q in DSL FMHA kernel.\n kv_indptr : torch.Tensor\n Cumulative sequence lengths for K/V, shape (batch_size + 1,).\n Same as cum_seqlen_k in DSL FMHA kernel.\n is_causal : bool\n Whether to apply causal masking.\n sm_scale : float, optional\n Softmax scale factor. Defaults to 1/sqrt(D).\n window_left : int\n Left sliding window size. -1 means no window.\n window_right : int\n Right sliding window size. -1 means no window. 0 for causal.\n lse : torch.Tensor, optional\n Log-sum-exp output tensor. None to skip.\n attention_sinks : torch.Tensor, optional\n Attention sink tensor, shape (H_q,) Float32. None to disable.\n scale_q : float\n Per-tensor scale for query (FP8 calibration). Default 1.0.\n scale_k : float\n Per-tensor scale for key (FP8 calibration). Default 1.0.\n scale_v : float\n Per-tensor scale for value (FP8 calibration). Default 1.0.\n scale_o : float\n Per-tensor scale for output (FP8 calibration). Default 1.0.\n enable_tvm_ffi : bool\n If True, use TVM-FFI ABI (pass data_ptr() for Pointer args, torch.Tensor\n for Tensor args, no explicit stream). Default False (CuTe native ABI).\n max_qo_len : int, optional\n Maximum query sequence length. Computed from qo_indptr if not provided.\n Pass this from plan() to avoid D2H copy during CUDA graph capture.\n max_kv_len : int, optional\n Maximum KV sequence length. Computed from kv_indptr if not provided.\n skip_softmax_threshold_scale_factor : float, optional\n Threshold scale factor for skip-softmax sparsity (https://arxiv.org/abs/2512.12087).\n The actual threshold = scale_factor / max_kv_len, then converted to log2 domain.\n None or 0 disables skip-softmax.\n \"\"\"\n total_q, H_q, D = q.shape\n total_kv, H_k, _ = k.shape\n D_v = v.shape[-1]\n\n batch_size = len(qo_indptr) - 1\n\n use_skip_softmax = (\n skip_softmax_threshold_scale_factor is not None\n and skip_softmax_threshold_scale_factor > 0\n )\n\n if kernel_fn is None:\n gpu_arch = _get_gpu_arch(q.device)\n # Q and K feed the same GEMM operand dtype: neither the prebuilt\n # artifacts nor the JIT compile (single qk_dtype) support q != k.\n if q.dtype != k.dtype:\n raise ValueError(\n f\"cute-dsl FMHA requires q.dtype == k.dtype, got {q.dtype} and {k.dtype}\"\n )\n try:\n if window_left != -1 or window_right != -1:\n # The exported artifact matrix has no window axis: every\n # prebuilt variant is traced with window_size_left=None (and\n # window_size_right present only for causal), so a windowed\n # call into one fails the FFI signature check. The causal\n # artifact lookup would falsely succeed here — force JIT.\n raise RuntimeError(\"windowed DSL FMHA variants are not exported\")\n kernel_fn = get_cute_dsl_fmha_kernel(\n gpu_arch,\n q.dtype,\n v.dtype,\n o.dtype,\n D,\n is_causal,\n is_persistent=False, # varlen always uses non-persistent\n varlen=True,\n enable_tvm_ffi=enable_tvm_ffi,\n with_lse=lse is not None,\n enable_skip_softmax=use_skip_softmax,\n enable_sink=attention_sinks is not None,\n use_pdl=enable_pdl,\n )\n except (RuntimeError, FileNotFoundError) as e:\n # Cubin variant not available / repo unreachable.\n # JIT-compile the trtllm kernel instead.\n logger.info(f\"DSL FMHA cubin unavailable ({e}); JIT-compiling the kernel.\")\n from flashinfer.cute_dsl.attention.fmha.compile import (\n compile_cute_dsl_fmha_kernel,\n )\n\n kernel_fn = compile_cute_dsl_fmha_kernel(\n q.dtype,\n v.dtype,\n o.dtype,\n H_q,\n H_k,\n D,\n D_v,\n is_causal,\n lse is not None,\n attention_sinks is not None,\n use_skip_softmax,\n enable_pdl,\n q.device,\n has_window_left=window_left != -1,\n has_window_right=is_causal or window_right != -1,\n )\n # JIT kernels are compiled with --enable-tvm-ffi; the CuTe-native branch\n # would not accept them.\n enable_tvm_ffi = True\n\n # Compute scale factors\n if sm_scale is None:\n sm_scale = 1.0 / math.sqrt(D)\n log2_e = math.log2(math.exp(1.0))\n scale_softmax = scale_q * scale_k * sm_scale\n scale_softmax_log2 = scale_softmax * log2_e\n scale_output = scale_v / scale_o\n\n # Max seq lengths for problem_size (prefer pre-computed values for CUDA graph compat)\n if max_qo_len is None:\n max_s_q = int((qo_indptr.cpu()[1:] - qo_indptr.cpu()[:-1]).max().item())\n else:\n max_s_q = max_qo_len\n if max_kv_len is None:\n max_s_k = int((kv_indptr.cpu()[1:] - kv_indptr.cpu()[:-1]).max().item())\n else:\n max_s_k = max_kv_len\n\n # problem_size: (B, max_s_q, s_lse, max_s_k, H_q, H_k, D, D_v)\n s_lse = total_q # for variable length, s_lse = total tokens\n problem_size = (batch_size, max_s_q, s_lse, max_s_k, H_q, H_k, D, D_v)\n\n # Skip-softmax threshold (convert scale_factor to log2 domain)\n skip_threshold_log2 = None\n if use_skip_softmax:\n threshold = skip_softmax_threshold_scale_factor / max_s_k\n skip_threshold_log2 = Float32(math.log2(threshold))\n\n # Window sizes\n ws_left = None if window_left == -1 else Int32(window_left)\n ws_right = None if window_right == -1 else Int32(window_right)\n if is_causal and ws_right is None:\n ws_right = Int32(0)\n\n # Reshape to 5D matching kernel docstring:\n # q/o: (b=1, total, h_k, h_r, d/dv)\n # k/v: (b=1, total, h_k, 1, d/dv)\n h_r = H_q // H_k\n q_5d = q.view(1, total_q, H_k, h_r, D)\n k_5d = k.view(1, total_kv, H_k, 1, D)\n v_5d = v.view(1, total_kv, H_k, 1, D_v)\n assert o.data_ptr() % 32 == 0, (\n \"o must be 32-byte aligned (kernel uses 256-bit store instructions)\"\n )\n o_5d = o.view(1, total_q, H_k, h_r, D_v)\n # LSE: (1, total_q, h_k, h_r) — 4D row-major.\n lse_4d = lse.view(1, total_q, H_k, h_r) if lse is not None else None\n\n if enable_tvm_ffi:\n # TVM-FFI: pass torch.Tensor directly, no explicit stream (env stream).\n kernel_fn(\n q_5d,\n k_5d,\n v_5d,\n o_5d,\n problem_size,\n qo_indptr.to(torch.int32), # cum_seqlen_q\n kv_indptr.to(torch.int32), # cum_seqlen_k\n lse_4d,\n attention_sinks,\n Float32(scale_softmax_log2),\n Float32(scale_softmax),\n Float32(scale_output),\n skip_threshold_log2,\n ws_left,\n ws_right,\n None, # skip_softmax_count\n None, # total_softmax_count\n enable_pdl,\n None,\n None,\n None,\n None,\n None,\n )\n else:\n # CuTe native ABI: convert to cute tensors and pass with explicit stream.\n is_fp8_qk = q.dtype == torch.float8_e4m3fn\n is_fp8_pv = v.dtype == torch.float8_e4m3fn\n is_fp8_out = o.dtype == torch.float8_e4m3fn\n if is_fp8_qk:\n q_cute = from_dlpack(\n q_5d.view(torch.int8), assumed_align=16\n ).mark_layout_dynamic(leading_dim=4)\n q_cute.element_type = cutlass.Float8E4M3FN\n k_cute = from_dlpack(\n k_5d.view(torch.int8), assumed_align=16\n ).mark_layout_dynamic(leading_dim=4)\n k_cute.element_type = cutlass.Float8E4M3FN\n else:\n q_cute = from_dlpack(q_5d, assumed_align=16).mark_layout_dynamic(\n leading_dim=4\n )\n k_cute = from_dlpack(k_5d, assumed_align=16).mark_layout_dynamic(\n leading_dim=4\n )\n if is_fp8_pv:\n v_cute = from_dlpack(\n v_5d.view(torch.int8), assumed_align=16\n ).mark_layout_dynamic(leading_dim=4)\n v_cute.element_type = cutlass.Float8E4M3FN\n else:\n v_cute = from_dlpack(v_5d, assumed_align=16).mark_layout_dynamic(\n leading_dim=4\n )\n if is_fp8_out:\n o_cute = from_dlpack(\n o_5d.view(torch.int8), assumed_align=32\n ).mark_layout_dynamic(leading_dim=4)\n o_cute.element_type = cutlass.Float8E4M3FN\n else:\n o_cute = from_dlpack(o_5d, assumed_align=32).mark_layout_dynamic(\n leading_dim=4\n )\n\n cum_seqlen_q_cute = from_dlpack(\n qo_indptr.to(torch.int32), assumed_align=16\n ).mark_layout_dynamic(leading_dim=0)\n cum_seqlen_k_cute = from_dlpack(\n kv_indptr.to(torch.int32), assumed_align=16\n ).mark_layout_dynamic(leading_dim=0)\n\n lse_cute = None\n if lse_4d is not None:\n lse_cute = from_dlpack(lse_4d, assumed_align=16).mark_layout_dynamic(\n leading_dim=3\n )\n\n sink_cute = None\n if attention_sinks is not None:\n sink_cute = from_dlpack(\n attention_sinks, assumed_align=16\n ).mark_layout_dynamic(leading_dim=0)\n\n stream = cuda_driver.CUstream(torch.cuda.current_stream().cuda_stream)\n\n kernel_fn(\n q_cute,\n k_cute,\n v_cute,\n o_cute,\n problem_size,\n cum_seqlen_q_cute,\n cum_seqlen_k_cute,\n lse_cute,\n sink_cute,\n Float32(scale_softmax_log2),\n Float32(scale_softmax),\n Float32(scale_output),\n skip_threshold_log2,\n ws_left,\n ws_right,\n None, # skip_softmax_count\n None, # total_softmax_count\n stream,\n enable_pdl,\n None,\n None,\n None,\n None,\n None,\n )\n"},"diff":{"kind":"string","value":"--- flashinfer/attention/cute_dsl/fmha.py\n+++ flashinfer/attention/cute_dsl/fmha.py\n@@ -542,6 +542,11 @@\n None, # skip_softmax_count\n None, # total_softmax_count\n enable_pdl,\n+ None,\n+ None,\n+ None,\n+ None,\n+ None,\n )\n else:\n # CuTe native ABI: convert to cute tensors and pass with explicit stream.\n@@ -624,4 +629,9 @@\n None, # total_softmax_count\n stream,\n enable_pdl,\n+ None,\n+ None,\n+ None,\n+ None,\n+ None,\n )"},"lines_added":{"kind":"number","value":10,"string":"10"},"lines_removed":{"kind":"number","value":0,"string":"0"},"files_in_commit":{"kind":"number","value":5,"string":"5"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["B300","BLACKWELL","CPU"],"string":"[\n \"B300\",\n \"BLACKWELL\",\n \"CPU\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":["1.0675x","1.0552x","1.0737x","1.0751x","1.0364x","0.9955x","1.0022x","0.9523x","1.0123x","1.0809x"],"string":"[\n \"1.0675x\",\n \"1.0552x\",\n \"1.0737x\",\n \"1.0751x\",\n \"1.0364x\",\n \"0.9955x\",\n \"1.0022x\",\n \"0.9523x\",\n \"1.0123x\",\n \"1.0809x\"\n]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cute_dsl kernel file from flashinfer (flashinfer/attention/cute_dsl/fmha.py).\n\nGoal: perf(attention): Refresh DSL_FMHA cubins\nTarget hardware: B300, BLACKWELL, CPU\nTarget models: unspecified\n\nCurrent file:\n```python\n# Copyright (c) 2026 by FlashInfer team.\n#\n# Licensed under the Apache License, Version 2.0 (the \"License\");\n# you may not use this file except in compliance with the License.\n# You may obtain a copy of the License at\n#\n# http://www.apache.org/licenses/LICENSE-2.0\n#\n# Unless required by applicable law or agreed to in writing, software\n# distributed under the License is distributed on an \"AS IS\" BASIS,\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n# See the License for the specific language governing permissions and\n# limitations under the License.\n\"\"\"\nCuTe DSL FMHA Kernel Loader (Cubin Distribution)\n=================================================\n\nLoads pre-compiled FMHA kernel .so artifacts via ExternalBinaryModule.\nThe .so files are compiled offline from the proprietary DSL kernel source\nand distributed through the cubin_publishing pipeline.\n\nRuntime flow:\n 1. get_artifact() downloads .so from artifactory (or local cache)\n 2. ExternalBinaryModule loads .so and extracts callable kernel\n 3. cute_dsl_fmha_ragged_prefill() wraps the kernel with a PyTorch-friendly API\n\"\"\"\n\nimport functools\nimport logging\nimport math\nimport os\nfrom typing import Optional\n\nimport cutlass\nimport cutlass.cute as cute\nimport torch\nfrom cuda.bindings import driver as cuda_driver\nfrom cutlass.cute.runtime import from_dlpack\nfrom cutlass.cute.typing import Float32, Int32\n\nlogger = logging.getLogger(\"flashinfer.attention.cute_dsl.fmha\")\n\n\n# =============================================================================\n# Artifact configuration\n# =============================================================================\n\nfrom flashinfer.artifacts import ArtifactPath\n\nDSL_FMHA_ARTIFACT_PATH = ArtifactPath.DSL_FMHA\n\nfrom flashinfer.artifacts import _get_host_cpu_arch as _get_cpu_arch\n\n\ndef _get_gpu_arch(device: torch.device) -> str:\n \"\"\"Get the GPU architecture string for *device* (e.g. 'sm_100a').\n\n Uses the same normalization as CompilationContext to match the arch\n subdirectory names used by the cubin publishing pipeline.\n \"\"\"\n major, minor = torch.cuda.get_device_capability(device)\n from flashinfer.compilation_context import CompilationContext\n\n _, minor_str = CompilationContext._normalize_cuda_arch(major, minor)\n return f\"sm_{major}{minor_str}\"\n\n\n# Cache: arch -> {variant_name: sha256} parsed from downloaded checksums.txt\n_checksums_cache: dict[str, dict[str, str]] = {}\n\n\ndef _get_checksums(gpu_arch: str) -> dict[str, str]:\n \"\"\"Download and parse checksums.txt for the given arch.\n\n The checksums.txt is generated by compile_dsl_fmha.py and published\n alongside the .so files at <artifact_path>/<arch>/checksums.txt.\n Format per line: \"sha256 filename.so\"\n \"\"\"\n if gpu_arch in _checksums_cache:\n return _checksums_cache[gpu_arch]\n\n from flashinfer.jit.cubin_loader import download_file, safe_urljoin\n from flashinfer.jit.cubin_loader import FLASHINFER_CUBINS_REPOSITORY\n from flashinfer.jit.env import FLASHINFER_CUBIN_DIR\n\n cpu_arch = _get_cpu_arch()\n checksums_rel = os.path.join(\n DSL_FMHA_ARTIFACT_PATH, cpu_arch, gpu_arch, \"checksums.txt\"\n )\n local_path = FLASHINFER_CUBIN_DIR / checksums_rel\n\n if not local_path.exists():\n os.makedirs(local_path.parent, exist_ok=True)\n uri = safe_urljoin(FLASHINFER_CUBINS_REPOSITORY, checksums_rel)\n logger.info(f\"Fetching checksums for {gpu_arch} from {uri}\")\n download_file(uri, str(local_path))\n\n checksums = {}\n with open(local_path) as f:\n for line in f:\n line = line.strip()\n if not line:\n continue\n sha256, filename = line.split(None, 1)\n variant_name = filename.rsplit(\".\", 1)[0] # strip .so extension\n checksums[variant_name] = sha256\n\n _checksums_cache[gpu_arch] = checksums\n return checksums\n\n\ndef _dtype_to_str(dtype: torch.dtype) -> str:\n \"\"\"Convert torch dtype to short string matching compile_cute_dsl_fmha.py naming.\"\"\"\n return {\n torch.float16: \"fp16\",\n torch.bfloat16: \"bf16\",\n torch.float8_e4m3fn: \"e4m3\",\n }[dtype]\n\n\ndef _get_variant_name(\n qk_dtype: torch.dtype,\n pv_dtype: torch.dtype,\n out_dtype: torch.dtype,\n head_dim: int,\n is_causal: bool,\n is_persistent: bool = True,\n varlen: bool = False,\n with_lse: bool = False,\n enable_tvm_ffi: bool = False,\n enable_skip_softmax: bool = False,\n enable_sink: bool = False,\n use_pdl: bool = False,\n) -> str:\n \"\"\"Generate the variant name matching compile_cute_dsl_fmha.py naming convention.\"\"\"\n qk_str = _dtype_to_str(qk_dtype)\n pv_str = _dtype_to_str(pv_dtype)\n out_str = _dtype_to_str(out_dtype)\n # Include all three dtypes for partially quantized kernels. Preserve the\n # compact legacy names when QK and PV use the same dtype.\n dtype_str = (\n f\"{qk_str}_{pv_str}_{out_str}\"\n if qk_dtype != pv_dtype\n else f\"{qk_str}_{out_str}\"\n if qk_dtype != out_dtype\n else qk_str\n )\n causal_str = \"causal\" if is_causal else \"nocausal\"\n persist_str = \"persistent\" if is_persistent else \"nonpersistent\"\n varlen_str = \"_varlen\" if varlen else \"\"\n lse_str = \"_lse\" if with_lse else \"\"\n skip_str = \"_skipsm\" if enable_skip_softmax else \"\"\n sink_str = \"_sink\" if enable_sink else \"\"\n pdl_str = \"_pdl\" if use_pdl else \"\"\n ffi_str = \"_tvmffi\" if enable_tvm_ffi else \"\"\n return f\"cute_dsl_fmha_{dtype_str}_h{head_dim}_{causal_str}_{persist_str}{varlen_str}{lse_str}{skip_str}{sink_str}{pdl_str}{ffi_str}\"\n\n\n# =============================================================================\n# Loading: ExternalBinaryModule path\n# =============================================================================\n\n\ndef _load_from_artifact(variant_name: str, gpu_arch: str, enable_tvm_ffi: bool = False):\n \"\"\"Download .so from artifactory and load via ExternalBinaryModule.\n\n This is the production path used when cubins are published.\n\n Parameters\n ----------\n variant_name : str\n The kernel variant name (matches function_prefix used during export).\n gpu_arch : str\n GPU architecture string (e.g. 'sm_100a').\n enable_tvm_ffi : bool\n If False (default), load with CuTe native ABI.\n If True, load with TVM-FFI ABI (TODO: compile-side support pending).\n \"\"\"\n from flashinfer.jit.cubin_loader import get_artifact\n from flashinfer.jit.env import FLASHINFER_CUBIN_DIR\n\n so_filename = f\"{variant_name}.so\"\n cpu_arch = _get_cpu_arch()\n artifact_path = os.path.join(\n DSL_FMHA_ARTIFACT_PATH, cpu_arch, gpu_arch, so_filename\n )\n\n checksums = _get_checksums(gpu_arch)\n sha256 = checksums.get(variant_name, \"\")\n if not sha256:\n raise RuntimeError(\n f\"No checksum found for DSL FMHA variant '{variant_name}' on {gpu_arch}. \"\n f\"Available variants: {list(checksums.keys())}\"\n )\n\n # get_artifact downloads to FLASHINFER_CUBIN_DIR / artifact_path and verifies sha256\n data = get_artifact(artifact_path, sha256)\n if not data:\n raise RuntimeError(f\"Failed to download DSL FMHA artifact: {artifact_path}\")\n\n local_path = FLASHINFER_CUBIN_DIR / artifact_path\n module = cute.runtime.load_module(str(local_path), enable_tvm_ffi=enable_tvm_ffi)\n return getattr(module, variant_name)\n\n\ndef _load_from_local(variant_name: str, local_dir: str, enable_tvm_ffi: bool = False):\n \"\"\"Load .so or .o from a local directory (for development/testing).\n\n Set FLASHINFER_DSL_FMHA_LOCAL_DIR to use this path.\n\n Parameters\n ----------\n variant_name : str\n The kernel variant name (matches function_prefix used during export).\n local_dir : str\n Directory containing the compiled .so/.o files.\n enable_tvm_ffi : bool\n If False (default), load with CuTe native ABI.\n If True, load with TVM-FFI ABI (TODO: compile-side support pending).\n \"\"\"\n # Try .so first, then .o\n so_path = os.path.join(local_dir, f\"{variant_name}.so\")\n o_path = os.path.join(local_dir, f\"{variant_name}.o\")\n if os.path.exists(so_path):\n load_path = so_path\n elif os.path.exists(o_path):\n load_path = o_path\n else:\n raise FileNotFoundError(\n f\"DSL FMHA .so/.o not found at {local_dir}/{variant_name}.[so|o]. \"\n f\"Run compile_cute_dsl_fmha.py to generate it.\"\n )\n\n module = cute.runtime.load_module(load_path, enable_tvm_ffi=enable_tvm_ffi)\n return getattr(module, variant_name)\n\n\n@functools.cache\ndef get_cute_dsl_fmha_kernel(\n gpu_arch: str,\n qk_dtype: torch.dtype,\n pv_dtype: torch.dtype,\n out_dtype: torch.dtype,\n head_dim: int,\n is_causal: bool,\n is_persistent: bool = True,\n enable_tvm_ffi: bool = False,\n varlen: bool = False,\n with_lse: bool = False,\n enable_skip_softmax: bool = False,\n enable_sink: bool = False,\n use_pdl: bool = False,\n):\n \"\"\"Get a compiled DSL FMHA kernel function.\n\n Checks local directory first (FLASHINFER_DSL_FMHA_LOCAL_DIR env var),\n then falls back to artifact download.\n\n Parameters\n ----------\n gpu_arch : str\n GPU architecture string (e.g. 'sm_100a'), used both for selecting the\n correct artifact and as part of the cache key.\n qk_dtype : torch.dtype\n Query/key data type (torch.float16, torch.bfloat16, or\n torch.float8_e4m3fn).\n pv_dtype : torch.dtype\n Value data type (torch.float16, torch.bfloat16, or\n torch.float8_e4m3fn).\n out_dtype : torch.dtype\n Output data type. Same as qk_dtype for non-mixed precision.\n head_dim : int\n Head dimension (e.g., 64, 128, 192). Note: 192 only supports FP8.\n is_causal : bool\n Whether to use causal masking.\n is_persistent : bool\n Whether to use persistent kernel mode.\n enable_tvm_ffi : bool\n If False (default), load with CuTe native ABI — kernel accepts\n cute Pointer/Tensor args (same calling convention as JIT mode).\n If True, load with TVM-FFI ABI — Pointer args accept data_ptr(),\n Tensor args accept torch.Tensor directly, stream uses env stream.\n enable_skip_softmax : bool\n If True, load kernel compiled with skip-softmax support.\n\n Returns\n -------\n callable\n The compiled kernel function.\n \"\"\"\n variant_name = _get_variant_name(\n qk_dtype,\n pv_dtype,\n out_dtype,\n head_dim,\n is_causal,\n is_persistent,\n varlen=varlen,\n with_lse=with_lse,\n enable_tvm_ffi=enable_tvm_ffi,\n enable_skip_softmax=enable_skip_softmax,\n enable_sink=enable_sink,\n use_pdl=use_pdl,\n )\n\n # Check for local .so directory (development mode)\n local_dir = os.environ.get(\"FLASHINFER_DSL_FMHA_LOCAL_DIR\")\n if local_dir:\n logger.info(\n f\"Loading DSL FMHA kernel from local dir: {local_dir} (tvm_ffi={enable_tvm_ffi})\"\n )\n return _load_from_local(variant_name, local_dir, enable_tvm_ffi=enable_tvm_ffi)\n\n # Production path: download from artifactory\n logger.info(\n f\"Loading DSL FMHA kernel variant: {variant_name} (tvm_ffi={enable_tvm_ffi})\"\n )\n return _load_from_artifact(variant_name, gpu_arch, enable_tvm_ffi=enable_tvm_ffi)\n\n\n# =============================================================================\n# PyTorch API wrapper\n# =============================================================================\n\n\ndef cute_dsl_fmha_ragged_prefill(\n q: torch.Tensor,\n k: torch.Tensor,\n v: torch.Tensor,\n o: torch.Tensor,\n qo_indptr: torch.Tensor,\n kv_indptr: torch.Tensor,\n is_causal: bool = False,\n sm_scale: Optional[float] = None,\n window_left: int = -1,\n window_right: int = -1,\n lse: Optional[torch.Tensor] = None,\n attention_sinks: Optional[torch.Tensor] = None,\n scale_q: float = 1.0,\n scale_k: float = 1.0,\n scale_v: float = 1.0,\n scale_o: float = 1.0,\n enable_tvm_ffi: bool = True,\n max_qo_len: Optional[int] = None,\n max_kv_len: Optional[int] = None,\n kernel_fn=None,\n skip_softmax_threshold_scale_factor: Optional[float] = None,\n enable_pdl: bool = False,\n) -> None:\n \"\"\"Run DSL FMHA prefill kernel on ragged (variable-length) tensors.\n\n Note: The DSL FMHA kernel only supports per-tensor scalar scales, not\n per-head scale tensors.\n\n Parameters\n ----------\n q : torch.Tensor\n Query tensor, shape (total_q_tokens, H_q, D).\n k : torch.Tensor\n Key tensor, shape (total_kv_tokens, H_k, D).\n v : torch.Tensor\n Value tensor, shape (total_kv_tokens, H_k, D_v).\n o : torch.Tensor\n Output tensor, shape (total_q_tokens, H_q, D_v). Modified in-place.\n Must be 32-byte aligned (kernel uses 256-bit store instructions).\n qo_indptr : torch.Tensor\n Cumulative sequence lengths for Q/O, shape (batch_size + 1,).\n Same as cum_seqlen_q in DSL FMHA kernel.\n kv_indptr : torch.Tensor\n Cumulative sequence lengths for K/V, shape (batch_size + 1,).\n Same as cum_seqlen_k in DSL FMHA kernel.\n is_causal : bool\n Whether to apply causal masking.\n sm_scale : float, optional\n Softmax scale factor. Defaults to 1/sqrt(D).\n window_left : int\n Left sliding window size. -1 means no window.\n window_right : int\n Right sliding window size. -1 means no window. 0 for causal.\n lse : torch.Tensor, optional\n Log-sum-exp output tensor. None to skip.\n attention_sinks : torch.Tensor, optional\n Attention sink tensor, shape (H_q,) Float32. None to disable.\n scale_q : float\n Per-tensor scale for query (FP8 calibration). Default 1.0.\n scale_k : float\n Per-tensor scale for key (FP8 calibration). Default 1.0.\n scale_v : float\n Per-tensor scale for value (FP8 calibration). Default 1.0.\n scale_o : float\n Per-tensor scale for output (FP8 calibration). Default 1.0.\n enable_tvm_ffi : bool\n If True, use TVM-FFI ABI (pass data_ptr() for Pointer args, torch.Tensor\n for Tensor args, no explicit stream). Default False (CuTe native ABI).\n max_qo_len : int, optional\n Maximum query sequence length. Computed from qo_indptr if not provided.\n Pass this from plan() to avoid D2H copy during CUDA graph capture.\n max_kv_len : int, optional\n Maximum KV sequence length. Computed from kv_indptr if not provided.\n skip_softmax_threshold_scale_factor : float, optional\n Threshold scale factor for skip-softmax sparsity (https://arxiv.org/abs/2512.12087).\n The actual threshold = scale_factor / max_kv_len, then converted to log2 domain.\n None or 0 disables skip-softmax.\n \"\"\"\n total_q, H_q, D = q.shape\n total_kv, H_k, _ = k.shape\n D_v = v.shape[-1]\n\n batch_size = len(qo_indptr) - 1\n\n use_skip_softmax = (\n skip_softmax_threshold_scale_factor is not None\n and skip_softmax_threshold_scale_factor > 0\n )\n\n if kernel_fn is None:\n gpu_arch = _get_gpu_arch(q.device)\n # Q and K feed the same GEMM operand dtype: neither the prebuilt\n # artifacts nor the JIT compile (single qk_dtype) support q != k.\n if q.dtype != k.dtype:\n raise ValueError(\n f\"cute-dsl FMHA requires q.dtype == k.dtype, got {q.dtype} and {k.dtype}\"\n )\n try:\n if window_left != -1 or window_right != -1:\n # The exported artifact matrix has no window axis: every\n # prebuilt variant is traced with window_size_left=None (and\n # window_size_right present only for causal), so a windowed\n # call into one fails the FFI signature check. The causal\n # artifact lookup would falsely succeed here — force JIT.\n raise RuntimeError(\"windowed DSL FMHA variants are not exported\")\n kernel_fn = get_cute_dsl_fmha_kernel(\n gpu_arch,\n q.dtype,\n v.dtype,\n o.dtype,\n D,\n is_causal,\n is_persistent=False, # varlen always uses non-persistent\n varlen=True,\n enable_tvm_ffi=enable_tvm_ffi,\n with_lse=lse is not None,\n enable_skip_softmax=use_skip_softmax,\n enable_sink=attention_sinks is not None,\n use_pdl=enable_pdl,\n )\n except (RuntimeError, FileNotFoundError) as e:\n # Cubin variant not available / repo unreachable.\n # JIT-compile the trtllm kernel instead.\n logger.info(f\"DSL FMHA cubin unavailable ({e}); JIT-compiling the kernel.\")\n from flashinfer.cute_dsl.attention.fmha.compile import (\n compile_cute_dsl_fmha_kernel,\n )\n\n kernel_fn = compile_cute_dsl_fmha_kernel(\n q.dtype,\n v.dtype,\n o.dtype,\n H_q,\n H_k,\n D,\n D_v,\n is_causal,\n lse is not None,\n attention_sinks is not None,\n use_skip_softmax,\n enable_pdl,\n q.device,\n has_window_left=window_left != -1,\n has_window_right=is_causal or window_right != -1,\n )\n # JIT kernels are compiled with --enable-tvm-ffi; the CuTe-native branch\n # would not accept them.\n enable_tvm_ffi = True\n\n # Compute scale factors\n if sm_scale is None:\n sm_scale = 1.0 / math.sqrt(D)\n log2_e = math.log2(math.exp(1.0))\n scale_softmax = scale_q * scale_k * sm_scale\n scale_softmax_log2 = scale_softmax * log2_e\n scale_output = scale_v / scale_o\n\n # Max seq lengths for problem_size (prefer pre-computed values for CUDA graph compat)\n if max_qo_len is None:\n max_s_q = int((qo_indptr.cpu()[1:] - qo_indptr.cpu()[:-1]).max().item())\n else:\n max_s_q = max_qo_len\n if max_kv_len is None:\n max_s_k = int((kv_indptr.cpu()[1:] - kv_indptr.cpu()[:-1]).max().item())\n else:\n max_s_k = max_kv_len\n\n # problem_size: (B, max_s_q, s_lse, max_s_k, H_q, H_k, D, D_v)\n s_lse = total_q # for variable length, s_lse = total tokens\n problem_size = (batch_size, max_s_q, s_lse, max_s_k, H_q, H_k, D, D_v)\n\n # Skip-softmax threshold (convert scale_factor to log2 domain)\n skip_threshold_log2 = None\n if use_skip_softmax:\n threshold = skip_softmax_threshold_scale_factor / max_s_k\n skip_threshold_log2 = Float32(math.log2(threshold))\n\n # Window sizes\n ws_left = None if window_left == -1 else Int32(window_left)\n ws_right = None if window_right == -1 else Int32(window_right)\n if is_causal and ws_right is None:\n ws_right = Int32(0)\n\n # Reshape to 5D matching kernel docstring:\n # q/o: (b=1, total, h_k, h_r, d/dv)\n # k/v: (b=1, total, h_k, 1, d/dv)\n h_r = H_q // H_k\n q_5d = q.view(1, total_q, H_k, h_r, D)\n k_5d = k.view(1, total_kv, H_k, 1, D)\n v_5d = v.view(1, total_kv, H_k, 1, D_v)\n assert o.data_ptr() % 32 == 0, (\n \"o must be 32-byte aligned (kernel uses 256-bit store instructions)\"\n )\n o_5d = o.view(1, total_q, H_k, h_r, D_v)\n # LSE: (1, total_q, h_k, h_r) — 4D row-major.\n lse_4d = lse.view(1, total_q, H_k, h_r) if lse is not None else None\n\n if enable_tvm_ffi:\n # TVM-FFI: pass torch.Tensor directly, no explicit stream (env stream).\n kernel_fn(\n q_5d,\n k_5d,\n v_5d,\n o_5d,\n problem_size,\n qo_indptr.to(torch.int32), # cum_seqlen_q\n kv_indptr.to(torch.int32), # cum_seqlen_k\n lse_4d,\n attention_sinks,\n Float32(scale_softmax_log2),\n Float32(scale_softmax),\n Float32(scale_output),\n skip_threshold_log2,\n ws_left,\n ws_right,\n None, # skip_softmax_count\n None, # total_softmax_count\n enable_pdl,\n )\n else:\n # CuTe native ABI: convert to cute tensors and pass with explicit stream.\n is_fp8_qk = q.dtype == torch.float8_e4m3fn\n is_fp8_pv = v.dtype == torch.float8_e4m3fn\n is_fp8_out = o.dtype == torch.float8_e4m3fn\n if is_fp8_qk:\n q_cute = from_dlpack(\n q_5d.view(torch.int8), assumed_align=16\n ).mark_layout_dynamic(leading_dim=4)\n q_cute.element_type = cutlass.Float8E4M3FN\n k_cute = from_dlpack(\n k_5d.view(torch.int8), assumed_align=16\n ).mark_layout_dynamic(leading_dim=4)\n k_cute.element_type = cutlass.Float8E4M3FN\n else:\n q_cute = from_dlpack(q_5d, assumed_align=16).mark_layout_dynamic(\n leading_dim=4\n )\n k_cute = from_dlpack(k_5d, assumed_align=16).mark_layout_dynamic(\n leading_dim=4\n )\n if is_fp8_pv:\n v_cute = from_dlpack(\n v_5d.view(torch.int8), assumed_align=16\n ).mark_layout_dynamic(leading_dim=4)\n v_cute.element_type = cutlass.Float8E4M3FN\n else:\n v_cute = from_dlpack(v_5d, assumed_align=16).mark_layout_dynamic(\n leading_dim=4\n )\n if is_fp8_out:\n o_cute = from_dlpack(\n o_5d.view(torch.int8), assumed_align=32\n ).mark_layout_dynamic(leading_dim=4)\n o_cute.element_type = cutlass.Float8E4M3FN\n else:\n o_cute = from_dlpack(o_5d, assumed_align=32).mark_layout_dynamic(\n leading_dim=4\n )\n\n cum_seqlen_q_cute = from_dlpack(\n qo_indptr.to(torch.int32), assumed_align=16\n ).mark_layout_dynamic(leading_dim=0)\n cum_seqlen_k_cute = from_dlpack(\n kv_indptr.to(torch.int32), assumed_align=16\n ).mark_layout_dynamic(leading_dim=0)\n\n lse_cute = None\n if lse_4d is not None:\n lse_cute = from_dlpack(lse_4d, assumed_align=16).mark_layout_dynamic(\n leading_dim=3\n )\n\n sink_cute = None\n if attention_sinks is not None:\n sink_cute = from_dlpack(\n attention_sinks, assumed_align=16\n ).mark_layout_dynamic(leading_dim=0)\n\n stream = cuda_driver.CUstream(torch.cuda.current_stream().cuda_stream)\n\n kernel_fn(\n q_cute,\n k_cute,\n v_cute,\n o_cute,\n problem_size,\n cum_seqlen_q_cute,\n cum_seqlen_k_cute,\n lse_cute,\n sink_cute,\n Float32(scale_softmax_log2),\n Float32(scale_softmax),\n Float32(scale_output),\n skip_threshold_log2,\n ws_left,\n ws_right,\n None, # skip_softmax_count\n None, # total_softmax_count\n stream,\n enable_pdl,\n )\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\n<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->\n\n+ Refresh DSL_FMHA cubins\n+ Minimal change to source code to keep backward compatibility (unlike cubin builder, FlashInfer needs to ensure JIT source compatibility with multiple `nvidia-cutlass-dsl` versions).\n\n### Performance on B300\n\nBase shape: B=2, H=16, D=128 data:\n- Internal compiler scheduling decision might have caused regression in some shapes, but overall there is a consistent latency improvement over the Blackwell Ultra horizon:\n\n| S | Causal | QK/V | `main` median (ms) | Refresh median (ms) | Refresh latency delta | Refresh speedup |\n|---:|:------:|:------|-------------------:|--------------------:|----------------------:|----------------:|\n| 2048 | True | BF16/BF16 | 0.064800 | 0.060704 | -6.32% | 1.0675x |\n| 2048 | True | BF16/FP8 | 0.059040 | 0.055952 | -5.23% | 1.0552x |\n| 2048 | True | FP8/FP8 | 0.053393 | 0.049728 | -6.86% | 1.0737x |\n| 2048 | False | BF16/BF16 | 0.070321 | 0.065408 | -6.99% | 1.0751x |\n| 2048 | False | BF16/FP8 | 0.061056 | 0.058912 | -3.51% | 1.0364x |\n| 2048 | False | FP8/FP8 | 0.049504 | 0.049729 | +0.45% | 0.9955x |\n| 16384 | True | BF16/BF16 | 1.386919 | 1.383943 | -0.21% | 1.0022x |\n| 16384 | True | BF16/FP8 | 1.114918 | 1.170806 | +5.01% | 0.9523x |\n| 16384 | True | FP8/FP8 | 1.050949 | 1.038149 | -1.22% | 1.0123x |\n| 16384 | False | BF16/BF16 | 2.621342 | 2.425229 | -7.48% | 1.0809x |\n| 16384 | False | BF16/FP8 | 2.146891 | 2.001659 | -6.76% | 1.0726x |\n| 16384 | False | FP8/FP8 | 1.764121 | 1.729594 | -1.96% | 1.0200x |\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\nN/A\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n## 🔬 Experimental Track\n\n<!-- Only for PRs submitted under the experimental policy (CONTRIBUTING.md → \"Experimental APIs and Backends\").\n Leave this section untouched for normal PRs. -->\n\n- [ ] This PR is **experimental**: it adds or changes code under `flashinfer/experimental/` and/or an `@flashinfer_experimental_api`. Tracking issue: #\n - [ ] The tracking issue names an owner, the reason for the experimental path, and a graduation plan with a target release.\n - [ ] Core changes are limited to a thin entry point (signature, shared validation, feature-gate check, backend selection, handoff).\n - [ ] Tests live in `tests/experimental/` and were validated on the intended hardware; a runnable example is included.\n - [ ] Nothing is registered in `flashinfer/aot.py`, and no experimental backend is reachable from `backend=\"auto\"` without `FLASHINFER_ALLOW_EXPERIMENTAL_AUTO_BACKENDS=1`. (Calling an `@flashinfer_experimental_api` or naming a backend explicitly is itself the opt-in and needs no environment variable.)\n - [ ] **Test scope declared below.** The experimental CI lane runs exactly these targets, so keep them as narrow as the change allows.\n\n<!-- Required for experimental PRs. Replace the commented lines below with your targets.\n Do not delete the fence or change its `experimental-tests` tag — the experimental-track\n watcher reads it verbatim to decide which targets to ask CI for. -->\n\n```experimental-tests\n# One target per line: a directory or a file. (A pytest ::selector is not\n# supported -- the sharding runner cannot consume one.) Must be under\n# tests/experimental/ and must exist. Delete these comment lines and add yours, e.g.\n#\n# tests/experimental/test_my_backend.py\n# tests/experimental/my_backend/\n#\n# Declaring the whole tree (tests/experimental/) is allowed but means every\n# experimental PR pays for every other feature's tests, in every matrix cell.\n```\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc. -->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n- **Bug Fixes**\n - Updated the CuTe DSL fused multi-head attention backend for compatibility with the latest kernel interface.\n - Improved softmax-scaling behavior for skip-softmax and low-precision attention modes.\n - Added configurable rescaling thresholds for standard and block-scaled attention paths.\n - Refreshed backend artifacts and checksums across supported GPU and CPU architectures.\n- **Documentation**\n - Clarified CuTe DSL attention backend coverage, including ALiBi and modular prefill behavior.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": \"B300\", \"model\": null, \"shape\": \"S=2048\", \"batch_size\": 2, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.0648, \"optimized\": 0.060704, \"stated_speedup\": 1.0675, \"speedup\": 1.0675}, {\"scope\": \"kernel\", \"hardware\": \"B300\", \"model\": null, \"shape\": \"S=2048\", \"batch_size\": 2, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.05904, \"optimized\": 0.055952, \"stated_speedup\": 1.0552, \"speedup\": 1.0552}, {\"scope\": \"kernel\", \"hardware\": \"B300\", \"model\": null, \"shape\": \"S=2048\", \"batch_size\": 2, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.053393, \"optimized\": 0.049728, \"stated_speedup\": 1.0737, \"speedup\": 1.0737}, {\"scope\": \"kernel\", \"hardware\": \"B300\", \"model\": null, \"shape\": \"S=2048\", \"batch_size\": 2, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.070321, \"optimized\": 0.065408, \"stated_speedup\": 1.0751, \"speedup\": 1.0751}, {\"scope\": \"kernel\", \"hardware\": \"B300\", \"model\": null, \"shape\": \"S=2048\", \"batch_size\": 2, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.061056, \"optimized\": 0.058912, \"stated_speedup\": 1.0364, \"speedup\": 1.0364}, {\"scope\": \"kernel\", \"hardware\": \"B300\", \"model\": null, \"shape\": \"S=2048\", \"batch_size\": 2, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.049504, \"optimized\": 0.049729, \"stated_speedup\": 0.9955, \"speedup\": 0.9955}, {\"scope\": \"kernel\", \"hardware\": \"B300\", \"model\": null, \"shape\": \"S=16384\", \"batch_size\": 2, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.386919, \"optimized\": 1.383943, \"stated_speedup\": 1.0022, \"speedup\": 1.0022}, {\"scope\": \"kernel\", \"hardware\": \"B300\", \"model\": null, \"shape\": \"S=16384\", \"batch_size\": 2, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.114918, \"optimized\": 1.170806, \"stated_speedup\": 0.9523, \"speedup\": 0.9523}, {\"scope\": \"kernel\", \"hardware\": \"B300\", \"model\": null, \"shape\": \"S=16384\", \"batch_size\": 2, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.050949, \"optimized\": 1.038149, \"stated_speedup\": 1.0123, \"speedup\": 1.0123}, {\"scope\": \"kernel\", \"hardware\": \"B300\", \"model\": null, \"shape\": \"S=16384\", \"batch_size\": 2, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 2.621342, \"optimized\": 2.425229, \"stated_speedup\": 1.0809, \"speedup\": 1.0809}, {\"scope\": \"kernel\", \"hardware\": \"B300\", \"model\": null, \"shape\": \"S=16384\", \"batch_size\": 2, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 2.146891, \"optimized\": 2.001659, \"stated_speedup\": 1.0726, \"speedup\": 1.0726}, {\"scope\": \"kernel\", \"hardware\": \"B300\", \"model\": null, \"shape\": \"S=16384\", \"batch_size\": 2, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.764121, \"optimized\": 1.729594, \"stated_speedup\": 1.02, \"speedup\": 1.02}]"},"kernel_speedup":{"kind":"number","value":1.0458,"string":"1.0458"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1062,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"75038cdf67a5ba577ef4b329badc301f185c5a95"},"date":{"kind":"string","value":"2026-09-10T02:48:58+09:00"},"pr_number":{"kind":"number","value":4997,"string":"4,997"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/4997"},"title":{"kind":"string","value":"perf(attention): Refresh DSL_FMHA cubins (#4997)"},"message":{"kind":"string","value":"perf(attention): Refresh DSL_FMHA cubins (#4997)\n\n<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\n<!-- What does this PR do? Briefly describe the changes and why they’re\nneeded. -->\n\n+ Refresh DSL_FMHA cubins\n+ Minimal change to source code to keep backward compatibility (unlike\ncubin builder, FlashInfer needs to ensure JIT source compatibility with\nmultiple `nvidia-cutlass-dsl` versions).\n\n### Performance on B300\n\nBase shape: B=2, H=16, D=128 data:\n- Internal compiler scheduling decision might have caused regression in\nsome shapes, but overall there is a consistent latency improvement over\nthe Blackwell Ultra horizon:\n\n| S | Causal | QK/V | `main` median (ms) | Refresh median (ms) | Refresh\nlatency delta | Refresh speedup |\n\n|---:|:------:|:------|-------------------:|--------------------:|----------------------:|----------------:|\n| 2048 | True | BF16/BF16 | 0.064800 | 0.060704 | -6.32% | 1.0675x |\n| 2048 | True | BF16/FP8 | 0.059040 | 0.055952 | -5.23% | 1.0552x |\n| 2048 | True | FP8/FP8 | 0.053393 | 0.049728 | -6.86% | 1.0737x |\n| 2048 | False | BF16/BF16 | 0.070321 | 0.065408 | -6.99% | 1.0751x |\n| 2048 | False | BF16/FP8 | 0.061056 | 0.058912 | -3.51% | 1.0364x |\n| 2048 | False | FP8/FP8 | 0.049504 | 0.049729 | +0.45% | 0.9955x |\n| 16384 | True | BF16/BF16 | 1.386919 | 1.383943 | -0.21% | 1.0022x |\n| 16384 | True | BF16/FP8 | 1.114918 | 1.170806 | +5.01% | 0.9523x |\n| 16384 | True | FP8/FP8 | 1.050949 | 1.038149 | -1.22% | 1.0123x |\n| 16384 | False | BF16/BF16 | 2.621342 | 2.425229 | -7.48% | 1.0809x |\n| 16384 | False | BF16/FP8 | 2.146891 | 2.001659 | -6.76% | 1.0726x |\n| 16384 | False | FP8/FP8 | 1.764121 | 1.729594 | -1.96% | 1.0200x |\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\nN/A\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the\npre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n## 🔬 Experimental Track\n\n<!-- Only for PRs submitted under the experimental policy\n(CONTRIBUTING.md → \"Experimental APIs and Backends\").\n Leave this section untouched for normal PRs. -->\n\n- [ ] This PR is **experimental**: it adds or changes code under\n`flashinfer/experimental/` and/or an `@flashinfer_experimental_api`.\nTracking issue: #\n- [ ] The tracking issue names an owner, the reason for the experimental\npath, and a graduation plan with a target release.\n- [ ] Core changes are limited to a thin entry point (signature, shared\nvalidation, feature-gate check, backend selection, handoff).\n- [ ] Tests live in `tests/experimental/` and were validated on the\nintended hardware; a runnable example is included.\n- [ ] Nothing is registered in `flashinfer/aot.py`, and no experimental\nbackend is reachable from `backend=\"auto\"` without\n`FLASHINFER_ALLOW_EXPERIMENTAL_AUTO_BACKENDS=1`. (Calling an\n`@flashinfer_experimental_api` or naming a backend explicitly is itself\nthe opt-in and needs no environment variable.)\n- [ ] **Test scope declared below.** The experimental CI lane runs\nexactly these targets, so keep them as narrow as the change allows.\n\n<!-- Required for experimental PRs. Replace the commented lines below\nwith your targets.\nDo not delete the fence or change its `experimental-tests` tag — the\nexperimental-track\nwatcher reads it verbatim to decide which targets to ask CI for. -->\n\n```experimental-tests\n# One target per line: a directory or a file. (A pytest ::selector is not\n# supported -- the sharding runner cannot consume one.) Must be under\n# tests/experimental/ and must exist. Delete these comment lines and add yours, e.g.\n#\n# tests/experimental/test_my_backend.py\n# tests/experimental/my_backend/\n#\n# Declaring the whole tree (tests/experimental/) is allowed but means every\n# experimental PR pays for every other feature's tests, in every matrix cell.\n```\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc.\n-->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n- **Bug Fixes**\n- Updated the CuTe DSL fused multi-head attention backend for\ncompatibility with the latest kernel interface.\n- Improved softmax-scaling behavior for skip-softmax and low-precision\nattention modes.\n- Added configurable rescaling thresholds for standard and block-scaled\nattention paths.\n- Refreshed backend artifacts and checksums across supported GPU and CPU\narchitectures.\n- **Documentation**\n- Clarified CuTe DSL attention backend coverage, including ALiBi and\nmodular prefill behavior.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->"},"path":{"kind":"string","value":"flashinfer/cute_dsl/attention/fmha/compile.py"},"language":{"kind":"string","value":"cute_dsl"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"# SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.\n# SPDX-License-Identifier: Apache-2.0\n#\n# Licensed under the Apache License, Version 2.0 (the \"License\");\n# you may not use this file except in compliance with the License.\n# You may obtain a copy of the License at\n#\n# http://www.apache.org/licenses/LICENSE-2.0\n#\n# Unless required by applicable law or agreed to in writing, software\n# distributed under the License is distributed on an \"AS IS\" BASIS,\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n# See the License for the specific language governing permissions and\n# limitations under the License.\n\"\"\"JIT-compilers for the trtllm CuTe DSL FMHA kernels.\n\n``compile_cute_dsl_fmha_kernel`` / ``compile_cute_dsl_fmha_blockscaled_kernel``\n``cute.compile`` (and cache) the trtllm ``BlackwellFusedMultiHead[BlockScaled]AttentionForward``\nclasses with symbolic batch/seqlen dims, returning a TVM-FFI-callable kernel handle.\n\"\"\"\n\nimport functools\nimport math\n\nimport cutlass\nimport cutlass.cute as cute\nimport torch\nfrom cutlass.cute.runtime import make_fake_compact_tensor, make_fake_stream\nfrom cutlass.cute.typing import Float32, Int32\n\n# torch dtype -> cutlass dtype\n_CUTLASS_DTYPE = {\n torch.float16: cutlass.Float16,\n torch.bfloat16: cutlass.BFloat16,\n torch.float8_e4m3fn: cutlass.Float8E4M3FN,\n}\n\n# Block-scaling mode -> (qk cutlass dtype, sf cutlass dtype, sf_vec_size)\n_BLOCKSCALED_MODES = {\n \"mxfp8\": (cutlass.Float8E4M3FN, cutlass.Float8E8M0FNU, 32),\n \"nvfp4\": (cutlass.Float4E2M1FN, cutlass.Float8E4M3FN, 16),\n}\n\n\ndef _mask_type(is_causal: bool):\n from .helpers import fmha_helpers as fmha_utils\n\n # Bottom-right aligned causal, matching FlashInfer convention.\n return (\n fmha_utils.MaskEnum.WINDOW_MASK_INFERENCE\n if is_causal\n else fmha_utils.MaskEnum.RESIDUAL_MASK\n )\n\n\ndef _ex2_emulation_enabled(device: torch.device) -> bool:\n # ex2 emulation is only beneficial / correct on CC 10.0 (sm_100/sm_100a/sm_100f);\n # not on sm_103 (CC 10.3) or later archs.\n return torch.cuda.get_device_capability(device) == (10, 0)\n\n\n# =============================================================================\n# Non-block-scaled\n# =============================================================================\n\n\n@functools.cache\ndef compile_cute_dsl_fmha_kernel(\n qk_dtype: torch.dtype,\n v_dtype: torch.dtype,\n out_dtype: torch.dtype,\n num_qo_heads: int,\n num_kv_heads: int,\n head_dim: int,\n head_dim_v: int,\n is_causal: bool,\n with_lse: bool,\n enable_sink: bool,\n enable_skip_softmax: bool,\n use_pdl: bool,\n device: torch.device,\n has_window_left: bool = False,\n has_window_right=None,\n):\n \"\"\"Compile (and cache) the trtllm FMHA kernel for a static config.\n\n Compiles with the TVM-FFI ABI (the handle takes ``torch.Tensor`` args on the env\n stream) and symbolic batch/seqlen dims, so a single compile serves all shapes for the\n given dtypes / head counts / head_dim / mask.\n\n Sliding-window bounds follow a presence/value split: only bound *presence*\n (``has_window_left`` / ``has_window_right``) specializes the kernel — the\n DSL traces ``Optional[Int32]`` window args as present-or-None — while the\n bound values are runtime arguments, so one compile serves every window\n size. ``has_window_right=None`` derives presence from ``is_causal``\n (causal is a right bound with runtime value 0).\n \"\"\"\n from .fmha import BlackwellFusedMultiHeadAttentionForward\n\n if has_window_right is None:\n has_window_right = is_causal\n enable_ex2_emulation = _ex2_emulation_enabled(device)\n qk = _CUTLASS_DTYPE[qk_dtype]\n pv = _CUTLASS_DTYPE[v_dtype]\n out = _CUTLASS_DTYPE[out_dtype]\n d = head_dim\n dv = head_dim_v\n head_dim_arg = d if d == dv else (d, dv)\n\n fmha = BlackwellFusedMultiHeadAttentionForward(\n qk_acc_dtype=cutlass.Float32,\n pv_acc_dtype=cutlass.Float32,\n mma_tiler=(128, 128),\n head_dim=head_dim_arg,\n is_persistent=False, # varlen ragged\n # Any band bound (causal or sliding window) uses the window mask.\n mask_type=_mask_type(has_window_left or has_window_right),\n enable_ex2_emulation=enable_ex2_emulation,\n enable_skip_correction=True,\n use_tma_store=False, # varlen -> STG\n )\n\n sym_b = cute.sym_int()\n sym_s_q = cute.sym_int()\n sym_s_k = cute.sym_int()\n sym_hk = cute.sym_int()\n sym_hr = cute.sym_int()\n sym_seq = cute.sym_int()\n q_fake = make_fake_compact_tensor(\n qk,\n (sym_b, sym_s_q, sym_hk, sym_hr, d),\n stride_order=(4, 3, 2, 1, 0),\n assumed_align=16,\n )\n k_fake = make_fake_compact_tensor(\n qk,\n (sym_b, sym_s_k, sym_hk, 1, d),\n stride_order=(4, 3, 2, 1, 0),\n assumed_align=16,\n )\n v_fake = make_fake_compact_tensor(\n pv,\n (sym_b, sym_s_k, sym_hk, 1, dv),\n stride_order=(4, 3, 2, 1, 0),\n assumed_align=16,\n )\n o_fake = make_fake_compact_tensor(\n out,\n (sym_b, sym_s_q, sym_hk, sym_hr, dv),\n stride_order=(4, 3, 2, 1, 0),\n assumed_align=32,\n )\n lse_fake = (\n make_fake_compact_tensor(\n cutlass.Float32,\n (sym_b, sym_s_q, sym_hk, sym_hr),\n stride_order=(3, 2, 1, 0),\n assumed_align=16,\n )\n if with_lse\n else None\n )\n sink_fake = (\n make_fake_compact_tensor(\n cutlass.Float32, (cute.sym_int(),), stride_order=(0,), assumed_align=16\n )\n if enable_sink\n else None\n )\n cum_q_fake = make_fake_compact_tensor(Int32, (sym_seq,), assumed_align=16)\n cum_k_fake = make_fake_compact_tensor(Int32, (sym_seq,), assumed_align=16)\n\n problem_size = (1, 1, 1, 1, num_qo_heads, num_kv_heads, d, dv)\n scale_softmax = 1.0 / math.sqrt(d)\n skip_threshold_log2 = Float32(0.0) if enable_skip_softmax else None\n # Trace-time presence only; the traced 0s are placeholders and the real\n # bound values arrive as runtime arguments on each call.\n ws_left = Int32(0) if has_window_left else None\n ws_right = Int32(0) if has_window_right else None\n stream_fake = make_fake_stream(use_tvm_ffi_env_stream=True)\n\n return cute.compile(\n fmha,\n q_fake,\n k_fake,\n v_fake,\n o_fake,\n problem_size,\n cum_q_fake,\n cum_k_fake,\n lse_fake,\n sink_fake,\n scale_softmax * math.log2(math.e),\n scale_softmax,\n 1.0,\n skip_threshold_log2,\n ws_left,\n ws_right,\n None,\n None,\n stream_fake,\n use_pdl,\n options=\"--enable-tvm-ffi --opt-level 2\",\n )\n\n\n# =============================================================================\n# Block-scaled (MXFP8 / NVFP4)\n# =============================================================================\n\n\n@functools.cache\ndef compile_cute_dsl_fmha_blockscaled_kernel(\n qk_mode: str,\n pv_dtype: torch.dtype,\n out_dtype: torch.dtype,\n num_qo_heads: int,\n num_kv_heads: int,\n head_dim: int,\n is_causal: bool,\n with_lse: bool,\n enable_skip_softmax: bool,\n use_pdl: bool,\n device: torch.device,\n has_window_left: bool = False,\n has_window_right=None,\n):\n \"\"\"Compile (and cache) the trtllm block-scaled FMHA kernel (batched, non-varlen).\"\"\"\n from .fmha_blockscaled import BlackwellFusedMultiHeadBlockScaledAttentionForward\n\n if has_window_right is None:\n has_window_right = is_causal\n enable_ex2_emulation = _ex2_emulation_enabled(device)\n qk, sf_dt, sf_vec = _BLOCKSCALED_MODES[qk_mode]\n pv = _CUTLASS_DTYPE[pv_dtype]\n out = _CUTLASS_DTYPE[out_dtype]\n d = dv = head_dim\n\n fmha = BlackwellFusedMultiHeadBlockScaledAttentionForward(\n qk_acc_dtype=cutlass.Float32,\n pv_acc_dtype=cutlass.Float32,\n mma_tiler=(128, 128),\n head_dim=d,\n is_persistent=False,\n mask_type=_mask_type(has_window_left or has_window_right),\n enable_ex2_emulation=enable_ex2_emulation,\n enable_skip_correction=True,\n qk_sf_vec_size=sf_vec,\n use_tma_store=True, # non-varlen\n )\n\n sym_b = cute.sym_int()\n sym_s_q = cute.sym_int()\n sym_s_k = cute.sym_int()\n sym_hk = cute.sym_int()\n sym_hr = cute.sym_int()\n # Sub-byte (fp4) stride-1 dim must be static.\n sym_d = d if qk.width < 8 else cute.sym_int()\n sym_dv = dv if qk.width < 8 else cute.sym_int()\n q_fake = make_fake_compact_tensor(\n qk,\n (sym_b, sym_s_q, sym_hk, sym_hr, sym_d),\n stride_order=(4, 3, 2, 1, 0),\n assumed_align=16,\n )\n k_fake = make_fake_compact_tensor(\n qk,\n (sym_b, sym_s_k, sym_hk, 1, sym_d),\n stride_order=(4, 3, 2, 1, 0),\n assumed_align=16,\n )\n v_fake = make_fake_compact_tensor(\n pv,\n (sym_b, sym_s_k, sym_hk, 1, sym_dv),\n stride_order=(4, 3, 2, 1, 0),\n assumed_align=16,\n )\n o_fake = make_fake_compact_tensor(\n out,\n (sym_b, sym_s_q, sym_hk, sym_hr, sym_dv),\n stride_order=(4, 3, 2, 1, 0),\n assumed_align=32,\n )\n # The fused quantizer produces the same contiguous 128x4-swizzled storage.\n # Expose it through the compiler's 6D ABI: (L, M/128, SF_K/4, 32, 4, 4).\n sym_sf_k_tiles = cute.sym_int()\n q_sf_fake = make_fake_compact_tensor(\n sf_dt,\n (cute.sym_int(), cute.sym_int(), sym_sf_k_tiles, 32, 4, 4),\n stride_order=(5, 4, 3, 2, 1, 0),\n assumed_align=16,\n )\n k_sf_fake = make_fake_compact_tensor(\n sf_dt,\n (cute.sym_int(), cute.sym_int(), sym_sf_k_tiles, 32, 4, 4),\n stride_order=(5, 4, 3, 2, 1, 0),\n assumed_align=16,\n )\n lse_fake = (\n make_fake_compact_tensor(\n cutlass.Float32,\n (sym_b, sym_s_q, sym_hk, sym_hr),\n stride_order=(3, 2, 1, 0),\n assumed_align=16,\n )\n if with_lse\n else None\n )\n\n problem_size = (1, 1, 1, 1, num_qo_heads, num_kv_heads, d, dv)\n scale_softmax = 1.0 / math.sqrt(d)\n skip_threshold_log2 = Float32(0.0) if enable_skip_softmax else None\n ws_left = Int32(0) if has_window_left else None\n ws_right = Int32(0) if has_window_right else None\n stream_fake = make_fake_stream(use_tvm_ffi_env_stream=True)\n\n return cute.compile(\n fmha,\n q_fake,\n k_fake,\n q_sf_fake,\n k_sf_fake,\n v_fake,\n o_fake,\n problem_size,\n None, # cum_seqlen_q (non-varlen)\n None, # cum_seqlen_k\n lse_fake,\n None, # sink\n scale_softmax * math.log2(math.e),\n scale_softmax,\n 1.0,\n None, # scale_v_channels\n skip_threshold_log2,\n ws_left,\n ws_right,\n None,\n None,\n stream_fake,\n use_pdl,\n options=\"--enable-tvm-ffi --opt-level 2\",\n )\n"},"after_code":{"kind":"string","value":"# SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.\n# SPDX-License-Identifier: Apache-2.0\n#\n# Licensed under the Apache License, Version 2.0 (the \"License\");\n# you may not use this file except in compliance with the License.\n# You may obtain a copy of the License at\n#\n# http://www.apache.org/licenses/LICENSE-2.0\n#\n# Unless required by applicable law or agreed to in writing, software\n# distributed under the License is distributed on an \"AS IS\" BASIS,\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n# See the License for the specific language governing permissions and\n# limitations under the License.\n\"\"\"JIT-compilers for the trtllm CuTe DSL FMHA kernels.\n\n``compile_cute_dsl_fmha_kernel`` / ``compile_cute_dsl_fmha_blockscaled_kernel``\n``cute.compile`` (and cache) the trtllm ``BlackwellFusedMultiHead[BlockScaled]AttentionForward``\nclasses with symbolic batch/seqlen dims, returning a TVM-FFI-callable kernel handle.\n\"\"\"\n\nimport functools\nimport math\n\nimport cutlass\nimport cutlass.cute as cute\nimport torch\nfrom cutlass.cute.runtime import make_fake_compact_tensor, make_fake_stream\nfrom cutlass.cute.typing import Float32, Int32\n\n# torch dtype -> cutlass dtype\n_CUTLASS_DTYPE = {\n torch.float16: cutlass.Float16,\n torch.bfloat16: cutlass.BFloat16,\n torch.float8_e4m3fn: cutlass.Float8E4M3FN,\n}\n\n# Block-scaling mode -> (qk cutlass dtype, sf cutlass dtype, sf_vec_size)\n_BLOCKSCALED_MODES = {\n \"mxfp8\": (cutlass.Float8E4M3FN, cutlass.Float8E8M0FNU, 32),\n \"nvfp4\": (cutlass.Float4E2M1FN, cutlass.Float8E4M3FN, 16),\n}\n\n\ndef _mask_type(is_causal: bool):\n from .helpers import fmha_helpers as fmha_utils\n\n # Bottom-right aligned causal, matching FlashInfer convention.\n return (\n fmha_utils.MaskEnum.WINDOW_MASK_INFERENCE\n if is_causal\n else fmha_utils.MaskEnum.RESIDUAL_MASK\n )\n\n\ndef _ex2_emulation_enabled(device: torch.device) -> bool:\n # ex2 emulation is only beneficial / correct on CC 10.0 (sm_100/sm_100a/sm_100f);\n # not on sm_103 (CC 10.3) or later archs.\n return torch.cuda.get_device_capability(device) == (10, 0)\n\n\n# =============================================================================\n# Non-block-scaled\n# =============================================================================\n\n\n@functools.cache\ndef compile_cute_dsl_fmha_kernel(\n qk_dtype: torch.dtype,\n v_dtype: torch.dtype,\n out_dtype: torch.dtype,\n num_qo_heads: int,\n num_kv_heads: int,\n head_dim: int,\n head_dim_v: int,\n is_causal: bool,\n with_lse: bool,\n enable_sink: bool,\n enable_skip_softmax: bool,\n use_pdl: bool,\n device: torch.device,\n has_window_left: bool = False,\n has_window_right=None,\n):\n \"\"\"Compile (and cache) the trtllm FMHA kernel for a static config.\n\n Compiles with the TVM-FFI ABI (the handle takes ``torch.Tensor`` args on the env\n stream) and symbolic batch/seqlen dims, so a single compile serves all shapes for the\n given dtypes / head counts / head_dim / mask.\n\n Sliding-window bounds follow a presence/value split: only bound *presence*\n (``has_window_left`` / ``has_window_right``) specializes the kernel — the\n DSL traces ``Optional[Int32]`` window args as present-or-None — while the\n bound values are runtime arguments, so one compile serves every window\n size. ``has_window_right=None`` derives presence from ``is_causal``\n (causal is a right bound with runtime value 0).\n \"\"\"\n from .fmha import BlackwellFusedMultiHeadAttentionForward\n\n if has_window_right is None:\n has_window_right = is_causal\n enable_ex2_emulation = _ex2_emulation_enabled(device)\n qk = _CUTLASS_DTYPE[qk_dtype]\n pv = _CUTLASS_DTYPE[v_dtype]\n out = _CUTLASS_DTYPE[out_dtype]\n d = head_dim\n dv = head_dim_v\n head_dim_arg = d if d == dv else (d, dv)\n\n fmha = BlackwellFusedMultiHeadAttentionForward(\n qk_acc_dtype=cutlass.Float32,\n pv_acc_dtype=cutlass.Float32,\n mma_tiler=(128, 128),\n head_dim=head_dim_arg,\n is_persistent=False, # varlen ragged\n # Any band bound (causal or sliding window) uses the window mask.\n mask_type=_mask_type(has_window_left or has_window_right),\n enable_ex2_emulation=enable_ex2_emulation,\n enable_skip_correction=True,\n # Rescale threshold compresses the dynamic range when quantizing P and interferes\n # skip-softmax criteria. Limit rescale threshold to a small epsilon (0.0 disables\n # skip-correction) when skip-softmax is enabled, or P becomes the main source of\n # quantization error (P, in v_dtype, being narrower than qk_dtype).\n rescale_threshold=2**-8 if enable_skip_softmax or pv.width < qk.width else 8.0,\n use_tma_store=False, # varlen -> STG\n )\n\n sym_b = cute.sym_int()\n sym_s_q = cute.sym_int()\n sym_s_k = cute.sym_int()\n sym_hk = cute.sym_int()\n sym_hr = cute.sym_int()\n sym_seq = cute.sym_int()\n q_fake = make_fake_compact_tensor(\n qk,\n (sym_b, sym_s_q, sym_hk, sym_hr, d),\n stride_order=(4, 3, 2, 1, 0),\n assumed_align=16,\n )\n k_fake = make_fake_compact_tensor(\n qk,\n (sym_b, sym_s_k, sym_hk, 1, d),\n stride_order=(4, 3, 2, 1, 0),\n assumed_align=16,\n )\n v_fake = make_fake_compact_tensor(\n pv,\n (sym_b, sym_s_k, sym_hk, 1, dv),\n stride_order=(4, 3, 2, 1, 0),\n assumed_align=16,\n )\n o_fake = make_fake_compact_tensor(\n out,\n (sym_b, sym_s_q, sym_hk, sym_hr, dv),\n stride_order=(4, 3, 2, 1, 0),\n assumed_align=32,\n )\n lse_fake = (\n make_fake_compact_tensor(\n cutlass.Float32,\n (sym_b, sym_s_q, sym_hk, sym_hr),\n stride_order=(3, 2, 1, 0),\n assumed_align=16,\n )\n if with_lse\n else None\n )\n sink_fake = (\n make_fake_compact_tensor(\n cutlass.Float32, (cute.sym_int(),), stride_order=(0,), assumed_align=16\n )\n if enable_sink\n else None\n )\n cum_q_fake = make_fake_compact_tensor(Int32, (sym_seq,), assumed_align=16)\n cum_k_fake = make_fake_compact_tensor(Int32, (sym_seq,), assumed_align=16)\n\n problem_size = (1, 1, 1, 1, num_qo_heads, num_kv_heads, d, dv)\n scale_softmax = 1.0 / math.sqrt(d)\n skip_threshold_log2 = Float32(0.0) if enable_skip_softmax else None\n # Trace-time presence only; the traced 0s are placeholders and the real\n # bound values arrive as runtime arguments on each call.\n ws_left = Int32(0) if has_window_left else None\n ws_right = Int32(0) if has_window_right else None\n stream_fake = make_fake_stream(use_tvm_ffi_env_stream=True)\n\n return cute.compile(\n fmha,\n q_fake,\n k_fake,\n v_fake,\n o_fake,\n problem_size,\n cum_q_fake,\n cum_k_fake,\n lse_fake,\n sink_fake,\n scale_softmax * math.log2(math.e),\n scale_softmax,\n 1.0,\n skip_threshold_log2,\n ws_left,\n ws_right,\n None,\n None,\n stream_fake,\n use_pdl,\n None,\n None,\n None,\n None,\n None,\n options=\"--enable-tvm-ffi --opt-level 2\",\n )\n\n\n# =============================================================================\n# Block-scaled (MXFP8 / NVFP4)\n# =============================================================================\n\n\n@functools.cache\ndef compile_cute_dsl_fmha_blockscaled_kernel(\n qk_mode: str,\n v_dtype: torch.dtype,\n out_dtype: torch.dtype,\n num_qo_heads: int,\n num_kv_heads: int,\n head_dim: int,\n is_causal: bool,\n with_lse: bool,\n enable_skip_softmax: bool,\n use_pdl: bool,\n device: torch.device,\n has_window_left: bool = False,\n has_window_right=None,\n):\n \"\"\"Compile (and cache) the trtllm block-scaled FMHA kernel (batched, non-varlen).\"\"\"\n from .fmha_blockscaled import BlackwellFusedMultiHeadBlockScaledAttentionForward\n\n if has_window_right is None:\n has_window_right = is_causal\n enable_ex2_emulation = _ex2_emulation_enabled(device)\n qk, sf_dt, sf_vec = _BLOCKSCALED_MODES[qk_mode]\n pv = _CUTLASS_DTYPE[v_dtype]\n out = _CUTLASS_DTYPE[out_dtype]\n d = dv = head_dim\n\n fmha = BlackwellFusedMultiHeadBlockScaledAttentionForward(\n qk_acc_dtype=cutlass.Float32,\n pv_acc_dtype=cutlass.Float32,\n mma_tiler=(128, 128),\n head_dim=d,\n is_persistent=False,\n mask_type=_mask_type(has_window_left or has_window_right),\n enable_ex2_emulation=enable_ex2_emulation,\n enable_skip_correction=True,\n qk_sf_vec_size=sf_vec,\n # Rescale threshold compresses the dynamic range when quantizing P and interferes\n # skip-softmax criteria. Limit rescale threshold to a small epsilon (0.0 disables\n # skip-correction) when either is enabled.\n rescale_threshold=2**-8 if enable_skip_softmax or pv.width <= 8 else 8.0,\n use_tma_store=True, # non-varlen\n )\n\n sym_b = cute.sym_int()\n sym_s_q = cute.sym_int()\n sym_s_k = cute.sym_int()\n sym_hk = cute.sym_int()\n sym_hr = cute.sym_int()\n # Sub-byte (fp4) stride-1 dim must be static.\n sym_d = d if qk.width < 8 else cute.sym_int()\n sym_dv = dv if qk.width < 8 else cute.sym_int()\n q_fake = make_fake_compact_tensor(\n qk,\n (sym_b, sym_s_q, sym_hk, sym_hr, sym_d),\n stride_order=(4, 3, 2, 1, 0),\n assumed_align=16,\n )\n k_fake = make_fake_compact_tensor(\n qk,\n (sym_b, sym_s_k, sym_hk, 1, sym_d),\n stride_order=(4, 3, 2, 1, 0),\n assumed_align=16,\n )\n v_fake = make_fake_compact_tensor(\n pv,\n (sym_b, sym_s_k, sym_hk, 1, sym_dv),\n stride_order=(4, 3, 2, 1, 0),\n assumed_align=16,\n )\n o_fake = make_fake_compact_tensor(\n out,\n (sym_b, sym_s_q, sym_hk, sym_hr, sym_dv),\n stride_order=(4, 3, 2, 1, 0),\n assumed_align=32,\n )\n # The fused quantizer produces the same contiguous 128x4-swizzled storage.\n # Expose it through the compiler's 6D ABI: (L, M/128, SF_K/4, 32, 4, 4).\n sym_sf_k_tiles = cute.sym_int()\n q_sf_fake = make_fake_compact_tensor(\n sf_dt,\n (cute.sym_int(), cute.sym_int(), sym_sf_k_tiles, 32, 4, 4),\n stride_order=(5, 4, 3, 2, 1, 0),\n assumed_align=16,\n )\n k_sf_fake = make_fake_compact_tensor(\n sf_dt,\n (cute.sym_int(), cute.sym_int(), sym_sf_k_tiles, 32, 4, 4),\n stride_order=(5, 4, 3, 2, 1, 0),\n assumed_align=16,\n )\n lse_fake = (\n make_fake_compact_tensor(\n cutlass.Float32,\n (sym_b, sym_s_q, sym_hk, sym_hr),\n stride_order=(3, 2, 1, 0),\n assumed_align=16,\n )\n if with_lse\n else None\n )\n\n problem_size = (1, 1, 1, 1, num_qo_heads, num_kv_heads, d, dv)\n scale_softmax = 1.0 / math.sqrt(d)\n skip_threshold_log2 = Float32(0.0) if enable_skip_softmax else None\n ws_left = Int32(0) if has_window_left else None\n ws_right = Int32(0) if has_window_right else None\n stream_fake = make_fake_stream(use_tvm_ffi_env_stream=True)\n\n return cute.compile(\n fmha,\n q_fake,\n k_fake,\n q_sf_fake,\n k_sf_fake,\n v_fake,\n o_fake,\n problem_size,\n None, # cum_seqlen_q (non-varlen)\n None, # cum_seqlen_k\n lse_fake,\n None, # sink\n scale_softmax * math.log2(math.e),\n scale_softmax,\n 1.0,\n None, # scale_v_channels\n skip_threshold_log2,\n ws_left,\n ws_right,\n None,\n None,\n stream_fake,\n use_pdl,\n options=\"--enable-tvm-ffi --opt-level 2\",\n )\n"},"diff":{"kind":"string","value":"--- flashinfer/cute_dsl/attention/fmha/compile.py\n+++ flashinfer/cute_dsl/attention/fmha/compile.py\n@@ -117,6 +117,11 @@\n mask_type=_mask_type(has_window_left or has_window_right),\n enable_ex2_emulation=enable_ex2_emulation,\n enable_skip_correction=True,\n+ # Rescale threshold compresses the dynamic range when quantizing P and interferes\n+ # skip-softmax criteria. Limit rescale threshold to a small epsilon (0.0 disables\n+ # skip-correction) when skip-softmax is enabled, or P becomes the main source of\n+ # quantization error (P, in v_dtype, being narrower than qk_dtype).\n+ rescale_threshold=2**-8 if enable_skip_softmax or pv.width < qk.width else 8.0,\n use_tma_store=False, # varlen -> STG\n )\n \n@@ -200,6 +205,11 @@\n None,\n stream_fake,\n use_pdl,\n+ None,\n+ None,\n+ None,\n+ None,\n+ None,\n options=\"--enable-tvm-ffi --opt-level 2\",\n )\n \n@@ -212,7 +222,7 @@\n @functools.cache\n def compile_cute_dsl_fmha_blockscaled_kernel(\n qk_mode: str,\n- pv_dtype: torch.dtype,\n+ v_dtype: torch.dtype,\n out_dtype: torch.dtype,\n num_qo_heads: int,\n num_kv_heads: int,\n@@ -232,7 +242,7 @@\n has_window_right = is_causal\n enable_ex2_emulation = _ex2_emulation_enabled(device)\n qk, sf_dt, sf_vec = _BLOCKSCALED_MODES[qk_mode]\n- pv = _CUTLASS_DTYPE[pv_dtype]\n+ pv = _CUTLASS_DTYPE[v_dtype]\n out = _CUTLASS_DTYPE[out_dtype]\n d = dv = head_dim\n \n@@ -246,6 +256,10 @@\n enable_ex2_emulation=enable_ex2_emulation,\n enable_skip_correction=True,\n qk_sf_vec_size=sf_vec,\n+ # Rescale threshold compresses the dynamic range when quantizing P and interferes\n+ # skip-softmax criteria. Limit rescale threshold to a small epsilon (0.0 disables\n+ # skip-correction) when either is enabled.\n+ rescale_threshold=2**-8 if enable_skip_softmax or pv.width <= 8 else 8.0,\n use_tma_store=True, # non-varlen\n )\n "},"lines_added":{"kind":"number","value":16,"string":"16"},"lines_removed":{"kind":"number","value":2,"string":"2"},"files_in_commit":{"kind":"number","value":5,"string":"5"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["B300","BLACKWELL","CPU"],"string":"[\n \"B300\",\n \"BLACKWELL\",\n \"CPU\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":["1.0675x","1.0552x","1.0737x","1.0751x","1.0364x","0.9955x","1.0022x","0.9523x","1.0123x","1.0809x"],"string":"[\n \"1.0675x\",\n \"1.0552x\",\n \"1.0737x\",\n \"1.0751x\",\n \"1.0364x\",\n \"0.9955x\",\n \"1.0022x\",\n \"0.9523x\",\n \"1.0123x\",\n \"1.0809x\"\n]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cute_dsl kernel file from flashinfer (flashinfer/cute_dsl/attention/fmha/compile.py).\n\nGoal: perf(attention): Refresh DSL_FMHA cubins\nTarget hardware: B300, BLACKWELL, CPU\nTarget models: unspecified\n\nCurrent file:\n```python\n# SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.\n# SPDX-License-Identifier: Apache-2.0\n#\n# Licensed under the Apache License, Version 2.0 (the \"License\");\n# you may not use this file except in compliance with the License.\n# You may obtain a copy of the License at\n#\n# http://www.apache.org/licenses/LICENSE-2.0\n#\n# Unless required by applicable law or agreed to in writing, software\n# distributed under the License is distributed on an \"AS IS\" BASIS,\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n# See the License for the specific language governing permissions and\n# limitations under the License.\n\"\"\"JIT-compilers for the trtllm CuTe DSL FMHA kernels.\n\n``compile_cute_dsl_fmha_kernel`` / ``compile_cute_dsl_fmha_blockscaled_kernel``\n``cute.compile`` (and cache) the trtllm ``BlackwellFusedMultiHead[BlockScaled]AttentionForward``\nclasses with symbolic batch/seqlen dims, returning a TVM-FFI-callable kernel handle.\n\"\"\"\n\nimport functools\nimport math\n\nimport cutlass\nimport cutlass.cute as cute\nimport torch\nfrom cutlass.cute.runtime import make_fake_compact_tensor, make_fake_stream\nfrom cutlass.cute.typing import Float32, Int32\n\n# torch dtype -> cutlass dtype\n_CUTLASS_DTYPE = {\n torch.float16: cutlass.Float16,\n torch.bfloat16: cutlass.BFloat16,\n torch.float8_e4m3fn: cutlass.Float8E4M3FN,\n}\n\n# Block-scaling mode -> (qk cutlass dtype, sf cutlass dtype, sf_vec_size)\n_BLOCKSCALED_MODES = {\n \"mxfp8\": (cutlass.Float8E4M3FN, cutlass.Float8E8M0FNU, 32),\n \"nvfp4\": (cutlass.Float4E2M1FN, cutlass.Float8E4M3FN, 16),\n}\n\n\ndef _mask_type(is_causal: bool):\n from .helpers import fmha_helpers as fmha_utils\n\n # Bottom-right aligned causal, matching FlashInfer convention.\n return (\n fmha_utils.MaskEnum.WINDOW_MASK_INFERENCE\n if is_causal\n else fmha_utils.MaskEnum.RESIDUAL_MASK\n )\n\n\ndef _ex2_emulation_enabled(device: torch.device) -> bool:\n # ex2 emulation is only beneficial / correct on CC 10.0 (sm_100/sm_100a/sm_100f);\n # not on sm_103 (CC 10.3) or later archs.\n return torch.cuda.get_device_capability(device) == (10, 0)\n\n\n# =============================================================================\n# Non-block-scaled\n# =============================================================================\n\n\n@functools.cache\ndef compile_cute_dsl_fmha_kernel(\n qk_dtype: torch.dtype,\n v_dtype: torch.dtype,\n out_dtype: torch.dtype,\n num_qo_heads: int,\n num_kv_heads: int,\n head_dim: int,\n head_dim_v: int,\n is_causal: bool,\n with_lse: bool,\n enable_sink: bool,\n enable_skip_softmax: bool,\n use_pdl: bool,\n device: torch.device,\n has_window_left: bool = False,\n has_window_right=None,\n):\n \"\"\"Compile (and cache) the trtllm FMHA kernel for a static config.\n\n Compiles with the TVM-FFI ABI (the handle takes ``torch.Tensor`` args on the env\n stream) and symbolic batch/seqlen dims, so a single compile serves all shapes for the\n given dtypes / head counts / head_dim / mask.\n\n Sliding-window bounds follow a presence/value split: only bound *presence*\n (``has_window_left`` / ``has_window_right``) specializes the kernel — the\n DSL traces ``Optional[Int32]`` window args as present-or-None — while the\n bound values are runtime arguments, so one compile serves every window\n size. ``has_window_right=None`` derives presence from ``is_causal``\n (causal is a right bound with runtime value 0).\n \"\"\"\n from .fmha import BlackwellFusedMultiHeadAttentionForward\n\n if has_window_right is None:\n has_window_right = is_causal\n enable_ex2_emulation = _ex2_emulation_enabled(device)\n qk = _CUTLASS_DTYPE[qk_dtype]\n pv = _CUTLASS_DTYPE[v_dtype]\n out = _CUTLASS_DTYPE[out_dtype]\n d = head_dim\n dv = head_dim_v\n head_dim_arg = d if d == dv else (d, dv)\n\n fmha = BlackwellFusedMultiHeadAttentionForward(\n qk_acc_dtype=cutlass.Float32,\n pv_acc_dtype=cutlass.Float32,\n mma_tiler=(128, 128),\n head_dim=head_dim_arg,\n is_persistent=False, # varlen ragged\n # Any band bound (causal or sliding window) uses the window mask.\n mask_type=_mask_type(has_window_left or has_window_right),\n enable_ex2_emulation=enable_ex2_emulation,\n enable_skip_correction=True,\n use_tma_store=False, # varlen -> STG\n )\n\n sym_b = cute.sym_int()\n sym_s_q = cute.sym_int()\n sym_s_k = cute.sym_int()\n sym_hk = cute.sym_int()\n sym_hr = cute.sym_int()\n sym_seq = cute.sym_int()\n q_fake = make_fake_compact_tensor(\n qk,\n (sym_b, sym_s_q, sym_hk, sym_hr, d),\n stride_order=(4, 3, 2, 1, 0),\n assumed_align=16,\n )\n k_fake = make_fake_compact_tensor(\n qk,\n (sym_b, sym_s_k, sym_hk, 1, d),\n stride_order=(4, 3, 2, 1, 0),\n assumed_align=16,\n )\n v_fake = make_fake_compact_tensor(\n pv,\n (sym_b, sym_s_k, sym_hk, 1, dv),\n stride_order=(4, 3, 2, 1, 0),\n assumed_align=16,\n )\n o_fake = make_fake_compact_tensor(\n out,\n (sym_b, sym_s_q, sym_hk, sym_hr, dv),\n stride_order=(4, 3, 2, 1, 0),\n assumed_align=32,\n )\n lse_fake = (\n make_fake_compact_tensor(\n cutlass.Float32,\n (sym_b, sym_s_q, sym_hk, sym_hr),\n stride_order=(3, 2, 1, 0),\n assumed_align=16,\n )\n if with_lse\n else None\n )\n sink_fake = (\n make_fake_compact_tensor(\n cutlass.Float32, (cute.sym_int(),), stride_order=(0,), assumed_align=16\n )\n if enable_sink\n else None\n )\n cum_q_fake = make_fake_compact_tensor(Int32, (sym_seq,), assumed_align=16)\n cum_k_fake = make_fake_compact_tensor(Int32, (sym_seq,), assumed_align=16)\n\n problem_size = (1, 1, 1, 1, num_qo_heads, num_kv_heads, d, dv)\n scale_softmax = 1.0 / math.sqrt(d)\n skip_threshold_log2 = Float32(0.0) if enable_skip_softmax else None\n # Trace-time presence only; the traced 0s are placeholders and the real\n # bound values arrive as runtime arguments on each call.\n ws_left = Int32(0) if has_window_left else None\n ws_right = Int32(0) if has_window_right else None\n stream_fake = make_fake_stream(use_tvm_ffi_env_stream=True)\n\n return cute.compile(\n fmha,\n q_fake,\n k_fake,\n v_fake,\n o_fake,\n problem_size,\n cum_q_fake,\n cum_k_fake,\n lse_fake,\n sink_fake,\n scale_softmax * math.log2(math.e),\n scale_softmax,\n 1.0,\n skip_threshold_log2,\n ws_left,\n ws_right,\n None,\n None,\n stream_fake,\n use_pdl,\n options=\"--enable-tvm-ffi --opt-level 2\",\n )\n\n\n# =============================================================================\n# Block-scaled (MXFP8 / NVFP4)\n# =============================================================================\n\n\n@functools.cache\ndef compile_cute_dsl_fmha_blockscaled_kernel(\n qk_mode: str,\n pv_dtype: torch.dtype,\n out_dtype: torch.dtype,\n num_qo_heads: int,\n num_kv_heads: int,\n head_dim: int,\n is_causal: bool,\n with_lse: bool,\n enable_skip_softmax: bool,\n use_pdl: bool,\n device: torch.device,\n has_window_left: bool = False,\n has_window_right=None,\n):\n \"\"\"Compile (and cache) the trtllm block-scaled FMHA kernel (batched, non-varlen).\"\"\"\n from .fmha_blockscaled import BlackwellFusedMultiHeadBlockScaledAttentionForward\n\n if has_window_right is None:\n has_window_right = is_causal\n enable_ex2_emulation = _ex2_emulation_enabled(device)\n qk, sf_dt, sf_vec = _BLOCKSCALED_MODES[qk_mode]\n pv = _CUTLASS_DTYPE[pv_dtype]\n out = _CUTLASS_DTYPE[out_dtype]\n d = dv = head_dim\n\n fmha = BlackwellFusedMultiHeadBlockScaledAttentionForward(\n qk_acc_dtype=cutlass.Float32,\n pv_acc_dtype=cutlass.Float32,\n mma_tiler=(128, 128),\n head_dim=d,\n is_persistent=False,\n mask_type=_mask_type(has_window_left or has_window_right),\n enable_ex2_emulation=enable_ex2_emulation,\n enable_skip_correction=True,\n qk_sf_vec_size=sf_vec,\n use_tma_store=True, # non-varlen\n )\n\n sym_b = cute.sym_int()\n sym_s_q = cute.sym_int()\n sym_s_k = cute.sym_int()\n sym_hk = cute.sym_int()\n sym_hr = cute.sym_int()\n # Sub-byte (fp4) stride-1 dim must be static.\n sym_d = d if qk.width < 8 else cute.sym_int()\n sym_dv = dv if qk.width < 8 else cute.sym_int()\n q_fake = make_fake_compact_tensor(\n qk,\n (sym_b, sym_s_q, sym_hk, sym_hr, sym_d),\n stride_order=(4, 3, 2, 1, 0),\n assumed_align=16,\n )\n k_fake = make_fake_compact_tensor(\n qk,\n (sym_b, sym_s_k, sym_hk, 1, sym_d),\n stride_order=(4, 3, 2, 1, 0),\n assumed_align=16,\n )\n v_fake = make_fake_compact_tensor(\n pv,\n (sym_b, sym_s_k, sym_hk, 1, sym_dv),\n stride_order=(4, 3, 2, 1, 0),\n assumed_align=16,\n )\n o_fake = make_fake_compact_tensor(\n out,\n (sym_b, sym_s_q, sym_hk, sym_hr, sym_dv),\n stride_order=(4, 3, 2, 1, 0),\n assumed_align=32,\n )\n # The fused quantizer produces the same contiguous 128x4-swizzled storage.\n # Expose it through the compiler's 6D ABI: (L, M/128, SF_K/4, 32, 4, 4).\n sym_sf_k_tiles = cute.sym_int()\n q_sf_fake = make_fake_compact_tensor(\n sf_dt,\n (cute.sym_int(), cute.sym_int(), sym_sf_k_tiles, 32, 4, 4),\n stride_order=(5, 4, 3, 2, 1, 0),\n assumed_align=16,\n )\n k_sf_fake = make_fake_compact_tensor(\n sf_dt,\n (cute.sym_int(), cute.sym_int(), sym_sf_k_tiles, 32, 4, 4),\n stride_order=(5, 4, 3, 2, 1, 0),\n assumed_align=16,\n )\n lse_fake = (\n make_fake_compact_tensor(\n cutlass.Float32,\n (sym_b, sym_s_q, sym_hk, sym_hr),\n stride_order=(3, 2, 1, 0),\n assumed_align=16,\n )\n if with_lse\n else None\n )\n\n problem_size = (1, 1, 1, 1, num_qo_heads, num_kv_heads, d, dv)\n scale_softmax = 1.0 / math.sqrt(d)\n skip_threshold_log2 = Float32(0.0) if enable_skip_softmax else None\n ws_left = Int32(0) if has_window_left else None\n ws_right = Int32(0) if has_window_right else None\n stream_fake = make_fake_stream(use_tvm_ffi_env_stream=True)\n\n return cute.compile(\n fmha,\n q_fake,\n k_fake,\n q_sf_fake,\n k_sf_fake,\n v_fake,\n o_fake,\n problem_size,\n None, # cum_seqlen_q (non-varlen)\n None, # cum_seqlen_k\n lse_fake,\n None, # sink\n scale_softmax * math.log2(math.e),\n scale_softmax,\n 1.0,\n None, # scale_v_channels\n skip_threshold_log2,\n ws_left,\n ws_right,\n None,\n None,\n stream_fake,\n use_pdl,\n options=\"--enable-tvm-ffi --opt-level 2\",\n )\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\n<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->\n\n+ Refresh DSL_FMHA cubins\n+ Minimal change to source code to keep backward compatibility (unlike cubin builder, FlashInfer needs to ensure JIT source compatibility with multiple `nvidia-cutlass-dsl` versions).\n\n### Performance on B300\n\nBase shape: B=2, H=16, D=128 data:\n- Internal compiler scheduling decision might have caused regression in some shapes, but overall there is a consistent latency improvement over the Blackwell Ultra horizon:\n\n| S | Causal | QK/V | `main` median (ms) | Refresh median (ms) | Refresh latency delta | Refresh speedup |\n|---:|:------:|:------|-------------------:|--------------------:|----------------------:|----------------:|\n| 2048 | True | BF16/BF16 | 0.064800 | 0.060704 | -6.32% | 1.0675x |\n| 2048 | True | BF16/FP8 | 0.059040 | 0.055952 | -5.23% | 1.0552x |\n| 2048 | True | FP8/FP8 | 0.053393 | 0.049728 | -6.86% | 1.0737x |\n| 2048 | False | BF16/BF16 | 0.070321 | 0.065408 | -6.99% | 1.0751x |\n| 2048 | False | BF16/FP8 | 0.061056 | 0.058912 | -3.51% | 1.0364x |\n| 2048 | False | FP8/FP8 | 0.049504 | 0.049729 | +0.45% | 0.9955x |\n| 16384 | True | BF16/BF16 | 1.386919 | 1.383943 | -0.21% | 1.0022x |\n| 16384 | True | BF16/FP8 | 1.114918 | 1.170806 | +5.01% | 0.9523x |\n| 16384 | True | FP8/FP8 | 1.050949 | 1.038149 | -1.22% | 1.0123x |\n| 16384 | False | BF16/BF16 | 2.621342 | 2.425229 | -7.48% | 1.0809x |\n| 16384 | False | BF16/FP8 | 2.146891 | 2.001659 | -6.76% | 1.0726x |\n| 16384 | False | FP8/FP8 | 1.764121 | 1.729594 | -1.96% | 1.0200x |\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\nN/A\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n## 🔬 Experimental Track\n\n<!-- Only for PRs submitted under the experimental policy (CONTRIBUTING.md → \"Experimental APIs and Backends\").\n Leave this section untouched for normal PRs. -->\n\n- [ ] This PR is **experimental**: it adds or changes code under `flashinfer/experimental/` and/or an `@flashinfer_experimental_api`. Tracking issue: #\n - [ ] The tracking issue names an owner, the reason for the experimental path, and a graduation plan with a target release.\n - [ ] Core changes are limited to a thin entry point (signature, shared validation, feature-gate check, backend selection, handoff).\n - [ ] Tests live in `tests/experimental/` and were validated on the intended hardware; a runnable example is included.\n - [ ] Nothing is registered in `flashinfer/aot.py`, and no experimental backend is reachable from `backend=\"auto\"` without `FLASHINFER_ALLOW_EXPERIMENTAL_AUTO_BACKENDS=1`. (Calling an `@flashinfer_experimental_api` or naming a backend explicitly is itself the opt-in and needs no environment variable.)\n - [ ] **Test scope declared below.** The experimental CI lane runs exactly these targets, so keep them as narrow as the change allows.\n\n<!-- Required for experimental PRs. Replace the commented lines below with your targets.\n Do not delete the fence or change its `experimental-tests` tag — the experimental-track\n watcher reads it verbatim to decide which targets to ask CI for. -->\n\n```experimental-tests\n# One target per line: a directory or a file. (A pytest ::selector is not\n# supported -- the sharding runner cannot consume one.) Must be under\n# tests/experimental/ and must exist. Delete these comment lines and add yours, e.g.\n#\n# tests/experimental/test_my_backend.py\n# tests/experimental/my_backend/\n#\n# Declaring the whole tree (tests/experimental/) is allowed but means every\n# experimental PR pays for every other feature's tests, in every matrix cell.\n```\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc. -->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n- **Bug Fixes**\n - Updated the CuTe DSL fused multi-head attention backend for compatibility with the latest kernel interface.\n - Improved softmax-scaling behavior for skip-softmax and low-precision attention modes.\n - Added configurable rescaling thresholds for standard and block-scaled attention paths.\n - Refreshed backend artifacts and checksums across supported GPU and CPU architectures.\n- **Documentation**\n - Clarified CuTe DSL attention backend coverage, including ALiBi and modular prefill behavior.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": \"B300\", \"model\": null, \"shape\": \"S=2048\", \"batch_size\": 2, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.0648, \"optimized\": 0.060704, \"stated_speedup\": 1.0675, \"speedup\": 1.0675}, {\"scope\": \"kernel\", \"hardware\": \"B300\", \"model\": null, \"shape\": \"S=2048\", \"batch_size\": 2, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.05904, \"optimized\": 0.055952, \"stated_speedup\": 1.0552, \"speedup\": 1.0552}, {\"scope\": \"kernel\", \"hardware\": \"B300\", \"model\": null, \"shape\": \"S=2048\", \"batch_size\": 2, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.053393, \"optimized\": 0.049728, \"stated_speedup\": 1.0737, \"speedup\": 1.0737}, {\"scope\": \"kernel\", \"hardware\": \"B300\", \"model\": null, \"shape\": \"S=2048\", \"batch_size\": 2, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.070321, \"optimized\": 0.065408, \"stated_speedup\": 1.0751, \"speedup\": 1.0751}, {\"scope\": \"kernel\", \"hardware\": \"B300\", \"model\": null, \"shape\": \"S=2048\", \"batch_size\": 2, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.061056, \"optimized\": 0.058912, \"stated_speedup\": 1.0364, \"speedup\": 1.0364}, {\"scope\": \"kernel\", \"hardware\": \"B300\", \"model\": null, \"shape\": \"S=2048\", \"batch_size\": 2, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.049504, \"optimized\": 0.049729, \"stated_speedup\": 0.9955, \"speedup\": 0.9955}, {\"scope\": \"kernel\", \"hardware\": \"B300\", \"model\": null, \"shape\": \"S=16384\", \"batch_size\": 2, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.386919, \"optimized\": 1.383943, \"stated_speedup\": 1.0022, \"speedup\": 1.0022}, {\"scope\": \"kernel\", \"hardware\": \"B300\", \"model\": null, \"shape\": \"S=16384\", \"batch_size\": 2, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.114918, \"optimized\": 1.170806, \"stated_speedup\": 0.9523, \"speedup\": 0.9523}, {\"scope\": \"kernel\", \"hardware\": \"B300\", \"model\": null, \"shape\": \"S=16384\", \"batch_size\": 2, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.050949, \"optimized\": 1.038149, \"stated_speedup\": 1.0123, \"speedup\": 1.0123}, {\"scope\": \"kernel\", \"hardware\": \"B300\", \"model\": null, \"shape\": \"S=16384\", \"batch_size\": 2, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 2.621342, \"optimized\": 2.425229, \"stated_speedup\": 1.0809, \"speedup\": 1.0809}, {\"scope\": \"kernel\", \"hardware\": \"B300\", \"model\": null, \"shape\": \"S=16384\", \"batch_size\": 2, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 2.146891, \"optimized\": 2.001659, \"stated_speedup\": 1.0726, \"speedup\": 1.0726}, {\"scope\": \"kernel\", \"hardware\": \"B300\", \"model\": null, \"shape\": \"S=16384\", \"batch_size\": 2, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.764121, \"optimized\": 1.729594, \"stated_speedup\": 1.02, \"speedup\": 1.02}]"},"kernel_speedup":{"kind":"number","value":1.0458,"string":"1.0458"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1063,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"af9b148e9133880154e33dc22205403b8b9698e6"},"date":{"kind":"string","value":"2026-09-08T17:44:35+02:00"},"pr_number":{"kind":"number","value":4067,"string":"4,067"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/4067"},"title":{"kind":"string","value":"perf(moe): phase NVFP4 dispatch payload copies at EP4/EP8/EP16 (#4067)"},"message":{"kind":"string","value":"perf(moe): phase NVFP4 dispatch payload copies at EP4/EP8/EP16 (#4067)\n\n## Summary\n\nFollow-up to #3846. The generic dispatch kernel makes every CTA thread\nbuild remote destination pointers for every payload before determining\nwhether that thread owns any bytes. NVFP4 has four predictably\nasymmetric payloads, so this change gives each payload only the workers\nit needs:\n\n- two warps for packed activations;\n- the required lanes of one warp for scales;\n- two lane groups in the final warp for expert IDs and routing weights.\n\nEP4 retains its compact per-rank destination list. EP8 and EP16 retain\nthe existing top-k-sized representation; only their copy schedule\nchanges. The phased path is gated to EP `{4, 8, 16}`, a 128-thread CTA,\nand validated four-payload NVFP4 layouts. Unsupported EP sizes, top-k\nvalues, widths, and payload layouts use the existing generic kernel.\n\nThe H2048/top-k-22 target retains compile-time payload widths. Validated\nsmaller layouts use the same schedule with runtime activation and scale\nwidths.\n\n## Performance\n\n### Single op\n\nGB200, H2048, top-k 22, CUDA graphs. EP8 and EP16 are true global\nexpert-parallel groups spanning two and four nodes.\n\n| Global EP | Nodes | Tokens/rank | Baseline | Candidate | Delta |\n|---:|---:|---:|---:|---:|---:|\n| 4 | 1 | 1 | 13.480 us | 12.862 us | -4.58% |\n| 4 | 1 | 4 | 14.408 us | 13.490 us | -6.37% |\n| 4 | 1 | 64 | 16.511 us | 15.284 us | -7.43% |\n| 4 | 1 | 512 | 18.155 us | 17.804 us | -1.93% |\n| 4 | 1 | 8192 | 55.072 us | 54.689 us | -0.70% |\n| 8 | 2 | 1 | 16.270 us | 13.877 us | -14.71% |\n| 8 | 2 | 4 | 18.394 us | 14.679 us | -20.20% |\n| 8 | 2 | 64 | 21.253 us | 17.358 us | -18.33% |\n| 8 | 2 | 512 | 40.520 us | 27.275 us | -32.69% |\n| 8 | 2 | 1024 | 64.713 us | 37.797 us | -41.59% |\n| 8 | 2 | 8192 | 308.292 us | 96.494 us | -68.70% |\n| 16 | 4 | 1 | 18.107 us | 15.733 us | -13.11% |\n| 16 | 4 | 4 | 21.639 us | 17.328 us | -19.92% |\n| 16 | 4 | 64 | 25.264 us | 20.652 us | -18.26% |\n| 16 | 4 | 512 | 55.275 us | 41.484 us | -24.95% |\n| 16 | 4 | 1024 | 100.321 us | 68.156 us | -32.06% |\n| 16 | 4 | 8192 | 373.115 us | 176.750 us | -52.63% |\n\n### E2e workload\n\nOn the **Nemotron Ultra NVFP4 end-to-end** workload (2 GB200 nodes,\nTP1/DP8/EP8, FlashInfer one-sided, CUDA graphs, ISL/OSL 8192/8,\nconcurrency 8), mean TTFT improves from 860.8 ms to 839.9 ms\n(**-2.43%**, 95% CI [-3.44%, -1.41%]). Throughput (+0.62%) and TPOT are\nstatistically on par.\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n## Summary by CodeRabbit\n\n* **New Features**\n* Added support for additional phased NVFP4 layouts in\nMixture-of-Experts all-to-all dispatch.\n* Added a specialized H2048 phased dispatch path, including top‑k=22\nconfigurations.\n* **Performance**\n* Improved dispatch efficiency by optimizing activation, scale, and\nrouting-metadata movement.\n* **Bug Fixes**\n* Strengthened validation to ensure payload layouts match runtime\nsettings.\n* **Tests**\n* Updated NVFP4 payload generation and expanded phased H2048 coverage\nacross supported configurations.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n\n---------\n\nSigned-off-by: snordmann <snordmann@nvidia.com>"},"path":{"kind":"string","value":"csrc/nv_internal/tensorrt_llm/kernels/communicationKernels/moeAlltoAllKernels.cu"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include <cooperative_groups.h>\n#include <cuda_fp8.h>\n\n#include <cstdint>\n#include <type_traits>\n\n#include \"flashinfer/exception.h\"\n#include \"flashinfer/utils.cuh\"\n#include \"flashinfer/vec_dtypes.cuh\"\n#include \"tensorrt_llm/common/dataType.h\"\n#include \"tensorrt_llm/common/envUtils.h\"\n#include \"tensorrt_llm/kernels/communicationKernels/moeAlltoAllKernels.h\"\n#include \"tensorrt_llm/kernels/quantization_utils.cuh\"\n\nnamespace tensorrt_llm::kernels::moe_alltoall {\n\nusing tensorrt_llm::common::launchWithPdlWhenEnabled;\n\n#define ENABLE_DEBUG_PRINT 0\n#define DISABLE_SYNC_FOR_PROFILING 0\n\nconstexpr int kEp4Size = 4;\nconstexpr int kCompactDispatchMaxPayloadBytes = 1024;\nconstexpr int kCompactDispatchBlockSize = 128;\n\n#ifndef DISABLE_TIMEOUT\n#define DISABLE_TIMEOUT 0\n#endif\n\n// Helper function for ceiling division\ntemplate <typename T>\n__host__ __device__ inline T ceilDiv(T m, T n) {\n return (m + n - 1) / n;\n}\n\n// Macros for concise launch-time specialization\n#define SWITCH_BOOL(flag, NAME, ...) \\\n if (flag) { \\\n constexpr bool NAME = true; \\\n __VA_ARGS__ \\\n } else { \\\n constexpr bool NAME = false; \\\n __VA_ARGS__ \\\n }\n\n#define SWITCH_TOP_K(top_k, TOP_K, ...) \\\n switch (top_k) { \\\n case 22: { \\\n constexpr int TOP_K = 22; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case 18: { \\\n constexpr int TOP_K = 18; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case 16: { \\\n constexpr int TOP_K = 16; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case 14: { \\\n constexpr int TOP_K = 14; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case 12: { \\\n constexpr int TOP_K = 12; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case 10: { \\\n constexpr int TOP_K = 10; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case 8: { \\\n constexpr int TOP_K = 8; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case 6: { \\\n constexpr int TOP_K = 6; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case 4: { \\\n constexpr int TOP_K = 4; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case 2: { \\\n constexpr int TOP_K = 2; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case 1: { \\\n constexpr int TOP_K = 1; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n default: { \\\n FLASHINFER_CHECK(false, \"Unsupported top_k\"); \\\n } \\\n }\n\n#define SWITCH_DTYPE(dtype, TYPE, ...) \\\n switch (dtype) { \\\n case nvinfer1::DataType::kHALF: { \\\n using TYPE = half; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case nvinfer1::DataType::kBF16: { \\\n using TYPE = __nv_bfloat16; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case nvinfer1::DataType::kFLOAT: { \\\n using TYPE = float; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case nvinfer1::DataType::kFP8: { \\\n using TYPE = __nv_fp8_e4m3; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n default: { \\\n FLASHINFER_CHECK(false, \"Unsupported dtype for moe_a2a_combine\"); \\\n } \\\n }\n\n// Quantized combine currently only supports FP16/BF16 inputs.\n#define SWITCH_QUANT_MODE(dtype, quant_mode, QUANT_MODE, ...) \\\n if constexpr (std::is_same_v<dtype, half> || std::is_same_v<dtype, __nv_bfloat16>) { \\\n switch (quant_mode) { \\\n case MoeA2ACombineQuantMode::NONE: { \\\n constexpr auto QUANT_MODE = MoeA2ACombineQuantMode::NONE; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case MoeA2ACombineQuantMode::MXFP8: { \\\n constexpr auto QUANT_MODE = MoeA2ACombineQuantMode::MXFP8; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case MoeA2ACombineQuantMode::NVFP4: { \\\n constexpr auto QUANT_MODE = MoeA2ACombineQuantMode::NVFP4; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case MoeA2ACombineQuantMode::MXFP4: { \\\n constexpr auto QUANT_MODE = MoeA2ACombineQuantMode::MXFP4; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n default: { \\\n FLASHINFER_CHECK(false, \"Unsupported quant_mode for moe_a2a_combine\"); \\\n } \\\n } \\\n } else { \\\n FLASHINFER_CHECK((quant_mode) == MoeA2ACombineQuantMode::NONE, \\\n \"All to All Combine Quantization currently only supports \" \\\n \"FP16/BF16\"); \\\n constexpr auto QUANT_MODE = MoeA2ACombineQuantMode::NONE; \\\n __VA_ARGS__; \\\n }\n\n#define SWITCH_SWIZZLE_MODE(swizzle_mode, SWIZZLE_MODE, ...) \\\n switch (swizzle_mode) { \\\n case MoeA2ACombineSwizzleSFMode::LINEAR: { \\\n constexpr auto SWIZZLE_MODE = MoeA2ACombineSwizzleSFMode::LINEAR; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case MoeA2ACombineSwizzleSFMode::SWIZZLE_128x4: { \\\n constexpr auto SWIZZLE_MODE = MoeA2ACombineSwizzleSFMode::SWIZZLE_128x4; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case MoeA2ACombineSwizzleSFMode::SWIZZLE_8x4: { \\\n constexpr auto SWIZZLE_MODE = MoeA2ACombineSwizzleSFMode::SWIZZLE_8x4; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n default: { \\\n FLASHINFER_CHECK(false, \"Unsupported swizzle_mode for moe_a2a_combine\"); \\\n } \\\n }\n\n#if DISABLE_TIMEOUT\n#define check_timeout(s) false\n#else\n// 300 * 2000 MHz - should be high enough on any GPU but will prevent a hang\n#define check_timeout(s) ((clock64() - (s)) > (300ll * 2000ll * 1000ll * 1000ll))\n#endif\n\n// ============================================================================\n// Helper Functions for Expert-to-Rank Mapping\n// ============================================================================\n\n// Compute which rank owns a given expert using contiguous ceil/floor partitioning.\n// Supports non-divisible distribution when num_experts % ep_size != 0:\n// base = num_experts / ep_size\n// remainder = num_experts % ep_size\n// - Ranks [0, remainder) each own (base + 1) experts.\n// - Ranks [remainder, ep_size) each own base experts.\n//\n// Example A (uniform): 32 experts, 4 ranks -> base=8, remainder=0\n// - Rank 0: experts 0-7, Rank 1: 8-15, Rank 2: 16-23, Rank 3: 24-31\n// Example B (non-divisible): 384 experts, 5 ranks -> base=76, remainder=4\n// - Ranks 0-3: 77 experts each, Rank 4: 76 experts\n//\n// base and remainder are precomputed by the caller once outside the per-token TOP_K loop\n// so the hot path performs at most one integer divide.\n__device__ __forceinline__ int compute_target_rank_id(int expert_id, int base, int remainder) {\n // Fast path for the uniform (num_experts % ep_size == 0) case: identical to the\n // pre-ceil/floor implementation, so existing divisible deployments incur no overhead.\n if (remainder == 0) {\n return expert_id / base;\n }\n int const split = remainder * (base + 1); // boundary expert id\n if (expert_id < split) {\n // Falls inside the (base + 1)-sized prefix block.\n return expert_id / (base + 1);\n }\n // Falls inside the base-sized suffix block.\n return remainder + (expert_id - split) / base;\n}\n\n// Test bit `rank` in a kRankMaskWords-wide little-endian uint64 bitmask.\n// Word 0 covers ranks 0..63, word 1 covers ranks 64..127, etc.\n// `rank >> 6` and `rank & 63` divide / modulo by 64.\n__device__ __forceinline__ bool is_rank_active(uint64_t const* mask, int rank) {\n return (mask[rank >> 6] >> (rank & 63)) & 1ULL;\n}\n\n// ============================================================================\n// Helper Functions for Vectorized Memory Operations\n// ============================================================================\n\ntemplate <int VEC_SIZE>\n__device__ void vectorized_copy_impl(void* dst, void const* src, int size) {\n using flashinfer::vec_t;\n\n uint8_t* dst_ptr = static_cast<uint8_t*>(dst);\n uint8_t const* src_ptr = static_cast<uint8_t const*>(src);\n\n int const stride = blockDim.x * VEC_SIZE;\n\n for (int offset = threadIdx.x * VEC_SIZE; offset < size; offset += stride) {\n vec_t<uint8_t, VEC_SIZE> v;\n v.load(src_ptr + offset);\n v.store(dst_ptr + offset);\n }\n}\n\n__device__ void vectorized_copy(void* dst, void const* src, int size) {\n if (size % 16 == 0) {\n vectorized_copy_impl<16>(dst, src, size);\n } else if (size % 8 == 0) {\n vectorized_copy_impl<8>(dst, src, size);\n } else if (size % 4 == 0) {\n vectorized_copy_impl<4>(dst, src, size);\n } else if (size % 2 == 0) {\n vectorized_copy_impl<2>(dst, src, size);\n } else {\n vectorized_copy_impl<1>(dst, src, size);\n }\n}\n\n// Vectorized dispatch: load one vec from source and write to up to TOP_K destinations\ntemplate <int VEC_SIZE, int TOP_K>\n__device__ void vectorized_dispatch_impl(uint8_t const* src_ptr, int bytes_per_token, int rank_id,\n int max_tokens_per_rank, int payload_idx,\n DispatchKernelPointers const& ptrs,\n int const* topk_target_ranks,\n int const* topk_send_indices) {\n using flashinfer::vec_t;\n\n // Precompute destination base pointers per k\n uint8_t* dst_base_k[TOP_K];\n#pragma unroll\n for (int k = 0; k < TOP_K; ++k) {\n int dst_idx_k = topk_send_indices[k];\n int target_rank_k = topk_target_ranks[k];\n if (dst_idx_k < 0) {\n dst_base_k[k] = nullptr;\n continue;\n }\n uint8_t* dst_data = static_cast<uint8_t*>(ptrs.recv_buffers[target_rank_k][payload_idx]);\n size_t base_source_rank =\n static_cast<size_t>(rank_id) * static_cast<size_t>(max_tokens_per_rank) +\n static_cast<size_t>(dst_idx_k);\n size_t base_token = base_source_rank * static_cast<size_t>(bytes_per_token);\n dst_base_k[k] = dst_data + base_token;\n }\n\n // TODO: process all payloads. index could be reused.\n int const stride = blockDim.x * VEC_SIZE;\n for (int offset = threadIdx.x * VEC_SIZE; offset < bytes_per_token; offset += stride) {\n vec_t<uint8_t, VEC_SIZE> v;\n v.load(src_ptr + offset);\n\n#pragma unroll\n for (int k = 0; k < TOP_K; ++k) {\n uint8_t* dst_base = dst_base_k[k];\n if (dst_base == nullptr) {\n continue;\n }\n v.store(dst_base + offset);\n }\n }\n}\n\ntemplate <int TOP_K>\n__device__ void vectorized_dispatch(uint8_t const* src_ptr, int bytes_per_token, int rank_id,\n int max_tokens_per_rank, int payload_idx,\n DispatchKernelPointers const& ptrs,\n int const* topk_target_ranks, int const* topk_send_indices) {\n if (bytes_per_token % 16 == 0) {\n vectorized_dispatch_impl<16, TOP_K>(src_ptr, bytes_per_token, rank_id, max_tokens_per_rank,\n payload_idx, ptrs, topk_target_ranks, topk_send_indices);\n } else if (bytes_per_token % 8 == 0) {\n vectorized_dispatch_impl<8, TOP_K>(src_ptr, bytes_per_token, rank_id, max_tokens_per_rank,\n payload_idx, ptrs, topk_target_ranks, topk_send_indices);\n } else if (bytes_per_token % 4 == 0) {\n vectorized_dispatch_impl<4, TOP_K>(src_ptr, bytes_per_token, rank_id, max_tokens_per_rank,\n payload_idx, ptrs, topk_target_ranks, topk_send_indices);\n } else if (bytes_per_token % 2 == 0) {\n vectorized_dispatch_impl<2, TOP_K>(src_ptr, bytes_per_token, rank_id, max_tokens_per_rank,\n payload_idx, ptrs, topk_target_ranks, topk_send_indices);\n } else {\n vectorized_dispatch_impl<1, TOP_K>(src_ptr, bytes_per_token, rank_id, max_tokens_per_rank,\n payload_idx, ptrs, topk_target_ranks, topk_send_indices);\n }\n}\n\n__global__ void moeA2APrepareDispatchKernel(int* send_counters, int* local_token_counter,\n int ep_size, uint32_t* flag_val_ptr, bool enable_pdl) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n if (enable_pdl) cudaGridDependencySynchronize();\n cudaTriggerProgrammaticLaunchCompletion();\n#endif\n int idx = blockIdx.x * blockDim.x + threadIdx.x;\n // Zero send_counters\n if (idx < ep_size) {\n send_counters[idx] = 0;\n }\n // Zero local_token_counter and increment flag_val\n if (idx == 0) {\n *local_token_counter = 0;\n // Increment flag_val for this dispatch round\n *flag_val_ptr = *flag_val_ptr + 1;\n }\n}\n\n// ============================================================================\n// Generic Dispatch Kernel Implementation\n// One CTA processes one token and all its payloads.\n// ============================================================================\n\ntemplate <int TOP_K, bool ENABLE_EPLB, bool ENABLE_RANK_MASK, bool COMPACT_EP4>\n__global__ void moeA2ADispatchKernel(\n int32_t const* token_selected_experts, // [local_num_tokens, TOP_K]\n const DispatchKernelPointers ptrs, // Struct containing all kernel pointers\n int num_payloads, // Number of payloads\n int max_tokens_per_rank, // Maximum tokens per rank\n int local_num_tokens, int rank_id, int ep_size, int num_experts, int eplb_stats_num_experts,\n bool enable_pdl) {\n static_assert(!COMPACT_EP4 || TOP_K > kEp4Size);\n int thread_idx = threadIdx.x;\n int local_token_idx = blockIdx.x;\n\n if (local_num_tokens == 0) {\n // Special case: If local_num_tokens == 0,\n // we need to keep the threads where local_token_idx == 0 alive to participate in the\n // synchronization. Other threads should return.\n if (local_token_idx > 0) return;\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n if (enable_pdl) cudaGridDependencySynchronize();\n#endif\n } else {\n // Threads that do not have a token to process should return.\n if (local_token_idx >= local_num_tokens) return;\n\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n if (enable_pdl) cudaGridDependencySynchronize();\n#endif\n\n // Prepare per-policy shared-memory tiles for this token\n extern __shared__ int smem[];\n int* smem_topk_target_ranks = smem;\n int* smem_topk_send_indices = nullptr;\n int* smem_compact_send_indices = smem;\n if constexpr (!COMPACT_EP4) {\n smem_topk_send_indices = smem + TOP_K;\n }\n\n // Precompute the ceil/floor partition parameters once per thread, outside the\n // per-token TOP_K loop. The fast path (remainder == 0) then collapses to a single\n // integer divide per call, matching the pre-PR uniform-partition cost exactly.\n int const ep_base = num_experts / ep_size;\n int const ep_remainder = num_experts - ep_base * ep_size; // == num_experts % ep_size\n\n if (thread_idx < warpSize) {\n int lane_id = thread_idx;\n if constexpr (COMPACT_EP4) {\n if (lane_id < kEp4Size) {\n smem_compact_send_indices[lane_id] = -1;\n }\n __syncwarp();\n }\n\n unsigned topk_mask = __ballot_sync(0xffffffff, lane_id < TOP_K);\n if (lane_id < TOP_K) {\n int k = lane_id;\n int expert_id = token_selected_experts[local_token_idx * TOP_K + k];\n // Use contiguous ceil/floor partitioning (supports non-divisible num_experts % ep_size).\n int target_rank = compute_target_rank_id(expert_id, ep_base, ep_remainder);\n\n // Elect the first top-k lane for each destination rank; duplicate targets within a\n // token collapse to a single send (replaces the old serial already_copied bitmask).\n unsigned matching_lanes = __match_any_sync(topk_mask, target_rank);\n bool is_first = lane_id == __ffs(matching_lanes) - 1;\n\n // Dead ranks (ENABLE_RANK_MASK) are dropped the same way as duplicates: no send is\n // issued and topk_send_indices[k] stays < 0, so combine's existing skip check on that\n // sentinel handles both cases uniformly. When ENABLE_RANK_MASK is false, the dead-rank\n // check is compiled out entirely (no active_rank_mask load/branch on this hot path).\n bool is_valid = is_first;\n if constexpr (ENABLE_RANK_MASK) {\n is_valid = is_valid && is_rank_active(ptrs.active_rank_mask, target_rank);\n }\n\n int dst_token_idx = -1;\n if (is_valid) {\n dst_token_idx = atomicAdd(&ptrs.send_counters[target_rank], 1);\n if constexpr (COMPACT_EP4) {\n smem_compact_send_indices[target_rank] = dst_token_idx;\n }\n } else {\n target_rank = -1;\n }\n\n ptrs.topk_target_ranks[local_token_idx * TOP_K + k] = target_rank;\n ptrs.topk_send_indices[local_token_idx * TOP_K + k] = dst_token_idx;\n if constexpr (!COMPACT_EP4) {\n smem_topk_target_ranks[k] = target_rank;\n smem_topk_send_indices[k] = dst_token_idx;\n }\n }\n }\n // Sync before dispatching data\n __syncthreads();\n\n // EP4 has at most four unique destinations, regardless of TOP_K. The compact\n // specialization avoids expanding those destinations back to TOP_K entries.\n constexpr int NUM_DESTINATIONS = COMPACT_EP4 ? kEp4Size : TOP_K;\n int target_ranks[NUM_DESTINATIONS];\n int send_indices[NUM_DESTINATIONS];\n if constexpr (COMPACT_EP4) {\n#pragma unroll\n for (int target_rank = 0; target_rank < NUM_DESTINATIONS; ++target_rank) {\n target_ranks[target_rank] = target_rank;\n send_indices[target_rank] = smem_compact_send_indices[target_rank];\n }\n } else {\n#pragma unroll\n for (int k = 0; k < TOP_K; ++k) {\n target_ranks[k] = smem_topk_target_ranks[k];\n send_indices[k] = smem_topk_send_indices[k];\n }\n }\n\n // Perform a single source load and fan out to each unique destination.\n for (int payload_idx = 0; payload_idx < num_payloads; payload_idx++) {\n uint8_t const* src_data = static_cast<uint8_t const*>(ptrs.src_data_ptrs[payload_idx]);\n int bytes_per_token = ptrs.payload_bytes_per_token[payload_idx];\n uint8_t const* src_ptr = src_data + local_token_idx * bytes_per_token;\n\n vectorized_dispatch<NUM_DESTINATIONS>(src_ptr, bytes_per_token, rank_id, max_tokens_per_rank,\n payload_idx, ptrs, target_ranks, send_indices);\n }\n\n __syncthreads();\n }\n\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n cudaTriggerProgrammaticLaunchCompletion();\n#endif\n\n bool is_first_warp = threadIdx.x / warpSize == 0;\n if (is_first_warp) {\n int lane_id = threadIdx.x % warpSize;\n\n bool is_last_token = false;\n if (lane_id == 0) {\n if (local_num_tokens != 0) {\n int cnt = atomicAdd(ptrs.local_token_counter, 1);\n is_last_token = cnt + 1 == local_num_tokens;\n } else {\n is_last_token = true;\n }\n }\n is_last_token = __shfl_sync(0xffffffff, is_last_token, 0);\n\n if (is_last_token) {\n// Store send_counters to recv_counters.\n// Skip masked target ranks: their symmetric memory may be inaccessible.\n#pragma unroll 1 // No unroll as one iter is typically enough\n for (int target_rank = lane_id; target_rank < ep_size; target_rank += warpSize) {\n if constexpr (ENABLE_RANK_MASK) {\n if (!is_rank_active(ptrs.active_rank_mask, target_rank)) continue;\n }\n int send_count = ptrs.send_counters[target_rank];\n ptrs.recv_counters[target_rank][rank_id] = send_count;\n }\n\n if constexpr (ENABLE_EPLB) {\n // Write local stats into peer buffers before the release fence below.\n // Skip masked target ranks for the same reason as above.\n#pragma unroll 1\n for (int target_rank = 0; target_rank < ep_size; ++target_rank) {\n if constexpr (ENABLE_RANK_MASK) {\n if (!is_rank_active(ptrs.active_rank_mask, target_rank)) continue;\n }\n int* target_stats = ptrs.eplb_gathered_stats[target_rank];\n for (int expert_id = lane_id; expert_id < eplb_stats_num_experts; expert_id += warpSize) {\n int stat_val = ptrs.eplb_local_stats[expert_id];\n target_stats[rank_id * eplb_stats_num_experts + expert_id] = stat_val;\n }\n }\n }\n\n#if !DISABLE_SYNC_FOR_PROFILING\n uint32_t expected_value = *ptrs.flag_val;\n\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"fence.release.sys;\");\n#else\n __threadfence_system();\n#endif\n// Signal completion to all active peers; skip dead ranks (their symmetric memory is\n// unreachable).\n#pragma unroll 1 // No unroll as one iter is typically enough\n for (int target_rank = lane_id; target_rank < ep_size; target_rank += warpSize) {\n if constexpr (ENABLE_RANK_MASK) {\n if (!is_rank_active(ptrs.active_rank_mask, target_rank)) continue;\n }\n uint32_t* flag_addr = &ptrs.completion_flags[target_rank][rank_id];\n asm volatile(\"st.relaxed.sys.u32 [%0], %1;\" ::\"l\"(flag_addr), \"r\"(expected_value));\n\n#if ENABLE_DEBUG_PRINT\n printf(\"dispatch: +++Rank %d setting completion flag to %d for rank %d\\n\", rank_id,\n expected_value, target_rank);\n#endif\n }\n\n// Wait for all active peers to signal; skip dead ranks (otherwise we would spin forever —\n// this is the bug the rank-mask is here to prevent).\n#pragma unroll 1 // No unroll\n for (int peer_rank = lane_id; peer_rank < ep_size; peer_rank += warpSize) {\n if constexpr (ENABLE_RANK_MASK) {\n if (!is_rank_active(ptrs.active_rank_mask, peer_rank)) continue;\n }\n bool flag_set = false;\n [[maybe_unused]] auto s = clock64();\n do {\n uint32_t* flag_ptr = &ptrs.completion_flags[rank_id][peer_rank];\n uint32_t flag_value;\n // Acquire load to ensure visibility of peer's release-store\n asm volatile(\"ld.relaxed.sys.u32 %0, [%1];\" : \"=r\"(flag_value) : \"l\"(flag_ptr));\n#if ENABLE_DEBUG_PRINT\n printf(\n \"dispatch: ---Rank %d received completion flag from rank %d, flag_value: %d, \"\n \"expected_value: \"\n \"%d, address: %p\\n\",\n rank_id, peer_rank, flag_value, expected_value, flag_ptr);\n#endif\n flag_set = flag_value == expected_value;\n } while (!flag_set && !check_timeout(s));\n\n if (__builtin_expect(!flag_set, 0)) {\n printf(\"dispatch: ---Rank %d timed out waiting for completion flag from rank %d\\n\",\n rank_id, peer_rank);\n asm volatile(\"trap;\");\n return;\n }\n }\n // asm volatile(\"fence.acquire.sys;\");\n#endif\n }\n }\n}\n\nvoid moe_a2a_prepare_dispatch_launch(MoeA2ADispatchParams const& params) {\n launchWithPdlWhenEnabled(\"moeA2APrepareDispatchKernel\", params.enable_pdl,\n moeA2APrepareDispatchKernel, 1, params.ep_size, 0, params.stream,\n params.send_counters, params.local_token_counter, params.ep_size,\n params.flag_val, params.enable_pdl);\n}\n\n// ============================================================================\n// Launch Functions\n// ============================================================================\n\nvoid moe_a2a_dispatch_launch(MoeA2ADispatchParams const& params) {\n // Validate parameters\n TLLM_CHECK(params.top_k > 0 && params.top_k <= kMaxTopK);\n TLLM_CHECK(params.ep_size > 0 && params.ep_size <= kMaxRanks);\n TLLM_CHECK(params.ep_rank >= 0 && params.ep_rank < params.ep_size);\n TLLM_CHECK(params.local_num_tokens >= 0);\n TLLM_CHECK(params.num_payloads > 0 && params.num_payloads <= kMaxPayloads);\n if (params.enable_rank_mask) {\n // The local rank must always be marked active in its own view of the mask; otherwise the\n // kernel itself would be running on a \"dead\" rank.\n TLLM_CHECK_WITH_INFO(\n (params.active_rank_mask[params.ep_rank >> 6] >> (params.ep_rank & 63)) & 1ULL,\n \"active_rank_mask must mark the local ep_rank (%d) as active\", params.ep_rank);\n }\n\n // Prepare kernel pointers struct\n DispatchKernelPointers kernel_ptrs = {};\n\n // Fill source data pointers and payload sizes\n for (int i = 0; i < params.num_payloads; i++) {\n kernel_ptrs.src_data_ptrs[i] = params.payloads[i].src_data;\n kernel_ptrs.payload_bytes_per_token[i] =\n params.payloads[i].element_size * params.payloads[i].elements_per_token;\n }\n\n // Fill receive buffer pointers\n for (int target_rank = 0; target_rank < params.ep_size; target_rank++) {\n kernel_ptrs.recv_counters[target_rank] = params.recv_counters[target_rank];\n kernel_ptrs.eplb_gathered_stats[target_rank] = params.eplb_gathered_stats[target_rank];\n for (int payload = 0; payload < params.num_payloads; payload++) {\n kernel_ptrs.recv_buffers[target_rank][payload] = params.recv_buffers[target_rank][payload];\n }\n }\n\n // Copy completion flag pointers\n for (int i = 0; i < params.ep_size; i++) {\n kernel_ptrs.completion_flags[i] = params.completion_flags[i];\n }\n kernel_ptrs.flag_val = params.flag_val;\n\n // Copy communication tracking pointers\n kernel_ptrs.send_counters = params.send_counters;\n kernel_ptrs.local_token_counter = params.local_token_counter;\n kernel_ptrs.topk_target_ranks = params.topk_target_ranks;\n kernel_ptrs.topk_send_indices = params.topk_send_indices;\n kernel_ptrs.eplb_local_stats = params.eplb_local_stats;\n\n // Copy active-rank bitmask into the kernel pointers struct\n for (int w = 0; w < kRankMaskWords; ++w) {\n kernel_ptrs.active_rank_mask[w] = params.active_rank_mask[w];\n }\n\n int block_size = tensorrt_llm::common::getEnvMoeA2ADispatchBlockSize();\n\n bool const use_compact_ep4 = params.ep_size == kEp4Size && params.top_k > kEp4Size;\n\n int max_payload_bytes_per_token = 0;\n for (int i = 0; i < params.num_payloads; ++i) {\n if (kernel_ptrs.payload_bytes_per_token[i] > max_payload_bytes_per_token) {\n max_payload_bytes_per_token = kernel_ptrs.payload_bytes_per_token[i];\n }\n }\n // Small payloads do not have enough 16-byte vectors to use larger CTAs. A GB200\n // sweep found 128 threads faster than both 64 and 256 at prefill token counts.\n if (use_compact_ep4 && max_payload_bytes_per_token <= kCompactDispatchMaxPayloadBytes &&\n block_size > kCompactDispatchBlockSize) {\n block_size = kCompactDispatchBlockSize;\n }\n\n // Configure kernel launch: one block per token\n int grid_size = params.local_num_tokens;\n // If local_num_tokens is 0, we still need to launch a minimal kernel to participate in the\n // synchronization.\n if (grid_size == 0) {\n grid_size = 1;\n }\n SWITCH_BOOL(params.enable_rank_mask, ENABLE_RANK_MASK, {\n SWITCH_BOOL(params.enable_eplb, EPLB_STATS, {\n if (use_compact_ep4) {\n int shared_bytes = kEp4Size * (int)sizeof(int);\n SWITCH_TOP_K(\n params.top_k, TOP_K, if constexpr (TOP_K > kEp4Size) {\n auto kernel_fn = moeA2ADispatchKernel<TOP_K, EPLB_STATS, ENABLE_RANK_MASK, true>;\n launchWithPdlWhenEnabled(\n \"moeA2ADispatchKernel\", params.enable_pdl, kernel_fn, grid_size, block_size,\n shared_bytes, params.stream, params.token_selected_experts, kernel_ptrs,\n params.num_payloads, params.max_tokens_per_rank, params.local_num_tokens,\n params.ep_rank, params.ep_size, params.num_experts, params.eplb_stats_num_experts,\n params.enable_pdl);\n })\n } else {\n int shared_bytes = 2 * params.top_k * (int)sizeof(int);\n SWITCH_TOP_K(params.top_k, TOP_K, {\n auto kernel_fn = moeA2ADispatchKernel<TOP_K, EPLB_STATS, ENABLE_RANK_MASK, false>;\n launchWithPdlWhenEnabled(\"moeA2ADispatchKernel\", params.enable_pdl, kernel_fn, grid_size,\n block_size, shared_bytes, params.stream,\n params.token_selected_experts, kernel_ptrs, params.num_payloads,\n params.max_tokens_per_rank, params.local_num_tokens,\n params.ep_rank, params.ep_size, params.num_experts,\n params.eplb_stats_num_experts, params.enable_pdl);\n });\n }\n });\n })\n}\n\n// ============================================================================\n// Combine kernels\n// ============================================================================\n\n// Accumulate across all valid ranks into float32 registers, then store as T (QuantMode==NONE)\n// or quantize the result to MXFP8 with a per-block scale factor (QuantMode==MXFP8).\n//\n// InT: input element type in the recv buffer (defaults to T for same-type accumulation;\n// __nv_fp8_e4m3 for the low-precision combine path). sizeof(InT) must divide VEC_SIZE_BYTES.\n// T: output / accumulation-cast element type (and the input type when InT == T).\n//\n// Unified path: load VEC_SIZE_BYTES bytes, reinterpret as InT[elems_per_vec], accumulate as\n// float32, then either cast_store as T (NONE) or convert to MXFP8 + emit the block scale factor\n// (MXFP8, which always uses InT == T). Block-per-token indexing\n// (threadIdx.x/blockDim.x/blockIdx.x).\ntemplate <int VEC_SIZE_BYTES, int TOP_K, typename T, typename InT = T,\n MoeA2ACombineQuantMode QuantMode = MoeA2ACombineQuantMode::NONE,\n MoeA2ACombineSwizzleSFMode SwizzleMode = MoeA2ACombineSwizzleSFMode::LINEAR>\n__device__ void vectorized_combine_impl(void* output_buffer, void* sf_output, int row_idx,\n int row_size, int stride_per_token, int rank_id,\n int max_tokens_per_rank, CombineKernelPointers const& ptrs,\n float OutputScalarScale = 1.0f) {\n using flashinfer::vec_t;\n\n // elems_per_vec: number of InT elements per VEC_SIZE_BYTES-byte load (constexpr).\n constexpr int elems_per_vec = VEC_SIZE_BYTES / static_cast<int>(sizeof(InT));\n // size_per_token: byte span of one token in the recv buffer (InT-typed).\n const int size_per_token = row_size * static_cast<int>(sizeof(InT));\n\n // Output base pointers. NONE writes T elements; MXFP8 writes packed fp8 bytes.\n T* dst_typed_base = nullptr;\n uint8_t* dst_bytes = nullptr;\n if constexpr (QuantMode == MoeA2ACombineQuantMode::NONE) {\n dst_typed_base = static_cast<T*>(output_buffer) + static_cast<size_t>(row_idx) * row_size;\n } else {\n // MXFP8 stores one byte per logical element; FP4 packs two e2m1 values per byte, so its\n // rows are half as wide. The accumulation still reads InT-sized inputs either way.\n size_t const bytes_per_row = QuantMode == MoeA2ACombineQuantMode::MXFP8\n ? static_cast<size_t>(row_size)\n : static_cast<size_t>(row_size) / 2;\n dst_bytes = static_cast<uint8_t*>(output_buffer) + static_cast<size_t>(row_idx) * bytes_per_row;\n }\n\n int const stride = blockDim.x * VEC_SIZE_BYTES;\n int const local_token_idx = blockIdx.x;\n\n // offset is a byte offset into the recv buffer, stepping by VEC_SIZE_BYTES bytes.\n for (int offset = threadIdx.x * VEC_SIZE_BYTES; offset < size_per_token; offset += stride) {\n int logical_offset = offset / static_cast<int>(sizeof(InT));\n // Per-k vec_t<float, elems_per_vec> accumulators, zero-initialised via fill().\n vec_t<float, elems_per_vec> acc[TOP_K];\n\n // Pass 1: issue all TOP_K loads back-to-back without any type conversion.\n // Raw InT bytes are loaded directly into acc[k]'s register storage, reinterpreted as\n // vec_t<InT, elems_per_vec> (VEC_SIZE_BYTES bytes, fitting in the low end of acc[k]'s\n // sizeof(float)*elems_per_vec allocation). Separating load from cast lets the compiler\n // schedule all VEC_SIZE_BYTES-byte global loads consecutively, hiding memory latency across k.\n#pragma unroll\n for (int k = 0; k < TOP_K; ++k) {\n int target_rank = ptrs.topk_target_ranks[local_token_idx * TOP_K + k];\n int dst_idx = ptrs.topk_send_indices[local_token_idx * TOP_K + k];\n // dst_idx < 0: duplicate/dead-target sentinel already set by dispatch (which consults\n // active_rank_mask once per token). Rechecking is_rank_active here is redundant and,\n // being on the per-k vectorized hot path, measurably regresses combine throughput.\n if (dst_idx < 0) {\n acc[k].fill(0.0f);\n continue;\n }\n\n uint8_t const* recv_buffer = static_cast<uint8_t const*>(ptrs.recv_buffers[target_rank][0]);\n size_t base_source_rank =\n static_cast<size_t>(rank_id) * static_cast<size_t>(max_tokens_per_rank) +\n static_cast<size_t>(dst_idx);\n // stride_per_token: byte distance between tokens in the recv buffer.\n // Equals size_per_token for normal cases; may differ for FP8 in-place\n // (BF16-stride workspace but FP8-sized payload).\n size_t base_token = base_source_rank * static_cast<size_t>(stride_per_token);\n\n reinterpret_cast<vec_t<InT, elems_per_vec>&>(acc[k]).load(\n reinterpret_cast<InT const*>(recv_buffer + base_token + offset));\n }\n\n // Pass 2: in-place cast InT → float, iterating j in descending order.\n // float[j] occupies bytes [j*4, j*4+3]; InT[j] occupies [j*sizeof(InT), ...).\n // For sizeof(InT) < sizeof(float), high-j float writes land above all remaining\n // InT bytes, so descending order is always write-after-read safe.\n#pragma unroll\n for (int k = 0; k < TOP_K; ++k) {\n if (ptrs.topk_send_indices[local_token_idx * TOP_K + k] < 0)\n continue; // acc[k] already holds 0.0f from fill() above\n#pragma unroll\n for (int j = elems_per_vec - 1; j >= 0; --j)\n acc[k][j] = static_cast<float>(reinterpret_cast<InT const*>(&acc[k])[j]);\n }\n // Reduce acc[TOP_K] into acc[0] via unrolled tree-reduction.\n // acc[k][j] uses vec_t::operator[] which returns float& — no indirection overhead.\n if constexpr (TOP_K == 22) {\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[1][j];\n acc[2][j] += acc[3][j];\n acc[4][j] += acc[5][j];\n acc[6][j] += acc[7][j];\n acc[8][j] += acc[9][j];\n acc[10][j] += acc[11][j];\n acc[12][j] += acc[13][j];\n acc[14][j] += acc[15][j];\n acc[16][j] += acc[17][j];\n acc[18][j] += acc[19][j];\n acc[20][j] += acc[21][j];\n }\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[2][j];\n acc[4][j] += acc[6][j];\n acc[8][j] += acc[10][j];\n acc[12][j] += acc[14][j];\n acc[16][j] += acc[18][j];\n }\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[4][j];\n acc[8][j] += acc[12][j];\n acc[16][j] += acc[20][j];\n }\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[8][j];\n acc[0][j] += acc[16][j];\n }\n } else if constexpr (TOP_K == 16) {\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[1][j];\n acc[2][j] += acc[3][j];\n acc[4][j] += acc[5][j];\n acc[6][j] += acc[7][j];\n acc[8][j] += acc[9][j];\n acc[10][j] += acc[11][j];\n acc[12][j] += acc[13][j];\n acc[14][j] += acc[15][j];\n }\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[2][j];\n acc[4][j] += acc[6][j];\n acc[8][j] += acc[10][j];\n acc[12][j] += acc[14][j];\n }\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[4][j];\n acc[8][j] += acc[12][j];\n }\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[8][j];\n }\n } else if constexpr (TOP_K == 10) {\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[1][j];\n acc[2][j] += acc[3][j];\n acc[4][j] += acc[5][j];\n acc[6][j] += acc[7][j];\n acc[8][j] += acc[9][j];\n }\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[2][j];\n acc[4][j] += acc[6][j];\n }\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[4][j];\n acc[0][j] += acc[8][j];\n }\n } else if constexpr (TOP_K == 8) {\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[1][j];\n acc[2][j] += acc[3][j];\n acc[4][j] += acc[5][j];\n acc[6][j] += acc[7][j];\n }\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[2][j];\n acc[4][j] += acc[6][j];\n }\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[4][j];\n }\n } else if constexpr (TOP_K == 6) {\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[1][j];\n acc[2][j] += acc[3][j];\n acc[4][j] += acc[5][j];\n }\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[2][j];\n acc[0][j] += acc[4][j];\n }\n } else if constexpr (TOP_K == 4) {\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[1][j];\n acc[2][j] += acc[3][j];\n }\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[2][j];\n }\n } else if constexpr (TOP_K == 2) {\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[1][j];\n }\n } else if constexpr (TOP_K == 1) {\n // nothing to do\n } else {\n // Generic fallback: accumulate all into acc[0]\n#pragma unroll\n for (int k = 1; k < TOP_K; ++k) {\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[k][j];\n }\n }\n }\n // Epilogue: store the float accumulator as T (NONE) or quantize to MXFP8 + scale factor.\n if constexpr (QuantMode == MoeA2ACombineQuantMode::NONE) {\n // cast_store: converts float->T element-by-element then writes via vectorized int4 store.\n acc[0].cast_store(dst_typed_base + offset / static_cast<int>(sizeof(InT)));\n } else {\n constexpr uint32_t sf_vec_size = QuantMode == MoeA2ACombineQuantMode::NVFP4 ? 16 : 32;\n constexpr uint32_t threads_per_sf = sf_vec_size / elems_per_vec;\n uint8_t scale;\n auto store_sf = [&]() {\n int64_t sf_offset;\n const int64_t num_vecs_per_row = (row_size + sf_vec_size - 1) / sf_vec_size;\n const int64_t sf_idx = logical_offset / sf_vec_size;\n if constexpr (SwizzleMode == MoeA2ACombineSwizzleSFMode::LINEAR) {\n sf_offset = row_idx * num_vecs_per_row + sf_idx;\n } else if constexpr (SwizzleMode == MoeA2ACombineSwizzleSFMode::SWIZZLE_128x4) {\n sf_offset = get_sf_out_offset_128x4(row_idx, sf_idx, num_vecs_per_row);\n } else { // SWIZZLE_8x4\n sf_offset = get_sf_out_offset_8x4(row_idx, sf_idx, num_vecs_per_row);\n }\n if (threadIdx.x % threads_per_sf == 0) {\n reinterpret_cast<uint8_t*>(sf_output)[sf_offset] = scale;\n }\n };\n // Cast the float32 accumulator down to T to feed the MXFP8/FP4 converter's PackedVec input.\n tensorrt_llm::kernels::PackedVec<T, elems_per_vec> packed_vec;\n T* packed_elems = reinterpret_cast<T*>(&packed_vec);\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n packed_elems[j] = static_cast<T>(acc[0][j]);\n }\n if constexpr (QuantMode == MoeA2ACombineQuantMode::MXFP8) {\n static_assert(elems_per_vec == 8, \"MXFP8 quantization requires 8 elements per vector\");\n uint64_t fp8x8 =\n tensorrt_llm::kernels::cvt_warp_fp16_to_mxfp8<T, 32, elems_per_vec>(packed_vec, &scale);\n reinterpret_cast<uint64_t*>(dst_bytes)[logical_offset / elems_per_vec] = fp8x8;\n } else if constexpr (QuantMode == MoeA2ACombineQuantMode::NVFP4 ||\n QuantMode == MoeA2ACombineQuantMode::MXFP4) {\n static_assert(elems_per_vec == 8 || elems_per_vec == 16,\n \"FP4 quantization requires 8 or 16 elements per vector\");\n constexpr int SF_VEC_SIZE = QuantMode == MoeA2ACombineQuantMode::MXFP4 ? 32 : 16;\n auto fp4_packed = tensorrt_llm::kernels::cvt_warp_fp16_to_fp4 < T, SF_VEC_SIZE,\n elems_per_vec,\n QuantMode == MoeA2ACombineQuantMode::MXFP4 > (packed_vec, OutputScalarScale, &scale);\n // cvt_warp_fp16_to_fp4 returns uint32_t for 8 elems (4 packed bytes) and uint64_t for 16\n // (8 packed bytes); store at the matching width so packed rows stay contiguous and fit the\n // dim/2-byte output buffer (a wider store would overflow into the next token's row).\n reinterpret_cast<decltype(fp4_packed)*>(dst_bytes)[logical_offset / elems_per_vec] =\n fp4_packed;\n }\n store_sf();\n }\n }\n}\n\n// Wrapper that selects vector width based on size_per_token alignment.\n// QuantMode==NONE writes T (optionally upcast from an fp8 InT); QuantMode==MXFP8 writes packed\n// fp8 + scale factors (always InT == T, fixed 16-byte / 8-element vectors).\n// stride_per_token: byte distance between tokens in the recv buffer (may differ from\n// size_per_token when FP8 in-place uses a BF16-stride workspace with an FP8-sized payload).\n// InT: input element type in recv buffer (defaults to T for same-type accumulation).\ntemplate <int TOP_K, typename T, typename InT = T,\n MoeA2ACombineQuantMode QuantMode = MoeA2ACombineQuantMode::NONE,\n MoeA2ACombineSwizzleSFMode SwizzleMode = MoeA2ACombineSwizzleSFMode::LINEAR>\n__device__ void vectorized_combine(void* output_buffer, void* sf_output, int row_idx, int row_size,\n int stride_per_token, int rank_id, int max_tokens_per_rank,\n CombineKernelPointers const& ptrs,\n float OutputScalarScale = 1.0f) {\n const int size_per_token = row_size * static_cast<int>(sizeof(InT));\n if constexpr (QuantMode != MoeA2ACombineQuantMode::NONE) {\n // MXFP8/FP4 require 16-byte vectors (8 or 16 elements per vec), always InT == T.\n vectorized_combine_impl<16, TOP_K, T, InT, QuantMode, SwizzleMode>(\n output_buffer, sf_output, row_idx, row_size, stride_per_token, rank_id, max_tokens_per_rank,\n ptrs, OutputScalarScale);\n } else {\n // Each branch is guarded by if constexpr (sizeof(InT) <= VEC_SIZE_BYTES) so the compiler\n // never instantiates vectorized_combine_impl with elems_per_vec == 0.\n if (size_per_token % 16 == 0) {\n if constexpr (static_cast<int>(sizeof(InT)) <= 16)\n vectorized_combine_impl<16, TOP_K, T, InT>(output_buffer, nullptr, row_idx, row_size,\n stride_per_token, rank_id, max_tokens_per_rank,\n ptrs);\n } else if (size_per_token % 8 == 0) {\n if constexpr (static_cast<int>(sizeof(InT)) <= 8)\n vectorized_combine_impl<8, TOP_K, T, InT>(output_buffer, nullptr, row_idx, row_size,\n stride_per_token, rank_id, max_tokens_per_rank,\n ptrs);\n } else if (size_per_token % 4 == 0) {\n if constexpr (static_cast<int>(sizeof(InT)) <= 4)\n vectorized_combine_impl<4, TOP_K, T, InT>(output_buffer, nullptr, row_idx, row_size,\n stride_per_token, rank_id, max_tokens_per_rank,\n ptrs);\n } else if (size_per_token % 2 == 0) {\n if constexpr (static_cast<int>(sizeof(InT)) <= 2)\n vectorized_combine_impl<2, TOP_K, T, InT>(output_buffer, nullptr, row_idx, row_size,\n stride_per_token, rank_id, max_tokens_per_rank,\n ptrs);\n } else {\n if constexpr (static_cast<int>(sizeof(InT)) <= 1)\n vectorized_combine_impl<1, TOP_K, T, InT>(output_buffer, nullptr, row_idx, row_size,\n stride_per_token, rank_id, max_tokens_per_rank,\n ptrs);\n }\n }\n}\n\n// ---- vec_convert: per-vector type conversion, specialized by PTX where available ----\n// Generic: SrcT -> float -> DstT (all architectures, all type combinations).\ntemplate <size_t VEC_SIZE, typename SrcT, typename DstT>\n__device__ __forceinline__ void vec_convert(flashinfer::vec_t<DstT, VEC_SIZE>& out,\n flashinfer::vec_t<SrcT, VEC_SIZE> const& in) {\n#pragma unroll\n for (int j = 0; j < VEC_SIZE; ++j) out[j] = DstT(static_cast<float>(in[j]));\n}\n\n// BF16 -> FP8 e4m3: use CUDA intrinsic (SM100+, Blackwell).\n// Inline PTX \"cvt.rn.satfinite.e4m3x2.bf16x2 %h, %r\" is rejected by SM100a ptxas\n// (\"Unexpected instruction types for cvt\") because SM100a requires a 32-bit output\n// register for this instruction. __nv_fp8x2_e4m3(bfloat162) emits the correct form.\n#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)\ntemplate <size_t VEC_SIZE, std::enable_if_t<(VEC_SIZE % 2 == 0), int> = 0>\n__device__ __forceinline__ void vec_convert(flashinfer::vec_t<__nv_fp8_e4m3, VEC_SIZE>& out,\n flashinfer::vec_t<__nv_bfloat16, VEC_SIZE> const& in) {\n __nv_fp8x2_e4m3* out_fp8x2 = reinterpret_cast<__nv_fp8x2_e4m3*>(&out);\n __nv_bfloat162 const* in_bf16x2 = reinterpret_cast<__nv_bfloat162 const*>(&in);\n#pragma unroll\n for (int p = 0; p < static_cast<int>(VEC_SIZE) / 2; ++p)\n out_fp8x2[p] = __nv_fp8x2_e4m3(in_bf16x2[p]);\n}\n#endif\n\n// FP16 -> FP8 e4m3: paired PTX cvt.rn.satfinite.e4m3x2.f16x2 (SM89+, Hopper).\n#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 890)\ntemplate <size_t VEC_SIZE, std::enable_if_t<(VEC_SIZE % 2 == 0), int> = 0>\n__device__ __forceinline__ void vec_convert(flashinfer::vec_t<__nv_fp8_e4m3, VEC_SIZE>& out,\n flashinfer::vec_t<half, VEC_SIZE> const& in) {\n uint32_t const* src_u32 = reinterpret_cast<uint32_t const*>(&in);\n uint16_t* dst_u16 = reinterpret_cast<uint16_t*>(&out);\n#pragma unroll\n for (int p = 0; p < VEC_SIZE / 2; ++p) {\n uint16_t d;\n asm volatile(\"cvt.rn.satfinite.e4m3x2.f16x2 %0, %1;\" : \"=h\"(d) : \"r\"(src_u32[p]));\n dst_u16[p] = d;\n }\n}\n#endif\n\n// ---- vectorized_quant_impl: load -> sync -> convert -> store ----\n// VEC_SIZE is in elements (not bytes), so both SrcT and DstT vectors hold VEC_SIZE values.\n// Block-per-token: threadIdx.x indexes vectors within the token, blockDim.x is the stride.\ntemplate <int VEC_SIZE, typename SrcT, typename DstT>\n__device__ void vectorized_quant_impl(DstT* dst, SrcT const* src, int num_elements) {\n using flashinfer::vec_t;\n\n // num_elements is a multiple of VEC_SIZE here (selected by the wrapper).\n int const num_vecs = num_elements / VEC_SIZE;\n // Round the iteration bound up to a multiple of blockDim.x so every thread reaches the\n // __syncthreads() the same number of times (a divergent barrier would deadlock when\n // num_vecs is not a multiple of blockDim.x, e.g. hidden=7168 with 256 threads).\n int const vec_iters = ((num_vecs + blockDim.x - 1) / blockDim.x) * blockDim.x;\n\n for (int iter = threadIdx.x; iter < vec_iters; iter += blockDim.x) {\n bool const active = iter < num_vecs;\n int const e = iter * VEC_SIZE;\n vec_t<SrcT, VEC_SIZE> in_vec;\n if (active) in_vec.load(src + e);\n\n // Sync so all threads finish loading inputs before any thread writes output. This avoids\n // write-after-read hazards in the FP8 in-place case where this kernel's output is read as\n // input on the next iteration. All threads participate (active guards the work, not the sync).\n __syncthreads();\n\n if (active) {\n vec_t<DstT, VEC_SIZE> out_vec;\n vec_convert(out_vec, in_vec);\n out_vec.store(dst + e);\n }\n }\n}\n\ntemplate <typename SrcT, typename DstT>\n__device__ void vectorized_quant(DstT* dst, SrcT const* src, int num_elements) {\n if (num_elements % 16 == 0)\n vectorized_quant_impl<16, SrcT, DstT>(dst, src, num_elements);\n else if (num_elements % 8 == 0)\n vectorized_quant_impl<8, SrcT, DstT>(dst, src, num_elements);\n else if (num_elements % 4 == 0)\n vectorized_quant_impl<4, SrcT, DstT>(dst, src, num_elements);\n else if (num_elements % 2 == 0)\n vectorized_quant_impl<2, SrcT, DstT>(dst, src, num_elements);\n else\n vectorized_quant_impl<1, SrcT, DstT>(dst, src, num_elements);\n}\n\n// LOW_PRECISION=false: vectorized byte-copy (SrcT = payload dtype).\n// LOW_PRECISION=true: vectorized SrcT->FP8 quantization via vectorized_quant<SrcT, fp8_e4m3>.\n// stride_per_token: byte distance between tokens in recv_buffer_bytes (host-computed, avoids\n// per-thread recomputation):\n// - FP8 external payload: elements_per_token x 1 (compact FP8 layout)\n// - FP8 in-place / byte-copy: elements_per_token x sizeof(SrcT) (payload-dtype stride)\n// Copy payload to recv buffer; one block per token.\ntemplate <bool LOW_PRECISION, typename SrcT>\n__global__ void moeA2APrepareCombineKernel(uint8_t* recv_buffer_bytes, void const* payload,\n int elements_per_token, int ep_size,\n int max_tokens_per_rank, uint32_t* flag_val_ptr,\n int const* recv_counters, int stride_per_token,\n bool enable_pdl) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n if (enable_pdl) cudaGridDependencySynchronize();\n cudaTriggerProgrammaticLaunchCompletion();\n#endif\n\n if (blockIdx.x == 0 && threadIdx.x == 0) {\n // Increment flag_val for this combine round\n *flag_val_ptr = *flag_val_ptr + 1;\n }\n\n // Copy path: null payload means data is already in workspace — nothing to do.\n if (!LOW_PRECISION && payload == nullptr) return;\n\n int global_token_idx = blockIdx.x;\n\n int global_token_num = ep_size * max_tokens_per_rank;\n if (global_token_idx >= global_token_num) return;\n\n // Map global_token_idx to (rank_idx, local_token_idx)\n int rank_idx = global_token_idx / max_tokens_per_rank;\n int local_token_idx = global_token_idx % max_tokens_per_rank;\n\n // Skip invalid tokens beyond per-rank recv count\n if (local_token_idx >= recv_counters[rank_idx]) return;\n\n size_t const token_offset = static_cast<size_t>(global_token_idx) * stride_per_token;\n\n if constexpr (LOW_PRECISION) {\n // Source pointer: external payload or in-place from workspace.\n SrcT const* src_ptr = (payload != nullptr)\n ? static_cast<SrcT const*>(payload) +\n static_cast<size_t>(global_token_idx) * elements_per_token\n : reinterpret_cast<SrcT const*>(recv_buffer_bytes + token_offset);\n\n // Destination: stride_per_token encodes the correct layout for both paths\n // (compact FP8 for external, payload-dtype stride for in-place).\n __nv_fp8_e4m3* dst_ptr = reinterpret_cast<__nv_fp8_e4m3*>(recv_buffer_bytes + token_offset);\n\n vectorized_quant<SrcT, __nv_fp8_e4m3>(dst_ptr, src_ptr, elements_per_token);\n } else {\n // Generic byte copy (payload guaranteed non-null by early return above).\n vectorized_copy(recv_buffer_bytes + token_offset,\n static_cast<uint8_t const*>(payload) + token_offset, stride_per_token);\n }\n}\n\n// ============================================================================\n// Generic Combine Kernel Implementation (Templated by data type)\n// ============================================================================\n\ntemplate <typename T, int TOP_K, bool ENABLE_RANK_MASK,\n MoeA2ACombineQuantMode QuantMode = MoeA2ACombineQuantMode::NONE,\n MoeA2ACombineSwizzleSFMode SwizzleMode = MoeA2ACombineSwizzleSFMode::LINEAR>\n__global__ void moeA2ACombineKernel(\n const CombineKernelPointers ptrs, // Combine-specific struct, src_data_ptrs[0] is output\n int max_tokens_per_rank, int elements_per_token, int stride_per_token, int local_num_tokens,\n int rank_id, int ep_size, bool enable_pdl, float OutputScalarScale) {\n int local_token_idx = blockIdx.x;\n\n if (local_num_tokens == 0) {\n // Special case: If local_num_tokens == 0,\n // we need to keep the threads where local_token_idx == 0 alive to participate in the\n // synchronization. Other threads should return.\n if (local_token_idx > 0) return;\n } else {\n // Threads that do not have a token to process should return.\n if (local_token_idx >= local_num_tokens) return;\n }\n\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n if (enable_pdl) cudaGridDependencySynchronize();\n#endif\n\n#if !DISABLE_SYNC_FOR_PROFILING\n // In-kernel readiness synchronization at start of combine:\n // - One warp signals readiness to all peers with current flag_val.\n // - The first warp of each block waits for all peers' readiness (equality), then __syncthreads.\n bool is_first_warp = threadIdx.x / warpSize == 0;\n if (is_first_warp) {\n int lane_id = threadIdx.x % warpSize;\n uint32_t expected_value = *ptrs.flag_val;\n\n if (blockIdx.x == 0) {\n // asm volatile(\"fence.release.sys;\");\n // Signal readiness to all active peers; skip dead ranks (their symmetric memory is\n // unreachable).\n#pragma unroll 1 // No unroll\n for (int peer_rank = lane_id; peer_rank < ep_size; peer_rank += warpSize) {\n if constexpr (ENABLE_RANK_MASK) {\n if (!is_rank_active(ptrs.active_rank_mask, peer_rank)) continue;\n }\n uint32_t* flag_addr = &ptrs.completion_flags[peer_rank][rank_id];\n asm volatile(\"st.relaxed.sys.u32 [%0], %1;\" ::\"l\"(flag_addr), \"r\"(expected_value));\n#if ENABLE_DEBUG_PRINT\n printf(\"combine: +++Rank %d setting completion flag to %d for rank %d\\n\", rank_id,\n expected_value, peer_rank);\n#endif\n }\n }\n\n// Wait for all active peers to signal; skip dead ranks (otherwise we would spin forever —\n// this is the bug the rank-mask is here to prevent).\n#pragma unroll 1 // No unroll\n for (int peer_rank = lane_id; peer_rank < ep_size; peer_rank += warpSize) {\n if constexpr (ENABLE_RANK_MASK) {\n if (!is_rank_active(ptrs.active_rank_mask, peer_rank)) continue;\n }\n bool flag_set = false;\n [[maybe_unused]] auto s = clock64();\n do {\n uint32_t* flag_ptr = &ptrs.completion_flags[rank_id][peer_rank];\n uint32_t flag_value;\n // Acquire load to ensure visibility of peer's release-store\n asm volatile(\"ld.relaxed.sys.u32 %0, [%1];\" : \"=r\"(flag_value) : \"l\"(flag_ptr));\n#if ENABLE_DEBUG_PRINT\n printf(\n \"combine: ---Rank %d received completion flag from rank %d, flag_value: %d, \"\n \"expected_value: %d, \"\n \"address: %p\\n\",\n rank_id, peer_rank, flag_value, expected_value, flag_ptr);\n#endif\n flag_set = flag_value == expected_value;\n } while (!flag_set && !check_timeout(s));\n\n if (__builtin_expect(!flag_set, 0)) {\n printf(\"combine: ---Rank %d timed out waiting for completion flag from rank %d\\n\", rank_id,\n peer_rank);\n asm volatile(\"trap;\");\n return;\n }\n }\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"fence.acquire.sys;\");\n#else\n __threadfence_system();\n#endif\n }\n __syncthreads();\n#endif\n\n if (local_num_tokens == 0) return;\n\n // Dispatch the combine path:\n // - T == fp8_e4m3: low-precision combine, FP8 recv buffer -> BF16 output (InT=fp8, NONE quant).\n // - otherwise: same-type accumulate, then store as T (NONE) or quantize to MXFP8/FP4\n // (QuantMode).\n // vectorized_combine derives the per-token output pointer from row_idx (= local_token_idx).\n if constexpr (std::is_same_v<T, __nv_fp8_e4m3>) {\n // src_data_ptrs[0] points to a BF16 output buffer (set by moeA2ACombineOp for low precision).\n vectorized_combine<TOP_K, __nv_bfloat16, __nv_fp8_e4m3>(\n ptrs.src_data_ptrs[0], nullptr, local_token_idx, elements_per_token, stride_per_token,\n rank_id, max_tokens_per_rank, ptrs);\n } else {\n vectorized_combine<TOP_K, T, T, QuantMode, SwizzleMode>(\n ptrs.src_data_ptrs[0], ptrs.output_scales, local_token_idx, elements_per_token,\n stride_per_token, rank_id, max_tokens_per_rank, ptrs, OutputScalarScale);\n }\n\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n if (enable_pdl) cudaTriggerProgrammaticLaunchCompletion();\n#endif\n}\n\nvoid moe_a2a_prepare_combine_launch(MoeA2ACombineParams const& params) {\n constexpr int kBlockSize = 256;\n\n // FP8 in-place (use_low_precision, prepare_payload==nullptr): each CTA writes FP8 at the\n // BF16-stride position, so CTAs never race — all tokens must be processed. Copy path with a\n // null payload is a no-op; 1 block suffices for the flag increment only.\n int grid = (params.use_low_precision || params.prepare_payload != nullptr)\n ? params.ep_size * params.max_tokens_per_rank\n : 1;\n\n uint8_t* recv_buffer_bytes =\n static_cast<uint8_t*>(const_cast<void*>(params.recv_buffers[params.ep_rank]));\n void const* payload = params.prepare_payload;\n\n // stride_per_token (host-computed, avoids per-thread recompute):\n // FP8 external: EPT x 1 (compact FP8, dst packed tightly)\n // FP8 in-place / byte-copy: EPT x sizeof(SrcT) (payload-dtype stride)\n SWITCH_BOOL(params.use_low_precision, LOW_PRECISION, {\n SWITCH_DTYPE(params.dtype, SrcT, {\n bool const low_precision_staged = LOW_PRECISION && (params.prepare_payload != nullptr);\n int const stride_per_token = low_precision_staged\n ? params.elements_per_token\n : params.elements_per_token * static_cast<int>(sizeof(SrcT));\n auto kernel_fn = moeA2APrepareCombineKernel<LOW_PRECISION, SrcT>;\n launchWithPdlWhenEnabled(\"moeA2APrepareCombineKernel\", params.enable_pdl, kernel_fn, grid,\n kBlockSize, 0, params.stream, recv_buffer_bytes, payload,\n params.elements_per_token, params.ep_size,\n params.max_tokens_per_rank, params.flag_val, params.recv_counters,\n stride_per_token, params.enable_pdl);\n });\n });\n}\n\n// ============================================================================\n// Combine Launch Function\n// ============================================================================\n\nvoid moe_a2a_combine_launch(MoeA2ACombineParams const& params) {\n // Validate parameters\n TLLM_CHECK(params.top_k > 0 && params.top_k <= kMaxTopK);\n TLLM_CHECK(params.ep_size > 0 && params.ep_size <= kMaxRanks);\n TLLM_CHECK(params.ep_rank >= 0 && params.ep_rank < params.ep_size);\n TLLM_CHECK(params.local_num_tokens >= 0);\n TLLM_CHECK(params.elements_per_token > 0);\n if (params.enable_rank_mask) {\n // The local rank must always be marked active in its own view of the mask; otherwise the\n // kernel itself would be running on a \"dead\" rank.\n TLLM_CHECK_WITH_INFO(\n (params.active_rank_mask[params.ep_rank >> 6] >> (params.ep_rank & 63)) & 1ULL,\n \"active_rank_mask must mark the local ep_rank (%d) as active\", params.ep_rank);\n }\n\n // Configure kernel launch: one block per token\n int const kBlockSize = tensorrt_llm::common::getEnvMoeA2ACombineBlockSize();\n int grid_size_block = params.local_num_tokens;\n // If local_num_tokens is 0, we still need to launch a minimal kernel to participate in the\n // synchronization.\n if (grid_size_block == 0) {\n grid_size_block = 1;\n }\n\n // Prepare kernel pointers struct for combine\n CombineKernelPointers kernel_ptrs = {}; // Zero-initialize\n\n // Set output data pointer in src_data_ptrs[0]\n kernel_ptrs.src_data_ptrs[0] = params.output_data;\n kernel_ptrs.output_scales = params.output_scales;\n\n // Fill recv buffer pointers\n for (int rank = 0; rank < params.ep_size; rank++) {\n kernel_ptrs.recv_buffers[rank][0] = params.recv_buffers[rank];\n }\n\n // Copy completion flag pointers\n for (int i = 0; i < params.ep_size; i++) {\n kernel_ptrs.completion_flags[i] = params.completion_flags[i];\n }\n kernel_ptrs.flag_val = params.flag_val;\n\n // Copy communication tracking pointers\n kernel_ptrs.topk_target_ranks = params.topk_target_ranks;\n kernel_ptrs.topk_send_indices = params.topk_send_indices;\n\n // Copy active-rank bitmask into the kernel pointers struct\n for (int w = 0; w < kRankMaskWords; ++w) {\n kernel_ptrs.active_rank_mask[w] = params.active_rank_mask[w];\n }\n\n int grid = grid_size_block; // one block per token\n\n // stride_per_token: byte distance between tokens in the recv buffer.\n // FP8 external payload: EPT × 1 (compact FP8 layout)\n // FP8 in-place / non-FP8: EPT × sizeof(PayloadT) (payload-dtype stride)\n bool const low_precision_staged = params.use_low_precision && (params.prepare_payload != nullptr);\n int stride_per_token;\n SWITCH_DTYPE(params.dtype, PayloadT, {\n stride_per_token = low_precision_staged\n ? params.elements_per_token\n : params.elements_per_token * static_cast<int>(sizeof(PayloadT));\n });\n\n // When use_low_precision is set the recv buffers contain FP8 data regardless of params.dtype,\n // so dispatch the FP8 accumulation kernel in that case.\n auto const effective_dtype = params.use_low_precision ? nvinfer1::DataType::kFP8 : params.dtype;\n\n // Launch appropriate kernel with compact macros\n SWITCH_BOOL(params.enable_rank_mask, ENABLE_RANK_MASK, {\n SWITCH_DTYPE(effective_dtype, TKernelType, {\n SWITCH_TOP_K(params.top_k, TOP_K, {\n SWITCH_QUANT_MODE(TKernelType, params.quant_mode, QUANT_MODE, {\n SWITCH_SWIZZLE_MODE(params.swizzle_mode, SWIZZLE_MODE, {\n auto kernel_fn =\n moeA2ACombineKernel<TKernelType, TOP_K, ENABLE_RANK_MASK, QUANT_MODE, SWIZZLE_MODE>;\n launchWithPdlWhenEnabled(\"moeA2ACombineKernel\", params.enable_pdl, kernel_fn, grid,\n kBlockSize, 0, params.stream, kernel_ptrs,\n params.max_tokens_per_rank, params.elements_per_token,\n stride_per_token, params.local_num_tokens, params.ep_rank,\n params.ep_size, params.enable_pdl, params.output_scalar_scale);\n });\n });\n });\n });\n })\n}\n\n// Kernel to sanitize expert ids for invalid tokens\n__global__ void moeA2ASanitizeExpertIdsKernel(int32_t* expert_ids_ptr,\n int32_t const* recv_counters_ptr, int ep_size,\n int max_tokens_per_rank, int top_k,\n int32_t invalid_id, bool enable_pdl) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n if (enable_pdl) cudaGridDependencySynchronize();\n cudaTriggerProgrammaticLaunchCompletion();\n#endif\n int tid = blockIdx.x * blockDim.x + threadIdx.x;\n int total_tokens = ep_size * max_tokens_per_rank;\n if (tid >= total_tokens) return;\n\n int source_rank = tid / max_tokens_per_rank;\n int token_idx = tid % max_tokens_per_rank;\n\n if (token_idx >= recv_counters_ptr[source_rank]) {\n int32_t* token_expert_ids = expert_ids_ptr + tid * top_k;\n for (int k = 0; k < top_k; ++k) {\n token_expert_ids[k] = invalid_id;\n }\n }\n}\n\nvoid moe_a2a_sanitize_expert_ids_launch(int32_t* expert_ids, int32_t const* recv_counters,\n int32_t invalid_id, int ep_size, int max_tokens_per_rank,\n int top_k, cudaStream_t stream, bool enable_pdl) {\n constexpr int kBlockSize = 256;\n int total_tokens = ep_size * max_tokens_per_rank;\n int grid = ceilDiv(total_tokens, kBlockSize);\n launchWithPdlWhenEnabled(\"moeA2ASanitizeExpertIdsKernel\", enable_pdl,\n moeA2ASanitizeExpertIdsKernel, grid, kBlockSize, 0, stream, expert_ids,\n recv_counters, ep_size, max_tokens_per_rank, top_k, invalid_id,\n enable_pdl);\n}\n\n} // namespace tensorrt_llm::kernels::moe_alltoall\n"},"after_code":{"kind":"string","value":"/*\n * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include <cooperative_groups.h>\n#include <cuda_fp8.h>\n\n#include <cstdint>\n#include <type_traits>\n\n#include \"flashinfer/exception.h\"\n#include \"flashinfer/utils.cuh\"\n#include \"flashinfer/vec_dtypes.cuh\"\n#include \"tensorrt_llm/common/dataType.h\"\n#include \"tensorrt_llm/common/envUtils.h\"\n#include \"tensorrt_llm/kernels/communicationKernels/moeAlltoAllKernels.h\"\n#include \"tensorrt_llm/kernels/quantization_utils.cuh\"\n\nnamespace tensorrt_llm::kernels::moe_alltoall {\n\nusing tensorrt_llm::common::launchWithPdlWhenEnabled;\n\n#define ENABLE_DEBUG_PRINT 0\n#define DISABLE_SYNC_FOR_PROFILING 0\n\nconstexpr int kEp4Size = 4;\n// Two 32-thread warps can cover at most 64 16-byte activation vectors.\nconstexpr int kCompactDispatchMaxPayloadBytes = 1024;\nconstexpr int kCompactDispatchBlockSize = 128;\nconstexpr int kDispatchWarpSize = 32;\nconstexpr int kDispatchActivationWarps = 2;\nconstexpr int kDispatchWideVectorBytes = 16;\nconstexpr int kDispatchMetadataVectorBytes = 8;\nconstexpr int kDispatchHalfWarpSize = 16;\nconstexpr int kNvfp4ActivationToScaleRatio = 8;\nconstexpr int kNvfp4H2048ActivationBytes = 2048 / 2;\nconstexpr int kNvfp4H2048ScaleBytes = 2048 / 16;\nconstexpr int kTopK22MetadataBytes = 22 * sizeof(int32_t);\nconstexpr int kNvfp4H2048ActivationWorkers = kNvfp4H2048ActivationBytes / kDispatchWideVectorBytes;\nconstexpr int kNvfp4H2048ScaleWorkers = kNvfp4H2048ScaleBytes / kDispatchWideVectorBytes;\nconstexpr int kTopK22MetadataWorkers = kTopK22MetadataBytes / kDispatchMetadataVectorBytes;\nstatic_assert(kCompactDispatchMaxPayloadBytes % kDispatchWideVectorBytes == 0);\nstatic_assert(kCompactDispatchMaxPayloadBytes / kDispatchWideVectorBytes <=\n kDispatchActivationWarps * kDispatchWarpSize);\nstatic_assert(kCompactDispatchBlockSize == (kDispatchActivationWarps + 2) * kDispatchWarpSize);\n\n#ifndef DISABLE_TIMEOUT\n#define DISABLE_TIMEOUT 0\n#endif\n\n// Helper function for ceiling division\ntemplate <typename T>\n__host__ __device__ inline T ceilDiv(T m, T n) {\n return (m + n - 1) / n;\n}\n\n// The phased schedule reserves two warps for packed activations, one for scales,\n// and splits the last warp between the two routing-metadata payloads. The\n// activation cap intentionally limits this path to hidden sizes up to 2048.\nstatic bool isPhasedNvfp4PayloadLayout(DispatchKernelPointers const& ptrs, int num_payloads,\n int top_k) {\n if (num_payloads != 4 || top_k <= kEp4Size) {\n return false;\n }\n\n int const activation_bytes = ptrs.payload_bytes_per_token[0];\n int const scale_bytes = ptrs.payload_bytes_per_token[1];\n int const metadata_bytes = top_k * static_cast<int>(sizeof(int32_t));\n // Smaller top-k layouts support runtime activation widths (including H1024).\n // Top-k 22 is restricted to the measured H2048 configuration.\n bool const validated_top_k_layout = top_k < 22 || activation_bytes == kNvfp4H2048ActivationBytes;\n return validated_top_k_layout && activation_bytes > 0 &&\n activation_bytes <= kCompactDispatchMaxPayloadBytes &&\n activation_bytes % kDispatchWideVectorBytes == 0 && scale_bytes > 0 &&\n scale_bytes % kDispatchWideVectorBytes == 0 &&\n activation_bytes == kNvfp4ActivationToScaleRatio * scale_bytes &&\n metadata_bytes % kDispatchMetadataVectorBytes == 0 &&\n metadata_bytes / kDispatchMetadataVectorBytes <= kDispatchHalfWarpSize &&\n ptrs.payload_bytes_per_token[2] == metadata_bytes &&\n ptrs.payload_bytes_per_token[3] == metadata_bytes;\n}\n\n// Macros for concise launch-time specialization\n#define SWITCH_BOOL(flag, NAME, ...) \\\n if (flag) { \\\n constexpr bool NAME = true; \\\n __VA_ARGS__ \\\n } else { \\\n constexpr bool NAME = false; \\\n __VA_ARGS__ \\\n }\n\n#define SWITCH_TOP_K(top_k, TOP_K, ...) \\\n switch (top_k) { \\\n case 22: { \\\n constexpr int TOP_K = 22; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case 18: { \\\n constexpr int TOP_K = 18; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case 16: { \\\n constexpr int TOP_K = 16; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case 14: { \\\n constexpr int TOP_K = 14; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case 12: { \\\n constexpr int TOP_K = 12; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case 10: { \\\n constexpr int TOP_K = 10; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case 8: { \\\n constexpr int TOP_K = 8; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case 6: { \\\n constexpr int TOP_K = 6; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case 4: { \\\n constexpr int TOP_K = 4; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case 2: { \\\n constexpr int TOP_K = 2; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case 1: { \\\n constexpr int TOP_K = 1; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n default: { \\\n FLASHINFER_CHECK(false, \"Unsupported top_k\"); \\\n } \\\n }\n\n#define SWITCH_DTYPE(dtype, TYPE, ...) \\\n switch (dtype) { \\\n case nvinfer1::DataType::kHALF: { \\\n using TYPE = half; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case nvinfer1::DataType::kBF16: { \\\n using TYPE = __nv_bfloat16; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case nvinfer1::DataType::kFLOAT: { \\\n using TYPE = float; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case nvinfer1::DataType::kFP8: { \\\n using TYPE = __nv_fp8_e4m3; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n default: { \\\n FLASHINFER_CHECK(false, \"Unsupported dtype for moe_a2a_combine\"); \\\n } \\\n }\n\n// Quantized combine currently only supports FP16/BF16 inputs.\n#define SWITCH_QUANT_MODE(dtype, quant_mode, QUANT_MODE, ...) \\\n if constexpr (std::is_same_v<dtype, half> || std::is_same_v<dtype, __nv_bfloat16>) { \\\n switch (quant_mode) { \\\n case MoeA2ACombineQuantMode::NONE: { \\\n constexpr auto QUANT_MODE = MoeA2ACombineQuantMode::NONE; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case MoeA2ACombineQuantMode::MXFP8: { \\\n constexpr auto QUANT_MODE = MoeA2ACombineQuantMode::MXFP8; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case MoeA2ACombineQuantMode::NVFP4: { \\\n constexpr auto QUANT_MODE = MoeA2ACombineQuantMode::NVFP4; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case MoeA2ACombineQuantMode::MXFP4: { \\\n constexpr auto QUANT_MODE = MoeA2ACombineQuantMode::MXFP4; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n default: { \\\n FLASHINFER_CHECK(false, \"Unsupported quant_mode for moe_a2a_combine\"); \\\n } \\\n } \\\n } else { \\\n FLASHINFER_CHECK((quant_mode) == MoeA2ACombineQuantMode::NONE, \\\n \"All to All Combine Quantization currently only supports \" \\\n \"FP16/BF16\"); \\\n constexpr auto QUANT_MODE = MoeA2ACombineQuantMode::NONE; \\\n __VA_ARGS__; \\\n }\n\n#define SWITCH_SWIZZLE_MODE(swizzle_mode, SWIZZLE_MODE, ...) \\\n switch (swizzle_mode) { \\\n case MoeA2ACombineSwizzleSFMode::LINEAR: { \\\n constexpr auto SWIZZLE_MODE = MoeA2ACombineSwizzleSFMode::LINEAR; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case MoeA2ACombineSwizzleSFMode::SWIZZLE_128x4: { \\\n constexpr auto SWIZZLE_MODE = MoeA2ACombineSwizzleSFMode::SWIZZLE_128x4; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case MoeA2ACombineSwizzleSFMode::SWIZZLE_8x4: { \\\n constexpr auto SWIZZLE_MODE = MoeA2ACombineSwizzleSFMode::SWIZZLE_8x4; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n default: { \\\n FLASHINFER_CHECK(false, \"Unsupported swizzle_mode for moe_a2a_combine\"); \\\n } \\\n }\n\n#if DISABLE_TIMEOUT\n#define check_timeout(s) false\n#else\n// 300 * 2000 MHz - should be high enough on any GPU but will prevent a hang\n#define check_timeout(s) ((clock64() - (s)) > (300ll * 2000ll * 1000ll * 1000ll))\n#endif\n\n// ============================================================================\n// Helper Functions for Expert-to-Rank Mapping\n// ============================================================================\n\n// Compute which rank owns a given expert using contiguous ceil/floor partitioning.\n// Supports non-divisible distribution when num_experts % ep_size != 0:\n// base = num_experts / ep_size\n// remainder = num_experts % ep_size\n// - Ranks [0, remainder) each own (base + 1) experts.\n// - Ranks [remainder, ep_size) each own base experts.\n//\n// Example A (uniform): 32 experts, 4 ranks -> base=8, remainder=0\n// - Rank 0: experts 0-7, Rank 1: 8-15, Rank 2: 16-23, Rank 3: 24-31\n// Example B (non-divisible): 384 experts, 5 ranks -> base=76, remainder=4\n// - Ranks 0-3: 77 experts each, Rank 4: 76 experts\n//\n// base and remainder are precomputed by the caller once outside the per-token TOP_K loop\n// so the hot path performs at most one integer divide.\n__device__ __forceinline__ int compute_target_rank_id(int expert_id, int base, int remainder) {\n // Fast path for the uniform (num_experts % ep_size == 0) case: identical to the\n // pre-ceil/floor implementation, so existing divisible deployments incur no overhead.\n if (remainder == 0) {\n return expert_id / base;\n }\n int const split = remainder * (base + 1); // boundary expert id\n if (expert_id < split) {\n // Falls inside the (base + 1)-sized prefix block.\n return expert_id / (base + 1);\n }\n // Falls inside the base-sized suffix block.\n return remainder + (expert_id - split) / base;\n}\n\n// Test bit `rank` in a kRankMaskWords-wide little-endian uint64 bitmask.\n// Word 0 covers ranks 0..63, word 1 covers ranks 64..127, etc.\n// `rank >> 6` and `rank & 63` divide / modulo by 64.\n__device__ __forceinline__ bool is_rank_active(uint64_t const* mask, int rank) {\n return (mask[rank >> 6] >> (rank & 63)) & 1ULL;\n}\n\n// ============================================================================\n// Helper Functions for Vectorized Memory Operations\n// ============================================================================\n\ntemplate <int VEC_SIZE>\n__device__ void vectorized_copy_impl(void* dst, void const* src, int size) {\n using flashinfer::vec_t;\n\n uint8_t* dst_ptr = static_cast<uint8_t*>(dst);\n uint8_t const* src_ptr = static_cast<uint8_t const*>(src);\n\n int const stride = blockDim.x * VEC_SIZE;\n\n for (int offset = threadIdx.x * VEC_SIZE; offset < size; offset += stride) {\n vec_t<uint8_t, VEC_SIZE> v;\n v.load(src_ptr + offset);\n v.store(dst_ptr + offset);\n }\n}\n\n__device__ void vectorized_copy(void* dst, void const* src, int size) {\n if (size % 16 == 0) {\n vectorized_copy_impl<16>(dst, src, size);\n } else if (size % 8 == 0) {\n vectorized_copy_impl<8>(dst, src, size);\n } else if (size % 4 == 0) {\n vectorized_copy_impl<4>(dst, src, size);\n } else if (size % 2 == 0) {\n vectorized_copy_impl<2>(dst, src, size);\n } else {\n vectorized_copy_impl<1>(dst, src, size);\n }\n}\n\n// Vectorized dispatch: load one vec from source and write to up to TOP_K destinations\ntemplate <int VEC_SIZE, int TOP_K>\n__device__ void vectorized_dispatch_impl(uint8_t const* src_ptr, int bytes_per_token, int rank_id,\n int max_tokens_per_rank, int payload_idx,\n DispatchKernelPointers const& ptrs,\n int const* topk_target_ranks, int const* topk_send_indices,\n int worker_idx, int num_workers) {\n using flashinfer::vec_t;\n\n // Precompute destination base pointers per k\n uint8_t* dst_base_k[TOP_K];\n#pragma unroll\n for (int k = 0; k < TOP_K; ++k) {\n int dst_idx_k = topk_send_indices[k];\n int target_rank_k = topk_target_ranks[k];\n if (dst_idx_k < 0) {\n dst_base_k[k] = nullptr;\n continue;\n }\n uint8_t* dst_data = static_cast<uint8_t*>(ptrs.recv_buffers[target_rank_k][payload_idx]);\n size_t base_source_rank =\n static_cast<size_t>(rank_id) * static_cast<size_t>(max_tokens_per_rank) +\n static_cast<size_t>(dst_idx_k);\n size_t base_token = base_source_rank * static_cast<size_t>(bytes_per_token);\n dst_base_k[k] = dst_data + base_token;\n }\n\n // The caller assigns a worker subset to this payload. Only those workers pay\n // the per-destination pointer setup and copy cost.\n int const stride = num_workers * VEC_SIZE;\n for (int offset = worker_idx * VEC_SIZE; offset < bytes_per_token; offset += stride) {\n vec_t<uint8_t, VEC_SIZE> v;\n v.load(src_ptr + offset);\n\n#pragma unroll\n for (int k = 0; k < TOP_K; ++k) {\n uint8_t* dst_base = dst_base_k[k];\n if (dst_base == nullptr) {\n continue;\n }\n v.store(dst_base + offset);\n }\n }\n}\n\ntemplate <int TOP_K>\n__device__ void vectorized_dispatch(uint8_t const* src_ptr, int bytes_per_token, int rank_id,\n int max_tokens_per_rank, int payload_idx,\n DispatchKernelPointers const& ptrs,\n int const* topk_target_ranks, int const* topk_send_indices) {\n if (bytes_per_token % 16 == 0) {\n vectorized_dispatch_impl<16, TOP_K>(src_ptr, bytes_per_token, rank_id, max_tokens_per_rank,\n payload_idx, ptrs, topk_target_ranks, topk_send_indices,\n threadIdx.x, blockDim.x);\n } else if (bytes_per_token % 8 == 0) {\n vectorized_dispatch_impl<8, TOP_K>(src_ptr, bytes_per_token, rank_id, max_tokens_per_rank,\n payload_idx, ptrs, topk_target_ranks, topk_send_indices,\n threadIdx.x, blockDim.x);\n } else if (bytes_per_token % 4 == 0) {\n vectorized_dispatch_impl<4, TOP_K>(src_ptr, bytes_per_token, rank_id, max_tokens_per_rank,\n payload_idx, ptrs, topk_target_ranks, topk_send_indices,\n threadIdx.x, blockDim.x);\n } else if (bytes_per_token % 2 == 0) {\n vectorized_dispatch_impl<2, TOP_K>(src_ptr, bytes_per_token, rank_id, max_tokens_per_rank,\n payload_idx, ptrs, topk_target_ranks, topk_send_indices,\n threadIdx.x, blockDim.x);\n } else {\n vectorized_dispatch_impl<1, TOP_K>(src_ptr, bytes_per_token, rank_id, max_tokens_per_rank,\n payload_idx, ptrs, topk_target_ranks, topk_send_indices,\n threadIdx.x, blockDim.x);\n }\n}\n\n__global__ void moeA2APrepareDispatchKernel(int* send_counters, int* local_token_counter,\n int ep_size, uint32_t* flag_val_ptr, bool enable_pdl) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n if (enable_pdl) cudaGridDependencySynchronize();\n cudaTriggerProgrammaticLaunchCompletion();\n#endif\n int idx = blockIdx.x * blockDim.x + threadIdx.x;\n // Zero send_counters\n if (idx < ep_size) {\n send_counters[idx] = 0;\n }\n // Zero local_token_counter and increment flag_val\n if (idx == 0) {\n *local_token_counter = 0;\n // Increment flag_val for this dispatch round\n *flag_val_ptr = *flag_val_ptr + 1;\n }\n}\n\n// ============================================================================\n// Generic Dispatch Kernel Implementation\n// One CTA processes one token and all its payloads.\n// ============================================================================\n\ntemplate <int TOP_K, bool ENABLE_EPLB, bool ENABLE_RANK_MASK, bool COMPACT_EP4,\n bool PHASE_H2048_NVFP4 = false, bool PHASE_NVFP4_PAYLOADS = false>\n__global__ void moeA2ADispatchKernel(\n int32_t const* token_selected_experts, // [local_num_tokens, TOP_K]\n const DispatchKernelPointers ptrs, // Struct containing all kernel pointers\n int num_payloads, // Number of payloads\n int max_tokens_per_rank, // Maximum tokens per rank\n int local_num_tokens, int rank_id, int ep_size, int num_experts, int eplb_stats_num_experts,\n bool enable_pdl) {\n static_assert(!COMPACT_EP4 || TOP_K > kEp4Size);\n static_assert(!PHASE_H2048_NVFP4 || TOP_K == 22);\n static_assert(!PHASE_NVFP4_PAYLOADS ||\n (TOP_K > kEp4Size && TOP_K % 2 == 0 &&\n TOP_K * static_cast<int>(sizeof(int32_t)) / kDispatchMetadataVectorBytes <=\n kDispatchHalfWarpSize));\n static_assert(!PHASE_H2048_NVFP4 || !PHASE_NVFP4_PAYLOADS);\n int thread_idx = threadIdx.x;\n int local_token_idx = blockIdx.x;\n\n if (local_num_tokens == 0) {\n // Special case: If local_num_tokens == 0,\n // we need to keep the threads where local_token_idx == 0 alive to participate in the\n // synchronization. Other threads should return.\n if (local_token_idx > 0) return;\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n if (enable_pdl) cudaGridDependencySynchronize();\n#endif\n } else {\n // Threads that do not have a token to process should return.\n if (local_token_idx >= local_num_tokens) return;\n\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n if (enable_pdl) cudaGridDependencySynchronize();\n#endif\n\n // Prepare per-policy shared-memory tiles for this token\n extern __shared__ int smem[];\n int* smem_topk_target_ranks = smem;\n int* smem_topk_send_indices = nullptr;\n int* smem_compact_send_indices = smem;\n if constexpr (!COMPACT_EP4) {\n smem_topk_send_indices = smem + TOP_K;\n }\n\n // Precompute the ceil/floor partition parameters once per thread, outside the\n // per-token TOP_K loop. The fast path (remainder == 0) then collapses to a single\n // integer divide per call, matching the pre-PR uniform-partition cost exactly.\n int const ep_base = num_experts / ep_size;\n int const ep_remainder = num_experts - ep_base * ep_size; // == num_experts % ep_size\n\n if (thread_idx < warpSize) {\n int lane_id = thread_idx;\n if constexpr (COMPACT_EP4) {\n if (lane_id < kEp4Size) {\n smem_compact_send_indices[lane_id] = -1;\n }\n __syncwarp();\n }\n\n unsigned topk_mask = __ballot_sync(0xffffffff, lane_id < TOP_K);\n if (lane_id < TOP_K) {\n int k = lane_id;\n int expert_id = token_selected_experts[local_token_idx * TOP_K + k];\n // Use contiguous ceil/floor partitioning (supports non-divisible num_experts % ep_size).\n int target_rank = compute_target_rank_id(expert_id, ep_base, ep_remainder);\n\n // Elect the first top-k lane for each destination rank; duplicate targets within a\n // token collapse to a single send (replaces the old serial already_copied bitmask).\n unsigned matching_lanes = __match_any_sync(topk_mask, target_rank);\n bool is_first = lane_id == __ffs(matching_lanes) - 1;\n\n // Dead ranks (ENABLE_RANK_MASK) are dropped the same way as duplicates: no send is\n // issued and topk_send_indices[k] stays < 0, so combine's existing skip check on that\n // sentinel handles both cases uniformly. When ENABLE_RANK_MASK is false, the dead-rank\n // check is compiled out entirely (no active_rank_mask load/branch on this hot path).\n bool is_valid = is_first;\n if constexpr (ENABLE_RANK_MASK) {\n is_valid = is_valid && is_rank_active(ptrs.active_rank_mask, target_rank);\n }\n\n int dst_token_idx = -1;\n if (is_valid) {\n dst_token_idx = atomicAdd(&ptrs.send_counters[target_rank], 1);\n if constexpr (COMPACT_EP4) {\n smem_compact_send_indices[target_rank] = dst_token_idx;\n }\n } else {\n target_rank = -1;\n }\n\n ptrs.topk_target_ranks[local_token_idx * TOP_K + k] = target_rank;\n ptrs.topk_send_indices[local_token_idx * TOP_K + k] = dst_token_idx;\n if constexpr (!COMPACT_EP4) {\n smem_topk_target_ranks[k] = target_rank;\n smem_topk_send_indices[k] = dst_token_idx;\n }\n }\n }\n // Sync before dispatching data\n __syncthreads();\n\n // EP4 has at most four unique destinations, regardless of TOP_K. The compact\n // specialization avoids expanding those destinations back to TOP_K entries.\n constexpr int NUM_DESTINATIONS = COMPACT_EP4 ? kEp4Size : TOP_K;\n int target_ranks[NUM_DESTINATIONS];\n int send_indices[NUM_DESTINATIONS];\n if constexpr (COMPACT_EP4) {\n#pragma unroll\n for (int target_rank = 0; target_rank < NUM_DESTINATIONS; ++target_rank) {\n target_ranks[target_rank] = target_rank;\n send_indices[target_rank] = smem_compact_send_indices[target_rank];\n }\n } else {\n#pragma unroll\n for (int k = 0; k < TOP_K; ++k) {\n target_ranks[k] = smem_topk_target_ranks[k];\n send_indices[k] = smem_topk_send_indices[k];\n }\n }\n\n if constexpr (PHASE_H2048_NVFP4) {\n // Keep compile-time bounds for the measured Nemotron H2048 target.\n int warp_id = thread_idx / warpSize;\n int lane_id = thread_idx % warpSize;\n if (warp_id < kDispatchActivationWarps) {\n auto const* src = static_cast<uint8_t const*>(ptrs.src_data_ptrs[0]) +\n static_cast<size_t>(local_token_idx) * kNvfp4H2048ActivationBytes;\n vectorized_dispatch_impl<16, NUM_DESTINATIONS>(\n src, kNvfp4H2048ActivationBytes, rank_id, max_tokens_per_rank, 0, ptrs, target_ranks,\n send_indices, thread_idx, kNvfp4H2048ActivationWorkers);\n } else if (warp_id == kDispatchActivationWarps && lane_id < kNvfp4H2048ScaleWorkers) {\n auto const* src = static_cast<uint8_t const*>(ptrs.src_data_ptrs[1]) +\n static_cast<size_t>(local_token_idx) * kNvfp4H2048ScaleBytes;\n vectorized_dispatch_impl<16, NUM_DESTINATIONS>(\n src, kNvfp4H2048ScaleBytes, rank_id, max_tokens_per_rank, 1, ptrs, target_ranks,\n send_indices, lane_id, kNvfp4H2048ScaleWorkers);\n } else if (warp_id == kDispatchActivationWarps + 1 && lane_id < 2 * kTopK22MetadataWorkers) {\n bool second_tail = lane_id >= kTopK22MetadataWorkers;\n int payload_idx = second_tail ? 3 : 2;\n int worker_idx = second_tail ? lane_id - kTopK22MetadataWorkers : lane_id;\n auto const* src = static_cast<uint8_t const*>(ptrs.src_data_ptrs[payload_idx]) +\n static_cast<size_t>(local_token_idx) * kTopK22MetadataBytes;\n vectorized_dispatch_impl<8, NUM_DESTINATIONS>(\n src, kTopK22MetadataBytes, rank_id, max_tokens_per_rank, payload_idx, ptrs,\n target_ranks, send_indices, worker_idx, kTopK22MetadataWorkers);\n }\n } else if constexpr (PHASE_NVFP4_PAYLOADS) {\n // Match warps to the NVFP4 payload widths instead of making all 128\n // threads materialize destination pointers for every payload.\n int const activation_bytes = ptrs.payload_bytes_per_token[0];\n int const scale_bytes = ptrs.payload_bytes_per_token[1];\n constexpr int METADATA_BYTES = TOP_K * sizeof(int32_t);\n constexpr int METADATA_WORKERS = METADATA_BYTES / kDispatchMetadataVectorBytes;\n int const activation_workers = activation_bytes / kDispatchWideVectorBytes;\n int const scale_workers = scale_bytes / kDispatchWideVectorBytes;\n int warp_id = thread_idx / warpSize;\n int lane_id = thread_idx % warpSize;\n if (warp_id < kDispatchActivationWarps && thread_idx < activation_workers) {\n auto const* src = static_cast<uint8_t const*>(ptrs.src_data_ptrs[0]) +\n static_cast<size_t>(local_token_idx) * activation_bytes;\n vectorized_dispatch_impl<kDispatchWideVectorBytes, NUM_DESTINATIONS>(\n src, activation_bytes, rank_id, max_tokens_per_rank, 0, ptrs, target_ranks,\n send_indices, thread_idx, activation_workers);\n } else if (warp_id == kDispatchActivationWarps && lane_id < scale_workers) {\n auto const* src = static_cast<uint8_t const*>(ptrs.src_data_ptrs[1]) +\n static_cast<size_t>(local_token_idx) * scale_bytes;\n vectorized_dispatch_impl<kDispatchWideVectorBytes, NUM_DESTINATIONS>(\n src, scale_bytes, rank_id, max_tokens_per_rank, 1, ptrs, target_ranks, send_indices,\n lane_id, scale_workers);\n } else if (warp_id == kDispatchActivationWarps + 1 && lane_id < 2 * METADATA_WORKERS) {\n bool second_tail = lane_id >= METADATA_WORKERS;\n int payload_idx = second_tail ? 3 : 2;\n int worker_idx = second_tail ? lane_id - METADATA_WORKERS : lane_id;\n auto const* src = static_cast<uint8_t const*>(ptrs.src_data_ptrs[payload_idx]) +\n static_cast<size_t>(local_token_idx) * METADATA_BYTES;\n vectorized_dispatch_impl<kDispatchMetadataVectorBytes, NUM_DESTINATIONS>(\n src, METADATA_BYTES, rank_id, max_tokens_per_rank, payload_idx, ptrs, target_ranks,\n send_indices, worker_idx, METADATA_WORKERS);\n }\n } else {\n // Perform a single source load and fan out to each unique destination.\n for (int payload_idx = 0; payload_idx < num_payloads; payload_idx++) {\n uint8_t const* src_data = static_cast<uint8_t const*>(ptrs.src_data_ptrs[payload_idx]);\n int bytes_per_token = ptrs.payload_bytes_per_token[payload_idx];\n uint8_t const* src_ptr = src_data + local_token_idx * bytes_per_token;\n\n vectorized_dispatch<NUM_DESTINATIONS>(src_ptr, bytes_per_token, rank_id,\n max_tokens_per_rank, payload_idx, ptrs, target_ranks,\n send_indices);\n }\n }\n\n __syncthreads();\n }\n\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n cudaTriggerProgrammaticLaunchCompletion();\n#endif\n\n bool is_first_warp = threadIdx.x / warpSize == 0;\n if (is_first_warp) {\n int lane_id = threadIdx.x % warpSize;\n\n bool is_last_token = false;\n if (lane_id == 0) {\n if (local_num_tokens != 0) {\n int cnt = atomicAdd(ptrs.local_token_counter, 1);\n is_last_token = cnt + 1 == local_num_tokens;\n } else {\n is_last_token = true;\n }\n }\n is_last_token = __shfl_sync(0xffffffff, is_last_token, 0);\n\n if (is_last_token) {\n// Store send_counters to recv_counters.\n// Skip masked target ranks: their symmetric memory may be inaccessible.\n#pragma unroll 1 // No unroll as one iter is typically enough\n for (int target_rank = lane_id; target_rank < ep_size; target_rank += warpSize) {\n if constexpr (ENABLE_RANK_MASK) {\n if (!is_rank_active(ptrs.active_rank_mask, target_rank)) continue;\n }\n int send_count = ptrs.send_counters[target_rank];\n ptrs.recv_counters[target_rank][rank_id] = send_count;\n }\n\n if constexpr (ENABLE_EPLB) {\n // Write local stats into peer buffers before the release fence below.\n // Skip masked target ranks for the same reason as above.\n#pragma unroll 1\n for (int target_rank = 0; target_rank < ep_size; ++target_rank) {\n if constexpr (ENABLE_RANK_MASK) {\n if (!is_rank_active(ptrs.active_rank_mask, target_rank)) continue;\n }\n int* target_stats = ptrs.eplb_gathered_stats[target_rank];\n for (int expert_id = lane_id; expert_id < eplb_stats_num_experts; expert_id += warpSize) {\n int stat_val = ptrs.eplb_local_stats[expert_id];\n target_stats[rank_id * eplb_stats_num_experts + expert_id] = stat_val;\n }\n }\n }\n\n#if !DISABLE_SYNC_FOR_PROFILING\n uint32_t expected_value = *ptrs.flag_val;\n\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"fence.release.sys;\");\n#else\n __threadfence_system();\n#endif\n// Signal completion to all active peers; skip dead ranks (their symmetric memory is\n// unreachable).\n#pragma unroll 1 // No unroll as one iter is typically enough\n for (int target_rank = lane_id; target_rank < ep_size; target_rank += warpSize) {\n if constexpr (ENABLE_RANK_MASK) {\n if (!is_rank_active(ptrs.active_rank_mask, target_rank)) continue;\n }\n uint32_t* flag_addr = &ptrs.completion_flags[target_rank][rank_id];\n asm volatile(\"st.relaxed.sys.u32 [%0], %1;\" ::\"l\"(flag_addr), \"r\"(expected_value));\n\n#if ENABLE_DEBUG_PRINT\n printf(\"dispatch: +++Rank %d setting completion flag to %d for rank %d\\n\", rank_id,\n expected_value, target_rank);\n#endif\n }\n\n// Wait for all active peers to signal; skip dead ranks (otherwise we would spin forever —\n// this is the bug the rank-mask is here to prevent).\n#pragma unroll 1 // No unroll\n for (int peer_rank = lane_id; peer_rank < ep_size; peer_rank += warpSize) {\n if constexpr (ENABLE_RANK_MASK) {\n if (!is_rank_active(ptrs.active_rank_mask, peer_rank)) continue;\n }\n bool flag_set = false;\n [[maybe_unused]] auto s = clock64();\n do {\n uint32_t* flag_ptr = &ptrs.completion_flags[rank_id][peer_rank];\n uint32_t flag_value;\n // Acquire load to ensure visibility of peer's release-store\n asm volatile(\"ld.relaxed.sys.u32 %0, [%1];\" : \"=r\"(flag_value) : \"l\"(flag_ptr));\n#if ENABLE_DEBUG_PRINT\n printf(\n \"dispatch: ---Rank %d received completion flag from rank %d, flag_value: %d, \"\n \"expected_value: \"\n \"%d, address: %p\\n\",\n rank_id, peer_rank, flag_value, expected_value, flag_ptr);\n#endif\n flag_set = flag_value == expected_value;\n } while (!flag_set && !check_timeout(s));\n\n if (__builtin_expect(!flag_set, 0)) {\n printf(\"dispatch: ---Rank %d timed out waiting for completion flag from rank %d\\n\",\n rank_id, peer_rank);\n asm volatile(\"trap;\");\n return;\n }\n }\n // asm volatile(\"fence.acquire.sys;\");\n#endif\n }\n }\n}\n\nvoid moe_a2a_prepare_dispatch_launch(MoeA2ADispatchParams const& params) {\n launchWithPdlWhenEnabled(\"moeA2APrepareDispatchKernel\", params.enable_pdl,\n moeA2APrepareDispatchKernel, 1, params.ep_size, 0, params.stream,\n params.send_counters, params.local_token_counter, params.ep_size,\n params.flag_val, params.enable_pdl);\n}\n\n// ============================================================================\n// Launch Functions\n// ============================================================================\n\nvoid moe_a2a_dispatch_launch(MoeA2ADispatchParams const& params) {\n // Validate parameters\n TLLM_CHECK(params.top_k > 0 && params.top_k <= kMaxTopK);\n TLLM_CHECK(params.ep_size > 0 && params.ep_size <= kMaxRanks);\n TLLM_CHECK(params.ep_rank >= 0 && params.ep_rank < params.ep_size);\n TLLM_CHECK(params.local_num_tokens >= 0);\n TLLM_CHECK(params.num_payloads > 0 && params.num_payloads <= kMaxPayloads);\n if (params.enable_rank_mask) {\n // The local rank must always be marked active in its own view of the mask; otherwise the\n // kernel itself would be running on a \"dead\" rank.\n TLLM_CHECK_WITH_INFO(\n (params.active_rank_mask[params.ep_rank >> 6] >> (params.ep_rank & 63)) & 1ULL,\n \"active_rank_mask must mark the local ep_rank (%d) as active\", params.ep_rank);\n }\n\n // Prepare kernel pointers struct\n DispatchKernelPointers kernel_ptrs = {};\n\n // Fill source data pointers and payload sizes\n for (int i = 0; i < params.num_payloads; i++) {\n kernel_ptrs.src_data_ptrs[i] = params.payloads[i].src_data;\n kernel_ptrs.payload_bytes_per_token[i] =\n params.payloads[i].element_size * params.payloads[i].elements_per_token;\n }\n\n // Fill receive buffer pointers\n for (int target_rank = 0; target_rank < params.ep_size; target_rank++) {\n kernel_ptrs.recv_counters[target_rank] = params.recv_counters[target_rank];\n kernel_ptrs.eplb_gathered_stats[target_rank] = params.eplb_gathered_stats[target_rank];\n for (int payload = 0; payload < params.num_payloads; payload++) {\n kernel_ptrs.recv_buffers[target_rank][payload] = params.recv_buffers[target_rank][payload];\n }\n }\n\n // Copy completion flag pointers\n for (int i = 0; i < params.ep_size; i++) {\n kernel_ptrs.completion_flags[i] = params.completion_flags[i];\n }\n kernel_ptrs.flag_val = params.flag_val;\n\n // Copy communication tracking pointers\n kernel_ptrs.send_counters = params.send_counters;\n kernel_ptrs.local_token_counter = params.local_token_counter;\n kernel_ptrs.topk_target_ranks = params.topk_target_ranks;\n kernel_ptrs.topk_send_indices = params.topk_send_indices;\n kernel_ptrs.eplb_local_stats = params.eplb_local_stats;\n\n // Copy active-rank bitmask into the kernel pointers struct\n for (int w = 0; w < kRankMaskWords; ++w) {\n kernel_ptrs.active_rank_mask[w] = params.active_rank_mask[w];\n }\n\n int block_size = tensorrt_llm::common::getEnvMoeA2ADispatchBlockSize();\n\n bool const use_compact_ep4 = params.ep_size == kEp4Size && params.top_k > kEp4Size;\n\n int max_payload_bytes_per_token = 0;\n for (int i = 0; i < params.num_payloads; ++i) {\n if (kernel_ptrs.payload_bytes_per_token[i] > max_payload_bytes_per_token) {\n max_payload_bytes_per_token = kernel_ptrs.payload_bytes_per_token[i];\n }\n }\n bool const supports_phased_nvfp4 =\n params.ep_size == kEp4Size || params.ep_size == 8 || params.ep_size == 16;\n bool const phased_nvfp4_layout =\n supports_phased_nvfp4 &&\n isPhasedNvfp4PayloadLayout(kernel_ptrs, params.num_payloads, params.top_k);\n\n // Small payloads do not have enough 16-byte vectors to use larger CTAs. A GB200\n // sweep found 128 threads faster than both 64 and 256 at prefill token counts.\n if ((use_compact_ep4 || phased_nvfp4_layout) &&\n max_payload_bytes_per_token <= kCompactDispatchMaxPayloadBytes &&\n block_size > kCompactDispatchBlockSize) {\n block_size = kCompactDispatchBlockSize;\n }\n bool const phase_nvfp4_payloads = phased_nvfp4_layout && block_size == kCompactDispatchBlockSize;\n\n // Configure kernel launch: one block per token\n int grid_size = params.local_num_tokens;\n // If local_num_tokens is 0, we still need to launch a minimal kernel to participate in the\n // synchronization.\n if (grid_size == 0) {\n grid_size = 1;\n }\n SWITCH_BOOL(params.enable_rank_mask, ENABLE_RANK_MASK, {\n SWITCH_BOOL(params.enable_eplb, EPLB_STATS, {\n if (phase_nvfp4_payloads && params.top_k == 22 &&\n kernel_ptrs.payload_bytes_per_token[0] == kNvfp4H2048ActivationBytes) {\n FLASHINFER_CHECK(kernel_ptrs.payload_bytes_per_token[1] == kNvfp4H2048ScaleBytes &&\n kernel_ptrs.payload_bytes_per_token[2] == kTopK22MetadataBytes &&\n kernel_ptrs.payload_bytes_per_token[3] == kTopK22MetadataBytes,\n \"Invalid H2048/top-k-22 NVFP4 dispatch payload layout\");\n if (use_compact_ep4) {\n int shared_bytes = kEp4Size * (int)sizeof(int);\n auto kernel_fn = moeA2ADispatchKernel<22, EPLB_STATS, ENABLE_RANK_MASK, true, true>;\n launchWithPdlWhenEnabled(\"moeA2ADispatchKernel\", params.enable_pdl, kernel_fn, grid_size,\n block_size, shared_bytes, params.stream,\n params.token_selected_experts, kernel_ptrs, params.num_payloads,\n params.max_tokens_per_rank, params.local_num_tokens,\n params.ep_rank, params.ep_size, params.num_experts,\n params.eplb_stats_num_experts, params.enable_pdl);\n } else {\n int shared_bytes = 2 * params.top_k * (int)sizeof(int);\n auto kernel_fn = moeA2ADispatchKernel<22, EPLB_STATS, ENABLE_RANK_MASK, false, true>;\n launchWithPdlWhenEnabled(\"moeA2ADispatchKernel\", params.enable_pdl, kernel_fn, grid_size,\n block_size, shared_bytes, params.stream,\n params.token_selected_experts, kernel_ptrs, params.num_payloads,\n params.max_tokens_per_rank, params.local_num_tokens,\n params.ep_rank, params.ep_size, params.num_experts,\n params.eplb_stats_num_experts, params.enable_pdl);\n }\n } else if (phase_nvfp4_payloads) {\n if (use_compact_ep4) {\n int shared_bytes = kEp4Size * (int)sizeof(int);\n SWITCH_TOP_K(\n params.top_k, TOP_K, if constexpr (TOP_K > kEp4Size && TOP_K % 2 == 0) {\n auto kernel_fn =\n moeA2ADispatchKernel<TOP_K, EPLB_STATS, ENABLE_RANK_MASK, true, false, true>;\n launchWithPdlWhenEnabled(\n \"moeA2ADispatchKernel\", params.enable_pdl, kernel_fn, grid_size, block_size,\n shared_bytes, params.stream, params.token_selected_experts, kernel_ptrs,\n params.num_payloads, params.max_tokens_per_rank, params.local_num_tokens,\n params.ep_rank, params.ep_size, params.num_experts,\n params.eplb_stats_num_experts, params.enable_pdl);\n })\n } else {\n int shared_bytes = 2 * params.top_k * (int)sizeof(int);\n SWITCH_TOP_K(\n params.top_k, TOP_K, if constexpr (TOP_K > kEp4Size && TOP_K % 2 == 0) {\n auto kernel_fn =\n moeA2ADispatchKernel<TOP_K, EPLB_STATS, ENABLE_RANK_MASK, false, false, true>;\n launchWithPdlWhenEnabled(\n \"moeA2ADispatchKernel\", params.enable_pdl, kernel_fn, grid_size, block_size,\n shared_bytes, params.stream, params.token_selected_experts, kernel_ptrs,\n params.num_payloads, params.max_tokens_per_rank, params.local_num_tokens,\n params.ep_rank, params.ep_size, params.num_experts,\n params.eplb_stats_num_experts, params.enable_pdl);\n })\n }\n } else if (use_compact_ep4) {\n int shared_bytes = kEp4Size * (int)sizeof(int);\n SWITCH_TOP_K(\n params.top_k, TOP_K, if constexpr (TOP_K > kEp4Size) {\n auto kernel_fn = moeA2ADispatchKernel<TOP_K, EPLB_STATS, ENABLE_RANK_MASK, true>;\n launchWithPdlWhenEnabled(\n \"moeA2ADispatchKernel\", params.enable_pdl, kernel_fn, grid_size, block_size,\n shared_bytes, params.stream, params.token_selected_experts, kernel_ptrs,\n params.num_payloads, params.max_tokens_per_rank, params.local_num_tokens,\n params.ep_rank, params.ep_size, params.num_experts, params.eplb_stats_num_experts,\n params.enable_pdl);\n })\n } else {\n int shared_bytes = 2 * params.top_k * (int)sizeof(int);\n SWITCH_TOP_K(params.top_k, TOP_K, {\n auto kernel_fn = moeA2ADispatchKernel<TOP_K, EPLB_STATS, ENABLE_RANK_MASK, false>;\n launchWithPdlWhenEnabled(\"moeA2ADispatchKernel\", params.enable_pdl, kernel_fn, grid_size,\n block_size, shared_bytes, params.stream,\n params.token_selected_experts, kernel_ptrs, params.num_payloads,\n params.max_tokens_per_rank, params.local_num_tokens,\n params.ep_rank, params.ep_size, params.num_experts,\n params.eplb_stats_num_experts, params.enable_pdl);\n });\n }\n });\n })\n}\n\n// ============================================================================\n// Combine kernels\n// ============================================================================\n\n// Accumulate across all valid ranks into float32 registers, then store as T (QuantMode==NONE)\n// or quantize the result to MXFP8 with a per-block scale factor (QuantMode==MXFP8).\n//\n// InT: input element type in the recv buffer (defaults to T for same-type accumulation;\n// __nv_fp8_e4m3 for the low-precision combine path). sizeof(InT) must divide VEC_SIZE_BYTES.\n// T: output / accumulation-cast element type (and the input type when InT == T).\n//\n// Unified path: load VEC_SIZE_BYTES bytes, reinterpret as InT[elems_per_vec], accumulate as\n// float32, then either cast_store as T (NONE) or convert to MXFP8 + emit the block scale factor\n// (MXFP8, which always uses InT == T). Block-per-token indexing\n// (threadIdx.x/blockDim.x/blockIdx.x).\ntemplate <int VEC_SIZE_BYTES, int TOP_K, typename T, typename InT = T,\n MoeA2ACombineQuantMode QuantMode = MoeA2ACombineQuantMode::NONE,\n MoeA2ACombineSwizzleSFMode SwizzleMode = MoeA2ACombineSwizzleSFMode::LINEAR>\n__device__ void vectorized_combine_impl(void* output_buffer, void* sf_output, int row_idx,\n int row_size, int stride_per_token, int rank_id,\n int max_tokens_per_rank, CombineKernelPointers const& ptrs,\n float OutputScalarScale = 1.0f) {\n using flashinfer::vec_t;\n\n // elems_per_vec: number of InT elements per VEC_SIZE_BYTES-byte load (constexpr).\n constexpr int elems_per_vec = VEC_SIZE_BYTES / static_cast<int>(sizeof(InT));\n // size_per_token: byte span of one token in the recv buffer (InT-typed).\n const int size_per_token = row_size * static_cast<int>(sizeof(InT));\n\n // Output base pointers. NONE writes T elements; MXFP8 writes packed fp8 bytes.\n T* dst_typed_base = nullptr;\n uint8_t* dst_bytes = nullptr;\n if constexpr (QuantMode == MoeA2ACombineQuantMode::NONE) {\n dst_typed_base = static_cast<T*>(output_buffer) + static_cast<size_t>(row_idx) * row_size;\n } else {\n // MXFP8 stores one byte per logical element; FP4 packs two e2m1 values per byte, so its\n // rows are half as wide. The accumulation still reads InT-sized inputs either way.\n size_t const bytes_per_row = QuantMode == MoeA2ACombineQuantMode::MXFP8\n ? static_cast<size_t>(row_size)\n : static_cast<size_t>(row_size) / 2;\n dst_bytes = static_cast<uint8_t*>(output_buffer) + static_cast<size_t>(row_idx) * bytes_per_row;\n }\n\n int const stride = blockDim.x * VEC_SIZE_BYTES;\n int const local_token_idx = blockIdx.x;\n\n // offset is a byte offset into the recv buffer, stepping by VEC_SIZE_BYTES bytes.\n for (int offset = threadIdx.x * VEC_SIZE_BYTES; offset < size_per_token; offset += stride) {\n int logical_offset = offset / static_cast<int>(sizeof(InT));\n // Per-k vec_t<float, elems_per_vec> accumulators, zero-initialised via fill().\n vec_t<float, elems_per_vec> acc[TOP_K];\n\n // Pass 1: issue all TOP_K loads back-to-back without any type conversion.\n // Raw InT bytes are loaded directly into acc[k]'s register storage, reinterpreted as\n // vec_t<InT, elems_per_vec> (VEC_SIZE_BYTES bytes, fitting in the low end of acc[k]'s\n // sizeof(float)*elems_per_vec allocation). Separating load from cast lets the compiler\n // schedule all VEC_SIZE_BYTES-byte global loads consecutively, hiding memory latency across k.\n#pragma unroll\n for (int k = 0; k < TOP_K; ++k) {\n int target_rank = ptrs.topk_target_ranks[local_token_idx * TOP_K + k];\n int dst_idx = ptrs.topk_send_indices[local_token_idx * TOP_K + k];\n // dst_idx < 0: duplicate/dead-target sentinel already set by dispatch (which consults\n // active_rank_mask once per token). Rechecking is_rank_active here is redundant and,\n // being on the per-k vectorized hot path, measurably regresses combine throughput.\n if (dst_idx < 0) {\n acc[k].fill(0.0f);\n continue;\n }\n\n uint8_t const* recv_buffer = static_cast<uint8_t const*>(ptrs.recv_buffers[target_rank][0]);\n size_t base_source_rank =\n static_cast<size_t>(rank_id) * static_cast<size_t>(max_tokens_per_rank) +\n static_cast<size_t>(dst_idx);\n // stride_per_token: byte distance between tokens in the recv buffer.\n // Equals size_per_token for normal cases; may differ for FP8 in-place\n // (BF16-stride workspace but FP8-sized payload).\n size_t base_token = base_source_rank * static_cast<size_t>(stride_per_token);\n\n reinterpret_cast<vec_t<InT, elems_per_vec>&>(acc[k]).load(\n reinterpret_cast<InT const*>(recv_buffer + base_token + offset));\n }\n\n // Pass 2: in-place cast InT → float, iterating j in descending order.\n // float[j] occupies bytes [j*4, j*4+3]; InT[j] occupies [j*sizeof(InT), ...).\n // For sizeof(InT) < sizeof(float), high-j float writes land above all remaining\n // InT bytes, so descending order is always write-after-read safe.\n#pragma unroll\n for (int k = 0; k < TOP_K; ++k) {\n if (ptrs.topk_send_indices[local_token_idx * TOP_K + k] < 0)\n continue; // acc[k] already holds 0.0f from fill() above\n#pragma unroll\n for (int j = elems_per_vec - 1; j >= 0; --j)\n acc[k][j] = static_cast<float>(reinterpret_cast<InT const*>(&acc[k])[j]);\n }\n // Reduce acc[TOP_K] into acc[0] via unrolled tree-reduction.\n // acc[k][j] uses vec_t::operator[] which returns float& — no indirection overhead.\n if constexpr (TOP_K == 22) {\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[1][j];\n acc[2][j] += acc[3][j];\n acc[4][j] += acc[5][j];\n acc[6][j] += acc[7][j];\n acc[8][j] += acc[9][j];\n acc[10][j] += acc[11][j];\n acc[12][j] += acc[13][j];\n acc[14][j] += acc[15][j];\n acc[16][j] += acc[17][j];\n acc[18][j] += acc[19][j];\n acc[20][j] += acc[21][j];\n }\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[2][j];\n acc[4][j] += acc[6][j];\n acc[8][j] += acc[10][j];\n acc[12][j] += acc[14][j];\n acc[16][j] += acc[18][j];\n }\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[4][j];\n acc[8][j] += acc[12][j];\n acc[16][j] += acc[20][j];\n }\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[8][j];\n acc[0][j] += acc[16][j];\n }\n } else if constexpr (TOP_K == 16) {\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[1][j];\n acc[2][j] += acc[3][j];\n acc[4][j] += acc[5][j];\n acc[6][j] += acc[7][j];\n acc[8][j] += acc[9][j];\n acc[10][j] += acc[11][j];\n acc[12][j] += acc[13][j];\n acc[14][j] += acc[15][j];\n }\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[2][j];\n acc[4][j] += acc[6][j];\n acc[8][j] += acc[10][j];\n acc[12][j] += acc[14][j];\n }\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[4][j];\n acc[8][j] += acc[12][j];\n }\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[8][j];\n }\n } else if constexpr (TOP_K == 10) {\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[1][j];\n acc[2][j] += acc[3][j];\n acc[4][j] += acc[5][j];\n acc[6][j] += acc[7][j];\n acc[8][j] += acc[9][j];\n }\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[2][j];\n acc[4][j] += acc[6][j];\n }\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[4][j];\n acc[0][j] += acc[8][j];\n }\n } else if constexpr (TOP_K == 8) {\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[1][j];\n acc[2][j] += acc[3][j];\n acc[4][j] += acc[5][j];\n acc[6][j] += acc[7][j];\n }\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[2][j];\n acc[4][j] += acc[6][j];\n }\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[4][j];\n }\n } else if constexpr (TOP_K == 6) {\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[1][j];\n acc[2][j] += acc[3][j];\n acc[4][j] += acc[5][j];\n }\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[2][j];\n acc[0][j] += acc[4][j];\n }\n } else if constexpr (TOP_K == 4) {\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[1][j];\n acc[2][j] += acc[3][j];\n }\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[2][j];\n }\n } else if constexpr (TOP_K == 2) {\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[1][j];\n }\n } else if constexpr (TOP_K == 1) {\n // nothing to do\n } else {\n // Generic fallback: accumulate all into acc[0]\n#pragma unroll\n for (int k = 1; k < TOP_K; ++k) {\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[k][j];\n }\n }\n }\n // Epilogue: store the float accumulator as T (NONE) or quantize to MXFP8 + scale factor.\n if constexpr (QuantMode == MoeA2ACombineQuantMode::NONE) {\n // cast_store: converts float->T element-by-element then writes via vectorized int4 store.\n acc[0].cast_store(dst_typed_base + offset / static_cast<int>(sizeof(InT)));\n } else {\n constexpr uint32_t sf_vec_size = QuantMode == MoeA2ACombineQuantMode::NVFP4 ? 16 : 32;\n constexpr uint32_t threads_per_sf = sf_vec_size / elems_per_vec;\n uint8_t scale;\n auto store_sf = [&]() {\n int64_t sf_offset;\n const int64_t num_vecs_per_row = (row_size + sf_vec_size - 1) / sf_vec_size;\n const int64_t sf_idx = logical_offset / sf_vec_size;\n if constexpr (SwizzleMode == MoeA2ACombineSwizzleSFMode::LINEAR) {\n sf_offset = row_idx * num_vecs_per_row + sf_idx;\n } else if constexpr (SwizzleMode == MoeA2ACombineSwizzleSFMode::SWIZZLE_128x4) {\n sf_offset = get_sf_out_offset_128x4(row_idx, sf_idx, num_vecs_per_row);\n } else { // SWIZZLE_8x4\n sf_offset = get_sf_out_offset_8x4(row_idx, sf_idx, num_vecs_per_row);\n }\n if (threadIdx.x % threads_per_sf == 0) {\n reinterpret_cast<uint8_t*>(sf_output)[sf_offset] = scale;\n }\n };\n // Cast the float32 accumulator down to T to feed the MXFP8/FP4 converter's PackedVec input.\n tensorrt_llm::kernels::PackedVec<T, elems_per_vec> packed_vec;\n T* packed_elems = reinterpret_cast<T*>(&packed_vec);\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n packed_elems[j] = static_cast<T>(acc[0][j]);\n }\n if constexpr (QuantMode == MoeA2ACombineQuantMode::MXFP8) {\n static_assert(elems_per_vec == 8, \"MXFP8 quantization requires 8 elements per vector\");\n uint64_t fp8x8 =\n tensorrt_llm::kernels::cvt_warp_fp16_to_mxfp8<T, 32, elems_per_vec>(packed_vec, &scale);\n reinterpret_cast<uint64_t*>(dst_bytes)[logical_offset / elems_per_vec] = fp8x8;\n } else if constexpr (QuantMode == MoeA2ACombineQuantMode::NVFP4 ||\n QuantMode == MoeA2ACombineQuantMode::MXFP4) {\n static_assert(elems_per_vec == 8 || elems_per_vec == 16,\n \"FP4 quantization requires 8 or 16 elements per vector\");\n constexpr int SF_VEC_SIZE = QuantMode == MoeA2ACombineQuantMode::MXFP4 ? 32 : 16;\n auto fp4_packed = tensorrt_llm::kernels::cvt_warp_fp16_to_fp4 < T, SF_VEC_SIZE,\n elems_per_vec,\n QuantMode == MoeA2ACombineQuantMode::MXFP4 > (packed_vec, OutputScalarScale, &scale);\n // cvt_warp_fp16_to_fp4 returns uint32_t for 8 elems (4 packed bytes) and uint64_t for 16\n // (8 packed bytes); store at the matching width so packed rows stay contiguous and fit the\n // dim/2-byte output buffer (a wider store would overflow into the next token's row).\n reinterpret_cast<decltype(fp4_packed)*>(dst_bytes)[logical_offset / elems_per_vec] =\n fp4_packed;\n }\n store_sf();\n }\n }\n}\n\n// Wrapper that selects vector width based on size_per_token alignment.\n// QuantMode==NONE writes T (optionally upcast from an fp8 InT); QuantMode==MXFP8 writes packed\n// fp8 + scale factors (always InT == T, fixed 16-byte / 8-element vectors).\n// stride_per_token: byte distance between tokens in the recv buffer (may differ from\n// size_per_token when FP8 in-place uses a BF16-stride workspace with an FP8-sized payload).\n// InT: input element type in recv buffer (defaults to T for same-type accumulation).\ntemplate <int TOP_K, typename T, typename InT = T,\n MoeA2ACombineQuantMode QuantMode = MoeA2ACombineQuantMode::NONE,\n MoeA2ACombineSwizzleSFMode SwizzleMode = MoeA2ACombineSwizzleSFMode::LINEAR>\n__device__ void vectorized_combine(void* output_buffer, void* sf_output, int row_idx, int row_size,\n int stride_per_token, int rank_id, int max_tokens_per_rank,\n CombineKernelPointers const& ptrs,\n float OutputScalarScale = 1.0f) {\n const int size_per_token = row_size * static_cast<int>(sizeof(InT));\n if constexpr (QuantMode != MoeA2ACombineQuantMode::NONE) {\n // MXFP8/FP4 require 16-byte vectors (8 or 16 elements per vec), always InT == T.\n vectorized_combine_impl<16, TOP_K, T, InT, QuantMode, SwizzleMode>(\n output_buffer, sf_output, row_idx, row_size, stride_per_token, rank_id, max_tokens_per_rank,\n ptrs, OutputScalarScale);\n } else {\n // Each branch is guarded by if constexpr (sizeof(InT) <= VEC_SIZE_BYTES) so the compiler\n // never instantiates vectorized_combine_impl with elems_per_vec == 0.\n if (size_per_token % 16 == 0) {\n if constexpr (static_cast<int>(sizeof(InT)) <= 16)\n vectorized_combine_impl<16, TOP_K, T, InT>(output_buffer, nullptr, row_idx, row_size,\n stride_per_token, rank_id, max_tokens_per_rank,\n ptrs);\n } else if (size_per_token % 8 == 0) {\n if constexpr (static_cast<int>(sizeof(InT)) <= 8)\n vectorized_combine_impl<8, TOP_K, T, InT>(output_buffer, nullptr, row_idx, row_size,\n stride_per_token, rank_id, max_tokens_per_rank,\n ptrs);\n } else if (size_per_token % 4 == 0) {\n if constexpr (static_cast<int>(sizeof(InT)) <= 4)\n vectorized_combine_impl<4, TOP_K, T, InT>(output_buffer, nullptr, row_idx, row_size,\n stride_per_token, rank_id, max_tokens_per_rank,\n ptrs);\n } else if (size_per_token % 2 == 0) {\n if constexpr (static_cast<int>(sizeof(InT)) <= 2)\n vectorized_combine_impl<2, TOP_K, T, InT>(output_buffer, nullptr, row_idx, row_size,\n stride_per_token, rank_id, max_tokens_per_rank,\n ptrs);\n } else {\n if constexpr (static_cast<int>(sizeof(InT)) <= 1)\n vectorized_combine_impl<1, TOP_K, T, InT>(output_buffer, nullptr, row_idx, row_size,\n stride_per_token, rank_id, max_tokens_per_rank,\n ptrs);\n }\n }\n}\n\n// ---- vec_convert: per-vector type conversion, specialized by PTX where available ----\n// Generic: SrcT -> float -> DstT (all architectures, all type combinations).\ntemplate <size_t VEC_SIZE, typename SrcT, typename DstT>\n__device__ __forceinline__ void vec_convert(flashinfer::vec_t<DstT, VEC_SIZE>& out,\n flashinfer::vec_t<SrcT, VEC_SIZE> const& in) {\n#pragma unroll\n for (int j = 0; j < VEC_SIZE; ++j) out[j] = DstT(static_cast<float>(in[j]));\n}\n\n// BF16 -> FP8 e4m3: use CUDA intrinsic (SM100+, Blackwell).\n// Inline PTX \"cvt.rn.satfinite.e4m3x2.bf16x2 %h, %r\" is rejected by SM100a ptxas\n// (\"Unexpected instruction types for cvt\") because SM100a requires a 32-bit output\n// register for this instruction. __nv_fp8x2_e4m3(bfloat162) emits the correct form.\n#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)\ntemplate <size_t VEC_SIZE, std::enable_if_t<(VEC_SIZE % 2 == 0), int> = 0>\n__device__ __forceinline__ void vec_convert(flashinfer::vec_t<__nv_fp8_e4m3, VEC_SIZE>& out,\n flashinfer::vec_t<__nv_bfloat16, VEC_SIZE> const& in) {\n __nv_fp8x2_e4m3* out_fp8x2 = reinterpret_cast<__nv_fp8x2_e4m3*>(&out);\n __nv_bfloat162 const* in_bf16x2 = reinterpret_cast<__nv_bfloat162 const*>(&in);\n#pragma unroll\n for (int p = 0; p < static_cast<int>(VEC_SIZE) / 2; ++p)\n out_fp8x2[p] = __nv_fp8x2_e4m3(in_bf16x2[p]);\n}\n#endif\n\n// FP16 -> FP8 e4m3: paired PTX cvt.rn.satfinite.e4m3x2.f16x2 (SM89+, Hopper).\n#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 890)\ntemplate <size_t VEC_SIZE, std::enable_if_t<(VEC_SIZE % 2 == 0), int> = 0>\n__device__ __forceinline__ void vec_convert(flashinfer::vec_t<__nv_fp8_e4m3, VEC_SIZE>& out,\n flashinfer::vec_t<half, VEC_SIZE> const& in) {\n uint32_t const* src_u32 = reinterpret_cast<uint32_t const*>(&in);\n uint16_t* dst_u16 = reinterpret_cast<uint16_t*>(&out);\n#pragma unroll\n for (int p = 0; p < VEC_SIZE / 2; ++p) {\n uint16_t d;\n asm volatile(\"cvt.rn.satfinite.e4m3x2.f16x2 %0, %1;\" : \"=h\"(d) : \"r\"(src_u32[p]));\n dst_u16[p] = d;\n }\n}\n#endif\n\n// ---- vectorized_quant_impl: load -> sync -> convert -> store ----\n// VEC_SIZE is in elements (not bytes), so both SrcT and DstT vectors hold VEC_SIZE values.\n// Block-per-token: threadIdx.x indexes vectors within the token, blockDim.x is the stride.\ntemplate <int VEC_SIZE, typename SrcT, typename DstT>\n__device__ void vectorized_quant_impl(DstT* dst, SrcT const* src, int num_elements) {\n using flashinfer::vec_t;\n\n // num_elements is a multiple of VEC_SIZE here (selected by the wrapper).\n int const num_vecs = num_elements / VEC_SIZE;\n // Round the iteration bound up to a multiple of blockDim.x so every thread reaches the\n // __syncthreads() the same number of times (a divergent barrier would deadlock when\n // num_vecs is not a multiple of blockDim.x, e.g. hidden=7168 with 256 threads).\n int const vec_iters = ((num_vecs + blockDim.x - 1) / blockDim.x) * blockDim.x;\n\n for (int iter = threadIdx.x; iter < vec_iters; iter += blockDim.x) {\n bool const active = iter < num_vecs;\n int const e = iter * VEC_SIZE;\n vec_t<SrcT, VEC_SIZE> in_vec;\n if (active) in_vec.load(src + e);\n\n // Sync so all threads finish loading inputs before any thread writes output. This avoids\n // write-after-read hazards in the FP8 in-place case where this kernel's output is read as\n // input on the next iteration. All threads participate (active guards the work, not the sync).\n __syncthreads();\n\n if (active) {\n vec_t<DstT, VEC_SIZE> out_vec;\n vec_convert(out_vec, in_vec);\n out_vec.store(dst + e);\n }\n }\n}\n\ntemplate <typename SrcT, typename DstT>\n__device__ void vectorized_quant(DstT* dst, SrcT const* src, int num_elements) {\n if (num_elements % 16 == 0)\n vectorized_quant_impl<16, SrcT, DstT>(dst, src, num_elements);\n else if (num_elements % 8 == 0)\n vectorized_quant_impl<8, SrcT, DstT>(dst, src, num_elements);\n else if (num_elements % 4 == 0)\n vectorized_quant_impl<4, SrcT, DstT>(dst, src, num_elements);\n else if (num_elements % 2 == 0)\n vectorized_quant_impl<2, SrcT, DstT>(dst, src, num_elements);\n else\n vectorized_quant_impl<1, SrcT, DstT>(dst, src, num_elements);\n}\n\n// LOW_PRECISION=false: vectorized byte-copy (SrcT = payload dtype).\n// LOW_PRECISION=true: vectorized SrcT->FP8 quantization via vectorized_quant<SrcT, fp8_e4m3>.\n// stride_per_token: byte distance between tokens in recv_buffer_bytes (host-computed, avoids\n// per-thread recomputation):\n// - FP8 external payload: elements_per_token x 1 (compact FP8 layout)\n// - FP8 in-place / byte-copy: elements_per_token x sizeof(SrcT) (payload-dtype stride)\n// Copy payload to recv buffer; one block per token.\ntemplate <bool LOW_PRECISION, typename SrcT>\n__global__ void moeA2APrepareCombineKernel(uint8_t* recv_buffer_bytes, void const* payload,\n int elements_per_token, int ep_size,\n int max_tokens_per_rank, uint32_t* flag_val_ptr,\n int const* recv_counters, int stride_per_token,\n bool enable_pdl) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n if (enable_pdl) cudaGridDependencySynchronize();\n cudaTriggerProgrammaticLaunchCompletion();\n#endif\n\n if (blockIdx.x == 0 && threadIdx.x == 0) {\n // Increment flag_val for this combine round\n *flag_val_ptr = *flag_val_ptr + 1;\n }\n\n // Copy path: null payload means data is already in workspace — nothing to do.\n if (!LOW_PRECISION && payload == nullptr) return;\n\n int global_token_idx = blockIdx.x;\n\n int global_token_num = ep_size * max_tokens_per_rank;\n if (global_token_idx >= global_token_num) return;\n\n // Map global_token_idx to (rank_idx, local_token_idx)\n int rank_idx = global_token_idx / max_tokens_per_rank;\n int local_token_idx = global_token_idx % max_tokens_per_rank;\n\n // Skip invalid tokens beyond per-rank recv count\n if (local_token_idx >= recv_counters[rank_idx]) return;\n\n size_t const token_offset = static_cast<size_t>(global_token_idx) * stride_per_token;\n\n if constexpr (LOW_PRECISION) {\n // Source pointer: external payload or in-place from workspace.\n SrcT const* src_ptr = (payload != nullptr)\n ? static_cast<SrcT const*>(payload) +\n static_cast<size_t>(global_token_idx) * elements_per_token\n : reinterpret_cast<SrcT const*>(recv_buffer_bytes + token_offset);\n\n // Destination: stride_per_token encodes the correct layout for both paths\n // (compact FP8 for external, payload-dtype stride for in-place).\n __nv_fp8_e4m3* dst_ptr = reinterpret_cast<__nv_fp8_e4m3*>(recv_buffer_bytes + token_offset);\n\n vectorized_quant<SrcT, __nv_fp8_e4m3>(dst_ptr, src_ptr, elements_per_token);\n } else {\n // Generic byte copy (payload guaranteed non-null by early return above).\n vectorized_copy(recv_buffer_bytes + token_offset,\n static_cast<uint8_t const*>(payload) + token_offset, stride_per_token);\n }\n}\n\n// ============================================================================\n// Generic Combine Kernel Implementation (Templated by data type)\n// ============================================================================\n\ntemplate <typename T, int TOP_K, bool ENABLE_RANK_MASK,\n MoeA2ACombineQuantMode QuantMode = MoeA2ACombineQuantMode::NONE,\n MoeA2ACombineSwizzleSFMode SwizzleMode = MoeA2ACombineSwizzleSFMode::LINEAR>\n__global__ void moeA2ACombineKernel(\n const CombineKernelPointers ptrs, // Combine-specific struct, src_data_ptrs[0] is output\n int max_tokens_per_rank, int elements_per_token, int stride_per_token, int local_num_tokens,\n int rank_id, int ep_size, bool enable_pdl, float OutputScalarScale) {\n int local_token_idx = blockIdx.x;\n\n if (local_num_tokens == 0) {\n // Special case: If local_num_tokens == 0,\n // we need to keep the threads where local_token_idx == 0 alive to participate in the\n // synchronization. Other threads should return.\n if (local_token_idx > 0) return;\n } else {\n // Threads that do not have a token to process should return.\n if (local_token_idx >= local_num_tokens) return;\n }\n\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n if (enable_pdl) cudaGridDependencySynchronize();\n#endif\n\n#if !DISABLE_SYNC_FOR_PROFILING\n // In-kernel readiness synchronization at start of combine:\n // - One warp signals readiness to all peers with current flag_val.\n // - The first warp of each block waits for all peers' readiness (equality), then __syncthreads.\n bool is_first_warp = threadIdx.x / warpSize == 0;\n if (is_first_warp) {\n int lane_id = threadIdx.x % warpSize;\n uint32_t expected_value = *ptrs.flag_val;\n\n if (blockIdx.x == 0) {\n // asm volatile(\"fence.release.sys;\");\n // Signal readiness to all active peers; skip dead ranks (their symmetric memory is\n // unreachable).\n#pragma unroll 1 // No unroll\n for (int peer_rank = lane_id; peer_rank < ep_size; peer_rank += warpSize) {\n if constexpr (ENABLE_RANK_MASK) {\n if (!is_rank_active(ptrs.active_rank_mask, peer_rank)) continue;\n }\n uint32_t* flag_addr = &ptrs.completion_flags[peer_rank][rank_id];\n asm volatile(\"st.relaxed.sys.u32 [%0], %1;\" ::\"l\"(flag_addr), \"r\"(expected_value));\n#if ENABLE_DEBUG_PRINT\n printf(\"combine: +++Rank %d setting completion flag to %d for rank %d\\n\", rank_id,\n expected_value, peer_rank);\n#endif\n }\n }\n\n// Wait for all active peers to signal; skip dead ranks (otherwise we would spin forever —\n// this is the bug the rank-mask is here to prevent).\n#pragma unroll 1 // No unroll\n for (int peer_rank = lane_id; peer_rank < ep_size; peer_rank += warpSize) {\n if constexpr (ENABLE_RANK_MASK) {\n if (!is_rank_active(ptrs.active_rank_mask, peer_rank)) continue;\n }\n bool flag_set = false;\n [[maybe_unused]] auto s = clock64();\n do {\n uint32_t* flag_ptr = &ptrs.completion_flags[rank_id][peer_rank];\n uint32_t flag_value;\n // Acquire load to ensure visibility of peer's release-store\n asm volatile(\"ld.relaxed.sys.u32 %0, [%1];\" : \"=r\"(flag_value) : \"l\"(flag_ptr));\n#if ENABLE_DEBUG_PRINT\n printf(\n \"combine: ---Rank %d received completion flag from rank %d, flag_value: %d, \"\n \"expected_value: %d, \"\n \"address: %p\\n\",\n rank_id, peer_rank, flag_value, expected_value, flag_ptr);\n#endif\n flag_set = flag_value == expected_value;\n } while (!flag_set && !check_timeout(s));\n\n if (__builtin_expect(!flag_set, 0)) {\n printf(\"combine: ---Rank %d timed out waiting for completion flag from rank %d\\n\", rank_id,\n peer_rank);\n asm volatile(\"trap;\");\n return;\n }\n }\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"fence.acquire.sys;\");\n#else\n __threadfence_system();\n#endif\n }\n __syncthreads();\n#endif\n\n if (local_num_tokens == 0) return;\n\n // Dispatch the combine path:\n // - T == fp8_e4m3: low-precision combine, FP8 recv buffer -> BF16 output (InT=fp8, NONE quant).\n // - otherwise: same-type accumulate, then store as T (NONE) or quantize to MXFP8/FP4\n // (QuantMode).\n // vectorized_combine derives the per-token output pointer from row_idx (= local_token_idx).\n if constexpr (std::is_same_v<T, __nv_fp8_e4m3>) {\n // src_data_ptrs[0] points to a BF16 output buffer (set by moeA2ACombineOp for low precision).\n vectorized_combine<TOP_K, __nv_bfloat16, __nv_fp8_e4m3>(\n ptrs.src_data_ptrs[0], nullptr, local_token_idx, elements_per_token, stride_per_token,\n rank_id, max_tokens_per_rank, ptrs);\n } else {\n vectorized_combine<TOP_K, T, T, QuantMode, SwizzleMode>(\n ptrs.src_data_ptrs[0], ptrs.output_scales, local_token_idx, elements_per_token,\n stride_per_token, rank_id, max_tokens_per_rank, ptrs, OutputScalarScale);\n }\n\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n if (enable_pdl) cudaTriggerProgrammaticLaunchCompletion();\n#endif\n}\n\nvoid moe_a2a_prepare_combine_launch(MoeA2ACombineParams const& params) {\n constexpr int kBlockSize = 256;\n\n // FP8 in-place (use_low_precision, prepare_payload==nullptr): each CTA writes FP8 at the\n // BF16-stride position, so CTAs never race — all tokens must be processed. Copy path with a\n // null payload is a no-op; 1 block suffices for the flag increment only.\n int grid = (params.use_low_precision || params.prepare_payload != nullptr)\n ? params.ep_size * params.max_tokens_per_rank\n : 1;\n\n uint8_t* recv_buffer_bytes =\n static_cast<uint8_t*>(const_cast<void*>(params.recv_buffers[params.ep_rank]));\n void const* payload = params.prepare_payload;\n\n // stride_per_token (host-computed, avoids per-thread recompute):\n // FP8 external: EPT x 1 (compact FP8, dst packed tightly)\n // FP8 in-place / byte-copy: EPT x sizeof(SrcT) (payload-dtype stride)\n SWITCH_BOOL(params.use_low_precision, LOW_PRECISION, {\n SWITCH_DTYPE(params.dtype, SrcT, {\n bool const low_precision_staged = LOW_PRECISION && (params.prepare_payload != nullptr);\n int const stride_per_token = low_precision_staged\n ? params.elements_per_token\n : params.elements_per_token * static_cast<int>(sizeof(SrcT));\n auto kernel_fn = moeA2APrepareCombineKernel<LOW_PRECISION, SrcT>;\n launchWithPdlWhenEnabled(\"moeA2APrepareCombineKernel\", params.enable_pdl, kernel_fn, grid,\n kBlockSize, 0, params.stream, recv_buffer_bytes, payload,\n params.elements_per_token, params.ep_size,\n params.max_tokens_per_rank, params.flag_val, params.recv_counters,\n stride_per_token, params.enable_pdl);\n });\n });\n}\n\n// ============================================================================\n// Combine Launch Function\n// ============================================================================\n\nvoid moe_a2a_combine_launch(MoeA2ACombineParams const& params) {\n // Validate parameters\n TLLM_CHECK(params.top_k > 0 && params.top_k <= kMaxTopK);\n TLLM_CHECK(params.ep_size > 0 && params.ep_size <= kMaxRanks);\n TLLM_CHECK(params.ep_rank >= 0 && params.ep_rank < params.ep_size);\n TLLM_CHECK(params.local_num_tokens >= 0);\n TLLM_CHECK(params.elements_per_token > 0);\n if (params.enable_rank_mask) {\n // The local rank must always be marked active in its own view of the mask; otherwise the\n // kernel itself would be running on a \"dead\" rank.\n TLLM_CHECK_WITH_INFO(\n (params.active_rank_mask[params.ep_rank >> 6] >> (params.ep_rank & 63)) & 1ULL,\n \"active_rank_mask must mark the local ep_rank (%d) as active\", params.ep_rank);\n }\n\n // Configure kernel launch: one block per token\n int const kBlockSize = tensorrt_llm::common::getEnvMoeA2ACombineBlockSize();\n int grid_size_block = params.local_num_tokens;\n // If local_num_tokens is 0, we still need to launch a minimal kernel to participate in the\n // synchronization.\n if (grid_size_block == 0) {\n grid_size_block = 1;\n }\n\n // Prepare kernel pointers struct for combine\n CombineKernelPointers kernel_ptrs = {}; // Zero-initialize\n\n // Set output data pointer in src_data_ptrs[0]\n kernel_ptrs.src_data_ptrs[0] = params.output_data;\n kernel_ptrs.output_scales = params.output_scales;\n\n // Fill recv buffer pointers\n for (int rank = 0; rank < params.ep_size; rank++) {\n kernel_ptrs.recv_buffers[rank][0] = params.recv_buffers[rank];\n }\n\n // Copy completion flag pointers\n for (int i = 0; i < params.ep_size; i++) {\n kernel_ptrs.completion_flags[i] = params.completion_flags[i];\n }\n kernel_ptrs.flag_val = params.flag_val;\n\n // Copy communication tracking pointers\n kernel_ptrs.topk_target_ranks = params.topk_target_ranks;\n kernel_ptrs.topk_send_indices = params.topk_send_indices;\n\n // Copy active-rank bitmask into the kernel pointers struct\n for (int w = 0; w < kRankMaskWords; ++w) {\n kernel_ptrs.active_rank_mask[w] = params.active_rank_mask[w];\n }\n\n int grid = grid_size_block; // one block per token\n\n // stride_per_token: byte distance between tokens in the recv buffer.\n // FP8 external payload: EPT × 1 (compact FP8 layout)\n // FP8 in-place / non-FP8: EPT × sizeof(PayloadT) (payload-dtype stride)\n bool const low_precision_staged = params.use_low_precision && (params.prepare_payload != nullptr);\n int stride_per_token;\n SWITCH_DTYPE(params.dtype, PayloadT, {\n stride_per_token = low_precision_staged\n ? params.elements_per_token\n : params.elements_per_token * static_cast<int>(sizeof(PayloadT));\n });\n\n // When use_low_precision is set the recv buffers contain FP8 data regardless of params.dtype,\n // so dispatch the FP8 accumulation kernel in that case.\n auto const effective_dtype = params.use_low_precision ? nvinfer1::DataType::kFP8 : params.dtype;\n\n // Launch appropriate kernel with compact macros\n SWITCH_BOOL(params.enable_rank_mask, ENABLE_RANK_MASK, {\n SWITCH_DTYPE(effective_dtype, TKernelType, {\n SWITCH_TOP_K(params.top_k, TOP_K, {\n SWITCH_QUANT_MODE(TKernelType, params.quant_mode, QUANT_MODE, {\n SWITCH_SWIZZLE_MODE(params.swizzle_mode, SWIZZLE_MODE, {\n auto kernel_fn =\n moeA2ACombineKernel<TKernelType, TOP_K, ENABLE_RANK_MASK, QUANT_MODE, SWIZZLE_MODE>;\n launchWithPdlWhenEnabled(\"moeA2ACombineKernel\", params.enable_pdl, kernel_fn, grid,\n kBlockSize, 0, params.stream, kernel_ptrs,\n params.max_tokens_per_rank, params.elements_per_token,\n stride_per_token, params.local_num_tokens, params.ep_rank,\n params.ep_size, params.enable_pdl, params.output_scalar_scale);\n });\n });\n });\n });\n })\n}\n\n// Kernel to sanitize expert ids for invalid tokens\n__global__ void moeA2ASanitizeExpertIdsKernel(int32_t* expert_ids_ptr,\n int32_t const* recv_counters_ptr, int ep_size,\n int max_tokens_per_rank, int top_k,\n int32_t invalid_id, bool enable_pdl) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n if (enable_pdl) cudaGridDependencySynchronize();\n cudaTriggerProgrammaticLaunchCompletion();\n#endif\n int tid = blockIdx.x * blockDim.x + threadIdx.x;\n int total_tokens = ep_size * max_tokens_per_rank;\n if (tid >= total_tokens) return;\n\n int source_rank = tid / max_tokens_per_rank;\n int token_idx = tid % max_tokens_per_rank;\n\n if (token_idx >= recv_counters_ptr[source_rank]) {\n int32_t* token_expert_ids = expert_ids_ptr + tid * top_k;\n for (int k = 0; k < top_k; ++k) {\n token_expert_ids[k] = invalid_id;\n }\n }\n}\n\nvoid moe_a2a_sanitize_expert_ids_launch(int32_t* expert_ids, int32_t const* recv_counters,\n int32_t invalid_id, int ep_size, int max_tokens_per_rank,\n int top_k, cudaStream_t stream, bool enable_pdl) {\n constexpr int kBlockSize = 256;\n int total_tokens = ep_size * max_tokens_per_rank;\n int grid = ceilDiv(total_tokens, kBlockSize);\n launchWithPdlWhenEnabled(\"moeA2ASanitizeExpertIdsKernel\", enable_pdl,\n moeA2ASanitizeExpertIdsKernel, grid, kBlockSize, 0, stream, expert_ids,\n recv_counters, ep_size, max_tokens_per_rank, top_k, invalid_id,\n enable_pdl);\n}\n\n} // namespace tensorrt_llm::kernels::moe_alltoall\n"},"diff":{"kind":"string","value":"--- csrc/nv_internal/tensorrt_llm/kernels/communicationKernels/moeAlltoAllKernels.cu\n+++ csrc/nv_internal/tensorrt_llm/kernels/communicationKernels/moeAlltoAllKernels.cu\n@@ -35,8 +35,25 @@\n #define DISABLE_SYNC_FOR_PROFILING 0\n \n constexpr int kEp4Size = 4;\n+// Two 32-thread warps can cover at most 64 16-byte activation vectors.\n constexpr int kCompactDispatchMaxPayloadBytes = 1024;\n constexpr int kCompactDispatchBlockSize = 128;\n+constexpr int kDispatchWarpSize = 32;\n+constexpr int kDispatchActivationWarps = 2;\n+constexpr int kDispatchWideVectorBytes = 16;\n+constexpr int kDispatchMetadataVectorBytes = 8;\n+constexpr int kDispatchHalfWarpSize = 16;\n+constexpr int kNvfp4ActivationToScaleRatio = 8;\n+constexpr int kNvfp4H2048ActivationBytes = 2048 / 2;\n+constexpr int kNvfp4H2048ScaleBytes = 2048 / 16;\n+constexpr int kTopK22MetadataBytes = 22 * sizeof(int32_t);\n+constexpr int kNvfp4H2048ActivationWorkers = kNvfp4H2048ActivationBytes / kDispatchWideVectorBytes;\n+constexpr int kNvfp4H2048ScaleWorkers = kNvfp4H2048ScaleBytes / kDispatchWideVectorBytes;\n+constexpr int kTopK22MetadataWorkers = kTopK22MetadataBytes / kDispatchMetadataVectorBytes;\n+static_assert(kCompactDispatchMaxPayloadBytes % kDispatchWideVectorBytes == 0);\n+static_assert(kCompactDispatchMaxPayloadBytes / kDispatchWideVectorBytes <=\n+ kDispatchActivationWarps * kDispatchWarpSize);\n+static_assert(kCompactDispatchBlockSize == (kDispatchActivationWarps + 2) * kDispatchWarpSize);\n \n #ifndef DISABLE_TIMEOUT\n #define DISABLE_TIMEOUT 0\n@@ -46,6 +63,32 @@\n template <typename T>\n __host__ __device__ inline T ceilDiv(T m, T n) {\n return (m + n - 1) / n;\n+}\n+\n+// The phased schedule reserves two warps for packed activations, one for scales,\n+// and splits the last warp between the two routing-metadata payloads. The\n+// activation cap intentionally limits this path to hidden sizes up to 2048.\n+static bool isPhasedNvfp4PayloadLayout(DispatchKernelPointers const& ptrs, int num_payloads,\n+ int top_k) {\n+ if (num_payloads != 4 || top_k <= kEp4Size) {\n+ return false;\n+ }\n+\n+ int const activation_bytes = ptrs.payload_bytes_per_token[0];\n+ int const scale_bytes = ptrs.payload_bytes_per_token[1];\n+ int const metadata_bytes = top_k * static_cast<int>(sizeof(int32_t));\n+ // Smaller top-k layouts support runtime activation widths (including H1024).\n+ // Top-k 22 is restricted to the measured H2048 configuration.\n+ bool const validated_top_k_layout = top_k < 22 || activation_bytes == kNvfp4H2048ActivationBytes;\n+ return validated_top_k_layout && activation_bytes > 0 &&\n+ activation_bytes <= kCompactDispatchMaxPayloadBytes &&\n+ activation_bytes % kDispatchWideVectorBytes == 0 && scale_bytes > 0 &&\n+ scale_bytes % kDispatchWideVectorBytes == 0 &&\n+ activation_bytes == kNvfp4ActivationToScaleRatio * scale_bytes &&\n+ metadata_bytes % kDispatchMetadataVectorBytes == 0 &&\n+ metadata_bytes / kDispatchMetadataVectorBytes <= kDispatchHalfWarpSize &&\n+ ptrs.payload_bytes_per_token[2] == metadata_bytes &&\n+ ptrs.payload_bytes_per_token[3] == metadata_bytes;\n }\n \n // Macros for concise launch-time specialization\n@@ -291,8 +334,8 @@\n __device__ void vectorized_dispatch_impl(uint8_t const* src_ptr, int bytes_per_token, int rank_id,\n int max_tokens_per_rank, int payload_idx,\n DispatchKernelPointers const& ptrs,\n- int const* topk_target_ranks,\n- int const* topk_send_indices) {\n+ int const* topk_target_ranks, int const* topk_send_indices,\n+ int worker_idx, int num_workers) {\n using flashinfer::vec_t;\n \n // Precompute destination base pointers per k\n@@ -313,9 +356,10 @@\n dst_base_k[k] = dst_data + base_token;\n }\n \n- // TODO: process all payloads. index could be reused.\n- int const stride = blockDim.x * VEC_SIZE;\n- for (int offset = threadIdx.x * VEC_SIZE; offset < bytes_per_token; offset += stride) {\n+ // The caller assigns a worker subset to this payload. Only those workers pay\n+ // the per-destination pointer setup and copy cost.\n+ int const stride = num_workers * VEC_SIZE;\n+ for (int offset = worker_idx * VEC_SIZE; offset < bytes_per_token; offset += stride) {\n vec_t<uint8_t, VEC_SIZE> v;\n v.load(src_ptr + offset);\n \n@@ -337,19 +381,24 @@\n int const* topk_target_ranks, int const* topk_send_indices) {\n if (bytes_per_token % 16 == 0) {\n vectorized_dispatch_impl<16, TOP_K>(src_ptr, bytes_per_token, rank_id, max_tokens_per_rank,\n- payload_idx, ptrs, topk_target_ranks, topk_send_indices);\n+ payload_idx, ptrs, topk_target_ranks, topk_send_indices,\n+ threadIdx.x, blockDim.x);\n } else if (bytes_per_token % 8 == 0) {\n vectorized_dispatch_impl<8, TOP_K>(src_ptr, bytes_per_token, rank_id, max_tokens_per_rank,\n- payload_idx, ptrs, topk_target_ranks, topk_send_indices);\n+ payload_idx, ptrs, topk_target_ranks, topk_send_indices,\n+ threadIdx.x, blockDim.x);\n } else if (bytes_per_token % 4 == 0) {\n vectorized_dispatch_impl<4, TOP_K>(src_ptr, bytes_per_token, rank_id, max_tokens_per_rank,\n- payload_idx, ptrs, topk_target_ranks, topk_send_indices);\n+ payload_idx, ptrs, topk_target_ranks, topk_send_indices,\n+ threadIdx.x, blockDim.x);\n } else if (bytes_per_token % 2 == 0) {\n vectorized_dispatch_impl<2, TOP_K>(src_ptr, bytes_per_token, rank_id, max_tokens_per_rank,\n- payload_idx, ptrs, topk_target_ranks, topk_send_indices);\n+ payload_idx, ptrs, topk_target_ranks, topk_send_indices,\n+ threadIdx.x, blockDim.x);\n } else {\n vectorized_dispatch_impl<1, TOP_K>(src_ptr, bytes_per_token, rank_id, max_tokens_per_rank,\n- payload_idx, ptrs, topk_target_ranks, topk_send_indices);\n+ payload_idx, ptrs, topk_target_ranks, topk_send_indices,\n+ threadIdx.x, blockDim.x);\n }\n }\n \n@@ -377,7 +426,8 @@\n // One CTA processes one token and all its payloads.\n // ============================================================================\n \n-template <int TOP_K, bool ENABLE_EPLB, bool ENABLE_RANK_MASK, bool COMPACT_EP4>\n+template <int TOP_K, bool ENABLE_EPLB, bool ENABLE_RANK_MASK, bool COMPACT_EP4,\n+ bool PHASE_H2048_NVFP4 = false, bool PHASE_NVFP4_PAYLOADS = false>\n __global__ void moeA2ADispatchKernel(\n int32_t const* token_selected_experts, // [local_num_tokens, TOP_K]\n const DispatchKernelPointers ptrs, // Struct containing all kernel pointers\n@@ -386,6 +436,12 @@\n int local_num_tokens, int rank_id, int ep_size, int num_experts, int eplb_stats_num_experts,\n bool enable_pdl) {\n static_assert(!COMPACT_EP4 || TOP_K > kEp4Size);\n+ static_assert(!PHASE_H2048_NVFP4 || TOP_K == 22);\n+ static_assert(!PHASE_NVFP4_PAYLOADS ||\n+ (TOP_K > kEp4Size && TOP_K % 2 == 0 &&\n+ TOP_K * static_cast<int>(sizeof(int32_t)) / kDispatchMetadataVectorBytes <=\n+ kDispatchHalfWarpSize));\n+ static_assert(!PHASE_H2048_NVFP4 || !PHASE_NVFP4_PAYLOADS);\n int thread_idx = threadIdx.x;\n int local_token_idx = blockIdx.x;\n \n@@ -490,14 +546,76 @@\n }\n }\n \n- // Perform a single source load and fan out to each unique destination.\n- for (int payload_idx = 0; payload_idx < num_payloads; payload_idx++) {\n- uint8_t const* src_data = static_cast<uint8_t const*>(ptrs.src_data_ptrs[payload_idx]);\n- int bytes_per_token = ptrs.payload_bytes_per_token[payload_idx];\n- uint8_t const* src_ptr = src_data + local_token_idx * bytes_per_token;\n-\n- vectorized_dispatch<NUM_DESTINATIONS>(src_ptr, bytes_per_token, rank_id, max_tokens_per_rank,\n- payload_idx, ptrs, target_ranks, send_indices);\n+ if constexpr (PHASE_H2048_NVFP4) {\n+ // Keep compile-time bounds for the measured Nemotron H2048 target.\n+ int warp_id = thread_idx / warpSize;\n+ int lane_id = thread_idx % warpSize;\n+ if (warp_id < kDispatchActivationWarps) {\n+ auto const* src = static_cast<uint8_t const*>(ptrs.src_data_ptrs[0]) +\n+ static_cast<size_t>(local_token_idx) * kNvfp4H2048ActivationBytes;\n+ vectorized_dispatch_impl<16, NUM_DESTINATIONS>(\n+ src, kNvfp4H2048ActivationBytes, rank_id, max_tokens_per_rank, 0, ptrs, target_ranks,\n+ send_indices, thread_idx, kNvfp4H2048ActivationWorkers);\n+ } else if (warp_id == kDispatchActivationWarps && lane_id < kNvfp4H2048ScaleWorkers) {\n+ auto const* src = static_cast<uint8_t const*>(ptrs.src_data_ptrs[1]) +\n+ static_cast<size_t>(local_token_idx) * kNvfp4H2048ScaleBytes;\n+ vectorized_dispatch_impl<16, NUM_DESTINATIONS>(\n+ src, kNvfp4H2048ScaleBytes, rank_id, max_tokens_per_rank, 1, ptrs, target_ranks,\n+ send_indices, lane_id, kNvfp4H2048ScaleWorkers);\n+ } else if (warp_id == kDispatchActivationWarps + 1 && lane_id < 2 * kTopK22MetadataWorkers) {\n+ bool second_tail = lane_id >= kTopK22MetadataWorkers;\n+ int payload_idx = second_tail ? 3 : 2;\n+ int worker_idx = second_tail ? lane_id - kTopK22MetadataWorkers : lane_id;\n+ auto const* src = static_cast<uint8_t const*>(ptrs.src_data_ptrs[payload_idx]) +\n+ static_cast<size_t>(local_token_idx) * kTopK22MetadataBytes;\n+ vectorized_dispatch_impl<8, NUM_DESTINATIONS>(\n+ src, kTopK22MetadataBytes, rank_id, max_tokens_per_rank, payload_idx, ptrs,\n+ target_ranks, send_indices, worker_idx, kTopK22MetadataWorkers);\n+ }\n+ } else if constexpr (PHASE_NVFP4_PAYLOADS) {\n+ // Match warps to the NVFP4 payload widths instead of making all 128\n+ // threads materialize destination pointers for every payload.\n+ int const activation_bytes = ptrs.payload_bytes_per_token[0];\n+ int const scale_bytes = ptrs.payload_bytes_per_token[1];\n+ constexpr int METADATA_BYTES = TOP_K * sizeof(int32_t);\n+ constexpr int METADATA_WORKERS = METADATA_BYTES / kDispatchMetadataVectorBytes;\n+ int const activation_workers = activation_bytes / kDispatchWideVectorBytes;\n+ int const scale_workers = scale_bytes / kDispatchWideVectorBytes;\n+ int warp_id = thread_idx / warpSize;\n+ int lane_id = thread_idx % warpSize;\n+ if (warp_id < kDispatchActivationWarps && thread_idx < activation_workers) {\n+ auto const* src = static_cast<uint8_t const*>(ptrs.src_data_ptrs[0]) +\n+ static_cast<size_t>(local_token_idx) * activation_bytes;\n+ vectorized_dispatch_impl<kDispatchWideVectorBytes, NUM_DESTINATIONS>(\n+ src, activation_bytes, rank_id, max_tokens_per_rank, 0, ptrs, target_ranks,\n+ send_indices, thread_idx, activation_workers);\n+ } else if (warp_id == kDispatchActivationWarps && lane_id < scale_workers) {\n+ auto const* src = static_cast<uint8_t const*>(ptrs.src_data_ptrs[1]) +\n+ static_cast<size_t>(local_token_idx) * scale_bytes;\n+ vectorized_dispatch_impl<kDispatchWideVectorBytes, NUM_DESTINATIONS>(\n+ src, scale_bytes, rank_id, max_tokens_per_rank, 1, ptrs, target_ranks, send_indices,\n+ lane_id, scale_workers);\n+ } else if (warp_id == kDispatchActivationWarps + 1 && lane_id < 2 * METADATA_WORKERS) {\n+ bool second_tail = lane_id >= METADATA_WORKERS;\n+ int payload_idx = second_tail ? 3 : 2;\n+ int worker_idx = second_tail ? lane_id - METADATA_WORKERS : lane_id;\n+ auto const* src = static_cast<uint8_t const*>(ptrs.src_data_ptrs[payload_idx]) +\n+ static_cast<size_t>(local_token_idx) * METADATA_BYTES;\n+ vectorized_dispatch_impl<kDispatchMetadataVectorBytes, NUM_DESTINATIONS>(\n+ src, METADATA_BYTES, rank_id, max_tokens_per_rank, payload_idx, ptrs, target_ranks,\n+ send_indices, worker_idx, METADATA_WORKERS);\n+ }\n+ } else {\n+ // Perform a single source load and fan out to each unique destination.\n+ for (int payload_idx = 0; payload_idx < num_payloads; payload_idx++) {\n+ uint8_t const* src_data = static_cast<uint8_t const*>(ptrs.src_data_ptrs[payload_idx]);\n+ int bytes_per_token = ptrs.payload_bytes_per_token[payload_idx];\n+ uint8_t const* src_ptr = src_data + local_token_idx * bytes_per_token;\n+\n+ vectorized_dispatch<NUM_DESTINATIONS>(src_ptr, bytes_per_token, rank_id,\n+ max_tokens_per_rank, payload_idx, ptrs, target_ranks,\n+ send_indices);\n+ }\n }\n \n __syncthreads();\n@@ -684,12 +802,20 @@\n max_payload_bytes_per_token = kernel_ptrs.payload_bytes_per_token[i];\n }\n }\n+ bool const supports_phased_nvfp4 =\n+ params.ep_size == kEp4Size || params.ep_size == 8 || params.ep_size == 16;\n+ bool const phased_nvfp4_layout =\n+ supports_phased_nvfp4 &&\n+ isPhasedNvfp4PayloadLayout(kernel_ptrs, params.num_payloads, params.top_k);\n+\n // Small payloads do not have enough 16-byte vectors to use larger CTAs. A GB200\n // sweep found 128 threads faster than both 64 and 256 at prefill token counts.\n- if (use_compact_ep4 && max_payload_bytes_per_token <= kCompactDispatchMaxPayloadBytes &&\n+ if ((use_compact_ep4 || phased_nvfp4_layout) &&\n+ max_payload_bytes_per_token <= kCompactDispatchMaxPayloadBytes &&\n block_size > kCompactDispatchBlockSize) {\n block_size = kCompactDispatchBlockSize;\n }\n+ bool const phase_nvfp4_payloads = phased_nvfp4_layout && block_size == kCompactDispatchBlockSize;\n \n // Configure kernel launch: one block per token\n int grid_size = params.local_num_tokens;\n@@ -700,7 +826,60 @@\n }\n SWITCH_BOOL(params.enable_rank_mask, ENABLE_RANK_MASK, {\n SWITCH_BOOL(params.enable_eplb, EPLB_STATS, {\n- if (use_compact_ep4) {\n+ if (phase_nvfp4_payloads && params.top_k == 22 &&\n+ kernel_ptrs.payload_bytes_per_token[0] == kNvfp4H2048ActivationBytes) {\n+ FLASHINFER_CHECK(kernel_ptrs.payload_bytes_per_token[1] == kNvfp4H2048ScaleBytes &&\n+ kernel_ptrs.payload_bytes_per_token[2] == kTopK22MetadataBytes &&\n+ kernel_ptrs.payload_bytes_per_token[3] == kTopK22MetadataBytes,\n+ \"Invalid H2048/top-k-22 NVFP4 dispatch payload layout\");\n+ if (use_compact_ep4) {\n+ int shared_bytes = kEp4Size * (int)sizeof(int);\n+ auto kernel_fn = moeA2ADispatchKernel<22, EPLB_STATS, ENABLE_RANK_MASK, true, true>;\n+ launchWithPdlWhenEnabled(\"moeA2ADispatchKernel\", params.enable_pdl, kernel_fn, grid_size,\n+ block_size, shared_bytes, params.stream,\n+ params.token_selected_experts, kernel_ptrs, params.num_payloads,\n+ params.max_tokens_per_rank, params.local_num_tokens,\n+ params.ep_rank, params.ep_size, params.num_experts,\n+ params.eplb_stats_num_experts, params.enable_pdl);\n+ } else {\n+ int shared_bytes = 2 * params.top_k * (int)sizeof(int);\n+ auto kernel_fn = moeA2ADispatchKernel<22, EPLB_STATS, ENABLE_RANK_MASK, false, true>;\n+ launchWithPdlWhenEnabled(\"moeA2ADispatchKernel\", params.enable_pdl, kernel_fn, grid_size,\n+ block_size, shared_bytes, params.stream,\n+ params.token_selected_experts, kernel_ptrs, params.num_payloads,\n+ params.max_tokens_per_rank, params.local_num_tokens,\n+ params.ep_rank, params.ep_size, params.num_experts,\n+ params.eplb_stats_num_experts, params.enable_pdl);\n+ }\n+ } else if (phase_nvfp4_payloads) {\n+ if (use_compact_ep4) {\n+ int shared_bytes = kEp4Size * (int)sizeof(int);\n+ SWITCH_TOP_K(\n+ params.top_k, TOP_K, if constexpr (TOP_K > kEp4Size && TOP_K % 2 == 0) {\n+ auto kernel_fn =\n+ moeA2ADispatchKernel<TOP_K, EPLB_STATS, ENABLE_RANK_MASK, true, false, true>;\n+ launchWithPdlWhenEnabled(\n+ \"moeA2ADispatchKernel\", params.enable_pdl, kernel_fn, grid_size, block_size,\n+ shared_bytes, params.stream, params.token_selected_experts, kernel_ptrs,\n+ params.num_payloads, params.max_tokens_per_rank, params.local_num_tokens,\n+ params.ep_rank, params.ep_size, params.num_experts,\n+ params.eplb_stats_num_experts, params.enable_pdl);\n+ })\n+ } else {\n+ int shared_bytes = 2 * params.top_k * (int)sizeof(int);\n+ SWITCH_TOP_K(\n+ params.top_k, TOP_K, if constexpr (TOP_K > kEp4Size && TOP_K % 2 == 0) {\n+ auto kernel_fn =\n+ moeA2ADispatchKernel<TOP_K, EPLB_STATS, ENABLE_RANK_MASK, false, false, true>;\n+ launchWithPdlWhenEnabled(\n+ \"moeA2ADispatchKernel\", params.enable_pdl, kernel_fn, grid_size, block_size,\n+ shared_bytes, params.stream, params.token_selected_experts, kernel_ptrs,\n+ params.num_payloads, params.max_tokens_per_rank, params.local_num_tokens,\n+ params.ep_rank, params.ep_size, params.num_experts,\n+ params.eplb_stats_num_experts, params.enable_pdl);\n+ })\n+ }\n+ } else if (use_compact_ep4) {\n int shared_bytes = kEp4Size * (int)sizeof(int);\n SWITCH_TOP_K(\n params.top_k, TOP_K, if constexpr (TOP_K > kEp4Size) {"},"lines_added":{"kind":"number","value":200,"string":"200"},"lines_removed":{"kind":"number","value":21,"string":"21"},"files_in_commit":{"kind":"number","value":1,"string":"1"},"models_mentioned":{"kind":"list like","value":["nemotron"],"string":"[\n \"nemotron\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["GB200"],"string":"[\n \"GB200\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (csrc/nv_internal/tensorrt_llm/kernels/communicationKernels/moeAlltoAllKernels.cu).\n\nGoal: perf(moe): phase NVFP4 dispatch payload copies at EP4/EP8/EP16\nTarget hardware: GB200\nTarget models: nemotron\n\nCurrent file:\n```cuda\n/*\n * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include <cooperative_groups.h>\n#include <cuda_fp8.h>\n\n#include <cstdint>\n#include <type_traits>\n\n#include \"flashinfer/exception.h\"\n#include \"flashinfer/utils.cuh\"\n#include \"flashinfer/vec_dtypes.cuh\"\n#include \"tensorrt_llm/common/dataType.h\"\n#include \"tensorrt_llm/common/envUtils.h\"\n#include \"tensorrt_llm/kernels/communicationKernels/moeAlltoAllKernels.h\"\n#include \"tensorrt_llm/kernels/quantization_utils.cuh\"\n\nnamespace tensorrt_llm::kernels::moe_alltoall {\n\nusing tensorrt_llm::common::launchWithPdlWhenEnabled;\n\n#define ENABLE_DEBUG_PRINT 0\n#define DISABLE_SYNC_FOR_PROFILING 0\n\nconstexpr int kEp4Size = 4;\nconstexpr int kCompactDispatchMaxPayloadBytes = 1024;\nconstexpr int kCompactDispatchBlockSize = 128;\n\n#ifndef DISABLE_TIMEOUT\n#define DISABLE_TIMEOUT 0\n#endif\n\n// Helper function for ceiling division\ntemplate <typename T>\n__host__ __device__ inline T ceilDiv(T m, T n) {\n return (m + n - 1) / n;\n}\n\n// Macros for concise launch-time specialization\n#define SWITCH_BOOL(flag, NAME, ...) \\\n if (flag) { \\\n constexpr bool NAME = true; \\\n __VA_ARGS__ \\\n } else { \\\n constexpr bool NAME = false; \\\n __VA_ARGS__ \\\n }\n\n#define SWITCH_TOP_K(top_k, TOP_K, ...) \\\n switch (top_k) { \\\n case 22: { \\\n constexpr int TOP_K = 22; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case 18: { \\\n constexpr int TOP_K = 18; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case 16: { \\\n constexpr int TOP_K = 16; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case 14: { \\\n constexpr int TOP_K = 14; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case 12: { \\\n constexpr int TOP_K = 12; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case 10: { \\\n constexpr int TOP_K = 10; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case 8: { \\\n constexpr int TOP_K = 8; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case 6: { \\\n constexpr int TOP_K = 6; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case 4: { \\\n constexpr int TOP_K = 4; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case 2: { \\\n constexpr int TOP_K = 2; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case 1: { \\\n constexpr int TOP_K = 1; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n default: { \\\n FLASHINFER_CHECK(false, \"Unsupported top_k\"); \\\n } \\\n }\n\n#define SWITCH_DTYPE(dtype, TYPE, ...) \\\n switch (dtype) { \\\n case nvinfer1::DataType::kHALF: { \\\n using TYPE = half; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case nvinfer1::DataType::kBF16: { \\\n using TYPE = __nv_bfloat16; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case nvinfer1::DataType::kFLOAT: { \\\n using TYPE = float; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case nvinfer1::DataType::kFP8: { \\\n using TYPE = __nv_fp8_e4m3; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n default: { \\\n FLASHINFER_CHECK(false, \"Unsupported dtype for moe_a2a_combine\"); \\\n } \\\n }\n\n// Quantized combine currently only supports FP16/BF16 inputs.\n#define SWITCH_QUANT_MODE(dtype, quant_mode, QUANT_MODE, ...) \\\n if constexpr (std::is_same_v<dtype, half> || std::is_same_v<dtype, __nv_bfloat16>) { \\\n switch (quant_mode) { \\\n case MoeA2ACombineQuantMode::NONE: { \\\n constexpr auto QUANT_MODE = MoeA2ACombineQuantMode::NONE; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case MoeA2ACombineQuantMode::MXFP8: { \\\n constexpr auto QUANT_MODE = MoeA2ACombineQuantMode::MXFP8; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case MoeA2ACombineQuantMode::NVFP4: { \\\n constexpr auto QUANT_MODE = MoeA2ACombineQuantMode::NVFP4; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case MoeA2ACombineQuantMode::MXFP4: { \\\n constexpr auto QUANT_MODE = MoeA2ACombineQuantMode::MXFP4; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n default: { \\\n FLASHINFER_CHECK(false, \"Unsupported quant_mode for moe_a2a_combine\"); \\\n } \\\n } \\\n } else { \\\n FLASHINFER_CHECK((quant_mode) == MoeA2ACombineQuantMode::NONE, \\\n \"All to All Combine Quantization currently only supports \" \\\n \"FP16/BF16\"); \\\n constexpr auto QUANT_MODE = MoeA2ACombineQuantMode::NONE; \\\n __VA_ARGS__; \\\n }\n\n#define SWITCH_SWIZZLE_MODE(swizzle_mode, SWIZZLE_MODE, ...) \\\n switch (swizzle_mode) { \\\n case MoeA2ACombineSwizzleSFMode::LINEAR: { \\\n constexpr auto SWIZZLE_MODE = MoeA2ACombineSwizzleSFMode::LINEAR; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case MoeA2ACombineSwizzleSFMode::SWIZZLE_128x4: { \\\n constexpr auto SWIZZLE_MODE = MoeA2ACombineSwizzleSFMode::SWIZZLE_128x4; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n case MoeA2ACombineSwizzleSFMode::SWIZZLE_8x4: { \\\n constexpr auto SWIZZLE_MODE = MoeA2ACombineSwizzleSFMode::SWIZZLE_8x4; \\\n __VA_ARGS__; \\\n break; \\\n } \\\n default: { \\\n FLASHINFER_CHECK(false, \"Unsupported swizzle_mode for moe_a2a_combine\"); \\\n } \\\n }\n\n#if DISABLE_TIMEOUT\n#define check_timeout(s) false\n#else\n// 300 * 2000 MHz - should be high enough on any GPU but will prevent a hang\n#define check_timeout(s) ((clock64() - (s)) > (300ll * 2000ll * 1000ll * 1000ll))\n#endif\n\n// ============================================================================\n// Helper Functions for Expert-to-Rank Mapping\n// ============================================================================\n\n// Compute which rank owns a given expert using contiguous ceil/floor partitioning.\n// Supports non-divisible distribution when num_experts % ep_size != 0:\n// base = num_experts / ep_size\n// remainder = num_experts % ep_size\n// - Ranks [0, remainder) each own (base + 1) experts.\n// - Ranks [remainder, ep_size) each own base experts.\n//\n// Example A (uniform): 32 experts, 4 ranks -> base=8, remainder=0\n// - Rank 0: experts 0-7, Rank 1: 8-15, Rank 2: 16-23, Rank 3: 24-31\n// Example B (non-divisible): 384 experts, 5 ranks -> base=76, remainder=4\n// - Ranks 0-3: 77 experts each, Rank 4: 76 experts\n//\n// base and remainder are precomputed by the caller once outside the per-token TOP_K loop\n// so the hot path performs at most one integer divide.\n__device__ __forceinline__ int compute_target_rank_id(int expert_id, int base, int remainder) {\n // Fast path for the uniform (num_experts % ep_size == 0) case: identical to the\n // pre-ceil/floor implementation, so existing divisible deployments incur no overhead.\n if (remainder == 0) {\n return expert_id / base;\n }\n int const split = remainder * (base + 1); // boundary expert id\n if (expert_id < split) {\n // Falls inside the (base + 1)-sized prefix block.\n return expert_id / (base + 1);\n }\n // Falls inside the base-sized suffix block.\n return remainder + (expert_id - split) / base;\n}\n\n// Test bit `rank` in a kRankMaskWords-wide little-endian uint64 bitmask.\n// Word 0 covers ranks 0..63, word 1 covers ranks 64..127, etc.\n// `rank >> 6` and `rank & 63` divide / modulo by 64.\n__device__ __forceinline__ bool is_rank_active(uint64_t const* mask, int rank) {\n return (mask[rank >> 6] >> (rank & 63)) & 1ULL;\n}\n\n// ============================================================================\n// Helper Functions for Vectorized Memory Operations\n// ============================================================================\n\ntemplate <int VEC_SIZE>\n__device__ void vectorized_copy_impl(void* dst, void const* src, int size) {\n using flashinfer::vec_t;\n\n uint8_t* dst_ptr = static_cast<uint8_t*>(dst);\n uint8_t const* src_ptr = static_cast<uint8_t const*>(src);\n\n int const stride = blockDim.x * VEC_SIZE;\n\n for (int offset = threadIdx.x * VEC_SIZE; offset < size; offset += stride) {\n vec_t<uint8_t, VEC_SIZE> v;\n v.load(src_ptr + offset);\n v.store(dst_ptr + offset);\n }\n}\n\n__device__ void vectorized_copy(void* dst, void const* src, int size) {\n if (size % 16 == 0) {\n vectorized_copy_impl<16>(dst, src, size);\n } else if (size % 8 == 0) {\n vectorized_copy_impl<8>(dst, src, size);\n } else if (size % 4 == 0) {\n vectorized_copy_impl<4>(dst, src, size);\n } else if (size % 2 == 0) {\n vectorized_copy_impl<2>(dst, src, size);\n } else {\n vectorized_copy_impl<1>(dst, src, size);\n }\n}\n\n// Vectorized dispatch: load one vec from source and write to up to TOP_K destinations\ntemplate <int VEC_SIZE, int TOP_K>\n__device__ void vectorized_dispatch_impl(uint8_t const* src_ptr, int bytes_per_token, int rank_id,\n int max_tokens_per_rank, int payload_idx,\n DispatchKernelPointers const& ptrs,\n int const* topk_target_ranks,\n int const* topk_send_indices) {\n using flashinfer::vec_t;\n\n // Precompute destination base pointers per k\n uint8_t* dst_base_k[TOP_K];\n#pragma unroll\n for (int k = 0; k < TOP_K; ++k) {\n int dst_idx_k = topk_send_indices[k];\n int target_rank_k = topk_target_ranks[k];\n if (dst_idx_k < 0) {\n dst_base_k[k] = nullptr;\n continue;\n }\n uint8_t* dst_data = static_cast<uint8_t*>(ptrs.recv_buffers[target_rank_k][payload_idx]);\n size_t base_source_rank =\n static_cast<size_t>(rank_id) * static_cast<size_t>(max_tokens_per_rank) +\n static_cast<size_t>(dst_idx_k);\n size_t base_token = base_source_rank * static_cast<size_t>(bytes_per_token);\n dst_base_k[k] = dst_data + base_token;\n }\n\n // TODO: process all payloads. index could be reused.\n int const stride = blockDim.x * VEC_SIZE;\n for (int offset = threadIdx.x * VEC_SIZE; offset < bytes_per_token; offset += stride) {\n vec_t<uint8_t, VEC_SIZE> v;\n v.load(src_ptr + offset);\n\n#pragma unroll\n for (int k = 0; k < TOP_K; ++k) {\n uint8_t* dst_base = dst_base_k[k];\n if (dst_base == nullptr) {\n continue;\n }\n v.store(dst_base + offset);\n }\n }\n}\n\ntemplate <int TOP_K>\n__device__ void vectorized_dispatch(uint8_t const* src_ptr, int bytes_per_token, int rank_id,\n int max_tokens_per_rank, int payload_idx,\n DispatchKernelPointers const& ptrs,\n int const* topk_target_ranks, int const* topk_send_indices) {\n if (bytes_per_token % 16 == 0) {\n vectorized_dispatch_impl<16, TOP_K>(src_ptr, bytes_per_token, rank_id, max_tokens_per_rank,\n payload_idx, ptrs, topk_target_ranks, topk_send_indices);\n } else if (bytes_per_token % 8 == 0) {\n vectorized_dispatch_impl<8, TOP_K>(src_ptr, bytes_per_token, rank_id, max_tokens_per_rank,\n payload_idx, ptrs, topk_target_ranks, topk_send_indices);\n } else if (bytes_per_token % 4 == 0) {\n vectorized_dispatch_impl<4, TOP_K>(src_ptr, bytes_per_token, rank_id, max_tokens_per_rank,\n payload_idx, ptrs, topk_target_ranks, topk_send_indices);\n } else if (bytes_per_token % 2 == 0) {\n vectorized_dispatch_impl<2, TOP_K>(src_ptr, bytes_per_token, rank_id, max_tokens_per_rank,\n payload_idx, ptrs, topk_target_ranks, topk_send_indices);\n } else {\n vectorized_dispatch_impl<1, TOP_K>(src_ptr, bytes_per_token, rank_id, max_tokens_per_rank,\n payload_idx, ptrs, topk_target_ranks, topk_send_indices);\n }\n}\n\n__global__ void moeA2APrepareDispatchKernel(int* send_counters, int* local_token_counter,\n int ep_size, uint32_t* flag_val_ptr, bool enable_pdl) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n if (enable_pdl) cudaGridDependencySynchronize();\n cudaTriggerProgrammaticLaunchCompletion();\n#endif\n int idx = blockIdx.x * blockDim.x + threadIdx.x;\n // Zero send_counters\n if (idx < ep_size) {\n send_counters[idx] = 0;\n }\n // Zero local_token_counter and increment flag_val\n if (idx == 0) {\n *local_token_counter = 0;\n // Increment flag_val for this dispatch round\n *flag_val_ptr = *flag_val_ptr + 1;\n }\n}\n\n// ============================================================================\n// Generic Dispatch Kernel Implementation\n// One CTA processes one token and all its payloads.\n// ============================================================================\n\ntemplate <int TOP_K, bool ENABLE_EPLB, bool ENABLE_RANK_MASK, bool COMPACT_EP4>\n__global__ void moeA2ADispatchKernel(\n int32_t const* token_selected_experts, // [local_num_tokens, TOP_K]\n const DispatchKernelPointers ptrs, // Struct containing all kernel pointers\n int num_payloads, // Number of payloads\n int max_tokens_per_rank, // Maximum tokens per rank\n int local_num_tokens, int rank_id, int ep_size, int num_experts, int eplb_stats_num_experts,\n bool enable_pdl) {\n static_assert(!COMPACT_EP4 || TOP_K > kEp4Size);\n int thread_idx = threadIdx.x;\n int local_token_idx = blockIdx.x;\n\n if (local_num_tokens == 0) {\n // Special case: If local_num_tokens == 0,\n // we need to keep the threads where local_token_idx == 0 alive to participate in the\n // synchronization. Other threads should return.\n if (local_token_idx > 0) return;\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n if (enable_pdl) cudaGridDependencySynchronize();\n#endif\n } else {\n // Threads that do not have a token to process should return.\n if (local_token_idx >= local_num_tokens) return;\n\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n if (enable_pdl) cudaGridDependencySynchronize();\n#endif\n\n // Prepare per-policy shared-memory tiles for this token\n extern __shared__ int smem[];\n int* smem_topk_target_ranks = smem;\n int* smem_topk_send_indices = nullptr;\n int* smem_compact_send_indices = smem;\n if constexpr (!COMPACT_EP4) {\n smem_topk_send_indices = smem + TOP_K;\n }\n\n // Precompute the ceil/floor partition parameters once per thread, outside the\n // per-token TOP_K loop. The fast path (remainder == 0) then collapses to a single\n // integer divide per call, matching the pre-PR uniform-partition cost exactly.\n int const ep_base = num_experts / ep_size;\n int const ep_remainder = num_experts - ep_base * ep_size; // == num_experts % ep_size\n\n if (thread_idx < warpSize) {\n int lane_id = thread_idx;\n if constexpr (COMPACT_EP4) {\n if (lane_id < kEp4Size) {\n smem_compact_send_indices[lane_id] = -1;\n }\n __syncwarp();\n }\n\n unsigned topk_mask = __ballot_sync(0xffffffff, lane_id < TOP_K);\n if (lane_id < TOP_K) {\n int k = lane_id;\n int expert_id = token_selected_experts[local_token_idx * TOP_K + k];\n // Use contiguous ceil/floor partitioning (supports non-divisible num_experts % ep_size).\n int target_rank = compute_target_rank_id(expert_id, ep_base, ep_remainder);\n\n // Elect the first top-k lane for each destination rank; duplicate targets within a\n // token collapse to a single send (replaces the old serial already_copied bitmask).\n unsigned matching_lanes = __match_any_sync(topk_mask, target_rank);\n bool is_first = lane_id == __ffs(matching_lanes) - 1;\n\n // Dead ranks (ENABLE_RANK_MASK) are dropped the same way as duplicates: no send is\n // issued and topk_send_indices[k] stays < 0, so combine's existing skip check on that\n // sentinel handles both cases uniformly. When ENABLE_RANK_MASK is false, the dead-rank\n // check is compiled out entirely (no active_rank_mask load/branch on this hot path).\n bool is_valid = is_first;\n if constexpr (ENABLE_RANK_MASK) {\n is_valid = is_valid && is_rank_active(ptrs.active_rank_mask, target_rank);\n }\n\n int dst_token_idx = -1;\n if (is_valid) {\n dst_token_idx = atomicAdd(&ptrs.send_counters[target_rank], 1);\n if constexpr (COMPACT_EP4) {\n smem_compact_send_indices[target_rank] = dst_token_idx;\n }\n } else {\n target_rank = -1;\n }\n\n ptrs.topk_target_ranks[local_token_idx * TOP_K + k] = target_rank;\n ptrs.topk_send_indices[local_token_idx * TOP_K + k] = dst_token_idx;\n if constexpr (!COMPACT_EP4) {\n smem_topk_target_ranks[k] = target_rank;\n smem_topk_send_indices[k] = dst_token_idx;\n }\n }\n }\n // Sync before dispatching data\n __syncthreads();\n\n // EP4 has at most four unique destinations, regardless of TOP_K. The compact\n // specialization avoids expanding those destinations back to TOP_K entries.\n constexpr int NUM_DESTINATIONS = COMPACT_EP4 ? kEp4Size : TOP_K;\n int target_ranks[NUM_DESTINATIONS];\n int send_indices[NUM_DESTINATIONS];\n if constexpr (COMPACT_EP4) {\n#pragma unroll\n for (int target_rank = 0; target_rank < NUM_DESTINATIONS; ++target_rank) {\n target_ranks[target_rank] = target_rank;\n send_indices[target_rank] = smem_compact_send_indices[target_rank];\n }\n } else {\n#pragma unroll\n for (int k = 0; k < TOP_K; ++k) {\n target_ranks[k] = smem_topk_target_ranks[k];\n send_indices[k] = smem_topk_send_indices[k];\n }\n }\n\n // Perform a single source load and fan out to each unique destination.\n for (int payload_idx = 0; payload_idx < num_payloads; payload_idx++) {\n uint8_t const* src_data = static_cast<uint8_t const*>(ptrs.src_data_ptrs[payload_idx]);\n int bytes_per_token = ptrs.payload_bytes_per_token[payload_idx];\n uint8_t const* src_ptr = src_data + local_token_idx * bytes_per_token;\n\n vectorized_dispatch<NUM_DESTINATIONS>(src_ptr, bytes_per_token, rank_id, max_tokens_per_rank,\n payload_idx, ptrs, target_ranks, send_indices);\n }\n\n __syncthreads();\n }\n\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n cudaTriggerProgrammaticLaunchCompletion();\n#endif\n\n bool is_first_warp = threadIdx.x / warpSize == 0;\n if (is_first_warp) {\n int lane_id = threadIdx.x % warpSize;\n\n bool is_last_token = false;\n if (lane_id == 0) {\n if (local_num_tokens != 0) {\n int cnt = atomicAdd(ptrs.local_token_counter, 1);\n is_last_token = cnt + 1 == local_num_tokens;\n } else {\n is_last_token = true;\n }\n }\n is_last_token = __shfl_sync(0xffffffff, is_last_token, 0);\n\n if (is_last_token) {\n// Store send_counters to recv_counters.\n// Skip masked target ranks: their symmetric memory may be inaccessible.\n#pragma unroll 1 // No unroll as one iter is typically enough\n for (int target_rank = lane_id; target_rank < ep_size; target_rank += warpSize) {\n if constexpr (ENABLE_RANK_MASK) {\n if (!is_rank_active(ptrs.active_rank_mask, target_rank)) continue;\n }\n int send_count = ptrs.send_counters[target_rank];\n ptrs.recv_counters[target_rank][rank_id] = send_count;\n }\n\n if constexpr (ENABLE_EPLB) {\n // Write local stats into peer buffers before the release fence below.\n // Skip masked target ranks for the same reason as above.\n#pragma unroll 1\n for (int target_rank = 0; target_rank < ep_size; ++target_rank) {\n if constexpr (ENABLE_RANK_MASK) {\n if (!is_rank_active(ptrs.active_rank_mask, target_rank)) continue;\n }\n int* target_stats = ptrs.eplb_gathered_stats[target_rank];\n for (int expert_id = lane_id; expert_id < eplb_stats_num_experts; expert_id += warpSize) {\n int stat_val = ptrs.eplb_local_stats[expert_id];\n target_stats[rank_id * eplb_stats_num_experts + expert_id] = stat_val;\n }\n }\n }\n\n#if !DISABLE_SYNC_FOR_PROFILING\n uint32_t expected_value = *ptrs.flag_val;\n\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"fence.release.sys;\");\n#else\n __threadfence_system();\n#endif\n// Signal completion to all active peers; skip dead ranks (their symmetric memory is\n// unreachable).\n#pragma unroll 1 // No unroll as one iter is typically enough\n for (int target_rank = lane_id; target_rank < ep_size; target_rank += warpSize) {\n if constexpr (ENABLE_RANK_MASK) {\n if (!is_rank_active(ptrs.active_rank_mask, target_rank)) continue;\n }\n uint32_t* flag_addr = &ptrs.completion_flags[target_rank][rank_id];\n asm volatile(\"st.relaxed.sys.u32 [%0], %1;\" ::\"l\"(flag_addr), \"r\"(expected_value));\n\n#if ENABLE_DEBUG_PRINT\n printf(\"dispatch: +++Rank %d setting completion flag to %d for rank %d\\n\", rank_id,\n expected_value, target_rank);\n#endif\n }\n\n// Wait for all active peers to signal; skip dead ranks (otherwise we would spin forever —\n// this is the bug the rank-mask is here to prevent).\n#pragma unroll 1 // No unroll\n for (int peer_rank = lane_id; peer_rank < ep_size; peer_rank += warpSize) {\n if constexpr (ENABLE_RANK_MASK) {\n if (!is_rank_active(ptrs.active_rank_mask, peer_rank)) continue;\n }\n bool flag_set = false;\n [[maybe_unused]] auto s = clock64();\n do {\n uint32_t* flag_ptr = &ptrs.completion_flags[rank_id][peer_rank];\n uint32_t flag_value;\n // Acquire load to ensure visibility of peer's release-store\n asm volatile(\"ld.relaxed.sys.u32 %0, [%1];\" : \"=r\"(flag_value) : \"l\"(flag_ptr));\n#if ENABLE_DEBUG_PRINT\n printf(\n \"dispatch: ---Rank %d received completion flag from rank %d, flag_value: %d, \"\n \"expected_value: \"\n \"%d, address: %p\\n\",\n rank_id, peer_rank, flag_value, expected_value, flag_ptr);\n#endif\n flag_set = flag_value == expected_value;\n } while (!flag_set && !check_timeout(s));\n\n if (__builtin_expect(!flag_set, 0)) {\n printf(\"dispatch: ---Rank %d timed out waiting for completion flag from rank %d\\n\",\n rank_id, peer_rank);\n asm volatile(\"trap;\");\n return;\n }\n }\n // asm volatile(\"fence.acquire.sys;\");\n#endif\n }\n }\n}\n\nvoid moe_a2a_prepare_dispatch_launch(MoeA2ADispatchParams const& params) {\n launchWithPdlWhenEnabled(\"moeA2APrepareDispatchKernel\", params.enable_pdl,\n moeA2APrepareDispatchKernel, 1, params.ep_size, 0, params.stream,\n params.send_counters, params.local_token_counter, params.ep_size,\n params.flag_val, params.enable_pdl);\n}\n\n// ============================================================================\n// Launch Functions\n// ============================================================================\n\nvoid moe_a2a_dispatch_launch(MoeA2ADispatchParams const& params) {\n // Validate parameters\n TLLM_CHECK(params.top_k > 0 && params.top_k <= kMaxTopK);\n TLLM_CHECK(params.ep_size > 0 && params.ep_size <= kMaxRanks);\n TLLM_CHECK(params.ep_rank >= 0 && params.ep_rank < params.ep_size);\n TLLM_CHECK(params.local_num_tokens >= 0);\n TLLM_CHECK(params.num_payloads > 0 && params.num_payloads <= kMaxPayloads);\n if (params.enable_rank_mask) {\n // The local rank must always be marked active in its own view of the mask; otherwise the\n // kernel itself would be running on a \"dead\" rank.\n TLLM_CHECK_WITH_INFO(\n (params.active_rank_mask[params.ep_rank >> 6] >> (params.ep_rank & 63)) & 1ULL,\n \"active_rank_mask must mark the local ep_rank (%d) as active\", params.ep_rank);\n }\n\n // Prepare kernel pointers struct\n DispatchKernelPointers kernel_ptrs = {};\n\n // Fill source data pointers and payload sizes\n for (int i = 0; i < params.num_payloads; i++) {\n kernel_ptrs.src_data_ptrs[i] = params.payloads[i].src_data;\n kernel_ptrs.payload_bytes_per_token[i] =\n params.payloads[i].element_size * params.payloads[i].elements_per_token;\n }\n\n // Fill receive buffer pointers\n for (int target_rank = 0; target_rank < params.ep_size; target_rank++) {\n kernel_ptrs.recv_counters[target_rank] = params.recv_counters[target_rank];\n kernel_ptrs.eplb_gathered_stats[target_rank] = params.eplb_gathered_stats[target_rank];\n for (int payload = 0; payload < params.num_payloads; payload++) {\n kernel_ptrs.recv_buffers[target_rank][payload] = params.recv_buffers[target_rank][payload];\n }\n }\n\n // Copy completion flag pointers\n for (int i = 0; i < params.ep_size; i++) {\n kernel_ptrs.completion_flags[i] = params.completion_flags[i];\n }\n kernel_ptrs.flag_val = params.flag_val;\n\n // Copy communication tracking pointers\n kernel_ptrs.send_counters = params.send_counters;\n kernel_ptrs.local_token_counter = params.local_token_counter;\n kernel_ptrs.topk_target_ranks = params.topk_target_ranks;\n kernel_ptrs.topk_send_indices = params.topk_send_indices;\n kernel_ptrs.eplb_local_stats = params.eplb_local_stats;\n\n // Copy active-rank bitmask into the kernel pointers struct\n for (int w = 0; w < kRankMaskWords; ++w) {\n kernel_ptrs.active_rank_mask[w] = params.active_rank_mask[w];\n }\n\n int block_size = tensorrt_llm::common::getEnvMoeA2ADispatchBlockSize();\n\n bool const use_compact_ep4 = params.ep_size == kEp4Size && params.top_k > kEp4Size;\n\n int max_payload_bytes_per_token = 0;\n for (int i = 0; i < params.num_payloads; ++i) {\n if (kernel_ptrs.payload_bytes_per_token[i] > max_payload_bytes_per_token) {\n max_payload_bytes_per_token = kernel_ptrs.payload_bytes_per_token[i];\n }\n }\n // Small payloads do not have enough 16-byte vectors to use larger CTAs. A GB200\n // sweep found 128 threads faster than both 64 and 256 at prefill token counts.\n if (use_compact_ep4 && max_payload_bytes_per_token <= kCompactDispatchMaxPayloadBytes &&\n block_size > kCompactDispatchBlockSize) {\n block_size = kCompactDispatchBlockSize;\n }\n\n // Configure kernel launch: one block per token\n int grid_size = params.local_num_tokens;\n // If local_num_tokens is 0, we still need to launch a minimal kernel to participate in the\n // synchronization.\n if (grid_size == 0) {\n grid_size = 1;\n }\n SWITCH_BOOL(params.enable_rank_mask, ENABLE_RANK_MASK, {\n SWITCH_BOOL(params.enable_eplb, EPLB_STATS, {\n if (use_compact_ep4) {\n int shared_bytes = kEp4Size * (int)sizeof(int);\n SWITCH_TOP_K(\n params.top_k, TOP_K, if constexpr (TOP_K > kEp4Size) {\n auto kernel_fn = moeA2ADispatchKernel<TOP_K, EPLB_STATS, ENABLE_RANK_MASK, true>;\n launchWithPdlWhenEnabled(\n \"moeA2ADispatchKernel\", params.enable_pdl, kernel_fn, grid_size, block_size,\n shared_bytes, params.stream, params.token_selected_experts, kernel_ptrs,\n params.num_payloads, params.max_tokens_per_rank, params.local_num_tokens,\n params.ep_rank, params.ep_size, params.num_experts, params.eplb_stats_num_experts,\n params.enable_pdl);\n })\n } else {\n int shared_bytes = 2 * params.top_k * (int)sizeof(int);\n SWITCH_TOP_K(params.top_k, TOP_K, {\n auto kernel_fn = moeA2ADispatchKernel<TOP_K, EPLB_STATS, ENABLE_RANK_MASK, false>;\n launchWithPdlWhenEnabled(\"moeA2ADispatchKernel\", params.enable_pdl, kernel_fn, grid_size,\n block_size, shared_bytes, params.stream,\n params.token_selected_experts, kernel_ptrs, params.num_payloads,\n params.max_tokens_per_rank, params.local_num_tokens,\n params.ep_rank, params.ep_size, params.num_experts,\n params.eplb_stats_num_experts, params.enable_pdl);\n });\n }\n });\n })\n}\n\n// ============================================================================\n// Combine kernels\n// ============================================================================\n\n// Accumulate across all valid ranks into float32 registers, then store as T (QuantMode==NONE)\n// or quantize the result to MXFP8 with a per-block scale factor (QuantMode==MXFP8).\n//\n// InT: input element type in the recv buffer (defaults to T for same-type accumulation;\n// __nv_fp8_e4m3 for the low-precision combine path). sizeof(InT) must divide VEC_SIZE_BYTES.\n// T: output / accumulation-cast element type (and the input type when InT == T).\n//\n// Unified path: load VEC_SIZE_BYTES bytes, reinterpret as InT[elems_per_vec], accumulate as\n// float32, then either cast_store as T (NONE) or convert to MXFP8 + emit the block scale factor\n// (MXFP8, which always uses InT == T). Block-per-token indexing\n// (threadIdx.x/blockDim.x/blockIdx.x).\ntemplate <int VEC_SIZE_BYTES, int TOP_K, typename T, typename InT = T,\n MoeA2ACombineQuantMode QuantMode = MoeA2ACombineQuantMode::NONE,\n MoeA2ACombineSwizzleSFMode SwizzleMode = MoeA2ACombineSwizzleSFMode::LINEAR>\n__device__ void vectorized_combine_impl(void* output_buffer, void* sf_output, int row_idx,\n int row_size, int stride_per_token, int rank_id,\n int max_tokens_per_rank, CombineKernelPointers const& ptrs,\n float OutputScalarScale = 1.0f) {\n using flashinfer::vec_t;\n\n // elems_per_vec: number of InT elements per VEC_SIZE_BYTES-byte load (constexpr).\n constexpr int elems_per_vec = VEC_SIZE_BYTES / static_cast<int>(sizeof(InT));\n // size_per_token: byte span of one token in the recv buffer (InT-typed).\n const int size_per_token = row_size * static_cast<int>(sizeof(InT));\n\n // Output base pointers. NONE writes T elements; MXFP8 writes packed fp8 bytes.\n T* dst_typed_base = nullptr;\n uint8_t* dst_bytes = nullptr;\n if constexpr (QuantMode == MoeA2ACombineQuantMode::NONE) {\n dst_typed_base = static_cast<T*>(output_buffer) + static_cast<size_t>(row_idx) * row_size;\n } else {\n // MXFP8 stores one byte per logical element; FP4 packs two e2m1 values per byte, so its\n // rows are half as wide. The accumulation still reads InT-sized inputs either way.\n size_t const bytes_per_row = QuantMode == MoeA2ACombineQuantMode::MXFP8\n ? static_cast<size_t>(row_size)\n : static_cast<size_t>(row_size) / 2;\n dst_bytes = static_cast<uint8_t*>(output_buffer) + static_cast<size_t>(row_idx) * bytes_per_row;\n }\n\n int const stride = blockDim.x * VEC_SIZE_BYTES;\n int const local_token_idx = blockIdx.x;\n\n // offset is a byte offset into the recv buffer, stepping by VEC_SIZE_BYTES bytes.\n for (int offset = threadIdx.x * VEC_SIZE_BYTES; offset < size_per_token; offset += stride) {\n int logical_offset = offset / static_cast<int>(sizeof(InT));\n // Per-k vec_t<float, elems_per_vec> accumulators, zero-initialised via fill().\n vec_t<float, elems_per_vec> acc[TOP_K];\n\n // Pass 1: issue all TOP_K loads back-to-back without any type conversion.\n // Raw InT bytes are loaded directly into acc[k]'s register storage, reinterpreted as\n // vec_t<InT, elems_per_vec> (VEC_SIZE_BYTES bytes, fitting in the low end of acc[k]'s\n // sizeof(float)*elems_per_vec allocation). Separating load from cast lets the compiler\n // schedule all VEC_SIZE_BYTES-byte global loads consecutively, hiding memory latency across k.\n#pragma unroll\n for (int k = 0; k < TOP_K; ++k) {\n int target_rank = ptrs.topk_target_ranks[local_token_idx * TOP_K + k];\n int dst_idx = ptrs.topk_send_indices[local_token_idx * TOP_K + k];\n // dst_idx < 0: duplicate/dead-target sentinel already set by dispatch (which consults\n // active_rank_mask once per token). Rechecking is_rank_active here is redundant and,\n // being on the per-k vectorized hot path, measurably regresses combine throughput.\n if (dst_idx < 0) {\n acc[k].fill(0.0f);\n continue;\n }\n\n uint8_t const* recv_buffer = static_cast<uint8_t const*>(ptrs.recv_buffers[target_rank][0]);\n size_t base_source_rank =\n static_cast<size_t>(rank_id) * static_cast<size_t>(max_tokens_per_rank) +\n static_cast<size_t>(dst_idx);\n // stride_per_token: byte distance between tokens in the recv buffer.\n // Equals size_per_token for normal cases; may differ for FP8 in-place\n // (BF16-stride workspace but FP8-sized payload).\n size_t base_token = base_source_rank * static_cast<size_t>(stride_per_token);\n\n reinterpret_cast<vec_t<InT, elems_per_vec>&>(acc[k]).load(\n reinterpret_cast<InT const*>(recv_buffer + base_token + offset));\n }\n\n // Pass 2: in-place cast InT → float, iterating j in descending order.\n // float[j] occupies bytes [j*4, j*4+3]; InT[j] occupies [j*sizeof(InT), ...).\n // For sizeof(InT) < sizeof(float), high-j float writes land above all remaining\n // InT bytes, so descending order is always write-after-read safe.\n#pragma unroll\n for (int k = 0; k < TOP_K; ++k) {\n if (ptrs.topk_send_indices[local_token_idx * TOP_K + k] < 0)\n continue; // acc[k] already holds 0.0f from fill() above\n#pragma unroll\n for (int j = elems_per_vec - 1; j >= 0; --j)\n acc[k][j] = static_cast<float>(reinterpret_cast<InT const*>(&acc[k])[j]);\n }\n // Reduce acc[TOP_K] into acc[0] via unrolled tree-reduction.\n // acc[k][j] uses vec_t::operator[] which returns float& — no indirection overhead.\n if constexpr (TOP_K == 22) {\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[1][j];\n acc[2][j] += acc[3][j];\n acc[4][j] += acc[5][j];\n acc[6][j] += acc[7][j];\n acc[8][j] += acc[9][j];\n acc[10][j] += acc[11][j];\n acc[12][j] += acc[13][j];\n acc[14][j] += acc[15][j];\n acc[16][j] += acc[17][j];\n acc[18][j] += acc[19][j];\n acc[20][j] += acc[21][j];\n }\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[2][j];\n acc[4][j] += acc[6][j];\n acc[8][j] += acc[10][j];\n acc[12][j] += acc[14][j];\n acc[16][j] += acc[18][j];\n }\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[4][j];\n acc[8][j] += acc[12][j];\n acc[16][j] += acc[20][j];\n }\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[8][j];\n acc[0][j] += acc[16][j];\n }\n } else if constexpr (TOP_K == 16) {\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[1][j];\n acc[2][j] += acc[3][j];\n acc[4][j] += acc[5][j];\n acc[6][j] += acc[7][j];\n acc[8][j] += acc[9][j];\n acc[10][j] += acc[11][j];\n acc[12][j] += acc[13][j];\n acc[14][j] += acc[15][j];\n }\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[2][j];\n acc[4][j] += acc[6][j];\n acc[8][j] += acc[10][j];\n acc[12][j] += acc[14][j];\n }\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[4][j];\n acc[8][j] += acc[12][j];\n }\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[8][j];\n }\n } else if constexpr (TOP_K == 10) {\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[1][j];\n acc[2][j] += acc[3][j];\n acc[4][j] += acc[5][j];\n acc[6][j] += acc[7][j];\n acc[8][j] += acc[9][j];\n }\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[2][j];\n acc[4][j] += acc[6][j];\n }\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[4][j];\n acc[0][j] += acc[8][j];\n }\n } else if constexpr (TOP_K == 8) {\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[1][j];\n acc[2][j] += acc[3][j];\n acc[4][j] += acc[5][j];\n acc[6][j] += acc[7][j];\n }\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[2][j];\n acc[4][j] += acc[6][j];\n }\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[4][j];\n }\n } else if constexpr (TOP_K == 6) {\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[1][j];\n acc[2][j] += acc[3][j];\n acc[4][j] += acc[5][j];\n }\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[2][j];\n acc[0][j] += acc[4][j];\n }\n } else if constexpr (TOP_K == 4) {\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[1][j];\n acc[2][j] += acc[3][j];\n }\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[2][j];\n }\n } else if constexpr (TOP_K == 2) {\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[1][j];\n }\n } else if constexpr (TOP_K == 1) {\n // nothing to do\n } else {\n // Generic fallback: accumulate all into acc[0]\n#pragma unroll\n for (int k = 1; k < TOP_K; ++k) {\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n acc[0][j] += acc[k][j];\n }\n }\n }\n // Epilogue: store the float accumulator as T (NONE) or quantize to MXFP8 + scale factor.\n if constexpr (QuantMode == MoeA2ACombineQuantMode::NONE) {\n // cast_store: converts float->T element-by-element then writes via vectorized int4 store.\n acc[0].cast_store(dst_typed_base + offset / static_cast<int>(sizeof(InT)));\n } else {\n constexpr uint32_t sf_vec_size = QuantMode == MoeA2ACombineQuantMode::NVFP4 ? 16 : 32;\n constexpr uint32_t threads_per_sf = sf_vec_size / elems_per_vec;\n uint8_t scale;\n auto store_sf = [&]() {\n int64_t sf_offset;\n const int64_t num_vecs_per_row = (row_size + sf_vec_size - 1) / sf_vec_size;\n const int64_t sf_idx = logical_offset / sf_vec_size;\n if constexpr (SwizzleMode == MoeA2ACombineSwizzleSFMode::LINEAR) {\n sf_offset = row_idx * num_vecs_per_row + sf_idx;\n } else if constexpr (SwizzleMode == MoeA2ACombineSwizzleSFMode::SWIZZLE_128x4) {\n sf_offset = get_sf_out_offset_128x4(row_idx, sf_idx, num_vecs_per_row);\n } else { // SWIZZLE_8x4\n sf_offset = get_sf_out_offset_8x4(row_idx, sf_idx, num_vecs_per_row);\n }\n if (threadIdx.x % threads_per_sf == 0) {\n reinterpret_cast<uint8_t*>(sf_output)[sf_offset] = scale;\n }\n };\n // Cast the float32 accumulator down to T to feed the MXFP8/FP4 converter's PackedVec input.\n tensorrt_llm::kernels::PackedVec<T, elems_per_vec> packed_vec;\n T* packed_elems = reinterpret_cast<T*>(&packed_vec);\n#pragma unroll\n for (int j = 0; j < elems_per_vec; ++j) {\n packed_elems[j] = static_cast<T>(acc[0][j]);\n }\n if constexpr (QuantMode == MoeA2ACombineQuantMode::MXFP8) {\n static_assert(elems_per_vec == 8, \"MXFP8 quantization requires 8 elements per vector\");\n uint64_t fp8x8 =\n tensorrt_llm::kernels::cvt_warp_fp16_to_mxfp8<T, 32, elems_per_vec>(packed_vec, &scale);\n reinterpret_cast<uint64_t*>(dst_bytes)[logical_offset / elems_per_vec] = fp8x8;\n } else if constexpr (QuantMode == MoeA2ACombineQuantMode::NVFP4 ||\n QuantMode == MoeA2ACombineQuantMode::MXFP4) {\n static_assert(elems_per_vec == 8 || elems_per_vec == 16,\n \"FP4 quantization requires 8 or 16 elements per vector\");\n constexpr int SF_VEC_SIZE = QuantMode == MoeA2ACombineQuantMode::MXFP4 ? 32 : 16;\n auto fp4_packed = tensorrt_llm::kernels::cvt_warp_fp16_to_fp4 < T, SF_VEC_SIZE,\n elems_per_vec,\n QuantMode == MoeA2ACombineQuantMode::MXFP4 > (packed_vec, OutputScalarScale, &scale);\n // cvt_warp_fp16_to_fp4 returns uint32_t for 8 elems (4 packed bytes) and uint64_t for 16\n // (8 packed bytes); store at the matching width so packed rows stay contiguous and fit the\n // dim/2-byte output buffer (a wider store would overflow into the next token's row).\n reinterpret_cast<decltype(fp4_packed)*>(dst_bytes)[logical_offset / elems_per_vec] =\n fp4_packed;\n }\n store_sf();\n }\n }\n}\n\n// Wrapper that selects vector width based on size_per_token alignment.\n// QuantMode==NONE writes T (optionally upcast from an fp8 InT); QuantMode==MXFP8 writes packed\n// fp8 + scale factors (always InT == T, fixed 16-byte / 8-element vectors).\n// stride_per_token: byte distance between tokens in the recv buffer (may differ from\n// size_per_token when FP8 in-place uses a BF16-stride workspace with an FP8-sized payload).\n// InT: input element type in recv buffer (defaults to T for same-type accumulation).\ntemplate <int TOP_K, typename T, typename InT = T,\n MoeA2ACombineQuantMode QuantMode = MoeA2ACombineQuantMode::NONE,\n MoeA2ACombineSwizzleSFMode SwizzleMode = MoeA2ACombineSwizzleSFMode::LINEAR>\n__device__ void vectorized_combine(void* output_buffer, void* sf_output, int row_idx, int row_size,\n int stride_per_token, int rank_id, int max_tokens_per_rank,\n CombineKernelPointers const& ptrs,\n float OutputScalarScale = 1.0f) {\n const int size_per_token = row_size * static_cast<int>(sizeof(InT));\n if constexpr (QuantMode != MoeA2ACombineQuantMode::NONE) {\n // MXFP8/FP4 require 16-byte vectors (8 or 16 elements per vec), always InT == T.\n vectorized_combine_impl<16, TOP_K, T, InT, QuantMode, SwizzleMode>(\n output_buffer, sf_output, row_idx, row_size, stride_per_token, rank_id, max_tokens_per_rank,\n ptrs, OutputScalarScale);\n } else {\n // Each branch is guarded by if constexpr (sizeof(InT) <= VEC_SIZE_BYTES) so the compiler\n // never instantiates vectorized_combine_impl with elems_per_vec == 0.\n if (size_per_token % 16 == 0) {\n if constexpr (static_cast<int>(sizeof(InT)) <= 16)\n vectorized_combine_impl<16, TOP_K, T, InT>(output_buffer, nullptr, row_idx, row_size,\n stride_per_token, rank_id, max_tokens_per_rank,\n ptrs);\n } else if (size_per_token % 8 == 0) {\n if constexpr (static_cast<int>(sizeof(InT)) <= 8)\n vectorized_combine_impl<8, TOP_K, T, InT>(output_buffer, nullptr, row_idx, row_size,\n stride_per_token, rank_id, max_tokens_per_rank,\n ptrs);\n } else if (size_per_token % 4 == 0) {\n if constexpr (static_cast<int>(sizeof(InT)) <= 4)\n vectorized_combine_impl<4, TOP_K, T, InT>(output_buffer, nullptr, row_idx, row_size,\n stride_per_token, rank_id, max_tokens_per_rank,\n ptrs);\n } else if (size_per_token % 2 == 0) {\n if constexpr (static_cast<int>(sizeof(InT)) <= 2)\n vectorized_combine_impl<2, TOP_K, T, InT>(output_buffer, nullptr, row_idx, row_size,\n stride_per_token, rank_id, max_tokens_per_rank,\n ptrs);\n } else {\n if constexpr (static_cast<int>(sizeof(InT)) <= 1)\n vectorized_combine_impl<1, TOP_K, T, InT>(output_buffer, nullptr, row_idx, row_size,\n stride_per_token, rank_id, max_tokens_per_rank,\n ptrs);\n }\n }\n}\n\n// ---- vec_convert: per-vector type conversion, specialized by PTX where available ----\n// Generic: SrcT -> float -> DstT (all architectures, all type combinations).\ntemplate <size_t VEC_SIZE, typename SrcT, typename DstT>\n__device__ __forceinline__ void vec_convert(flashinfer::vec_t<DstT, VEC_SIZE>& out,\n flashinfer::vec_t<SrcT, VEC_SIZE> const& in) {\n#pragma unroll\n for (int j = 0; j < VEC_SIZE; ++j) out[j] = DstT(static_cast<float>(in[j]));\n}\n\n// BF16 -> FP8 e4m3: use CUDA intrinsic (SM100+, Blackwell).\n// Inline PTX \"cvt.rn.satfinite.e4m3x2.bf16x2 %h, %r\" is rejected by SM100a ptxas\n// (\"Unexpected instruction types for cvt\") because SM100a requires a 32-bit output\n// register for this instruction. __nv_fp8x2_e4m3(bfloat162) emits the correct form.\n#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)\ntemplate <size_t VEC_SIZE, std::enable_if_t<(VEC_SIZE % 2 == 0), int> = 0>\n__device__ __forceinline__ void vec_convert(flashinfer::vec_t<__nv_fp8_e4m3, VEC_SIZE>& out,\n flashinfer::vec_t<__nv_bfloat16, VEC_SIZE> const& in) {\n __nv_fp8x2_e4m3* out_fp8x2 = reinterpret_cast<__nv_fp8x2_e4m3*>(&out);\n __nv_bfloat162 const* in_bf16x2 = reinterpret_cast<__nv_bfloat162 const*>(&in);\n#pragma unroll\n for (int p = 0; p < static_cast<int>(VEC_SIZE) / 2; ++p)\n out_fp8x2[p] = __nv_fp8x2_e4m3(in_bf16x2[p]);\n}\n#endif\n\n// FP16 -> FP8 e4m3: paired PTX cvt.rn.satfinite.e4m3x2.f16x2 (SM89+, Hopper).\n#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 890)\ntemplate <size_t VEC_SIZE, std::enable_if_t<(VEC_SIZE % 2 == 0), int> = 0>\n__device__ __forceinline__ void vec_convert(flashinfer::vec_t<__nv_fp8_e4m3, VEC_SIZE>& out,\n flashinfer::vec_t<half, VEC_SIZE> const& in) {\n uint32_t const* src_u32 = reinterpret_cast<uint32_t const*>(&in);\n uint16_t* dst_u16 = reinterpret_cast<uint16_t*>(&out);\n#pragma unroll\n for (int p = 0; p < VEC_SIZE / 2; ++p) {\n uint16_t d;\n asm volatile(\"cvt.rn.satfinite.e4m3x2.f16x2 %0, %1;\" : \"=h\"(d) : \"r\"(src_u32[p]));\n dst_u16[p] = d;\n }\n}\n#endif\n\n// ---- vectorized_quant_impl: load -> sync -> convert -> store ----\n// VEC_SIZE is in elements (not bytes), so both SrcT and DstT vectors hold VEC_SIZE values.\n// Block-per-token: threadIdx.x indexes vectors within the token, blockDim.x is the stride.\ntemplate <int VEC_SIZE, typename SrcT, typename DstT>\n__device__ void vectorized_quant_impl(DstT* dst, SrcT const* src, int num_elements) {\n using flashinfer::vec_t;\n\n // num_elements is a multiple of VEC_SIZE here (selected by the wrapper).\n int const num_vecs = num_elements / VEC_SIZE;\n // Round the iteration bound up to a multiple of blockDim.x so every thread reaches the\n // __syncthreads() the same number of times (a divergent barrier would deadlock when\n // num_vecs is not a multiple of blockDim.x, e.g. hidden=7168 with 256 threads).\n int const vec_iters = ((num_vecs + blockDim.x - 1) / blockDim.x) * blockDim.x;\n\n for (int iter = threadIdx.x; iter < vec_iters; iter += blockDim.x) {\n bool const active = iter < num_vecs;\n int const e = iter * VEC_SIZE;\n vec_t<SrcT, VEC_SIZE> in_vec;\n if (active) in_vec.load(src + e);\n\n // Sync so all threads finish loading inputs before any thread writes output. This avoids\n // write-after-read hazards in the FP8 in-place case where this kernel's output is read as\n // input on the next iteration. All threads participate (active guards the work, not the sync).\n __syncthreads();\n\n if (active) {\n vec_t<DstT, VEC_SIZE> out_vec;\n vec_convert(out_vec, in_vec);\n out_vec.store(dst + e);\n }\n }\n}\n\ntemplate <typename SrcT, typename DstT>\n__device__ void vectorized_quant(DstT* dst, SrcT const* src, int num_elements) {\n if (num_elements % 16 == 0)\n vectorized_quant_impl<16, SrcT, DstT>(dst, src, num_elements);\n else if (num_elements % 8 == 0)\n vectorized_quant_impl<8, SrcT, DstT>(dst, src, num_elements);\n else if (num_elements % 4 == 0)\n vectorized_quant_impl<4, SrcT, DstT>(dst, src, num_elements);\n else if (num_elements % 2 == 0)\n vectorized_quant_impl<2, SrcT, DstT>(dst, src, num_elements);\n else\n vectorized_quant_impl<1, SrcT, DstT>(dst, src, num_elements);\n}\n\n// LOW_PRECISION=false: vectorized byte-copy (SrcT = payload dtype).\n// LOW_PRECISION=true: vectorized SrcT->FP8 quantization via vectorized_quant<SrcT, fp8_e4m3>.\n// stride_per_token: byte distance between tokens in recv_buffer_bytes (host-computed, avoids\n// per-thread recomputation):\n// - FP8 external payload: elements_per_token x 1 (compact FP8 layout)\n// - FP8 in-place / byte-copy: elements_per_token x sizeof(SrcT) (payload-dtype stride)\n// Copy payload to recv buffer; one block per token.\ntemplate <bool LOW_PRECISION, typename SrcT>\n__global__ void moeA2APrepareCombineKernel(uint8_t* recv_buffer_bytes, void const* payload,\n int elements_per_token, int ep_size,\n int max_tokens_per_rank, uint32_t* flag_val_ptr,\n int const* recv_counters, int stride_per_token,\n bool enable_pdl) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n if (enable_pdl) cudaGridDependencySynchronize();\n cudaTriggerProgrammaticLaunchCompletion();\n#endif\n\n if (blockIdx.x == 0 && threadIdx.x == 0) {\n // Increment flag_val for this combine round\n *flag_val_ptr = *flag_val_ptr + 1;\n }\n\n // Copy path: null payload means data is already in workspace — nothing to do.\n if (!LOW_PRECISION && payload == nullptr) return;\n\n int global_token_idx = blockIdx.x;\n\n int global_token_num = ep_size * max_tokens_per_rank;\n if (global_token_idx >= global_token_num) return;\n\n // Map global_token_idx to (rank_idx, local_token_idx)\n int rank_idx = global_token_idx / max_tokens_per_rank;\n int local_token_idx = global_token_idx % max_tokens_per_rank;\n\n // Skip invalid tokens beyond per-rank recv count\n if (local_token_idx >= recv_counters[rank_idx]) return;\n\n size_t const token_offset = static_cast<size_t>(global_token_idx) * stride_per_token;\n\n if constexpr (LOW_PRECISION) {\n // Source pointer: external payload or in-place from workspace.\n SrcT const* src_ptr = (payload != nullptr)\n ? static_cast<SrcT const*>(payload) +\n static_cast<size_t>(global_token_idx) * elements_per_token\n : reinterpret_cast<SrcT const*>(recv_buffer_bytes + token_offset);\n\n // Destination: stride_per_token encodes the correct layout for both paths\n // (compact FP8 for external, payload-dtype stride for in-place).\n __nv_fp8_e4m3* dst_ptr = reinterpret_cast<__nv_fp8_e4m3*>(recv_buffer_bytes + token_offset);\n\n vectorized_quant<SrcT, __nv_fp8_e4m3>(dst_ptr, src_ptr, elements_per_token);\n } else {\n // Generic byte copy (payload guaranteed non-null by early return above).\n vectorized_copy(recv_buffer_bytes + token_offset,\n static_cast<uint8_t const*>(payload) + token_offset, stride_per_token);\n }\n}\n\n// ============================================================================\n// Generic Combine Kernel Implementation (Templated by data type)\n// ============================================================================\n\ntemplate <typename T, int TOP_K, bool ENABLE_RANK_MASK,\n MoeA2ACombineQuantMode QuantMode = MoeA2ACombineQuantMode::NONE,\n MoeA2ACombineSwizzleSFMode SwizzleMode = MoeA2ACombineSwizzleSFMode::LINEAR>\n__global__ void moeA2ACombineKernel(\n const CombineKernelPointers ptrs, // Combine-specific struct, src_data_ptrs[0] is output\n int max_tokens_per_rank, int elements_per_token, int stride_per_token, int local_num_tokens,\n int rank_id, int ep_size, bool enable_pdl, float OutputScalarScale) {\n int local_token_idx = blockIdx.x;\n\n if (local_num_tokens == 0) {\n // Special case: If local_num_tokens == 0,\n // we need to keep the threads where local_token_idx == 0 alive to participate in the\n // synchronization. Other threads should return.\n if (local_token_idx > 0) return;\n } else {\n // Threads that do not have a token to process should return.\n if (local_token_idx >= local_num_tokens) return;\n }\n\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n if (enable_pdl) cudaGridDependencySynchronize();\n#endif\n\n#if !DISABLE_SYNC_FOR_PROFILING\n // In-kernel readiness synchronization at start of combine:\n // - One warp signals readiness to all peers with current flag_val.\n // - The first warp of each block waits for all peers' readiness (equality), then __syncthreads.\n bool is_first_warp = threadIdx.x / warpSize == 0;\n if (is_first_warp) {\n int lane_id = threadIdx.x % warpSize;\n uint32_t expected_value = *ptrs.flag_val;\n\n if (blockIdx.x == 0) {\n // asm volatile(\"fence.release.sys;\");\n // Signal readiness to all active peers; skip dead ranks (their symmetric memory is\n // unreachable).\n#pragma unroll 1 // No unroll\n for (int peer_rank = lane_id; peer_rank < ep_size; peer_rank += warpSize) {\n if constexpr (ENABLE_RANK_MASK) {\n if (!is_rank_active(ptrs.active_rank_mask, peer_rank)) continue;\n }\n uint32_t* flag_addr = &ptrs.completion_flags[peer_rank][rank_id];\n asm volatile(\"st.relaxed.sys.u32 [%0], %1;\" ::\"l\"(flag_addr), \"r\"(expected_value));\n#if ENABLE_DEBUG_PRINT\n printf(\"combine: +++Rank %d setting completion flag to %d for rank %d\\n\", rank_id,\n expected_value, peer_rank);\n#endif\n }\n }\n\n// Wait for all active peers to signal; skip dead ranks (otherwise we would spin forever —\n// this is the bug the rank-mask is here to prevent).\n#pragma unroll 1 // No unroll\n for (int peer_rank = lane_id; peer_rank < ep_size; peer_rank += warpSize) {\n if constexpr (ENABLE_RANK_MASK) {\n if (!is_rank_active(ptrs.active_rank_mask, peer_rank)) continue;\n }\n bool flag_set = false;\n [[maybe_unused]] auto s = clock64();\n do {\n uint32_t* flag_ptr = &ptrs.completion_flags[rank_id][peer_rank];\n uint32_t flag_value;\n // Acquire load to ensure visibility of peer's release-store\n asm volatile(\"ld.relaxed.sys.u32 %0, [%1];\" : \"=r\"(flag_value) : \"l\"(flag_ptr));\n#if ENABLE_DEBUG_PRINT\n printf(\n \"combine: ---Rank %d received completion flag from rank %d, flag_value: %d, \"\n \"expected_value: %d, \"\n \"address: %p\\n\",\n rank_id, peer_rank, flag_value, expected_value, flag_ptr);\n#endif\n flag_set = flag_value == expected_value;\n } while (!flag_set && !check_timeout(s));\n\n if (__builtin_expect(!flag_set, 0)) {\n printf(\"combine: ---Rank %d timed out waiting for completion flag from rank %d\\n\", rank_id,\n peer_rank);\n asm volatile(\"trap;\");\n return;\n }\n }\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"fence.acquire.sys;\");\n#else\n __threadfence_system();\n#endif\n }\n __syncthreads();\n#endif\n\n if (local_num_tokens == 0) return;\n\n // Dispatch the combine path:\n // - T == fp8_e4m3: low-precision combine, FP8 recv buffer -> BF16 output (InT=fp8, NONE quant).\n // - otherwise: same-type accumulate, then store as T (NONE) or quantize to MXFP8/FP4\n // (QuantMode).\n // vectorized_combine derives the per-token output pointer from row_idx (= local_token_idx).\n if constexpr (std::is_same_v<T, __nv_fp8_e4m3>) {\n // src_data_ptrs[0] points to a BF16 output buffer (set by moeA2ACombineOp for low precision).\n vectorized_combine<TOP_K, __nv_bfloat16, __nv_fp8_e4m3>(\n ptrs.src_data_ptrs[0], nullptr, local_token_idx, elements_per_token, stride_per_token,\n rank_id, max_tokens_per_rank, ptrs);\n } else {\n vectorized_combine<TOP_K, T, T, QuantMode, SwizzleMode>(\n ptrs.src_data_ptrs[0], ptrs.output_scales, local_token_idx, elements_per_token,\n stride_per_token, rank_id, max_tokens_per_rank, ptrs, OutputScalarScale);\n }\n\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n if (enable_pdl) cudaTriggerProgrammaticLaunchCompletion();\n#endif\n}\n\nvoid moe_a2a_prepare_combine_launch(MoeA2ACombineParams const& params) {\n constexpr int kBlockSize = 256;\n\n // FP8 in-place (use_low_precision, prepare_payload==nullptr): each CTA writes FP8 at the\n // BF16-stride position, so CTAs never race — all tokens must be processed. Copy path with a\n // null payload is a no-op; 1 block suffices for the flag increment only.\n int grid = (params.use_low_precision || params.prepare_payload != nullptr)\n ? params.ep_size * params.max_tokens_per_rank\n : 1;\n\n uint8_t* recv_buffer_bytes =\n static_cast<uint8_t*>(const_cast<void*>(params.recv_buffers[params.ep_rank]));\n void const* payload = params.prepare_payload;\n\n // stride_per_token (host-computed, avoids per-thread recompute):\n // FP8 external: EPT x 1 (compact FP8, dst packed tightly)\n // FP8 in-place / byte-copy: EPT x sizeof(SrcT) (payload-dtype stride)\n SWITCH_BOOL(params.use_low_precision, LOW_PRECISION, {\n SWITCH_DTYPE(params.dtype, SrcT, {\n bool const low_precision_staged = LOW_PRECISION && (params.prepare_payload != nullptr);\n int const stride_per_token = low_precision_staged\n ? params.elements_per_token\n : params.elements_per_token * static_cast<int>(sizeof(SrcT));\n auto kernel_fn = moeA2APrepareCombineKernel<LOW_PRECISION, SrcT>;\n launchWithPdlWhenEnabled(\"moeA2APrepareCombineKernel\", params.enable_pdl, kernel_fn, grid,\n kBlockSize, 0, params.stream, recv_buffer_bytes, payload,\n params.elements_per_token, params.ep_size,\n params.max_tokens_per_rank, params.flag_val, params.recv_counters,\n stride_per_token, params.enable_pdl);\n });\n });\n}\n\n// ============================================================================\n// Combine Launch Function\n// ============================================================================\n\nvoid moe_a2a_combine_launch(MoeA2ACombineParams const& params) {\n // Validate parameters\n TLLM_CHECK(params.top_k > 0 && params.top_k <= kMaxTopK);\n TLLM_CHECK(params.ep_size > 0 && params.ep_size <= kMaxRanks);\n TLLM_CHECK(params.ep_rank >= 0 && params.ep_rank < params.ep_size);\n TLLM_CHECK(params.local_num_tokens >= 0);\n TLLM_CHECK(params.elements_per_token > 0);\n if (params.enable_rank_mask) {\n // The local rank must always be marked active in its own view of the mask; otherwise the\n // kernel itself would be running on a \"dead\" rank.\n TLLM_CHECK_WITH_INFO(\n (params.active_rank_mask[params.ep_rank >> 6] >> (params.ep_rank & 63)) & 1ULL,\n \"active_rank_mask must mark the local ep_rank (%d) as active\", params.ep_rank);\n }\n\n // Configure kernel launch: one block per token\n int const kBlockSize = tensorrt_llm::common::getEnvMoeA2ACombineBlockSize();\n int grid_size_block = params.local_num_tokens;\n // If local_num_tokens is 0, we still need to launch a minimal kernel to participate in the\n // synchronization.\n if (grid_size_block == 0) {\n grid_size_block = 1;\n }\n\n // Prepare kernel pointers struct for combine\n CombineKernelPointers kernel_ptrs = {}; // Zero-initialize\n\n // Set output data pointer in src_data_ptrs[0]\n kernel_ptrs.src_data_ptrs[0] = params.output_data;\n kernel_ptrs.output_scales = params.output_scales;\n\n // Fill recv buffer pointers\n for (int rank = 0; rank < params.ep_size; rank++) {\n kernel_ptrs.recv_buffers[rank][0] = params.recv_buffers[rank];\n }\n\n // Copy completion flag pointers\n for (int i = 0; i < params.ep_size; i++) {\n kernel_ptrs.completion_flags[i] = params.completion_flags[i];\n }\n kernel_ptrs.flag_val = params.flag_val;\n\n // Copy communication tracking pointers\n kernel_ptrs.topk_target_ranks = params.topk_target_ranks;\n kernel_ptrs.topk_send_indices = params.topk_send_indices;\n\n // Copy active-rank bitmask into the kernel pointers struct\n for (int w = 0; w < kRankMaskWords; ++w) {\n kernel_ptrs.active_rank_mask[w] = params.active_rank_mask[w];\n }\n\n int grid = grid_size_block; // one block per token\n\n // stride_per_token: byte distance between tokens in the recv buffer.\n // FP8 external payload: EPT × 1 (compact FP8 layout)\n // FP8 in-place / non-FP8: EPT × sizeof(PayloadT) (payload-dtype stride)\n bool const low_precision_staged = params.use_low_precision && (params.prepare_payload != nullptr);\n int stride_per_token;\n SWITCH_DTYPE(params.dtype, PayloadT, {\n stride_per_token = low_precision_staged\n ? params.elements_per_token\n : params.elements_per_token * static_cast<int>(sizeof(PayloadT));\n });\n\n // When use_low_precision is set the recv buffers contain FP8 data regardless of params.dtype,\n // so dispatch the FP8 accumulation kernel in that case.\n auto const effective_dtype = params.use_low_precision ? nvinfer1::DataType::kFP8 : params.dtype;\n\n // Launch appropriate kernel with compact macros\n SWITCH_BOOL(params.enable_rank_mask, ENABLE_RANK_MASK, {\n SWITCH_DTYPE(effective_dtype, TKernelType, {\n SWITCH_TOP_K(params.top_k, TOP_K, {\n SWITCH_QUANT_MODE(TKernelType, params.quant_mode, QUANT_MODE, {\n SWITCH_SWIZZLE_MODE(params.swizzle_mode, SWIZZLE_MODE, {\n auto kernel_fn =\n moeA2ACombineKernel<TKernelType, TOP_K, ENABLE_RANK_MASK, QUANT_MODE, SWIZZLE_MODE>;\n launchWithPdlWhenEnabled(\"moeA2ACombineKernel\", params.enable_pdl, kernel_fn, grid,\n kBlockSize, 0, params.stream, kernel_ptrs,\n params.max_tokens_per_rank, params.elements_per_token,\n stride_per_token, params.local_num_tokens, params.ep_rank,\n params.ep_size, params.enable_pdl, params.output_scalar_scale);\n });\n });\n });\n });\n })\n}\n\n// Kernel to sanitize expert ids for invalid tokens\n__global__ void moeA2ASanitizeExpertIdsKernel(int32_t* expert_ids_ptr,\n int32_t const* recv_counters_ptr, int ep_size,\n int max_tokens_per_rank, int top_k,\n int32_t invalid_id, bool enable_pdl) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n if (enable_pdl) cudaGridDependencySynchronize();\n cudaTriggerProgrammaticLaunchCompletion();\n#endif\n int tid = blockIdx.x * blockDim.x + threadIdx.x;\n int total_tokens = ep_size * max_tokens_per_rank;\n if (tid >= total_tokens) return;\n\n int source_rank = tid / max_tokens_per_rank;\n int token_idx = tid % max_tokens_per_rank;\n\n if (token_idx >= recv_counters_ptr[source_rank]) {\n int32_t* token_expert_ids = expert_ids_ptr + tid * top_k;\n for (int k = 0; k < top_k; ++k) {\n token_expert_ids[k] = invalid_id;\n }\n }\n}\n\nvoid moe_a2a_sanitize_expert_ids_launch(int32_t* expert_ids, int32_t const* recv_counters,\n int32_t invalid_id, int ep_size, int max_tokens_per_rank,\n int top_k, cudaStream_t stream, bool enable_pdl) {\n constexpr int kBlockSize = 256;\n int total_tokens = ep_size * max_tokens_per_rank;\n int grid = ceilDiv(total_tokens, kBlockSize);\n launchWithPdlWhenEnabled(\"moeA2ASanitizeExpertIdsKernel\", enable_pdl,\n moeA2ASanitizeExpertIdsKernel, grid, kBlockSize, 0, stream, expert_ids,\n recv_counters, ep_size, max_tokens_per_rank, top_k, invalid_id,\n enable_pdl);\n}\n\n} // namespace tensorrt_llm::kernels::moe_alltoall\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## Summary\n\nFollow-up to #3846. The generic dispatch kernel makes every CTA thread build remote destination pointers for every payload before determining whether that thread owns any bytes. NVFP4 has four predictably asymmetric payloads, so this change gives each payload only the workers it needs:\n\n- two warps for packed activations;\n- the required lanes of one warp for scales;\n- two lane groups in the final warp for expert IDs and routing weights.\n\nEP4 retains its compact per-rank destination list. EP8 and EP16 retain the existing top-k-sized representation; only their copy schedule changes. The phased path is gated to EP `{4, 8, 16}`, a 128-thread CTA, and validated four-payload NVFP4 layouts. Unsupported EP sizes, top-k values, widths, and payload layouts use the existing generic kernel.\n\nThe H2048/top-k-22 target retains compile-time payload widths. Validated smaller layouts use the same schedule with runtime activation and scale widths.\n\n## Performance\n\n### Single op\n\nGB200, H2048, top-k 22, CUDA graphs. EP8 and EP16 are true global expert-parallel groups spanning two and four nodes.\n\n| Global EP | Nodes | Tokens/rank | Baseline | Candidate | Delta |\n|---:|---:|---:|---:|---:|---:|\n| 4 | 1 | 1 | 13.480 us | 12.862 us | -4.58% |\n| 4 | 1 | 4 | 14.408 us | 13.490 us | -6.37% |\n| 4 | 1 | 64 | 16.511 us | 15.284 us | -7.43% |\n| 4 | 1 | 512 | 18.155 us | 17.804 us | -1.93% |\n| 4 | 1 | 8192 | 55.072 us | 54.689 us | -0.70% |\n| 8 | 2 | 1 | 16.270 us | 13.877 us | -14.71% |\n| 8 | 2 | 4 | 18.394 us | 14.679 us | -20.20% |\n| 8 | 2 | 64 | 21.253 us | 17.358 us | -18.33% |\n| 8 | 2 | 512 | 40.520 us | 27.275 us | -32.69% |\n| 8 | 2 | 1024 | 64.713 us | 37.797 us | -41.59% |\n| 8 | 2 | 8192 | 308.292 us | 96.494 us | -68.70% |\n| 16 | 4 | 1 | 18.107 us | 15.733 us | -13.11% |\n| 16 | 4 | 4 | 21.639 us | 17.328 us | -19.92% |\n| 16 | 4 | 64 | 25.264 us | 20.652 us | -18.26% |\n| 16 | 4 | 512 | 55.275 us | 41.484 us | -24.95% |\n| 16 | 4 | 1024 | 100.321 us | 68.156 us | -32.06% |\n| 16 | 4 | 8192 | 373.115 us | 176.750 us | -52.63% |\n\n### E2e workload\n\nOn the **Nemotron Ultra NVFP4 end-to-end** workload (2 GB200 nodes, TP1/DP8/EP8, FlashInfer one-sided, CUDA graphs, ISL/OSL 8192/8, concurrency 8), mean TTFT improves from 860.8 ms to 839.9 ms (**-2.43%**, 95% CI [-3.44%, -1.41%]). Throughput (+0.62%) and TPOT are statistically on par.\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n## Summary by CodeRabbit\n\n* **New Features**\n * Added support for additional phased NVFP4 layouts in Mixture-of-Experts all-to-all dispatch.\n * Added a specialized H2048 phased dispatch path, including top‑k=22 configurations.\n* **Performance**\n * Improved dispatch efficiency by optimizing activation, scale, and routing-metadata movement.\n* **Bug Fixes**\n * Strengthened validation to ensure payload layouts match runtime settings.\n* **Tests**\n * Updated NVFP4 payload generation and expanded phased H2048 coverage across supported configurations.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": \"GB200\", \"model\": \"H2048\", \"shape\": \"top-k=22\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 13.48, \"optimized\": 12.862, \"stated_speedup\": null, \"speedup\": 1.048}, {\"scope\": \"kernel\", \"hardware\": \"GB200\", \"model\": \"H2048\", \"shape\": \"top-k=22\", \"batch_size\": 4, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 14.408, \"optimized\": 13.49, \"stated_speedup\": null, \"speedup\": 1.0681}, {\"scope\": \"kernel\", \"hardware\": \"GB200\", \"model\": \"H2048\", \"shape\": \"top-k=22\", \"batch_size\": 64, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 16.511, \"optimized\": 15.284, \"stated_speedup\": null, \"speedup\": 1.0803}, {\"scope\": \"kernel\", \"hardware\": \"GB200\", \"model\": \"H2048\", \"shape\": \"top-k=22\", \"batch_size\": 512, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 18.155, \"optimized\": 17.804, \"stated_speedup\": null, \"speedup\": 1.0197}, {\"scope\": \"kernel\", \"hardware\": \"GB200\", \"model\": \"H2048\", \"shape\": \"top-k=22\", \"batch_size\": 8192, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 55.072, \"optimized\": 54.689, \"stated_speedup\": null, \"speedup\": 1.007}, {\"scope\": \"kernel\", \"hardware\": \"GB200\", \"model\": \"H2048\", \"shape\": \"top-k=22\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 16.27, \"optimized\": 13.877, \"stated_speedup\": null, \"speedup\": 1.1724}, {\"scope\": \"kernel\", \"hardware\": \"GB200\", \"model\": \"H2048\", \"shape\": \"top-k=22\", \"batch_size\": 4, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 18.394, \"optimized\": 14.679, \"stated_speedup\": null, \"speedup\": 1.2531}, {\"scope\": \"kernel\", \"hardware\": \"GB200\", \"model\": \"H2048\", \"shape\": \"top-k=22\", \"batch_size\": 64, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 21.253, \"optimized\": 17.358, \"stated_speedup\": null, \"speedup\": 1.2244}, {\"scope\": \"kernel\", \"hardware\": \"GB200\", \"model\": \"H2048\", \"shape\": \"top-k=22\", \"batch_size\": 512, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 40.52, \"optimized\": 27.275, \"stated_speedup\": null, \"speedup\": 1.4856}, {\"scope\": \"kernel\", \"hardware\": \"GB200\", \"model\": \"H2048\", \"shape\": \"top-k=22\", \"batch_size\": 1024, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 64.713, \"optimized\": 37.797, \"stated_speedup\": null, \"speedup\": 1.7121}, {\"scope\": \"kernel\", \"hardware\": \"GB200\", \"model\": \"H2048\", \"shape\": \"top-k=22\", \"batch_size\": 8192, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 308.292, \"optimized\": 96.494, \"stated_speedup\": null, \"speedup\": 3.1949}, {\"scope\": \"kernel\", \"hardware\": \"GB200\", \"model\": \"H2048\", \"shape\": \"top-k=22\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 18.107, \"optimized\": 15.733, \"stated_speedup\": null, \"speedup\": 1.1509}, {\"scope\": \"kernel\", \"hardware\": \"GB200\", \"model\": \"H2048\", \"shape\": \"top-k=22\", \"batch_size\": 4, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 21.639, \"optimized\": 17.328, \"stated_speedup\": null, \"speedup\": 1.2488}, {\"scope\": \"kernel\", \"hardware\": \"GB200\", \"model\": \"H2048\", \"shape\": \"top-k=22\", \"batch_size\": 64, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 25.264, \"optimized\": 20.652, \"stated_speedup\": null, \"speedup\": 1.2233}, {\"scope\": \"kernel\", \"hardware\": \"GB200\", \"model\": \"H2048\", \"shape\": \"top-k=22\", \"batch_size\": 512, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 55.275, \"optimized\": 41.484, \"stated_speedup\": null, \"speedup\": 1.3324}, {\"scope\": \"kernel\", \"hardware\": \"GB200\", \"model\": \"H2048\", \"shape\": \"top-k=22\", \"batch_size\": 1024, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 100.321, \"optimized\": 68.156, \"stated_speedup\": null, \"speedup\": 1.4719}, {\"scope\": \"kernel\", \"hardware\": \"GB200\", \"model\": \"H2048\", \"shape\": \"top-k=22\", \"batch_size\": 8192, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 373.115, \"optimized\": 176.75, \"stated_speedup\": null, \"speedup\": 2.111}, {\"scope\": \"e2e\", \"hardware\": \"GB200\", \"model\": \"Nemotron Ultra NVFP4\", \"shape\": \"TP1/DP8/EP8, ISL/OSL=8192/8, concurrency=8\", \"batch_size\": null, \"metric\": \"TTFT\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 860.8, \"optimized\": 839.9, \"stated_speedup\": null, \"speedup\": 1.0249}]"},"kernel_speedup":{"kind":"number","value":1.2244,"string":"1.2244"},"e2e_speedup":{"kind":"number","value":1.0249,"string":"1.0249"}}},{"rowIdx":1064,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"b255f54480b7754ea094a43575d0c2cfbd0bff18"},"date":{"kind":"string","value":"2026-09-04T01:39:10+02:00"},"pr_number":{"kind":"number","value":4545,"string":"4,545"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/4545"},"title":{"kind":"string","value":"Add ReplaySSM autotuning (#4545)"},"message":{"kind":"string","value":"Add ReplaySSM autotuning (#4545)\n\n## Summary\n\nAdds framework-agnostic runtime autotuning for ReplaySSM checkpointing\nSSU. For eligible dense decode workloads, FlashInfer profiles supported\nmonolithic and two-kernel launches and caches the fastest tactic for\nreuse.\n\n## What changes\n\n- Exposes main-kernel pipeline stages and CTAs per SM as runtime launch\ncontrols, alongside the existing precompute heads-per-CTA control.\n- Adds a `CheckpointingSSURunner` that tunes the algorithm, `d_split`,\nmain launch geometry, and precompute grouping through FlashInfer's\ngeneric autotuner.\n- Buckets the active batch dimension while profiling compact private\nstate/ring buffers, preserving the production `dt` broadcast layout and\nrepresentative replay history.\n- Uses cold-L2 and CUDA-graph profiling, and exposes a scratch allocator\nso inference frameworks can provide graph-stable two-kernel workspace.\n- Keeps explicit algorithm/launch overrides and unsupported\nconfigurations on the normal fallback path.\n\n## Scope\n\nGeneric autotuning is enabled only for dense calls (`cu_seqlens is\nNone`) with the two-kernel scratch buffers present and launch controls\nleft on automatic selection. The implementation contains no\nvLLM-specific policy or state.\n\n## Validation\n\n- Base-head H100 focused suite: 7 passed, covering scratch allocation,\ndynamic profiles, cache keys, tactic generation, `d_split`, autotune\ncache reuse, and monolithic/two-kernel parity.\n- Review-followup H100 checks: 3 focused tests passed, and the newly\nadmitted non-power-of-two launch (`heads_per_group=14`,\n`heads_per_cta=3`) compiled and executed successfully.\n- H100 `autotune(True)` wall clock at `max_batch=1024`: **63.856\nseconds** with a warm JIT module and empty autotuner cache. This used\ndense `T=4`, BF16 inputs, FP32 state, and Nemotron TP8 geometry\n(`nheads=16`, `ngroups=1`, `head_dim=64`, `d_state=128`); all 12 batch\nbuckets were saved (3,574 distinct tactic profiles after launch\ndeduplication).\n- Pre-commit and public API/documentation checks pass. The full\nrepository test matrix is pending maintainer CI authorization.\n\n---------\n\nSigned-off-by: Andrii Skliar <askliar@nvidia.com>\nCo-authored-by: Andrii Skliar <askliar@nvidia.com>\nCo-authored-by: Albert Cheng <albecheng@nvidia.com>"},"path":{"kind":"string","value":"csrc/checkpointing_ssu.cu"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * Copyright (c) 2025 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n// clang-format off\n// config.inc MUST come before the header: it defines DIM, DSTATE, NPREDICTED,\n// MAX_WINDOW constexprs that the header's function templates rely on.\n#include \"checkpointing_ssu_config.inc\"\n#include <flashinfer/mamba/checkpointing_ssu.cuh>\n#include <flashinfer/mamba/launch_checkpointing_ssu.cuh>\n// clang-format on\n#include \"tvm_ffi_utils.h\"\n\nusing namespace flashinfer;\nusing tvm::ffi::Optional;\n\nnamespace flashinfer::mamba::checkpointing {\n\nvoid checkpointing_ssu(\n TensorView state, // (state_cache_size, nheads, dim, dstate)\n TensorView x, // (batch, NPREDICTED, nheads, dim) / (1, total_tokens, nheads, dim) under varlen\n TensorView dt, // (batch, NPREDICTED, nheads, dim) tie_hdim / (1, total_tokens, nheads, dim)\n TensorView A, // (nheads, dim, dstate) tie_hdim\n TensorView B, // (batch, NPREDICTED, ngroups, dstate) / (1, total_tokens, ngroups, dstate)\n TensorView C, // same as B\n TensorView output, // same layout as x\n // Ring-buffer cache tensors (single-buffered, head-major; RING_BUFFER_LEN\n // = row count, runtime-implicit; MAX_WINDOW = RING_BUFFER_LEN - NPREDICTED)\n TensorView x_cache, // (state_cache_size, nheads, RING_BUFFER_LEN, dim)\n TensorView B_cache, // (state_cache_size, ngroups, RING_BUFFER_LEN, dstate)\n TensorView dt_cache, // (state_cache_size, nheads, RING_BUFFER_LEN) f32\n TensorView ring_start, // (state_cache_size,) int32\n TensorView prev_num_accepted, // (state_cache_size,) int32\n // Optional tensors\n Optional<TensorView> D, // (nheads, dim)\n Optional<TensorView> z, // same layout as x\n Optional<TensorView> dt_bias, // (nheads, dim) tie_hdim\n bool dt_softplus,\n Optional<TensorView> state_batch_indices, // (batch,) int32\n int64_t pad_slot_id,\n Optional<TensorView> state_scale, // (state_cache_size, nheads, dim) f32\n Optional<TensorView> rand_seed, // single int64\n int64_t d_split, // v12 §59: per-head DIM split factor (1, 2, or 4)\n Optional<TensorView> cu_seqlens, // (batch+1,) int32, varlen mode\n Optional<TensorView> cb_scaled, // two-kernel: bf16 (batch, nheads, 32, 8) fragA-native\n Optional<TensorView> cumAdt_vec, // two-kernel: f32 (batch, nheads, T_pad) raw cumAdt\n Optional<TensorView> cb_old, // two-kernel: bf16 (batch, nheads, 32, K_old/2) fragA-native\n int64_t precompute_heads_per_cta) { // two-kernel PRECOMPUTE: heads per CTA (0 = heuristic)\n\n bool const is_varlen = cu_seqlens.has_value();\n\n // ── Extract dimensions ──\n auto const state_cache_size = state.size(0);\n auto const nheads = state.size(1);\n auto const dim = state.size(2);\n auto const dstate = state.size(3);\n auto const ring_buffer_len = x_cache.size(2);\n auto const ngroups = B.size(2);\n\n // In non-varlen mode, batch = x.size(0) and npredicted = x.size(1) (the\n // 4D batched layout). In varlen, the JIT compile-time NPREDICTED is the\n // max seq_len the caller commits to; the wrapper stamped it into the JIT\n // URI from `max_seqlen` and we read it back as the constexpr `NPREDICTED`\n // (validated against runtime cu_seqlens on the host side below). `batch`\n // = number of sequences = `cu_seqlens.size(0) - 1`.\n int64_t batch;\n int64_t npredicted;\n if (is_varlen) {\n auto const& cs = cu_seqlens.value();\n CHECK_CUDA(cs);\n CHECK_DIM(1, cs);\n FLASHINFER_CHECK(\n cs.size(0) >= 2,\n \"cu_seqlens must have shape (batch+1,) with batch >= 1, got size(0)=\", cs.size(0));\n FLASHINFER_CHECK(cs.dtype().code == kDLInt && cs.dtype().bits == 32,\n \"cu_seqlens must be int32\");\n CHECK_CONTIGUOUS(cs);\n batch = cs.size(0) - 1;\n npredicted = NPREDICTED; // JIT-stamped — wrapper ensures max(seq_lens) <= NPREDICTED.\n } else {\n batch = x.size(0);\n npredicted = x.size(1);\n }\n\n // ── JIT compile-time / runtime cross-check ──\n // NPREDICTED and MAX_WINDOW are JIT compile-time constants stamped by the\n // wrapper. In non-varlen NPREDICTED = x.shape[1]; in varlen NPREDICTED =\n // user-supplied `max_seqlen` (upper bound on every cu_seqlens diff).\n FLASHINFER_CHECK(npredicted == NPREDICTED, is_varlen ? \"max_seqlen=\" : \"x.size(1)=\", npredicted,\n \" must equal JIT NPREDICTED=\", NPREDICTED);\n // The LOGICAL replay window is the ring row count minus one speculative\n // window (ReplaySSM early-flush rule: pnat + 2T > RING_BUFFER_LEN).\n auto const max_window = ring_buffer_len - npredicted;\n FLASHINFER_CHECK(max_window == MAX_WINDOW, \"x_cache.size(2) - npredicted = \", max_window,\n \" must equal JIT MAX_WINDOW=\", MAX_WINDOW);\n FLASHINFER_CHECK(npredicted <= max_window, \"npredicted=\", npredicted,\n \" must be <= max_window=\", max_window, \" (ring_buffer_len=\", ring_buffer_len,\n \")\");\n\n // ── Validate state ──\n CHECK_CUDA(state);\n CHECK_DIM(4, state);\n {\n auto s = state.strides();\n auto sz = state.sizes();\n FLASHINFER_CHECK(s[3] == 1, \"state dim 3 (dstate) must have stride 1, got \", s[3]);\n FLASHINFER_CHECK(s[2] == sz[3], \"state dim 2 (dim) must be contiguous with dim 3, got stride \",\n s[2], \" expected \", sz[3]);\n FLASHINFER_CHECK(s[1] == sz[2] * sz[3],\n \"state dim 1 (nheads) must be contiguous with dim 2, got stride \", s[1],\n \" expected \", sz[2] * sz[3]);\n }\n\n // ── Validate x ──\n // Non-varlen: shape (batch, NPREDICTED, nheads, dim).\n // Varlen : shape (1, total_tokens, nheads, dim) — batch axis collapsed,\n // token axis is the outer iteration. The kernel reads x via\n // `bos * x_stride_token + …` so x_stride_token is the per-token\n // stride in either layout (= nheads*dim for contig).\n CHECK_CUDA(x);\n CHECK_DIM(4, x);\n if (is_varlen) {\n FLASHINFER_CHECK(x.size(0) == 1, \"varlen: x.size(0)=\", x.size(0), \" must be 1\");\n } else {\n FLASHINFER_CHECK(x.size(0) == batch, \"x.size(0)=\", x.size(0), \" must equal batch=\", batch);\n FLASHINFER_CHECK(x.size(1) == npredicted, \"x.size(1)=\", x.size(1),\n \" must equal npredicted=\", npredicted);\n }\n FLASHINFER_CHECK(x.size(2) == nheads, \"x.size(2)=\", x.size(2), \" must equal nheads=\", nheads);\n FLASHINFER_CHECK(x.size(3) == dim, \"x.size(3)=\", x.size(3), \" must equal dim=\", dim);\n CHECK_LAST_DIM_CONTIGUOUS(x);\n FLASHINFER_CHECK(x.stride(2) == dim, \"x.stride(2)=\", x.stride(2), \" must equal dim=\", dim,\n \" ((nheads, dim) must be contiguous)\");\n\n // In varlen, all per-token tensors share the flattened token axis — use\n // x.size(1) as the canonical total_tokens and cross-check the others below.\n int64_t const total_tokens = is_varlen ? x.size(1) : 0;\n\n // ── Validate dt ──\n CHECK_CUDA(dt);\n CHECK_DIM(4, dt);\n if (is_varlen) {\n FLASHINFER_CHECK(dt.size(0) == 1, \"varlen: dt.size(0)=\", dt.size(0), \" must be 1\");\n FLASHINFER_CHECK(dt.size(1) == total_tokens, \"varlen: dt.size(1)=\", dt.size(1),\n \" must equal x.size(1)=\", total_tokens);\n } else {\n FLASHINFER_CHECK(dt.size(0) == batch, \"dt.size(0)=\", dt.size(0), \" must equal batch=\", batch);\n FLASHINFER_CHECK(dt.size(1) == npredicted, \"dt.size(1)=\", dt.size(1),\n \" must equal npredicted=\", npredicted);\n }\n FLASHINFER_CHECK(dt.size(2) == nheads, \"dt.size(2)=\", dt.size(2), \" must equal nheads=\", nheads);\n FLASHINFER_CHECK(dt.size(3) == dim, \"dt.size(3)=\", dt.size(3), \" must equal dim=\", dim);\n FLASHINFER_CHECK(dt.stride(2) == 1, \"dt.stride(2) must be 1 (tie_hdim), got \", dt.stride(2));\n FLASHINFER_CHECK(dt.stride(3) == 0, \"dt.stride(3) must be 0 (tie_hdim), got \", dt.stride(3));\n\n // ── Validate A: (nheads, dim, dstate) tie_hdim ──\n CHECK_CUDA(A);\n CHECK_DIM(3, A);\n FLASHINFER_CHECK(A.size(0) == nheads, \"A.size(0)=\", A.size(0), \" must equal nheads=\", nheads);\n FLASHINFER_CHECK(A.size(1) == dim, \"A.size(1)=\", A.size(1), \" must equal dim=\", dim);\n FLASHINFER_CHECK(A.size(2) == dstate, \"A.size(2)=\", A.size(2), \" must equal dstate=\", dstate);\n FLASHINFER_CHECK(A.stride(0) == 1, \"A.stride(0) must be 1, got \", A.stride(0));\n FLASHINFER_CHECK(A.stride(1) == 0, \"A.stride(1) must be 0 (tie_hdim), got \", A.stride(1));\n FLASHINFER_CHECK(A.stride(2) == 0, \"A.stride(2) must be 0 (tie_hdim), got \", A.stride(2));\n\n // ── Validate B ──\n CHECK_CUDA(B);\n CHECK_DIM(4, B);\n if (is_varlen) {\n FLASHINFER_CHECK(B.size(0) == 1, \"varlen: B.size(0)=\", B.size(0), \" must be 1\");\n FLASHINFER_CHECK(B.size(1) == total_tokens, \"varlen: B.size(1)=\", B.size(1),\n \" must equal x.size(1)=\", total_tokens);\n } else {\n FLASHINFER_CHECK(B.size(0) == batch, \"B.size(0)=\", B.size(0), \" must equal batch=\", batch);\n FLASHINFER_CHECK(B.size(1) == npredicted, \"B.size(1)=\", B.size(1),\n \" must equal npredicted=\", npredicted);\n }\n FLASHINFER_CHECK(B.size(3) == dstate, \"B.size(3)=\", B.size(3), \" must equal dstate=\", dstate);\n CHECK_LAST_DIM_CONTIGUOUS(B);\n FLASHINFER_CHECK(B.stride(2) == dstate, \"B.stride(2)=\", B.stride(2),\n \" must equal dstate=\", dstate, \" ((ngroups, dstate) must be contiguous)\");\n FLASHINFER_CHECK(nheads % ngroups == 0, \"nheads=\", nheads,\n \" must be divisible by ngroups=\", ngroups);\n\n // ── Validate C ──\n CHECK_CUDA(C);\n CHECK_DIM(4, C);\n if (is_varlen) {\n FLASHINFER_CHECK(C.size(0) == 1, \"varlen: C.size(0)=\", C.size(0), \" must be 1\");\n FLASHINFER_CHECK(C.size(1) == total_tokens, \"varlen: C.size(1)=\", C.size(1),\n \" must equal x.size(1)=\", total_tokens);\n } else {\n FLASHINFER_CHECK(C.size(0) == batch, \"C.size(0)=\", C.size(0), \" must equal batch=\", batch);\n FLASHINFER_CHECK(C.size(1) == npredicted, \"C.size(1)=\", C.size(1),\n \" must equal npredicted=\", npredicted);\n }\n FLASHINFER_CHECK(C.size(2) == ngroups, \"C.size(2)=\", C.size(2), \" must equal ngroups=\", ngroups);\n FLASHINFER_CHECK(C.size(3) == dstate, \"C.size(3)=\", C.size(3), \" must equal dstate=\", dstate);\n CHECK_LAST_DIM_CONTIGUOUS(C);\n FLASHINFER_CHECK(C.stride(2) == dstate, \"C.stride(2)=\", C.stride(2),\n \" must equal dstate=\", dstate, \" ((ngroups, dstate) must be contiguous)\");\n\n // ── Validate output ──\n CHECK_CUDA(output);\n CHECK_DIM(4, output);\n if (is_varlen) {\n FLASHINFER_CHECK(output.size(0) == 1, \"varlen: output.size(0)=\", output.size(0), \" must be 1\");\n FLASHINFER_CHECK(output.size(1) == total_tokens, \"varlen: output.size(1)=\", output.size(1),\n \" must equal x.size(1)=\", total_tokens);\n } else {\n FLASHINFER_CHECK(output.size(0) == batch, \"output.size(0)=\", output.size(0),\n \" must equal batch=\", batch);\n FLASHINFER_CHECK(output.size(1) == npredicted, \"output.size(1)=\", output.size(1),\n \" must equal npredicted=\", npredicted);\n }\n FLASHINFER_CHECK(output.size(2) == nheads, \"output.size(2)=\", output.size(2),\n \" must equal nheads=\", nheads);\n FLASHINFER_CHECK(output.size(3) == dim, \"output.size(3)=\", output.size(3),\n \" must equal dim=\", dim);\n CHECK_LAST_DIM_CONTIGUOUS(output);\n FLASHINFER_CHECK(output.stride(2) == dim, \"output.stride(2)=\", output.stride(2),\n \" must equal dim=\", dim, \" ((nheads, dim) must be contiguous)\");\n\n // ── Validate ring-buffer cache tensors ──\n // x_cache: kernel gathers one head's rows → (RING_BUFFER_LEN, dim) contig per head.\n CHECK_CUDA(x_cache);\n CHECK_DIM(4, x_cache); // (state_cache_size, nheads, RING_BUFFER_LEN, dim)\n FLASHINFER_CHECK(x_cache.size(0) == state_cache_size, \"x_cache.size(0)=\", x_cache.size(0),\n \" must equal state_cache_size=\", state_cache_size);\n FLASHINFER_CHECK(x_cache.size(1) == nheads, \"x_cache.size(1)=\", x_cache.size(1),\n \" must equal nheads=\", nheads);\n FLASHINFER_CHECK(x_cache.size(3) == dim, \"x_cache.size(3)=\", x_cache.size(3),\n \" must equal dim=\", dim);\n CHECK_LAST_DIM_CONTIGUOUS(x_cache);\n FLASHINFER_CHECK(x_cache.stride(2) == dim, \"x_cache.stride(2)=\", x_cache.stride(2),\n \" must equal dim=\", dim, \" ((RING_BUFFER_LEN, dim) must be contiguous)\");\n\n // B_cache: one group's rows → (RING_BUFFER_LEN, dstate) contig per group.\n CHECK_CUDA(B_cache);\n CHECK_DIM(4, B_cache); // (state_cache_size, ngroups, RING_BUFFER_LEN, dstate)\n FLASHINFER_CHECK(B_cache.size(0) == state_cache_size, \"B_cache.size(0)=\", B_cache.size(0),\n \" must equal state_cache_size=\", state_cache_size);\n FLASHINFER_CHECK(B_cache.size(1) == ngroups, \"B_cache.size(1)=\", B_cache.size(1),\n \" must equal ngroups=\", ngroups);\n FLASHINFER_CHECK(B_cache.size(2) == ring_buffer_len, \"B_cache.size(2)=\", B_cache.size(2),\n \" must equal ring_buffer_len=\", ring_buffer_len);\n FLASHINFER_CHECK(B_cache.size(3) == dstate, \"B_cache.size(3)=\", B_cache.size(3),\n \" must equal dstate=\", dstate);\n CHECK_LAST_DIM_CONTIGUOUS(B_cache);\n FLASHINFER_CHECK(B_cache.stride(2) == dstate, \"B_cache.stride(2)=\", B_cache.stride(2),\n \" must equal dstate=\", dstate,\n \" ((RING_BUFFER_LEN, dstate) must be contiguous)\");\n\n // dt_cache: one head's row → RING_BUFFER_LEN contig.\n CHECK_CUDA(dt_cache);\n CHECK_DIM(3, dt_cache); // (state_cache_size, nheads, RING_BUFFER_LEN)\n FLASHINFER_CHECK(dt_cache.size(0) == state_cache_size, \"dt_cache.size(0)=\", dt_cache.size(0),\n \" must equal state_cache_size=\", state_cache_size);\n FLASHINFER_CHECK(dt_cache.size(1) == nheads, \"dt_cache.size(1)=\", dt_cache.size(1),\n \" must equal nheads=\", nheads);\n FLASHINFER_CHECK(dt_cache.size(2) == ring_buffer_len, \"dt_cache.size(2)=\", dt_cache.size(2),\n \" must equal ring_buffer_len=\", ring_buffer_len);\n CHECK_LAST_DIM_CONTIGUOUS(dt_cache);\n\n CHECK_CUDA(ring_start);\n CHECK_DIM(1, ring_start);\n FLASHINFER_CHECK(ring_start.size(0) == state_cache_size,\n \"ring_start.size(0)=\", ring_start.size(0),\n \" must equal state_cache_size=\", state_cache_size);\n CHECK_CONTIGUOUS(ring_start);\n\n CHECK_CUDA(prev_num_accepted);\n CHECK_DIM(1, prev_num_accepted);\n FLASHINFER_CHECK(prev_num_accepted.size(0) == state_cache_size,\n \"prev_num_accepted.size(0)=\", prev_num_accepted.size(0),\n \" must equal state_cache_size=\", state_cache_size);\n CHECK_CONTIGUOUS(prev_num_accepted);\n\n // ── Validate optional D ──\n if (D.has_value()) {\n auto& Dv = D.value();\n CHECK_CUDA(Dv);\n CHECK_DIM(2, Dv);\n FLASHINFER_CHECK(Dv.size(0) == nheads, \"D.size(0)=\", Dv.size(0), \" must equal nheads=\", nheads);\n FLASHINFER_CHECK(Dv.size(1) == dim, \"D.size(1)=\", Dv.size(1), \" must equal dim=\", dim);\n FLASHINFER_CHECK(Dv.stride(0) == 1, \"D.stride(0) must be 1 (tie_hdim), got \", Dv.stride(0));\n FLASHINFER_CHECK(Dv.stride(1) == 0, \"D.stride(1) must be 0 (tie_hdim), got \", Dv.stride(1));\n }\n\n // ── Validate optional dt_bias ──\n if (dt_bias.has_value()) {\n auto& db = dt_bias.value();\n CHECK_CUDA(db);\n CHECK_DIM(2, db);\n FLASHINFER_CHECK(db.size(0) == nheads, \"dt_bias.size(0)=\", db.size(0),\n \" must equal nheads=\", nheads);\n FLASHINFER_CHECK(db.size(1) == dim, \"dt_bias.size(1)=\", db.size(1), \" must equal dim=\", dim);\n FLASHINFER_CHECK(db.stride(0) == 1, \"dt_bias.stride(0) must be 1 (tie_hdim), got \",\n db.stride(0));\n FLASHINFER_CHECK(db.stride(1) == 0, \"dt_bias.stride(1) must be 0 (tie_hdim), got \",\n db.stride(1));\n }\n\n // ── Validate optional z: same layout/contig rules as x ──\n if (z.has_value()) {\n auto& zv = z.value();\n CHECK_CUDA(zv);\n CHECK_DIM(4, zv);\n if (is_varlen) {\n FLASHINFER_CHECK(zv.size(0) == 1, \"varlen: z.size(0)=\", zv.size(0), \" must be 1\");\n FLASHINFER_CHECK(zv.size(1) == total_tokens, \"varlen: z.size(1)=\", zv.size(1),\n \" must equal x.size(1)=\", total_tokens);\n } else {\n FLASHINFER_CHECK(zv.size(0) == batch, \"z.size(0)=\", zv.size(0), \" must equal batch=\", batch);\n FLASHINFER_CHECK(zv.size(1) == npredicted, \"z.size(1)=\", zv.size(1),\n \" must equal npredicted=\", npredicted);\n }\n FLASHINFER_CHECK(zv.size(2) == nheads, \"z.size(2)=\", zv.size(2), \" must equal nheads=\", nheads);\n FLASHINFER_CHECK(zv.size(3) == dim, \"z.size(3)=\", zv.size(3), \" must equal dim=\", dim);\n CHECK_LAST_DIM_CONTIGUOUS(zv);\n FLASHINFER_CHECK(zv.stride(2) == dim, \"z.stride(2)=\", zv.stride(2), \" must equal dim=\", dim,\n \" ((nheads, dim) must be contiguous)\");\n }\n\n // ── Validate optional state_batch_indices ──\n if (state_batch_indices.has_value()) {\n auto& sbi = state_batch_indices.value();\n CHECK_CUDA(sbi);\n CHECK_DIM(1, sbi);\n FLASHINFER_CHECK(sbi.size(0) == batch, \"state_batch_indices.size(0)=\", sbi.size(0),\n \" must equal batch=\", batch);\n CHECK_CONTIGUOUS(sbi);\n }\n\n // ── Validate optional state_scale: (state_cache_size, nheads, dim) ──\n // Inner two dims (nheads, dim) must be contiguous; only batch stride is\n // parameterized in the params struct.\n if (state_scale.has_value()) {\n auto const& ss = state_scale.value();\n CHECK_CUDA(ss);\n CHECK_DIM(3, ss);\n FLASHINFER_CHECK(ss.size(0) == state_cache_size, \"state_scale.size(0)=\", ss.size(0),\n \" must equal state_cache_size=\", state_cache_size);\n FLASHINFER_CHECK(ss.size(1) == nheads, \"state_scale.size(1)=\", ss.size(1),\n \" must equal nheads=\", nheads);\n FLASHINFER_CHECK(ss.size(2) == dim, \"state_scale.size(2)=\", ss.size(2),\n \" must equal dim=\", dim);\n FLASHINFER_CHECK(ss.stride(2) == 1, \"state_scale.stride(2) must be 1, got \", ss.stride(2));\n FLASHINFER_CHECK(ss.stride(1) == dim, \"state_scale.stride(1)=\", ss.stride(1),\n \" must equal dim=\", dim, \" ((nheads, dim) must be contiguous)\");\n }\n\n // ── Dtype consistency ──\n // input_dtype = x.dtype; all activation tensors (B, C, output, z, x_cache,\n // B_cache) and the state cache's \"input-side\" mirrors must match it.\n // weight_dtype = D.dtype = dt_bias.dtype (kernel template sees one\n // weight_t for both).\n // Cache scalar tensors have fixed dtypes hardcoded in the kernel.\n {\n auto input_dtype = x.dtype();\n FLASHINFER_CHECK(B.dtype() == input_dtype, \"B.dtype must match x.dtype\");\n FLASHINFER_CHECK(C.dtype() == input_dtype, \"C.dtype must match x.dtype\");\n FLASHINFER_CHECK(output.dtype() == input_dtype, \"output.dtype must match x.dtype\");\n FLASHINFER_CHECK(x_cache.dtype() == input_dtype, \"x_cache.dtype must match x.dtype\");\n FLASHINFER_CHECK(B_cache.dtype() == input_dtype, \"B_cache.dtype must match x.dtype\");\n if (z.has_value()) {\n FLASHINFER_CHECK(z.value().dtype() == input_dtype, \"z.dtype must match x.dtype\");\n }\n if (D.has_value() && dt_bias.has_value()) {\n FLASHINFER_CHECK(D.value().dtype() == dt_bias.value().dtype(),\n \"D.dtype must equal dt_bias.dtype (kernel uses a single weight_t)\");\n }\n // dt_cache is produced by this same kernel in f32 and consumed back in\n // f32 on the next call (replay decays are recomputed from it).\n FLASHINFER_CHECK(dt_cache.dtype().code == kDLFloat && dt_cache.dtype().bits == 32,\n \"dt_cache must be float32\");\n // Index tensors used by the kernel as int32 scalars.\n FLASHINFER_CHECK(ring_start.dtype().code == kDLInt && ring_start.dtype().bits == 32,\n \"ring_start must be int32\");\n FLASHINFER_CHECK(\n prev_num_accepted.dtype().code == kDLInt && prev_num_accepted.dtype().bits == 32,\n \"prev_num_accepted must be int32\");\n if (state_batch_indices.has_value()) {\n auto sbi_dt = state_batch_indices.value().dtype();\n FLASHINFER_CHECK(sbi_dt.code == kDLInt && (sbi_dt.bits == 32 || sbi_dt.bits == 64),\n \"state_batch_indices must be int32 or int64\");\n }\n if (state_scale.has_value()) {\n auto ss_dt = state_scale.value().dtype();\n FLASHINFER_CHECK(ss_dt.code == kDLFloat && ss_dt.bits == 32, \"state_scale must be float32\");\n }\n // Quantized state dtypes (int8, fp8_e4m3fn, ...) require a state_scale\n // tensor; non-quantized dtypes must not pass one. Mirrors the Python\n // wrapper assertion and matches the kernel's compile-time\n // `state_scale_t == void` gating.\n {\n auto sd = state.dtype();\n bool const is_int8 = (sd.code == kDLInt && sd.bits == 8);\n bool const is_fp8 = (sd.code == kDLFloat8_e4m3fn && sd.bits == 8);\n bool const is_quantized_state = is_int8 || is_fp8;\n if (is_quantized_state) {\n FLASHINFER_CHECK(state_scale.has_value(),\n \"Quantized state.dtype (int8/fp8_e4m3fn) requires a state_scale tensor \"\n \"of shape (state_cache_size, nheads, dim) and dtype float32\");\n // The 8-bit replay path uses Layout<_4, _1> (M-shard per warp) which\n // needs per-warp M = D_PER_CTA / 4 >= 16 (m16n8 atom M). This forces\n // D_PER_CTA >= 64, i.e. d_split == 1.\n FLASHINFER_CHECK(\n d_split == 1,\n \"Quantized state.dtype (int8/fp8_e4m3fn) requires d_split=1 (got d_split=\", d_split,\n \"); the M-shard-per-warp replay layout needs D_PER_CTA / 4 >= 16.\");\n } else {\n FLASHINFER_CHECK(!state_scale.has_value(),\n \"state_scale must be None for non-quantized state.dtype \"\n \"(allowed quantized dtypes: {int8, fp8_e4m3fn})\");\n }\n }\n }\n\n // ── Populate params ──\n CheckpointingSsuParams p;\n\n // ── Validate d_split (v12 §59) ──\n // Allowed for v12: {1, 2}. d_split=4 deferred to v12.x (needs warp-count\n // restructure — output MMA `_1×4` layout requires D_PER_CTA ≥ 32).\n FLASHINFER_CHECK(d_split == 1 || d_split == 2, \"d_split=\", d_split,\n \" must be one of {1, 2} (d_split=4 is deferred to v12.x)\");\n FLASHINFER_CHECK(dim % d_split == 0, \"dim=\", dim, \" must be divisible by d_split=\", d_split);\n FLASHINFER_CHECK(dim / d_split >= 32, \"d_split=\", d_split, \" gives D_PER_CTA=\", dim / d_split,\n \" < 32 (output MMA m16n8 atom floor with _1×4 warp layout)\");\n\n // ── Validate precompute_heads_per_cta (two-kernel PRECOMPUTE head-tiling, host knob) ──\n // 0 = use the launcher's co-residency heuristic; >0 overrides (must divide HEADS_PER_GROUP).\n {\n int64_t const hpg = nheads / ngroups;\n FLASHINFER_CHECK(precompute_heads_per_cta >= 0 &&\n (precompute_heads_per_cta == 0 || hpg % precompute_heads_per_cta == 0),\n \"precompute_heads_per_cta=\", precompute_heads_per_cta,\n \" must be 0 (heuristic) or a positive divisor of HEADS_PER_GROUP \"\n \"(nheads/ngroups=\",\n hpg, \")\");\n }\n\n p.batch = batch;\n p.nheads = nheads;\n p.dim = dim;\n p.dstate = dstate;\n p.ngroups = ngroups;\n p.state_cache_size = state_cache_size;\n p.npredicted = npredicted;\n p.max_window = max_window;\n p.pad_slot_id = pad_slot_id;\n p.d_split = static_cast<int32_t>(d_split);\n p.dt_softplus = dt_softplus;\n\n // Pointers\n p.state = state.data_ptr();\n p.x = const_cast<void*>(x.data_ptr());\n p.dt = const_cast<void*>(dt.data_ptr());\n p.A = const_cast<void*>(A.data_ptr());\n p.B = const_cast<void*>(B.data_ptr());\n p.C = const_cast<void*>(C.data_ptr());\n p.output = output.data_ptr();\n\n p.x_cache = x_cache.data_ptr();\n p.B_cache = B_cache.data_ptr();\n p.dt_cache = dt_cache.data_ptr();\n p.ring_start = const_cast<void*>(ring_start.data_ptr());\n p.ring_buffer_len = static_cast<int32_t>(ring_buffer_len);\n p.prev_num_accepted = const_cast<void*>(prev_num_accepted.data_ptr());\n\n if (D.has_value()) p.D = const_cast<void*>(D.value().data_ptr());\n if (z.has_value()) {\n p.z = const_cast<void*>(z.value().data_ptr());\n // Same seq-dim selection as the rest of the batch-side tensors below.\n p.z_stride_seq = z.value().stride(is_varlen ? 1 : 0);\n p.z_stride_token = z.value().stride(1);\n }\n if (dt_bias.has_value()) p.dt_bias = const_cast<void*>(dt_bias.value().data_ptr());\n if (state_batch_indices.has_value())\n p.state_batch_indices = const_cast<void*>(state_batch_indices.value().data_ptr());\n if (is_varlen) {\n p.cu_seqlens = const_cast<void*>(cu_seqlens.value().data_ptr());\n }\n if (state_scale.has_value()) {\n p.state_scale = state_scale.value().data_ptr();\n p.state_scale_stride_seq = state_scale.value().stride(0);\n }\n if (rand_seed.has_value()) {\n auto const& rs = rand_seed.value();\n CHECK_CUDA(rs);\n FLASHINFER_CHECK(rs.numel() == 1, \"rand_seed must be single-element, got numel=\", rs.numel());\n FLASHINFER_CHECK(rs.dtype().code == kDLInt && rs.dtype().bits == 64, \"rand_seed must be int64\");\n p.rand_seed = static_cast<const int64_t*>(rs.data_ptr());\n }\n\n // Two-kernel split scratch (presence of cb_scaled selects precompute+main).\n // Caller-allocated (graph-safe). The Python wrapper enforces the all-or-none\n // trio; shape/device/contiguity/dtype are validated here so a bad scratch\n // fails loudly instead of corrupting memory or faulting inside the kernel.\n // Expected layouts (see the wrapper / bench allocator): cb_scaled/cb_old are\n // input-dtype fragA-native (., ., 32, regs); cumAdt_vec is f32 (., ., T_pad).\n // fragA-native scratch: each (batch, head)'s CB is one MMA A-fragment stored\n // as [warp lane, register]. The lane axis is a full warp; the register axis\n // is the A-operand size — kCbScaledRegs for the new-token m16n8k16 CB,\n // k_old_half (= K_old/2) for the old-token m16n8k{K_old} CB.\n constexpr int64_t kWarpSize = 32;\n constexpr int64_t kCbScaledRegs = 8; // m16n8k16 A-operand regs/lane\n int64_t const t_pad = ((npredicted + 15) / 16) * 16; // cumAdt_vec: next_multiple_of<16>\n int64_t const k_old_half = (((max_window + 7) / 8) * 8) / 2; // K_old/2, K_old=next_mult<8>\n if (cb_scaled.has_value()) {\n auto const& cb = cb_scaled.value();\n CHECK_CUDA(cb);\n CHECK_DIM(4, cb);\n CHECK_CONTIGUOUS(cb);\n FLASHINFER_CHECK(cb.dtype().code == x.dtype().code && cb.dtype().bits == x.dtype().bits,\n \"cb_scaled dtype must match x (input dtype)\");\n FLASHINFER_CHECK(cb.size(0) >= batch && cb.size(1) == nheads && cb.size(2) == kWarpSize &&\n cb.size(3) == kCbScaledRegs,\n \"cb_scaled must be (>=batch, nheads, \", kWarpSize, \", \", kCbScaledRegs,\n \"), got (\", cb.size(0), \", \", cb.size(1), \", \", cb.size(2), \", \", cb.size(3),\n \")\");\n p.cb_scaled = const_cast<void*>(cb.data_ptr());\n }\n if (cumAdt_vec.has_value()) {\n auto const& cv = cumAdt_vec.value();\n CHECK_CUDA(cv);\n CHECK_DIM(3, cv);\n CHECK_CONTIGUOUS(cv);\n FLASHINFER_CHECK(cv.dtype().code == kDLFloat && cv.dtype().bits == 32,\n \"cumAdt_vec must be float32\");\n FLASHINFER_CHECK(cv.size(0) >= batch && cv.size(1) == nheads && cv.size(2) == t_pad,\n \"cumAdt_vec must be (>=batch, nheads, \", t_pad, \"), got (\", cv.size(0), \", \",\n cv.size(1), \", \", cv.size(2), \")\");\n p.cumAdt_vec = const_cast<void*>(cv.data_ptr());\n }\n if (cb_old.has_value()) {\n auto const& cbo = cb_old.value();\n CHECK_CUDA(cbo);\n CHECK_DIM(4, cbo);\n CHECK_CONTIGUOUS(cbo);\n FLASHINFER_CHECK(cbo.dtype().code == x.dtype().code && cbo.dtype().bits == x.dtype().bits,\n \"cb_old dtype must match x (input dtype)\");\n FLASHINFER_CHECK(cbo.size(0) >= batch && cbo.size(1) == nheads && cbo.size(2) == kWarpSize &&\n cbo.size(3) == k_old_half,\n \"cb_old must be (>=batch, nheads, \", kWarpSize, \", \", k_old_half, \"), got (\",\n cbo.size(0), \", \", cbo.size(1), \", \", cbo.size(2), \", \", cbo.size(3), \")\");\n p.cb_old = const_cast<void*>(cbo.data_ptr());\n }\n // Strides\n p.state_stride_seq = state.stride(0);\n\n // `*_stride_seq` is the outer iteration stride. Non-varlen iterates over\n // dim 0 (per-batch), varlen iterates over dim 1 (per-token) — sequences\n // are packed into a single batch in the (1, total_tokens, ...) layout.\n // The kernel uses one formula `seq * *_stride_seq` for both modes.\n int const seq_dim = is_varlen ? 1 : 0;\n p.x_stride_seq = x.stride(seq_dim);\n p.x_stride_token = x.stride(1);\n p.dt_stride_seq = dt.stride(seq_dim);\n p.dt_stride_token = dt.stride(1);\n p.B_stride_seq = B.stride(seq_dim);\n p.B_stride_token = B.stride(1);\n p.C_stride_seq = C.stride(seq_dim);\n p.C_stride_token = C.stride(1);\n p.out_stride_seq = output.stride(seq_dim);\n p.out_stride_token = output.stride(1);\n\n p.x_cache_stride_seq = x_cache.stride(0);\n p.x_cache_stride_head = x_cache.stride(1);\n p.x_cache_stride_pos = x_cache.stride(2);\n p.B_cache_stride_seq = B_cache.stride(0);\n p.B_cache_stride_group = B_cache.stride(1);\n p.B_cache_stride_pos = B_cache.stride(2);\n p.dt_cache_stride_seq = dt_cache.stride(0);\n p.dt_cache_stride_head = dt_cache.stride(1);\n\n // 32-bit address-fold guard. The kernel folds within-buffer inner indices (head*dim*dstate,\n // head*head_stride, group*dstate, …) into int32 before adding the int64 buffer/slot base — see\n // load_head / prefetch_state / store_state / the dt_cache scan. Buffer/slot-distance strides\n // (*_stride_seq, *_stride_dbuf) stay int64 and are unconstrained; only these inner ceilings must\n // fit int32. `nheads*dim*dstate` (the per-slot state extent) dominates every constexpr-stride\n // fold; the head-stride folds use runtime strides so are checked explicitly. Assert here so a\n // future large-tensor layout fails loudly instead of silently truncating an address.\n constexpr int64_t kInt32Max = 2147483647;\n FLASHINFER_CHECK(nheads * dim * dstate <= kInt32Max,\n \"32-bit address fold would overflow: nheads*dim*dstate=\", nheads * dim * dstate,\n \" exceeds int32 max=\", kInt32Max);\n FLASHINFER_CHECK(nheads * p.dt_cache_stride_head <= kInt32Max,\n \"32-bit address fold would overflow: nheads*dt_cache_stride_head=\",\n nheads * p.dt_cache_stride_head, \" exceeds int32 max=\", kInt32Max);\n\n // Launch\n ffi::CUDADeviceGuard device_guard(state.device().device_id);\n const cudaStream_t stream = get_stream(state.device());\n\n launchCheckpointingSsu<input_t, dt_t, weight_t, matrixA_t, state_t, stateIndex_t, state_scale_t>(\n p, static_cast<int>(precompute_heads_per_cta), stream);\n}\n\n} // namespace flashinfer::mamba::checkpointing\n"},"after_code":{"kind":"string","value":"/*\n * Copyright (c) 2025 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n// clang-format off\n// config.inc MUST come before the header: it defines DIM, DSTATE, NPREDICTED,\n// MAX_WINDOW constexprs that the header's function templates rely on.\n#include \"checkpointing_ssu_config.inc\"\n#include <flashinfer/mamba/checkpointing_ssu.cuh>\n#include <flashinfer/mamba/launch_checkpointing_ssu.cuh>\n// clang-format on\n#include <limits>\n\n#include \"tvm_ffi_utils.h\"\n\nusing namespace flashinfer;\nusing tvm::ffi::Optional;\n\nnamespace flashinfer::mamba::checkpointing {\n\nvoid checkpointing_ssu(\n TensorView state, // (state_cache_size, nheads, dim, dstate)\n TensorView x, // (batch, NPREDICTED, nheads, dim) / (1, total_tokens, nheads, dim) under varlen\n TensorView dt, // (batch, NPREDICTED, nheads, dim) tie_hdim / (1, total_tokens, nheads, dim)\n TensorView A, // (nheads, dim, dstate) tie_hdim\n TensorView B, // (batch, NPREDICTED, ngroups, dstate) / (1, total_tokens, ngroups, dstate)\n TensorView C, // same as B\n TensorView output, // same layout as x\n // Ring-buffer cache tensors (single-buffered, head-major; RING_BUFFER_LEN\n // = row count, runtime-implicit; MAX_WINDOW = RING_BUFFER_LEN - NPREDICTED)\n TensorView x_cache, // (state_cache_size, nheads, RING_BUFFER_LEN, dim)\n TensorView B_cache, // (state_cache_size, ngroups, RING_BUFFER_LEN, dstate)\n TensorView dt_cache, // (state_cache_size, nheads, RING_BUFFER_LEN) f32\n TensorView ring_start, // (state_cache_size,) int32\n TensorView prev_num_accepted, // (state_cache_size,) int32\n // Optional tensors\n Optional<TensorView> D, // (nheads, dim)\n Optional<TensorView> z, // same layout as x\n Optional<TensorView> dt_bias, // (nheads, dim) tie_hdim\n bool dt_softplus,\n Optional<TensorView> state_batch_indices, // (batch,) int32\n int64_t pad_slot_id,\n Optional<TensorView> state_scale, // (state_cache_size, nheads, dim) f32\n Optional<TensorView> rand_seed, // single int64\n int64_t d_split, // v12 §59: per-head DIM split factor (1, 2, or 4)\n Optional<TensorView> cu_seqlens, // (batch+1,) int32, varlen mode\n Optional<TensorView> cb_scaled, // two-kernel: bf16 (batch, nheads, 32, 8) fragA-native\n Optional<TensorView> cumAdt_vec, // two-kernel: f32 (batch, nheads, T_pad) raw cumAdt\n Optional<TensorView> cb_old, // two-kernel: bf16 (batch, nheads, 32, K_old/2) fragA-native\n int64_t precompute_heads_per_cta, // two-kernel PRECOMPUTE: heads per CTA (0 = heuristic)\n int64_t main_pipeline_stages, // two-kernel MAIN: pipeline depth (0 = heuristic)\n int64_t main_ctas_per_sm) { // two-kernel MAIN: grid cap (0 = heuristic)\n\n bool const is_varlen = cu_seqlens.has_value();\n\n // ── Extract dimensions ──\n auto const state_cache_size = state.size(0);\n auto const nheads = state.size(1);\n auto const dim = state.size(2);\n auto const dstate = state.size(3);\n auto const ring_buffer_len = x_cache.size(2);\n auto const ngroups = B.size(2);\n\n // In non-varlen mode, batch = x.size(0) and npredicted = x.size(1) (the\n // 4D batched layout). In varlen, the JIT compile-time NPREDICTED is the\n // max seq_len the caller commits to; the wrapper stamped it into the JIT\n // URI from `max_seqlen` and we read it back as the constexpr `NPREDICTED`\n // (validated against runtime cu_seqlens on the host side below). `batch`\n // = number of sequences = `cu_seqlens.size(0) - 1`.\n int64_t batch;\n int64_t npredicted;\n if (is_varlen) {\n auto const& cs = cu_seqlens.value();\n CHECK_CUDA(cs);\n CHECK_DIM(1, cs);\n FLASHINFER_CHECK(\n cs.size(0) >= 2,\n \"cu_seqlens must have shape (batch+1,) with batch >= 1, got size(0)=\", cs.size(0));\n FLASHINFER_CHECK(cs.dtype().code == kDLInt && cs.dtype().bits == 32,\n \"cu_seqlens must be int32\");\n CHECK_CONTIGUOUS(cs);\n batch = cs.size(0) - 1;\n npredicted = NPREDICTED; // JIT-stamped — wrapper ensures max(seq_lens) <= NPREDICTED.\n } else {\n batch = x.size(0);\n npredicted = x.size(1);\n }\n\n // ── JIT compile-time / runtime cross-check ──\n // NPREDICTED and MAX_WINDOW are JIT compile-time constants stamped by the\n // wrapper. In non-varlen NPREDICTED = x.shape[1]; in varlen NPREDICTED =\n // user-supplied `max_seqlen` (upper bound on every cu_seqlens diff).\n FLASHINFER_CHECK(npredicted == NPREDICTED, is_varlen ? \"max_seqlen=\" : \"x.size(1)=\", npredicted,\n \" must equal JIT NPREDICTED=\", NPREDICTED);\n // The LOGICAL replay window is the ring row count minus one speculative\n // window (ReplaySSM early-flush rule: pnat + 2T > RING_BUFFER_LEN).\n auto const max_window = ring_buffer_len - npredicted;\n FLASHINFER_CHECK(max_window == MAX_WINDOW, \"x_cache.size(2) - npredicted = \", max_window,\n \" must equal JIT MAX_WINDOW=\", MAX_WINDOW);\n FLASHINFER_CHECK(npredicted <= max_window, \"npredicted=\", npredicted,\n \" must be <= max_window=\", max_window, \" (ring_buffer_len=\", ring_buffer_len,\n \")\");\n\n // ── Validate state ──\n CHECK_CUDA(state);\n CHECK_DIM(4, state);\n {\n auto s = state.strides();\n auto sz = state.sizes();\n FLASHINFER_CHECK(s[3] == 1, \"state dim 3 (dstate) must have stride 1, got \", s[3]);\n FLASHINFER_CHECK(s[2] == sz[3], \"state dim 2 (dim) must be contiguous with dim 3, got stride \",\n s[2], \" expected \", sz[3]);\n FLASHINFER_CHECK(s[1] == sz[2] * sz[3],\n \"state dim 1 (nheads) must be contiguous with dim 2, got stride \", s[1],\n \" expected \", sz[2] * sz[3]);\n }\n\n // Two-kernel persistent-main runtime tuning knobs. Zero preserves the\n // launcher's regime default; positive values override it.\n FLASHINFER_CHECK(\n main_pipeline_stages == 0 || main_pipeline_stages == 1 || main_pipeline_stages == 2,\n \"main_pipeline_stages=\", main_pipeline_stages, \" must be 0 (heuristic), 1, or 2\");\n FLASHINFER_CHECK(main_ctas_per_sm >= 0 && main_ctas_per_sm <= std::numeric_limits<int>::max(),\n \"main_ctas_per_sm=\", main_ctas_per_sm,\n \" must be 0 (heuristic) or a positive value representable as int\");\n\n // ── Validate x ──\n // Non-varlen: shape (batch, NPREDICTED, nheads, dim).\n // Varlen : shape (1, total_tokens, nheads, dim) — batch axis collapsed,\n // token axis is the outer iteration. The kernel reads x via\n // `bos * x_stride_token + …` so x_stride_token is the per-token\n // stride in either layout (= nheads*dim for contig).\n CHECK_CUDA(x);\n CHECK_DIM(4, x);\n if (is_varlen) {\n FLASHINFER_CHECK(x.size(0) == 1, \"varlen: x.size(0)=\", x.size(0), \" must be 1\");\n } else {\n FLASHINFER_CHECK(x.size(0) == batch, \"x.size(0)=\", x.size(0), \" must equal batch=\", batch);\n FLASHINFER_CHECK(x.size(1) == npredicted, \"x.size(1)=\", x.size(1),\n \" must equal npredicted=\", npredicted);\n }\n FLASHINFER_CHECK(x.size(2) == nheads, \"x.size(2)=\", x.size(2), \" must equal nheads=\", nheads);\n FLASHINFER_CHECK(x.size(3) == dim, \"x.size(3)=\", x.size(3), \" must equal dim=\", dim);\n CHECK_LAST_DIM_CONTIGUOUS(x);\n FLASHINFER_CHECK(x.stride(2) == dim, \"x.stride(2)=\", x.stride(2), \" must equal dim=\", dim,\n \" ((nheads, dim) must be contiguous)\");\n\n // In varlen, all per-token tensors share the flattened token axis — use\n // x.size(1) as the canonical total_tokens and cross-check the others below.\n int64_t const total_tokens = is_varlen ? x.size(1) : 0;\n\n // ── Validate dt ──\n CHECK_CUDA(dt);\n CHECK_DIM(4, dt);\n if (is_varlen) {\n FLASHINFER_CHECK(dt.size(0) == 1, \"varlen: dt.size(0)=\", dt.size(0), \" must be 1\");\n FLASHINFER_CHECK(dt.size(1) == total_tokens, \"varlen: dt.size(1)=\", dt.size(1),\n \" must equal x.size(1)=\", total_tokens);\n } else {\n FLASHINFER_CHECK(dt.size(0) == batch, \"dt.size(0)=\", dt.size(0), \" must equal batch=\", batch);\n FLASHINFER_CHECK(dt.size(1) == npredicted, \"dt.size(1)=\", dt.size(1),\n \" must equal npredicted=\", npredicted);\n }\n FLASHINFER_CHECK(dt.size(2) == nheads, \"dt.size(2)=\", dt.size(2), \" must equal nheads=\", nheads);\n FLASHINFER_CHECK(dt.size(3) == dim, \"dt.size(3)=\", dt.size(3), \" must equal dim=\", dim);\n FLASHINFER_CHECK(dt.stride(2) == 1, \"dt.stride(2) must be 1 (tie_hdim), got \", dt.stride(2));\n FLASHINFER_CHECK(dt.stride(3) == 0, \"dt.stride(3) must be 0 (tie_hdim), got \", dt.stride(3));\n\n // ── Validate A: (nheads, dim, dstate) tie_hdim ──\n CHECK_CUDA(A);\n CHECK_DIM(3, A);\n FLASHINFER_CHECK(A.size(0) == nheads, \"A.size(0)=\", A.size(0), \" must equal nheads=\", nheads);\n FLASHINFER_CHECK(A.size(1) == dim, \"A.size(1)=\", A.size(1), \" must equal dim=\", dim);\n FLASHINFER_CHECK(A.size(2) == dstate, \"A.size(2)=\", A.size(2), \" must equal dstate=\", dstate);\n FLASHINFER_CHECK(A.stride(0) == 1, \"A.stride(0) must be 1, got \", A.stride(0));\n FLASHINFER_CHECK(A.stride(1) == 0, \"A.stride(1) must be 0 (tie_hdim), got \", A.stride(1));\n FLASHINFER_CHECK(A.stride(2) == 0, \"A.stride(2) must be 0 (tie_hdim), got \", A.stride(2));\n\n // ── Validate B ──\n CHECK_CUDA(B);\n CHECK_DIM(4, B);\n if (is_varlen) {\n FLASHINFER_CHECK(B.size(0) == 1, \"varlen: B.size(0)=\", B.size(0), \" must be 1\");\n FLASHINFER_CHECK(B.size(1) == total_tokens, \"varlen: B.size(1)=\", B.size(1),\n \" must equal x.size(1)=\", total_tokens);\n } else {\n FLASHINFER_CHECK(B.size(0) == batch, \"B.size(0)=\", B.size(0), \" must equal batch=\", batch);\n FLASHINFER_CHECK(B.size(1) == npredicted, \"B.size(1)=\", B.size(1),\n \" must equal npredicted=\", npredicted);\n }\n FLASHINFER_CHECK(B.size(3) == dstate, \"B.size(3)=\", B.size(3), \" must equal dstate=\", dstate);\n CHECK_LAST_DIM_CONTIGUOUS(B);\n FLASHINFER_CHECK(B.stride(2) == dstate, \"B.stride(2)=\", B.stride(2),\n \" must equal dstate=\", dstate, \" ((ngroups, dstate) must be contiguous)\");\n FLASHINFER_CHECK(nheads % ngroups == 0, \"nheads=\", nheads,\n \" must be divisible by ngroups=\", ngroups);\n\n // ── Validate C ──\n CHECK_CUDA(C);\n CHECK_DIM(4, C);\n if (is_varlen) {\n FLASHINFER_CHECK(C.size(0) == 1, \"varlen: C.size(0)=\", C.size(0), \" must be 1\");\n FLASHINFER_CHECK(C.size(1) == total_tokens, \"varlen: C.size(1)=\", C.size(1),\n \" must equal x.size(1)=\", total_tokens);\n } else {\n FLASHINFER_CHECK(C.size(0) == batch, \"C.size(0)=\", C.size(0), \" must equal batch=\", batch);\n FLASHINFER_CHECK(C.size(1) == npredicted, \"C.size(1)=\", C.size(1),\n \" must equal npredicted=\", npredicted);\n }\n FLASHINFER_CHECK(C.size(2) == ngroups, \"C.size(2)=\", C.size(2), \" must equal ngroups=\", ngroups);\n FLASHINFER_CHECK(C.size(3) == dstate, \"C.size(3)=\", C.size(3), \" must equal dstate=\", dstate);\n CHECK_LAST_DIM_CONTIGUOUS(C);\n FLASHINFER_CHECK(C.stride(2) == dstate, \"C.stride(2)=\", C.stride(2),\n \" must equal dstate=\", dstate, \" ((ngroups, dstate) must be contiguous)\");\n\n // ── Validate output ──\n CHECK_CUDA(output);\n CHECK_DIM(4, output);\n if (is_varlen) {\n FLASHINFER_CHECK(output.size(0) == 1, \"varlen: output.size(0)=\", output.size(0), \" must be 1\");\n FLASHINFER_CHECK(output.size(1) == total_tokens, \"varlen: output.size(1)=\", output.size(1),\n \" must equal x.size(1)=\", total_tokens);\n } else {\n FLASHINFER_CHECK(output.size(0) == batch, \"output.size(0)=\", output.size(0),\n \" must equal batch=\", batch);\n FLASHINFER_CHECK(output.size(1) == npredicted, \"output.size(1)=\", output.size(1),\n \" must equal npredicted=\", npredicted);\n }\n FLASHINFER_CHECK(output.size(2) == nheads, \"output.size(2)=\", output.size(2),\n \" must equal nheads=\", nheads);\n FLASHINFER_CHECK(output.size(3) == dim, \"output.size(3)=\", output.size(3),\n \" must equal dim=\", dim);\n CHECK_LAST_DIM_CONTIGUOUS(output);\n FLASHINFER_CHECK(output.stride(2) == dim, \"output.stride(2)=\", output.stride(2),\n \" must equal dim=\", dim, \" ((nheads, dim) must be contiguous)\");\n\n // ── Validate ring-buffer cache tensors ──\n // x_cache: kernel gathers one head's rows → (RING_BUFFER_LEN, dim) contig per head.\n CHECK_CUDA(x_cache);\n CHECK_DIM(4, x_cache); // (state_cache_size, nheads, RING_BUFFER_LEN, dim)\n FLASHINFER_CHECK(x_cache.size(0) == state_cache_size, \"x_cache.size(0)=\", x_cache.size(0),\n \" must equal state_cache_size=\", state_cache_size);\n FLASHINFER_CHECK(x_cache.size(1) == nheads, \"x_cache.size(1)=\", x_cache.size(1),\n \" must equal nheads=\", nheads);\n FLASHINFER_CHECK(x_cache.size(3) == dim, \"x_cache.size(3)=\", x_cache.size(3),\n \" must equal dim=\", dim);\n CHECK_LAST_DIM_CONTIGUOUS(x_cache);\n FLASHINFER_CHECK(x_cache.stride(2) == dim, \"x_cache.stride(2)=\", x_cache.stride(2),\n \" must equal dim=\", dim, \" ((RING_BUFFER_LEN, dim) must be contiguous)\");\n\n // B_cache: one group's rows → (RING_BUFFER_LEN, dstate) contig per group.\n CHECK_CUDA(B_cache);\n CHECK_DIM(4, B_cache); // (state_cache_size, ngroups, RING_BUFFER_LEN, dstate)\n FLASHINFER_CHECK(B_cache.size(0) == state_cache_size, \"B_cache.size(0)=\", B_cache.size(0),\n \" must equal state_cache_size=\", state_cache_size);\n FLASHINFER_CHECK(B_cache.size(1) == ngroups, \"B_cache.size(1)=\", B_cache.size(1),\n \" must equal ngroups=\", ngroups);\n FLASHINFER_CHECK(B_cache.size(2) == ring_buffer_len, \"B_cache.size(2)=\", B_cache.size(2),\n \" must equal ring_buffer_len=\", ring_buffer_len);\n FLASHINFER_CHECK(B_cache.size(3) == dstate, \"B_cache.size(3)=\", B_cache.size(3),\n \" must equal dstate=\", dstate);\n CHECK_LAST_DIM_CONTIGUOUS(B_cache);\n FLASHINFER_CHECK(B_cache.stride(2) == dstate, \"B_cache.stride(2)=\", B_cache.stride(2),\n \" must equal dstate=\", dstate,\n \" ((RING_BUFFER_LEN, dstate) must be contiguous)\");\n\n // dt_cache: one head's row → RING_BUFFER_LEN contig.\n CHECK_CUDA(dt_cache);\n CHECK_DIM(3, dt_cache); // (state_cache_size, nheads, RING_BUFFER_LEN)\n FLASHINFER_CHECK(dt_cache.size(0) == state_cache_size, \"dt_cache.size(0)=\", dt_cache.size(0),\n \" must equal state_cache_size=\", state_cache_size);\n FLASHINFER_CHECK(dt_cache.size(1) == nheads, \"dt_cache.size(1)=\", dt_cache.size(1),\n \" must equal nheads=\", nheads);\n FLASHINFER_CHECK(dt_cache.size(2) == ring_buffer_len, \"dt_cache.size(2)=\", dt_cache.size(2),\n \" must equal ring_buffer_len=\", ring_buffer_len);\n CHECK_LAST_DIM_CONTIGUOUS(dt_cache);\n\n CHECK_CUDA(ring_start);\n CHECK_DIM(1, ring_start);\n FLASHINFER_CHECK(ring_start.size(0) == state_cache_size,\n \"ring_start.size(0)=\", ring_start.size(0),\n \" must equal state_cache_size=\", state_cache_size);\n CHECK_CONTIGUOUS(ring_start);\n\n CHECK_CUDA(prev_num_accepted);\n CHECK_DIM(1, prev_num_accepted);\n FLASHINFER_CHECK(prev_num_accepted.size(0) == state_cache_size,\n \"prev_num_accepted.size(0)=\", prev_num_accepted.size(0),\n \" must equal state_cache_size=\", state_cache_size);\n CHECK_CONTIGUOUS(prev_num_accepted);\n\n // ── Validate optional D ──\n if (D.has_value()) {\n auto& Dv = D.value();\n CHECK_CUDA(Dv);\n CHECK_DIM(2, Dv);\n FLASHINFER_CHECK(Dv.size(0) == nheads, \"D.size(0)=\", Dv.size(0), \" must equal nheads=\", nheads);\n FLASHINFER_CHECK(Dv.size(1) == dim, \"D.size(1)=\", Dv.size(1), \" must equal dim=\", dim);\n FLASHINFER_CHECK(Dv.stride(0) == 1, \"D.stride(0) must be 1 (tie_hdim), got \", Dv.stride(0));\n FLASHINFER_CHECK(Dv.stride(1) == 0, \"D.stride(1) must be 0 (tie_hdim), got \", Dv.stride(1));\n }\n\n // ── Validate optional dt_bias ──\n if (dt_bias.has_value()) {\n auto& db = dt_bias.value();\n CHECK_CUDA(db);\n CHECK_DIM(2, db);\n FLASHINFER_CHECK(db.size(0) == nheads, \"dt_bias.size(0)=\", db.size(0),\n \" must equal nheads=\", nheads);\n FLASHINFER_CHECK(db.size(1) == dim, \"dt_bias.size(1)=\", db.size(1), \" must equal dim=\", dim);\n FLASHINFER_CHECK(db.stride(0) == 1, \"dt_bias.stride(0) must be 1 (tie_hdim), got \",\n db.stride(0));\n FLASHINFER_CHECK(db.stride(1) == 0, \"dt_bias.stride(1) must be 0 (tie_hdim), got \",\n db.stride(1));\n }\n\n // ── Validate optional z: same layout/contig rules as x ──\n if (z.has_value()) {\n auto& zv = z.value();\n CHECK_CUDA(zv);\n CHECK_DIM(4, zv);\n if (is_varlen) {\n FLASHINFER_CHECK(zv.size(0) == 1, \"varlen: z.size(0)=\", zv.size(0), \" must be 1\");\n FLASHINFER_CHECK(zv.size(1) == total_tokens, \"varlen: z.size(1)=\", zv.size(1),\n \" must equal x.size(1)=\", total_tokens);\n } else {\n FLASHINFER_CHECK(zv.size(0) == batch, \"z.size(0)=\", zv.size(0), \" must equal batch=\", batch);\n FLASHINFER_CHECK(zv.size(1) == npredicted, \"z.size(1)=\", zv.size(1),\n \" must equal npredicted=\", npredicted);\n }\n FLASHINFER_CHECK(zv.size(2) == nheads, \"z.size(2)=\", zv.size(2), \" must equal nheads=\", nheads);\n FLASHINFER_CHECK(zv.size(3) == dim, \"z.size(3)=\", zv.size(3), \" must equal dim=\", dim);\n CHECK_LAST_DIM_CONTIGUOUS(zv);\n FLASHINFER_CHECK(zv.stride(2) == dim, \"z.stride(2)=\", zv.stride(2), \" must equal dim=\", dim,\n \" ((nheads, dim) must be contiguous)\");\n }\n\n // ── Validate optional state_batch_indices ──\n if (state_batch_indices.has_value()) {\n auto& sbi = state_batch_indices.value();\n CHECK_CUDA(sbi);\n CHECK_DIM(1, sbi);\n FLASHINFER_CHECK(sbi.size(0) == batch, \"state_batch_indices.size(0)=\", sbi.size(0),\n \" must equal batch=\", batch);\n CHECK_CONTIGUOUS(sbi);\n }\n\n // ── Validate optional state_scale: (state_cache_size, nheads, dim) ──\n // Inner two dims (nheads, dim) must be contiguous; only batch stride is\n // parameterized in the params struct.\n if (state_scale.has_value()) {\n auto const& ss = state_scale.value();\n CHECK_CUDA(ss);\n CHECK_DIM(3, ss);\n FLASHINFER_CHECK(ss.size(0) == state_cache_size, \"state_scale.size(0)=\", ss.size(0),\n \" must equal state_cache_size=\", state_cache_size);\n FLASHINFER_CHECK(ss.size(1) == nheads, \"state_scale.size(1)=\", ss.size(1),\n \" must equal nheads=\", nheads);\n FLASHINFER_CHECK(ss.size(2) == dim, \"state_scale.size(2)=\", ss.size(2),\n \" must equal dim=\", dim);\n FLASHINFER_CHECK(ss.stride(2) == 1, \"state_scale.stride(2) must be 1, got \", ss.stride(2));\n FLASHINFER_CHECK(ss.stride(1) == dim, \"state_scale.stride(1)=\", ss.stride(1),\n \" must equal dim=\", dim, \" ((nheads, dim) must be contiguous)\");\n }\n\n // ── Dtype consistency ──\n // input_dtype = x.dtype; all activation tensors (B, C, output, z, x_cache,\n // B_cache) and the state cache's \"input-side\" mirrors must match it.\n // weight_dtype = D.dtype = dt_bias.dtype (kernel template sees one\n // weight_t for both).\n // Cache scalar tensors have fixed dtypes hardcoded in the kernel.\n {\n auto input_dtype = x.dtype();\n FLASHINFER_CHECK(B.dtype() == input_dtype, \"B.dtype must match x.dtype\");\n FLASHINFER_CHECK(C.dtype() == input_dtype, \"C.dtype must match x.dtype\");\n FLASHINFER_CHECK(output.dtype() == input_dtype, \"output.dtype must match x.dtype\");\n FLASHINFER_CHECK(x_cache.dtype() == input_dtype, \"x_cache.dtype must match x.dtype\");\n FLASHINFER_CHECK(B_cache.dtype() == input_dtype, \"B_cache.dtype must match x.dtype\");\n if (z.has_value()) {\n FLASHINFER_CHECK(z.value().dtype() == input_dtype, \"z.dtype must match x.dtype\");\n }\n if (D.has_value() && dt_bias.has_value()) {\n FLASHINFER_CHECK(D.value().dtype() == dt_bias.value().dtype(),\n \"D.dtype must equal dt_bias.dtype (kernel uses a single weight_t)\");\n }\n // dt_cache is produced by this same kernel in f32 and consumed back in\n // f32 on the next call (replay decays are recomputed from it).\n FLASHINFER_CHECK(dt_cache.dtype().code == kDLFloat && dt_cache.dtype().bits == 32,\n \"dt_cache must be float32\");\n // Index tensors used by the kernel as int32 scalars.\n FLASHINFER_CHECK(ring_start.dtype().code == kDLInt && ring_start.dtype().bits == 32,\n \"ring_start must be int32\");\n FLASHINFER_CHECK(\n prev_num_accepted.dtype().code == kDLInt && prev_num_accepted.dtype().bits == 32,\n \"prev_num_accepted must be int32\");\n if (state_batch_indices.has_value()) {\n auto sbi_dt = state_batch_indices.value().dtype();\n FLASHINFER_CHECK(sbi_dt.code == kDLInt && (sbi_dt.bits == 32 || sbi_dt.bits == 64),\n \"state_batch_indices must be int32 or int64\");\n }\n if (state_scale.has_value()) {\n auto ss_dt = state_scale.value().dtype();\n FLASHINFER_CHECK(ss_dt.code == kDLFloat && ss_dt.bits == 32, \"state_scale must be float32\");\n }\n // Quantized state dtypes (int8, fp8_e4m3fn, ...) require a state_scale\n // tensor; non-quantized dtypes must not pass one. Mirrors the Python\n // wrapper assertion and matches the kernel's compile-time\n // `state_scale_t == void` gating.\n {\n auto sd = state.dtype();\n bool const is_int8 = (sd.code == kDLInt && sd.bits == 8);\n bool const is_fp8 = (sd.code == kDLFloat8_e4m3fn && sd.bits == 8);\n bool const is_quantized_state = is_int8 || is_fp8;\n if (is_quantized_state) {\n FLASHINFER_CHECK(state_scale.has_value(),\n \"Quantized state.dtype (int8/fp8_e4m3fn) requires a state_scale tensor \"\n \"of shape (state_cache_size, nheads, dim) and dtype float32\");\n // The 8-bit replay path uses Layout<_4, _1> (M-shard per warp) which\n // needs per-warp M = D_PER_CTA / 4 >= 16 (m16n8 atom M). This forces\n // D_PER_CTA >= 64, i.e. d_split == 1.\n FLASHINFER_CHECK(\n d_split == 1,\n \"Quantized state.dtype (int8/fp8_e4m3fn) requires d_split=1 (got d_split=\", d_split,\n \"); the M-shard-per-warp replay layout needs D_PER_CTA / 4 >= 16.\");\n } else {\n FLASHINFER_CHECK(!state_scale.has_value(),\n \"state_scale must be None for non-quantized state.dtype \"\n \"(allowed quantized dtypes: {int8, fp8_e4m3fn})\");\n }\n }\n }\n\n // ── Populate params ──\n CheckpointingSsuParams p;\n\n // ── Validate d_split (v12 §59) ──\n // Allowed for v12: {1, 2}. d_split=4 deferred to v12.x (needs warp-count\n // restructure — output MMA `_1×4` layout requires D_PER_CTA ≥ 32).\n FLASHINFER_CHECK(d_split == 1 || d_split == 2, \"d_split=\", d_split,\n \" must be one of {1, 2} (d_split=4 is deferred to v12.x)\");\n FLASHINFER_CHECK(dim % d_split == 0, \"dim=\", dim, \" must be divisible by d_split=\", d_split);\n FLASHINFER_CHECK(dim / d_split >= 32, \"d_split=\", d_split, \" gives D_PER_CTA=\", dim / d_split,\n \" < 32 (output MMA m16n8 atom floor with _1×4 warp layout)\");\n\n // ── Validate precompute_heads_per_cta (two-kernel PRECOMPUTE head-tiling, host knob) ──\n // 0 = use the launcher's co-residency heuristic; >0 overrides and must match\n // the HEADS_PER_GROUP>>k chain instantiated by dispatch_heads_per_cta.\n {\n int64_t const hpg = nheads / ngroups;\n bool valid_heads_per_cta = precompute_heads_per_cta == 0;\n for (int64_t candidate = hpg; candidate >= 1; candidate >>= 1) {\n valid_heads_per_cta |= precompute_heads_per_cta == candidate;\n if (candidate == 1) break;\n }\n FLASHINFER_CHECK(valid_heads_per_cta, \"precompute_heads_per_cta=\", precompute_heads_per_cta,\n \" must be 0 (heuristic) or a value on the HEADS_PER_GROUP>>k chain \"\n \"(HEADS_PER_GROUP=\",\n hpg, \")\");\n }\n\n p.batch = batch;\n p.nheads = nheads;\n p.dim = dim;\n p.dstate = dstate;\n p.ngroups = ngroups;\n p.state_cache_size = state_cache_size;\n p.npredicted = npredicted;\n p.max_window = max_window;\n p.pad_slot_id = pad_slot_id;\n p.d_split = static_cast<int32_t>(d_split);\n p.dt_softplus = dt_softplus;\n\n // Pointers\n p.state = state.data_ptr();\n p.x = const_cast<void*>(x.data_ptr());\n p.dt = const_cast<void*>(dt.data_ptr());\n p.A = const_cast<void*>(A.data_ptr());\n p.B = const_cast<void*>(B.data_ptr());\n p.C = const_cast<void*>(C.data_ptr());\n p.output = output.data_ptr();\n\n p.x_cache = x_cache.data_ptr();\n p.B_cache = B_cache.data_ptr();\n p.dt_cache = dt_cache.data_ptr();\n p.ring_start = const_cast<void*>(ring_start.data_ptr());\n p.ring_buffer_len = static_cast<int32_t>(ring_buffer_len);\n p.prev_num_accepted = const_cast<void*>(prev_num_accepted.data_ptr());\n\n if (D.has_value()) p.D = const_cast<void*>(D.value().data_ptr());\n if (z.has_value()) {\n p.z = const_cast<void*>(z.value().data_ptr());\n // Same seq-dim selection as the rest of the batch-side tensors below.\n p.z_stride_seq = z.value().stride(is_varlen ? 1 : 0);\n p.z_stride_token = z.value().stride(1);\n }\n if (dt_bias.has_value()) p.dt_bias = const_cast<void*>(dt_bias.value().data_ptr());\n if (state_batch_indices.has_value())\n p.state_batch_indices = const_cast<void*>(state_batch_indices.value().data_ptr());\n if (is_varlen) {\n p.cu_seqlens = const_cast<void*>(cu_seqlens.value().data_ptr());\n }\n if (state_scale.has_value()) {\n p.state_scale = state_scale.value().data_ptr();\n p.state_scale_stride_seq = state_scale.value().stride(0);\n }\n if (rand_seed.has_value()) {\n auto const& rs = rand_seed.value();\n CHECK_CUDA(rs);\n FLASHINFER_CHECK(rs.numel() == 1, \"rand_seed must be single-element, got numel=\", rs.numel());\n FLASHINFER_CHECK(rs.dtype().code == kDLInt && rs.dtype().bits == 64, \"rand_seed must be int64\");\n p.rand_seed = static_cast<const int64_t*>(rs.data_ptr());\n }\n\n // Two-kernel split scratch (presence of cb_scaled selects precompute+main).\n // Caller-allocated (graph-safe). The Python wrapper enforces the all-or-none\n // trio; shape/device/contiguity/dtype are validated here so a bad scratch\n // fails loudly instead of corrupting memory or faulting inside the kernel.\n // Expected layouts (see the wrapper / bench allocator): cb_scaled/cb_old are\n // input-dtype fragA-native (., ., 32, regs); cumAdt_vec is f32 (., ., T_pad).\n // fragA-native scratch: each (batch, head)'s CB is one MMA A-fragment stored\n // as [warp lane, register]. The lane axis is a full warp; the register axis\n // is the A-operand size — kCbScaledRegs for the new-token m16n8k16 CB,\n // k_old_half (= K_old/2) for the old-token m16n8k{K_old} CB.\n constexpr int64_t kWarpSize = 32;\n constexpr int64_t kCbScaledRegs = 8; // m16n8k16 A-operand regs/lane\n int64_t const t_pad = ((npredicted + 15) / 16) * 16; // cumAdt_vec: next_multiple_of<16>\n int64_t const k_old_half = (((max_window + 7) / 8) * 8) / 2; // K_old/2, K_old=next_mult<8>\n if (cb_scaled.has_value()) {\n auto const& cb = cb_scaled.value();\n CHECK_CUDA(cb);\n CHECK_DIM(4, cb);\n CHECK_CONTIGUOUS(cb);\n FLASHINFER_CHECK(cb.dtype().code == x.dtype().code && cb.dtype().bits == x.dtype().bits,\n \"cb_scaled dtype must match x (input dtype)\");\n FLASHINFER_CHECK(cb.size(0) >= batch && cb.size(1) == nheads && cb.size(2) == kWarpSize &&\n cb.size(3) == kCbScaledRegs,\n \"cb_scaled must be (>=batch, nheads, \", kWarpSize, \", \", kCbScaledRegs,\n \"), got (\", cb.size(0), \", \", cb.size(1), \", \", cb.size(2), \", \", cb.size(3),\n \")\");\n p.cb_scaled = const_cast<void*>(cb.data_ptr());\n }\n if (cumAdt_vec.has_value()) {\n auto const& cv = cumAdt_vec.value();\n CHECK_CUDA(cv);\n CHECK_DIM(3, cv);\n CHECK_CONTIGUOUS(cv);\n FLASHINFER_CHECK(cv.dtype().code == kDLFloat && cv.dtype().bits == 32,\n \"cumAdt_vec must be float32\");\n FLASHINFER_CHECK(cv.size(0) >= batch && cv.size(1) == nheads && cv.size(2) == t_pad,\n \"cumAdt_vec must be (>=batch, nheads, \", t_pad, \"), got (\", cv.size(0), \", \",\n cv.size(1), \", \", cv.size(2), \")\");\n p.cumAdt_vec = const_cast<void*>(cv.data_ptr());\n }\n if (cb_old.has_value()) {\n auto const& cbo = cb_old.value();\n CHECK_CUDA(cbo);\n CHECK_DIM(4, cbo);\n CHECK_CONTIGUOUS(cbo);\n FLASHINFER_CHECK(cbo.dtype().code == x.dtype().code && cbo.dtype().bits == x.dtype().bits,\n \"cb_old dtype must match x (input dtype)\");\n FLASHINFER_CHECK(cbo.size(0) >= batch && cbo.size(1) == nheads && cbo.size(2) == kWarpSize &&\n cbo.size(3) == k_old_half,\n \"cb_old must be (>=batch, nheads, \", kWarpSize, \", \", k_old_half, \"), got (\",\n cbo.size(0), \", \", cbo.size(1), \", \", cbo.size(2), \", \", cbo.size(3), \")\");\n p.cb_old = const_cast<void*>(cbo.data_ptr());\n }\n // Strides\n p.state_stride_seq = state.stride(0);\n\n // `*_stride_seq` is the outer iteration stride. Non-varlen iterates over\n // dim 0 (per-batch), varlen iterates over dim 1 (per-token) — sequences\n // are packed into a single batch in the (1, total_tokens, ...) layout.\n // The kernel uses one formula `seq * *_stride_seq` for both modes.\n int const seq_dim = is_varlen ? 1 : 0;\n p.x_stride_seq = x.stride(seq_dim);\n p.x_stride_token = x.stride(1);\n p.dt_stride_seq = dt.stride(seq_dim);\n p.dt_stride_token = dt.stride(1);\n p.B_stride_seq = B.stride(seq_dim);\n p.B_stride_token = B.stride(1);\n p.C_stride_seq = C.stride(seq_dim);\n p.C_stride_token = C.stride(1);\n p.out_stride_seq = output.stride(seq_dim);\n p.out_stride_token = output.stride(1);\n\n p.x_cache_stride_seq = x_cache.stride(0);\n p.x_cache_stride_head = x_cache.stride(1);\n p.x_cache_stride_pos = x_cache.stride(2);\n p.B_cache_stride_seq = B_cache.stride(0);\n p.B_cache_stride_group = B_cache.stride(1);\n p.B_cache_stride_pos = B_cache.stride(2);\n p.dt_cache_stride_seq = dt_cache.stride(0);\n p.dt_cache_stride_head = dt_cache.stride(1);\n\n // 32-bit address-fold guard. The kernel folds within-buffer inner indices (head*dim*dstate,\n // head*head_stride, group*dstate, …) into int32 before adding the int64 buffer/slot base — see\n // load_head / prefetch_state / store_state / the dt_cache scan. Buffer/slot-distance strides\n // (*_stride_seq, *_stride_dbuf) stay int64 and are unconstrained; only these inner ceilings must\n // fit int32. `nheads*dim*dstate` (the per-slot state extent) dominates every constexpr-stride\n // fold; the head-stride folds use runtime strides so are checked explicitly. Assert here so a\n // future large-tensor layout fails loudly instead of silently truncating an address.\n constexpr int64_t kInt32Max = 2147483647;\n FLASHINFER_CHECK(nheads * dim * dstate <= kInt32Max,\n \"32-bit address fold would overflow: nheads*dim*dstate=\", nheads * dim * dstate,\n \" exceeds int32 max=\", kInt32Max);\n FLASHINFER_CHECK(nheads * p.dt_cache_stride_head <= kInt32Max,\n \"32-bit address fold would overflow: nheads*dt_cache_stride_head=\",\n nheads * p.dt_cache_stride_head, \" exceeds int32 max=\", kInt32Max);\n\n // Launch\n ffi::CUDADeviceGuard device_guard(state.device().device_id);\n const cudaStream_t stream = get_stream(state.device());\n\n launchCheckpointingSsu<input_t, dt_t, weight_t, matrixA_t, state_t, stateIndex_t, state_scale_t>(\n p, static_cast<int>(precompute_heads_per_cta), static_cast<int>(main_pipeline_stages),\n static_cast<int>(main_ctas_per_sm), stream);\n}\n\n} // namespace flashinfer::mamba::checkpointing\n"},"diff":{"kind":"string","value":"--- csrc/checkpointing_ssu.cu\n+++ csrc/checkpointing_ssu.cu\n@@ -20,6 +20,8 @@\n #include <flashinfer/mamba/checkpointing_ssu.cuh>\n #include <flashinfer/mamba/launch_checkpointing_ssu.cuh>\n // clang-format on\n+#include <limits>\n+\n #include \"tvm_ffi_utils.h\"\n \n using namespace flashinfer;\n@@ -56,7 +58,9 @@\n Optional<TensorView> cb_scaled, // two-kernel: bf16 (batch, nheads, 32, 8) fragA-native\n Optional<TensorView> cumAdt_vec, // two-kernel: f32 (batch, nheads, T_pad) raw cumAdt\n Optional<TensorView> cb_old, // two-kernel: bf16 (batch, nheads, 32, K_old/2) fragA-native\n- int64_t precompute_heads_per_cta) { // two-kernel PRECOMPUTE: heads per CTA (0 = heuristic)\n+ int64_t precompute_heads_per_cta, // two-kernel PRECOMPUTE: heads per CTA (0 = heuristic)\n+ int64_t main_pipeline_stages, // two-kernel MAIN: pipeline depth (0 = heuristic)\n+ int64_t main_ctas_per_sm) { // two-kernel MAIN: grid cap (0 = heuristic)\n \n bool const is_varlen = cu_seqlens.has_value();\n \n@@ -121,6 +125,15 @@\n \"state dim 1 (nheads) must be contiguous with dim 2, got stride \", s[1],\n \" expected \", sz[2] * sz[3]);\n }\n+\n+ // Two-kernel persistent-main runtime tuning knobs. Zero preserves the\n+ // launcher's regime default; positive values override it.\n+ FLASHINFER_CHECK(\n+ main_pipeline_stages == 0 || main_pipeline_stages == 1 || main_pipeline_stages == 2,\n+ \"main_pipeline_stages=\", main_pipeline_stages, \" must be 0 (heuristic), 1, or 2\");\n+ FLASHINFER_CHECK(main_ctas_per_sm >= 0 && main_ctas_per_sm <= std::numeric_limits<int>::max(),\n+ \"main_ctas_per_sm=\", main_ctas_per_sm,\n+ \" must be 0 (heuristic) or a positive value representable as int\");\n \n // ── Validate x ──\n // Non-varlen: shape (batch, NPREDICTED, nheads, dim).\n@@ -441,14 +454,18 @@\n \" < 32 (output MMA m16n8 atom floor with _1×4 warp layout)\");\n \n // ── Validate precompute_heads_per_cta (two-kernel PRECOMPUTE head-tiling, host knob) ──\n- // 0 = use the launcher's co-residency heuristic; >0 overrides (must divide HEADS_PER_GROUP).\n+ // 0 = use the launcher's co-residency heuristic; >0 overrides and must match\n+ // the HEADS_PER_GROUP>>k chain instantiated by dispatch_heads_per_cta.\n {\n int64_t const hpg = nheads / ngroups;\n- FLASHINFER_CHECK(precompute_heads_per_cta >= 0 &&\n- (precompute_heads_per_cta == 0 || hpg % precompute_heads_per_cta == 0),\n- \"precompute_heads_per_cta=\", precompute_heads_per_cta,\n- \" must be 0 (heuristic) or a positive divisor of HEADS_PER_GROUP \"\n- \"(nheads/ngroups=\",\n+ bool valid_heads_per_cta = precompute_heads_per_cta == 0;\n+ for (int64_t candidate = hpg; candidate >= 1; candidate >>= 1) {\n+ valid_heads_per_cta |= precompute_heads_per_cta == candidate;\n+ if (candidate == 1) break;\n+ }\n+ FLASHINFER_CHECK(valid_heads_per_cta, \"precompute_heads_per_cta=\", precompute_heads_per_cta,\n+ \" must be 0 (heuristic) or a value on the HEADS_PER_GROUP>>k chain \"\n+ \"(HEADS_PER_GROUP=\",\n hpg, \")\");\n }\n \n@@ -606,7 +623,8 @@\n const cudaStream_t stream = get_stream(state.device());\n \n launchCheckpointingSsu<input_t, dt_t, weight_t, matrixA_t, state_t, stateIndex_t, state_scale_t>(\n- p, static_cast<int>(precompute_heads_per_cta), stream);\n+ p, static_cast<int>(precompute_heads_per_cta), static_cast<int>(main_pipeline_stages),\n+ static_cast<int>(main_ctas_per_sm), stream);\n }\n \n } // namespace flashinfer::mamba::checkpointing"},"lines_added":{"kind":"number","value":26,"string":"26"},"lines_removed":{"kind":"number","value":8,"string":"8"},"files_in_commit":{"kind":"number","value":7,"string":"7"},"models_mentioned":{"kind":"list like","value":["nemotron"],"string":"[\n \"nemotron\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["H100"],"string":"[\n \"H100\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (csrc/checkpointing_ssu.cu).\n\nGoal: Add ReplaySSM autotuning\nTarget hardware: H100\nTarget models: nemotron\n\nCurrent file:\n```cuda\n/*\n * Copyright (c) 2025 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n// clang-format off\n// config.inc MUST come before the header: it defines DIM, DSTATE, NPREDICTED,\n// MAX_WINDOW constexprs that the header's function templates rely on.\n#include \"checkpointing_ssu_config.inc\"\n#include <flashinfer/mamba/checkpointing_ssu.cuh>\n#include <flashinfer/mamba/launch_checkpointing_ssu.cuh>\n// clang-format on\n#include \"tvm_ffi_utils.h\"\n\nusing namespace flashinfer;\nusing tvm::ffi::Optional;\n\nnamespace flashinfer::mamba::checkpointing {\n\nvoid checkpointing_ssu(\n TensorView state, // (state_cache_size, nheads, dim, dstate)\n TensorView x, // (batch, NPREDICTED, nheads, dim) / (1, total_tokens, nheads, dim) under varlen\n TensorView dt, // (batch, NPREDICTED, nheads, dim) tie_hdim / (1, total_tokens, nheads, dim)\n TensorView A, // (nheads, dim, dstate) tie_hdim\n TensorView B, // (batch, NPREDICTED, ngroups, dstate) / (1, total_tokens, ngroups, dstate)\n TensorView C, // same as B\n TensorView output, // same layout as x\n // Ring-buffer cache tensors (single-buffered, head-major; RING_BUFFER_LEN\n // = row count, runtime-implicit; MAX_WINDOW = RING_BUFFER_LEN - NPREDICTED)\n TensorView x_cache, // (state_cache_size, nheads, RING_BUFFER_LEN, dim)\n TensorView B_cache, // (state_cache_size, ngroups, RING_BUFFER_LEN, dstate)\n TensorView dt_cache, // (state_cache_size, nheads, RING_BUFFER_LEN) f32\n TensorView ring_start, // (state_cache_size,) int32\n TensorView prev_num_accepted, // (state_cache_size,) int32\n // Optional tensors\n Optional<TensorView> D, // (nheads, dim)\n Optional<TensorView> z, // same layout as x\n Optional<TensorView> dt_bias, // (nheads, dim) tie_hdim\n bool dt_softplus,\n Optional<TensorView> state_batch_indices, // (batch,) int32\n int64_t pad_slot_id,\n Optional<TensorView> state_scale, // (state_cache_size, nheads, dim) f32\n Optional<TensorView> rand_seed, // single int64\n int64_t d_split, // v12 §59: per-head DIM split factor (1, 2, or 4)\n Optional<TensorView> cu_seqlens, // (batch+1,) int32, varlen mode\n Optional<TensorView> cb_scaled, // two-kernel: bf16 (batch, nheads, 32, 8) fragA-native\n Optional<TensorView> cumAdt_vec, // two-kernel: f32 (batch, nheads, T_pad) raw cumAdt\n Optional<TensorView> cb_old, // two-kernel: bf16 (batch, nheads, 32, K_old/2) fragA-native\n int64_t precompute_heads_per_cta) { // two-kernel PRECOMPUTE: heads per CTA (0 = heuristic)\n\n bool const is_varlen = cu_seqlens.has_value();\n\n // ── Extract dimensions ──\n auto const state_cache_size = state.size(0);\n auto const nheads = state.size(1);\n auto const dim = state.size(2);\n auto const dstate = state.size(3);\n auto const ring_buffer_len = x_cache.size(2);\n auto const ngroups = B.size(2);\n\n // In non-varlen mode, batch = x.size(0) and npredicted = x.size(1) (the\n // 4D batched layout). In varlen, the JIT compile-time NPREDICTED is the\n // max seq_len the caller commits to; the wrapper stamped it into the JIT\n // URI from `max_seqlen` and we read it back as the constexpr `NPREDICTED`\n // (validated against runtime cu_seqlens on the host side below). `batch`\n // = number of sequences = `cu_seqlens.size(0) - 1`.\n int64_t batch;\n int64_t npredicted;\n if (is_varlen) {\n auto const& cs = cu_seqlens.value();\n CHECK_CUDA(cs);\n CHECK_DIM(1, cs);\n FLASHINFER_CHECK(\n cs.size(0) >= 2,\n \"cu_seqlens must have shape (batch+1,) with batch >= 1, got size(0)=\", cs.size(0));\n FLASHINFER_CHECK(cs.dtype().code == kDLInt && cs.dtype().bits == 32,\n \"cu_seqlens must be int32\");\n CHECK_CONTIGUOUS(cs);\n batch = cs.size(0) - 1;\n npredicted = NPREDICTED; // JIT-stamped — wrapper ensures max(seq_lens) <= NPREDICTED.\n } else {\n batch = x.size(0);\n npredicted = x.size(1);\n }\n\n // ── JIT compile-time / runtime cross-check ──\n // NPREDICTED and MAX_WINDOW are JIT compile-time constants stamped by the\n // wrapper. In non-varlen NPREDICTED = x.shape[1]; in varlen NPREDICTED =\n // user-supplied `max_seqlen` (upper bound on every cu_seqlens diff).\n FLASHINFER_CHECK(npredicted == NPREDICTED, is_varlen ? \"max_seqlen=\" : \"x.size(1)=\", npredicted,\n \" must equal JIT NPREDICTED=\", NPREDICTED);\n // The LOGICAL replay window is the ring row count minus one speculative\n // window (ReplaySSM early-flush rule: pnat + 2T > RING_BUFFER_LEN).\n auto const max_window = ring_buffer_len - npredicted;\n FLASHINFER_CHECK(max_window == MAX_WINDOW, \"x_cache.size(2) - npredicted = \", max_window,\n \" must equal JIT MAX_WINDOW=\", MAX_WINDOW);\n FLASHINFER_CHECK(npredicted <= max_window, \"npredicted=\", npredicted,\n \" must be <= max_window=\", max_window, \" (ring_buffer_len=\", ring_buffer_len,\n \")\");\n\n // ── Validate state ──\n CHECK_CUDA(state);\n CHECK_DIM(4, state);\n {\n auto s = state.strides();\n auto sz = state.sizes();\n FLASHINFER_CHECK(s[3] == 1, \"state dim 3 (dstate) must have stride 1, got \", s[3]);\n FLASHINFER_CHECK(s[2] == sz[3], \"state dim 2 (dim) must be contiguous with dim 3, got stride \",\n s[2], \" expected \", sz[3]);\n FLASHINFER_CHECK(s[1] == sz[2] * sz[3],\n \"state dim 1 (nheads) must be contiguous with dim 2, got stride \", s[1],\n \" expected \", sz[2] * sz[3]);\n }\n\n // ── Validate x ──\n // Non-varlen: shape (batch, NPREDICTED, nheads, dim).\n // Varlen : shape (1, total_tokens, nheads, dim) — batch axis collapsed,\n // token axis is the outer iteration. The kernel reads x via\n // `bos * x_stride_token + …` so x_stride_token is the per-token\n // stride in either layout (= nheads*dim for contig).\n CHECK_CUDA(x);\n CHECK_DIM(4, x);\n if (is_varlen) {\n FLASHINFER_CHECK(x.size(0) == 1, \"varlen: x.size(0)=\", x.size(0), \" must be 1\");\n } else {\n FLASHINFER_CHECK(x.size(0) == batch, \"x.size(0)=\", x.size(0), \" must equal batch=\", batch);\n FLASHINFER_CHECK(x.size(1) == npredicted, \"x.size(1)=\", x.size(1),\n \" must equal npredicted=\", npredicted);\n }\n FLASHINFER_CHECK(x.size(2) == nheads, \"x.size(2)=\", x.size(2), \" must equal nheads=\", nheads);\n FLASHINFER_CHECK(x.size(3) == dim, \"x.size(3)=\", x.size(3), \" must equal dim=\", dim);\n CHECK_LAST_DIM_CONTIGUOUS(x);\n FLASHINFER_CHECK(x.stride(2) == dim, \"x.stride(2)=\", x.stride(2), \" must equal dim=\", dim,\n \" ((nheads, dim) must be contiguous)\");\n\n // In varlen, all per-token tensors share the flattened token axis — use\n // x.size(1) as the canonical total_tokens and cross-check the others below.\n int64_t const total_tokens = is_varlen ? x.size(1) : 0;\n\n // ── Validate dt ──\n CHECK_CUDA(dt);\n CHECK_DIM(4, dt);\n if (is_varlen) {\n FLASHINFER_CHECK(dt.size(0) == 1, \"varlen: dt.size(0)=\", dt.size(0), \" must be 1\");\n FLASHINFER_CHECK(dt.size(1) == total_tokens, \"varlen: dt.size(1)=\", dt.size(1),\n \" must equal x.size(1)=\", total_tokens);\n } else {\n FLASHINFER_CHECK(dt.size(0) == batch, \"dt.size(0)=\", dt.size(0), \" must equal batch=\", batch);\n FLASHINFER_CHECK(dt.size(1) == npredicted, \"dt.size(1)=\", dt.size(1),\n \" must equal npredicted=\", npredicted);\n }\n FLASHINFER_CHECK(dt.size(2) == nheads, \"dt.size(2)=\", dt.size(2), \" must equal nheads=\", nheads);\n FLASHINFER_CHECK(dt.size(3) == dim, \"dt.size(3)=\", dt.size(3), \" must equal dim=\", dim);\n FLASHINFER_CHECK(dt.stride(2) == 1, \"dt.stride(2) must be 1 (tie_hdim), got \", dt.stride(2));\n FLASHINFER_CHECK(dt.stride(3) == 0, \"dt.stride(3) must be 0 (tie_hdim), got \", dt.stride(3));\n\n // ── Validate A: (nheads, dim, dstate) tie_hdim ──\n CHECK_CUDA(A);\n CHECK_DIM(3, A);\n FLASHINFER_CHECK(A.size(0) == nheads, \"A.size(0)=\", A.size(0), \" must equal nheads=\", nheads);\n FLASHINFER_CHECK(A.size(1) == dim, \"A.size(1)=\", A.size(1), \" must equal dim=\", dim);\n FLASHINFER_CHECK(A.size(2) == dstate, \"A.size(2)=\", A.size(2), \" must equal dstate=\", dstate);\n FLASHINFER_CHECK(A.stride(0) == 1, \"A.stride(0) must be 1, got \", A.stride(0));\n FLASHINFER_CHECK(A.stride(1) == 0, \"A.stride(1) must be 0 (tie_hdim), got \", A.stride(1));\n FLASHINFER_CHECK(A.stride(2) == 0, \"A.stride(2) must be 0 (tie_hdim), got \", A.stride(2));\n\n // ── Validate B ──\n CHECK_CUDA(B);\n CHECK_DIM(4, B);\n if (is_varlen) {\n FLASHINFER_CHECK(B.size(0) == 1, \"varlen: B.size(0)=\", B.size(0), \" must be 1\");\n FLASHINFER_CHECK(B.size(1) == total_tokens, \"varlen: B.size(1)=\", B.size(1),\n \" must equal x.size(1)=\", total_tokens);\n } else {\n FLASHINFER_CHECK(B.size(0) == batch, \"B.size(0)=\", B.size(0), \" must equal batch=\", batch);\n FLASHINFER_CHECK(B.size(1) == npredicted, \"B.size(1)=\", B.size(1),\n \" must equal npredicted=\", npredicted);\n }\n FLASHINFER_CHECK(B.size(3) == dstate, \"B.size(3)=\", B.size(3), \" must equal dstate=\", dstate);\n CHECK_LAST_DIM_CONTIGUOUS(B);\n FLASHINFER_CHECK(B.stride(2) == dstate, \"B.stride(2)=\", B.stride(2),\n \" must equal dstate=\", dstate, \" ((ngroups, dstate) must be contiguous)\");\n FLASHINFER_CHECK(nheads % ngroups == 0, \"nheads=\", nheads,\n \" must be divisible by ngroups=\", ngroups);\n\n // ── Validate C ──\n CHECK_CUDA(C);\n CHECK_DIM(4, C);\n if (is_varlen) {\n FLASHINFER_CHECK(C.size(0) == 1, \"varlen: C.size(0)=\", C.size(0), \" must be 1\");\n FLASHINFER_CHECK(C.size(1) == total_tokens, \"varlen: C.size(1)=\", C.size(1),\n \" must equal x.size(1)=\", total_tokens);\n } else {\n FLASHINFER_CHECK(C.size(0) == batch, \"C.size(0)=\", C.size(0), \" must equal batch=\", batch);\n FLASHINFER_CHECK(C.size(1) == npredicted, \"C.size(1)=\", C.size(1),\n \" must equal npredicted=\", npredicted);\n }\n FLASHINFER_CHECK(C.size(2) == ngroups, \"C.size(2)=\", C.size(2), \" must equal ngroups=\", ngroups);\n FLASHINFER_CHECK(C.size(3) == dstate, \"C.size(3)=\", C.size(3), \" must equal dstate=\", dstate);\n CHECK_LAST_DIM_CONTIGUOUS(C);\n FLASHINFER_CHECK(C.stride(2) == dstate, \"C.stride(2)=\", C.stride(2),\n \" must equal dstate=\", dstate, \" ((ngroups, dstate) must be contiguous)\");\n\n // ── Validate output ──\n CHECK_CUDA(output);\n CHECK_DIM(4, output);\n if (is_varlen) {\n FLASHINFER_CHECK(output.size(0) == 1, \"varlen: output.size(0)=\", output.size(0), \" must be 1\");\n FLASHINFER_CHECK(output.size(1) == total_tokens, \"varlen: output.size(1)=\", output.size(1),\n \" must equal x.size(1)=\", total_tokens);\n } else {\n FLASHINFER_CHECK(output.size(0) == batch, \"output.size(0)=\", output.size(0),\n \" must equal batch=\", batch);\n FLASHINFER_CHECK(output.size(1) == npredicted, \"output.size(1)=\", output.size(1),\n \" must equal npredicted=\", npredicted);\n }\n FLASHINFER_CHECK(output.size(2) == nheads, \"output.size(2)=\", output.size(2),\n \" must equal nheads=\", nheads);\n FLASHINFER_CHECK(output.size(3) == dim, \"output.size(3)=\", output.size(3),\n \" must equal dim=\", dim);\n CHECK_LAST_DIM_CONTIGUOUS(output);\n FLASHINFER_CHECK(output.stride(2) == dim, \"output.stride(2)=\", output.stride(2),\n \" must equal dim=\", dim, \" ((nheads, dim) must be contiguous)\");\n\n // ── Validate ring-buffer cache tensors ──\n // x_cache: kernel gathers one head's rows → (RING_BUFFER_LEN, dim) contig per head.\n CHECK_CUDA(x_cache);\n CHECK_DIM(4, x_cache); // (state_cache_size, nheads, RING_BUFFER_LEN, dim)\n FLASHINFER_CHECK(x_cache.size(0) == state_cache_size, \"x_cache.size(0)=\", x_cache.size(0),\n \" must equal state_cache_size=\", state_cache_size);\n FLASHINFER_CHECK(x_cache.size(1) == nheads, \"x_cache.size(1)=\", x_cache.size(1),\n \" must equal nheads=\", nheads);\n FLASHINFER_CHECK(x_cache.size(3) == dim, \"x_cache.size(3)=\", x_cache.size(3),\n \" must equal dim=\", dim);\n CHECK_LAST_DIM_CONTIGUOUS(x_cache);\n FLASHINFER_CHECK(x_cache.stride(2) == dim, \"x_cache.stride(2)=\", x_cache.stride(2),\n \" must equal dim=\", dim, \" ((RING_BUFFER_LEN, dim) must be contiguous)\");\n\n // B_cache: one group's rows → (RING_BUFFER_LEN, dstate) contig per group.\n CHECK_CUDA(B_cache);\n CHECK_DIM(4, B_cache); // (state_cache_size, ngroups, RING_BUFFER_LEN, dstate)\n FLASHINFER_CHECK(B_cache.size(0) == state_cache_size, \"B_cache.size(0)=\", B_cache.size(0),\n \" must equal state_cache_size=\", state_cache_size);\n FLASHINFER_CHECK(B_cache.size(1) == ngroups, \"B_cache.size(1)=\", B_cache.size(1),\n \" must equal ngroups=\", ngroups);\n FLASHINFER_CHECK(B_cache.size(2) == ring_buffer_len, \"B_cache.size(2)=\", B_cache.size(2),\n \" must equal ring_buffer_len=\", ring_buffer_len);\n FLASHINFER_CHECK(B_cache.size(3) == dstate, \"B_cache.size(3)=\", B_cache.size(3),\n \" must equal dstate=\", dstate);\n CHECK_LAST_DIM_CONTIGUOUS(B_cache);\n FLASHINFER_CHECK(B_cache.stride(2) == dstate, \"B_cache.stride(2)=\", B_cache.stride(2),\n \" must equal dstate=\", dstate,\n \" ((RING_BUFFER_LEN, dstate) must be contiguous)\");\n\n // dt_cache: one head's row → RING_BUFFER_LEN contig.\n CHECK_CUDA(dt_cache);\n CHECK_DIM(3, dt_cache); // (state_cache_size, nheads, RING_BUFFER_LEN)\n FLASHINFER_CHECK(dt_cache.size(0) == state_cache_size, \"dt_cache.size(0)=\", dt_cache.size(0),\n \" must equal state_cache_size=\", state_cache_size);\n FLASHINFER_CHECK(dt_cache.size(1) == nheads, \"dt_cache.size(1)=\", dt_cache.size(1),\n \" must equal nheads=\", nheads);\n FLASHINFER_CHECK(dt_cache.size(2) == ring_buffer_len, \"dt_cache.size(2)=\", dt_cache.size(2),\n \" must equal ring_buffer_len=\", ring_buffer_len);\n CHECK_LAST_DIM_CONTIGUOUS(dt_cache);\n\n CHECK_CUDA(ring_start);\n CHECK_DIM(1, ring_start);\n FLASHINFER_CHECK(ring_start.size(0) == state_cache_size,\n \"ring_start.size(0)=\", ring_start.size(0),\n \" must equal state_cache_size=\", state_cache_size);\n CHECK_CONTIGUOUS(ring_start);\n\n CHECK_CUDA(prev_num_accepted);\n CHECK_DIM(1, prev_num_accepted);\n FLASHINFER_CHECK(prev_num_accepted.size(0) == state_cache_size,\n \"prev_num_accepted.size(0)=\", prev_num_accepted.size(0),\n \" must equal state_cache_size=\", state_cache_size);\n CHECK_CONTIGUOUS(prev_num_accepted);\n\n // ── Validate optional D ──\n if (D.has_value()) {\n auto& Dv = D.value();\n CHECK_CUDA(Dv);\n CHECK_DIM(2, Dv);\n FLASHINFER_CHECK(Dv.size(0) == nheads, \"D.size(0)=\", Dv.size(0), \" must equal nheads=\", nheads);\n FLASHINFER_CHECK(Dv.size(1) == dim, \"D.size(1)=\", Dv.size(1), \" must equal dim=\", dim);\n FLASHINFER_CHECK(Dv.stride(0) == 1, \"D.stride(0) must be 1 (tie_hdim), got \", Dv.stride(0));\n FLASHINFER_CHECK(Dv.stride(1) == 0, \"D.stride(1) must be 0 (tie_hdim), got \", Dv.stride(1));\n }\n\n // ── Validate optional dt_bias ──\n if (dt_bias.has_value()) {\n auto& db = dt_bias.value();\n CHECK_CUDA(db);\n CHECK_DIM(2, db);\n FLASHINFER_CHECK(db.size(0) == nheads, \"dt_bias.size(0)=\", db.size(0),\n \" must equal nheads=\", nheads);\n FLASHINFER_CHECK(db.size(1) == dim, \"dt_bias.size(1)=\", db.size(1), \" must equal dim=\", dim);\n FLASHINFER_CHECK(db.stride(0) == 1, \"dt_bias.stride(0) must be 1 (tie_hdim), got \",\n db.stride(0));\n FLASHINFER_CHECK(db.stride(1) == 0, \"dt_bias.stride(1) must be 0 (tie_hdim), got \",\n db.stride(1));\n }\n\n // ── Validate optional z: same layout/contig rules as x ──\n if (z.has_value()) {\n auto& zv = z.value();\n CHECK_CUDA(zv);\n CHECK_DIM(4, zv);\n if (is_varlen) {\n FLASHINFER_CHECK(zv.size(0) == 1, \"varlen: z.size(0)=\", zv.size(0), \" must be 1\");\n FLASHINFER_CHECK(zv.size(1) == total_tokens, \"varlen: z.size(1)=\", zv.size(1),\n \" must equal x.size(1)=\", total_tokens);\n } else {\n FLASHINFER_CHECK(zv.size(0) == batch, \"z.size(0)=\", zv.size(0), \" must equal batch=\", batch);\n FLASHINFER_CHECK(zv.size(1) == npredicted, \"z.size(1)=\", zv.size(1),\n \" must equal npredicted=\", npredicted);\n }\n FLASHINFER_CHECK(zv.size(2) == nheads, \"z.size(2)=\", zv.size(2), \" must equal nheads=\", nheads);\n FLASHINFER_CHECK(zv.size(3) == dim, \"z.size(3)=\", zv.size(3), \" must equal dim=\", dim);\n CHECK_LAST_DIM_CONTIGUOUS(zv);\n FLASHINFER_CHECK(zv.stride(2) == dim, \"z.stride(2)=\", zv.stride(2), \" must equal dim=\", dim,\n \" ((nheads, dim) must be contiguous)\");\n }\n\n // ── Validate optional state_batch_indices ──\n if (state_batch_indices.has_value()) {\n auto& sbi = state_batch_indices.value();\n CHECK_CUDA(sbi);\n CHECK_DIM(1, sbi);\n FLASHINFER_CHECK(sbi.size(0) == batch, \"state_batch_indices.size(0)=\", sbi.size(0),\n \" must equal batch=\", batch);\n CHECK_CONTIGUOUS(sbi);\n }\n\n // ── Validate optional state_scale: (state_cache_size, nheads, dim) ──\n // Inner two dims (nheads, dim) must be contiguous; only batch stride is\n // parameterized in the params struct.\n if (state_scale.has_value()) {\n auto const& ss = state_scale.value();\n CHECK_CUDA(ss);\n CHECK_DIM(3, ss);\n FLASHINFER_CHECK(ss.size(0) == state_cache_size, \"state_scale.size(0)=\", ss.size(0),\n \" must equal state_cache_size=\", state_cache_size);\n FLASHINFER_CHECK(ss.size(1) == nheads, \"state_scale.size(1)=\", ss.size(1),\n \" must equal nheads=\", nheads);\n FLASHINFER_CHECK(ss.size(2) == dim, \"state_scale.size(2)=\", ss.size(2),\n \" must equal dim=\", dim);\n FLASHINFER_CHECK(ss.stride(2) == 1, \"state_scale.stride(2) must be 1, got \", ss.stride(2));\n FLASHINFER_CHECK(ss.stride(1) == dim, \"state_scale.stride(1)=\", ss.stride(1),\n \" must equal dim=\", dim, \" ((nheads, dim) must be contiguous)\");\n }\n\n // ── Dtype consistency ──\n // input_dtype = x.dtype; all activation tensors (B, C, output, z, x_cache,\n // B_cache) and the state cache's \"input-side\" mirrors must match it.\n // weight_dtype = D.dtype = dt_bias.dtype (kernel template sees one\n // weight_t for both).\n // Cache scalar tensors have fixed dtypes hardcoded in the kernel.\n {\n auto input_dtype = x.dtype();\n FLASHINFER_CHECK(B.dtype() == input_dtype, \"B.dtype must match x.dtype\");\n FLASHINFER_CHECK(C.dtype() == input_dtype, \"C.dtype must match x.dtype\");\n FLASHINFER_CHECK(output.dtype() == input_dtype, \"output.dtype must match x.dtype\");\n FLASHINFER_CHECK(x_cache.dtype() == input_dtype, \"x_cache.dtype must match x.dtype\");\n FLASHINFER_CHECK(B_cache.dtype() == input_dtype, \"B_cache.dtype must match x.dtype\");\n if (z.has_value()) {\n FLASHINFER_CHECK(z.value().dtype() == input_dtype, \"z.dtype must match x.dtype\");\n }\n if (D.has_value() && dt_bias.has_value()) {\n FLASHINFER_CHECK(D.value().dtype() == dt_bias.value().dtype(),\n \"D.dtype must equal dt_bias.dtype (kernel uses a single weight_t)\");\n }\n // dt_cache is produced by this same kernel in f32 and consumed back in\n // f32 on the next call (replay decays are recomputed from it).\n FLASHINFER_CHECK(dt_cache.dtype().code == kDLFloat && dt_cache.dtype().bits == 32,\n \"dt_cache must be float32\");\n // Index tensors used by the kernel as int32 scalars.\n FLASHINFER_CHECK(ring_start.dtype().code == kDLInt && ring_start.dtype().bits == 32,\n \"ring_start must be int32\");\n FLASHINFER_CHECK(\n prev_num_accepted.dtype().code == kDLInt && prev_num_accepted.dtype().bits == 32,\n \"prev_num_accepted must be int32\");\n if (state_batch_indices.has_value()) {\n auto sbi_dt = state_batch_indices.value().dtype();\n FLASHINFER_CHECK(sbi_dt.code == kDLInt && (sbi_dt.bits == 32 || sbi_dt.bits == 64),\n \"state_batch_indices must be int32 or int64\");\n }\n if (state_scale.has_value()) {\n auto ss_dt = state_scale.value().dtype();\n FLASHINFER_CHECK(ss_dt.code == kDLFloat && ss_dt.bits == 32, \"state_scale must be float32\");\n }\n // Quantized state dtypes (int8, fp8_e4m3fn, ...) require a state_scale\n // tensor; non-quantized dtypes must not pass one. Mirrors the Python\n // wrapper assertion and matches the kernel's compile-time\n // `state_scale_t == void` gating.\n {\n auto sd = state.dtype();\n bool const is_int8 = (sd.code == kDLInt && sd.bits == 8);\n bool const is_fp8 = (sd.code == kDLFloat8_e4m3fn && sd.bits == 8);\n bool const is_quantized_state = is_int8 || is_fp8;\n if (is_quantized_state) {\n FLASHINFER_CHECK(state_scale.has_value(),\n \"Quantized state.dtype (int8/fp8_e4m3fn) requires a state_scale tensor \"\n \"of shape (state_cache_size, nheads, dim) and dtype float32\");\n // The 8-bit replay path uses Layout<_4, _1> (M-shard per warp) which\n // needs per-warp M = D_PER_CTA / 4 >= 16 (m16n8 atom M). This forces\n // D_PER_CTA >= 64, i.e. d_split == 1.\n FLASHINFER_CHECK(\n d_split == 1,\n \"Quantized state.dtype (int8/fp8_e4m3fn) requires d_split=1 (got d_split=\", d_split,\n \"); the M-shard-per-warp replay layout needs D_PER_CTA / 4 >= 16.\");\n } else {\n FLASHINFER_CHECK(!state_scale.has_value(),\n \"state_scale must be None for non-quantized state.dtype \"\n \"(allowed quantized dtypes: {int8, fp8_e4m3fn})\");\n }\n }\n }\n\n // ── Populate params ──\n CheckpointingSsuParams p;\n\n // ── Validate d_split (v12 §59) ──\n // Allowed for v12: {1, 2}. d_split=4 deferred to v12.x (needs warp-count\n // restructure — output MMA `_1×4` layout requires D_PER_CTA ≥ 32).\n FLASHINFER_CHECK(d_split == 1 || d_split == 2, \"d_split=\", d_split,\n \" must be one of {1, 2} (d_split=4 is deferred to v12.x)\");\n FLASHINFER_CHECK(dim % d_split == 0, \"dim=\", dim, \" must be divisible by d_split=\", d_split);\n FLASHINFER_CHECK(dim / d_split >= 32, \"d_split=\", d_split, \" gives D_PER_CTA=\", dim / d_split,\n \" < 32 (output MMA m16n8 atom floor with _1×4 warp layout)\");\n\n // ── Validate precompute_heads_per_cta (two-kernel PRECOMPUTE head-tiling, host knob) ──\n // 0 = use the launcher's co-residency heuristic; >0 overrides (must divide HEADS_PER_GROUP).\n {\n int64_t const hpg = nheads / ngroups;\n FLASHINFER_CHECK(precompute_heads_per_cta >= 0 &&\n (precompute_heads_per_cta == 0 || hpg % precompute_heads_per_cta == 0),\n \"precompute_heads_per_cta=\", precompute_heads_per_cta,\n \" must be 0 (heuristic) or a positive divisor of HEADS_PER_GROUP \"\n \"(nheads/ngroups=\",\n hpg, \")\");\n }\n\n p.batch = batch;\n p.nheads = nheads;\n p.dim = dim;\n p.dstate = dstate;\n p.ngroups = ngroups;\n p.state_cache_size = state_cache_size;\n p.npredicted = npredicted;\n p.max_window = max_window;\n p.pad_slot_id = pad_slot_id;\n p.d_split = static_cast<int32_t>(d_split);\n p.dt_softplus = dt_softplus;\n\n // Pointers\n p.state = state.data_ptr();\n p.x = const_cast<void*>(x.data_ptr());\n p.dt = const_cast<void*>(dt.data_ptr());\n p.A = const_cast<void*>(A.data_ptr());\n p.B = const_cast<void*>(B.data_ptr());\n p.C = const_cast<void*>(C.data_ptr());\n p.output = output.data_ptr();\n\n p.x_cache = x_cache.data_ptr();\n p.B_cache = B_cache.data_ptr();\n p.dt_cache = dt_cache.data_ptr();\n p.ring_start = const_cast<void*>(ring_start.data_ptr());\n p.ring_buffer_len = static_cast<int32_t>(ring_buffer_len);\n p.prev_num_accepted = const_cast<void*>(prev_num_accepted.data_ptr());\n\n if (D.has_value()) p.D = const_cast<void*>(D.value().data_ptr());\n if (z.has_value()) {\n p.z = const_cast<void*>(z.value().data_ptr());\n // Same seq-dim selection as the rest of the batch-side tensors below.\n p.z_stride_seq = z.value().stride(is_varlen ? 1 : 0);\n p.z_stride_token = z.value().stride(1);\n }\n if (dt_bias.has_value()) p.dt_bias = const_cast<void*>(dt_bias.value().data_ptr());\n if (state_batch_indices.has_value())\n p.state_batch_indices = const_cast<void*>(state_batch_indices.value().data_ptr());\n if (is_varlen) {\n p.cu_seqlens = const_cast<void*>(cu_seqlens.value().data_ptr());\n }\n if (state_scale.has_value()) {\n p.state_scale = state_scale.value().data_ptr();\n p.state_scale_stride_seq = state_scale.value().stride(0);\n }\n if (rand_seed.has_value()) {\n auto const& rs = rand_seed.value();\n CHECK_CUDA(rs);\n FLASHINFER_CHECK(rs.numel() == 1, \"rand_seed must be single-element, got numel=\", rs.numel());\n FLASHINFER_CHECK(rs.dtype().code == kDLInt && rs.dtype().bits == 64, \"rand_seed must be int64\");\n p.rand_seed = static_cast<const int64_t*>(rs.data_ptr());\n }\n\n // Two-kernel split scratch (presence of cb_scaled selects precompute+main).\n // Caller-allocated (graph-safe). The Python wrapper enforces the all-or-none\n // trio; shape/device/contiguity/dtype are validated here so a bad scratch\n // fails loudly instead of corrupting memory or faulting inside the kernel.\n // Expected layouts (see the wrapper / bench allocator): cb_scaled/cb_old are\n // input-dtype fragA-native (., ., 32, regs); cumAdt_vec is f32 (., ., T_pad).\n // fragA-native scratch: each (batch, head)'s CB is one MMA A-fragment stored\n // as [warp lane, register]. The lane axis is a full warp; the register axis\n // is the A-operand size — kCbScaledRegs for the new-token m16n8k16 CB,\n // k_old_half (= K_old/2) for the old-token m16n8k{K_old} CB.\n constexpr int64_t kWarpSize = 32;\n constexpr int64_t kCbScaledRegs = 8; // m16n8k16 A-operand regs/lane\n int64_t const t_pad = ((npredicted + 15) / 16) * 16; // cumAdt_vec: next_multiple_of<16>\n int64_t const k_old_half = (((max_window + 7) / 8) * 8) / 2; // K_old/2, K_old=next_mult<8>\n if (cb_scaled.has_value()) {\n auto const& cb = cb_scaled.value();\n CHECK_CUDA(cb);\n CHECK_DIM(4, cb);\n CHECK_CONTIGUOUS(cb);\n FLASHINFER_CHECK(cb.dtype().code == x.dtype().code && cb.dtype().bits == x.dtype().bits,\n \"cb_scaled dtype must match x (input dtype)\");\n FLASHINFER_CHECK(cb.size(0) >= batch && cb.size(1) == nheads && cb.size(2) == kWarpSize &&\n cb.size(3) == kCbScaledRegs,\n \"cb_scaled must be (>=batch, nheads, \", kWarpSize, \", \", kCbScaledRegs,\n \"), got (\", cb.size(0), \", \", cb.size(1), \", \", cb.size(2), \", \", cb.size(3),\n \")\");\n p.cb_scaled = const_cast<void*>(cb.data_ptr());\n }\n if (cumAdt_vec.has_value()) {\n auto const& cv = cumAdt_vec.value();\n CHECK_CUDA(cv);\n CHECK_DIM(3, cv);\n CHECK_CONTIGUOUS(cv);\n FLASHINFER_CHECK(cv.dtype().code == kDLFloat && cv.dtype().bits == 32,\n \"cumAdt_vec must be float32\");\n FLASHINFER_CHECK(cv.size(0) >= batch && cv.size(1) == nheads && cv.size(2) == t_pad,\n \"cumAdt_vec must be (>=batch, nheads, \", t_pad, \"), got (\", cv.size(0), \", \",\n cv.size(1), \", \", cv.size(2), \")\");\n p.cumAdt_vec = const_cast<void*>(cv.data_ptr());\n }\n if (cb_old.has_value()) {\n auto const& cbo = cb_old.value();\n CHECK_CUDA(cbo);\n CHECK_DIM(4, cbo);\n CHECK_CONTIGUOUS(cbo);\n FLASHINFER_CHECK(cbo.dtype().code == x.dtype().code && cbo.dtype().bits == x.dtype().bits,\n \"cb_old dtype must match x (input dtype)\");\n FLASHINFER_CHECK(cbo.size(0) >= batch && cbo.size(1) == nheads && cbo.size(2) == kWarpSize &&\n cbo.size(3) == k_old_half,\n \"cb_old must be (>=batch, nheads, \", kWarpSize, \", \", k_old_half, \"), got (\",\n cbo.size(0), \", \", cbo.size(1), \", \", cbo.size(2), \", \", cbo.size(3), \")\");\n p.cb_old = const_cast<void*>(cbo.data_ptr());\n }\n // Strides\n p.state_stride_seq = state.stride(0);\n\n // `*_stride_seq` is the outer iteration stride. Non-varlen iterates over\n // dim 0 (per-batch), varlen iterates over dim 1 (per-token) — sequences\n // are packed into a single batch in the (1, total_tokens, ...) layout.\n // The kernel uses one formula `seq * *_stride_seq` for both modes.\n int const seq_dim = is_varlen ? 1 : 0;\n p.x_stride_seq = x.stride(seq_dim);\n p.x_stride_token = x.stride(1);\n p.dt_stride_seq = dt.stride(seq_dim);\n p.dt_stride_token = dt.stride(1);\n p.B_stride_seq = B.stride(seq_dim);\n p.B_stride_token = B.stride(1);\n p.C_stride_seq = C.stride(seq_dim);\n p.C_stride_token = C.stride(1);\n p.out_stride_seq = output.stride(seq_dim);\n p.out_stride_token = output.stride(1);\n\n p.x_cache_stride_seq = x_cache.stride(0);\n p.x_cache_stride_head = x_cache.stride(1);\n p.x_cache_stride_pos = x_cache.stride(2);\n p.B_cache_stride_seq = B_cache.stride(0);\n p.B_cache_stride_group = B_cache.stride(1);\n p.B_cache_stride_pos = B_cache.stride(2);\n p.dt_cache_stride_seq = dt_cache.stride(0);\n p.dt_cache_stride_head = dt_cache.stride(1);\n\n // 32-bit address-fold guard. The kernel folds within-buffer inner indices (head*dim*dstate,\n // head*head_stride, group*dstate, …) into int32 before adding the int64 buffer/slot base — see\n // load_head / prefetch_state / store_state / the dt_cache scan. Buffer/slot-distance strides\n // (*_stride_seq, *_stride_dbuf) stay int64 and are unconstrained; only these inner ceilings must\n // fit int32. `nheads*dim*dstate` (the per-slot state extent) dominates every constexpr-stride\n // fold; the head-stride folds use runtime strides so are checked explicitly. Assert here so a\n // future large-tensor layout fails loudly instead of silently truncating an address.\n constexpr int64_t kInt32Max = 2147483647;\n FLASHINFER_CHECK(nheads * dim * dstate <= kInt32Max,\n \"32-bit address fold would overflow: nheads*dim*dstate=\", nheads * dim * dstate,\n \" exceeds int32 max=\", kInt32Max);\n FLASHINFER_CHECK(nheads * p.dt_cache_stride_head <= kInt32Max,\n \"32-bit address fold would overflow: nheads*dt_cache_stride_head=\",\n nheads * p.dt_cache_stride_head, \" exceeds int32 max=\", kInt32Max);\n\n // Launch\n ffi::CUDADeviceGuard device_guard(state.device().device_id);\n const cudaStream_t stream = get_stream(state.device());\n\n launchCheckpointingSsu<input_t, dt_t, weight_t, matrixA_t, state_t, stateIndex_t, state_scale_t>(\n p, static_cast<int>(precompute_heads_per_cta), stream);\n}\n\n} // namespace flashinfer::mamba::checkpointing\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## Summary\n\nAdds framework-agnostic runtime autotuning for ReplaySSM checkpointing SSU. For eligible dense decode workloads, FlashInfer profiles supported monolithic and two-kernel launches and caches the fastest tactic for reuse.\n\n## What changes\n\n- Exposes main-kernel pipeline stages and CTAs per SM as runtime launch controls, alongside the existing precompute heads-per-CTA control.\n- Adds a `CheckpointingSSURunner` that tunes the algorithm, `d_split`, main launch geometry, and precompute grouping through FlashInfer's generic autotuner.\n- Buckets the active batch dimension while profiling compact private state/ring buffers, preserving the production `dt` broadcast layout and representative replay history.\n- Uses cold-L2 and CUDA-graph profiling, and exposes a scratch allocator so inference frameworks can provide graph-stable two-kernel workspace.\n- Keeps explicit algorithm/launch overrides and unsupported configurations on the normal fallback path.\n\n## Scope\n\nGeneric autotuning is enabled only for dense calls (`cu_seqlens is None`) with the two-kernel scratch buffers present and launch controls left on automatic selection. The implementation contains no vLLM-specific policy or state.\n\n## Validation\n\n- Base-head H100 focused suite: 7 passed, covering scratch allocation, dynamic profiles, cache keys, tactic generation, `d_split`, autotune cache reuse, and monolithic/two-kernel parity.\n- Review-followup H100 checks: 3 focused tests passed, and the newly admitted non-power-of-two launch (`heads_per_group=14`, `heads_per_cta=3`) compiled and executed successfully.\n- H100 `autotune(True)` wall clock at `max_batch=1024`: **63.856 seconds** with a warm JIT module and empty autotuner cache. This used dense `T=4`, BF16 inputs, FP32 state, and Nemotron TP8 geometry (`nheads=16`, `ngroups=1`, `head_dim=64`, `d_state=128`); all 12 batch buckets were saved (3,574 distinct tactic profiles after launch deduplication).\n- Pre-commit and public API/documentation checks pass. The full repository test matrix is pending maintainer CI authorization.\n\n"},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1065,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"b255f54480b7754ea094a43575d0c2cfbd0bff18"},"date":{"kind":"string","value":"2026-09-04T01:39:10+02:00"},"pr_number":{"kind":"number","value":4545,"string":"4,545"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/4545"},"title":{"kind":"string","value":"Add ReplaySSM autotuning (#4545)"},"message":{"kind":"string","value":"Add ReplaySSM autotuning (#4545)\n\n## Summary\n\nAdds framework-agnostic runtime autotuning for ReplaySSM checkpointing\nSSU. For eligible dense decode workloads, FlashInfer profiles supported\nmonolithic and two-kernel launches and caches the fastest tactic for\nreuse.\n\n## What changes\n\n- Exposes main-kernel pipeline stages and CTAs per SM as runtime launch\ncontrols, alongside the existing precompute heads-per-CTA control.\n- Adds a `CheckpointingSSURunner` that tunes the algorithm, `d_split`,\nmain launch geometry, and precompute grouping through FlashInfer's\ngeneric autotuner.\n- Buckets the active batch dimension while profiling compact private\nstate/ring buffers, preserving the production `dt` broadcast layout and\nrepresentative replay history.\n- Uses cold-L2 and CUDA-graph profiling, and exposes a scratch allocator\nso inference frameworks can provide graph-stable two-kernel workspace.\n- Keeps explicit algorithm/launch overrides and unsupported\nconfigurations on the normal fallback path.\n\n## Scope\n\nGeneric autotuning is enabled only for dense calls (`cu_seqlens is\nNone`) with the two-kernel scratch buffers present and launch controls\nleft on automatic selection. The implementation contains no\nvLLM-specific policy or state.\n\n## Validation\n\n- Base-head H100 focused suite: 7 passed, covering scratch allocation,\ndynamic profiles, cache keys, tactic generation, `d_split`, autotune\ncache reuse, and monolithic/two-kernel parity.\n- Review-followup H100 checks: 3 focused tests passed, and the newly\nadmitted non-power-of-two launch (`heads_per_group=14`,\n`heads_per_cta=3`) compiled and executed successfully.\n- H100 `autotune(True)` wall clock at `max_batch=1024`: **63.856\nseconds** with a warm JIT module and empty autotuner cache. This used\ndense `T=4`, BF16 inputs, FP32 state, and Nemotron TP8 geometry\n(`nheads=16`, `ngroups=1`, `head_dim=64`, `d_state=128`); all 12 batch\nbuckets were saved (3,574 distinct tactic profiles after launch\ndeduplication).\n- Pre-commit and public API/documentation checks pass. The full\nrepository test matrix is pending maintainer CI authorization.\n\n---------\n\nSigned-off-by: Andrii Skliar <askliar@nvidia.com>\nCo-authored-by: Andrii Skliar <askliar@nvidia.com>\nCo-authored-by: Albert Cheng <albecheng@nvidia.com>"},"path":{"kind":"string","value":"csrc/checkpointing_ssu_jit_binding.cu"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * Copyright (c) 2025 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include \"tvm_ffi_utils.h\"\n\nusing tvm::ffi::Optional;\n\nnamespace flashinfer::mamba::checkpointing {\n\nvoid checkpointing_ssu(\n TensorView state, // (cache, nheads, dim, dstate)\n TensorView x, // 4D (batch, T, nheads, dim) or 4D (1, total_tokens, nheads, dim) under varlen\n TensorView\n dt, // (batch, T, nheads, dim) tie_hdim / (1, total_tokens, nheads, dim) under varlen\n TensorView A, // (nheads, dim, dstate) tie_hdim\n TensorView B, // (batch, T, ngroups, dstate) / (1, total_tokens, ngroups, dstate) under varlen\n TensorView C, // same as B\n TensorView output, // same layout as x\n // Cache tensors\n TensorView x_cache, // (cache, nheads, RING_BUFFER_LEN, dim)\n TensorView B_cache, // (cache, ngroups, RING_BUFFER_LEN, dstate)\n TensorView dt_cache, // (cache, nheads, RING_BUFFER_LEN) f32\n TensorView ring_start, // (cache,) int32\n TensorView prev_num_accepted, // (cache,) int32\n // Optional tensors\n Optional<TensorView> D, // (nheads, dim)\n Optional<TensorView> z, // same layout as x\n Optional<TensorView> dt_bias, // (nheads, dim) tie_hdim\n bool dt_softplus,\n Optional<TensorView> state_batch_indices, // (batch,) int32\n int64_t pad_slot_id,\n Optional<TensorView> state_scale, // (cache, nheads, dim) f32\n Optional<TensorView> rand_seed, // single int64\n int64_t d_split, // v12 §59: per-head DIM split factor (1, 2, or 4)\n Optional<TensorView> cu_seqlens, // (batch+1,) int32 — varlen mode\n Optional<TensorView> cb_scaled, // two-kernel scratch: bf16 (batch, nheads, 32, 8)\n Optional<TensorView> cumAdt_vec, // two-kernel scratch: f32 (batch, nheads, T_pad)\n Optional<TensorView> cb_old, // two-kernel scratch: bf16 (batch, nheads, 32, K_old/2)\n int64_t precompute_heads_per_cta); // two-kernel PRECOMPUTE: heads per CTA (0 = heuristic)\n\n} // namespace flashinfer::mamba::checkpointing\n\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(checkpointing_ssu,\n flashinfer::mamba::checkpointing::checkpointing_ssu);\n"},"after_code":{"kind":"string","value":"/*\n * Copyright (c) 2025 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include \"tvm_ffi_utils.h\"\n\nusing tvm::ffi::Optional;\n\nnamespace flashinfer::mamba::checkpointing {\n\nvoid checkpointing_ssu(\n TensorView state, // (cache, nheads, dim, dstate)\n TensorView x, // 4D (batch, T, nheads, dim) or 4D (1, total_tokens, nheads, dim) under varlen\n TensorView\n dt, // (batch, T, nheads, dim) tie_hdim / (1, total_tokens, nheads, dim) under varlen\n TensorView A, // (nheads, dim, dstate) tie_hdim\n TensorView B, // (batch, T, ngroups, dstate) / (1, total_tokens, ngroups, dstate) under varlen\n TensorView C, // same as B\n TensorView output, // same layout as x\n // Cache tensors\n TensorView x_cache, // (cache, nheads, RING_BUFFER_LEN, dim)\n TensorView B_cache, // (cache, ngroups, RING_BUFFER_LEN, dstate)\n TensorView dt_cache, // (cache, nheads, RING_BUFFER_LEN) f32\n TensorView ring_start, // (cache,) int32\n TensorView prev_num_accepted, // (cache,) int32\n // Optional tensors\n Optional<TensorView> D, // (nheads, dim)\n Optional<TensorView> z, // same layout as x\n Optional<TensorView> dt_bias, // (nheads, dim) tie_hdim\n bool dt_softplus,\n Optional<TensorView> state_batch_indices, // (batch,) int32\n int64_t pad_slot_id,\n Optional<TensorView> state_scale, // (cache, nheads, dim) f32\n Optional<TensorView> rand_seed, // single int64\n int64_t d_split, // v12 §59: per-head DIM split factor (1, 2, or 4)\n Optional<TensorView> cu_seqlens, // (batch+1,) int32 — varlen mode\n Optional<TensorView> cb_scaled, // two-kernel scratch: bf16 (batch, nheads, 32, 8)\n Optional<TensorView> cumAdt_vec, // two-kernel scratch: f32 (batch, nheads, T_pad)\n Optional<TensorView> cb_old, // two-kernel scratch: bf16 (batch, nheads, 32, K_old/2)\n int64_t precompute_heads_per_cta, // two-kernel PRECOMPUTE: heads per CTA (0 = heuristic)\n int64_t main_pipeline_stages, // two-kernel MAIN: pipeline depth (0 = heuristic)\n int64_t main_ctas_per_sm); // two-kernel MAIN: grid cap (0 = heuristic)\n\n} // namespace flashinfer::mamba::checkpointing\n\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(checkpointing_ssu,\n flashinfer::mamba::checkpointing::checkpointing_ssu);\n"},"diff":{"kind":"string","value":"--- csrc/checkpointing_ssu_jit_binding.cu\n+++ csrc/checkpointing_ssu_jit_binding.cu\n@@ -41,14 +41,16 @@\n bool dt_softplus,\n Optional<TensorView> state_batch_indices, // (batch,) int32\n int64_t pad_slot_id,\n- Optional<TensorView> state_scale, // (cache, nheads, dim) f32\n- Optional<TensorView> rand_seed, // single int64\n- int64_t d_split, // v12 §59: per-head DIM split factor (1, 2, or 4)\n- Optional<TensorView> cu_seqlens, // (batch+1,) int32 — varlen mode\n- Optional<TensorView> cb_scaled, // two-kernel scratch: bf16 (batch, nheads, 32, 8)\n- Optional<TensorView> cumAdt_vec, // two-kernel scratch: f32 (batch, nheads, T_pad)\n- Optional<TensorView> cb_old, // two-kernel scratch: bf16 (batch, nheads, 32, K_old/2)\n- int64_t precompute_heads_per_cta); // two-kernel PRECOMPUTE: heads per CTA (0 = heuristic)\n+ Optional<TensorView> state_scale, // (cache, nheads, dim) f32\n+ Optional<TensorView> rand_seed, // single int64\n+ int64_t d_split, // v12 §59: per-head DIM split factor (1, 2, or 4)\n+ Optional<TensorView> cu_seqlens, // (batch+1,) int32 — varlen mode\n+ Optional<TensorView> cb_scaled, // two-kernel scratch: bf16 (batch, nheads, 32, 8)\n+ Optional<TensorView> cumAdt_vec, // two-kernel scratch: f32 (batch, nheads, T_pad)\n+ Optional<TensorView> cb_old, // two-kernel scratch: bf16 (batch, nheads, 32, K_old/2)\n+ int64_t precompute_heads_per_cta, // two-kernel PRECOMPUTE: heads per CTA (0 = heuristic)\n+ int64_t main_pipeline_stages, // two-kernel MAIN: pipeline depth (0 = heuristic)\n+ int64_t main_ctas_per_sm); // two-kernel MAIN: grid cap (0 = heuristic)\n \n } // namespace flashinfer::mamba::checkpointing\n "},"lines_added":{"kind":"number","value":10,"string":"10"},"lines_removed":{"kind":"number","value":8,"string":"8"},"files_in_commit":{"kind":"number","value":7,"string":"7"},"models_mentioned":{"kind":"list like","value":["nemotron"],"string":"[\n \"nemotron\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["H100"],"string":"[\n \"H100\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (csrc/checkpointing_ssu_jit_binding.cu).\n\nGoal: Add ReplaySSM autotuning\nTarget hardware: H100\nTarget models: nemotron\n\nCurrent file:\n```cuda\n/*\n * Copyright (c) 2025 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include \"tvm_ffi_utils.h\"\n\nusing tvm::ffi::Optional;\n\nnamespace flashinfer::mamba::checkpointing {\n\nvoid checkpointing_ssu(\n TensorView state, // (cache, nheads, dim, dstate)\n TensorView x, // 4D (batch, T, nheads, dim) or 4D (1, total_tokens, nheads, dim) under varlen\n TensorView\n dt, // (batch, T, nheads, dim) tie_hdim / (1, total_tokens, nheads, dim) under varlen\n TensorView A, // (nheads, dim, dstate) tie_hdim\n TensorView B, // (batch, T, ngroups, dstate) / (1, total_tokens, ngroups, dstate) under varlen\n TensorView C, // same as B\n TensorView output, // same layout as x\n // Cache tensors\n TensorView x_cache, // (cache, nheads, RING_BUFFER_LEN, dim)\n TensorView B_cache, // (cache, ngroups, RING_BUFFER_LEN, dstate)\n TensorView dt_cache, // (cache, nheads, RING_BUFFER_LEN) f32\n TensorView ring_start, // (cache,) int32\n TensorView prev_num_accepted, // (cache,) int32\n // Optional tensors\n Optional<TensorView> D, // (nheads, dim)\n Optional<TensorView> z, // same layout as x\n Optional<TensorView> dt_bias, // (nheads, dim) tie_hdim\n bool dt_softplus,\n Optional<TensorView> state_batch_indices, // (batch,) int32\n int64_t pad_slot_id,\n Optional<TensorView> state_scale, // (cache, nheads, dim) f32\n Optional<TensorView> rand_seed, // single int64\n int64_t d_split, // v12 §59: per-head DIM split factor (1, 2, or 4)\n Optional<TensorView> cu_seqlens, // (batch+1,) int32 — varlen mode\n Optional<TensorView> cb_scaled, // two-kernel scratch: bf16 (batch, nheads, 32, 8)\n Optional<TensorView> cumAdt_vec, // two-kernel scratch: f32 (batch, nheads, T_pad)\n Optional<TensorView> cb_old, // two-kernel scratch: bf16 (batch, nheads, 32, K_old/2)\n int64_t precompute_heads_per_cta); // two-kernel PRECOMPUTE: heads per CTA (0 = heuristic)\n\n} // namespace flashinfer::mamba::checkpointing\n\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(checkpointing_ssu,\n flashinfer::mamba::checkpointing::checkpointing_ssu);\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## Summary\n\nAdds framework-agnostic runtime autotuning for ReplaySSM checkpointing SSU. For eligible dense decode workloads, FlashInfer profiles supported monolithic and two-kernel launches and caches the fastest tactic for reuse.\n\n## What changes\n\n- Exposes main-kernel pipeline stages and CTAs per SM as runtime launch controls, alongside the existing precompute heads-per-CTA control.\n- Adds a `CheckpointingSSURunner` that tunes the algorithm, `d_split`, main launch geometry, and precompute grouping through FlashInfer's generic autotuner.\n- Buckets the active batch dimension while profiling compact private state/ring buffers, preserving the production `dt` broadcast layout and representative replay history.\n- Uses cold-L2 and CUDA-graph profiling, and exposes a scratch allocator so inference frameworks can provide graph-stable two-kernel workspace.\n- Keeps explicit algorithm/launch overrides and unsupported configurations on the normal fallback path.\n\n## Scope\n\nGeneric autotuning is enabled only for dense calls (`cu_seqlens is None`) with the two-kernel scratch buffers present and launch controls left on automatic selection. The implementation contains no vLLM-specific policy or state.\n\n## Validation\n\n- Base-head H100 focused suite: 7 passed, covering scratch allocation, dynamic profiles, cache keys, tactic generation, `d_split`, autotune cache reuse, and monolithic/two-kernel parity.\n- Review-followup H100 checks: 3 focused tests passed, and the newly admitted non-power-of-two launch (`heads_per_group=14`, `heads_per_cta=3`) compiled and executed successfully.\n- H100 `autotune(True)` wall clock at `max_batch=1024`: **63.856 seconds** with a warm JIT module and empty autotuner cache. This used dense `T=4`, BF16 inputs, FP32 state, and Nemotron TP8 geometry (`nheads=16`, `ngroups=1`, `head_dim=64`, `d_state=128`); all 12 batch buckets were saved (3,574 distinct tactic profiles after launch deduplication).\n- Pre-commit and public API/documentation checks pass. The full repository test matrix is pending maintainer CI authorization.\n\n"},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1066,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"b255f54480b7754ea094a43575d0c2cfbd0bff18"},"date":{"kind":"string","value":"2026-09-04T01:39:10+02:00"},"pr_number":{"kind":"number","value":4545,"string":"4,545"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/4545"},"title":{"kind":"string","value":"Add ReplaySSM autotuning (#4545)"},"message":{"kind":"string","value":"Add ReplaySSM autotuning (#4545)\n\n## Summary\n\nAdds framework-agnostic runtime autotuning for ReplaySSM checkpointing\nSSU. For eligible dense decode workloads, FlashInfer profiles supported\nmonolithic and two-kernel launches and caches the fastest tactic for\nreuse.\n\n## What changes\n\n- Exposes main-kernel pipeline stages and CTAs per SM as runtime launch\ncontrols, alongside the existing precompute heads-per-CTA control.\n- Adds a `CheckpointingSSURunner` that tunes the algorithm, `d_split`,\nmain launch geometry, and precompute grouping through FlashInfer's\ngeneric autotuner.\n- Buckets the active batch dimension while profiling compact private\nstate/ring buffers, preserving the production `dt` broadcast layout and\nrepresentative replay history.\n- Uses cold-L2 and CUDA-graph profiling, and exposes a scratch allocator\nso inference frameworks can provide graph-stable two-kernel workspace.\n- Keeps explicit algorithm/launch overrides and unsupported\nconfigurations on the normal fallback path.\n\n## Scope\n\nGeneric autotuning is enabled only for dense calls (`cu_seqlens is\nNone`) with the two-kernel scratch buffers present and launch controls\nleft on automatic selection. The implementation contains no\nvLLM-specific policy or state.\n\n## Validation\n\n- Base-head H100 focused suite: 7 passed, covering scratch allocation,\ndynamic profiles, cache keys, tactic generation, `d_split`, autotune\ncache reuse, and monolithic/two-kernel parity.\n- Review-followup H100 checks: 3 focused tests passed, and the newly\nadmitted non-power-of-two launch (`heads_per_group=14`,\n`heads_per_cta=3`) compiled and executed successfully.\n- H100 `autotune(True)` wall clock at `max_batch=1024`: **63.856\nseconds** with a warm JIT module and empty autotuner cache. This used\ndense `T=4`, BF16 inputs, FP32 state, and Nemotron TP8 geometry\n(`nheads=16`, `ngroups=1`, `head_dim=64`, `d_state=128`); all 12 batch\nbuckets were saved (3,574 distinct tactic profiles after launch\ndeduplication).\n- Pre-commit and public API/documentation checks pass. The full\nrepository test matrix is pending maintainer CI authorization.\n\n---------\n\nSigned-off-by: Andrii Skliar <askliar@nvidia.com>\nCo-authored-by: Andrii Skliar <askliar@nvidia.com>\nCo-authored-by: Albert Cheng <albecheng@nvidia.com>"},"path":{"kind":"string","value":"csrc/checkpointing_ssu_kernel_inst.cu"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"// clang-format off\n#include \"checkpointing_ssu_config.inc\"\n#include <flashinfer/mamba/checkpointing_ssu.cuh>\n#include <flashinfer/mamba/launch_checkpointing_ssu.cuh>\n// clang-format on\n\nnamespace flashinfer::mamba::checkpointing {\n\ntemplate void launchCheckpointingSsu<input_t, dt_t, weight_t, matrixA_t, state_t, stateIndex_t,\n state_scale_t>(CheckpointingSsuParams&, int, cudaStream_t);\n\n} // namespace flashinfer::mamba::checkpointing\n"},"after_code":{"kind":"string","value":"// clang-format off\n#include \"checkpointing_ssu_config.inc\"\n#include <flashinfer/mamba/checkpointing_ssu.cuh>\n#include <flashinfer/mamba/launch_checkpointing_ssu.cuh>\n// clang-format on\n\nnamespace flashinfer::mamba::checkpointing {\n\ntemplate void launchCheckpointingSsu<input_t, dt_t, weight_t, matrixA_t, state_t, stateIndex_t,\n state_scale_t>(CheckpointingSsuParams&, int, int, int,\n cudaStream_t);\n\n} // namespace flashinfer::mamba::checkpointing\n"},"diff":{"kind":"string","value":"--- csrc/checkpointing_ssu_kernel_inst.cu\n+++ csrc/checkpointing_ssu_kernel_inst.cu\n@@ -7,6 +7,7 @@\n namespace flashinfer::mamba::checkpointing {\n \n template void launchCheckpointingSsu<input_t, dt_t, weight_t, matrixA_t, state_t, stateIndex_t,\n- state_scale_t>(CheckpointingSsuParams&, int, cudaStream_t);\n+ state_scale_t>(CheckpointingSsuParams&, int, int, int,\n+ cudaStream_t);\n \n } // namespace flashinfer::mamba::checkpointing"},"lines_added":{"kind":"number","value":2,"string":"2"},"lines_removed":{"kind":"number","value":1,"string":"1"},"files_in_commit":{"kind":"number","value":7,"string":"7"},"models_mentioned":{"kind":"list like","value":["nemotron"],"string":"[\n \"nemotron\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["H100"],"string":"[\n \"H100\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (csrc/checkpointing_ssu_kernel_inst.cu).\n\nGoal: Add ReplaySSM autotuning\nTarget hardware: H100\nTarget models: nemotron\n\nCurrent file:\n```cuda\n// clang-format off\n#include \"checkpointing_ssu_config.inc\"\n#include <flashinfer/mamba/checkpointing_ssu.cuh>\n#include <flashinfer/mamba/launch_checkpointing_ssu.cuh>\n// clang-format on\n\nnamespace flashinfer::mamba::checkpointing {\n\ntemplate void launchCheckpointingSsu<input_t, dt_t, weight_t, matrixA_t, state_t, stateIndex_t,\n state_scale_t>(CheckpointingSsuParams&, int, cudaStream_t);\n\n} // namespace flashinfer::mamba::checkpointing\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## Summary\n\nAdds framework-agnostic runtime autotuning for ReplaySSM checkpointing SSU. For eligible dense decode workloads, FlashInfer profiles supported monolithic and two-kernel launches and caches the fastest tactic for reuse.\n\n## What changes\n\n- Exposes main-kernel pipeline stages and CTAs per SM as runtime launch controls, alongside the existing precompute heads-per-CTA control.\n- Adds a `CheckpointingSSURunner` that tunes the algorithm, `d_split`, main launch geometry, and precompute grouping through FlashInfer's generic autotuner.\n- Buckets the active batch dimension while profiling compact private state/ring buffers, preserving the production `dt` broadcast layout and representative replay history.\n- Uses cold-L2 and CUDA-graph profiling, and exposes a scratch allocator so inference frameworks can provide graph-stable two-kernel workspace.\n- Keeps explicit algorithm/launch overrides and unsupported configurations on the normal fallback path.\n\n## Scope\n\nGeneric autotuning is enabled only for dense calls (`cu_seqlens is None`) with the two-kernel scratch buffers present and launch controls left on automatic selection. The implementation contains no vLLM-specific policy or state.\n\n## Validation\n\n- Base-head H100 focused suite: 7 passed, covering scratch allocation, dynamic profiles, cache keys, tactic generation, `d_split`, autotune cache reuse, and monolithic/two-kernel parity.\n- Review-followup H100 checks: 3 focused tests passed, and the newly admitted non-power-of-two launch (`heads_per_group=14`, `heads_per_cta=3`) compiled and executed successfully.\n- H100 `autotune(True)` wall clock at `max_batch=1024`: **63.856 seconds** with a warm JIT module and empty autotuner cache. This used dense `T=4`, BF16 inputs, FP32 state, and Nemotron TP8 geometry (`nheads=16`, `ngroups=1`, `head_dim=64`, `d_state=128`); all 12 batch buckets were saved (3,574 distinct tactic profiles after launch deduplication).\n- Pre-commit and public API/documentation checks pass. The full repository test matrix is pending maintainer CI authorization.\n\n"},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1067,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"b255f54480b7754ea094a43575d0c2cfbd0bff18"},"date":{"kind":"string","value":"2026-09-04T01:39:10+02:00"},"pr_number":{"kind":"number","value":4545,"string":"4,545"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/4545"},"title":{"kind":"string","value":"Add ReplaySSM autotuning (#4545)"},"message":{"kind":"string","value":"Add ReplaySSM autotuning (#4545)\n\n## Summary\n\nAdds framework-agnostic runtime autotuning for ReplaySSM checkpointing\nSSU. For eligible dense decode workloads, FlashInfer profiles supported\nmonolithic and two-kernel launches and caches the fastest tactic for\nreuse.\n\n## What changes\n\n- Exposes main-kernel pipeline stages and CTAs per SM as runtime launch\ncontrols, alongside the existing precompute heads-per-CTA control.\n- Adds a `CheckpointingSSURunner` that tunes the algorithm, `d_split`,\nmain launch geometry, and precompute grouping through FlashInfer's\ngeneric autotuner.\n- Buckets the active batch dimension while profiling compact private\nstate/ring buffers, preserving the production `dt` broadcast layout and\nrepresentative replay history.\n- Uses cold-L2 and CUDA-graph profiling, and exposes a scratch allocator\nso inference frameworks can provide graph-stable two-kernel workspace.\n- Keeps explicit algorithm/launch overrides and unsupported\nconfigurations on the normal fallback path.\n\n## Scope\n\nGeneric autotuning is enabled only for dense calls (`cu_seqlens is\nNone`) with the two-kernel scratch buffers present and launch controls\nleft on automatic selection. The implementation contains no\nvLLM-specific policy or state.\n\n## Validation\n\n- Base-head H100 focused suite: 7 passed, covering scratch allocation,\ndynamic profiles, cache keys, tactic generation, `d_split`, autotune\ncache reuse, and monolithic/two-kernel parity.\n- Review-followup H100 checks: 3 focused tests passed, and the newly\nadmitted non-power-of-two launch (`heads_per_group=14`,\n`heads_per_cta=3`) compiled and executed successfully.\n- H100 `autotune(True)` wall clock at `max_batch=1024`: **63.856\nseconds** with a warm JIT module and empty autotuner cache. This used\ndense `T=4`, BF16 inputs, FP32 state, and Nemotron TP8 geometry\n(`nheads=16`, `ngroups=1`, `head_dim=64`, `d_state=128`); all 12 batch\nbuckets were saved (3,574 distinct tactic profiles after launch\ndeduplication).\n- Pre-commit and public API/documentation checks pass. The full\nrepository test matrix is pending maintainer CI authorization.\n\n---------\n\nSigned-off-by: Andrii Skliar <askliar@nvidia.com>\nCo-authored-by: Andrii Skliar <askliar@nvidia.com>\nCo-authored-by: Albert Cheng <albecheng@nvidia.com>"},"path":{"kind":"string","value":"include/flashinfer/mamba/launch_checkpointing_ssu.cuh"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * Copyright (c) 2025 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_MAMBA_LAUNCH_CHECKPOINTING_SSU_CUH_\n#define FLASHINFER_MAMBA_LAUNCH_CHECKPOINTING_SSU_CUH_\n\n// Launcher functions for the incremental SSU kernel.\n// Includes both the bf16/fp16/fp32 and 8-bit kernel headers.\n\n#include \"kernel_checkpointing_ssu.cuh\"\n#include \"kernel_checkpointing_ssu_8bit.cuh\"\n#include \"kernel_checkpointing_ssu_main.cuh\"\n#include \"kernel_checkpointing_ssu_precompute.cuh\"\n\nnamespace flashinfer::mamba::checkpointing {\n\n// Map a runtime heads-per-CTA `hc` (a value on the HEADS_PER_GROUP>>k chain the\n// tiling heuristic produces) to a compile-time template arg. Recurses\n// HC = HC_MAX, HC_MAX/2, ... 1 and calls fn<HC>() for the largest HC <= hc, so\n// the per-head smem footprint and grid.z are both compile-time constants.\ntemplate <int HC_MAX, typename Fn>\nvoid dispatch_heads_per_cta(int hc, Fn&& fn) {\n if constexpr (HC_MAX <= 1) {\n fn.template operator()<1>();\n } else if (hc >= HC_MAX) {\n fn.template operator()<HC_MAX>();\n } else {\n dispatch_heads_per_cta<HC_MAX / 2>(hc, fn);\n }\n}\n\n// Map a runtime precompute warp count to a compile-time template arg.\n// Valid values: 4, 8, 16 (minimum 4 — the CB matmul uses 4 warps).\ntemplate <typename Fn>\nvoid dispatch_precompute_num_warps(int nw, Fn&& fn) {\n if (nw >= 16) {\n fn.template operator()<16>();\n } else if (nw >= 8) {\n fn.template operator()<8>();\n } else {\n fn.template operator()<4>();\n }\n}\n\n// ── Dispatcher ─────────────────────────────────────────────────────────────\n// `D_SPLIT` splits each head's DIM axis across `D_SPLIT` CTAs.\n// `VARLEN` selects the packed-token gmem layout (cu_seqlens-driven).\n// `launchCheckpointingSsuImpl` is the per-(D_SPLIT, VARLEN) specialization;\n// `launchCheckpointingSsu` (below) is the runtime dispatcher.\ntemplate <typename input_t, typename dt_t, typename weight_t, typename matrixA_t, typename state_t,\n typename stateIndex_t, typename state_scale_t, int D_SPLIT, bool VARLEN>\nvoid launchCheckpointingSsuImpl(CheckpointingSsuParams& params, int precompute_heads_per_cta,\n cudaStream_t stream) {\n constexpr int NUM_WARPS = 4;\n\n FLASHINFER_CHECK(params.nheads % params.ngroups == 0, \"nheads (\", params.nheads,\n \") must be divisible by ngroups (\", params.ngroups, \")\");\n\n // cp.async.ca with .L2::128B requires 16B-aligned pointers (128-bit / sizeof element).\n // The .L2::128B hint further requires the base address to be 128B-aligned for full\n // cache line utilization, but the hardware only faults on < 16B alignment.\n // All cp.async-loaded operands need 16B alignment; output is also vectorized\n // (Pair<input_t> stores partitioned by m16n8k16 partition_C — base must be at\n // least 16B-aligned for the stride math to keep per-thread stores aligned).\n FLASHINFER_CHECK_ALIGNMENT(params.B, 16);\n FLASHINFER_CHECK_ALIGNMENT(params.C, 16);\n FLASHINFER_CHECK_ALIGNMENT(params.x, 16);\n FLASHINFER_CHECK_ALIGNMENT(params.state, 16);\n FLASHINFER_CHECK_ALIGNMENT(params.x_cache, 16);\n FLASHINFER_CHECK_ALIGNMENT(params.B_cache, 16);\n FLASHINFER_CHECK_ALIGNMENT(params.output, 16);\n if (params.z != nullptr) {\n FLASHINFER_CHECK_ALIGNMENT(params.z, 16);\n }\n\n // Per-CTA D = DIM / D_SPLIT. Smem footprint shrinks for D-owned\n // buffers (state, x, z, old_x); non-D buffers (B, C, old_B, scalars) unchanged.\n constexpr int D_PER_CTA = DIM / D_SPLIT;\n\n // HEADS_PER_GROUP is JIT-stamped via the customize_config jinja, so only\n // one (nheads / ngroups) specialization gets baked into this .so. The\n // wrapper has already validated `nheads / ngroups == HEADS_PER_GROUP`\n // before reaching us — the kernel cross-checks with an assert below.\n FLASHINFER_CHECK(params.nheads / params.ngroups == HEADS_PER_GROUP,\n \"nheads/ngroups (=\", params.nheads / params.ngroups,\n \") must match JIT HEADS_PER_GROUP=\", HEADS_PER_GROUP);\n // NGROUPS is JIT-stamped too; the ratio check above doesn't pin the absolute\n // group count, and the kernel's unflatten bakes NHEADS = NGROUPS * HEADS_PER_GROUP.\n FLASHINFER_CHECK(params.ngroups == NGROUPS, \"ngroups (=\", params.ngroups,\n \") must match JIT NGROUPS=\", NGROUPS);\n // PDL launch attribute (EXTERNAL chain: a programmatic upstream kernel — e.g.\n // conv1d — overlapping THIS kernel). ENABLE_PDL is JIT-stamped (see\n // checkpointing_ssu_customize_config.jinja); the kernel body gates its\n // conv1d-facing PDL PTX on the same constexpr via `if constexpr (ENABLE_PDL)`.\n // This is the ONLY PDL knob a caller controls — \"does my upstream conv1d\n // overlap the SSU?\". The two-kernel split's INTERNAL precompute→main PDL is\n // NOT gated by this (see below): it is intrinsic to the split, always on.\n // When ENABLE_PDL is false the attribute is 0 — cudaLaunchKernelEx is used\n // either way per FlashInfer convention (see norm.cuh:135).\n cudaLaunchAttribute attrs[1];\n attrs[0].id = cudaLaunchAttributeProgrammaticStreamSerialization;\n attrs[0].val.programmaticStreamSerializationAllowed = ENABLE_PDL ? 1 : 0;\n\n // ── Two-kernel split: precompute → main, when the caller provides scratch ──\n // (cb_scaled/cb_old/cumAdt_vec). Requires 2-byte input (bf16/fp16\n // activations); state may be 2-byte (LDSM path) or 4-byte f32 (LDS.64 +\n // in-register narrow — see make_a_s2r). 8-bit state has no two-kernel\n // split (the monolithic checkpointing_ssu_kernel_8bit handles it).\n //\n // INTERNAL PDL (precompute → main) is ALWAYS on — it is the split's mechanism,\n // not a user knob: the main co-launches with the precompute (its attr below is\n // hard-wired to 1) and runs its precompute-independent state replay while the\n // precompute computes CB / waits on conv1d; the main's own gdc_wait then blocks\n // for the precompute to finish before it reads cb_scaled. This is what lets\n // the replay overlap conv1d on the cliff, so it must not be disable-able.\n //\n // EXTERNAL PDL (conv1d → precompute) rides on ENABLE_PDL (`attrs`): the\n // precompute co-launches with a programmatic conv1d and gdc_waits for B/C.\n // The precompute fires cudaTriggerProgrammaticLaunchCompletion() at its TOP\n // (unconditional) so the main becomes eligible to launch immediately.\n if (params.cb_scaled != nullptr) {\n if constexpr ((sizeof(state_t) == 2 || sizeof(state_t) == 4) && sizeof(input_t) == 2) {\n // Precompute: grid (batch, ngroups, ceil(HEADS_PER_GROUP/HEADS_PER_CTA)).\n // Heads are tiled across grid.z to fill the GPU at small batch (heuristic\n // below). HEADS_PER_CTA is picked at runtime, dispatched to a template arg;\n // DT_SOFTPLUS is JIT-folded on the runtime flag.\n auto launch_precompute =\n [&]<int HEADS_PER_CTA, int PRECOMPUTE_NUM_WARPS, bool DT_SOFTPLUS>() {\n auto pfunc =\n checkpointing_ssu_precompute_kernel<input_t, dt_t, weight_t, matrixA_t, state_t,\n stateIndex_t, NPREDICTED, MAX_WINDOW, DIM,\n DSTATE, HEADS_PER_GROUP, HEADS_PER_CTA,\n PRECOMPUTE_NUM_WARPS, DT_SOFTPLUS, VARLEN>;\n constexpr size_t psmem =\n sizeof(CheckpointingSsuPrecomputeStorage<input_t, NPREDICTED, MAX_WINDOW, DSTATE,\n PRECOMPUTE_NUM_WARPS, HEADS_PER_CTA>);\n if constexpr (psmem > 0) {\n FLASHINFER_CUDA_CHECK(\n cudaFuncSetAttribute(pfunc, cudaFuncAttributeMaxDynamicSharedMemorySize, psmem));\n }\n constexpr int head_tiles = (HEADS_PER_GROUP + HEADS_PER_CTA - 1) / HEADS_PER_CTA;\n cudaLaunchConfig_t pcfg;\n pcfg.gridDim = dim3(params.batch, params.ngroups, head_tiles);\n pcfg.blockDim = dim3(warpSize, PRECOMPUTE_NUM_WARPS);\n pcfg.dynamicSmemBytes = psmem;\n pcfg.stream = stream;\n pcfg.attrs = attrs;\n pcfg.numAttrs = 1;\n FLASHINFER_CUDA_CHECK(cudaLaunchKernelEx(&pcfg, pfunc, params));\n };\n static int const num_sms = [] {\n int dev = 0, n = 0;\n FLASHINFER_CUDA_CHECK(cudaGetDevice(&dev));\n FLASHINFER_CUDA_CHECK(cudaDeviceGetAttribute(&n, cudaDevAttrMultiProcessorCount, dev));\n return n;\n }();\n\n // ── Head-tiling default: heads/CTA == warps/CTA (1 head/warp), coupled in\n // launch_precompute (PRECOMPUTE_NUM_WARPS = max(hc, 4)). hc=8 (→ 8 warps) measured as\n // the robust optimum on B200, across BOTH the cliff and large batch:\n // • small batch: the precompute is latency-bound + under-occupied — 8 warps double\n // the resident warps (occ 6%→12%, matching triton's _dynamic_precompute) to hide\n // the load latency (no-issue 93%→88%, b=16 11.3µs→10.7µs).\n // • large batch: fewer head-tiles per group HALVE the redundant per-group C·B matmul\n // (b=1024: hc=8 136µs vs the old hc=2 143µs — now beats triton-replay-pm).\n // At tiny grids the precompute is so under-occupied that spreading into MORE, smaller\n // CTAs (hc=4 → 4 tiles vs hc=8 → 2) lights up more SMs and edges ahead (+0.1–0.2µs),\n // so back off there. The boundary — measured as b=8 at ng=1/HPG=16 on the 148-SM B200 —\n // is the hc=8 grid (batch·ngroups·HPG/8 CTAs) covering ≥ ~1/10 of the SMs; expressing it\n // that way (instead of raw `batch >= 8`) scales it with ngroups (TP) and GPU size.\n // hc=16 regressed small batch (too few CTAs, 512 thr) without helping large — not worth\n // a 3rd tier. Tunable via precompute_heads_per_cta / the env below;\n // dispatch_heads_per_cta snaps to the HEADS_PER_GROUP>>k chain (clamps to HPG).\n int64_t const hc8_grid = static_cast<int64_t>(params.batch) * params.ngroups *\n (HEADS_PER_GROUP >= 8 ? HEADS_PER_GROUP / 8 : 1);\n int const hc_ideal = (hc8_grid * 10 >= num_sms) ? 8 : 4;\n int hc = HEADS_PER_GROUP;\n while (hc > 1 && hc > hc_ideal) hc >>= 1;\n // Overrides (both snap to the HEADS_PER_GROUP>>k chain in dispatch_heads_per_cta):\n // • precompute_heads_per_cta — the exposed HOST handle (Python-tunable; 0 = heuristic);\n // • FLASHINFER_SSU_HEADS_PER_CTA — an ad-hoc env for quick sweeps.\n // Precedence: explicit handle > env > heuristic. Envs are read PER LAUNCH\n // (getenv is ~ns against a launch; not static, so sweeps/tests see each change).\n int const hc_env = [] {\n char const* e = std::getenv(\"FLASHINFER_SSU_HEADS_PER_CTA\");\n return e ? std::atoi(e) : 0;\n }();\n if (hc_env > 0) hc = hc_env;\n if (precompute_heads_per_cta > 0) hc = precompute_heads_per_cta;\n int const pnw_env = [] {\n char const* e = std::getenv(\"FLASHINFER_SSU_PRECOMPUTE_NUM_WARPS\");\n return e ? std::atoi(e) : 0;\n }();\n dispatch_heads_per_cta<HEADS_PER_GROUP>(hc, [&]<int HEADS_PER_CTA>() {\n int pnw = (HEADS_PER_CTA > 4) ? HEADS_PER_CTA : 4; // default: 1 head/warp, min 4\n if (pnw_env > 0) pnw = pnw_env;\n dispatch_precompute_num_warps(pnw, [&]<int PNW>() {\n if (params.dt_softplus) {\n launch_precompute.template operator()<HEADS_PER_CTA, PNW, true>();\n } else {\n launch_precompute.template operator()<HEADS_PER_CTA, PNW, false>();\n }\n });\n });\n\n // ── Persistent main: 1D grid-stride loop over single-head work-units ──\n // One work-unit = one head; the grid-stride loop is the head-tiling (no host knob).\n // Launch min(cta_per_sm·NUM_SMS, total_work) CTAs; each grid-strides over work-units.\n // Fewer CTAs leave SM room to co-reside with conv1d (closing the no-write gap to\n // triton-replay-pm), and consecutive work-units (head_tile-fastest, see kernel) keep\n // per-group C/old_B L2-hot. Default cta_per_sm huge ⇒ grid == total_work ⇒ one\n // work-unit/CTA ⇒ bit-identical to the old (D_SPLIT, batch, nheads) launch.\n //\n // MAIN_NUM_WARPS=4: the main is NUM_WARPS-generic but feed-bound (long/short scoreboard),\n // not warp-hideable, so 8 warps buys nothing and costs finer MMA tiling + publish barriers.\n constexpr int MAIN_NUM_WARPS = 4;\n\n int const main_total_work =\n D_SPLIT * static_cast<int>(params.batch) * static_cast<int>(params.nheads);\n\n // ── Launch-regime defaults: {NUM_STAGES, cta_per_sm} per (state width, total work) ──\n // THE tuning table — the defaults here must stand on their own; the\n // FLASHINFER_SSU_MAIN_{PIPELINE_STAGES,CTA_PER_SM} envs are optional overrides for\n // experiments, never required. Tuned on the production-shaped workload (mixed PNATs +\n // conv1d/PDL, bench_ssu_checkpoint_mixed.py):\n // • 2-byte state → {1, 16} at every work level. Occupancy regime: ~29 KB/block → 6\n // blocks/SM at the derived reg cap; depth 2 loses b=1024 bf16 (94.0 vs 79.6 µs\n // no-write). cps=16 slightly oversubscribed beats exactly-resident (133.6 vs 139.6);\n // below-occupancy grids are catastrophic.\n // • 4-byte state → {1, 16} at every work level. In mixed batches stg1/cps16 beats\n // stg2/cps4 at EVERY batch (b=32: 14.05 vs 17.22; b=1024: 154.9 vs 163.3 µs e2e):\n // the cps=4 grid's long-lived CTAs eat a binomial write-count straggler tail\n // (~9.5 µs, slot-order experiment) and can't co-reside with conv1d. The ONE regime\n // preferring {2, 4} is UNIFORM-PNAT kernel isolation at work ≳ 8·SMs, where depth 2\n // covers the doubled state prefetch (122.8 vs 150.5 µs b=1024 no-write) — that mix\n // is undetectable at launch (per-slot PNATs live on device) and isn't production-\n // shaped, so it is NOT a default; the envs can pin it for such experiments.\n // `total_work` parameterizes the table for future batch-dependent entries (none today:\n // small batches self-cap the grid at total_work, so cps needs no small-batch entry).\n struct MainRegime {\n int stages, cta_per_sm;\n };\n auto const regime = [](int /*total_work*/) -> MainRegime { return {1, 16}; }(main_total_work);\n\n // Envs are read PER LAUNCH (getenv is ~ns against a launch): tests monkeypatch them\n // per-case, and a static latch would pin the first-seen value for the whole process.\n int const main_cta_per_sm = [&] {\n char const* e = std::getenv(\"FLASHINFER_SSU_MAIN_CTA_PER_SM\");\n int const v = e ? std::atoi(e) : 0; // unset/<=0 → regime default\n return v > 0 ? v : regime.cta_per_sm;\n }();\n int64_t const main_grid_ll = static_cast<int64_t>(main_cta_per_sm) * num_sms;\n int const main_grid =\n static_cast<int>(main_grid_ll < main_total_work ? main_grid_ll : main_total_work);\n\n int const main_stages = [&] {\n char const* e = std::getenv(\"FLASHINFER_SSU_MAIN_PIPELINE_STAGES\");\n int const v = e ? std::atoi(e) : 0; // unset → regime default\n FLASHINFER_CHECK(v == 0 || v == 1 || v == 2,\n \"FLASHINFER_SSU_MAIN_PIPELINE_STAGES must be 1 or 2, got \", v);\n return v > 0 ? v : regime.stages;\n }();\n\n // INTERNAL PDL: the main ALWAYS co-launches with the precompute (attr hard-wired to 1,\n // independent of ENABLE_PDL). The one-shot gdc_wait on a CTA's first work-unit blocks for\n // the precompute before reading cb_scaled / cumAdt_vec.\n cudaLaunchAttribute main_attrs[1];\n main_attrs[0].id = cudaLaunchAttributeProgrammaticStreamSerialization;\n main_attrs[0].val.programmaticStreamSerializationAllowed = 1;\n cudaLaunchConfig_t mcfg;\n mcfg.gridDim = dim3(main_grid);\n mcfg.blockDim = dim3(warpSize, MAIN_NUM_WARPS);\n mcfg.stream = stream;\n mcfg.attrs = main_attrs;\n mcfg.numAttrs = 1;\n\n // NGROUPS is the jinja-stamped compile-time group count → the kernel's unflatten divides only\n // by compile-time constants (no runtime div/mod).\n auto launch_main = [&](auto stages_tag) {\n constexpr int MAIN_STAGES = decltype(stages_tag)::value;\n auto mfunc =\n checkpointing_ssu_main_kernel<input_t, dt_t, weight_t, matrixA_t, state_t, stateIndex_t,\n state_scale_t, NPREDICTED, MAX_WINDOW, DIM, DSTATE,\n HEADS_PER_GROUP, PHILOX_ROUNDS, MAIN_NUM_WARPS, D_SPLIT,\n VARLEN, NGROUPS, MAIN_STAGES>;\n constexpr size_t msmem =\n sizeof(CheckpointingSsuMainStorage<input_t, state_t, NPREDICTED, MAX_WINDOW, D_PER_CTA,\n DSTATE, MAIN_STAGES, VARLEN>);\n if constexpr (msmem > 0) {\n FLASHINFER_CUDA_CHECK(\n cudaFuncSetAttribute(mfunc, cudaFuncAttributeMaxDynamicSharedMemorySize, msmem));\n }\n mcfg.dynamicSmemBytes = msmem;\n FLASHINFER_CUDA_CHECK(cudaLaunchKernelEx(&mcfg, mfunc, params));\n };\n if (main_stages == 2) {\n launch_main(std::integral_constant<int, 2>{});\n } else {\n launch_main(std::integral_constant<int, 1>{});\n }\n return;\n } else {\n FLASHINFER_CHECK(false,\n \"two-kernel SSU split (cb_scaled provided) requires 2-byte input \"\n \"(bf16/fp16) and 2- or 4-byte state (bf16/fp16/fp32); got \"\n \"sizeof(input_t)=\",\n sizeof(input_t), \", sizeof(state_t)=\", sizeof(state_t));\n }\n }\n\n auto launch_kernel = [&]() {\n if constexpr (sizeof(state_t) == 1) {\n // int8 chain rewrite — uses checkpointing_ssu_kernel_8bit +\n // CheckpointingSsuStorage8bit. Only D_SPLIT == 1 is valid (the wrapper\n // asserts this); D_SPLIT == 2 still gets template-instantiated by the\n // public dispatcher's switch but is unreachable at runtime — gate the\n // body with `if constexpr (D_SPLIT == 1)` so that path doesn't launch.\n if constexpr (D_SPLIT == 1) {\n auto func =\n checkpointing_ssu_kernel_8bit<input_t, dt_t, weight_t, matrixA_t, state_t, stateIndex_t,\n state_scale_t, NPREDICTED, MAX_WINDOW, DIM, DSTATE,\n HEADS_PER_GROUP, PHILOX_ROUNDS, NUM_WARPS, VARLEN>;\n constexpr size_t smem_size =\n sizeof(CheckpointingSsuStorage8bit<input_t, state_t, NPREDICTED, MAX_WINDOW, D_PER_CTA,\n DSTATE>);\n\n if constexpr (smem_size > 0) {\n FLASHINFER_CUDA_CHECK(\n cudaFuncSetAttribute(func, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n }\n\n cudaLaunchConfig_t config;\n config.gridDim = dim3(D_SPLIT, params.batch, params.nheads);\n config.blockDim = dim3(warpSize, NUM_WARPS);\n config.dynamicSmemBytes = smem_size;\n config.stream = stream;\n config.attrs = attrs;\n config.numAttrs = 1;\n FLASHINFER_CUDA_CHECK(cudaLaunchKernelEx(&config, func, params));\n } else {\n FLASHINFER_CHECK(false,\n \"checkpointing_ssu_kernel_8bit: unsupported D_SPLIT != 1 for 8-bit \"\n \"state_t (got D_SPLIT=\",\n D_SPLIT, \")\");\n }\n } else {\n // Generic kernel: bf16 / fp16 / fp32 state, supports D_SPLIT ∈ {1, 2}.\n auto func =\n checkpointing_ssu_kernel<input_t, dt_t, weight_t, matrixA_t, state_t, stateIndex_t,\n state_scale_t, NPREDICTED, MAX_WINDOW, DIM, DSTATE,\n HEADS_PER_GROUP, PHILOX_ROUNDS, NUM_WARPS, D_SPLIT, VARLEN>;\n\n constexpr size_t smem_size = sizeof(\n CheckpointingSsuStorage<input_t, state_t, NPREDICTED, MAX_WINDOW, D_PER_CTA, DSTATE>);\n\n if constexpr (smem_size > 0) {\n FLASHINFER_CUDA_CHECK(\n cudaFuncSetAttribute(func, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n }\n\n // Grid is (D_SPLIT, batch, nheads). D-tile is the fastest axis so the\n // `D_SPLIT` CTAs of the same head land on adjacent SMs and share L2\n // lines for the redundantly-loaded inputs (C, B, dt, ...).\n cudaLaunchConfig_t config;\n config.gridDim = dim3(D_SPLIT, params.batch, params.nheads);\n config.blockDim = dim3(warpSize, NUM_WARPS);\n config.dynamicSmemBytes = smem_size;\n config.stream = stream;\n config.attrs = attrs;\n config.numAttrs = 1;\n FLASHINFER_CUDA_CHECK(cudaLaunchKernelEx(&config, func, params));\n }\n };\n\n launch_kernel();\n}\n\n// Public dispatcher: routes on `params.d_split` ({1, 2}) and varlen\n// (`params.cu_seqlens != nullptr` → VARLEN=true). Each (D_SPLIT, VARLEN)\n// pair gets its own template specialization — the JIT URI distinguishes them\n// only via `d_split` today, so the same compiled `.so` will hold all four\n// specializations after this commit.\ntemplate <typename input_t, typename dt_t, typename weight_t, typename matrixA_t, typename state_t,\n typename stateIndex_t, typename state_scale_t>\nvoid launchCheckpointingSsu(CheckpointingSsuParams& params, int precompute_heads_per_cta,\n cudaStream_t stream) {\n bool const is_varlen = (params.cu_seqlens != nullptr);\n auto launch = [&]<int D_SPLIT, bool VARLEN>() {\n launchCheckpointingSsuImpl<input_t, dt_t, weight_t, matrixA_t, state_t, stateIndex_t,\n state_scale_t, D_SPLIT, VARLEN>(params, precompute_heads_per_cta,\n stream);\n };\n auto launch_d_split = [&]<int D_SPLIT>() {\n if (is_varlen) {\n launch.template operator()<D_SPLIT, true>();\n } else {\n launch.template operator()<D_SPLIT, false>();\n }\n };\n switch (params.d_split) {\n case 1:\n launch_d_split.template operator()<1>();\n break;\n case 2:\n launch_d_split.template operator()<2>();\n break;\n default:\n FLASHINFER_CHECK(false, \"Unsupported d_split: \", params.d_split,\n \". Allowed values: {1, 2}. d_split=4 needs \"\n \"warp-count restructure.\");\n }\n}\n\n} // namespace flashinfer::mamba::checkpointing\n\n#endif // FLASHINFER_MAMBA_LAUNCH_CHECKPOINTING_SSU_CUH_\n"},"after_code":{"kind":"string","value":"/*\n * Copyright (c) 2025 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_MAMBA_LAUNCH_CHECKPOINTING_SSU_CUH_\n#define FLASHINFER_MAMBA_LAUNCH_CHECKPOINTING_SSU_CUH_\n\n// Launcher functions for the incremental SSU kernel.\n// Includes both the bf16/fp16/fp32 and 8-bit kernel headers.\n\n#include \"kernel_checkpointing_ssu.cuh\"\n#include \"kernel_checkpointing_ssu_8bit.cuh\"\n#include \"kernel_checkpointing_ssu_main.cuh\"\n#include \"kernel_checkpointing_ssu_precompute.cuh\"\n\nnamespace flashinfer::mamba::checkpointing {\n\n// Map a runtime heads-per-CTA `hc` (a value on the HEADS_PER_GROUP>>k chain the\n// tiling heuristic produces) to a compile-time template arg. Recurses\n// HC = HC_MAX, HC_MAX/2, ... 1 and calls fn<HC>() for the largest HC <= hc, so\n// the per-head smem footprint and grid.z are both compile-time constants.\ntemplate <int HC_MAX, typename Fn>\nvoid dispatch_heads_per_cta(int hc, Fn&& fn) {\n if constexpr (HC_MAX <= 1) {\n fn.template operator()<1>();\n } else if (hc >= HC_MAX) {\n fn.template operator()<HC_MAX>();\n } else {\n dispatch_heads_per_cta<HC_MAX / 2>(hc, fn);\n }\n}\n\n// Map a runtime precompute warp count to a compile-time template arg.\n// Valid values: 4, 8, 16 (minimum 4 — the CB matmul uses 4 warps).\ntemplate <typename Fn>\nvoid dispatch_precompute_num_warps(int nw, Fn&& fn) {\n if (nw >= 16) {\n fn.template operator()<16>();\n } else if (nw >= 8) {\n fn.template operator()<8>();\n } else {\n fn.template operator()<4>();\n }\n}\n\n// ── Dispatcher ─────────────────────────────────────────────────────────────\n// `D_SPLIT` splits each head's DIM axis across `D_SPLIT` CTAs.\n// `VARLEN` selects the packed-token gmem layout (cu_seqlens-driven).\n// `launchCheckpointingSsuImpl` is the per-(D_SPLIT, VARLEN) specialization;\n// `launchCheckpointingSsu` (below) is the runtime dispatcher.\ntemplate <typename input_t, typename dt_t, typename weight_t, typename matrixA_t, typename state_t,\n typename stateIndex_t, typename state_scale_t, int D_SPLIT, bool VARLEN>\nvoid launchCheckpointingSsuImpl(CheckpointingSsuParams& params, int precompute_heads_per_cta,\n int main_pipeline_stages, int main_ctas_per_sm,\n cudaStream_t stream) {\n constexpr int NUM_WARPS = 4;\n\n FLASHINFER_CHECK(params.nheads % params.ngroups == 0, \"nheads (\", params.nheads,\n \") must be divisible by ngroups (\", params.ngroups, \")\");\n\n // cp.async.ca with .L2::128B requires 16B-aligned pointers (128-bit / sizeof element).\n // The .L2::128B hint further requires the base address to be 128B-aligned for full\n // cache line utilization, but the hardware only faults on < 16B alignment.\n // All cp.async-loaded operands need 16B alignment; output is also vectorized\n // (Pair<input_t> stores partitioned by m16n8k16 partition_C — base must be at\n // least 16B-aligned for the stride math to keep per-thread stores aligned).\n FLASHINFER_CHECK_ALIGNMENT(params.B, 16);\n FLASHINFER_CHECK_ALIGNMENT(params.C, 16);\n FLASHINFER_CHECK_ALIGNMENT(params.x, 16);\n FLASHINFER_CHECK_ALIGNMENT(params.state, 16);\n FLASHINFER_CHECK_ALIGNMENT(params.x_cache, 16);\n FLASHINFER_CHECK_ALIGNMENT(params.B_cache, 16);\n FLASHINFER_CHECK_ALIGNMENT(params.output, 16);\n if (params.z != nullptr) {\n FLASHINFER_CHECK_ALIGNMENT(params.z, 16);\n }\n\n // Per-CTA D = DIM / D_SPLIT. Smem footprint shrinks for D-owned\n // buffers (state, x, z, old_x); non-D buffers (B, C, old_B, scalars) unchanged.\n constexpr int D_PER_CTA = DIM / D_SPLIT;\n\n // HEADS_PER_GROUP is JIT-stamped via the customize_config jinja, so only\n // one (nheads / ngroups) specialization gets baked into this .so. The\n // wrapper has already validated `nheads / ngroups == HEADS_PER_GROUP`\n // before reaching us — the kernel cross-checks with an assert below.\n FLASHINFER_CHECK(params.nheads / params.ngroups == HEADS_PER_GROUP,\n \"nheads/ngroups (=\", params.nheads / params.ngroups,\n \") must match JIT HEADS_PER_GROUP=\", HEADS_PER_GROUP);\n // NGROUPS is JIT-stamped too; the ratio check above doesn't pin the absolute\n // group count, and the kernel's unflatten bakes NHEADS = NGROUPS * HEADS_PER_GROUP.\n FLASHINFER_CHECK(params.ngroups == NGROUPS, \"ngroups (=\", params.ngroups,\n \") must match JIT NGROUPS=\", NGROUPS);\n // PDL launch attribute (EXTERNAL chain: a programmatic upstream kernel — e.g.\n // conv1d — overlapping THIS kernel). ENABLE_PDL is JIT-stamped (see\n // checkpointing_ssu_customize_config.jinja); the kernel body gates its\n // conv1d-facing PDL PTX on the same constexpr via `if constexpr (ENABLE_PDL)`.\n // This is the ONLY PDL knob a caller controls — \"does my upstream conv1d\n // overlap the SSU?\". The two-kernel split's INTERNAL precompute→main PDL is\n // NOT gated by this (see below): it is intrinsic to the split, always on.\n // When ENABLE_PDL is false the attribute is 0 — cudaLaunchKernelEx is used\n // either way per FlashInfer convention (see norm.cuh:135).\n cudaLaunchAttribute attrs[1];\n attrs[0].id = cudaLaunchAttributeProgrammaticStreamSerialization;\n attrs[0].val.programmaticStreamSerializationAllowed = ENABLE_PDL ? 1 : 0;\n\n // ── Two-kernel split: precompute → main, when the caller provides scratch ──\n // (cb_scaled/cb_old/cumAdt_vec). Requires 2-byte input (bf16/fp16\n // activations); state may be 2-byte (LDSM path) or 4-byte f32 (LDS.64 +\n // in-register narrow — see make_a_s2r). 8-bit state has no two-kernel\n // split (the monolithic checkpointing_ssu_kernel_8bit handles it).\n //\n // INTERNAL PDL (precompute → main) is ALWAYS on — it is the split's mechanism,\n // not a user knob: the main co-launches with the precompute (its attr below is\n // hard-wired to 1) and runs its precompute-independent state replay while the\n // precompute computes CB / waits on conv1d; the main's own gdc_wait then blocks\n // for the precompute to finish before it reads cb_scaled. This is what lets\n // the replay overlap conv1d on the cliff, so it must not be disable-able.\n //\n // EXTERNAL PDL (conv1d → precompute) rides on ENABLE_PDL (`attrs`): the\n // precompute co-launches with a programmatic conv1d and gdc_waits for B/C.\n // The precompute fires cudaTriggerProgrammaticLaunchCompletion() at its TOP\n // (unconditional) so the main becomes eligible to launch immediately.\n if (params.cb_scaled != nullptr) {\n if constexpr ((sizeof(state_t) == 2 || sizeof(state_t) == 4) && sizeof(input_t) == 2) {\n // Precompute: grid (batch, ngroups, ceil(HEADS_PER_GROUP/HEADS_PER_CTA)).\n // Heads are tiled across grid.z to fill the GPU at small batch (heuristic\n // below). HEADS_PER_CTA is picked at runtime, dispatched to a template arg;\n // DT_SOFTPLUS is JIT-folded on the runtime flag.\n auto launch_precompute =\n [&]<int HEADS_PER_CTA, int PRECOMPUTE_NUM_WARPS, bool DT_SOFTPLUS>() {\n auto pfunc =\n checkpointing_ssu_precompute_kernel<input_t, dt_t, weight_t, matrixA_t, state_t,\n stateIndex_t, NPREDICTED, MAX_WINDOW, DIM,\n DSTATE, HEADS_PER_GROUP, HEADS_PER_CTA,\n PRECOMPUTE_NUM_WARPS, DT_SOFTPLUS, VARLEN>;\n constexpr size_t psmem =\n sizeof(CheckpointingSsuPrecomputeStorage<input_t, NPREDICTED, MAX_WINDOW, DSTATE,\n PRECOMPUTE_NUM_WARPS, HEADS_PER_CTA>);\n if constexpr (psmem > 0) {\n FLASHINFER_CUDA_CHECK(\n cudaFuncSetAttribute(pfunc, cudaFuncAttributeMaxDynamicSharedMemorySize, psmem));\n }\n constexpr int head_tiles = (HEADS_PER_GROUP + HEADS_PER_CTA - 1) / HEADS_PER_CTA;\n cudaLaunchConfig_t pcfg;\n pcfg.gridDim = dim3(params.batch, params.ngroups, head_tiles);\n pcfg.blockDim = dim3(warpSize, PRECOMPUTE_NUM_WARPS);\n pcfg.dynamicSmemBytes = psmem;\n pcfg.stream = stream;\n pcfg.attrs = attrs;\n pcfg.numAttrs = 1;\n FLASHINFER_CUDA_CHECK(cudaLaunchKernelEx(&pcfg, pfunc, params));\n };\n static int const num_sms = [] {\n int dev = 0, n = 0;\n FLASHINFER_CUDA_CHECK(cudaGetDevice(&dev));\n FLASHINFER_CUDA_CHECK(cudaDeviceGetAttribute(&n, cudaDevAttrMultiProcessorCount, dev));\n return n;\n }();\n\n // ── Head-tiling default: heads/CTA == warps/CTA (1 head/warp), coupled in\n // launch_precompute (PRECOMPUTE_NUM_WARPS = max(hc, 4)). hc=8 (→ 8 warps) measured as\n // the robust optimum on B200, across BOTH the cliff and large batch:\n // • small batch: the precompute is latency-bound + under-occupied — 8 warps double\n // the resident warps (occ 6%→12%, matching triton's _dynamic_precompute) to hide\n // the load latency (no-issue 93%→88%, b=16 11.3µs→10.7µs).\n // • large batch: fewer head-tiles per group HALVE the redundant per-group C·B matmul\n // (b=1024: hc=8 136µs vs the old hc=2 143µs — now beats triton-replay-pm).\n // At tiny grids the precompute is so under-occupied that spreading into MORE, smaller\n // CTAs (hc=4 → 4 tiles vs hc=8 → 2) lights up more SMs and edges ahead (+0.1–0.2µs),\n // so back off there. The boundary — measured as b=8 at ng=1/HPG=16 on the 148-SM B200 —\n // is the hc=8 grid (batch·ngroups·HPG/8 CTAs) covering ≥ ~1/10 of the SMs; expressing it\n // that way (instead of raw `batch >= 8`) scales it with ngroups (TP) and GPU size.\n // hc=16 regressed small batch (too few CTAs, 512 thr) without helping large — not worth\n // a 3rd tier. Tunable via precompute_heads_per_cta / the env below;\n // dispatch_heads_per_cta snaps to the HEADS_PER_GROUP>>k chain (clamps to HPG).\n int64_t const hc8_grid = static_cast<int64_t>(params.batch) * params.ngroups *\n (HEADS_PER_GROUP >= 8 ? HEADS_PER_GROUP / 8 : 1);\n int const hc_ideal = (hc8_grid * 10 >= num_sms) ? 8 : 4;\n int hc = HEADS_PER_GROUP;\n while (hc > 1 && hc > hc_ideal) hc >>= 1;\n // Overrides (both snap to the HEADS_PER_GROUP>>k chain in dispatch_heads_per_cta):\n // • precompute_heads_per_cta — the exposed HOST handle (Python-tunable; 0 = heuristic);\n // • FLASHINFER_SSU_HEADS_PER_CTA — an ad-hoc env for quick sweeps.\n // Precedence: explicit handle > env > heuristic. Envs are read PER LAUNCH\n // (getenv is ~ns against a launch; not static, so sweeps/tests see each change).\n int const hc_env = [] {\n char const* e = std::getenv(\"FLASHINFER_SSU_HEADS_PER_CTA\");\n return e ? std::atoi(e) : 0;\n }();\n if (hc_env > 0) hc = hc_env;\n if (precompute_heads_per_cta > 0) hc = precompute_heads_per_cta;\n int const pnw_env = [] {\n char const* e = std::getenv(\"FLASHINFER_SSU_PRECOMPUTE_NUM_WARPS\");\n return e ? std::atoi(e) : 0;\n }();\n dispatch_heads_per_cta<HEADS_PER_GROUP>(hc, [&]<int HEADS_PER_CTA>() {\n int pnw = (HEADS_PER_CTA > 4) ? HEADS_PER_CTA : 4; // default: 1 head/warp, min 4\n if (pnw_env > 0) pnw = pnw_env;\n dispatch_precompute_num_warps(pnw, [&]<int PNW>() {\n if (params.dt_softplus) {\n launch_precompute.template operator()<HEADS_PER_CTA, PNW, true>();\n } else {\n launch_precompute.template operator()<HEADS_PER_CTA, PNW, false>();\n }\n });\n });\n\n // ── Persistent main: 1D grid-stride loop over single-head work-units ──\n // One work-unit = one head; the grid-stride loop is the head-tiling (no host knob).\n // Launch min(cta_per_sm·NUM_SMS, total_work) CTAs; each grid-strides over work-units.\n // Fewer CTAs leave SM room to co-reside with conv1d (closing the no-write gap to\n // triton-replay-pm), and consecutive work-units (head_tile-fastest, see kernel) keep\n // per-group C/old_B L2-hot. Default cta_per_sm huge ⇒ grid == total_work ⇒ one\n // work-unit/CTA ⇒ bit-identical to the old (D_SPLIT, batch, nheads) launch.\n //\n // MAIN_NUM_WARPS=4: the main is NUM_WARPS-generic but feed-bound (long/short scoreboard),\n // not warp-hideable, so 8 warps buys nothing and costs finer MMA tiling + publish barriers.\n constexpr int MAIN_NUM_WARPS = 4;\n\n int const main_total_work =\n D_SPLIT * static_cast<int>(params.batch) * static_cast<int>(params.nheads);\n\n // ── Launch-regime defaults: {NUM_STAGES, cta_per_sm} per (state width, total work) ──\n // THE tuning table — the defaults here must stand on their own; the\n // FLASHINFER_SSU_MAIN_{PIPELINE_STAGES,CTA_PER_SM} envs are optional overrides for\n // experiments, never required. Tuned on the production-shaped workload (mixed PNATs +\n // conv1d/PDL, bench_ssu_checkpoint_mixed.py):\n // • 2-byte state → {1, 16} at every work level. Occupancy regime: ~29 KB/block → 6\n // blocks/SM at the derived reg cap; depth 2 loses b=1024 bf16 (94.0 vs 79.6 µs\n // no-write). cps=16 slightly oversubscribed beats exactly-resident (133.6 vs 139.6);\n // below-occupancy grids are catastrophic.\n // • 4-byte state → {1, 16} at every work level. In mixed batches stg1/cps16 beats\n // stg2/cps4 at EVERY batch (b=32: 14.05 vs 17.22; b=1024: 154.9 vs 163.3 µs e2e):\n // the cps=4 grid's long-lived CTAs eat a binomial write-count straggler tail\n // (~9.5 µs, slot-order experiment) and can't co-reside with conv1d. The ONE regime\n // preferring {2, 4} is UNIFORM-PNAT kernel isolation at work ≳ 8·SMs, where depth 2\n // covers the doubled state prefetch (122.8 vs 150.5 µs b=1024 no-write) — that mix\n // is undetectable at launch (per-slot PNATs live on device) and isn't production-\n // shaped, so it is NOT a default; the envs can pin it for such experiments.\n // `total_work` parameterizes the table for future batch-dependent entries (none today:\n // small batches self-cap the grid at total_work, so cps needs no small-batch entry).\n struct MainRegime {\n int stages, cta_per_sm;\n };\n auto const regime = [](int /*total_work*/) -> MainRegime { return {1, 16}; }(main_total_work);\n\n // Explicit host handles take precedence over the experiment-only envs.\n // Envs are read PER LAUNCH (getenv is ~ns against a launch): tests monkeypatch them\n // per-case, and a static latch would pin the first-seen value for the whole process.\n int const main_cta_per_sm = [&] {\n if (main_ctas_per_sm > 0) return main_ctas_per_sm;\n char const* e = std::getenv(\"FLASHINFER_SSU_MAIN_CTA_PER_SM\");\n int const v = e ? std::atoi(e) : 0; // unset/<=0 → regime default\n return v > 0 ? v : regime.cta_per_sm;\n }();\n int64_t const main_grid_ll = static_cast<int64_t>(main_cta_per_sm) * num_sms;\n int const main_grid =\n static_cast<int>(main_grid_ll < main_total_work ? main_grid_ll : main_total_work);\n\n int const main_stages = [&] {\n if (main_pipeline_stages > 0) {\n FLASHINFER_CHECK(main_pipeline_stages == 1 || main_pipeline_stages == 2,\n \"main_pipeline_stages must be 0 (heuristic), 1, or 2, got \",\n main_pipeline_stages);\n return main_pipeline_stages;\n }\n char const* e = std::getenv(\"FLASHINFER_SSU_MAIN_PIPELINE_STAGES\");\n int const v = e ? std::atoi(e) : 0; // unset → regime default\n FLASHINFER_CHECK(v == 0 || v == 1 || v == 2,\n \"FLASHINFER_SSU_MAIN_PIPELINE_STAGES must be 1 or 2, got \", v);\n return v > 0 ? v : regime.stages;\n }();\n\n // INTERNAL PDL: the main ALWAYS co-launches with the precompute (attr hard-wired to 1,\n // independent of ENABLE_PDL). The one-shot gdc_wait on a CTA's first work-unit blocks for\n // the precompute before reading cb_scaled / cumAdt_vec.\n cudaLaunchAttribute main_attrs[1];\n main_attrs[0].id = cudaLaunchAttributeProgrammaticStreamSerialization;\n main_attrs[0].val.programmaticStreamSerializationAllowed = 1;\n cudaLaunchConfig_t mcfg;\n mcfg.gridDim = dim3(main_grid);\n mcfg.blockDim = dim3(warpSize, MAIN_NUM_WARPS);\n mcfg.stream = stream;\n mcfg.attrs = main_attrs;\n mcfg.numAttrs = 1;\n\n // NGROUPS is the jinja-stamped compile-time group count → the kernel's unflatten divides only\n // by compile-time constants (no runtime div/mod).\n auto launch_main = [&](auto stages_tag) {\n constexpr int MAIN_STAGES = decltype(stages_tag)::value;\n auto mfunc =\n checkpointing_ssu_main_kernel<input_t, dt_t, weight_t, matrixA_t, state_t, stateIndex_t,\n state_scale_t, NPREDICTED, MAX_WINDOW, DIM, DSTATE,\n HEADS_PER_GROUP, PHILOX_ROUNDS, MAIN_NUM_WARPS, D_SPLIT,\n VARLEN, NGROUPS, MAIN_STAGES>;\n constexpr size_t msmem =\n sizeof(CheckpointingSsuMainStorage<input_t, state_t, NPREDICTED, MAX_WINDOW, D_PER_CTA,\n DSTATE, MAIN_STAGES, VARLEN>);\n if constexpr (msmem > 0) {\n FLASHINFER_CUDA_CHECK(\n cudaFuncSetAttribute(mfunc, cudaFuncAttributeMaxDynamicSharedMemorySize, msmem));\n }\n mcfg.dynamicSmemBytes = msmem;\n FLASHINFER_CUDA_CHECK(cudaLaunchKernelEx(&mcfg, mfunc, params));\n };\n if (main_stages == 2) {\n launch_main(std::integral_constant<int, 2>{});\n } else {\n launch_main(std::integral_constant<int, 1>{});\n }\n return;\n } else {\n FLASHINFER_CHECK(false,\n \"two-kernel SSU split (cb_scaled provided) requires 2-byte input \"\n \"(bf16/fp16) and 2- or 4-byte state (bf16/fp16/fp32); got \"\n \"sizeof(input_t)=\",\n sizeof(input_t), \", sizeof(state_t)=\", sizeof(state_t));\n }\n }\n\n auto launch_kernel = [&]() {\n if constexpr (sizeof(state_t) == 1) {\n // int8 chain rewrite — uses checkpointing_ssu_kernel_8bit +\n // CheckpointingSsuStorage8bit. Only D_SPLIT == 1 is valid (the wrapper\n // asserts this); D_SPLIT == 2 still gets template-instantiated by the\n // public dispatcher's switch but is unreachable at runtime — gate the\n // body with `if constexpr (D_SPLIT == 1)` so that path doesn't launch.\n if constexpr (D_SPLIT == 1) {\n auto func =\n checkpointing_ssu_kernel_8bit<input_t, dt_t, weight_t, matrixA_t, state_t, stateIndex_t,\n state_scale_t, NPREDICTED, MAX_WINDOW, DIM, DSTATE,\n HEADS_PER_GROUP, PHILOX_ROUNDS, NUM_WARPS, VARLEN>;\n constexpr size_t smem_size =\n sizeof(CheckpointingSsuStorage8bit<input_t, state_t, NPREDICTED, MAX_WINDOW, D_PER_CTA,\n DSTATE>);\n\n if constexpr (smem_size > 0) {\n FLASHINFER_CUDA_CHECK(\n cudaFuncSetAttribute(func, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n }\n\n cudaLaunchConfig_t config;\n config.gridDim = dim3(D_SPLIT, params.batch, params.nheads);\n config.blockDim = dim3(warpSize, NUM_WARPS);\n config.dynamicSmemBytes = smem_size;\n config.stream = stream;\n config.attrs = attrs;\n config.numAttrs = 1;\n FLASHINFER_CUDA_CHECK(cudaLaunchKernelEx(&config, func, params));\n } else {\n FLASHINFER_CHECK(false,\n \"checkpointing_ssu_kernel_8bit: unsupported D_SPLIT != 1 for 8-bit \"\n \"state_t (got D_SPLIT=\",\n D_SPLIT, \")\");\n }\n } else {\n // Generic kernel: bf16 / fp16 / fp32 state, supports D_SPLIT ∈ {1, 2}.\n auto func =\n checkpointing_ssu_kernel<input_t, dt_t, weight_t, matrixA_t, state_t, stateIndex_t,\n state_scale_t, NPREDICTED, MAX_WINDOW, DIM, DSTATE,\n HEADS_PER_GROUP, PHILOX_ROUNDS, NUM_WARPS, D_SPLIT, VARLEN>;\n\n constexpr size_t smem_size = sizeof(\n CheckpointingSsuStorage<input_t, state_t, NPREDICTED, MAX_WINDOW, D_PER_CTA, DSTATE>);\n\n if constexpr (smem_size > 0) {\n FLASHINFER_CUDA_CHECK(\n cudaFuncSetAttribute(func, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n }\n\n // Grid is (D_SPLIT, batch, nheads). D-tile is the fastest axis so the\n // `D_SPLIT` CTAs of the same head land on adjacent SMs and share L2\n // lines for the redundantly-loaded inputs (C, B, dt, ...).\n cudaLaunchConfig_t config;\n config.gridDim = dim3(D_SPLIT, params.batch, params.nheads);\n config.blockDim = dim3(warpSize, NUM_WARPS);\n config.dynamicSmemBytes = smem_size;\n config.stream = stream;\n config.attrs = attrs;\n config.numAttrs = 1;\n FLASHINFER_CUDA_CHECK(cudaLaunchKernelEx(&config, func, params));\n }\n };\n\n launch_kernel();\n}\n\n// Public dispatcher: routes on `params.d_split` ({1, 2}) and varlen\n// (`params.cu_seqlens != nullptr` → VARLEN=true). Each (D_SPLIT, VARLEN)\n// pair gets its own template specialization — the JIT URI distinguishes them\n// only via `d_split` today, so the same compiled `.so` will hold all four\n// specializations after this commit.\ntemplate <typename input_t, typename dt_t, typename weight_t, typename matrixA_t, typename state_t,\n typename stateIndex_t, typename state_scale_t>\nvoid launchCheckpointingSsu(CheckpointingSsuParams& params, int precompute_heads_per_cta,\n int main_pipeline_stages, int main_ctas_per_sm, cudaStream_t stream) {\n bool const is_varlen = (params.cu_seqlens != nullptr);\n auto launch = [&]<int D_SPLIT, bool VARLEN>() {\n launchCheckpointingSsuImpl<input_t, dt_t, weight_t, matrixA_t, state_t, stateIndex_t,\n state_scale_t, D_SPLIT, VARLEN>(\n params, precompute_heads_per_cta, main_pipeline_stages, main_ctas_per_sm, stream);\n };\n auto launch_d_split = [&]<int D_SPLIT>() {\n if (is_varlen) {\n launch.template operator()<D_SPLIT, true>();\n } else {\n launch.template operator()<D_SPLIT, false>();\n }\n };\n switch (params.d_split) {\n case 1:\n launch_d_split.template operator()<1>();\n break;\n case 2:\n launch_d_split.template operator()<2>();\n break;\n default:\n FLASHINFER_CHECK(false, \"Unsupported d_split: \", params.d_split,\n \". Allowed values: {1, 2}. d_split=4 needs \"\n \"warp-count restructure.\");\n }\n}\n\n} // namespace flashinfer::mamba::checkpointing\n\n#endif // FLASHINFER_MAMBA_LAUNCH_CHECKPOINTING_SSU_CUH_\n"},"diff":{"kind":"string","value":"--- include/flashinfer/mamba/launch_checkpointing_ssu.cuh\n+++ include/flashinfer/mamba/launch_checkpointing_ssu.cuh\n@@ -62,6 +62,7 @@\n template <typename input_t, typename dt_t, typename weight_t, typename matrixA_t, typename state_t,\n typename stateIndex_t, typename state_scale_t, int D_SPLIT, bool VARLEN>\n void launchCheckpointingSsuImpl(CheckpointingSsuParams& params, int precompute_heads_per_cta,\n+ int main_pipeline_stages, int main_ctas_per_sm,\n cudaStream_t stream) {\n constexpr int NUM_WARPS = 4;\n \n@@ -254,9 +255,11 @@\n };\n auto const regime = [](int /*total_work*/) -> MainRegime { return {1, 16}; }(main_total_work);\n \n+ // Explicit host handles take precedence over the experiment-only envs.\n // Envs are read PER LAUNCH (getenv is ~ns against a launch): tests monkeypatch them\n // per-case, and a static latch would pin the first-seen value for the whole process.\n int const main_cta_per_sm = [&] {\n+ if (main_ctas_per_sm > 0) return main_ctas_per_sm;\n char const* e = std::getenv(\"FLASHINFER_SSU_MAIN_CTA_PER_SM\");\n int const v = e ? std::atoi(e) : 0; // unset/<=0 → regime default\n return v > 0 ? v : regime.cta_per_sm;\n@@ -266,6 +269,12 @@\n static_cast<int>(main_grid_ll < main_total_work ? main_grid_ll : main_total_work);\n \n int const main_stages = [&] {\n+ if (main_pipeline_stages > 0) {\n+ FLASHINFER_CHECK(main_pipeline_stages == 1 || main_pipeline_stages == 2,\n+ \"main_pipeline_stages must be 0 (heuristic), 1, or 2, got \",\n+ main_pipeline_stages);\n+ return main_pipeline_stages;\n+ }\n char const* e = std::getenv(\"FLASHINFER_SSU_MAIN_PIPELINE_STAGES\");\n int const v = e ? std::atoi(e) : 0; // unset → regime default\n FLASHINFER_CHECK(v == 0 || v == 1 || v == 2,\n@@ -395,12 +404,12 @@\n template <typename input_t, typename dt_t, typename weight_t, typename matrixA_t, typename state_t,\n typename stateIndex_t, typename state_scale_t>\n void launchCheckpointingSsu(CheckpointingSsuParams& params, int precompute_heads_per_cta,\n- cudaStream_t stream) {\n+ int main_pipeline_stages, int main_ctas_per_sm, cudaStream_t stream) {\n bool const is_varlen = (params.cu_seqlens != nullptr);\n auto launch = [&]<int D_SPLIT, bool VARLEN>() {\n launchCheckpointingSsuImpl<input_t, dt_t, weight_t, matrixA_t, state_t, stateIndex_t,\n- state_scale_t, D_SPLIT, VARLEN>(params, precompute_heads_per_cta,\n- stream);\n+ state_scale_t, D_SPLIT, VARLEN>(\n+ params, precompute_heads_per_cta, main_pipeline_stages, main_ctas_per_sm, stream);\n };\n auto launch_d_split = [&]<int D_SPLIT>() {\n if (is_varlen) {"},"lines_added":{"kind":"number","value":12,"string":"12"},"lines_removed":{"kind":"number","value":3,"string":"3"},"files_in_commit":{"kind":"number","value":7,"string":"7"},"models_mentioned":{"kind":"list like","value":["mamba","nemotron"],"string":"[\n \"mamba\",\n \"nemotron\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["H100"],"string":"[\n \"H100\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (include/flashinfer/mamba/launch_checkpointing_ssu.cuh).\n\nGoal: Add ReplaySSM autotuning\nTarget hardware: H100\nTarget models: mamba, nemotron\n\nCurrent file:\n```cuda\n/*\n * Copyright (c) 2025 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_MAMBA_LAUNCH_CHECKPOINTING_SSU_CUH_\n#define FLASHINFER_MAMBA_LAUNCH_CHECKPOINTING_SSU_CUH_\n\n// Launcher functions for the incremental SSU kernel.\n// Includes both the bf16/fp16/fp32 and 8-bit kernel headers.\n\n#include \"kernel_checkpointing_ssu.cuh\"\n#include \"kernel_checkpointing_ssu_8bit.cuh\"\n#include \"kernel_checkpointing_ssu_main.cuh\"\n#include \"kernel_checkpointing_ssu_precompute.cuh\"\n\nnamespace flashinfer::mamba::checkpointing {\n\n// Map a runtime heads-per-CTA `hc` (a value on the HEADS_PER_GROUP>>k chain the\n// tiling heuristic produces) to a compile-time template arg. Recurses\n// HC = HC_MAX, HC_MAX/2, ... 1 and calls fn<HC>() for the largest HC <= hc, so\n// the per-head smem footprint and grid.z are both compile-time constants.\ntemplate <int HC_MAX, typename Fn>\nvoid dispatch_heads_per_cta(int hc, Fn&& fn) {\n if constexpr (HC_MAX <= 1) {\n fn.template operator()<1>();\n } else if (hc >= HC_MAX) {\n fn.template operator()<HC_MAX>();\n } else {\n dispatch_heads_per_cta<HC_MAX / 2>(hc, fn);\n }\n}\n\n// Map a runtime precompute warp count to a compile-time template arg.\n// Valid values: 4, 8, 16 (minimum 4 — the CB matmul uses 4 warps).\ntemplate <typename Fn>\nvoid dispatch_precompute_num_warps(int nw, Fn&& fn) {\n if (nw >= 16) {\n fn.template operator()<16>();\n } else if (nw >= 8) {\n fn.template operator()<8>();\n } else {\n fn.template operator()<4>();\n }\n}\n\n// ── Dispatcher ─────────────────────────────────────────────────────────────\n// `D_SPLIT` splits each head's DIM axis across `D_SPLIT` CTAs.\n// `VARLEN` selects the packed-token gmem layout (cu_seqlens-driven).\n// `launchCheckpointingSsuImpl` is the per-(D_SPLIT, VARLEN) specialization;\n// `launchCheckpointingSsu` (below) is the runtime dispatcher.\ntemplate <typename input_t, typename dt_t, typename weight_t, typename matrixA_t, typename state_t,\n typename stateIndex_t, typename state_scale_t, int D_SPLIT, bool VARLEN>\nvoid launchCheckpointingSsuImpl(CheckpointingSsuParams& params, int precompute_heads_per_cta,\n cudaStream_t stream) {\n constexpr int NUM_WARPS = 4;\n\n FLASHINFER_CHECK(params.nheads % params.ngroups == 0, \"nheads (\", params.nheads,\n \") must be divisible by ngroups (\", params.ngroups, \")\");\n\n // cp.async.ca with .L2::128B requires 16B-aligned pointers (128-bit / sizeof element).\n // The .L2::128B hint further requires the base address to be 128B-aligned for full\n // cache line utilization, but the hardware only faults on < 16B alignment.\n // All cp.async-loaded operands need 16B alignment; output is also vectorized\n // (Pair<input_t> stores partitioned by m16n8k16 partition_C — base must be at\n // least 16B-aligned for the stride math to keep per-thread stores aligned).\n FLASHINFER_CHECK_ALIGNMENT(params.B, 16);\n FLASHINFER_CHECK_ALIGNMENT(params.C, 16);\n FLASHINFER_CHECK_ALIGNMENT(params.x, 16);\n FLASHINFER_CHECK_ALIGNMENT(params.state, 16);\n FLASHINFER_CHECK_ALIGNMENT(params.x_cache, 16);\n FLASHINFER_CHECK_ALIGNMENT(params.B_cache, 16);\n FLASHINFER_CHECK_ALIGNMENT(params.output, 16);\n if (params.z != nullptr) {\n FLASHINFER_CHECK_ALIGNMENT(params.z, 16);\n }\n\n // Per-CTA D = DIM / D_SPLIT. Smem footprint shrinks for D-owned\n // buffers (state, x, z, old_x); non-D buffers (B, C, old_B, scalars) unchanged.\n constexpr int D_PER_CTA = DIM / D_SPLIT;\n\n // HEADS_PER_GROUP is JIT-stamped via the customize_config jinja, so only\n // one (nheads / ngroups) specialization gets baked into this .so. The\n // wrapper has already validated `nheads / ngroups == HEADS_PER_GROUP`\n // before reaching us — the kernel cross-checks with an assert below.\n FLASHINFER_CHECK(params.nheads / params.ngroups == HEADS_PER_GROUP,\n \"nheads/ngroups (=\", params.nheads / params.ngroups,\n \") must match JIT HEADS_PER_GROUP=\", HEADS_PER_GROUP);\n // NGROUPS is JIT-stamped too; the ratio check above doesn't pin the absolute\n // group count, and the kernel's unflatten bakes NHEADS = NGROUPS * HEADS_PER_GROUP.\n FLASHINFER_CHECK(params.ngroups == NGROUPS, \"ngroups (=\", params.ngroups,\n \") must match JIT NGROUPS=\", NGROUPS);\n // PDL launch attribute (EXTERNAL chain: a programmatic upstream kernel — e.g.\n // conv1d — overlapping THIS kernel). ENABLE_PDL is JIT-stamped (see\n // checkpointing_ssu_customize_config.jinja); the kernel body gates its\n // conv1d-facing PDL PTX on the same constexpr via `if constexpr (ENABLE_PDL)`.\n // This is the ONLY PDL knob a caller controls — \"does my upstream conv1d\n // overlap the SSU?\". The two-kernel split's INTERNAL precompute→main PDL is\n // NOT gated by this (see below): it is intrinsic to the split, always on.\n // When ENABLE_PDL is false the attribute is 0 — cudaLaunchKernelEx is used\n // either way per FlashInfer convention (see norm.cuh:135).\n cudaLaunchAttribute attrs[1];\n attrs[0].id = cudaLaunchAttributeProgrammaticStreamSerialization;\n attrs[0].val.programmaticStreamSerializationAllowed = ENABLE_PDL ? 1 : 0;\n\n // ── Two-kernel split: precompute → main, when the caller provides scratch ──\n // (cb_scaled/cb_old/cumAdt_vec). Requires 2-byte input (bf16/fp16\n // activations); state may be 2-byte (LDSM path) or 4-byte f32 (LDS.64 +\n // in-register narrow — see make_a_s2r). 8-bit state has no two-kernel\n // split (the monolithic checkpointing_ssu_kernel_8bit handles it).\n //\n // INTERNAL PDL (precompute → main) is ALWAYS on — it is the split's mechanism,\n // not a user knob: the main co-launches with the precompute (its attr below is\n // hard-wired to 1) and runs its precompute-independent state replay while the\n // precompute computes CB / waits on conv1d; the main's own gdc_wait then blocks\n // for the precompute to finish before it reads cb_scaled. This is what lets\n // the replay overlap conv1d on the cliff, so it must not be disable-able.\n //\n // EXTERNAL PDL (conv1d → precompute) rides on ENABLE_PDL (`attrs`): the\n // precompute co-launches with a programmatic conv1d and gdc_waits for B/C.\n // The precompute fires cudaTriggerProgrammaticLaunchCompletion() at its TOP\n // (unconditional) so the main becomes eligible to launch immediately.\n if (params.cb_scaled != nullptr) {\n if constexpr ((sizeof(state_t) == 2 || sizeof(state_t) == 4) && sizeof(input_t) == 2) {\n // Precompute: grid (batch, ngroups, ceil(HEADS_PER_GROUP/HEADS_PER_CTA)).\n // Heads are tiled across grid.z to fill the GPU at small batch (heuristic\n // below). HEADS_PER_CTA is picked at runtime, dispatched to a template arg;\n // DT_SOFTPLUS is JIT-folded on the runtime flag.\n auto launch_precompute =\n [&]<int HEADS_PER_CTA, int PRECOMPUTE_NUM_WARPS, bool DT_SOFTPLUS>() {\n auto pfunc =\n checkpointing_ssu_precompute_kernel<input_t, dt_t, weight_t, matrixA_t, state_t,\n stateIndex_t, NPREDICTED, MAX_WINDOW, DIM,\n DSTATE, HEADS_PER_GROUP, HEADS_PER_CTA,\n PRECOMPUTE_NUM_WARPS, DT_SOFTPLUS, VARLEN>;\n constexpr size_t psmem =\n sizeof(CheckpointingSsuPrecomputeStorage<input_t, NPREDICTED, MAX_WINDOW, DSTATE,\n PRECOMPUTE_NUM_WARPS, HEADS_PER_CTA>);\n if constexpr (psmem > 0) {\n FLASHINFER_CUDA_CHECK(\n cudaFuncSetAttribute(pfunc, cudaFuncAttributeMaxDynamicSharedMemorySize, psmem));\n }\n constexpr int head_tiles = (HEADS_PER_GROUP + HEADS_PER_CTA - 1) / HEADS_PER_CTA;\n cudaLaunchConfig_t pcfg;\n pcfg.gridDim = dim3(params.batch, params.ngroups, head_tiles);\n pcfg.blockDim = dim3(warpSize, PRECOMPUTE_NUM_WARPS);\n pcfg.dynamicSmemBytes = psmem;\n pcfg.stream = stream;\n pcfg.attrs = attrs;\n pcfg.numAttrs = 1;\n FLASHINFER_CUDA_CHECK(cudaLaunchKernelEx(&pcfg, pfunc, params));\n };\n static int const num_sms = [] {\n int dev = 0, n = 0;\n FLASHINFER_CUDA_CHECK(cudaGetDevice(&dev));\n FLASHINFER_CUDA_CHECK(cudaDeviceGetAttribute(&n, cudaDevAttrMultiProcessorCount, dev));\n return n;\n }();\n\n // ── Head-tiling default: heads/CTA == warps/CTA (1 head/warp), coupled in\n // launch_precompute (PRECOMPUTE_NUM_WARPS = max(hc, 4)). hc=8 (→ 8 warps) measured as\n // the robust optimum on B200, across BOTH the cliff and large batch:\n // • small batch: the precompute is latency-bound + under-occupied — 8 warps double\n // the resident warps (occ 6%→12%, matching triton's _dynamic_precompute) to hide\n // the load latency (no-issue 93%→88%, b=16 11.3µs→10.7µs).\n // • large batch: fewer head-tiles per group HALVE the redundant per-group C·B matmul\n // (b=1024: hc=8 136µs vs the old hc=2 143µs — now beats triton-replay-pm).\n // At tiny grids the precompute is so under-occupied that spreading into MORE, smaller\n // CTAs (hc=4 → 4 tiles vs hc=8 → 2) lights up more SMs and edges ahead (+0.1–0.2µs),\n // so back off there. The boundary — measured as b=8 at ng=1/HPG=16 on the 148-SM B200 —\n // is the hc=8 grid (batch·ngroups·HPG/8 CTAs) covering ≥ ~1/10 of the SMs; expressing it\n // that way (instead of raw `batch >= 8`) scales it with ngroups (TP) and GPU size.\n // hc=16 regressed small batch (too few CTAs, 512 thr) without helping large — not worth\n // a 3rd tier. Tunable via precompute_heads_per_cta / the env below;\n // dispatch_heads_per_cta snaps to the HEADS_PER_GROUP>>k chain (clamps to HPG).\n int64_t const hc8_grid = static_cast<int64_t>(params.batch) * params.ngroups *\n (HEADS_PER_GROUP >= 8 ? HEADS_PER_GROUP / 8 : 1);\n int const hc_ideal = (hc8_grid * 10 >= num_sms) ? 8 : 4;\n int hc = HEADS_PER_GROUP;\n while (hc > 1 && hc > hc_ideal) hc >>= 1;\n // Overrides (both snap to the HEADS_PER_GROUP>>k chain in dispatch_heads_per_cta):\n // • precompute_heads_per_cta — the exposed HOST handle (Python-tunable; 0 = heuristic);\n // • FLASHINFER_SSU_HEADS_PER_CTA — an ad-hoc env for quick sweeps.\n // Precedence: explicit handle > env > heuristic. Envs are read PER LAUNCH\n // (getenv is ~ns against a launch; not static, so sweeps/tests see each change).\n int const hc_env = [] {\n char const* e = std::getenv(\"FLASHINFER_SSU_HEADS_PER_CTA\");\n return e ? std::atoi(e) : 0;\n }();\n if (hc_env > 0) hc = hc_env;\n if (precompute_heads_per_cta > 0) hc = precompute_heads_per_cta;\n int const pnw_env = [] {\n char const* e = std::getenv(\"FLASHINFER_SSU_PRECOMPUTE_NUM_WARPS\");\n return e ? std::atoi(e) : 0;\n }();\n dispatch_heads_per_cta<HEADS_PER_GROUP>(hc, [&]<int HEADS_PER_CTA>() {\n int pnw = (HEADS_PER_CTA > 4) ? HEADS_PER_CTA : 4; // default: 1 head/warp, min 4\n if (pnw_env > 0) pnw = pnw_env;\n dispatch_precompute_num_warps(pnw, [&]<int PNW>() {\n if (params.dt_softplus) {\n launch_precompute.template operator()<HEADS_PER_CTA, PNW, true>();\n } else {\n launch_precompute.template operator()<HEADS_PER_CTA, PNW, false>();\n }\n });\n });\n\n // ── Persistent main: 1D grid-stride loop over single-head work-units ──\n // One work-unit = one head; the grid-stride loop is the head-tiling (no host knob).\n // Launch min(cta_per_sm·NUM_SMS, total_work) CTAs; each grid-strides over work-units.\n // Fewer CTAs leave SM room to co-reside with conv1d (closing the no-write gap to\n // triton-replay-pm), and consecutive work-units (head_tile-fastest, see kernel) keep\n // per-group C/old_B L2-hot. Default cta_per_sm huge ⇒ grid == total_work ⇒ one\n // work-unit/CTA ⇒ bit-identical to the old (D_SPLIT, batch, nheads) launch.\n //\n // MAIN_NUM_WARPS=4: the main is NUM_WARPS-generic but feed-bound (long/short scoreboard),\n // not warp-hideable, so 8 warps buys nothing and costs finer MMA tiling + publish barriers.\n constexpr int MAIN_NUM_WARPS = 4;\n\n int const main_total_work =\n D_SPLIT * static_cast<int>(params.batch) * static_cast<int>(params.nheads);\n\n // ── Launch-regime defaults: {NUM_STAGES, cta_per_sm} per (state width, total work) ──\n // THE tuning table — the defaults here must stand on their own; the\n // FLASHINFER_SSU_MAIN_{PIPELINE_STAGES,CTA_PER_SM} envs are optional overrides for\n // experiments, never required. Tuned on the production-shaped workload (mixed PNATs +\n // conv1d/PDL, bench_ssu_checkpoint_mixed.py):\n // • 2-byte state → {1, 16} at every work level. Occupancy regime: ~29 KB/block → 6\n // blocks/SM at the derived reg cap; depth 2 loses b=1024 bf16 (94.0 vs 79.6 µs\n // no-write). cps=16 slightly oversubscribed beats exactly-resident (133.6 vs 139.6);\n // below-occupancy grids are catastrophic.\n // • 4-byte state → {1, 16} at every work level. In mixed batches stg1/cps16 beats\n // stg2/cps4 at EVERY batch (b=32: 14.05 vs 17.22; b=1024: 154.9 vs 163.3 µs e2e):\n // the cps=4 grid's long-lived CTAs eat a binomial write-count straggler tail\n // (~9.5 µs, slot-order experiment) and can't co-reside with conv1d. The ONE regime\n // preferring {2, 4} is UNIFORM-PNAT kernel isolation at work ≳ 8·SMs, where depth 2\n // covers the doubled state prefetch (122.8 vs 150.5 µs b=1024 no-write) — that mix\n // is undetectable at launch (per-slot PNATs live on device) and isn't production-\n // shaped, so it is NOT a default; the envs can pin it for such experiments.\n // `total_work` parameterizes the table for future batch-dependent entries (none today:\n // small batches self-cap the grid at total_work, so cps needs no small-batch entry).\n struct MainRegime {\n int stages, cta_per_sm;\n };\n auto const regime = [](int /*total_work*/) -> MainRegime { return {1, 16}; }(main_total_work);\n\n // Envs are read PER LAUNCH (getenv is ~ns against a launch): tests monkeypatch them\n // per-case, and a static latch would pin the first-seen value for the whole process.\n int const main_cta_per_sm = [&] {\n char const* e = std::getenv(\"FLASHINFER_SSU_MAIN_CTA_PER_SM\");\n int const v = e ? std::atoi(e) : 0; // unset/<=0 → regime default\n return v > 0 ? v : regime.cta_per_sm;\n }();\n int64_t const main_grid_ll = static_cast<int64_t>(main_cta_per_sm) * num_sms;\n int const main_grid =\n static_cast<int>(main_grid_ll < main_total_work ? main_grid_ll : main_total_work);\n\n int const main_stages = [&] {\n char const* e = std::getenv(\"FLASHINFER_SSU_MAIN_PIPELINE_STAGES\");\n int const v = e ? std::atoi(e) : 0; // unset → regime default\n FLASHINFER_CHECK(v == 0 || v == 1 || v == 2,\n \"FLASHINFER_SSU_MAIN_PIPELINE_STAGES must be 1 or 2, got \", v);\n return v > 0 ? v : regime.stages;\n }();\n\n // INTERNAL PDL: the main ALWAYS co-launches with the precompute (attr hard-wired to 1,\n // independent of ENABLE_PDL). The one-shot gdc_wait on a CTA's first work-unit blocks for\n // the precompute before reading cb_scaled / cumAdt_vec.\n cudaLaunchAttribute main_attrs[1];\n main_attrs[0].id = cudaLaunchAttributeProgrammaticStreamSerialization;\n main_attrs[0].val.programmaticStreamSerializationAllowed = 1;\n cudaLaunchConfig_t mcfg;\n mcfg.gridDim = dim3(main_grid);\n mcfg.blockDim = dim3(warpSize, MAIN_NUM_WARPS);\n mcfg.stream = stream;\n mcfg.attrs = main_attrs;\n mcfg.numAttrs = 1;\n\n // NGROUPS is the jinja-stamped compile-time group count → the kernel's unflatten divides only\n // by compile-time constants (no runtime div/mod).\n auto launch_main = [&](auto stages_tag) {\n constexpr int MAIN_STAGES = decltype(stages_tag)::value;\n auto mfunc =\n checkpointing_ssu_main_kernel<input_t, dt_t, weight_t, matrixA_t, state_t, stateIndex_t,\n state_scale_t, NPREDICTED, MAX_WINDOW, DIM, DSTATE,\n HEADS_PER_GROUP, PHILOX_ROUNDS, MAIN_NUM_WARPS, D_SPLIT,\n VARLEN, NGROUPS, MAIN_STAGES>;\n constexpr size_t msmem =\n sizeof(CheckpointingSsuMainStorage<input_t, state_t, NPREDICTED, MAX_WINDOW, D_PER_CTA,\n DSTATE, MAIN_STAGES, VARLEN>);\n if constexpr (msmem > 0) {\n FLASHINFER_CUDA_CHECK(\n cudaFuncSetAttribute(mfunc, cudaFuncAttributeMaxDynamicSharedMemorySize, msmem));\n }\n mcfg.dynamicSmemBytes = msmem;\n FLASHINFER_CUDA_CHECK(cudaLaunchKernelEx(&mcfg, mfunc, params));\n };\n if (main_stages == 2) {\n launch_main(std::integral_constant<int, 2>{});\n } else {\n launch_main(std::integral_constant<int, 1>{});\n }\n return;\n } else {\n FLASHINFER_CHECK(false,\n \"two-kernel SSU split (cb_scaled provided) requires 2-byte input \"\n \"(bf16/fp16) and 2- or 4-byte state (bf16/fp16/fp32); got \"\n \"sizeof(input_t)=\",\n sizeof(input_t), \", sizeof(state_t)=\", sizeof(state_t));\n }\n }\n\n auto launch_kernel = [&]() {\n if constexpr (sizeof(state_t) == 1) {\n // int8 chain rewrite — uses checkpointing_ssu_kernel_8bit +\n // CheckpointingSsuStorage8bit. Only D_SPLIT == 1 is valid (the wrapper\n // asserts this); D_SPLIT == 2 still gets template-instantiated by the\n // public dispatcher's switch but is unreachable at runtime — gate the\n // body with `if constexpr (D_SPLIT == 1)` so that path doesn't launch.\n if constexpr (D_SPLIT == 1) {\n auto func =\n checkpointing_ssu_kernel_8bit<input_t, dt_t, weight_t, matrixA_t, state_t, stateIndex_t,\n state_scale_t, NPREDICTED, MAX_WINDOW, DIM, DSTATE,\n HEADS_PER_GROUP, PHILOX_ROUNDS, NUM_WARPS, VARLEN>;\n constexpr size_t smem_size =\n sizeof(CheckpointingSsuStorage8bit<input_t, state_t, NPREDICTED, MAX_WINDOW, D_PER_CTA,\n DSTATE>);\n\n if constexpr (smem_size > 0) {\n FLASHINFER_CUDA_CHECK(\n cudaFuncSetAttribute(func, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n }\n\n cudaLaunchConfig_t config;\n config.gridDim = dim3(D_SPLIT, params.batch, params.nheads);\n config.blockDim = dim3(warpSize, NUM_WARPS);\n config.dynamicSmemBytes = smem_size;\n config.stream = stream;\n config.attrs = attrs;\n config.numAttrs = 1;\n FLASHINFER_CUDA_CHECK(cudaLaunchKernelEx(&config, func, params));\n } else {\n FLASHINFER_CHECK(false,\n \"checkpointing_ssu_kernel_8bit: unsupported D_SPLIT != 1 for 8-bit \"\n \"state_t (got D_SPLIT=\",\n D_SPLIT, \")\");\n }\n } else {\n // Generic kernel: bf16 / fp16 / fp32 state, supports D_SPLIT ∈ {1, 2}.\n auto func =\n checkpointing_ssu_kernel<input_t, dt_t, weight_t, matrixA_t, state_t, stateIndex_t,\n state_scale_t, NPREDICTED, MAX_WINDOW, DIM, DSTATE,\n HEADS_PER_GROUP, PHILOX_ROUNDS, NUM_WARPS, D_SPLIT, VARLEN>;\n\n constexpr size_t smem_size = sizeof(\n CheckpointingSsuStorage<input_t, state_t, NPREDICTED, MAX_WINDOW, D_PER_CTA, DSTATE>);\n\n if constexpr (smem_size > 0) {\n FLASHINFER_CUDA_CHECK(\n cudaFuncSetAttribute(func, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n }\n\n // Grid is (D_SPLIT, batch, nheads). D-tile is the fastest axis so the\n // `D_SPLIT` CTAs of the same head land on adjacent SMs and share L2\n // lines for the redundantly-loaded inputs (C, B, dt, ...).\n cudaLaunchConfig_t config;\n config.gridDim = dim3(D_SPLIT, params.batch, params.nheads);\n config.blockDim = dim3(warpSize, NUM_WARPS);\n config.dynamicSmemBytes = smem_size;\n config.stream = stream;\n config.attrs = attrs;\n config.numAttrs = 1;\n FLASHINFER_CUDA_CHECK(cudaLaunchKernelEx(&config, func, params));\n }\n };\n\n launch_kernel();\n}\n\n// Public dispatcher: routes on `params.d_split` ({1, 2}) and varlen\n// (`params.cu_seqlens != nullptr` → VARLEN=true). Each (D_SPLIT, VARLEN)\n// pair gets its own template specialization — the JIT URI distinguishes them\n// only via `d_split` today, so the same compiled `.so` will hold all four\n// specializations after this commit.\ntemplate <typename input_t, typename dt_t, typename weight_t, typename matrixA_t, typename state_t,\n typename stateIndex_t, typename state_scale_t>\nvoid launchCheckpointingSsu(CheckpointingSsuParams& params, int precompute_heads_per_cta,\n cudaStream_t stream) {\n bool const is_varlen = (params.cu_seqlens != nullptr);\n auto launch = [&]<int D_SPLIT, bool VARLEN>() {\n launchCheckpointingSsuImpl<input_t, dt_t, weight_t, matrixA_t, state_t, stateIndex_t,\n state_scale_t, D_SPLIT, VARLEN>(params, precompute_heads_per_cta,\n stream);\n };\n auto launch_d_split = [&]<int D_SPLIT>() {\n if (is_varlen) {\n launch.template operator()<D_SPLIT, true>();\n } else {\n launch.template operator()<D_SPLIT, false>();\n }\n };\n switch (params.d_split) {\n case 1:\n launch_d_split.template operator()<1>();\n break;\n case 2:\n launch_d_split.template operator()<2>();\n break;\n default:\n FLASHINFER_CHECK(false, \"Unsupported d_split: \", params.d_split,\n \". Allowed values: {1, 2}. d_split=4 needs \"\n \"warp-count restructure.\");\n }\n}\n\n} // namespace flashinfer::mamba::checkpointing\n\n#endif // FLASHINFER_MAMBA_LAUNCH_CHECKPOINTING_SSU_CUH_\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## Summary\n\nAdds framework-agnostic runtime autotuning for ReplaySSM checkpointing SSU. For eligible dense decode workloads, FlashInfer profiles supported monolithic and two-kernel launches and caches the fastest tactic for reuse.\n\n## What changes\n\n- Exposes main-kernel pipeline stages and CTAs per SM as runtime launch controls, alongside the existing precompute heads-per-CTA control.\n- Adds a `CheckpointingSSURunner` that tunes the algorithm, `d_split`, main launch geometry, and precompute grouping through FlashInfer's generic autotuner.\n- Buckets the active batch dimension while profiling compact private state/ring buffers, preserving the production `dt` broadcast layout and representative replay history.\n- Uses cold-L2 and CUDA-graph profiling, and exposes a scratch allocator so inference frameworks can provide graph-stable two-kernel workspace.\n- Keeps explicit algorithm/launch overrides and unsupported configurations on the normal fallback path.\n\n## Scope\n\nGeneric autotuning is enabled only for dense calls (`cu_seqlens is None`) with the two-kernel scratch buffers present and launch controls left on automatic selection. The implementation contains no vLLM-specific policy or state.\n\n## Validation\n\n- Base-head H100 focused suite: 7 passed, covering scratch allocation, dynamic profiles, cache keys, tactic generation, `d_split`, autotune cache reuse, and monolithic/two-kernel parity.\n- Review-followup H100 checks: 3 focused tests passed, and the newly admitted non-power-of-two launch (`heads_per_group=14`, `heads_per_cta=3`) compiled and executed successfully.\n- H100 `autotune(True)` wall clock at `max_batch=1024`: **63.856 seconds** with a warm JIT module and empty autotuner cache. This used dense `T=4`, BF16 inputs, FP32 state, and Nemotron TP8 geometry (`nheads=16`, `ngroups=1`, `head_dim=64`, `d_state=128`); all 12 batch buckets were saved (3,574 distinct tactic profiles after launch deduplication).\n- Pre-commit and public API/documentation checks pass. The full repository test matrix is pending maintainer CI authorization.\n\n"},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1068,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"6f9a513ab9046319d765dd8c6c7085439a29afbf"},"date":{"kind":"string","value":"2026-09-02T10:57:09-07:00"},"pr_number":{"kind":"number","value":4752,"string":"4,752"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/4752"},"title":{"kind":"string","value":"perf(sparse mla): Update sparse MLA half-Q-tile heuristic to apply to short queries only (#4752)"},"message":{"kind":"string","value":"perf(sparse mla): Update sparse MLA half-Q-tile heuristic to apply to short queries only (#4752)\n\n## 📌 Description\n\n### Summary\n\nThis PR restricts the sparse-MLA half-Q-tile heuristic to short queries\n(`mMaxSeqLenQ <= 16`). Short decode/MTP queries retain the existing Q8\nchoice,\nwhile long-query DeepSeek-V4 prefill uses Q16.\n\nThe existing heuristic considers the number of KV-split CTAs and batch\nsize,\nbut not the amount of Q-axis parallelism. For the DeepSeek-V4 prefill\ncase on\nB200:\n\n- `numHeadsQPerKv = 16`, so the full and half Q tiles are Q16 and Q8.\n- `maxNumCtasPerSeqKv = ceil(min(maxSeqLenKv, sparseMlaTopK) /\ntileSizeKv)`.\n- With `sparseMlaTopK = 2048` and `tileSizeKv = 128`,\n `maxNumCtasPerSeqKv = 16`.\n- At batch 1 on a 148-SM B200, `1 * 16 <= 148 / 8`, so the current\ncondition\n selects Q8 even when `maxSeqLenQ = 16384`.\n\nQ8 is useful for short batch-1 queries because it creates more\nhead-splitting\nCTAs. A 16K query already supplies 16K-way Q-axis parallelism. In that\ncase Q8\nchanges the main-kernel grid from `(16384, 1, 1)` to `(16384, 2, 1)` and\nmakes\ntwo CTAs load the same sparse KV set for the two eight-head groups. Q16\navoids\nthat duplicated KV traffic.\n\nNo new cubin is required: both Q8 and Q16 variants are already shipped.\nThe\nchange only narrows the host-side selector condition.\n\n### vLLM DeepSeek-V4 prefill call site\n\nvLLM invokes this generation-form FlashInfer API from its DeepSeek-V4\n`_forward_prefill` path:\n[`flashinfer_sparse.py:L781-L886`](https://github.com/vllm-project/vllm/blob/728d3ad09/vllm/models/deepseek_v4/nvidia/flashinfer_sparse.py#L781-L886).\nSpecifically, `_forward_prefill` calls\n`flashinfer_trtllm_batch_decode_sparse_mla_dsv4(query=q_chunk, ...)`,\nwhich is\nwhy prefill reaches `selectSparseMlaGenerationKernel()`.\n\n### Native FlashInfer B200 benchmark\n\nThis PR adds `trtllm_batch_decode_sparse_mla_dsv4` as a first-class\nattention\nroutine in the repository's canonical\n`benchmarks/flashinfer_benchmark.py`\ndriver. It uses the public FlashInfer API and the driver's existing\nbackend\nfiltering, common CLI flags, `bench_gpu_time`, cold-L2 handling, CSV\nschema,\ntest-list execution, and generated reproduction commands. Correctness is\nchecked before timing against an independent sampled FP32 attention\noracle.\n\nNative benchmark contract:\n\n- 1x NVIDIA B200; PyTorch `2.13.0+cu130`; FlashInfer `0.6.16.post3`.\n- Batch 1, 16 Q heads, head dim 512, FP8 E4M3 Q/KV, BF16 output.\n- KV sequence length 16,384; 128 SWA + 1,920 compressed entries per\nquery\n (`sparseMlaTopK=2048`); HND cache layout; PDL disabled.\n- Query lengths `1,8,16,17,32,256,4096,16384` cover both sides of the\nguard\n and the target long-prefill case.\n- Canonical `bench_gpu_time`: cold L2, 20 untimed warmups and 100\nmeasured\niterations per case. `cupti-python` was absent in the application image,\nso\n the driver used its documented CUDA-event fallback.\n- Sampled FP32 reference checking ran before timing for every case. All\nBF16\n outputs were finite and the maximum absolute error was `1.81e-4`.\n\nFrom the FlashInfer repository root, the target 16K case can be\nreproduced\nwith the canonical benchmark driver as follows:\n\n```bash\npython3 benchmarks/flashinfer_benchmark.py \\\n --routine trtllm_batch_decode_sparse_mla_dsv4 \\\n --backends trtllm-gen \\\n --batch_size 1 \\\n --s_qo 16384 \\\n --s_kv 16384 \\\n --num_qo_heads 16 \\\n --num_kv_heads 1 \\\n --head_dim_qk 512 \\\n --head_dim_vo 512 \\\n --page_size 256 \\\n --swa_topk 128 \\\n --compressed_kv_len 4096 \\\n --compressed_page_size 64 \\\n --compressed_topk 1920 \\\n --kv_layout HND \\\n --q_dtype fp8_e4m3 \\\n --kv_dtype fp8_e4m3 \\\n --out_dtype bfloat16 \\\n --no_cuda_graph \\\n --refcheck \\\n --dry_run_iters 20 \\\n --num_iters 100 \\\n --generate_repro_command \\\n --case_tag dsv4-q16384 \\\n -vv\n```\n\nFor the full boundary sweep, repeat the same command with\n`--s_qo 1, 8, 16, 17, 32, 256, 4096, 16384` individually. Parent and PR\nmeasurements must be run from their respective source checkouts with a\nfreshly\nbuilt `fmha_gen` host launcher; an installed AOT launcher can otherwise\nhide\nthe selector change.\n\n| Q length | Parent tile | PR tile | Parent (ms) | PR (ms) | Speedup |\n|---:|:---:|:---:|---:|---:|---:|\n| 1 | Q8 | Q8 | 0.027616 | 0.027616 | 1.000x |\n| 8 | Q8 | Q8 | 0.027648 | 0.027584 | 1.002x |\n| 16 | Q8 | Q8 | 0.029696 | 0.029680 | 1.001x |\n| 17 | Q8 | Q16 | 0.029696 | 0.025568 | 1.162x |\n| 32 | Q8 | Q16 | 0.037920 | 0.029696 | 1.277x |\n| 256 | Q8 | Q16 | 0.134144 | 0.080736 | 1.662x |\n| 4,096 | Q8 | Q16 | 1.565744 | 0.825200 | **1.897x** |\n| 16,384 | Q8 | Q16 | 4.931104 | 2.614256 | **1.886x** |\n\nThe canonical-run logs show that the kernel name stays Q8 through `Q=16`\nand\nchanges to Q16 at `Q=17`, exactly matching the new boundary. At the\ntarget\n`Q=16384`, the native API result is a 46.99% latency reduction. The\n`Q<=16`\narms use the same Q8 selector path and agree within 0.23%.\n\n### vLLM DeepSeek-V4 B200 benchmark\n\nHardware and software:\n\n- 8x NVIDIA B200, TP=8\n- DeepSeek-V4-Pro, FP8 KV cache, block size 256\n- vLLM `0.1.dev19908+g728d3ad09`\n- FlashInfer `0.6.16.post3`\n- Image `vllm/vllm-openai:nightly-dev-x86_64-cu13.0.1-728d3ad`\n(SHA-256\n`9d812de47e34568de2a945635dd29cf2d6784fee62e3a602283d2665a9459cac`)\n- `FLASHINFER_MLA_SPARSE_DSV4`, prefill-query quantization enabled, FP4\n indexer cache enabled, MTP=3\n- Concurrency 16, ISL=16,384, OSL=1, seed 42,\n `max_num_batched_tokens=16384`, prefix caching disabled\n\nThe server used the DeepSeek-V4 configuration with the workload changes\nabove.\nThe relevant launch arguments were:\n\n```bash\nvllm serve /models/DeepSeek-V4-Pro \\\n --served-model-name deepseek-ai/DeepSeek-V4-Pro \\\n --trust-remote-code --tensor-parallel-size 8 \\\n --kv-cache-dtype fp8 --block-size 256 --max-model-len 1048576 \\\n --max-num-seqs 32 --max-num-batched-tokens 16384 \\\n --attention-config '{\"backend\":\"FLASHINFER_MLA_SPARSE_DSV4\",\"use_prefill_query_quantization\":true,\"use_fp4_indexer_cache\":true}' \\\n --speculative-config '{\"method\":\"mtp\",\"num_speculative_tokens\":3,\"rejection_sample_method\":\"synthetic\",\"synthetic_acceptance_length\":2.49}' \\\n --no-enable-flashinfer-autotune --no-enable-prefix-caching --enforce-eager\n```\n\nEach arm ran four unprofiled repeats of 16 requests. The first repeat\nused 16\nwarmup requests; the server remained warm for the other repeats. The\nclient\ncommand was:\n\n```bash\npython utils/bench_serving/benchmark_serving.py \\\n --model deepseek-ai/DeepSeek-V4-Pro \\\n --served-model-name deepseek-ai/DeepSeek-V4-Pro \\\n --backend vllm --base-url http://127.0.0.1:8888 \\\n --dataset-name random --random-input-len 16384 --random-output-len 1 \\\n --random-range-ratio 1.0 --max-concurrency 16 --request-rate inf \\\n --num-prompts 16 --ignore-eos --seed 42 --trust-remote-code \\\n --tokenizer-mode deepseek_v4 --use-chat-template --dsv4\n```\n\nQ8 is the parent selector. Q16 is the same image and workload with only\nthis\nquery-length guard applied and the AOT host launcher rebuilt.\n\n| Metric | Q8 (parent) | Q16 (this PR) | Change |\n|---|---:|---:|---:|\n| Four throughput repeats (tok/s) | 25,292.38; 25,286.59; 25,308.48;\n25,294.95 | 27,892.23; 27,939.74; 27,923.39; 27,938.74 | -- |\n| Mean total throughput | 25,295.60 tok/s | 27,923.53 tok/s |\n**+10.39%** |\n| Mean throughput per GPU | 3,161.95 tok/s | 3,490.44 tok/s |\n**+10.39%** |\n| Exact main sparse-MLA kernel | 142.38 ms/step | 75.89 ms/step |\n**1.88x faster; -46.70%** |\n| Overlap-accounted attention | 198.72 ms/step | 132.66 ms/step |\n**-33.24%** |\n| Iteration wall time | 648.73 ms/step | 589.02 ms/step | **-9.20%** |\n| Main-kernel grid | `(16384, 2, 1)` | `(16384, 1, 1)` | **2x fewer\nCTAs** |\n\nThe throughput coefficient of variation was 0.037% for Q8 and 0.079% for\nQ16.\nThe wall-time ratio implies +10.14% throughput, consistent with the\nindependent\nunprofiled +10.39% result.\n\nA 64-step profile validated the selector on all eight ranks. Per rank,\nall\n`62 layers * 64 steps = 3968` main sparse-MLA calls used the Q16 kernel,\nwith\nzero main-path Q8 calls. The two "},"path":{"kind":"string","value":"include/flashinfer/trtllm/fmha/fmhaKernels.cuh"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * Copyright (c) 2020-2026, NVIDIA CORPORATION. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#pragma once\n\n#include <cuda.h>\n\n#include <cfloat>\n#include <cstdint>\n#include <cstring>\n#include <cuda/std/cfloat>\n#include <iterator>\n#include <memory>\n#include <mutex>\n#include <unordered_map>\n\n#include \"../../exception.h\"\n#include \"../../utils.cuh\"\n#include \"../common.h\"\n#include \"cuda_runtime_api.h\"\n#include \"flashInferMetaInfo.h\"\n#include \"fmhaReduction.h\"\n#include \"fmhaRunnerParams.h\"\n#include \"kernelParams.h\"\n#include \"lse.cuh\"\n\n#ifdef TLLM_GEN_FMHA_CUBIN_PATH\nstatic const std::string tllm_gen_fmha_cubin_path = std::string(TLLM_GEN_FMHA_CUBIN_PATH);\n#else\nstatic_assert(false, \"TLLM_GEN_FMHA_CUBIN_PATH macro is not defined when compiling\");\n#endif\n\n#ifdef TLLM_GEN_FMHA_METAINFO_HASH\nstatic const std::string tllm_gen_fmha_metainfo_hash = std::string(TLLM_GEN_FMHA_METAINFO_HASH);\n#else\nstatic_assert(false, \"TLLM_GEN_FMHA_METAINFO_HASH macro is not defined when compiling\");\n#endif\n\nnamespace flashinfer::trtllm_cubin_loader {\nstd::string getCubin(const std::string& kernelName, const std::string& sha256);\n} // namespace flashinfer::trtllm_cubin_loader\nusing flashinfer::trtllm_cubin_loader::getCubin;\n\n// Check if two SM values are family/specific versions of the same architecture\n// Returns true only if one is a family version and the other is a compatible specific version\nconstexpr bool isFamilySpecificSMPair(int sm1, int sm2) {\n if ((sm1 == kSM_100f && (sm2 == kSM_100 || sm2 == kSM_103 || sm2 == kSM_107)) ||\n (sm2 == kSM_100f && (sm1 == kSM_100 || sm1 == kSM_103 || sm1 == kSM_107))) {\n return true;\n }\n return false;\n}\n\nconstexpr bool isSMCompatible(int gpuSM, int kernelSM) {\n if (gpuSM == kSM_103) {\n return kernelSM == kSM_100f || kernelSM == kSM_103;\n } else if (gpuSM == kSM_107) {\n return kernelSM == kSM_100f || kernelSM == kSM_107;\n } else if (gpuSM == kSM_100) {\n return kernelSM == kSM_100f || kernelSM == kSM_100;\n }\n\n return gpuSM == kernelSM;\n}\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\nclass TllmGenFmhaKernel {\n public:\n static constexpr int kDynamicNumTokensPerPageThreshold = 128;\n static constexpr int kDynamicNumTokensPerPageKernelKey = 128;\n\n // The parameters for launching the kernel.\n // maxNumCtasQ, maxNumCtasKv, numCtasX, numCtasY, numCtasZ, clusterDimX\n struct CtaLaunchParams {\n // The maximum number of CTAs in Q dimension.\n int mMaxNumCtasQ;\n // The maximum number of CTAs in Kv dimension.\n int mMaxNumCtasKv;\n // The number of CTAs in X dimension.\n int mNumCtasX;\n // The number of CTAs in Y dimension.\n int mNumCtasY;\n // The number of CTAs in Z dimension.\n int mNumCtasZ;\n // The cluster size in the X dimension.\n int mClusterDimX;\n };\n\n public:\n using KernelMeta = tensorrt_llm::kernels::TllmGenFmhaKernelMetaInfo;\n using RunnerParams = TllmGenFmhaRunnerParams;\n using SelectKernelParams = TllmGenSelectKernelParams;\n\n // Ctor.\n TllmGenFmhaKernel(KernelMeta const* pMetaStart, unsigned int nMetaCount, Data_type dtypeQ,\n Data_type dtypeK, Data_type dtypeV, Data_type dtypeOut, unsigned int smArch,\n int numEltsPerSageAttnBlkQ = 0, int numEltsPerSageAttnBlkK = 0,\n int numEltsPerSageAttnBlkP = 0, int numEltsPerSageAttnBlkV = 0)\n : mDtypeQ(dtypeQ),\n mDtypeK(dtypeK),\n mDtypeV(dtypeV),\n mDtypeOut(dtypeOut),\n mNumEltsPerSageAttnBlkQ(numEltsPerSageAttnBlkQ),\n mNumEltsPerSageAttnBlkK(numEltsPerSageAttnBlkK),\n mNumEltsPerSageAttnBlkP(numEltsPerSageAttnBlkP),\n mNumEltsPerSageAttnBlkV(numEltsPerSageAttnBlkV),\n mKernelMeta(pMetaStart),\n mKernelMetaCount(nMetaCount),\n mSM(smArch),\n mMaxDeviceSmemSize(queryMaxDeviceSmemSize(smArch)) {}\n\n static constexpr unsigned int kSmemOptInThreshold = 48 * 1024;\n static constexpr unsigned int kRubinLegacySmemCap = 228 * 1024;\n static constexpr unsigned int kStaticSmemReserve = 1024;\n\n static bool isRubinOversized(unsigned int sm, unsigned int sharedMemBytes) {\n return sm == kSM_107 && (sharedMemBytes + kStaticSmemReserve > kRubinLegacySmemCap);\n }\n\n void setupKernelSmem(CUfunction func, KernelMeta const& kernelMeta) const {\n // CU_FUNC_ATTRIBUTE_SHARED_MEMORY_MODE and the ALLOW_OVERSIZED enum value require\n // CUDA >= 13.4; CUDA 13.3 only ships the launch-attribute half of this API.\n#if CUDA_VERSION >= 13040\n if (isRubinOversized(mSM, kernelMeta.mSharedMemBytes)) {\n cuErrCheck(cuFuncSetAttribute(func, CU_FUNC_ATTRIBUTE_SHARED_MEMORY_MODE,\n CU_SHARED_MEMORY_MODE_ALLOW_OVERSIZED_SHARED_MEMORY));\n return;\n }\n#endif\n if (kernelMeta.mSharedMemBytes >= kSmemOptInThreshold) {\n cuErrCheck(cuFuncSetAttribute(func, CU_FUNC_ATTRIBUTE_MAX_DYNAMIC_SHARED_SIZE_BYTES,\n kernelMeta.mSharedMemBytes));\n }\n }\n\n void appendOversizedSmemLaunchAttr(CUlaunchAttribute* launch_attribute,\n CUlaunchConfig& launch_config,\n KernelMeta const& kernelMeta) const {\n#if CUDA_VERSION >= 13040\n if (isRubinOversized(mSM, kernelMeta.mSharedMemBytes)) {\n IKL_LOG_DEBUG(\n \"TRTLLM-Gen launch info: using oversized shared memory for kernel %s (smem=%u bytes)\",\n kernelMeta.mFuncName, kernelMeta.mSharedMemBytes);\n launch_attribute[launch_config.numAttrs].id = CU_LAUNCH_ATTRIBUTE_SHARED_MEMORY_MODE;\n launch_attribute[launch_config.numAttrs].value.sharedMemoryMode =\n CU_SHARED_MEMORY_MODE_ALLOW_OVERSIZED_SHARED_MEMORY;\n launch_config.numAttrs += 1;\n }\n#endif\n }\n\n static unsigned int queryMaxDeviceSmemSize(unsigned int smArch) {\n CUdevice device;\n cuErrCheck(cuCtxGetDevice(&device));\n int smem_bytes = 0;\n#if CUDA_VERSION >= 13040\n if (smArch == kSM_107) {\n cuErrCheck(cuDeviceGetAttribute(\n &smem_bytes, CU_DEVICE_ATTRIBUTE_MAX_OVERSIZED_SHARED_MEMORY_PER_BLOCK, device));\n return static_cast<unsigned int>(smem_bytes);\n }\n#endif\n cuErrCheck(cuDeviceGetAttribute(&smem_bytes,\n CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_BLOCK_OPTIN, device));\n return static_cast<unsigned int>(smem_bytes);\n }\n\n void loadKernels() {\n for (unsigned int i = 0; i < mKernelMetaCount; ++i) {\n auto const& kernelMeta = mKernelMeta[i];\n IKL_LOG_DEBUG(\"Checking tllmgen attention kernel %s\", kernelMeta.mFuncName);\n if (kernelMeta.mSharedMemBytes + kStaticSmemReserve > mMaxDeviceSmemSize) {\n continue;\n }\n if (isSMCompatible(mSM, kernelMeta.mSM) && kernelMeta.mDataTypeQ == mDtypeQ &&\n kernelMeta.mDataTypeK == mDtypeK && kernelMeta.mDataTypeV == mDtypeV &&\n kernelMeta.mDataTypeO == mDtypeOut &&\n kernelMeta.mNumEltsPerSageAttnBlkQ == mNumEltsPerSageAttnBlkQ &&\n kernelMeta.mNumEltsPerSageAttnBlkK == mNumEltsPerSageAttnBlkK &&\n kernelMeta.mNumEltsPerSageAttnBlkP == mNumEltsPerSageAttnBlkP &&\n kernelMeta.mNumEltsPerSageAttnBlkV == mNumEltsPerSageAttnBlkV) {\n // Store metadata for later use.\n IKL_LOG_DEBUG(\"Adding tllmgen attention kernel %s\", kernelMeta.mFuncName);\n // Check for hash conflicts.\n uint64_t hash = hashID(kernelMeta);\n if (mKernelMetaMap.find(hash) != mKernelMetaMap.end()) {\n // The kernelMeta of the existing kernel.\n auto const& existingKernelMeta = mKernelMeta[mKernelMetaMap.at(hash)];\n FLASHINFER_CHECK(isFamilySpecificSMPair(existingKernelMeta.mSM, kernelMeta.mSM),\n \"Hash conflicts exist between %s and %s.\", existingKernelMeta.mFuncName,\n kernelMeta.mFuncName);\n\n // Prefer specific SM version over family version (replace if existing is family).\n if (existingKernelMeta.mSM == kSM_100f) {\n mKernelMetaMap[hash] = i;\n }\n } else {\n mKernelMetaMap[hash] = i;\n }\n }\n }\n }\n\n size_t getNumLoadedKernels() const { return mKernelMetaMap.size(); }\n\n inline int getBf16QFp8KvTransformMode(bool enablesKOnlyTransform,\n bool separateTransformedKv) const {\n FLASHINFER_CHECK(!(enablesKOnlyTransform && separateTransformedKv),\n \"BF16Q FP8KV transform mode cannot be both K-only and separate K/V.\");\n if (enablesKOnlyTransform) {\n return static_cast<int>(Bf16QFp8KvTransformMode::KOnly);\n }\n if (separateTransformedKv) {\n return static_cast<int>(Bf16QFp8KvTransformMode::SeparateKv);\n }\n return static_cast<int>(Bf16QFp8KvTransformMode::Full);\n }\n\n inline bool isBf16QFp8KvGeneration() const {\n return mDtypeQ == DATA_TYPE_BF16 && mDtypeK == DATA_TYPE_E4M3 && mDtypeV == DATA_TYPE_E4M3 &&\n mDtypeOut == DATA_TYPE_BF16;\n }\n\n inline bool supportsGqaGroupingTokensHeadsQ(SelectKernelParams const& selectKernelParams) const {\n return mDtypeQ == mDtypeK ||\n (isBf16QFp8KvGeneration() &&\n selectKernelParams.mBf16QFp8KvTransformMode != Bf16QFp8KvTransformMode::Full);\n }\n\n inline uint64_t hashID(int qkvLayout, int maskType, int kernelType, int scheduler,\n int multiCtasKvMode, int headDimPerCtaV, int headDimQk, int headDimV,\n int tileSizeQ, int tileSizeKv, int numTokensPerPage,\n bool dynamicNumTokensPerPage, bool reuseSmemKForV, bool uses2CtaMma,\n bool groupsTokensHeadsQ, int sparseMlaType, bool skipsSoftmax,\n int bf16QFp8KvTransformMode, bool uses2QSlidingWindowKernel,\n bool fp16Softmax, bool usesSpcompress) const {\n FLASHINFER_CHECK((headDimPerCtaV >= 32) && (headDimQk >= 32) && (headDimV >= 32) &&\n (headDimPerCtaV <= 1024) && (headDimQk <= 1024) && (headDimV <= 1024),\n \"Expect (32 <= headDim <= 1024), got headDimPerCtaV=%d, headDimQk=%d, \"\n \"headDimV=%d\",\n headDimPerCtaV, headDimQk, headDimV);\n // The numTokensPerPage must be 0 (unused for non-paged kernels) or power of 2.\n FLASHINFER_CHECK(numTokensPerPage == 0 || ((numTokensPerPage & (numTokensPerPage - 1)) == 0),\n \"The numTokensPerPage must be 0 or power of 2.\");\n FLASHINFER_CHECK(tileSizeQ <= 128 && tileSizeKv <= 128,\n \"The tileSizeQ and tileSizeKv must be <= 128.\");\n FLASHINFER_CHECK((tileSizeQ & (tileSizeQ - 1)) == 0 && (tileSizeKv & (tileSizeKv - 1)) == 0,\n \"The tileSizeQ and tileSizeKv must be power of 2.\");\n FLASHINFER_CHECK(tileSizeKv == 64 || tileSizeKv == 128, \"The tileSizeKv must be 64 or 128.\");\n FLASHINFER_CHECK(sparseMlaType >= 0 && sparseMlaType <= 3,\n \"The sparse MLA type must fit in 2 bits.\");\n FLASHINFER_CHECK(bf16QFp8KvTransformMode >= 0 && bf16QFp8KvTransformMode <= 2,\n \"The BF16Q FP8KV transform mode must fit in 2 bits.\");\n // The enum fields are packed tightly, so an out-of-range value would alias onto its neighbour\n // instead of producing a distinct key. Check them rather than trusting the exporter.\n uint64_t const numTokensPerPageLog2 =\n numTokensPerPage == 0 ? 0 : static_cast<uint64_t>(log2(numTokensPerPage));\n FLASHINFER_CHECK(qkvLayout >= 0 && qkvLayout < 4 && maskType >= 0 && maskType < 8 &&\n kernelType >= 0 && kernelType < 8 && scheduler >= 0 && scheduler < 4 &&\n multiCtasKvMode >= 0 && multiCtasKvMode < 4 &&\n bf16QFp8KvTransformMode >= 0 && bf16QFp8KvTransformMode < 4 &&\n numTokensPerPageLog2 < 16,\n \"Kernel attribute out of range for the hash key: qkvLayout=%d, maskType=%d, \"\n \"kernelType=%d, tileScheduler=%d, multiCtasKvMode=%d, \"\n \"bf16QFp8KvTransformMode=%d, numTokensPerPage=%d\",\n qkvLayout, maskType, kernelType, scheduler, multiCtasKvMode,\n bf16QFp8KvTransformMode, numTokensPerPage);\n // Format of the hash key. The enum fields are packed to their actual width rather than a\n // round 4 bits, which is what makes room for fp16Softmax and usesSpcompress; the key is a\n // private lookup key (nothing persists it), so the layout can move as long as\n // hashID(KernelMeta) and hashFromRunnerParams() move with it.\n // Bit 0 - 1 : qkvLayout.\n // Bit 2 - 4 : maskType.\n // Bit 5 - 7 : kernelType.\n // Bit 8 - 9 : tileScheduler.\n // Bit 10 - 11: multiCtasKvMode.\n // Bit 12 - 19: (headDimPerCtaV >> 3).\n // Bit 20 - 27: (headDimQk >> 3).\n // Bit 28 - 35: (headDimV >> 3).\n // Bit 36 - 37: (tileSizeKv >> 6).\n // Bit 38 - 41: (log2(numTokensPerPage)).\n // Bit 42 - 44: (log2(tileSizeQ)).\n // Bit 45 - 45: reuseSmemKForV.\n // Bit 46 - 46: uses2CtaMma.\n // Bit 47 - 48: sparseMlaType (0=none, 1=static token sparse, 2=dynamic token sparse).\n // Bit 49 - 49: skipsSoftmax.\n // Bit 50 - 50: dynamicNumTokensPerPage.\n // Bit 51 - 52: BF16Q FP8KV transform mode (0=full, 1=K-only, 2=separate K/V).\n // Bit 53 - 53: groupsTokensHeadsQ.\n // Bit 54 - 54: uses2QSlidingWindowKernel (Keeps generation 2Qx1KV SlidingWindowCustom).\n // Bit 55 - 55: fp16Softmax.\n // Bit 56 - 56: usesSpcompress.\n // Bit 57 - 63: unused.\n return (static_cast<uint64_t>(qkvLayout) << 0) | (static_cast<uint64_t>(maskType) << 2) |\n (static_cast<uint64_t>(kernelType) << 5) | (static_cast<uint64_t>(scheduler) << 8) |\n (static_cast<uint64_t>(multiCtasKvMode) << 10) |\n (static_cast<uint64_t>(headDimPerCtaV >> 3) << 12) |\n (static_cast<uint64_t>(headDimQk >> 3) << 20) |\n (static_cast<uint64_t>(headDimV >> 3) << 28) |\n (static_cast<uint64_t>(tileSizeKv >> 6) << 36) | (numTokensPerPageLog2 << 38) |\n (static_cast<uint64_t>(log2(tileSizeQ)) << 42) |\n (static_cast<uint64_t>(reuseSmemKForV) << 45) |\n (static_cast<uint64_t>(uses2CtaMma) << 46) |\n (static_cast<uint64_t>(sparseMlaType) << 47) |\n (static_cast<uint64_t>(skipsSoftmax) << 49) |\n (static_cast<uint64_t>(dynamicNumTokensPerPage) << 50) |\n (static_cast<uint64_t>(bf16QFp8KvTransformMode) << 51) |\n (static_cast<uint64_t>(groupsTokensHeadsQ) << 53) |\n (static_cast<uint64_t>(uses2QSlidingWindowKernel) << 54) |\n (static_cast<uint64_t>(fp16Softmax) << 55) |\n (static_cast<uint64_t>(usesSpcompress) << 56);\n }\n\n inline bool is2QSlidingWindowKernel(KernelMeta const& kernelMeta) const {\n return kernelMeta.mKernelType == static_cast<int>(FmhaKernelType::KeepsMmaAbForGeneration) &&\n kernelMeta.mGroupsTokensHeadsQ && kernelMeta.mStepQ == 2 * kernelMeta.mTileSizeQ;\n }\n\n inline bool isDynamicNumTokensPerPageKernel(KernelMeta const& kernelMeta) const {\n return kernelMeta.mNumTokensPerPage == kDynamicNumTokensPerPageKernelKey &&\n std::strstr(kernelMeta.mFuncName, \"P128\") == nullptr;\n }\n\n uint64_t hashID(KernelMeta const& kernelMeta) const {\n return hashID(\n kernelMeta.mQkvLayout, kernelMeta.mMaskType, kernelMeta.mKernelType,\n kernelMeta.mTileScheduler, kernelMeta.mMultiCtasKvMode, kernelMeta.mHeadDimPerCtaV,\n kernelMeta.mHeadDimQk, kernelMeta.mHeadDimV, kernelMeta.mTileSizeQ, kernelMeta.mTileSizeKv,\n kernelMeta.mNumTokensPerPage, isDynamicNumTokensPerPageKernel(kernelMeta),\n kernelMeta.mReuseSmemKForV, kernelMeta.m2CtaMma, kernelMeta.mGroupsTokensHeadsQ,\n kernelMeta.mSparseAttn, kernelMeta.mSkipsSoftmaxWhenPossible,\n getBf16QFp8KvTransformMode(kernelMeta.mEnablesBf16QFp8KvKOnlyTransform,\n kernelMeta.mSeparateTransformedKv),\n is2QSlidingWindowKernel(kernelMeta), kernelMeta.mFp16Softmax, kernelMeta.mUsesSpcompress);\n }\n\n std::pair<bool, std::string> checkIfKernelExist(RunnerParams const& params) const {\n // The selectKernelParams that might be updated.\n SelectKernelParams selectKernelParams{params};\n // Select the kernel.\n selectKernel(params, selectKernelParams);\n // Hash the runner params.\n auto [hashId, info] = hashFromRunnerParams(params, selectKernelParams);\n return std::make_pair(mKernelMetaMap.find(hashId) != mKernelMetaMap.end(), info);\n }\n\n // start here\n void run(RunnerParams const& params) const {\n SelectKernelParams selectKernelParams{params};\n CtaLaunchParams ctaLaunchParams;\n\n // Kernel selection loop (bounded). Each pass may update selectKernelParams (e.g. switch\n // MultiCtasKvMode to Disabled, upgrade to CgaSmemReduction, or reduce headDimPerCtaV) and\n // request a re-select via mSelectNewKernel. Each trigger fires at most once, so the sequence\n // converges in at most kMaxKernelSelectionPasses passes.\n static constexpr int kMaxKernelSelectionPasses = 4;\n CUfunction func{};\n KernelMeta kernelMeta{};\n for (int pass = 0; pass < kMaxKernelSelectionPasses; ++pass) {\n selectKernel(params, selectKernelParams);\n std::tie(func, kernelMeta) = loadKernel(params, selectKernelParams);\n computeCtaAndClusterConfig(ctaLaunchParams, params, kernelMeta, selectKernelParams);\n if (!selectKernelParams.mSelectNewKernel) {\n break;\n }\n FLASHINFER_CHECK(pass + 1 < kMaxKernelSelectionPasses,\n \"trtllm-gen kernel selection did not converge in %d passes.\",\n kMaxKernelSelectionPasses);\n }\n\n // Prepare the kernel parameters.\n auto kernelParams = KernelParams::setKernelParams(\n params, kernelMeta, ctaLaunchParams.mMaxNumCtasQ, ctaLaunchParams.mMaxNumCtasKv);\n\n // Override SageAttention parameters.\n auto sageParamEncode = [](int blockSize) -> int32_t {\n FLASHINFER_CHECK((blockSize & (blockSize - 1)) == 0,\n \"SageAttention block size must be a power of 2.\");\n return blockSize == 0 ? 0 : __builtin_ctz(static_cast<unsigned int>(blockSize));\n };\n kernelParams.ptrSageAttnSfsQ = params.ptrSageAttnSfsQ;\n kernelParams.ptrSageAttnSfsK = params.ptrSageAttnSfsK;\n kernelParams.ptrSageAttnSfsP = params.ptrSageAttnSfsP;\n kernelParams.ptrSageAttnSfsV = params.ptrSageAttnSfsV;\n kernelParams.mLogNumEltsPerSageAttnBlkQ = sageParamEncode(kernelMeta.mNumEltsPerSageAttnBlkQ);\n kernelParams.mLogNumEltsPerSageAttnBlkK = sageParamEncode(kernelMeta.mNumEltsPerSageAttnBlkK);\n kernelParams.mLogNumEltsPerSageAttnBlkP = sageParamEncode(kernelMeta.mNumEltsPerSageAttnBlkP);\n kernelParams.mLogNumEltsPerSageAttnBlkV = sageParamEncode(kernelMeta.mNumEltsPerSageAttnBlkV);\n\n void* kernelParamsList[] = {&kernelParams};\n CUlaunchAttribute launch_attribute[4] = {};\n CUlaunchConfig launch_config;\n buildLaunchConfig(launch_config, launch_attribute, kernelMeta, ctaLaunchParams, params);\n\n // Debug info.\n IKL_LOG_DEBUG(\n \"TRTLLM-Gen launch info (in TllmGenFmhaKernel %s, %s, %s, %s, %d): kernelName = %s\",\n toStr(mDtypeQ), toStr(mDtypeK), toStr(mDtypeV), toStr(mDtypeOut), mSM,\n kernelMeta.mFuncName);\n IKL_LOG_DEBUG(\n \"TRTLLM-Gen launch info: maxSeqLenQ = %d, \"\n \"maxSeqLenKv = %d, \"\n \"numHeadsQ = %d, \"\n \"numHeadsKv = %d, batchSize = %d, kernelType = %d\",\n params.mMaxSeqLenQ, params.mMaxSeqLenKv, params.mNumHeadsQ, params.mNumHeadsKv,\n params.mBatchSize, static_cast<int>(params.mKernelType));\n IKL_LOG_DEBUG(\n \"TRTLLM-Gen launch info: numCtasX = %d, numCtasY = %d, numCtasZ = %d, clusterDimX = %d\",\n ctaLaunchParams.mNumCtasX, ctaLaunchParams.mNumCtasY, ctaLaunchParams.mNumCtasZ,\n ctaLaunchParams.mClusterDimX);\n\n setNonPortableClusterIfNeeded(func, ctaLaunchParams);\n\n // Force GmemReduction if CgaSmemReduction would need more than one wave (cluster occupancy\n // limit). TODO: find a better heuristic of using CgaSmemReduction.\n if (isCgaSmemReduction(selectKernelParams.mMultiCtasKvMode)) {\n int maxActiveClusters = 1;\n cuErrCheck(cuOccupancyMaxActiveClusters(&maxActiveClusters, func, &launch_config));\n if (maxActiveClusters * ctaLaunchParams.mClusterDimX <\n ctaLaunchParams.mNumCtasX * ctaLaunchParams.mNumCtasY * ctaLaunchParams.mNumCtasZ) {\n selectKernelParams.mForceGmemReduction = true;\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::GmemReduction;\n selectKernel(params, selectKernelParams);\n std::tie(func, kernelMeta) = loadKernel(params, selectKernelParams);\n computeCtaAndClusterConfig(ctaLaunchParams, params, kernelMeta, selectKernelParams);\n FLASHINFER_CHECK(!selectKernelParams.mSelectNewKernel,\n \"trtllm-gen kernel selection did not converge after CgaSmemReduction \"\n \"fallback to GmemReduction.\");\n // Rebuild kernelParams: setKernelParams uses kernelMeta (TMA descriptors, tile shapes)\n // which changed when switching from CgaSmemReduction to GmemReduction kernel.\n kernelParams = KernelParams::setKernelParams(\n params, kernelMeta, ctaLaunchParams.mMaxNumCtasQ, ctaLaunchParams.mMaxNumCtasKv);\n buildLaunchConfig(launch_config, launch_attribute, kernelMeta, ctaLaunchParams, params);\n setNonPortableClusterIfNeeded(func, ctaLaunchParams);\n }\n }\n\n cuErrCheck(cuLaunchKernelEx(&launch_config, func, kernelParamsList, nullptr));\n\n // Run the separate reduction kernel if needed.\n tensorrt_llm::kernels::runFmhaReduction(kernelMeta, kernelParams, params.mMultiProcessorCount,\n params.enable_pdl, params.stream);\n\n if (params.lsePtr != nullptr) {\n FLASHINFER_CUDA_CHECK(flashinfer::ComputeLSEFromMD(\n params.softmaxStatsPtr, params.lsePtr, params.mSumOfSeqLensQ, params.mNumHeadsQ,\n params.lseStrideTokens, params.lseStrideHeads, params.enable_pdl, params.stream));\n }\n }\n\n private:\n // Fill a CUlaunchConfig and its associated attribute array from the current kernel and CTA\n // params. The caller owns the storage for launch_attribute (must be an array of at least 3\n // elements) and is responsible for ensuring it outlives launch_config.\n void buildLaunchConfig(CUlaunchConfig& launch_config, CUlaunchAttribute* launch_attribute,\n KernelMeta const& kernelMeta, CtaLaunchParams const& ctaLaunchParams,\n RunnerParams const& params) const {\n launch_config.blockDimX = kernelMeta.mThreadsPerCTA;\n launch_config.blockDimY = 1;\n launch_config.blockDimZ = 1;\n launch_config.gridDimX = ctaLaunchParams.mNumCtasX;\n launch_config.gridDimY = ctaLaunchParams.mNumCtasY;\n launch_config.gridDimZ = ctaLaunchParams.mNumCtasZ;\n launch_config.hStream = params.stream;\n launch_config.sharedMemBytes = kernelMeta.mSharedMemBytes;\n launch_attribute[0].id = CU_LAUNCH_ATTRIBUTE_CLUSTER_DIMENSION;\n launch_attribute[0].value.clusterDim.x = ctaLaunchParams.mClusterDimX;\n launch_attribute[0].value.clusterDim.y = 1;\n launch_attribute[0].value.clusterDim.z = 1;\n launch_attribute[1].id = CU_LAUNCH_ATTRIBUTE_CLUSTER_SCHEDULING_POLICY_PREFERENCE;\n launch_attribute[1].value.clusterSchedulingPolicyPreference =\n ctaLaunchParams.mClusterDimX > 1 ? CU_CLUSTER_SCHEDULING_POLICY_SPREAD\n : CU_CLUSTER_SCHEDULING_POLICY_DEFAULT;\n launch_attribute[2].id = CU_LAUNCH_ATTRIBUTE_PROGRAMMATIC_STREAM_SERIALIZATION;\n launch_attribute[2].value.programmaticStreamSerializationAllowed = params.enable_pdl;\n launch_config.attrs = launch_attribute;\n launch_config.numAttrs = 3;\n appendOversizedSmemLaunchAttr(launch_attribute, launch_config, kernelMeta);\n }\n\n // Enable non-portable cluster sizes when clusterDimX exceeds the portable limit of 8.\n void setNonPortableClusterIfNeeded(CUfunction func,\n CtaLaunchParams const& ctaLaunchParams) const {\n if (ctaLaunchParams.mClusterDimX > 8) {\n cuErrCheck(cuFuncSetAttribute(func, CU_FUNC_ATTRIBUTE_NON_PORTABLE_CLUSTER_SIZE_ALLOWED,\n 1 // Enable non-portable cluster sizes\n ));\n }\n }\n\n // Is it MLA generation kernel ?\n inline bool isMlaGenKernel(RunnerParams const& params) const {\n return (params.mHeadDimQk == 576 && params.mHeadDimV == 512) ||\n (params.mHeadDimQk == 320 && params.mHeadDimV == 256) ||\n (isSparseMla(params.mSparseMlaType) && params.mHeadDimQk == 512 &&\n params.mHeadDimV == 512);\n }\n\n inline bool useDynamicNumTokensPerPage(RunnerParams const& params) const {\n return isPagedKv(params.mQkvLayout) && !isSparseMla(params.mSparseMlaType) &&\n params.mHeadDimQk == params.mHeadDimV &&\n params.mNumTokensPerPage >= kDynamicNumTokensPerPageThreshold;\n }\n\n void selectNumTokensPerPage(RunnerParams const& params,\n SelectKernelParams& selectKernelParams) const {\n selectKernelParams.mDynamicNumTokensPerPage = false;\n if (isSparseMla(params.mSparseMlaType)) {\n // SparseMla kernels use a fixed numTokensPerPage = 1.\n selectKernelParams.mNumTokensPerPage = 1;\n } else if (!isPagedKv(params.mQkvLayout)) {\n // NumTokensPerPage is set to 0 when not selecting pagedKv-layout kernels.\n selectKernelParams.mNumTokensPerPage = 0;\n } else if (useDynamicNumTokensPerPage(params)) {\n FLASHINFER_CHECK((params.mNumTokensPerPage & (params.mNumTokensPerPage - 1)) == 0,\n \"Dynamic numTokensPerPage requires a power-of-2 page size, got %d.\",\n params.mNumTokensPerPage);\n selectKernelParams.mDynamicNumTokensPerPage = true;\n selectKernelParams.mNumTokensPerPage = kDynamicNumTokensPerPageKernelKey;\n } else {\n selectKernelParams.mNumTokensPerPage = params.mNumTokensPerPage;\n }\n }\n\n bool hasCgaSmemReductionKernel(RunnerParams const& params,\n SelectKernelParams selectKernelParams) const {\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::CgaSmemReduction;\n auto const hashId = hashFromRunnerParams(params, selectKernelParams).first;\n return mKernelMetaMap.find(hashId) != mKernelMetaMap.end();\n }\n\n // Compute the number of CTAs in X, Y and Z dimension and the cluster size in the X dimension.\n void computeCtaAndClusterConfig(CtaLaunchParams& ctaLaunchParams, RunnerParams const& params,\n KernelMeta const& kernelMeta,\n SelectKernelParams& selectKernelParams) const {\n bool isDsv3MinLatencyMode = params.mBatchSize == 1 && params.mMaxSeqLenQ >= 1 &&\n params.mMaxSeqLenQ <= 16 && params.mHeadDimQk == 576 &&\n params.mHeadDimV == 512;\n // Do we need to select a new kernel ?\n selectKernelParams.mSelectNewKernel = false;\n\n // The number of Ctas per Q sequence.\n int numCtasPerSeqQ = (params.mMaxSeqLenQ + kernelMeta.mStepQ - 1) / kernelMeta.mStepQ;\n // The generation-phase kernels might need to group both tokensQ and headsQ into one CTA.\n if (params.mMaxSeqLenQ > 1 && !isContextKernel(params.mKernelType)) {\n // Each CTA handles one tokenQ by default for spec-decoding generation kernel.\n if (!kernelMeta.mGroupsTokensHeadsQ) {\n numCtasPerSeqQ = params.mMaxSeqLenQ;\n } else {\n // Compute numTokensPerCtaQ where each CTA must process complete numGroupedHeadsQ.\n // Note that each CTA must process complete numHeadsQPerKv.\n int numTokensPerCtaQ = std::max(1, kernelMeta.mStepQ / params.mNumHeadsQPerKv);\n // Group both headsQ and tokensQ into one CTA.\n numCtasPerSeqQ = flashinfer::ceil_div(params.mMaxSeqLenQ, numTokensPerCtaQ);\n }\n }\n\n // Compute the grid dimension Y.\n int numHeadsPerCta =\n kernelMeta.mGroupsHeadsQ ? std::min(params.mNumHeadsQPerKv, kernelMeta.mStepQ) : 1;\n int numCtasForAllHeadsQ = params.mNumHeadsQ / numHeadsPerCta;\n FLASHINFER_CHECK(numHeadsPerCta * numCtasForAllHeadsQ == params.mNumHeadsQ,\n \"The numHeadsQ/numHeadsKv is not supported.\");\n // Take the number of headDim CTAs.\n FLASHINFER_CHECK(kernelMeta.mHeadDimV % selectKernelParams.mHeadDimPerCtaV == 0,\n \"The headDimPerCtaV is not supported.\");\n int numCtasPerHeadDim = kernelMeta.mHeadDimV / selectKernelParams.mHeadDimPerCtaV;\n // Compute the current numCtasX.\n int numCtasX = numCtasPerSeqQ;\n // Update the numCtasY.\n int numCtasY = numCtasForAllHeadsQ * numCtasPerHeadDim;\n // Compute the grid dimension Z.\n int numCtasZ = params.mBatchSize;\n // The 2CtaMma kernels will use 2 Ctas in the x dimension (only used by MLA generation kernels)\n // for heads, so numCtasPerHeadDim and numCtasForAllHeadsQ will be handled by the 2Ctas in the x\n // dimension.\n if (isMlaGenKernel(params) && selectKernelParams.mUses2CtaMma) {\n FLASHINFER_CHECK(numCtasForAllHeadsQ == 2 && numCtasPerHeadDim == 2,\n \"Internal error: numCtasPerHeadDim should be 2.\");\n numCtasX *= 2;\n numCtasY /= (numCtasForAllHeadsQ * numCtasPerHeadDim);\n }\n\n // First split the seqLenKv into multiple CTAs if the utilization is not full.\n // The number of Ctas per KV sequence.\n int numCtasPerSeqKv = 1;\n // Consider the multiCtasKvMode for better GPU utilization.\n if (isMultiCtasKvEnabled(selectKernelParams.mMultiCtasKvMode)) {\n // The maximum attention window (the maximum number of tokensKv that will be attended to).\n int maxAttentionWindow{params.mMaxSeqLenKv};\n // The sparseMla only selects topK tokensKv.\n if (isSparseMla(params.mSparseMlaType)) {\n maxAttentionWindow = std::min(params.mMaxSeqLenKv, params.mSparseMlaTopK);\n }\n // Some of the tilesKv will be skipped if the sliding window attention or chunked attention is\n // used.\n if (isSlidingOrChunkedCausalMask(selectKernelParams.mMaskType)) {\n if (params.mMaxSeqLenKv > params.mAttentionWindowSize) {\n // Consider that the first tileKv might contain tokensKv that is out of the attention\n // window.\n maxAttentionWindow =\n std::min(params.mMaxSeqLenKv, params.mAttentionWindowSize + kernelMeta.mStepKv - 1);\n } else {\n maxAttentionWindow = std::min(params.mMaxSeqLenKv, params.mChunkedAttentionSize);\n }\n }\n\n // The maximum number Ctas per Kv sequence, which makes sure that each CtaKv has work to do.\n // The factor of 2 is applied here to ensure the reduction overhead does not outweigh the\n // benefits of a shorter mainloop.\n int const maxNumCtasPerSeqKv =\n (maxAttentionWindow + 2 * kernelMeta.mStepKv - 1) / (2 * kernelMeta.mStepKv);\n int tunedMaxNumCtasPerSeqKv = maxNumCtasPerSeqKv;\n // Cap BF16Q+FP8KV separate-transform splits so the runtime key selects\n // CGA reduction when the smaller split is expected.\n if (isBf16QFp8KvGeneration() &&\n selectKernelParams.mBf16QFp8KvTransformMode == Bf16QFp8KvTransformMode::SeparateKv &&\n isSwapsMmaAbForGenerationKernel(selectKernelParams.mKernelType) &&\n !isGmemReductionWithSeparateKernel(selectKernelParams.mMultiCtasKvMode) &&\n params.mHeadDimV < 512) {\n int const clusterDimX = selectKernelParams.mUses2CtaMma ? 2 : 1;\n int const maxKvSplitsPerCgaCluster = 16 / clusterDimX;\n if (maxNumCtasPerSeqKv <= numCtasForAllHeadsQ * maxKvSplitsPerCgaCluster) {\n int const launchedClusters =\n flashinfer::ceil_div(numCtasX, clusterDimX) * numCtasY * numCtasZ;\n int const residentSplitBudget = std::max(\n 4, flashinfer::ceil_div(params.mMultiProcessorCount * 13 / 20, launchedClusters));\n int const targetMaxNumCtasPerSeqKv =\n std::min(maxNumCtasPerSeqKv, std::min(maxKvSplitsPerCgaCluster, residentSplitBudget));\n if (targetMaxNumCtasPerSeqKv > 1 && targetMaxNumCtasPerSeqKv < maxNumCtasPerSeqKv) {\n int const targetTileSizePerCtaKv =\n isSlidingOrChunkedCausalMask(selectKernelParams.mMaskType)\n ? flashinfer::ceil_div(params.mAttentionWindowSize,\n targetMaxNumCtasPerSeqKv - 1)\n : flashinfer::ceil_div(maxAttentionWindow, targetMaxNumCtasPerSeqKv);\n if (targetTileSizePerCtaKv <= 1024) {\n tunedMaxNumCtasPerSeqKv = targetMaxNumCtasPerSeqKv;\n }\n }\n }\n }\n // Compute numCtasPerSeqKv.\n numCtasPerSeqKv = std::min(\n tunedMaxNumCtasPerSeqKv,\n std::max(1, int32_t(params.mMultiProcessorCount / (numCtasX * numCtasY * numCtasZ))));\n // Update the numCtasX.\n numCtasX *= numCtasPerSeqKv;\n // The current total number of CTAs.\n int totalNumCtas = numCtasX * numCtasZ * numCtasY;\n // Disable the multiCtasKvMode if there is only one CtaKv.\n if (numCtasPerSeqKv <= 1) {\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::Disabled;\n // Enable the persistent scheduler for better performance.\n selectKernelParams.mTileScheduler = TileScheduler::Persistent;\n // Need to select a different kernel.\n selectKernelParams.mSelectNewKernel = true;\n } else if (totalNumCtas < params.mMultiProcessorCount && isMlaGenKernel(params) &&\n !isSparseMla(params.mSparseMlaType) && selectKernelParams.mTileSizeKv == 128 &&\n getEnvUseTileSizeKv64ForTrtllmGen()) {\n // Use smaller tileSizeKv to fully utilize the SMs.\n selectKernelParams.mTileSizeKv = 64;\n // Need to select a different kernel.\n selectKernelParams.mSelectNewKernel = true;\n }\n\n // The P32 cubin inventory contains an H576/V512 CGA kernel for the split-V\n // headDimPerCtaV=128 form. Let the first selection pass split V, then use CGA for the\n // exact one-token decode shape when the matching dtype-specific cubin is registered.\n bool const useMlaH512Cga = isDsv3MinLatencyMode && params.mMaxSeqLenQ == 1 &&\n selectKernelParams.mNumTokensPerPage == 32 &&\n selectKernelParams.mHeadDimPerCtaV == 128 &&\n selectKernelParams.mTileSizeQ == 16 &&\n hasCgaSmemReductionKernel(params, selectKernelParams);\n bool const useCgaSmemReduction =\n (!isDsv3MinLatencyMode && params.mHeadDimV < 512) || useMlaH512Cga;\n\n // Enable the CgaSmemReduction if the numCtasPerSeqKv <= 16 as the maximum cluster dimension\n // is 16. Only the swapsMmaAbForGeneration kernel supports the CgaSmemReduction for now.\n // Other headDimV >= 512 shapes remain excluded because the cubin inventory is incomplete,\n // and tileSizeQ >= 32 CGA variants can exceed the device shared-memory limit.\n if (useCgaSmemReduction && numCtasPerSeqKv > 1 && numCtasPerSeqKv <= 16 &&\n isSwapsMmaAbForGenerationKernel(selectKernelParams.mKernelType) &&\n isGmemReduction(selectKernelParams.mMultiCtasKvMode) &&\n !selectKernelParams.mForceGmemReduction) {\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::CgaSmemReduction;\n // Need to select a different kernel.\n selectKernelParams.mSelectNewKernel = true;\n }\n\n // Add the debug info when multiCtasKvMode is enabled.\n if (numCtasPerSeqKv > 1) {\n IKL_LOG_DEBUG(\n \"TRTLLM-Gen launch info: multiCtasKvMode is enabled with tileSizeKv = %d, \"\n \"numCtasPerSeqKv = %d, \"\n \"numCtasPerSeqQ = \"\n \"%d, numCtasY = %d, numCtasZ = %d\",\n selectKernelParams.mTileSizeKv, numCtasPerSeqKv, numCtasPerSeqQ, numCtasY, numCtasZ);\n }\n }\n\n // The cluster size in the X dimension.\n int clusterDimX = selectKernelParams.mUses2CtaMma ? 2 : 1;\n if (isCgaSmemReduction(selectKernelParams.mMultiCtasKvMode)) {\n // Note 2CtaMma and CgaSmemReduction cannot be used together currently.\n clusterDimX *= numCtasPerSeqKv;\n }\n\n // Compute the current number of CTAs in total.\n int totalNumCtas = numCtasX * numCtasZ * numCtasY;\n\n // Then split the headDimV into multiple CTAs if there are still unused SMs.\n if (isMlaGenKernel(params) && !selectKernelParams.mGroupsTokensHeadsQ &&\n !selectKernelParams.mReuseSmemKForV && !selectKernelParams.mSelectNewKernel &&\n !selectKernelParams.mUses2CtaMma) {\n // Split the headDimV into multiple CTAs if the utilization is not full.\n // It doesn't work with reuseSmemKForV currently.\n // TODO: find better heuristic of splitting headDimV across multiple CTAs.\n\n int corrFactor = isDsv3MinLatencyMode ? 1 : 2;\n if (selectKernelParams.mHeadDimPerCtaV == 512 &&\n totalNumCtas * corrFactor <= params.mMultiProcessorCount) {\n // Use smaller headDimPerCtaV to fully utilize the SMs.\n selectKernelParams.mHeadDimPerCtaV =\n totalNumCtas * 2 * corrFactor <= params.mMultiProcessorCount ? 128 : 256;\n // Need to select a different kernel.\n selectKernelParams.mSelectNewKernel = true;\n }\n }\n\n // Update the parameters for launching the kernel.\n ctaLaunchParams.mMaxNumCtasQ = numCtasPerSeqQ;\n ctaLaunchParams.mMaxNumCtasKv = numCtasPerSeqKv;\n ctaLaunchParams.mNumCtasX = numCtasX;\n ctaLaunchParams.mNumCtasY = numCtasY;\n ctaLaunchParams.mNumCtasZ = numCtasZ;\n ctaLaunchParams.mClusterDimX = clusterDimX;\n }\n\n // Determine if we should use the SwapsMmaAbForGeneration kernel for MLA generation.\n bool useSwapsMmaAbMlaGenKernel(RunnerParams const& params) const {\n // Use the SwapsMmaAbForGeneration kernel for MLA generation when the following conditions are\n // met:\n // 1. The seqLenPerCtaKv <= 1024 based on the benchmark results (this might be fine-tuned\n // later).\n // 2. The numCtas (after splitting the heads across multiple CTAs) <=\n // params.mMultiProcessorCount.\n\n // The maximum number Ctas per Kv sequence, which makes sure that each CtaKv has work to do.\n // Here we assume the stepKv is 256.\n int const maxNumCtasPerSeqKv = flashinfer::ceil_div(params.mMaxSeqLenKv, 256);\n ;\n // The number of Ctas.\n int const numCtas = static_cast<int32_t>(params.mBatchSize * params.mMaxSeqLenQ *\n flashinfer::ceil_div(params.mNumHeadsQPerKv, 16));\n // Compute numCtasPerSeqKv.\n int const numCtasPerSeqKv =\n std::min(maxNumCtasPerSeqKv, std::max(1, int32_t(params.mMultiProcessorCount / numCtas)));\n // Compute the seqLenPerCtaKv.\n int const seqLenPerCtaKv = flashinfer::ceil_div(params.mMaxSeqLenKv, numCtasPerSeqKv);\n // Whether we should use the SwapsMmaAbForGeneration kernel for MLA generation.\n return seqLenPerCtaKv <= 1024 && numCtas <= params.mMultiProcessorCount;\n }\n\n // Return the smallest shipped MLA head tile that contains a non-power-of-two head group below\n // 64 heads. Power-of-two groups and groups with at least 128 heads return zero so callers\n // preserve their existing heuristics; the unsupported 65-127 gap has no Q128 MLA cubin.\n static int getPaddedMlaTileSizeQ(int numHeadsQPerKv) {\n FLASHINFER_CHECK(numHeadsQPerKv > 0, \"The numHeadsQPerKv must be positive, got %d.\",\n numHeadsQPerKv);\n if (numHeadsQPerKv >= 128 || (numHeadsQPerKv & (numHeadsQPerKv - 1)) == 0) {\n return 0;\n }\n FLASHINFER_CHECK(numHeadsQPerKv <= 64,\n \"Non-power-of-two MLA numHeadsQPerKv must be <= 64, got %d.\", numHeadsQPerKv);\n return std::max(8, flashinfer::UpPowerOfTwo(numHeadsQPerKv));\n }\n\n // Select the sparse MLA generation kernel.\n // Heuristics benchmarked on B200 (SM=148, sparseMlaTopK=2048).\n void selectSparseMlaGenerationKernel(RunnerParams const& params,\n SelectKernelParams& selectKernelParams) const {\n // numHeadsQ <= 32 : SwapsMmaAbForGeneration\n // Non-power-of-two head counts use one padded Q8/Q16/Q32 tile. Power-of-two head counts use\n // tileSizeQ = numHeadsQPerKv/2 at batch=1 or numHeadsQPerKv at batch>=2.\n // Threshold: batchSize * maxNumCtasPerSeqKv <= MP/8 (crossover at batch=1->2 on B200).\n // Benchmarks (seqLen=8192, topK=2048): half tileSizeQ wins by 2-6% at batch=1;\n // full tileSizeQ wins by 2-11% at batch>=2.\n // numHeadsQ > 32 : KeepsMmaAbForGeneration, tileSizeQ = 64\n // numHeadsQ=128 at large batch : 2CTA (clusterDimX=2, headDimPerCtaV=256)\n // otherwise : 1CTA, headDimPerCtaV fine-tuned later\n // Note: at small batch e4m3 prefers SwapsMmaAb tileSizeQ=32 (+10%), but fp16 prefers\n // KeepsMmaAb tileSizeQ=64 (+19% at numHeadsQ=128). We keep KeepsMmaAb for numHeadsQ>=64\n // to avoid penalizing fp16.\n\n FmhaKernelType& kernelType = selectKernelParams.mKernelType;\n int& tileSizeQ = selectKernelParams.mTileSizeQ;\n\n if (params.mNumHeadsQPerKv <= 32) {\n kernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n selectKernelParams.mTileSizeKv = 128;\n // mMultiCtasKvMode defaults to GmemReduction from the constructor. computeCtaAndClusterConfig\n // may upgrade it to CgaSmemReduction; that update is preserved naturally across\n // re-selections. The base tileSizeQ is numHeadsQPerKv (one CTA covers all Q heads per token).\n // At batch=1 the GPU is under-utilized, so we halve tileSizeQ to create 2x more\n // head-splitting CTAs. Threshold: batchSize * maxNumCtasPerSeqKv <= MP/8.\n // effectiveSeqLenKv = min(seqLen, topK) = 2048 -> maxNumCtasPerSeqKv = 16.\n // Condition: batchSize * 16 <= MP/8 -> batchSize <= 1 (crossover at batch=1->2).\n // Only halve when half tileSizeQ >= 8 (no valid SwapsMmaAb kernel below tileSizeQ=8).\n int const fullTileSizeQ = params.mNumHeadsQPerKv;\n int const halfTileSizeQ = fullTileSizeQ / 2;\n int const effectiveSeqLenKv = std::min(params.mMaxSeqLenKv, params.mSparseMlaTopK);\n int const maxNumCtasPerSeqKv =\n flashinfer::ceil_div(effectiveSeqLenKv, selectKernelParams.mTileSizeKv);\n bool const useHalfTileSizeQ = halfTileSizeQ >= 8 && params.mBatchSize * maxNumCtasPerSeqKv <=\n params.mMultiProcessorCount / 8;\n tileSizeQ = useHalfTileSizeQ ? halfTileSizeQ : fullTileSizeQ;\n } else {\n // numHeadsQ > 32: use KeepsMmaAbForGeneration.\n kernelType = FmhaKernelType::KeepsMmaAbForGeneration;\n tileSizeQ = 64;\n selectKernelParams.mTileSizeKv = 128;\n // Upgrade GmemReduction (constructor default) to GmemReductionWithSeparateKernel.\n // If computeCtaAndClusterConfig already set it to Disabled (numCtasPerSeqKv==1), the\n // isGmemReduction() guard is false and the Disabled state is preserved on re-selection.\n if (isGmemReduction(selectKernelParams.mMultiCtasKvMode)) {\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::GmemReductionWithSeparateKernel;\n }\n // For numHeadsQ=128, use 2CTA when there are enough CTAs to amortize 2CTA overhead.\n // numCtasPerToken = numHeadsQPerKv / tileSizeQ (number of CTAs per token per batch item).\n // Benchmarks (fp16/e4m3, sparseMlaTopK=2048):\n // decode, s_q=1:\n // batch=1 : 1CTA wins by ~20%; batch=8 : 1CTA wins by 3-8%\n // batch=16 : 2CTA wins by 8-16%; batch=32+: 2CTA wins by 12-20%\n // prefill/spec, s_q>1, DS MLA generation:\n // 2CTA wins by ~20-50% because it avoids the 1CTA h128 path's duplicated head-dim work.\n // Threshold: batchSize * numCtasPerToken * 8 > MP -> crossover at batch ~ MP/16 ~ 9.\n int const numCtasPerToken = params.mNumHeadsQPerKv / 64;\n bool const use2CtaForMultiTokenMla = params.mMaxSeqLenQ > 1;\n bool const use2Cta = params.mNumHeadsQPerKv == 128 &&\n (use2CtaForMultiTokenMla ||\n params.mBatchSize * numCtasPerToken * 8 > params.mMultiProcessorCount);\n if (use2Cta) {\n selectKernelParams.mUses2CtaMma = true;\n selectKernelParams.mHeadDimPerCtaV = 256;\n }\n }\n // Preserve the legacy heuristic above for power-of-two groups. A non-power-of-two group must\n // fit in one padded tile because the final head CTA cannot process a partial tile.\n if (int const paddedTileSizeQ = getPaddedMlaTileSizeQ(params.mNumHeadsQPerKv);\n paddedTileSizeQ != 0) {\n tileSizeQ = paddedTileSizeQ;\n }\n }\n\n inline bool usesGroupedMlaGenerationKernel(RunnerParams const& params) const {\n bool const usesSupportedDtypes = (mDtypeQ == DATA_TYPE_BF16 && mDtypeK == DATA_TYPE_BF16 &&\n mDtypeV == DATA_TYPE_BF16 && mDtypeOut == DATA_TYPE_BF16) ||\n (mDtypeQ == DATA_TYPE_E4M3 && mDtypeK == DATA_TYPE_E4M3 &&\n mDtypeV == DATA_TYPE_E4M3 && mDtypeOut == DATA_TYPE_BF16);\n bool const usesSupportedHeadRatio =\n params.mNumHeadsQPerKv == 8 || params.mNumHeadsQPerKv == 16 || params.mNumHeadsQPerKv == 32;\n\n return !isSparseMla(params.mSparseMlaType) && params.mMaxSeqLenQ > 1 &&\n usesSupportedHeadRatio && params.mBatchSize >= 1 && params.mBatchSize <= 16 &&\n params.mNumTokensPerPage == 32 && params.mHeadDimQk == 576 && params.mHeadDimV == 512 &&\n usesSupportedDtypes;\n }\n\n // Grouped MLA generation packs query tokens and local Q heads into Q64 CTAs.\n void selectGroupedMlaGenerationKernel(RunnerParams const& params,\n SelectKernelParams& selectKernelParams) const {\n selectKernelParams.mKernelType = FmhaKernelType::KeepsMmaAbForGeneration;\n selectKernelParams.mTileSizeQ = 64;\n selectKernelParams.mTileSizeKv = 128;\n // Preserve Disabled/Persistent selected by an earlier low-KV pass.\n if (isMultiCtasKvEnabled(selectKernelParams.mMultiCtasKvMode)) {\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::GmemReductionWithSeparateKernel;\n selectKernelParams.mTileScheduler = TileScheduler::Static;\n }\n selectKernelParams.mForceGmemReduction = true;\n selectKernelParams.mMaskType = TrtllmGenAttentionMaskType::Dense;\n selectKernelParams.mReuseSmemKForV = false;\n selectKernelParams.mGroupsTokensHeadsQ = true;\n selectKernelParams.mUses2CtaMma = false;\n\n int const groupedRows = params.mMaxSeqLenQ * params.mNumHeadsQPerKv;\n int const baseNumCtas =\n params.mBatchSize * params.mNumHeadsKv * flashinfer::ceil_div(groupedRows, 64);\n if (baseNumCtas <= 1) {\n selectKernelParams.mHeadDimPerCtaV = 128;\n } else if (baseNumCtas <= 4) {\n selectKernelParams.mHeadDimPerCtaV = 256;\n } else {\n selectKernelParams.mHeadDimPerCtaV = 512;\n }\n selectKernelParams.mHeadDimPerCtaV =\n std::min(selectKernelParams.mHeadDimPerCtaV, params.mHeadDimV);\n }\n\n // Select the MLA generation kernel.\n void selectMlaGenerationKernel(RunnerParams const& params,\n SelectKernelParams& selectKernelParams) const {\n if (usesGroupedMlaGenerationKernel(params)) {\n selectGroupedMlaGenerationKernel(params, selectKernelParams);\n return;\n }\n selectKernelParams.mGroupsTokensHeadsQ = false;\n\n // The kernel type.\n FmhaKernelType& kernelType = selectKernelParams.mKernelType;\n // The tile size for Q.\n int& tileSizeQ = selectKernelParams.mTileSizeQ;\n\n if (isSparseMla(params.mSparseMlaType)) {\n selectSparseMlaGenerationKernel(params, selectKernelParams);\n } else {\n int const paddedTileSizeQ = getPaddedMlaTileSizeQ(params.mNumHeadsQPerKv);\n // Non-sparse MLA: use SwapsMmaAb when numHeadsQPerKv <= 32 or seqLenPerCtaKv is small.\n // Padded Q64 must use KeepsMmaAb so split-KV also follows its standalone-reducer path.\n bool const useSwapsMmaAb =\n paddedTileSizeQ != 0 ? paddedTileSizeQ <= 32\n : params.mNumHeadsQPerKv <= 32 || useSwapsMmaAbMlaGenKernel(params);\n\n if (useSwapsMmaAb) {\n kernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n tileSizeQ = paddedTileSizeQ != 0 ? paddedTileSizeQ : (params.mNumHeadsQPerKv <= 8 ? 8 : 16);\n } else {\n kernelType = FmhaKernelType::KeepsMmaAbForGeneration;\n tileSizeQ = 64;\n // Always use the separate reduction kernel.\n if (isMultiCtasKvEnabled(selectKernelParams.mMultiCtasKvMode)) {\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::GmemReductionWithSeparateKernel;\n }\n // For non-sparse MLA, always use 2CTA for numHeadsQPerKv=128 (legacy behavior).\n if (params.mNumHeadsQPerKv == 128) {\n selectKernelParams.mUses2CtaMma = true;\n selectKernelParams.mHeadDimPerCtaV = 256;\n }\n }\n }\n }\n\n void syncGqaGenerationTraitsForKernelHash(RunnerParams const& params,\n SelectKernelParams& selectKernelParams) const {\n // Same-dtype GQA generation cubins export this trait for every tile size, including runtime\n // shapes where the resulting CTA covers only one query token.\n selectKernelParams.mGroupsTokensHeadsQ = true;\n bool const multiCtasKvEnabled = isMultiCtasKvEnabled(selectKernelParams.mMultiCtasKvMode);\n if (selectKernelParams.mKernelType == FmhaKernelType::KeepsMmaAbForGeneration &&\n params.mHeadDimV > 256) {\n // Current GQA keepsMmaAb H512 cubins are registered in the split-V\n // headDimPerCtaV=256 form; full-V H512 is a cubin coverage follow-up.\n selectKernelParams.mHeadDimPerCtaV = 256;\n if (multiCtasKvEnabled) {\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::GmemReductionWithSeparateKernel;\n }\n } else {\n // SwapsMmaAb hashes the full-V form; undo a previous keepsMmaAb separate-reduction upgrade\n // when the tile-size cost model walks back to swapsMmaAb.\n selectKernelParams.mHeadDimPerCtaV = params.mHeadDimV;\n if (multiCtasKvEnabled &&\n selectKernelParams.mMultiCtasKvMode == MultiCtasKvMode::GmemReductionWithSeparateKernel) {\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::GmemReduction;\n }\n }\n }\n\n // Selects a heuristic tileSizeQ if groupsTokensHeadsQ is true.\n void selectTileSizeQForGqaGeneration(RunnerParams const& params,\n SelectKernelParams& selectKernelParams) const {\n // Define the per-tile mainloop cost model for different tileSizeQ choices.\n std::unordered_map<int, float> kernelMainloopCost = {\n {128, 2.2}, // Cost factor when tileSizeQ = 128\n {64, 1.68}, // Cost factor when tileSizeQ = 64\n {32, 1.48}, // Cost factor when tileSizeQ = 32\n {16, 1.2}, // Cost factor when tileSizeQ = 16\n {8, 1.0} // Cost factor when tileSizeQ = 8\n };\n\n bool const isBf16QFp8KvFullTransform =\n isBf16QFp8KvGeneration() &&\n selectKernelParams.mBf16QFp8KvTransformMode == Bf16QFp8KvTransformMode::SeparateKv;\n\n // Define the per-tile reduction cost model for different tileSizeQ choices.\n std::unordered_map<int, float> kernelReductionCost = {\n {128, 1.32}, // Reduction cost factor when tileSizeQ = 128\n {64, 1.2}, // Reduction cost factor when tileSizeQ = 64\n {32, 1.08}, // Reduction cost factor when tileSizeQ = 32\n {16, 1.03}, // Reduction cost factor when tileSizeQ = 16\n {8, 1.0} // Reduction cost factor when tileSizeQ = 8\n };\n\n // Full-transform kernels pay conversion work in the KV mainloop, so bias the model toward\n // keeping enough KV parallelism without changing the reduction model.\n float const kernelMainloopCostFactor = isBf16QFp8KvFullTransform ? 2.0f : 1.0f;\n // The reduction cost emulated as a sequence length factor.\n float const kernelReductionSeqLenFactor = 128.0f;\n\n // The parameters for launching the kernel.\n CtaLaunchParams ctaLaunchParams;\n // The copy of the selectKernelParams, which makes sure it won't modify the original\n // selectKernelParams when computing the number of CTAs.\n SelectKernelParams selectKernelParamsCopy = selectKernelParams;\n // Load the kernel.\n auto [func, kernelMeta] = loadKernel(params, selectKernelParamsCopy);\n // Compute numCtasX, numCtasY and numCtasZ.\n computeCtaAndClusterConfig(ctaLaunchParams, params, kernelMeta, selectKernelParamsCopy);\n\n // If there are no free SMs or tileSizeQ is already the smallest one, skip the heuristic\n // selection.\n if (ctaLaunchParams.mNumCtasX * ctaLaunchParams.mNumCtasY * ctaLaunchParams.mNumCtasZ * 2 >\n params.mMultiProcessorCount ||\n selectKernelParamsCopy.mTileSizeQ <= 8) {\n // No need to select the kernel further.\n return;\n }\n\n // Candidate tile sizes for tileSizeQ to explore.\n int const candidateTileSizesQ[] = {128, 64, 32, 16, 8};\n\n // The default tileSizeQ.\n int defaultTileSizeQ = selectKernelParamsCopy.mTileSizeQ;\n // The selected tileSizeQ.\n int selectedTileSizeQ = selectKernelParamsCopy.mTileSizeQ;\n\n // The minimum modeling kernel time.\n float globalModelingKernelTime = FLT_MAX;\n // Loop over each candidate tile size.\n for (int tileSizeQ : candidateTileSizesQ) {\n // Only consider candidates <= default tileSizeQ and ensure each CTA processes full\n // numHeadsQPerKv.\n if (tileSizeQ > defaultTileSizeQ || tileSizeQ < params.mNumHeadsQPerKv) {\n continue;\n }\n\n selectKernelParamsCopy.mTileSizeQ = tileSizeQ;\n if (tileSizeQ >= 64) {\n selectKernelParamsCopy.mKernelType = FmhaKernelType::KeepsMmaAbForGeneration;\n } else {\n selectKernelParamsCopy.mKernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n }\n // Keep headDimPerCtaV and multiCtasKvMode in sync with the candidate kernelType so\n // loadKernel hashes a registered kernel.\n syncGqaGenerationTraitsForKernelHash(params, selectKernelParamsCopy);\n\n // Load the kernel.\n std::tie(func, kernelMeta) = loadKernel(params, selectKernelParamsCopy);\n\n // Compute the number of CTAs.\n computeCtaAndClusterConfig(ctaLaunchParams, params, kernelMeta, selectKernelParamsCopy);\n\n // Compute the seqLenPerCtaKv.\n int32_t seqLenPerCtaKv =\n flashinfer::ceil_div(flashinfer::ceil_div(params.mMaxSeqLenKv, kernelMeta.mStepKv),\n ctaLaunchParams.mMaxNumCtasKv) *\n kernelMeta.mStepKv;\n\n // Compute the modeling kernel time = mainloop cost + reduction cost.\n float modelingKernelTime =\n kernelMainloopCostFactor * kernelMainloopCost.at(tileSizeQ) * seqLenPerCtaKv +\n kernelReductionCost.at(tileSizeQ) * kernelReductionSeqLenFactor *\n ctaLaunchParams.mMaxNumCtasKv;\n\n // Compute the total number of CTAs.\n int32_t numCtas =\n ctaLaunchParams.mNumCtasX * ctaLaunchParams.mNumCtasY * ctaLaunchParams.mNumCtasZ;\n // Compute the number of waves.\n int32_t numWaves = flashinfer::ceil_div(numCtas, params.mMultiProcessorCount);\n // Compute the total modeling kernel time.\n modelingKernelTime *= numWaves;\n\n // If this candidate has a lower time than the global minimum, update the global minimum.\n if (modelingKernelTime < globalModelingKernelTime) {\n globalModelingKernelTime = modelingKernelTime;\n selectedTileSizeQ = tileSizeQ;\n }\n }\n\n // Update the tileSizeQ.\n selectKernelParams.mTileSizeQ = selectedTileSizeQ;\n // Update the kernel type.\n if (selectKernelParams.mTileSizeQ >= 64) {\n selectKernelParams.mKernelType = FmhaKernelType::KeepsMmaAbForGeneration;\n } else {\n selectKernelParams.mKernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n }\n // Apply the same sync to the committed kernelType; the probe above mutated only the copy.\n syncGqaGenerationTraitsForKernelHash(params, selectKernelParams);\n }\n\n // Selects a heuristic kernel for GQA generation.\n void selectGqGenerationKernel(RunnerParams const& params,\n SelectKernelParams& selectKernelParams) const {\n // The kernel type.\n FmhaKernelType& kernelType = selectKernelParams.mKernelType;\n // The tile size for Q.\n int& tileSizeQ = selectKernelParams.mTileSizeQ;\n selectKernelParams.mGroupsTokensHeadsQ = false;\n\n // Generic mixed precision kernels don't work with groupsTokensHeadsQ = true. BF16Q+FP8KV\n // transform paths present BF16 K to BMM1, so they can use the grouped-token cubins.\n if (!supportsGqaGroupingTokensHeadsQ(selectKernelParams)) {\n selectKernelParams.mGroupsTokensHeadsQ = false;\n tileSizeQ = params.mNumHeadsQPerKv <= 8 ? 8 : 16;\n kernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n return;\n }\n selectKernelParams.mGroupsTokensHeadsQ = true;\n\n // The number of tokensQ and headsQ that can be grouped into one CTA.\n int numTokensHeadsQ = params.mNumHeadsQPerKv * params.mMaxSeqLenQ;\n // When numHeadsQPerKv >= 64, use KeepsMmaAbForGeneration kernel.\n if (numTokensHeadsQ <= 8) {\n tileSizeQ = 8;\n kernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n } else if (numTokensHeadsQ <= 16) {\n tileSizeQ = 16;\n kernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n } else if (numTokensHeadsQ <= 32) {\n tileSizeQ = 32;\n kernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n } else if (numTokensHeadsQ <= 64) {\n tileSizeQ = 64;\n kernelType = FmhaKernelType::KeepsMmaAbForGeneration;\n } else {\n tileSizeQ = 128;\n kernelType = FmhaKernelType::KeepsMmaAbForGeneration;\n }\n\n // Normalize traits before the cost-model probe calls loadKernel().\n syncGqaGenerationTraitsForKernelHash(params, selectKernelParams);\n\n // When maxSeqLenQ > 1, use an experimental kernel-timing model to select the best kernel that\n // groups both tokensQ and headsQ into one CTA.\n if (params.mMaxSeqLenQ > 1) {\n selectTileSizeQForGqaGeneration(params, selectKernelParams);\n }\n }\n\n // Select a kernel based on the heuristic.\n void selectKernel(RunnerParams const& params, SelectKernelParams& selectKernelParams) const {\n // Normalize this before heuristic probing; some GQA-generation heuristics load candidate\n // kernels while selecting tileSizeQ.\n selectNumTokensPerPage(params, selectKernelParams);\n bool const isMlaGeneration = isGenerationKernel(params.mKernelType) && isMlaGenKernel(params);\n\n // Select the kernel based on the kernel type.\n if (isMlaGeneration) {\n selectMlaGenerationKernel(params, selectKernelParams);\n // TRTLLM-GEN MLA generation kernels are exported with dense mask metadata. Each generation\n // CTA processes a bounded query tile, so the runtime sequence lengths/indices provide the\n // effective masking.\n selectKernelParams.mMaskType = TrtllmGenAttentionMaskType::Dense;\n if (!isSparseMla(params.mSparseMlaType)) {\n FLASHINFER_CHECK(\n params.mMaxSeqLenKv <= params.mAttentionWindowSize &&\n params.mChunkedAttentionSize == INT_MAX,\n \"TRTLLM-GEN MLA generation does not support sliding-window or chunked attention.\");\n }\n } else if (isGenerationKernel(params.mKernelType)) {\n selectGqGenerationKernel(params, selectKernelParams);\n }\n\n // For headDimV > 256, set headDimPerCtaV to 256 for context and keepsMmaAbForGeneration\n // kernels. swapsMmaAbForGeneration has enough TMEM resources to hold the full headDimV.\n // Called for context and GQA generation; MLA sets headDimPerCtaV separately.\n if (params.mHeadDimV > 256 && !isMlaGenKernel(params) &&\n !isSwapsMmaAbForGenerationKernel(selectKernelParams.mKernelType)) {\n selectKernelParams.mHeadDimPerCtaV = 256;\n }\n\n // Enable sliding window or chunked causal if the max kv sequence length exceeds attention\n // window size or chunked attention size. This is supported by causal-mask context kernels and\n // generation-phase kernels.\n if (!isSparseMla(params.mSparseMlaType) &&\n (selectKernelParams.mMaskType == TrtllmGenAttentionMaskType::Causal ||\n !isContextKernel(params.mKernelType)) &&\n (params.mMaxSeqLenKv > params.mAttentionWindowSize ||\n params.mChunkedAttentionSize != INT_MAX)) {\n FLASHINFER_CHECK(\n params.mMaxSeqLenKv <= params.mAttentionWindowSize ||\n params.mMaxSeqLenKv <= params.mChunkedAttentionSize,\n \"Sliding window attention and chunked attention should not be used together\");\n selectKernelParams.mMaskType = TrtllmGenAttentionMaskType::SlidingOrChunkedCausal;\n }\n }\n\n std::pair<uint64_t, std::string> hashFromRunnerParams(\n RunnerParams const& params, SelectKernelParams& selectKernelParams) const {\n // Debug info.\n std::string info =\n \"qkvLayout=\" + std::to_string(static_cast<int>(params.mQkvLayout)) +\n \", maskType=\" + std::to_string(static_cast<int>(selectKernelParams.mMaskType)) +\n \", kernelType=\" + std::to_string(static_cast<int>(selectKernelParams.mKernelType)) +\n \", tileScheduler=\" + std::to_string(static_cast<int>(selectKernelParams.mTileScheduler)) +\n \", multiCtasKvMode=\" +\n std::to_string(static_cast<int>(selectKernelParams.mMultiCtasKvMode)) +\n \", headDimPerCtaV=\" + std::to_string(selectKernelParams.mHeadDimPerCtaV) +\n \", headDimQk=\" + std::to_string(params.mHeadDimQk) +\n \", headDimV=\" + std::to_string(params.mHeadDimV) +\n \", tileSizeQ=\" + std::to_string(selectKernelParams.mTileSizeQ) +\n \", tileSizeKv=\" + std::to_string(selectKernelParams.mTileSizeKv) +\n \", numTokensPerPage=\" + std::to_string(selectKernelParams.mNumTokensPerPage) +\n \", dynamicNumTokensPerPage=\" + std::to_string(selectKernelParams.mDynamicNumTokensPerPage) +\n \", reuseSmemKForV=\" + std::to_string(selectKernelParams.mReuseSmemKForV) +\n \", uses2CtaMma=\" + std::to_string(selectKernelParams.mUses2CtaMma) +\n \", groupsTokensHeadsQ=\" + std::to_string(selectKernelParams.mGroupsTokensHeadsQ) +\n \", sparseMlaType=\" + std::to_string(static_cast<int>(params.mSparseMlaType)) +\n \", skipsSoftmax=\" + std::to_string(selectKernelParams.mSkipsSoftmaxWhenPossible) +\n \", bf16QFp8KvTransformMode=\" +\n std::to_string(static_cast<int>(selectKernelParams.mBf16QFp8KvTransformMode)) +\n \", fp16Softmax=\" + std::to_string(selectKernelParams.mUseFp16Softmax) +\n \", usesSpcompress=\" + std::to_string(selectKernelParams.mUsesSpcompress);\n IKL_LOG_DEBUG(\n \"Searching for kernel traits (%d available) in TllmGenFmhaKernel(%s, %s, %s, %s, %d) %s\",\n getNumLoadedKernels(), toStr(mDtypeQ), toStr(mDtypeK), toStr(mDtypeV), toStr(mDtypeOut),\n mSM, info.c_str());\n\n return std::make_pair(\n hashID(static_cast<int>(params.mQkvLayout), static_cast<int>(selectKernelParams.mMaskType),\n static_cast<int>(selectKernelParams.mKernelType),\n static_cast<int>(selectKernelParams.mTileScheduler),\n static_cast<int>(selectKernelParams.mMultiCtasKvMode),\n selectKernelParams.mHeadDimPerCtaV, params.mHeadDimQk, params.mHeadDimV,\n selectKernelParams.mTileSizeQ, selectKernelParams.mTileSizeKv,\n selectKernelParams.mNumTokensPerPage, selectKernelParams.mDynamicNumTokensPerPage,\n selectKernelParams.mReuseSmemKForV, selectKernelParams.mUses2CtaMma,\n selectKernelParams.mGroupsTokensHeadsQ, static_cast<int>(params.mSparseMlaType),\n selectKernelParams.mSkipsSoftmaxWhenPossible,\n static_cast<int>(selectKernelParams.mBf16QFp8KvTransformMode),\n /*uses2QSlidingWindowKernel=*/false, selectKernelParams.mUseFp16Softmax,\n selectKernelParams.mUsesSpcompress),\n info);\n }\n\n // Load a single kernel (called by `run()` when needed).\n std::pair<CUfunction, KernelMeta> loadKernel(RunnerParams const& params,\n SelectKernelParams& selectKernelParams) const {\n // Hash the runner params.\n auto [hashId, info] = hashFromRunnerParams(params, selectKernelParams);\n auto const findMetaIter = mKernelMetaMap.find(hashId);\n\n // Add debug info when kernels are not found.\n FLASHINFER_CHECK(findMetaIter != mKernelMetaMap.end(), \"Trtllm-gen kernels not found: \" + info);\n\n // The meta index.\n auto const metaIndex = findMetaIter->second;\n\n // Load the function if not found.\n if (mFunctions.find(hashId) == mFunctions.end()) {\n // Load the kernel on-demand.\n auto const& kernelMeta = mKernelMeta[metaIndex];\n CUmodule hmod{0};\n std::string kernelName(kernelMeta.mFuncName);\n\n // Check if the module is already loaded.\n auto findModuleIter = mModules.find(kernelMeta.mFuncName);\n auto capitalizeFirst = [](std::string str) {\n if (!str.empty()) {\n str[0] = std::toupper(str[0]);\n }\n return str;\n };\n if (findModuleIter == mModules.end()) {\n // Load the module.\n std::string cubin_path = tllm_gen_fmha_cubin_path + \"/\" + kernelMeta.mFuncName + \".cubin\";\n std::string cubin = getCubin(cubin_path, kernelMeta.sha256);\n if (cubin.empty()) {\n throw std::runtime_error(\"Failed to load cubin for \" + kernelName);\n }\n cuErrCheck(cuModuleLoadData(&hmod, cubin.data()));\n mModules[kernelName] = hmod;\n } else {\n hmod = findModuleIter->second;\n }\n\n // Load the function.\n KernelInfo funcInfo;\n funcInfo.mMetaInfoIndex = metaIndex;\n cuErrCheck(cuModuleGetFunction(&funcInfo.mDeviceFunction, hmod, kernelMeta.mFuncName));\n\n setupKernelSmem(funcInfo.mDeviceFunction, kernelMeta);\n\n // Cache the loaded function.\n mFunctions[hashId] = funcInfo;\n }\n\n // Retrieve the loaded kernel.\n auto const& kernelInfo = mFunctions.at(hashId);\n auto const& kernelMeta = mKernelMeta[kernelInfo.mMetaInfoIndex];\n CUfunction func = kernelInfo.mDeviceFunction;\n\n // Return the function and kernelMeta.\n return std::make_pair(func, kernelMeta);\n }\n\n Data_type mDtypeQ, mDtypeK, mDtypeV, mDtypeOut;\n int mNumEltsPerSageAttnBlkQ, mNumEltsPerSageAttnBlkK, mNumEltsPerSageAttnBlkP,\n mNumEltsPerSageAttnBlkV;\n KernelMeta const* mKernelMeta;\n unsigned int mKernelMetaCount;\n unsigned int mSM;\n unsigned int mMaxDeviceSmemSize;\n mutable std::unordered_map<std::string, CUmodule> mModules;\n\n mutable std::unordered_map<uint64_t, unsigned int> mKernelMetaMap;\n\n struct KernelInfo {\n unsigned int mMetaInfoIndex;\n CUfunction mDeviceFunction;\n };\n\n mutable std::unordered_map<uint64_t, KernelInfo> mFunctions;\n};\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n\nclass TllmFmhaKernelFactory {\n public:\n using KernelType = TllmGenFmhaKernel;\n\n KernelType const* getKernels(const typename KernelType::KernelMeta* pKernelList,\n unsigned int nbKernels, Data_type dtypeQ, Data_type dtypeK,\n Data_type dtypeV, Data_type dtypeOut, unsigned int sm,\n int numEltsPerSageAttnBlkQ = 0, int numEltsPerSageAttnBlkK = 0,\n int numEltsPerSageAttnBlkP = 0, int numEltsPerSageAttnBlkV = 0) {\n static std::mutex s_mutex;\n std::lock_guard<std::mutex> lg(s_mutex);\n\n auto const id = hashID(dtypeQ, dtypeK, dtypeV, dtypeOut, sm, numEltsPerSageAttnBlkQ,\n numEltsPerSageAttnBlkK, numEltsPerSageAttnBlkP, numEltsPerSageAttnBlkV);\n auto const findIter = mKernels.find(id);\n if (findIter == mKernels.end()) {\n KernelType* newKernel = new KernelType{pKernelList,\n nbKernels,\n dtypeQ,\n dtypeK,\n dtypeV,\n dtypeOut,\n sm,\n numEltsPerSageAttnBlkQ,\n numEltsPerSageAttnBlkK,\n numEltsPerSageAttnBlkP,\n numEltsPerSageAttnBlkV};\n newKernel->loadKernels();\n mKernels.insert(std::make_pair(id, std::unique_ptr<KernelType>(newKernel)));\n IKL_LOG_DEBUG(\n \"Loading new kernel for dtypeQ=%s, dtypeK=%s, dtypeV=%s, dtypeOut=%s, sm=%d with %d \"\n \"loaded kernels\",\n toStr(dtypeQ), toStr(dtypeK), toStr(dtypeV), toStr(dtypeOut), sm,\n newKernel->getNumLoadedKernels());\n return newKernel;\n }\n return findIter->second.get();\n }\n\n static TllmFmhaKernelFactory& Get() {\n int deviceId;\n cudaGetDevice(&deviceId);\n static std::unique_ptr<TllmFmhaKernelFactory> sFactory[32] = {nullptr};\n if (sFactory[deviceId] == nullptr) {\n FLASHINFER_CHECK(deviceId < 32, \"Invalid deviceId %d (max is 32 devices)\", deviceId);\n sFactory[deviceId] = std::make_unique<TllmFmhaKernelFactory>(TllmFmhaKernelFactory());\n }\n\n return *(sFactory[deviceId]);\n }\n\n private:\n TllmFmhaKernelFactory() = default;\n\n inline uint64_t hashID(Data_type dtypeQ, Data_type dtypeK, Data_type dtypeV, Data_type dtypeOut,\n unsigned int sm, int numEltsPerSageAttnBlkQ, int numEltsPerSageAttnBlkK,\n int numEltsPerSageAttnBlkP, int numEltsPerSageAttnBlkV) const {\n // Encode sage block sizes as log2(size)+1 (0 when unused) to fit in 4 bits each.\n auto const sageEncode = [](int n) -> uint64_t {\n return n > 0 ? static_cast<uint64_t>(log2f(static_cast<float>(n))) + 1 : 0;\n };\n // Bit layout:\n // Bits 0-15: sm\n // Bits 16-19: dtypeQ\n // Bits 20-23: dtypeK\n // Bits 24-27: dtypeV\n // Bits 28-31: dtypeOut\n // Bits 32-35: numEltsPerSageAttnBlkQ (log2+1 encoding)\n // Bits 36-39: numEltsPerSageAttnBlkK\n // Bits 40-43: numEltsPerSageAttnBlkP\n // Bits 44-47: numEltsPerSageAttnBlkV\n return static_cast<uint64_t>(sm) | static_cast<uint64_t>(dtypeQ) << 16 |\n static_cast<uint64_t>(dtypeK) << 20 | static_cast<uint64_t>(dtypeV) << 24 |\n static_cast<uint64_t>(dtypeOut) << 28 | sageEncode(numEltsPerSageAttnBlkQ) << 32 |\n sageEncode(numEltsPerSageAttnBlkK) << 36 | sageEncode(numEltsPerSageAttnBlkP) << 40 |\n sageEncode(numEltsPerSageAttnBlkV) << 44;\n }\n\n std::unordered_map<uint64_t, const std::unique_ptr<KernelType>> mKernels;\n};\n\ninline TllmGenFmhaKernel const* getTllmFmhaKernels(Data_type dtypeQ, Data_type dtypeK,\n Data_type dtypeV, Data_type dtypeOut,\n unsigned int sm, int numEltsPerSageAttnBlkQ = 0,\n int numEltsPerSageAttnBlkK = 0,\n int numEltsPerSageAttnBlkP = 0,\n int numEltsPerSageAttnBlkV = 0) {\n#ifndef EXCLUDE_SM_100\n return TllmFmhaKernelFactory::Get().getKernels(\n tensorrt_llm::kernels::sTllmGenFmhaKernelMetaInfos,\n sizeof(tensorrt_llm::kernels::sTllmGenFmhaKernelMetaInfos) /\n sizeof(tensorrt_llm::kernels::sTllmGenFmhaKernelMetaInfos[0]),\n dtypeQ, dtypeK, dtypeV, dtypeOut, sm, numEltsPerSageAttnBlkQ, numEltsPerSageAttnBlkK,\n numEltsPerSageAttnBlkP, numEltsPerSageAttnBlkV);\n#else\n return nullptr;\n#endif // EXCLUDE_SM_100\n}\n"},"after_code":{"kind":"string","value":"/*\n * Copyright (c) 2020-2026, NVIDIA CORPORATION. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#pragma once\n\n#include <cuda.h>\n\n#include <cfloat>\n#include <cstdint>\n#include <cstring>\n#include <cuda/std/cfloat>\n#include <iterator>\n#include <memory>\n#include <mutex>\n#include <unordered_map>\n\n#include \"../../exception.h\"\n#include \"../../utils.cuh\"\n#include \"../common.h\"\n#include \"cuda_runtime_api.h\"\n#include \"flashInferMetaInfo.h\"\n#include \"fmhaReduction.h\"\n#include \"fmhaRunnerParams.h\"\n#include \"kernelParams.h\"\n#include \"lse.cuh\"\n\n#ifdef TLLM_GEN_FMHA_CUBIN_PATH\nstatic const std::string tllm_gen_fmha_cubin_path = std::string(TLLM_GEN_FMHA_CUBIN_PATH);\n#else\nstatic_assert(false, \"TLLM_GEN_FMHA_CUBIN_PATH macro is not defined when compiling\");\n#endif\n\n#ifdef TLLM_GEN_FMHA_METAINFO_HASH\nstatic const std::string tllm_gen_fmha_metainfo_hash = std::string(TLLM_GEN_FMHA_METAINFO_HASH);\n#else\nstatic_assert(false, \"TLLM_GEN_FMHA_METAINFO_HASH macro is not defined when compiling\");\n#endif\n\nnamespace flashinfer::trtllm_cubin_loader {\nstd::string getCubin(const std::string& kernelName, const std::string& sha256);\n} // namespace flashinfer::trtllm_cubin_loader\nusing flashinfer::trtllm_cubin_loader::getCubin;\n\n// Check if two SM values are family/specific versions of the same architecture\n// Returns true only if one is a family version and the other is a compatible specific version\nconstexpr bool isFamilySpecificSMPair(int sm1, int sm2) {\n if ((sm1 == kSM_100f && (sm2 == kSM_100 || sm2 == kSM_103 || sm2 == kSM_107)) ||\n (sm2 == kSM_100f && (sm1 == kSM_100 || sm1 == kSM_103 || sm1 == kSM_107))) {\n return true;\n }\n return false;\n}\n\nconstexpr bool isSMCompatible(int gpuSM, int kernelSM) {\n if (gpuSM == kSM_103) {\n return kernelSM == kSM_100f || kernelSM == kSM_103;\n } else if (gpuSM == kSM_107) {\n return kernelSM == kSM_100f || kernelSM == kSM_107;\n } else if (gpuSM == kSM_100) {\n return kernelSM == kSM_100f || kernelSM == kSM_100;\n }\n\n return gpuSM == kernelSM;\n}\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\nclass TllmGenFmhaKernel {\n public:\n static constexpr int kDynamicNumTokensPerPageThreshold = 128;\n static constexpr int kDynamicNumTokensPerPageKernelKey = 128;\n\n // The parameters for launching the kernel.\n // maxNumCtasQ, maxNumCtasKv, numCtasX, numCtasY, numCtasZ, clusterDimX\n struct CtaLaunchParams {\n // The maximum number of CTAs in Q dimension.\n int mMaxNumCtasQ;\n // The maximum number of CTAs in Kv dimension.\n int mMaxNumCtasKv;\n // The number of CTAs in X dimension.\n int mNumCtasX;\n // The number of CTAs in Y dimension.\n int mNumCtasY;\n // The number of CTAs in Z dimension.\n int mNumCtasZ;\n // The cluster size in the X dimension.\n int mClusterDimX;\n };\n\n public:\n using KernelMeta = tensorrt_llm::kernels::TllmGenFmhaKernelMetaInfo;\n using RunnerParams = TllmGenFmhaRunnerParams;\n using SelectKernelParams = TllmGenSelectKernelParams;\n\n // Ctor.\n TllmGenFmhaKernel(KernelMeta const* pMetaStart, unsigned int nMetaCount, Data_type dtypeQ,\n Data_type dtypeK, Data_type dtypeV, Data_type dtypeOut, unsigned int smArch,\n int numEltsPerSageAttnBlkQ = 0, int numEltsPerSageAttnBlkK = 0,\n int numEltsPerSageAttnBlkP = 0, int numEltsPerSageAttnBlkV = 0)\n : mDtypeQ(dtypeQ),\n mDtypeK(dtypeK),\n mDtypeV(dtypeV),\n mDtypeOut(dtypeOut),\n mNumEltsPerSageAttnBlkQ(numEltsPerSageAttnBlkQ),\n mNumEltsPerSageAttnBlkK(numEltsPerSageAttnBlkK),\n mNumEltsPerSageAttnBlkP(numEltsPerSageAttnBlkP),\n mNumEltsPerSageAttnBlkV(numEltsPerSageAttnBlkV),\n mKernelMeta(pMetaStart),\n mKernelMetaCount(nMetaCount),\n mSM(smArch),\n mMaxDeviceSmemSize(queryMaxDeviceSmemSize(smArch)) {}\n\n static constexpr unsigned int kSmemOptInThreshold = 48 * 1024;\n static constexpr unsigned int kRubinLegacySmemCap = 228 * 1024;\n static constexpr unsigned int kStaticSmemReserve = 1024;\n\n static bool isRubinOversized(unsigned int sm, unsigned int sharedMemBytes) {\n return sm == kSM_107 && (sharedMemBytes + kStaticSmemReserve > kRubinLegacySmemCap);\n }\n\n void setupKernelSmem(CUfunction func, KernelMeta const& kernelMeta) const {\n // CU_FUNC_ATTRIBUTE_SHARED_MEMORY_MODE and the ALLOW_OVERSIZED enum value require\n // CUDA >= 13.4; CUDA 13.3 only ships the launch-attribute half of this API.\n#if CUDA_VERSION >= 13040\n if (isRubinOversized(mSM, kernelMeta.mSharedMemBytes)) {\n cuErrCheck(cuFuncSetAttribute(func, CU_FUNC_ATTRIBUTE_SHARED_MEMORY_MODE,\n CU_SHARED_MEMORY_MODE_ALLOW_OVERSIZED_SHARED_MEMORY));\n return;\n }\n#endif\n if (kernelMeta.mSharedMemBytes >= kSmemOptInThreshold) {\n cuErrCheck(cuFuncSetAttribute(func, CU_FUNC_ATTRIBUTE_MAX_DYNAMIC_SHARED_SIZE_BYTES,\n kernelMeta.mSharedMemBytes));\n }\n }\n\n void appendOversizedSmemLaunchAttr(CUlaunchAttribute* launch_attribute,\n CUlaunchConfig& launch_config,\n KernelMeta const& kernelMeta) const {\n#if CUDA_VERSION >= 13040\n if (isRubinOversized(mSM, kernelMeta.mSharedMemBytes)) {\n IKL_LOG_DEBUG(\n \"TRTLLM-Gen launch info: using oversized shared memory for kernel %s (smem=%u bytes)\",\n kernelMeta.mFuncName, kernelMeta.mSharedMemBytes);\n launch_attribute[launch_config.numAttrs].id = CU_LAUNCH_ATTRIBUTE_SHARED_MEMORY_MODE;\n launch_attribute[launch_config.numAttrs].value.sharedMemoryMode =\n CU_SHARED_MEMORY_MODE_ALLOW_OVERSIZED_SHARED_MEMORY;\n launch_config.numAttrs += 1;\n }\n#endif\n }\n\n static unsigned int queryMaxDeviceSmemSize(unsigned int smArch) {\n CUdevice device;\n cuErrCheck(cuCtxGetDevice(&device));\n int smem_bytes = 0;\n#if CUDA_VERSION >= 13040\n if (smArch == kSM_107) {\n cuErrCheck(cuDeviceGetAttribute(\n &smem_bytes, CU_DEVICE_ATTRIBUTE_MAX_OVERSIZED_SHARED_MEMORY_PER_BLOCK, device));\n return static_cast<unsigned int>(smem_bytes);\n }\n#endif\n cuErrCheck(cuDeviceGetAttribute(&smem_bytes,\n CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_BLOCK_OPTIN, device));\n return static_cast<unsigned int>(smem_bytes);\n }\n\n void loadKernels() {\n for (unsigned int i = 0; i < mKernelMetaCount; ++i) {\n auto const& kernelMeta = mKernelMeta[i];\n IKL_LOG_DEBUG(\"Checking tllmgen attention kernel %s\", kernelMeta.mFuncName);\n if (kernelMeta.mSharedMemBytes + kStaticSmemReserve > mMaxDeviceSmemSize) {\n continue;\n }\n if (isSMCompatible(mSM, kernelMeta.mSM) && kernelMeta.mDataTypeQ == mDtypeQ &&\n kernelMeta.mDataTypeK == mDtypeK && kernelMeta.mDataTypeV == mDtypeV &&\n kernelMeta.mDataTypeO == mDtypeOut &&\n kernelMeta.mNumEltsPerSageAttnBlkQ == mNumEltsPerSageAttnBlkQ &&\n kernelMeta.mNumEltsPerSageAttnBlkK == mNumEltsPerSageAttnBlkK &&\n kernelMeta.mNumEltsPerSageAttnBlkP == mNumEltsPerSageAttnBlkP &&\n kernelMeta.mNumEltsPerSageAttnBlkV == mNumEltsPerSageAttnBlkV) {\n // Store metadata for later use.\n IKL_LOG_DEBUG(\"Adding tllmgen attention kernel %s\", kernelMeta.mFuncName);\n // Check for hash conflicts.\n uint64_t hash = hashID(kernelMeta);\n if (mKernelMetaMap.find(hash) != mKernelMetaMap.end()) {\n // The kernelMeta of the existing kernel.\n auto const& existingKernelMeta = mKernelMeta[mKernelMetaMap.at(hash)];\n FLASHINFER_CHECK(isFamilySpecificSMPair(existingKernelMeta.mSM, kernelMeta.mSM),\n \"Hash conflicts exist between %s and %s.\", existingKernelMeta.mFuncName,\n kernelMeta.mFuncName);\n\n // Prefer specific SM version over family version (replace if existing is family).\n if (existingKernelMeta.mSM == kSM_100f) {\n mKernelMetaMap[hash] = i;\n }\n } else {\n mKernelMetaMap[hash] = i;\n }\n }\n }\n }\n\n size_t getNumLoadedKernels() const { return mKernelMetaMap.size(); }\n\n inline int getBf16QFp8KvTransformMode(bool enablesKOnlyTransform,\n bool separateTransformedKv) const {\n FLASHINFER_CHECK(!(enablesKOnlyTransform && separateTransformedKv),\n \"BF16Q FP8KV transform mode cannot be both K-only and separate K/V.\");\n if (enablesKOnlyTransform) {\n return static_cast<int>(Bf16QFp8KvTransformMode::KOnly);\n }\n if (separateTransformedKv) {\n return static_cast<int>(Bf16QFp8KvTransformMode::SeparateKv);\n }\n return static_cast<int>(Bf16QFp8KvTransformMode::Full);\n }\n\n inline bool isBf16QFp8KvGeneration() const {\n return mDtypeQ == DATA_TYPE_BF16 && mDtypeK == DATA_TYPE_E4M3 && mDtypeV == DATA_TYPE_E4M3 &&\n mDtypeOut == DATA_TYPE_BF16;\n }\n\n inline bool supportsGqaGroupingTokensHeadsQ(SelectKernelParams const& selectKernelParams) const {\n return mDtypeQ == mDtypeK ||\n (isBf16QFp8KvGeneration() &&\n selectKernelParams.mBf16QFp8KvTransformMode != Bf16QFp8KvTransformMode::Full);\n }\n\n inline uint64_t hashID(int qkvLayout, int maskType, int kernelType, int scheduler,\n int multiCtasKvMode, int headDimPerCtaV, int headDimQk, int headDimV,\n int tileSizeQ, int tileSizeKv, int numTokensPerPage,\n bool dynamicNumTokensPerPage, bool reuseSmemKForV, bool uses2CtaMma,\n bool groupsTokensHeadsQ, int sparseMlaType, bool skipsSoftmax,\n int bf16QFp8KvTransformMode, bool uses2QSlidingWindowKernel,\n bool fp16Softmax, bool usesSpcompress) const {\n FLASHINFER_CHECK((headDimPerCtaV >= 32) && (headDimQk >= 32) && (headDimV >= 32) &&\n (headDimPerCtaV <= 1024) && (headDimQk <= 1024) && (headDimV <= 1024),\n \"Expect (32 <= headDim <= 1024), got headDimPerCtaV=%d, headDimQk=%d, \"\n \"headDimV=%d\",\n headDimPerCtaV, headDimQk, headDimV);\n // The numTokensPerPage must be 0 (unused for non-paged kernels) or power of 2.\n FLASHINFER_CHECK(numTokensPerPage == 0 || ((numTokensPerPage & (numTokensPerPage - 1)) == 0),\n \"The numTokensPerPage must be 0 or power of 2.\");\n FLASHINFER_CHECK(tileSizeQ <= 128 && tileSizeKv <= 128,\n \"The tileSizeQ and tileSizeKv must be <= 128.\");\n FLASHINFER_CHECK((tileSizeQ & (tileSizeQ - 1)) == 0 && (tileSizeKv & (tileSizeKv - 1)) == 0,\n \"The tileSizeQ and tileSizeKv must be power of 2.\");\n FLASHINFER_CHECK(tileSizeKv == 64 || tileSizeKv == 128, \"The tileSizeKv must be 64 or 128.\");\n FLASHINFER_CHECK(sparseMlaType >= 0 && sparseMlaType <= 3,\n \"The sparse MLA type must fit in 2 bits.\");\n FLASHINFER_CHECK(bf16QFp8KvTransformMode >= 0 && bf16QFp8KvTransformMode <= 2,\n \"The BF16Q FP8KV transform mode must fit in 2 bits.\");\n // The enum fields are packed tightly, so an out-of-range value would alias onto its neighbour\n // instead of producing a distinct key. Check them rather than trusting the exporter.\n uint64_t const numTokensPerPageLog2 =\n numTokensPerPage == 0 ? 0 : static_cast<uint64_t>(log2(numTokensPerPage));\n FLASHINFER_CHECK(qkvLayout >= 0 && qkvLayout < 4 && maskType >= 0 && maskType < 8 &&\n kernelType >= 0 && kernelType < 8 && scheduler >= 0 && scheduler < 4 &&\n multiCtasKvMode >= 0 && multiCtasKvMode < 4 &&\n bf16QFp8KvTransformMode >= 0 && bf16QFp8KvTransformMode < 4 &&\n numTokensPerPageLog2 < 16,\n \"Kernel attribute out of range for the hash key: qkvLayout=%d, maskType=%d, \"\n \"kernelType=%d, tileScheduler=%d, multiCtasKvMode=%d, \"\n \"bf16QFp8KvTransformMode=%d, numTokensPerPage=%d\",\n qkvLayout, maskType, kernelType, scheduler, multiCtasKvMode,\n bf16QFp8KvTransformMode, numTokensPerPage);\n // Format of the hash key. The enum fields are packed to their actual width rather than a\n // round 4 bits, which is what makes room for fp16Softmax and usesSpcompress; the key is a\n // private lookup key (nothing persists it), so the layout can move as long as\n // hashID(KernelMeta) and hashFromRunnerParams() move with it.\n // Bit 0 - 1 : qkvLayout.\n // Bit 2 - 4 : maskType.\n // Bit 5 - 7 : kernelType.\n // Bit 8 - 9 : tileScheduler.\n // Bit 10 - 11: multiCtasKvMode.\n // Bit 12 - 19: (headDimPerCtaV >> 3).\n // Bit 20 - 27: (headDimQk >> 3).\n // Bit 28 - 35: (headDimV >> 3).\n // Bit 36 - 37: (tileSizeKv >> 6).\n // Bit 38 - 41: (log2(numTokensPerPage)).\n // Bit 42 - 44: (log2(tileSizeQ)).\n // Bit 45 - 45: reuseSmemKForV.\n // Bit 46 - 46: uses2CtaMma.\n // Bit 47 - 48: sparseMlaType (0=none, 1=static token sparse, 2=dynamic token sparse).\n // Bit 49 - 49: skipsSoftmax.\n // Bit 50 - 50: dynamicNumTokensPerPage.\n // Bit 51 - 52: BF16Q FP8KV transform mode (0=full, 1=K-only, 2=separate K/V).\n // Bit 53 - 53: groupsTokensHeadsQ.\n // Bit 54 - 54: uses2QSlidingWindowKernel (Keeps generation 2Qx1KV SlidingWindowCustom).\n // Bit 55 - 55: fp16Softmax.\n // Bit 56 - 56: usesSpcompress.\n // Bit 57 - 63: unused.\n return (static_cast<uint64_t>(qkvLayout) << 0) | (static_cast<uint64_t>(maskType) << 2) |\n (static_cast<uint64_t>(kernelType) << 5) | (static_cast<uint64_t>(scheduler) << 8) |\n (static_cast<uint64_t>(multiCtasKvMode) << 10) |\n (static_cast<uint64_t>(headDimPerCtaV >> 3) << 12) |\n (static_cast<uint64_t>(headDimQk >> 3) << 20) |\n (static_cast<uint64_t>(headDimV >> 3) << 28) |\n (static_cast<uint64_t>(tileSizeKv >> 6) << 36) | (numTokensPerPageLog2 << 38) |\n (static_cast<uint64_t>(log2(tileSizeQ)) << 42) |\n (static_cast<uint64_t>(reuseSmemKForV) << 45) |\n (static_cast<uint64_t>(uses2CtaMma) << 46) |\n (static_cast<uint64_t>(sparseMlaType) << 47) |\n (static_cast<uint64_t>(skipsSoftmax) << 49) |\n (static_cast<uint64_t>(dynamicNumTokensPerPage) << 50) |\n (static_cast<uint64_t>(bf16QFp8KvTransformMode) << 51) |\n (static_cast<uint64_t>(groupsTokensHeadsQ) << 53) |\n (static_cast<uint64_t>(uses2QSlidingWindowKernel) << 54) |\n (static_cast<uint64_t>(fp16Softmax) << 55) |\n (static_cast<uint64_t>(usesSpcompress) << 56);\n }\n\n inline bool is2QSlidingWindowKernel(KernelMeta const& kernelMeta) const {\n return kernelMeta.mKernelType == static_cast<int>(FmhaKernelType::KeepsMmaAbForGeneration) &&\n kernelMeta.mGroupsTokensHeadsQ && kernelMeta.mStepQ == 2 * kernelMeta.mTileSizeQ;\n }\n\n inline bool isDynamicNumTokensPerPageKernel(KernelMeta const& kernelMeta) const {\n return kernelMeta.mNumTokensPerPage == kDynamicNumTokensPerPageKernelKey &&\n std::strstr(kernelMeta.mFuncName, \"P128\") == nullptr;\n }\n\n uint64_t hashID(KernelMeta const& kernelMeta) const {\n return hashID(\n kernelMeta.mQkvLayout, kernelMeta.mMaskType, kernelMeta.mKernelType,\n kernelMeta.mTileScheduler, kernelMeta.mMultiCtasKvMode, kernelMeta.mHeadDimPerCtaV,\n kernelMeta.mHeadDimQk, kernelMeta.mHeadDimV, kernelMeta.mTileSizeQ, kernelMeta.mTileSizeKv,\n kernelMeta.mNumTokensPerPage, isDynamicNumTokensPerPageKernel(kernelMeta),\n kernelMeta.mReuseSmemKForV, kernelMeta.m2CtaMma, kernelMeta.mGroupsTokensHeadsQ,\n kernelMeta.mSparseAttn, kernelMeta.mSkipsSoftmaxWhenPossible,\n getBf16QFp8KvTransformMode(kernelMeta.mEnablesBf16QFp8KvKOnlyTransform,\n kernelMeta.mSeparateTransformedKv),\n is2QSlidingWindowKernel(kernelMeta), kernelMeta.mFp16Softmax, kernelMeta.mUsesSpcompress);\n }\n\n std::pair<bool, std::string> checkIfKernelExist(RunnerParams const& params) const {\n // The selectKernelParams that might be updated.\n SelectKernelParams selectKernelParams{params};\n // Select the kernel.\n selectKernel(params, selectKernelParams);\n // Hash the runner params.\n auto [hashId, info] = hashFromRunnerParams(params, selectKernelParams);\n return std::make_pair(mKernelMetaMap.find(hashId) != mKernelMetaMap.end(), info);\n }\n\n // start here\n void run(RunnerParams const& params) const {\n SelectKernelParams selectKernelParams{params};\n CtaLaunchParams ctaLaunchParams;\n\n // Kernel selection loop (bounded). Each pass may update selectKernelParams (e.g. switch\n // MultiCtasKvMode to Disabled, upgrade to CgaSmemReduction, or reduce headDimPerCtaV) and\n // request a re-select via mSelectNewKernel. Each trigger fires at most once, so the sequence\n // converges in at most kMaxKernelSelectionPasses passes.\n static constexpr int kMaxKernelSelectionPasses = 4;\n CUfunction func{};\n KernelMeta kernelMeta{};\n for (int pass = 0; pass < kMaxKernelSelectionPasses; ++pass) {\n selectKernel(params, selectKernelParams);\n std::tie(func, kernelMeta) = loadKernel(params, selectKernelParams);\n computeCtaAndClusterConfig(ctaLaunchParams, params, kernelMeta, selectKernelParams);\n if (!selectKernelParams.mSelectNewKernel) {\n break;\n }\n FLASHINFER_CHECK(pass + 1 < kMaxKernelSelectionPasses,\n \"trtllm-gen kernel selection did not converge in %d passes.\",\n kMaxKernelSelectionPasses);\n }\n\n // Prepare the kernel parameters.\n auto kernelParams = KernelParams::setKernelParams(\n params, kernelMeta, ctaLaunchParams.mMaxNumCtasQ, ctaLaunchParams.mMaxNumCtasKv);\n\n // Override SageAttention parameters.\n auto sageParamEncode = [](int blockSize) -> int32_t {\n FLASHINFER_CHECK((blockSize & (blockSize - 1)) == 0,\n \"SageAttention block size must be a power of 2.\");\n return blockSize == 0 ? 0 : __builtin_ctz(static_cast<unsigned int>(blockSize));\n };\n kernelParams.ptrSageAttnSfsQ = params.ptrSageAttnSfsQ;\n kernelParams.ptrSageAttnSfsK = params.ptrSageAttnSfsK;\n kernelParams.ptrSageAttnSfsP = params.ptrSageAttnSfsP;\n kernelParams.ptrSageAttnSfsV = params.ptrSageAttnSfsV;\n kernelParams.mLogNumEltsPerSageAttnBlkQ = sageParamEncode(kernelMeta.mNumEltsPerSageAttnBlkQ);\n kernelParams.mLogNumEltsPerSageAttnBlkK = sageParamEncode(kernelMeta.mNumEltsPerSageAttnBlkK);\n kernelParams.mLogNumEltsPerSageAttnBlkP = sageParamEncode(kernelMeta.mNumEltsPerSageAttnBlkP);\n kernelParams.mLogNumEltsPerSageAttnBlkV = sageParamEncode(kernelMeta.mNumEltsPerSageAttnBlkV);\n\n void* kernelParamsList[] = {&kernelParams};\n CUlaunchAttribute launch_attribute[4] = {};\n CUlaunchConfig launch_config;\n buildLaunchConfig(launch_config, launch_attribute, kernelMeta, ctaLaunchParams, params);\n\n // Debug info.\n IKL_LOG_DEBUG(\n \"TRTLLM-Gen launch info (in TllmGenFmhaKernel %s, %s, %s, %s, %d): kernelName = %s\",\n toStr(mDtypeQ), toStr(mDtypeK), toStr(mDtypeV), toStr(mDtypeOut), mSM,\n kernelMeta.mFuncName);\n IKL_LOG_DEBUG(\n \"TRTLLM-Gen launch info: maxSeqLenQ = %d, \"\n \"maxSeqLenKv = %d, \"\n \"numHeadsQ = %d, \"\n \"numHeadsKv = %d, batchSize = %d, kernelType = %d\",\n params.mMaxSeqLenQ, params.mMaxSeqLenKv, params.mNumHeadsQ, params.mNumHeadsKv,\n params.mBatchSize, static_cast<int>(params.mKernelType));\n IKL_LOG_DEBUG(\n \"TRTLLM-Gen launch info: numCtasX = %d, numCtasY = %d, numCtasZ = %d, clusterDimX = %d\",\n ctaLaunchParams.mNumCtasX, ctaLaunchParams.mNumCtasY, ctaLaunchParams.mNumCtasZ,\n ctaLaunchParams.mClusterDimX);\n\n setNonPortableClusterIfNeeded(func, ctaLaunchParams);\n\n // Force GmemReduction if CgaSmemReduction would need more than one wave (cluster occupancy\n // limit). TODO: find a better heuristic of using CgaSmemReduction.\n if (isCgaSmemReduction(selectKernelParams.mMultiCtasKvMode)) {\n int maxActiveClusters = 1;\n cuErrCheck(cuOccupancyMaxActiveClusters(&maxActiveClusters, func, &launch_config));\n if (maxActiveClusters * ctaLaunchParams.mClusterDimX <\n ctaLaunchParams.mNumCtasX * ctaLaunchParams.mNumCtasY * ctaLaunchParams.mNumCtasZ) {\n selectKernelParams.mForceGmemReduction = true;\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::GmemReduction;\n selectKernel(params, selectKernelParams);\n std::tie(func, kernelMeta) = loadKernel(params, selectKernelParams);\n computeCtaAndClusterConfig(ctaLaunchParams, params, kernelMeta, selectKernelParams);\n FLASHINFER_CHECK(!selectKernelParams.mSelectNewKernel,\n \"trtllm-gen kernel selection did not converge after CgaSmemReduction \"\n \"fallback to GmemReduction.\");\n // Rebuild kernelParams: setKernelParams uses kernelMeta (TMA descriptors, tile shapes)\n // which changed when switching from CgaSmemReduction to GmemReduction kernel.\n kernelParams = KernelParams::setKernelParams(\n params, kernelMeta, ctaLaunchParams.mMaxNumCtasQ, ctaLaunchParams.mMaxNumCtasKv);\n buildLaunchConfig(launch_config, launch_attribute, kernelMeta, ctaLaunchParams, params);\n setNonPortableClusterIfNeeded(func, ctaLaunchParams);\n }\n }\n\n cuErrCheck(cuLaunchKernelEx(&launch_config, func, kernelParamsList, nullptr));\n\n // Run the separate reduction kernel if needed.\n tensorrt_llm::kernels::runFmhaReduction(kernelMeta, kernelParams, params.mMultiProcessorCount,\n params.enable_pdl, params.stream);\n\n if (params.lsePtr != nullptr) {\n FLASHINFER_CUDA_CHECK(flashinfer::ComputeLSEFromMD(\n params.softmaxStatsPtr, params.lsePtr, params.mSumOfSeqLensQ, params.mNumHeadsQ,\n params.lseStrideTokens, params.lseStrideHeads, params.enable_pdl, params.stream));\n }\n }\n\n private:\n // Fill a CUlaunchConfig and its associated attribute array from the current kernel and CTA\n // params. The caller owns the storage for launch_attribute (must be an array of at least 3\n // elements) and is responsible for ensuring it outlives launch_config.\n void buildLaunchConfig(CUlaunchConfig& launch_config, CUlaunchAttribute* launch_attribute,\n KernelMeta const& kernelMeta, CtaLaunchParams const& ctaLaunchParams,\n RunnerParams const& params) const {\n launch_config.blockDimX = kernelMeta.mThreadsPerCTA;\n launch_config.blockDimY = 1;\n launch_config.blockDimZ = 1;\n launch_config.gridDimX = ctaLaunchParams.mNumCtasX;\n launch_config.gridDimY = ctaLaunchParams.mNumCtasY;\n launch_config.gridDimZ = ctaLaunchParams.mNumCtasZ;\n launch_config.hStream = params.stream;\n launch_config.sharedMemBytes = kernelMeta.mSharedMemBytes;\n launch_attribute[0].id = CU_LAUNCH_ATTRIBUTE_CLUSTER_DIMENSION;\n launch_attribute[0].value.clusterDim.x = ctaLaunchParams.mClusterDimX;\n launch_attribute[0].value.clusterDim.y = 1;\n launch_attribute[0].value.clusterDim.z = 1;\n launch_attribute[1].id = CU_LAUNCH_ATTRIBUTE_CLUSTER_SCHEDULING_POLICY_PREFERENCE;\n launch_attribute[1].value.clusterSchedulingPolicyPreference =\n ctaLaunchParams.mClusterDimX > 1 ? CU_CLUSTER_SCHEDULING_POLICY_SPREAD\n : CU_CLUSTER_SCHEDULING_POLICY_DEFAULT;\n launch_attribute[2].id = CU_LAUNCH_ATTRIBUTE_PROGRAMMATIC_STREAM_SERIALIZATION;\n launch_attribute[2].value.programmaticStreamSerializationAllowed = params.enable_pdl;\n launch_config.attrs = launch_attribute;\n launch_config.numAttrs = 3;\n appendOversizedSmemLaunchAttr(launch_attribute, launch_config, kernelMeta);\n }\n\n // Enable non-portable cluster sizes when clusterDimX exceeds the portable limit of 8.\n void setNonPortableClusterIfNeeded(CUfunction func,\n CtaLaunchParams const& ctaLaunchParams) const {\n if (ctaLaunchParams.mClusterDimX > 8) {\n cuErrCheck(cuFuncSetAttribute(func, CU_FUNC_ATTRIBUTE_NON_PORTABLE_CLUSTER_SIZE_ALLOWED,\n 1 // Enable non-portable cluster sizes\n ));\n }\n }\n\n // Is it MLA generation kernel ?\n inline bool isMlaGenKernel(RunnerParams const& params) const {\n return (params.mHeadDimQk == 576 && params.mHeadDimV == 512) ||\n (params.mHeadDimQk == 320 && params.mHeadDimV == 256) ||\n (isSparseMla(params.mSparseMlaType) && params.mHeadDimQk == 512 &&\n params.mHeadDimV == 512);\n }\n\n inline bool useDynamicNumTokensPerPage(RunnerParams const& params) const {\n return isPagedKv(params.mQkvLayout) && !isSparseMla(params.mSparseMlaType) &&\n params.mHeadDimQk == params.mHeadDimV &&\n params.mNumTokensPerPage >= kDynamicNumTokensPerPageThreshold;\n }\n\n void selectNumTokensPerPage(RunnerParams const& params,\n SelectKernelParams& selectKernelParams) const {\n selectKernelParams.mDynamicNumTokensPerPage = false;\n if (isSparseMla(params.mSparseMlaType)) {\n // SparseMla kernels use a fixed numTokensPerPage = 1.\n selectKernelParams.mNumTokensPerPage = 1;\n } else if (!isPagedKv(params.mQkvLayout)) {\n // NumTokensPerPage is set to 0 when not selecting pagedKv-layout kernels.\n selectKernelParams.mNumTokensPerPage = 0;\n } else if (useDynamicNumTokensPerPage(params)) {\n FLASHINFER_CHECK((params.mNumTokensPerPage & (params.mNumTokensPerPage - 1)) == 0,\n \"Dynamic numTokensPerPage requires a power-of-2 page size, got %d.\",\n params.mNumTokensPerPage);\n selectKernelParams.mDynamicNumTokensPerPage = true;\n selectKernelParams.mNumTokensPerPage = kDynamicNumTokensPerPageKernelKey;\n } else {\n selectKernelParams.mNumTokensPerPage = params.mNumTokensPerPage;\n }\n }\n\n bool hasCgaSmemReductionKernel(RunnerParams const& params,\n SelectKernelParams selectKernelParams) const {\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::CgaSmemReduction;\n auto const hashId = hashFromRunnerParams(params, selectKernelParams).first;\n return mKernelMetaMap.find(hashId) != mKernelMetaMap.end();\n }\n\n // Compute the number of CTAs in X, Y and Z dimension and the cluster size in the X dimension.\n void computeCtaAndClusterConfig(CtaLaunchParams& ctaLaunchParams, RunnerParams const& params,\n KernelMeta const& kernelMeta,\n SelectKernelParams& selectKernelParams) const {\n bool isDsv3MinLatencyMode = params.mBatchSize == 1 && params.mMaxSeqLenQ >= 1 &&\n params.mMaxSeqLenQ <= 16 && params.mHeadDimQk == 576 &&\n params.mHeadDimV == 512;\n // Do we need to select a new kernel ?\n selectKernelParams.mSelectNewKernel = false;\n\n // The number of Ctas per Q sequence.\n int numCtasPerSeqQ = (params.mMaxSeqLenQ + kernelMeta.mStepQ - 1) / kernelMeta.mStepQ;\n // The generation-phase kernels might need to group both tokensQ and headsQ into one CTA.\n if (params.mMaxSeqLenQ > 1 && !isContextKernel(params.mKernelType)) {\n // Each CTA handles one tokenQ by default for spec-decoding generation kernel.\n if (!kernelMeta.mGroupsTokensHeadsQ) {\n numCtasPerSeqQ = params.mMaxSeqLenQ;\n } else {\n // Compute numTokensPerCtaQ where each CTA must process complete numGroupedHeadsQ.\n // Note that each CTA must process complete numHeadsQPerKv.\n int numTokensPerCtaQ = std::max(1, kernelMeta.mStepQ / params.mNumHeadsQPerKv);\n // Group both headsQ and tokensQ into one CTA.\n numCtasPerSeqQ = flashinfer::ceil_div(params.mMaxSeqLenQ, numTokensPerCtaQ);\n }\n }\n\n // Compute the grid dimension Y.\n int numHeadsPerCta =\n kernelMeta.mGroupsHeadsQ ? std::min(params.mNumHeadsQPerKv, kernelMeta.mStepQ) : 1;\n int numCtasForAllHeadsQ = params.mNumHeadsQ / numHeadsPerCta;\n FLASHINFER_CHECK(numHeadsPerCta * numCtasForAllHeadsQ == params.mNumHeadsQ,\n \"The numHeadsQ/numHeadsKv is not supported.\");\n // Take the number of headDim CTAs.\n FLASHINFER_CHECK(kernelMeta.mHeadDimV % selectKernelParams.mHeadDimPerCtaV == 0,\n \"The headDimPerCtaV is not supported.\");\n int numCtasPerHeadDim = kernelMeta.mHeadDimV / selectKernelParams.mHeadDimPerCtaV;\n // Compute the current numCtasX.\n int numCtasX = numCtasPerSeqQ;\n // Update the numCtasY.\n int numCtasY = numCtasForAllHeadsQ * numCtasPerHeadDim;\n // Compute the grid dimension Z.\n int numCtasZ = params.mBatchSize;\n // The 2CtaMma kernels will use 2 Ctas in the x dimension (only used by MLA generation kernels)\n // for heads, so numCtasPerHeadDim and numCtasForAllHeadsQ will be handled by the 2Ctas in the x\n // dimension.\n if (isMlaGenKernel(params) && selectKernelParams.mUses2CtaMma) {\n FLASHINFER_CHECK(numCtasForAllHeadsQ == 2 && numCtasPerHeadDim == 2,\n \"Internal error: numCtasPerHeadDim should be 2.\");\n numCtasX *= 2;\n numCtasY /= (numCtasForAllHeadsQ * numCtasPerHeadDim);\n }\n\n // First split the seqLenKv into multiple CTAs if the utilization is not full.\n // The number of Ctas per KV sequence.\n int numCtasPerSeqKv = 1;\n // Consider the multiCtasKvMode for better GPU utilization.\n if (isMultiCtasKvEnabled(selectKernelParams.mMultiCtasKvMode)) {\n // The maximum attention window (the maximum number of tokensKv that will be attended to).\n int maxAttentionWindow{params.mMaxSeqLenKv};\n // The sparseMla only selects topK tokensKv.\n if (isSparseMla(params.mSparseMlaType)) {\n maxAttentionWindow = std::min(params.mMaxSeqLenKv, params.mSparseMlaTopK);\n }\n // Some of the tilesKv will be skipped if the sliding window attention or chunked attention is\n // used.\n if (isSlidingOrChunkedCausalMask(selectKernelParams.mMaskType)) {\n if (params.mMaxSeqLenKv > params.mAttentionWindowSize) {\n // Consider that the first tileKv might contain tokensKv that is out of the attention\n // window.\n maxAttentionWindow =\n std::min(params.mMaxSeqLenKv, params.mAttentionWindowSize + kernelMeta.mStepKv - 1);\n } else {\n maxAttentionWindow = std::min(params.mMaxSeqLenKv, params.mChunkedAttentionSize);\n }\n }\n\n // The maximum number Ctas per Kv sequence, which makes sure that each CtaKv has work to do.\n // The factor of 2 is applied here to ensure the reduction overhead does not outweigh the\n // benefits of a shorter mainloop.\n int const maxNumCtasPerSeqKv =\n (maxAttentionWindow + 2 * kernelMeta.mStepKv - 1) / (2 * kernelMeta.mStepKv);\n int tunedMaxNumCtasPerSeqKv = maxNumCtasPerSeqKv;\n // Cap BF16Q+FP8KV separate-transform splits so the runtime key selects\n // CGA reduction when the smaller split is expected.\n if (isBf16QFp8KvGeneration() &&\n selectKernelParams.mBf16QFp8KvTransformMode == Bf16QFp8KvTransformMode::SeparateKv &&\n isSwapsMmaAbForGenerationKernel(selectKernelParams.mKernelType) &&\n !isGmemReductionWithSeparateKernel(selectKernelParams.mMultiCtasKvMode) &&\n params.mHeadDimV < 512) {\n int const clusterDimX = selectKernelParams.mUses2CtaMma ? 2 : 1;\n int const maxKvSplitsPerCgaCluster = 16 / clusterDimX;\n if (maxNumCtasPerSeqKv <= numCtasForAllHeadsQ * maxKvSplitsPerCgaCluster) {\n int const launchedClusters =\n flashinfer::ceil_div(numCtasX, clusterDimX) * numCtasY * numCtasZ;\n int const residentSplitBudget = std::max(\n 4, flashinfer::ceil_div(params.mMultiProcessorCount * 13 / 20, launchedClusters));\n int const targetMaxNumCtasPerSeqKv =\n std::min(maxNumCtasPerSeqKv, std::min(maxKvSplitsPerCgaCluster, residentSplitBudget));\n if (targetMaxNumCtasPerSeqKv > 1 && targetMaxNumCtasPerSeqKv < maxNumCtasPerSeqKv) {\n int const targetTileSizePerCtaKv =\n isSlidingOrChunkedCausalMask(selectKernelParams.mMaskType)\n ? flashinfer::ceil_div(params.mAttentionWindowSize,\n targetMaxNumCtasPerSeqKv - 1)\n : flashinfer::ceil_div(maxAttentionWindow, targetMaxNumCtasPerSeqKv);\n if (targetTileSizePerCtaKv <= 1024) {\n tunedMaxNumCtasPerSeqKv = targetMaxNumCtasPerSeqKv;\n }\n }\n }\n }\n // Compute numCtasPerSeqKv.\n numCtasPerSeqKv = std::min(\n tunedMaxNumCtasPerSeqKv,\n std::max(1, int32_t(params.mMultiProcessorCount / (numCtasX * numCtasY * numCtasZ))));\n // Update the numCtasX.\n numCtasX *= numCtasPerSeqKv;\n // The current total number of CTAs.\n int totalNumCtas = numCtasX * numCtasZ * numCtasY;\n // Disable the multiCtasKvMode if there is only one CtaKv.\n if (numCtasPerSeqKv <= 1) {\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::Disabled;\n // Enable the persistent scheduler for better performance.\n selectKernelParams.mTileScheduler = TileScheduler::Persistent;\n // Need to select a different kernel.\n selectKernelParams.mSelectNewKernel = true;\n } else if (totalNumCtas < params.mMultiProcessorCount && isMlaGenKernel(params) &&\n !isSparseMla(params.mSparseMlaType) && selectKernelParams.mTileSizeKv == 128 &&\n getEnvUseTileSizeKv64ForTrtllmGen()) {\n // Use smaller tileSizeKv to fully utilize the SMs.\n selectKernelParams.mTileSizeKv = 64;\n // Need to select a different kernel.\n selectKernelParams.mSelectNewKernel = true;\n }\n\n // The P32 cubin inventory contains an H576/V512 CGA kernel for the split-V\n // headDimPerCtaV=128 form. Let the first selection pass split V, then use CGA for the\n // exact one-token decode shape when the matching dtype-specific cubin is registered.\n bool const useMlaH512Cga = isDsv3MinLatencyMode && params.mMaxSeqLenQ == 1 &&\n selectKernelParams.mNumTokensPerPage == 32 &&\n selectKernelParams.mHeadDimPerCtaV == 128 &&\n selectKernelParams.mTileSizeQ == 16 &&\n hasCgaSmemReductionKernel(params, selectKernelParams);\n bool const useCgaSmemReduction =\n (!isDsv3MinLatencyMode && params.mHeadDimV < 512) || useMlaH512Cga;\n\n // Enable the CgaSmemReduction if the numCtasPerSeqKv <= 16 as the maximum cluster dimension\n // is 16. Only the swapsMmaAbForGeneration kernel supports the CgaSmemReduction for now.\n // Other headDimV >= 512 shapes remain excluded because the cubin inventory is incomplete,\n // and tileSizeQ >= 32 CGA variants can exceed the device shared-memory limit.\n if (useCgaSmemReduction && numCtasPerSeqKv > 1 && numCtasPerSeqKv <= 16 &&\n isSwapsMmaAbForGenerationKernel(selectKernelParams.mKernelType) &&\n isGmemReduction(selectKernelParams.mMultiCtasKvMode) &&\n !selectKernelParams.mForceGmemReduction) {\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::CgaSmemReduction;\n // Need to select a different kernel.\n selectKernelParams.mSelectNewKernel = true;\n }\n\n // Add the debug info when multiCtasKvMode is enabled.\n if (numCtasPerSeqKv > 1) {\n IKL_LOG_DEBUG(\n \"TRTLLM-Gen launch info: multiCtasKvMode is enabled with tileSizeKv = %d, \"\n \"numCtasPerSeqKv = %d, \"\n \"numCtasPerSeqQ = \"\n \"%d, numCtasY = %d, numCtasZ = %d\",\n selectKernelParams.mTileSizeKv, numCtasPerSeqKv, numCtasPerSeqQ, numCtasY, numCtasZ);\n }\n }\n\n // The cluster size in the X dimension.\n int clusterDimX = selectKernelParams.mUses2CtaMma ? 2 : 1;\n if (isCgaSmemReduction(selectKernelParams.mMultiCtasKvMode)) {\n // Note 2CtaMma and CgaSmemReduction cannot be used together currently.\n clusterDimX *= numCtasPerSeqKv;\n }\n\n // Compute the current number of CTAs in total.\n int totalNumCtas = numCtasX * numCtasZ * numCtasY;\n\n // Then split the headDimV into multiple CTAs if there are still unused SMs.\n if (isMlaGenKernel(params) && !selectKernelParams.mGroupsTokensHeadsQ &&\n !selectKernelParams.mReuseSmemKForV && !selectKernelParams.mSelectNewKernel &&\n !selectKernelParams.mUses2CtaMma) {\n // Split the headDimV into multiple CTAs if the utilization is not full.\n // It doesn't work with reuseSmemKForV currently.\n // TODO: find better heuristic of splitting headDimV across multiple CTAs.\n\n int corrFactor = isDsv3MinLatencyMode ? 1 : 2;\n if (selectKernelParams.mHeadDimPerCtaV == 512 &&\n totalNumCtas * corrFactor <= params.mMultiProcessorCount) {\n // Use smaller headDimPerCtaV to fully utilize the SMs.\n selectKernelParams.mHeadDimPerCtaV =\n totalNumCtas * 2 * corrFactor <= params.mMultiProcessorCount ? 128 : 256;\n // Need to select a different kernel.\n selectKernelParams.mSelectNewKernel = true;\n }\n }\n\n // Update the parameters for launching the kernel.\n ctaLaunchParams.mMaxNumCtasQ = numCtasPerSeqQ;\n ctaLaunchParams.mMaxNumCtasKv = numCtasPerSeqKv;\n ctaLaunchParams.mNumCtasX = numCtasX;\n ctaLaunchParams.mNumCtasY = numCtasY;\n ctaLaunchParams.mNumCtasZ = numCtasZ;\n ctaLaunchParams.mClusterDimX = clusterDimX;\n }\n\n // Determine if we should use the SwapsMmaAbForGeneration kernel for MLA generation.\n bool useSwapsMmaAbMlaGenKernel(RunnerParams const& params) const {\n // Use the SwapsMmaAbForGeneration kernel for MLA generation when the following conditions are\n // met:\n // 1. The seqLenPerCtaKv <= 1024 based on the benchmark results (this might be fine-tuned\n // later).\n // 2. The numCtas (after splitting the heads across multiple CTAs) <=\n // params.mMultiProcessorCount.\n\n // The maximum number Ctas per Kv sequence, which makes sure that each CtaKv has work to do.\n // Here we assume the stepKv is 256.\n int const maxNumCtasPerSeqKv = flashinfer::ceil_div(params.mMaxSeqLenKv, 256);\n ;\n // The number of Ctas.\n int const numCtas = static_cast<int32_t>(params.mBatchSize * params.mMaxSeqLenQ *\n flashinfer::ceil_div(params.mNumHeadsQPerKv, 16));\n // Compute numCtasPerSeqKv.\n int const numCtasPerSeqKv =\n std::min(maxNumCtasPerSeqKv, std::max(1, int32_t(params.mMultiProcessorCount / numCtas)));\n // Compute the seqLenPerCtaKv.\n int const seqLenPerCtaKv = flashinfer::ceil_div(params.mMaxSeqLenKv, numCtasPerSeqKv);\n // Whether we should use the SwapsMmaAbForGeneration kernel for MLA generation.\n return seqLenPerCtaKv <= 1024 && numCtas <= params.mMultiProcessorCount;\n }\n\n // Return the smallest shipped MLA head tile that contains a non-power-of-two head group below\n // 64 heads. Power-of-two groups and groups with at least 128 heads return zero so callers\n // preserve their existing heuristics; the unsupported 65-127 gap has no Q128 MLA cubin.\n static int getPaddedMlaTileSizeQ(int numHeadsQPerKv) {\n FLASHINFER_CHECK(numHeadsQPerKv > 0, \"The numHeadsQPerKv must be positive, got %d.\",\n numHeadsQPerKv);\n if (numHeadsQPerKv >= 128 || (numHeadsQPerKv & (numHeadsQPerKv - 1)) == 0) {\n return 0;\n }\n FLASHINFER_CHECK(numHeadsQPerKv <= 64,\n \"Non-power-of-two MLA numHeadsQPerKv must be <= 64, got %d.\", numHeadsQPerKv);\n return std::max(8, flashinfer::UpPowerOfTwo(numHeadsQPerKv));\n }\n\n // Select the sparse MLA generation kernel.\n // Heuristics benchmarked on B200 (SM=148, sparseMlaTopK=2048).\n void selectSparseMlaGenerationKernel(RunnerParams const& params,\n SelectKernelParams& selectKernelParams) const {\n // numHeadsQ <= 32 : SwapsMmaAbForGeneration\n // Non-power-of-two head counts use one padded Q8/Q16/Q32 tile. Power-of-two head counts use\n // tileSizeQ = numHeadsQPerKv/2 for short queries at batch=1, otherwise numHeadsQPerKv.\n // Threshold: maxSeqLenQ <= 16 and batchSize * maxNumCtasPerSeqKv <= MP/8\n // (crossover at batch=1->2 on B200).\n // Short-query benchmarks (seqLenKv=8192, topK=2048): half tileSizeQ wins by 2-6% at\n // batch=1; full tileSizeQ wins by 2-11% at batch>=2.\n // numHeadsQ > 32 : KeepsMmaAbForGeneration, tileSizeQ = 64\n // numHeadsQ=128 at large batch : 2CTA (clusterDimX=2, headDimPerCtaV=256)\n // otherwise : 1CTA, headDimPerCtaV fine-tuned later\n // Note: at small batch e4m3 prefers SwapsMmaAb tileSizeQ=32 (+10%), but fp16 prefers\n // KeepsMmaAb tileSizeQ=64 (+19% at numHeadsQ=128). We keep KeepsMmaAb for numHeadsQ>=64\n // to avoid penalizing fp16.\n\n FmhaKernelType& kernelType = selectKernelParams.mKernelType;\n int& tileSizeQ = selectKernelParams.mTileSizeQ;\n\n if (params.mNumHeadsQPerKv <= 32) {\n kernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n selectKernelParams.mTileSizeKv = 128;\n // mMultiCtasKvMode defaults to GmemReduction from the constructor. computeCtaAndClusterConfig\n // may upgrade it to CgaSmemReduction; that update is preserved naturally across\n // re-selections. The base tileSizeQ is numHeadsQPerKv (one CTA covers all Q heads per token).\n // At batch=1 short queries under-utilize the GPU, so halve tileSizeQ to create 2x more\n // head-splitting CTAs. Long-query prefill already has Q-axis parallelism; halving the tile\n // duplicates the KV loads for each token.\n // Threshold: maxSeqLenQ <= 16 and batchSize * maxNumCtasPerSeqKv <= MP/8.\n // effectiveSeqLenKv = min(seqLen, topK) = 2048 -> maxNumCtasPerSeqKv = 16.\n // Condition: batchSize * 16 <= MP/8 -> batchSize <= 1 (crossover at batch=1->2).\n // Only halve when half tileSizeQ >= 8 (no valid SwapsMmaAb kernel below tileSizeQ=8).\n int const fullTileSizeQ = params.mNumHeadsQPerKv;\n int const halfTileSizeQ = fullTileSizeQ / 2;\n int const effectiveSeqLenKv = std::min(params.mMaxSeqLenKv, params.mSparseMlaTopK);\n int const maxNumCtasPerSeqKv =\n flashinfer::ceil_div(effectiveSeqLenKv, selectKernelParams.mTileSizeKv);\n bool const useHalfTileSizeQ =\n halfTileSizeQ >= 8 &&\n params.mBatchSize * maxNumCtasPerSeqKv <= params.mMultiProcessorCount / 8 &&\n params.mMaxSeqLenQ <= 16;\n tileSizeQ = useHalfTileSizeQ ? halfTileSizeQ : fullTileSizeQ;\n } else {\n // numHeadsQ > 32: use KeepsMmaAbForGeneration.\n kernelType = FmhaKernelType::KeepsMmaAbForGeneration;\n tileSizeQ = 64;\n selectKernelParams.mTileSizeKv = 128;\n // Upgrade GmemReduction (constructor default) to GmemReductionWithSeparateKernel.\n // If computeCtaAndClusterConfig already set it to Disabled (numCtasPerSeqKv==1), the\n // isGmemReduction() guard is false and the Disabled state is preserved on re-selection.\n if (isGmemReduction(selectKernelParams.mMultiCtasKvMode)) {\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::GmemReductionWithSeparateKernel;\n }\n // For numHeadsQ=128, use 2CTA when there are enough CTAs to amortize 2CTA overhead.\n // numCtasPerToken = numHeadsQPerKv / tileSizeQ (number of CTAs per token per batch item).\n // Benchmarks (fp16/e4m3, sparseMlaTopK=2048):\n // decode, s_q=1:\n // batch=1 : 1CTA wins by ~20%; batch=8 : 1CTA wins by 3-8%\n // batch=16 : 2CTA wins by 8-16%; batch=32+: 2CTA wins by 12-20%\n // prefill/spec, s_q>1, DS MLA generation:\n // 2CTA wins by ~20-50% because it avoids the 1CTA h128 path's duplicated head-dim work.\n // Threshold: batchSize * numCtasPerToken * 8 > MP -> crossover at batch ~ MP/16 ~ 9.\n int const numCtasPerToken = params.mNumHeadsQPerKv / 64;\n bool const use2CtaForMultiTokenMla = params.mMaxSeqLenQ > 1;\n bool const use2Cta = params.mNumHeadsQPerKv == 128 &&\n (use2CtaForMultiTokenMla ||\n params.mBatchSize * numCtasPerToken * 8 > params.mMultiProcessorCount);\n if (use2Cta) {\n selectKernelParams.mUses2CtaMma = true;\n selectKernelParams.mHeadDimPerCtaV = 256;\n }\n }\n // Preserve the legacy heuristic above for power-of-two groups. A non-power-of-two group must\n // fit in one padded tile because the final head CTA cannot process a partial tile.\n if (int const paddedTileSizeQ = getPaddedMlaTileSizeQ(params.mNumHeadsQPerKv);\n paddedTileSizeQ != 0) {\n tileSizeQ = paddedTileSizeQ;\n }\n }\n\n inline bool usesGroupedMlaGenerationKernel(RunnerParams const& params) const {\n bool const usesSupportedDtypes = (mDtypeQ == DATA_TYPE_BF16 && mDtypeK == DATA_TYPE_BF16 &&\n mDtypeV == DATA_TYPE_BF16 && mDtypeOut == DATA_TYPE_BF16) ||\n (mDtypeQ == DATA_TYPE_E4M3 && mDtypeK == DATA_TYPE_E4M3 &&\n mDtypeV == DATA_TYPE_E4M3 && mDtypeOut == DATA_TYPE_BF16);\n bool const usesSupportedHeadRatio =\n params.mNumHeadsQPerKv == 8 || params.mNumHeadsQPerKv == 16 || params.mNumHeadsQPerKv == 32;\n\n return !isSparseMla(params.mSparseMlaType) && params.mMaxSeqLenQ > 1 &&\n usesSupportedHeadRatio && params.mBatchSize >= 1 && params.mBatchSize <= 16 &&\n params.mNumTokensPerPage == 32 && params.mHeadDimQk == 576 && params.mHeadDimV == 512 &&\n usesSupportedDtypes;\n }\n\n // Grouped MLA generation packs query tokens and local Q heads into Q64 CTAs.\n void selectGroupedMlaGenerationKernel(RunnerParams const& params,\n SelectKernelParams& selectKernelParams) const {\n selectKernelParams.mKernelType = FmhaKernelType::KeepsMmaAbForGeneration;\n selectKernelParams.mTileSizeQ = 64;\n selectKernelParams.mTileSizeKv = 128;\n // Preserve Disabled/Persistent selected by an earlier low-KV pass.\n if (isMultiCtasKvEnabled(selectKernelParams.mMultiCtasKvMode)) {\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::GmemReductionWithSeparateKernel;\n selectKernelParams.mTileScheduler = TileScheduler::Static;\n }\n selectKernelParams.mForceGmemReduction = true;\n selectKernelParams.mMaskType = TrtllmGenAttentionMaskType::Dense;\n selectKernelParams.mReuseSmemKForV = false;\n selectKernelParams.mGroupsTokensHeadsQ = true;\n selectKernelParams.mUses2CtaMma = false;\n\n int const groupedRows = params.mMaxSeqLenQ * params.mNumHeadsQPerKv;\n int const baseNumCtas =\n params.mBatchSize * params.mNumHeadsKv * flashinfer::ceil_div(groupedRows, 64);\n if (baseNumCtas <= 1) {\n selectKernelParams.mHeadDimPerCtaV = 128;\n } else if (baseNumCtas <= 4) {\n selectKernelParams.mHeadDimPerCtaV = 256;\n } else {\n selectKernelParams.mHeadDimPerCtaV = 512;\n }\n selectKernelParams.mHeadDimPerCtaV =\n std::min(selectKernelParams.mHeadDimPerCtaV, params.mHeadDimV);\n }\n\n // Select the MLA generation kernel.\n void selectMlaGenerationKernel(RunnerParams const& params,\n SelectKernelParams& selectKernelParams) const {\n if (usesGroupedMlaGenerationKernel(params)) {\n selectGroupedMlaGenerationKernel(params, selectKernelParams);\n return;\n }\n selectKernelParams.mGroupsTokensHeadsQ = false;\n\n // The kernel type.\n FmhaKernelType& kernelType = selectKernelParams.mKernelType;\n // The tile size for Q.\n int& tileSizeQ = selectKernelParams.mTileSizeQ;\n\n if (isSparseMla(params.mSparseMlaType)) {\n selectSparseMlaGenerationKernel(params, selectKernelParams);\n } else {\n int const paddedTileSizeQ = getPaddedMlaTileSizeQ(params.mNumHeadsQPerKv);\n // Non-sparse MLA: use SwapsMmaAb when numHeadsQPerKv <= 32 or seqLenPerCtaKv is small.\n // Padded Q64 must use KeepsMmaAb so split-KV also follows its standalone-reducer path.\n bool const useSwapsMmaAb =\n paddedTileSizeQ != 0 ? paddedTileSizeQ <= 32\n : params.mNumHeadsQPerKv <= 32 || useSwapsMmaAbMlaGenKernel(params);\n\n if (useSwapsMmaAb) {\n kernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n tileSizeQ = paddedTileSizeQ != 0 ? paddedTileSizeQ : (params.mNumHeadsQPerKv <= 8 ? 8 : 16);\n } else {\n kernelType = FmhaKernelType::KeepsMmaAbForGeneration;\n tileSizeQ = 64;\n // Always use the separate reduction kernel.\n if (isMultiCtasKvEnabled(selectKernelParams.mMultiCtasKvMode)) {\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::GmemReductionWithSeparateKernel;\n }\n // For non-sparse MLA, always use 2CTA for numHeadsQPerKv=128 (legacy behavior).\n if (params.mNumHeadsQPerKv == 128) {\n selectKernelParams.mUses2CtaMma = true;\n selectKernelParams.mHeadDimPerCtaV = 256;\n }\n }\n }\n }\n\n void syncGqaGenerationTraitsForKernelHash(RunnerParams const& params,\n SelectKernelParams& selectKernelParams) const {\n // Same-dtype GQA generation cubins export this trait for every tile size, including runtime\n // shapes where the resulting CTA covers only one query token.\n selectKernelParams.mGroupsTokensHeadsQ = true;\n bool const multiCtasKvEnabled = isMultiCtasKvEnabled(selectKernelParams.mMultiCtasKvMode);\n if (selectKernelParams.mKernelType == FmhaKernelType::KeepsMmaAbForGeneration &&\n params.mHeadDimV > 256) {\n // Current GQA keepsMmaAb H512 cubins are registered in the split-V\n // headDimPerCtaV=256 form; full-V H512 is a cubin coverage follow-up.\n selectKernelParams.mHeadDimPerCtaV = 256;\n if (multiCtasKvEnabled) {\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::GmemReductionWithSeparateKernel;\n }\n } else {\n // SwapsMmaAb hashes the full-V form; undo a previous keepsMmaAb separate-reduction upgrade\n // when the tile-size cost model walks back to swapsMmaAb.\n selectKernelParams.mHeadDimPerCtaV = params.mHeadDimV;\n if (multiCtasKvEnabled &&\n selectKernelParams.mMultiCtasKvMode == MultiCtasKvMode::GmemReductionWithSeparateKernel) {\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::GmemReduction;\n }\n }\n }\n\n // Selects a heuristic tileSizeQ if groupsTokensHeadsQ is true.\n void selectTileSizeQForGqaGeneration(RunnerParams const& params,\n SelectKernelParams& selectKernelParams) const {\n // Define the per-tile mainloop cost model for different tileSizeQ choices.\n std::unordered_map<int, float> kernelMainloopCost = {\n {128, 2.2}, // Cost factor when tileSizeQ = 128\n {64, 1.68}, // Cost factor when tileSizeQ = 64\n {32, 1.48}, // Cost factor when tileSizeQ = 32\n {16, 1.2}, // Cost factor when tileSizeQ = 16\n {8, 1.0} // Cost factor when tileSizeQ = 8\n };\n\n bool const isBf16QFp8KvFullTransform =\n isBf16QFp8KvGeneration() &&\n selectKernelParams.mBf16QFp8KvTransformMode == Bf16QFp8KvTransformMode::SeparateKv;\n\n // Define the per-tile reduction cost model for different tileSizeQ choices.\n std::unordered_map<int, float> kernelReductionCost = {\n {128, 1.32}, // Reduction cost factor when tileSizeQ = 128\n {64, 1.2}, // Reduction cost factor when tileSizeQ = 64\n {32, 1.08}, // Reduction cost factor when tileSizeQ = 32\n {16, 1.03}, // Reduction cost factor when tileSizeQ = 16\n {8, 1.0} // Reduction cost factor when tileSizeQ = 8\n };\n\n // Full-transform kernels pay conversion work in the KV mainloop, so bias the model toward\n // keeping enough KV parallelism without changing the reduction model.\n float const kernelMainloopCostFactor = isBf16QFp8KvFullTransform ? 2.0f : 1.0f;\n // The reduction cost emulated as a sequence length factor.\n float const kernelReductionSeqLenFactor = 128.0f;\n\n // The parameters for launching the kernel.\n CtaLaunchParams ctaLaunchParams;\n // The copy of the selectKernelParams, which makes sure it won't modify the original\n // selectKernelParams when computing the number of CTAs.\n SelectKernelParams selectKernelParamsCopy = selectKernelParams;\n // Load the kernel.\n auto [func, kernelMeta] = loadKernel(params, selectKernelParamsCopy);\n // Compute numCtasX, numCtasY and numCtasZ.\n computeCtaAndClusterConfig(ctaLaunchParams, params, kernelMeta, selectKernelParamsCopy);\n\n // If there are no free SMs or tileSizeQ is already the smallest one, skip the heuristic\n // selection.\n if (ctaLaunchParams.mNumCtasX * ctaLaunchParams.mNumCtasY * ctaLaunchParams.mNumCtasZ * 2 >\n params.mMultiProcessorCount ||\n selectKernelParamsCopy.mTileSizeQ <= 8) {\n // No need to select the kernel further.\n return;\n }\n\n // Candidate tile sizes for tileSizeQ to explore.\n int const candidateTileSizesQ[] = {128, 64, 32, 16, 8};\n\n // The default tileSizeQ.\n int defaultTileSizeQ = selectKernelParamsCopy.mTileSizeQ;\n // The selected tileSizeQ.\n int selectedTileSizeQ = selectKernelParamsCopy.mTileSizeQ;\n\n // The minimum modeling kernel time.\n float globalModelingKernelTime = FLT_MAX;\n // Loop over each candidate tile size.\n for (int tileSizeQ : candidateTileSizesQ) {\n // Only consider candidates <= default tileSizeQ and ensure each CTA processes full\n // numHeadsQPerKv.\n if (tileSizeQ > defaultTileSizeQ || tileSizeQ < params.mNumHeadsQPerKv) {\n continue;\n }\n\n selectKernelParamsCopy.mTileSizeQ = tileSizeQ;\n if (tileSizeQ >= 64) {\n selectKernelParamsCopy.mKernelType = FmhaKernelType::KeepsMmaAbForGeneration;\n } else {\n selectKernelParamsCopy.mKernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n }\n // Keep headDimPerCtaV and multiCtasKvMode in sync with the candidate kernelType so\n // loadKernel hashes a registered kernel.\n syncGqaGenerationTraitsForKernelHash(params, selectKernelParamsCopy);\n\n // Load the kernel.\n std::tie(func, kernelMeta) = loadKernel(params, selectKernelParamsCopy);\n\n // Compute the number of CTAs.\n computeCtaAndClusterConfig(ctaLaunchParams, params, kernelMeta, selectKernelParamsCopy);\n\n // Compute the seqLenPerCtaKv.\n int32_t seqLenPerCtaKv =\n flashinfer::ceil_div(flashinfer::ceil_div(params.mMaxSeqLenKv, kernelMeta.mStepKv),\n ctaLaunchParams.mMaxNumCtasKv) *\n kernelMeta.mStepKv;\n\n // Compute the modeling kernel time = mainloop cost + reduction cost.\n float modelingKernelTime =\n kernelMainloopCostFactor * kernelMainloopCost.at(tileSizeQ) * seqLenPerCtaKv +\n kernelReductionCost.at(tileSizeQ) * kernelReductionSeqLenFactor *\n ctaLaunchParams.mMaxNumCtasKv;\n\n // Compute the total number of CTAs.\n int32_t numCtas =\n ctaLaunchParams.mNumCtasX * ctaLaunchParams.mNumCtasY * ctaLaunchParams.mNumCtasZ;\n // Compute the number of waves.\n int32_t numWaves = flashinfer::ceil_div(numCtas, params.mMultiProcessorCount);\n // Compute the total modeling kernel time.\n modelingKernelTime *= numWaves;\n\n // If this candidate has a lower time than the global minimum, update the global minimum.\n if (modelingKernelTime < globalModelingKernelTime) {\n globalModelingKernelTime = modelingKernelTime;\n selectedTileSizeQ = tileSizeQ;\n }\n }\n\n // Update the tileSizeQ.\n selectKernelParams.mTileSizeQ = selectedTileSizeQ;\n // Update the kernel type.\n if (selectKernelParams.mTileSizeQ >= 64) {\n selectKernelParams.mKernelType = FmhaKernelType::KeepsMmaAbForGeneration;\n } else {\n selectKernelParams.mKernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n }\n // Apply the same sync to the committed kernelType; the probe above mutated only the copy.\n syncGqaGenerationTraitsForKernelHash(params, selectKernelParams);\n }\n\n // Selects a heuristic kernel for GQA generation.\n void selectGqGenerationKernel(RunnerParams const& params,\n SelectKernelParams& selectKernelParams) const {\n // The kernel type.\n FmhaKernelType& kernelType = selectKernelParams.mKernelType;\n // The tile size for Q.\n int& tileSizeQ = selectKernelParams.mTileSizeQ;\n selectKernelParams.mGroupsTokensHeadsQ = false;\n\n // Generic mixed precision kernels don't work with groupsTokensHeadsQ = true. BF16Q+FP8KV\n // transform paths present BF16 K to BMM1, so they can use the grouped-token cubins.\n if (!supportsGqaGroupingTokensHeadsQ(selectKernelParams)) {\n selectKernelParams.mGroupsTokensHeadsQ = false;\n tileSizeQ = params.mNumHeadsQPerKv <= 8 ? 8 : 16;\n kernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n return;\n }\n selectKernelParams.mGroupsTokensHeadsQ = true;\n\n // The number of tokensQ and headsQ that can be grouped into one CTA.\n int numTokensHeadsQ = params.mNumHeadsQPerKv * params.mMaxSeqLenQ;\n // When numHeadsQPerKv >= 64, use KeepsMmaAbForGeneration kernel.\n if (numTokensHeadsQ <= 8) {\n tileSizeQ = 8;\n kernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n } else if (numTokensHeadsQ <= 16) {\n tileSizeQ = 16;\n kernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n } else if (numTokensHeadsQ <= 32) {\n tileSizeQ = 32;\n kernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n } else if (numTokensHeadsQ <= 64) {\n tileSizeQ = 64;\n kernelType = FmhaKernelType::KeepsMmaAbForGeneration;\n } else {\n tileSizeQ = 128;\n kernelType = FmhaKernelType::KeepsMmaAbForGeneration;\n }\n\n // Normalize traits before the cost-model probe calls loadKernel().\n syncGqaGenerationTraitsForKernelHash(params, selectKernelParams);\n\n // When maxSeqLenQ > 1, use an experimental kernel-timing model to select the best kernel that\n // groups both tokensQ and headsQ into one CTA.\n if (params.mMaxSeqLenQ > 1) {\n selectTileSizeQForGqaGeneration(params, selectKernelParams);\n }\n }\n\n // Select a kernel based on the heuristic.\n void selectKernel(RunnerParams const& params, SelectKernelParams& selectKernelParams) const {\n // Normalize this before heuristic probing; some GQA-generation heuristics load candidate\n // kernels while selecting tileSizeQ.\n selectNumTokensPerPage(params, selectKernelParams);\n bool const isMlaGeneration = isGenerationKernel(params.mKernelType) && isMlaGenKernel(params);\n\n // Select the kernel based on the kernel type.\n if (isMlaGeneration) {\n selectMlaGenerationKernel(params, selectKernelParams);\n // TRTLLM-GEN MLA generation kernels are exported with dense mask metadata. Each generation\n // CTA processes a bounded query tile, so the runtime sequence lengths/indices provide the\n // effective masking.\n selectKernelParams.mMaskType = TrtllmGenAttentionMaskType::Dense;\n if (!isSparseMla(params.mSparseMlaType)) {\n FLASHINFER_CHECK(\n params.mMaxSeqLenKv <= params.mAttentionWindowSize &&\n params.mChunkedAttentionSize == INT_MAX,\n \"TRTLLM-GEN MLA generation does not support sliding-window or chunked attention.\");\n }\n } else if (isGenerationKernel(params.mKernelType)) {\n selectGqGenerationKernel(params, selectKernelParams);\n }\n\n // For headDimV > 256, set headDimPerCtaV to 256 for context and keepsMmaAbForGeneration\n // kernels. swapsMmaAbForGeneration has enough TMEM resources to hold the full headDimV.\n // Called for context and GQA generation; MLA sets headDimPerCtaV separately.\n if (params.mHeadDimV > 256 && !isMlaGenKernel(params) &&\n !isSwapsMmaAbForGenerationKernel(selectKernelParams.mKernelType)) {\n selectKernelParams.mHeadDimPerCtaV = 256;\n }\n\n // Enable sliding window or chunked causal if the max kv sequence length exceeds attention\n // window size or chunked attention size. This is supported by causal-mask context kernels and\n // generation-phase kernels.\n if (!isSparseMla(params.mSparseMlaType) &&\n (selectKernelParams.mMaskType == TrtllmGenAttentionMaskType::Causal ||\n !isContextKernel(params.mKernelType)) &&\n (params.mMaxSeqLenKv > params.mAttentionWindowSize ||\n params.mChunkedAttentionSize != INT_MAX)) {\n FLASHINFER_CHECK(\n params.mMaxSeqLenKv <= params.mAttentionWindowSize ||\n params.mMaxSeqLenKv <= params.mChunkedAttentionSize,\n \"Sliding window attention and chunked attention should not be used together\");\n selectKernelParams.mMaskType = TrtllmGenAttentionMaskType::SlidingOrChunkedCausal;\n }\n }\n\n std::pair<uint64_t, std::string> hashFromRunnerParams(\n RunnerParams const& params, SelectKernelParams& selectKernelParams) const {\n // Debug info.\n std::string info =\n \"qkvLayout=\" + std::to_string(static_cast<int>(params.mQkvLayout)) +\n \", maskType=\" + std::to_string(static_cast<int>(selectKernelParams.mMaskType)) +\n \", kernelType=\" + std::to_string(static_cast<int>(selectKernelParams.mKernelType)) +\n \", tileScheduler=\" + std::to_string(static_cast<int>(selectKernelParams.mTileScheduler)) +\n \", multiCtasKvMode=\" +\n std::to_string(static_cast<int>(selectKernelParams.mMultiCtasKvMode)) +\n \", headDimPerCtaV=\" + std::to_string(selectKernelParams.mHeadDimPerCtaV) +\n \", headDimQk=\" + std::to_string(params.mHeadDimQk) +\n \", headDimV=\" + std::to_string(params.mHeadDimV) +\n \", tileSizeQ=\" + std::to_string(selectKernelParams.mTileSizeQ) +\n \", tileSizeKv=\" + std::to_string(selectKernelParams.mTileSizeKv) +\n \", numTokensPerPage=\" + std::to_string(selectKernelParams.mNumTokensPerPage) +\n \", dynamicNumTokensPerPage=\" + std::to_string(selectKernelParams.mDynamicNumTokensPerPage) +\n \", reuseSmemKForV=\" + std::to_string(selectKernelParams.mReuseSmemKForV) +\n \", uses2CtaMma=\" + std::to_string(selectKernelParams.mUses2CtaMma) +\n \", groupsTokensHeadsQ=\" + std::to_string(selectKernelParams.mGroupsTokensHeadsQ) +\n \", sparseMlaType=\" + std::to_string(static_cast<int>(params.mSparseMlaType)) +\n \", skipsSoftmax=\" + std::to_string(selectKernelParams.mSkipsSoftmaxWhenPossible) +\n \", bf16QFp8KvTransformMode=\" +\n std::to_string(static_cast<int>(selectKernelParams.mBf16QFp8KvTransformMode)) +\n \", fp16Softmax=\" + std::to_string(selectKernelParams.mUseFp16Softmax) +\n \", usesSpcompress=\" + std::to_string(selectKernelParams.mUsesSpcompress);\n IKL_LOG_DEBUG(\n \"Searching for kernel traits (%d available) in TllmGenFmhaKernel(%s, %s, %s, %s, %d) %s\",\n getNumLoadedKernels(), toStr(mDtypeQ), toStr(mDtypeK), toStr(mDtypeV), toStr(mDtypeOut),\n mSM, info.c_str());\n\n return std::make_pair(\n hashID(static_cast<int>(params.mQkvLayout), static_cast<int>(selectKernelParams.mMaskType),\n static_cast<int>(selectKernelParams.mKernelType),\n static_cast<int>(selectKernelParams.mTileScheduler),\n static_cast<int>(selectKernelParams.mMultiCtasKvMode),\n selectKernelParams.mHeadDimPerCtaV, params.mHeadDimQk, params.mHeadDimV,\n selectKernelParams.mTileSizeQ, selectKernelParams.mTileSizeKv,\n selectKernelParams.mNumTokensPerPage, selectKernelParams.mDynamicNumTokensPerPage,\n selectKernelParams.mReuseSmemKForV, selectKernelParams.mUses2CtaMma,\n selectKernelParams.mGroupsTokensHeadsQ, static_cast<int>(params.mSparseMlaType),\n selectKernelParams.mSkipsSoftmaxWhenPossible,\n static_cast<int>(selectKernelParams.mBf16QFp8KvTransformMode),\n /*uses2QSlidingWindowKernel=*/false, selectKernelParams.mUseFp16Softmax,\n selectKernelParams.mUsesSpcompress),\n info);\n }\n\n // Load a single kernel (called by `run()` when needed).\n std::pair<CUfunction, KernelMeta> loadKernel(RunnerParams const& params,\n SelectKernelParams& selectKernelParams) const {\n // Hash the runner params.\n auto [hashId, info] = hashFromRunnerParams(params, selectKernelParams);\n auto const findMetaIter = mKernelMetaMap.find(hashId);\n\n // Add debug info when kernels are not found.\n FLASHINFER_CHECK(findMetaIter != mKernelMetaMap.end(), \"Trtllm-gen kernels not found: \" + info);\n\n // The meta index.\n auto const metaIndex = findMetaIter->second;\n\n // Load the function if not found.\n if (mFunctions.find(hashId) == mFunctions.end()) {\n // Load the kernel on-demand.\n auto const& kernelMeta = mKernelMeta[metaIndex];\n CUmodule hmod{0};\n std::string kernelName(kernelMeta.mFuncName);\n\n // Check if the module is already loaded.\n auto findModuleIter = mModules.find(kernelMeta.mFuncName);\n auto capitalizeFirst = [](std::string str) {\n if (!str.empty()) {\n str[0] = std::toupper(str[0]);\n }\n return str;\n };\n if (findModuleIter == mModules.end()) {\n // Load the module.\n std::string cubin_path = tllm_gen_fmha_cubin_path + \"/\" + kernelMeta.mFuncName + \".cubin\";\n std::string cubin = getCubin(cubin_path, kernelMeta.sha256);\n if (cubin.empty()) {\n throw std::runtime_error(\"Failed to load cubin for \" + kernelName);\n }\n cuErrCheck(cuModuleLoadData(&hmod, cubin.data()));\n mModules[kernelName] = hmod;\n } else {\n hmod = findModuleIter->second;\n }\n\n // Load the function.\n KernelInfo funcInfo;\n funcInfo.mMetaInfoIndex = metaIndex;\n cuErrCheck(cuModuleGetFunction(&funcInfo.mDeviceFunction, hmod, kernelMeta.mFuncName));\n\n setupKernelSmem(funcInfo.mDeviceFunction, kernelMeta);\n\n // Cache the loaded function.\n mFunctions[hashId] = funcInfo;\n }\n\n // Retrieve the loaded kernel.\n auto const& kernelInfo = mFunctions.at(hashId);\n auto const& kernelMeta = mKernelMeta[kernelInfo.mMetaInfoIndex];\n CUfunction func = kernelInfo.mDeviceFunction;\n\n // Return the function and kernelMeta.\n return std::make_pair(func, kernelMeta);\n }\n\n Data_type mDtypeQ, mDtypeK, mDtypeV, mDtypeOut;\n int mNumEltsPerSageAttnBlkQ, mNumEltsPerSageAttnBlkK, mNumEltsPerSageAttnBlkP,\n mNumEltsPerSageAttnBlkV;\n KernelMeta const* mKernelMeta;\n unsigned int mKernelMetaCount;\n unsigned int mSM;\n unsigned int mMaxDeviceSmemSize;\n mutable std::unordered_map<std::string, CUmodule> mModules;\n\n mutable std::unordered_map<uint64_t, unsigned int> mKernelMetaMap;\n\n struct KernelInfo {\n unsigned int mMetaInfoIndex;\n CUfunction mDeviceFunction;\n };\n\n mutable std::unordered_map<uint64_t, KernelInfo> mFunctions;\n};\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n\nclass TllmFmhaKernelFactory {\n public:\n using KernelType = TllmGenFmhaKernel;\n\n KernelType const* getKernels(const typename KernelType::KernelMeta* pKernelList,\n unsigned int nbKernels, Data_type dtypeQ, Data_type dtypeK,\n Data_type dtypeV, Data_type dtypeOut, unsigned int sm,\n int numEltsPerSageAttnBlkQ = 0, int numEltsPerSageAttnBlkK = 0,\n int numEltsPerSageAttnBlkP = 0, int numEltsPerSageAttnBlkV = 0) {\n static std::mutex s_mutex;\n std::lock_guard<std::mutex> lg(s_mutex);\n\n auto const id = hashID(dtypeQ, dtypeK, dtypeV, dtypeOut, sm, numEltsPerSageAttnBlkQ,\n numEltsPerSageAttnBlkK, numEltsPerSageAttnBlkP, numEltsPerSageAttnBlkV);\n auto const findIter = mKernels.find(id);\n if (findIter == mKernels.end()) {\n KernelType* newKernel = new KernelType{pKernelList,\n nbKernels,\n dtypeQ,\n dtypeK,\n dtypeV,\n dtypeOut,\n sm,\n numEltsPerSageAttnBlkQ,\n numEltsPerSageAttnBlkK,\n numEltsPerSageAttnBlkP,\n numEltsPerSageAttnBlkV};\n newKernel->loadKernels();\n mKernels.insert(std::make_pair(id, std::unique_ptr<KernelType>(newKernel)));\n IKL_LOG_DEBUG(\n \"Loading new kernel for dtypeQ=%s, dtypeK=%s, dtypeV=%s, dtypeOut=%s, sm=%d with %d \"\n \"loaded kernels\",\n toStr(dtypeQ), toStr(dtypeK), toStr(dtypeV), toStr(dtypeOut), sm,\n newKernel->getNumLoadedKernels());\n return newKernel;\n }\n return findIter->second.get();\n }\n\n static TllmFmhaKernelFactory& Get() {\n int deviceId;\n cudaGetDevice(&deviceId);\n static std::unique_ptr<TllmFmhaKernelFactory> sFactory[32] = {nullptr};\n if (sFactory[deviceId] == nullptr) {\n FLASHINFER_CHECK(deviceId < 32, \"Invalid deviceId %d (max is 32 devices)\", deviceId);\n sFactory[deviceId] = std::make_unique<TllmFmhaKernelFactory>(TllmFmhaKernelFactory());\n }\n\n return *(sFactory[deviceId]);\n }\n\n private:\n TllmFmhaKernelFactory() = default;\n\n inline uint64_t hashID(Data_type dtypeQ, Data_type dtypeK, Data_type dtypeV, Data_type dtypeOut,\n unsigned int sm, int numEltsPerSageAttnBlkQ, int numEltsPerSageAttnBlkK,\n int numEltsPerSageAttnBlkP, int numEltsPerSageAttnBlkV) const {\n // Encode sage block sizes as log2(size)+1 (0 when unused) to fit in 4 bits each.\n auto const sageEncode = [](int n) -> uint64_t {\n return n > 0 ? static_cast<uint64_t>(log2f(static_cast<float>(n))) + 1 : 0;\n };\n // Bit layout:\n // Bits 0-15: sm\n // Bits 16-19: dtypeQ\n // Bits 20-23: dtypeK\n // Bits 24-27: dtypeV\n // Bits 28-31: dtypeOut\n // Bits 32-35: numEltsPerSageAttnBlkQ (log2+1 encoding)\n // Bits 36-39: numEltsPerSageAttnBlkK\n // Bits 40-43: numEltsPerSageAttnBlkP\n // Bits 44-47: numEltsPerSageAttnBlkV\n return static_cast<uint64_t>(sm) | static_cast<uint64_t>(dtypeQ) << 16 |\n static_cast<uint64_t>(dtypeK) << 20 | static_cast<uint64_t>(dtypeV) << 24 |\n static_cast<uint64_t>(dtypeOut) << 28 | sageEncode(numEltsPerSageAttnBlkQ) << 32 |\n sageEncode(numEltsPerSageAttnBlkK) << 36 | sageEncode(numEltsPerSageAttnBlkP) << 40 |\n sageEncode(numEltsPerSageAttnBlkV) << 44;\n }\n\n std::unordered_map<uint64_t, const std::unique_ptr<KernelType>> mKernels;\n};\n\ninline TllmGenFmhaKernel const* getTllmFmhaKernels(Data_type dtypeQ, Data_type dtypeK,\n Data_type dtypeV, Data_type dtypeOut,\n unsigned int sm, int numEltsPerSageAttnBlkQ = 0,\n int numEltsPerSageAttnBlkK = 0,\n int numEltsPerSageAttnBlkP = 0,\n int numEltsPerSageAttnBlkV = 0) {\n#ifndef EXCLUDE_SM_100\n return TllmFmhaKernelFactory::Get().getKernels(\n tensorrt_llm::kernels::sTllmGenFmhaKernelMetaInfos,\n sizeof(tensorrt_llm::kernels::sTllmGenFmhaKernelMetaInfos) /\n sizeof(tensorrt_llm::kernels::sTllmGenFmhaKernelMetaInfos[0]),\n dtypeQ, dtypeK, dtypeV, dtypeOut, sm, numEltsPerSageAttnBlkQ, numEltsPerSageAttnBlkK,\n numEltsPerSageAttnBlkP, numEltsPerSageAttnBlkV);\n#else\n return nullptr;\n#endif // EXCLUDE_SM_100\n}\n"},"diff":{"kind":"string","value":"--- include/flashinfer/trtllm/fmha/fmhaKernels.cuh\n+++ include/flashinfer/trtllm/fmha/fmhaKernels.cuh\n@@ -794,10 +794,11 @@\n SelectKernelParams& selectKernelParams) const {\n // numHeadsQ <= 32 : SwapsMmaAbForGeneration\n // Non-power-of-two head counts use one padded Q8/Q16/Q32 tile. Power-of-two head counts use\n- // tileSizeQ = numHeadsQPerKv/2 at batch=1 or numHeadsQPerKv at batch>=2.\n- // Threshold: batchSize * maxNumCtasPerSeqKv <= MP/8 (crossover at batch=1->2 on B200).\n- // Benchmarks (seqLen=8192, topK=2048): half tileSizeQ wins by 2-6% at batch=1;\n- // full tileSizeQ wins by 2-11% at batch>=2.\n+ // tileSizeQ = numHeadsQPerKv/2 for short queries at batch=1, otherwise numHeadsQPerKv.\n+ // Threshold: maxSeqLenQ <= 16 and batchSize * maxNumCtasPerSeqKv <= MP/8\n+ // (crossover at batch=1->2 on B200).\n+ // Short-query benchmarks (seqLenKv=8192, topK=2048): half tileSizeQ wins by 2-6% at\n+ // batch=1; full tileSizeQ wins by 2-11% at batch>=2.\n // numHeadsQ > 32 : KeepsMmaAbForGeneration, tileSizeQ = 64\n // numHeadsQ=128 at large batch : 2CTA (clusterDimX=2, headDimPerCtaV=256)\n // otherwise : 1CTA, headDimPerCtaV fine-tuned later\n@@ -814,8 +815,10 @@\n // mMultiCtasKvMode defaults to GmemReduction from the constructor. computeCtaAndClusterConfig\n // may upgrade it to CgaSmemReduction; that update is preserved naturally across\n // re-selections. The base tileSizeQ is numHeadsQPerKv (one CTA covers all Q heads per token).\n- // At batch=1 the GPU is under-utilized, so we halve tileSizeQ to create 2x more\n- // head-splitting CTAs. Threshold: batchSize * maxNumCtasPerSeqKv <= MP/8.\n+ // At batch=1 short queries under-utilize the GPU, so halve tileSizeQ to create 2x more\n+ // head-splitting CTAs. Long-query prefill already has Q-axis parallelism; halving the tile\n+ // duplicates the KV loads for each token.\n+ // Threshold: maxSeqLenQ <= 16 and batchSize * maxNumCtasPerSeqKv <= MP/8.\n // effectiveSeqLenKv = min(seqLen, topK) = 2048 -> maxNumCtasPerSeqKv = 16.\n // Condition: batchSize * 16 <= MP/8 -> batchSize <= 1 (crossover at batch=1->2).\n // Only halve when half tileSizeQ >= 8 (no valid SwapsMmaAb kernel below tileSizeQ=8).\n@@ -824,8 +827,10 @@\n int const effectiveSeqLenKv = std::min(params.mMaxSeqLenKv, params.mSparseMlaTopK);\n int const maxNumCtasPerSeqKv =\n flashinfer::ceil_div(effectiveSeqLenKv, selectKernelParams.mTileSizeKv);\n- bool const useHalfTileSizeQ = halfTileSizeQ >= 8 && params.mBatchSize * maxNumCtasPerSeqKv <=\n- params.mMultiProcessorCount / 8;\n+ bool const useHalfTileSizeQ =\n+ halfTileSizeQ >= 8 &&\n+ params.mBatchSize * maxNumCtasPerSeqKv <= params.mMultiProcessorCount / 8 &&\n+ params.mMaxSeqLenQ <= 16;\n tileSizeQ = useHalfTileSizeQ ? halfTileSizeQ : fullTileSizeQ;\n } else {\n // numHeadsQ > 32: use KeepsMmaAbForGeneration."},"lines_added":{"kind":"number","value":13,"string":"13"},"lines_removed":{"kind":"number","value":8,"string":"8"},"files_in_commit":{"kind":"number","value":1,"string":"1"},"models_mentioned":{"kind":"list like","value":["deepseek"],"string":"[\n \"deepseek\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["B200"],"string":"[\n \"B200\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":["1x","1.000x","1.002x","1.001x","1.162x","1.277x","1.662x","1.897x","1.886x","8x"],"string":"[\n \"1x\",\n \"1.000x\",\n \"1.002x\",\n \"1.001x\",\n \"1.162x\",\n \"1.277x\",\n \"1.662x\",\n \"1.897x\",\n \"1.886x\",\n \"8x\"\n]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (include/flashinfer/trtllm/fmha/fmhaKernels.cuh).\n\nGoal: perf(sparse mla): Update sparse MLA half-Q-tile heuristic to apply to short queries only\nTarget hardware: B200\nTarget models: deepseek\n\nCurrent file:\n```cuda\n/*\n * Copyright (c) 2020-2026, NVIDIA CORPORATION. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#pragma once\n\n#include <cuda.h>\n\n#include <cfloat>\n#include <cstdint>\n#include <cstring>\n#include <cuda/std/cfloat>\n#include <iterator>\n#include <memory>\n#include <mutex>\n#include <unordered_map>\n\n#include \"../../exception.h\"\n#include \"../../utils.cuh\"\n#include \"../common.h\"\n#include \"cuda_runtime_api.h\"\n#include \"flashInferMetaInfo.h\"\n#include \"fmhaReduction.h\"\n#include \"fmhaRunnerParams.h\"\n#include \"kernelParams.h\"\n#include \"lse.cuh\"\n\n#ifdef TLLM_GEN_FMHA_CUBIN_PATH\nstatic const std::string tllm_gen_fmha_cubin_path = std::string(TLLM_GEN_FMHA_CUBIN_PATH);\n#else\nstatic_assert(false, \"TLLM_GEN_FMHA_CUBIN_PATH macro is not defined when compiling\");\n#endif\n\n#ifdef TLLM_GEN_FMHA_METAINFO_HASH\nstatic const std::string tllm_gen_fmha_metainfo_hash = std::string(TLLM_GEN_FMHA_METAINFO_HASH);\n#else\nstatic_assert(false, \"TLLM_GEN_FMHA_METAINFO_HASH macro is not defined when compiling\");\n#endif\n\nnamespace flashinfer::trtllm_cubin_loader {\nstd::string getCubin(const std::string& kernelName, const std::string& sha256);\n} // namespace flashinfer::trtllm_cubin_loader\nusing flashinfer::trtllm_cubin_loader::getCubin;\n\n// Check if two SM values are family/specific versions of the same architecture\n// Returns true only if one is a family version and the other is a compatible specific version\nconstexpr bool isFamilySpecificSMPair(int sm1, int sm2) {\n if ((sm1 == kSM_100f && (sm2 == kSM_100 || sm2 == kSM_103 || sm2 == kSM_107)) ||\n (sm2 == kSM_100f && (sm1 == kSM_100 || sm1 == kSM_103 || sm1 == kSM_107))) {\n return true;\n }\n return false;\n}\n\nconstexpr bool isSMCompatible(int gpuSM, int kernelSM) {\n if (gpuSM == kSM_103) {\n return kernelSM == kSM_100f || kernelSM == kSM_103;\n } else if (gpuSM == kSM_107) {\n return kernelSM == kSM_100f || kernelSM == kSM_107;\n } else if (gpuSM == kSM_100) {\n return kernelSM == kSM_100f || kernelSM == kSM_100;\n }\n\n return gpuSM == kernelSM;\n}\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\nclass TllmGenFmhaKernel {\n public:\n static constexpr int kDynamicNumTokensPerPageThreshold = 128;\n static constexpr int kDynamicNumTokensPerPageKernelKey = 128;\n\n // The parameters for launching the kernel.\n // maxNumCtasQ, maxNumCtasKv, numCtasX, numCtasY, numCtasZ, clusterDimX\n struct CtaLaunchParams {\n // The maximum number of CTAs in Q dimension.\n int mMaxNumCtasQ;\n // The maximum number of CTAs in Kv dimension.\n int mMaxNumCtasKv;\n // The number of CTAs in X dimension.\n int mNumCtasX;\n // The number of CTAs in Y dimension.\n int mNumCtasY;\n // The number of CTAs in Z dimension.\n int mNumCtasZ;\n // The cluster size in the X dimension.\n int mClusterDimX;\n };\n\n public:\n using KernelMeta = tensorrt_llm::kernels::TllmGenFmhaKernelMetaInfo;\n using RunnerParams = TllmGenFmhaRunnerParams;\n using SelectKernelParams = TllmGenSelectKernelParams;\n\n // Ctor.\n TllmGenFmhaKernel(KernelMeta const* pMetaStart, unsigned int nMetaCount, Data_type dtypeQ,\n Data_type dtypeK, Data_type dtypeV, Data_type dtypeOut, unsigned int smArch,\n int numEltsPerSageAttnBlkQ = 0, int numEltsPerSageAttnBlkK = 0,\n int numEltsPerSageAttnBlkP = 0, int numEltsPerSageAttnBlkV = 0)\n : mDtypeQ(dtypeQ),\n mDtypeK(dtypeK),\n mDtypeV(dtypeV),\n mDtypeOut(dtypeOut),\n mNumEltsPerSageAttnBlkQ(numEltsPerSageAttnBlkQ),\n mNumEltsPerSageAttnBlkK(numEltsPerSageAttnBlkK),\n mNumEltsPerSageAttnBlkP(numEltsPerSageAttnBlkP),\n mNumEltsPerSageAttnBlkV(numEltsPerSageAttnBlkV),\n mKernelMeta(pMetaStart),\n mKernelMetaCount(nMetaCount),\n mSM(smArch),\n mMaxDeviceSmemSize(queryMaxDeviceSmemSize(smArch)) {}\n\n static constexpr unsigned int kSmemOptInThreshold = 48 * 1024;\n static constexpr unsigned int kRubinLegacySmemCap = 228 * 1024;\n static constexpr unsigned int kStaticSmemReserve = 1024;\n\n static bool isRubinOversized(unsigned int sm, unsigned int sharedMemBytes) {\n return sm == kSM_107 && (sharedMemBytes + kStaticSmemReserve > kRubinLegacySmemCap);\n }\n\n void setupKernelSmem(CUfunction func, KernelMeta const& kernelMeta) const {\n // CU_FUNC_ATTRIBUTE_SHARED_MEMORY_MODE and the ALLOW_OVERSIZED enum value require\n // CUDA >= 13.4; CUDA 13.3 only ships the launch-attribute half of this API.\n#if CUDA_VERSION >= 13040\n if (isRubinOversized(mSM, kernelMeta.mSharedMemBytes)) {\n cuErrCheck(cuFuncSetAttribute(func, CU_FUNC_ATTRIBUTE_SHARED_MEMORY_MODE,\n CU_SHARED_MEMORY_MODE_ALLOW_OVERSIZED_SHARED_MEMORY));\n return;\n }\n#endif\n if (kernelMeta.mSharedMemBytes >= kSmemOptInThreshold) {\n cuErrCheck(cuFuncSetAttribute(func, CU_FUNC_ATTRIBUTE_MAX_DYNAMIC_SHARED_SIZE_BYTES,\n kernelMeta.mSharedMemBytes));\n }\n }\n\n void appendOversizedSmemLaunchAttr(CUlaunchAttribute* launch_attribute,\n CUlaunchConfig& launch_config,\n KernelMeta const& kernelMeta) const {\n#if CUDA_VERSION >= 13040\n if (isRubinOversized(mSM, kernelMeta.mSharedMemBytes)) {\n IKL_LOG_DEBUG(\n \"TRTLLM-Gen launch info: using oversized shared memory for kernel %s (smem=%u bytes)\",\n kernelMeta.mFuncName, kernelMeta.mSharedMemBytes);\n launch_attribute[launch_config.numAttrs].id = CU_LAUNCH_ATTRIBUTE_SHARED_MEMORY_MODE;\n launch_attribute[launch_config.numAttrs].value.sharedMemoryMode =\n CU_SHARED_MEMORY_MODE_ALLOW_OVERSIZED_SHARED_MEMORY;\n launch_config.numAttrs += 1;\n }\n#endif\n }\n\n static unsigned int queryMaxDeviceSmemSize(unsigned int smArch) {\n CUdevice device;\n cuErrCheck(cuCtxGetDevice(&device));\n int smem_bytes = 0;\n#if CUDA_VERSION >= 13040\n if (smArch == kSM_107) {\n cuErrCheck(cuDeviceGetAttribute(\n &smem_bytes, CU_DEVICE_ATTRIBUTE_MAX_OVERSIZED_SHARED_MEMORY_PER_BLOCK, device));\n return static_cast<unsigned int>(smem_bytes);\n }\n#endif\n cuErrCheck(cuDeviceGetAttribute(&smem_bytes,\n CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_BLOCK_OPTIN, device));\n return static_cast<unsigned int>(smem_bytes);\n }\n\n void loadKernels() {\n for (unsigned int i = 0; i < mKernelMetaCount; ++i) {\n auto const& kernelMeta = mKernelMeta[i];\n IKL_LOG_DEBUG(\"Checking tllmgen attention kernel %s\", kernelMeta.mFuncName);\n if (kernelMeta.mSharedMemBytes + kStaticSmemReserve > mMaxDeviceSmemSize) {\n continue;\n }\n if (isSMCompatible(mSM, kernelMeta.mSM) && kernelMeta.mDataTypeQ == mDtypeQ &&\n kernelMeta.mDataTypeK == mDtypeK && kernelMeta.mDataTypeV == mDtypeV &&\n kernelMeta.mDataTypeO == mDtypeOut &&\n kernelMeta.mNumEltsPerSageAttnBlkQ == mNumEltsPerSageAttnBlkQ &&\n kernelMeta.mNumEltsPerSageAttnBlkK == mNumEltsPerSageAttnBlkK &&\n kernelMeta.mNumEltsPerSageAttnBlkP == mNumEltsPerSageAttnBlkP &&\n kernelMeta.mNumEltsPerSageAttnBlkV == mNumEltsPerSageAttnBlkV) {\n // Store metadata for later use.\n IKL_LOG_DEBUG(\"Adding tllmgen attention kernel %s\", kernelMeta.mFuncName);\n // Check for hash conflicts.\n uint64_t hash = hashID(kernelMeta);\n if (mKernelMetaMap.find(hash) != mKernelMetaMap.end()) {\n // The kernelMeta of the existing kernel.\n auto const& existingKernelMeta = mKernelMeta[mKernelMetaMap.at(hash)];\n FLASHINFER_CHECK(isFamilySpecificSMPair(existingKernelMeta.mSM, kernelMeta.mSM),\n \"Hash conflicts exist between %s and %s.\", existingKernelMeta.mFuncName,\n kernelMeta.mFuncName);\n\n // Prefer specific SM version over family version (replace if existing is family).\n if (existingKernelMeta.mSM == kSM_100f) {\n mKernelMetaMap[hash] = i;\n }\n } else {\n mKernelMetaMap[hash] = i;\n }\n }\n }\n }\n\n size_t getNumLoadedKernels() const { return mKernelMetaMap.size(); }\n\n inline int getBf16QFp8KvTransformMode(bool enablesKOnlyTransform,\n bool separateTransformedKv) const {\n FLASHINFER_CHECK(!(enablesKOnlyTransform && separateTransformedKv),\n \"BF16Q FP8KV transform mode cannot be both K-only and separate K/V.\");\n if (enablesKOnlyTransform) {\n return static_cast<int>(Bf16QFp8KvTransformMode::KOnly);\n }\n if (separateTransformedKv) {\n return static_cast<int>(Bf16QFp8KvTransformMode::SeparateKv);\n }\n return static_cast<int>(Bf16QFp8KvTransformMode::Full);\n }\n\n inline bool isBf16QFp8KvGeneration() const {\n return mDtypeQ == DATA_TYPE_BF16 && mDtypeK == DATA_TYPE_E4M3 && mDtypeV == DATA_TYPE_E4M3 &&\n mDtypeOut == DATA_TYPE_BF16;\n }\n\n inline bool supportsGqaGroupingTokensHeadsQ(SelectKernelParams const& selectKernelParams) const {\n return mDtypeQ == mDtypeK ||\n (isBf16QFp8KvGeneration() &&\n selectKernelParams.mBf16QFp8KvTransformMode != Bf16QFp8KvTransformMode::Full);\n }\n\n inline uint64_t hashID(int qkvLayout, int maskType, int kernelType, int scheduler,\n int multiCtasKvMode, int headDimPerCtaV, int headDimQk, int headDimV,\n int tileSizeQ, int tileSizeKv, int numTokensPerPage,\n bool dynamicNumTokensPerPage, bool reuseSmemKForV, bool uses2CtaMma,\n bool groupsTokensHeadsQ, int sparseMlaType, bool skipsSoftmax,\n int bf16QFp8KvTransformMode, bool uses2QSlidingWindowKernel,\n bool fp16Softmax, bool usesSpcompress) const {\n FLASHINFER_CHECK((headDimPerCtaV >= 32) && (headDimQk >= 32) && (headDimV >= 32) &&\n (headDimPerCtaV <= 1024) && (headDimQk <= 1024) && (headDimV <= 1024),\n \"Expect (32 <= headDim <= 1024), got headDimPerCtaV=%d, headDimQk=%d, \"\n \"headDimV=%d\",\n headDimPerCtaV, headDimQk, headDimV);\n // The numTokensPerPage must be 0 (unused for non-paged kernels) or power of 2.\n FLASHINFER_CHECK(numTokensPerPage == 0 || ((numTokensPerPage & (numTokensPerPage - 1)) == 0),\n \"The numTokensPerPage must be 0 or power of 2.\");\n FLASHINFER_CHECK(tileSizeQ <= 128 && tileSizeKv <= 128,\n \"The tileSizeQ and tileSizeKv must be <= 128.\");\n FLASHINFER_CHECK((tileSizeQ & (tileSizeQ - 1)) == 0 && (tileSizeKv & (tileSizeKv - 1)) == 0,\n \"The tileSizeQ and tileSizeKv must be power of 2.\");\n FLASHINFER_CHECK(tileSizeKv == 64 || tileSizeKv == 128, \"The tileSizeKv must be 64 or 128.\");\n FLASHINFER_CHECK(sparseMlaType >= 0 && sparseMlaType <= 3,\n \"The sparse MLA type must fit in 2 bits.\");\n FLASHINFER_CHECK(bf16QFp8KvTransformMode >= 0 && bf16QFp8KvTransformMode <= 2,\n \"The BF16Q FP8KV transform mode must fit in 2 bits.\");\n // The enum fields are packed tightly, so an out-of-range value would alias onto its neighbour\n // instead of producing a distinct key. Check them rather than trusting the exporter.\n uint64_t const numTokensPerPageLog2 =\n numTokensPerPage == 0 ? 0 : static_cast<uint64_t>(log2(numTokensPerPage));\n FLASHINFER_CHECK(qkvLayout >= 0 && qkvLayout < 4 && maskType >= 0 && maskType < 8 &&\n kernelType >= 0 && kernelType < 8 && scheduler >= 0 && scheduler < 4 &&\n multiCtasKvMode >= 0 && multiCtasKvMode < 4 &&\n bf16QFp8KvTransformMode >= 0 && bf16QFp8KvTransformMode < 4 &&\n numTokensPerPageLog2 < 16,\n \"Kernel attribute out of range for the hash key: qkvLayout=%d, maskType=%d, \"\n \"kernelType=%d, tileScheduler=%d, multiCtasKvMode=%d, \"\n \"bf16QFp8KvTransformMode=%d, numTokensPerPage=%d\",\n qkvLayout, maskType, kernelType, scheduler, multiCtasKvMode,\n bf16QFp8KvTransformMode, numTokensPerPage);\n // Format of the hash key. The enum fields are packed to their actual width rather than a\n // round 4 bits, which is what makes room for fp16Softmax and usesSpcompress; the key is a\n // private lookup key (nothing persists it), so the layout can move as long as\n // hashID(KernelMeta) and hashFromRunnerParams() move with it.\n // Bit 0 - 1 : qkvLayout.\n // Bit 2 - 4 : maskType.\n // Bit 5 - 7 : kernelType.\n // Bit 8 - 9 : tileScheduler.\n // Bit 10 - 11: multiCtasKvMode.\n // Bit 12 - 19: (headDimPerCtaV >> 3).\n // Bit 20 - 27: (headDimQk >> 3).\n // Bit 28 - 35: (headDimV >> 3).\n // Bit 36 - 37: (tileSizeKv >> 6).\n // Bit 38 - 41: (log2(numTokensPerPage)).\n // Bit 42 - 44: (log2(tileSizeQ)).\n // Bit 45 - 45: reuseSmemKForV.\n // Bit 46 - 46: uses2CtaMma.\n // Bit 47 - 48: sparseMlaType (0=none, 1=static token sparse, 2=dynamic token sparse).\n // Bit 49 - 49: skipsSoftmax.\n // Bit 50 - 50: dynamicNumTokensPerPage.\n // Bit 51 - 52: BF16Q FP8KV transform mode (0=full, 1=K-only, 2=separate K/V).\n // Bit 53 - 53: groupsTokensHeadsQ.\n // Bit 54 - 54: uses2QSlidingWindowKernel (Keeps generation 2Qx1KV SlidingWindowCustom).\n // Bit 55 - 55: fp16Softmax.\n // Bit 56 - 56: usesSpcompress.\n // Bit 57 - 63: unused.\n return (static_cast<uint64_t>(qkvLayout) << 0) | (static_cast<uint64_t>(maskType) << 2) |\n (static_cast<uint64_t>(kernelType) << 5) | (static_cast<uint64_t>(scheduler) << 8) |\n (static_cast<uint64_t>(multiCtasKvMode) << 10) |\n (static_cast<uint64_t>(headDimPerCtaV >> 3) << 12) |\n (static_cast<uint64_t>(headDimQk >> 3) << 20) |\n (static_cast<uint64_t>(headDimV >> 3) << 28) |\n (static_cast<uint64_t>(tileSizeKv >> 6) << 36) | (numTokensPerPageLog2 << 38) |\n (static_cast<uint64_t>(log2(tileSizeQ)) << 42) |\n (static_cast<uint64_t>(reuseSmemKForV) << 45) |\n (static_cast<uint64_t>(uses2CtaMma) << 46) |\n (static_cast<uint64_t>(sparseMlaType) << 47) |\n (static_cast<uint64_t>(skipsSoftmax) << 49) |\n (static_cast<uint64_t>(dynamicNumTokensPerPage) << 50) |\n (static_cast<uint64_t>(bf16QFp8KvTransformMode) << 51) |\n (static_cast<uint64_t>(groupsTokensHeadsQ) << 53) |\n (static_cast<uint64_t>(uses2QSlidingWindowKernel) << 54) |\n (static_cast<uint64_t>(fp16Softmax) << 55) |\n (static_cast<uint64_t>(usesSpcompress) << 56);\n }\n\n inline bool is2QSlidingWindowKernel(KernelMeta const& kernelMeta) const {\n return kernelMeta.mKernelType == static_cast<int>(FmhaKernelType::KeepsMmaAbForGeneration) &&\n kernelMeta.mGroupsTokensHeadsQ && kernelMeta.mStepQ == 2 * kernelMeta.mTileSizeQ;\n }\n\n inline bool isDynamicNumTokensPerPageKernel(KernelMeta const& kernelMeta) const {\n return kernelMeta.mNumTokensPerPage == kDynamicNumTokensPerPageKernelKey &&\n std::strstr(kernelMeta.mFuncName, \"P128\") == nullptr;\n }\n\n uint64_t hashID(KernelMeta const& kernelMeta) const {\n return hashID(\n kernelMeta.mQkvLayout, kernelMeta.mMaskType, kernelMeta.mKernelType,\n kernelMeta.mTileScheduler, kernelMeta.mMultiCtasKvMode, kernelMeta.mHeadDimPerCtaV,\n kernelMeta.mHeadDimQk, kernelMeta.mHeadDimV, kernelMeta.mTileSizeQ, kernelMeta.mTileSizeKv,\n kernelMeta.mNumTokensPerPage, isDynamicNumTokensPerPageKernel(kernelMeta),\n kernelMeta.mReuseSmemKForV, kernelMeta.m2CtaMma, kernelMeta.mGroupsTokensHeadsQ,\n kernelMeta.mSparseAttn, kernelMeta.mSkipsSoftmaxWhenPossible,\n getBf16QFp8KvTransformMode(kernelMeta.mEnablesBf16QFp8KvKOnlyTransform,\n kernelMeta.mSeparateTransformedKv),\n is2QSlidingWindowKernel(kernelMeta), kernelMeta.mFp16Softmax, kernelMeta.mUsesSpcompress);\n }\n\n std::pair<bool, std::string> checkIfKernelExist(RunnerParams const& params) const {\n // The selectKernelParams that might be updated.\n SelectKernelParams selectKernelParams{params};\n // Select the kernel.\n selectKernel(params, selectKernelParams);\n // Hash the runner params.\n auto [hashId, info] = hashFromRunnerParams(params, selectKernelParams);\n return std::make_pair(mKernelMetaMap.find(hashId) != mKernelMetaMap.end(), info);\n }\n\n // start here\n void run(RunnerParams const& params) const {\n SelectKernelParams selectKernelParams{params};\n CtaLaunchParams ctaLaunchParams;\n\n // Kernel selection loop (bounded). Each pass may update selectKernelParams (e.g. switch\n // MultiCtasKvMode to Disabled, upgrade to CgaSmemReduction, or reduce headDimPerCtaV) and\n // request a re-select via mSelectNewKernel. Each trigger fires at most once, so the sequence\n // converges in at most kMaxKernelSelectionPasses passes.\n static constexpr int kMaxKernelSelectionPasses = 4;\n CUfunction func{};\n KernelMeta kernelMeta{};\n for (int pass = 0; pass < kMaxKernelSelectionPasses; ++pass) {\n selectKernel(params, selectKernelParams);\n std::tie(func, kernelMeta) = loadKernel(params, selectKernelParams);\n computeCtaAndClusterConfig(ctaLaunchParams, params, kernelMeta, selectKernelParams);\n if (!selectKernelParams.mSelectNewKernel) {\n break;\n }\n FLASHINFER_CHECK(pass + 1 < kMaxKernelSelectionPasses,\n \"trtllm-gen kernel selection did not converge in %d passes.\",\n kMaxKernelSelectionPasses);\n }\n\n // Prepare the kernel parameters.\n auto kernelParams = KernelParams::setKernelParams(\n params, kernelMeta, ctaLaunchParams.mMaxNumCtasQ, ctaLaunchParams.mMaxNumCtasKv);\n\n // Override SageAttention parameters.\n auto sageParamEncode = [](int blockSize) -> int32_t {\n FLASHINFER_CHECK((blockSize & (blockSize - 1)) == 0,\n \"SageAttention block size must be a power of 2.\");\n return blockSize == 0 ? 0 : __builtin_ctz(static_cast<unsigned int>(blockSize));\n };\n kernelParams.ptrSageAttnSfsQ = params.ptrSageAttnSfsQ;\n kernelParams.ptrSageAttnSfsK = params.ptrSageAttnSfsK;\n kernelParams.ptrSageAttnSfsP = params.ptrSageAttnSfsP;\n kernelParams.ptrSageAttnSfsV = params.ptrSageAttnSfsV;\n kernelParams.mLogNumEltsPerSageAttnBlkQ = sageParamEncode(kernelMeta.mNumEltsPerSageAttnBlkQ);\n kernelParams.mLogNumEltsPerSageAttnBlkK = sageParamEncode(kernelMeta.mNumEltsPerSageAttnBlkK);\n kernelParams.mLogNumEltsPerSageAttnBlkP = sageParamEncode(kernelMeta.mNumEltsPerSageAttnBlkP);\n kernelParams.mLogNumEltsPerSageAttnBlkV = sageParamEncode(kernelMeta.mNumEltsPerSageAttnBlkV);\n\n void* kernelParamsList[] = {&kernelParams};\n CUlaunchAttribute launch_attribute[4] = {};\n CUlaunchConfig launch_config;\n buildLaunchConfig(launch_config, launch_attribute, kernelMeta, ctaLaunchParams, params);\n\n // Debug info.\n IKL_LOG_DEBUG(\n \"TRTLLM-Gen launch info (in TllmGenFmhaKernel %s, %s, %s, %s, %d): kernelName = %s\",\n toStr(mDtypeQ), toStr(mDtypeK), toStr(mDtypeV), toStr(mDtypeOut), mSM,\n kernelMeta.mFuncName);\n IKL_LOG_DEBUG(\n \"TRTLLM-Gen launch info: maxSeqLenQ = %d, \"\n \"maxSeqLenKv = %d, \"\n \"numHeadsQ = %d, \"\n \"numHeadsKv = %d, batchSize = %d, kernelType = %d\",\n params.mMaxSeqLenQ, params.mMaxSeqLenKv, params.mNumHeadsQ, params.mNumHeadsKv,\n params.mBatchSize, static_cast<int>(params.mKernelType));\n IKL_LOG_DEBUG(\n \"TRTLLM-Gen launch info: numCtasX = %d, numCtasY = %d, numCtasZ = %d, clusterDimX = %d\",\n ctaLaunchParams.mNumCtasX, ctaLaunchParams.mNumCtasY, ctaLaunchParams.mNumCtasZ,\n ctaLaunchParams.mClusterDimX);\n\n setNonPortableClusterIfNeeded(func, ctaLaunchParams);\n\n // Force GmemReduction if CgaSmemReduction would need more than one wave (cluster occupancy\n // limit). TODO: find a better heuristic of using CgaSmemReduction.\n if (isCgaSmemReduction(selectKernelParams.mMultiCtasKvMode)) {\n int maxActiveClusters = 1;\n cuErrCheck(cuOccupancyMaxActiveClusters(&maxActiveClusters, func, &launch_config));\n if (maxActiveClusters * ctaLaunchParams.mClusterDimX <\n ctaLaunchParams.mNumCtasX * ctaLaunchParams.mNumCtasY * ctaLaunchParams.mNumCtasZ) {\n selectKernelParams.mForceGmemReduction = true;\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::GmemReduction;\n selectKernel(params, selectKernelParams);\n std::tie(func, kernelMeta) = loadKernel(params, selectKernelParams);\n computeCtaAndClusterConfig(ctaLaunchParams, params, kernelMeta, selectKernelParams);\n FLASHINFER_CHECK(!selectKernelParams.mSelectNewKernel,\n \"trtllm-gen kernel selection did not converge after CgaSmemReduction \"\n \"fallback to GmemReduction.\");\n // Rebuild kernelParams: setKernelParams uses kernelMeta (TMA descriptors, tile shapes)\n // which changed when switching from CgaSmemReduction to GmemReduction kernel.\n kernelParams = KernelParams::setKernelParams(\n params, kernelMeta, ctaLaunchParams.mMaxNumCtasQ, ctaLaunchParams.mMaxNumCtasKv);\n buildLaunchConfig(launch_config, launch_attribute, kernelMeta, ctaLaunchParams, params);\n setNonPortableClusterIfNeeded(func, ctaLaunchParams);\n }\n }\n\n cuErrCheck(cuLaunchKernelEx(&launch_config, func, kernelParamsList, nullptr));\n\n // Run the separate reduction kernel if needed.\n tensorrt_llm::kernels::runFmhaReduction(kernelMeta, kernelParams, params.mMultiProcessorCount,\n params.enable_pdl, params.stream);\n\n if (params.lsePtr != nullptr) {\n FLASHINFER_CUDA_CHECK(flashinfer::ComputeLSEFromMD(\n params.softmaxStatsPtr, params.lsePtr, params.mSumOfSeqLensQ, params.mNumHeadsQ,\n params.lseStrideTokens, params.lseStrideHeads, params.enable_pdl, params.stream));\n }\n }\n\n private:\n // Fill a CUlaunchConfig and its associated attribute array from the current kernel and CTA\n // params. The caller owns the storage for launch_attribute (must be an array of at least 3\n // elements) and is responsible for ensuring it outlives launch_config.\n void buildLaunchConfig(CUlaunchConfig& launch_config, CUlaunchAttribute* launch_attribute,\n KernelMeta const& kernelMeta, CtaLaunchParams const& ctaLaunchParams,\n RunnerParams const& params) const {\n launch_config.blockDimX = kernelMeta.mThreadsPerCTA;\n launch_config.blockDimY = 1;\n launch_config.blockDimZ = 1;\n launch_config.gridDimX = ctaLaunchParams.mNumCtasX;\n launch_config.gridDimY = ctaLaunchParams.mNumCtasY;\n launch_config.gridDimZ = ctaLaunchParams.mNumCtasZ;\n launch_config.hStream = params.stream;\n launch_config.sharedMemBytes = kernelMeta.mSharedMemBytes;\n launch_attribute[0].id = CU_LAUNCH_ATTRIBUTE_CLUSTER_DIMENSION;\n launch_attribute[0].value.clusterDim.x = ctaLaunchParams.mClusterDimX;\n launch_attribute[0].value.clusterDim.y = 1;\n launch_attribute[0].value.clusterDim.z = 1;\n launch_attribute[1].id = CU_LAUNCH_ATTRIBUTE_CLUSTER_SCHEDULING_POLICY_PREFERENCE;\n launch_attribute[1].value.clusterSchedulingPolicyPreference =\n ctaLaunchParams.mClusterDimX > 1 ? CU_CLUSTER_SCHEDULING_POLICY_SPREAD\n : CU_CLUSTER_SCHEDULING_POLICY_DEFAULT;\n launch_attribute[2].id = CU_LAUNCH_ATTRIBUTE_PROGRAMMATIC_STREAM_SERIALIZATION;\n launch_attribute[2].value.programmaticStreamSerializationAllowed = params.enable_pdl;\n launch_config.attrs = launch_attribute;\n launch_config.numAttrs = 3;\n appendOversizedSmemLaunchAttr(launch_attribute, launch_config, kernelMeta);\n }\n\n // Enable non-portable cluster sizes when clusterDimX exceeds the portable limit of 8.\n void setNonPortableClusterIfNeeded(CUfunction func,\n CtaLaunchParams const& ctaLaunchParams) const {\n if (ctaLaunchParams.mClusterDimX > 8) {\n cuErrCheck(cuFuncSetAttribute(func, CU_FUNC_ATTRIBUTE_NON_PORTABLE_CLUSTER_SIZE_ALLOWED,\n 1 // Enable non-portable cluster sizes\n ));\n }\n }\n\n // Is it MLA generation kernel ?\n inline bool isMlaGenKernel(RunnerParams const& params) const {\n return (params.mHeadDimQk == 576 && params.mHeadDimV == 512) ||\n (params.mHeadDimQk == 320 && params.mHeadDimV == 256) ||\n (isSparseMla(params.mSparseMlaType) && params.mHeadDimQk == 512 &&\n params.mHeadDimV == 512);\n }\n\n inline bool useDynamicNumTokensPerPage(RunnerParams const& params) const {\n return isPagedKv(params.mQkvLayout) && !isSparseMla(params.mSparseMlaType) &&\n params.mHeadDimQk == params.mHeadDimV &&\n params.mNumTokensPerPage >= kDynamicNumTokensPerPageThreshold;\n }\n\n void selectNumTokensPerPage(RunnerParams const& params,\n SelectKernelParams& selectKernelParams) const {\n selectKernelParams.mDynamicNumTokensPerPage = false;\n if (isSparseMla(params.mSparseMlaType)) {\n // SparseMla kernels use a fixed numTokensPerPage = 1.\n selectKernelParams.mNumTokensPerPage = 1;\n } else if (!isPagedKv(params.mQkvLayout)) {\n // NumTokensPerPage is set to 0 when not selecting pagedKv-layout kernels.\n selectKernelParams.mNumTokensPerPage = 0;\n } else if (useDynamicNumTokensPerPage(params)) {\n FLASHINFER_CHECK((params.mNumTokensPerPage & (params.mNumTokensPerPage - 1)) == 0,\n \"Dynamic numTokensPerPage requires a power-of-2 page size, got %d.\",\n params.mNumTokensPerPage);\n selectKernelParams.mDynamicNumTokensPerPage = true;\n selectKernelParams.mNumTokensPerPage = kDynamicNumTokensPerPageKernelKey;\n } else {\n selectKernelParams.mNumTokensPerPage = params.mNumTokensPerPage;\n }\n }\n\n bool hasCgaSmemReductionKernel(RunnerParams const& params,\n SelectKernelParams selectKernelParams) const {\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::CgaSmemReduction;\n auto const hashId = hashFromRunnerParams(params, selectKernelParams).first;\n return mKernelMetaMap.find(hashId) != mKernelMetaMap.end();\n }\n\n // Compute the number of CTAs in X, Y and Z dimension and the cluster size in the X dimension.\n void computeCtaAndClusterConfig(CtaLaunchParams& ctaLaunchParams, RunnerParams const& params,\n KernelMeta const& kernelMeta,\n SelectKernelParams& selectKernelParams) const {\n bool isDsv3MinLatencyMode = params.mBatchSize == 1 && params.mMaxSeqLenQ >= 1 &&\n params.mMaxSeqLenQ <= 16 && params.mHeadDimQk == 576 &&\n params.mHeadDimV == 512;\n // Do we need to select a new kernel ?\n selectKernelParams.mSelectNewKernel = false;\n\n // The number of Ctas per Q sequence.\n int numCtasPerSeqQ = (params.mMaxSeqLenQ + kernelMeta.mStepQ - 1) / kernelMeta.mStepQ;\n // The generation-phase kernels might need to group both tokensQ and headsQ into one CTA.\n if (params.mMaxSeqLenQ > 1 && !isContextKernel(params.mKernelType)) {\n // Each CTA handles one tokenQ by default for spec-decoding generation kernel.\n if (!kernelMeta.mGroupsTokensHeadsQ) {\n numCtasPerSeqQ = params.mMaxSeqLenQ;\n } else {\n // Compute numTokensPerCtaQ where each CTA must process complete numGroupedHeadsQ.\n // Note that each CTA must process complete numHeadsQPerKv.\n int numTokensPerCtaQ = std::max(1, kernelMeta.mStepQ / params.mNumHeadsQPerKv);\n // Group both headsQ and tokensQ into one CTA.\n numCtasPerSeqQ = flashinfer::ceil_div(params.mMaxSeqLenQ, numTokensPerCtaQ);\n }\n }\n\n // Compute the grid dimension Y.\n int numHeadsPerCta =\n kernelMeta.mGroupsHeadsQ ? std::min(params.mNumHeadsQPerKv, kernelMeta.mStepQ) : 1;\n int numCtasForAllHeadsQ = params.mNumHeadsQ / numHeadsPerCta;\n FLASHINFER_CHECK(numHeadsPerCta * numCtasForAllHeadsQ == params.mNumHeadsQ,\n \"The numHeadsQ/numHeadsKv is not supported.\");\n // Take the number of headDim CTAs.\n FLASHINFER_CHECK(kernelMeta.mHeadDimV % selectKernelParams.mHeadDimPerCtaV == 0,\n \"The headDimPerCtaV is not supported.\");\n int numCtasPerHeadDim = kernelMeta.mHeadDimV / selectKernelParams.mHeadDimPerCtaV;\n // Compute the current numCtasX.\n int numCtasX = numCtasPerSeqQ;\n // Update the numCtasY.\n int numCtasY = numCtasForAllHeadsQ * numCtasPerHeadDim;\n // Compute the grid dimension Z.\n int numCtasZ = params.mBatchSize;\n // The 2CtaMma kernels will use 2 Ctas in the x dimension (only used by MLA generation kernels)\n // for heads, so numCtasPerHeadDim and numCtasForAllHeadsQ will be handled by the 2Ctas in the x\n // dimension.\n if (isMlaGenKernel(params) && selectKernelParams.mUses2CtaMma) {\n FLASHINFER_CHECK(numCtasForAllHeadsQ == 2 && numCtasPerHeadDim == 2,\n \"Internal error: numCtasPerHeadDim should be 2.\");\n numCtasX *= 2;\n numCtasY /= (numCtasForAllHeadsQ * numCtasPerHeadDim);\n }\n\n // First split the seqLenKv into multiple CTAs if the utilization is not full.\n // The number of Ctas per KV sequence.\n int numCtasPerSeqKv = 1;\n // Consider the multiCtasKvMode for better GPU utilization.\n if (isMultiCtasKvEnabled(selectKernelParams.mMultiCtasKvMode)) {\n // The maximum attention window (the maximum number of tokensKv that will be attended to).\n int maxAttentionWindow{params.mMaxSeqLenKv};\n // The sparseMla only selects topK tokensKv.\n if (isSparseMla(params.mSparseMlaType)) {\n maxAttentionWindow = std::min(params.mMaxSeqLenKv, params.mSparseMlaTopK);\n }\n // Some of the tilesKv will be skipped if the sliding window attention or chunked attention is\n // used.\n if (isSlidingOrChunkedCausalMask(selectKernelParams.mMaskType)) {\n if (params.mMaxSeqLenKv > params.mAttentionWindowSize) {\n // Consider that the first tileKv might contain tokensKv that is out of the attention\n // window.\n maxAttentionWindow =\n std::min(params.mMaxSeqLenKv, params.mAttentionWindowSize + kernelMeta.mStepKv - 1);\n } else {\n maxAttentionWindow = std::min(params.mMaxSeqLenKv, params.mChunkedAttentionSize);\n }\n }\n\n // The maximum number Ctas per Kv sequence, which makes sure that each CtaKv has work to do.\n // The factor of 2 is applied here to ensure the reduction overhead does not outweigh the\n // benefits of a shorter mainloop.\n int const maxNumCtasPerSeqKv =\n (maxAttentionWindow + 2 * kernelMeta.mStepKv - 1) / (2 * kernelMeta.mStepKv);\n int tunedMaxNumCtasPerSeqKv = maxNumCtasPerSeqKv;\n // Cap BF16Q+FP8KV separate-transform splits so the runtime key selects\n // CGA reduction when the smaller split is expected.\n if (isBf16QFp8KvGeneration() &&\n selectKernelParams.mBf16QFp8KvTransformMode == Bf16QFp8KvTransformMode::SeparateKv &&\n isSwapsMmaAbForGenerationKernel(selectKernelParams.mKernelType) &&\n !isGmemReductionWithSeparateKernel(selectKernelParams.mMultiCtasKvMode) &&\n params.mHeadDimV < 512) {\n int const clusterDimX = selectKernelParams.mUses2CtaMma ? 2 : 1;\n int const maxKvSplitsPerCgaCluster = 16 / clusterDimX;\n if (maxNumCtasPerSeqKv <= numCtasForAllHeadsQ * maxKvSplitsPerCgaCluster) {\n int const launchedClusters =\n flashinfer::ceil_div(numCtasX, clusterDimX) * numCtasY * numCtasZ;\n int const residentSplitBudget = std::max(\n 4, flashinfer::ceil_div(params.mMultiProcessorCount * 13 / 20, launchedClusters));\n int const targetMaxNumCtasPerSeqKv =\n std::min(maxNumCtasPerSeqKv, std::min(maxKvSplitsPerCgaCluster, residentSplitBudget));\n if (targetMaxNumCtasPerSeqKv > 1 && targetMaxNumCtasPerSeqKv < maxNumCtasPerSeqKv) {\n int const targetTileSizePerCtaKv =\n isSlidingOrChunkedCausalMask(selectKernelParams.mMaskType)\n ? flashinfer::ceil_div(params.mAttentionWindowSize,\n targetMaxNumCtasPerSeqKv - 1)\n : flashinfer::ceil_div(maxAttentionWindow, targetMaxNumCtasPerSeqKv);\n if (targetTileSizePerCtaKv <= 1024) {\n tunedMaxNumCtasPerSeqKv = targetMaxNumCtasPerSeqKv;\n }\n }\n }\n }\n // Compute numCtasPerSeqKv.\n numCtasPerSeqKv = std::min(\n tunedMaxNumCtasPerSeqKv,\n std::max(1, int32_t(params.mMultiProcessorCount / (numCtasX * numCtasY * numCtasZ))));\n // Update the numCtasX.\n numCtasX *= numCtasPerSeqKv;\n // The current total number of CTAs.\n int totalNumCtas = numCtasX * numCtasZ * numCtasY;\n // Disable the multiCtasKvMode if there is only one CtaKv.\n if (numCtasPerSeqKv <= 1) {\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::Disabled;\n // Enable the persistent scheduler for better performance.\n selectKernelParams.mTileScheduler = TileScheduler::Persistent;\n // Need to select a different kernel.\n selectKernelParams.mSelectNewKernel = true;\n } else if (totalNumCtas < params.mMultiProcessorCount && isMlaGenKernel(params) &&\n !isSparseMla(params.mSparseMlaType) && selectKernelParams.mTileSizeKv == 128 &&\n getEnvUseTileSizeKv64ForTrtllmGen()) {\n // Use smaller tileSizeKv to fully utilize the SMs.\n selectKernelParams.mTileSizeKv = 64;\n // Need to select a different kernel.\n selectKernelParams.mSelectNewKernel = true;\n }\n\n // The P32 cubin inventory contains an H576/V512 CGA kernel for the split-V\n // headDimPerCtaV=128 form. Let the first selection pass split V, then use CGA for the\n // exact one-token decode shape when the matching dtype-specific cubin is registered.\n bool const useMlaH512Cga = isDsv3MinLatencyMode && params.mMaxSeqLenQ == 1 &&\n selectKernelParams.mNumTokensPerPage == 32 &&\n selectKernelParams.mHeadDimPerCtaV == 128 &&\n selectKernelParams.mTileSizeQ == 16 &&\n hasCgaSmemReductionKernel(params, selectKernelParams);\n bool const useCgaSmemReduction =\n (!isDsv3MinLatencyMode && params.mHeadDimV < 512) || useMlaH512Cga;\n\n // Enable the CgaSmemReduction if the numCtasPerSeqKv <= 16 as the maximum cluster dimension\n // is 16. Only the swapsMmaAbForGeneration kernel supports the CgaSmemReduction for now.\n // Other headDimV >= 512 shapes remain excluded because the cubin inventory is incomplete,\n // and tileSizeQ >= 32 CGA variants can exceed the device shared-memory limit.\n if (useCgaSmemReduction && numCtasPerSeqKv > 1 && numCtasPerSeqKv <= 16 &&\n isSwapsMmaAbForGenerationKernel(selectKernelParams.mKernelType) &&\n isGmemReduction(selectKernelParams.mMultiCtasKvMode) &&\n !selectKernelParams.mForceGmemReduction) {\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::CgaSmemReduction;\n // Need to select a different kernel.\n selectKernelParams.mSelectNewKernel = true;\n }\n\n // Add the debug info when multiCtasKvMode is enabled.\n if (numCtasPerSeqKv > 1) {\n IKL_LOG_DEBUG(\n \"TRTLLM-Gen launch info: multiCtasKvMode is enabled with tileSizeKv = %d, \"\n \"numCtasPerSeqKv = %d, \"\n \"numCtasPerSeqQ = \"\n \"%d, numCtasY = %d, numCtasZ = %d\",\n selectKernelParams.mTileSizeKv, numCtasPerSeqKv, numCtasPerSeqQ, numCtasY, numCtasZ);\n }\n }\n\n // The cluster size in the X dimension.\n int clusterDimX = selectKernelParams.mUses2CtaMma ? 2 : 1;\n if (isCgaSmemReduction(selectKernelParams.mMultiCtasKvMode)) {\n // Note 2CtaMma and CgaSmemReduction cannot be used together currently.\n clusterDimX *= numCtasPerSeqKv;\n }\n\n // Compute the current number of CTAs in total.\n int totalNumCtas = numCtasX * numCtasZ * numCtasY;\n\n // Then split the headDimV into multiple CTAs if there are still unused SMs.\n if (isMlaGenKernel(params) && !selectKernelParams.mGroupsTokensHeadsQ &&\n !selectKernelParams.mReuseSmemKForV && !selectKernelParams.mSelectNewKernel &&\n !selectKernelParams.mUses2CtaMma) {\n // Split the headDimV into multiple CTAs if the utilization is not full.\n // It doesn't work with reuseSmemKForV currently.\n // TODO: find better heuristic of splitting headDimV across multiple CTAs.\n\n int corrFactor = isDsv3MinLatencyMode ? 1 : 2;\n if (selectKernelParams.mHeadDimPerCtaV == 512 &&\n totalNumCtas * corrFactor <= params.mMultiProcessorCount) {\n // Use smaller headDimPerCtaV to fully utilize the SMs.\n selectKernelParams.mHeadDimPerCtaV =\n totalNumCtas * 2 * corrFactor <= params.mMultiProcessorCount ? 128 : 256;\n // Need to select a different kernel.\n selectKernelParams.mSelectNewKernel = true;\n }\n }\n\n // Update the parameters for launching the kernel.\n ctaLaunchParams.mMaxNumCtasQ = numCtasPerSeqQ;\n ctaLaunchParams.mMaxNumCtasKv = numCtasPerSeqKv;\n ctaLaunchParams.mNumCtasX = numCtasX;\n ctaLaunchParams.mNumCtasY = numCtasY;\n ctaLaunchParams.mNumCtasZ = numCtasZ;\n ctaLaunchParams.mClusterDimX = clusterDimX;\n }\n\n // Determine if we should use the SwapsMmaAbForGeneration kernel for MLA generation.\n bool useSwapsMmaAbMlaGenKernel(RunnerParams const& params) const {\n // Use the SwapsMmaAbForGeneration kernel for MLA generation when the following conditions are\n // met:\n // 1. The seqLenPerCtaKv <= 1024 based on the benchmark results (this might be fine-tuned\n // later).\n // 2. The numCtas (after splitting the heads across multiple CTAs) <=\n // params.mMultiProcessorCount.\n\n // The maximum number Ctas per Kv sequence, which makes sure that each CtaKv has work to do.\n // Here we assume the stepKv is 256.\n int const maxNumCtasPerSeqKv = flashinfer::ceil_div(params.mMaxSeqLenKv, 256);\n ;\n // The number of Ctas.\n int const numCtas = static_cast<int32_t>(params.mBatchSize * params.mMaxSeqLenQ *\n flashinfer::ceil_div(params.mNumHeadsQPerKv, 16));\n // Compute numCtasPerSeqKv.\n int const numCtasPerSeqKv =\n std::min(maxNumCtasPerSeqKv, std::max(1, int32_t(params.mMultiProcessorCount / numCtas)));\n // Compute the seqLenPerCtaKv.\n int const seqLenPerCtaKv = flashinfer::ceil_div(params.mMaxSeqLenKv, numCtasPerSeqKv);\n // Whether we should use the SwapsMmaAbForGeneration kernel for MLA generation.\n return seqLenPerCtaKv <= 1024 && numCtas <= params.mMultiProcessorCount;\n }\n\n // Return the smallest shipped MLA head tile that contains a non-power-of-two head group below\n // 64 heads. Power-of-two groups and groups with at least 128 heads return zero so callers\n // preserve their existing heuristics; the unsupported 65-127 gap has no Q128 MLA cubin.\n static int getPaddedMlaTileSizeQ(int numHeadsQPerKv) {\n FLASHINFER_CHECK(numHeadsQPerKv > 0, \"The numHeadsQPerKv must be positive, got %d.\",\n numHeadsQPerKv);\n if (numHeadsQPerKv >= 128 || (numHeadsQPerKv & (numHeadsQPerKv - 1)) == 0) {\n return 0;\n }\n FLASHINFER_CHECK(numHeadsQPerKv <= 64,\n \"Non-power-of-two MLA numHeadsQPerKv must be <= 64, got %d.\", numHeadsQPerKv);\n return std::max(8, flashinfer::UpPowerOfTwo(numHeadsQPerKv));\n }\n\n // Select the sparse MLA generation kernel.\n // Heuristics benchmarked on B200 (SM=148, sparseMlaTopK=2048).\n void selectSparseMlaGenerationKernel(RunnerParams const& params,\n SelectKernelParams& selectKernelParams) const {\n // numHeadsQ <= 32 : SwapsMmaAbForGeneration\n // Non-power-of-two head counts use one padded Q8/Q16/Q32 tile. Power-of-two head counts use\n // tileSizeQ = numHeadsQPerKv/2 at batch=1 or numHeadsQPerKv at batch>=2.\n // Threshold: batchSize * maxNumCtasPerSeqKv <= MP/8 (crossover at batch=1->2 on B200).\n // Benchmarks (seqLen=8192, topK=2048): half tileSizeQ wins by 2-6% at batch=1;\n // full tileSizeQ wins by 2-11% at batch>=2.\n // numHeadsQ > 32 : KeepsMmaAbForGeneration, tileSizeQ = 64\n // numHeadsQ=128 at large batch : 2CTA (clusterDimX=2, headDimPerCtaV=256)\n // otherwise : 1CTA, headDimPerCtaV fine-tuned later\n // Note: at small batch e4m3 prefers SwapsMmaAb tileSizeQ=32 (+10%), but fp16 prefers\n // KeepsMmaAb tileSizeQ=64 (+19% at numHeadsQ=128). We keep KeepsMmaAb for numHeadsQ>=64\n // to avoid penalizing fp16.\n\n FmhaKernelType& kernelType = selectKernelParams.mKernelType;\n int& tileSizeQ = selectKernelParams.mTileSizeQ;\n\n if (params.mNumHeadsQPerKv <= 32) {\n kernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n selectKernelParams.mTileSizeKv = 128;\n // mMultiCtasKvMode defaults to GmemReduction from the constructor. computeCtaAndClusterConfig\n // may upgrade it to CgaSmemReduction; that update is preserved naturally across\n // re-selections. The base tileSizeQ is numHeadsQPerKv (one CTA covers all Q heads per token).\n // At batch=1 the GPU is under-utilized, so we halve tileSizeQ to create 2x more\n // head-splitting CTAs. Threshold: batchSize * maxNumCtasPerSeqKv <= MP/8.\n // effectiveSeqLenKv = min(seqLen, topK) = 2048 -> maxNumCtasPerSeqKv = 16.\n // Condition: batchSize * 16 <= MP/8 -> batchSize <= 1 (crossover at batch=1->2).\n // Only halve when half tileSizeQ >= 8 (no valid SwapsMmaAb kernel below tileSizeQ=8).\n int const fullTileSizeQ = params.mNumHeadsQPerKv;\n int const halfTileSizeQ = fullTileSizeQ / 2;\n int const effectiveSeqLenKv = std::min(params.mMaxSeqLenKv, params.mSparseMlaTopK);\n int const maxNumCtasPerSeqKv =\n flashinfer::ceil_div(effectiveSeqLenKv, selectKernelParams.mTileSizeKv);\n bool const useHalfTileSizeQ = halfTileSizeQ >= 8 && params.mBatchSize * maxNumCtasPerSeqKv <=\n params.mMultiProcessorCount / 8;\n tileSizeQ = useHalfTileSizeQ ? halfTileSizeQ : fullTileSizeQ;\n } else {\n // numHeadsQ > 32: use KeepsMmaAbForGeneration.\n kernelType = FmhaKernelType::KeepsMmaAbForGeneration;\n tileSizeQ = 64;\n selectKernelParams.mTileSizeKv = 128;\n // Upgrade GmemReduction (constructor default) to GmemReductionWithSeparateKernel.\n // If computeCtaAndClusterConfig already set it to Disabled (numCtasPerSeqKv==1), the\n // isGmemReduction() guard is false and the Disabled state is preserved on re-selection.\n if (isGmemReduction(selectKernelParams.mMultiCtasKvMode)) {\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::GmemReductionWithSeparateKernel;\n }\n // For numHeadsQ=128, use 2CTA when there are enough CTAs to amortize 2CTA overhead.\n // numCtasPerToken = numHeadsQPerKv / tileSizeQ (number of CTAs per token per batch item).\n // Benchmarks (fp16/e4m3, sparseMlaTopK=2048):\n // decode, s_q=1:\n // batch=1 : 1CTA wins by ~20%; batch=8 : 1CTA wins by 3-8%\n // batch=16 : 2CTA wins by 8-16%; batch=32+: 2CTA wins by 12-20%\n // prefill/spec, s_q>1, DS MLA generation:\n // 2CTA wins by ~20-50% because it avoids the 1CTA h128 path's duplicated head-dim work.\n // Threshold: batchSize * numCtasPerToken * 8 > MP -> crossover at batch ~ MP/16 ~ 9.\n int const numCtasPerToken = params.mNumHeadsQPerKv / 64;\n bool const use2CtaForMultiTokenMla = params.mMaxSeqLenQ > 1;\n bool const use2Cta = params.mNumHeadsQPerKv == 128 &&\n (use2CtaForMultiTokenMla ||\n params.mBatchSize * numCtasPerToken * 8 > params.mMultiProcessorCount);\n if (use2Cta) {\n selectKernelParams.mUses2CtaMma = true;\n selectKernelParams.mHeadDimPerCtaV = 256;\n }\n }\n // Preserve the legacy heuristic above for power-of-two groups. A non-power-of-two group must\n // fit in one padded tile because the final head CTA cannot process a partial tile.\n if (int const paddedTileSizeQ = getPaddedMlaTileSizeQ(params.mNumHeadsQPerKv);\n paddedTileSizeQ != 0) {\n tileSizeQ = paddedTileSizeQ;\n }\n }\n\n inline bool usesGroupedMlaGenerationKernel(RunnerParams const& params) const {\n bool const usesSupportedDtypes = (mDtypeQ == DATA_TYPE_BF16 && mDtypeK == DATA_TYPE_BF16 &&\n mDtypeV == DATA_TYPE_BF16 && mDtypeOut == DATA_TYPE_BF16) ||\n (mDtypeQ == DATA_TYPE_E4M3 && mDtypeK == DATA_TYPE_E4M3 &&\n mDtypeV == DATA_TYPE_E4M3 && mDtypeOut == DATA_TYPE_BF16);\n bool const usesSupportedHeadRatio =\n params.mNumHeadsQPerKv == 8 || params.mNumHeadsQPerKv == 16 || params.mNumHeadsQPerKv == 32;\n\n return !isSparseMla(params.mSparseMlaType) && params.mMaxSeqLenQ > 1 &&\n usesSupportedHeadRatio && params.mBatchSize >= 1 && params.mBatchSize <= 16 &&\n params.mNumTokensPerPage == 32 && params.mHeadDimQk == 576 && params.mHeadDimV == 512 &&\n usesSupportedDtypes;\n }\n\n // Grouped MLA generation packs query tokens and local Q heads into Q64 CTAs.\n void selectGroupedMlaGenerationKernel(RunnerParams const& params,\n SelectKernelParams& selectKernelParams) const {\n selectKernelParams.mKernelType = FmhaKernelType::KeepsMmaAbForGeneration;\n selectKernelParams.mTileSizeQ = 64;\n selectKernelParams.mTileSizeKv = 128;\n // Preserve Disabled/Persistent selected by an earlier low-KV pass.\n if (isMultiCtasKvEnabled(selectKernelParams.mMultiCtasKvMode)) {\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::GmemReductionWithSeparateKernel;\n selectKernelParams.mTileScheduler = TileScheduler::Static;\n }\n selectKernelParams.mForceGmemReduction = true;\n selectKernelParams.mMaskType = TrtllmGenAttentionMaskType::Dense;\n selectKernelParams.mReuseSmemKForV = false;\n selectKernelParams.mGroupsTokensHeadsQ = true;\n selectKernelParams.mUses2CtaMma = false;\n\n int const groupedRows = params.mMaxSeqLenQ * params.mNumHeadsQPerKv;\n int const baseNumCtas =\n params.mBatchSize * params.mNumHeadsKv * flashinfer::ceil_div(groupedRows, 64);\n if (baseNumCtas <= 1) {\n selectKernelParams.mHeadDimPerCtaV = 128;\n } else if (baseNumCtas <= 4) {\n selectKernelParams.mHeadDimPerCtaV = 256;\n } else {\n selectKernelParams.mHeadDimPerCtaV = 512;\n }\n selectKernelParams.mHeadDimPerCtaV =\n std::min(selectKernelParams.mHeadDimPerCtaV, params.mHeadDimV);\n }\n\n // Select the MLA generation kernel.\n void selectMlaGenerationKernel(RunnerParams const& params,\n SelectKernelParams& selectKernelParams) const {\n if (usesGroupedMlaGenerationKernel(params)) {\n selectGroupedMlaGenerationKernel(params, selectKernelParams);\n return;\n }\n selectKernelParams.mGroupsTokensHeadsQ = false;\n\n // The kernel type.\n FmhaKernelType& kernelType = selectKernelParams.mKernelType;\n // The tile size for Q.\n int& tileSizeQ = selectKernelParams.mTileSizeQ;\n\n if (isSparseMla(params.mSparseMlaType)) {\n selectSparseMlaGenerationKernel(params, selectKernelParams);\n } else {\n int const paddedTileSizeQ = getPaddedMlaTileSizeQ(params.mNumHeadsQPerKv);\n // Non-sparse MLA: use SwapsMmaAb when numHeadsQPerKv <= 32 or seqLenPerCtaKv is small.\n // Padded Q64 must use KeepsMmaAb so split-KV also follows its standalone-reducer path.\n bool const useSwapsMmaAb =\n paddedTileSizeQ != 0 ? paddedTileSizeQ <= 32\n : params.mNumHeadsQPerKv <= 32 || useSwapsMmaAbMlaGenKernel(params);\n\n if (useSwapsMmaAb) {\n kernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n tileSizeQ = paddedTileSizeQ != 0 ? paddedTileSizeQ : (params.mNumHeadsQPerKv <= 8 ? 8 : 16);\n } else {\n kernelType = FmhaKernelType::KeepsMmaAbForGeneration;\n tileSizeQ = 64;\n // Always use the separate reduction kernel.\n if (isMultiCtasKvEnabled(selectKernelParams.mMultiCtasKvMode)) {\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::GmemReductionWithSeparateKernel;\n }\n // For non-sparse MLA, always use 2CTA for numHeadsQPerKv=128 (legacy behavior).\n if (params.mNumHeadsQPerKv == 128) {\n selectKernelParams.mUses2CtaMma = true;\n selectKernelParams.mHeadDimPerCtaV = 256;\n }\n }\n }\n }\n\n void syncGqaGenerationTraitsForKernelHash(RunnerParams const& params,\n SelectKernelParams& selectKernelParams) const {\n // Same-dtype GQA generation cubins export this trait for every tile size, including runtime\n // shapes where the resulting CTA covers only one query token.\n selectKernelParams.mGroupsTokensHeadsQ = true;\n bool const multiCtasKvEnabled = isMultiCtasKvEnabled(selectKernelParams.mMultiCtasKvMode);\n if (selectKernelParams.mKernelType == FmhaKernelType::KeepsMmaAbForGeneration &&\n params.mHeadDimV > 256) {\n // Current GQA keepsMmaAb H512 cubins are registered in the split-V\n // headDimPerCtaV=256 form; full-V H512 is a cubin coverage follow-up.\n selectKernelParams.mHeadDimPerCtaV = 256;\n if (multiCtasKvEnabled) {\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::GmemReductionWithSeparateKernel;\n }\n } else {\n // SwapsMmaAb hashes the full-V form; undo a previous keepsMmaAb separate-reduction upgrade\n // when the tile-size cost model walks back to swapsMmaAb.\n selectKernelParams.mHeadDimPerCtaV = params.mHeadDimV;\n if (multiCtasKvEnabled &&\n selectKernelParams.mMultiCtasKvMode == MultiCtasKvMode::GmemReductionWithSeparateKernel) {\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::GmemReduction;\n }\n }\n }\n\n // Selects a heuristic tileSizeQ if groupsTokensHeadsQ is true.\n void selectTileSizeQForGqaGeneration(RunnerParams const& params,\n SelectKernelParams& selectKernelParams) const {\n // Define the per-tile mainloop cost model for different tileSizeQ choices.\n std::unordered_map<int, float> kernelMainloopCost = {\n {128, 2.2}, // Cost factor when tileSizeQ = 128\n {64, 1.68}, // Cost factor when tileSizeQ = 64\n {32, 1.48}, // Cost factor when tileSizeQ = 32\n {16, 1.2}, // Cost factor when tileSizeQ = 16\n {8, 1.0} // Cost factor when tileSizeQ = 8\n };\n\n bool const isBf16QFp8KvFullTransform =\n isBf16QFp8KvGeneration() &&\n selectKernelParams.mBf16QFp8KvTransformMode == Bf16QFp8KvTransformMode::SeparateKv;\n\n // Define the per-tile reduction cost model for different tileSizeQ choices.\n std::unordered_map<int, float> kernelReductionCost = {\n {128, 1.32}, // Reduction cost factor when tileSizeQ = 128\n {64, 1.2}, // Reduction cost factor when tileSizeQ = 64\n {32, 1.08}, // Reduction cost factor when tileSizeQ = 32\n {16, 1.03}, // Reduction cost factor when tileSizeQ = 16\n {8, 1.0} // Reduction cost factor when tileSizeQ = 8\n };\n\n // Full-transform kernels pay conversion work in the KV mainloop, so bias the model toward\n // keeping enough KV parallelism without changing the reduction model.\n float const kernelMainloopCostFactor = isBf16QFp8KvFullTransform ? 2.0f : 1.0f;\n // The reduction cost emulated as a sequence length factor.\n float const kernelReductionSeqLenFactor = 128.0f;\n\n // The parameters for launching the kernel.\n CtaLaunchParams ctaLaunchParams;\n // The copy of the selectKernelParams, which makes sure it won't modify the original\n // selectKernelParams when computing the number of CTAs.\n SelectKernelParams selectKernelParamsCopy = selectKernelParams;\n // Load the kernel.\n auto [func, kernelMeta] = loadKernel(params, selectKernelParamsCopy);\n // Compute numCtasX, numCtasY and numCtasZ.\n computeCtaAndClusterConfig(ctaLaunchParams, params, kernelMeta, selectKernelParamsCopy);\n\n // If there are no free SMs or tileSizeQ is already the smallest one, skip the heuristic\n // selection.\n if (ctaLaunchParams.mNumCtasX * ctaLaunchParams.mNumCtasY * ctaLaunchParams.mNumCtasZ * 2 >\n params.mMultiProcessorCount ||\n selectKernelParamsCopy.mTileSizeQ <= 8) {\n // No need to select the kernel further.\n return;\n }\n\n // Candidate tile sizes for tileSizeQ to explore.\n int const candidateTileSizesQ[] = {128, 64, 32, 16, 8};\n\n // The default tileSizeQ.\n int defaultTileSizeQ = selectKernelParamsCopy.mTileSizeQ;\n // The selected tileSizeQ.\n int selectedTileSizeQ = selectKernelParamsCopy.mTileSizeQ;\n\n // The minimum modeling kernel time.\n float globalModelingKernelTime = FLT_MAX;\n // Loop over each candidate tile size.\n for (int tileSizeQ : candidateTileSizesQ) {\n // Only consider candidates <= default tileSizeQ and ensure each CTA processes full\n // numHeadsQPerKv.\n if (tileSizeQ > defaultTileSizeQ || tileSizeQ < params.mNumHeadsQPerKv) {\n continue;\n }\n\n selectKernelParamsCopy.mTileSizeQ = tileSizeQ;\n if (tileSizeQ >= 64) {\n selectKernelParamsCopy.mKernelType = FmhaKernelType::KeepsMmaAbForGeneration;\n } else {\n selectKernelParamsCopy.mKernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n }\n // Keep headDimPerCtaV and multiCtasKvMode in sync with the candidate kernelType so\n // loadKernel hashes a registered kernel.\n syncGqaGenerationTraitsForKernelHash(params, selectKernelParamsCopy);\n\n // Load the kernel.\n std::tie(func, kernelMeta) = loadKernel(params, selectKernelParamsCopy);\n\n // Compute the number of CTAs.\n computeCtaAndClusterConfig(ctaLaunchParams, params, kernelMeta, selectKernelParamsCopy);\n\n // Compute the seqLenPerCtaKv.\n int32_t seqLenPerCtaKv =\n flashinfer::ceil_div(flashinfer::ceil_div(params.mMaxSeqLenKv, kernelMeta.mStepKv),\n ctaLaunchParams.mMaxNumCtasKv) *\n kernelMeta.mStepKv;\n\n // Compute the modeling kernel time = mainloop cost + reduction cost.\n float modelingKernelTime =\n kernelMainloopCostFactor * kernelMainloopCost.at(tileSizeQ) * seqLenPerCtaKv +\n kernelReductionCost.at(tileSizeQ) * kernelReductionSeqLenFactor *\n ctaLaunchParams.mMaxNumCtasKv;\n\n // Compute the total number of CTAs.\n int32_t numCtas =\n ctaLaunchParams.mNumCtasX * ctaLaunchParams.mNumCtasY * ctaLaunchParams.mNumCtasZ;\n // Compute the number of waves.\n int32_t numWaves = flashinfer::ceil_div(numCtas, params.mMultiProcessorCount);\n // Compute the total modeling kernel time.\n modelingKernelTime *= numWaves;\n\n // If this candidate has a lower time than the global minimum, update the global minimum.\n if (modelingKernelTime < globalModelingKernelTime) {\n globalModelingKernelTime = modelingKernelTime;\n selectedTileSizeQ = tileSizeQ;\n }\n }\n\n // Update the tileSizeQ.\n selectKernelParams.mTileSizeQ = selectedTileSizeQ;\n // Update the kernel type.\n if (selectKernelParams.mTileSizeQ >= 64) {\n selectKernelParams.mKernelType = FmhaKernelType::KeepsMmaAbForGeneration;\n } else {\n selectKernelParams.mKernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n }\n // Apply the same sync to the committed kernelType; the probe above mutated only the copy.\n syncGqaGenerationTraitsForKernelHash(params, selectKernelParams);\n }\n\n // Selects a heuristic kernel for GQA generation.\n void selectGqGenerationKernel(RunnerParams const& params,\n SelectKernelParams& selectKernelParams) const {\n // The kernel type.\n FmhaKernelType& kernelType = selectKernelParams.mKernelType;\n // The tile size for Q.\n int& tileSizeQ = selectKernelParams.mTileSizeQ;\n selectKernelParams.mGroupsTokensHeadsQ = false;\n\n // Generic mixed precision kernels don't work with groupsTokensHeadsQ = true. BF16Q+FP8KV\n // transform paths present BF16 K to BMM1, so they can use the grouped-token cubins.\n if (!supportsGqaGroupingTokensHeadsQ(selectKernelParams)) {\n selectKernelParams.mGroupsTokensHeadsQ = false;\n tileSizeQ = params.mNumHeadsQPerKv <= 8 ? 8 : 16;\n kernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n return;\n }\n selectKernelParams.mGroupsTokensHeadsQ = true;\n\n // The number of tokensQ and headsQ that can be grouped into one CTA.\n int numTokensHeadsQ = params.mNumHeadsQPerKv * params.mMaxSeqLenQ;\n // When numHeadsQPerKv >= 64, use KeepsMmaAbForGeneration kernel.\n if (numTokensHeadsQ <= 8) {\n tileSizeQ = 8;\n kernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n } else if (numTokensHeadsQ <= 16) {\n tileSizeQ = 16;\n kernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n } else if (numTokensHeadsQ <= 32) {\n tileSizeQ = 32;\n kernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n } else if (numTokensHeadsQ <= 64) {\n tileSizeQ = 64;\n kernelType = FmhaKernelType::KeepsMmaAbForGeneration;\n } else {\n tileSizeQ = 128;\n kernelType = FmhaKernelType::KeepsMmaAbForGeneration;\n }\n\n // Normalize traits before the cost-model probe calls loadKernel().\n syncGqaGenerationTraitsForKernelHash(params, selectKernelParams);\n\n // When maxSeqLenQ > 1, use an experimental kernel-timing model to select the best kernel that\n // groups both tokensQ and headsQ into one CTA.\n if (params.mMaxSeqLenQ > 1) {\n selectTileSizeQForGqaGeneration(params, selectKernelParams);\n }\n }\n\n // Select a kernel based on the heuristic.\n void selectKernel(RunnerParams const& params, SelectKernelParams& selectKernelParams) const {\n // Normalize this before heuristic probing; some GQA-generation heuristics load candidate\n // kernels while selecting tileSizeQ.\n selectNumTokensPerPage(params, selectKernelParams);\n bool const isMlaGeneration = isGenerationKernel(params.mKernelType) && isMlaGenKernel(params);\n\n // Select the kernel based on the kernel type.\n if (isMlaGeneration) {\n selectMlaGenerationKernel(params, selectKernelParams);\n // TRTLLM-GEN MLA generation kernels are exported with dense mask metadata. Each generation\n // CTA processes a bounded query tile, so the runtime sequence lengths/indices provide the\n // effective masking.\n selectKernelParams.mMaskType = TrtllmGenAttentionMaskType::Dense;\n if (!isSparseMla(params.mSparseMlaType)) {\n FLASHINFER_CHECK(\n params.mMaxSeqLenKv <= params.mAttentionWindowSize &&\n params.mChunkedAttentionSize == INT_MAX,\n \"TRTLLM-GEN MLA generation does not support sliding-window or chunked attention.\");\n }\n } else if (isGenerationKernel(params.mKernelType)) {\n selectGqGenerationKernel(params, selectKernelParams);\n }\n\n // For headDimV > 256, set headDimPerCtaV to 256 for context and keepsMmaAbForGeneration\n // kernels. swapsMmaAbForGeneration has enough TMEM resources to hold the full headDimV.\n // Called for context and GQA generation; MLA sets headDimPerCtaV separately.\n if (params.mHeadDimV > 256 && !isMlaGenKernel(params) &&\n !isSwapsMmaAbForGenerationKernel(selectKernelParams.mKernelType)) {\n selectKernelParams.mHeadDimPerCtaV = 256;\n }\n\n // Enable sliding window or chunked causal if the max kv sequence length exceeds attention\n // window size or chunked attention size. This is supported by causal-mask context kernels and\n // generation-phase kernels.\n if (!isSparseMla(params.mSparseMlaType) &&\n (selectKernelParams.mMaskType == TrtllmGenAttentionMaskType::Causal ||\n !isContextKernel(params.mKernelType)) &&\n (params.mMaxSeqLenKv > params.mAttentionWindowSize ||\n params.mChunkedAttentionSize != INT_MAX)) {\n FLASHINFER_CHECK(\n params.mMaxSeqLenKv <= params.mAttentionWindowSize ||\n params.mMaxSeqLenKv <= params.mChunkedAttentionSize,\n \"Sliding window attention and chunked attention should not be used together\");\n selectKernelParams.mMaskType = TrtllmGenAttentionMaskType::SlidingOrChunkedCausal;\n }\n }\n\n std::pair<uint64_t, std::string> hashFromRunnerParams(\n RunnerParams const& params, SelectKernelParams& selectKernelParams) const {\n // Debug info.\n std::string info =\n \"qkvLayout=\" + std::to_string(static_cast<int>(params.mQkvLayout)) +\n \", maskType=\" + std::to_string(static_cast<int>(selectKernelParams.mMaskType)) +\n \", kernelType=\" + std::to_string(static_cast<int>(selectKernelParams.mKernelType)) +\n \", tileScheduler=\" + std::to_string(static_cast<int>(selectKernelParams.mTileScheduler)) +\n \", multiCtasKvMode=\" +\n std::to_string(static_cast<int>(selectKernelParams.mMultiCtasKvMode)) +\n \", headDimPerCtaV=\" + std::to_string(selectKernelParams.mHeadDimPerCtaV) +\n \", headDimQk=\" + std::to_string(params.mHeadDimQk) +\n \", headDimV=\" + std::to_string(params.mHeadDimV) +\n \", tileSizeQ=\" + std::to_string(selectKernelParams.mTileSizeQ) +\n \", tileSizeKv=\" + std::to_string(selectKernelParams.mTileSizeKv) +\n \", numTokensPerPage=\" + std::to_string(selectKernelParams.mNumTokensPerPage) +\n \", dynamicNumTokensPerPage=\" + std::to_string(selectKernelParams.mDynamicNumTokensPerPage) +\n \", reuseSmemKForV=\" + std::to_string(selectKernelParams.mReuseSmemKForV) +\n \", uses2CtaMma=\" + std::to_string(selectKernelParams.mUses2CtaMma) +\n \", groupsTokensHeadsQ=\" + std::to_string(selectKernelParams.mGroupsTokensHeadsQ) +\n \", sparseMlaType=\" + std::to_string(static_cast<int>(params.mSparseMlaType)) +\n \", skipsSoftmax=\" + std::to_string(selectKernelParams.mSkipsSoftmaxWhenPossible) +\n \", bf16QFp8KvTransformMode=\" +\n std::to_string(static_cast<int>(selectKernelParams.mBf16QFp8KvTransformMode)) +\n \", fp16Softmax=\" + std::to_string(selectKernelParams.mUseFp16Softmax) +\n \", usesSpcompress=\" + std::to_string(selectKernelParams.mUsesSpcompress);\n IKL_LOG_DEBUG(\n \"Searching for kernel traits (%d available) in TllmGenFmhaKernel(%s, %s, %s, %s, %d) %s\",\n getNumLoadedKernels(), toStr(mDtypeQ), toStr(mDtypeK), toStr(mDtypeV), toStr(mDtypeOut),\n mSM, info.c_str());\n\n return std::make_pair(\n hashID(static_cast<int>(params.mQkvLayout), static_cast<int>(selectKernelParams.mMaskType),\n static_cast<int>(selectKernelParams.mKernelType),\n static_cast<int>(selectKernelParams.mTileScheduler),\n static_cast<int>(selectKernelParams.mMultiCtasKvMode),\n selectKernelParams.mHeadDimPerCtaV, params.mHeadDimQk, params.mHeadDimV,\n selectKernelParams.mTileSizeQ, selectKernelParams.mTileSizeKv,\n selectKernelParams.mNumTokensPerPage, selectKernelParams.mDynamicNumTokensPerPage,\n selectKernelParams.mReuseSmemKForV, selectKernelParams.mUses2CtaMma,\n selectKernelParams.mGroupsTokensHeadsQ, static_cast<int>(params.mSparseMlaType),\n selectKernelParams.mSkipsSoftmaxWhenPossible,\n static_cast<int>(selectKernelParams.mBf16QFp8KvTransformMode),\n /*uses2QSlidingWindowKernel=*/false, selectKernelParams.mUseFp16Softmax,\n selectKernelParams.mUsesSpcompress),\n info);\n }\n\n // Load a single kernel (called by `run()` when needed).\n std::pair<CUfunction, KernelMeta> loadKernel(RunnerParams const& params,\n SelectKernelParams& selectKernelParams) const {\n // Hash the runner params.\n auto [hashId, info] = hashFromRunnerParams(params, selectKernelParams);\n auto const findMetaIter = mKernelMetaMap.find(hashId);\n\n // Add debug info when kernels are not found.\n FLASHINFER_CHECK(findMetaIter != mKernelMetaMap.end(), \"Trtllm-gen kernels not found: \" + info);\n\n // The meta index.\n auto const metaIndex = findMetaIter->second;\n\n // Load the function if not found.\n if (mFunctions.find(hashId) == mFunctions.end()) {\n // Load the kernel on-demand.\n auto const& kernelMeta = mKernelMeta[metaIndex];\n CUmodule hmod{0};\n std::string kernelName(kernelMeta.mFuncName);\n\n // Check if the module is already loaded.\n auto findModuleIter = mModules.find(kernelMeta.mFuncName);\n auto capitalizeFirst = [](std::string str) {\n if (!str.empty()) {\n str[0] = std::toupper(str[0]);\n }\n return str;\n };\n if (findModuleIter == mModules.end()) {\n // Load the module.\n std::string cubin_path = tllm_gen_fmha_cubin_path + \"/\" + kernelMeta.mFuncName + \".cubin\";\n std::string cubin = getCubin(cubin_path, kernelMeta.sha256);\n if (cubin.empty()) {\n throw std::runtime_error(\"Failed to load cubin for \" + kernelName);\n }\n cuErrCheck(cuModuleLoadData(&hmod, cubin.data()));\n mModules[kernelName] = hmod;\n } else {\n hmod = findModuleIter->second;\n }\n\n // Load the function.\n KernelInfo funcInfo;\n funcInfo.mMetaInfoIndex = metaIndex;\n cuErrCheck(cuModuleGetFunction(&funcInfo.mDeviceFunction, hmod, kernelMeta.mFuncName));\n\n setupKernelSmem(funcInfo.mDeviceFunction, kernelMeta);\n\n // Cache the loaded function.\n mFunctions[hashId] = funcInfo;\n }\n\n // Retrieve the loaded kernel.\n auto const& kernelInfo = mFunctions.at(hashId);\n auto const& kernelMeta = mKernelMeta[kernelInfo.mMetaInfoIndex];\n CUfunction func = kernelInfo.mDeviceFunction;\n\n // Return the function and kernelMeta.\n return std::make_pair(func, kernelMeta);\n }\n\n Data_type mDtypeQ, mDtypeK, mDtypeV, mDtypeOut;\n int mNumEltsPerSageAttnBlkQ, mNumEltsPerSageAttnBlkK, mNumEltsPerSageAttnBlkP,\n mNumEltsPerSageAttnBlkV;\n KernelMeta const* mKernelMeta;\n unsigned int mKernelMetaCount;\n unsigned int mSM;\n unsigned int mMaxDeviceSmemSize;\n mutable std::unordered_map<std::string, CUmodule> mModules;\n\n mutable std::unordered_map<uint64_t, unsigned int> mKernelMetaMap;\n\n struct KernelInfo {\n unsigned int mMetaInfoIndex;\n CUfunction mDeviceFunction;\n };\n\n mutable std::unordered_map<uint64_t, KernelInfo> mFunctions;\n};\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n\nclass TllmFmhaKernelFactory {\n public:\n using KernelType = TllmGenFmhaKernel;\n\n KernelType const* getKernels(const typename KernelType::KernelMeta* pKernelList,\n unsigned int nbKernels, Data_type dtypeQ, Data_type dtypeK,\n Data_type dtypeV, Data_type dtypeOut, unsigned int sm,\n int numEltsPerSageAttnBlkQ = 0, int numEltsPerSageAttnBlkK = 0,\n int numEltsPerSageAttnBlkP = 0, int numEltsPerSageAttnBlkV = 0) {\n static std::mutex s_mutex;\n std::lock_guard<std::mutex> lg(s_mutex);\n\n auto const id = hashID(dtypeQ, dtypeK, dtypeV, dtypeOut, sm, numEltsPerSageAttnBlkQ,\n numEltsPerSageAttnBlkK, numEltsPerSageAttnBlkP, numEltsPerSageAttnBlkV);\n auto const findIter = mKernels.find(id);\n if (findIter == mKernels.end()) {\n KernelType* newKernel = new KernelType{pKernelList,\n nbKernels,\n dtypeQ,\n dtypeK,\n dtypeV,\n dtypeOut,\n sm,\n numEltsPerSageAttnBlkQ,\n numEltsPerSageAttnBlkK,\n numEltsPerSageAttnBlkP,\n numEltsPerSageAttnBlkV};\n newKernel->loadKernels();\n mKernels.insert(std::make_pair(id, std::unique_ptr<KernelType>(newKernel)));\n IKL_LOG_DEBUG(\n \"Loading new kernel for dtypeQ=%s, dtypeK=%s, dtypeV=%s, dtypeOut=%s, sm=%d with %d \"\n \"loaded kernels\",\n toStr(dtypeQ), toStr(dtypeK), toStr(dtypeV), toStr(dtypeOut), sm,\n newKernel->getNumLoadedKernels());\n return newKernel;\n }\n return findIter->second.get();\n }\n\n static TllmFmhaKernelFactory& Get() {\n int deviceId;\n cudaGetDevice(&deviceId);\n static std::unique_ptr<TllmFmhaKernelFactory> sFactory[32] = {nullptr};\n if (sFactory[deviceId] == nullptr) {\n FLASHINFER_CHECK(deviceId < 32, \"Invalid deviceId %d (max is 32 devices)\", deviceId);\n sFactory[deviceId] = std::make_unique<TllmFmhaKernelFactory>(TllmFmhaKernelFactory());\n }\n\n return *(sFactory[deviceId]);\n }\n\n private:\n TllmFmhaKernelFactory() = default;\n\n inline uint64_t hashID(Data_type dtypeQ, Data_type dtypeK, Data_type dtypeV, Data_type dtypeOut,\n unsigned int sm, int numEltsPerSageAttnBlkQ, int numEltsPerSageAttnBlkK,\n int numEltsPerSageAttnBlkP, int numEltsPerSageAttnBlkV) const {\n // Encode sage block sizes as log2(size)+1 (0 when unused) to fit in 4 bits each.\n auto const sageEncode = [](int n) -> uint64_t {\n return n > 0 ? static_cast<uint64_t>(log2f(static_cast<float>(n))) + 1 : 0;\n };\n // Bit layout:\n // Bits 0-15: sm\n // Bits 16-19: dtypeQ\n // Bits 20-23: dtypeK\n // Bits 24-27: dtypeV\n // Bits 28-31: dtypeOut\n // Bits 32-35: numEltsPerSageAttnBlkQ (log2+1 encoding)\n // Bits 36-39: numEltsPerSageAttnBlkK\n // Bits 40-43: numEltsPerSageAttnBlkP\n // Bits 44-47: numEltsPerSageAttnBlkV\n return static_cast<uint64_t>(sm) | static_cast<uint64_t>(dtypeQ) << 16 |\n static_cast<uint64_t>(dtypeK) << 20 | static_cast<uint64_t>(dtypeV) << 24 |\n static_cast<uint64_t>(dtypeOut) << 28 | sageEncode(numEltsPerSageAttnBlkQ) << 32 |\n sageEncode(numEltsPerSageAttnBlkK) << 36 | sageEncode(numEltsPerSageAttnBlkP) << 40 |\n sageEncode(numEltsPerSageAttnBlkV) << 44;\n }\n\n std::unordered_map<uint64_t, const std::unique_ptr<KernelType>> mKernels;\n};\n\ninline TllmGenFmhaKernel const* getTllmFmhaKernels(Data_type dtypeQ, Data_type dtypeK,\n Data_type dtypeV, Data_type dtypeOut,\n unsigned int sm, int numEltsPerSageAttnBlkQ = 0,\n int numEltsPerSageAttnBlkK = 0,\n int numEltsPerSageAttnBlkP = 0,\n int numEltsPerSageAttnBlkV = 0) {\n#ifndef EXCLUDE_SM_100\n return TllmFmhaKernelFactory::Get().getKernels(\n tensorrt_llm::kernels::sTllmGenFmhaKernelMetaInfos,\n sizeof(tensorrt_llm::kernels::sTllmGenFmhaKernelMetaInfos) /\n sizeof(tensorrt_llm::kernels::sTllmGenFmhaKernelMetaInfos[0]),\n dtypeQ, dtypeK, dtypeV, dtypeOut, sm, numEltsPerSageAttnBlkQ, numEltsPerSageAttnBlkK,\n numEltsPerSageAttnBlkP, numEltsPerSageAttnBlkV);\n#else\n return nullptr;\n#endif // EXCLUDE_SM_100\n}\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## 📌 Description\n\n### Summary\n\nThis PR restricts the sparse-MLA half-Q-tile heuristic to short queries\n(`mMaxSeqLenQ <= 16`). Short decode/MTP queries retain the existing Q8 choice,\nwhile long-query DeepSeek-V4 prefill uses Q16.\n\nThe existing heuristic considers the number of KV-split CTAs and batch size,\nbut not the amount of Q-axis parallelism. For the DeepSeek-V4 prefill case on\nB200:\n\n- `numHeadsQPerKv = 16`, so the full and half Q tiles are Q16 and Q8.\n- `maxNumCtasPerSeqKv = ceil(min(maxSeqLenKv, sparseMlaTopK) / tileSizeKv)`.\n- With `sparseMlaTopK = 2048` and `tileSizeKv = 128`,\n `maxNumCtasPerSeqKv = 16`.\n- At batch 1 on a 148-SM B200, `1 * 16 <= 148 / 8`, so the current condition\n selects Q8 even when `maxSeqLenQ = 16384`.\n\nQ8 is useful for short batch-1 queries because it creates more head-splitting\nCTAs. A 16K query already supplies 16K-way Q-axis parallelism. In that case Q8\nchanges the main-kernel grid from `(16384, 1, 1)` to `(16384, 2, 1)` and makes\ntwo CTAs load the same sparse KV set for the two eight-head groups. Q16 avoids\nthat duplicated KV traffic.\n\nNo new cubin is required: both Q8 and Q16 variants are already shipped. The\nchange only narrows the host-side selector condition.\n\n### vLLM DeepSeek-V4 prefill call site\n\nvLLM invokes this generation-form FlashInfer API from its DeepSeek-V4\n`_forward_prefill` path: [`flashinfer_sparse.py:L781-L886`](https://github.com/vllm-project/vllm/blob/728d3ad09/vllm/models/deepseek_v4/nvidia/flashinfer_sparse.py#L781-L886).\nSpecifically, `_forward_prefill` calls\n`flashinfer_trtllm_batch_decode_sparse_mla_dsv4(query=q_chunk, ...)`, which is\nwhy prefill reaches `selectSparseMlaGenerationKernel()`.\n\n### Native FlashInfer B200 benchmark\n\nThis PR adds `trtllm_batch_decode_sparse_mla_dsv4` as a first-class attention\nroutine in the repository's canonical `benchmarks/flashinfer_benchmark.py`\ndriver. It uses the public FlashInfer API and the driver's existing backend\nfiltering, common CLI flags, `bench_gpu_time`, cold-L2 handling, CSV schema,\ntest-list execution, and generated reproduction commands. Correctness is\nchecked before timing against an independent sampled FP32 attention oracle.\n\nNative benchmark contract:\n\n- 1x NVIDIA B200; PyTorch `2.13.0+cu130`; FlashInfer `0.6.16.post3`.\n- Batch 1, 16 Q heads, head dim 512, FP8 E4M3 Q/KV, BF16 output.\n- KV sequence length 16,384; 128 SWA + 1,920 compressed entries per query\n (`sparseMlaTopK=2048`); HND cache layout; PDL disabled.\n- Query lengths `1,8,16,17,32,256,4096,16384` cover both sides of the guard\n and the target long-prefill case.\n- Canonical `bench_gpu_time`: cold L2, 20 untimed warmups and 100 measured\n iterations per case. `cupti-python` was absent in the application image, so\n the driver used its documented CUDA-event fallback.\n- Sampled FP32 reference checking ran before timing for every case. All BF16\n outputs were finite and the maximum absolute error was `1.81e-4`.\n\nFrom the FlashInfer repository root, the target 16K case can be reproduced\nwith the canonical benchmark driver as follows:\n\n```bash\npython3 benchmarks/flashinfer_benchmark.py \\\n --routine trtllm_batch_decode_sparse_mla_dsv4 \\\n --backends trtllm-gen \\\n --batch_size 1 \\\n --s_qo 16384 \\\n --s_kv 16384 \\\n --num_qo_heads 16 \\\n --num_kv_heads 1 \\\n --head_dim_qk 512 \\\n --head_dim_vo 512 \\\n --page_size 256 \\\n --swa_topk 128 \\\n --compressed_kv_len 4096 \\\n --compressed_page_size 64 \\\n --compressed_topk 1920 \\\n --kv_layout HND \\\n --q_dtype fp8_e4m3 \\\n --kv_dtype fp8_e4m3 \\\n --out_dtype bfloat16 \\\n --no_cuda_graph \\\n --refcheck \\\n --dry_run_iters 20 \\\n --num_iters 100 \\\n --generate_repro_command \\\n --case_tag dsv4-q16384 \\\n -vv\n```\n\nFor the full boundary sweep, repeat the same command with\n`--s_qo 1, 8, 16, 17, 32, 256, 4096, 16384` individually. Parent and PR\nmeasurements must be run from their respective source checkouts with a freshly\nbuilt `fmha_gen` host launcher; an installed AOT launcher can otherwise hide\nthe selector change.\n\n| Q length | Parent tile | PR tile | Parent (ms) | PR (ms) | Speedup |\n|---:|:---:|:---:|---:|---:|---:|\n| 1 | Q8 | Q8 | 0.027616 | 0.027616 | 1.000x |\n| 8 | Q8 | Q8 | 0.027648 | 0.027584 | 1.002x |\n| 16 | Q8 | Q8 | 0.029696 | 0.029680 | 1.001x |\n| 17 | Q8 | Q16 | 0.029696 | 0.025568 | 1.162x |\n| 32 | Q8 | Q16 | 0.037920 | 0.029696 | 1.277x |\n| 256 | Q8 | Q16 | 0.134144 | 0.080736 | 1.662x |\n| 4,096 | Q8 | Q16 | 1.565744 | 0.825200 | **1.897x** |\n| 16,384 | Q8 | Q16 | 4.931104 | 2.614256 | **1.886x** |\n\nThe canonical-run logs show that the kernel name stays Q8 through `Q=16` and\nchanges to Q16 at `Q=17`, exactly matching the new boundary. At the target\n`Q=16384`, the native API result is a 46.99% latency reduction. The `Q<=16`\narms use the same Q8 selector path and agree within 0.23%.\n\n### vLLM DeepSeek-V4 B200 benchmark\n\nHardware and software:\n\n- 8x NVIDIA B200, TP=8\n- DeepSeek-V4-Pro, FP8 KV cache, block size 256\n- vLLM `0.1.dev19908+g728d3ad09`\n- FlashInfer `0.6.16.post3`\n- Image `vllm/vllm-openai:nightly-dev-x86_64-cu13.0.1-728d3ad`\n (SHA-256 `9d812de47e34568de2a945635dd29cf2d6784fee62e3a602283d2665a9459cac`)\n- `FLASHINFER_MLA_SPARSE_DSV4`, prefill-query quantization enabled, FP4\n indexer cache enabled, MTP=3\n- Concurrency 16, ISL=16,384, OSL=1, seed 42,\n `max_num_batched_tokens=16384`, prefix caching disabled\n\nThe server used the DeepSeek-V4 configuration with the workload changes above.\nThe relevant launch arguments were:\n\n```bash\nvllm serve /models/DeepSeek-V4-Pro \\\n --served-model-name deepseek-ai/DeepSeek-V4-Pro \\\n --trust-remote-code --tensor-parallel-size 8 \\\n --kv-cache-dtype fp8 --block-size 256 --max-model-len 1048576 \\\n --max-num-seqs 32 --max-num-batched-tokens 16384 \\\n --attention-config '{\"backend\":\"FLASHINFER_MLA_SPARSE_DSV4\",\"use_prefill_query_quantization\":true,\"use_fp4_indexer_cache\":true}' \\\n --speculative-config '{\"method\":\"mtp\",\"num_speculative_tokens\":3,\"rejection_sample_method\":\"synthetic\",\"synthetic_acceptance_length\":2.49}' \\\n --no-enable-flashinfer-autotune --no-enable-prefix-caching --enforce-eager\n```\n\nEach arm ran four unprofiled repeats of 16 requests. The first repeat used 16\nwarmup requests; the server remained warm for the other repeats. The client\ncommand was:\n\n```bash\npython utils/bench_serving/benchmark_serving.py \\\n --model deepseek-ai/DeepSeek-V4-Pro \\\n --served-model-name deepseek-ai/DeepSeek-V4-Pro \\\n --backend vllm --base-url http://127.0.0.1:8888 \\\n --dataset-name random --random-input-len 16384 --random-output-len 1 \\\n --random-range-ratio 1.0 --max-concurrency 16 --request-rate inf \\\n --num-prompts 16 --ignore-eos --seed 42 --trust-remote-code \\\n --tokenizer-mode deepseek_v4 --use-chat-template --dsv4\n```\n\nQ8 is the parent selector. Q16 is the same image and workload with only this\nquery-length guard applied and the AOT host launcher rebuilt.\n\n| Metric | Q8 (parent) | Q16 (this PR) | Change |\n|---|---:|---:|---:|\n| Four throughput repeats (tok/s) | 25,292.38; 25,286.59; 25,308.48; 25,294.95 | 27,892.23; 27,939.74; 27,923.39; 27,938.74 | -- |\n| Mean total throughput | 25,295.60 tok/s | 27,923.53 tok/s | **+10.39%** |\n| Mean throughput per GPU | 3,161.95 tok/s | 3,490.44 tok/s | **+10.39%** |\n| Exact main sparse-MLA kernel | 142.38 ms/step | 75.89 ms/step | **1.88x faster; -46.70%** |\n| Overlap-accounted attention | 198.72 ms/step | 132.66 ms/step | **-33.24%** |\n| Iteration wall time | 648.73 ms/step | 589.02 ms/step | **-9.20%** |\n| Main-kernel grid | `(16384, 2, 1)` | `(16384, 1, 1)` | **2x fewer CTAs** |\n\nThe throughput coefficient of variation was 0.037% for Q8 and 0.079% for Q16.\nThe wall-time ratio implies +10.14% throughput, consistent with the independent\nunprofiled +10.39% result.\n\nA 64-step profile validated the selector on all eight ranks. Per rank, all\n`62 layers * 64 steps = 3968` main sparse-MLA calls used the Q16 kernel, with\nzero main-path Q8 calls. The two short MTP calls per step remained Q8\n(`128` calls per rank), as intended.\n\nThe Q8 and Q16 throughput arms used different B200 nodes. The image, framework,\nmodel, and workload were identical; non-attention categories agreed within\nabout 2.4%, and the exact main FMHA reduction (66.48 ms/step) accounts for the\nfull raw-attention reduction (66.10 ms/step). A same-node rerun would provide\nthe strictest hardware-controlled A/B.\n\n## 🔍 Related Issues\n\nN/A\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\nValidation performed:\n\n- `pre-commit run --all-files`: passed.\n- Canonical `benchmarks/flashinfer_benchmark.py` public-API benchmark on one\n B200: 20 warmups + 100 measured iterations for each of eight Q lengths and\n both selector variants; all sampled FP32 correctness checks passed.\n Long-prefill Q16 was 1.886x faster at `Q=16384` with cold L2.\n- 4x unprofiled B200 throughput repeats per arm: passed, 16/16 requests each.\n- 64-step, eight-rank B200 selector profile: Q16 on all 3968 main-layer calls\n per rank; short MTP remained Q8.\n\n## Reviewer Notes\n\n- This deliberately changes only the host-side tile selector. It does not\n modify numerical code or cubin artifacts.\n- The `<= 16` boundary matches the existing short-query/DSv3 min-latency\n boundary in this runner and covers decode plus the configured MTP length.\n- The benchmarked package used an AOT host launcher, so the validation rebuilt\n that launcher after editing the header. Normal source/CI builds will compile\n the updated selector into the launcher.\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n* **New Features**\n * Added benchmarking support for DeepSeek-V4 sparse MLA attention with configurable sparse-window, compressed-cache, paging, and cache-length settings.\n * Added performance metrics, support-matrix coverage, documentation, and sample configurations for supported hardware and the TensorRT-LLM generation backend.\n* **Bug Fixes**\n * Improved sparse MLA tile selection for long-query prefill workloads.\n* **Tests**\n * Added validation for availability, configuration, tensor layouts, execution behavior, and reported metrics.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": \"DeepSeek-V4\", \"shape\": \"N=16384,K=16384,num_qo_heads=16,num_kv_heads=1,head_dim=512\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 4.931104, \"optimized\": 2.614256, \"stated_speedup\": 1.886, \"speedup\": 1.8862}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": \"DeepSeek-V4\", \"shape\": \"N=4096,K=16384,num_qo_heads=16,num_kv_heads=1,head_dim=512\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.565744, \"optimized\": 0.8252, \"stated_speedup\": 1.897, \"speedup\": 1.8974}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": \"DeepSeek-V4\", \"shape\": \"N=256,K=16384,num_qo_heads=16,num_kv_heads=1,head_dim=512\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.134144, \"optimized\": 0.080736, \"stated_speedup\": 1.662, \"speedup\": 1.6615}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": \"DeepSeek-V4\", \"shape\": \"N=32,K=16384,num_qo_heads=16,num_kv_heads=1,head_dim=512\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.03792, \"optimized\": 0.029696, \"stated_speedup\": 1.277, \"speedup\": 1.2769}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": \"DeepSeek-V4\", \"shape\": \"N=17,K=16384,num_qo_heads=16,num_kv_heads=1,head_dim=512\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.029696, \"optimized\": 0.025568, \"stated_speedup\": 1.162, \"speedup\": 1.1615}, {\"scope\": \"e2e\", \"hardware\": \"B200\", \"model\": \"DeepSeek-V4-Pro\", \"shape\": \"ISL=16384,OSL=1\", \"batch_size\": 16, \"metric\": \"throughput\", \"unit\": \"tok/s\", \"higher_is_better\": true, \"baseline\": 25295.6, \"optimized\": 27923.53, \"stated_speedup\": 1.1039, \"speedup\": 1.1039}, {\"scope\": \"e2e\", \"hardware\": \"B200\", \"model\": \"DeepSeek-V4-Pro\", \"shape\": \"ISL=16384,OSL=1\", \"batch_size\": 16, \"metric\": \"throughput_per_gpu\", \"unit\": \"tok/s\", \"higher_is_better\": true, \"baseline\": 3161.95, \"optimized\": 3490.44, \"stated_speedup\": 1.1039, \"speedup\": 1.1039}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": \"DeepSeek-V4-Pro\", \"shape\": \"ISL=16384,OSL=1\", \"batch_size\": null, \"metric\": \"latency\", \"unit\": \"ms/step\", \"higher_is_better\": false, \"baseline\": 142.38, \"optimized\": 75.89, \"stated_speedup\": 1.88, \"speedup\": 1.8761}, {\"scope\": \"e2e\", \"hardware\": \"B200\", \"model\": \"DeepSeek-V4-Pro\", \"shape\": \"ISL=16384,OSL=1\", \"batch_size\": null, \"metric\": \"latency\", \"unit\": \"ms/step\", \"higher_is_better\": false, \"baseline\": 198.72, \"optimized\": 132.66, \"stated_speedup\": null, \"speedup\": 1.498}, {\"scope\": \"e2e\", \"hardware\": \"B200\", \"model\": \"DeepSeek-V4-Pro\", \"shape\": \"ISL=16384,OSL=1\", \"batch_size\": null, \"metric\": \"iteration_wall_time\", \"unit\": \"ms/step\", \"higher_is_better\": false, \"baseline\": 648.73, \"optimized\": 589.02, \"stated_speedup\": null, \"speedup\": 1.1014}]"},"kernel_speedup":{"kind":"number","value":1.7688,"string":"1.7688"},"e2e_speedup":{"kind":"number","value":1.1039,"string":"1.1039"}}},{"rowIdx":1069,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"2c78870399f72bdeaf5dad4ee8939a10ff331c5b"},"date":{"kind":"string","value":"2026-08-31T23:31:41-07:00"},"pr_number":{"kind":"number","value":4773,"string":"4,773"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/4773"},"title":{"kind":"string","value":"fix: skip SM107 low-latency GEMM cubins on Blackwell (#4773) (#4848)"},"message":{"kind":"string","value":"fix: skip SM107 low-latency GEMM cubins on Blackwell (#4773) (#4848)\n\n## 📌 Description\n\nPort of #4786 (plus the #4792 `Sm100f`/sm107 allowance) onto `main`.\nAfter #4648 the trtllm-gen GEMM pack is a single multi-arch artifact, so\n`getValidTactics()` on the low-latency runner returned SM107 cubins on\nBlackwell. Autotune then handed those indices to `cuModuleLoadData`.\n\n`trtllm_low_latency_gemm_runner.cu` was the one trtllm-gen runner still\nmissing the `isArchCompatible` / `checkPassingConfigIndex` filter that\n#4280 added to `trtllm_gemm_runner.cu` and\n`trtllm_batched_gemm_runner.cu`.\n\nDo not cherry-pick #4786 verbatim: that filter treated `Sm100f` as\nsm100/sm103 only, and `select_kernel()` still names `_sm100f`\nheuristics, which #4792 showed fails every `mm_fp8` case on Rubin. This\nPR uses the combined `release-v0.6.18` rule (`Sm100f` on 100/103/107).\n\nOn B200 (SM100) unpatched `getValidTactics(4, 2560, 8192)` returned 16\nindices (`0,2,3,4,5,7,10,11` + `93,95,96,97,101,102,104,109`). Forced\ntactic `93` failed inside `gemm.run`. After the filter: 8 sm100f\ntactics; tactic `93` raises `Tactic 93 is not in this runner's\ncompatible config set`.\n\n## 🔍 Related Issues\n\n- Closes #4773\n- Cherry-pick / port of #4786 onto `main` (not a verbatim cherry-pick;\nincludes the #4792 `Sm100f` sm107 allowance)\n\n## 🚀 Pull Request Checklist\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit`.\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\nLocal B200 (SM100, CUDA 13.0, torch 2.13.0+cu130), worktree at\n`upstream/main` + this commit:\n\n- `pytest tests/gemm/test_mm_fp8.py\ntests/utils/test_logging_replay.py::test_mm_fp8_replay` → 31 passed\n- Tactic dump and forced-sm107a FFI path as above\n\nNot verified here: SM103 (B300) or SM107 (Rubin). Those were covered on\n`release-v0.6.18` by #4786 / #4792.\n\n## Reviewer Notes\n\nSibling runners on `main` still map `Sm100f` to `100 || 103` only. They\nwere left alone: they already have an arch filter, their heuristics have\ndedicated `_sm107a` names, and #4792 called that follow-up out of scope\nfor the low-latency crash.\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n\n## Summary by CodeRabbit\n\n* **Bug Fixes**\n* Improved low-latency matrix multiplication compatibility across\nsupported GPU architectures.\n* Prevented execution with unsupported kernel configurations, reducing\nthe risk of invalid tactics and runtime failures.\n\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->"},"path":{"kind":"string","value":"csrc/trtllm_low_latency_gemm_runner.cu"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <cuda.h>\n#include <tvm/ffi/container/array.h>\n#include <tvm/ffi/error.h>\n#include <tvm_ffi_utils.h>\n\n#include <vector>\n\n#include \"flashinfer/exception.h\"\n#include \"flashinfer/trtllm/common.h\"\n#include \"flashinfer/trtllm/gemm/trtllmGen_gemm_export/Enums.h\"\n#include \"flashinfer/trtllm/gemm/trtllmGen_gemm_export/GemmInterface.h\"\n#include \"flashinfer/trtllm/gemm/trtllmGen_gemm_export/trtllm/gen/DtypeDecl.h\"\n#include \"flashinfer/trtllm/gemm/trtllmGen_gemm_export/trtllm/gen/SfLayoutDecl.h\"\n\nnamespace {\nstatic thread_local gemm::gemm::GemmInterface::ModuleCache globalTrtllmLowLatencyGemmModuleCache;\n} // namespace\n\nnamespace flashinfer {\n\nusing tvm::ffi::Array;\nusing tvm::ffi::Optional;\n\nstruct TrtllmLowLatencyGemmRunnerOptions {\n gemm::trtllm::gen::Dtype eltType;\n gemm::trtllm::gen::Dtype outputType;\n};\n\ngemm::gemm::GemmData createGemmData(int64_t m, int64_t n, int64_t k) {\n gemm::gemm::GemmData gemmData{};\n\n // Dims\n gemmData.mProblemDimensions.mM = n;\n gemmData.mProblemDimensions.mN = m;\n gemmData.mProblemDimensions.mK = k;\n gemmData.mProblemDimensions.mValidM = gemmData.mProblemDimensions.mM;\n gemmData.mProblemDimensions.mValidN = gemmData.mProblemDimensions.mN;\n gemmData.mProblemDimensions.mValidK = gemmData.mProblemDimensions.mK;\n gemmData.mProblemDimensions.mRank = 0;\n gemmData.mProblemDimensions.mWorldSize = 1;\n\n return gemmData;\n}\n\n/**\n * Very rough heuristic for selecting a kernel. Prefer using auto-tuning.\n */\nint64_t select_kernel(int32_t m, int32_t n, int32_t k, const gemm::gemm::GemmInterface& interface) {\n static constexpr const char* KERNEL_MMAN_8_TILEK_128 =\n \"gemm_Bfloat16_E4m3E4m3_Fp32_t128x8x128_s7_et128x8_m128x8x32_c1x1x1_rM_BN_\"\n \"transOut_schedS_sm100f\";\n static constexpr const char* KERNEL_MMAN_8_TILEK_256 =\n \"gemm_Bfloat16_E4m3E4m3_Fp32_t128x8x256_s4_et128x8_m128x8x32_c1x1x1_rM_BN_\"\n \"transOut_schedS_sm100f\";\n static constexpr const char* KERNEL_MMAN_16_TILEK_128 =\n \"gemm_Bfloat16_E4m3E4m3_Fp32_t128x64x128_s7_et128x32_m128x64x32_c1x1x1_rM_BN_\"\n \"transOut_schedS_sm100f\";\n static constexpr const char* KERNEL_MMAN_16_TILEK_256 =\n \"gemm_Bfloat16_E4m3E4m3_Fp32_t128x64x256_s3_et128x32_m128x64x32_c1x1x1_rM_BN_\"\n \"transOut_schedS_sm100f\";\n static constexpr const char* KERNEL_MMAN_32_TILEK_128 =\n \"gemm_Bfloat16_E4m3E4m3_Fp32_t128x32x128_s9_et128x32_m128x32x32_c1x1x1_rM_BN_\"\n \"transOut_schedS_sm100f\";\n static constexpr const char* KERNEL_MMAN_32_TILEK_256 =\n \"gemm_Bfloat16_E4m3E4m3_Fp32_t128x32x256_s5_et128x32_m128x32x32_c1x1x1_rM_BN_\"\n \"transOut_schedS_sm100f\";\n static constexpr const char* KERNEL_MMAN_64_TILEK_128 =\n \"gemm_Bfloat16_E4m3E4m3_Fp32_t128x16x128_s7_et128x16_m128x16x32_c1x1x1_rM_BN_\"\n \"transOut_schedS_sm100f\";\n static constexpr const char* KERNEL_MMAN_64_TILEK_256 =\n \"gemm_Bfloat16_E4m3E4m3_Fp32_t128x16x256_s5_et128x16_m128x16x32_c1x1x1_rM_BN_\"\n \"transOut_schedS_sm100f\";\n\n std::string kernel_name;\n if (m <= 8) {\n kernel_name = KERNEL_MMAN_8_TILEK_128;\n } else if (m <= 16) {\n kernel_name = KERNEL_MMAN_16_TILEK_128;\n } else if (m <= 32) {\n kernel_name = KERNEL_MMAN_32_TILEK_128;\n } else {\n kernel_name = KERNEL_MMAN_64_TILEK_128;\n }\n\n auto const& configs = interface.getGemmConfigs();\n size_t const num_configs = interface.getNumGemmConfigs();\n\n for (size_t i = 0; i < num_configs; ++i) {\n if (std::string(configs[i].mFunctionName) == kernel_name) {\n return static_cast<int64_t>(i);\n }\n }\n\n TVM_FFI_LOG_AND_THROW(RuntimeError)\n << \"No kernel was found heuristically for the given problem size\";\n}\n\nint64_t getWorkspaceSizeInBytes(int64_t m, int64_t n, int64_t k, int64_t tactic) {\n auto gemm = gemm::gemm::GemmInterface();\n\n if (tactic == -1) {\n tactic = select_kernel(m, n, k, gemm);\n }\n\n auto const configs = gemm.getGemmConfigs();\n FLASHINFER_CHECK(tactic >= 0 && tactic < gemm.getNumGemmConfigs(),\n \"Invalid tactic in getWorkspaceSizeInBytes\");\n auto const config = configs[tactic];\n\n auto const gemmData = createGemmData(m, n, k);\n\n return gemm.getWorkspaceSizeInBytes(config, gemmData);\n}\n\nclass TrtllmLowLatencyGemmRunner {\n public:\n explicit TrtllmLowLatencyGemmRunner(TrtllmLowLatencyGemmRunnerOptions const& options)\n : mOptions(options) {\n // Select a GEMM kernel config to use\n auto const gemm = gemm::gemm::GemmInterface();\n auto const configs = gemm.getGemmConfigs();\n\n mPassingConfigIndices.clear();\n\n for (size_t i = 0; i < gemm.getNumGemmConfigs(); ++i) {\n auto const configOptions = configs[i].mOptions;\n\n if (configOptions.mDtypeA == mOptions.eltType &&\n configOptions.mDtypeC == mOptions.outputType &&\n configOptions.mTransposeMmaOutput == true &&\n configOptions.mLayoutA == gemm::gemm::MatrixLayout::BlockMajorK &&\n configOptions.mUseShuffledMatrix) {\n mPassingConfigIndices.push_back(i);\n }\n }\n\n FLASHINFER_CHECK(\n mPassingConfigIndices.size() > 0,\n \"No valid low latency TRTLLM-GEN GEMM kernel was found for the given data types.\");\n }\n\n void run(int64_t m, int64_t n, int64_t k, void const* a, void const* b, void* c, void* cScale,\n void* workspace, CUstream stream, int32_t device_index, int64_t tactic) {\n auto gemm = gemm::gemm::GemmInterface();\n auto const configs = gemm.getGemmConfigs();\n TVM_FFI_ICHECK(tactic >= 0 && tactic < gemm.getNumGemmConfigs()) << \"Invalid tactic id in run\";\n auto const& config = configs[tactic];\n\n gemm::gemm::GemmData gemmData = createGemmData(m, n, k);\n\n // Inputs\n gemmData.mInputBuffers.mPtrA = b;\n gemmData.mInputBuffers.mPtrB = a;\n gemmData.mInputBuffers.mPtrScaleC = cScale;\n\n // Outputs\n gemmData.mOutputBuffers.mPtrC = c;\n\n TVM_FFI_ICHECK(gemm.isValidConfig(config, gemmData))\n << \"The selected tactic points to a TRTLLM-GEN low latency GEMM kernel that is not valid \"\n \"for \"\n \"the given problem size.\";\n\n int32_t const multiProcessorCount = [device_index]() {\n static thread_local int32_t cached_multi_processor_count = -1;\n static thread_local int cached_device_index = -1;\n\n if (device_index == cached_device_index && cached_multi_processor_count != -1) {\n return cached_multi_processor_count;\n } else {\n int32_t count;\n cudaError_t cudaStatus =\n cudaDeviceGetAttribute(&count, cudaDevAttrMultiProcessorCount, device_index);\n TVM_FFI_ICHECK(cudaStatus == cudaSuccess)\n << \"Failed to get device attribute: \" << cudaGetErrorString(cudaStatus);\n cached_multi_processor_count = count;\n cached_device_index = device_index;\n return count;\n }\n }();\n\n TVM_FFI_ICHECK(gemm.run(config, workspace, gemmData, static_cast<void*>(stream),\n multiProcessorCount, true, globalTrtllmLowLatencyGemmModuleCache) == 0)\n << \"Error occurred when running low latency TRTLLM-GEN GEMM!\";\n }\n\n std::vector<int64_t> getValidTactics(int64_t m, int64_t n, int64_t k) const {\n auto const gemm = gemm::gemm::GemmInterface();\n auto const configs = gemm.getGemmConfigs();\n\n auto const gemmData = createGemmData(m, n, k);\n\n std::vector<int64_t> validTactics{};\n for (auto const& configIndex : mPassingConfigIndices) {\n auto const& config = configs[configIndex];\n if (gemm.isValidConfig(config, gemmData)) {\n validTactics.push_back(configIndex);\n }\n }\n return validTactics;\n }\n\n private:\n TrtllmLowLatencyGemmRunnerOptions mOptions;\n std::vector<int64_t> mPassingConfigIndices;\n};\n\nvoid trtllm_low_latency_gemm(TensorView workspace_buffer, TensorView a, TensorView b,\n TensorView globalScale, TensorView out, int64_t tactic) {\n CHECK_DEVICE(a, b);\n CHECK_DEVICE(a, out);\n CHECK_INPUT(a);\n CHECK_INPUT(b);\n CHECK_INPUT(out);\n CHECK_INPUT(workspace_buffer);\n CHECK_DIM(2, a);\n TVM_FFI_ICHECK(b.ndim() == 3) << \"b must be a block layout matrix (3D tensor with \"\n \"dims [N/BLOCK_SIZE, K, BLOCK_SIZE])\";\n TVM_FFI_ICHECK_EQ(a.dtype(), b.dtype());\n TVM_FFI_ICHECK(a.dtype() == dl_float8_e4m3fn) << \"a must be a Float8 tensor\";\n\n int32_t m = a.size(0);\n int32_t k = a.size(1);\n int32_t n = b.size(1);\n auto const blockSize = b.size(2);\n auto const kFromB = b.size(0) * blockSize;\n TVM_FFI_ICHECK(kFromB == a.size(1)) << \"Matrix dimensions don't match for multiplication\";\n TVM_FFI_ICHECK(out.size(0) == m && out.size(1) == n) << \"Output tensor has wrong dimensions\";\n\n if (tactic == -1) {\n tactic = select_kernel(m, n, k, gemm::gemm::GemmInterface());\n }\n\n auto runner =\n flashinfer::TrtllmLowLatencyGemmRunner(flashinfer::TrtllmLowLatencyGemmRunnerOptions{\n .eltType = gemm::trtllm::gen::Dtype::E4m3,\n .outputType = gemm::trtllm::gen::Dtype::Bfloat16,\n });\n\n auto stream = get_stream(a.device());\n\n int64_t const required_workspace_size = getWorkspaceSizeInBytes(m, n, k, tactic);\n int64_t const provided_workspace_size =\n workspace_buffer.numel() * get_element_size(workspace_buffer);\n if (provided_workspace_size < required_workspace_size) {\n TVM_FFI_LOG_AND_THROW(RuntimeError)\n << \"The size of the provided workspace to the TRTLLM-GEN low latency GEMM is too small. \"\n \"Please use the provided workspace sizing function to pre-allocate an adequate \"\n \"workspace.\";\n }\n\n runner.run(m, n, k, a.data_ptr(), b.data_ptr(), out.data_ptr(), globalScale.data_ptr(),\n workspace_buffer.data_ptr(), stream, a.device().device_id, tactic);\n}\n\nenum class Dtype : int64_t {\n E2m1 = 0,\n E4m3 = 1,\n Bfloat16 = 2,\n};\n\nArray<int64_t> trtllm_low_latency_gemm_tactics(int64_t m, int64_t n, int64_t k, int64_t input_dtype,\n int64_t output_dtype) {\n TVM_FFI_ICHECK(input_dtype == static_cast<int64_t>(Dtype::E4m3)) << \"Unsupported input dtype\";\n TVM_FFI_ICHECK_EQ(output_dtype, static_cast<int64_t>(Dtype::Bfloat16))\n << \"Unsupported output dtype\";\n\n auto runner =\n flashinfer::TrtllmLowLatencyGemmRunner(flashinfer::TrtllmLowLatencyGemmRunnerOptions{\n .eltType = gemm::trtllm::gen::Dtype::E4m3,\n .outputType = gemm::trtllm::gen::Dtype::Bfloat16,\n });\n\n return runner.getValidTactics(m, n, k);\n}\n\nnamespace trtllm_cubin_loader {\n#include <flashinfer/cubin_loader.h>\n}\n\n} // namespace flashinfer\n\n// Exposes low latency optimized GEMMs that require some pre-processing of the inputs.\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(trtllm_low_latency_gemm, flashinfer::trtllm_low_latency_gemm);\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(trtllm_low_latency_gemm_tactics,\n flashinfer::trtllm_low_latency_gemm_tactics);\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(get_workspace_size_in_bytes, flashinfer::getWorkspaceSizeInBytes);\n"},"after_code":{"kind":"string","value":"/*\n * Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <cuda.h>\n#include <tvm/ffi/container/array.h>\n#include <tvm/ffi/error.h>\n#include <tvm_ffi_utils.h>\n\n#include <algorithm>\n#include <vector>\n\n#include \"flashinfer/exception.h\"\n#include \"flashinfer/trtllm/common.h\"\n#include \"flashinfer/trtllm/gemm/trtllmGen_gemm_export/Enums.h\"\n#include \"flashinfer/trtllm/gemm/trtllmGen_gemm_export/GemmInterface.h\"\n#include \"flashinfer/trtllm/gemm/trtllmGen_gemm_export/trtllm/gen/DtypeDecl.h\"\n#include \"flashinfer/trtllm/gemm/trtllmGen_gemm_export/trtllm/gen/SfLayoutDecl.h\"\n\nnamespace {\nstatic thread_local gemm::gemm::GemmInterface::ModuleCache globalTrtllmLowLatencyGemmModuleCache;\n} // namespace\n\nnamespace flashinfer {\n\nusing tvm::ffi::Array;\nusing tvm::ffi::Optional;\n\nnamespace {\n\nbool isArchCompatible(int smVersion, gemm::trtllm::gen::CudaArch cubinArch) {\n using CudaArch = gemm::trtllm::gen::CudaArch;\n switch (cubinArch) {\n case CudaArch::Sm100a:\n return smVersion == 100;\n case CudaArch::Sm100f:\n // Low-latency heuristic kernels are named `_sm100f` and also run on sm107.\n return smVersion == 100 || smVersion == 103 || smVersion == 107;\n case CudaArch::Sm103a:\n return smVersion == 103;\n#ifdef TLLM_RUBIN_FEATURES\n case CudaArch::Sm107a:\n return smVersion == 107;\n#endif\n default:\n return false;\n }\n}\n\n} // namespace\n\nstruct TrtllmLowLatencyGemmRunnerOptions {\n gemm::trtllm::gen::Dtype eltType;\n gemm::trtllm::gen::Dtype outputType;\n};\n\ngemm::gemm::GemmData createGemmData(int64_t m, int64_t n, int64_t k) {\n gemm::gemm::GemmData gemmData{};\n\n // Dims\n gemmData.mProblemDimensions.mM = n;\n gemmData.mProblemDimensions.mN = m;\n gemmData.mProblemDimensions.mK = k;\n gemmData.mProblemDimensions.mValidM = gemmData.mProblemDimensions.mM;\n gemmData.mProblemDimensions.mValidN = gemmData.mProblemDimensions.mN;\n gemmData.mProblemDimensions.mValidK = gemmData.mProblemDimensions.mK;\n gemmData.mProblemDimensions.mRank = 0;\n gemmData.mProblemDimensions.mWorldSize = 1;\n\n return gemmData;\n}\n\n/**\n * Very rough heuristic for selecting a kernel. Prefer using auto-tuning.\n */\nint64_t select_kernel(int32_t m, int32_t n, int32_t k, const gemm::gemm::GemmInterface& interface) {\n static constexpr const char* KERNEL_MMAN_8_TILEK_128 =\n \"gemm_Bfloat16_E4m3E4m3_Fp32_t128x8x128_s7_et128x8_m128x8x32_c1x1x1_rM_BN_\"\n \"transOut_schedS_sm100f\";\n static constexpr const char* KERNEL_MMAN_8_TILEK_256 =\n \"gemm_Bfloat16_E4m3E4m3_Fp32_t128x8x256_s4_et128x8_m128x8x32_c1x1x1_rM_BN_\"\n \"transOut_schedS_sm100f\";\n static constexpr const char* KERNEL_MMAN_16_TILEK_128 =\n \"gemm_Bfloat16_E4m3E4m3_Fp32_t128x64x128_s7_et128x32_m128x64x32_c1x1x1_rM_BN_\"\n \"transOut_schedS_sm100f\";\n static constexpr const char* KERNEL_MMAN_16_TILEK_256 =\n \"gemm_Bfloat16_E4m3E4m3_Fp32_t128x64x256_s3_et128x32_m128x64x32_c1x1x1_rM_BN_\"\n \"transOut_schedS_sm100f\";\n static constexpr const char* KERNEL_MMAN_32_TILEK_128 =\n \"gemm_Bfloat16_E4m3E4m3_Fp32_t128x32x128_s9_et128x32_m128x32x32_c1x1x1_rM_BN_\"\n \"transOut_schedS_sm100f\";\n static constexpr const char* KERNEL_MMAN_32_TILEK_256 =\n \"gemm_Bfloat16_E4m3E4m3_Fp32_t128x32x256_s5_et128x32_m128x32x32_c1x1x1_rM_BN_\"\n \"transOut_schedS_sm100f\";\n static constexpr const char* KERNEL_MMAN_64_TILEK_128 =\n \"gemm_Bfloat16_E4m3E4m3_Fp32_t128x16x128_s7_et128x16_m128x16x32_c1x1x1_rM_BN_\"\n \"transOut_schedS_sm100f\";\n static constexpr const char* KERNEL_MMAN_64_TILEK_256 =\n \"gemm_Bfloat16_E4m3E4m3_Fp32_t128x16x256_s5_et128x16_m128x16x32_c1x1x1_rM_BN_\"\n \"transOut_schedS_sm100f\";\n\n std::string kernel_name;\n if (m <= 8) {\n kernel_name = KERNEL_MMAN_8_TILEK_128;\n } else if (m <= 16) {\n kernel_name = KERNEL_MMAN_16_TILEK_128;\n } else if (m <= 32) {\n kernel_name = KERNEL_MMAN_32_TILEK_128;\n } else {\n kernel_name = KERNEL_MMAN_64_TILEK_128;\n }\n\n auto const& configs = interface.getGemmConfigs();\n size_t const num_configs = interface.getNumGemmConfigs();\n\n for (size_t i = 0; i < num_configs; ++i) {\n if (std::string(configs[i].mFunctionName) == kernel_name) {\n return static_cast<int64_t>(i);\n }\n }\n\n TVM_FFI_LOG_AND_THROW(RuntimeError)\n << \"No kernel was found heuristically for the given problem size\";\n}\n\nint64_t getWorkspaceSizeInBytes(int64_t m, int64_t n, int64_t k, int64_t tactic) {\n auto gemm = gemm::gemm::GemmInterface();\n\n if (tactic == -1) {\n tactic = select_kernel(m, n, k, gemm);\n }\n\n auto const configs = gemm.getGemmConfigs();\n FLASHINFER_CHECK(tactic >= 0 && tactic < gemm.getNumGemmConfigs(),\n \"Invalid tactic in getWorkspaceSizeInBytes\");\n auto const config = configs[tactic];\n\n auto const gemmData = createGemmData(m, n, k);\n\n return gemm.getWorkspaceSizeInBytes(config, gemmData);\n}\n\nclass TrtllmLowLatencyGemmRunner {\n public:\n explicit TrtllmLowLatencyGemmRunner(TrtllmLowLatencyGemmRunnerOptions const& options)\n : mOptions(options) {\n // Select a GEMM kernel config to use\n auto const gemm = gemm::gemm::GemmInterface();\n auto const configs = gemm.getGemmConfigs();\n\n mPassingConfigIndices.clear();\n int const sv = getSMVersion();\n\n for (size_t i = 0; i < gemm.getNumGemmConfigs(); ++i) {\n auto const configOptions = configs[i].mOptions;\n\n if (configOptions.mDtypeA == mOptions.eltType &&\n configOptions.mDtypeC == mOptions.outputType &&\n configOptions.mTransposeMmaOutput == true &&\n configOptions.mLayoutA == gemm::gemm::MatrixLayout::BlockMajorK &&\n configOptions.mUseShuffledMatrix) {\n if (!isArchCompatible(sv, configs[i].mSm)) continue;\n mPassingConfigIndices.push_back(i);\n }\n }\n\n FLASHINFER_CHECK(\n mPassingConfigIndices.size() > 0,\n \"No valid low latency TRTLLM-GEN GEMM kernel was found for the given data types.\");\n }\n\n void checkPassingConfigIndex(int64_t tactic) const {\n auto it = std::find(mPassingConfigIndices.begin(), mPassingConfigIndices.end(), tactic);\n TVM_FFI_ICHECK(it != mPassingConfigIndices.end())\n << \"Tactic \" << tactic\n << \" is not in this runner's compatible config set (device architecture or GEMM options \"\n \"mismatch)\";\n }\n\n void run(int64_t m, int64_t n, int64_t k, void const* a, void const* b, void* c, void* cScale,\n void* workspace, CUstream stream, int32_t device_index, int64_t tactic) {\n auto gemm = gemm::gemm::GemmInterface();\n auto const configs = gemm.getGemmConfigs();\n TVM_FFI_ICHECK(tactic >= 0 && tactic < gemm.getNumGemmConfigs()) << \"Invalid tactic id in run\";\n checkPassingConfigIndex(tactic);\n auto const& config = configs[tactic];\n\n gemm::gemm::GemmData gemmData = createGemmData(m, n, k);\n\n // Inputs\n gemmData.mInputBuffers.mPtrA = b;\n gemmData.mInputBuffers.mPtrB = a;\n gemmData.mInputBuffers.mPtrScaleC = cScale;\n\n // Outputs\n gemmData.mOutputBuffers.mPtrC = c;\n\n TVM_FFI_ICHECK(gemm.isValidConfig(config, gemmData))\n << \"The selected tactic points to a TRTLLM-GEN low latency GEMM kernel that is not valid \"\n \"for \"\n \"the given problem size.\";\n\n int32_t const multiProcessorCount = [device_index]() {\n static thread_local int32_t cached_multi_processor_count = -1;\n static thread_local int cached_device_index = -1;\n\n if (device_index == cached_device_index && cached_multi_processor_count != -1) {\n return cached_multi_processor_count;\n } else {\n int32_t count;\n cudaError_t cudaStatus =\n cudaDeviceGetAttribute(&count, cudaDevAttrMultiProcessorCount, device_index);\n TVM_FFI_ICHECK(cudaStatus == cudaSuccess)\n << \"Failed to get device attribute: \" << cudaGetErrorString(cudaStatus);\n cached_multi_processor_count = count;\n cached_device_index = device_index;\n return count;\n }\n }();\n\n TVM_FFI_ICHECK(gemm.run(config, workspace, gemmData, static_cast<void*>(stream),\n multiProcessorCount, true, globalTrtllmLowLatencyGemmModuleCache) == 0)\n << \"Error occurred when running low latency TRTLLM-GEN GEMM!\";\n }\n\n std::vector<int64_t> getValidTactics(int64_t m, int64_t n, int64_t k) const {\n auto const gemm = gemm::gemm::GemmInterface();\n auto const configs = gemm.getGemmConfigs();\n\n auto const gemmData = createGemmData(m, n, k);\n\n std::vector<int64_t> validTactics{};\n for (auto const& configIndex : mPassingConfigIndices) {\n auto const& config = configs[configIndex];\n if (gemm.isValidConfig(config, gemmData)) {\n validTactics.push_back(configIndex);\n }\n }\n return validTactics;\n }\n\n private:\n TrtllmLowLatencyGemmRunnerOptions mOptions;\n std::vector<int64_t> mPassingConfigIndices;\n};\n\nvoid trtllm_low_latency_gemm(TensorView workspace_buffer, TensorView a, TensorView b,\n TensorView globalScale, TensorView out, int64_t tactic) {\n CHECK_DEVICE(a, b);\n CHECK_DEVICE(a, out);\n CHECK_INPUT(a);\n CHECK_INPUT(b);\n CHECK_INPUT(out);\n CHECK_INPUT(workspace_buffer);\n CHECK_DIM(2, a);\n TVM_FFI_ICHECK(b.ndim() == 3) << \"b must be a block layout matrix (3D tensor with \"\n \"dims [N/BLOCK_SIZE, K, BLOCK_SIZE])\";\n TVM_FFI_ICHECK_EQ(a.dtype(), b.dtype());\n TVM_FFI_ICHECK(a.dtype() == dl_float8_e4m3fn) << \"a must be a Float8 tensor\";\n\n int32_t m = a.size(0);\n int32_t k = a.size(1);\n int32_t n = b.size(1);\n auto const blockSize = b.size(2);\n auto const kFromB = b.size(0) * blockSize;\n TVM_FFI_ICHECK(kFromB == a.size(1)) << \"Matrix dimensions don't match for multiplication\";\n TVM_FFI_ICHECK(out.size(0) == m && out.size(1) == n) << \"Output tensor has wrong dimensions\";\n\n if (tactic == -1) {\n tactic = select_kernel(m, n, k, gemm::gemm::GemmInterface());\n }\n\n auto runner =\n flashinfer::TrtllmLowLatencyGemmRunner(flashinfer::TrtllmLowLatencyGemmRunnerOptions{\n .eltType = gemm::trtllm::gen::Dtype::E4m3,\n .outputType = gemm::trtllm::gen::Dtype::Bfloat16,\n });\n\n auto stream = get_stream(a.device());\n\n int64_t const required_workspace_size = getWorkspaceSizeInBytes(m, n, k, tactic);\n int64_t const provided_workspace_size =\n workspace_buffer.numel() * get_element_size(workspace_buffer);\n if (provided_workspace_size < required_workspace_size) {\n TVM_FFI_LOG_AND_THROW(RuntimeError)\n << \"The size of the provided workspace to the TRTLLM-GEN low latency GEMM is too small. \"\n \"Please use the provided workspace sizing function to pre-allocate an adequate \"\n \"workspace.\";\n }\n\n runner.run(m, n, k, a.data_ptr(), b.data_ptr(), out.data_ptr(), globalScale.data_ptr(),\n workspace_buffer.data_ptr(), stream, a.device().device_id, tactic);\n}\n\nenum class Dtype : int64_t {\n E2m1 = 0,\n E4m3 = 1,\n Bfloat16 = 2,\n};\n\nArray<int64_t> trtllm_low_latency_gemm_tactics(int64_t m, int64_t n, int64_t k, int64_t input_dtype,\n int64_t output_dtype) {\n TVM_FFI_ICHECK(input_dtype == static_cast<int64_t>(Dtype::E4m3)) << \"Unsupported input dtype\";\n TVM_FFI_ICHECK_EQ(output_dtype, static_cast<int64_t>(Dtype::Bfloat16))\n << \"Unsupported output dtype\";\n\n auto runner =\n flashinfer::TrtllmLowLatencyGemmRunner(flashinfer::TrtllmLowLatencyGemmRunnerOptions{\n .eltType = gemm::trtllm::gen::Dtype::E4m3,\n .outputType = gemm::trtllm::gen::Dtype::Bfloat16,\n });\n\n return runner.getValidTactics(m, n, k);\n}\n\nnamespace trtllm_cubin_loader {\n#include <flashinfer/cubin_loader.h>\n}\n\n} // namespace flashinfer\n\n// Exposes low latency optimized GEMMs that require some pre-processing of the inputs.\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(trtllm_low_latency_gemm, flashinfer::trtllm_low_latency_gemm);\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(trtllm_low_latency_gemm_tactics,\n flashinfer::trtllm_low_latency_gemm_tactics);\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(get_workspace_size_in_bytes, flashinfer::getWorkspaceSizeInBytes);\n"},"diff":{"kind":"string","value":"--- csrc/trtllm_low_latency_gemm_runner.cu\n+++ csrc/trtllm_low_latency_gemm_runner.cu\n@@ -19,6 +19,7 @@\n #include <tvm/ffi/error.h>\n #include <tvm_ffi_utils.h>\n \n+#include <algorithm>\n #include <vector>\n \n #include \"flashinfer/exception.h\"\n@@ -36,6 +37,29 @@\n \n using tvm::ffi::Array;\n using tvm::ffi::Optional;\n+\n+namespace {\n+\n+bool isArchCompatible(int smVersion, gemm::trtllm::gen::CudaArch cubinArch) {\n+ using CudaArch = gemm::trtllm::gen::CudaArch;\n+ switch (cubinArch) {\n+ case CudaArch::Sm100a:\n+ return smVersion == 100;\n+ case CudaArch::Sm100f:\n+ // Low-latency heuristic kernels are named `_sm100f` and also run on sm107.\n+ return smVersion == 100 || smVersion == 103 || smVersion == 107;\n+ case CudaArch::Sm103a:\n+ return smVersion == 103;\n+#ifdef TLLM_RUBIN_FEATURES\n+ case CudaArch::Sm107a:\n+ return smVersion == 107;\n+#endif\n+ default:\n+ return false;\n+ }\n+}\n+\n+} // namespace\n \n struct TrtllmLowLatencyGemmRunnerOptions {\n gemm::trtllm::gen::Dtype eltType;\n@@ -137,6 +161,7 @@\n auto const configs = gemm.getGemmConfigs();\n \n mPassingConfigIndices.clear();\n+ int const sv = getSMVersion();\n \n for (size_t i = 0; i < gemm.getNumGemmConfigs(); ++i) {\n auto const configOptions = configs[i].mOptions;\n@@ -146,6 +171,7 @@\n configOptions.mTransposeMmaOutput == true &&\n configOptions.mLayoutA == gemm::gemm::MatrixLayout::BlockMajorK &&\n configOptions.mUseShuffledMatrix) {\n+ if (!isArchCompatible(sv, configs[i].mSm)) continue;\n mPassingConfigIndices.push_back(i);\n }\n }\n@@ -153,6 +179,14 @@\n FLASHINFER_CHECK(\n mPassingConfigIndices.size() > 0,\n \"No valid low latency TRTLLM-GEN GEMM kernel was found for the given data types.\");\n+ }\n+\n+ void checkPassingConfigIndex(int64_t tactic) const {\n+ auto it = std::find(mPassingConfigIndices.begin(), mPassingConfigIndices.end(), tactic);\n+ TVM_FFI_ICHECK(it != mPassingConfigIndices.end())\n+ << \"Tactic \" << tactic\n+ << \" is not in this runner's compatible config set (device architecture or GEMM options \"\n+ \"mismatch)\";\n }\n \n void run(int64_t m, int64_t n, int64_t k, void const* a, void const* b, void* c, void* cScale,\n@@ -160,6 +194,7 @@\n auto gemm = gemm::gemm::GemmInterface();\n auto const configs = gemm.getGemmConfigs();\n TVM_FFI_ICHECK(tactic >= 0 && tactic < gemm.getNumGemmConfigs()) << \"Invalid tactic id in run\";\n+ checkPassingConfigIndex(tactic);\n auto const& config = configs[tactic];\n \n gemm::gemm::GemmData gemmData = createGemmData(m, n, k);"},"lines_added":{"kind":"number","value":35,"string":"35"},"lines_removed":{"kind":"number","value":0,"string":"0"},"files_in_commit":{"kind":"number","value":1,"string":"1"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["B200","B300","BLACKWELL","SM100","SM103","SM107"],"string":"[\n \"B200\",\n \"B300\",\n \"BLACKWELL\",\n \"SM100\",\n \"SM103\",\n \"SM107\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (csrc/trtllm_low_latency_gemm_runner.cu).\n\nGoal: fix: skip SM107 low-latency GEMM cubins on Blackwell (#4773)\nTarget hardware: B200, B300, BLACKWELL, SM100, SM103, SM107\nTarget models: unspecified\n\nCurrent file:\n```cuda\n/*\n * Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <cuda.h>\n#include <tvm/ffi/container/array.h>\n#include <tvm/ffi/error.h>\n#include <tvm_ffi_utils.h>\n\n#include <vector>\n\n#include \"flashinfer/exception.h\"\n#include \"flashinfer/trtllm/common.h\"\n#include \"flashinfer/trtllm/gemm/trtllmGen_gemm_export/Enums.h\"\n#include \"flashinfer/trtllm/gemm/trtllmGen_gemm_export/GemmInterface.h\"\n#include \"flashinfer/trtllm/gemm/trtllmGen_gemm_export/trtllm/gen/DtypeDecl.h\"\n#include \"flashinfer/trtllm/gemm/trtllmGen_gemm_export/trtllm/gen/SfLayoutDecl.h\"\n\nnamespace {\nstatic thread_local gemm::gemm::GemmInterface::ModuleCache globalTrtllmLowLatencyGemmModuleCache;\n} // namespace\n\nnamespace flashinfer {\n\nusing tvm::ffi::Array;\nusing tvm::ffi::Optional;\n\nstruct TrtllmLowLatencyGemmRunnerOptions {\n gemm::trtllm::gen::Dtype eltType;\n gemm::trtllm::gen::Dtype outputType;\n};\n\ngemm::gemm::GemmData createGemmData(int64_t m, int64_t n, int64_t k) {\n gemm::gemm::GemmData gemmData{};\n\n // Dims\n gemmData.mProblemDimensions.mM = n;\n gemmData.mProblemDimensions.mN = m;\n gemmData.mProblemDimensions.mK = k;\n gemmData.mProblemDimensions.mValidM = gemmData.mProblemDimensions.mM;\n gemmData.mProblemDimensions.mValidN = gemmData.mProblemDimensions.mN;\n gemmData.mProblemDimensions.mValidK = gemmData.mProblemDimensions.mK;\n gemmData.mProblemDimensions.mRank = 0;\n gemmData.mProblemDimensions.mWorldSize = 1;\n\n return gemmData;\n}\n\n/**\n * Very rough heuristic for selecting a kernel. Prefer using auto-tuning.\n */\nint64_t select_kernel(int32_t m, int32_t n, int32_t k, const gemm::gemm::GemmInterface& interface) {\n static constexpr const char* KERNEL_MMAN_8_TILEK_128 =\n \"gemm_Bfloat16_E4m3E4m3_Fp32_t128x8x128_s7_et128x8_m128x8x32_c1x1x1_rM_BN_\"\n \"transOut_schedS_sm100f\";\n static constexpr const char* KERNEL_MMAN_8_TILEK_256 =\n \"gemm_Bfloat16_E4m3E4m3_Fp32_t128x8x256_s4_et128x8_m128x8x32_c1x1x1_rM_BN_\"\n \"transOut_schedS_sm100f\";\n static constexpr const char* KERNEL_MMAN_16_TILEK_128 =\n \"gemm_Bfloat16_E4m3E4m3_Fp32_t128x64x128_s7_et128x32_m128x64x32_c1x1x1_rM_BN_\"\n \"transOut_schedS_sm100f\";\n static constexpr const char* KERNEL_MMAN_16_TILEK_256 =\n \"gemm_Bfloat16_E4m3E4m3_Fp32_t128x64x256_s3_et128x32_m128x64x32_c1x1x1_rM_BN_\"\n \"transOut_schedS_sm100f\";\n static constexpr const char* KERNEL_MMAN_32_TILEK_128 =\n \"gemm_Bfloat16_E4m3E4m3_Fp32_t128x32x128_s9_et128x32_m128x32x32_c1x1x1_rM_BN_\"\n \"transOut_schedS_sm100f\";\n static constexpr const char* KERNEL_MMAN_32_TILEK_256 =\n \"gemm_Bfloat16_E4m3E4m3_Fp32_t128x32x256_s5_et128x32_m128x32x32_c1x1x1_rM_BN_\"\n \"transOut_schedS_sm100f\";\n static constexpr const char* KERNEL_MMAN_64_TILEK_128 =\n \"gemm_Bfloat16_E4m3E4m3_Fp32_t128x16x128_s7_et128x16_m128x16x32_c1x1x1_rM_BN_\"\n \"transOut_schedS_sm100f\";\n static constexpr const char* KERNEL_MMAN_64_TILEK_256 =\n \"gemm_Bfloat16_E4m3E4m3_Fp32_t128x16x256_s5_et128x16_m128x16x32_c1x1x1_rM_BN_\"\n \"transOut_schedS_sm100f\";\n\n std::string kernel_name;\n if (m <= 8) {\n kernel_name = KERNEL_MMAN_8_TILEK_128;\n } else if (m <= 16) {\n kernel_name = KERNEL_MMAN_16_TILEK_128;\n } else if (m <= 32) {\n kernel_name = KERNEL_MMAN_32_TILEK_128;\n } else {\n kernel_name = KERNEL_MMAN_64_TILEK_128;\n }\n\n auto const& configs = interface.getGemmConfigs();\n size_t const num_configs = interface.getNumGemmConfigs();\n\n for (size_t i = 0; i < num_configs; ++i) {\n if (std::string(configs[i].mFunctionName) == kernel_name) {\n return static_cast<int64_t>(i);\n }\n }\n\n TVM_FFI_LOG_AND_THROW(RuntimeError)\n << \"No kernel was found heuristically for the given problem size\";\n}\n\nint64_t getWorkspaceSizeInBytes(int64_t m, int64_t n, int64_t k, int64_t tactic) {\n auto gemm = gemm::gemm::GemmInterface();\n\n if (tactic == -1) {\n tactic = select_kernel(m, n, k, gemm);\n }\n\n auto const configs = gemm.getGemmConfigs();\n FLASHINFER_CHECK(tactic >= 0 && tactic < gemm.getNumGemmConfigs(),\n \"Invalid tactic in getWorkspaceSizeInBytes\");\n auto const config = configs[tactic];\n\n auto const gemmData = createGemmData(m, n, k);\n\n return gemm.getWorkspaceSizeInBytes(config, gemmData);\n}\n\nclass TrtllmLowLatencyGemmRunner {\n public:\n explicit TrtllmLowLatencyGemmRunner(TrtllmLowLatencyGemmRunnerOptions const& options)\n : mOptions(options) {\n // Select a GEMM kernel config to use\n auto const gemm = gemm::gemm::GemmInterface();\n auto const configs = gemm.getGemmConfigs();\n\n mPassingConfigIndices.clear();\n\n for (size_t i = 0; i < gemm.getNumGemmConfigs(); ++i) {\n auto const configOptions = configs[i].mOptions;\n\n if (configOptions.mDtypeA == mOptions.eltType &&\n configOptions.mDtypeC == mOptions.outputType &&\n configOptions.mTransposeMmaOutput == true &&\n configOptions.mLayoutA == gemm::gemm::MatrixLayout::BlockMajorK &&\n configOptions.mUseShuffledMatrix) {\n mPassingConfigIndices.push_back(i);\n }\n }\n\n FLASHINFER_CHECK(\n mPassingConfigIndices.size() > 0,\n \"No valid low latency TRTLLM-GEN GEMM kernel was found for the given data types.\");\n }\n\n void run(int64_t m, int64_t n, int64_t k, void const* a, void const* b, void* c, void* cScale,\n void* workspace, CUstream stream, int32_t device_index, int64_t tactic) {\n auto gemm = gemm::gemm::GemmInterface();\n auto const configs = gemm.getGemmConfigs();\n TVM_FFI_ICHECK(tactic >= 0 && tactic < gemm.getNumGemmConfigs()) << \"Invalid tactic id in run\";\n auto const& config = configs[tactic];\n\n gemm::gemm::GemmData gemmData = createGemmData(m, n, k);\n\n // Inputs\n gemmData.mInputBuffers.mPtrA = b;\n gemmData.mInputBuffers.mPtrB = a;\n gemmData.mInputBuffers.mPtrScaleC = cScale;\n\n // Outputs\n gemmData.mOutputBuffers.mPtrC = c;\n\n TVM_FFI_ICHECK(gemm.isValidConfig(config, gemmData))\n << \"The selected tactic points to a TRTLLM-GEN low latency GEMM kernel that is not valid \"\n \"for \"\n \"the given problem size.\";\n\n int32_t const multiProcessorCount = [device_index]() {\n static thread_local int32_t cached_multi_processor_count = -1;\n static thread_local int cached_device_index = -1;\n\n if (device_index == cached_device_index && cached_multi_processor_count != -1) {\n return cached_multi_processor_count;\n } else {\n int32_t count;\n cudaError_t cudaStatus =\n cudaDeviceGetAttribute(&count, cudaDevAttrMultiProcessorCount, device_index);\n TVM_FFI_ICHECK(cudaStatus == cudaSuccess)\n << \"Failed to get device attribute: \" << cudaGetErrorString(cudaStatus);\n cached_multi_processor_count = count;\n cached_device_index = device_index;\n return count;\n }\n }();\n\n TVM_FFI_ICHECK(gemm.run(config, workspace, gemmData, static_cast<void*>(stream),\n multiProcessorCount, true, globalTrtllmLowLatencyGemmModuleCache) == 0)\n << \"Error occurred when running low latency TRTLLM-GEN GEMM!\";\n }\n\n std::vector<int64_t> getValidTactics(int64_t m, int64_t n, int64_t k) const {\n auto const gemm = gemm::gemm::GemmInterface();\n auto const configs = gemm.getGemmConfigs();\n\n auto const gemmData = createGemmData(m, n, k);\n\n std::vector<int64_t> validTactics{};\n for (auto const& configIndex : mPassingConfigIndices) {\n auto const& config = configs[configIndex];\n if (gemm.isValidConfig(config, gemmData)) {\n validTactics.push_back(configIndex);\n }\n }\n return validTactics;\n }\n\n private:\n TrtllmLowLatencyGemmRunnerOptions mOptions;\n std::vector<int64_t> mPassingConfigIndices;\n};\n\nvoid trtllm_low_latency_gemm(TensorView workspace_buffer, TensorView a, TensorView b,\n TensorView globalScale, TensorView out, int64_t tactic) {\n CHECK_DEVICE(a, b);\n CHECK_DEVICE(a, out);\n CHECK_INPUT(a);\n CHECK_INPUT(b);\n CHECK_INPUT(out);\n CHECK_INPUT(workspace_buffer);\n CHECK_DIM(2, a);\n TVM_FFI_ICHECK(b.ndim() == 3) << \"b must be a block layout matrix (3D tensor with \"\n \"dims [N/BLOCK_SIZE, K, BLOCK_SIZE])\";\n TVM_FFI_ICHECK_EQ(a.dtype(), b.dtype());\n TVM_FFI_ICHECK(a.dtype() == dl_float8_e4m3fn) << \"a must be a Float8 tensor\";\n\n int32_t m = a.size(0);\n int32_t k = a.size(1);\n int32_t n = b.size(1);\n auto const blockSize = b.size(2);\n auto const kFromB = b.size(0) * blockSize;\n TVM_FFI_ICHECK(kFromB == a.size(1)) << \"Matrix dimensions don't match for multiplication\";\n TVM_FFI_ICHECK(out.size(0) == m && out.size(1) == n) << \"Output tensor has wrong dimensions\";\n\n if (tactic == -1) {\n tactic = select_kernel(m, n, k, gemm::gemm::GemmInterface());\n }\n\n auto runner =\n flashinfer::TrtllmLowLatencyGemmRunner(flashinfer::TrtllmLowLatencyGemmRunnerOptions{\n .eltType = gemm::trtllm::gen::Dtype::E4m3,\n .outputType = gemm::trtllm::gen::Dtype::Bfloat16,\n });\n\n auto stream = get_stream(a.device());\n\n int64_t const required_workspace_size = getWorkspaceSizeInBytes(m, n, k, tactic);\n int64_t const provided_workspace_size =\n workspace_buffer.numel() * get_element_size(workspace_buffer);\n if (provided_workspace_size < required_workspace_size) {\n TVM_FFI_LOG_AND_THROW(RuntimeError)\n << \"The size of the provided workspace to the TRTLLM-GEN low latency GEMM is too small. \"\n \"Please use the provided workspace sizing function to pre-allocate an adequate \"\n \"workspace.\";\n }\n\n runner.run(m, n, k, a.data_ptr(), b.data_ptr(), out.data_ptr(), globalScale.data_ptr(),\n workspace_buffer.data_ptr(), stream, a.device().device_id, tactic);\n}\n\nenum class Dtype : int64_t {\n E2m1 = 0,\n E4m3 = 1,\n Bfloat16 = 2,\n};\n\nArray<int64_t> trtllm_low_latency_gemm_tactics(int64_t m, int64_t n, int64_t k, int64_t input_dtype,\n int64_t output_dtype) {\n TVM_FFI_ICHECK(input_dtype == static_cast<int64_t>(Dtype::E4m3)) << \"Unsupported input dtype\";\n TVM_FFI_ICHECK_EQ(output_dtype, static_cast<int64_t>(Dtype::Bfloat16))\n << \"Unsupported output dtype\";\n\n auto runner =\n flashinfer::TrtllmLowLatencyGemmRunner(flashinfer::TrtllmLowLatencyGemmRunnerOptions{\n .eltType = gemm::trtllm::gen::Dtype::E4m3,\n .outputType = gemm::trtllm::gen::Dtype::Bfloat16,\n });\n\n return runner.getValidTactics(m, n, k);\n}\n\nnamespace trtllm_cubin_loader {\n#include <flashinfer/cubin_loader.h>\n}\n\n} // namespace flashinfer\n\n// Exposes low latency optimized GEMMs that require some pre-processing of the inputs.\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(trtllm_low_latency_gemm, flashinfer::trtllm_low_latency_gemm);\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(trtllm_low_latency_gemm_tactics,\n flashinfer::trtllm_low_latency_gemm_tactics);\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(get_workspace_size_in_bytes, flashinfer::getWorkspaceSizeInBytes);\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":""},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1070,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"72e5c3ab632247eab680dd953a6debf72e141c2e"},"date":{"kind":"string","value":"2026-09-01T13:05:35+09:00"},"pr_number":{"kind":"number","value":4746,"string":"4,746"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/4746"},"title":{"kind":"string","value":"perf(attention): cut NVFP4 KV dequant instructions on targets without native FP4/FP8 conversion (#4746)"},"message":{"kind":"string","value":"perf(attention): cut NVFP4 KV dequant instructions on targets without native FP4/FP8 conversion (#4746)\n\n<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\nNVFP4 KV cache works on pre-SM100 but was never performance-tuned there.\nOn sm_80 (head_dim 128, 32/8 heads, page_size 16) NVFP4 KV costs\n**6.8–8.2x FP8 KV in prefill and 4.4–5.4x in decode**, even though it\nreads *half* the bytes FP8 does. FP8 KV — which also dequantizes — is\nessentially free on the same hardware, so the gap is not \"quantized KV\nis slow\", it is specific to the FP4 path.\n\n`ncu` says why. At identical shapes the NVFP4 and FP16 kernels have the\n**same launch config, same occupancy, same MMA instruction count, and\nthe same number of `ldmatrix`**; the only difference is that NVFP4\nexecutes **6.75x more instructions** (249.6M vs 36.97M). DRAM throughput\nis 0.36% of peak — it is not memory-bound, it is instruction-bound. The\nextra 212.7M instructions are 30% `LOP3`, 14% `PRMT`, 14% `IMAD`, 8%\n`SHF` — the bit-manipulation signature of dequantization — plus 13%\nbranch opcodes (`ISETP`/`BRA`/`BSSY`/`BSYNC`), which turned out to be\nthe most actionable part.\n\n#4769 stacks on this PR: its NVFP4 tile repack calls the\n`e2m1x8_to_f16x8` / `e2m1x8_to_bf16x8` helpers and\n`nvfp4_sf4_to_packed2x2` added here, so its diff carries these commits\nuntil this one lands.\n\nThis PR is four changes, each gated to the targets that actually lack\nthe corresponding hardware instruction. All of them produce\nbit-identical output, with one documented exception in the scale-factor\nconversion covered under \"Known behavioral difference\" below.\n\n**1. `vec_dtypes.cuh`: the arch<SM100 `vec_cast<half|nv_bfloat16,\n__nv_fp4x2_e2m1>` fallback indexed a function-local `constexpr uint16_t\nlut[16]`.** nvcc puts that array in **local memory**: SASS shows\n`STL.128` x2 re-storing the table to the thread stack on *every inlined\ncall*, one dependent `LDL.U16` per element, and a 32-byte stack frame in\nevery kernel that inlines it.\n\nReplaced with a register-only `prmt` path. The FP16 encodings of the\neight E2M1 magnitudes {0, .5, 1, 1.5, 2, 3, 4, 6} are {0x0000, 0x3800,\n0x3C00, 0x3E00, 0x4000, 0x4200, 0x4400, 0x4600} — **every low byte is\nzero**, so the whole magnitude table is eight distinct high bytes, which\nis exactly what one `prmt` indexes from its two source registers. BF16\nmagnitudes have a varying low byte, so that specialization indexes two\n8-byte tables and interleaves them. Guarded by `if constexpr (vec_size %\n8 == 0)`; every other size keeps the LUT, and SM100+ keeps\n`cvt.rn.f16x2.e2m1x2`.\n\nModule-wide on the FA2 NVFP4-KV instantiation: **`LDL` 36202 → 128,\n`STL` 9602 → 190**, kernels with a zero-byte stack frame **0/72 →\n54/72**, kernels at the 255-register ceiling **25 → 19**.\n\n**2 + 3. `prefill.cuh`: every per-fragment E4M3 scale byte was converted\nwith `static_cast<DTypeQ>(sf_fp8)`.** Where there is no hardware\ne4m3→f16 convert — below SM90 — that expands to a software conversion\nwhose denormal path is a data-dependent\n\n```\nwhile ((mantissa & 0x0400U) == 0U) { ... }\n```\n\nrenormalization loop. `ncu` source correlation put that single loop at\nthe **top of the kernel's branch profile** — a divergent branch per\nscale byte, in the innermost loop.\n\nAdded `nvfp4_sf4_to_packed2x2()`, which packs four scale bytes into one\nword and hands them to the in-tree `fast_dequant_f8f16x4` (prmt/lop3,\nbranch-free), producing exactly the two `half2`/`nv_bfloat162` operands\nthe scale multiply needs. Applied at all four sites — the K path in\n`compute_qk`, the K path in `compute_qk_fp4_rope`, and both V paths. The\nhelper is gated on `FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED` — the\nsame macro `vec_cast<*, __nv_fp8_e4m3>` already uses — rather than a\nseparate threshold, so SM90+ keeps `static_cast` and still lowers to the\nhardware instruction. Verified by SASS: sm_80 emits the `prmt` sequence,\nsm_90 emits `F2FP.F16.E4M3.UNPACK_B`.\n\nAfter all three, branch opcodes drop out of the top of the profile\nentirely and instruction count falls 249.6M → 171.1M.\n\n### 4. Spread the E2M1 signs with one `prmt` instead of a shift chain\n\nThe pre-SM100 e2m1 to 16-bit path built each value's sign by moving bit\n`4j+3` to the msb of byte `j` with four shift/mask/or chains per half of\nthe vector — eight shifts and eight `lop3` per eight values, the largest\npart of the sequence.\n\n`prmt`'s default mode replicates the sign of the selected byte across\nthe output byte when the msb of a selector nibble is set. Byte `j` of\nthe packed nibbles already carries an odd value's sign in its msb, and\n`packed << 4` puts the even value's sign in the same place, so one\nsign-replicating `prmt` gathers four signs in value order as\n`0x00`/`0xFF` bytes. Masking to `0x80` and merging folds into a single\n`lop3`. `__byte_perm()` discards the mode bit, so this reaches for the\nPTX instruction directly.\n\nPer eight values the sequence drops from 25 to 14 instructions (half;\nbf16 26 to 15). Across the NVFP4 prefill module on sm_80, `cuobjdump`\ncounts 501575 instructions before and 448209 after.\n\nThis one is exhaustively checked rather than sampled: all 2^32\nfour-payload-byte inputs against the plain-LUT reference, for both half\nand bf16, zero mismatches. The magnitude-table body is also lifted into\n`e2m1x8_to_f16x8` / `e2m1x8_to_bf16x8` so a caller holding contiguous\nnibbles can convert without the stride-2 gather `vec_cast` has to do.\n\n### Results\n\nKernel latency, sm_80, head_dim 128, 32/8 heads, page_size 16, seeded\nKV, no D2H sync in the timed loop. **FP8 KV is the meaningful\nyardstick**: it also dequantizes, its dequant is already optimized\nupstream, and NVFP4 moves half its bytes — so the fair target is <1.0x,\nnot 1.0x.\n\n| case | FP8 KV | NVFP4 before | NVFP4 after | before/FP8 |\n**after/FP8** |\n|---|---|---|---|---|---|\n| prefill b1 4096² | 1.866 ms | 12.616 | **4.531** | 6.76x | **2.43x** |\n| prefill b4 2048² | 1.489 | 12.157 | **4.427** | 8.17x | **2.97x** |\n| prefill b8 1024² | 0.937 | 6.351 | **2.399** | 6.78x | **2.56x** |\n| decode b8 kv8192 | 0.172 | 0.921 | **0.295** | 5.36x | **1.72x** |\n| decode b32 kv8192 | 0.673 | 3.298 | **1.146** | 4.90x | **1.70x** |\n| decode b64 kv8192 40h | 1.544 | 6.815 | **2.347** | 4.41x | **1.52x**\n|\n\nSpeedup over the current NVFP4 path: **prefill 2.65–2.78x, decode\n2.88–3.12x**.\n\n**Measurement caveat.** At this commit\n`_nvfp4_kv_requires_disabled_split_kv()` force-disables split-KV for\nNVFP4 KV on every architecture, while FP8 KV keeps it. The FP8 column\nabove is therefore *unfair to NVFP4* in the decode rows — NVFP4 is\nrunning without flash-decoding and FP8 is not. The before/after columns\nare unaffected, since both sides carry the same gate. #4747 narrows that\ngate to the architecture it was found on; NVFP4 decode improves further\nonce it lands.\n\nEnd-to-end serving numbers are omitted for the same reason: with the\ngate in place, NVFP4 decode at low batch is up to 3x off its own\nachievable latency, so an end-to-end table taken here would measure the\ngate rather than this change.\n\nAn isolated microbenchmark of change 1 alone gives 6.82x on the\nconversion when ALU-bound and 3.69x when streaming from HBM (322 → 1187\nGB/s) — the old path could not saturate HBM at all.\n\n## 🔍 Related Issues\n\nN/A\n\n## 🚀 Pull Request Checklist\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed. *(No new tests: every\nchange is an arithmetic-identity replacement, so the existing suite plus\na bit-identity check is the stronger assertion. See the head_dim gap\nbelow, which is why I did add coverage there manually rather than as a\ncommitted test.)*\n- [x] All tests are passing — the NVFP4/FP4 selection of the attention\nand quantization suites on SM80, not the full suite.\n\n`"},"path":{"kind":"string","value":"include/flashinfer/vec_dtypes.cuh"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * Copyright (c) 2023 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef VEC_DTYPES_CUH_\n#define VEC_DTYPES_CUH_\n\n#include <cuda.h>\n#include <cuda_bf16.h>\n#include <cuda_fp16.h>\n#include <cuda_fp8.h>\n#if CUDA_VERSION >= 12080\n#include <cuda_fp4.h>\n#endif\n#include <cuda_runtime.h>\n\n#include <type_traits>\n\nnamespace flashinfer {\n\n#if (!defined(__CUDA_ARCH__) || (__CUDA_ARCH__ >= 900))\n#define FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n#endif\n\n#define FLASHINFER_INLINE inline __attribute__((always_inline)) __device__\n\n__device__ __forceinline__ void st_global_release(int4 const& val, int4* addr) {\n asm volatile(\"st.release.global.sys.v4.b32 [%4], {%0, %1, %2, %3};\" ::\"r\"(val.x), \"r\"(val.y),\n \"r\"(val.z), \"r\"(val.w), \"l\"(addr));\n}\n\n__device__ __forceinline__ int4 ld_global_acquire(int4* addr) {\n int4 val;\n asm volatile(\"ld.acquire.global.sys.v4.b32 {%0, %1, %2, %3}, [%4];\"\n : \"=r\"(val.x), \"=r\"(val.y), \"=r\"(val.z), \"=r\"(val.w)\n : \"l\"(addr));\n return val;\n}\n\n__device__ __forceinline__ void st_global_volatile(int4 const& val, int4* addr) {\n asm volatile(\"st.volatile.global.v4.b32 [%4], {%0, %1, %2, %3};\" ::\"r\"(val.x), \"r\"(val.y),\n \"r\"(val.z), \"r\"(val.w), \"l\"(addr));\n}\n\n__device__ __forceinline__ int4 ld_global_volatile(int4* addr) {\n int4 val;\n asm volatile(\"ld.volatile.global.v4.b32 {%0, %1, %2, %3}, [%4];\"\n : \"=r\"(val.x), \"=r\"(val.y), \"=r\"(val.z), \"=r\"(val.w)\n : \"l\"(addr));\n return val;\n}\n\n#if (__CUDACC_VER_MAJOR__ * 10000 + __CUDACC_VER_MINOR__ * 100 < 120200) && \\\n (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ < 800))\n// CUDA version < 12.2 and GPU architecture < 80\nFLASHINFER_INLINE __nv_bfloat162 make_bfloat162(const __nv_bfloat16 x, const __nv_bfloat16 y) {\n __nv_bfloat162 t;\n t.x = x;\n t.y = y;\n return t;\n}\n\nFLASHINFER_INLINE __nv_bfloat16 __hmul(const __nv_bfloat16 a, const __nv_bfloat16 b) {\n __nv_bfloat16 val;\n const float fa = __bfloat162float(a);\n const float fb = __bfloat162float(b);\n // avoid ftz in device code\n val = __float2bfloat16(__fmaf_ieee_rn(fa, fb, -0.0f));\n return val;\n}\n\nFLASHINFER_INLINE __nv_bfloat162 __hmul2(const __nv_bfloat162 a, const __nv_bfloat162 b) {\n __nv_bfloat162 val;\n val.x = __hmul(a.x, b.x);\n val.y = __hmul(a.y, b.y);\n return val;\n}\n\nFLASHINFER_INLINE __nv_bfloat162 __floats2bfloat162_rn(const float a, const float b) {\n __nv_bfloat162 val;\n val = __nv_bfloat162(__float2bfloat16_rn(a), __float2bfloat16_rn(b));\n return val;\n}\n\nFLASHINFER_INLINE __nv_bfloat162 __float22bfloat162_rn(const float2 a) {\n __nv_bfloat162 val = __floats2bfloat162_rn(a.x, a.y);\n return val;\n}\nFLASHINFER_INLINE float2 __bfloat1622float2(const __nv_bfloat162 a) {\n float hi_float;\n float lo_float;\n lo_float = __internal_bfloat162float(((__nv_bfloat162_raw)a).x);\n hi_float = __internal_bfloat162float(((__nv_bfloat162_raw)a).y);\n return make_float2(lo_float, hi_float);\n}\n#endif\n\n/******************* vec_t type cast *******************/\n\ntemplate <typename dst_t, typename src_t>\nstruct vec_cast {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(dst_t* dst, const src_t* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size; ++i) {\n dst[i] = (dst_t)src[i];\n }\n }\n};\n\ntemplate <>\nstruct vec_cast<__nv_fp8_e4m3, float> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(__nv_fp8_e4m3* dst, const float* src) {\n if constexpr (vec_size == 1) {\n dst[0] = __nv_fp8_e4m3(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n ((__nv_fp8x2_storage_t*)dst)[i] =\n __nv_cvt_float2_to_fp8x2(((float2*)src)[i], __NV_SATFINITE, __NV_E4M3);\n }\n }\n }\n};\n\ntemplate <>\nstruct vec_cast<__nv_fp8_e5m2, float> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(__nv_fp8_e5m2* dst, const float* src) {\n if constexpr (vec_size == 1) {\n dst[0] = __nv_fp8_e5m2(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n ((__nv_fp8x2_storage_t*)dst)[i] =\n __nv_cvt_float2_to_fp8x2(((float2*)src)[i], __NV_SATFINITE, __NV_E5M2);\n }\n }\n }\n};\n\ntemplate <>\nstruct vec_cast<float, half> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(float* dst, const half* src) {\n if constexpr (vec_size == 1) {\n dst[0] = (float)src[0];\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n ((float2*)dst)[i] = __half22float2(((half2*)src)[i]);\n }\n }\n }\n};\n\ntemplate <>\nstruct vec_cast<half, float> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(half* dst, const float* src) {\n if constexpr (vec_size == 1) {\n dst[0] = __float2half(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n ((half2*)dst)[i] = __float22half2_rn(((float2*)src)[i]);\n }\n }\n }\n};\n\ntemplate <typename T>\nconstexpr FLASHINFER_INLINE int get_exponent_bits() {\n if constexpr (std::is_same_v<T, __nv_fp8_e4m3>) {\n return 4;\n } else if constexpr (std::is_same_v<T, __nv_fp8_e5m2>) {\n return 5;\n } else if constexpr (std::is_same_v<T, half>) {\n return 5;\n } else if constexpr (std::is_same_v<T, nv_bfloat16>) {\n return 8;\n }\n}\n\ntemplate <typename T>\nconstexpr FLASHINFER_INLINE int get_mantissa_bits() {\n if constexpr (std::is_same_v<T, __nv_fp8_e4m3>) {\n return 3;\n } else if constexpr (std::is_same_v<T, __nv_fp8_e5m2>) {\n return 2;\n } else if constexpr (std::is_same_v<T, half>) {\n return 11;\n } else if constexpr (std::is_same_v<T, nv_bfloat16>) {\n return 7;\n }\n}\n\n/*!\n * \\brief Fallback to software fast dequant implementation if hardware dequantization is not\n * available.\n * \\note Inspired by Marlin's fast dequantization, but here we don't have to permute\n * weights order.\n * \\ref\n * https://github.com/vllm-project/vllm/blob/6dffa4b0a6120159ef2fe44d695a46817aff65bc/csrc/quantization/fp8/fp8_marlin.cu#L120\n */\ntemplate <typename fp8_dtype, typename fp16_dtype>\n__device__ void fast_dequant_f8f16x4(uint32_t* input, uint2* output) {\n uint32_t q = *input;\n if constexpr (std::is_same_v<fp8_dtype, __nv_fp8_e5m2> && std::is_same_v<fp16_dtype, half>) {\n output->x = __byte_perm(0U, q, 0x5140);\n output->y = __byte_perm(0U, q, 0x7362);\n } else {\n constexpr int FP8_EXPONENT = get_exponent_bits<fp8_dtype>();\n constexpr int FP8_MANTISSA = get_mantissa_bits<fp8_dtype>();\n constexpr int FP16_EXPONENT = get_exponent_bits<fp16_dtype>();\n\n constexpr int RIGHT_SHIFT = FP16_EXPONENT - FP8_EXPONENT;\n // Calculate MASK for extracting mantissa and exponent\n constexpr int MASK1 = 0x80000000;\n constexpr int MASK2 = MASK1 >> (FP8_EXPONENT + FP8_MANTISSA);\n constexpr int MASK3 = MASK2 & 0x7fffffff;\n constexpr int MASK = MASK3 | (MASK3 >> 16);\n q = __byte_perm(q, q, 0x1302);\n\n // Extract and shift FP8 values to FP16 format\n uint32_t Out1 = (q & 0x80008000) | ((q & MASK) >> RIGHT_SHIFT);\n uint32_t Out2 = ((q << 8) & 0x80008000) | (((q << 8) & MASK) >> RIGHT_SHIFT);\n\n constexpr int BIAS_OFFSET = (1 << (FP16_EXPONENT - 1)) - (1 << (FP8_EXPONENT - 1));\n // Construct and apply exponent bias\n if constexpr (std::is_same_v<fp16_dtype, half>) {\n const half2 bias_reg = __float2half2_rn(float(1 << BIAS_OFFSET));\n\n // Convert to half2 and apply bias\n *(half2*)&(output->x) = __hmul2(*reinterpret_cast<const half2*>(&Out1), bias_reg);\n *(half2*)&(output->y) = __hmul2(*reinterpret_cast<const half2*>(&Out2), bias_reg);\n } else {\n constexpr uint32_t BIAS = (BIAS_OFFSET + 127) << 23;\n const nv_bfloat162 bias_reg = __float2bfloat162_rn(*reinterpret_cast<const float*>(&BIAS));\n // Convert to bfloat162 and apply bias\n *(nv_bfloat162*)&(output->x) =\n __hmul2(*reinterpret_cast<const nv_bfloat162*>(&Out1), bias_reg);\n *(nv_bfloat162*)&(output->y) =\n __hmul2(*reinterpret_cast<const nv_bfloat162*>(&Out2), bias_reg);\n }\n }\n}\n\ntemplate <>\nstruct vec_cast<nv_bfloat16, __nv_fp8_e4m3> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(nv_bfloat16* dst, const __nv_fp8_e4m3* src) {\n if constexpr (vec_size == 1) {\n dst[0] = nv_bfloat16(src[0]);\n } else if constexpr (vec_size == 2) {\n dst[0] = nv_bfloat16(src[0]);\n dst[1] = nv_bfloat16(src[1]);\n } else {\n static_assert(vec_size % 4 == 0, \"vec_size must be a multiple of 4\");\n#pragma unroll\n for (uint32_t i = 0; i < vec_size / 4; ++i) {\n fast_dequant_f8f16x4<__nv_fp8_e4m3, nv_bfloat16>((uint32_t*)&src[i * 4],\n (uint2*)&dst[i * 4]);\n }\n }\n }\n};\n\ntemplate <>\nstruct vec_cast<nv_bfloat16, __nv_fp8_e5m2> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(nv_bfloat16* dst, const __nv_fp8_e5m2* src) {\n if constexpr (vec_size == 1) {\n dst[0] = nv_bfloat16(src[0]);\n } else if constexpr (vec_size == 2) {\n dst[0] = nv_bfloat16(src[0]);\n dst[1] = nv_bfloat16(src[1]);\n } else {\n static_assert(vec_size % 4 == 0, \"vec_size must be a multiple of 4\");\n#pragma unroll\n for (uint32_t i = 0; i < vec_size / 4; ++i) {\n fast_dequant_f8f16x4<__nv_fp8_e5m2, nv_bfloat16>((uint32_t*)&src[i * 4],\n (uint2*)&dst[i * 4]);\n }\n }\n }\n};\n\ntemplate <>\nstruct vec_cast<__nv_fp8_e4m3, half> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(__nv_fp8_e4m3* dst, const half* src) {\n#ifdef FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n if constexpr (vec_size == 1) {\n dst[0] = __nv_fp8_e4m3(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint16_t y;\n uint32_t x = *(uint32_t*)&src[i * 2];\n asm volatile(\"cvt.rn.satfinite.e4m3x2.f16x2 %0, %1;\" : \"=h\"(y) : \"r\"(x));\n *(uint16_t*)&dst[i * 2] = y;\n }\n }\n#else\n#pragma unroll\n for (size_t i = 0; i < vec_size; ++i) {\n dst[i] = __nv_fp8_e4m3(src[i]);\n }\n#endif // FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n }\n};\n\ntemplate <>\nstruct vec_cast<__nv_fp8_e5m2, half> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(__nv_fp8_e5m2* dst, const half* src) {\n#ifdef FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n if constexpr (vec_size == 1) {\n dst[0] = __nv_fp8_e5m2(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint16_t y;\n uint32_t x = *(uint32_t*)&src[i * 2];\n asm volatile(\"cvt.rn.satfinite.e5m2x2.f16x2 %0, %1;\" : \"=h\"(y) : \"r\"(x));\n *(uint16_t*)&dst[i * 2] = y;\n }\n }\n#else\n#pragma unroll\n for (size_t i = 0; i < vec_size; ++i) {\n dst[i] = __nv_fp8_e5m2(src[i]);\n }\n#endif // FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n }\n};\n\ntemplate <>\nstruct vec_cast<half, __nv_fp8_e4m3> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(half* dst, const __nv_fp8_e4m3* src) {\n#ifdef FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n if constexpr (vec_size == 1) {\n dst[0] = half(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint32_t y;\n uint16_t x = *(uint16_t*)&src[i * 2];\n asm volatile(\"cvt.rn.f16x2.e4m3x2 %0, %1;\" : \"=r\"(y) : \"h\"(x));\n *(uint32_t*)&dst[i * 2] = y;\n }\n }\n#else\n if constexpr (vec_size == 1) {\n dst[0] = half(src[0]);\n } else if constexpr (vec_size == 2) {\n dst[0] = half(src[0]);\n dst[1] = half(src[1]);\n } else {\n static_assert(vec_size % 4 == 0, \"vec_size must be a multiple of 4\");\n#pragma unroll\n for (uint32_t i = 0; i < vec_size / 4; ++i) {\n fast_dequant_f8f16x4<__nv_fp8_e4m3, half>((uint32_t*)&src[i * 4], (uint2*)&dst[i * 4]);\n }\n }\n#endif // FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n }\n};\n\ntemplate <>\nstruct vec_cast<half, __nv_fp8_e5m2> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(half* dst, const __nv_fp8_e5m2* src) {\n#ifdef FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n if constexpr (vec_size == 1) {\n dst[0] = half(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint32_t y;\n uint16_t x = *(uint16_t*)&src[i * 2];\n asm volatile(\"cvt.rn.f16x2.e5m2x2 %0, %1;\" : \"=r\"(y) : \"h\"(x));\n *(uint32_t*)&dst[i * 2] = y;\n }\n }\n#else\n if constexpr (vec_size == 1) {\n dst[0] = half(src[0]);\n } else if constexpr (vec_size == 2) {\n dst[0] = half(src[0]);\n dst[1] = half(src[1]);\n } else {\n static_assert(vec_size % 4 == 0, \"vec_size must be a multiple of 4\");\n#pragma unroll\n for (uint32_t i = 0; i < vec_size / 4; ++i) {\n fast_dequant_f8f16x4<__nv_fp8_e5m2, half>((uint32_t*)&src[i * 4], (uint2*)&dst[i * 4]);\n }\n }\n#endif // FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n }\n};\n\n#if defined(FLASHINFER_ENABLE_FP4_E2M1) && CUDA_VERSION >= 12080\n// Convert __nv_fp4x2_e2m1 (2 fp4 values per byte) to fp16.\n// vec_size counts fp16 output elements; src has stride-2 layout:\n// src[0] holds x0,x1 src[1] is padding\n// src[2] holds x2,x3 src[3] is padding ... etc.\n// Each valid byte encodes 2 fp4 values -> 2 fp16 via cvt.rn.f16x2.e2m1x2.\ntemplate <>\nstruct vec_cast<half, __nv_fp4x2_e2m1> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(half* dst, const __nv_fp4x2_e2m1* src) {\n static_assert(vec_size % 2 == 0, \"vec_size must be even for fp4x2 dequantization\");\n#if (defined __CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint32_t y;\n // Valid fp4x2 bytes are at even positions (stride 2); odd positions are padding.\n uint32_t b = reinterpret_cast<const uint8_t*>(src)[i * 2];\n asm volatile(\n \"{\\n\"\n \".reg .b8 fp4_byte;\\n\"\n \"mov.b32 {fp4_byte, _, _, _}, %1;\\n\"\n \"cvt.rn.f16x2.e2m1x2 %0, fp4_byte;\\n\"\n \"}\"\n : \"=r\"(y)\n : \"r\"(b));\n reinterpret_cast<uint32_t*>(dst)[i] = y;\n }\n#else\n // Software LUT fallback for arch < SM100.\n // e2m1 encoding: bit[3]=sign, bit[2:0]=magnitude index in {0,0.5,1,1.5,2,3,4,6}.\n // Each packed byte holds two fp4 values: bits[3:0]=first, bits[7:4]=second.\n constexpr uint16_t lut[16] = {\n 0x0000, // +0.0\n 0x3800, // +0.5\n 0x3C00, // +1.0\n 0x3E00, // +1.5\n 0x4000, // +2.0\n 0x4200, // +3.0\n 0x4400, // +4.0\n 0x4600, // +6.0\n 0x8000, // -0.0\n 0xB800, // -0.5\n 0xBC00, // -1.0\n 0xBE00, // -1.5\n 0xC000, // -2.0\n 0xC200, // -3.0\n 0xC400, // -4.0\n 0xC600, // -6.0\n };\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint8_t b = reinterpret_cast<const uint8_t*>(src)[i * 2];\n reinterpret_cast<uint16_t*>(dst)[i * 2 + 0] = lut[b & 0x0F];\n reinterpret_cast<uint16_t*>(dst)[i * 2 + 1] = lut[(b >> 4) & 0x0F];\n }\n#endif\n }\n};\n\ntemplate <>\nstruct vec_cast<float, __nv_fp4x2_e2m1> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(float* dst, const __nv_fp4x2_e2m1* src) {\n static_assert(vec_size % 2 == 0, \"vec_size must be even for fp4x2 dequantization\");\n#if (defined __CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint32_t fp16x2;\n // Valid fp4x2 bytes are at even positions (stride 2); odd positions are padding.\n uint32_t b = reinterpret_cast<const uint8_t*>(src)[i * 2];\n asm volatile(\n \"{\\n\"\n \".reg .b8 fp4_byte;\\n\"\n \"mov.b32 {fp4_byte, _, _, _}, %1;\\n\"\n \"cvt.rn.f16x2.e2m1x2 %0, fp4_byte;\\n\"\n \"}\"\n : \"=r\"(fp16x2)\n : \"r\"(b));\n __half2 h2 = *reinterpret_cast<__half2*>(&fp16x2);\n reinterpret_cast<float2*>(dst)[i] = __half22float2(h2);\n }\n#else\n constexpr float lut[16] = {\n 0.0f, 0.5f, 1.0f, 1.5f, 2.0f, 3.0f, 4.0f, 6.0f,\n -0.0f, -0.5f, -1.0f, -1.5f, -2.0f, -3.0f, -4.0f, -6.0f,\n };\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint8_t b = reinterpret_cast<const uint8_t*>(src)[i * 2];\n dst[i * 2 + 0] = lut[b & 0x0F];\n dst[i * 2 + 1] = lut[(b >> 4) & 0x0F];\n }\n#endif\n }\n};\n\ntemplate <>\nstruct vec_cast<nv_bfloat16, __nv_fp4x2_e2m1> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(nv_bfloat16* dst, const __nv_fp4x2_e2m1* src) {\n static_assert(vec_size % 2 == 0, \"vec_size must be even for fp4x2 dequantization\");\n#if (defined __CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint32_t y;\n // Valid fp4x2 bytes are at even positions (stride 2); odd positions are padding.\n uint32_t b = reinterpret_cast<const uint8_t*>(src)[i * 2];\n#if (defined __CUDACC_VER_MAJOR__) && (defined __CUDACC_VER_MINOR__) && \\\n ((__CUDACC_VER_MAJOR__ > 13) || ((__CUDACC_VER_MAJOR__ == 13) && (__CUDACC_VER_MINOR__ >= 2)))\n // cvt.rn.bf16x2.e2m1x2 requires CUDA Toolkit >= 13.2\n asm volatile(\n \"{\\n\"\n \".reg .b8 fp4_byte;\\n\"\n \"mov.b32 {fp4_byte, _, _, _}, %1;\\n\"\n \"cvt.rn.bf16x2.e2m1x2 %0, fp4_byte;\\n\"\n \"}\"\n : \"=r\"(y)\n : \"r\"(b));\n#else\n // Fallback: convert e2m1 -> fp16 -> bf16 when cvt.rn.bf16x2.e2m1x2 is unavailable\n uint32_t fp16x2;\n asm volatile(\n \"{\\n\"\n \".reg .b8 fp4_byte;\\n\"\n \"mov.b32 {fp4_byte, _, _, _}, %1;\\n\"\n \"cvt.rn.f16x2.e2m1x2 %0, fp4_byte;\\n\"\n \"}\"\n : \"=r\"(fp16x2)\n : \"r\"(b));\n __half2 h2 = reinterpret_cast<__half2&>(fp16x2);\n __nv_bfloat162 bf16x2 = __float22bfloat162_rn(__half22float2(h2));\n y = reinterpret_cast<uint32_t&>(bf16x2);\n#endif\n reinterpret_cast<uint32_t*>(dst)[i] = y;\n }\n#else\n // Software LUT fallback for arch < SM100.\n // e2m1 encoding: bit[3]=sign, bit[2:0]=magnitude index in {0,0.5,1,1.5,2,3,4,6}.\n // Each packed byte holds two fp4 values: bits[3:0]=first, bits[7:4]=second.\n constexpr uint16_t lut[16] = {\n 0x0000, // +0.0\n 0x3F00, // +0.5\n 0x3F80, // +1.0\n 0x3FC0, // +1.5\n 0x4000, // +2.0\n 0x4040, // +3.0\n 0x4080, // +4.0\n 0x40C0, // +6.0\n 0x8000, // -0.0\n 0xBF00, // -0.5\n 0xBF80, // -1.0\n 0xBFC0, // -1.5\n 0xC000, // -2.0\n 0xC040, // -3.0\n 0xC080, // -4.0\n 0xC0C0, // -6.0\n };\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint8_t b = reinterpret_cast<const uint8_t*>(src)[i * 2];\n reinterpret_cast<uint16_t*>(dst)[i * 2 + 0] = lut[b & 0x0F];\n reinterpret_cast<uint16_t*>(dst)[i * 2 + 1] = lut[(b >> 4) & 0x0F];\n }\n#endif\n }\n};\n\n#endif // FLASHINFER_ENABLE_FP4_E2M1 && CUDA_VERSION >= 12080\n\ntemplate <>\nstruct vec_cast<float, nv_bfloat16> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(float* dst, const nv_bfloat16* src) {\n if constexpr (vec_size == 1) {\n dst[0] = (float)src[0];\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n ((float2*)dst)[i] = __bfloat1622float2(((nv_bfloat162*)src)[i]);\n }\n }\n }\n};\n\ntemplate <>\nstruct vec_cast<nv_bfloat16, float> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(nv_bfloat16* dst, const float* src) {\n if constexpr (vec_size == 1) {\n dst[0] = nv_bfloat16(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n ((nv_bfloat162*)dst)[i] = __float22bfloat162_rn(((float2*)src)[i]);\n }\n }\n }\n};\n\ntemplate <typename float_t, size_t vec_size>\nstruct vec_t {\n FLASHINFER_INLINE float_t& operator[](size_t i);\n FLASHINFER_INLINE const float_t& operator[](size_t i) const;\n FLASHINFER_INLINE void fill(float_t val);\n FLASHINFER_INLINE void load(const float_t* ptr);\n FLASHINFER_INLINE void store(float_t* ptr) const;\n FLASHINFER_INLINE void load_global_acquire(float* addr);\n FLASHINFER_INLINE void store_global_release(float* addr) const;\n FLASHINFER_INLINE void load_global_volatile(float* addr);\n FLASHINFER_INLINE void store_global_volatile(float* addr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src);\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr);\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const;\n FLASHINFER_INLINE static void memcpy(float_t* dst, const float_t* src);\n FLASHINFER_INLINE float_t* ptr();\n};\n\ntemplate <typename src_float_t, typename tgt_float_t, size_t vec_size>\nFLASHINFER_INLINE void cast_from_impl(vec_t<tgt_float_t, vec_size>& dst,\n const vec_t<src_float_t, vec_size>& src) {\n vec_cast<tgt_float_t, src_float_t>::cast<vec_size>(\n dst.ptr(), const_cast<vec_t<src_float_t, vec_size>*>(&src)->ptr());\n}\n\ntemplate <typename src_float_t, typename tgt_float_t, size_t vec_size>\nFLASHINFER_INLINE void cast_load_impl(vec_t<tgt_float_t, vec_size>& dst,\n const src_float_t* src_ptr) {\n if constexpr (std::is_same_v<src_float_t, tgt_float_t>) {\n dst.load(src_ptr);\n } else {\n vec_t<src_float_t, vec_size> tmp;\n tmp.load(src_ptr);\n dst.cast_from(tmp);\n }\n}\n\ntemplate <typename src_float_t, typename tgt_float_t, size_t vec_size>\nFLASHINFER_INLINE void cast_store_impl(tgt_float_t* dst_ptr,\n const vec_t<src_float_t, vec_size>& src) {\n if constexpr (std::is_same_v<src_float_t, tgt_float_t>) {\n src.store(dst_ptr);\n } else {\n vec_t<tgt_float_t, vec_size> tmp;\n tmp.cast_from(src);\n tmp.store(dst_ptr);\n }\n}\n\n/******************* vec_t<__nv_fp8_e4m3> *******************/\n\n// __nv_fp8_e4m3 x 1\ntemplate <>\nstruct vec_t<__nv_fp8_e4m3, 1> {\n __nv_fp8_e4m3 data;\n\n FLASHINFER_INLINE __nv_fp8_e4m3& operator[](size_t i) { return ((__nv_fp8_e4m3*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e4m3& operator[](size_t i) const {\n return ((const __nv_fp8_e4m3*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e4m3* ptr() { return reinterpret_cast<__nv_fp8_e4m3*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e4m3 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e4m3* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e4m3* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 1>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e4m3* dst, const __nv_fp8_e4m3* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 1>::fill(__nv_fp8_e4m3 val) { data = val; }\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 1>::load(const __nv_fp8_e4m3* ptr) { data = *ptr; }\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 1>::store(__nv_fp8_e4m3* ptr) const { *ptr = data; }\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 1>::memcpy(__nv_fp8_e4m3* dst,\n const __nv_fp8_e4m3* src) {\n *dst = *src;\n}\n\n// __nv_fp8_e4m3 x 2\ntemplate <>\nstruct vec_t<__nv_fp8_e4m3, 2> {\n __nv_fp8x2_e4m3 data;\n\n FLASHINFER_INLINE __nv_fp8_e4m3& operator[](size_t i) { return ((__nv_fp8_e4m3*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e4m3& operator[](size_t i) const {\n return ((const __nv_fp8_e4m3*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e4m3* ptr() { return reinterpret_cast<__nv_fp8_e4m3*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e4m3 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e4m3* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e4m3* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 2>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e4m3* dst, const __nv_fp8_e4m3* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 2>::fill(__nv_fp8_e4m3 val) {\n data.__x = (__nv_fp8x2_storage_t(val.__x) << 8) | __nv_fp8x2_storage_t(val.__x);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 2>::load(const __nv_fp8_e4m3* ptr) {\n data = *((__nv_fp8x2_e4m3*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 2>::store(__nv_fp8_e4m3* ptr) const {\n *((__nv_fp8x2_e4m3*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 2>::memcpy(__nv_fp8_e4m3* dst,\n const __nv_fp8_e4m3* src) {\n *((__nv_fp8x2_e4m3*)dst) = *((__nv_fp8x2_e4m3*)src);\n}\n\n// __nv_fp8_e4m3 x 4\n\ntemplate <>\nstruct vec_t<__nv_fp8_e4m3, 4> {\n __nv_fp8x4_e4m3 data;\n\n FLASHINFER_INLINE __nv_fp8_e4m3& operator[](size_t i) { return ((__nv_fp8_e4m3*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e4m3& operator[](size_t i) const {\n return ((const __nv_fp8_e4m3*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e4m3* ptr() { return reinterpret_cast<__nv_fp8_e4m3*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e4m3 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e4m3* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e4m3* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 4>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e4m3* dst, const __nv_fp8_e4m3* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 4>::fill(__nv_fp8_e4m3 val) {\n data.__x = (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 4>::load(const __nv_fp8_e4m3* ptr) {\n data = *((__nv_fp8x4_e4m3*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 4>::store(__nv_fp8_e4m3* ptr) const {\n *((__nv_fp8x4_e4m3*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 4>::memcpy(__nv_fp8_e4m3* dst,\n const __nv_fp8_e4m3* src) {\n *((__nv_fp8x4_e4m3*)dst) = *((__nv_fp8x4_e4m3*)src);\n}\n\n// __nv_fp8_e4m3 x 8\n\ntemplate <>\nstruct vec_t<__nv_fp8_e4m3, 8> {\n uint2 data;\n\n FLASHINFER_INLINE __nv_fp8_e4m3& operator[](size_t i) { return ((__nv_fp8_e4m3*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e4m3& operator[](size_t i) const {\n return ((const __nv_fp8_e4m3*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e4m3* ptr() { return reinterpret_cast<__nv_fp8_e4m3*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e4m3 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e4m3* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e4m3* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 8>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e4m3* dst, const __nv_fp8_e4m3* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 8>::fill(__nv_fp8_e4m3 val) {\n ((__nv_fp8x4_e4m3*)(&data.x))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e4m3*)(&data.y))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 8>::load(const __nv_fp8_e4m3* ptr) {\n data = *((uint2*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 8>::store(__nv_fp8_e4m3* ptr) const {\n *((uint2*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 8>::memcpy(__nv_fp8_e4m3* dst,\n const __nv_fp8_e4m3* src) {\n *((uint2*)dst) = *((uint2*)src);\n}\n\n// __nv_fp8_e4m3 x 16 or more\ntemplate <size_t vec_size>\nstruct vec_t<__nv_fp8_e4m3, vec_size> {\n static_assert(vec_size % 16 == 0, \"Invalid vector size\");\n int4 data[vec_size / 16];\n\n FLASHINFER_INLINE __nv_fp8_e4m3& operator[](size_t i) { return ((__nv_fp8_e4m3*)data)[i]; }\n FLASHINFER_INLINE const __nv_fp8_e4m3& operator[](size_t i) const {\n return ((const __nv_fp8_e4m3*)data)[i];\n }\n FLASHINFER_INLINE __nv_fp8_e4m3* ptr() { return reinterpret_cast<__nv_fp8_e4m3*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e4m3 val) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((__nv_fp8x4_e4m3*)(&(data[i].x)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e4m3*)(&(data[i].y)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e4m3*)(&(data[i].z)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e4m3*)(&(data[i].w)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n }\n }\n FLASHINFER_INLINE void load(const __nv_fp8_e4m3* ptr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i] = ((int4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(__nv_fp8_e4m3* ptr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((int4*)ptr)[i] = data[i];\n }\n }\n FLASHINFER_INLINE void load_global_acquire(__nv_fp8_e4m3* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n *((int4*)(data + i)) = ld_global_acquire((int4*)(addr + i * 16));\n }\n }\n FLASHINFER_INLINE void store_global_release(__nv_fp8_e4m3* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n st_global_release(data[i], (int4*)(addr + i * 16));\n }\n }\n FLASHINFER_INLINE void load_global_volatile(__nv_fp8_e4m3* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i] = ld_global_volatile((int4*)(addr + i * 16));\n }\n }\n FLASHINFER_INLINE void store_global_volatile(__nv_fp8_e4m3* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n st_global_volatile(data[i], (int4*)(addr + i * 16));\n }\n }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e4m3* dst, const __nv_fp8_e4m3* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((int4*)dst)[i] = ((int4*)src)[i];\n }\n }\n};\n\n/******************* vec_t<__nv_fp8_e5m2> *******************/\n\n// __nv_fp8_e5m2 x 1\ntemplate <>\nstruct vec_t<__nv_fp8_e5m2, 1> {\n __nv_fp8_e5m2 data;\n\n FLASHINFER_INLINE __nv_fp8_e5m2& operator[](size_t i) { return ((__nv_fp8_e5m2*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e5m2& operator[](size_t i) const {\n return ((const __nv_fp8_e5m2*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e5m2* ptr() { return reinterpret_cast<__nv_fp8_e5m2*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e5m2 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e5m2* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e5m2* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 1>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e5m2* dst, const __nv_fp8_e5m2* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 1>::fill(__nv_fp8_e5m2 val) { data = val; }\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 1>::load(const __nv_fp8_e5m2* ptr) { data = *ptr; }\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 1>::store(__nv_fp8_e5m2* ptr) const { *ptr = data; }\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 1>::memcpy(__nv_fp8_e5m2* dst,\n const __nv_fp8_e5m2* src) {\n *dst = *src;\n}\n\n// __nv_fp8_e5m2 x 2\ntemplate <>\nstruct vec_t<__nv_fp8_e5m2, 2> {\n __nv_fp8x2_e5m2 data;\n\n FLASHINFER_INLINE __nv_fp8_e5m2& operator[](size_t i) { return ((__nv_fp8_e5m2*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e5m2& operator[](size_t i) const {\n return ((const __nv_fp8_e5m2*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e5m2* ptr() { return reinterpret_cast<__nv_fp8_e5m2*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e5m2 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e5m2* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e5m2* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 2>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e5m2* dst, const __nv_fp8_e5m2* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 2>::fill(__nv_fp8_e5m2 val) {\n data.__x = (__nv_fp8x2_storage_t(val.__x) << 8) | __nv_fp8x2_storage_t(val.__x);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 2>::load(const __nv_fp8_e5m2* ptr) {\n data = *((__nv_fp8x2_e5m2*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 2>::store(__nv_fp8_e5m2* ptr) const {\n *((__nv_fp8x2_e5m2*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 2>::memcpy(__nv_fp8_e5m2* dst,\n const __nv_fp8_e5m2* src) {\n *((__nv_fp8x2_e5m2*)dst) = *((__nv_fp8x2_e5m2*)src);\n}\n\n// __nv_fp8_e5m2 x 4\n\ntemplate <>\nstruct vec_t<__nv_fp8_e5m2, 4> {\n __nv_fp8x4_e5m2 data;\n\n FLASHINFER_INLINE __nv_fp8_e5m2& operator[](size_t i) { return ((__nv_fp8_e5m2*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e5m2& operator[](size_t i) const {\n return ((const __nv_fp8_e5m2*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e5m2* ptr() { return reinterpret_cast<__nv_fp8_e5m2*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e5m2 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e5m2* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e5m2* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 4>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e5m2* dst, const __nv_fp8_e5m2* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 4>::fill(__nv_fp8_e5m2 val) {\n data.__x = (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 4>::load(const __nv_fp8_e5m2* ptr) {\n data = *((__nv_fp8x4_e5m2*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 4>::store(__nv_fp8_e5m2* ptr) const {\n *((__nv_fp8x4_e5m2*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 4>::memcpy(__nv_fp8_e5m2* dst,\n const __nv_fp8_e5m2* src) {\n *((__nv_fp8x4_e5m2*)dst) = *((__nv_fp8x4_e5m2*)src);\n}\n\n// __nv_fp8_e5m2 x 8\n\ntemplate <>\nstruct vec_t<__nv_fp8_e5m2, 8> {\n uint2 data;\n\n FLASHINFER_INLINE __nv_fp8_e5m2& operator[](size_t i) { return ((__nv_fp8_e5m2*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e5m2& operator[](size_t i) const {\n return ((const __nv_fp8_e5m2*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e5m2* ptr() { return reinterpret_cast<__nv_fp8_e5m2*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e5m2 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e5m2* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e5m2* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 8>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e5m2* dst, const __nv_fp8_e5m2* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 8>::fill(__nv_fp8_e5m2 val) {\n ((__nv_fp8x4_e5m2*)(&data.x))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e5m2*)(&data.y))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 8>::load(const __nv_fp8_e5m2* ptr) {\n data = *((uint2*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 8>::store(__nv_fp8_e5m2* ptr) const {\n *((uint2*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 8>::memcpy(__nv_fp8_e5m2* dst,\n const __nv_fp8_e5m2* src) {\n *((uint2*)dst) = *((uint2*)src);\n}\n\n// __nv_fp8_e5m2 x 16 or more\n\ntemplate <size_t vec_size>\nstruct vec_t<__nv_fp8_e5m2, vec_size> {\n static_assert(vec_size % 16 == 0, \"Invalid vector size\");\n int4 data[vec_size / 16];\n\n FLASHINFER_INLINE __nv_fp8_e5m2& operator[](size_t i) { return ((__nv_fp8_e5m2*)data)[i]; }\n FLASHINFER_INLINE const __nv_fp8_e5m2& operator[](size_t i) const {\n return ((const __nv_fp8_e5m2*)data)[i];\n }\n FLASHINFER_INLINE __nv_fp8_e5m2* ptr() { return reinterpret_cast<__nv_fp8_e5m2*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e5m2 val) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((__nv_fp8x4_e5m2*)(&(data[i].x)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e5m2*)(&(data[i].y)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e5m2*)(&(data[i].z)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e5m2*)(&(data[i].w)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n }\n }\n FLASHINFER_INLINE void load(const __nv_fp8_e5m2* ptr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i] = ((int4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(__nv_fp8_e5m2* ptr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((int4*)ptr)[i] = data[i];\n }\n }\n FLASHINFER_INLINE void store_global_release(__nv_fp8_e5m2* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n st_global_release(data[i], (int4*)(addr + i * 16));\n }\n }\n FLASHINFER_INLINE void load_global_acquire(__nv_fp8_e5m2* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i] = ld_global_acquire((int4*)(addr + i * 16));\n }\n }\n FLASHINFER_INLINE void store_global_volatile(__nv_fp8_e5m2* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n st_global_volatile(data[i], (int4*)(addr + i * 16));\n }\n }\n FLASHINFER_INLINE void load_global_volatile(__nv_fp8_e5m2* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i] = ld_global_volatile((int4*)(addr + i * 16));\n }\n }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e5m2* dst, const __nv_fp8_e5m2* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((int4*)dst)[i] = ((int4*)src)[i];\n }\n }\n};\n\n#if defined(FLASHINFER_ENABLE_FP4_E2M1) && CUDA_VERSION >= 12080\n/******************* vec_t<__nv_fp4x2_e2m1> *******************/\n\n// __nv_fp4x2_e2m1 is used as a one-byte packed container for FP4 KV-cache data.\n// The current FA2 NVFP4 path stores valid packed bytes at even positions and padding at odd\n// positions, so vec_size still counts logical elements in the surrounding kernels.\ntemplate <size_t vec_size>\nstruct vec_t<__nv_fp4x2_e2m1, vec_size> {\n static_assert(vec_size % 16 == 0, \"Invalid vector size\");\n int4 data[vec_size / 16];\n\n FLASHINFER_INLINE __nv_fp4x2_e2m1& operator[](size_t i) { return ((__nv_fp4x2_e2m1*)data)[i]; }\n FLASHINFER_INLINE const __nv_fp4x2_e2m1& operator[](size_t i) const {\n return ((const __nv_fp4x2_e2m1*)data)[i];\n }\n FLASHINFER_INLINE __nv_fp4x2_e2m1* ptr() { return reinterpret_cast<__nv_fp4x2_e2m1*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp4x2_e2m1 val) {\n uint32_t val8 = __nv_fp4x2_storage_t(val.__x);\n uint32_t val16 = (val8 << 8) | val8;\n uint32_t val32 = (val16 << 16) | val16;\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i].x = val32;\n data[i].y = val32;\n data[i].z = val32;\n data[i].w = val32;\n }\n }\n FLASHINFER_INLINE void load(const __nv_fp4x2_e2m1* ptr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i] = ((int4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(__nv_fp4x2_e2m1* ptr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((int4*)ptr)[i] = data[i];\n }\n }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(__nv_fp4x2_e2m1* dst, const __nv_fp4x2_e2m1* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((int4*)dst)[i] = ((int4*)src)[i];\n }\n }\n};\n\n/******************* vec_t<__nv_fp4_e2m1> *******************/\n\n// __nv_fp4_e2m1 x 2\ntemplate <>\nstruct vec_t<__nv_fp4_e2m1, 2> {\n uint8_t data;\n // index access is not supported for sub-byte data type\n FLASHINFER_INLINE __nv_fp4_e2m1* ptr() { return reinterpret_cast<__nv_fp4_e2m1*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp4_e2m1 val) {\n data = (__nv_fp4x2_storage_t(val.__x) << 4) | __nv_fp4x2_storage_t(val.__x);\n }\n FLASHINFER_INLINE void load(const __nv_fp4_e2m1* ptr) { data = *((uint8_t*)ptr); }\n FLASHINFER_INLINE void store(__nv_fp4_e2m1* ptr) const { *((uint8_t*)ptr) = data; }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 2>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(__nv_fp4_e2m1* dst, const __nv_fp4_e2m1* src) {\n *((uint8_t*)dst) = *((uint8_t*)src);\n }\n};\n\n// __nv_fp4_e2m1 x 4\ntemplate <>\nstruct vec_t<__nv_fp4_e2m1, 4> {\n uint16_t data;\n\n FLASHINFER_INLINE __nv_fp4_e2m1* ptr() { return reinterpret_cast<__nv_fp4_e2m1*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp4_e2m1 val) {\n __nv_fp4x2_storage_t val8 =\n (__nv_fp4x2_storage_t(val.__x) << 4) | __nv_fp4x2_storage_t(val.__x);\n data = (uint16_t(val8) << 8) | uint16_t(val8);\n }\n FLASHINFER_INLINE void load(const __nv_fp4_e2m1* ptr) { data = *((uint16_t*)ptr); }\n FLASHINFER_INLINE void store(__nv_fp4_e2m1* ptr) const { *((uint16_t*)ptr) = data; }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 4>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(__nv_fp4_e2m1* dst, const __nv_fp4_e2m1* src) {\n *((uint16_t*)dst) = *((uint16_t*)src);\n }\n};\n\n// __nv_fp4_e2m1 x 8\ntemplate <>\nstruct vec_t<__nv_fp4_e2m1, 8> {\n uint32_t data;\n\n FLASHINFER_INLINE __nv_fp4_e2m1* ptr() { return reinterpret_cast<__nv_fp4_e2m1*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp4_e2m1 val) {\n __nv_fp4x2_storage_t val8 =\n (__nv_fp4x2_storage_t(val.__x) << 4) | __nv_fp4x2_storage_t(val.__x);\n uint16_t val16 = (uint16_t(val8) << 8) | uint16_t(val8);\n data = (uint32_t(val16) << 16) | uint32_t(val16);\n }\n FLASHINFER_INLINE void load(const __nv_fp4_e2m1* ptr) { data = *((uint32_t*)ptr); }\n FLASHINFER_INLINE void store(__nv_fp4_e2m1* ptr) const { *((uint32_t*)ptr) = data; }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 8>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(__nv_fp4_e2m1* dst, const __nv_fp4_e2m1* src) {\n *((uint32_t*)dst) = *((uint32_t*)src);\n }\n};\n\ntemplate <>\nstruct vec_t<__nv_fp4_e2m1, 16> {\n uint2 data;\n FLASHINFER_INLINE __nv_fp4_e2m1* ptr() { return reinterpret_cast<__nv_fp4_e2m1*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp4_e2m1 val) {\n __nv_fp4x2_storage_t val8 =\n (__nv_fp4x2_storage_t(val.__x) << 4) | __nv_fp4x2_storage_t(val.__x);\n uint16_t val16 = (uint16_t(val8) << 8) | uint16_t(val8);\n uint32_t val32 = (uint32_t(val16) << 16) | uint32_t(val16);\n data.x = val32;\n data.y = val32;\n }\n FLASHINFER_INLINE void load(const __nv_fp4_e2m1* ptr) { data = *((uint2*)ptr); }\n FLASHINFER_INLINE void store(__nv_fp4_e2m1* ptr) const { *((uint2*)ptr) = data; }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 16>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(__nv_fp4_e2m1* dst, const __nv_fp4_e2m1* src) {\n *((uint2*)dst) = *((uint2*)src);\n }\n};\n\n// __nv_fp4_e2m1 x 32 or more\ntemplate <size_t vec_size>\nstruct vec_t<__nv_fp4_e2m1, vec_size> {\n static_assert(vec_size % 32 == 0, \"Invalid vector size\");\n int4 data[vec_size / 32];\n\n FLASHINFER_INLINE __nv_fp4_e2m1* ptr() { return reinterpret_cast<__nv_fp4_e2m1*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp4_e2m1 val) {\n __nv_fp4x2_storage_t val8 =\n (__nv_fp4x2_storage_t(val.__x) << 4) | __nv_fp4x2_storage_t(val.__x);\n uint16_t val16 = (uint16_t(val8) << 8) | uint16_t(val8);\n uint32_t val32 = (uint32_t(val16) << 16) | uint32_t(val16);\n#pragma unroll\n for (size_t i = 0; i < vec_size / 32; ++i) {\n data[i].x = val32;\n data[i].y = val32;\n data[i].z = val32;\n data[i].w = val32;\n }\n }\n FLASHINFER_INLINE void load(const __nv_fp4_e2m1* ptr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 32; ++i) {\n data[i] = ((int4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(__nv_fp4_e2m1* ptr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 32; ++i) {\n ((int4*)ptr)[i] = data[i];\n }\n }\n FLASHINFER_INLINE void store_global_release(__nv_fp4_e2m1* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 32; ++i) {\n st_global_release(*(int4*)&data[i], (int4*)(addr + i * 16));\n }\n }\n FLASHINFER_INLINE void load_global_acquire(__nv_fp4_e2m1* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 32; ++i) {\n *(int4*)&data[i] = ld_global_acquire((int4*)(addr + i * 16));\n }\n }\n FLASHINFER_INLINE void store_global_volatile(__nv_fp4_e2m1* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 32; ++i) {\n st_global_volatile(*(int4*)&data[i], (int4*)(addr + i * 16));\n }\n }\n FLASHINFER_INLINE void load_global_volatile(__nv_fp4_e2m1* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 32; ++i) {\n *(int4*)&data[i] = ld_global_volatile((int4*)(addr + i * 16));\n }\n }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(__nv_fp4_e2m1* dst, const __nv_fp4_e2m1* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 32; ++i) {\n ((int4*)dst)[i] = ((int4*)src)[i];\n }\n }\n};\n\n#endif // FLASHINFER_ENABLE_FP4_E2M1 && CUDA_VERSION >= 12080\n\n/******************* vec_t<half> *******************/\n\n// half x 1\ntemplate <>\nstruct vec_t<half, 1> {\n half data;\n\n FLASHINFER_INLINE half& operator[](size_t i) { return ((half*)(&data))[i]; }\n FLASHINFER_INLINE const half& operator[](size_t i) const { return ((const half*)(&data))[i]; }\n FLASHINFER_INLINE half* ptr() { return reinterpret_cast<half*>(&data); }\n FLASHINFER_INLINE void fill(half val);\n FLASHINFER_INLINE void load(const half* ptr);\n FLASHINFER_INLINE void store(half* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 1>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(half* dst, const half* src);\n};\n\nFLASHINFER_INLINE void vec_t<half, 1>::fill(half val) { data = val; }\n\nFLASHINFER_INLINE void vec_t<half, 1>::load(const half* ptr) { data = *ptr; }\n\nFLASHINFER_INLINE void vec_t<half, 1>::store(half* ptr) const { *ptr = data; }\n\nFLASHINFER_INLINE void vec_t<half, 1>::memcpy(half* dst, const half* src) { *dst = *src; }\n\n// half x 2\ntemplate <>\nstruct vec_t<half, 2> {\n half2 data;\n\n FLASHINFER_INLINE half& operator[](size_t i) { return ((half*)(&data))[i]; }\n FLASHINFER_INLINE const half& operator[](size_t i) const { return ((const half*)(&data))[i]; }\n FLASHINFER_INLINE half* ptr() { return reinterpret_cast<half*>(&data); }\n FLASHINFER_INLINE void fill(half val);\n FLASHINFER_INLINE void load(const half* ptr);\n FLASHINFER_INLINE void store(half* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 2>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(half* dst, const half* src);\n};\n\nFLASHINFER_INLINE void vec_t<half, 2>::fill(half val) { data = make_half2(val, val); }\n\nFLASHINFER_INLINE void vec_t<half, 2>::load(const half* ptr) { data = *((half2*)ptr); }\n\nFLASHINFER_INLINE void vec_t<half, 2>::store(half* ptr) const { *((half2*)ptr) = data; }\n\nFLASHINFER_INLINE void vec_t<half, 2>::memcpy(half* dst, const half* src) {\n *((half2*)dst) = *((half2*)src);\n}\n\n// half x 4\n\ntemplate <>\nstruct vec_t<half, 4> {\n uint2 data;\n\n FLASHINFER_INLINE half& operator[](size_t i) { return ((half*)(&data))[i]; }\n FLASHINFER_INLINE const half& operator[](size_t i) const { return ((const half*)(&data))[i]; }\n FLASHINFER_INLINE half* ptr() { return reinterpret_cast<half*>(&data); }\n FLASHINFER_INLINE void fill(half val);\n FLASHINFER_INLINE void load(const half* ptr);\n FLASHINFER_INLINE void store(half* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 4>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(half* dst, const half* src);\n};\n\nFLASHINFER_INLINE void vec_t<half, 4>::fill(half val) {\n *(half2*)(&data.x) = make_half2(val, val);\n *(half2*)(&data.y) = make_half2(val, val);\n}\n\nFLASHINFER_INLINE void vec_t<half, 4>::load(const half* ptr) { data = *((uint2*)ptr); }\n\nFLASHINFER_INLINE void vec_t<half, 4>::store(half* ptr) const { *((uint2*)ptr) = data; }\n\nFLASHINFER_INLINE void vec_t<half, 4>::memcpy(half* dst, const half* src) {\n *((uint2*)dst) = *((uint2*)src);\n}\n\n// half x 8 or more\n\ntemplate <size_t vec_size>\nstruct vec_t<half, vec_size> {\n static_assert(vec_size % 8 == 0, \"Invalid vector size\");\n int4 data[vec_size / 8];\n FLASHINFER_INLINE half& operator[](size_t i) { return ((half*)data)[i]; }\n FLASHINFER_INLINE const half& operator[](size_t i) const { return ((const half*)data)[i]; }\n FLASHINFER_INLINE half* ptr() { return reinterpret_cast<half*>(&data); }\n FLASHINFER_INLINE void fill(half val) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n *(half2*)(&(data[i].x)) = make_half2(val, val);\n *(half2*)(&(data[i].y)) = make_half2(val, val);\n *(half2*)(&(data[i].z)) = make_half2(val, val);\n *(half2*)(&(data[i].w)) = make_half2(val, val);\n }\n }\n FLASHINFER_INLINE void load(const half* ptr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n data[i] = ((int4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(half* ptr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n ((int4*)ptr)[i] = data[i];\n }\n }\n FLASHINFER_INLINE void load_global_acquire(half* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n data[i] = ld_global_acquire((int4*)(addr + i * 8));\n }\n }\n FLASHINFER_INLINE void store_global_release(half* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n st_global_release(data[i], (int4*)(addr + i * 8));\n }\n }\n FLASHINFER_INLINE void store_global_volatile(half* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n st_global_volatile(data[i], (int4*)(addr + i * 8));\n }\n }\n FLASHINFER_INLINE void load_global_volatile(half* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n data[i] = ld_global_volatile((int4*)(addr + i * 8));\n }\n }\n\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(half* dst, const half* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n ((int4*)dst)[i] = ((int4*)src)[i];\n }\n }\n};\n\n/******************* vec_t<nv_bfloat16> *******************/\n\n// nv_bfloat16 x 1\ntemplate <>\nstruct vec_t<nv_bfloat16, 1> {\n nv_bfloat16 data;\n FLASHINFER_INLINE nv_bfloat16& operator[](size_t i) { return ((nv_bfloat16*)(&data))[i]; }\n FLASHINFER_INLINE const nv_bfloat16& operator[](size_t i) const {\n return ((const nv_bfloat16*)(&data))[i];\n }\n FLASHINFER_INLINE nv_bfloat16* ptr() { return reinterpret_cast<nv_bfloat16*>(&data); }\n FLASHINFER_INLINE void fill(nv_bfloat16 val);\n FLASHINFER_INLINE void load(const nv_bfloat16* ptr);\n FLASHINFER_INLINE void store(nv_bfloat16* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 1>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(nv_bfloat16* dst, const nv_bfloat16* src);\n};\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 1>::fill(nv_bfloat16 val) { data = val; }\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 1>::load(const nv_bfloat16* ptr) { data = *ptr; }\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 1>::store(nv_bfloat16* ptr) const { *ptr = data; }\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 1>::memcpy(nv_bfloat16* dst, const nv_bfloat16* src) {\n *dst = *src;\n}\n\n// nv_bfloat16 x 2\ntemplate <>\nstruct vec_t<nv_bfloat16, 2> {\n nv_bfloat162 data;\n\n FLASHINFER_INLINE nv_bfloat16& operator[](size_t i) { return ((nv_bfloat16*)(&data))[i]; }\n FLASHINFER_INLINE const nv_bfloat16& operator[](size_t i) const {\n return ((const nv_bfloat16*)(&data))[i];\n }\n FLASHINFER_INLINE nv_bfloat16* ptr() { return reinterpret_cast<nv_bfloat16*>(&data); }\n FLASHINFER_INLINE void fill(nv_bfloat16 val);\n FLASHINFER_INLINE void load(const nv_bfloat16* ptr);\n FLASHINFER_INLINE void store(nv_bfloat16* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 2>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(nv_bfloat16* dst, const nv_bfloat16* src);\n};\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 2>::fill(nv_bfloat16 val) {\n data = make_bfloat162(val, val);\n}\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 2>::load(const nv_bfloat16* ptr) {\n data = *((nv_bfloat162*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 2>::store(nv_bfloat16* ptr) const {\n *((nv_bfloat162*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 2>::memcpy(nv_bfloat16* dst, const nv_bfloat16* src) {\n *((nv_bfloat162*)dst) = *((nv_bfloat162*)src);\n}\n\n// nv_bfloat16 x 4\n\ntemplate <>\nstruct vec_t<nv_bfloat16, 4> {\n uint2 data;\n\n FLASHINFER_INLINE nv_bfloat16& operator[](size_t i) { return ((nv_bfloat16*)(&data))[i]; }\n FLASHINFER_INLINE const nv_bfloat16& operator[](size_t i) const {\n return ((const nv_bfloat16*)(&data))[i];\n }\n FLASHINFER_INLINE nv_bfloat16* ptr() { return reinterpret_cast<nv_bfloat16*>(&data); }\n FLASHINFER_INLINE void fill(nv_bfloat16 val);\n FLASHINFER_INLINE void load(const nv_bfloat16* ptr);\n FLASHINFER_INLINE void store(nv_bfloat16* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 4>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(nv_bfloat16* dst, const nv_bfloat16* src);\n};\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 4>::fill(nv_bfloat16 val) {\n *(nv_bfloat162*)(&data.x) = make_bfloat162(val, val);\n *(nv_bfloat162*)(&data.y) = make_bfloat162(val, val);\n}\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 4>::load(const nv_bfloat16* ptr) {\n data = *((uint2*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 4>::store(nv_bfloat16* ptr) const {\n *((uint2*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 4>::memcpy(nv_bfloat16* dst, const nv_bfloat16* src) {\n *((uint2*)dst) = *((uint2*)src);\n}\n\n// nv_bfloat16 x 8 or more\n\ntemplate <size_t vec_size>\nstruct vec_t<nv_bfloat16, vec_size> {\n static_assert(vec_size % 8 == 0, \"Invalid vector size\");\n int4 data[vec_size / 8];\n\n FLASHINFER_INLINE nv_bfloat16& operator[](size_t i) { return ((nv_bfloat16*)data)[i]; }\n FLASHINFER_INLINE const nv_bfloat16& operator[](size_t i) const {\n return ((const nv_bfloat16*)data)[i];\n }\n FLASHINFER_INLINE nv_bfloat16* ptr() { return reinterpret_cast<nv_bfloat16*>(&data); }\n FLASHINFER_INLINE void fill(nv_bfloat16 val) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n *(nv_bfloat162*)(&(data[i].x)) = make_bfloat162(val, val);\n *(nv_bfloat162*)(&(data[i].y)) = make_bfloat162(val, val);\n *(nv_bfloat162*)(&(data[i].z)) = make_bfloat162(val, val);\n *(nv_bfloat162*)(&(data[i].w)) = make_bfloat162(val, val);\n }\n }\n FLASHINFER_INLINE void load(const nv_bfloat16* ptr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n data[i] = ((int4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(nv_bfloat16* ptr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n ((int4*)ptr)[i] = data[i];\n }\n }\n FLASHINFER_INLINE void store_global_release(nv_bfloat16* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n st_global_release(data[i], (int4*)(addr + i * 8));\n }\n }\n FLASHINFER_INLINE void load_global_acquire(nv_bfloat16* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n data[i] = ld_global_acquire((int4*)(addr + i * 8));\n }\n }\n FLASHINFER_INLINE void store_global_volatile(nv_bfloat16* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n st_global_volatile(data[i], (int4*)(addr + i * 8));\n }\n }\n FLASHINFER_INLINE void load_global_volatile(nv_bfloat16* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n data[i] = ld_global_volatile((int4*)(addr + i * 8));\n }\n }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(nv_bfloat16* dst, const nv_bfloat16* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n ((int4*)dst)[i] = ((int4*)src)[i];\n }\n }\n};\n\n/******************* vec_t<uint8_t> *******************/\n\n// uint8_t x 1\ntemplate <>\nstruct vec_t<uint8_t, 1> {\n uint8_t data;\n\n FLASHINFER_INLINE uint8_t& operator[](size_t i) { return ((uint8_t*)(&data))[i]; }\n FLASHINFER_INLINE const uint8_t& operator[](size_t i) const {\n return ((const uint8_t*)(&data))[i];\n }\n FLASHINFER_INLINE uint8_t* ptr() { return reinterpret_cast<uint8_t*>(&data); }\n FLASHINFER_INLINE void fill(uint8_t val);\n FLASHINFER_INLINE void load(const uint8_t* ptr);\n FLASHINFER_INLINE void store(uint8_t* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 1>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(uint8_t* dst, const uint8_t* src);\n};\n\nFLASHINFER_INLINE void vec_t<uint8_t, 1>::fill(uint8_t val) { data = val; }\n\nFLASHINFER_INLINE void vec_t<uint8_t, 1>::load(const uint8_t* ptr) { data = *ptr; }\n\nFLASHINFER_INLINE void vec_t<uint8_t, 1>::store(uint8_t* ptr) const { *ptr = data; }\n\nFLASHINFER_INLINE void vec_t<uint8_t, 1>::memcpy(uint8_t* dst, const uint8_t* src) { *dst = *src; }\n\n// uint8_t x 2\ntemplate <>\nstruct vec_t<uint8_t, 2> {\n uint16_t data;\n\n FLASHINFER_INLINE uint8_t& operator[](size_t i) { return ((uint8_t*)(&data))[i]; }\n FLASHINFER_INLINE const uint8_t& operator[](size_t i) const {\n return ((const uint8_t*)(&data))[i];\n }\n FLASHINFER_INLINE uint8_t* ptr() { return reinterpret_cast<uint8_t*>(&data); }\n FLASHINFER_INLINE void fill(uint8_t val);\n FLASHINFER_INLINE void load(const uint8_t* ptr);\n FLASHINFER_INLINE void store(uint8_t* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 2>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(uint8_t* dst, const uint8_t* src);\n};\n\nFLASHINFER_INLINE void vec_t<uint8_t, 2>::fill(uint8_t val) {\n data = (uint16_t(val) << 8) | uint16_t(val);\n}\n\nFLASHINFER_INLINE void vec_t<uint8_t, 2>::load(const uint8_t* ptr) { data = *((uint16_t*)ptr); }\n\nFLASHINFER_INLINE void vec_t<uint8_t, 2>::store(uint8_t* ptr) const { *((uint16_t*)ptr) = data; }\n\nFLASHINFER_INLINE void vec_t<uint8_t, 2>::memcpy(uint8_t* dst, const uint8_t* src) {\n *((uint16_t*)dst) = *((uint16_t*)src);\n}\n\n// uint8_t x 4\n\ntemplate <>\nstruct vec_t<uint8_t, 4> {\n uint32_t data;\n\n FLASHINFER_INLINE uint8_t& operator[](size_t i) { return ((uint8_t*)(&data))[i]; }\n FLASHINFER_INLINE const uint8_t& operator[](size_t i) const {\n return ((const uint8_t*)(&data))[i];\n }\n FLASHINFER_INLINE uint8_t* ptr() { return reinterpret_cast<uint8_t*>(&data); }\n FLASHINFER_INLINE void fill(uint8_t val);\n FLASHINFER_INLINE void load(const uint8_t* ptr);\n FLASHINFER_INLINE void store(uint8_t* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 4>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(uint8_t* dst, const uint8_t* src);\n};\n\nFLASHINFER_INLINE void vec_t<uint8_t, 4>::fill(uint8_t val) {\n data = (uint32_t(val) << 24) | (uint32_t(val) << 16) | (uint32_t(val) << 8) | uint32_t(val);\n}\n\nFLASHINFER_INLINE void vec_t<uint8_t, 4>::load(const uint8_t* ptr) { data = *((uint32_t*)ptr); }\n\nFLASHINFER_INLINE void vec_t<uint8_t, 4>::store(uint8_t* ptr) const { *((uint32_t*)ptr) = data; }\n\nFLASHINFER_INLINE void vec_t<uint8_t, 4>::memcpy(uint8_t* dst, const uint8_t* src) {\n *((uint32_t*)dst) = *((uint32_t*)src);\n}\n\n// uint8_t x 8\n\ntemplate <>\nstruct vec_t<uint8_t, 8> {\n uint2 data;\n\n FLASHINFER_INLINE uint8_t& operator[](size_t i) { return ((uint8_t*)(&data))[i]; }\n FLASHINFER_INLINE const uint8_t& operator[](size_t i) const {\n return ((const uint8_t*)(&data))[i];\n }\n FLASHINFER_INLINE uint8_t* ptr() { return reinterpret_cast<uint8_t*>(&data); }\n FLASHINFER_INLINE void fill(uint8_t val);\n FLASHINFER_INLINE void load(const uint8_t* ptr);\n FLASHINFER_INLINE void store(uint8_t* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 8>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(uint8_t* dst, const uint8_t* src);\n};\n\nFLASHINFER_INLINE void vec_t<uint8_t, 8>::fill(uint8_t val) {\n uint32_t val32 =\n (uint32_t(val) << 24) | (uint32_t(val) << 16) | (uint32_t(val) << 8) | uint32_t(val);\n data.x = val32;\n data.y = val32;\n}\n\nFLASHINFER_INLINE void vec_t<uint8_t, 8>::load(const uint8_t* ptr) { data = *((uint2*)ptr); }\n\nFLASHINFER_INLINE void vec_t<uint8_t, 8>::store(uint8_t* ptr) const { *((uint2*)ptr) = data; }\n\nFLASHINFER_INLINE void vec_t<uint8_t, 8>::memcpy(uint8_t* dst, const uint8_t* src) {\n *((uint2*)dst) = *((uint2*)src);\n}\n\n// uint8_t x 16 or more\n\ntemplate <size_t vec_size>\nstruct vec_t<uint8_t, vec_size> {\n static_assert(vec_size % 16 == 0, \"Invalid vector size\");\n int4 data[vec_size / 16];\n\n FLASHINFER_INLINE uint8_t& operator[](size_t i) { return ((uint8_t*)data)[i]; }\n FLASHINFER_INLINE const uint8_t& operator[](size_t i) const { return ((const uint8_t*)data)[i]; }\n FLASHINFER_INLINE uint8_t* ptr() { return reinterpret_cast<uint8_t*>(&data); }\n FLASHINFER_INLINE void fill(uint8_t val) {\n uint32_t val32 =\n (uint32_t(val) << 24) | (uint32_t(val) << 16) | (uint32_t(val) << 8) | uint32_t(val);\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i].x = val32;\n data[i].y = val32;\n data[i].z = val32;\n data[i].w = val32;\n }\n }\n FLASHINFER_INLINE void load(const uint8_t* ptr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i] = ((int4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(uint8_t* ptr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((int4*)ptr)[i] = data[i];\n }\n }\n FLASHINFER_INLINE void load_global_acquire(uint8_t* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i] = ld_global_acquire((int4*)(addr + i * 16));\n }\n }\n FLASHINFER_INLINE void store_global_release(uint8_t* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n st_global_release(data[i], (int4*)(addr + i * 16));\n }\n }\n FLASHINFER_INLINE void load_global_volatile(uint8_t* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i] = ld_global_volatile((int4*)(addr + i * 16));\n }\n }\n FLASHINFER_INLINE void store_global_volatile(uint8_t* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n st_global_volatile(data[i], (int4*)(addr + i * 16));\n }\n }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(uint8_t* dst, const uint8_t* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((int4*)dst)[i] = ((int4*)src)[i];\n }\n }\n};\n\n/******************* vec_t<float> *******************/\n\n// float x 1\n\ntemplate <>\nstruct vec_t<float, 1> {\n float data;\n\n FLASHINFER_INLINE float& operator[](size_t i) { return ((float*)(&data))[i]; }\n FLASHINFER_INLINE const float& operator[](size_t i) const { return ((const float*)(&data))[i]; }\n FLASHINFER_INLINE float* ptr() { return reinterpret_cast<float*>(&data); }\n FLASHINFER_INLINE void fill(float val);\n FLASHINFER_INLINE void load(const float* ptr);\n FLASHINFER_INLINE void store(float* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 1>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(float* dst, const float* src);\n};\n\nFLASHINFER_INLINE void vec_t<float, 1>::fill(float val) { data = val; }\n\nFLASHINFER_INLINE void vec_t<float, 1>::load(const float* ptr) { data = *ptr; }\n\nFLASHINFER_INLINE void vec_t<float, 1>::store(float* ptr) const { *ptr = data; }\n\nFLASHINFER_INLINE void vec_t<float, 1>::memcpy(float* dst, const float* src) { *dst = *src; }\n\n// float x 2\n\ntemplate <>\nstruct vec_t<float, 2> {\n float2 data;\n\n FLASHINFER_INLINE float& operator[](size_t i) { return ((float*)(&data))[i]; }\n FLASHINFER_INLINE const float& operator[](size_t i) const { return ((const float*)(&data))[i]; }\n FLASHINFER_INLINE float* ptr() { return reinterpret_cast<float*>(&data); }\n FLASHINFER_INLINE void fill(float val);\n FLASHINFER_INLINE void load(const float* ptr);\n FLASHINFER_INLINE void store(float* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 2>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(float* dst, const float* src);\n};\n\nFLASHINFER_INLINE void vec_t<float, 2>::fill(float val) { data = make_float2(val, val); }\n\nFLASHINFER_INLINE void vec_t<float, 2>::load(const float* ptr) { data = *((float2*)ptr); }\n\nFLASHINFER_INLINE void vec_t<float, 2>::store(float* ptr) const { *((float2*)ptr) = data; }\n\nFLASHINFER_INLINE void vec_t<float, 2>::memcpy(float* dst, const float* src) {\n *((float2*)dst) = *((float2*)src);\n}\n\n// float x 4 or more\ntemplate <size_t vec_size>\nstruct vec_t<float, vec_size> {\n static_assert(vec_size % 4 == 0, \"Invalid vector size\");\n float4 data[vec_size / 4];\n\n FLASHINFER_INLINE float& operator[](size_t i) { return ((float*)(data))[i]; }\n FLASHINFER_INLINE const float& operator[](size_t i) const { return ((const float*)(data))[i]; }\n FLASHINFER_INLINE float* ptr() { return reinterpret_cast<float*>(&data); }\n FLASHINFER_INLINE void fill(float val) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 4; ++i) {\n data[i] = make_float4(val, val, val, val);\n }\n }\n FLASHINFER_INLINE void load(const float* ptr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 4; ++i) {\n data[i] = ((float4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(float* ptr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 4; ++i) {\n ((float4*)ptr)[i] = data[i];\n }\n }\n FLASHINFER_INLINE void store_global_release(float* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 4; ++i) {\n st_global_release(*(int4*)(data + i), (int4*)(addr + i * 4));\n }\n }\n FLASHINFER_INLINE void load_global_acquire(float* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 4; ++i) {\n *((int4*)(data + i)) = ld_global_acquire((int4*)(addr + i * 4));\n }\n }\n FLASHINFER_INLINE void store_global_volatile(float* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 4; ++i) {\n st_global_volatile(*(int4*)(data + i), (int4*)(addr + i * 4));\n }\n }\n FLASHINFER_INLINE void load_global_volatile(float* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 4; ++i) {\n *((int4*)(data + i)) = ld_global_volatile((int4*)(addr + i * 4));\n }\n }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(float* dst, const float* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 4; ++i) {\n ((float4*)dst)[i] = ((float4*)src)[i];\n }\n }\n};\n\ntemplate <typename T>\nstruct vec2_dtype {\n using type = T;\n};\n\ntemplate <>\nstruct vec2_dtype<half> {\n using type = half2;\n};\n\ntemplate <>\nstruct vec2_dtype<__nv_bfloat16> {\n using type = __nv_bfloat162;\n};\n\ntemplate <>\nstruct vec2_dtype<__nv_fp8_e4m3> {\n using type = __nv_fp8x2_e4m3;\n};\n\ntemplate <>\nstruct vec2_dtype<__nv_fp8_e5m2> {\n using type = __nv_fp8x2_e5m2;\n};\n\ntemplate <typename T>\nusing vec2_dtype_t = typename vec2_dtype<T>::type;\n\ntemplate <typename T, size_t VEC_SIZE>\nFLASHINFER_INLINE vec2_dtype_t<T> get_vec2_element(vec_t<T, VEC_SIZE>& vec, int i) {\n static_assert(VEC_SIZE % 2 == 0, \"VEC_SIZE must be a multiple of 2\");\n return ((vec2_dtype_t<T>*)&(vec[0]))[i];\n}\n\n} // namespace flashinfer\n\n#endif // VEC_DTYPES_CUH_\n"},"after_code":{"kind":"string","value":"/*\n * Copyright (c) 2023 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef VEC_DTYPES_CUH_\n#define VEC_DTYPES_CUH_\n\n#include <cuda.h>\n#include <cuda_bf16.h>\n#include <cuda_fp16.h>\n#include <cuda_fp8.h>\n#if CUDA_VERSION >= 12080\n#include <cuda_fp4.h>\n#endif\n#include <cuda_runtime.h>\n\n#include <type_traits>\n\nnamespace flashinfer {\n\n#if (!defined(__CUDA_ARCH__) || (__CUDA_ARCH__ >= 900))\n#define FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n#endif\n\n#define FLASHINFER_INLINE inline __attribute__((always_inline)) __device__\n\n__device__ __forceinline__ void st_global_release(int4 const& val, int4* addr) {\n asm volatile(\"st.release.global.sys.v4.b32 [%4], {%0, %1, %2, %3};\" ::\"r\"(val.x), \"r\"(val.y),\n \"r\"(val.z), \"r\"(val.w), \"l\"(addr));\n}\n\n__device__ __forceinline__ int4 ld_global_acquire(int4* addr) {\n int4 val;\n asm volatile(\"ld.acquire.global.sys.v4.b32 {%0, %1, %2, %3}, [%4];\"\n : \"=r\"(val.x), \"=r\"(val.y), \"=r\"(val.z), \"=r\"(val.w)\n : \"l\"(addr));\n return val;\n}\n\n__device__ __forceinline__ void st_global_volatile(int4 const& val, int4* addr) {\n asm volatile(\"st.volatile.global.v4.b32 [%4], {%0, %1, %2, %3};\" ::\"r\"(val.x), \"r\"(val.y),\n \"r\"(val.z), \"r\"(val.w), \"l\"(addr));\n}\n\n__device__ __forceinline__ int4 ld_global_volatile(int4* addr) {\n int4 val;\n asm volatile(\"ld.volatile.global.v4.b32 {%0, %1, %2, %3}, [%4];\"\n : \"=r\"(val.x), \"=r\"(val.y), \"=r\"(val.z), \"=r\"(val.w)\n : \"l\"(addr));\n return val;\n}\n\n#if (__CUDACC_VER_MAJOR__ * 10000 + __CUDACC_VER_MINOR__ * 100 < 120200) && \\\n (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ < 800))\n// CUDA version < 12.2 and GPU architecture < 80\nFLASHINFER_INLINE __nv_bfloat162 make_bfloat162(const __nv_bfloat16 x, const __nv_bfloat16 y) {\n __nv_bfloat162 t;\n t.x = x;\n t.y = y;\n return t;\n}\n\nFLASHINFER_INLINE __nv_bfloat16 __hmul(const __nv_bfloat16 a, const __nv_bfloat16 b) {\n __nv_bfloat16 val;\n const float fa = __bfloat162float(a);\n const float fb = __bfloat162float(b);\n // avoid ftz in device code\n val = __float2bfloat16(__fmaf_ieee_rn(fa, fb, -0.0f));\n return val;\n}\n\nFLASHINFER_INLINE __nv_bfloat162 __hmul2(const __nv_bfloat162 a, const __nv_bfloat162 b) {\n __nv_bfloat162 val;\n val.x = __hmul(a.x, b.x);\n val.y = __hmul(a.y, b.y);\n return val;\n}\n\nFLASHINFER_INLINE __nv_bfloat162 __floats2bfloat162_rn(const float a, const float b) {\n __nv_bfloat162 val;\n val = __nv_bfloat162(__float2bfloat16_rn(a), __float2bfloat16_rn(b));\n return val;\n}\n\nFLASHINFER_INLINE __nv_bfloat162 __float22bfloat162_rn(const float2 a) {\n __nv_bfloat162 val = __floats2bfloat162_rn(a.x, a.y);\n return val;\n}\nFLASHINFER_INLINE float2 __bfloat1622float2(const __nv_bfloat162 a) {\n float hi_float;\n float lo_float;\n lo_float = __internal_bfloat162float(((__nv_bfloat162_raw)a).x);\n hi_float = __internal_bfloat162float(((__nv_bfloat162_raw)a).y);\n return make_float2(lo_float, hi_float);\n}\n#endif\n\n/******************* vec_t type cast *******************/\n\ntemplate <typename dst_t, typename src_t>\nstruct vec_cast {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(dst_t* dst, const src_t* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size; ++i) {\n dst[i] = (dst_t)src[i];\n }\n }\n};\n\ntemplate <>\nstruct vec_cast<__nv_fp8_e4m3, float> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(__nv_fp8_e4m3* dst, const float* src) {\n if constexpr (vec_size == 1) {\n dst[0] = __nv_fp8_e4m3(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n ((__nv_fp8x2_storage_t*)dst)[i] =\n __nv_cvt_float2_to_fp8x2(((float2*)src)[i], __NV_SATFINITE, __NV_E4M3);\n }\n }\n }\n};\n\ntemplate <>\nstruct vec_cast<__nv_fp8_e5m2, float> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(__nv_fp8_e5m2* dst, const float* src) {\n if constexpr (vec_size == 1) {\n dst[0] = __nv_fp8_e5m2(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n ((__nv_fp8x2_storage_t*)dst)[i] =\n __nv_cvt_float2_to_fp8x2(((float2*)src)[i], __NV_SATFINITE, __NV_E5M2);\n }\n }\n }\n};\n\ntemplate <>\nstruct vec_cast<float, half> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(float* dst, const half* src) {\n if constexpr (vec_size == 1) {\n dst[0] = (float)src[0];\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n ((float2*)dst)[i] = __half22float2(((half2*)src)[i]);\n }\n }\n }\n};\n\ntemplate <>\nstruct vec_cast<half, float> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(half* dst, const float* src) {\n if constexpr (vec_size == 1) {\n dst[0] = __float2half(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n ((half2*)dst)[i] = __float22half2_rn(((float2*)src)[i]);\n }\n }\n }\n};\n\ntemplate <typename T>\nconstexpr FLASHINFER_INLINE int get_exponent_bits() {\n if constexpr (std::is_same_v<T, __nv_fp8_e4m3>) {\n return 4;\n } else if constexpr (std::is_same_v<T, __nv_fp8_e5m2>) {\n return 5;\n } else if constexpr (std::is_same_v<T, half>) {\n return 5;\n } else if constexpr (std::is_same_v<T, nv_bfloat16>) {\n return 8;\n }\n}\n\ntemplate <typename T>\nconstexpr FLASHINFER_INLINE int get_mantissa_bits() {\n if constexpr (std::is_same_v<T, __nv_fp8_e4m3>) {\n return 3;\n } else if constexpr (std::is_same_v<T, __nv_fp8_e5m2>) {\n return 2;\n } else if constexpr (std::is_same_v<T, half>) {\n return 11;\n } else if constexpr (std::is_same_v<T, nv_bfloat16>) {\n return 7;\n }\n}\n\n/*!\n * \\brief Fallback to software fast dequant implementation if hardware dequantization is not\n * available.\n * \\note Inspired by Marlin's fast dequantization, but here we don't have to permute\n * weights order.\n * \\ref\n * https://github.com/vllm-project/vllm/blob/6dffa4b0a6120159ef2fe44d695a46817aff65bc/csrc/quantization/fp8/fp8_marlin.cu#L120\n */\ntemplate <typename fp8_dtype, typename fp16_dtype>\n__device__ void fast_dequant_f8f16x4(uint32_t* input, uint2* output) {\n uint32_t q = *input;\n if constexpr (std::is_same_v<fp8_dtype, __nv_fp8_e5m2> && std::is_same_v<fp16_dtype, half>) {\n output->x = __byte_perm(0U, q, 0x5140);\n output->y = __byte_perm(0U, q, 0x7362);\n } else {\n constexpr int FP8_EXPONENT = get_exponent_bits<fp8_dtype>();\n constexpr int FP8_MANTISSA = get_mantissa_bits<fp8_dtype>();\n constexpr int FP16_EXPONENT = get_exponent_bits<fp16_dtype>();\n\n constexpr int RIGHT_SHIFT = FP16_EXPONENT - FP8_EXPONENT;\n // Calculate MASK for extracting mantissa and exponent\n constexpr int MASK1 = 0x80000000;\n constexpr int MASK2 = MASK1 >> (FP8_EXPONENT + FP8_MANTISSA);\n constexpr int MASK3 = MASK2 & 0x7fffffff;\n constexpr int MASK = MASK3 | (MASK3 >> 16);\n q = __byte_perm(q, q, 0x1302);\n\n // Extract and shift FP8 values to FP16 format\n uint32_t Out1 = (q & 0x80008000) | ((q & MASK) >> RIGHT_SHIFT);\n uint32_t Out2 = ((q << 8) & 0x80008000) | (((q << 8) & MASK) >> RIGHT_SHIFT);\n\n constexpr int BIAS_OFFSET = (1 << (FP16_EXPONENT - 1)) - (1 << (FP8_EXPONENT - 1));\n // Construct and apply exponent bias\n if constexpr (std::is_same_v<fp16_dtype, half>) {\n const half2 bias_reg = __float2half2_rn(float(1 << BIAS_OFFSET));\n\n // Convert to half2 and apply bias\n *(half2*)&(output->x) = __hmul2(*reinterpret_cast<const half2*>(&Out1), bias_reg);\n *(half2*)&(output->y) = __hmul2(*reinterpret_cast<const half2*>(&Out2), bias_reg);\n } else {\n constexpr uint32_t BIAS = (BIAS_OFFSET + 127) << 23;\n const nv_bfloat162 bias_reg = __float2bfloat162_rn(*reinterpret_cast<const float*>(&BIAS));\n // Convert to bfloat162 and apply bias\n *(nv_bfloat162*)&(output->x) =\n __hmul2(*reinterpret_cast<const nv_bfloat162*>(&Out1), bias_reg);\n *(nv_bfloat162*)&(output->y) =\n __hmul2(*reinterpret_cast<const nv_bfloat162*>(&Out2), bias_reg);\n }\n }\n}\n\ntemplate <>\nstruct vec_cast<nv_bfloat16, __nv_fp8_e4m3> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(nv_bfloat16* dst, const __nv_fp8_e4m3* src) {\n if constexpr (vec_size == 1) {\n dst[0] = nv_bfloat16(src[0]);\n } else if constexpr (vec_size == 2) {\n dst[0] = nv_bfloat16(src[0]);\n dst[1] = nv_bfloat16(src[1]);\n } else {\n static_assert(vec_size % 4 == 0, \"vec_size must be a multiple of 4\");\n#pragma unroll\n for (uint32_t i = 0; i < vec_size / 4; ++i) {\n fast_dequant_f8f16x4<__nv_fp8_e4m3, nv_bfloat16>((uint32_t*)&src[i * 4],\n (uint2*)&dst[i * 4]);\n }\n }\n }\n};\n\ntemplate <>\nstruct vec_cast<nv_bfloat16, __nv_fp8_e5m2> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(nv_bfloat16* dst, const __nv_fp8_e5m2* src) {\n if constexpr (vec_size == 1) {\n dst[0] = nv_bfloat16(src[0]);\n } else if constexpr (vec_size == 2) {\n dst[0] = nv_bfloat16(src[0]);\n dst[1] = nv_bfloat16(src[1]);\n } else {\n static_assert(vec_size % 4 == 0, \"vec_size must be a multiple of 4\");\n#pragma unroll\n for (uint32_t i = 0; i < vec_size / 4; ++i) {\n fast_dequant_f8f16x4<__nv_fp8_e5m2, nv_bfloat16>((uint32_t*)&src[i * 4],\n (uint2*)&dst[i * 4]);\n }\n }\n }\n};\n\ntemplate <>\nstruct vec_cast<__nv_fp8_e4m3, half> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(__nv_fp8_e4m3* dst, const half* src) {\n#ifdef FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n if constexpr (vec_size == 1) {\n dst[0] = __nv_fp8_e4m3(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint16_t y;\n uint32_t x = *(uint32_t*)&src[i * 2];\n asm volatile(\"cvt.rn.satfinite.e4m3x2.f16x2 %0, %1;\" : \"=h\"(y) : \"r\"(x));\n *(uint16_t*)&dst[i * 2] = y;\n }\n }\n#else\n#pragma unroll\n for (size_t i = 0; i < vec_size; ++i) {\n dst[i] = __nv_fp8_e4m3(src[i]);\n }\n#endif // FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n }\n};\n\ntemplate <>\nstruct vec_cast<__nv_fp8_e5m2, half> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(__nv_fp8_e5m2* dst, const half* src) {\n#ifdef FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n if constexpr (vec_size == 1) {\n dst[0] = __nv_fp8_e5m2(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint16_t y;\n uint32_t x = *(uint32_t*)&src[i * 2];\n asm volatile(\"cvt.rn.satfinite.e5m2x2.f16x2 %0, %1;\" : \"=h\"(y) : \"r\"(x));\n *(uint16_t*)&dst[i * 2] = y;\n }\n }\n#else\n#pragma unroll\n for (size_t i = 0; i < vec_size; ++i) {\n dst[i] = __nv_fp8_e5m2(src[i]);\n }\n#endif // FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n }\n};\n\ntemplate <>\nstruct vec_cast<half, __nv_fp8_e4m3> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(half* dst, const __nv_fp8_e4m3* src) {\n#ifdef FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n if constexpr (vec_size == 1) {\n dst[0] = half(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint32_t y;\n uint16_t x = *(uint16_t*)&src[i * 2];\n asm volatile(\"cvt.rn.f16x2.e4m3x2 %0, %1;\" : \"=r\"(y) : \"h\"(x));\n *(uint32_t*)&dst[i * 2] = y;\n }\n }\n#else\n if constexpr (vec_size == 1) {\n dst[0] = half(src[0]);\n } else if constexpr (vec_size == 2) {\n dst[0] = half(src[0]);\n dst[1] = half(src[1]);\n } else {\n static_assert(vec_size % 4 == 0, \"vec_size must be a multiple of 4\");\n#pragma unroll\n for (uint32_t i = 0; i < vec_size / 4; ++i) {\n fast_dequant_f8f16x4<__nv_fp8_e4m3, half>((uint32_t*)&src[i * 4], (uint2*)&dst[i * 4]);\n }\n }\n#endif // FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n }\n};\n\ntemplate <>\nstruct vec_cast<half, __nv_fp8_e5m2> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(half* dst, const __nv_fp8_e5m2* src) {\n#ifdef FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n if constexpr (vec_size == 1) {\n dst[0] = half(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint32_t y;\n uint16_t x = *(uint16_t*)&src[i * 2];\n asm volatile(\"cvt.rn.f16x2.e5m2x2 %0, %1;\" : \"=r\"(y) : \"h\"(x));\n *(uint32_t*)&dst[i * 2] = y;\n }\n }\n#else\n if constexpr (vec_size == 1) {\n dst[0] = half(src[0]);\n } else if constexpr (vec_size == 2) {\n dst[0] = half(src[0]);\n dst[1] = half(src[1]);\n } else {\n static_assert(vec_size % 4 == 0, \"vec_size must be a multiple of 4\");\n#pragma unroll\n for (uint32_t i = 0; i < vec_size / 4; ++i) {\n fast_dequant_f8f16x4<__nv_fp8_e5m2, half>((uint32_t*)&src[i * 4], (uint2*)&dst[i * 4]);\n }\n }\n#endif // FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n }\n};\n\n// E2M1 nibble decoding helpers. These are plain integer and 16-bit bit manipulation with no\n// FP4 type in their signatures, so they sit outside the FP4 feature guard below: the tile\n// repack in attention/prefill.cuh names them from a template whose FP4 branch is discarded,\n// not removed, and would otherwise fail to compile in builds without FP4 enabled.\n// `prmt` with the msb of a selector nibble set replicates the sign (msb) of the selected byte\n// across the whole output byte, giving 0x00 or 0xFF. `__byte_perm` discards that bit, so the\n// E2M1 sign spread below has to reach for the PTX instruction directly.\n__device__ __forceinline__ uint32_t prmt_b32(uint32_t a, uint32_t b, uint32_t sel) {\n uint32_t r;\n asm(\"prmt.b32 %0, %1, %2, %3;\" : \"=r\"(r) : \"r\"(a), \"r\"(b), \"r\"(sel));\n return r;\n}\n\n// Spread the four E2M1 sign bits of `packed`'s low/high half into byte msbs.\n//\n// `packed` holds eight fp4 values as eight nibbles; byte j carries value 2j in bits[3:0] and\n// value 2j+1 in bits[7:4], so bit 3 of byte j is an even value's sign and bit 7 is an odd\n// value's sign. Byte j's msb is therefore already the odd sign, and `packed << 4` puts the even\n// sign in the same place. One sign-replicating `prmt` then gathers the four signs in value order\n// as 0x00/0xFF bytes; the caller masks to 0x80 and merges, which `lop3` folds into one\n// instruction. Selector 0xD9C8 covers values 0..3, 0xFBEA covers values 4..7.\n__device__ __forceinline__ uint32_t e2m1_sign_bytes(uint32_t packed, uint32_t sel) {\n return prmt_b32(packed << 4, packed, sel) & 0x80808080u;\n}\n\n// Dequantize eight E2M1 values, held as the eight nibbles of `packed` in value order, into four\n// packed 16-bit pairs. Pure ALU, register-only: the magnitude table is indexed by `prmt`.\n//\n// FP16: all eight E2M1 magnitudes {0,0.5,1,1.5,2,3,4,6} encode with a zero low byte, so the whole\n// table is eight high bytes -- exactly one `prmt` source window -- and the expansion just inserts\n// zero low bytes. BF16 magnitudes have varying low bytes, so two tables are indexed and the\n// {low, high} byte pairs are interleaved instead.\n__device__ __forceinline__ void e2m1x8_to_f16x8(uint32_t packed, uint32_t* d) {\n constexpr uint32_t kHi0 = 0x3E3C3800u; // high bytes of +{0.0, 0.5, 1.0, 1.5}\n constexpr uint32_t kHi1 = 0x46444240u; // high bytes of +{2.0, 3.0, 4.0, 6.0}\n const uint32_t mag = packed & 0x77777777u;\n uint32_t hi_a = __byte_perm(kHi0, kHi1, mag); // magnitudes of values 0..3\n uint32_t hi_b = __byte_perm(kHi0, kHi1, mag >> 16); // magnitudes of values 4..7\n hi_a |= e2m1_sign_bytes(packed, 0xD9C8u);\n hi_b |= e2m1_sign_bytes(packed, 0xFBEAu);\n d[0] = __byte_perm(hi_a, 0u, 0x1404u);\n d[1] = __byte_perm(hi_a, 0u, 0x3424u);\n d[2] = __byte_perm(hi_b, 0u, 0x1404u);\n d[3] = __byte_perm(hi_b, 0u, 0x3424u);\n}\n\n__device__ __forceinline__ void e2m1x8_to_bf16x8(uint32_t packed, uint32_t* d) {\n constexpr uint32_t kHi0 = 0x3F3F3F00u; // high bytes of +{0.0, 0.5, 1.0, 1.5}\n constexpr uint32_t kHi1 = 0x40404040u; // high bytes of +{2.0, 3.0, 4.0, 6.0}\n constexpr uint32_t kLo0 = 0xC0800000u; // low bytes of +{0.0, 0.5, 1.0, 1.5}\n constexpr uint32_t kLo1 = 0xC0804000u; // low bytes of +{2.0, 3.0, 4.0, 6.0}\n const uint32_t mag = packed & 0x77777777u;\n const uint32_t mag_a = mag, mag_b = mag >> 16;\n uint32_t hi_a = __byte_perm(kHi0, kHi1, mag_a);\n uint32_t hi_b = __byte_perm(kHi0, kHi1, mag_b);\n const uint32_t lo_a = __byte_perm(kLo0, kLo1, mag_a);\n const uint32_t lo_b = __byte_perm(kLo0, kLo1, mag_b);\n hi_a |= e2m1_sign_bytes(packed, 0xD9C8u);\n hi_b |= e2m1_sign_bytes(packed, 0xFBEAu);\n d[0] = __byte_perm(lo_a, hi_a, 0x5140u);\n d[1] = __byte_perm(lo_a, hi_a, 0x7362u);\n d[2] = __byte_perm(lo_b, hi_b, 0x5140u);\n d[3] = __byte_perm(lo_b, hi_b, 0x7362u);\n}\n\ntemplate <typename DType16>\n__device__ __forceinline__ void e2m1x8_to_16bx8(uint32_t packed, uint32_t* d) {\n if constexpr (std::is_same_v<DType16, half>) {\n e2m1x8_to_f16x8(packed, d);\n } else {\n e2m1x8_to_bf16x8(packed, d);\n }\n}\n\n#if defined(FLASHINFER_ENABLE_FP4_E2M1) && CUDA_VERSION >= 12080\n\n// Convert __nv_fp4x2_e2m1 (2 fp4 values per byte) to fp16.\n// vec_size counts fp16 output elements; src has stride-2 layout:\n// src[0] holds x0,x1 src[1] is padding\n// src[2] holds x2,x3 src[3] is padding ... etc.\n// Each valid byte encodes 2 fp4 values -> 2 fp16 via cvt.rn.f16x2.e2m1x2.\ntemplate <>\nstruct vec_cast<half, __nv_fp4x2_e2m1> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(half* dst, const __nv_fp4x2_e2m1* src) {\n static_assert(vec_size % 2 == 0, \"vec_size must be even for fp4x2 dequantization\");\n#if (defined __CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint32_t y;\n // Valid fp4x2 bytes are at even positions (stride 2); odd positions are padding.\n uint32_t b = reinterpret_cast<const uint8_t*>(src)[i * 2];\n asm volatile(\n \"{\\n\"\n \".reg .b8 fp4_byte;\\n\"\n \"mov.b32 {fp4_byte, _, _, _}, %1;\\n\"\n \"cvt.rn.f16x2.e2m1x2 %0, fp4_byte;\\n\"\n \"}\"\n : \"=r\"(y)\n : \"r\"(b));\n reinterpret_cast<uint32_t*>(dst)[i] = y;\n }\n#else\n#if defined(__CUDA_ARCH__)\n // Fast path for arch < SM100: pure-ALU table lookup through `prmt`.\n // The FP16 encodings of the eight E2M1 magnitudes {0,0.5,1,1.5,2,3,4,6} all have a zero low\n // byte, so the whole magnitude table fits in the 8 bytes a single `prmt` can index and the\n // conversion stays in registers. The `uint16_t lut[16]` array below instead lands in local\n // memory: one dependent LDL per element, plus a 32-byte stack frame in every kernel that\n // inlines this.\n if constexpr (vec_size % 8 == 0) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n const uint32_t* s = reinterpret_cast<const uint32_t*>(src) + i * 2;\n // Payload bytes sit at stride 2; gather them into eight nibbles (nibble j == value j).\n e2m1x8_to_f16x8(__byte_perm(s[0], s[1], 0x6420u), reinterpret_cast<uint32_t*>(dst) + i * 4);\n }\n return;\n }\n#endif\n // Software LUT fallback for arch < SM100.\n // e2m1 encoding: bit[3]=sign, bit[2:0]=magnitude index in {0,0.5,1,1.5,2,3,4,6}.\n // Each packed byte holds two fp4 values: bits[3:0]=first, bits[7:4]=second.\n constexpr uint16_t lut[16] = {\n 0x0000, // +0.0\n 0x3800, // +0.5\n 0x3C00, // +1.0\n 0x3E00, // +1.5\n 0x4000, // +2.0\n 0x4200, // +3.0\n 0x4400, // +4.0\n 0x4600, // +6.0\n 0x8000, // -0.0\n 0xB800, // -0.5\n 0xBC00, // -1.0\n 0xBE00, // -1.5\n 0xC000, // -2.0\n 0xC200, // -3.0\n 0xC400, // -4.0\n 0xC600, // -6.0\n };\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint8_t b = reinterpret_cast<const uint8_t*>(src)[i * 2];\n reinterpret_cast<uint16_t*>(dst)[i * 2 + 0] = lut[b & 0x0F];\n reinterpret_cast<uint16_t*>(dst)[i * 2 + 1] = lut[(b >> 4) & 0x0F];\n }\n#endif\n }\n};\n\ntemplate <>\nstruct vec_cast<float, __nv_fp4x2_e2m1> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(float* dst, const __nv_fp4x2_e2m1* src) {\n static_assert(vec_size % 2 == 0, \"vec_size must be even for fp4x2 dequantization\");\n#if (defined __CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint32_t fp16x2;\n // Valid fp4x2 bytes are at even positions (stride 2); odd positions are padding.\n uint32_t b = reinterpret_cast<const uint8_t*>(src)[i * 2];\n asm volatile(\n \"{\\n\"\n \".reg .b8 fp4_byte;\\n\"\n \"mov.b32 {fp4_byte, _, _, _}, %1;\\n\"\n \"cvt.rn.f16x2.e2m1x2 %0, fp4_byte;\\n\"\n \"}\"\n : \"=r\"(fp16x2)\n : \"r\"(b));\n __half2 h2 = *reinterpret_cast<__half2*>(&fp16x2);\n reinterpret_cast<float2*>(dst)[i] = __half22float2(h2);\n }\n#else\n constexpr float lut[16] = {\n 0.0f, 0.5f, 1.0f, 1.5f, 2.0f, 3.0f, 4.0f, 6.0f,\n -0.0f, -0.5f, -1.0f, -1.5f, -2.0f, -3.0f, -4.0f, -6.0f,\n };\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint8_t b = reinterpret_cast<const uint8_t*>(src)[i * 2];\n dst[i * 2 + 0] = lut[b & 0x0F];\n dst[i * 2 + 1] = lut[(b >> 4) & 0x0F];\n }\n#endif\n }\n};\n\ntemplate <>\nstruct vec_cast<nv_bfloat16, __nv_fp4x2_e2m1> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(nv_bfloat16* dst, const __nv_fp4x2_e2m1* src) {\n static_assert(vec_size % 2 == 0, \"vec_size must be even for fp4x2 dequantization\");\n#if (defined __CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint32_t y;\n // Valid fp4x2 bytes are at even positions (stride 2); odd positions are padding.\n uint32_t b = reinterpret_cast<const uint8_t*>(src)[i * 2];\n#if (defined __CUDACC_VER_MAJOR__) && (defined __CUDACC_VER_MINOR__) && \\\n ((__CUDACC_VER_MAJOR__ > 13) || ((__CUDACC_VER_MAJOR__ == 13) && (__CUDACC_VER_MINOR__ >= 2)))\n // cvt.rn.bf16x2.e2m1x2 requires CUDA Toolkit >= 13.2\n asm volatile(\n \"{\\n\"\n \".reg .b8 fp4_byte;\\n\"\n \"mov.b32 {fp4_byte, _, _, _}, %1;\\n\"\n \"cvt.rn.bf16x2.e2m1x2 %0, fp4_byte;\\n\"\n \"}\"\n : \"=r\"(y)\n : \"r\"(b));\n#else\n // Fallback: convert e2m1 -> fp16 -> bf16 when cvt.rn.bf16x2.e2m1x2 is unavailable\n uint32_t fp16x2;\n asm volatile(\n \"{\\n\"\n \".reg .b8 fp4_byte;\\n\"\n \"mov.b32 {fp4_byte, _, _, _}, %1;\\n\"\n \"cvt.rn.f16x2.e2m1x2 %0, fp4_byte;\\n\"\n \"}\"\n : \"=r\"(fp16x2)\n : \"r\"(b));\n __half2 h2 = reinterpret_cast<__half2&>(fp16x2);\n __nv_bfloat162 bf16x2 = __float22bfloat162_rn(__half22float2(h2));\n y = reinterpret_cast<uint32_t&>(bf16x2);\n#endif\n reinterpret_cast<uint32_t*>(dst)[i] = y;\n }\n#else\n#if defined(__CUDA_ARCH__)\n // Fast path for arch < SM100: pure-ALU table lookup through `prmt`. Unlike FP16, the BF16\n // encodings of the E2M1 magnitudes have a varying low byte, so two 8-byte tables are indexed\n // and then interleaved. Still register-only; see the FP16 specialization for why the\n // `uint16_t lut[16]` array below is expensive.\n if constexpr (vec_size % 8 == 0) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n const uint32_t* s = reinterpret_cast<const uint32_t*>(src) + i * 2;\n e2m1x8_to_bf16x8(__byte_perm(s[0], s[1], 0x6420u),\n reinterpret_cast<uint32_t*>(dst) + i * 4);\n }\n return;\n }\n#endif\n // Software LUT fallback for arch < SM100.\n // e2m1 encoding: bit[3]=sign, bit[2:0]=magnitude index in {0,0.5,1,1.5,2,3,4,6}.\n // Each packed byte holds two fp4 values: bits[3:0]=first, bits[7:4]=second.\n constexpr uint16_t lut[16] = {\n 0x0000, // +0.0\n 0x3F00, // +0.5\n 0x3F80, // +1.0\n 0x3FC0, // +1.5\n 0x4000, // +2.0\n 0x4040, // +3.0\n 0x4080, // +4.0\n 0x40C0, // +6.0\n 0x8000, // -0.0\n 0xBF00, // -0.5\n 0xBF80, // -1.0\n 0xBFC0, // -1.5\n 0xC000, // -2.0\n 0xC040, // -3.0\n 0xC080, // -4.0\n 0xC0C0, // -6.0\n };\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint8_t b = reinterpret_cast<const uint8_t*>(src)[i * 2];\n reinterpret_cast<uint16_t*>(dst)[i * 2 + 0] = lut[b & 0x0F];\n reinterpret_cast<uint16_t*>(dst)[i * 2 + 1] = lut[(b >> 4) & 0x0F];\n }\n#endif\n }\n};\n\n#endif // FLASHINFER_ENABLE_FP4_E2M1 && CUDA_VERSION >= 12080\n\ntemplate <>\nstruct vec_cast<float, nv_bfloat16> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(float* dst, const nv_bfloat16* src) {\n if constexpr (vec_size == 1) {\n dst[0] = (float)src[0];\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n ((float2*)dst)[i] = __bfloat1622float2(((nv_bfloat162*)src)[i]);\n }\n }\n }\n};\n\ntemplate <>\nstruct vec_cast<nv_bfloat16, float> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(nv_bfloat16* dst, const float* src) {\n if constexpr (vec_size == 1) {\n dst[0] = nv_bfloat16(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n ((nv_bfloat162*)dst)[i] = __float22bfloat162_rn(((float2*)src)[i]);\n }\n }\n }\n};\n\ntemplate <typename float_t, size_t vec_size>\nstruct vec_t {\n FLASHINFER_INLINE float_t& operator[](size_t i);\n FLASHINFER_INLINE const float_t& operator[](size_t i) const;\n FLASHINFER_INLINE void fill(float_t val);\n FLASHINFER_INLINE void load(const float_t* ptr);\n FLASHINFER_INLINE void store(float_t* ptr) const;\n FLASHINFER_INLINE void load_global_acquire(float* addr);\n FLASHINFER_INLINE void store_global_release(float* addr) const;\n FLASHINFER_INLINE void load_global_volatile(float* addr);\n FLASHINFER_INLINE void store_global_volatile(float* addr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src);\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr);\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const;\n FLASHINFER_INLINE static void memcpy(float_t* dst, const float_t* src);\n FLASHINFER_INLINE float_t* ptr();\n};\n\ntemplate <typename src_float_t, typename tgt_float_t, size_t vec_size>\nFLASHINFER_INLINE void cast_from_impl(vec_t<tgt_float_t, vec_size>& dst,\n const vec_t<src_float_t, vec_size>& src) {\n vec_cast<tgt_float_t, src_float_t>::cast<vec_size>(\n dst.ptr(), const_cast<vec_t<src_float_t, vec_size>*>(&src)->ptr());\n}\n\ntemplate <typename src_float_t, typename tgt_float_t, size_t vec_size>\nFLASHINFER_INLINE void cast_load_impl(vec_t<tgt_float_t, vec_size>& dst,\n const src_float_t* src_ptr) {\n if constexpr (std::is_same_v<src_float_t, tgt_float_t>) {\n dst.load(src_ptr);\n } else {\n vec_t<src_float_t, vec_size> tmp;\n tmp.load(src_ptr);\n dst.cast_from(tmp);\n }\n}\n\ntemplate <typename src_float_t, typename tgt_float_t, size_t vec_size>\nFLASHINFER_INLINE void cast_store_impl(tgt_float_t* dst_ptr,\n const vec_t<src_float_t, vec_size>& src) {\n if constexpr (std::is_same_v<src_float_t, tgt_float_t>) {\n src.store(dst_ptr);\n } else {\n vec_t<tgt_float_t, vec_size> tmp;\n tmp.cast_from(src);\n tmp.store(dst_ptr);\n }\n}\n\n/******************* vec_t<__nv_fp8_e4m3> *******************/\n\n// __nv_fp8_e4m3 x 1\ntemplate <>\nstruct vec_t<__nv_fp8_e4m3, 1> {\n __nv_fp8_e4m3 data;\n\n FLASHINFER_INLINE __nv_fp8_e4m3& operator[](size_t i) { return ((__nv_fp8_e4m3*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e4m3& operator[](size_t i) const {\n return ((const __nv_fp8_e4m3*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e4m3* ptr() { return reinterpret_cast<__nv_fp8_e4m3*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e4m3 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e4m3* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e4m3* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 1>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e4m3* dst, const __nv_fp8_e4m3* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 1>::fill(__nv_fp8_e4m3 val) { data = val; }\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 1>::load(const __nv_fp8_e4m3* ptr) { data = *ptr; }\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 1>::store(__nv_fp8_e4m3* ptr) const { *ptr = data; }\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 1>::memcpy(__nv_fp8_e4m3* dst,\n const __nv_fp8_e4m3* src) {\n *dst = *src;\n}\n\n// __nv_fp8_e4m3 x 2\ntemplate <>\nstruct vec_t<__nv_fp8_e4m3, 2> {\n __nv_fp8x2_e4m3 data;\n\n FLASHINFER_INLINE __nv_fp8_e4m3& operator[](size_t i) { return ((__nv_fp8_e4m3*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e4m3& operator[](size_t i) const {\n return ((const __nv_fp8_e4m3*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e4m3* ptr() { return reinterpret_cast<__nv_fp8_e4m3*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e4m3 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e4m3* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e4m3* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 2>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e4m3* dst, const __nv_fp8_e4m3* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 2>::fill(__nv_fp8_e4m3 val) {\n data.__x = (__nv_fp8x2_storage_t(val.__x) << 8) | __nv_fp8x2_storage_t(val.__x);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 2>::load(const __nv_fp8_e4m3* ptr) {\n data = *((__nv_fp8x2_e4m3*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 2>::store(__nv_fp8_e4m3* ptr) const {\n *((__nv_fp8x2_e4m3*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 2>::memcpy(__nv_fp8_e4m3* dst,\n const __nv_fp8_e4m3* src) {\n *((__nv_fp8x2_e4m3*)dst) = *((__nv_fp8x2_e4m3*)src);\n}\n\n// __nv_fp8_e4m3 x 4\n\ntemplate <>\nstruct vec_t<__nv_fp8_e4m3, 4> {\n __nv_fp8x4_e4m3 data;\n\n FLASHINFER_INLINE __nv_fp8_e4m3& operator[](size_t i) { return ((__nv_fp8_e4m3*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e4m3& operator[](size_t i) const {\n return ((const __nv_fp8_e4m3*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e4m3* ptr() { return reinterpret_cast<__nv_fp8_e4m3*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e4m3 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e4m3* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e4m3* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 4>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e4m3* dst, const __nv_fp8_e4m3* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 4>::fill(__nv_fp8_e4m3 val) {\n data.__x = (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 4>::load(const __nv_fp8_e4m3* ptr) {\n data = *((__nv_fp8x4_e4m3*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 4>::store(__nv_fp8_e4m3* ptr) const {\n *((__nv_fp8x4_e4m3*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 4>::memcpy(__nv_fp8_e4m3* dst,\n const __nv_fp8_e4m3* src) {\n *((__nv_fp8x4_e4m3*)dst) = *((__nv_fp8x4_e4m3*)src);\n}\n\n// __nv_fp8_e4m3 x 8\n\ntemplate <>\nstruct vec_t<__nv_fp8_e4m3, 8> {\n uint2 data;\n\n FLASHINFER_INLINE __nv_fp8_e4m3& operator[](size_t i) { return ((__nv_fp8_e4m3*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e4m3& operator[](size_t i) const {\n return ((const __nv_fp8_e4m3*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e4m3* ptr() { return reinterpret_cast<__nv_fp8_e4m3*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e4m3 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e4m3* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e4m3* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 8>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e4m3* dst, const __nv_fp8_e4m3* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 8>::fill(__nv_fp8_e4m3 val) {\n ((__nv_fp8x4_e4m3*)(&data.x))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e4m3*)(&data.y))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 8>::load(const __nv_fp8_e4m3* ptr) {\n data = *((uint2*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 8>::store(__nv_fp8_e4m3* ptr) const {\n *((uint2*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 8>::memcpy(__nv_fp8_e4m3* dst,\n const __nv_fp8_e4m3* src) {\n *((uint2*)dst) = *((uint2*)src);\n}\n\n// __nv_fp8_e4m3 x 16 or more\ntemplate <size_t vec_size>\nstruct vec_t<__nv_fp8_e4m3, vec_size> {\n static_assert(vec_size % 16 == 0, \"Invalid vector size\");\n int4 data[vec_size / 16];\n\n FLASHINFER_INLINE __nv_fp8_e4m3& operator[](size_t i) { return ((__nv_fp8_e4m3*)data)[i]; }\n FLASHINFER_INLINE const __nv_fp8_e4m3& operator[](size_t i) const {\n return ((const __nv_fp8_e4m3*)data)[i];\n }\n FLASHINFER_INLINE __nv_fp8_e4m3* ptr() { return reinterpret_cast<__nv_fp8_e4m3*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e4m3 val) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((__nv_fp8x4_e4m3*)(&(data[i].x)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e4m3*)(&(data[i].y)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e4m3*)(&(data[i].z)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e4m3*)(&(data[i].w)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n }\n }\n FLASHINFER_INLINE void load(const __nv_fp8_e4m3* ptr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i] = ((int4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(__nv_fp8_e4m3* ptr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((int4*)ptr)[i] = data[i];\n }\n }\n FLASHINFER_INLINE void load_global_acquire(__nv_fp8_e4m3* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n *((int4*)(data + i)) = ld_global_acquire((int4*)(addr + i * 16));\n }\n }\n FLASHINFER_INLINE void store_global_release(__nv_fp8_e4m3* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n st_global_release(data[i], (int4*)(addr + i * 16));\n }\n }\n FLASHINFER_INLINE void load_global_volatile(__nv_fp8_e4m3* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i] = ld_global_volatile((int4*)(addr + i * 16));\n }\n }\n FLASHINFER_INLINE void store_global_volatile(__nv_fp8_e4m3* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n st_global_volatile(data[i], (int4*)(addr + i * 16));\n }\n }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e4m3* dst, const __nv_fp8_e4m3* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((int4*)dst)[i] = ((int4*)src)[i];\n }\n }\n};\n\n/******************* vec_t<__nv_fp8_e5m2> *******************/\n\n// __nv_fp8_e5m2 x 1\ntemplate <>\nstruct vec_t<__nv_fp8_e5m2, 1> {\n __nv_fp8_e5m2 data;\n\n FLASHINFER_INLINE __nv_fp8_e5m2& operator[](size_t i) { return ((__nv_fp8_e5m2*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e5m2& operator[](size_t i) const {\n return ((const __nv_fp8_e5m2*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e5m2* ptr() { return reinterpret_cast<__nv_fp8_e5m2*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e5m2 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e5m2* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e5m2* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 1>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e5m2* dst, const __nv_fp8_e5m2* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 1>::fill(__nv_fp8_e5m2 val) { data = val; }\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 1>::load(const __nv_fp8_e5m2* ptr) { data = *ptr; }\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 1>::store(__nv_fp8_e5m2* ptr) const { *ptr = data; }\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 1>::memcpy(__nv_fp8_e5m2* dst,\n const __nv_fp8_e5m2* src) {\n *dst = *src;\n}\n\n// __nv_fp8_e5m2 x 2\ntemplate <>\nstruct vec_t<__nv_fp8_e5m2, 2> {\n __nv_fp8x2_e5m2 data;\n\n FLASHINFER_INLINE __nv_fp8_e5m2& operator[](size_t i) { return ((__nv_fp8_e5m2*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e5m2& operator[](size_t i) const {\n return ((const __nv_fp8_e5m2*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e5m2* ptr() { return reinterpret_cast<__nv_fp8_e5m2*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e5m2 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e5m2* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e5m2* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 2>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e5m2* dst, const __nv_fp8_e5m2* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 2>::fill(__nv_fp8_e5m2 val) {\n data.__x = (__nv_fp8x2_storage_t(val.__x) << 8) | __nv_fp8x2_storage_t(val.__x);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 2>::load(const __nv_fp8_e5m2* ptr) {\n data = *((__nv_fp8x2_e5m2*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 2>::store(__nv_fp8_e5m2* ptr) const {\n *((__nv_fp8x2_e5m2*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 2>::memcpy(__nv_fp8_e5m2* dst,\n const __nv_fp8_e5m2* src) {\n *((__nv_fp8x2_e5m2*)dst) = *((__nv_fp8x2_e5m2*)src);\n}\n\n// __nv_fp8_e5m2 x 4\n\ntemplate <>\nstruct vec_t<__nv_fp8_e5m2, 4> {\n __nv_fp8x4_e5m2 data;\n\n FLASHINFER_INLINE __nv_fp8_e5m2& operator[](size_t i) { return ((__nv_fp8_e5m2*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e5m2& operator[](size_t i) const {\n return ((const __nv_fp8_e5m2*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e5m2* ptr() { return reinterpret_cast<__nv_fp8_e5m2*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e5m2 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e5m2* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e5m2* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 4>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e5m2* dst, const __nv_fp8_e5m2* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 4>::fill(__nv_fp8_e5m2 val) {\n data.__x = (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 4>::load(const __nv_fp8_e5m2* ptr) {\n data = *((__nv_fp8x4_e5m2*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 4>::store(__nv_fp8_e5m2* ptr) const {\n *((__nv_fp8x4_e5m2*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 4>::memcpy(__nv_fp8_e5m2* dst,\n const __nv_fp8_e5m2* src) {\n *((__nv_fp8x4_e5m2*)dst) = *((__nv_fp8x4_e5m2*)src);\n}\n\n// __nv_fp8_e5m2 x 8\n\ntemplate <>\nstruct vec_t<__nv_fp8_e5m2, 8> {\n uint2 data;\n\n FLASHINFER_INLINE __nv_fp8_e5m2& operator[](size_t i) { return ((__nv_fp8_e5m2*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e5m2& operator[](size_t i) const {\n return ((const __nv_fp8_e5m2*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e5m2* ptr() { return reinterpret_cast<__nv_fp8_e5m2*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e5m2 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e5m2* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e5m2* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 8>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e5m2* dst, const __nv_fp8_e5m2* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 8>::fill(__nv_fp8_e5m2 val) {\n ((__nv_fp8x4_e5m2*)(&data.x))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e5m2*)(&data.y))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 8>::load(const __nv_fp8_e5m2* ptr) {\n data = *((uint2*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 8>::store(__nv_fp8_e5m2* ptr) const {\n *((uint2*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 8>::memcpy(__nv_fp8_e5m2* dst,\n const __nv_fp8_e5m2* src) {\n *((uint2*)dst) = *((uint2*)src);\n}\n\n// __nv_fp8_e5m2 x 16 or more\n\ntemplate <size_t vec_size>\nstruct vec_t<__nv_fp8_e5m2, vec_size> {\n static_assert(vec_size % 16 == 0, \"Invalid vector size\");\n int4 data[vec_size / 16];\n\n FLASHINFER_INLINE __nv_fp8_e5m2& operator[](size_t i) { return ((__nv_fp8_e5m2*)data)[i]; }\n FLASHINFER_INLINE const __nv_fp8_e5m2& operator[](size_t i) const {\n return ((const __nv_fp8_e5m2*)data)[i];\n }\n FLASHINFER_INLINE __nv_fp8_e5m2* ptr() { return reinterpret_cast<__nv_fp8_e5m2*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e5m2 val) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((__nv_fp8x4_e5m2*)(&(data[i].x)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e5m2*)(&(data[i].y)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e5m2*)(&(data[i].z)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e5m2*)(&(data[i].w)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n }\n }\n FLASHINFER_INLINE void load(const __nv_fp8_e5m2* ptr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i] = ((int4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(__nv_fp8_e5m2* ptr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((int4*)ptr)[i] = data[i];\n }\n }\n FLASHINFER_INLINE void store_global_release(__nv_fp8_e5m2* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n st_global_release(data[i], (int4*)(addr + i * 16));\n }\n }\n FLASHINFER_INLINE void load_global_acquire(__nv_fp8_e5m2* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i] = ld_global_acquire((int4*)(addr + i * 16));\n }\n }\n FLASHINFER_INLINE void store_global_volatile(__nv_fp8_e5m2* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n st_global_volatile(data[i], (int4*)(addr + i * 16));\n }\n }\n FLASHINFER_INLINE void load_global_volatile(__nv_fp8_e5m2* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i] = ld_global_volatile((int4*)(addr + i * 16));\n }\n }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e5m2* dst, const __nv_fp8_e5m2* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((int4*)dst)[i] = ((int4*)src)[i];\n }\n }\n};\n\n#if defined(FLASHINFER_ENABLE_FP4_E2M1) && CUDA_VERSION >= 12080\n/******************* vec_t<__nv_fp4x2_e2m1> *******************/\n\n// __nv_fp4x2_e2m1 is used as a one-byte packed container for FP4 KV-cache data.\n// The current FA2 NVFP4 path stores valid packed bytes at even positions and padding at odd\n// positions, so vec_size still counts logical elements in the surrounding kernels.\ntemplate <size_t vec_size>\nstruct vec_t<__nv_fp4x2_e2m1, vec_size> {\n static_assert(vec_size % 16 == 0, \"Invalid vector size\");\n int4 data[vec_size / 16];\n\n FLASHINFER_INLINE __nv_fp4x2_e2m1& operator[](size_t i) { return ((__nv_fp4x2_e2m1*)data)[i]; }\n FLASHINFER_INLINE const __nv_fp4x2_e2m1& operator[](size_t i) const {\n return ((const __nv_fp4x2_e2m1*)data)[i];\n }\n FLASHINFER_INLINE __nv_fp4x2_e2m1* ptr() { return reinterpret_cast<__nv_fp4x2_e2m1*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp4x2_e2m1 val) {\n uint32_t val8 = __nv_fp4x2_storage_t(val.__x);\n uint32_t val16 = (val8 << 8) | val8;\n uint32_t val32 = (val16 << 16) | val16;\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i].x = val32;\n data[i].y = val32;\n data[i].z = val32;\n data[i].w = val32;\n }\n }\n FLASHINFER_INLINE void load(const __nv_fp4x2_e2m1* ptr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i] = ((int4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(__nv_fp4x2_e2m1* ptr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((int4*)ptr)[i] = data[i];\n }\n }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(__nv_fp4x2_e2m1* dst, const __nv_fp4x2_e2m1* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((int4*)dst)[i] = ((int4*)src)[i];\n }\n }\n};\n\n/******************* vec_t<__nv_fp4_e2m1> *******************/\n\n// __nv_fp4_e2m1 x 2\ntemplate <>\nstruct vec_t<__nv_fp4_e2m1, 2> {\n uint8_t data;\n // index access is not supported for sub-byte data type\n FLASHINFER_INLINE __nv_fp4_e2m1* ptr() { return reinterpret_cast<__nv_fp4_e2m1*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp4_e2m1 val) {\n data = (__nv_fp4x2_storage_t(val.__x) << 4) | __nv_fp4x2_storage_t(val.__x);\n }\n FLASHINFER_INLINE void load(const __nv_fp4_e2m1* ptr) { data = *((uint8_t*)ptr); }\n FLASHINFER_INLINE void store(__nv_fp4_e2m1* ptr) const { *((uint8_t*)ptr) = data; }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 2>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(__nv_fp4_e2m1* dst, const __nv_fp4_e2m1* src) {\n *((uint8_t*)dst) = *((uint8_t*)src);\n }\n};\n\n// __nv_fp4_e2m1 x 4\ntemplate <>\nstruct vec_t<__nv_fp4_e2m1, 4> {\n uint16_t data;\n\n FLASHINFER_INLINE __nv_fp4_e2m1* ptr() { return reinterpret_cast<__nv_fp4_e2m1*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp4_e2m1 val) {\n __nv_fp4x2_storage_t val8 =\n (__nv_fp4x2_storage_t(val.__x) << 4) | __nv_fp4x2_storage_t(val.__x);\n data = (uint16_t(val8) << 8) | uint16_t(val8);\n }\n FLASHINFER_INLINE void load(const __nv_fp4_e2m1* ptr) { data = *((uint16_t*)ptr); }\n FLASHINFER_INLINE void store(__nv_fp4_e2m1* ptr) const { *((uint16_t*)ptr) = data; }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 4>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(__nv_fp4_e2m1* dst, const __nv_fp4_e2m1* src) {\n *((uint16_t*)dst) = *((uint16_t*)src);\n }\n};\n\n// __nv_fp4_e2m1 x 8\ntemplate <>\nstruct vec_t<__nv_fp4_e2m1, 8> {\n uint32_t data;\n\n FLASHINFER_INLINE __nv_fp4_e2m1* ptr() { return reinterpret_cast<__nv_fp4_e2m1*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp4_e2m1 val) {\n __nv_fp4x2_storage_t val8 =\n (__nv_fp4x2_storage_t(val.__x) << 4) | __nv_fp4x2_storage_t(val.__x);\n uint16_t val16 = (uint16_t(val8) << 8) | uint16_t(val8);\n data = (uint32_t(val16) << 16) | uint32_t(val16);\n }\n FLASHINFER_INLINE void load(const __nv_fp4_e2m1* ptr) { data = *((uint32_t*)ptr); }\n FLASHINFER_INLINE void store(__nv_fp4_e2m1* ptr) const { *((uint32_t*)ptr) = data; }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 8>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(__nv_fp4_e2m1* dst, const __nv_fp4_e2m1* src) {\n *((uint32_t*)dst) = *((uint32_t*)src);\n }\n};\n\ntemplate <>\nstruct vec_t<__nv_fp4_e2m1, 16> {\n uint2 data;\n FLASHINFER_INLINE __nv_fp4_e2m1* ptr() { return reinterpret_cast<__nv_fp4_e2m1*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp4_e2m1 val) {\n __nv_fp4x2_storage_t val8 =\n (__nv_fp4x2_storage_t(val.__x) << 4) | __nv_fp4x2_storage_t(val.__x);\n uint16_t val16 = (uint16_t(val8) << 8) | uint16_t(val8);\n uint32_t val32 = (uint32_t(val16) << 16) | uint32_t(val16);\n data.x = val32;\n data.y = val32;\n }\n FLASHINFER_INLINE void load(const __nv_fp4_e2m1* ptr) { data = *((uint2*)ptr); }\n FLASHINFER_INLINE void store(__nv_fp4_e2m1* ptr) const { *((uint2*)ptr) = data; }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 16>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(__nv_fp4_e2m1* dst, const __nv_fp4_e2m1* src) {\n *((uint2*)dst) = *((uint2*)src);\n }\n};\n\n// __nv_fp4_e2m1 x 32 or more\ntemplate <size_t vec_size>\nstruct vec_t<__nv_fp4_e2m1, vec_size> {\n static_assert(vec_size % 32 == 0, \"Invalid vector size\");\n int4 data[vec_size / 32];\n\n FLASHINFER_INLINE __nv_fp4_e2m1* ptr() { return reinterpret_cast<__nv_fp4_e2m1*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp4_e2m1 val) {\n __nv_fp4x2_storage_t val8 =\n (__nv_fp4x2_storage_t(val.__x) << 4) | __nv_fp4x2_storage_t(val.__x);\n uint16_t val16 = (uint16_t(val8) << 8) | uint16_t(val8);\n uint32_t val32 = (uint32_t(val16) << 16) | uint32_t(val16);\n#pragma unroll\n for (size_t i = 0; i < vec_size / 32; ++i) {\n data[i].x = val32;\n data[i].y = val32;\n data[i].z = val32;\n data[i].w = val32;\n }\n }\n FLASHINFER_INLINE void load(const __nv_fp4_e2m1* ptr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 32; ++i) {\n data[i] = ((int4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(__nv_fp4_e2m1* ptr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 32; ++i) {\n ((int4*)ptr)[i] = data[i];\n }\n }\n FLASHINFER_INLINE void store_global_release(__nv_fp4_e2m1* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 32; ++i) {\n st_global_release(*(int4*)&data[i], (int4*)(addr + i * 16));\n }\n }\n FLASHINFER_INLINE void load_global_acquire(__nv_fp4_e2m1* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 32; ++i) {\n *(int4*)&data[i] = ld_global_acquire((int4*)(addr + i * 16));\n }\n }\n FLASHINFER_INLINE void store_global_volatile(__nv_fp4_e2m1* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 32; ++i) {\n st_global_volatile(*(int4*)&data[i], (int4*)(addr + i * 16));\n }\n }\n FLASHINFER_INLINE void load_global_volatile(__nv_fp4_e2m1* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 32; ++i) {\n *(int4*)&data[i] = ld_global_volatile((int4*)(addr + i * 16));\n }\n }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(__nv_fp4_e2m1* dst, const __nv_fp4_e2m1* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 32; ++i) {\n ((int4*)dst)[i] = ((int4*)src)[i];\n }\n }\n};\n\n#endif // FLASHINFER_ENABLE_FP4_E2M1 && CUDA_VERSION >= 12080\n\n/******************* vec_t<half> *******************/\n\n// half x 1\ntemplate <>\nstruct vec_t<half, 1> {\n half data;\n\n FLASHINFER_INLINE half& operator[](size_t i) { return ((half*)(&data))[i]; }\n FLASHINFER_INLINE const half& operator[](size_t i) const { return ((const half*)(&data))[i]; }\n FLASHINFER_INLINE half* ptr() { return reinterpret_cast<half*>(&data); }\n FLASHINFER_INLINE void fill(half val);\n FLASHINFER_INLINE void load(const half* ptr);\n FLASHINFER_INLINE void store(half* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 1>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(half* dst, const half* src);\n};\n\nFLASHINFER_INLINE void vec_t<half, 1>::fill(half val) { data = val; }\n\nFLASHINFER_INLINE void vec_t<half, 1>::load(const half* ptr) { data = *ptr; }\n\nFLASHINFER_INLINE void vec_t<half, 1>::store(half* ptr) const { *ptr = data; }\n\nFLASHINFER_INLINE void vec_t<half, 1>::memcpy(half* dst, const half* src) { *dst = *src; }\n\n// half x 2\ntemplate <>\nstruct vec_t<half, 2> {\n half2 data;\n\n FLASHINFER_INLINE half& operator[](size_t i) { return ((half*)(&data))[i]; }\n FLASHINFER_INLINE const half& operator[](size_t i) const { return ((const half*)(&data))[i]; }\n FLASHINFER_INLINE half* ptr() { return reinterpret_cast<half*>(&data); }\n FLASHINFER_INLINE void fill(half val);\n FLASHINFER_INLINE void load(const half* ptr);\n FLASHINFER_INLINE void store(half* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 2>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(half* dst, const half* src);\n};\n\nFLASHINFER_INLINE void vec_t<half, 2>::fill(half val) { data = make_half2(val, val); }\n\nFLASHINFER_INLINE void vec_t<half, 2>::load(const half* ptr) { data = *((half2*)ptr); }\n\nFLASHINFER_INLINE void vec_t<half, 2>::store(half* ptr) const { *((half2*)ptr) = data; }\n\nFLASHINFER_INLINE void vec_t<half, 2>::memcpy(half* dst, const half* src) {\n *((half2*)dst) = *((half2*)src);\n}\n\n// half x 4\n\ntemplate <>\nstruct vec_t<half, 4> {\n uint2 data;\n\n FLASHINFER_INLINE half& operator[](size_t i) { return ((half*)(&data))[i]; }\n FLASHINFER_INLINE const half& operator[](size_t i) const { return ((const half*)(&data))[i]; }\n FLASHINFER_INLINE half* ptr() { return reinterpret_cast<half*>(&data); }\n FLASHINFER_INLINE void fill(half val);\n FLASHINFER_INLINE void load(const half* ptr);\n FLASHINFER_INLINE void store(half* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 4>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(half* dst, const half* src);\n};\n\nFLASHINFER_INLINE void vec_t<half, 4>::fill(half val) {\n *(half2*)(&data.x) = make_half2(val, val);\n *(half2*)(&data.y) = make_half2(val, val);\n}\n\nFLASHINFER_INLINE void vec_t<half, 4>::load(const half* ptr) { data = *((uint2*)ptr); }\n\nFLASHINFER_INLINE void vec_t<half, 4>::store(half* ptr) const { *((uint2*)ptr) = data; }\n\nFLASHINFER_INLINE void vec_t<half, 4>::memcpy(half* dst, const half* src) {\n *((uint2*)dst) = *((uint2*)src);\n}\n\n// half x 8 or more\n\ntemplate <size_t vec_size>\nstruct vec_t<half, vec_size> {\n static_assert(vec_size % 8 == 0, \"Invalid vector size\");\n int4 data[vec_size / 8];\n FLASHINFER_INLINE half& operator[](size_t i) { return ((half*)data)[i]; }\n FLASHINFER_INLINE const half& operator[](size_t i) const { return ((const half*)data)[i]; }\n FLASHINFER_INLINE half* ptr() { return reinterpret_cast<half*>(&data); }\n FLASHINFER_INLINE void fill(half val) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n *(half2*)(&(data[i].x)) = make_half2(val, val);\n *(half2*)(&(data[i].y)) = make_half2(val, val);\n *(half2*)(&(data[i].z)) = make_half2(val, val);\n *(half2*)(&(data[i].w)) = make_half2(val, val);\n }\n }\n FLASHINFER_INLINE void load(const half* ptr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n data[i] = ((int4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(half* ptr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n ((int4*)ptr)[i] = data[i];\n }\n }\n FLASHINFER_INLINE void load_global_acquire(half* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n data[i] = ld_global_acquire((int4*)(addr + i * 8));\n }\n }\n FLASHINFER_INLINE void store_global_release(half* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n st_global_release(data[i], (int4*)(addr + i * 8));\n }\n }\n FLASHINFER_INLINE void store_global_volatile(half* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n st_global_volatile(data[i], (int4*)(addr + i * 8));\n }\n }\n FLASHINFER_INLINE void load_global_volatile(half* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n data[i] = ld_global_volatile((int4*)(addr + i * 8));\n }\n }\n\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(half* dst, const half* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n ((int4*)dst)[i] = ((int4*)src)[i];\n }\n }\n};\n\n/******************* vec_t<nv_bfloat16> *******************/\n\n// nv_bfloat16 x 1\ntemplate <>\nstruct vec_t<nv_bfloat16, 1> {\n nv_bfloat16 data;\n FLASHINFER_INLINE nv_bfloat16& operator[](size_t i) { return ((nv_bfloat16*)(&data))[i]; }\n FLASHINFER_INLINE const nv_bfloat16& operator[](size_t i) const {\n return ((const nv_bfloat16*)(&data))[i];\n }\n FLASHINFER_INLINE nv_bfloat16* ptr() { return reinterpret_cast<nv_bfloat16*>(&data); }\n FLASHINFER_INLINE void fill(nv_bfloat16 val);\n FLASHINFER_INLINE void load(const nv_bfloat16* ptr);\n FLASHINFER_INLINE void store(nv_bfloat16* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 1>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(nv_bfloat16* dst, const nv_bfloat16* src);\n};\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 1>::fill(nv_bfloat16 val) { data = val; }\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 1>::load(const nv_bfloat16* ptr) { data = *ptr; }\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 1>::store(nv_bfloat16* ptr) const { *ptr = data; }\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 1>::memcpy(nv_bfloat16* dst, const nv_bfloat16* src) {\n *dst = *src;\n}\n\n// nv_bfloat16 x 2\ntemplate <>\nstruct vec_t<nv_bfloat16, 2> {\n nv_bfloat162 data;\n\n FLASHINFER_INLINE nv_bfloat16& operator[](size_t i) { return ((nv_bfloat16*)(&data))[i]; }\n FLASHINFER_INLINE const nv_bfloat16& operator[](size_t i) const {\n return ((const nv_bfloat16*)(&data))[i];\n }\n FLASHINFER_INLINE nv_bfloat16* ptr() { return reinterpret_cast<nv_bfloat16*>(&data); }\n FLASHINFER_INLINE void fill(nv_bfloat16 val);\n FLASHINFER_INLINE void load(const nv_bfloat16* ptr);\n FLASHINFER_INLINE void store(nv_bfloat16* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 2>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(nv_bfloat16* dst, const nv_bfloat16* src);\n};\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 2>::fill(nv_bfloat16 val) {\n data = make_bfloat162(val, val);\n}\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 2>::load(const nv_bfloat16* ptr) {\n data = *((nv_bfloat162*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 2>::store(nv_bfloat16* ptr) const {\n *((nv_bfloat162*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 2>::memcpy(nv_bfloat16* dst, const nv_bfloat16* src) {\n *((nv_bfloat162*)dst) = *((nv_bfloat162*)src);\n}\n\n// nv_bfloat16 x 4\n\ntemplate <>\nstruct vec_t<nv_bfloat16, 4> {\n uint2 data;\n\n FLASHINFER_INLINE nv_bfloat16& operator[](size_t i) { return ((nv_bfloat16*)(&data))[i]; }\n FLASHINFER_INLINE const nv_bfloat16& operator[](size_t i) const {\n return ((const nv_bfloat16*)(&data))[i];\n }\n FLASHINFER_INLINE nv_bfloat16* ptr() { return reinterpret_cast<nv_bfloat16*>(&data); }\n FLASHINFER_INLINE void fill(nv_bfloat16 val);\n FLASHINFER_INLINE void load(const nv_bfloat16* ptr);\n FLASHINFER_INLINE void store(nv_bfloat16* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 4>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(nv_bfloat16* dst, const nv_bfloat16* src);\n};\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 4>::fill(nv_bfloat16 val) {\n *(nv_bfloat162*)(&data.x) = make_bfloat162(val, val);\n *(nv_bfloat162*)(&data.y) = make_bfloat162(val, val);\n}\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 4>::load(const nv_bfloat16* ptr) {\n data = *((uint2*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 4>::store(nv_bfloat16* ptr) const {\n *((uint2*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 4>::memcpy(nv_bfloat16* dst, const nv_bfloat16* src) {\n *((uint2*)dst) = *((uint2*)src);\n}\n\n// nv_bfloat16 x 8 or more\n\ntemplate <size_t vec_size>\nstruct vec_t<nv_bfloat16, vec_size> {\n static_assert(vec_size % 8 == 0, \"Invalid vector size\");\n int4 data[vec_size / 8];\n\n FLASHINFER_INLINE nv_bfloat16& operator[](size_t i) { return ((nv_bfloat16*)data)[i]; }\n FLASHINFER_INLINE const nv_bfloat16& operator[](size_t i) const {\n return ((const nv_bfloat16*)data)[i];\n }\n FLASHINFER_INLINE nv_bfloat16* ptr() { return reinterpret_cast<nv_bfloat16*>(&data); }\n FLASHINFER_INLINE void fill(nv_bfloat16 val) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n *(nv_bfloat162*)(&(data[i].x)) = make_bfloat162(val, val);\n *(nv_bfloat162*)(&(data[i].y)) = make_bfloat162(val, val);\n *(nv_bfloat162*)(&(data[i].z)) = make_bfloat162(val, val);\n *(nv_bfloat162*)(&(data[i].w)) = make_bfloat162(val, val);\n }\n }\n FLASHINFER_INLINE void load(const nv_bfloat16* ptr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n data[i] = ((int4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(nv_bfloat16* ptr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n ((int4*)ptr)[i] = data[i];\n }\n }\n FLASHINFER_INLINE void store_global_release(nv_bfloat16* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n st_global_release(data[i], (int4*)(addr + i * 8));\n }\n }\n FLASHINFER_INLINE void load_global_acquire(nv_bfloat16* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n data[i] = ld_global_acquire((int4*)(addr + i * 8));\n }\n }\n FLASHINFER_INLINE void store_global_volatile(nv_bfloat16* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n st_global_volatile(data[i], (int4*)(addr + i * 8));\n }\n }\n FLASHINFER_INLINE void load_global_volatile(nv_bfloat16* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n data[i] = ld_global_volatile((int4*)(addr + i * 8));\n }\n }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(nv_bfloat16* dst, const nv_bfloat16* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n ((int4*)dst)[i] = ((int4*)src)[i];\n }\n }\n};\n\n/******************* vec_t<uint8_t> *******************/\n\n// uint8_t x 1\ntemplate <>\nstruct vec_t<uint8_t, 1> {\n uint8_t data;\n\n FLASHINFER_INLINE uint8_t& operator[](size_t i) { return ((uint8_t*)(&data))[i]; }\n FLASHINFER_INLINE const uint8_t& operator[](size_t i) const {\n return ((const uint8_t*)(&data))[i];\n }\n FLASHINFER_INLINE uint8_t* ptr() { return reinterpret_cast<uint8_t*>(&data); }\n FLASHINFER_INLINE void fill(uint8_t val);\n FLASHINFER_INLINE void load(const uint8_t* ptr);\n FLASHINFER_INLINE void store(uint8_t* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 1>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(uint8_t* dst, const uint8_t* src);\n};\n\nFLASHINFER_INLINE void vec_t<uint8_t, 1>::fill(uint8_t val) { data = val; }\n\nFLASHINFER_INLINE void vec_t<uint8_t, 1>::load(const uint8_t* ptr) { data = *ptr; }\n\nFLASHINFER_INLINE void vec_t<uint8_t, 1>::store(uint8_t* ptr) const { *ptr = data; }\n\nFLASHINFER_INLINE void vec_t<uint8_t, 1>::memcpy(uint8_t* dst, const uint8_t* src) { *dst = *src; }\n\n// uint8_t x 2\ntemplate <>\nstruct vec_t<uint8_t, 2> {\n uint16_t data;\n\n FLASHINFER_INLINE uint8_t& operator[](size_t i) { return ((uint8_t*)(&data))[i]; }\n FLASHINFER_INLINE const uint8_t& operator[](size_t i) const {\n return ((const uint8_t*)(&data))[i];\n }\n FLASHINFER_INLINE uint8_t* ptr() { return reinterpret_cast<uint8_t*>(&data); }\n FLASHINFER_INLINE void fill(uint8_t val);\n FLASHINFER_INLINE void load(const uint8_t* ptr);\n FLASHINFER_INLINE void store(uint8_t* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 2>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(uint8_t* dst, const uint8_t* src);\n};\n\nFLASHINFER_INLINE void vec_t<uint8_t, 2>::fill(uint8_t val) {\n data = (uint16_t(val) << 8) | uint16_t(val);\n}\n\nFLASHINFER_INLINE void vec_t<uint8_t, 2>::load(const uint8_t* ptr) { data = *((uint16_t*)ptr); }\n\nFLASHINFER_INLINE void vec_t<uint8_t, 2>::store(uint8_t* ptr) const { *((uint16_t*)ptr) = data; }\n\nFLASHINFER_INLINE void vec_t<uint8_t, 2>::memcpy(uint8_t* dst, const uint8_t* src) {\n *((uint16_t*)dst) = *((uint16_t*)src);\n}\n\n// uint8_t x 4\n\ntemplate <>\nstruct vec_t<uint8_t, 4> {\n uint32_t data;\n\n FLASHINFER_INLINE uint8_t& operator[](size_t i) { return ((uint8_t*)(&data))[i]; }\n FLASHINFER_INLINE const uint8_t& operator[](size_t i) const {\n return ((const uint8_t*)(&data))[i];\n }\n FLASHINFER_INLINE uint8_t* ptr() { return reinterpret_cast<uint8_t*>(&data); }\n FLASHINFER_INLINE void fill(uint8_t val);\n FLASHINFER_INLINE void load(const uint8_t* ptr);\n FLASHINFER_INLINE void store(uint8_t* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 4>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(uint8_t* dst, const uint8_t* src);\n};\n\nFLASHINFER_INLINE void vec_t<uint8_t, 4>::fill(uint8_t val) {\n data = (uint32_t(val) << 24) | (uint32_t(val) << 16) | (uint32_t(val) << 8) | uint32_t(val);\n}\n\nFLASHINFER_INLINE void vec_t<uint8_t, 4>::load(const uint8_t* ptr) { data = *((uint32_t*)ptr); }\n\nFLASHINFER_INLINE void vec_t<uint8_t, 4>::store(uint8_t* ptr) const { *((uint32_t*)ptr) = data; }\n\nFLASHINFER_INLINE void vec_t<uint8_t, 4>::memcpy(uint8_t* dst, const uint8_t* src) {\n *((uint32_t*)dst) = *((uint32_t*)src);\n}\n\n// uint8_t x 8\n\ntemplate <>\nstruct vec_t<uint8_t, 8> {\n uint2 data;\n\n FLASHINFER_INLINE uint8_t& operator[](size_t i) { return ((uint8_t*)(&data))[i]; }\n FLASHINFER_INLINE const uint8_t& operator[](size_t i) const {\n return ((const uint8_t*)(&data))[i];\n }\n FLASHINFER_INLINE uint8_t* ptr() { return reinterpret_cast<uint8_t*>(&data); }\n FLASHINFER_INLINE void fill(uint8_t val);\n FLASHINFER_INLINE void load(const uint8_t* ptr);\n FLASHINFER_INLINE void store(uint8_t* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 8>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(uint8_t* dst, const uint8_t* src);\n};\n\nFLASHINFER_INLINE void vec_t<uint8_t, 8>::fill(uint8_t val) {\n uint32_t val32 =\n (uint32_t(val) << 24) | (uint32_t(val) << 16) | (uint32_t(val) << 8) | uint32_t(val);\n data.x = val32;\n data.y = val32;\n}\n\nFLASHINFER_INLINE void vec_t<uint8_t, 8>::load(const uint8_t* ptr) { data = *((uint2*)ptr); }\n\nFLASHINFER_INLINE void vec_t<uint8_t, 8>::store(uint8_t* ptr) const { *((uint2*)ptr) = data; }\n\nFLASHINFER_INLINE void vec_t<uint8_t, 8>::memcpy(uint8_t* dst, const uint8_t* src) {\n *((uint2*)dst) = *((uint2*)src);\n}\n\n// uint8_t x 16 or more\n\ntemplate <size_t vec_size>\nstruct vec_t<uint8_t, vec_size> {\n static_assert(vec_size % 16 == 0, \"Invalid vector size\");\n int4 data[vec_size / 16];\n\n FLASHINFER_INLINE uint8_t& operator[](size_t i) { return ((uint8_t*)data)[i]; }\n FLASHINFER_INLINE const uint8_t& operator[](size_t i) const { return ((const uint8_t*)data)[i]; }\n FLASHINFER_INLINE uint8_t* ptr() { return reinterpret_cast<uint8_t*>(&data); }\n FLASHINFER_INLINE void fill(uint8_t val) {\n uint32_t val32 =\n (uint32_t(val) << 24) | (uint32_t(val) << 16) | (uint32_t(val) << 8) | uint32_t(val);\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i].x = val32;\n data[i].y = val32;\n data[i].z = val32;\n data[i].w = val32;\n }\n }\n FLASHINFER_INLINE void load(const uint8_t* ptr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i] = ((int4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(uint8_t* ptr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((int4*)ptr)[i] = data[i];\n }\n }\n FLASHINFER_INLINE void load_global_acquire(uint8_t* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i] = ld_global_acquire((int4*)(addr + i * 16));\n }\n }\n FLASHINFER_INLINE void store_global_release(uint8_t* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n st_global_release(data[i], (int4*)(addr + i * 16));\n }\n }\n FLASHINFER_INLINE void load_global_volatile(uint8_t* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i] = ld_global_volatile((int4*)(addr + i * 16));\n }\n }\n FLASHINFER_INLINE void store_global_volatile(uint8_t* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n st_global_volatile(data[i], (int4*)(addr + i * 16));\n }\n }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(uint8_t* dst, const uint8_t* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((int4*)dst)[i] = ((int4*)src)[i];\n }\n }\n};\n\n/******************* vec_t<float> *******************/\n\n// float x 1\n\ntemplate <>\nstruct vec_t<float, 1> {\n float data;\n\n FLASHINFER_INLINE float& operator[](size_t i) { return ((float*)(&data))[i]; }\n FLASHINFER_INLINE const float& operator[](size_t i) const { return ((const float*)(&data))[i]; }\n FLASHINFER_INLINE float* ptr() { return reinterpret_cast<float*>(&data); }\n FLASHINFER_INLINE void fill(float val);\n FLASHINFER_INLINE void load(const float* ptr);\n FLASHINFER_INLINE void store(float* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 1>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(float* dst, const float* src);\n};\n\nFLASHINFER_INLINE void vec_t<float, 1>::fill(float val) { data = val; }\n\nFLASHINFER_INLINE void vec_t<float, 1>::load(const float* ptr) { data = *ptr; }\n\nFLASHINFER_INLINE void vec_t<float, 1>::store(float* ptr) const { *ptr = data; }\n\nFLASHINFER_INLINE void vec_t<float, 1>::memcpy(float* dst, const float* src) { *dst = *src; }\n\n// float x 2\n\ntemplate <>\nstruct vec_t<float, 2> {\n float2 data;\n\n FLASHINFER_INLINE float& operator[](size_t i) { return ((float*)(&data))[i]; }\n FLASHINFER_INLINE const float& operator[](size_t i) const { return ((const float*)(&data))[i]; }\n FLASHINFER_INLINE float* ptr() { return reinterpret_cast<float*>(&data); }\n FLASHINFER_INLINE void fill(float val);\n FLASHINFER_INLINE void load(const float* ptr);\n FLASHINFER_INLINE void store(float* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 2>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(float* dst, const float* src);\n};\n\nFLASHINFER_INLINE void vec_t<float, 2>::fill(float val) { data = make_float2(val, val); }\n\nFLASHINFER_INLINE void vec_t<float, 2>::load(const float* ptr) { data = *((float2*)ptr); }\n\nFLASHINFER_INLINE void vec_t<float, 2>::store(float* ptr) const { *((float2*)ptr) = data; }\n\nFLASHINFER_INLINE void vec_t<float, 2>::memcpy(float* dst, const float* src) {\n *((float2*)dst) = *((float2*)src);\n}\n\n// float x 4 or more\ntemplate <size_t vec_size>\nstruct vec_t<float, vec_size> {\n static_assert(vec_size % 4 == 0, \"Invalid vector size\");\n float4 data[vec_size / 4];\n\n FLASHINFER_INLINE float& operator[](size_t i) { return ((float*)(data))[i]; }\n FLASHINFER_INLINE const float& operator[](size_t i) const { return ((const float*)(data))[i]; }\n FLASHINFER_INLINE float* ptr() { return reinterpret_cast<float*>(&data); }\n FLASHINFER_INLINE void fill(float val) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 4; ++i) {\n data[i] = make_float4(val, val, val, val);\n }\n }\n FLASHINFER_INLINE void load(const float* ptr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 4; ++i) {\n data[i] = ((float4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(float* ptr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 4; ++i) {\n ((float4*)ptr)[i] = data[i];\n }\n }\n FLASHINFER_INLINE void store_global_release(float* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 4; ++i) {\n st_global_release(*(int4*)(data + i), (int4*)(addr + i * 4));\n }\n }\n FLASHINFER_INLINE void load_global_acquire(float* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 4; ++i) {\n *((int4*)(data + i)) = ld_global_acquire((int4*)(addr + i * 4));\n }\n }\n FLASHINFER_INLINE void store_global_volatile(float* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 4; ++i) {\n st_global_volatile(*(int4*)(data + i), (int4*)(addr + i * 4));\n }\n }\n FLASHINFER_INLINE void load_global_volatile(float* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 4; ++i) {\n *((int4*)(data + i)) = ld_global_volatile((int4*)(addr + i * 4));\n }\n }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(float* dst, const float* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 4; ++i) {\n ((float4*)dst)[i] = ((float4*)src)[i];\n }\n }\n};\n\ntemplate <typename T>\nstruct vec2_dtype {\n using type = T;\n};\n\ntemplate <>\nstruct vec2_dtype<half> {\n using type = half2;\n};\n\ntemplate <>\nstruct vec2_dtype<__nv_bfloat16> {\n using type = __nv_bfloat162;\n};\n\ntemplate <>\nstruct vec2_dtype<__nv_fp8_e4m3> {\n using type = __nv_fp8x2_e4m3;\n};\n\ntemplate <>\nstruct vec2_dtype<__nv_fp8_e5m2> {\n using type = __nv_fp8x2_e5m2;\n};\n\ntemplate <typename T>\nusing vec2_dtype_t = typename vec2_dtype<T>::type;\n\ntemplate <typename T, size_t VEC_SIZE>\nFLASHINFER_INLINE vec2_dtype_t<T> get_vec2_element(vec_t<T, VEC_SIZE>& vec, int i) {\n static_assert(VEC_SIZE % 2 == 0, \"VEC_SIZE must be a multiple of 2\");\n return ((vec2_dtype_t<T>*)&(vec[0]))[i];\n}\n\n} // namespace flashinfer\n\n#endif // VEC_DTYPES_CUH_\n"},"diff":{"kind":"string","value":"--- include/flashinfer/vec_dtypes.cuh\n+++ include/flashinfer/vec_dtypes.cuh\n@@ -414,7 +414,82 @@\n }\n };\n \n+// E2M1 nibble decoding helpers. These are plain integer and 16-bit bit manipulation with no\n+// FP4 type in their signatures, so they sit outside the FP4 feature guard below: the tile\n+// repack in attention/prefill.cuh names them from a template whose FP4 branch is discarded,\n+// not removed, and would otherwise fail to compile in builds without FP4 enabled.\n+// `prmt` with the msb of a selector nibble set replicates the sign (msb) of the selected byte\n+// across the whole output byte, giving 0x00 or 0xFF. `__byte_perm` discards that bit, so the\n+// E2M1 sign spread below has to reach for the PTX instruction directly.\n+__device__ __forceinline__ uint32_t prmt_b32(uint32_t a, uint32_t b, uint32_t sel) {\n+ uint32_t r;\n+ asm(\"prmt.b32 %0, %1, %2, %3;\" : \"=r\"(r) : \"r\"(a), \"r\"(b), \"r\"(sel));\n+ return r;\n+}\n+\n+// Spread the four E2M1 sign bits of `packed`'s low/high half into byte msbs.\n+//\n+// `packed` holds eight fp4 values as eight nibbles; byte j carries value 2j in bits[3:0] and\n+// value 2j+1 in bits[7:4], so bit 3 of byte j is an even value's sign and bit 7 is an odd\n+// value's sign. Byte j's msb is therefore already the odd sign, and `packed << 4` puts the even\n+// sign in the same place. One sign-replicating `prmt` then gathers the four signs in value order\n+// as 0x00/0xFF bytes; the caller masks to 0x80 and merges, which `lop3` folds into one\n+// instruction. Selector 0xD9C8 covers values 0..3, 0xFBEA covers values 4..7.\n+__device__ __forceinline__ uint32_t e2m1_sign_bytes(uint32_t packed, uint32_t sel) {\n+ return prmt_b32(packed << 4, packed, sel) & 0x80808080u;\n+}\n+\n+// Dequantize eight E2M1 values, held as the eight nibbles of `packed` in value order, into four\n+// packed 16-bit pairs. Pure ALU, register-only: the magnitude table is indexed by `prmt`.\n+//\n+// FP16: all eight E2M1 magnitudes {0,0.5,1,1.5,2,3,4,6} encode with a zero low byte, so the whole\n+// table is eight high bytes -- exactly one `prmt` source window -- and the expansion just inserts\n+// zero low bytes. BF16 magnitudes have varying low bytes, so two tables are indexed and the\n+// {low, high} byte pairs are interleaved instead.\n+__device__ __forceinline__ void e2m1x8_to_f16x8(uint32_t packed, uint32_t* d) {\n+ constexpr uint32_t kHi0 = 0x3E3C3800u; // high bytes of +{0.0, 0.5, 1.0, 1.5}\n+ constexpr uint32_t kHi1 = 0x46444240u; // high bytes of +{2.0, 3.0, 4.0, 6.0}\n+ const uint32_t mag = packed & 0x77777777u;\n+ uint32_t hi_a = __byte_perm(kHi0, kHi1, mag); // magnitudes of values 0..3\n+ uint32_t hi_b = __byte_perm(kHi0, kHi1, mag >> 16); // magnitudes of values 4..7\n+ hi_a |= e2m1_sign_bytes(packed, 0xD9C8u);\n+ hi_b |= e2m1_sign_bytes(packed, 0xFBEAu);\n+ d[0] = __byte_perm(hi_a, 0u, 0x1404u);\n+ d[1] = __byte_perm(hi_a, 0u, 0x3424u);\n+ d[2] = __byte_perm(hi_b, 0u, 0x1404u);\n+ d[3] = __byte_perm(hi_b, 0u, 0x3424u);\n+}\n+\n+__device__ __forceinline__ void e2m1x8_to_bf16x8(uint32_t packed, uint32_t* d) {\n+ constexpr uint32_t kHi0 = 0x3F3F3F00u; // high bytes of +{0.0, 0.5, 1.0, 1.5}\n+ constexpr uint32_t kHi1 = 0x40404040u; // high bytes of +{2.0, 3.0, 4.0, 6.0}\n+ constexpr uint32_t kLo0 = 0xC0800000u; // low bytes of +{0.0, 0.5, 1.0, 1.5}\n+ constexpr uint32_t kLo1 = 0xC0804000u; // low bytes of +{2.0, 3.0, 4.0, 6.0}\n+ const uint32_t mag = packed & 0x77777777u;\n+ const uint32_t mag_a = mag, mag_b = mag >> 16;\n+ uint32_t hi_a = __byte_perm(kHi0, kHi1, mag_a);\n+ uint32_t hi_b = __byte_perm(kHi0, kHi1, mag_b);\n+ const uint32_t lo_a = __byte_perm(kLo0, kLo1, mag_a);\n+ const uint32_t lo_b = __byte_perm(kLo0, kLo1, mag_b);\n+ hi_a |= e2m1_sign_bytes(packed, 0xD9C8u);\n+ hi_b |= e2m1_sign_bytes(packed, 0xFBEAu);\n+ d[0] = __byte_perm(lo_a, hi_a, 0x5140u);\n+ d[1] = __byte_perm(lo_a, hi_a, 0x7362u);\n+ d[2] = __byte_perm(lo_b, hi_b, 0x5140u);\n+ d[3] = __byte_perm(lo_b, hi_b, 0x7362u);\n+}\n+\n+template <typename DType16>\n+__device__ __forceinline__ void e2m1x8_to_16bx8(uint32_t packed, uint32_t* d) {\n+ if constexpr (std::is_same_v<DType16, half>) {\n+ e2m1x8_to_f16x8(packed, d);\n+ } else {\n+ e2m1x8_to_bf16x8(packed, d);\n+ }\n+}\n+\n #if defined(FLASHINFER_ENABLE_FP4_E2M1) && CUDA_VERSION >= 12080\n+\n // Convert __nv_fp4x2_e2m1 (2 fp4 values per byte) to fp16.\n // vec_size counts fp16 output elements; src has stride-2 layout:\n // src[0] holds x0,x1 src[1] is padding\n@@ -442,6 +517,23 @@\n reinterpret_cast<uint32_t*>(dst)[i] = y;\n }\n #else\n+#if defined(__CUDA_ARCH__)\n+ // Fast path for arch < SM100: pure-ALU table lookup through `prmt`.\n+ // The FP16 encodings of the eight E2M1 magnitudes {0,0.5,1,1.5,2,3,4,6} all have a zero low\n+ // byte, so the whole magnitude table fits in the 8 bytes a single `prmt` can index and the\n+ // conversion stays in registers. The `uint16_t lut[16]` array below instead lands in local\n+ // memory: one dependent LDL per element, plus a 32-byte stack frame in every kernel that\n+ // inlines this.\n+ if constexpr (vec_size % 8 == 0) {\n+#pragma unroll\n+ for (size_t i = 0; i < vec_size / 8; ++i) {\n+ const uint32_t* s = reinterpret_cast<const uint32_t*>(src) + i * 2;\n+ // Payload bytes sit at stride 2; gather them into eight nibbles (nibble j == value j).\n+ e2m1x8_to_f16x8(__byte_perm(s[0], s[1], 0x6420u), reinterpret_cast<uint32_t*>(dst) + i * 4);\n+ }\n+ return;\n+ }\n+#endif\n // Software LUT fallback for arch < SM100.\n // e2m1 encoding: bit[3]=sign, bit[2:0]=magnitude index in {0,0.5,1,1.5,2,3,4,6}.\n // Each packed byte holds two fp4 values: bits[3:0]=first, bits[7:4]=second.\n@@ -550,6 +642,21 @@\n reinterpret_cast<uint32_t*>(dst)[i] = y;\n }\n #else\n+#if defined(__CUDA_ARCH__)\n+ // Fast path for arch < SM100: pure-ALU table lookup through `prmt`. Unlike FP16, the BF16\n+ // encodings of the E2M1 magnitudes have a varying low byte, so two 8-byte tables are indexed\n+ // and then interleaved. Still register-only; see the FP16 specialization for why the\n+ // `uint16_t lut[16]` array below is expensive.\n+ if constexpr (vec_size % 8 == 0) {\n+#pragma unroll\n+ for (size_t i = 0; i < vec_size / 8; ++i) {\n+ const uint32_t* s = reinterpret_cast<const uint32_t*>(src) + i * 2;\n+ e2m1x8_to_bf16x8(__byte_perm(s[0], s[1], 0x6420u),\n+ reinterpret_cast<uint32_t*>(dst) + i * 4);\n+ }\n+ return;\n+ }\n+#endif\n // Software LUT fallback for arch < SM100.\n // e2m1 encoding: bit[3]=sign, bit[2:0]=magnitude index in {0,0.5,1,1.5,2,3,4,6}.\n // Each packed byte holds two fp4 values: bits[3:0]=first, bits[7:4]=second."},"lines_added":{"kind":"number","value":107,"string":"107"},"lines_removed":{"kind":"number","value":0,"string":"0"},"files_in_commit":{"kind":"number","value":2,"string":"2"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["HOPPER","SM100","SM80","SM86","SM89","SM90"],"string":"[\n \"HOPPER\",\n \"SM100\",\n \"SM80\",\n \"SM86\",\n \"SM89\",\n \"SM90\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":["8.2x","5.4x","6.75x","1.0x","1.0x","6.76x","2.43x","8.17x","2.97x","6.78x"],"string":"[\n \"8.2x\",\n \"5.4x\",\n \"6.75x\",\n \"1.0x\",\n \"1.0x\",\n \"6.76x\",\n \"2.43x\",\n \"8.17x\",\n \"2.97x\",\n \"6.78x\"\n]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (include/flashinfer/vec_dtypes.cuh).\n\nGoal: perf(attention): cut NVFP4 KV dequant instructions on targets without native FP4/FP8 conversion\nTarget hardware: HOPPER, SM100, SM80, SM86, SM89, SM90\nTarget models: unspecified\n\nCurrent file:\n```cuda\n/*\n * Copyright (c) 2023 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef VEC_DTYPES_CUH_\n#define VEC_DTYPES_CUH_\n\n#include <cuda.h>\n#include <cuda_bf16.h>\n#include <cuda_fp16.h>\n#include <cuda_fp8.h>\n#if CUDA_VERSION >= 12080\n#include <cuda_fp4.h>\n#endif\n#include <cuda_runtime.h>\n\n#include <type_traits>\n\nnamespace flashinfer {\n\n#if (!defined(__CUDA_ARCH__) || (__CUDA_ARCH__ >= 900))\n#define FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n#endif\n\n#define FLASHINFER_INLINE inline __attribute__((always_inline)) __device__\n\n__device__ __forceinline__ void st_global_release(int4 const& val, int4* addr) {\n asm volatile(\"st.release.global.sys.v4.b32 [%4], {%0, %1, %2, %3};\" ::\"r\"(val.x), \"r\"(val.y),\n \"r\"(val.z), \"r\"(val.w), \"l\"(addr));\n}\n\n__device__ __forceinline__ int4 ld_global_acquire(int4* addr) {\n int4 val;\n asm volatile(\"ld.acquire.global.sys.v4.b32 {%0, %1, %2, %3}, [%4];\"\n : \"=r\"(val.x), \"=r\"(val.y), \"=r\"(val.z), \"=r\"(val.w)\n : \"l\"(addr));\n return val;\n}\n\n__device__ __forceinline__ void st_global_volatile(int4 const& val, int4* addr) {\n asm volatile(\"st.volatile.global.v4.b32 [%4], {%0, %1, %2, %3};\" ::\"r\"(val.x), \"r\"(val.y),\n \"r\"(val.z), \"r\"(val.w), \"l\"(addr));\n}\n\n__device__ __forceinline__ int4 ld_global_volatile(int4* addr) {\n int4 val;\n asm volatile(\"ld.volatile.global.v4.b32 {%0, %1, %2, %3}, [%4];\"\n : \"=r\"(val.x), \"=r\"(val.y), \"=r\"(val.z), \"=r\"(val.w)\n : \"l\"(addr));\n return val;\n}\n\n#if (__CUDACC_VER_MAJOR__ * 10000 + __CUDACC_VER_MINOR__ * 100 < 120200) && \\\n (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ < 800))\n// CUDA version < 12.2 and GPU architecture < 80\nFLASHINFER_INLINE __nv_bfloat162 make_bfloat162(const __nv_bfloat16 x, const __nv_bfloat16 y) {\n __nv_bfloat162 t;\n t.x = x;\n t.y = y;\n return t;\n}\n\nFLASHINFER_INLINE __nv_bfloat16 __hmul(const __nv_bfloat16 a, const __nv_bfloat16 b) {\n __nv_bfloat16 val;\n const float fa = __bfloat162float(a);\n const float fb = __bfloat162float(b);\n // avoid ftz in device code\n val = __float2bfloat16(__fmaf_ieee_rn(fa, fb, -0.0f));\n return val;\n}\n\nFLASHINFER_INLINE __nv_bfloat162 __hmul2(const __nv_bfloat162 a, const __nv_bfloat162 b) {\n __nv_bfloat162 val;\n val.x = __hmul(a.x, b.x);\n val.y = __hmul(a.y, b.y);\n return val;\n}\n\nFLASHINFER_INLINE __nv_bfloat162 __floats2bfloat162_rn(const float a, const float b) {\n __nv_bfloat162 val;\n val = __nv_bfloat162(__float2bfloat16_rn(a), __float2bfloat16_rn(b));\n return val;\n}\n\nFLASHINFER_INLINE __nv_bfloat162 __float22bfloat162_rn(const float2 a) {\n __nv_bfloat162 val = __floats2bfloat162_rn(a.x, a.y);\n return val;\n}\nFLASHINFER_INLINE float2 __bfloat1622float2(const __nv_bfloat162 a) {\n float hi_float;\n float lo_float;\n lo_float = __internal_bfloat162float(((__nv_bfloat162_raw)a).x);\n hi_float = __internal_bfloat162float(((__nv_bfloat162_raw)a).y);\n return make_float2(lo_float, hi_float);\n}\n#endif\n\n/******************* vec_t type cast *******************/\n\ntemplate <typename dst_t, typename src_t>\nstruct vec_cast {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(dst_t* dst, const src_t* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size; ++i) {\n dst[i] = (dst_t)src[i];\n }\n }\n};\n\ntemplate <>\nstruct vec_cast<__nv_fp8_e4m3, float> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(__nv_fp8_e4m3* dst, const float* src) {\n if constexpr (vec_size == 1) {\n dst[0] = __nv_fp8_e4m3(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n ((__nv_fp8x2_storage_t*)dst)[i] =\n __nv_cvt_float2_to_fp8x2(((float2*)src)[i], __NV_SATFINITE, __NV_E4M3);\n }\n }\n }\n};\n\ntemplate <>\nstruct vec_cast<__nv_fp8_e5m2, float> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(__nv_fp8_e5m2* dst, const float* src) {\n if constexpr (vec_size == 1) {\n dst[0] = __nv_fp8_e5m2(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n ((__nv_fp8x2_storage_t*)dst)[i] =\n __nv_cvt_float2_to_fp8x2(((float2*)src)[i], __NV_SATFINITE, __NV_E5M2);\n }\n }\n }\n};\n\ntemplate <>\nstruct vec_cast<float, half> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(float* dst, const half* src) {\n if constexpr (vec_size == 1) {\n dst[0] = (float)src[0];\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n ((float2*)dst)[i] = __half22float2(((half2*)src)[i]);\n }\n }\n }\n};\n\ntemplate <>\nstruct vec_cast<half, float> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(half* dst, const float* src) {\n if constexpr (vec_size == 1) {\n dst[0] = __float2half(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n ((half2*)dst)[i] = __float22half2_rn(((float2*)src)[i]);\n }\n }\n }\n};\n\ntemplate <typename T>\nconstexpr FLASHINFER_INLINE int get_exponent_bits() {\n if constexpr (std::is_same_v<T, __nv_fp8_e4m3>) {\n return 4;\n } else if constexpr (std::is_same_v<T, __nv_fp8_e5m2>) {\n return 5;\n } else if constexpr (std::is_same_v<T, half>) {\n return 5;\n } else if constexpr (std::is_same_v<T, nv_bfloat16>) {\n return 8;\n }\n}\n\ntemplate <typename T>\nconstexpr FLASHINFER_INLINE int get_mantissa_bits() {\n if constexpr (std::is_same_v<T, __nv_fp8_e4m3>) {\n return 3;\n } else if constexpr (std::is_same_v<T, __nv_fp8_e5m2>) {\n return 2;\n } else if constexpr (std::is_same_v<T, half>) {\n return 11;\n } else if constexpr (std::is_same_v<T, nv_bfloat16>) {\n return 7;\n }\n}\n\n/*!\n * \\brief Fallback to software fast dequant implementation if hardware dequantization is not\n * available.\n * \\note Inspired by Marlin's fast dequantization, but here we don't have to permute\n * weights order.\n * \\ref\n * https://github.com/vllm-project/vllm/blob/6dffa4b0a6120159ef2fe44d695a46817aff65bc/csrc/quantization/fp8/fp8_marlin.cu#L120\n */\ntemplate <typename fp8_dtype, typename fp16_dtype>\n__device__ void fast_dequant_f8f16x4(uint32_t* input, uint2* output) {\n uint32_t q = *input;\n if constexpr (std::is_same_v<fp8_dtype, __nv_fp8_e5m2> && std::is_same_v<fp16_dtype, half>) {\n output->x = __byte_perm(0U, q, 0x5140);\n output->y = __byte_perm(0U, q, 0x7362);\n } else {\n constexpr int FP8_EXPONENT = get_exponent_bits<fp8_dtype>();\n constexpr int FP8_MANTISSA = get_mantissa_bits<fp8_dtype>();\n constexpr int FP16_EXPONENT = get_exponent_bits<fp16_dtype>();\n\n constexpr int RIGHT_SHIFT = FP16_EXPONENT - FP8_EXPONENT;\n // Calculate MASK for extracting mantissa and exponent\n constexpr int MASK1 = 0x80000000;\n constexpr int MASK2 = MASK1 >> (FP8_EXPONENT + FP8_MANTISSA);\n constexpr int MASK3 = MASK2 & 0x7fffffff;\n constexpr int MASK = MASK3 | (MASK3 >> 16);\n q = __byte_perm(q, q, 0x1302);\n\n // Extract and shift FP8 values to FP16 format\n uint32_t Out1 = (q & 0x80008000) | ((q & MASK) >> RIGHT_SHIFT);\n uint32_t Out2 = ((q << 8) & 0x80008000) | (((q << 8) & MASK) >> RIGHT_SHIFT);\n\n constexpr int BIAS_OFFSET = (1 << (FP16_EXPONENT - 1)) - (1 << (FP8_EXPONENT - 1));\n // Construct and apply exponent bias\n if constexpr (std::is_same_v<fp16_dtype, half>) {\n const half2 bias_reg = __float2half2_rn(float(1 << BIAS_OFFSET));\n\n // Convert to half2 and apply bias\n *(half2*)&(output->x) = __hmul2(*reinterpret_cast<const half2*>(&Out1), bias_reg);\n *(half2*)&(output->y) = __hmul2(*reinterpret_cast<const half2*>(&Out2), bias_reg);\n } else {\n constexpr uint32_t BIAS = (BIAS_OFFSET + 127) << 23;\n const nv_bfloat162 bias_reg = __float2bfloat162_rn(*reinterpret_cast<const float*>(&BIAS));\n // Convert to bfloat162 and apply bias\n *(nv_bfloat162*)&(output->x) =\n __hmul2(*reinterpret_cast<const nv_bfloat162*>(&Out1), bias_reg);\n *(nv_bfloat162*)&(output->y) =\n __hmul2(*reinterpret_cast<const nv_bfloat162*>(&Out2), bias_reg);\n }\n }\n}\n\ntemplate <>\nstruct vec_cast<nv_bfloat16, __nv_fp8_e4m3> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(nv_bfloat16* dst, const __nv_fp8_e4m3* src) {\n if constexpr (vec_size == 1) {\n dst[0] = nv_bfloat16(src[0]);\n } else if constexpr (vec_size == 2) {\n dst[0] = nv_bfloat16(src[0]);\n dst[1] = nv_bfloat16(src[1]);\n } else {\n static_assert(vec_size % 4 == 0, \"vec_size must be a multiple of 4\");\n#pragma unroll\n for (uint32_t i = 0; i < vec_size / 4; ++i) {\n fast_dequant_f8f16x4<__nv_fp8_e4m3, nv_bfloat16>((uint32_t*)&src[i * 4],\n (uint2*)&dst[i * 4]);\n }\n }\n }\n};\n\ntemplate <>\nstruct vec_cast<nv_bfloat16, __nv_fp8_e5m2> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(nv_bfloat16* dst, const __nv_fp8_e5m2* src) {\n if constexpr (vec_size == 1) {\n dst[0] = nv_bfloat16(src[0]);\n } else if constexpr (vec_size == 2) {\n dst[0] = nv_bfloat16(src[0]);\n dst[1] = nv_bfloat16(src[1]);\n } else {\n static_assert(vec_size % 4 == 0, \"vec_size must be a multiple of 4\");\n#pragma unroll\n for (uint32_t i = 0; i < vec_size / 4; ++i) {\n fast_dequant_f8f16x4<__nv_fp8_e5m2, nv_bfloat16>((uint32_t*)&src[i * 4],\n (uint2*)&dst[i * 4]);\n }\n }\n }\n};\n\ntemplate <>\nstruct vec_cast<__nv_fp8_e4m3, half> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(__nv_fp8_e4m3* dst, const half* src) {\n#ifdef FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n if constexpr (vec_size == 1) {\n dst[0] = __nv_fp8_e4m3(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint16_t y;\n uint32_t x = *(uint32_t*)&src[i * 2];\n asm volatile(\"cvt.rn.satfinite.e4m3x2.f16x2 %0, %1;\" : \"=h\"(y) : \"r\"(x));\n *(uint16_t*)&dst[i * 2] = y;\n }\n }\n#else\n#pragma unroll\n for (size_t i = 0; i < vec_size; ++i) {\n dst[i] = __nv_fp8_e4m3(src[i]);\n }\n#endif // FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n }\n};\n\ntemplate <>\nstruct vec_cast<__nv_fp8_e5m2, half> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(__nv_fp8_e5m2* dst, const half* src) {\n#ifdef FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n if constexpr (vec_size == 1) {\n dst[0] = __nv_fp8_e5m2(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint16_t y;\n uint32_t x = *(uint32_t*)&src[i * 2];\n asm volatile(\"cvt.rn.satfinite.e5m2x2.f16x2 %0, %1;\" : \"=h\"(y) : \"r\"(x));\n *(uint16_t*)&dst[i * 2] = y;\n }\n }\n#else\n#pragma unroll\n for (size_t i = 0; i < vec_size; ++i) {\n dst[i] = __nv_fp8_e5m2(src[i]);\n }\n#endif // FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n }\n};\n\ntemplate <>\nstruct vec_cast<half, __nv_fp8_e4m3> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(half* dst, const __nv_fp8_e4m3* src) {\n#ifdef FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n if constexpr (vec_size == 1) {\n dst[0] = half(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint32_t y;\n uint16_t x = *(uint16_t*)&src[i * 2];\n asm volatile(\"cvt.rn.f16x2.e4m3x2 %0, %1;\" : \"=r\"(y) : \"h\"(x));\n *(uint32_t*)&dst[i * 2] = y;\n }\n }\n#else\n if constexpr (vec_size == 1) {\n dst[0] = half(src[0]);\n } else if constexpr (vec_size == 2) {\n dst[0] = half(src[0]);\n dst[1] = half(src[1]);\n } else {\n static_assert(vec_size % 4 == 0, \"vec_size must be a multiple of 4\");\n#pragma unroll\n for (uint32_t i = 0; i < vec_size / 4; ++i) {\n fast_dequant_f8f16x4<__nv_fp8_e4m3, half>((uint32_t*)&src[i * 4], (uint2*)&dst[i * 4]);\n }\n }\n#endif // FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n }\n};\n\ntemplate <>\nstruct vec_cast<half, __nv_fp8_e5m2> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(half* dst, const __nv_fp8_e5m2* src) {\n#ifdef FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n if constexpr (vec_size == 1) {\n dst[0] = half(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint32_t y;\n uint16_t x = *(uint16_t*)&src[i * 2];\n asm volatile(\"cvt.rn.f16x2.e5m2x2 %0, %1;\" : \"=r\"(y) : \"h\"(x));\n *(uint32_t*)&dst[i * 2] = y;\n }\n }\n#else\n if constexpr (vec_size == 1) {\n dst[0] = half(src[0]);\n } else if constexpr (vec_size == 2) {\n dst[0] = half(src[0]);\n dst[1] = half(src[1]);\n } else {\n static_assert(vec_size % 4 == 0, \"vec_size must be a multiple of 4\");\n#pragma unroll\n for (uint32_t i = 0; i < vec_size / 4; ++i) {\n fast_dequant_f8f16x4<__nv_fp8_e5m2, half>((uint32_t*)&src[i * 4], (uint2*)&dst[i * 4]);\n }\n }\n#endif // FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED\n }\n};\n\n#if defined(FLASHINFER_ENABLE_FP4_E2M1) && CUDA_VERSION >= 12080\n// Convert __nv_fp4x2_e2m1 (2 fp4 values per byte) to fp16.\n// vec_size counts fp16 output elements; src has stride-2 layout:\n// src[0] holds x0,x1 src[1] is padding\n// src[2] holds x2,x3 src[3] is padding ... etc.\n// Each valid byte encodes 2 fp4 values -> 2 fp16 via cvt.rn.f16x2.e2m1x2.\ntemplate <>\nstruct vec_cast<half, __nv_fp4x2_e2m1> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(half* dst, const __nv_fp4x2_e2m1* src) {\n static_assert(vec_size % 2 == 0, \"vec_size must be even for fp4x2 dequantization\");\n#if (defined __CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint32_t y;\n // Valid fp4x2 bytes are at even positions (stride 2); odd positions are padding.\n uint32_t b = reinterpret_cast<const uint8_t*>(src)[i * 2];\n asm volatile(\n \"{\\n\"\n \".reg .b8 fp4_byte;\\n\"\n \"mov.b32 {fp4_byte, _, _, _}, %1;\\n\"\n \"cvt.rn.f16x2.e2m1x2 %0, fp4_byte;\\n\"\n \"}\"\n : \"=r\"(y)\n : \"r\"(b));\n reinterpret_cast<uint32_t*>(dst)[i] = y;\n }\n#else\n // Software LUT fallback for arch < SM100.\n // e2m1 encoding: bit[3]=sign, bit[2:0]=magnitude index in {0,0.5,1,1.5,2,3,4,6}.\n // Each packed byte holds two fp4 values: bits[3:0]=first, bits[7:4]=second.\n constexpr uint16_t lut[16] = {\n 0x0000, // +0.0\n 0x3800, // +0.5\n 0x3C00, // +1.0\n 0x3E00, // +1.5\n 0x4000, // +2.0\n 0x4200, // +3.0\n 0x4400, // +4.0\n 0x4600, // +6.0\n 0x8000, // -0.0\n 0xB800, // -0.5\n 0xBC00, // -1.0\n 0xBE00, // -1.5\n 0xC000, // -2.0\n 0xC200, // -3.0\n 0xC400, // -4.0\n 0xC600, // -6.0\n };\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint8_t b = reinterpret_cast<const uint8_t*>(src)[i * 2];\n reinterpret_cast<uint16_t*>(dst)[i * 2 + 0] = lut[b & 0x0F];\n reinterpret_cast<uint16_t*>(dst)[i * 2 + 1] = lut[(b >> 4) & 0x0F];\n }\n#endif\n }\n};\n\ntemplate <>\nstruct vec_cast<float, __nv_fp4x2_e2m1> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(float* dst, const __nv_fp4x2_e2m1* src) {\n static_assert(vec_size % 2 == 0, \"vec_size must be even for fp4x2 dequantization\");\n#if (defined __CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint32_t fp16x2;\n // Valid fp4x2 bytes are at even positions (stride 2); odd positions are padding.\n uint32_t b = reinterpret_cast<const uint8_t*>(src)[i * 2];\n asm volatile(\n \"{\\n\"\n \".reg .b8 fp4_byte;\\n\"\n \"mov.b32 {fp4_byte, _, _, _}, %1;\\n\"\n \"cvt.rn.f16x2.e2m1x2 %0, fp4_byte;\\n\"\n \"}\"\n : \"=r\"(fp16x2)\n : \"r\"(b));\n __half2 h2 = *reinterpret_cast<__half2*>(&fp16x2);\n reinterpret_cast<float2*>(dst)[i] = __half22float2(h2);\n }\n#else\n constexpr float lut[16] = {\n 0.0f, 0.5f, 1.0f, 1.5f, 2.0f, 3.0f, 4.0f, 6.0f,\n -0.0f, -0.5f, -1.0f, -1.5f, -2.0f, -3.0f, -4.0f, -6.0f,\n };\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint8_t b = reinterpret_cast<const uint8_t*>(src)[i * 2];\n dst[i * 2 + 0] = lut[b & 0x0F];\n dst[i * 2 + 1] = lut[(b >> 4) & 0x0F];\n }\n#endif\n }\n};\n\ntemplate <>\nstruct vec_cast<nv_bfloat16, __nv_fp4x2_e2m1> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(nv_bfloat16* dst, const __nv_fp4x2_e2m1* src) {\n static_assert(vec_size % 2 == 0, \"vec_size must be even for fp4x2 dequantization\");\n#if (defined __CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint32_t y;\n // Valid fp4x2 bytes are at even positions (stride 2); odd positions are padding.\n uint32_t b = reinterpret_cast<const uint8_t*>(src)[i * 2];\n#if (defined __CUDACC_VER_MAJOR__) && (defined __CUDACC_VER_MINOR__) && \\\n ((__CUDACC_VER_MAJOR__ > 13) || ((__CUDACC_VER_MAJOR__ == 13) && (__CUDACC_VER_MINOR__ >= 2)))\n // cvt.rn.bf16x2.e2m1x2 requires CUDA Toolkit >= 13.2\n asm volatile(\n \"{\\n\"\n \".reg .b8 fp4_byte;\\n\"\n \"mov.b32 {fp4_byte, _, _, _}, %1;\\n\"\n \"cvt.rn.bf16x2.e2m1x2 %0, fp4_byte;\\n\"\n \"}\"\n : \"=r\"(y)\n : \"r\"(b));\n#else\n // Fallback: convert e2m1 -> fp16 -> bf16 when cvt.rn.bf16x2.e2m1x2 is unavailable\n uint32_t fp16x2;\n asm volatile(\n \"{\\n\"\n \".reg .b8 fp4_byte;\\n\"\n \"mov.b32 {fp4_byte, _, _, _}, %1;\\n\"\n \"cvt.rn.f16x2.e2m1x2 %0, fp4_byte;\\n\"\n \"}\"\n : \"=r\"(fp16x2)\n : \"r\"(b));\n __half2 h2 = reinterpret_cast<__half2&>(fp16x2);\n __nv_bfloat162 bf16x2 = __float22bfloat162_rn(__half22float2(h2));\n y = reinterpret_cast<uint32_t&>(bf16x2);\n#endif\n reinterpret_cast<uint32_t*>(dst)[i] = y;\n }\n#else\n // Software LUT fallback for arch < SM100.\n // e2m1 encoding: bit[3]=sign, bit[2:0]=magnitude index in {0,0.5,1,1.5,2,3,4,6}.\n // Each packed byte holds two fp4 values: bits[3:0]=first, bits[7:4]=second.\n constexpr uint16_t lut[16] = {\n 0x0000, // +0.0\n 0x3F00, // +0.5\n 0x3F80, // +1.0\n 0x3FC0, // +1.5\n 0x4000, // +2.0\n 0x4040, // +3.0\n 0x4080, // +4.0\n 0x40C0, // +6.0\n 0x8000, // -0.0\n 0xBF00, // -0.5\n 0xBF80, // -1.0\n 0xBFC0, // -1.5\n 0xC000, // -2.0\n 0xC040, // -3.0\n 0xC080, // -4.0\n 0xC0C0, // -6.0\n };\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n uint8_t b = reinterpret_cast<const uint8_t*>(src)[i * 2];\n reinterpret_cast<uint16_t*>(dst)[i * 2 + 0] = lut[b & 0x0F];\n reinterpret_cast<uint16_t*>(dst)[i * 2 + 1] = lut[(b >> 4) & 0x0F];\n }\n#endif\n }\n};\n\n#endif // FLASHINFER_ENABLE_FP4_E2M1 && CUDA_VERSION >= 12080\n\ntemplate <>\nstruct vec_cast<float, nv_bfloat16> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(float* dst, const nv_bfloat16* src) {\n if constexpr (vec_size == 1) {\n dst[0] = (float)src[0];\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n ((float2*)dst)[i] = __bfloat1622float2(((nv_bfloat162*)src)[i]);\n }\n }\n }\n};\n\ntemplate <>\nstruct vec_cast<nv_bfloat16, float> {\n template <size_t vec_size>\n FLASHINFER_INLINE static void cast(nv_bfloat16* dst, const float* src) {\n if constexpr (vec_size == 1) {\n dst[0] = nv_bfloat16(src[0]);\n } else {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 2; ++i) {\n ((nv_bfloat162*)dst)[i] = __float22bfloat162_rn(((float2*)src)[i]);\n }\n }\n }\n};\n\ntemplate <typename float_t, size_t vec_size>\nstruct vec_t {\n FLASHINFER_INLINE float_t& operator[](size_t i);\n FLASHINFER_INLINE const float_t& operator[](size_t i) const;\n FLASHINFER_INLINE void fill(float_t val);\n FLASHINFER_INLINE void load(const float_t* ptr);\n FLASHINFER_INLINE void store(float_t* ptr) const;\n FLASHINFER_INLINE void load_global_acquire(float* addr);\n FLASHINFER_INLINE void store_global_release(float* addr) const;\n FLASHINFER_INLINE void load_global_volatile(float* addr);\n FLASHINFER_INLINE void store_global_volatile(float* addr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src);\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr);\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const;\n FLASHINFER_INLINE static void memcpy(float_t* dst, const float_t* src);\n FLASHINFER_INLINE float_t* ptr();\n};\n\ntemplate <typename src_float_t, typename tgt_float_t, size_t vec_size>\nFLASHINFER_INLINE void cast_from_impl(vec_t<tgt_float_t, vec_size>& dst,\n const vec_t<src_float_t, vec_size>& src) {\n vec_cast<tgt_float_t, src_float_t>::cast<vec_size>(\n dst.ptr(), const_cast<vec_t<src_float_t, vec_size>*>(&src)->ptr());\n}\n\ntemplate <typename src_float_t, typename tgt_float_t, size_t vec_size>\nFLASHINFER_INLINE void cast_load_impl(vec_t<tgt_float_t, vec_size>& dst,\n const src_float_t* src_ptr) {\n if constexpr (std::is_same_v<src_float_t, tgt_float_t>) {\n dst.load(src_ptr);\n } else {\n vec_t<src_float_t, vec_size> tmp;\n tmp.load(src_ptr);\n dst.cast_from(tmp);\n }\n}\n\ntemplate <typename src_float_t, typename tgt_float_t, size_t vec_size>\nFLASHINFER_INLINE void cast_store_impl(tgt_float_t* dst_ptr,\n const vec_t<src_float_t, vec_size>& src) {\n if constexpr (std::is_same_v<src_float_t, tgt_float_t>) {\n src.store(dst_ptr);\n } else {\n vec_t<tgt_float_t, vec_size> tmp;\n tmp.cast_from(src);\n tmp.store(dst_ptr);\n }\n}\n\n/******************* vec_t<__nv_fp8_e4m3> *******************/\n\n// __nv_fp8_e4m3 x 1\ntemplate <>\nstruct vec_t<__nv_fp8_e4m3, 1> {\n __nv_fp8_e4m3 data;\n\n FLASHINFER_INLINE __nv_fp8_e4m3& operator[](size_t i) { return ((__nv_fp8_e4m3*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e4m3& operator[](size_t i) const {\n return ((const __nv_fp8_e4m3*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e4m3* ptr() { return reinterpret_cast<__nv_fp8_e4m3*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e4m3 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e4m3* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e4m3* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 1>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e4m3* dst, const __nv_fp8_e4m3* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 1>::fill(__nv_fp8_e4m3 val) { data = val; }\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 1>::load(const __nv_fp8_e4m3* ptr) { data = *ptr; }\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 1>::store(__nv_fp8_e4m3* ptr) const { *ptr = data; }\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 1>::memcpy(__nv_fp8_e4m3* dst,\n const __nv_fp8_e4m3* src) {\n *dst = *src;\n}\n\n// __nv_fp8_e4m3 x 2\ntemplate <>\nstruct vec_t<__nv_fp8_e4m3, 2> {\n __nv_fp8x2_e4m3 data;\n\n FLASHINFER_INLINE __nv_fp8_e4m3& operator[](size_t i) { return ((__nv_fp8_e4m3*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e4m3& operator[](size_t i) const {\n return ((const __nv_fp8_e4m3*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e4m3* ptr() { return reinterpret_cast<__nv_fp8_e4m3*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e4m3 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e4m3* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e4m3* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 2>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e4m3* dst, const __nv_fp8_e4m3* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 2>::fill(__nv_fp8_e4m3 val) {\n data.__x = (__nv_fp8x2_storage_t(val.__x) << 8) | __nv_fp8x2_storage_t(val.__x);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 2>::load(const __nv_fp8_e4m3* ptr) {\n data = *((__nv_fp8x2_e4m3*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 2>::store(__nv_fp8_e4m3* ptr) const {\n *((__nv_fp8x2_e4m3*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 2>::memcpy(__nv_fp8_e4m3* dst,\n const __nv_fp8_e4m3* src) {\n *((__nv_fp8x2_e4m3*)dst) = *((__nv_fp8x2_e4m3*)src);\n}\n\n// __nv_fp8_e4m3 x 4\n\ntemplate <>\nstruct vec_t<__nv_fp8_e4m3, 4> {\n __nv_fp8x4_e4m3 data;\n\n FLASHINFER_INLINE __nv_fp8_e4m3& operator[](size_t i) { return ((__nv_fp8_e4m3*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e4m3& operator[](size_t i) const {\n return ((const __nv_fp8_e4m3*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e4m3* ptr() { return reinterpret_cast<__nv_fp8_e4m3*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e4m3 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e4m3* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e4m3* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 4>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e4m3* dst, const __nv_fp8_e4m3* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 4>::fill(__nv_fp8_e4m3 val) {\n data.__x = (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 4>::load(const __nv_fp8_e4m3* ptr) {\n data = *((__nv_fp8x4_e4m3*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 4>::store(__nv_fp8_e4m3* ptr) const {\n *((__nv_fp8x4_e4m3*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 4>::memcpy(__nv_fp8_e4m3* dst,\n const __nv_fp8_e4m3* src) {\n *((__nv_fp8x4_e4m3*)dst) = *((__nv_fp8x4_e4m3*)src);\n}\n\n// __nv_fp8_e4m3 x 8\n\ntemplate <>\nstruct vec_t<__nv_fp8_e4m3, 8> {\n uint2 data;\n\n FLASHINFER_INLINE __nv_fp8_e4m3& operator[](size_t i) { return ((__nv_fp8_e4m3*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e4m3& operator[](size_t i) const {\n return ((const __nv_fp8_e4m3*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e4m3* ptr() { return reinterpret_cast<__nv_fp8_e4m3*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e4m3 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e4m3* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e4m3* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 8>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e4m3* dst, const __nv_fp8_e4m3* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 8>::fill(__nv_fp8_e4m3 val) {\n ((__nv_fp8x4_e4m3*)(&data.x))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e4m3*)(&data.y))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 8>::load(const __nv_fp8_e4m3* ptr) {\n data = *((uint2*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 8>::store(__nv_fp8_e4m3* ptr) const {\n *((uint2*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e4m3, 8>::memcpy(__nv_fp8_e4m3* dst,\n const __nv_fp8_e4m3* src) {\n *((uint2*)dst) = *((uint2*)src);\n}\n\n// __nv_fp8_e4m3 x 16 or more\ntemplate <size_t vec_size>\nstruct vec_t<__nv_fp8_e4m3, vec_size> {\n static_assert(vec_size % 16 == 0, \"Invalid vector size\");\n int4 data[vec_size / 16];\n\n FLASHINFER_INLINE __nv_fp8_e4m3& operator[](size_t i) { return ((__nv_fp8_e4m3*)data)[i]; }\n FLASHINFER_INLINE const __nv_fp8_e4m3& operator[](size_t i) const {\n return ((const __nv_fp8_e4m3*)data)[i];\n }\n FLASHINFER_INLINE __nv_fp8_e4m3* ptr() { return reinterpret_cast<__nv_fp8_e4m3*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e4m3 val) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((__nv_fp8x4_e4m3*)(&(data[i].x)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e4m3*)(&(data[i].y)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e4m3*)(&(data[i].z)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e4m3*)(&(data[i].w)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n }\n }\n FLASHINFER_INLINE void load(const __nv_fp8_e4m3* ptr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i] = ((int4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(__nv_fp8_e4m3* ptr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((int4*)ptr)[i] = data[i];\n }\n }\n FLASHINFER_INLINE void load_global_acquire(__nv_fp8_e4m3* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n *((int4*)(data + i)) = ld_global_acquire((int4*)(addr + i * 16));\n }\n }\n FLASHINFER_INLINE void store_global_release(__nv_fp8_e4m3* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n st_global_release(data[i], (int4*)(addr + i * 16));\n }\n }\n FLASHINFER_INLINE void load_global_volatile(__nv_fp8_e4m3* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i] = ld_global_volatile((int4*)(addr + i * 16));\n }\n }\n FLASHINFER_INLINE void store_global_volatile(__nv_fp8_e4m3* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n st_global_volatile(data[i], (int4*)(addr + i * 16));\n }\n }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e4m3* dst, const __nv_fp8_e4m3* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((int4*)dst)[i] = ((int4*)src)[i];\n }\n }\n};\n\n/******************* vec_t<__nv_fp8_e5m2> *******************/\n\n// __nv_fp8_e5m2 x 1\ntemplate <>\nstruct vec_t<__nv_fp8_e5m2, 1> {\n __nv_fp8_e5m2 data;\n\n FLASHINFER_INLINE __nv_fp8_e5m2& operator[](size_t i) { return ((__nv_fp8_e5m2*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e5m2& operator[](size_t i) const {\n return ((const __nv_fp8_e5m2*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e5m2* ptr() { return reinterpret_cast<__nv_fp8_e5m2*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e5m2 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e5m2* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e5m2* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 1>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e5m2* dst, const __nv_fp8_e5m2* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 1>::fill(__nv_fp8_e5m2 val) { data = val; }\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 1>::load(const __nv_fp8_e5m2* ptr) { data = *ptr; }\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 1>::store(__nv_fp8_e5m2* ptr) const { *ptr = data; }\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 1>::memcpy(__nv_fp8_e5m2* dst,\n const __nv_fp8_e5m2* src) {\n *dst = *src;\n}\n\n// __nv_fp8_e5m2 x 2\ntemplate <>\nstruct vec_t<__nv_fp8_e5m2, 2> {\n __nv_fp8x2_e5m2 data;\n\n FLASHINFER_INLINE __nv_fp8_e5m2& operator[](size_t i) { return ((__nv_fp8_e5m2*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e5m2& operator[](size_t i) const {\n return ((const __nv_fp8_e5m2*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e5m2* ptr() { return reinterpret_cast<__nv_fp8_e5m2*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e5m2 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e5m2* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e5m2* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 2>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e5m2* dst, const __nv_fp8_e5m2* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 2>::fill(__nv_fp8_e5m2 val) {\n data.__x = (__nv_fp8x2_storage_t(val.__x) << 8) | __nv_fp8x2_storage_t(val.__x);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 2>::load(const __nv_fp8_e5m2* ptr) {\n data = *((__nv_fp8x2_e5m2*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 2>::store(__nv_fp8_e5m2* ptr) const {\n *((__nv_fp8x2_e5m2*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 2>::memcpy(__nv_fp8_e5m2* dst,\n const __nv_fp8_e5m2* src) {\n *((__nv_fp8x2_e5m2*)dst) = *((__nv_fp8x2_e5m2*)src);\n}\n\n// __nv_fp8_e5m2 x 4\n\ntemplate <>\nstruct vec_t<__nv_fp8_e5m2, 4> {\n __nv_fp8x4_e5m2 data;\n\n FLASHINFER_INLINE __nv_fp8_e5m2& operator[](size_t i) { return ((__nv_fp8_e5m2*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e5m2& operator[](size_t i) const {\n return ((const __nv_fp8_e5m2*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e5m2* ptr() { return reinterpret_cast<__nv_fp8_e5m2*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e5m2 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e5m2* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e5m2* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 4>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e5m2* dst, const __nv_fp8_e5m2* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 4>::fill(__nv_fp8_e5m2 val) {\n data.__x = (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 4>::load(const __nv_fp8_e5m2* ptr) {\n data = *((__nv_fp8x4_e5m2*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 4>::store(__nv_fp8_e5m2* ptr) const {\n *((__nv_fp8x4_e5m2*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 4>::memcpy(__nv_fp8_e5m2* dst,\n const __nv_fp8_e5m2* src) {\n *((__nv_fp8x4_e5m2*)dst) = *((__nv_fp8x4_e5m2*)src);\n}\n\n// __nv_fp8_e5m2 x 8\n\ntemplate <>\nstruct vec_t<__nv_fp8_e5m2, 8> {\n uint2 data;\n\n FLASHINFER_INLINE __nv_fp8_e5m2& operator[](size_t i) { return ((__nv_fp8_e5m2*)(&data))[i]; }\n FLASHINFER_INLINE const __nv_fp8_e5m2& operator[](size_t i) const {\n return ((const __nv_fp8_e5m2*)(&data))[i];\n }\n FLASHINFER_INLINE __nv_fp8_e5m2* ptr() { return reinterpret_cast<__nv_fp8_e5m2*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e5m2 val);\n FLASHINFER_INLINE void load(const __nv_fp8_e5m2* ptr);\n FLASHINFER_INLINE void store(__nv_fp8_e5m2* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 8>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e5m2* dst, const __nv_fp8_e5m2* src);\n};\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 8>::fill(__nv_fp8_e5m2 val) {\n ((__nv_fp8x4_e5m2*)(&data.x))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e5m2*)(&data.y))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 8>::load(const __nv_fp8_e5m2* ptr) {\n data = *((uint2*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 8>::store(__nv_fp8_e5m2* ptr) const {\n *((uint2*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<__nv_fp8_e5m2, 8>::memcpy(__nv_fp8_e5m2* dst,\n const __nv_fp8_e5m2* src) {\n *((uint2*)dst) = *((uint2*)src);\n}\n\n// __nv_fp8_e5m2 x 16 or more\n\ntemplate <size_t vec_size>\nstruct vec_t<__nv_fp8_e5m2, vec_size> {\n static_assert(vec_size % 16 == 0, \"Invalid vector size\");\n int4 data[vec_size / 16];\n\n FLASHINFER_INLINE __nv_fp8_e5m2& operator[](size_t i) { return ((__nv_fp8_e5m2*)data)[i]; }\n FLASHINFER_INLINE const __nv_fp8_e5m2& operator[](size_t i) const {\n return ((const __nv_fp8_e5m2*)data)[i];\n }\n FLASHINFER_INLINE __nv_fp8_e5m2* ptr() { return reinterpret_cast<__nv_fp8_e5m2*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp8_e5m2 val) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((__nv_fp8x4_e5m2*)(&(data[i].x)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e5m2*)(&(data[i].y)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e5m2*)(&(data[i].z)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n ((__nv_fp8x4_e5m2*)(&(data[i].w)))->__x =\n (__nv_fp8x4_storage_t(val.__x) << 24) | (__nv_fp8x4_storage_t(val.__x) << 16) |\n (__nv_fp8x4_storage_t(val.__x) << 8) | __nv_fp8x4_storage_t(val.__x);\n }\n }\n FLASHINFER_INLINE void load(const __nv_fp8_e5m2* ptr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i] = ((int4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(__nv_fp8_e5m2* ptr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((int4*)ptr)[i] = data[i];\n }\n }\n FLASHINFER_INLINE void store_global_release(__nv_fp8_e5m2* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n st_global_release(data[i], (int4*)(addr + i * 16));\n }\n }\n FLASHINFER_INLINE void load_global_acquire(__nv_fp8_e5m2* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i] = ld_global_acquire((int4*)(addr + i * 16));\n }\n }\n FLASHINFER_INLINE void store_global_volatile(__nv_fp8_e5m2* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n st_global_volatile(data[i], (int4*)(addr + i * 16));\n }\n }\n FLASHINFER_INLINE void load_global_volatile(__nv_fp8_e5m2* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i] = ld_global_volatile((int4*)(addr + i * 16));\n }\n }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(__nv_fp8_e5m2* dst, const __nv_fp8_e5m2* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((int4*)dst)[i] = ((int4*)src)[i];\n }\n }\n};\n\n#if defined(FLASHINFER_ENABLE_FP4_E2M1) && CUDA_VERSION >= 12080\n/******************* vec_t<__nv_fp4x2_e2m1> *******************/\n\n// __nv_fp4x2_e2m1 is used as a one-byte packed container for FP4 KV-cache data.\n// The current FA2 NVFP4 path stores valid packed bytes at even positions and padding at odd\n// positions, so vec_size still counts logical elements in the surrounding kernels.\ntemplate <size_t vec_size>\nstruct vec_t<__nv_fp4x2_e2m1, vec_size> {\n static_assert(vec_size % 16 == 0, \"Invalid vector size\");\n int4 data[vec_size / 16];\n\n FLASHINFER_INLINE __nv_fp4x2_e2m1& operator[](size_t i) { return ((__nv_fp4x2_e2m1*)data)[i]; }\n FLASHINFER_INLINE const __nv_fp4x2_e2m1& operator[](size_t i) const {\n return ((const __nv_fp4x2_e2m1*)data)[i];\n }\n FLASHINFER_INLINE __nv_fp4x2_e2m1* ptr() { return reinterpret_cast<__nv_fp4x2_e2m1*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp4x2_e2m1 val) {\n uint32_t val8 = __nv_fp4x2_storage_t(val.__x);\n uint32_t val16 = (val8 << 8) | val8;\n uint32_t val32 = (val16 << 16) | val16;\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i].x = val32;\n data[i].y = val32;\n data[i].z = val32;\n data[i].w = val32;\n }\n }\n FLASHINFER_INLINE void load(const __nv_fp4x2_e2m1* ptr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i] = ((int4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(__nv_fp4x2_e2m1* ptr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((int4*)ptr)[i] = data[i];\n }\n }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(__nv_fp4x2_e2m1* dst, const __nv_fp4x2_e2m1* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((int4*)dst)[i] = ((int4*)src)[i];\n }\n }\n};\n\n/******************* vec_t<__nv_fp4_e2m1> *******************/\n\n// __nv_fp4_e2m1 x 2\ntemplate <>\nstruct vec_t<__nv_fp4_e2m1, 2> {\n uint8_t data;\n // index access is not supported for sub-byte data type\n FLASHINFER_INLINE __nv_fp4_e2m1* ptr() { return reinterpret_cast<__nv_fp4_e2m1*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp4_e2m1 val) {\n data = (__nv_fp4x2_storage_t(val.__x) << 4) | __nv_fp4x2_storage_t(val.__x);\n }\n FLASHINFER_INLINE void load(const __nv_fp4_e2m1* ptr) { data = *((uint8_t*)ptr); }\n FLASHINFER_INLINE void store(__nv_fp4_e2m1* ptr) const { *((uint8_t*)ptr) = data; }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 2>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(__nv_fp4_e2m1* dst, const __nv_fp4_e2m1* src) {\n *((uint8_t*)dst) = *((uint8_t*)src);\n }\n};\n\n// __nv_fp4_e2m1 x 4\ntemplate <>\nstruct vec_t<__nv_fp4_e2m1, 4> {\n uint16_t data;\n\n FLASHINFER_INLINE __nv_fp4_e2m1* ptr() { return reinterpret_cast<__nv_fp4_e2m1*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp4_e2m1 val) {\n __nv_fp4x2_storage_t val8 =\n (__nv_fp4x2_storage_t(val.__x) << 4) | __nv_fp4x2_storage_t(val.__x);\n data = (uint16_t(val8) << 8) | uint16_t(val8);\n }\n FLASHINFER_INLINE void load(const __nv_fp4_e2m1* ptr) { data = *((uint16_t*)ptr); }\n FLASHINFER_INLINE void store(__nv_fp4_e2m1* ptr) const { *((uint16_t*)ptr) = data; }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 4>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(__nv_fp4_e2m1* dst, const __nv_fp4_e2m1* src) {\n *((uint16_t*)dst) = *((uint16_t*)src);\n }\n};\n\n// __nv_fp4_e2m1 x 8\ntemplate <>\nstruct vec_t<__nv_fp4_e2m1, 8> {\n uint32_t data;\n\n FLASHINFER_INLINE __nv_fp4_e2m1* ptr() { return reinterpret_cast<__nv_fp4_e2m1*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp4_e2m1 val) {\n __nv_fp4x2_storage_t val8 =\n (__nv_fp4x2_storage_t(val.__x) << 4) | __nv_fp4x2_storage_t(val.__x);\n uint16_t val16 = (uint16_t(val8) << 8) | uint16_t(val8);\n data = (uint32_t(val16) << 16) | uint32_t(val16);\n }\n FLASHINFER_INLINE void load(const __nv_fp4_e2m1* ptr) { data = *((uint32_t*)ptr); }\n FLASHINFER_INLINE void store(__nv_fp4_e2m1* ptr) const { *((uint32_t*)ptr) = data; }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 8>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(__nv_fp4_e2m1* dst, const __nv_fp4_e2m1* src) {\n *((uint32_t*)dst) = *((uint32_t*)src);\n }\n};\n\ntemplate <>\nstruct vec_t<__nv_fp4_e2m1, 16> {\n uint2 data;\n FLASHINFER_INLINE __nv_fp4_e2m1* ptr() { return reinterpret_cast<__nv_fp4_e2m1*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp4_e2m1 val) {\n __nv_fp4x2_storage_t val8 =\n (__nv_fp4x2_storage_t(val.__x) << 4) | __nv_fp4x2_storage_t(val.__x);\n uint16_t val16 = (uint16_t(val8) << 8) | uint16_t(val8);\n uint32_t val32 = (uint32_t(val16) << 16) | uint32_t(val16);\n data.x = val32;\n data.y = val32;\n }\n FLASHINFER_INLINE void load(const __nv_fp4_e2m1* ptr) { data = *((uint2*)ptr); }\n FLASHINFER_INLINE void store(__nv_fp4_e2m1* ptr) const { *((uint2*)ptr) = data; }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 16>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(__nv_fp4_e2m1* dst, const __nv_fp4_e2m1* src) {\n *((uint2*)dst) = *((uint2*)src);\n }\n};\n\n// __nv_fp4_e2m1 x 32 or more\ntemplate <size_t vec_size>\nstruct vec_t<__nv_fp4_e2m1, vec_size> {\n static_assert(vec_size % 32 == 0, \"Invalid vector size\");\n int4 data[vec_size / 32];\n\n FLASHINFER_INLINE __nv_fp4_e2m1* ptr() { return reinterpret_cast<__nv_fp4_e2m1*>(&data); }\n FLASHINFER_INLINE void fill(__nv_fp4_e2m1 val) {\n __nv_fp4x2_storage_t val8 =\n (__nv_fp4x2_storage_t(val.__x) << 4) | __nv_fp4x2_storage_t(val.__x);\n uint16_t val16 = (uint16_t(val8) << 8) | uint16_t(val8);\n uint32_t val32 = (uint32_t(val16) << 16) | uint32_t(val16);\n#pragma unroll\n for (size_t i = 0; i < vec_size / 32; ++i) {\n data[i].x = val32;\n data[i].y = val32;\n data[i].z = val32;\n data[i].w = val32;\n }\n }\n FLASHINFER_INLINE void load(const __nv_fp4_e2m1* ptr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 32; ++i) {\n data[i] = ((int4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(__nv_fp4_e2m1* ptr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 32; ++i) {\n ((int4*)ptr)[i] = data[i];\n }\n }\n FLASHINFER_INLINE void store_global_release(__nv_fp4_e2m1* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 32; ++i) {\n st_global_release(*(int4*)&data[i], (int4*)(addr + i * 16));\n }\n }\n FLASHINFER_INLINE void load_global_acquire(__nv_fp4_e2m1* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 32; ++i) {\n *(int4*)&data[i] = ld_global_acquire((int4*)(addr + i * 16));\n }\n }\n FLASHINFER_INLINE void store_global_volatile(__nv_fp4_e2m1* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 32; ++i) {\n st_global_volatile(*(int4*)&data[i], (int4*)(addr + i * 16));\n }\n }\n FLASHINFER_INLINE void load_global_volatile(__nv_fp4_e2m1* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 32; ++i) {\n *(int4*)&data[i] = ld_global_volatile((int4*)(addr + i * 16));\n }\n }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(__nv_fp4_e2m1* dst, const __nv_fp4_e2m1* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 32; ++i) {\n ((int4*)dst)[i] = ((int4*)src)[i];\n }\n }\n};\n\n#endif // FLASHINFER_ENABLE_FP4_E2M1 && CUDA_VERSION >= 12080\n\n/******************* vec_t<half> *******************/\n\n// half x 1\ntemplate <>\nstruct vec_t<half, 1> {\n half data;\n\n FLASHINFER_INLINE half& operator[](size_t i) { return ((half*)(&data))[i]; }\n FLASHINFER_INLINE const half& operator[](size_t i) const { return ((const half*)(&data))[i]; }\n FLASHINFER_INLINE half* ptr() { return reinterpret_cast<half*>(&data); }\n FLASHINFER_INLINE void fill(half val);\n FLASHINFER_INLINE void load(const half* ptr);\n FLASHINFER_INLINE void store(half* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 1>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(half* dst, const half* src);\n};\n\nFLASHINFER_INLINE void vec_t<half, 1>::fill(half val) { data = val; }\n\nFLASHINFER_INLINE void vec_t<half, 1>::load(const half* ptr) { data = *ptr; }\n\nFLASHINFER_INLINE void vec_t<half, 1>::store(half* ptr) const { *ptr = data; }\n\nFLASHINFER_INLINE void vec_t<half, 1>::memcpy(half* dst, const half* src) { *dst = *src; }\n\n// half x 2\ntemplate <>\nstruct vec_t<half, 2> {\n half2 data;\n\n FLASHINFER_INLINE half& operator[](size_t i) { return ((half*)(&data))[i]; }\n FLASHINFER_INLINE const half& operator[](size_t i) const { return ((const half*)(&data))[i]; }\n FLASHINFER_INLINE half* ptr() { return reinterpret_cast<half*>(&data); }\n FLASHINFER_INLINE void fill(half val);\n FLASHINFER_INLINE void load(const half* ptr);\n FLASHINFER_INLINE void store(half* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 2>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(half* dst, const half* src);\n};\n\nFLASHINFER_INLINE void vec_t<half, 2>::fill(half val) { data = make_half2(val, val); }\n\nFLASHINFER_INLINE void vec_t<half, 2>::load(const half* ptr) { data = *((half2*)ptr); }\n\nFLASHINFER_INLINE void vec_t<half, 2>::store(half* ptr) const { *((half2*)ptr) = data; }\n\nFLASHINFER_INLINE void vec_t<half, 2>::memcpy(half* dst, const half* src) {\n *((half2*)dst) = *((half2*)src);\n}\n\n// half x 4\n\ntemplate <>\nstruct vec_t<half, 4> {\n uint2 data;\n\n FLASHINFER_INLINE half& operator[](size_t i) { return ((half*)(&data))[i]; }\n FLASHINFER_INLINE const half& operator[](size_t i) const { return ((const half*)(&data))[i]; }\n FLASHINFER_INLINE half* ptr() { return reinterpret_cast<half*>(&data); }\n FLASHINFER_INLINE void fill(half val);\n FLASHINFER_INLINE void load(const half* ptr);\n FLASHINFER_INLINE void store(half* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 4>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(half* dst, const half* src);\n};\n\nFLASHINFER_INLINE void vec_t<half, 4>::fill(half val) {\n *(half2*)(&data.x) = make_half2(val, val);\n *(half2*)(&data.y) = make_half2(val, val);\n}\n\nFLASHINFER_INLINE void vec_t<half, 4>::load(const half* ptr) { data = *((uint2*)ptr); }\n\nFLASHINFER_INLINE void vec_t<half, 4>::store(half* ptr) const { *((uint2*)ptr) = data; }\n\nFLASHINFER_INLINE void vec_t<half, 4>::memcpy(half* dst, const half* src) {\n *((uint2*)dst) = *((uint2*)src);\n}\n\n// half x 8 or more\n\ntemplate <size_t vec_size>\nstruct vec_t<half, vec_size> {\n static_assert(vec_size % 8 == 0, \"Invalid vector size\");\n int4 data[vec_size / 8];\n FLASHINFER_INLINE half& operator[](size_t i) { return ((half*)data)[i]; }\n FLASHINFER_INLINE const half& operator[](size_t i) const { return ((const half*)data)[i]; }\n FLASHINFER_INLINE half* ptr() { return reinterpret_cast<half*>(&data); }\n FLASHINFER_INLINE void fill(half val) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n *(half2*)(&(data[i].x)) = make_half2(val, val);\n *(half2*)(&(data[i].y)) = make_half2(val, val);\n *(half2*)(&(data[i].z)) = make_half2(val, val);\n *(half2*)(&(data[i].w)) = make_half2(val, val);\n }\n }\n FLASHINFER_INLINE void load(const half* ptr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n data[i] = ((int4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(half* ptr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n ((int4*)ptr)[i] = data[i];\n }\n }\n FLASHINFER_INLINE void load_global_acquire(half* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n data[i] = ld_global_acquire((int4*)(addr + i * 8));\n }\n }\n FLASHINFER_INLINE void store_global_release(half* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n st_global_release(data[i], (int4*)(addr + i * 8));\n }\n }\n FLASHINFER_INLINE void store_global_volatile(half* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n st_global_volatile(data[i], (int4*)(addr + i * 8));\n }\n }\n FLASHINFER_INLINE void load_global_volatile(half* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n data[i] = ld_global_volatile((int4*)(addr + i * 8));\n }\n }\n\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(half* dst, const half* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n ((int4*)dst)[i] = ((int4*)src)[i];\n }\n }\n};\n\n/******************* vec_t<nv_bfloat16> *******************/\n\n// nv_bfloat16 x 1\ntemplate <>\nstruct vec_t<nv_bfloat16, 1> {\n nv_bfloat16 data;\n FLASHINFER_INLINE nv_bfloat16& operator[](size_t i) { return ((nv_bfloat16*)(&data))[i]; }\n FLASHINFER_INLINE const nv_bfloat16& operator[](size_t i) const {\n return ((const nv_bfloat16*)(&data))[i];\n }\n FLASHINFER_INLINE nv_bfloat16* ptr() { return reinterpret_cast<nv_bfloat16*>(&data); }\n FLASHINFER_INLINE void fill(nv_bfloat16 val);\n FLASHINFER_INLINE void load(const nv_bfloat16* ptr);\n FLASHINFER_INLINE void store(nv_bfloat16* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 1>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(nv_bfloat16* dst, const nv_bfloat16* src);\n};\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 1>::fill(nv_bfloat16 val) { data = val; }\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 1>::load(const nv_bfloat16* ptr) { data = *ptr; }\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 1>::store(nv_bfloat16* ptr) const { *ptr = data; }\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 1>::memcpy(nv_bfloat16* dst, const nv_bfloat16* src) {\n *dst = *src;\n}\n\n// nv_bfloat16 x 2\ntemplate <>\nstruct vec_t<nv_bfloat16, 2> {\n nv_bfloat162 data;\n\n FLASHINFER_INLINE nv_bfloat16& operator[](size_t i) { return ((nv_bfloat16*)(&data))[i]; }\n FLASHINFER_INLINE const nv_bfloat16& operator[](size_t i) const {\n return ((const nv_bfloat16*)(&data))[i];\n }\n FLASHINFER_INLINE nv_bfloat16* ptr() { return reinterpret_cast<nv_bfloat16*>(&data); }\n FLASHINFER_INLINE void fill(nv_bfloat16 val);\n FLASHINFER_INLINE void load(const nv_bfloat16* ptr);\n FLASHINFER_INLINE void store(nv_bfloat16* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 2>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(nv_bfloat16* dst, const nv_bfloat16* src);\n};\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 2>::fill(nv_bfloat16 val) {\n data = make_bfloat162(val, val);\n}\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 2>::load(const nv_bfloat16* ptr) {\n data = *((nv_bfloat162*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 2>::store(nv_bfloat16* ptr) const {\n *((nv_bfloat162*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 2>::memcpy(nv_bfloat16* dst, const nv_bfloat16* src) {\n *((nv_bfloat162*)dst) = *((nv_bfloat162*)src);\n}\n\n// nv_bfloat16 x 4\n\ntemplate <>\nstruct vec_t<nv_bfloat16, 4> {\n uint2 data;\n\n FLASHINFER_INLINE nv_bfloat16& operator[](size_t i) { return ((nv_bfloat16*)(&data))[i]; }\n FLASHINFER_INLINE const nv_bfloat16& operator[](size_t i) const {\n return ((const nv_bfloat16*)(&data))[i];\n }\n FLASHINFER_INLINE nv_bfloat16* ptr() { return reinterpret_cast<nv_bfloat16*>(&data); }\n FLASHINFER_INLINE void fill(nv_bfloat16 val);\n FLASHINFER_INLINE void load(const nv_bfloat16* ptr);\n FLASHINFER_INLINE void store(nv_bfloat16* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 4>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(nv_bfloat16* dst, const nv_bfloat16* src);\n};\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 4>::fill(nv_bfloat16 val) {\n *(nv_bfloat162*)(&data.x) = make_bfloat162(val, val);\n *(nv_bfloat162*)(&data.y) = make_bfloat162(val, val);\n}\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 4>::load(const nv_bfloat16* ptr) {\n data = *((uint2*)ptr);\n}\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 4>::store(nv_bfloat16* ptr) const {\n *((uint2*)ptr) = data;\n}\n\nFLASHINFER_INLINE void vec_t<nv_bfloat16, 4>::memcpy(nv_bfloat16* dst, const nv_bfloat16* src) {\n *((uint2*)dst) = *((uint2*)src);\n}\n\n// nv_bfloat16 x 8 or more\n\ntemplate <size_t vec_size>\nstruct vec_t<nv_bfloat16, vec_size> {\n static_assert(vec_size % 8 == 0, \"Invalid vector size\");\n int4 data[vec_size / 8];\n\n FLASHINFER_INLINE nv_bfloat16& operator[](size_t i) { return ((nv_bfloat16*)data)[i]; }\n FLASHINFER_INLINE const nv_bfloat16& operator[](size_t i) const {\n return ((const nv_bfloat16*)data)[i];\n }\n FLASHINFER_INLINE nv_bfloat16* ptr() { return reinterpret_cast<nv_bfloat16*>(&data); }\n FLASHINFER_INLINE void fill(nv_bfloat16 val) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n *(nv_bfloat162*)(&(data[i].x)) = make_bfloat162(val, val);\n *(nv_bfloat162*)(&(data[i].y)) = make_bfloat162(val, val);\n *(nv_bfloat162*)(&(data[i].z)) = make_bfloat162(val, val);\n *(nv_bfloat162*)(&(data[i].w)) = make_bfloat162(val, val);\n }\n }\n FLASHINFER_INLINE void load(const nv_bfloat16* ptr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n data[i] = ((int4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(nv_bfloat16* ptr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n ((int4*)ptr)[i] = data[i];\n }\n }\n FLASHINFER_INLINE void store_global_release(nv_bfloat16* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n st_global_release(data[i], (int4*)(addr + i * 8));\n }\n }\n FLASHINFER_INLINE void load_global_acquire(nv_bfloat16* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n data[i] = ld_global_acquire((int4*)(addr + i * 8));\n }\n }\n FLASHINFER_INLINE void store_global_volatile(nv_bfloat16* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n st_global_volatile(data[i], (int4*)(addr + i * 8));\n }\n }\n FLASHINFER_INLINE void load_global_volatile(nv_bfloat16* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n data[i] = ld_global_volatile((int4*)(addr + i * 8));\n }\n }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(nv_bfloat16* dst, const nv_bfloat16* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 8; ++i) {\n ((int4*)dst)[i] = ((int4*)src)[i];\n }\n }\n};\n\n/******************* vec_t<uint8_t> *******************/\n\n// uint8_t x 1\ntemplate <>\nstruct vec_t<uint8_t, 1> {\n uint8_t data;\n\n FLASHINFER_INLINE uint8_t& operator[](size_t i) { return ((uint8_t*)(&data))[i]; }\n FLASHINFER_INLINE const uint8_t& operator[](size_t i) const {\n return ((const uint8_t*)(&data))[i];\n }\n FLASHINFER_INLINE uint8_t* ptr() { return reinterpret_cast<uint8_t*>(&data); }\n FLASHINFER_INLINE void fill(uint8_t val);\n FLASHINFER_INLINE void load(const uint8_t* ptr);\n FLASHINFER_INLINE void store(uint8_t* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 1>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(uint8_t* dst, const uint8_t* src);\n};\n\nFLASHINFER_INLINE void vec_t<uint8_t, 1>::fill(uint8_t val) { data = val; }\n\nFLASHINFER_INLINE void vec_t<uint8_t, 1>::load(const uint8_t* ptr) { data = *ptr; }\n\nFLASHINFER_INLINE void vec_t<uint8_t, 1>::store(uint8_t* ptr) const { *ptr = data; }\n\nFLASHINFER_INLINE void vec_t<uint8_t, 1>::memcpy(uint8_t* dst, const uint8_t* src) { *dst = *src; }\n\n// uint8_t x 2\ntemplate <>\nstruct vec_t<uint8_t, 2> {\n uint16_t data;\n\n FLASHINFER_INLINE uint8_t& operator[](size_t i) { return ((uint8_t*)(&data))[i]; }\n FLASHINFER_INLINE const uint8_t& operator[](size_t i) const {\n return ((const uint8_t*)(&data))[i];\n }\n FLASHINFER_INLINE uint8_t* ptr() { return reinterpret_cast<uint8_t*>(&data); }\n FLASHINFER_INLINE void fill(uint8_t val);\n FLASHINFER_INLINE void load(const uint8_t* ptr);\n FLASHINFER_INLINE void store(uint8_t* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 2>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(uint8_t* dst, const uint8_t* src);\n};\n\nFLASHINFER_INLINE void vec_t<uint8_t, 2>::fill(uint8_t val) {\n data = (uint16_t(val) << 8) | uint16_t(val);\n}\n\nFLASHINFER_INLINE void vec_t<uint8_t, 2>::load(const uint8_t* ptr) { data = *((uint16_t*)ptr); }\n\nFLASHINFER_INLINE void vec_t<uint8_t, 2>::store(uint8_t* ptr) const { *((uint16_t*)ptr) = data; }\n\nFLASHINFER_INLINE void vec_t<uint8_t, 2>::memcpy(uint8_t* dst, const uint8_t* src) {\n *((uint16_t*)dst) = *((uint16_t*)src);\n}\n\n// uint8_t x 4\n\ntemplate <>\nstruct vec_t<uint8_t, 4> {\n uint32_t data;\n\n FLASHINFER_INLINE uint8_t& operator[](size_t i) { return ((uint8_t*)(&data))[i]; }\n FLASHINFER_INLINE const uint8_t& operator[](size_t i) const {\n return ((const uint8_t*)(&data))[i];\n }\n FLASHINFER_INLINE uint8_t* ptr() { return reinterpret_cast<uint8_t*>(&data); }\n FLASHINFER_INLINE void fill(uint8_t val);\n FLASHINFER_INLINE void load(const uint8_t* ptr);\n FLASHINFER_INLINE void store(uint8_t* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 4>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n\n FLASHINFER_INLINE static void memcpy(uint8_t* dst, const uint8_t* src);\n};\n\nFLASHINFER_INLINE void vec_t<uint8_t, 4>::fill(uint8_t val) {\n data = (uint32_t(val) << 24) | (uint32_t(val) << 16) | (uint32_t(val) << 8) | uint32_t(val);\n}\n\nFLASHINFER_INLINE void vec_t<uint8_t, 4>::load(const uint8_t* ptr) { data = *((uint32_t*)ptr); }\n\nFLASHINFER_INLINE void vec_t<uint8_t, 4>::store(uint8_t* ptr) const { *((uint32_t*)ptr) = data; }\n\nFLASHINFER_INLINE void vec_t<uint8_t, 4>::memcpy(uint8_t* dst, const uint8_t* src) {\n *((uint32_t*)dst) = *((uint32_t*)src);\n}\n\n// uint8_t x 8\n\ntemplate <>\nstruct vec_t<uint8_t, 8> {\n uint2 data;\n\n FLASHINFER_INLINE uint8_t& operator[](size_t i) { return ((uint8_t*)(&data))[i]; }\n FLASHINFER_INLINE const uint8_t& operator[](size_t i) const {\n return ((const uint8_t*)(&data))[i];\n }\n FLASHINFER_INLINE uint8_t* ptr() { return reinterpret_cast<uint8_t*>(&data); }\n FLASHINFER_INLINE void fill(uint8_t val);\n FLASHINFER_INLINE void load(const uint8_t* ptr);\n FLASHINFER_INLINE void store(uint8_t* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 8>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(uint8_t* dst, const uint8_t* src);\n};\n\nFLASHINFER_INLINE void vec_t<uint8_t, 8>::fill(uint8_t val) {\n uint32_t val32 =\n (uint32_t(val) << 24) | (uint32_t(val) << 16) | (uint32_t(val) << 8) | uint32_t(val);\n data.x = val32;\n data.y = val32;\n}\n\nFLASHINFER_INLINE void vec_t<uint8_t, 8>::load(const uint8_t* ptr) { data = *((uint2*)ptr); }\n\nFLASHINFER_INLINE void vec_t<uint8_t, 8>::store(uint8_t* ptr) const { *((uint2*)ptr) = data; }\n\nFLASHINFER_INLINE void vec_t<uint8_t, 8>::memcpy(uint8_t* dst, const uint8_t* src) {\n *((uint2*)dst) = *((uint2*)src);\n}\n\n// uint8_t x 16 or more\n\ntemplate <size_t vec_size>\nstruct vec_t<uint8_t, vec_size> {\n static_assert(vec_size % 16 == 0, \"Invalid vector size\");\n int4 data[vec_size / 16];\n\n FLASHINFER_INLINE uint8_t& operator[](size_t i) { return ((uint8_t*)data)[i]; }\n FLASHINFER_INLINE const uint8_t& operator[](size_t i) const { return ((const uint8_t*)data)[i]; }\n FLASHINFER_INLINE uint8_t* ptr() { return reinterpret_cast<uint8_t*>(&data); }\n FLASHINFER_INLINE void fill(uint8_t val) {\n uint32_t val32 =\n (uint32_t(val) << 24) | (uint32_t(val) << 16) | (uint32_t(val) << 8) | uint32_t(val);\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i].x = val32;\n data[i].y = val32;\n data[i].z = val32;\n data[i].w = val32;\n }\n }\n FLASHINFER_INLINE void load(const uint8_t* ptr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i] = ((int4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(uint8_t* ptr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((int4*)ptr)[i] = data[i];\n }\n }\n FLASHINFER_INLINE void load_global_acquire(uint8_t* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i] = ld_global_acquire((int4*)(addr + i * 16));\n }\n }\n FLASHINFER_INLINE void store_global_release(uint8_t* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n st_global_release(data[i], (int4*)(addr + i * 16));\n }\n }\n FLASHINFER_INLINE void load_global_volatile(uint8_t* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n data[i] = ld_global_volatile((int4*)(addr + i * 16));\n }\n }\n FLASHINFER_INLINE void store_global_volatile(uint8_t* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n st_global_volatile(data[i], (int4*)(addr + i * 16));\n }\n }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(uint8_t* dst, const uint8_t* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 16; ++i) {\n ((int4*)dst)[i] = ((int4*)src)[i];\n }\n }\n};\n\n/******************* vec_t<float> *******************/\n\n// float x 1\n\ntemplate <>\nstruct vec_t<float, 1> {\n float data;\n\n FLASHINFER_INLINE float& operator[](size_t i) { return ((float*)(&data))[i]; }\n FLASHINFER_INLINE const float& operator[](size_t i) const { return ((const float*)(&data))[i]; }\n FLASHINFER_INLINE float* ptr() { return reinterpret_cast<float*>(&data); }\n FLASHINFER_INLINE void fill(float val);\n FLASHINFER_INLINE void load(const float* ptr);\n FLASHINFER_INLINE void store(float* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 1>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(float* dst, const float* src);\n};\n\nFLASHINFER_INLINE void vec_t<float, 1>::fill(float val) { data = val; }\n\nFLASHINFER_INLINE void vec_t<float, 1>::load(const float* ptr) { data = *ptr; }\n\nFLASHINFER_INLINE void vec_t<float, 1>::store(float* ptr) const { *ptr = data; }\n\nFLASHINFER_INLINE void vec_t<float, 1>::memcpy(float* dst, const float* src) { *dst = *src; }\n\n// float x 2\n\ntemplate <>\nstruct vec_t<float, 2> {\n float2 data;\n\n FLASHINFER_INLINE float& operator[](size_t i) { return ((float*)(&data))[i]; }\n FLASHINFER_INLINE const float& operator[](size_t i) const { return ((const float*)(&data))[i]; }\n FLASHINFER_INLINE float* ptr() { return reinterpret_cast<float*>(&data); }\n FLASHINFER_INLINE void fill(float val);\n FLASHINFER_INLINE void load(const float* ptr);\n FLASHINFER_INLINE void store(float* ptr) const;\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, 2>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(float* dst, const float* src);\n};\n\nFLASHINFER_INLINE void vec_t<float, 2>::fill(float val) { data = make_float2(val, val); }\n\nFLASHINFER_INLINE void vec_t<float, 2>::load(const float* ptr) { data = *((float2*)ptr); }\n\nFLASHINFER_INLINE void vec_t<float, 2>::store(float* ptr) const { *((float2*)ptr) = data; }\n\nFLASHINFER_INLINE void vec_t<float, 2>::memcpy(float* dst, const float* src) {\n *((float2*)dst) = *((float2*)src);\n}\n\n// float x 4 or more\ntemplate <size_t vec_size>\nstruct vec_t<float, vec_size> {\n static_assert(vec_size % 4 == 0, \"Invalid vector size\");\n float4 data[vec_size / 4];\n\n FLASHINFER_INLINE float& operator[](size_t i) { return ((float*)(data))[i]; }\n FLASHINFER_INLINE const float& operator[](size_t i) const { return ((const float*)(data))[i]; }\n FLASHINFER_INLINE float* ptr() { return reinterpret_cast<float*>(&data); }\n FLASHINFER_INLINE void fill(float val) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 4; ++i) {\n data[i] = make_float4(val, val, val, val);\n }\n }\n FLASHINFER_INLINE void load(const float* ptr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 4; ++i) {\n data[i] = ((float4*)ptr)[i];\n }\n }\n FLASHINFER_INLINE void store(float* ptr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 4; ++i) {\n ((float4*)ptr)[i] = data[i];\n }\n }\n FLASHINFER_INLINE void store_global_release(float* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 4; ++i) {\n st_global_release(*(int4*)(data + i), (int4*)(addr + i * 4));\n }\n }\n FLASHINFER_INLINE void load_global_acquire(float* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 4; ++i) {\n *((int4*)(data + i)) = ld_global_acquire((int4*)(addr + i * 4));\n }\n }\n FLASHINFER_INLINE void store_global_volatile(float* addr) const {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 4; ++i) {\n st_global_volatile(*(int4*)(data + i), (int4*)(addr + i * 4));\n }\n }\n FLASHINFER_INLINE void load_global_volatile(float* addr) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 4; ++i) {\n *((int4*)(data + i)) = ld_global_volatile((int4*)(addr + i * 4));\n }\n }\n template <typename T>\n FLASHINFER_INLINE void cast_from(const vec_t<T, vec_size>& src) {\n cast_from_impl(*this, src);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_load(const T* ptr) {\n cast_load_impl(*this, ptr);\n }\n template <typename T>\n FLASHINFER_INLINE void cast_store(T* ptr) const {\n cast_store_impl(ptr, *this);\n }\n FLASHINFER_INLINE static void memcpy(float* dst, const float* src) {\n#pragma unroll\n for (size_t i = 0; i < vec_size / 4; ++i) {\n ((float4*)dst)[i] = ((float4*)src)[i];\n }\n }\n};\n\ntemplate <typename T>\nstruct vec2_dtype {\n using type = T;\n};\n\ntemplate <>\nstruct vec2_dtype<half> {\n using type = half2;\n};\n\ntemplate <>\nstruct vec2_dtype<__nv_bfloat16> {\n using type = __nv_bfloat162;\n};\n\ntemplate <>\nstruct vec2_dtype<__nv_fp8_e4m3> {\n using type = __nv_fp8x2_e4m3;\n};\n\ntemplate <>\nstruct vec2_dtype<__nv_fp8_e5m2> {\n using type = __nv_fp8x2_e5m2;\n};\n\ntemplate <typename T>\nusing vec2_dtype_t = typename vec2_dtype<T>::type;\n\ntemplate <typename T, size_t VEC_SIZE>\nFLASHINFER_INLINE vec2_dtype_t<T> get_vec2_element(vec_t<T, VEC_SIZE>& vec, int i) {\n static_assert(VEC_SIZE % 2 == 0, \"VEC_SIZE must be a multiple of 2\");\n return ((vec2_dtype_t<T>*)&(vec[0]))[i];\n}\n\n} // namespace flashinfer\n\n#endif // VEC_DTYPES_CUH_\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\nNVFP4 KV cache works on pre-SM100 but was never performance-tuned there. On sm_80 (head_dim 128, 32/8 heads, page_size 16) NVFP4 KV costs **6.8–8.2x FP8 KV in prefill and 4.4–5.4x in decode**, even though it reads *half* the bytes FP8 does. FP8 KV — which also dequantizes — is essentially free on the same hardware, so the gap is not \"quantized KV is slow\", it is specific to the FP4 path.\n\n`ncu` says why. At identical shapes the NVFP4 and FP16 kernels have the **same launch config, same occupancy, same MMA instruction count, and the same number of `ldmatrix`**; the only difference is that NVFP4 executes **6.75x more instructions** (249.6M vs 36.97M). DRAM throughput is 0.36% of peak — it is not memory-bound, it is instruction-bound. The extra 212.7M instructions are 30% `LOP3`, 14% `PRMT`, 14% `IMAD`, 8% `SHF` — the bit-manipulation signature of dequantization — plus 13% branch opcodes (`ISETP`/`BRA`/`BSSY`/`BSYNC`), which turned out to be the most actionable part.\n\n#4769 stacks on this PR: its NVFP4 tile repack calls the `e2m1x8_to_f16x8` / `e2m1x8_to_bf16x8` helpers and `nvfp4_sf4_to_packed2x2` added here, so its diff carries these commits until this one lands.\n\nThis PR is four changes, each gated to the targets that actually lack the corresponding hardware instruction. All of them produce bit-identical output, with one documented exception in the scale-factor conversion covered under \"Known behavioral difference\" below.\n\n**1. `vec_dtypes.cuh`: the arch<SM100 `vec_cast<half|nv_bfloat16, __nv_fp4x2_e2m1>` fallback indexed a function-local `constexpr uint16_t lut[16]`.** nvcc puts that array in **local memory**: SASS shows `STL.128` x2 re-storing the table to the thread stack on *every inlined call*, one dependent `LDL.U16` per element, and a 32-byte stack frame in every kernel that inlines it.\n\nReplaced with a register-only `prmt` path. The FP16 encodings of the eight E2M1 magnitudes {0, .5, 1, 1.5, 2, 3, 4, 6} are {0x0000, 0x3800, 0x3C00, 0x3E00, 0x4000, 0x4200, 0x4400, 0x4600} — **every low byte is zero**, so the whole magnitude table is eight distinct high bytes, which is exactly what one `prmt` indexes from its two source registers. BF16 magnitudes have a varying low byte, so that specialization indexes two 8-byte tables and interleaves them. Guarded by `if constexpr (vec_size % 8 == 0)`; every other size keeps the LUT, and SM100+ keeps `cvt.rn.f16x2.e2m1x2`.\n\nModule-wide on the FA2 NVFP4-KV instantiation: **`LDL` 36202 → 128, `STL` 9602 → 190**, kernels with a zero-byte stack frame **0/72 → 54/72**, kernels at the 255-register ceiling **25 → 19**.\n\n**2 + 3. `prefill.cuh`: every per-fragment E4M3 scale byte was converted with `static_cast<DTypeQ>(sf_fp8)`.** Where there is no hardware e4m3→f16 convert — below SM90 — that expands to a software conversion whose denormal path is a data-dependent\n\n```\nwhile ((mantissa & 0x0400U) == 0U) { ... }\n```\n\nrenormalization loop. `ncu` source correlation put that single loop at the **top of the kernel's branch profile** — a divergent branch per scale byte, in the innermost loop.\n\nAdded `nvfp4_sf4_to_packed2x2()`, which packs four scale bytes into one word and hands them to the in-tree `fast_dequant_f8f16x4` (prmt/lop3, branch-free), producing exactly the two `half2`/`nv_bfloat162` operands the scale multiply needs. Applied at all four sites — the K path in `compute_qk`, the K path in `compute_qk_fp4_rope`, and both V paths. The helper is gated on `FLASHINFER_HARDWARE_FP8_CONVERSION_ENABLED` — the same macro `vec_cast<*, __nv_fp8_e4m3>` already uses — rather than a separate threshold, so SM90+ keeps `static_cast` and still lowers to the hardware instruction. Verified by SASS: sm_80 emits the `prmt` sequence, sm_90 emits `F2FP.F16.E4M3.UNPACK_B`.\n\nAfter all three, branch opcodes drop out of the top of the profile entirely and instruction count falls 249.6M → 171.1M.\n\n### 4. Spread the E2M1 signs with one `prmt` instead of a shift chain\n\nThe pre-SM100 e2m1 to 16-bit path built each value's sign by moving bit `4j+3` to the msb of byte `j` with four shift/mask/or chains per half of the vector — eight shifts and eight `lop3` per eight values, the largest part of the sequence.\n\n`prmt`'s default mode replicates the sign of the selected byte across the output byte when the msb of a selector nibble is set. Byte `j` of the packed nibbles already carries an odd value's sign in its msb, and `packed << 4` puts the even value's sign in the same place, so one sign-replicating `prmt` gathers four signs in value order as `0x00`/`0xFF` bytes. Masking to `0x80` and merging folds into a single `lop3`. `__byte_perm()` discards the mode bit, so this reaches for the PTX instruction directly.\n\nPer eight values the sequence drops from 25 to 14 instructions (half; bf16 26 to 15). Across the NVFP4 prefill module on sm_80, `cuobjdump` counts 501575 instructions before and 448209 after.\n\nThis one is exhaustively checked rather than sampled: all 2^32 four-payload-byte inputs against the plain-LUT reference, for both half and bf16, zero mismatches. The magnitude-table body is also lifted into `e2m1x8_to_f16x8` / `e2m1x8_to_bf16x8` so a caller holding contiguous nibbles can convert without the stride-2 gather `vec_cast` has to do.\n\n### Results\n\nKernel latency, sm_80, head_dim 128, 32/8 heads, page_size 16, seeded KV, no D2H sync in the timed loop. **FP8 KV is the meaningful yardstick**: it also dequantizes, its dequant is already optimized upstream, and NVFP4 moves half its bytes — so the fair target is <1.0x, not 1.0x.\n\n| case | FP8 KV | NVFP4 before | NVFP4 after | before/FP8 | **after/FP8** |\n|---|---|---|---|---|---|\n| prefill b1 4096² | 1.866 ms | 12.616 | **4.531** | 6.76x | **2.43x** |\n| prefill b4 2048² | 1.489 | 12.157 | **4.427** | 8.17x | **2.97x** |\n| prefill b8 1024² | 0.937 | 6.351 | **2.399** | 6.78x | **2.56x** |\n| decode b8 kv8192 | 0.172 | 0.921 | **0.295** | 5.36x | **1.72x** |\n| decode b32 kv8192 | 0.673 | 3.298 | **1.146** | 4.90x | **1.70x** |\n| decode b64 kv8192 40h | 1.544 | 6.815 | **2.347** | 4.41x | **1.52x** |\n\nSpeedup over the current NVFP4 path: **prefill 2.65–2.78x, decode 2.88–3.12x**.\n\n**Measurement caveat.** At this commit `_nvfp4_kv_requires_disabled_split_kv()` force-disables split-KV for NVFP4 KV on every architecture, while FP8 KV keeps it. The FP8 column above is therefore *unfair to NVFP4* in the decode rows — NVFP4 is running without flash-decoding and FP8 is not. The before/after columns are unaffected, since both sides carry the same gate. #4747 narrows that gate to the architecture it was found on; NVFP4 decode improves further once it lands.\n\nEnd-to-end serving numbers are omitted for the same reason: with the gate in place, NVFP4 decode at low batch is up to 3x off its own achievable latency, so an end-to-end table taken here would measure the gate rather than this change.\n\nAn isolated microbenchmark of change 1 alone gives 6.82x on the conversion when ALU-bound and 3.69x when streaming from HBM (322 → 1187 GB/s) — the old path could not saturate HBM at all.\n\n## 🔍 Related Issues\n\nN/A\n\n## 🚀 Pull Request Checklist\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed. *(No new tests: every change is an arithmetic-identity replacement, so the existing suite plus a bit-identity check is the stronger assertion. See the head_dim gap below, which is why I did add coverage there manually rather than as a committed test.)*\n- [x] All tests are passing — the NVFP4/FP4 selection of the attention and quantization suites on SM80, not the full suite.\n\n```bash\npytest tests/attention/test_batch_prefill_kernels.py \\\n tests/attention/test_batch_decode_kernels.py \\\n tests/attention/test_single_prefill.py \\\n tests/attention/test_batch_attention.py \\\n tests/utils/test_fp4_kv_quantization.py -k \"nvfp4 or fp4\"\n# 425 passed, 25 skipped in 1837s\n```\n\n**Bit-identity.** Every change replaces an arithmetic expression with an equal one, so the oracle is byte equality against the unpatched build rather than a tolerance. Captured attention output before and after across `head_dim {64,128,256,512}` × `page_size {1,16,64}` × `{NHD,HND}` × `{float16,bfloat16}` × `causal {True,False}`, prefill and decode: **bit-identical everywhere** (`torch.equal` true, max abs diff 0). The one exception is `page_size=1`, which is **already non-deterministic upstream** — two runs of the *same* build differ by up to 7.3e-1 — so it cannot be compared this way in either direction.\n\nThe `prmt` conversion tables were also verified exhaustively in isolation: all 16 nibble values × 8 fragment positions against the previous LUT, both dtypes, on sm_80 hardware — 0 mismatches.\n\n## Reviewer Notes\n\n**Known behavioral difference, pre-existing, not introduced here.** `fast_dequant_f8f16x4` is not bit-equivalent to `static_cast<DTypeQ>(__nv_fp8_e4m3)` on the two E4M3 NaN encodings:\n\n| byte | fast path (FP16) | fast path (BF16) | `static_cast` |\n|---|---|---|---|\n| `0x7F` | `0x5F80` = +480 | `0x43F0` = +480 | `0x7FFF` NaN |\n| `0xFF` | `0xDF80` = −480 | `0xC3F0` = −480 | `0x7FFF` NaN |\n\nThe other 254 byte values are bit-identical, including every E4M3 denormal, ±0, and all finite negatives. This is a property of `fast_dequant_f8f16x4` itself, which the `USE_VEC_V_SCALE` path already used before this PR — so the behavior is not new, but this PR does extend it to the other four sites. The in-tree append quantizer never emits a NaN scale; an externally supplied `kv_cache_sf` tensor is not validated, so it is reachable in principle. Making it exact would put a `(byte & 0x7F) == 0x7F` test back into the innermost loop — i.e. re-introduce the branch this PR removes — so I left it and am flagging it instead. Fixing `fast_dequant_f8f16x4` itself would be a separate change affecting the whole FP8 KV path.\n\n**Why the scale multiply still scales K rather than the accumulator.** Hoisting the per-block scale onto the MMA accumulator looks attractive (it is what SM100 block-scaled MMA does in hardware) but is *worse* at this geometry: for `m16n8` a thread holds 8 halves of `b_frag` (4 `__hmul2`) versus 8 accumulator floats (8 `FFMA`), and the K fragment is reused across every `mma_q`. The existing arrangement is already the cheaper side, so it is unchanged.\n\nWhat I verified and what I did not: I have sm_80 hardware, so every runtime result above is sm_80. The arch split was checked by compilation and SASS rather than execution — sm_80 emits the `prmt` sequence, sm_90 emits `F2FP.F16.E4M3.UNPACK_B`, and a host pass plus `sm_100a` compile both succeed — but I have not run sm_86, sm_89, sm_90 or SM100 at runtime. Change 1 takes the `prmt` path on every target below SM100, so sm_86/89/90 exercise code I could not execute; changes 2 and 3 leave SM90+ on `static_cast`, so those targets keep the current behavior by construction. Hopper coverage in particular would be worth a second pair of eyes.\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n* **Performance Improvements**\n * Improved NVFP4 scale-factor dequantization during attention processing.\n * Added faster FP4-to-FP16 and FP4-to-BF16 conversion paths on supported CUDA hardware.\n * Reduced conversion overhead for FP4 attention and vector operations while preserving existing behavior and fallback support.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n\n\n\n\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": \"sm_80\", \"model\": null, \"shape\": \"head_dim=128,32/8 heads,page_size=16\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 12.616, \"optimized\": 4.531, \"stated_speedup\": null, \"speedup\": 2.7844}, {\"scope\": \"kernel\", \"hardware\": \"sm_80\", \"model\": null, \"shape\": \"head_dim=128,32/8 heads,page_size=16\", \"batch_size\": 4, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 12.157, \"optimized\": 4.427, \"stated_speedup\": null, \"speedup\": 2.7461}, {\"scope\": \"kernel\", \"hardware\": \"sm_80\", \"model\": null, \"shape\": \"head_dim=128,32/8 heads,page_size=16\", \"batch_size\": 8, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 6.351, \"optimized\": 2.399, \"stated_speedup\": null, \"speedup\": 2.6474}, {\"scope\": \"kernel\", \"hardware\": \"sm_80\", \"model\": null, \"shape\": \"head_dim=128,32/8 heads,page_size=16,kv=8192\", \"batch_size\": 8, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.921, \"optimized\": 0.295, \"stated_speedup\": null, \"speedup\": 3.122}, {\"scope\": \"kernel\", \"hardware\": \"sm_80\", \"model\": null, \"shape\": \"head_dim=128,32/8 heads,page_size=16,kv=8192\", \"batch_size\": 32, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 3.298, \"optimized\": 1.146, \"stated_speedup\": null, \"speedup\": 2.8778}, {\"scope\": \"kernel\", \"hardware\": \"sm_80\", \"model\": null, \"shape\": \"head_dim=128,32/8 heads,page_size=16,kv=8192,40h\", \"batch_size\": 64, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 6.815, \"optimized\": 2.347, \"stated_speedup\": null, \"speedup\": 2.9037}, {\"scope\": \"kernel\", \"hardware\": \"sm_80\", \"model\": null, \"shape\": null, \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 2.65, \"speedup\": 2.65}, {\"scope\": \"kernel\", \"hardware\": \"sm_80\", \"model\": null, \"shape\": null, \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 2.78, \"speedup\": 2.78}, {\"scope\": \"kernel\", \"hardware\": \"sm_80\", \"model\": null, \"shape\": null, \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 2.88, \"speedup\": 2.88}, {\"scope\": \"kernel\", \"hardware\": \"sm_80\", \"model\": null, \"shape\": null, \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 3.12, \"speedup\": 3.12}, {\"scope\": \"kernel\", \"hardware\": \"sm_80\", \"model\": null, \"shape\": null, \"batch_size\": null, \"metric\": \"bandwidth\", \"unit\": \"GB/s\", \"higher_is_better\": true, \"baseline\": 322, \"optimized\": 1187, \"stated_speedup\": null, \"speedup\": 3.6863}]"},"kernel_speedup":{"kind":"number","value":2.8778,"string":"2.8778"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1071,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"9caa4488a485bb34ac05a065b694b28ca21b2b4e"},"date":{"kind":"string","value":"2026-08-26T16:08:54-07:00"},"pr_number":{"kind":"number","value":4733,"string":"4,733"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/4733"},"title":{"kind":"string","value":"perf(activation): cap act_and_mul_kernel block size for ~17-19% speedup at large hidden dims (#4733)"},"message":{"kind":"string","value":"perf(activation): cap act_and_mul_kernel block size for ~17-19% speedup at large hidden dims (#4733)\n\n## Description\n\n**~17-19% faster `act_and_mul_kernel`** (used by `silu_and_mul` /\n`gelu_and_mul` /\n`gelu_tanh_and_mul`) **at large hidden dims** — measured 1.17x–1.19x at\n`d=8192` on NVIDIA B200\n(see Performance Results below) — by capping the kernel's thread block\nsize instead of letting it\nscale up to 1024 threads.\n\n`act_and_mul_kernel` sizes its thread block directly off the hidden\ndimension:\n`blockDim = min(d / vec_size, 1024)`. For large hidden sizes (e.g.\n`d=8192`, a common LLM FFN\nwidth), this drives the block to 1024 threads, raising per-block\nregister pressure enough to limit\nhow many blocks can be resident on an SM at once.\n\nThe kernel body already contains a block-stride loop over `d /\nvec_size`, so it doesn't need one\nthread per element — capping the block size and letting that existing\nloop iterate more is enough\nto improve occupancy/DRAM throughput, with no change to kernel\nsemantics.\n\nWhat changed:\n1. `flashinfer/jit/activation.py`: cap `blockDim` at 256 instead of\nscaling up to 1024 for large `d`.\n For small `d` (`d / vec_size < 256`), behavior is unchanged.\n2. `include/flashinfer/activation.cuh`: add `__launch_bounds__(256)` so\nthe compiler doesn't need to\n plan register allocation for a larger block.\n\n## Related Issues\n\nNo existing issue tracks this specific problem. Two other open PRs touch\nnearby code in the same\nkernel and may be worth cross-checking for conflicts: #2613\n(non-power-of-2 `vec_size` handling)\nand #2720 (rewrites the PDL/`griddepcontrol` block). Neither overlaps\nwith this fix's specific\nchange (block-size capping), but both touch the same function.\n\n## Pre-commit Checks\n- [ ] Ran `pre-commit run -a`\n\n## Performance Results\n\n**Testing environment:** NVIDIA B200 (SM100a), fp16.\n\n| shape (tokens × hidden) | before | after | speedup |\n|---|---|---|---|\n| 16384 × 8192 | 139.3us (DRAM 72.7%, occupancy 84.0%) | 119.3us (DRAM\n84.5%, occupancy 88.7%) | 1.17x |\n| 4096 × 8192 | 34.6us (DRAM 64.9%, occupancy 82.9%) | 29.0us (DRAM\n75.6%, occupancy 82.9%) | 1.19x |\n\n2/2 measured shapes improved, no regressions observed. The 16384×8192\ngain comes from both higher\noccupancy and higher DRAM throughput; the 4096×8192 gain is from higher\nDRAM throughput at\nunchanged occupancy — the underlying mechanism is \"more/better-scheduled\nblocks per SM,\" which\ndoesn't always show up as an occupancy-metric change.\n\nBoth configurations compiled to 32 registers/thread on the toolchain\nused here; the exact register\ncount (and therefore the exact gain) will vary by CUDA/compiler version.\nThis change should not\nregress any shape — it only shrinks the block size in a regime where the\nold size already exceeded\nwhat was needed for full occupancy, and small-`d` shapes are unaffected.\n\n## Key Limitations\n- Only one GPU SKU (B200) tested; not verified on Hopper/SM90 or SM120,\nthough the change is\narchitecture-agnostic (host-side launch config only, no kernel math\nchanged).\n- Only 2 shapes profiled with Nsight Compute; broader shape sweep not\nrun.\n- No new test added — this is a launch-config-only change exercised by\nthe existing test suite's\n coverage, not a new code path.\n\n## Tests\n- [x] `pytest tests/utils/test_activation.py` — all `dim` values\n(128–16384) × `silu_and_mul` /\n `gelu_tanh_and_mul` pass against the PyTorch reference.\n\n## Reviewer Notes\n@yzh119 — this touches the launch-config code from #930. @cyx-6 — most\nrecent author of this\nfunction. @bkryu — you're an auto-requested reviewer on #2613 which\ntouches the same kernel,\nflagging in case of overlap.\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n* **Performance**\n* Optimized activation and elementwise multiplication kernels by\nadjusting their launch configuration.\n * Preserved existing kernel behavior and results.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->"},"path":{"kind":"string","value":"include/flashinfer/activation.cuh"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * Copyright (c) 2024 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef FLASHINFER_ACTIVATION_CUH_\n#define FLASHINFER_ACTIVATION_CUH_\n\n#include \"math.cuh\"\n#include \"utils.cuh\"\n#include \"vec_dtypes.cuh\"\n\nnamespace flashinfer {\n\nnamespace activation {\n\ntemplate <typename T, float (*Activation)(const float&)>\n__global__ void act_and_mul_kernel(T* __restrict__ out, const T* __restrict__ input, const int d) {\n constexpr uint32_t vec_size = 16 / sizeof(T);\n const int64_t token_idx = blockIdx.x;\n const int64_t thread_idx = threadIdx.x;\n const int64_t stride = blockDim.x;\n const int64_t offset = token_idx * 2 * d;\n\n#if (__CUDACC_VER_MAJOR__ >= 12 && defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"griddepcontrol.wait;\");\n#endif\n\n#pragma unroll 1\n for (uint32_t idx = thread_idx; idx < d / vec_size; idx += stride) {\n vec_t<float, vec_size> x_vec, y_vec, out_vec;\n x_vec.cast_load(input + offset + idx * vec_size);\n y_vec.cast_load(input + offset + d + idx * vec_size);\n#pragma unroll\n for (uint32_t i = 0; i < vec_size; ++i) {\n out_vec[i] = Activation(x_vec[i]) * y_vec[i];\n }\n out_vec.cast_store(out + token_idx * d + idx * vec_size);\n }\n\n const int64_t remaining_offset = d - d % (stride * vec_size);\n // process the remaining elements\n#pragma unroll 1\n for (int64_t idx = thread_idx; idx < d % (stride * vec_size); idx += stride) {\n float x = input[offset + remaining_offset + idx],\n y = input[offset + remaining_offset + d + idx];\n out[token_idx * d + remaining_offset + idx] = Activation(x) * y;\n }\n\n#if (__CUDACC_VER_MAJOR__ >= 12 && defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"griddepcontrol.launch_dependents;\");\n#endif\n}\n\n} // namespace activation\n} // namespace flashinfer\n\n#endif // FLASHINFER_ACTIVATION_CUH_\n"},"after_code":{"kind":"string","value":"/*\n * Copyright (c) 2024 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef FLASHINFER_ACTIVATION_CUH_\n#define FLASHINFER_ACTIVATION_CUH_\n\n#include \"math.cuh\"\n#include \"utils.cuh\"\n#include \"vec_dtypes.cuh\"\n\nnamespace flashinfer {\n\nnamespace activation {\n\ntemplate <typename T, float (*Activation)(const float&)>\n__global__ __launch_bounds__(256) void act_and_mul_kernel(T* __restrict__ out,\n const T* __restrict__ input,\n const int d) {\n constexpr uint32_t vec_size = 16 / sizeof(T);\n const int64_t token_idx = blockIdx.x;\n const int64_t thread_idx = threadIdx.x;\n const int64_t stride = blockDim.x;\n const int64_t offset = token_idx * 2 * d;\n\n#if (__CUDACC_VER_MAJOR__ >= 12 && defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"griddepcontrol.wait;\");\n#endif\n\n#pragma unroll 1\n for (uint32_t idx = thread_idx; idx < d / vec_size; idx += stride) {\n vec_t<float, vec_size> x_vec, y_vec, out_vec;\n x_vec.cast_load(input + offset + idx * vec_size);\n y_vec.cast_load(input + offset + d + idx * vec_size);\n#pragma unroll\n for (uint32_t i = 0; i < vec_size; ++i) {\n out_vec[i] = Activation(x_vec[i]) * y_vec[i];\n }\n out_vec.cast_store(out + token_idx * d + idx * vec_size);\n }\n\n const int64_t remaining_offset = d - d % (stride * vec_size);\n // process the remaining elements\n#pragma unroll 1\n for (int64_t idx = thread_idx; idx < d % (stride * vec_size); idx += stride) {\n float x = input[offset + remaining_offset + idx],\n y = input[offset + remaining_offset + d + idx];\n out[token_idx * d + remaining_offset + idx] = Activation(x) * y;\n }\n\n#if (__CUDACC_VER_MAJOR__ >= 12 && defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"griddepcontrol.launch_dependents;\");\n#endif\n}\n\n} // namespace activation\n} // namespace flashinfer\n\n#endif // FLASHINFER_ACTIVATION_CUH_\n"},"diff":{"kind":"string","value":"--- include/flashinfer/activation.cuh\n+++ include/flashinfer/activation.cuh\n@@ -26,7 +26,9 @@\n namespace activation {\n \n template <typename T, float (*Activation)(const float&)>\n-__global__ void act_and_mul_kernel(T* __restrict__ out, const T* __restrict__ input, const int d) {\n+__global__ __launch_bounds__(256) void act_and_mul_kernel(T* __restrict__ out,\n+ const T* __restrict__ input,\n+ const int d) {\n constexpr uint32_t vec_size = 16 / sizeof(T);\n const int64_t token_idx = blockIdx.x;\n const int64_t thread_idx = threadIdx.x;"},"lines_added":{"kind":"number","value":3,"string":"3"},"lines_removed":{"kind":"number","value":1,"string":"1"},"files_in_commit":{"kind":"number","value":2,"string":"2"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["B200","HOPPER","SM100","SM120","SM90"],"string":"[\n \"B200\",\n \"HOPPER\",\n \"SM100\",\n \"SM120\",\n \"SM90\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":["1.17x","1.19x","16384 ×","1.17x","4096 ×","1.19x"],"string":"[\n \"1.17x\",\n \"1.19x\",\n \"16384 ×\",\n \"1.17x\",\n \"4096 ×\",\n \"1.19x\"\n]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (include/flashinfer/activation.cuh).\n\nGoal: perf(activation): cap act_and_mul_kernel block size for ~17-19% speedup at large hidden dims\nTarget hardware: B200, HOPPER, SM100, SM120, SM90\nTarget models: unspecified\n\nCurrent file:\n```cuda\n/*\n * Copyright (c) 2024 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef FLASHINFER_ACTIVATION_CUH_\n#define FLASHINFER_ACTIVATION_CUH_\n\n#include \"math.cuh\"\n#include \"utils.cuh\"\n#include \"vec_dtypes.cuh\"\n\nnamespace flashinfer {\n\nnamespace activation {\n\ntemplate <typename T, float (*Activation)(const float&)>\n__global__ void act_and_mul_kernel(T* __restrict__ out, const T* __restrict__ input, const int d) {\n constexpr uint32_t vec_size = 16 / sizeof(T);\n const int64_t token_idx = blockIdx.x;\n const int64_t thread_idx = threadIdx.x;\n const int64_t stride = blockDim.x;\n const int64_t offset = token_idx * 2 * d;\n\n#if (__CUDACC_VER_MAJOR__ >= 12 && defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"griddepcontrol.wait;\");\n#endif\n\n#pragma unroll 1\n for (uint32_t idx = thread_idx; idx < d / vec_size; idx += stride) {\n vec_t<float, vec_size> x_vec, y_vec, out_vec;\n x_vec.cast_load(input + offset + idx * vec_size);\n y_vec.cast_load(input + offset + d + idx * vec_size);\n#pragma unroll\n for (uint32_t i = 0; i < vec_size; ++i) {\n out_vec[i] = Activation(x_vec[i]) * y_vec[i];\n }\n out_vec.cast_store(out + token_idx * d + idx * vec_size);\n }\n\n const int64_t remaining_offset = d - d % (stride * vec_size);\n // process the remaining elements\n#pragma unroll 1\n for (int64_t idx = thread_idx; idx < d % (stride * vec_size); idx += stride) {\n float x = input[offset + remaining_offset + idx],\n y = input[offset + remaining_offset + d + idx];\n out[token_idx * d + remaining_offset + idx] = Activation(x) * y;\n }\n\n#if (__CUDACC_VER_MAJOR__ >= 12 && defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"griddepcontrol.launch_dependents;\");\n#endif\n}\n\n} // namespace activation\n} // namespace flashinfer\n\n#endif // FLASHINFER_ACTIVATION_CUH_\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## Description\n\n**~17-19% faster `act_and_mul_kernel`** (used by `silu_and_mul` / `gelu_and_mul` /\n`gelu_tanh_and_mul`) **at large hidden dims** — measured 1.17x–1.19x at `d=8192` on NVIDIA B200\n(see Performance Results below) — by capping the kernel's thread block size instead of letting it\nscale up to 1024 threads.\n\n`act_and_mul_kernel` sizes its thread block directly off the hidden dimension:\n`blockDim = min(d / vec_size, 1024)`. For large hidden sizes (e.g. `d=8192`, a common LLM FFN\nwidth), this drives the block to 1024 threads, raising per-block register pressure enough to limit\nhow many blocks can be resident on an SM at once.\n\nThe kernel body already contains a block-stride loop over `d / vec_size`, so it doesn't need one\nthread per element — capping the block size and letting that existing loop iterate more is enough\nto improve occupancy/DRAM throughput, with no change to kernel semantics.\n\nWhat changed:\n1. `flashinfer/jit/activation.py`: cap `blockDim` at 256 instead of scaling up to 1024 for large `d`.\n For small `d` (`d / vec_size < 256`), behavior is unchanged.\n2. `include/flashinfer/activation.cuh`: add `__launch_bounds__(256)` so the compiler doesn't need to\n plan register allocation for a larger block.\n\n## Related Issues\n\nNo existing issue tracks this specific problem. Two other open PRs touch nearby code in the same\nkernel and may be worth cross-checking for conflicts: #2613 (non-power-of-2 `vec_size` handling)\nand #2720 (rewrites the PDL/`griddepcontrol` block). Neither overlaps with this fix's specific\nchange (block-size capping), but both touch the same function.\n\n## Pre-commit Checks\n- [ ] Ran `pre-commit run -a`\n\n## Performance Results\n\n**Testing environment:** NVIDIA B200 (SM100a), fp16.\n\n| shape (tokens × hidden) | before | after | speedup |\n|---|---|---|---|\n| 16384 × 8192 | 139.3us (DRAM 72.7%, occupancy 84.0%) | 119.3us (DRAM 84.5%, occupancy 88.7%) | 1.17x |\n| 4096 × 8192 | 34.6us (DRAM 64.9%, occupancy 82.9%) | 29.0us (DRAM 75.6%, occupancy 82.9%) | 1.19x |\n\n2/2 measured shapes improved, no regressions observed. The 16384×8192 gain comes from both higher\noccupancy and higher DRAM throughput; the 4096×8192 gain is from higher DRAM throughput at\nunchanged occupancy — the underlying mechanism is \"more/better-scheduled blocks per SM,\" which\ndoesn't always show up as an occupancy-metric change.\n\nBoth configurations compiled to 32 registers/thread on the toolchain used here; the exact register\ncount (and therefore the exact gain) will vary by CUDA/compiler version. This change should not\nregress any shape — it only shrinks the block size in a regime where the old size already exceeded\nwhat was needed for full occupancy, and small-`d` shapes are unaffected.\n\n## Key Limitations\n- Only one GPU SKU (B200) tested; not verified on Hopper/SM90 or SM120, though the change is\n architecture-agnostic (host-side launch config only, no kernel math changed).\n- Only 2 shapes profiled with Nsight Compute; broader shape sweep not run.\n- No new test added — this is a launch-config-only change exercised by the existing test suite's\n coverage, not a new code path.\n\n## Tests\n- [x] `pytest tests/utils/test_activation.py` — all `dim` values (128–16384) × `silu_and_mul` /\n `gelu_tanh_and_mul` pass against the PyTorch reference.\n\n## Reviewer Notes\n@yzh119 — this touches the launch-config code from #930. @cyx-6 — most recent author of this\nfunction. @bkryu — you're an auto-requested reviewer on #2613 which touches the same kernel,\nflagging in case of overlap.\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n* **Performance**\n * Optimized activation and elementwise multiplication kernels by adjusting their launch configuration.\n * Preserved existing kernel behavior and results.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": \"NVIDIA B200\", \"model\": null, \"shape\": \"tokens=16384,hidden=8192\", \"batch_size\": 16384, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 139.3, \"optimized\": 119.3, \"stated_speedup\": 1.17, \"speedup\": 1.1676}, {\"scope\": \"kernel\", \"hardware\": \"NVIDIA B200\", \"model\": null, \"shape\": \"tokens=4096,hidden=8192\", \"batch_size\": 4096, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 34.6, \"optimized\": 29.0, \"stated_speedup\": 1.19, \"speedup\": 1.1931}]"},"kernel_speedup":{"kind":"number","value":1.1804,"string":"1.1804"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1072,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"8c5347726f30063fa1c17c4e81e75d509936d610"},"date":{"kind":"string","value":"2026-08-25T22:12:51-04:00"},"pr_number":{"kind":"number","value":4030,"string":"4,030"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/4030"},"title":{"kind":"string","value":"perf(msa): chunked top-k and in-kernel causal offsets for the SM12x indexer (#4030)"},"message":{"kind":"string","value":"perf(msa): chunked top-k and in-kernel causal offsets for the SM12x indexer (#4030)\n\n## 📌 Description\n\nFollow-up to #3655, which enabled MiniMax Sparse Attention (MSA) on\nSM120/SM121. The indexer (proxy score + top-k, the two ops that pick\neach query's KV blocks) stayed behind vLLM in a few regimes there. All\nof the gaps traced to `msa_topk_select` and its wrapper rather than to\nthe proxy kernel:\n\n- At decode with small batches, the top-k launches one CTA per (query,\nhead) row, which is 4 CTAs at batch 1, leaving the GPU nearly idle. At\n32k context those rows also fall into the radix kernel, which costs\nabout as much as the proxy itself.\n- At long-sequence prefill, the top-k reads scores with strided\naccesses, and the radix kernel re-reads them once per digit pass.\n- The packed decode wrappers built the causal-offset tensor with three\nsmall torch kernels per call, about as costly as the top-k itself at\nshort sequence lengths.\n\nChanges:\n\n- A new chunked top-k. A partial kernel ranks 64-block chunks\nindependently, one CTA per (query, head, chunk), and a merge kernel then\nre-ranks the surviving candidates for each row. Both use the same\nordering as the existing top-k kernels, so selections are identical. The\nmerge launches with PDL to overlap with the partial kernel.\n- A q-tiled variant of the partial kernel for large grids. It covers 32\nqueries per CTA so that every score load is one coalesced line, which\nextends the chunked path to prefill under a 128 MB scratch cap; larger\ngrids keep the radix kernel.\n- The packed decode kernels (bf16 and NVFP4) now compute the causal\noffset in-kernel when `q_offset` is not given, removing the wrapper's\ntorch launches from the decode path.\n\nThe kernel choice depends only on shapes, so it is CUDA-graph safe; a\nnew test covers graph capture on the chunked path.\n\n### Performance\n\nMeasured as in #3655: median GPU time over CUDA-graph replays (CUPTI),\nwith the L2 cache flushed between replays so one replay cannot reuse the\nprevious replay's data. The baseline is vLLM's MiniMax-M3 Triton MSA\nkernels on the same GPUs and shapes. Each cell is an RTX PRO 6000 Server\n/ RTX 5080 / GB10 triple, and speedup = vLLM time / FlashInfer time, so\nhigher is better. \"Before\" is main as of #3655. The MTP columns run the\nsame call with 4 draft tokens per request, as in a speculative-decoding\nverify step.\n\nIndexer decode (proxy + top-k), batch 1:\n\n| S | before | after | before (4-token MTP) | after (4-token MTP) |\n|--:|:--:|:--:|:--:|:--:|\n| 2k | 1.31 / 1.43 / 1.33 | 1.31 / 1.42 / 1.38 | 0.73 / 0.71 / 0.91 |\n1.20 / 1.12 / 1.29 |\n| 4k | 1.40 / 1.39 / 1.21 | 1.43 / 1.38 / 1.24 | 0.87 / 0.86 / 1.03 |\n1.39 / 1.29 / 1.33 |\n| 8k | 1.18 / 1.10 / 1.08 | 1.28 / 1.22 / 1.10 | 0.82 / 0.90 / 0.95 |\n1.26 / 1.34 / 1.11 |\n| 16k | 1.18 / 1.09 / 1.02 | 1.25 / 1.17 / 1.09 | 0.95 / 0.85 / 0.97 |\n1.34 / 1.19 / 1.09 |\n| 32k | 0.90 / 0.98 / 0.98 | 1.08 / 1.11 / 1.03 | 0.95 / 0.94 / 0.96 |\n1.36 / 1.30 / 1.07 |\n\nIndexer prefill, batch 1 (the 2k and 4k rows keep the old kernels and\nare unchanged within noise):\n\n| S | before | after |\n|--:|:--:|:--:|\n| 8k | 1.04 / 1.14 / 1.01 | 1.06 / 1.18 / 1.02 |\n| 16k | 1.04 / 1.18 / 1.02 | 1.19 / 1.25 / 1.16 |\n| 32k | 0.90 / 1.08 / 0.89 | 1.16 / 1.28 / 1.19 |\n\nMeasured against the kernels this PR replaces:\n\n- The new top-k alone is 1.4-2.2x faster at decode (batch 1 to 128) and\n1.2-2.1x faster at 8k-32k prefill.\n- The proxy kernel is untouched, so shapes where it dominates do not\nmove: at batch 128 the end-to-end ratio stays at 1.00-1.03 vs vLLM.\n- The optional NVFP4 decode path also speeds up because its wrapper\nsheds the same torch launches.\n\n## 🔍 Related Issues\n\nFollow-up to #3655.\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the\npre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\nAll 155 tests in `tests/msa_ops/` pass on an RTX 5080 (SM120) after\nrebasing onto current main. This PR adds tests for:\n\n- the dispatch boundaries between the three top-k kernels\n- selection identity between the chunked and existing kernels, including\nNaN scores, forced blocks, and the ragged q-tile tail\n- CUDA-graph capture on the chunked path\n- explicit `q_offset` on both packed decode kernels\n\nIt also moves the paged-varlen fp4 test's reference to float32: the\nkernel's fp4 x scale products never round through bf16, so the\nbf16-rounded reference misses the 5e-2 tolerance on causal-boundary\nblocks (16 of 40 seeds on an RTX 5080, including the checked-in seed).\nThe same treatment the other fp4 tests already use.\n\n`compute-sanitizer` racecheck and memcheck are clean on the new kernels.\n\n## Reviewer Notes\n\n- Per-token `num_valid_pages` calls (added by #4324) stay on the\nsingle-kernel paths: the chunked kernels' geometry is host-derived from\nthe scalar count.\n- Selection identity across the top-k kernels (same bit-key and tie\norder) is pinned by tests.\n- The row-per-CTA and q-tiled partial kernels keep separate bodies on\npurpose: the row-per-CTA binary is production-validated.\n- Deferred for the same reason: skipping the redundant sentinel prefill\nof the candidate scratch, and sharing the forced-slot fill across the\nthree kernels.\n\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n- **New Features**\n- Added chunked top-k selection for large candidate sets, including\ntiled execution and forced-page handling.\n- Added optional default query-offset handling for packed decode with\nright-aligned causal masking.\n - Added tracing support for MSA top-k selection.\n\n- **Bug Fixes**\n - Improved causal masking consistency across packed decode formats.\n- Preserved sentinel results and selected-score correctness during top-k\nselection.\n\n- **Tests**\n- Expanded coverage for large contexts, query offsets, chunked\nselection, tracing, and CUDA graph execution.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n\n---------\n\nCo-authored-by: Claude Fable 5 <noreply@anthropic.com>"},"path":{"kind":"string","value":"flashinfer/msa_ops/cute_dsl/proxy_score_fp4_sm12x.py"},"language":{"kind":"string","value":"cute_dsl"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"\"\"\"\nCopyright (c) 2026 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nNVFP4 tensor-core MSA proxy-score kernels for SM120/SM121: same contract as\n:mod:`proxy_score_sm12x`, with a general split-K and a packed-decode schedule.\n\nNo scalar stream schedule here (unlike the bf16 decode path): at 4-bit K the\nMMA pipeline hides the small tile's load latency, and the per-lane fp4 decode\nchain makes a scalar port slower, not faster.\n\"\"\"\n\nimport cuda.bindings.driver as cuda\nimport cutlass\nimport cutlass.cute as cute\nimport cutlass.pipeline as pipeline\nimport cutlass.utils.blackwell_helpers as sm120_utils\nfrom cutlass import Uint8, Uint32\nfrom cutlass.cute.nvgpu import warp\nfrom cutlass.cute.nvgpu.warp.mma import Field as WarpField\n\nfrom flashinfer.cute_dsl.utils import (\n sm120_make_smem_layout_sfa,\n sm120_make_smem_layout_sfb,\n)\n\n# NVFP4: 16-element scale groups (head_dim 128 -> 8 groups/row).\n_SF_VEC_SIZE = 16\n\n# Launch bound: cap registers so two CTAs stay resident per SM; one CTA cannot\n# hide the K-load latency and three would force spills. The split-K host\n# heuristic in proxy_score.py assumes this occupancy (target = 2 * num_sms).\n_MIN_BLOCKS_PER_MP = 2\n\n\nclass MsaProxyScoreFp4MmaSm12x:\n \"\"\"General NVFP4 tensor-core proxy schedule (any q length, flat or paged K);\n every query head scores independently.\"\"\"\n\n # The cuBLAS SF layout groups rows in blocks of 128, so a 128-row q-tile's\n # scale factors are a single contiguous block.\n _M = 128\n _N = 128 # kv-block: MSA scores per 128-token KV block\n _NUM_THREADS = 256 # 8 MMA warps for the (4,2,1) atom\n\n def __init__(\n self, head_dim: int = 128, is_causal: bool = True, paged: bool = False\n ):\n if head_dim != 128:\n raise ValueError(\"only head_dim == 128 is supported\")\n self._head_dim = head_dim\n self._is_causal = is_causal\n self._paged = paged\n self._num_threads = self._NUM_THREADS\n self.sf_vec_size = _SF_VEC_SIZE\n self.acc_dtype = cutlass.Float32\n self.a_dtype = cutlass.Float4E2M1FN\n self.sf_dtype = cutlass.Float8E4M3FN\n self.tile_shape_mnk = (self._M, self._N, head_dim)\n self._sf_per_row = head_dim // _SF_VEC_SIZE\n self._sf_tiles_n = (self._sf_per_row + 3) // 4\n self._chunks_u32 = head_dim // 8 # 16 Uint32 / packed-fp4 row\n # atom (4,2,1) over the m16n8k64 fp4 MMA -> group m64 n16 k64.\n self._atom_shape = (4, 2, 1)\n self.num_m_tiles = self._M // (16 * self._atom_shape[0])\n self.num_n_tiles = self._N // (8 * self._atom_shape[1])\n self.num_k_blocks = head_dim // 64\n self._min_blocks = _MIN_BLOCKS_PER_MP\n\n self.cta_sync_barrier = pipeline.NamedBarrier(\n barrier_id=1, num_threads=self._num_threads\n )\n\n @cute.jit\n def _build_mma(self):\n \"\"\"fp4 tiled MMA + bare atom + SF smem layouts. Built inside the jit\n context (``make_layout`` / ``get_permutation_mnk`` need an MLIR context).\"\"\"\n mma_op = cute.nvgpu.warp.MmaMXF4NVF4Op(\n self.a_dtype, self.acc_dtype, self.sf_dtype\n )\n permutation_mnk = sm120_utils.get_permutation_mnk(\n self.tile_shape_mnk, self.sf_vec_size, False\n )\n tiled_mma = cute.make_tiled_mma(\n mma_op,\n cute.make_layout(self._atom_shape),\n permutation_mnk=permutation_mnk,\n )\n mma_atom = cute.make_mma_atom(mma_op)\n sfa_layout = sm120_make_smem_layout_sfa(\n tiled_mma, self.tile_shape_mnk, self.sf_vec_size, 1\n )\n sfb_layout = sm120_make_smem_layout_sfb(\n tiled_mma, self.tile_shape_mnk, self.sf_vec_size, 1\n )\n return tiled_mma, mma_atom, sfa_layout, sfb_layout\n\n def _ab_layout(self, mode_n: int):\n return cute.make_layout((mode_n, self._head_dim), stride=(self._head_dim, 1))\n\n @cute.jit\n def __call__(\n self,\n mQ: cute.Tensor, # (total_q, Hq, head_dim//2) packed e2m1, uint8\n mK: cute.Tensor, # flat (total_k,Hkv,hd/2) | paged (pages,Hkv,128,hd/2) u8\n mQsf: cute.Tensor, # uint8 e4m3 scales, cuBLAS 128x4 tiled\n mKsf: cute.Tensor, # uint8 e4m3 scales, cuBLAS 128x4 tiled\n mPageTable: cute.Tensor, # (B, max_pages) int32 paged; dummy (1,1) flat\n mMaxScore: cute.Tensor, # (Hq, max_k_tiles, total_q) f32\n mCuQ: cute.Tensor, # (B + 1,) int32\n mCuK: cute.Tensor, # (B + 1,) int32\n mQOffset: cute.Tensor, # (B,) int32 causal offset\n q_global_scale: cutlass.Float32,\n k_global_scale: cutlass.Float32,\n max_seqlen_q: cutlass.Int32,\n batch_size: cutlass.Int32,\n num_qo_heads: cutlass.Int32,\n max_k_tiles: cutlass.Int32,\n num_splits: cutlass.Int32,\n stream: cuda.CUstream,\n ):\n # Split-K grid, as in proxy_score_sm12x.\n self.kernel(\n mQ,\n mK,\n mQsf,\n mKsf,\n mPageTable,\n mMaxScore,\n mCuQ,\n mCuK,\n mQOffset,\n q_global_scale * k_global_scale,\n max_k_tiles,\n num_splits,\n ).launch(\n grid=(\n cute.ceil_div(max_seqlen_q, self._M) * num_splits,\n batch_size,\n num_qo_heads,\n ),\n block=[self._num_threads, 1, 1],\n stream=stream,\n min_blocks_per_mp=self._min_blocks,\n )\n\n @cute.kernel\n def kernel(\n self,\n mQ: cute.Tensor,\n mK: cute.Tensor,\n mQsf: cute.Tensor,\n mKsf: cute.Tensor,\n mPageTable: cute.Tensor,\n mMaxScore: cute.Tensor,\n mCuQ: cute.Tensor,\n mCuK: cute.Tensor,\n mQOffset: cute.Tensor,\n global_scale: cutlass.Float32, # q_global * k_global, applied at store\n max_k_tiles: cutlass.Int32,\n num_splits: cutlass.Int32,\n ):\n tidx, _, _ = cute.arch.thread_idx()\n bx, batch_idx, qo_head = cute.arch.block_idx()\n # grid x packs (m_block, split), as in the bf16 kernel.\n m_block = bx // num_splits\n split_idx = bx % num_splits\n\n q_start = mCuQ[batch_idx]\n seqlen_q = mCuQ[batch_idx + 1] - q_start\n if cutlass.const_expr(self._paged):\n # mCuK holds per-request lengths on the paged path:\n # page_table supplies every KV address, so there is\n # no base offset to add.\n k_start = cutlass.Int32(0)\n seqlen_k = mCuK[batch_idx]\n else:\n k_start = mCuK[batch_idx]\n seqlen_k = mCuK[batch_idx + 1] - k_start\n num_kv_blocks = cute.ceil_div(seqlen_k, self._N)\n group_size = mQ.shape[1] // mK.shape[1]\n kv_head = qo_head // group_size\n\n if m_block * self._M < seqlen_q:\n tiled_mma, mma_atom, sfa_layout, sfb_layout = self._build_mma()\n sA_layout = self._ab_layout(self._M)\n sB_layout = self._ab_layout(self._N)\n\n @cute.struct\n class SharedStorage:\n sA: cute.struct.Align[\n cute.struct.MemRange[self.a_dtype, cute.cosize(sA_layout)], 1024\n ]\n sB: cute.struct.Align[\n cute.struct.MemRange[self.a_dtype, cute.cosize(sB_layout)], 1024\n ]\n sSFA: cute.struct.Align[\n cute.struct.MemRange[self.sf_dtype, cute.cosize(sfa_layout)], 1024\n ]\n sSFB: cute.struct.Align[\n cute.struct.MemRange[self.sf_dtype, cute.cosize(sfb_layout)], 1024\n ]\n # Warp-epilogue cross-warp scratch: one f32 per (q-row, N-warp).\n # 1KB vs a full 64KB [M,N] scatter, so smem stops capping occupancy.\n sRed: cute.struct.Align[\n cute.struct.MemRange[cutlass.Float32, self._M * 2], 1024\n ]\n\n smem = cutlass.utils.SmemAllocator()\n storage = smem.allocate(SharedStorage)\n sA = storage.sA.get_tensor(sA_layout)\n sB = storage.sB.get_tensor(sB_layout)\n # sm120 SF layouts append a (size-1) stage mode; drop it for the MMA\n # partition. The compound layout's byte offsets for one 128-row/K=128 tile\n # equal the cuBLAS 128x4 layout (== _sf_offset), so the fill is a flat view.\n sSFA = storage.sSFA.get_tensor(sfa_layout)[None, None, 0]\n sSFB = storage.sSFB.get_tensor(sfb_layout)[None, None, 0]\n sfa_n = cute.cosize(sfa_layout)\n sfb_n = cute.cosize(sfb_layout)\n sSFA_u8 = cute.recast_tensor(\n storage.sSFA.get_tensor(cute.make_layout(sfa_n, stride=1)), Uint8\n )\n sSFB_u8 = cute.recast_tensor(\n storage.sSFB.get_tensor(cute.make_layout(sfb_n, stride=1)), Uint8\n )\n sRed = storage.sRed.get_tensor(\n cute.make_layout((self._M, 2), stride=(2, 1))\n )\n\n mQ_u32 = cute.recast_tensor(mQ, Uint32)\n mK_u32 = cute.recast_tensor(mK, Uint32)\n sA_u32 = cute.recast_tensor(sA, Uint32)\n sB_u32 = cute.recast_tensor(sB, Uint32)\n\n # Q is always flat (current query tokens, never paged): read absolute\n # row q_tile0+m, mask on the in-tile position m_block*M+m.\n q_tile0 = q_start + m_block * self._M\n q_pos0 = m_block * self._M\n self._load_packed(\n mQ_u32[None, qo_head, None], sA_u32, q_tile0, q_pos0, seqlen_q, tidx\n )\n self._load_sf(\n mQsf,\n sSFA_u8,\n q_pos0,\n seqlen_q,\n q_tile0 * mQ.shape[1] + qo_head,\n mQ.shape[1],\n tidx,\n )\n self.cta_sync_barrier.arrive_and_wait()\n\n thr_mma = tiled_mma.get_slice(tidx)\n tCsA = thr_mma.partition_A(sA)\n tCsB = thr_mma.partition_B(sB)\n tCrA = tiled_mma.make_fragment_A(tCsA)\n tCrB = tiled_mma.make_fragment_B(tCsB)\n tCrSFA = self._partition_fragment_SFA(sSFA, thr_mma, tidx)\n tCrSFB = self._partition_fragment_SFB(sSFB, thr_mma, tidx)\n cS = cute.make_identity_tensor((self._M, self._N))\n tCcC = thr_mma.partition_C(cS)\n acc = cute.make_rmem_tensor(tCcC.shape[:3], self.acc_dtype)\n\n ldm_A = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(transpose=False, num_matrices=4), self.a_dtype\n )\n ldm_B = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(transpose=False, num_matrices=4), self.a_dtype\n )\n tiled_copy_A = cute.make_tiled_copy_A(ldm_A, tiled_mma)\n tiled_copy_B = cute.make_tiled_copy_B(ldm_B, tiled_mma)\n cp_sf = cute.make_copy_atom(cute.nvgpu.CopyUniversalOp(), self.sf_dtype)\n tiled_copy_SFA = cute.make_tiled_copy(\n cp_sf,\n self._get_layoutSFA_TV(tiled_mma),\n (\n cute.size(tiled_mma.permutation_mnk[0]),\n cute.size(tiled_mma.permutation_mnk[2]),\n ),\n )\n tiled_copy_SFB = cute.make_tiled_copy(\n cp_sf,\n self._get_layoutSFB_TV(tiled_mma),\n (\n cute.size(tiled_mma.permutation_mnk[1]),\n cute.size(tiled_mma.permutation_mnk[2]),\n ),\n )\n thr_A = tiled_copy_A.get_slice(tidx)\n thr_B = tiled_copy_B.get_slice(tidx)\n thr_SFA = tiled_copy_SFA.get_slice(tidx)\n thr_SFB = tiled_copy_SFB.get_slice(tidx)\n tCsA_cp = thr_A.partition_S(sA)\n tCrA_cp = thr_A.retile(tCrA)\n tCsB_cp = thr_B.partition_S(sB)\n tCrB_cp = thr_B.retile(tCrB)\n tCsSFA_cp = thr_SFA.partition_S(sSFA)\n tCrSFA_cp = thr_SFA.retile(tCrSFA)\n tCsSFB_cp = thr_SFB.partition_S(sSFB)\n tCrSFB_cp = thr_SFB.retile(tCrSFB)\n\n # Q fragments load once (sA / sSFA reused across all kv-blocks)\n for kb in cutlass.range_constexpr(self.num_k_blocks):\n cute.copy(\n tiled_copy_A, tCsA_cp[None, None, kb], tCrA_cp[None, None, kb]\n )\n cute.copy(\n tiled_copy_SFA,\n cute.filter_zeros(tCsSFA_cp),\n cute.filter_zeros(tCrSFA_cp),\n )\n\n # Split-K stride + causal skip, as in the bf16 kernel.\n if cutlass.const_expr(self._is_causal):\n causal_last = (\n m_block * self._M + (self._M - 1) + mQOffset[batch_idx]\n ) // self._N\n last_block = cutlass.min(causal_last, num_kv_blocks - 1)\n else:\n last_block = num_kv_blocks - 1\n\n n_iter = cute.ceil_div(max_k_tiles, num_splits)\n for it in cutlass.range(n_iter):\n kv_block = split_idx + it * num_splits\n if kv_block <= last_block:\n self.cta_sync_barrier.arrive_and_wait()\n k_pos0 = kv_block * self._N\n if cutlass.const_expr(self._paged):\n # paged: kv_block maps to a 128-row page via the page table.\n # Read it page-local (read_base 0) and mask on the global\n # position; SF row = (page*Hkv + kv_head)*N + token, stride 1.\n page = mPageTable[batch_idx, kv_block]\n gK_pg = cute.recast_tensor(\n mK[page, kv_head, None, None], Uint32\n )\n self._load_packed(gK_pg, sB_u32, 0, k_pos0, seqlen_k, tidx)\n self._load_sf(\n mKsf,\n sSFB_u8,\n k_pos0,\n seqlen_k,\n (page * mK.shape[1] + kv_head) * self._N,\n 1,\n tidx,\n )\n else:\n # flat: read absolute row k_tile0+m, SF row = token*Hkv+kv_head.\n k_tile0 = k_start + kv_block * self._N\n self._load_packed(\n mK_u32[None, kv_head, None],\n sB_u32,\n k_tile0,\n k_pos0,\n seqlen_k,\n tidx,\n )\n self._load_sf(\n mKsf,\n sSFB_u8,\n k_pos0,\n seqlen_k,\n k_tile0 * mK.shape[1] + kv_head,\n mK.shape[1],\n tidx,\n )\n self.cta_sync_barrier.arrive_and_wait()\n\n for kb in cutlass.range_constexpr(self.num_k_blocks):\n cute.copy(\n tiled_copy_B,\n tCsB_cp[None, None, kb],\n tCrB_cp[None, None, kb],\n )\n cute.copy(\n tiled_copy_SFB,\n cute.filter_zeros(tCsSFB_cp),\n cute.filter_zeros(tCrSFB_cp),\n )\n\n acc.fill(0.0)\n for mt in cutlass.range_constexpr(self.num_m_tiles):\n for nt in cutlass.range_constexpr(self.num_n_tiles):\n for kb in cutlass.range_constexpr(self.num_k_blocks):\n mma_atom.set(\n WarpField.SFA, tCrSFA[None, mt, kb].iterator\n )\n mma_atom.set(\n WarpField.SFB, tCrSFB[None, nt, kb].iterator\n )\n cute.gemm(\n mma_atom,\n acc[None, mt, nt],\n tCrA[None, mt, kb],\n tCrB[None, nt, kb],\n acc[None, mt, nt],\n )\n\n # Warp-level block-max epilogue (no scatter buffer): each thread\n # reduces its N columns, a thread-quad shuffle yields the per-q-row\n # warp max, and the two N-warps combine through sRed.\n acc_mn = self._make_acc_tensor_mn_view(acc)\n tScS_mn = self._make_acc_tensor_mn_view(tCcC)\n n_rows = cute.size(acc_mn.shape[0])\n thr_vmnk = tiled_mma.thr_layout_vmnk.get_flat_coord(tidx)\n nwarp = thr_vmnk[2]\n self.cta_sync_barrier.arrive_and_wait()\n for r in cutlass.range_constexpr(n_rows):\n row = tScS_mn[r, 0][0]\n q_loc = m_block * self._M + row\n if cutlass.const_expr(self._is_causal):\n col_limit = cutlass.min(\n q_loc + mQOffset[batch_idx] + 1, seqlen_k\n )\n else:\n col_limit = seqlen_k\n for c in cutlass.range_constexpr(cute.size(acc_mn.shape[1])):\n k_pos = kv_block * self._N + tScS_mn[0, c][1]\n if cute.elem_less(col_limit, k_pos + 1):\n acc_mn[r, c] = -cutlass.Float32.inf\n tile_max = (\n acc_mn[r, None]\n .load()\n .reduce(cute.ReductionOp.MAX, -cutlass.Float32.inf, 0)\n )\n tile_max = self._threadquad_reduce_max(tile_max)\n sRed[row, nwarp] = tile_max\n self.cta_sync_barrier.arrive_and_wait()\n # Combine the two N-warps; one writer per q-row (the nwarp-0\n # warp owns the write).\n if nwarp == 0:\n for r in cutlass.range_constexpr(n_rows):\n row = tScS_mn[r, 0][0]\n q_loc = m_block * self._M + row\n both = cute.arch.fmax(sRed[row, 0], sRed[row, 1])\n if q_loc < seqlen_q:\n mMaxScore[qo_head, kv_block, q_start + q_loc] = (\n both * global_scale\n )\n elif kv_block < max_k_tiles:\n if tidx < self._M:\n q_loc2 = m_block * self._M + tidx\n if q_loc2 < seqlen_q:\n mMaxScore[\n qo_head, kv_block, q_start + q_loc2\n ] = -cutlass.Float32.inf\n\n @cute.jit\n def _sf_offset(self, srow, scol):\n \"\"\"cuBLAS 128x4 tiled SF byte offset; for one 128-row K=128 tile it equals\n the SM120 SF smem layout, so sSFA/sSFB fill by this offset directly.\"\"\"\n srow_in = srow % 128\n return (\n ((srow // 128) * self._sf_tiles_n + scol // 4) * 512\n + (srow_in % 32) * 16\n + (srow_in // 32) * 4\n + scol % 4\n )\n\n @cute.jit\n def _load_packed(self, gX_u32, sX_u32, read_base, pos_base, seqlen, tidx):\n \"\"\"read_base is decoupled from pos_base so the paged path reads a page-local\n tile (read_base 0) but masks on the global token position pos_base + m.\"\"\"\n rows = cute.size(sX_u32.shape[0])\n total = rows * self._chunks_u32\n for it in cutlass.range_constexpr(total // self._num_threads):\n e = tidx + it * self._num_threads\n m = e // self._chunks_u32\n c = e % self._chunks_u32\n if cute.elem_less(pos_base + m, seqlen):\n sX_u32[m, c] = gX_u32[read_base + m, c]\n else:\n sX_u32[m, c] = Uint32(0)\n\n @cute.jit\n def _load_sf(self, mXsf, sXsf_u8, pos_base, seqlen, sf_row_base, sf_stride, tidx):\n \"\"\"Fill the SF smem from the e4m3 buffer: flat passes row base token*heads+head\n with stride num_heads; paged passes (page*Hkv + kv_head)*N with stride 1.\"\"\"\n total = self._M * self._sf_per_row\n for it in cutlass.range_constexpr(total // self._num_threads):\n e = tidx + it * self._num_threads\n m = e // self._sf_per_row\n g = e % self._sf_per_row\n dst = self._sf_offset(m, g)\n if cute.elem_less(pos_base + m, seqlen):\n sXsf_u8[dst] = mXsf[self._sf_offset(sf_row_base + m * sf_stride, g)]\n else:\n sXsf_u8[dst] = Uint8(0)\n\n def _partition_fragment_SFA(self, sfa_tensor, thr_mma, tidx):\n thrfrg = self._thrfrg_SFA(sfa_tensor.layout, thr_mma)\n thr_tensor = cute.make_tensor(sfa_tensor.iterator, thrfrg)\n thr_vmnk = thr_mma.thr_layout_vmnk.get_flat_coord(tidx)\n thr_vmk = (thr_vmnk[0], (thr_vmnk[1], thr_vmnk[3]))\n part = thr_tensor[thr_vmk, (None, None)]\n part = cute.group_modes(cute.flatten(part), 0, 2)\n return cute.make_fragment_like(part)\n\n def _partition_fragment_SFB(self, sfb_tensor, thr_mma, tidx):\n thrfrg = self._thrfrg_SFB(sfb_tensor.layout, thr_mma)\n thr_tensor = cute.make_tensor(sfb_tensor.iterator, thrfrg)\n thr_vmnk = thr_mma.thr_layout_vmnk.get_flat_coord(tidx)\n thr_vnk = (thr_vmnk[0], (thr_vmnk[2], thr_vmnk[3]))\n part = thr_tensor[thr_vnk, (None, None)]\n part = cute.group_modes(cute.flatten(part), 0, 2)\n part = cute.group_modes(part, 1, 3)\n return cute.make_fragment_like(part)\n\n def _thrfrg_SFA(self, sfa_tensor, tiled_mma):\n atom_shape_mnk = tiled_mma.shape_mnk\n atom_sfa_layout = cute.make_layout(\n shape=((2, 2, 8), 64), stride=((8, 0, 1), 16)\n )\n permutation_mnk = tiled_mma.permutation_mnk\n thr_layout_vmnk = tiled_mma.thr_layout_vmnk\n t_tile = (permutation_mnk[0], permutation_mnk[2])\n t_tensor = cute.logical_divide(sfa_tensor, t_tile)\n a_tile = (\n cute.make_layout((atom_shape_mnk[0])),\n cute.make_layout((atom_shape_mnk[2])),\n )\n a_tensor = cute.zipped_divide(t_tensor, a_tile)\n tv_tensor = cute.composition(a_tensor, (atom_sfa_layout, None))\n thr_tile = (\n None,\n (\n cute.make_layout(cute.size(thr_layout_vmnk[1])),\n cute.make_layout(cute.size(thr_layout_vmnk[3])),\n ),\n )\n return cute.zipped_divide(tv_tensor, thr_tile)\n\n def _thrfrg_SFB(self, sfb_tensor, tiled_mma):\n atom_shape_mnk = tiled_mma.shape_mnk\n atom_sfb_layout = cute.make_layout(shape=((4, 8), 64), stride=((0, 1), 8))\n permutation_mnk = tiled_mma.permutation_mnk\n thr_layout_vmnk = tiled_mma.thr_layout_vmnk\n t_tile = (permutation_mnk[1], permutation_mnk[2])\n t_tensor = cute.logical_divide(sfb_tensor, t_tile)\n a_tile = (\n cute.make_layout((atom_shape_mnk[1])),\n cute.make_layout((atom_shape_mnk[2])),\n )\n a_tensor = cute.zipped_divide(t_tensor, a_tile)\n tv_tensor = cute.composition(a_tensor, (atom_sfb_layout, None))\n thr_tile = (\n None,\n (\n cute.make_layout(cute.size(thr_layout_vmnk[2])),\n cute.make_layout(cute.size(thr_layout_vmnk[3])),\n ),\n )\n return cute.zipped_divide(tv_tensor, thr_tile)\n\n def _get_layoutSFA_TV(self, tiled_mma):\n perm_m = tiled_mma.permutation_mnk[0]\n perm_k = tiled_mma.permutation_mnk[2]\n ref_A = cute.make_layout((cute.size(perm_m), cute.size(perm_k)))\n thr_layout_vmnk = tiled_mma.thr_layout_vmnk\n atile = (\n None,\n (\n cute.make_layout(\n shape=(\n cute.size(thr_layout_vmnk[1]),\n cute.size(thr_layout_vmnk[2]),\n ),\n stride=(1, 0),\n ),\n None,\n ),\n )\n thridx_2_thrid = cute.right_inverse(thr_layout_vmnk)\n thrfrg_sfa = self._thrfrg_SFA(ref_A, tiled_mma)\n layout_tv = cute.composition(thrfrg_sfa, (atile, None))\n return cute.composition(layout_tv, (thridx_2_thrid, None))\n\n def _get_layoutSFB_TV(self, tiled_mma):\n perm_n = tiled_mma.permutation_mnk[1]\n perm_k = tiled_mma.permutation_mnk[2]\n ref_B = cute.make_layout((cute.size(perm_n), cute.size(perm_k)))\n thr_layout_vmnk = tiled_mma.thr_layout_vmnk\n atile = (\n None,\n (\n cute.make_layout(\n shape=(\n cute.size(thr_layout_vmnk[1]),\n cute.size(thr_layout_vmnk[2]),\n ),\n stride=(0, 1),\n ),\n None,\n ),\n )\n thridx_2_thrid = cute.right_inverse(thr_layout_vmnk)\n thrfrg_sfb = self._thrfrg_SFB(ref_B, tiled_mma)\n layout_tv = cute.composition(thrfrg_sfb, (atile, None))\n return cute.composition(layout_tv, (thridx_2_thrid, None))\n\n @cute.jit\n def _threadquad_reduce_max(self, val):\n # Max across the 4 lanes of an m16n8 row-quad (the N lanes within a warp)\n val = cute.arch.fmax(\n val,\n cute.arch.shuffle_sync_bfly(val, offset=2, mask=-1, mask_and_clamp=31),\n )\n val = cute.arch.fmax(\n val,\n cute.arch.shuffle_sync_bfly(val, offset=1, mask=-1, mask_and_clamp=31),\n )\n return val\n\n def _make_acc_tensor_mn_view(self, acc: cute.Tensor) -> cute.Tensor:\n acc_layout_col_major = cute.make_layout(acc.layout.shape)\n acc_layout_mn = cute.make_layout(\n (\n (acc_layout_col_major.shape[0][1], acc_layout_col_major.shape[1]),\n (acc_layout_col_major.shape[0][0], acc_layout_col_major.shape[2]),\n ),\n stride=(\n (acc_layout_col_major.stride[0][1], acc_layout_col_major.stride[1]),\n (acc_layout_col_major.stride[0][0], acc_layout_col_major.stride[2]),\n ),\n )\n acc_layout_mn = cute.composition(acc.layout, acc_layout_mn)\n return cute.make_tensor(acc.iterator, acc_layout_mn)\n\n\nclass MsaProxyScoreFp4MmaDecodePackedSm12x(MsaProxyScoreFp4MmaSm12x):\n \"\"\"Head-fused packed-decode fp4 schedule: packs qhead_per_kv heads x pack_q_len\n tokens into the 128 MMA rows so the shared index-K is read once per kv_head.\"\"\"\n\n _PACK_Q_LEN = 8\n _QHEAD_PER_KV = 16\n\n def __init__(\n self,\n head_dim: int = 128,\n is_causal: bool = True,\n paged: bool = False,\n qhead_per_kv: int = _QHEAD_PER_KV,\n pack_q_len: int = _PACK_Q_LEN,\n ):\n super().__init__(head_dim=head_dim, is_causal=is_causal, paged=paged)\n if qhead_per_kv * pack_q_len != self._M:\n raise ValueError(\n f\"qhead_per_kv * pack_q_len must equal the {self._M}-row MMA tile, \"\n f\"got {qhead_per_kv} x {pack_q_len}\"\n )\n # Instance attrs shadow the class defaults; they are constexpr-baked into the\n # gather/epilogue, so each factorization compiles to its own kernel.\n self._QHEAD_PER_KV = qhead_per_kv\n self._PACK_Q_LEN = pack_q_len\n\n @cute.jit\n def __call__(\n self,\n mQ: cute.Tensor,\n mK: cute.Tensor,\n mQsf: cute.Tensor,\n mKsf: cute.Tensor,\n mPageTable: cute.Tensor,\n mMaxScore: cute.Tensor,\n mCuQ: cute.Tensor,\n mCuK: cute.Tensor,\n mQOffset: cute.Tensor,\n q_global_scale: cutlass.Float32,\n k_global_scale: cutlass.Float32,\n max_seqlen_q: cutlass.Int32,\n batch_size: cutlass.Int32,\n num_qo_heads: cutlass.Int32,\n max_k_tiles: cutlass.Int32,\n num_splits: cutlass.Int32,\n stream: cuda.CUstream,\n ):\n # One CTA per (split, batch, kv_head), as in the bf16 packed kernel:\n # the shared index-K is read once per kv_head.\n self.kernel(\n mQ,\n mK,\n mQsf,\n mKsf,\n mPageTable,\n mMaxScore,\n mCuQ,\n mCuK,\n mQOffset,\n q_global_scale * k_global_scale,\n max_k_tiles,\n num_splits,\n ).launch(\n grid=(\n num_splits,\n batch_size,\n num_qo_heads // self._QHEAD_PER_KV,\n ),\n block=[self._num_threads, 1, 1],\n stream=stream,\n min_blocks_per_mp=self._min_blocks,\n )\n\n @cute.kernel\n def kernel(\n self,\n mQ: cute.Tensor,\n mK: cute.Tensor,\n mQsf: cute.Tensor,\n mKsf: cute.Tensor,\n mPageTable: cute.Tensor,\n mMaxScore: cute.Tensor,\n mCuQ: cute.Tensor,\n mCuK: cute.Tensor,\n mQOffset: cute.Tensor,\n global_scale: cutlass.Float32, # q_global * k_global, applied at store\n max_k_tiles: cutlass.Int32,\n num_splits: cutlass.Int32,\n ):\n tidx, _, _ = cute.arch.thread_idx()\n split_idx, batch_idx, kv_head = cute.arch.block_idx()\n\n q_start = mCuQ[batch_idx]\n seqlen_q = mCuQ[batch_idx + 1] - q_start\n if cutlass.const_expr(self._paged):\n # mCuK holds per-request lengths on the paged path:\n # page_table supplies every KV address, so there is\n # no base offset to add.\n k_start = cutlass.Int32(0)\n seqlen_k = mCuK[batch_idx]\n else:\n k_start = mCuK[batch_idx]\n seqlen_k = mCuK[batch_idx + 1] - k_start\n num_kv_blocks = cute.ceil_div(seqlen_k, self._N)\n num_qo_heads = mQ.shape[1]\n\n tiled_mma, mma_atom, sfa_layout, sfb_layout = self._build_mma()\n sA_layout = self._ab_layout(self._M)\n sB_layout = self._ab_layout(self._N)\n\n @cute.struct\n class SharedStorage:\n sA: cute.struct.Align[\n cute.struct.MemRange[self.a_dtype, cute.cosize(sA_layout)], 1024\n ]\n sB: cute.struct.Align[\n cute.struct.MemRange[self.a_dtype, cute.cosize(sB_layout)], 1024\n ]\n sSFA: cute.struct.Align[\n cute.struct.MemRange[self.sf_dtype, cute.cosize(sfa_layout)], 1024\n ]\n sSFB: cute.struct.Align[\n cute.struct.MemRange[self.sf_dtype, cute.cosize(sfb_layout)], 1024\n ]\n sRed: cute.struct.Align[\n cute.struct.MemRange[cutlass.Float32, self._M * 2], 1024\n ]\n\n smem = cutlass.utils.SmemAllocator()\n storage = smem.allocate(SharedStorage)\n sA = storage.sA.get_tensor(sA_layout)\n sB = storage.sB.get_tensor(sB_layout)\n sSFA = storage.sSFA.get_tensor(sfa_layout)[None, None, 0]\n sSFB = storage.sSFB.get_tensor(sfb_layout)[None, None, 0]\n sfa_n = cute.cosize(sfa_layout)\n sfb_n = cute.cosize(sfb_layout)\n sSFA_u8 = cute.recast_tensor(\n storage.sSFA.get_tensor(cute.make_layout(sfa_n, stride=1)), Uint8\n )\n sSFB_u8 = cute.recast_tensor(\n storage.sSFB.get_tensor(cute.make_layout(sfb_n, stride=1)), Uint8\n )\n sRed = storage.sRed.get_tensor(cute.make_layout((self._M, 2), stride=(2, 1)))\n\n mQ_u32 = cute.recast_tensor(mQ, Uint32)\n mK_u32 = cute.recast_tensor(mK, Uint32)\n sA_u32 = cute.recast_tensor(sA, Uint32)\n sB_u32 = cute.recast_tensor(sB, Uint32)\n\n self._load_packed_q(mQ_u32, sA_u32, q_start, kv_head, seqlen_q, tidx)\n self._load_packed_q_sf(\n mQsf, sSFA_u8, q_start, kv_head, num_qo_heads, seqlen_q, tidx\n )\n self.cta_sync_barrier.arrive_and_wait()\n\n thr_mma = tiled_mma.get_slice(tidx)\n tCsA = thr_mma.partition_A(sA)\n tCsB = thr_mma.partition_B(sB)\n tCrA = tiled_mma.make_fragment_A(tCsA)\n tCrB = tiled_mma.make_fragment_B(tCsB)\n tCrSFA = self._partition_fragment_SFA(sSFA, thr_mma, tidx)\n tCrSFB = self._partition_fragment_SFB(sSFB, thr_mma, tidx)\n cS = cute.make_identity_tensor((self._M, self._N))\n tCcC = thr_mma.partition_C(cS)\n acc = cute.make_rmem_tensor(tCcC.shape[:3], self.acc_dtype)\n\n ldm_A = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(transpose=False, num_matrices=4), self.a_dtype\n )\n ldm_B = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(transpose=False, num_matrices=4), self.a_dtype\n )\n tiled_copy_A = cute.make_tiled_copy_A(ldm_A, tiled_mma)\n tiled_copy_B = cute.make_tiled_copy_B(ldm_B, tiled_mma)\n cp_sf = cute.make_copy_atom(cute.nvgpu.CopyUniversalOp(), self.sf_dtype)\n tiled_copy_SFA = cute.make_tiled_copy(\n cp_sf,\n self._get_layoutSFA_TV(tiled_mma),\n (\n cute.size(tiled_mma.permutation_mnk[0]),\n cute.size(tiled_mma.permutation_mnk[2]),\n ),\n )\n tiled_copy_SFB = cute.make_tiled_copy(\n cp_sf,\n self._get_layoutSFB_TV(tiled_mma),\n (\n cute.size(tiled_mma.permutation_mnk[1]),\n cute.size(tiled_mma.permutation_mnk[2]),\n ),\n )\n thr_A = tiled_copy_A.get_slice(tidx)\n thr_B = tiled_copy_B.get_slice(tidx)\n thr_SFA = tiled_copy_SFA.get_slice(tidx)\n thr_SFB = tiled_copy_SFB.get_slice(tidx)\n tCsA_cp = thr_A.partition_S(sA)\n tCrA_cp = thr_A.retile(tCrA)\n tCsB_cp = thr_B.partition_S(sB)\n tCrB_cp = thr_B.retile(tCrB)\n tCsSFA_cp = thr_SFA.partition_S(sSFA)\n tCrSFA_cp = thr_SFA.retile(tCrSFA)\n tCsSFB_cp = thr_SFB.partition_S(sSFB)\n tCrSFB_cp = thr_SFB.retile(tCrSFB)\n\n for kb in cutlass.range_constexpr(self.num_k_blocks):\n cute.copy(tiled_copy_A, tCsA_cp[None, None, kb], tCrA_cp[None, None, kb])\n cute.copy(\n tiled_copy_SFA,\n cute.filter_zeros(tCsSFA_cp),\n cute.filter_zeros(tCrSFA_cp),\n )\n\n n_iter = cute.ceil_div(max_k_tiles, num_splits)\n for it in cutlass.range(n_iter):\n kv_block = split_idx + it * num_splits\n if kv_block < num_kv_blocks:\n self.cta_sync_barrier.arrive_and_wait()\n k_pos0 = kv_block * self._N\n if cutlass.const_expr(self._paged):\n # paged: same page-table indirection as the general kernel; the\n # packed schedule only changes the Q gather, not the K load.\n page = mPageTable[batch_idx, kv_block]\n gK_pg = cute.recast_tensor(mK[page, kv_head, None, None], Uint32)\n self._load_packed(gK_pg, sB_u32, 0, k_pos0, seqlen_k, tidx)\n self._load_sf(\n mKsf,\n sSFB_u8,\n k_pos0,\n seqlen_k,\n (page * mK.shape[1] + kv_head) * self._N,\n 1,\n tidx,\n )\n else:\n k_tile0 = k_start + kv_block * self._N\n self._load_packed(\n mK_u32[None, kv_head, None],\n sB_u32,\n k_tile0,\n k_pos0,\n seqlen_k,\n tidx,\n )\n self._load_sf(\n mKsf,\n sSFB_u8,\n k_pos0,\n seqlen_k,\n k_tile0 * mK.shape[1] + kv_head,\n mK.shape[1],\n tidx,\n )\n self.cta_sync_barrier.arrive_and_wait()\n\n for kb in cutlass.range_constexpr(self.num_k_blocks):\n cute.copy(\n tiled_copy_B,\n tCsB_cp[None, None, kb],\n tCrB_cp[None, None, kb],\n )\n cute.copy(\n tiled_copy_SFB,\n cute.filter_zeros(tCsSFB_cp),\n cute.filter_zeros(tCrSFB_cp),\n )\n\n acc.fill(0.0)\n for mt in cutlass.range_constexpr(self.num_m_tiles):\n for nt in cutlass.range_constexpr(self.num_n_tiles):\n for kb in cutlass.range_constexpr(self.num_k_blocks):\n mma_atom.set(WarpField.SFA, tCrSFA[None, mt, kb].iterator)\n mma_atom.set(WarpField.SFB, tCrSFB[None, nt, kb].iterator)\n cute.gemm(\n mma_atom,\n acc[None, mt, nt],\n tCrA[None, mt, kb],\n tCrB[None, nt, kb],\n acc[None, mt, nt],\n )\n\n # Warp block-max epilogue, as in the general kernel; a packed row\n # maps to (local_head, token).\n acc_mn = self._make_acc_tensor_mn_view(acc)\n tScS_mn = self._make_acc_tensor_mn_view(tCcC)\n n_rows = cute.size(acc_mn.shape[0])\n thr_vmnk = tiled_mma.thr_layout_vmnk.get_flat_coord(tidx)\n nwarp = thr_vmnk[2]\n self.cta_sync_barrier.arrive_and_wait()\n for r in cutlass.range_constexpr(n_rows):\n row = tScS_mn[r, 0][0]\n token = row % self._PACK_Q_LEN\n if cutlass.const_expr(self._is_causal):\n col_limit = cutlass.min(\n token + mQOffset[batch_idx] + 1, seqlen_k\n )\n else:\n col_limit = seqlen_k\n for c in cutlass.range_constexpr(cute.size(acc_mn.shape[1])):\n k_pos = kv_block * self._N + tScS_mn[0, c][1]\n if cute.elem_less(col_limit, k_pos + 1):\n acc_mn[r, c] = -cutlass.Float32.inf\n tile_max = (\n acc_mn[r, None]\n .load()\n .reduce(cute.ReductionOp.MAX, -cutlass.Float32.inf, 0)\n )\n tile_max = self._threadquad_reduce_max(tile_max)\n sRed[row, nwarp] = tile_max\n self.cta_sync_barrier.arrive_and_wait()\n if nwarp == 0:\n for r in cutlass.range_constexpr(n_rows):\n row = tScS_mn[r, 0][0]\n local_head = row // self._PACK_Q_LEN\n token = row % self._PACK_Q_LEN\n head = kv_head * self._QHEAD_PER_KV + local_head\n both = cute.arch.fmax(sRed[row, 0], sRed[row, 1])\n if cute.elem_less(token, seqlen_q):\n mMaxScore[head, kv_block, q_start + token] = (\n both * global_scale\n )\n elif kv_block < max_k_tiles:\n if tidx < self._M:\n local_head2 = tidx // self._PACK_Q_LEN\n token2 = tidx % self._PACK_Q_LEN\n head2 = kv_head * self._QHEAD_PER_KV + local_head2\n if cute.elem_less(token2, seqlen_q):\n mMaxScore[\n head2, kv_block, q_start + token2\n ] = -cutlass.Float32.inf\n\n @cute.jit\n def _load_packed_q(self, mQ_u32, sX_u32, q_start, kv_head, seqlen_q, tidx):\n \"\"\"Gather the packed-fp4 Q tile into the 128-row tile; rows past seqlen_q are\n zero-filled (epilogue masks them).\"\"\"\n total = self._M * self._chunks_u32\n for it in cutlass.range_constexpr(total // self._num_threads):\n e = tidx + it * self._num_threads\n r = e // self._chunks_u32\n c = e % self._chunks_u32\n local_head = r // self._PACK_Q_LEN\n token = r % self._PACK_Q_LEN\n head = kv_head * self._QHEAD_PER_KV + local_head\n if cute.elem_less(token, seqlen_q):\n sX_u32[r, c] = mQ_u32[q_start + token, head, c]\n else:\n sX_u32[r, c] = Uint32(0)\n\n @cute.jit\n def _load_packed_q_sf(\n self, mQsf, sXsf_u8, q_start, kv_head, num_qo_heads, seqlen_q, tidx\n ):\n \"\"\"Fill the SF smem for the packed Q tile; SF logical row = (q_start + token)\n * num_qo_heads + head, the row order nvfp4_quantize produces.\"\"\"\n total = self._M * self._sf_per_row\n for it in cutlass.range_constexpr(total // self._num_threads):\n e = tidx + it * self._num_threads\n r = e // self._sf_per_row\n g = e % self._sf_per_row\n dst = self._sf_offset(r, g)\n local_head = r // self._PACK_Q_LEN\n token = r % self._PACK_Q_LEN\n head = kv_head * self._QHEAD_PER_KV + local_head\n if cute.elem_less(token, seqlen_q):\n sXsf_u8[dst] = mQsf[\n self._sf_offset((q_start + token) * num_qo_heads + head, g)\n ]\n else:\n sXsf_u8[dst] = Uint8(0)\n"},"after_code":{"kind":"string","value":"\"\"\"\nCopyright (c) 2026 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nNVFP4 tensor-core MSA proxy-score kernels for SM120/SM121: same contract as\n:mod:`proxy_score_sm12x`, with a general split-K and a packed-decode schedule.\n\nNo scalar stream schedule here (unlike the bf16 decode path): at 4-bit K the\nMMA pipeline hides the small tile's load latency, and the per-lane fp4 decode\nchain makes a scalar port slower, not faster.\n\"\"\"\n\nimport cuda.bindings.driver as cuda\nimport cutlass\nimport cutlass.cute as cute\nimport cutlass.pipeline as pipeline\nimport cutlass.utils.blackwell_helpers as sm120_utils\nfrom cutlass import Uint8, Uint32\nfrom cutlass.cute.nvgpu import warp\nfrom cutlass.cute.nvgpu.warp.mma import Field as WarpField\n\nfrom flashinfer.cute_dsl.utils import (\n sm120_make_smem_layout_sfa,\n sm120_make_smem_layout_sfb,\n)\n\n# NVFP4: 16-element scale groups (head_dim 128 -> 8 groups/row).\n_SF_VEC_SIZE = 16\n\n# Launch bound: cap registers so two CTAs stay resident per SM; one CTA cannot\n# hide the K-load latency and three would force spills. The split-K host\n# heuristic in proxy_score.py assumes this occupancy (target = 2 * num_sms).\n_MIN_BLOCKS_PER_MP = 2\n\n\nclass MsaProxyScoreFp4MmaSm12x:\n \"\"\"General NVFP4 tensor-core proxy schedule (any q length, flat or paged K);\n every query head scores independently.\"\"\"\n\n # The cuBLAS SF layout groups rows in blocks of 128, so a 128-row q-tile's\n # scale factors are a single contiguous block.\n _M = 128\n _N = 128 # kv-block: MSA scores per 128-token KV block\n _NUM_THREADS = 256 # 8 MMA warps for the (4,2,1) atom\n\n def __init__(\n self, head_dim: int = 128, is_causal: bool = True, paged: bool = False\n ):\n if head_dim != 128:\n raise ValueError(\"only head_dim == 128 is supported\")\n self._head_dim = head_dim\n self._is_causal = is_causal\n self._paged = paged\n self._num_threads = self._NUM_THREADS\n self.sf_vec_size = _SF_VEC_SIZE\n self.acc_dtype = cutlass.Float32\n self.a_dtype = cutlass.Float4E2M1FN\n self.sf_dtype = cutlass.Float8E4M3FN\n self.tile_shape_mnk = (self._M, self._N, head_dim)\n self._sf_per_row = head_dim // _SF_VEC_SIZE\n self._sf_tiles_n = (self._sf_per_row + 3) // 4\n self._chunks_u32 = head_dim // 8 # 16 Uint32 / packed-fp4 row\n # atom (4,2,1) over the m16n8k64 fp4 MMA -> group m64 n16 k64.\n self._atom_shape = (4, 2, 1)\n self.num_m_tiles = self._M // (16 * self._atom_shape[0])\n self.num_n_tiles = self._N // (8 * self._atom_shape[1])\n self.num_k_blocks = head_dim // 64\n self._min_blocks = _MIN_BLOCKS_PER_MP\n\n self.cta_sync_barrier = pipeline.NamedBarrier(\n barrier_id=1, num_threads=self._num_threads\n )\n\n @cute.jit\n def _build_mma(self):\n \"\"\"fp4 tiled MMA + bare atom + SF smem layouts. Built inside the jit\n context (``make_layout`` / ``get_permutation_mnk`` need an MLIR context).\"\"\"\n mma_op = cute.nvgpu.warp.MmaMXF4NVF4Op(\n self.a_dtype, self.acc_dtype, self.sf_dtype\n )\n permutation_mnk = sm120_utils.get_permutation_mnk(\n self.tile_shape_mnk, self.sf_vec_size, False\n )\n tiled_mma = cute.make_tiled_mma(\n mma_op,\n cute.make_layout(self._atom_shape),\n permutation_mnk=permutation_mnk,\n )\n mma_atom = cute.make_mma_atom(mma_op)\n sfa_layout = sm120_make_smem_layout_sfa(\n tiled_mma, self.tile_shape_mnk, self.sf_vec_size, 1\n )\n sfb_layout = sm120_make_smem_layout_sfb(\n tiled_mma, self.tile_shape_mnk, self.sf_vec_size, 1\n )\n return tiled_mma, mma_atom, sfa_layout, sfb_layout\n\n def _ab_layout(self, mode_n: int):\n return cute.make_layout((mode_n, self._head_dim), stride=(self._head_dim, 1))\n\n @cute.jit\n def __call__(\n self,\n mQ: cute.Tensor, # (total_q, Hq, head_dim//2) packed e2m1, uint8\n mK: cute.Tensor, # flat (total_k,Hkv,hd/2) | paged (pages,Hkv,128,hd/2) u8\n mQsf: cute.Tensor, # uint8 e4m3 scales, cuBLAS 128x4 tiled\n mKsf: cute.Tensor, # uint8 e4m3 scales, cuBLAS 128x4 tiled\n mPageTable: cute.Tensor, # (B, max_pages) int32 paged; dummy (1,1) flat\n mMaxScore: cute.Tensor, # (Hq, max_k_tiles, total_q) f32\n mCuQ: cute.Tensor, # (B + 1,) int32\n mCuK: cute.Tensor, # (B + 1,) int32\n mQOffset: cute.Tensor, # (B,) int32 causal offset\n q_global_scale: cutlass.Float32,\n k_global_scale: cutlass.Float32,\n max_seqlen_q: cutlass.Int32,\n batch_size: cutlass.Int32,\n num_qo_heads: cutlass.Int32,\n max_k_tiles: cutlass.Int32,\n num_splits: cutlass.Int32,\n stream: cuda.CUstream,\n ):\n # Split-K grid, as in proxy_score_sm12x.\n self.kernel(\n mQ,\n mK,\n mQsf,\n mKsf,\n mPageTable,\n mMaxScore,\n mCuQ,\n mCuK,\n mQOffset,\n q_global_scale * k_global_scale,\n max_k_tiles,\n num_splits,\n ).launch(\n grid=(\n cute.ceil_div(max_seqlen_q, self._M) * num_splits,\n batch_size,\n num_qo_heads,\n ),\n block=[self._num_threads, 1, 1],\n stream=stream,\n min_blocks_per_mp=self._min_blocks,\n )\n\n @cute.kernel\n def kernel(\n self,\n mQ: cute.Tensor,\n mK: cute.Tensor,\n mQsf: cute.Tensor,\n mKsf: cute.Tensor,\n mPageTable: cute.Tensor,\n mMaxScore: cute.Tensor,\n mCuQ: cute.Tensor,\n mCuK: cute.Tensor,\n mQOffset: cute.Tensor,\n global_scale: cutlass.Float32, # q_global * k_global, applied at store\n max_k_tiles: cutlass.Int32,\n num_splits: cutlass.Int32,\n ):\n tidx, _, _ = cute.arch.thread_idx()\n bx, batch_idx, qo_head = cute.arch.block_idx()\n # grid x packs (m_block, split), as in the bf16 kernel.\n m_block = bx // num_splits\n split_idx = bx % num_splits\n\n q_start = mCuQ[batch_idx]\n seqlen_q = mCuQ[batch_idx + 1] - q_start\n if cutlass.const_expr(self._paged):\n # mCuK holds per-request lengths on the paged path:\n # page_table supplies every KV address, so there is\n # no base offset to add.\n k_start = cutlass.Int32(0)\n seqlen_k = mCuK[batch_idx]\n else:\n k_start = mCuK[batch_idx]\n seqlen_k = mCuK[batch_idx + 1] - k_start\n num_kv_blocks = cute.ceil_div(seqlen_k, self._N)\n group_size = mQ.shape[1] // mK.shape[1]\n kv_head = qo_head // group_size\n\n if m_block * self._M < seqlen_q:\n tiled_mma, mma_atom, sfa_layout, sfb_layout = self._build_mma()\n sA_layout = self._ab_layout(self._M)\n sB_layout = self._ab_layout(self._N)\n\n @cute.struct\n class SharedStorage:\n sA: cute.struct.Align[\n cute.struct.MemRange[self.a_dtype, cute.cosize(sA_layout)], 1024\n ]\n sB: cute.struct.Align[\n cute.struct.MemRange[self.a_dtype, cute.cosize(sB_layout)], 1024\n ]\n sSFA: cute.struct.Align[\n cute.struct.MemRange[self.sf_dtype, cute.cosize(sfa_layout)], 1024\n ]\n sSFB: cute.struct.Align[\n cute.struct.MemRange[self.sf_dtype, cute.cosize(sfb_layout)], 1024\n ]\n # Warp-epilogue cross-warp scratch: one f32 per (q-row, N-warp).\n # 1KB vs a full 64KB [M,N] scatter, so smem stops capping occupancy.\n sRed: cute.struct.Align[\n cute.struct.MemRange[cutlass.Float32, self._M * 2], 1024\n ]\n\n smem = cutlass.utils.SmemAllocator()\n storage = smem.allocate(SharedStorage)\n sA = storage.sA.get_tensor(sA_layout)\n sB = storage.sB.get_tensor(sB_layout)\n # sm120 SF layouts append a (size-1) stage mode; drop it for the MMA\n # partition. The compound layout's byte offsets for one 128-row/K=128 tile\n # equal the cuBLAS 128x4 layout (== _sf_offset), so the fill is a flat view.\n sSFA = storage.sSFA.get_tensor(sfa_layout)[None, None, 0]\n sSFB = storage.sSFB.get_tensor(sfb_layout)[None, None, 0]\n sfa_n = cute.cosize(sfa_layout)\n sfb_n = cute.cosize(sfb_layout)\n sSFA_u8 = cute.recast_tensor(\n storage.sSFA.get_tensor(cute.make_layout(sfa_n, stride=1)), Uint8\n )\n sSFB_u8 = cute.recast_tensor(\n storage.sSFB.get_tensor(cute.make_layout(sfb_n, stride=1)), Uint8\n )\n sRed = storage.sRed.get_tensor(\n cute.make_layout((self._M, 2), stride=(2, 1))\n )\n\n mQ_u32 = cute.recast_tensor(mQ, Uint32)\n mK_u32 = cute.recast_tensor(mK, Uint32)\n sA_u32 = cute.recast_tensor(sA, Uint32)\n sB_u32 = cute.recast_tensor(sB, Uint32)\n\n # Q is always flat (current query tokens, never paged): read absolute\n # row q_tile0+m, mask on the in-tile position m_block*M+m.\n q_tile0 = q_start + m_block * self._M\n q_pos0 = m_block * self._M\n self._load_packed(\n mQ_u32[None, qo_head, None], sA_u32, q_tile0, q_pos0, seqlen_q, tidx\n )\n self._load_sf(\n mQsf,\n sSFA_u8,\n q_pos0,\n seqlen_q,\n q_tile0 * mQ.shape[1] + qo_head,\n mQ.shape[1],\n tidx,\n )\n self.cta_sync_barrier.arrive_and_wait()\n\n thr_mma = tiled_mma.get_slice(tidx)\n tCsA = thr_mma.partition_A(sA)\n tCsB = thr_mma.partition_B(sB)\n tCrA = tiled_mma.make_fragment_A(tCsA)\n tCrB = tiled_mma.make_fragment_B(tCsB)\n tCrSFA = self._partition_fragment_SFA(sSFA, thr_mma, tidx)\n tCrSFB = self._partition_fragment_SFB(sSFB, thr_mma, tidx)\n cS = cute.make_identity_tensor((self._M, self._N))\n tCcC = thr_mma.partition_C(cS)\n acc = cute.make_rmem_tensor(tCcC.shape[:3], self.acc_dtype)\n\n ldm_A = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(transpose=False, num_matrices=4), self.a_dtype\n )\n ldm_B = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(transpose=False, num_matrices=4), self.a_dtype\n )\n tiled_copy_A = cute.make_tiled_copy_A(ldm_A, tiled_mma)\n tiled_copy_B = cute.make_tiled_copy_B(ldm_B, tiled_mma)\n cp_sf = cute.make_copy_atom(cute.nvgpu.CopyUniversalOp(), self.sf_dtype)\n tiled_copy_SFA = cute.make_tiled_copy(\n cp_sf,\n self._get_layoutSFA_TV(tiled_mma),\n (\n cute.size(tiled_mma.permutation_mnk[0]),\n cute.size(tiled_mma.permutation_mnk[2]),\n ),\n )\n tiled_copy_SFB = cute.make_tiled_copy(\n cp_sf,\n self._get_layoutSFB_TV(tiled_mma),\n (\n cute.size(tiled_mma.permutation_mnk[1]),\n cute.size(tiled_mma.permutation_mnk[2]),\n ),\n )\n thr_A = tiled_copy_A.get_slice(tidx)\n thr_B = tiled_copy_B.get_slice(tidx)\n thr_SFA = tiled_copy_SFA.get_slice(tidx)\n thr_SFB = tiled_copy_SFB.get_slice(tidx)\n tCsA_cp = thr_A.partition_S(sA)\n tCrA_cp = thr_A.retile(tCrA)\n tCsB_cp = thr_B.partition_S(sB)\n tCrB_cp = thr_B.retile(tCrB)\n tCsSFA_cp = thr_SFA.partition_S(sSFA)\n tCrSFA_cp = thr_SFA.retile(tCrSFA)\n tCsSFB_cp = thr_SFB.partition_S(sSFB)\n tCrSFB_cp = thr_SFB.retile(tCrSFB)\n\n # Q fragments load once (sA / sSFA reused across all kv-blocks)\n for kb in cutlass.range_constexpr(self.num_k_blocks):\n cute.copy(\n tiled_copy_A, tCsA_cp[None, None, kb], tCrA_cp[None, None, kb]\n )\n cute.copy(\n tiled_copy_SFA,\n cute.filter_zeros(tCsSFA_cp),\n cute.filter_zeros(tCrSFA_cp),\n )\n\n # Split-K stride + causal skip, as in the bf16 kernel.\n if cutlass.const_expr(self._is_causal):\n causal_last = (\n m_block * self._M + (self._M - 1) + mQOffset[batch_idx]\n ) // self._N\n last_block = cutlass.min(causal_last, num_kv_blocks - 1)\n else:\n last_block = num_kv_blocks - 1\n\n n_iter = cute.ceil_div(max_k_tiles, num_splits)\n for it in cutlass.range(n_iter):\n kv_block = split_idx + it * num_splits\n if kv_block <= last_block:\n self.cta_sync_barrier.arrive_and_wait()\n k_pos0 = kv_block * self._N\n if cutlass.const_expr(self._paged):\n # paged: kv_block maps to a 128-row page via the page table.\n # Read it page-local (read_base 0) and mask on the global\n # position; SF row = (page*Hkv + kv_head)*N + token, stride 1.\n page = mPageTable[batch_idx, kv_block]\n gK_pg = cute.recast_tensor(\n mK[page, kv_head, None, None], Uint32\n )\n self._load_packed(gK_pg, sB_u32, 0, k_pos0, seqlen_k, tidx)\n self._load_sf(\n mKsf,\n sSFB_u8,\n k_pos0,\n seqlen_k,\n (page * mK.shape[1] + kv_head) * self._N,\n 1,\n tidx,\n )\n else:\n # flat: read absolute row k_tile0+m, SF row = token*Hkv+kv_head.\n k_tile0 = k_start + kv_block * self._N\n self._load_packed(\n mK_u32[None, kv_head, None],\n sB_u32,\n k_tile0,\n k_pos0,\n seqlen_k,\n tidx,\n )\n self._load_sf(\n mKsf,\n sSFB_u8,\n k_pos0,\n seqlen_k,\n k_tile0 * mK.shape[1] + kv_head,\n mK.shape[1],\n tidx,\n )\n self.cta_sync_barrier.arrive_and_wait()\n\n for kb in cutlass.range_constexpr(self.num_k_blocks):\n cute.copy(\n tiled_copy_B,\n tCsB_cp[None, None, kb],\n tCrB_cp[None, None, kb],\n )\n cute.copy(\n tiled_copy_SFB,\n cute.filter_zeros(tCsSFB_cp),\n cute.filter_zeros(tCrSFB_cp),\n )\n\n acc.fill(0.0)\n for mt in cutlass.range_constexpr(self.num_m_tiles):\n for nt in cutlass.range_constexpr(self.num_n_tiles):\n for kb in cutlass.range_constexpr(self.num_k_blocks):\n mma_atom.set(\n WarpField.SFA, tCrSFA[None, mt, kb].iterator\n )\n mma_atom.set(\n WarpField.SFB, tCrSFB[None, nt, kb].iterator\n )\n cute.gemm(\n mma_atom,\n acc[None, mt, nt],\n tCrA[None, mt, kb],\n tCrB[None, nt, kb],\n acc[None, mt, nt],\n )\n\n # Warp-level block-max epilogue (no scatter buffer): each thread\n # reduces its N columns, a thread-quad shuffle yields the per-q-row\n # warp max, and the two N-warps combine through sRed.\n acc_mn = self._make_acc_tensor_mn_view(acc)\n tScS_mn = self._make_acc_tensor_mn_view(tCcC)\n n_rows = cute.size(acc_mn.shape[0])\n thr_vmnk = tiled_mma.thr_layout_vmnk.get_flat_coord(tidx)\n nwarp = thr_vmnk[2]\n self.cta_sync_barrier.arrive_and_wait()\n for r in cutlass.range_constexpr(n_rows):\n row = tScS_mn[r, 0][0]\n q_loc = m_block * self._M + row\n if cutlass.const_expr(self._is_causal):\n col_limit = cutlass.min(\n q_loc + mQOffset[batch_idx] + 1, seqlen_k\n )\n else:\n col_limit = seqlen_k\n for c in cutlass.range_constexpr(cute.size(acc_mn.shape[1])):\n k_pos = kv_block * self._N + tScS_mn[0, c][1]\n if cute.elem_less(col_limit, k_pos + 1):\n acc_mn[r, c] = -cutlass.Float32.inf\n tile_max = (\n acc_mn[r, None]\n .load()\n .reduce(cute.ReductionOp.MAX, -cutlass.Float32.inf, 0)\n )\n tile_max = self._threadquad_reduce_max(tile_max)\n sRed[row, nwarp] = tile_max\n self.cta_sync_barrier.arrive_and_wait()\n # Combine the two N-warps; one writer per q-row (the nwarp-0\n # warp owns the write).\n if nwarp == 0:\n for r in cutlass.range_constexpr(n_rows):\n row = tScS_mn[r, 0][0]\n q_loc = m_block * self._M + row\n both = cute.arch.fmax(sRed[row, 0], sRed[row, 1])\n if q_loc < seqlen_q:\n mMaxScore[qo_head, kv_block, q_start + q_loc] = (\n both * global_scale\n )\n elif kv_block < max_k_tiles:\n if tidx < self._M:\n q_loc2 = m_block * self._M + tidx\n if q_loc2 < seqlen_q:\n mMaxScore[\n qo_head, kv_block, q_start + q_loc2\n ] = -cutlass.Float32.inf\n\n @cute.jit\n def _sf_offset(self, srow, scol):\n \"\"\"cuBLAS 128x4 tiled SF byte offset; for one 128-row K=128 tile it equals\n the SM120 SF smem layout, so sSFA/sSFB fill by this offset directly.\"\"\"\n srow_in = srow % 128\n return (\n ((srow // 128) * self._sf_tiles_n + scol // 4) * 512\n + (srow_in % 32) * 16\n + (srow_in // 32) * 4\n + scol % 4\n )\n\n @cute.jit\n def _load_packed(self, gX_u32, sX_u32, read_base, pos_base, seqlen, tidx):\n \"\"\"read_base is decoupled from pos_base so the paged path reads a page-local\n tile (read_base 0) but masks on the global token position pos_base + m.\"\"\"\n rows = cute.size(sX_u32.shape[0])\n total = rows * self._chunks_u32\n for it in cutlass.range_constexpr(total // self._num_threads):\n e = tidx + it * self._num_threads\n m = e // self._chunks_u32\n c = e % self._chunks_u32\n if cute.elem_less(pos_base + m, seqlen):\n sX_u32[m, c] = gX_u32[read_base + m, c]\n else:\n sX_u32[m, c] = Uint32(0)\n\n @cute.jit\n def _load_sf(self, mXsf, sXsf_u8, pos_base, seqlen, sf_row_base, sf_stride, tidx):\n \"\"\"Fill the SF smem from the e4m3 buffer: flat passes row base token*heads+head\n with stride num_heads; paged passes (page*Hkv + kv_head)*N with stride 1.\"\"\"\n total = self._M * self._sf_per_row\n for it in cutlass.range_constexpr(total // self._num_threads):\n e = tidx + it * self._num_threads\n m = e // self._sf_per_row\n g = e % self._sf_per_row\n dst = self._sf_offset(m, g)\n if cute.elem_less(pos_base + m, seqlen):\n sXsf_u8[dst] = mXsf[self._sf_offset(sf_row_base + m * sf_stride, g)]\n else:\n sXsf_u8[dst] = Uint8(0)\n\n def _partition_fragment_SFA(self, sfa_tensor, thr_mma, tidx):\n thrfrg = self._thrfrg_SFA(sfa_tensor.layout, thr_mma)\n thr_tensor = cute.make_tensor(sfa_tensor.iterator, thrfrg)\n thr_vmnk = thr_mma.thr_layout_vmnk.get_flat_coord(tidx)\n thr_vmk = (thr_vmnk[0], (thr_vmnk[1], thr_vmnk[3]))\n part = thr_tensor[thr_vmk, (None, None)]\n part = cute.group_modes(cute.flatten(part), 0, 2)\n return cute.make_fragment_like(part)\n\n def _partition_fragment_SFB(self, sfb_tensor, thr_mma, tidx):\n thrfrg = self._thrfrg_SFB(sfb_tensor.layout, thr_mma)\n thr_tensor = cute.make_tensor(sfb_tensor.iterator, thrfrg)\n thr_vmnk = thr_mma.thr_layout_vmnk.get_flat_coord(tidx)\n thr_vnk = (thr_vmnk[0], (thr_vmnk[2], thr_vmnk[3]))\n part = thr_tensor[thr_vnk, (None, None)]\n part = cute.group_modes(cute.flatten(part), 0, 2)\n part = cute.group_modes(part, 1, 3)\n return cute.make_fragment_like(part)\n\n def _thrfrg_SFA(self, sfa_tensor, tiled_mma):\n atom_shape_mnk = tiled_mma.shape_mnk\n atom_sfa_layout = cute.make_layout(\n shape=((2, 2, 8), 64), stride=((8, 0, 1), 16)\n )\n permutation_mnk = tiled_mma.permutation_mnk\n thr_layout_vmnk = tiled_mma.thr_layout_vmnk\n t_tile = (permutation_mnk[0], permutation_mnk[2])\n t_tensor = cute.logical_divide(sfa_tensor, t_tile)\n a_tile = (\n cute.make_layout((atom_shape_mnk[0])),\n cute.make_layout((atom_shape_mnk[2])),\n )\n a_tensor = cute.zipped_divide(t_tensor, a_tile)\n tv_tensor = cute.composition(a_tensor, (atom_sfa_layout, None))\n thr_tile = (\n None,\n (\n cute.make_layout(cute.size(thr_layout_vmnk[1])),\n cute.make_layout(cute.size(thr_layout_vmnk[3])),\n ),\n )\n return cute.zipped_divide(tv_tensor, thr_tile)\n\n def _thrfrg_SFB(self, sfb_tensor, tiled_mma):\n atom_shape_mnk = tiled_mma.shape_mnk\n atom_sfb_layout = cute.make_layout(shape=((4, 8), 64), stride=((0, 1), 8))\n permutation_mnk = tiled_mma.permutation_mnk\n thr_layout_vmnk = tiled_mma.thr_layout_vmnk\n t_tile = (permutation_mnk[1], permutation_mnk[2])\n t_tensor = cute.logical_divide(sfb_tensor, t_tile)\n a_tile = (\n cute.make_layout((atom_shape_mnk[1])),\n cute.make_layout((atom_shape_mnk[2])),\n )\n a_tensor = cute.zipped_divide(t_tensor, a_tile)\n tv_tensor = cute.composition(a_tensor, (atom_sfb_layout, None))\n thr_tile = (\n None,\n (\n cute.make_layout(cute.size(thr_layout_vmnk[2])),\n cute.make_layout(cute.size(thr_layout_vmnk[3])),\n ),\n )\n return cute.zipped_divide(tv_tensor, thr_tile)\n\n def _get_layoutSFA_TV(self, tiled_mma):\n perm_m = tiled_mma.permutation_mnk[0]\n perm_k = tiled_mma.permutation_mnk[2]\n ref_A = cute.make_layout((cute.size(perm_m), cute.size(perm_k)))\n thr_layout_vmnk = tiled_mma.thr_layout_vmnk\n atile = (\n None,\n (\n cute.make_layout(\n shape=(\n cute.size(thr_layout_vmnk[1]),\n cute.size(thr_layout_vmnk[2]),\n ),\n stride=(1, 0),\n ),\n None,\n ),\n )\n thridx_2_thrid = cute.right_inverse(thr_layout_vmnk)\n thrfrg_sfa = self._thrfrg_SFA(ref_A, tiled_mma)\n layout_tv = cute.composition(thrfrg_sfa, (atile, None))\n return cute.composition(layout_tv, (thridx_2_thrid, None))\n\n def _get_layoutSFB_TV(self, tiled_mma):\n perm_n = tiled_mma.permutation_mnk[1]\n perm_k = tiled_mma.permutation_mnk[2]\n ref_B = cute.make_layout((cute.size(perm_n), cute.size(perm_k)))\n thr_layout_vmnk = tiled_mma.thr_layout_vmnk\n atile = (\n None,\n (\n cute.make_layout(\n shape=(\n cute.size(thr_layout_vmnk[1]),\n cute.size(thr_layout_vmnk[2]),\n ),\n stride=(0, 1),\n ),\n None,\n ),\n )\n thridx_2_thrid = cute.right_inverse(thr_layout_vmnk)\n thrfrg_sfb = self._thrfrg_SFB(ref_B, tiled_mma)\n layout_tv = cute.composition(thrfrg_sfb, (atile, None))\n return cute.composition(layout_tv, (thridx_2_thrid, None))\n\n @cute.jit\n def _threadquad_reduce_max(self, val):\n # Max across the 4 lanes of an m16n8 row-quad (the N lanes within a warp)\n val = cute.arch.fmax(\n val,\n cute.arch.shuffle_sync_bfly(val, offset=2, mask=-1, mask_and_clamp=31),\n )\n val = cute.arch.fmax(\n val,\n cute.arch.shuffle_sync_bfly(val, offset=1, mask=-1, mask_and_clamp=31),\n )\n return val\n\n def _make_acc_tensor_mn_view(self, acc: cute.Tensor) -> cute.Tensor:\n acc_layout_col_major = cute.make_layout(acc.layout.shape)\n acc_layout_mn = cute.make_layout(\n (\n (acc_layout_col_major.shape[0][1], acc_layout_col_major.shape[1]),\n (acc_layout_col_major.shape[0][0], acc_layout_col_major.shape[2]),\n ),\n stride=(\n (acc_layout_col_major.stride[0][1], acc_layout_col_major.stride[1]),\n (acc_layout_col_major.stride[0][0], acc_layout_col_major.stride[2]),\n ),\n )\n acc_layout_mn = cute.composition(acc.layout, acc_layout_mn)\n return cute.make_tensor(acc.iterator, acc_layout_mn)\n\n\nclass MsaProxyScoreFp4MmaDecodePackedSm12x(MsaProxyScoreFp4MmaSm12x):\n \"\"\"Head-fused packed-decode fp4 schedule: packs qhead_per_kv heads x pack_q_len\n tokens into the 128 MMA rows so the shared index-K is read once per kv_head.\"\"\"\n\n _PACK_Q_LEN = 8\n _QHEAD_PER_KV = 16\n\n def __init__(\n self,\n head_dim: int = 128,\n is_causal: bool = True,\n paged: bool = False,\n qhead_per_kv: int = _QHEAD_PER_KV,\n pack_q_len: int = _PACK_Q_LEN,\n qoff_default: bool = False,\n ):\n super().__init__(head_dim=head_dim, is_causal=is_causal, paged=paged)\n if qhead_per_kv * pack_q_len != self._M:\n raise ValueError(\n f\"qhead_per_kv * pack_q_len must equal the {self._M}-row MMA tile, \"\n f\"got {qhead_per_kv} x {pack_q_len}\"\n )\n # Instance attrs shadow the class defaults; they are constexpr-baked into the\n # gather/epilogue, so each factorization compiles to its own kernel.\n self._QHEAD_PER_KV = qhead_per_kv\n self._PACK_Q_LEN = pack_q_len\n # True: right-aligned decode; the causal offset is computed in-kernel.\n self._qoff_default = qoff_default\n\n @cute.jit\n def __call__(\n self,\n mQ: cute.Tensor,\n mK: cute.Tensor,\n mQsf: cute.Tensor,\n mKsf: cute.Tensor,\n mPageTable: cute.Tensor,\n mMaxScore: cute.Tensor,\n mCuQ: cute.Tensor,\n mCuK: cute.Tensor,\n mQOffset: cute.Tensor,\n q_global_scale: cutlass.Float32,\n k_global_scale: cutlass.Float32,\n max_seqlen_q: cutlass.Int32,\n batch_size: cutlass.Int32,\n num_qo_heads: cutlass.Int32,\n max_k_tiles: cutlass.Int32,\n num_splits: cutlass.Int32,\n stream: cuda.CUstream,\n ):\n # One CTA per (split, batch, kv_head), as in the bf16 packed kernel:\n # the shared index-K is read once per kv_head.\n self.kernel(\n mQ,\n mK,\n mQsf,\n mKsf,\n mPageTable,\n mMaxScore,\n mCuQ,\n mCuK,\n mQOffset,\n q_global_scale * k_global_scale,\n max_k_tiles,\n num_splits,\n ).launch(\n grid=(\n num_splits,\n batch_size,\n num_qo_heads // self._QHEAD_PER_KV,\n ),\n block=[self._num_threads, 1, 1],\n stream=stream,\n min_blocks_per_mp=self._min_blocks,\n )\n\n @cute.kernel\n def kernel(\n self,\n mQ: cute.Tensor,\n mK: cute.Tensor,\n mQsf: cute.Tensor,\n mKsf: cute.Tensor,\n mPageTable: cute.Tensor,\n mMaxScore: cute.Tensor,\n mCuQ: cute.Tensor,\n mCuK: cute.Tensor,\n mQOffset: cute.Tensor,\n global_scale: cutlass.Float32, # q_global * k_global, applied at store\n max_k_tiles: cutlass.Int32,\n num_splits: cutlass.Int32,\n ):\n tidx, _, _ = cute.arch.thread_idx()\n split_idx, batch_idx, kv_head = cute.arch.block_idx()\n\n q_start = mCuQ[batch_idx]\n seqlen_q = mCuQ[batch_idx + 1] - q_start\n if cutlass.const_expr(self._paged):\n # mCuK holds per-request lengths on the paged path:\n # page_table supplies every KV address, so there is\n # no base offset to add.\n k_start = cutlass.Int32(0)\n seqlen_k = mCuK[batch_idx]\n else:\n k_start = mCuK[batch_idx]\n seqlen_k = mCuK[batch_idx + 1] - k_start\n num_kv_blocks = cute.ceil_div(seqlen_k, self._N)\n num_qo_heads = mQ.shape[1]\n q_off = cutlass.Int32(0)\n if cutlass.const_expr(self._is_causal):\n if cutlass.const_expr(self._qoff_default):\n q_off = seqlen_k - seqlen_q\n else:\n q_off = mQOffset[batch_idx]\n\n tiled_mma, mma_atom, sfa_layout, sfb_layout = self._build_mma()\n sA_layout = self._ab_layout(self._M)\n sB_layout = self._ab_layout(self._N)\n\n @cute.struct\n class SharedStorage:\n sA: cute.struct.Align[\n cute.struct.MemRange[self.a_dtype, cute.cosize(sA_layout)], 1024\n ]\n sB: cute.struct.Align[\n cute.struct.MemRange[self.a_dtype, cute.cosize(sB_layout)], 1024\n ]\n sSFA: cute.struct.Align[\n cute.struct.MemRange[self.sf_dtype, cute.cosize(sfa_layout)], 1024\n ]\n sSFB: cute.struct.Align[\n cute.struct.MemRange[self.sf_dtype, cute.cosize(sfb_layout)], 1024\n ]\n sRed: cute.struct.Align[\n cute.struct.MemRange[cutlass.Float32, self._M * 2], 1024\n ]\n\n smem = cutlass.utils.SmemAllocator()\n storage = smem.allocate(SharedStorage)\n sA = storage.sA.get_tensor(sA_layout)\n sB = storage.sB.get_tensor(sB_layout)\n sSFA = storage.sSFA.get_tensor(sfa_layout)[None, None, 0]\n sSFB = storage.sSFB.get_tensor(sfb_layout)[None, None, 0]\n sfa_n = cute.cosize(sfa_layout)\n sfb_n = cute.cosize(sfb_layout)\n sSFA_u8 = cute.recast_tensor(\n storage.sSFA.get_tensor(cute.make_layout(sfa_n, stride=1)), Uint8\n )\n sSFB_u8 = cute.recast_tensor(\n storage.sSFB.get_tensor(cute.make_layout(sfb_n, stride=1)), Uint8\n )\n sRed = storage.sRed.get_tensor(cute.make_layout((self._M, 2), stride=(2, 1)))\n\n mQ_u32 = cute.recast_tensor(mQ, Uint32)\n mK_u32 = cute.recast_tensor(mK, Uint32)\n sA_u32 = cute.recast_tensor(sA, Uint32)\n sB_u32 = cute.recast_tensor(sB, Uint32)\n\n self._load_packed_q(mQ_u32, sA_u32, q_start, kv_head, seqlen_q, tidx)\n self._load_packed_q_sf(\n mQsf, sSFA_u8, q_start, kv_head, num_qo_heads, seqlen_q, tidx\n )\n self.cta_sync_barrier.arrive_and_wait()\n\n thr_mma = tiled_mma.get_slice(tidx)\n tCsA = thr_mma.partition_A(sA)\n tCsB = thr_mma.partition_B(sB)\n tCrA = tiled_mma.make_fragment_A(tCsA)\n tCrB = tiled_mma.make_fragment_B(tCsB)\n tCrSFA = self._partition_fragment_SFA(sSFA, thr_mma, tidx)\n tCrSFB = self._partition_fragment_SFB(sSFB, thr_mma, tidx)\n cS = cute.make_identity_tensor((self._M, self._N))\n tCcC = thr_mma.partition_C(cS)\n acc = cute.make_rmem_tensor(tCcC.shape[:3], self.acc_dtype)\n\n ldm_A = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(transpose=False, num_matrices=4), self.a_dtype\n )\n ldm_B = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(transpose=False, num_matrices=4), self.a_dtype\n )\n tiled_copy_A = cute.make_tiled_copy_A(ldm_A, tiled_mma)\n tiled_copy_B = cute.make_tiled_copy_B(ldm_B, tiled_mma)\n cp_sf = cute.make_copy_atom(cute.nvgpu.CopyUniversalOp(), self.sf_dtype)\n tiled_copy_SFA = cute.make_tiled_copy(\n cp_sf,\n self._get_layoutSFA_TV(tiled_mma),\n (\n cute.size(tiled_mma.permutation_mnk[0]),\n cute.size(tiled_mma.permutation_mnk[2]),\n ),\n )\n tiled_copy_SFB = cute.make_tiled_copy(\n cp_sf,\n self._get_layoutSFB_TV(tiled_mma),\n (\n cute.size(tiled_mma.permutation_mnk[1]),\n cute.size(tiled_mma.permutation_mnk[2]),\n ),\n )\n thr_A = tiled_copy_A.get_slice(tidx)\n thr_B = tiled_copy_B.get_slice(tidx)\n thr_SFA = tiled_copy_SFA.get_slice(tidx)\n thr_SFB = tiled_copy_SFB.get_slice(tidx)\n tCsA_cp = thr_A.partition_S(sA)\n tCrA_cp = thr_A.retile(tCrA)\n tCsB_cp = thr_B.partition_S(sB)\n tCrB_cp = thr_B.retile(tCrB)\n tCsSFA_cp = thr_SFA.partition_S(sSFA)\n tCrSFA_cp = thr_SFA.retile(tCrSFA)\n tCsSFB_cp = thr_SFB.partition_S(sSFB)\n tCrSFB_cp = thr_SFB.retile(tCrSFB)\n\n for kb in cutlass.range_constexpr(self.num_k_blocks):\n cute.copy(tiled_copy_A, tCsA_cp[None, None, kb], tCrA_cp[None, None, kb])\n cute.copy(\n tiled_copy_SFA,\n cute.filter_zeros(tCsSFA_cp),\n cute.filter_zeros(tCrSFA_cp),\n )\n\n n_iter = cute.ceil_div(max_k_tiles, num_splits)\n for it in cutlass.range(n_iter):\n kv_block = split_idx + it * num_splits\n if kv_block < num_kv_blocks:\n self.cta_sync_barrier.arrive_and_wait()\n k_pos0 = kv_block * self._N\n if cutlass.const_expr(self._paged):\n # paged: same page-table indirection as the general kernel; the\n # packed schedule only changes the Q gather, not the K load.\n page = mPageTable[batch_idx, kv_block]\n gK_pg = cute.recast_tensor(mK[page, kv_head, None, None], Uint32)\n self._load_packed(gK_pg, sB_u32, 0, k_pos0, seqlen_k, tidx)\n self._load_sf(\n mKsf,\n sSFB_u8,\n k_pos0,\n seqlen_k,\n (page * mK.shape[1] + kv_head) * self._N,\n 1,\n tidx,\n )\n else:\n k_tile0 = k_start + kv_block * self._N\n self._load_packed(\n mK_u32[None, kv_head, None],\n sB_u32,\n k_tile0,\n k_pos0,\n seqlen_k,\n tidx,\n )\n self._load_sf(\n mKsf,\n sSFB_u8,\n k_pos0,\n seqlen_k,\n k_tile0 * mK.shape[1] + kv_head,\n mK.shape[1],\n tidx,\n )\n self.cta_sync_barrier.arrive_and_wait()\n\n for kb in cutlass.range_constexpr(self.num_k_blocks):\n cute.copy(\n tiled_copy_B,\n tCsB_cp[None, None, kb],\n tCrB_cp[None, None, kb],\n )\n cute.copy(\n tiled_copy_SFB,\n cute.filter_zeros(tCsSFB_cp),\n cute.filter_zeros(tCrSFB_cp),\n )\n\n acc.fill(0.0)\n for mt in cutlass.range_constexpr(self.num_m_tiles):\n for nt in cutlass.range_constexpr(self.num_n_tiles):\n for kb in cutlass.range_constexpr(self.num_k_blocks):\n mma_atom.set(WarpField.SFA, tCrSFA[None, mt, kb].iterator)\n mma_atom.set(WarpField.SFB, tCrSFB[None, nt, kb].iterator)\n cute.gemm(\n mma_atom,\n acc[None, mt, nt],\n tCrA[None, mt, kb],\n tCrB[None, nt, kb],\n acc[None, mt, nt],\n )\n\n # Warp block-max epilogue, as in the general kernel; a packed row\n # maps to (local_head, token).\n acc_mn = self._make_acc_tensor_mn_view(acc)\n tScS_mn = self._make_acc_tensor_mn_view(tCcC)\n n_rows = cute.size(acc_mn.shape[0])\n thr_vmnk = tiled_mma.thr_layout_vmnk.get_flat_coord(tidx)\n nwarp = thr_vmnk[2]\n self.cta_sync_barrier.arrive_and_wait()\n for r in cutlass.range_constexpr(n_rows):\n row = tScS_mn[r, 0][0]\n token = row % self._PACK_Q_LEN\n if cutlass.const_expr(self._is_causal):\n col_limit = cutlass.min(token + q_off + 1, seqlen_k)\n else:\n col_limit = seqlen_k\n for c in cutlass.range_constexpr(cute.size(acc_mn.shape[1])):\n k_pos = kv_block * self._N + tScS_mn[0, c][1]\n if cute.elem_less(col_limit, k_pos + 1):\n acc_mn[r, c] = -cutlass.Float32.inf\n tile_max = (\n acc_mn[r, None]\n .load()\n .reduce(cute.ReductionOp.MAX, -cutlass.Float32.inf, 0)\n )\n tile_max = self._threadquad_reduce_max(tile_max)\n sRed[row, nwarp] = tile_max\n self.cta_sync_barrier.arrive_and_wait()\n if nwarp == 0:\n for r in cutlass.range_constexpr(n_rows):\n row = tScS_mn[r, 0][0]\n local_head = row // self._PACK_Q_LEN\n token = row % self._PACK_Q_LEN\n head = kv_head * self._QHEAD_PER_KV + local_head\n both = cute.arch.fmax(sRed[row, 0], sRed[row, 1])\n if cute.elem_less(token, seqlen_q):\n mMaxScore[head, kv_block, q_start + token] = (\n both * global_scale\n )\n elif kv_block < max_k_tiles:\n if tidx < self._M:\n local_head2 = tidx // self._PACK_Q_LEN\n token2 = tidx % self._PACK_Q_LEN\n head2 = kv_head * self._QHEAD_PER_KV + local_head2\n if cute.elem_less(token2, seqlen_q):\n mMaxScore[\n head2, kv_block, q_start + token2\n ] = -cutlass.Float32.inf\n\n @cute.jit\n def _load_packed_q(self, mQ_u32, sX_u32, q_start, kv_head, seqlen_q, tidx):\n \"\"\"Gather the packed-fp4 Q tile into the 128-row tile; rows past seqlen_q are\n zero-filled (epilogue masks them).\"\"\"\n total = self._M * self._chunks_u32\n for it in cutlass.range_constexpr(total // self._num_threads):\n e = tidx + it * self._num_threads\n r = e // self._chunks_u32\n c = e % self._chunks_u32\n local_head = r // self._PACK_Q_LEN\n token = r % self._PACK_Q_LEN\n head = kv_head * self._QHEAD_PER_KV + local_head\n if cute.elem_less(token, seqlen_q):\n sX_u32[r, c] = mQ_u32[q_start + token, head, c]\n else:\n sX_u32[r, c] = Uint32(0)\n\n @cute.jit\n def _load_packed_q_sf(\n self, mQsf, sXsf_u8, q_start, kv_head, num_qo_heads, seqlen_q, tidx\n ):\n \"\"\"Fill the SF smem for the packed Q tile; SF logical row = (q_start + token)\n * num_qo_heads + head, the row order nvfp4_quantize produces.\"\"\"\n total = self._M * self._sf_per_row\n for it in cutlass.range_constexpr(total // self._num_threads):\n e = tidx + it * self._num_threads\n r = e // self._sf_per_row\n g = e % self._sf_per_row\n dst = self._sf_offset(r, g)\n local_head = r // self._PACK_Q_LEN\n token = r % self._PACK_Q_LEN\n head = kv_head * self._QHEAD_PER_KV + local_head\n if cute.elem_less(token, seqlen_q):\n sXsf_u8[dst] = mQsf[\n self._sf_offset((q_start + token) * num_qo_heads + head, g)\n ]\n else:\n sXsf_u8[dst] = Uint8(0)\n"},"diff":{"kind":"string","value":"--- flashinfer/msa_ops/cute_dsl/proxy_score_fp4_sm12x.py\n+++ flashinfer/msa_ops/cute_dsl/proxy_score_fp4_sm12x.py\n@@ -651,6 +651,7 @@\n paged: bool = False,\n qhead_per_kv: int = _QHEAD_PER_KV,\n pack_q_len: int = _PACK_Q_LEN,\n+ qoff_default: bool = False,\n ):\n super().__init__(head_dim=head_dim, is_causal=is_causal, paged=paged)\n if qhead_per_kv * pack_q_len != self._M:\n@@ -662,6 +663,8 @@\n # gather/epilogue, so each factorization compiles to its own kernel.\n self._QHEAD_PER_KV = qhead_per_kv\n self._PACK_Q_LEN = pack_q_len\n+ # True: right-aligned decode; the causal offset is computed in-kernel.\n+ self._qoff_default = qoff_default\n \n @cute.jit\n def __call__(\n@@ -742,6 +745,12 @@\n seqlen_k = mCuK[batch_idx + 1] - k_start\n num_kv_blocks = cute.ceil_div(seqlen_k, self._N)\n num_qo_heads = mQ.shape[1]\n+ q_off = cutlass.Int32(0)\n+ if cutlass.const_expr(self._is_causal):\n+ if cutlass.const_expr(self._qoff_default):\n+ q_off = seqlen_k - seqlen_q\n+ else:\n+ q_off = mQOffset[batch_idx]\n \n tiled_mma, mma_atom, sfa_layout, sfb_layout = self._build_mma()\n sA_layout = self._ab_layout(self._M)\n@@ -929,9 +938,7 @@\n row = tScS_mn[r, 0][0]\n token = row % self._PACK_Q_LEN\n if cutlass.const_expr(self._is_causal):\n- col_limit = cutlass.min(\n- token + mQOffset[batch_idx] + 1, seqlen_k\n- )\n+ col_limit = cutlass.min(token + q_off + 1, seqlen_k)\n else:\n col_limit = seqlen_k\n for c in cutlass.range_constexpr(cute.size(acc_mn.shape[1])):"},"lines_added":{"kind":"number","value":10,"string":"10"},"lines_removed":{"kind":"number","value":3,"string":"3"},"files_in_commit":{"kind":"number","value":7,"string":"7"},"models_mentioned":{"kind":"list like","value":["minimax"],"string":"[\n \"minimax\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["RTX5080","SM120","SM121"],"string":"[\n \"RTX5080\",\n \"SM120\",\n \"SM121\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":["2.2x","2.1x"],"string":"[\n \"2.2x\",\n \"2.1x\"\n]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cute_dsl kernel file from flashinfer (flashinfer/msa_ops/cute_dsl/proxy_score_fp4_sm12x.py).\n\nGoal: perf(msa): chunked top-k and in-kernel causal offsets for the SM12x indexer\nTarget hardware: RTX5080, SM120, SM121\nTarget models: minimax\n\nCurrent file:\n```python\n\"\"\"\nCopyright (c) 2026 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nNVFP4 tensor-core MSA proxy-score kernels for SM120/SM121: same contract as\n:mod:`proxy_score_sm12x`, with a general split-K and a packed-decode schedule.\n\nNo scalar stream schedule here (unlike the bf16 decode path): at 4-bit K the\nMMA pipeline hides the small tile's load latency, and the per-lane fp4 decode\nchain makes a scalar port slower, not faster.\n\"\"\"\n\nimport cuda.bindings.driver as cuda\nimport cutlass\nimport cutlass.cute as cute\nimport cutlass.pipeline as pipeline\nimport cutlass.utils.blackwell_helpers as sm120_utils\nfrom cutlass import Uint8, Uint32\nfrom cutlass.cute.nvgpu import warp\nfrom cutlass.cute.nvgpu.warp.mma import Field as WarpField\n\nfrom flashinfer.cute_dsl.utils import (\n sm120_make_smem_layout_sfa,\n sm120_make_smem_layout_sfb,\n)\n\n# NVFP4: 16-element scale groups (head_dim 128 -> 8 groups/row).\n_SF_VEC_SIZE = 16\n\n# Launch bound: cap registers so two CTAs stay resident per SM; one CTA cannot\n# hide the K-load latency and three would force spills. The split-K host\n# heuristic in proxy_score.py assumes this occupancy (target = 2 * num_sms).\n_MIN_BLOCKS_PER_MP = 2\n\n\nclass MsaProxyScoreFp4MmaSm12x:\n \"\"\"General NVFP4 tensor-core proxy schedule (any q length, flat or paged K);\n every query head scores independently.\"\"\"\n\n # The cuBLAS SF layout groups rows in blocks of 128, so a 128-row q-tile's\n # scale factors are a single contiguous block.\n _M = 128\n _N = 128 # kv-block: MSA scores per 128-token KV block\n _NUM_THREADS = 256 # 8 MMA warps for the (4,2,1) atom\n\n def __init__(\n self, head_dim: int = 128, is_causal: bool = True, paged: bool = False\n ):\n if head_dim != 128:\n raise ValueError(\"only head_dim == 128 is supported\")\n self._head_dim = head_dim\n self._is_causal = is_causal\n self._paged = paged\n self._num_threads = self._NUM_THREADS\n self.sf_vec_size = _SF_VEC_SIZE\n self.acc_dtype = cutlass.Float32\n self.a_dtype = cutlass.Float4E2M1FN\n self.sf_dtype = cutlass.Float8E4M3FN\n self.tile_shape_mnk = (self._M, self._N, head_dim)\n self._sf_per_row = head_dim // _SF_VEC_SIZE\n self._sf_tiles_n = (self._sf_per_row + 3) // 4\n self._chunks_u32 = head_dim // 8 # 16 Uint32 / packed-fp4 row\n # atom (4,2,1) over the m16n8k64 fp4 MMA -> group m64 n16 k64.\n self._atom_shape = (4, 2, 1)\n self.num_m_tiles = self._M // (16 * self._atom_shape[0])\n self.num_n_tiles = self._N // (8 * self._atom_shape[1])\n self.num_k_blocks = head_dim // 64\n self._min_blocks = _MIN_BLOCKS_PER_MP\n\n self.cta_sync_barrier = pipeline.NamedBarrier(\n barrier_id=1, num_threads=self._num_threads\n )\n\n @cute.jit\n def _build_mma(self):\n \"\"\"fp4 tiled MMA + bare atom + SF smem layouts. Built inside the jit\n context (``make_layout`` / ``get_permutation_mnk`` need an MLIR context).\"\"\"\n mma_op = cute.nvgpu.warp.MmaMXF4NVF4Op(\n self.a_dtype, self.acc_dtype, self.sf_dtype\n )\n permutation_mnk = sm120_utils.get_permutation_mnk(\n self.tile_shape_mnk, self.sf_vec_size, False\n )\n tiled_mma = cute.make_tiled_mma(\n mma_op,\n cute.make_layout(self._atom_shape),\n permutation_mnk=permutation_mnk,\n )\n mma_atom = cute.make_mma_atom(mma_op)\n sfa_layout = sm120_make_smem_layout_sfa(\n tiled_mma, self.tile_shape_mnk, self.sf_vec_size, 1\n )\n sfb_layout = sm120_make_smem_layout_sfb(\n tiled_mma, self.tile_shape_mnk, self.sf_vec_size, 1\n )\n return tiled_mma, mma_atom, sfa_layout, sfb_layout\n\n def _ab_layout(self, mode_n: int):\n return cute.make_layout((mode_n, self._head_dim), stride=(self._head_dim, 1))\n\n @cute.jit\n def __call__(\n self,\n mQ: cute.Tensor, # (total_q, Hq, head_dim//2) packed e2m1, uint8\n mK: cute.Tensor, # flat (total_k,Hkv,hd/2) | paged (pages,Hkv,128,hd/2) u8\n mQsf: cute.Tensor, # uint8 e4m3 scales, cuBLAS 128x4 tiled\n mKsf: cute.Tensor, # uint8 e4m3 scales, cuBLAS 128x4 tiled\n mPageTable: cute.Tensor, # (B, max_pages) int32 paged; dummy (1,1) flat\n mMaxScore: cute.Tensor, # (Hq, max_k_tiles, total_q) f32\n mCuQ: cute.Tensor, # (B + 1,) int32\n mCuK: cute.Tensor, # (B + 1,) int32\n mQOffset: cute.Tensor, # (B,) int32 causal offset\n q_global_scale: cutlass.Float32,\n k_global_scale: cutlass.Float32,\n max_seqlen_q: cutlass.Int32,\n batch_size: cutlass.Int32,\n num_qo_heads: cutlass.Int32,\n max_k_tiles: cutlass.Int32,\n num_splits: cutlass.Int32,\n stream: cuda.CUstream,\n ):\n # Split-K grid, as in proxy_score_sm12x.\n self.kernel(\n mQ,\n mK,\n mQsf,\n mKsf,\n mPageTable,\n mMaxScore,\n mCuQ,\n mCuK,\n mQOffset,\n q_global_scale * k_global_scale,\n max_k_tiles,\n num_splits,\n ).launch(\n grid=(\n cute.ceil_div(max_seqlen_q, self._M) * num_splits,\n batch_size,\n num_qo_heads,\n ),\n block=[self._num_threads, 1, 1],\n stream=stream,\n min_blocks_per_mp=self._min_blocks,\n )\n\n @cute.kernel\n def kernel(\n self,\n mQ: cute.Tensor,\n mK: cute.Tensor,\n mQsf: cute.Tensor,\n mKsf: cute.Tensor,\n mPageTable: cute.Tensor,\n mMaxScore: cute.Tensor,\n mCuQ: cute.Tensor,\n mCuK: cute.Tensor,\n mQOffset: cute.Tensor,\n global_scale: cutlass.Float32, # q_global * k_global, applied at store\n max_k_tiles: cutlass.Int32,\n num_splits: cutlass.Int32,\n ):\n tidx, _, _ = cute.arch.thread_idx()\n bx, batch_idx, qo_head = cute.arch.block_idx()\n # grid x packs (m_block, split), as in the bf16 kernel.\n m_block = bx // num_splits\n split_idx = bx % num_splits\n\n q_start = mCuQ[batch_idx]\n seqlen_q = mCuQ[batch_idx + 1] - q_start\n if cutlass.const_expr(self._paged):\n # mCuK holds per-request lengths on the paged path:\n # page_table supplies every KV address, so there is\n # no base offset to add.\n k_start = cutlass.Int32(0)\n seqlen_k = mCuK[batch_idx]\n else:\n k_start = mCuK[batch_idx]\n seqlen_k = mCuK[batch_idx + 1] - k_start\n num_kv_blocks = cute.ceil_div(seqlen_k, self._N)\n group_size = mQ.shape[1] // mK.shape[1]\n kv_head = qo_head // group_size\n\n if m_block * self._M < seqlen_q:\n tiled_mma, mma_atom, sfa_layout, sfb_layout = self._build_mma()\n sA_layout = self._ab_layout(self._M)\n sB_layout = self._ab_layout(self._N)\n\n @cute.struct\n class SharedStorage:\n sA: cute.struct.Align[\n cute.struct.MemRange[self.a_dtype, cute.cosize(sA_layout)], 1024\n ]\n sB: cute.struct.Align[\n cute.struct.MemRange[self.a_dtype, cute.cosize(sB_layout)], 1024\n ]\n sSFA: cute.struct.Align[\n cute.struct.MemRange[self.sf_dtype, cute.cosize(sfa_layout)], 1024\n ]\n sSFB: cute.struct.Align[\n cute.struct.MemRange[self.sf_dtype, cute.cosize(sfb_layout)], 1024\n ]\n # Warp-epilogue cross-warp scratch: one f32 per (q-row, N-warp).\n # 1KB vs a full 64KB [M,N] scatter, so smem stops capping occupancy.\n sRed: cute.struct.Align[\n cute.struct.MemRange[cutlass.Float32, self._M * 2], 1024\n ]\n\n smem = cutlass.utils.SmemAllocator()\n storage = smem.allocate(SharedStorage)\n sA = storage.sA.get_tensor(sA_layout)\n sB = storage.sB.get_tensor(sB_layout)\n # sm120 SF layouts append a (size-1) stage mode; drop it for the MMA\n # partition. The compound layout's byte offsets for one 128-row/K=128 tile\n # equal the cuBLAS 128x4 layout (== _sf_offset), so the fill is a flat view.\n sSFA = storage.sSFA.get_tensor(sfa_layout)[None, None, 0]\n sSFB = storage.sSFB.get_tensor(sfb_layout)[None, None, 0]\n sfa_n = cute.cosize(sfa_layout)\n sfb_n = cute.cosize(sfb_layout)\n sSFA_u8 = cute.recast_tensor(\n storage.sSFA.get_tensor(cute.make_layout(sfa_n, stride=1)), Uint8\n )\n sSFB_u8 = cute.recast_tensor(\n storage.sSFB.get_tensor(cute.make_layout(sfb_n, stride=1)), Uint8\n )\n sRed = storage.sRed.get_tensor(\n cute.make_layout((self._M, 2), stride=(2, 1))\n )\n\n mQ_u32 = cute.recast_tensor(mQ, Uint32)\n mK_u32 = cute.recast_tensor(mK, Uint32)\n sA_u32 = cute.recast_tensor(sA, Uint32)\n sB_u32 = cute.recast_tensor(sB, Uint32)\n\n # Q is always flat (current query tokens, never paged): read absolute\n # row q_tile0+m, mask on the in-tile position m_block*M+m.\n q_tile0 = q_start + m_block * self._M\n q_pos0 = m_block * self._M\n self._load_packed(\n mQ_u32[None, qo_head, None], sA_u32, q_tile0, q_pos0, seqlen_q, tidx\n )\n self._load_sf(\n mQsf,\n sSFA_u8,\n q_pos0,\n seqlen_q,\n q_tile0 * mQ.shape[1] + qo_head,\n mQ.shape[1],\n tidx,\n )\n self.cta_sync_barrier.arrive_and_wait()\n\n thr_mma = tiled_mma.get_slice(tidx)\n tCsA = thr_mma.partition_A(sA)\n tCsB = thr_mma.partition_B(sB)\n tCrA = tiled_mma.make_fragment_A(tCsA)\n tCrB = tiled_mma.make_fragment_B(tCsB)\n tCrSFA = self._partition_fragment_SFA(sSFA, thr_mma, tidx)\n tCrSFB = self._partition_fragment_SFB(sSFB, thr_mma, tidx)\n cS = cute.make_identity_tensor((self._M, self._N))\n tCcC = thr_mma.partition_C(cS)\n acc = cute.make_rmem_tensor(tCcC.shape[:3], self.acc_dtype)\n\n ldm_A = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(transpose=False, num_matrices=4), self.a_dtype\n )\n ldm_B = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(transpose=False, num_matrices=4), self.a_dtype\n )\n tiled_copy_A = cute.make_tiled_copy_A(ldm_A, tiled_mma)\n tiled_copy_B = cute.make_tiled_copy_B(ldm_B, tiled_mma)\n cp_sf = cute.make_copy_atom(cute.nvgpu.CopyUniversalOp(), self.sf_dtype)\n tiled_copy_SFA = cute.make_tiled_copy(\n cp_sf,\n self._get_layoutSFA_TV(tiled_mma),\n (\n cute.size(tiled_mma.permutation_mnk[0]),\n cute.size(tiled_mma.permutation_mnk[2]),\n ),\n )\n tiled_copy_SFB = cute.make_tiled_copy(\n cp_sf,\n self._get_layoutSFB_TV(tiled_mma),\n (\n cute.size(tiled_mma.permutation_mnk[1]),\n cute.size(tiled_mma.permutation_mnk[2]),\n ),\n )\n thr_A = tiled_copy_A.get_slice(tidx)\n thr_B = tiled_copy_B.get_slice(tidx)\n thr_SFA = tiled_copy_SFA.get_slice(tidx)\n thr_SFB = tiled_copy_SFB.get_slice(tidx)\n tCsA_cp = thr_A.partition_S(sA)\n tCrA_cp = thr_A.retile(tCrA)\n tCsB_cp = thr_B.partition_S(sB)\n tCrB_cp = thr_B.retile(tCrB)\n tCsSFA_cp = thr_SFA.partition_S(sSFA)\n tCrSFA_cp = thr_SFA.retile(tCrSFA)\n tCsSFB_cp = thr_SFB.partition_S(sSFB)\n tCrSFB_cp = thr_SFB.retile(tCrSFB)\n\n # Q fragments load once (sA / sSFA reused across all kv-blocks)\n for kb in cutlass.range_constexpr(self.num_k_blocks):\n cute.copy(\n tiled_copy_A, tCsA_cp[None, None, kb], tCrA_cp[None, None, kb]\n )\n cute.copy(\n tiled_copy_SFA,\n cute.filter_zeros(tCsSFA_cp),\n cute.filter_zeros(tCrSFA_cp),\n )\n\n # Split-K stride + causal skip, as in the bf16 kernel.\n if cutlass.const_expr(self._is_causal):\n causal_last = (\n m_block * self._M + (self._M - 1) + mQOffset[batch_idx]\n ) // self._N\n last_block = cutlass.min(causal_last, num_kv_blocks - 1)\n else:\n last_block = num_kv_blocks - 1\n\n n_iter = cute.ceil_div(max_k_tiles, num_splits)\n for it in cutlass.range(n_iter):\n kv_block = split_idx + it * num_splits\n if kv_block <= last_block:\n self.cta_sync_barrier.arrive_and_wait()\n k_pos0 = kv_block * self._N\n if cutlass.const_expr(self._paged):\n # paged: kv_block maps to a 128-row page via the page table.\n # Read it page-local (read_base 0) and mask on the global\n # position; SF row = (page*Hkv + kv_head)*N + token, stride 1.\n page = mPageTable[batch_idx, kv_block]\n gK_pg = cute.recast_tensor(\n mK[page, kv_head, None, None], Uint32\n )\n self._load_packed(gK_pg, sB_u32, 0, k_pos0, seqlen_k, tidx)\n self._load_sf(\n mKsf,\n sSFB_u8,\n k_pos0,\n seqlen_k,\n (page * mK.shape[1] + kv_head) * self._N,\n 1,\n tidx,\n )\n else:\n # flat: read absolute row k_tile0+m, SF row = token*Hkv+kv_head.\n k_tile0 = k_start + kv_block * self._N\n self._load_packed(\n mK_u32[None, kv_head, None],\n sB_u32,\n k_tile0,\n k_pos0,\n seqlen_k,\n tidx,\n )\n self._load_sf(\n mKsf,\n sSFB_u8,\n k_pos0,\n seqlen_k,\n k_tile0 * mK.shape[1] + kv_head,\n mK.shape[1],\n tidx,\n )\n self.cta_sync_barrier.arrive_and_wait()\n\n for kb in cutlass.range_constexpr(self.num_k_blocks):\n cute.copy(\n tiled_copy_B,\n tCsB_cp[None, None, kb],\n tCrB_cp[None, None, kb],\n )\n cute.copy(\n tiled_copy_SFB,\n cute.filter_zeros(tCsSFB_cp),\n cute.filter_zeros(tCrSFB_cp),\n )\n\n acc.fill(0.0)\n for mt in cutlass.range_constexpr(self.num_m_tiles):\n for nt in cutlass.range_constexpr(self.num_n_tiles):\n for kb in cutlass.range_constexpr(self.num_k_blocks):\n mma_atom.set(\n WarpField.SFA, tCrSFA[None, mt, kb].iterator\n )\n mma_atom.set(\n WarpField.SFB, tCrSFB[None, nt, kb].iterator\n )\n cute.gemm(\n mma_atom,\n acc[None, mt, nt],\n tCrA[None, mt, kb],\n tCrB[None, nt, kb],\n acc[None, mt, nt],\n )\n\n # Warp-level block-max epilogue (no scatter buffer): each thread\n # reduces its N columns, a thread-quad shuffle yields the per-q-row\n # warp max, and the two N-warps combine through sRed.\n acc_mn = self._make_acc_tensor_mn_view(acc)\n tScS_mn = self._make_acc_tensor_mn_view(tCcC)\n n_rows = cute.size(acc_mn.shape[0])\n thr_vmnk = tiled_mma.thr_layout_vmnk.get_flat_coord(tidx)\n nwarp = thr_vmnk[2]\n self.cta_sync_barrier.arrive_and_wait()\n for r in cutlass.range_constexpr(n_rows):\n row = tScS_mn[r, 0][0]\n q_loc = m_block * self._M + row\n if cutlass.const_expr(self._is_causal):\n col_limit = cutlass.min(\n q_loc + mQOffset[batch_idx] + 1, seqlen_k\n )\n else:\n col_limit = seqlen_k\n for c in cutlass.range_constexpr(cute.size(acc_mn.shape[1])):\n k_pos = kv_block * self._N + tScS_mn[0, c][1]\n if cute.elem_less(col_limit, k_pos + 1):\n acc_mn[r, c] = -cutlass.Float32.inf\n tile_max = (\n acc_mn[r, None]\n .load()\n .reduce(cute.ReductionOp.MAX, -cutlass.Float32.inf, 0)\n )\n tile_max = self._threadquad_reduce_max(tile_max)\n sRed[row, nwarp] = tile_max\n self.cta_sync_barrier.arrive_and_wait()\n # Combine the two N-warps; one writer per q-row (the nwarp-0\n # warp owns the write).\n if nwarp == 0:\n for r in cutlass.range_constexpr(n_rows):\n row = tScS_mn[r, 0][0]\n q_loc = m_block * self._M + row\n both = cute.arch.fmax(sRed[row, 0], sRed[row, 1])\n if q_loc < seqlen_q:\n mMaxScore[qo_head, kv_block, q_start + q_loc] = (\n both * global_scale\n )\n elif kv_block < max_k_tiles:\n if tidx < self._M:\n q_loc2 = m_block * self._M + tidx\n if q_loc2 < seqlen_q:\n mMaxScore[\n qo_head, kv_block, q_start + q_loc2\n ] = -cutlass.Float32.inf\n\n @cute.jit\n def _sf_offset(self, srow, scol):\n \"\"\"cuBLAS 128x4 tiled SF byte offset; for one 128-row K=128 tile it equals\n the SM120 SF smem layout, so sSFA/sSFB fill by this offset directly.\"\"\"\n srow_in = srow % 128\n return (\n ((srow // 128) * self._sf_tiles_n + scol // 4) * 512\n + (srow_in % 32) * 16\n + (srow_in // 32) * 4\n + scol % 4\n )\n\n @cute.jit\n def _load_packed(self, gX_u32, sX_u32, read_base, pos_base, seqlen, tidx):\n \"\"\"read_base is decoupled from pos_base so the paged path reads a page-local\n tile (read_base 0) but masks on the global token position pos_base + m.\"\"\"\n rows = cute.size(sX_u32.shape[0])\n total = rows * self._chunks_u32\n for it in cutlass.range_constexpr(total // self._num_threads):\n e = tidx + it * self._num_threads\n m = e // self._chunks_u32\n c = e % self._chunks_u32\n if cute.elem_less(pos_base + m, seqlen):\n sX_u32[m, c] = gX_u32[read_base + m, c]\n else:\n sX_u32[m, c] = Uint32(0)\n\n @cute.jit\n def _load_sf(self, mXsf, sXsf_u8, pos_base, seqlen, sf_row_base, sf_stride, tidx):\n \"\"\"Fill the SF smem from the e4m3 buffer: flat passes row base token*heads+head\n with stride num_heads; paged passes (page*Hkv + kv_head)*N with stride 1.\"\"\"\n total = self._M * self._sf_per_row\n for it in cutlass.range_constexpr(total // self._num_threads):\n e = tidx + it * self._num_threads\n m = e // self._sf_per_row\n g = e % self._sf_per_row\n dst = self._sf_offset(m, g)\n if cute.elem_less(pos_base + m, seqlen):\n sXsf_u8[dst] = mXsf[self._sf_offset(sf_row_base + m * sf_stride, g)]\n else:\n sXsf_u8[dst] = Uint8(0)\n\n def _partition_fragment_SFA(self, sfa_tensor, thr_mma, tidx):\n thrfrg = self._thrfrg_SFA(sfa_tensor.layout, thr_mma)\n thr_tensor = cute.make_tensor(sfa_tensor.iterator, thrfrg)\n thr_vmnk = thr_mma.thr_layout_vmnk.get_flat_coord(tidx)\n thr_vmk = (thr_vmnk[0], (thr_vmnk[1], thr_vmnk[3]))\n part = thr_tensor[thr_vmk, (None, None)]\n part = cute.group_modes(cute.flatten(part), 0, 2)\n return cute.make_fragment_like(part)\n\n def _partition_fragment_SFB(self, sfb_tensor, thr_mma, tidx):\n thrfrg = self._thrfrg_SFB(sfb_tensor.layout, thr_mma)\n thr_tensor = cute.make_tensor(sfb_tensor.iterator, thrfrg)\n thr_vmnk = thr_mma.thr_layout_vmnk.get_flat_coord(tidx)\n thr_vnk = (thr_vmnk[0], (thr_vmnk[2], thr_vmnk[3]))\n part = thr_tensor[thr_vnk, (None, None)]\n part = cute.group_modes(cute.flatten(part), 0, 2)\n part = cute.group_modes(part, 1, 3)\n return cute.make_fragment_like(part)\n\n def _thrfrg_SFA(self, sfa_tensor, tiled_mma):\n atom_shape_mnk = tiled_mma.shape_mnk\n atom_sfa_layout = cute.make_layout(\n shape=((2, 2, 8), 64), stride=((8, 0, 1), 16)\n )\n permutation_mnk = tiled_mma.permutation_mnk\n thr_layout_vmnk = tiled_mma.thr_layout_vmnk\n t_tile = (permutation_mnk[0], permutation_mnk[2])\n t_tensor = cute.logical_divide(sfa_tensor, t_tile)\n a_tile = (\n cute.make_layout((atom_shape_mnk[0])),\n cute.make_layout((atom_shape_mnk[2])),\n )\n a_tensor = cute.zipped_divide(t_tensor, a_tile)\n tv_tensor = cute.composition(a_tensor, (atom_sfa_layout, None))\n thr_tile = (\n None,\n (\n cute.make_layout(cute.size(thr_layout_vmnk[1])),\n cute.make_layout(cute.size(thr_layout_vmnk[3])),\n ),\n )\n return cute.zipped_divide(tv_tensor, thr_tile)\n\n def _thrfrg_SFB(self, sfb_tensor, tiled_mma):\n atom_shape_mnk = tiled_mma.shape_mnk\n atom_sfb_layout = cute.make_layout(shape=((4, 8), 64), stride=((0, 1), 8))\n permutation_mnk = tiled_mma.permutation_mnk\n thr_layout_vmnk = tiled_mma.thr_layout_vmnk\n t_tile = (permutation_mnk[1], permutation_mnk[2])\n t_tensor = cute.logical_divide(sfb_tensor, t_tile)\n a_tile = (\n cute.make_layout((atom_shape_mnk[1])),\n cute.make_layout((atom_shape_mnk[2])),\n )\n a_tensor = cute.zipped_divide(t_tensor, a_tile)\n tv_tensor = cute.composition(a_tensor, (atom_sfb_layout, None))\n thr_tile = (\n None,\n (\n cute.make_layout(cute.size(thr_layout_vmnk[2])),\n cute.make_layout(cute.size(thr_layout_vmnk[3])),\n ),\n )\n return cute.zipped_divide(tv_tensor, thr_tile)\n\n def _get_layoutSFA_TV(self, tiled_mma):\n perm_m = tiled_mma.permutation_mnk[0]\n perm_k = tiled_mma.permutation_mnk[2]\n ref_A = cute.make_layout((cute.size(perm_m), cute.size(perm_k)))\n thr_layout_vmnk = tiled_mma.thr_layout_vmnk\n atile = (\n None,\n (\n cute.make_layout(\n shape=(\n cute.size(thr_layout_vmnk[1]),\n cute.size(thr_layout_vmnk[2]),\n ),\n stride=(1, 0),\n ),\n None,\n ),\n )\n thridx_2_thrid = cute.right_inverse(thr_layout_vmnk)\n thrfrg_sfa = self._thrfrg_SFA(ref_A, tiled_mma)\n layout_tv = cute.composition(thrfrg_sfa, (atile, None))\n return cute.composition(layout_tv, (thridx_2_thrid, None))\n\n def _get_layoutSFB_TV(self, tiled_mma):\n perm_n = tiled_mma.permutation_mnk[1]\n perm_k = tiled_mma.permutation_mnk[2]\n ref_B = cute.make_layout((cute.size(perm_n), cute.size(perm_k)))\n thr_layout_vmnk = tiled_mma.thr_layout_vmnk\n atile = (\n None,\n (\n cute.make_layout(\n shape=(\n cute.size(thr_layout_vmnk[1]),\n cute.size(thr_layout_vmnk[2]),\n ),\n stride=(0, 1),\n ),\n None,\n ),\n )\n thridx_2_thrid = cute.right_inverse(thr_layout_vmnk)\n thrfrg_sfb = self._thrfrg_SFB(ref_B, tiled_mma)\n layout_tv = cute.composition(thrfrg_sfb, (atile, None))\n return cute.composition(layout_tv, (thridx_2_thrid, None))\n\n @cute.jit\n def _threadquad_reduce_max(self, val):\n # Max across the 4 lanes of an m16n8 row-quad (the N lanes within a warp)\n val = cute.arch.fmax(\n val,\n cute.arch.shuffle_sync_bfly(val, offset=2, mask=-1, mask_and_clamp=31),\n )\n val = cute.arch.fmax(\n val,\n cute.arch.shuffle_sync_bfly(val, offset=1, mask=-1, mask_and_clamp=31),\n )\n return val\n\n def _make_acc_tensor_mn_view(self, acc: cute.Tensor) -> cute.Tensor:\n acc_layout_col_major = cute.make_layout(acc.layout.shape)\n acc_layout_mn = cute.make_layout(\n (\n (acc_layout_col_major.shape[0][1], acc_layout_col_major.shape[1]),\n (acc_layout_col_major.shape[0][0], acc_layout_col_major.shape[2]),\n ),\n stride=(\n (acc_layout_col_major.stride[0][1], acc_layout_col_major.stride[1]),\n (acc_layout_col_major.stride[0][0], acc_layout_col_major.stride[2]),\n ),\n )\n acc_layout_mn = cute.composition(acc.layout, acc_layout_mn)\n return cute.make_tensor(acc.iterator, acc_layout_mn)\n\n\nclass MsaProxyScoreFp4MmaDecodePackedSm12x(MsaProxyScoreFp4MmaSm12x):\n \"\"\"Head-fused packed-decode fp4 schedule: packs qhead_per_kv heads x pack_q_len\n tokens into the 128 MMA rows so the shared index-K is read once per kv_head.\"\"\"\n\n _PACK_Q_LEN = 8\n _QHEAD_PER_KV = 16\n\n def __init__(\n self,\n head_dim: int = 128,\n is_causal: bool = True,\n paged: bool = False,\n qhead_per_kv: int = _QHEAD_PER_KV,\n pack_q_len: int = _PACK_Q_LEN,\n ):\n super().__init__(head_dim=head_dim, is_causal=is_causal, paged=paged)\n if qhead_per_kv * pack_q_len != self._M:\n raise ValueError(\n f\"qhead_per_kv * pack_q_len must equal the {self._M}-row MMA tile, \"\n f\"got {qhead_per_kv} x {pack_q_len}\"\n )\n # Instance attrs shadow the class defaults; they are constexpr-baked into the\n # gather/epilogue, so each factorization compiles to its own kernel.\n self._QHEAD_PER_KV = qhead_per_kv\n self._PACK_Q_LEN = pack_q_len\n\n @cute.jit\n def __call__(\n self,\n mQ: cute.Tensor,\n mK: cute.Tensor,\n mQsf: cute.Tensor,\n mKsf: cute.Tensor,\n mPageTable: cute.Tensor,\n mMaxScore: cute.Tensor,\n mCuQ: cute.Tensor,\n mCuK: cute.Tensor,\n mQOffset: cute.Tensor,\n q_global_scale: cutlass.Float32,\n k_global_scale: cutlass.Float32,\n max_seqlen_q: cutlass.Int32,\n batch_size: cutlass.Int32,\n num_qo_heads: cutlass.Int32,\n max_k_tiles: cutlass.Int32,\n num_splits: cutlass.Int32,\n stream: cuda.CUstream,\n ):\n # One CTA per (split, batch, kv_head), as in the bf16 packed kernel:\n # the shared index-K is read once per kv_head.\n self.kernel(\n mQ,\n mK,\n mQsf,\n mKsf,\n mPageTable,\n mMaxScore,\n mCuQ,\n mCuK,\n mQOffset,\n q_global_scale * k_global_scale,\n max_k_tiles,\n num_splits,\n ).launch(\n grid=(\n num_splits,\n batch_size,\n num_qo_heads // self._QHEAD_PER_KV,\n ),\n block=[self._num_threads, 1, 1],\n stream=stream,\n min_blocks_per_mp=self._min_blocks,\n )\n\n @cute.kernel\n def kernel(\n self,\n mQ: cute.Tensor,\n mK: cute.Tensor,\n mQsf: cute.Tensor,\n mKsf: cute.Tensor,\n mPageTable: cute.Tensor,\n mMaxScore: cute.Tensor,\n mCuQ: cute.Tensor,\n mCuK: cute.Tensor,\n mQOffset: cute.Tensor,\n global_scale: cutlass.Float32, # q_global * k_global, applied at store\n max_k_tiles: cutlass.Int32,\n num_splits: cutlass.Int32,\n ):\n tidx, _, _ = cute.arch.thread_idx()\n split_idx, batch_idx, kv_head = cute.arch.block_idx()\n\n q_start = mCuQ[batch_idx]\n seqlen_q = mCuQ[batch_idx + 1] - q_start\n if cutlass.const_expr(self._paged):\n # mCuK holds per-request lengths on the paged path:\n # page_table supplies every KV address, so there is\n # no base offset to add.\n k_start = cutlass.Int32(0)\n seqlen_k = mCuK[batch_idx]\n else:\n k_start = mCuK[batch_idx]\n seqlen_k = mCuK[batch_idx + 1] - k_start\n num_kv_blocks = cute.ceil_div(seqlen_k, self._N)\n num_qo_heads = mQ.shape[1]\n\n tiled_mma, mma_atom, sfa_layout, sfb_layout = self._build_mma()\n sA_layout = self._ab_layout(self._M)\n sB_layout = self._ab_layout(self._N)\n\n @cute.struct\n class SharedStorage:\n sA: cute.struct.Align[\n cute.struct.MemRange[self.a_dtype, cute.cosize(sA_layout)], 1024\n ]\n sB: cute.struct.Align[\n cute.struct.MemRange[self.a_dtype, cute.cosize(sB_layout)], 1024\n ]\n sSFA: cute.struct.Align[\n cute.struct.MemRange[self.sf_dtype, cute.cosize(sfa_layout)], 1024\n ]\n sSFB: cute.struct.Align[\n cute.struct.MemRange[self.sf_dtype, cute.cosize(sfb_layout)], 1024\n ]\n sRed: cute.struct.Align[\n cute.struct.MemRange[cutlass.Float32, self._M * 2], 1024\n ]\n\n smem = cutlass.utils.SmemAllocator()\n storage = smem.allocate(SharedStorage)\n sA = storage.sA.get_tensor(sA_layout)\n sB = storage.sB.get_tensor(sB_layout)\n sSFA = storage.sSFA.get_tensor(sfa_layout)[None, None, 0]\n sSFB = storage.sSFB.get_tensor(sfb_layout)[None, None, 0]\n sfa_n = cute.cosize(sfa_layout)\n sfb_n = cute.cosize(sfb_layout)\n sSFA_u8 = cute.recast_tensor(\n storage.sSFA.get_tensor(cute.make_layout(sfa_n, stride=1)), Uint8\n )\n sSFB_u8 = cute.recast_tensor(\n storage.sSFB.get_tensor(cute.make_layout(sfb_n, stride=1)), Uint8\n )\n sRed = storage.sRed.get_tensor(cute.make_layout((self._M, 2), stride=(2, 1)))\n\n mQ_u32 = cute.recast_tensor(mQ, Uint32)\n mK_u32 = cute.recast_tensor(mK, Uint32)\n sA_u32 = cute.recast_tensor(sA, Uint32)\n sB_u32 = cute.recast_tensor(sB, Uint32)\n\n self._load_packed_q(mQ_u32, sA_u32, q_start, kv_head, seqlen_q, tidx)\n self._load_packed_q_sf(\n mQsf, sSFA_u8, q_start, kv_head, num_qo_heads, seqlen_q, tidx\n )\n self.cta_sync_barrier.arrive_and_wait()\n\n thr_mma = tiled_mma.get_slice(tidx)\n tCsA = thr_mma.partition_A(sA)\n tCsB = thr_mma.partition_B(sB)\n tCrA = tiled_mma.make_fragment_A(tCsA)\n tCrB = tiled_mma.make_fragment_B(tCsB)\n tCrSFA = self._partition_fragment_SFA(sSFA, thr_mma, tidx)\n tCrSFB = self._partition_fragment_SFB(sSFB, thr_mma, tidx)\n cS = cute.make_identity_tensor((self._M, self._N))\n tCcC = thr_mma.partition_C(cS)\n acc = cute.make_rmem_tensor(tCcC.shape[:3], self.acc_dtype)\n\n ldm_A = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(transpose=False, num_matrices=4), self.a_dtype\n )\n ldm_B = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(transpose=False, num_matrices=4), self.a_dtype\n )\n tiled_copy_A = cute.make_tiled_copy_A(ldm_A, tiled_mma)\n tiled_copy_B = cute.make_tiled_copy_B(ldm_B, tiled_mma)\n cp_sf = cute.make_copy_atom(cute.nvgpu.CopyUniversalOp(), self.sf_dtype)\n tiled_copy_SFA = cute.make_tiled_copy(\n cp_sf,\n self._get_layoutSFA_TV(tiled_mma),\n (\n cute.size(tiled_mma.permutation_mnk[0]),\n cute.size(tiled_mma.permutation_mnk[2]),\n ),\n )\n tiled_copy_SFB = cute.make_tiled_copy(\n cp_sf,\n self._get_layoutSFB_TV(tiled_mma),\n (\n cute.size(tiled_mma.permutation_mnk[1]),\n cute.size(tiled_mma.permutation_mnk[2]),\n ),\n )\n thr_A = tiled_copy_A.get_slice(tidx)\n thr_B = tiled_copy_B.get_slice(tidx)\n thr_SFA = tiled_copy_SFA.get_slice(tidx)\n thr_SFB = tiled_copy_SFB.get_slice(tidx)\n tCsA_cp = thr_A.partition_S(sA)\n tCrA_cp = thr_A.retile(tCrA)\n tCsB_cp = thr_B.partition_S(sB)\n tCrB_cp = thr_B.retile(tCrB)\n tCsSFA_cp = thr_SFA.partition_S(sSFA)\n tCrSFA_cp = thr_SFA.retile(tCrSFA)\n tCsSFB_cp = thr_SFB.partition_S(sSFB)\n tCrSFB_cp = thr_SFB.retile(tCrSFB)\n\n for kb in cutlass.range_constexpr(self.num_k_blocks):\n cute.copy(tiled_copy_A, tCsA_cp[None, None, kb], tCrA_cp[None, None, kb])\n cute.copy(\n tiled_copy_SFA,\n cute.filter_zeros(tCsSFA_cp),\n cute.filter_zeros(tCrSFA_cp),\n )\n\n n_iter = cute.ceil_div(max_k_tiles, num_splits)\n for it in cutlass.range(n_iter):\n kv_block = split_idx + it * num_splits\n if kv_block < num_kv_blocks:\n self.cta_sync_barrier.arrive_and_wait()\n k_pos0 = kv_block * self._N\n if cutlass.const_expr(self._paged):\n # paged: same page-table indirection as the general kernel; the\n # packed schedule only changes the Q gather, not the K load.\n page = mPageTable[batch_idx, kv_block]\n gK_pg = cute.recast_tensor(mK[page, kv_head, None, None], Uint32)\n self._load_packed(gK_pg, sB_u32, 0, k_pos0, seqlen_k, tidx)\n self._load_sf(\n mKsf,\n sSFB_u8,\n k_pos0,\n seqlen_k,\n (page * mK.shape[1] + kv_head) * self._N,\n 1,\n tidx,\n )\n else:\n k_tile0 = k_start + kv_block * self._N\n self._load_packed(\n mK_u32[None, kv_head, None],\n sB_u32,\n k_tile0,\n k_pos0,\n seqlen_k,\n tidx,\n )\n self._load_sf(\n mKsf,\n sSFB_u8,\n k_pos0,\n seqlen_k,\n k_tile0 * mK.shape[1] + kv_head,\n mK.shape[1],\n tidx,\n )\n self.cta_sync_barrier.arrive_and_wait()\n\n for kb in cutlass.range_constexpr(self.num_k_blocks):\n cute.copy(\n tiled_copy_B,\n tCsB_cp[None, None, kb],\n tCrB_cp[None, None, kb],\n )\n cute.copy(\n tiled_copy_SFB,\n cute.filter_zeros(tCsSFB_cp),\n cute.filter_zeros(tCrSFB_cp),\n )\n\n acc.fill(0.0)\n for mt in cutlass.range_constexpr(self.num_m_tiles):\n for nt in cutlass.range_constexpr(self.num_n_tiles):\n for kb in cutlass.range_constexpr(self.num_k_blocks):\n mma_atom.set(WarpField.SFA, tCrSFA[None, mt, kb].iterator)\n mma_atom.set(WarpField.SFB, tCrSFB[None, nt, kb].iterator)\n cute.gemm(\n mma_atom,\n acc[None, mt, nt],\n tCrA[None, mt, kb],\n tCrB[None, nt, kb],\n acc[None, mt, nt],\n )\n\n # Warp block-max epilogue, as in the general kernel; a packed row\n # maps to (local_head, token).\n acc_mn = self._make_acc_tensor_mn_view(acc)\n tScS_mn = self._make_acc_tensor_mn_view(tCcC)\n n_rows = cute.size(acc_mn.shape[0])\n thr_vmnk = tiled_mma.thr_layout_vmnk.get_flat_coord(tidx)\n nwarp = thr_vmnk[2]\n self.cta_sync_barrier.arrive_and_wait()\n for r in cutlass.range_constexpr(n_rows):\n row = tScS_mn[r, 0][0]\n token = row % self._PACK_Q_LEN\n if cutlass.const_expr(self._is_causal):\n col_limit = cutlass.min(\n token + mQOffset[batch_idx] + 1, seqlen_k\n )\n else:\n col_limit = seqlen_k\n for c in cutlass.range_constexpr(cute.size(acc_mn.shape[1])):\n k_pos = kv_block * self._N + tScS_mn[0, c][1]\n if cute.elem_less(col_limit, k_pos + 1):\n acc_mn[r, c] = -cutlass.Float32.inf\n tile_max = (\n acc_mn[r, None]\n .load()\n .reduce(cute.ReductionOp.MAX, -cutlass.Float32.inf, 0)\n )\n tile_max = self._threadquad_reduce_max(tile_max)\n sRed[row, nwarp] = tile_max\n self.cta_sync_barrier.arrive_and_wait()\n if nwarp == 0:\n for r in cutlass.range_constexpr(n_rows):\n row = tScS_mn[r, 0][0]\n local_head = row // self._PACK_Q_LEN\n token = row % self._PACK_Q_LEN\n head = kv_head * self._QHEAD_PER_KV + local_head\n both = cute.arch.fmax(sRed[row, 0], sRed[row, 1])\n if cute.elem_less(token, seqlen_q):\n mMaxScore[head, kv_block, q_start + token] = (\n both * global_scale\n )\n elif kv_block < max_k_tiles:\n if tidx < self._M:\n local_head2 = tidx // self._PACK_Q_LEN\n token2 = tidx % self._PACK_Q_LEN\n head2 = kv_head * self._QHEAD_PER_KV + local_head2\n if cute.elem_less(token2, seqlen_q):\n mMaxScore[\n head2, kv_block, q_start + token2\n ] = -cutlass.Float32.inf\n\n @cute.jit\n def _load_packed_q(self, mQ_u32, sX_u32, q_start, kv_head, seqlen_q, tidx):\n \"\"\"Gather the packed-fp4 Q tile into the 128-row tile; rows past seqlen_q are\n zero-filled (epilogue masks them).\"\"\"\n total = self._M * self._chunks_u32\n for it in cutlass.range_constexpr(total // self._num_threads):\n e = tidx + it * self._num_threads\n r = e // self._chunks_u32\n c = e % self._chunks_u32\n local_head = r // self._PACK_Q_LEN\n token = r % self._PACK_Q_LEN\n head = kv_head * self._QHEAD_PER_KV + local_head\n if cute.elem_less(token, seqlen_q):\n sX_u32[r, c] = mQ_u32[q_start + token, head, c]\n else:\n sX_u32[r, c] = Uint32(0)\n\n @cute.jit\n def _load_packed_q_sf(\n self, mQsf, sXsf_u8, q_start, kv_head, num_qo_heads, seqlen_q, tidx\n ):\n \"\"\"Fill the SF smem for the packed Q tile; SF logical row = (q_start + token)\n * num_qo_heads + head, the row order nvfp4_quantize produces.\"\"\"\n total = self._M * self._sf_per_row\n for it in cutlass.range_constexpr(total // self._num_threads):\n e = tidx + it * self._num_threads\n r = e // self._sf_per_row\n g = e % self._sf_per_row\n dst = self._sf_offset(r, g)\n local_head = r // self._PACK_Q_LEN\n token = r % self._PACK_Q_LEN\n head = kv_head * self._QHEAD_PER_KV + local_head\n if cute.elem_less(token, seqlen_q):\n sXsf_u8[dst] = mQsf[\n self._sf_offset((q_start + token) * num_qo_heads + head, g)\n ]\n else:\n sXsf_u8[dst] = Uint8(0)\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## 📌 Description\n\nFollow-up to #3655, which enabled MiniMax Sparse Attention (MSA) on SM120/SM121. The indexer (proxy score + top-k, the two ops that pick each query's KV blocks) stayed behind vLLM in a few regimes there. All of the gaps traced to `msa_topk_select` and its wrapper rather than to the proxy kernel:\n\n- At decode with small batches, the top-k launches one CTA per (query, head) row, which is 4 CTAs at batch 1, leaving the GPU nearly idle. At 32k context those rows also fall into the radix kernel, which costs about as much as the proxy itself.\n- At long-sequence prefill, the top-k reads scores with strided accesses, and the radix kernel re-reads them once per digit pass.\n- The packed decode wrappers built the causal-offset tensor with three small torch kernels per call, about as costly as the top-k itself at short sequence lengths.\n\nChanges:\n\n- A new chunked top-k. A partial kernel ranks 64-block chunks independently, one CTA per (query, head, chunk), and a merge kernel then re-ranks the surviving candidates for each row. Both use the same ordering as the existing top-k kernels, so selections are identical. The merge launches with PDL to overlap with the partial kernel.\n- A q-tiled variant of the partial kernel for large grids. It covers 32 queries per CTA so that every score load is one coalesced line, which extends the chunked path to prefill under a 128 MB scratch cap; larger grids keep the radix kernel.\n- The packed decode kernels (bf16 and NVFP4) now compute the causal offset in-kernel when `q_offset` is not given, removing the wrapper's torch launches from the decode path.\n\nThe kernel choice depends only on shapes, so it is CUDA-graph safe; a new test covers graph capture on the chunked path.\n\n### Performance\n\nMeasured as in #3655: median GPU time over CUDA-graph replays (CUPTI), with the L2 cache flushed between replays so one replay cannot reuse the previous replay's data. The baseline is vLLM's MiniMax-M3 Triton MSA kernels on the same GPUs and shapes. Each cell is an RTX PRO 6000 Server / RTX 5080 / GB10 triple, and speedup = vLLM time / FlashInfer time, so higher is better. \"Before\" is main as of #3655. The MTP columns run the same call with 4 draft tokens per request, as in a speculative-decoding verify step.\n\nIndexer decode (proxy + top-k), batch 1:\n\n| S | before | after | before (4-token MTP) | after (4-token MTP) |\n|--:|:--:|:--:|:--:|:--:|\n| 2k | 1.31 / 1.43 / 1.33 | 1.31 / 1.42 / 1.38 | 0.73 / 0.71 / 0.91 | 1.20 / 1.12 / 1.29 |\n| 4k | 1.40 / 1.39 / 1.21 | 1.43 / 1.38 / 1.24 | 0.87 / 0.86 / 1.03 | 1.39 / 1.29 / 1.33 |\n| 8k | 1.18 / 1.10 / 1.08 | 1.28 / 1.22 / 1.10 | 0.82 / 0.90 / 0.95 | 1.26 / 1.34 / 1.11 |\n| 16k | 1.18 / 1.09 / 1.02 | 1.25 / 1.17 / 1.09 | 0.95 / 0.85 / 0.97 | 1.34 / 1.19 / 1.09 |\n| 32k | 0.90 / 0.98 / 0.98 | 1.08 / 1.11 / 1.03 | 0.95 / 0.94 / 0.96 | 1.36 / 1.30 / 1.07 |\n\nIndexer prefill, batch 1 (the 2k and 4k rows keep the old kernels and are unchanged within noise):\n\n| S | before | after |\n|--:|:--:|:--:|\n| 8k | 1.04 / 1.14 / 1.01 | 1.06 / 1.18 / 1.02 |\n| 16k | 1.04 / 1.18 / 1.02 | 1.19 / 1.25 / 1.16 |\n| 32k | 0.90 / 1.08 / 0.89 | 1.16 / 1.28 / 1.19 |\n\nMeasured against the kernels this PR replaces:\n\n- The new top-k alone is 1.4-2.2x faster at decode (batch 1 to 128) and 1.2-2.1x faster at 8k-32k prefill.\n- The proxy kernel is untouched, so shapes where it dominates do not move: at batch 128 the end-to-end ratio stays at 1.00-1.03 vs vLLM.\n- The optional NVFP4 decode path also speeds up because its wrapper sheds the same torch launches.\n\n## 🔍 Related Issues\n\nFollow-up to #3655.\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\nAll 155 tests in `tests/msa_ops/` pass on an RTX 5080 (SM120) after rebasing onto current main. This PR adds tests for:\n\n- the dispatch boundaries between the three top-k kernels\n- selection identity between the chunked and existing kernels, including NaN scores, forced blocks, and the ragged q-tile tail\n- CUDA-graph capture on the chunked path\n- explicit `q_offset` on both packed decode kernels\n\nIt also moves the paged-varlen fp4 test's reference to float32: the kernel's fp4 x scale products never round through bf16, so the bf16-rounded reference misses the 5e-2 tolerance on causal-boundary blocks (16 of 40 seeds on an RTX 5080, including the checked-in seed). The same treatment the other fp4 tests already use.\n\n`compute-sanitizer` racecheck and memcheck are clean on the new kernels.\n\n## Reviewer Notes\n\n- Per-token `num_valid_pages` calls (added by #4324) stay on the single-kernel paths: the chunked kernels' geometry is host-derived from the scalar count.\n- Selection identity across the top-k kernels (same bit-key and tie order) is pinned by tests.\n- The row-per-CTA and q-tiled partial kernels keep separate bodies on purpose: the row-per-CTA binary is production-validated.\n- Deferred for the same reason: skipping the redundant sentinel prefill of the candidate scratch, and sharing the forced-slot fill across the three kernels.\n\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n- **New Features**\n - Added chunked top-k selection for large candidate sets, including tiled execution and forced-page handling.\n - Added optional default query-offset handling for packed decode with right-aligned causal masking.\n - Added tracing support for MSA top-k selection.\n\n- **Bug Fixes**\n - Improved causal masking consistency across packed decode formats.\n - Preserved sentinel results and selected-score correctness during top-k selection.\n\n- **Tests**\n - Expanded coverage for large contexts, query offsets, chunked selection, tracing, and CUDA graph execution.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000 Server\", \"model\": null, \"shape\": \"S=2k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.31, \"optimized\": 1.31, \"stated_speedup\": null, \"speedup\": 1.0}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"S=2k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.43, \"optimized\": 1.42, \"stated_speedup\": null, \"speedup\": 1.007}, {\"scope\": \"kernel\", \"hardware\": \"GB10\", \"model\": null, \"shape\": \"S=2k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.33, \"optimized\": 1.38, \"stated_speedup\": null, \"speedup\": 0.9638}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000 Server\", \"model\": null, \"shape\": \"S=2k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.73, \"optimized\": 1.2, \"stated_speedup\": null, \"speedup\": 0.6083}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"S=2k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.71, \"optimized\": 1.12, \"stated_speedup\": null, \"speedup\": 0.6339}, {\"scope\": \"kernel\", \"hardware\": \"GB10\", \"model\": null, \"shape\": \"S=2k\", \"batch_size\": 1, \"metric\": \"latency\", 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\"optimized\": 1.09, \"stated_speedup\": null, \"speedup\": 0.8899}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000 Server\", \"model\": null, \"shape\": \"S=32k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.9, \"optimized\": 1.08, \"stated_speedup\": null, \"speedup\": 0.8333}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"S=32k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.98, \"optimized\": 1.11, \"stated_speedup\": null, \"speedup\": 0.8829}, {\"scope\": \"kernel\", \"hardware\": \"GB10\", \"model\": null, \"shape\": \"S=32k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.98, \"optimized\": 1.03, \"stated_speedup\": null, \"speedup\": 0.9515}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000 Server\", \"model\": null, \"shape\": \"S=32k\", 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{\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"S=8k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.14, \"optimized\": 1.18, \"stated_speedup\": null, \"speedup\": 0.9661}, {\"scope\": \"kernel\", \"hardware\": \"GB10\", \"model\": null, \"shape\": \"S=8k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.01, \"optimized\": 1.02, \"stated_speedup\": null, \"speedup\": 0.9902}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000 Server\", \"model\": null, \"shape\": \"S=16k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.04, \"optimized\": 1.19, \"stated_speedup\": null, \"speedup\": 0.8739}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"S=16k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, 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\"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.89, \"optimized\": 1.19, \"stated_speedup\": null, \"speedup\": 0.7479}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": null, \"shape\": null, \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.4, \"speedup\": 1.4}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": null, \"shape\": null, \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 2.2, \"speedup\": 2.2}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": null, \"shape\": null, \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.2, \"speedup\": 1.2}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": null, \"shape\": null, \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 2.1, \"speedup\": 2.1}]"},"kernel_speedup":{"kind":"number","value":0.8972,"string":"0.8972"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1073,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"8c5347726f30063fa1c17c4e81e75d509936d610"},"date":{"kind":"string","value":"2026-08-25T22:12:51-04:00"},"pr_number":{"kind":"number","value":4030,"string":"4,030"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/4030"},"title":{"kind":"string","value":"perf(msa): chunked top-k and in-kernel causal offsets for the SM12x indexer (#4030)"},"message":{"kind":"string","value":"perf(msa): chunked top-k and in-kernel causal offsets for the SM12x indexer (#4030)\n\n## 📌 Description\n\nFollow-up to #3655, which enabled MiniMax Sparse Attention (MSA) on\nSM120/SM121. The indexer (proxy score + top-k, the two ops that pick\neach query's KV blocks) stayed behind vLLM in a few regimes there. All\nof the gaps traced to `msa_topk_select` and its wrapper rather than to\nthe proxy kernel:\n\n- At decode with small batches, the top-k launches one CTA per (query,\nhead) row, which is 4 CTAs at batch 1, leaving the GPU nearly idle. At\n32k context those rows also fall into the radix kernel, which costs\nabout as much as the proxy itself.\n- At long-sequence prefill, the top-k reads scores with strided\naccesses, and the radix kernel re-reads them once per digit pass.\n- The packed decode wrappers built the causal-offset tensor with three\nsmall torch kernels per call, about as costly as the top-k itself at\nshort sequence lengths.\n\nChanges:\n\n- A new chunked top-k. A partial kernel ranks 64-block chunks\nindependently, one CTA per (query, head, chunk), and a merge kernel then\nre-ranks the surviving candidates for each row. Both use the same\nordering as the existing top-k kernels, so selections are identical. The\nmerge launches with PDL to overlap with the partial kernel.\n- A q-tiled variant of the partial kernel for large grids. It covers 32\nqueries per CTA so that every score load is one coalesced line, which\nextends the chunked path to prefill under a 128 MB scratch cap; larger\ngrids keep the radix kernel.\n- The packed decode kernels (bf16 and NVFP4) now compute the causal\noffset in-kernel when `q_offset` is not given, removing the wrapper's\ntorch launches from the decode path.\n\nThe kernel choice depends only on shapes, so it is CUDA-graph safe; a\nnew test covers graph capture on the chunked path.\n\n### Performance\n\nMeasured as in #3655: median GPU time over CUDA-graph replays (CUPTI),\nwith the L2 cache flushed between replays so one replay cannot reuse the\nprevious replay's data. The baseline is vLLM's MiniMax-M3 Triton MSA\nkernels on the same GPUs and shapes. Each cell is an RTX PRO 6000 Server\n/ RTX 5080 / GB10 triple, and speedup = vLLM time / FlashInfer time, so\nhigher is better. \"Before\" is main as of #3655. The MTP columns run the\nsame call with 4 draft tokens per request, as in a speculative-decoding\nverify step.\n\nIndexer decode (proxy + top-k), batch 1:\n\n| S | before | after | before (4-token MTP) | after (4-token MTP) |\n|--:|:--:|:--:|:--:|:--:|\n| 2k | 1.31 / 1.43 / 1.33 | 1.31 / 1.42 / 1.38 | 0.73 / 0.71 / 0.91 |\n1.20 / 1.12 / 1.29 |\n| 4k | 1.40 / 1.39 / 1.21 | 1.43 / 1.38 / 1.24 | 0.87 / 0.86 / 1.03 |\n1.39 / 1.29 / 1.33 |\n| 8k | 1.18 / 1.10 / 1.08 | 1.28 / 1.22 / 1.10 | 0.82 / 0.90 / 0.95 |\n1.26 / 1.34 / 1.11 |\n| 16k | 1.18 / 1.09 / 1.02 | 1.25 / 1.17 / 1.09 | 0.95 / 0.85 / 0.97 |\n1.34 / 1.19 / 1.09 |\n| 32k | 0.90 / 0.98 / 0.98 | 1.08 / 1.11 / 1.03 | 0.95 / 0.94 / 0.96 |\n1.36 / 1.30 / 1.07 |\n\nIndexer prefill, batch 1 (the 2k and 4k rows keep the old kernels and\nare unchanged within noise):\n\n| S | before | after |\n|--:|:--:|:--:|\n| 8k | 1.04 / 1.14 / 1.01 | 1.06 / 1.18 / 1.02 |\n| 16k | 1.04 / 1.18 / 1.02 | 1.19 / 1.25 / 1.16 |\n| 32k | 0.90 / 1.08 / 0.89 | 1.16 / 1.28 / 1.19 |\n\nMeasured against the kernels this PR replaces:\n\n- The new top-k alone is 1.4-2.2x faster at decode (batch 1 to 128) and\n1.2-2.1x faster at 8k-32k prefill.\n- The proxy kernel is untouched, so shapes where it dominates do not\nmove: at batch 128 the end-to-end ratio stays at 1.00-1.03 vs vLLM.\n- The optional NVFP4 decode path also speeds up because its wrapper\nsheds the same torch launches.\n\n## 🔍 Related Issues\n\nFollow-up to #3655.\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the\npre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\nAll 155 tests in `tests/msa_ops/` pass on an RTX 5080 (SM120) after\nrebasing onto current main. This PR adds tests for:\n\n- the dispatch boundaries between the three top-k kernels\n- selection identity between the chunked and existing kernels, including\nNaN scores, forced blocks, and the ragged q-tile tail\n- CUDA-graph capture on the chunked path\n- explicit `q_offset` on both packed decode kernels\n\nIt also moves the paged-varlen fp4 test's reference to float32: the\nkernel's fp4 x scale products never round through bf16, so the\nbf16-rounded reference misses the 5e-2 tolerance on causal-boundary\nblocks (16 of 40 seeds on an RTX 5080, including the checked-in seed).\nThe same treatment the other fp4 tests already use.\n\n`compute-sanitizer` racecheck and memcheck are clean on the new kernels.\n\n## Reviewer Notes\n\n- Per-token `num_valid_pages` calls (added by #4324) stay on the\nsingle-kernel paths: the chunked kernels' geometry is host-derived from\nthe scalar count.\n- Selection identity across the top-k kernels (same bit-key and tie\norder) is pinned by tests.\n- The row-per-CTA and q-tiled partial kernels keep separate bodies on\npurpose: the row-per-CTA binary is production-validated.\n- Deferred for the same reason: skipping the redundant sentinel prefill\nof the candidate scratch, and sharing the forced-slot fill across the\nthree kernels.\n\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n- **New Features**\n- Added chunked top-k selection for large candidate sets, including\ntiled execution and forced-page handling.\n- Added optional default query-offset handling for packed decode with\nright-aligned causal masking.\n - Added tracing support for MSA top-k selection.\n\n- **Bug Fixes**\n - Improved causal masking consistency across packed decode formats.\n- Preserved sentinel results and selected-score correctness during top-k\nselection.\n\n- **Tests**\n- Expanded coverage for large contexts, query offsets, chunked\nselection, tracing, and CUDA graph execution.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n\n---------\n\nCo-authored-by: Claude Fable 5 <noreply@anthropic.com>"},"path":{"kind":"string","value":"flashinfer/msa_ops/cute_dsl/proxy_score_sm12x.py"},"language":{"kind":"string","value":"cute_dsl"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"\"\"\"\nCopyright (c) 2026 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nMSA dense proxy-score kernels for SM120/SM121: per (head, KV block, query) max\nof the unscaled post-mask QK^T logits; masked blocks yield -inf.\n\"\"\"\n\nfrom typing import Type\n\nimport cuda.bindings.driver as cuda\nimport cutlass\nimport cutlass.cute as cute\nimport cutlass.pipeline as pipeline\nfrom cutlass._mlir.dialects import llvm\nfrom cutlass.cute.nvgpu import cpasync, warp\nfrom cutlass.cutlass_dsl import T, dsl_user_op\n\n\n@dsl_user_op\ndef _fp8x4_to_f16x4(x: cutlass.Uint32, *, loc=None, ip=None):\n out = llvm.inline_asm(\n llvm.StructType.get_literal([T.i32()] * 2),\n [x.ir_value(loc=loc, ip=ip)],\n \"{\\n\\t\"\n \".reg .b16 lo, hi;\\n\\t\"\n \"mov.b32 {lo, hi}, $2;\\n\\t\"\n \"cvt.rn.f16x2.e4m3x2 $0, lo;\\n\\t\"\n \"cvt.rn.f16x2.e4m3x2 $1, hi;\\n\\t\"\n \"}\\n\",\n \"=r,=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n loc=loc,\n ip=ip,\n )\n return (\n cutlass.Uint32(llvm.extractvalue(T.i32(), out, [0], loc=loc, ip=ip)),\n cutlass.Uint32(llvm.extractvalue(T.i32(), out, [1], loc=loc, ip=ip)),\n )\n\n\n@dsl_user_op\ndef _fp8x4_to_bf16x4(x: cutlass.Uint32, *, loc=None, ip=None):\n # There is no e4m3 -> bf16 cvt; round-trip through f16, which is exact\n # (every e4m3 value is representable in both f16 and bf16).\n out = llvm.inline_asm(\n llvm.StructType.get_literal([T.i32()] * 2),\n [x.ir_value(loc=loc, ip=ip)],\n \"{\\n\\t\"\n \".reg .b16 lo, hi, t00, t01, t10, t11;\\n\\t\"\n \"mov.b32 {lo, hi}, $2;\\n\\t\"\n \"cvt.rn.f16x2.e4m3x2 $0, lo;\\n\\t\"\n \"cvt.rn.f16x2.e4m3x2 $1, hi;\\n\\t\"\n \"mov.b32 {t00, t01}, $0;\\n\\t\"\n \"mov.b32 {t10, t11}, $1;\\n\\t\"\n \"cvt.rn.bf16.f16 t00, t00;\\n\\t\"\n \"cvt.rn.bf16.f16 t01, t01;\\n\\t\"\n \"cvt.rn.bf16.f16 t10, t10;\\n\\t\"\n \"cvt.rn.bf16.f16 t11, t11;\\n\\t\"\n \"mov.b32 $0, {t00, t01};\\n\\t\"\n \"mov.b32 $1, {t10, t11};\\n\\t\"\n \"}\\n\",\n \"=r,=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n loc=loc,\n ip=ip,\n )\n return (\n cutlass.Uint32(llvm.extractvalue(T.i32(), out, [0], loc=loc, ip=ip)),\n cutlass.Uint32(llvm.extractvalue(T.i32(), out, [1], loc=loc, ip=ip)),\n )\n\n\n@cute.jit\ndef _cvt_fp8_frag(src: cute.Tensor, dst: cute.Tensor):\n \"\"\"Convert an e4m3 register fragment to dst's f16/bf16 element type with\n packed cvt (one instruction per four elements); element-wise ``.to()``\n lowers to a byte-extract sequence.\"\"\"\n src_u32 = cute.recast_tensor(src, cutlass.Uint32)\n dst_u32 = cute.recast_tensor(dst, cutlass.Uint32)\n for i in cutlass.range_constexpr(cute.size(src.shape) // 4):\n if cutlass.const_expr(dst.element_type is cutlass.BFloat16):\n lo, hi = _fp8x4_to_bf16x4(src_u32[i])\n else:\n lo, hi = _fp8x4_to_f16x4(src_u32[i])\n dst_u32[i * 2] = lo\n dst_u32[i * 2 + 1] = hi\n\n\nclass MsaProxyScoreSm12x:\n \"\"\"General bf16/fp16 proxy schedule (any q length, fp8 K, flat or paged):\n every query head scores against its kv_head's index-K independently.\"\"\"\n\n def __init__(\n self,\n head_dim: int = 128,\n m_block_size: int = 64,\n n_block_size: int = 128,\n num_threads: int = 128,\n is_causal: bool = True,\n paged: bool = False,\n kv_fp8: bool = False,\n ):\n if head_dim != 128 or n_block_size != 128:\n raise ValueError(\"only head_dim == n_block_size == 128 is supported\")\n self._head_dim = head_dim\n self._m_block_size = m_block_size\n self._n_block_size = n_block_size\n self._num_threads = num_threads\n self._is_causal = is_causal\n self._paged = paged\n self._kv_fp8 = kv_fp8\n\n self.cta_sync_barrier = pipeline.NamedBarrier(\n barrier_id=1, num_threads=num_threads\n )\n\n def _make_sk_layout(self):\n \"\"\"K SMEM layout (built in-kernel for region isolation). The fp8\n convert path stores 16B-aligned chunks, so the swizzle works for it\n too; a padded layout would cost a second CTA per SM (48KB -> >50KB).\"\"\"\n atom = cute.make_composed_layout(\n cute.make_swizzle(3, 3, 3),\n 0,\n cute.make_layout((8, 64), stride=(64, 1)),\n )\n return cute.tile_to_shape(atom, (self._n_block_size, self._head_dim), (0, 1))\n\n def _make_sq_layout(self):\n atom = cute.make_composed_layout(\n cute.make_swizzle(3, 3, 3),\n 0,\n cute.make_layout((8, 64), stride=(64, 1)),\n )\n return cute.tile_to_shape(atom, (self._m_block_size, self._head_dim), (0, 1))\n\n @cute.jit\n def __call__(\n self,\n mQ: cute.Tensor, # (total_q, Hq, d)\n mK: cute.Tensor, # (total_k, Hkv, d) flat | (pages, Hkv, 128, d) paged\n mPageTable: cute.Tensor, # (B, max_pages) int32 (dummy (1,1) if flat)\n mMaxScore: cute.Tensor, # (Hq, max_k_tiles, total_q) f32\n mCuQ: cute.Tensor, # (B + 1,) int32\n mCuK: cute.Tensor, # (B + 1,) int32\n mQOffset: cute.Tensor, # (B,) int32 causal offset (MSA q_offset)\n max_seqlen_q: cutlass.Int32,\n batch_size: cutlass.Int32,\n num_qo_heads: cutlass.Int32,\n max_k_tiles: cutlass.Int32,\n num_splits: cutlass.Int32,\n stream: cuda.CUstream,\n ):\n if cutlass.const_expr(\n not (\n mQ.element_type == cutlass.Float16\n or mQ.element_type == cutlass.BFloat16\n )\n ):\n raise TypeError(\"Only Float16 or BFloat16 q is supported\")\n self._dtype: Type[cutlass.Numeric] = mQ.element_type\n\n # Split-K: fold a kv-block split factor into grid x to fill the SMs when the\n # base grid (1, batch, heads) starves at low batch. Output is per-(head,\n # kv_block, query) so splits write disjoint columns, no reduction.\n self.kernel(\n mQ,\n mK,\n mPageTable,\n mMaxScore,\n mCuQ,\n mCuK,\n mQOffset,\n max_k_tiles,\n num_splits,\n ).launch(\n grid=(\n cute.ceil_div(max_seqlen_q, self._m_block_size) * num_splits,\n batch_size,\n num_qo_heads,\n ),\n block=[self._num_threads, 1, 1],\n stream=stream,\n )\n\n @cute.kernel\n def kernel(\n self,\n mQ: cute.Tensor,\n mK: cute.Tensor,\n mPageTable: cute.Tensor,\n mMaxScore: cute.Tensor,\n mCuQ: cute.Tensor,\n mCuK: cute.Tensor,\n mQOffset: cute.Tensor,\n max_k_tiles: cutlass.Int32,\n num_splits: cutlass.Int32,\n ):\n tidx, _, _ = cute.arch.thread_idx()\n bx, batch_idx, qo_head = cute.arch.block_idx()\n # grid x packs (m_block, split): splits of one m_block are adjacent so\n # they share the same Q tile in L2 (only the kv-block subset differs).\n m_block = bx // num_splits\n split_idx = bx % num_splits\n\n q_start = mCuQ[batch_idx]\n seqlen_q = mCuQ[batch_idx + 1] - q_start\n if cutlass.const_expr(self._paged):\n # mCuK holds per-request lengths on the paged path:\n # page_table supplies every KV address, so there is\n # no base offset to add.\n k_start = cutlass.Int32(0)\n seqlen_k = mCuK[batch_idx]\n else:\n k_start = mCuK[batch_idx]\n seqlen_k = mCuK[batch_idx + 1] - k_start\n num_kv_blocks = cute.ceil_div(seqlen_k, self._n_block_size)\n group_size = mQ.shape[1] // mK.shape[1]\n kv_head = qo_head // group_size\n\n if m_block * self._m_block_size < seqlen_q:\n sQ_layout = self._make_sq_layout()\n sK_layout = self._make_sk_layout()\n\n @cute.struct\n class SharedStorage:\n sQ: cute.struct.Align[\n cute.struct.MemRange[self._dtype, cute.cosize(sQ_layout)],\n 1024,\n ]\n sK: cute.struct.Align[\n cute.struct.MemRange[self._dtype, cute.cosize(sK_layout)],\n 1024,\n ]\n\n smem = cutlass.utils.SmemAllocator()\n storage = smem.allocate(SharedStorage)\n sQ = storage.sQ.get_tensor(sQ_layout)\n sK = storage.sK.get_tensor(sK_layout)\n\n # K is in this tiled copy only on the non-fp8 path (fp8 K loads separately)\n universal_copy_bits = 128\n async_copy_elems = universal_copy_bits // self._dtype.width\n atom_async_copy = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n self._dtype,\n num_bits_per_copy=universal_copy_bits,\n )\n t_dim1 = 64 // async_copy_elems\n t_layout = cute.make_layout(\n (self._num_threads // t_dim1, t_dim1), stride=(t_dim1, 1)\n )\n v_layout = cute.make_layout((1, async_copy_elems))\n gmem_tiled_copy = cute.make_tiled_copy_tv(\n atom_async_copy, t_layout, v_layout\n )\n gmem_thr_copy = gmem_tiled_copy.get_slice(tidx)\n\n mQ_h = cute.domain_offset((q_start, 0), mQ[None, qo_head, None])\n gQ = cute.local_tile(\n mQ_h, (self._m_block_size, self._head_dim), (m_block, 0)\n )\n tQgQ = gmem_thr_copy.partition_S(gQ)\n tQsQ = gmem_thr_copy.partition_D(sQ)\n cQ = cute.make_identity_tensor((self._m_block_size, self._head_dim))\n tQcQ = gmem_thr_copy.partition_S(cQ)\n\n for m in cutlass.range_constexpr(cute.size(tQsQ.shape[1])):\n if (m_block * self._m_block_size + tQcQ[0, m, 0][0]) < seqlen_q:\n cute.copy(\n gmem_tiled_copy,\n tQgQ[None, m, None],\n tQsQ[None, m, None],\n )\n else:\n tQsQ[None, m, None].fill(0)\n cute.arch.cp_async_commit_group()\n\n tiled_mma = cute.make_tiled_mma(\n warp.MmaF16BF16Op(self._dtype, cutlass.Float32, (16, 8, 16)),\n (self._num_threads // 32, 1, 1),\n permutation_mnk=(self._num_threads // 32 * 16, 16, 16),\n )\n thr_mma = tiled_mma.get_slice(tidx)\n tSrQ = thr_mma.make_fragment_A(thr_mma.partition_A(sQ))\n tSrK = thr_mma.make_fragment_B(thr_mma.partition_B(sK))\n acc_S = cute.make_rmem_tensor(\n thr_mma.partition_shape_C((self._m_block_size, self._n_block_size)),\n cutlass.Float32,\n )\n\n smem_copy_atom = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(transpose=False, num_matrices=4),\n self._dtype,\n )\n smem_tiled_copy_Q = cute.make_tiled_copy_A(smem_copy_atom, tiled_mma)\n smem_tiled_copy_K = cute.make_tiled_copy_B(smem_copy_atom, tiled_mma)\n smem_thr_copy_Q = smem_tiled_copy_Q.get_slice(tidx)\n smem_thr_copy_K = smem_tiled_copy_K.get_slice(tidx)\n tSsQ = smem_thr_copy_Q.partition_S(sQ)\n tSrQ_copy_view = smem_thr_copy_Q.retile(tSrQ)\n tSsK = smem_thr_copy_K.partition_S(sK)\n tSrK_copy_view = smem_thr_copy_K.retile(tSrK)\n\n cS = cute.make_identity_tensor((self._m_block_size, self._n_block_size))\n tScS_mn = self._make_acc_tensor_mn_view(thr_mma.partition_C(cS))\n acc_S_mn = self._make_acc_tensor_mn_view(acc_S)\n n_rows = cute.size(acc_S_mn.shape[0])\n\n # K gmem views; the block mode is indexed after partitioning so the\n # copy tile shapes stay static.\n if cutlass.const_expr(not self._kv_fp8):\n if cutlass.const_expr(self._paged):\n pass # per-block page lookup happens inside the loop\n else:\n mK_h = cute.domain_offset((k_start, 0), mK[None, kv_head, None])\n gK = cute.local_tile(\n mK_h, (self._n_block_size, self._head_dim), (None, 0)\n )\n tKgK_flat = gmem_thr_copy.partition_S(gK)\n tKsK = gmem_thr_copy.partition_D(sK)\n cKV = cute.make_identity_tensor((self._n_block_size, self._head_dim))\n tKVcKV = gmem_thr_copy.partition_S(cKV)\n\n # sQ is reused across all kv-blocks, so Q fragments load once here\n cute.arch.cp_async_wait_group(0)\n self.cta_sync_barrier.arrive_and_wait()\n for kk in cutlass.range_constexpr(cute.size(tSsQ.shape[2])):\n cute.copy(\n smem_tiled_copy_Q,\n tSsQ[None, None, kk],\n tSrQ_copy_view[None, None, kk],\n )\n\n # Split-K CTAs stride kv_block by num_splits. Causal skip: kv-blocks\n # entirely above the q-tile's causal limit get their -inf written directly,\n # with no K load or MMA (masking after the MMA would waste the work).\n if cutlass.const_expr(self._is_causal):\n causal_last = (\n m_block * self._m_block_size\n + (self._m_block_size - 1)\n + mQOffset[batch_idx]\n ) // self._n_block_size\n last_block = cutlass.min(causal_last, num_kv_blocks - 1)\n else:\n last_block = num_kv_blocks - 1\n\n n_iter = cute.ceil_div(max_k_tiles, num_splits)\n for it in cutlass.range(n_iter):\n kv_block = split_idx + it * num_splits\n if kv_block <= last_block:\n self.cta_sync_barrier.arrive_and_wait()\n if cutlass.const_expr(self._kv_fp8):\n if cutlass.const_expr(self._paged):\n page8 = mPageTable[batch_idx, kv_block]\n mK_h8 = mK[page8, kv_head, None, None]\n row_off8 = cutlass.Int32(0)\n else:\n mK_h8 = cute.domain_offset(\n (k_start, 0), mK[None, kv_head, None]\n )\n row_off8 = kv_block * self._n_block_size\n chunks_per_row = self._head_dim // 8\n total_chunks = self._n_block_size * chunks_per_row\n cvt_frag = cute.make_rmem_tensor(\n cute.make_layout(8), self._dtype\n )\n for kv_it in cutlass.range_constexpr(\n total_chunks // self._num_threads\n ):\n kv_chunk = tidx + kv_it * self._num_threads\n kv_m = kv_chunk // chunks_per_row\n kv_c8 = kv_chunk % chunks_per_row\n sK_chunk = cute.local_tile(sK[kv_m, None], (8,), (kv_c8,))\n if (kv_block * self._n_block_size + kv_m) < seqlen_k:\n gKc = cute.local_tile(\n mK_h8[row_off8 + kv_m, None], (8,), (kv_c8,)\n )\n cvt_frag.store(\n gKc.load()\n .to(cutlass.Float16)\n .to(cutlass.Float32)\n .to(self._dtype)\n )\n else:\n cvt_frag.fill(0)\n cute.autovec_copy(cvt_frag, sK_chunk)\n else:\n # Branch bodies keep their own tensor names: aliasing an outer\n # tensor in this dynamic loop would make it loop-carried.\n if cutlass.const_expr(self._paged):\n page = mPageTable[batch_idx, kv_block]\n gK_pg = cute.local_tile(\n mK[page, kv_head, None, None],\n (self._n_block_size, self._head_dim),\n (None, 0),\n )\n tKgK_pg = gmem_thr_copy.partition_S(gK_pg)\n for n in cutlass.range_constexpr(cute.size(tKsK.shape[1])):\n if (\n kv_block * self._n_block_size + tKVcKV[0, n, 0][0]\n ) < seqlen_k:\n cute.copy(\n gmem_tiled_copy,\n tKgK_pg[None, n, None, 0],\n tKsK[None, n, None],\n )\n else:\n tKsK[None, n, None].fill(0)\n else:\n for n in cutlass.range_constexpr(cute.size(tKsK.shape[1])):\n if (\n kv_block * self._n_block_size + tKVcKV[0, n, 0][0]\n ) < seqlen_k:\n cute.copy(\n gmem_tiled_copy,\n tKgK_flat[None, n, None, kv_block],\n tKsK[None, n, None],\n )\n else:\n tKsK[None, n, None].fill(0)\n cute.arch.cp_async_commit_group()\n cute.arch.cp_async_wait_group(0)\n self.cta_sync_barrier.arrive_and_wait()\n\n # S = Q K^T (unscaled)\n acc_S.fill(0.0)\n for kk in cutlass.range_constexpr(cute.size(tSsK.shape[2])):\n cute.copy(\n smem_tiled_copy_K,\n tSsK[None, None, kk],\n tSrK_copy_view[None, None, kk],\n )\n for kk in cutlass.range_constexpr(cute.size(tSsK.shape[2])):\n cute.gemm(\n tiled_mma,\n acc_S,\n tSrQ[None, None, kk],\n tSrK[None, None, kk],\n acc_S,\n )\n\n for r in cutlass.range_constexpr(n_rows):\n row_local = tScS_mn[r, 0][0]\n q_loc = m_block * self._m_block_size + row_local\n if cutlass.const_expr(self._is_causal):\n col_limit = cutlass.min(\n q_loc + mQOffset[batch_idx] + 1, seqlen_k\n )\n else:\n col_limit = seqlen_k\n for c in cutlass.range_constexpr(cute.size(tScS_mn.shape[1])):\n k_pos = kv_block * self._n_block_size + tScS_mn[0, c][1]\n if cute.elem_less(col_limit, k_pos + 1):\n acc_S_mn[r, c] = -cutlass.Float32.inf\n tile_max = (\n acc_S_mn[r, None]\n .load()\n .reduce(cute.ReductionOp.MAX, -cutlass.Float32.inf, 0)\n )\n tile_max = self._threadquad_reduce_max(tile_max)\n if q_loc < seqlen_q:\n # All 4 quad threads hold the same value; the\n # duplicate stores are idempotent.\n mMaxScore[qo_head, kv_block, q_start + q_loc] = tile_max\n elif kv_block < max_k_tiles:\n # Blocks past last_block (causally future or padding) get -inf, no\n # MMA. Bounded by max_k_tiles so split-K overshoot writes nothing.\n for r in cutlass.range_constexpr(n_rows):\n row_local2 = tScS_mn[r, 0][0]\n q_loc2 = m_block * self._m_block_size + row_local2\n if q_loc2 < seqlen_q:\n mMaxScore[\n qo_head, kv_block, q_start + q_loc2\n ] = -cutlass.Float32.inf\n\n @cute.jit\n def _threadquad_reduce_max(self, val):\n val = cute.arch.fmax(\n val,\n cute.arch.shuffle_sync_bfly(val, offset=2, mask=-1, mask_and_clamp=31),\n )\n val = cute.arch.fmax(\n val,\n cute.arch.shuffle_sync_bfly(val, offset=1, mask=-1, mask_and_clamp=31),\n )\n return val\n\n def _make_acc_tensor_mn_view(self, acc: cute.Tensor) -> cute.Tensor:\n acc_layout_col_major = cute.make_layout(acc.layout.shape)\n acc_layout_mn = cute.make_layout(\n (\n (acc_layout_col_major.shape[0][1], acc_layout_col_major.shape[1]),\n (acc_layout_col_major.shape[0][0], acc_layout_col_major.shape[2]),\n ),\n stride=(\n (acc_layout_col_major.stride[0][1], acc_layout_col_major.stride[1]),\n (acc_layout_col_major.stride[0][0], acc_layout_col_major.stride[2]),\n ),\n )\n acc_layout_mn = cute.composition(acc.layout, acc_layout_mn)\n return cute.make_tensor(acc.iterator, acc_layout_mn)\n\n\nclass MsaProxyScoreDecodePackedSm12x(MsaProxyScoreSm12x):\n \"\"\"Head-fused packed-decode bf16/fp16 schedule: packs qhead_per_kv heads x\n pack_q_len tokens into the M rows so the shared index-K is read once per\n kv_head. fp8 K takes the key-split subclass instead.\"\"\"\n\n def __init__(\n self,\n head_dim: int = 128,\n m_block_size: int = 64,\n n_block_size: int = 128,\n num_threads: int = 128,\n is_causal: bool = True,\n paged: bool = False,\n kv_fp8: bool = False,\n qhead_per_kv: int = 4,\n pack_q_len: int = 16,\n ):\n super().__init__(\n head_dim=head_dim,\n m_block_size=m_block_size,\n n_block_size=n_block_size,\n num_threads=num_threads,\n is_causal=is_causal,\n paged=paged,\n kv_fp8=kv_fp8,\n )\n if qhead_per_kv * pack_q_len != m_block_size:\n raise ValueError(\n f\"qhead_per_kv * pack_q_len must equal the {m_block_size}-row MMA \"\n f\"tile, got {qhead_per_kv} x {pack_q_len}\"\n )\n # These attrs are constexpr-baked into the gather/epilogue, so each\n # factorization compiles to its own kernel.\n self._qhead_per_kv = qhead_per_kv\n self._pack_q_len = pack_q_len\n\n @cute.jit\n def __call__(\n self,\n mQ: cute.Tensor,\n mK: cute.Tensor,\n mPageTable: cute.Tensor,\n mMaxScore: cute.Tensor,\n mCuQ: cute.Tensor,\n mCuK: cute.Tensor,\n mQOffset: cute.Tensor,\n max_seqlen_q: cutlass.Int32,\n batch_size: cutlass.Int32,\n num_qo_heads: cutlass.Int32,\n max_k_tiles: cutlass.Int32,\n num_splits: cutlass.Int32,\n stream: cuda.CUstream,\n ):\n if cutlass.const_expr(\n not (\n mQ.element_type == cutlass.Float16\n or mQ.element_type == cutlass.BFloat16\n )\n ):\n raise TypeError(\"Only Float16 or BFloat16 q is supported\")\n self._dtype: Type[cutlass.Numeric] = mQ.element_type\n\n # One CTA per (split, batch, kv_head): all qhead_per_kv heads of a kv_head\n # are packed into the single m_block_size-row tile, so the index-K is read\n # once per kv_head (qhead_per_kv x less K traffic than the per-head schedule).\n self.kernel(\n mQ,\n mK,\n mPageTable,\n mMaxScore,\n mCuQ,\n mCuK,\n mQOffset,\n max_k_tiles,\n num_splits,\n ).launch(\n grid=(\n num_splits,\n batch_size,\n num_qo_heads // self._qhead_per_kv,\n ),\n block=[self._num_threads, 1, 1],\n stream=stream,\n )\n\n @cute.kernel\n def kernel(\n self,\n mQ: cute.Tensor,\n mK: cute.Tensor,\n mPageTable: cute.Tensor,\n mMaxScore: cute.Tensor,\n mCuQ: cute.Tensor,\n mCuK: cute.Tensor,\n mQOffset: cute.Tensor,\n max_k_tiles: cutlass.Int32,\n num_splits: cutlass.Int32,\n ):\n tidx, _, _ = cute.arch.thread_idx()\n split_idx, batch_idx, kv_head = cute.arch.block_idx()\n\n q_start = mCuQ[batch_idx]\n seqlen_q = mCuQ[batch_idx + 1] - q_start\n if cutlass.const_expr(self._paged):\n # mCuK holds per-request lengths on the paged path:\n # page_table supplies every KV address, so there is\n # no base offset to add.\n k_start = cutlass.Int32(0)\n seqlen_k = mCuK[batch_idx]\n else:\n k_start = mCuK[batch_idx]\n seqlen_k = mCuK[batch_idx + 1] - k_start\n num_kv_blocks = cute.ceil_div(seqlen_k, self._n_block_size)\n\n sQ_layout = self._make_sq_layout()\n sK_layout = self._make_sk_layout()\n\n @cute.struct\n class SharedStorage:\n sQ: cute.struct.Align[\n cute.struct.MemRange[self._dtype, cute.cosize(sQ_layout)],\n 1024,\n ]\n sK: cute.struct.Align[\n cute.struct.MemRange[self._dtype, cute.cosize(sK_layout)],\n 1024,\n ]\n\n smem = cutlass.utils.SmemAllocator()\n storage = smem.allocate(SharedStorage)\n sQ = storage.sQ.get_tensor(sQ_layout)\n sK = storage.sK.get_tensor(sK_layout)\n\n # Tiled copy covers K only; Q is gathered per-head below\n universal_copy_bits = 128\n async_copy_elems = universal_copy_bits // self._dtype.width\n atom_async_copy = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n self._dtype,\n num_bits_per_copy=universal_copy_bits,\n )\n t_dim1 = 64 // async_copy_elems\n t_layout = cute.make_layout(\n (self._num_threads // t_dim1, t_dim1), stride=(t_dim1, 1)\n )\n v_layout = cute.make_layout((1, async_copy_elems))\n gmem_tiled_copy = cute.make_tiled_copy_tv(atom_async_copy, t_layout, v_layout)\n gmem_thr_copy = gmem_tiled_copy.get_slice(tidx)\n\n self._gather_packed_q(mQ, sQ, q_start, kv_head, seqlen_q, tidx)\n\n tiled_mma = cute.make_tiled_mma(\n warp.MmaF16BF16Op(self._dtype, cutlass.Float32, (16, 8, 16)),\n (self._num_threads // 32, 1, 1),\n permutation_mnk=(self._num_threads // 32 * 16, 16, 16),\n )\n thr_mma = tiled_mma.get_slice(tidx)\n tSrQ = thr_mma.make_fragment_A(thr_mma.partition_A(sQ))\n tSrK = thr_mma.make_fragment_B(thr_mma.partition_B(sK))\n acc_S = cute.make_rmem_tensor(\n thr_mma.partition_shape_C((self._m_block_size, self._n_block_size)),\n cutlass.Float32,\n )\n\n smem_copy_atom = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(transpose=False, num_matrices=4),\n self._dtype,\n )\n smem_tiled_copy_Q = cute.make_tiled_copy_A(smem_copy_atom, tiled_mma)\n smem_tiled_copy_K = cute.make_tiled_copy_B(smem_copy_atom, tiled_mma)\n smem_thr_copy_Q = smem_tiled_copy_Q.get_slice(tidx)\n smem_thr_copy_K = smem_tiled_copy_K.get_slice(tidx)\n tSsQ = smem_thr_copy_Q.partition_S(sQ)\n tSrQ_copy_view = smem_thr_copy_Q.retile(tSrQ)\n tSsK = smem_thr_copy_K.partition_S(sK)\n tSrK_copy_view = smem_thr_copy_K.retile(tSrK)\n\n cS = cute.make_identity_tensor((self._m_block_size, self._n_block_size))\n tScS_mn = self._make_acc_tensor_mn_view(thr_mma.partition_C(cS))\n acc_S_mn = self._make_acc_tensor_mn_view(acc_S)\n n_rows = cute.size(acc_S_mn.shape[0])\n\n # K gmem views, as in the general kernel.\n if cutlass.const_expr(self._paged):\n pass # per-block page lookup happens inside the loop\n else:\n mK_h = cute.domain_offset((k_start, 0), mK[None, kv_head, None])\n gK = cute.local_tile(mK_h, (self._n_block_size, self._head_dim), (None, 0))\n tKgK_flat = gmem_thr_copy.partition_S(gK)\n tKsK = gmem_thr_copy.partition_D(sK)\n cKV = cute.make_identity_tensor((self._n_block_size, self._head_dim))\n tKVcKV = gmem_thr_copy.partition_S(cKV)\n\n # Gather stores are synchronous; order them before the Q fragment reads,\n # then preload the Q fragments once (sQ reused across all kv-blocks).\n self.cta_sync_barrier.arrive_and_wait()\n for kk in cutlass.range_constexpr(cute.size(tSsQ.shape[2])):\n cute.copy(\n smem_tiled_copy_Q,\n tSsQ[None, None, kk],\n tSrQ_copy_view[None, None, kk],\n )\n\n # Split-K CTAs stride kv_block by num_splits, as in the general kernel.\n # No causal skip here: packed decode attends every kv-block and masks\n # the per-token causal tail in the epilogue.\n n_iter = cute.ceil_div(max_k_tiles, num_splits)\n for it in cutlass.range(n_iter):\n kv_block = split_idx + it * num_splits\n if kv_block < num_kv_blocks:\n self.cta_sync_barrier.arrive_and_wait()\n if cutlass.const_expr(self._paged):\n page = mPageTable[batch_idx, kv_block]\n gK_pg = cute.local_tile(\n mK[page, kv_head, None, None],\n (self._n_block_size, self._head_dim),\n (None, 0),\n )\n tKgK_pg = gmem_thr_copy.partition_S(gK_pg)\n for n in cutlass.range_constexpr(cute.size(tKsK.shape[1])):\n if (\n kv_block * self._n_block_size + tKVcKV[0, n, 0][0]\n ) < seqlen_k:\n cute.copy(\n gmem_tiled_copy,\n tKgK_pg[None, n, None, 0],\n tKsK[None, n, None],\n )\n else:\n tKsK[None, n, None].fill(0)\n else:\n for n in cutlass.range_constexpr(cute.size(tKsK.shape[1])):\n if (\n kv_block * self._n_block_size + tKVcKV[0, n, 0][0]\n ) < seqlen_k:\n cute.copy(\n gmem_tiled_copy,\n tKgK_flat[None, n, None, kv_block],\n tKsK[None, n, None],\n )\n else:\n tKsK[None, n, None].fill(0)\n cute.arch.cp_async_commit_group()\n cute.arch.cp_async_wait_group(0)\n self.cta_sync_barrier.arrive_and_wait()\n\n # S = Q K^T (unscaled)\n acc_S.fill(0.0)\n for kk in cutlass.range_constexpr(cute.size(tSsK.shape[2])):\n cute.copy(\n smem_tiled_copy_K,\n tSsK[None, None, kk],\n tSrK_copy_view[None, None, kk],\n )\n for kk in cutlass.range_constexpr(cute.size(tSsK.shape[2])):\n cute.gemm(\n tiled_mma,\n acc_S,\n tSrQ[None, None, kk],\n tSrK[None, None, kk],\n acc_S,\n )\n\n # A packed row maps to (local_head, token); a packed query's causal\n # position is its token index (the decode q within this step).\n for r in cutlass.range_constexpr(n_rows):\n row = tScS_mn[r, 0][0]\n token = row % self._pack_q_len\n if cutlass.const_expr(self._is_causal):\n col_limit = cutlass.min(\n token + mQOffset[batch_idx] + 1, seqlen_k\n )\n else:\n col_limit = seqlen_k\n for c in cutlass.range_constexpr(cute.size(tScS_mn.shape[1])):\n k_pos = kv_block * self._n_block_size + tScS_mn[0, c][1]\n if cute.elem_less(col_limit, k_pos + 1):\n acc_S_mn[r, c] = -cutlass.Float32.inf\n tile_max = (\n acc_S_mn[r, None]\n .load()\n .reduce(cute.ReductionOp.MAX, -cutlass.Float32.inf, 0)\n )\n tile_max = self._threadquad_reduce_max(tile_max)\n local_head = row // self._pack_q_len\n head = kv_head * self._qhead_per_kv + local_head\n if cute.elem_less(token, seqlen_q):\n # All 4 quad threads hold the same value; the duplicate\n # stores are idempotent.\n mMaxScore[head, kv_block, q_start + token] = tile_max\n elif kv_block < max_k_tiles:\n # Padding tile in [num_kv_blocks, max_k_tiles) -> -inf. Bounded by\n # max_k_tiles because split-K can stride kv_block past the last\n # output column (those overshoot blocks write nothing).\n for r in cutlass.range_constexpr(n_rows):\n row2 = tScS_mn[r, 0][0]\n token2 = row2 % self._pack_q_len\n local_head2 = row2 // self._pack_q_len\n head2 = kv_head * self._qhead_per_kv + local_head2\n if cute.elem_less(token2, seqlen_q):\n mMaxScore[\n head2, kv_block, q_start + token2\n ] = -cutlass.Float32.inf\n\n @cute.jit\n def _gather_packed_q(self, mQ, sQ, q_start, kv_head, seqlen_q, tidx):\n \"\"\"Gather the packed Q tile into swizzled smem; rows past seqlen_q are\n zero-filled (epilogue masks them).\"\"\"\n elems = 128 // self._dtype.width\n chunks = self._head_dim // elems\n total = self._m_block_size * chunks\n frag = cute.make_rmem_tensor(cute.make_layout(elems), self._dtype)\n for it in cutlass.range_constexpr(total // self._num_threads):\n e = tidx + it * self._num_threads\n r = e // chunks\n c8 = e % chunks\n local_head = r // self._pack_q_len\n token = r % self._pack_q_len\n head = kv_head * self._qhead_per_kv + local_head\n sQ_chunk = cute.local_tile(sQ[r, None], (elems,), (c8,))\n if cute.elem_less(token, seqlen_q):\n gQ_chunk = cute.local_tile(\n mQ[q_start + token, head, None], (elems,), (c8,)\n )\n frag.store(gQ_chunk.load())\n cute.autovec_copy(frag, sQ_chunk)\n else:\n sQ_chunk.fill(0)\n\n\nclass MsaProxyScoreDecodePackedFp8Sm12x(MsaProxyScoreDecodePackedSm12x):\n \"\"\"fp8-K packed-decode schedule. Same head-fused M rows as the packed\n schedule, but warps split over keys instead of query rows, so the\n e4m3 -> f16/bf16 upconvert runs once per K element instead of once per\n warp. K stays raw e4m3 through cp.async\n and smem, arriving as a 16-bit view with half the head dim (see\n msa_proxy_score), and upconverts in registers between the smem loads and\n the mma. Q is stored column-permuted to match the converted K fragments\n (see _gather_packed_q).\n\n K staging is pipelined at two granularities because split-K often leaves\n a CTA a single KV block: two smem buffers with a one-block prefetch\n overlap across blocks, and each fill commits as two 64-key cp.async\n groups so the mma starts on the first half while the second is still in\n flight.\n \"\"\"\n\n @cute.kernel\n def kernel(\n self,\n mQ: cute.Tensor,\n mK: cute.Tensor,\n mPageTable: cute.Tensor,\n mMaxScore: cute.Tensor,\n mCuQ: cute.Tensor,\n mCuK: cute.Tensor,\n mQOffset: cute.Tensor,\n max_k_tiles: cutlass.Int32,\n num_splits: cutlass.Int32,\n ):\n tidx, _, _ = cute.arch.thread_idx()\n split_idx, batch_idx, kv_head = cute.arch.block_idx()\n\n q_start = mCuQ[batch_idx]\n seqlen_q = mCuQ[batch_idx + 1] - q_start\n if cutlass.const_expr(self._paged):\n # mCuK holds per-request lengths on the paged path:\n # page_table supplies every KV address, so there is\n # no base offset to add.\n k_start = cutlass.Int32(0)\n seqlen_k = mCuK[batch_idx]\n else:\n k_start = mCuK[batch_idx]\n seqlen_k = mCuK[batch_idx + 1] - k_start\n num_kv_blocks = cute.ceil_div(seqlen_k, self._n_block_size)\n\n sQ_layout = self._make_sq_layout()\n sK_layout = self._make_sk8_layout()\n\n @cute.struct\n class SharedStorage:\n sQ: cute.struct.Align[\n cute.struct.MemRange[self._dtype, cute.cosize(sQ_layout)],\n 1024,\n ]\n sK0: cute.struct.Align[\n cute.struct.MemRange[self._dtype, cute.cosize(sK_layout)],\n 1024,\n ]\n sK1: cute.struct.Align[\n cute.struct.MemRange[self._dtype, cute.cosize(sK_layout)],\n 1024,\n ]\n # Epilogue staging cannot alias K here: with the prefetch both K\n # buffers stay live across the epilogue window.\n sMax: cute.struct.Align[\n cute.struct.MemRange[cutlass.Float32, 4 * self._m_block_size],\n 16,\n ]\n\n smem = cutlass.utils.SmemAllocator()\n storage = smem.allocate(SharedStorage)\n sQ = storage.sQ.get_tensor(sQ_layout)\n sK0 = storage.sK0.get_tensor(sK_layout)\n sK1 = storage.sK1.get_tensor(sK_layout)\n # Full-width layout on the same pointer: shapes the mma B fragment\n # only, no accesses go through it.\n sK_frag_ref = cute.make_tensor(sK0.iterator, self._make_sk_layout())\n sMax = storage.sMax.get_tensor(cute.make_layout(4 * self._m_block_size))\n\n universal_copy_bits = 128\n async_copy_elems = universal_copy_bits // self._dtype.width\n atom_async_copy = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n self._dtype,\n num_bits_per_copy=universal_copy_bits,\n )\n t_dim1 = 64 // async_copy_elems\n t_layout = cute.make_layout(\n (self._num_threads // t_dim1, t_dim1), stride=(t_dim1, 1)\n )\n v_layout = cute.make_layout((1, async_copy_elems))\n gmem_tiled_copy = cute.make_tiled_copy_tv(atom_async_copy, t_layout, v_layout)\n gmem_thr_copy = gmem_tiled_copy.get_slice(tidx)\n\n # First block's K fill goes out before the synchronous Q gather so the\n # cp.async flight time hides under it.\n if split_idx < num_kv_blocks:\n self._fill_k8_tile(\n gmem_tiled_copy,\n gmem_thr_copy,\n mK,\n mPageTable,\n batch_idx,\n kv_head,\n k_start,\n split_idx,\n seqlen_k,\n sK0,\n )\n\n self._gather_packed_q(mQ, sQ, q_start, kv_head, seqlen_q, tidx)\n\n # Warps side by side along N: each owns interleaved 8-column slices\n # of the 128 keys (32 columns total), so the fp8 K fragments are\n # converted once instead of replicated across the M-split warps.\n num_warps = self._num_threads // 32\n tiled_mma = cute.make_tiled_mma(\n warp.MmaF16BF16Op(self._dtype, cutlass.Float32, (16, 8, 16)),\n (1, num_warps, 1),\n permutation_mnk=(16, num_warps * 8, 16),\n )\n thr_mma = tiled_mma.get_slice(tidx)\n tSrQ = thr_mma.make_fragment_A(thr_mma.partition_A(sQ))\n tSrK = thr_mma.make_fragment_B(thr_mma.partition_B(sK_frag_ref))\n acc_S = cute.make_rmem_tensor(\n thr_mma.partition_shape_C((self._m_block_size, self._n_block_size)),\n cutlass.Float32,\n )\n\n smem_copy_atom_Q = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(transpose=False, num_matrices=4),\n self._dtype,\n )\n smem_tiled_copy_Q = cute.make_tiled_copy_A(smem_copy_atom_Q, tiled_mma)\n smem_thr_copy_Q = smem_tiled_copy_Q.get_slice(tidx)\n tSsQ = smem_thr_copy_Q.partition_S(sQ)\n tSrQ_copy_view = smem_thr_copy_Q.retile(tSrQ)\n\n # B loads are plain 4B reads, not ldmatrix: a warp's slice per\n # (n-tile, k-step pair) is only 8 rows x 16B, which the ldmatrix tiled\n # copies cannot partition. The convert splits each 4-byte pair into\n # the even/odd mma k-steps; the resulting K-axis column permutation is\n # mirrored by the Q gather, so Q K^T is unchanged.\n kpair = cute.make_rmem_tensor(cute.make_layout(2), self._dtype)\n kpair_u32 = cute.recast_tensor(kpair, cutlass.Uint32)\n tSrK_u32 = cute.recast_tensor(\n cute.make_tensor(tSrK.iterator, cute.make_layout(cute.cosize(tSrK.layout))),\n cutlass.Uint32,\n )\n warp_idx = tidx // 32\n\n cS = cute.make_identity_tensor((self._m_block_size, self._n_block_size))\n tScS_mn = self._make_acc_tensor_mn_view(thr_mma.partition_C(cS))\n acc_S_mn = self._make_acc_tensor_mn_view(acc_S)\n n_rows = cute.size(acc_S_mn.shape[0])\n\n # Gather stores are synchronous; order them before the Q fragment\n # reads. Q fragments load per k-step inside the block loop, since a\n # full-tile preload would cost a CTA of occupancy.\n self.cta_sync_barrier.arrive_and_wait()\n\n # Buffer selection is a pointer pick rather than cloned fill/consume\n # bodies: small-batch grids run one cold-I-cache CTA per SM, where the\n # duplicated code costs more than it saves.\n base0 = sK0.iterator.toint()\n buf_step = sK1.iterator.toint() - base0\n\n n_iter = cute.ceil_div(max_k_tiles, num_splits)\n for it in cutlass.range(n_iter):\n kv_block = split_idx + it * num_splits\n if kv_block < num_kv_blocks:\n par = it % 2\n sK_cur = cute.make_tensor(\n cute.make_ptr(\n self._dtype,\n base0 + par * buf_step,\n cute.AddressSpace.smem,\n assumed_align=1024,\n ),\n sK_layout,\n )\n sK_nxt = cute.make_tensor(\n cute.make_ptr(\n self._dtype,\n base0 + (1 - par) * buf_step,\n cute.AddressSpace.smem,\n assumed_align=1024,\n ),\n sK_layout,\n )\n # Prefetch the next block into the idle buffer; its loads fly\n # under this block's mma and epilogue. Two commit groups go\n # out either way (empty ones at the tail), which keeps the\n # wait_group counts below static.\n nxt_block = kv_block + num_splits\n if nxt_block < num_kv_blocks:\n self._fill_k8_tile(\n gmem_tiled_copy,\n gmem_thr_copy,\n mK,\n mPageTable,\n batch_idx,\n kv_head,\n k_start,\n nxt_block,\n seqlen_k,\n sK_nxt,\n )\n else:\n cute.arch.cp_async_commit_group()\n cute.arch.cp_async_commit_group()\n\n # S = Q K^T (unscaled), consumed one 64-key half behind each\n # fill group so the mma starts before the tile finishes\n # landing.\n acc_S.fill(0.0)\n for h in cutlass.range_constexpr(2):\n cute.arch.cp_async_wait_group(3 - h)\n self.cta_sync_barrier.arrive_and_wait()\n self._consume_k8_half(\n h,\n sK_cur,\n smem_tiled_copy_Q,\n tSsQ,\n tSrQ,\n tSrQ_copy_view,\n tiled_mma,\n tSrK,\n tSrK_u32,\n kpair,\n kpair_u32,\n acc_S,\n )\n\n # Every warp's K fragment loads must land before the next\n # iteration's prefetch overwrites this buffer.\n self.cta_sync_barrier.arrive_and_wait()\n\n # Per-warp row maxes over the warp's 32 key columns, staged to\n # smem; one thread per row then joins the 4 warps and stores.\n for r in cutlass.range_constexpr(n_rows):\n row = tScS_mn[r, 0][0]\n token = row % self._pack_q_len\n if cutlass.const_expr(self._is_causal):\n col_limit = cutlass.min(\n token + mQOffset[batch_idx] + 1, seqlen_k\n )\n else:\n col_limit = seqlen_k\n for c in cutlass.range_constexpr(cute.size(tScS_mn.shape[1])):\n k_pos = kv_block * self._n_block_size + tScS_mn[0, c][1]\n if cute.elem_less(col_limit, k_pos + 1):\n acc_S_mn[r, c] = -cutlass.Float32.inf\n tile_max = (\n acc_S_mn[r, None]\n .load()\n .reduce(cute.ReductionOp.MAX, -cutlass.Float32.inf, 0)\n )\n tile_max = self._threadquad_reduce_max(tile_max)\n if tidx % 4 == 0:\n sMax[row * 4 + warp_idx] = tile_max\n self.cta_sync_barrier.arrive_and_wait()\n if tidx < self._m_block_size:\n row_max = sMax[tidx * 4]\n for w in cutlass.range_constexpr(1, 4):\n row_max = cute.arch.fmax(row_max, sMax[tidx * 4 + w])\n token_f = tidx % self._pack_q_len\n head_f = kv_head * self._qhead_per_kv + tidx // self._pack_q_len\n if cute.elem_less(token_f, seqlen_q):\n mMaxScore[head_f, kv_block, q_start + token_f] = row_max\n elif kv_block < max_k_tiles:\n # Padding tile in [num_kv_blocks, max_k_tiles) -> -inf, as in\n # the packed kernel.\n for r in cutlass.range_constexpr(n_rows):\n row2 = tScS_mn[r, 0][0]\n token2 = row2 % self._pack_q_len\n local_head2 = row2 // self._pack_q_len\n head2 = kv_head * self._qhead_per_kv + local_head2\n if cute.elem_less(token2, seqlen_q):\n mMaxScore[\n head2, kv_block, q_start + token2\n ] = -cutlass.Float32.inf\n\n @cute.jit\n def _fill_k8_tile(\n self,\n gmem_tiled_copy,\n gmem_thr_copy,\n mK: cute.Tensor,\n mPageTable: cute.Tensor,\n batch_idx: cutlass.Int32,\n kv_head: cutlass.Int32,\n k_start: cutlass.Int32,\n kv_block: cutlass.Int32,\n seqlen_k: cutlass.Int32,\n sK_buf: cute.Tensor,\n ):\n \"\"\"Issue one raw-e4m3 K tile's cp.async fill as two commit groups\n (keys 0-63 and 64-127), matching the consumer's half order.\"\"\"\n kw = self._head_dim // 2\n tKsK = gmem_thr_copy.partition_D(sK_buf)\n cKV = cute.make_identity_tensor((self._n_block_size, kw))\n tKVcKV = gmem_thr_copy.partition_S(cKV)\n if cutlass.const_expr(self._paged):\n page = mPageTable[batch_idx, kv_block]\n gK = cute.local_tile(\n mK[page, kv_head, None, None], (self._n_block_size, kw), (None, 0)\n )\n tKgK = gmem_thr_copy.partition_S(gK)[None, None, None, 0]\n else:\n mK_h = cute.domain_offset((k_start, 0), mK[None, kv_head, None])\n gK = cute.local_tile(mK_h, (self._n_block_size, kw), (None, 0))\n tKgK = gmem_thr_copy.partition_S(gK)[None, None, None, kv_block]\n n_passes = cute.size(tKsK.shape[1])\n for n in cutlass.range_constexpr(n_passes):\n if (kv_block * self._n_block_size + tKVcKV[0, n, 0][0]) < seqlen_k:\n cute.copy(gmem_tiled_copy, tKgK[None, n, None], tKsK[None, n, None])\n else:\n tKsK[None, n, None].fill(0)\n if n == n_passes // 2 - 1:\n cute.arch.cp_async_commit_group()\n cute.arch.cp_async_commit_group()\n\n @cute.jit\n def _consume_k8_half(\n self,\n half: cutlass.Constexpr,\n sK_buf: cute.Tensor,\n smem_tiled_copy_Q,\n tSsQ: cute.Tensor,\n tSrQ: cute.Tensor,\n tSrQ_copy_view: cute.Tensor,\n tiled_mma,\n tSrK: cute.Tensor,\n tSrK_u32: cute.Tensor,\n kpair: cute.Tensor,\n kpair_u32: cute.Tensor,\n acc_S: cute.Tensor,\n ):\n \"\"\"Convert-and-mma over one 64-key half (n-tiles ``2*half`` and\n ``2*half + 1``). Q fragments load just in time so ptxas keeps the\n per-thread A footprint at one k-step.\"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n # Fragment geometry of the m16n8k16 B atom: lane covers key row\n # n = 32*nt + 8*warp + lane//4 and k16 pairs at 2*(lane%4) (+8).\n nb_row = 8 * (tidx // 32) + (tidx % 32) // 4\n m4 = tidx % 4\n # This half's slice of the acc and B fragments (n-tile mode cut to 2),\n # so the gemm keeps the full-rank form cute.gemm requires.\n acc_h = cute.make_tensor(\n acc_S.iterator + 2 * half * acc_S.layout.stride[2],\n cute.make_layout(\n (acc_S.layout.shape[0], acc_S.layout.shape[1], 2),\n stride=acc_S.layout.stride,\n ),\n )\n tSrK_h = cute.make_tensor(\n tSrK.iterator + 2 * half * tSrK.layout.stride[1],\n cute.make_layout(\n (tSrK.layout.shape[0], 2, tSrK.layout.shape[2]),\n stride=tSrK.layout.stride,\n ),\n )\n for kk8 in cutlass.range_constexpr(self._head_dim // 32):\n for nt in cutlass.range_constexpr(2 * half, 2 * half + 2):\n n_row = 32 * nt + nb_row\n for g in cutlass.range_constexpr(2):\n src = cute.local_tile(\n sK_buf[n_row, None], (2,), (8 * kk8 + 4 * g + m4,)\n )\n cute.autovec_copy(src, kpair)\n if cutlass.const_expr(self._dtype is cutlass.BFloat16):\n lo, hi = _fp8x4_to_bf16x4(kpair_u32[0])\n else:\n lo, hi = _fp8x4_to_f16x4(kpair_u32[0])\n # All four e4m3 of this u32 belong to canonical 16-column\n # group g, so both converted pairs go into mma step\n # 2*kk8 + g: each product lands in the same instruction as\n # the reference schedules, keeping the result bit-identical.\n kk = 2 * kk8 + g\n d0 = cute.crd2idx(((0, 0), nt, kk), tSrK.layout)\n d1 = cute.crd2idx(((0, 1), nt, kk), tSrK.layout)\n tSrK_u32[d0 // 2] = lo\n tSrK_u32[d1 // 2] = hi\n for s in cutlass.range_constexpr(2):\n kk = 2 * kk8 + s\n cute.copy(\n smem_tiled_copy_Q,\n tSsQ[None, None, kk],\n tSrQ_copy_view[None, None, kk],\n )\n cute.gemm(\n tiled_mma,\n acc_h,\n tSrQ[None, None, kk],\n tSrK_h[None, None, kk],\n acc_h,\n )\n\n def _make_sk8_layout(self):\n \"\"\"K smem layout for the raw e4m3 bytes viewed as 16-bit pairs: half\n the width of the converted tile, same swizzle.\"\"\"\n atom = cute.make_composed_layout(\n cute.make_swizzle(3, 3, 3),\n 0,\n cute.make_layout((8, 64), stride=(64, 1)),\n )\n return cute.tile_to_shape(\n atom, (self._n_block_size, self._head_dim // 2), (0, 1)\n )\n\n @cute.jit\n def _gather_packed_q(self, mQ, sQ, q_start, kv_head, seqlen_q, tidx):\n \"\"\"Gather the packed Q tile into swizzled smem, column-permuted to\n match the converted K fragments: within each 32-wide block, column\n ``16g + 4m + 2h + j`` (two-bit ``m``, one-bit rest) moves to slot\n ``16g + 8h + 2m + j``, where ``g = (c8 % 4) // 2``,\n ``m = 2 * (c8 % 2) + i // 2``, and ``h = i % 2`` below. Rows past\n seqlen_q are zero-filled; the epilogue masks them.\"\"\"\n elems = 128 // self._dtype.width\n chunks = self._head_dim // elems\n total = self._m_block_size * chunks\n frag = cute.make_rmem_tensor(cute.make_layout(elems), self._dtype)\n for it in cutlass.range_constexpr(total // self._num_threads):\n e = tidx + it * self._num_threads\n r = e // chunks\n c8 = e % chunks\n local_head = r // self._pack_q_len\n token = r % self._pack_q_len\n head = kv_head * self._qhead_per_kv + local_head\n if cute.elem_less(token, seqlen_q):\n gQ_chunk = cute.local_tile(\n mQ[q_start + token, head, None], (elems,), (c8,)\n )\n frag.store(gQ_chunk.load())\n # Chunk column a = 8*c8 + 2*i + j goes to permuted pair\n # position p2 (see the docstring); pairs stay contiguous.\n for i in cutlass.range_constexpr(4):\n pr = cute.make_tensor(frag.iterator + 2 * i, cute.make_layout(2))\n p2 = (\n 16 * (c8 // 4)\n + 8 * ((c8 % 4) // 2)\n + 4 * (i % 2)\n + 2 * (c8 % 2)\n + i // 2\n )\n dst = cute.local_tile(sQ[r, None], (2,), (p2,))\n cute.autovec_copy(pr, dst)\n else:\n sQ_chunk0 = cute.local_tile(sQ[r, None], (elems,), (c8,))\n sQ_chunk0.fill(0)\n\n\n# `createpolicy.fractional.L2::evict_first.b64` at fraction 1.0: K tiles\n# are read once per CTA, so they should not evict resident lines.\n_TMA_EVICT_FIRST = cutlass.Int64(0x12F0000000000000)\n\n\n@dsl_user_op\ndef _mma_m16n8k16(a: cute.Tensor, b: cute.Tensor, c: cute.Tensor, *, loc=None, ip=None):\n \"\"\"One m16n8k16 f16/bf16 mma.sync with f32 accumulate; a is 4 u32, b is\n 2 u32, c is 4 f32 (read-modify-write).\"\"\"\n ab_ty = \"bf16\" if a.element_type is cutlass.BFloat16 else \"f16\"\n a_u32 = cute.recast_tensor(a, cutlass.Uint32)\n b_u32 = cute.recast_tensor(b, cutlass.Uint32)\n out = llvm.inline_asm(\n llvm.StructType.get_literal([cutlass.Float32.mlir_type] * 4),\n [a_u32[i].ir_value(loc=loc, ip=ip) for i in range(4)]\n + [b_u32[i].ir_value(loc=loc, ip=ip) for i in range(2)]\n + [c[i].ir_value(loc=loc, ip=ip) for i in range(4)],\n f\"mma.sync.aligned.m16n8k16.row.col.f32.{ab_ty}.{ab_ty}.f32 \"\n \"{$0, $1, $2, $3}, {$4, $5, $6, $7}, {$8, $9}, {$10, $11, $12, $13};\",\n \"=f,=f,=f,=f,r,r,r,r,r,r,f,f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n loc=loc,\n ip=ip,\n )\n for i in range(4):\n c[i] = cutlass.Float32(\n llvm.extractvalue(cutlass.Float32.mlir_type, out, [i], loc=loc, ip=ip)\n )\n\n\n@cute.jit\ndef _tma_copy_g2s(atom, gmem, smem, mbar, cache_policy=None):\n \"\"\"One bulk-tensor TMA G2S copy (call without elect_one; the atom elects).\"\"\"\n s_part, g_part = cpasync.tma_partition(\n atom,\n 0,\n cute.make_layout(1),\n cute.group_modes(smem, 0),\n cute.group_modes(gmem, 0),\n )\n cute.copy(atom, g_part, s_part, tma_bar_ptr=mbar, cache_policy=cache_policy)\n\n\nclass MsaProxyScoreDecodeKeyMajorSm12x:\n \"\"\"Key-major packed-decode schedule for small fused-row tiles\n (group_size * pack_q_len <= 32): the score GEMM runs as K Q^T with the\n 128 keys as the MMA M dimension and the fused (head, token) query rows as\n N. Each of the 4 MMA warps owns 32 contiguous keys, so ldmatrix is legal\n on both operands and the Q fragments load once per CTA and stay in\n registers across KV blocks. A fifth warp is a TMA producer feeding a\n two-stage mbarrier pipeline (Q's smem aliases K stage 0), which leaves\n two intra-CTA barriers per block. The low per-CTA fixed cost (no Q\n gather, no fill barriers, no per-step Q reloads) is what wins on the\n one-block-per-CTA grids that split-K produces at small batch.\n \"\"\"\n\n _BLOCK_K = 128\n _BAR_MMA = 1\n _NUM_STAGES = 2\n\n def __init__(\n self,\n head_dim: int = 128,\n group_size: int = 4,\n pack_q_len: int = 4,\n is_causal: bool = True,\n paged: bool = False,\n kv_fp8: bool = False,\n q_fp8: bool = False,\n qoff_default: bool = True,\n ):\n if head_dim != 128:\n raise ValueError(\"only head_dim == 128 is supported\")\n if group_size * pack_q_len > 32:\n raise ValueError(\"group_size * pack_q_len must be <= 32\")\n if q_fp8 and not kv_fp8:\n raise ValueError(\"q_fp8 requires kv_fp8\")\n self._head_dim = head_dim\n self._group = group_size\n self._pack_q_len = pack_q_len\n self._is_causal = is_causal\n self._paged = paged\n self._kv_fp8 = kv_fp8\n self._q_fp8 = q_fp8\n # Right-aligned decode (q_offset=None) computes the causal offset\n # in-kernel, skipping the host-side offset-tensor build kernels that\n # dominate at batch 1.\n self._qoff_default = qoff_default\n self._block_q = group_size * pack_q_len\n self._q_tiles = (self._block_q + 7) // 8\n self._num_threads = 32 * 5\n\n @cute.jit\n def __call__(\n self,\n mQ: cute.Tensor,\n mK: cute.Tensor,\n mPageTable: cute.Tensor,\n mMaxScore: cute.Tensor,\n mCuQ: cute.Tensor,\n mCuK: cute.Tensor,\n mQOffset: cute.Tensor,\n max_seqlen_q: cutlass.Int32,\n batch_size: cutlass.Int32,\n num_qo_heads: cutlass.Int32,\n max_k_tiles: cutlass.Int32,\n num_splits: cutlass.Int32,\n stream: cuda.CUstream,\n ):\n if cutlass.const_expr(\n not (\n mQ.element_type == cutlass.Float16\n or mQ.element_type == cutlass.BFloat16\n )\n ):\n raise TypeError(\"Only Float16 or BFloat16 q is supported\")\n self._dtype: Type[cutlass.Numeric] = mQ.element_type\n\n dtype = self._dtype\n hd = self._head_dim\n pack = self._pack_q_len\n group = self._group\n block_q = self._block_q\n elems = 128 * 8 // dtype.width\n tma_g2s = cpasync.CopyBulkTensorTileG2SOp()\n swizzle_128b = cute.make_swizzle(3, 4, 3)\n\n # fp8 operands arrive as 16-bit views of the e4m3 bytes (half\n # head_dim), so their tiles are half as wide.\n qw = hd // 2 if cutlass.const_expr(self._q_fp8) else hd\n sQ_layout = cute.make_composed_layout(\n swizzle_128b,\n 0,\n cute.make_layout(\n (pack, group, (elems, qw // elems)),\n stride=(elems, pack * elems, (1, block_q * elems)),\n ),\n )\n q_tma = cpasync.make_tiled_tma_atom(\n tma_g2s,\n cute.logical_divide(mQ, (None, None, elems)),\n sQ_layout,\n cta_tiler=(pack, group, qw),\n )\n\n kw = hd // 2 if cutlass.const_expr(self._kv_fp8) else hd\n if cutlass.const_expr(self._paged):\n sK_layout = cute.make_composed_layout(\n swizzle_128b,\n 0,\n cute.make_layout(\n (1, 1, self._BLOCK_K, (elems, kw // elems), self._NUM_STAGES),\n stride=(\n 0,\n 0,\n elems,\n (1, self._BLOCK_K * elems),\n self._BLOCK_K * kw,\n ),\n ),\n )\n k_tma = cpasync.make_tiled_tma_atom(\n tma_g2s,\n cute.logical_divide(mK, (None, None, None, elems)),\n sK_layout,\n cta_tiler=(1, 1, self._BLOCK_K, kw),\n )\n else:\n sK_layout = cute.make_composed_layout(\n swizzle_128b,\n 0,\n cute.make_layout(\n (self._BLOCK_K, 1, (elems, kw // elems), self._NUM_STAGES),\n stride=(\n elems,\n 0,\n (1, self._BLOCK_K * elems),\n self._BLOCK_K * kw,\n ),\n ),\n )\n k_tma = cpasync.make_tiled_tma_atom(\n tma_g2s,\n cute.logical_divide(mK, (None, None, elems)),\n sK_layout,\n cta_tiler=(self._BLOCK_K, 1, kw),\n )\n\n self.kernel(\n q_tma,\n k_tma,\n mPageTable,\n mMaxScore,\n mCuQ,\n mCuK,\n mQOffset,\n max_k_tiles,\n num_splits,\n ).launch(\n grid=(num_splits, batch_size, num_qo_heads // group),\n block=[self._num_threads, 1, 1],\n stream=stream,\n use_pdl=True,\n )\n\n @cute.kernel\n def kernel(\n self,\n q_tma: cpasync.TmaInfo,\n k_tma: cpasync.TmaInfo,\n mPageTable: cute.Tensor,\n mMaxScore: cute.Tensor,\n mCuQ: cute.Tensor,\n mCuK: cute.Tensor,\n mQOffset: cute.Tensor,\n max_k_tiles: cutlass.Int32,\n num_splits: cutlass.Int32,\n ):\n split_idx, batch_idx, kv_head = cute.arch.block_idx()\n warp_id = cute.arch.make_warp_uniform(cute.arch.warp_idx())\n lane_id = cute.arch.lane_idx()\n\n dtype = self._dtype\n hd = self._head_dim\n pack = self._pack_q_len\n group = self._group\n block_q = self._block_q\n block_k = self._BLOCK_K\n num_stages = self._NUM_STAGES\n q_tiles = self._q_tiles\n epi_q = q_tiles * 8\n elems = 128 // dtype.width\n mma_k = 32 * 8 // dtype.width\n\n kw = hd // 2 if self._kv_fp8 else hd\n qw = hd // 2 if self._q_fp8 else hd\n\n smem = cutlass.utils.SmemAllocator()\n sK_full = smem.allocate_tensor(\n dtype,\n k_tma.smem_layout.outer,\n byte_alignment=128,\n swizzle=k_tma.smem_layout.inner,\n )\n if cutlass.const_expr(self._paged):\n sK = sK_full[0, 0, None, None, None]\n else:\n sK = sK_full[None, 0, None, None]\n # Q's smem aliases K stage 0: the Q fragments are register-resident\n # before the first K tile is allowed in (empty-mbarrier order).\n sQ_tma = cute.make_tensor(\n sK[None, None, 0].iterator, layout=q_tma.smem_layout.outer\n )\n q_tma_elems = 128 * 8 // dtype.width\n sQ = cute.coalesce(\n cute.group_modes(sQ_tma, 0, 2),\n target_profile=(block_q, (q_tma_elems, qw // q_tma_elems)),\n )\n epi_buffer = smem.allocate_tensor(cutlass.Float32, cute.make_layout((epi_q, 4)))\n tma_full_mbar = smem.allocate_array(cutlass.Int64, num_stages)\n tma_empty_mbar = smem.allocate_array(cutlass.Int64, num_stages)\n\n n_iter = cute.ceil_div(max_k_tiles, num_splits)\n\n if warp_id == 0:\n with cute.arch.elect_one():\n for i in cutlass.range_constexpr(num_stages):\n cute.arch.mbarrier_init(tma_full_mbar + i, 1)\n cute.arch.mbarrier_init(tma_empty_mbar + i, 128)\n cute.arch.mbarrier_init_fence()\n elif warp_id == 1:\n cpasync.prefetch_descriptor(q_tma.atom)\n cpasync.prefetch_descriptor(k_tma.atom)\n cute.arch.sync_threads()\n\n # PDL: the preceding kernel may still be writing the seqlen tensors,\n # so they are read only after the dependency wait (the setup above is\n # independent of global data and can overlap).\n cute.arch.griddepcontrol_wait()\n cute.arch.griddepcontrol_launch_dependents()\n\n q_start = mCuQ[batch_idx]\n seqlen_q = mCuQ[batch_idx + 1] - q_start\n if cutlass.const_expr(self._paged):\n k_start = cutlass.Int32(0)\n seqlen_k = mCuK[batch_idx]\n else:\n k_start = mCuK[batch_idx]\n seqlen_k = mCuK[batch_idx + 1] - k_start\n num_kv_blocks = cute.ceil_div(seqlen_k, block_k)\n\n if split_idx < num_kv_blocks:\n if warp_id == 4:\n # TMA producer warp: Q once, then one K tile per valid block.\n tma_stage = 0\n tma_parity = 1\n\n gq_tile = cute.local_tile(\n cute.domain_offset((q_start, kv_head * group, 0), q_tma.tma_tensor),\n tiler=(pack, group, qw),\n coord=(0, 0, 0),\n )\n cute.arch.mbarrier_wait(tma_empty_mbar, tma_parity)\n with cute.arch.elect_one():\n q_size = block_q * qw * (dtype.width // 8)\n cute.arch.mbarrier_arrive_and_expect_tx(tma_full_mbar, q_size)\n _tma_copy_g2s(q_tma.atom, gq_tile, sQ_tma, tma_full_mbar)\n\n tma_stage = (tma_stage + 1) % num_stages\n if tma_stage == 0:\n tma_parity ^= 1\n\n for it in cutlass.range(n_iter):\n kv_block = split_idx + it * num_splits\n if kv_block < num_kv_blocks:\n if cutlass.const_expr(self._paged):\n page = mPageTable[batch_idx, kv_block]\n gk_tile = k_tma.tma_tensor[page, kv_head, None, None]\n else:\n gk_tile = cute.local_tile(\n cute.domain_offset(\n (k_start, kv_head, 0), k_tma.tma_tensor\n ),\n tiler=(block_k, 1, kw),\n coord=(kv_block, 0, 0),\n )\n k_mbar = tma_full_mbar + tma_stage\n\n cute.arch.mbarrier_wait(tma_empty_mbar + tma_stage, tma_parity)\n with cute.arch.elect_one():\n k_size = block_k * kw * (dtype.width // 8)\n cute.arch.mbarrier_arrive_and_expect_tx(k_mbar, k_size)\n _tma_copy_g2s(\n k_tma.atom,\n gk_tile,\n sK[None, None, tma_stage],\n k_mbar,\n cache_policy=_TMA_EVICT_FIRST,\n )\n\n tma_stage = (tma_stage + 1) % num_stages\n if tma_stage == 0:\n tma_parity ^= 1\n\n else:\n # MMA warps: each owns 32 contiguous keys across all q rows.\n sK_warp = cute.local_tile(sK, (32, kw, num_stages), (warp_id, 0, 0))\n sQ_ldsm = cute.zipped_divide(sQ, (8, cute.make_layout((elems, 4))))\n sQ_ldsm = sQ_ldsm[(lane_id % 8, (None, lane_id // 8)), None]\n\n ldsm_atom = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(num_matrices=4), dtype\n )\n\n rQ = cute.make_rmem_tensor(\n ((elems // 2, 2), qw // (mma_k * 2), q_tiles), dtype\n )\n rC = cute.make_rmem_tensor((4, 2, q_tiles), cutlass.Float32)\n sK_ldsm = cute.zipped_divide(\n sK_warp, (16, cute.make_layout((elems, 2)), 1)\n )\n sK_ldsm = sK_ldsm[(lane_id % 16, (None, lane_id // 16), 0), None]\n rK = cute.make_rmem_tensor((elems, 2, kw // mma_k), dtype)\n if cutlass.const_expr(self._kv_fp8):\n # ldmatrix on the 16-bit view hands each lane 4 consecutive\n # e4m3 per u32, so splitting each converted u32 into its\n # low and high pair yields the two k16 A-fragments as pure\n # register renames. Q is permuted once below to the same\n # column order.\n rK_u32 = cute.recast_tensor(rK, cutlass.Uint32)\n rK_lo = cute.make_rmem_tensor((elems,), dtype)\n rK_hi = cute.make_rmem_tensor((elems,), dtype)\n rK_lo_u32 = cute.recast_tensor(rK_lo, cutlass.Uint32)\n rK_hi_u32 = cute.recast_tensor(rK_hi, cutlass.Uint32)\n rQp = cute.make_rmem_tensor((4, kw // mma_k, q_tiles, 2), dtype)\n rQp_u32 = cute.recast_tensor(rQp, cutlass.Uint32)\n\n if warp_id == 0:\n cute.arch.mbarrier_wait(tma_full_mbar, 0)\n cute.arch.barrier(barrier_id=self._BAR_MMA, number_of_threads=128)\n for q in cutlass.range_constexpr(q_tiles):\n cute.copy(ldsm_atom, sQ_ldsm[None, (q, None)], rQ[None, None, q])\n cute.arch.mbarrier_arrive(tma_empty_mbar)\n\n if cutlass.const_expr(self._kv_fp8):\n rQ_u32 = cute.recast_tensor(rQ, cutlass.Uint32)\n if cutlass.const_expr(self._q_fp8):\n # Raw e4m3 q gets the same fp8 column order as K from\n # ldmatrix, so the split converts already are the\n # matching B-fragments.\n for g in cutlass.range_constexpr(kw // mma_k):\n for n in cutlass.range_constexpr(q_tiles):\n for j in cutlass.range_constexpr(2):\n if cutlass.const_expr(dtype is cutlass.BFloat16):\n q_lo, q_hi = _fp8x4_to_bf16x4(\n rQ_u32[(j, g % 2), g // 2, n]\n )\n else:\n q_lo, q_hi = _fp8x4_to_f16x4(\n rQ_u32[(j, g % 2), g // 2, n]\n )\n rQp_u32[j, g, n, 0] = q_lo\n rQp_u32[j, g, n, 1] = q_hi\n else:\n # One-time cross-lane permute of the bf16/f16 Q\n # B-fragments into the fp8 K column order: quad\n # position q4 needs columns 4*q4..4*q4+3, which sit as\n # u32 pairs on quad lanes 2*(q4%2) and 2*(q4%2)+1 of\n # the canonical fragments.\n q4 = lane_id % 4\n src_lo = lane_id - q4 + 2 * (q4 % 2)\n sel_mask = cutlass.Uint32(0) - cutlass.Uint32(q4 // 2)\n for g in cutlass.range_constexpr(kw // mma_k):\n for n in cutlass.range_constexpr(q_tiles):\n for h in cutlass.range_constexpr(2):\n src = src_lo + h\n p0 = cute.arch.shuffle_sync(\n rQ_u32[(0, 0), g, n], src\n )\n p1 = cute.arch.shuffle_sync(\n rQ_u32[(1, 0), g, n], src\n )\n p2 = cute.arch.shuffle_sync(\n rQ_u32[(0, 1), g, n], src\n )\n p3 = cute.arch.shuffle_sync(\n rQ_u32[(1, 1), g, n], src\n )\n rQp_u32[0, g, n, h] = p0 ^ ((p0 ^ p1) & sel_mask)\n rQp_u32[1, g, n, h] = p2 ^ ((p2 ^ p3) & sel_mask)\n\n tma_stage = 1 % num_stages\n tma_parity = 0\n if tma_stage == 0:\n tma_parity ^= 1\n\n if cutlass.const_expr(self._is_causal):\n if cutlass.const_expr(self._qoff_default):\n q_off = seqlen_k - seqlen_q\n else:\n q_off = mQOffset[batch_idx]\n else:\n q_off = cutlass.Int32(0)\n\n for it in cutlass.range(n_iter):\n kv_block = split_idx + it * num_splits\n if kv_block < num_kv_blocks:\n rC.fill(0.0)\n\n if warp_id == 0:\n cute.arch.mbarrier_wait(\n tma_full_mbar + tma_stage, tma_parity\n )\n cute.arch.barrier(\n barrier_id=self._BAR_MMA, number_of_threads=128\n )\n\n if cutlass.const_expr(self._kv_fp8):\n # The lower/upper regrouping puts different\n # products in each mma than the bf16 schedule.\n # With e4m3 operands every f32 dot term is exact,\n # so the result still matches dequantized K\n # bit-for-bit.\n for k in cutlass.range_constexpr(kw // mma_k):\n cute.copy(\n ldsm_atom,\n sK_ldsm[None, (None, k, tma_stage)],\n rK[None, None, k],\n )\n for m in cutlass.range_constexpr(2):\n for i in cutlass.range_constexpr(elems // 2):\n if cutlass.const_expr(\n dtype is cutlass.BFloat16\n ):\n lo, hi = _fp8x4_to_bf16x4(rK_u32[i, m, k])\n else:\n lo, hi = _fp8x4_to_f16x4(rK_u32[i, m, k])\n rK_lo_u32[i] = lo\n rK_hi_u32[i] = hi\n for n in cutlass.range_constexpr(q_tiles):\n _mma_m16n8k16(\n rK_lo,\n rQp[None, k, n, 0],\n rC[None, m, n],\n )\n _mma_m16n8k16(\n rK_hi,\n rQp[None, k, n, 1],\n rC[None, m, n],\n )\n else:\n for k in cutlass.range_constexpr(hd // mma_k):\n cute.copy(\n ldsm_atom,\n sK_ldsm[None, (None, k, tma_stage)],\n rK[None, None, k],\n )\n for m in cutlass.range_constexpr(2):\n for n in cutlass.range_constexpr(q_tiles):\n _mma_m16n8k16(\n rK[None, m, k],\n rQ[(None, k % 2), k // 2, n],\n rC[None, m, n],\n )\n\n cute.arch.mbarrier_arrive(tma_empty_mbar + tma_stage)\n\n # Mask keys past the causal limit and the sequence\n # tail (TMA zero-fills out-of-bounds rows).\n k_base = kv_block * block_k + warp_id * 32\n for q in cutlass.range_constexpr(q_tiles):\n for i in cutlass.range_constexpr(4):\n for j in cutlass.range_constexpr(2):\n col = q * 8 + (lane_id % 4) * 2 + j\n token = col % pack\n if cutlass.const_expr(self._is_causal):\n col_limit = cutlass.min(\n token + q_off + 1, seqlen_k\n )\n else:\n col_limit = seqlen_k\n k_pos = k_base + i * 8 + lane_id // 4\n if cute.elem_less(col_limit, k_pos + 1):\n rC[q * 8 + i * 2 + j] = -cutlass.Float32.inf\n\n for q in cutlass.range_constexpr(q_tiles):\n r0 = rC[q * 8 + 0]\n r1 = rC[q * 8 + 1]\n for i in cutlass.range_constexpr(1, 4):\n r0 = cute.arch.fmax(r0, rC[q * 8 + i * 2 + 0])\n r1 = cute.arch.fmax(r1, rC[q * 8 + i * 2 + 1])\n for i in cutlass.range_constexpr(3):\n off = 4 << i\n r0 = cute.arch.fmax(\n r0,\n cute.arch.shuffle_sync_bfly(\n r0, offset=off, mask=-1, mask_and_clamp=31\n ),\n )\n r1 = cute.arch.fmax(\n r1,\n cute.arch.shuffle_sync_bfly(\n r1, offset=off, mask=-1, mask_and_clamp=31\n ),\n )\n if lane_id * 2 < 8:\n epi_buffer[q * 8 + lane_id * 2 + 0, warp_id] = r0\n epi_buffer[q * 8 + lane_id * 2 + 1, warp_id] = r1\n cute.arch.barrier(\n barrier_id=self._BAR_MMA, number_of_threads=128\n )\n\n if warp_id == 0:\n head_local = lane_id // pack\n token_f = lane_id - head_local * pack\n if lane_id < block_q and cute.elem_less(token_f, seqlen_q):\n score = epi_buffer[lane_id, 0]\n for i in cutlass.range_constexpr(1, 4):\n score = cute.arch.fmax(\n score, epi_buffer[lane_id, i]\n )\n mMaxScore[\n kv_head * group + head_local,\n kv_block,\n q_start + token_f,\n ] = score\n\n tma_stage = (tma_stage + 1) % num_stages\n if tma_stage == 0:\n tma_parity ^= 1\n elif kv_block < max_k_tiles:\n # Padding tile in [num_kv_blocks, max_k_tiles) -> -inf.\n if warp_id == 0:\n head_p = lane_id // pack\n token_p = lane_id - head_p * pack\n if lane_id < block_q and cute.elem_less(token_p, seqlen_q):\n mMaxScore[\n kv_head * group + head_p,\n kv_block,\n q_start + token_p,\n ] = -cutlass.Float32.inf\n elif split_idx < max_k_tiles:\n # CTA with no valid block: only padding stores remain.\n if warp_id == 0:\n for it in cutlass.range(n_iter):\n kv_block = split_idx + it * num_splits\n if kv_block < max_k_tiles:\n head_p2 = lane_id // pack\n token_p2 = lane_id - head_p2 * pack\n if lane_id < block_q and cute.elem_less(token_p2, seqlen_q):\n mMaxScore[\n kv_head * group + head_p2,\n kv_block,\n q_start + token_p2,\n ] = -cutlass.Float32.inf\n\n\nclass MsaProxyScoreDecodeStreamSm12x:\n \"\"\"Single-token decode schedule: at one query token the score tile is only\n group_size rows, too skinny for the MMA atom, so K streams straight from\n GMEM to registers (no smem, no tensor cores) and dim-parallel lanes reduce\n each key's dot products with warp shuffles.\n\n Deliberately q_len == 1 only: the shuffle+FMA phase scales with q_len\n while the K loads don't, and that rising arithmetic intensity is exactly\n what starts paying for the tensor cores. MTP stays on the packed-MMA\n schedules.\"\"\"\n\n _NUM_WARPS = 8\n _KEYS_PER_ITER = 2 # 32 lanes = 2 keys x 16 dim-slice lanes\n\n def __init__(\n self,\n head_dim: int = 128,\n group_size: int = 4,\n is_causal: bool = True,\n paged: bool = False,\n kv_fp8: bool = False,\n qoff_default: bool = True,\n ):\n if head_dim != 128:\n raise ValueError(\"only head_dim == 128 is supported\")\n # Q and the running maxes live in registers per lane; past 8 heads the\n # footprint approaches the spill point, so larger groups keep the\n # packed MMA schedule.\n if not 1 <= group_size <= 8:\n raise ValueError(\"group_size must be in [1, 8]\")\n self._head_dim = head_dim\n self._G = group_size\n self._is_causal = is_causal\n self._paged = paged\n self._kv_fp8 = kv_fp8\n # Right-aligned decode (q_offset=None): the single query sits at\n # seqlen_k - 1, so the causal limit is just seqlen_k and no offset\n # tensor is needed.\n self._qoff_default = qoff_default\n self._blk_kv = 128\n self._num_threads = self._NUM_WARPS * 32\n self._keys_per_warp = self._blk_kv // self._NUM_WARPS\n self._num_iters = self._keys_per_warp // self._KEYS_PER_ITER\n\n @cute.jit\n def __call__(\n self,\n mQ: cute.Tensor, # (total_q, Hq, d)\n mK: cute.Tensor, # (total_k, Hkv, d) flat | (pages, Hkv, 128, d) paged\n mPageTable: cute.Tensor, # (B, max_pages) int32 (dummy if flat)\n mMaxScore: cute.Tensor, # (Hq, max_k_tiles, total_q) f32\n mCuQ: cute.Tensor, # (B + 1,) int32 (unused: one q token per request)\n mCuK: cute.Tensor, # (B + 1,) int32\n mQOffset: cute.Tensor, # (B,) int32 causal offset (MSA q_offset)\n max_seqlen_q: cutlass.Int32, # 1 (kept for signature parity)\n batch_size: cutlass.Int32,\n num_qo_heads: cutlass.Int32,\n max_k_tiles: cutlass.Int32,\n num_splits: cutlass.Int32, # unused: the grid is already per KV block\n stream: cuda.CUstream,\n ):\n if cutlass.const_expr(\n not (\n mQ.element_type == cutlass.Float16\n or mQ.element_type == cutlass.BFloat16\n )\n ):\n raise TypeError(\"Only Float16 or BFloat16 q is supported\")\n self._dtype: Type[cutlass.Numeric] = mQ.element_type\n self.kernel(mQ, mK, mPageTable, mMaxScore, mCuK, mQOffset).launch(\n grid=(max_k_tiles, batch_size, num_qo_heads // self._G),\n block=[self._num_threads, 1, 1],\n stream=stream,\n )\n\n @cute.kernel\n def kernel(\n self,\n mQ: cute.Tensor,\n mK: cute.Tensor,\n mPageTable: cute.Tensor,\n mMaxScore: cute.Tensor,\n mCuK: cute.Tensor,\n mQOffset: cute.Tensor,\n ):\n lane = cute.arch.lane_idx()\n warp = cute.arch.warp_idx()\n tile, qi, kv_head = cute.arch.block_idx()\n\n G = self._G\n if cutlass.const_expr(self._paged):\n # mCuK holds per-request lengths on the paged path:\n # page_table supplies every KV address, so there is\n # no base offset to add.\n k_start = cutlass.Int32(0)\n seqlen_k = mCuK[qi]\n else:\n k_start = mCuK[qi]\n seqlen_k = mCuK[qi + 1] - k_start\n if cutlass.const_expr(self._is_causal and not self._qoff_default):\n col_limit = cutlass.min(mQOffset[qi] + 1, seqlen_k)\n else:\n col_limit = seqlen_k\n tile_base = tile * self._blk_kv\n\n lane_key = lane >> 4 # which of the warp's two keys this half-warp owns\n lane_grp = lane & 15 # this lane's 8-dim slice index within its key\n\n mfrag = cute.make_rmem_tensor((G,), cutlass.Float32)\n mfrag.fill(-cutlass.Float32.inf)\n\n # tile/qi are CTA-uniform, so the whole block skips dead tiles together\n # (their output stays -inf) and the shuffles below stay full-warp.\n if tile_base < col_limit:\n qfrags = [\n cute.make_rmem_tensor(cute.make_layout(8), self._dtype)\n for _ in range(G)\n ]\n for g in cutlass.range_constexpr(G):\n q_chunk = cute.local_tile(\n mQ[qi, kv_head * G + g, None], (8,), (lane_grp,)\n )\n cute.autovec_copy(q_chunk, qfrags[g])\n qs = [[cutlass.Float32(qfrags[g][i]) for i in range(8)] for g in range(G)]\n\n if cutlass.const_expr(self._paged):\n page = mPageTable[qi, tile]\n mK_blk = mK[page, kv_head, None, None] # (128, d)\n else:\n mK_h = mK[None, kv_head, None] # (total_k, d)\n\n # Keep this loop separate from the compute loop below: issuing all\n # loads before any consumption is the latency hiding. fp8 K stays\n # e4m3 through the loads (half the DRAM bytes) and upconverts per\n # iteration in the compute loop.\n kfrag = cute.make_rmem_tensor(\n cute.make_layout(self._num_iters * 8), mK.element_type\n )\n for it in cutlass.range_constexpr(self._num_iters):\n off = warp * self._keys_per_warp + it * self._KEYS_PER_ITER + lane_key\n # Tail keys clamp to the tile's first row (always in range for a\n # live tile) so loads stay unpredicated; the max step masks them.\n ld_off = off if tile_base + off < col_limit else 0\n if cutlass.const_expr(self._paged):\n k_row = mK_blk[ld_off, None]\n else:\n k_row = mK_h[k_start + tile_base + ld_off, None]\n k_chunk = cute.local_tile(k_row, (8,), (lane_grp,))\n dst = cute.make_tensor(kfrag.iterator + it * 8, cute.make_layout(8))\n cute.autovec_copy(k_chunk, dst)\n\n for it in cutlass.range_constexpr(self._num_iters):\n if cutlass.const_expr(self._kv_fp8):\n # f16 intermediate (exact for e4m3), packed cvt.\n k8 = cute.make_tensor(kfrag.iterator + it * 8, cute.make_layout(8))\n kf16 = cute.make_rmem_tensor(cute.make_layout(8), cutlass.Float16)\n _cvt_fp8_frag(k8, kf16)\n ks = [cutlass.Float32(kf16[i]) for i in range(8)]\n else:\n ks = [cutlass.Float32(kfrag[it * 8 + i]) for i in range(8)]\n es = [\n qs[g][0] * ks[0]\n + qs[g][1] * ks[1]\n + qs[g][2] * ks[2]\n + qs[g][3] * ks[3]\n + qs[g][4] * ks[4]\n + qs[g][5] * ks[5]\n + qs[g][6] * ks[6]\n + qs[g][7] * ks[7]\n for g in range(G)\n ]\n # Butterfly-add over the 16 dim-slice lanes of this key.\n for s in cutlass.range_constexpr(4):\n off_r = 8 >> s\n es = [\n es[g] + cute.arch.shuffle_sync_bfly(es[g], off_r)\n for g in range(G)\n ]\n pos = (\n tile_base\n + warp * self._keys_per_warp\n + it * self._KEYS_PER_ITER\n + lane_key\n )\n if pos < col_limit:\n for g in cutlass.range_constexpr(G):\n mfrag[g] = cute.arch.fmax(mfrag[g], es[g])\n\n # Max-combine the two half-warps' keys.\n for g in cutlass.range_constexpr(G):\n mfrag[g] = cute.arch.fmax(\n mfrag[g], cute.arch.shuffle_sync_bfly(mfrag[g], 16)\n )\n\n @cute.struct\n class SharedStorage:\n s_max: cute.struct.MemRange[cutlass.Float32, self._NUM_WARPS * G]\n\n smem = cutlass.utils.SmemAllocator()\n storage = smem.allocate(SharedStorage)\n s_max = storage.s_max.get_tensor(\n cute.make_layout((self._NUM_WARPS, G), stride=(G, 1))\n )\n if lane == 0:\n for g in cutlass.range_constexpr(G):\n s_max[warp, g] = mfrag[g]\n cute.arch.sync_threads()\n\n if warp == 0 and lane < G:\n r = s_max[0, lane]\n for w in cutlass.range_constexpr(1, self._NUM_WARPS):\n r = cute.arch.fmax(r, s_max[w, lane])\n mMaxScore[kv_head * G + lane, tile, qi] = r\n"},"after_code":{"kind":"string","value":"\"\"\"\nCopyright (c) 2026 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nMSA dense proxy-score kernels for SM120/SM121: per (head, KV block, query) max\nof the unscaled post-mask QK^T logits; masked blocks yield -inf.\n\"\"\"\n\nfrom typing import Type\n\nimport cuda.bindings.driver as cuda\nimport cutlass\nimport cutlass.cute as cute\nimport cutlass.pipeline as pipeline\nfrom cutlass._mlir.dialects import llvm\nfrom cutlass.cute.nvgpu import cpasync, warp\nfrom cutlass.cutlass_dsl import T, dsl_user_op\n\n\n@dsl_user_op\ndef _fp8x4_to_f16x4(x: cutlass.Uint32, *, loc=None, ip=None):\n out = llvm.inline_asm(\n llvm.StructType.get_literal([T.i32()] * 2),\n [x.ir_value(loc=loc, ip=ip)],\n \"{\\n\\t\"\n \".reg .b16 lo, hi;\\n\\t\"\n \"mov.b32 {lo, hi}, $2;\\n\\t\"\n \"cvt.rn.f16x2.e4m3x2 $0, lo;\\n\\t\"\n \"cvt.rn.f16x2.e4m3x2 $1, hi;\\n\\t\"\n \"}\\n\",\n \"=r,=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n loc=loc,\n ip=ip,\n )\n return (\n cutlass.Uint32(llvm.extractvalue(T.i32(), out, [0], loc=loc, ip=ip)),\n cutlass.Uint32(llvm.extractvalue(T.i32(), out, [1], loc=loc, ip=ip)),\n )\n\n\n@dsl_user_op\ndef _fp8x4_to_bf16x4(x: cutlass.Uint32, *, loc=None, ip=None):\n # There is no e4m3 -> bf16 cvt; round-trip through f16, which is exact\n # (every e4m3 value is representable in both f16 and bf16).\n out = llvm.inline_asm(\n llvm.StructType.get_literal([T.i32()] * 2),\n [x.ir_value(loc=loc, ip=ip)],\n \"{\\n\\t\"\n \".reg .b16 lo, hi, t00, t01, t10, t11;\\n\\t\"\n \"mov.b32 {lo, hi}, $2;\\n\\t\"\n \"cvt.rn.f16x2.e4m3x2 $0, lo;\\n\\t\"\n \"cvt.rn.f16x2.e4m3x2 $1, hi;\\n\\t\"\n \"mov.b32 {t00, t01}, $0;\\n\\t\"\n \"mov.b32 {t10, t11}, $1;\\n\\t\"\n \"cvt.rn.bf16.f16 t00, t00;\\n\\t\"\n \"cvt.rn.bf16.f16 t01, t01;\\n\\t\"\n \"cvt.rn.bf16.f16 t10, t10;\\n\\t\"\n \"cvt.rn.bf16.f16 t11, t11;\\n\\t\"\n \"mov.b32 $0, {t00, t01};\\n\\t\"\n \"mov.b32 $1, {t10, t11};\\n\\t\"\n \"}\\n\",\n \"=r,=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n loc=loc,\n ip=ip,\n )\n return (\n cutlass.Uint32(llvm.extractvalue(T.i32(), out, [0], loc=loc, ip=ip)),\n cutlass.Uint32(llvm.extractvalue(T.i32(), out, [1], loc=loc, ip=ip)),\n )\n\n\n@cute.jit\ndef _cvt_fp8_frag(src: cute.Tensor, dst: cute.Tensor):\n \"\"\"Convert an e4m3 register fragment to dst's f16/bf16 element type with\n packed cvt (one instruction per four elements); element-wise ``.to()``\n lowers to a byte-extract sequence.\"\"\"\n src_u32 = cute.recast_tensor(src, cutlass.Uint32)\n dst_u32 = cute.recast_tensor(dst, cutlass.Uint32)\n for i in cutlass.range_constexpr(cute.size(src.shape) // 4):\n if cutlass.const_expr(dst.element_type is cutlass.BFloat16):\n lo, hi = _fp8x4_to_bf16x4(src_u32[i])\n else:\n lo, hi = _fp8x4_to_f16x4(src_u32[i])\n dst_u32[i * 2] = lo\n dst_u32[i * 2 + 1] = hi\n\n\nclass MsaProxyScoreSm12x:\n \"\"\"General bf16/fp16 proxy schedule (any q length, fp8 K, flat or paged):\n every query head scores against its kv_head's index-K independently.\"\"\"\n\n def __init__(\n self,\n head_dim: int = 128,\n m_block_size: int = 64,\n n_block_size: int = 128,\n num_threads: int = 128,\n is_causal: bool = True,\n paged: bool = False,\n kv_fp8: bool = False,\n ):\n if head_dim != 128 or n_block_size != 128:\n raise ValueError(\"only head_dim == n_block_size == 128 is supported\")\n self._head_dim = head_dim\n self._m_block_size = m_block_size\n self._n_block_size = n_block_size\n self._num_threads = num_threads\n self._is_causal = is_causal\n self._paged = paged\n self._kv_fp8 = kv_fp8\n\n self.cta_sync_barrier = pipeline.NamedBarrier(\n barrier_id=1, num_threads=num_threads\n )\n\n def _make_sk_layout(self):\n \"\"\"K SMEM layout (built in-kernel for region isolation). The fp8\n convert path stores 16B-aligned chunks, so the swizzle works for it\n too; a padded layout would cost a second CTA per SM (48KB -> >50KB).\"\"\"\n atom = cute.make_composed_layout(\n cute.make_swizzle(3, 3, 3),\n 0,\n cute.make_layout((8, 64), stride=(64, 1)),\n )\n return cute.tile_to_shape(atom, (self._n_block_size, self._head_dim), (0, 1))\n\n def _make_sq_layout(self):\n atom = cute.make_composed_layout(\n cute.make_swizzle(3, 3, 3),\n 0,\n cute.make_layout((8, 64), stride=(64, 1)),\n )\n return cute.tile_to_shape(atom, (self._m_block_size, self._head_dim), (0, 1))\n\n @cute.jit\n def __call__(\n self,\n mQ: cute.Tensor, # (total_q, Hq, d)\n mK: cute.Tensor, # (total_k, Hkv, d) flat | (pages, Hkv, 128, d) paged\n mPageTable: cute.Tensor, # (B, max_pages) int32 (dummy (1,1) if flat)\n mMaxScore: cute.Tensor, # (Hq, max_k_tiles, total_q) f32\n mCuQ: cute.Tensor, # (B + 1,) int32\n mCuK: cute.Tensor, # (B + 1,) int32\n mQOffset: cute.Tensor, # (B,) int32 causal offset (MSA q_offset)\n max_seqlen_q: cutlass.Int32,\n batch_size: cutlass.Int32,\n num_qo_heads: cutlass.Int32,\n max_k_tiles: cutlass.Int32,\n num_splits: cutlass.Int32,\n stream: cuda.CUstream,\n ):\n if cutlass.const_expr(\n not (\n mQ.element_type == cutlass.Float16\n or mQ.element_type == cutlass.BFloat16\n )\n ):\n raise TypeError(\"Only Float16 or BFloat16 q is supported\")\n self._dtype: Type[cutlass.Numeric] = mQ.element_type\n\n # Split-K: fold a kv-block split factor into grid x to fill the SMs when the\n # base grid (1, batch, heads) starves at low batch. Output is per-(head,\n # kv_block, query) so splits write disjoint columns, no reduction.\n self.kernel(\n mQ,\n mK,\n mPageTable,\n mMaxScore,\n mCuQ,\n mCuK,\n mQOffset,\n max_k_tiles,\n num_splits,\n ).launch(\n grid=(\n cute.ceil_div(max_seqlen_q, self._m_block_size) * num_splits,\n batch_size,\n num_qo_heads,\n ),\n block=[self._num_threads, 1, 1],\n stream=stream,\n )\n\n @cute.kernel\n def kernel(\n self,\n mQ: cute.Tensor,\n mK: cute.Tensor,\n mPageTable: cute.Tensor,\n mMaxScore: cute.Tensor,\n mCuQ: cute.Tensor,\n mCuK: cute.Tensor,\n mQOffset: cute.Tensor,\n max_k_tiles: cutlass.Int32,\n num_splits: cutlass.Int32,\n ):\n tidx, _, _ = cute.arch.thread_idx()\n bx, batch_idx, qo_head = cute.arch.block_idx()\n # grid x packs (m_block, split): splits of one m_block are adjacent so\n # they share the same Q tile in L2 (only the kv-block subset differs).\n m_block = bx // num_splits\n split_idx = bx % num_splits\n\n q_start = mCuQ[batch_idx]\n seqlen_q = mCuQ[batch_idx + 1] - q_start\n if cutlass.const_expr(self._paged):\n # mCuK holds per-request lengths on the paged path:\n # page_table supplies every KV address, so there is\n # no base offset to add.\n k_start = cutlass.Int32(0)\n seqlen_k = mCuK[batch_idx]\n else:\n k_start = mCuK[batch_idx]\n seqlen_k = mCuK[batch_idx + 1] - k_start\n num_kv_blocks = cute.ceil_div(seqlen_k, self._n_block_size)\n group_size = mQ.shape[1] // mK.shape[1]\n kv_head = qo_head // group_size\n\n if m_block * self._m_block_size < seqlen_q:\n sQ_layout = self._make_sq_layout()\n sK_layout = self._make_sk_layout()\n\n @cute.struct\n class SharedStorage:\n sQ: cute.struct.Align[\n cute.struct.MemRange[self._dtype, cute.cosize(sQ_layout)],\n 1024,\n ]\n sK: cute.struct.Align[\n cute.struct.MemRange[self._dtype, cute.cosize(sK_layout)],\n 1024,\n ]\n\n smem = cutlass.utils.SmemAllocator()\n storage = smem.allocate(SharedStorage)\n sQ = storage.sQ.get_tensor(sQ_layout)\n sK = storage.sK.get_tensor(sK_layout)\n\n # K is in this tiled copy only on the non-fp8 path (fp8 K loads separately)\n universal_copy_bits = 128\n async_copy_elems = universal_copy_bits // self._dtype.width\n atom_async_copy = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n self._dtype,\n num_bits_per_copy=universal_copy_bits,\n )\n t_dim1 = 64 // async_copy_elems\n t_layout = cute.make_layout(\n (self._num_threads // t_dim1, t_dim1), stride=(t_dim1, 1)\n )\n v_layout = cute.make_layout((1, async_copy_elems))\n gmem_tiled_copy = cute.make_tiled_copy_tv(\n atom_async_copy, t_layout, v_layout\n )\n gmem_thr_copy = gmem_tiled_copy.get_slice(tidx)\n\n mQ_h = cute.domain_offset((q_start, 0), mQ[None, qo_head, None])\n gQ = cute.local_tile(\n mQ_h, (self._m_block_size, self._head_dim), (m_block, 0)\n )\n tQgQ = gmem_thr_copy.partition_S(gQ)\n tQsQ = gmem_thr_copy.partition_D(sQ)\n cQ = cute.make_identity_tensor((self._m_block_size, self._head_dim))\n tQcQ = gmem_thr_copy.partition_S(cQ)\n\n for m in cutlass.range_constexpr(cute.size(tQsQ.shape[1])):\n if (m_block * self._m_block_size + tQcQ[0, m, 0][0]) < seqlen_q:\n cute.copy(\n gmem_tiled_copy,\n tQgQ[None, m, None],\n tQsQ[None, m, None],\n )\n else:\n tQsQ[None, m, None].fill(0)\n cute.arch.cp_async_commit_group()\n\n tiled_mma = cute.make_tiled_mma(\n warp.MmaF16BF16Op(self._dtype, cutlass.Float32, (16, 8, 16)),\n (self._num_threads // 32, 1, 1),\n permutation_mnk=(self._num_threads // 32 * 16, 16, 16),\n )\n thr_mma = tiled_mma.get_slice(tidx)\n tSrQ = thr_mma.make_fragment_A(thr_mma.partition_A(sQ))\n tSrK = thr_mma.make_fragment_B(thr_mma.partition_B(sK))\n acc_S = cute.make_rmem_tensor(\n thr_mma.partition_shape_C((self._m_block_size, self._n_block_size)),\n cutlass.Float32,\n )\n\n smem_copy_atom = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(transpose=False, num_matrices=4),\n self._dtype,\n )\n smem_tiled_copy_Q = cute.make_tiled_copy_A(smem_copy_atom, tiled_mma)\n smem_tiled_copy_K = cute.make_tiled_copy_B(smem_copy_atom, tiled_mma)\n smem_thr_copy_Q = smem_tiled_copy_Q.get_slice(tidx)\n smem_thr_copy_K = smem_tiled_copy_K.get_slice(tidx)\n tSsQ = smem_thr_copy_Q.partition_S(sQ)\n tSrQ_copy_view = smem_thr_copy_Q.retile(tSrQ)\n tSsK = smem_thr_copy_K.partition_S(sK)\n tSrK_copy_view = smem_thr_copy_K.retile(tSrK)\n\n cS = cute.make_identity_tensor((self._m_block_size, self._n_block_size))\n tScS_mn = self._make_acc_tensor_mn_view(thr_mma.partition_C(cS))\n acc_S_mn = self._make_acc_tensor_mn_view(acc_S)\n n_rows = cute.size(acc_S_mn.shape[0])\n\n # K gmem views; the block mode is indexed after partitioning so the\n # copy tile shapes stay static.\n if cutlass.const_expr(not self._kv_fp8):\n if cutlass.const_expr(self._paged):\n pass # per-block page lookup happens inside the loop\n else:\n mK_h = cute.domain_offset((k_start, 0), mK[None, kv_head, None])\n gK = cute.local_tile(\n mK_h, (self._n_block_size, self._head_dim), (None, 0)\n )\n tKgK_flat = gmem_thr_copy.partition_S(gK)\n tKsK = gmem_thr_copy.partition_D(sK)\n cKV = cute.make_identity_tensor((self._n_block_size, self._head_dim))\n tKVcKV = gmem_thr_copy.partition_S(cKV)\n\n # sQ is reused across all kv-blocks, so Q fragments load once here\n cute.arch.cp_async_wait_group(0)\n self.cta_sync_barrier.arrive_and_wait()\n for kk in cutlass.range_constexpr(cute.size(tSsQ.shape[2])):\n cute.copy(\n smem_tiled_copy_Q,\n tSsQ[None, None, kk],\n tSrQ_copy_view[None, None, kk],\n )\n\n # Split-K CTAs stride kv_block by num_splits. Causal skip: kv-blocks\n # entirely above the q-tile's causal limit get their -inf written directly,\n # with no K load or MMA (masking after the MMA would waste the work).\n if cutlass.const_expr(self._is_causal):\n causal_last = (\n m_block * self._m_block_size\n + (self._m_block_size - 1)\n + mQOffset[batch_idx]\n ) // self._n_block_size\n last_block = cutlass.min(causal_last, num_kv_blocks - 1)\n else:\n last_block = num_kv_blocks - 1\n\n n_iter = cute.ceil_div(max_k_tiles, num_splits)\n for it in cutlass.range(n_iter):\n kv_block = split_idx + it * num_splits\n if kv_block <= last_block:\n self.cta_sync_barrier.arrive_and_wait()\n if cutlass.const_expr(self._kv_fp8):\n if cutlass.const_expr(self._paged):\n page8 = mPageTable[batch_idx, kv_block]\n mK_h8 = mK[page8, kv_head, None, None]\n row_off8 = cutlass.Int32(0)\n else:\n mK_h8 = cute.domain_offset(\n (k_start, 0), mK[None, kv_head, None]\n )\n row_off8 = kv_block * self._n_block_size\n chunks_per_row = self._head_dim // 8\n total_chunks = self._n_block_size * chunks_per_row\n cvt_frag = cute.make_rmem_tensor(\n cute.make_layout(8), self._dtype\n )\n for kv_it in cutlass.range_constexpr(\n total_chunks // self._num_threads\n ):\n kv_chunk = tidx + kv_it * self._num_threads\n kv_m = kv_chunk // chunks_per_row\n kv_c8 = kv_chunk % chunks_per_row\n sK_chunk = cute.local_tile(sK[kv_m, None], (8,), (kv_c8,))\n if (kv_block * self._n_block_size + kv_m) < seqlen_k:\n gKc = cute.local_tile(\n mK_h8[row_off8 + kv_m, None], (8,), (kv_c8,)\n )\n cvt_frag.store(\n gKc.load()\n .to(cutlass.Float16)\n .to(cutlass.Float32)\n .to(self._dtype)\n )\n else:\n cvt_frag.fill(0)\n cute.autovec_copy(cvt_frag, sK_chunk)\n else:\n # Branch bodies keep their own tensor names: aliasing an outer\n # tensor in this dynamic loop would make it loop-carried.\n if cutlass.const_expr(self._paged):\n page = mPageTable[batch_idx, kv_block]\n gK_pg = cute.local_tile(\n mK[page, kv_head, None, None],\n (self._n_block_size, self._head_dim),\n (None, 0),\n )\n tKgK_pg = gmem_thr_copy.partition_S(gK_pg)\n for n in cutlass.range_constexpr(cute.size(tKsK.shape[1])):\n if (\n kv_block * self._n_block_size + tKVcKV[0, n, 0][0]\n ) < seqlen_k:\n cute.copy(\n gmem_tiled_copy,\n tKgK_pg[None, n, None, 0],\n tKsK[None, n, None],\n )\n else:\n tKsK[None, n, None].fill(0)\n else:\n for n in cutlass.range_constexpr(cute.size(tKsK.shape[1])):\n if (\n kv_block * self._n_block_size + tKVcKV[0, n, 0][0]\n ) < seqlen_k:\n cute.copy(\n gmem_tiled_copy,\n tKgK_flat[None, n, None, kv_block],\n tKsK[None, n, None],\n )\n else:\n tKsK[None, n, None].fill(0)\n cute.arch.cp_async_commit_group()\n cute.arch.cp_async_wait_group(0)\n self.cta_sync_barrier.arrive_and_wait()\n\n # S = Q K^T (unscaled)\n acc_S.fill(0.0)\n for kk in cutlass.range_constexpr(cute.size(tSsK.shape[2])):\n cute.copy(\n smem_tiled_copy_K,\n tSsK[None, None, kk],\n tSrK_copy_view[None, None, kk],\n )\n for kk in cutlass.range_constexpr(cute.size(tSsK.shape[2])):\n cute.gemm(\n tiled_mma,\n acc_S,\n tSrQ[None, None, kk],\n tSrK[None, None, kk],\n acc_S,\n )\n\n for r in cutlass.range_constexpr(n_rows):\n row_local = tScS_mn[r, 0][0]\n q_loc = m_block * self._m_block_size + row_local\n if cutlass.const_expr(self._is_causal):\n col_limit = cutlass.min(\n q_loc + mQOffset[batch_idx] + 1, seqlen_k\n )\n else:\n col_limit = seqlen_k\n for c in cutlass.range_constexpr(cute.size(tScS_mn.shape[1])):\n k_pos = kv_block * self._n_block_size + tScS_mn[0, c][1]\n if cute.elem_less(col_limit, k_pos + 1):\n acc_S_mn[r, c] = -cutlass.Float32.inf\n tile_max = (\n acc_S_mn[r, None]\n .load()\n .reduce(cute.ReductionOp.MAX, -cutlass.Float32.inf, 0)\n )\n tile_max = self._threadquad_reduce_max(tile_max)\n if q_loc < seqlen_q:\n # All 4 quad threads hold the same value; the\n # duplicate stores are idempotent.\n mMaxScore[qo_head, kv_block, q_start + q_loc] = tile_max\n elif kv_block < max_k_tiles:\n # Blocks past last_block (causally future or padding) get -inf, no\n # MMA. Bounded by max_k_tiles so split-K overshoot writes nothing.\n for r in cutlass.range_constexpr(n_rows):\n row_local2 = tScS_mn[r, 0][0]\n q_loc2 = m_block * self._m_block_size + row_local2\n if q_loc2 < seqlen_q:\n mMaxScore[\n qo_head, kv_block, q_start + q_loc2\n ] = -cutlass.Float32.inf\n\n @cute.jit\n def _threadquad_reduce_max(self, val):\n val = cute.arch.fmax(\n val,\n cute.arch.shuffle_sync_bfly(val, offset=2, mask=-1, mask_and_clamp=31),\n )\n val = cute.arch.fmax(\n val,\n cute.arch.shuffle_sync_bfly(val, offset=1, mask=-1, mask_and_clamp=31),\n )\n return val\n\n def _make_acc_tensor_mn_view(self, acc: cute.Tensor) -> cute.Tensor:\n acc_layout_col_major = cute.make_layout(acc.layout.shape)\n acc_layout_mn = cute.make_layout(\n (\n (acc_layout_col_major.shape[0][1], acc_layout_col_major.shape[1]),\n (acc_layout_col_major.shape[0][0], acc_layout_col_major.shape[2]),\n ),\n stride=(\n (acc_layout_col_major.stride[0][1], acc_layout_col_major.stride[1]),\n (acc_layout_col_major.stride[0][0], acc_layout_col_major.stride[2]),\n ),\n )\n acc_layout_mn = cute.composition(acc.layout, acc_layout_mn)\n return cute.make_tensor(acc.iterator, acc_layout_mn)\n\n\nclass MsaProxyScoreDecodePackedSm12x(MsaProxyScoreSm12x):\n \"\"\"Head-fused packed-decode bf16/fp16 schedule: packs qhead_per_kv heads x\n pack_q_len tokens into the M rows so the shared index-K is read once per\n kv_head. fp8 K takes the key-split subclass instead.\"\"\"\n\n def __init__(\n self,\n head_dim: int = 128,\n m_block_size: int = 64,\n n_block_size: int = 128,\n num_threads: int = 128,\n is_causal: bool = True,\n paged: bool = False,\n kv_fp8: bool = False,\n qhead_per_kv: int = 4,\n pack_q_len: int = 16,\n qoff_default: bool = False,\n ):\n super().__init__(\n head_dim=head_dim,\n m_block_size=m_block_size,\n n_block_size=n_block_size,\n num_threads=num_threads,\n is_causal=is_causal,\n paged=paged,\n kv_fp8=kv_fp8,\n )\n if qhead_per_kv * pack_q_len != m_block_size:\n raise ValueError(\n f\"qhead_per_kv * pack_q_len must equal the {m_block_size}-row MMA \"\n f\"tile, got {qhead_per_kv} x {pack_q_len}\"\n )\n # These attrs are constexpr-baked into the gather/epilogue, so each\n # factorization compiles to its own kernel.\n self._qhead_per_kv = qhead_per_kv\n self._pack_q_len = pack_q_len\n # True: right-aligned decode; the causal offset is computed in-kernel.\n self._qoff_default = qoff_default\n\n @cute.jit\n def __call__(\n self,\n mQ: cute.Tensor,\n mK: cute.Tensor,\n mPageTable: cute.Tensor,\n mMaxScore: cute.Tensor,\n mCuQ: cute.Tensor,\n mCuK: cute.Tensor,\n mQOffset: cute.Tensor,\n max_seqlen_q: cutlass.Int32,\n batch_size: cutlass.Int32,\n num_qo_heads: cutlass.Int32,\n max_k_tiles: cutlass.Int32,\n num_splits: cutlass.Int32,\n stream: cuda.CUstream,\n ):\n if cutlass.const_expr(\n not (\n mQ.element_type == cutlass.Float16\n or mQ.element_type == cutlass.BFloat16\n )\n ):\n raise TypeError(\"Only Float16 or BFloat16 q is supported\")\n self._dtype: Type[cutlass.Numeric] = mQ.element_type\n\n # One CTA per (split, batch, kv_head): all qhead_per_kv heads of a kv_head\n # are packed into the single m_block_size-row tile, so the index-K is read\n # once per kv_head (qhead_per_kv x less K traffic than the per-head schedule).\n self.kernel(\n mQ,\n mK,\n mPageTable,\n mMaxScore,\n mCuQ,\n mCuK,\n mQOffset,\n max_k_tiles,\n num_splits,\n ).launch(\n grid=(\n num_splits,\n batch_size,\n num_qo_heads // self._qhead_per_kv,\n ),\n block=[self._num_threads, 1, 1],\n stream=stream,\n )\n\n @cute.kernel\n def kernel(\n self,\n mQ: cute.Tensor,\n mK: cute.Tensor,\n mPageTable: cute.Tensor,\n mMaxScore: cute.Tensor,\n mCuQ: cute.Tensor,\n mCuK: cute.Tensor,\n mQOffset: cute.Tensor,\n max_k_tiles: cutlass.Int32,\n num_splits: cutlass.Int32,\n ):\n tidx, _, _ = cute.arch.thread_idx()\n split_idx, batch_idx, kv_head = cute.arch.block_idx()\n\n q_start = mCuQ[batch_idx]\n seqlen_q = mCuQ[batch_idx + 1] - q_start\n if cutlass.const_expr(self._paged):\n # mCuK holds per-request lengths on the paged path:\n # page_table supplies every KV address, so there is\n # no base offset to add.\n k_start = cutlass.Int32(0)\n seqlen_k = mCuK[batch_idx]\n else:\n k_start = mCuK[batch_idx]\n seqlen_k = mCuK[batch_idx + 1] - k_start\n num_kv_blocks = cute.ceil_div(seqlen_k, self._n_block_size)\n q_off = cutlass.Int32(0)\n if cutlass.const_expr(self._is_causal):\n if cutlass.const_expr(self._qoff_default):\n q_off = seqlen_k - seqlen_q\n else:\n q_off = mQOffset[batch_idx]\n\n sQ_layout = self._make_sq_layout()\n sK_layout = self._make_sk_layout()\n\n @cute.struct\n class SharedStorage:\n sQ: cute.struct.Align[\n cute.struct.MemRange[self._dtype, cute.cosize(sQ_layout)],\n 1024,\n ]\n sK: cute.struct.Align[\n cute.struct.MemRange[self._dtype, cute.cosize(sK_layout)],\n 1024,\n ]\n\n smem = cutlass.utils.SmemAllocator()\n storage = smem.allocate(SharedStorage)\n sQ = storage.sQ.get_tensor(sQ_layout)\n sK = storage.sK.get_tensor(sK_layout)\n\n # Tiled copy covers K only; Q is gathered per-head below\n universal_copy_bits = 128\n async_copy_elems = universal_copy_bits // self._dtype.width\n atom_async_copy = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n self._dtype,\n num_bits_per_copy=universal_copy_bits,\n )\n t_dim1 = 64 // async_copy_elems\n t_layout = cute.make_layout(\n (self._num_threads // t_dim1, t_dim1), stride=(t_dim1, 1)\n )\n v_layout = cute.make_layout((1, async_copy_elems))\n gmem_tiled_copy = cute.make_tiled_copy_tv(atom_async_copy, t_layout, v_layout)\n gmem_thr_copy = gmem_tiled_copy.get_slice(tidx)\n\n self._gather_packed_q(mQ, sQ, q_start, kv_head, seqlen_q, tidx)\n\n tiled_mma = cute.make_tiled_mma(\n warp.MmaF16BF16Op(self._dtype, cutlass.Float32, (16, 8, 16)),\n (self._num_threads // 32, 1, 1),\n permutation_mnk=(self._num_threads // 32 * 16, 16, 16),\n )\n thr_mma = tiled_mma.get_slice(tidx)\n tSrQ = thr_mma.make_fragment_A(thr_mma.partition_A(sQ))\n tSrK = thr_mma.make_fragment_B(thr_mma.partition_B(sK))\n acc_S = cute.make_rmem_tensor(\n thr_mma.partition_shape_C((self._m_block_size, self._n_block_size)),\n cutlass.Float32,\n )\n\n smem_copy_atom = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(transpose=False, num_matrices=4),\n self._dtype,\n )\n smem_tiled_copy_Q = cute.make_tiled_copy_A(smem_copy_atom, tiled_mma)\n smem_tiled_copy_K = cute.make_tiled_copy_B(smem_copy_atom, tiled_mma)\n smem_thr_copy_Q = smem_tiled_copy_Q.get_slice(tidx)\n smem_thr_copy_K = smem_tiled_copy_K.get_slice(tidx)\n tSsQ = smem_thr_copy_Q.partition_S(sQ)\n tSrQ_copy_view = smem_thr_copy_Q.retile(tSrQ)\n tSsK = smem_thr_copy_K.partition_S(sK)\n tSrK_copy_view = smem_thr_copy_K.retile(tSrK)\n\n cS = cute.make_identity_tensor((self._m_block_size, self._n_block_size))\n tScS_mn = self._make_acc_tensor_mn_view(thr_mma.partition_C(cS))\n acc_S_mn = self._make_acc_tensor_mn_view(acc_S)\n n_rows = cute.size(acc_S_mn.shape[0])\n\n # K gmem views, as in the general kernel.\n if cutlass.const_expr(self._paged):\n pass # per-block page lookup happens inside the loop\n else:\n mK_h = cute.domain_offset((k_start, 0), mK[None, kv_head, None])\n gK = cute.local_tile(mK_h, (self._n_block_size, self._head_dim), (None, 0))\n tKgK_flat = gmem_thr_copy.partition_S(gK)\n tKsK = gmem_thr_copy.partition_D(sK)\n cKV = cute.make_identity_tensor((self._n_block_size, self._head_dim))\n tKVcKV = gmem_thr_copy.partition_S(cKV)\n\n # Gather stores are synchronous; order them before the Q fragment reads,\n # then preload the Q fragments once (sQ reused across all kv-blocks).\n self.cta_sync_barrier.arrive_and_wait()\n for kk in cutlass.range_constexpr(cute.size(tSsQ.shape[2])):\n cute.copy(\n smem_tiled_copy_Q,\n tSsQ[None, None, kk],\n tSrQ_copy_view[None, None, kk],\n )\n\n # Split-K CTAs stride kv_block by num_splits, as in the general kernel.\n # No causal skip here: packed decode attends every kv-block and masks\n # the per-token causal tail in the epilogue.\n n_iter = cute.ceil_div(max_k_tiles, num_splits)\n for it in cutlass.range(n_iter):\n kv_block = split_idx + it * num_splits\n if kv_block < num_kv_blocks:\n self.cta_sync_barrier.arrive_and_wait()\n if cutlass.const_expr(self._paged):\n page = mPageTable[batch_idx, kv_block]\n gK_pg = cute.local_tile(\n mK[page, kv_head, None, None],\n (self._n_block_size, self._head_dim),\n (None, 0),\n )\n tKgK_pg = gmem_thr_copy.partition_S(gK_pg)\n for n in cutlass.range_constexpr(cute.size(tKsK.shape[1])):\n if (\n kv_block * self._n_block_size + tKVcKV[0, n, 0][0]\n ) < seqlen_k:\n cute.copy(\n gmem_tiled_copy,\n tKgK_pg[None, n, None, 0],\n tKsK[None, n, None],\n )\n else:\n tKsK[None, n, None].fill(0)\n else:\n for n in cutlass.range_constexpr(cute.size(tKsK.shape[1])):\n if (\n kv_block * self._n_block_size + tKVcKV[0, n, 0][0]\n ) < seqlen_k:\n cute.copy(\n gmem_tiled_copy,\n tKgK_flat[None, n, None, kv_block],\n tKsK[None, n, None],\n )\n else:\n tKsK[None, n, None].fill(0)\n cute.arch.cp_async_commit_group()\n cute.arch.cp_async_wait_group(0)\n self.cta_sync_barrier.arrive_and_wait()\n\n # S = Q K^T (unscaled)\n acc_S.fill(0.0)\n for kk in cutlass.range_constexpr(cute.size(tSsK.shape[2])):\n cute.copy(\n smem_tiled_copy_K,\n tSsK[None, None, kk],\n tSrK_copy_view[None, None, kk],\n )\n for kk in cutlass.range_constexpr(cute.size(tSsK.shape[2])):\n cute.gemm(\n tiled_mma,\n acc_S,\n tSrQ[None, None, kk],\n tSrK[None, None, kk],\n acc_S,\n )\n\n # A packed row maps to (local_head, token); a packed query's causal\n # position is its token index (the decode q within this step).\n for r in cutlass.range_constexpr(n_rows):\n row = tScS_mn[r, 0][0]\n token = row % self._pack_q_len\n if cutlass.const_expr(self._is_causal):\n col_limit = cutlass.min(token + q_off + 1, seqlen_k)\n else:\n col_limit = seqlen_k\n for c in cutlass.range_constexpr(cute.size(tScS_mn.shape[1])):\n k_pos = kv_block * self._n_block_size + tScS_mn[0, c][1]\n if cute.elem_less(col_limit, k_pos + 1):\n acc_S_mn[r, c] = -cutlass.Float32.inf\n tile_max = (\n acc_S_mn[r, None]\n .load()\n .reduce(cute.ReductionOp.MAX, -cutlass.Float32.inf, 0)\n )\n tile_max = self._threadquad_reduce_max(tile_max)\n local_head = row // self._pack_q_len\n head = kv_head * self._qhead_per_kv + local_head\n if cute.elem_less(token, seqlen_q):\n # All 4 quad threads hold the same value; the duplicate\n # stores are idempotent.\n mMaxScore[head, kv_block, q_start + token] = tile_max\n elif kv_block < max_k_tiles:\n # Padding tile in [num_kv_blocks, max_k_tiles) -> -inf. Bounded by\n # max_k_tiles because split-K can stride kv_block past the last\n # output column (those overshoot blocks write nothing).\n for r in cutlass.range_constexpr(n_rows):\n row2 = tScS_mn[r, 0][0]\n token2 = row2 % self._pack_q_len\n local_head2 = row2 // self._pack_q_len\n head2 = kv_head * self._qhead_per_kv + local_head2\n if cute.elem_less(token2, seqlen_q):\n mMaxScore[\n head2, kv_block, q_start + token2\n ] = -cutlass.Float32.inf\n\n @cute.jit\n def _gather_packed_q(self, mQ, sQ, q_start, kv_head, seqlen_q, tidx):\n \"\"\"Gather the packed Q tile into swizzled smem; rows past seqlen_q are\n zero-filled (epilogue masks them).\"\"\"\n elems = 128 // self._dtype.width\n chunks = self._head_dim // elems\n total = self._m_block_size * chunks\n frag = cute.make_rmem_tensor(cute.make_layout(elems), self._dtype)\n for it in cutlass.range_constexpr(total // self._num_threads):\n e = tidx + it * self._num_threads\n r = e // chunks\n c8 = e % chunks\n local_head = r // self._pack_q_len\n token = r % self._pack_q_len\n head = kv_head * self._qhead_per_kv + local_head\n sQ_chunk = cute.local_tile(sQ[r, None], (elems,), (c8,))\n if cute.elem_less(token, seqlen_q):\n gQ_chunk = cute.local_tile(\n mQ[q_start + token, head, None], (elems,), (c8,)\n )\n frag.store(gQ_chunk.load())\n cute.autovec_copy(frag, sQ_chunk)\n else:\n sQ_chunk.fill(0)\n\n\nclass MsaProxyScoreDecodePackedFp8Sm12x(MsaProxyScoreDecodePackedSm12x):\n \"\"\"fp8-K packed-decode schedule. Same head-fused M rows as the packed\n schedule, but warps split over keys instead of query rows, so the\n e4m3 -> f16/bf16 upconvert runs once per K element instead of once per\n warp. K stays raw e4m3 through cp.async\n and smem, arriving as a 16-bit view with half the head dim (see\n msa_proxy_score), and upconverts in registers between the smem loads and\n the mma. Q is stored column-permuted to match the converted K fragments\n (see _gather_packed_q).\n\n K staging is pipelined at two granularities because split-K often leaves\n a CTA a single KV block: two smem buffers with a one-block prefetch\n overlap across blocks, and each fill commits as two 64-key cp.async\n groups so the mma starts on the first half while the second is still in\n flight.\n \"\"\"\n\n @cute.kernel\n def kernel(\n self,\n mQ: cute.Tensor,\n mK: cute.Tensor,\n mPageTable: cute.Tensor,\n mMaxScore: cute.Tensor,\n mCuQ: cute.Tensor,\n mCuK: cute.Tensor,\n mQOffset: cute.Tensor,\n max_k_tiles: cutlass.Int32,\n num_splits: cutlass.Int32,\n ):\n tidx, _, _ = cute.arch.thread_idx()\n split_idx, batch_idx, kv_head = cute.arch.block_idx()\n\n q_start = mCuQ[batch_idx]\n seqlen_q = mCuQ[batch_idx + 1] - q_start\n if cutlass.const_expr(self._paged):\n # mCuK holds per-request lengths on the paged path:\n # page_table supplies every KV address, so there is\n # no base offset to add.\n k_start = cutlass.Int32(0)\n seqlen_k = mCuK[batch_idx]\n else:\n k_start = mCuK[batch_idx]\n seqlen_k = mCuK[batch_idx + 1] - k_start\n num_kv_blocks = cute.ceil_div(seqlen_k, self._n_block_size)\n q_off = cutlass.Int32(0)\n if cutlass.const_expr(self._is_causal):\n if cutlass.const_expr(self._qoff_default):\n q_off = seqlen_k - seqlen_q\n else:\n q_off = mQOffset[batch_idx]\n\n sQ_layout = self._make_sq_layout()\n sK_layout = self._make_sk8_layout()\n\n @cute.struct\n class SharedStorage:\n sQ: cute.struct.Align[\n cute.struct.MemRange[self._dtype, cute.cosize(sQ_layout)],\n 1024,\n ]\n sK0: cute.struct.Align[\n cute.struct.MemRange[self._dtype, cute.cosize(sK_layout)],\n 1024,\n ]\n sK1: cute.struct.Align[\n cute.struct.MemRange[self._dtype, cute.cosize(sK_layout)],\n 1024,\n ]\n # Epilogue staging cannot alias K here: with the prefetch both K\n # buffers stay live across the epilogue window.\n sMax: cute.struct.Align[\n cute.struct.MemRange[cutlass.Float32, 4 * self._m_block_size],\n 16,\n ]\n\n smem = cutlass.utils.SmemAllocator()\n storage = smem.allocate(SharedStorage)\n sQ = storage.sQ.get_tensor(sQ_layout)\n sK0 = storage.sK0.get_tensor(sK_layout)\n sK1 = storage.sK1.get_tensor(sK_layout)\n # Full-width layout on the same pointer: shapes the mma B fragment\n # only, no accesses go through it.\n sK_frag_ref = cute.make_tensor(sK0.iterator, self._make_sk_layout())\n sMax = storage.sMax.get_tensor(cute.make_layout(4 * self._m_block_size))\n\n universal_copy_bits = 128\n async_copy_elems = universal_copy_bits // self._dtype.width\n atom_async_copy = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n self._dtype,\n num_bits_per_copy=universal_copy_bits,\n )\n t_dim1 = 64 // async_copy_elems\n t_layout = cute.make_layout(\n (self._num_threads // t_dim1, t_dim1), stride=(t_dim1, 1)\n )\n v_layout = cute.make_layout((1, async_copy_elems))\n gmem_tiled_copy = cute.make_tiled_copy_tv(atom_async_copy, t_layout, v_layout)\n gmem_thr_copy = gmem_tiled_copy.get_slice(tidx)\n\n # First block's K fill goes out before the synchronous Q gather so the\n # cp.async flight time hides under it.\n if split_idx < num_kv_blocks:\n self._fill_k8_tile(\n gmem_tiled_copy,\n gmem_thr_copy,\n mK,\n mPageTable,\n batch_idx,\n kv_head,\n k_start,\n split_idx,\n seqlen_k,\n sK0,\n )\n\n self._gather_packed_q(mQ, sQ, q_start, kv_head, seqlen_q, tidx)\n\n # Warps side by side along N: each owns interleaved 8-column slices\n # of the 128 keys (32 columns total), so the fp8 K fragments are\n # converted once instead of replicated across the M-split warps.\n num_warps = self._num_threads // 32\n tiled_mma = cute.make_tiled_mma(\n warp.MmaF16BF16Op(self._dtype, cutlass.Float32, (16, 8, 16)),\n (1, num_warps, 1),\n permutation_mnk=(16, num_warps * 8, 16),\n )\n thr_mma = tiled_mma.get_slice(tidx)\n tSrQ = thr_mma.make_fragment_A(thr_mma.partition_A(sQ))\n tSrK = thr_mma.make_fragment_B(thr_mma.partition_B(sK_frag_ref))\n acc_S = cute.make_rmem_tensor(\n thr_mma.partition_shape_C((self._m_block_size, self._n_block_size)),\n cutlass.Float32,\n )\n\n smem_copy_atom_Q = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(transpose=False, num_matrices=4),\n self._dtype,\n )\n smem_tiled_copy_Q = cute.make_tiled_copy_A(smem_copy_atom_Q, tiled_mma)\n smem_thr_copy_Q = smem_tiled_copy_Q.get_slice(tidx)\n tSsQ = smem_thr_copy_Q.partition_S(sQ)\n tSrQ_copy_view = smem_thr_copy_Q.retile(tSrQ)\n\n # B loads are plain 4B reads, not ldmatrix: a warp's slice per\n # (n-tile, k-step pair) is only 8 rows x 16B, which the ldmatrix tiled\n # copies cannot partition. The convert splits each 4-byte pair into\n # the even/odd mma k-steps; the resulting K-axis column permutation is\n # mirrored by the Q gather, so Q K^T is unchanged.\n kpair = cute.make_rmem_tensor(cute.make_layout(2), self._dtype)\n kpair_u32 = cute.recast_tensor(kpair, cutlass.Uint32)\n tSrK_u32 = cute.recast_tensor(\n cute.make_tensor(tSrK.iterator, cute.make_layout(cute.cosize(tSrK.layout))),\n cutlass.Uint32,\n )\n warp_idx = tidx // 32\n\n cS = cute.make_identity_tensor((self._m_block_size, self._n_block_size))\n tScS_mn = self._make_acc_tensor_mn_view(thr_mma.partition_C(cS))\n acc_S_mn = self._make_acc_tensor_mn_view(acc_S)\n n_rows = cute.size(acc_S_mn.shape[0])\n\n # Gather stores are synchronous; order them before the Q fragment\n # reads. Q fragments load per k-step inside the block loop, since a\n # full-tile preload would cost a CTA of occupancy.\n self.cta_sync_barrier.arrive_and_wait()\n\n # Buffer selection is a pointer pick rather than cloned fill/consume\n # bodies: small-batch grids run one cold-I-cache CTA per SM, where the\n # duplicated code costs more than it saves.\n base0 = sK0.iterator.toint()\n buf_step = sK1.iterator.toint() - base0\n\n n_iter = cute.ceil_div(max_k_tiles, num_splits)\n for it in cutlass.range(n_iter):\n kv_block = split_idx + it * num_splits\n if kv_block < num_kv_blocks:\n par = it % 2\n sK_cur = cute.make_tensor(\n cute.make_ptr(\n self._dtype,\n base0 + par * buf_step,\n cute.AddressSpace.smem,\n assumed_align=1024,\n ),\n sK_layout,\n )\n sK_nxt = cute.make_tensor(\n cute.make_ptr(\n self._dtype,\n base0 + (1 - par) * buf_step,\n cute.AddressSpace.smem,\n assumed_align=1024,\n ),\n sK_layout,\n )\n # Prefetch the next block into the idle buffer; its loads fly\n # under this block's mma and epilogue. Two commit groups go\n # out either way (empty ones at the tail), which keeps the\n # wait_group counts below static.\n nxt_block = kv_block + num_splits\n if nxt_block < num_kv_blocks:\n self._fill_k8_tile(\n gmem_tiled_copy,\n gmem_thr_copy,\n mK,\n mPageTable,\n batch_idx,\n kv_head,\n k_start,\n nxt_block,\n seqlen_k,\n sK_nxt,\n )\n else:\n cute.arch.cp_async_commit_group()\n cute.arch.cp_async_commit_group()\n\n # S = Q K^T (unscaled), consumed one 64-key half behind each\n # fill group so the mma starts before the tile finishes\n # landing.\n acc_S.fill(0.0)\n for h in cutlass.range_constexpr(2):\n cute.arch.cp_async_wait_group(3 - h)\n self.cta_sync_barrier.arrive_and_wait()\n self._consume_k8_half(\n h,\n sK_cur,\n smem_tiled_copy_Q,\n tSsQ,\n tSrQ,\n tSrQ_copy_view,\n tiled_mma,\n tSrK,\n tSrK_u32,\n kpair,\n kpair_u32,\n acc_S,\n )\n\n # Every warp's K fragment loads must land before the next\n # iteration's prefetch overwrites this buffer.\n self.cta_sync_barrier.arrive_and_wait()\n\n # Per-warp row maxes over the warp's 32 key columns, staged to\n # smem; one thread per row then joins the 4 warps and stores.\n for r in cutlass.range_constexpr(n_rows):\n row = tScS_mn[r, 0][0]\n token = row % self._pack_q_len\n if cutlass.const_expr(self._is_causal):\n col_limit = cutlass.min(token + q_off + 1, seqlen_k)\n else:\n col_limit = seqlen_k\n for c in cutlass.range_constexpr(cute.size(tScS_mn.shape[1])):\n k_pos = kv_block * self._n_block_size + tScS_mn[0, c][1]\n if cute.elem_less(col_limit, k_pos + 1):\n acc_S_mn[r, c] = -cutlass.Float32.inf\n tile_max = (\n acc_S_mn[r, None]\n .load()\n .reduce(cute.ReductionOp.MAX, -cutlass.Float32.inf, 0)\n )\n tile_max = self._threadquad_reduce_max(tile_max)\n if tidx % 4 == 0:\n sMax[row * 4 + warp_idx] = tile_max\n self.cta_sync_barrier.arrive_and_wait()\n if tidx < self._m_block_size:\n row_max = sMax[tidx * 4]\n for w in cutlass.range_constexpr(1, 4):\n row_max = cute.arch.fmax(row_max, sMax[tidx * 4 + w])\n token_f = tidx % self._pack_q_len\n head_f = kv_head * self._qhead_per_kv + tidx // self._pack_q_len\n if cute.elem_less(token_f, seqlen_q):\n mMaxScore[head_f, kv_block, q_start + token_f] = row_max\n elif kv_block < max_k_tiles:\n # Padding tile in [num_kv_blocks, max_k_tiles) -> -inf, as in\n # the packed kernel.\n for r in cutlass.range_constexpr(n_rows):\n row2 = tScS_mn[r, 0][0]\n token2 = row2 % self._pack_q_len\n local_head2 = row2 // self._pack_q_len\n head2 = kv_head * self._qhead_per_kv + local_head2\n if cute.elem_less(token2, seqlen_q):\n mMaxScore[\n head2, kv_block, q_start + token2\n ] = -cutlass.Float32.inf\n\n @cute.jit\n def _fill_k8_tile(\n self,\n gmem_tiled_copy,\n gmem_thr_copy,\n mK: cute.Tensor,\n mPageTable: cute.Tensor,\n batch_idx: cutlass.Int32,\n kv_head: cutlass.Int32,\n k_start: cutlass.Int32,\n kv_block: cutlass.Int32,\n seqlen_k: cutlass.Int32,\n sK_buf: cute.Tensor,\n ):\n \"\"\"Issue one raw-e4m3 K tile's cp.async fill as two commit groups\n (keys 0-63 and 64-127), matching the consumer's half order.\"\"\"\n kw = self._head_dim // 2\n tKsK = gmem_thr_copy.partition_D(sK_buf)\n cKV = cute.make_identity_tensor((self._n_block_size, kw))\n tKVcKV = gmem_thr_copy.partition_S(cKV)\n if cutlass.const_expr(self._paged):\n page = mPageTable[batch_idx, kv_block]\n gK = cute.local_tile(\n mK[page, kv_head, None, None], (self._n_block_size, kw), (None, 0)\n )\n tKgK = gmem_thr_copy.partition_S(gK)[None, None, None, 0]\n else:\n mK_h = cute.domain_offset((k_start, 0), mK[None, kv_head, None])\n gK = cute.local_tile(mK_h, (self._n_block_size, kw), (None, 0))\n tKgK = gmem_thr_copy.partition_S(gK)[None, None, None, kv_block]\n n_passes = cute.size(tKsK.shape[1])\n for n in cutlass.range_constexpr(n_passes):\n if (kv_block * self._n_block_size + tKVcKV[0, n, 0][0]) < seqlen_k:\n cute.copy(gmem_tiled_copy, tKgK[None, n, None], tKsK[None, n, None])\n else:\n tKsK[None, n, None].fill(0)\n if n == n_passes // 2 - 1:\n cute.arch.cp_async_commit_group()\n cute.arch.cp_async_commit_group()\n\n @cute.jit\n def _consume_k8_half(\n self,\n half: cutlass.Constexpr,\n sK_buf: cute.Tensor,\n smem_tiled_copy_Q,\n tSsQ: cute.Tensor,\n tSrQ: cute.Tensor,\n tSrQ_copy_view: cute.Tensor,\n tiled_mma,\n tSrK: cute.Tensor,\n tSrK_u32: cute.Tensor,\n kpair: cute.Tensor,\n kpair_u32: cute.Tensor,\n acc_S: cute.Tensor,\n ):\n \"\"\"Convert-and-mma over one 64-key half (n-tiles ``2*half`` and\n ``2*half + 1``). Q fragments load just in time so ptxas keeps the\n per-thread A footprint at one k-step.\"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n # Fragment geometry of the m16n8k16 B atom: lane covers key row\n # n = 32*nt + 8*warp + lane//4 and k16 pairs at 2*(lane%4) (+8).\n nb_row = 8 * (tidx // 32) + (tidx % 32) // 4\n m4 = tidx % 4\n # This half's slice of the acc and B fragments (n-tile mode cut to 2),\n # so the gemm keeps the full-rank form cute.gemm requires.\n acc_h = cute.make_tensor(\n acc_S.iterator + 2 * half * acc_S.layout.stride[2],\n cute.make_layout(\n (acc_S.layout.shape[0], acc_S.layout.shape[1], 2),\n stride=acc_S.layout.stride,\n ),\n )\n tSrK_h = cute.make_tensor(\n tSrK.iterator + 2 * half * tSrK.layout.stride[1],\n cute.make_layout(\n (tSrK.layout.shape[0], 2, tSrK.layout.shape[2]),\n stride=tSrK.layout.stride,\n ),\n )\n for kk8 in cutlass.range_constexpr(self._head_dim // 32):\n for nt in cutlass.range_constexpr(2 * half, 2 * half + 2):\n n_row = 32 * nt + nb_row\n for g in cutlass.range_constexpr(2):\n src = cute.local_tile(\n sK_buf[n_row, None], (2,), (8 * kk8 + 4 * g + m4,)\n )\n cute.autovec_copy(src, kpair)\n if cutlass.const_expr(self._dtype is cutlass.BFloat16):\n lo, hi = _fp8x4_to_bf16x4(kpair_u32[0])\n else:\n lo, hi = _fp8x4_to_f16x4(kpair_u32[0])\n # All four e4m3 of this u32 belong to canonical 16-column\n # group g, so both converted pairs go into mma step\n # 2*kk8 + g: each product lands in the same instruction as\n # the reference schedules, keeping the result bit-identical.\n kk = 2 * kk8 + g\n d0 = cute.crd2idx(((0, 0), nt, kk), tSrK.layout)\n d1 = cute.crd2idx(((0, 1), nt, kk), tSrK.layout)\n tSrK_u32[d0 // 2] = lo\n tSrK_u32[d1 // 2] = hi\n for s in cutlass.range_constexpr(2):\n kk = 2 * kk8 + s\n cute.copy(\n smem_tiled_copy_Q,\n tSsQ[None, None, kk],\n tSrQ_copy_view[None, None, kk],\n )\n cute.gemm(\n tiled_mma,\n acc_h,\n tSrQ[None, None, kk],\n tSrK_h[None, None, kk],\n acc_h,\n )\n\n def _make_sk8_layout(self):\n \"\"\"K smem layout for the raw e4m3 bytes viewed as 16-bit pairs: half\n the width of the converted tile, same swizzle.\"\"\"\n atom = cute.make_composed_layout(\n cute.make_swizzle(3, 3, 3),\n 0,\n cute.make_layout((8, 64), stride=(64, 1)),\n )\n return cute.tile_to_shape(\n atom, (self._n_block_size, self._head_dim // 2), (0, 1)\n )\n\n @cute.jit\n def _gather_packed_q(self, mQ, sQ, q_start, kv_head, seqlen_q, tidx):\n \"\"\"Gather the packed Q tile into swizzled smem, column-permuted to\n match the converted K fragments: within each 32-wide block, column\n ``16g + 4m + 2h + j`` (two-bit ``m``, one-bit rest) moves to slot\n ``16g + 8h + 2m + j``, where ``g = (c8 % 4) // 2``,\n ``m = 2 * (c8 % 2) + i // 2``, and ``h = i % 2`` below. Rows past\n seqlen_q are zero-filled; the epilogue masks them.\"\"\"\n elems = 128 // self._dtype.width\n chunks = self._head_dim // elems\n total = self._m_block_size * chunks\n frag = cute.make_rmem_tensor(cute.make_layout(elems), self._dtype)\n for it in cutlass.range_constexpr(total // self._num_threads):\n e = tidx + it * self._num_threads\n r = e // chunks\n c8 = e % chunks\n local_head = r // self._pack_q_len\n token = r % self._pack_q_len\n head = kv_head * self._qhead_per_kv + local_head\n if cute.elem_less(token, seqlen_q):\n gQ_chunk = cute.local_tile(\n mQ[q_start + token, head, None], (elems,), (c8,)\n )\n frag.store(gQ_chunk.load())\n # Chunk column a = 8*c8 + 2*i + j goes to permuted pair\n # position p2 (see the docstring); pairs stay contiguous.\n for i in cutlass.range_constexpr(4):\n pr = cute.make_tensor(frag.iterator + 2 * i, cute.make_layout(2))\n p2 = (\n 16 * (c8 // 4)\n + 8 * ((c8 % 4) // 2)\n + 4 * (i % 2)\n + 2 * (c8 % 2)\n + i // 2\n )\n dst = cute.local_tile(sQ[r, None], (2,), (p2,))\n cute.autovec_copy(pr, dst)\n else:\n sQ_chunk0 = cute.local_tile(sQ[r, None], (elems,), (c8,))\n sQ_chunk0.fill(0)\n\n\n# `createpolicy.fractional.L2::evict_first.b64` at fraction 1.0: K tiles\n# are read once per CTA, so they should not evict resident lines.\n_TMA_EVICT_FIRST = cutlass.Int64(0x12F0000000000000)\n\n\n@dsl_user_op\ndef _mma_m16n8k16(a: cute.Tensor, b: cute.Tensor, c: cute.Tensor, *, loc=None, ip=None):\n \"\"\"One m16n8k16 f16/bf16 mma.sync with f32 accumulate; a is 4 u32, b is\n 2 u32, c is 4 f32 (read-modify-write).\"\"\"\n ab_ty = \"bf16\" if a.element_type is cutlass.BFloat16 else \"f16\"\n a_u32 = cute.recast_tensor(a, cutlass.Uint32)\n b_u32 = cute.recast_tensor(b, cutlass.Uint32)\n out = llvm.inline_asm(\n llvm.StructType.get_literal([cutlass.Float32.mlir_type] * 4),\n [a_u32[i].ir_value(loc=loc, ip=ip) for i in range(4)]\n + [b_u32[i].ir_value(loc=loc, ip=ip) for i in range(2)]\n + [c[i].ir_value(loc=loc, ip=ip) for i in range(4)],\n f\"mma.sync.aligned.m16n8k16.row.col.f32.{ab_ty}.{ab_ty}.f32 \"\n \"{$0, $1, $2, $3}, {$4, $5, $6, $7}, {$8, $9}, {$10, $11, $12, $13};\",\n \"=f,=f,=f,=f,r,r,r,r,r,r,f,f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n loc=loc,\n ip=ip,\n )\n for i in range(4):\n c[i] = cutlass.Float32(\n llvm.extractvalue(cutlass.Float32.mlir_type, out, [i], loc=loc, ip=ip)\n )\n\n\n@cute.jit\ndef _tma_copy_g2s(atom, gmem, smem, mbar, cache_policy=None):\n \"\"\"One bulk-tensor TMA G2S copy (call without elect_one; the atom elects).\"\"\"\n s_part, g_part = cpasync.tma_partition(\n atom,\n 0,\n cute.make_layout(1),\n cute.group_modes(smem, 0),\n cute.group_modes(gmem, 0),\n )\n cute.copy(atom, g_part, s_part, tma_bar_ptr=mbar, cache_policy=cache_policy)\n\n\nclass MsaProxyScoreDecodeKeyMajorSm12x:\n \"\"\"Key-major packed-decode schedule for small fused-row tiles\n (group_size * pack_q_len <= 32): the score GEMM runs as K Q^T with the\n 128 keys as the MMA M dimension and the fused (head, token) query rows as\n N. Each of the 4 MMA warps owns 32 contiguous keys, so ldmatrix is legal\n on both operands and the Q fragments load once per CTA and stay in\n registers across KV blocks. A fifth warp is a TMA producer feeding a\n two-stage mbarrier pipeline (Q's smem aliases K stage 0), which leaves\n two intra-CTA barriers per block. The low per-CTA fixed cost (no Q\n gather, no fill barriers, no per-step Q reloads) is what wins on the\n one-block-per-CTA grids that split-K produces at small batch.\n \"\"\"\n\n _BLOCK_K = 128\n _BAR_MMA = 1\n _NUM_STAGES = 2\n\n def __init__(\n self,\n head_dim: int = 128,\n group_size: int = 4,\n pack_q_len: int = 4,\n is_causal: bool = True,\n paged: bool = False,\n kv_fp8: bool = False,\n q_fp8: bool = False,\n qoff_default: bool = True,\n ):\n if head_dim != 128:\n raise ValueError(\"only head_dim == 128 is supported\")\n if group_size * pack_q_len > 32:\n raise ValueError(\"group_size * pack_q_len must be <= 32\")\n if q_fp8 and not kv_fp8:\n raise ValueError(\"q_fp8 requires kv_fp8\")\n self._head_dim = head_dim\n self._group = group_size\n self._pack_q_len = pack_q_len\n self._is_causal = is_causal\n self._paged = paged\n self._kv_fp8 = kv_fp8\n self._q_fp8 = q_fp8\n # Right-aligned decode (q_offset=None) computes the causal offset\n # in-kernel, skipping the host-side offset-tensor build kernels that\n # dominate at batch 1.\n self._qoff_default = qoff_default\n self._block_q = group_size * pack_q_len\n self._q_tiles = (self._block_q + 7) // 8\n self._num_threads = 32 * 5\n\n @cute.jit\n def __call__(\n self,\n mQ: cute.Tensor,\n mK: cute.Tensor,\n mPageTable: cute.Tensor,\n mMaxScore: cute.Tensor,\n mCuQ: cute.Tensor,\n mCuK: cute.Tensor,\n mQOffset: cute.Tensor,\n max_seqlen_q: cutlass.Int32,\n batch_size: cutlass.Int32,\n num_qo_heads: cutlass.Int32,\n max_k_tiles: cutlass.Int32,\n num_splits: cutlass.Int32,\n stream: cuda.CUstream,\n ):\n if cutlass.const_expr(\n not (\n mQ.element_type == cutlass.Float16\n or mQ.element_type == cutlass.BFloat16\n )\n ):\n raise TypeError(\"Only Float16 or BFloat16 q is supported\")\n self._dtype: Type[cutlass.Numeric] = mQ.element_type\n\n dtype = self._dtype\n hd = self._head_dim\n pack = self._pack_q_len\n group = self._group\n block_q = self._block_q\n elems = 128 * 8 // dtype.width\n tma_g2s = cpasync.CopyBulkTensorTileG2SOp()\n swizzle_128b = cute.make_swizzle(3, 4, 3)\n\n # fp8 operands arrive as 16-bit views of the e4m3 bytes (half\n # head_dim), so their tiles are half as wide.\n qw = hd // 2 if cutlass.const_expr(self._q_fp8) else hd\n sQ_layout = cute.make_composed_layout(\n swizzle_128b,\n 0,\n cute.make_layout(\n (pack, group, (elems, qw // elems)),\n stride=(elems, pack * elems, (1, block_q * elems)),\n ),\n )\n q_tma = cpasync.make_tiled_tma_atom(\n tma_g2s,\n cute.logical_divide(mQ, (None, None, elems)),\n sQ_layout,\n cta_tiler=(pack, group, qw),\n )\n\n kw = hd // 2 if cutlass.const_expr(self._kv_fp8) else hd\n if cutlass.const_expr(self._paged):\n sK_layout = cute.make_composed_layout(\n swizzle_128b,\n 0,\n cute.make_layout(\n (1, 1, self._BLOCK_K, (elems, kw // elems), self._NUM_STAGES),\n stride=(\n 0,\n 0,\n elems,\n (1, self._BLOCK_K * elems),\n self._BLOCK_K * kw,\n ),\n ),\n )\n k_tma = cpasync.make_tiled_tma_atom(\n tma_g2s,\n cute.logical_divide(mK, (None, None, None, elems)),\n sK_layout,\n cta_tiler=(1, 1, self._BLOCK_K, kw),\n )\n else:\n sK_layout = cute.make_composed_layout(\n swizzle_128b,\n 0,\n cute.make_layout(\n (self._BLOCK_K, 1, (elems, kw // elems), self._NUM_STAGES),\n stride=(\n elems,\n 0,\n (1, self._BLOCK_K * elems),\n self._BLOCK_K * kw,\n ),\n ),\n )\n k_tma = cpasync.make_tiled_tma_atom(\n tma_g2s,\n cute.logical_divide(mK, (None, None, elems)),\n sK_layout,\n cta_tiler=(self._BLOCK_K, 1, kw),\n )\n\n self.kernel(\n q_tma,\n k_tma,\n mPageTable,\n mMaxScore,\n mCuQ,\n mCuK,\n mQOffset,\n max_k_tiles,\n num_splits,\n ).launch(\n grid=(num_splits, batch_size, num_qo_heads // group),\n block=[self._num_threads, 1, 1],\n stream=stream,\n use_pdl=True,\n )\n\n @cute.kernel\n def kernel(\n self,\n q_tma: cpasync.TmaInfo,\n k_tma: cpasync.TmaInfo,\n mPageTable: cute.Tensor,\n mMaxScore: cute.Tensor,\n mCuQ: cute.Tensor,\n mCuK: cute.Tensor,\n mQOffset: cute.Tensor,\n max_k_tiles: cutlass.Int32,\n num_splits: cutlass.Int32,\n ):\n split_idx, batch_idx, kv_head = cute.arch.block_idx()\n warp_id = cute.arch.make_warp_uniform(cute.arch.warp_idx())\n lane_id = cute.arch.lane_idx()\n\n dtype = self._dtype\n hd = self._head_dim\n pack = self._pack_q_len\n group = self._group\n block_q = self._block_q\n block_k = self._BLOCK_K\n num_stages = self._NUM_STAGES\n q_tiles = self._q_tiles\n epi_q = q_tiles * 8\n elems = 128 // dtype.width\n mma_k = 32 * 8 // dtype.width\n\n kw = hd // 2 if self._kv_fp8 else hd\n qw = hd // 2 if self._q_fp8 else hd\n\n smem = cutlass.utils.SmemAllocator()\n sK_full = smem.allocate_tensor(\n dtype,\n k_tma.smem_layout.outer,\n byte_alignment=128,\n swizzle=k_tma.smem_layout.inner,\n )\n if cutlass.const_expr(self._paged):\n sK = sK_full[0, 0, None, None, None]\n else:\n sK = sK_full[None, 0, None, None]\n # Q's smem aliases K stage 0: the Q fragments are register-resident\n # before the first K tile is allowed in (empty-mbarrier order).\n sQ_tma = cute.make_tensor(\n sK[None, None, 0].iterator, layout=q_tma.smem_layout.outer\n )\n q_tma_elems = 128 * 8 // dtype.width\n sQ = cute.coalesce(\n cute.group_modes(sQ_tma, 0, 2),\n target_profile=(block_q, (q_tma_elems, qw // q_tma_elems)),\n )\n epi_buffer = smem.allocate_tensor(cutlass.Float32, cute.make_layout((epi_q, 4)))\n tma_full_mbar = smem.allocate_array(cutlass.Int64, num_stages)\n tma_empty_mbar = smem.allocate_array(cutlass.Int64, num_stages)\n\n n_iter = cute.ceil_div(max_k_tiles, num_splits)\n\n if warp_id == 0:\n with cute.arch.elect_one():\n for i in cutlass.range_constexpr(num_stages):\n cute.arch.mbarrier_init(tma_full_mbar + i, 1)\n cute.arch.mbarrier_init(tma_empty_mbar + i, 128)\n cute.arch.mbarrier_init_fence()\n elif warp_id == 1:\n cpasync.prefetch_descriptor(q_tma.atom)\n cpasync.prefetch_descriptor(k_tma.atom)\n cute.arch.sync_threads()\n\n # PDL: the preceding kernel may still be writing the seqlen tensors,\n # so they are read only after the dependency wait (the setup above is\n # independent of global data and can overlap).\n cute.arch.griddepcontrol_wait()\n cute.arch.griddepcontrol_launch_dependents()\n\n q_start = mCuQ[batch_idx]\n seqlen_q = mCuQ[batch_idx + 1] - q_start\n if cutlass.const_expr(self._paged):\n k_start = cutlass.Int32(0)\n seqlen_k = mCuK[batch_idx]\n else:\n k_start = mCuK[batch_idx]\n seqlen_k = mCuK[batch_idx + 1] - k_start\n num_kv_blocks = cute.ceil_div(seqlen_k, block_k)\n\n if split_idx < num_kv_blocks:\n if warp_id == 4:\n # TMA producer warp: Q once, then one K tile per valid block.\n tma_stage = 0\n tma_parity = 1\n\n gq_tile = cute.local_tile(\n cute.domain_offset((q_start, kv_head * group, 0), q_tma.tma_tensor),\n tiler=(pack, group, qw),\n coord=(0, 0, 0),\n )\n cute.arch.mbarrier_wait(tma_empty_mbar, tma_parity)\n with cute.arch.elect_one():\n q_size = block_q * qw * (dtype.width // 8)\n cute.arch.mbarrier_arrive_and_expect_tx(tma_full_mbar, q_size)\n _tma_copy_g2s(q_tma.atom, gq_tile, sQ_tma, tma_full_mbar)\n\n tma_stage = (tma_stage + 1) % num_stages\n if tma_stage == 0:\n tma_parity ^= 1\n\n for it in cutlass.range(n_iter):\n kv_block = split_idx + it * num_splits\n if kv_block < num_kv_blocks:\n if cutlass.const_expr(self._paged):\n page = mPageTable[batch_idx, kv_block]\n gk_tile = k_tma.tma_tensor[page, kv_head, None, None]\n else:\n gk_tile = cute.local_tile(\n cute.domain_offset(\n (k_start, kv_head, 0), k_tma.tma_tensor\n ),\n tiler=(block_k, 1, kw),\n coord=(kv_block, 0, 0),\n )\n k_mbar = tma_full_mbar + tma_stage\n\n cute.arch.mbarrier_wait(tma_empty_mbar + tma_stage, tma_parity)\n with cute.arch.elect_one():\n k_size = block_k * kw * (dtype.width // 8)\n cute.arch.mbarrier_arrive_and_expect_tx(k_mbar, k_size)\n _tma_copy_g2s(\n k_tma.atom,\n gk_tile,\n sK[None, None, tma_stage],\n k_mbar,\n cache_policy=_TMA_EVICT_FIRST,\n )\n\n tma_stage = (tma_stage + 1) % num_stages\n if tma_stage == 0:\n tma_parity ^= 1\n\n else:\n # MMA warps: each owns 32 contiguous keys across all q rows.\n sK_warp = cute.local_tile(sK, (32, kw, num_stages), (warp_id, 0, 0))\n sQ_ldsm = cute.zipped_divide(sQ, (8, cute.make_layout((elems, 4))))\n sQ_ldsm = sQ_ldsm[(lane_id % 8, (None, lane_id // 8)), None]\n\n ldsm_atom = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(num_matrices=4), dtype\n )\n\n rQ = cute.make_rmem_tensor(\n ((elems // 2, 2), qw // (mma_k * 2), q_tiles), dtype\n )\n rC = cute.make_rmem_tensor((4, 2, q_tiles), cutlass.Float32)\n sK_ldsm = cute.zipped_divide(\n sK_warp, (16, cute.make_layout((elems, 2)), 1)\n )\n sK_ldsm = sK_ldsm[(lane_id % 16, (None, lane_id // 16), 0), None]\n rK = cute.make_rmem_tensor((elems, 2, kw // mma_k), dtype)\n if cutlass.const_expr(self._kv_fp8):\n # ldmatrix on the 16-bit view hands each lane 4 consecutive\n # e4m3 per u32, so splitting each converted u32 into its\n # low and high pair yields the two k16 A-fragments as pure\n # register renames. Q is permuted once below to the same\n # column order.\n rK_u32 = cute.recast_tensor(rK, cutlass.Uint32)\n rK_lo = cute.make_rmem_tensor((elems,), dtype)\n rK_hi = cute.make_rmem_tensor((elems,), dtype)\n rK_lo_u32 = cute.recast_tensor(rK_lo, cutlass.Uint32)\n rK_hi_u32 = cute.recast_tensor(rK_hi, cutlass.Uint32)\n rQp = cute.make_rmem_tensor((4, kw // mma_k, q_tiles, 2), dtype)\n rQp_u32 = cute.recast_tensor(rQp, cutlass.Uint32)\n\n if warp_id == 0:\n cute.arch.mbarrier_wait(tma_full_mbar, 0)\n cute.arch.barrier(barrier_id=self._BAR_MMA, number_of_threads=128)\n for q in cutlass.range_constexpr(q_tiles):\n cute.copy(ldsm_atom, sQ_ldsm[None, (q, None)], rQ[None, None, q])\n cute.arch.mbarrier_arrive(tma_empty_mbar)\n\n if cutlass.const_expr(self._kv_fp8):\n rQ_u32 = cute.recast_tensor(rQ, cutlass.Uint32)\n if cutlass.const_expr(self._q_fp8):\n # Raw e4m3 q gets the same fp8 column order as K from\n # ldmatrix, so the split converts already are the\n # matching B-fragments.\n for g in cutlass.range_constexpr(kw // mma_k):\n for n in cutlass.range_constexpr(q_tiles):\n for j in cutlass.range_constexpr(2):\n if cutlass.const_expr(dtype is cutlass.BFloat16):\n q_lo, q_hi = _fp8x4_to_bf16x4(\n rQ_u32[(j, g % 2), g // 2, n]\n )\n else:\n q_lo, q_hi = _fp8x4_to_f16x4(\n rQ_u32[(j, g % 2), g // 2, n]\n )\n rQp_u32[j, g, n, 0] = q_lo\n rQp_u32[j, g, n, 1] = q_hi\n else:\n # One-time cross-lane permute of the bf16/f16 Q\n # B-fragments into the fp8 K column order: quad\n # position q4 needs columns 4*q4..4*q4+3, which sit as\n # u32 pairs on quad lanes 2*(q4%2) and 2*(q4%2)+1 of\n # the canonical fragments.\n q4 = lane_id % 4\n src_lo = lane_id - q4 + 2 * (q4 % 2)\n sel_mask = cutlass.Uint32(0) - cutlass.Uint32(q4 // 2)\n for g in cutlass.range_constexpr(kw // mma_k):\n for n in cutlass.range_constexpr(q_tiles):\n for h in cutlass.range_constexpr(2):\n src = src_lo + h\n p0 = cute.arch.shuffle_sync(\n rQ_u32[(0, 0), g, n], src\n )\n p1 = cute.arch.shuffle_sync(\n rQ_u32[(1, 0), g, n], src\n )\n p2 = cute.arch.shuffle_sync(\n rQ_u32[(0, 1), g, n], src\n )\n p3 = cute.arch.shuffle_sync(\n rQ_u32[(1, 1), g, n], src\n )\n rQp_u32[0, g, n, h] = p0 ^ ((p0 ^ p1) & sel_mask)\n rQp_u32[1, g, n, h] = p2 ^ ((p2 ^ p3) & sel_mask)\n\n tma_stage = 1 % num_stages\n tma_parity = 0\n if tma_stage == 0:\n tma_parity ^= 1\n\n if cutlass.const_expr(self._is_causal):\n if cutlass.const_expr(self._qoff_default):\n q_off = seqlen_k - seqlen_q\n else:\n q_off = mQOffset[batch_idx]\n else:\n q_off = cutlass.Int32(0)\n\n for it in cutlass.range(n_iter):\n kv_block = split_idx + it * num_splits\n if kv_block < num_kv_blocks:\n rC.fill(0.0)\n\n if warp_id == 0:\n cute.arch.mbarrier_wait(\n tma_full_mbar + tma_stage, tma_parity\n )\n cute.arch.barrier(\n barrier_id=self._BAR_MMA, number_of_threads=128\n )\n\n if cutlass.const_expr(self._kv_fp8):\n # The lower/upper regrouping puts different\n # products in each mma than the bf16 schedule.\n # With e4m3 operands every f32 dot term is exact,\n # so the result still matches dequantized K\n # bit-for-bit.\n for k in cutlass.range_constexpr(kw // mma_k):\n cute.copy(\n ldsm_atom,\n sK_ldsm[None, (None, k, tma_stage)],\n rK[None, None, k],\n )\n for m in cutlass.range_constexpr(2):\n for i in cutlass.range_constexpr(elems // 2):\n if cutlass.const_expr(\n dtype is cutlass.BFloat16\n ):\n lo, hi = _fp8x4_to_bf16x4(rK_u32[i, m, k])\n else:\n lo, hi = _fp8x4_to_f16x4(rK_u32[i, m, k])\n rK_lo_u32[i] = lo\n rK_hi_u32[i] = hi\n for n in cutlass.range_constexpr(q_tiles):\n _mma_m16n8k16(\n rK_lo,\n rQp[None, k, n, 0],\n rC[None, m, n],\n )\n _mma_m16n8k16(\n rK_hi,\n rQp[None, k, n, 1],\n rC[None, m, n],\n )\n else:\n for k in cutlass.range_constexpr(hd // mma_k):\n cute.copy(\n ldsm_atom,\n sK_ldsm[None, (None, k, tma_stage)],\n rK[None, None, k],\n )\n for m in cutlass.range_constexpr(2):\n for n in cutlass.range_constexpr(q_tiles):\n _mma_m16n8k16(\n rK[None, m, k],\n rQ[(None, k % 2), k // 2, n],\n rC[None, m, n],\n )\n\n cute.arch.mbarrier_arrive(tma_empty_mbar + tma_stage)\n\n # Mask keys past the causal limit and the sequence\n # tail (TMA zero-fills out-of-bounds rows).\n k_base = kv_block * block_k + warp_id * 32\n for q in cutlass.range_constexpr(q_tiles):\n for i in cutlass.range_constexpr(4):\n for j in cutlass.range_constexpr(2):\n col = q * 8 + (lane_id % 4) * 2 + j\n token = col % pack\n if cutlass.const_expr(self._is_causal):\n col_limit = cutlass.min(\n token + q_off + 1, seqlen_k\n )\n else:\n col_limit = seqlen_k\n k_pos = k_base + i * 8 + lane_id // 4\n if cute.elem_less(col_limit, k_pos + 1):\n rC[q * 8 + i * 2 + j] = -cutlass.Float32.inf\n\n for q in cutlass.range_constexpr(q_tiles):\n r0 = rC[q * 8 + 0]\n r1 = rC[q * 8 + 1]\n for i in cutlass.range_constexpr(1, 4):\n r0 = cute.arch.fmax(r0, rC[q * 8 + i * 2 + 0])\n r1 = cute.arch.fmax(r1, rC[q * 8 + i * 2 + 1])\n for i in cutlass.range_constexpr(3):\n off = 4 << i\n r0 = cute.arch.fmax(\n r0,\n cute.arch.shuffle_sync_bfly(\n r0, offset=off, mask=-1, mask_and_clamp=31\n ),\n )\n r1 = cute.arch.fmax(\n r1,\n cute.arch.shuffle_sync_bfly(\n r1, offset=off, mask=-1, mask_and_clamp=31\n ),\n )\n if lane_id * 2 < 8:\n epi_buffer[q * 8 + lane_id * 2 + 0, warp_id] = r0\n epi_buffer[q * 8 + lane_id * 2 + 1, warp_id] = r1\n cute.arch.barrier(\n barrier_id=self._BAR_MMA, number_of_threads=128\n )\n\n if warp_id == 0:\n head_local = lane_id // pack\n token_f = lane_id - head_local * pack\n if lane_id < block_q and cute.elem_less(token_f, seqlen_q):\n score = epi_buffer[lane_id, 0]\n for i in cutlass.range_constexpr(1, 4):\n score = cute.arch.fmax(\n score, epi_buffer[lane_id, i]\n )\n mMaxScore[\n kv_head * group + head_local,\n kv_block,\n q_start + token_f,\n ] = score\n\n tma_stage = (tma_stage + 1) % num_stages\n if tma_stage == 0:\n tma_parity ^= 1\n elif kv_block < max_k_tiles:\n # Padding tile in [num_kv_blocks, max_k_tiles) -> -inf.\n if warp_id == 0:\n head_p = lane_id // pack\n token_p = lane_id - head_p * pack\n if lane_id < block_q and cute.elem_less(token_p, seqlen_q):\n mMaxScore[\n kv_head * group + head_p,\n kv_block,\n q_start + token_p,\n ] = -cutlass.Float32.inf\n elif split_idx < max_k_tiles:\n # CTA with no valid block: only padding stores remain.\n if warp_id == 0:\n for it in cutlass.range(n_iter):\n kv_block = split_idx + it * num_splits\n if kv_block < max_k_tiles:\n head_p2 = lane_id // pack\n token_p2 = lane_id - head_p2 * pack\n if lane_id < block_q and cute.elem_less(token_p2, seqlen_q):\n mMaxScore[\n kv_head * group + head_p2,\n kv_block,\n q_start + token_p2,\n ] = -cutlass.Float32.inf\n\n\nclass MsaProxyScoreDecodeStreamSm12x:\n \"\"\"Single-token decode schedule: at one query token the score tile is only\n group_size rows, too skinny for the MMA atom, so K streams straight from\n GMEM to registers (no smem, no tensor cores) and dim-parallel lanes reduce\n each key's dot products with warp shuffles.\n\n Deliberately q_len == 1 only: the shuffle+FMA phase scales with q_len\n while the K loads don't, and that rising arithmetic intensity is exactly\n what starts paying for the tensor cores. MTP stays on the packed-MMA\n schedules.\"\"\"\n\n _NUM_WARPS = 8\n _KEYS_PER_ITER = 2 # 32 lanes = 2 keys x 16 dim-slice lanes\n\n def __init__(\n self,\n head_dim: int = 128,\n group_size: int = 4,\n is_causal: bool = True,\n paged: bool = False,\n kv_fp8: bool = False,\n qoff_default: bool = True,\n ):\n if head_dim != 128:\n raise ValueError(\"only head_dim == 128 is supported\")\n # Q and the running maxes live in registers per lane; past 8 heads the\n # footprint approaches the spill point, so larger groups keep the\n # packed MMA schedule.\n if not 1 <= group_size <= 8:\n raise ValueError(\"group_size must be in [1, 8]\")\n self._head_dim = head_dim\n self._G = group_size\n self._is_causal = is_causal\n self._paged = paged\n self._kv_fp8 = kv_fp8\n # Right-aligned decode (q_offset=None): the single query sits at\n # seqlen_k - 1, so the causal limit is just seqlen_k and no offset\n # tensor is needed.\n self._qoff_default = qoff_default\n self._blk_kv = 128\n self._num_threads = self._NUM_WARPS * 32\n self._keys_per_warp = self._blk_kv // self._NUM_WARPS\n self._num_iters = self._keys_per_warp // self._KEYS_PER_ITER\n\n @cute.jit\n def __call__(\n self,\n mQ: cute.Tensor, # (total_q, Hq, d)\n mK: cute.Tensor, # (total_k, Hkv, d) flat | (pages, Hkv, 128, d) paged\n mPageTable: cute.Tensor, # (B, max_pages) int32 (dummy if flat)\n mMaxScore: cute.Tensor, # (Hq, max_k_tiles, total_q) f32\n mCuQ: cute.Tensor, # (B + 1,) int32 (unused: one q token per request)\n mCuK: cute.Tensor, # (B + 1,) int32\n mQOffset: cute.Tensor, # (B,) int32 causal offset (MSA q_offset)\n max_seqlen_q: cutlass.Int32, # 1 (kept for signature parity)\n batch_size: cutlass.Int32,\n num_qo_heads: cutlass.Int32,\n max_k_tiles: cutlass.Int32,\n num_splits: cutlass.Int32, # unused: the grid is already per KV block\n stream: cuda.CUstream,\n ):\n if cutlass.const_expr(\n not (\n mQ.element_type == cutlass.Float16\n or mQ.element_type == cutlass.BFloat16\n )\n ):\n raise TypeError(\"Only Float16 or BFloat16 q is supported\")\n self._dtype: Type[cutlass.Numeric] = mQ.element_type\n self.kernel(mQ, mK, mPageTable, mMaxScore, mCuK, mQOffset).launch(\n grid=(max_k_tiles, batch_size, num_qo_heads // self._G),\n block=[self._num_threads, 1, 1],\n stream=stream,\n )\n\n @cute.kernel\n def kernel(\n self,\n mQ: cute.Tensor,\n mK: cute.Tensor,\n mPageTable: cute.Tensor,\n mMaxScore: cute.Tensor,\n mCuK: cute.Tensor,\n mQOffset: cute.Tensor,\n ):\n lane = cute.arch.lane_idx()\n warp = cute.arch.warp_idx()\n tile, qi, kv_head = cute.arch.block_idx()\n\n G = self._G\n if cutlass.const_expr(self._paged):\n # mCuK holds per-request lengths on the paged path:\n # page_table supplies every KV address, so there is\n # no base offset to add.\n k_start = cutlass.Int32(0)\n seqlen_k = mCuK[qi]\n else:\n k_start = mCuK[qi]\n seqlen_k = mCuK[qi + 1] - k_start\n if cutlass.const_expr(self._is_causal and not self._qoff_default):\n col_limit = cutlass.min(mQOffset[qi] + 1, seqlen_k)\n else:\n col_limit = seqlen_k\n tile_base = tile * self._blk_kv\n\n lane_key = lane >> 4 # which of the warp's two keys this half-warp owns\n lane_grp = lane & 15 # this lane's 8-dim slice index within its key\n\n mfrag = cute.make_rmem_tensor((G,), cutlass.Float32)\n mfrag.fill(-cutlass.Float32.inf)\n\n # tile/qi are CTA-uniform, so the whole block skips dead tiles together\n # (their output stays -inf) and the shuffles below stay full-warp.\n if tile_base < col_limit:\n qfrags = [\n cute.make_rmem_tensor(cute.make_layout(8), self._dtype)\n for _ in range(G)\n ]\n for g in cutlass.range_constexpr(G):\n q_chunk = cute.local_tile(\n mQ[qi, kv_head * G + g, None], (8,), (lane_grp,)\n )\n cute.autovec_copy(q_chunk, qfrags[g])\n qs = [[cutlass.Float32(qfrags[g][i]) for i in range(8)] for g in range(G)]\n\n if cutlass.const_expr(self._paged):\n page = mPageTable[qi, tile]\n mK_blk = mK[page, kv_head, None, None] # (128, d)\n else:\n mK_h = mK[None, kv_head, None] # (total_k, d)\n\n # Keep this loop separate from the compute loop below: issuing all\n # loads before any consumption is the latency hiding. fp8 K stays\n # e4m3 through the loads (half the DRAM bytes) and upconverts per\n # iteration in the compute loop.\n kfrag = cute.make_rmem_tensor(\n cute.make_layout(self._num_iters * 8), mK.element_type\n )\n for it in cutlass.range_constexpr(self._num_iters):\n off = warp * self._keys_per_warp + it * self._KEYS_PER_ITER + lane_key\n # Tail keys clamp to the tile's first row (always in range for a\n # live tile) so loads stay unpredicated; the max step masks them.\n ld_off = off if tile_base + off < col_limit else 0\n if cutlass.const_expr(self._paged):\n k_row = mK_blk[ld_off, None]\n else:\n k_row = mK_h[k_start + tile_base + ld_off, None]\n k_chunk = cute.local_tile(k_row, (8,), (lane_grp,))\n dst = cute.make_tensor(kfrag.iterator + it * 8, cute.make_layout(8))\n cute.autovec_copy(k_chunk, dst)\n\n for it in cutlass.range_constexpr(self._num_iters):\n if cutlass.const_expr(self._kv_fp8):\n # f16 intermediate (exact for e4m3), packed cvt.\n k8 = cute.make_tensor(kfrag.iterator + it * 8, cute.make_layout(8))\n kf16 = cute.make_rmem_tensor(cute.make_layout(8), cutlass.Float16)\n _cvt_fp8_frag(k8, kf16)\n ks = [cutlass.Float32(kf16[i]) for i in range(8)]\n else:\n ks = [cutlass.Float32(kfrag[it * 8 + i]) for i in range(8)]\n es = [\n qs[g][0] * ks[0]\n + qs[g][1] * ks[1]\n + qs[g][2] * ks[2]\n + qs[g][3] * ks[3]\n + qs[g][4] * ks[4]\n + qs[g][5] * ks[5]\n + qs[g][6] * ks[6]\n + qs[g][7] * ks[7]\n for g in range(G)\n ]\n # Butterfly-add over the 16 dim-slice lanes of this key.\n for s in cutlass.range_constexpr(4):\n off_r = 8 >> s\n es = [\n es[g] + cute.arch.shuffle_sync_bfly(es[g], off_r)\n for g in range(G)\n ]\n pos = (\n tile_base\n + warp * self._keys_per_warp\n + it * self._KEYS_PER_ITER\n + lane_key\n )\n if pos < col_limit:\n for g in cutlass.range_constexpr(G):\n mfrag[g] = cute.arch.fmax(mfrag[g], es[g])\n\n # Max-combine the two half-warps' keys.\n for g in cutlass.range_constexpr(G):\n mfrag[g] = cute.arch.fmax(\n mfrag[g], cute.arch.shuffle_sync_bfly(mfrag[g], 16)\n )\n\n @cute.struct\n class SharedStorage:\n s_max: cute.struct.MemRange[cutlass.Float32, self._NUM_WARPS * G]\n\n smem = cutlass.utils.SmemAllocator()\n storage = smem.allocate(SharedStorage)\n s_max = storage.s_max.get_tensor(\n cute.make_layout((self._NUM_WARPS, G), stride=(G, 1))\n )\n if lane == 0:\n for g in cutlass.range_constexpr(G):\n s_max[warp, g] = mfrag[g]\n cute.arch.sync_threads()\n\n if warp == 0 and lane < G:\n r = s_max[0, lane]\n for w in cutlass.range_constexpr(1, self._NUM_WARPS):\n r = cute.arch.fmax(r, s_max[w, lane])\n mMaxScore[kv_head * G + lane, tile, qi] = r\n"},"diff":{"kind":"string","value":"--- flashinfer/msa_ops/cute_dsl/proxy_score_sm12x.py\n+++ flashinfer/msa_ops/cute_dsl/proxy_score_sm12x.py\n@@ -531,6 +531,7 @@\n kv_fp8: bool = False,\n qhead_per_kv: int = 4,\n pack_q_len: int = 16,\n+ qoff_default: bool = False,\n ):\n super().__init__(\n head_dim=head_dim,\n@@ -550,6 +551,8 @@\n # factorization compiles to its own kernel.\n self._qhead_per_kv = qhead_per_kv\n self._pack_q_len = pack_q_len\n+ # True: right-aligned decode; the causal offset is computed in-kernel.\n+ self._qoff_default = qoff_default\n \n @cute.jit\n def __call__(\n@@ -628,6 +631,12 @@\n k_start = mCuK[batch_idx]\n seqlen_k = mCuK[batch_idx + 1] - k_start\n num_kv_blocks = cute.ceil_div(seqlen_k, self._n_block_size)\n+ q_off = cutlass.Int32(0)\n+ if cutlass.const_expr(self._is_causal):\n+ if cutlass.const_expr(self._qoff_default):\n+ q_off = seqlen_k - seqlen_q\n+ else:\n+ q_off = mQOffset[batch_idx]\n \n sQ_layout = self._make_sq_layout()\n sK_layout = self._make_sk_layout()\n@@ -784,9 +793,7 @@\n row = tScS_mn[r, 0][0]\n token = row % self._pack_q_len\n if cutlass.const_expr(self._is_causal):\n- col_limit = cutlass.min(\n- token + mQOffset[batch_idx] + 1, seqlen_k\n- )\n+ col_limit = cutlass.min(token + q_off + 1, seqlen_k)\n else:\n col_limit = seqlen_k\n for c in cutlass.range_constexpr(cute.size(tScS_mn.shape[1])):\n@@ -890,6 +897,12 @@\n k_start = mCuK[batch_idx]\n seqlen_k = mCuK[batch_idx + 1] - k_start\n num_kv_blocks = cute.ceil_div(seqlen_k, self._n_block_size)\n+ q_off = cutlass.Int32(0)\n+ if cutlass.const_expr(self._is_causal):\n+ if cutlass.const_expr(self._qoff_default):\n+ q_off = seqlen_k - seqlen_q\n+ else:\n+ q_off = mQOffset[batch_idx]\n \n sQ_layout = self._make_sq_layout()\n sK_layout = self._make_sk8_layout()\n@@ -1090,9 +1103,7 @@\n row = tScS_mn[r, 0][0]\n token = row % self._pack_q_len\n if cutlass.const_expr(self._is_causal):\n- col_limit = cutlass.min(\n- token + mQOffset[batch_idx] + 1, seqlen_k\n- )\n+ col_limit = cutlass.min(token + q_off + 1, seqlen_k)\n else:\n col_limit = seqlen_k\n for c in cutlass.range_constexpr(cute.size(tScS_mn.shape[1])):"},"lines_added":{"kind":"number","value":17,"string":"17"},"lines_removed":{"kind":"number","value":6,"string":"6"},"files_in_commit":{"kind":"number","value":7,"string":"7"},"models_mentioned":{"kind":"list like","value":["minimax"],"string":"[\n \"minimax\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["RTX5080","SM120","SM121"],"string":"[\n \"RTX5080\",\n \"SM120\",\n \"SM121\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":["2.2x","2.1x"],"string":"[\n \"2.2x\",\n \"2.1x\"\n]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cute_dsl kernel file from flashinfer (flashinfer/msa_ops/cute_dsl/proxy_score_sm12x.py).\n\nGoal: perf(msa): chunked top-k and in-kernel causal offsets for the SM12x indexer\nTarget hardware: RTX5080, SM120, SM121\nTarget models: minimax\n\nCurrent file:\n```python\n\"\"\"\nCopyright (c) 2026 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nMSA dense proxy-score kernels for SM120/SM121: per (head, KV block, query) max\nof the unscaled post-mask QK^T logits; masked blocks yield -inf.\n\"\"\"\n\nfrom typing import Type\n\nimport cuda.bindings.driver as cuda\nimport cutlass\nimport cutlass.cute as cute\nimport cutlass.pipeline as pipeline\nfrom cutlass._mlir.dialects import llvm\nfrom cutlass.cute.nvgpu import cpasync, warp\nfrom cutlass.cutlass_dsl import T, dsl_user_op\n\n\n@dsl_user_op\ndef _fp8x4_to_f16x4(x: cutlass.Uint32, *, loc=None, ip=None):\n out = llvm.inline_asm(\n llvm.StructType.get_literal([T.i32()] * 2),\n [x.ir_value(loc=loc, ip=ip)],\n \"{\\n\\t\"\n \".reg .b16 lo, hi;\\n\\t\"\n \"mov.b32 {lo, hi}, $2;\\n\\t\"\n \"cvt.rn.f16x2.e4m3x2 $0, lo;\\n\\t\"\n \"cvt.rn.f16x2.e4m3x2 $1, hi;\\n\\t\"\n \"}\\n\",\n \"=r,=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n loc=loc,\n ip=ip,\n )\n return (\n cutlass.Uint32(llvm.extractvalue(T.i32(), out, [0], loc=loc, ip=ip)),\n cutlass.Uint32(llvm.extractvalue(T.i32(), out, [1], loc=loc, ip=ip)),\n )\n\n\n@dsl_user_op\ndef _fp8x4_to_bf16x4(x: cutlass.Uint32, *, loc=None, ip=None):\n # There is no e4m3 -> bf16 cvt; round-trip through f16, which is exact\n # (every e4m3 value is representable in both f16 and bf16).\n out = llvm.inline_asm(\n llvm.StructType.get_literal([T.i32()] * 2),\n [x.ir_value(loc=loc, ip=ip)],\n \"{\\n\\t\"\n \".reg .b16 lo, hi, t00, t01, t10, t11;\\n\\t\"\n \"mov.b32 {lo, hi}, $2;\\n\\t\"\n \"cvt.rn.f16x2.e4m3x2 $0, lo;\\n\\t\"\n \"cvt.rn.f16x2.e4m3x2 $1, hi;\\n\\t\"\n \"mov.b32 {t00, t01}, $0;\\n\\t\"\n \"mov.b32 {t10, t11}, $1;\\n\\t\"\n \"cvt.rn.bf16.f16 t00, t00;\\n\\t\"\n \"cvt.rn.bf16.f16 t01, t01;\\n\\t\"\n \"cvt.rn.bf16.f16 t10, t10;\\n\\t\"\n \"cvt.rn.bf16.f16 t11, t11;\\n\\t\"\n \"mov.b32 $0, {t00, t01};\\n\\t\"\n \"mov.b32 $1, {t10, t11};\\n\\t\"\n \"}\\n\",\n \"=r,=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n loc=loc,\n ip=ip,\n )\n return (\n cutlass.Uint32(llvm.extractvalue(T.i32(), out, [0], loc=loc, ip=ip)),\n cutlass.Uint32(llvm.extractvalue(T.i32(), out, [1], loc=loc, ip=ip)),\n )\n\n\n@cute.jit\ndef _cvt_fp8_frag(src: cute.Tensor, dst: cute.Tensor):\n \"\"\"Convert an e4m3 register fragment to dst's f16/bf16 element type with\n packed cvt (one instruction per four elements); element-wise ``.to()``\n lowers to a byte-extract sequence.\"\"\"\n src_u32 = cute.recast_tensor(src, cutlass.Uint32)\n dst_u32 = cute.recast_tensor(dst, cutlass.Uint32)\n for i in cutlass.range_constexpr(cute.size(src.shape) // 4):\n if cutlass.const_expr(dst.element_type is cutlass.BFloat16):\n lo, hi = _fp8x4_to_bf16x4(src_u32[i])\n else:\n lo, hi = _fp8x4_to_f16x4(src_u32[i])\n dst_u32[i * 2] = lo\n dst_u32[i * 2 + 1] = hi\n\n\nclass MsaProxyScoreSm12x:\n \"\"\"General bf16/fp16 proxy schedule (any q length, fp8 K, flat or paged):\n every query head scores against its kv_head's index-K independently.\"\"\"\n\n def __init__(\n self,\n head_dim: int = 128,\n m_block_size: int = 64,\n n_block_size: int = 128,\n num_threads: int = 128,\n is_causal: bool = True,\n paged: bool = False,\n kv_fp8: bool = False,\n ):\n if head_dim != 128 or n_block_size != 128:\n raise ValueError(\"only head_dim == n_block_size == 128 is supported\")\n self._head_dim = head_dim\n self._m_block_size = m_block_size\n self._n_block_size = n_block_size\n self._num_threads = num_threads\n self._is_causal = is_causal\n self._paged = paged\n self._kv_fp8 = kv_fp8\n\n self.cta_sync_barrier = pipeline.NamedBarrier(\n barrier_id=1, num_threads=num_threads\n )\n\n def _make_sk_layout(self):\n \"\"\"K SMEM layout (built in-kernel for region isolation). The fp8\n convert path stores 16B-aligned chunks, so the swizzle works for it\n too; a padded layout would cost a second CTA per SM (48KB -> >50KB).\"\"\"\n atom = cute.make_composed_layout(\n cute.make_swizzle(3, 3, 3),\n 0,\n cute.make_layout((8, 64), stride=(64, 1)),\n )\n return cute.tile_to_shape(atom, (self._n_block_size, self._head_dim), (0, 1))\n\n def _make_sq_layout(self):\n atom = cute.make_composed_layout(\n cute.make_swizzle(3, 3, 3),\n 0,\n cute.make_layout((8, 64), stride=(64, 1)),\n )\n return cute.tile_to_shape(atom, (self._m_block_size, self._head_dim), (0, 1))\n\n @cute.jit\n def __call__(\n self,\n mQ: cute.Tensor, # (total_q, Hq, d)\n mK: cute.Tensor, # (total_k, Hkv, d) flat | (pages, Hkv, 128, d) paged\n mPageTable: cute.Tensor, # (B, max_pages) int32 (dummy (1,1) if flat)\n mMaxScore: cute.Tensor, # (Hq, max_k_tiles, total_q) f32\n mCuQ: cute.Tensor, # (B + 1,) int32\n mCuK: cute.Tensor, # (B + 1,) int32\n mQOffset: cute.Tensor, # (B,) int32 causal offset (MSA q_offset)\n max_seqlen_q: cutlass.Int32,\n batch_size: cutlass.Int32,\n num_qo_heads: cutlass.Int32,\n max_k_tiles: cutlass.Int32,\n num_splits: cutlass.Int32,\n stream: cuda.CUstream,\n ):\n if cutlass.const_expr(\n not (\n mQ.element_type == cutlass.Float16\n or mQ.element_type == cutlass.BFloat16\n )\n ):\n raise TypeError(\"Only Float16 or BFloat16 q is supported\")\n self._dtype: Type[cutlass.Numeric] = mQ.element_type\n\n # Split-K: fold a kv-block split factor into grid x to fill the SMs when the\n # base grid (1, batch, heads) starves at low batch. Output is per-(head,\n # kv_block, query) so splits write disjoint columns, no reduction.\n self.kernel(\n mQ,\n mK,\n mPageTable,\n mMaxScore,\n mCuQ,\n mCuK,\n mQOffset,\n max_k_tiles,\n num_splits,\n ).launch(\n grid=(\n cute.ceil_div(max_seqlen_q, self._m_block_size) * num_splits,\n batch_size,\n num_qo_heads,\n ),\n block=[self._num_threads, 1, 1],\n stream=stream,\n )\n\n @cute.kernel\n def kernel(\n self,\n mQ: cute.Tensor,\n mK: cute.Tensor,\n mPageTable: cute.Tensor,\n mMaxScore: cute.Tensor,\n mCuQ: cute.Tensor,\n mCuK: cute.Tensor,\n mQOffset: cute.Tensor,\n max_k_tiles: cutlass.Int32,\n num_splits: cutlass.Int32,\n ):\n tidx, _, _ = cute.arch.thread_idx()\n bx, batch_idx, qo_head = cute.arch.block_idx()\n # grid x packs (m_block, split): splits of one m_block are adjacent so\n # they share the same Q tile in L2 (only the kv-block subset differs).\n m_block = bx // num_splits\n split_idx = bx % num_splits\n\n q_start = mCuQ[batch_idx]\n seqlen_q = mCuQ[batch_idx + 1] - q_start\n if cutlass.const_expr(self._paged):\n # mCuK holds per-request lengths on the paged path:\n # page_table supplies every KV address, so there is\n # no base offset to add.\n k_start = cutlass.Int32(0)\n seqlen_k = mCuK[batch_idx]\n else:\n k_start = mCuK[batch_idx]\n seqlen_k = mCuK[batch_idx + 1] - k_start\n num_kv_blocks = cute.ceil_div(seqlen_k, self._n_block_size)\n group_size = mQ.shape[1] // mK.shape[1]\n kv_head = qo_head // group_size\n\n if m_block * self._m_block_size < seqlen_q:\n sQ_layout = self._make_sq_layout()\n sK_layout = self._make_sk_layout()\n\n @cute.struct\n class SharedStorage:\n sQ: cute.struct.Align[\n cute.struct.MemRange[self._dtype, cute.cosize(sQ_layout)],\n 1024,\n ]\n sK: cute.struct.Align[\n cute.struct.MemRange[self._dtype, cute.cosize(sK_layout)],\n 1024,\n ]\n\n smem = cutlass.utils.SmemAllocator()\n storage = smem.allocate(SharedStorage)\n sQ = storage.sQ.get_tensor(sQ_layout)\n sK = storage.sK.get_tensor(sK_layout)\n\n # K is in this tiled copy only on the non-fp8 path (fp8 K loads separately)\n universal_copy_bits = 128\n async_copy_elems = universal_copy_bits // self._dtype.width\n atom_async_copy = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n self._dtype,\n num_bits_per_copy=universal_copy_bits,\n )\n t_dim1 = 64 // async_copy_elems\n t_layout = cute.make_layout(\n (self._num_threads // t_dim1, t_dim1), stride=(t_dim1, 1)\n )\n v_layout = cute.make_layout((1, async_copy_elems))\n gmem_tiled_copy = cute.make_tiled_copy_tv(\n atom_async_copy, t_layout, v_layout\n )\n gmem_thr_copy = gmem_tiled_copy.get_slice(tidx)\n\n mQ_h = cute.domain_offset((q_start, 0), mQ[None, qo_head, None])\n gQ = cute.local_tile(\n mQ_h, (self._m_block_size, self._head_dim), (m_block, 0)\n )\n tQgQ = gmem_thr_copy.partition_S(gQ)\n tQsQ = gmem_thr_copy.partition_D(sQ)\n cQ = cute.make_identity_tensor((self._m_block_size, self._head_dim))\n tQcQ = gmem_thr_copy.partition_S(cQ)\n\n for m in cutlass.range_constexpr(cute.size(tQsQ.shape[1])):\n if (m_block * self._m_block_size + tQcQ[0, m, 0][0]) < seqlen_q:\n cute.copy(\n gmem_tiled_copy,\n tQgQ[None, m, None],\n tQsQ[None, m, None],\n )\n else:\n tQsQ[None, m, None].fill(0)\n cute.arch.cp_async_commit_group()\n\n tiled_mma = cute.make_tiled_mma(\n warp.MmaF16BF16Op(self._dtype, cutlass.Float32, (16, 8, 16)),\n (self._num_threads // 32, 1, 1),\n permutation_mnk=(self._num_threads // 32 * 16, 16, 16),\n )\n thr_mma = tiled_mma.get_slice(tidx)\n tSrQ = thr_mma.make_fragment_A(thr_mma.partition_A(sQ))\n tSrK = thr_mma.make_fragment_B(thr_mma.partition_B(sK))\n acc_S = cute.make_rmem_tensor(\n thr_mma.partition_shape_C((self._m_block_size, self._n_block_size)),\n cutlass.Float32,\n )\n\n smem_copy_atom = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(transpose=False, num_matrices=4),\n self._dtype,\n )\n smem_tiled_copy_Q = cute.make_tiled_copy_A(smem_copy_atom, tiled_mma)\n smem_tiled_copy_K = cute.make_tiled_copy_B(smem_copy_atom, tiled_mma)\n smem_thr_copy_Q = smem_tiled_copy_Q.get_slice(tidx)\n smem_thr_copy_K = smem_tiled_copy_K.get_slice(tidx)\n tSsQ = smem_thr_copy_Q.partition_S(sQ)\n tSrQ_copy_view = smem_thr_copy_Q.retile(tSrQ)\n tSsK = smem_thr_copy_K.partition_S(sK)\n tSrK_copy_view = smem_thr_copy_K.retile(tSrK)\n\n cS = cute.make_identity_tensor((self._m_block_size, self._n_block_size))\n tScS_mn = self._make_acc_tensor_mn_view(thr_mma.partition_C(cS))\n acc_S_mn = self._make_acc_tensor_mn_view(acc_S)\n n_rows = cute.size(acc_S_mn.shape[0])\n\n # K gmem views; the block mode is indexed after partitioning so the\n # copy tile shapes stay static.\n if cutlass.const_expr(not self._kv_fp8):\n if cutlass.const_expr(self._paged):\n pass # per-block page lookup happens inside the loop\n else:\n mK_h = cute.domain_offset((k_start, 0), mK[None, kv_head, None])\n gK = cute.local_tile(\n mK_h, (self._n_block_size, self._head_dim), (None, 0)\n )\n tKgK_flat = gmem_thr_copy.partition_S(gK)\n tKsK = gmem_thr_copy.partition_D(sK)\n cKV = cute.make_identity_tensor((self._n_block_size, self._head_dim))\n tKVcKV = gmem_thr_copy.partition_S(cKV)\n\n # sQ is reused across all kv-blocks, so Q fragments load once here\n cute.arch.cp_async_wait_group(0)\n self.cta_sync_barrier.arrive_and_wait()\n for kk in cutlass.range_constexpr(cute.size(tSsQ.shape[2])):\n cute.copy(\n smem_tiled_copy_Q,\n tSsQ[None, None, kk],\n tSrQ_copy_view[None, None, kk],\n )\n\n # Split-K CTAs stride kv_block by num_splits. Causal skip: kv-blocks\n # entirely above the q-tile's causal limit get their -inf written directly,\n # with no K load or MMA (masking after the MMA would waste the work).\n if cutlass.const_expr(self._is_causal):\n causal_last = (\n m_block * self._m_block_size\n + (self._m_block_size - 1)\n + mQOffset[batch_idx]\n ) // self._n_block_size\n last_block = cutlass.min(causal_last, num_kv_blocks - 1)\n else:\n last_block = num_kv_blocks - 1\n\n n_iter = cute.ceil_div(max_k_tiles, num_splits)\n for it in cutlass.range(n_iter):\n kv_block = split_idx + it * num_splits\n if kv_block <= last_block:\n self.cta_sync_barrier.arrive_and_wait()\n if cutlass.const_expr(self._kv_fp8):\n if cutlass.const_expr(self._paged):\n page8 = mPageTable[batch_idx, kv_block]\n mK_h8 = mK[page8, kv_head, None, None]\n row_off8 = cutlass.Int32(0)\n else:\n mK_h8 = cute.domain_offset(\n (k_start, 0), mK[None, kv_head, None]\n )\n row_off8 = kv_block * self._n_block_size\n chunks_per_row = self._head_dim // 8\n total_chunks = self._n_block_size * chunks_per_row\n cvt_frag = cute.make_rmem_tensor(\n cute.make_layout(8), self._dtype\n )\n for kv_it in cutlass.range_constexpr(\n total_chunks // self._num_threads\n ):\n kv_chunk = tidx + kv_it * self._num_threads\n kv_m = kv_chunk // chunks_per_row\n kv_c8 = kv_chunk % chunks_per_row\n sK_chunk = cute.local_tile(sK[kv_m, None], (8,), (kv_c8,))\n if (kv_block * self._n_block_size + kv_m) < seqlen_k:\n gKc = cute.local_tile(\n mK_h8[row_off8 + kv_m, None], (8,), (kv_c8,)\n )\n cvt_frag.store(\n gKc.load()\n .to(cutlass.Float16)\n .to(cutlass.Float32)\n .to(self._dtype)\n )\n else:\n cvt_frag.fill(0)\n cute.autovec_copy(cvt_frag, sK_chunk)\n else:\n # Branch bodies keep their own tensor names: aliasing an outer\n # tensor in this dynamic loop would make it loop-carried.\n if cutlass.const_expr(self._paged):\n page = mPageTable[batch_idx, kv_block]\n gK_pg = cute.local_tile(\n mK[page, kv_head, None, None],\n (self._n_block_size, self._head_dim),\n (None, 0),\n )\n tKgK_pg = gmem_thr_copy.partition_S(gK_pg)\n for n in cutlass.range_constexpr(cute.size(tKsK.shape[1])):\n if (\n kv_block * self._n_block_size + tKVcKV[0, n, 0][0]\n ) < seqlen_k:\n cute.copy(\n gmem_tiled_copy,\n tKgK_pg[None, n, None, 0],\n tKsK[None, n, None],\n )\n else:\n tKsK[None, n, None].fill(0)\n else:\n for n in cutlass.range_constexpr(cute.size(tKsK.shape[1])):\n if (\n kv_block * self._n_block_size + tKVcKV[0, n, 0][0]\n ) < seqlen_k:\n cute.copy(\n gmem_tiled_copy,\n tKgK_flat[None, n, None, kv_block],\n tKsK[None, n, None],\n )\n else:\n tKsK[None, n, None].fill(0)\n cute.arch.cp_async_commit_group()\n cute.arch.cp_async_wait_group(0)\n self.cta_sync_barrier.arrive_and_wait()\n\n # S = Q K^T (unscaled)\n acc_S.fill(0.0)\n for kk in cutlass.range_constexpr(cute.size(tSsK.shape[2])):\n cute.copy(\n smem_tiled_copy_K,\n tSsK[None, None, kk],\n tSrK_copy_view[None, None, kk],\n )\n for kk in cutlass.range_constexpr(cute.size(tSsK.shape[2])):\n cute.gemm(\n tiled_mma,\n acc_S,\n tSrQ[None, None, kk],\n tSrK[None, None, kk],\n acc_S,\n )\n\n for r in cutlass.range_constexpr(n_rows):\n row_local = tScS_mn[r, 0][0]\n q_loc = m_block * self._m_block_size + row_local\n if cutlass.const_expr(self._is_causal):\n col_limit = cutlass.min(\n q_loc + mQOffset[batch_idx] + 1, seqlen_k\n )\n else:\n col_limit = seqlen_k\n for c in cutlass.range_constexpr(cute.size(tScS_mn.shape[1])):\n k_pos = kv_block * self._n_block_size + tScS_mn[0, c][1]\n if cute.elem_less(col_limit, k_pos + 1):\n acc_S_mn[r, c] = -cutlass.Float32.inf\n tile_max = (\n acc_S_mn[r, None]\n .load()\n .reduce(cute.ReductionOp.MAX, -cutlass.Float32.inf, 0)\n )\n tile_max = self._threadquad_reduce_max(tile_max)\n if q_loc < seqlen_q:\n # All 4 quad threads hold the same value; the\n # duplicate stores are idempotent.\n mMaxScore[qo_head, kv_block, q_start + q_loc] = tile_max\n elif kv_block < max_k_tiles:\n # Blocks past last_block (causally future or padding) get -inf, no\n # MMA. Bounded by max_k_tiles so split-K overshoot writes nothing.\n for r in cutlass.range_constexpr(n_rows):\n row_local2 = tScS_mn[r, 0][0]\n q_loc2 = m_block * self._m_block_size + row_local2\n if q_loc2 < seqlen_q:\n mMaxScore[\n qo_head, kv_block, q_start + q_loc2\n ] = -cutlass.Float32.inf\n\n @cute.jit\n def _threadquad_reduce_max(self, val):\n val = cute.arch.fmax(\n val,\n cute.arch.shuffle_sync_bfly(val, offset=2, mask=-1, mask_and_clamp=31),\n )\n val = cute.arch.fmax(\n val,\n cute.arch.shuffle_sync_bfly(val, offset=1, mask=-1, mask_and_clamp=31),\n )\n return val\n\n def _make_acc_tensor_mn_view(self, acc: cute.Tensor) -> cute.Tensor:\n acc_layout_col_major = cute.make_layout(acc.layout.shape)\n acc_layout_mn = cute.make_layout(\n (\n (acc_layout_col_major.shape[0][1], acc_layout_col_major.shape[1]),\n (acc_layout_col_major.shape[0][0], acc_layout_col_major.shape[2]),\n ),\n stride=(\n (acc_layout_col_major.stride[0][1], acc_layout_col_major.stride[1]),\n (acc_layout_col_major.stride[0][0], acc_layout_col_major.stride[2]),\n ),\n )\n acc_layout_mn = cute.composition(acc.layout, acc_layout_mn)\n return cute.make_tensor(acc.iterator, acc_layout_mn)\n\n\nclass MsaProxyScoreDecodePackedSm12x(MsaProxyScoreSm12x):\n \"\"\"Head-fused packed-decode bf16/fp16 schedule: packs qhead_per_kv heads x\n pack_q_len tokens into the M rows so the shared index-K is read once per\n kv_head. fp8 K takes the key-split subclass instead.\"\"\"\n\n def __init__(\n self,\n head_dim: int = 128,\n m_block_size: int = 64,\n n_block_size: int = 128,\n num_threads: int = 128,\n is_causal: bool = True,\n paged: bool = False,\n kv_fp8: bool = False,\n qhead_per_kv: int = 4,\n pack_q_len: int = 16,\n ):\n super().__init__(\n head_dim=head_dim,\n m_block_size=m_block_size,\n n_block_size=n_block_size,\n num_threads=num_threads,\n is_causal=is_causal,\n paged=paged,\n kv_fp8=kv_fp8,\n )\n if qhead_per_kv * pack_q_len != m_block_size:\n raise ValueError(\n f\"qhead_per_kv * pack_q_len must equal the {m_block_size}-row MMA \"\n f\"tile, got {qhead_per_kv} x {pack_q_len}\"\n )\n # These attrs are constexpr-baked into the gather/epilogue, so each\n # factorization compiles to its own kernel.\n self._qhead_per_kv = qhead_per_kv\n self._pack_q_len = pack_q_len\n\n @cute.jit\n def __call__(\n self,\n mQ: cute.Tensor,\n mK: cute.Tensor,\n mPageTable: cute.Tensor,\n mMaxScore: cute.Tensor,\n mCuQ: cute.Tensor,\n mCuK: cute.Tensor,\n mQOffset: cute.Tensor,\n max_seqlen_q: cutlass.Int32,\n batch_size: cutlass.Int32,\n num_qo_heads: cutlass.Int32,\n max_k_tiles: cutlass.Int32,\n num_splits: cutlass.Int32,\n stream: cuda.CUstream,\n ):\n if cutlass.const_expr(\n not (\n mQ.element_type == cutlass.Float16\n or mQ.element_type == cutlass.BFloat16\n )\n ):\n raise TypeError(\"Only Float16 or BFloat16 q is supported\")\n self._dtype: Type[cutlass.Numeric] = mQ.element_type\n\n # One CTA per (split, batch, kv_head): all qhead_per_kv heads of a kv_head\n # are packed into the single m_block_size-row tile, so the index-K is read\n # once per kv_head (qhead_per_kv x less K traffic than the per-head schedule).\n self.kernel(\n mQ,\n mK,\n mPageTable,\n mMaxScore,\n mCuQ,\n mCuK,\n mQOffset,\n max_k_tiles,\n num_splits,\n ).launch(\n grid=(\n num_splits,\n batch_size,\n num_qo_heads // self._qhead_per_kv,\n ),\n block=[self._num_threads, 1, 1],\n stream=stream,\n )\n\n @cute.kernel\n def kernel(\n self,\n mQ: cute.Tensor,\n mK: cute.Tensor,\n mPageTable: cute.Tensor,\n mMaxScore: cute.Tensor,\n mCuQ: cute.Tensor,\n mCuK: cute.Tensor,\n mQOffset: cute.Tensor,\n max_k_tiles: cutlass.Int32,\n num_splits: cutlass.Int32,\n ):\n tidx, _, _ = cute.arch.thread_idx()\n split_idx, batch_idx, kv_head = cute.arch.block_idx()\n\n q_start = mCuQ[batch_idx]\n seqlen_q = mCuQ[batch_idx + 1] - q_start\n if cutlass.const_expr(self._paged):\n # mCuK holds per-request lengths on the paged path:\n # page_table supplies every KV address, so there is\n # no base offset to add.\n k_start = cutlass.Int32(0)\n seqlen_k = mCuK[batch_idx]\n else:\n k_start = mCuK[batch_idx]\n seqlen_k = mCuK[batch_idx + 1] - k_start\n num_kv_blocks = cute.ceil_div(seqlen_k, self._n_block_size)\n\n sQ_layout = self._make_sq_layout()\n sK_layout = self._make_sk_layout()\n\n @cute.struct\n class SharedStorage:\n sQ: cute.struct.Align[\n cute.struct.MemRange[self._dtype, cute.cosize(sQ_layout)],\n 1024,\n ]\n sK: cute.struct.Align[\n cute.struct.MemRange[self._dtype, cute.cosize(sK_layout)],\n 1024,\n ]\n\n smem = cutlass.utils.SmemAllocator()\n storage = smem.allocate(SharedStorage)\n sQ = storage.sQ.get_tensor(sQ_layout)\n sK = storage.sK.get_tensor(sK_layout)\n\n # Tiled copy covers K only; Q is gathered per-head below\n universal_copy_bits = 128\n async_copy_elems = universal_copy_bits // self._dtype.width\n atom_async_copy = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n self._dtype,\n num_bits_per_copy=universal_copy_bits,\n )\n t_dim1 = 64 // async_copy_elems\n t_layout = cute.make_layout(\n (self._num_threads // t_dim1, t_dim1), stride=(t_dim1, 1)\n )\n v_layout = cute.make_layout((1, async_copy_elems))\n gmem_tiled_copy = cute.make_tiled_copy_tv(atom_async_copy, t_layout, v_layout)\n gmem_thr_copy = gmem_tiled_copy.get_slice(tidx)\n\n self._gather_packed_q(mQ, sQ, q_start, kv_head, seqlen_q, tidx)\n\n tiled_mma = cute.make_tiled_mma(\n warp.MmaF16BF16Op(self._dtype, cutlass.Float32, (16, 8, 16)),\n (self._num_threads // 32, 1, 1),\n permutation_mnk=(self._num_threads // 32 * 16, 16, 16),\n )\n thr_mma = tiled_mma.get_slice(tidx)\n tSrQ = thr_mma.make_fragment_A(thr_mma.partition_A(sQ))\n tSrK = thr_mma.make_fragment_B(thr_mma.partition_B(sK))\n acc_S = cute.make_rmem_tensor(\n thr_mma.partition_shape_C((self._m_block_size, self._n_block_size)),\n cutlass.Float32,\n )\n\n smem_copy_atom = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(transpose=False, num_matrices=4),\n self._dtype,\n )\n smem_tiled_copy_Q = cute.make_tiled_copy_A(smem_copy_atom, tiled_mma)\n smem_tiled_copy_K = cute.make_tiled_copy_B(smem_copy_atom, tiled_mma)\n smem_thr_copy_Q = smem_tiled_copy_Q.get_slice(tidx)\n smem_thr_copy_K = smem_tiled_copy_K.get_slice(tidx)\n tSsQ = smem_thr_copy_Q.partition_S(sQ)\n tSrQ_copy_view = smem_thr_copy_Q.retile(tSrQ)\n tSsK = smem_thr_copy_K.partition_S(sK)\n tSrK_copy_view = smem_thr_copy_K.retile(tSrK)\n\n cS = cute.make_identity_tensor((self._m_block_size, self._n_block_size))\n tScS_mn = self._make_acc_tensor_mn_view(thr_mma.partition_C(cS))\n acc_S_mn = self._make_acc_tensor_mn_view(acc_S)\n n_rows = cute.size(acc_S_mn.shape[0])\n\n # K gmem views, as in the general kernel.\n if cutlass.const_expr(self._paged):\n pass # per-block page lookup happens inside the loop\n else:\n mK_h = cute.domain_offset((k_start, 0), mK[None, kv_head, None])\n gK = cute.local_tile(mK_h, (self._n_block_size, self._head_dim), (None, 0))\n tKgK_flat = gmem_thr_copy.partition_S(gK)\n tKsK = gmem_thr_copy.partition_D(sK)\n cKV = cute.make_identity_tensor((self._n_block_size, self._head_dim))\n tKVcKV = gmem_thr_copy.partition_S(cKV)\n\n # Gather stores are synchronous; order them before the Q fragment reads,\n # then preload the Q fragments once (sQ reused across all kv-blocks).\n self.cta_sync_barrier.arrive_and_wait()\n for kk in cutlass.range_constexpr(cute.size(tSsQ.shape[2])):\n cute.copy(\n smem_tiled_copy_Q,\n tSsQ[None, None, kk],\n tSrQ_copy_view[None, None, kk],\n )\n\n # Split-K CTAs stride kv_block by num_splits, as in the general kernel.\n # No causal skip here: packed decode attends every kv-block and masks\n # the per-token causal tail in the epilogue.\n n_iter = cute.ceil_div(max_k_tiles, num_splits)\n for it in cutlass.range(n_iter):\n kv_block = split_idx + it * num_splits\n if kv_block < num_kv_blocks:\n self.cta_sync_barrier.arrive_and_wait()\n if cutlass.const_expr(self._paged):\n page = mPageTable[batch_idx, kv_block]\n gK_pg = cute.local_tile(\n mK[page, kv_head, None, None],\n (self._n_block_size, self._head_dim),\n (None, 0),\n )\n tKgK_pg = gmem_thr_copy.partition_S(gK_pg)\n for n in cutlass.range_constexpr(cute.size(tKsK.shape[1])):\n if (\n kv_block * self._n_block_size + tKVcKV[0, n, 0][0]\n ) < seqlen_k:\n cute.copy(\n gmem_tiled_copy,\n tKgK_pg[None, n, None, 0],\n tKsK[None, n, None],\n )\n else:\n tKsK[None, n, None].fill(0)\n else:\n for n in cutlass.range_constexpr(cute.size(tKsK.shape[1])):\n if (\n kv_block * self._n_block_size + tKVcKV[0, n, 0][0]\n ) < seqlen_k:\n cute.copy(\n gmem_tiled_copy,\n tKgK_flat[None, n, None, kv_block],\n tKsK[None, n, None],\n )\n else:\n tKsK[None, n, None].fill(0)\n cute.arch.cp_async_commit_group()\n cute.arch.cp_async_wait_group(0)\n self.cta_sync_barrier.arrive_and_wait()\n\n # S = Q K^T (unscaled)\n acc_S.fill(0.0)\n for kk in cutlass.range_constexpr(cute.size(tSsK.shape[2])):\n cute.copy(\n smem_tiled_copy_K,\n tSsK[None, None, kk],\n tSrK_copy_view[None, None, kk],\n )\n for kk in cutlass.range_constexpr(cute.size(tSsK.shape[2])):\n cute.gemm(\n tiled_mma,\n acc_S,\n tSrQ[None, None, kk],\n tSrK[None, None, kk],\n acc_S,\n )\n\n # A packed row maps to (local_head, token); a packed query's causal\n # position is its token index (the decode q within this step).\n for r in cutlass.range_constexpr(n_rows):\n row = tScS_mn[r, 0][0]\n token = row % self._pack_q_len\n if cutlass.const_expr(self._is_causal):\n col_limit = cutlass.min(\n token + mQOffset[batch_idx] + 1, seqlen_k\n )\n else:\n col_limit = seqlen_k\n for c in cutlass.range_constexpr(cute.size(tScS_mn.shape[1])):\n k_pos = kv_block * self._n_block_size + tScS_mn[0, c][1]\n if cute.elem_less(col_limit, k_pos + 1):\n acc_S_mn[r, c] = -cutlass.Float32.inf\n tile_max = (\n acc_S_mn[r, None]\n .load()\n .reduce(cute.ReductionOp.MAX, -cutlass.Float32.inf, 0)\n )\n tile_max = self._threadquad_reduce_max(tile_max)\n local_head = row // self._pack_q_len\n head = kv_head * self._qhead_per_kv + local_head\n if cute.elem_less(token, seqlen_q):\n # All 4 quad threads hold the same value; the duplicate\n # stores are idempotent.\n mMaxScore[head, kv_block, q_start + token] = tile_max\n elif kv_block < max_k_tiles:\n # Padding tile in [num_kv_blocks, max_k_tiles) -> -inf. Bounded by\n # max_k_tiles because split-K can stride kv_block past the last\n # output column (those overshoot blocks write nothing).\n for r in cutlass.range_constexpr(n_rows):\n row2 = tScS_mn[r, 0][0]\n token2 = row2 % self._pack_q_len\n local_head2 = row2 // self._pack_q_len\n head2 = kv_head * self._qhead_per_kv + local_head2\n if cute.elem_less(token2, seqlen_q):\n mMaxScore[\n head2, kv_block, q_start + token2\n ] = -cutlass.Float32.inf\n\n @cute.jit\n def _gather_packed_q(self, mQ, sQ, q_start, kv_head, seqlen_q, tidx):\n \"\"\"Gather the packed Q tile into swizzled smem; rows past seqlen_q are\n zero-filled (epilogue masks them).\"\"\"\n elems = 128 // self._dtype.width\n chunks = self._head_dim // elems\n total = self._m_block_size * chunks\n frag = cute.make_rmem_tensor(cute.make_layout(elems), self._dtype)\n for it in cutlass.range_constexpr(total // self._num_threads):\n e = tidx + it * self._num_threads\n r = e // chunks\n c8 = e % chunks\n local_head = r // self._pack_q_len\n token = r % self._pack_q_len\n head = kv_head * self._qhead_per_kv + local_head\n sQ_chunk = cute.local_tile(sQ[r, None], (elems,), (c8,))\n if cute.elem_less(token, seqlen_q):\n gQ_chunk = cute.local_tile(\n mQ[q_start + token, head, None], (elems,), (c8,)\n )\n frag.store(gQ_chunk.load())\n cute.autovec_copy(frag, sQ_chunk)\n else:\n sQ_chunk.fill(0)\n\n\nclass MsaProxyScoreDecodePackedFp8Sm12x(MsaProxyScoreDecodePackedSm12x):\n \"\"\"fp8-K packed-decode schedule. Same head-fused M rows as the packed\n schedule, but warps split over keys instead of query rows, so the\n e4m3 -> f16/bf16 upconvert runs once per K element instead of once per\n warp. K stays raw e4m3 through cp.async\n and smem, arriving as a 16-bit view with half the head dim (see\n msa_proxy_score), and upconverts in registers between the smem loads and\n the mma. Q is stored column-permuted to match the converted K fragments\n (see _gather_packed_q).\n\n K staging is pipelined at two granularities because split-K often leaves\n a CTA a single KV block: two smem buffers with a one-block prefetch\n overlap across blocks, and each fill commits as two 64-key cp.async\n groups so the mma starts on the first half while the second is still in\n flight.\n \"\"\"\n\n @cute.kernel\n def kernel(\n self,\n mQ: cute.Tensor,\n mK: cute.Tensor,\n mPageTable: cute.Tensor,\n mMaxScore: cute.Tensor,\n mCuQ: cute.Tensor,\n mCuK: cute.Tensor,\n mQOffset: cute.Tensor,\n max_k_tiles: cutlass.Int32,\n num_splits: cutlass.Int32,\n ):\n tidx, _, _ = cute.arch.thread_idx()\n split_idx, batch_idx, kv_head = cute.arch.block_idx()\n\n q_start = mCuQ[batch_idx]\n seqlen_q = mCuQ[batch_idx + 1] - q_start\n if cutlass.const_expr(self._paged):\n # mCuK holds per-request lengths on the paged path:\n # page_table supplies every KV address, so there is\n # no base offset to add.\n k_start = cutlass.Int32(0)\n seqlen_k = mCuK[batch_idx]\n else:\n k_start = mCuK[batch_idx]\n seqlen_k = mCuK[batch_idx + 1] - k_start\n num_kv_blocks = cute.ceil_div(seqlen_k, self._n_block_size)\n\n sQ_layout = self._make_sq_layout()\n sK_layout = self._make_sk8_layout()\n\n @cute.struct\n class SharedStorage:\n sQ: cute.struct.Align[\n cute.struct.MemRange[self._dtype, cute.cosize(sQ_layout)],\n 1024,\n ]\n sK0: cute.struct.Align[\n cute.struct.MemRange[self._dtype, cute.cosize(sK_layout)],\n 1024,\n ]\n sK1: cute.struct.Align[\n cute.struct.MemRange[self._dtype, cute.cosize(sK_layout)],\n 1024,\n ]\n # Epilogue staging cannot alias K here: with the prefetch both K\n # buffers stay live across the epilogue window.\n sMax: cute.struct.Align[\n cute.struct.MemRange[cutlass.Float32, 4 * self._m_block_size],\n 16,\n ]\n\n smem = cutlass.utils.SmemAllocator()\n storage = smem.allocate(SharedStorage)\n sQ = storage.sQ.get_tensor(sQ_layout)\n sK0 = storage.sK0.get_tensor(sK_layout)\n sK1 = storage.sK1.get_tensor(sK_layout)\n # Full-width layout on the same pointer: shapes the mma B fragment\n # only, no accesses go through it.\n sK_frag_ref = cute.make_tensor(sK0.iterator, self._make_sk_layout())\n sMax = storage.sMax.get_tensor(cute.make_layout(4 * self._m_block_size))\n\n universal_copy_bits = 128\n async_copy_elems = universal_copy_bits // self._dtype.width\n atom_async_copy = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n self._dtype,\n num_bits_per_copy=universal_copy_bits,\n )\n t_dim1 = 64 // async_copy_elems\n t_layout = cute.make_layout(\n (self._num_threads // t_dim1, t_dim1), stride=(t_dim1, 1)\n )\n v_layout = cute.make_layout((1, async_copy_elems))\n gmem_tiled_copy = cute.make_tiled_copy_tv(atom_async_copy, t_layout, v_layout)\n gmem_thr_copy = gmem_tiled_copy.get_slice(tidx)\n\n # First block's K fill goes out before the synchronous Q gather so the\n # cp.async flight time hides under it.\n if split_idx < num_kv_blocks:\n self._fill_k8_tile(\n gmem_tiled_copy,\n gmem_thr_copy,\n mK,\n mPageTable,\n batch_idx,\n kv_head,\n k_start,\n split_idx,\n seqlen_k,\n sK0,\n )\n\n self._gather_packed_q(mQ, sQ, q_start, kv_head, seqlen_q, tidx)\n\n # Warps side by side along N: each owns interleaved 8-column slices\n # of the 128 keys (32 columns total), so the fp8 K fragments are\n # converted once instead of replicated across the M-split warps.\n num_warps = self._num_threads // 32\n tiled_mma = cute.make_tiled_mma(\n warp.MmaF16BF16Op(self._dtype, cutlass.Float32, (16, 8, 16)),\n (1, num_warps, 1),\n permutation_mnk=(16, num_warps * 8, 16),\n )\n thr_mma = tiled_mma.get_slice(tidx)\n tSrQ = thr_mma.make_fragment_A(thr_mma.partition_A(sQ))\n tSrK = thr_mma.make_fragment_B(thr_mma.partition_B(sK_frag_ref))\n acc_S = cute.make_rmem_tensor(\n thr_mma.partition_shape_C((self._m_block_size, self._n_block_size)),\n cutlass.Float32,\n )\n\n smem_copy_atom_Q = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(transpose=False, num_matrices=4),\n self._dtype,\n )\n smem_tiled_copy_Q = cute.make_tiled_copy_A(smem_copy_atom_Q, tiled_mma)\n smem_thr_copy_Q = smem_tiled_copy_Q.get_slice(tidx)\n tSsQ = smem_thr_copy_Q.partition_S(sQ)\n tSrQ_copy_view = smem_thr_copy_Q.retile(tSrQ)\n\n # B loads are plain 4B reads, not ldmatrix: a warp's slice per\n # (n-tile, k-step pair) is only 8 rows x 16B, which the ldmatrix tiled\n # copies cannot partition. The convert splits each 4-byte pair into\n # the even/odd mma k-steps; the resulting K-axis column permutation is\n # mirrored by the Q gather, so Q K^T is unchanged.\n kpair = cute.make_rmem_tensor(cute.make_layout(2), self._dtype)\n kpair_u32 = cute.recast_tensor(kpair, cutlass.Uint32)\n tSrK_u32 = cute.recast_tensor(\n cute.make_tensor(tSrK.iterator, cute.make_layout(cute.cosize(tSrK.layout))),\n cutlass.Uint32,\n )\n warp_idx = tidx // 32\n\n cS = cute.make_identity_tensor((self._m_block_size, self._n_block_size))\n tScS_mn = self._make_acc_tensor_mn_view(thr_mma.partition_C(cS))\n acc_S_mn = self._make_acc_tensor_mn_view(acc_S)\n n_rows = cute.size(acc_S_mn.shape[0])\n\n # Gather stores are synchronous; order them before the Q fragment\n # reads. Q fragments load per k-step inside the block loop, since a\n # full-tile preload would cost a CTA of occupancy.\n self.cta_sync_barrier.arrive_and_wait()\n\n # Buffer selection is a pointer pick rather than cloned fill/consume\n # bodies: small-batch grids run one cold-I-cache CTA per SM, where the\n # duplicated code costs more than it saves.\n base0 = sK0.iterator.toint()\n buf_step = sK1.iterator.toint() - base0\n\n n_iter = cute.ceil_div(max_k_tiles, num_splits)\n for it in cutlass.range(n_iter):\n kv_block = split_idx + it * num_splits\n if kv_block < num_kv_blocks:\n par = it % 2\n sK_cur = cute.make_tensor(\n cute.make_ptr(\n self._dtype,\n base0 + par * buf_step,\n cute.AddressSpace.smem,\n assumed_align=1024,\n ),\n sK_layout,\n )\n sK_nxt = cute.make_tensor(\n cute.make_ptr(\n self._dtype,\n base0 + (1 - par) * buf_step,\n cute.AddressSpace.smem,\n assumed_align=1024,\n ),\n sK_layout,\n )\n # Prefetch the next block into the idle buffer; its loads fly\n # under this block's mma and epilogue. Two commit groups go\n # out either way (empty ones at the tail), which keeps the\n # wait_group counts below static.\n nxt_block = kv_block + num_splits\n if nxt_block < num_kv_blocks:\n self._fill_k8_tile(\n gmem_tiled_copy,\n gmem_thr_copy,\n mK,\n mPageTable,\n batch_idx,\n kv_head,\n k_start,\n nxt_block,\n seqlen_k,\n sK_nxt,\n )\n else:\n cute.arch.cp_async_commit_group()\n cute.arch.cp_async_commit_group()\n\n # S = Q K^T (unscaled), consumed one 64-key half behind each\n # fill group so the mma starts before the tile finishes\n # landing.\n acc_S.fill(0.0)\n for h in cutlass.range_constexpr(2):\n cute.arch.cp_async_wait_group(3 - h)\n self.cta_sync_barrier.arrive_and_wait()\n self._consume_k8_half(\n h,\n sK_cur,\n smem_tiled_copy_Q,\n tSsQ,\n tSrQ,\n tSrQ_copy_view,\n tiled_mma,\n tSrK,\n tSrK_u32,\n kpair,\n kpair_u32,\n acc_S,\n )\n\n # Every warp's K fragment loads must land before the next\n # iteration's prefetch overwrites this buffer.\n self.cta_sync_barrier.arrive_and_wait()\n\n # Per-warp row maxes over the warp's 32 key columns, staged to\n # smem; one thread per row then joins the 4 warps and stores.\n for r in cutlass.range_constexpr(n_rows):\n row = tScS_mn[r, 0][0]\n token = row % self._pack_q_len\n if cutlass.const_expr(self._is_causal):\n col_limit = cutlass.min(\n token + mQOffset[batch_idx] + 1, seqlen_k\n )\n else:\n col_limit = seqlen_k\n for c in cutlass.range_constexpr(cute.size(tScS_mn.shape[1])):\n k_pos = kv_block * self._n_block_size + tScS_mn[0, c][1]\n if cute.elem_less(col_limit, k_pos + 1):\n acc_S_mn[r, c] = -cutlass.Float32.inf\n tile_max = (\n acc_S_mn[r, None]\n .load()\n .reduce(cute.ReductionOp.MAX, -cutlass.Float32.inf, 0)\n )\n tile_max = self._threadquad_reduce_max(tile_max)\n if tidx % 4 == 0:\n sMax[row * 4 + warp_idx] = tile_max\n self.cta_sync_barrier.arrive_and_wait()\n if tidx < self._m_block_size:\n row_max = sMax[tidx * 4]\n for w in cutlass.range_constexpr(1, 4):\n row_max = cute.arch.fmax(row_max, sMax[tidx * 4 + w])\n token_f = tidx % self._pack_q_len\n head_f = kv_head * self._qhead_per_kv + tidx // self._pack_q_len\n if cute.elem_less(token_f, seqlen_q):\n mMaxScore[head_f, kv_block, q_start + token_f] = row_max\n elif kv_block < max_k_tiles:\n # Padding tile in [num_kv_blocks, max_k_tiles) -> -inf, as in\n # the packed kernel.\n for r in cutlass.range_constexpr(n_rows):\n row2 = tScS_mn[r, 0][0]\n token2 = row2 % self._pack_q_len\n local_head2 = row2 // self._pack_q_len\n head2 = kv_head * self._qhead_per_kv + local_head2\n if cute.elem_less(token2, seqlen_q):\n mMaxScore[\n head2, kv_block, q_start + token2\n ] = -cutlass.Float32.inf\n\n @cute.jit\n def _fill_k8_tile(\n self,\n gmem_tiled_copy,\n gmem_thr_copy,\n mK: cute.Tensor,\n mPageTable: cute.Tensor,\n batch_idx: cutlass.Int32,\n kv_head: cutlass.Int32,\n k_start: cutlass.Int32,\n kv_block: cutlass.Int32,\n seqlen_k: cutlass.Int32,\n sK_buf: cute.Tensor,\n ):\n \"\"\"Issue one raw-e4m3 K tile's cp.async fill as two commit groups\n (keys 0-63 and 64-127), matching the consumer's half order.\"\"\"\n kw = self._head_dim // 2\n tKsK = gmem_thr_copy.partition_D(sK_buf)\n cKV = cute.make_identity_tensor((self._n_block_size, kw))\n tKVcKV = gmem_thr_copy.partition_S(cKV)\n if cutlass.const_expr(self._paged):\n page = mPageTable[batch_idx, kv_block]\n gK = cute.local_tile(\n mK[page, kv_head, None, None], (self._n_block_size, kw), (None, 0)\n )\n tKgK = gmem_thr_copy.partition_S(gK)[None, None, None, 0]\n else:\n mK_h = cute.domain_offset((k_start, 0), mK[None, kv_head, None])\n gK = cute.local_tile(mK_h, (self._n_block_size, kw), (None, 0))\n tKgK = gmem_thr_copy.partition_S(gK)[None, None, None, kv_block]\n n_passes = cute.size(tKsK.shape[1])\n for n in cutlass.range_constexpr(n_passes):\n if (kv_block * self._n_block_size + tKVcKV[0, n, 0][0]) < seqlen_k:\n cute.copy(gmem_tiled_copy, tKgK[None, n, None], tKsK[None, n, None])\n else:\n tKsK[None, n, None].fill(0)\n if n == n_passes // 2 - 1:\n cute.arch.cp_async_commit_group()\n cute.arch.cp_async_commit_group()\n\n @cute.jit\n def _consume_k8_half(\n self,\n half: cutlass.Constexpr,\n sK_buf: cute.Tensor,\n smem_tiled_copy_Q,\n tSsQ: cute.Tensor,\n tSrQ: cute.Tensor,\n tSrQ_copy_view: cute.Tensor,\n tiled_mma,\n tSrK: cute.Tensor,\n tSrK_u32: cute.Tensor,\n kpair: cute.Tensor,\n kpair_u32: cute.Tensor,\n acc_S: cute.Tensor,\n ):\n \"\"\"Convert-and-mma over one 64-key half (n-tiles ``2*half`` and\n ``2*half + 1``). Q fragments load just in time so ptxas keeps the\n per-thread A footprint at one k-step.\"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n # Fragment geometry of the m16n8k16 B atom: lane covers key row\n # n = 32*nt + 8*warp + lane//4 and k16 pairs at 2*(lane%4) (+8).\n nb_row = 8 * (tidx // 32) + (tidx % 32) // 4\n m4 = tidx % 4\n # This half's slice of the acc and B fragments (n-tile mode cut to 2),\n # so the gemm keeps the full-rank form cute.gemm requires.\n acc_h = cute.make_tensor(\n acc_S.iterator + 2 * half * acc_S.layout.stride[2],\n cute.make_layout(\n (acc_S.layout.shape[0], acc_S.layout.shape[1], 2),\n stride=acc_S.layout.stride,\n ),\n )\n tSrK_h = cute.make_tensor(\n tSrK.iterator + 2 * half * tSrK.layout.stride[1],\n cute.make_layout(\n (tSrK.layout.shape[0], 2, tSrK.layout.shape[2]),\n stride=tSrK.layout.stride,\n ),\n )\n for kk8 in cutlass.range_constexpr(self._head_dim // 32):\n for nt in cutlass.range_constexpr(2 * half, 2 * half + 2):\n n_row = 32 * nt + nb_row\n for g in cutlass.range_constexpr(2):\n src = cute.local_tile(\n sK_buf[n_row, None], (2,), (8 * kk8 + 4 * g + m4,)\n )\n cute.autovec_copy(src, kpair)\n if cutlass.const_expr(self._dtype is cutlass.BFloat16):\n lo, hi = _fp8x4_to_bf16x4(kpair_u32[0])\n else:\n lo, hi = _fp8x4_to_f16x4(kpair_u32[0])\n # All four e4m3 of this u32 belong to canonical 16-column\n # group g, so both converted pairs go into mma step\n # 2*kk8 + g: each product lands in the same instruction as\n # the reference schedules, keeping the result bit-identical.\n kk = 2 * kk8 + g\n d0 = cute.crd2idx(((0, 0), nt, kk), tSrK.layout)\n d1 = cute.crd2idx(((0, 1), nt, kk), tSrK.layout)\n tSrK_u32[d0 // 2] = lo\n tSrK_u32[d1 // 2] = hi\n for s in cutlass.range_constexpr(2):\n kk = 2 * kk8 + s\n cute.copy(\n smem_tiled_copy_Q,\n tSsQ[None, None, kk],\n tSrQ_copy_view[None, None, kk],\n )\n cute.gemm(\n tiled_mma,\n acc_h,\n tSrQ[None, None, kk],\n tSrK_h[None, None, kk],\n acc_h,\n )\n\n def _make_sk8_layout(self):\n \"\"\"K smem layout for the raw e4m3 bytes viewed as 16-bit pairs: half\n the width of the converted tile, same swizzle.\"\"\"\n atom = cute.make_composed_layout(\n cute.make_swizzle(3, 3, 3),\n 0,\n cute.make_layout((8, 64), stride=(64, 1)),\n )\n return cute.tile_to_shape(\n atom, (self._n_block_size, self._head_dim // 2), (0, 1)\n )\n\n @cute.jit\n def _gather_packed_q(self, mQ, sQ, q_start, kv_head, seqlen_q, tidx):\n \"\"\"Gather the packed Q tile into swizzled smem, column-permuted to\n match the converted K fragments: within each 32-wide block, column\n ``16g + 4m + 2h + j`` (two-bit ``m``, one-bit rest) moves to slot\n ``16g + 8h + 2m + j``, where ``g = (c8 % 4) // 2``,\n ``m = 2 * (c8 % 2) + i // 2``, and ``h = i % 2`` below. Rows past\n seqlen_q are zero-filled; the epilogue masks them.\"\"\"\n elems = 128 // self._dtype.width\n chunks = self._head_dim // elems\n total = self._m_block_size * chunks\n frag = cute.make_rmem_tensor(cute.make_layout(elems), self._dtype)\n for it in cutlass.range_constexpr(total // self._num_threads):\n e = tidx + it * self._num_threads\n r = e // chunks\n c8 = e % chunks\n local_head = r // self._pack_q_len\n token = r % self._pack_q_len\n head = kv_head * self._qhead_per_kv + local_head\n if cute.elem_less(token, seqlen_q):\n gQ_chunk = cute.local_tile(\n mQ[q_start + token, head, None], (elems,), (c8,)\n )\n frag.store(gQ_chunk.load())\n # Chunk column a = 8*c8 + 2*i + j goes to permuted pair\n # position p2 (see the docstring); pairs stay contiguous.\n for i in cutlass.range_constexpr(4):\n pr = cute.make_tensor(frag.iterator + 2 * i, cute.make_layout(2))\n p2 = (\n 16 * (c8 // 4)\n + 8 * ((c8 % 4) // 2)\n + 4 * (i % 2)\n + 2 * (c8 % 2)\n + i // 2\n )\n dst = cute.local_tile(sQ[r, None], (2,), (p2,))\n cute.autovec_copy(pr, dst)\n else:\n sQ_chunk0 = cute.local_tile(sQ[r, None], (elems,), (c8,))\n sQ_chunk0.fill(0)\n\n\n# `createpolicy.fractional.L2::evict_first.b64` at fraction 1.0: K tiles\n# are read once per CTA, so they should not evict resident lines.\n_TMA_EVICT_FIRST = cutlass.Int64(0x12F0000000000000)\n\n\n@dsl_user_op\ndef _mma_m16n8k16(a: cute.Tensor, b: cute.Tensor, c: cute.Tensor, *, loc=None, ip=None):\n \"\"\"One m16n8k16 f16/bf16 mma.sync with f32 accumulate; a is 4 u32, b is\n 2 u32, c is 4 f32 (read-modify-write).\"\"\"\n ab_ty = \"bf16\" if a.element_type is cutlass.BFloat16 else \"f16\"\n a_u32 = cute.recast_tensor(a, cutlass.Uint32)\n b_u32 = cute.recast_tensor(b, cutlass.Uint32)\n out = llvm.inline_asm(\n llvm.StructType.get_literal([cutlass.Float32.mlir_type] * 4),\n [a_u32[i].ir_value(loc=loc, ip=ip) for i in range(4)]\n + [b_u32[i].ir_value(loc=loc, ip=ip) for i in range(2)]\n + [c[i].ir_value(loc=loc, ip=ip) for i in range(4)],\n f\"mma.sync.aligned.m16n8k16.row.col.f32.{ab_ty}.{ab_ty}.f32 \"\n \"{$0, $1, $2, $3}, {$4, $5, $6, $7}, {$8, $9}, {$10, $11, $12, $13};\",\n \"=f,=f,=f,=f,r,r,r,r,r,r,f,f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n loc=loc,\n ip=ip,\n )\n for i in range(4):\n c[i] = cutlass.Float32(\n llvm.extractvalue(cutlass.Float32.mlir_type, out, [i], loc=loc, ip=ip)\n )\n\n\n@cute.jit\ndef _tma_copy_g2s(atom, gmem, smem, mbar, cache_policy=None):\n \"\"\"One bulk-tensor TMA G2S copy (call without elect_one; the atom elects).\"\"\"\n s_part, g_part = cpasync.tma_partition(\n atom,\n 0,\n cute.make_layout(1),\n cute.group_modes(smem, 0),\n cute.group_modes(gmem, 0),\n )\n cute.copy(atom, g_part, s_part, tma_bar_ptr=mbar, cache_policy=cache_policy)\n\n\nclass MsaProxyScoreDecodeKeyMajorSm12x:\n \"\"\"Key-major packed-decode schedule for small fused-row tiles\n (group_size * pack_q_len <= 32): the score GEMM runs as K Q^T with the\n 128 keys as the MMA M dimension and the fused (head, token) query rows as\n N. Each of the 4 MMA warps owns 32 contiguous keys, so ldmatrix is legal\n on both operands and the Q fragments load once per CTA and stay in\n registers across KV blocks. A fifth warp is a TMA producer feeding a\n two-stage mbarrier pipeline (Q's smem aliases K stage 0), which leaves\n two intra-CTA barriers per block. The low per-CTA fixed cost (no Q\n gather, no fill barriers, no per-step Q reloads) is what wins on the\n one-block-per-CTA grids that split-K produces at small batch.\n \"\"\"\n\n _BLOCK_K = 128\n _BAR_MMA = 1\n _NUM_STAGES = 2\n\n def __init__(\n self,\n head_dim: int = 128,\n group_size: int = 4,\n pack_q_len: int = 4,\n is_causal: bool = True,\n paged: bool = False,\n kv_fp8: bool = False,\n q_fp8: bool = False,\n qoff_default: bool = True,\n ):\n if head_dim != 128:\n raise ValueError(\"only head_dim == 128 is supported\")\n if group_size * pack_q_len > 32:\n raise ValueError(\"group_size * pack_q_len must be <= 32\")\n if q_fp8 and not kv_fp8:\n raise ValueError(\"q_fp8 requires kv_fp8\")\n self._head_dim = head_dim\n self._group = group_size\n self._pack_q_len = pack_q_len\n self._is_causal = is_causal\n self._paged = paged\n self._kv_fp8 = kv_fp8\n self._q_fp8 = q_fp8\n # Right-aligned decode (q_offset=None) computes the causal offset\n # in-kernel, skipping the host-side offset-tensor build kernels that\n # dominate at batch 1.\n self._qoff_default = qoff_default\n self._block_q = group_size * pack_q_len\n self._q_tiles = (self._block_q + 7) // 8\n self._num_threads = 32 * 5\n\n @cute.jit\n def __call__(\n self,\n mQ: cute.Tensor,\n mK: cute.Tensor,\n mPageTable: cute.Tensor,\n mMaxScore: cute.Tensor,\n mCuQ: cute.Tensor,\n mCuK: cute.Tensor,\n mQOffset: cute.Tensor,\n max_seqlen_q: cutlass.Int32,\n batch_size: cutlass.Int32,\n num_qo_heads: cutlass.Int32,\n max_k_tiles: cutlass.Int32,\n num_splits: cutlass.Int32,\n stream: cuda.CUstream,\n ):\n if cutlass.const_expr(\n not (\n mQ.element_type == cutlass.Float16\n or mQ.element_type == cutlass.BFloat16\n )\n ):\n raise TypeError(\"Only Float16 or BFloat16 q is supported\")\n self._dtype: Type[cutlass.Numeric] = mQ.element_type\n\n dtype = self._dtype\n hd = self._head_dim\n pack = self._pack_q_len\n group = self._group\n block_q = self._block_q\n elems = 128 * 8 // dtype.width\n tma_g2s = cpasync.CopyBulkTensorTileG2SOp()\n swizzle_128b = cute.make_swizzle(3, 4, 3)\n\n # fp8 operands arrive as 16-bit views of the e4m3 bytes (half\n # head_dim), so their tiles are half as wide.\n qw = hd // 2 if cutlass.const_expr(self._q_fp8) else hd\n sQ_layout = cute.make_composed_layout(\n swizzle_128b,\n 0,\n cute.make_layout(\n (pack, group, (elems, qw // elems)),\n stride=(elems, pack * elems, (1, block_q * elems)),\n ),\n )\n q_tma = cpasync.make_tiled_tma_atom(\n tma_g2s,\n cute.logical_divide(mQ, (None, None, elems)),\n sQ_layout,\n cta_tiler=(pack, group, qw),\n )\n\n kw = hd // 2 if cutlass.const_expr(self._kv_fp8) else hd\n if cutlass.const_expr(self._paged):\n sK_layout = cute.make_composed_layout(\n swizzle_128b,\n 0,\n cute.make_layout(\n (1, 1, self._BLOCK_K, (elems, kw // elems), self._NUM_STAGES),\n stride=(\n 0,\n 0,\n elems,\n (1, self._BLOCK_K * elems),\n self._BLOCK_K * kw,\n ),\n ),\n )\n k_tma = cpasync.make_tiled_tma_atom(\n tma_g2s,\n cute.logical_divide(mK, (None, None, None, elems)),\n sK_layout,\n cta_tiler=(1, 1, self._BLOCK_K, kw),\n )\n else:\n sK_layout = cute.make_composed_layout(\n swizzle_128b,\n 0,\n cute.make_layout(\n (self._BLOCK_K, 1, (elems, kw // elems), self._NUM_STAGES),\n stride=(\n elems,\n 0,\n (1, self._BLOCK_K * elems),\n self._BLOCK_K * kw,\n ),\n ),\n )\n k_tma = cpasync.make_tiled_tma_atom(\n tma_g2s,\n cute.logical_divide(mK, (None, None, elems)),\n sK_layout,\n cta_tiler=(self._BLOCK_K, 1, kw),\n )\n\n self.kernel(\n q_tma,\n k_tma,\n mPageTable,\n mMaxScore,\n mCuQ,\n mCuK,\n mQOffset,\n max_k_tiles,\n num_splits,\n ).launch(\n grid=(num_splits, batch_size, num_qo_heads // group),\n block=[self._num_threads, 1, 1],\n stream=stream,\n use_pdl=True,\n )\n\n @cute.kernel\n def kernel(\n self,\n q_tma: cpasync.TmaInfo,\n k_tma: cpasync.TmaInfo,\n mPageTable: cute.Tensor,\n mMaxScore: cute.Tensor,\n mCuQ: cute.Tensor,\n mCuK: cute.Tensor,\n mQOffset: cute.Tensor,\n max_k_tiles: cutlass.Int32,\n num_splits: cutlass.Int32,\n ):\n split_idx, batch_idx, kv_head = cute.arch.block_idx()\n warp_id = cute.arch.make_warp_uniform(cute.arch.warp_idx())\n lane_id = cute.arch.lane_idx()\n\n dtype = self._dtype\n hd = self._head_dim\n pack = self._pack_q_len\n group = self._group\n block_q = self._block_q\n block_k = self._BLOCK_K\n num_stages = self._NUM_STAGES\n q_tiles = self._q_tiles\n epi_q = q_tiles * 8\n elems = 128 // dtype.width\n mma_k = 32 * 8 // dtype.width\n\n kw = hd // 2 if self._kv_fp8 else hd\n qw = hd // 2 if self._q_fp8 else hd\n\n smem = cutlass.utils.SmemAllocator()\n sK_full = smem.allocate_tensor(\n dtype,\n k_tma.smem_layout.outer,\n byte_alignment=128,\n swizzle=k_tma.smem_layout.inner,\n )\n if cutlass.const_expr(self._paged):\n sK = sK_full[0, 0, None, None, None]\n else:\n sK = sK_full[None, 0, None, None]\n # Q's smem aliases K stage 0: the Q fragments are register-resident\n # before the first K tile is allowed in (empty-mbarrier order).\n sQ_tma = cute.make_tensor(\n sK[None, None, 0].iterator, layout=q_tma.smem_layout.outer\n )\n q_tma_elems = 128 * 8 // dtype.width\n sQ = cute.coalesce(\n cute.group_modes(sQ_tma, 0, 2),\n target_profile=(block_q, (q_tma_elems, qw // q_tma_elems)),\n )\n epi_buffer = smem.allocate_tensor(cutlass.Float32, cute.make_layout((epi_q, 4)))\n tma_full_mbar = smem.allocate_array(cutlass.Int64, num_stages)\n tma_empty_mbar = smem.allocate_array(cutlass.Int64, num_stages)\n\n n_iter = cute.ceil_div(max_k_tiles, num_splits)\n\n if warp_id == 0:\n with cute.arch.elect_one():\n for i in cutlass.range_constexpr(num_stages):\n cute.arch.mbarrier_init(tma_full_mbar + i, 1)\n cute.arch.mbarrier_init(tma_empty_mbar + i, 128)\n cute.arch.mbarrier_init_fence()\n elif warp_id == 1:\n cpasync.prefetch_descriptor(q_tma.atom)\n cpasync.prefetch_descriptor(k_tma.atom)\n cute.arch.sync_threads()\n\n # PDL: the preceding kernel may still be writing the seqlen tensors,\n # so they are read only after the dependency wait (the setup above is\n # independent of global data and can overlap).\n cute.arch.griddepcontrol_wait()\n cute.arch.griddepcontrol_launch_dependents()\n\n q_start = mCuQ[batch_idx]\n seqlen_q = mCuQ[batch_idx + 1] - q_start\n if cutlass.const_expr(self._paged):\n k_start = cutlass.Int32(0)\n seqlen_k = mCuK[batch_idx]\n else:\n k_start = mCuK[batch_idx]\n seqlen_k = mCuK[batch_idx + 1] - k_start\n num_kv_blocks = cute.ceil_div(seqlen_k, block_k)\n\n if split_idx < num_kv_blocks:\n if warp_id == 4:\n # TMA producer warp: Q once, then one K tile per valid block.\n tma_stage = 0\n tma_parity = 1\n\n gq_tile = cute.local_tile(\n cute.domain_offset((q_start, kv_head * group, 0), q_tma.tma_tensor),\n tiler=(pack, group, qw),\n coord=(0, 0, 0),\n )\n cute.arch.mbarrier_wait(tma_empty_mbar, tma_parity)\n with cute.arch.elect_one():\n q_size = block_q * qw * (dtype.width // 8)\n cute.arch.mbarrier_arrive_and_expect_tx(tma_full_mbar, q_size)\n _tma_copy_g2s(q_tma.atom, gq_tile, sQ_tma, tma_full_mbar)\n\n tma_stage = (tma_stage + 1) % num_stages\n if tma_stage == 0:\n tma_parity ^= 1\n\n for it in cutlass.range(n_iter):\n kv_block = split_idx + it * num_splits\n if kv_block < num_kv_blocks:\n if cutlass.const_expr(self._paged):\n page = mPageTable[batch_idx, kv_block]\n gk_tile = k_tma.tma_tensor[page, kv_head, None, None]\n else:\n gk_tile = cute.local_tile(\n cute.domain_offset(\n (k_start, kv_head, 0), k_tma.tma_tensor\n ),\n tiler=(block_k, 1, kw),\n coord=(kv_block, 0, 0),\n )\n k_mbar = tma_full_mbar + tma_stage\n\n cute.arch.mbarrier_wait(tma_empty_mbar + tma_stage, tma_parity)\n with cute.arch.elect_one():\n k_size = block_k * kw * (dtype.width // 8)\n cute.arch.mbarrier_arrive_and_expect_tx(k_mbar, k_size)\n _tma_copy_g2s(\n k_tma.atom,\n gk_tile,\n sK[None, None, tma_stage],\n k_mbar,\n cache_policy=_TMA_EVICT_FIRST,\n )\n\n tma_stage = (tma_stage + 1) % num_stages\n if tma_stage == 0:\n tma_parity ^= 1\n\n else:\n # MMA warps: each owns 32 contiguous keys across all q rows.\n sK_warp = cute.local_tile(sK, (32, kw, num_stages), (warp_id, 0, 0))\n sQ_ldsm = cute.zipped_divide(sQ, (8, cute.make_layout((elems, 4))))\n sQ_ldsm = sQ_ldsm[(lane_id % 8, (None, lane_id // 8)), None]\n\n ldsm_atom = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(num_matrices=4), dtype\n )\n\n rQ = cute.make_rmem_tensor(\n ((elems // 2, 2), qw // (mma_k * 2), q_tiles), dtype\n )\n rC = cute.make_rmem_tensor((4, 2, q_tiles), cutlass.Float32)\n sK_ldsm = cute.zipped_divide(\n sK_warp, (16, cute.make_layout((elems, 2)), 1)\n )\n sK_ldsm = sK_ldsm[(lane_id % 16, (None, lane_id // 16), 0), None]\n rK = cute.make_rmem_tensor((elems, 2, kw // mma_k), dtype)\n if cutlass.const_expr(self._kv_fp8):\n # ldmatrix on the 16-bit view hands each lane 4 consecutive\n # e4m3 per u32, so splitting each converted u32 into its\n # low and high pair yields the two k16 A-fragments as pure\n # register renames. Q is permuted once below to the same\n # column order.\n rK_u32 = cute.recast_tensor(rK, cutlass.Uint32)\n rK_lo = cute.make_rmem_tensor((elems,), dtype)\n rK_hi = cute.make_rmem_tensor((elems,), dtype)\n rK_lo_u32 = cute.recast_tensor(rK_lo, cutlass.Uint32)\n rK_hi_u32 = cute.recast_tensor(rK_hi, cutlass.Uint32)\n rQp = cute.make_rmem_tensor((4, kw // mma_k, q_tiles, 2), dtype)\n rQp_u32 = cute.recast_tensor(rQp, cutlass.Uint32)\n\n if warp_id == 0:\n cute.arch.mbarrier_wait(tma_full_mbar, 0)\n cute.arch.barrier(barrier_id=self._BAR_MMA, number_of_threads=128)\n for q in cutlass.range_constexpr(q_tiles):\n cute.copy(ldsm_atom, sQ_ldsm[None, (q, None)], rQ[None, None, q])\n cute.arch.mbarrier_arrive(tma_empty_mbar)\n\n if cutlass.const_expr(self._kv_fp8):\n rQ_u32 = cute.recast_tensor(rQ, cutlass.Uint32)\n if cutlass.const_expr(self._q_fp8):\n # Raw e4m3 q gets the same fp8 column order as K from\n # ldmatrix, so the split converts already are the\n # matching B-fragments.\n for g in cutlass.range_constexpr(kw // mma_k):\n for n in cutlass.range_constexpr(q_tiles):\n for j in cutlass.range_constexpr(2):\n if cutlass.const_expr(dtype is cutlass.BFloat16):\n q_lo, q_hi = _fp8x4_to_bf16x4(\n rQ_u32[(j, g % 2), g // 2, n]\n )\n else:\n q_lo, q_hi = _fp8x4_to_f16x4(\n rQ_u32[(j, g % 2), g // 2, n]\n )\n rQp_u32[j, g, n, 0] = q_lo\n rQp_u32[j, g, n, 1] = q_hi\n else:\n # One-time cross-lane permute of the bf16/f16 Q\n # B-fragments into the fp8 K column order: quad\n # position q4 needs columns 4*q4..4*q4+3, which sit as\n # u32 pairs on quad lanes 2*(q4%2) and 2*(q4%2)+1 of\n # the canonical fragments.\n q4 = lane_id % 4\n src_lo = lane_id - q4 + 2 * (q4 % 2)\n sel_mask = cutlass.Uint32(0) - cutlass.Uint32(q4 // 2)\n for g in cutlass.range_constexpr(kw // mma_k):\n for n in cutlass.range_constexpr(q_tiles):\n for h in cutlass.range_constexpr(2):\n src = src_lo + h\n p0 = cute.arch.shuffle_sync(\n rQ_u32[(0, 0), g, n], src\n )\n p1 = cute.arch.shuffle_sync(\n rQ_u32[(1, 0), g, n], src\n )\n p2 = cute.arch.shuffle_sync(\n rQ_u32[(0, 1), g, n], src\n )\n p3 = cute.arch.shuffle_sync(\n rQ_u32[(1, 1), g, n], src\n )\n rQp_u32[0, g, n, h] = p0 ^ ((p0 ^ p1) & sel_mask)\n rQp_u32[1, g, n, h] = p2 ^ ((p2 ^ p3) & sel_mask)\n\n tma_stage = 1 % num_stages\n tma_parity = 0\n if tma_stage == 0:\n tma_parity ^= 1\n\n if cutlass.const_expr(self._is_causal):\n if cutlass.const_expr(self._qoff_default):\n q_off = seqlen_k - seqlen_q\n else:\n q_off = mQOffset[batch_idx]\n else:\n q_off = cutlass.Int32(0)\n\n for it in cutlass.range(n_iter):\n kv_block = split_idx + it * num_splits\n if kv_block < num_kv_blocks:\n rC.fill(0.0)\n\n if warp_id == 0:\n cute.arch.mbarrier_wait(\n tma_full_mbar + tma_stage, tma_parity\n )\n cute.arch.barrier(\n barrier_id=self._BAR_MMA, number_of_threads=128\n )\n\n if cutlass.const_expr(self._kv_fp8):\n # The lower/upper regrouping puts different\n # products in each mma than the bf16 schedule.\n # With e4m3 operands every f32 dot term is exact,\n # so the result still matches dequantized K\n # bit-for-bit.\n for k in cutlass.range_constexpr(kw // mma_k):\n cute.copy(\n ldsm_atom,\n sK_ldsm[None, (None, k, tma_stage)],\n rK[None, None, k],\n )\n for m in cutlass.range_constexpr(2):\n for i in cutlass.range_constexpr(elems // 2):\n if cutlass.const_expr(\n dtype is cutlass.BFloat16\n ):\n lo, hi = _fp8x4_to_bf16x4(rK_u32[i, m, k])\n else:\n lo, hi = _fp8x4_to_f16x4(rK_u32[i, m, k])\n rK_lo_u32[i] = lo\n rK_hi_u32[i] = hi\n for n in cutlass.range_constexpr(q_tiles):\n _mma_m16n8k16(\n rK_lo,\n rQp[None, k, n, 0],\n rC[None, m, n],\n )\n _mma_m16n8k16(\n rK_hi,\n rQp[None, k, n, 1],\n rC[None, m, n],\n )\n else:\n for k in cutlass.range_constexpr(hd // mma_k):\n cute.copy(\n ldsm_atom,\n sK_ldsm[None, (None, k, tma_stage)],\n rK[None, None, k],\n )\n for m in cutlass.range_constexpr(2):\n for n in cutlass.range_constexpr(q_tiles):\n _mma_m16n8k16(\n rK[None, m, k],\n rQ[(None, k % 2), k // 2, n],\n rC[None, m, n],\n )\n\n cute.arch.mbarrier_arrive(tma_empty_mbar + tma_stage)\n\n # Mask keys past the causal limit and the sequence\n # tail (TMA zero-fills out-of-bounds rows).\n k_base = kv_block * block_k + warp_id * 32\n for q in cutlass.range_constexpr(q_tiles):\n for i in cutlass.range_constexpr(4):\n for j in cutlass.range_constexpr(2):\n col = q * 8 + (lane_id % 4) * 2 + j\n token = col % pack\n if cutlass.const_expr(self._is_causal):\n col_limit = cutlass.min(\n token + q_off + 1, seqlen_k\n )\n else:\n col_limit = seqlen_k\n k_pos = k_base + i * 8 + lane_id // 4\n if cute.elem_less(col_limit, k_pos + 1):\n rC[q * 8 + i * 2 + j] = -cutlass.Float32.inf\n\n for q in cutlass.range_constexpr(q_tiles):\n r0 = rC[q * 8 + 0]\n r1 = rC[q * 8 + 1]\n for i in cutlass.range_constexpr(1, 4):\n r0 = cute.arch.fmax(r0, rC[q * 8 + i * 2 + 0])\n r1 = cute.arch.fmax(r1, rC[q * 8 + i * 2 + 1])\n for i in cutlass.range_constexpr(3):\n off = 4 << i\n r0 = cute.arch.fmax(\n r0,\n cute.arch.shuffle_sync_bfly(\n r0, offset=off, mask=-1, mask_and_clamp=31\n ),\n )\n r1 = cute.arch.fmax(\n r1,\n cute.arch.shuffle_sync_bfly(\n r1, offset=off, mask=-1, mask_and_clamp=31\n ),\n )\n if lane_id * 2 < 8:\n epi_buffer[q * 8 + lane_id * 2 + 0, warp_id] = r0\n epi_buffer[q * 8 + lane_id * 2 + 1, warp_id] = r1\n cute.arch.barrier(\n barrier_id=self._BAR_MMA, number_of_threads=128\n )\n\n if warp_id == 0:\n head_local = lane_id // pack\n token_f = lane_id - head_local * pack\n if lane_id < block_q and cute.elem_less(token_f, seqlen_q):\n score = epi_buffer[lane_id, 0]\n for i in cutlass.range_constexpr(1, 4):\n score = cute.arch.fmax(\n score, epi_buffer[lane_id, i]\n )\n mMaxScore[\n kv_head * group + head_local,\n kv_block,\n q_start + token_f,\n ] = score\n\n tma_stage = (tma_stage + 1) % num_stages\n if tma_stage == 0:\n tma_parity ^= 1\n elif kv_block < max_k_tiles:\n # Padding tile in [num_kv_blocks, max_k_tiles) -> -inf.\n if warp_id == 0:\n head_p = lane_id // pack\n token_p = lane_id - head_p * pack\n if lane_id < block_q and cute.elem_less(token_p, seqlen_q):\n mMaxScore[\n kv_head * group + head_p,\n kv_block,\n q_start + token_p,\n ] = -cutlass.Float32.inf\n elif split_idx < max_k_tiles:\n # CTA with no valid block: only padding stores remain.\n if warp_id == 0:\n for it in cutlass.range(n_iter):\n kv_block = split_idx + it * num_splits\n if kv_block < max_k_tiles:\n head_p2 = lane_id // pack\n token_p2 = lane_id - head_p2 * pack\n if lane_id < block_q and cute.elem_less(token_p2, seqlen_q):\n mMaxScore[\n kv_head * group + head_p2,\n kv_block,\n q_start + token_p2,\n ] = -cutlass.Float32.inf\n\n\nclass MsaProxyScoreDecodeStreamSm12x:\n \"\"\"Single-token decode schedule: at one query token the score tile is only\n group_size rows, too skinny for the MMA atom, so K streams straight from\n GMEM to registers (no smem, no tensor cores) and dim-parallel lanes reduce\n each key's dot products with warp shuffles.\n\n Deliberately q_len == 1 only: the shuffle+FMA phase scales with q_len\n while the K loads don't, and that rising arithmetic intensity is exactly\n what starts paying for the tensor cores. MTP stays on the packed-MMA\n schedules.\"\"\"\n\n _NUM_WARPS = 8\n _KEYS_PER_ITER = 2 # 32 lanes = 2 keys x 16 dim-slice lanes\n\n def __init__(\n self,\n head_dim: int = 128,\n group_size: int = 4,\n is_causal: bool = True,\n paged: bool = False,\n kv_fp8: bool = False,\n qoff_default: bool = True,\n ):\n if head_dim != 128:\n raise ValueError(\"only head_dim == 128 is supported\")\n # Q and the running maxes live in registers per lane; past 8 heads the\n # footprint approaches the spill point, so larger groups keep the\n # packed MMA schedule.\n if not 1 <= group_size <= 8:\n raise ValueError(\"group_size must be in [1, 8]\")\n self._head_dim = head_dim\n self._G = group_size\n self._is_causal = is_causal\n self._paged = paged\n self._kv_fp8 = kv_fp8\n # Right-aligned decode (q_offset=None): the single query sits at\n # seqlen_k - 1, so the causal limit is just seqlen_k and no offset\n # tensor is needed.\n self._qoff_default = qoff_default\n self._blk_kv = 128\n self._num_threads = self._NUM_WARPS * 32\n self._keys_per_warp = self._blk_kv // self._NUM_WARPS\n self._num_iters = self._keys_per_warp // self._KEYS_PER_ITER\n\n @cute.jit\n def __call__(\n self,\n mQ: cute.Tensor, # (total_q, Hq, d)\n mK: cute.Tensor, # (total_k, Hkv, d) flat | (pages, Hkv, 128, d) paged\n mPageTable: cute.Tensor, # (B, max_pages) int32 (dummy if flat)\n mMaxScore: cute.Tensor, # (Hq, max_k_tiles, total_q) f32\n mCuQ: cute.Tensor, # (B + 1,) int32 (unused: one q token per request)\n mCuK: cute.Tensor, # (B + 1,) int32\n mQOffset: cute.Tensor, # (B,) int32 causal offset (MSA q_offset)\n max_seqlen_q: cutlass.Int32, # 1 (kept for signature parity)\n batch_size: cutlass.Int32,\n num_qo_heads: cutlass.Int32,\n max_k_tiles: cutlass.Int32,\n num_splits: cutlass.Int32, # unused: the grid is already per KV block\n stream: cuda.CUstream,\n ):\n if cutlass.const_expr(\n not (\n mQ.element_type == cutlass.Float16\n or mQ.element_type == cutlass.BFloat16\n )\n ):\n raise TypeError(\"Only Float16 or BFloat16 q is supported\")\n self._dtype: Type[cutlass.Numeric] = mQ.element_type\n self.kernel(mQ, mK, mPageTable, mMaxScore, mCuK, mQOffset).launch(\n grid=(max_k_tiles, batch_size, num_qo_heads // self._G),\n block=[self._num_threads, 1, 1],\n stream=stream,\n )\n\n @cute.kernel\n def kernel(\n self,\n mQ: cute.Tensor,\n mK: cute.Tensor,\n mPageTable: cute.Tensor,\n mMaxScore: cute.Tensor,\n mCuK: cute.Tensor,\n mQOffset: cute.Tensor,\n ):\n lane = cute.arch.lane_idx()\n warp = cute.arch.warp_idx()\n tile, qi, kv_head = cute.arch.block_idx()\n\n G = self._G\n if cutlass.const_expr(self._paged):\n # mCuK holds per-request lengths on the paged path:\n # page_table supplies every KV address, so there is\n # no base offset to add.\n k_start = cutlass.Int32(0)\n seqlen_k = mCuK[qi]\n else:\n k_start = mCuK[qi]\n seqlen_k = mCuK[qi + 1] - k_start\n if cutlass.const_expr(self._is_causal and not self._qoff_default):\n col_limit = cutlass.min(mQOffset[qi] + 1, seqlen_k)\n else:\n col_limit = seqlen_k\n tile_base = tile * self._blk_kv\n\n lane_key = lane >> 4 # which of the warp's two keys this half-warp owns\n lane_grp = lane & 15 # this lane's 8-dim slice index within its key\n\n mfrag = cute.make_rmem_tensor((G,), cutlass.Float32)\n mfrag.fill(-cutlass.Float32.inf)\n\n # tile/qi are CTA-uniform, so the whole block skips dead tiles together\n # (their output stays -inf) and the shuffles below stay full-warp.\n if tile_base < col_limit:\n qfrags = [\n cute.make_rmem_tensor(cute.make_layout(8), self._dtype)\n for _ in range(G)\n ]\n for g in cutlass.range_constexpr(G):\n q_chunk = cute.local_tile(\n mQ[qi, kv_head * G + g, None], (8,), (lane_grp,)\n )\n cute.autovec_copy(q_chunk, qfrags[g])\n qs = [[cutlass.Float32(qfrags[g][i]) for i in range(8)] for g in range(G)]\n\n if cutlass.const_expr(self._paged):\n page = mPageTable[qi, tile]\n mK_blk = mK[page, kv_head, None, None] # (128, d)\n else:\n mK_h = mK[None, kv_head, None] # (total_k, d)\n\n # Keep this loop separate from the compute loop below: issuing all\n # loads before any consumption is the latency hiding. fp8 K stays\n # e4m3 through the loads (half the DRAM bytes) and upconverts per\n # iteration in the compute loop.\n kfrag = cute.make_rmem_tensor(\n cute.make_layout(self._num_iters * 8), mK.element_type\n )\n for it in cutlass.range_constexpr(self._num_iters):\n off = warp * self._keys_per_warp + it * self._KEYS_PER_ITER + lane_key\n # Tail keys clamp to the tile's first row (always in range for a\n # live tile) so loads stay unpredicated; the max step masks them.\n ld_off = off if tile_base + off < col_limit else 0\n if cutlass.const_expr(self._paged):\n k_row = mK_blk[ld_off, None]\n else:\n k_row = mK_h[k_start + tile_base + ld_off, None]\n k_chunk = cute.local_tile(k_row, (8,), (lane_grp,))\n dst = cute.make_tensor(kfrag.iterator + it * 8, cute.make_layout(8))\n cute.autovec_copy(k_chunk, dst)\n\n for it in cutlass.range_constexpr(self._num_iters):\n if cutlass.const_expr(self._kv_fp8):\n # f16 intermediate (exact for e4m3), packed cvt.\n k8 = cute.make_tensor(kfrag.iterator + it * 8, cute.make_layout(8))\n kf16 = cute.make_rmem_tensor(cute.make_layout(8), cutlass.Float16)\n _cvt_fp8_frag(k8, kf16)\n ks = [cutlass.Float32(kf16[i]) for i in range(8)]\n else:\n ks = [cutlass.Float32(kfrag[it * 8 + i]) for i in range(8)]\n es = [\n qs[g][0] * ks[0]\n + qs[g][1] * ks[1]\n + qs[g][2] * ks[2]\n + qs[g][3] * ks[3]\n + qs[g][4] * ks[4]\n + qs[g][5] * ks[5]\n + qs[g][6] * ks[6]\n + qs[g][7] * ks[7]\n for g in range(G)\n ]\n # Butterfly-add over the 16 dim-slice lanes of this key.\n for s in cutlass.range_constexpr(4):\n off_r = 8 >> s\n es = [\n es[g] + cute.arch.shuffle_sync_bfly(es[g], off_r)\n for g in range(G)\n ]\n pos = (\n tile_base\n + warp * self._keys_per_warp\n + it * self._KEYS_PER_ITER\n + lane_key\n )\n if pos < col_limit:\n for g in cutlass.range_constexpr(G):\n mfrag[g] = cute.arch.fmax(mfrag[g], es[g])\n\n # Max-combine the two half-warps' keys.\n for g in cutlass.range_constexpr(G):\n mfrag[g] = cute.arch.fmax(\n mfrag[g], cute.arch.shuffle_sync_bfly(mfrag[g], 16)\n )\n\n @cute.struct\n class SharedStorage:\n s_max: cute.struct.MemRange[cutlass.Float32, self._NUM_WARPS * G]\n\n smem = cutlass.utils.SmemAllocator()\n storage = smem.allocate(SharedStorage)\n s_max = storage.s_max.get_tensor(\n cute.make_layout((self._NUM_WARPS, G), stride=(G, 1))\n )\n if lane == 0:\n for g in cutlass.range_constexpr(G):\n s_max[warp, g] = mfrag[g]\n cute.arch.sync_threads()\n\n if warp == 0 and lane < G:\n r = s_max[0, lane]\n for w in cutlass.range_constexpr(1, self._NUM_WARPS):\n r = cute.arch.fmax(r, s_max[w, lane])\n mMaxScore[kv_head * G + lane, tile, qi] = r\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## 📌 Description\n\nFollow-up to #3655, which enabled MiniMax Sparse Attention (MSA) on SM120/SM121. The indexer (proxy score + top-k, the two ops that pick each query's KV blocks) stayed behind vLLM in a few regimes there. All of the gaps traced to `msa_topk_select` and its wrapper rather than to the proxy kernel:\n\n- At decode with small batches, the top-k launches one CTA per (query, head) row, which is 4 CTAs at batch 1, leaving the GPU nearly idle. At 32k context those rows also fall into the radix kernel, which costs about as much as the proxy itself.\n- At long-sequence prefill, the top-k reads scores with strided accesses, and the radix kernel re-reads them once per digit pass.\n- The packed decode wrappers built the causal-offset tensor with three small torch kernels per call, about as costly as the top-k itself at short sequence lengths.\n\nChanges:\n\n- A new chunked top-k. A partial kernel ranks 64-block chunks independently, one CTA per (query, head, chunk), and a merge kernel then re-ranks the surviving candidates for each row. Both use the same ordering as the existing top-k kernels, so selections are identical. The merge launches with PDL to overlap with the partial kernel.\n- A q-tiled variant of the partial kernel for large grids. It covers 32 queries per CTA so that every score load is one coalesced line, which extends the chunked path to prefill under a 128 MB scratch cap; larger grids keep the radix kernel.\n- The packed decode kernels (bf16 and NVFP4) now compute the causal offset in-kernel when `q_offset` is not given, removing the wrapper's torch launches from the decode path.\n\nThe kernel choice depends only on shapes, so it is CUDA-graph safe; a new test covers graph capture on the chunked path.\n\n### Performance\n\nMeasured as in #3655: median GPU time over CUDA-graph replays (CUPTI), with the L2 cache flushed between replays so one replay cannot reuse the previous replay's data. The baseline is vLLM's MiniMax-M3 Triton MSA kernels on the same GPUs and shapes. Each cell is an RTX PRO 6000 Server / RTX 5080 / GB10 triple, and speedup = vLLM time / FlashInfer time, so higher is better. \"Before\" is main as of #3655. The MTP columns run the same call with 4 draft tokens per request, as in a speculative-decoding verify step.\n\nIndexer decode (proxy + top-k), batch 1:\n\n| S | before | after | before (4-token MTP) | after (4-token MTP) |\n|--:|:--:|:--:|:--:|:--:|\n| 2k | 1.31 / 1.43 / 1.33 | 1.31 / 1.42 / 1.38 | 0.73 / 0.71 / 0.91 | 1.20 / 1.12 / 1.29 |\n| 4k | 1.40 / 1.39 / 1.21 | 1.43 / 1.38 / 1.24 | 0.87 / 0.86 / 1.03 | 1.39 / 1.29 / 1.33 |\n| 8k | 1.18 / 1.10 / 1.08 | 1.28 / 1.22 / 1.10 | 0.82 / 0.90 / 0.95 | 1.26 / 1.34 / 1.11 |\n| 16k | 1.18 / 1.09 / 1.02 | 1.25 / 1.17 / 1.09 | 0.95 / 0.85 / 0.97 | 1.34 / 1.19 / 1.09 |\n| 32k | 0.90 / 0.98 / 0.98 | 1.08 / 1.11 / 1.03 | 0.95 / 0.94 / 0.96 | 1.36 / 1.30 / 1.07 |\n\nIndexer prefill, batch 1 (the 2k and 4k rows keep the old kernels and are unchanged within noise):\n\n| S | before | after |\n|--:|:--:|:--:|\n| 8k | 1.04 / 1.14 / 1.01 | 1.06 / 1.18 / 1.02 |\n| 16k | 1.04 / 1.18 / 1.02 | 1.19 / 1.25 / 1.16 |\n| 32k | 0.90 / 1.08 / 0.89 | 1.16 / 1.28 / 1.19 |\n\nMeasured against the kernels this PR replaces:\n\n- The new top-k alone is 1.4-2.2x faster at decode (batch 1 to 128) and 1.2-2.1x faster at 8k-32k prefill.\n- The proxy kernel is untouched, so shapes where it dominates do not move: at batch 128 the end-to-end ratio stays at 1.00-1.03 vs vLLM.\n- The optional NVFP4 decode path also speeds up because its wrapper sheds the same torch launches.\n\n## 🔍 Related Issues\n\nFollow-up to #3655.\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\nAll 155 tests in `tests/msa_ops/` pass on an RTX 5080 (SM120) after rebasing onto current main. This PR adds tests for:\n\n- the dispatch boundaries between the three top-k kernels\n- selection identity between the chunked and existing kernels, including NaN scores, forced blocks, and the ragged q-tile tail\n- CUDA-graph capture on the chunked path\n- explicit `q_offset` on both packed decode kernels\n\nIt also moves the paged-varlen fp4 test's reference to float32: the kernel's fp4 x scale products never round through bf16, so the bf16-rounded reference misses the 5e-2 tolerance on causal-boundary blocks (16 of 40 seeds on an RTX 5080, including the checked-in seed). The same treatment the other fp4 tests already use.\n\n`compute-sanitizer` racecheck and memcheck are clean on the new kernels.\n\n## Reviewer Notes\n\n- Per-token `num_valid_pages` calls (added by #4324) stay on the single-kernel paths: the chunked kernels' geometry is host-derived from the scalar count.\n- Selection identity across the top-k kernels (same bit-key and tie order) is pinned by tests.\n- The row-per-CTA and q-tiled partial kernels keep separate bodies on purpose: the row-per-CTA binary is production-validated.\n- Deferred for the same reason: skipping the redundant sentinel prefill of the candidate scratch, and sharing the forced-slot fill across the three kernels.\n\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n- **New Features**\n - Added chunked top-k selection for large candidate sets, including tiled execution and forced-page handling.\n - Added optional default query-offset handling for packed decode with right-aligned causal masking.\n - Added tracing support for MSA top-k selection.\n\n- **Bug Fixes**\n - Improved causal masking consistency across packed decode formats.\n - Preserved sentinel results and selected-score correctness during top-k selection.\n\n- **Tests**\n - Expanded coverage for large contexts, query offsets, chunked selection, tracing, and CUDA graph execution.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000 Server\", \"model\": null, \"shape\": \"S=2k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.31, \"optimized\": 1.31, \"stated_speedup\": null, \"speedup\": 1.0}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"S=2k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.43, \"optimized\": 1.42, \"stated_speedup\": null, \"speedup\": 1.007}, {\"scope\": \"kernel\", \"hardware\": \"GB10\", \"model\": null, \"shape\": \"S=2k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.33, \"optimized\": 1.38, \"stated_speedup\": null, \"speedup\": 0.9638}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000 Server\", \"model\": null, \"shape\": \"S=2k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.73, \"optimized\": 1.2, \"stated_speedup\": null, \"speedup\": 0.6083}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"S=2k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.71, \"optimized\": 1.12, \"stated_speedup\": null, \"speedup\": 0.6339}, {\"scope\": \"kernel\", \"hardware\": \"GB10\", \"model\": null, \"shape\": \"S=2k\", \"batch_size\": 1, \"metric\": \"latency\", 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\"hardware\": \"GB10\", \"model\": null, \"shape\": \"S=16k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.02, \"optimized\": 1.09, \"stated_speedup\": null, \"speedup\": 0.9358}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000 Server\", \"model\": null, \"shape\": \"S=16k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.95, \"optimized\": 1.34, \"stated_speedup\": null, \"speedup\": 0.709}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"S=16k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.85, \"optimized\": 1.19, \"stated_speedup\": null, \"speedup\": 0.7143}, {\"scope\": \"kernel\", \"hardware\": \"GB10\", \"model\": null, \"shape\": \"S=16k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.97, \"optimized\": 1.09, \"stated_speedup\": null, \"speedup\": 0.8899}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000 Server\", \"model\": null, \"shape\": \"S=32k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.9, \"optimized\": 1.08, \"stated_speedup\": null, \"speedup\": 0.8333}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"S=32k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.98, \"optimized\": 1.11, \"stated_speedup\": null, \"speedup\": 0.8829}, {\"scope\": \"kernel\", \"hardware\": \"GB10\", \"model\": null, \"shape\": \"S=32k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.98, \"optimized\": 1.03, \"stated_speedup\": null, \"speedup\": 0.9515}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000 Server\", \"model\": null, \"shape\": \"S=32k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.95, \"optimized\": 1.36, \"stated_speedup\": null, \"speedup\": 0.6985}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"S=32k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.94, \"optimized\": 1.3, \"stated_speedup\": null, \"speedup\": 0.7231}, {\"scope\": \"kernel\", \"hardware\": \"GB10\", \"model\": null, \"shape\": \"S=32k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.96, \"optimized\": 1.07, \"stated_speedup\": null, \"speedup\": 0.8972}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000 Server\", \"model\": null, \"shape\": \"S=8k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.04, \"optimized\": 1.06, \"stated_speedup\": null, \"speedup\": 0.9811}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"S=8k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.14, \"optimized\": 1.18, \"stated_speedup\": null, \"speedup\": 0.9661}, {\"scope\": \"kernel\", \"hardware\": \"GB10\", \"model\": null, \"shape\": \"S=8k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.01, \"optimized\": 1.02, \"stated_speedup\": null, \"speedup\": 0.9902}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000 Server\", \"model\": null, \"shape\": \"S=16k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.04, \"optimized\": 1.19, \"stated_speedup\": null, \"speedup\": 0.8739}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"S=16k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.18, \"optimized\": 1.25, \"stated_speedup\": null, \"speedup\": 0.944}, {\"scope\": \"kernel\", \"hardware\": \"GB10\", \"model\": null, \"shape\": \"S=16k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.02, \"optimized\": 1.16, \"stated_speedup\": null, \"speedup\": 0.8793}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000 Server\", \"model\": null, \"shape\": \"S=32k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.9, \"optimized\": 1.16, \"stated_speedup\": null, \"speedup\": 0.7759}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"S=32k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.08, \"optimized\": 1.28, \"stated_speedup\": null, \"speedup\": 0.8438}, {\"scope\": \"kernel\", \"hardware\": \"GB10\", \"model\": null, \"shape\": \"S=32k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.89, \"optimized\": 1.19, \"stated_speedup\": null, \"speedup\": 0.7479}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": null, \"shape\": null, \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.4, \"speedup\": 1.4}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": null, \"shape\": null, \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 2.2, \"speedup\": 2.2}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": null, \"shape\": null, \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.2, \"speedup\": 1.2}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": null, \"shape\": null, \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 2.1, \"speedup\": 2.1}]"},"kernel_speedup":{"kind":"number","value":0.8972,"string":"0.8972"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1074,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"8c5347726f30063fa1c17c4e81e75d509936d610"},"date":{"kind":"string","value":"2026-08-25T22:12:51-04:00"},"pr_number":{"kind":"number","value":4030,"string":"4,030"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/4030"},"title":{"kind":"string","value":"perf(msa): chunked top-k and in-kernel causal offsets for the SM12x indexer (#4030)"},"message":{"kind":"string","value":"perf(msa): chunked top-k and in-kernel causal offsets for the SM12x indexer (#4030)\n\n## 📌 Description\n\nFollow-up to #3655, which enabled MiniMax Sparse Attention (MSA) on\nSM120/SM121. The indexer (proxy score + top-k, the two ops that pick\neach query's KV blocks) stayed behind vLLM in a few regimes there. All\nof the gaps traced to `msa_topk_select` and its wrapper rather than to\nthe proxy kernel:\n\n- At decode with small batches, the top-k launches one CTA per (query,\nhead) row, which is 4 CTAs at batch 1, leaving the GPU nearly idle. At\n32k context those rows also fall into the radix kernel, which costs\nabout as much as the proxy itself.\n- At long-sequence prefill, the top-k reads scores with strided\naccesses, and the radix kernel re-reads them once per digit pass.\n- The packed decode wrappers built the causal-offset tensor with three\nsmall torch kernels per call, about as costly as the top-k itself at\nshort sequence lengths.\n\nChanges:\n\n- A new chunked top-k. A partial kernel ranks 64-block chunks\nindependently, one CTA per (query, head, chunk), and a merge kernel then\nre-ranks the surviving candidates for each row. Both use the same\nordering as the existing top-k kernels, so selections are identical. The\nmerge launches with PDL to overlap with the partial kernel.\n- A q-tiled variant of the partial kernel for large grids. It covers 32\nqueries per CTA so that every score load is one coalesced line, which\nextends the chunked path to prefill under a 128 MB scratch cap; larger\ngrids keep the radix kernel.\n- The packed decode kernels (bf16 and NVFP4) now compute the causal\noffset in-kernel when `q_offset` is not given, removing the wrapper's\ntorch launches from the decode path.\n\nThe kernel choice depends only on shapes, so it is CUDA-graph safe; a\nnew test covers graph capture on the chunked path.\n\n### Performance\n\nMeasured as in #3655: median GPU time over CUDA-graph replays (CUPTI),\nwith the L2 cache flushed between replays so one replay cannot reuse the\nprevious replay's data. The baseline is vLLM's MiniMax-M3 Triton MSA\nkernels on the same GPUs and shapes. Each cell is an RTX PRO 6000 Server\n/ RTX 5080 / GB10 triple, and speedup = vLLM time / FlashInfer time, so\nhigher is better. \"Before\" is main as of #3655. The MTP columns run the\nsame call with 4 draft tokens per request, as in a speculative-decoding\nverify step.\n\nIndexer decode (proxy + top-k), batch 1:\n\n| S | before | after | before (4-token MTP) | after (4-token MTP) |\n|--:|:--:|:--:|:--:|:--:|\n| 2k | 1.31 / 1.43 / 1.33 | 1.31 / 1.42 / 1.38 | 0.73 / 0.71 / 0.91 |\n1.20 / 1.12 / 1.29 |\n| 4k | 1.40 / 1.39 / 1.21 | 1.43 / 1.38 / 1.24 | 0.87 / 0.86 / 1.03 |\n1.39 / 1.29 / 1.33 |\n| 8k | 1.18 / 1.10 / 1.08 | 1.28 / 1.22 / 1.10 | 0.82 / 0.90 / 0.95 |\n1.26 / 1.34 / 1.11 |\n| 16k | 1.18 / 1.09 / 1.02 | 1.25 / 1.17 / 1.09 | 0.95 / 0.85 / 0.97 |\n1.34 / 1.19 / 1.09 |\n| 32k | 0.90 / 0.98 / 0.98 | 1.08 / 1.11 / 1.03 | 0.95 / 0.94 / 0.96 |\n1.36 / 1.30 / 1.07 |\n\nIndexer prefill, batch 1 (the 2k and 4k rows keep the old kernels and\nare unchanged within noise):\n\n| S | before | after |\n|--:|:--:|:--:|\n| 8k | 1.04 / 1.14 / 1.01 | 1.06 / 1.18 / 1.02 |\n| 16k | 1.04 / 1.18 / 1.02 | 1.19 / 1.25 / 1.16 |\n| 32k | 0.90 / 1.08 / 0.89 | 1.16 / 1.28 / 1.19 |\n\nMeasured against the kernels this PR replaces:\n\n- The new top-k alone is 1.4-2.2x faster at decode (batch 1 to 128) and\n1.2-2.1x faster at 8k-32k prefill.\n- The proxy kernel is untouched, so shapes where it dominates do not\nmove: at batch 128 the end-to-end ratio stays at 1.00-1.03 vs vLLM.\n- The optional NVFP4 decode path also speeds up because its wrapper\nsheds the same torch launches.\n\n## 🔍 Related Issues\n\nFollow-up to #3655.\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the\npre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\nAll 155 tests in `tests/msa_ops/` pass on an RTX 5080 (SM120) after\nrebasing onto current main. This PR adds tests for:\n\n- the dispatch boundaries between the three top-k kernels\n- selection identity between the chunked and existing kernels, including\nNaN scores, forced blocks, and the ragged q-tile tail\n- CUDA-graph capture on the chunked path\n- explicit `q_offset` on both packed decode kernels\n\nIt also moves the paged-varlen fp4 test's reference to float32: the\nkernel's fp4 x scale products never round through bf16, so the\nbf16-rounded reference misses the 5e-2 tolerance on causal-boundary\nblocks (16 of 40 seeds on an RTX 5080, including the checked-in seed).\nThe same treatment the other fp4 tests already use.\n\n`compute-sanitizer` racecheck and memcheck are clean on the new kernels.\n\n## Reviewer Notes\n\n- Per-token `num_valid_pages` calls (added by #4324) stay on the\nsingle-kernel paths: the chunked kernels' geometry is host-derived from\nthe scalar count.\n- Selection identity across the top-k kernels (same bit-key and tie\norder) is pinned by tests.\n- The row-per-CTA and q-tiled partial kernels keep separate bodies on\npurpose: the row-per-CTA binary is production-validated.\n- Deferred for the same reason: skipping the redundant sentinel prefill\nof the candidate scratch, and sharing the forced-slot fill across the\nthree kernels.\n\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n- **New Features**\n- Added chunked top-k selection for large candidate sets, including\ntiled execution and forced-page handling.\n- Added optional default query-offset handling for packed decode with\nright-aligned causal masking.\n - Added tracing support for MSA top-k selection.\n\n- **Bug Fixes**\n - Improved causal masking consistency across packed decode formats.\n- Preserved sentinel results and selected-score correctness during top-k\nselection.\n\n- **Tests**\n- Expanded coverage for large contexts, query offsets, chunked\nselection, tracing, and CUDA graph execution.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n\n---------\n\nCo-authored-by: Claude Fable 5 <noreply@anthropic.com>"},"path":{"kind":"string","value":"flashinfer/msa_ops/cute_dsl/topk_select_countrank_sm12x.py"},"language":{"kind":"string","value":"cute_dsl"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"\"\"\"\nCopyright (c) 2026 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nCount-rank MSA top-K KV-block selection for SM120/SM121: O(N^2) rank count,\ndispatched below ``_MAX_BLOCKS`` where it beats the radix kernel's fixed pass cost.\n\"\"\"\n\nimport cuda.bindings.driver as cuda\nimport cutlass\nimport cutlass.cute as cute\n\nfrom .topk_select_radix_sm12x import _atomic_add_i32\n\n# SMEM-resident score cap and dispatch threshold. Below this many candidate blocks\n# (128 blocks = 16k context) the O(N^2) rank count beats the radix kernel's fixed\n# multi-pass cost; the crossover was measured empirically, and 128 is conservative\n# for parts with more SMs.\n_MAX_BLOCKS = 128\n_NTHREADS = 256\n_SENTINEL = 0x7FFFFFFF # INT32_MAX: empty slots sort to the tail, unlike -1\n\n\nclass TopKSelectCountRankSm12x:\n \"\"\"O(N^2) count-rank top-K selection for small candidate counts.\"\"\"\n\n def __init__(self, topk: int, per_token_nvp: bool = False):\n if topk != 16:\n raise ValueError(f\"topk must be 16, got {topk}\")\n self._topk = topk\n # Per-token valid-page counts: each query token carries its own causal\n # KV extent, so the forced local window and the ranked middle range are\n # token-relative instead of batch-uniform.\n self._per_token_nvp = per_token_nvp\n\n @cute.jit\n def __call__(\n self,\n mMaxScore: cute.Tensor, # (H, P, S) f32 (P = max_k_tiles)\n mOut: cute.Tensor, # (S, H, topk) int32\n mNumValidPages: cute.Tensor, # (S,) int32; dummy when not per-token\n num_valid_pages: cutlass.Int32,\n force_begin: cutlass.Int32,\n force_end: cutlass.Int32,\n total_qo_len: cutlass.Int32,\n num_qo_heads: cutlass.Int32,\n stream: cuda.CUstream,\n ):\n mBits = cute.recast_tensor(mMaxScore, cutlass.Uint32)\n self.kernel(\n mBits, mOut, mNumValidPages, num_valid_pages, force_begin, force_end\n ).launch(\n grid=(total_qo_len, num_qo_heads, 1),\n block=(_NTHREADS, 1, 1),\n stream=stream,\n )\n\n @cute.jit\n def _radix_key(self, bits):\n \"\"\"Order-preserving transform: ascending key == descending float score.\"\"\"\n key = (~bits) & cutlass.Uint32(0x7FFFFFFF)\n if (bits & cutlass.Uint32(0x80000000)) != cutlass.Uint32(0):\n key = bits\n return key\n\n @cute.kernel\n def kernel(\n self,\n mScore: cute.Tensor, # (H, P, S) f32 recast to u32 bits\n mOut: cute.Tensor, # (S, H, topk) int32\n mNumValidPages: cute.Tensor, # (S,) int32\n num_valid_pages: cutlass.Int32,\n force_begin: cutlass.Int32,\n force_end: cutlass.Int32,\n ):\n tid, _, _ = cute.arch.thread_idx()\n q, h, _ = cute.arch.block_idx()\n\n @cute.struct\n class SharedStorage:\n score: cute.struct.MemRange[cutlass.Uint32, _MAX_BLOCKS]\n sel: cute.struct.MemRange[cutlass.Int32, 16]\n cnt: cute.struct.MemRange[cutlass.Int32, 1]\n\n smem = cutlass.utils.SmemAllocator()\n st = smem.allocate(SharedStorage)\n score = st.score.get_tensor(cute.make_layout(_MAX_BLOCKS))\n sel = st.sel.get_tensor(cute.make_layout(16))\n cnt = st.cnt.get_tensor(cute.make_layout(1))\n\n if cutlass.const_expr(self._per_token_nvp):\n # Per-token counts arrive on device, so nothing on the host bounds\n # them (reading them would sync). Clamp to the score tensor's own\n # block extent, which is also the `score` staging bound because the\n # host only dispatches here when max_k_tiles fits _MAX_BLOCKS: an\n # out-of-range entry would otherwise read mScore past its end,\n # overrun smem, and emit block indices the attend kernel cannot\n # address. An over-large count degrades to the full block range.\n cap = cutlass.min(\n cutlass.Int32(mScore.shape[1]), cutlass.Int32(_MAX_BLOCKS)\n )\n nvp = cutlass.max(cutlass.Int32(0), cutlass.min(mNumValidPages[q], cap))\n else:\n nvp = num_valid_pages\n\n # Per-token nvp can be smaller than the forced region (a token whose\n # causal extent is shorter than the local window), which the host-side\n # scalar check cannot rule out. Shrink the forced region to fit rather\n # than emitting negative block indices.\n fb = cutlass.min(force_begin, nvp)\n fe = cutlass.min(force_end, nvp - fb)\n\n mid_lo = fb\n mid_hi = nvp - fe\n n_forced = fb + fe\n target = cutlass.Int32(self._topk) - n_forced\n\n # Stage the middle scores' radix keys in SMEM: the rank loop rereads each\n # one N times, and the bit key preserves the exact radix-kernel order,\n # with deterministic NaN placement.\n b = mid_lo + tid\n while b < mid_hi:\n score[b] = self._radix_key(mScore[h, b, q])\n b += _NTHREADS\n\n # Forced sink/window blocks bypass ranking; emit slots start after them\n if tid == 0:\n w = cutlass.Int32(0)\n i = cutlass.Int32(0)\n while i < fb:\n sel[w] = i\n w += 1\n i += 1\n j = cutlass.Int32(0)\n while j < fe:\n sel[w] = mid_hi + j\n w += 1\n j += 1\n k = w\n while k < self._topk:\n sel[k] = cutlass.Int32(_SENTINEL)\n k += 1\n cnt[0] = cutlass.Int32(0)\n cute.arch.barrier()\n\n # rank = count of strictly-better blocks (lower key = higher score, ties\n # broken toward the lower index); a block is selected iff rank < target.\n b = mid_lo + tid\n while b < mid_hi:\n kb = score[b]\n rank = cutlass.Int32(0)\n j = mid_lo\n while j < mid_hi:\n kj = score[j]\n if (kj < kb) or ((kj == kb) and (j < b)):\n rank += 1\n j += 1\n if rank < target:\n slot = _atomic_add_i32(1, cnt.iterator + 0)\n if n_forced + slot < cutlass.Int32(self._topk):\n sel[n_forced + slot] = b\n b += _NTHREADS\n cute.arch.barrier()\n\n # Ascending-by-index sort, then write.\n if tid == 0:\n a = cutlass.Int32(1)\n while a < self._topk:\n key2 = sel[a]\n p = a - 1\n while (p >= 0) and (sel[p] > key2):\n sel[p + 1] = sel[p]\n p -= 1\n sel[p + 1] = key2\n a += 1\n kk = cutlass.Int32(0)\n while kk < self._topk:\n v = sel[kk]\n if v == cutlass.Int32(_SENTINEL):\n v = cutlass.Int32(-1)\n mOut[q, h, kk] = v\n kk += 1\n"},"after_code":{"kind":"string","value":"\"\"\"\nCopyright (c) 2026 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nCount-rank MSA top-K KV-block selection for SM120/SM121: O(N^2) rank count,\ndispatched below ``_MAX_BLOCKS`` where it beats the radix kernel's fixed pass cost.\n\"\"\"\n\nimport cuda.bindings.driver as cuda\nimport cutlass\nimport cutlass.cute as cute\n\nfrom .topk_select_radix_sm12x import _atomic_add_i32, _radix_key\n\n# SMEM-resident score cap and dispatch threshold. Below this many candidate blocks\n# (128 blocks = 16k context) the O(N^2) rank count beats the radix kernel's fixed\n# multi-pass cost; the crossover was measured empirically, and 128 is conservative\n# for parts with more SMs.\n_MAX_BLOCKS = 128\n_NTHREADS = 256\n_SENTINEL = 0x7FFFFFFF # INT32_MAX: empty slots sort to the tail, unlike -1\n\n\nclass TopKSelectCountRankSm12x:\n \"\"\"O(N^2) count-rank top-K selection for small candidate counts.\"\"\"\n\n def __init__(self, topk: int, per_token_nvp: bool = False):\n if topk != 16:\n raise ValueError(f\"topk must be 16, got {topk}\")\n self._topk = topk\n # Per-token valid-page counts: each query token carries its own causal\n # KV extent, so the forced local window and the ranked middle range are\n # token-relative instead of batch-uniform.\n self._per_token_nvp = per_token_nvp\n\n @cute.jit\n def __call__(\n self,\n mMaxScore: cute.Tensor, # (H, P, S) f32 (P = max_k_tiles)\n mOut: cute.Tensor, # (S, H, topk) int32\n mNumValidPages: cute.Tensor, # (S,) int32; dummy when not per-token\n num_valid_pages: cutlass.Int32,\n force_begin: cutlass.Int32,\n force_end: cutlass.Int32,\n total_qo_len: cutlass.Int32,\n num_qo_heads: cutlass.Int32,\n stream: cuda.CUstream,\n ):\n mBits = cute.recast_tensor(mMaxScore, cutlass.Uint32)\n self.kernel(\n mBits, mOut, mNumValidPages, num_valid_pages, force_begin, force_end\n ).launch(\n grid=(total_qo_len, num_qo_heads, 1),\n block=(_NTHREADS, 1, 1),\n stream=stream,\n )\n\n @cute.kernel\n def kernel(\n self,\n mScore: cute.Tensor, # (H, P, S) f32 recast to u32 bits\n mOut: cute.Tensor, # (S, H, topk) int32\n mNumValidPages: cute.Tensor, # (S,) int32\n num_valid_pages: cutlass.Int32,\n force_begin: cutlass.Int32,\n force_end: cutlass.Int32,\n ):\n tid, _, _ = cute.arch.thread_idx()\n q, h, _ = cute.arch.block_idx()\n\n @cute.struct\n class SharedStorage:\n score: cute.struct.MemRange[cutlass.Uint32, _MAX_BLOCKS]\n sel: cute.struct.MemRange[cutlass.Int32, 16]\n cnt: cute.struct.MemRange[cutlass.Int32, 1]\n\n smem = cutlass.utils.SmemAllocator()\n st = smem.allocate(SharedStorage)\n score = st.score.get_tensor(cute.make_layout(_MAX_BLOCKS))\n sel = st.sel.get_tensor(cute.make_layout(16))\n cnt = st.cnt.get_tensor(cute.make_layout(1))\n\n if cutlass.const_expr(self._per_token_nvp):\n # Per-token counts arrive on device, so nothing on the host bounds\n # them (reading them would sync). Clamp to the score tensor's own\n # block extent, which is also the `score` staging bound because the\n # host only dispatches here when max_k_tiles fits _MAX_BLOCKS: an\n # out-of-range entry would otherwise read mScore past its end,\n # overrun smem, and emit block indices the attend kernel cannot\n # address. An over-large count degrades to the full block range.\n cap = cutlass.min(\n cutlass.Int32(mScore.shape[1]), cutlass.Int32(_MAX_BLOCKS)\n )\n nvp = cutlass.max(cutlass.Int32(0), cutlass.min(mNumValidPages[q], cap))\n else:\n nvp = num_valid_pages\n\n # Per-token nvp can be smaller than the forced region (a token whose\n # causal extent is shorter than the local window), which the host-side\n # scalar check cannot rule out. Shrink the forced region to fit rather\n # than emitting negative block indices.\n fb = cutlass.min(force_begin, nvp)\n fe = cutlass.min(force_end, nvp - fb)\n\n mid_lo = fb\n mid_hi = nvp - fe\n n_forced = fb + fe\n target = cutlass.Int32(self._topk) - n_forced\n\n # Stage the middle scores' radix keys in SMEM: the rank loop rereads each\n # one N times, and the bit key preserves the exact radix-kernel order,\n # with deterministic NaN placement.\n b = mid_lo + tid\n while b < mid_hi:\n score[b] = _radix_key(mScore[h, b, q])\n b += _NTHREADS\n\n # Forced sink/window blocks bypass ranking; emit slots start after them\n if tid == 0:\n w = cutlass.Int32(0)\n i = cutlass.Int32(0)\n while i < fb:\n sel[w] = i\n w += 1\n i += 1\n j = cutlass.Int32(0)\n while j < fe:\n sel[w] = mid_hi + j\n w += 1\n j += 1\n k = w\n while k < self._topk:\n sel[k] = cutlass.Int32(_SENTINEL)\n k += 1\n cnt[0] = cutlass.Int32(0)\n cute.arch.barrier()\n\n # rank = count of strictly-better blocks (lower key = higher score, ties\n # broken toward the lower index); a block is selected iff rank < target.\n b = mid_lo + tid\n while b < mid_hi:\n kb = score[b]\n rank = cutlass.Int32(0)\n j = mid_lo\n while j < mid_hi:\n kj = score[j]\n if (kj < kb) or ((kj == kb) and (j < b)):\n rank += 1\n j += 1\n if rank < target:\n slot = _atomic_add_i32(1, cnt.iterator + 0)\n if n_forced + slot < cutlass.Int32(self._topk):\n sel[n_forced + slot] = b\n b += _NTHREADS\n cute.arch.barrier()\n\n # Ascending-by-index sort, then write.\n if tid == 0:\n a = cutlass.Int32(1)\n while a < self._topk:\n key2 = sel[a]\n p = a - 1\n while (p >= 0) and (sel[p] > key2):\n sel[p + 1] = sel[p]\n p -= 1\n sel[p + 1] = key2\n a += 1\n kk = cutlass.Int32(0)\n while kk < self._topk:\n v = sel[kk]\n if v == cutlass.Int32(_SENTINEL):\n v = cutlass.Int32(-1)\n mOut[q, h, kk] = v\n kk += 1\n"},"diff":{"kind":"string","value":"--- flashinfer/msa_ops/cute_dsl/topk_select_countrank_sm12x.py\n+++ flashinfer/msa_ops/cute_dsl/topk_select_countrank_sm12x.py\n@@ -21,7 +21,7 @@\n import cutlass\n import cutlass.cute as cute\n \n-from .topk_select_radix_sm12x import _atomic_add_i32\n+from .topk_select_radix_sm12x import _atomic_add_i32, _radix_key\n \n # SMEM-resident score cap and dispatch threshold. Below this many candidate blocks\n # (128 blocks = 16k context) the O(N^2) rank count beats the radix kernel's fixed\n@@ -65,14 +65,6 @@\n block=(_NTHREADS, 1, 1),\n stream=stream,\n )\n-\n- @cute.jit\n- def _radix_key(self, bits):\n- \"\"\"Order-preserving transform: ascending key == descending float score.\"\"\"\n- key = (~bits) & cutlass.Uint32(0x7FFFFFFF)\n- if (bits & cutlass.Uint32(0x80000000)) != cutlass.Uint32(0):\n- key = bits\n- return key\n \n @cute.kernel\n def kernel(\n@@ -131,7 +123,7 @@\n # with deterministic NaN placement.\n b = mid_lo + tid\n while b < mid_hi:\n- score[b] = self._radix_key(mScore[h, b, q])\n+ score[b] = _radix_key(mScore[h, b, q])\n b += _NTHREADS\n \n # Forced sink/window blocks bypass ranking; emit slots start after them"},"lines_added":{"kind":"number","value":2,"string":"2"},"lines_removed":{"kind":"number","value":10,"string":"10"},"files_in_commit":{"kind":"number","value":7,"string":"7"},"models_mentioned":{"kind":"list like","value":["minimax"],"string":"[\n \"minimax\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["RTX5080","SM120","SM121"],"string":"[\n \"RTX5080\",\n \"SM120\",\n \"SM121\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":["2.2x","2.1x"],"string":"[\n \"2.2x\",\n \"2.1x\"\n]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cute_dsl kernel file from flashinfer (flashinfer/msa_ops/cute_dsl/topk_select_countrank_sm12x.py).\n\nGoal: perf(msa): chunked top-k and in-kernel causal offsets for the SM12x indexer\nTarget hardware: RTX5080, SM120, SM121\nTarget models: minimax\n\nCurrent file:\n```python\n\"\"\"\nCopyright (c) 2026 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nCount-rank MSA top-K KV-block selection for SM120/SM121: O(N^2) rank count,\ndispatched below ``_MAX_BLOCKS`` where it beats the radix kernel's fixed pass cost.\n\"\"\"\n\nimport cuda.bindings.driver as cuda\nimport cutlass\nimport cutlass.cute as cute\n\nfrom .topk_select_radix_sm12x import _atomic_add_i32\n\n# SMEM-resident score cap and dispatch threshold. Below this many candidate blocks\n# (128 blocks = 16k context) the O(N^2) rank count beats the radix kernel's fixed\n# multi-pass cost; the crossover was measured empirically, and 128 is conservative\n# for parts with more SMs.\n_MAX_BLOCKS = 128\n_NTHREADS = 256\n_SENTINEL = 0x7FFFFFFF # INT32_MAX: empty slots sort to the tail, unlike -1\n\n\nclass TopKSelectCountRankSm12x:\n \"\"\"O(N^2) count-rank top-K selection for small candidate counts.\"\"\"\n\n def __init__(self, topk: int, per_token_nvp: bool = False):\n if topk != 16:\n raise ValueError(f\"topk must be 16, got {topk}\")\n self._topk = topk\n # Per-token valid-page counts: each query token carries its own causal\n # KV extent, so the forced local window and the ranked middle range are\n # token-relative instead of batch-uniform.\n self._per_token_nvp = per_token_nvp\n\n @cute.jit\n def __call__(\n self,\n mMaxScore: cute.Tensor, # (H, P, S) f32 (P = max_k_tiles)\n mOut: cute.Tensor, # (S, H, topk) int32\n mNumValidPages: cute.Tensor, # (S,) int32; dummy when not per-token\n num_valid_pages: cutlass.Int32,\n force_begin: cutlass.Int32,\n force_end: cutlass.Int32,\n total_qo_len: cutlass.Int32,\n num_qo_heads: cutlass.Int32,\n stream: cuda.CUstream,\n ):\n mBits = cute.recast_tensor(mMaxScore, cutlass.Uint32)\n self.kernel(\n mBits, mOut, mNumValidPages, num_valid_pages, force_begin, force_end\n ).launch(\n grid=(total_qo_len, num_qo_heads, 1),\n block=(_NTHREADS, 1, 1),\n stream=stream,\n )\n\n @cute.jit\n def _radix_key(self, bits):\n \"\"\"Order-preserving transform: ascending key == descending float score.\"\"\"\n key = (~bits) & cutlass.Uint32(0x7FFFFFFF)\n if (bits & cutlass.Uint32(0x80000000)) != cutlass.Uint32(0):\n key = bits\n return key\n\n @cute.kernel\n def kernel(\n self,\n mScore: cute.Tensor, # (H, P, S) f32 recast to u32 bits\n mOut: cute.Tensor, # (S, H, topk) int32\n mNumValidPages: cute.Tensor, # (S,) int32\n num_valid_pages: cutlass.Int32,\n force_begin: cutlass.Int32,\n force_end: cutlass.Int32,\n ):\n tid, _, _ = cute.arch.thread_idx()\n q, h, _ = cute.arch.block_idx()\n\n @cute.struct\n class SharedStorage:\n score: cute.struct.MemRange[cutlass.Uint32, _MAX_BLOCKS]\n sel: cute.struct.MemRange[cutlass.Int32, 16]\n cnt: cute.struct.MemRange[cutlass.Int32, 1]\n\n smem = cutlass.utils.SmemAllocator()\n st = smem.allocate(SharedStorage)\n score = st.score.get_tensor(cute.make_layout(_MAX_BLOCKS))\n sel = st.sel.get_tensor(cute.make_layout(16))\n cnt = st.cnt.get_tensor(cute.make_layout(1))\n\n if cutlass.const_expr(self._per_token_nvp):\n # Per-token counts arrive on device, so nothing on the host bounds\n # them (reading them would sync). Clamp to the score tensor's own\n # block extent, which is also the `score` staging bound because the\n # host only dispatches here when max_k_tiles fits _MAX_BLOCKS: an\n # out-of-range entry would otherwise read mScore past its end,\n # overrun smem, and emit block indices the attend kernel cannot\n # address. An over-large count degrades to the full block range.\n cap = cutlass.min(\n cutlass.Int32(mScore.shape[1]), cutlass.Int32(_MAX_BLOCKS)\n )\n nvp = cutlass.max(cutlass.Int32(0), cutlass.min(mNumValidPages[q], cap))\n else:\n nvp = num_valid_pages\n\n # Per-token nvp can be smaller than the forced region (a token whose\n # causal extent is shorter than the local window), which the host-side\n # scalar check cannot rule out. Shrink the forced region to fit rather\n # than emitting negative block indices.\n fb = cutlass.min(force_begin, nvp)\n fe = cutlass.min(force_end, nvp - fb)\n\n mid_lo = fb\n mid_hi = nvp - fe\n n_forced = fb + fe\n target = cutlass.Int32(self._topk) - n_forced\n\n # Stage the middle scores' radix keys in SMEM: the rank loop rereads each\n # one N times, and the bit key preserves the exact radix-kernel order,\n # with deterministic NaN placement.\n b = mid_lo + tid\n while b < mid_hi:\n score[b] = self._radix_key(mScore[h, b, q])\n b += _NTHREADS\n\n # Forced sink/window blocks bypass ranking; emit slots start after them\n if tid == 0:\n w = cutlass.Int32(0)\n i = cutlass.Int32(0)\n while i < fb:\n sel[w] = i\n w += 1\n i += 1\n j = cutlass.Int32(0)\n while j < fe:\n sel[w] = mid_hi + j\n w += 1\n j += 1\n k = w\n while k < self._topk:\n sel[k] = cutlass.Int32(_SENTINEL)\n k += 1\n cnt[0] = cutlass.Int32(0)\n cute.arch.barrier()\n\n # rank = count of strictly-better blocks (lower key = higher score, ties\n # broken toward the lower index); a block is selected iff rank < target.\n b = mid_lo + tid\n while b < mid_hi:\n kb = score[b]\n rank = cutlass.Int32(0)\n j = mid_lo\n while j < mid_hi:\n kj = score[j]\n if (kj < kb) or ((kj == kb) and (j < b)):\n rank += 1\n j += 1\n if rank < target:\n slot = _atomic_add_i32(1, cnt.iterator + 0)\n if n_forced + slot < cutlass.Int32(self._topk):\n sel[n_forced + slot] = b\n b += _NTHREADS\n cute.arch.barrier()\n\n # Ascending-by-index sort, then write.\n if tid == 0:\n a = cutlass.Int32(1)\n while a < self._topk:\n key2 = sel[a]\n p = a - 1\n while (p >= 0) and (sel[p] > key2):\n sel[p + 1] = sel[p]\n p -= 1\n sel[p + 1] = key2\n a += 1\n kk = cutlass.Int32(0)\n while kk < self._topk:\n v = sel[kk]\n if v == cutlass.Int32(_SENTINEL):\n v = cutlass.Int32(-1)\n mOut[q, h, kk] = v\n kk += 1\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## 📌 Description\n\nFollow-up to #3655, which enabled MiniMax Sparse Attention (MSA) on SM120/SM121. The indexer (proxy score + top-k, the two ops that pick each query's KV blocks) stayed behind vLLM in a few regimes there. All of the gaps traced to `msa_topk_select` and its wrapper rather than to the proxy kernel:\n\n- At decode with small batches, the top-k launches one CTA per (query, head) row, which is 4 CTAs at batch 1, leaving the GPU nearly idle. At 32k context those rows also fall into the radix kernel, which costs about as much as the proxy itself.\n- At long-sequence prefill, the top-k reads scores with strided accesses, and the radix kernel re-reads them once per digit pass.\n- The packed decode wrappers built the causal-offset tensor with three small torch kernels per call, about as costly as the top-k itself at short sequence lengths.\n\nChanges:\n\n- A new chunked top-k. A partial kernel ranks 64-block chunks independently, one CTA per (query, head, chunk), and a merge kernel then re-ranks the surviving candidates for each row. Both use the same ordering as the existing top-k kernels, so selections are identical. The merge launches with PDL to overlap with the partial kernel.\n- A q-tiled variant of the partial kernel for large grids. It covers 32 queries per CTA so that every score load is one coalesced line, which extends the chunked path to prefill under a 128 MB scratch cap; larger grids keep the radix kernel.\n- The packed decode kernels (bf16 and NVFP4) now compute the causal offset in-kernel when `q_offset` is not given, removing the wrapper's torch launches from the decode path.\n\nThe kernel choice depends only on shapes, so it is CUDA-graph safe; a new test covers graph capture on the chunked path.\n\n### Performance\n\nMeasured as in #3655: median GPU time over CUDA-graph replays (CUPTI), with the L2 cache flushed between replays so one replay cannot reuse the previous replay's data. The baseline is vLLM's MiniMax-M3 Triton MSA kernels on the same GPUs and shapes. Each cell is an RTX PRO 6000 Server / RTX 5080 / GB10 triple, and speedup = vLLM time / FlashInfer time, so higher is better. \"Before\" is main as of #3655. The MTP columns run the same call with 4 draft tokens per request, as in a speculative-decoding verify step.\n\nIndexer decode (proxy + top-k), batch 1:\n\n| S | before | after | before (4-token MTP) | after (4-token MTP) |\n|--:|:--:|:--:|:--:|:--:|\n| 2k | 1.31 / 1.43 / 1.33 | 1.31 / 1.42 / 1.38 | 0.73 / 0.71 / 0.91 | 1.20 / 1.12 / 1.29 |\n| 4k | 1.40 / 1.39 / 1.21 | 1.43 / 1.38 / 1.24 | 0.87 / 0.86 / 1.03 | 1.39 / 1.29 / 1.33 |\n| 8k | 1.18 / 1.10 / 1.08 | 1.28 / 1.22 / 1.10 | 0.82 / 0.90 / 0.95 | 1.26 / 1.34 / 1.11 |\n| 16k | 1.18 / 1.09 / 1.02 | 1.25 / 1.17 / 1.09 | 0.95 / 0.85 / 0.97 | 1.34 / 1.19 / 1.09 |\n| 32k | 0.90 / 0.98 / 0.98 | 1.08 / 1.11 / 1.03 | 0.95 / 0.94 / 0.96 | 1.36 / 1.30 / 1.07 |\n\nIndexer prefill, batch 1 (the 2k and 4k rows keep the old kernels and are unchanged within noise):\n\n| S | before | after |\n|--:|:--:|:--:|\n| 8k | 1.04 / 1.14 / 1.01 | 1.06 / 1.18 / 1.02 |\n| 16k | 1.04 / 1.18 / 1.02 | 1.19 / 1.25 / 1.16 |\n| 32k | 0.90 / 1.08 / 0.89 | 1.16 / 1.28 / 1.19 |\n\nMeasured against the kernels this PR replaces:\n\n- The new top-k alone is 1.4-2.2x faster at decode (batch 1 to 128) and 1.2-2.1x faster at 8k-32k prefill.\n- The proxy kernel is untouched, so shapes where it dominates do not move: at batch 128 the end-to-end ratio stays at 1.00-1.03 vs vLLM.\n- The optional NVFP4 decode path also speeds up because its wrapper sheds the same torch launches.\n\n## 🔍 Related Issues\n\nFollow-up to #3655.\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\nAll 155 tests in `tests/msa_ops/` pass on an RTX 5080 (SM120) after rebasing onto current main. This PR adds tests for:\n\n- the dispatch boundaries between the three top-k kernels\n- selection identity between the chunked and existing kernels, including NaN scores, forced blocks, and the ragged q-tile tail\n- CUDA-graph capture on the chunked path\n- explicit `q_offset` on both packed decode kernels\n\nIt also moves the paged-varlen fp4 test's reference to float32: the kernel's fp4 x scale products never round through bf16, so the bf16-rounded reference misses the 5e-2 tolerance on causal-boundary blocks (16 of 40 seeds on an RTX 5080, including the checked-in seed). The same treatment the other fp4 tests already use.\n\n`compute-sanitizer` racecheck and memcheck are clean on the new kernels.\n\n## Reviewer Notes\n\n- Per-token `num_valid_pages` calls (added by #4324) stay on the single-kernel paths: the chunked kernels' geometry is host-derived from the scalar count.\n- Selection identity across the top-k kernels (same bit-key and tie order) is pinned by tests.\n- The row-per-CTA and q-tiled partial kernels keep separate bodies on purpose: the row-per-CTA binary is production-validated.\n- Deferred for the same reason: skipping the redundant sentinel prefill of the candidate scratch, and sharing the forced-slot fill across the three kernels.\n\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n- **New Features**\n - Added chunked top-k selection for large candidate sets, including tiled execution and forced-page handling.\n - Added optional default query-offset handling for packed decode with right-aligned causal masking.\n - Added tracing support for MSA top-k selection.\n\n- **Bug Fixes**\n - Improved causal masking consistency across packed decode formats.\n - Preserved sentinel results and selected-score correctness during top-k selection.\n\n- **Tests**\n - Expanded coverage for large contexts, query offsets, chunked selection, tracing, and CUDA graph execution.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000 Server\", \"model\": null, \"shape\": \"S=2k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.31, \"optimized\": 1.31, \"stated_speedup\": null, \"speedup\": 1.0}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"S=2k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.43, \"optimized\": 1.42, \"stated_speedup\": null, \"speedup\": 1.007}, {\"scope\": \"kernel\", \"hardware\": \"GB10\", \"model\": null, \"shape\": \"S=2k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.33, \"optimized\": 1.38, \"stated_speedup\": null, \"speedup\": 0.9638}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000 Server\", \"model\": null, \"shape\": \"S=2k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.73, \"optimized\": 1.2, \"stated_speedup\": null, \"speedup\": 0.6083}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"S=2k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.71, \"optimized\": 1.12, \"stated_speedup\": null, \"speedup\": 0.6339}, {\"scope\": \"kernel\", \"hardware\": \"GB10\", \"model\": null, \"shape\": \"S=2k\", \"batch_size\": 1, \"metric\": \"latency\", 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6000 Server\", \"model\": null, \"shape\": \"S=4k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.87, \"optimized\": 1.39, \"stated_speedup\": null, \"speedup\": 0.6259}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"S=4k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.86, \"optimized\": 1.29, \"stated_speedup\": null, \"speedup\": 0.6667}, {\"scope\": \"kernel\", \"hardware\": \"GB10\", \"model\": null, \"shape\": \"S=4k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.03, \"optimized\": 1.33, \"stated_speedup\": null, \"speedup\": 0.7744}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000 Server\", \"model\": null, \"shape\": \"S=8k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.18, \"optimized\": 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\"optimized\": 1.09, \"stated_speedup\": null, \"speedup\": 0.8899}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000 Server\", \"model\": null, \"shape\": \"S=32k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.9, \"optimized\": 1.08, \"stated_speedup\": null, \"speedup\": 0.8333}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"S=32k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.98, \"optimized\": 1.11, \"stated_speedup\": null, \"speedup\": 0.8829}, {\"scope\": \"kernel\", \"hardware\": \"GB10\", \"model\": null, \"shape\": \"S=32k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.98, \"optimized\": 1.03, \"stated_speedup\": null, \"speedup\": 0.9515}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000 Server\", \"model\": null, \"shape\": \"S=32k\", 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{\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"S=8k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.14, \"optimized\": 1.18, \"stated_speedup\": null, \"speedup\": 0.9661}, {\"scope\": \"kernel\", \"hardware\": \"GB10\", \"model\": null, \"shape\": \"S=8k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.01, \"optimized\": 1.02, \"stated_speedup\": null, \"speedup\": 0.9902}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000 Server\", \"model\": null, \"shape\": \"S=16k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.04, \"optimized\": 1.19, \"stated_speedup\": null, \"speedup\": 0.8739}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"S=16k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, 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\"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.89, \"optimized\": 1.19, \"stated_speedup\": null, \"speedup\": 0.7479}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": null, \"shape\": null, \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.4, \"speedup\": 1.4}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": null, \"shape\": null, \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 2.2, \"speedup\": 2.2}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": null, \"shape\": null, \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.2, \"speedup\": 1.2}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": null, \"shape\": null, \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 2.1, \"speedup\": 2.1}]"},"kernel_speedup":{"kind":"number","value":0.8972,"string":"0.8972"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1075,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"8c5347726f30063fa1c17c4e81e75d509936d610"},"date":{"kind":"string","value":"2026-08-25T22:12:51-04:00"},"pr_number":{"kind":"number","value":4030,"string":"4,030"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/4030"},"title":{"kind":"string","value":"perf(msa): chunked top-k and in-kernel causal offsets for the SM12x indexer (#4030)"},"message":{"kind":"string","value":"perf(msa): chunked top-k and in-kernel causal offsets for the SM12x indexer (#4030)\n\n## 📌 Description\n\nFollow-up to #3655, which enabled MiniMax Sparse Attention (MSA) on\nSM120/SM121. The indexer (proxy score + top-k, the two ops that pick\neach query's KV blocks) stayed behind vLLM in a few regimes there. All\nof the gaps traced to `msa_topk_select` and its wrapper rather than to\nthe proxy kernel:\n\n- At decode with small batches, the top-k launches one CTA per (query,\nhead) row, which is 4 CTAs at batch 1, leaving the GPU nearly idle. At\n32k context those rows also fall into the radix kernel, which costs\nabout as much as the proxy itself.\n- At long-sequence prefill, the top-k reads scores with strided\naccesses, and the radix kernel re-reads them once per digit pass.\n- The packed decode wrappers built the causal-offset tensor with three\nsmall torch kernels per call, about as costly as the top-k itself at\nshort sequence lengths.\n\nChanges:\n\n- A new chunked top-k. A partial kernel ranks 64-block chunks\nindependently, one CTA per (query, head, chunk), and a merge kernel then\nre-ranks the surviving candidates for each row. Both use the same\nordering as the existing top-k kernels, so selections are identical. The\nmerge launches with PDL to overlap with the partial kernel.\n- A q-tiled variant of the partial kernel for large grids. It covers 32\nqueries per CTA so that every score load is one coalesced line, which\nextends the chunked path to prefill under a 128 MB scratch cap; larger\ngrids keep the radix kernel.\n- The packed decode kernels (bf16 and NVFP4) now compute the causal\noffset in-kernel when `q_offset` is not given, removing the wrapper's\ntorch launches from the decode path.\n\nThe kernel choice depends only on shapes, so it is CUDA-graph safe; a\nnew test covers graph capture on the chunked path.\n\n### Performance\n\nMeasured as in #3655: median GPU time over CUDA-graph replays (CUPTI),\nwith the L2 cache flushed between replays so one replay cannot reuse the\nprevious replay's data. The baseline is vLLM's MiniMax-M3 Triton MSA\nkernels on the same GPUs and shapes. Each cell is an RTX PRO 6000 Server\n/ RTX 5080 / GB10 triple, and speedup = vLLM time / FlashInfer time, so\nhigher is better. \"Before\" is main as of #3655. The MTP columns run the\nsame call with 4 draft tokens per request, as in a speculative-decoding\nverify step.\n\nIndexer decode (proxy + top-k), batch 1:\n\n| S | before | after | before (4-token MTP) | after (4-token MTP) |\n|--:|:--:|:--:|:--:|:--:|\n| 2k | 1.31 / 1.43 / 1.33 | 1.31 / 1.42 / 1.38 | 0.73 / 0.71 / 0.91 |\n1.20 / 1.12 / 1.29 |\n| 4k | 1.40 / 1.39 / 1.21 | 1.43 / 1.38 / 1.24 | 0.87 / 0.86 / 1.03 |\n1.39 / 1.29 / 1.33 |\n| 8k | 1.18 / 1.10 / 1.08 | 1.28 / 1.22 / 1.10 | 0.82 / 0.90 / 0.95 |\n1.26 / 1.34 / 1.11 |\n| 16k | 1.18 / 1.09 / 1.02 | 1.25 / 1.17 / 1.09 | 0.95 / 0.85 / 0.97 |\n1.34 / 1.19 / 1.09 |\n| 32k | 0.90 / 0.98 / 0.98 | 1.08 / 1.11 / 1.03 | 0.95 / 0.94 / 0.96 |\n1.36 / 1.30 / 1.07 |\n\nIndexer prefill, batch 1 (the 2k and 4k rows keep the old kernels and\nare unchanged within noise):\n\n| S | before | after |\n|--:|:--:|:--:|\n| 8k | 1.04 / 1.14 / 1.01 | 1.06 / 1.18 / 1.02 |\n| 16k | 1.04 / 1.18 / 1.02 | 1.19 / 1.25 / 1.16 |\n| 32k | 0.90 / 1.08 / 0.89 | 1.16 / 1.28 / 1.19 |\n\nMeasured against the kernels this PR replaces:\n\n- The new top-k alone is 1.4-2.2x faster at decode (batch 1 to 128) and\n1.2-2.1x faster at 8k-32k prefill.\n- The proxy kernel is untouched, so shapes where it dominates do not\nmove: at batch 128 the end-to-end ratio stays at 1.00-1.03 vs vLLM.\n- The optional NVFP4 decode path also speeds up because its wrapper\nsheds the same torch launches.\n\n## 🔍 Related Issues\n\nFollow-up to #3655.\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the\npre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\nAll 155 tests in `tests/msa_ops/` pass on an RTX 5080 (SM120) after\nrebasing onto current main. This PR adds tests for:\n\n- the dispatch boundaries between the three top-k kernels\n- selection identity between the chunked and existing kernels, including\nNaN scores, forced blocks, and the ragged q-tile tail\n- CUDA-graph capture on the chunked path\n- explicit `q_offset` on both packed decode kernels\n\nIt also moves the paged-varlen fp4 test's reference to float32: the\nkernel's fp4 x scale products never round through bf16, so the\nbf16-rounded reference misses the 5e-2 tolerance on causal-boundary\nblocks (16 of 40 seeds on an RTX 5080, including the checked-in seed).\nThe same treatment the other fp4 tests already use.\n\n`compute-sanitizer` racecheck and memcheck are clean on the new kernels.\n\n## Reviewer Notes\n\n- Per-token `num_valid_pages` calls (added by #4324) stay on the\nsingle-kernel paths: the chunked kernels' geometry is host-derived from\nthe scalar count.\n- Selection identity across the top-k kernels (same bit-key and tie\norder) is pinned by tests.\n- The row-per-CTA and q-tiled partial kernels keep separate bodies on\npurpose: the row-per-CTA binary is production-validated.\n- Deferred for the same reason: skipping the redundant sentinel prefill\nof the candidate scratch, and sharing the forced-slot fill across the\nthree kernels.\n\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n- **New Features**\n- Added chunked top-k selection for large candidate sets, including\ntiled execution and forced-page handling.\n- Added optional default query-offset handling for packed decode with\nright-aligned causal masking.\n - Added tracing support for MSA top-k selection.\n\n- **Bug Fixes**\n - Improved causal masking consistency across packed decode formats.\n- Preserved sentinel results and selected-score correctness during top-k\nselection.\n\n- **Tests**\n- Expanded coverage for large contexts, query offsets, chunked\nselection, tracing, and CUDA graph execution.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n\n---------\n\nCo-authored-by: Claude Fable 5 <noreply@anthropic.com>"},"path":{"kind":"string","value":"flashinfer/msa_ops/cute_dsl/topk_select_radix_sm12x.py"},"language":{"kind":"string","value":"cute_dsl"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"\"\"\"\nCopyright (c) 2026 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nMulti-stage MSD radix-select MSA top-K KV-block selection for SM120/SM121.\n\"\"\"\n\nimport inspect\n\nimport cuda.bindings.driver as cuda\nimport cutlass\nimport cutlass.cute as cute\nfrom cutlass._mlir.dialects import nvvm\n\n# nvvm.atomicrmw's signature comes from the cutlass-dsl libs wheel, not the pinned DSL\n# version: libs-base needs a leading ``res`` (result type) arg, libs-cu13 infers it.\n_ATOMICRMW_NEEDS_RES = \"res\" in inspect.signature(nvvm.atomicrmw).parameters\n\n_NUM_BINS = 1024 # 10-bit radix digit per stage\n_STAGE_CAP = 2048 # threshold-bin staging capacity (per stage, not per row)\n_KTHREADS = 256\n_GROUP = 32 # bins per group for the 2-level threshold scan (_NUM_BINS / _GROUP groups)\n_SENTINEL = 0x7FFFFFFF # INT32_MAX: empty slots sort to the tail, unlike -1\n\n# Per-stage radix-digit shift of the 32-bit key: stage 1 bits 31..22, stage 2\n# bits 21..12, stage 3 bits 11..2 (bits 0-1 dropped, they are true ties).\n_STAGE_SHIFT = {1: 22, 2: 12, 3: 2}\n# Filter shift to the previous stage's threshold bin (stage 1 ranks everything).\n_MATCH_SHIFT = {2: 22, 3: 12}\n\n\ndef _atomic_add_i32(a, ptr: cute.Pointer) -> cutlass.Int32:\n \"\"\"int32 atomic add (SMEM/global generic ptr); returns the OLD value.\"\"\"\n av = cutlass.Int32(a).ir_value()\n if _ATOMICRMW_NEEDS_RES:\n return nvvm.atomicrmw(\n res=av.type, op=nvvm.AtomicOpKind.ADD, ptr=ptr.llvm_ptr, a=av\n )\n return nvvm.atomicrmw(op=nvvm.AtomicOpKind.ADD, ptr=ptr.llvm_ptr, a=av)\n\n\nclass TopKSelectRadixSm12x:\n \"\"\"Multi-stage MSD radix top-K selection over per-block proxy scores.\"\"\"\n\n def __init__(self, topk: int, per_token_nvp: bool = False):\n if topk != 16:\n raise ValueError(f\"topk must be 16, got {topk}\")\n self._topk = topk\n # See TopKSelectCountRankSm12x: per-token causal KV extents.\n self._per_token_nvp = per_token_nvp\n\n @cute.jit\n def __call__(\n self,\n mMaxScore: cute.Tensor, # (H, P, S) f32 (P = max_k_tiles)\n mOut: cute.Tensor, # (S, H, topk) int32\n mNumValidPages: cute.Tensor, # (S,) int32; dummy when not per-token\n num_valid_pages: cutlass.Int32,\n force_begin: cutlass.Int32,\n force_end: cutlass.Int32,\n total_qo_len: cutlass.Int32,\n num_qo_heads: cutlass.Int32,\n stream: cuda.CUstream,\n ):\n mBits = cute.recast_tensor(mMaxScore, cutlass.Uint32)\n self.kernel(\n mBits, mOut, mNumValidPages, num_valid_pages, force_begin, force_end\n ).launch(\n grid=(total_qo_len, num_qo_heads, 1),\n block=(_KTHREADS, 1, 1),\n stream=stream,\n )\n\n @cute.jit\n def _radix_key(self, bits):\n \"\"\"Order-preserving transform: ascending key == descending float score.\"\"\"\n key = (~bits) & cutlass.Uint32(0x7FFFFFFF)\n if (bits & cutlass.Uint32(0x80000000)) != cutlass.Uint32(0):\n key = bits\n return key\n\n @cute.kernel\n def kernel(\n self,\n mBits: cute.Tensor, # (H, P, S) uint32, raw bits of max_score\n mOut: cute.Tensor, # (S, H, topk) int32\n mNumValidPages: cute.Tensor, # (S,) int32\n num_valid_pages: cutlass.Int32,\n force_begin: cutlass.Int32,\n force_end: cutlass.Int32,\n ):\n tid, _, _ = cute.arch.thread_idx()\n q, h, _ = cute.arch.block_idx()\n\n @cute.struct\n class SharedStorage:\n hist: cute.struct.MemRange[cutlass.Int32, _NUM_BINS]\n grpsum: cute.struct.MemRange[cutlass.Int32, _NUM_BINS // _GROUP]\n stage_key: cute.struct.MemRange[cutlass.Uint32, _STAGE_CAP]\n stage_idx: cute.struct.MemRange[cutlass.Int32, _STAGE_CAP]\n sel: cute.struct.MemRange[cutlass.Int32, 16]\n scal: cute.struct.MemRange[cutlass.Int32, 8]\n pat: cute.struct.MemRange[cutlass.Uint32, 1]\n\n smem = cutlass.utils.SmemAllocator()\n st = smem.allocate(SharedStorage)\n hist = st.hist.get_tensor(cute.make_layout(_NUM_BINS))\n grpsum = st.grpsum.get_tensor(cute.make_layout(_NUM_BINS // _GROUP))\n stage_key = st.stage_key.get_tensor(cute.make_layout(_STAGE_CAP))\n stage_idx = st.stage_idx.get_tensor(cute.make_layout(_STAGE_CAP))\n sel = st.sel.get_tensor(cute.make_layout(16))\n scal = st.scal.get_tensor(cute.make_layout(8))\n pat = st.pat.get_tensor(cute.make_layout(1))\n # scal holds the block-uniform selection state, one int32 slot each\n # (readers name them: found = scal[0], threshold = scal[2], ...):\n # [0] found: blocks selected so far (emit cursor into sel)\n # [1] stage_count: items staged into stage_key/stage_idx this stage\n # [2] threshold: histogram bin where the running count crosses `need`\n # [3] base: number of items strictly below the threshold bin\n # [4] fbs: item count of the threshold bin itself\n # [5] done: selection complete, remaining stages no-op\n # [6] need: slots still to fill this stage (target - found)\n\n if cutlass.const_expr(self._per_token_nvp):\n # Clamp the device-side count to the score tensor's own block extent;\n # see TopKSelectCountRankSm12x. Nothing on the host bounds it, and an\n # out-of-range entry would read mBits past its end and emit block\n # indices the attend kernel cannot address.\n nvp = cutlass.max(\n cutlass.Int32(0),\n cutlass.min(mNumValidPages[q], cutlass.Int32(mBits.shape[1])),\n )\n else:\n nvp = num_valid_pages\n\n # Shrink the forced region to fit a token whose causal extent is\n # shorter than it; see TopKSelectCountRankSm12x.\n fb = cutlass.min(force_begin, nvp)\n fe = cutlass.min(force_end, nvp - fb)\n\n mid_lo = fb\n mid_hi = nvp - fe\n n_forced = fb + fe\n target = cutlass.Int32(self._topk) - n_forced\n\n n_groups = _NUM_BINS // _GROUP\n\n # Forced sink/window blocks bypass ranking; emit slots start after them.\n if tid == 0:\n w = cutlass.Int32(0)\n i = cutlass.Int32(0)\n while i < fb:\n sel[w] = i\n w += 1\n i += 1\n j = cutlass.Int32(0)\n while j < fe:\n sel[w] = mid_hi + j\n w += 1\n j += 1\n k = w\n while k < self._topk:\n sel[k] = cutlass.Int32(_SENTINEL)\n k += 1\n scal[0] = cutlass.Int32(0) # found\n pat[0] = cutlass.Uint32(0) # accumulated radix pattern\n # If every slot is forced (target <= 0) there is no middle to rank.\n scal[5] = (\n cutlass.Int32(0) if target > cutlass.Int32(0) else cutlass.Int32(1)\n )\n cute.arch.barrier()\n\n # MSD radix-select stages (high -> mid -> low 10 bits). The Python loop is\n # unrolled at trace time so `step` specializes statically; `done` is\n # block-uniform, so the `if dn == 0:` guards keep the barriers balanced.\n for step in (1, 2, 3):\n shift = _STAGE_SHIFT[step]\n\n if tid == 0:\n if scal[5] == cutlass.Int32(0):\n if cutlass.const_expr(step == 2):\n pat[0] = cutlass.Uint32(scal[2]) << cutlass.Uint32(22)\n elif cutlass.const_expr(step == 3):\n pat[0] = pat[0] | (\n cutlass.Uint32(scal[2]) << cutlass.Uint32(12)\n )\n scal[1] = cutlass.Int32(0) # stage_count\n scal[6] = target - scal[0] # need (remaining to select)\n cute.arch.barrier()\n\n pattern = pat[0]\n\n dn = scal[5]\n if dn == cutlass.Int32(0):\n bb = tid\n while bb < _NUM_BINS:\n hist[bb] = cutlass.Int32(0)\n bb += _KTHREADS\n cute.arch.barrier()\n\n dn = scal[5]\n if dn == cutlass.Int32(0):\n b = mid_lo + tid\n while b < mid_hi:\n okey = self._radix_key(mBits[h, b, q])\n binv = cutlass.Int32((okey >> shift) & cutlass.Uint32(0x3FF))\n if cutlass.const_expr(step == 1):\n _atomic_add_i32(1, hist.iterator + binv)\n else:\n mshift = _MATCH_SHIFT[step]\n if (\n (okey ^ pattern) >> cutlass.Uint32(mshift)\n ) == cutlass.Uint32(0):\n _atomic_add_i32(1, hist.iterator + binv)\n b += _KTHREADS\n cute.arch.barrier()\n\n # 2-level threshold scan: find the histogram bin where the running\n # count crosses `need`, with a critical serial path of ~ 2*_GROUP\n # bins instead of _NUM_BINS.\n dn = scal[5]\n if dn == cutlass.Int32(0):\n # Phase A: each thread sums one contiguous _GROUP-bin group.\n if tid < n_groups:\n gs = cutlass.Int32(0)\n gi = cutlass.Int32(0)\n gbase = tid * _GROUP\n while gi < _GROUP:\n gs += hist[gbase + gi]\n gi += 1\n grpsum[tid] = gs\n cute.arch.barrier()\n\n dn = scal[5]\n if dn == cutlass.Int32(0):\n if tid == 0:\n need = scal[6]\n # Phase B: find the group whose running count crosses `need`.\n running = cutlass.Int32(0)\n grp = cutlass.Int32(n_groups)\n base_grp = cutlass.Int32(0)\n gg = cutlass.Int32(0)\n while gg < n_groups:\n s = grpsum[gg]\n if (\n (grp == n_groups)\n and (running < need)\n and (running + s >= need)\n ):\n grp = gg\n base_grp = running\n running += s\n gg += 1\n # Default (need unreachable): all candidates selected.\n threshold = cutlass.Int32(_NUM_BINS)\n base = running\n fbs = cutlass.Int32(0)\n # Phase C: refine within the found group.\n if grp < n_groups:\n run2 = base_grp\n bi = grp * _GROUP\n end = bi + _GROUP\n while bi < end:\n c = hist[bi]\n if (\n (threshold == _NUM_BINS)\n and (run2 < need)\n and (run2 + c >= need)\n ):\n threshold = bi\n base = run2\n fbs = c\n run2 += c\n bi += 1\n scal[2] = threshold\n scal[3] = base\n scal[4] = fbs\n if cutlass.const_expr(step == 3):\n # Terminal stage emits sub-threshold and threshold-bin\n # candidates into disjoint ranges: sub-threshold via `found`\n # [found, found+base), threshold-bin here [found+base, target).\n scal[1] = scal[0] + base\n cute.arch.barrier()\n\n # Bins below the threshold emit directly; the threshold bin is staged\n # for the next stage (stage 3 emits it directly).\n dn = scal[5]\n if dn == cutlass.Int32(0):\n threshold = scal[2]\n fbs = scal[4]\n fits = fbs <= cutlass.Int32(_STAGE_CAP)\n b = mid_lo + tid\n while b < mid_hi:\n okey = self._radix_key(mBits[h, b, q])\n # `proceed` is always a dynamic (uniform-true for stage 1)\n # bool so the body below traces once, not per static branch.\n if cutlass.const_expr(step == 1):\n proceed = okey == okey\n else:\n mshift = _MATCH_SHIFT[step]\n proceed = (\n (okey ^ pattern) >> cutlass.Uint32(mshift)\n ) == cutlass.Uint32(0)\n if proceed:\n binv = cutlass.Int32((okey >> shift) & cutlass.Uint32(0x3FF))\n if binv < threshold:\n slot = _atomic_add_i32(1, scal.iterator + 0)\n if n_forced + slot < cutlass.Int32(self._topk):\n sel[n_forced + slot] = b\n elif binv == threshold:\n if cutlass.const_expr(step == 3):\n # Terminal stage: residual ties (equal in bits 31..2)\n # emit via the separate counter, capped at topk slots.\n slot = _atomic_add_i32(1, scal.iterator + 1)\n if n_forced + slot < cutlass.Int32(self._topk):\n sel[n_forced + slot] = b\n else:\n if fits:\n s = _atomic_add_i32(1, scal.iterator + 1)\n if s < cutlass.Int32(_STAGE_CAP):\n stage_key[s] = okey\n stage_idx[s] = b\n b += _KTHREADS\n cute.arch.barrier()\n\n if cutlass.const_expr(step != 3):\n # Rank the staged threshold-bin items; only the best (need - base)\n # of them, by rank, still fit in the selection.\n dn = scal[5]\n if dn == cutlass.Int32(0):\n fbs = scal[4]\n if fbs <= cutlass.Int32(_STAGE_CAP):\n stage_count = scal[1]\n base = scal[3]\n need = scal[6]\n ii = tid\n while ii < stage_count:\n ti = stage_key[ii]\n rank = cutlass.Int32(0)\n jj = cutlass.Int32(0)\n while jj < stage_count:\n tj = stage_key[jj]\n # Higher score == smaller key; ties by stage index\n if (ti > tj) or ((ti == tj) and (ii < jj)):\n rank += 1\n jj += 1\n if base + rank < need:\n slot = _atomic_add_i32(1, scal.iterator + 0)\n if n_forced + slot < cutlass.Int32(self._topk):\n sel[n_forced + slot] = stage_idx[ii]\n ii += _KTHREADS\n cute.arch.barrier()\n\n # Mark done if this stage's threshold bin fit the buffer. Thread 0\n # only: guarding all threads on scal[5] would race this write\n # (read vs write of the same slot, no barrier between).\n if tid == 0:\n if scal[5] == cutlass.Int32(0):\n if scal[4] <= cutlass.Int32(_STAGE_CAP):\n scal[5] = cutlass.Int32(1)\n cute.arch.barrier()\n else:\n if tid == 0:\n scal[5] = cutlass.Int32(1)\n cute.arch.barrier()\n\n # Ascending-by-index sort, then write.\n if tid == 0:\n a = cutlass.Int32(1)\n while a < self._topk:\n key2 = sel[a]\n p = a - 1\n while (p >= 0) and (sel[p] > key2):\n sel[p + 1] = sel[p]\n p -= 1\n sel[p + 1] = key2\n a += 1\n kk = cutlass.Int32(0)\n while kk < self._topk:\n v = sel[kk]\n if v == cutlass.Int32(_SENTINEL):\n v = cutlass.Int32(-1)\n mOut[q, h, kk] = v\n kk += 1\n"},"after_code":{"kind":"string","value":"\"\"\"\nCopyright (c) 2026 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nMulti-stage MSD radix-select MSA top-K KV-block selection for SM120/SM121.\n\"\"\"\n\nimport inspect\n\nimport cuda.bindings.driver as cuda\nimport cutlass\nimport cutlass.cute as cute\nfrom cutlass._mlir.dialects import nvvm\n\n# nvvm.atomicrmw's signature comes from the cutlass-dsl libs wheel, not the pinned DSL\n# version: libs-base needs a leading ``res`` (result type) arg, libs-cu13 infers it.\n_ATOMICRMW_NEEDS_RES = \"res\" in inspect.signature(nvvm.atomicrmw).parameters\n\n_NUM_BINS = 1024 # 10-bit radix digit per stage\n_STAGE_CAP = 2048 # threshold-bin staging capacity (per stage, not per row)\n_KTHREADS = 256\n_GROUP = 32 # bins per group for the 2-level threshold scan (_NUM_BINS / _GROUP groups)\n_SENTINEL = 0x7FFFFFFF # INT32_MAX: empty slots sort to the tail, unlike -1\n\n# Per-stage radix-digit shift of the 32-bit key: stage 1 bits 31..22, stage 2\n# bits 21..12, stage 3 bits 11..2 (bits 0-1 dropped, they are true ties).\n_STAGE_SHIFT = {1: 22, 2: 12, 3: 2}\n# Filter shift to the previous stage's threshold bin (stage 1 ranks everything).\n_MATCH_SHIFT = {2: 22, 3: 12}\n\n\ndef _atomic_add_i32(a, ptr: cute.Pointer) -> cutlass.Int32:\n \"\"\"int32 atomic add (SMEM/global generic ptr); returns the OLD value.\"\"\"\n av = cutlass.Int32(a).ir_value()\n if _ATOMICRMW_NEEDS_RES:\n return nvvm.atomicrmw(\n res=av.type, op=nvvm.AtomicOpKind.ADD, ptr=ptr.llvm_ptr, a=av\n )\n return nvvm.atomicrmw(op=nvvm.AtomicOpKind.ADD, ptr=ptr.llvm_ptr, a=av)\n\n\n@cute.jit\ndef _radix_key(bits):\n \"\"\"Order-preserving transform: ascending key == descending float score.\n\n Shared by every top-k kernel; the cross-kernel identical-selection\n invariant depends on all of them ranking on this exact key.\n \"\"\"\n key = (~bits) & cutlass.Uint32(0x7FFFFFFF)\n if (bits & cutlass.Uint32(0x80000000)) != cutlass.Uint32(0):\n key = bits\n return key\n\n\nclass TopKSelectRadixSm12x:\n \"\"\"Multi-stage MSD radix top-K selection over per-block proxy scores.\"\"\"\n\n def __init__(self, topk: int, per_token_nvp: bool = False):\n if topk != 16:\n raise ValueError(f\"topk must be 16, got {topk}\")\n self._topk = topk\n # See TopKSelectCountRankSm12x: per-token causal KV extents.\n self._per_token_nvp = per_token_nvp\n\n @cute.jit\n def __call__(\n self,\n mMaxScore: cute.Tensor, # (H, P, S) f32 (P = max_k_tiles)\n mOut: cute.Tensor, # (S, H, topk) int32\n mNumValidPages: cute.Tensor, # (S,) int32; dummy when not per-token\n num_valid_pages: cutlass.Int32,\n force_begin: cutlass.Int32,\n force_end: cutlass.Int32,\n total_qo_len: cutlass.Int32,\n num_qo_heads: cutlass.Int32,\n stream: cuda.CUstream,\n ):\n mBits = cute.recast_tensor(mMaxScore, cutlass.Uint32)\n self.kernel(\n mBits, mOut, mNumValidPages, num_valid_pages, force_begin, force_end\n ).launch(\n grid=(total_qo_len, num_qo_heads, 1),\n block=(_KTHREADS, 1, 1),\n stream=stream,\n )\n\n @cute.kernel\n def kernel(\n self,\n mBits: cute.Tensor, # (H, P, S) uint32, raw bits of max_score\n mOut: cute.Tensor, # (S, H, topk) int32\n mNumValidPages: cute.Tensor, # (S,) int32\n num_valid_pages: cutlass.Int32,\n force_begin: cutlass.Int32,\n force_end: cutlass.Int32,\n ):\n tid, _, _ = cute.arch.thread_idx()\n q, h, _ = cute.arch.block_idx()\n\n @cute.struct\n class SharedStorage:\n hist: cute.struct.MemRange[cutlass.Int32, _NUM_BINS]\n grpsum: cute.struct.MemRange[cutlass.Int32, _NUM_BINS // _GROUP]\n stage_key: cute.struct.MemRange[cutlass.Uint32, _STAGE_CAP]\n stage_idx: cute.struct.MemRange[cutlass.Int32, _STAGE_CAP]\n sel: cute.struct.MemRange[cutlass.Int32, 16]\n scal: cute.struct.MemRange[cutlass.Int32, 8]\n pat: cute.struct.MemRange[cutlass.Uint32, 1]\n\n smem = cutlass.utils.SmemAllocator()\n st = smem.allocate(SharedStorage)\n hist = st.hist.get_tensor(cute.make_layout(_NUM_BINS))\n grpsum = st.grpsum.get_tensor(cute.make_layout(_NUM_BINS // _GROUP))\n stage_key = st.stage_key.get_tensor(cute.make_layout(_STAGE_CAP))\n stage_idx = st.stage_idx.get_tensor(cute.make_layout(_STAGE_CAP))\n sel = st.sel.get_tensor(cute.make_layout(16))\n scal = st.scal.get_tensor(cute.make_layout(8))\n pat = st.pat.get_tensor(cute.make_layout(1))\n # scal holds the block-uniform selection state, one int32 slot each\n # (readers name them: found = scal[0], threshold = scal[2], ...):\n # [0] found: blocks selected so far (emit cursor into sel)\n # [1] stage_count: items staged into stage_key/stage_idx this stage\n # [2] threshold: histogram bin where the running count crosses `need`\n # [3] base: number of items strictly below the threshold bin\n # [4] fbs: item count of the threshold bin itself\n # [5] done: selection complete, remaining stages no-op\n # [6] need: slots still to fill this stage (target - found)\n\n if cutlass.const_expr(self._per_token_nvp):\n # Clamp the device-side count to the score tensor's own block extent;\n # see TopKSelectCountRankSm12x. Nothing on the host bounds it, and an\n # out-of-range entry would read mBits past its end and emit block\n # indices the attend kernel cannot address.\n nvp = cutlass.max(\n cutlass.Int32(0),\n cutlass.min(mNumValidPages[q], cutlass.Int32(mBits.shape[1])),\n )\n else:\n nvp = num_valid_pages\n\n # Shrink the forced region to fit a token whose causal extent is\n # shorter than it; see TopKSelectCountRankSm12x.\n fb = cutlass.min(force_begin, nvp)\n fe = cutlass.min(force_end, nvp - fb)\n\n mid_lo = fb\n mid_hi = nvp - fe\n n_forced = fb + fe\n target = cutlass.Int32(self._topk) - n_forced\n\n n_groups = _NUM_BINS // _GROUP\n\n # Forced sink/window blocks bypass ranking; emit slots start after them.\n if tid == 0:\n w = cutlass.Int32(0)\n i = cutlass.Int32(0)\n while i < fb:\n sel[w] = i\n w += 1\n i += 1\n j = cutlass.Int32(0)\n while j < fe:\n sel[w] = mid_hi + j\n w += 1\n j += 1\n k = w\n while k < self._topk:\n sel[k] = cutlass.Int32(_SENTINEL)\n k += 1\n scal[0] = cutlass.Int32(0) # found\n pat[0] = cutlass.Uint32(0) # accumulated radix pattern\n # If every slot is forced (target <= 0) there is no middle to rank.\n scal[5] = (\n cutlass.Int32(0) if target > cutlass.Int32(0) else cutlass.Int32(1)\n )\n cute.arch.barrier()\n\n # MSD radix-select stages (high -> mid -> low 10 bits). The Python loop is\n # unrolled at trace time so `step` specializes statically; `done` is\n # block-uniform, so the `if dn == 0:` guards keep the barriers balanced.\n for step in (1, 2, 3):\n shift = _STAGE_SHIFT[step]\n\n if tid == 0:\n if scal[5] == cutlass.Int32(0):\n if cutlass.const_expr(step == 2):\n pat[0] = cutlass.Uint32(scal[2]) << cutlass.Uint32(22)\n elif cutlass.const_expr(step == 3):\n pat[0] = pat[0] | (\n cutlass.Uint32(scal[2]) << cutlass.Uint32(12)\n )\n scal[1] = cutlass.Int32(0) # stage_count\n scal[6] = target - scal[0] # need (remaining to select)\n cute.arch.barrier()\n\n pattern = pat[0]\n\n dn = scal[5]\n if dn == cutlass.Int32(0):\n bb = tid\n while bb < _NUM_BINS:\n hist[bb] = cutlass.Int32(0)\n bb += _KTHREADS\n cute.arch.barrier()\n\n dn = scal[5]\n if dn == cutlass.Int32(0):\n b = mid_lo + tid\n while b < mid_hi:\n okey = _radix_key(mBits[h, b, q])\n binv = cutlass.Int32((okey >> shift) & cutlass.Uint32(0x3FF))\n if cutlass.const_expr(step == 1):\n _atomic_add_i32(1, hist.iterator + binv)\n else:\n mshift = _MATCH_SHIFT[step]\n if (\n (okey ^ pattern) >> cutlass.Uint32(mshift)\n ) == cutlass.Uint32(0):\n _atomic_add_i32(1, hist.iterator + binv)\n b += _KTHREADS\n cute.arch.barrier()\n\n # 2-level threshold scan: find the histogram bin where the running\n # count crosses `need`, with a critical serial path of ~ 2*_GROUP\n # bins instead of _NUM_BINS.\n dn = scal[5]\n if dn == cutlass.Int32(0):\n # Phase A: each thread sums one contiguous _GROUP-bin group.\n if tid < n_groups:\n gs = cutlass.Int32(0)\n gi = cutlass.Int32(0)\n gbase = tid * _GROUP\n while gi < _GROUP:\n gs += hist[gbase + gi]\n gi += 1\n grpsum[tid] = gs\n cute.arch.barrier()\n\n dn = scal[5]\n if dn == cutlass.Int32(0):\n if tid == 0:\n need = scal[6]\n # Phase B: find the group whose running count crosses `need`.\n running = cutlass.Int32(0)\n grp = cutlass.Int32(n_groups)\n base_grp = cutlass.Int32(0)\n gg = cutlass.Int32(0)\n while gg < n_groups:\n s = grpsum[gg]\n if (\n (grp == n_groups)\n and (running < need)\n and (running + s >= need)\n ):\n grp = gg\n base_grp = running\n running += s\n gg += 1\n # Default (need unreachable): all candidates selected.\n threshold = cutlass.Int32(_NUM_BINS)\n base = running\n fbs = cutlass.Int32(0)\n # Phase C: refine within the found group.\n if grp < n_groups:\n run2 = base_grp\n bi = grp * _GROUP\n end = bi + _GROUP\n while bi < end:\n c = hist[bi]\n if (\n (threshold == _NUM_BINS)\n and (run2 < need)\n and (run2 + c >= need)\n ):\n threshold = bi\n base = run2\n fbs = c\n run2 += c\n bi += 1\n scal[2] = threshold\n scal[3] = base\n scal[4] = fbs\n if cutlass.const_expr(step == 3):\n # Terminal stage emits sub-threshold and threshold-bin\n # candidates into disjoint ranges: sub-threshold via `found`\n # [found, found+base), threshold-bin here [found+base, target).\n scal[1] = scal[0] + base\n cute.arch.barrier()\n\n # Bins below the threshold emit directly; the threshold bin is staged\n # for the next stage (stage 3 emits it directly).\n dn = scal[5]\n if dn == cutlass.Int32(0):\n threshold = scal[2]\n fbs = scal[4]\n fits = fbs <= cutlass.Int32(_STAGE_CAP)\n b = mid_lo + tid\n while b < mid_hi:\n okey = _radix_key(mBits[h, b, q])\n # `proceed` is always a dynamic (uniform-true for stage 1)\n # bool so the body below traces once, not per static branch.\n if cutlass.const_expr(step == 1):\n proceed = okey == okey\n else:\n mshift = _MATCH_SHIFT[step]\n proceed = (\n (okey ^ pattern) >> cutlass.Uint32(mshift)\n ) == cutlass.Uint32(0)\n if proceed:\n binv = cutlass.Int32((okey >> shift) & cutlass.Uint32(0x3FF))\n if binv < threshold:\n slot = _atomic_add_i32(1, scal.iterator + 0)\n if n_forced + slot < cutlass.Int32(self._topk):\n sel[n_forced + slot] = b\n elif binv == threshold:\n if cutlass.const_expr(step == 3):\n # Terminal stage: residual ties (equal in bits 31..2)\n # emit via the separate counter, capped at topk slots.\n slot = _atomic_add_i32(1, scal.iterator + 1)\n if n_forced + slot < cutlass.Int32(self._topk):\n sel[n_forced + slot] = b\n else:\n if fits:\n s = _atomic_add_i32(1, scal.iterator + 1)\n if s < cutlass.Int32(_STAGE_CAP):\n stage_key[s] = okey\n stage_idx[s] = b\n b += _KTHREADS\n cute.arch.barrier()\n\n if cutlass.const_expr(step != 3):\n # Rank the staged threshold-bin items; only the best (need - base)\n # of them, by rank, still fit in the selection.\n dn = scal[5]\n if dn == cutlass.Int32(0):\n fbs = scal[4]\n if fbs <= cutlass.Int32(_STAGE_CAP):\n stage_count = scal[1]\n base = scal[3]\n need = scal[6]\n ii = tid\n while ii < stage_count:\n ti = stage_key[ii]\n rank = cutlass.Int32(0)\n jj = cutlass.Int32(0)\n while jj < stage_count:\n tj = stage_key[jj]\n # Higher score == smaller key; ties by stage index\n if (ti > tj) or ((ti == tj) and (ii < jj)):\n rank += 1\n jj += 1\n if base + rank < need:\n slot = _atomic_add_i32(1, scal.iterator + 0)\n if n_forced + slot < cutlass.Int32(self._topk):\n sel[n_forced + slot] = stage_idx[ii]\n ii += _KTHREADS\n cute.arch.barrier()\n\n # Mark done if this stage's threshold bin fit the buffer. Thread 0\n # only: guarding all threads on scal[5] would race this write\n # (read vs write of the same slot, no barrier between).\n if tid == 0:\n if scal[5] == cutlass.Int32(0):\n if scal[4] <= cutlass.Int32(_STAGE_CAP):\n scal[5] = cutlass.Int32(1)\n cute.arch.barrier()\n else:\n if tid == 0:\n scal[5] = cutlass.Int32(1)\n cute.arch.barrier()\n\n # Ascending-by-index sort, then write.\n if tid == 0:\n a = cutlass.Int32(1)\n while a < self._topk:\n key2 = sel[a]\n p = a - 1\n while (p >= 0) and (sel[p] > key2):\n sel[p + 1] = sel[p]\n p -= 1\n sel[p + 1] = key2\n a += 1\n kk = cutlass.Int32(0)\n while kk < self._topk:\n v = sel[kk]\n if v == cutlass.Int32(_SENTINEL):\n v = cutlass.Int32(-1)\n mOut[q, h, kk] = v\n kk += 1\n"},"diff":{"kind":"string","value":"--- flashinfer/msa_ops/cute_dsl/topk_select_radix_sm12x.py\n+++ flashinfer/msa_ops/cute_dsl/topk_select_radix_sm12x.py\n@@ -48,6 +48,19 @@\n res=av.type, op=nvvm.AtomicOpKind.ADD, ptr=ptr.llvm_ptr, a=av\n )\n return nvvm.atomicrmw(op=nvvm.AtomicOpKind.ADD, ptr=ptr.llvm_ptr, a=av)\n+\n+\n+@cute.jit\n+def _radix_key(bits):\n+ \"\"\"Order-preserving transform: ascending key == descending float score.\n+\n+ Shared by every top-k kernel; the cross-kernel identical-selection\n+ invariant depends on all of them ranking on this exact key.\n+ \"\"\"\n+ key = (~bits) & cutlass.Uint32(0x7FFFFFFF)\n+ if (bits & cutlass.Uint32(0x80000000)) != cutlass.Uint32(0):\n+ key = bits\n+ return key\n \n \n class TopKSelectRadixSm12x:\n@@ -81,14 +94,6 @@\n block=(_KTHREADS, 1, 1),\n stream=stream,\n )\n-\n- @cute.jit\n- def _radix_key(self, bits):\n- \"\"\"Order-preserving transform: ascending key == descending float score.\"\"\"\n- key = (~bits) & cutlass.Uint32(0x7FFFFFFF)\n- if (bits & cutlass.Uint32(0x80000000)) != cutlass.Uint32(0):\n- key = bits\n- return key\n \n @cute.kernel\n def kernel(\n@@ -213,7 +218,7 @@\n if dn == cutlass.Int32(0):\n b = mid_lo + tid\n while b < mid_hi:\n- okey = self._radix_key(mBits[h, b, q])\n+ okey = _radix_key(mBits[h, b, q])\n binv = cutlass.Int32((okey >> shift) & cutlass.Uint32(0x3FF))\n if cutlass.const_expr(step == 1):\n _atomic_add_i32(1, hist.iterator + binv)\n@@ -302,7 +307,7 @@\n fits = fbs <= cutlass.Int32(_STAGE_CAP)\n b = mid_lo + tid\n while b < mid_hi:\n- okey = self._radix_key(mBits[h, b, q])\n+ okey = _radix_key(mBits[h, b, q])\n # `proceed` is always a dynamic (uniform-true for stage 1)\n # bool so the body below traces once, not per static branch.\n if cutlass.const_expr(step == 1):"},"lines_added":{"kind":"number","value":15,"string":"15"},"lines_removed":{"kind":"number","value":10,"string":"10"},"files_in_commit":{"kind":"number","value":7,"string":"7"},"models_mentioned":{"kind":"list like","value":["minimax"],"string":"[\n \"minimax\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["RTX5080","SM120","SM121"],"string":"[\n \"RTX5080\",\n \"SM120\",\n \"SM121\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":["2.2x","2.1x"],"string":"[\n \"2.2x\",\n \"2.1x\"\n]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cute_dsl kernel file from flashinfer (flashinfer/msa_ops/cute_dsl/topk_select_radix_sm12x.py).\n\nGoal: perf(msa): chunked top-k and in-kernel causal offsets for the SM12x indexer\nTarget hardware: RTX5080, SM120, SM121\nTarget models: minimax\n\nCurrent file:\n```python\n\"\"\"\nCopyright (c) 2026 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nMulti-stage MSD radix-select MSA top-K KV-block selection for SM120/SM121.\n\"\"\"\n\nimport inspect\n\nimport cuda.bindings.driver as cuda\nimport cutlass\nimport cutlass.cute as cute\nfrom cutlass._mlir.dialects import nvvm\n\n# nvvm.atomicrmw's signature comes from the cutlass-dsl libs wheel, not the pinned DSL\n# version: libs-base needs a leading ``res`` (result type) arg, libs-cu13 infers it.\n_ATOMICRMW_NEEDS_RES = \"res\" in inspect.signature(nvvm.atomicrmw).parameters\n\n_NUM_BINS = 1024 # 10-bit radix digit per stage\n_STAGE_CAP = 2048 # threshold-bin staging capacity (per stage, not per row)\n_KTHREADS = 256\n_GROUP = 32 # bins per group for the 2-level threshold scan (_NUM_BINS / _GROUP groups)\n_SENTINEL = 0x7FFFFFFF # INT32_MAX: empty slots sort to the tail, unlike -1\n\n# Per-stage radix-digit shift of the 32-bit key: stage 1 bits 31..22, stage 2\n# bits 21..12, stage 3 bits 11..2 (bits 0-1 dropped, they are true ties).\n_STAGE_SHIFT = {1: 22, 2: 12, 3: 2}\n# Filter shift to the previous stage's threshold bin (stage 1 ranks everything).\n_MATCH_SHIFT = {2: 22, 3: 12}\n\n\ndef _atomic_add_i32(a, ptr: cute.Pointer) -> cutlass.Int32:\n \"\"\"int32 atomic add (SMEM/global generic ptr); returns the OLD value.\"\"\"\n av = cutlass.Int32(a).ir_value()\n if _ATOMICRMW_NEEDS_RES:\n return nvvm.atomicrmw(\n res=av.type, op=nvvm.AtomicOpKind.ADD, ptr=ptr.llvm_ptr, a=av\n )\n return nvvm.atomicrmw(op=nvvm.AtomicOpKind.ADD, ptr=ptr.llvm_ptr, a=av)\n\n\nclass TopKSelectRadixSm12x:\n \"\"\"Multi-stage MSD radix top-K selection over per-block proxy scores.\"\"\"\n\n def __init__(self, topk: int, per_token_nvp: bool = False):\n if topk != 16:\n raise ValueError(f\"topk must be 16, got {topk}\")\n self._topk = topk\n # See TopKSelectCountRankSm12x: per-token causal KV extents.\n self._per_token_nvp = per_token_nvp\n\n @cute.jit\n def __call__(\n self,\n mMaxScore: cute.Tensor, # (H, P, S) f32 (P = max_k_tiles)\n mOut: cute.Tensor, # (S, H, topk) int32\n mNumValidPages: cute.Tensor, # (S,) int32; dummy when not per-token\n num_valid_pages: cutlass.Int32,\n force_begin: cutlass.Int32,\n force_end: cutlass.Int32,\n total_qo_len: cutlass.Int32,\n num_qo_heads: cutlass.Int32,\n stream: cuda.CUstream,\n ):\n mBits = cute.recast_tensor(mMaxScore, cutlass.Uint32)\n self.kernel(\n mBits, mOut, mNumValidPages, num_valid_pages, force_begin, force_end\n ).launch(\n grid=(total_qo_len, num_qo_heads, 1),\n block=(_KTHREADS, 1, 1),\n stream=stream,\n )\n\n @cute.jit\n def _radix_key(self, bits):\n \"\"\"Order-preserving transform: ascending key == descending float score.\"\"\"\n key = (~bits) & cutlass.Uint32(0x7FFFFFFF)\n if (bits & cutlass.Uint32(0x80000000)) != cutlass.Uint32(0):\n key = bits\n return key\n\n @cute.kernel\n def kernel(\n self,\n mBits: cute.Tensor, # (H, P, S) uint32, raw bits of max_score\n mOut: cute.Tensor, # (S, H, topk) int32\n mNumValidPages: cute.Tensor, # (S,) int32\n num_valid_pages: cutlass.Int32,\n force_begin: cutlass.Int32,\n force_end: cutlass.Int32,\n ):\n tid, _, _ = cute.arch.thread_idx()\n q, h, _ = cute.arch.block_idx()\n\n @cute.struct\n class SharedStorage:\n hist: cute.struct.MemRange[cutlass.Int32, _NUM_BINS]\n grpsum: cute.struct.MemRange[cutlass.Int32, _NUM_BINS // _GROUP]\n stage_key: cute.struct.MemRange[cutlass.Uint32, _STAGE_CAP]\n stage_idx: cute.struct.MemRange[cutlass.Int32, _STAGE_CAP]\n sel: cute.struct.MemRange[cutlass.Int32, 16]\n scal: cute.struct.MemRange[cutlass.Int32, 8]\n pat: cute.struct.MemRange[cutlass.Uint32, 1]\n\n smem = cutlass.utils.SmemAllocator()\n st = smem.allocate(SharedStorage)\n hist = st.hist.get_tensor(cute.make_layout(_NUM_BINS))\n grpsum = st.grpsum.get_tensor(cute.make_layout(_NUM_BINS // _GROUP))\n stage_key = st.stage_key.get_tensor(cute.make_layout(_STAGE_CAP))\n stage_idx = st.stage_idx.get_tensor(cute.make_layout(_STAGE_CAP))\n sel = st.sel.get_tensor(cute.make_layout(16))\n scal = st.scal.get_tensor(cute.make_layout(8))\n pat = st.pat.get_tensor(cute.make_layout(1))\n # scal holds the block-uniform selection state, one int32 slot each\n # (readers name them: found = scal[0], threshold = scal[2], ...):\n # [0] found: blocks selected so far (emit cursor into sel)\n # [1] stage_count: items staged into stage_key/stage_idx this stage\n # [2] threshold: histogram bin where the running count crosses `need`\n # [3] base: number of items strictly below the threshold bin\n # [4] fbs: item count of the threshold bin itself\n # [5] done: selection complete, remaining stages no-op\n # [6] need: slots still to fill this stage (target - found)\n\n if cutlass.const_expr(self._per_token_nvp):\n # Clamp the device-side count to the score tensor's own block extent;\n # see TopKSelectCountRankSm12x. Nothing on the host bounds it, and an\n # out-of-range entry would read mBits past its end and emit block\n # indices the attend kernel cannot address.\n nvp = cutlass.max(\n cutlass.Int32(0),\n cutlass.min(mNumValidPages[q], cutlass.Int32(mBits.shape[1])),\n )\n else:\n nvp = num_valid_pages\n\n # Shrink the forced region to fit a token whose causal extent is\n # shorter than it; see TopKSelectCountRankSm12x.\n fb = cutlass.min(force_begin, nvp)\n fe = cutlass.min(force_end, nvp - fb)\n\n mid_lo = fb\n mid_hi = nvp - fe\n n_forced = fb + fe\n target = cutlass.Int32(self._topk) - n_forced\n\n n_groups = _NUM_BINS // _GROUP\n\n # Forced sink/window blocks bypass ranking; emit slots start after them.\n if tid == 0:\n w = cutlass.Int32(0)\n i = cutlass.Int32(0)\n while i < fb:\n sel[w] = i\n w += 1\n i += 1\n j = cutlass.Int32(0)\n while j < fe:\n sel[w] = mid_hi + j\n w += 1\n j += 1\n k = w\n while k < self._topk:\n sel[k] = cutlass.Int32(_SENTINEL)\n k += 1\n scal[0] = cutlass.Int32(0) # found\n pat[0] = cutlass.Uint32(0) # accumulated radix pattern\n # If every slot is forced (target <= 0) there is no middle to rank.\n scal[5] = (\n cutlass.Int32(0) if target > cutlass.Int32(0) else cutlass.Int32(1)\n )\n cute.arch.barrier()\n\n # MSD radix-select stages (high -> mid -> low 10 bits). The Python loop is\n # unrolled at trace time so `step` specializes statically; `done` is\n # block-uniform, so the `if dn == 0:` guards keep the barriers balanced.\n for step in (1, 2, 3):\n shift = _STAGE_SHIFT[step]\n\n if tid == 0:\n if scal[5] == cutlass.Int32(0):\n if cutlass.const_expr(step == 2):\n pat[0] = cutlass.Uint32(scal[2]) << cutlass.Uint32(22)\n elif cutlass.const_expr(step == 3):\n pat[0] = pat[0] | (\n cutlass.Uint32(scal[2]) << cutlass.Uint32(12)\n )\n scal[1] = cutlass.Int32(0) # stage_count\n scal[6] = target - scal[0] # need (remaining to select)\n cute.arch.barrier()\n\n pattern = pat[0]\n\n dn = scal[5]\n if dn == cutlass.Int32(0):\n bb = tid\n while bb < _NUM_BINS:\n hist[bb] = cutlass.Int32(0)\n bb += _KTHREADS\n cute.arch.barrier()\n\n dn = scal[5]\n if dn == cutlass.Int32(0):\n b = mid_lo + tid\n while b < mid_hi:\n okey = self._radix_key(mBits[h, b, q])\n binv = cutlass.Int32((okey >> shift) & cutlass.Uint32(0x3FF))\n if cutlass.const_expr(step == 1):\n _atomic_add_i32(1, hist.iterator + binv)\n else:\n mshift = _MATCH_SHIFT[step]\n if (\n (okey ^ pattern) >> cutlass.Uint32(mshift)\n ) == cutlass.Uint32(0):\n _atomic_add_i32(1, hist.iterator + binv)\n b += _KTHREADS\n cute.arch.barrier()\n\n # 2-level threshold scan: find the histogram bin where the running\n # count crosses `need`, with a critical serial path of ~ 2*_GROUP\n # bins instead of _NUM_BINS.\n dn = scal[5]\n if dn == cutlass.Int32(0):\n # Phase A: each thread sums one contiguous _GROUP-bin group.\n if tid < n_groups:\n gs = cutlass.Int32(0)\n gi = cutlass.Int32(0)\n gbase = tid * _GROUP\n while gi < _GROUP:\n gs += hist[gbase + gi]\n gi += 1\n grpsum[tid] = gs\n cute.arch.barrier()\n\n dn = scal[5]\n if dn == cutlass.Int32(0):\n if tid == 0:\n need = scal[6]\n # Phase B: find the group whose running count crosses `need`.\n running = cutlass.Int32(0)\n grp = cutlass.Int32(n_groups)\n base_grp = cutlass.Int32(0)\n gg = cutlass.Int32(0)\n while gg < n_groups:\n s = grpsum[gg]\n if (\n (grp == n_groups)\n and (running < need)\n and (running + s >= need)\n ):\n grp = gg\n base_grp = running\n running += s\n gg += 1\n # Default (need unreachable): all candidates selected.\n threshold = cutlass.Int32(_NUM_BINS)\n base = running\n fbs = cutlass.Int32(0)\n # Phase C: refine within the found group.\n if grp < n_groups:\n run2 = base_grp\n bi = grp * _GROUP\n end = bi + _GROUP\n while bi < end:\n c = hist[bi]\n if (\n (threshold == _NUM_BINS)\n and (run2 < need)\n and (run2 + c >= need)\n ):\n threshold = bi\n base = run2\n fbs = c\n run2 += c\n bi += 1\n scal[2] = threshold\n scal[3] = base\n scal[4] = fbs\n if cutlass.const_expr(step == 3):\n # Terminal stage emits sub-threshold and threshold-bin\n # candidates into disjoint ranges: sub-threshold via `found`\n # [found, found+base), threshold-bin here [found+base, target).\n scal[1] = scal[0] + base\n cute.arch.barrier()\n\n # Bins below the threshold emit directly; the threshold bin is staged\n # for the next stage (stage 3 emits it directly).\n dn = scal[5]\n if dn == cutlass.Int32(0):\n threshold = scal[2]\n fbs = scal[4]\n fits = fbs <= cutlass.Int32(_STAGE_CAP)\n b = mid_lo + tid\n while b < mid_hi:\n okey = self._radix_key(mBits[h, b, q])\n # `proceed` is always a dynamic (uniform-true for stage 1)\n # bool so the body below traces once, not per static branch.\n if cutlass.const_expr(step == 1):\n proceed = okey == okey\n else:\n mshift = _MATCH_SHIFT[step]\n proceed = (\n (okey ^ pattern) >> cutlass.Uint32(mshift)\n ) == cutlass.Uint32(0)\n if proceed:\n binv = cutlass.Int32((okey >> shift) & cutlass.Uint32(0x3FF))\n if binv < threshold:\n slot = _atomic_add_i32(1, scal.iterator + 0)\n if n_forced + slot < cutlass.Int32(self._topk):\n sel[n_forced + slot] = b\n elif binv == threshold:\n if cutlass.const_expr(step == 3):\n # Terminal stage: residual ties (equal in bits 31..2)\n # emit via the separate counter, capped at topk slots.\n slot = _atomic_add_i32(1, scal.iterator + 1)\n if n_forced + slot < cutlass.Int32(self._topk):\n sel[n_forced + slot] = b\n else:\n if fits:\n s = _atomic_add_i32(1, scal.iterator + 1)\n if s < cutlass.Int32(_STAGE_CAP):\n stage_key[s] = okey\n stage_idx[s] = b\n b += _KTHREADS\n cute.arch.barrier()\n\n if cutlass.const_expr(step != 3):\n # Rank the staged threshold-bin items; only the best (need - base)\n # of them, by rank, still fit in the selection.\n dn = scal[5]\n if dn == cutlass.Int32(0):\n fbs = scal[4]\n if fbs <= cutlass.Int32(_STAGE_CAP):\n stage_count = scal[1]\n base = scal[3]\n need = scal[6]\n ii = tid\n while ii < stage_count:\n ti = stage_key[ii]\n rank = cutlass.Int32(0)\n jj = cutlass.Int32(0)\n while jj < stage_count:\n tj = stage_key[jj]\n # Higher score == smaller key; ties by stage index\n if (ti > tj) or ((ti == tj) and (ii < jj)):\n rank += 1\n jj += 1\n if base + rank < need:\n slot = _atomic_add_i32(1, scal.iterator + 0)\n if n_forced + slot < cutlass.Int32(self._topk):\n sel[n_forced + slot] = stage_idx[ii]\n ii += _KTHREADS\n cute.arch.barrier()\n\n # Mark done if this stage's threshold bin fit the buffer. Thread 0\n # only: guarding all threads on scal[5] would race this write\n # (read vs write of the same slot, no barrier between).\n if tid == 0:\n if scal[5] == cutlass.Int32(0):\n if scal[4] <= cutlass.Int32(_STAGE_CAP):\n scal[5] = cutlass.Int32(1)\n cute.arch.barrier()\n else:\n if tid == 0:\n scal[5] = cutlass.Int32(1)\n cute.arch.barrier()\n\n # Ascending-by-index sort, then write.\n if tid == 0:\n a = cutlass.Int32(1)\n while a < self._topk:\n key2 = sel[a]\n p = a - 1\n while (p >= 0) and (sel[p] > key2):\n sel[p + 1] = sel[p]\n p -= 1\n sel[p + 1] = key2\n a += 1\n kk = cutlass.Int32(0)\n while kk < self._topk:\n v = sel[kk]\n if v == cutlass.Int32(_SENTINEL):\n v = cutlass.Int32(-1)\n mOut[q, h, kk] = v\n kk += 1\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## 📌 Description\n\nFollow-up to #3655, which enabled MiniMax Sparse Attention (MSA) on SM120/SM121. The indexer (proxy score + top-k, the two ops that pick each query's KV blocks) stayed behind vLLM in a few regimes there. All of the gaps traced to `msa_topk_select` and its wrapper rather than to the proxy kernel:\n\n- At decode with small batches, the top-k launches one CTA per (query, head) row, which is 4 CTAs at batch 1, leaving the GPU nearly idle. At 32k context those rows also fall into the radix kernel, which costs about as much as the proxy itself.\n- At long-sequence prefill, the top-k reads scores with strided accesses, and the radix kernel re-reads them once per digit pass.\n- The packed decode wrappers built the causal-offset tensor with three small torch kernels per call, about as costly as the top-k itself at short sequence lengths.\n\nChanges:\n\n- A new chunked top-k. A partial kernel ranks 64-block chunks independently, one CTA per (query, head, chunk), and a merge kernel then re-ranks the surviving candidates for each row. Both use the same ordering as the existing top-k kernels, so selections are identical. The merge launches with PDL to overlap with the partial kernel.\n- A q-tiled variant of the partial kernel for large grids. It covers 32 queries per CTA so that every score load is one coalesced line, which extends the chunked path to prefill under a 128 MB scratch cap; larger grids keep the radix kernel.\n- The packed decode kernels (bf16 and NVFP4) now compute the causal offset in-kernel when `q_offset` is not given, removing the wrapper's torch launches from the decode path.\n\nThe kernel choice depends only on shapes, so it is CUDA-graph safe; a new test covers graph capture on the chunked path.\n\n### Performance\n\nMeasured as in #3655: median GPU time over CUDA-graph replays (CUPTI), with the L2 cache flushed between replays so one replay cannot reuse the previous replay's data. The baseline is vLLM's MiniMax-M3 Triton MSA kernels on the same GPUs and shapes. Each cell is an RTX PRO 6000 Server / RTX 5080 / GB10 triple, and speedup = vLLM time / FlashInfer time, so higher is better. \"Before\" is main as of #3655. The MTP columns run the same call with 4 draft tokens per request, as in a speculative-decoding verify step.\n\nIndexer decode (proxy + top-k), batch 1:\n\n| S | before | after | before (4-token MTP) | after (4-token MTP) |\n|--:|:--:|:--:|:--:|:--:|\n| 2k | 1.31 / 1.43 / 1.33 | 1.31 / 1.42 / 1.38 | 0.73 / 0.71 / 0.91 | 1.20 / 1.12 / 1.29 |\n| 4k | 1.40 / 1.39 / 1.21 | 1.43 / 1.38 / 1.24 | 0.87 / 0.86 / 1.03 | 1.39 / 1.29 / 1.33 |\n| 8k | 1.18 / 1.10 / 1.08 | 1.28 / 1.22 / 1.10 | 0.82 / 0.90 / 0.95 | 1.26 / 1.34 / 1.11 |\n| 16k | 1.18 / 1.09 / 1.02 | 1.25 / 1.17 / 1.09 | 0.95 / 0.85 / 0.97 | 1.34 / 1.19 / 1.09 |\n| 32k | 0.90 / 0.98 / 0.98 | 1.08 / 1.11 / 1.03 | 0.95 / 0.94 / 0.96 | 1.36 / 1.30 / 1.07 |\n\nIndexer prefill, batch 1 (the 2k and 4k rows keep the old kernels and are unchanged within noise):\n\n| S | before | after |\n|--:|:--:|:--:|\n| 8k | 1.04 / 1.14 / 1.01 | 1.06 / 1.18 / 1.02 |\n| 16k | 1.04 / 1.18 / 1.02 | 1.19 / 1.25 / 1.16 |\n| 32k | 0.90 / 1.08 / 0.89 | 1.16 / 1.28 / 1.19 |\n\nMeasured against the kernels this PR replaces:\n\n- The new top-k alone is 1.4-2.2x faster at decode (batch 1 to 128) and 1.2-2.1x faster at 8k-32k prefill.\n- The proxy kernel is untouched, so shapes where it dominates do not move: at batch 128 the end-to-end ratio stays at 1.00-1.03 vs vLLM.\n- The optional NVFP4 decode path also speeds up because its wrapper sheds the same torch launches.\n\n## 🔍 Related Issues\n\nFollow-up to #3655.\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\nAll 155 tests in `tests/msa_ops/` pass on an RTX 5080 (SM120) after rebasing onto current main. This PR adds tests for:\n\n- the dispatch boundaries between the three top-k kernels\n- selection identity between the chunked and existing kernels, including NaN scores, forced blocks, and the ragged q-tile tail\n- CUDA-graph capture on the chunked path\n- explicit `q_offset` on both packed decode kernels\n\nIt also moves the paged-varlen fp4 test's reference to float32: the kernel's fp4 x scale products never round through bf16, so the bf16-rounded reference misses the 5e-2 tolerance on causal-boundary blocks (16 of 40 seeds on an RTX 5080, including the checked-in seed). The same treatment the other fp4 tests already use.\n\n`compute-sanitizer` racecheck and memcheck are clean on the new kernels.\n\n## Reviewer Notes\n\n- Per-token `num_valid_pages` calls (added by #4324) stay on the single-kernel paths: the chunked kernels' geometry is host-derived from the scalar count.\n- Selection identity across the top-k kernels (same bit-key and tie order) is pinned by tests.\n- The row-per-CTA and q-tiled partial kernels keep separate bodies on purpose: the row-per-CTA binary is production-validated.\n- Deferred for the same reason: skipping the redundant sentinel prefill of the candidate scratch, and sharing the forced-slot fill across the three kernels.\n\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n- **New Features**\n - Added chunked top-k selection for large candidate sets, including tiled execution and forced-page handling.\n - Added optional default query-offset handling for packed decode with right-aligned causal masking.\n - Added tracing support for MSA top-k selection.\n\n- **Bug Fixes**\n - Improved causal masking consistency across packed decode formats.\n - Preserved sentinel results and selected-score correctness during top-k selection.\n\n- **Tests**\n - Expanded coverage for large contexts, query offsets, chunked selection, tracing, and CUDA graph execution.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000 Server\", \"model\": null, \"shape\": \"S=2k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.31, \"optimized\": 1.31, \"stated_speedup\": null, \"speedup\": 1.0}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"S=2k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.43, \"optimized\": 1.42, \"stated_speedup\": null, \"speedup\": 1.007}, {\"scope\": \"kernel\", \"hardware\": \"GB10\", \"model\": null, \"shape\": \"S=2k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.33, \"optimized\": 1.38, \"stated_speedup\": null, \"speedup\": 0.9638}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000 Server\", \"model\": null, \"shape\": \"S=2k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.73, \"optimized\": 1.2, \"stated_speedup\": null, \"speedup\": 0.6083}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"S=2k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.71, \"optimized\": 1.12, \"stated_speedup\": null, \"speedup\": 0.6339}, {\"scope\": \"kernel\", \"hardware\": \"GB10\", \"model\": null, \"shape\": \"S=2k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.91, \"optimized\": 1.29, \"stated_speedup\": null, \"speedup\": 0.7054}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000 Server\", \"model\": null, \"shape\": \"S=4k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.4, \"optimized\": 1.43, \"stated_speedup\": null, \"speedup\": 0.979}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"S=4k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.39, \"optimized\": 1.38, \"stated_speedup\": null, \"speedup\": 1.0072}, {\"scope\": \"kernel\", \"hardware\": \"GB10\", \"model\": null, \"shape\": \"S=4k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.21, \"optimized\": 1.24, \"stated_speedup\": null, \"speedup\": 0.9758}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 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\"optimized\": 1.09, \"stated_speedup\": null, \"speedup\": 0.8899}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000 Server\", \"model\": null, \"shape\": \"S=32k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.9, \"optimized\": 1.08, \"stated_speedup\": null, \"speedup\": 0.8333}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"S=32k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.98, \"optimized\": 1.11, \"stated_speedup\": null, \"speedup\": 0.8829}, {\"scope\": \"kernel\", \"hardware\": \"GB10\", \"model\": null, \"shape\": \"S=32k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.98, \"optimized\": 1.03, \"stated_speedup\": null, \"speedup\": 0.9515}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000 Server\", \"model\": null, \"shape\": \"S=32k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.95, \"optimized\": 1.36, \"stated_speedup\": null, \"speedup\": 0.6985}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"S=32k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.94, \"optimized\": 1.3, \"stated_speedup\": null, \"speedup\": 0.7231}, {\"scope\": \"kernel\", \"hardware\": \"GB10\", \"model\": null, \"shape\": \"S=32k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.96, \"optimized\": 1.07, \"stated_speedup\": null, \"speedup\": 0.8972}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000 Server\", \"model\": null, \"shape\": \"S=8k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.04, \"optimized\": 1.06, \"stated_speedup\": null, \"speedup\": 0.9811}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"S=8k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.14, \"optimized\": 1.18, \"stated_speedup\": null, \"speedup\": 0.9661}, {\"scope\": \"kernel\", \"hardware\": \"GB10\", \"model\": null, \"shape\": \"S=8k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.01, \"optimized\": 1.02, \"stated_speedup\": null, \"speedup\": 0.9902}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000 Server\", \"model\": null, \"shape\": \"S=16k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.04, \"optimized\": 1.19, \"stated_speedup\": null, \"speedup\": 0.8739}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"S=16k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, 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\"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.89, \"optimized\": 1.19, \"stated_speedup\": null, \"speedup\": 0.7479}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": null, \"shape\": null, \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.4, \"speedup\": 1.4}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": null, \"shape\": null, \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 2.2, \"speedup\": 2.2}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": null, \"shape\": null, \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.2, \"speedup\": 1.2}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": null, \"shape\": null, \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 2.1, \"speedup\": 2.1}]"},"kernel_speedup":{"kind":"number","value":0.8972,"string":"0.8972"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1076,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"8c5347726f30063fa1c17c4e81e75d509936d610"},"date":{"kind":"string","value":"2026-08-25T22:12:51-04:00"},"pr_number":{"kind":"number","value":4030,"string":"4,030"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/4030"},"title":{"kind":"string","value":"perf(msa): chunked top-k and in-kernel causal offsets for the SM12x indexer (#4030)"},"message":{"kind":"string","value":"perf(msa): chunked top-k and in-kernel causal offsets for the SM12x indexer (#4030)\n\n## 📌 Description\n\nFollow-up to #3655, which enabled MiniMax Sparse Attention (MSA) on\nSM120/SM121. The indexer (proxy score + top-k, the two ops that pick\neach query's KV blocks) stayed behind vLLM in a few regimes there. All\nof the gaps traced to `msa_topk_select` and its wrapper rather than to\nthe proxy kernel:\n\n- At decode with small batches, the top-k launches one CTA per (query,\nhead) row, which is 4 CTAs at batch 1, leaving the GPU nearly idle. At\n32k context those rows also fall into the radix kernel, which costs\nabout as much as the proxy itself.\n- At long-sequence prefill, the top-k reads scores with strided\naccesses, and the radix kernel re-reads them once per digit pass.\n- The packed decode wrappers built the causal-offset tensor with three\nsmall torch kernels per call, about as costly as the top-k itself at\nshort sequence lengths.\n\nChanges:\n\n- A new chunked top-k. A partial kernel ranks 64-block chunks\nindependently, one CTA per (query, head, chunk), and a merge kernel then\nre-ranks the surviving candidates for each row. Both use the same\nordering as the existing top-k kernels, so selections are identical. The\nmerge launches with PDL to overlap with the partial kernel.\n- A q-tiled variant of the partial kernel for large grids. It covers 32\nqueries per CTA so that every score load is one coalesced line, which\nextends the chunked path to prefill under a 128 MB scratch cap; larger\ngrids keep the radix kernel.\n- The packed decode kernels (bf16 and NVFP4) now compute the causal\noffset in-kernel when `q_offset` is not given, removing the wrapper's\ntorch launches from the decode path.\n\nThe kernel choice depends only on shapes, so it is CUDA-graph safe; a\nnew test covers graph capture on the chunked path.\n\n### Performance\n\nMeasured as in #3655: median GPU time over CUDA-graph replays (CUPTI),\nwith the L2 cache flushed between replays so one replay cannot reuse the\nprevious replay's data. The baseline is vLLM's MiniMax-M3 Triton MSA\nkernels on the same GPUs and shapes. Each cell is an RTX PRO 6000 Server\n/ RTX 5080 / GB10 triple, and speedup = vLLM time / FlashInfer time, so\nhigher is better. \"Before\" is main as of #3655. The MTP columns run the\nsame call with 4 draft tokens per request, as in a speculative-decoding\nverify step.\n\nIndexer decode (proxy + top-k), batch 1:\n\n| S | before | after | before (4-token MTP) | after (4-token MTP) |\n|--:|:--:|:--:|:--:|:--:|\n| 2k | 1.31 / 1.43 / 1.33 | 1.31 / 1.42 / 1.38 | 0.73 / 0.71 / 0.91 |\n1.20 / 1.12 / 1.29 |\n| 4k | 1.40 / 1.39 / 1.21 | 1.43 / 1.38 / 1.24 | 0.87 / 0.86 / 1.03 |\n1.39 / 1.29 / 1.33 |\n| 8k | 1.18 / 1.10 / 1.08 | 1.28 / 1.22 / 1.10 | 0.82 / 0.90 / 0.95 |\n1.26 / 1.34 / 1.11 |\n| 16k | 1.18 / 1.09 / 1.02 | 1.25 / 1.17 / 1.09 | 0.95 / 0.85 / 0.97 |\n1.34 / 1.19 / 1.09 |\n| 32k | 0.90 / 0.98 / 0.98 | 1.08 / 1.11 / 1.03 | 0.95 / 0.94 / 0.96 |\n1.36 / 1.30 / 1.07 |\n\nIndexer prefill, batch 1 (the 2k and 4k rows keep the old kernels and\nare unchanged within noise):\n\n| S | before | after |\n|--:|:--:|:--:|\n| 8k | 1.04 / 1.14 / 1.01 | 1.06 / 1.18 / 1.02 |\n| 16k | 1.04 / 1.18 / 1.02 | 1.19 / 1.25 / 1.16 |\n| 32k | 0.90 / 1.08 / 0.89 | 1.16 / 1.28 / 1.19 |\n\nMeasured against the kernels this PR replaces:\n\n- The new top-k alone is 1.4-2.2x faster at decode (batch 1 to 128) and\n1.2-2.1x faster at 8k-32k prefill.\n- The proxy kernel is untouched, so shapes where it dominates do not\nmove: at batch 128 the end-to-end ratio stays at 1.00-1.03 vs vLLM.\n- The optional NVFP4 decode path also speeds up because its wrapper\nsheds the same torch launches.\n\n## 🔍 Related Issues\n\nFollow-up to #3655.\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the\npre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\nAll 155 tests in `tests/msa_ops/` pass on an RTX 5080 (SM120) after\nrebasing onto current main. This PR adds tests for:\n\n- the dispatch boundaries between the three top-k kernels\n- selection identity between the chunked and existing kernels, including\nNaN scores, forced blocks, and the ragged q-tile tail\n- CUDA-graph capture on the chunked path\n- explicit `q_offset` on both packed decode kernels\n\nIt also moves the paged-varlen fp4 test's reference to float32: the\nkernel's fp4 x scale products never round through bf16, so the\nbf16-rounded reference misses the 5e-2 tolerance on causal-boundary\nblocks (16 of 40 seeds on an RTX 5080, including the checked-in seed).\nThe same treatment the other fp4 tests already use.\n\n`compute-sanitizer` racecheck and memcheck are clean on the new kernels.\n\n## Reviewer Notes\n\n- Per-token `num_valid_pages` calls (added by #4324) stay on the\nsingle-kernel paths: the chunked kernels' geometry is host-derived from\nthe scalar count.\n- Selection identity across the top-k kernels (same bit-key and tie\norder) is pinned by tests.\n- The row-per-CTA and q-tiled partial kernels keep separate bodies on\npurpose: the row-per-CTA binary is production-validated.\n- Deferred for the same reason: skipping the redundant sentinel prefill\nof the candidate scratch, and sharing the forced-slot fill across the\nthree kernels.\n\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n- **New Features**\n- Added chunked top-k selection for large candidate sets, including\ntiled execution and forced-page handling.\n- Added optional default query-offset handling for packed decode with\nright-aligned causal masking.\n - Added tracing support for MSA top-k selection.\n\n- **Bug Fixes**\n - Improved causal masking consistency across packed decode formats.\n- Preserved sentinel results and selected-score correctness during top-k\nselection.\n\n- **Tests**\n- Expanded coverage for large contexts, query offsets, chunked\nselection, tracing, and CUDA graph execution.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n\n---------\n\nCo-authored-by: Claude Fable 5 <noreply@anthropic.com>"},"path":{"kind":"string","value":"flashinfer/msa_ops/proxy_score.py"},"language":{"kind":"string","value":"cute_dsl"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"\"\"\"\nCopyright (c) 2026 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\"\"\"\n\nimport functools\nfrom typing import Optional, Tuple, Union\n\nimport torch\n\nfrom ..api_logging import flashinfer_api\nfrom ..autotuner import AutoTuner, TunableRunner, TuningConfig\nfrom ..trace.templates.msa import (\n msa_proxy_score_fp4_trace,\n msa_proxy_score_trace,\n)\nfrom ..utils import get_device_sm_count, is_sm12x_supported\nfrom ._common import _BLK_KV\n\n# NVFP4 scale granularity: one e4m3 block scale per 16 e2m1 elements.\n_SF_VEC_SIZE = 16\n\n\ndef _resolve_proxy_dims(\n cu_seqlens_q, k_len_or_cu, max_seqlen_q, max_k_tiles, output, k_is_lengths=False\n):\n \"\"\"Resolve grid dims ``(max_seqlen_q, max_k_tiles)`` as Python ints; deriving\n them reads ``cu_seqlens`` on host, so under CUDA-graph capture we raise.\n\n ``k_len_or_cu`` is per-request lengths when ``k_is_lengths`` (the paged\n path), else a prefix sum.\"\"\"\n if max_k_tiles is None and output is not None:\n max_k_tiles = int(output.shape[1])\n if max_seqlen_q is not None and max_k_tiles is not None:\n return max_seqlen_q, max_k_tiles\n if torch.cuda.is_current_stream_capturing():\n raise ValueError(\n \"msa_proxy_score[_fp4] needs max_seqlen_q and max_k_tiles during CUDA \"\n \"graph capture (deriving them from cu_seqlens would sync the stream). \"\n \"Pass both (computed once at plan time) or pre-allocate `output`.\"\n )\n if max_seqlen_q is None:\n cu_q_cpu = cu_seqlens_q.cpu()\n max_seqlen_q = int((cu_q_cpu[1:] - cu_q_cpu[:-1]).max().item())\n if max_k_tiles is None:\n k_cpu = k_len_or_cu.cpu()\n seqlens_k = k_cpu if k_is_lengths else (k_cpu[1:] - k_cpu[:-1])\n max_k_tiles = int((seqlens_k.max().item() + _BLK_KV - 1) // _BLK_KV)\n return max_seqlen_q, max_k_tiles\n\n\ndef _proxy_split_k(\n base_ctas: int,\n max_k_tiles: int,\n device,\n *,\n wave_target: float,\n gate_factor: float,\n ceil_to_target: bool,\n) -> int:\n \"\"\"KV-block split factor that fills the SMs when the base proxy grid is small\n (long context, low batch). Splits need no reduction: the per-(head, kv_block,\n query) output means each split writes disjoint columns. Returns 1 once the\n base grid already covers ``gate_factor`` SM-waves.\"\"\"\n if base_ctas <= 0 or max_k_tiles <= 1:\n return 1\n num_sms = get_device_sm_count(device)\n if base_ctas >= gate_factor * num_sms:\n return 1\n target = wave_target * num_sms\n splits = (\n -(-int(target) // base_ctas) if ceil_to_target else round(target / base_ctas)\n )\n return max(1, min(splits, max_k_tiles))\n\n\n# bf16 split-K heuristic, tuned empirically: target ~1.5 waves and round (the\n# Q reload per split makes over-splitting regress).\n_proxy_split_k_bf16 = functools.partial(\n _proxy_split_k, wave_target=1.5, gate_factor=1.0, ceil_to_target=False\n)\n\n\n@functools.lru_cache(maxsize=None)\ndef _split_k_makespan_argmin(\n base_ctas: int, max_k_tiles: int, resident_ctas: int\n) -> int:\n \"\"\"Split factor minimizing a makespan model: full resident-CTA waves times\n per-split work, with ~one KV block of fixed per-CTA overhead (launch + Q\n load). Ties break to the smaller split (fewer Q reloads). A model rather\n than a wave target because the optimum shifts between filling residency\n exactly (moderate batch), max split (batch 1), and no split (large batch,\n short kv) -- no single target covers all three regimes.\"\"\"\n best_ns, best_cost = 1, None\n for ns in range(1, min(max_k_tiles, 4096) + 1):\n waves = -(-(base_ctas * ns) // resident_ctas)\n cost = waves * (-(-max_k_tiles // ns) + 1)\n if best_cost is None or cost < best_cost:\n best_ns, best_cost = ns, cost\n return best_ns\n\n\ndef _proxy_split_k_fp4(base_ctas: int, max_k_tiles: int, device) -> int:\n \"\"\"fp4 split-K: 4-bit K reads make splits cheap, so pick by the makespan\n model at the kernel's 2-CTA/SM residency (see _MIN_BLOCKS_PER_MP).\"\"\"\n if base_ctas <= 0 or max_k_tiles <= 1:\n return 1\n return _split_k_makespan_argmin(\n base_ctas, max_k_tiles, 2 * get_device_sm_count(device)\n )\n\n\nclass _ProxySplitKRunner(TunableRunner):\n \"\"\"Autotunes the proxy kv-block split factor: ``tactic`` *is* the split\n factor (a runtime arg, so one compiled kernel covers every candidate).\"\"\"\n\n def __init__(\n self,\n call_fn,\n *,\n max_seqlen_q,\n max_k_tiles,\n base_ctas,\n device,\n heuristic,\n causal,\n paged,\n reduce_heads,\n ):\n # call_fn(inputs, num_splits) -> output; lets one runner serve both the\n # bf16 and (longer-signature) fp4 proxy invocations.\n self._call = call_fn\n self._msq = int(max_seqlen_q)\n self._mkt = int(max_k_tiles)\n self._base = int(base_ctas)\n self._device = device\n self._heuristic = heuristic # callable(base_ctas, max_k_tiles, device) -> int\n self._causal = bool(causal)\n self._paged = bool(paged)\n self._reduce = bool(reduce_heads)\n\n def __hash__(self):\n return hash(type(self))\n\n def get_valid_tactics(self, inputs, profile):\n # Powers of two up to ~4 SM-waves, capped by max_k_tiles; always include\n # the closed-form heuristic so a tuned op is never worse than eager.\n num_sms = get_device_sm_count(self._device)\n cap = min(self._mkt, max(1, -(-4 * num_sms // max(self._base, 1))))\n cands = {s for s in (1, 2, 4, 8, 16, 32) if s <= cap}\n cands.add(self._heuristic(self._base, self._mkt, self._device))\n return sorted(cands)\n\n def get_cache_key_extras(self, inputs):\n # max_seqlen_q / max_k_tiles are varlen-derived (not in any tensor shape),\n # so they must key the cache; causal/paged/reduce flip the work pattern.\n return (self._causal, self._paged, self._reduce, self._msq, self._mkt)\n\n def forward(self, inputs, tactic: int = -1, do_preparation: bool = False, **kwargs):\n # tactic == -1 falls back to the closed-form heuristic, so eager\n # (un-tuned) behavior is unchanged.\n ns = (\n tactic\n if tactic >= 0\n else self._heuristic(self._base, self._mkt, self._device)\n )\n return self._call(inputs, int(ns))\n\n\n# (op, shape) keys that already went through the autotuner in this process. Until\n# a shape is tuned the proxy uses its closed-form heuristic and skips choose_one,\n# whose per-call lock/bookkeeping (~tens of us) would dominate the tiny low-batch\n# decode.\n_PROXY_TUNED: set = set()\n\n\ndef _proxy_tuned_key(\n op_name, *, causal, paged, reduce_heads, max_seqlen_q, max_k_tiles, base_ctas\n):\n # base_ctas folds in batch/heads/max_seqlen_q, so this matches the autotuner's\n # own cache granularity (shape + get_cache_key_extras) closely enough to gate on.\n return (\n op_name,\n bool(causal),\n bool(paged),\n bool(reduce_heads),\n int(max_seqlen_q),\n int(max_k_tiles),\n int(base_ctas),\n )\n\n\ndef _run_proxy_autotuned(\n op_name,\n call_fn,\n tensors,\n *,\n max_seqlen_q,\n max_k_tiles,\n base_ctas,\n device,\n heuristic,\n causal,\n paged,\n reduce_heads,\n):\n \"\"\"Run the proxy with an autotuned split factor; un-tuned shapes use the\n closed-form heuristic directly and skip the autotuner entirely.\"\"\"\n tuner = AutoTuner.get()\n tuning = tuner.is_tuning_mode\n tuned_key = _proxy_tuned_key(\n op_name,\n causal=causal,\n paged=paged,\n reduce_heads=reduce_heads,\n max_seqlen_q=max_seqlen_q,\n max_k_tiles=max_k_tiles,\n base_ctas=base_ctas,\n )\n if tuning:\n _PROXY_TUNED.add(tuned_key)\n elif tuned_key not in _PROXY_TUNED:\n call_fn(tensors, heuristic(base_ctas, max_k_tiles, device))\n return\n\n runner = _ProxySplitKRunner(\n call_fn,\n max_seqlen_q=max_seqlen_q,\n max_k_tiles=max_k_tiles,\n base_ctas=base_ctas,\n device=device,\n heuristic=heuristic,\n causal=causal,\n paged=paged,\n reduce_heads=reduce_heads,\n )\n # No DynamicTensorSpec: the autotuner would synthesize a shape-correct but\n # value-invalid varlen cu_seqlens; with static inputs it profiles the\n # candidates on the caller's real (valid) tensors.\n runner_sel, tactic = tuner.choose_one(op_name, [runner], TuningConfig(), tensors)\n runner_sel(inputs=tensors, tactic=tactic)\n\n\n@functools.cache\ndef _proxy_dummies(device_index: int):\n # Signature fillers for paths that never read them; cached so repeat decode\n # calls do not launch fill kernels.\n dev = torch.device(\"cuda\", device_index)\n return (\n torch.zeros((1, 1), dtype=torch.int32, device=dev),\n torch.zeros(1, dtype=torch.int32, device=dev),\n )\n\n\n@flashinfer_api(trace=msa_proxy_score_trace)\ndef msa_proxy_score(\n q: torch.Tensor,\n k: torch.Tensor,\n cu_seqlens_q: torch.Tensor,\n cu_seqlens_k: Optional[torch.Tensor] = None,\n *,\n page_table: Optional[torch.Tensor] = None,\n seqused_k: Optional[torch.Tensor] = None,\n causal: bool = True,\n max_seqlen_q: Optional[int] = None,\n max_k_tiles: Optional[int] = None,\n output: Optional[torch.Tensor] = None,\n reduce_heads: bool = False,\n q_offset=None,\n) -> torch.Tensor:\n \"\"\"MSA dense proxy pass for SM120/SM121: per-KV-block max attention\n logits.\n\n Computes ``max_score[h, t, q]``, the maximum of the unscaled,\n causally-masked ``Q K^T`` logits over the 128 tokens of KV block ``t``,\n for every query token and query head. The output feeds directly into\n :func:`msa_topk_select`. KV blocks beyond a sequence's valid range, or\n entirely above the causal limit, yield ``-inf``.\n\n There is no softmax and no V: this is MSA pipeline stage 1.\n\n Single-token decode uses a dim-parallel scalar schedule that streams\n index-K straight to registers. Short multi-token decode (MTP) uses a\n head-fused packed schedule that scores all ``group_size`` heads of a\n kv_head from one shared index-K read. Prefill uses the general schedule;\n see the dispatch below for the exact regime bounds.\n\n Parameters\n ----------\n q : torch.Tensor\n ``(total_q, num_qo_heads, 128)``, bf16 or fp16 (the cheap proxy Q).\n May be fp8 E4M3 when ``k`` is fp8: decode shapes consume it natively,\n other shapes upconvert it once internally.\n k : torch.Tensor\n Flat ``(total_k, num_kv_heads, 128)`` with ``cu_seqlens_k``, or\n paged ``(num_pages, num_kv_heads, 128, 128)`` with ``page_table`` +\n ``seqused_k``. May be fp8 E4M3 (upconverted in-kernel).\n ``num_qo_heads`` must be a multiple of ``num_kv_heads``.\n cu_seqlens_q : torch.Tensor\n ``(batch_size + 1,)`` int32 cumulative query lengths.\n cu_seqlens_k : torch.Tensor, optional\n ``(batch_size + 1,)`` int32 cumulative KV lengths. Required for flat\n KV layout and unused for paged KV layout.\n page_table : torch.Tensor, optional\n Page-table mapping for paged KV layout. Required together with\n ``seqused_k`` when ``k`` is paged.\n seqused_k : torch.Tensor, optional\n Per-sequence valid KV-token counts. Required together with\n ``page_table`` for paged KV layout.\n causal : bool\n Right-aligned causal masking, applied *before* the block max.\n max_seqlen_q : int, optional\n Maximum query length. Required by some CUDA Graph / compilation paths.\n max_k_tiles : int, optional\n Number of KV-block columns in the output; defaults to the maximum\n ``ceil(seqlen_k / 128)`` over the batch.\n output : torch.Tensor, optional\n Pre-allocated float32 output. Shape is\n ``(num_qo_heads, max_k_tiles, total_q)`` normally, or\n ``(1, max_k_tiles, total_q)`` when ``reduce_heads=True``.\n reduce_heads : bool\n If ``True``, max-reduce the per-head ``max_score`` over the query-head\n axis and return a single ``(1, max_k_tiles, total_q)`` score. Use this\n when the query heads are an indexer's proxy heads that collapse to one\n shared block selection per query (MiniMax-M3 indexer semantics).\n Defaults to ``False``: per-head ``max_score``, where each head selects\n its own blocks.\n The reduction is currently a post-kernel ``amax`` over the per-head\n buffer (the kernel is one CTA per head, so a cross-head epilogue would\n need cross-CTA float atomics); folding it into the kernel is a possible\n future optimization (saves materializing the per-head buffer).\n q_offset : int or torch.Tensor, optional\n Optional query-position offset used by the causal alignment logic.\n\n Returns\n -------\n torch.Tensor\n Float32 ``max_score`` ready for :func:`msa_topk_select`:\n ``(num_qo_heads, max_k_tiles, total_q)``, or\n ``(1, max_k_tiles, total_q)`` when ``reduce_heads=True``.\n \"\"\"\n import cutlass\n import cutlass.cute as cute\n\n from .cute_dsl.proxy_score_sm12x import (\n MsaProxyScoreDecodeKeyMajorSm12x,\n MsaProxyScoreDecodePackedFp8Sm12x,\n MsaProxyScoreDecodePackedSm12x,\n MsaProxyScoreDecodeStreamSm12x,\n MsaProxyScoreSm12x,\n )\n from ._common import (\n _compile_cache,\n _cutlass_dtype,\n _fake,\n _q_offset_tensor,\n )\n\n if not is_sm12x_supported(q.device):\n raise RuntimeError(\"msa_proxy_score requires SM120 or SM121 and CUDA >= 12.8\")\n q_fp8 = q.dtype == torch.float8_e4m3fn\n if q.dtype not in (torch.bfloat16, torch.float16) and not q_fp8:\n raise ValueError(f\"q must be bf16, fp16, or fp8 e4m3, got {q.dtype}\")\n total_q, num_qo_heads, head_dim = q.shape\n if head_dim != 128:\n raise ValueError(f\"head_dim must be 128, got {head_dim}\")\n num_kv_heads = k.shape[1]\n if num_qo_heads % num_kv_heads != 0:\n raise ValueError(\"num_qo_heads must be a multiple of num_kv_heads\")\n kv_fp8 = k.dtype == torch.float8_e4m3fn\n if q_fp8 and not kv_fp8:\n raise ValueError(\"fp8 q requires fp8 k\")\n if not kv_fp8 and k.dtype != q.dtype:\n raise ValueError(\"k dtype must match q (or be float8_e4m3fn)\")\n dev = q.device\n\n paged = page_table is not None\n if paged:\n if seqused_k is None:\n raise ValueError(\"paged proxy requires seqused_k\")\n if k.ndim != 4 or k.shape[2] != _BLK_KV or k.shape[3] != head_dim:\n raise ValueError(\n f\"paged k must be (num_pages, num_kv_heads, {_BLK_KV}, {head_dim})\"\n )\n batch_size = seqused_k.numel()\n # Paged addressing comes entirely from page_table, so the kernel needs\n # only each request's length. Pass seqused_k through instead of building\n # a prefix sum (zeros + cumsum + slice-copy on every call) for the\n # kernel to difference back apart; `paged` tells it which form this is.\n k_len_or_cu = seqused_k if seqused_k.device == dev else seqused_k.to(dev)\n k_len_or_cu = k_len_or_cu.contiguous()\n pt_dev = page_table.contiguous()\n else:\n if cu_seqlens_k is None:\n raise ValueError(\"flat proxy requires cu_seqlens_k\")\n if k.ndim != 3:\n raise ValueError(\"flat k must be (total_k, num_kv_heads, head_dim)\")\n k_len_or_cu = cu_seqlens_k.to(dev)\n pt_dev = _proxy_dummies(dev.index)[0]\n batch_size = k_len_or_cu.numel() - 1\n\n cu_q_dev = cu_seqlens_q.to(dev)\n max_seqlen_q, max_k_tiles = _resolve_proxy_dims(\n cu_seqlens_q, k_len_or_cu, max_seqlen_q, max_k_tiles, output, k_is_lengths=paged\n )\n\n per_head_shape = (num_qo_heads, max_k_tiles, total_q)\n final_shape = (1, max_k_tiles, total_q) if reduce_heads else per_head_shape\n if output is not None:\n if output.shape != final_shape:\n raise ValueError(f\"output must be {final_shape}\")\n if output.dtype != torch.float32:\n raise ValueError(\"output must be float32\")\n\n # The kernel always writes the per-head buffer; reduce_heads then collapses\n # it. When not reducing and an output was given, that buffer *is* the output.\n if reduce_heads or output is None:\n per_head = torch.empty(per_head_shape, dtype=torch.float32, device=dev)\n else:\n per_head = output\n\n group_size = num_qo_heads // num_kv_heads\n _PACK_ROWS = 64 # bf16 MMA q-tile rows (== m_block_size)\n p = 1\n while p < max_seqlen_q:\n p *= 2\n # Fused tiles of at most 32 rows (group_size * next_pow2(q_len)) take the\n # key-major TMA schedule (see MsaProxyScoreDecodeKeyMajorSm12x); larger\n # fused tiles keep the row-major/key-split schedules. bf16 single-token\n # decode stays on the dim-parallel stream schedule (see\n # MsaProxyScoreDecodeStreamSm12x), which also covers the group sizes\n # key-major cannot take; fp8 single-token decode goes key-major, whose\n # in-register convert beats the stream schedule's per-element CUDA-core\n # convert. total_q == batch_size guarantees exactly one q token per\n # request, which the stream schedule's token == batch indexing relies on.\n keymajor_ok = (\n group_size >= 2 and _PACK_ROWS % group_size == 0 and group_size * p <= 32\n )\n use_stream = (\n max_seqlen_q == 1\n and total_q == batch_size\n and group_size <= 8\n and not (kv_fp8 and keymajor_ok)\n )\n qoff_default = q_offset is None\n\n # Head-fused decode path: pack group_size heads x pack_q_len q-tokens into one\n # 64-row MMA tile so index-K is read once per (batch, kv_head). Outside the regime\n # (prefill, group_size not dividing 64) use the general schedule.\n use_packed = (\n not use_stream\n and group_size >= 2\n and _PACK_ROWS % group_size == 0\n and max_seqlen_q <= _PACK_ROWS // group_size\n )\n use_keymajor = use_packed and keymajor_ok\n if use_keymajor:\n pack_q_len = p\n else:\n pack_q_len = _PACK_ROWS // group_size if use_packed else 0\n\n # fp8 q (the vLLM M3 fp8-cache contract) is consumed natively only by the\n # key-major schedule; other shapes upconvert once (e4m3 -> bf16 is\n # lossless) and take their usual route.\n if q_fp8 and not use_keymajor:\n q = q.to(torch.bfloat16)\n q_fp8 = False\n\n # Right-aligned decode on the stream and key-major paths computes the\n # causal limit in-kernel, so no offset tensor (and its build kernels,\n # which dominate at batch 1) is needed.\n if (use_stream or use_keymajor) and qoff_default:\n qoff_dev = _proxy_dummies(dev.index)[1]\n else:\n qoff_dev = _q_offset_tensor(\n q_offset, cu_q_dev, k_len_or_cu, dev, k_is_lengths=paged\n )\n\n # group_size and pack_q_len are constexpr-baked into the decode schedules'\n # gather/epilogue, so each factorization is its own kernel; both must key\n # the cache (key-major's pack_q_len does not determine group_size).\n key = (\n \"proxy\",\n str(q.dtype),\n causal,\n paged,\n kv_fp8,\n use_stream,\n use_packed,\n use_keymajor,\n group_size,\n pack_q_len,\n qoff_default if (use_stream or use_keymajor) else None,\n )\n # The packed fp8 schedules take e4m3 operands as 16-bit torch views (half\n # the last dim): the kernel moves raw bytes and upconverts in registers,\n # and a typed view keeps the TMA/cp.async source alignment provable where\n # an in-kernel recast of a symbolic layout does not. fp8 q rides an f16\n # carrier so its register convert hits the native e4m3 -> f16 path.\n kv16 = kv_fp8 and use_packed\n carrier = torch.float16 if q_fp8 else q.dtype\n q_call = q.contiguous().view(carrier) if q_fp8 else q\n k_call = k.contiguous().view(carrier) if kv16 else k\n compiled = _compile_cache.get(key)\n if compiled is None:\n cdt = _cutlass_dtype(q_call.dtype)\n kdt = _cutlass_dtype(k_call.dtype)\n i32 = _cutlass_dtype(torch.int32)\n f32 = _cutlass_dtype(torch.float32)\n # s_bk is mCuK's own symbol: on the paged path it holds per-request\n # lengths (batch entries), not a prefix sum (batch + 1), so it must not\n # share mCuQ's dim or the compiled signature rejects the call.\n s_tq, s_hq, s_tk, s_hkv, s_b1, s_bk, s_b0, s_pb, s_pm, s_mt = (\n cute.sym_int() for _ in range(10)\n )\n qd = head_dim // 2 if q_fp8 else head_dim\n kd = head_dim // 2 if kv16 else head_dim\n k_shape = (s_tk, s_hkv, _BLK_KV, kd) if paged else (s_tk, s_hkv, kd)\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n kernel_obj: Union[\n \"MsaProxyScoreDecodeKeyMajorSm12x\",\n \"MsaProxyScoreDecodeStreamSm12x\",\n \"MsaProxyScoreSm12x\",\n ]\n if use_stream:\n kernel_obj = MsaProxyScoreDecodeStreamSm12x(\n head_dim=head_dim,\n group_size=group_size,\n is_causal=causal,\n paged=paged,\n kv_fp8=kv_fp8,\n qoff_default=qoff_default,\n )\n elif use_keymajor:\n kernel_obj = MsaProxyScoreDecodeKeyMajorSm12x(\n head_dim=head_dim,\n group_size=group_size,\n pack_q_len=pack_q_len,\n is_causal=causal,\n paged=paged,\n kv_fp8=kv_fp8,\n q_fp8=q_fp8,\n qoff_default=qoff_default,\n )\n elif use_packed:\n # fp8 K gets the key-split warp layout so the e4m3 upconvert\n # is not replicated across warps.\n packed_cls = (\n MsaProxyScoreDecodePackedFp8Sm12x\n if kv_fp8\n else MsaProxyScoreDecodePackedSm12x\n )\n kernel_obj = packed_cls(\n head_dim=head_dim,\n m_block_size=group_size * pack_q_len,\n n_block_size=_BLK_KV,\n num_threads=128,\n is_causal=causal,\n paged=paged,\n kv_fp8=kv_fp8,\n qhead_per_kv=group_size,\n pack_q_len=pack_q_len,\n )\n else:\n kernel_obj = MsaProxyScoreSm12x(\n head_dim=head_dim,\n m_block_size=64,\n n_block_size=_BLK_KV,\n num_threads=128,\n is_causal=causal,\n paged=paged,\n kv_fp8=kv_fp8,\n )\n compiled = cute.compile(\n kernel_obj,\n _fake(cdt, (s_tq, s_hq, qd)),\n _fake(kdt, k_shape),\n _fake(i32, (s_pb, s_pm), align=4),\n _fake(f32, (s_hq, s_mt, s_tq), align=4),\n _fake(i32, (s_b1,), align=4), # mCuQ\n _fake(i32, (s_bk,), align=4), # mCuK (lengths when paged)\n _fake(i32, (s_b0,), align=4),\n cutlass.Int32(1),\n cutlass.Int32(1),\n cutlass.Int32(1),\n cutlass.Int32(1),\n cutlass.Int32(1),\n stream_fake,\n options=\"--enable-tvm-ffi\",\n )\n _compile_cache[key] = compiled\n\n # Base grid CTAs (feeds split-K, see _proxy_split_k): the packed path is one\n # CTA per (batch, kv_head); the general path one per (q-tile, batch, head) with\n # 64-row q-tiles. num_splits is a runtime arg, not part of the cache key.\n if use_packed:\n base_ctas = batch_size * num_kv_heads\n else:\n base_ctas = ((max_seqlen_q + 63) // 64) * batch_size * num_qo_heads\n\n def _call(tensors, ns):\n q_, k_, pt_, ph_, cq_, ck_, qoff_ = tensors\n compiled(\n q_,\n k_,\n pt_,\n ph_,\n cq_,\n ck_,\n qoff_,\n int(max_seqlen_q),\n int(batch_size),\n int(num_qo_heads),\n int(max_k_tiles),\n ns,\n )\n return ph_\n\n if use_stream:\n # One CTA per (KV block, token, kv_head): the grid is already maximally\n # split, so there is no split factor to tune.\n _call([q_call, k_call, pt_dev, per_head, cu_q_dev, k_len_or_cu, qoff_dev], 1)\n else:\n _run_proxy_autotuned(\n \"msa_proxy_score\",\n _call,\n [q_call, k_call, pt_dev, per_head, cu_q_dev, k_len_or_cu, qoff_dev],\n max_seqlen_q=max_seqlen_q,\n max_k_tiles=max_k_tiles,\n base_ctas=base_ctas,\n device=dev,\n heuristic=_proxy_split_k_bf16,\n causal=causal,\n paged=paged,\n reduce_heads=reduce_heads,\n )\n\n if not reduce_heads:\n return per_head\n if output is None:\n output = torch.empty(final_shape, dtype=torch.float32, device=dev)\n torch.amax(per_head, dim=0, keepdim=True, out=output)\n return output\n\n\ndef _quantize_qk_to_nvfp4(\n x: torch.Tensor,\n global_scale: Optional[float] = None,\n) -> Tuple[torch.Tensor, torch.Tensor, float]:\n \"\"\"Test/bench/trace glue (deployment quantizes upstream): quantize a\n ``(total, num_heads, 128)`` bf16/fp16 proxy Q or K to packed NVFP4 in the\n 128x4 tiled scale layout; returns ``(x_fp4, block scales, 1/global_scale)``.\"\"\"\n from flashinfer import nvfp4_quantize\n\n if x.ndim != 3 or x.shape[2] != 128:\n raise ValueError(f\"x must be (total, num_heads, 128), got {tuple(x.shape)}\")\n total, num_heads, head_dim = x.shape\n x2d = x.reshape(-1, head_dim)\n if global_scale is None:\n global_scale = (448.0 * 6.0) / x2d.float().abs().max().clamp_min(1e-12)\n gsf = torch.as_tensor([float(global_scale)], dtype=torch.float32, device=x.device)\n # Default sfLayout is the cuBLAS 128x4 tiled layout; SF row = token*num_heads\n # + head (the natural (total, num_heads, d).reshape(-1, d) row order).\n xq, sf = nvfp4_quantize(x2d, gsf, sf_vec_size=_SF_VEC_SIZE)\n x_fp4 = xq.view(torch.uint8).reshape(total, num_heads, head_dim // 2)\n x_scale = sf.view(torch.uint8).reshape(-1) # flat, 128x4 tiled\n return x_fp4, x_scale, 1.0 / float(global_scale)\n\n\n@flashinfer_api(trace=msa_proxy_score_fp4_trace)\ndef msa_proxy_score_fp4(\n q_fp4: torch.Tensor,\n k_fp4: torch.Tensor,\n q_scale: torch.Tensor,\n k_scale: torch.Tensor,\n q_global_scale: float,\n k_global_scale: float,\n cu_seqlens_q: torch.Tensor,\n cu_seqlens_k: Optional[torch.Tensor] = None,\n *,\n page_table: Optional[torch.Tensor] = None,\n seqused_k: Optional[torch.Tensor] = None,\n causal: bool = True,\n max_seqlen_q: Optional[int] = None,\n max_k_tiles: Optional[int] = None,\n output: Optional[torch.Tensor] = None,\n reduce_heads: bool = False,\n q_offset=None,\n) -> torch.Tensor:\n \"\"\"NVFP4 MSA dense proxy pass for SM120/SM121 (the FP4 counterpart of\n :func:`msa_proxy_score`).\n\n Same contract and output as :func:`msa_proxy_score` (per-KV-block max of\n the unscaled, causally-masked ``Q K^T`` logits), but Q/K arrive pre-quantized\n as packed NVFP4 (``e2m1`` + per-16 ``e4m3`` block scales + per-tensor global\n scales), so the index K is read from HBM at ~4 bits/elem. The full-KV index\n read is the dominant decode-step cost, so this is the bandwidth-saving\n path; :func:`msa_proxy_score` stays as the bf16 precision reference.\n\n Numerics equal a torch dequant of the same packed inputs (not the bf16\n reference, which differs by fp4 rounding). The two global scales are folded\n into the logits as ``q_global_scale * k_global_scale`` before the block-max.\n Short q (decode, including multi-token verify) uses a head-fused packed\n schedule on the fp4 tensor cores (``MmaMXF4NVF4Op``) that scores all\n ``group_size`` heads of a kv_head from one shared index-K read; longer q\n uses the general tensor-core schedule. Both flat and paged K are supported;\n see the dispatch below for the exact regime bounds.\n\n Parameters\n ----------\n q_fp4 : torch.Tensor\n ``(total_q, num_qo_heads, 64)`` uint8, packed e2m1 (2 nibbles/byte).\n k_fp4 : torch.Tensor\n Flat ``(total_k, num_kv_heads, 64)`` with ``cu_seqlens_k``, or paged\n ``(num_pages, num_kv_heads, 128, 64)`` with ``page_table`` +\n ``seqused_k``. ``num_qo_heads`` must be a multiple of ``num_kv_heads``.\n q_scale, k_scale : torch.Tensor\n Flat uint8 e4m3 block scales in the cuBLAS 128x4 tiled layout, indexed by\n logical row ``token*num_heads + head`` (paged K: ``(page*num_kv_heads +\n kv_head)*128 + token_in_page``). Produced by :func:`nvfp4_quantize`\n (128x4 layout, ``sf_vec_size=16``); shared with the attention + decode kernels.\n q_global_scale, k_global_scale : float\n Per-tensor inverse global scales (``1 / global_scale``).\n cu_seqlens_q, cu_seqlens_k : torch.Tensor\n As in :func:`msa_proxy_score`.\n page_table : torch.Tensor, optional\n As in :func:`msa_proxy_score`.\n seqused_k : torch.Tensor, optional\n As in :func:`msa_proxy_score`.\n causal : bool\n As in :func:`msa_proxy_score`.\n max_seqlen_q : int, optional\n As in :func:`msa_proxy_score`.\n max_k_tiles : int, optional\n As in :func:`msa_proxy_score`.\n output : torch.Tensor, optional\n As in :func:`msa_proxy_score`.\n reduce_heads : bool\n As in :func:`msa_proxy_score`.\n q_offset : int or torch.Tensor, optional\n As in :func:`msa_proxy_score`.\n\n Returns\n -------\n torch.Tensor\n Float32 ``max_score`` for :func:`msa_topk_select`:\n ``(num_qo_heads, max_k_tiles, total_q)``, or\n ``(1, max_k_tiles, total_q)`` when ``reduce_heads=True``.\n \"\"\"\n import cutlass\n import cutlass.cute as cute\n\n from .cute_dsl.proxy_score_fp4_sm12x import (\n MsaProxyScoreFp4MmaDecodePackedSm12x,\n MsaProxyScoreFp4MmaSm12x,\n )\n from ._common import (\n _compile_cache,\n _cutlass_dtype,\n _fake,\n _q_offset_tensor,\n )\n\n if not is_sm12x_supported(q_fp4.device):\n raise RuntimeError(\n \"msa_proxy_score_fp4 requires SM120 or SM121 and CUDA >= 12.8\"\n )\n if q_fp4.dtype != torch.uint8 or k_fp4.dtype != torch.uint8:\n raise ValueError(\"q_fp4/k_fp4 must be packed uint8 (e2m1x2)\")\n if q_scale.dtype != torch.uint8 or k_scale.dtype != torch.uint8:\n raise ValueError(\"q_scale/k_scale must be uint8 (e4m3 bytes)\")\n hd2 = _BLK_KV // 2 # 64 packed bytes / row\n q_scale = q_scale.reshape(-1)\n k_scale = k_scale.reshape(-1)\n total_q, num_qo_heads, q_last = q_fp4.shape\n if q_last != hd2:\n raise ValueError(f\"q_fp4 last dim must be {hd2} (head_dim/2), got {q_last}\")\n num_kv_heads = k_fp4.shape[1]\n if num_qo_heads % num_kv_heads != 0:\n raise ValueError(\"num_qo_heads must be a multiple of num_kv_heads\")\n dev = q_fp4.device\n\n paged = page_table is not None\n if paged:\n if seqused_k is None:\n raise ValueError(\"paged proxy requires seqused_k\")\n if k_fp4.ndim != 4 or k_fp4.shape[2] != _BLK_KV or k_fp4.shape[3] != hd2:\n raise ValueError(\n f\"paged k_fp4 must be (num_pages, num_kv_heads, {_BLK_KV}, {hd2})\"\n )\n batch_size = seqused_k.numel()\n # Paged addressing comes entirely from page_table, so the kernel needs\n # only each request's length. Pass seqused_k through instead of building\n # a prefix sum (zeros + cumsum + slice-copy on every call) for the\n # kernel to difference back apart; `paged` tells it which form this is.\n k_len_or_cu = seqused_k if seqused_k.device == dev else seqused_k.to(dev)\n k_len_or_cu = k_len_or_cu.contiguous()\n pt_dev = page_table.contiguous()\n else:\n if cu_seqlens_k is None:\n raise ValueError(\"flat proxy requires cu_seqlens_k\")\n if k_fp4.ndim != 3:\n raise ValueError(\"flat k_fp4 must be (total_k, num_kv_heads, 64)\")\n k_len_or_cu = cu_seqlens_k.to(dev)\n pt_dev = torch.zeros((1, 1), dtype=torch.int32, device=dev)\n batch_size = k_len_or_cu.numel() - 1\n\n cu_q_dev = cu_seqlens_q.to(dev)\n qoff_dev = _q_offset_tensor(\n q_offset, cu_q_dev, k_len_or_cu, dev, k_is_lengths=paged\n )\n max_seqlen_q, max_k_tiles = _resolve_proxy_dims(\n cu_seqlens_q, k_len_or_cu, max_seqlen_q, max_k_tiles, output, k_is_lengths=paged\n )\n\n per_head_shape = (num_qo_heads, max_k_tiles, total_q)\n final_shape = (1, max_k_tiles, total_q) if reduce_heads else per_head_shape\n if output is not None:\n if output.shape != final_shape:\n raise ValueError(f\"output must be {final_shape}\")\n if output.dtype != torch.float32:\n raise ValueError(\"output must be float32\")\n if reduce_heads or output is None:\n per_head = torch.empty(per_head_shape, dtype=torch.float32, device=dev)\n else:\n per_head = output\n\n # Head-fused decode path, as in msa_proxy_score, but on the 128-row fp4-MMA\n # tile and with no fp8-K exclusion.\n _PACK_ROWS = MsaProxyScoreFp4MmaSm12x._M\n group_size = num_qo_heads // num_kv_heads\n use_packed = (\n group_size >= 2\n and _PACK_ROWS % group_size == 0\n and max_seqlen_q <= _PACK_ROWS // group_size\n )\n pack_q_len = _PACK_ROWS // group_size if use_packed else 0\n\n # Base grid CTAs (feeds split-K) and cache key, as in msa_proxy_score.\n if use_packed:\n base_ctas = batch_size * num_kv_heads\n else:\n base_ctas = ((max_seqlen_q + 127) // 128) * batch_size * num_qo_heads\n\n key = (\"proxy_fp4\", causal, paged, use_packed, pack_q_len)\n compiled = _compile_cache.get(key)\n if compiled is None:\n u8 = _cutlass_dtype(torch.uint8)\n i32 = _cutlass_dtype(torch.int32)\n f32 = _cutlass_dtype(torch.float32)\n (\n s_tq,\n s_hq,\n s_tk,\n s_hkv,\n s_b1,\n # mCuK's own symbol: per-request lengths (batch) when paged, a\n # prefix sum (batch + 1) when flat, so it cannot share mCuQ's dim.\n s_bk,\n s_b0,\n s_pb,\n s_pm,\n s_mt,\n s_qsf,\n s_ksf,\n ) = (cute.sym_int() for _ in range(12))\n if paged:\n k_shape: tuple = (s_tk, s_hkv, _BLK_KV, hd2)\n else:\n k_shape = (s_tk, s_hkv, hd2)\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n kernel_obj: \"MsaProxyScoreFp4MmaSm12x\"\n if use_packed:\n kernel_obj = MsaProxyScoreFp4MmaDecodePackedSm12x(\n head_dim=_BLK_KV,\n is_causal=causal,\n paged=paged,\n qhead_per_kv=group_size,\n pack_q_len=pack_q_len,\n )\n else:\n kernel_obj = MsaProxyScoreFp4MmaSm12x(\n head_dim=_BLK_KV,\n is_causal=causal,\n paged=paged,\n )\n compiled = cute.compile(\n kernel_obj,\n _fake(u8, (s_tq, s_hq, hd2), align=4),\n _fake(u8, k_shape, align=4),\n _fake(u8, (s_qsf,), align=4),\n _fake(u8, (s_ksf,), align=4),\n _fake(i32, (s_pb, s_pm), align=4),\n _fake(f32, (s_hq, s_mt, s_tq), align=4),\n _fake(i32, (s_b1,), align=4), # mCuQ\n _fake(i32, (s_bk,), align=4), # mCuK (lengths when paged)\n _fake(i32, (s_b0,), align=4),\n cutlass.Float32(1.0),\n cutlass.Float32(1.0),\n cutlass.Int32(1),\n cutlass.Int32(1),\n cutlass.Int32(1),\n cutlass.Int32(1),\n cutlass.Int32(1), # num_splits\n stream_fake,\n options=\"--enable-tvm-ffi\",\n )\n _compile_cache[key] = compiled\n\n def _call(tensors, ns):\n qf, kf, qs, ks, pt_, ph_, cq_, ck_, qoff_ = tensors\n compiled(\n qf,\n kf,\n qs,\n ks,\n pt_,\n ph_,\n cq_,\n ck_,\n qoff_,\n float(q_global_scale),\n float(k_global_scale),\n int(max_seqlen_q),\n int(batch_size),\n int(num_qo_heads),\n int(max_k_tiles),\n ns,\n )\n return ph_\n\n _run_proxy_autotuned(\n \"msa_proxy_score_fp4\",\n _call,\n [\n q_fp4,\n k_fp4,\n q_scale,\n k_scale,\n pt_dev,\n per_head,\n cu_q_dev,\n k_len_or_cu,\n qoff_dev,\n ],\n max_seqlen_q=max_seqlen_q,\n max_k_tiles=max_k_tiles,\n base_ctas=base_ctas,\n device=dev,\n heuristic=_proxy_split_k_fp4,\n causal=causal,\n paged=paged,\n reduce_heads=reduce_heads,\n )\n\n if not reduce_heads:\n return per_head\n if output is None:\n output = torch.empty(final_shape, dtype=torch.float32, device=dev)\n torch.amax(per_head, dim=0, keepdim=True, out=output)\n return output\n"},"after_code":{"kind":"string","value":"\"\"\"\nCopyright (c) 2026 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\"\"\"\n\nimport functools\nfrom typing import Optional, Tuple, Union\n\nimport torch\n\nfrom ..api_logging import flashinfer_api\nfrom ..autotuner import AutoTuner, TunableRunner, TuningConfig\nfrom ..trace.templates.msa import (\n msa_proxy_score_fp4_trace,\n msa_proxy_score_trace,\n)\nfrom ..utils import get_device_sm_count, is_sm12x_supported\nfrom ._common import _BLK_KV\n\n# NVFP4 scale granularity: one e4m3 block scale per 16 e2m1 elements.\n_SF_VEC_SIZE = 16\n\n\ndef _resolve_proxy_dims(\n cu_seqlens_q, k_len_or_cu, max_seqlen_q, max_k_tiles, output, k_is_lengths=False\n):\n \"\"\"Resolve grid dims ``(max_seqlen_q, max_k_tiles)`` as Python ints; deriving\n them reads ``cu_seqlens`` on host, so under CUDA-graph capture we raise.\n\n ``k_len_or_cu`` is per-request lengths when ``k_is_lengths`` (the paged\n path), else a prefix sum.\"\"\"\n if max_k_tiles is None and output is not None:\n max_k_tiles = int(output.shape[1])\n if max_seqlen_q is not None and max_k_tiles is not None:\n return max_seqlen_q, max_k_tiles\n if torch.cuda.is_current_stream_capturing():\n raise ValueError(\n \"msa_proxy_score[_fp4] needs max_seqlen_q and max_k_tiles during CUDA \"\n \"graph capture (deriving them from cu_seqlens would sync the stream). \"\n \"Pass both (computed once at plan time) or pre-allocate `output`.\"\n )\n if max_seqlen_q is None:\n cu_q_cpu = cu_seqlens_q.cpu()\n max_seqlen_q = int((cu_q_cpu[1:] - cu_q_cpu[:-1]).max().item())\n if max_k_tiles is None:\n k_cpu = k_len_or_cu.cpu()\n seqlens_k = k_cpu if k_is_lengths else (k_cpu[1:] - k_cpu[:-1])\n max_k_tiles = int((seqlens_k.max().item() + _BLK_KV - 1) // _BLK_KV)\n return max_seqlen_q, max_k_tiles\n\n\ndef _proxy_split_k(\n base_ctas: int,\n max_k_tiles: int,\n device,\n *,\n wave_target: float,\n gate_factor: float,\n ceil_to_target: bool,\n) -> int:\n \"\"\"KV-block split factor that fills the SMs when the base proxy grid is small\n (long context, low batch). Splits need no reduction: the per-(head, kv_block,\n query) output means each split writes disjoint columns. Returns 1 once the\n base grid already covers ``gate_factor`` SM-waves.\"\"\"\n if base_ctas <= 0 or max_k_tiles <= 1:\n return 1\n num_sms = get_device_sm_count(device)\n if base_ctas >= gate_factor * num_sms:\n return 1\n target = wave_target * num_sms\n splits = (\n -(-int(target) // base_ctas) if ceil_to_target else round(target / base_ctas)\n )\n return max(1, min(splits, max_k_tiles))\n\n\n# bf16 split-K heuristic, tuned empirically: target ~1.5 waves and round (the\n# Q reload per split makes over-splitting regress).\n_proxy_split_k_bf16 = functools.partial(\n _proxy_split_k, wave_target=1.5, gate_factor=1.0, ceil_to_target=False\n)\n\n\n@functools.lru_cache(maxsize=None)\ndef _split_k_makespan_argmin(\n base_ctas: int, max_k_tiles: int, resident_ctas: int\n) -> int:\n \"\"\"Split factor minimizing a makespan model: full resident-CTA waves times\n per-split work, with ~one KV block of fixed per-CTA overhead (launch + Q\n load). Ties break to the smaller split (fewer Q reloads). A model rather\n than a wave target because the optimum shifts between filling residency\n exactly (moderate batch), max split (batch 1), and no split (large batch,\n short kv) -- no single target covers all three regimes.\"\"\"\n best_ns, best_cost = 1, None\n for ns in range(1, min(max_k_tiles, 4096) + 1):\n waves = -(-(base_ctas * ns) // resident_ctas)\n cost = waves * (-(-max_k_tiles // ns) + 1)\n if best_cost is None or cost < best_cost:\n best_ns, best_cost = ns, cost\n return best_ns\n\n\ndef _proxy_split_k_fp4(base_ctas: int, max_k_tiles: int, device) -> int:\n \"\"\"fp4 split-K: 4-bit K reads make splits cheap, so pick by the makespan\n model at the kernel's 2-CTA/SM residency (see _MIN_BLOCKS_PER_MP).\"\"\"\n if base_ctas <= 0 or max_k_tiles <= 1:\n return 1\n return _split_k_makespan_argmin(\n base_ctas, max_k_tiles, 2 * get_device_sm_count(device)\n )\n\n\nclass _ProxySplitKRunner(TunableRunner):\n \"\"\"Autotunes the proxy kv-block split factor: ``tactic`` *is* the split\n factor (a runtime arg, so one compiled kernel covers every candidate).\"\"\"\n\n def __init__(\n self,\n call_fn,\n *,\n max_seqlen_q,\n max_k_tiles,\n base_ctas,\n device,\n heuristic,\n causal,\n paged,\n reduce_heads,\n ):\n # call_fn(inputs, num_splits) -> output; lets one runner serve both the\n # bf16 and (longer-signature) fp4 proxy invocations.\n self._call = call_fn\n self._msq = int(max_seqlen_q)\n self._mkt = int(max_k_tiles)\n self._base = int(base_ctas)\n self._device = device\n self._heuristic = heuristic # callable(base_ctas, max_k_tiles, device) -> int\n self._causal = bool(causal)\n self._paged = bool(paged)\n self._reduce = bool(reduce_heads)\n\n def __hash__(self):\n return hash(type(self))\n\n def get_valid_tactics(self, inputs, profile):\n # Powers of two up to ~4 SM-waves, capped by max_k_tiles; always include\n # the closed-form heuristic so a tuned op is never worse than eager.\n num_sms = get_device_sm_count(self._device)\n cap = min(self._mkt, max(1, -(-4 * num_sms // max(self._base, 1))))\n cands = {s for s in (1, 2, 4, 8, 16, 32) if s <= cap}\n cands.add(self._heuristic(self._base, self._mkt, self._device))\n return sorted(cands)\n\n def get_cache_key_extras(self, inputs):\n # max_seqlen_q / max_k_tiles are varlen-derived (not in any tensor shape),\n # so they must key the cache; causal/paged/reduce flip the work pattern.\n return (self._causal, self._paged, self._reduce, self._msq, self._mkt)\n\n def forward(self, inputs, tactic: int = -1, do_preparation: bool = False, **kwargs):\n # tactic == -1 falls back to the closed-form heuristic, so eager\n # (un-tuned) behavior is unchanged.\n ns = (\n tactic\n if tactic >= 0\n else self._heuristic(self._base, self._mkt, self._device)\n )\n return self._call(inputs, int(ns))\n\n\n# (op, shape) keys that already went through the autotuner in this process. Until\n# a shape is tuned the proxy uses its closed-form heuristic and skips choose_one,\n# whose per-call lock/bookkeeping (~tens of us) would dominate the tiny low-batch\n# decode.\n_PROXY_TUNED: set = set()\n\n\ndef _proxy_tuned_key(\n op_name, *, causal, paged, reduce_heads, max_seqlen_q, max_k_tiles, base_ctas\n):\n # base_ctas folds in batch/heads/max_seqlen_q, so this matches the autotuner's\n # own cache granularity (shape + get_cache_key_extras) closely enough to gate on.\n return (\n op_name,\n bool(causal),\n bool(paged),\n bool(reduce_heads),\n int(max_seqlen_q),\n int(max_k_tiles),\n int(base_ctas),\n )\n\n\ndef _run_proxy_autotuned(\n op_name,\n call_fn,\n tensors,\n *,\n max_seqlen_q,\n max_k_tiles,\n base_ctas,\n device,\n heuristic,\n causal,\n paged,\n reduce_heads,\n):\n \"\"\"Run the proxy with an autotuned split factor; un-tuned shapes use the\n closed-form heuristic directly and skip the autotuner entirely.\"\"\"\n tuner = AutoTuner.get()\n tuning = tuner.is_tuning_mode\n tuned_key = _proxy_tuned_key(\n op_name,\n causal=causal,\n paged=paged,\n reduce_heads=reduce_heads,\n max_seqlen_q=max_seqlen_q,\n max_k_tiles=max_k_tiles,\n base_ctas=base_ctas,\n )\n if tuning:\n _PROXY_TUNED.add(tuned_key)\n elif tuned_key not in _PROXY_TUNED:\n call_fn(tensors, heuristic(base_ctas, max_k_tiles, device))\n return\n\n runner = _ProxySplitKRunner(\n call_fn,\n max_seqlen_q=max_seqlen_q,\n max_k_tiles=max_k_tiles,\n base_ctas=base_ctas,\n device=device,\n heuristic=heuristic,\n causal=causal,\n paged=paged,\n reduce_heads=reduce_heads,\n )\n # No DynamicTensorSpec: the autotuner would synthesize a shape-correct but\n # value-invalid varlen cu_seqlens; with static inputs it profiles the\n # candidates on the caller's real (valid) tensors.\n runner_sel, tactic = tuner.choose_one(op_name, [runner], TuningConfig(), tensors)\n runner_sel(inputs=tensors, tactic=tactic)\n\n\n@functools.cache\ndef _proxy_dummies(device_index: int):\n # Signature fillers for paths that never read them; cached so repeat decode\n # calls do not launch fill kernels.\n dev = torch.device(\"cuda\", device_index)\n return (\n torch.zeros((1, 1), dtype=torch.int32, device=dev),\n torch.zeros(1, dtype=torch.int32, device=dev),\n )\n\n\n@flashinfer_api(trace=msa_proxy_score_trace)\ndef msa_proxy_score(\n q: torch.Tensor,\n k: torch.Tensor,\n cu_seqlens_q: torch.Tensor,\n cu_seqlens_k: Optional[torch.Tensor] = None,\n *,\n page_table: Optional[torch.Tensor] = None,\n seqused_k: Optional[torch.Tensor] = None,\n causal: bool = True,\n max_seqlen_q: Optional[int] = None,\n max_k_tiles: Optional[int] = None,\n output: Optional[torch.Tensor] = None,\n reduce_heads: bool = False,\n q_offset=None,\n) -> torch.Tensor:\n \"\"\"MSA dense proxy pass for SM120/SM121: per-KV-block max attention\n logits.\n\n Computes ``max_score[h, t, q]``, the maximum of the unscaled,\n causally-masked ``Q K^T`` logits over the 128 tokens of KV block ``t``,\n for every query token and query head. The output feeds directly into\n :func:`msa_topk_select`. KV blocks beyond a sequence's valid range, or\n entirely above the causal limit, yield ``-inf``.\n\n There is no softmax and no V: this is MSA pipeline stage 1.\n\n Single-token decode uses a dim-parallel scalar schedule that streams\n index-K straight to registers. Short multi-token decode (MTP) uses a\n head-fused packed schedule that scores all ``group_size`` heads of a\n kv_head from one shared index-K read. Prefill uses the general schedule;\n see the dispatch below for the exact regime bounds.\n\n Parameters\n ----------\n q : torch.Tensor\n ``(total_q, num_qo_heads, 128)``, bf16 or fp16 (the cheap proxy Q).\n May be fp8 E4M3 when ``k`` is fp8: decode shapes consume it natively,\n other shapes upconvert it once internally.\n k : torch.Tensor\n Flat ``(total_k, num_kv_heads, 128)`` with ``cu_seqlens_k``, or\n paged ``(num_pages, num_kv_heads, 128, 128)`` with ``page_table`` +\n ``seqused_k``. May be fp8 E4M3 (upconverted in-kernel).\n ``num_qo_heads`` must be a multiple of ``num_kv_heads``.\n cu_seqlens_q : torch.Tensor\n ``(batch_size + 1,)`` int32 cumulative query lengths.\n cu_seqlens_k : torch.Tensor, optional\n ``(batch_size + 1,)`` int32 cumulative KV lengths. Required for flat\n KV layout and unused for paged KV layout.\n page_table : torch.Tensor, optional\n Page-table mapping for paged KV layout. Required together with\n ``seqused_k`` when ``k`` is paged.\n seqused_k : torch.Tensor, optional\n Per-sequence valid KV-token counts. Required together with\n ``page_table`` for paged KV layout.\n causal : bool\n Right-aligned causal masking, applied *before* the block max.\n max_seqlen_q : int, optional\n Maximum query length. Required by some CUDA Graph / compilation paths.\n max_k_tiles : int, optional\n Number of KV-block columns in the output; defaults to the maximum\n ``ceil(seqlen_k / 128)`` over the batch.\n output : torch.Tensor, optional\n Pre-allocated float32 output. Shape is\n ``(num_qo_heads, max_k_tiles, total_q)`` normally, or\n ``(1, max_k_tiles, total_q)`` when ``reduce_heads=True``.\n reduce_heads : bool\n If ``True``, max-reduce the per-head ``max_score`` over the query-head\n axis and return a single ``(1, max_k_tiles, total_q)`` score. Use this\n when the query heads are an indexer's proxy heads that collapse to one\n shared block selection per query (MiniMax-M3 indexer semantics).\n Defaults to ``False``: per-head ``max_score``, where each head selects\n its own blocks.\n The reduction is currently a post-kernel ``amax`` over the per-head\n buffer (the kernel is one CTA per head, so a cross-head epilogue would\n need cross-CTA float atomics); folding it into the kernel is a possible\n future optimization (saves materializing the per-head buffer).\n q_offset : int or torch.Tensor, optional\n Optional query-position offset used by the causal alignment logic.\n\n Returns\n -------\n torch.Tensor\n Float32 ``max_score`` ready for :func:`msa_topk_select`:\n ``(num_qo_heads, max_k_tiles, total_q)``, or\n ``(1, max_k_tiles, total_q)`` when ``reduce_heads=True``.\n \"\"\"\n import cutlass\n import cutlass.cute as cute\n\n from .cute_dsl.proxy_score_sm12x import (\n MsaProxyScoreDecodeKeyMajorSm12x,\n MsaProxyScoreDecodePackedFp8Sm12x,\n MsaProxyScoreDecodePackedSm12x,\n MsaProxyScoreDecodeStreamSm12x,\n MsaProxyScoreSm12x,\n )\n from ._common import (\n _compile_cache,\n _cutlass_dtype,\n _fake,\n _q_offset_tensor,\n )\n\n if not is_sm12x_supported(q.device):\n raise RuntimeError(\"msa_proxy_score requires SM120 or SM121 and CUDA >= 12.8\")\n q_fp8 = q.dtype == torch.float8_e4m3fn\n if q.dtype not in (torch.bfloat16, torch.float16) and not q_fp8:\n raise ValueError(f\"q must be bf16, fp16, or fp8 e4m3, got {q.dtype}\")\n total_q, num_qo_heads, head_dim = q.shape\n if head_dim != 128:\n raise ValueError(f\"head_dim must be 128, got {head_dim}\")\n num_kv_heads = k.shape[1]\n if num_qo_heads % num_kv_heads != 0:\n raise ValueError(\"num_qo_heads must be a multiple of num_kv_heads\")\n kv_fp8 = k.dtype == torch.float8_e4m3fn\n if q_fp8 and not kv_fp8:\n raise ValueError(\"fp8 q requires fp8 k\")\n if not kv_fp8 and k.dtype != q.dtype:\n raise ValueError(\"k dtype must match q (or be float8_e4m3fn)\")\n dev = q.device\n\n paged = page_table is not None\n if paged:\n if seqused_k is None:\n raise ValueError(\"paged proxy requires seqused_k\")\n if k.ndim != 4 or k.shape[2] != _BLK_KV or k.shape[3] != head_dim:\n raise ValueError(\n f\"paged k must be (num_pages, num_kv_heads, {_BLK_KV}, {head_dim})\"\n )\n batch_size = seqused_k.numel()\n # Paged addressing comes entirely from page_table, so the kernel needs\n # only each request's length. Pass seqused_k through instead of building\n # a prefix sum (zeros + cumsum + slice-copy on every call) for the\n # kernel to difference back apart; `paged` tells it which form this is.\n k_len_or_cu = seqused_k if seqused_k.device == dev else seqused_k.to(dev)\n k_len_or_cu = k_len_or_cu.contiguous()\n pt_dev = page_table.contiguous()\n else:\n if cu_seqlens_k is None:\n raise ValueError(\"flat proxy requires cu_seqlens_k\")\n if k.ndim != 3:\n raise ValueError(\"flat k must be (total_k, num_kv_heads, head_dim)\")\n k_len_or_cu = cu_seqlens_k.to(dev)\n pt_dev = _proxy_dummies(dev.index)[0]\n batch_size = k_len_or_cu.numel() - 1\n\n cu_q_dev = cu_seqlens_q.to(dev)\n max_seqlen_q, max_k_tiles = _resolve_proxy_dims(\n cu_seqlens_q, k_len_or_cu, max_seqlen_q, max_k_tiles, output, k_is_lengths=paged\n )\n\n per_head_shape = (num_qo_heads, max_k_tiles, total_q)\n final_shape = (1, max_k_tiles, total_q) if reduce_heads else per_head_shape\n if output is not None:\n if output.shape != final_shape:\n raise ValueError(f\"output must be {final_shape}\")\n if output.dtype != torch.float32:\n raise ValueError(\"output must be float32\")\n\n # The kernel always writes the per-head buffer; reduce_heads then collapses\n # it. When not reducing and an output was given, that buffer *is* the output.\n if reduce_heads or output is None:\n per_head = torch.empty(per_head_shape, dtype=torch.float32, device=dev)\n else:\n per_head = output\n\n group_size = num_qo_heads // num_kv_heads\n _PACK_ROWS = 64 # bf16 MMA q-tile rows (== m_block_size)\n p = 1\n while p < max_seqlen_q:\n p *= 2\n # Fused tiles of at most 32 rows (group_size * next_pow2(q_len)) take the\n # key-major TMA schedule (see MsaProxyScoreDecodeKeyMajorSm12x); larger\n # fused tiles keep the row-major/key-split schedules. bf16 single-token\n # decode stays on the dim-parallel stream schedule (see\n # MsaProxyScoreDecodeStreamSm12x), which also covers the group sizes\n # key-major cannot take; fp8 single-token decode goes key-major, whose\n # in-register convert beats the stream schedule's per-element CUDA-core\n # convert. total_q == batch_size guarantees exactly one q token per\n # request, which the stream schedule's token == batch indexing relies on.\n keymajor_ok = (\n group_size >= 2 and _PACK_ROWS % group_size == 0 and group_size * p <= 32\n )\n use_stream = (\n max_seqlen_q == 1\n and total_q == batch_size\n and group_size <= 8\n and not (kv_fp8 and keymajor_ok)\n )\n qoff_default = q_offset is None\n\n # Head-fused decode path: pack group_size heads x pack_q_len q-tokens into one\n # 64-row MMA tile so index-K is read once per (batch, kv_head). Outside the regime\n # (prefill, group_size not dividing 64) use the general schedule.\n use_packed = (\n not use_stream\n and group_size >= 2\n and _PACK_ROWS % group_size == 0\n and max_seqlen_q <= _PACK_ROWS // group_size\n )\n use_keymajor = use_packed and keymajor_ok\n if use_keymajor:\n pack_q_len = p\n else:\n pack_q_len = _PACK_ROWS // group_size if use_packed else 0\n\n # fp8 q (the vLLM M3 fp8-cache contract) is consumed natively only by the\n # key-major schedule; other shapes upconvert once (e4m3 -> bf16 is\n # lossless) and take their usual route.\n if q_fp8 and not use_keymajor:\n q = q.to(torch.bfloat16)\n q_fp8 = False\n\n # Right-aligned decode on the stream and packed paths computes the causal\n # limit in-kernel, so no offset tensor (and its build kernels, which\n # dominate at batch 1) is needed.\n if (use_stream or use_packed) and qoff_default:\n qoff_dev = _proxy_dummies(dev.index)[1]\n else:\n qoff_dev = _q_offset_tensor(\n q_offset, cu_q_dev, k_len_or_cu, dev, k_is_lengths=paged\n )\n\n # group_size and pack_q_len are constexpr-baked into the decode schedules'\n # gather/epilogue, so each factorization is its own kernel; both must key\n # the cache (key-major's pack_q_len does not determine group_size).\n key = (\n \"proxy\",\n str(q.dtype),\n causal,\n paged,\n kv_fp8,\n use_stream,\n use_packed,\n use_keymajor,\n group_size,\n pack_q_len,\n qoff_default if (use_stream or use_packed) else None,\n )\n # The packed fp8 schedules take e4m3 operands as 16-bit torch views (half\n # the last dim): the kernel moves raw bytes and upconverts in registers,\n # and a typed view keeps the TMA/cp.async source alignment provable where\n # an in-kernel recast of a symbolic layout does not. fp8 q rides an f16\n # carrier so its register convert hits the native e4m3 -> f16 path.\n kv16 = kv_fp8 and use_packed\n carrier = torch.float16 if q_fp8 else q.dtype\n q_call = q.contiguous().view(carrier) if q_fp8 else q\n k_call = k.contiguous().view(carrier) if kv16 else k\n compiled = _compile_cache.get(key)\n if compiled is None:\n cdt = _cutlass_dtype(q_call.dtype)\n kdt = _cutlass_dtype(k_call.dtype)\n i32 = _cutlass_dtype(torch.int32)\n f32 = _cutlass_dtype(torch.float32)\n # s_bk is mCuK's own symbol: on the paged path it holds per-request\n # lengths (batch entries), not a prefix sum (batch + 1), so it must not\n # share mCuQ's dim or the compiled signature rejects the call.\n s_tq, s_hq, s_tk, s_hkv, s_b1, s_bk, s_b0, s_pb, s_pm, s_mt = (\n cute.sym_int() for _ in range(10)\n )\n qd = head_dim // 2 if q_fp8 else head_dim\n kd = head_dim // 2 if kv16 else head_dim\n k_shape = (s_tk, s_hkv, _BLK_KV, kd) if paged else (s_tk, s_hkv, kd)\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n kernel_obj: Union[\n \"MsaProxyScoreDecodeKeyMajorSm12x\",\n \"MsaProxyScoreDecodeStreamSm12x\",\n \"MsaProxyScoreSm12x\",\n ]\n if use_stream:\n kernel_obj = MsaProxyScoreDecodeStreamSm12x(\n head_dim=head_dim,\n group_size=group_size,\n is_causal=causal,\n paged=paged,\n kv_fp8=kv_fp8,\n qoff_default=qoff_default,\n )\n elif use_keymajor:\n kernel_obj = MsaProxyScoreDecodeKeyMajorSm12x(\n head_dim=head_dim,\n group_size=group_size,\n pack_q_len=pack_q_len,\n is_causal=causal,\n paged=paged,\n kv_fp8=kv_fp8,\n q_fp8=q_fp8,\n qoff_default=qoff_default,\n )\n elif use_packed:\n # fp8 K gets the key-split warp layout so the e4m3 upconvert\n # is not replicated across warps.\n packed_cls = (\n MsaProxyScoreDecodePackedFp8Sm12x\n if kv_fp8\n else MsaProxyScoreDecodePackedSm12x\n )\n kernel_obj = packed_cls(\n head_dim=head_dim,\n m_block_size=group_size * pack_q_len,\n n_block_size=_BLK_KV,\n num_threads=128,\n is_causal=causal,\n paged=paged,\n kv_fp8=kv_fp8,\n qhead_per_kv=group_size,\n pack_q_len=pack_q_len,\n qoff_default=qoff_default,\n )\n else:\n kernel_obj = MsaProxyScoreSm12x(\n head_dim=head_dim,\n m_block_size=64,\n n_block_size=_BLK_KV,\n num_threads=128,\n is_causal=causal,\n paged=paged,\n kv_fp8=kv_fp8,\n )\n compiled = cute.compile(\n kernel_obj,\n _fake(cdt, (s_tq, s_hq, qd)),\n _fake(kdt, k_shape),\n _fake(i32, (s_pb, s_pm), align=4),\n _fake(f32, (s_hq, s_mt, s_tq), align=4),\n _fake(i32, (s_b1,), align=4), # mCuQ\n _fake(i32, (s_bk,), align=4), # mCuK (lengths when paged)\n _fake(i32, (s_b0,), align=4),\n cutlass.Int32(1),\n cutlass.Int32(1),\n cutlass.Int32(1),\n cutlass.Int32(1),\n cutlass.Int32(1),\n stream_fake,\n options=\"--enable-tvm-ffi\",\n )\n _compile_cache[key] = compiled\n\n # Base grid CTAs (feeds split-K, see _proxy_split_k): the packed path is one\n # CTA per (batch, kv_head); the general path one per (q-tile, batch, head) with\n # 64-row q-tiles. num_splits is a runtime arg, not part of the cache key.\n if use_packed:\n base_ctas = batch_size * num_kv_heads\n else:\n base_ctas = ((max_seqlen_q + 63) // 64) * batch_size * num_qo_heads\n\n def _call(tensors, ns):\n q_, k_, pt_, ph_, cq_, ck_, qoff_ = tensors\n compiled(\n q_,\n k_,\n pt_,\n ph_,\n cq_,\n ck_,\n qoff_,\n int(max_seqlen_q),\n int(batch_size),\n int(num_qo_heads),\n int(max_k_tiles),\n ns,\n )\n return ph_\n\n if use_stream:\n # One CTA per (KV block, token, kv_head): the grid is already maximally\n # split, so there is no split factor to tune.\n _call([q_call, k_call, pt_dev, per_head, cu_q_dev, k_len_or_cu, qoff_dev], 1)\n else:\n _run_proxy_autotuned(\n \"msa_proxy_score\",\n _call,\n [q_call, k_call, pt_dev, per_head, cu_q_dev, k_len_or_cu, qoff_dev],\n max_seqlen_q=max_seqlen_q,\n max_k_tiles=max_k_tiles,\n base_ctas=base_ctas,\n device=dev,\n heuristic=_proxy_split_k_bf16,\n causal=causal,\n paged=paged,\n reduce_heads=reduce_heads,\n )\n\n if not reduce_heads:\n return per_head\n if output is None:\n output = torch.empty(final_shape, dtype=torch.float32, device=dev)\n torch.amax(per_head, dim=0, keepdim=True, out=output)\n return output\n\n\ndef _quantize_qk_to_nvfp4(\n x: torch.Tensor,\n global_scale: Optional[float] = None,\n) -> Tuple[torch.Tensor, torch.Tensor, float]:\n \"\"\"Test/bench/trace glue (deployment quantizes upstream): quantize a\n ``(total, num_heads, 128)`` bf16/fp16 proxy Q or K to packed NVFP4 in the\n 128x4 tiled scale layout; returns ``(x_fp4, block scales, 1/global_scale)``.\"\"\"\n from flashinfer import nvfp4_quantize\n\n if x.ndim != 3 or x.shape[2] != 128:\n raise ValueError(f\"x must be (total, num_heads, 128), got {tuple(x.shape)}\")\n total, num_heads, head_dim = x.shape\n x2d = x.reshape(-1, head_dim)\n if global_scale is None:\n global_scale = (448.0 * 6.0) / x2d.float().abs().max().clamp_min(1e-12)\n gsf = torch.as_tensor([float(global_scale)], dtype=torch.float32, device=x.device)\n # Default sfLayout is the cuBLAS 128x4 tiled layout; SF row = token*num_heads\n # + head (the natural (total, num_heads, d).reshape(-1, d) row order).\n xq, sf = nvfp4_quantize(x2d, gsf, sf_vec_size=_SF_VEC_SIZE)\n x_fp4 = xq.view(torch.uint8).reshape(total, num_heads, head_dim // 2)\n x_scale = sf.view(torch.uint8).reshape(-1) # flat, 128x4 tiled\n return x_fp4, x_scale, 1.0 / float(global_scale)\n\n\n@flashinfer_api(trace=msa_proxy_score_fp4_trace)\ndef msa_proxy_score_fp4(\n q_fp4: torch.Tensor,\n k_fp4: torch.Tensor,\n q_scale: torch.Tensor,\n k_scale: torch.Tensor,\n q_global_scale: float,\n k_global_scale: float,\n cu_seqlens_q: torch.Tensor,\n cu_seqlens_k: Optional[torch.Tensor] = None,\n *,\n page_table: Optional[torch.Tensor] = None,\n seqused_k: Optional[torch.Tensor] = None,\n causal: bool = True,\n max_seqlen_q: Optional[int] = None,\n max_k_tiles: Optional[int] = None,\n output: Optional[torch.Tensor] = None,\n reduce_heads: bool = False,\n q_offset=None,\n) -> torch.Tensor:\n \"\"\"NVFP4 MSA dense proxy pass for SM120/SM121 (the FP4 counterpart of\n :func:`msa_proxy_score`).\n\n Same contract and output as :func:`msa_proxy_score` (per-KV-block max of\n the unscaled, causally-masked ``Q K^T`` logits), but Q/K arrive pre-quantized\n as packed NVFP4 (``e2m1`` + per-16 ``e4m3`` block scales + per-tensor global\n scales), so the index K is read from HBM at ~4 bits/elem. The full-KV index\n read is the dominant decode-step cost, so this is the bandwidth-saving\n path; :func:`msa_proxy_score` stays as the bf16 precision reference.\n\n Numerics equal a torch dequant of the same packed inputs (not the bf16\n reference, which differs by fp4 rounding). The two global scales are folded\n into the logits as ``q_global_scale * k_global_scale`` before the block-max.\n Short q (decode, including multi-token verify) uses a head-fused packed\n schedule on the fp4 tensor cores (``MmaMXF4NVF4Op``) that scores all\n ``group_size`` heads of a kv_head from one shared index-K read; longer q\n uses the general tensor-core schedule. Both flat and paged K are supported;\n see the dispatch below for the exact regime bounds.\n\n Parameters\n ----------\n q_fp4 : torch.Tensor\n ``(total_q, num_qo_heads, 64)`` uint8, packed e2m1 (2 nibbles/byte).\n k_fp4 : torch.Tensor\n Flat ``(total_k, num_kv_heads, 64)`` with ``cu_seqlens_k``, or paged\n ``(num_pages, num_kv_heads, 128, 64)`` with ``page_table`` +\n ``seqused_k``. ``num_qo_heads`` must be a multiple of ``num_kv_heads``.\n q_scale, k_scale : torch.Tensor\n Flat uint8 e4m3 block scales in the cuBLAS 128x4 tiled layout, indexed by\n logical row ``token*num_heads + head`` (paged K: ``(page*num_kv_heads +\n kv_head)*128 + token_in_page``). Produced by :func:`nvfp4_quantize`\n (128x4 layout, ``sf_vec_size=16``); shared with the attention + decode kernels.\n q_global_scale, k_global_scale : float\n Per-tensor inverse global scales (``1 / global_scale``).\n cu_seqlens_q, cu_seqlens_k : torch.Tensor\n As in :func:`msa_proxy_score`.\n page_table : torch.Tensor, optional\n As in :func:`msa_proxy_score`.\n seqused_k : torch.Tensor, optional\n As in :func:`msa_proxy_score`.\n causal : bool\n As in :func:`msa_proxy_score`.\n max_seqlen_q : int, optional\n As in :func:`msa_proxy_score`.\n max_k_tiles : int, optional\n As in :func:`msa_proxy_score`.\n output : torch.Tensor, optional\n As in :func:`msa_proxy_score`.\n reduce_heads : bool\n As in :func:`msa_proxy_score`.\n q_offset : int or torch.Tensor, optional\n As in :func:`msa_proxy_score`.\n\n Returns\n -------\n torch.Tensor\n Float32 ``max_score`` for :func:`msa_topk_select`:\n ``(num_qo_heads, max_k_tiles, total_q)``, or\n ``(1, max_k_tiles, total_q)`` when ``reduce_heads=True``.\n \"\"\"\n import cutlass\n import cutlass.cute as cute\n\n from .cute_dsl.proxy_score_fp4_sm12x import (\n MsaProxyScoreFp4MmaDecodePackedSm12x,\n MsaProxyScoreFp4MmaSm12x,\n )\n from ._common import (\n _compile_cache,\n _cutlass_dtype,\n _fake,\n _q_offset_tensor,\n )\n\n if not is_sm12x_supported(q_fp4.device):\n raise RuntimeError(\n \"msa_proxy_score_fp4 requires SM120 or SM121 and CUDA >= 12.8\"\n )\n if q_fp4.dtype != torch.uint8 or k_fp4.dtype != torch.uint8:\n raise ValueError(\"q_fp4/k_fp4 must be packed uint8 (e2m1x2)\")\n if q_scale.dtype != torch.uint8 or k_scale.dtype != torch.uint8:\n raise ValueError(\"q_scale/k_scale must be uint8 (e4m3 bytes)\")\n hd2 = _BLK_KV // 2 # 64 packed bytes / row\n q_scale = q_scale.reshape(-1)\n k_scale = k_scale.reshape(-1)\n total_q, num_qo_heads, q_last = q_fp4.shape\n if q_last != hd2:\n raise ValueError(f\"q_fp4 last dim must be {hd2} (head_dim/2), got {q_last}\")\n num_kv_heads = k_fp4.shape[1]\n if num_qo_heads % num_kv_heads != 0:\n raise ValueError(\"num_qo_heads must be a multiple of num_kv_heads\")\n dev = q_fp4.device\n\n paged = page_table is not None\n if paged:\n if seqused_k is None:\n raise ValueError(\"paged proxy requires seqused_k\")\n if k_fp4.ndim != 4 or k_fp4.shape[2] != _BLK_KV or k_fp4.shape[3] != hd2:\n raise ValueError(\n f\"paged k_fp4 must be (num_pages, num_kv_heads, {_BLK_KV}, {hd2})\"\n )\n batch_size = seqused_k.numel()\n # Paged addressing comes entirely from page_table, so the kernel needs\n # only each request's length. Pass seqused_k through instead of building\n # a prefix sum (zeros + cumsum + slice-copy on every call) for the\n # kernel to difference back apart; `paged` tells it which form this is.\n k_len_or_cu = seqused_k if seqused_k.device == dev else seqused_k.to(dev)\n k_len_or_cu = k_len_or_cu.contiguous()\n pt_dev = page_table.contiguous()\n else:\n if cu_seqlens_k is None:\n raise ValueError(\"flat proxy requires cu_seqlens_k\")\n if k_fp4.ndim != 3:\n raise ValueError(\"flat k_fp4 must be (total_k, num_kv_heads, 64)\")\n k_len_or_cu = cu_seqlens_k.to(dev)\n pt_dev = _proxy_dummies(dev.index)[0]\n batch_size = k_len_or_cu.numel() - 1\n\n cu_q_dev = cu_seqlens_q.to(dev)\n max_seqlen_q, max_k_tiles = _resolve_proxy_dims(\n cu_seqlens_q, k_len_or_cu, max_seqlen_q, max_k_tiles, output, k_is_lengths=paged\n )\n\n per_head_shape = (num_qo_heads, max_k_tiles, total_q)\n final_shape = (1, max_k_tiles, total_q) if reduce_heads else per_head_shape\n if output is not None:\n if output.shape != final_shape:\n raise ValueError(f\"output must be {final_shape}\")\n if output.dtype != torch.float32:\n raise ValueError(\"output must be float32\")\n if reduce_heads or output is None:\n per_head = torch.empty(per_head_shape, dtype=torch.float32, device=dev)\n else:\n per_head = output\n\n # Head-fused decode path, as in msa_proxy_score, but on the 128-row fp4-MMA\n # tile and with no fp8-K exclusion.\n _PACK_ROWS = MsaProxyScoreFp4MmaSm12x._M\n group_size = num_qo_heads // num_kv_heads\n use_packed = (\n group_size >= 2\n and _PACK_ROWS % group_size == 0\n and max_seqlen_q <= _PACK_ROWS // group_size\n )\n pack_q_len = _PACK_ROWS // group_size if use_packed else 0\n\n # Right-aligned decode on the packed path computes the causal limit\n # in-kernel, so no offset tensor (and its build kernels) is needed.\n qoff_default = q_offset is None\n if use_packed and qoff_default:\n qoff_dev = _proxy_dummies(dev.index)[1]\n else:\n qoff_dev = _q_offset_tensor(\n q_offset, cu_q_dev, k_len_or_cu, dev, k_is_lengths=paged\n )\n\n # Base grid CTAs (feeds split-K) and cache key, as in msa_proxy_score.\n if use_packed:\n base_ctas = batch_size * num_kv_heads\n else:\n base_ctas = ((max_seqlen_q + 127) // 128) * batch_size * num_qo_heads\n\n key = (\n \"proxy_fp4\",\n causal,\n paged,\n use_packed,\n pack_q_len,\n qoff_default if use_packed else None,\n )\n compiled = _compile_cache.get(key)\n if compiled is None:\n u8 = _cutlass_dtype(torch.uint8)\n i32 = _cutlass_dtype(torch.int32)\n f32 = _cutlass_dtype(torch.float32)\n (\n s_tq,\n s_hq,\n s_tk,\n s_hkv,\n s_b1,\n # mCuK's own symbol: per-request lengths (batch) when paged, a\n # prefix sum (batch + 1) when flat, so it cannot share mCuQ's dim.\n s_bk,\n s_b0,\n s_pb,\n s_pm,\n s_mt,\n s_qsf,\n s_ksf,\n ) = (cute.sym_int() for _ in range(12))\n if paged:\n k_shape: tuple = (s_tk, s_hkv, _BLK_KV, hd2)\n else:\n k_shape = (s_tk, s_hkv, hd2)\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n kernel_obj: \"MsaProxyScoreFp4MmaSm12x\"\n if use_packed:\n kernel_obj = MsaProxyScoreFp4MmaDecodePackedSm12x(\n head_dim=_BLK_KV,\n is_causal=causal,\n paged=paged,\n qhead_per_kv=group_size,\n pack_q_len=pack_q_len,\n qoff_default=qoff_default,\n )\n else:\n kernel_obj = MsaProxyScoreFp4MmaSm12x(\n head_dim=_BLK_KV,\n is_causal=causal,\n paged=paged,\n )\n compiled = cute.compile(\n kernel_obj,\n _fake(u8, (s_tq, s_hq, hd2), align=4),\n _fake(u8, k_shape, align=4),\n _fake(u8, (s_qsf,), align=4),\n _fake(u8, (s_ksf,), align=4),\n _fake(i32, (s_pb, s_pm), align=4),\n _fake(f32, (s_hq, s_mt, s_tq), align=4),\n _fake(i32, (s_b1,), align=4), # mCuQ\n _fake(i32, (s_bk,), align=4), # mCuK (lengths when paged)\n _fake(i32, (s_b0,), align=4),\n cutlass.Float32(1.0),\n cutlass.Float32(1.0),\n cutlass.Int32(1),\n cutlass.Int32(1),\n cutlass.Int32(1),\n cutlass.Int32(1),\n cutlass.Int32(1), # num_splits\n stream_fake,\n options=\"--enable-tvm-ffi\",\n )\n _compile_cache[key] = compiled\n\n def _call(tensors, ns):\n qf, kf, qs, ks, pt_, ph_, cq_, ck_, qoff_ = tensors\n compiled(\n qf,\n kf,\n qs,\n ks,\n pt_,\n ph_,\n cq_,\n ck_,\n qoff_,\n float(q_global_scale),\n float(k_global_scale),\n int(max_seqlen_q),\n int(batch_size),\n int(num_qo_heads),\n int(max_k_tiles),\n ns,\n )\n return ph_\n\n _run_proxy_autotuned(\n \"msa_proxy_score_fp4\",\n _call,\n [\n q_fp4,\n k_fp4,\n q_scale,\n k_scale,\n pt_dev,\n per_head,\n cu_q_dev,\n k_len_or_cu,\n qoff_dev,\n ],\n max_seqlen_q=max_seqlen_q,\n max_k_tiles=max_k_tiles,\n base_ctas=base_ctas,\n device=dev,\n heuristic=_proxy_split_k_fp4,\n causal=causal,\n paged=paged,\n reduce_heads=reduce_heads,\n )\n\n if not reduce_heads:\n return per_head\n if output is None:\n output = torch.empty(final_shape, dtype=torch.float32, device=dev)\n torch.amax(per_head, dim=0, keepdim=True, out=output)\n return output\n"},"diff":{"kind":"string","value":"--- flashinfer/msa_ops/proxy_score.py\n+++ flashinfer/msa_ops/proxy_score.py\n@@ -477,10 +477,10 @@\n q = q.to(torch.bfloat16)\n q_fp8 = False\n \n- # Right-aligned decode on the stream and key-major paths computes the\n- # causal limit in-kernel, so no offset tensor (and its build kernels,\n- # which dominate at batch 1) is needed.\n- if (use_stream or use_keymajor) and qoff_default:\n+ # Right-aligned decode on the stream and packed paths computes the causal\n+ # limit in-kernel, so no offset tensor (and its build kernels, which\n+ # dominate at batch 1) is needed.\n+ if (use_stream or use_packed) and qoff_default:\n qoff_dev = _proxy_dummies(dev.index)[1]\n else:\n qoff_dev = _q_offset_tensor(\n@@ -501,7 +501,7 @@\n use_keymajor,\n group_size,\n pack_q_len,\n- qoff_default if (use_stream or use_keymajor) else None,\n+ qoff_default if (use_stream or use_packed) else None,\n )\n # The packed fp8 schedules take e4m3 operands as 16-bit torch views (half\n # the last dim): the kernel moves raw bytes and upconverts in registers,\n@@ -571,6 +571,7 @@\n kv_fp8=kv_fp8,\n qhead_per_kv=group_size,\n pack_q_len=pack_q_len,\n+ qoff_default=qoff_default,\n )\n else:\n kernel_obj = MsaProxyScoreSm12x(\n@@ -813,13 +814,10 @@\n if k_fp4.ndim != 3:\n raise ValueError(\"flat k_fp4 must be (total_k, num_kv_heads, 64)\")\n k_len_or_cu = cu_seqlens_k.to(dev)\n- pt_dev = torch.zeros((1, 1), dtype=torch.int32, device=dev)\n+ pt_dev = _proxy_dummies(dev.index)[0]\n batch_size = k_len_or_cu.numel() - 1\n \n cu_q_dev = cu_seqlens_q.to(dev)\n- qoff_dev = _q_offset_tensor(\n- q_offset, cu_q_dev, k_len_or_cu, dev, k_is_lengths=paged\n- )\n max_seqlen_q, max_k_tiles = _resolve_proxy_dims(\n cu_seqlens_q, k_len_or_cu, max_seqlen_q, max_k_tiles, output, k_is_lengths=paged\n )\n@@ -847,13 +845,30 @@\n )\n pack_q_len = _PACK_ROWS // group_size if use_packed else 0\n \n+ # Right-aligned decode on the packed path computes the causal limit\n+ # in-kernel, so no offset tensor (and its build kernels) is needed.\n+ qoff_default = q_offset is None\n+ if use_packed and qoff_default:\n+ qoff_dev = _proxy_dummies(dev.index)[1]\n+ else:\n+ qoff_dev = _q_offset_tensor(\n+ q_offset, cu_q_dev, k_len_or_cu, dev, k_is_lengths=paged\n+ )\n+\n # Base grid CTAs (feeds split-K) and cache key, as in msa_proxy_score.\n if use_packed:\n base_ctas = batch_size * num_kv_heads\n else:\n base_ctas = ((max_seqlen_q + 127) // 128) * batch_size * num_qo_heads\n \n- key = (\"proxy_fp4\", causal, paged, use_packed, pack_q_len)\n+ key = (\n+ \"proxy_fp4\",\n+ causal,\n+ paged,\n+ use_packed,\n+ pack_q_len,\n+ qoff_default if use_packed else None,\n+ )\n compiled = _compile_cache.get(key)\n if compiled is None:\n u8 = _cutlass_dtype(torch.uint8)\n@@ -888,6 +903,7 @@\n paged=paged,\n qhead_per_kv=group_size,\n pack_q_len=pack_q_len,\n+ qoff_default=qoff_default,\n )\n else:\n kernel_obj = MsaProxyScoreFp4MmaSm12x("},"lines_added":{"kind":"number","value":26,"string":"26"},"lines_removed":{"kind":"number","value":10,"string":"10"},"files_in_commit":{"kind":"number","value":7,"string":"7"},"models_mentioned":{"kind":"list like","value":["minimax"],"string":"[\n \"minimax\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["RTX5080","SM120","SM121"],"string":"[\n \"RTX5080\",\n \"SM120\",\n \"SM121\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":["2.2x","2.1x"],"string":"[\n \"2.2x\",\n \"2.1x\"\n]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cute_dsl kernel file from flashinfer (flashinfer/msa_ops/proxy_score.py).\n\nGoal: perf(msa): chunked top-k and in-kernel causal offsets for the SM12x indexer\nTarget hardware: RTX5080, SM120, SM121\nTarget models: minimax\n\nCurrent file:\n```python\n\"\"\"\nCopyright (c) 2026 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\"\"\"\n\nimport functools\nfrom typing import Optional, Tuple, Union\n\nimport torch\n\nfrom ..api_logging import flashinfer_api\nfrom ..autotuner import AutoTuner, TunableRunner, TuningConfig\nfrom ..trace.templates.msa import (\n msa_proxy_score_fp4_trace,\n msa_proxy_score_trace,\n)\nfrom ..utils import get_device_sm_count, is_sm12x_supported\nfrom ._common import _BLK_KV\n\n# NVFP4 scale granularity: one e4m3 block scale per 16 e2m1 elements.\n_SF_VEC_SIZE = 16\n\n\ndef _resolve_proxy_dims(\n cu_seqlens_q, k_len_or_cu, max_seqlen_q, max_k_tiles, output, k_is_lengths=False\n):\n \"\"\"Resolve grid dims ``(max_seqlen_q, max_k_tiles)`` as Python ints; deriving\n them reads ``cu_seqlens`` on host, so under CUDA-graph capture we raise.\n\n ``k_len_or_cu`` is per-request lengths when ``k_is_lengths`` (the paged\n path), else a prefix sum.\"\"\"\n if max_k_tiles is None and output is not None:\n max_k_tiles = int(output.shape[1])\n if max_seqlen_q is not None and max_k_tiles is not None:\n return max_seqlen_q, max_k_tiles\n if torch.cuda.is_current_stream_capturing():\n raise ValueError(\n \"msa_proxy_score[_fp4] needs max_seqlen_q and max_k_tiles during CUDA \"\n \"graph capture (deriving them from cu_seqlens would sync the stream). \"\n \"Pass both (computed once at plan time) or pre-allocate `output`.\"\n )\n if max_seqlen_q is None:\n cu_q_cpu = cu_seqlens_q.cpu()\n max_seqlen_q = int((cu_q_cpu[1:] - cu_q_cpu[:-1]).max().item())\n if max_k_tiles is None:\n k_cpu = k_len_or_cu.cpu()\n seqlens_k = k_cpu if k_is_lengths else (k_cpu[1:] - k_cpu[:-1])\n max_k_tiles = int((seqlens_k.max().item() + _BLK_KV - 1) // _BLK_KV)\n return max_seqlen_q, max_k_tiles\n\n\ndef _proxy_split_k(\n base_ctas: int,\n max_k_tiles: int,\n device,\n *,\n wave_target: float,\n gate_factor: float,\n ceil_to_target: bool,\n) -> int:\n \"\"\"KV-block split factor that fills the SMs when the base proxy grid is small\n (long context, low batch). Splits need no reduction: the per-(head, kv_block,\n query) output means each split writes disjoint columns. Returns 1 once the\n base grid already covers ``gate_factor`` SM-waves.\"\"\"\n if base_ctas <= 0 or max_k_tiles <= 1:\n return 1\n num_sms = get_device_sm_count(device)\n if base_ctas >= gate_factor * num_sms:\n return 1\n target = wave_target * num_sms\n splits = (\n -(-int(target) // base_ctas) if ceil_to_target else round(target / base_ctas)\n )\n return max(1, min(splits, max_k_tiles))\n\n\n# bf16 split-K heuristic, tuned empirically: target ~1.5 waves and round (the\n# Q reload per split makes over-splitting regress).\n_proxy_split_k_bf16 = functools.partial(\n _proxy_split_k, wave_target=1.5, gate_factor=1.0, ceil_to_target=False\n)\n\n\n@functools.lru_cache(maxsize=None)\ndef _split_k_makespan_argmin(\n base_ctas: int, max_k_tiles: int, resident_ctas: int\n) -> int:\n \"\"\"Split factor minimizing a makespan model: full resident-CTA waves times\n per-split work, with ~one KV block of fixed per-CTA overhead (launch + Q\n load). Ties break to the smaller split (fewer Q reloads). A model rather\n than a wave target because the optimum shifts between filling residency\n exactly (moderate batch), max split (batch 1), and no split (large batch,\n short kv) -- no single target covers all three regimes.\"\"\"\n best_ns, best_cost = 1, None\n for ns in range(1, min(max_k_tiles, 4096) + 1):\n waves = -(-(base_ctas * ns) // resident_ctas)\n cost = waves * (-(-max_k_tiles // ns) + 1)\n if best_cost is None or cost < best_cost:\n best_ns, best_cost = ns, cost\n return best_ns\n\n\ndef _proxy_split_k_fp4(base_ctas: int, max_k_tiles: int, device) -> int:\n \"\"\"fp4 split-K: 4-bit K reads make splits cheap, so pick by the makespan\n model at the kernel's 2-CTA/SM residency (see _MIN_BLOCKS_PER_MP).\"\"\"\n if base_ctas <= 0 or max_k_tiles <= 1:\n return 1\n return _split_k_makespan_argmin(\n base_ctas, max_k_tiles, 2 * get_device_sm_count(device)\n )\n\n\nclass _ProxySplitKRunner(TunableRunner):\n \"\"\"Autotunes the proxy kv-block split factor: ``tactic`` *is* the split\n factor (a runtime arg, so one compiled kernel covers every candidate).\"\"\"\n\n def __init__(\n self,\n call_fn,\n *,\n max_seqlen_q,\n max_k_tiles,\n base_ctas,\n device,\n heuristic,\n causal,\n paged,\n reduce_heads,\n ):\n # call_fn(inputs, num_splits) -> output; lets one runner serve both the\n # bf16 and (longer-signature) fp4 proxy invocations.\n self._call = call_fn\n self._msq = int(max_seqlen_q)\n self._mkt = int(max_k_tiles)\n self._base = int(base_ctas)\n self._device = device\n self._heuristic = heuristic # callable(base_ctas, max_k_tiles, device) -> int\n self._causal = bool(causal)\n self._paged = bool(paged)\n self._reduce = bool(reduce_heads)\n\n def __hash__(self):\n return hash(type(self))\n\n def get_valid_tactics(self, inputs, profile):\n # Powers of two up to ~4 SM-waves, capped by max_k_tiles; always include\n # the closed-form heuristic so a tuned op is never worse than eager.\n num_sms = get_device_sm_count(self._device)\n cap = min(self._mkt, max(1, -(-4 * num_sms // max(self._base, 1))))\n cands = {s for s in (1, 2, 4, 8, 16, 32) if s <= cap}\n cands.add(self._heuristic(self._base, self._mkt, self._device))\n return sorted(cands)\n\n def get_cache_key_extras(self, inputs):\n # max_seqlen_q / max_k_tiles are varlen-derived (not in any tensor shape),\n # so they must key the cache; causal/paged/reduce flip the work pattern.\n return (self._causal, self._paged, self._reduce, self._msq, self._mkt)\n\n def forward(self, inputs, tactic: int = -1, do_preparation: bool = False, **kwargs):\n # tactic == -1 falls back to the closed-form heuristic, so eager\n # (un-tuned) behavior is unchanged.\n ns = (\n tactic\n if tactic >= 0\n else self._heuristic(self._base, self._mkt, self._device)\n )\n return self._call(inputs, int(ns))\n\n\n# (op, shape) keys that already went through the autotuner in this process. Until\n# a shape is tuned the proxy uses its closed-form heuristic and skips choose_one,\n# whose per-call lock/bookkeeping (~tens of us) would dominate the tiny low-batch\n# decode.\n_PROXY_TUNED: set = set()\n\n\ndef _proxy_tuned_key(\n op_name, *, causal, paged, reduce_heads, max_seqlen_q, max_k_tiles, base_ctas\n):\n # base_ctas folds in batch/heads/max_seqlen_q, so this matches the autotuner's\n # own cache granularity (shape + get_cache_key_extras) closely enough to gate on.\n return (\n op_name,\n bool(causal),\n bool(paged),\n bool(reduce_heads),\n int(max_seqlen_q),\n int(max_k_tiles),\n int(base_ctas),\n )\n\n\ndef _run_proxy_autotuned(\n op_name,\n call_fn,\n tensors,\n *,\n max_seqlen_q,\n max_k_tiles,\n base_ctas,\n device,\n heuristic,\n causal,\n paged,\n reduce_heads,\n):\n \"\"\"Run the proxy with an autotuned split factor; un-tuned shapes use the\n closed-form heuristic directly and skip the autotuner entirely.\"\"\"\n tuner = AutoTuner.get()\n tuning = tuner.is_tuning_mode\n tuned_key = _proxy_tuned_key(\n op_name,\n causal=causal,\n paged=paged,\n reduce_heads=reduce_heads,\n max_seqlen_q=max_seqlen_q,\n max_k_tiles=max_k_tiles,\n base_ctas=base_ctas,\n )\n if tuning:\n _PROXY_TUNED.add(tuned_key)\n elif tuned_key not in _PROXY_TUNED:\n call_fn(tensors, heuristic(base_ctas, max_k_tiles, device))\n return\n\n runner = _ProxySplitKRunner(\n call_fn,\n max_seqlen_q=max_seqlen_q,\n max_k_tiles=max_k_tiles,\n base_ctas=base_ctas,\n device=device,\n heuristic=heuristic,\n causal=causal,\n paged=paged,\n reduce_heads=reduce_heads,\n )\n # No DynamicTensorSpec: the autotuner would synthesize a shape-correct but\n # value-invalid varlen cu_seqlens; with static inputs it profiles the\n # candidates on the caller's real (valid) tensors.\n runner_sel, tactic = tuner.choose_one(op_name, [runner], TuningConfig(), tensors)\n runner_sel(inputs=tensors, tactic=tactic)\n\n\n@functools.cache\ndef _proxy_dummies(device_index: int):\n # Signature fillers for paths that never read them; cached so repeat decode\n # calls do not launch fill kernels.\n dev = torch.device(\"cuda\", device_index)\n return (\n torch.zeros((1, 1), dtype=torch.int32, device=dev),\n torch.zeros(1, dtype=torch.int32, device=dev),\n )\n\n\n@flashinfer_api(trace=msa_proxy_score_trace)\ndef msa_proxy_score(\n q: torch.Tensor,\n k: torch.Tensor,\n cu_seqlens_q: torch.Tensor,\n cu_seqlens_k: Optional[torch.Tensor] = None,\n *,\n page_table: Optional[torch.Tensor] = None,\n seqused_k: Optional[torch.Tensor] = None,\n causal: bool = True,\n max_seqlen_q: Optional[int] = None,\n max_k_tiles: Optional[int] = None,\n output: Optional[torch.Tensor] = None,\n reduce_heads: bool = False,\n q_offset=None,\n) -> torch.Tensor:\n \"\"\"MSA dense proxy pass for SM120/SM121: per-KV-block max attention\n logits.\n\n Computes ``max_score[h, t, q]``, the maximum of the unscaled,\n causally-masked ``Q K^T`` logits over the 128 tokens of KV block ``t``,\n for every query token and query head. The output feeds directly into\n :func:`msa_topk_select`. KV blocks beyond a sequence's valid range, or\n entirely above the causal limit, yield ``-inf``.\n\n There is no softmax and no V: this is MSA pipeline stage 1.\n\n Single-token decode uses a dim-parallel scalar schedule that streams\n index-K straight to registers. Short multi-token decode (MTP) uses a\n head-fused packed schedule that scores all ``group_size`` heads of a\n kv_head from one shared index-K read. Prefill uses the general schedule;\n see the dispatch below for the exact regime bounds.\n\n Parameters\n ----------\n q : torch.Tensor\n ``(total_q, num_qo_heads, 128)``, bf16 or fp16 (the cheap proxy Q).\n May be fp8 E4M3 when ``k`` is fp8: decode shapes consume it natively,\n other shapes upconvert it once internally.\n k : torch.Tensor\n Flat ``(total_k, num_kv_heads, 128)`` with ``cu_seqlens_k``, or\n paged ``(num_pages, num_kv_heads, 128, 128)`` with ``page_table`` +\n ``seqused_k``. May be fp8 E4M3 (upconverted in-kernel).\n ``num_qo_heads`` must be a multiple of ``num_kv_heads``.\n cu_seqlens_q : torch.Tensor\n ``(batch_size + 1,)`` int32 cumulative query lengths.\n cu_seqlens_k : torch.Tensor, optional\n ``(batch_size + 1,)`` int32 cumulative KV lengths. Required for flat\n KV layout and unused for paged KV layout.\n page_table : torch.Tensor, optional\n Page-table mapping for paged KV layout. Required together with\n ``seqused_k`` when ``k`` is paged.\n seqused_k : torch.Tensor, optional\n Per-sequence valid KV-token counts. Required together with\n ``page_table`` for paged KV layout.\n causal : bool\n Right-aligned causal masking, applied *before* the block max.\n max_seqlen_q : int, optional\n Maximum query length. Required by some CUDA Graph / compilation paths.\n max_k_tiles : int, optional\n Number of KV-block columns in the output; defaults to the maximum\n ``ceil(seqlen_k / 128)`` over the batch.\n output : torch.Tensor, optional\n Pre-allocated float32 output. Shape is\n ``(num_qo_heads, max_k_tiles, total_q)`` normally, or\n ``(1, max_k_tiles, total_q)`` when ``reduce_heads=True``.\n reduce_heads : bool\n If ``True``, max-reduce the per-head ``max_score`` over the query-head\n axis and return a single ``(1, max_k_tiles, total_q)`` score. Use this\n when the query heads are an indexer's proxy heads that collapse to one\n shared block selection per query (MiniMax-M3 indexer semantics).\n Defaults to ``False``: per-head ``max_score``, where each head selects\n its own blocks.\n The reduction is currently a post-kernel ``amax`` over the per-head\n buffer (the kernel is one CTA per head, so a cross-head epilogue would\n need cross-CTA float atomics); folding it into the kernel is a possible\n future optimization (saves materializing the per-head buffer).\n q_offset : int or torch.Tensor, optional\n Optional query-position offset used by the causal alignment logic.\n\n Returns\n -------\n torch.Tensor\n Float32 ``max_score`` ready for :func:`msa_topk_select`:\n ``(num_qo_heads, max_k_tiles, total_q)``, or\n ``(1, max_k_tiles, total_q)`` when ``reduce_heads=True``.\n \"\"\"\n import cutlass\n import cutlass.cute as cute\n\n from .cute_dsl.proxy_score_sm12x import (\n MsaProxyScoreDecodeKeyMajorSm12x,\n MsaProxyScoreDecodePackedFp8Sm12x,\n MsaProxyScoreDecodePackedSm12x,\n MsaProxyScoreDecodeStreamSm12x,\n MsaProxyScoreSm12x,\n )\n from ._common import (\n _compile_cache,\n _cutlass_dtype,\n _fake,\n _q_offset_tensor,\n )\n\n if not is_sm12x_supported(q.device):\n raise RuntimeError(\"msa_proxy_score requires SM120 or SM121 and CUDA >= 12.8\")\n q_fp8 = q.dtype == torch.float8_e4m3fn\n if q.dtype not in (torch.bfloat16, torch.float16) and not q_fp8:\n raise ValueError(f\"q must be bf16, fp16, or fp8 e4m3, got {q.dtype}\")\n total_q, num_qo_heads, head_dim = q.shape\n if head_dim != 128:\n raise ValueError(f\"head_dim must be 128, got {head_dim}\")\n num_kv_heads = k.shape[1]\n if num_qo_heads % num_kv_heads != 0:\n raise ValueError(\"num_qo_heads must be a multiple of num_kv_heads\")\n kv_fp8 = k.dtype == torch.float8_e4m3fn\n if q_fp8 and not kv_fp8:\n raise ValueError(\"fp8 q requires fp8 k\")\n if not kv_fp8 and k.dtype != q.dtype:\n raise ValueError(\"k dtype must match q (or be float8_e4m3fn)\")\n dev = q.device\n\n paged = page_table is not None\n if paged:\n if seqused_k is None:\n raise ValueError(\"paged proxy requires seqused_k\")\n if k.ndim != 4 or k.shape[2] != _BLK_KV or k.shape[3] != head_dim:\n raise ValueError(\n f\"paged k must be (num_pages, num_kv_heads, {_BLK_KV}, {head_dim})\"\n )\n batch_size = seqused_k.numel()\n # Paged addressing comes entirely from page_table, so the kernel needs\n # only each request's length. Pass seqused_k through instead of building\n # a prefix sum (zeros + cumsum + slice-copy on every call) for the\n # kernel to difference back apart; `paged` tells it which form this is.\n k_len_or_cu = seqused_k if seqused_k.device == dev else seqused_k.to(dev)\n k_len_or_cu = k_len_or_cu.contiguous()\n pt_dev = page_table.contiguous()\n else:\n if cu_seqlens_k is None:\n raise ValueError(\"flat proxy requires cu_seqlens_k\")\n if k.ndim != 3:\n raise ValueError(\"flat k must be (total_k, num_kv_heads, head_dim)\")\n k_len_or_cu = cu_seqlens_k.to(dev)\n pt_dev = _proxy_dummies(dev.index)[0]\n batch_size = k_len_or_cu.numel() - 1\n\n cu_q_dev = cu_seqlens_q.to(dev)\n max_seqlen_q, max_k_tiles = _resolve_proxy_dims(\n cu_seqlens_q, k_len_or_cu, max_seqlen_q, max_k_tiles, output, k_is_lengths=paged\n )\n\n per_head_shape = (num_qo_heads, max_k_tiles, total_q)\n final_shape = (1, max_k_tiles, total_q) if reduce_heads else per_head_shape\n if output is not None:\n if output.shape != final_shape:\n raise ValueError(f\"output must be {final_shape}\")\n if output.dtype != torch.float32:\n raise ValueError(\"output must be float32\")\n\n # The kernel always writes the per-head buffer; reduce_heads then collapses\n # it. When not reducing and an output was given, that buffer *is* the output.\n if reduce_heads or output is None:\n per_head = torch.empty(per_head_shape, dtype=torch.float32, device=dev)\n else:\n per_head = output\n\n group_size = num_qo_heads // num_kv_heads\n _PACK_ROWS = 64 # bf16 MMA q-tile rows (== m_block_size)\n p = 1\n while p < max_seqlen_q:\n p *= 2\n # Fused tiles of at most 32 rows (group_size * next_pow2(q_len)) take the\n # key-major TMA schedule (see MsaProxyScoreDecodeKeyMajorSm12x); larger\n # fused tiles keep the row-major/key-split schedules. bf16 single-token\n # decode stays on the dim-parallel stream schedule (see\n # MsaProxyScoreDecodeStreamSm12x), which also covers the group sizes\n # key-major cannot take; fp8 single-token decode goes key-major, whose\n # in-register convert beats the stream schedule's per-element CUDA-core\n # convert. total_q == batch_size guarantees exactly one q token per\n # request, which the stream schedule's token == batch indexing relies on.\n keymajor_ok = (\n group_size >= 2 and _PACK_ROWS % group_size == 0 and group_size * p <= 32\n )\n use_stream = (\n max_seqlen_q == 1\n and total_q == batch_size\n and group_size <= 8\n and not (kv_fp8 and keymajor_ok)\n )\n qoff_default = q_offset is None\n\n # Head-fused decode path: pack group_size heads x pack_q_len q-tokens into one\n # 64-row MMA tile so index-K is read once per (batch, kv_head). Outside the regime\n # (prefill, group_size not dividing 64) use the general schedule.\n use_packed = (\n not use_stream\n and group_size >= 2\n and _PACK_ROWS % group_size == 0\n and max_seqlen_q <= _PACK_ROWS // group_size\n )\n use_keymajor = use_packed and keymajor_ok\n if use_keymajor:\n pack_q_len = p\n else:\n pack_q_len = _PACK_ROWS // group_size if use_packed else 0\n\n # fp8 q (the vLLM M3 fp8-cache contract) is consumed natively only by the\n # key-major schedule; other shapes upconvert once (e4m3 -> bf16 is\n # lossless) and take their usual route.\n if q_fp8 and not use_keymajor:\n q = q.to(torch.bfloat16)\n q_fp8 = False\n\n # Right-aligned decode on the stream and key-major paths computes the\n # causal limit in-kernel, so no offset tensor (and its build kernels,\n # which dominate at batch 1) is needed.\n if (use_stream or use_keymajor) and qoff_default:\n qoff_dev = _proxy_dummies(dev.index)[1]\n else:\n qoff_dev = _q_offset_tensor(\n q_offset, cu_q_dev, k_len_or_cu, dev, k_is_lengths=paged\n )\n\n # group_size and pack_q_len are constexpr-baked into the decode schedules'\n # gather/epilogue, so each factorization is its own kernel; both must key\n # the cache (key-major's pack_q_len does not determine group_size).\n key = (\n \"proxy\",\n str(q.dtype),\n causal,\n paged,\n kv_fp8,\n use_stream,\n use_packed,\n use_keymajor,\n group_size,\n pack_q_len,\n qoff_default if (use_stream or use_keymajor) else None,\n )\n # The packed fp8 schedules take e4m3 operands as 16-bit torch views (half\n # the last dim): the kernel moves raw bytes and upconverts in registers,\n # and a typed view keeps the TMA/cp.async source alignment provable where\n # an in-kernel recast of a symbolic layout does not. fp8 q rides an f16\n # carrier so its register convert hits the native e4m3 -> f16 path.\n kv16 = kv_fp8 and use_packed\n carrier = torch.float16 if q_fp8 else q.dtype\n q_call = q.contiguous().view(carrier) if q_fp8 else q\n k_call = k.contiguous().view(carrier) if kv16 else k\n compiled = _compile_cache.get(key)\n if compiled is None:\n cdt = _cutlass_dtype(q_call.dtype)\n kdt = _cutlass_dtype(k_call.dtype)\n i32 = _cutlass_dtype(torch.int32)\n f32 = _cutlass_dtype(torch.float32)\n # s_bk is mCuK's own symbol: on the paged path it holds per-request\n # lengths (batch entries), not a prefix sum (batch + 1), so it must not\n # share mCuQ's dim or the compiled signature rejects the call.\n s_tq, s_hq, s_tk, s_hkv, s_b1, s_bk, s_b0, s_pb, s_pm, s_mt = (\n cute.sym_int() for _ in range(10)\n )\n qd = head_dim // 2 if q_fp8 else head_dim\n kd = head_dim // 2 if kv16 else head_dim\n k_shape = (s_tk, s_hkv, _BLK_KV, kd) if paged else (s_tk, s_hkv, kd)\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n kernel_obj: Union[\n \"MsaProxyScoreDecodeKeyMajorSm12x\",\n \"MsaProxyScoreDecodeStreamSm12x\",\n \"MsaProxyScoreSm12x\",\n ]\n if use_stream:\n kernel_obj = MsaProxyScoreDecodeStreamSm12x(\n head_dim=head_dim,\n group_size=group_size,\n is_causal=causal,\n paged=paged,\n kv_fp8=kv_fp8,\n qoff_default=qoff_default,\n )\n elif use_keymajor:\n kernel_obj = MsaProxyScoreDecodeKeyMajorSm12x(\n head_dim=head_dim,\n group_size=group_size,\n pack_q_len=pack_q_len,\n is_causal=causal,\n paged=paged,\n kv_fp8=kv_fp8,\n q_fp8=q_fp8,\n qoff_default=qoff_default,\n )\n elif use_packed:\n # fp8 K gets the key-split warp layout so the e4m3 upconvert\n # is not replicated across warps.\n packed_cls = (\n MsaProxyScoreDecodePackedFp8Sm12x\n if kv_fp8\n else MsaProxyScoreDecodePackedSm12x\n )\n kernel_obj = packed_cls(\n head_dim=head_dim,\n m_block_size=group_size * pack_q_len,\n n_block_size=_BLK_KV,\n num_threads=128,\n is_causal=causal,\n paged=paged,\n kv_fp8=kv_fp8,\n qhead_per_kv=group_size,\n pack_q_len=pack_q_len,\n )\n else:\n kernel_obj = MsaProxyScoreSm12x(\n head_dim=head_dim,\n m_block_size=64,\n n_block_size=_BLK_KV,\n num_threads=128,\n is_causal=causal,\n paged=paged,\n kv_fp8=kv_fp8,\n )\n compiled = cute.compile(\n kernel_obj,\n _fake(cdt, (s_tq, s_hq, qd)),\n _fake(kdt, k_shape),\n _fake(i32, (s_pb, s_pm), align=4),\n _fake(f32, (s_hq, s_mt, s_tq), align=4),\n _fake(i32, (s_b1,), align=4), # mCuQ\n _fake(i32, (s_bk,), align=4), # mCuK (lengths when paged)\n _fake(i32, (s_b0,), align=4),\n cutlass.Int32(1),\n cutlass.Int32(1),\n cutlass.Int32(1),\n cutlass.Int32(1),\n cutlass.Int32(1),\n stream_fake,\n options=\"--enable-tvm-ffi\",\n )\n _compile_cache[key] = compiled\n\n # Base grid CTAs (feeds split-K, see _proxy_split_k): the packed path is one\n # CTA per (batch, kv_head); the general path one per (q-tile, batch, head) with\n # 64-row q-tiles. num_splits is a runtime arg, not part of the cache key.\n if use_packed:\n base_ctas = batch_size * num_kv_heads\n else:\n base_ctas = ((max_seqlen_q + 63) // 64) * batch_size * num_qo_heads\n\n def _call(tensors, ns):\n q_, k_, pt_, ph_, cq_, ck_, qoff_ = tensors\n compiled(\n q_,\n k_,\n pt_,\n ph_,\n cq_,\n ck_,\n qoff_,\n int(max_seqlen_q),\n int(batch_size),\n int(num_qo_heads),\n int(max_k_tiles),\n ns,\n )\n return ph_\n\n if use_stream:\n # One CTA per (KV block, token, kv_head): the grid is already maximally\n # split, so there is no split factor to tune.\n _call([q_call, k_call, pt_dev, per_head, cu_q_dev, k_len_or_cu, qoff_dev], 1)\n else:\n _run_proxy_autotuned(\n \"msa_proxy_score\",\n _call,\n [q_call, k_call, pt_dev, per_head, cu_q_dev, k_len_or_cu, qoff_dev],\n max_seqlen_q=max_seqlen_q,\n max_k_tiles=max_k_tiles,\n base_ctas=base_ctas,\n device=dev,\n heuristic=_proxy_split_k_bf16,\n causal=causal,\n paged=paged,\n reduce_heads=reduce_heads,\n )\n\n if not reduce_heads:\n return per_head\n if output is None:\n output = torch.empty(final_shape, dtype=torch.float32, device=dev)\n torch.amax(per_head, dim=0, keepdim=True, out=output)\n return output\n\n\ndef _quantize_qk_to_nvfp4(\n x: torch.Tensor,\n global_scale: Optional[float] = None,\n) -> Tuple[torch.Tensor, torch.Tensor, float]:\n \"\"\"Test/bench/trace glue (deployment quantizes upstream): quantize a\n ``(total, num_heads, 128)`` bf16/fp16 proxy Q or K to packed NVFP4 in the\n 128x4 tiled scale layout; returns ``(x_fp4, block scales, 1/global_scale)``.\"\"\"\n from flashinfer import nvfp4_quantize\n\n if x.ndim != 3 or x.shape[2] != 128:\n raise ValueError(f\"x must be (total, num_heads, 128), got {tuple(x.shape)}\")\n total, num_heads, head_dim = x.shape\n x2d = x.reshape(-1, head_dim)\n if global_scale is None:\n global_scale = (448.0 * 6.0) / x2d.float().abs().max().clamp_min(1e-12)\n gsf = torch.as_tensor([float(global_scale)], dtype=torch.float32, device=x.device)\n # Default sfLayout is the cuBLAS 128x4 tiled layout; SF row = token*num_heads\n # + head (the natural (total, num_heads, d).reshape(-1, d) row order).\n xq, sf = nvfp4_quantize(x2d, gsf, sf_vec_size=_SF_VEC_SIZE)\n x_fp4 = xq.view(torch.uint8).reshape(total, num_heads, head_dim // 2)\n x_scale = sf.view(torch.uint8).reshape(-1) # flat, 128x4 tiled\n return x_fp4, x_scale, 1.0 / float(global_scale)\n\n\n@flashinfer_api(trace=msa_proxy_score_fp4_trace)\ndef msa_proxy_score_fp4(\n q_fp4: torch.Tensor,\n k_fp4: torch.Tensor,\n q_scale: torch.Tensor,\n k_scale: torch.Tensor,\n q_global_scale: float,\n k_global_scale: float,\n cu_seqlens_q: torch.Tensor,\n cu_seqlens_k: Optional[torch.Tensor] = None,\n *,\n page_table: Optional[torch.Tensor] = None,\n seqused_k: Optional[torch.Tensor] = None,\n causal: bool = True,\n max_seqlen_q: Optional[int] = None,\n max_k_tiles: Optional[int] = None,\n output: Optional[torch.Tensor] = None,\n reduce_heads: bool = False,\n q_offset=None,\n) -> torch.Tensor:\n \"\"\"NVFP4 MSA dense proxy pass for SM120/SM121 (the FP4 counterpart of\n :func:`msa_proxy_score`).\n\n Same contract and output as :func:`msa_proxy_score` (per-KV-block max of\n the unscaled, causally-masked ``Q K^T`` logits), but Q/K arrive pre-quantized\n as packed NVFP4 (``e2m1`` + per-16 ``e4m3`` block scales + per-tensor global\n scales), so the index K is read from HBM at ~4 bits/elem. The full-KV index\n read is the dominant decode-step cost, so this is the bandwidth-saving\n path; :func:`msa_proxy_score` stays as the bf16 precision reference.\n\n Numerics equal a torch dequant of the same packed inputs (not the bf16\n reference, which differs by fp4 rounding). The two global scales are folded\n into the logits as ``q_global_scale * k_global_scale`` before the block-max.\n Short q (decode, including multi-token verify) uses a head-fused packed\n schedule on the fp4 tensor cores (``MmaMXF4NVF4Op``) that scores all\n ``group_size`` heads of a kv_head from one shared index-K read; longer q\n uses the general tensor-core schedule. Both flat and paged K are supported;\n see the dispatch below for the exact regime bounds.\n\n Parameters\n ----------\n q_fp4 : torch.Tensor\n ``(total_q, num_qo_heads, 64)`` uint8, packed e2m1 (2 nibbles/byte).\n k_fp4 : torch.Tensor\n Flat ``(total_k, num_kv_heads, 64)`` with ``cu_seqlens_k``, or paged\n ``(num_pages, num_kv_heads, 128, 64)`` with ``page_table`` +\n ``seqused_k``. ``num_qo_heads`` must be a multiple of ``num_kv_heads``.\n q_scale, k_scale : torch.Tensor\n Flat uint8 e4m3 block scales in the cuBLAS 128x4 tiled layout, indexed by\n logical row ``token*num_heads + head`` (paged K: ``(page*num_kv_heads +\n kv_head)*128 + token_in_page``). Produced by :func:`nvfp4_quantize`\n (128x4 layout, ``sf_vec_size=16``); shared with the attention + decode kernels.\n q_global_scale, k_global_scale : float\n Per-tensor inverse global scales (``1 / global_scale``).\n cu_seqlens_q, cu_seqlens_k : torch.Tensor\n As in :func:`msa_proxy_score`.\n page_table : torch.Tensor, optional\n As in :func:`msa_proxy_score`.\n seqused_k : torch.Tensor, optional\n As in :func:`msa_proxy_score`.\n causal : bool\n As in :func:`msa_proxy_score`.\n max_seqlen_q : int, optional\n As in :func:`msa_proxy_score`.\n max_k_tiles : int, optional\n As in :func:`msa_proxy_score`.\n output : torch.Tensor, optional\n As in :func:`msa_proxy_score`.\n reduce_heads : bool\n As in :func:`msa_proxy_score`.\n q_offset : int or torch.Tensor, optional\n As in :func:`msa_proxy_score`.\n\n Returns\n -------\n torch.Tensor\n Float32 ``max_score`` for :func:`msa_topk_select`:\n ``(num_qo_heads, max_k_tiles, total_q)``, or\n ``(1, max_k_tiles, total_q)`` when ``reduce_heads=True``.\n \"\"\"\n import cutlass\n import cutlass.cute as cute\n\n from .cute_dsl.proxy_score_fp4_sm12x import (\n MsaProxyScoreFp4MmaDecodePackedSm12x,\n MsaProxyScoreFp4MmaSm12x,\n )\n from ._common import (\n _compile_cache,\n _cutlass_dtype,\n _fake,\n _q_offset_tensor,\n )\n\n if not is_sm12x_supported(q_fp4.device):\n raise RuntimeError(\n \"msa_proxy_score_fp4 requires SM120 or SM121 and CUDA >= 12.8\"\n )\n if q_fp4.dtype != torch.uint8 or k_fp4.dtype != torch.uint8:\n raise ValueError(\"q_fp4/k_fp4 must be packed uint8 (e2m1x2)\")\n if q_scale.dtype != torch.uint8 or k_scale.dtype != torch.uint8:\n raise ValueError(\"q_scale/k_scale must be uint8 (e4m3 bytes)\")\n hd2 = _BLK_KV // 2 # 64 packed bytes / row\n q_scale = q_scale.reshape(-1)\n k_scale = k_scale.reshape(-1)\n total_q, num_qo_heads, q_last = q_fp4.shape\n if q_last != hd2:\n raise ValueError(f\"q_fp4 last dim must be {hd2} (head_dim/2), got {q_last}\")\n num_kv_heads = k_fp4.shape[1]\n if num_qo_heads % num_kv_heads != 0:\n raise ValueError(\"num_qo_heads must be a multiple of num_kv_heads\")\n dev = q_fp4.device\n\n paged = page_table is not None\n if paged:\n if seqused_k is None:\n raise ValueError(\"paged proxy requires seqused_k\")\n if k_fp4.ndim != 4 or k_fp4.shape[2] != _BLK_KV or k_fp4.shape[3] != hd2:\n raise ValueError(\n f\"paged k_fp4 must be (num_pages, num_kv_heads, {_BLK_KV}, {hd2})\"\n )\n batch_size = seqused_k.numel()\n # Paged addressing comes entirely from page_table, so the kernel needs\n # only each request's length. Pass seqused_k through instead of building\n # a prefix sum (zeros + cumsum + slice-copy on every call) for the\n # kernel to difference back apart; `paged` tells it which form this is.\n k_len_or_cu = seqused_k if seqused_k.device == dev else seqused_k.to(dev)\n k_len_or_cu = k_len_or_cu.contiguous()\n pt_dev = page_table.contiguous()\n else:\n if cu_seqlens_k is None:\n raise ValueError(\"flat proxy requires cu_seqlens_k\")\n if k_fp4.ndim != 3:\n raise ValueError(\"flat k_fp4 must be (total_k, num_kv_heads, 64)\")\n k_len_or_cu = cu_seqlens_k.to(dev)\n pt_dev = torch.zeros((1, 1), dtype=torch.int32, device=dev)\n batch_size = k_len_or_cu.numel() - 1\n\n cu_q_dev = cu_seqlens_q.to(dev)\n qoff_dev = _q_offset_tensor(\n q_offset, cu_q_dev, k_len_or_cu, dev, k_is_lengths=paged\n )\n max_seqlen_q, max_k_tiles = _resolve_proxy_dims(\n cu_seqlens_q, k_len_or_cu, max_seqlen_q, max_k_tiles, output, k_is_lengths=paged\n )\n\n per_head_shape = (num_qo_heads, max_k_tiles, total_q)\n final_shape = (1, max_k_tiles, total_q) if reduce_heads else per_head_shape\n if output is not None:\n if output.shape != final_shape:\n raise ValueError(f\"output must be {final_shape}\")\n if output.dtype != torch.float32:\n raise ValueError(\"output must be float32\")\n if reduce_heads or output is None:\n per_head = torch.empty(per_head_shape, dtype=torch.float32, device=dev)\n else:\n per_head = output\n\n # Head-fused decode path, as in msa_proxy_score, but on the 128-row fp4-MMA\n # tile and with no fp8-K exclusion.\n _PACK_ROWS = MsaProxyScoreFp4MmaSm12x._M\n group_size = num_qo_heads // num_kv_heads\n use_packed = (\n group_size >= 2\n and _PACK_ROWS % group_size == 0\n and max_seqlen_q <= _PACK_ROWS // group_size\n )\n pack_q_len = _PACK_ROWS // group_size if use_packed else 0\n\n # Base grid CTAs (feeds split-K) and cache key, as in msa_proxy_score.\n if use_packed:\n base_ctas = batch_size * num_kv_heads\n else:\n base_ctas = ((max_seqlen_q + 127) // 128) * batch_size * num_qo_heads\n\n key = (\"proxy_fp4\", causal, paged, use_packed, pack_q_len)\n compiled = _compile_cache.get(key)\n if compiled is None:\n u8 = _cutlass_dtype(torch.uint8)\n i32 = _cutlass_dtype(torch.int32)\n f32 = _cutlass_dtype(torch.float32)\n (\n s_tq,\n s_hq,\n s_tk,\n s_hkv,\n s_b1,\n # mCuK's own symbol: per-request lengths (batch) when paged, a\n # prefix sum (batch + 1) when flat, so it cannot share mCuQ's dim.\n s_bk,\n s_b0,\n s_pb,\n s_pm,\n s_mt,\n s_qsf,\n s_ksf,\n ) = (cute.sym_int() for _ in range(12))\n if paged:\n k_shape: tuple = (s_tk, s_hkv, _BLK_KV, hd2)\n else:\n k_shape = (s_tk, s_hkv, hd2)\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n kernel_obj: \"MsaProxyScoreFp4MmaSm12x\"\n if use_packed:\n kernel_obj = MsaProxyScoreFp4MmaDecodePackedSm12x(\n head_dim=_BLK_KV,\n is_causal=causal,\n paged=paged,\n qhead_per_kv=group_size,\n pack_q_len=pack_q_len,\n )\n else:\n kernel_obj = MsaProxyScoreFp4MmaSm12x(\n head_dim=_BLK_KV,\n is_causal=causal,\n paged=paged,\n )\n compiled = cute.compile(\n kernel_obj,\n _fake(u8, (s_tq, s_hq, hd2), align=4),\n _fake(u8, k_shape, align=4),\n _fake(u8, (s_qsf,), align=4),\n _fake(u8, (s_ksf,), align=4),\n _fake(i32, (s_pb, s_pm), align=4),\n _fake(f32, (s_hq, s_mt, s_tq), align=4),\n _fake(i32, (s_b1,), align=4), # mCuQ\n _fake(i32, (s_bk,), align=4), # mCuK (lengths when paged)\n _fake(i32, (s_b0,), align=4),\n cutlass.Float32(1.0),\n cutlass.Float32(1.0),\n cutlass.Int32(1),\n cutlass.Int32(1),\n cutlass.Int32(1),\n cutlass.Int32(1),\n cutlass.Int32(1), # num_splits\n stream_fake,\n options=\"--enable-tvm-ffi\",\n )\n _compile_cache[key] = compiled\n\n def _call(tensors, ns):\n qf, kf, qs, ks, pt_, ph_, cq_, ck_, qoff_ = tensors\n compiled(\n qf,\n kf,\n qs,\n ks,\n pt_,\n ph_,\n cq_,\n ck_,\n qoff_,\n float(q_global_scale),\n float(k_global_scale),\n int(max_seqlen_q),\n int(batch_size),\n int(num_qo_heads),\n int(max_k_tiles),\n ns,\n )\n return ph_\n\n _run_proxy_autotuned(\n \"msa_proxy_score_fp4\",\n _call,\n [\n q_fp4,\n k_fp4,\n q_scale,\n k_scale,\n pt_dev,\n per_head,\n cu_q_dev,\n k_len_or_cu,\n qoff_dev,\n ],\n max_seqlen_q=max_seqlen_q,\n max_k_tiles=max_k_tiles,\n base_ctas=base_ctas,\n device=dev,\n heuristic=_proxy_split_k_fp4,\n causal=causal,\n paged=paged,\n reduce_heads=reduce_heads,\n )\n\n if not reduce_heads:\n return per_head\n if output is None:\n output = torch.empty(final_shape, dtype=torch.float32, device=dev)\n torch.amax(per_head, dim=0, keepdim=True, out=output)\n return output\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## 📌 Description\n\nFollow-up to #3655, which enabled MiniMax Sparse Attention (MSA) on SM120/SM121. The indexer (proxy score + top-k, the two ops that pick each query's KV blocks) stayed behind vLLM in a few regimes there. All of the gaps traced to `msa_topk_select` and its wrapper rather than to the proxy kernel:\n\n- At decode with small batches, the top-k launches one CTA per (query, head) row, which is 4 CTAs at batch 1, leaving the GPU nearly idle. At 32k context those rows also fall into the radix kernel, which costs about as much as the proxy itself.\n- At long-sequence prefill, the top-k reads scores with strided accesses, and the radix kernel re-reads them once per digit pass.\n- The packed decode wrappers built the causal-offset tensor with three small torch kernels per call, about as costly as the top-k itself at short sequence lengths.\n\nChanges:\n\n- A new chunked top-k. A partial kernel ranks 64-block chunks independently, one CTA per (query, head, chunk), and a merge kernel then re-ranks the surviving candidates for each row. Both use the same ordering as the existing top-k kernels, so selections are identical. The merge launches with PDL to overlap with the partial kernel.\n- A q-tiled variant of the partial kernel for large grids. It covers 32 queries per CTA so that every score load is one coalesced line, which extends the chunked path to prefill under a 128 MB scratch cap; larger grids keep the radix kernel.\n- The packed decode kernels (bf16 and NVFP4) now compute the causal offset in-kernel when `q_offset` is not given, removing the wrapper's torch launches from the decode path.\n\nThe kernel choice depends only on shapes, so it is CUDA-graph safe; a new test covers graph capture on the chunked path.\n\n### Performance\n\nMeasured as in #3655: median GPU time over CUDA-graph replays (CUPTI), with the L2 cache flushed between replays so one replay cannot reuse the previous replay's data. The baseline is vLLM's MiniMax-M3 Triton MSA kernels on the same GPUs and shapes. Each cell is an RTX PRO 6000 Server / RTX 5080 / GB10 triple, and speedup = vLLM time / FlashInfer time, so higher is better. \"Before\" is main as of #3655. The MTP columns run the same call with 4 draft tokens per request, as in a speculative-decoding verify step.\n\nIndexer decode (proxy + top-k), batch 1:\n\n| S | before | after | before (4-token MTP) | after (4-token MTP) |\n|--:|:--:|:--:|:--:|:--:|\n| 2k | 1.31 / 1.43 / 1.33 | 1.31 / 1.42 / 1.38 | 0.73 / 0.71 / 0.91 | 1.20 / 1.12 / 1.29 |\n| 4k | 1.40 / 1.39 / 1.21 | 1.43 / 1.38 / 1.24 | 0.87 / 0.86 / 1.03 | 1.39 / 1.29 / 1.33 |\n| 8k | 1.18 / 1.10 / 1.08 | 1.28 / 1.22 / 1.10 | 0.82 / 0.90 / 0.95 | 1.26 / 1.34 / 1.11 |\n| 16k | 1.18 / 1.09 / 1.02 | 1.25 / 1.17 / 1.09 | 0.95 / 0.85 / 0.97 | 1.34 / 1.19 / 1.09 |\n| 32k | 0.90 / 0.98 / 0.98 | 1.08 / 1.11 / 1.03 | 0.95 / 0.94 / 0.96 | 1.36 / 1.30 / 1.07 |\n\nIndexer prefill, batch 1 (the 2k and 4k rows keep the old kernels and are unchanged within noise):\n\n| S | before | after |\n|--:|:--:|:--:|\n| 8k | 1.04 / 1.14 / 1.01 | 1.06 / 1.18 / 1.02 |\n| 16k | 1.04 / 1.18 / 1.02 | 1.19 / 1.25 / 1.16 |\n| 32k | 0.90 / 1.08 / 0.89 | 1.16 / 1.28 / 1.19 |\n\nMeasured against the kernels this PR replaces:\n\n- The new top-k alone is 1.4-2.2x faster at decode (batch 1 to 128) and 1.2-2.1x faster at 8k-32k prefill.\n- The proxy kernel is untouched, so shapes where it dominates do not move: at batch 128 the end-to-end ratio stays at 1.00-1.03 vs vLLM.\n- The optional NVFP4 decode path also speeds up because its wrapper sheds the same torch launches.\n\n## 🔍 Related Issues\n\nFollow-up to #3655.\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\nAll 155 tests in `tests/msa_ops/` pass on an RTX 5080 (SM120) after rebasing onto current main. This PR adds tests for:\n\n- the dispatch boundaries between the three top-k kernels\n- selection identity between the chunked and existing kernels, including NaN scores, forced blocks, and the ragged q-tile tail\n- CUDA-graph capture on the chunked path\n- explicit `q_offset` on both packed decode kernels\n\nIt also moves the paged-varlen fp4 test's reference to float32: the kernel's fp4 x scale products never round through bf16, so the bf16-rounded reference misses the 5e-2 tolerance on causal-boundary blocks (16 of 40 seeds on an RTX 5080, including the checked-in seed). The same treatment the other fp4 tests already use.\n\n`compute-sanitizer` racecheck and memcheck are clean on the new kernels.\n\n## Reviewer Notes\n\n- Per-token `num_valid_pages` calls (added by #4324) stay on the single-kernel paths: the chunked kernels' geometry is host-derived from the scalar count.\n- Selection identity across the top-k kernels (same bit-key and tie order) is pinned by tests.\n- The row-per-CTA and q-tiled partial kernels keep separate bodies on purpose: the row-per-CTA binary is production-validated.\n- Deferred for the same reason: skipping the redundant sentinel prefill of the candidate scratch, and sharing the forced-slot fill across the three kernels.\n\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n- **New Features**\n - Added chunked top-k selection for large candidate sets, including tiled execution and forced-page handling.\n - Added optional default query-offset handling for packed decode with right-aligned causal masking.\n - Added tracing support for MSA top-k selection.\n\n- **Bug Fixes**\n - Improved causal masking consistency across packed decode formats.\n - Preserved sentinel results and selected-score correctness during top-k selection.\n\n- **Tests**\n - Expanded coverage for large contexts, query offsets, chunked selection, tracing, and CUDA graph execution.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000 Server\", \"model\": null, \"shape\": \"S=2k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.31, \"optimized\": 1.31, \"stated_speedup\": null, \"speedup\": 1.0}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"S=2k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.43, \"optimized\": 1.42, \"stated_speedup\": null, \"speedup\": 1.007}, {\"scope\": \"kernel\", \"hardware\": \"GB10\", \"model\": null, \"shape\": \"S=2k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.33, \"optimized\": 1.38, \"stated_speedup\": null, \"speedup\": 0.9638}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000 Server\", \"model\": null, \"shape\": \"S=2k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.73, \"optimized\": 1.2, \"stated_speedup\": null, \"speedup\": 0.6083}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"S=2k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.71, \"optimized\": 1.12, \"stated_speedup\": null, \"speedup\": 0.6339}, {\"scope\": \"kernel\", \"hardware\": \"GB10\", \"model\": null, \"shape\": \"S=2k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.91, \"optimized\": 1.29, \"stated_speedup\": null, \"speedup\": 0.7054}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000 Server\", \"model\": null, \"shape\": \"S=4k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.4, \"optimized\": 1.43, \"stated_speedup\": null, \"speedup\": 0.979}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"S=4k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.39, \"optimized\": 1.38, \"stated_speedup\": null, \"speedup\": 1.0072}, {\"scope\": \"kernel\", \"hardware\": \"GB10\", \"model\": null, \"shape\": \"S=4k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.21, \"optimized\": 1.24, \"stated_speedup\": null, \"speedup\": 0.9758}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000 Server\", \"model\": null, \"shape\": \"S=4k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.87, \"optimized\": 1.39, \"stated_speedup\": null, \"speedup\": 0.6259}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"S=4k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.86, \"optimized\": 1.29, \"stated_speedup\": null, \"speedup\": 0.6667}, {\"scope\": \"kernel\", \"hardware\": \"GB10\", \"model\": null, \"shape\": \"S=4k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.03, \"optimized\": 1.33, \"stated_speedup\": null, \"speedup\": 0.7744}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000 Server\", \"model\": null, \"shape\": \"S=8k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.18, \"optimized\": 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\"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.9, \"optimized\": 1.34, \"stated_speedup\": null, \"speedup\": 0.6716}, {\"scope\": \"kernel\", \"hardware\": \"GB10\", \"model\": null, \"shape\": \"S=8k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.95, \"optimized\": 1.11, \"stated_speedup\": null, \"speedup\": 0.8559}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000 Server\", \"model\": null, \"shape\": \"S=16k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.18, \"optimized\": 1.25, \"stated_speedup\": null, \"speedup\": 0.944}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"S=16k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.09, \"optimized\": 1.17, \"stated_speedup\": null, \"speedup\": 0.9316}, {\"scope\": \"kernel\", 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\"optimized\": 1.09, \"stated_speedup\": null, \"speedup\": 0.8899}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000 Server\", \"model\": null, \"shape\": \"S=32k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.9, \"optimized\": 1.08, \"stated_speedup\": null, \"speedup\": 0.8333}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"S=32k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.98, \"optimized\": 1.11, \"stated_speedup\": null, \"speedup\": 0.8829}, {\"scope\": \"kernel\", \"hardware\": \"GB10\", \"model\": null, \"shape\": \"S=32k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.98, \"optimized\": 1.03, \"stated_speedup\": null, \"speedup\": 0.9515}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000 Server\", \"model\": null, \"shape\": \"S=32k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.95, \"optimized\": 1.36, \"stated_speedup\": null, \"speedup\": 0.6985}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"S=32k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.94, \"optimized\": 1.3, \"stated_speedup\": null, \"speedup\": 0.7231}, {\"scope\": \"kernel\", \"hardware\": \"GB10\", \"model\": null, \"shape\": \"S=32k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.96, \"optimized\": 1.07, \"stated_speedup\": null, \"speedup\": 0.8972}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000 Server\", \"model\": null, \"shape\": \"S=8k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.04, \"optimized\": 1.06, \"stated_speedup\": null, \"speedup\": 0.9811}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"S=8k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.14, \"optimized\": 1.18, \"stated_speedup\": null, \"speedup\": 0.9661}, {\"scope\": \"kernel\", \"hardware\": \"GB10\", \"model\": null, \"shape\": \"S=8k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.01, \"optimized\": 1.02, \"stated_speedup\": null, \"speedup\": 0.9902}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000 Server\", \"model\": null, \"shape\": \"S=16k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.04, \"optimized\": 1.19, \"stated_speedup\": null, \"speedup\": 0.8739}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"S=16k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.18, \"optimized\": 1.25, \"stated_speedup\": null, \"speedup\": 0.944}, {\"scope\": \"kernel\", \"hardware\": \"GB10\", \"model\": null, \"shape\": \"S=16k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.02, \"optimized\": 1.16, \"stated_speedup\": null, \"speedup\": 0.8793}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000 Server\", \"model\": null, \"shape\": \"S=32k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.9, \"optimized\": 1.16, \"stated_speedup\": null, \"speedup\": 0.7759}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"S=32k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.08, \"optimized\": 1.28, \"stated_speedup\": null, \"speedup\": 0.8438}, {\"scope\": \"kernel\", \"hardware\": \"GB10\", \"model\": null, \"shape\": \"S=32k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.89, \"optimized\": 1.19, \"stated_speedup\": null, \"speedup\": 0.7479}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": null, \"shape\": null, \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.4, \"speedup\": 1.4}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": null, \"shape\": null, \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 2.2, \"speedup\": 2.2}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": null, \"shape\": null, \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.2, \"speedup\": 1.2}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": null, \"shape\": null, \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 2.1, \"speedup\": 2.1}]"},"kernel_speedup":{"kind":"number","value":0.8972,"string":"0.8972"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1077,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"8c5347726f30063fa1c17c4e81e75d509936d610"},"date":{"kind":"string","value":"2026-08-25T22:12:51-04:00"},"pr_number":{"kind":"number","value":4030,"string":"4,030"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/4030"},"title":{"kind":"string","value":"perf(msa): chunked top-k and in-kernel causal offsets for the SM12x indexer (#4030)"},"message":{"kind":"string","value":"perf(msa): chunked top-k and in-kernel causal offsets for the SM12x indexer (#4030)\n\n## 📌 Description\n\nFollow-up to #3655, which enabled MiniMax Sparse Attention (MSA) on\nSM120/SM121. The indexer (proxy score + top-k, the two ops that pick\neach query's KV blocks) stayed behind vLLM in a few regimes there. All\nof the gaps traced to `msa_topk_select` and its wrapper rather than to\nthe proxy kernel:\n\n- At decode with small batches, the top-k launches one CTA per (query,\nhead) row, which is 4 CTAs at batch 1, leaving the GPU nearly idle. At\n32k context those rows also fall into the radix kernel, which costs\nabout as much as the proxy itself.\n- At long-sequence prefill, the top-k reads scores with strided\naccesses, and the radix kernel re-reads them once per digit pass.\n- The packed decode wrappers built the causal-offset tensor with three\nsmall torch kernels per call, about as costly as the top-k itself at\nshort sequence lengths.\n\nChanges:\n\n- A new chunked top-k. A partial kernel ranks 64-block chunks\nindependently, one CTA per (query, head, chunk), and a merge kernel then\nre-ranks the surviving candidates for each row. Both use the same\nordering as the existing top-k kernels, so selections are identical. The\nmerge launches with PDL to overlap with the partial kernel.\n- A q-tiled variant of the partial kernel for large grids. It covers 32\nqueries per CTA so that every score load is one coalesced line, which\nextends the chunked path to prefill under a 128 MB scratch cap; larger\ngrids keep the radix kernel.\n- The packed decode kernels (bf16 and NVFP4) now compute the causal\noffset in-kernel when `q_offset` is not given, removing the wrapper's\ntorch launches from the decode path.\n\nThe kernel choice depends only on shapes, so it is CUDA-graph safe; a\nnew test covers graph capture on the chunked path.\n\n### Performance\n\nMeasured as in #3655: median GPU time over CUDA-graph replays (CUPTI),\nwith the L2 cache flushed between replays so one replay cannot reuse the\nprevious replay's data. The baseline is vLLM's MiniMax-M3 Triton MSA\nkernels on the same GPUs and shapes. Each cell is an RTX PRO 6000 Server\n/ RTX 5080 / GB10 triple, and speedup = vLLM time / FlashInfer time, so\nhigher is better. \"Before\" is main as of #3655. The MTP columns run the\nsame call with 4 draft tokens per request, as in a speculative-decoding\nverify step.\n\nIndexer decode (proxy + top-k), batch 1:\n\n| S | before | after | before (4-token MTP) | after (4-token MTP) |\n|--:|:--:|:--:|:--:|:--:|\n| 2k | 1.31 / 1.43 / 1.33 | 1.31 / 1.42 / 1.38 | 0.73 / 0.71 / 0.91 |\n1.20 / 1.12 / 1.29 |\n| 4k | 1.40 / 1.39 / 1.21 | 1.43 / 1.38 / 1.24 | 0.87 / 0.86 / 1.03 |\n1.39 / 1.29 / 1.33 |\n| 8k | 1.18 / 1.10 / 1.08 | 1.28 / 1.22 / 1.10 | 0.82 / 0.90 / 0.95 |\n1.26 / 1.34 / 1.11 |\n| 16k | 1.18 / 1.09 / 1.02 | 1.25 / 1.17 / 1.09 | 0.95 / 0.85 / 0.97 |\n1.34 / 1.19 / 1.09 |\n| 32k | 0.90 / 0.98 / 0.98 | 1.08 / 1.11 / 1.03 | 0.95 / 0.94 / 0.96 |\n1.36 / 1.30 / 1.07 |\n\nIndexer prefill, batch 1 (the 2k and 4k rows keep the old kernels and\nare unchanged within noise):\n\n| S | before | after |\n|--:|:--:|:--:|\n| 8k | 1.04 / 1.14 / 1.01 | 1.06 / 1.18 / 1.02 |\n| 16k | 1.04 / 1.18 / 1.02 | 1.19 / 1.25 / 1.16 |\n| 32k | 0.90 / 1.08 / 0.89 | 1.16 / 1.28 / 1.19 |\n\nMeasured against the kernels this PR replaces:\n\n- The new top-k alone is 1.4-2.2x faster at decode (batch 1 to 128) and\n1.2-2.1x faster at 8k-32k prefill.\n- The proxy kernel is untouched, so shapes where it dominates do not\nmove: at batch 128 the end-to-end ratio stays at 1.00-1.03 vs vLLM.\n- The optional NVFP4 decode path also speeds up because its wrapper\nsheds the same torch launches.\n\n## 🔍 Related Issues\n\nFollow-up to #3655.\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the\npre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\nAll 155 tests in `tests/msa_ops/` pass on an RTX 5080 (SM120) after\nrebasing onto current main. This PR adds tests for:\n\n- the dispatch boundaries between the three top-k kernels\n- selection identity between the chunked and existing kernels, including\nNaN scores, forced blocks, and the ragged q-tile tail\n- CUDA-graph capture on the chunked path\n- explicit `q_offset` on both packed decode kernels\n\nIt also moves the paged-varlen fp4 test's reference to float32: the\nkernel's fp4 x scale products never round through bf16, so the\nbf16-rounded reference misses the 5e-2 tolerance on causal-boundary\nblocks (16 of 40 seeds on an RTX 5080, including the checked-in seed).\nThe same treatment the other fp4 tests already use.\n\n`compute-sanitizer` racecheck and memcheck are clean on the new kernels.\n\n## Reviewer Notes\n\n- Per-token `num_valid_pages` calls (added by #4324) stay on the\nsingle-kernel paths: the chunked kernels' geometry is host-derived from\nthe scalar count.\n- Selection identity across the top-k kernels (same bit-key and tie\norder) is pinned by tests.\n- The row-per-CTA and q-tiled partial kernels keep separate bodies on\npurpose: the row-per-CTA binary is production-validated.\n- Deferred for the same reason: skipping the redundant sentinel prefill\nof the candidate scratch, and sharing the forced-slot fill across the\nthree kernels.\n\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n- **New Features**\n- Added chunked top-k selection for large candidate sets, including\ntiled execution and forced-page handling.\n- Added optional default query-offset handling for packed decode with\nright-aligned causal masking.\n - Added tracing support for MSA top-k selection.\n\n- **Bug Fixes**\n - Improved causal masking consistency across packed decode formats.\n- Preserved sentinel results and selected-score correctness during top-k\nselection.\n\n- **Tests**\n- Expanded coverage for large contexts, query offsets, chunked\nselection, tracing, and CUDA graph execution.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n\n---------\n\nCo-authored-by: Claude Fable 5 <noreply@anthropic.com>"},"path":{"kind":"string","value":"flashinfer/msa_ops/sparse_topk_select.py"},"language":{"kind":"string","value":"cute_dsl"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"\"\"\"\nCopyright (c) 2026 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\"\"\"\n\nimport functools\nfrom typing import Optional, Union\n\nimport torch\n\nfrom ..api_logging import flashinfer_api\nfrom ..utils import is_sm12x_supported\nfrom ._blackwell_sm100 import blackwell_msa_topk_select, is_blackwell_msa_device\n\n\n@functools.cache\ndef _dummy_nvp(device_index: int) -> torch.Tensor:\n \"\"\"Signature filler for the scalar-``num_valid_pages`` path, which never\n reads it; cached so repeat calls do not launch a fill kernel.\"\"\"\n return torch.zeros(1, dtype=torch.int32, device=torch.device(\"cuda\", device_index))\n\n\n@functools.cache\ndef _get_compiled_topk(topk: int, small: bool, per_token_nvp: bool):\n \"\"\"``small`` picks the O(N^2) count-rank kernel, else the radix kernel; the\n two give identical selections only on distinct-score inputs (ties may differ).\n\n No default on ``per_token_nvp``: it keys the cache, and a call that omitted\n it would compile a second copy of an identical kernel.\"\"\"\n import cutlass\n import cutlass.cute as cute\n\n if small:\n from .cute_dsl.topk_select_countrank_sm12x import (\n TopKSelectCountRankSm12x as _TopKKernel,\n )\n else:\n from .cute_dsl.topk_select_radix_sm12x import ( # type: ignore[assignment,no-redef]\n TopKSelectRadixSm12x as _TopKKernel,\n )\n kernel_obj = _TopKKernel(topk=topk, per_token_nvp=per_token_nvp)\n\n def fk(dtype, ndim, align):\n return cute.runtime.make_fake_compact_tensor(\n dtype,\n tuple(cute.sym_int() for _ in range(ndim)),\n stride_order=tuple(reversed(range(ndim))),\n assumed_align=align,\n )\n\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n compiled = cute.compile(\n kernel_obj,\n fk(cutlass.Float32, 3, 4), # max_score (H, P, S)\n fk(cutlass.Int32, 3, 4), # out (S, H, topk)\n fk(cutlass.Int32, 1, 4), # num_valid_pages tensor (S,)\n cutlass.Int32(1), # num_valid_pages scalar\n cutlass.Int32(0), # force_begin\n cutlass.Int32(0), # force_end\n cutlass.Int32(1), # total_qo_len\n cutlass.Int32(1), # num_qo_heads\n stream_fake,\n options=\"--enable-tvm-ffi\",\n )\n return compiled\n\n\n@flashinfer_api\ndef msa_topk_select(\n max_score: torch.Tensor,\n topk: int,\n num_valid_pages: Optional[Union[int, torch.Tensor]] = None,\n output: Optional[torch.Tensor] = None,\n force_begin_blocks: int = 0,\n force_end_blocks: int = 0,\n) -> torch.Tensor:\n \"\"\"Select the top-K KV blocks per query token based on attention scores.\n\n Implements the block-scoring pass of Minimax Sparse Attention: given the\n per-block maximum attention scores from a cheap proxy prefill, selects the\n ``topk`` most important KV blocks for each (query token, head) pair and\n returns their sorted indices. Dispatch supports compute capability\n 10.0/10.3 and SM120/SM121.\n\n Parameters\n ----------\n max_score : torch.Tensor\n Shape ``(num_qo_heads, max_k_tiles, total_qo_len)``, dtype float32.\n Per-KV-block maximum attention scores produced by the proxy prefill\n pass. Entries for invalid tiles (beyond the actual KV length) must be\n set to ``-inf`` by the caller.\n topk : int\n Number of KV blocks to select per (query token, head). Must be 16.\n num_valid_pages : int or torch.Tensor, optional\n Actual number of valid KV pages (``<= max_k_tiles``). Indices\n ``>= num_valid_pages`` are replaced with -1 and sorted to the tail.\n Defaults to ``max_k_tiles`` (disables clamping).\n\n May instead be an int32 tensor of shape ``(total_qo_len,)`` giving each\n query token its own valid-page count. Callers whose tokens have\n differing causal KV extents (decode batches, chunked prefill) want this:\n with a batch-wide scalar the only way to recover per-token semantics is\n to post-process the output on the host side, which costs several extra\n kernel launches per call and is easy to get wrong. ``force_end_blocks``\n then denotes each token's own trailing local window, and no selected\n index can exceed that token's extent, so no masking pass is needed.\n Entries are clamped in-kernel to ``[0, max_k_tiles]`` (checking them on\n the host would sync), so an over-large count degrades to the full block\n range rather than reading out of bounds.\n\n The tensor form is supported only on SM120/SM121. On compute\n capability 10.0/10.3, pass a scalar or ``None``; a tensor is rejected\n before dispatch because that backend accepts only a scalar bound.\n output : torch.Tensor, optional\n Pre-allocated output tensor of shape\n ``(total_qo_len, num_qo_heads, topk)``, dtype int32. Allocated\n internally if not provided.\n force_begin_blocks : int\n Number of KV blocks at the beginning (sink tokens) to always include.\n force_end_blocks : int\n Number of KV blocks at the end (local window) to always include.\n\n Returns\n -------\n torch.Tensor\n Shape ``(total_qo_len, num_qo_heads, topk)``, dtype int32.\n Ascending KV-block indices; ``-1`` entries are tail-padded invalid\n slots.\n \"\"\"\n if is_blackwell_msa_device(max_score.device):\n if isinstance(num_valid_pages, torch.Tensor):\n raise NotImplementedError(\n \"per-token tensor num_valid_pages is only supported on \"\n \"SM120/SM121; compute capability 10.0/10.3 requires a scalar\"\n )\n return blackwell_msa_topk_select(\n max_score,\n topk,\n num_valid_pages=num_valid_pages,\n output=output,\n force_begin_blocks=force_begin_blocks,\n force_end_blocks=force_end_blocks,\n )\n if not is_sm12x_supported(max_score.device):\n raise RuntimeError(\n \"msa_topk_select requires SM120 or SM121 (Blackwell) and CUDA >= 12.8\"\n )\n\n if max_score.dtype != torch.float32:\n raise ValueError(f\"max_score must be float32, got {max_score.dtype}\")\n if not max_score.is_contiguous():\n raise ValueError(\"max_score must be contiguous\")\n if max_score.ndim != 3:\n raise ValueError(\n f\"max_score must be 3D (num_qo_heads, max_k_tiles, total_qo_len), got {max_score.ndim}D\"\n )\n if topk != 16:\n raise ValueError(f\"topk must be 16, got {topk}\")\n\n from .cute_dsl.topk_select_countrank_sm12x import _MAX_BLOCKS\n\n num_qo_heads, max_k_tiles, total_qo_len = max_score.shape\n\n if num_valid_pages is None:\n num_valid_pages = max_k_tiles\n\n per_token_nvp = isinstance(num_valid_pages, torch.Tensor)\n\n if force_begin_blocks < 0 or force_end_blocks < 0:\n raise ValueError(\"force_begin_blocks / force_end_blocks must be >= 0\")\n if force_begin_blocks + force_end_blocks > topk:\n raise ValueError(\n f\"force_begin_blocks + force_end_blocks ({force_begin_blocks} + \"\n f\"{force_end_blocks}) must be <= topk ({topk})\"\n )\n\n if isinstance(num_valid_pages, torch.Tensor):\n if num_valid_pages.dtype != torch.int32 or num_valid_pages.ndim != 1:\n raise ValueError(\"num_valid_pages tensor must be 1D int32\")\n if num_valid_pages.numel() != total_qo_len:\n raise ValueError(\n f\"num_valid_pages tensor must have total_qo_len ({total_qo_len}) \"\n f\"entries, got {num_valid_pages.numel()}\"\n )\n if not num_valid_pages.is_contiguous():\n raise ValueError(\"num_valid_pages tensor must be contiguous\")\n if num_valid_pages.device != max_score.device:\n raise ValueError(\"num_valid_pages must be on max_score's device\")\n # Values stay on device (reading them would force a sync, which is\n # illegal under CUDA graph capture), so both the max_k_tiles bound and\n # the per-token forced-region fit are clamped in-kernel instead of\n # checked here. Unchecked, an out-of-range entry reads max_score out of\n # bounds and emits block indices the attend kernel cannot address --\n # reachable in practice, since callers derive the count and max_k_tiles\n # from different metadata.\n nvp_dev = num_valid_pages\n nvp_scalar = 0\n # Cannot dispatch on the runtime values without a sync, so bound by the\n # allocated tile count. Conservative: picks radix when max_k_tiles\n # exceeds the SMEM cap even if every token is actually shorter.\n small = int(max_k_tiles) <= _MAX_BLOCKS\n else:\n # Input guards (the radix kernel does not clamp internally): an\n # out-of-range num_valid_pages reads max_score out of bounds, and\n # oversized forced regions overrun the kernel's fixed forced-index\n # buffer or underflow to negative blocks.\n if not 0 < num_valid_pages <= max_k_tiles:\n raise ValueError(\n f\"num_valid_pages must be in (0, max_k_tiles={max_k_tiles}], \"\n f\"got {num_valid_pages}\"\n )\n if force_begin_blocks + force_end_blocks > num_valid_pages:\n raise ValueError(\n f\"force_begin_blocks + force_end_blocks ({force_begin_blocks} + \"\n f\"{force_end_blocks}) must be <= num_valid_pages ({num_valid_pages})\"\n )\n nvp_dev = _dummy_nvp(max_score.device.index)\n nvp_scalar = int(num_valid_pages)\n # Dispatch on the runtime valid-page count: the count-rank kernel only\n # ever touches blocks below num_valid_pages, regardless of the allocated\n # score dimension.\n small = nvp_scalar <= _MAX_BLOCKS\n\n if output is None:\n output = torch.empty(\n (total_qo_len, num_qo_heads, topk),\n dtype=torch.int32,\n device=max_score.device,\n )\n else:\n if output.shape != (total_qo_len, num_qo_heads, topk):\n raise ValueError(\n f\"output shape must be ({total_qo_len}, {num_qo_heads}, {topk}), \"\n f\"got {tuple(output.shape)}\"\n )\n if output.dtype != torch.int32:\n raise ValueError(f\"output must be int32, got {output.dtype}\")\n\n _get_compiled_topk(topk, small, per_token_nvp)(\n max_score,\n output,\n nvp_dev,\n nvp_scalar,\n int(force_begin_blocks),\n int(force_end_blocks),\n int(total_qo_len),\n int(num_qo_heads),\n )\n\n return output\n"},"after_code":{"kind":"string","value":"\"\"\"\nCopyright (c) 2026 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\"\"\"\n\nimport functools\nfrom typing import Optional, Union\n\nimport torch\n\nfrom ..api_logging import flashinfer_api\nfrom ..trace.templates.msa import msa_topk_select_trace\nfrom ..utils import is_sm12x_supported\nfrom ._blackwell_sm100 import blackwell_msa_topk_select, is_blackwell_msa_device\n\n\n@functools.cache\ndef _dummy_nvp(device_index: int) -> torch.Tensor:\n \"\"\"Signature filler for the scalar-``num_valid_pages`` path, which never\n reads it; cached so repeat calls do not launch a fill kernel.\"\"\"\n return torch.zeros(1, dtype=torch.int32, device=torch.device(\"cuda\", device_index))\n\n\ndef _compile_topk(kernel_obj, num_score_tensors: int, num_scalars: int):\n \"\"\"Compile plumbing shared by the chunked top-k variants. All tensor\n arguments are 3D and the scalar values are placeholders (the compiled\n kernels take them dynamically).\"\"\"\n import cutlass\n import cutlass.cute as cute\n\n def fk(dtype):\n return cute.runtime.make_fake_compact_tensor(\n dtype,\n tuple(cute.sym_int() for _ in range(3)),\n stride_order=(2, 1, 0),\n assumed_align=4,\n )\n\n args = [fk(cutlass.Float32)] # max_score (H, P, S)\n args += [fk(cutlass.Int32) for _ in range(num_score_tensors - 1)]\n args += [cutlass.Int32(1)] * num_scalars\n args.append(cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True))\n return cute.compile(kernel_obj, *args, options=\"--enable-tvm-ffi\")\n\n\n@functools.cache\ndef _get_compiled_topk(topk: int, small: bool, per_token_nvp: bool):\n \"\"\"``small`` picks the O(N^2) count-rank kernel, else the radix kernel; the\n two give identical selections only on distinct-score inputs (ties may differ).\n\n No default on ``per_token_nvp``: it keys the cache, and a call that omitted\n it would compile a second copy of an identical kernel.\"\"\"\n import cutlass\n import cutlass.cute as cute\n\n if small:\n from .cute_dsl.topk_select_countrank_sm12x import (\n TopKSelectCountRankSm12x as _TopKKernel,\n )\n else:\n from .cute_dsl.topk_select_radix_sm12x import ( # type: ignore[assignment,no-redef]\n TopKSelectRadixSm12x as _TopKKernel,\n )\n kernel_obj = _TopKKernel(topk=topk, per_token_nvp=per_token_nvp)\n\n def fk(dtype, ndim, align):\n return cute.runtime.make_fake_compact_tensor(\n dtype,\n tuple(cute.sym_int() for _ in range(ndim)),\n stride_order=tuple(reversed(range(ndim))),\n assumed_align=align,\n )\n\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n compiled = cute.compile(\n kernel_obj,\n fk(cutlass.Float32, 3, 4), # max_score (H, P, S)\n fk(cutlass.Int32, 3, 4), # out (S, H, topk)\n fk(cutlass.Int32, 1, 4), # num_valid_pages tensor (S,)\n cutlass.Int32(1), # num_valid_pages scalar\n cutlass.Int32(0), # force_begin\n cutlass.Int32(0), # force_end\n cutlass.Int32(1), # total_qo_len\n cutlass.Int32(1), # num_qo_heads\n stream_fake,\n options=\"--enable-tvm-ffi\",\n )\n return compiled\n\n\n@functools.cache\ndef _get_compiled_topk_chunked(topk: int, tiled: bool):\n \"\"\"Two-kernel (per-chunk rank + merge) variant; selections match the\n count-rank kernel exactly (same bit-key and tie order). ``tiled`` picks\n the full-grid partial kernel (coalesced q-tile staging) over the\n row-per-CTA one.\"\"\"\n from .cute_dsl.topk_select_chunked_sm12x import TopKSelectChunkedSm12x\n\n return _compile_topk(TopKSelectChunkedSm12x(topk=topk, tiled=tiled), 4, 7)\n\n\n@flashinfer_api(trace=msa_topk_select_trace)\ndef msa_topk_select(\n max_score: torch.Tensor,\n topk: int,\n num_valid_pages: Optional[Union[int, torch.Tensor]] = None,\n output: Optional[torch.Tensor] = None,\n force_begin_blocks: int = 0,\n force_end_blocks: int = 0,\n) -> torch.Tensor:\n \"\"\"Select the top-K KV blocks per query token based on attention scores.\n\n Implements the block-scoring pass of Minimax Sparse Attention: given the\n per-block maximum attention scores from a cheap proxy prefill, selects the\n ``topk`` most important KV blocks for each (query token, head) pair and\n returns their sorted indices. Dispatch supports compute capability\n 10.0/10.3 and SM120/SM121.\n\n Parameters\n ----------\n max_score : torch.Tensor\n Shape ``(num_qo_heads, max_k_tiles, total_qo_len)``, dtype float32.\n Per-KV-block maximum attention scores produced by the proxy prefill\n pass. Entries for invalid tiles (beyond the actual KV length) must be\n set to ``-inf`` by the caller.\n topk : int\n Number of KV blocks to select per (query token, head). Must be 16.\n num_valid_pages : int or torch.Tensor, optional\n Actual number of valid KV pages (``<= max_k_tiles``). Indices\n ``>= num_valid_pages`` are replaced with -1 and sorted to the tail.\n Defaults to ``max_k_tiles`` (disables clamping).\n\n May instead be an int32 tensor of shape ``(total_qo_len,)`` giving each\n query token its own valid-page count. Callers whose tokens have\n differing causal KV extents (decode batches, chunked prefill) want this:\n with a batch-wide scalar the only way to recover per-token semantics is\n to post-process the output on the host side, which costs several extra\n kernel launches per call and is easy to get wrong. ``force_end_blocks``\n then denotes each token's own trailing local window, and no selected\n index can exceed that token's extent, so no masking pass is needed.\n Entries are clamped in-kernel to ``[0, max_k_tiles]`` (checking them on\n the host would sync), so an over-large count degrades to the full block\n range rather than reading out of bounds.\n\n The tensor form is supported only on SM120/SM121. On compute\n capability 10.0/10.3, pass a scalar or ``None``; a tensor is rejected\n before dispatch because that backend accepts only a scalar bound.\n output : torch.Tensor, optional\n Pre-allocated output tensor of shape\n ``(total_qo_len, num_qo_heads, topk)``, dtype int32. Allocated\n internally if not provided.\n force_begin_blocks : int\n Number of KV blocks at the beginning (sink tokens) to always include.\n force_end_blocks : int\n Number of KV blocks at the end (local window) to always include.\n\n Returns\n -------\n torch.Tensor\n Shape ``(total_qo_len, num_qo_heads, topk)``, dtype int32.\n Ascending KV-block indices; ``-1`` entries are tail-padded invalid\n slots.\n\n Notes\n -----\n When near-tied scores compete for the last slots, either block may be\n selected; exact indices may vary across problem sizes and releases, but\n the selected score values always match.\n \"\"\"\n if is_blackwell_msa_device(max_score.device):\n if isinstance(num_valid_pages, torch.Tensor):\n raise NotImplementedError(\n \"per-token tensor num_valid_pages is only supported on \"\n \"SM120/SM121; compute capability 10.0/10.3 requires a scalar\"\n )\n return blackwell_msa_topk_select(\n max_score,\n topk,\n num_valid_pages=num_valid_pages,\n output=output,\n force_begin_blocks=force_begin_blocks,\n force_end_blocks=force_end_blocks,\n )\n if not is_sm12x_supported(max_score.device):\n raise RuntimeError(\n \"msa_topk_select requires SM120 or SM121 (Blackwell) and CUDA >= 12.8\"\n )\n\n if max_score.dtype != torch.float32:\n raise ValueError(f\"max_score must be float32, got {max_score.dtype}\")\n if not max_score.is_contiguous():\n raise ValueError(\"max_score must be contiguous\")\n if max_score.ndim != 3:\n raise ValueError(\n f\"max_score must be 3D (num_qo_heads, max_k_tiles, total_qo_len), got {max_score.ndim}D\"\n )\n if topk != 16:\n raise ValueError(f\"topk must be 16, got {topk}\")\n\n from .cute_dsl.topk_select_countrank_sm12x import _MAX_BLOCKS\n\n num_qo_heads, max_k_tiles, total_qo_len = max_score.shape\n\n if num_valid_pages is None:\n num_valid_pages = max_k_tiles\n\n per_token_nvp = isinstance(num_valid_pages, torch.Tensor)\n\n if force_begin_blocks < 0 or force_end_blocks < 0:\n raise ValueError(\"force_begin_blocks / force_end_blocks must be >= 0\")\n if force_begin_blocks + force_end_blocks > topk:\n raise ValueError(\n f\"force_begin_blocks + force_end_blocks ({force_begin_blocks} + \"\n f\"{force_end_blocks}) must be <= topk ({topk})\"\n )\n\n if isinstance(num_valid_pages, torch.Tensor):\n if num_valid_pages.dtype != torch.int32 or num_valid_pages.ndim != 1:\n raise ValueError(\"num_valid_pages tensor must be 1D int32\")\n if num_valid_pages.numel() != total_qo_len:\n raise ValueError(\n f\"num_valid_pages tensor must have total_qo_len ({total_qo_len}) \"\n f\"entries, got {num_valid_pages.numel()}\"\n )\n if not num_valid_pages.is_contiguous():\n raise ValueError(\"num_valid_pages tensor must be contiguous\")\n if num_valid_pages.device != max_score.device:\n raise ValueError(\"num_valid_pages must be on max_score's device\")\n # Values stay on device (reading them would force a sync, which is\n # illegal under CUDA graph capture), so both the max_k_tiles bound and\n # the per-token forced-region fit are clamped in-kernel instead of\n # checked here. Unchecked, an out-of-range entry reads max_score out of\n # bounds and emits block indices the attend kernel cannot address --\n # reachable in practice, since callers derive the count and max_k_tiles\n # from different metadata.\n nvp_dev = num_valid_pages\n nvp_scalar = 0\n # Cannot dispatch on the runtime values without a sync, so bound by the\n # allocated tile count. Conservative: picks radix when max_k_tiles\n # exceeds the SMEM cap even if every token is actually shorter.\n small = int(max_k_tiles) <= _MAX_BLOCKS\n else:\n # Input guards (the radix kernel does not clamp internally): an\n # out-of-range num_valid_pages reads max_score out of bounds, and\n # oversized forced regions overrun the kernel's fixed forced-index\n # buffer or underflow to negative blocks.\n if not 0 < num_valid_pages <= max_k_tiles:\n raise ValueError(\n f\"num_valid_pages must be in (0, max_k_tiles={max_k_tiles}], \"\n f\"got {num_valid_pages}\"\n )\n if force_begin_blocks + force_end_blocks > num_valid_pages:\n raise ValueError(\n f\"force_begin_blocks + force_end_blocks ({force_begin_blocks} + \"\n f\"{force_end_blocks}) must be <= num_valid_pages ({num_valid_pages})\"\n )\n nvp_dev = _dummy_nvp(max_score.device.index)\n nvp_scalar = int(num_valid_pages)\n # Dispatch on the runtime valid-page count: the count-rank kernel only\n # ever touches blocks below num_valid_pages, regardless of the allocated\n # score dimension.\n small = nvp_scalar <= _MAX_BLOCKS\n\n if output is None:\n output = torch.empty(\n (total_qo_len, num_qo_heads, topk),\n dtype=torch.int32,\n device=max_score.device,\n )\n else:\n if output.shape != (total_qo_len, num_qo_heads, topk):\n raise ValueError(\n f\"output shape must be ({total_qo_len}, {num_qo_heads}, {topk}), \"\n f\"got {tuple(output.shape)}\"\n )\n if output.dtype != torch.int32:\n raise ValueError(f\"output must be int32, got {output.dtype}\")\n\n from .cute_dsl.topk_select_chunked_sm12x import (\n _CHUNK_BLOCKS,\n _MAX_CHUNK_BLOCKS,\n _TILED_MIN_QUERIES,\n _MAX_CHUNKED_SCRATCH_BYTES,\n _MAX_CHUNKS,\n _MIN_BLOCKS,\n _MIN_CHUNKS,\n )\n\n # topk_select_chunked_sm12x explains why chunked wins on both small and\n # full grids; per-token extents stay on the single-kernel paths.\n # Everything here is shape-constant, so CUDA-graph safe.\n if not per_token_nvp:\n rows = total_qo_len * num_qo_heads\n n_mid = nvp_scalar - force_begin_blocks - force_end_blocks\n chunked = _MIN_BLOCKS < n_mid <= _MAX_CHUNKS * _MAX_CHUNK_BLOCKS\n # Keyed on queries, not rows: the tiled kernel's lanes parallelize\n # over queries only, so a head-heavy grid with few queries would run\n # it with mostly idle lanes even though rows is large.\n tiled = total_qo_len > _TILED_MIN_QUERIES\n if chunked:\n num_chunks = max(_MIN_CHUNKS, min(_MAX_CHUNKS, -(-n_mid // _CHUNK_BLOCKS)))\n if rows * num_chunks * topk * 8 > _MAX_CHUNKED_SCRATCH_BYTES:\n chunked = False\n if chunked:\n chunk_len = -(-n_mid // num_chunks)\n # The partial kernels' SMEM staging has no in-kernel clamp.\n assert chunk_len <= _MAX_CHUNK_BLOCKS\n # One allocation for both candidate buffers keeps this hot path at\n # a single allocator call.\n cand = torch.empty(\n (2, total_qo_len, num_qo_heads, num_chunks * topk),\n dtype=torch.int32,\n device=max_score.device,\n )\n cand_key, cand_idx = cand[0], cand[1]\n _get_compiled_topk_chunked(topk, tiled)(\n max_score,\n cand_key,\n cand_idx,\n output,\n nvp_scalar,\n int(force_begin_blocks),\n int(force_end_blocks),\n num_chunks,\n chunk_len,\n int(total_qo_len),\n int(num_qo_heads),\n )\n return output\n\n _get_compiled_topk(topk, small, per_token_nvp)(\n max_score,\n output,\n nvp_dev,\n nvp_scalar,\n int(force_begin_blocks),\n int(force_end_blocks),\n int(total_qo_len),\n int(num_qo_heads),\n )\n\n return output\n"},"diff":{"kind":"string","value":"--- flashinfer/msa_ops/sparse_topk_select.py\n+++ flashinfer/msa_ops/sparse_topk_select.py\n@@ -20,6 +20,7 @@\n import torch\n \n from ..api_logging import flashinfer_api\n+from ..trace.templates.msa import msa_topk_select_trace\n from ..utils import is_sm12x_supported\n from ._blackwell_sm100 import blackwell_msa_topk_select, is_blackwell_msa_device\n \n@@ -29,6 +30,28 @@\n \"\"\"Signature filler for the scalar-``num_valid_pages`` path, which never\n reads it; cached so repeat calls do not launch a fill kernel.\"\"\"\n return torch.zeros(1, dtype=torch.int32, device=torch.device(\"cuda\", device_index))\n+\n+\n+def _compile_topk(kernel_obj, num_score_tensors: int, num_scalars: int):\n+ \"\"\"Compile plumbing shared by the chunked top-k variants. All tensor\n+ arguments are 3D and the scalar values are placeholders (the compiled\n+ kernels take them dynamically).\"\"\"\n+ import cutlass\n+ import cutlass.cute as cute\n+\n+ def fk(dtype):\n+ return cute.runtime.make_fake_compact_tensor(\n+ dtype,\n+ tuple(cute.sym_int() for _ in range(3)),\n+ stride_order=(2, 1, 0),\n+ assumed_align=4,\n+ )\n+\n+ args = [fk(cutlass.Float32)] # max_score (H, P, S)\n+ args += [fk(cutlass.Int32) for _ in range(num_score_tensors - 1)]\n+ args += [cutlass.Int32(1)] * num_scalars\n+ args.append(cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True))\n+ return cute.compile(kernel_obj, *args, options=\"--enable-tvm-ffi\")\n \n \n @functools.cache\n@@ -76,7 +99,18 @@\n return compiled\n \n \n-@flashinfer_api\n+@functools.cache\n+def _get_compiled_topk_chunked(topk: int, tiled: bool):\n+ \"\"\"Two-kernel (per-chunk rank + merge) variant; selections match the\n+ count-rank kernel exactly (same bit-key and tie order). ``tiled`` picks\n+ the full-grid partial kernel (coalesced q-tile staging) over the\n+ row-per-CTA one.\"\"\"\n+ from .cute_dsl.topk_select_chunked_sm12x import TopKSelectChunkedSm12x\n+\n+ return _compile_topk(TopKSelectChunkedSm12x(topk=topk, tiled=tiled), 4, 7)\n+\n+\n+@flashinfer_api(trace=msa_topk_select_trace)\n def msa_topk_select(\n max_score: torch.Tensor,\n topk: int,\n@@ -137,6 +171,12 @@\n Shape ``(total_qo_len, num_qo_heads, topk)``, dtype int32.\n Ascending KV-block indices; ``-1`` entries are tail-padded invalid\n slots.\n+\n+ Notes\n+ -----\n+ When near-tied scores compete for the last slots, either block may be\n+ selected; exact indices may vary across problem sizes and releases, but\n+ the selected score values always match.\n \"\"\"\n if is_blackwell_msa_device(max_score.device):\n if isinstance(num_valid_pages, torch.Tensor):\n@@ -247,6 +287,58 @@\n if output.dtype != torch.int32:\n raise ValueError(f\"output must be int32, got {output.dtype}\")\n \n+ from .cute_dsl.topk_select_chunked_sm12x import (\n+ _CHUNK_BLOCKS,\n+ _MAX_CHUNK_BLOCKS,\n+ _TILED_MIN_QUERIES,\n+ _MAX_CHUNKED_SCRATCH_BYTES,\n+ _MAX_CHUNKS,\n+ _MIN_BLOCKS,\n+ _MIN_CHUNKS,\n+ )\n+\n+ # topk_select_chunked_sm12x explains why chunked wins on both small and\n+ # full grids; per-token extents stay on the single-kernel paths.\n+ # Everything here is shape-constant, so CUDA-graph safe.\n+ if not per_token_nvp:\n+ rows = total_qo_len * num_qo_heads\n+ n_mid = nvp_scalar - force_begin_blocks - force_end_blocks\n+ chunked = _MIN_BLOCKS < n_mid <= _MAX_CHUNKS * _MAX_CHUNK_BLOCKS\n+ # Keyed on queries, not rows: the tiled kernel's lanes parallelize\n+ # over queries only, so a head-heavy grid with few queries would run\n+ # it with mostly idle lanes even though rows is large.\n+ tiled = total_qo_len > _TILED_MIN_QUERIES\n+ if chunked:\n+ num_chunks = max(_MIN_CHUNKS, min(_MAX_CHUNKS, -(-n_mid // _CHUNK_BLOCKS)))\n+ if rows * num_chunks * topk * 8 > _MAX_CHUNKED_SCRATCH_BYTES:\n+ chunked = False\n+ if chunked:\n+ chunk_len = -(-n_mid // num_chunks)\n+ # The partial kernels' SMEM staging has no in-kernel clamp.\n+ assert chunk_len <= _MAX_CHUNK_BLOCKS\n+ # One allocation for both candidate buffers keeps this hot path at\n+ # a single allocator call.\n+ cand = torch.empty(\n+ (2, total_qo_len, num_qo_heads, num_chunks * topk),\n+ dtype=torch.int32,\n+ device=max_score.device,\n+ )\n+ cand_key, cand_idx = cand[0], cand[1]\n+ _get_compiled_topk_chunked(topk, tiled)(\n+ max_score,\n+ cand_key,\n+ cand_idx,\n+ output,\n+ nvp_scalar,\n+ int(force_begin_blocks),\n+ int(force_end_blocks),\n+ num_chunks,\n+ chunk_len,\n+ int(total_qo_len),\n+ int(num_qo_heads),\n+ )\n+ return output\n+\n _get_compiled_topk(topk, small, per_token_nvp)(\n max_score,\n output,"},"lines_added":{"kind":"number","value":93,"string":"93"},"lines_removed":{"kind":"number","value":1,"string":"1"},"files_in_commit":{"kind":"number","value":7,"string":"7"},"models_mentioned":{"kind":"list like","value":["minimax"],"string":"[\n \"minimax\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["RTX5080","SM120","SM121"],"string":"[\n \"RTX5080\",\n \"SM120\",\n \"SM121\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":["2.2x","2.1x"],"string":"[\n \"2.2x\",\n \"2.1x\"\n]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cute_dsl kernel file from flashinfer (flashinfer/msa_ops/sparse_topk_select.py).\n\nGoal: perf(msa): chunked top-k and in-kernel causal offsets for the SM12x indexer\nTarget hardware: RTX5080, SM120, SM121\nTarget models: minimax\n\nCurrent file:\n```python\n\"\"\"\nCopyright (c) 2026 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\"\"\"\n\nimport functools\nfrom typing import Optional, Union\n\nimport torch\n\nfrom ..api_logging import flashinfer_api\nfrom ..utils import is_sm12x_supported\nfrom ._blackwell_sm100 import blackwell_msa_topk_select, is_blackwell_msa_device\n\n\n@functools.cache\ndef _dummy_nvp(device_index: int) -> torch.Tensor:\n \"\"\"Signature filler for the scalar-``num_valid_pages`` path, which never\n reads it; cached so repeat calls do not launch a fill kernel.\"\"\"\n return torch.zeros(1, dtype=torch.int32, device=torch.device(\"cuda\", device_index))\n\n\n@functools.cache\ndef _get_compiled_topk(topk: int, small: bool, per_token_nvp: bool):\n \"\"\"``small`` picks the O(N^2) count-rank kernel, else the radix kernel; the\n two give identical selections only on distinct-score inputs (ties may differ).\n\n No default on ``per_token_nvp``: it keys the cache, and a call that omitted\n it would compile a second copy of an identical kernel.\"\"\"\n import cutlass\n import cutlass.cute as cute\n\n if small:\n from .cute_dsl.topk_select_countrank_sm12x import (\n TopKSelectCountRankSm12x as _TopKKernel,\n )\n else:\n from .cute_dsl.topk_select_radix_sm12x import ( # type: ignore[assignment,no-redef]\n TopKSelectRadixSm12x as _TopKKernel,\n )\n kernel_obj = _TopKKernel(topk=topk, per_token_nvp=per_token_nvp)\n\n def fk(dtype, ndim, align):\n return cute.runtime.make_fake_compact_tensor(\n dtype,\n tuple(cute.sym_int() for _ in range(ndim)),\n stride_order=tuple(reversed(range(ndim))),\n assumed_align=align,\n )\n\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n compiled = cute.compile(\n kernel_obj,\n fk(cutlass.Float32, 3, 4), # max_score (H, P, S)\n fk(cutlass.Int32, 3, 4), # out (S, H, topk)\n fk(cutlass.Int32, 1, 4), # num_valid_pages tensor (S,)\n cutlass.Int32(1), # num_valid_pages scalar\n cutlass.Int32(0), # force_begin\n cutlass.Int32(0), # force_end\n cutlass.Int32(1), # total_qo_len\n cutlass.Int32(1), # num_qo_heads\n stream_fake,\n options=\"--enable-tvm-ffi\",\n )\n return compiled\n\n\n@flashinfer_api\ndef msa_topk_select(\n max_score: torch.Tensor,\n topk: int,\n num_valid_pages: Optional[Union[int, torch.Tensor]] = None,\n output: Optional[torch.Tensor] = None,\n force_begin_blocks: int = 0,\n force_end_blocks: int = 0,\n) -> torch.Tensor:\n \"\"\"Select the top-K KV blocks per query token based on attention scores.\n\n Implements the block-scoring pass of Minimax Sparse Attention: given the\n per-block maximum attention scores from a cheap proxy prefill, selects the\n ``topk`` most important KV blocks for each (query token, head) pair and\n returns their sorted indices. Dispatch supports compute capability\n 10.0/10.3 and SM120/SM121.\n\n Parameters\n ----------\n max_score : torch.Tensor\n Shape ``(num_qo_heads, max_k_tiles, total_qo_len)``, dtype float32.\n Per-KV-block maximum attention scores produced by the proxy prefill\n pass. Entries for invalid tiles (beyond the actual KV length) must be\n set to ``-inf`` by the caller.\n topk : int\n Number of KV blocks to select per (query token, head). Must be 16.\n num_valid_pages : int or torch.Tensor, optional\n Actual number of valid KV pages (``<= max_k_tiles``). Indices\n ``>= num_valid_pages`` are replaced with -1 and sorted to the tail.\n Defaults to ``max_k_tiles`` (disables clamping).\n\n May instead be an int32 tensor of shape ``(total_qo_len,)`` giving each\n query token its own valid-page count. Callers whose tokens have\n differing causal KV extents (decode batches, chunked prefill) want this:\n with a batch-wide scalar the only way to recover per-token semantics is\n to post-process the output on the host side, which costs several extra\n kernel launches per call and is easy to get wrong. ``force_end_blocks``\n then denotes each token's own trailing local window, and no selected\n index can exceed that token's extent, so no masking pass is needed.\n Entries are clamped in-kernel to ``[0, max_k_tiles]`` (checking them on\n the host would sync), so an over-large count degrades to the full block\n range rather than reading out of bounds.\n\n The tensor form is supported only on SM120/SM121. On compute\n capability 10.0/10.3, pass a scalar or ``None``; a tensor is rejected\n before dispatch because that backend accepts only a scalar bound.\n output : torch.Tensor, optional\n Pre-allocated output tensor of shape\n ``(total_qo_len, num_qo_heads, topk)``, dtype int32. Allocated\n internally if not provided.\n force_begin_blocks : int\n Number of KV blocks at the beginning (sink tokens) to always include.\n force_end_blocks : int\n Number of KV blocks at the end (local window) to always include.\n\n Returns\n -------\n torch.Tensor\n Shape ``(total_qo_len, num_qo_heads, topk)``, dtype int32.\n Ascending KV-block indices; ``-1`` entries are tail-padded invalid\n slots.\n \"\"\"\n if is_blackwell_msa_device(max_score.device):\n if isinstance(num_valid_pages, torch.Tensor):\n raise NotImplementedError(\n \"per-token tensor num_valid_pages is only supported on \"\n \"SM120/SM121; compute capability 10.0/10.3 requires a scalar\"\n )\n return blackwell_msa_topk_select(\n max_score,\n topk,\n num_valid_pages=num_valid_pages,\n output=output,\n force_begin_blocks=force_begin_blocks,\n force_end_blocks=force_end_blocks,\n )\n if not is_sm12x_supported(max_score.device):\n raise RuntimeError(\n \"msa_topk_select requires SM120 or SM121 (Blackwell) and CUDA >= 12.8\"\n )\n\n if max_score.dtype != torch.float32:\n raise ValueError(f\"max_score must be float32, got {max_score.dtype}\")\n if not max_score.is_contiguous():\n raise ValueError(\"max_score must be contiguous\")\n if max_score.ndim != 3:\n raise ValueError(\n f\"max_score must be 3D (num_qo_heads, max_k_tiles, total_qo_len), got {max_score.ndim}D\"\n )\n if topk != 16:\n raise ValueError(f\"topk must be 16, got {topk}\")\n\n from .cute_dsl.topk_select_countrank_sm12x import _MAX_BLOCKS\n\n num_qo_heads, max_k_tiles, total_qo_len = max_score.shape\n\n if num_valid_pages is None:\n num_valid_pages = max_k_tiles\n\n per_token_nvp = isinstance(num_valid_pages, torch.Tensor)\n\n if force_begin_blocks < 0 or force_end_blocks < 0:\n raise ValueError(\"force_begin_blocks / force_end_blocks must be >= 0\")\n if force_begin_blocks + force_end_blocks > topk:\n raise ValueError(\n f\"force_begin_blocks + force_end_blocks ({force_begin_blocks} + \"\n f\"{force_end_blocks}) must be <= topk ({topk})\"\n )\n\n if isinstance(num_valid_pages, torch.Tensor):\n if num_valid_pages.dtype != torch.int32 or num_valid_pages.ndim != 1:\n raise ValueError(\"num_valid_pages tensor must be 1D int32\")\n if num_valid_pages.numel() != total_qo_len:\n raise ValueError(\n f\"num_valid_pages tensor must have total_qo_len ({total_qo_len}) \"\n f\"entries, got {num_valid_pages.numel()}\"\n )\n if not num_valid_pages.is_contiguous():\n raise ValueError(\"num_valid_pages tensor must be contiguous\")\n if num_valid_pages.device != max_score.device:\n raise ValueError(\"num_valid_pages must be on max_score's device\")\n # Values stay on device (reading them would force a sync, which is\n # illegal under CUDA graph capture), so both the max_k_tiles bound and\n # the per-token forced-region fit are clamped in-kernel instead of\n # checked here. Unchecked, an out-of-range entry reads max_score out of\n # bounds and emits block indices the attend kernel cannot address --\n # reachable in practice, since callers derive the count and max_k_tiles\n # from different metadata.\n nvp_dev = num_valid_pages\n nvp_scalar = 0\n # Cannot dispatch on the runtime values without a sync, so bound by the\n # allocated tile count. Conservative: picks radix when max_k_tiles\n # exceeds the SMEM cap even if every token is actually shorter.\n small = int(max_k_tiles) <= _MAX_BLOCKS\n else:\n # Input guards (the radix kernel does not clamp internally): an\n # out-of-range num_valid_pages reads max_score out of bounds, and\n # oversized forced regions overrun the kernel's fixed forced-index\n # buffer or underflow to negative blocks.\n if not 0 < num_valid_pages <= max_k_tiles:\n raise ValueError(\n f\"num_valid_pages must be in (0, max_k_tiles={max_k_tiles}], \"\n f\"got {num_valid_pages}\"\n )\n if force_begin_blocks + force_end_blocks > num_valid_pages:\n raise ValueError(\n f\"force_begin_blocks + force_end_blocks ({force_begin_blocks} + \"\n f\"{force_end_blocks}) must be <= num_valid_pages ({num_valid_pages})\"\n )\n nvp_dev = _dummy_nvp(max_score.device.index)\n nvp_scalar = int(num_valid_pages)\n # Dispatch on the runtime valid-page count: the count-rank kernel only\n # ever touches blocks below num_valid_pages, regardless of the allocated\n # score dimension.\n small = nvp_scalar <= _MAX_BLOCKS\n\n if output is None:\n output = torch.empty(\n (total_qo_len, num_qo_heads, topk),\n dtype=torch.int32,\n device=max_score.device,\n )\n else:\n if output.shape != (total_qo_len, num_qo_heads, topk):\n raise ValueError(\n f\"output shape must be ({total_qo_len}, {num_qo_heads}, {topk}), \"\n f\"got {tuple(output.shape)}\"\n )\n if output.dtype != torch.int32:\n raise ValueError(f\"output must be int32, got {output.dtype}\")\n\n _get_compiled_topk(topk, small, per_token_nvp)(\n max_score,\n output,\n nvp_dev,\n nvp_scalar,\n int(force_begin_blocks),\n int(force_end_blocks),\n int(total_qo_len),\n int(num_qo_heads),\n )\n\n return output\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## 📌 Description\n\nFollow-up to #3655, which enabled MiniMax Sparse Attention (MSA) on SM120/SM121. The indexer (proxy score + top-k, the two ops that pick each query's KV blocks) stayed behind vLLM in a few regimes there. All of the gaps traced to `msa_topk_select` and its wrapper rather than to the proxy kernel:\n\n- At decode with small batches, the top-k launches one CTA per (query, head) row, which is 4 CTAs at batch 1, leaving the GPU nearly idle. At 32k context those rows also fall into the radix kernel, which costs about as much as the proxy itself.\n- At long-sequence prefill, the top-k reads scores with strided accesses, and the radix kernel re-reads them once per digit pass.\n- The packed decode wrappers built the causal-offset tensor with three small torch kernels per call, about as costly as the top-k itself at short sequence lengths.\n\nChanges:\n\n- A new chunked top-k. A partial kernel ranks 64-block chunks independently, one CTA per (query, head, chunk), and a merge kernel then re-ranks the surviving candidates for each row. Both use the same ordering as the existing top-k kernels, so selections are identical. The merge launches with PDL to overlap with the partial kernel.\n- A q-tiled variant of the partial kernel for large grids. It covers 32 queries per CTA so that every score load is one coalesced line, which extends the chunked path to prefill under a 128 MB scratch cap; larger grids keep the radix kernel.\n- The packed decode kernels (bf16 and NVFP4) now compute the causal offset in-kernel when `q_offset` is not given, removing the wrapper's torch launches from the decode path.\n\nThe kernel choice depends only on shapes, so it is CUDA-graph safe; a new test covers graph capture on the chunked path.\n\n### Performance\n\nMeasured as in #3655: median GPU time over CUDA-graph replays (CUPTI), with the L2 cache flushed between replays so one replay cannot reuse the previous replay's data. The baseline is vLLM's MiniMax-M3 Triton MSA kernels on the same GPUs and shapes. Each cell is an RTX PRO 6000 Server / RTX 5080 / GB10 triple, and speedup = vLLM time / FlashInfer time, so higher is better. \"Before\" is main as of #3655. The MTP columns run the same call with 4 draft tokens per request, as in a speculative-decoding verify step.\n\nIndexer decode (proxy + top-k), batch 1:\n\n| S | before | after | before (4-token MTP) | after (4-token MTP) |\n|--:|:--:|:--:|:--:|:--:|\n| 2k | 1.31 / 1.43 / 1.33 | 1.31 / 1.42 / 1.38 | 0.73 / 0.71 / 0.91 | 1.20 / 1.12 / 1.29 |\n| 4k | 1.40 / 1.39 / 1.21 | 1.43 / 1.38 / 1.24 | 0.87 / 0.86 / 1.03 | 1.39 / 1.29 / 1.33 |\n| 8k | 1.18 / 1.10 / 1.08 | 1.28 / 1.22 / 1.10 | 0.82 / 0.90 / 0.95 | 1.26 / 1.34 / 1.11 |\n| 16k | 1.18 / 1.09 / 1.02 | 1.25 / 1.17 / 1.09 | 0.95 / 0.85 / 0.97 | 1.34 / 1.19 / 1.09 |\n| 32k | 0.90 / 0.98 / 0.98 | 1.08 / 1.11 / 1.03 | 0.95 / 0.94 / 0.96 | 1.36 / 1.30 / 1.07 |\n\nIndexer prefill, batch 1 (the 2k and 4k rows keep the old kernels and are unchanged within noise):\n\n| S | before | after |\n|--:|:--:|:--:|\n| 8k | 1.04 / 1.14 / 1.01 | 1.06 / 1.18 / 1.02 |\n| 16k | 1.04 / 1.18 / 1.02 | 1.19 / 1.25 / 1.16 |\n| 32k | 0.90 / 1.08 / 0.89 | 1.16 / 1.28 / 1.19 |\n\nMeasured against the kernels this PR replaces:\n\n- The new top-k alone is 1.4-2.2x faster at decode (batch 1 to 128) and 1.2-2.1x faster at 8k-32k prefill.\n- The proxy kernel is untouched, so shapes where it dominates do not move: at batch 128 the end-to-end ratio stays at 1.00-1.03 vs vLLM.\n- The optional NVFP4 decode path also speeds up because its wrapper sheds the same torch launches.\n\n## 🔍 Related Issues\n\nFollow-up to #3655.\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\nAll 155 tests in `tests/msa_ops/` pass on an RTX 5080 (SM120) after rebasing onto current main. This PR adds tests for:\n\n- the dispatch boundaries between the three top-k kernels\n- selection identity between the chunked and existing kernels, including NaN scores, forced blocks, and the ragged q-tile tail\n- CUDA-graph capture on the chunked path\n- explicit `q_offset` on both packed decode kernels\n\nIt also moves the paged-varlen fp4 test's reference to float32: the kernel's fp4 x scale products never round through bf16, so the bf16-rounded reference misses the 5e-2 tolerance on causal-boundary blocks (16 of 40 seeds on an RTX 5080, including the checked-in seed). The same treatment the other fp4 tests already use.\n\n`compute-sanitizer` racecheck and memcheck are clean on the new kernels.\n\n## Reviewer Notes\n\n- Per-token `num_valid_pages` calls (added by #4324) stay on the single-kernel paths: the chunked kernels' geometry is host-derived from the scalar count.\n- Selection identity across the top-k kernels (same bit-key and tie order) is pinned by tests.\n- The row-per-CTA and q-tiled partial kernels keep separate bodies on purpose: the row-per-CTA binary is production-validated.\n- Deferred for the same reason: skipping the redundant sentinel prefill of the candidate scratch, and sharing the forced-slot fill across the three kernels.\n\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n- **New Features**\n - Added chunked top-k selection for large candidate sets, including tiled execution and forced-page handling.\n - Added optional default query-offset handling for packed decode with right-aligned causal masking.\n - Added tracing support for MSA top-k selection.\n\n- **Bug Fixes**\n - Improved causal masking consistency across packed decode formats.\n - Preserved sentinel results and selected-score correctness during top-k selection.\n\n- **Tests**\n - Expanded coverage for large contexts, query offsets, chunked selection, tracing, and CUDA graph execution.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000 Server\", \"model\": null, \"shape\": \"S=2k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.31, \"optimized\": 1.31, \"stated_speedup\": null, \"speedup\": 1.0}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"S=2k\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 1.43, \"optimized\": 1.42, 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null, \"shape\": null, \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 2.1, \"speedup\": 2.1}]"},"kernel_speedup":{"kind":"number","value":0.8972,"string":"0.8972"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1078,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"75e834d633bc87267accc6e3f9749d18e459566a"},"date":{"kind":"string","value":"2026-08-25T09:23:27-07:00"},"pr_number":{"kind":"number","value":4708,"string":"4,708"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/4708"},"title":{"kind":"string","value":"(perf) add fused_GDN_step support for Qwen 3.6 35B A3B on sm120 (#4708)"},"message":{"kind":"string","value":"(perf) add fused_GDN_step support for Qwen 3.6 35B A3B on sm120 (#4708)\n\n<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\nFollow up with #4481 \n- Adds Qwen3.6-35B-A3B support at batches 1/2/4 for both CUDA and\nCuTe-DSL implementations.\n- Generates one geometry-specific CUDA JIT module using FI_GDN_* compile\ndefinitions.\n - Passes geometry as cutlass.Constexpr to CuTe-DSL kernels.\n- Includes geometry in compiled-kernel, workspace, and CUDA Graph\nreadiness cache keys.\n - Adds compile-time/static geometry checks to prevent invalid tiling.\n- Adds registry_geometries() for introspection and potential AOT\niteration.\n- Expands tests across both geometries, both implementations, registry\nshape, invalid geometry rejection, JIT module uniqueness, and numerical\nequivalence.\n- Updates documentation for the multi-geometry registry and JIT/AOT\nbehavior.\n- Removes the hypothetical FLASHINFER_QWEN_GDN_FUSED_DECODE_DISABLE test\nreference.\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [ ] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [ ] I have installed the hooks with `pre-commit install`.\n- [ ] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the\npre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [ ] Tests have been added or updated as needed.\n- [ ] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc.\n-->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n* **New Features**\n* Added fused GDN decode support for an additional model configuration,\nincluding its supported decode batch sizes.\n* Kernel compilation, dispatch, caching, and CUDA graph capture now\naccount for each layer geometry, batch size, scale, and layout.\n* Added validation for supported dimensions and tiling relationships,\nwith fallback behavior for unsupported geometries.\n * Expanded supported workloads across both shipped geometries.\n\n* **Documentation**\n* Updated support, registry, CUDA graph, build, and model-integration\nguidance with expanded geometry requirements and configurations.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->"},"path":{"kind":"string","value":"flashinfer/gdn_kernels/experimental/kernel/gdn_fused_decode_cutedsl_sm120_pdl.py"},"language":{"kind":"string","value":"cute_dsl"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"\"\"\"\nCopyright (c) 2026 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nFused GDN Decode Step - two-launch CuTe-DSL impl with PDL (SM120)\n=================================================================\n\nHost and kernel side of the ``cutedsl_sm120_pdl`` registry impl: a\ntwo-launch CuTe-DSL implementation of the fused GDN decode step, compiled\nper (batch, scale, conv-state layout) and launched on the current torch\nstream. The conv-state pool arrives as a logical [P, QKV_DIM,\nCONV_STATE_LEN] view of either a transposed SD pool (vLLM default) or a\nDS-dense pool; indexing is stride-generic, so the layouts differ only in\nwhich mode carries the static unit stride. The first launch\nfuses the depthwise conv1d update with a heavily K-split b/a GEMV (fp32\npartials accumulated with device-scope atomics); the second applies the gated\ndelta rule. Both launches use programmatic dependent launch (PDL); the\nwait/trigger contract that makes that safe is stated in full above\n:func:`pre_kernel` and pinned by ``tests/gdn/test_fused_decode.py``.\n\nImplements the impl-module interface documented in ../README.md.\nCompilation is lazy: the first eager :func:`execute` of a (batch, scale,\nconv-state layout) variant compiles it and allocates the per-(batch,\ndevice) workspace; once warm, calls are capture-safe (kernel launches plus\none stream memset). Consumed by\n:mod:`flashinfer.gdn_kernels.experimental.gdn_fused_decode_specialized`;\nimport errors are tolerated there (the cutlass DSL dependency stays\noptional).\n\"\"\"\n\nfrom typing import Any\n\nimport torch\nimport cutlass\nimport cutlass.cute as cute\nimport cuda.bindings.driver as cuda_driver\nfrom cutlass.cute.runtime import from_dlpack\n\nfrom ....cuda_utils import checkCudaErrors\nfrom ._stream_order import order_after_previous_stream\n\nHIDDEN = 5120\nN_BA = 96\nQKV_DIM = 10240\nH_Q = 16\nHV = 48\nD = 128\nCONV_WIDTH = 4\nCONV_STATE_LEN = 3\nGQA = HV // H_Q # 3\nRPB = 8 # v-rows per block in delta kernel (8 warps = 256 thr)\nNRB = D // RPB # row-blocks per head = 16\nKS = 512 # K-split factor for the GEMV (atomic fp32 partials)\nKCHUNK = HIDDEN // KS # 10\n\nNCONV = QKV_DIM // 256 # conv tiles per batch = 40\n\n\n# ---------------------------------------------------------------------------\n# PDL contract for this op -- read this before moving either griddepcontrol.\n# ---------------------------------------------------------------------------\n# Both launches carry ``use_pdl=True``\n# (CU_LAUNCH_ATTRIBUTE_PROGRAMMATIC_STREAM_SERIALIZATION), which tells the\n# driver it \"is safe to launch the secondary kernel early and not wait on the\n# completion and memory flush of the primary before launching the secondary\"\n# (CUDA programming guide, Programmatic Dependent Launch). Two DIFFERENT\n# hardware events then keep that safe, and conflating them is the way this\n# code goes wrong:\n#\n# griddepcontrol.launch_dependents -- a SCHEDULING gate only. PTX: the\n# designated dependents \"can be scheduled as soon as all other CTAs in\n# the grid issue the same instruction or have completed\". It publishes\n# nothing, orders nothing, and is not what a dependent's wait observes.\n# griddepcontrol.wait -- the VISIBILITY barrier. PTX: the thread waits\n# \"until all prerequisite grids in flight have completed and all the\n# memory operations from the prerequisite grids are performed and made\n# visible to the current grid\", i.e. until the predecessor grid's\n# grid-ending membar has drained. This, and only this, makes a read of\n# a predecessor's output legal.\n#\n# Who waits, who triggers, and what each ordering protects:\n#\n# pre_kernel WAITS FIRST, unconditionally, before its first global load and\n# before the conv/GEMV block split so that every block reaches it.\n# Everything it loads is produced by a stream predecessor -- mixed_qkv\n# and hidden by this layer's projections, state_indices by the caller's\n# metadata prep, conv_state by an earlier decode step, and ``part`` by\n# the cuMemsetD32Async this launch is queued behind. The launch\n# attribute above explicitly releases the driver from waiting on those,\n# so without this wait the op's correctness would rest on whether some\n# unrelated upstream kernel happens to fire a trigger -- a property this\n# op cannot see and must not depend on.\n# pre_kernel THEN TRIGGERS, in the same unconditional prologue. Order\n# matters and is not cosmetic: the trigger is what places delta_kernel's\n# CTAs on the SMs, and delta_kernel reads ssm_state BEFORE its own wait.\n# Triggering ahead of pre_kernel's wait would schedule delta while\n# pre_kernel is itself still unordered against its predecessors, and\n# delta's pre-wait prefetch would inherit exactly that -- no ordering\n# against whoever last wrote ssm_state/state_indices. Waiting first is\n# what hands the dependent an already-ordered state.\n# pre_kernel triggers HERE rather than after its stores on purpose. The\n# trigger does not publish qkv_act/part and is not what releases\n# delta_kernel's wait; delta's wait does not return until pre_kernel's\n# whole grid has completed and flushed, which covers every store in this\n# kernel wherever it sits. Firing at entry is what buys the overlap the\n# impl exists for (upstream's gdn_decode_bf16_wy_ucache_flush.py fires at\n# entry for the same reason). What it does cost is SM competition:\n# delta's CTAs are resident and parked on their wait while pre_kernel\n# runs. That trade is measured, not assumed -- see ../README.md.\n# delta_kernel WAITS in both arms of its padded-row branch, after the\n# ssm_state prefetch and before the first read of qkv_act/part. That\n# wait is the ordering that protects the conv output and the GEMV\n# partials.\n# delta_kernel does NOT trigger, so nothing downstream is scheduled early on\n# its account and its ssm_state/output stores need no further signal\n# here: a successor is scheduled at this grid's completion. Adding a\n# trigger to delta_kernel would be a performance change that also\n# obliges every PDL successor to wait -- do not add one without the\n# matching wait on the other side.\n#\n# Pinned by ``test_pdl_kernels_wait_before_their_first_launch_dependents`` and\n# ``test_every_pdl_kernel_waits_on_all_paths`` in tests/gdn/test_fused_decode.py.\n@cute.kernel\ndef pre_kernel(\n mixed_qkv: cute.Tensor, # [B, QKV_DIM] bf16\n conv_weight: cute.Tensor, # [QKV_DIM, CONV_WIDTH] bf16\n conv_bias: cute.Tensor, # [QKV_DIM] bf16\n conv_state: cute.Tensor, # [P, QKV_DIM, CONV_STATE_LEN] bf16 (in-place)\n state_indices: cute.Tensor, # [B] int32\n qkv_act: cute.Tensor, # [B, QKV_DIM] bf16 scratch\n hidden: cute.Tensor, # [B, HIDDEN] bf16\n w_ba: cute.Tensor, # [HIDDEN, N_BA] bf16\n part: cute.Tensor, # [B, N_BA] f32, zeroed before launch\n Bc: cutlass.Constexpr,\n):\n \"\"\"First of the two launches: conv1d state update and the b/a GEMV.\n\n One grid does both, since neither depends on the other: blocks\n ``[0, B*NCONV)`` shift the conv-state rows, append the new input and write\n the silu-activated conv output to ``qkv_act``; the remaining blocks\n accumulate K-split partials of ``hidden @ w_ba`` into ``part`` with\n gpu-scope atomics (hence the memset of ``part`` before the launch). It\n waits on its own stream predecessors and then signals PDL launch\n dependents up front, so ``delta_kernel``'s ``ssm_state`` prefetch overlaps\n this entire body -- see the PDL contract block above.\n \"\"\"\n # Combined conv + K-split GEMV in one launch. Blocks [0, B*NCONV) do conv;\n # blocks [B*NCONV, ...) accumulate GEMV partials with gpu-scope atomics.\n #\n # PDL prologue, above the block split so EVERY block runs both halves.\n # (1) Wait: this grid is launched with programmatic stream serialization,\n # so it may already be running while its predecessors are still draining.\n # Every global load below -- state_indices, conv_state, mixed_qkv, hidden,\n # the weights, and the atomics into the freshly memset `part` -- reads what\n # those predecessors produced, so this is the barrier that makes them\n # legal, not an optimization.\n cute.arch.griddepcontrol_wait()\n # (2) Only then release delta_kernel onto the SMs, so its long-latency\n # ssm_state prefetch overlaps this whole body. Never before the wait:\n # delta reads global memory before its own wait and would inherit this\n # grid's unordered state. This does not publish anything -- delta's wait\n # covers pre_kernel's stores wherever they sit.\n cute.arch.griddepcontrol_launch_dependents()\n\n tidx, _, _ = cute.arch.thread_idx()\n bidx, _, _ = cute.arch.block_idx()\n\n if bidx < Bc * NCONV:\n b_idx = bidx // NCONV\n tile = bidx % NCONV\n c = tile * 256 + tidx\n pp = cutlass.Int32(state_indices[b_idx])\n # A negative slot index (vLLM's PAD_SLOT_ID = -1) marks a padded batch\n # row -- what a CUDA-graph replay carries between the live request\n # count and the captured batch size. It owns no conv-state row, so\n # neither read nor write one for it; ``delta_kernel`` skips the same\n # row and zeroes its output. The predicate depends only on ``bidx``,\n # so it is block-uniform: one taken branch per block, not divergence.\n # ``qkv_act`` is left untouched for such a row -- it is per-call\n # scratch that only the skipped delta blocks would read.\n if pp >= 0:\n st0_bf = conv_state[pp, c, 0]\n st1_bf = conv_state[pp, c, 1]\n st2_bf = conv_state[pp, c, 2]\n st0 = st0_bf.to(cutlass.Float32)\n st1 = st1_bf.to(cutlass.Float32)\n st2 = st2_bf.to(cutlass.Float32)\n xbf = mixed_qkv[b_idx, c]\n xx = xbf.to(cutlass.Float32)\n w0 = conv_weight[c, 0].to(cutlass.Float32)\n w1 = conv_weight[c, 1].to(cutlass.Float32)\n w2 = conv_weight[c, 2].to(cutlass.Float32)\n w3 = conv_weight[c, 3].to(cutlass.Float32)\n bb = conv_bias[c].to(cutlass.Float32)\n y = cutlass.Float32(st0 * w0 + st1 * w1 + st2 * w2 + xx * w3 + bb)\n ey = cute.math.exp(cutlass.Float32(-y), fastmath=False)\n yv = cutlass.Float32(y / cutlass.Float32(cutlass.Float32(1.0) + ey))\n qkv_act[b_idx, c] = yv.to(cutlass.BFloat16)\n conv_state[pp, c, 0] = st1_bf\n conv_state[pp, c, 1] = st2_bf\n conv_state[pp, c, 2] = xbf\n else:\n g = bidx - Bc * NCONV\n b_idx = g // KS\n ks = g % KS\n n = tidx\n if n < N_BA:\n base = ks * KCHUNK\n acc = cutlass.Float32(0.0)\n for i in cutlass.range_constexpr(KCHUNK):\n gi = base + i\n hv = hidden[b_idx, gi].to(cutlass.Float32)\n acc = acc + hv * w_ba[gi, n].to(cutlass.Float32)\n cute.arch.atomic_add(part.iterator + (b_idx * N_BA + n), acc, scope=\"gpu\")\n\n\n@cute.kernel\ndef delta_kernel(\n qkv_act: cute.Tensor, # [B, QKV_DIM] bf16\n part: cute.Tensor, # [B, N_BA] f32\n A_log: cute.Tensor, # [HV] f32\n dt_bias: cute.Tensor, # [HV] bf16\n ssm_state: cute.Tensor, # [P, HV, D, D] f32 (in-place)\n state_indices: cute.Tensor, # [B] int32\n output: cute.Tensor, # [B, 1, HV, D] bf16\n scale: cutlass.Constexpr,\n):\n \"\"\"Second launch: gates, qk-L2-norm and the gated delta-rule update.\n\n One warp owns one ``ssm_state`` row: it prefetches the row before waiting\n on PDL (``pre_kernel`` never touches ``ssm_state``, so the long-latency\n fp32 loads overlap the whole first kernel), reduces the b/a GEMV partials\n into the beta and decay gates, and writes the updated row back in place\n plus this row's slice of the attention output.\n \"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n bidx, _, _ = cute.arch.block_idx()\n hh = bidx // NRB # global head index (b_idx*HV + h)\n rb = bidx % NRB # row-block within head\n b_idx = hh // HV\n h = hh % HV\n qhd = h // GQA\n warp = tidx // 32\n lane = tidx % 32\n v = rb * RPB + warp # ssm row index this warp owns\n\n # Second global read issued before this kernel's PDL wait (with the\n # ssm_state prefetch below). pre_kernel does not write state_indices;\n # ordering against whoever did is inherited from pre_kernel waiting before\n # it triggers -- see the PDL contract block at the top of this file.\n pp = cutlass.Int32(state_indices[b_idx])\n\n # A negative slot index (vLLM's PAD_SLOT_ID = -1) marks a padded batch\n # row: it owns no pool slot, so neither state pool may be read or written\n # for it and its output row is zero -- the same contract the fp32 path of\n # gated_delta_rule_decode_pretranspose already documents. The predicate\n # depends only on bidx, so it is block-uniform: one taken branch per\n # block, and the warp-wide shuffles below are never reached under a\n # partial mask. Both arms wait on PDL: the padded arm reads nothing\n # pre_kernel wrote and would be correct without it, but keeping the wait\n # uniform across blocks keeps the launch's dependency semantics simple.\n if pp >= 0:\n # fp32 state loads issued before the PDL wait: pre_kernel never writes\n # ssm_state, so these long-latency loads overlap its whole body. What\n # orders them against the PREVIOUS step's writer of ssm_state is\n # pre_kernel waiting before it triggers: this grid cannot be scheduled\n # until pre_kernel has released it, and pre_kernel only releases after\n # its own wait has drained the predecessors. Keep that order there.\n k0 = lane\n k1 = lane + 32\n k2 = lane + 64\n k3 = lane + 96\n sv0 = ssm_state[pp, h, v, k0]\n sv1 = ssm_state[pp, h, v, k1]\n sv2 = ssm_state[pp, h, v, k2]\n sv3 = ssm_state[pp, h, v, k3]\n\n cute.arch.griddepcontrol_wait()\n\n qbase = qhd * D\n kbase = H_Q * D + qhd * D\n q0 = qkv_act[b_idx, qbase + k0].to(cutlass.Float32)\n q1 = qkv_act[b_idx, qbase + k1].to(cutlass.Float32)\n q2 = qkv_act[b_idx, qbase + k2].to(cutlass.Float32)\n q3 = qkv_act[b_idx, qbase + k3].to(cutlass.Float32)\n kk0 = qkv_act[b_idx, kbase + k0].to(cutlass.Float32)\n kk1 = qkv_act[b_idx, kbase + k1].to(cutlass.Float32)\n kk2 = qkv_act[b_idx, kbase + k2].to(cutlass.Float32)\n kk3 = qkv_act[b_idx, kbase + k3].to(cutlass.Float32)\n vvv = qkv_act[b_idx, 2 * H_Q * D + h * D + v].to(cutlass.Float32)\n\n # Redundant per-thread gate computation (no smem/sync needed). The fp32\n # gate sums round through bf16 to match the composable path's GEMV output\n # dtype before the sigmoid/softplus gates.\n b_sum = part[b_idx, h]\n a_sum = part[b_idx, HV + h]\n b_bf = b_sum.to(cutlass.BFloat16).to(cutlass.Float32)\n a_bf = a_sum.to(cutlass.BFloat16).to(cutlass.Float32)\n eb = cute.math.exp(cutlass.Float32(-b_bf), fastmath=False)\n beta = cutlass.Float32(1.0) / cutlass.Float32(cutlass.Float32(1.0) + eb)\n dtb = dt_bias[h].to(cutlass.Float32)\n x = cutlass.Float32(a_bf + dtb)\n # softplus via the overflow-free identity\n # softplus(x) = max(x, 0) + log(1 + exp(-|x|)),\n # branch-free. The naive log(1 + exp(x)) sends exp(x) to +inf for\n # x > ~88.7 in fp32, which collapses the decay gate to exactly 0 instead\n # of exp(-exp(A_log) * x) -- a silently wrong gate whenever exp(A_log) is\n # small enough for the true gate to stay O(1). The identity agrees with\n # torch.nn.functional.softplus (threshold=20, i.e. the composable path)\n # and with the CUDA impl's `x > 20 ? x : log1p(exp(x))` to fp32 rounding\n # over the whole range: worst case 1e-6 on the resulting gate, three\n # orders below the bf16 tolerance the correctness tests use.\n #\n # ``max(x, 0)`` is built out of ``absf`` rather than a max primitive on\n # purpose. ``cute.math`` only gained ``max`` in nvidia-cutlass-dsl 4.6,\n # where the module became a re-export of ``cutlass._mlir_helpers.math``;\n # 4.5's hand-written ``cute.math`` exports 19 names and ``max`` is not\n # among them, so ``cute.math.max`` raises AttributeError there. ``absf``\n # is in every release this repo supports -- 4.5 defines it, and 4.6+\n # deliberately keeps ``absf`` as an alias of the new ``abs``. The\n # supported set is pinned by\n # ``test_cutedsl_impl_only_uses_portable_cute_math_primitives``.\n #\n # max(x, 0) == 0.5*x + 0.5*|x|\n #\n # exact in fp32 for either sign (halving is exact and the two halves are\n # either equal or exact opposites) and, unlike ``0.5*(x + |x|)``, free of\n # the overflow that doubling a large x would introduce.\n x_abs = cute.math.absf(x, fastmath=False)\n x_pos = cutlass.Float32(cutlass.Float32(0.5) * x + cutlass.Float32(0.5) * x_abs)\n ex = cute.math.exp(cutlass.Float32(-x_abs), fastmath=False)\n sp = cutlass.Float32(\n x_pos\n + cute.math.log(cutlass.Float32(cutlass.Float32(1.0) + ex), fastmath=False)\n )\n eal = cute.math.exp(A_log[h], fastmath=False)\n arg = cutlass.Float32(-cutlass.Float32(eal * sp))\n g = cute.math.exp(arg, fastmath=False)\n\n qsq = cutlass.Float32(q0 * q0 + q1 * q1 + q2 * q2 + q3 * q3)\n ksq = cutlass.Float32(kk0 * kk0 + kk1 * kk1 + kk2 * kk2 + kk3 * kk3)\n qsq = qsq + cute.arch.shuffle_sync_bfly(qsq, 16)\n qsq = qsq + cute.arch.shuffle_sync_bfly(qsq, 8)\n qsq = qsq + cute.arch.shuffle_sync_bfly(qsq, 4)\n qsq = qsq + cute.arch.shuffle_sync_bfly(qsq, 2)\n qsq = qsq + cute.arch.shuffle_sync_bfly(qsq, 1)\n ksq = ksq + cute.arch.shuffle_sync_bfly(ksq, 16)\n ksq = ksq + cute.arch.shuffle_sync_bfly(ksq, 8)\n ksq = ksq + cute.arch.shuffle_sync_bfly(ksq, 4)\n ksq = ksq + cute.arch.shuffle_sync_bfly(ksq, 2)\n ksq = ksq + cute.arch.shuffle_sync_bfly(ksq, 1)\n q_rms = cute.math.rsqrt(\n cutlass.Float32(qsq + cutlass.Float32(1e-6)), fastmath=False\n )\n k_rms = cute.math.rsqrt(\n cutlass.Float32(ksq + cutlass.Float32(1e-6)), fastmath=False\n )\n qn0 = cutlass.Float32(q0 * q_rms)\n qn1 = cutlass.Float32(q1 * q_rms)\n qn2 = cutlass.Float32(q2 * q_rms)\n qn3 = cutlass.Float32(q3 * q_rms)\n kn0 = cutlass.Float32(kk0 * k_rms)\n kn1 = cutlass.Float32(kk1 * k_rms)\n kn2 = cutlass.Float32(kk2 * k_rms)\n kn3 = cutlass.Float32(kk3 * k_rms)\n\n ov = cutlass.Float32(\n kn0 * cutlass.Float32(g * sv0)\n + kn1 * cutlass.Float32(g * sv1)\n + kn2 * cutlass.Float32(g * sv2)\n + kn3 * cutlass.Float32(g * sv3)\n )\n ov = ov + cute.arch.shuffle_sync_bfly(ov, 16)\n ov = ov + cute.arch.shuffle_sync_bfly(ov, 8)\n ov = ov + cute.arch.shuffle_sync_bfly(ov, 4)\n ov = ov + cute.arch.shuffle_sync_bfly(ov, 2)\n ov = ov + cute.arch.shuffle_sync_bfly(ov, 1)\n old_v = ov # all lanes hold the sum\n new_v = cutlass.Float32(\n beta * vvv + cutlass.Float32(cutlass.Float32(1.0) - beta) * old_v\n )\n d = cutlass.Float32(new_v - old_v)\n\n hs0 = cutlass.Float32(g * sv0 + kn0 * d)\n hs1 = cutlass.Float32(g * sv1 + kn1 * d)\n hs2 = cutlass.Float32(g * sv2 + kn2 * d)\n hs3 = cutlass.Float32(g * sv3 + kn3 * d)\n ssm_state[pp, h, v, k0] = hs0\n ssm_state[pp, h, v, k1] = hs1\n ssm_state[pp, h, v, k2] = hs2\n ssm_state[pp, h, v, k3] = hs3\n outp = cutlass.Float32(qn0 * hs0 + qn1 * hs1 + qn2 * hs2 + qn3 * hs3)\n outp = outp + cute.arch.shuffle_sync_bfly(outp, 16)\n outp = outp + cute.arch.shuffle_sync_bfly(outp, 8)\n outp = outp + cute.arch.shuffle_sync_bfly(outp, 4)\n outp = outp + cute.arch.shuffle_sync_bfly(outp, 2)\n outp = outp + cute.arch.shuffle_sync_bfly(outp, 1)\n if lane == 0:\n out_v = cutlass.Float32(outp * cutlass.Float32(scale))\n output[b_idx, 0, h, v] = out_v.to(cutlass.BFloat16)\n else:\n cute.arch.griddepcontrol_wait()\n if lane == 0:\n output[b_idx, 0, h, v] = cutlass.BFloat16(0.0)\n\n\n@cute.jit\ndef fused_launch(\n hidden,\n w_ba,\n mixed_qkv,\n conv_weight,\n conv_bias,\n conv_state,\n A_log,\n dt_bias,\n ssm_state,\n state_indices,\n output,\n qkv_act,\n part,\n stream: cuda_driver.CUstream,\n B: cutlass.Constexpr,\n scale: cutlass.Constexpr,\n):\n \"\"\"Host-side launcher: ``pre_kernel`` then ``delta_kernel``, PDL-chained.\n\n Compiled once per (batch size, scale, conv-state stride mode); ``B`` and\n ``scale`` are constexpr because both shape the generated code.\n\n ``use_pdl=True`` on BOTH launches is a promise about the kernels, not just\n a scheduling hint: each of them may start before its stream predecessor has\n completed and flushed, so each must issue ``griddepcontrol_wait()`` before\n reading what a predecessor produced. Do not add a third PDL launch here\n without reading the contract block above ``pre_kernel``.\n \"\"\"\n pre_kernel(\n mixed_qkv,\n conv_weight,\n conv_bias,\n conv_state,\n state_indices,\n qkv_act,\n hidden,\n w_ba,\n part,\n B,\n ).launch(\n grid=[B * NCONV + B * KS, 1, 1], block=[256, 1, 1], stream=stream, use_pdl=True\n )\n delta_kernel(\n qkv_act,\n part,\n A_log,\n dt_bias,\n ssm_state,\n state_indices,\n output,\n scale,\n ).launch(grid=[B * HV * NRB, 1, 1], block=[256, 1, 1], stream=stream, use_pdl=True)\n\n\n# Keyed by the three things that change the generated kernel -- batch size,\n# the softmax scale baked in as a constant, and the conv-state stride mode --\n# and, for the workspace, by (batch size, device). The compiled-kernel value\n# is whatever ``cute.compile`` returns, which has no public static type.\n_compiled: dict[tuple[int, float, int], Any] = {}\n_workspace_cache: dict[tuple[int, str], tuple[torch.Tensor, torch.Tensor]] = {}\n_launch_count = 0\n\n# Stream that last used the per-(batch, device) workspace, per device. The\n# workspace (``part``/``qkv_act``) is shared by every call with that batch\n# size, so two calls in flight on different streams would interleave writes\n# into the same buffers; order_after_previous_stream() (see _stream_order.py)\n# makes the later call wait on the earlier one instead.\n_workspace_stream: dict[str, torch.cuda.Stream] = {}\n\n\ndef conv_state_leading_dim(conv_state: torch.Tensor) -> int:\n \"\"\"Stride-1 mode of the logical [P, QKV_DIM, CONV_STATE_LEN] conv-state\n view: 1 for a transposed SD pool (vLLM default), 2 for a DS-dense pool.\n The dispatch gate has already validated the stride pattern.\"\"\"\n return 1 if conv_state.stride(1) == 1 else 2\n\n\ndef _cache_has(\n B: int, scale: float, device: torch.device, conv_leading_dim: int = 1\n) -> bool:\n \"\"\"True if the (B, scale, conv-state layout) variant is compiled AND the\n per-(B, device) workspace exists — i.e. a call is capture-safe (kernel\n launches plus one stream memset, no compilation or allocation).\"\"\"\n return (int(B), float(scale), int(conv_leading_dim)) in _compiled and (\n int(B),\n str(device),\n ) in _workspace_cache\n\n\ndef ready_for_graph_capture(\n hidden_states: torch.Tensor, conv_state: torch.Tensor, scale: float\n) -> bool:\n \"\"\"True when this exact call (batch size, scale, conv-state layout) can\n be recorded into a CUDA graph without compiling or allocating.\"\"\"\n return _cache_has(\n int(hidden_states.shape[0]),\n float(scale),\n hidden_states.device,\n conv_state_leading_dim(conv_state),\n )\n\n\ndef execute(\n hidden_states,\n w_ba,\n mixed_qkv,\n conv_weight,\n conv_bias,\n conv_state,\n A_log,\n dt_bias,\n scale,\n ssm_state,\n state_indices,\n out=None,\n):\n \"\"\"Run the fused step on the caller's current stream; raise on failure.\n\n The dispatch layer has already validated the call against the registry\n and the op contract. Both state pools are updated in place.\n \"\"\"\n global _launch_count\n B = int(hidden_states.shape[0])\n scale_f = float(scale)\n dev = hidden_states.device\n\n output = (\n out\n if out is not None\n else torch.empty((B, 1, HV, D), dtype=torch.bfloat16, device=dev)\n )\n\n # Persistent workspace: the GEMV partials are accumulated with atomics, so\n # `part` is re-zeroed each call with a driver memset on the current stream\n # (no extra torch kernel launch; captured as a memset node under graphs).\n wkey = (B, str(dev))\n workspace = _workspace_cache.get(wkey)\n if workspace is None:\n workspace = (\n torch.zeros((B, N_BA), dtype=torch.float32, device=dev),\n torch.empty((B, QKV_DIM), dtype=torch.bfloat16, device=dev),\n )\n _workspace_cache[wkey] = workspace\n part, qkv_act = workspace\n order_after_previous_stream(_workspace_stream, dev)\n # Take the stream from the tensors' device explicitly rather than from the\n # ambient one: the dispatcher makes that device current before calling in,\n # but an impl that reads torch.cuda.current_stream() with no argument would\n # silently follow the ambient device if that ever stopped being true.\n stream = cuda_driver.CUstream(torch.cuda.current_stream(dev).cuda_stream)\n # Checked, not fire-and-forget: `part` is the accumulator the K-split GEMV\n # atomically adds into, so a memset that did not run leaves the previous\n # step's partials in place and both gates are silently wrong -- exactly the\n # class of failure the impl attestation exists to make visible. Raising\n # instead hands the call to the dispatch layer, which latches this impl off\n # and serves the composable path.\n checkCudaErrors(\n cuda_driver.cuMemsetD32Async(int(part.data_ptr()), 0, B * N_BA, stream)\n )\n\n # conv_state is a logical [P, QKV_DIM, CONV_STATE_LEN] view over either a\n # transposed SD pool (stride-1 channels, vLLM default) or a DS-dense pool\n # (stride-1 time steps); pick the matching leading dim and compile one\n # variant per layout (indexing is stride-generic, only the layout's\n # static stride-1 mode differs).\n cs_ld = conv_state_leading_dim(conv_state)\n\n key = (B, scale_f, cs_ld)\n fn = _compiled.get(key)\n if fn is None:\n # The DLPack markers exist only to describe the argument layouts to\n # cute.compile; the compiled kernel is invoked with the torch tensors\n # themselves. Building them on a warm call would be thirteen\n # from_dlpack round-trips of pure host overhead per decode step per\n # layer, so they are built only on the compiling call.\n m_hidden = from_dlpack(hidden_states, enable_tvm_ffi=True).mark_layout_dynamic()\n m_wba = from_dlpack(w_ba, enable_tvm_ffi=True).mark_layout_dynamic()\n m_qkv = from_dlpack(mixed_qkv, enable_tvm_ffi=True).mark_layout_dynamic()\n m_cw = from_dlpack(conv_weight, enable_tvm_ffi=True).mark_layout_dynamic()\n m_cb = from_dlpack(conv_bias, enable_tvm_ffi=True).mark_layout_dynamic()\n m_cs = from_dlpack(conv_state, enable_tvm_ffi=True).mark_layout_dynamic(\n leading_dim=cs_ld\n )\n m_alog = from_dlpack(A_log, enable_tvm_ffi=True).mark_layout_dynamic()\n m_dtb = from_dlpack(dt_bias, enable_tvm_ffi=True).mark_layout_dynamic()\n m_ssm = from_dlpack(ssm_state, enable_tvm_ffi=True).mark_layout_dynamic()\n m_si = from_dlpack(state_indices, enable_tvm_ffi=True).mark_layout_dynamic()\n m_out = from_dlpack(output, enable_tvm_ffi=True).mark_layout_dynamic()\n m_qa = from_dlpack(qkv_act, enable_tvm_ffi=True).mark_layout_dynamic()\n m_part = from_dlpack(part, enable_tvm_ffi=True).mark_layout_dynamic()\n fn = cute.compile(\n fused_launch,\n m_hidden,\n m_wba,\n m_qkv,\n m_cw,\n m_cb,\n m_cs,\n m_alog,\n m_dtb,\n m_ssm,\n m_si,\n m_out,\n m_qa,\n m_part,\n stream,\n B,\n scale_f,\n options=\"--enable-tvm-ffi\",\n )\n _compiled[key] = fn\n fn(\n hidden_states,\n w_ba,\n mixed_qkv,\n conv_weight,\n conv_bias,\n conv_state,\n A_log,\n dt_bias,\n ssm_state,\n state_indices,\n output,\n qkv_act,\n part,\n stream,\n )\n _launch_count += 1\n return output, conv_state, ssm_state\n\n\ndef launch_count() -> int:\n \"\"\"Host-side dispatches so far (a CUDA-graph capture counts once).\"\"\"\n return _launch_count\n\n\ndef compiled_variant_keys() -> list:\n \"\"\"Compiled-kernel descriptors resident in this process.\"\"\"\n return [\n f\"b{B}_scale{scale}_ld{leading_dim}\"\n for (B, scale, leading_dim) in sorted(_compiled)\n ]\n\n\ndef variant_plan(rows) -> set:\n \"\"\"Distinct compiled kernels this impl needs for its registry rows: one\n per (batch size, conv-state layout). The query scale is also part of\n the compile key but is a runtime value (a serving process uses one\n scale), so the plan counts (b, conv_layout) pairs.\"\"\"\n return {f\"b{row['b']}_{row['conv_layout']}\" for row in rows}\n"},"after_code":{"kind":"string","value":"\"\"\"\nCopyright (c) 2026 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nFused GDN Decode Step - two-launch CuTe-DSL impl with PDL (SM120)\n=================================================================\n\nHost and kernel side of the ``cutedsl_sm120_pdl`` registry impl: a\ntwo-launch CuTe-DSL implementation of the fused GDN decode step, compiled\nper (layer geometry, batch, scale, conv-state layout) and launched on the\ncurrent torch stream. The conv-state pool arrives as a logical [P, QKV_DIM,\nCONV_STATE_LEN] view of either a transposed SD pool (vLLM default) or a\nDS-dense pool; indexing is stride-generic, so the layouts differ only in\nwhich mode carries the static unit stride. The first launch\nfuses the depthwise conv1d update with a heavily K-split b/a GEMV (fp32\npartials accumulated with device-scope atomics); the second applies the gated\ndelta rule. Both launches use programmatic dependent launch (PDL); the\nwait/trigger contract that makes that safe is stated in full above\n:func:`pre_kernel` and pinned by ``tests/gdn/test_fused_decode.py``.\n\nImplements the impl-module interface documented in ../README.md.\nCompilation is lazy: the first eager :func:`execute` of a (geometry, batch,\nscale, conv-state layout) variant compiles it and allocates the\nper-(geometry, batch, device) workspace; once warm, calls are capture-safe\n(kernel launches plus one stream memset). Consumed by\n:mod:`flashinfer.gdn_kernels.experimental.gdn_fused_decode_specialized`;\nimport errors are tolerated there (the cutlass DSL dependency stays\noptional).\n\"\"\"\n\nfrom typing import Any\n\nimport torch\nimport cutlass\nimport cutlass.cute as cute\nimport cuda.bindings.driver as cuda_driver\nfrom cutlass.cute.runtime import from_dlpack\n\nfrom ....cuda_utils import checkCudaErrors\nfrom ._stream_order import order_after_previous_stream\n\n# The layer geometry (HIDDEN, N_BA, QKV_DIM, H_Q, HV, D) is a compile-time\n# parameter: it is passed down as ``cutlass.Constexpr`` and baked into the\n# kernel exactly as a module constant would be, so one variant is compiled\n# per (geometry, batch, scale, conv-state layout). The block shape, the\n# warp->row mapping and the reduction trees do not depend on it; only the\n# sizes and the derived tile counts do.\nRPB = 8 # v-rows per block in delta kernel (8 warps = 256 thr)\nKS = 512 # K-split factor for the GEMV (atomic fp32 partials)\nCONV_TILE = 256 # conv channels per block (== block threads)\n\n\ndef _derived(hidden: int, qkv_dim: int, hv: int, h_q: int, d: int) -> tuple:\n \"\"\"Tile counts derived from a geometry: (GQA, NRB, KCHUNK, NCONV).\n\n Every division here is exact for a supported geometry; the dispatch\n registry only lists geometries that satisfy these relations (asserted in\n :func:`_check_geometry`).\n \"\"\"\n return (hv // h_q, d // RPB, hidden // KS, qkv_dim // CONV_TILE)\n\n\ndef _check_geometry(hidden: int, n_ba: int, qkv_dim: int, h_q: int, hv: int, d: int):\n \"\"\"Reject a geometry whose tiling would not be exact.\n\n The registry is the dispatch surface, so this is a guard against a bad\n row rather than a runtime condition; it raises, and the dispatch layer\n turns that into a fallback.\n \"\"\"\n if (\n hv % h_q\n or d % RPB\n or hidden % KS\n or qkv_dim % CONV_TILE\n or n_ba != 2 * hv\n or d != 4 * 32\n or qkv_dim != (2 * h_q + hv) * d\n or n_ba > CONV_TILE\n ):\n raise RuntimeError(\n \"unsupported fused GDN decode geometry for the CuTe-DSL impl: \"\n f\"hidden={hidden} n_ba={n_ba} qkv_dim={qkv_dim} h_q={h_q} \"\n f\"hv={hv} d={d}\"\n )\n\n\n# ---------------------------------------------------------------------------\n# PDL contract for this op -- read this before moving either griddepcontrol.\n# ---------------------------------------------------------------------------\n# Both launches carry ``use_pdl=True``\n# (CU_LAUNCH_ATTRIBUTE_PROGRAMMATIC_STREAM_SERIALIZATION), which tells the\n# driver it \"is safe to launch the secondary kernel early and not wait on the\n# completion and memory flush of the primary before launching the secondary\"\n# (CUDA programming guide, Programmatic Dependent Launch). Two DIFFERENT\n# hardware events then keep that safe, and conflating them is the way this\n# code goes wrong:\n#\n# griddepcontrol.launch_dependents -- a SCHEDULING gate only. PTX: the\n# designated dependents \"can be scheduled as soon as all other CTAs in\n# the grid issue the same instruction or have completed\". It publishes\n# nothing, orders nothing, and is not what a dependent's wait observes.\n# griddepcontrol.wait -- the VISIBILITY barrier. PTX: the thread waits\n# \"until all prerequisite grids in flight have completed and all the\n# memory operations from the prerequisite grids are performed and made\n# visible to the current grid\", i.e. until the predecessor grid's\n# grid-ending membar has drained. This, and only this, makes a read of\n# a predecessor's output legal.\n#\n# Who waits, who triggers, and what each ordering protects:\n#\n# pre_kernel WAITS FIRST, unconditionally, before its first global load and\n# before the conv/GEMV block split so that every block reaches it.\n# Everything it loads is produced by a stream predecessor -- mixed_qkv\n# and hidden by this layer's projections, state_indices by the caller's\n# metadata prep, conv_state by an earlier decode step, and ``part`` by\n# the cuMemsetD32Async this launch is queued behind. The launch\n# attribute above explicitly releases the driver from waiting on those,\n# so without this wait the op's correctness would rest on whether some\n# unrelated upstream kernel happens to fire a trigger -- a property this\n# op cannot see and must not depend on.\n# pre_kernel THEN TRIGGERS, in the same unconditional prologue. Order\n# matters and is not cosmetic: the trigger is what places delta_kernel's\n# CTAs on the SMs, and delta_kernel reads ssm_state BEFORE its own wait.\n# Triggering ahead of pre_kernel's wait would schedule delta while\n# pre_kernel is itself still unordered against its predecessors, and\n# delta's pre-wait prefetch would inherit exactly that -- no ordering\n# against whoever last wrote ssm_state/state_indices. Waiting first is\n# what hands the dependent an already-ordered state.\n# pre_kernel triggers HERE rather than after its stores on purpose. The\n# trigger does not publish qkv_act/part and is not what releases\n# delta_kernel's wait; delta's wait does not return until pre_kernel's\n# whole grid has completed and flushed, which covers every store in this\n# kernel wherever it sits. Firing at entry is what buys the overlap the\n# impl exists for (upstream's gdn_decode_bf16_wy_ucache_flush.py fires at\n# entry for the same reason). What it does cost is SM competition:\n# delta's CTAs are resident and parked on their wait while pre_kernel\n# runs. That trade is measured, not assumed -- see ../README.md.\n# delta_kernel WAITS in both arms of its padded-row branch, after the\n# ssm_state prefetch and before the first read of qkv_act/part. That\n# wait is the ordering that protects the conv output and the GEMV\n# partials.\n# delta_kernel does NOT trigger, so nothing downstream is scheduled early on\n# its account and its ssm_state/output stores need no further signal\n# here: a successor is scheduled at this grid's completion. Adding a\n# trigger to delta_kernel would be a performance change that also\n# obliges every PDL successor to wait -- do not add one without the\n# matching wait on the other side.\n#\n# Pinned by ``test_pdl_kernels_wait_before_their_first_launch_dependents`` and\n# ``test_every_pdl_kernel_waits_on_all_paths`` in tests/gdn/test_fused_decode.py.\n@cute.kernel\ndef pre_kernel(\n mixed_qkv: cute.Tensor, # [B, QKV_DIM] bf16\n conv_weight: cute.Tensor, # [QKV_DIM, CONV_WIDTH] bf16\n conv_bias: cute.Tensor, # [QKV_DIM] bf16\n conv_state: cute.Tensor, # [P, QKV_DIM, CONV_STATE_LEN] bf16 (in-place)\n state_indices: cute.Tensor, # [B] int32\n qkv_act: cute.Tensor, # [B, QKV_DIM] bf16 scratch\n hidden: cute.Tensor, # [B, HIDDEN] bf16\n w_ba: cute.Tensor, # [HIDDEN, N_BA] bf16\n part: cute.Tensor, # [B, N_BA] f32, zeroed before launch\n Bc: cutlass.Constexpr,\n N_BA: cutlass.Constexpr,\n NCONV: cutlass.Constexpr,\n KCHUNK: cutlass.Constexpr,\n):\n \"\"\"First of the two launches: conv1d state update and the b/a GEMV.\n\n One grid does both, since neither depends on the other: blocks\n ``[0, B*NCONV)`` shift the conv-state rows, append the new input and write\n the silu-activated conv output to ``qkv_act``; the remaining blocks\n accumulate K-split partials of ``hidden @ w_ba`` into ``part`` with\n gpu-scope atomics (hence the memset of ``part`` before the launch). It\n waits on its own stream predecessors and then signals PDL launch\n dependents up front, so ``delta_kernel``'s ``ssm_state`` prefetch overlaps\n this entire body -- see the PDL contract block above.\n \"\"\"\n # Combined conv + K-split GEMV in one launch. Blocks [0, B*NCONV) do conv;\n # blocks [B*NCONV, ...) accumulate GEMV partials with gpu-scope atomics.\n #\n # PDL prologue, above the block split so EVERY block runs both halves.\n # (1) Wait: this grid is launched with programmatic stream serialization,\n # so it may already be running while its predecessors are still draining.\n # Every global load below -- state_indices, conv_state, mixed_qkv, hidden,\n # the weights, and the atomics into the freshly memset `part` -- reads what\n # those predecessors produced, so this is the barrier that makes them\n # legal, not an optimization.\n cute.arch.griddepcontrol_wait()\n # (2) Only then release delta_kernel onto the SMs, so its long-latency\n # ssm_state prefetch overlaps this whole body. Never before the wait:\n # delta reads global memory before its own wait and would inherit this\n # grid's unordered state. This does not publish anything -- delta's wait\n # covers pre_kernel's stores wherever they sit.\n cute.arch.griddepcontrol_launch_dependents()\n\n tidx, _, _ = cute.arch.thread_idx()\n bidx, _, _ = cute.arch.block_idx()\n\n if bidx < Bc * NCONV:\n b_idx = bidx // NCONV\n tile = bidx % NCONV\n c = tile * CONV_TILE + tidx\n pp = cutlass.Int32(state_indices[b_idx])\n # A negative slot index (vLLM's PAD_SLOT_ID = -1) marks a padded batch\n # row -- what a CUDA-graph replay carries between the live request\n # count and the captured batch size. It owns no conv-state row, so\n # neither read nor write one for it; ``delta_kernel`` skips the same\n # row and zeroes its output. The predicate depends only on ``bidx``,\n # so it is block-uniform: one taken branch per block, not divergence.\n # ``qkv_act`` is left untouched for such a row -- it is per-call\n # scratch that only the skipped delta blocks would read.\n if pp >= 0:\n st0_bf = conv_state[pp, c, 0]\n st1_bf = conv_state[pp, c, 1]\n st2_bf = conv_state[pp, c, 2]\n st0 = st0_bf.to(cutlass.Float32)\n st1 = st1_bf.to(cutlass.Float32)\n st2 = st2_bf.to(cutlass.Float32)\n xbf = mixed_qkv[b_idx, c]\n xx = xbf.to(cutlass.Float32)\n w0 = conv_weight[c, 0].to(cutlass.Float32)\n w1 = conv_weight[c, 1].to(cutlass.Float32)\n w2 = conv_weight[c, 2].to(cutlass.Float32)\n w3 = conv_weight[c, 3].to(cutlass.Float32)\n bb = conv_bias[c].to(cutlass.Float32)\n y = cutlass.Float32(st0 * w0 + st1 * w1 + st2 * w2 + xx * w3 + bb)\n ey = cute.math.exp(cutlass.Float32(-y), fastmath=False)\n yv = cutlass.Float32(y / cutlass.Float32(cutlass.Float32(1.0) + ey))\n qkv_act[b_idx, c] = yv.to(cutlass.BFloat16)\n conv_state[pp, c, 0] = st1_bf\n conv_state[pp, c, 1] = st2_bf\n conv_state[pp, c, 2] = xbf\n else:\n g = bidx - Bc * NCONV\n b_idx = g // KS\n ks = g % KS\n n = tidx\n if n < N_BA:\n base = ks * KCHUNK\n acc = cutlass.Float32(0.0)\n for i in cutlass.range_constexpr(KCHUNK):\n gi = base + i\n hv = hidden[b_idx, gi].to(cutlass.Float32)\n acc = acc + hv * w_ba[gi, n].to(cutlass.Float32)\n cute.arch.atomic_add(part.iterator + (b_idx * N_BA + n), acc, scope=\"gpu\")\n\n\n@cute.kernel\ndef delta_kernel(\n qkv_act: cute.Tensor, # [B, QKV_DIM] bf16\n part: cute.Tensor, # [B, N_BA] f32\n A_log: cute.Tensor, # [HV] f32\n dt_bias: cute.Tensor, # [HV] bf16\n ssm_state: cute.Tensor, # [P, HV, D, D] f32 (in-place)\n state_indices: cute.Tensor, # [B] int32\n output: cute.Tensor, # [B, 1, HV, D] bf16\n scale: cutlass.Constexpr,\n H_Q: cutlass.Constexpr,\n HV: cutlass.Constexpr,\n D: cutlass.Constexpr,\n GQA: cutlass.Constexpr,\n NRB: cutlass.Constexpr,\n):\n \"\"\"Second launch: gates, qk-L2-norm and the gated delta-rule update.\n\n One warp owns one ``ssm_state`` row: it prefetches the row before waiting\n on PDL (``pre_kernel`` never touches ``ssm_state``, so the long-latency\n fp32 loads overlap the whole first kernel), reduces the b/a GEMV partials\n into the beta and decay gates, and writes the updated row back in place\n plus this row's slice of the attention output.\n \"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n bidx, _, _ = cute.arch.block_idx()\n hh = bidx // NRB # global head index (b_idx*HV + h)\n rb = bidx % NRB # row-block within head\n b_idx = hh // HV\n h = hh % HV\n qhd = h // GQA\n warp = tidx // 32\n lane = tidx % 32\n v = rb * RPB + warp # ssm row index this warp owns\n\n # Second global read issued before this kernel's PDL wait (with the\n # ssm_state prefetch below). pre_kernel does not write state_indices;\n # ordering against whoever did is inherited from pre_kernel waiting before\n # it triggers -- see the PDL contract block at the top of this file.\n pp = cutlass.Int32(state_indices[b_idx])\n\n # A negative slot index (vLLM's PAD_SLOT_ID = -1) marks a padded batch\n # row: it owns no pool slot, so neither state pool may be read or written\n # for it and its output row is zero -- the same contract the fp32 path of\n # gated_delta_rule_decode_pretranspose already documents. The predicate\n # depends only on bidx, so it is block-uniform: one taken branch per\n # block, and the warp-wide shuffles below are never reached under a\n # partial mask. Both arms wait on PDL: the padded arm reads nothing\n # pre_kernel wrote and would be correct without it, but keeping the wait\n # uniform across blocks keeps the launch's dependency semantics simple.\n if pp >= 0:\n # fp32 state loads issued before the PDL wait: pre_kernel never writes\n # ssm_state, so these long-latency loads overlap its whole body. What\n # orders them against the PREVIOUS step's writer of ssm_state is\n # pre_kernel waiting before it triggers: this grid cannot be scheduled\n # until pre_kernel has released it, and pre_kernel only releases after\n # its own wait has drained the predecessors. Keep that order there.\n k0 = lane\n k1 = lane + 32\n k2 = lane + 64\n k3 = lane + 96\n sv0 = ssm_state[pp, h, v, k0]\n sv1 = ssm_state[pp, h, v, k1]\n sv2 = ssm_state[pp, h, v, k2]\n sv3 = ssm_state[pp, h, v, k3]\n\n cute.arch.griddepcontrol_wait()\n\n qbase = qhd * D\n kbase = H_Q * D + qhd * D\n q0 = qkv_act[b_idx, qbase + k0].to(cutlass.Float32)\n q1 = qkv_act[b_idx, qbase + k1].to(cutlass.Float32)\n q2 = qkv_act[b_idx, qbase + k2].to(cutlass.Float32)\n q3 = qkv_act[b_idx, qbase + k3].to(cutlass.Float32)\n kk0 = qkv_act[b_idx, kbase + k0].to(cutlass.Float32)\n kk1 = qkv_act[b_idx, kbase + k1].to(cutlass.Float32)\n kk2 = qkv_act[b_idx, kbase + k2].to(cutlass.Float32)\n kk3 = qkv_act[b_idx, kbase + k3].to(cutlass.Float32)\n vvv = qkv_act[b_idx, 2 * H_Q * D + h * D + v].to(cutlass.Float32)\n\n # Redundant per-thread gate computation (no smem/sync needed). The fp32\n # gate sums round through bf16 to match the composable path's GEMV output\n # dtype before the sigmoid/softplus gates.\n b_sum = part[b_idx, h]\n a_sum = part[b_idx, HV + h]\n b_bf = b_sum.to(cutlass.BFloat16).to(cutlass.Float32)\n a_bf = a_sum.to(cutlass.BFloat16).to(cutlass.Float32)\n eb = cute.math.exp(cutlass.Float32(-b_bf), fastmath=False)\n beta = cutlass.Float32(1.0) / cutlass.Float32(cutlass.Float32(1.0) + eb)\n dtb = dt_bias[h].to(cutlass.Float32)\n x = cutlass.Float32(a_bf + dtb)\n # softplus via the overflow-free identity\n # softplus(x) = max(x, 0) + log(1 + exp(-|x|)),\n # branch-free. The naive log(1 + exp(x)) sends exp(x) to +inf for\n # x > ~88.7 in fp32, which collapses the decay gate to exactly 0 instead\n # of exp(-exp(A_log) * x) -- a silently wrong gate whenever exp(A_log) is\n # small enough for the true gate to stay O(1). The identity agrees with\n # torch.nn.functional.softplus (threshold=20, i.e. the composable path)\n # and with the CUDA impl's `x > 20 ? x : log1p(exp(x))` to fp32 rounding\n # over the whole range: worst case 1e-6 on the resulting gate, three\n # orders below the bf16 tolerance the correctness tests use.\n #\n # ``max(x, 0)`` is built out of ``absf`` rather than a max primitive on\n # purpose. ``cute.math`` only gained ``max`` in nvidia-cutlass-dsl 4.6,\n # where the module became a re-export of ``cutlass._mlir_helpers.math``;\n # 4.5's hand-written ``cute.math`` exports 19 names and ``max`` is not\n # among them, so ``cute.math.max`` raises AttributeError there. ``absf``\n # is in every release this repo supports -- 4.5 defines it, and 4.6+\n # deliberately keeps ``absf`` as an alias of the new ``abs``. The\n # supported set is pinned by\n # ``test_cutedsl_impl_only_uses_portable_cute_math_primitives``.\n #\n # max(x, 0) == 0.5*x + 0.5*|x|\n #\n # exact in fp32 for either sign (halving is exact and the two halves are\n # either equal or exact opposites) and, unlike ``0.5*(x + |x|)``, free of\n # the overflow that doubling a large x would introduce.\n x_abs = cute.math.absf(x, fastmath=False)\n x_pos = cutlass.Float32(cutlass.Float32(0.5) * x + cutlass.Float32(0.5) * x_abs)\n ex = cute.math.exp(cutlass.Float32(-x_abs), fastmath=False)\n sp = cutlass.Float32(\n x_pos\n + cute.math.log(cutlass.Float32(cutlass.Float32(1.0) + ex), fastmath=False)\n )\n eal = cute.math.exp(A_log[h], fastmath=False)\n arg = cutlass.Float32(-cutlass.Float32(eal * sp))\n g = cute.math.exp(arg, fastmath=False)\n\n qsq = cutlass.Float32(q0 * q0 + q1 * q1 + q2 * q2 + q3 * q3)\n ksq = cutlass.Float32(kk0 * kk0 + kk1 * kk1 + kk2 * kk2 + kk3 * kk3)\n qsq = qsq + cute.arch.shuffle_sync_bfly(qsq, 16)\n qsq = qsq + cute.arch.shuffle_sync_bfly(qsq, 8)\n qsq = qsq + cute.arch.shuffle_sync_bfly(qsq, 4)\n qsq = qsq + cute.arch.shuffle_sync_bfly(qsq, 2)\n qsq = qsq + cute.arch.shuffle_sync_bfly(qsq, 1)\n ksq = ksq + cute.arch.shuffle_sync_bfly(ksq, 16)\n ksq = ksq + cute.arch.shuffle_sync_bfly(ksq, 8)\n ksq = ksq + cute.arch.shuffle_sync_bfly(ksq, 4)\n ksq = ksq + cute.arch.shuffle_sync_bfly(ksq, 2)\n ksq = ksq + cute.arch.shuffle_sync_bfly(ksq, 1)\n q_rms = cute.math.rsqrt(\n cutlass.Float32(qsq + cutlass.Float32(1e-6)), fastmath=False\n )\n k_rms = cute.math.rsqrt(\n cutlass.Float32(ksq + cutlass.Float32(1e-6)), fastmath=False\n )\n qn0 = cutlass.Float32(q0 * q_rms)\n qn1 = cutlass.Float32(q1 * q_rms)\n qn2 = cutlass.Float32(q2 * q_rms)\n qn3 = cutlass.Float32(q3 * q_rms)\n kn0 = cutlass.Float32(kk0 * k_rms)\n kn1 = cutlass.Float32(kk1 * k_rms)\n kn2 = cutlass.Float32(kk2 * k_rms)\n kn3 = cutlass.Float32(kk3 * k_rms)\n\n ov = cutlass.Float32(\n kn0 * cutlass.Float32(g * sv0)\n + kn1 * cutlass.Float32(g * sv1)\n + kn2 * cutlass.Float32(g * sv2)\n + kn3 * cutlass.Float32(g * sv3)\n )\n ov = ov + cute.arch.shuffle_sync_bfly(ov, 16)\n ov = ov + cute.arch.shuffle_sync_bfly(ov, 8)\n ov = ov + cute.arch.shuffle_sync_bfly(ov, 4)\n ov = ov + cute.arch.shuffle_sync_bfly(ov, 2)\n ov = ov + cute.arch.shuffle_sync_bfly(ov, 1)\n old_v = ov # all lanes hold the sum\n new_v = cutlass.Float32(\n beta * vvv + cutlass.Float32(cutlass.Float32(1.0) - beta) * old_v\n )\n d = cutlass.Float32(new_v - old_v)\n\n hs0 = cutlass.Float32(g * sv0 + kn0 * d)\n hs1 = cutlass.Float32(g * sv1 + kn1 * d)\n hs2 = cutlass.Float32(g * sv2 + kn2 * d)\n hs3 = cutlass.Float32(g * sv3 + kn3 * d)\n ssm_state[pp, h, v, k0] = hs0\n ssm_state[pp, h, v, k1] = hs1\n ssm_state[pp, h, v, k2] = hs2\n ssm_state[pp, h, v, k3] = hs3\n outp = cutlass.Float32(qn0 * hs0 + qn1 * hs1 + qn2 * hs2 + qn3 * hs3)\n outp = outp + cute.arch.shuffle_sync_bfly(outp, 16)\n outp = outp + cute.arch.shuffle_sync_bfly(outp, 8)\n outp = outp + cute.arch.shuffle_sync_bfly(outp, 4)\n outp = outp + cute.arch.shuffle_sync_bfly(outp, 2)\n outp = outp + cute.arch.shuffle_sync_bfly(outp, 1)\n if lane == 0:\n out_v = cutlass.Float32(outp * cutlass.Float32(scale))\n output[b_idx, 0, h, v] = out_v.to(cutlass.BFloat16)\n else:\n cute.arch.griddepcontrol_wait()\n if lane == 0:\n output[b_idx, 0, h, v] = cutlass.BFloat16(0.0)\n\n\n@cute.jit\ndef fused_launch(\n hidden,\n w_ba,\n mixed_qkv,\n conv_weight,\n conv_bias,\n conv_state,\n A_log,\n dt_bias,\n ssm_state,\n state_indices,\n output,\n qkv_act,\n part,\n stream: cuda_driver.CUstream,\n B: cutlass.Constexpr,\n scale: cutlass.Constexpr,\n HIDDEN: cutlass.Constexpr,\n N_BA: cutlass.Constexpr,\n QKV_DIM: cutlass.Constexpr,\n H_Q: cutlass.Constexpr,\n HV: cutlass.Constexpr,\n D: cutlass.Constexpr,\n):\n \"\"\"Host-side launcher: ``pre_kernel`` then ``delta_kernel``, PDL-chained.\n\n Compiled once per (layer geometry, batch size, scale, conv-state stride\n mode); ``B``, ``scale`` and the geometry are constexpr because all of\n them shape the generated code.\n\n ``use_pdl=True`` on BOTH launches is a promise about the kernels, not just\n a scheduling hint: each of them may start before its stream predecessor has\n completed and flushed, so each must issue ``griddepcontrol_wait()`` before\n reading what a predecessor produced. Do not add a third PDL launch here\n without reading the contract block above ``pre_kernel``.\n \"\"\"\n GQA, NRB, KCHUNK, NCONV = _derived(HIDDEN, QKV_DIM, HV, H_Q, D)\n pre_kernel(\n mixed_qkv,\n conv_weight,\n conv_bias,\n conv_state,\n state_indices,\n qkv_act,\n hidden,\n w_ba,\n part,\n B,\n N_BA,\n NCONV,\n KCHUNK,\n ).launch(\n grid=[B * NCONV + B * KS, 1, 1],\n block=[CONV_TILE, 1, 1],\n stream=stream,\n use_pdl=True,\n )\n delta_kernel(\n qkv_act,\n part,\n A_log,\n dt_bias,\n ssm_state,\n state_indices,\n output,\n scale,\n H_Q,\n HV,\n D,\n GQA,\n NRB,\n ).launch(\n grid=[B * HV * NRB, 1, 1],\n block=[RPB * 32, 1, 1], # one warp per state row block\n stream=stream,\n use_pdl=True,\n )\n\n\n# Keyed by the four things that change the generated kernel -- the layer\n# geometry, batch size, the softmax scale baked in as a constant, and the\n# conv-state stride mode -- and, for the workspace, by (geometry, batch size,\n# device). The compiled-kernel value is whatever ``cute.compile`` returns,\n# which has no public static type.\n_compiled: dict[tuple[tuple, int, float, int], Any] = {}\n_workspace_cache: dict[tuple[tuple, int, str], tuple[torch.Tensor, torch.Tensor]] = {}\n_launch_count = 0\n\n# Stream that last used the per-(geometry, batch, device) workspace, per\n# device. The workspace (``part``/``qkv_act``) is shared by every call with\n# that geometry and batch size, so two calls in flight on different streams\n# would interleave writes into the same buffers;\n# order_after_previous_stream() (see _stream_order.py) makes the later call\n# wait on the earlier one instead.\n_workspace_stream: dict[str, torch.cuda.Stream] = {}\n\n\ndef conv_state_leading_dim(conv_state: torch.Tensor) -> int:\n \"\"\"Stride-1 mode of the logical [P, QKV_DIM, CONV_STATE_LEN] conv-state\n view: 1 for a transposed SD pool (vLLM default), 2 for a DS-dense pool.\n The dispatch gate has already validated the stride pattern.\"\"\"\n return 1 if conv_state.stride(1) == 1 else 2\n\n\ndef geometry_key(signature: dict) -> tuple:\n \"\"\"Compile-time geometry key of a dispatch signature.\"\"\"\n return (\n int(signature[\"hidden\"]),\n int(signature[\"n_ba\"]),\n int(signature[\"qkv_dim\"]),\n int(signature[\"h_q\"]),\n int(signature[\"hv\"]),\n int(signature[\"d\"]),\n )\n\n\ndef _cache_has(\n geometry: tuple,\n B: int,\n scale: float,\n device: torch.device,\n conv_leading_dim: int = 1,\n) -> bool:\n \"\"\"True if the (geometry, B, scale, conv-state layout) variant is compiled\n AND the per-(geometry, B, device) workspace exists — i.e. a call is\n capture-safe (kernel launches plus one stream memset, no compilation or\n allocation).\"\"\"\n return (geometry, int(B), float(scale), int(conv_leading_dim)) in _compiled and (\n geometry,\n int(B),\n str(device),\n ) in _workspace_cache\n\n\ndef ready_for_graph_capture(\n signature: dict,\n hidden_states: torch.Tensor,\n conv_state: torch.Tensor,\n scale: float,\n) -> bool:\n \"\"\"True when this exact call (geometry, batch size, scale, conv-state\n layout) can be recorded into a CUDA graph without compiling or\n allocating.\n\n The geometry comes from the matched dispatch signature rather than being\n re-derived here: readiness must be answered about the exact compiled\n variant the dispatcher is about to run, so a process warm for one model\n cannot make a differently-shaped model's call look capture-ready.\"\"\"\n return _cache_has(\n geometry_key(signature),\n int(hidden_states.shape[0]),\n float(scale),\n hidden_states.device,\n conv_state_leading_dim(conv_state),\n )\n\n\ndef execute(\n hidden_states,\n w_ba,\n mixed_qkv,\n conv_weight,\n conv_bias,\n conv_state,\n A_log,\n dt_bias,\n scale,\n ssm_state,\n state_indices,\n out=None,\n):\n \"\"\"Run the fused step on the caller's current stream; raise on failure.\n\n The dispatch layer has already validated the call against the registry\n and the op contract. Both state pools are updated in place.\n \"\"\"\n global _launch_count\n B = int(hidden_states.shape[0])\n scale_f = float(scale)\n dev = hidden_states.device\n\n # Layer geometry of this call (the dispatch layer has already matched it\n # against the registry); h_q is derived from the q/k/v head split.\n HIDDEN = int(hidden_states.shape[1])\n N_BA = int(w_ba.shape[1])\n QKV_DIM = int(mixed_qkv.shape[1])\n HV = int(A_log.shape[0])\n D = int(ssm_state.shape[-1])\n H_Q = (QKV_DIM - HV * D) // (2 * D)\n _check_geometry(HIDDEN, N_BA, QKV_DIM, H_Q, HV, D)\n geometry = (HIDDEN, N_BA, QKV_DIM, H_Q, HV, D)\n\n output = (\n out\n if out is not None\n else torch.empty((B, 1, HV, D), dtype=torch.bfloat16, device=dev)\n )\n\n # Persistent workspace: the GEMV partials are accumulated with atomics, so\n # `part` is re-zeroed each call with a driver memset on the current stream\n # (no extra torch kernel launch; captured as a memset node under graphs).\n wkey = (geometry, B, str(dev))\n workspace = _workspace_cache.get(wkey)\n if workspace is None:\n workspace = (\n torch.zeros((B, N_BA), dtype=torch.float32, device=dev),\n torch.empty((B, QKV_DIM), dtype=torch.bfloat16, device=dev),\n )\n _workspace_cache[wkey] = workspace\n part, qkv_act = workspace\n order_after_previous_stream(_workspace_stream, dev)\n # Take the stream from the tensors' device explicitly rather than from the\n # ambient one: the dispatcher makes that device current before calling in,\n # but an impl that reads torch.cuda.current_stream() with no argument would\n # silently follow the ambient device if that ever stopped being true.\n stream = cuda_driver.CUstream(torch.cuda.current_stream(dev).cuda_stream)\n # Checked, not fire-and-forget: `part` is the accumulator the K-split GEMV\n # atomically adds into, so a memset that did not run leaves the previous\n # step's partials in place and both gates are silently wrong -- exactly the\n # class of failure the impl attestation exists to make visible. Raising\n # instead hands the call to the dispatch layer, which latches this impl off\n # and serves the composable path.\n checkCudaErrors(\n cuda_driver.cuMemsetD32Async(int(part.data_ptr()), 0, B * N_BA, stream)\n )\n\n # conv_state is a logical [P, QKV_DIM, CONV_STATE_LEN] view over either a\n # transposed SD pool (stride-1 channels, vLLM default) or a DS-dense pool\n # (stride-1 time steps); pick the matching leading dim and compile one\n # variant per layout (indexing is stride-generic, only the layout's\n # static stride-1 mode differs).\n cs_ld = conv_state_leading_dim(conv_state)\n\n key = (geometry, B, scale_f, cs_ld)\n fn = _compiled.get(key)\n if fn is None:\n # The DLPack markers exist only to describe the argument layouts to\n # cute.compile; the compiled kernel is invoked with the torch tensors\n # themselves. Building them on a warm call would be thirteen\n # from_dlpack round-trips of pure host overhead per decode step per\n # layer, so they are built only on the compiling call.\n m_hidden = from_dlpack(hidden_states, enable_tvm_ffi=True).mark_layout_dynamic()\n m_wba = from_dlpack(w_ba, enable_tvm_ffi=True).mark_layout_dynamic()\n m_qkv = from_dlpack(mixed_qkv, enable_tvm_ffi=True).mark_layout_dynamic()\n m_cw = from_dlpack(conv_weight, enable_tvm_ffi=True).mark_layout_dynamic()\n m_cb = from_dlpack(conv_bias, enable_tvm_ffi=True).mark_layout_dynamic()\n m_cs = from_dlpack(conv_state, enable_tvm_ffi=True).mark_layout_dynamic(\n leading_dim=cs_ld\n )\n m_alog = from_dlpack(A_log, enable_tvm_ffi=True).mark_layout_dynamic()\n m_dtb = from_dlpack(dt_bias, enable_tvm_ffi=True).mark_layout_dynamic()\n m_ssm = from_dlpack(ssm_state, enable_tvm_ffi=True).mark_layout_dynamic()\n m_si = from_dlpack(state_indices, enable_tvm_ffi=True).mark_layout_dynamic()\n m_out = from_dlpack(output, enable_tvm_ffi=True).mark_layout_dynamic()\n m_qa = from_dlpack(qkv_act, enable_tvm_ffi=True).mark_layout_dynamic()\n m_part = from_dlpack(part, enable_tvm_ffi=True).mark_layout_dynamic()\n fn = cute.compile(\n fused_launch,\n m_hidden,\n m_wba,\n m_qkv,\n m_cw,\n m_cb,\n m_cs,\n m_alog,\n m_dtb,\n m_ssm,\n m_si,\n m_out,\n m_qa,\n m_part,\n stream,\n B,\n scale_f,\n HIDDEN,\n N_BA,\n QKV_DIM,\n H_Q,\n HV,\n D,\n options=\"--enable-tvm-ffi\",\n )\n _compiled[key] = fn\n fn(\n hidden_states,\n w_ba,\n mixed_qkv,\n conv_weight,\n conv_bias,\n conv_state,\n A_log,\n dt_bias,\n ssm_state,\n state_indices,\n output,\n qkv_act,\n part,\n stream,\n )\n _launch_count += 1\n return output, conv_state, ssm_state\n\n\ndef launch_count() -> int:\n \"\"\"Host-side dispatches so far (a CUDA-graph capture counts once).\"\"\"\n return _launch_count\n\n\ndef _geometry_tag(geometry: tuple) -> str:\n hidden, n_ba, qkv_dim, h_q, hv, d = geometry\n return f\"h{hidden}_nba{n_ba}_qkv{qkv_dim}_hq{h_q}_hv{hv}_d{d}\"\n\n\ndef compiled_variant_keys() -> list:\n \"\"\"Compiled-kernel descriptors resident in this process.\"\"\"\n return [\n f\"{_geometry_tag(geometry)}_b{B}_scale{scale}_ld{leading_dim}\"\n for (geometry, B, scale, leading_dim) in sorted(_compiled)\n ]\n\n\ndef variant_plan(rows) -> set:\n \"\"\"Distinct compiled kernels this impl needs for its registry rows: one\n per (layer geometry, batch size, conv-state layout). The query scale is\n also part of the compile key but is a runtime value (a serving process\n uses one scale), so the plan counts (geometry, b, conv_layout) triples.\"\"\"\n return {\n f\"{_geometry_tag(geometry_key(row))}_b{row['b']}_{row['conv_layout']}\"\n for row in rows\n }\n"},"diff":{"kind":"string","value":"--- flashinfer/gdn_kernels/experimental/kernel/gdn_fused_decode_cutedsl_sm120_pdl.py\n+++ flashinfer/gdn_kernels/experimental/kernel/gdn_fused_decode_cutedsl_sm120_pdl.py\n@@ -18,8 +18,8 @@\n \n Host and kernel side of the ``cutedsl_sm120_pdl`` registry impl: a\n two-launch CuTe-DSL implementation of the fused GDN decode step, compiled\n-per (batch, scale, conv-state layout) and launched on the current torch\n-stream. The conv-state pool arrives as a logical [P, QKV_DIM,\n+per (layer geometry, batch, scale, conv-state layout) and launched on the\n+current torch stream. The conv-state pool arrives as a logical [P, QKV_DIM,\n CONV_STATE_LEN] view of either a transposed SD pool (vLLM default) or a\n DS-dense pool; indexing is stride-generic, so the layouts differ only in\n which mode carries the static unit stride. The first launch\n@@ -30,10 +30,10 @@\n :func:`pre_kernel` and pinned by ``tests/gdn/test_fused_decode.py``.\n \n Implements the impl-module interface documented in ../README.md.\n-Compilation is lazy: the first eager :func:`execute` of a (batch, scale,\n-conv-state layout) variant compiles it and allocates the per-(batch,\n-device) workspace; once warm, calls are capture-safe (kernel launches plus\n-one stream memset). Consumed by\n+Compilation is lazy: the first eager :func:`execute` of a (geometry, batch,\n+scale, conv-state layout) variant compiles it and allocates the\n+per-(geometry, batch, device) workspace; once warm, calls are capture-safe\n+(kernel launches plus one stream memset). Consumed by\n :mod:`flashinfer.gdn_kernels.experimental.gdn_fused_decode_specialized`;\n import errors are tolerated there (the cutlass DSL dependency stays\n optional).\n@@ -50,21 +50,49 @@\n from ....cuda_utils import checkCudaErrors\n from ._stream_order import order_after_previous_stream\n \n-HIDDEN = 5120\n-N_BA = 96\n-QKV_DIM = 10240\n-H_Q = 16\n-HV = 48\n-D = 128\n-CONV_WIDTH = 4\n-CONV_STATE_LEN = 3\n-GQA = HV // H_Q # 3\n+# The layer geometry (HIDDEN, N_BA, QKV_DIM, H_Q, HV, D) is a compile-time\n+# parameter: it is passed down as ``cutlass.Constexpr`` and baked into the\n+# kernel exactly as a module constant would be, so one variant is compiled\n+# per (geometry, batch, scale, conv-state layout). The block shape, the\n+# warp->row mapping and the reduction trees do not depend on it; only the\n+# sizes and the derived tile counts do.\n RPB = 8 # v-rows per block in delta kernel (8 warps = 256 thr)\n-NRB = D // RPB # row-blocks per head = 16\n KS = 512 # K-split factor for the GEMV (atomic fp32 partials)\n-KCHUNK = HIDDEN // KS # 10\n-\n-NCONV = QKV_DIM // 256 # conv tiles per batch = 40\n+CONV_TILE = 256 # conv channels per block (== block threads)\n+\n+\n+def _derived(hidden: int, qkv_dim: int, hv: int, h_q: int, d: int) -> tuple:\n+ \"\"\"Tile counts derived from a geometry: (GQA, NRB, KCHUNK, NCONV).\n+\n+ Every division here is exact for a supported geometry; the dispatch\n+ registry only lists geometries that satisfy these relations (asserted in\n+ :func:`_check_geometry`).\n+ \"\"\"\n+ return (hv // h_q, d // RPB, hidden // KS, qkv_dim // CONV_TILE)\n+\n+\n+def _check_geometry(hidden: int, n_ba: int, qkv_dim: int, h_q: int, hv: int, d: int):\n+ \"\"\"Reject a geometry whose tiling would not be exact.\n+\n+ The registry is the dispatch surface, so this is a guard against a bad\n+ row rather than a runtime condition; it raises, and the dispatch layer\n+ turns that into a fallback.\n+ \"\"\"\n+ if (\n+ hv % h_q\n+ or d % RPB\n+ or hidden % KS\n+ or qkv_dim % CONV_TILE\n+ or n_ba != 2 * hv\n+ or d != 4 * 32\n+ or qkv_dim != (2 * h_q + hv) * d\n+ or n_ba > CONV_TILE\n+ ):\n+ raise RuntimeError(\n+ \"unsupported fused GDN decode geometry for the CuTe-DSL impl: \"\n+ f\"hidden={hidden} n_ba={n_ba} qkv_dim={qkv_dim} h_q={h_q} \"\n+ f\"hv={hv} d={d}\"\n+ )\n \n \n # ---------------------------------------------------------------------------\n@@ -143,6 +171,9 @@\n w_ba: cute.Tensor, # [HIDDEN, N_BA] bf16\n part: cute.Tensor, # [B, N_BA] f32, zeroed before launch\n Bc: cutlass.Constexpr,\n+ N_BA: cutlass.Constexpr,\n+ NCONV: cutlass.Constexpr,\n+ KCHUNK: cutlass.Constexpr,\n ):\n \"\"\"First of the two launches: conv1d state update and the b/a GEMV.\n \n@@ -179,7 +210,7 @@\n if bidx < Bc * NCONV:\n b_idx = bidx // NCONV\n tile = bidx % NCONV\n- c = tile * 256 + tidx\n+ c = tile * CONV_TILE + tidx\n pp = cutlass.Int32(state_indices[b_idx])\n # A negative slot index (vLLM's PAD_SLOT_ID = -1) marks a padded batch\n # row -- what a CUDA-graph replay carries between the live request\n@@ -235,6 +266,11 @@\n state_indices: cute.Tensor, # [B] int32\n output: cute.Tensor, # [B, 1, HV, D] bf16\n scale: cutlass.Constexpr,\n+ H_Q: cutlass.Constexpr,\n+ HV: cutlass.Constexpr,\n+ D: cutlass.Constexpr,\n+ GQA: cutlass.Constexpr,\n+ NRB: cutlass.Constexpr,\n ):\n \"\"\"Second launch: gates, qk-L2-norm and the gated delta-rule update.\n \n@@ -433,11 +469,18 @@\n stream: cuda_driver.CUstream,\n B: cutlass.Constexpr,\n scale: cutlass.Constexpr,\n+ HIDDEN: cutlass.Constexpr,\n+ N_BA: cutlass.Constexpr,\n+ QKV_DIM: cutlass.Constexpr,\n+ H_Q: cutlass.Constexpr,\n+ HV: cutlass.Constexpr,\n+ D: cutlass.Constexpr,\n ):\n \"\"\"Host-side launcher: ``pre_kernel`` then ``delta_kernel``, PDL-chained.\n \n- Compiled once per (batch size, scale, conv-state stride mode); ``B`` and\n- ``scale`` are constexpr because both shape the generated code.\n+ Compiled once per (layer geometry, batch size, scale, conv-state stride\n+ mode); ``B``, ``scale`` and the geometry are constexpr because all of\n+ them shape the generated code.\n \n ``use_pdl=True`` on BOTH launches is a promise about the kernels, not just\n a scheduling hint: each of them may start before its stream predecessor has\n@@ -445,6 +488,7 @@\n reading what a predecessor produced. Do not add a third PDL launch here\n without reading the contract block above ``pre_kernel``.\n \"\"\"\n+ GQA, NRB, KCHUNK, NCONV = _derived(HIDDEN, QKV_DIM, HV, H_Q, D)\n pre_kernel(\n mixed_qkv,\n conv_weight,\n@@ -456,8 +500,14 @@\n w_ba,\n part,\n B,\n+ N_BA,\n+ NCONV,\n+ KCHUNK,\n ).launch(\n- grid=[B * NCONV + B * KS, 1, 1], block=[256, 1, 1], stream=stream, use_pdl=True\n+ grid=[B * NCONV + B * KS, 1, 1],\n+ block=[CONV_TILE, 1, 1],\n+ stream=stream,\n+ use_pdl=True,\n )\n delta_kernel(\n qkv_act,\n@@ -468,22 +518,34 @@\n state_indices,\n output,\n scale,\n- ).launch(grid=[B * HV * NRB, 1, 1], block=[256, 1, 1], stream=stream, use_pdl=True)\n-\n-\n-# Keyed by the three things that change the generated kernel -- batch size,\n-# the softmax scale baked in as a constant, and the conv-state stride mode --\n-# and, for the workspace, by (batch size, device). The compiled-kernel value\n-# is whatever ``cute.compile`` returns, which has no public static type.\n-_compiled: dict[tuple[int, float, int], Any] = {}\n-_workspace_cache: dict[tuple[int, str], tuple[torch.Tensor, torch.Tensor]] = {}\n+ H_Q,\n+ HV,\n+ D,\n+ GQA,\n+ NRB,\n+ ).launch(\n+ grid=[B * HV * NRB, 1, 1],\n+ block=[RPB * 32, 1, 1], # one warp per state row block\n+ stream=stream,\n+ use_pdl=True,\n+ )\n+\n+\n+# Keyed by the four things that change the generated kernel -- the layer\n+# geometry, batch size, the softmax scale baked in as a constant, and the\n+# conv-state stride mode -- and, for the workspace, by (geometry, batch size,\n+# device). The compiled-kernel value is whatever ``cute.compile`` returns,\n+# which has no public static type.\n+_compiled: dict[tuple[tuple, int, float, int], Any] = {}\n+_workspace_cache: dict[tuple[tuple, int, str], tuple[torch.Tensor, torch.Tensor]] = {}\n _launch_count = 0\n \n-# Stream that last used the per-(batch, device) workspace, per device. The\n-# workspace (``part``/``qkv_act``) is shared by every call with that batch\n-# size, so two calls in flight on different streams would interleave writes\n-# into the same buffers; order_after_previous_stream() (see _stream_order.py)\n-# makes the later call wait on the earlier one instead.\n+# Stream that last used the per-(geometry, batch, device) workspace, per\n+# device. The workspace (``part``/``qkv_act``) is shared by every call with\n+# that geometry and batch size, so two calls in flight on different streams\n+# would interleave writes into the same buffers;\n+# order_after_previous_stream() (see _stream_order.py) makes the later call\n+# wait on the earlier one instead.\n _workspace_stream: dict[str, torch.cuda.Stream] = {}\n \n \n@@ -494,24 +556,52 @@\n return 1 if conv_state.stride(1) == 1 else 2\n \n \n+def geometry_key(signature: dict) -> tuple:\n+ \"\"\"Compile-time geometry key of a dispatch signature.\"\"\"\n+ return (\n+ int(signature[\"hidden\"]),\n+ int(signature[\"n_ba\"]),\n+ int(signature[\"qkv_dim\"]),\n+ int(signature[\"h_q\"]),\n+ int(signature[\"hv\"]),\n+ int(signature[\"d\"]),\n+ )\n+\n+\n def _cache_has(\n- B: int, scale: float, device: torch.device, conv_leading_dim: int = 1\n+ geometry: tuple,\n+ B: int,\n+ scale: float,\n+ device: torch.device,\n+ conv_leading_dim: int = 1,\n ) -> bool:\n- \"\"\"True if the (B, scale, conv-state layout) variant is compiled AND the\n- per-(B, device) workspace exists — i.e. a call is capture-safe (kernel\n- launches plus one stream memset, no compilation or allocation).\"\"\"\n- return (int(B), float(scale), int(conv_leading_dim)) in _compiled and (\n+ \"\"\"True if the (geometry, B, scale, conv-state layout) variant is compiled\n+ AND the per-(geometry, B, device) workspace exists — i.e. a call is\n+ capture-safe (kernel launches plus one stream memset, no compilation or\n+ allocation).\"\"\"\n+ return (geometry, int(B), float(scale), int(conv_leading_dim)) in _compiled and (\n+ geometry,\n int(B),\n str(device),\n ) in _workspace_cache\n \n \n def ready_for_graph_capture(\n- hidden_states: torch.Tensor, conv_state: torch.Tensor, scale: float\n+ signature: dict,\n+ hidden_states: torch.Tensor,\n+ conv_state: torch.Tensor,\n+ scale: float,\n ) -> bool:\n- \"\"\"True when this exact call (batch size, scale, conv-state layout) can\n- be recorded into a CUDA graph without compiling or allocating.\"\"\"\n+ \"\"\"True when this exact call (geometry, batch size, scale, conv-state\n+ layout) can be recorded into a CUDA graph without compiling or\n+ allocating.\n+\n+ The geometry comes from the matched dispatch signature rather than being\n+ re-derived here: readiness must be answered about the exact compiled\n+ variant the dispatcher is about to run, so a process warm for one model\n+ cannot make a differently-shaped model's call look capture-ready.\"\"\"\n return _cache_has(\n+ geometry_key(signature),\n int(hidden_states.shape[0]),\n float(scale),\n hidden_states.device,\n@@ -543,6 +633,17 @@\n scale_f = float(scale)\n dev = hidden_states.device\n \n+ # Layer geometry of this call (the dispatch layer has already matched it\n+ # against the registry); h_q is derived from the q/k/v head split.\n+ HIDDEN = int(hidden_states.shape[1])\n+ N_BA = int(w_ba.shape[1])\n+ QKV_DIM = int(mixed_qkv.shape[1])\n+ HV = int(A_log.shape[0])\n+ D = int(ssm_state.shape[-1])\n+ H_Q = (QKV_DIM - HV * D) // (2 * D)\n+ _check_geometry(HIDDEN, N_BA, QKV_DIM, H_Q, HV, D)\n+ geometry = (HIDDEN, N_BA, QKV_DIM, H_Q, HV, D)\n+\n output = (\n out\n if out is not None\n@@ -552,7 +653,7 @@\n # Persistent workspace: the GEMV partials are accumulated with atomics, so\n # `part` is re-zeroed each call with a driver memset on the current stream\n # (no extra torch kernel launch; captured as a memset node under graphs).\n- wkey = (B, str(dev))\n+ wkey = (geometry, B, str(dev))\n workspace = _workspace_cache.get(wkey)\n if workspace is None:\n workspace = (\n@@ -584,7 +685,7 @@\n # static stride-1 mode differs).\n cs_ld = conv_state_leading_dim(conv_state)\n \n- key = (B, scale_f, cs_ld)\n+ key = (geometry, B, scale_f, cs_ld)\n fn = _compiled.get(key)\n if fn is None:\n # The DLPack markers exist only to describe the argument layouts to\n@@ -625,6 +726,12 @@\n stream,\n B,\n scale_f,\n+ HIDDEN,\n+ N_BA,\n+ QKV_DIM,\n+ H_Q,\n+ HV,\n+ D,\n options=\"--enable-tvm-ffi\",\n )\n _compiled[key] = fn\n@@ -653,17 +760,25 @@\n return _launch_count\n \n \n+def _geometry_tag(geometry: tuple) -> str:\n+ hidden, n_ba, qkv_dim, h_q, hv, d = geometry\n+ return f\"h{hidden}_nba{n_ba}_qkv{qkv_dim}_hq{h_q}_hv{hv}_d{d}\"\n+\n+\n def compiled_variant_keys() -> list:\n \"\"\"Compiled-kernel descriptors resident in this process.\"\"\"\n return [\n- f\"b{B}_scale{scale}_ld{leading_dim}\"\n- for (B, scale, leading_dim) in sorted(_compiled)\n+ f\"{_geometry_tag(geometry)}_b{B}_scale{scale}_ld{leading_dim}\"\n+ for (geometry, B, scale, leading_dim) in sorted(_compiled)\n ]\n \n \n def variant_plan(rows) -> set:\n \"\"\"Distinct compiled kernels this impl needs for its registry rows: one\n- per (batch size, conv-state layout). The query scale is also part of\n- the compile key but is a runtime value (a serving process uses one\n- scale), so the plan counts (b, conv_layout) pairs.\"\"\"\n- return {f\"b{row['b']}_{row['conv_layout']}\" for row in rows}\n+ per (layer geometry, batch size, conv-state layout). The query scale is\n+ also part of the compile key but is a runtime value (a serving process\n+ uses one scale), so the plan counts (geometry, b, conv_layout) triples.\"\"\"\n+ return {\n+ f\"{_geometry_tag(geometry_key(row))}_b{row['b']}_{row['conv_layout']}\"\n+ for row in rows\n+ }"},"lines_added":{"kind":"number","value":168,"string":"168"},"lines_removed":{"kind":"number","value":53,"string":"53"},"files_in_commit":{"kind":"number","value":6,"string":"6"},"models_mentioned":{"kind":"list like","value":["qwen"],"string":"[\n \"qwen\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["SM120"],"string":"[\n \"SM120\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cute_dsl kernel file from flashinfer (flashinfer/gdn_kernels/experimental/kernel/gdn_fused_decode_cutedsl_sm120_pdl.py).\n\nGoal: (perf) add fused_GDN_step support for Qwen 3.6 35B A3B on sm120\nTarget hardware: SM120\nTarget models: qwen\n\nCurrent file:\n```python\n\"\"\"\nCopyright (c) 2026 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nFused GDN Decode Step - two-launch CuTe-DSL impl with PDL (SM120)\n=================================================================\n\nHost and kernel side of the ``cutedsl_sm120_pdl`` registry impl: a\ntwo-launch CuTe-DSL implementation of the fused GDN decode step, compiled\nper (batch, scale, conv-state layout) and launched on the current torch\nstream. The conv-state pool arrives as a logical [P, QKV_DIM,\nCONV_STATE_LEN] view of either a transposed SD pool (vLLM default) or a\nDS-dense pool; indexing is stride-generic, so the layouts differ only in\nwhich mode carries the static unit stride. The first launch\nfuses the depthwise conv1d update with a heavily K-split b/a GEMV (fp32\npartials accumulated with device-scope atomics); the second applies the gated\ndelta rule. Both launches use programmatic dependent launch (PDL); the\nwait/trigger contract that makes that safe is stated in full above\n:func:`pre_kernel` and pinned by ``tests/gdn/test_fused_decode.py``.\n\nImplements the impl-module interface documented in ../README.md.\nCompilation is lazy: the first eager :func:`execute` of a (batch, scale,\nconv-state layout) variant compiles it and allocates the per-(batch,\ndevice) workspace; once warm, calls are capture-safe (kernel launches plus\none stream memset). Consumed by\n:mod:`flashinfer.gdn_kernels.experimental.gdn_fused_decode_specialized`;\nimport errors are tolerated there (the cutlass DSL dependency stays\noptional).\n\"\"\"\n\nfrom typing import Any\n\nimport torch\nimport cutlass\nimport cutlass.cute as cute\nimport cuda.bindings.driver as cuda_driver\nfrom cutlass.cute.runtime import from_dlpack\n\nfrom ....cuda_utils import checkCudaErrors\nfrom ._stream_order import order_after_previous_stream\n\nHIDDEN = 5120\nN_BA = 96\nQKV_DIM = 10240\nH_Q = 16\nHV = 48\nD = 128\nCONV_WIDTH = 4\nCONV_STATE_LEN = 3\nGQA = HV // H_Q # 3\nRPB = 8 # v-rows per block in delta kernel (8 warps = 256 thr)\nNRB = D // RPB # row-blocks per head = 16\nKS = 512 # K-split factor for the GEMV (atomic fp32 partials)\nKCHUNK = HIDDEN // KS # 10\n\nNCONV = QKV_DIM // 256 # conv tiles per batch = 40\n\n\n# ---------------------------------------------------------------------------\n# PDL contract for this op -- read this before moving either griddepcontrol.\n# ---------------------------------------------------------------------------\n# Both launches carry ``use_pdl=True``\n# (CU_LAUNCH_ATTRIBUTE_PROGRAMMATIC_STREAM_SERIALIZATION), which tells the\n# driver it \"is safe to launch the secondary kernel early and not wait on the\n# completion and memory flush of the primary before launching the secondary\"\n# (CUDA programming guide, Programmatic Dependent Launch). Two DIFFERENT\n# hardware events then keep that safe, and conflating them is the way this\n# code goes wrong:\n#\n# griddepcontrol.launch_dependents -- a SCHEDULING gate only. PTX: the\n# designated dependents \"can be scheduled as soon as all other CTAs in\n# the grid issue the same instruction or have completed\". It publishes\n# nothing, orders nothing, and is not what a dependent's wait observes.\n# griddepcontrol.wait -- the VISIBILITY barrier. PTX: the thread waits\n# \"until all prerequisite grids in flight have completed and all the\n# memory operations from the prerequisite grids are performed and made\n# visible to the current grid\", i.e. until the predecessor grid's\n# grid-ending membar has drained. This, and only this, makes a read of\n# a predecessor's output legal.\n#\n# Who waits, who triggers, and what each ordering protects:\n#\n# pre_kernel WAITS FIRST, unconditionally, before its first global load and\n# before the conv/GEMV block split so that every block reaches it.\n# Everything it loads is produced by a stream predecessor -- mixed_qkv\n# and hidden by this layer's projections, state_indices by the caller's\n# metadata prep, conv_state by an earlier decode step, and ``part`` by\n# the cuMemsetD32Async this launch is queued behind. The launch\n# attribute above explicitly releases the driver from waiting on those,\n# so without this wait the op's correctness would rest on whether some\n# unrelated upstream kernel happens to fire a trigger -- a property this\n# op cannot see and must not depend on.\n# pre_kernel THEN TRIGGERS, in the same unconditional prologue. Order\n# matters and is not cosmetic: the trigger is what places delta_kernel's\n# CTAs on the SMs, and delta_kernel reads ssm_state BEFORE its own wait.\n# Triggering ahead of pre_kernel's wait would schedule delta while\n# pre_kernel is itself still unordered against its predecessors, and\n# delta's pre-wait prefetch would inherit exactly that -- no ordering\n# against whoever last wrote ssm_state/state_indices. Waiting first is\n# what hands the dependent an already-ordered state.\n# pre_kernel triggers HERE rather than after its stores on purpose. The\n# trigger does not publish qkv_act/part and is not what releases\n# delta_kernel's wait; delta's wait does not return until pre_kernel's\n# whole grid has completed and flushed, which covers every store in this\n# kernel wherever it sits. Firing at entry is what buys the overlap the\n# impl exists for (upstream's gdn_decode_bf16_wy_ucache_flush.py fires at\n# entry for the same reason). What it does cost is SM competition:\n# delta's CTAs are resident and parked on their wait while pre_kernel\n# runs. That trade is measured, not assumed -- see ../README.md.\n# delta_kernel WAITS in both arms of its padded-row branch, after the\n# ssm_state prefetch and before the first read of qkv_act/part. That\n# wait is the ordering that protects the conv output and the GEMV\n# partials.\n# delta_kernel does NOT trigger, so nothing downstream is scheduled early on\n# its account and its ssm_state/output stores need no further signal\n# here: a successor is scheduled at this grid's completion. Adding a\n# trigger to delta_kernel would be a performance change that also\n# obliges every PDL successor to wait -- do not add one without the\n# matching wait on the other side.\n#\n# Pinned by ``test_pdl_kernels_wait_before_their_first_launch_dependents`` and\n# ``test_every_pdl_kernel_waits_on_all_paths`` in tests/gdn/test_fused_decode.py.\n@cute.kernel\ndef pre_kernel(\n mixed_qkv: cute.Tensor, # [B, QKV_DIM] bf16\n conv_weight: cute.Tensor, # [QKV_DIM, CONV_WIDTH] bf16\n conv_bias: cute.Tensor, # [QKV_DIM] bf16\n conv_state: cute.Tensor, # [P, QKV_DIM, CONV_STATE_LEN] bf16 (in-place)\n state_indices: cute.Tensor, # [B] int32\n qkv_act: cute.Tensor, # [B, QKV_DIM] bf16 scratch\n hidden: cute.Tensor, # [B, HIDDEN] bf16\n w_ba: cute.Tensor, # [HIDDEN, N_BA] bf16\n part: cute.Tensor, # [B, N_BA] f32, zeroed before launch\n Bc: cutlass.Constexpr,\n):\n \"\"\"First of the two launches: conv1d state update and the b/a GEMV.\n\n One grid does both, since neither depends on the other: blocks\n ``[0, B*NCONV)`` shift the conv-state rows, append the new input and write\n the silu-activated conv output to ``qkv_act``; the remaining blocks\n accumulate K-split partials of ``hidden @ w_ba`` into ``part`` with\n gpu-scope atomics (hence the memset of ``part`` before the launch). It\n waits on its own stream predecessors and then signals PDL launch\n dependents up front, so ``delta_kernel``'s ``ssm_state`` prefetch overlaps\n this entire body -- see the PDL contract block above.\n \"\"\"\n # Combined conv + K-split GEMV in one launch. Blocks [0, B*NCONV) do conv;\n # blocks [B*NCONV, ...) accumulate GEMV partials with gpu-scope atomics.\n #\n # PDL prologue, above the block split so EVERY block runs both halves.\n # (1) Wait: this grid is launched with programmatic stream serialization,\n # so it may already be running while its predecessors are still draining.\n # Every global load below -- state_indices, conv_state, mixed_qkv, hidden,\n # the weights, and the atomics into the freshly memset `part` -- reads what\n # those predecessors produced, so this is the barrier that makes them\n # legal, not an optimization.\n cute.arch.griddepcontrol_wait()\n # (2) Only then release delta_kernel onto the SMs, so its long-latency\n # ssm_state prefetch overlaps this whole body. Never before the wait:\n # delta reads global memory before its own wait and would inherit this\n # grid's unordered state. This does not publish anything -- delta's wait\n # covers pre_kernel's stores wherever they sit.\n cute.arch.griddepcontrol_launch_dependents()\n\n tidx, _, _ = cute.arch.thread_idx()\n bidx, _, _ = cute.arch.block_idx()\n\n if bidx < Bc * NCONV:\n b_idx = bidx // NCONV\n tile = bidx % NCONV\n c = tile * 256 + tidx\n pp = cutlass.Int32(state_indices[b_idx])\n # A negative slot index (vLLM's PAD_SLOT_ID = -1) marks a padded batch\n # row -- what a CUDA-graph replay carries between the live request\n # count and the captured batch size. It owns no conv-state row, so\n # neither read nor write one for it; ``delta_kernel`` skips the same\n # row and zeroes its output. The predicate depends only on ``bidx``,\n # so it is block-uniform: one taken branch per block, not divergence.\n # ``qkv_act`` is left untouched for such a row -- it is per-call\n # scratch that only the skipped delta blocks would read.\n if pp >= 0:\n st0_bf = conv_state[pp, c, 0]\n st1_bf = conv_state[pp, c, 1]\n st2_bf = conv_state[pp, c, 2]\n st0 = st0_bf.to(cutlass.Float32)\n st1 = st1_bf.to(cutlass.Float32)\n st2 = st2_bf.to(cutlass.Float32)\n xbf = mixed_qkv[b_idx, c]\n xx = xbf.to(cutlass.Float32)\n w0 = conv_weight[c, 0].to(cutlass.Float32)\n w1 = conv_weight[c, 1].to(cutlass.Float32)\n w2 = conv_weight[c, 2].to(cutlass.Float32)\n w3 = conv_weight[c, 3].to(cutlass.Float32)\n bb = conv_bias[c].to(cutlass.Float32)\n y = cutlass.Float32(st0 * w0 + st1 * w1 + st2 * w2 + xx * w3 + bb)\n ey = cute.math.exp(cutlass.Float32(-y), fastmath=False)\n yv = cutlass.Float32(y / cutlass.Float32(cutlass.Float32(1.0) + ey))\n qkv_act[b_idx, c] = yv.to(cutlass.BFloat16)\n conv_state[pp, c, 0] = st1_bf\n conv_state[pp, c, 1] = st2_bf\n conv_state[pp, c, 2] = xbf\n else:\n g = bidx - Bc * NCONV\n b_idx = g // KS\n ks = g % KS\n n = tidx\n if n < N_BA:\n base = ks * KCHUNK\n acc = cutlass.Float32(0.0)\n for i in cutlass.range_constexpr(KCHUNK):\n gi = base + i\n hv = hidden[b_idx, gi].to(cutlass.Float32)\n acc = acc + hv * w_ba[gi, n].to(cutlass.Float32)\n cute.arch.atomic_add(part.iterator + (b_idx * N_BA + n), acc, scope=\"gpu\")\n\n\n@cute.kernel\ndef delta_kernel(\n qkv_act: cute.Tensor, # [B, QKV_DIM] bf16\n part: cute.Tensor, # [B, N_BA] f32\n A_log: cute.Tensor, # [HV] f32\n dt_bias: cute.Tensor, # [HV] bf16\n ssm_state: cute.Tensor, # [P, HV, D, D] f32 (in-place)\n state_indices: cute.Tensor, # [B] int32\n output: cute.Tensor, # [B, 1, HV, D] bf16\n scale: cutlass.Constexpr,\n):\n \"\"\"Second launch: gates, qk-L2-norm and the gated delta-rule update.\n\n One warp owns one ``ssm_state`` row: it prefetches the row before waiting\n on PDL (``pre_kernel`` never touches ``ssm_state``, so the long-latency\n fp32 loads overlap the whole first kernel), reduces the b/a GEMV partials\n into the beta and decay gates, and writes the updated row back in place\n plus this row's slice of the attention output.\n \"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n bidx, _, _ = cute.arch.block_idx()\n hh = bidx // NRB # global head index (b_idx*HV + h)\n rb = bidx % NRB # row-block within head\n b_idx = hh // HV\n h = hh % HV\n qhd = h // GQA\n warp = tidx // 32\n lane = tidx % 32\n v = rb * RPB + warp # ssm row index this warp owns\n\n # Second global read issued before this kernel's PDL wait (with the\n # ssm_state prefetch below). pre_kernel does not write state_indices;\n # ordering against whoever did is inherited from pre_kernel waiting before\n # it triggers -- see the PDL contract block at the top of this file.\n pp = cutlass.Int32(state_indices[b_idx])\n\n # A negative slot index (vLLM's PAD_SLOT_ID = -1) marks a padded batch\n # row: it owns no pool slot, so neither state pool may be read or written\n # for it and its output row is zero -- the same contract the fp32 path of\n # gated_delta_rule_decode_pretranspose already documents. The predicate\n # depends only on bidx, so it is block-uniform: one taken branch per\n # block, and the warp-wide shuffles below are never reached under a\n # partial mask. Both arms wait on PDL: the padded arm reads nothing\n # pre_kernel wrote and would be correct without it, but keeping the wait\n # uniform across blocks keeps the launch's dependency semantics simple.\n if pp >= 0:\n # fp32 state loads issued before the PDL wait: pre_kernel never writes\n # ssm_state, so these long-latency loads overlap its whole body. What\n # orders them against the PREVIOUS step's writer of ssm_state is\n # pre_kernel waiting before it triggers: this grid cannot be scheduled\n # until pre_kernel has released it, and pre_kernel only releases after\n # its own wait has drained the predecessors. Keep that order there.\n k0 = lane\n k1 = lane + 32\n k2 = lane + 64\n k3 = lane + 96\n sv0 = ssm_state[pp, h, v, k0]\n sv1 = ssm_state[pp, h, v, k1]\n sv2 = ssm_state[pp, h, v, k2]\n sv3 = ssm_state[pp, h, v, k3]\n\n cute.arch.griddepcontrol_wait()\n\n qbase = qhd * D\n kbase = H_Q * D + qhd * D\n q0 = qkv_act[b_idx, qbase + k0].to(cutlass.Float32)\n q1 = qkv_act[b_idx, qbase + k1].to(cutlass.Float32)\n q2 = qkv_act[b_idx, qbase + k2].to(cutlass.Float32)\n q3 = qkv_act[b_idx, qbase + k3].to(cutlass.Float32)\n kk0 = qkv_act[b_idx, kbase + k0].to(cutlass.Float32)\n kk1 = qkv_act[b_idx, kbase + k1].to(cutlass.Float32)\n kk2 = qkv_act[b_idx, kbase + k2].to(cutlass.Float32)\n kk3 = qkv_act[b_idx, kbase + k3].to(cutlass.Float32)\n vvv = qkv_act[b_idx, 2 * H_Q * D + h * D + v].to(cutlass.Float32)\n\n # Redundant per-thread gate computation (no smem/sync needed). The fp32\n # gate sums round through bf16 to match the composable path's GEMV output\n # dtype before the sigmoid/softplus gates.\n b_sum = part[b_idx, h]\n a_sum = part[b_idx, HV + h]\n b_bf = b_sum.to(cutlass.BFloat16).to(cutlass.Float32)\n a_bf = a_sum.to(cutlass.BFloat16).to(cutlass.Float32)\n eb = cute.math.exp(cutlass.Float32(-b_bf), fastmath=False)\n beta = cutlass.Float32(1.0) / cutlass.Float32(cutlass.Float32(1.0) + eb)\n dtb = dt_bias[h].to(cutlass.Float32)\n x = cutlass.Float32(a_bf + dtb)\n # softplus via the overflow-free identity\n # softplus(x) = max(x, 0) + log(1 + exp(-|x|)),\n # branch-free. The naive log(1 + exp(x)) sends exp(x) to +inf for\n # x > ~88.7 in fp32, which collapses the decay gate to exactly 0 instead\n # of exp(-exp(A_log) * x) -- a silently wrong gate whenever exp(A_log) is\n # small enough for the true gate to stay O(1). The identity agrees with\n # torch.nn.functional.softplus (threshold=20, i.e. the composable path)\n # and with the CUDA impl's `x > 20 ? x : log1p(exp(x))` to fp32 rounding\n # over the whole range: worst case 1e-6 on the resulting gate, three\n # orders below the bf16 tolerance the correctness tests use.\n #\n # ``max(x, 0)`` is built out of ``absf`` rather than a max primitive on\n # purpose. ``cute.math`` only gained ``max`` in nvidia-cutlass-dsl 4.6,\n # where the module became a re-export of ``cutlass._mlir_helpers.math``;\n # 4.5's hand-written ``cute.math`` exports 19 names and ``max`` is not\n # among them, so ``cute.math.max`` raises AttributeError there. ``absf``\n # is in every release this repo supports -- 4.5 defines it, and 4.6+\n # deliberately keeps ``absf`` as an alias of the new ``abs``. The\n # supported set is pinned by\n # ``test_cutedsl_impl_only_uses_portable_cute_math_primitives``.\n #\n # max(x, 0) == 0.5*x + 0.5*|x|\n #\n # exact in fp32 for either sign (halving is exact and the two halves are\n # either equal or exact opposites) and, unlike ``0.5*(x + |x|)``, free of\n # the overflow that doubling a large x would introduce.\n x_abs = cute.math.absf(x, fastmath=False)\n x_pos = cutlass.Float32(cutlass.Float32(0.5) * x + cutlass.Float32(0.5) * x_abs)\n ex = cute.math.exp(cutlass.Float32(-x_abs), fastmath=False)\n sp = cutlass.Float32(\n x_pos\n + cute.math.log(cutlass.Float32(cutlass.Float32(1.0) + ex), fastmath=False)\n )\n eal = cute.math.exp(A_log[h], fastmath=False)\n arg = cutlass.Float32(-cutlass.Float32(eal * sp))\n g = cute.math.exp(arg, fastmath=False)\n\n qsq = cutlass.Float32(q0 * q0 + q1 * q1 + q2 * q2 + q3 * q3)\n ksq = cutlass.Float32(kk0 * kk0 + kk1 * kk1 + kk2 * kk2 + kk3 * kk3)\n qsq = qsq + cute.arch.shuffle_sync_bfly(qsq, 16)\n qsq = qsq + cute.arch.shuffle_sync_bfly(qsq, 8)\n qsq = qsq + cute.arch.shuffle_sync_bfly(qsq, 4)\n qsq = qsq + cute.arch.shuffle_sync_bfly(qsq, 2)\n qsq = qsq + cute.arch.shuffle_sync_bfly(qsq, 1)\n ksq = ksq + cute.arch.shuffle_sync_bfly(ksq, 16)\n ksq = ksq + cute.arch.shuffle_sync_bfly(ksq, 8)\n ksq = ksq + cute.arch.shuffle_sync_bfly(ksq, 4)\n ksq = ksq + cute.arch.shuffle_sync_bfly(ksq, 2)\n ksq = ksq + cute.arch.shuffle_sync_bfly(ksq, 1)\n q_rms = cute.math.rsqrt(\n cutlass.Float32(qsq + cutlass.Float32(1e-6)), fastmath=False\n )\n k_rms = cute.math.rsqrt(\n cutlass.Float32(ksq + cutlass.Float32(1e-6)), fastmath=False\n )\n qn0 = cutlass.Float32(q0 * q_rms)\n qn1 = cutlass.Float32(q1 * q_rms)\n qn2 = cutlass.Float32(q2 * q_rms)\n qn3 = cutlass.Float32(q3 * q_rms)\n kn0 = cutlass.Float32(kk0 * k_rms)\n kn1 = cutlass.Float32(kk1 * k_rms)\n kn2 = cutlass.Float32(kk2 * k_rms)\n kn3 = cutlass.Float32(kk3 * k_rms)\n\n ov = cutlass.Float32(\n kn0 * cutlass.Float32(g * sv0)\n + kn1 * cutlass.Float32(g * sv1)\n + kn2 * cutlass.Float32(g * sv2)\n + kn3 * cutlass.Float32(g * sv3)\n )\n ov = ov + cute.arch.shuffle_sync_bfly(ov, 16)\n ov = ov + cute.arch.shuffle_sync_bfly(ov, 8)\n ov = ov + cute.arch.shuffle_sync_bfly(ov, 4)\n ov = ov + cute.arch.shuffle_sync_bfly(ov, 2)\n ov = ov + cute.arch.shuffle_sync_bfly(ov, 1)\n old_v = ov # all lanes hold the sum\n new_v = cutlass.Float32(\n beta * vvv + cutlass.Float32(cutlass.Float32(1.0) - beta) * old_v\n )\n d = cutlass.Float32(new_v - old_v)\n\n hs0 = cutlass.Float32(g * sv0 + kn0 * d)\n hs1 = cutlass.Float32(g * sv1 + kn1 * d)\n hs2 = cutlass.Float32(g * sv2 + kn2 * d)\n hs3 = cutlass.Float32(g * sv3 + kn3 * d)\n ssm_state[pp, h, v, k0] = hs0\n ssm_state[pp, h, v, k1] = hs1\n ssm_state[pp, h, v, k2] = hs2\n ssm_state[pp, h, v, k3] = hs3\n outp = cutlass.Float32(qn0 * hs0 + qn1 * hs1 + qn2 * hs2 + qn3 * hs3)\n outp = outp + cute.arch.shuffle_sync_bfly(outp, 16)\n outp = outp + cute.arch.shuffle_sync_bfly(outp, 8)\n outp = outp + cute.arch.shuffle_sync_bfly(outp, 4)\n outp = outp + cute.arch.shuffle_sync_bfly(outp, 2)\n outp = outp + cute.arch.shuffle_sync_bfly(outp, 1)\n if lane == 0:\n out_v = cutlass.Float32(outp * cutlass.Float32(scale))\n output[b_idx, 0, h, v] = out_v.to(cutlass.BFloat16)\n else:\n cute.arch.griddepcontrol_wait()\n if lane == 0:\n output[b_idx, 0, h, v] = cutlass.BFloat16(0.0)\n\n\n@cute.jit\ndef fused_launch(\n hidden,\n w_ba,\n mixed_qkv,\n conv_weight,\n conv_bias,\n conv_state,\n A_log,\n dt_bias,\n ssm_state,\n state_indices,\n output,\n qkv_act,\n part,\n stream: cuda_driver.CUstream,\n B: cutlass.Constexpr,\n scale: cutlass.Constexpr,\n):\n \"\"\"Host-side launcher: ``pre_kernel`` then ``delta_kernel``, PDL-chained.\n\n Compiled once per (batch size, scale, conv-state stride mode); ``B`` and\n ``scale`` are constexpr because both shape the generated code.\n\n ``use_pdl=True`` on BOTH launches is a promise about the kernels, not just\n a scheduling hint: each of them may start before its stream predecessor has\n completed and flushed, so each must issue ``griddepcontrol_wait()`` before\n reading what a predecessor produced. Do not add a third PDL launch here\n without reading the contract block above ``pre_kernel``.\n \"\"\"\n pre_kernel(\n mixed_qkv,\n conv_weight,\n conv_bias,\n conv_state,\n state_indices,\n qkv_act,\n hidden,\n w_ba,\n part,\n B,\n ).launch(\n grid=[B * NCONV + B * KS, 1, 1], block=[256, 1, 1], stream=stream, use_pdl=True\n )\n delta_kernel(\n qkv_act,\n part,\n A_log,\n dt_bias,\n ssm_state,\n state_indices,\n output,\n scale,\n ).launch(grid=[B * HV * NRB, 1, 1], block=[256, 1, 1], stream=stream, use_pdl=True)\n\n\n# Keyed by the three things that change the generated kernel -- batch size,\n# the softmax scale baked in as a constant, and the conv-state stride mode --\n# and, for the workspace, by (batch size, device). The compiled-kernel value\n# is whatever ``cute.compile`` returns, which has no public static type.\n_compiled: dict[tuple[int, float, int], Any] = {}\n_workspace_cache: dict[tuple[int, str], tuple[torch.Tensor, torch.Tensor]] = {}\n_launch_count = 0\n\n# Stream that last used the per-(batch, device) workspace, per device. The\n# workspace (``part``/``qkv_act``) is shared by every call with that batch\n# size, so two calls in flight on different streams would interleave writes\n# into the same buffers; order_after_previous_stream() (see _stream_order.py)\n# makes the later call wait on the earlier one instead.\n_workspace_stream: dict[str, torch.cuda.Stream] = {}\n\n\ndef conv_state_leading_dim(conv_state: torch.Tensor) -> int:\n \"\"\"Stride-1 mode of the logical [P, QKV_DIM, CONV_STATE_LEN] conv-state\n view: 1 for a transposed SD pool (vLLM default), 2 for a DS-dense pool.\n The dispatch gate has already validated the stride pattern.\"\"\"\n return 1 if conv_state.stride(1) == 1 else 2\n\n\ndef _cache_has(\n B: int, scale: float, device: torch.device, conv_leading_dim: int = 1\n) -> bool:\n \"\"\"True if the (B, scale, conv-state layout) variant is compiled AND the\n per-(B, device) workspace exists — i.e. a call is capture-safe (kernel\n launches plus one stream memset, no compilation or allocation).\"\"\"\n return (int(B), float(scale), int(conv_leading_dim)) in _compiled and (\n int(B),\n str(device),\n ) in _workspace_cache\n\n\ndef ready_for_graph_capture(\n hidden_states: torch.Tensor, conv_state: torch.Tensor, scale: float\n) -> bool:\n \"\"\"True when this exact call (batch size, scale, conv-state layout) can\n be recorded into a CUDA graph without compiling or allocating.\"\"\"\n return _cache_has(\n int(hidden_states.shape[0]),\n float(scale),\n hidden_states.device,\n conv_state_leading_dim(conv_state),\n )\n\n\ndef execute(\n hidden_states,\n w_ba,\n mixed_qkv,\n conv_weight,\n conv_bias,\n conv_state,\n A_log,\n dt_bias,\n scale,\n ssm_state,\n state_indices,\n out=None,\n):\n \"\"\"Run the fused step on the caller's current stream; raise on failure.\n\n The dispatch layer has already validated the call against the registry\n and the op contract. Both state pools are updated in place.\n \"\"\"\n global _launch_count\n B = int(hidden_states.shape[0])\n scale_f = float(scale)\n dev = hidden_states.device\n\n output = (\n out\n if out is not None\n else torch.empty((B, 1, HV, D), dtype=torch.bfloat16, device=dev)\n )\n\n # Persistent workspace: the GEMV partials are accumulated with atomics, so\n # `part` is re-zeroed each call with a driver memset on the current stream\n # (no extra torch kernel launch; captured as a memset node under graphs).\n wkey = (B, str(dev))\n workspace = _workspace_cache.get(wkey)\n if workspace is None:\n workspace = (\n torch.zeros((B, N_BA), dtype=torch.float32, device=dev),\n torch.empty((B, QKV_DIM), dtype=torch.bfloat16, device=dev),\n )\n _workspace_cache[wkey] = workspace\n part, qkv_act = workspace\n order_after_previous_stream(_workspace_stream, dev)\n # Take the stream from the tensors' device explicitly rather than from the\n # ambient one: the dispatcher makes that device current before calling in,\n # but an impl that reads torch.cuda.current_stream() with no argument would\n # silently follow the ambient device if that ever stopped being true.\n stream = cuda_driver.CUstream(torch.cuda.current_stream(dev).cuda_stream)\n # Checked, not fire-and-forget: `part` is the accumulator the K-split GEMV\n # atomically adds into, so a memset that did not run leaves the previous\n # step's partials in place and both gates are silently wrong -- exactly the\n # class of failure the impl attestation exists to make visible. Raising\n # instead hands the call to the dispatch layer, which latches this impl off\n # and serves the composable path.\n checkCudaErrors(\n cuda_driver.cuMemsetD32Async(int(part.data_ptr()), 0, B * N_BA, stream)\n )\n\n # conv_state is a logical [P, QKV_DIM, CONV_STATE_LEN] view over either a\n # transposed SD pool (stride-1 channels, vLLM default) or a DS-dense pool\n # (stride-1 time steps); pick the matching leading dim and compile one\n # variant per layout (indexing is stride-generic, only the layout's\n # static stride-1 mode differs).\n cs_ld = conv_state_leading_dim(conv_state)\n\n key = (B, scale_f, cs_ld)\n fn = _compiled.get(key)\n if fn is None:\n # The DLPack markers exist only to describe the argument layouts to\n # cute.compile; the compiled kernel is invoked with the torch tensors\n # themselves. Building them on a warm call would be thirteen\n # from_dlpack round-trips of pure host overhead per decode step per\n # layer, so they are built only on the compiling call.\n m_hidden = from_dlpack(hidden_states, enable_tvm_ffi=True).mark_layout_dynamic()\n m_wba = from_dlpack(w_ba, enable_tvm_ffi=True).mark_layout_dynamic()\n m_qkv = from_dlpack(mixed_qkv, enable_tvm_ffi=True).mark_layout_dynamic()\n m_cw = from_dlpack(conv_weight, enable_tvm_ffi=True).mark_layout_dynamic()\n m_cb = from_dlpack(conv_bias, enable_tvm_ffi=True).mark_layout_dynamic()\n m_cs = from_dlpack(conv_state, enable_tvm_ffi=True).mark_layout_dynamic(\n leading_dim=cs_ld\n )\n m_alog = from_dlpack(A_log, enable_tvm_ffi=True).mark_layout_dynamic()\n m_dtb = from_dlpack(dt_bias, enable_tvm_ffi=True).mark_layout_dynamic()\n m_ssm = from_dlpack(ssm_state, enable_tvm_ffi=True).mark_layout_dynamic()\n m_si = from_dlpack(state_indices, enable_tvm_ffi=True).mark_layout_dynamic()\n m_out = from_dlpack(output, enable_tvm_ffi=True).mark_layout_dynamic()\n m_qa = from_dlpack(qkv_act, enable_tvm_ffi=True).mark_layout_dynamic()\n m_part = from_dlpack(part, enable_tvm_ffi=True).mark_layout_dynamic()\n fn = cute.compile(\n fused_launch,\n m_hidden,\n m_wba,\n m_qkv,\n m_cw,\n m_cb,\n m_cs,\n m_alog,\n m_dtb,\n m_ssm,\n m_si,\n m_out,\n m_qa,\n m_part,\n stream,\n B,\n scale_f,\n options=\"--enable-tvm-ffi\",\n )\n _compiled[key] = fn\n fn(\n hidden_states,\n w_ba,\n mixed_qkv,\n conv_weight,\n conv_bias,\n conv_state,\n A_log,\n dt_bias,\n ssm_state,\n state_indices,\n output,\n qkv_act,\n part,\n stream,\n )\n _launch_count += 1\n return output, conv_state, ssm_state\n\n\ndef launch_count() -> int:\n \"\"\"Host-side dispatches so far (a CUDA-graph capture counts once).\"\"\"\n return _launch_count\n\n\ndef compiled_variant_keys() -> list:\n \"\"\"Compiled-kernel descriptors resident in this process.\"\"\"\n return [\n f\"b{B}_scale{scale}_ld{leading_dim}\"\n for (B, scale, leading_dim) in sorted(_compiled)\n ]\n\n\ndef variant_plan(rows) -> set:\n \"\"\"Distinct compiled kernels this impl needs for its registry rows: one\n per (batch size, conv-state layout). The query scale is also part of\n the compile key but is a runtime value (a serving process uses one\n scale), so the plan counts (b, conv_layout) pairs.\"\"\"\n return {f\"b{row['b']}_{row['conv_layout']}\" for row in rows}\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\nFollow up with #4481 \n - Adds Qwen3.6-35B-A3B support at batches 1/2/4 for both CUDA and CuTe-DSL implementations.\n - Generates one geometry-specific CUDA JIT module using FI_GDN_* compile definitions.\n - Passes geometry as cutlass.Constexpr to CuTe-DSL kernels.\n - Includes geometry in compiled-kernel, workspace, and CUDA Graph readiness cache keys.\n - Adds compile-time/static geometry checks to prevent invalid tiling.\n - Adds registry_geometries() for introspection and potential AOT iteration.\n - Expands tests across both geometries, both implementations, registry shape, invalid geometry rejection, JIT module uniqueness, and numerical equivalence.\n - Updates documentation for the multi-geometry registry and JIT/AOT behavior.\n - Removes the hypothetical FLASHINFER_QWEN_GDN_FUSED_DECODE_DISABLE test reference.\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [ ] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [ ] I have installed the hooks with `pre-commit install`.\n- [ ] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [ ] Tests have been added or updated as needed.\n- [ ] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc. -->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n* **New Features**\n * Added fused GDN decode support for an additional model configuration, including its supported decode batch sizes.\n * Kernel compilation, dispatch, caching, and CUDA graph capture now account for each layer geometry, batch size, scale, and layout.\n * Added validation for supported dimensions and tiling relationships, with fallback behavior for unsupported geometries.\n * Expanded supported workloads across both shipped geometries.\n\n* **Documentation**\n * Updated support, registry, CUDA graph, build, and model-integration guidance with expanded geometry requirements and configurations.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1079,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"75e834d633bc87267accc6e3f9749d18e459566a"},"date":{"kind":"string","value":"2026-08-25T09:23:27-07:00"},"pr_number":{"kind":"number","value":4708,"string":"4,708"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/4708"},"title":{"kind":"string","value":"(perf) add fused_GDN_step support for Qwen 3.6 35B A3B on sm120 (#4708)"},"message":{"kind":"string","value":"(perf) add fused_GDN_step support for Qwen 3.6 35B A3B on sm120 (#4708)\n\n<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\nFollow up with #4481 \n- Adds Qwen3.6-35B-A3B support at batches 1/2/4 for both CUDA and\nCuTe-DSL implementations.\n- Generates one geometry-specific CUDA JIT module using FI_GDN_* compile\ndefinitions.\n - Passes geometry as cutlass.Constexpr to CuTe-DSL kernels.\n- Includes geometry in compiled-kernel, workspace, and CUDA Graph\nreadiness cache keys.\n - Adds compile-time/static geometry checks to prevent invalid tiling.\n- Adds registry_geometries() for introspection and potential AOT\niteration.\n- Expands tests across both geometries, both implementations, registry\nshape, invalid geometry rejection, JIT module uniqueness, and numerical\nequivalence.\n- Updates documentation for the multi-geometry registry and JIT/AOT\nbehavior.\n- Removes the hypothetical FLASHINFER_QWEN_GDN_FUSED_DECODE_DISABLE test\nreference.\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [ ] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [ ] I have installed the hooks with `pre-commit install`.\n- [ ] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the\npre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [ ] Tests have been added or updated as needed.\n- [ ] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc.\n-->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n* **New Features**\n* Added fused GDN decode support for an additional model configuration,\nincluding its supported decode batch sizes.\n* Kernel compilation, dispatch, caching, and CUDA graph capture now\naccount for each layer geometry, batch size, scale, and layout.\n* Added validation for supported dimensions and tiling relationships,\nwith fallback behavior for unsupported geometries.\n * Expanded supported workloads across both shipped geometries.\n\n* **Documentation**\n* Updated support, registry, CUDA graph, build, and model-integration\nguidance with expanded geometry requirements and configurations.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->"},"path":{"kind":"string","value":"flashinfer/gdn_kernels/experimental/kernel/gdn_fused_decode_sm120.cu"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * Copyright (c) 2026 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <cuda_bf16.h>\n#include <cuda_runtime.h>\n#include <math.h>\n\n#include <atomic>\n\n#include \"tvm_ffi_utils.h\"\n\nnamespace {\n\n// Fused GDN decode step for a fixed traced layer geometry: one persistent\n// kernel covering the in_proj_ba GEMV, the depthwise causal conv1d update\n// (width 4, silu), the q/k/v head split, and the gated delta-rule state\n// update with qk-L2-norm, replacing the multi-launch serving chain.\nconstexpr int HIDDEN = 5120;\nconstexpr int N_BA = 96;\nconstexpr int QKV_DIM = 10240;\nconstexpr int H_Q = 16;\nconstexpr int HV = 48;\nconstexpr int D = 128;\nconstexpr int CONV_WIDTH = 4;\nconstexpr int CONV_STATE_LEN = 3;\nconstexpr int HEADS_PER_QK = 3;\nconstexpr int ROWS_PER_WARP = 8;\nconstexpr int GEMV_NSPLIT = 160;\n// The gate reduction below unrolls the GEMV partials as 5 warp-wide loads.\nstatic_assert(GEMV_NSPLIT == 5 * 32, \"gate reduction assumes 5 warp-strided loads\");\n\ntypedef __nv_bfloat16 bf16;\n\n__device__ __forceinline__ float siluf(float x) { return x / (1.0f + __expf(-x)); }\n__device__ __forceinline__ float sigmoidf(float x) { return 1.0f / (1.0f + __expf(-x)); }\n__device__ __forceinline__ float softplusf(float x) { return x > 20.0f ? x : log1pf(__expf(x)); }\n__device__ __forceinline__ float warp_reduce(float v) {\n#pragma unroll\n for (int o = 16; o > 0; o >>= 1) v += __shfl_down_sync(0xffffffff, v, o);\n return v;\n}\n\n// Reusable device-wide barrier (regular launch -> graph-capturable) that\n// needs no host-side reset between launches: barrier[0] is the arrival\n// counter (reset by the releasing block before it releases), barrier[1] is a\n// monotonic release generation. Each block samples the generation at its own\n// arrival; release of the current launch cannot precede that sample, and the\n// previous launch's release is stream-ordered before this kernel starts, so\n// the sampled value is uniform. The generation spin uses equality, so counter\n// wrap-around is harmless, and the arrival reset keeps the barrier correct\n// when consecutive launches use different grid sizes.\n// Requires: barrier zero-initialized once at allocation, all blocks\n// co-resident (grid capped to occupancy), and at most one kernel using the\n// buffer in flight (single-stream use; the in-place state pools already\n// require this).\n//\n// Memory ordering: the barrier is release/acquire, not just a flag.\n// - Release: the block that completes the count fences before bumping the\n// generation, so every pre-barrier write of every block that arrived\n// before it is visible at the point the generation changes.\n// - Acquire: a block leaving the barrier fences AGAIN before its\n// post-barrier reads. Observing the new generation through a volatile\n// (L2-serviced) load only orders that one location; without the leaving\n// fence, a subsequent ordinary load of ba_part / conv_out -- written by a\n// *different* block, i.e. potentially a different SM -- may be serviced\n// from a stale non-coherent L1 line or be hoisted by the compiler above\n// the spin. This mirrors cooperative_groups' own grid barrier, which\n// calls its `bar_flush()` (a __threadfence) on the way out for exactly\n// this reason. The fence is executed by the same thread that spun and is\n// followed by __syncthreads(), which propagates the ordering to the rest\n// of the block.\n__device__ __forceinline__ void grid_barrier(volatile unsigned* barrier, int nblocks) {\n __syncthreads();\n if (threadIdx.x == 0) {\n unsigned gen = barrier[1];\n __threadfence();\n unsigned arrived = atomicAdd((unsigned*)&barrier[0], 1u) + 1u;\n if (arrived == (unsigned)nblocks) {\n barrier[0] = 0u; // reset the arrival counter for the next launch\n __threadfence();\n atomicAdd((unsigned*)&barrier[1], 1u); // release everyone\n } else {\n while (barrier[1] == gen) { /* spin */\n }\n }\n __threadfence(); // acquire: peers' pre-barrier writes before our reads\n }\n __syncthreads();\n}\n\n// Single persistent kernel: gemv+conv -> [barrier] -> delta. Regular launch.\n// The kB1 instantiation specializes the serving-hot B=1 case: batch/split\n// index math collapses to compile-time constants and the fp32 state rows for\n// the (single) delta task of each warp are prefetched before the barrier so\n// their long-scoreboard latency overlaps the gemv/conv phases (the state pool\n// is only written after the barrier, each row by the warp that prefetched it).\n//\n// Padded batch rows: a NEGATIVE state index (vLLM's PAD_SLOT_ID = -1) marks a\n// batch row that owns no pool slot -- what a CUDA-graph replay carries in the\n// rows between the live request count and the captured batch size. Such a row\n// is skipped in every phase that touches a pool (no read and no write of\n// conv_state / ssm_state) and its output rows are written as zero, matching\n// the fp32 path of gated_delta_rule_decode_pretranspose. The check has to be\n// here rather than on the host: reading index VALUES host-side costs a\n// device-to-host sync per layer per decode step and is impossible under graph\n// capture. Each guard is uniform over the threads that share a batch row\n// (warp-uniform in the delta phase, where the warp-wide shuffles below make\n// divergence unacceptable), so it costs one predicated branch, not divergence.\n// Indices >= P are NOT padding and are not checked -- see the note on\n// state_indices in the FFI entry point below.\n//\n// Aliasing: the op updates both state pools IN PLACE, so the launcher passes\n// the same pointer for (conv_state, updated_conv) and for (ssm_state,\n// ssm_out). Those four parameters therefore carry no __restrict__ -- the\n// pools are read and written through two different parameters, which is\n// exactly what restrict promises does not happen, and promising it would let\n// the compiler reorder a pool load across a pool store. The remaining\n// pointers are genuinely disjoint buffers and keep the qualifier. The read\n// path pays for this: loads from the pools can no longer be promoted to\n// ld.global.nc. Only this impl is affected -- the registry prefers the\n// CuTe-DSL kernel for every shipped row -- and correctness is not a thing to\n// trade for a read-only-cache hint.\ntemplate <bool kB1>\n__global__ void gdn_fused_decode_kernel(\n const bf16* __restrict__ hidden, const bf16* __restrict__ w_ba,\n const bf16* __restrict__ mixed_qkv, const bf16* __restrict__ conv_weight,\n const bf16* __restrict__ conv_bias, const bf16* conv_state, const float* __restrict__ A_log,\n const bf16* __restrict__ dt_bias, const float* ssm_state, const int* __restrict__ state_indices,\n float scale, long state_stride_0, long qkv_stride, long conv_stride_p, long conv_stride_c,\n long conv_stride_t, bf16* __restrict__ output, bf16* updated_conv, float* ssm_out,\n float* __restrict__ ba_part, bf16* __restrict__ conv_out, unsigned* __restrict__ barrier,\n int B) {\n int tid = blockIdx.x * blockDim.x + threadIdx.x;\n int nthreads = gridDim.x * blockDim.x;\n const int Beff = kB1 ? 1 : B;\n\n // ---- Phase A1: GEMV partials ----\n // tasks: (split in 0..GEMV_NSPLIT-1) x (b) x (col in 0..95). Partials are\n // stored split-major per (col, b) so the gate reduction reads them with\n // warp-coalesced loads.\n long gemv_tasks = (long)GEMV_NSPLIT * Beff * N_BA;\n for (long t = tid; t < gemv_tasks; t += nthreads) {\n int col = t % N_BA;\n long r = t / N_BA;\n int b;\n int split;\n if constexpr (kB1) {\n b = 0;\n split = (int)r;\n } else {\n b = r % B;\n split = r / B;\n }\n const bf16* hrow = hidden + (long)b * HIDDEN;\n float a0 = 0, a1 = 0, a2 = 0, a3 = 0;\n int k = split;\n for (; k + 3 * GEMV_NSPLIT < HIDDEN; k += 4 * GEMV_NSPLIT) {\n a0 += __bfloat162float(hrow[k]) * __bfloat162float(w_ba[(long)k * N_BA + col]);\n a1 += __bfloat162float(hrow[k + GEMV_NSPLIT]) *\n __bfloat162float(w_ba[(long)(k + GEMV_NSPLIT) * N_BA + col]);\n a2 += __bfloat162float(hrow[k + 2 * GEMV_NSPLIT]) *\n __bfloat162float(w_ba[(long)(k + 2 * GEMV_NSPLIT) * N_BA + col]);\n a3 += __bfloat162float(hrow[k + 3 * GEMV_NSPLIT]) *\n __bfloat162float(w_ba[(long)(k + 3 * GEMV_NSPLIT) * N_BA + col]);\n }\n for (; k < HIDDEN; k += GEMV_NSPLIT)\n a0 += __bfloat162float(hrow[k]) * __bfloat162float(w_ba[(long)k * N_BA + col]);\n ba_part[((long)col * Beff + b) * GEMV_NSPLIT + split] = (a0 + a1) + (a2 + a3);\n }\n\n // ---- Phase A2: conv (independent of gemv) ----\n long conv_tasks = (long)Beff * QKV_DIM;\n for (long t = tid; t < conv_tasks; t += nthreads) {\n int b;\n int c;\n if constexpr (kB1) {\n b = 0;\n c = (int)t;\n } else {\n b = t / QKV_DIM;\n c = t % QKV_DIM;\n }\n int idx = state_indices[b];\n // Padded row: owns no conv-state slot, so neither shift it nor append to\n // it. conv_out for this row stays whatever the scratch held -- the delta\n // phase skips the same row, so nothing reads it.\n if (idx < 0) continue;\n // conv_state addressing is stride-parameterized: the pool arrives as a\n // logical [P, QKV_DIM, CONV_STATE_LEN] view of either a DS-dense pool\n // (strides p,3,1 -> per-thread 3-element rows) or a transposed SD pool\n // (strides p,1,QKV_DIM -> fully coalesced across channels, the vLLM\n // default). Pure index arithmetic; the update math is identical.\n const bf16* st = conv_state + (long)idx * conv_stride_p + (long)c * conv_stride_c;\n bf16 s0 = st[0], s1 = st[conv_stride_t], s2 = st[2 * conv_stride_t];\n // mixed_qkv rows may be strided (e.g. a view into a wider projection).\n bf16 xr = mixed_qkv[(long)b * qkv_stride + c];\n const bf16* w = conv_weight + (long)c * CONV_WIDTH;\n float y = __bfloat162float(s0) * __bfloat162float(w[0]) +\n __bfloat162float(s1) * __bfloat162float(w[1]) +\n __bfloat162float(s2) * __bfloat162float(w[2]) +\n __bfloat162float(xr) * __bfloat162float(w[3]) + __bfloat162float(conv_bias[c]);\n conv_out[(long)b * QKV_DIM + c] = __float2bfloat16(siluf(y));\n bf16* uc = updated_conv + (long)idx * conv_stride_p + (long)c * conv_stride_c;\n uc[0] = s1;\n uc[conv_stride_t] = s2;\n uc[2 * conv_stride_t] = xr;\n }\n\n // ---- Pre-barrier prefetch of this warp's first delta task's state rows.\n // The state pool is read-only until phase C, and each row is written only\n // by the warp that owns (and prefetched) it, so this is race-free.\n int gwarp = tid >> 5;\n int lane = threadIdx.x & 31;\n int nwarps = nthreads >> 5;\n long total_rows = (long)Beff * HV * D;\n long warps_needed = (total_rows + ROWS_PER_WARP - 1) / ROWS_PER_WARP;\n\n float4 s_pre[ROWS_PER_WARP];\n long pre_row_base = -1;\n if (gwarp < warps_needed) {\n long first_row = (long)gwarp * ROWS_PER_WARP;\n int v0;\n int h;\n int b;\n if constexpr (kB1) {\n v0 = (int)(first_row & (D - 1));\n h = (int)(first_row >> 7);\n b = 0;\n } else {\n v0 = first_row % D;\n long tmp = first_row / D;\n h = tmp % HV;\n b = tmp / HV;\n }\n int idx = state_indices[b];\n // A padded row has no state row to prefetch. pre_row_base stays -1, which\n // no live row_base can equal, so the delta phase never mistakes the\n // (unwritten) s_pre registers for this warp's prefetched rows.\n if (idx >= 0) {\n pre_row_base = (long)idx * state_stride_0 + (long)h * (D * D);\n const float4* base_srow = (const float4*)(ssm_state + pre_row_base + (long)v0 * D);\n#pragma unroll\n for (int r = 0; r < ROWS_PER_WARP; ++r) s_pre[r] = base_srow[r * (D / 4) + lane];\n }\n }\n\n grid_barrier(barrier, gridDim.x);\n\n // ---- Phase C: delta (gate reduced inline from ba_part) ----\n for (long w = gwarp; w < warps_needed; w += nwarps) {\n long first_row = w * ROWS_PER_WARP;\n int v0;\n int h;\n int b;\n if constexpr (kB1) {\n v0 = (int)(first_row & (D - 1));\n h = (int)(first_row >> 7);\n b = 0;\n } else {\n v0 = first_row % D;\n long tmp = first_row / D;\n h = tmp % HV;\n b = tmp / HV;\n }\n int j = h / HEADS_PER_QK;\n const bf16* co = conv_out + (long)b * QKV_DIM;\n const bf16* qb = co + j * D;\n const bf16* kb = co + H_Q * D + j * D;\n int k0 = lane * 4;\n int idx = state_indices[b];\n if (idx < 0) {\n // Padded row: no state row to read or write; its output rows are zero.\n // b (hence idx) is warp-uniform -- first_row is a multiple of\n // ROWS_PER_WARP and the whole warp shares w -- so the whole warp takes\n // this branch together and the warp-wide shuffles below are never\n // reached with a partial mask.\n if (lane == 0) {\n#pragma unroll\n for (int r = 0; r < ROWS_PER_WARP; ++r)\n output[((long)b * HV + h) * D + v0 + r] = __float2bfloat16(0.0f);\n }\n continue;\n }\n long row_base = (long)idx * state_stride_0 + (long)h * (D * D);\n float4 s4[ROWS_PER_WARP];\n if (w == gwarp && row_base == pre_row_base) {\n // First iteration (the only one for B=1): use the prefetched rows.\n#pragma unroll\n for (int r = 0; r < ROWS_PER_WARP; ++r) s4[r] = s_pre[r];\n } else {\n const float4* base_srow = (const float4*)(ssm_state + row_base + (long)v0 * D);\n#pragma unroll\n for (int r = 0; r < ROWS_PER_WARP; ++r) s4[r] = base_srow[r * (D / 4) + lane];\n }\n // Issue the gate-partial loads early (10 concurrent warp-wide loads) so\n // they overlap the qk-norm compute below.\n const float* base_b = ba_part + ((long)h * Beff + b) * GEMV_NSPLIT;\n const float* base_a = ba_part + ((long)(HV + h) * Beff + b) * GEMV_NSPLIT;\n float b0 = base_b[lane + 0];\n float a0v = base_a[lane + 0];\n float b1 = base_b[lane + 32];\n float a1v = base_a[lane + 32];\n float b2 = base_b[lane + 64];\n float a2v = base_a[lane + 64];\n float b3 = base_b[lane + 96];\n float a3v = base_a[lane + 96];\n float b4 = base_b[lane + 128];\n float a4v = base_a[lane + 128];\n float qraw[4], kraw[4];\n float qss = 0.f, kss = 0.f;\n#pragma unroll\n for (int i = 0; i < 4; ++i) {\n qraw[i] = __bfloat162float(qb[k0 + i]);\n kraw[i] = __bfloat162float(kb[k0 + i]);\n qss += qraw[i] * qraw[i];\n kss += kraw[i] * kraw[i];\n }\n qss = warp_reduce(qss);\n kss = warp_reduce(kss);\n qss = __shfl_sync(0xffffffff, qss, 0);\n kss = __shfl_sync(0xffffffff, kss, 0);\n float qn = rsqrtf(qss + 1e-6f), kn = rsqrtf(kss + 1e-6f);\n float qh[4], kh[4], QKp = 0.f;\n#pragma unroll\n for (int i = 0; i < 4; ++i) {\n qh[i] = qraw[i] * qn;\n kh[i] = kraw[i] * kn;\n QKp += qh[i] * kh[i];\n }\n QKp = warp_reduce(QKp);\n float QK = __shfl_sync(0xffffffff, QKp, 0);\n // gate g,beta reduced from the split-major partials (values now arrived)\n float accb = ((b0 + b1) + (b2 + b3)) + b4;\n float acca = ((a0v + a1v) + (a2v + a3v)) + a4v;\n accb = warp_reduce(accb);\n acca = warp_reduce(acca);\n accb = __shfl_sync(0xffffffff, accb, 0);\n acca = __shfl_sync(0xffffffff, acca, 0);\n // The bf16 round-trip of the two gate sums is load-bearing, not a leftover:\n // the composable path materializes `ba = (hidden @ w_ba)` as a bf16 tensor\n // and only then widens it for the gates, so the values it feeds\n // sigmoid/softplus are bf16-rounded. Keeping the fp32 accumulator here\n // would make this kernel *more* precise than the operation it implements\n // and move the gates off the reference by up to one bf16 ulp -- amplified\n // by exp() in the decay gate. Track the composable path's `ba` dtype, not\n // the accumulator's.\n float beta = sigmoidf(__bfloat162float(__float2bfloat16(accb)));\n float xg = __bfloat162float(__float2bfloat16(acca)) + __bfloat162float(dt_bias[h]);\n float g = __expf(-__expf(A_log[h]) * softplusf(xg));\n#pragma unroll\n for (int r = 0; r < ROWS_PER_WARP; ++r) {\n int v = v0 + r;\n float s[4] = {s4[r].x, s4[r].y, s4[r].z, s4[r].w};\n float vv = __bfloat162float(co[2 * H_Q * D + h * D + v]);\n float kSp = 0.f, qSp = 0.f;\n#pragma unroll\n for (int i = 0; i < 4; ++i) {\n kSp += kh[i] * s[i];\n qSp += qh[i] * s[i];\n }\n#pragma unroll\n for (int o = 16; o > 0; o >>= 1) {\n kSp += __shfl_down_sync(0xffffffff, kSp, o);\n qSp += __shfl_down_sync(0xffffffff, qSp, o);\n }\n float kS = __shfl_sync(0xffffffff, kSp, 0);\n float qS = __shfl_sync(0xffffffff, qSp, 0);\n float old_v = g * kS;\n float delta = beta * (vv - old_v);\n float out_v = scale * (g * qS + delta * QK);\n float4* Sorow = (float4*)(ssm_out + row_base + (long)v * D);\n float4 o4;\n o4.x = g * s[0] + kh[0] * delta;\n o4.y = g * s[1] + kh[1] * delta;\n o4.z = g * s[2] + kh[2] * delta;\n o4.w = g * s[3] + kh[3] * delta;\n Sorow[lane] = o4;\n if (lane == 0) output[((long)b * HV + h) * D + v] = __float2bfloat16(out_v);\n }\n }\n}\n\nvoid gdn_fused_decode_launch(const void* hidden, const void* w_ba, const void* mixed_qkv,\n const void* conv_weight, const void* conv_bias, void* conv_state,\n const void* A_log, const void* dt_bias, float scale, void* ssm_state,\n const void* state_indices, void* output, void* conv_out_scratch,\n void* ba_scratch, void* barrier, long state_stride_0, long qkv_stride,\n long conv_stride_p, long conv_stride_c, long conv_stride_t, int B,\n cudaStream_t stream) {\n constexpr int kBlock = 256;\n constexpr int kWarpsPerBlock = kBlock / 32;\n constexpr int kMaxDevices = 64;\n // Per-device launch-geometry cache. num_sm[dev] doubles as the entry's\n // COMPLETION flag and is therefore published LAST, with release ordering:\n // a second launcher thread that sees it non-zero must also see the two\n // occupancy values. Writing it first (and the occupancies after) would let\n // such a thread read blocks_per_sm_*[dev] == 0, collapse `cap` to 0 and run\n // the persistent kernel on a single block -- still correct (both the\n // barrier and the delta loop are grid-size agnostic) but orders of\n // magnitude slower, and only on the unlucky interleaving. Two threads\n // filling the entry concurrently is harmless: the queries are pure and\n // return identical values.\n static int blocks_per_sm_b1[kMaxDevices] = {0};\n static int blocks_per_sm_gen[kMaxDevices] = {0};\n static std::atomic<int> num_sm[kMaxDevices] = {};\n int dev = 0;\n cudaGetDevice(&dev);\n if (dev < 0 || dev >= kMaxDevices) dev = 0;\n int sm_count = num_sm[dev].load(std::memory_order_acquire);\n if (sm_count == 0) {\n int occ_b1 = 0;\n int occ_gen = 0;\n cudaDeviceGetAttribute(&sm_count, cudaDevAttrMultiProcessorCount, dev);\n cudaOccupancyMaxActiveBlocksPerMultiprocessor(&occ_b1, gdn_fused_decode_kernel<true>, kBlock,\n 0);\n cudaOccupancyMaxActiveBlocksPerMultiprocessor(&occ_gen, gdn_fused_decode_kernel<false>, kBlock,\n 0);\n blocks_per_sm_b1[dev] = occ_b1;\n blocks_per_sm_gen[dev] = occ_gen;\n num_sm[dev].store(sm_count, std::memory_order_release);\n }\n // Grid must be <= resident capacity (persistent barrier needs co-residency),\n // but no larger than needed. Delta single-pass needs\n // ceil(rows / ROWS_PER_WARP / warps-per-block) blocks -- derived from kBlock\n // so the two cannot drift apart.\n long rows = (long)B * HV * D;\n long warps_needed = (rows + ROWS_PER_WARP - 1) / ROWS_PER_WARP;\n int delta_blocks = (int)((warps_needed + kWarpsPerBlock - 1) / kWarpsPerBlock);\n int cap = (B == 1 ? blocks_per_sm_b1[dev] : blocks_per_sm_gen[dev]) * sm_count;\n int grid = delta_blocks < cap ? delta_blocks : cap;\n if (grid < 1) grid = 1;\n // No per-call barrier reset: the barrier is zero-initialized at allocation\n // and self-resetting across launches (see grid_barrier).\n if (B == 1) {\n gdn_fused_decode_kernel<true><<<grid, kBlock, 0, stream>>>(\n static_cast<const bf16*>(hidden), static_cast<const bf16*>(w_ba),\n static_cast<const bf16*>(mixed_qkv), static_cast<const bf16*>(conv_weight),\n static_cast<const bf16*>(conv_bias), static_cast<const bf16*>(conv_state),\n static_cast<const float*>(A_log), static_cast<const bf16*>(dt_bias),\n static_cast<const float*>(ssm_state), static_cast<const int*>(state_indices), scale,\n state_stride_0, qkv_stride, conv_stride_p, conv_stride_c, conv_stride_t,\n static_cast<bf16*>(output), static_cast<bf16*>(conv_state), static_cast<float*>(ssm_state),\n static_cast<float*>(ba_scratch), static_cast<bf16*>(conv_out_scratch),\n static_cast<unsigned*>(barrier), B);\n } else {\n gdn_fused_decode_kernel<false><<<grid, kBlock, 0, stream>>>(\n static_cast<const bf16*>(hidden), static_cast<const bf16*>(w_ba),\n static_cast<const bf16*>(mixed_qkv), static_cast<const bf16*>(conv_weight),\n static_cast<const bf16*>(conv_bias), static_cast<const bf16*>(conv_state),\n static_cast<const float*>(A_log), static_cast<const bf16*>(dt_bias),\n static_cast<const float*>(ssm_state), static_cast<const int*>(state_indices), scale,\n state_stride_0, qkv_stride, conv_stride_p, conv_stride_c, conv_stride_t,\n static_cast<bf16*>(output), static_cast<bf16*>(conv_state), static_cast<float*>(ssm_state),\n static_cast<float*>(ba_scratch), static_cast<bf16*>(conv_out_scratch),\n static_cast<unsigned*>(barrier), B);\n }\n}\n\n} // namespace\n\nvoid gdn_fused_decode(TensorView hidden_states, TensorView w_ba, TensorView mixed_qkv,\n TensorView conv_weight, TensorView conv_bias, TensorView conv_state,\n TensorView A_log, TensorView dt_bias, TensorView ssm_state,\n TensorView state_indices, TensorView output, TensorView conv_out_scratch,\n TensorView ba_scratch, TensorView barrier, double scale) {\n CHECK_INPUT_TYPE(hidden_states, dl_bfloat16);\n CHECK_INPUT_TYPE(w_ba, dl_bfloat16);\n CHECK_INPUT_TYPE(mixed_qkv, dl_bfloat16);\n CHECK_INPUT_TYPE(conv_weight, dl_bfloat16);\n CHECK_INPUT_TYPE(conv_bias, dl_bfloat16);\n CHECK_INPUT_TYPE(conv_state, dl_bfloat16);\n CHECK_INPUT_TYPE(A_log, dl_float32);\n CHECK_INPUT_TYPE(dt_bias, dl_bfloat16);\n CHECK_INPUT_TYPE(ssm_state, dl_float32);\n CHECK_INPUT_TYPE(state_indices, dl_int32);\n CHECK_INPUT_TYPE(output, dl_bfloat16);\n CHECK_INPUT_TYPE(conv_out_scratch, dl_bfloat16);\n CHECK_INPUT_TYPE(ba_scratch, dl_float32);\n CHECK_INPUT_TYPE(barrier, dl_int32);\n\n CHECK_DIM(2, hidden_states);\n CHECK_DIM(2, w_ba);\n CHECK_DIM(2, mixed_qkv);\n CHECK_DIM(2, conv_weight);\n CHECK_DIM(1, conv_bias);\n CHECK_DIM(3, conv_state);\n CHECK_DIM(1, A_log);\n CHECK_DIM(1, dt_bias);\n CHECK_DIM(4, ssm_state);\n CHECK_DIM(1, state_indices);\n CHECK_DIM(4, output);\n CHECK_DIM(2, conv_out_scratch);\n CHECK_DIM(1, ba_scratch);\n CHECK_DIM(1, barrier);\n\n const int B = static_cast<int>(hidden_states.size(0));\n TVM_FFI_ICHECK_GT(B, 0);\n TVM_FFI_ICHECK_EQ(hidden_states.size(1), HIDDEN);\n TVM_FFI_ICHECK_EQ(w_ba.size(0), HIDDEN);\n TVM_FFI_ICHECK_EQ(w_ba.size(1), N_BA);\n TVM_FFI_ICHECK_EQ(mixed_qkv.size(0), B);\n TVM_FFI_ICHECK_EQ(mixed_qkv.size(1), QKV_DIM);\n TVM_FFI_ICHECK_EQ(conv_weight.size(0), QKV_DIM);\n TVM_FFI_ICHECK_EQ(conv_weight.size(1), CONV_WIDTH);\n TVM_FFI_ICHECK_EQ(conv_bias.size(0), QKV_DIM);\n TVM_FFI_ICHECK_EQ(conv_state.size(1), QKV_DIM);\n TVM_FFI_ICHECK_EQ(conv_state.size(2), CONV_STATE_LEN);\n TVM_FFI_ICHECK_EQ(A_log.size(0), HV);\n TVM_FFI_ICHECK_EQ(dt_bias.size(0), HV);\n TVM_FFI_ICHECK_EQ(ssm_state.size(1), HV);\n TVM_FFI_ICHECK_EQ(ssm_state.size(2), D);\n TVM_FFI_ICHECK_EQ(ssm_state.size(3), D);\n // state_indices holds SHAPE checks only, deliberately. Its VALUES are a\n // per-row property that lives on the device: a host-side range check would\n // need a device-to-host copy of the index vector on every layer of every\n // decode step, and cannot run at all inside a CUDA-graph capture (which is\n // the regime that produces padded rows in the first place). So the two value\n // classes are handled where they can be:\n // - NEGATIVE (vLLM's PAD_SLOT_ID = -1) is the padding convention. The\n // kernel skips those rows entirely -- neither pool is read or written --\n // and zeroes their output rows, matching the fp32 path of\n // gated_delta_rule_decode_pretranspose.\n // - >= P (the pool's leading extent) is a CALLER BUG, not padding, and is\n // left undefined rather than clamped or silently skipped: clamping would\n // corrupt a real slot without a diagnostic, and skipping would turn a\n // caller's index arithmetic error into silently missing state updates.\n // Conflating it with -1 would make both failure modes invisible.\n TVM_FFI_ICHECK_EQ(state_indices.size(0), B);\n TVM_FFI_ICHECK_EQ(output.size(0), B);\n TVM_FFI_ICHECK_EQ(output.size(1), 1);\n TVM_FFI_ICHECK_EQ(output.size(2), HV);\n TVM_FFI_ICHECK_EQ(output.size(3), D);\n TVM_FFI_ICHECK_EQ(conv_out_scratch.size(0), B);\n TVM_FFI_ICHECK_EQ(conv_out_scratch.size(1), QKV_DIM);\n TVM_FFI_ICHECK_EQ(ba_scratch.size(0), (long)GEMV_NSPLIT * B * N_BA);\n TVM_FFI_ICHECK_EQ(barrier.size(0), 2);\n\n // Dense inner layout everywhere; the fp32 state pool may have a padded row\n // stride (stride(0) >= HV*D*D), which the kernel consumes directly.\n TVM_FFI_ICHECK_EQ(hidden_states.stride(1), 1);\n TVM_FFI_ICHECK_EQ(hidden_states.stride(0), HIDDEN);\n TVM_FFI_ICHECK_EQ(w_ba.stride(1), 1);\n TVM_FFI_ICHECK_EQ(w_ba.stride(0), N_BA);\n TVM_FFI_ICHECK_EQ(mixed_qkv.stride(1), 1);\n // mixed_qkv rows may be strided (a view into a wider fused projection).\n TVM_FFI_ICHECK_GE(mixed_qkv.stride(0), QKV_DIM);\n TVM_FFI_ICHECK_EQ(conv_weight.stride(1), 1);\n TVM_FFI_ICHECK_EQ(conv_weight.stride(0), CONV_WIDTH);\n // conv_state is a logical [P, QKV_DIM, CONV_STATE_LEN] view over one of the\n // two serving pool layouts (page stride may be padded):\n // - DS pool (dim-first, dense rows): strides (p, CONV_STATE_LEN, 1);\n // - SD pool (vLLM default; physical [P, CONV_STATE_LEN, QKV_DIM] passed as\n // its transpose): strides (p, 1, QKV_DIM).\n {\n const long conv_stride_c = static_cast<long>(conv_state.stride(1));\n const long conv_stride_t = static_cast<long>(conv_state.stride(2));\n const bool conv_ds = conv_stride_c == CONV_STATE_LEN && conv_stride_t == 1;\n const bool conv_sd = conv_stride_c == 1 && conv_stride_t == QKV_DIM;\n TVM_FFI_ICHECK(conv_ds || conv_sd)\n << \"conv_state must be a DS-dense pool or a transposed SD pool view\";\n TVM_FFI_ICHECK_GE(conv_state.stride(0), (long)QKV_DIM * CONV_STATE_LEN);\n }\n TVM_FFI_ICHECK_EQ(ssm_state.stride(3), 1);\n TVM_FFI_ICHECK_EQ(ssm_state.stride(2), D);\n TVM_FFI_ICHECK_EQ(ssm_state.stride(1), (long)D * D);\n TVM_FFI_ICHECK_GE(ssm_state.stride(0), (long)HV * D * D);\n // The delta phase loads and stores whole state rows as float4, so every row\n // base -- idx*stride(0) + h*D*D + v*D -- must be 16B aligned. D*D and v*D\n // already are; a padded page stride is the only term that can break it, and\n // an odd pad would fault rather than degrade.\n TVM_FFI_ICHECK_EQ(ssm_state.stride(0) % 4, 0)\n << \"ssm_state page stride must be a multiple of 4 floats (float4 row access)\";\n TVM_FFI_ICHECK_EQ(output.stride(3), 1);\n TVM_FFI_ICHECK_EQ(output.stride(2), D);\n // The kernel addresses output as one dense [B, 1, HV, D] block\n // (output[((b*HV) + h)*D + v]), so the batch stride is not free either: a\n // destination that is dense per row but strided across the batch (a slice of\n // a wider buffer) would be written at the wrong offsets rather than\n // rejected. stride(1) is deliberately NOT checked -- that axis has extent 1,\n // so the kernel never uses its stride and torch leaves it unconstrained on\n // otherwise contiguous tensors; checking it could reject a valid buffer, and\n // a rejection here latches the whole impl off.\n TVM_FFI_ICHECK_EQ(output.stride(0), (long)HV * D);\n\n const long state_stride_0 = static_cast<long>(ssm_state.stride(0));\n const long qkv_stride = static_cast<long>(mixed_qkv.stride(0));\n const long conv_stride_p = static_cast<long>(conv_state.stride(0));\n const long conv_stride_c = static_cast<long>(conv_state.stride(1));\n const long conv_stride_t = static_cast<long>(conv_state.stride(2));\n\n ffi::CUDADeviceGuard device_guard(hidden_states.device().device_id);\n const cudaStream_t stream = get_stream(hidden_states.device());\n gdn_fused_decode_launch(\n hidden_states.data_ptr(), w_ba.data_ptr(), mixed_qkv.data_ptr(), conv_weight.data_ptr(),\n conv_bias.data_ptr(), conv_state.data_ptr(), A_log.data_ptr(), dt_bias.data_ptr(),\n static_cast<float>(scale), ssm_state.data_ptr(), state_indices.data_ptr(), output.data_ptr(),\n conv_out_scratch.data_ptr(), ba_scratch.data_ptr(), barrier.data_ptr(), state_stride_0,\n qkv_stride, conv_stride_p, conv_stride_c, conv_stride_t, B, stream);\n\n cudaError_t status = cudaGetLastError();\n TVM_FFI_ICHECK(status == cudaSuccess)\n << \"gdn_fused_decode failed with error code \" << cudaGetErrorString(status);\n}\n\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(gdn_fused_decode, gdn_fused_decode);\n"},"after_code":{"kind":"string","value":"/*\n * Copyright (c) 2026 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <cuda_bf16.h>\n#include <cuda_runtime.h>\n#include <math.h>\n\n#include <atomic>\n\n#include \"tvm_ffi_utils.h\"\n\nnamespace {\n\n// Fused GDN decode step for one layer geometry: a single persistent kernel\n// covering the in_proj_ba GEMV, the depthwise causal conv1d update (width 4,\n// silu), the q/k/v head split, and the gated delta-rule state update with\n// qk-L2-norm, replacing the multi-launch serving chain.\n//\n// The layer geometry is a compile-time parameter of this translation unit,\n// supplied by flashinfer/jit/gdn_fused_decode.py as -D defines (one JIT\n// module per geometry; a serving process runs one model, hence one module).\n// Only the sizes change: the block shape, warp->row mapping and reduction\n// trees below are geometry-independent, and the static_asserts state exactly\n// which divisibility relations the code relies on.\n#if !defined(FI_GDN_HIDDEN) || !defined(FI_GDN_N_BA) || !defined(FI_GDN_QKV_DIM) || \\\n !defined(FI_GDN_H_Q) || !defined(FI_GDN_HV) || !defined(FI_GDN_D) || \\\n !defined(FI_GDN_CONV_WIDTH) || !defined(FI_GDN_CONV_STATE_LEN)\n#error \"gdn_fused_decode_sm120.cu requires the FI_GDN_* geometry defines\"\n#endif\nconstexpr int HIDDEN = FI_GDN_HIDDEN;\nconstexpr int N_BA = FI_GDN_N_BA;\nconstexpr int QKV_DIM = FI_GDN_QKV_DIM;\nconstexpr int H_Q = FI_GDN_H_Q;\nconstexpr int HV = FI_GDN_HV;\nconstexpr int D = FI_GDN_D;\nconstexpr int CONV_WIDTH = FI_GDN_CONV_WIDTH;\nconstexpr int CONV_STATE_LEN = FI_GDN_CONV_STATE_LEN;\n// v-heads per qk-head: the delta phase maps v-head h to qk-head h/HEADS_PER_QK.\nconstexpr int HEADS_PER_QK = HV / H_Q;\nconstexpr int ROWS_PER_WARP = 8;\nconstexpr int GEMV_NSPLIT = 160;\n// The gate reduction below unrolls the GEMV partials as 5 warp-wide loads.\nstatic_assert(GEMV_NSPLIT == 5 * 32, \"gate reduction assumes 5 warp-strided loads\");\n// The b/a projection produces HV gate values and HV decay values, stored as\n// the low and high halves of the N_BA columns (see the delta phase's\n// base_b/base_a offsets).\nstatic_assert(N_BA == 2 * HV, \"w_ba columns are [b gates | a decays], HV each\");\nstatic_assert(HV % H_Q == 0, \"each qk-head must serve a whole number of v-heads\");\n// The delta phase gives each lane 4 consecutive channels of a D-wide row and\n// reduces across the warp; the B=1 fast path indexes rows with shifts/masks.\nstatic_assert(D == 4 * 32, \"delta phase maps one D-wide row onto a warp, 4 per lane\");\nstatic_assert((D & (D - 1)) == 0, \"B=1 row index math uses D as a power of two\");\nstatic_assert(D % ROWS_PER_WARP == 0, \"warps own whole groups of state rows\");\n// mixed_qkv is [q | k | v] with H_Q q-heads, H_Q k-heads and HV v-heads.\nstatic_assert(QKV_DIM == (2 * H_Q + HV) * D, \"qkv_dim must match the head split\");\n// The conv phase is unrolled over the width-4 / 3-step shift register below.\nstatic_assert(CONV_WIDTH == 4 && CONV_STATE_LEN == 3, \"conv taps are unrolled as width 4\");\n\n// log2(D), for the B=1 fast path's shift/mask row indexing.\nconstexpr int ilog2_ce(int v) { return v <= 1 ? 0 : 1 + ilog2_ce(v >> 1); }\nconstexpr int D_LOG2 = ilog2_ce(D);\n\ntypedef __nv_bfloat16 bf16;\n\n__device__ __forceinline__ float siluf(float x) { return x / (1.0f + __expf(-x)); }\n__device__ __forceinline__ float sigmoidf(float x) { return 1.0f / (1.0f + __expf(-x)); }\n__device__ __forceinline__ float softplusf(float x) { return x > 20.0f ? x : log1pf(__expf(x)); }\n__device__ __forceinline__ float warp_reduce(float v) {\n#pragma unroll\n for (int o = 16; o > 0; o >>= 1) v += __shfl_down_sync(0xffffffff, v, o);\n return v;\n}\n\n// Reusable device-wide barrier (regular launch -> graph-capturable) that\n// needs no host-side reset between launches: barrier[0] is the arrival\n// counter (reset by the releasing block before it releases), barrier[1] is a\n// monotonic release generation. Each block samples the generation at its own\n// arrival; release of the current launch cannot precede that sample, and the\n// previous launch's release is stream-ordered before this kernel starts, so\n// the sampled value is uniform. The generation spin uses equality, so counter\n// wrap-around is harmless, and the arrival reset keeps the barrier correct\n// when consecutive launches use different grid sizes.\n// Requires: barrier zero-initialized once at allocation, all blocks\n// co-resident (grid capped to occupancy), and at most one kernel using the\n// buffer in flight (single-stream use; the in-place state pools already\n// require this).\n//\n// Memory ordering: the barrier is release/acquire, not just a flag.\n// - Release: the block that completes the count fences before bumping the\n// generation, so every pre-barrier write of every block that arrived\n// before it is visible at the point the generation changes.\n// - Acquire: a block leaving the barrier fences AGAIN before its\n// post-barrier reads. Observing the new generation through a volatile\n// (L2-serviced) load only orders that one location; without the leaving\n// fence, a subsequent ordinary load of ba_part / conv_out -- written by a\n// *different* block, i.e. potentially a different SM -- may be serviced\n// from a stale non-coherent L1 line or be hoisted by the compiler above\n// the spin. This mirrors cooperative_groups' own grid barrier, which\n// calls its `bar_flush()` (a __threadfence) on the way out for exactly\n// this reason. The fence is executed by the same thread that spun and is\n// followed by __syncthreads(), which propagates the ordering to the rest\n// of the block.\n__device__ __forceinline__ void grid_barrier(volatile unsigned* barrier, int nblocks) {\n __syncthreads();\n if (threadIdx.x == 0) {\n unsigned gen = barrier[1];\n __threadfence();\n unsigned arrived = atomicAdd((unsigned*)&barrier[0], 1u) + 1u;\n if (arrived == (unsigned)nblocks) {\n barrier[0] = 0u; // reset the arrival counter for the next launch\n __threadfence();\n atomicAdd((unsigned*)&barrier[1], 1u); // release everyone\n } else {\n while (barrier[1] == gen) { /* spin */\n }\n }\n __threadfence(); // acquire: peers' pre-barrier writes before our reads\n }\n __syncthreads();\n}\n\n// Single persistent kernel: gemv+conv -> [barrier] -> delta. Regular launch.\n// The kB1 instantiation specializes the serving-hot B=1 case: batch/split\n// index math collapses to compile-time constants and the fp32 state rows for\n// the (single) delta task of each warp are prefetched before the barrier so\n// their long-scoreboard latency overlaps the gemv/conv phases (the state pool\n// is only written after the barrier, each row by the warp that prefetched it).\n//\n// Padded batch rows: a NEGATIVE state index (vLLM's PAD_SLOT_ID = -1) marks a\n// batch row that owns no pool slot -- what a CUDA-graph replay carries in the\n// rows between the live request count and the captured batch size. Such a row\n// is skipped in every phase that touches a pool (no read and no write of\n// conv_state / ssm_state) and its output rows are written as zero, matching\n// the fp32 path of gated_delta_rule_decode_pretranspose. The check has to be\n// here rather than on the host: reading index VALUES host-side costs a\n// device-to-host sync per layer per decode step and is impossible under graph\n// capture. Each guard is uniform over the threads that share a batch row\n// (warp-uniform in the delta phase, where the warp-wide shuffles below make\n// divergence unacceptable), so it costs one predicated branch, not divergence.\n// Indices >= P are NOT padding and are not checked -- see the note on\n// state_indices in the FFI entry point below.\n//\n// Aliasing: the op updates both state pools IN PLACE, so the launcher passes\n// the same pointer for (conv_state, updated_conv) and for (ssm_state,\n// ssm_out). Those four parameters therefore carry no __restrict__ -- the\n// pools are read and written through two different parameters, which is\n// exactly what restrict promises does not happen, and promising it would let\n// the compiler reorder a pool load across a pool store. The remaining\n// pointers are genuinely disjoint buffers and keep the qualifier. The read\n// path pays for this: loads from the pools can no longer be promoted to\n// ld.global.nc. Only this impl is affected -- the registry prefers the\n// CuTe-DSL kernel for every shipped row -- and correctness is not a thing to\n// trade for a read-only-cache hint.\ntemplate <bool kB1>\n__global__ void gdn_fused_decode_kernel(\n const bf16* __restrict__ hidden, const bf16* __restrict__ w_ba,\n const bf16* __restrict__ mixed_qkv, const bf16* __restrict__ conv_weight,\n const bf16* __restrict__ conv_bias, const bf16* conv_state, const float* __restrict__ A_log,\n const bf16* __restrict__ dt_bias, const float* ssm_state, const int* __restrict__ state_indices,\n float scale, long state_stride_0, long qkv_stride, long conv_stride_p, long conv_stride_c,\n long conv_stride_t, bf16* __restrict__ output, bf16* updated_conv, float* ssm_out,\n float* __restrict__ ba_part, bf16* __restrict__ conv_out, unsigned* __restrict__ barrier,\n int B) {\n int tid = blockIdx.x * blockDim.x + threadIdx.x;\n int nthreads = gridDim.x * blockDim.x;\n const int Beff = kB1 ? 1 : B;\n\n // ---- Phase A1: GEMV partials ----\n // tasks: (split in 0..GEMV_NSPLIT-1) x (b) x (col in 0..N_BA-1). Partials\n // are stored split-major per (col, b) so the gate reduction reads them with\n // warp-coalesced loads.\n long gemv_tasks = (long)GEMV_NSPLIT * Beff * N_BA;\n for (long t = tid; t < gemv_tasks; t += nthreads) {\n int col = t % N_BA;\n long r = t / N_BA;\n int b;\n int split;\n if constexpr (kB1) {\n b = 0;\n split = (int)r;\n } else {\n b = r % B;\n split = r / B;\n }\n const bf16* hrow = hidden + (long)b * HIDDEN;\n float a0 = 0, a1 = 0, a2 = 0, a3 = 0;\n int k = split;\n for (; k + 3 * GEMV_NSPLIT < HIDDEN; k += 4 * GEMV_NSPLIT) {\n a0 += __bfloat162float(hrow[k]) * __bfloat162float(w_ba[(long)k * N_BA + col]);\n a1 += __bfloat162float(hrow[k + GEMV_NSPLIT]) *\n __bfloat162float(w_ba[(long)(k + GEMV_NSPLIT) * N_BA + col]);\n a2 += __bfloat162float(hrow[k + 2 * GEMV_NSPLIT]) *\n __bfloat162float(w_ba[(long)(k + 2 * GEMV_NSPLIT) * N_BA + col]);\n a3 += __bfloat162float(hrow[k + 3 * GEMV_NSPLIT]) *\n __bfloat162float(w_ba[(long)(k + 3 * GEMV_NSPLIT) * N_BA + col]);\n }\n for (; k < HIDDEN; k += GEMV_NSPLIT)\n a0 += __bfloat162float(hrow[k]) * __bfloat162float(w_ba[(long)k * N_BA + col]);\n ba_part[((long)col * Beff + b) * GEMV_NSPLIT + split] = (a0 + a1) + (a2 + a3);\n }\n\n // ---- Phase A2: conv (independent of gemv) ----\n long conv_tasks = (long)Beff * QKV_DIM;\n for (long t = tid; t < conv_tasks; t += nthreads) {\n int b;\n int c;\n if constexpr (kB1) {\n b = 0;\n c = (int)t;\n } else {\n b = t / QKV_DIM;\n c = t % QKV_DIM;\n }\n int idx = state_indices[b];\n // Padded row: owns no conv-state slot, so neither shift it nor append to\n // it. conv_out for this row stays whatever the scratch held -- the delta\n // phase skips the same row, so nothing reads it.\n if (idx < 0) continue;\n // conv_state addressing is stride-parameterized: the pool arrives as a\n // logical [P, QKV_DIM, CONV_STATE_LEN] view of either a DS-dense pool\n // (strides p,3,1 -> per-thread 3-element rows) or a transposed SD pool\n // (strides p,1,QKV_DIM -> fully coalesced across channels, the vLLM\n // default). Pure index arithmetic; the update math is identical.\n const bf16* st = conv_state + (long)idx * conv_stride_p + (long)c * conv_stride_c;\n bf16 s0 = st[0], s1 = st[conv_stride_t], s2 = st[2 * conv_stride_t];\n // mixed_qkv rows may be strided (e.g. a view into a wider projection).\n bf16 xr = mixed_qkv[(long)b * qkv_stride + c];\n const bf16* w = conv_weight + (long)c * CONV_WIDTH;\n float y = __bfloat162float(s0) * __bfloat162float(w[0]) +\n __bfloat162float(s1) * __bfloat162float(w[1]) +\n __bfloat162float(s2) * __bfloat162float(w[2]) +\n __bfloat162float(xr) * __bfloat162float(w[3]) + __bfloat162float(conv_bias[c]);\n conv_out[(long)b * QKV_DIM + c] = __float2bfloat16(siluf(y));\n bf16* uc = updated_conv + (long)idx * conv_stride_p + (long)c * conv_stride_c;\n uc[0] = s1;\n uc[conv_stride_t] = s2;\n uc[2 * conv_stride_t] = xr;\n }\n\n // ---- Pre-barrier prefetch of this warp's first delta task's state rows.\n // The state pool is read-only until phase C, and each row is written only\n // by the warp that owns (and prefetched) it, so this is race-free.\n int gwarp = tid >> 5;\n int lane = threadIdx.x & 31;\n int nwarps = nthreads >> 5;\n long total_rows = (long)Beff * HV * D;\n long warps_needed = (total_rows + ROWS_PER_WARP - 1) / ROWS_PER_WARP;\n\n float4 s_pre[ROWS_PER_WARP];\n long pre_row_base = -1;\n if (gwarp < warps_needed) {\n long first_row = (long)gwarp * ROWS_PER_WARP;\n int v0;\n int h;\n int b;\n if constexpr (kB1) {\n v0 = (int)(first_row & (D - 1));\n h = (int)(first_row >> D_LOG2);\n b = 0;\n } else {\n v0 = first_row % D;\n long tmp = first_row / D;\n h = tmp % HV;\n b = tmp / HV;\n }\n int idx = state_indices[b];\n // A padded row has no state row to prefetch. pre_row_base stays -1, which\n // no live row_base can equal, so the delta phase never mistakes the\n // (unwritten) s_pre registers for this warp's prefetched rows.\n if (idx >= 0) {\n pre_row_base = (long)idx * state_stride_0 + (long)h * (D * D);\n const float4* base_srow = (const float4*)(ssm_state + pre_row_base + (long)v0 * D);\n#pragma unroll\n for (int r = 0; r < ROWS_PER_WARP; ++r) s_pre[r] = base_srow[r * (D / 4) + lane];\n }\n }\n\n grid_barrier(barrier, gridDim.x);\n\n // ---- Phase C: delta (gate reduced inline from ba_part) ----\n for (long w = gwarp; w < warps_needed; w += nwarps) {\n long first_row = w * ROWS_PER_WARP;\n int v0;\n int h;\n int b;\n if constexpr (kB1) {\n v0 = (int)(first_row & (D - 1));\n h = (int)(first_row >> D_LOG2);\n b = 0;\n } else {\n v0 = first_row % D;\n long tmp = first_row / D;\n h = tmp % HV;\n b = tmp / HV;\n }\n int j = h / HEADS_PER_QK;\n const bf16* co = conv_out + (long)b * QKV_DIM;\n const bf16* qb = co + j * D;\n const bf16* kb = co + H_Q * D + j * D;\n int k0 = lane * 4;\n int idx = state_indices[b];\n if (idx < 0) {\n // Padded row: no state row to read or write; its output rows are zero.\n // b (hence idx) is warp-uniform -- first_row is a multiple of\n // ROWS_PER_WARP and the whole warp shares w -- so the whole warp takes\n // this branch together and the warp-wide shuffles below are never\n // reached with a partial mask.\n if (lane == 0) {\n#pragma unroll\n for (int r = 0; r < ROWS_PER_WARP; ++r)\n output[((long)b * HV + h) * D + v0 + r] = __float2bfloat16(0.0f);\n }\n continue;\n }\n long row_base = (long)idx * state_stride_0 + (long)h * (D * D);\n float4 s4[ROWS_PER_WARP];\n if (w == gwarp && row_base == pre_row_base) {\n // First iteration (the only one for B=1): use the prefetched rows.\n#pragma unroll\n for (int r = 0; r < ROWS_PER_WARP; ++r) s4[r] = s_pre[r];\n } else {\n const float4* base_srow = (const float4*)(ssm_state + row_base + (long)v0 * D);\n#pragma unroll\n for (int r = 0; r < ROWS_PER_WARP; ++r) s4[r] = base_srow[r * (D / 4) + lane];\n }\n // Issue the gate-partial loads early (10 concurrent warp-wide loads) so\n // they overlap the qk-norm compute below.\n const float* base_b = ba_part + ((long)h * Beff + b) * GEMV_NSPLIT;\n const float* base_a = ba_part + ((long)(HV + h) * Beff + b) * GEMV_NSPLIT;\n float b0 = base_b[lane + 0];\n float a0v = base_a[lane + 0];\n float b1 = base_b[lane + 32];\n float a1v = base_a[lane + 32];\n float b2 = base_b[lane + 64];\n float a2v = base_a[lane + 64];\n float b3 = base_b[lane + 96];\n float a3v = base_a[lane + 96];\n float b4 = base_b[lane + 128];\n float a4v = base_a[lane + 128];\n float qraw[4], kraw[4];\n float qss = 0.f, kss = 0.f;\n#pragma unroll\n for (int i = 0; i < 4; ++i) {\n qraw[i] = __bfloat162float(qb[k0 + i]);\n kraw[i] = __bfloat162float(kb[k0 + i]);\n qss += qraw[i] * qraw[i];\n kss += kraw[i] * kraw[i];\n }\n qss = warp_reduce(qss);\n kss = warp_reduce(kss);\n qss = __shfl_sync(0xffffffff, qss, 0);\n kss = __shfl_sync(0xffffffff, kss, 0);\n float qn = rsqrtf(qss + 1e-6f), kn = rsqrtf(kss + 1e-6f);\n float qh[4], kh[4], QKp = 0.f;\n#pragma unroll\n for (int i = 0; i < 4; ++i) {\n qh[i] = qraw[i] * qn;\n kh[i] = kraw[i] * kn;\n QKp += qh[i] * kh[i];\n }\n QKp = warp_reduce(QKp);\n float QK = __shfl_sync(0xffffffff, QKp, 0);\n // gate g,beta reduced from the split-major partials (values now arrived)\n float accb = ((b0 + b1) + (b2 + b3)) + b4;\n float acca = ((a0v + a1v) + (a2v + a3v)) + a4v;\n accb = warp_reduce(accb);\n acca = warp_reduce(acca);\n accb = __shfl_sync(0xffffffff, accb, 0);\n acca = __shfl_sync(0xffffffff, acca, 0);\n // The bf16 round-trip of the two gate sums is load-bearing, not a leftover:\n // the composable path materializes `ba = (hidden @ w_ba)` as a bf16 tensor\n // and only then widens it for the gates, so the values it feeds\n // sigmoid/softplus are bf16-rounded. Keeping the fp32 accumulator here\n // would make this kernel *more* precise than the operation it implements\n // and move the gates off the reference by up to one bf16 ulp -- amplified\n // by exp() in the decay gate. Track the composable path's `ba` dtype, not\n // the accumulator's.\n float beta = sigmoidf(__bfloat162float(__float2bfloat16(accb)));\n float xg = __bfloat162float(__float2bfloat16(acca)) + __bfloat162float(dt_bias[h]);\n float g = __expf(-__expf(A_log[h]) * softplusf(xg));\n#pragma unroll\n for (int r = 0; r < ROWS_PER_WARP; ++r) {\n int v = v0 + r;\n float s[4] = {s4[r].x, s4[r].y, s4[r].z, s4[r].w};\n float vv = __bfloat162float(co[2 * H_Q * D + h * D + v]);\n float kSp = 0.f, qSp = 0.f;\n#pragma unroll\n for (int i = 0; i < 4; ++i) {\n kSp += kh[i] * s[i];\n qSp += qh[i] * s[i];\n }\n#pragma unroll\n for (int o = 16; o > 0; o >>= 1) {\n kSp += __shfl_down_sync(0xffffffff, kSp, o);\n qSp += __shfl_down_sync(0xffffffff, qSp, o);\n }\n float kS = __shfl_sync(0xffffffff, kSp, 0);\n float qS = __shfl_sync(0xffffffff, qSp, 0);\n float old_v = g * kS;\n float delta = beta * (vv - old_v);\n float out_v = scale * (g * qS + delta * QK);\n float4* Sorow = (float4*)(ssm_out + row_base + (long)v * D);\n float4 o4;\n o4.x = g * s[0] + kh[0] * delta;\n o4.y = g * s[1] + kh[1] * delta;\n o4.z = g * s[2] + kh[2] * delta;\n o4.w = g * s[3] + kh[3] * delta;\n Sorow[lane] = o4;\n if (lane == 0) output[((long)b * HV + h) * D + v] = __float2bfloat16(out_v);\n }\n }\n}\n\nvoid gdn_fused_decode_launch(const void* hidden, const void* w_ba, const void* mixed_qkv,\n const void* conv_weight, const void* conv_bias, void* conv_state,\n const void* A_log, const void* dt_bias, float scale, void* ssm_state,\n const void* state_indices, void* output, void* conv_out_scratch,\n void* ba_scratch, void* barrier, long state_stride_0, long qkv_stride,\n long conv_stride_p, long conv_stride_c, long conv_stride_t, int B,\n cudaStream_t stream) {\n constexpr int kBlock = 256;\n constexpr int kWarpsPerBlock = kBlock / 32;\n constexpr int kMaxDevices = 64;\n // Per-device launch-geometry cache. num_sm[dev] doubles as the entry's\n // COMPLETION flag and is therefore published LAST, with release ordering:\n // a second launcher thread that sees it non-zero must also see the two\n // occupancy values. Writing it first (and the occupancies after) would let\n // such a thread read blocks_per_sm_*[dev] == 0, collapse `cap` to 0 and run\n // the persistent kernel on a single block -- still correct (both the\n // barrier and the delta loop are grid-size agnostic) but orders of\n // magnitude slower, and only on the unlucky interleaving. Two threads\n // filling the entry concurrently is harmless: the queries are pure and\n // return identical values.\n static int blocks_per_sm_b1[kMaxDevices] = {0};\n static int blocks_per_sm_gen[kMaxDevices] = {0};\n static std::atomic<int> num_sm[kMaxDevices] = {};\n int dev = 0;\n cudaGetDevice(&dev);\n if (dev < 0 || dev >= kMaxDevices) dev = 0;\n int sm_count = num_sm[dev].load(std::memory_order_acquire);\n if (sm_count == 0) {\n int occ_b1 = 0;\n int occ_gen = 0;\n cudaDeviceGetAttribute(&sm_count, cudaDevAttrMultiProcessorCount, dev);\n cudaOccupancyMaxActiveBlocksPerMultiprocessor(&occ_b1, gdn_fused_decode_kernel<true>, kBlock,\n 0);\n cudaOccupancyMaxActiveBlocksPerMultiprocessor(&occ_gen, gdn_fused_decode_kernel<false>, kBlock,\n 0);\n blocks_per_sm_b1[dev] = occ_b1;\n blocks_per_sm_gen[dev] = occ_gen;\n num_sm[dev].store(sm_count, std::memory_order_release);\n }\n // Grid must be <= resident capacity (persistent barrier needs co-residency),\n // but no larger than needed. Delta single-pass needs\n // ceil(rows / ROWS_PER_WARP / warps-per-block) blocks -- derived from kBlock\n // so the two cannot drift apart.\n long rows = (long)B * HV * D;\n long warps_needed = (rows + ROWS_PER_WARP - 1) / ROWS_PER_WARP;\n int delta_blocks = (int)((warps_needed + kWarpsPerBlock - 1) / kWarpsPerBlock);\n int cap = (B == 1 ? blocks_per_sm_b1[dev] : blocks_per_sm_gen[dev]) * sm_count;\n int grid = delta_blocks < cap ? delta_blocks : cap;\n if (grid < 1) grid = 1;\n // No per-call barrier reset: the barrier is zero-initialized at allocation\n // and self-resetting across launches (see grid_barrier).\n if (B == 1) {\n gdn_fused_decode_kernel<true><<<grid, kBlock, 0, stream>>>(\n static_cast<const bf16*>(hidden), static_cast<const bf16*>(w_ba),\n static_cast<const bf16*>(mixed_qkv), static_cast<const bf16*>(conv_weight),\n static_cast<const bf16*>(conv_bias), static_cast<const bf16*>(conv_state),\n static_cast<const float*>(A_log), static_cast<const bf16*>(dt_bias),\n static_cast<const float*>(ssm_state), static_cast<const int*>(state_indices), scale,\n state_stride_0, qkv_stride, conv_stride_p, conv_stride_c, conv_stride_t,\n static_cast<bf16*>(output), static_cast<bf16*>(conv_state), static_cast<float*>(ssm_state),\n static_cast<float*>(ba_scratch), static_cast<bf16*>(conv_out_scratch),\n static_cast<unsigned*>(barrier), B);\n } else {\n gdn_fused_decode_kernel<false><<<grid, kBlock, 0, stream>>>(\n static_cast<const bf16*>(hidden), static_cast<const bf16*>(w_ba),\n static_cast<const bf16*>(mixed_qkv), static_cast<const bf16*>(conv_weight),\n static_cast<const bf16*>(conv_bias), static_cast<const bf16*>(conv_state),\n static_cast<const float*>(A_log), static_cast<const bf16*>(dt_bias),\n static_cast<const float*>(ssm_state), static_cast<const int*>(state_indices), scale,\n state_stride_0, qkv_stride, conv_stride_p, conv_stride_c, conv_stride_t,\n static_cast<bf16*>(output), static_cast<bf16*>(conv_state), static_cast<float*>(ssm_state),\n static_cast<float*>(ba_scratch), static_cast<bf16*>(conv_out_scratch),\n static_cast<unsigned*>(barrier), B);\n }\n}\n\n} // namespace\n\nvoid gdn_fused_decode(TensorView hidden_states, TensorView w_ba, TensorView mixed_qkv,\n TensorView conv_weight, TensorView conv_bias, TensorView conv_state,\n TensorView A_log, TensorView dt_bias, TensorView ssm_state,\n TensorView state_indices, TensorView output, TensorView conv_out_scratch,\n TensorView ba_scratch, TensorView barrier, double scale) {\n CHECK_INPUT_TYPE(hidden_states, dl_bfloat16);\n CHECK_INPUT_TYPE(w_ba, dl_bfloat16);\n CHECK_INPUT_TYPE(mixed_qkv, dl_bfloat16);\n CHECK_INPUT_TYPE(conv_weight, dl_bfloat16);\n CHECK_INPUT_TYPE(conv_bias, dl_bfloat16);\n CHECK_INPUT_TYPE(conv_state, dl_bfloat16);\n CHECK_INPUT_TYPE(A_log, dl_float32);\n CHECK_INPUT_TYPE(dt_bias, dl_bfloat16);\n CHECK_INPUT_TYPE(ssm_state, dl_float32);\n CHECK_INPUT_TYPE(state_indices, dl_int32);\n CHECK_INPUT_TYPE(output, dl_bfloat16);\n CHECK_INPUT_TYPE(conv_out_scratch, dl_bfloat16);\n CHECK_INPUT_TYPE(ba_scratch, dl_float32);\n CHECK_INPUT_TYPE(barrier, dl_int32);\n\n CHECK_DIM(2, hidden_states);\n CHECK_DIM(2, w_ba);\n CHECK_DIM(2, mixed_qkv);\n CHECK_DIM(2, conv_weight);\n CHECK_DIM(1, conv_bias);\n CHECK_DIM(3, conv_state);\n CHECK_DIM(1, A_log);\n CHECK_DIM(1, dt_bias);\n CHECK_DIM(4, ssm_state);\n CHECK_DIM(1, state_indices);\n CHECK_DIM(4, output);\n CHECK_DIM(2, conv_out_scratch);\n CHECK_DIM(1, ba_scratch);\n CHECK_DIM(1, barrier);\n\n const int B = static_cast<int>(hidden_states.size(0));\n TVM_FFI_ICHECK_GT(B, 0);\n TVM_FFI_ICHECK_EQ(hidden_states.size(1), HIDDEN);\n TVM_FFI_ICHECK_EQ(w_ba.size(0), HIDDEN);\n TVM_FFI_ICHECK_EQ(w_ba.size(1), N_BA);\n TVM_FFI_ICHECK_EQ(mixed_qkv.size(0), B);\n TVM_FFI_ICHECK_EQ(mixed_qkv.size(1), QKV_DIM);\n TVM_FFI_ICHECK_EQ(conv_weight.size(0), QKV_DIM);\n TVM_FFI_ICHECK_EQ(conv_weight.size(1), CONV_WIDTH);\n TVM_FFI_ICHECK_EQ(conv_bias.size(0), QKV_DIM);\n TVM_FFI_ICHECK_EQ(conv_state.size(1), QKV_DIM);\n TVM_FFI_ICHECK_EQ(conv_state.size(2), CONV_STATE_LEN);\n TVM_FFI_ICHECK_EQ(A_log.size(0), HV);\n TVM_FFI_ICHECK_EQ(dt_bias.size(0), HV);\n TVM_FFI_ICHECK_EQ(ssm_state.size(1), HV);\n TVM_FFI_ICHECK_EQ(ssm_state.size(2), D);\n TVM_FFI_ICHECK_EQ(ssm_state.size(3), D);\n // state_indices holds SHAPE checks only, deliberately. Its VALUES are a\n // per-row property that lives on the device: a host-side range check would\n // need a device-to-host copy of the index vector on every layer of every\n // decode step, and cannot run at all inside a CUDA-graph capture (which is\n // the regime that produces padded rows in the first place). So the two value\n // classes are handled where they can be:\n // - NEGATIVE (vLLM's PAD_SLOT_ID = -1) is the padding convention. The\n // kernel skips those rows entirely -- neither pool is read or written --\n // and zeroes their output rows, matching the fp32 path of\n // gated_delta_rule_decode_pretranspose.\n // - >= P (the pool's leading extent) is a CALLER BUG, not padding, and is\n // left undefined rather than clamped or silently skipped: clamping would\n // corrupt a real slot without a diagnostic, and skipping would turn a\n // caller's index arithmetic error into silently missing state updates.\n // Conflating it with -1 would make both failure modes invisible.\n TVM_FFI_ICHECK_EQ(state_indices.size(0), B);\n TVM_FFI_ICHECK_EQ(output.size(0), B);\n TVM_FFI_ICHECK_EQ(output.size(1), 1);\n TVM_FFI_ICHECK_EQ(output.size(2), HV);\n TVM_FFI_ICHECK_EQ(output.size(3), D);\n TVM_FFI_ICHECK_EQ(conv_out_scratch.size(0), B);\n TVM_FFI_ICHECK_EQ(conv_out_scratch.size(1), QKV_DIM);\n TVM_FFI_ICHECK_EQ(ba_scratch.size(0), (long)GEMV_NSPLIT * B * N_BA);\n TVM_FFI_ICHECK_EQ(barrier.size(0), 2);\n\n // Dense inner layout everywhere; the fp32 state pool may have a padded row\n // stride (stride(0) >= HV*D*D), which the kernel consumes directly.\n TVM_FFI_ICHECK_EQ(hidden_states.stride(1), 1);\n TVM_FFI_ICHECK_EQ(hidden_states.stride(0), HIDDEN);\n TVM_FFI_ICHECK_EQ(w_ba.stride(1), 1);\n TVM_FFI_ICHECK_EQ(w_ba.stride(0), N_BA);\n TVM_FFI_ICHECK_EQ(mixed_qkv.stride(1), 1);\n // mixed_qkv rows may be strided (a view into a wider fused projection).\n TVM_FFI_ICHECK_GE(mixed_qkv.stride(0), QKV_DIM);\n TVM_FFI_ICHECK_EQ(conv_weight.stride(1), 1);\n TVM_FFI_ICHECK_EQ(conv_weight.stride(0), CONV_WIDTH);\n // conv_state is a logical [P, QKV_DIM, CONV_STATE_LEN] view over one of the\n // two serving pool layouts (page stride may be padded):\n // - DS pool (dim-first, dense rows): strides (p, CONV_STATE_LEN, 1);\n // - SD pool (vLLM default; physical [P, CONV_STATE_LEN, QKV_DIM] passed as\n // its transpose): strides (p, 1, QKV_DIM).\n {\n const long conv_stride_c = static_cast<long>(conv_state.stride(1));\n const long conv_stride_t = static_cast<long>(conv_state.stride(2));\n const bool conv_ds = conv_stride_c == CONV_STATE_LEN && conv_stride_t == 1;\n const bool conv_sd = conv_stride_c == 1 && conv_stride_t == QKV_DIM;\n TVM_FFI_ICHECK(conv_ds || conv_sd)\n << \"conv_state must be a DS-dense pool or a transposed SD pool view\";\n TVM_FFI_ICHECK_GE(conv_state.stride(0), (long)QKV_DIM * CONV_STATE_LEN);\n }\n TVM_FFI_ICHECK_EQ(ssm_state.stride(3), 1);\n TVM_FFI_ICHECK_EQ(ssm_state.stride(2), D);\n TVM_FFI_ICHECK_EQ(ssm_state.stride(1), (long)D * D);\n TVM_FFI_ICHECK_GE(ssm_state.stride(0), (long)HV * D * D);\n // The delta phase loads and stores whole state rows as float4, so every row\n // base -- idx*stride(0) + h*D*D + v*D -- must be 16B aligned. D*D and v*D\n // already are; a padded page stride is the only term that can break it, and\n // an odd pad would fault rather than degrade.\n TVM_FFI_ICHECK_EQ(ssm_state.stride(0) % 4, 0)\n << \"ssm_state page stride must be a multiple of 4 floats (float4 row access)\";\n TVM_FFI_ICHECK_EQ(output.stride(3), 1);\n TVM_FFI_ICHECK_EQ(output.stride(2), D);\n // The kernel addresses output as one dense [B, 1, HV, D] block\n // (output[((b*HV) + h)*D + v]), so the batch stride is not free either: a\n // destination that is dense per row but strided across the batch (a slice of\n // a wider buffer) would be written at the wrong offsets rather than\n // rejected. stride(1) is deliberately NOT checked -- that axis has extent 1,\n // so the kernel never uses its stride and torch leaves it unconstrained on\n // otherwise contiguous tensors; checking it could reject a valid buffer, and\n // a rejection here latches the whole impl off.\n TVM_FFI_ICHECK_EQ(output.stride(0), (long)HV * D);\n\n const long state_stride_0 = static_cast<long>(ssm_state.stride(0));\n const long qkv_stride = static_cast<long>(mixed_qkv.stride(0));\n const long conv_stride_p = static_cast<long>(conv_state.stride(0));\n const long conv_stride_c = static_cast<long>(conv_state.stride(1));\n const long conv_stride_t = static_cast<long>(conv_state.stride(2));\n\n ffi::CUDADeviceGuard device_guard(hidden_states.device().device_id);\n const cudaStream_t stream = get_stream(hidden_states.device());\n gdn_fused_decode_launch(\n hidden_states.data_ptr(), w_ba.data_ptr(), mixed_qkv.data_ptr(), conv_weight.data_ptr(),\n conv_bias.data_ptr(), conv_state.data_ptr(), A_log.data_ptr(), dt_bias.data_ptr(),\n static_cast<float>(scale), ssm_state.data_ptr(), state_indices.data_ptr(), output.data_ptr(),\n conv_out_scratch.data_ptr(), ba_scratch.data_ptr(), barrier.data_ptr(), state_stride_0,\n qkv_stride, conv_stride_p, conv_stride_c, conv_stride_t, B, stream);\n\n cudaError_t status = cudaGetLastError();\n TVM_FFI_ICHECK(status == cudaSuccess)\n << \"gdn_fused_decode failed with error code \" << cudaGetErrorString(status);\n}\n\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(gdn_fused_decode, gdn_fused_decode);\n"},"diff":{"kind":"string","value":"--- flashinfer/gdn_kernels/experimental/kernel/gdn_fused_decode_sm120.cu\n+++ flashinfer/gdn_kernels/experimental/kernel/gdn_fused_decode_sm120.cu\n@@ -24,23 +24,54 @@\n \n namespace {\n \n-// Fused GDN decode step for a fixed traced layer geometry: one persistent\n-// kernel covering the in_proj_ba GEMV, the depthwise causal conv1d update\n-// (width 4, silu), the q/k/v head split, and the gated delta-rule state\n-// update with qk-L2-norm, replacing the multi-launch serving chain.\n-constexpr int HIDDEN = 5120;\n-constexpr int N_BA = 96;\n-constexpr int QKV_DIM = 10240;\n-constexpr int H_Q = 16;\n-constexpr int HV = 48;\n-constexpr int D = 128;\n-constexpr int CONV_WIDTH = 4;\n-constexpr int CONV_STATE_LEN = 3;\n-constexpr int HEADS_PER_QK = 3;\n+// Fused GDN decode step for one layer geometry: a single persistent kernel\n+// covering the in_proj_ba GEMV, the depthwise causal conv1d update (width 4,\n+// silu), the q/k/v head split, and the gated delta-rule state update with\n+// qk-L2-norm, replacing the multi-launch serving chain.\n+//\n+// The layer geometry is a compile-time parameter of this translation unit,\n+// supplied by flashinfer/jit/gdn_fused_decode.py as -D defines (one JIT\n+// module per geometry; a serving process runs one model, hence one module).\n+// Only the sizes change: the block shape, warp->row mapping and reduction\n+// trees below are geometry-independent, and the static_asserts state exactly\n+// which divisibility relations the code relies on.\n+#if !defined(FI_GDN_HIDDEN) || !defined(FI_GDN_N_BA) || !defined(FI_GDN_QKV_DIM) || \\\n+ !defined(FI_GDN_H_Q) || !defined(FI_GDN_HV) || !defined(FI_GDN_D) || \\\n+ !defined(FI_GDN_CONV_WIDTH) || !defined(FI_GDN_CONV_STATE_LEN)\n+#error \"gdn_fused_decode_sm120.cu requires the FI_GDN_* geometry defines\"\n+#endif\n+constexpr int HIDDEN = FI_GDN_HIDDEN;\n+constexpr int N_BA = FI_GDN_N_BA;\n+constexpr int QKV_DIM = FI_GDN_QKV_DIM;\n+constexpr int H_Q = FI_GDN_H_Q;\n+constexpr int HV = FI_GDN_HV;\n+constexpr int D = FI_GDN_D;\n+constexpr int CONV_WIDTH = FI_GDN_CONV_WIDTH;\n+constexpr int CONV_STATE_LEN = FI_GDN_CONV_STATE_LEN;\n+// v-heads per qk-head: the delta phase maps v-head h to qk-head h/HEADS_PER_QK.\n+constexpr int HEADS_PER_QK = HV / H_Q;\n constexpr int ROWS_PER_WARP = 8;\n constexpr int GEMV_NSPLIT = 160;\n // The gate reduction below unrolls the GEMV partials as 5 warp-wide loads.\n static_assert(GEMV_NSPLIT == 5 * 32, \"gate reduction assumes 5 warp-strided loads\");\n+// The b/a projection produces HV gate values and HV decay values, stored as\n+// the low and high halves of the N_BA columns (see the delta phase's\n+// base_b/base_a offsets).\n+static_assert(N_BA == 2 * HV, \"w_ba columns are [b gates | a decays], HV each\");\n+static_assert(HV % H_Q == 0, \"each qk-head must serve a whole number of v-heads\");\n+// The delta phase gives each lane 4 consecutive channels of a D-wide row and\n+// reduces across the warp; the B=1 fast path indexes rows with shifts/masks.\n+static_assert(D == 4 * 32, \"delta phase maps one D-wide row onto a warp, 4 per lane\");\n+static_assert((D & (D - 1)) == 0, \"B=1 row index math uses D as a power of two\");\n+static_assert(D % ROWS_PER_WARP == 0, \"warps own whole groups of state rows\");\n+// mixed_qkv is [q | k | v] with H_Q q-heads, H_Q k-heads and HV v-heads.\n+static_assert(QKV_DIM == (2 * H_Q + HV) * D, \"qkv_dim must match the head split\");\n+// The conv phase is unrolled over the width-4 / 3-step shift register below.\n+static_assert(CONV_WIDTH == 4 && CONV_STATE_LEN == 3, \"conv taps are unrolled as width 4\");\n+\n+// log2(D), for the B=1 fast path's shift/mask row indexing.\n+constexpr int ilog2_ce(int v) { return v <= 1 ? 0 : 1 + ilog2_ce(v >> 1); }\n+constexpr int D_LOG2 = ilog2_ce(D);\n \n typedef __nv_bfloat16 bf16;\n \n@@ -148,8 +179,8 @@\n const int Beff = kB1 ? 1 : B;\n \n // ---- Phase A1: GEMV partials ----\n- // tasks: (split in 0..GEMV_NSPLIT-1) x (b) x (col in 0..95). Partials are\n- // stored split-major per (col, b) so the gate reduction reads them with\n+ // tasks: (split in 0..GEMV_NSPLIT-1) x (b) x (col in 0..N_BA-1). Partials\n+ // are stored split-major per (col, b) so the gate reduction reads them with\n // warp-coalesced loads.\n long gemv_tasks = (long)GEMV_NSPLIT * Beff * N_BA;\n for (long t = tid; t < gemv_tasks; t += nthreads) {\n@@ -237,7 +268,7 @@\n int b;\n if constexpr (kB1) {\n v0 = (int)(first_row & (D - 1));\n- h = (int)(first_row >> 7);\n+ h = (int)(first_row >> D_LOG2);\n b = 0;\n } else {\n v0 = first_row % D;\n@@ -267,7 +298,7 @@\n int b;\n if constexpr (kB1) {\n v0 = (int)(first_row & (D - 1));\n- h = (int)(first_row >> 7);\n+ h = (int)(first_row >> D_LOG2);\n b = 0;\n } else {\n v0 = first_row % D;"},"lines_added":{"kind":"number","value":48,"string":"48"},"lines_removed":{"kind":"number","value":17,"string":"17"},"files_in_commit":{"kind":"number","value":6,"string":"6"},"models_mentioned":{"kind":"list like","value":["qwen"],"string":"[\n \"qwen\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["SM120"],"string":"[\n \"SM120\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (flashinfer/gdn_kernels/experimental/kernel/gdn_fused_decode_sm120.cu).\n\nGoal: (perf) add fused_GDN_step support for Qwen 3.6 35B A3B on sm120\nTarget hardware: SM120\nTarget models: qwen\n\nCurrent file:\n```cuda\n/*\n * Copyright (c) 2026 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <cuda_bf16.h>\n#include <cuda_runtime.h>\n#include <math.h>\n\n#include <atomic>\n\n#include \"tvm_ffi_utils.h\"\n\nnamespace {\n\n// Fused GDN decode step for a fixed traced layer geometry: one persistent\n// kernel covering the in_proj_ba GEMV, the depthwise causal conv1d update\n// (width 4, silu), the q/k/v head split, and the gated delta-rule state\n// update with qk-L2-norm, replacing the multi-launch serving chain.\nconstexpr int HIDDEN = 5120;\nconstexpr int N_BA = 96;\nconstexpr int QKV_DIM = 10240;\nconstexpr int H_Q = 16;\nconstexpr int HV = 48;\nconstexpr int D = 128;\nconstexpr int CONV_WIDTH = 4;\nconstexpr int CONV_STATE_LEN = 3;\nconstexpr int HEADS_PER_QK = 3;\nconstexpr int ROWS_PER_WARP = 8;\nconstexpr int GEMV_NSPLIT = 160;\n// The gate reduction below unrolls the GEMV partials as 5 warp-wide loads.\nstatic_assert(GEMV_NSPLIT == 5 * 32, \"gate reduction assumes 5 warp-strided loads\");\n\ntypedef __nv_bfloat16 bf16;\n\n__device__ __forceinline__ float siluf(float x) { return x / (1.0f + __expf(-x)); }\n__device__ __forceinline__ float sigmoidf(float x) { return 1.0f / (1.0f + __expf(-x)); }\n__device__ __forceinline__ float softplusf(float x) { return x > 20.0f ? x : log1pf(__expf(x)); }\n__device__ __forceinline__ float warp_reduce(float v) {\n#pragma unroll\n for (int o = 16; o > 0; o >>= 1) v += __shfl_down_sync(0xffffffff, v, o);\n return v;\n}\n\n// Reusable device-wide barrier (regular launch -> graph-capturable) that\n// needs no host-side reset between launches: barrier[0] is the arrival\n// counter (reset by the releasing block before it releases), barrier[1] is a\n// monotonic release generation. Each block samples the generation at its own\n// arrival; release of the current launch cannot precede that sample, and the\n// previous launch's release is stream-ordered before this kernel starts, so\n// the sampled value is uniform. The generation spin uses equality, so counter\n// wrap-around is harmless, and the arrival reset keeps the barrier correct\n// when consecutive launches use different grid sizes.\n// Requires: barrier zero-initialized once at allocation, all blocks\n// co-resident (grid capped to occupancy), and at most one kernel using the\n// buffer in flight (single-stream use; the in-place state pools already\n// require this).\n//\n// Memory ordering: the barrier is release/acquire, not just a flag.\n// - Release: the block that completes the count fences before bumping the\n// generation, so every pre-barrier write of every block that arrived\n// before it is visible at the point the generation changes.\n// - Acquire: a block leaving the barrier fences AGAIN before its\n// post-barrier reads. Observing the new generation through a volatile\n// (L2-serviced) load only orders that one location; without the leaving\n// fence, a subsequent ordinary load of ba_part / conv_out -- written by a\n// *different* block, i.e. potentially a different SM -- may be serviced\n// from a stale non-coherent L1 line or be hoisted by the compiler above\n// the spin. This mirrors cooperative_groups' own grid barrier, which\n// calls its `bar_flush()` (a __threadfence) on the way out for exactly\n// this reason. The fence is executed by the same thread that spun and is\n// followed by __syncthreads(), which propagates the ordering to the rest\n// of the block.\n__device__ __forceinline__ void grid_barrier(volatile unsigned* barrier, int nblocks) {\n __syncthreads();\n if (threadIdx.x == 0) {\n unsigned gen = barrier[1];\n __threadfence();\n unsigned arrived = atomicAdd((unsigned*)&barrier[0], 1u) + 1u;\n if (arrived == (unsigned)nblocks) {\n barrier[0] = 0u; // reset the arrival counter for the next launch\n __threadfence();\n atomicAdd((unsigned*)&barrier[1], 1u); // release everyone\n } else {\n while (barrier[1] == gen) { /* spin */\n }\n }\n __threadfence(); // acquire: peers' pre-barrier writes before our reads\n }\n __syncthreads();\n}\n\n// Single persistent kernel: gemv+conv -> [barrier] -> delta. Regular launch.\n// The kB1 instantiation specializes the serving-hot B=1 case: batch/split\n// index math collapses to compile-time constants and the fp32 state rows for\n// the (single) delta task of each warp are prefetched before the barrier so\n// their long-scoreboard latency overlaps the gemv/conv phases (the state pool\n// is only written after the barrier, each row by the warp that prefetched it).\n//\n// Padded batch rows: a NEGATIVE state index (vLLM's PAD_SLOT_ID = -1) marks a\n// batch row that owns no pool slot -- what a CUDA-graph replay carries in the\n// rows between the live request count and the captured batch size. Such a row\n// is skipped in every phase that touches a pool (no read and no write of\n// conv_state / ssm_state) and its output rows are written as zero, matching\n// the fp32 path of gated_delta_rule_decode_pretranspose. The check has to be\n// here rather than on the host: reading index VALUES host-side costs a\n// device-to-host sync per layer per decode step and is impossible under graph\n// capture. Each guard is uniform over the threads that share a batch row\n// (warp-uniform in the delta phase, where the warp-wide shuffles below make\n// divergence unacceptable), so it costs one predicated branch, not divergence.\n// Indices >= P are NOT padding and are not checked -- see the note on\n// state_indices in the FFI entry point below.\n//\n// Aliasing: the op updates both state pools IN PLACE, so the launcher passes\n// the same pointer for (conv_state, updated_conv) and for (ssm_state,\n// ssm_out). Those four parameters therefore carry no __restrict__ -- the\n// pools are read and written through two different parameters, which is\n// exactly what restrict promises does not happen, and promising it would let\n// the compiler reorder a pool load across a pool store. The remaining\n// pointers are genuinely disjoint buffers and keep the qualifier. The read\n// path pays for this: loads from the pools can no longer be promoted to\n// ld.global.nc. Only this impl is affected -- the registry prefers the\n// CuTe-DSL kernel for every shipped row -- and correctness is not a thing to\n// trade for a read-only-cache hint.\ntemplate <bool kB1>\n__global__ void gdn_fused_decode_kernel(\n const bf16* __restrict__ hidden, const bf16* __restrict__ w_ba,\n const bf16* __restrict__ mixed_qkv, const bf16* __restrict__ conv_weight,\n const bf16* __restrict__ conv_bias, const bf16* conv_state, const float* __restrict__ A_log,\n const bf16* __restrict__ dt_bias, const float* ssm_state, const int* __restrict__ state_indices,\n float scale, long state_stride_0, long qkv_stride, long conv_stride_p, long conv_stride_c,\n long conv_stride_t, bf16* __restrict__ output, bf16* updated_conv, float* ssm_out,\n float* __restrict__ ba_part, bf16* __restrict__ conv_out, unsigned* __restrict__ barrier,\n int B) {\n int tid = blockIdx.x * blockDim.x + threadIdx.x;\n int nthreads = gridDim.x * blockDim.x;\n const int Beff = kB1 ? 1 : B;\n\n // ---- Phase A1: GEMV partials ----\n // tasks: (split in 0..GEMV_NSPLIT-1) x (b) x (col in 0..95). Partials are\n // stored split-major per (col, b) so the gate reduction reads them with\n // warp-coalesced loads.\n long gemv_tasks = (long)GEMV_NSPLIT * Beff * N_BA;\n for (long t = tid; t < gemv_tasks; t += nthreads) {\n int col = t % N_BA;\n long r = t / N_BA;\n int b;\n int split;\n if constexpr (kB1) {\n b = 0;\n split = (int)r;\n } else {\n b = r % B;\n split = r / B;\n }\n const bf16* hrow = hidden + (long)b * HIDDEN;\n float a0 = 0, a1 = 0, a2 = 0, a3 = 0;\n int k = split;\n for (; k + 3 * GEMV_NSPLIT < HIDDEN; k += 4 * GEMV_NSPLIT) {\n a0 += __bfloat162float(hrow[k]) * __bfloat162float(w_ba[(long)k * N_BA + col]);\n a1 += __bfloat162float(hrow[k + GEMV_NSPLIT]) *\n __bfloat162float(w_ba[(long)(k + GEMV_NSPLIT) * N_BA + col]);\n a2 += __bfloat162float(hrow[k + 2 * GEMV_NSPLIT]) *\n __bfloat162float(w_ba[(long)(k + 2 * GEMV_NSPLIT) * N_BA + col]);\n a3 += __bfloat162float(hrow[k + 3 * GEMV_NSPLIT]) *\n __bfloat162float(w_ba[(long)(k + 3 * GEMV_NSPLIT) * N_BA + col]);\n }\n for (; k < HIDDEN; k += GEMV_NSPLIT)\n a0 += __bfloat162float(hrow[k]) * __bfloat162float(w_ba[(long)k * N_BA + col]);\n ba_part[((long)col * Beff + b) * GEMV_NSPLIT + split] = (a0 + a1) + (a2 + a3);\n }\n\n // ---- Phase A2: conv (independent of gemv) ----\n long conv_tasks = (long)Beff * QKV_DIM;\n for (long t = tid; t < conv_tasks; t += nthreads) {\n int b;\n int c;\n if constexpr (kB1) {\n b = 0;\n c = (int)t;\n } else {\n b = t / QKV_DIM;\n c = t % QKV_DIM;\n }\n int idx = state_indices[b];\n // Padded row: owns no conv-state slot, so neither shift it nor append to\n // it. conv_out for this row stays whatever the scratch held -- the delta\n // phase skips the same row, so nothing reads it.\n if (idx < 0) continue;\n // conv_state addressing is stride-parameterized: the pool arrives as a\n // logical [P, QKV_DIM, CONV_STATE_LEN] view of either a DS-dense pool\n // (strides p,3,1 -> per-thread 3-element rows) or a transposed SD pool\n // (strides p,1,QKV_DIM -> fully coalesced across channels, the vLLM\n // default). Pure index arithmetic; the update math is identical.\n const bf16* st = conv_state + (long)idx * conv_stride_p + (long)c * conv_stride_c;\n bf16 s0 = st[0], s1 = st[conv_stride_t], s2 = st[2 * conv_stride_t];\n // mixed_qkv rows may be strided (e.g. a view into a wider projection).\n bf16 xr = mixed_qkv[(long)b * qkv_stride + c];\n const bf16* w = conv_weight + (long)c * CONV_WIDTH;\n float y = __bfloat162float(s0) * __bfloat162float(w[0]) +\n __bfloat162float(s1) * __bfloat162float(w[1]) +\n __bfloat162float(s2) * __bfloat162float(w[2]) +\n __bfloat162float(xr) * __bfloat162float(w[3]) + __bfloat162float(conv_bias[c]);\n conv_out[(long)b * QKV_DIM + c] = __float2bfloat16(siluf(y));\n bf16* uc = updated_conv + (long)idx * conv_stride_p + (long)c * conv_stride_c;\n uc[0] = s1;\n uc[conv_stride_t] = s2;\n uc[2 * conv_stride_t] = xr;\n }\n\n // ---- Pre-barrier prefetch of this warp's first delta task's state rows.\n // The state pool is read-only until phase C, and each row is written only\n // by the warp that owns (and prefetched) it, so this is race-free.\n int gwarp = tid >> 5;\n int lane = threadIdx.x & 31;\n int nwarps = nthreads >> 5;\n long total_rows = (long)Beff * HV * D;\n long warps_needed = (total_rows + ROWS_PER_WARP - 1) / ROWS_PER_WARP;\n\n float4 s_pre[ROWS_PER_WARP];\n long pre_row_base = -1;\n if (gwarp < warps_needed) {\n long first_row = (long)gwarp * ROWS_PER_WARP;\n int v0;\n int h;\n int b;\n if constexpr (kB1) {\n v0 = (int)(first_row & (D - 1));\n h = (int)(first_row >> 7);\n b = 0;\n } else {\n v0 = first_row % D;\n long tmp = first_row / D;\n h = tmp % HV;\n b = tmp / HV;\n }\n int idx = state_indices[b];\n // A padded row has no state row to prefetch. pre_row_base stays -1, which\n // no live row_base can equal, so the delta phase never mistakes the\n // (unwritten) s_pre registers for this warp's prefetched rows.\n if (idx >= 0) {\n pre_row_base = (long)idx * state_stride_0 + (long)h * (D * D);\n const float4* base_srow = (const float4*)(ssm_state + pre_row_base + (long)v0 * D);\n#pragma unroll\n for (int r = 0; r < ROWS_PER_WARP; ++r) s_pre[r] = base_srow[r * (D / 4) + lane];\n }\n }\n\n grid_barrier(barrier, gridDim.x);\n\n // ---- Phase C: delta (gate reduced inline from ba_part) ----\n for (long w = gwarp; w < warps_needed; w += nwarps) {\n long first_row = w * ROWS_PER_WARP;\n int v0;\n int h;\n int b;\n if constexpr (kB1) {\n v0 = (int)(first_row & (D - 1));\n h = (int)(first_row >> 7);\n b = 0;\n } else {\n v0 = first_row % D;\n long tmp = first_row / D;\n h = tmp % HV;\n b = tmp / HV;\n }\n int j = h / HEADS_PER_QK;\n const bf16* co = conv_out + (long)b * QKV_DIM;\n const bf16* qb = co + j * D;\n const bf16* kb = co + H_Q * D + j * D;\n int k0 = lane * 4;\n int idx = state_indices[b];\n if (idx < 0) {\n // Padded row: no state row to read or write; its output rows are zero.\n // b (hence idx) is warp-uniform -- first_row is a multiple of\n // ROWS_PER_WARP and the whole warp shares w -- so the whole warp takes\n // this branch together and the warp-wide shuffles below are never\n // reached with a partial mask.\n if (lane == 0) {\n#pragma unroll\n for (int r = 0; r < ROWS_PER_WARP; ++r)\n output[((long)b * HV + h) * D + v0 + r] = __float2bfloat16(0.0f);\n }\n continue;\n }\n long row_base = (long)idx * state_stride_0 + (long)h * (D * D);\n float4 s4[ROWS_PER_WARP];\n if (w == gwarp && row_base == pre_row_base) {\n // First iteration (the only one for B=1): use the prefetched rows.\n#pragma unroll\n for (int r = 0; r < ROWS_PER_WARP; ++r) s4[r] = s_pre[r];\n } else {\n const float4* base_srow = (const float4*)(ssm_state + row_base + (long)v0 * D);\n#pragma unroll\n for (int r = 0; r < ROWS_PER_WARP; ++r) s4[r] = base_srow[r * (D / 4) + lane];\n }\n // Issue the gate-partial loads early (10 concurrent warp-wide loads) so\n // they overlap the qk-norm compute below.\n const float* base_b = ba_part + ((long)h * Beff + b) * GEMV_NSPLIT;\n const float* base_a = ba_part + ((long)(HV + h) * Beff + b) * GEMV_NSPLIT;\n float b0 = base_b[lane + 0];\n float a0v = base_a[lane + 0];\n float b1 = base_b[lane + 32];\n float a1v = base_a[lane + 32];\n float b2 = base_b[lane + 64];\n float a2v = base_a[lane + 64];\n float b3 = base_b[lane + 96];\n float a3v = base_a[lane + 96];\n float b4 = base_b[lane + 128];\n float a4v = base_a[lane + 128];\n float qraw[4], kraw[4];\n float qss = 0.f, kss = 0.f;\n#pragma unroll\n for (int i = 0; i < 4; ++i) {\n qraw[i] = __bfloat162float(qb[k0 + i]);\n kraw[i] = __bfloat162float(kb[k0 + i]);\n qss += qraw[i] * qraw[i];\n kss += kraw[i] * kraw[i];\n }\n qss = warp_reduce(qss);\n kss = warp_reduce(kss);\n qss = __shfl_sync(0xffffffff, qss, 0);\n kss = __shfl_sync(0xffffffff, kss, 0);\n float qn = rsqrtf(qss + 1e-6f), kn = rsqrtf(kss + 1e-6f);\n float qh[4], kh[4], QKp = 0.f;\n#pragma unroll\n for (int i = 0; i < 4; ++i) {\n qh[i] = qraw[i] * qn;\n kh[i] = kraw[i] * kn;\n QKp += qh[i] * kh[i];\n }\n QKp = warp_reduce(QKp);\n float QK = __shfl_sync(0xffffffff, QKp, 0);\n // gate g,beta reduced from the split-major partials (values now arrived)\n float accb = ((b0 + b1) + (b2 + b3)) + b4;\n float acca = ((a0v + a1v) + (a2v + a3v)) + a4v;\n accb = warp_reduce(accb);\n acca = warp_reduce(acca);\n accb = __shfl_sync(0xffffffff, accb, 0);\n acca = __shfl_sync(0xffffffff, acca, 0);\n // The bf16 round-trip of the two gate sums is load-bearing, not a leftover:\n // the composable path materializes `ba = (hidden @ w_ba)` as a bf16 tensor\n // and only then widens it for the gates, so the values it feeds\n // sigmoid/softplus are bf16-rounded. Keeping the fp32 accumulator here\n // would make this kernel *more* precise than the operation it implements\n // and move the gates off the reference by up to one bf16 ulp -- amplified\n // by exp() in the decay gate. Track the composable path's `ba` dtype, not\n // the accumulator's.\n float beta = sigmoidf(__bfloat162float(__float2bfloat16(accb)));\n float xg = __bfloat162float(__float2bfloat16(acca)) + __bfloat162float(dt_bias[h]);\n float g = __expf(-__expf(A_log[h]) * softplusf(xg));\n#pragma unroll\n for (int r = 0; r < ROWS_PER_WARP; ++r) {\n int v = v0 + r;\n float s[4] = {s4[r].x, s4[r].y, s4[r].z, s4[r].w};\n float vv = __bfloat162float(co[2 * H_Q * D + h * D + v]);\n float kSp = 0.f, qSp = 0.f;\n#pragma unroll\n for (int i = 0; i < 4; ++i) {\n kSp += kh[i] * s[i];\n qSp += qh[i] * s[i];\n }\n#pragma unroll\n for (int o = 16; o > 0; o >>= 1) {\n kSp += __shfl_down_sync(0xffffffff, kSp, o);\n qSp += __shfl_down_sync(0xffffffff, qSp, o);\n }\n float kS = __shfl_sync(0xffffffff, kSp, 0);\n float qS = __shfl_sync(0xffffffff, qSp, 0);\n float old_v = g * kS;\n float delta = beta * (vv - old_v);\n float out_v = scale * (g * qS + delta * QK);\n float4* Sorow = (float4*)(ssm_out + row_base + (long)v * D);\n float4 o4;\n o4.x = g * s[0] + kh[0] * delta;\n o4.y = g * s[1] + kh[1] * delta;\n o4.z = g * s[2] + kh[2] * delta;\n o4.w = g * s[3] + kh[3] * delta;\n Sorow[lane] = o4;\n if (lane == 0) output[((long)b * HV + h) * D + v] = __float2bfloat16(out_v);\n }\n }\n}\n\nvoid gdn_fused_decode_launch(const void* hidden, const void* w_ba, const void* mixed_qkv,\n const void* conv_weight, const void* conv_bias, void* conv_state,\n const void* A_log, const void* dt_bias, float scale, void* ssm_state,\n const void* state_indices, void* output, void* conv_out_scratch,\n void* ba_scratch, void* barrier, long state_stride_0, long qkv_stride,\n long conv_stride_p, long conv_stride_c, long conv_stride_t, int B,\n cudaStream_t stream) {\n constexpr int kBlock = 256;\n constexpr int kWarpsPerBlock = kBlock / 32;\n constexpr int kMaxDevices = 64;\n // Per-device launch-geometry cache. num_sm[dev] doubles as the entry's\n // COMPLETION flag and is therefore published LAST, with release ordering:\n // a second launcher thread that sees it non-zero must also see the two\n // occupancy values. Writing it first (and the occupancies after) would let\n // such a thread read blocks_per_sm_*[dev] == 0, collapse `cap` to 0 and run\n // the persistent kernel on a single block -- still correct (both the\n // barrier and the delta loop are grid-size agnostic) but orders of\n // magnitude slower, and only on the unlucky interleaving. Two threads\n // filling the entry concurrently is harmless: the queries are pure and\n // return identical values.\n static int blocks_per_sm_b1[kMaxDevices] = {0};\n static int blocks_per_sm_gen[kMaxDevices] = {0};\n static std::atomic<int> num_sm[kMaxDevices] = {};\n int dev = 0;\n cudaGetDevice(&dev);\n if (dev < 0 || dev >= kMaxDevices) dev = 0;\n int sm_count = num_sm[dev].load(std::memory_order_acquire);\n if (sm_count == 0) {\n int occ_b1 = 0;\n int occ_gen = 0;\n cudaDeviceGetAttribute(&sm_count, cudaDevAttrMultiProcessorCount, dev);\n cudaOccupancyMaxActiveBlocksPerMultiprocessor(&occ_b1, gdn_fused_decode_kernel<true>, kBlock,\n 0);\n cudaOccupancyMaxActiveBlocksPerMultiprocessor(&occ_gen, gdn_fused_decode_kernel<false>, kBlock,\n 0);\n blocks_per_sm_b1[dev] = occ_b1;\n blocks_per_sm_gen[dev] = occ_gen;\n num_sm[dev].store(sm_count, std::memory_order_release);\n }\n // Grid must be <= resident capacity (persistent barrier needs co-residency),\n // but no larger than needed. Delta single-pass needs\n // ceil(rows / ROWS_PER_WARP / warps-per-block) blocks -- derived from kBlock\n // so the two cannot drift apart.\n long rows = (long)B * HV * D;\n long warps_needed = (rows + ROWS_PER_WARP - 1) / ROWS_PER_WARP;\n int delta_blocks = (int)((warps_needed + kWarpsPerBlock - 1) / kWarpsPerBlock);\n int cap = (B == 1 ? blocks_per_sm_b1[dev] : blocks_per_sm_gen[dev]) * sm_count;\n int grid = delta_blocks < cap ? delta_blocks : cap;\n if (grid < 1) grid = 1;\n // No per-call barrier reset: the barrier is zero-initialized at allocation\n // and self-resetting across launches (see grid_barrier).\n if (B == 1) {\n gdn_fused_decode_kernel<true><<<grid, kBlock, 0, stream>>>(\n static_cast<const bf16*>(hidden), static_cast<const bf16*>(w_ba),\n static_cast<const bf16*>(mixed_qkv), static_cast<const bf16*>(conv_weight),\n static_cast<const bf16*>(conv_bias), static_cast<const bf16*>(conv_state),\n static_cast<const float*>(A_log), static_cast<const bf16*>(dt_bias),\n static_cast<const float*>(ssm_state), static_cast<const int*>(state_indices), scale,\n state_stride_0, qkv_stride, conv_stride_p, conv_stride_c, conv_stride_t,\n static_cast<bf16*>(output), static_cast<bf16*>(conv_state), static_cast<float*>(ssm_state),\n static_cast<float*>(ba_scratch), static_cast<bf16*>(conv_out_scratch),\n static_cast<unsigned*>(barrier), B);\n } else {\n gdn_fused_decode_kernel<false><<<grid, kBlock, 0, stream>>>(\n static_cast<const bf16*>(hidden), static_cast<const bf16*>(w_ba),\n static_cast<const bf16*>(mixed_qkv), static_cast<const bf16*>(conv_weight),\n static_cast<const bf16*>(conv_bias), static_cast<const bf16*>(conv_state),\n static_cast<const float*>(A_log), static_cast<const bf16*>(dt_bias),\n static_cast<const float*>(ssm_state), static_cast<const int*>(state_indices), scale,\n state_stride_0, qkv_stride, conv_stride_p, conv_stride_c, conv_stride_t,\n static_cast<bf16*>(output), static_cast<bf16*>(conv_state), static_cast<float*>(ssm_state),\n static_cast<float*>(ba_scratch), static_cast<bf16*>(conv_out_scratch),\n static_cast<unsigned*>(barrier), B);\n }\n}\n\n} // namespace\n\nvoid gdn_fused_decode(TensorView hidden_states, TensorView w_ba, TensorView mixed_qkv,\n TensorView conv_weight, TensorView conv_bias, TensorView conv_state,\n TensorView A_log, TensorView dt_bias, TensorView ssm_state,\n TensorView state_indices, TensorView output, TensorView conv_out_scratch,\n TensorView ba_scratch, TensorView barrier, double scale) {\n CHECK_INPUT_TYPE(hidden_states, dl_bfloat16);\n CHECK_INPUT_TYPE(w_ba, dl_bfloat16);\n CHECK_INPUT_TYPE(mixed_qkv, dl_bfloat16);\n CHECK_INPUT_TYPE(conv_weight, dl_bfloat16);\n CHECK_INPUT_TYPE(conv_bias, dl_bfloat16);\n CHECK_INPUT_TYPE(conv_state, dl_bfloat16);\n CHECK_INPUT_TYPE(A_log, dl_float32);\n CHECK_INPUT_TYPE(dt_bias, dl_bfloat16);\n CHECK_INPUT_TYPE(ssm_state, dl_float32);\n CHECK_INPUT_TYPE(state_indices, dl_int32);\n CHECK_INPUT_TYPE(output, dl_bfloat16);\n CHECK_INPUT_TYPE(conv_out_scratch, dl_bfloat16);\n CHECK_INPUT_TYPE(ba_scratch, dl_float32);\n CHECK_INPUT_TYPE(barrier, dl_int32);\n\n CHECK_DIM(2, hidden_states);\n CHECK_DIM(2, w_ba);\n CHECK_DIM(2, mixed_qkv);\n CHECK_DIM(2, conv_weight);\n CHECK_DIM(1, conv_bias);\n CHECK_DIM(3, conv_state);\n CHECK_DIM(1, A_log);\n CHECK_DIM(1, dt_bias);\n CHECK_DIM(4, ssm_state);\n CHECK_DIM(1, state_indices);\n CHECK_DIM(4, output);\n CHECK_DIM(2, conv_out_scratch);\n CHECK_DIM(1, ba_scratch);\n CHECK_DIM(1, barrier);\n\n const int B = static_cast<int>(hidden_states.size(0));\n TVM_FFI_ICHECK_GT(B, 0);\n TVM_FFI_ICHECK_EQ(hidden_states.size(1), HIDDEN);\n TVM_FFI_ICHECK_EQ(w_ba.size(0), HIDDEN);\n TVM_FFI_ICHECK_EQ(w_ba.size(1), N_BA);\n TVM_FFI_ICHECK_EQ(mixed_qkv.size(0), B);\n TVM_FFI_ICHECK_EQ(mixed_qkv.size(1), QKV_DIM);\n TVM_FFI_ICHECK_EQ(conv_weight.size(0), QKV_DIM);\n TVM_FFI_ICHECK_EQ(conv_weight.size(1), CONV_WIDTH);\n TVM_FFI_ICHECK_EQ(conv_bias.size(0), QKV_DIM);\n TVM_FFI_ICHECK_EQ(conv_state.size(1), QKV_DIM);\n TVM_FFI_ICHECK_EQ(conv_state.size(2), CONV_STATE_LEN);\n TVM_FFI_ICHECK_EQ(A_log.size(0), HV);\n TVM_FFI_ICHECK_EQ(dt_bias.size(0), HV);\n TVM_FFI_ICHECK_EQ(ssm_state.size(1), HV);\n TVM_FFI_ICHECK_EQ(ssm_state.size(2), D);\n TVM_FFI_ICHECK_EQ(ssm_state.size(3), D);\n // state_indices holds SHAPE checks only, deliberately. Its VALUES are a\n // per-row property that lives on the device: a host-side range check would\n // need a device-to-host copy of the index vector on every layer of every\n // decode step, and cannot run at all inside a CUDA-graph capture (which is\n // the regime that produces padded rows in the first place). So the two value\n // classes are handled where they can be:\n // - NEGATIVE (vLLM's PAD_SLOT_ID = -1) is the padding convention. The\n // kernel skips those rows entirely -- neither pool is read or written --\n // and zeroes their output rows, matching the fp32 path of\n // gated_delta_rule_decode_pretranspose.\n // - >= P (the pool's leading extent) is a CALLER BUG, not padding, and is\n // left undefined rather than clamped or silently skipped: clamping would\n // corrupt a real slot without a diagnostic, and skipping would turn a\n // caller's index arithmetic error into silently missing state updates.\n // Conflating it with -1 would make both failure modes invisible.\n TVM_FFI_ICHECK_EQ(state_indices.size(0), B);\n TVM_FFI_ICHECK_EQ(output.size(0), B);\n TVM_FFI_ICHECK_EQ(output.size(1), 1);\n TVM_FFI_ICHECK_EQ(output.size(2), HV);\n TVM_FFI_ICHECK_EQ(output.size(3), D);\n TVM_FFI_ICHECK_EQ(conv_out_scratch.size(0), B);\n TVM_FFI_ICHECK_EQ(conv_out_scratch.size(1), QKV_DIM);\n TVM_FFI_ICHECK_EQ(ba_scratch.size(0), (long)GEMV_NSPLIT * B * N_BA);\n TVM_FFI_ICHECK_EQ(barrier.size(0), 2);\n\n // Dense inner layout everywhere; the fp32 state pool may have a padded row\n // stride (stride(0) >= HV*D*D), which the kernel consumes directly.\n TVM_FFI_ICHECK_EQ(hidden_states.stride(1), 1);\n TVM_FFI_ICHECK_EQ(hidden_states.stride(0), HIDDEN);\n TVM_FFI_ICHECK_EQ(w_ba.stride(1), 1);\n TVM_FFI_ICHECK_EQ(w_ba.stride(0), N_BA);\n TVM_FFI_ICHECK_EQ(mixed_qkv.stride(1), 1);\n // mixed_qkv rows may be strided (a view into a wider fused projection).\n TVM_FFI_ICHECK_GE(mixed_qkv.stride(0), QKV_DIM);\n TVM_FFI_ICHECK_EQ(conv_weight.stride(1), 1);\n TVM_FFI_ICHECK_EQ(conv_weight.stride(0), CONV_WIDTH);\n // conv_state is a logical [P, QKV_DIM, CONV_STATE_LEN] view over one of the\n // two serving pool layouts (page stride may be padded):\n // - DS pool (dim-first, dense rows): strides (p, CONV_STATE_LEN, 1);\n // - SD pool (vLLM default; physical [P, CONV_STATE_LEN, QKV_DIM] passed as\n // its transpose): strides (p, 1, QKV_DIM).\n {\n const long conv_stride_c = static_cast<long>(conv_state.stride(1));\n const long conv_stride_t = static_cast<long>(conv_state.stride(2));\n const bool conv_ds = conv_stride_c == CONV_STATE_LEN && conv_stride_t == 1;\n const bool conv_sd = conv_stride_c == 1 && conv_stride_t == QKV_DIM;\n TVM_FFI_ICHECK(conv_ds || conv_sd)\n << \"conv_state must be a DS-dense pool or a transposed SD pool view\";\n TVM_FFI_ICHECK_GE(conv_state.stride(0), (long)QKV_DIM * CONV_STATE_LEN);\n }\n TVM_FFI_ICHECK_EQ(ssm_state.stride(3), 1);\n TVM_FFI_ICHECK_EQ(ssm_state.stride(2), D);\n TVM_FFI_ICHECK_EQ(ssm_state.stride(1), (long)D * D);\n TVM_FFI_ICHECK_GE(ssm_state.stride(0), (long)HV * D * D);\n // The delta phase loads and stores whole state rows as float4, so every row\n // base -- idx*stride(0) + h*D*D + v*D -- must be 16B aligned. D*D and v*D\n // already are; a padded page stride is the only term that can break it, and\n // an odd pad would fault rather than degrade.\n TVM_FFI_ICHECK_EQ(ssm_state.stride(0) % 4, 0)\n << \"ssm_state page stride must be a multiple of 4 floats (float4 row access)\";\n TVM_FFI_ICHECK_EQ(output.stride(3), 1);\n TVM_FFI_ICHECK_EQ(output.stride(2), D);\n // The kernel addresses output as one dense [B, 1, HV, D] block\n // (output[((b*HV) + h)*D + v]), so the batch stride is not free either: a\n // destination that is dense per row but strided across the batch (a slice of\n // a wider buffer) would be written at the wrong offsets rather than\n // rejected. stride(1) is deliberately NOT checked -- that axis has extent 1,\n // so the kernel never uses its stride and torch leaves it unconstrained on\n // otherwise contiguous tensors; checking it could reject a valid buffer, and\n // a rejection here latches the whole impl off.\n TVM_FFI_ICHECK_EQ(output.stride(0), (long)HV * D);\n\n const long state_stride_0 = static_cast<long>(ssm_state.stride(0));\n const long qkv_stride = static_cast<long>(mixed_qkv.stride(0));\n const long conv_stride_p = static_cast<long>(conv_state.stride(0));\n const long conv_stride_c = static_cast<long>(conv_state.stride(1));\n const long conv_stride_t = static_cast<long>(conv_state.stride(2));\n\n ffi::CUDADeviceGuard device_guard(hidden_states.device().device_id);\n const cudaStream_t stream = get_stream(hidden_states.device());\n gdn_fused_decode_launch(\n hidden_states.data_ptr(), w_ba.data_ptr(), mixed_qkv.data_ptr(), conv_weight.data_ptr(),\n conv_bias.data_ptr(), conv_state.data_ptr(), A_log.data_ptr(), dt_bias.data_ptr(),\n static_cast<float>(scale), ssm_state.data_ptr(), state_indices.data_ptr(), output.data_ptr(),\n conv_out_scratch.data_ptr(), ba_scratch.data_ptr(), barrier.data_ptr(), state_stride_0,\n qkv_stride, conv_stride_p, conv_stride_c, conv_stride_t, B, stream);\n\n cudaError_t status = cudaGetLastError();\n TVM_FFI_ICHECK(status == cudaSuccess)\n << \"gdn_fused_decode failed with error code \" << cudaGetErrorString(status);\n}\n\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(gdn_fused_decode, gdn_fused_decode);\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\nFollow up with #4481 \n - Adds Qwen3.6-35B-A3B support at batches 1/2/4 for both CUDA and CuTe-DSL implementations.\n - Generates one geometry-specific CUDA JIT module using FI_GDN_* compile definitions.\n - Passes geometry as cutlass.Constexpr to CuTe-DSL kernels.\n - Includes geometry in compiled-kernel, workspace, and CUDA Graph readiness cache keys.\n - Adds compile-time/static geometry checks to prevent invalid tiling.\n - Adds registry_geometries() for introspection and potential AOT iteration.\n - Expands tests across both geometries, both implementations, registry shape, invalid geometry rejection, JIT module uniqueness, and numerical equivalence.\n - Updates documentation for the multi-geometry registry and JIT/AOT behavior.\n - Removes the hypothetical FLASHINFER_QWEN_GDN_FUSED_DECODE_DISABLE test reference.\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [ ] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [ ] I have installed the hooks with `pre-commit install`.\n- [ ] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [ ] Tests have been added or updated as needed.\n- [ ] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc. -->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n* **New Features**\n * Added fused GDN decode support for an additional model configuration, including its supported decode batch sizes.\n * Kernel compilation, dispatch, caching, and CUDA graph capture now account for each layer geometry, batch size, scale, and layout.\n * Added validation for supported dimensions and tiling relationships, with fallback behavior for unsupported geometries.\n * Expanded supported workloads across both shipped geometries.\n\n* **Documentation**\n * Updated support, registry, CUDA graph, build, and model-integration guidance with expanded geometry requirements and configurations.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1080,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"f47f2d254d78afb7bf4600170f007edd4a6b556e"},"date":{"kind":"string","value":"2026-08-24T19:31:00+08:00"},"pr_number":{"kind":"number","value":4699,"string":"4,699"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/4699"},"title":{"kind":"string","value":"perf(gdn): reduce non-CP CuTeDSL launch overhead (#4699)"},"message":{"kind":"string","value":"perf(gdn): reduce non-CP CuTeDSL launch overhead (#4699)\n\nCache SM90 and SM120 non-CP kernel objects and compile options, and\nconstruct CuTe tensor wrappers only during compilation. Replay compiled\nkernels through raw TVM-FFI arguments to remove repeated launch\npreparation from the eager path.\n\nfollow up of #4374 for non-CP launch path."},"path":{"kind":"string","value":"flashinfer/gdn_kernels/delta_rule_dsl/delta_rule_sm120.py"},"language":{"kind":"string","value":"cute_dsl"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"from enum import IntEnum\n\nimport torch\nimport cutlass\nimport cutlass.cute as cute\nimport cutlass.pipeline as pipeline\nfrom cutlass.cute.nvgpu import warp, warpgroup, cpasync\nfrom ...utils import get_device_sm_count, _get_cache_buf\nfrom .alpha import AlphaProcessor\nfrom .collective_store_tma import CollectiveStoreTma\nfrom .custom_compile_cache import (\n KeyedCompileMixin,\n cached_compile,\n sm12x_compile_options,\n)\nfrom .collective_inverse_hmma import CollectiveInverse\nfrom .helpers import SM80, round_down, state_dtype_to_cutlass\nfrom .schedule import WorkDesc\nfrom .varlen_helper import is_integer_dtype\n\n\n# ─── Named-barrier IDs used by the compute kernel ────────────────────────────\n# Must not conflict with each other or with pipeline barrier storage.\n\n\nclass NamedBarrier(IntEnum):\n MATH_WG0 = 4 # OrderedMathBarriers: StreamkBarrier0\n MATH_WG1 = 5 # OrderedMathBarriers: StreamkBarrier1\n KK_SYNC = 13 # sync all 128 WG0 threads before collective_inverse\n\n\nclass WarpGroupRole(IntEnum):\n LDST = 0\n MATH_KK = 1\n MATH_QK = 2\n\n\nclass LoadStoreWarpRole(IntEnum):\n LOAD_QKV = 0\n STORE_O = 1\n LOAD_BETA = 2\n LOAD_ALPHA = 3\n\n\nclass MathWarpGroupRole(IntEnum):\n KK = 0\n QK = 1\n\n\n# ─── Warp-specialized delta-rule kernel ───────────────────────────────────────\n# Grid: (num_seqs * num_sab_heads, 1, 1)\n# Block: 384 threads → WG0=[0,127], WG1=[128,255], WG2=[256,383]\n#\n# needs_alpha / needs_beta / needs_init_state are class attributes set in __init__.\n# The JIT compiler specialises per instance, so they are compile-time booleans\n# inside the kernel without any parameter-passing trickery.\n\n\nclass _FullyFusedDeltaRuleSm120(KeyedCompileMixin):\n @staticmethod\n def get_register_requirements(\n max_threads_per_block: int,\n min_blocks_per_multiprocessor: int,\n num_mma_warp_groups: int,\n threads_per_warp_group: int,\n ) -> tuple[int, int]:\n reg_alloc_granularity = 8\n load_registers = 40 - 2 * reg_alloc_granularity\n total_registers = (\n round_down(\n 64 * 1024 // min_blocks_per_multiprocessor,\n max_threads_per_block * reg_alloc_granularity,\n )\n // threads_per_warp_group\n )\n mma_registers = round_down(\n (total_registers - load_registers) // num_mma_warp_groups,\n reg_alloc_granularity,\n )\n return min(248, load_registers), min(248, mma_registers)\n\n @staticmethod\n def can_implement(\n num_q_heads: int,\n num_k_heads: int,\n num_v_heads: int,\n head_size: int,\n element_size: int,\n ) -> bool:\n ratio = (\n num_q_heads // num_v_heads\n if num_q_heads > num_v_heads\n else num_v_heads // num_q_heads\n )\n is_gva_enabled = num_v_heads > num_q_heads\n\n is_gqa_like = (\n (num_k_heads == num_v_heads)\n and (num_q_heads == ratio * num_k_heads)\n and (num_q_heads == ratio * num_v_heads)\n )\n is_gva_like = (\n (num_q_heads == num_k_heads)\n and (num_v_heads == ratio * num_q_heads)\n and (num_v_heads == ratio * num_k_heads)\n )\n\n alignment = 16 // element_size\n return (\n ((not is_gva_enabled and is_gqa_like) or (is_gva_enabled and is_gva_like))\n and (head_size <= 128)\n and ((head_size % alignment) == 0)\n )\n\n def __init__(\n self,\n needs_alpha: bool,\n needs_beta: bool,\n needs_init_state: bool,\n needs_checkpointing: bool,\n dtype: type[cutlass.Numeric] = cutlass.Float16,\n acc_dtype: type[cutlass.Numeric] = cutlass.Float32,\n initial_state_dtype: type[cutlass.Numeric] = cutlass.Float32,\n state_dtype: type[cutlass.Numeric] = cutlass.Float32,\n checkpoint_state_dtype: type[cutlass.Numeric] = cutlass.Float32,\n use_state_indices: bool = False,\n cu_seqlens_dtype: torch.dtype = torch.int64,\n state_indices_dtype: torch.dtype | None = None,\n checkpoint_cu_starts_dtype: torch.dtype | None = None,\n state_inner_strides: tuple[int, ...] | None = None,\n init_state_inner_strides: tuple[int, ...] | None = None,\n ):\n self.needs_alpha = needs_alpha\n self.needs_beta = needs_beta\n self.needs_init_state = needs_init_state\n self.needs_checkpointing = needs_checkpointing\n self.dtype = dtype\n self.acc_dtype = acc_dtype\n self.initial_state_dtype = initial_state_dtype\n self.state_dtype = state_dtype\n self.checkpoint_state_dtype = checkpoint_state_dtype\n self.use_state_indices = use_state_indices\n self.cu_seqlens_dtype = cu_seqlens_dtype\n self.state_indices_dtype = state_indices_dtype\n self.checkpoint_cu_starts_dtype = checkpoint_cu_starts_dtype\n self.state_inner_strides = state_inner_strides\n self.init_state_inner_strides = init_state_inner_strides\n self.inverse_dtype = cutlass.Float16\n self.BLK_Q = 64\n self.BLK_KV = 64\n self.D = 128\n self.q_stage = 1\n self.k_stage = 2\n self.v_stage = 1\n self.o_stage = 1\n self.alpha_beta_stage = 2\n self.manual_cache_key(\n \"needs_alpha\",\n \"needs_beta\",\n \"needs_init_state\",\n \"needs_checkpointing\",\n \"dtype\",\n \"acc_dtype\",\n \"initial_state_dtype\",\n \"state_dtype\",\n \"checkpoint_state_dtype\",\n \"use_state_indices\",\n \"cu_seqlens_dtype\",\n \"state_indices_dtype\",\n \"checkpoint_cu_starts_dtype\",\n \"state_inner_strides\",\n \"init_state_inner_strides\",\n \"inverse_dtype\",\n \"BLK_Q\",\n \"BLK_KV\",\n \"D\",\n \"q_stage\",\n \"k_stage\",\n \"v_stage\",\n \"o_stage\",\n \"alpha_beta_stage\",\n )\n\n def get_next_work(\n self,\n cu_seqlens: cute.Tensor,\n num_q_heads: cutlass.Int32,\n num_v_heads: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n ) -> WorkDesc:\n bx, _, _ = cute.arch.block_idx()\n seq_idx = bx // num_sab_heads\n o_head_idx = bx % num_sab_heads\n q_head_idx = o_head_idx * num_q_heads // num_sab_heads\n v_head_idx = o_head_idx * num_v_heads // num_sab_heads\n tok_start = cu_seqlens[seq_idx]\n seq_len = cutlass.Int32(cu_seqlens[seq_idx + 1] - tok_start)\n\n return WorkDesc(\n seq_idx=seq_idx,\n private_q_head_idx=q_head_idx,\n private_v_head_idx=v_head_idx,\n tok_offset=tok_start,\n seq_len=seq_len,\n tile_idx=cutlass.Int32(0),\n )\n\n # ─── Ordered 2-WG math barriers ───────────────────────────────────────────\n # Translates flat::OrderedNamedBarriers<UseReservedNB, NB0, NB1>.\n # wg_idx: MathWarpGroupRole.KK or MathWarpGroupRole.QK.\n\n @cute.jit\n def _math_order_init(self, wg_idx: cutlass.Int32):\n \"\"\"Pre-arrive at WG0's barrier so WG0 is unblocked on the first wait.\"\"\"\n if wg_idx == MathWarpGroupRole.QK:\n cute.arch.barrier_arrive(\n barrier_id=NamedBarrier.MATH_WG0, number_of_threads=256\n )\n\n @cute.jit\n def _math_order_wait(self, wg_idx: cutlass.Int32):\n \"\"\"Arrive+wait on this WG's own ordered barrier.\"\"\"\n if wg_idx == MathWarpGroupRole.KK:\n cute.arch.barrier(barrier_id=NamedBarrier.MATH_WG0, number_of_threads=256)\n else:\n cute.arch.barrier(barrier_id=NamedBarrier.MATH_WG1, number_of_threads=256)\n\n @cute.jit\n def _math_order_notify(self, wg_idx: cutlass.Int32):\n \"\"\"Arrive at the other WG's barrier to unblock it.\"\"\"\n if wg_idx == MathWarpGroupRole.KK:\n cute.arch.barrier_arrive(\n barrier_id=NamedBarrier.MATH_WG1, number_of_threads=256\n )\n else:\n cute.arch.barrier_arrive(\n barrier_id=NamedBarrier.MATH_WG0, number_of_threads=256\n )\n\n # ─── kk_store_and_inv ─────────────────────────────────────────────────────\n\n @cute.jit\n def _kk_store_and_inv(\n self,\n tKKrKK: cute.Tensor, # fp32 KK accumulator (from 128-thread kk_tiled_mma)\n kk_tiled_mma,\n kk_thread_idx: cutlass.Int32,\n sKK_inv: cute.Tensor, # (BlkKV, BlkKV)\n sKK_opd: cute.Tensor, # sKK_inv storage recast as Element for MMA operand\n sBeta: cute.Tensor, # (BlkKV, StagesBeta) - used when needs_beta\n beta_pipe_idx: cutlass.Int32,\n tKKcMkk: cute.Tensor, # coordinate mapping for KK fragment\n ):\n \"\"\"Store tKKrKK → sKK_inv, Inverse, optionally reload+beta.\"\"\"\n stsm_atom = cute.make_copy_atom(\n warp.StMatrix8x8x16bOp(transpose=False, num_matrices=4), self.inverse_dtype\n )\n tiled_store = cute.make_tiled_copy_C(stsm_atom, kk_tiled_mma)\n thr_store = tiled_store.get_slice(kk_thread_idx)\n tKKsKK = thr_store.partition_D(sKK_inv)\n tKKrKK_inv = cute.make_fragment_like(tKKrKK, self.inverse_dtype)\n tKKrKK_cv = thr_store.retile(tKKrKK_inv)\n for i in cutlass.range_constexpr(cute.size(tKKrKK)):\n tKKrKK_inv[i] = self.inverse_dtype(tKKrKK[i])\n cute.copy(tiled_store, tKKrKK_cv, tKKsKK)\n\n cute.arch.barrier(barrier_id=NamedBarrier.KK_SYNC, number_of_threads=128)\n CollectiveInverse().run(sKK_inv, NamedBarrier.KK_SYNC)\n\n if cutlass.const_expr(self.needs_beta or self.dtype != self.inverse_dtype):\n cute.arch.barrier(barrier_id=NamedBarrier.KK_SYNC, number_of_threads=128)\n ldsm_atom = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(transpose=False, num_matrices=4),\n self.inverse_dtype,\n )\n tiled_load = cute.make_tiled_copy_C(ldsm_atom, kk_tiled_mma)\n thr_load = tiled_load.get_slice(kk_thread_idx)\n tKKrKK_cpy = cute.make_fragment_like(tKKrKK_inv)\n tKKrKK_cvt = cute.make_fragment_like(tKKrKK_inv, self.dtype)\n tKKrKK_cv2 = thr_load.retile(tKKrKK_cpy)\n cute.copy(tiled_load, thr_load.partition_S(sKK_inv), tKKrKK_cv2)\n tKKcMkk_cv = thr_load.retile(tKKcMkk)\n\n for i in cutlass.range_constexpr(cute.size(tKKrKK_cpy)):\n if cutlass.const_expr(self.needs_beta):\n _, t = tKKcMkk_cv[i]\n tKKrKK_cvt[i] = self.dtype(\n cutlass.Float32(tKKrKK_cpy[i])\n * cutlass.Float32(sBeta[t, beta_pipe_idx])\n )\n else:\n tKKrKK_cvt[i] = self.dtype(tKKrKK_cpy[i])\n\n tKKsKK2 = thr_store.partition_D(sKK_opd)\n tKKrKK_cv3 = thr_store.retile(tKKrKK_cvt)\n cute.copy(tiled_store, tKKrKK_cv3, tKKsKK2)\n\n # ─── kk_epi ───────────────────────────────────────────────────────────────\n\n @cute.jit\n def kk_epi(\n self,\n tKKrKK: cute.Tensor,\n tKKcMkk: cute.Tensor,\n sAlpha: cute.Tensor,\n sBeta: cute.Tensor,\n alpha_stage: cutlass.Int32,\n beta_stage: cutlass.Int32,\n ):\n if cutlass.const_expr(self.needs_alpha):\n alpha_cumlog = sAlpha[None, AlphaProcessor.CUMSUM_LOG, alpha_stage]\n for i in cutlass.range_constexpr(cute.size(tKKrKK)):\n s, t = tKKcMkk[i]\n tKKrKK[i] = tKKrKK[i] * cute.math.exp2(\n cutlass.Float32(alpha_cumlog[s]) - cutlass.Float32(alpha_cumlog[t]),\n fastmath=True,\n )\n if cutlass.const_expr(self.needs_beta):\n beta_row = sBeta[None, beta_stage]\n for i in cutlass.range_constexpr(cute.size(tKKrKK)):\n s, _ = tKKcMkk[i]\n tKKrKK[i] = tKKrKK[i] * cutlass.Float32(beta_row[s])\n\n # ─── qk_or_kk_mask ────────────────────────────────────────────────────────\n\n @cute.jit\n def qk_or_kk_mask(\n self,\n frag: cute.Tensor,\n coord_tensor: cute.Tensor,\n is_final_block: bool,\n B: cutlass.Int32,\n ):\n for i in cutlass.range_constexpr(cute.size(frag)):\n s, t = coord_tensor[i]\n pred = s >= t\n if cutlass.const_expr(is_final_block):\n pred = pred and (s < B and t < B)\n if not pred:\n frag[i] = cutlass.Float32(0.0)\n\n # ─── qk_epi ───────────────────────────────────────────────────────────────\n\n @cute.jit\n def qk_epi(\n self,\n tQKrQK: cute.Tensor,\n tQKcMqk: cute.Tensor,\n sAlpha: cute.Tensor,\n alpha_stage: cutlass.Int32,\n scale: cutlass.Float32,\n ):\n if cutlass.const_expr(self.needs_alpha):\n alpha_cumlog = sAlpha[None, AlphaProcessor.CUMSUM_LOG, alpha_stage]\n for i in cutlass.range_constexpr(cute.size(tQKrQK)):\n s, t = tQKcMqk[i]\n tQKrQK[i] = (\n tQKrQK[i]\n * cute.math.exp2(\n cutlass.Float32(alpha_cumlog[s])\n - cutlass.Float32(alpha_cumlog[t]),\n fastmath=True,\n )\n * scale\n )\n else:\n for i in cutlass.range_constexpr(cute.size(tQKrQK)):\n tQKrQK[i] = tQKrQK[i] * scale\n\n # ─── qk_store ─────────────────────────────────────────────────────────────\n\n @cute.jit\n def qk_store(\n self,\n tQKrQK: cute.Tensor,\n sQK: cute.Tensor,\n qk_tiled_mma,\n qk_thread_idx: cutlass.Int32,\n ):\n stsm_atom = cute.make_copy_atom(\n warp.StMatrix8x8x16bOp(transpose=False, num_matrices=4), self.dtype\n )\n qk_tiled_copy = cute.make_tiled_copy_C(stsm_atom, qk_tiled_mma)\n qk_thr_copy = qk_tiled_copy.get_slice(qk_thread_idx)\n tQKsQK = qk_thr_copy.partition_D(sQK)\n tQKrQK_cvt = cute.make_fragment_like(tQKrQK, self.dtype)\n tQKrQK_cvt_cv = qk_thr_copy.retile(tQKrQK_cvt)\n for i in cutlass.range_constexpr(cute.size(tQKrQK)):\n tQKrQK_cvt[i] = self.dtype(tQKrQK[i])\n cute.copy(qk_tiled_copy, tQKrQK_cvt_cv, tQKsQK)\n\n # ─── o1_epi ───────────────────────────────────────────────────────────────\n\n @cute.jit\n def o1_epi(\n self,\n tOrO: cute.Tensor,\n tOcO: cute.Tensor,\n sAlpha: cute.Tensor,\n alpha_stage: cutlass.Int32,\n scale: cutlass.Float32,\n ):\n if cutlass.const_expr(self.needs_alpha):\n alpha_cpscale = sAlpha[None, AlphaProcessor.CUMPROD_SCALE, alpha_stage]\n for i in cutlass.range_constexpr(cute.size(tOrO)):\n _, tok_q = tOcO[i]\n tOrO[i] = cutlass.Float32(alpha_cpscale[tok_q]) * tOrO[i]\n else:\n for i in cutlass.range_constexpr(cute.size(tOrO)):\n tOrO[i] = scale * tOrO[i]\n\n # ─── sk_epi ───────────────────────────────────────────────────────────────\n\n @cute.jit\n def sk_epi(\n self,\n tSKrSK: cute.Tensor,\n tSKcSK: cute.Tensor,\n sAlpha: cute.Tensor,\n alpha_stage: cutlass.Int32,\n ):\n if cutlass.const_expr(self.needs_alpha):\n alpha_cp = sAlpha[None, AlphaProcessor.CUMPROD, alpha_stage]\n for i in cutlass.range_constexpr(cute.size(tSKrSK)):\n _, tok_kv = tSKcSK[i]\n tSKrSK[i] = tSKrSK[i] * cutlass.Float32(alpha_cp[tok_kv])\n\n # ─── sk_load_v ────────────────────────────────────────────────────────────\n\n @cute.jit\n def sk_load_v(\n self,\n tSKrSK: cute.Tensor,\n sV_DS: cute.Tensor,\n sk_tiled_copy_C,\n sk_thr_copy_C,\n v_stage: cutlass.Int32,\n ) -> cute.Tensor:\n tSKrV = cute.make_fragment_like(tSKrSK, self.dtype)\n tSKrV_cv = sk_thr_copy_C.retile(tSKrV)\n tSKsV = sk_thr_copy_C.partition_S(sV_DS)\n cute.copy(sk_tiled_copy_C, tSKsV[None, None, None, v_stage], tSKrV_cv)\n return tSKrV\n\n # ─── kv_decay_v ───────────────────────────────────────────────────────────\n\n @cute.jit\n def kv_decay_v(\n self,\n tKVrV: cute.Tensor,\n tKVcV: cute.Tensor,\n sAlpha: cute.Tensor,\n alpha_stage: cutlass.Int32,\n is_final_block: bool,\n B: cutlass.Int32,\n ):\n if cutlass.const_expr(self.needs_alpha):\n alpha_cumlog = sAlpha[None, AlphaProcessor.CUMSUM_LOG, alpha_stage]\n block_log = cutlass.Float32(alpha_cumlog[B - cutlass.Int32(1)])\n for i in cutlass.range_constexpr(cute.size(tKVrV)):\n _, tok = tKVcV[i]\n coeff = cute.math.exp2(\n block_log - cutlass.Float32(alpha_cumlog[tok]), fastmath=True\n )\n if cutlass.const_expr(is_final_block):\n if tok >= B:\n coeff = cutlass.Float32(0.0)\n tKVrV[i] = self.dtype(cutlass.Float32(tKVrV[i]) * coeff)\n else:\n for i in cutlass.range_constexpr(cute.size(tKVrV)):\n _, tok = tKVcV[i]\n if cutlass.const_expr(is_final_block):\n if tok >= B:\n tKVrV[i] = self.dtype(0.0)\n\n # ─── o_store ──────────────────────────────────────────────────────────────\n\n @cute.jit\n def o_store(\n self,\n tOrO: cute.Tensor,\n tOsO: cute.Tensor,\n o_tiled_copy_r2s,\n o_thr_copy_r2s,\n ):\n tOrO_f16 = cute.make_fragment_like(tOrO, self.dtype)\n for i in cutlass.range_constexpr(cute.size(tOrO)):\n tOrO_f16[i] = self.dtype(tOrO[i])\n tOrO_cv = o_thr_copy_r2s.retile(tOrO_f16)\n cute.arch.fence_view_async_shared()\n cute.copy(o_tiled_copy_r2s, tOrO_cv, tOsO)\n cute.arch.fence_view_async_shared()\n\n # ─── TMA load helpers ────────────────────────────────────────────────────\n\n @cute.jit\n def load_qkv_tma(\n self,\n sQ_SD: cute.Tensor,\n sK_DS: cute.Tensor,\n sV_DS: cute.Tensor,\n tma_atom_q: cute.CopyAtom,\n tma_tensor_q: cute.Tensor,\n tma_atom_k: cute.CopyAtom,\n tma_tensor_k: cute.Tensor,\n tma_atom_v: cute.CopyAtom,\n tma_tensor_v: cute.Tensor,\n q_pipeline,\n q_producer_state,\n k_pipeline,\n k_producer_state,\n v_pipeline,\n v_producer_state,\n blk: cutlass.Int32,\n tok_start,\n q_head_idx: cutlass.Int32,\n k_head_idx: cutlass.Int32,\n v_head_idx: cutlass.Int32,\n ):\n blk_tok = tok_start + blk * cutlass.Int32(self.BLK_KV)\n\n sK = sK_DS[None, None, k_producer_state.index]\n mK = cute.domain_offset(\n (cutlass.Int32(0), blk_tok),\n tma_tensor_k[None, None, k_head_idx],\n )\n gK = cute.zipped_divide(mK, (self.D, self.BLK_KV))[\n ((None, None), (cutlass.Int32(0), cutlass.Int32(0)))\n ]\n tKsK, tKgK = cpasync.tma_partition(\n tma_atom_k,\n 0,\n cute.make_layout(1),\n cute.group_modes(sK, 0, 2),\n cute.group_modes(gK, 0, 2),\n )\n k_pipeline.producer_acquire(k_producer_state)\n cute.copy(\n tma_atom_k,\n tKgK,\n tKsK,\n tma_bar_ptr=k_pipeline.producer_get_barrier(k_producer_state),\n )\n k_pipeline.producer_commit(k_producer_state)\n k_producer_state.advance()\n\n sQ = sQ_SD[None, None, q_producer_state.index]\n mQ = cute.domain_offset(\n (blk_tok, cutlass.Int32(0)),\n tma_tensor_q[None, None, q_head_idx],\n )\n gQ = cute.zipped_divide(mQ, (self.BLK_Q, self.D))[\n ((None, None), (cutlass.Int32(0), cutlass.Int32(0)))\n ]\n tQsQ, tQgQ = cpasync.tma_partition(\n tma_atom_q,\n 0,\n cute.make_layout(1),\n cute.group_modes(sQ, 0, 2),\n cute.group_modes(gQ, 0, 2),\n )\n q_pipeline.producer_acquire(q_producer_state)\n cute.copy(\n tma_atom_q,\n tQgQ,\n tQsQ,\n tma_bar_ptr=q_pipeline.producer_get_barrier(q_producer_state),\n )\n q_pipeline.producer_commit(q_producer_state)\n q_producer_state.advance()\n\n sV = sV_DS[None, None, v_producer_state.index]\n mV = cute.domain_offset(\n (cutlass.Int32(0), blk_tok),\n tma_tensor_v[None, None, v_head_idx],\n )\n gV = cute.zipped_divide(mV, (self.D, self.BLK_KV))[\n ((None, None), (cutlass.Int32(0), cutlass.Int32(0)))\n ]\n tVsV, tVgV = cpasync.tma_partition(\n tma_atom_v,\n 0,\n cute.make_layout(1),\n cute.group_modes(sV, 0, 2),\n cute.group_modes(gV, 0, 2),\n )\n v_pipeline.producer_acquire(v_producer_state)\n cute.copy(\n tma_atom_v,\n tVgV,\n tVsV,\n tma_bar_ptr=v_pipeline.producer_get_barrier(v_producer_state),\n )\n v_pipeline.producer_commit(v_producer_state)\n v_producer_state.advance()\n return q_producer_state, k_producer_state, v_producer_state\n\n # ─── load_alpha ───────────────────────────────────────────────────────────\n # Translates FlatMainloopTmaWarpSpecializedDeltaRule::load_alpha (scalar load).\n # Caller must sync before calling AlphaProcessor on the loaded data.\n\n @cute.jit\n def load_alpha(\n self,\n sAlpha: cute.Tensor,\n g_alpha: cute.Tensor,\n blk_tok: cutlass.Int32,\n tok_end,\n sab_head_idx: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n alpha_stage: cutlass.Int32,\n ):\n lane_id = cute.arch.lane_idx()\n sAlpha_k = sAlpha[None, None, alpha_stage]\n num_iters = self.BLK_Q // 32\n for i in cutlass.range_constexpr(num_iters):\n row = cutlass.Int32(i * 32) + lane_id\n tok = blk_tok + row\n if tok < tok_end:\n sAlpha_k[row, AlphaProcessor.CUMSUM_LOG] = g_alpha[\n tok * num_sab_heads + sab_head_idx\n ]\n else:\n sAlpha_k[row, AlphaProcessor.CUMSUM_LOG] = cutlass.Float32(1.0)\n\n # ─── load_beta ────────────────────────────────────────────────────────────\n # Translates FlatMainloopTmaWarpSpecializedDeltaRule::load_beta.\n\n @cute.jit\n def load_beta(\n self,\n sBeta: cute.Tensor,\n g_beta: cute.Tensor,\n blk_tok: cutlass.Int32,\n tok_end,\n sab_head_idx: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n beta_stage: cutlass.Int32,\n ):\n lane_id = cute.arch.lane_idx()\n sBeta_k = sBeta[None, beta_stage]\n num_iters = self.BLK_KV // 32\n for i in cutlass.range_constexpr(num_iters):\n row = cutlass.Int32(i * 32) + lane_id\n tok = blk_tok + row\n if tok < tok_end:\n sBeta_k[row] = g_beta[tok * num_sab_heads + sab_head_idx]\n else:\n sBeta_k[row] = cutlass.Float32(0.0)\n\n # ─── kv_load / kv_store ───────────────────────────────────────────────────\n\n @cute.jit\n def kv_load(\n self,\n tKVrKV: cute.Tensor,\n gKV: cute.Tensor,\n kv_thr_mma,\n ):\n c_kv = cute.make_identity_tensor((self.D, self.D))\n tKVcKV = kv_thr_mma.partition_C(c_kv)\n for i in cutlass.range(cute.size(tKVrKV), unroll_full=True):\n v_idx, k_idx = tKVcKV[i]\n tKVrKV[i] = gKV[k_idx, v_idx].to(self.acc_dtype)\n\n @cute.jit\n def kv_store(\n self,\n tKVrKV: cute.Tensor,\n gKV: cute.Tensor,\n kv_thr_mma,\n ):\n c_kv = cute.make_identity_tensor((self.D, self.D))\n tKVcKV = kv_thr_mma.partition_C(c_kv)\n for i in cutlass.range(cute.size(tKVrKV), unroll_full=True):\n v_idx, k_idx = tKVcKV[i]\n gKV[k_idx, v_idx] = tKVrKV[i].to(gKV.element_type)\n\n @cute.jit\n def maybe_store_checkpoint(\n self,\n tKVrKV: cute.Tensor,\n g_state_checkpoints: cute.Tensor,\n checkpoint_cu_starts: cute.Tensor,\n checkpoint_every_n_tokens: cutlass.Int32,\n kv_thr_mma,\n seq_idx: cutlass.Int32,\n o_head_idx: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n total_checkpoints: cutlass.Int32,\n block_end: cutlass.Int32,\n seq_len: cutlass.Int32,\n ):\n if cutlass.const_expr(self.needs_checkpointing):\n if (\n block_end <= seq_len\n and block_end % checkpoint_every_n_tokens == cutlass.Int32(0)\n ):\n checkpoint_idx = (\n cutlass.Int32(checkpoint_cu_starts[seq_idx])\n + block_end // checkpoint_every_n_tokens\n - cutlass.Int32(1)\n )\n checkpoint_layout = cute.make_ordered_layout(\n (self.D, self.D, num_sab_heads, total_checkpoints),\n order=(0, 1, 2, 3),\n )\n mCheckpoint = cute.make_tensor(\n g_state_checkpoints.iterator, checkpoint_layout\n )\n gCheckpointKV = mCheckpoint[None, None, o_head_idx, checkpoint_idx]\n self.kv_store(tKVrKV, gCheckpointKV, kv_thr_mma)\n\n # ─── compute_loop_body ───────────────────────────────────────────────────\n # Translates the C++ compute_loop_body lambda captured inside compute().\n # Called by Math WGs (tidx >= 128) for one block iteration.\n\n @cute.jit\n def compute_loop_body(\n self,\n # Smem tensors (staged; caller indexes the active stage)\n sQ_SD: cute.Tensor, # (BlkQ, D, StagesQ) – row-major atom, swizzled\n sK_SD: cute.Tensor, # (BlkKV, D, StagesK) – same atom\n sK_DS: cute.Tensor, # (D, BlkKV, StagesK) – K transposed\n sV_DS: cute.Tensor, # (D, BlkKV, StagesV) – V transposed\n sQK: cute.Tensor, # (BlkQ, BlkKV)\n sKK_inv: cute.Tensor, # (BlkKV, BlkKV)\n sKK_opd: cute.Tensor, # sKK_inv storage recast as Element\n sO: cute.Tensor, # O output smem (staged)\n sAlpha: cute.Tensor, # (BlkQ, AlphaProcessor.NUM_CHANNELS, StagesAlpha) or zero-shaped\n sBeta: cute.Tensor, # (BlkKV, StagesBeta) or zero-shaped\n kv_tiled_mma,\n # Mainloop pipelines and active read states\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n v_pipeline,\n v_consumer_state,\n o_pipeline,\n o_producer_state,\n alpha_pipeline,\n alpha_consumer_state,\n beta_pipeline,\n beta_consumer_state,\n # Compile-time flags\n is_first_block: bool,\n is_final_block: bool,\n # Valid token count for masking on final block\n B: cutlass.Int32,\n # Running KV state (D×D fp32, in registers across all blocks)\n tKVrKV: cute.Tensor,\n # Scale factor\n scale: cutlass.Float32,\n # WG role: MathWarpGroupRole.KK or MathWarpGroupRole.QK.\n wg_idx: cutlass.Int32,\n ):\n tidx, _, _ = cute.arch.thread_idx()\n thread_idx = tidx - cutlass.Int32(128) # relative to compute threads\n kk_thread_idx = thread_idx % cutlass.Int32(128)\n qk_thread_idx = thread_idx % cutlass.Int32(128)\n\n # ── TiledMMAs ─────────────────────────────────────────────────────────\n blk_q = cute.size(sQ_SD, mode=[0])\n blk_kv = cute.size(sK_SD, mode=[0])\n d = cute.size(sQ_SD, mode=[1])\n tile_shape_qk = (blk_q, blk_kv, d)\n tile_shape_kk = tile_shape_qk\n tile_shape_o1 = (d, blk_q, d)\n tile_shape_o2 = (d, blk_q, blk_kv)\n tile_shape_sk = (d, blk_kv, d)\n tile_shape_newv = (d, blk_kv, blk_kv)\n k_stage = k_consumer_state.index\n q_stage = q_consumer_state.index\n v_stage = v_consumer_state.index\n o_stage = cutlass.Int32(0)\n alpha_stage = alpha_consumer_state.index\n beta_stage = beta_consumer_state.index\n\n mma_atom_4w = warp.MmaF16BF16Op(self.dtype, self.acc_dtype, (16, 8, 16))\n mma_atom_8w = warp.MmaF16BF16Op(self.dtype, self.acc_dtype, (16, 8, 16))\n\n # QK/KK: 4 warps × 16M = 64M (1 warpgroup, 128 threads)\n qk_tiled_mma = cute.make_tiled_mma(\n mma_atom_4w, cute.make_layout((4, 1, 1)), permutation_mnk=tile_shape_qk\n )\n kk_tiled_mma = cute.make_tiled_mma(\n mma_atom_4w, cute.make_layout((4, 1, 1)), permutation_mnk=tile_shape_kk\n )\n\n # O1/O2/SK/NewV: 8 warps × 16M = 128M (both warpgroups, 256 threads)\n o1_tiled_mma = cute.make_tiled_mma(\n mma_atom_8w, cute.make_layout((8, 1, 1)), permutation_mnk=tile_shape_o1\n )\n o2_tiled_mma = cute.make_tiled_mma(\n mma_atom_8w, cute.make_layout((8, 1, 1)), permutation_mnk=tile_shape_o2\n )\n sk_tiled_mma = cute.make_tiled_mma(\n mma_atom_8w, cute.make_layout((8, 1, 1)), permutation_mnk=tile_shape_sk\n )\n newv_tiled_mma = cute.make_tiled_mma(\n mma_atom_8w, cute.make_layout((8, 1, 1)), permutation_mnk=tile_shape_newv\n )\n\n # ── Thread slices ─────────────────────────────────────────────────────\n qk_thr_mma = qk_tiled_mma.get_slice(qk_thread_idx)\n kk_thr_mma = kk_tiled_mma.get_slice(kk_thread_idx)\n sk_thr_mma = sk_tiled_mma.get_slice(thread_idx)\n newv_thr_mma = newv_tiled_mma.get_slice(thread_idx)\n o1_thr_mma = o1_tiled_mma.get_slice(thread_idx)\n o2_thr_mma = o2_tiled_mma.get_slice(thread_idx)\n kv_thr_mma = kv_tiled_mma.get_slice(thread_idx)\n\n # ── Copy atoms ────────────────────────────────────────────────────────\n ldsm_n4 = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(transpose=False, num_matrices=4), self.dtype\n )\n ldsm_t4 = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(transpose=True, num_matrices=4), self.dtype\n )\n\n # ── Active smem slices (extract 2D from staged tensors) ───────────────\n sQ_k = sQ_SD[None, None, q_stage] # (BlkQ, D)\n sK_SD_k = sK_SD[None, None, k_stage] # (BlkKV, D)\n sK_DS_k = sK_DS[None, None, k_stage] # (D, BlkKV)\n\n # ── QK copies ─────────────────────────────────────────────────────────\n qk_tiled_copy_A = cute.make_tiled_copy_A(ldsm_n4, qk_tiled_mma)\n qk_tiled_copy_B = cute.make_tiled_copy_B(ldsm_n4, qk_tiled_mma)\n qk_thr_copy_A = qk_tiled_copy_A.get_slice(qk_thread_idx)\n qk_thr_copy_B = qk_tiled_copy_B.get_slice(qk_thread_idx)\n\n tQKrQ = qk_thr_mma.make_fragment_A(qk_thr_mma.partition_A(sQ_k))\n tQKrQ_cv = qk_thr_copy_A.retile(tQKrQ)\n tQKsQ = qk_thr_copy_A.partition_S(sQ_SD)\n tQKrK = qk_thr_mma.make_fragment_B(qk_thr_mma.partition_B(sK_SD_k))\n tQKrK_cv = qk_thr_copy_B.retile(tQKrK)\n tQKsK = qk_thr_copy_B.partition_S(sK_SD)\n\n # ── KK copies (same atom as QK) ───────────────────────────────────────\n kk_tiled_copy_A = cute.make_tiled_copy_A(ldsm_n4, kk_tiled_mma)\n kk_tiled_copy_B = cute.make_tiled_copy_B(ldsm_n4, kk_tiled_mma)\n kk_thr_copy_A = kk_tiled_copy_A.get_slice(kk_thread_idx)\n kk_thr_copy_B = kk_tiled_copy_B.get_slice(kk_thread_idx)\n\n tKKrA = kk_thr_mma.make_fragment_A(kk_thr_mma.partition_A(sK_SD_k))\n tKKrA_cv = kk_thr_copy_A.retile(tKKrA)\n tKKsA = kk_thr_copy_A.partition_S(sK_SD)\n tKKrB = kk_thr_mma.make_fragment_B(kk_thr_mma.partition_B(sK_SD_k))\n tKKrB_cv = kk_thr_copy_B.retile(tKKrB)\n tKKsB = kk_thr_copy_B.partition_S(sK_SD)\n\n # ── SK copies ─────────────────────────────────────────────────────────\n # SK B: K loaded from sK_SD (row-major BlkKV×D) with LDSM_N — matches C++ SK B-operand\n # SK C: V loaded from sV_DS (col-major D×BlkKV) with LDSM_T\n sk_tiled_copy_B = cute.make_tiled_copy_B(ldsm_n4, sk_tiled_mma)\n sk_tiled_copy_C = cute.make_tiled_copy_C(ldsm_t4, sk_tiled_mma)\n sk_thr_copy_B = sk_tiled_copy_B.get_slice(thread_idx)\n sk_thr_copy_C = sk_tiled_copy_C.get_slice(thread_idx)\n\n # Work around DSL make_fragment_B not accepting partition_shape_B output directly.\n tSKrK = cute.make_rmem_tensor(\n sk_thr_mma.partition_shape_B(cute.slice_(tile_shape_sk, (0, None, None))),\n self.dtype,\n )\n tSKrK_cv = sk_thr_copy_B.retile(tSKrK)\n tSKsK = sk_thr_copy_B.partition_S(sK_SD)\n\n # ── NewV copies ───────────────────────────────────────────────────────\n newv_tiled_copy_B = cute.make_tiled_copy_B(ldsm_n4, newv_tiled_mma)\n newv_thr_copy_B = newv_tiled_copy_B.get_slice(thread_idx)\n tNewVrB = newv_thr_mma.make_fragment_B(newv_thr_mma.partition_B(sKK_opd))\n tNewVrB_cv = newv_thr_copy_B.retile(tNewVrB)\n tNewVsB = newv_thr_copy_B.partition_S(sKK_opd)\n\n # ── KV copies ─────────────────────────────────────────────────────────\n kv_tiled_copy_B = cute.make_tiled_copy_B(ldsm_t4, kv_tiled_mma)\n kv_thr_copy_B = kv_tiled_copy_B.get_slice(thread_idx)\n tKVrK = kv_thr_mma.make_fragment_B(kv_thr_mma.partition_B(sK_DS_k))\n tKVrK_cv = kv_thr_copy_B.retile(tKVrK)\n tKVsK = kv_thr_copy_B.partition_S(sK_DS)\n\n # ── O1/O2 copies ──────────────────────────────────────────────────────\n o1_tiled_copy_B = cute.make_tiled_copy_B(ldsm_n4, o1_tiled_mma)\n o2_tiled_copy_B = cute.make_tiled_copy_B(ldsm_n4, o2_tiled_mma)\n o1_thr_copy_B = o1_tiled_copy_B.get_slice(thread_idx)\n o2_thr_copy_B = o2_tiled_copy_B.get_slice(thread_idx)\n\n # Direct partition_B(sQ_k) preserves the swizzled Q layout here and produces\n # a non-C++ B fragment shape; derive the fragment from TileShapeO1 instead.\n tOrQ = cute.make_rmem_tensor(\n o1_thr_mma.partition_shape_B(cute.slice_(tile_shape_o1, (0, None, None))),\n self.dtype,\n )\n tOrQ_cv = o1_thr_copy_B.retile(tOrQ)\n tOsQ = o1_thr_copy_B.partition_S(sQ_SD)\n tOrQK = o2_thr_mma.make_fragment_B(o2_thr_mma.partition_B(sQK))\n tOrQK_cv = o2_thr_copy_B.retile(tOrQK)\n tOsQK = o2_thr_copy_B.partition_S(sQK)\n\n # ── O store (R→S STSM) ────────────────────────────────────────────────\n o_stsm = cute.make_copy_atom(\n warp.StMatrix8x8x16bOp(transpose=True, num_matrices=4), self.dtype\n )\n o_tiled_copy_r2s = cute.make_tiled_copy_C(o_stsm, o1_tiled_mma)\n o_thr_copy_r2s = o_tiled_copy_r2s.get_slice(thread_idx)\n tOsO = o_thr_copy_r2s.partition_D(sO)\n\n # ── Coordinate tensors for masking / alpha/beta indexing ──────────────\n cMqk = cute.make_identity_tensor((blk_q, blk_kv))\n tQKcMqk = qk_thr_mma.partition_C(cMqk)\n cMkk = cMqk # same shape (BlkKV == BlkQ == 64)\n tKKcMkk = kk_thr_mma.partition_C(cMkk)\n cO = cute.make_identity_tensor((d, blk_q))\n tOcO = o1_thr_mma.partition_C(cO)\n cSK = cute.make_identity_tensor((d, blk_kv))\n tSKcSK = sk_thr_mma.partition_C(cSK)\n cV = cute.make_identity_tensor((d, blk_kv))\n tKVcV = kv_thr_mma.partition_A(cV)\n\n # ── KK GEMM (WG0 only) ────────────────────────────────────────────────\n k_pipeline.consumer_wait(k_consumer_state)\n if cutlass.const_expr(self.needs_alpha):\n alpha_pipeline.consumer_wait(alpha_consumer_state)\n cute.arch.fence_view_async_shared()\n if cutlass.const_expr(self.needs_beta):\n beta_pipeline.consumer_wait(beta_consumer_state)\n cute.arch.fence_view_async_shared()\n # Match the C++ reject-non-role-first shape; ptxas keeps BRA.U around\n # the role body instead of predicating the HMMA/LDSM/STSM sequence.\n if wg_idx != MathWarpGroupRole.KK:\n cute.arch.sync_warp()\n else:\n cute.copy(kk_tiled_copy_A, tKKsA[None, None, None, k_stage], tKKrA_cv)\n cute.copy(kk_tiled_copy_B, tKKsB[None, None, None, k_stage], tKKrB_cv)\n tKKrKK = cute.make_rmem_tensor(\n kk_thr_mma.partition_shape_C((blk_kv, blk_kv)), self.acc_dtype\n )\n tKKrKK.fill(self.acc_dtype(0.0))\n cute.gemm(kk_tiled_mma, tKKrKK, tKKrA, tKKrB, tKKrKK)\n self.kk_epi(tKKrKK, tKKcMkk, sAlpha, sBeta, alpha_stage, beta_stage)\n self.qk_or_kk_mask(tKKrKK, tKKcMkk, is_final_block, B)\n self._kk_store_and_inv(\n tKKrKK,\n kk_tiled_mma,\n kk_thread_idx,\n sKK_inv,\n sKK_opd,\n sBeta,\n beta_stage,\n tKKcMkk,\n )\n if cutlass.const_expr(self.needs_beta):\n beta_pipeline.consumer_release(beta_consumer_state)\n beta_consumer_state.advance()\n\n # ── QK GEMM (WG1 only) ────────────────────────────────────────────────\n q_pipeline.consumer_wait(q_consumer_state)\n if wg_idx != MathWarpGroupRole.QK:\n cute.arch.sync_warp()\n else:\n cute.copy(qk_tiled_copy_A, tQKsQ[None, None, None, q_stage], tQKrQ_cv)\n cute.copy(qk_tiled_copy_B, tQKsK[None, None, None, k_stage], tQKrK_cv)\n tQKrQK = cute.make_rmem_tensor(\n qk_thr_mma.partition_shape_C((blk_q, blk_kv)), self.acc_dtype\n )\n tQKrQK.fill(self.acc_dtype(0.0))\n cute.gemm(qk_tiled_mma, tQKrQK, tQKrQ, tQKrK, tQKrQK)\n self.qk_epi(tQKrQK, tQKcMqk, sAlpha, alpha_stage, scale)\n self.qk_or_kk_mask(tQKrQK, tQKcMqk, is_final_block, B)\n self.qk_store(tQKrQK, sQK, qk_tiled_mma, qk_thread_idx)\n\n # ── O1: KV_state @ Q (both WGs, skip on first block) ─────────────────\n tOrO = cute.make_rmem_tensor(\n o1_thr_mma.partition_shape_C((d, blk_q)), self.acc_dtype\n )\n tOrO.fill(self.acc_dtype(0.0))\n if cutlass.const_expr(not is_first_block):\n cute.copy(o1_tiled_copy_B, tOsQ[None, None, None, q_stage], tOrQ_cv)\n tOrKV = SM80.make_acc_into_op(tKVrKV, o1_tiled_mma, self.dtype)\n cute.gemm(o1_tiled_mma, tOrO, tOrKV, tOrQ, tOrO)\n self.o1_epi(tOrO, tOcO, sAlpha, alpha_stage, scale)\n q_pipeline.consumer_release(q_consumer_state)\n q_consumer_state.advance()\n\n # ── SK: KV_state @ K^T (result negated below via V - SK) ─────────────\n tSKrSK = cute.make_rmem_tensor(\n sk_thr_mma.partition_shape_C((d, blk_kv)), self.acc_dtype\n )\n tSKrSK.fill(self.acc_dtype(0.0))\n if cutlass.const_expr(not is_first_block):\n tSKrS = SM80.make_acc_into_op(tKVrKV, sk_tiled_mma, self.dtype)\n cute.copy(sk_tiled_copy_B, tSKsK[None, None, None, k_stage], tSKrK_cv)\n cute.gemm(sk_tiled_mma, tSKrSK, tSKrS, tSKrK, tSKrSK)\n\n # ── Load V from smem ──────────────────────────────────────────────────\n v_pipeline.consumer_wait(v_consumer_state)\n tSKrV = self.sk_load_v(tSKrSK, sV_DS, sk_tiled_copy_C, sk_thr_copy_C, v_stage)\n\n # sk_epi + V - SK (SK=0 on first block, so V - SK = V)\n if cutlass.const_expr(not is_first_block):\n self.sk_epi(tSKrSK, tSKcSK, sAlpha, alpha_stage)\n for i in cutlass.range_constexpr(cute.size(tSKrV)):\n tSKrV[i] = tSKrV[i] - self.dtype(tSKrSK[i])\n\n # ── NewV = (V - SK) @ T^T (ordered: WG0 first) ──────────────────────\n tNewVrA = SM80.make_acc_into_op(tSKrV, newv_tiled_mma, self.dtype)\n tNewVrC = cute.make_rmem_tensor(\n newv_thr_mma.partition_shape_C((d, blk_kv)), self.acc_dtype\n )\n self._math_order_wait(wg_idx)\n cute.copy(newv_tiled_copy_B, tNewVsB, tNewVrB_cv)\n tNewVrC.fill(self.acc_dtype(0.0))\n cute.gemm(newv_tiled_mma, tNewVrC, tNewVrA, tNewVrB, tNewVrC)\n self._math_order_notify(wg_idx)\n v_pipeline.consumer_release(v_consumer_state)\n v_consumer_state.advance()\n\n # ── O2 = O1 + NewV @ QK (ordered: WG0 first) ────────────────────────\n tOrNewV = SM80.make_acc_into_op(tNewVrC, o2_tiled_mma, self.dtype)\n self._math_order_wait(wg_idx)\n cute.copy(o2_tiled_copy_B, tOsQK, tOrQK_cv)\n cute.gemm(o2_tiled_mma, tOrO, tOrNewV, tOrQK, tOrO)\n self._math_order_notify(wg_idx)\n\n # ── O store to smem ───────────────────────────────────────────────────\n o_pipeline.producer_acquire(o_producer_state)\n self.o_store(\n tOrO,\n tOsO[None, None, None, o_stage],\n o_tiled_copy_r2s,\n o_thr_copy_r2s,\n )\n o_pipeline.producer_commit(o_producer_state)\n o_producer_state.advance()\n\n # ── KV state update ───────────────────────────────────────────────────\n block_coeff = cutlass.Float32(1.0)\n if cutlass.const_expr(self.needs_alpha):\n block_coeff = cutlass.Float32(\n sAlpha[B - cutlass.Int32(1), AlphaProcessor.CUMPROD, alpha_stage]\n )\n\n for i in cutlass.range(cute.size(tKVrKV), unroll_full=True):\n tKVrKV[i] = block_coeff * tKVrKV[i]\n\n self.kv_decay_v(tOrNewV, tKVcV, sAlpha, alpha_stage, is_final_block, B)\n\n # KV += NewV @ K\n cute.copy(kv_tiled_copy_B, tKVsK[None, None, None, k_stage], tKVrK_cv)\n cute.gemm(kv_tiled_mma, tKVrKV, tOrNewV, tKVrK, tKVrKV)\n k_pipeline.consumer_release(k_consumer_state)\n k_consumer_state.advance()\n if cutlass.const_expr(self.needs_alpha):\n alpha_pipeline.consumer_release(alpha_consumer_state)\n alpha_consumer_state.advance()\n return (\n q_consumer_state,\n k_consumer_state,\n v_consumer_state,\n o_producer_state,\n alpha_consumer_state,\n beta_consumer_state,\n )\n\n # ─── Warp role entry points ──────────────────────────────────────────────\n # The current DSL bridge still uses CTA-wide sync epochs, but each role owns\n # its own loop, matching the C++ warp-specialized dispatch shape.\n\n @cute.jit\n def run_load_qkv_role(\n self,\n sQ_SD: cute.Tensor,\n sK_DS: cute.Tensor,\n sV_DS: cute.Tensor,\n tma_atom_q: cute.CopyAtom,\n tma_tensor_q: cute.Tensor,\n tma_atom_k: cute.CopyAtom,\n tma_tensor_k: cute.Tensor,\n tma_atom_v: cute.CopyAtom,\n tma_tensor_v: cute.Tensor,\n q_pipeline,\n k_pipeline,\n v_pipeline,\n num_blocks: cutlass.Int32,\n tok_start,\n q_head_idx: cutlass.Int32,\n k_head_idx: cutlass.Int32,\n v_head_idx: cutlass.Int32,\n ):\n q_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.q_stage\n )\n k_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.k_stage\n )\n v_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.v_stage\n )\n for blk in cutlass.range(num_blocks, unroll=1):\n (\n q_producer_state,\n k_producer_state,\n v_producer_state,\n ) = self.load_qkv_tma(\n sQ_SD,\n sK_DS,\n sV_DS,\n tma_atom_q,\n tma_tensor_q,\n tma_atom_k,\n tma_tensor_k,\n tma_atom_v,\n tma_tensor_v,\n q_pipeline,\n q_producer_state,\n k_pipeline,\n k_producer_state,\n v_pipeline,\n v_producer_state,\n blk,\n tok_start,\n q_head_idx,\n k_head_idx,\n v_head_idx,\n )\n\n @cute.jit\n def run_load_alpha_role(\n self,\n sAlpha: cute.Tensor,\n g_alpha: cute.Tensor,\n alpha_pipeline,\n scale: cutlass.Float32,\n num_blocks: cutlass.Int32,\n tok_start,\n tok_end,\n sab_head_idx: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n ):\n alpha_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.alpha_beta_stage\n )\n for blk in cutlass.range(num_blocks, unroll=1):\n blk_tok = tok_start + blk * cutlass.Int32(self.BLK_Q)\n if cutlass.const_expr(self.needs_alpha):\n alpha_pipeline.producer_acquire(alpha_producer_state)\n cute.arch.fence_view_async_shared()\n self.load_alpha(\n sAlpha,\n g_alpha,\n blk_tok,\n tok_end,\n sab_head_idx,\n num_sab_heads,\n alpha_producer_state.index,\n )\n AlphaProcessor().run(\n sAlpha[None, None, alpha_producer_state.index], scale\n )\n cute.arch.fence_view_async_shared()\n alpha_pipeline.producer_commit(alpha_producer_state)\n alpha_producer_state.advance()\n\n @cute.jit\n def run_load_beta_role(\n self,\n sBeta: cute.Tensor,\n g_beta: cute.Tensor,\n beta_pipeline,\n num_blocks: cutlass.Int32,\n tok_start,\n tok_end,\n sab_head_idx: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n ):\n beta_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.alpha_beta_stage\n )\n for blk in cutlass.range(num_blocks, unroll=1):\n blk_tok = tok_start + blk * cutlass.Int32(self.BLK_KV)\n if cutlass.const_expr(self.needs_beta):\n beta_pipeline.producer_acquire(beta_producer_state)\n cute.arch.fence_view_async_shared()\n self.load_beta(\n sBeta,\n g_beta,\n blk_tok,\n tok_end,\n sab_head_idx,\n num_sab_heads,\n beta_producer_state.index,\n )\n cute.arch.fence_view_async_shared()\n beta_pipeline.producer_commit(beta_producer_state)\n beta_producer_state.advance()\n\n @cute.jit\n def run_math_role(\n self,\n sQ_SD: cute.Tensor,\n sK_SD: cute.Tensor,\n sK_DS: cute.Tensor,\n sV_DS: cute.Tensor,\n sQK: cute.Tensor,\n sKK_inv: cute.Tensor,\n sKK_opd: cute.Tensor,\n sO: cute.Tensor,\n sAlpha: cute.Tensor,\n sBeta: cute.Tensor,\n q_pipeline,\n k_pipeline,\n v_pipeline,\n o_pipeline,\n alpha_pipeline,\n beta_pipeline,\n g_state: cute.Tensor,\n g_init_state: cute.Tensor,\n g_state_indices: cute.Tensor,\n g_state_checkpoints: cute.Tensor,\n checkpoint_cu_starts: cute.Tensor,\n work_desc: WorkDesc,\n scale: cutlass.Float32,\n wg_idx: cutlass.Int32,\n math_tidx: cutlass.Int32,\n num_blocks: cutlass.Int32,\n num_q_heads: cutlass.Int32,\n num_v_heads: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n num_seqs: cutlass.Int32,\n total_checkpoints: cutlass.Int32,\n checkpoint_every_n_tokens: cutlass.Int32,\n ):\n self._math_order_init(wg_idx)\n q_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.q_stage\n )\n k_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.k_stage\n )\n v_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.v_stage\n )\n o_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.o_stage\n )\n alpha_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.alpha_beta_stage\n )\n beta_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.alpha_beta_stage\n )\n\n kv_tiled_mma = cute.make_tiled_mma(\n warp.MmaF16BF16Op(self.dtype, self.acc_dtype, (16, 8, 16)),\n cute.make_layout((8, 1, 1)),\n permutation_mnk=(self.D, self.D, self.BLK_KV),\n )\n kv_thr_mma = kv_tiled_mma.get_slice(math_tidx)\n tKVrKV = cute.make_rmem_tensor(\n kv_thr_mma.partition_shape_C((self.D, self.D)), self.acc_dtype\n )\n tKVrKV.fill(self.acc_dtype(0.0))\n\n packed_state_layout = cute.make_ordered_layout(\n (self.D, self.D, num_sab_heads, num_seqs), order=(0, 1, 2, 3)\n )\n state_ref_shape = (g_state.shape[0], g_state.shape[1], self.D, self.D)\n state_ref_layout = cute.make_layout(state_ref_shape, stride=g_state.stride)\n indexed_state_layout = cute.select(state_ref_layout, mode=[3, 2, 1, 0])\n state_idx = work_desc.seq_idx\n if cutlass.const_expr(self.use_state_indices):\n state_idx = cutlass.Int32(g_state_indices[work_desc.seq_idx])\n state_layout = indexed_state_layout\n else:\n state_layout = packed_state_layout\n o_head_idx = work_desc.o_head_idx(num_q_heads, num_v_heads)\n mState = cute.make_tensor(g_state.iterator, state_layout)\n gStateKV = mState[None, None, o_head_idx, state_idx]\n if cutlass.const_expr(self.needs_init_state):\n init_state_ref_layout = cute.make_layout(\n state_ref_shape, stride=g_init_state.stride\n )\n indexed_init_state_layout = cute.select(\n init_state_ref_layout, mode=[3, 2, 1, 0]\n )\n if cutlass.const_expr(self.use_state_indices):\n init_state_layout = indexed_init_state_layout\n else:\n init_state_layout = packed_state_layout\n mInitState = cute.make_tensor(g_init_state.iterator, init_state_layout)\n gInitKV = mInitState[None, None, o_head_idx, state_idx]\n self.kv_load(tKVrKV, gInitKV, kv_thr_mma)\n\n first_B = work_desc.seq_len\n if first_B > cutlass.Int32(self.BLK_KV):\n first_B = cutlass.Int32(self.BLK_KV)\n if cutlass.const_expr(self.needs_init_state):\n (\n q_consumer_state,\n k_consumer_state,\n v_consumer_state,\n o_producer_state,\n alpha_consumer_state,\n beta_consumer_state,\n ) = self.compute_loop_body(\n sQ_SD,\n sK_SD,\n sK_DS,\n sV_DS,\n sQK,\n sKK_inv,\n sKK_opd,\n sO,\n sAlpha,\n sBeta,\n kv_tiled_mma,\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n v_pipeline,\n v_consumer_state,\n o_pipeline,\n o_producer_state,\n alpha_pipeline,\n alpha_consumer_state,\n beta_pipeline,\n beta_consumer_state,\n False,\n True,\n first_B,\n tKVrKV,\n scale,\n wg_idx,\n )\n else:\n (\n q_consumer_state,\n k_consumer_state,\n v_consumer_state,\n o_producer_state,\n alpha_consumer_state,\n beta_consumer_state,\n ) = self.compute_loop_body(\n sQ_SD,\n sK_SD,\n sK_DS,\n sV_DS,\n sQK,\n sKK_inv,\n sKK_opd,\n sO,\n sAlpha,\n sBeta,\n kv_tiled_mma,\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n v_pipeline,\n v_consumer_state,\n o_pipeline,\n o_producer_state,\n alpha_pipeline,\n alpha_consumer_state,\n beta_pipeline,\n beta_consumer_state,\n True,\n True,\n first_B,\n tKVrKV,\n scale,\n wg_idx,\n )\n self.maybe_store_checkpoint(\n tKVrKV,\n g_state_checkpoints,\n checkpoint_cu_starts,\n checkpoint_every_n_tokens,\n kv_thr_mma,\n work_desc.seq_idx,\n o_head_idx,\n num_sab_heads,\n total_checkpoints,\n cutlass.Int32(self.BLK_KV),\n work_desc.seq_len,\n )\n\n for blk in cutlass.range(\n cutlass.Int32(1), num_blocks - cutlass.Int32(1), cutlass.Int32(1), unroll=1\n ):\n (\n q_consumer_state,\n k_consumer_state,\n v_consumer_state,\n o_producer_state,\n alpha_consumer_state,\n beta_consumer_state,\n ) = self.compute_loop_body(\n sQ_SD,\n sK_SD,\n sK_DS,\n sV_DS,\n sQK,\n sKK_inv,\n sKK_opd,\n sO,\n sAlpha,\n sBeta,\n kv_tiled_mma,\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n v_pipeline,\n v_consumer_state,\n o_pipeline,\n o_producer_state,\n alpha_pipeline,\n alpha_consumer_state,\n beta_pipeline,\n beta_consumer_state,\n False,\n False,\n cutlass.Int32(self.BLK_KV),\n tKVrKV,\n scale,\n wg_idx,\n )\n self.maybe_store_checkpoint(\n tKVrKV,\n g_state_checkpoints,\n checkpoint_cu_starts,\n checkpoint_every_n_tokens,\n kv_thr_mma,\n work_desc.seq_idx,\n o_head_idx,\n num_sab_heads,\n total_checkpoints,\n (blk + cutlass.Int32(1)) * cutlass.Int32(self.BLK_KV),\n work_desc.seq_len,\n )\n\n if num_blocks != cutlass.Int32(1):\n last_blk = num_blocks - cutlass.Int32(1)\n last_B = work_desc.seq_len - last_blk * cutlass.Int32(self.BLK_KV)\n (\n q_consumer_state,\n k_consumer_state,\n v_consumer_state,\n o_producer_state,\n alpha_consumer_state,\n beta_consumer_state,\n ) = self.compute_loop_body(\n sQ_SD,\n sK_SD,\n sK_DS,\n sV_DS,\n sQK,\n sKK_inv,\n sKK_opd,\n sO,\n sAlpha,\n sBeta,\n kv_tiled_mma,\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n v_pipeline,\n v_consumer_state,\n o_pipeline,\n o_producer_state,\n alpha_pipeline,\n alpha_consumer_state,\n beta_pipeline,\n beta_consumer_state,\n False,\n True,\n last_B,\n tKVrKV,\n scale,\n wg_idx,\n )\n self.maybe_store_checkpoint(\n tKVrKV,\n g_state_checkpoints,\n checkpoint_cu_starts,\n checkpoint_every_n_tokens,\n kv_thr_mma,\n work_desc.seq_idx,\n o_head_idx,\n num_sab_heads,\n total_checkpoints,\n (last_blk + cutlass.Int32(1)) * cutlass.Int32(self.BLK_KV),\n work_desc.seq_len,\n )\n self.kv_store(tKVrKV, gStateKV, kv_thr_mma)\n\n # ─── Kernel entry point ───────────────────────────────────────────────────\n\n @cute.jit\n def __call__(\n self,\n g_q: cute.Tensor,\n g_k: cute.Tensor,\n g_v: cute.Tensor,\n g_o: cute.Tensor,\n g_alpha: cute.Tensor,\n g_beta: cute.Tensor,\n g_state: cute.Tensor,\n g_init_state: cute.Tensor,\n g_state_indices: cute.Tensor,\n g_state_checkpoints: cute.Tensor,\n checkpoint_cu_starts: cute.Tensor,\n g_tensormaps: cute.Tensor,\n cu_seqlens: cute.Tensor,\n scale: cutlass.Float32,\n num_q_heads: cutlass.Int32,\n num_k_heads: cutlass.Int32,\n num_v_heads: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n num_seqs: cutlass.Int32,\n total_checkpoints: cutlass.Int32,\n checkpoint_every_n_tokens: cutlass.Int32,\n grid_x: int,\n stream,\n ):\n qkv_smem_layout_atom = warpgroup.make_smem_layout_atom(\n warpgroup.SmemLayoutAtomKind.K_SW128,\n self.dtype,\n )\n q_storage_layout = cute.coalesce(\n cute.tile_to_shape(\n qkv_smem_layout_atom,\n (self.BLK_Q, self.D, self.q_stage),\n order=(0, 1, 2),\n ),\n target_profile=(1, 1, 1),\n )\n q_smem_layout = cute.slice_(q_storage_layout, (None, None, 0))\n k_storage_layout_sd = cute.coalesce(\n cute.tile_to_shape(\n qkv_smem_layout_atom,\n (self.BLK_KV, self.D, self.k_stage),\n order=(0, 1, 2),\n ),\n target_profile=(1, 1, 1),\n )\n k_storage_layout_ds = cute.select(k_storage_layout_sd, [1, 0, 2])\n v_storage_layout_sd = cute.coalesce(\n cute.tile_to_shape(\n qkv_smem_layout_atom,\n (self.BLK_KV, self.D, self.v_stage),\n order=(0, 1, 2),\n ),\n target_profile=(1, 1, 1),\n )\n v_storage_layout_ds = cute.select(v_storage_layout_sd, [1, 0, 2])\n k_smem_layout = cute.slice_(k_storage_layout_ds, (None, None, 0))\n v_smem_layout = cute.slice_(v_storage_layout_ds, (None, None, 0))\n o_smem_layout_atom = warpgroup.make_smem_layout_atom(\n warpgroup.SmemLayoutAtomKind.MN_SW32,\n self.dtype,\n )\n o_storage_layout = cute.tile_to_shape(\n o_smem_layout_atom,\n (self.D, self.BLK_Q, self.o_stage),\n order=(1, 0, 2),\n )\n o_smem_layout = cute.slice_(o_storage_layout, (None, None, 0))\n\n tma_load_op = cpasync.CopyBulkTensorTileG2SOp()\n tma_atom_q, tma_tensor_q = cpasync.make_tiled_tma_atom(\n tma_load_op, g_q, q_smem_layout, (self.BLK_Q, self.D)\n )\n tma_atom_k, tma_tensor_k = cpasync.make_tiled_tma_atom(\n tma_load_op, g_k, k_smem_layout, (self.D, self.BLK_KV)\n )\n tma_atom_v, tma_tensor_v = cpasync.make_tiled_tma_atom(\n tma_load_op, g_v, v_smem_layout, (self.D, self.BLK_KV)\n )\n\n tma_store_op = cpasync.CopyBulkTensorTileS2GOp()\n tma_atom_o, tma_tensor_o = cpasync.make_tiled_tma_atom(\n tma_store_op, g_o, o_smem_layout, (self.D, self.BLK_Q)\n )\n\n dtype_bytes = self.dtype.width // 8\n self.tma_load_q_bytes = cute.size(q_smem_layout) * dtype_bytes\n self.tma_load_k_bytes = cute.size(k_smem_layout) * dtype_bytes\n self.tma_load_v_bytes = cute.size(v_smem_layout) * dtype_bytes\n\n qk_layout_atom = cute.make_layout((8, 8), stride=(8, 1))\n qk_storage_layout = cute.tile_to_shape(\n qk_layout_atom, (self.BLK_Q, self.BLK_KV), order=(1, 0)\n )\n kk_storage_layout = cute.tile_to_shape(\n qk_layout_atom, (self.BLK_KV, self.BLK_KV), order=(1, 0)\n )\n alpha_storage_layout = cute.make_layout(\n (self.BLK_Q, AlphaProcessor.NUM_CHANNELS, self.alpha_beta_stage)\n )\n beta_storage_layout = cute.make_layout((self.BLK_KV, self.alpha_beta_stage))\n\n @cute.struct\n class SharedStorage:\n q_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.q_stage * 2]\n k_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.k_stage * 2]\n v_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.v_stage * 2]\n o_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.o_stage * 2]\n alpha_mbar_ptr: cute.struct.MemRange[\n cutlass.Int64, self.alpha_beta_stage * 2\n ]\n beta_mbar_ptr: cute.struct.MemRange[\n cutlass.Int64, self.alpha_beta_stage * 2\n ]\n\n smem_q: cute.struct.Align[\n cute.struct.MemRange[self.dtype, cute.cosize(q_storage_layout)],\n 128,\n ]\n smem_k: cute.struct.Align[\n cute.struct.MemRange[self.dtype, cute.cosize(k_storage_layout_sd)],\n 128,\n ]\n smem_v: cute.struct.Align[\n cute.struct.MemRange[self.dtype, cute.cosize(v_storage_layout_sd)],\n 128,\n ]\n smem_qk: cute.struct.Align[\n cute.struct.MemRange[self.dtype, cute.cosize(qk_storage_layout)],\n 16,\n ]\n smem_kk: cute.struct.Align[\n cute.struct.MemRange[\n self.inverse_dtype, cute.cosize(kk_storage_layout)\n ],\n 16,\n ]\n smem_o: cute.struct.Align[\n cute.struct.MemRange[self.dtype, cute.cosize(o_storage_layout)],\n 128,\n ]\n smem_alpha: cute.struct.Align[\n cute.struct.MemRange[\n cutlass.Float32, cute.cosize(alpha_storage_layout)\n ],\n 16,\n ]\n smem_beta: cute.struct.Align[\n cute.struct.MemRange[cutlass.Float32, cute.cosize(beta_storage_layout)],\n 16,\n ]\n\n self.shared_storage = SharedStorage\n\n self.kernel(\n g_alpha,\n g_beta,\n tma_atom_q,\n tma_tensor_q,\n tma_atom_k,\n tma_tensor_k,\n tma_atom_v,\n tma_tensor_v,\n tma_atom_o,\n tma_tensor_o,\n g_state,\n g_init_state,\n g_state_indices,\n g_state_checkpoints,\n checkpoint_cu_starts,\n g_tensormaps,\n cu_seqlens,\n scale,\n num_q_heads,\n num_k_heads,\n num_v_heads,\n num_sab_heads,\n num_seqs,\n total_checkpoints,\n checkpoint_every_n_tokens,\n ).launch(\n grid=(grid_x, 1, 1),\n block=(384, 1, 1),\n max_number_threads=(384, 1, 1),\n stream=stream,\n min_blocks_per_mp=1,\n )\n\n @cute.kernel\n def kernel(\n self,\n g_alpha: cute.Tensor,\n g_beta: cute.Tensor,\n tma_atom_q: cute.CopyAtom,\n tma_tensor_q: cute.Tensor,\n tma_atom_k: cute.CopyAtom,\n tma_tensor_k: cute.Tensor,\n tma_atom_v: cute.CopyAtom,\n tma_tensor_v: cute.Tensor,\n tma_atom_o: cute.CopyAtom,\n tma_tensor_o: cute.Tensor,\n g_state: cute.Tensor,\n g_init_state: cute.Tensor,\n g_state_indices: cute.Tensor,\n g_state_checkpoints: cute.Tensor,\n checkpoint_cu_starts: cute.Tensor,\n g_tensormaps: cute.Tensor,\n cu_seqlens: cute.Tensor,\n scale: cutlass.Float32,\n num_q_heads: cutlass.Int32,\n num_k_heads: cutlass.Int32,\n num_v_heads: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n num_seqs: cutlass.Int32,\n total_checkpoints: cutlass.Int32,\n checkpoint_every_n_tokens: cutlass.Int32,\n ):\n NUM_LOAD_WARP_GROUPS = 1\n NUM_MMA_WARP_GROUPS = 2\n THREADS_PER_WARP_GROUP = 128\n WARPS_PER_WARP_GROUP = 4\n MIN_BLOCKS_PER_MP = 1\n MAX_THREADS_PER_BLOCK = (\n NUM_LOAD_WARP_GROUPS + NUM_MMA_WARP_GROUPS\n ) * THREADS_PER_WARP_GROUP\n load_registers, mma_registers = self.get_register_requirements(\n MAX_THREADS_PER_BLOCK,\n MIN_BLOCKS_PER_MP,\n NUM_MMA_WARP_GROUPS,\n THREADS_PER_WARP_GROUP,\n )\n\n tidx, _, _ = cute.arch.thread_idx()\n warp_idx = cute.arch.make_warp_uniform(cute.arch.warp_idx())\n warp_group_idx = cute.arch.make_warp_uniform(\n tidx // cutlass.Int32(THREADS_PER_WARP_GROUP)\n )\n ldst_warp_role = cute.arch.make_warp_uniform(\n warp_idx % cutlass.Int32(WARPS_PER_WARP_GROUP)\n )\n\n if warp_idx == LoadStoreWarpRole.LOAD_QKV:\n cpasync.prefetch_descriptor(tma_atom_q)\n cpasync.prefetch_descriptor(tma_atom_k)\n cpasync.prefetch_descriptor(tma_atom_v)\n cpasync.prefetch_descriptor(tma_atom_o)\n\n work_desc = self.get_next_work(\n cu_seqlens,\n num_q_heads,\n num_v_heads,\n num_sab_heads,\n )\n tok_end = work_desc.tok_offset + work_desc.seq_len\n num_blocks = (\n work_desc.seq_len + cutlass.Int32(self.BLK_KV) - cutlass.Int32(1)\n ) // cutlass.Int32(self.BLK_KV)\n\n # math_tidx / wg_idx: valid for Math WG threads; LdSt WG gets negative values (unused)\n math_tidx = tidx - cutlass.Int32(THREADS_PER_WARP_GROUP)\n wg_idx = math_tidx // cutlass.Int32(THREADS_PER_WARP_GROUP)\n\n # ── Smem allocation ───────────────────────────────────────────────────\n allocator = cutlass.utils.SmemAllocator()\n storage = allocator.allocate(self.shared_storage)\n\n qkv_smem_layout_atom = warpgroup.make_smem_layout_atom(\n warpgroup.SmemLayoutAtomKind.K_SW128,\n self.dtype,\n )\n q_layout_sd = cute.coalesce(\n cute.tile_to_shape(\n qkv_smem_layout_atom,\n (self.BLK_Q, self.D, self.q_stage),\n order=(0, 1, 2),\n ),\n target_profile=(1, 1, 1),\n )\n sQ_SD = storage.smem_q.get_tensor(q_layout_sd.outer, swizzle=q_layout_sd.inner)\n\n k_layout_sd = cute.coalesce(\n cute.tile_to_shape(\n qkv_smem_layout_atom,\n (self.BLK_KV, self.D, self.k_stage),\n order=(0, 1, 2),\n ),\n target_profile=(1, 1, 1),\n )\n k_layout_ds = cute.select(k_layout_sd, [1, 0, 2])\n sK_SD = storage.smem_k.get_tensor(k_layout_sd.outer, swizzle=k_layout_sd.inner)\n sK_DS = storage.smem_k.get_tensor(k_layout_ds.outer, swizzle=k_layout_ds.inner)\n\n v_layout_sd = cute.coalesce(\n cute.tile_to_shape(\n qkv_smem_layout_atom,\n (self.BLK_KV, self.D, self.v_stage),\n order=(0, 1, 2),\n ),\n target_profile=(1, 1, 1),\n )\n v_layout_ds = cute.select(v_layout_sd, [1, 0, 2])\n sV_DS = storage.smem_v.get_tensor(v_layout_ds.outer, swizzle=v_layout_ds.inner)\n\n qk_layout_atom = cute.make_layout((8, 8), stride=(8, 1))\n qk_layout = cute.tile_to_shape(\n qk_layout_atom, (self.BLK_Q, self.BLK_KV), order=(1, 0)\n )\n sQK = storage.smem_qk.get_tensor(qk_layout)\n\n kk_layout = cute.tile_to_shape(\n qk_layout_atom, (self.BLK_KV, self.BLK_KV), order=(1, 0)\n )\n sKK_inv = storage.smem_kk.get_tensor(kk_layout)\n kk_opd_ptr = cute.recast_ptr(storage.smem_kk.data_ptr(), dtype=self.dtype)\n sKK_opd = cute.make_tensor(kk_opd_ptr, kk_layout)\n\n o_smem_layout_atom = warpgroup.make_smem_layout_atom(\n warpgroup.SmemLayoutAtomKind.MN_SW32,\n self.dtype,\n )\n o_layout = cute.tile_to_shape(\n o_smem_layout_atom,\n (self.D, self.BLK_Q, self.o_stage),\n order=(1, 0, 2),\n )\n sO = storage.smem_o.get_tensor(o_layout.outer, swizzle=o_layout.inner)\n alpha_layout = cute.make_layout(\n (self.BLK_Q, AlphaProcessor.NUM_CHANNELS, self.alpha_beta_stage)\n )\n sAlpha = storage.smem_alpha.get_tensor(alpha_layout)\n\n beta_layout = cute.make_layout((self.BLK_KV, self.alpha_beta_stage))\n sBeta = storage.smem_beta.get_tensor(beta_layout)\n\n load_producer_group = pipeline.CooperativeGroup(pipeline.Agent.Thread, 1)\n load_consumer_group = pipeline.CooperativeGroup(pipeline.Agent.Thread, 8)\n vector_producer_group = pipeline.CooperativeGroup(pipeline.Agent.Thread, 32)\n vector_consumer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread, NUM_MMA_WARP_GROUPS * THREADS_PER_WARP_GROUP\n )\n o_producer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread, NUM_MMA_WARP_GROUPS * THREADS_PER_WARP_GROUP\n )\n o_consumer_group = pipeline.CooperativeGroup(pipeline.Agent.Thread, 32)\n q_pipeline = pipeline.PipelineTmaAsync.create(\n barrier_storage=storage.q_mbar_ptr.data_ptr(),\n num_stages=self.q_stage,\n producer_group=load_producer_group,\n consumer_group=load_consumer_group,\n tx_count=self.tma_load_q_bytes,\n cta_layout_vmnk=cute.make_layout((1, 1, 1, 1)),\n )\n k_pipeline = pipeline.PipelineTmaAsync.create(\n barrier_storage=storage.k_mbar_ptr.data_ptr(),\n num_stages=self.k_stage,\n producer_group=load_producer_group,\n consumer_group=load_consumer_group,\n tx_count=self.tma_load_k_bytes,\n cta_layout_vmnk=cute.make_layout((1, 1, 1, 1)),\n )\n v_pipeline = pipeline.PipelineTmaAsync.create(\n barrier_storage=storage.v_mbar_ptr.data_ptr(),\n num_stages=self.v_stage,\n producer_group=load_producer_group,\n consumer_group=load_consumer_group,\n tx_count=self.tma_load_v_bytes,\n cta_layout_vmnk=cute.make_layout((1, 1, 1, 1)),\n )\n o_pipeline = pipeline.PipelineAsync.create(\n barrier_storage=storage.o_mbar_ptr.data_ptr(),\n num_stages=self.o_stage,\n producer_group=o_producer_group,\n consumer_group=o_consumer_group,\n )\n alpha_pipeline = pipeline.PipelineAsync.create(\n barrier_storage=storage.alpha_mbar_ptr.data_ptr(),\n num_stages=self.alpha_beta_stage,\n producer_group=vector_producer_group,\n consumer_group=vector_consumer_group,\n )\n beta_pipeline = pipeline.PipelineAsync.create(\n barrier_storage=storage.beta_mbar_ptr.data_ptr(),\n num_stages=self.alpha_beta_stage,\n producer_group=vector_producer_group,\n consumer_group=vector_consumer_group,\n )\n cute.arch.mbarrier_init_fence()\n cute.arch.sync_threads()\n\n if (\n work_desc.seq_len != cutlass.Int32(0)\n and warp_group_idx == WarpGroupRole.LDST\n ):\n cute.arch.setmaxregister_decrease(load_registers)\n if ldst_warp_role == LoadStoreWarpRole.LOAD_QKV:\n self.run_load_qkv_role(\n sQ_SD,\n sK_DS,\n sV_DS,\n tma_atom_q,\n tma_tensor_q,\n tma_atom_k,\n tma_tensor_k,\n tma_atom_v,\n tma_tensor_v,\n q_pipeline,\n k_pipeline,\n v_pipeline,\n num_blocks,\n work_desc.tok_offset,\n work_desc.q_head_idx(),\n work_desc.k_head_idx(num_q_heads, num_v_heads),\n work_desc.v_head_idx(),\n )\n elif ldst_warp_role == LoadStoreWarpRole.STORE_O:\n CollectiveStoreTma(self.BLK_Q, self.D).run(\n sO,\n tma_atom_o,\n tma_tensor_o,\n g_tensormaps,\n o_pipeline,\n num_blocks,\n work_desc,\n num_seqs,\n self.o_stage,\n num_q_heads,\n num_v_heads,\n )\n elif ldst_warp_role == LoadStoreWarpRole.LOAD_BETA:\n self.run_load_beta_role(\n sBeta,\n g_beta,\n beta_pipeline,\n num_blocks,\n work_desc.tok_offset,\n tok_end,\n work_desc.o_head_idx(num_q_heads, num_v_heads),\n num_sab_heads,\n )\n elif ldst_warp_role == LoadStoreWarpRole.LOAD_ALPHA:\n self.run_load_alpha_role(\n sAlpha,\n g_alpha,\n alpha_pipeline,\n scale,\n num_blocks,\n work_desc.tok_offset,\n tok_end,\n work_desc.o_head_idx(num_q_heads, num_v_heads),\n num_sab_heads,\n )\n elif work_desc.seq_len != cutlass.Int32(0):\n cute.arch.setmaxregister_increase(mma_registers)\n\n self.run_math_role(\n sQ_SD,\n sK_SD,\n sK_DS,\n sV_DS,\n sQK,\n sKK_inv,\n sKK_opd,\n sO,\n sAlpha,\n sBeta,\n q_pipeline,\n k_pipeline,\n v_pipeline,\n o_pipeline,\n alpha_pipeline,\n beta_pipeline,\n g_state,\n g_init_state,\n g_state_indices,\n g_state_checkpoints,\n checkpoint_cu_starts,\n work_desc,\n scale,\n wg_idx,\n math_tidx,\n num_blocks,\n num_q_heads,\n num_v_heads,\n num_sab_heads,\n num_seqs,\n total_checkpoints,\n checkpoint_every_n_tokens,\n )\n\n\n# ─── Public API ──────────────────────────────────────────────────────────────\n\n\ndef delta_rule_prefill_dsl(\n o: torch.Tensor, # (total_seqlen, num_o_heads, D) fp16/bf16, output\n state: torch.Tensor, # (num_seqs, num_sab_heads, D, D) fp32, output\n q: torch.Tensor, # (total_seqlen, num_q_heads, D)\n k: torch.Tensor, # (total_seqlen, num_k_heads, D)\n v: torch.Tensor, # (total_seqlen, num_v_heads, D)\n init_state: torch.Tensor | None, # (num_seqs, num_sab_heads, D, D) fp32, optional\n alpha: torch.Tensor | None,\n beta: torch.Tensor | None,\n cu_seqlens: torch.Tensor, # (num_seqs+1,) int64\n scale: float,\n state_checkpoints: torch.Tensor | None = None,\n checkpoint_cu_starts: torch.Tensor | None = None,\n checkpoint_every_n_tokens: int = 0,\n state_indices: torch.Tensor | None = None,\n):\n from cutlass.cute.runtime import from_dlpack\n import cuda.bindings.driver as cuda_driver\n\n D = q.shape[-1]\n\n num_seqs = cu_seqlens.shape[0] - 1\n num_q_heads = q.shape[1]\n num_k_heads = k.shape[1]\n num_v_heads = v.shape[1]\n num_sab_heads = max(num_q_heads, num_v_heads)\n\n if not _FullyFusedDeltaRuleSm120.can_implement(\n num_q_heads, num_k_heads, num_v_heads, D, q.element_size()\n ):\n raise RuntimeError(\"can_implement failed\")\n if D != 128:\n raise RuntimeError(f\"DSL kernel only supports D=128, got {D}\")\n\n needs_alpha = alpha is not None\n needs_beta = beta is not None\n needs_init_state = init_state is not None\n needs_checkpointing = checkpoint_every_n_tokens > 0\n use_state_indices = state_indices is not None\n kernel_dtype = {\n torch.float16: cutlass.Float16,\n torch.bfloat16: cutlass.BFloat16,\n }.get(q.dtype)\n if kernel_dtype is None:\n raise RuntimeError(f\"DSL kernel only supports fp16/bf16 inputs, got {q.dtype}\")\n\n if k.dtype != q.dtype or v.dtype != q.dtype or o.dtype != q.dtype:\n raise RuntimeError(\n f\"q/k/v/o dtypes must match, got {q.dtype}, {k.dtype}, {v.dtype}, {o.dtype}\"\n )\n if alpha is not None and alpha.dtype != torch.float32:\n raise RuntimeError(f\"alpha must have dtype torch.float32, got {alpha.dtype}\")\n if beta is not None and beta.dtype != torch.float32:\n raise RuntimeError(f\"beta must have dtype torch.float32, got {beta.dtype}\")\n if init_state is not None:\n state_dtype_to_cutlass(init_state.dtype)\n state_dtype_to_cutlass(state.dtype)\n if state_checkpoints is not None:\n state_dtype_to_cutlass(state_checkpoints.dtype)\n if not is_integer_dtype(cu_seqlens.dtype):\n raise RuntimeError(\n f\"cu_seqlens must have an integer dtype, got {cu_seqlens.dtype}\"\n )\n\n expected_state_tail = (num_sab_heads, D, D)\n for name, tensor in ((\"state\", state), (\"init_state\", init_state)):\n if tensor is None:\n continue\n if (\n not use_state_indices and tensor.shape != (num_seqs, *expected_state_tail)\n ) or (use_state_indices and tuple(tensor.shape[1:]) != expected_state_tail):\n raise RuntimeError(\n f\"{name} must have shape \"\n f\"{('[N_pool]' if use_state_indices else f'[{num_seqs}]')} + {expected_state_tail}, \"\n f\"got {tuple(tensor.shape)}\"\n )\n if use_state_indices and (\n not is_integer_dtype(state_indices.dtype) or state_indices.shape != (num_seqs,)\n ):\n raise RuntimeError(\n f\"state_indices must have shape {(num_seqs,)} and an integer dtype\"\n )\n\n for name, tensor in (\n (\"q\", q),\n (\"k\", k),\n (\"v\", v),\n (\"o\", o),\n (\"cu_seqlens\", cu_seqlens),\n ):\n if not tensor.is_contiguous():\n raise RuntimeError(f\"{name} must be contiguous\")\n for name, tensor in (\n (\"alpha\", alpha),\n (\"beta\", beta),\n (\"state_indices\", state_indices),\n ):\n if tensor is not None and not tensor.is_contiguous():\n raise RuntimeError(f\"{name} must be contiguous\")\n for name, tensor in ((\"state\", state), (\"init_state\", init_state)):\n if tensor is None:\n continue\n if not use_state_indices and not tensor.is_contiguous():\n raise RuntimeError(f\"{name} must be contiguous\")\n\n total_seqlen = q.shape[0]\n num_o_heads = o.shape[1]\n q_tma = q.as_strided(\n (total_seqlen, D, num_q_heads),\n (num_q_heads * D, 1, D),\n )\n k_tma = k.as_strided(\n (D, total_seqlen, num_k_heads),\n (1, num_k_heads * D, D),\n )\n v_tma = v.as_strided(\n (D, total_seqlen, num_v_heads),\n (1, num_v_heads * D, D),\n )\n o_tma = o.as_strided(\n (D, total_seqlen, num_o_heads),\n (1, num_o_heads * D, D),\n )\n total_checkpoints = state_checkpoints.shape[0] if needs_checkpointing else 1\n\n workspace_size = get_device_sm_count(q.device) * 128\n tensormaps_t = _get_cache_buf(\"gdn_prefill_tensormaps\", workspace_size, q.device)\n\n stream_val = torch.cuda.current_stream().cuda_stream\n stream = cuda_driver.CUstream(stream_val)\n\n enable_tvm_ffi = True\n if enable_tvm_ffi:\n from_dlpack = lambda *args, **kwargs: cute.runtime.from_dlpack(\n *args, **{**kwargs, \"enable_tvm_ffi\": True}\n )\n\n # Keep head counts and varlen extents runtime values across cached compiles.\n q_cute = from_dlpack(q_tma, assumed_align=16).mark_layout_dynamic(leading_dim=1)\n k_cute = from_dlpack(k_tma, assumed_align=16).mark_layout_dynamic(leading_dim=0)\n v_cute = from_dlpack(v_tma, assumed_align=16).mark_layout_dynamic(leading_dim=0)\n o_cute = from_dlpack(o_tma, assumed_align=16).mark_layout_dynamic(leading_dim=0)\n alpha_cute = (\n from_dlpack(alpha.reshape(-1), assumed_align=16).mark_layout_dynamic()\n if needs_alpha\n else None\n )\n beta_cute = (\n from_dlpack(beta.reshape(-1), assumed_align=16).mark_layout_dynamic()\n if needs_beta\n else None\n )\n state_cute = from_dlpack(state, assumed_align=16).mark_layout_dynamic()\n init_state_cute = (\n from_dlpack(init_state, assumed_align=16).mark_layout_dynamic()\n if needs_init_state\n else None\n )\n state_indices_cute = (\n from_dlpack(state_indices, assumed_align=4).mark_layout_dynamic()\n if use_state_indices\n else None\n )\n state_checkpoints_cute = (\n from_dlpack(\n state_checkpoints.reshape(-1), assumed_align=16\n ).mark_layout_dynamic()\n if needs_checkpointing\n else None\n )\n checkpoint_cu_cute = (\n from_dlpack(checkpoint_cu_starts, assumed_align=8).mark_layout_dynamic()\n if needs_checkpointing\n else None\n )\n tensormaps_cute = from_dlpack(tensormaps_t, assumed_align=128).mark_layout_dynamic()\n cu_cute = from_dlpack(cu_seqlens, assumed_align=8).mark_layout_dynamic()\n\n delta_rule_kernel = _FullyFusedDeltaRuleSm120(\n needs_alpha,\n needs_beta,\n needs_init_state,\n needs_checkpointing,\n kernel_dtype,\n initial_state_dtype=state_dtype_to_cutlass(\n init_state.dtype if needs_init_state else torch.float32\n ),\n state_dtype=state_dtype_to_cutlass(state.dtype),\n checkpoint_state_dtype=state_dtype_to_cutlass(\n state_checkpoints.dtype if needs_checkpointing else torch.float32\n ),\n use_state_indices=use_state_indices,\n cu_seqlens_dtype=cu_seqlens.dtype,\n state_indices_dtype=state_indices.dtype if use_state_indices else None,\n checkpoint_cu_starts_dtype=(\n checkpoint_cu_starts.dtype if needs_checkpointing else None\n ),\n state_inner_strides=(tuple(state.stride()[1:]) if use_state_indices else None),\n init_state_inner_strides=(\n tuple(init_state.stride()[1:])\n if use_state_indices and needs_init_state\n else None\n ),\n )\n\n kernel_args = (\n q_cute,\n k_cute,\n v_cute,\n o_cute,\n alpha_cute,\n beta_cute,\n state_cute,\n init_state_cute,\n state_indices_cute,\n state_checkpoints_cute,\n checkpoint_cu_cute,\n tensormaps_cute,\n cu_cute,\n cutlass.Float32(scale),\n cutlass.Int32(num_q_heads),\n cutlass.Int32(num_k_heads),\n cutlass.Int32(num_v_heads),\n cutlass.Int32(num_sab_heads),\n cutlass.Int32(num_seqs),\n cutlass.Int32(total_checkpoints),\n cutlass.Int32(checkpoint_every_n_tokens),\n num_seqs * num_sab_heads,\n stream,\n )\n compiled_delta_rule_kernel = cached_compile(\n delta_rule_kernel,\n *kernel_args,\n compile_options=sm12x_compile_options(q.device),\n )\n compiled_delta_rule_kernel(*kernel_args)\n"},"after_code":{"kind":"string","value":"import functools\nfrom enum import IntEnum\n\nimport torch\nimport cutlass\nimport cutlass.cute as cute\nimport cutlass.pipeline as pipeline\nfrom cutlass.cute.nvgpu import warp, warpgroup, cpasync\nfrom ...utils import get_device_sm_count, _get_cache_buf\nfrom .alpha import AlphaProcessor\nfrom .collective_store_tma import CollectiveStoreTma\nfrom .custom_compile_cache import (\n KeyedCompileMixin,\n cached_compile,\n get_cached_compile,\n sm12x_compile_options,\n)\nfrom .collective_inverse_hmma import CollectiveInverse\nfrom .helpers import SM80, round_down, state_dtype_to_cutlass\nfrom .schedule import WorkDesc\nfrom .varlen_helper import is_integer_dtype\n\n\n@functools.cache\ndef _sm120_compile_options(device):\n return (cute.EnableTVMFFI(True),) + sm12x_compile_options(device)\n\n\n# ─── Named-barrier IDs used by the compute kernel ────────────────────────────\n# Must not conflict with each other or with pipeline barrier storage.\n\n\nclass NamedBarrier(IntEnum):\n MATH_WG0 = 4 # OrderedMathBarriers: StreamkBarrier0\n MATH_WG1 = 5 # OrderedMathBarriers: StreamkBarrier1\n KK_SYNC = 13 # sync all 128 WG0 threads before collective_inverse\n\n\nclass WarpGroupRole(IntEnum):\n LDST = 0\n MATH_KK = 1\n MATH_QK = 2\n\n\nclass LoadStoreWarpRole(IntEnum):\n LOAD_QKV = 0\n STORE_O = 1\n LOAD_BETA = 2\n LOAD_ALPHA = 3\n\n\nclass MathWarpGroupRole(IntEnum):\n KK = 0\n QK = 1\n\n\n# ─── Warp-specialized delta-rule kernel ───────────────────────────────────────\n# Grid: (num_seqs * num_sab_heads, 1, 1)\n# Block: 384 threads → WG0=[0,127], WG1=[128,255], WG2=[256,383]\n#\n# needs_alpha / needs_beta / needs_init_state are class attributes set in __init__.\n# The JIT compiler specialises per instance, so they are compile-time booleans\n# inside the kernel without any parameter-passing trickery.\n\n\nclass _FullyFusedDeltaRuleSm120(KeyedCompileMixin):\n @staticmethod\n def get_register_requirements(\n max_threads_per_block: int,\n min_blocks_per_multiprocessor: int,\n num_mma_warp_groups: int,\n threads_per_warp_group: int,\n ) -> tuple[int, int]:\n reg_alloc_granularity = 8\n load_registers = 40 - 2 * reg_alloc_granularity\n total_registers = (\n round_down(\n 64 * 1024 // min_blocks_per_multiprocessor,\n max_threads_per_block * reg_alloc_granularity,\n )\n // threads_per_warp_group\n )\n mma_registers = round_down(\n (total_registers - load_registers) // num_mma_warp_groups,\n reg_alloc_granularity,\n )\n return min(248, load_registers), min(248, mma_registers)\n\n @staticmethod\n def can_implement(\n num_q_heads: int,\n num_k_heads: int,\n num_v_heads: int,\n head_size: int,\n element_size: int,\n ) -> bool:\n ratio = (\n num_q_heads // num_v_heads\n if num_q_heads > num_v_heads\n else num_v_heads // num_q_heads\n )\n is_gva_enabled = num_v_heads > num_q_heads\n\n is_gqa_like = (\n (num_k_heads == num_v_heads)\n and (num_q_heads == ratio * num_k_heads)\n and (num_q_heads == ratio * num_v_heads)\n )\n is_gva_like = (\n (num_q_heads == num_k_heads)\n and (num_v_heads == ratio * num_q_heads)\n and (num_v_heads == ratio * num_k_heads)\n )\n\n alignment = 16 // element_size\n return (\n ((not is_gva_enabled and is_gqa_like) or (is_gva_enabled and is_gva_like))\n and (head_size <= 128)\n and ((head_size % alignment) == 0)\n )\n\n def __init__(\n self,\n needs_alpha: bool,\n needs_beta: bool,\n needs_init_state: bool,\n needs_checkpointing: bool,\n dtype: type[cutlass.Numeric] = cutlass.Float16,\n acc_dtype: type[cutlass.Numeric] = cutlass.Float32,\n initial_state_dtype: type[cutlass.Numeric] = cutlass.Float32,\n state_dtype: type[cutlass.Numeric] = cutlass.Float32,\n checkpoint_state_dtype: type[cutlass.Numeric] = cutlass.Float32,\n use_state_indices: bool = False,\n cu_seqlens_dtype: torch.dtype = torch.int64,\n state_indices_dtype: torch.dtype | None = None,\n checkpoint_cu_starts_dtype: torch.dtype | None = None,\n state_inner_strides: tuple[int, ...] | None = None,\n init_state_inner_strides: tuple[int, ...] | None = None,\n ):\n self.needs_alpha = needs_alpha\n self.needs_beta = needs_beta\n self.needs_init_state = needs_init_state\n self.needs_checkpointing = needs_checkpointing\n self.dtype = dtype\n self.acc_dtype = acc_dtype\n self.initial_state_dtype = initial_state_dtype\n self.state_dtype = state_dtype\n self.checkpoint_state_dtype = checkpoint_state_dtype\n self.use_state_indices = use_state_indices\n self.cu_seqlens_dtype = cu_seqlens_dtype\n self.state_indices_dtype = state_indices_dtype\n self.checkpoint_cu_starts_dtype = checkpoint_cu_starts_dtype\n self.state_inner_strides = state_inner_strides\n self.init_state_inner_strides = init_state_inner_strides\n self.inverse_dtype = cutlass.Float16\n self.BLK_Q = 64\n self.BLK_KV = 64\n self.D = 128\n self.q_stage = 1\n self.k_stage = 2\n self.v_stage = 1\n self.o_stage = 1\n self.alpha_beta_stage = 2\n self.manual_cache_key(\n \"needs_alpha\",\n \"needs_beta\",\n \"needs_init_state\",\n \"needs_checkpointing\",\n \"dtype\",\n \"acc_dtype\",\n \"initial_state_dtype\",\n \"state_dtype\",\n \"checkpoint_state_dtype\",\n \"use_state_indices\",\n \"cu_seqlens_dtype\",\n \"state_indices_dtype\",\n \"checkpoint_cu_starts_dtype\",\n \"state_inner_strides\",\n \"init_state_inner_strides\",\n \"inverse_dtype\",\n \"BLK_Q\",\n \"BLK_KV\",\n \"D\",\n \"q_stage\",\n \"k_stage\",\n \"v_stage\",\n \"o_stage\",\n \"alpha_beta_stage\",\n )\n\n def get_next_work(\n self,\n cu_seqlens: cute.Tensor,\n num_q_heads: cutlass.Int32,\n num_v_heads: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n ) -> WorkDesc:\n bx, _, _ = cute.arch.block_idx()\n seq_idx = bx // num_sab_heads\n o_head_idx = bx % num_sab_heads\n q_head_idx = o_head_idx * num_q_heads // num_sab_heads\n v_head_idx = o_head_idx * num_v_heads // num_sab_heads\n tok_start = cu_seqlens[seq_idx]\n seq_len = cutlass.Int32(cu_seqlens[seq_idx + 1] - tok_start)\n\n return WorkDesc(\n seq_idx=seq_idx,\n private_q_head_idx=q_head_idx,\n private_v_head_idx=v_head_idx,\n tok_offset=tok_start,\n seq_len=seq_len,\n tile_idx=cutlass.Int32(0),\n )\n\n # ─── Ordered 2-WG math barriers ───────────────────────────────────────────\n # Translates flat::OrderedNamedBarriers<UseReservedNB, NB0, NB1>.\n # wg_idx: MathWarpGroupRole.KK or MathWarpGroupRole.QK.\n\n @cute.jit\n def _math_order_init(self, wg_idx: cutlass.Int32):\n \"\"\"Pre-arrive at WG0's barrier so WG0 is unblocked on the first wait.\"\"\"\n if wg_idx == MathWarpGroupRole.QK:\n cute.arch.barrier_arrive(\n barrier_id=NamedBarrier.MATH_WG0, number_of_threads=256\n )\n\n @cute.jit\n def _math_order_wait(self, wg_idx: cutlass.Int32):\n \"\"\"Arrive+wait on this WG's own ordered barrier.\"\"\"\n if wg_idx == MathWarpGroupRole.KK:\n cute.arch.barrier(barrier_id=NamedBarrier.MATH_WG0, number_of_threads=256)\n else:\n cute.arch.barrier(barrier_id=NamedBarrier.MATH_WG1, number_of_threads=256)\n\n @cute.jit\n def _math_order_notify(self, wg_idx: cutlass.Int32):\n \"\"\"Arrive at the other WG's barrier to unblock it.\"\"\"\n if wg_idx == MathWarpGroupRole.KK:\n cute.arch.barrier_arrive(\n barrier_id=NamedBarrier.MATH_WG1, number_of_threads=256\n )\n else:\n cute.arch.barrier_arrive(\n barrier_id=NamedBarrier.MATH_WG0, number_of_threads=256\n )\n\n # ─── kk_store_and_inv ─────────────────────────────────────────────────────\n\n @cute.jit\n def _kk_store_and_inv(\n self,\n tKKrKK: cute.Tensor, # fp32 KK accumulator (from 128-thread kk_tiled_mma)\n kk_tiled_mma,\n kk_thread_idx: cutlass.Int32,\n sKK_inv: cute.Tensor, # (BlkKV, BlkKV)\n sKK_opd: cute.Tensor, # sKK_inv storage recast as Element for MMA operand\n sBeta: cute.Tensor, # (BlkKV, StagesBeta) - used when needs_beta\n beta_pipe_idx: cutlass.Int32,\n tKKcMkk: cute.Tensor, # coordinate mapping for KK fragment\n ):\n \"\"\"Store tKKrKK → sKK_inv, Inverse, optionally reload+beta.\"\"\"\n stsm_atom = cute.make_copy_atom(\n warp.StMatrix8x8x16bOp(transpose=False, num_matrices=4), self.inverse_dtype\n )\n tiled_store = cute.make_tiled_copy_C(stsm_atom, kk_tiled_mma)\n thr_store = tiled_store.get_slice(kk_thread_idx)\n tKKsKK = thr_store.partition_D(sKK_inv)\n tKKrKK_inv = cute.make_fragment_like(tKKrKK, self.inverse_dtype)\n tKKrKK_cv = thr_store.retile(tKKrKK_inv)\n for i in cutlass.range_constexpr(cute.size(tKKrKK)):\n tKKrKK_inv[i] = self.inverse_dtype(tKKrKK[i])\n cute.copy(tiled_store, tKKrKK_cv, tKKsKK)\n\n cute.arch.barrier(barrier_id=NamedBarrier.KK_SYNC, number_of_threads=128)\n CollectiveInverse().run(sKK_inv, NamedBarrier.KK_SYNC)\n\n if cutlass.const_expr(self.needs_beta or self.dtype != self.inverse_dtype):\n cute.arch.barrier(barrier_id=NamedBarrier.KK_SYNC, number_of_threads=128)\n ldsm_atom = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(transpose=False, num_matrices=4),\n self.inverse_dtype,\n )\n tiled_load = cute.make_tiled_copy_C(ldsm_atom, kk_tiled_mma)\n thr_load = tiled_load.get_slice(kk_thread_idx)\n tKKrKK_cpy = cute.make_fragment_like(tKKrKK_inv)\n tKKrKK_cvt = cute.make_fragment_like(tKKrKK_inv, self.dtype)\n tKKrKK_cv2 = thr_load.retile(tKKrKK_cpy)\n cute.copy(tiled_load, thr_load.partition_S(sKK_inv), tKKrKK_cv2)\n tKKcMkk_cv = thr_load.retile(tKKcMkk)\n\n for i in cutlass.range_constexpr(cute.size(tKKrKK_cpy)):\n if cutlass.const_expr(self.needs_beta):\n _, t = tKKcMkk_cv[i]\n tKKrKK_cvt[i] = self.dtype(\n cutlass.Float32(tKKrKK_cpy[i])\n * cutlass.Float32(sBeta[t, beta_pipe_idx])\n )\n else:\n tKKrKK_cvt[i] = self.dtype(tKKrKK_cpy[i])\n\n tKKsKK2 = thr_store.partition_D(sKK_opd)\n tKKrKK_cv3 = thr_store.retile(tKKrKK_cvt)\n cute.copy(tiled_store, tKKrKK_cv3, tKKsKK2)\n\n # ─── kk_epi ───────────────────────────────────────────────────────────────\n\n @cute.jit\n def kk_epi(\n self,\n tKKrKK: cute.Tensor,\n tKKcMkk: cute.Tensor,\n sAlpha: cute.Tensor,\n sBeta: cute.Tensor,\n alpha_stage: cutlass.Int32,\n beta_stage: cutlass.Int32,\n ):\n if cutlass.const_expr(self.needs_alpha):\n alpha_cumlog = sAlpha[None, AlphaProcessor.CUMSUM_LOG, alpha_stage]\n for i in cutlass.range_constexpr(cute.size(tKKrKK)):\n s, t = tKKcMkk[i]\n tKKrKK[i] = tKKrKK[i] * cute.math.exp2(\n cutlass.Float32(alpha_cumlog[s]) - cutlass.Float32(alpha_cumlog[t]),\n fastmath=True,\n )\n if cutlass.const_expr(self.needs_beta):\n beta_row = sBeta[None, beta_stage]\n for i in cutlass.range_constexpr(cute.size(tKKrKK)):\n s, _ = tKKcMkk[i]\n tKKrKK[i] = tKKrKK[i] * cutlass.Float32(beta_row[s])\n\n # ─── qk_or_kk_mask ────────────────────────────────────────────────────────\n\n @cute.jit\n def qk_or_kk_mask(\n self,\n frag: cute.Tensor,\n coord_tensor: cute.Tensor,\n is_final_block: bool,\n B: cutlass.Int32,\n ):\n for i in cutlass.range_constexpr(cute.size(frag)):\n s, t = coord_tensor[i]\n pred = s >= t\n if cutlass.const_expr(is_final_block):\n pred = pred and (s < B and t < B)\n if not pred:\n frag[i] = cutlass.Float32(0.0)\n\n # ─── qk_epi ───────────────────────────────────────────────────────────────\n\n @cute.jit\n def qk_epi(\n self,\n tQKrQK: cute.Tensor,\n tQKcMqk: cute.Tensor,\n sAlpha: cute.Tensor,\n alpha_stage: cutlass.Int32,\n scale: cutlass.Float32,\n ):\n if cutlass.const_expr(self.needs_alpha):\n alpha_cumlog = sAlpha[None, AlphaProcessor.CUMSUM_LOG, alpha_stage]\n for i in cutlass.range_constexpr(cute.size(tQKrQK)):\n s, t = tQKcMqk[i]\n tQKrQK[i] = (\n tQKrQK[i]\n * cute.math.exp2(\n cutlass.Float32(alpha_cumlog[s])\n - cutlass.Float32(alpha_cumlog[t]),\n fastmath=True,\n )\n * scale\n )\n else:\n for i in cutlass.range_constexpr(cute.size(tQKrQK)):\n tQKrQK[i] = tQKrQK[i] * scale\n\n # ─── qk_store ─────────────────────────────────────────────────────────────\n\n @cute.jit\n def qk_store(\n self,\n tQKrQK: cute.Tensor,\n sQK: cute.Tensor,\n qk_tiled_mma,\n qk_thread_idx: cutlass.Int32,\n ):\n stsm_atom = cute.make_copy_atom(\n warp.StMatrix8x8x16bOp(transpose=False, num_matrices=4), self.dtype\n )\n qk_tiled_copy = cute.make_tiled_copy_C(stsm_atom, qk_tiled_mma)\n qk_thr_copy = qk_tiled_copy.get_slice(qk_thread_idx)\n tQKsQK = qk_thr_copy.partition_D(sQK)\n tQKrQK_cvt = cute.make_fragment_like(tQKrQK, self.dtype)\n tQKrQK_cvt_cv = qk_thr_copy.retile(tQKrQK_cvt)\n for i in cutlass.range_constexpr(cute.size(tQKrQK)):\n tQKrQK_cvt[i] = self.dtype(tQKrQK[i])\n cute.copy(qk_tiled_copy, tQKrQK_cvt_cv, tQKsQK)\n\n # ─── o1_epi ───────────────────────────────────────────────────────────────\n\n @cute.jit\n def o1_epi(\n self,\n tOrO: cute.Tensor,\n tOcO: cute.Tensor,\n sAlpha: cute.Tensor,\n alpha_stage: cutlass.Int32,\n scale: cutlass.Float32,\n ):\n if cutlass.const_expr(self.needs_alpha):\n alpha_cpscale = sAlpha[None, AlphaProcessor.CUMPROD_SCALE, alpha_stage]\n for i in cutlass.range_constexpr(cute.size(tOrO)):\n _, tok_q = tOcO[i]\n tOrO[i] = cutlass.Float32(alpha_cpscale[tok_q]) * tOrO[i]\n else:\n for i in cutlass.range_constexpr(cute.size(tOrO)):\n tOrO[i] = scale * tOrO[i]\n\n # ─── sk_epi ───────────────────────────────────────────────────────────────\n\n @cute.jit\n def sk_epi(\n self,\n tSKrSK: cute.Tensor,\n tSKcSK: cute.Tensor,\n sAlpha: cute.Tensor,\n alpha_stage: cutlass.Int32,\n ):\n if cutlass.const_expr(self.needs_alpha):\n alpha_cp = sAlpha[None, AlphaProcessor.CUMPROD, alpha_stage]\n for i in cutlass.range_constexpr(cute.size(tSKrSK)):\n _, tok_kv = tSKcSK[i]\n tSKrSK[i] = tSKrSK[i] * cutlass.Float32(alpha_cp[tok_kv])\n\n # ─── sk_load_v ────────────────────────────────────────────────────────────\n\n @cute.jit\n def sk_load_v(\n self,\n tSKrSK: cute.Tensor,\n sV_DS: cute.Tensor,\n sk_tiled_copy_C,\n sk_thr_copy_C,\n v_stage: cutlass.Int32,\n ) -> cute.Tensor:\n tSKrV = cute.make_fragment_like(tSKrSK, self.dtype)\n tSKrV_cv = sk_thr_copy_C.retile(tSKrV)\n tSKsV = sk_thr_copy_C.partition_S(sV_DS)\n cute.copy(sk_tiled_copy_C, tSKsV[None, None, None, v_stage], tSKrV_cv)\n return tSKrV\n\n # ─── kv_decay_v ───────────────────────────────────────────────────────────\n\n @cute.jit\n def kv_decay_v(\n self,\n tKVrV: cute.Tensor,\n tKVcV: cute.Tensor,\n sAlpha: cute.Tensor,\n alpha_stage: cutlass.Int32,\n is_final_block: bool,\n B: cutlass.Int32,\n ):\n if cutlass.const_expr(self.needs_alpha):\n alpha_cumlog = sAlpha[None, AlphaProcessor.CUMSUM_LOG, alpha_stage]\n block_log = cutlass.Float32(alpha_cumlog[B - cutlass.Int32(1)])\n for i in cutlass.range_constexpr(cute.size(tKVrV)):\n _, tok = tKVcV[i]\n coeff = cute.math.exp2(\n block_log - cutlass.Float32(alpha_cumlog[tok]), fastmath=True\n )\n if cutlass.const_expr(is_final_block):\n if tok >= B:\n coeff = cutlass.Float32(0.0)\n tKVrV[i] = self.dtype(cutlass.Float32(tKVrV[i]) * coeff)\n else:\n for i in cutlass.range_constexpr(cute.size(tKVrV)):\n _, tok = tKVcV[i]\n if cutlass.const_expr(is_final_block):\n if tok >= B:\n tKVrV[i] = self.dtype(0.0)\n\n # ─── o_store ──────────────────────────────────────────────────────────────\n\n @cute.jit\n def o_store(\n self,\n tOrO: cute.Tensor,\n tOsO: cute.Tensor,\n o_tiled_copy_r2s,\n o_thr_copy_r2s,\n ):\n tOrO_f16 = cute.make_fragment_like(tOrO, self.dtype)\n for i in cutlass.range_constexpr(cute.size(tOrO)):\n tOrO_f16[i] = self.dtype(tOrO[i])\n tOrO_cv = o_thr_copy_r2s.retile(tOrO_f16)\n cute.arch.fence_view_async_shared()\n cute.copy(o_tiled_copy_r2s, tOrO_cv, tOsO)\n cute.arch.fence_view_async_shared()\n\n # ─── TMA load helpers ────────────────────────────────────────────────────\n\n @cute.jit\n def load_qkv_tma(\n self,\n sQ_SD: cute.Tensor,\n sK_DS: cute.Tensor,\n sV_DS: cute.Tensor,\n tma_atom_q: cute.CopyAtom,\n tma_tensor_q: cute.Tensor,\n tma_atom_k: cute.CopyAtom,\n tma_tensor_k: cute.Tensor,\n tma_atom_v: cute.CopyAtom,\n tma_tensor_v: cute.Tensor,\n q_pipeline,\n q_producer_state,\n k_pipeline,\n k_producer_state,\n v_pipeline,\n v_producer_state,\n blk: cutlass.Int32,\n tok_start,\n q_head_idx: cutlass.Int32,\n k_head_idx: cutlass.Int32,\n v_head_idx: cutlass.Int32,\n ):\n blk_tok = tok_start + blk * cutlass.Int32(self.BLK_KV)\n\n sK = sK_DS[None, None, k_producer_state.index]\n mK = cute.domain_offset(\n (cutlass.Int32(0), blk_tok),\n tma_tensor_k[None, None, k_head_idx],\n )\n gK = cute.zipped_divide(mK, (self.D, self.BLK_KV))[\n ((None, None), (cutlass.Int32(0), cutlass.Int32(0)))\n ]\n tKsK, tKgK = cpasync.tma_partition(\n tma_atom_k,\n 0,\n cute.make_layout(1),\n cute.group_modes(sK, 0, 2),\n cute.group_modes(gK, 0, 2),\n )\n k_pipeline.producer_acquire(k_producer_state)\n cute.copy(\n tma_atom_k,\n tKgK,\n tKsK,\n tma_bar_ptr=k_pipeline.producer_get_barrier(k_producer_state),\n )\n k_pipeline.producer_commit(k_producer_state)\n k_producer_state.advance()\n\n sQ = sQ_SD[None, None, q_producer_state.index]\n mQ = cute.domain_offset(\n (blk_tok, cutlass.Int32(0)),\n tma_tensor_q[None, None, q_head_idx],\n )\n gQ = cute.zipped_divide(mQ, (self.BLK_Q, self.D))[\n ((None, None), (cutlass.Int32(0), cutlass.Int32(0)))\n ]\n tQsQ, tQgQ = cpasync.tma_partition(\n tma_atom_q,\n 0,\n cute.make_layout(1),\n cute.group_modes(sQ, 0, 2),\n cute.group_modes(gQ, 0, 2),\n )\n q_pipeline.producer_acquire(q_producer_state)\n cute.copy(\n tma_atom_q,\n tQgQ,\n tQsQ,\n tma_bar_ptr=q_pipeline.producer_get_barrier(q_producer_state),\n )\n q_pipeline.producer_commit(q_producer_state)\n q_producer_state.advance()\n\n sV = sV_DS[None, None, v_producer_state.index]\n mV = cute.domain_offset(\n (cutlass.Int32(0), blk_tok),\n tma_tensor_v[None, None, v_head_idx],\n )\n gV = cute.zipped_divide(mV, (self.D, self.BLK_KV))[\n ((None, None), (cutlass.Int32(0), cutlass.Int32(0)))\n ]\n tVsV, tVgV = cpasync.tma_partition(\n tma_atom_v,\n 0,\n cute.make_layout(1),\n cute.group_modes(sV, 0, 2),\n cute.group_modes(gV, 0, 2),\n )\n v_pipeline.producer_acquire(v_producer_state)\n cute.copy(\n tma_atom_v,\n tVgV,\n tVsV,\n tma_bar_ptr=v_pipeline.producer_get_barrier(v_producer_state),\n )\n v_pipeline.producer_commit(v_producer_state)\n v_producer_state.advance()\n return q_producer_state, k_producer_state, v_producer_state\n\n # ─── load_alpha ───────────────────────────────────────────────────────────\n # Translates FlatMainloopTmaWarpSpecializedDeltaRule::load_alpha (scalar load).\n # Caller must sync before calling AlphaProcessor on the loaded data.\n\n @cute.jit\n def load_alpha(\n self,\n sAlpha: cute.Tensor,\n g_alpha: cute.Tensor,\n blk_tok: cutlass.Int32,\n tok_end,\n sab_head_idx: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n alpha_stage: cutlass.Int32,\n ):\n lane_id = cute.arch.lane_idx()\n sAlpha_k = sAlpha[None, None, alpha_stage]\n num_iters = self.BLK_Q // 32\n for i in cutlass.range_constexpr(num_iters):\n row = cutlass.Int32(i * 32) + lane_id\n tok = blk_tok + row\n if tok < tok_end:\n sAlpha_k[row, AlphaProcessor.CUMSUM_LOG] = g_alpha[\n tok * num_sab_heads + sab_head_idx\n ]\n else:\n sAlpha_k[row, AlphaProcessor.CUMSUM_LOG] = cutlass.Float32(1.0)\n\n # ─── load_beta ────────────────────────────────────────────────────────────\n # Translates FlatMainloopTmaWarpSpecializedDeltaRule::load_beta.\n\n @cute.jit\n def load_beta(\n self,\n sBeta: cute.Tensor,\n g_beta: cute.Tensor,\n blk_tok: cutlass.Int32,\n tok_end,\n sab_head_idx: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n beta_stage: cutlass.Int32,\n ):\n lane_id = cute.arch.lane_idx()\n sBeta_k = sBeta[None, beta_stage]\n num_iters = self.BLK_KV // 32\n for i in cutlass.range_constexpr(num_iters):\n row = cutlass.Int32(i * 32) + lane_id\n tok = blk_tok + row\n if tok < tok_end:\n sBeta_k[row] = g_beta[tok * num_sab_heads + sab_head_idx]\n else:\n sBeta_k[row] = cutlass.Float32(0.0)\n\n # ─── kv_load / kv_store ───────────────────────────────────────────────────\n\n @cute.jit\n def kv_load(\n self,\n tKVrKV: cute.Tensor,\n gKV: cute.Tensor,\n kv_thr_mma,\n ):\n c_kv = cute.make_identity_tensor((self.D, self.D))\n tKVcKV = kv_thr_mma.partition_C(c_kv)\n for i in cutlass.range(cute.size(tKVrKV), unroll_full=True):\n v_idx, k_idx = tKVcKV[i]\n tKVrKV[i] = gKV[k_idx, v_idx].to(self.acc_dtype)\n\n @cute.jit\n def kv_store(\n self,\n tKVrKV: cute.Tensor,\n gKV: cute.Tensor,\n kv_thr_mma,\n ):\n c_kv = cute.make_identity_tensor((self.D, self.D))\n tKVcKV = kv_thr_mma.partition_C(c_kv)\n for i in cutlass.range(cute.size(tKVrKV), unroll_full=True):\n v_idx, k_idx = tKVcKV[i]\n gKV[k_idx, v_idx] = tKVrKV[i].to(gKV.element_type)\n\n @cute.jit\n def maybe_store_checkpoint(\n self,\n tKVrKV: cute.Tensor,\n g_state_checkpoints: cute.Tensor,\n checkpoint_cu_starts: cute.Tensor,\n checkpoint_every_n_tokens: cutlass.Int32,\n kv_thr_mma,\n seq_idx: cutlass.Int32,\n o_head_idx: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n total_checkpoints: cutlass.Int32,\n block_end: cutlass.Int32,\n seq_len: cutlass.Int32,\n ):\n if cutlass.const_expr(self.needs_checkpointing):\n if (\n block_end <= seq_len\n and block_end % checkpoint_every_n_tokens == cutlass.Int32(0)\n ):\n checkpoint_idx = (\n cutlass.Int32(checkpoint_cu_starts[seq_idx])\n + block_end // checkpoint_every_n_tokens\n - cutlass.Int32(1)\n )\n checkpoint_layout = cute.make_ordered_layout(\n (self.D, self.D, num_sab_heads, total_checkpoints),\n order=(0, 1, 2, 3),\n )\n mCheckpoint = cute.make_tensor(\n g_state_checkpoints.iterator, checkpoint_layout\n )\n gCheckpointKV = mCheckpoint[None, None, o_head_idx, checkpoint_idx]\n self.kv_store(tKVrKV, gCheckpointKV, kv_thr_mma)\n\n # ─── compute_loop_body ───────────────────────────────────────────────────\n # Translates the C++ compute_loop_body lambda captured inside compute().\n # Called by Math WGs (tidx >= 128) for one block iteration.\n\n @cute.jit\n def compute_loop_body(\n self,\n # Smem tensors (staged; caller indexes the active stage)\n sQ_SD: cute.Tensor, # (BlkQ, D, StagesQ) – row-major atom, swizzled\n sK_SD: cute.Tensor, # (BlkKV, D, StagesK) – same atom\n sK_DS: cute.Tensor, # (D, BlkKV, StagesK) – K transposed\n sV_DS: cute.Tensor, # (D, BlkKV, StagesV) – V transposed\n sQK: cute.Tensor, # (BlkQ, BlkKV)\n sKK_inv: cute.Tensor, # (BlkKV, BlkKV)\n sKK_opd: cute.Tensor, # sKK_inv storage recast as Element\n sO: cute.Tensor, # O output smem (staged)\n sAlpha: cute.Tensor, # (BlkQ, AlphaProcessor.NUM_CHANNELS, StagesAlpha) or zero-shaped\n sBeta: cute.Tensor, # (BlkKV, StagesBeta) or zero-shaped\n kv_tiled_mma,\n # Mainloop pipelines and active read states\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n v_pipeline,\n v_consumer_state,\n o_pipeline,\n o_producer_state,\n alpha_pipeline,\n alpha_consumer_state,\n beta_pipeline,\n beta_consumer_state,\n # Compile-time flags\n is_first_block: bool,\n is_final_block: bool,\n # Valid token count for masking on final block\n B: cutlass.Int32,\n # Running KV state (D×D fp32, in registers across all blocks)\n tKVrKV: cute.Tensor,\n # Scale factor\n scale: cutlass.Float32,\n # WG role: MathWarpGroupRole.KK or MathWarpGroupRole.QK.\n wg_idx: cutlass.Int32,\n ):\n tidx, _, _ = cute.arch.thread_idx()\n thread_idx = tidx - cutlass.Int32(128) # relative to compute threads\n kk_thread_idx = thread_idx % cutlass.Int32(128)\n qk_thread_idx = thread_idx % cutlass.Int32(128)\n\n # ── TiledMMAs ─────────────────────────────────────────────────────────\n blk_q = cute.size(sQ_SD, mode=[0])\n blk_kv = cute.size(sK_SD, mode=[0])\n d = cute.size(sQ_SD, mode=[1])\n tile_shape_qk = (blk_q, blk_kv, d)\n tile_shape_kk = tile_shape_qk\n tile_shape_o1 = (d, blk_q, d)\n tile_shape_o2 = (d, blk_q, blk_kv)\n tile_shape_sk = (d, blk_kv, d)\n tile_shape_newv = (d, blk_kv, blk_kv)\n k_stage = k_consumer_state.index\n q_stage = q_consumer_state.index\n v_stage = v_consumer_state.index\n o_stage = cutlass.Int32(0)\n alpha_stage = alpha_consumer_state.index\n beta_stage = beta_consumer_state.index\n\n mma_atom_4w = warp.MmaF16BF16Op(self.dtype, self.acc_dtype, (16, 8, 16))\n mma_atom_8w = warp.MmaF16BF16Op(self.dtype, self.acc_dtype, (16, 8, 16))\n\n # QK/KK: 4 warps × 16M = 64M (1 warpgroup, 128 threads)\n qk_tiled_mma = cute.make_tiled_mma(\n mma_atom_4w, cute.make_layout((4, 1, 1)), permutation_mnk=tile_shape_qk\n )\n kk_tiled_mma = cute.make_tiled_mma(\n mma_atom_4w, cute.make_layout((4, 1, 1)), permutation_mnk=tile_shape_kk\n )\n\n # O1/O2/SK/NewV: 8 warps × 16M = 128M (both warpgroups, 256 threads)\n o1_tiled_mma = cute.make_tiled_mma(\n mma_atom_8w, cute.make_layout((8, 1, 1)), permutation_mnk=tile_shape_o1\n )\n o2_tiled_mma = cute.make_tiled_mma(\n mma_atom_8w, cute.make_layout((8, 1, 1)), permutation_mnk=tile_shape_o2\n )\n sk_tiled_mma = cute.make_tiled_mma(\n mma_atom_8w, cute.make_layout((8, 1, 1)), permutation_mnk=tile_shape_sk\n )\n newv_tiled_mma = cute.make_tiled_mma(\n mma_atom_8w, cute.make_layout((8, 1, 1)), permutation_mnk=tile_shape_newv\n )\n\n # ── Thread slices ─────────────────────────────────────────────────────\n qk_thr_mma = qk_tiled_mma.get_slice(qk_thread_idx)\n kk_thr_mma = kk_tiled_mma.get_slice(kk_thread_idx)\n sk_thr_mma = sk_tiled_mma.get_slice(thread_idx)\n newv_thr_mma = newv_tiled_mma.get_slice(thread_idx)\n o1_thr_mma = o1_tiled_mma.get_slice(thread_idx)\n o2_thr_mma = o2_tiled_mma.get_slice(thread_idx)\n kv_thr_mma = kv_tiled_mma.get_slice(thread_idx)\n\n # ── Copy atoms ────────────────────────────────────────────────────────\n ldsm_n4 = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(transpose=False, num_matrices=4), self.dtype\n )\n ldsm_t4 = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(transpose=True, num_matrices=4), self.dtype\n )\n\n # ── Active smem slices (extract 2D from staged tensors) ───────────────\n sQ_k = sQ_SD[None, None, q_stage] # (BlkQ, D)\n sK_SD_k = sK_SD[None, None, k_stage] # (BlkKV, D)\n sK_DS_k = sK_DS[None, None, k_stage] # (D, BlkKV)\n\n # ── QK copies ─────────────────────────────────────────────────────────\n qk_tiled_copy_A = cute.make_tiled_copy_A(ldsm_n4, qk_tiled_mma)\n qk_tiled_copy_B = cute.make_tiled_copy_B(ldsm_n4, qk_tiled_mma)\n qk_thr_copy_A = qk_tiled_copy_A.get_slice(qk_thread_idx)\n qk_thr_copy_B = qk_tiled_copy_B.get_slice(qk_thread_idx)\n\n tQKrQ = qk_thr_mma.make_fragment_A(qk_thr_mma.partition_A(sQ_k))\n tQKrQ_cv = qk_thr_copy_A.retile(tQKrQ)\n tQKsQ = qk_thr_copy_A.partition_S(sQ_SD)\n tQKrK = qk_thr_mma.make_fragment_B(qk_thr_mma.partition_B(sK_SD_k))\n tQKrK_cv = qk_thr_copy_B.retile(tQKrK)\n tQKsK = qk_thr_copy_B.partition_S(sK_SD)\n\n # ── KK copies (same atom as QK) ───────────────────────────────────────\n kk_tiled_copy_A = cute.make_tiled_copy_A(ldsm_n4, kk_tiled_mma)\n kk_tiled_copy_B = cute.make_tiled_copy_B(ldsm_n4, kk_tiled_mma)\n kk_thr_copy_A = kk_tiled_copy_A.get_slice(kk_thread_idx)\n kk_thr_copy_B = kk_tiled_copy_B.get_slice(kk_thread_idx)\n\n tKKrA = kk_thr_mma.make_fragment_A(kk_thr_mma.partition_A(sK_SD_k))\n tKKrA_cv = kk_thr_copy_A.retile(tKKrA)\n tKKsA = kk_thr_copy_A.partition_S(sK_SD)\n tKKrB = kk_thr_mma.make_fragment_B(kk_thr_mma.partition_B(sK_SD_k))\n tKKrB_cv = kk_thr_copy_B.retile(tKKrB)\n tKKsB = kk_thr_copy_B.partition_S(sK_SD)\n\n # ── SK copies ─────────────────────────────────────────────────────────\n # SK B: K loaded from sK_SD (row-major BlkKV×D) with LDSM_N — matches C++ SK B-operand\n # SK C: V loaded from sV_DS (col-major D×BlkKV) with LDSM_T\n sk_tiled_copy_B = cute.make_tiled_copy_B(ldsm_n4, sk_tiled_mma)\n sk_tiled_copy_C = cute.make_tiled_copy_C(ldsm_t4, sk_tiled_mma)\n sk_thr_copy_B = sk_tiled_copy_B.get_slice(thread_idx)\n sk_thr_copy_C = sk_tiled_copy_C.get_slice(thread_idx)\n\n # Work around DSL make_fragment_B not accepting partition_shape_B output directly.\n tSKrK = cute.make_rmem_tensor(\n sk_thr_mma.partition_shape_B(cute.slice_(tile_shape_sk, (0, None, None))),\n self.dtype,\n )\n tSKrK_cv = sk_thr_copy_B.retile(tSKrK)\n tSKsK = sk_thr_copy_B.partition_S(sK_SD)\n\n # ── NewV copies ───────────────────────────────────────────────────────\n newv_tiled_copy_B = cute.make_tiled_copy_B(ldsm_n4, newv_tiled_mma)\n newv_thr_copy_B = newv_tiled_copy_B.get_slice(thread_idx)\n tNewVrB = newv_thr_mma.make_fragment_B(newv_thr_mma.partition_B(sKK_opd))\n tNewVrB_cv = newv_thr_copy_B.retile(tNewVrB)\n tNewVsB = newv_thr_copy_B.partition_S(sKK_opd)\n\n # ── KV copies ─────────────────────────────────────────────────────────\n kv_tiled_copy_B = cute.make_tiled_copy_B(ldsm_t4, kv_tiled_mma)\n kv_thr_copy_B = kv_tiled_copy_B.get_slice(thread_idx)\n tKVrK = kv_thr_mma.make_fragment_B(kv_thr_mma.partition_B(sK_DS_k))\n tKVrK_cv = kv_thr_copy_B.retile(tKVrK)\n tKVsK = kv_thr_copy_B.partition_S(sK_DS)\n\n # ── O1/O2 copies ──────────────────────────────────────────────────────\n o1_tiled_copy_B = cute.make_tiled_copy_B(ldsm_n4, o1_tiled_mma)\n o2_tiled_copy_B = cute.make_tiled_copy_B(ldsm_n4, o2_tiled_mma)\n o1_thr_copy_B = o1_tiled_copy_B.get_slice(thread_idx)\n o2_thr_copy_B = o2_tiled_copy_B.get_slice(thread_idx)\n\n # Direct partition_B(sQ_k) preserves the swizzled Q layout here and produces\n # a non-C++ B fragment shape; derive the fragment from TileShapeO1 instead.\n tOrQ = cute.make_rmem_tensor(\n o1_thr_mma.partition_shape_B(cute.slice_(tile_shape_o1, (0, None, None))),\n self.dtype,\n )\n tOrQ_cv = o1_thr_copy_B.retile(tOrQ)\n tOsQ = o1_thr_copy_B.partition_S(sQ_SD)\n tOrQK = o2_thr_mma.make_fragment_B(o2_thr_mma.partition_B(sQK))\n tOrQK_cv = o2_thr_copy_B.retile(tOrQK)\n tOsQK = o2_thr_copy_B.partition_S(sQK)\n\n # ── O store (R→S STSM) ────────────────────────────────────────────────\n o_stsm = cute.make_copy_atom(\n warp.StMatrix8x8x16bOp(transpose=True, num_matrices=4), self.dtype\n )\n o_tiled_copy_r2s = cute.make_tiled_copy_C(o_stsm, o1_tiled_mma)\n o_thr_copy_r2s = o_tiled_copy_r2s.get_slice(thread_idx)\n tOsO = o_thr_copy_r2s.partition_D(sO)\n\n # ── Coordinate tensors for masking / alpha/beta indexing ──────────────\n cMqk = cute.make_identity_tensor((blk_q, blk_kv))\n tQKcMqk = qk_thr_mma.partition_C(cMqk)\n cMkk = cMqk # same shape (BlkKV == BlkQ == 64)\n tKKcMkk = kk_thr_mma.partition_C(cMkk)\n cO = cute.make_identity_tensor((d, blk_q))\n tOcO = o1_thr_mma.partition_C(cO)\n cSK = cute.make_identity_tensor((d, blk_kv))\n tSKcSK = sk_thr_mma.partition_C(cSK)\n cV = cute.make_identity_tensor((d, blk_kv))\n tKVcV = kv_thr_mma.partition_A(cV)\n\n # ── KK GEMM (WG0 only) ────────────────────────────────────────────────\n k_pipeline.consumer_wait(k_consumer_state)\n if cutlass.const_expr(self.needs_alpha):\n alpha_pipeline.consumer_wait(alpha_consumer_state)\n cute.arch.fence_view_async_shared()\n if cutlass.const_expr(self.needs_beta):\n beta_pipeline.consumer_wait(beta_consumer_state)\n cute.arch.fence_view_async_shared()\n # Match the C++ reject-non-role-first shape; ptxas keeps BRA.U around\n # the role body instead of predicating the HMMA/LDSM/STSM sequence.\n if wg_idx != MathWarpGroupRole.KK:\n cute.arch.sync_warp()\n else:\n cute.copy(kk_tiled_copy_A, tKKsA[None, None, None, k_stage], tKKrA_cv)\n cute.copy(kk_tiled_copy_B, tKKsB[None, None, None, k_stage], tKKrB_cv)\n tKKrKK = cute.make_rmem_tensor(\n kk_thr_mma.partition_shape_C((blk_kv, blk_kv)), self.acc_dtype\n )\n tKKrKK.fill(self.acc_dtype(0.0))\n cute.gemm(kk_tiled_mma, tKKrKK, tKKrA, tKKrB, tKKrKK)\n self.kk_epi(tKKrKK, tKKcMkk, sAlpha, sBeta, alpha_stage, beta_stage)\n self.qk_or_kk_mask(tKKrKK, tKKcMkk, is_final_block, B)\n self._kk_store_and_inv(\n tKKrKK,\n kk_tiled_mma,\n kk_thread_idx,\n sKK_inv,\n sKK_opd,\n sBeta,\n beta_stage,\n tKKcMkk,\n )\n if cutlass.const_expr(self.needs_beta):\n beta_pipeline.consumer_release(beta_consumer_state)\n beta_consumer_state.advance()\n\n # ── QK GEMM (WG1 only) ────────────────────────────────────────────────\n q_pipeline.consumer_wait(q_consumer_state)\n if wg_idx != MathWarpGroupRole.QK:\n cute.arch.sync_warp()\n else:\n cute.copy(qk_tiled_copy_A, tQKsQ[None, None, None, q_stage], tQKrQ_cv)\n cute.copy(qk_tiled_copy_B, tQKsK[None, None, None, k_stage], tQKrK_cv)\n tQKrQK = cute.make_rmem_tensor(\n qk_thr_mma.partition_shape_C((blk_q, blk_kv)), self.acc_dtype\n )\n tQKrQK.fill(self.acc_dtype(0.0))\n cute.gemm(qk_tiled_mma, tQKrQK, tQKrQ, tQKrK, tQKrQK)\n self.qk_epi(tQKrQK, tQKcMqk, sAlpha, alpha_stage, scale)\n self.qk_or_kk_mask(tQKrQK, tQKcMqk, is_final_block, B)\n self.qk_store(tQKrQK, sQK, qk_tiled_mma, qk_thread_idx)\n\n # ── O1: KV_state @ Q (both WGs, skip on first block) ─────────────────\n tOrO = cute.make_rmem_tensor(\n o1_thr_mma.partition_shape_C((d, blk_q)), self.acc_dtype\n )\n tOrO.fill(self.acc_dtype(0.0))\n if cutlass.const_expr(not is_first_block):\n cute.copy(o1_tiled_copy_B, tOsQ[None, None, None, q_stage], tOrQ_cv)\n tOrKV = SM80.make_acc_into_op(tKVrKV, o1_tiled_mma, self.dtype)\n cute.gemm(o1_tiled_mma, tOrO, tOrKV, tOrQ, tOrO)\n self.o1_epi(tOrO, tOcO, sAlpha, alpha_stage, scale)\n q_pipeline.consumer_release(q_consumer_state)\n q_consumer_state.advance()\n\n # ── SK: KV_state @ K^T (result negated below via V - SK) ─────────────\n tSKrSK = cute.make_rmem_tensor(\n sk_thr_mma.partition_shape_C((d, blk_kv)), self.acc_dtype\n )\n tSKrSK.fill(self.acc_dtype(0.0))\n if cutlass.const_expr(not is_first_block):\n tSKrS = SM80.make_acc_into_op(tKVrKV, sk_tiled_mma, self.dtype)\n cute.copy(sk_tiled_copy_B, tSKsK[None, None, None, k_stage], tSKrK_cv)\n cute.gemm(sk_tiled_mma, tSKrSK, tSKrS, tSKrK, tSKrSK)\n\n # ── Load V from smem ──────────────────────────────────────────────────\n v_pipeline.consumer_wait(v_consumer_state)\n tSKrV = self.sk_load_v(tSKrSK, sV_DS, sk_tiled_copy_C, sk_thr_copy_C, v_stage)\n\n # sk_epi + V - SK (SK=0 on first block, so V - SK = V)\n if cutlass.const_expr(not is_first_block):\n self.sk_epi(tSKrSK, tSKcSK, sAlpha, alpha_stage)\n for i in cutlass.range_constexpr(cute.size(tSKrV)):\n tSKrV[i] = tSKrV[i] - self.dtype(tSKrSK[i])\n\n # ── NewV = (V - SK) @ T^T (ordered: WG0 first) ──────────────────────\n tNewVrA = SM80.make_acc_into_op(tSKrV, newv_tiled_mma, self.dtype)\n tNewVrC = cute.make_rmem_tensor(\n newv_thr_mma.partition_shape_C((d, blk_kv)), self.acc_dtype\n )\n self._math_order_wait(wg_idx)\n cute.copy(newv_tiled_copy_B, tNewVsB, tNewVrB_cv)\n tNewVrC.fill(self.acc_dtype(0.0))\n cute.gemm(newv_tiled_mma, tNewVrC, tNewVrA, tNewVrB, tNewVrC)\n self._math_order_notify(wg_idx)\n v_pipeline.consumer_release(v_consumer_state)\n v_consumer_state.advance()\n\n # ── O2 = O1 + NewV @ QK (ordered: WG0 first) ────────────────────────\n tOrNewV = SM80.make_acc_into_op(tNewVrC, o2_tiled_mma, self.dtype)\n self._math_order_wait(wg_idx)\n cute.copy(o2_tiled_copy_B, tOsQK, tOrQK_cv)\n cute.gemm(o2_tiled_mma, tOrO, tOrNewV, tOrQK, tOrO)\n self._math_order_notify(wg_idx)\n\n # ── O store to smem ───────────────────────────────────────────────────\n o_pipeline.producer_acquire(o_producer_state)\n self.o_store(\n tOrO,\n tOsO[None, None, None, o_stage],\n o_tiled_copy_r2s,\n o_thr_copy_r2s,\n )\n o_pipeline.producer_commit(o_producer_state)\n o_producer_state.advance()\n\n # ── KV state update ───────────────────────────────────────────────────\n block_coeff = cutlass.Float32(1.0)\n if cutlass.const_expr(self.needs_alpha):\n block_coeff = cutlass.Float32(\n sAlpha[B - cutlass.Int32(1), AlphaProcessor.CUMPROD, alpha_stage]\n )\n\n for i in cutlass.range(cute.size(tKVrKV), unroll_full=True):\n tKVrKV[i] = block_coeff * tKVrKV[i]\n\n self.kv_decay_v(tOrNewV, tKVcV, sAlpha, alpha_stage, is_final_block, B)\n\n # KV += NewV @ K\n cute.copy(kv_tiled_copy_B, tKVsK[None, None, None, k_stage], tKVrK_cv)\n cute.gemm(kv_tiled_mma, tKVrKV, tOrNewV, tKVrK, tKVrKV)\n k_pipeline.consumer_release(k_consumer_state)\n k_consumer_state.advance()\n if cutlass.const_expr(self.needs_alpha):\n alpha_pipeline.consumer_release(alpha_consumer_state)\n alpha_consumer_state.advance()\n return (\n q_consumer_state,\n k_consumer_state,\n v_consumer_state,\n o_producer_state,\n alpha_consumer_state,\n beta_consumer_state,\n )\n\n # ─── Warp role entry points ──────────────────────────────────────────────\n # The current DSL bridge still uses CTA-wide sync epochs, but each role owns\n # its own loop, matching the C++ warp-specialized dispatch shape.\n\n @cute.jit\n def run_load_qkv_role(\n self,\n sQ_SD: cute.Tensor,\n sK_DS: cute.Tensor,\n sV_DS: cute.Tensor,\n tma_atom_q: cute.CopyAtom,\n tma_tensor_q: cute.Tensor,\n tma_atom_k: cute.CopyAtom,\n tma_tensor_k: cute.Tensor,\n tma_atom_v: cute.CopyAtom,\n tma_tensor_v: cute.Tensor,\n q_pipeline,\n k_pipeline,\n v_pipeline,\n num_blocks: cutlass.Int32,\n tok_start,\n q_head_idx: cutlass.Int32,\n k_head_idx: cutlass.Int32,\n v_head_idx: cutlass.Int32,\n ):\n q_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.q_stage\n )\n k_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.k_stage\n )\n v_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.v_stage\n )\n for blk in cutlass.range(num_blocks, unroll=1):\n (\n q_producer_state,\n k_producer_state,\n v_producer_state,\n ) = self.load_qkv_tma(\n sQ_SD,\n sK_DS,\n sV_DS,\n tma_atom_q,\n tma_tensor_q,\n tma_atom_k,\n tma_tensor_k,\n tma_atom_v,\n tma_tensor_v,\n q_pipeline,\n q_producer_state,\n k_pipeline,\n k_producer_state,\n v_pipeline,\n v_producer_state,\n blk,\n tok_start,\n q_head_idx,\n k_head_idx,\n v_head_idx,\n )\n\n @cute.jit\n def run_load_alpha_role(\n self,\n sAlpha: cute.Tensor,\n g_alpha: cute.Tensor,\n alpha_pipeline,\n scale: cutlass.Float32,\n num_blocks: cutlass.Int32,\n tok_start,\n tok_end,\n sab_head_idx: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n ):\n alpha_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.alpha_beta_stage\n )\n for blk in cutlass.range(num_blocks, unroll=1):\n blk_tok = tok_start + blk * cutlass.Int32(self.BLK_Q)\n if cutlass.const_expr(self.needs_alpha):\n alpha_pipeline.producer_acquire(alpha_producer_state)\n cute.arch.fence_view_async_shared()\n self.load_alpha(\n sAlpha,\n g_alpha,\n blk_tok,\n tok_end,\n sab_head_idx,\n num_sab_heads,\n alpha_producer_state.index,\n )\n AlphaProcessor().run(\n sAlpha[None, None, alpha_producer_state.index], scale\n )\n cute.arch.fence_view_async_shared()\n alpha_pipeline.producer_commit(alpha_producer_state)\n alpha_producer_state.advance()\n\n @cute.jit\n def run_load_beta_role(\n self,\n sBeta: cute.Tensor,\n g_beta: cute.Tensor,\n beta_pipeline,\n num_blocks: cutlass.Int32,\n tok_start,\n tok_end,\n sab_head_idx: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n ):\n beta_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.alpha_beta_stage\n )\n for blk in cutlass.range(num_blocks, unroll=1):\n blk_tok = tok_start + blk * cutlass.Int32(self.BLK_KV)\n if cutlass.const_expr(self.needs_beta):\n beta_pipeline.producer_acquire(beta_producer_state)\n cute.arch.fence_view_async_shared()\n self.load_beta(\n sBeta,\n g_beta,\n blk_tok,\n tok_end,\n sab_head_idx,\n num_sab_heads,\n beta_producer_state.index,\n )\n cute.arch.fence_view_async_shared()\n beta_pipeline.producer_commit(beta_producer_state)\n beta_producer_state.advance()\n\n @cute.jit\n def run_math_role(\n self,\n sQ_SD: cute.Tensor,\n sK_SD: cute.Tensor,\n sK_DS: cute.Tensor,\n sV_DS: cute.Tensor,\n sQK: cute.Tensor,\n sKK_inv: cute.Tensor,\n sKK_opd: cute.Tensor,\n sO: cute.Tensor,\n sAlpha: cute.Tensor,\n sBeta: cute.Tensor,\n q_pipeline,\n k_pipeline,\n v_pipeline,\n o_pipeline,\n alpha_pipeline,\n beta_pipeline,\n g_state: cute.Tensor,\n g_init_state: cute.Tensor,\n g_state_indices: cute.Tensor,\n g_state_checkpoints: cute.Tensor,\n checkpoint_cu_starts: cute.Tensor,\n work_desc: WorkDesc,\n scale: cutlass.Float32,\n wg_idx: cutlass.Int32,\n math_tidx: cutlass.Int32,\n num_blocks: cutlass.Int32,\n num_q_heads: cutlass.Int32,\n num_v_heads: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n num_seqs: cutlass.Int32,\n total_checkpoints: cutlass.Int32,\n checkpoint_every_n_tokens: cutlass.Int32,\n ):\n self._math_order_init(wg_idx)\n q_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.q_stage\n )\n k_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.k_stage\n )\n v_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.v_stage\n )\n o_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.o_stage\n )\n alpha_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.alpha_beta_stage\n )\n beta_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.alpha_beta_stage\n )\n\n kv_tiled_mma = cute.make_tiled_mma(\n warp.MmaF16BF16Op(self.dtype, self.acc_dtype, (16, 8, 16)),\n cute.make_layout((8, 1, 1)),\n permutation_mnk=(self.D, self.D, self.BLK_KV),\n )\n kv_thr_mma = kv_tiled_mma.get_slice(math_tidx)\n tKVrKV = cute.make_rmem_tensor(\n kv_thr_mma.partition_shape_C((self.D, self.D)), self.acc_dtype\n )\n tKVrKV.fill(self.acc_dtype(0.0))\n\n packed_state_layout = cute.make_ordered_layout(\n (self.D, self.D, num_sab_heads, num_seqs), order=(0, 1, 2, 3)\n )\n state_ref_shape = (g_state.shape[0], g_state.shape[1], self.D, self.D)\n state_ref_layout = cute.make_layout(state_ref_shape, stride=g_state.stride)\n indexed_state_layout = cute.select(state_ref_layout, mode=[3, 2, 1, 0])\n state_idx = work_desc.seq_idx\n if cutlass.const_expr(self.use_state_indices):\n state_idx = cutlass.Int32(g_state_indices[work_desc.seq_idx])\n state_layout = indexed_state_layout\n else:\n state_layout = packed_state_layout\n o_head_idx = work_desc.o_head_idx(num_q_heads, num_v_heads)\n mState = cute.make_tensor(g_state.iterator, state_layout)\n gStateKV = mState[None, None, o_head_idx, state_idx]\n if cutlass.const_expr(self.needs_init_state):\n init_state_ref_layout = cute.make_layout(\n state_ref_shape, stride=g_init_state.stride\n )\n indexed_init_state_layout = cute.select(\n init_state_ref_layout, mode=[3, 2, 1, 0]\n )\n if cutlass.const_expr(self.use_state_indices):\n init_state_layout = indexed_init_state_layout\n else:\n init_state_layout = packed_state_layout\n mInitState = cute.make_tensor(g_init_state.iterator, init_state_layout)\n gInitKV = mInitState[None, None, o_head_idx, state_idx]\n self.kv_load(tKVrKV, gInitKV, kv_thr_mma)\n\n first_B = work_desc.seq_len\n if first_B > cutlass.Int32(self.BLK_KV):\n first_B = cutlass.Int32(self.BLK_KV)\n if cutlass.const_expr(self.needs_init_state):\n (\n q_consumer_state,\n k_consumer_state,\n v_consumer_state,\n o_producer_state,\n alpha_consumer_state,\n beta_consumer_state,\n ) = self.compute_loop_body(\n sQ_SD,\n sK_SD,\n sK_DS,\n sV_DS,\n sQK,\n sKK_inv,\n sKK_opd,\n sO,\n sAlpha,\n sBeta,\n kv_tiled_mma,\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n v_pipeline,\n v_consumer_state,\n o_pipeline,\n o_producer_state,\n alpha_pipeline,\n alpha_consumer_state,\n beta_pipeline,\n beta_consumer_state,\n False,\n True,\n first_B,\n tKVrKV,\n scale,\n wg_idx,\n )\n else:\n (\n q_consumer_state,\n k_consumer_state,\n v_consumer_state,\n o_producer_state,\n alpha_consumer_state,\n beta_consumer_state,\n ) = self.compute_loop_body(\n sQ_SD,\n sK_SD,\n sK_DS,\n sV_DS,\n sQK,\n sKK_inv,\n sKK_opd,\n sO,\n sAlpha,\n sBeta,\n kv_tiled_mma,\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n v_pipeline,\n v_consumer_state,\n o_pipeline,\n o_producer_state,\n alpha_pipeline,\n alpha_consumer_state,\n beta_pipeline,\n beta_consumer_state,\n True,\n True,\n first_B,\n tKVrKV,\n scale,\n wg_idx,\n )\n self.maybe_store_checkpoint(\n tKVrKV,\n g_state_checkpoints,\n checkpoint_cu_starts,\n checkpoint_every_n_tokens,\n kv_thr_mma,\n work_desc.seq_idx,\n o_head_idx,\n num_sab_heads,\n total_checkpoints,\n cutlass.Int32(self.BLK_KV),\n work_desc.seq_len,\n )\n\n for blk in cutlass.range(\n cutlass.Int32(1), num_blocks - cutlass.Int32(1), cutlass.Int32(1), unroll=1\n ):\n (\n q_consumer_state,\n k_consumer_state,\n v_consumer_state,\n o_producer_state,\n alpha_consumer_state,\n beta_consumer_state,\n ) = self.compute_loop_body(\n sQ_SD,\n sK_SD,\n sK_DS,\n sV_DS,\n sQK,\n sKK_inv,\n sKK_opd,\n sO,\n sAlpha,\n sBeta,\n kv_tiled_mma,\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n v_pipeline,\n v_consumer_state,\n o_pipeline,\n o_producer_state,\n alpha_pipeline,\n alpha_consumer_state,\n beta_pipeline,\n beta_consumer_state,\n False,\n False,\n cutlass.Int32(self.BLK_KV),\n tKVrKV,\n scale,\n wg_idx,\n )\n self.maybe_store_checkpoint(\n tKVrKV,\n g_state_checkpoints,\n checkpoint_cu_starts,\n checkpoint_every_n_tokens,\n kv_thr_mma,\n work_desc.seq_idx,\n o_head_idx,\n num_sab_heads,\n total_checkpoints,\n (blk + cutlass.Int32(1)) * cutlass.Int32(self.BLK_KV),\n work_desc.seq_len,\n )\n\n if num_blocks != cutlass.Int32(1):\n last_blk = num_blocks - cutlass.Int32(1)\n last_B = work_desc.seq_len - last_blk * cutlass.Int32(self.BLK_KV)\n (\n q_consumer_state,\n k_consumer_state,\n v_consumer_state,\n o_producer_state,\n alpha_consumer_state,\n beta_consumer_state,\n ) = self.compute_loop_body(\n sQ_SD,\n sK_SD,\n sK_DS,\n sV_DS,\n sQK,\n sKK_inv,\n sKK_opd,\n sO,\n sAlpha,\n sBeta,\n kv_tiled_mma,\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n v_pipeline,\n v_consumer_state,\n o_pipeline,\n o_producer_state,\n alpha_pipeline,\n alpha_consumer_state,\n beta_pipeline,\n beta_consumer_state,\n False,\n True,\n last_B,\n tKVrKV,\n scale,\n wg_idx,\n )\n self.maybe_store_checkpoint(\n tKVrKV,\n g_state_checkpoints,\n checkpoint_cu_starts,\n checkpoint_every_n_tokens,\n kv_thr_mma,\n work_desc.seq_idx,\n o_head_idx,\n num_sab_heads,\n total_checkpoints,\n (last_blk + cutlass.Int32(1)) * cutlass.Int32(self.BLK_KV),\n work_desc.seq_len,\n )\n self.kv_store(tKVrKV, gStateKV, kv_thr_mma)\n\n # ─── Kernel entry point ───────────────────────────────────────────────────\n\n @cute.jit\n def __call__(\n self,\n g_q: cute.Tensor,\n g_k: cute.Tensor,\n g_v: cute.Tensor,\n g_o: cute.Tensor,\n g_alpha: cute.Tensor,\n g_beta: cute.Tensor,\n g_state: cute.Tensor,\n g_init_state: cute.Tensor,\n g_state_indices: cute.Tensor,\n g_state_checkpoints: cute.Tensor,\n checkpoint_cu_starts: cute.Tensor,\n g_tensormaps: cute.Tensor,\n cu_seqlens: cute.Tensor,\n scale: cutlass.Float32,\n num_q_heads: cutlass.Int32,\n num_k_heads: cutlass.Int32,\n num_v_heads: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n num_seqs: cutlass.Int32,\n total_checkpoints: cutlass.Int32,\n checkpoint_every_n_tokens: cutlass.Int32,\n grid_x: int,\n stream,\n ):\n qkv_smem_layout_atom = warpgroup.make_smem_layout_atom(\n warpgroup.SmemLayoutAtomKind.K_SW128,\n self.dtype,\n )\n q_storage_layout = cute.coalesce(\n cute.tile_to_shape(\n qkv_smem_layout_atom,\n (self.BLK_Q, self.D, self.q_stage),\n order=(0, 1, 2),\n ),\n target_profile=(1, 1, 1),\n )\n q_smem_layout = cute.slice_(q_storage_layout, (None, None, 0))\n k_storage_layout_sd = cute.coalesce(\n cute.tile_to_shape(\n qkv_smem_layout_atom,\n (self.BLK_KV, self.D, self.k_stage),\n order=(0, 1, 2),\n ),\n target_profile=(1, 1, 1),\n )\n k_storage_layout_ds = cute.select(k_storage_layout_sd, [1, 0, 2])\n v_storage_layout_sd = cute.coalesce(\n cute.tile_to_shape(\n qkv_smem_layout_atom,\n (self.BLK_KV, self.D, self.v_stage),\n order=(0, 1, 2),\n ),\n target_profile=(1, 1, 1),\n )\n v_storage_layout_ds = cute.select(v_storage_layout_sd, [1, 0, 2])\n k_smem_layout = cute.slice_(k_storage_layout_ds, (None, None, 0))\n v_smem_layout = cute.slice_(v_storage_layout_ds, (None, None, 0))\n o_smem_layout_atom = warpgroup.make_smem_layout_atom(\n warpgroup.SmemLayoutAtomKind.MN_SW32,\n self.dtype,\n )\n o_storage_layout = cute.tile_to_shape(\n o_smem_layout_atom,\n (self.D, self.BLK_Q, self.o_stage),\n order=(1, 0, 2),\n )\n o_smem_layout = cute.slice_(o_storage_layout, (None, None, 0))\n\n tma_load_op = cpasync.CopyBulkTensorTileG2SOp()\n tma_atom_q, tma_tensor_q = cpasync.make_tiled_tma_atom(\n tma_load_op, g_q, q_smem_layout, (self.BLK_Q, self.D)\n )\n tma_atom_k, tma_tensor_k = cpasync.make_tiled_tma_atom(\n tma_load_op, g_k, k_smem_layout, (self.D, self.BLK_KV)\n )\n tma_atom_v, tma_tensor_v = cpasync.make_tiled_tma_atom(\n tma_load_op, g_v, v_smem_layout, (self.D, self.BLK_KV)\n )\n\n tma_store_op = cpasync.CopyBulkTensorTileS2GOp()\n tma_atom_o, tma_tensor_o = cpasync.make_tiled_tma_atom(\n tma_store_op, g_o, o_smem_layout, (self.D, self.BLK_Q)\n )\n\n dtype_bytes = self.dtype.width // 8\n self.tma_load_q_bytes = cute.size(q_smem_layout) * dtype_bytes\n self.tma_load_k_bytes = cute.size(k_smem_layout) * dtype_bytes\n self.tma_load_v_bytes = cute.size(v_smem_layout) * dtype_bytes\n\n qk_layout_atom = cute.make_layout((8, 8), stride=(8, 1))\n qk_storage_layout = cute.tile_to_shape(\n qk_layout_atom, (self.BLK_Q, self.BLK_KV), order=(1, 0)\n )\n kk_storage_layout = cute.tile_to_shape(\n qk_layout_atom, (self.BLK_KV, self.BLK_KV), order=(1, 0)\n )\n alpha_storage_layout = cute.make_layout(\n (self.BLK_Q, AlphaProcessor.NUM_CHANNELS, self.alpha_beta_stage)\n )\n beta_storage_layout = cute.make_layout((self.BLK_KV, self.alpha_beta_stage))\n\n @cute.struct\n class SharedStorage:\n q_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.q_stage * 2]\n k_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.k_stage * 2]\n v_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.v_stage * 2]\n o_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.o_stage * 2]\n alpha_mbar_ptr: cute.struct.MemRange[\n cutlass.Int64, self.alpha_beta_stage * 2\n ]\n beta_mbar_ptr: cute.struct.MemRange[\n cutlass.Int64, self.alpha_beta_stage * 2\n ]\n\n smem_q: cute.struct.Align[\n cute.struct.MemRange[self.dtype, cute.cosize(q_storage_layout)],\n 128,\n ]\n smem_k: cute.struct.Align[\n cute.struct.MemRange[self.dtype, cute.cosize(k_storage_layout_sd)],\n 128,\n ]\n smem_v: cute.struct.Align[\n cute.struct.MemRange[self.dtype, cute.cosize(v_storage_layout_sd)],\n 128,\n ]\n smem_qk: cute.struct.Align[\n cute.struct.MemRange[self.dtype, cute.cosize(qk_storage_layout)],\n 16,\n ]\n smem_kk: cute.struct.Align[\n cute.struct.MemRange[\n self.inverse_dtype, cute.cosize(kk_storage_layout)\n ],\n 16,\n ]\n smem_o: cute.struct.Align[\n cute.struct.MemRange[self.dtype, cute.cosize(o_storage_layout)],\n 128,\n ]\n smem_alpha: cute.struct.Align[\n cute.struct.MemRange[\n cutlass.Float32, cute.cosize(alpha_storage_layout)\n ],\n 16,\n ]\n smem_beta: cute.struct.Align[\n cute.struct.MemRange[cutlass.Float32, cute.cosize(beta_storage_layout)],\n 16,\n ]\n\n self.shared_storage = SharedStorage\n\n self.kernel(\n g_alpha,\n g_beta,\n tma_atom_q,\n tma_tensor_q,\n tma_atom_k,\n tma_tensor_k,\n tma_atom_v,\n tma_tensor_v,\n tma_atom_o,\n tma_tensor_o,\n g_state,\n g_init_state,\n g_state_indices,\n g_state_checkpoints,\n checkpoint_cu_starts,\n g_tensormaps,\n cu_seqlens,\n scale,\n num_q_heads,\n num_k_heads,\n num_v_heads,\n num_sab_heads,\n num_seqs,\n total_checkpoints,\n checkpoint_every_n_tokens,\n ).launch(\n grid=(grid_x, 1, 1),\n block=(384, 1, 1),\n max_number_threads=(384, 1, 1),\n stream=stream,\n min_blocks_per_mp=1,\n )\n\n @cute.kernel\n def kernel(\n self,\n g_alpha: cute.Tensor,\n g_beta: cute.Tensor,\n tma_atom_q: cute.CopyAtom,\n tma_tensor_q: cute.Tensor,\n tma_atom_k: cute.CopyAtom,\n tma_tensor_k: cute.Tensor,\n tma_atom_v: cute.CopyAtom,\n tma_tensor_v: cute.Tensor,\n tma_atom_o: cute.CopyAtom,\n tma_tensor_o: cute.Tensor,\n g_state: cute.Tensor,\n g_init_state: cute.Tensor,\n g_state_indices: cute.Tensor,\n g_state_checkpoints: cute.Tensor,\n checkpoint_cu_starts: cute.Tensor,\n g_tensormaps: cute.Tensor,\n cu_seqlens: cute.Tensor,\n scale: cutlass.Float32,\n num_q_heads: cutlass.Int32,\n num_k_heads: cutlass.Int32,\n num_v_heads: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n num_seqs: cutlass.Int32,\n total_checkpoints: cutlass.Int32,\n checkpoint_every_n_tokens: cutlass.Int32,\n ):\n NUM_LOAD_WARP_GROUPS = 1\n NUM_MMA_WARP_GROUPS = 2\n THREADS_PER_WARP_GROUP = 128\n WARPS_PER_WARP_GROUP = 4\n MIN_BLOCKS_PER_MP = 1\n MAX_THREADS_PER_BLOCK = (\n NUM_LOAD_WARP_GROUPS + NUM_MMA_WARP_GROUPS\n ) * THREADS_PER_WARP_GROUP\n load_registers, mma_registers = self.get_register_requirements(\n MAX_THREADS_PER_BLOCK,\n MIN_BLOCKS_PER_MP,\n NUM_MMA_WARP_GROUPS,\n THREADS_PER_WARP_GROUP,\n )\n\n tidx, _, _ = cute.arch.thread_idx()\n warp_idx = cute.arch.make_warp_uniform(cute.arch.warp_idx())\n warp_group_idx = cute.arch.make_warp_uniform(\n tidx // cutlass.Int32(THREADS_PER_WARP_GROUP)\n )\n ldst_warp_role = cute.arch.make_warp_uniform(\n warp_idx % cutlass.Int32(WARPS_PER_WARP_GROUP)\n )\n\n if warp_idx == LoadStoreWarpRole.LOAD_QKV:\n cpasync.prefetch_descriptor(tma_atom_q)\n cpasync.prefetch_descriptor(tma_atom_k)\n cpasync.prefetch_descriptor(tma_atom_v)\n cpasync.prefetch_descriptor(tma_atom_o)\n\n work_desc = self.get_next_work(\n cu_seqlens,\n num_q_heads,\n num_v_heads,\n num_sab_heads,\n )\n tok_end = work_desc.tok_offset + work_desc.seq_len\n num_blocks = (\n work_desc.seq_len + cutlass.Int32(self.BLK_KV) - cutlass.Int32(1)\n ) // cutlass.Int32(self.BLK_KV)\n\n # math_tidx / wg_idx: valid for Math WG threads; LdSt WG gets negative values (unused)\n math_tidx = tidx - cutlass.Int32(THREADS_PER_WARP_GROUP)\n wg_idx = math_tidx // cutlass.Int32(THREADS_PER_WARP_GROUP)\n\n # ── Smem allocation ───────────────────────────────────────────────────\n allocator = cutlass.utils.SmemAllocator()\n storage = allocator.allocate(self.shared_storage)\n\n qkv_smem_layout_atom = warpgroup.make_smem_layout_atom(\n warpgroup.SmemLayoutAtomKind.K_SW128,\n self.dtype,\n )\n q_layout_sd = cute.coalesce(\n cute.tile_to_shape(\n qkv_smem_layout_atom,\n (self.BLK_Q, self.D, self.q_stage),\n order=(0, 1, 2),\n ),\n target_profile=(1, 1, 1),\n )\n sQ_SD = storage.smem_q.get_tensor(q_layout_sd.outer, swizzle=q_layout_sd.inner)\n\n k_layout_sd = cute.coalesce(\n cute.tile_to_shape(\n qkv_smem_layout_atom,\n (self.BLK_KV, self.D, self.k_stage),\n order=(0, 1, 2),\n ),\n target_profile=(1, 1, 1),\n )\n k_layout_ds = cute.select(k_layout_sd, [1, 0, 2])\n sK_SD = storage.smem_k.get_tensor(k_layout_sd.outer, swizzle=k_layout_sd.inner)\n sK_DS = storage.smem_k.get_tensor(k_layout_ds.outer, swizzle=k_layout_ds.inner)\n\n v_layout_sd = cute.coalesce(\n cute.tile_to_shape(\n qkv_smem_layout_atom,\n (self.BLK_KV, self.D, self.v_stage),\n order=(0, 1, 2),\n ),\n target_profile=(1, 1, 1),\n )\n v_layout_ds = cute.select(v_layout_sd, [1, 0, 2])\n sV_DS = storage.smem_v.get_tensor(v_layout_ds.outer, swizzle=v_layout_ds.inner)\n\n qk_layout_atom = cute.make_layout((8, 8), stride=(8, 1))\n qk_layout = cute.tile_to_shape(\n qk_layout_atom, (self.BLK_Q, self.BLK_KV), order=(1, 0)\n )\n sQK = storage.smem_qk.get_tensor(qk_layout)\n\n kk_layout = cute.tile_to_shape(\n qk_layout_atom, (self.BLK_KV, self.BLK_KV), order=(1, 0)\n )\n sKK_inv = storage.smem_kk.get_tensor(kk_layout)\n kk_opd_ptr = cute.recast_ptr(storage.smem_kk.data_ptr(), dtype=self.dtype)\n sKK_opd = cute.make_tensor(kk_opd_ptr, kk_layout)\n\n o_smem_layout_atom = warpgroup.make_smem_layout_atom(\n warpgroup.SmemLayoutAtomKind.MN_SW32,\n self.dtype,\n )\n o_layout = cute.tile_to_shape(\n o_smem_layout_atom,\n (self.D, self.BLK_Q, self.o_stage),\n order=(1, 0, 2),\n )\n sO = storage.smem_o.get_tensor(o_layout.outer, swizzle=o_layout.inner)\n alpha_layout = cute.make_layout(\n (self.BLK_Q, AlphaProcessor.NUM_CHANNELS, self.alpha_beta_stage)\n )\n sAlpha = storage.smem_alpha.get_tensor(alpha_layout)\n\n beta_layout = cute.make_layout((self.BLK_KV, self.alpha_beta_stage))\n sBeta = storage.smem_beta.get_tensor(beta_layout)\n\n load_producer_group = pipeline.CooperativeGroup(pipeline.Agent.Thread, 1)\n load_consumer_group = pipeline.CooperativeGroup(pipeline.Agent.Thread, 8)\n vector_producer_group = pipeline.CooperativeGroup(pipeline.Agent.Thread, 32)\n vector_consumer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread, NUM_MMA_WARP_GROUPS * THREADS_PER_WARP_GROUP\n )\n o_producer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread, NUM_MMA_WARP_GROUPS * THREADS_PER_WARP_GROUP\n )\n o_consumer_group = pipeline.CooperativeGroup(pipeline.Agent.Thread, 32)\n q_pipeline = pipeline.PipelineTmaAsync.create(\n barrier_storage=storage.q_mbar_ptr.data_ptr(),\n num_stages=self.q_stage,\n producer_group=load_producer_group,\n consumer_group=load_consumer_group,\n tx_count=self.tma_load_q_bytes,\n cta_layout_vmnk=cute.make_layout((1, 1, 1, 1)),\n )\n k_pipeline = pipeline.PipelineTmaAsync.create(\n barrier_storage=storage.k_mbar_ptr.data_ptr(),\n num_stages=self.k_stage,\n producer_group=load_producer_group,\n consumer_group=load_consumer_group,\n tx_count=self.tma_load_k_bytes,\n cta_layout_vmnk=cute.make_layout((1, 1, 1, 1)),\n )\n v_pipeline = pipeline.PipelineTmaAsync.create(\n barrier_storage=storage.v_mbar_ptr.data_ptr(),\n num_stages=self.v_stage,\n producer_group=load_producer_group,\n consumer_group=load_consumer_group,\n tx_count=self.tma_load_v_bytes,\n cta_layout_vmnk=cute.make_layout((1, 1, 1, 1)),\n )\n o_pipeline = pipeline.PipelineAsync.create(\n barrier_storage=storage.o_mbar_ptr.data_ptr(),\n num_stages=self.o_stage,\n producer_group=o_producer_group,\n consumer_group=o_consumer_group,\n )\n alpha_pipeline = pipeline.PipelineAsync.create(\n barrier_storage=storage.alpha_mbar_ptr.data_ptr(),\n num_stages=self.alpha_beta_stage,\n producer_group=vector_producer_group,\n consumer_group=vector_consumer_group,\n )\n beta_pipeline = pipeline.PipelineAsync.create(\n barrier_storage=storage.beta_mbar_ptr.data_ptr(),\n num_stages=self.alpha_beta_stage,\n producer_group=vector_producer_group,\n consumer_group=vector_consumer_group,\n )\n cute.arch.mbarrier_init_fence()\n cute.arch.sync_threads()\n\n if (\n work_desc.seq_len != cutlass.Int32(0)\n and warp_group_idx == WarpGroupRole.LDST\n ):\n cute.arch.setmaxregister_decrease(load_registers)\n if ldst_warp_role == LoadStoreWarpRole.LOAD_QKV:\n self.run_load_qkv_role(\n sQ_SD,\n sK_DS,\n sV_DS,\n tma_atom_q,\n tma_tensor_q,\n tma_atom_k,\n tma_tensor_k,\n tma_atom_v,\n tma_tensor_v,\n q_pipeline,\n k_pipeline,\n v_pipeline,\n num_blocks,\n work_desc.tok_offset,\n work_desc.q_head_idx(),\n work_desc.k_head_idx(num_q_heads, num_v_heads),\n work_desc.v_head_idx(),\n )\n elif ldst_warp_role == LoadStoreWarpRole.STORE_O:\n CollectiveStoreTma(self.BLK_Q, self.D).run(\n sO,\n tma_atom_o,\n tma_tensor_o,\n g_tensormaps,\n o_pipeline,\n num_blocks,\n work_desc,\n num_seqs,\n self.o_stage,\n num_q_heads,\n num_v_heads,\n )\n elif ldst_warp_role == LoadStoreWarpRole.LOAD_BETA:\n self.run_load_beta_role(\n sBeta,\n g_beta,\n beta_pipeline,\n num_blocks,\n work_desc.tok_offset,\n tok_end,\n work_desc.o_head_idx(num_q_heads, num_v_heads),\n num_sab_heads,\n )\n elif ldst_warp_role == LoadStoreWarpRole.LOAD_ALPHA:\n self.run_load_alpha_role(\n sAlpha,\n g_alpha,\n alpha_pipeline,\n scale,\n num_blocks,\n work_desc.tok_offset,\n tok_end,\n work_desc.o_head_idx(num_q_heads, num_v_heads),\n num_sab_heads,\n )\n elif work_desc.seq_len != cutlass.Int32(0):\n cute.arch.setmaxregister_increase(mma_registers)\n\n self.run_math_role(\n sQ_SD,\n sK_SD,\n sK_DS,\n sV_DS,\n sQK,\n sKK_inv,\n sKK_opd,\n sO,\n sAlpha,\n sBeta,\n q_pipeline,\n k_pipeline,\n v_pipeline,\n o_pipeline,\n alpha_pipeline,\n beta_pipeline,\n g_state,\n g_init_state,\n g_state_indices,\n g_state_checkpoints,\n checkpoint_cu_starts,\n work_desc,\n scale,\n wg_idx,\n math_tidx,\n num_blocks,\n num_q_heads,\n num_v_heads,\n num_sab_heads,\n num_seqs,\n total_checkpoints,\n checkpoint_every_n_tokens,\n )\n\n\n# ─── Public API ──────────────────────────────────────────────────────────────\n\n\n@functools.cache\ndef _get_prefill_kernel(\n needs_alpha,\n needs_beta,\n needs_init_state,\n needs_checkpointing,\n kernel_dtype,\n initial_state_dtype,\n state_dtype,\n checkpoint_state_dtype,\n use_state_indices,\n cu_seqlens_dtype,\n state_indices_dtype,\n checkpoint_cu_starts_dtype,\n state_inner_strides,\n init_state_inner_strides,\n):\n return _FullyFusedDeltaRuleSm120(\n needs_alpha,\n needs_beta,\n needs_init_state,\n needs_checkpointing,\n kernel_dtype,\n initial_state_dtype=state_dtype_to_cutlass(initial_state_dtype),\n state_dtype=state_dtype_to_cutlass(state_dtype),\n checkpoint_state_dtype=state_dtype_to_cutlass(checkpoint_state_dtype),\n use_state_indices=use_state_indices,\n cu_seqlens_dtype=cu_seqlens_dtype,\n state_indices_dtype=state_indices_dtype,\n checkpoint_cu_starts_dtype=checkpoint_cu_starts_dtype,\n state_inner_strides=state_inner_strides,\n init_state_inner_strides=init_state_inner_strides,\n )\n\n\ndef delta_rule_prefill_dsl(\n o: torch.Tensor, # (total_seqlen, num_o_heads, D) fp16/bf16, output\n state: torch.Tensor, # (num_seqs, num_sab_heads, D, D) fp32, output\n q: torch.Tensor, # (total_seqlen, num_q_heads, D)\n k: torch.Tensor, # (total_seqlen, num_k_heads, D)\n v: torch.Tensor, # (total_seqlen, num_v_heads, D)\n init_state: torch.Tensor | None, # (num_seqs, num_sab_heads, D, D) fp32, optional\n alpha: torch.Tensor | None,\n beta: torch.Tensor | None,\n cu_seqlens: torch.Tensor, # (num_seqs+1,) int64\n scale: float,\n state_checkpoints: torch.Tensor | None = None,\n checkpoint_cu_starts: torch.Tensor | None = None,\n checkpoint_every_n_tokens: int = 0,\n state_indices: torch.Tensor | None = None,\n):\n import cuda.bindings.driver as cuda_driver\n\n device = q.device\n D = q.shape[-1]\n\n num_seqs = cu_seqlens.shape[0] - 1\n num_q_heads = q.shape[1]\n num_k_heads = k.shape[1]\n num_v_heads = v.shape[1]\n num_sab_heads = max(num_q_heads, num_v_heads)\n\n if not _FullyFusedDeltaRuleSm120.can_implement(\n num_q_heads, num_k_heads, num_v_heads, D, q.element_size()\n ):\n raise RuntimeError(\"can_implement failed\")\n if D != 128:\n raise RuntimeError(f\"DSL kernel only supports D=128, got {D}\")\n\n needs_alpha = alpha is not None\n needs_beta = beta is not None\n needs_init_state = init_state is not None\n needs_checkpointing = checkpoint_every_n_tokens > 0\n use_state_indices = state_indices is not None\n kernel_dtype = {\n torch.float16: cutlass.Float16,\n torch.bfloat16: cutlass.BFloat16,\n }.get(q.dtype)\n if kernel_dtype is None:\n raise RuntimeError(f\"DSL kernel only supports fp16/bf16 inputs, got {q.dtype}\")\n\n if k.dtype != q.dtype or v.dtype != q.dtype or o.dtype != q.dtype:\n raise RuntimeError(\n f\"q/k/v/o dtypes must match, got {q.dtype}, {k.dtype}, {v.dtype}, {o.dtype}\"\n )\n if alpha is not None and alpha.dtype != torch.float32:\n raise RuntimeError(f\"alpha must have dtype torch.float32, got {alpha.dtype}\")\n if beta is not None and beta.dtype != torch.float32:\n raise RuntimeError(f\"beta must have dtype torch.float32, got {beta.dtype}\")\n if init_state is not None:\n state_dtype_to_cutlass(init_state.dtype)\n state_dtype_to_cutlass(state.dtype)\n if state_checkpoints is not None:\n state_dtype_to_cutlass(state_checkpoints.dtype)\n if not is_integer_dtype(cu_seqlens.dtype):\n raise RuntimeError(\n f\"cu_seqlens must have an integer dtype, got {cu_seqlens.dtype}\"\n )\n\n expected_state_tail = (num_sab_heads, D, D)\n for name, tensor in ((\"state\", state), (\"init_state\", init_state)):\n if tensor is None:\n continue\n if (\n not use_state_indices and tensor.shape != (num_seqs, *expected_state_tail)\n ) or (use_state_indices and tuple(tensor.shape[1:]) != expected_state_tail):\n raise RuntimeError(\n f\"{name} must have shape \"\n f\"{('[N_pool]' if use_state_indices else f'[{num_seqs}]')} + {expected_state_tail}, \"\n f\"got {tuple(tensor.shape)}\"\n )\n if use_state_indices and (\n not is_integer_dtype(state_indices.dtype) or state_indices.shape != (num_seqs,)\n ):\n raise RuntimeError(\n f\"state_indices must have shape {(num_seqs,)} and an integer dtype\"\n )\n\n for name, tensor in (\n (\"q\", q),\n (\"k\", k),\n (\"v\", v),\n (\"o\", o),\n (\"cu_seqlens\", cu_seqlens),\n ):\n if not tensor.is_contiguous():\n raise RuntimeError(f\"{name} must be contiguous\")\n for name, tensor in (\n (\"alpha\", alpha),\n (\"beta\", beta),\n (\"state_indices\", state_indices),\n ):\n if tensor is not None and not tensor.is_contiguous():\n raise RuntimeError(f\"{name} must be contiguous\")\n for name, tensor in ((\"state\", state), (\"init_state\", init_state)):\n if tensor is None:\n continue\n if not use_state_indices and not tensor.is_contiguous():\n raise RuntimeError(f\"{name} must be contiguous\")\n\n total_seqlen = q.shape[0]\n num_o_heads = o.shape[1]\n q_tma = q.as_strided(\n (total_seqlen, D, num_q_heads),\n (num_q_heads * D, 1, D),\n )\n k_tma = k.as_strided(\n (D, total_seqlen, num_k_heads),\n (1, num_k_heads * D, D),\n )\n v_tma = v.as_strided(\n (D, total_seqlen, num_v_heads),\n (1, num_v_heads * D, D),\n )\n o_tma = o.as_strided(\n (D, total_seqlen, num_o_heads),\n (1, num_o_heads * D, D),\n )\n total_checkpoints = state_checkpoints.shape[0] if needs_checkpointing else 1\n\n workspace_size = get_device_sm_count(device) * 128\n tensormaps_t = _get_cache_buf(\"gdn_prefill_tensormaps\", workspace_size, device)\n stream = cuda_driver.CUstream(torch.cuda.current_stream(device).cuda_stream)\n\n delta_rule_kernel = _get_prefill_kernel(\n needs_alpha,\n needs_beta,\n needs_init_state,\n needs_checkpointing,\n kernel_dtype,\n initial_state_dtype=(init_state.dtype if needs_init_state else torch.float32),\n state_dtype=state.dtype,\n checkpoint_state_dtype=(\n state_checkpoints.dtype if needs_checkpointing else torch.float32\n ),\n use_state_indices=use_state_indices,\n cu_seqlens_dtype=cu_seqlens.dtype,\n state_indices_dtype=state_indices.dtype if use_state_indices else None,\n checkpoint_cu_starts_dtype=(\n checkpoint_cu_starts.dtype if needs_checkpointing else None\n ),\n state_inner_strides=(tuple(state.stride()[1:]) if use_state_indices else None),\n init_state_inner_strides=(\n tuple(init_state.stride()[1:])\n if use_state_indices and needs_init_state\n else None\n ),\n )\n\n compile_options = _sm120_compile_options(device)\n compiled_delta_rule_kernel = get_cached_compile(delta_rule_kernel, compile_options)\n if compiled_delta_rule_kernel is None:\n from_dlpack = lambda *args, **kwargs: cute.runtime.from_dlpack(\n *args, **{**kwargs, \"enable_tvm_ffi\": True}\n )\n kernel_args = (\n from_dlpack(q_tma, assumed_align=16).mark_layout_dynamic(leading_dim=1),\n from_dlpack(k_tma, assumed_align=16).mark_layout_dynamic(leading_dim=0),\n from_dlpack(v_tma, assumed_align=16).mark_layout_dynamic(leading_dim=0),\n from_dlpack(o_tma, assumed_align=16).mark_layout_dynamic(leading_dim=0),\n (\n from_dlpack(alpha.reshape(-1), assumed_align=16).mark_layout_dynamic()\n if needs_alpha\n else None\n ),\n (\n from_dlpack(beta.reshape(-1), assumed_align=16).mark_layout_dynamic()\n if needs_beta\n else None\n ),\n from_dlpack(state, assumed_align=16).mark_layout_dynamic(),\n (\n from_dlpack(init_state, assumed_align=16).mark_layout_dynamic()\n if needs_init_state\n else None\n ),\n (\n from_dlpack(state_indices, assumed_align=4).mark_layout_dynamic()\n if use_state_indices\n else None\n ),\n (\n from_dlpack(\n state_checkpoints.reshape(-1), assumed_align=16\n ).mark_layout_dynamic()\n if needs_checkpointing\n else None\n ),\n (\n from_dlpack(checkpoint_cu_starts, assumed_align=8).mark_layout_dynamic()\n if needs_checkpointing\n else None\n ),\n from_dlpack(tensormaps_t, assumed_align=128).mark_layout_dynamic(),\n from_dlpack(cu_seqlens, assumed_align=8).mark_layout_dynamic(),\n cutlass.Float32(scale),\n cutlass.Int32(num_q_heads),\n cutlass.Int32(num_k_heads),\n cutlass.Int32(num_v_heads),\n cutlass.Int32(num_sab_heads),\n cutlass.Int32(num_seqs),\n cutlass.Int32(total_checkpoints),\n cutlass.Int32(checkpoint_every_n_tokens),\n num_seqs * num_sab_heads,\n stream,\n )\n compiled_delta_rule_kernel = cached_compile(\n delta_rule_kernel,\n *kernel_args,\n compile_options=compile_options,\n )\n compiled_delta_rule_kernel(\n q_tma,\n k_tma,\n v_tma,\n o_tma,\n alpha.reshape(-1) if needs_alpha else None,\n beta.reshape(-1) if needs_beta else None,\n state,\n init_state if needs_init_state else None,\n state_indices if use_state_indices else None,\n state_checkpoints.reshape(-1) if needs_checkpointing else None,\n checkpoint_cu_starts if needs_checkpointing else None,\n tensormaps_t,\n cu_seqlens,\n scale,\n num_q_heads,\n num_k_heads,\n num_v_heads,\n num_sab_heads,\n num_seqs,\n total_checkpoints,\n checkpoint_every_n_tokens,\n num_seqs * num_sab_heads,\n stream,\n )\n"},"diff":{"kind":"string","value":"--- flashinfer/gdn_kernels/delta_rule_dsl/delta_rule_sm120.py\n+++ flashinfer/gdn_kernels/delta_rule_dsl/delta_rule_sm120.py\n@@ -1,3 +1,4 @@\n+import functools\n from enum import IntEnum\n \n import torch\n@@ -11,12 +12,18 @@\n from .custom_compile_cache import (\n KeyedCompileMixin,\n cached_compile,\n+ get_cached_compile,\n sm12x_compile_options,\n )\n from .collective_inverse_hmma import CollectiveInverse\n from .helpers import SM80, round_down, state_dtype_to_cutlass\n from .schedule import WorkDesc\n from .varlen_helper import is_integer_dtype\n+\n+\n+@functools.cache\n+def _sm120_compile_options(device):\n+ return (cute.EnableTVMFFI(True),) + sm12x_compile_options(device)\n \n \n # ─── Named-barrier IDs used by the compute kernel ────────────────────────────\n@@ -1995,6 +2002,41 @@\n # ─── Public API ──────────────────────────────────────────────────────────────\n \n \n+@functools.cache\n+def _get_prefill_kernel(\n+ needs_alpha,\n+ needs_beta,\n+ needs_init_state,\n+ needs_checkpointing,\n+ kernel_dtype,\n+ initial_state_dtype,\n+ state_dtype,\n+ checkpoint_state_dtype,\n+ use_state_indices,\n+ cu_seqlens_dtype,\n+ state_indices_dtype,\n+ checkpoint_cu_starts_dtype,\n+ state_inner_strides,\n+ init_state_inner_strides,\n+):\n+ return _FullyFusedDeltaRuleSm120(\n+ needs_alpha,\n+ needs_beta,\n+ needs_init_state,\n+ needs_checkpointing,\n+ kernel_dtype,\n+ initial_state_dtype=state_dtype_to_cutlass(initial_state_dtype),\n+ state_dtype=state_dtype_to_cutlass(state_dtype),\n+ checkpoint_state_dtype=state_dtype_to_cutlass(checkpoint_state_dtype),\n+ use_state_indices=use_state_indices,\n+ cu_seqlens_dtype=cu_seqlens_dtype,\n+ state_indices_dtype=state_indices_dtype,\n+ checkpoint_cu_starts_dtype=checkpoint_cu_starts_dtype,\n+ state_inner_strides=state_inner_strides,\n+ init_state_inner_strides=init_state_inner_strides,\n+ )\n+\n+\n def delta_rule_prefill_dsl(\n o: torch.Tensor, # (total_seqlen, num_o_heads, D) fp16/bf16, output\n state: torch.Tensor, # (num_seqs, num_sab_heads, D, D) fp32, output\n@@ -2011,9 +2053,9 @@\n checkpoint_every_n_tokens: int = 0,\n state_indices: torch.Tensor | None = None,\n ):\n- from cutlass.cute.runtime import from_dlpack\n import cuda.bindings.driver as cuda_driver\n \n+ device = q.device\n D = q.shape[-1]\n \n num_seqs = cu_seqlens.shape[0] - 1\n@@ -2120,70 +2162,19 @@\n )\n total_checkpoints = state_checkpoints.shape[0] if needs_checkpointing else 1\n \n- workspace_size = get_device_sm_count(q.device) * 128\n- tensormaps_t = _get_cache_buf(\"gdn_prefill_tensormaps\", workspace_size, q.device)\n-\n- stream_val = torch.cuda.current_stream().cuda_stream\n- stream = cuda_driver.CUstream(stream_val)\n-\n- enable_tvm_ffi = True\n- if enable_tvm_ffi:\n- from_dlpack = lambda *args, **kwargs: cute.runtime.from_dlpack(\n- *args, **{**kwargs, \"enable_tvm_ffi\": True}\n- )\n-\n- # Keep head counts and varlen extents runtime values across cached compiles.\n- q_cute = from_dlpack(q_tma, assumed_align=16).mark_layout_dynamic(leading_dim=1)\n- k_cute = from_dlpack(k_tma, assumed_align=16).mark_layout_dynamic(leading_dim=0)\n- v_cute = from_dlpack(v_tma, assumed_align=16).mark_layout_dynamic(leading_dim=0)\n- o_cute = from_dlpack(o_tma, assumed_align=16).mark_layout_dynamic(leading_dim=0)\n- alpha_cute = (\n- from_dlpack(alpha.reshape(-1), assumed_align=16).mark_layout_dynamic()\n- if needs_alpha\n- else None\n- )\n- beta_cute = (\n- from_dlpack(beta.reshape(-1), assumed_align=16).mark_layout_dynamic()\n- if needs_beta\n- else None\n- )\n- state_cute = from_dlpack(state, assumed_align=16).mark_layout_dynamic()\n- init_state_cute = (\n- from_dlpack(init_state, assumed_align=16).mark_layout_dynamic()\n- if needs_init_state\n- else None\n- )\n- state_indices_cute = (\n- from_dlpack(state_indices, assumed_align=4).mark_layout_dynamic()\n- if use_state_indices\n- else None\n- )\n- state_checkpoints_cute = (\n- from_dlpack(\n- state_checkpoints.reshape(-1), assumed_align=16\n- ).mark_layout_dynamic()\n- if needs_checkpointing\n- else None\n- )\n- checkpoint_cu_cute = (\n- from_dlpack(checkpoint_cu_starts, assumed_align=8).mark_layout_dynamic()\n- if needs_checkpointing\n- else None\n- )\n- tensormaps_cute = from_dlpack(tensormaps_t, assumed_align=128).mark_layout_dynamic()\n- cu_cute = from_dlpack(cu_seqlens, assumed_align=8).mark_layout_dynamic()\n-\n- delta_rule_kernel = _FullyFusedDeltaRuleSm120(\n+ workspace_size = get_device_sm_count(device) * 128\n+ tensormaps_t = _get_cache_buf(\"gdn_prefill_tensormaps\", workspace_size, device)\n+ stream = cuda_driver.CUstream(torch.cuda.current_stream(device).cuda_stream)\n+\n+ delta_rule_kernel = _get_prefill_kernel(\n needs_alpha,\n needs_beta,\n needs_init_state,\n needs_checkpointing,\n kernel_dtype,\n- initial_state_dtype=state_dtype_to_cutlass(\n- init_state.dtype if needs_init_state else torch.float32\n- ),\n- state_dtype=state_dtype_to_cutlass(state.dtype),\n- checkpoint_state_dtype=state_dtype_to_cutlass(\n+ initial_state_dtype=(init_state.dtype if needs_init_state else torch.float32),\n+ state_dtype=state.dtype,\n+ checkpoint_state_dtype=(\n state_checkpoints.dtype if needs_checkpointing else torch.float32\n ),\n use_state_indices=use_state_indices,\n@@ -2200,34 +2191,90 @@\n ),\n )\n \n- kernel_args = (\n- q_cute,\n- k_cute,\n- v_cute,\n- o_cute,\n- alpha_cute,\n- beta_cute,\n- state_cute,\n- init_state_cute,\n- state_indices_cute,\n- state_checkpoints_cute,\n- checkpoint_cu_cute,\n- tensormaps_cute,\n- cu_cute,\n- cutlass.Float32(scale),\n- cutlass.Int32(num_q_heads),\n- cutlass.Int32(num_k_heads),\n- cutlass.Int32(num_v_heads),\n- cutlass.Int32(num_sab_heads),\n- cutlass.Int32(num_seqs),\n- cutlass.Int32(total_checkpoints),\n- cutlass.Int32(checkpoint_every_n_tokens),\n+ compile_options = _sm120_compile_options(device)\n+ compiled_delta_rule_kernel = get_cached_compile(delta_rule_kernel, compile_options)\n+ if compiled_delta_rule_kernel is None:\n+ from_dlpack = lambda *args, **kwargs: cute.runtime.from_dlpack(\n+ *args, **{**kwargs, \"enable_tvm_ffi\": True}\n+ )\n+ kernel_args = (\n+ from_dlpack(q_tma, assumed_align=16).mark_layout_dynamic(leading_dim=1),\n+ from_dlpack(k_tma, assumed_align=16).mark_layout_dynamic(leading_dim=0),\n+ from_dlpack(v_tma, assumed_align=16).mark_layout_dynamic(leading_dim=0),\n+ from_dlpack(o_tma, assumed_align=16).mark_layout_dynamic(leading_dim=0),\n+ (\n+ from_dlpack(alpha.reshape(-1), assumed_align=16).mark_layout_dynamic()\n+ if needs_alpha\n+ else None\n+ ),\n+ (\n+ from_dlpack(beta.reshape(-1), assumed_align=16).mark_layout_dynamic()\n+ if needs_beta\n+ else None\n+ ),\n+ from_dlpack(state, assumed_align=16).mark_layout_dynamic(),\n+ (\n+ from_dlpack(init_state, assumed_align=16).mark_layout_dynamic()\n+ if needs_init_state\n+ else None\n+ ),\n+ (\n+ from_dlpack(state_indices, assumed_align=4).mark_layout_dynamic()\n+ if use_state_indices\n+ else None\n+ ),\n+ (\n+ from_dlpack(\n+ state_checkpoints.reshape(-1), assumed_align=16\n+ ).mark_layout_dynamic()\n+ if needs_checkpointing\n+ else None\n+ ),\n+ (\n+ from_dlpack(checkpoint_cu_starts, assumed_align=8).mark_layout_dynamic()\n+ if needs_checkpointing\n+ else None\n+ ),\n+ from_dlpack(tensormaps_t, assumed_align=128).mark_layout_dynamic(),\n+ from_dlpack(cu_seqlens, assumed_align=8).mark_layout_dynamic(),\n+ cutlass.Float32(scale),\n+ cutlass.Int32(num_q_heads),\n+ cutlass.Int32(num_k_heads),\n+ cutlass.Int32(num_v_heads),\n+ cutlass.Int32(num_sab_heads),\n+ cutlass.Int32(num_seqs),\n+ cutlass.Int32(total_checkpoints),\n+ cutlass.Int32(checkpoint_every_n_tokens),\n+ num_seqs * num_sab_heads,\n+ stream,\n+ )\n+ compiled_delta_rule_kernel = cached_compile(\n+ delta_rule_kernel,\n+ *kernel_args,\n+ compile_options=compile_options,\n+ )\n+ compiled_delta_rule_kernel(\n+ q_tma,\n+ k_tma,\n+ v_tma,\n+ o_tma,\n+ alpha.reshape(-1) if needs_alpha else None,\n+ beta.reshape(-1) if needs_beta else None,\n+ state,\n+ init_state if needs_init_state else None,\n+ state_indices if use_state_indices else None,\n+ state_checkpoints.reshape(-1) if needs_checkpointing else None,\n+ checkpoint_cu_starts if needs_checkpointing else None,\n+ tensormaps_t,\n+ cu_seqlens,\n+ scale,\n+ num_q_heads,\n+ num_k_heads,\n+ num_v_heads,\n+ num_sab_heads,\n+ num_seqs,\n+ total_checkpoints,\n+ checkpoint_every_n_tokens,\n num_seqs * num_sab_heads,\n stream,\n )\n- compiled_delta_rule_kernel = cached_compile(\n- delta_rule_kernel,\n- *kernel_args,\n- compile_options=sm12x_compile_options(q.device),\n- )\n- compiled_delta_rule_kernel(*kernel_args)"},"lines_added":{"kind":"number","value":135,"string":"135"},"lines_removed":{"kind":"number","value":88,"string":"88"},"files_in_commit":{"kind":"number","value":2,"string":"2"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["SM120","SM90"],"string":"[\n \"SM120\",\n \"SM90\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cute_dsl kernel file from flashinfer (flashinfer/gdn_kernels/delta_rule_dsl/delta_rule_sm120.py).\n\nGoal: perf(gdn): reduce non-CP CuTeDSL launch overhead\nTarget hardware: SM120, SM90\nTarget models: unspecified\n\nCurrent file:\n```python\nfrom enum import IntEnum\n\nimport torch\nimport cutlass\nimport cutlass.cute as cute\nimport cutlass.pipeline as pipeline\nfrom cutlass.cute.nvgpu import warp, warpgroup, cpasync\nfrom ...utils import get_device_sm_count, _get_cache_buf\nfrom .alpha import AlphaProcessor\nfrom .collective_store_tma import CollectiveStoreTma\nfrom .custom_compile_cache import (\n KeyedCompileMixin,\n cached_compile,\n sm12x_compile_options,\n)\nfrom .collective_inverse_hmma import CollectiveInverse\nfrom .helpers import SM80, round_down, state_dtype_to_cutlass\nfrom .schedule import WorkDesc\nfrom .varlen_helper import is_integer_dtype\n\n\n# ─── Named-barrier IDs used by the compute kernel ────────────────────────────\n# Must not conflict with each other or with pipeline barrier storage.\n\n\nclass NamedBarrier(IntEnum):\n MATH_WG0 = 4 # OrderedMathBarriers: StreamkBarrier0\n MATH_WG1 = 5 # OrderedMathBarriers: StreamkBarrier1\n KK_SYNC = 13 # sync all 128 WG0 threads before collective_inverse\n\n\nclass WarpGroupRole(IntEnum):\n LDST = 0\n MATH_KK = 1\n MATH_QK = 2\n\n\nclass LoadStoreWarpRole(IntEnum):\n LOAD_QKV = 0\n STORE_O = 1\n LOAD_BETA = 2\n LOAD_ALPHA = 3\n\n\nclass MathWarpGroupRole(IntEnum):\n KK = 0\n QK = 1\n\n\n# ─── Warp-specialized delta-rule kernel ───────────────────────────────────────\n# Grid: (num_seqs * num_sab_heads, 1, 1)\n# Block: 384 threads → WG0=[0,127], WG1=[128,255], WG2=[256,383]\n#\n# needs_alpha / needs_beta / needs_init_state are class attributes set in __init__.\n# The JIT compiler specialises per instance, so they are compile-time booleans\n# inside the kernel without any parameter-passing trickery.\n\n\nclass _FullyFusedDeltaRuleSm120(KeyedCompileMixin):\n @staticmethod\n def get_register_requirements(\n max_threads_per_block: int,\n min_blocks_per_multiprocessor: int,\n num_mma_warp_groups: int,\n threads_per_warp_group: int,\n ) -> tuple[int, int]:\n reg_alloc_granularity = 8\n load_registers = 40 - 2 * reg_alloc_granularity\n total_registers = (\n round_down(\n 64 * 1024 // min_blocks_per_multiprocessor,\n max_threads_per_block * reg_alloc_granularity,\n )\n // threads_per_warp_group\n )\n mma_registers = round_down(\n (total_registers - load_registers) // num_mma_warp_groups,\n reg_alloc_granularity,\n )\n return min(248, load_registers), min(248, mma_registers)\n\n @staticmethod\n def can_implement(\n num_q_heads: int,\n num_k_heads: int,\n num_v_heads: int,\n head_size: int,\n element_size: int,\n ) -> bool:\n ratio = (\n num_q_heads // num_v_heads\n if num_q_heads > num_v_heads\n else num_v_heads // num_q_heads\n )\n is_gva_enabled = num_v_heads > num_q_heads\n\n is_gqa_like = (\n (num_k_heads == num_v_heads)\n and (num_q_heads == ratio * num_k_heads)\n and (num_q_heads == ratio * num_v_heads)\n )\n is_gva_like = (\n (num_q_heads == num_k_heads)\n and (num_v_heads == ratio * num_q_heads)\n and (num_v_heads == ratio * num_k_heads)\n )\n\n alignment = 16 // element_size\n return (\n ((not is_gva_enabled and is_gqa_like) or (is_gva_enabled and is_gva_like))\n and (head_size <= 128)\n and ((head_size % alignment) == 0)\n )\n\n def __init__(\n self,\n needs_alpha: bool,\n needs_beta: bool,\n needs_init_state: bool,\n needs_checkpointing: bool,\n dtype: type[cutlass.Numeric] = cutlass.Float16,\n acc_dtype: type[cutlass.Numeric] = cutlass.Float32,\n initial_state_dtype: type[cutlass.Numeric] = cutlass.Float32,\n state_dtype: type[cutlass.Numeric] = cutlass.Float32,\n checkpoint_state_dtype: type[cutlass.Numeric] = cutlass.Float32,\n use_state_indices: bool = False,\n cu_seqlens_dtype: torch.dtype = torch.int64,\n state_indices_dtype: torch.dtype | None = None,\n checkpoint_cu_starts_dtype: torch.dtype | None = None,\n state_inner_strides: tuple[int, ...] | None = None,\n init_state_inner_strides: tuple[int, ...] | None = None,\n ):\n self.needs_alpha = needs_alpha\n self.needs_beta = needs_beta\n self.needs_init_state = needs_init_state\n self.needs_checkpointing = needs_checkpointing\n self.dtype = dtype\n self.acc_dtype = acc_dtype\n self.initial_state_dtype = initial_state_dtype\n self.state_dtype = state_dtype\n self.checkpoint_state_dtype = checkpoint_state_dtype\n self.use_state_indices = use_state_indices\n self.cu_seqlens_dtype = cu_seqlens_dtype\n self.state_indices_dtype = state_indices_dtype\n self.checkpoint_cu_starts_dtype = checkpoint_cu_starts_dtype\n self.state_inner_strides = state_inner_strides\n self.init_state_inner_strides = init_state_inner_strides\n self.inverse_dtype = cutlass.Float16\n self.BLK_Q = 64\n self.BLK_KV = 64\n self.D = 128\n self.q_stage = 1\n self.k_stage = 2\n self.v_stage = 1\n self.o_stage = 1\n self.alpha_beta_stage = 2\n self.manual_cache_key(\n \"needs_alpha\",\n \"needs_beta\",\n \"needs_init_state\",\n \"needs_checkpointing\",\n \"dtype\",\n \"acc_dtype\",\n \"initial_state_dtype\",\n \"state_dtype\",\n \"checkpoint_state_dtype\",\n \"use_state_indices\",\n \"cu_seqlens_dtype\",\n \"state_indices_dtype\",\n \"checkpoint_cu_starts_dtype\",\n \"state_inner_strides\",\n \"init_state_inner_strides\",\n \"inverse_dtype\",\n \"BLK_Q\",\n \"BLK_KV\",\n \"D\",\n \"q_stage\",\n \"k_stage\",\n \"v_stage\",\n \"o_stage\",\n \"alpha_beta_stage\",\n )\n\n def get_next_work(\n self,\n cu_seqlens: cute.Tensor,\n num_q_heads: cutlass.Int32,\n num_v_heads: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n ) -> WorkDesc:\n bx, _, _ = cute.arch.block_idx()\n seq_idx = bx // num_sab_heads\n o_head_idx = bx % num_sab_heads\n q_head_idx = o_head_idx * num_q_heads // num_sab_heads\n v_head_idx = o_head_idx * num_v_heads // num_sab_heads\n tok_start = cu_seqlens[seq_idx]\n seq_len = cutlass.Int32(cu_seqlens[seq_idx + 1] - tok_start)\n\n return WorkDesc(\n seq_idx=seq_idx,\n private_q_head_idx=q_head_idx,\n private_v_head_idx=v_head_idx,\n tok_offset=tok_start,\n seq_len=seq_len,\n tile_idx=cutlass.Int32(0),\n )\n\n # ─── Ordered 2-WG math barriers ───────────────────────────────────────────\n # Translates flat::OrderedNamedBarriers<UseReservedNB, NB0, NB1>.\n # wg_idx: MathWarpGroupRole.KK or MathWarpGroupRole.QK.\n\n @cute.jit\n def _math_order_init(self, wg_idx: cutlass.Int32):\n \"\"\"Pre-arrive at WG0's barrier so WG0 is unblocked on the first wait.\"\"\"\n if wg_idx == MathWarpGroupRole.QK:\n cute.arch.barrier_arrive(\n barrier_id=NamedBarrier.MATH_WG0, number_of_threads=256\n )\n\n @cute.jit\n def _math_order_wait(self, wg_idx: cutlass.Int32):\n \"\"\"Arrive+wait on this WG's own ordered barrier.\"\"\"\n if wg_idx == MathWarpGroupRole.KK:\n cute.arch.barrier(barrier_id=NamedBarrier.MATH_WG0, number_of_threads=256)\n else:\n cute.arch.barrier(barrier_id=NamedBarrier.MATH_WG1, number_of_threads=256)\n\n @cute.jit\n def _math_order_notify(self, wg_idx: cutlass.Int32):\n \"\"\"Arrive at the other WG's barrier to unblock it.\"\"\"\n if wg_idx == MathWarpGroupRole.KK:\n cute.arch.barrier_arrive(\n barrier_id=NamedBarrier.MATH_WG1, number_of_threads=256\n )\n else:\n cute.arch.barrier_arrive(\n barrier_id=NamedBarrier.MATH_WG0, number_of_threads=256\n )\n\n # ─── kk_store_and_inv ─────────────────────────────────────────────────────\n\n @cute.jit\n def _kk_store_and_inv(\n self,\n tKKrKK: cute.Tensor, # fp32 KK accumulator (from 128-thread kk_tiled_mma)\n kk_tiled_mma,\n kk_thread_idx: cutlass.Int32,\n sKK_inv: cute.Tensor, # (BlkKV, BlkKV)\n sKK_opd: cute.Tensor, # sKK_inv storage recast as Element for MMA operand\n sBeta: cute.Tensor, # (BlkKV, StagesBeta) - used when needs_beta\n beta_pipe_idx: cutlass.Int32,\n tKKcMkk: cute.Tensor, # coordinate mapping for KK fragment\n ):\n \"\"\"Store tKKrKK → sKK_inv, Inverse, optionally reload+beta.\"\"\"\n stsm_atom = cute.make_copy_atom(\n warp.StMatrix8x8x16bOp(transpose=False, num_matrices=4), self.inverse_dtype\n )\n tiled_store = cute.make_tiled_copy_C(stsm_atom, kk_tiled_mma)\n thr_store = tiled_store.get_slice(kk_thread_idx)\n tKKsKK = thr_store.partition_D(sKK_inv)\n tKKrKK_inv = cute.make_fragment_like(tKKrKK, self.inverse_dtype)\n tKKrKK_cv = thr_store.retile(tKKrKK_inv)\n for i in cutlass.range_constexpr(cute.size(tKKrKK)):\n tKKrKK_inv[i] = self.inverse_dtype(tKKrKK[i])\n cute.copy(tiled_store, tKKrKK_cv, tKKsKK)\n\n cute.arch.barrier(barrier_id=NamedBarrier.KK_SYNC, number_of_threads=128)\n CollectiveInverse().run(sKK_inv, NamedBarrier.KK_SYNC)\n\n if cutlass.const_expr(self.needs_beta or self.dtype != self.inverse_dtype):\n cute.arch.barrier(barrier_id=NamedBarrier.KK_SYNC, number_of_threads=128)\n ldsm_atom = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(transpose=False, num_matrices=4),\n self.inverse_dtype,\n )\n tiled_load = cute.make_tiled_copy_C(ldsm_atom, kk_tiled_mma)\n thr_load = tiled_load.get_slice(kk_thread_idx)\n tKKrKK_cpy = cute.make_fragment_like(tKKrKK_inv)\n tKKrKK_cvt = cute.make_fragment_like(tKKrKK_inv, self.dtype)\n tKKrKK_cv2 = thr_load.retile(tKKrKK_cpy)\n cute.copy(tiled_load, thr_load.partition_S(sKK_inv), tKKrKK_cv2)\n tKKcMkk_cv = thr_load.retile(tKKcMkk)\n\n for i in cutlass.range_constexpr(cute.size(tKKrKK_cpy)):\n if cutlass.const_expr(self.needs_beta):\n _, t = tKKcMkk_cv[i]\n tKKrKK_cvt[i] = self.dtype(\n cutlass.Float32(tKKrKK_cpy[i])\n * cutlass.Float32(sBeta[t, beta_pipe_idx])\n )\n else:\n tKKrKK_cvt[i] = self.dtype(tKKrKK_cpy[i])\n\n tKKsKK2 = thr_store.partition_D(sKK_opd)\n tKKrKK_cv3 = thr_store.retile(tKKrKK_cvt)\n cute.copy(tiled_store, tKKrKK_cv3, tKKsKK2)\n\n # ─── kk_epi ───────────────────────────────────────────────────────────────\n\n @cute.jit\n def kk_epi(\n self,\n tKKrKK: cute.Tensor,\n tKKcMkk: cute.Tensor,\n sAlpha: cute.Tensor,\n sBeta: cute.Tensor,\n alpha_stage: cutlass.Int32,\n beta_stage: cutlass.Int32,\n ):\n if cutlass.const_expr(self.needs_alpha):\n alpha_cumlog = sAlpha[None, AlphaProcessor.CUMSUM_LOG, alpha_stage]\n for i in cutlass.range_constexpr(cute.size(tKKrKK)):\n s, t = tKKcMkk[i]\n tKKrKK[i] = tKKrKK[i] * cute.math.exp2(\n cutlass.Float32(alpha_cumlog[s]) - cutlass.Float32(alpha_cumlog[t]),\n fastmath=True,\n )\n if cutlass.const_expr(self.needs_beta):\n beta_row = sBeta[None, beta_stage]\n for i in cutlass.range_constexpr(cute.size(tKKrKK)):\n s, _ = tKKcMkk[i]\n tKKrKK[i] = tKKrKK[i] * cutlass.Float32(beta_row[s])\n\n # ─── qk_or_kk_mask ────────────────────────────────────────────────────────\n\n @cute.jit\n def qk_or_kk_mask(\n self,\n frag: cute.Tensor,\n coord_tensor: cute.Tensor,\n is_final_block: bool,\n B: cutlass.Int32,\n ):\n for i in cutlass.range_constexpr(cute.size(frag)):\n s, t = coord_tensor[i]\n pred = s >= t\n if cutlass.const_expr(is_final_block):\n pred = pred and (s < B and t < B)\n if not pred:\n frag[i] = cutlass.Float32(0.0)\n\n # ─── qk_epi ───────────────────────────────────────────────────────────────\n\n @cute.jit\n def qk_epi(\n self,\n tQKrQK: cute.Tensor,\n tQKcMqk: cute.Tensor,\n sAlpha: cute.Tensor,\n alpha_stage: cutlass.Int32,\n scale: cutlass.Float32,\n ):\n if cutlass.const_expr(self.needs_alpha):\n alpha_cumlog = sAlpha[None, AlphaProcessor.CUMSUM_LOG, alpha_stage]\n for i in cutlass.range_constexpr(cute.size(tQKrQK)):\n s, t = tQKcMqk[i]\n tQKrQK[i] = (\n tQKrQK[i]\n * cute.math.exp2(\n cutlass.Float32(alpha_cumlog[s])\n - cutlass.Float32(alpha_cumlog[t]),\n fastmath=True,\n )\n * scale\n )\n else:\n for i in cutlass.range_constexpr(cute.size(tQKrQK)):\n tQKrQK[i] = tQKrQK[i] * scale\n\n # ─── qk_store ─────────────────────────────────────────────────────────────\n\n @cute.jit\n def qk_store(\n self,\n tQKrQK: cute.Tensor,\n sQK: cute.Tensor,\n qk_tiled_mma,\n qk_thread_idx: cutlass.Int32,\n ):\n stsm_atom = cute.make_copy_atom(\n warp.StMatrix8x8x16bOp(transpose=False, num_matrices=4), self.dtype\n )\n qk_tiled_copy = cute.make_tiled_copy_C(stsm_atom, qk_tiled_mma)\n qk_thr_copy = qk_tiled_copy.get_slice(qk_thread_idx)\n tQKsQK = qk_thr_copy.partition_D(sQK)\n tQKrQK_cvt = cute.make_fragment_like(tQKrQK, self.dtype)\n tQKrQK_cvt_cv = qk_thr_copy.retile(tQKrQK_cvt)\n for i in cutlass.range_constexpr(cute.size(tQKrQK)):\n tQKrQK_cvt[i] = self.dtype(tQKrQK[i])\n cute.copy(qk_tiled_copy, tQKrQK_cvt_cv, tQKsQK)\n\n # ─── o1_epi ───────────────────────────────────────────────────────────────\n\n @cute.jit\n def o1_epi(\n self,\n tOrO: cute.Tensor,\n tOcO: cute.Tensor,\n sAlpha: cute.Tensor,\n alpha_stage: cutlass.Int32,\n scale: cutlass.Float32,\n ):\n if cutlass.const_expr(self.needs_alpha):\n alpha_cpscale = sAlpha[None, AlphaProcessor.CUMPROD_SCALE, alpha_stage]\n for i in cutlass.range_constexpr(cute.size(tOrO)):\n _, tok_q = tOcO[i]\n tOrO[i] = cutlass.Float32(alpha_cpscale[tok_q]) * tOrO[i]\n else:\n for i in cutlass.range_constexpr(cute.size(tOrO)):\n tOrO[i] = scale * tOrO[i]\n\n # ─── sk_epi ───────────────────────────────────────────────────────────────\n\n @cute.jit\n def sk_epi(\n self,\n tSKrSK: cute.Tensor,\n tSKcSK: cute.Tensor,\n sAlpha: cute.Tensor,\n alpha_stage: cutlass.Int32,\n ):\n if cutlass.const_expr(self.needs_alpha):\n alpha_cp = sAlpha[None, AlphaProcessor.CUMPROD, alpha_stage]\n for i in cutlass.range_constexpr(cute.size(tSKrSK)):\n _, tok_kv = tSKcSK[i]\n tSKrSK[i] = tSKrSK[i] * cutlass.Float32(alpha_cp[tok_kv])\n\n # ─── sk_load_v ────────────────────────────────────────────────────────────\n\n @cute.jit\n def sk_load_v(\n self,\n tSKrSK: cute.Tensor,\n sV_DS: cute.Tensor,\n sk_tiled_copy_C,\n sk_thr_copy_C,\n v_stage: cutlass.Int32,\n ) -> cute.Tensor:\n tSKrV = cute.make_fragment_like(tSKrSK, self.dtype)\n tSKrV_cv = sk_thr_copy_C.retile(tSKrV)\n tSKsV = sk_thr_copy_C.partition_S(sV_DS)\n cute.copy(sk_tiled_copy_C, tSKsV[None, None, None, v_stage], tSKrV_cv)\n return tSKrV\n\n # ─── kv_decay_v ───────────────────────────────────────────────────────────\n\n @cute.jit\n def kv_decay_v(\n self,\n tKVrV: cute.Tensor,\n tKVcV: cute.Tensor,\n sAlpha: cute.Tensor,\n alpha_stage: cutlass.Int32,\n is_final_block: bool,\n B: cutlass.Int32,\n ):\n if cutlass.const_expr(self.needs_alpha):\n alpha_cumlog = sAlpha[None, AlphaProcessor.CUMSUM_LOG, alpha_stage]\n block_log = cutlass.Float32(alpha_cumlog[B - cutlass.Int32(1)])\n for i in cutlass.range_constexpr(cute.size(tKVrV)):\n _, tok = tKVcV[i]\n coeff = cute.math.exp2(\n block_log - cutlass.Float32(alpha_cumlog[tok]), fastmath=True\n )\n if cutlass.const_expr(is_final_block):\n if tok >= B:\n coeff = cutlass.Float32(0.0)\n tKVrV[i] = self.dtype(cutlass.Float32(tKVrV[i]) * coeff)\n else:\n for i in cutlass.range_constexpr(cute.size(tKVrV)):\n _, tok = tKVcV[i]\n if cutlass.const_expr(is_final_block):\n if tok >= B:\n tKVrV[i] = self.dtype(0.0)\n\n # ─── o_store ──────────────────────────────────────────────────────────────\n\n @cute.jit\n def o_store(\n self,\n tOrO: cute.Tensor,\n tOsO: cute.Tensor,\n o_tiled_copy_r2s,\n o_thr_copy_r2s,\n ):\n tOrO_f16 = cute.make_fragment_like(tOrO, self.dtype)\n for i in cutlass.range_constexpr(cute.size(tOrO)):\n tOrO_f16[i] = self.dtype(tOrO[i])\n tOrO_cv = o_thr_copy_r2s.retile(tOrO_f16)\n cute.arch.fence_view_async_shared()\n cute.copy(o_tiled_copy_r2s, tOrO_cv, tOsO)\n cute.arch.fence_view_async_shared()\n\n # ─── TMA load helpers ────────────────────────────────────────────────────\n\n @cute.jit\n def load_qkv_tma(\n self,\n sQ_SD: cute.Tensor,\n sK_DS: cute.Tensor,\n sV_DS: cute.Tensor,\n tma_atom_q: cute.CopyAtom,\n tma_tensor_q: cute.Tensor,\n tma_atom_k: cute.CopyAtom,\n tma_tensor_k: cute.Tensor,\n tma_atom_v: cute.CopyAtom,\n tma_tensor_v: cute.Tensor,\n q_pipeline,\n q_producer_state,\n k_pipeline,\n k_producer_state,\n v_pipeline,\n v_producer_state,\n blk: cutlass.Int32,\n tok_start,\n q_head_idx: cutlass.Int32,\n k_head_idx: cutlass.Int32,\n v_head_idx: cutlass.Int32,\n ):\n blk_tok = tok_start + blk * cutlass.Int32(self.BLK_KV)\n\n sK = sK_DS[None, None, k_producer_state.index]\n mK = cute.domain_offset(\n (cutlass.Int32(0), blk_tok),\n tma_tensor_k[None, None, k_head_idx],\n )\n gK = cute.zipped_divide(mK, (self.D, self.BLK_KV))[\n ((None, None), (cutlass.Int32(0), cutlass.Int32(0)))\n ]\n tKsK, tKgK = cpasync.tma_partition(\n tma_atom_k,\n 0,\n cute.make_layout(1),\n cute.group_modes(sK, 0, 2),\n cute.group_modes(gK, 0, 2),\n )\n k_pipeline.producer_acquire(k_producer_state)\n cute.copy(\n tma_atom_k,\n tKgK,\n tKsK,\n tma_bar_ptr=k_pipeline.producer_get_barrier(k_producer_state),\n )\n k_pipeline.producer_commit(k_producer_state)\n k_producer_state.advance()\n\n sQ = sQ_SD[None, None, q_producer_state.index]\n mQ = cute.domain_offset(\n (blk_tok, cutlass.Int32(0)),\n tma_tensor_q[None, None, q_head_idx],\n )\n gQ = cute.zipped_divide(mQ, (self.BLK_Q, self.D))[\n ((None, None), (cutlass.Int32(0), cutlass.Int32(0)))\n ]\n tQsQ, tQgQ = cpasync.tma_partition(\n tma_atom_q,\n 0,\n cute.make_layout(1),\n cute.group_modes(sQ, 0, 2),\n cute.group_modes(gQ, 0, 2),\n )\n q_pipeline.producer_acquire(q_producer_state)\n cute.copy(\n tma_atom_q,\n tQgQ,\n tQsQ,\n tma_bar_ptr=q_pipeline.producer_get_barrier(q_producer_state),\n )\n q_pipeline.producer_commit(q_producer_state)\n q_producer_state.advance()\n\n sV = sV_DS[None, None, v_producer_state.index]\n mV = cute.domain_offset(\n (cutlass.Int32(0), blk_tok),\n tma_tensor_v[None, None, v_head_idx],\n )\n gV = cute.zipped_divide(mV, (self.D, self.BLK_KV))[\n ((None, None), (cutlass.Int32(0), cutlass.Int32(0)))\n ]\n tVsV, tVgV = cpasync.tma_partition(\n tma_atom_v,\n 0,\n cute.make_layout(1),\n cute.group_modes(sV, 0, 2),\n cute.group_modes(gV, 0, 2),\n )\n v_pipeline.producer_acquire(v_producer_state)\n cute.copy(\n tma_atom_v,\n tVgV,\n tVsV,\n tma_bar_ptr=v_pipeline.producer_get_barrier(v_producer_state),\n )\n v_pipeline.producer_commit(v_producer_state)\n v_producer_state.advance()\n return q_producer_state, k_producer_state, v_producer_state\n\n # ─── load_alpha ───────────────────────────────────────────────────────────\n # Translates FlatMainloopTmaWarpSpecializedDeltaRule::load_alpha (scalar load).\n # Caller must sync before calling AlphaProcessor on the loaded data.\n\n @cute.jit\n def load_alpha(\n self,\n sAlpha: cute.Tensor,\n g_alpha: cute.Tensor,\n blk_tok: cutlass.Int32,\n tok_end,\n sab_head_idx: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n alpha_stage: cutlass.Int32,\n ):\n lane_id = cute.arch.lane_idx()\n sAlpha_k = sAlpha[None, None, alpha_stage]\n num_iters = self.BLK_Q // 32\n for i in cutlass.range_constexpr(num_iters):\n row = cutlass.Int32(i * 32) + lane_id\n tok = blk_tok + row\n if tok < tok_end:\n sAlpha_k[row, AlphaProcessor.CUMSUM_LOG] = g_alpha[\n tok * num_sab_heads + sab_head_idx\n ]\n else:\n sAlpha_k[row, AlphaProcessor.CUMSUM_LOG] = cutlass.Float32(1.0)\n\n # ─── load_beta ────────────────────────────────────────────────────────────\n # Translates FlatMainloopTmaWarpSpecializedDeltaRule::load_beta.\n\n @cute.jit\n def load_beta(\n self,\n sBeta: cute.Tensor,\n g_beta: cute.Tensor,\n blk_tok: cutlass.Int32,\n tok_end,\n sab_head_idx: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n beta_stage: cutlass.Int32,\n ):\n lane_id = cute.arch.lane_idx()\n sBeta_k = sBeta[None, beta_stage]\n num_iters = self.BLK_KV // 32\n for i in cutlass.range_constexpr(num_iters):\n row = cutlass.Int32(i * 32) + lane_id\n tok = blk_tok + row\n if tok < tok_end:\n sBeta_k[row] = g_beta[tok * num_sab_heads + sab_head_idx]\n else:\n sBeta_k[row] = cutlass.Float32(0.0)\n\n # ─── kv_load / kv_store ───────────────────────────────────────────────────\n\n @cute.jit\n def kv_load(\n self,\n tKVrKV: cute.Tensor,\n gKV: cute.Tensor,\n kv_thr_mma,\n ):\n c_kv = cute.make_identity_tensor((self.D, self.D))\n tKVcKV = kv_thr_mma.partition_C(c_kv)\n for i in cutlass.range(cute.size(tKVrKV), unroll_full=True):\n v_idx, k_idx = tKVcKV[i]\n tKVrKV[i] = gKV[k_idx, v_idx].to(self.acc_dtype)\n\n @cute.jit\n def kv_store(\n self,\n tKVrKV: cute.Tensor,\n gKV: cute.Tensor,\n kv_thr_mma,\n ):\n c_kv = cute.make_identity_tensor((self.D, self.D))\n tKVcKV = kv_thr_mma.partition_C(c_kv)\n for i in cutlass.range(cute.size(tKVrKV), unroll_full=True):\n v_idx, k_idx = tKVcKV[i]\n gKV[k_idx, v_idx] = tKVrKV[i].to(gKV.element_type)\n\n @cute.jit\n def maybe_store_checkpoint(\n self,\n tKVrKV: cute.Tensor,\n g_state_checkpoints: cute.Tensor,\n checkpoint_cu_starts: cute.Tensor,\n checkpoint_every_n_tokens: cutlass.Int32,\n kv_thr_mma,\n seq_idx: cutlass.Int32,\n o_head_idx: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n total_checkpoints: cutlass.Int32,\n block_end: cutlass.Int32,\n seq_len: cutlass.Int32,\n ):\n if cutlass.const_expr(self.needs_checkpointing):\n if (\n block_end <= seq_len\n and block_end % checkpoint_every_n_tokens == cutlass.Int32(0)\n ):\n checkpoint_idx = (\n cutlass.Int32(checkpoint_cu_starts[seq_idx])\n + block_end // checkpoint_every_n_tokens\n - cutlass.Int32(1)\n )\n checkpoint_layout = cute.make_ordered_layout(\n (self.D, self.D, num_sab_heads, total_checkpoints),\n order=(0, 1, 2, 3),\n )\n mCheckpoint = cute.make_tensor(\n g_state_checkpoints.iterator, checkpoint_layout\n )\n gCheckpointKV = mCheckpoint[None, None, o_head_idx, checkpoint_idx]\n self.kv_store(tKVrKV, gCheckpointKV, kv_thr_mma)\n\n # ─── compute_loop_body ───────────────────────────────────────────────────\n # Translates the C++ compute_loop_body lambda captured inside compute().\n # Called by Math WGs (tidx >= 128) for one block iteration.\n\n @cute.jit\n def compute_loop_body(\n self,\n # Smem tensors (staged; caller indexes the active stage)\n sQ_SD: cute.Tensor, # (BlkQ, D, StagesQ) – row-major atom, swizzled\n sK_SD: cute.Tensor, # (BlkKV, D, StagesK) – same atom\n sK_DS: cute.Tensor, # (D, BlkKV, StagesK) – K transposed\n sV_DS: cute.Tensor, # (D, BlkKV, StagesV) – V transposed\n sQK: cute.Tensor, # (BlkQ, BlkKV)\n sKK_inv: cute.Tensor, # (BlkKV, BlkKV)\n sKK_opd: cute.Tensor, # sKK_inv storage recast as Element\n sO: cute.Tensor, # O output smem (staged)\n sAlpha: cute.Tensor, # (BlkQ, AlphaProcessor.NUM_CHANNELS, StagesAlpha) or zero-shaped\n sBeta: cute.Tensor, # (BlkKV, StagesBeta) or zero-shaped\n kv_tiled_mma,\n # Mainloop pipelines and active read states\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n v_pipeline,\n v_consumer_state,\n o_pipeline,\n o_producer_state,\n alpha_pipeline,\n alpha_consumer_state,\n beta_pipeline,\n beta_consumer_state,\n # Compile-time flags\n is_first_block: bool,\n is_final_block: bool,\n # Valid token count for masking on final block\n B: cutlass.Int32,\n # Running KV state (D×D fp32, in registers across all blocks)\n tKVrKV: cute.Tensor,\n # Scale factor\n scale: cutlass.Float32,\n # WG role: MathWarpGroupRole.KK or MathWarpGroupRole.QK.\n wg_idx: cutlass.Int32,\n ):\n tidx, _, _ = cute.arch.thread_idx()\n thread_idx = tidx - cutlass.Int32(128) # relative to compute threads\n kk_thread_idx = thread_idx % cutlass.Int32(128)\n qk_thread_idx = thread_idx % cutlass.Int32(128)\n\n # ── TiledMMAs ─────────────────────────────────────────────────────────\n blk_q = cute.size(sQ_SD, mode=[0])\n blk_kv = cute.size(sK_SD, mode=[0])\n d = cute.size(sQ_SD, mode=[1])\n tile_shape_qk = (blk_q, blk_kv, d)\n tile_shape_kk = tile_shape_qk\n tile_shape_o1 = (d, blk_q, d)\n tile_shape_o2 = (d, blk_q, blk_kv)\n tile_shape_sk = (d, blk_kv, d)\n tile_shape_newv = (d, blk_kv, blk_kv)\n k_stage = k_consumer_state.index\n q_stage = q_consumer_state.index\n v_stage = v_consumer_state.index\n o_stage = cutlass.Int32(0)\n alpha_stage = alpha_consumer_state.index\n beta_stage = beta_consumer_state.index\n\n mma_atom_4w = warp.MmaF16BF16Op(self.dtype, self.acc_dtype, (16, 8, 16))\n mma_atom_8w = warp.MmaF16BF16Op(self.dtype, self.acc_dtype, (16, 8, 16))\n\n # QK/KK: 4 warps × 16M = 64M (1 warpgroup, 128 threads)\n qk_tiled_mma = cute.make_tiled_mma(\n mma_atom_4w, cute.make_layout((4, 1, 1)), permutation_mnk=tile_shape_qk\n )\n kk_tiled_mma = cute.make_tiled_mma(\n mma_atom_4w, cute.make_layout((4, 1, 1)), permutation_mnk=tile_shape_kk\n )\n\n # O1/O2/SK/NewV: 8 warps × 16M = 128M (both warpgroups, 256 threads)\n o1_tiled_mma = cute.make_tiled_mma(\n mma_atom_8w, cute.make_layout((8, 1, 1)), permutation_mnk=tile_shape_o1\n )\n o2_tiled_mma = cute.make_tiled_mma(\n mma_atom_8w, cute.make_layout((8, 1, 1)), permutation_mnk=tile_shape_o2\n )\n sk_tiled_mma = cute.make_tiled_mma(\n mma_atom_8w, cute.make_layout((8, 1, 1)), permutation_mnk=tile_shape_sk\n )\n newv_tiled_mma = cute.make_tiled_mma(\n mma_atom_8w, cute.make_layout((8, 1, 1)), permutation_mnk=tile_shape_newv\n )\n\n # ── Thread slices ─────────────────────────────────────────────────────\n qk_thr_mma = qk_tiled_mma.get_slice(qk_thread_idx)\n kk_thr_mma = kk_tiled_mma.get_slice(kk_thread_idx)\n sk_thr_mma = sk_tiled_mma.get_slice(thread_idx)\n newv_thr_mma = newv_tiled_mma.get_slice(thread_idx)\n o1_thr_mma = o1_tiled_mma.get_slice(thread_idx)\n o2_thr_mma = o2_tiled_mma.get_slice(thread_idx)\n kv_thr_mma = kv_tiled_mma.get_slice(thread_idx)\n\n # ── Copy atoms ────────────────────────────────────────────────────────\n ldsm_n4 = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(transpose=False, num_matrices=4), self.dtype\n )\n ldsm_t4 = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(transpose=True, num_matrices=4), self.dtype\n )\n\n # ── Active smem slices (extract 2D from staged tensors) ───────────────\n sQ_k = sQ_SD[None, None, q_stage] # (BlkQ, D)\n sK_SD_k = sK_SD[None, None, k_stage] # (BlkKV, D)\n sK_DS_k = sK_DS[None, None, k_stage] # (D, BlkKV)\n\n # ── QK copies ─────────────────────────────────────────────────────────\n qk_tiled_copy_A = cute.make_tiled_copy_A(ldsm_n4, qk_tiled_mma)\n qk_tiled_copy_B = cute.make_tiled_copy_B(ldsm_n4, qk_tiled_mma)\n qk_thr_copy_A = qk_tiled_copy_A.get_slice(qk_thread_idx)\n qk_thr_copy_B = qk_tiled_copy_B.get_slice(qk_thread_idx)\n\n tQKrQ = qk_thr_mma.make_fragment_A(qk_thr_mma.partition_A(sQ_k))\n tQKrQ_cv = qk_thr_copy_A.retile(tQKrQ)\n tQKsQ = qk_thr_copy_A.partition_S(sQ_SD)\n tQKrK = qk_thr_mma.make_fragment_B(qk_thr_mma.partition_B(sK_SD_k))\n tQKrK_cv = qk_thr_copy_B.retile(tQKrK)\n tQKsK = qk_thr_copy_B.partition_S(sK_SD)\n\n # ── KK copies (same atom as QK) ───────────────────────────────────────\n kk_tiled_copy_A = cute.make_tiled_copy_A(ldsm_n4, kk_tiled_mma)\n kk_tiled_copy_B = cute.make_tiled_copy_B(ldsm_n4, kk_tiled_mma)\n kk_thr_copy_A = kk_tiled_copy_A.get_slice(kk_thread_idx)\n kk_thr_copy_B = kk_tiled_copy_B.get_slice(kk_thread_idx)\n\n tKKrA = kk_thr_mma.make_fragment_A(kk_thr_mma.partition_A(sK_SD_k))\n tKKrA_cv = kk_thr_copy_A.retile(tKKrA)\n tKKsA = kk_thr_copy_A.partition_S(sK_SD)\n tKKrB = kk_thr_mma.make_fragment_B(kk_thr_mma.partition_B(sK_SD_k))\n tKKrB_cv = kk_thr_copy_B.retile(tKKrB)\n tKKsB = kk_thr_copy_B.partition_S(sK_SD)\n\n # ── SK copies ─────────────────────────────────────────────────────────\n # SK B: K loaded from sK_SD (row-major BlkKV×D) with LDSM_N — matches C++ SK B-operand\n # SK C: V loaded from sV_DS (col-major D×BlkKV) with LDSM_T\n sk_tiled_copy_B = cute.make_tiled_copy_B(ldsm_n4, sk_tiled_mma)\n sk_tiled_copy_C = cute.make_tiled_copy_C(ldsm_t4, sk_tiled_mma)\n sk_thr_copy_B = sk_tiled_copy_B.get_slice(thread_idx)\n sk_thr_copy_C = sk_tiled_copy_C.get_slice(thread_idx)\n\n # Work around DSL make_fragment_B not accepting partition_shape_B output directly.\n tSKrK = cute.make_rmem_tensor(\n sk_thr_mma.partition_shape_B(cute.slice_(tile_shape_sk, (0, None, None))),\n self.dtype,\n )\n tSKrK_cv = sk_thr_copy_B.retile(tSKrK)\n tSKsK = sk_thr_copy_B.partition_S(sK_SD)\n\n # ── NewV copies ───────────────────────────────────────────────────────\n newv_tiled_copy_B = cute.make_tiled_copy_B(ldsm_n4, newv_tiled_mma)\n newv_thr_copy_B = newv_tiled_copy_B.get_slice(thread_idx)\n tNewVrB = newv_thr_mma.make_fragment_B(newv_thr_mma.partition_B(sKK_opd))\n tNewVrB_cv = newv_thr_copy_B.retile(tNewVrB)\n tNewVsB = newv_thr_copy_B.partition_S(sKK_opd)\n\n # ── KV copies ─────────────────────────────────────────────────────────\n kv_tiled_copy_B = cute.make_tiled_copy_B(ldsm_t4, kv_tiled_mma)\n kv_thr_copy_B = kv_tiled_copy_B.get_slice(thread_idx)\n tKVrK = kv_thr_mma.make_fragment_B(kv_thr_mma.partition_B(sK_DS_k))\n tKVrK_cv = kv_thr_copy_B.retile(tKVrK)\n tKVsK = kv_thr_copy_B.partition_S(sK_DS)\n\n # ── O1/O2 copies ──────────────────────────────────────────────────────\n o1_tiled_copy_B = cute.make_tiled_copy_B(ldsm_n4, o1_tiled_mma)\n o2_tiled_copy_B = cute.make_tiled_copy_B(ldsm_n4, o2_tiled_mma)\n o1_thr_copy_B = o1_tiled_copy_B.get_slice(thread_idx)\n o2_thr_copy_B = o2_tiled_copy_B.get_slice(thread_idx)\n\n # Direct partition_B(sQ_k) preserves the swizzled Q layout here and produces\n # a non-C++ B fragment shape; derive the fragment from TileShapeO1 instead.\n tOrQ = cute.make_rmem_tensor(\n o1_thr_mma.partition_shape_B(cute.slice_(tile_shape_o1, (0, None, None))),\n self.dtype,\n )\n tOrQ_cv = o1_thr_copy_B.retile(tOrQ)\n tOsQ = o1_thr_copy_B.partition_S(sQ_SD)\n tOrQK = o2_thr_mma.make_fragment_B(o2_thr_mma.partition_B(sQK))\n tOrQK_cv = o2_thr_copy_B.retile(tOrQK)\n tOsQK = o2_thr_copy_B.partition_S(sQK)\n\n # ── O store (R→S STSM) ────────────────────────────────────────────────\n o_stsm = cute.make_copy_atom(\n warp.StMatrix8x8x16bOp(transpose=True, num_matrices=4), self.dtype\n )\n o_tiled_copy_r2s = cute.make_tiled_copy_C(o_stsm, o1_tiled_mma)\n o_thr_copy_r2s = o_tiled_copy_r2s.get_slice(thread_idx)\n tOsO = o_thr_copy_r2s.partition_D(sO)\n\n # ── Coordinate tensors for masking / alpha/beta indexing ──────────────\n cMqk = cute.make_identity_tensor((blk_q, blk_kv))\n tQKcMqk = qk_thr_mma.partition_C(cMqk)\n cMkk = cMqk # same shape (BlkKV == BlkQ == 64)\n tKKcMkk = kk_thr_mma.partition_C(cMkk)\n cO = cute.make_identity_tensor((d, blk_q))\n tOcO = o1_thr_mma.partition_C(cO)\n cSK = cute.make_identity_tensor((d, blk_kv))\n tSKcSK = sk_thr_mma.partition_C(cSK)\n cV = cute.make_identity_tensor((d, blk_kv))\n tKVcV = kv_thr_mma.partition_A(cV)\n\n # ── KK GEMM (WG0 only) ────────────────────────────────────────────────\n k_pipeline.consumer_wait(k_consumer_state)\n if cutlass.const_expr(self.needs_alpha):\n alpha_pipeline.consumer_wait(alpha_consumer_state)\n cute.arch.fence_view_async_shared()\n if cutlass.const_expr(self.needs_beta):\n beta_pipeline.consumer_wait(beta_consumer_state)\n cute.arch.fence_view_async_shared()\n # Match the C++ reject-non-role-first shape; ptxas keeps BRA.U around\n # the role body instead of predicating the HMMA/LDSM/STSM sequence.\n if wg_idx != MathWarpGroupRole.KK:\n cute.arch.sync_warp()\n else:\n cute.copy(kk_tiled_copy_A, tKKsA[None, None, None, k_stage], tKKrA_cv)\n cute.copy(kk_tiled_copy_B, tKKsB[None, None, None, k_stage], tKKrB_cv)\n tKKrKK = cute.make_rmem_tensor(\n kk_thr_mma.partition_shape_C((blk_kv, blk_kv)), self.acc_dtype\n )\n tKKrKK.fill(self.acc_dtype(0.0))\n cute.gemm(kk_tiled_mma, tKKrKK, tKKrA, tKKrB, tKKrKK)\n self.kk_epi(tKKrKK, tKKcMkk, sAlpha, sBeta, alpha_stage, beta_stage)\n self.qk_or_kk_mask(tKKrKK, tKKcMkk, is_final_block, B)\n self._kk_store_and_inv(\n tKKrKK,\n kk_tiled_mma,\n kk_thread_idx,\n sKK_inv,\n sKK_opd,\n sBeta,\n beta_stage,\n tKKcMkk,\n )\n if cutlass.const_expr(self.needs_beta):\n beta_pipeline.consumer_release(beta_consumer_state)\n beta_consumer_state.advance()\n\n # ── QK GEMM (WG1 only) ────────────────────────────────────────────────\n q_pipeline.consumer_wait(q_consumer_state)\n if wg_idx != MathWarpGroupRole.QK:\n cute.arch.sync_warp()\n else:\n cute.copy(qk_tiled_copy_A, tQKsQ[None, None, None, q_stage], tQKrQ_cv)\n cute.copy(qk_tiled_copy_B, tQKsK[None, None, None, k_stage], tQKrK_cv)\n tQKrQK = cute.make_rmem_tensor(\n qk_thr_mma.partition_shape_C((blk_q, blk_kv)), self.acc_dtype\n )\n tQKrQK.fill(self.acc_dtype(0.0))\n cute.gemm(qk_tiled_mma, tQKrQK, tQKrQ, tQKrK, tQKrQK)\n self.qk_epi(tQKrQK, tQKcMqk, sAlpha, alpha_stage, scale)\n self.qk_or_kk_mask(tQKrQK, tQKcMqk, is_final_block, B)\n self.qk_store(tQKrQK, sQK, qk_tiled_mma, qk_thread_idx)\n\n # ── O1: KV_state @ Q (both WGs, skip on first block) ─────────────────\n tOrO = cute.make_rmem_tensor(\n o1_thr_mma.partition_shape_C((d, blk_q)), self.acc_dtype\n )\n tOrO.fill(self.acc_dtype(0.0))\n if cutlass.const_expr(not is_first_block):\n cute.copy(o1_tiled_copy_B, tOsQ[None, None, None, q_stage], tOrQ_cv)\n tOrKV = SM80.make_acc_into_op(tKVrKV, o1_tiled_mma, self.dtype)\n cute.gemm(o1_tiled_mma, tOrO, tOrKV, tOrQ, tOrO)\n self.o1_epi(tOrO, tOcO, sAlpha, alpha_stage, scale)\n q_pipeline.consumer_release(q_consumer_state)\n q_consumer_state.advance()\n\n # ── SK: KV_state @ K^T (result negated below via V - SK) ─────────────\n tSKrSK = cute.make_rmem_tensor(\n sk_thr_mma.partition_shape_C((d, blk_kv)), self.acc_dtype\n )\n tSKrSK.fill(self.acc_dtype(0.0))\n if cutlass.const_expr(not is_first_block):\n tSKrS = SM80.make_acc_into_op(tKVrKV, sk_tiled_mma, self.dtype)\n cute.copy(sk_tiled_copy_B, tSKsK[None, None, None, k_stage], tSKrK_cv)\n cute.gemm(sk_tiled_mma, tSKrSK, tSKrS, tSKrK, tSKrSK)\n\n # ── Load V from smem ──────────────────────────────────────────────────\n v_pipeline.consumer_wait(v_consumer_state)\n tSKrV = self.sk_load_v(tSKrSK, sV_DS, sk_tiled_copy_C, sk_thr_copy_C, v_stage)\n\n # sk_epi + V - SK (SK=0 on first block, so V - SK = V)\n if cutlass.const_expr(not is_first_block):\n self.sk_epi(tSKrSK, tSKcSK, sAlpha, alpha_stage)\n for i in cutlass.range_constexpr(cute.size(tSKrV)):\n tSKrV[i] = tSKrV[i] - self.dtype(tSKrSK[i])\n\n # ── NewV = (V - SK) @ T^T (ordered: WG0 first) ──────────────────────\n tNewVrA = SM80.make_acc_into_op(tSKrV, newv_tiled_mma, self.dtype)\n tNewVrC = cute.make_rmem_tensor(\n newv_thr_mma.partition_shape_C((d, blk_kv)), self.acc_dtype\n )\n self._math_order_wait(wg_idx)\n cute.copy(newv_tiled_copy_B, tNewVsB, tNewVrB_cv)\n tNewVrC.fill(self.acc_dtype(0.0))\n cute.gemm(newv_tiled_mma, tNewVrC, tNewVrA, tNewVrB, tNewVrC)\n self._math_order_notify(wg_idx)\n v_pipeline.consumer_release(v_consumer_state)\n v_consumer_state.advance()\n\n # ── O2 = O1 + NewV @ QK (ordered: WG0 first) ────────────────────────\n tOrNewV = SM80.make_acc_into_op(tNewVrC, o2_tiled_mma, self.dtype)\n self._math_order_wait(wg_idx)\n cute.copy(o2_tiled_copy_B, tOsQK, tOrQK_cv)\n cute.gemm(o2_tiled_mma, tOrO, tOrNewV, tOrQK, tOrO)\n self._math_order_notify(wg_idx)\n\n # ── O store to smem ───────────────────────────────────────────────────\n o_pipeline.producer_acquire(o_producer_state)\n self.o_store(\n tOrO,\n tOsO[None, None, None, o_stage],\n o_tiled_copy_r2s,\n o_thr_copy_r2s,\n )\n o_pipeline.producer_commit(o_producer_state)\n o_producer_state.advance()\n\n # ── KV state update ───────────────────────────────────────────────────\n block_coeff = cutlass.Float32(1.0)\n if cutlass.const_expr(self.needs_alpha):\n block_coeff = cutlass.Float32(\n sAlpha[B - cutlass.Int32(1), AlphaProcessor.CUMPROD, alpha_stage]\n )\n\n for i in cutlass.range(cute.size(tKVrKV), unroll_full=True):\n tKVrKV[i] = block_coeff * tKVrKV[i]\n\n self.kv_decay_v(tOrNewV, tKVcV, sAlpha, alpha_stage, is_final_block, B)\n\n # KV += NewV @ K\n cute.copy(kv_tiled_copy_B, tKVsK[None, None, None, k_stage], tKVrK_cv)\n cute.gemm(kv_tiled_mma, tKVrKV, tOrNewV, tKVrK, tKVrKV)\n k_pipeline.consumer_release(k_consumer_state)\n k_consumer_state.advance()\n if cutlass.const_expr(self.needs_alpha):\n alpha_pipeline.consumer_release(alpha_consumer_state)\n alpha_consumer_state.advance()\n return (\n q_consumer_state,\n k_consumer_state,\n v_consumer_state,\n o_producer_state,\n alpha_consumer_state,\n beta_consumer_state,\n )\n\n # ─── Warp role entry points ──────────────────────────────────────────────\n # The current DSL bridge still uses CTA-wide sync epochs, but each role owns\n # its own loop, matching the C++ warp-specialized dispatch shape.\n\n @cute.jit\n def run_load_qkv_role(\n self,\n sQ_SD: cute.Tensor,\n sK_DS: cute.Tensor,\n sV_DS: cute.Tensor,\n tma_atom_q: cute.CopyAtom,\n tma_tensor_q: cute.Tensor,\n tma_atom_k: cute.CopyAtom,\n tma_tensor_k: cute.Tensor,\n tma_atom_v: cute.CopyAtom,\n tma_tensor_v: cute.Tensor,\n q_pipeline,\n k_pipeline,\n v_pipeline,\n num_blocks: cutlass.Int32,\n tok_start,\n q_head_idx: cutlass.Int32,\n k_head_idx: cutlass.Int32,\n v_head_idx: cutlass.Int32,\n ):\n q_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.q_stage\n )\n k_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.k_stage\n )\n v_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.v_stage\n )\n for blk in cutlass.range(num_blocks, unroll=1):\n (\n q_producer_state,\n k_producer_state,\n v_producer_state,\n ) = self.load_qkv_tma(\n sQ_SD,\n sK_DS,\n sV_DS,\n tma_atom_q,\n tma_tensor_q,\n tma_atom_k,\n tma_tensor_k,\n tma_atom_v,\n tma_tensor_v,\n q_pipeline,\n q_producer_state,\n k_pipeline,\n k_producer_state,\n v_pipeline,\n v_producer_state,\n blk,\n tok_start,\n q_head_idx,\n k_head_idx,\n v_head_idx,\n )\n\n @cute.jit\n def run_load_alpha_role(\n self,\n sAlpha: cute.Tensor,\n g_alpha: cute.Tensor,\n alpha_pipeline,\n scale: cutlass.Float32,\n num_blocks: cutlass.Int32,\n tok_start,\n tok_end,\n sab_head_idx: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n ):\n alpha_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.alpha_beta_stage\n )\n for blk in cutlass.range(num_blocks, unroll=1):\n blk_tok = tok_start + blk * cutlass.Int32(self.BLK_Q)\n if cutlass.const_expr(self.needs_alpha):\n alpha_pipeline.producer_acquire(alpha_producer_state)\n cute.arch.fence_view_async_shared()\n self.load_alpha(\n sAlpha,\n g_alpha,\n blk_tok,\n tok_end,\n sab_head_idx,\n num_sab_heads,\n alpha_producer_state.index,\n )\n AlphaProcessor().run(\n sAlpha[None, None, alpha_producer_state.index], scale\n )\n cute.arch.fence_view_async_shared()\n alpha_pipeline.producer_commit(alpha_producer_state)\n alpha_producer_state.advance()\n\n @cute.jit\n def run_load_beta_role(\n self,\n sBeta: cute.Tensor,\n g_beta: cute.Tensor,\n beta_pipeline,\n num_blocks: cutlass.Int32,\n tok_start,\n tok_end,\n sab_head_idx: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n ):\n beta_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.alpha_beta_stage\n )\n for blk in cutlass.range(num_blocks, unroll=1):\n blk_tok = tok_start + blk * cutlass.Int32(self.BLK_KV)\n if cutlass.const_expr(self.needs_beta):\n beta_pipeline.producer_acquire(beta_producer_state)\n cute.arch.fence_view_async_shared()\n self.load_beta(\n sBeta,\n g_beta,\n blk_tok,\n tok_end,\n sab_head_idx,\n num_sab_heads,\n beta_producer_state.index,\n )\n cute.arch.fence_view_async_shared()\n beta_pipeline.producer_commit(beta_producer_state)\n beta_producer_state.advance()\n\n @cute.jit\n def run_math_role(\n self,\n sQ_SD: cute.Tensor,\n sK_SD: cute.Tensor,\n sK_DS: cute.Tensor,\n sV_DS: cute.Tensor,\n sQK: cute.Tensor,\n sKK_inv: cute.Tensor,\n sKK_opd: cute.Tensor,\n sO: cute.Tensor,\n sAlpha: cute.Tensor,\n sBeta: cute.Tensor,\n q_pipeline,\n k_pipeline,\n v_pipeline,\n o_pipeline,\n alpha_pipeline,\n beta_pipeline,\n g_state: cute.Tensor,\n g_init_state: cute.Tensor,\n g_state_indices: cute.Tensor,\n g_state_checkpoints: cute.Tensor,\n checkpoint_cu_starts: cute.Tensor,\n work_desc: WorkDesc,\n scale: cutlass.Float32,\n wg_idx: cutlass.Int32,\n math_tidx: cutlass.Int32,\n num_blocks: cutlass.Int32,\n num_q_heads: cutlass.Int32,\n num_v_heads: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n num_seqs: cutlass.Int32,\n total_checkpoints: cutlass.Int32,\n checkpoint_every_n_tokens: cutlass.Int32,\n ):\n self._math_order_init(wg_idx)\n q_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.q_stage\n )\n k_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.k_stage\n )\n v_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.v_stage\n )\n o_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.o_stage\n )\n alpha_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.alpha_beta_stage\n )\n beta_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.alpha_beta_stage\n )\n\n kv_tiled_mma = cute.make_tiled_mma(\n warp.MmaF16BF16Op(self.dtype, self.acc_dtype, (16, 8, 16)),\n cute.make_layout((8, 1, 1)),\n permutation_mnk=(self.D, self.D, self.BLK_KV),\n )\n kv_thr_mma = kv_tiled_mma.get_slice(math_tidx)\n tKVrKV = cute.make_rmem_tensor(\n kv_thr_mma.partition_shape_C((self.D, self.D)), self.acc_dtype\n )\n tKVrKV.fill(self.acc_dtype(0.0))\n\n packed_state_layout = cute.make_ordered_layout(\n (self.D, self.D, num_sab_heads, num_seqs), order=(0, 1, 2, 3)\n )\n state_ref_shape = (g_state.shape[0], g_state.shape[1], self.D, self.D)\n state_ref_layout = cute.make_layout(state_ref_shape, stride=g_state.stride)\n indexed_state_layout = cute.select(state_ref_layout, mode=[3, 2, 1, 0])\n state_idx = work_desc.seq_idx\n if cutlass.const_expr(self.use_state_indices):\n state_idx = cutlass.Int32(g_state_indices[work_desc.seq_idx])\n state_layout = indexed_state_layout\n else:\n state_layout = packed_state_layout\n o_head_idx = work_desc.o_head_idx(num_q_heads, num_v_heads)\n mState = cute.make_tensor(g_state.iterator, state_layout)\n gStateKV = mState[None, None, o_head_idx, state_idx]\n if cutlass.const_expr(self.needs_init_state):\n init_state_ref_layout = cute.make_layout(\n state_ref_shape, stride=g_init_state.stride\n )\n indexed_init_state_layout = cute.select(\n init_state_ref_layout, mode=[3, 2, 1, 0]\n )\n if cutlass.const_expr(self.use_state_indices):\n init_state_layout = indexed_init_state_layout\n else:\n init_state_layout = packed_state_layout\n mInitState = cute.make_tensor(g_init_state.iterator, init_state_layout)\n gInitKV = mInitState[None, None, o_head_idx, state_idx]\n self.kv_load(tKVrKV, gInitKV, kv_thr_mma)\n\n first_B = work_desc.seq_len\n if first_B > cutlass.Int32(self.BLK_KV):\n first_B = cutlass.Int32(self.BLK_KV)\n if cutlass.const_expr(self.needs_init_state):\n (\n q_consumer_state,\n k_consumer_state,\n v_consumer_state,\n o_producer_state,\n alpha_consumer_state,\n beta_consumer_state,\n ) = self.compute_loop_body(\n sQ_SD,\n sK_SD,\n sK_DS,\n sV_DS,\n sQK,\n sKK_inv,\n sKK_opd,\n sO,\n sAlpha,\n sBeta,\n kv_tiled_mma,\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n v_pipeline,\n v_consumer_state,\n o_pipeline,\n o_producer_state,\n alpha_pipeline,\n alpha_consumer_state,\n beta_pipeline,\n beta_consumer_state,\n False,\n True,\n first_B,\n tKVrKV,\n scale,\n wg_idx,\n )\n else:\n (\n q_consumer_state,\n k_consumer_state,\n v_consumer_state,\n o_producer_state,\n alpha_consumer_state,\n beta_consumer_state,\n ) = self.compute_loop_body(\n sQ_SD,\n sK_SD,\n sK_DS,\n sV_DS,\n sQK,\n sKK_inv,\n sKK_opd,\n sO,\n sAlpha,\n sBeta,\n kv_tiled_mma,\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n v_pipeline,\n v_consumer_state,\n o_pipeline,\n o_producer_state,\n alpha_pipeline,\n alpha_consumer_state,\n beta_pipeline,\n beta_consumer_state,\n True,\n True,\n first_B,\n tKVrKV,\n scale,\n wg_idx,\n )\n self.maybe_store_checkpoint(\n tKVrKV,\n g_state_checkpoints,\n checkpoint_cu_starts,\n checkpoint_every_n_tokens,\n kv_thr_mma,\n work_desc.seq_idx,\n o_head_idx,\n num_sab_heads,\n total_checkpoints,\n cutlass.Int32(self.BLK_KV),\n work_desc.seq_len,\n )\n\n for blk in cutlass.range(\n cutlass.Int32(1), num_blocks - cutlass.Int32(1), cutlass.Int32(1), unroll=1\n ):\n (\n q_consumer_state,\n k_consumer_state,\n v_consumer_state,\n o_producer_state,\n alpha_consumer_state,\n beta_consumer_state,\n ) = self.compute_loop_body(\n sQ_SD,\n sK_SD,\n sK_DS,\n sV_DS,\n sQK,\n sKK_inv,\n sKK_opd,\n sO,\n sAlpha,\n sBeta,\n kv_tiled_mma,\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n v_pipeline,\n v_consumer_state,\n o_pipeline,\n o_producer_state,\n alpha_pipeline,\n alpha_consumer_state,\n beta_pipeline,\n beta_consumer_state,\n False,\n False,\n cutlass.Int32(self.BLK_KV),\n tKVrKV,\n scale,\n wg_idx,\n )\n self.maybe_store_checkpoint(\n tKVrKV,\n g_state_checkpoints,\n checkpoint_cu_starts,\n checkpoint_every_n_tokens,\n kv_thr_mma,\n work_desc.seq_idx,\n o_head_idx,\n num_sab_heads,\n total_checkpoints,\n (blk + cutlass.Int32(1)) * cutlass.Int32(self.BLK_KV),\n work_desc.seq_len,\n )\n\n if num_blocks != cutlass.Int32(1):\n last_blk = num_blocks - cutlass.Int32(1)\n last_B = work_desc.seq_len - last_blk * cutlass.Int32(self.BLK_KV)\n (\n q_consumer_state,\n k_consumer_state,\n v_consumer_state,\n o_producer_state,\n alpha_consumer_state,\n beta_consumer_state,\n ) = self.compute_loop_body(\n sQ_SD,\n sK_SD,\n sK_DS,\n sV_DS,\n sQK,\n sKK_inv,\n sKK_opd,\n sO,\n sAlpha,\n sBeta,\n kv_tiled_mma,\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n v_pipeline,\n v_consumer_state,\n o_pipeline,\n o_producer_state,\n alpha_pipeline,\n alpha_consumer_state,\n beta_pipeline,\n beta_consumer_state,\n False,\n True,\n last_B,\n tKVrKV,\n scale,\n wg_idx,\n )\n self.maybe_store_checkpoint(\n tKVrKV,\n g_state_checkpoints,\n checkpoint_cu_starts,\n checkpoint_every_n_tokens,\n kv_thr_mma,\n work_desc.seq_idx,\n o_head_idx,\n num_sab_heads,\n total_checkpoints,\n (last_blk + cutlass.Int32(1)) * cutlass.Int32(self.BLK_KV),\n work_desc.seq_len,\n )\n self.kv_store(tKVrKV, gStateKV, kv_thr_mma)\n\n # ─── Kernel entry point ───────────────────────────────────────────────────\n\n @cute.jit\n def __call__(\n self,\n g_q: cute.Tensor,\n g_k: cute.Tensor,\n g_v: cute.Tensor,\n g_o: cute.Tensor,\n g_alpha: cute.Tensor,\n g_beta: cute.Tensor,\n g_state: cute.Tensor,\n g_init_state: cute.Tensor,\n g_state_indices: cute.Tensor,\n g_state_checkpoints: cute.Tensor,\n checkpoint_cu_starts: cute.Tensor,\n g_tensormaps: cute.Tensor,\n cu_seqlens: cute.Tensor,\n scale: cutlass.Float32,\n num_q_heads: cutlass.Int32,\n num_k_heads: cutlass.Int32,\n num_v_heads: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n num_seqs: cutlass.Int32,\n total_checkpoints: cutlass.Int32,\n checkpoint_every_n_tokens: cutlass.Int32,\n grid_x: int,\n stream,\n ):\n qkv_smem_layout_atom = warpgroup.make_smem_layout_atom(\n warpgroup.SmemLayoutAtomKind.K_SW128,\n self.dtype,\n )\n q_storage_layout = cute.coalesce(\n cute.tile_to_shape(\n qkv_smem_layout_atom,\n (self.BLK_Q, self.D, self.q_stage),\n order=(0, 1, 2),\n ),\n target_profile=(1, 1, 1),\n )\n q_smem_layout = cute.slice_(q_storage_layout, (None, None, 0))\n k_storage_layout_sd = cute.coalesce(\n cute.tile_to_shape(\n qkv_smem_layout_atom,\n (self.BLK_KV, self.D, self.k_stage),\n order=(0, 1, 2),\n ),\n target_profile=(1, 1, 1),\n )\n k_storage_layout_ds = cute.select(k_storage_layout_sd, [1, 0, 2])\n v_storage_layout_sd = cute.coalesce(\n cute.tile_to_shape(\n qkv_smem_layout_atom,\n (self.BLK_KV, self.D, self.v_stage),\n order=(0, 1, 2),\n ),\n target_profile=(1, 1, 1),\n )\n v_storage_layout_ds = cute.select(v_storage_layout_sd, [1, 0, 2])\n k_smem_layout = cute.slice_(k_storage_layout_ds, (None, None, 0))\n v_smem_layout = cute.slice_(v_storage_layout_ds, (None, None, 0))\n o_smem_layout_atom = warpgroup.make_smem_layout_atom(\n warpgroup.SmemLayoutAtomKind.MN_SW32,\n self.dtype,\n )\n o_storage_layout = cute.tile_to_shape(\n o_smem_layout_atom,\n (self.D, self.BLK_Q, self.o_stage),\n order=(1, 0, 2),\n )\n o_smem_layout = cute.slice_(o_storage_layout, (None, None, 0))\n\n tma_load_op = cpasync.CopyBulkTensorTileG2SOp()\n tma_atom_q, tma_tensor_q = cpasync.make_tiled_tma_atom(\n tma_load_op, g_q, q_smem_layout, (self.BLK_Q, self.D)\n )\n tma_atom_k, tma_tensor_k = cpasync.make_tiled_tma_atom(\n tma_load_op, g_k, k_smem_layout, (self.D, self.BLK_KV)\n )\n tma_atom_v, tma_tensor_v = cpasync.make_tiled_tma_atom(\n tma_load_op, g_v, v_smem_layout, (self.D, self.BLK_KV)\n )\n\n tma_store_op = cpasync.CopyBulkTensorTileS2GOp()\n tma_atom_o, tma_tensor_o = cpasync.make_tiled_tma_atom(\n tma_store_op, g_o, o_smem_layout, (self.D, self.BLK_Q)\n )\n\n dtype_bytes = self.dtype.width // 8\n self.tma_load_q_bytes = cute.size(q_smem_layout) * dtype_bytes\n self.tma_load_k_bytes = cute.size(k_smem_layout) * dtype_bytes\n self.tma_load_v_bytes = cute.size(v_smem_layout) * dtype_bytes\n\n qk_layout_atom = cute.make_layout((8, 8), stride=(8, 1))\n qk_storage_layout = cute.tile_to_shape(\n qk_layout_atom, (self.BLK_Q, self.BLK_KV), order=(1, 0)\n )\n kk_storage_layout = cute.tile_to_shape(\n qk_layout_atom, (self.BLK_KV, self.BLK_KV), order=(1, 0)\n )\n alpha_storage_layout = cute.make_layout(\n (self.BLK_Q, AlphaProcessor.NUM_CHANNELS, self.alpha_beta_stage)\n )\n beta_storage_layout = cute.make_layout((self.BLK_KV, self.alpha_beta_stage))\n\n @cute.struct\n class SharedStorage:\n q_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.q_stage * 2]\n k_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.k_stage * 2]\n v_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.v_stage * 2]\n o_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.o_stage * 2]\n alpha_mbar_ptr: cute.struct.MemRange[\n cutlass.Int64, self.alpha_beta_stage * 2\n ]\n beta_mbar_ptr: cute.struct.MemRange[\n cutlass.Int64, self.alpha_beta_stage * 2\n ]\n\n smem_q: cute.struct.Align[\n cute.struct.MemRange[self.dtype, cute.cosize(q_storage_layout)],\n 128,\n ]\n smem_k: cute.struct.Align[\n cute.struct.MemRange[self.dtype, cute.cosize(k_storage_layout_sd)],\n 128,\n ]\n smem_v: cute.struct.Align[\n cute.struct.MemRange[self.dtype, cute.cosize(v_storage_layout_sd)],\n 128,\n ]\n smem_qk: cute.struct.Align[\n cute.struct.MemRange[self.dtype, cute.cosize(qk_storage_layout)],\n 16,\n ]\n smem_kk: cute.struct.Align[\n cute.struct.MemRange[\n self.inverse_dtype, cute.cosize(kk_storage_layout)\n ],\n 16,\n ]\n smem_o: cute.struct.Align[\n cute.struct.MemRange[self.dtype, cute.cosize(o_storage_layout)],\n 128,\n ]\n smem_alpha: cute.struct.Align[\n cute.struct.MemRange[\n cutlass.Float32, cute.cosize(alpha_storage_layout)\n ],\n 16,\n ]\n smem_beta: cute.struct.Align[\n cute.struct.MemRange[cutlass.Float32, cute.cosize(beta_storage_layout)],\n 16,\n ]\n\n self.shared_storage = SharedStorage\n\n self.kernel(\n g_alpha,\n g_beta,\n tma_atom_q,\n tma_tensor_q,\n tma_atom_k,\n tma_tensor_k,\n tma_atom_v,\n tma_tensor_v,\n tma_atom_o,\n tma_tensor_o,\n g_state,\n g_init_state,\n g_state_indices,\n g_state_checkpoints,\n checkpoint_cu_starts,\n g_tensormaps,\n cu_seqlens,\n scale,\n num_q_heads,\n num_k_heads,\n num_v_heads,\n num_sab_heads,\n num_seqs,\n total_checkpoints,\n checkpoint_every_n_tokens,\n ).launch(\n grid=(grid_x, 1, 1),\n block=(384, 1, 1),\n max_number_threads=(384, 1, 1),\n stream=stream,\n min_blocks_per_mp=1,\n )\n\n @cute.kernel\n def kernel(\n self,\n g_alpha: cute.Tensor,\n g_beta: cute.Tensor,\n tma_atom_q: cute.CopyAtom,\n tma_tensor_q: cute.Tensor,\n tma_atom_k: cute.CopyAtom,\n tma_tensor_k: cute.Tensor,\n tma_atom_v: cute.CopyAtom,\n tma_tensor_v: cute.Tensor,\n tma_atom_o: cute.CopyAtom,\n tma_tensor_o: cute.Tensor,\n g_state: cute.Tensor,\n g_init_state: cute.Tensor,\n g_state_indices: cute.Tensor,\n g_state_checkpoints: cute.Tensor,\n checkpoint_cu_starts: cute.Tensor,\n g_tensormaps: cute.Tensor,\n cu_seqlens: cute.Tensor,\n scale: cutlass.Float32,\n num_q_heads: cutlass.Int32,\n num_k_heads: cutlass.Int32,\n num_v_heads: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n num_seqs: cutlass.Int32,\n total_checkpoints: cutlass.Int32,\n checkpoint_every_n_tokens: cutlass.Int32,\n ):\n NUM_LOAD_WARP_GROUPS = 1\n NUM_MMA_WARP_GROUPS = 2\n THREADS_PER_WARP_GROUP = 128\n WARPS_PER_WARP_GROUP = 4\n MIN_BLOCKS_PER_MP = 1\n MAX_THREADS_PER_BLOCK = (\n NUM_LOAD_WARP_GROUPS + NUM_MMA_WARP_GROUPS\n ) * THREADS_PER_WARP_GROUP\n load_registers, mma_registers = self.get_register_requirements(\n MAX_THREADS_PER_BLOCK,\n MIN_BLOCKS_PER_MP,\n NUM_MMA_WARP_GROUPS,\n THREADS_PER_WARP_GROUP,\n )\n\n tidx, _, _ = cute.arch.thread_idx()\n warp_idx = cute.arch.make_warp_uniform(cute.arch.warp_idx())\n warp_group_idx = cute.arch.make_warp_uniform(\n tidx // cutlass.Int32(THREADS_PER_WARP_GROUP)\n )\n ldst_warp_role = cute.arch.make_warp_uniform(\n warp_idx % cutlass.Int32(WARPS_PER_WARP_GROUP)\n )\n\n if warp_idx == LoadStoreWarpRole.LOAD_QKV:\n cpasync.prefetch_descriptor(tma_atom_q)\n cpasync.prefetch_descriptor(tma_atom_k)\n cpasync.prefetch_descriptor(tma_atom_v)\n cpasync.prefetch_descriptor(tma_atom_o)\n\n work_desc = self.get_next_work(\n cu_seqlens,\n num_q_heads,\n num_v_heads,\n num_sab_heads,\n )\n tok_end = work_desc.tok_offset + work_desc.seq_len\n num_blocks = (\n work_desc.seq_len + cutlass.Int32(self.BLK_KV) - cutlass.Int32(1)\n ) // cutlass.Int32(self.BLK_KV)\n\n # math_tidx / wg_idx: valid for Math WG threads; LdSt WG gets negative values (unused)\n math_tidx = tidx - cutlass.Int32(THREADS_PER_WARP_GROUP)\n wg_idx = math_tidx // cutlass.Int32(THREADS_PER_WARP_GROUP)\n\n # ── Smem allocation ───────────────────────────────────────────────────\n allocator = cutlass.utils.SmemAllocator()\n storage = allocator.allocate(self.shared_storage)\n\n qkv_smem_layout_atom = warpgroup.make_smem_layout_atom(\n warpgroup.SmemLayoutAtomKind.K_SW128,\n self.dtype,\n )\n q_layout_sd = cute.coalesce(\n cute.tile_to_shape(\n qkv_smem_layout_atom,\n (self.BLK_Q, self.D, self.q_stage),\n order=(0, 1, 2),\n ),\n target_profile=(1, 1, 1),\n )\n sQ_SD = storage.smem_q.get_tensor(q_layout_sd.outer, swizzle=q_layout_sd.inner)\n\n k_layout_sd = cute.coalesce(\n cute.tile_to_shape(\n qkv_smem_layout_atom,\n (self.BLK_KV, self.D, self.k_stage),\n order=(0, 1, 2),\n ),\n target_profile=(1, 1, 1),\n )\n k_layout_ds = cute.select(k_layout_sd, [1, 0, 2])\n sK_SD = storage.smem_k.get_tensor(k_layout_sd.outer, swizzle=k_layout_sd.inner)\n sK_DS = storage.smem_k.get_tensor(k_layout_ds.outer, swizzle=k_layout_ds.inner)\n\n v_layout_sd = cute.coalesce(\n cute.tile_to_shape(\n qkv_smem_layout_atom,\n (self.BLK_KV, self.D, self.v_stage),\n order=(0, 1, 2),\n ),\n target_profile=(1, 1, 1),\n )\n v_layout_ds = cute.select(v_layout_sd, [1, 0, 2])\n sV_DS = storage.smem_v.get_tensor(v_layout_ds.outer, swizzle=v_layout_ds.inner)\n\n qk_layout_atom = cute.make_layout((8, 8), stride=(8, 1))\n qk_layout = cute.tile_to_shape(\n qk_layout_atom, (self.BLK_Q, self.BLK_KV), order=(1, 0)\n )\n sQK = storage.smem_qk.get_tensor(qk_layout)\n\n kk_layout = cute.tile_to_shape(\n qk_layout_atom, (self.BLK_KV, self.BLK_KV), order=(1, 0)\n )\n sKK_inv = storage.smem_kk.get_tensor(kk_layout)\n kk_opd_ptr = cute.recast_ptr(storage.smem_kk.data_ptr(), dtype=self.dtype)\n sKK_opd = cute.make_tensor(kk_opd_ptr, kk_layout)\n\n o_smem_layout_atom = warpgroup.make_smem_layout_atom(\n warpgroup.SmemLayoutAtomKind.MN_SW32,\n self.dtype,\n )\n o_layout = cute.tile_to_shape(\n o_smem_layout_atom,\n (self.D, self.BLK_Q, self.o_stage),\n order=(1, 0, 2),\n )\n sO = storage.smem_o.get_tensor(o_layout.outer, swizzle=o_layout.inner)\n alpha_layout = cute.make_layout(\n (self.BLK_Q, AlphaProcessor.NUM_CHANNELS, self.alpha_beta_stage)\n )\n sAlpha = storage.smem_alpha.get_tensor(alpha_layout)\n\n beta_layout = cute.make_layout((self.BLK_KV, self.alpha_beta_stage))\n sBeta = storage.smem_beta.get_tensor(beta_layout)\n\n load_producer_group = pipeline.CooperativeGroup(pipeline.Agent.Thread, 1)\n load_consumer_group = pipeline.CooperativeGroup(pipeline.Agent.Thread, 8)\n vector_producer_group = pipeline.CooperativeGroup(pipeline.Agent.Thread, 32)\n vector_consumer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread, NUM_MMA_WARP_GROUPS * THREADS_PER_WARP_GROUP\n )\n o_producer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread, NUM_MMA_WARP_GROUPS * THREADS_PER_WARP_GROUP\n )\n o_consumer_group = pipeline.CooperativeGroup(pipeline.Agent.Thread, 32)\n q_pipeline = pipeline.PipelineTmaAsync.create(\n barrier_storage=storage.q_mbar_ptr.data_ptr(),\n num_stages=self.q_stage,\n producer_group=load_producer_group,\n consumer_group=load_consumer_group,\n tx_count=self.tma_load_q_bytes,\n cta_layout_vmnk=cute.make_layout((1, 1, 1, 1)),\n )\n k_pipeline = pipeline.PipelineTmaAsync.create(\n barrier_storage=storage.k_mbar_ptr.data_ptr(),\n num_stages=self.k_stage,\n producer_group=load_producer_group,\n consumer_group=load_consumer_group,\n tx_count=self.tma_load_k_bytes,\n cta_layout_vmnk=cute.make_layout((1, 1, 1, 1)),\n )\n v_pipeline = pipeline.PipelineTmaAsync.create(\n barrier_storage=storage.v_mbar_ptr.data_ptr(),\n num_stages=self.v_stage,\n producer_group=load_producer_group,\n consumer_group=load_consumer_group,\n tx_count=self.tma_load_v_bytes,\n cta_layout_vmnk=cute.make_layout((1, 1, 1, 1)),\n )\n o_pipeline = pipeline.PipelineAsync.create(\n barrier_storage=storage.o_mbar_ptr.data_ptr(),\n num_stages=self.o_stage,\n producer_group=o_producer_group,\n consumer_group=o_consumer_group,\n )\n alpha_pipeline = pipeline.PipelineAsync.create(\n barrier_storage=storage.alpha_mbar_ptr.data_ptr(),\n num_stages=self.alpha_beta_stage,\n producer_group=vector_producer_group,\n consumer_group=vector_consumer_group,\n )\n beta_pipeline = pipeline.PipelineAsync.create(\n barrier_storage=storage.beta_mbar_ptr.data_ptr(),\n num_stages=self.alpha_beta_stage,\n producer_group=vector_producer_group,\n consumer_group=vector_consumer_group,\n )\n cute.arch.mbarrier_init_fence()\n cute.arch.sync_threads()\n\n if (\n work_desc.seq_len != cutlass.Int32(0)\n and warp_group_idx == WarpGroupRole.LDST\n ):\n cute.arch.setmaxregister_decrease(load_registers)\n if ldst_warp_role == LoadStoreWarpRole.LOAD_QKV:\n self.run_load_qkv_role(\n sQ_SD,\n sK_DS,\n sV_DS,\n tma_atom_q,\n tma_tensor_q,\n tma_atom_k,\n tma_tensor_k,\n tma_atom_v,\n tma_tensor_v,\n q_pipeline,\n k_pipeline,\n v_pipeline,\n num_blocks,\n work_desc.tok_offset,\n work_desc.q_head_idx(),\n work_desc.k_head_idx(num_q_heads, num_v_heads),\n work_desc.v_head_idx(),\n )\n elif ldst_warp_role == LoadStoreWarpRole.STORE_O:\n CollectiveStoreTma(self.BLK_Q, self.D).run(\n sO,\n tma_atom_o,\n tma_tensor_o,\n g_tensormaps,\n o_pipeline,\n num_blocks,\n work_desc,\n num_seqs,\n self.o_stage,\n num_q_heads,\n num_v_heads,\n )\n elif ldst_warp_role == LoadStoreWarpRole.LOAD_BETA:\n self.run_load_beta_role(\n sBeta,\n g_beta,\n beta_pipeline,\n num_blocks,\n work_desc.tok_offset,\n tok_end,\n work_desc.o_head_idx(num_q_heads, num_v_heads),\n num_sab_heads,\n )\n elif ldst_warp_role == LoadStoreWarpRole.LOAD_ALPHA:\n self.run_load_alpha_role(\n sAlpha,\n g_alpha,\n alpha_pipeline,\n scale,\n num_blocks,\n work_desc.tok_offset,\n tok_end,\n work_desc.o_head_idx(num_q_heads, num_v_heads),\n num_sab_heads,\n )\n elif work_desc.seq_len != cutlass.Int32(0):\n cute.arch.setmaxregister_increase(mma_registers)\n\n self.run_math_role(\n sQ_SD,\n sK_SD,\n sK_DS,\n sV_DS,\n sQK,\n sKK_inv,\n sKK_opd,\n sO,\n sAlpha,\n sBeta,\n q_pipeline,\n k_pipeline,\n v_pipeline,\n o_pipeline,\n alpha_pipeline,\n beta_pipeline,\n g_state,\n g_init_state,\n g_state_indices,\n g_state_checkpoints,\n checkpoint_cu_starts,\n work_desc,\n scale,\n wg_idx,\n math_tidx,\n num_blocks,\n num_q_heads,\n num_v_heads,\n num_sab_heads,\n num_seqs,\n total_checkpoints,\n checkpoint_every_n_tokens,\n )\n\n\n# ─── Public API ──────────────────────────────────────────────────────────────\n\n\ndef delta_rule_prefill_dsl(\n o: torch.Tensor, # (total_seqlen, num_o_heads, D) fp16/bf16, output\n state: torch.Tensor, # (num_seqs, num_sab_heads, D, D) fp32, output\n q: torch.Tensor, # (total_seqlen, num_q_heads, D)\n k: torch.Tensor, # (total_seqlen, num_k_heads, D)\n v: torch.Tensor, # (total_seqlen, num_v_heads, D)\n init_state: torch.Tensor | None, # (num_seqs, num_sab_heads, D, D) fp32, optional\n alpha: torch.Tensor | None,\n beta: torch.Tensor | None,\n cu_seqlens: torch.Tensor, # (num_seqs+1,) int64\n scale: float,\n state_checkpoints: torch.Tensor | None = None,\n checkpoint_cu_starts: torch.Tensor | None = None,\n checkpoint_every_n_tokens: int = 0,\n state_indices: torch.Tensor | None = None,\n):\n from cutlass.cute.runtime import from_dlpack\n import cuda.bindings.driver as cuda_driver\n\n D = q.shape[-1]\n\n num_seqs = cu_seqlens.shape[0] - 1\n num_q_heads = q.shape[1]\n num_k_heads = k.shape[1]\n num_v_heads = v.shape[1]\n num_sab_heads = max(num_q_heads, num_v_heads)\n\n if not _FullyFusedDeltaRuleSm120.can_implement(\n num_q_heads, num_k_heads, num_v_heads, D, q.element_size()\n ):\n raise RuntimeError(\"can_implement failed\")\n if D != 128:\n raise RuntimeError(f\"DSL kernel only supports D=128, got {D}\")\n\n needs_alpha = alpha is not None\n needs_beta = beta is not None\n needs_init_state = init_state is not None\n needs_checkpointing = checkpoint_every_n_tokens > 0\n use_state_indices = state_indices is not None\n kernel_dtype = {\n torch.float16: cutlass.Float16,\n torch.bfloat16: cutlass.BFloat16,\n }.get(q.dtype)\n if kernel_dtype is None:\n raise RuntimeError(f\"DSL kernel only supports fp16/bf16 inputs, got {q.dtype}\")\n\n if k.dtype != q.dtype or v.dtype != q.dtype or o.dtype != q.dtype:\n raise RuntimeError(\n f\"q/k/v/o dtypes must match, got {q.dtype}, {k.dtype}, {v.dtype}, {o.dtype}\"\n )\n if alpha is not None and alpha.dtype != torch.float32:\n raise RuntimeError(f\"alpha must have dtype torch.float32, got {alpha.dtype}\")\n if beta is not None and beta.dtype != torch.float32:\n raise RuntimeError(f\"beta must have dtype torch.float32, got {beta.dtype}\")\n if init_state is not None:\n state_dtype_to_cutlass(init_state.dtype)\n state_dtype_to_cutlass(state.dtype)\n if state_checkpoints is not None:\n state_dtype_to_cutlass(state_checkpoints.dtype)\n if not is_integer_dtype(cu_seqlens.dtype):\n raise RuntimeError(\n f\"cu_seqlens must have an integer dtype, got {cu_seqlens.dtype}\"\n )\n\n expected_state_tail = (num_sab_heads, D, D)\n for name, tensor in ((\"state\", state), (\"init_state\", init_state)):\n if tensor is None:\n continue\n if (\n not use_state_indices and tensor.shape != (num_seqs, *expected_state_tail)\n ) or (use_state_indices and tuple(tensor.shape[1:]) != expected_state_tail):\n raise RuntimeError(\n f\"{name} must have shape \"\n f\"{('[N_pool]' if use_state_indices else f'[{num_seqs}]')} + {expected_state_tail}, \"\n f\"got {tuple(tensor.shape)}\"\n )\n if use_state_indices and (\n not is_integer_dtype(state_indices.dtype) or state_indices.shape != (num_seqs,)\n ):\n raise RuntimeError(\n f\"state_indices must have shape {(num_seqs,)} and an integer dtype\"\n )\n\n for name, tensor in (\n (\"q\", q),\n (\"k\", k),\n (\"v\", v),\n (\"o\", o),\n (\"cu_seqlens\", cu_seqlens),\n ):\n if not tensor.is_contiguous():\n raise RuntimeError(f\"{name} must be contiguous\")\n for name, tensor in (\n (\"alpha\", alpha),\n (\"beta\", beta),\n (\"state_indices\", state_indices),\n ):\n if tensor is not None and not tensor.is_contiguous():\n raise RuntimeError(f\"{name} must be contiguous\")\n for name, tensor in ((\"state\", state), (\"init_state\", init_state)):\n if tensor is None:\n continue\n if not use_state_indices and not tensor.is_contiguous():\n raise RuntimeError(f\"{name} must be contiguous\")\n\n total_seqlen = q.shape[0]\n num_o_heads = o.shape[1]\n q_tma = q.as_strided(\n (total_seqlen, D, num_q_heads),\n (num_q_heads * D, 1, D),\n )\n k_tma = k.as_strided(\n (D, total_seqlen, num_k_heads),\n (1, num_k_heads * D, D),\n )\n v_tma = v.as_strided(\n (D, total_seqlen, num_v_heads),\n (1, num_v_heads * D, D),\n )\n o_tma = o.as_strided(\n (D, total_seqlen, num_o_heads),\n (1, num_o_heads * D, D),\n )\n total_checkpoints = state_checkpoints.shape[0] if needs_checkpointing else 1\n\n workspace_size = get_device_sm_count(q.device) * 128\n tensormaps_t = _get_cache_buf(\"gdn_prefill_tensormaps\", workspace_size, q.device)\n\n stream_val = torch.cuda.current_stream().cuda_stream\n stream = cuda_driver.CUstream(stream_val)\n\n enable_tvm_ffi = True\n if enable_tvm_ffi:\n from_dlpack = lambda *args, **kwargs: cute.runtime.from_dlpack(\n *args, **{**kwargs, \"enable_tvm_ffi\": True}\n )\n\n # Keep head counts and varlen extents runtime values across cached compiles.\n q_cute = from_dlpack(q_tma, assumed_align=16).mark_layout_dynamic(leading_dim=1)\n k_cute = from_dlpack(k_tma, assumed_align=16).mark_layout_dynamic(leading_dim=0)\n v_cute = from_dlpack(v_tma, assumed_align=16).mark_layout_dynamic(leading_dim=0)\n o_cute = from_dlpack(o_tma, assumed_align=16).mark_layout_dynamic(leading_dim=0)\n alpha_cute = (\n from_dlpack(alpha.reshape(-1), assumed_align=16).mark_layout_dynamic()\n if needs_alpha\n else None\n )\n beta_cute = (\n from_dlpack(beta.reshape(-1), assumed_align=16).mark_layout_dynamic()\n if needs_beta\n else None\n )\n state_cute = from_dlpack(state, assumed_align=16).mark_layout_dynamic()\n init_state_cute = (\n from_dlpack(init_state, assumed_align=16).mark_layout_dynamic()\n if needs_init_state\n else None\n )\n state_indices_cute = (\n from_dlpack(state_indices, assumed_align=4).mark_layout_dynamic()\n if use_state_indices\n else None\n )\n state_checkpoints_cute = (\n from_dlpack(\n state_checkpoints.reshape(-1), assumed_align=16\n ).mark_layout_dynamic()\n if needs_checkpointing\n else None\n )\n checkpoint_cu_cute = (\n from_dlpack(checkpoint_cu_starts, assumed_align=8).mark_layout_dynamic()\n if needs_checkpointing\n else None\n )\n tensormaps_cute = from_dlpack(tensormaps_t, assumed_align=128).mark_layout_dynamic()\n cu_cute = from_dlpack(cu_seqlens, assumed_align=8).mark_layout_dynamic()\n\n delta_rule_kernel = _FullyFusedDeltaRuleSm120(\n needs_alpha,\n needs_beta,\n needs_init_state,\n needs_checkpointing,\n kernel_dtype,\n initial_state_dtype=state_dtype_to_cutlass(\n init_state.dtype if needs_init_state else torch.float32\n ),\n state_dtype=state_dtype_to_cutlass(state.dtype),\n checkpoint_state_dtype=state_dtype_to_cutlass(\n state_checkpoints.dtype if needs_checkpointing else torch.float32\n ),\n use_state_indices=use_state_indices,\n cu_seqlens_dtype=cu_seqlens.dtype,\n state_indices_dtype=state_indices.dtype if use_state_indices else None,\n checkpoint_cu_starts_dtype=(\n checkpoint_cu_starts.dtype if needs_checkpointing else None\n ),\n state_inner_strides=(tuple(state.stride()[1:]) if use_state_indices else None),\n init_state_inner_strides=(\n tuple(init_state.stride()[1:])\n if use_state_indices and needs_init_state\n else None\n ),\n )\n\n kernel_args = (\n q_cute,\n k_cute,\n v_cute,\n o_cute,\n alpha_cute,\n beta_cute,\n state_cute,\n init_state_cute,\n state_indices_cute,\n state_checkpoints_cute,\n checkpoint_cu_cute,\n tensormaps_cute,\n cu_cute,\n cutlass.Float32(scale),\n cutlass.Int32(num_q_heads),\n cutlass.Int32(num_k_heads),\n cutlass.Int32(num_v_heads),\n cutlass.Int32(num_sab_heads),\n cutlass.Int32(num_seqs),\n cutlass.Int32(total_checkpoints),\n cutlass.Int32(checkpoint_every_n_tokens),\n num_seqs * num_sab_heads,\n stream,\n )\n compiled_delta_rule_kernel = cached_compile(\n delta_rule_kernel,\n *kernel_args,\n compile_options=sm12x_compile_options(q.device),\n )\n compiled_delta_rule_kernel(*kernel_args)\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## 📌 Description\n\nCache SM90 and SM120 non-CP kernel objects and compile options, and construct CuTe tensor wrappers only during compilation. Replay compiled kernels through raw TVM-FFI arguments to remove repeated launch preparation from the eager path.\n\nfollow up of #4374 for non-CP launch path.\n\n## 🔍 Related Issues\n## 🚀 Pull Request Checklist\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc. -->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n\n## Summary by CodeRabbit\n\n* **Performance Improvements**\n * Improved prefill execution by reusing compiled device-specific kernels across calls.\n * Reduced repeated setup and conversion overhead, especially for workloads with recurring prefill operations.\n * Added optimized handling for supported SM90 and SM120 GPU architectures.\n* **Compatibility**\n * Existing public interfaces remain unchanged.\n\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1081,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"f47f2d254d78afb7bf4600170f007edd4a6b556e"},"date":{"kind":"string","value":"2026-08-24T19:31:00+08:00"},"pr_number":{"kind":"number","value":4699,"string":"4,699"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/4699"},"title":{"kind":"string","value":"perf(gdn): reduce non-CP CuTeDSL launch overhead (#4699)"},"message":{"kind":"string","value":"perf(gdn): reduce non-CP CuTeDSL launch overhead (#4699)\n\nCache SM90 and SM120 non-CP kernel objects and compile options, and\nconstruct CuTe tensor wrappers only during compilation. Replay compiled\nkernels through raw TVM-FFI arguments to remove repeated launch\npreparation from the eager path.\n\nfollow up of #4374 for non-CP launch path."},"path":{"kind":"string","value":"flashinfer/gdn_kernels/delta_rule_dsl/delta_rule_sm90.py"},"language":{"kind":"string","value":"cute_dsl"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"from enum import IntEnum\n\nimport torch\nimport cutlass\nimport cutlass.cute as cute\nimport cutlass.pipeline as pipeline\nfrom cutlass.cute.nvgpu import warp, warpgroup, cpasync\nfrom ...utils import get_device_sm_count, _get_cache_buf\nfrom .alpha import AlphaProcessor\nfrom .collective_store_tma import CollectiveStoreTma\nfrom .custom_compile_cache import KeyedCompileMixin, cached_compile\nfrom .collective_inverse_hmma import CollectiveInverse\nfrom .helpers import SM90, round_down, select_tensor_10, state_dtype_to_cutlass\nfrom .schedule import WorkDesc\nfrom .varlen_helper import is_integer_dtype\n\n\n# ─── Named-barrier IDs used by the compute kernel ────────────────────────────\n# Must not conflict with each other or with pipeline barrier storage.\n\n\nclass NamedBarrier(IntEnum):\n MATH_WG0 = 4 # OrderedMathBarriers: StreamkBarrier0\n MATH_WG1 = 5 # OrderedMathBarriers: StreamkBarrier1\n KK_SYNC = 13 # sync all 128 WG0 threads before collective_inverse\n\n\nclass WarpGroupRole(IntEnum):\n LDST = 0\n MATH_STATE0 = 1\n MATH_STATE1 = 2\n MATH_AUX = 3\n\n\nclass LoadStoreWarpRole(IntEnum):\n STORE_O = 0\n LOAD_QKV = 1\n LOAD_BETA = 2\n LOAD_ALPHA = 3\n\n\nclass MathWarpGroupRole(IntEnum):\n STATE0 = 0\n STATE1 = 1\n AUX = 2\n KK = 0\n QK = 1\n\n\n# ─── Warp-specialized delta-rule kernel ───────────────────────────────────────\n# Grid: (num_seqs * num_sab_heads, 1, 1)\n# Block: 512 threads → WG0=LD/ST, WG1/WG2=state math, WG3=aux math.\n#\n# needs_alpha / needs_beta / needs_init_state are class attributes set in __init__.\n# The JIT compiler specialises per instance, so they are compile-time booleans\n# inside the kernel without any parameter-passing trickery.\n\n\nclass _FullyFusedDeltaRuleSm90(KeyedCompileMixin):\n @staticmethod\n def get_register_requirements(\n max_threads_per_block: int,\n min_blocks_per_multiprocessor: int,\n num_state_mma_warp_groups: int,\n threads_per_warp_group: int,\n ) -> tuple[int, int, int]:\n reg_alloc_granularity = 8\n load_registers = 40 - 2 * reg_alloc_granularity\n aux_registers = 128 - load_registers\n total_registers = (\n round_down(\n 64 * 1024 // min_blocks_per_multiprocessor,\n max_threads_per_block * reg_alloc_granularity,\n )\n // threads_per_warp_group\n )\n state_mma_registers = round_down(\n (total_registers - load_registers - aux_registers)\n // num_state_mma_warp_groups,\n reg_alloc_granularity,\n )\n return (\n min(248, load_registers),\n min(248, state_mma_registers),\n min(248, aux_registers),\n )\n\n @staticmethod\n def can_implement(\n num_q_heads: int,\n num_k_heads: int,\n num_v_heads: int,\n head_size: int,\n element_size: int,\n ) -> bool:\n ratio = (\n num_q_heads // num_v_heads\n if num_q_heads > num_v_heads\n else num_v_heads // num_q_heads\n )\n is_gva_enabled = num_v_heads > num_q_heads\n\n is_gqa_like = (\n (num_k_heads == num_v_heads)\n and (num_q_heads == ratio * num_k_heads)\n and (num_q_heads == ratio * num_v_heads)\n )\n is_gva_like = (\n (num_q_heads == num_k_heads)\n and (num_v_heads == ratio * num_q_heads)\n and (num_v_heads == ratio * num_k_heads)\n )\n\n alignment = 16 // element_size\n return (\n ((not is_gva_enabled and is_gqa_like) or (is_gva_enabled and is_gva_like))\n and (head_size <= 128)\n and ((head_size % alignment) == 0)\n )\n\n def __init__(\n self,\n needs_alpha: bool,\n needs_beta: bool,\n needs_init_state: bool,\n needs_checkpointing: bool,\n dtype: type[cutlass.Numeric] = cutlass.Float16,\n acc_dtype: type[cutlass.Numeric] = cutlass.Float32,\n initial_state_dtype: type[cutlass.Numeric] = cutlass.Float32,\n state_dtype: type[cutlass.Numeric] = cutlass.Float32,\n checkpoint_state_dtype: type[cutlass.Numeric] = cutlass.Float32,\n use_state_indices: bool = False,\n cu_seqlens_dtype: torch.dtype = torch.int64,\n state_indices_dtype: torch.dtype | None = None,\n checkpoint_cu_starts_dtype: torch.dtype | None = None,\n state_inner_strides: tuple[int, ...] | None = None,\n init_state_inner_strides: tuple[int, ...] | None = None,\n ):\n self.needs_alpha = needs_alpha\n self.needs_beta = needs_beta\n self.needs_init_state = needs_init_state\n self.needs_checkpointing = needs_checkpointing\n self.dtype = dtype\n self.acc_dtype = acc_dtype\n self.initial_state_dtype = initial_state_dtype\n self.state_dtype = state_dtype\n self.checkpoint_state_dtype = checkpoint_state_dtype\n self.use_state_indices = use_state_indices\n self.cu_seqlens_dtype = cu_seqlens_dtype\n self.state_indices_dtype = state_indices_dtype\n self.checkpoint_cu_starts_dtype = checkpoint_cu_starts_dtype\n self.state_inner_strides = state_inner_strides\n self.init_state_inner_strides = init_state_inner_strides\n self.inverse_dtype = cutlass.Float16\n self.BLK_Q = 64\n self.BLK_KV = 64\n self.D = 128\n self.q_stage = 2\n self.k_stage = 3\n self.v_stage = 2\n self.o_stage = 2\n self.qk_stage = 2\n self.kk_stage = 2\n self.alpha_beta_stage = 5\n self.manual_cache_key(\n \"needs_alpha\",\n \"needs_beta\",\n \"needs_init_state\",\n \"needs_checkpointing\",\n \"dtype\",\n \"acc_dtype\",\n \"initial_state_dtype\",\n \"state_dtype\",\n \"checkpoint_state_dtype\",\n \"use_state_indices\",\n \"cu_seqlens_dtype\",\n \"state_indices_dtype\",\n \"checkpoint_cu_starts_dtype\",\n \"state_inner_strides\",\n \"init_state_inner_strides\",\n \"inverse_dtype\",\n \"BLK_Q\",\n \"BLK_KV\",\n \"D\",\n \"q_stage\",\n \"k_stage\",\n \"v_stage\",\n \"o_stage\",\n \"qk_stage\",\n \"kk_stage\",\n \"alpha_beta_stage\",\n )\n\n def get_next_work(\n self,\n cu_seqlens: cute.Tensor,\n num_q_heads: cutlass.Int32,\n num_v_heads: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n ) -> WorkDesc:\n bx, _, _ = cute.arch.block_idx()\n seq_idx = bx // num_sab_heads\n o_head_idx = bx % num_sab_heads\n q_head_idx = o_head_idx * num_q_heads // num_sab_heads\n v_head_idx = o_head_idx * num_v_heads // num_sab_heads\n tok_start = cu_seqlens[seq_idx]\n seq_len = cutlass.Int32(cu_seqlens[seq_idx + 1] - tok_start)\n\n return WorkDesc(\n seq_idx=seq_idx,\n private_q_head_idx=q_head_idx,\n private_v_head_idx=v_head_idx,\n tok_offset=tok_start,\n seq_len=seq_len,\n tile_idx=cutlass.Int32(0),\n )\n\n # ─── Ordered 2-WG math barriers ───────────────────────────────────────────\n # Translates flat::OrderedNamedBarriers<UseReservedNB, NB0, NB1>.\n # wg_idx: MathWarpGroupRole.KK or MathWarpGroupRole.QK.\n\n @cute.jit\n def _math_order_init(self, wg_idx: cutlass.Int32):\n \"\"\"Pre-arrive at WG0's barrier so WG0 is unblocked on the first wait.\"\"\"\n if wg_idx == MathWarpGroupRole.QK:\n cute.arch.barrier_arrive(\n barrier_id=NamedBarrier.MATH_WG0, number_of_threads=256\n )\n\n @cute.jit\n def _math_order_wait(self, wg_idx: cutlass.Int32):\n \"\"\"Arrive+wait on this WG's own ordered barrier.\"\"\"\n if wg_idx == MathWarpGroupRole.KK:\n cute.arch.barrier(barrier_id=NamedBarrier.MATH_WG0, number_of_threads=256)\n else:\n cute.arch.barrier(barrier_id=NamedBarrier.MATH_WG1, number_of_threads=256)\n\n @cute.jit\n def _math_order_notify(self, wg_idx: cutlass.Int32):\n \"\"\"Arrive at the other WG's barrier to unblock it.\"\"\"\n if wg_idx == MathWarpGroupRole.KK:\n cute.arch.barrier_arrive(\n barrier_id=NamedBarrier.MATH_WG1, number_of_threads=256\n )\n else:\n cute.arch.barrier_arrive(\n barrier_id=NamedBarrier.MATH_WG0, number_of_threads=256\n )\n\n # ─── kk_store_and_inv ─────────────────────────────────────────────────────\n\n @cute.jit\n def _kk_store_and_inv(\n self,\n tKKrKK: cute.Tensor, # fp32 KK accumulator (from 128-thread kk_tiled_mma)\n kk_tiled_mma,\n kk_thread_idx: cutlass.Int32,\n sKK_inv: cute.Tensor, # (BlkKV, BlkKV) 8×8-tiled smem\n sKK_opd: cute.Tensor, # sKK_inv storage recast as Element for MMA operand\n sBeta: cute.Tensor, # (BlkKV, StagesBeta) - used when needs_beta\n beta_pipe_idx: cutlass.Int32,\n tKKcMkk: cute.Tensor, # coordinate mapping for KK fragment\n ):\n \"\"\"Store tKKrKK → sKK_inv, Inverse, optionally reload+beta.\"\"\"\n stsm_atom = cute.make_copy_atom(\n warp.StMatrix8x8x16bOp(transpose=False, num_matrices=4), self.inverse_dtype\n )\n tiled_store = cute.make_tiled_copy_C(stsm_atom, kk_tiled_mma)\n thr_store = tiled_store.get_slice(kk_thread_idx)\n tKKsKK = thr_store.partition_D(sKK_inv)\n tKKrKK_cv = thr_store.retile(tKKrKK)\n tKKrKK_inv = cute.make_fragment_like(tKKrKK_cv, self.inverse_dtype)\n for i in cutlass.range_constexpr(cute.size(tKKrKK_cv)):\n tKKrKK_inv[i] = self.inverse_dtype(tKKrKK_cv[i])\n cute.copy(tiled_store, tKKrKK_inv, tKKsKK)\n\n cute.arch.barrier(barrier_id=NamedBarrier.KK_SYNC, number_of_threads=128)\n CollectiveInverse().run(sKK_inv, NamedBarrier.KK_SYNC)\n\n if cutlass.const_expr(self.needs_beta or self.dtype != self.inverse_dtype):\n cute.arch.barrier(barrier_id=NamedBarrier.KK_SYNC, number_of_threads=128)\n ldsm_atom = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(transpose=False, num_matrices=4),\n self.inverse_dtype,\n )\n tiled_load = cute.make_tiled_copy_C(ldsm_atom, kk_tiled_mma)\n thr_load = tiled_load.get_slice(kk_thread_idx)\n tKKrKK_cpy = cute.make_fragment_like(tKKrKK_inv)\n tKKrKK_cvt = cute.make_fragment_like(tKKrKK_inv, self.dtype)\n cute.copy(tiled_load, thr_load.partition_S(sKK_inv), tKKrKK_cpy)\n tKKcMkk_cv = thr_load.retile(tKKcMkk)\n\n for i in cutlass.range_constexpr(cute.size(tKKrKK_cpy)):\n if cutlass.const_expr(self.needs_beta):\n _, t = tKKcMkk_cv[i]\n tKKrKK_cvt[i] = self.dtype(\n cutlass.Float32(tKKrKK_cpy[i])\n * cutlass.Float32(sBeta[t, beta_pipe_idx])\n )\n else:\n tKKrKK_cvt[i] = self.dtype(tKKrKK_cpy[i])\n\n tKKsKK2 = thr_store.partition_D(sKK_opd)\n cute.copy(tiled_store, tKKrKK_cvt, tKKsKK2)\n\n # ─── qk_and_kk_epi ───────────────────────────────────────────────────────\n\n @cute.jit\n def qk_and_kk_epi(\n self,\n tQKrQK: cute.Tensor,\n tKKrKK: cute.Tensor,\n tQKcMqk: cute.Tensor,\n tKKcMkk: cute.Tensor,\n sAlpha: cute.Tensor,\n sBeta: cute.Tensor,\n alpha_stage: cutlass.Int32,\n beta_stage: cutlass.Int32,\n is_final_block: bool,\n B: cutlass.Int32,\n scale: cutlass.Float32,\n ):\n if cutlass.const_expr(self.needs_beta):\n beta_row = sBeta[None, beta_stage]\n for i in cutlass.range_constexpr(cute.size(tKKcMkk)):\n s, _ = tKKcMkk[i]\n tKKrKK[i] = tKKrKK[i] * cutlass.Float32(beta_row[s])\n\n if cutlass.const_expr(self.needs_alpha):\n alpha_cumlog = sAlpha[None, AlphaProcessor.CUMSUM_LOG, alpha_stage]\n for i in cutlass.range_constexpr(cute.size(tKKcMkk)):\n # s, t = tKKcMkk[i]\n s, t = tQKcMqk[i]\n alpha = cute.math.exp2(\n cutlass.Float32(alpha_cumlog[s]) - cutlass.Float32(alpha_cumlog[t]),\n fastmath=True,\n )\n tQKrQK[i] = tQKrQK[i] * alpha * scale\n tKKrKK[i] = tKKrKK[i] * alpha\n else:\n for i in cutlass.range_constexpr(cute.size(tQKrQK)):\n tQKrQK[i] = tQKrQK[i] * scale\n\n for i in cutlass.range_constexpr(cute.size(tKKcMkk)):\n # s, t = tKKcMkk[i]\n s, t = tQKcMqk[i]\n pred = s >= t\n tQKrQK[i] = tQKrQK[i] if pred else cutlass.Float32(0.0)\n tKKrKK[i] = tKKrKK[i] if pred else cutlass.Float32(0.0)\n if cutlass.const_expr(is_final_block):\n pred = s < B and t < B\n tQKrQK[i] = tQKrQK[i] if pred else cutlass.Float32(0.0)\n tKKrKK[i] = tKKrKK[i] if pred else cutlass.Float32(0.0)\n\n # ─── qk_store ─────────────────────────────────────────────────────────────\n\n @cute.jit\n def qk_store(\n self,\n tQKrQK: cute.Tensor,\n sQK: cute.Tensor,\n qk_tiled_mma,\n qk_thread_idx: cutlass.Int32,\n ):\n stsm_atom = cute.make_copy_atom(\n warp.StMatrix8x8x16bOp(transpose=False, num_matrices=4), self.dtype\n )\n qk_tiled_copy = cute.make_tiled_copy_C(stsm_atom, qk_tiled_mma)\n qk_thr_copy = qk_tiled_copy.get_slice(qk_thread_idx)\n tQKsQK = qk_thr_copy.partition_D(sQK)\n tQKrQK_cvt = cute.make_fragment_like(tQKrQK, self.dtype)\n tQKrQK_cvt_cv = qk_thr_copy.retile(tQKrQK_cvt)\n for i in cutlass.range_constexpr(cute.size(tQKrQK)):\n tQKrQK_cvt[i] = self.dtype(tQKrQK[i])\n cute.copy(qk_tiled_copy, tQKrQK_cvt_cv, tQKsQK)\n\n # ─── o1_epi ───────────────────────────────────────────────────────────────\n\n @cute.jit\n def o1_epi(\n self,\n tOrO: cute.Tensor,\n tOcO: cute.Tensor,\n sAlpha: cute.Tensor,\n alpha_stage: cutlass.Int32,\n scale: cutlass.Float32,\n ):\n if cutlass.const_expr(self.needs_alpha):\n alpha_cpscale = sAlpha[None, AlphaProcessor.CUMPROD_SCALE, alpha_stage]\n for i in cutlass.range_constexpr(cute.size(tOrO)):\n _, tok_q = tOcO[i]\n tOrO[i] = cutlass.Float32(alpha_cpscale[tok_q]) * tOrO[i]\n else:\n for i in cutlass.range_constexpr(cute.size(tOrO)):\n tOrO[i] = scale * tOrO[i]\n\n # ─── sk_epi ───────────────────────────────────────────────────────────────\n\n @cute.jit\n def sk_epi(\n self,\n tSKrSK: cute.Tensor,\n tSKcSK: cute.Tensor,\n sAlpha: cute.Tensor,\n alpha_stage: cutlass.Int32,\n ):\n if cutlass.const_expr(self.needs_alpha):\n alpha_cp = sAlpha[None, AlphaProcessor.CUMPROD, alpha_stage]\n for i in cutlass.range_constexpr(cute.size(tSKrSK)):\n _, tok_kv = tSKcSK[i]\n tSKrSK[i] = tSKrSK[i] * cutlass.Float32(alpha_cp[tok_kv])\n\n # ─── sk_load_v ────────────────────────────────────────────────────────────\n\n @cute.jit\n def sk_load_v(\n self,\n tSKrSK: cute.Tensor,\n sV_DS: cute.Tensor,\n sk_tiled_copy_C,\n sk_thr_copy_C,\n v_stage: cutlass.Int32,\n ) -> cute.Tensor:\n tSKrV = cute.make_fragment_like(tSKrSK, self.dtype)\n tSKrV_cv = sk_thr_copy_C.retile(tSKrV)\n tSKsV = sk_thr_copy_C.partition_S(sV_DS)\n cute.copy(sk_tiled_copy_C, tSKsV[None, None, None, v_stage], tSKrV_cv)\n return tSKrV\n\n # ─── kv_decay_v ───────────────────────────────────────────────────────────\n\n @cute.jit\n def kv_decay_v(\n self,\n tKVrV: cute.Tensor,\n tKVcV: cute.Tensor,\n sAlpha: cute.Tensor,\n alpha_stage: cutlass.Int32,\n is_final_block: bool,\n B: cutlass.Int32,\n ):\n if cutlass.const_expr(self.needs_alpha):\n alpha_cumlog = sAlpha[None, AlphaProcessor.CUMSUM_LOG, alpha_stage]\n block_log = cutlass.Float32(alpha_cumlog[B - cutlass.Int32(1)])\n for i in cutlass.range_constexpr(cute.size(tKVrV)):\n _, tok = tKVcV[i]\n coeff = cute.math.exp2(\n block_log - cutlass.Float32(alpha_cumlog[tok]), fastmath=True\n )\n if cutlass.const_expr(is_final_block):\n if tok >= B:\n coeff = cutlass.Float32(0.0)\n tKVrV[i] = self.dtype(cutlass.Float32(tKVrV[i]) * coeff)\n else:\n for i in cutlass.range_constexpr(cute.size(tKVrV)):\n _, tok = tKVcV[i]\n if cutlass.const_expr(is_final_block):\n if tok >= B:\n tKVrV[i] = self.dtype(0.0)\n\n # ─── o_store ──────────────────────────────────────────────────────────────\n\n @cute.jit\n def o_store(\n self,\n tOrO: cute.Tensor,\n tOsO: cute.Tensor,\n o_tiled_copy_r2s,\n o_thr_copy_r2s,\n ):\n tOrO_f16 = cute.make_fragment_like(tOrO, self.dtype)\n for i in cutlass.range_constexpr(cute.size(tOrO)):\n tOrO_f16[i] = self.dtype(tOrO[i])\n tOrO_cv = o_thr_copy_r2s.retile(tOrO_f16)\n cute.arch.fence_view_async_shared()\n cute.copy(o_tiled_copy_r2s, tOrO_cv, tOsO)\n cute.arch.fence_view_async_shared()\n\n # ─── TMA load helpers ────────────────────────────────────────────────────\n\n @cute.jit\n def load_qkv_tma(\n self,\n sQ_SD: cute.Tensor,\n sK_DS: cute.Tensor,\n sV_DS: cute.Tensor,\n tma_atom_q: cute.CopyAtom,\n tma_tensor_q: cute.Tensor,\n tma_atom_k: cute.CopyAtom,\n tma_tensor_k: cute.Tensor,\n tma_atom_v: cute.CopyAtom,\n tma_tensor_v: cute.Tensor,\n q_pipeline,\n q_producer_state,\n k_pipeline,\n k_producer_state,\n v_pipeline,\n v_producer_state,\n blk: cutlass.Int32,\n tok_start,\n q_head_idx: cutlass.Int32,\n k_head_idx: cutlass.Int32,\n v_head_idx: cutlass.Int32,\n ):\n blk_tok = tok_start + blk * cutlass.Int32(self.BLK_KV)\n\n sK = sK_DS[None, None, k_producer_state.index]\n mK = cute.domain_offset(\n (cutlass.Int32(0), blk_tok),\n tma_tensor_k[None, None, k_head_idx],\n )\n gK = cute.zipped_divide(mK, (self.D, self.BLK_KV))[\n ((None, None), (cutlass.Int32(0), cutlass.Int32(0)))\n ]\n tKsK, tKgK = cpasync.tma_partition(\n tma_atom_k,\n 0,\n cute.make_layout(1),\n cute.group_modes(sK, 0, 2),\n cute.group_modes(gK, 0, 2),\n )\n k_pipeline.producer_acquire(k_producer_state)\n cute.copy(\n tma_atom_k,\n tKgK,\n tKsK,\n tma_bar_ptr=k_pipeline.producer_get_barrier(k_producer_state),\n )\n k_pipeline.producer_commit(k_producer_state)\n k_producer_state.advance()\n\n sQ = sQ_SD[None, None, q_producer_state.index]\n mQ = cute.domain_offset(\n (blk_tok, cutlass.Int32(0)),\n tma_tensor_q[None, None, q_head_idx],\n )\n gQ = cute.zipped_divide(mQ, (self.BLK_Q, self.D))[\n ((None, None), (cutlass.Int32(0), cutlass.Int32(0)))\n ]\n tQsQ, tQgQ = cpasync.tma_partition(\n tma_atom_q,\n 0,\n cute.make_layout(1),\n cute.group_modes(sQ, 0, 2),\n cute.group_modes(gQ, 0, 2),\n )\n q_pipeline.producer_acquire(q_producer_state)\n cute.copy(\n tma_atom_q,\n tQgQ,\n tQsQ,\n tma_bar_ptr=q_pipeline.producer_get_barrier(q_producer_state),\n )\n q_pipeline.producer_commit(q_producer_state)\n q_producer_state.advance()\n\n sV = sV_DS[None, None, v_producer_state.index]\n mV = cute.domain_offset(\n (cutlass.Int32(0), blk_tok),\n tma_tensor_v[None, None, v_head_idx],\n )\n gV = cute.zipped_divide(mV, (self.D, self.BLK_KV))[\n ((None, None), (cutlass.Int32(0), cutlass.Int32(0)))\n ]\n tVsV, tVgV = cpasync.tma_partition(\n tma_atom_v,\n 0,\n cute.make_layout(1),\n cute.group_modes(sV, 0, 2),\n cute.group_modes(gV, 0, 2),\n )\n v_pipeline.producer_acquire(v_producer_state)\n cute.copy(\n tma_atom_v,\n tVgV,\n tVsV,\n tma_bar_ptr=v_pipeline.producer_get_barrier(v_producer_state),\n )\n v_pipeline.producer_commit(v_producer_state)\n v_producer_state.advance()\n return q_producer_state, k_producer_state, v_producer_state\n\n # ─── load_alpha ───────────────────────────────────────────────────────────\n # Translates FlatMainloopTmaWarpSpecializedDeltaRule::load_alpha (scalar load).\n # Caller must sync before calling AlphaProcessor on the loaded data.\n\n @cute.jit\n def load_alpha(\n self,\n sAlpha: cute.Tensor,\n g_alpha: cute.Tensor,\n blk_tok: cutlass.Int32,\n tok_end,\n sab_head_idx: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n alpha_stage: cutlass.Int32,\n ):\n lane_id = cute.arch.lane_idx()\n sAlpha_k = sAlpha[None, None, alpha_stage]\n num_iters = self.BLK_Q // 32\n for i in cutlass.range_constexpr(num_iters):\n row = cutlass.Int32(i * 32) + lane_id\n tok = blk_tok + row\n if tok < tok_end:\n sAlpha_k[row, AlphaProcessor.CUMSUM_LOG] = g_alpha[\n tok * num_sab_heads + sab_head_idx\n ]\n else:\n sAlpha_k[row, AlphaProcessor.CUMSUM_LOG] = cutlass.Float32(1.0)\n\n # ─── load_beta ────────────────────────────────────────────────────────────\n # Translates FlatMainloopTmaWarpSpecializedDeltaRule::load_beta.\n\n @cute.jit\n def load_beta(\n self,\n sBeta: cute.Tensor,\n g_beta: cute.Tensor,\n blk_tok: cutlass.Int32,\n tok_end,\n sab_head_idx: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n beta_stage: cutlass.Int32,\n ):\n lane_id = cute.arch.lane_idx()\n sBeta_k = sBeta[None, beta_stage]\n num_iters = self.BLK_KV // 32\n for i in cutlass.range_constexpr(num_iters):\n row = cutlass.Int32(i * 32) + lane_id\n tok = blk_tok + row\n if tok < tok_end:\n sBeta_k[row] = g_beta[tok * num_sab_heads + sab_head_idx]\n else:\n sBeta_k[row] = cutlass.Float32(0.0)\n\n # ─── kv_load / kv_store ───────────────────────────────────────────────────\n\n @cute.jit\n def kv_load(\n self,\n tKVrKV: cute.Tensor,\n gKV: cute.Tensor,\n kv_tiled_mma,\n thread_idx: cutlass.Int32,\n ):\n copy_atom_kv = cute.make_copy_atom(\n cute.nvgpu.CopyUniversalOp(), gKV.element_type\n )\n tiled_copy_kv = cute.make_tiled_copy_C(copy_atom_kv, kv_tiled_mma)\n thr_copy_kv = tiled_copy_kv.get_slice(thread_idx)\n tKVgKV = thr_copy_kv.partition_S(select_tensor_10(gKV))\n tKVrKV_storage = cute.make_rmem_tensor_like(tKVrKV, gKV.element_type)\n cute.copy(tiled_copy_kv, tKVgKV, tKVrKV_storage)\n tKVrKV.store(tKVrKV_storage.load().to(self.acc_dtype))\n\n @cute.jit\n def kv_store(\n self,\n tKVrKV: cute.Tensor,\n gKV: cute.Tensor,\n kv_tiled_mma,\n thread_idx: cutlass.Int32,\n ):\n copy_atom_kv = cute.make_copy_atom(\n cute.nvgpu.CopyUniversalOp(), gKV.element_type\n )\n tiled_copy_kv = cute.make_tiled_copy_C(copy_atom_kv, kv_tiled_mma)\n thr_copy_kv = tiled_copy_kv.get_slice(thread_idx)\n tKVgKV = thr_copy_kv.partition_D(select_tensor_10(gKV))\n tKVrKV_storage = cute.make_rmem_tensor_like(tKVrKV, gKV.element_type)\n tKVrKV_storage.store(tKVrKV.load().to(gKV.element_type))\n cute.copy(tiled_copy_kv, tKVrKV_storage, tKVgKV)\n\n @cute.jit\n def maybe_store_checkpoint(\n self,\n tKVrKV: cute.Tensor,\n g_state_checkpoints: cute.Tensor,\n checkpoint_cu_starts: cute.Tensor,\n checkpoint_every_n_tokens: cutlass.Int32,\n kv_tiled_mma,\n thread_idx: cutlass.Int32,\n seq_idx: cutlass.Int32,\n o_head_idx: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n total_checkpoints: cutlass.Int32,\n block_end: cutlass.Int32,\n seq_len: cutlass.Int32,\n ):\n if cutlass.const_expr(self.needs_checkpointing):\n if (\n block_end <= seq_len\n and block_end % checkpoint_every_n_tokens == cutlass.Int32(0)\n ):\n checkpoint_idx = (\n cutlass.Int32(checkpoint_cu_starts[seq_idx])\n + block_end // checkpoint_every_n_tokens\n - cutlass.Int32(1)\n )\n checkpoint_layout = cute.make_ordered_layout(\n (self.D, self.D, num_sab_heads, total_checkpoints),\n order=(0, 1, 2, 3),\n )\n mCheckpoint = cute.make_tensor(\n g_state_checkpoints.iterator, checkpoint_layout\n )\n gCheckpointKV = mCheckpoint[None, None, o_head_idx, checkpoint_idx]\n self.kv_store(tKVrKV, gCheckpointKV, kv_tiled_mma, thread_idx)\n\n # ─── compute_loop_body ───────────────────────────────────────────────────\n # Translates the C++ compute_loop_body lambda captured inside compute().\n # Called by Math WGs (tidx >= 128) for one block iteration.\n\n @cute.jit\n def compute_loop_body(\n self,\n # Smem tensors (staged; caller indexes the active stage)\n sQ_SD: cute.Tensor, # (BlkQ, D, StagesQ) – row-major atom, swizzled\n sK_SD: cute.Tensor, # (BlkKV, D, StagesK) – same atom\n sK_DS: cute.Tensor, # (D, BlkKV, StagesK) – K transposed\n sV_DS: cute.Tensor, # (D, BlkKV, StagesV) – V transposed\n sQK: cute.Tensor, # (BlkQ, BlkKV, StagesQK)\n sKK_inv: cute.Tensor, # (BlkKV, BlkKV, StagesKK)\n sKK_opd: cute.Tensor, # sKK_inv storage recast as Element\n sO: cute.Tensor, # O output smem (staged)\n sAlpha: cute.Tensor, # (BlkQ, AlphaProcessor.NUM_CHANNELS, StagesAlpha) or zero-shaped\n kv_tiled_mma,\n # Mainloop pipelines and active read states\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n v_pipeline,\n v_consumer_state,\n o_pipeline,\n o_producer_state,\n qk_pipeline,\n qk_consumer_state,\n kk_pipeline,\n kk_consumer_state,\n alpha_pipeline,\n alpha_consumer_state,\n # Compile-time flags\n is_first_block: bool,\n is_final_block: bool,\n # Valid token count for masking on final block\n B: cutlass.Int32,\n # Running KV state (D×D fp32, in registers across all blocks)\n tKVrKV: cute.Tensor,\n # Scale factor\n scale: cutlass.Float32,\n # WG role: MathWarpGroupRole.STATE0 or MathWarpGroupRole.STATE1.\n wg_idx: cutlass.Int32,\n ):\n tidx, _, _ = cute.arch.thread_idx()\n thread_idx = tidx - cutlass.Int32(128) # relative to compute threads\n # ── TiledMMAs ─────────────────────────────────────────────────────────\n blk_q = cute.size(sQ_SD, mode=[0])\n blk_kv = cute.size(sK_SD, mode=[0])\n d = cute.size(sQ_SD, mode=[1])\n mma_atom_o1 = cute.make_mma_atom(\n warpgroup.MmaF16BF16Op(\n self.dtype,\n self.acc_dtype,\n (64, blk_q, 16),\n warpgroup.OperandSource.RMEM,\n cute.nvgpu.OperandMajorMode.K,\n cute.nvgpu.OperandMajorMode.K,\n )\n )\n mma_atom_o2 = cute.make_mma_atom(\n warpgroup.MmaF16BF16Op(\n self.dtype,\n self.acc_dtype,\n (64, blk_q, 16),\n warpgroup.OperandSource.RMEM,\n cute.nvgpu.OperandMajorMode.K,\n cute.nvgpu.OperandMajorMode.K,\n )\n )\n mma_atom_sk = cute.make_mma_atom(\n warpgroup.MmaF16BF16Op(\n self.dtype,\n self.acc_dtype,\n (64, blk_kv, 16),\n warpgroup.OperandSource.RMEM,\n cute.nvgpu.OperandMajorMode.K,\n cute.nvgpu.OperandMajorMode.K,\n )\n )\n mma_atom_newv = cute.make_mma_atom(\n warpgroup.MmaF16BF16Op(\n self.dtype,\n self.acc_dtype,\n (64, blk_kv, 16),\n warpgroup.OperandSource.RMEM,\n cute.nvgpu.OperandMajorMode.K,\n cute.nvgpu.OperandMajorMode.K,\n )\n )\n\n # O1/O2/SK/NewV: two state warpgroups cooperate as in the C++ Hopper GMMA path.\n o1_tiled_mma = cute.make_tiled_mma(mma_atom_o1, cute.make_layout((2, 1, 1)))\n o2_tiled_mma = cute.make_tiled_mma(mma_atom_o2, cute.make_layout((2, 1, 1)))\n sk_tiled_mma = cute.make_tiled_mma(mma_atom_sk, cute.make_layout((2, 1, 1)))\n newv_tiled_mma = cute.make_tiled_mma(mma_atom_newv, cute.make_layout((2, 1, 1)))\n\n # ── Thread slices ─────────────────────────────────────────────────────\n sk_thr_mma = sk_tiled_mma.get_slice(thread_idx)\n newv_thr_mma = newv_tiled_mma.get_slice(thread_idx)\n o1_thr_mma = o1_tiled_mma.get_slice(thread_idx)\n o2_thr_mma = o2_tiled_mma.get_slice(thread_idx)\n kv_thr_mma = kv_tiled_mma.get_slice(thread_idx)\n\n # ── Copy atoms ────────────────────────────────────────────────────────\n ldsm_t4 = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(transpose=True, num_matrices=4), self.dtype\n )\n\n # ── SK copies ─────────────────────────────────────────────────────────\n # SK C: V loaded from sV_DS (col-major D×BlkKV) with LDSM_T.\n sk_tiled_copy_C = cute.make_tiled_copy_C(ldsm_t4, sk_tiled_mma)\n sk_thr_copy_C = sk_tiled_copy_C.get_slice(thread_idx)\n tSKsK = sk_thr_mma.partition_B(sK_SD)\n tSKrK = sk_thr_mma.make_fragment_B(tSKsK)\n\n # ── NewV copies ───────────────────────────────────────────────────────\n tNewVsB = newv_thr_mma.partition_B(sKK_opd)\n tNewVrB = newv_thr_mma.make_fragment_B(tNewVsB)\n\n # ── KV copies ─────────────────────────────────────────────────────────\n tKVsK = kv_thr_mma.partition_B(sK_DS)\n tKVrK = kv_thr_mma.make_fragment_B(tKVsK)\n\n # ── O1/O2 copies ──────────────────────────────────────────────────────\n tOsQ = o1_thr_mma.partition_B(sQ_SD)\n tOrQ = o1_thr_mma.make_fragment_B(tOsQ)\n tOsQK = o2_thr_mma.partition_B(sQK)\n tOrQK = o2_thr_mma.make_fragment_B(tOsQK)\n\n # ── O store (R→S STSM) ────────────────────────────────────────────────\n o_stsm = cute.make_copy_atom(\n warp.StMatrix8x8x16bOp(transpose=True, num_matrices=4), self.dtype\n )\n o_tiled_copy_r2s = cute.make_tiled_copy_C(o_stsm, o1_tiled_mma)\n o_thr_copy_r2s = o_tiled_copy_r2s.get_slice(thread_idx)\n tOsO = o_thr_copy_r2s.partition_D(sO)\n\n # ── Coordinate tensors for masking / alpha/beta indexing ──────────────\n cO = cute.make_identity_tensor((d, blk_q))\n tOcO = o1_thr_mma.partition_C(cO)\n cSK = cute.make_identity_tensor((d, blk_kv))\n tSKcSK = sk_thr_mma.partition_C(cSK)\n cV = cute.make_identity_tensor((d, blk_kv))\n tKVcV = kv_thr_mma.partition_A(cV)\n\n # ── O1: KV_state @ Q (both state WGs, skip on first block) ───────────\n q_pipeline.consumer_wait(q_consumer_state)\n if cutlass.const_expr(self.needs_alpha):\n alpha_pipeline.consumer_wait(alpha_consumer_state)\n cute.arch.fence_view_async_shared()\n tOrO = o1_thr_mma.make_fragment_C(o1_thr_mma.partition_shape_C((d, blk_q)))\n if cutlass.const_expr(not is_first_block):\n tOrKV = SM90.make_acc_into_op(tKVrKV, o1_tiled_mma, self.dtype)\n SM90.warpgroup_fence_operand(tOrKV)\n SM90.warpgroup_fence_operand(tOrO)\n cute.nvgpu.warpgroup.fence()\n self._math_order_wait(wg_idx)\n SM90.wgmma_gemm_zero_acc(\n o1_tiled_mma,\n tOrO,\n tOrKV,\n tOrQ[None, None, None, q_consumer_state.index],\n )\n cute.nvgpu.warpgroup.commit_group()\n self._math_order_notify(wg_idx)\n cute.nvgpu.warpgroup.wait_group(0)\n self.o1_epi(tOrO, tOcO, sAlpha, alpha_consumer_state.index, scale)\n q_pipeline.consumer_release(q_consumer_state)\n q_consumer_state.advance()\n\n # ── SK: KV_state @ K^T (result negated below via V - SK) ─────────────\n k_pipeline.consumer_wait(k_consumer_state)\n tSKrSK = sk_thr_mma.make_fragment_C(sk_thr_mma.partition_shape_C((d, blk_kv)))\n if cutlass.const_expr(not is_first_block):\n tSKrS = SM90.make_acc_into_op(tKVrKV, sk_tiled_mma, self.dtype)\n SM90.warpgroup_fence_operand(tSKrSK)\n SM90.warpgroup_fence_operand(tSKrS)\n cute.nvgpu.warpgroup.fence()\n self._math_order_wait(wg_idx)\n SM90.wgmma_gemm_zero_acc(\n sk_tiled_mma,\n tSKrSK,\n tSKrS,\n tSKrK[None, None, None, k_consumer_state.index],\n )\n cute.nvgpu.warpgroup.commit_group()\n self._math_order_notify(wg_idx)\n cute.nvgpu.warpgroup.wait_group(0)\n\n # ── Load V from smem ──────────────────────────────────────────────────\n v_pipeline.consumer_wait(v_consumer_state)\n tSKrV = self.sk_load_v(\n tSKrSK,\n sV_DS,\n sk_tiled_copy_C,\n sk_thr_copy_C,\n v_consumer_state.index,\n )\n\n # sk_epi + V - SK (SK=0 on first block, so V - SK = V)\n if cutlass.const_expr(not is_first_block):\n self.sk_epi(tSKrSK, tSKcSK, sAlpha, alpha_consumer_state.index)\n for i in cutlass.range_constexpr(cute.size(tSKrV)):\n tSKrV[i] = tSKrV[i] - self.dtype(tSKrSK[i])\n\n # ── NewV = (V - SK) @ T^T (ordered: WG0 first) ──────────────────────\n tNewVrA = SM90.make_acc_into_op(tSKrV, newv_tiled_mma, self.dtype)\n tNewVrC = newv_thr_mma.make_fragment_C(\n newv_thr_mma.partition_shape_C((d, blk_kv))\n )\n kk_pipeline.consumer_wait(kk_consumer_state)\n SM90.warpgroup_fence_operand(tNewVrA)\n SM90.warpgroup_fence_operand(tNewVrC)\n cute.nvgpu.warpgroup.fence()\n self._math_order_wait(wg_idx)\n SM90.wgmma_gemm_zero_acc(\n newv_tiled_mma,\n tNewVrC,\n tNewVrA,\n tNewVrB[None, None, None, kk_consumer_state.index],\n )\n cute.nvgpu.warpgroup.commit_group()\n self._math_order_notify(wg_idx)\n cute.nvgpu.warpgroup.wait_group(0)\n v_pipeline.consumer_release(v_consumer_state)\n v_consumer_state.advance()\n kk_pipeline.consumer_release(kk_consumer_state)\n kk_consumer_state.advance()\n\n # ── O2 = O1 + NewV @ QK (ordered: WG0 first) ────────────────────────\n tOrV_or_tKVrV = SM90.make_acc_into_op(tNewVrC, kv_tiled_mma, self.dtype)\n qk_pipeline.consumer_wait(qk_consumer_state)\n SM90.warpgroup_fence_operand(tOrV_or_tKVrV)\n SM90.warpgroup_fence_operand(tOrO)\n cute.nvgpu.warpgroup.fence()\n self._math_order_wait(wg_idx)\n SM90.wgmma_gemm(\n o2_tiled_mma,\n tOrO,\n tOrV_or_tKVrV,\n tOrQK[None, None, None, qk_consumer_state.index],\n not is_first_block,\n )\n cute.nvgpu.warpgroup.commit_group()\n self._math_order_notify(wg_idx)\n cute.nvgpu.warpgroup.wait_group(0)\n qk_pipeline.consumer_release(qk_consumer_state)\n qk_consumer_state.advance()\n\n # ── O store to smem ───────────────────────────────────────────────────\n o_pipeline.producer_acquire(o_producer_state)\n self.o_store(\n tOrO,\n tOsO[None, None, None, o_producer_state.index],\n o_tiled_copy_r2s,\n o_thr_copy_r2s,\n )\n o_pipeline.producer_commit(o_producer_state)\n o_producer_state.advance()\n\n # ── KV state update ───────────────────────────────────────────────────\n block_coeff = cutlass.Float32(1.0)\n if cutlass.const_expr(self.needs_alpha):\n block_coeff = cutlass.Float32(\n sAlpha[\n B - cutlass.Int32(1),\n AlphaProcessor.CUMPROD,\n alpha_consumer_state.index,\n ]\n )\n\n for i in cutlass.range(cute.size(tKVrKV), unroll_full=True):\n tKVrKV[i] = block_coeff * tKVrKV[i]\n\n self.kv_decay_v(\n tOrV_or_tKVrV, tKVcV, sAlpha, alpha_consumer_state.index, is_final_block, B\n )\n\n # KV += NewV @ K\n SM90.warpgroup_fence_operand(tOrV_or_tKVrV)\n SM90.warpgroup_fence_operand(tKVrKV)\n cute.nvgpu.warpgroup.fence()\n self._math_order_wait(wg_idx)\n SM90.wgmma_gemm(\n kv_tiled_mma,\n tKVrKV,\n tOrV_or_tKVrV,\n tKVrK[None, None, None, k_consumer_state.index],\n True,\n )\n cute.nvgpu.warpgroup.commit_group()\n self._math_order_notify(wg_idx)\n cute.nvgpu.warpgroup.wait_group(0)\n k_pipeline.consumer_release(k_consumer_state)\n k_consumer_state.advance()\n if cutlass.const_expr(self.needs_alpha):\n alpha_pipeline.consumer_release(alpha_consumer_state)\n alpha_consumer_state.advance()\n return (\n q_consumer_state,\n k_consumer_state,\n v_consumer_state,\n o_producer_state,\n qk_consumer_state,\n kk_consumer_state,\n alpha_consumer_state,\n )\n\n # ─── Warp role entry points ──────────────────────────────────────────────\n # The current DSL bridge still uses CTA-wide sync epochs, but each role owns\n # its own loop, matching the C++ warp-specialized dispatch shape.\n\n @cute.jit\n def run_load_qkv_role(\n self,\n sQ_SD: cute.Tensor,\n sK_DS: cute.Tensor,\n sV_DS: cute.Tensor,\n tma_atom_q: cute.CopyAtom,\n tma_tensor_q: cute.Tensor,\n tma_atom_k: cute.CopyAtom,\n tma_tensor_k: cute.Tensor,\n tma_atom_v: cute.CopyAtom,\n tma_tensor_v: cute.Tensor,\n q_pipeline,\n k_pipeline,\n v_pipeline,\n num_blocks: cutlass.Int32,\n tok_start,\n q_head_idx: cutlass.Int32,\n k_head_idx: cutlass.Int32,\n v_head_idx: cutlass.Int32,\n ):\n q_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.q_stage\n )\n k_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.k_stage\n )\n v_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.v_stage\n )\n for blk in cutlass.range(num_blocks, unroll=1):\n (\n q_producer_state,\n k_producer_state,\n v_producer_state,\n ) = self.load_qkv_tma(\n sQ_SD,\n sK_DS,\n sV_DS,\n tma_atom_q,\n tma_tensor_q,\n tma_atom_k,\n tma_tensor_k,\n tma_atom_v,\n tma_tensor_v,\n q_pipeline,\n q_producer_state,\n k_pipeline,\n k_producer_state,\n v_pipeline,\n v_producer_state,\n blk,\n tok_start,\n q_head_idx,\n k_head_idx,\n v_head_idx,\n )\n\n @cute.jit\n def run_load_alpha_role(\n self,\n sAlpha: cute.Tensor,\n g_alpha: cute.Tensor,\n alpha_pipeline,\n scale: cutlass.Float32,\n num_blocks: cutlass.Int32,\n tok_start,\n tok_end,\n sab_head_idx: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n ):\n alpha_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.alpha_beta_stage\n )\n for blk in cutlass.range(num_blocks, unroll=1):\n blk_tok = tok_start + blk * cutlass.Int32(self.BLK_Q)\n if cutlass.const_expr(self.needs_alpha):\n alpha_pipeline.producer_acquire(alpha_producer_state)\n cute.arch.fence_view_async_shared()\n self.load_alpha(\n sAlpha,\n g_alpha,\n blk_tok,\n tok_end,\n sab_head_idx,\n num_sab_heads,\n alpha_producer_state.index,\n )\n AlphaProcessor().run(\n sAlpha[None, None, alpha_producer_state.index], scale\n )\n cute.arch.fence_view_async_shared()\n alpha_pipeline.producer_commit(alpha_producer_state)\n alpha_producer_state.advance()\n\n @cute.jit\n def run_load_beta_role(\n self,\n sBeta: cute.Tensor,\n g_beta: cute.Tensor,\n beta_pipeline,\n num_blocks: cutlass.Int32,\n tok_start,\n tok_end,\n sab_head_idx: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n ):\n beta_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.alpha_beta_stage\n )\n for blk in cutlass.range(num_blocks, unroll=1):\n blk_tok = tok_start + blk * cutlass.Int32(self.BLK_KV)\n if cutlass.const_expr(self.needs_beta):\n beta_pipeline.producer_acquire(beta_producer_state)\n cute.arch.fence_view_async_shared()\n self.load_beta(\n sBeta,\n g_beta,\n blk_tok,\n tok_end,\n sab_head_idx,\n num_sab_heads,\n beta_producer_state.index,\n )\n cute.arch.fence_view_async_shared()\n beta_pipeline.producer_commit(beta_producer_state)\n beta_producer_state.advance()\n\n @cute.jit\n def run_state_math_role(\n self,\n sQ_SD: cute.Tensor,\n sK_SD: cute.Tensor,\n sK_DS: cute.Tensor,\n sV_DS: cute.Tensor,\n sQK: cute.Tensor,\n sKK_inv: cute.Tensor,\n sKK_opd: cute.Tensor,\n sO: cute.Tensor,\n sAlpha: cute.Tensor,\n q_pipeline,\n k_pipeline,\n v_pipeline,\n o_pipeline,\n qk_pipeline,\n kk_pipeline,\n alpha_pipeline,\n g_state: cute.Tensor,\n g_init_state: cute.Tensor,\n g_state_indices: cute.Tensor,\n g_state_checkpoints: cute.Tensor,\n checkpoint_cu_starts: cute.Tensor,\n work_desc: WorkDesc,\n scale: cutlass.Float32,\n wg_idx: cutlass.Int32,\n math_tidx: cutlass.Int32,\n num_blocks: cutlass.Int32,\n num_q_heads: cutlass.Int32,\n num_v_heads: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n num_seqs: cutlass.Int32,\n total_checkpoints: cutlass.Int32,\n checkpoint_every_n_tokens: cutlass.Int32,\n ):\n self._math_order_init(wg_idx)\n q_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.q_stage\n )\n k_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.k_stage\n )\n v_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.v_stage\n )\n o_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.o_stage\n )\n qk_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.qk_stage\n )\n kk_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.kk_stage\n )\n alpha_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.alpha_beta_stage\n )\n\n kv_tiled_mma = cute.make_tiled_mma(\n cute.make_mma_atom(\n warpgroup.MmaF16BF16Op(\n self.dtype,\n self.acc_dtype,\n (64, self.D, 16),\n warpgroup.OperandSource.RMEM,\n cute.nvgpu.OperandMajorMode.K,\n cute.nvgpu.OperandMajorMode.MN,\n )\n ),\n cute.make_layout((2, 1, 1)),\n )\n kv_thr_mma = kv_tiled_mma.get_slice(math_tidx)\n tKVrKV = kv_thr_mma.make_fragment_C(\n kv_thr_mma.partition_shape_C((self.D, self.D))\n )\n tKVrKV.fill(self.acc_dtype(0.0))\n\n packed_state_layout = cute.make_ordered_layout(\n (self.D, self.D, num_sab_heads, num_seqs), order=(0, 1, 2, 3)\n )\n state_ref_shape = (g_state.shape[0], g_state.shape[1], self.D, self.D)\n state_ref_layout = cute.make_layout(state_ref_shape, stride=g_state.stride)\n indexed_state_layout = cute.select(state_ref_layout, mode=[3, 2, 1, 0])\n state_idx = work_desc.seq_idx\n if cutlass.const_expr(self.use_state_indices):\n state_idx = cutlass.Int32(g_state_indices[work_desc.seq_idx])\n state_layout = indexed_state_layout\n else:\n state_layout = packed_state_layout\n o_head_idx = work_desc.o_head_idx(num_q_heads, num_v_heads)\n mState = cute.make_tensor(g_state.iterator, state_layout)\n gStateKV = mState[None, None, o_head_idx, state_idx]\n if cutlass.const_expr(self.needs_init_state):\n init_state_ref_layout = cute.make_layout(\n state_ref_shape, stride=g_init_state.stride\n )\n indexed_init_state_layout = cute.select(\n init_state_ref_layout, mode=[3, 2, 1, 0]\n )\n if cutlass.const_expr(self.use_state_indices):\n init_state_layout = indexed_init_state_layout\n else:\n init_state_layout = packed_state_layout\n mInitState = cute.make_tensor(g_init_state.iterator, init_state_layout)\n gInitKV = mInitState[None, None, o_head_idx, state_idx]\n self.kv_load(tKVrKV, gInitKV, kv_tiled_mma, math_tidx)\n\n first_B = work_desc.seq_len\n if first_B > cutlass.Int32(self.BLK_KV):\n first_B = cutlass.Int32(self.BLK_KV)\n if cutlass.const_expr(self.needs_init_state):\n (\n q_consumer_state,\n k_consumer_state,\n v_consumer_state,\n o_producer_state,\n qk_consumer_state,\n kk_consumer_state,\n alpha_consumer_state,\n ) = self.compute_loop_body(\n sQ_SD,\n sK_SD,\n sK_DS,\n sV_DS,\n sQK,\n sKK_inv,\n sKK_opd,\n sO,\n sAlpha,\n kv_tiled_mma,\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n v_pipeline,\n v_consumer_state,\n o_pipeline,\n o_producer_state,\n qk_pipeline,\n qk_consumer_state,\n kk_pipeline,\n kk_consumer_state,\n alpha_pipeline,\n alpha_consumer_state,\n False,\n True,\n first_B,\n tKVrKV,\n scale,\n wg_idx,\n )\n else:\n (\n q_consumer_state,\n k_consumer_state,\n v_consumer_state,\n o_producer_state,\n qk_consumer_state,\n kk_consumer_state,\n alpha_consumer_state,\n ) = self.compute_loop_body(\n sQ_SD,\n sK_SD,\n sK_DS,\n sV_DS,\n sQK,\n sKK_inv,\n sKK_opd,\n sO,\n sAlpha,\n kv_tiled_mma,\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n v_pipeline,\n v_consumer_state,\n o_pipeline,\n o_producer_state,\n qk_pipeline,\n qk_consumer_state,\n kk_pipeline,\n kk_consumer_state,\n alpha_pipeline,\n alpha_consumer_state,\n True,\n True,\n first_B,\n tKVrKV,\n scale,\n wg_idx,\n )\n self.maybe_store_checkpoint(\n tKVrKV,\n g_state_checkpoints,\n checkpoint_cu_starts,\n checkpoint_every_n_tokens,\n kv_tiled_mma,\n math_tidx,\n work_desc.seq_idx,\n o_head_idx,\n num_sab_heads,\n total_checkpoints,\n cutlass.Int32(self.BLK_KV),\n work_desc.seq_len,\n )\n\n for blk in cutlass.range(\n cutlass.Int32(1), num_blocks - cutlass.Int32(1), cutlass.Int32(1), unroll=1\n ):\n (\n q_consumer_state,\n k_consumer_state,\n v_consumer_state,\n o_producer_state,\n qk_consumer_state,\n kk_consumer_state,\n alpha_consumer_state,\n ) = self.compute_loop_body(\n sQ_SD,\n sK_SD,\n sK_DS,\n sV_DS,\n sQK,\n sKK_inv,\n sKK_opd,\n sO,\n sAlpha,\n kv_tiled_mma,\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n v_pipeline,\n v_consumer_state,\n o_pipeline,\n o_producer_state,\n qk_pipeline,\n qk_consumer_state,\n kk_pipeline,\n kk_consumer_state,\n alpha_pipeline,\n alpha_consumer_state,\n False,\n False,\n cutlass.Int32(self.BLK_KV),\n tKVrKV,\n scale,\n wg_idx,\n )\n self.maybe_store_checkpoint(\n tKVrKV,\n g_state_checkpoints,\n checkpoint_cu_starts,\n checkpoint_every_n_tokens,\n kv_tiled_mma,\n math_tidx,\n work_desc.seq_idx,\n o_head_idx,\n num_sab_heads,\n total_checkpoints,\n (blk + cutlass.Int32(1)) * cutlass.Int32(self.BLK_KV),\n work_desc.seq_len,\n )\n\n if num_blocks != cutlass.Int32(1):\n last_blk = num_blocks - cutlass.Int32(1)\n last_B = work_desc.seq_len - last_blk * cutlass.Int32(self.BLK_KV)\n (\n q_consumer_state,\n k_consumer_state,\n v_consumer_state,\n o_producer_state,\n qk_consumer_state,\n kk_consumer_state,\n alpha_consumer_state,\n ) = self.compute_loop_body(\n sQ_SD,\n sK_SD,\n sK_DS,\n sV_DS,\n sQK,\n sKK_inv,\n sKK_opd,\n sO,\n sAlpha,\n kv_tiled_mma,\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n v_pipeline,\n v_consumer_state,\n o_pipeline,\n o_producer_state,\n qk_pipeline,\n qk_consumer_state,\n kk_pipeline,\n kk_consumer_state,\n alpha_pipeline,\n alpha_consumer_state,\n False,\n True,\n last_B,\n tKVrKV,\n scale,\n wg_idx,\n )\n self.maybe_store_checkpoint(\n tKVrKV,\n g_state_checkpoints,\n checkpoint_cu_starts,\n checkpoint_every_n_tokens,\n kv_tiled_mma,\n math_tidx,\n work_desc.seq_idx,\n o_head_idx,\n num_sab_heads,\n total_checkpoints,\n (last_blk + cutlass.Int32(1)) * cutlass.Int32(self.BLK_KV),\n work_desc.seq_len,\n )\n self.kv_store(tKVrKV, gStateKV, kv_tiled_mma, math_tidx)\n\n @cute.jit\n def run_aux_loop_body(\n self,\n sQK: cute.Tensor,\n sKK_inv: cute.Tensor,\n sKK_opd: cute.Tensor,\n sAlpha: cute.Tensor,\n sBeta: cute.Tensor,\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n qk_pipeline,\n qk_producer_state,\n kk_pipeline,\n kk_producer_state,\n alpha_pipeline,\n alpha_consumer_state,\n beta_pipeline,\n beta_consumer_state,\n work_desc: WorkDesc,\n scale: cutlass.Float32,\n blk: cutlass.Int32,\n is_final_block: bool,\n qk_tiled_mma,\n kk_tiled_mma,\n tQKrQ: cute.Tensor,\n tQKrK: cute.Tensor,\n tKKrA: cute.Tensor,\n tKKrB: cute.Tensor,\n tQKcMqk: cute.Tensor,\n tKKcMkk: cute.Tensor,\n aux_tidx: cutlass.Int32,\n ):\n B = cutlass.Int32(self.BLK_KV)\n if cutlass.const_expr(is_final_block):\n B = work_desc.seq_len - blk * cutlass.Int32(self.BLK_KV)\n\n k_pipeline.consumer_wait(k_consumer_state)\n\n tKKrKK = kk_tiled_mma.get_slice(aux_tidx).make_fragment_C(\n kk_tiled_mma.get_slice(aux_tidx).partition_shape_C(\n (self.BLK_KV, self.BLK_KV)\n )\n )\n cute.nvgpu.warpgroup.fence()\n SM90.wgmma_gemm_zero_acc(\n kk_tiled_mma,\n tKKrKK,\n tKKrA[None, None, None, k_consumer_state.index],\n tKKrB[None, None, None, k_consumer_state.index],\n )\n cute.nvgpu.warpgroup.commit_group()\n\n q_pipeline.consumer_wait(q_consumer_state)\n tQKrQK = qk_tiled_mma.get_slice(aux_tidx).make_fragment_C(\n qk_tiled_mma.get_slice(aux_tidx).partition_shape_C(\n (self.BLK_Q, self.BLK_KV)\n )\n )\n cute.nvgpu.warpgroup.fence()\n SM90.wgmma_gemm_zero_acc(\n qk_tiled_mma,\n tQKrQK,\n tQKrQ[None, None, None, q_consumer_state.index],\n tQKrK[None, None, None, k_consumer_state.index],\n )\n cute.nvgpu.warpgroup.commit_group()\n cute.nvgpu.warpgroup.wait_group(0)\n\n k_pipeline.consumer_release(k_consumer_state)\n k_consumer_state.advance()\n q_pipeline.consumer_release(q_consumer_state)\n q_consumer_state.advance()\n\n if cutlass.const_expr(self.needs_alpha):\n alpha_pipeline.consumer_wait(alpha_consumer_state)\n if cutlass.const_expr(self.needs_beta):\n beta_pipeline.consumer_wait(beta_consumer_state)\n cute.arch.fence_view_async_shared()\n\n self.qk_and_kk_epi(\n tQKrQK,\n tKKrKK,\n tQKcMqk,\n tKKcMkk,\n sAlpha,\n sBeta,\n alpha_consumer_state.index,\n beta_consumer_state.index,\n is_final_block,\n B,\n scale,\n )\n\n kk_pipeline.producer_acquire(kk_producer_state)\n self._kk_store_and_inv(\n tKKrKK,\n kk_tiled_mma,\n aux_tidx,\n sKK_inv[None, None, kk_producer_state.index],\n sKK_opd[None, None, kk_producer_state.index],\n sBeta,\n beta_consumer_state.index,\n tKKcMkk,\n )\n cute.arch.fence_view_async_shared()\n kk_pipeline.producer_commit(kk_producer_state)\n kk_producer_state.advance()\n\n qk_pipeline.producer_acquire(qk_producer_state)\n self.qk_store(\n tQKrQK,\n sQK[None, None, qk_producer_state.index],\n qk_tiled_mma,\n aux_tidx,\n )\n cute.arch.fence_view_async_shared()\n qk_pipeline.producer_commit(qk_producer_state)\n qk_producer_state.advance()\n\n if cutlass.const_expr(self.needs_alpha):\n alpha_pipeline.consumer_release(alpha_consumer_state)\n alpha_consumer_state.advance()\n if cutlass.const_expr(self.needs_beta):\n beta_pipeline.consumer_release(beta_consumer_state)\n beta_consumer_state.advance()\n\n return (\n q_consumer_state,\n k_consumer_state,\n qk_producer_state,\n kk_producer_state,\n alpha_consumer_state,\n beta_consumer_state,\n )\n\n @cute.jit\n def run_aux_math_role(\n self,\n sQ_SD: cute.Tensor,\n sK_SD: cute.Tensor,\n sQK: cute.Tensor,\n sKK_inv: cute.Tensor,\n sKK_opd: cute.Tensor,\n sAlpha: cute.Tensor,\n sBeta: cute.Tensor,\n q_pipeline,\n k_pipeline,\n qk_pipeline,\n kk_pipeline,\n alpha_pipeline,\n beta_pipeline,\n work_desc: WorkDesc,\n scale: cutlass.Float32,\n math_tidx: cutlass.Int32,\n num_blocks: cutlass.Int32,\n ):\n aux_tidx = math_tidx % cutlass.Int32(128)\n\n qk_tiled_mma = cute.make_tiled_mma(\n cute.make_mma_atom(\n warpgroup.MmaF16BF16Op(\n self.dtype,\n self.acc_dtype,\n (self.BLK_Q, self.BLK_KV, 16),\n warpgroup.OperandSource.SMEM,\n cute.nvgpu.OperandMajorMode.K,\n cute.nvgpu.OperandMajorMode.K,\n )\n ),\n cute.make_layout((1, 1, 1)),\n )\n kk_tiled_mma = cute.make_tiled_mma(\n cute.make_mma_atom(\n warpgroup.MmaF16BF16Op(\n self.dtype,\n self.acc_dtype,\n (self.BLK_KV, self.BLK_KV, 16),\n warpgroup.OperandSource.SMEM,\n cute.nvgpu.OperandMajorMode.K,\n cute.nvgpu.OperandMajorMode.K,\n )\n ),\n cute.make_layout((1, 1, 1)),\n )\n\n qk_thr_mma = qk_tiled_mma.get_slice(aux_tidx)\n kk_thr_mma = kk_tiled_mma.get_slice(aux_tidx)\n\n tQKsQ = qk_thr_mma.partition_A(sQ_SD)\n tQKsK = qk_thr_mma.partition_B(sK_SD)\n tQKrQ = qk_thr_mma.make_fragment_A(tQKsQ)\n tQKrK = qk_thr_mma.make_fragment_B(tQKsK)\n\n tKKsA = kk_thr_mma.partition_A(sK_SD)\n tKKsB = kk_thr_mma.partition_B(sK_SD)\n tKKrA = kk_thr_mma.make_fragment_A(tKKsA)\n tKKrB = kk_thr_mma.make_fragment_B(tKKsB)\n\n cMqk = cute.make_identity_tensor((self.BLK_Q, self.BLK_KV))\n tQKcMqk = qk_thr_mma.partition_C(cMqk)\n tKKcMkk = kk_thr_mma.partition_C(cMqk)\n\n q_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.q_stage\n )\n k_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.k_stage\n )\n qk_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.qk_stage\n )\n kk_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.kk_stage\n )\n alpha_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.alpha_beta_stage\n )\n beta_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.alpha_beta_stage\n )\n\n for blk in cutlass.range(num_blocks - cutlass.Int32(1), unroll=1):\n (\n q_consumer_state,\n k_consumer_state,\n qk_producer_state,\n kk_producer_state,\n alpha_consumer_state,\n beta_consumer_state,\n ) = self.run_aux_loop_body(\n sQK,\n sKK_inv,\n sKK_opd,\n sAlpha,\n sBeta,\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n qk_pipeline,\n qk_producer_state,\n kk_pipeline,\n kk_producer_state,\n alpha_pipeline,\n alpha_consumer_state,\n beta_pipeline,\n beta_consumer_state,\n work_desc,\n scale,\n blk,\n False,\n qk_tiled_mma,\n kk_tiled_mma,\n tQKrQ,\n tQKrK,\n tKKrA,\n tKKrB,\n tQKcMqk,\n tKKcMkk,\n aux_tidx,\n )\n\n last_blk = num_blocks - cutlass.Int32(1)\n (\n q_consumer_state,\n k_consumer_state,\n qk_producer_state,\n kk_producer_state,\n alpha_consumer_state,\n beta_consumer_state,\n ) = self.run_aux_loop_body(\n sQK,\n sKK_inv,\n sKK_opd,\n sAlpha,\n sBeta,\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n qk_pipeline,\n qk_producer_state,\n kk_pipeline,\n kk_producer_state,\n alpha_pipeline,\n alpha_consumer_state,\n beta_pipeline,\n beta_consumer_state,\n work_desc,\n scale,\n last_blk,\n True,\n qk_tiled_mma,\n kk_tiled_mma,\n tQKrQ,\n tQKrK,\n tKKrA,\n tKKrB,\n tQKcMqk,\n tKKcMkk,\n aux_tidx,\n )\n\n # ─── Kernel entry point ───────────────────────────────────────────────────\n\n @cute.jit\n def __call__(\n self,\n g_q: cute.Tensor,\n g_k: cute.Tensor,\n g_v: cute.Tensor,\n g_o: cute.Tensor,\n g_alpha: cute.Tensor,\n g_beta: cute.Tensor,\n g_state: cute.Tensor,\n g_init_state: cute.Tensor,\n g_state_indices: cute.Tensor,\n g_state_checkpoints: cute.Tensor,\n checkpoint_cu_starts: cute.Tensor,\n g_tensormaps: cute.Tensor,\n cu_seqlens: cute.Tensor,\n scale: cutlass.Float32,\n num_q_heads: cutlass.Int32,\n num_k_heads: cutlass.Int32,\n num_v_heads: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n num_seqs: cutlass.Int32,\n total_checkpoints: cutlass.Int32,\n checkpoint_every_n_tokens: cutlass.Int32,\n grid_x: int,\n stream,\n ):\n qkv_smem_layout_atom = warpgroup.make_smem_layout_atom(\n warpgroup.SmemLayoutAtomKind.K_SW128,\n self.dtype,\n )\n q_storage_layout = cute.coalesce(\n cute.tile_to_shape(\n qkv_smem_layout_atom,\n (self.BLK_Q, self.D, self.q_stage),\n order=(0, 1, 2),\n ),\n target_profile=(1, 1, 1),\n )\n q_smem_layout = cute.slice_(q_storage_layout, (None, None, 0))\n k_storage_layout_sd = cute.coalesce(\n cute.tile_to_shape(\n qkv_smem_layout_atom,\n (self.BLK_KV, self.D, self.k_stage),\n order=(0, 1, 2),\n ),\n target_profile=(1, 1, 1),\n )\n k_storage_layout_ds = cute.select(k_storage_layout_sd, [1, 0, 2])\n v_storage_layout_sd = cute.coalesce(\n cute.tile_to_shape(\n qkv_smem_layout_atom,\n (self.BLK_KV, self.D, self.v_stage),\n order=(0, 1, 2),\n ),\n target_profile=(1, 1, 1),\n )\n v_storage_layout_ds = cute.select(v_storage_layout_sd, [1, 0, 2])\n k_smem_layout = cute.slice_(k_storage_layout_ds, (None, None, 0))\n v_smem_layout = cute.slice_(v_storage_layout_ds, (None, None, 0))\n o_smem_layout_atom = warpgroup.make_smem_layout_atom(\n warpgroup.SmemLayoutAtomKind.MN_SW32,\n self.dtype,\n )\n o_storage_layout = cute.tile_to_shape(\n o_smem_layout_atom,\n (self.D, self.BLK_Q, self.o_stage),\n order=(1, 0, 2),\n )\n o_smem_layout = cute.slice_(o_storage_layout, (None, None, 0))\n\n tma_load_op = cpasync.CopyBulkTensorTileG2SOp()\n tma_atom_q, tma_tensor_q = cpasync.make_tiled_tma_atom(\n tma_load_op, g_q, q_smem_layout, (self.BLK_Q, self.D)\n )\n tma_atom_k, tma_tensor_k = cpasync.make_tiled_tma_atom(\n tma_load_op, g_k, k_smem_layout, (self.D, self.BLK_KV)\n )\n tma_atom_v, tma_tensor_v = cpasync.make_tiled_tma_atom(\n tma_load_op, g_v, v_smem_layout, (self.D, self.BLK_KV)\n )\n\n tma_store_op = cpasync.CopyBulkTensorTileS2GOp()\n tma_atom_o, tma_tensor_o = cpasync.make_tiled_tma_atom(\n tma_store_op, g_o, o_smem_layout, (self.D, self.BLK_Q)\n )\n\n dtype_bytes = self.dtype.width // 8\n self.tma_load_q_bytes = cute.size(q_smem_layout) * dtype_bytes\n self.tma_load_k_bytes = cute.size(k_smem_layout) * dtype_bytes\n self.tma_load_v_bytes = cute.size(v_smem_layout) * dtype_bytes\n\n qk_layout_atom = cute.make_layout((8, 8), stride=(8, 1))\n qk_storage_layout = cute.tile_to_shape(\n qk_layout_atom, (self.BLK_Q, self.BLK_KV, self.qk_stage), order=(0, 1, 2)\n )\n kk_storage_layout = cute.tile_to_shape(\n qk_layout_atom, (self.BLK_KV, self.BLK_KV, self.kk_stage), order=(0, 1, 2)\n )\n alpha_storage_layout = cute.make_layout(\n (self.BLK_Q, AlphaProcessor.NUM_CHANNELS, self.alpha_beta_stage)\n )\n beta_storage_layout = cute.make_layout((self.BLK_KV, self.alpha_beta_stage))\n\n @cute.struct\n class SharedStorage:\n q_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.q_stage * 2]\n k_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.k_stage * 2]\n v_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.v_stage * 2]\n o_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.o_stage * 2]\n qk_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.qk_stage * 2]\n kk_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.kk_stage * 2]\n alpha_mbar_ptr: cute.struct.MemRange[\n cutlass.Int64, self.alpha_beta_stage * 2\n ]\n beta_mbar_ptr: cute.struct.MemRange[\n cutlass.Int64, self.alpha_beta_stage * 2\n ]\n\n smem_q: cute.struct.Align[\n cute.struct.MemRange[self.dtype, cute.cosize(q_storage_layout)],\n 128,\n ]\n smem_k: cute.struct.Align[\n cute.struct.MemRange[self.dtype, cute.cosize(k_storage_layout_sd)],\n 128,\n ]\n smem_v: cute.struct.Align[\n cute.struct.MemRange[self.dtype, cute.cosize(v_storage_layout_sd)],\n 128,\n ]\n smem_qk: cute.struct.Align[\n cute.struct.MemRange[self.dtype, cute.cosize(qk_storage_layout)],\n 16,\n ]\n smem_kk: cute.struct.Align[\n cute.struct.MemRange[\n self.inverse_dtype, cute.cosize(kk_storage_layout)\n ],\n 16,\n ]\n smem_o: cute.struct.Align[\n cute.struct.MemRange[self.dtype, cute.cosize(o_storage_layout)],\n 128,\n ]\n smem_alpha: cute.struct.Align[\n cute.struct.MemRange[\n cutlass.Float32, cute.cosize(alpha_storage_layout)\n ],\n 16,\n ]\n smem_beta: cute.struct.Align[\n cute.struct.MemRange[cutlass.Float32, cute.cosize(beta_storage_layout)],\n 16,\n ]\n\n self.shared_storage = SharedStorage\n\n self.kernel(\n g_alpha,\n g_beta,\n tma_atom_q,\n tma_tensor_q,\n tma_atom_k,\n tma_tensor_k,\n tma_atom_v,\n tma_tensor_v,\n tma_atom_o,\n tma_tensor_o,\n g_state,\n g_init_state,\n g_state_indices,\n g_state_checkpoints,\n checkpoint_cu_starts,\n g_tensormaps,\n cu_seqlens,\n scale,\n num_q_heads,\n num_k_heads,\n num_v_heads,\n num_sab_heads,\n num_seqs,\n total_checkpoints,\n checkpoint_every_n_tokens,\n ).launch(\n grid=(grid_x, 1, 1),\n block=(512, 1, 1),\n max_number_threads=(512, 1, 1),\n stream=stream,\n min_blocks_per_mp=1,\n )\n\n @cute.kernel\n def kernel(\n self,\n g_alpha: cute.Tensor,\n g_beta: cute.Tensor,\n tma_atom_q: cute.CopyAtom,\n tma_tensor_q: cute.Tensor,\n tma_atom_k: cute.CopyAtom,\n tma_tensor_k: cute.Tensor,\n tma_atom_v: cute.CopyAtom,\n tma_tensor_v: cute.Tensor,\n tma_atom_o: cute.CopyAtom,\n tma_tensor_o: cute.Tensor,\n g_state: cute.Tensor,\n g_init_state: cute.Tensor,\n g_state_indices: cute.Tensor,\n g_state_checkpoints: cute.Tensor,\n checkpoint_cu_starts: cute.Tensor,\n g_tensormaps: cute.Tensor,\n cu_seqlens: cute.Tensor,\n scale: cutlass.Float32,\n num_q_heads: cutlass.Int32,\n num_k_heads: cutlass.Int32,\n num_v_heads: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n num_seqs: cutlass.Int32,\n total_checkpoints: cutlass.Int32,\n checkpoint_every_n_tokens: cutlass.Int32,\n ):\n NUM_LOAD_WARP_GROUPS = 1\n NUM_STATE_MMA_WARP_GROUPS = 2\n NUM_AUX_MMA_WARP_GROUPS = 1\n THREADS_PER_WARP_GROUP = 128\n WARPS_PER_WARP_GROUP = 4\n MIN_BLOCKS_PER_MP = 1\n MAX_THREADS_PER_BLOCK = (\n NUM_LOAD_WARP_GROUPS + NUM_STATE_MMA_WARP_GROUPS + NUM_AUX_MMA_WARP_GROUPS\n ) * THREADS_PER_WARP_GROUP\n (\n load_registers,\n state_mma_registers,\n aux_mma_registers,\n ) = self.get_register_requirements(\n MAX_THREADS_PER_BLOCK,\n MIN_BLOCKS_PER_MP,\n NUM_STATE_MMA_WARP_GROUPS,\n THREADS_PER_WARP_GROUP,\n )\n\n tidx, _, _ = cute.arch.thread_idx()\n warp_idx = cute.arch.make_warp_uniform(cute.arch.warp_idx())\n warp_group_idx = cute.arch.make_warp_uniform(\n tidx // cutlass.Int32(THREADS_PER_WARP_GROUP)\n )\n ldst_warp_role = cute.arch.make_warp_uniform(\n warp_idx % cutlass.Int32(WARPS_PER_WARP_GROUP)\n )\n\n if warp_idx == LoadStoreWarpRole.LOAD_QKV:\n cpasync.prefetch_descriptor(tma_atom_q)\n cpasync.prefetch_descriptor(tma_atom_k)\n cpasync.prefetch_descriptor(tma_atom_v)\n cpasync.prefetch_descriptor(tma_atom_o)\n\n work_desc = self.get_next_work(\n cu_seqlens,\n num_q_heads,\n num_v_heads,\n num_sab_heads,\n )\n tok_end = work_desc.tok_offset + work_desc.seq_len\n num_blocks = (\n work_desc.seq_len + cutlass.Int32(self.BLK_KV) - cutlass.Int32(1)\n ) // cutlass.Int32(self.BLK_KV)\n\n # math_tidx / wg_idx: valid for Math WG threads; LdSt WG gets negative values (unused)\n math_tidx = tidx - cutlass.Int32(THREADS_PER_WARP_GROUP)\n wg_idx = math_tidx // cutlass.Int32(THREADS_PER_WARP_GROUP)\n\n # ── Smem allocation ───────────────────────────────────────────────────\n allocator = cutlass.utils.SmemAllocator()\n storage = allocator.allocate(self.shared_storage)\n\n qkv_smem_layout_atom = warpgroup.make_smem_layout_atom(\n warpgroup.SmemLayoutAtomKind.K_SW128,\n self.dtype,\n )\n q_layout_sd = cute.coalesce(\n cute.tile_to_shape(\n qkv_smem_layout_atom,\n (self.BLK_Q, self.D, self.q_stage),\n order=(0, 1, 2),\n ),\n target_profile=(1, 1, 1),\n )\n sQ_SD = storage.smem_q.get_tensor(q_layout_sd.outer, swizzle=q_layout_sd.inner)\n\n k_layout_sd = cute.coalesce(\n cute.tile_to_shape(\n qkv_smem_layout_atom,\n (self.BLK_KV, self.D, self.k_stage),\n order=(0, 1, 2),\n ),\n target_profile=(1, 1, 1),\n )\n k_layout_ds = cute.select(k_layout_sd, [1, 0, 2])\n sK_SD = storage.smem_k.get_tensor(k_layout_sd.outer, swizzle=k_layout_sd.inner)\n sK_DS = storage.smem_k.get_tensor(k_layout_ds.outer, swizzle=k_layout_ds.inner)\n\n v_layout_sd = cute.coalesce(\n cute.tile_to_shape(\n qkv_smem_layout_atom,\n (self.BLK_KV, self.D, self.v_stage),\n order=(0, 1, 2),\n ),\n target_profile=(1, 1, 1),\n )\n v_layout_ds = cute.select(v_layout_sd, [1, 0, 2])\n sV_DS = storage.smem_v.get_tensor(v_layout_ds.outer, swizzle=v_layout_ds.inner)\n\n qk_layout_atom = cute.make_layout((8, 8), stride=(8, 1))\n qk_layout = cute.tile_to_shape(\n qk_layout_atom, (self.BLK_Q, self.BLK_KV, self.qk_stage), order=(0, 1, 2)\n )\n sQK = storage.smem_qk.get_tensor(qk_layout)\n\n kk_layout = cute.tile_to_shape(\n qk_layout_atom, (self.BLK_KV, self.BLK_KV, self.kk_stage), order=(0, 1, 2)\n )\n sKK_inv = storage.smem_kk.get_tensor(kk_layout)\n kk_opd_ptr = cute.recast_ptr(storage.smem_kk.data_ptr(), dtype=self.dtype)\n sKK_opd = cute.make_tensor(kk_opd_ptr, kk_layout)\n\n o_smem_layout_atom = warpgroup.make_smem_layout_atom(\n warpgroup.SmemLayoutAtomKind.MN_SW32,\n self.dtype,\n )\n o_layout = cute.tile_to_shape(\n o_smem_layout_atom,\n (self.D, self.BLK_Q, self.o_stage),\n order=(1, 0, 2),\n )\n sO = storage.smem_o.get_tensor(o_layout.outer, swizzle=o_layout.inner)\n alpha_layout = cute.make_layout(\n (self.BLK_Q, AlphaProcessor.NUM_CHANNELS, self.alpha_beta_stage)\n )\n sAlpha = storage.smem_alpha.get_tensor(alpha_layout)\n\n beta_layout = cute.make_layout((self.BLK_KV, self.alpha_beta_stage))\n sBeta = storage.smem_beta.get_tensor(beta_layout)\n\n load_producer_group = pipeline.CooperativeGroup(pipeline.Agent.Thread, 1)\n # PipelineTmaAsync release is signalled by one lane per consumer warp.\n qk_load_consumer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n (NUM_STATE_MMA_WARP_GROUPS + NUM_AUX_MMA_WARP_GROUPS)\n * WARPS_PER_WARP_GROUP,\n )\n v_consumer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n NUM_STATE_MMA_WARP_GROUPS * WARPS_PER_WARP_GROUP,\n )\n vector_producer_group = pipeline.CooperativeGroup(pipeline.Agent.Thread, 32)\n alpha_consumer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n (NUM_AUX_MMA_WARP_GROUPS + NUM_STATE_MMA_WARP_GROUPS)\n * THREADS_PER_WARP_GROUP,\n )\n beta_consumer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread, NUM_AUX_MMA_WARP_GROUPS * THREADS_PER_WARP_GROUP\n )\n o_producer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread, NUM_STATE_MMA_WARP_GROUPS * THREADS_PER_WARP_GROUP\n )\n o_consumer_group = pipeline.CooperativeGroup(pipeline.Agent.Thread, 32)\n q_pipeline = pipeline.PipelineTmaAsync.create(\n barrier_storage=storage.q_mbar_ptr.data_ptr(),\n num_stages=self.q_stage,\n producer_group=load_producer_group,\n consumer_group=qk_load_consumer_group,\n tx_count=self.tma_load_q_bytes,\n cta_layout_vmnk=cute.make_layout((1, 1, 1, 1)),\n )\n k_pipeline = pipeline.PipelineTmaAsync.create(\n barrier_storage=storage.k_mbar_ptr.data_ptr(),\n num_stages=self.k_stage,\n producer_group=load_producer_group,\n consumer_group=qk_load_consumer_group,\n tx_count=self.tma_load_k_bytes,\n cta_layout_vmnk=cute.make_layout((1, 1, 1, 1)),\n )\n v_pipeline = pipeline.PipelineTmaAsync.create(\n barrier_storage=storage.v_mbar_ptr.data_ptr(),\n num_stages=self.v_stage,\n producer_group=load_producer_group,\n consumer_group=v_consumer_group,\n tx_count=self.tma_load_v_bytes,\n cta_layout_vmnk=cute.make_layout((1, 1, 1, 1)),\n )\n o_pipeline = pipeline.PipelineAsync.create(\n barrier_storage=storage.o_mbar_ptr.data_ptr(),\n num_stages=self.o_stage,\n producer_group=o_producer_group,\n consumer_group=o_consumer_group,\n )\n qk_pipeline = pipeline.PipelineAsync.create(\n barrier_storage=storage.qk_mbar_ptr.data_ptr(),\n num_stages=self.qk_stage,\n producer_group=pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n NUM_AUX_MMA_WARP_GROUPS * THREADS_PER_WARP_GROUP,\n ),\n consumer_group=pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n NUM_STATE_MMA_WARP_GROUPS * THREADS_PER_WARP_GROUP,\n ),\n )\n kk_pipeline = pipeline.PipelineAsync.create(\n barrier_storage=storage.kk_mbar_ptr.data_ptr(),\n num_stages=self.kk_stage,\n producer_group=pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n NUM_AUX_MMA_WARP_GROUPS * THREADS_PER_WARP_GROUP,\n ),\n consumer_group=pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n NUM_STATE_MMA_WARP_GROUPS * THREADS_PER_WARP_GROUP,\n ),\n )\n alpha_pipeline = pipeline.PipelineAsync.create(\n barrier_storage=storage.alpha_mbar_ptr.data_ptr(),\n num_stages=self.alpha_beta_stage,\n producer_group=vector_producer_group,\n consumer_group=alpha_consumer_group,\n )\n beta_pipeline = pipeline.PipelineAsync.create(\n barrier_storage=storage.beta_mbar_ptr.data_ptr(),\n num_stages=self.alpha_beta_stage,\n producer_group=vector_producer_group,\n consumer_group=beta_consumer_group,\n )\n cute.arch.mbarrier_init_fence()\n cute.arch.sync_threads()\n\n if (\n work_desc.seq_len != cutlass.Int32(0)\n and warp_group_idx == WarpGroupRole.LDST\n ):\n cute.arch.setmaxregister_decrease(load_registers)\n if ldst_warp_role == LoadStoreWarpRole.LOAD_QKV:\n self.run_load_qkv_role(\n sQ_SD,\n sK_DS,\n sV_DS,\n tma_atom_q,\n tma_tensor_q,\n tma_atom_k,\n tma_tensor_k,\n tma_atom_v,\n tma_tensor_v,\n q_pipeline,\n k_pipeline,\n v_pipeline,\n num_blocks,\n work_desc.tok_offset,\n work_desc.q_head_idx(),\n work_desc.k_head_idx(num_q_heads, num_v_heads),\n work_desc.v_head_idx(),\n )\n elif ldst_warp_role == LoadStoreWarpRole.STORE_O:\n CollectiveStoreTma(self.BLK_Q, self.D).run(\n sO,\n tma_atom_o,\n tma_tensor_o,\n g_tensormaps,\n o_pipeline,\n num_blocks,\n work_desc,\n num_seqs,\n self.o_stage,\n num_q_heads,\n num_v_heads,\n )\n elif ldst_warp_role == LoadStoreWarpRole.LOAD_BETA:\n self.run_load_beta_role(\n sBeta,\n g_beta,\n beta_pipeline,\n num_blocks,\n work_desc.tok_offset,\n tok_end,\n work_desc.o_head_idx(num_q_heads, num_v_heads),\n num_sab_heads,\n )\n elif ldst_warp_role == LoadStoreWarpRole.LOAD_ALPHA:\n self.run_load_alpha_role(\n sAlpha,\n g_alpha,\n alpha_pipeline,\n scale,\n num_blocks,\n work_desc.tok_offset,\n tok_end,\n work_desc.o_head_idx(num_q_heads, num_v_heads),\n num_sab_heads,\n )\n elif work_desc.seq_len != cutlass.Int32(0):\n if warp_group_idx == WarpGroupRole.MATH_AUX:\n cute.arch.setmaxregister_decrease(aux_mma_registers)\n self.run_aux_math_role(\n sQ_SD,\n sK_SD,\n sQK,\n sKK_inv,\n sKK_opd,\n sAlpha,\n sBeta,\n q_pipeline,\n k_pipeline,\n qk_pipeline,\n kk_pipeline,\n alpha_pipeline,\n beta_pipeline,\n work_desc,\n scale,\n math_tidx,\n num_blocks,\n )\n else:\n cute.arch.setmaxregister_increase(state_mma_registers)\n self.run_state_math_role(\n sQ_SD,\n sK_SD,\n sK_DS,\n sV_DS,\n sQK,\n sKK_inv,\n sKK_opd,\n sO,\n sAlpha,\n q_pipeline,\n k_pipeline,\n v_pipeline,\n o_pipeline,\n qk_pipeline,\n kk_pipeline,\n alpha_pipeline,\n g_state,\n g_init_state,\n g_state_indices,\n g_state_checkpoints,\n checkpoint_cu_starts,\n work_desc,\n scale,\n wg_idx,\n math_tidx,\n num_blocks,\n num_q_heads,\n num_v_heads,\n num_sab_heads,\n num_seqs,\n total_checkpoints,\n checkpoint_every_n_tokens,\n )\n\n\n# ─── Public API ──────────────────────────────────────────────────────────────\n\n\ndef delta_rule_prefill_dsl_sm90(\n o: torch.Tensor, # (total_seqlen, num_o_heads, D) fp16/bf16, output\n state: torch.Tensor, # (num_seqs, num_sab_heads, D, D) fp32, output\n q: torch.Tensor, # (total_seqlen, num_q_heads, D)\n k: torch.Tensor, # (total_seqlen, num_k_heads, D)\n v: torch.Tensor, # (total_seqlen, num_v_heads, D)\n init_state: torch.Tensor | None, # (num_seqs, num_sab_heads, D, D) fp32, optional\n alpha: torch.Tensor | None,\n beta: torch.Tensor | None,\n cu_seqlens: torch.Tensor, # (num_seqs+1,) int64\n scale: float,\n state_checkpoints: torch.Tensor | None = None,\n checkpoint_cu_starts: torch.Tensor | None = None,\n checkpoint_every_n_tokens: int = 0,\n state_indices: torch.Tensor | None = None,\n):\n from cutlass.cute.runtime import from_dlpack\n import cuda.bindings.driver as cuda_driver\n\n D = q.shape[-1]\n\n num_seqs = cu_seqlens.shape[0] - 1\n num_q_heads = q.shape[1]\n num_k_heads = k.shape[1]\n num_v_heads = v.shape[1]\n num_sab_heads = max(num_q_heads, num_v_heads)\n\n if not _FullyFusedDeltaRuleSm90.can_implement(\n num_q_heads, num_k_heads, num_v_heads, D, q.element_size()\n ):\n raise RuntimeError(\"can_implement failed\")\n if D != 128:\n raise RuntimeError(f\"DSL kernel only supports D=128, got {D}\")\n\n needs_alpha = alpha is not None\n needs_beta = beta is not None\n needs_init_state = init_state is not None\n needs_checkpointing = checkpoint_every_n_tokens > 0\n use_state_indices = state_indices is not None\n kernel_dtype = {\n torch.float16: cutlass.Float16,\n torch.bfloat16: cutlass.BFloat16,\n }.get(q.dtype)\n if kernel_dtype is None:\n raise RuntimeError(f\"DSL kernel only supports fp16/bf16 inputs, got {q.dtype}\")\n\n if k.dtype != q.dtype or v.dtype != q.dtype or o.dtype != q.dtype:\n raise RuntimeError(\n f\"q/k/v/o dtypes must match, got {q.dtype}, {k.dtype}, {v.dtype}, {o.dtype}\"\n )\n if alpha is not None and alpha.dtype != torch.float32:\n raise RuntimeError(f\"alpha must have dtype torch.float32, got {alpha.dtype}\")\n if beta is not None and beta.dtype != torch.float32:\n raise RuntimeError(f\"beta must have dtype torch.float32, got {beta.dtype}\")\n if init_state is not None:\n state_dtype_to_cutlass(init_state.dtype)\n state_dtype_to_cutlass(state.dtype)\n if state_checkpoints is not None:\n state_dtype_to_cutlass(state_checkpoints.dtype)\n if not is_integer_dtype(cu_seqlens.dtype):\n raise RuntimeError(\n f\"cu_seqlens must have an integer dtype, got {cu_seqlens.dtype}\"\n )\n\n expected_state_tail = (num_sab_heads, D, D)\n for name, tensor in ((\"state\", state), (\"init_state\", init_state)):\n if tensor is None:\n continue\n if (\n not use_state_indices and tensor.shape != (num_seqs, *expected_state_tail)\n ) or (use_state_indices and tuple(tensor.shape[1:]) != expected_state_tail):\n raise RuntimeError(\n f\"{name} must have shape \"\n f\"{('[N_pool]' if use_state_indices else f'[{num_seqs}]')} + {expected_state_tail}, \"\n f\"got {tuple(tensor.shape)}\"\n )\n if use_state_indices and (\n not is_integer_dtype(state_indices.dtype) or state_indices.shape != (num_seqs,)\n ):\n raise RuntimeError(\n f\"state_indices must have shape {(num_seqs,)} and an integer dtype\"\n )\n\n for name, tensor in (\n (\"q\", q),\n (\"k\", k),\n (\"v\", v),\n (\"o\", o),\n (\"cu_seqlens\", cu_seqlens),\n ):\n if not tensor.is_contiguous():\n raise RuntimeError(f\"{name} must be contiguous\")\n for name, tensor in (\n (\"alpha\", alpha),\n (\"beta\", beta),\n (\"state_indices\", state_indices),\n ):\n if tensor is not None and not tensor.is_contiguous():\n raise RuntimeError(f\"{name} must be contiguous\")\n for name, tensor in ((\"state\", state), (\"init_state\", init_state)):\n if tensor is None:\n continue\n if not use_state_indices and not tensor.is_contiguous():\n raise RuntimeError(f\"{name} must be contiguous\")\n\n total_seqlen = q.shape[0]\n num_o_heads = o.shape[1]\n q_tma = q.as_strided(\n (total_seqlen, D, num_q_heads),\n (num_q_heads * D, 1, D),\n )\n k_tma = k.as_strided(\n (D, total_seqlen, num_k_heads),\n (1, num_k_heads * D, D),\n )\n v_tma = v.as_strided(\n (D, total_seqlen, num_v_heads),\n (1, num_v_heads * D, D),\n )\n o_tma = o.as_strided(\n (D, total_seqlen, num_o_heads),\n (1, num_o_heads * D, D),\n )\n total_checkpoints = state_checkpoints.shape[0] if needs_checkpointing else 1\n\n workspace_size = get_device_sm_count(q.device) * 128\n tensormaps_t = _get_cache_buf(\"gdn_prefill_tensormaps\", workspace_size, q.device)\n\n stream_val = torch.cuda.current_stream().cuda_stream\n stream = cuda_driver.CUstream(stream_val)\n\n enable_tvm_ffi = True\n if enable_tvm_ffi:\n from_dlpack = lambda *args, **kwargs: cute.runtime.from_dlpack(\n *args, **{**kwargs, \"enable_tvm_ffi\": True}\n )\n\n # Keep head counts and varlen extents runtime values across cached compiles.\n q_cute = from_dlpack(q_tma, assumed_align=16).mark_layout_dynamic(leading_dim=1)\n k_cute = from_dlpack(k_tma, assumed_align=16).mark_layout_dynamic(leading_dim=0)\n v_cute = from_dlpack(v_tma, assumed_align=16).mark_layout_dynamic(leading_dim=0)\n o_cute = from_dlpack(o_tma, assumed_align=16).mark_layout_dynamic(leading_dim=0)\n alpha_cute = (\n from_dlpack(alpha.reshape(-1), assumed_align=16).mark_layout_dynamic()\n if needs_alpha\n else None\n )\n beta_cute = (\n from_dlpack(beta.reshape(-1), assumed_align=16).mark_layout_dynamic()\n if needs_beta\n else None\n )\n state_cute = from_dlpack(state, assumed_align=16).mark_layout_dynamic()\n init_state_cute = (\n from_dlpack(init_state, assumed_align=16).mark_layout_dynamic()\n if needs_init_state\n else None\n )\n state_indices_cute = (\n from_dlpack(state_indices, assumed_align=4).mark_layout_dynamic()\n if use_state_indices\n else None\n )\n state_checkpoints_cute = (\n from_dlpack(\n state_checkpoints.reshape(-1), assumed_align=16\n ).mark_layout_dynamic()\n if needs_checkpointing\n else None\n )\n checkpoint_cu_cute = (\n from_dlpack(checkpoint_cu_starts, assumed_align=8).mark_layout_dynamic()\n if needs_checkpointing\n else None\n )\n tensormaps_cute = from_dlpack(tensormaps_t, assumed_align=128).mark_layout_dynamic()\n cu_cute = from_dlpack(cu_seqlens, assumed_align=8).mark_layout_dynamic()\n\n delta_rule_kernel = _FullyFusedDeltaRuleSm90(\n needs_alpha,\n needs_beta,\n needs_init_state,\n needs_checkpointing,\n kernel_dtype,\n initial_state_dtype=state_dtype_to_cutlass(\n init_state.dtype if needs_init_state else torch.float32\n ),\n state_dtype=state_dtype_to_cutlass(state.dtype),\n checkpoint_state_dtype=state_dtype_to_cutlass(\n state_checkpoints.dtype if needs_checkpointing else torch.float32\n ),\n use_state_indices=use_state_indices,\n cu_seqlens_dtype=cu_seqlens.dtype,\n state_indices_dtype=state_indices.dtype if use_state_indices else None,\n checkpoint_cu_starts_dtype=(\n checkpoint_cu_starts.dtype if needs_checkpointing else None\n ),\n state_inner_strides=(tuple(state.stride()[1:]) if use_state_indices else None),\n init_state_inner_strides=(\n tuple(init_state.stride()[1:])\n if use_state_indices and needs_init_state\n else None\n ),\n )\n\n kernel_args = (\n q_cute,\n k_cute,\n v_cute,\n o_cute,\n alpha_cute,\n beta_cute,\n state_cute,\n init_state_cute,\n state_indices_cute,\n state_checkpoints_cute,\n checkpoint_cu_cute,\n tensormaps_cute,\n cu_cute,\n cutlass.Float32(scale),\n cutlass.Int32(num_q_heads),\n cutlass.Int32(num_k_heads),\n cutlass.Int32(num_v_heads),\n cutlass.Int32(num_sab_heads),\n cutlass.Int32(num_seqs),\n cutlass.Int32(total_checkpoints),\n cutlass.Int32(checkpoint_every_n_tokens),\n num_seqs * num_sab_heads,\n stream,\n )\n compiled_delta_rule_kernel = cached_compile(\n delta_rule_kernel,\n *kernel_args,\n compile_options=(cute.GPUArch(\"sm_90a\"),),\n )\n compiled_delta_rule_kernel(*kernel_args)\n"},"after_code":{"kind":"string","value":"import functools\nfrom enum import IntEnum\n\nimport torch\nimport cutlass\nimport cutlass.cute as cute\nimport cutlass.pipeline as pipeline\nfrom cutlass.cute.nvgpu import warp, warpgroup, cpasync\nfrom ...utils import get_device_sm_count, _get_cache_buf\nfrom .alpha import AlphaProcessor\nfrom .collective_store_tma import CollectiveStoreTma\nfrom .custom_compile_cache import KeyedCompileMixin, cached_compile, get_cached_compile\nfrom .collective_inverse_hmma import CollectiveInverse\nfrom .helpers import SM90, round_down, select_tensor_10, state_dtype_to_cutlass\nfrom .schedule import WorkDesc\nfrom .varlen_helper import is_integer_dtype\n\n\n_SM90_COMPILE_OPTIONS = (cute.EnableTVMFFI(True), cute.GPUArch(\"sm_90a\"))\n\n\n# ─── Named-barrier IDs used by the compute kernel ────────────────────────────\n# Must not conflict with each other or with pipeline barrier storage.\n\n\nclass NamedBarrier(IntEnum):\n MATH_WG0 = 4 # OrderedMathBarriers: StreamkBarrier0\n MATH_WG1 = 5 # OrderedMathBarriers: StreamkBarrier1\n KK_SYNC = 13 # sync all 128 WG0 threads before collective_inverse\n\n\nclass WarpGroupRole(IntEnum):\n LDST = 0\n MATH_STATE0 = 1\n MATH_STATE1 = 2\n MATH_AUX = 3\n\n\nclass LoadStoreWarpRole(IntEnum):\n STORE_O = 0\n LOAD_QKV = 1\n LOAD_BETA = 2\n LOAD_ALPHA = 3\n\n\nclass MathWarpGroupRole(IntEnum):\n STATE0 = 0\n STATE1 = 1\n AUX = 2\n KK = 0\n QK = 1\n\n\n# ─── Warp-specialized delta-rule kernel ───────────────────────────────────────\n# Grid: (num_seqs * num_sab_heads, 1, 1)\n# Block: 512 threads → WG0=LD/ST, WG1/WG2=state math, WG3=aux math.\n#\n# needs_alpha / needs_beta / needs_init_state are class attributes set in __init__.\n# The JIT compiler specialises per instance, so they are compile-time booleans\n# inside the kernel without any parameter-passing trickery.\n\n\nclass _FullyFusedDeltaRuleSm90(KeyedCompileMixin):\n @staticmethod\n def get_register_requirements(\n max_threads_per_block: int,\n min_blocks_per_multiprocessor: int,\n num_state_mma_warp_groups: int,\n threads_per_warp_group: int,\n ) -> tuple[int, int, int]:\n reg_alloc_granularity = 8\n load_registers = 40 - 2 * reg_alloc_granularity\n aux_registers = 128 - load_registers\n total_registers = (\n round_down(\n 64 * 1024 // min_blocks_per_multiprocessor,\n max_threads_per_block * reg_alloc_granularity,\n )\n // threads_per_warp_group\n )\n state_mma_registers = round_down(\n (total_registers - load_registers - aux_registers)\n // num_state_mma_warp_groups,\n reg_alloc_granularity,\n )\n return (\n min(248, load_registers),\n min(248, state_mma_registers),\n min(248, aux_registers),\n )\n\n @staticmethod\n def can_implement(\n num_q_heads: int,\n num_k_heads: int,\n num_v_heads: int,\n head_size: int,\n element_size: int,\n ) -> bool:\n ratio = (\n num_q_heads // num_v_heads\n if num_q_heads > num_v_heads\n else num_v_heads // num_q_heads\n )\n is_gva_enabled = num_v_heads > num_q_heads\n\n is_gqa_like = (\n (num_k_heads == num_v_heads)\n and (num_q_heads == ratio * num_k_heads)\n and (num_q_heads == ratio * num_v_heads)\n )\n is_gva_like = (\n (num_q_heads == num_k_heads)\n and (num_v_heads == ratio * num_q_heads)\n and (num_v_heads == ratio * num_k_heads)\n )\n\n alignment = 16 // element_size\n return (\n ((not is_gva_enabled and is_gqa_like) or (is_gva_enabled and is_gva_like))\n and (head_size <= 128)\n and ((head_size % alignment) == 0)\n )\n\n def __init__(\n self,\n needs_alpha: bool,\n needs_beta: bool,\n needs_init_state: bool,\n needs_checkpointing: bool,\n dtype: type[cutlass.Numeric] = cutlass.Float16,\n acc_dtype: type[cutlass.Numeric] = cutlass.Float32,\n initial_state_dtype: type[cutlass.Numeric] = cutlass.Float32,\n state_dtype: type[cutlass.Numeric] = cutlass.Float32,\n checkpoint_state_dtype: type[cutlass.Numeric] = cutlass.Float32,\n use_state_indices: bool = False,\n cu_seqlens_dtype: torch.dtype = torch.int64,\n state_indices_dtype: torch.dtype | None = None,\n checkpoint_cu_starts_dtype: torch.dtype | None = None,\n state_inner_strides: tuple[int, ...] | None = None,\n init_state_inner_strides: tuple[int, ...] | None = None,\n ):\n self.needs_alpha = needs_alpha\n self.needs_beta = needs_beta\n self.needs_init_state = needs_init_state\n self.needs_checkpointing = needs_checkpointing\n self.dtype = dtype\n self.acc_dtype = acc_dtype\n self.initial_state_dtype = initial_state_dtype\n self.state_dtype = state_dtype\n self.checkpoint_state_dtype = checkpoint_state_dtype\n self.use_state_indices = use_state_indices\n self.cu_seqlens_dtype = cu_seqlens_dtype\n self.state_indices_dtype = state_indices_dtype\n self.checkpoint_cu_starts_dtype = checkpoint_cu_starts_dtype\n self.state_inner_strides = state_inner_strides\n self.init_state_inner_strides = init_state_inner_strides\n self.inverse_dtype = cutlass.Float16\n self.BLK_Q = 64\n self.BLK_KV = 64\n self.D = 128\n self.q_stage = 2\n self.k_stage = 3\n self.v_stage = 2\n self.o_stage = 2\n self.qk_stage = 2\n self.kk_stage = 2\n self.alpha_beta_stage = 5\n self.manual_cache_key(\n \"needs_alpha\",\n \"needs_beta\",\n \"needs_init_state\",\n \"needs_checkpointing\",\n \"dtype\",\n \"acc_dtype\",\n \"initial_state_dtype\",\n \"state_dtype\",\n \"checkpoint_state_dtype\",\n \"use_state_indices\",\n \"cu_seqlens_dtype\",\n \"state_indices_dtype\",\n \"checkpoint_cu_starts_dtype\",\n \"state_inner_strides\",\n \"init_state_inner_strides\",\n \"inverse_dtype\",\n \"BLK_Q\",\n \"BLK_KV\",\n \"D\",\n \"q_stage\",\n \"k_stage\",\n \"v_stage\",\n \"o_stage\",\n \"qk_stage\",\n \"kk_stage\",\n \"alpha_beta_stage\",\n )\n\n def get_next_work(\n self,\n cu_seqlens: cute.Tensor,\n num_q_heads: cutlass.Int32,\n num_v_heads: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n ) -> WorkDesc:\n bx, _, _ = cute.arch.block_idx()\n seq_idx = bx // num_sab_heads\n o_head_idx = bx % num_sab_heads\n q_head_idx = o_head_idx * num_q_heads // num_sab_heads\n v_head_idx = o_head_idx * num_v_heads // num_sab_heads\n tok_start = cu_seqlens[seq_idx]\n seq_len = cutlass.Int32(cu_seqlens[seq_idx + 1] - tok_start)\n\n return WorkDesc(\n seq_idx=seq_idx,\n private_q_head_idx=q_head_idx,\n private_v_head_idx=v_head_idx,\n tok_offset=tok_start,\n seq_len=seq_len,\n tile_idx=cutlass.Int32(0),\n )\n\n # ─── Ordered 2-WG math barriers ───────────────────────────────────────────\n # Translates flat::OrderedNamedBarriers<UseReservedNB, NB0, NB1>.\n # wg_idx: MathWarpGroupRole.KK or MathWarpGroupRole.QK.\n\n @cute.jit\n def _math_order_init(self, wg_idx: cutlass.Int32):\n \"\"\"Pre-arrive at WG0's barrier so WG0 is unblocked on the first wait.\"\"\"\n if wg_idx == MathWarpGroupRole.QK:\n cute.arch.barrier_arrive(\n barrier_id=NamedBarrier.MATH_WG0, number_of_threads=256\n )\n\n @cute.jit\n def _math_order_wait(self, wg_idx: cutlass.Int32):\n \"\"\"Arrive+wait on this WG's own ordered barrier.\"\"\"\n if wg_idx == MathWarpGroupRole.KK:\n cute.arch.barrier(barrier_id=NamedBarrier.MATH_WG0, number_of_threads=256)\n else:\n cute.arch.barrier(barrier_id=NamedBarrier.MATH_WG1, number_of_threads=256)\n\n @cute.jit\n def _math_order_notify(self, wg_idx: cutlass.Int32):\n \"\"\"Arrive at the other WG's barrier to unblock it.\"\"\"\n if wg_idx == MathWarpGroupRole.KK:\n cute.arch.barrier_arrive(\n barrier_id=NamedBarrier.MATH_WG1, number_of_threads=256\n )\n else:\n cute.arch.barrier_arrive(\n barrier_id=NamedBarrier.MATH_WG0, number_of_threads=256\n )\n\n # ─── kk_store_and_inv ─────────────────────────────────────────────────────\n\n @cute.jit\n def _kk_store_and_inv(\n self,\n tKKrKK: cute.Tensor, # fp32 KK accumulator (from 128-thread kk_tiled_mma)\n kk_tiled_mma,\n kk_thread_idx: cutlass.Int32,\n sKK_inv: cute.Tensor, # (BlkKV, BlkKV) 8×8-tiled smem\n sKK_opd: cute.Tensor, # sKK_inv storage recast as Element for MMA operand\n sBeta: cute.Tensor, # (BlkKV, StagesBeta) - used when needs_beta\n beta_pipe_idx: cutlass.Int32,\n tKKcMkk: cute.Tensor, # coordinate mapping for KK fragment\n ):\n \"\"\"Store tKKrKK → sKK_inv, Inverse, optionally reload+beta.\"\"\"\n stsm_atom = cute.make_copy_atom(\n warp.StMatrix8x8x16bOp(transpose=False, num_matrices=4), self.inverse_dtype\n )\n tiled_store = cute.make_tiled_copy_C(stsm_atom, kk_tiled_mma)\n thr_store = tiled_store.get_slice(kk_thread_idx)\n tKKsKK = thr_store.partition_D(sKK_inv)\n tKKrKK_cv = thr_store.retile(tKKrKK)\n tKKrKK_inv = cute.make_fragment_like(tKKrKK_cv, self.inverse_dtype)\n for i in cutlass.range_constexpr(cute.size(tKKrKK_cv)):\n tKKrKK_inv[i] = self.inverse_dtype(tKKrKK_cv[i])\n cute.copy(tiled_store, tKKrKK_inv, tKKsKK)\n\n cute.arch.barrier(barrier_id=NamedBarrier.KK_SYNC, number_of_threads=128)\n CollectiveInverse().run(sKK_inv, NamedBarrier.KK_SYNC)\n\n if cutlass.const_expr(self.needs_beta or self.dtype != self.inverse_dtype):\n cute.arch.barrier(barrier_id=NamedBarrier.KK_SYNC, number_of_threads=128)\n ldsm_atom = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(transpose=False, num_matrices=4),\n self.inverse_dtype,\n )\n tiled_load = cute.make_tiled_copy_C(ldsm_atom, kk_tiled_mma)\n thr_load = tiled_load.get_slice(kk_thread_idx)\n tKKrKK_cpy = cute.make_fragment_like(tKKrKK_inv)\n tKKrKK_cvt = cute.make_fragment_like(tKKrKK_inv, self.dtype)\n cute.copy(tiled_load, thr_load.partition_S(sKK_inv), tKKrKK_cpy)\n tKKcMkk_cv = thr_load.retile(tKKcMkk)\n\n for i in cutlass.range_constexpr(cute.size(tKKrKK_cpy)):\n if cutlass.const_expr(self.needs_beta):\n _, t = tKKcMkk_cv[i]\n tKKrKK_cvt[i] = self.dtype(\n cutlass.Float32(tKKrKK_cpy[i])\n * cutlass.Float32(sBeta[t, beta_pipe_idx])\n )\n else:\n tKKrKK_cvt[i] = self.dtype(tKKrKK_cpy[i])\n\n tKKsKK2 = thr_store.partition_D(sKK_opd)\n cute.copy(tiled_store, tKKrKK_cvt, tKKsKK2)\n\n # ─── qk_and_kk_epi ───────────────────────────────────────────────────────\n\n @cute.jit\n def qk_and_kk_epi(\n self,\n tQKrQK: cute.Tensor,\n tKKrKK: cute.Tensor,\n tQKcMqk: cute.Tensor,\n tKKcMkk: cute.Tensor,\n sAlpha: cute.Tensor,\n sBeta: cute.Tensor,\n alpha_stage: cutlass.Int32,\n beta_stage: cutlass.Int32,\n is_final_block: bool,\n B: cutlass.Int32,\n scale: cutlass.Float32,\n ):\n if cutlass.const_expr(self.needs_beta):\n beta_row = sBeta[None, beta_stage]\n for i in cutlass.range_constexpr(cute.size(tKKcMkk)):\n s, _ = tKKcMkk[i]\n tKKrKK[i] = tKKrKK[i] * cutlass.Float32(beta_row[s])\n\n if cutlass.const_expr(self.needs_alpha):\n alpha_cumlog = sAlpha[None, AlphaProcessor.CUMSUM_LOG, alpha_stage]\n for i in cutlass.range_constexpr(cute.size(tKKcMkk)):\n # s, t = tKKcMkk[i]\n s, t = tQKcMqk[i]\n alpha = cute.math.exp2(\n cutlass.Float32(alpha_cumlog[s]) - cutlass.Float32(alpha_cumlog[t]),\n fastmath=True,\n )\n tQKrQK[i] = tQKrQK[i] * alpha * scale\n tKKrKK[i] = tKKrKK[i] * alpha\n else:\n for i in cutlass.range_constexpr(cute.size(tQKrQK)):\n tQKrQK[i] = tQKrQK[i] * scale\n\n for i in cutlass.range_constexpr(cute.size(tKKcMkk)):\n # s, t = tKKcMkk[i]\n s, t = tQKcMqk[i]\n pred = s >= t\n tQKrQK[i] = tQKrQK[i] if pred else cutlass.Float32(0.0)\n tKKrKK[i] = tKKrKK[i] if pred else cutlass.Float32(0.0)\n if cutlass.const_expr(is_final_block):\n pred = s < B and t < B\n tQKrQK[i] = tQKrQK[i] if pred else cutlass.Float32(0.0)\n tKKrKK[i] = tKKrKK[i] if pred else cutlass.Float32(0.0)\n\n # ─── qk_store ─────────────────────────────────────────────────────────────\n\n @cute.jit\n def qk_store(\n self,\n tQKrQK: cute.Tensor,\n sQK: cute.Tensor,\n qk_tiled_mma,\n qk_thread_idx: cutlass.Int32,\n ):\n stsm_atom = cute.make_copy_atom(\n warp.StMatrix8x8x16bOp(transpose=False, num_matrices=4), self.dtype\n )\n qk_tiled_copy = cute.make_tiled_copy_C(stsm_atom, qk_tiled_mma)\n qk_thr_copy = qk_tiled_copy.get_slice(qk_thread_idx)\n tQKsQK = qk_thr_copy.partition_D(sQK)\n tQKrQK_cvt = cute.make_fragment_like(tQKrQK, self.dtype)\n tQKrQK_cvt_cv = qk_thr_copy.retile(tQKrQK_cvt)\n for i in cutlass.range_constexpr(cute.size(tQKrQK)):\n tQKrQK_cvt[i] = self.dtype(tQKrQK[i])\n cute.copy(qk_tiled_copy, tQKrQK_cvt_cv, tQKsQK)\n\n # ─── o1_epi ───────────────────────────────────────────────────────────────\n\n @cute.jit\n def o1_epi(\n self,\n tOrO: cute.Tensor,\n tOcO: cute.Tensor,\n sAlpha: cute.Tensor,\n alpha_stage: cutlass.Int32,\n scale: cutlass.Float32,\n ):\n if cutlass.const_expr(self.needs_alpha):\n alpha_cpscale = sAlpha[None, AlphaProcessor.CUMPROD_SCALE, alpha_stage]\n for i in cutlass.range_constexpr(cute.size(tOrO)):\n _, tok_q = tOcO[i]\n tOrO[i] = cutlass.Float32(alpha_cpscale[tok_q]) * tOrO[i]\n else:\n for i in cutlass.range_constexpr(cute.size(tOrO)):\n tOrO[i] = scale * tOrO[i]\n\n # ─── sk_epi ───────────────────────────────────────────────────────────────\n\n @cute.jit\n def sk_epi(\n self,\n tSKrSK: cute.Tensor,\n tSKcSK: cute.Tensor,\n sAlpha: cute.Tensor,\n alpha_stage: cutlass.Int32,\n ):\n if cutlass.const_expr(self.needs_alpha):\n alpha_cp = sAlpha[None, AlphaProcessor.CUMPROD, alpha_stage]\n for i in cutlass.range_constexpr(cute.size(tSKrSK)):\n _, tok_kv = tSKcSK[i]\n tSKrSK[i] = tSKrSK[i] * cutlass.Float32(alpha_cp[tok_kv])\n\n # ─── sk_load_v ────────────────────────────────────────────────────────────\n\n @cute.jit\n def sk_load_v(\n self,\n tSKrSK: cute.Tensor,\n sV_DS: cute.Tensor,\n sk_tiled_copy_C,\n sk_thr_copy_C,\n v_stage: cutlass.Int32,\n ) -> cute.Tensor:\n tSKrV = cute.make_fragment_like(tSKrSK, self.dtype)\n tSKrV_cv = sk_thr_copy_C.retile(tSKrV)\n tSKsV = sk_thr_copy_C.partition_S(sV_DS)\n cute.copy(sk_tiled_copy_C, tSKsV[None, None, None, v_stage], tSKrV_cv)\n return tSKrV\n\n # ─── kv_decay_v ───────────────────────────────────────────────────────────\n\n @cute.jit\n def kv_decay_v(\n self,\n tKVrV: cute.Tensor,\n tKVcV: cute.Tensor,\n sAlpha: cute.Tensor,\n alpha_stage: cutlass.Int32,\n is_final_block: bool,\n B: cutlass.Int32,\n ):\n if cutlass.const_expr(self.needs_alpha):\n alpha_cumlog = sAlpha[None, AlphaProcessor.CUMSUM_LOG, alpha_stage]\n block_log = cutlass.Float32(alpha_cumlog[B - cutlass.Int32(1)])\n for i in cutlass.range_constexpr(cute.size(tKVrV)):\n _, tok = tKVcV[i]\n coeff = cute.math.exp2(\n block_log - cutlass.Float32(alpha_cumlog[tok]), fastmath=True\n )\n if cutlass.const_expr(is_final_block):\n if tok >= B:\n coeff = cutlass.Float32(0.0)\n tKVrV[i] = self.dtype(cutlass.Float32(tKVrV[i]) * coeff)\n else:\n for i in cutlass.range_constexpr(cute.size(tKVrV)):\n _, tok = tKVcV[i]\n if cutlass.const_expr(is_final_block):\n if tok >= B:\n tKVrV[i] = self.dtype(0.0)\n\n # ─── o_store ──────────────────────────────────────────────────────────────\n\n @cute.jit\n def o_store(\n self,\n tOrO: cute.Tensor,\n tOsO: cute.Tensor,\n o_tiled_copy_r2s,\n o_thr_copy_r2s,\n ):\n tOrO_f16 = cute.make_fragment_like(tOrO, self.dtype)\n for i in cutlass.range_constexpr(cute.size(tOrO)):\n tOrO_f16[i] = self.dtype(tOrO[i])\n tOrO_cv = o_thr_copy_r2s.retile(tOrO_f16)\n cute.arch.fence_view_async_shared()\n cute.copy(o_tiled_copy_r2s, tOrO_cv, tOsO)\n cute.arch.fence_view_async_shared()\n\n # ─── TMA load helpers ────────────────────────────────────────────────────\n\n @cute.jit\n def load_qkv_tma(\n self,\n sQ_SD: cute.Tensor,\n sK_DS: cute.Tensor,\n sV_DS: cute.Tensor,\n tma_atom_q: cute.CopyAtom,\n tma_tensor_q: cute.Tensor,\n tma_atom_k: cute.CopyAtom,\n tma_tensor_k: cute.Tensor,\n tma_atom_v: cute.CopyAtom,\n tma_tensor_v: cute.Tensor,\n q_pipeline,\n q_producer_state,\n k_pipeline,\n k_producer_state,\n v_pipeline,\n v_producer_state,\n blk: cutlass.Int32,\n tok_start,\n q_head_idx: cutlass.Int32,\n k_head_idx: cutlass.Int32,\n v_head_idx: cutlass.Int32,\n ):\n blk_tok = tok_start + blk * cutlass.Int32(self.BLK_KV)\n\n sK = sK_DS[None, None, k_producer_state.index]\n mK = cute.domain_offset(\n (cutlass.Int32(0), blk_tok),\n tma_tensor_k[None, None, k_head_idx],\n )\n gK = cute.zipped_divide(mK, (self.D, self.BLK_KV))[\n ((None, None), (cutlass.Int32(0), cutlass.Int32(0)))\n ]\n tKsK, tKgK = cpasync.tma_partition(\n tma_atom_k,\n 0,\n cute.make_layout(1),\n cute.group_modes(sK, 0, 2),\n cute.group_modes(gK, 0, 2),\n )\n k_pipeline.producer_acquire(k_producer_state)\n cute.copy(\n tma_atom_k,\n tKgK,\n tKsK,\n tma_bar_ptr=k_pipeline.producer_get_barrier(k_producer_state),\n )\n k_pipeline.producer_commit(k_producer_state)\n k_producer_state.advance()\n\n sQ = sQ_SD[None, None, q_producer_state.index]\n mQ = cute.domain_offset(\n (blk_tok, cutlass.Int32(0)),\n tma_tensor_q[None, None, q_head_idx],\n )\n gQ = cute.zipped_divide(mQ, (self.BLK_Q, self.D))[\n ((None, None), (cutlass.Int32(0), cutlass.Int32(0)))\n ]\n tQsQ, tQgQ = cpasync.tma_partition(\n tma_atom_q,\n 0,\n cute.make_layout(1),\n cute.group_modes(sQ, 0, 2),\n cute.group_modes(gQ, 0, 2),\n )\n q_pipeline.producer_acquire(q_producer_state)\n cute.copy(\n tma_atom_q,\n tQgQ,\n tQsQ,\n tma_bar_ptr=q_pipeline.producer_get_barrier(q_producer_state),\n )\n q_pipeline.producer_commit(q_producer_state)\n q_producer_state.advance()\n\n sV = sV_DS[None, None, v_producer_state.index]\n mV = cute.domain_offset(\n (cutlass.Int32(0), blk_tok),\n tma_tensor_v[None, None, v_head_idx],\n )\n gV = cute.zipped_divide(mV, (self.D, self.BLK_KV))[\n ((None, None), (cutlass.Int32(0), cutlass.Int32(0)))\n ]\n tVsV, tVgV = cpasync.tma_partition(\n tma_atom_v,\n 0,\n cute.make_layout(1),\n cute.group_modes(sV, 0, 2),\n cute.group_modes(gV, 0, 2),\n )\n v_pipeline.producer_acquire(v_producer_state)\n cute.copy(\n tma_atom_v,\n tVgV,\n tVsV,\n tma_bar_ptr=v_pipeline.producer_get_barrier(v_producer_state),\n )\n v_pipeline.producer_commit(v_producer_state)\n v_producer_state.advance()\n return q_producer_state, k_producer_state, v_producer_state\n\n # ─── load_alpha ───────────────────────────────────────────────────────────\n # Translates FlatMainloopTmaWarpSpecializedDeltaRule::load_alpha (scalar load).\n # Caller must sync before calling AlphaProcessor on the loaded data.\n\n @cute.jit\n def load_alpha(\n self,\n sAlpha: cute.Tensor,\n g_alpha: cute.Tensor,\n blk_tok: cutlass.Int32,\n tok_end,\n sab_head_idx: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n alpha_stage: cutlass.Int32,\n ):\n lane_id = cute.arch.lane_idx()\n sAlpha_k = sAlpha[None, None, alpha_stage]\n num_iters = self.BLK_Q // 32\n for i in cutlass.range_constexpr(num_iters):\n row = cutlass.Int32(i * 32) + lane_id\n tok = blk_tok + row\n if tok < tok_end:\n sAlpha_k[row, AlphaProcessor.CUMSUM_LOG] = g_alpha[\n tok * num_sab_heads + sab_head_idx\n ]\n else:\n sAlpha_k[row, AlphaProcessor.CUMSUM_LOG] = cutlass.Float32(1.0)\n\n # ─── load_beta ────────────────────────────────────────────────────────────\n # Translates FlatMainloopTmaWarpSpecializedDeltaRule::load_beta.\n\n @cute.jit\n def load_beta(\n self,\n sBeta: cute.Tensor,\n g_beta: cute.Tensor,\n blk_tok: cutlass.Int32,\n tok_end,\n sab_head_idx: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n beta_stage: cutlass.Int32,\n ):\n lane_id = cute.arch.lane_idx()\n sBeta_k = sBeta[None, beta_stage]\n num_iters = self.BLK_KV // 32\n for i in cutlass.range_constexpr(num_iters):\n row = cutlass.Int32(i * 32) + lane_id\n tok = blk_tok + row\n if tok < tok_end:\n sBeta_k[row] = g_beta[tok * num_sab_heads + sab_head_idx]\n else:\n sBeta_k[row] = cutlass.Float32(0.0)\n\n # ─── kv_load / kv_store ───────────────────────────────────────────────────\n\n @cute.jit\n def kv_load(\n self,\n tKVrKV: cute.Tensor,\n gKV: cute.Tensor,\n kv_tiled_mma,\n thread_idx: cutlass.Int32,\n ):\n copy_atom_kv = cute.make_copy_atom(\n cute.nvgpu.CopyUniversalOp(), gKV.element_type\n )\n tiled_copy_kv = cute.make_tiled_copy_C(copy_atom_kv, kv_tiled_mma)\n thr_copy_kv = tiled_copy_kv.get_slice(thread_idx)\n tKVgKV = thr_copy_kv.partition_S(select_tensor_10(gKV))\n tKVrKV_storage = cute.make_rmem_tensor_like(tKVrKV, gKV.element_type)\n cute.copy(tiled_copy_kv, tKVgKV, tKVrKV_storage)\n tKVrKV.store(tKVrKV_storage.load().to(self.acc_dtype))\n\n @cute.jit\n def kv_store(\n self,\n tKVrKV: cute.Tensor,\n gKV: cute.Tensor,\n kv_tiled_mma,\n thread_idx: cutlass.Int32,\n ):\n copy_atom_kv = cute.make_copy_atom(\n cute.nvgpu.CopyUniversalOp(), gKV.element_type\n )\n tiled_copy_kv = cute.make_tiled_copy_C(copy_atom_kv, kv_tiled_mma)\n thr_copy_kv = tiled_copy_kv.get_slice(thread_idx)\n tKVgKV = thr_copy_kv.partition_D(select_tensor_10(gKV))\n tKVrKV_storage = cute.make_rmem_tensor_like(tKVrKV, gKV.element_type)\n tKVrKV_storage.store(tKVrKV.load().to(gKV.element_type))\n cute.copy(tiled_copy_kv, tKVrKV_storage, tKVgKV)\n\n @cute.jit\n def maybe_store_checkpoint(\n self,\n tKVrKV: cute.Tensor,\n g_state_checkpoints: cute.Tensor,\n checkpoint_cu_starts: cute.Tensor,\n checkpoint_every_n_tokens: cutlass.Int32,\n kv_tiled_mma,\n thread_idx: cutlass.Int32,\n seq_idx: cutlass.Int32,\n o_head_idx: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n total_checkpoints: cutlass.Int32,\n block_end: cutlass.Int32,\n seq_len: cutlass.Int32,\n ):\n if cutlass.const_expr(self.needs_checkpointing):\n if (\n block_end <= seq_len\n and block_end % checkpoint_every_n_tokens == cutlass.Int32(0)\n ):\n checkpoint_idx = (\n cutlass.Int32(checkpoint_cu_starts[seq_idx])\n + block_end // checkpoint_every_n_tokens\n - cutlass.Int32(1)\n )\n checkpoint_layout = cute.make_ordered_layout(\n (self.D, self.D, num_sab_heads, total_checkpoints),\n order=(0, 1, 2, 3),\n )\n mCheckpoint = cute.make_tensor(\n g_state_checkpoints.iterator, checkpoint_layout\n )\n gCheckpointKV = mCheckpoint[None, None, o_head_idx, checkpoint_idx]\n self.kv_store(tKVrKV, gCheckpointKV, kv_tiled_mma, thread_idx)\n\n # ─── compute_loop_body ───────────────────────────────────────────────────\n # Translates the C++ compute_loop_body lambda captured inside compute().\n # Called by Math WGs (tidx >= 128) for one block iteration.\n\n @cute.jit\n def compute_loop_body(\n self,\n # Smem tensors (staged; caller indexes the active stage)\n sQ_SD: cute.Tensor, # (BlkQ, D, StagesQ) – row-major atom, swizzled\n sK_SD: cute.Tensor, # (BlkKV, D, StagesK) – same atom\n sK_DS: cute.Tensor, # (D, BlkKV, StagesK) – K transposed\n sV_DS: cute.Tensor, # (D, BlkKV, StagesV) – V transposed\n sQK: cute.Tensor, # (BlkQ, BlkKV, StagesQK)\n sKK_inv: cute.Tensor, # (BlkKV, BlkKV, StagesKK)\n sKK_opd: cute.Tensor, # sKK_inv storage recast as Element\n sO: cute.Tensor, # O output smem (staged)\n sAlpha: cute.Tensor, # (BlkQ, AlphaProcessor.NUM_CHANNELS, StagesAlpha) or zero-shaped\n kv_tiled_mma,\n # Mainloop pipelines and active read states\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n v_pipeline,\n v_consumer_state,\n o_pipeline,\n o_producer_state,\n qk_pipeline,\n qk_consumer_state,\n kk_pipeline,\n kk_consumer_state,\n alpha_pipeline,\n alpha_consumer_state,\n # Compile-time flags\n is_first_block: bool,\n is_final_block: bool,\n # Valid token count for masking on final block\n B: cutlass.Int32,\n # Running KV state (D×D fp32, in registers across all blocks)\n tKVrKV: cute.Tensor,\n # Scale factor\n scale: cutlass.Float32,\n # WG role: MathWarpGroupRole.STATE0 or MathWarpGroupRole.STATE1.\n wg_idx: cutlass.Int32,\n ):\n tidx, _, _ = cute.arch.thread_idx()\n thread_idx = tidx - cutlass.Int32(128) # relative to compute threads\n # ── TiledMMAs ─────────────────────────────────────────────────────────\n blk_q = cute.size(sQ_SD, mode=[0])\n blk_kv = cute.size(sK_SD, mode=[0])\n d = cute.size(sQ_SD, mode=[1])\n mma_atom_o1 = cute.make_mma_atom(\n warpgroup.MmaF16BF16Op(\n self.dtype,\n self.acc_dtype,\n (64, blk_q, 16),\n warpgroup.OperandSource.RMEM,\n cute.nvgpu.OperandMajorMode.K,\n cute.nvgpu.OperandMajorMode.K,\n )\n )\n mma_atom_o2 = cute.make_mma_atom(\n warpgroup.MmaF16BF16Op(\n self.dtype,\n self.acc_dtype,\n (64, blk_q, 16),\n warpgroup.OperandSource.RMEM,\n cute.nvgpu.OperandMajorMode.K,\n cute.nvgpu.OperandMajorMode.K,\n )\n )\n mma_atom_sk = cute.make_mma_atom(\n warpgroup.MmaF16BF16Op(\n self.dtype,\n self.acc_dtype,\n (64, blk_kv, 16),\n warpgroup.OperandSource.RMEM,\n cute.nvgpu.OperandMajorMode.K,\n cute.nvgpu.OperandMajorMode.K,\n )\n )\n mma_atom_newv = cute.make_mma_atom(\n warpgroup.MmaF16BF16Op(\n self.dtype,\n self.acc_dtype,\n (64, blk_kv, 16),\n warpgroup.OperandSource.RMEM,\n cute.nvgpu.OperandMajorMode.K,\n cute.nvgpu.OperandMajorMode.K,\n )\n )\n\n # O1/O2/SK/NewV: two state warpgroups cooperate as in the C++ Hopper GMMA path.\n o1_tiled_mma = cute.make_tiled_mma(mma_atom_o1, cute.make_layout((2, 1, 1)))\n o2_tiled_mma = cute.make_tiled_mma(mma_atom_o2, cute.make_layout((2, 1, 1)))\n sk_tiled_mma = cute.make_tiled_mma(mma_atom_sk, cute.make_layout((2, 1, 1)))\n newv_tiled_mma = cute.make_tiled_mma(mma_atom_newv, cute.make_layout((2, 1, 1)))\n\n # ── Thread slices ─────────────────────────────────────────────────────\n sk_thr_mma = sk_tiled_mma.get_slice(thread_idx)\n newv_thr_mma = newv_tiled_mma.get_slice(thread_idx)\n o1_thr_mma = o1_tiled_mma.get_slice(thread_idx)\n o2_thr_mma = o2_tiled_mma.get_slice(thread_idx)\n kv_thr_mma = kv_tiled_mma.get_slice(thread_idx)\n\n # ── Copy atoms ────────────────────────────────────────────────────────\n ldsm_t4 = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(transpose=True, num_matrices=4), self.dtype\n )\n\n # ── SK copies ─────────────────────────────────────────────────────────\n # SK C: V loaded from sV_DS (col-major D×BlkKV) with LDSM_T.\n sk_tiled_copy_C = cute.make_tiled_copy_C(ldsm_t4, sk_tiled_mma)\n sk_thr_copy_C = sk_tiled_copy_C.get_slice(thread_idx)\n tSKsK = sk_thr_mma.partition_B(sK_SD)\n tSKrK = sk_thr_mma.make_fragment_B(tSKsK)\n\n # ── NewV copies ───────────────────────────────────────────────────────\n tNewVsB = newv_thr_mma.partition_B(sKK_opd)\n tNewVrB = newv_thr_mma.make_fragment_B(tNewVsB)\n\n # ── KV copies ─────────────────────────────────────────────────────────\n tKVsK = kv_thr_mma.partition_B(sK_DS)\n tKVrK = kv_thr_mma.make_fragment_B(tKVsK)\n\n # ── O1/O2 copies ──────────────────────────────────────────────────────\n tOsQ = o1_thr_mma.partition_B(sQ_SD)\n tOrQ = o1_thr_mma.make_fragment_B(tOsQ)\n tOsQK = o2_thr_mma.partition_B(sQK)\n tOrQK = o2_thr_mma.make_fragment_B(tOsQK)\n\n # ── O store (R→S STSM) ────────────────────────────────────────────────\n o_stsm = cute.make_copy_atom(\n warp.StMatrix8x8x16bOp(transpose=True, num_matrices=4), self.dtype\n )\n o_tiled_copy_r2s = cute.make_tiled_copy_C(o_stsm, o1_tiled_mma)\n o_thr_copy_r2s = o_tiled_copy_r2s.get_slice(thread_idx)\n tOsO = o_thr_copy_r2s.partition_D(sO)\n\n # ── Coordinate tensors for masking / alpha/beta indexing ──────────────\n cO = cute.make_identity_tensor((d, blk_q))\n tOcO = o1_thr_mma.partition_C(cO)\n cSK = cute.make_identity_tensor((d, blk_kv))\n tSKcSK = sk_thr_mma.partition_C(cSK)\n cV = cute.make_identity_tensor((d, blk_kv))\n tKVcV = kv_thr_mma.partition_A(cV)\n\n # ── O1: KV_state @ Q (both state WGs, skip on first block) ───────────\n q_pipeline.consumer_wait(q_consumer_state)\n if cutlass.const_expr(self.needs_alpha):\n alpha_pipeline.consumer_wait(alpha_consumer_state)\n cute.arch.fence_view_async_shared()\n tOrO = o1_thr_mma.make_fragment_C(o1_thr_mma.partition_shape_C((d, blk_q)))\n if cutlass.const_expr(not is_first_block):\n tOrKV = SM90.make_acc_into_op(tKVrKV, o1_tiled_mma, self.dtype)\n SM90.warpgroup_fence_operand(tOrKV)\n SM90.warpgroup_fence_operand(tOrO)\n cute.nvgpu.warpgroup.fence()\n self._math_order_wait(wg_idx)\n SM90.wgmma_gemm_zero_acc(\n o1_tiled_mma,\n tOrO,\n tOrKV,\n tOrQ[None, None, None, q_consumer_state.index],\n )\n cute.nvgpu.warpgroup.commit_group()\n self._math_order_notify(wg_idx)\n cute.nvgpu.warpgroup.wait_group(0)\n self.o1_epi(tOrO, tOcO, sAlpha, alpha_consumer_state.index, scale)\n q_pipeline.consumer_release(q_consumer_state)\n q_consumer_state.advance()\n\n # ── SK: KV_state @ K^T (result negated below via V - SK) ─────────────\n k_pipeline.consumer_wait(k_consumer_state)\n tSKrSK = sk_thr_mma.make_fragment_C(sk_thr_mma.partition_shape_C((d, blk_kv)))\n if cutlass.const_expr(not is_first_block):\n tSKrS = SM90.make_acc_into_op(tKVrKV, sk_tiled_mma, self.dtype)\n SM90.warpgroup_fence_operand(tSKrSK)\n SM90.warpgroup_fence_operand(tSKrS)\n cute.nvgpu.warpgroup.fence()\n self._math_order_wait(wg_idx)\n SM90.wgmma_gemm_zero_acc(\n sk_tiled_mma,\n tSKrSK,\n tSKrS,\n tSKrK[None, None, None, k_consumer_state.index],\n )\n cute.nvgpu.warpgroup.commit_group()\n self._math_order_notify(wg_idx)\n cute.nvgpu.warpgroup.wait_group(0)\n\n # ── Load V from smem ──────────────────────────────────────────────────\n v_pipeline.consumer_wait(v_consumer_state)\n tSKrV = self.sk_load_v(\n tSKrSK,\n sV_DS,\n sk_tiled_copy_C,\n sk_thr_copy_C,\n v_consumer_state.index,\n )\n\n # sk_epi + V - SK (SK=0 on first block, so V - SK = V)\n if cutlass.const_expr(not is_first_block):\n self.sk_epi(tSKrSK, tSKcSK, sAlpha, alpha_consumer_state.index)\n for i in cutlass.range_constexpr(cute.size(tSKrV)):\n tSKrV[i] = tSKrV[i] - self.dtype(tSKrSK[i])\n\n # ── NewV = (V - SK) @ T^T (ordered: WG0 first) ──────────────────────\n tNewVrA = SM90.make_acc_into_op(tSKrV, newv_tiled_mma, self.dtype)\n tNewVrC = newv_thr_mma.make_fragment_C(\n newv_thr_mma.partition_shape_C((d, blk_kv))\n )\n kk_pipeline.consumer_wait(kk_consumer_state)\n SM90.warpgroup_fence_operand(tNewVrA)\n SM90.warpgroup_fence_operand(tNewVrC)\n cute.nvgpu.warpgroup.fence()\n self._math_order_wait(wg_idx)\n SM90.wgmma_gemm_zero_acc(\n newv_tiled_mma,\n tNewVrC,\n tNewVrA,\n tNewVrB[None, None, None, kk_consumer_state.index],\n )\n cute.nvgpu.warpgroup.commit_group()\n self._math_order_notify(wg_idx)\n cute.nvgpu.warpgroup.wait_group(0)\n v_pipeline.consumer_release(v_consumer_state)\n v_consumer_state.advance()\n kk_pipeline.consumer_release(kk_consumer_state)\n kk_consumer_state.advance()\n\n # ── O2 = O1 + NewV @ QK (ordered: WG0 first) ────────────────────────\n tOrV_or_tKVrV = SM90.make_acc_into_op(tNewVrC, kv_tiled_mma, self.dtype)\n qk_pipeline.consumer_wait(qk_consumer_state)\n SM90.warpgroup_fence_operand(tOrV_or_tKVrV)\n SM90.warpgroup_fence_operand(tOrO)\n cute.nvgpu.warpgroup.fence()\n self._math_order_wait(wg_idx)\n SM90.wgmma_gemm(\n o2_tiled_mma,\n tOrO,\n tOrV_or_tKVrV,\n tOrQK[None, None, None, qk_consumer_state.index],\n not is_first_block,\n )\n cute.nvgpu.warpgroup.commit_group()\n self._math_order_notify(wg_idx)\n cute.nvgpu.warpgroup.wait_group(0)\n qk_pipeline.consumer_release(qk_consumer_state)\n qk_consumer_state.advance()\n\n # ── O store to smem ───────────────────────────────────────────────────\n o_pipeline.producer_acquire(o_producer_state)\n self.o_store(\n tOrO,\n tOsO[None, None, None, o_producer_state.index],\n o_tiled_copy_r2s,\n o_thr_copy_r2s,\n )\n o_pipeline.producer_commit(o_producer_state)\n o_producer_state.advance()\n\n # ── KV state update ───────────────────────────────────────────────────\n block_coeff = cutlass.Float32(1.0)\n if cutlass.const_expr(self.needs_alpha):\n block_coeff = cutlass.Float32(\n sAlpha[\n B - cutlass.Int32(1),\n AlphaProcessor.CUMPROD,\n alpha_consumer_state.index,\n ]\n )\n\n for i in cutlass.range(cute.size(tKVrKV), unroll_full=True):\n tKVrKV[i] = block_coeff * tKVrKV[i]\n\n self.kv_decay_v(\n tOrV_or_tKVrV, tKVcV, sAlpha, alpha_consumer_state.index, is_final_block, B\n )\n\n # KV += NewV @ K\n SM90.warpgroup_fence_operand(tOrV_or_tKVrV)\n SM90.warpgroup_fence_operand(tKVrKV)\n cute.nvgpu.warpgroup.fence()\n self._math_order_wait(wg_idx)\n SM90.wgmma_gemm(\n kv_tiled_mma,\n tKVrKV,\n tOrV_or_tKVrV,\n tKVrK[None, None, None, k_consumer_state.index],\n True,\n )\n cute.nvgpu.warpgroup.commit_group()\n self._math_order_notify(wg_idx)\n cute.nvgpu.warpgroup.wait_group(0)\n k_pipeline.consumer_release(k_consumer_state)\n k_consumer_state.advance()\n if cutlass.const_expr(self.needs_alpha):\n alpha_pipeline.consumer_release(alpha_consumer_state)\n alpha_consumer_state.advance()\n return (\n q_consumer_state,\n k_consumer_state,\n v_consumer_state,\n o_producer_state,\n qk_consumer_state,\n kk_consumer_state,\n alpha_consumer_state,\n )\n\n # ─── Warp role entry points ──────────────────────────────────────────────\n # The current DSL bridge still uses CTA-wide sync epochs, but each role owns\n # its own loop, matching the C++ warp-specialized dispatch shape.\n\n @cute.jit\n def run_load_qkv_role(\n self,\n sQ_SD: cute.Tensor,\n sK_DS: cute.Tensor,\n sV_DS: cute.Tensor,\n tma_atom_q: cute.CopyAtom,\n tma_tensor_q: cute.Tensor,\n tma_atom_k: cute.CopyAtom,\n tma_tensor_k: cute.Tensor,\n tma_atom_v: cute.CopyAtom,\n tma_tensor_v: cute.Tensor,\n q_pipeline,\n k_pipeline,\n v_pipeline,\n num_blocks: cutlass.Int32,\n tok_start,\n q_head_idx: cutlass.Int32,\n k_head_idx: cutlass.Int32,\n v_head_idx: cutlass.Int32,\n ):\n q_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.q_stage\n )\n k_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.k_stage\n )\n v_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.v_stage\n )\n for blk in cutlass.range(num_blocks, unroll=1):\n (\n q_producer_state,\n k_producer_state,\n v_producer_state,\n ) = self.load_qkv_tma(\n sQ_SD,\n sK_DS,\n sV_DS,\n tma_atom_q,\n tma_tensor_q,\n tma_atom_k,\n tma_tensor_k,\n tma_atom_v,\n tma_tensor_v,\n q_pipeline,\n q_producer_state,\n k_pipeline,\n k_producer_state,\n v_pipeline,\n v_producer_state,\n blk,\n tok_start,\n q_head_idx,\n k_head_idx,\n v_head_idx,\n )\n\n @cute.jit\n def run_load_alpha_role(\n self,\n sAlpha: cute.Tensor,\n g_alpha: cute.Tensor,\n alpha_pipeline,\n scale: cutlass.Float32,\n num_blocks: cutlass.Int32,\n tok_start,\n tok_end,\n sab_head_idx: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n ):\n alpha_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.alpha_beta_stage\n )\n for blk in cutlass.range(num_blocks, unroll=1):\n blk_tok = tok_start + blk * cutlass.Int32(self.BLK_Q)\n if cutlass.const_expr(self.needs_alpha):\n alpha_pipeline.producer_acquire(alpha_producer_state)\n cute.arch.fence_view_async_shared()\n self.load_alpha(\n sAlpha,\n g_alpha,\n blk_tok,\n tok_end,\n sab_head_idx,\n num_sab_heads,\n alpha_producer_state.index,\n )\n AlphaProcessor().run(\n sAlpha[None, None, alpha_producer_state.index], scale\n )\n cute.arch.fence_view_async_shared()\n alpha_pipeline.producer_commit(alpha_producer_state)\n alpha_producer_state.advance()\n\n @cute.jit\n def run_load_beta_role(\n self,\n sBeta: cute.Tensor,\n g_beta: cute.Tensor,\n beta_pipeline,\n num_blocks: cutlass.Int32,\n tok_start,\n tok_end,\n sab_head_idx: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n ):\n beta_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.alpha_beta_stage\n )\n for blk in cutlass.range(num_blocks, unroll=1):\n blk_tok = tok_start + blk * cutlass.Int32(self.BLK_KV)\n if cutlass.const_expr(self.needs_beta):\n beta_pipeline.producer_acquire(beta_producer_state)\n cute.arch.fence_view_async_shared()\n self.load_beta(\n sBeta,\n g_beta,\n blk_tok,\n tok_end,\n sab_head_idx,\n num_sab_heads,\n beta_producer_state.index,\n )\n cute.arch.fence_view_async_shared()\n beta_pipeline.producer_commit(beta_producer_state)\n beta_producer_state.advance()\n\n @cute.jit\n def run_state_math_role(\n self,\n sQ_SD: cute.Tensor,\n sK_SD: cute.Tensor,\n sK_DS: cute.Tensor,\n sV_DS: cute.Tensor,\n sQK: cute.Tensor,\n sKK_inv: cute.Tensor,\n sKK_opd: cute.Tensor,\n sO: cute.Tensor,\n sAlpha: cute.Tensor,\n q_pipeline,\n k_pipeline,\n v_pipeline,\n o_pipeline,\n qk_pipeline,\n kk_pipeline,\n alpha_pipeline,\n g_state: cute.Tensor,\n g_init_state: cute.Tensor,\n g_state_indices: cute.Tensor,\n g_state_checkpoints: cute.Tensor,\n checkpoint_cu_starts: cute.Tensor,\n work_desc: WorkDesc,\n scale: cutlass.Float32,\n wg_idx: cutlass.Int32,\n math_tidx: cutlass.Int32,\n num_blocks: cutlass.Int32,\n num_q_heads: cutlass.Int32,\n num_v_heads: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n num_seqs: cutlass.Int32,\n total_checkpoints: cutlass.Int32,\n checkpoint_every_n_tokens: cutlass.Int32,\n ):\n self._math_order_init(wg_idx)\n q_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.q_stage\n )\n k_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.k_stage\n )\n v_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.v_stage\n )\n o_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.o_stage\n )\n qk_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.qk_stage\n )\n kk_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.kk_stage\n )\n alpha_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.alpha_beta_stage\n )\n\n kv_tiled_mma = cute.make_tiled_mma(\n cute.make_mma_atom(\n warpgroup.MmaF16BF16Op(\n self.dtype,\n self.acc_dtype,\n (64, self.D, 16),\n warpgroup.OperandSource.RMEM,\n cute.nvgpu.OperandMajorMode.K,\n cute.nvgpu.OperandMajorMode.MN,\n )\n ),\n cute.make_layout((2, 1, 1)),\n )\n kv_thr_mma = kv_tiled_mma.get_slice(math_tidx)\n tKVrKV = kv_thr_mma.make_fragment_C(\n kv_thr_mma.partition_shape_C((self.D, self.D))\n )\n tKVrKV.fill(self.acc_dtype(0.0))\n\n packed_state_layout = cute.make_ordered_layout(\n (self.D, self.D, num_sab_heads, num_seqs), order=(0, 1, 2, 3)\n )\n state_ref_shape = (g_state.shape[0], g_state.shape[1], self.D, self.D)\n state_ref_layout = cute.make_layout(state_ref_shape, stride=g_state.stride)\n indexed_state_layout = cute.select(state_ref_layout, mode=[3, 2, 1, 0])\n state_idx = work_desc.seq_idx\n if cutlass.const_expr(self.use_state_indices):\n state_idx = cutlass.Int32(g_state_indices[work_desc.seq_idx])\n state_layout = indexed_state_layout\n else:\n state_layout = packed_state_layout\n o_head_idx = work_desc.o_head_idx(num_q_heads, num_v_heads)\n mState = cute.make_tensor(g_state.iterator, state_layout)\n gStateKV = mState[None, None, o_head_idx, state_idx]\n if cutlass.const_expr(self.needs_init_state):\n init_state_ref_layout = cute.make_layout(\n state_ref_shape, stride=g_init_state.stride\n )\n indexed_init_state_layout = cute.select(\n init_state_ref_layout, mode=[3, 2, 1, 0]\n )\n if cutlass.const_expr(self.use_state_indices):\n init_state_layout = indexed_init_state_layout\n else:\n init_state_layout = packed_state_layout\n mInitState = cute.make_tensor(g_init_state.iterator, init_state_layout)\n gInitKV = mInitState[None, None, o_head_idx, state_idx]\n self.kv_load(tKVrKV, gInitKV, kv_tiled_mma, math_tidx)\n\n first_B = work_desc.seq_len\n if first_B > cutlass.Int32(self.BLK_KV):\n first_B = cutlass.Int32(self.BLK_KV)\n if cutlass.const_expr(self.needs_init_state):\n (\n q_consumer_state,\n k_consumer_state,\n v_consumer_state,\n o_producer_state,\n qk_consumer_state,\n kk_consumer_state,\n alpha_consumer_state,\n ) = self.compute_loop_body(\n sQ_SD,\n sK_SD,\n sK_DS,\n sV_DS,\n sQK,\n sKK_inv,\n sKK_opd,\n sO,\n sAlpha,\n kv_tiled_mma,\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n v_pipeline,\n v_consumer_state,\n o_pipeline,\n o_producer_state,\n qk_pipeline,\n qk_consumer_state,\n kk_pipeline,\n kk_consumer_state,\n alpha_pipeline,\n alpha_consumer_state,\n False,\n True,\n first_B,\n tKVrKV,\n scale,\n wg_idx,\n )\n else:\n (\n q_consumer_state,\n k_consumer_state,\n v_consumer_state,\n o_producer_state,\n qk_consumer_state,\n kk_consumer_state,\n alpha_consumer_state,\n ) = self.compute_loop_body(\n sQ_SD,\n sK_SD,\n sK_DS,\n sV_DS,\n sQK,\n sKK_inv,\n sKK_opd,\n sO,\n sAlpha,\n kv_tiled_mma,\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n v_pipeline,\n v_consumer_state,\n o_pipeline,\n o_producer_state,\n qk_pipeline,\n qk_consumer_state,\n kk_pipeline,\n kk_consumer_state,\n alpha_pipeline,\n alpha_consumer_state,\n True,\n True,\n first_B,\n tKVrKV,\n scale,\n wg_idx,\n )\n self.maybe_store_checkpoint(\n tKVrKV,\n g_state_checkpoints,\n checkpoint_cu_starts,\n checkpoint_every_n_tokens,\n kv_tiled_mma,\n math_tidx,\n work_desc.seq_idx,\n o_head_idx,\n num_sab_heads,\n total_checkpoints,\n cutlass.Int32(self.BLK_KV),\n work_desc.seq_len,\n )\n\n for blk in cutlass.range(\n cutlass.Int32(1), num_blocks - cutlass.Int32(1), cutlass.Int32(1), unroll=1\n ):\n (\n q_consumer_state,\n k_consumer_state,\n v_consumer_state,\n o_producer_state,\n qk_consumer_state,\n kk_consumer_state,\n alpha_consumer_state,\n ) = self.compute_loop_body(\n sQ_SD,\n sK_SD,\n sK_DS,\n sV_DS,\n sQK,\n sKK_inv,\n sKK_opd,\n sO,\n sAlpha,\n kv_tiled_mma,\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n v_pipeline,\n v_consumer_state,\n o_pipeline,\n o_producer_state,\n qk_pipeline,\n qk_consumer_state,\n kk_pipeline,\n kk_consumer_state,\n alpha_pipeline,\n alpha_consumer_state,\n False,\n False,\n cutlass.Int32(self.BLK_KV),\n tKVrKV,\n scale,\n wg_idx,\n )\n self.maybe_store_checkpoint(\n tKVrKV,\n g_state_checkpoints,\n checkpoint_cu_starts,\n checkpoint_every_n_tokens,\n kv_tiled_mma,\n math_tidx,\n work_desc.seq_idx,\n o_head_idx,\n num_sab_heads,\n total_checkpoints,\n (blk + cutlass.Int32(1)) * cutlass.Int32(self.BLK_KV),\n work_desc.seq_len,\n )\n\n if num_blocks != cutlass.Int32(1):\n last_blk = num_blocks - cutlass.Int32(1)\n last_B = work_desc.seq_len - last_blk * cutlass.Int32(self.BLK_KV)\n (\n q_consumer_state,\n k_consumer_state,\n v_consumer_state,\n o_producer_state,\n qk_consumer_state,\n kk_consumer_state,\n alpha_consumer_state,\n ) = self.compute_loop_body(\n sQ_SD,\n sK_SD,\n sK_DS,\n sV_DS,\n sQK,\n sKK_inv,\n sKK_opd,\n sO,\n sAlpha,\n kv_tiled_mma,\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n v_pipeline,\n v_consumer_state,\n o_pipeline,\n o_producer_state,\n qk_pipeline,\n qk_consumer_state,\n kk_pipeline,\n kk_consumer_state,\n alpha_pipeline,\n alpha_consumer_state,\n False,\n True,\n last_B,\n tKVrKV,\n scale,\n wg_idx,\n )\n self.maybe_store_checkpoint(\n tKVrKV,\n g_state_checkpoints,\n checkpoint_cu_starts,\n checkpoint_every_n_tokens,\n kv_tiled_mma,\n math_tidx,\n work_desc.seq_idx,\n o_head_idx,\n num_sab_heads,\n total_checkpoints,\n (last_blk + cutlass.Int32(1)) * cutlass.Int32(self.BLK_KV),\n work_desc.seq_len,\n )\n self.kv_store(tKVrKV, gStateKV, kv_tiled_mma, math_tidx)\n\n @cute.jit\n def run_aux_loop_body(\n self,\n sQK: cute.Tensor,\n sKK_inv: cute.Tensor,\n sKK_opd: cute.Tensor,\n sAlpha: cute.Tensor,\n sBeta: cute.Tensor,\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n qk_pipeline,\n qk_producer_state,\n kk_pipeline,\n kk_producer_state,\n alpha_pipeline,\n alpha_consumer_state,\n beta_pipeline,\n beta_consumer_state,\n work_desc: WorkDesc,\n scale: cutlass.Float32,\n blk: cutlass.Int32,\n is_final_block: bool,\n qk_tiled_mma,\n kk_tiled_mma,\n tQKrQ: cute.Tensor,\n tQKrK: cute.Tensor,\n tKKrA: cute.Tensor,\n tKKrB: cute.Tensor,\n tQKcMqk: cute.Tensor,\n tKKcMkk: cute.Tensor,\n aux_tidx: cutlass.Int32,\n ):\n B = cutlass.Int32(self.BLK_KV)\n if cutlass.const_expr(is_final_block):\n B = work_desc.seq_len - blk * cutlass.Int32(self.BLK_KV)\n\n k_pipeline.consumer_wait(k_consumer_state)\n\n tKKrKK = kk_tiled_mma.get_slice(aux_tidx).make_fragment_C(\n kk_tiled_mma.get_slice(aux_tidx).partition_shape_C(\n (self.BLK_KV, self.BLK_KV)\n )\n )\n cute.nvgpu.warpgroup.fence()\n SM90.wgmma_gemm_zero_acc(\n kk_tiled_mma,\n tKKrKK,\n tKKrA[None, None, None, k_consumer_state.index],\n tKKrB[None, None, None, k_consumer_state.index],\n )\n cute.nvgpu.warpgroup.commit_group()\n\n q_pipeline.consumer_wait(q_consumer_state)\n tQKrQK = qk_tiled_mma.get_slice(aux_tidx).make_fragment_C(\n qk_tiled_mma.get_slice(aux_tidx).partition_shape_C(\n (self.BLK_Q, self.BLK_KV)\n )\n )\n cute.nvgpu.warpgroup.fence()\n SM90.wgmma_gemm_zero_acc(\n qk_tiled_mma,\n tQKrQK,\n tQKrQ[None, None, None, q_consumer_state.index],\n tQKrK[None, None, None, k_consumer_state.index],\n )\n cute.nvgpu.warpgroup.commit_group()\n cute.nvgpu.warpgroup.wait_group(0)\n\n k_pipeline.consumer_release(k_consumer_state)\n k_consumer_state.advance()\n q_pipeline.consumer_release(q_consumer_state)\n q_consumer_state.advance()\n\n if cutlass.const_expr(self.needs_alpha):\n alpha_pipeline.consumer_wait(alpha_consumer_state)\n if cutlass.const_expr(self.needs_beta):\n beta_pipeline.consumer_wait(beta_consumer_state)\n cute.arch.fence_view_async_shared()\n\n self.qk_and_kk_epi(\n tQKrQK,\n tKKrKK,\n tQKcMqk,\n tKKcMkk,\n sAlpha,\n sBeta,\n alpha_consumer_state.index,\n beta_consumer_state.index,\n is_final_block,\n B,\n scale,\n )\n\n kk_pipeline.producer_acquire(kk_producer_state)\n self._kk_store_and_inv(\n tKKrKK,\n kk_tiled_mma,\n aux_tidx,\n sKK_inv[None, None, kk_producer_state.index],\n sKK_opd[None, None, kk_producer_state.index],\n sBeta,\n beta_consumer_state.index,\n tKKcMkk,\n )\n cute.arch.fence_view_async_shared()\n kk_pipeline.producer_commit(kk_producer_state)\n kk_producer_state.advance()\n\n qk_pipeline.producer_acquire(qk_producer_state)\n self.qk_store(\n tQKrQK,\n sQK[None, None, qk_producer_state.index],\n qk_tiled_mma,\n aux_tidx,\n )\n cute.arch.fence_view_async_shared()\n qk_pipeline.producer_commit(qk_producer_state)\n qk_producer_state.advance()\n\n if cutlass.const_expr(self.needs_alpha):\n alpha_pipeline.consumer_release(alpha_consumer_state)\n alpha_consumer_state.advance()\n if cutlass.const_expr(self.needs_beta):\n beta_pipeline.consumer_release(beta_consumer_state)\n beta_consumer_state.advance()\n\n return (\n q_consumer_state,\n k_consumer_state,\n qk_producer_state,\n kk_producer_state,\n alpha_consumer_state,\n beta_consumer_state,\n )\n\n @cute.jit\n def run_aux_math_role(\n self,\n sQ_SD: cute.Tensor,\n sK_SD: cute.Tensor,\n sQK: cute.Tensor,\n sKK_inv: cute.Tensor,\n sKK_opd: cute.Tensor,\n sAlpha: cute.Tensor,\n sBeta: cute.Tensor,\n q_pipeline,\n k_pipeline,\n qk_pipeline,\n kk_pipeline,\n alpha_pipeline,\n beta_pipeline,\n work_desc: WorkDesc,\n scale: cutlass.Float32,\n math_tidx: cutlass.Int32,\n num_blocks: cutlass.Int32,\n ):\n aux_tidx = math_tidx % cutlass.Int32(128)\n\n qk_tiled_mma = cute.make_tiled_mma(\n cute.make_mma_atom(\n warpgroup.MmaF16BF16Op(\n self.dtype,\n self.acc_dtype,\n (self.BLK_Q, self.BLK_KV, 16),\n warpgroup.OperandSource.SMEM,\n cute.nvgpu.OperandMajorMode.K,\n cute.nvgpu.OperandMajorMode.K,\n )\n ),\n cute.make_layout((1, 1, 1)),\n )\n kk_tiled_mma = cute.make_tiled_mma(\n cute.make_mma_atom(\n warpgroup.MmaF16BF16Op(\n self.dtype,\n self.acc_dtype,\n (self.BLK_KV, self.BLK_KV, 16),\n warpgroup.OperandSource.SMEM,\n cute.nvgpu.OperandMajorMode.K,\n cute.nvgpu.OperandMajorMode.K,\n )\n ),\n cute.make_layout((1, 1, 1)),\n )\n\n qk_thr_mma = qk_tiled_mma.get_slice(aux_tidx)\n kk_thr_mma = kk_tiled_mma.get_slice(aux_tidx)\n\n tQKsQ = qk_thr_mma.partition_A(sQ_SD)\n tQKsK = qk_thr_mma.partition_B(sK_SD)\n tQKrQ = qk_thr_mma.make_fragment_A(tQKsQ)\n tQKrK = qk_thr_mma.make_fragment_B(tQKsK)\n\n tKKsA = kk_thr_mma.partition_A(sK_SD)\n tKKsB = kk_thr_mma.partition_B(sK_SD)\n tKKrA = kk_thr_mma.make_fragment_A(tKKsA)\n tKKrB = kk_thr_mma.make_fragment_B(tKKsB)\n\n cMqk = cute.make_identity_tensor((self.BLK_Q, self.BLK_KV))\n tQKcMqk = qk_thr_mma.partition_C(cMqk)\n tKKcMkk = kk_thr_mma.partition_C(cMqk)\n\n q_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.q_stage\n )\n k_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.k_stage\n )\n qk_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.qk_stage\n )\n kk_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.kk_stage\n )\n alpha_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.alpha_beta_stage\n )\n beta_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.alpha_beta_stage\n )\n\n for blk in cutlass.range(num_blocks - cutlass.Int32(1), unroll=1):\n (\n q_consumer_state,\n k_consumer_state,\n qk_producer_state,\n kk_producer_state,\n alpha_consumer_state,\n beta_consumer_state,\n ) = self.run_aux_loop_body(\n sQK,\n sKK_inv,\n sKK_opd,\n sAlpha,\n sBeta,\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n qk_pipeline,\n qk_producer_state,\n kk_pipeline,\n kk_producer_state,\n alpha_pipeline,\n alpha_consumer_state,\n beta_pipeline,\n beta_consumer_state,\n work_desc,\n scale,\n blk,\n False,\n qk_tiled_mma,\n kk_tiled_mma,\n tQKrQ,\n tQKrK,\n tKKrA,\n tKKrB,\n tQKcMqk,\n tKKcMkk,\n aux_tidx,\n )\n\n last_blk = num_blocks - cutlass.Int32(1)\n (\n q_consumer_state,\n k_consumer_state,\n qk_producer_state,\n kk_producer_state,\n alpha_consumer_state,\n beta_consumer_state,\n ) = self.run_aux_loop_body(\n sQK,\n sKK_inv,\n sKK_opd,\n sAlpha,\n sBeta,\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n qk_pipeline,\n qk_producer_state,\n kk_pipeline,\n kk_producer_state,\n alpha_pipeline,\n alpha_consumer_state,\n beta_pipeline,\n beta_consumer_state,\n work_desc,\n scale,\n last_blk,\n True,\n qk_tiled_mma,\n kk_tiled_mma,\n tQKrQ,\n tQKrK,\n tKKrA,\n tKKrB,\n tQKcMqk,\n tKKcMkk,\n aux_tidx,\n )\n\n # ─── Kernel entry point ───────────────────────────────────────────────────\n\n @cute.jit\n def __call__(\n self,\n g_q: cute.Tensor,\n g_k: cute.Tensor,\n g_v: cute.Tensor,\n g_o: cute.Tensor,\n g_alpha: cute.Tensor,\n g_beta: cute.Tensor,\n g_state: cute.Tensor,\n g_init_state: cute.Tensor,\n g_state_indices: cute.Tensor,\n g_state_checkpoints: cute.Tensor,\n checkpoint_cu_starts: cute.Tensor,\n g_tensormaps: cute.Tensor,\n cu_seqlens: cute.Tensor,\n scale: cutlass.Float32,\n num_q_heads: cutlass.Int32,\n num_k_heads: cutlass.Int32,\n num_v_heads: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n num_seqs: cutlass.Int32,\n total_checkpoints: cutlass.Int32,\n checkpoint_every_n_tokens: cutlass.Int32,\n grid_x: int,\n stream,\n ):\n qkv_smem_layout_atom = warpgroup.make_smem_layout_atom(\n warpgroup.SmemLayoutAtomKind.K_SW128,\n self.dtype,\n )\n q_storage_layout = cute.coalesce(\n cute.tile_to_shape(\n qkv_smem_layout_atom,\n (self.BLK_Q, self.D, self.q_stage),\n order=(0, 1, 2),\n ),\n target_profile=(1, 1, 1),\n )\n q_smem_layout = cute.slice_(q_storage_layout, (None, None, 0))\n k_storage_layout_sd = cute.coalesce(\n cute.tile_to_shape(\n qkv_smem_layout_atom,\n (self.BLK_KV, self.D, self.k_stage),\n order=(0, 1, 2),\n ),\n target_profile=(1, 1, 1),\n )\n k_storage_layout_ds = cute.select(k_storage_layout_sd, [1, 0, 2])\n v_storage_layout_sd = cute.coalesce(\n cute.tile_to_shape(\n qkv_smem_layout_atom,\n (self.BLK_KV, self.D, self.v_stage),\n order=(0, 1, 2),\n ),\n target_profile=(1, 1, 1),\n )\n v_storage_layout_ds = cute.select(v_storage_layout_sd, [1, 0, 2])\n k_smem_layout = cute.slice_(k_storage_layout_ds, (None, None, 0))\n v_smem_layout = cute.slice_(v_storage_layout_ds, (None, None, 0))\n o_smem_layout_atom = warpgroup.make_smem_layout_atom(\n warpgroup.SmemLayoutAtomKind.MN_SW32,\n self.dtype,\n )\n o_storage_layout = cute.tile_to_shape(\n o_smem_layout_atom,\n (self.D, self.BLK_Q, self.o_stage),\n order=(1, 0, 2),\n )\n o_smem_layout = cute.slice_(o_storage_layout, (None, None, 0))\n\n tma_load_op = cpasync.CopyBulkTensorTileG2SOp()\n tma_atom_q, tma_tensor_q = cpasync.make_tiled_tma_atom(\n tma_load_op, g_q, q_smem_layout, (self.BLK_Q, self.D)\n )\n tma_atom_k, tma_tensor_k = cpasync.make_tiled_tma_atom(\n tma_load_op, g_k, k_smem_layout, (self.D, self.BLK_KV)\n )\n tma_atom_v, tma_tensor_v = cpasync.make_tiled_tma_atom(\n tma_load_op, g_v, v_smem_layout, (self.D, self.BLK_KV)\n )\n\n tma_store_op = cpasync.CopyBulkTensorTileS2GOp()\n tma_atom_o, tma_tensor_o = cpasync.make_tiled_tma_atom(\n tma_store_op, g_o, o_smem_layout, (self.D, self.BLK_Q)\n )\n\n dtype_bytes = self.dtype.width // 8\n self.tma_load_q_bytes = cute.size(q_smem_layout) * dtype_bytes\n self.tma_load_k_bytes = cute.size(k_smem_layout) * dtype_bytes\n self.tma_load_v_bytes = cute.size(v_smem_layout) * dtype_bytes\n\n qk_layout_atom = cute.make_layout((8, 8), stride=(8, 1))\n qk_storage_layout = cute.tile_to_shape(\n qk_layout_atom, (self.BLK_Q, self.BLK_KV, self.qk_stage), order=(0, 1, 2)\n )\n kk_storage_layout = cute.tile_to_shape(\n qk_layout_atom, (self.BLK_KV, self.BLK_KV, self.kk_stage), order=(0, 1, 2)\n )\n alpha_storage_layout = cute.make_layout(\n (self.BLK_Q, AlphaProcessor.NUM_CHANNELS, self.alpha_beta_stage)\n )\n beta_storage_layout = cute.make_layout((self.BLK_KV, self.alpha_beta_stage))\n\n @cute.struct\n class SharedStorage:\n q_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.q_stage * 2]\n k_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.k_stage * 2]\n v_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.v_stage * 2]\n o_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.o_stage * 2]\n qk_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.qk_stage * 2]\n kk_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.kk_stage * 2]\n alpha_mbar_ptr: cute.struct.MemRange[\n cutlass.Int64, self.alpha_beta_stage * 2\n ]\n beta_mbar_ptr: cute.struct.MemRange[\n cutlass.Int64, self.alpha_beta_stage * 2\n ]\n\n smem_q: cute.struct.Align[\n cute.struct.MemRange[self.dtype, cute.cosize(q_storage_layout)],\n 128,\n ]\n smem_k: cute.struct.Align[\n cute.struct.MemRange[self.dtype, cute.cosize(k_storage_layout_sd)],\n 128,\n ]\n smem_v: cute.struct.Align[\n cute.struct.MemRange[self.dtype, cute.cosize(v_storage_layout_sd)],\n 128,\n ]\n smem_qk: cute.struct.Align[\n cute.struct.MemRange[self.dtype, cute.cosize(qk_storage_layout)],\n 16,\n ]\n smem_kk: cute.struct.Align[\n cute.struct.MemRange[\n self.inverse_dtype, cute.cosize(kk_storage_layout)\n ],\n 16,\n ]\n smem_o: cute.struct.Align[\n cute.struct.MemRange[self.dtype, cute.cosize(o_storage_layout)],\n 128,\n ]\n smem_alpha: cute.struct.Align[\n cute.struct.MemRange[\n cutlass.Float32, cute.cosize(alpha_storage_layout)\n ],\n 16,\n ]\n smem_beta: cute.struct.Align[\n cute.struct.MemRange[cutlass.Float32, cute.cosize(beta_storage_layout)],\n 16,\n ]\n\n self.shared_storage = SharedStorage\n\n self.kernel(\n g_alpha,\n g_beta,\n tma_atom_q,\n tma_tensor_q,\n tma_atom_k,\n tma_tensor_k,\n tma_atom_v,\n tma_tensor_v,\n tma_atom_o,\n tma_tensor_o,\n g_state,\n g_init_state,\n g_state_indices,\n g_state_checkpoints,\n checkpoint_cu_starts,\n g_tensormaps,\n cu_seqlens,\n scale,\n num_q_heads,\n num_k_heads,\n num_v_heads,\n num_sab_heads,\n num_seqs,\n total_checkpoints,\n checkpoint_every_n_tokens,\n ).launch(\n grid=(grid_x, 1, 1),\n block=(512, 1, 1),\n max_number_threads=(512, 1, 1),\n stream=stream,\n min_blocks_per_mp=1,\n )\n\n @cute.kernel\n def kernel(\n self,\n g_alpha: cute.Tensor,\n g_beta: cute.Tensor,\n tma_atom_q: cute.CopyAtom,\n tma_tensor_q: cute.Tensor,\n tma_atom_k: cute.CopyAtom,\n tma_tensor_k: cute.Tensor,\n tma_atom_v: cute.CopyAtom,\n tma_tensor_v: cute.Tensor,\n tma_atom_o: cute.CopyAtom,\n tma_tensor_o: cute.Tensor,\n g_state: cute.Tensor,\n g_init_state: cute.Tensor,\n g_state_indices: cute.Tensor,\n g_state_checkpoints: cute.Tensor,\n checkpoint_cu_starts: cute.Tensor,\n g_tensormaps: cute.Tensor,\n cu_seqlens: cute.Tensor,\n scale: cutlass.Float32,\n num_q_heads: cutlass.Int32,\n num_k_heads: cutlass.Int32,\n num_v_heads: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n num_seqs: cutlass.Int32,\n total_checkpoints: cutlass.Int32,\n checkpoint_every_n_tokens: cutlass.Int32,\n ):\n NUM_LOAD_WARP_GROUPS = 1\n NUM_STATE_MMA_WARP_GROUPS = 2\n NUM_AUX_MMA_WARP_GROUPS = 1\n THREADS_PER_WARP_GROUP = 128\n WARPS_PER_WARP_GROUP = 4\n MIN_BLOCKS_PER_MP = 1\n MAX_THREADS_PER_BLOCK = (\n NUM_LOAD_WARP_GROUPS + NUM_STATE_MMA_WARP_GROUPS + NUM_AUX_MMA_WARP_GROUPS\n ) * THREADS_PER_WARP_GROUP\n (\n load_registers,\n state_mma_registers,\n aux_mma_registers,\n ) = self.get_register_requirements(\n MAX_THREADS_PER_BLOCK,\n MIN_BLOCKS_PER_MP,\n NUM_STATE_MMA_WARP_GROUPS,\n THREADS_PER_WARP_GROUP,\n )\n\n tidx, _, _ = cute.arch.thread_idx()\n warp_idx = cute.arch.make_warp_uniform(cute.arch.warp_idx())\n warp_group_idx = cute.arch.make_warp_uniform(\n tidx // cutlass.Int32(THREADS_PER_WARP_GROUP)\n )\n ldst_warp_role = cute.arch.make_warp_uniform(\n warp_idx % cutlass.Int32(WARPS_PER_WARP_GROUP)\n )\n\n if warp_idx == LoadStoreWarpRole.LOAD_QKV:\n cpasync.prefetch_descriptor(tma_atom_q)\n cpasync.prefetch_descriptor(tma_atom_k)\n cpasync.prefetch_descriptor(tma_atom_v)\n cpasync.prefetch_descriptor(tma_atom_o)\n\n work_desc = self.get_next_work(\n cu_seqlens,\n num_q_heads,\n num_v_heads,\n num_sab_heads,\n )\n tok_end = work_desc.tok_offset + work_desc.seq_len\n num_blocks = (\n work_desc.seq_len + cutlass.Int32(self.BLK_KV) - cutlass.Int32(1)\n ) // cutlass.Int32(self.BLK_KV)\n\n # math_tidx / wg_idx: valid for Math WG threads; LdSt WG gets negative values (unused)\n math_tidx = tidx - cutlass.Int32(THREADS_PER_WARP_GROUP)\n wg_idx = math_tidx // cutlass.Int32(THREADS_PER_WARP_GROUP)\n\n # ── Smem allocation ───────────────────────────────────────────────────\n allocator = cutlass.utils.SmemAllocator()\n storage = allocator.allocate(self.shared_storage)\n\n qkv_smem_layout_atom = warpgroup.make_smem_layout_atom(\n warpgroup.SmemLayoutAtomKind.K_SW128,\n self.dtype,\n )\n q_layout_sd = cute.coalesce(\n cute.tile_to_shape(\n qkv_smem_layout_atom,\n (self.BLK_Q, self.D, self.q_stage),\n order=(0, 1, 2),\n ),\n target_profile=(1, 1, 1),\n )\n sQ_SD = storage.smem_q.get_tensor(q_layout_sd.outer, swizzle=q_layout_sd.inner)\n\n k_layout_sd = cute.coalesce(\n cute.tile_to_shape(\n qkv_smem_layout_atom,\n (self.BLK_KV, self.D, self.k_stage),\n order=(0, 1, 2),\n ),\n target_profile=(1, 1, 1),\n )\n k_layout_ds = cute.select(k_layout_sd, [1, 0, 2])\n sK_SD = storage.smem_k.get_tensor(k_layout_sd.outer, swizzle=k_layout_sd.inner)\n sK_DS = storage.smem_k.get_tensor(k_layout_ds.outer, swizzle=k_layout_ds.inner)\n\n v_layout_sd = cute.coalesce(\n cute.tile_to_shape(\n qkv_smem_layout_atom,\n (self.BLK_KV, self.D, self.v_stage),\n order=(0, 1, 2),\n ),\n target_profile=(1, 1, 1),\n )\n v_layout_ds = cute.select(v_layout_sd, [1, 0, 2])\n sV_DS = storage.smem_v.get_tensor(v_layout_ds.outer, swizzle=v_layout_ds.inner)\n\n qk_layout_atom = cute.make_layout((8, 8), stride=(8, 1))\n qk_layout = cute.tile_to_shape(\n qk_layout_atom, (self.BLK_Q, self.BLK_KV, self.qk_stage), order=(0, 1, 2)\n )\n sQK = storage.smem_qk.get_tensor(qk_layout)\n\n kk_layout = cute.tile_to_shape(\n qk_layout_atom, (self.BLK_KV, self.BLK_KV, self.kk_stage), order=(0, 1, 2)\n )\n sKK_inv = storage.smem_kk.get_tensor(kk_layout)\n kk_opd_ptr = cute.recast_ptr(storage.smem_kk.data_ptr(), dtype=self.dtype)\n sKK_opd = cute.make_tensor(kk_opd_ptr, kk_layout)\n\n o_smem_layout_atom = warpgroup.make_smem_layout_atom(\n warpgroup.SmemLayoutAtomKind.MN_SW32,\n self.dtype,\n )\n o_layout = cute.tile_to_shape(\n o_smem_layout_atom,\n (self.D, self.BLK_Q, self.o_stage),\n order=(1, 0, 2),\n )\n sO = storage.smem_o.get_tensor(o_layout.outer, swizzle=o_layout.inner)\n alpha_layout = cute.make_layout(\n (self.BLK_Q, AlphaProcessor.NUM_CHANNELS, self.alpha_beta_stage)\n )\n sAlpha = storage.smem_alpha.get_tensor(alpha_layout)\n\n beta_layout = cute.make_layout((self.BLK_KV, self.alpha_beta_stage))\n sBeta = storage.smem_beta.get_tensor(beta_layout)\n\n load_producer_group = pipeline.CooperativeGroup(pipeline.Agent.Thread, 1)\n # PipelineTmaAsync release is signalled by one lane per consumer warp.\n qk_load_consumer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n (NUM_STATE_MMA_WARP_GROUPS + NUM_AUX_MMA_WARP_GROUPS)\n * WARPS_PER_WARP_GROUP,\n )\n v_consumer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n NUM_STATE_MMA_WARP_GROUPS * WARPS_PER_WARP_GROUP,\n )\n vector_producer_group = pipeline.CooperativeGroup(pipeline.Agent.Thread, 32)\n alpha_consumer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n (NUM_AUX_MMA_WARP_GROUPS + NUM_STATE_MMA_WARP_GROUPS)\n * THREADS_PER_WARP_GROUP,\n )\n beta_consumer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread, NUM_AUX_MMA_WARP_GROUPS * THREADS_PER_WARP_GROUP\n )\n o_producer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread, NUM_STATE_MMA_WARP_GROUPS * THREADS_PER_WARP_GROUP\n )\n o_consumer_group = pipeline.CooperativeGroup(pipeline.Agent.Thread, 32)\n q_pipeline = pipeline.PipelineTmaAsync.create(\n barrier_storage=storage.q_mbar_ptr.data_ptr(),\n num_stages=self.q_stage,\n producer_group=load_producer_group,\n consumer_group=qk_load_consumer_group,\n tx_count=self.tma_load_q_bytes,\n cta_layout_vmnk=cute.make_layout((1, 1, 1, 1)),\n )\n k_pipeline = pipeline.PipelineTmaAsync.create(\n barrier_storage=storage.k_mbar_ptr.data_ptr(),\n num_stages=self.k_stage,\n producer_group=load_producer_group,\n consumer_group=qk_load_consumer_group,\n tx_count=self.tma_load_k_bytes,\n cta_layout_vmnk=cute.make_layout((1, 1, 1, 1)),\n )\n v_pipeline = pipeline.PipelineTmaAsync.create(\n barrier_storage=storage.v_mbar_ptr.data_ptr(),\n num_stages=self.v_stage,\n producer_group=load_producer_group,\n consumer_group=v_consumer_group,\n tx_count=self.tma_load_v_bytes,\n cta_layout_vmnk=cute.make_layout((1, 1, 1, 1)),\n )\n o_pipeline = pipeline.PipelineAsync.create(\n barrier_storage=storage.o_mbar_ptr.data_ptr(),\n num_stages=self.o_stage,\n producer_group=o_producer_group,\n consumer_group=o_consumer_group,\n )\n qk_pipeline = pipeline.PipelineAsync.create(\n barrier_storage=storage.qk_mbar_ptr.data_ptr(),\n num_stages=self.qk_stage,\n producer_group=pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n NUM_AUX_MMA_WARP_GROUPS * THREADS_PER_WARP_GROUP,\n ),\n consumer_group=pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n NUM_STATE_MMA_WARP_GROUPS * THREADS_PER_WARP_GROUP,\n ),\n )\n kk_pipeline = pipeline.PipelineAsync.create(\n barrier_storage=storage.kk_mbar_ptr.data_ptr(),\n num_stages=self.kk_stage,\n producer_group=pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n NUM_AUX_MMA_WARP_GROUPS * THREADS_PER_WARP_GROUP,\n ),\n consumer_group=pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n NUM_STATE_MMA_WARP_GROUPS * THREADS_PER_WARP_GROUP,\n ),\n )\n alpha_pipeline = pipeline.PipelineAsync.create(\n barrier_storage=storage.alpha_mbar_ptr.data_ptr(),\n num_stages=self.alpha_beta_stage,\n producer_group=vector_producer_group,\n consumer_group=alpha_consumer_group,\n )\n beta_pipeline = pipeline.PipelineAsync.create(\n barrier_storage=storage.beta_mbar_ptr.data_ptr(),\n num_stages=self.alpha_beta_stage,\n producer_group=vector_producer_group,\n consumer_group=beta_consumer_group,\n )\n cute.arch.mbarrier_init_fence()\n cute.arch.sync_threads()\n\n if (\n work_desc.seq_len != cutlass.Int32(0)\n and warp_group_idx == WarpGroupRole.LDST\n ):\n cute.arch.setmaxregister_decrease(load_registers)\n if ldst_warp_role == LoadStoreWarpRole.LOAD_QKV:\n self.run_load_qkv_role(\n sQ_SD,\n sK_DS,\n sV_DS,\n tma_atom_q,\n tma_tensor_q,\n tma_atom_k,\n tma_tensor_k,\n tma_atom_v,\n tma_tensor_v,\n q_pipeline,\n k_pipeline,\n v_pipeline,\n num_blocks,\n work_desc.tok_offset,\n work_desc.q_head_idx(),\n work_desc.k_head_idx(num_q_heads, num_v_heads),\n work_desc.v_head_idx(),\n )\n elif ldst_warp_role == LoadStoreWarpRole.STORE_O:\n CollectiveStoreTma(self.BLK_Q, self.D).run(\n sO,\n tma_atom_o,\n tma_tensor_o,\n g_tensormaps,\n o_pipeline,\n num_blocks,\n work_desc,\n num_seqs,\n self.o_stage,\n num_q_heads,\n num_v_heads,\n )\n elif ldst_warp_role == LoadStoreWarpRole.LOAD_BETA:\n self.run_load_beta_role(\n sBeta,\n g_beta,\n beta_pipeline,\n num_blocks,\n work_desc.tok_offset,\n tok_end,\n work_desc.o_head_idx(num_q_heads, num_v_heads),\n num_sab_heads,\n )\n elif ldst_warp_role == LoadStoreWarpRole.LOAD_ALPHA:\n self.run_load_alpha_role(\n sAlpha,\n g_alpha,\n alpha_pipeline,\n scale,\n num_blocks,\n work_desc.tok_offset,\n tok_end,\n work_desc.o_head_idx(num_q_heads, num_v_heads),\n num_sab_heads,\n )\n elif work_desc.seq_len != cutlass.Int32(0):\n if warp_group_idx == WarpGroupRole.MATH_AUX:\n cute.arch.setmaxregister_decrease(aux_mma_registers)\n self.run_aux_math_role(\n sQ_SD,\n sK_SD,\n sQK,\n sKK_inv,\n sKK_opd,\n sAlpha,\n sBeta,\n q_pipeline,\n k_pipeline,\n qk_pipeline,\n kk_pipeline,\n alpha_pipeline,\n beta_pipeline,\n work_desc,\n scale,\n math_tidx,\n num_blocks,\n )\n else:\n cute.arch.setmaxregister_increase(state_mma_registers)\n self.run_state_math_role(\n sQ_SD,\n sK_SD,\n sK_DS,\n sV_DS,\n sQK,\n sKK_inv,\n sKK_opd,\n sO,\n sAlpha,\n q_pipeline,\n k_pipeline,\n v_pipeline,\n o_pipeline,\n qk_pipeline,\n kk_pipeline,\n alpha_pipeline,\n g_state,\n g_init_state,\n g_state_indices,\n g_state_checkpoints,\n checkpoint_cu_starts,\n work_desc,\n scale,\n wg_idx,\n math_tidx,\n num_blocks,\n num_q_heads,\n num_v_heads,\n num_sab_heads,\n num_seqs,\n total_checkpoints,\n checkpoint_every_n_tokens,\n )\n\n\n# ─── Public API ──────────────────────────────────────────────────────────────\n\n\n@functools.cache\ndef _get_prefill_kernel(\n needs_alpha,\n needs_beta,\n needs_init_state,\n needs_checkpointing,\n kernel_dtype,\n initial_state_dtype,\n state_dtype,\n checkpoint_state_dtype,\n use_state_indices,\n cu_seqlens_dtype,\n state_indices_dtype,\n checkpoint_cu_starts_dtype,\n state_inner_strides,\n init_state_inner_strides,\n):\n return _FullyFusedDeltaRuleSm90(\n needs_alpha,\n needs_beta,\n needs_init_state,\n needs_checkpointing,\n kernel_dtype,\n initial_state_dtype=state_dtype_to_cutlass(initial_state_dtype),\n state_dtype=state_dtype_to_cutlass(state_dtype),\n checkpoint_state_dtype=state_dtype_to_cutlass(checkpoint_state_dtype),\n use_state_indices=use_state_indices,\n cu_seqlens_dtype=cu_seqlens_dtype,\n state_indices_dtype=state_indices_dtype,\n checkpoint_cu_starts_dtype=checkpoint_cu_starts_dtype,\n state_inner_strides=state_inner_strides,\n init_state_inner_strides=init_state_inner_strides,\n )\n\n\ndef delta_rule_prefill_dsl_sm90(\n o: torch.Tensor, # (total_seqlen, num_o_heads, D) fp16/bf16, output\n state: torch.Tensor, # (num_seqs, num_sab_heads, D, D) fp32, output\n q: torch.Tensor, # (total_seqlen, num_q_heads, D)\n k: torch.Tensor, # (total_seqlen, num_k_heads, D)\n v: torch.Tensor, # (total_seqlen, num_v_heads, D)\n init_state: torch.Tensor | None, # (num_seqs, num_sab_heads, D, D) fp32, optional\n alpha: torch.Tensor | None,\n beta: torch.Tensor | None,\n cu_seqlens: torch.Tensor, # (num_seqs+1,) int64\n scale: float,\n state_checkpoints: torch.Tensor | None = None,\n checkpoint_cu_starts: torch.Tensor | None = None,\n checkpoint_every_n_tokens: int = 0,\n state_indices: torch.Tensor | None = None,\n):\n import cuda.bindings.driver as cuda_driver\n\n device = q.device\n D = q.shape[-1]\n\n num_seqs = cu_seqlens.shape[0] - 1\n num_q_heads = q.shape[1]\n num_k_heads = k.shape[1]\n num_v_heads = v.shape[1]\n num_sab_heads = max(num_q_heads, num_v_heads)\n\n if not _FullyFusedDeltaRuleSm90.can_implement(\n num_q_heads, num_k_heads, num_v_heads, D, q.element_size()\n ):\n raise RuntimeError(\"can_implement failed\")\n if D != 128:\n raise RuntimeError(f\"DSL kernel only supports D=128, got {D}\")\n\n needs_alpha = alpha is not None\n needs_beta = beta is not None\n needs_init_state = init_state is not None\n needs_checkpointing = checkpoint_every_n_tokens > 0\n use_state_indices = state_indices is not None\n kernel_dtype = {\n torch.float16: cutlass.Float16,\n torch.bfloat16: cutlass.BFloat16,\n }.get(q.dtype)\n if kernel_dtype is None:\n raise RuntimeError(f\"DSL kernel only supports fp16/bf16 inputs, got {q.dtype}\")\n\n if k.dtype != q.dtype or v.dtype != q.dtype or o.dtype != q.dtype:\n raise RuntimeError(\n f\"q/k/v/o dtypes must match, got {q.dtype}, {k.dtype}, {v.dtype}, {o.dtype}\"\n )\n if alpha is not None and alpha.dtype != torch.float32:\n raise RuntimeError(f\"alpha must have dtype torch.float32, got {alpha.dtype}\")\n if beta is not None and beta.dtype != torch.float32:\n raise RuntimeError(f\"beta must have dtype torch.float32, got {beta.dtype}\")\n if init_state is not None:\n state_dtype_to_cutlass(init_state.dtype)\n state_dtype_to_cutlass(state.dtype)\n if state_checkpoints is not None:\n state_dtype_to_cutlass(state_checkpoints.dtype)\n if not is_integer_dtype(cu_seqlens.dtype):\n raise RuntimeError(\n f\"cu_seqlens must have an integer dtype, got {cu_seqlens.dtype}\"\n )\n\n expected_state_tail = (num_sab_heads, D, D)\n for name, tensor in ((\"state\", state), (\"init_state\", init_state)):\n if tensor is None:\n continue\n if (\n not use_state_indices and tensor.shape != (num_seqs, *expected_state_tail)\n ) or (use_state_indices and tuple(tensor.shape[1:]) != expected_state_tail):\n raise RuntimeError(\n f\"{name} must have shape \"\n f\"{('[N_pool]' if use_state_indices else f'[{num_seqs}]')} + {expected_state_tail}, \"\n f\"got {tuple(tensor.shape)}\"\n )\n if use_state_indices and (\n not is_integer_dtype(state_indices.dtype) or state_indices.shape != (num_seqs,)\n ):\n raise RuntimeError(\n f\"state_indices must have shape {(num_seqs,)} and an integer dtype\"\n )\n\n for name, tensor in (\n (\"q\", q),\n (\"k\", k),\n (\"v\", v),\n (\"o\", o),\n (\"cu_seqlens\", cu_seqlens),\n ):\n if not tensor.is_contiguous():\n raise RuntimeError(f\"{name} must be contiguous\")\n for name, tensor in (\n (\"alpha\", alpha),\n (\"beta\", beta),\n (\"state_indices\", state_indices),\n ):\n if tensor is not None and not tensor.is_contiguous():\n raise RuntimeError(f\"{name} must be contiguous\")\n for name, tensor in ((\"state\", state), (\"init_state\", init_state)):\n if tensor is None:\n continue\n if not use_state_indices and not tensor.is_contiguous():\n raise RuntimeError(f\"{name} must be contiguous\")\n\n total_seqlen = q.shape[0]\n num_o_heads = o.shape[1]\n q_tma = q.as_strided(\n (total_seqlen, D, num_q_heads),\n (num_q_heads * D, 1, D),\n )\n k_tma = k.as_strided(\n (D, total_seqlen, num_k_heads),\n (1, num_k_heads * D, D),\n )\n v_tma = v.as_strided(\n (D, total_seqlen, num_v_heads),\n (1, num_v_heads * D, D),\n )\n o_tma = o.as_strided(\n (D, total_seqlen, num_o_heads),\n (1, num_o_heads * D, D),\n )\n total_checkpoints = state_checkpoints.shape[0] if needs_checkpointing else 1\n\n workspace_size = get_device_sm_count(device) * 128\n tensormaps_t = _get_cache_buf(\"gdn_prefill_tensormaps\", workspace_size, device)\n stream = cuda_driver.CUstream(torch.cuda.current_stream(device).cuda_stream)\n\n delta_rule_kernel = _get_prefill_kernel(\n needs_alpha,\n needs_beta,\n needs_init_state,\n needs_checkpointing,\n kernel_dtype,\n initial_state_dtype=(init_state.dtype if needs_init_state else torch.float32),\n state_dtype=state.dtype,\n checkpoint_state_dtype=(\n state_checkpoints.dtype if needs_checkpointing else torch.float32\n ),\n use_state_indices=use_state_indices,\n cu_seqlens_dtype=cu_seqlens.dtype,\n state_indices_dtype=state_indices.dtype if use_state_indices else None,\n checkpoint_cu_starts_dtype=(\n checkpoint_cu_starts.dtype if needs_checkpointing else None\n ),\n state_inner_strides=(tuple(state.stride()[1:]) if use_state_indices else None),\n init_state_inner_strides=(\n tuple(init_state.stride()[1:])\n if use_state_indices and needs_init_state\n else None\n ),\n )\n\n compiled_delta_rule_kernel = get_cached_compile(\n delta_rule_kernel, _SM90_COMPILE_OPTIONS\n )\n if compiled_delta_rule_kernel is None:\n from_dlpack = lambda *args, **kwargs: cute.runtime.from_dlpack(\n *args, **{**kwargs, \"enable_tvm_ffi\": True}\n )\n kernel_args = (\n from_dlpack(q_tma, assumed_align=16).mark_layout_dynamic(leading_dim=1),\n from_dlpack(k_tma, assumed_align=16).mark_layout_dynamic(leading_dim=0),\n from_dlpack(v_tma, assumed_align=16).mark_layout_dynamic(leading_dim=0),\n from_dlpack(o_tma, assumed_align=16).mark_layout_dynamic(leading_dim=0),\n (\n from_dlpack(alpha.reshape(-1), assumed_align=16).mark_layout_dynamic()\n if needs_alpha\n else None\n ),\n (\n from_dlpack(beta.reshape(-1), assumed_align=16).mark_layout_dynamic()\n if needs_beta\n else None\n ),\n from_dlpack(state, assumed_align=16).mark_layout_dynamic(),\n (\n from_dlpack(init_state, assumed_align=16).mark_layout_dynamic()\n if needs_init_state\n else None\n ),\n (\n from_dlpack(state_indices, assumed_align=4).mark_layout_dynamic()\n if use_state_indices\n else None\n ),\n (\n from_dlpack(\n state_checkpoints.reshape(-1), assumed_align=16\n ).mark_layout_dynamic()\n if needs_checkpointing\n else None\n ),\n (\n from_dlpack(checkpoint_cu_starts, assumed_align=8).mark_layout_dynamic()\n if needs_checkpointing\n else None\n ),\n from_dlpack(tensormaps_t, assumed_align=128).mark_layout_dynamic(),\n from_dlpack(cu_seqlens, assumed_align=8).mark_layout_dynamic(),\n cutlass.Float32(scale),\n cutlass.Int32(num_q_heads),\n cutlass.Int32(num_k_heads),\n cutlass.Int32(num_v_heads),\n cutlass.Int32(num_sab_heads),\n cutlass.Int32(num_seqs),\n cutlass.Int32(total_checkpoints),\n cutlass.Int32(checkpoint_every_n_tokens),\n num_seqs * num_sab_heads,\n stream,\n )\n compiled_delta_rule_kernel = cached_compile(\n delta_rule_kernel,\n *kernel_args,\n compile_options=_SM90_COMPILE_OPTIONS,\n )\n compiled_delta_rule_kernel(\n q_tma,\n k_tma,\n v_tma,\n o_tma,\n alpha.reshape(-1) if needs_alpha else None,\n beta.reshape(-1) if needs_beta else None,\n state,\n init_state if needs_init_state else None,\n state_indices if use_state_indices else None,\n state_checkpoints.reshape(-1) if needs_checkpointing else None,\n checkpoint_cu_starts if needs_checkpointing else None,\n tensormaps_t,\n cu_seqlens,\n scale,\n num_q_heads,\n num_k_heads,\n num_v_heads,\n num_sab_heads,\n num_seqs,\n total_checkpoints,\n checkpoint_every_n_tokens,\n num_seqs * num_sab_heads,\n stream,\n )\n"},"diff":{"kind":"string","value":"--- flashinfer/gdn_kernels/delta_rule_dsl/delta_rule_sm90.py\n+++ flashinfer/gdn_kernels/delta_rule_dsl/delta_rule_sm90.py\n@@ -1,3 +1,4 @@\n+import functools\n from enum import IntEnum\n \n import torch\n@@ -8,11 +9,14 @@\n from ...utils import get_device_sm_count, _get_cache_buf\n from .alpha import AlphaProcessor\n from .collective_store_tma import CollectiveStoreTma\n-from .custom_compile_cache import KeyedCompileMixin, cached_compile\n+from .custom_compile_cache import KeyedCompileMixin, cached_compile, get_cached_compile\n from .collective_inverse_hmma import CollectiveInverse\n from .helpers import SM90, round_down, select_tensor_10, state_dtype_to_cutlass\n from .schedule import WorkDesc\n from .varlen_helper import is_integer_dtype\n+\n+\n+_SM90_COMPILE_OPTIONS = (cute.EnableTVMFFI(True), cute.GPUArch(\"sm_90a\"))\n \n \n # ─── Named-barrier IDs used by the compute kernel ────────────────────────────\n@@ -2342,6 +2346,41 @@\n # ─── Public API ──────────────────────────────────────────────────────────────\n \n \n+@functools.cache\n+def _get_prefill_kernel(\n+ needs_alpha,\n+ needs_beta,\n+ needs_init_state,\n+ needs_checkpointing,\n+ kernel_dtype,\n+ initial_state_dtype,\n+ state_dtype,\n+ checkpoint_state_dtype,\n+ use_state_indices,\n+ cu_seqlens_dtype,\n+ state_indices_dtype,\n+ checkpoint_cu_starts_dtype,\n+ state_inner_strides,\n+ init_state_inner_strides,\n+):\n+ return _FullyFusedDeltaRuleSm90(\n+ needs_alpha,\n+ needs_beta,\n+ needs_init_state,\n+ needs_checkpointing,\n+ kernel_dtype,\n+ initial_state_dtype=state_dtype_to_cutlass(initial_state_dtype),\n+ state_dtype=state_dtype_to_cutlass(state_dtype),\n+ checkpoint_state_dtype=state_dtype_to_cutlass(checkpoint_state_dtype),\n+ use_state_indices=use_state_indices,\n+ cu_seqlens_dtype=cu_seqlens_dtype,\n+ state_indices_dtype=state_indices_dtype,\n+ checkpoint_cu_starts_dtype=checkpoint_cu_starts_dtype,\n+ state_inner_strides=state_inner_strides,\n+ init_state_inner_strides=init_state_inner_strides,\n+ )\n+\n+\n def delta_rule_prefill_dsl_sm90(\n o: torch.Tensor, # (total_seqlen, num_o_heads, D) fp16/bf16, output\n state: torch.Tensor, # (num_seqs, num_sab_heads, D, D) fp32, output\n@@ -2358,9 +2397,9 @@\n checkpoint_every_n_tokens: int = 0,\n state_indices: torch.Tensor | None = None,\n ):\n- from cutlass.cute.runtime import from_dlpack\n import cuda.bindings.driver as cuda_driver\n \n+ device = q.device\n D = q.shape[-1]\n \n num_seqs = cu_seqlens.shape[0] - 1\n@@ -2467,70 +2506,19 @@\n )\n total_checkpoints = state_checkpoints.shape[0] if needs_checkpointing else 1\n \n- workspace_size = get_device_sm_count(q.device) * 128\n- tensormaps_t = _get_cache_buf(\"gdn_prefill_tensormaps\", workspace_size, q.device)\n-\n- stream_val = torch.cuda.current_stream().cuda_stream\n- stream = cuda_driver.CUstream(stream_val)\n-\n- enable_tvm_ffi = True\n- if enable_tvm_ffi:\n- from_dlpack = lambda *args, **kwargs: cute.runtime.from_dlpack(\n- *args, **{**kwargs, \"enable_tvm_ffi\": True}\n- )\n-\n- # Keep head counts and varlen extents runtime values across cached compiles.\n- q_cute = from_dlpack(q_tma, assumed_align=16).mark_layout_dynamic(leading_dim=1)\n- k_cute = from_dlpack(k_tma, assumed_align=16).mark_layout_dynamic(leading_dim=0)\n- v_cute = from_dlpack(v_tma, assumed_align=16).mark_layout_dynamic(leading_dim=0)\n- o_cute = from_dlpack(o_tma, assumed_align=16).mark_layout_dynamic(leading_dim=0)\n- alpha_cute = (\n- from_dlpack(alpha.reshape(-1), assumed_align=16).mark_layout_dynamic()\n- if needs_alpha\n- else None\n- )\n- beta_cute = (\n- from_dlpack(beta.reshape(-1), assumed_align=16).mark_layout_dynamic()\n- if needs_beta\n- else None\n- )\n- state_cute = from_dlpack(state, assumed_align=16).mark_layout_dynamic()\n- init_state_cute = (\n- from_dlpack(init_state, assumed_align=16).mark_layout_dynamic()\n- if needs_init_state\n- else None\n- )\n- state_indices_cute = (\n- from_dlpack(state_indices, assumed_align=4).mark_layout_dynamic()\n- if use_state_indices\n- else None\n- )\n- state_checkpoints_cute = (\n- from_dlpack(\n- state_checkpoints.reshape(-1), assumed_align=16\n- ).mark_layout_dynamic()\n- if needs_checkpointing\n- else None\n- )\n- checkpoint_cu_cute = (\n- from_dlpack(checkpoint_cu_starts, assumed_align=8).mark_layout_dynamic()\n- if needs_checkpointing\n- else None\n- )\n- tensormaps_cute = from_dlpack(tensormaps_t, assumed_align=128).mark_layout_dynamic()\n- cu_cute = from_dlpack(cu_seqlens, assumed_align=8).mark_layout_dynamic()\n-\n- delta_rule_kernel = _FullyFusedDeltaRuleSm90(\n+ workspace_size = get_device_sm_count(device) * 128\n+ tensormaps_t = _get_cache_buf(\"gdn_prefill_tensormaps\", workspace_size, device)\n+ stream = cuda_driver.CUstream(torch.cuda.current_stream(device).cuda_stream)\n+\n+ delta_rule_kernel = _get_prefill_kernel(\n needs_alpha,\n needs_beta,\n needs_init_state,\n needs_checkpointing,\n kernel_dtype,\n- initial_state_dtype=state_dtype_to_cutlass(\n- init_state.dtype if needs_init_state else torch.float32\n- ),\n- state_dtype=state_dtype_to_cutlass(state.dtype),\n- checkpoint_state_dtype=state_dtype_to_cutlass(\n+ initial_state_dtype=(init_state.dtype if needs_init_state else torch.float32),\n+ state_dtype=state.dtype,\n+ checkpoint_state_dtype=(\n state_checkpoints.dtype if needs_checkpointing else torch.float32\n ),\n use_state_indices=use_state_indices,\n@@ -2547,34 +2535,91 @@\n ),\n )\n \n- kernel_args = (\n- q_cute,\n- k_cute,\n- v_cute,\n- o_cute,\n- alpha_cute,\n- beta_cute,\n- state_cute,\n- init_state_cute,\n- state_indices_cute,\n- state_checkpoints_cute,\n- checkpoint_cu_cute,\n- tensormaps_cute,\n- cu_cute,\n- cutlass.Float32(scale),\n- cutlass.Int32(num_q_heads),\n- cutlass.Int32(num_k_heads),\n- cutlass.Int32(num_v_heads),\n- cutlass.Int32(num_sab_heads),\n- cutlass.Int32(num_seqs),\n- cutlass.Int32(total_checkpoints),\n- cutlass.Int32(checkpoint_every_n_tokens),\n+ compiled_delta_rule_kernel = get_cached_compile(\n+ delta_rule_kernel, _SM90_COMPILE_OPTIONS\n+ )\n+ if compiled_delta_rule_kernel is None:\n+ from_dlpack = lambda *args, **kwargs: cute.runtime.from_dlpack(\n+ *args, **{**kwargs, \"enable_tvm_ffi\": True}\n+ )\n+ kernel_args = (\n+ from_dlpack(q_tma, assumed_align=16).mark_layout_dynamic(leading_dim=1),\n+ from_dlpack(k_tma, assumed_align=16).mark_layout_dynamic(leading_dim=0),\n+ from_dlpack(v_tma, assumed_align=16).mark_layout_dynamic(leading_dim=0),\n+ from_dlpack(o_tma, assumed_align=16).mark_layout_dynamic(leading_dim=0),\n+ (\n+ from_dlpack(alpha.reshape(-1), assumed_align=16).mark_layout_dynamic()\n+ if needs_alpha\n+ else None\n+ ),\n+ (\n+ from_dlpack(beta.reshape(-1), assumed_align=16).mark_layout_dynamic()\n+ if needs_beta\n+ else None\n+ ),\n+ from_dlpack(state, assumed_align=16).mark_layout_dynamic(),\n+ (\n+ from_dlpack(init_state, assumed_align=16).mark_layout_dynamic()\n+ if needs_init_state\n+ else None\n+ ),\n+ (\n+ from_dlpack(state_indices, assumed_align=4).mark_layout_dynamic()\n+ if use_state_indices\n+ else None\n+ ),\n+ (\n+ from_dlpack(\n+ state_checkpoints.reshape(-1), assumed_align=16\n+ ).mark_layout_dynamic()\n+ if needs_checkpointing\n+ else None\n+ ),\n+ (\n+ from_dlpack(checkpoint_cu_starts, assumed_align=8).mark_layout_dynamic()\n+ if needs_checkpointing\n+ else None\n+ ),\n+ from_dlpack(tensormaps_t, assumed_align=128).mark_layout_dynamic(),\n+ from_dlpack(cu_seqlens, assumed_align=8).mark_layout_dynamic(),\n+ cutlass.Float32(scale),\n+ cutlass.Int32(num_q_heads),\n+ cutlass.Int32(num_k_heads),\n+ cutlass.Int32(num_v_heads),\n+ cutlass.Int32(num_sab_heads),\n+ cutlass.Int32(num_seqs),\n+ cutlass.Int32(total_checkpoints),\n+ cutlass.Int32(checkpoint_every_n_tokens),\n+ num_seqs * num_sab_heads,\n+ stream,\n+ )\n+ compiled_delta_rule_kernel = cached_compile(\n+ delta_rule_kernel,\n+ *kernel_args,\n+ compile_options=_SM90_COMPILE_OPTIONS,\n+ )\n+ compiled_delta_rule_kernel(\n+ q_tma,\n+ k_tma,\n+ v_tma,\n+ o_tma,\n+ alpha.reshape(-1) if needs_alpha else None,\n+ beta.reshape(-1) if needs_beta else None,\n+ state,\n+ init_state if needs_init_state else None,\n+ state_indices if use_state_indices else None,\n+ state_checkpoints.reshape(-1) if needs_checkpointing else None,\n+ checkpoint_cu_starts if needs_checkpointing else None,\n+ tensormaps_t,\n+ cu_seqlens,\n+ scale,\n+ num_q_heads,\n+ num_k_heads,\n+ num_v_heads,\n+ num_sab_heads,\n+ num_seqs,\n+ total_checkpoints,\n+ checkpoint_every_n_tokens,\n num_seqs * num_sab_heads,\n stream,\n )\n- compiled_delta_rule_kernel = cached_compile(\n- delta_rule_kernel,\n- *kernel_args,\n- compile_options=(cute.GPUArch(\"sm_90a\"),),\n- )\n- compiled_delta_rule_kernel(*kernel_args)"},"lines_added":{"kind":"number","value":134,"string":"134"},"lines_removed":{"kind":"number","value":89,"string":"89"},"files_in_commit":{"kind":"number","value":2,"string":"2"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["SM120","SM90"],"string":"[\n \"SM120\",\n \"SM90\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cute_dsl kernel file from flashinfer (flashinfer/gdn_kernels/delta_rule_dsl/delta_rule_sm90.py).\n\nGoal: perf(gdn): reduce non-CP CuTeDSL launch overhead\nTarget hardware: SM120, SM90\nTarget models: unspecified\n\nCurrent file:\n```python\nfrom enum import IntEnum\n\nimport torch\nimport cutlass\nimport cutlass.cute as cute\nimport cutlass.pipeline as pipeline\nfrom cutlass.cute.nvgpu import warp, warpgroup, cpasync\nfrom ...utils import get_device_sm_count, _get_cache_buf\nfrom .alpha import AlphaProcessor\nfrom .collective_store_tma import CollectiveStoreTma\nfrom .custom_compile_cache import KeyedCompileMixin, cached_compile\nfrom .collective_inverse_hmma import CollectiveInverse\nfrom .helpers import SM90, round_down, select_tensor_10, state_dtype_to_cutlass\nfrom .schedule import WorkDesc\nfrom .varlen_helper import is_integer_dtype\n\n\n# ─── Named-barrier IDs used by the compute kernel ────────────────────────────\n# Must not conflict with each other or with pipeline barrier storage.\n\n\nclass NamedBarrier(IntEnum):\n MATH_WG0 = 4 # OrderedMathBarriers: StreamkBarrier0\n MATH_WG1 = 5 # OrderedMathBarriers: StreamkBarrier1\n KK_SYNC = 13 # sync all 128 WG0 threads before collective_inverse\n\n\nclass WarpGroupRole(IntEnum):\n LDST = 0\n MATH_STATE0 = 1\n MATH_STATE1 = 2\n MATH_AUX = 3\n\n\nclass LoadStoreWarpRole(IntEnum):\n STORE_O = 0\n LOAD_QKV = 1\n LOAD_BETA = 2\n LOAD_ALPHA = 3\n\n\nclass MathWarpGroupRole(IntEnum):\n STATE0 = 0\n STATE1 = 1\n AUX = 2\n KK = 0\n QK = 1\n\n\n# ─── Warp-specialized delta-rule kernel ───────────────────────────────────────\n# Grid: (num_seqs * num_sab_heads, 1, 1)\n# Block: 512 threads → WG0=LD/ST, WG1/WG2=state math, WG3=aux math.\n#\n# needs_alpha / needs_beta / needs_init_state are class attributes set in __init__.\n# The JIT compiler specialises per instance, so they are compile-time booleans\n# inside the kernel without any parameter-passing trickery.\n\n\nclass _FullyFusedDeltaRuleSm90(KeyedCompileMixin):\n @staticmethod\n def get_register_requirements(\n max_threads_per_block: int,\n min_blocks_per_multiprocessor: int,\n num_state_mma_warp_groups: int,\n threads_per_warp_group: int,\n ) -> tuple[int, int, int]:\n reg_alloc_granularity = 8\n load_registers = 40 - 2 * reg_alloc_granularity\n aux_registers = 128 - load_registers\n total_registers = (\n round_down(\n 64 * 1024 // min_blocks_per_multiprocessor,\n max_threads_per_block * reg_alloc_granularity,\n )\n // threads_per_warp_group\n )\n state_mma_registers = round_down(\n (total_registers - load_registers - aux_registers)\n // num_state_mma_warp_groups,\n reg_alloc_granularity,\n )\n return (\n min(248, load_registers),\n min(248, state_mma_registers),\n min(248, aux_registers),\n )\n\n @staticmethod\n def can_implement(\n num_q_heads: int,\n num_k_heads: int,\n num_v_heads: int,\n head_size: int,\n element_size: int,\n ) -> bool:\n ratio = (\n num_q_heads // num_v_heads\n if num_q_heads > num_v_heads\n else num_v_heads // num_q_heads\n )\n is_gva_enabled = num_v_heads > num_q_heads\n\n is_gqa_like = (\n (num_k_heads == num_v_heads)\n and (num_q_heads == ratio * num_k_heads)\n and (num_q_heads == ratio * num_v_heads)\n )\n is_gva_like = (\n (num_q_heads == num_k_heads)\n and (num_v_heads == ratio * num_q_heads)\n and (num_v_heads == ratio * num_k_heads)\n )\n\n alignment = 16 // element_size\n return (\n ((not is_gva_enabled and is_gqa_like) or (is_gva_enabled and is_gva_like))\n and (head_size <= 128)\n and ((head_size % alignment) == 0)\n )\n\n def __init__(\n self,\n needs_alpha: bool,\n needs_beta: bool,\n needs_init_state: bool,\n needs_checkpointing: bool,\n dtype: type[cutlass.Numeric] = cutlass.Float16,\n acc_dtype: type[cutlass.Numeric] = cutlass.Float32,\n initial_state_dtype: type[cutlass.Numeric] = cutlass.Float32,\n state_dtype: type[cutlass.Numeric] = cutlass.Float32,\n checkpoint_state_dtype: type[cutlass.Numeric] = cutlass.Float32,\n use_state_indices: bool = False,\n cu_seqlens_dtype: torch.dtype = torch.int64,\n state_indices_dtype: torch.dtype | None = None,\n checkpoint_cu_starts_dtype: torch.dtype | None = None,\n state_inner_strides: tuple[int, ...] | None = None,\n init_state_inner_strides: tuple[int, ...] | None = None,\n ):\n self.needs_alpha = needs_alpha\n self.needs_beta = needs_beta\n self.needs_init_state = needs_init_state\n self.needs_checkpointing = needs_checkpointing\n self.dtype = dtype\n self.acc_dtype = acc_dtype\n self.initial_state_dtype = initial_state_dtype\n self.state_dtype = state_dtype\n self.checkpoint_state_dtype = checkpoint_state_dtype\n self.use_state_indices = use_state_indices\n self.cu_seqlens_dtype = cu_seqlens_dtype\n self.state_indices_dtype = state_indices_dtype\n self.checkpoint_cu_starts_dtype = checkpoint_cu_starts_dtype\n self.state_inner_strides = state_inner_strides\n self.init_state_inner_strides = init_state_inner_strides\n self.inverse_dtype = cutlass.Float16\n self.BLK_Q = 64\n self.BLK_KV = 64\n self.D = 128\n self.q_stage = 2\n self.k_stage = 3\n self.v_stage = 2\n self.o_stage = 2\n self.qk_stage = 2\n self.kk_stage = 2\n self.alpha_beta_stage = 5\n self.manual_cache_key(\n \"needs_alpha\",\n \"needs_beta\",\n \"needs_init_state\",\n \"needs_checkpointing\",\n \"dtype\",\n \"acc_dtype\",\n \"initial_state_dtype\",\n \"state_dtype\",\n \"checkpoint_state_dtype\",\n \"use_state_indices\",\n \"cu_seqlens_dtype\",\n \"state_indices_dtype\",\n \"checkpoint_cu_starts_dtype\",\n \"state_inner_strides\",\n \"init_state_inner_strides\",\n \"inverse_dtype\",\n \"BLK_Q\",\n \"BLK_KV\",\n \"D\",\n \"q_stage\",\n \"k_stage\",\n \"v_stage\",\n \"o_stage\",\n \"qk_stage\",\n \"kk_stage\",\n \"alpha_beta_stage\",\n )\n\n def get_next_work(\n self,\n cu_seqlens: cute.Tensor,\n num_q_heads: cutlass.Int32,\n num_v_heads: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n ) -> WorkDesc:\n bx, _, _ = cute.arch.block_idx()\n seq_idx = bx // num_sab_heads\n o_head_idx = bx % num_sab_heads\n q_head_idx = o_head_idx * num_q_heads // num_sab_heads\n v_head_idx = o_head_idx * num_v_heads // num_sab_heads\n tok_start = cu_seqlens[seq_idx]\n seq_len = cutlass.Int32(cu_seqlens[seq_idx + 1] - tok_start)\n\n return WorkDesc(\n seq_idx=seq_idx,\n private_q_head_idx=q_head_idx,\n private_v_head_idx=v_head_idx,\n tok_offset=tok_start,\n seq_len=seq_len,\n tile_idx=cutlass.Int32(0),\n )\n\n # ─── Ordered 2-WG math barriers ───────────────────────────────────────────\n # Translates flat::OrderedNamedBarriers<UseReservedNB, NB0, NB1>.\n # wg_idx: MathWarpGroupRole.KK or MathWarpGroupRole.QK.\n\n @cute.jit\n def _math_order_init(self, wg_idx: cutlass.Int32):\n \"\"\"Pre-arrive at WG0's barrier so WG0 is unblocked on the first wait.\"\"\"\n if wg_idx == MathWarpGroupRole.QK:\n cute.arch.barrier_arrive(\n barrier_id=NamedBarrier.MATH_WG0, number_of_threads=256\n )\n\n @cute.jit\n def _math_order_wait(self, wg_idx: cutlass.Int32):\n \"\"\"Arrive+wait on this WG's own ordered barrier.\"\"\"\n if wg_idx == MathWarpGroupRole.KK:\n cute.arch.barrier(barrier_id=NamedBarrier.MATH_WG0, number_of_threads=256)\n else:\n cute.arch.barrier(barrier_id=NamedBarrier.MATH_WG1, number_of_threads=256)\n\n @cute.jit\n def _math_order_notify(self, wg_idx: cutlass.Int32):\n \"\"\"Arrive at the other WG's barrier to unblock it.\"\"\"\n if wg_idx == MathWarpGroupRole.KK:\n cute.arch.barrier_arrive(\n barrier_id=NamedBarrier.MATH_WG1, number_of_threads=256\n )\n else:\n cute.arch.barrier_arrive(\n barrier_id=NamedBarrier.MATH_WG0, number_of_threads=256\n )\n\n # ─── kk_store_and_inv ─────────────────────────────────────────────────────\n\n @cute.jit\n def _kk_store_and_inv(\n self,\n tKKrKK: cute.Tensor, # fp32 KK accumulator (from 128-thread kk_tiled_mma)\n kk_tiled_mma,\n kk_thread_idx: cutlass.Int32,\n sKK_inv: cute.Tensor, # (BlkKV, BlkKV) 8×8-tiled smem\n sKK_opd: cute.Tensor, # sKK_inv storage recast as Element for MMA operand\n sBeta: cute.Tensor, # (BlkKV, StagesBeta) - used when needs_beta\n beta_pipe_idx: cutlass.Int32,\n tKKcMkk: cute.Tensor, # coordinate mapping for KK fragment\n ):\n \"\"\"Store tKKrKK → sKK_inv, Inverse, optionally reload+beta.\"\"\"\n stsm_atom = cute.make_copy_atom(\n warp.StMatrix8x8x16bOp(transpose=False, num_matrices=4), self.inverse_dtype\n )\n tiled_store = cute.make_tiled_copy_C(stsm_atom, kk_tiled_mma)\n thr_store = tiled_store.get_slice(kk_thread_idx)\n tKKsKK = thr_store.partition_D(sKK_inv)\n tKKrKK_cv = thr_store.retile(tKKrKK)\n tKKrKK_inv = cute.make_fragment_like(tKKrKK_cv, self.inverse_dtype)\n for i in cutlass.range_constexpr(cute.size(tKKrKK_cv)):\n tKKrKK_inv[i] = self.inverse_dtype(tKKrKK_cv[i])\n cute.copy(tiled_store, tKKrKK_inv, tKKsKK)\n\n cute.arch.barrier(barrier_id=NamedBarrier.KK_SYNC, number_of_threads=128)\n CollectiveInverse().run(sKK_inv, NamedBarrier.KK_SYNC)\n\n if cutlass.const_expr(self.needs_beta or self.dtype != self.inverse_dtype):\n cute.arch.barrier(barrier_id=NamedBarrier.KK_SYNC, number_of_threads=128)\n ldsm_atom = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(transpose=False, num_matrices=4),\n self.inverse_dtype,\n )\n tiled_load = cute.make_tiled_copy_C(ldsm_atom, kk_tiled_mma)\n thr_load = tiled_load.get_slice(kk_thread_idx)\n tKKrKK_cpy = cute.make_fragment_like(tKKrKK_inv)\n tKKrKK_cvt = cute.make_fragment_like(tKKrKK_inv, self.dtype)\n cute.copy(tiled_load, thr_load.partition_S(sKK_inv), tKKrKK_cpy)\n tKKcMkk_cv = thr_load.retile(tKKcMkk)\n\n for i in cutlass.range_constexpr(cute.size(tKKrKK_cpy)):\n if cutlass.const_expr(self.needs_beta):\n _, t = tKKcMkk_cv[i]\n tKKrKK_cvt[i] = self.dtype(\n cutlass.Float32(tKKrKK_cpy[i])\n * cutlass.Float32(sBeta[t, beta_pipe_idx])\n )\n else:\n tKKrKK_cvt[i] = self.dtype(tKKrKK_cpy[i])\n\n tKKsKK2 = thr_store.partition_D(sKK_opd)\n cute.copy(tiled_store, tKKrKK_cvt, tKKsKK2)\n\n # ─── qk_and_kk_epi ───────────────────────────────────────────────────────\n\n @cute.jit\n def qk_and_kk_epi(\n self,\n tQKrQK: cute.Tensor,\n tKKrKK: cute.Tensor,\n tQKcMqk: cute.Tensor,\n tKKcMkk: cute.Tensor,\n sAlpha: cute.Tensor,\n sBeta: cute.Tensor,\n alpha_stage: cutlass.Int32,\n beta_stage: cutlass.Int32,\n is_final_block: bool,\n B: cutlass.Int32,\n scale: cutlass.Float32,\n ):\n if cutlass.const_expr(self.needs_beta):\n beta_row = sBeta[None, beta_stage]\n for i in cutlass.range_constexpr(cute.size(tKKcMkk)):\n s, _ = tKKcMkk[i]\n tKKrKK[i] = tKKrKK[i] * cutlass.Float32(beta_row[s])\n\n if cutlass.const_expr(self.needs_alpha):\n alpha_cumlog = sAlpha[None, AlphaProcessor.CUMSUM_LOG, alpha_stage]\n for i in cutlass.range_constexpr(cute.size(tKKcMkk)):\n # s, t = tKKcMkk[i]\n s, t = tQKcMqk[i]\n alpha = cute.math.exp2(\n cutlass.Float32(alpha_cumlog[s]) - cutlass.Float32(alpha_cumlog[t]),\n fastmath=True,\n )\n tQKrQK[i] = tQKrQK[i] * alpha * scale\n tKKrKK[i] = tKKrKK[i] * alpha\n else:\n for i in cutlass.range_constexpr(cute.size(tQKrQK)):\n tQKrQK[i] = tQKrQK[i] * scale\n\n for i in cutlass.range_constexpr(cute.size(tKKcMkk)):\n # s, t = tKKcMkk[i]\n s, t = tQKcMqk[i]\n pred = s >= t\n tQKrQK[i] = tQKrQK[i] if pred else cutlass.Float32(0.0)\n tKKrKK[i] = tKKrKK[i] if pred else cutlass.Float32(0.0)\n if cutlass.const_expr(is_final_block):\n pred = s < B and t < B\n tQKrQK[i] = tQKrQK[i] if pred else cutlass.Float32(0.0)\n tKKrKK[i] = tKKrKK[i] if pred else cutlass.Float32(0.0)\n\n # ─── qk_store ─────────────────────────────────────────────────────────────\n\n @cute.jit\n def qk_store(\n self,\n tQKrQK: cute.Tensor,\n sQK: cute.Tensor,\n qk_tiled_mma,\n qk_thread_idx: cutlass.Int32,\n ):\n stsm_atom = cute.make_copy_atom(\n warp.StMatrix8x8x16bOp(transpose=False, num_matrices=4), self.dtype\n )\n qk_tiled_copy = cute.make_tiled_copy_C(stsm_atom, qk_tiled_mma)\n qk_thr_copy = qk_tiled_copy.get_slice(qk_thread_idx)\n tQKsQK = qk_thr_copy.partition_D(sQK)\n tQKrQK_cvt = cute.make_fragment_like(tQKrQK, self.dtype)\n tQKrQK_cvt_cv = qk_thr_copy.retile(tQKrQK_cvt)\n for i in cutlass.range_constexpr(cute.size(tQKrQK)):\n tQKrQK_cvt[i] = self.dtype(tQKrQK[i])\n cute.copy(qk_tiled_copy, tQKrQK_cvt_cv, tQKsQK)\n\n # ─── o1_epi ───────────────────────────────────────────────────────────────\n\n @cute.jit\n def o1_epi(\n self,\n tOrO: cute.Tensor,\n tOcO: cute.Tensor,\n sAlpha: cute.Tensor,\n alpha_stage: cutlass.Int32,\n scale: cutlass.Float32,\n ):\n if cutlass.const_expr(self.needs_alpha):\n alpha_cpscale = sAlpha[None, AlphaProcessor.CUMPROD_SCALE, alpha_stage]\n for i in cutlass.range_constexpr(cute.size(tOrO)):\n _, tok_q = tOcO[i]\n tOrO[i] = cutlass.Float32(alpha_cpscale[tok_q]) * tOrO[i]\n else:\n for i in cutlass.range_constexpr(cute.size(tOrO)):\n tOrO[i] = scale * tOrO[i]\n\n # ─── sk_epi ───────────────────────────────────────────────────────────────\n\n @cute.jit\n def sk_epi(\n self,\n tSKrSK: cute.Tensor,\n tSKcSK: cute.Tensor,\n sAlpha: cute.Tensor,\n alpha_stage: cutlass.Int32,\n ):\n if cutlass.const_expr(self.needs_alpha):\n alpha_cp = sAlpha[None, AlphaProcessor.CUMPROD, alpha_stage]\n for i in cutlass.range_constexpr(cute.size(tSKrSK)):\n _, tok_kv = tSKcSK[i]\n tSKrSK[i] = tSKrSK[i] * cutlass.Float32(alpha_cp[tok_kv])\n\n # ─── sk_load_v ────────────────────────────────────────────────────────────\n\n @cute.jit\n def sk_load_v(\n self,\n tSKrSK: cute.Tensor,\n sV_DS: cute.Tensor,\n sk_tiled_copy_C,\n sk_thr_copy_C,\n v_stage: cutlass.Int32,\n ) -> cute.Tensor:\n tSKrV = cute.make_fragment_like(tSKrSK, self.dtype)\n tSKrV_cv = sk_thr_copy_C.retile(tSKrV)\n tSKsV = sk_thr_copy_C.partition_S(sV_DS)\n cute.copy(sk_tiled_copy_C, tSKsV[None, None, None, v_stage], tSKrV_cv)\n return tSKrV\n\n # ─── kv_decay_v ───────────────────────────────────────────────────────────\n\n @cute.jit\n def kv_decay_v(\n self,\n tKVrV: cute.Tensor,\n tKVcV: cute.Tensor,\n sAlpha: cute.Tensor,\n alpha_stage: cutlass.Int32,\n is_final_block: bool,\n B: cutlass.Int32,\n ):\n if cutlass.const_expr(self.needs_alpha):\n alpha_cumlog = sAlpha[None, AlphaProcessor.CUMSUM_LOG, alpha_stage]\n block_log = cutlass.Float32(alpha_cumlog[B - cutlass.Int32(1)])\n for i in cutlass.range_constexpr(cute.size(tKVrV)):\n _, tok = tKVcV[i]\n coeff = cute.math.exp2(\n block_log - cutlass.Float32(alpha_cumlog[tok]), fastmath=True\n )\n if cutlass.const_expr(is_final_block):\n if tok >= B:\n coeff = cutlass.Float32(0.0)\n tKVrV[i] = self.dtype(cutlass.Float32(tKVrV[i]) * coeff)\n else:\n for i in cutlass.range_constexpr(cute.size(tKVrV)):\n _, tok = tKVcV[i]\n if cutlass.const_expr(is_final_block):\n if tok >= B:\n tKVrV[i] = self.dtype(0.0)\n\n # ─── o_store ──────────────────────────────────────────────────────────────\n\n @cute.jit\n def o_store(\n self,\n tOrO: cute.Tensor,\n tOsO: cute.Tensor,\n o_tiled_copy_r2s,\n o_thr_copy_r2s,\n ):\n tOrO_f16 = cute.make_fragment_like(tOrO, self.dtype)\n for i in cutlass.range_constexpr(cute.size(tOrO)):\n tOrO_f16[i] = self.dtype(tOrO[i])\n tOrO_cv = o_thr_copy_r2s.retile(tOrO_f16)\n cute.arch.fence_view_async_shared()\n cute.copy(o_tiled_copy_r2s, tOrO_cv, tOsO)\n cute.arch.fence_view_async_shared()\n\n # ─── TMA load helpers ────────────────────────────────────────────────────\n\n @cute.jit\n def load_qkv_tma(\n self,\n sQ_SD: cute.Tensor,\n sK_DS: cute.Tensor,\n sV_DS: cute.Tensor,\n tma_atom_q: cute.CopyAtom,\n tma_tensor_q: cute.Tensor,\n tma_atom_k: cute.CopyAtom,\n tma_tensor_k: cute.Tensor,\n tma_atom_v: cute.CopyAtom,\n tma_tensor_v: cute.Tensor,\n q_pipeline,\n q_producer_state,\n k_pipeline,\n k_producer_state,\n v_pipeline,\n v_producer_state,\n blk: cutlass.Int32,\n tok_start,\n q_head_idx: cutlass.Int32,\n k_head_idx: cutlass.Int32,\n v_head_idx: cutlass.Int32,\n ):\n blk_tok = tok_start + blk * cutlass.Int32(self.BLK_KV)\n\n sK = sK_DS[None, None, k_producer_state.index]\n mK = cute.domain_offset(\n (cutlass.Int32(0), blk_tok),\n tma_tensor_k[None, None, k_head_idx],\n )\n gK = cute.zipped_divide(mK, (self.D, self.BLK_KV))[\n ((None, None), (cutlass.Int32(0), cutlass.Int32(0)))\n ]\n tKsK, tKgK = cpasync.tma_partition(\n tma_atom_k,\n 0,\n cute.make_layout(1),\n cute.group_modes(sK, 0, 2),\n cute.group_modes(gK, 0, 2),\n )\n k_pipeline.producer_acquire(k_producer_state)\n cute.copy(\n tma_atom_k,\n tKgK,\n tKsK,\n tma_bar_ptr=k_pipeline.producer_get_barrier(k_producer_state),\n )\n k_pipeline.producer_commit(k_producer_state)\n k_producer_state.advance()\n\n sQ = sQ_SD[None, None, q_producer_state.index]\n mQ = cute.domain_offset(\n (blk_tok, cutlass.Int32(0)),\n tma_tensor_q[None, None, q_head_idx],\n )\n gQ = cute.zipped_divide(mQ, (self.BLK_Q, self.D))[\n ((None, None), (cutlass.Int32(0), cutlass.Int32(0)))\n ]\n tQsQ, tQgQ = cpasync.tma_partition(\n tma_atom_q,\n 0,\n cute.make_layout(1),\n cute.group_modes(sQ, 0, 2),\n cute.group_modes(gQ, 0, 2),\n )\n q_pipeline.producer_acquire(q_producer_state)\n cute.copy(\n tma_atom_q,\n tQgQ,\n tQsQ,\n tma_bar_ptr=q_pipeline.producer_get_barrier(q_producer_state),\n )\n q_pipeline.producer_commit(q_producer_state)\n q_producer_state.advance()\n\n sV = sV_DS[None, None, v_producer_state.index]\n mV = cute.domain_offset(\n (cutlass.Int32(0), blk_tok),\n tma_tensor_v[None, None, v_head_idx],\n )\n gV = cute.zipped_divide(mV, (self.D, self.BLK_KV))[\n ((None, None), (cutlass.Int32(0), cutlass.Int32(0)))\n ]\n tVsV, tVgV = cpasync.tma_partition(\n tma_atom_v,\n 0,\n cute.make_layout(1),\n cute.group_modes(sV, 0, 2),\n cute.group_modes(gV, 0, 2),\n )\n v_pipeline.producer_acquire(v_producer_state)\n cute.copy(\n tma_atom_v,\n tVgV,\n tVsV,\n tma_bar_ptr=v_pipeline.producer_get_barrier(v_producer_state),\n )\n v_pipeline.producer_commit(v_producer_state)\n v_producer_state.advance()\n return q_producer_state, k_producer_state, v_producer_state\n\n # ─── load_alpha ───────────────────────────────────────────────────────────\n # Translates FlatMainloopTmaWarpSpecializedDeltaRule::load_alpha (scalar load).\n # Caller must sync before calling AlphaProcessor on the loaded data.\n\n @cute.jit\n def load_alpha(\n self,\n sAlpha: cute.Tensor,\n g_alpha: cute.Tensor,\n blk_tok: cutlass.Int32,\n tok_end,\n sab_head_idx: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n alpha_stage: cutlass.Int32,\n ):\n lane_id = cute.arch.lane_idx()\n sAlpha_k = sAlpha[None, None, alpha_stage]\n num_iters = self.BLK_Q // 32\n for i in cutlass.range_constexpr(num_iters):\n row = cutlass.Int32(i * 32) + lane_id\n tok = blk_tok + row\n if tok < tok_end:\n sAlpha_k[row, AlphaProcessor.CUMSUM_LOG] = g_alpha[\n tok * num_sab_heads + sab_head_idx\n ]\n else:\n sAlpha_k[row, AlphaProcessor.CUMSUM_LOG] = cutlass.Float32(1.0)\n\n # ─── load_beta ────────────────────────────────────────────────────────────\n # Translates FlatMainloopTmaWarpSpecializedDeltaRule::load_beta.\n\n @cute.jit\n def load_beta(\n self,\n sBeta: cute.Tensor,\n g_beta: cute.Tensor,\n blk_tok: cutlass.Int32,\n tok_end,\n sab_head_idx: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n beta_stage: cutlass.Int32,\n ):\n lane_id = cute.arch.lane_idx()\n sBeta_k = sBeta[None, beta_stage]\n num_iters = self.BLK_KV // 32\n for i in cutlass.range_constexpr(num_iters):\n row = cutlass.Int32(i * 32) + lane_id\n tok = blk_tok + row\n if tok < tok_end:\n sBeta_k[row] = g_beta[tok * num_sab_heads + sab_head_idx]\n else:\n sBeta_k[row] = cutlass.Float32(0.0)\n\n # ─── kv_load / kv_store ───────────────────────────────────────────────────\n\n @cute.jit\n def kv_load(\n self,\n tKVrKV: cute.Tensor,\n gKV: cute.Tensor,\n kv_tiled_mma,\n thread_idx: cutlass.Int32,\n ):\n copy_atom_kv = cute.make_copy_atom(\n cute.nvgpu.CopyUniversalOp(), gKV.element_type\n )\n tiled_copy_kv = cute.make_tiled_copy_C(copy_atom_kv, kv_tiled_mma)\n thr_copy_kv = tiled_copy_kv.get_slice(thread_idx)\n tKVgKV = thr_copy_kv.partition_S(select_tensor_10(gKV))\n tKVrKV_storage = cute.make_rmem_tensor_like(tKVrKV, gKV.element_type)\n cute.copy(tiled_copy_kv, tKVgKV, tKVrKV_storage)\n tKVrKV.store(tKVrKV_storage.load().to(self.acc_dtype))\n\n @cute.jit\n def kv_store(\n self,\n tKVrKV: cute.Tensor,\n gKV: cute.Tensor,\n kv_tiled_mma,\n thread_idx: cutlass.Int32,\n ):\n copy_atom_kv = cute.make_copy_atom(\n cute.nvgpu.CopyUniversalOp(), gKV.element_type\n )\n tiled_copy_kv = cute.make_tiled_copy_C(copy_atom_kv, kv_tiled_mma)\n thr_copy_kv = tiled_copy_kv.get_slice(thread_idx)\n tKVgKV = thr_copy_kv.partition_D(select_tensor_10(gKV))\n tKVrKV_storage = cute.make_rmem_tensor_like(tKVrKV, gKV.element_type)\n tKVrKV_storage.store(tKVrKV.load().to(gKV.element_type))\n cute.copy(tiled_copy_kv, tKVrKV_storage, tKVgKV)\n\n @cute.jit\n def maybe_store_checkpoint(\n self,\n tKVrKV: cute.Tensor,\n g_state_checkpoints: cute.Tensor,\n checkpoint_cu_starts: cute.Tensor,\n checkpoint_every_n_tokens: cutlass.Int32,\n kv_tiled_mma,\n thread_idx: cutlass.Int32,\n seq_idx: cutlass.Int32,\n o_head_idx: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n total_checkpoints: cutlass.Int32,\n block_end: cutlass.Int32,\n seq_len: cutlass.Int32,\n ):\n if cutlass.const_expr(self.needs_checkpointing):\n if (\n block_end <= seq_len\n and block_end % checkpoint_every_n_tokens == cutlass.Int32(0)\n ):\n checkpoint_idx = (\n cutlass.Int32(checkpoint_cu_starts[seq_idx])\n + block_end // checkpoint_every_n_tokens\n - cutlass.Int32(1)\n )\n checkpoint_layout = cute.make_ordered_layout(\n (self.D, self.D, num_sab_heads, total_checkpoints),\n order=(0, 1, 2, 3),\n )\n mCheckpoint = cute.make_tensor(\n g_state_checkpoints.iterator, checkpoint_layout\n )\n gCheckpointKV = mCheckpoint[None, None, o_head_idx, checkpoint_idx]\n self.kv_store(tKVrKV, gCheckpointKV, kv_tiled_mma, thread_idx)\n\n # ─── compute_loop_body ───────────────────────────────────────────────────\n # Translates the C++ compute_loop_body lambda captured inside compute().\n # Called by Math WGs (tidx >= 128) for one block iteration.\n\n @cute.jit\n def compute_loop_body(\n self,\n # Smem tensors (staged; caller indexes the active stage)\n sQ_SD: cute.Tensor, # (BlkQ, D, StagesQ) – row-major atom, swizzled\n sK_SD: cute.Tensor, # (BlkKV, D, StagesK) – same atom\n sK_DS: cute.Tensor, # (D, BlkKV, StagesK) – K transposed\n sV_DS: cute.Tensor, # (D, BlkKV, StagesV) – V transposed\n sQK: cute.Tensor, # (BlkQ, BlkKV, StagesQK)\n sKK_inv: cute.Tensor, # (BlkKV, BlkKV, StagesKK)\n sKK_opd: cute.Tensor, # sKK_inv storage recast as Element\n sO: cute.Tensor, # O output smem (staged)\n sAlpha: cute.Tensor, # (BlkQ, AlphaProcessor.NUM_CHANNELS, StagesAlpha) or zero-shaped\n kv_tiled_mma,\n # Mainloop pipelines and active read states\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n v_pipeline,\n v_consumer_state,\n o_pipeline,\n o_producer_state,\n qk_pipeline,\n qk_consumer_state,\n kk_pipeline,\n kk_consumer_state,\n alpha_pipeline,\n alpha_consumer_state,\n # Compile-time flags\n is_first_block: bool,\n is_final_block: bool,\n # Valid token count for masking on final block\n B: cutlass.Int32,\n # Running KV state (D×D fp32, in registers across all blocks)\n tKVrKV: cute.Tensor,\n # Scale factor\n scale: cutlass.Float32,\n # WG role: MathWarpGroupRole.STATE0 or MathWarpGroupRole.STATE1.\n wg_idx: cutlass.Int32,\n ):\n tidx, _, _ = cute.arch.thread_idx()\n thread_idx = tidx - cutlass.Int32(128) # relative to compute threads\n # ── TiledMMAs ─────────────────────────────────────────────────────────\n blk_q = cute.size(sQ_SD, mode=[0])\n blk_kv = cute.size(sK_SD, mode=[0])\n d = cute.size(sQ_SD, mode=[1])\n mma_atom_o1 = cute.make_mma_atom(\n warpgroup.MmaF16BF16Op(\n self.dtype,\n self.acc_dtype,\n (64, blk_q, 16),\n warpgroup.OperandSource.RMEM,\n cute.nvgpu.OperandMajorMode.K,\n cute.nvgpu.OperandMajorMode.K,\n )\n )\n mma_atom_o2 = cute.make_mma_atom(\n warpgroup.MmaF16BF16Op(\n self.dtype,\n self.acc_dtype,\n (64, blk_q, 16),\n warpgroup.OperandSource.RMEM,\n cute.nvgpu.OperandMajorMode.K,\n cute.nvgpu.OperandMajorMode.K,\n )\n )\n mma_atom_sk = cute.make_mma_atom(\n warpgroup.MmaF16BF16Op(\n self.dtype,\n self.acc_dtype,\n (64, blk_kv, 16),\n warpgroup.OperandSource.RMEM,\n cute.nvgpu.OperandMajorMode.K,\n cute.nvgpu.OperandMajorMode.K,\n )\n )\n mma_atom_newv = cute.make_mma_atom(\n warpgroup.MmaF16BF16Op(\n self.dtype,\n self.acc_dtype,\n (64, blk_kv, 16),\n warpgroup.OperandSource.RMEM,\n cute.nvgpu.OperandMajorMode.K,\n cute.nvgpu.OperandMajorMode.K,\n )\n )\n\n # O1/O2/SK/NewV: two state warpgroups cooperate as in the C++ Hopper GMMA path.\n o1_tiled_mma = cute.make_tiled_mma(mma_atom_o1, cute.make_layout((2, 1, 1)))\n o2_tiled_mma = cute.make_tiled_mma(mma_atom_o2, cute.make_layout((2, 1, 1)))\n sk_tiled_mma = cute.make_tiled_mma(mma_atom_sk, cute.make_layout((2, 1, 1)))\n newv_tiled_mma = cute.make_tiled_mma(mma_atom_newv, cute.make_layout((2, 1, 1)))\n\n # ── Thread slices ─────────────────────────────────────────────────────\n sk_thr_mma = sk_tiled_mma.get_slice(thread_idx)\n newv_thr_mma = newv_tiled_mma.get_slice(thread_idx)\n o1_thr_mma = o1_tiled_mma.get_slice(thread_idx)\n o2_thr_mma = o2_tiled_mma.get_slice(thread_idx)\n kv_thr_mma = kv_tiled_mma.get_slice(thread_idx)\n\n # ── Copy atoms ────────────────────────────────────────────────────────\n ldsm_t4 = cute.make_copy_atom(\n warp.LdMatrix8x8x16bOp(transpose=True, num_matrices=4), self.dtype\n )\n\n # ── SK copies ─────────────────────────────────────────────────────────\n # SK C: V loaded from sV_DS (col-major D×BlkKV) with LDSM_T.\n sk_tiled_copy_C = cute.make_tiled_copy_C(ldsm_t4, sk_tiled_mma)\n sk_thr_copy_C = sk_tiled_copy_C.get_slice(thread_idx)\n tSKsK = sk_thr_mma.partition_B(sK_SD)\n tSKrK = sk_thr_mma.make_fragment_B(tSKsK)\n\n # ── NewV copies ───────────────────────────────────────────────────────\n tNewVsB = newv_thr_mma.partition_B(sKK_opd)\n tNewVrB = newv_thr_mma.make_fragment_B(tNewVsB)\n\n # ── KV copies ─────────────────────────────────────────────────────────\n tKVsK = kv_thr_mma.partition_B(sK_DS)\n tKVrK = kv_thr_mma.make_fragment_B(tKVsK)\n\n # ── O1/O2 copies ──────────────────────────────────────────────────────\n tOsQ = o1_thr_mma.partition_B(sQ_SD)\n tOrQ = o1_thr_mma.make_fragment_B(tOsQ)\n tOsQK = o2_thr_mma.partition_B(sQK)\n tOrQK = o2_thr_mma.make_fragment_B(tOsQK)\n\n # ── O store (R→S STSM) ────────────────────────────────────────────────\n o_stsm = cute.make_copy_atom(\n warp.StMatrix8x8x16bOp(transpose=True, num_matrices=4), self.dtype\n )\n o_tiled_copy_r2s = cute.make_tiled_copy_C(o_stsm, o1_tiled_mma)\n o_thr_copy_r2s = o_tiled_copy_r2s.get_slice(thread_idx)\n tOsO = o_thr_copy_r2s.partition_D(sO)\n\n # ── Coordinate tensors for masking / alpha/beta indexing ──────────────\n cO = cute.make_identity_tensor((d, blk_q))\n tOcO = o1_thr_mma.partition_C(cO)\n cSK = cute.make_identity_tensor((d, blk_kv))\n tSKcSK = sk_thr_mma.partition_C(cSK)\n cV = cute.make_identity_tensor((d, blk_kv))\n tKVcV = kv_thr_mma.partition_A(cV)\n\n # ── O1: KV_state @ Q (both state WGs, skip on first block) ───────────\n q_pipeline.consumer_wait(q_consumer_state)\n if cutlass.const_expr(self.needs_alpha):\n alpha_pipeline.consumer_wait(alpha_consumer_state)\n cute.arch.fence_view_async_shared()\n tOrO = o1_thr_mma.make_fragment_C(o1_thr_mma.partition_shape_C((d, blk_q)))\n if cutlass.const_expr(not is_first_block):\n tOrKV = SM90.make_acc_into_op(tKVrKV, o1_tiled_mma, self.dtype)\n SM90.warpgroup_fence_operand(tOrKV)\n SM90.warpgroup_fence_operand(tOrO)\n cute.nvgpu.warpgroup.fence()\n self._math_order_wait(wg_idx)\n SM90.wgmma_gemm_zero_acc(\n o1_tiled_mma,\n tOrO,\n tOrKV,\n tOrQ[None, None, None, q_consumer_state.index],\n )\n cute.nvgpu.warpgroup.commit_group()\n self._math_order_notify(wg_idx)\n cute.nvgpu.warpgroup.wait_group(0)\n self.o1_epi(tOrO, tOcO, sAlpha, alpha_consumer_state.index, scale)\n q_pipeline.consumer_release(q_consumer_state)\n q_consumer_state.advance()\n\n # ── SK: KV_state @ K^T (result negated below via V - SK) ─────────────\n k_pipeline.consumer_wait(k_consumer_state)\n tSKrSK = sk_thr_mma.make_fragment_C(sk_thr_mma.partition_shape_C((d, blk_kv)))\n if cutlass.const_expr(not is_first_block):\n tSKrS = SM90.make_acc_into_op(tKVrKV, sk_tiled_mma, self.dtype)\n SM90.warpgroup_fence_operand(tSKrSK)\n SM90.warpgroup_fence_operand(tSKrS)\n cute.nvgpu.warpgroup.fence()\n self._math_order_wait(wg_idx)\n SM90.wgmma_gemm_zero_acc(\n sk_tiled_mma,\n tSKrSK,\n tSKrS,\n tSKrK[None, None, None, k_consumer_state.index],\n )\n cute.nvgpu.warpgroup.commit_group()\n self._math_order_notify(wg_idx)\n cute.nvgpu.warpgroup.wait_group(0)\n\n # ── Load V from smem ──────────────────────────────────────────────────\n v_pipeline.consumer_wait(v_consumer_state)\n tSKrV = self.sk_load_v(\n tSKrSK,\n sV_DS,\n sk_tiled_copy_C,\n sk_thr_copy_C,\n v_consumer_state.index,\n )\n\n # sk_epi + V - SK (SK=0 on first block, so V - SK = V)\n if cutlass.const_expr(not is_first_block):\n self.sk_epi(tSKrSK, tSKcSK, sAlpha, alpha_consumer_state.index)\n for i in cutlass.range_constexpr(cute.size(tSKrV)):\n tSKrV[i] = tSKrV[i] - self.dtype(tSKrSK[i])\n\n # ── NewV = (V - SK) @ T^T (ordered: WG0 first) ──────────────────────\n tNewVrA = SM90.make_acc_into_op(tSKrV, newv_tiled_mma, self.dtype)\n tNewVrC = newv_thr_mma.make_fragment_C(\n newv_thr_mma.partition_shape_C((d, blk_kv))\n )\n kk_pipeline.consumer_wait(kk_consumer_state)\n SM90.warpgroup_fence_operand(tNewVrA)\n SM90.warpgroup_fence_operand(tNewVrC)\n cute.nvgpu.warpgroup.fence()\n self._math_order_wait(wg_idx)\n SM90.wgmma_gemm_zero_acc(\n newv_tiled_mma,\n tNewVrC,\n tNewVrA,\n tNewVrB[None, None, None, kk_consumer_state.index],\n )\n cute.nvgpu.warpgroup.commit_group()\n self._math_order_notify(wg_idx)\n cute.nvgpu.warpgroup.wait_group(0)\n v_pipeline.consumer_release(v_consumer_state)\n v_consumer_state.advance()\n kk_pipeline.consumer_release(kk_consumer_state)\n kk_consumer_state.advance()\n\n # ── O2 = O1 + NewV @ QK (ordered: WG0 first) ────────────────────────\n tOrV_or_tKVrV = SM90.make_acc_into_op(tNewVrC, kv_tiled_mma, self.dtype)\n qk_pipeline.consumer_wait(qk_consumer_state)\n SM90.warpgroup_fence_operand(tOrV_or_tKVrV)\n SM90.warpgroup_fence_operand(tOrO)\n cute.nvgpu.warpgroup.fence()\n self._math_order_wait(wg_idx)\n SM90.wgmma_gemm(\n o2_tiled_mma,\n tOrO,\n tOrV_or_tKVrV,\n tOrQK[None, None, None, qk_consumer_state.index],\n not is_first_block,\n )\n cute.nvgpu.warpgroup.commit_group()\n self._math_order_notify(wg_idx)\n cute.nvgpu.warpgroup.wait_group(0)\n qk_pipeline.consumer_release(qk_consumer_state)\n qk_consumer_state.advance()\n\n # ── O store to smem ───────────────────────────────────────────────────\n o_pipeline.producer_acquire(o_producer_state)\n self.o_store(\n tOrO,\n tOsO[None, None, None, o_producer_state.index],\n o_tiled_copy_r2s,\n o_thr_copy_r2s,\n )\n o_pipeline.producer_commit(o_producer_state)\n o_producer_state.advance()\n\n # ── KV state update ───────────────────────────────────────────────────\n block_coeff = cutlass.Float32(1.0)\n if cutlass.const_expr(self.needs_alpha):\n block_coeff = cutlass.Float32(\n sAlpha[\n B - cutlass.Int32(1),\n AlphaProcessor.CUMPROD,\n alpha_consumer_state.index,\n ]\n )\n\n for i in cutlass.range(cute.size(tKVrKV), unroll_full=True):\n tKVrKV[i] = block_coeff * tKVrKV[i]\n\n self.kv_decay_v(\n tOrV_or_tKVrV, tKVcV, sAlpha, alpha_consumer_state.index, is_final_block, B\n )\n\n # KV += NewV @ K\n SM90.warpgroup_fence_operand(tOrV_or_tKVrV)\n SM90.warpgroup_fence_operand(tKVrKV)\n cute.nvgpu.warpgroup.fence()\n self._math_order_wait(wg_idx)\n SM90.wgmma_gemm(\n kv_tiled_mma,\n tKVrKV,\n tOrV_or_tKVrV,\n tKVrK[None, None, None, k_consumer_state.index],\n True,\n )\n cute.nvgpu.warpgroup.commit_group()\n self._math_order_notify(wg_idx)\n cute.nvgpu.warpgroup.wait_group(0)\n k_pipeline.consumer_release(k_consumer_state)\n k_consumer_state.advance()\n if cutlass.const_expr(self.needs_alpha):\n alpha_pipeline.consumer_release(alpha_consumer_state)\n alpha_consumer_state.advance()\n return (\n q_consumer_state,\n k_consumer_state,\n v_consumer_state,\n o_producer_state,\n qk_consumer_state,\n kk_consumer_state,\n alpha_consumer_state,\n )\n\n # ─── Warp role entry points ──────────────────────────────────────────────\n # The current DSL bridge still uses CTA-wide sync epochs, but each role owns\n # its own loop, matching the C++ warp-specialized dispatch shape.\n\n @cute.jit\n def run_load_qkv_role(\n self,\n sQ_SD: cute.Tensor,\n sK_DS: cute.Tensor,\n sV_DS: cute.Tensor,\n tma_atom_q: cute.CopyAtom,\n tma_tensor_q: cute.Tensor,\n tma_atom_k: cute.CopyAtom,\n tma_tensor_k: cute.Tensor,\n tma_atom_v: cute.CopyAtom,\n tma_tensor_v: cute.Tensor,\n q_pipeline,\n k_pipeline,\n v_pipeline,\n num_blocks: cutlass.Int32,\n tok_start,\n q_head_idx: cutlass.Int32,\n k_head_idx: cutlass.Int32,\n v_head_idx: cutlass.Int32,\n ):\n q_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.q_stage\n )\n k_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.k_stage\n )\n v_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.v_stage\n )\n for blk in cutlass.range(num_blocks, unroll=1):\n (\n q_producer_state,\n k_producer_state,\n v_producer_state,\n ) = self.load_qkv_tma(\n sQ_SD,\n sK_DS,\n sV_DS,\n tma_atom_q,\n tma_tensor_q,\n tma_atom_k,\n tma_tensor_k,\n tma_atom_v,\n tma_tensor_v,\n q_pipeline,\n q_producer_state,\n k_pipeline,\n k_producer_state,\n v_pipeline,\n v_producer_state,\n blk,\n tok_start,\n q_head_idx,\n k_head_idx,\n v_head_idx,\n )\n\n @cute.jit\n def run_load_alpha_role(\n self,\n sAlpha: cute.Tensor,\n g_alpha: cute.Tensor,\n alpha_pipeline,\n scale: cutlass.Float32,\n num_blocks: cutlass.Int32,\n tok_start,\n tok_end,\n sab_head_idx: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n ):\n alpha_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.alpha_beta_stage\n )\n for blk in cutlass.range(num_blocks, unroll=1):\n blk_tok = tok_start + blk * cutlass.Int32(self.BLK_Q)\n if cutlass.const_expr(self.needs_alpha):\n alpha_pipeline.producer_acquire(alpha_producer_state)\n cute.arch.fence_view_async_shared()\n self.load_alpha(\n sAlpha,\n g_alpha,\n blk_tok,\n tok_end,\n sab_head_idx,\n num_sab_heads,\n alpha_producer_state.index,\n )\n AlphaProcessor().run(\n sAlpha[None, None, alpha_producer_state.index], scale\n )\n cute.arch.fence_view_async_shared()\n alpha_pipeline.producer_commit(alpha_producer_state)\n alpha_producer_state.advance()\n\n @cute.jit\n def run_load_beta_role(\n self,\n sBeta: cute.Tensor,\n g_beta: cute.Tensor,\n beta_pipeline,\n num_blocks: cutlass.Int32,\n tok_start,\n tok_end,\n sab_head_idx: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n ):\n beta_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.alpha_beta_stage\n )\n for blk in cutlass.range(num_blocks, unroll=1):\n blk_tok = tok_start + blk * cutlass.Int32(self.BLK_KV)\n if cutlass.const_expr(self.needs_beta):\n beta_pipeline.producer_acquire(beta_producer_state)\n cute.arch.fence_view_async_shared()\n self.load_beta(\n sBeta,\n g_beta,\n blk_tok,\n tok_end,\n sab_head_idx,\n num_sab_heads,\n beta_producer_state.index,\n )\n cute.arch.fence_view_async_shared()\n beta_pipeline.producer_commit(beta_producer_state)\n beta_producer_state.advance()\n\n @cute.jit\n def run_state_math_role(\n self,\n sQ_SD: cute.Tensor,\n sK_SD: cute.Tensor,\n sK_DS: cute.Tensor,\n sV_DS: cute.Tensor,\n sQK: cute.Tensor,\n sKK_inv: cute.Tensor,\n sKK_opd: cute.Tensor,\n sO: cute.Tensor,\n sAlpha: cute.Tensor,\n q_pipeline,\n k_pipeline,\n v_pipeline,\n o_pipeline,\n qk_pipeline,\n kk_pipeline,\n alpha_pipeline,\n g_state: cute.Tensor,\n g_init_state: cute.Tensor,\n g_state_indices: cute.Tensor,\n g_state_checkpoints: cute.Tensor,\n checkpoint_cu_starts: cute.Tensor,\n work_desc: WorkDesc,\n scale: cutlass.Float32,\n wg_idx: cutlass.Int32,\n math_tidx: cutlass.Int32,\n num_blocks: cutlass.Int32,\n num_q_heads: cutlass.Int32,\n num_v_heads: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n num_seqs: cutlass.Int32,\n total_checkpoints: cutlass.Int32,\n checkpoint_every_n_tokens: cutlass.Int32,\n ):\n self._math_order_init(wg_idx)\n q_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.q_stage\n )\n k_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.k_stage\n )\n v_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.v_stage\n )\n o_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.o_stage\n )\n qk_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.qk_stage\n )\n kk_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.kk_stage\n )\n alpha_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.alpha_beta_stage\n )\n\n kv_tiled_mma = cute.make_tiled_mma(\n cute.make_mma_atom(\n warpgroup.MmaF16BF16Op(\n self.dtype,\n self.acc_dtype,\n (64, self.D, 16),\n warpgroup.OperandSource.RMEM,\n cute.nvgpu.OperandMajorMode.K,\n cute.nvgpu.OperandMajorMode.MN,\n )\n ),\n cute.make_layout((2, 1, 1)),\n )\n kv_thr_mma = kv_tiled_mma.get_slice(math_tidx)\n tKVrKV = kv_thr_mma.make_fragment_C(\n kv_thr_mma.partition_shape_C((self.D, self.D))\n )\n tKVrKV.fill(self.acc_dtype(0.0))\n\n packed_state_layout = cute.make_ordered_layout(\n (self.D, self.D, num_sab_heads, num_seqs), order=(0, 1, 2, 3)\n )\n state_ref_shape = (g_state.shape[0], g_state.shape[1], self.D, self.D)\n state_ref_layout = cute.make_layout(state_ref_shape, stride=g_state.stride)\n indexed_state_layout = cute.select(state_ref_layout, mode=[3, 2, 1, 0])\n state_idx = work_desc.seq_idx\n if cutlass.const_expr(self.use_state_indices):\n state_idx = cutlass.Int32(g_state_indices[work_desc.seq_idx])\n state_layout = indexed_state_layout\n else:\n state_layout = packed_state_layout\n o_head_idx = work_desc.o_head_idx(num_q_heads, num_v_heads)\n mState = cute.make_tensor(g_state.iterator, state_layout)\n gStateKV = mState[None, None, o_head_idx, state_idx]\n if cutlass.const_expr(self.needs_init_state):\n init_state_ref_layout = cute.make_layout(\n state_ref_shape, stride=g_init_state.stride\n )\n indexed_init_state_layout = cute.select(\n init_state_ref_layout, mode=[3, 2, 1, 0]\n )\n if cutlass.const_expr(self.use_state_indices):\n init_state_layout = indexed_init_state_layout\n else:\n init_state_layout = packed_state_layout\n mInitState = cute.make_tensor(g_init_state.iterator, init_state_layout)\n gInitKV = mInitState[None, None, o_head_idx, state_idx]\n self.kv_load(tKVrKV, gInitKV, kv_tiled_mma, math_tidx)\n\n first_B = work_desc.seq_len\n if first_B > cutlass.Int32(self.BLK_KV):\n first_B = cutlass.Int32(self.BLK_KV)\n if cutlass.const_expr(self.needs_init_state):\n (\n q_consumer_state,\n k_consumer_state,\n v_consumer_state,\n o_producer_state,\n qk_consumer_state,\n kk_consumer_state,\n alpha_consumer_state,\n ) = self.compute_loop_body(\n sQ_SD,\n sK_SD,\n sK_DS,\n sV_DS,\n sQK,\n sKK_inv,\n sKK_opd,\n sO,\n sAlpha,\n kv_tiled_mma,\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n v_pipeline,\n v_consumer_state,\n o_pipeline,\n o_producer_state,\n qk_pipeline,\n qk_consumer_state,\n kk_pipeline,\n kk_consumer_state,\n alpha_pipeline,\n alpha_consumer_state,\n False,\n True,\n first_B,\n tKVrKV,\n scale,\n wg_idx,\n )\n else:\n (\n q_consumer_state,\n k_consumer_state,\n v_consumer_state,\n o_producer_state,\n qk_consumer_state,\n kk_consumer_state,\n alpha_consumer_state,\n ) = self.compute_loop_body(\n sQ_SD,\n sK_SD,\n sK_DS,\n sV_DS,\n sQK,\n sKK_inv,\n sKK_opd,\n sO,\n sAlpha,\n kv_tiled_mma,\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n v_pipeline,\n v_consumer_state,\n o_pipeline,\n o_producer_state,\n qk_pipeline,\n qk_consumer_state,\n kk_pipeline,\n kk_consumer_state,\n alpha_pipeline,\n alpha_consumer_state,\n True,\n True,\n first_B,\n tKVrKV,\n scale,\n wg_idx,\n )\n self.maybe_store_checkpoint(\n tKVrKV,\n g_state_checkpoints,\n checkpoint_cu_starts,\n checkpoint_every_n_tokens,\n kv_tiled_mma,\n math_tidx,\n work_desc.seq_idx,\n o_head_idx,\n num_sab_heads,\n total_checkpoints,\n cutlass.Int32(self.BLK_KV),\n work_desc.seq_len,\n )\n\n for blk in cutlass.range(\n cutlass.Int32(1), num_blocks - cutlass.Int32(1), cutlass.Int32(1), unroll=1\n ):\n (\n q_consumer_state,\n k_consumer_state,\n v_consumer_state,\n o_producer_state,\n qk_consumer_state,\n kk_consumer_state,\n alpha_consumer_state,\n ) = self.compute_loop_body(\n sQ_SD,\n sK_SD,\n sK_DS,\n sV_DS,\n sQK,\n sKK_inv,\n sKK_opd,\n sO,\n sAlpha,\n kv_tiled_mma,\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n v_pipeline,\n v_consumer_state,\n o_pipeline,\n o_producer_state,\n qk_pipeline,\n qk_consumer_state,\n kk_pipeline,\n kk_consumer_state,\n alpha_pipeline,\n alpha_consumer_state,\n False,\n False,\n cutlass.Int32(self.BLK_KV),\n tKVrKV,\n scale,\n wg_idx,\n )\n self.maybe_store_checkpoint(\n tKVrKV,\n g_state_checkpoints,\n checkpoint_cu_starts,\n checkpoint_every_n_tokens,\n kv_tiled_mma,\n math_tidx,\n work_desc.seq_idx,\n o_head_idx,\n num_sab_heads,\n total_checkpoints,\n (blk + cutlass.Int32(1)) * cutlass.Int32(self.BLK_KV),\n work_desc.seq_len,\n )\n\n if num_blocks != cutlass.Int32(1):\n last_blk = num_blocks - cutlass.Int32(1)\n last_B = work_desc.seq_len - last_blk * cutlass.Int32(self.BLK_KV)\n (\n q_consumer_state,\n k_consumer_state,\n v_consumer_state,\n o_producer_state,\n qk_consumer_state,\n kk_consumer_state,\n alpha_consumer_state,\n ) = self.compute_loop_body(\n sQ_SD,\n sK_SD,\n sK_DS,\n sV_DS,\n sQK,\n sKK_inv,\n sKK_opd,\n sO,\n sAlpha,\n kv_tiled_mma,\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n v_pipeline,\n v_consumer_state,\n o_pipeline,\n o_producer_state,\n qk_pipeline,\n qk_consumer_state,\n kk_pipeline,\n kk_consumer_state,\n alpha_pipeline,\n alpha_consumer_state,\n False,\n True,\n last_B,\n tKVrKV,\n scale,\n wg_idx,\n )\n self.maybe_store_checkpoint(\n tKVrKV,\n g_state_checkpoints,\n checkpoint_cu_starts,\n checkpoint_every_n_tokens,\n kv_tiled_mma,\n math_tidx,\n work_desc.seq_idx,\n o_head_idx,\n num_sab_heads,\n total_checkpoints,\n (last_blk + cutlass.Int32(1)) * cutlass.Int32(self.BLK_KV),\n work_desc.seq_len,\n )\n self.kv_store(tKVrKV, gStateKV, kv_tiled_mma, math_tidx)\n\n @cute.jit\n def run_aux_loop_body(\n self,\n sQK: cute.Tensor,\n sKK_inv: cute.Tensor,\n sKK_opd: cute.Tensor,\n sAlpha: cute.Tensor,\n sBeta: cute.Tensor,\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n qk_pipeline,\n qk_producer_state,\n kk_pipeline,\n kk_producer_state,\n alpha_pipeline,\n alpha_consumer_state,\n beta_pipeline,\n beta_consumer_state,\n work_desc: WorkDesc,\n scale: cutlass.Float32,\n blk: cutlass.Int32,\n is_final_block: bool,\n qk_tiled_mma,\n kk_tiled_mma,\n tQKrQ: cute.Tensor,\n tQKrK: cute.Tensor,\n tKKrA: cute.Tensor,\n tKKrB: cute.Tensor,\n tQKcMqk: cute.Tensor,\n tKKcMkk: cute.Tensor,\n aux_tidx: cutlass.Int32,\n ):\n B = cutlass.Int32(self.BLK_KV)\n if cutlass.const_expr(is_final_block):\n B = work_desc.seq_len - blk * cutlass.Int32(self.BLK_KV)\n\n k_pipeline.consumer_wait(k_consumer_state)\n\n tKKrKK = kk_tiled_mma.get_slice(aux_tidx).make_fragment_C(\n kk_tiled_mma.get_slice(aux_tidx).partition_shape_C(\n (self.BLK_KV, self.BLK_KV)\n )\n )\n cute.nvgpu.warpgroup.fence()\n SM90.wgmma_gemm_zero_acc(\n kk_tiled_mma,\n tKKrKK,\n tKKrA[None, None, None, k_consumer_state.index],\n tKKrB[None, None, None, k_consumer_state.index],\n )\n cute.nvgpu.warpgroup.commit_group()\n\n q_pipeline.consumer_wait(q_consumer_state)\n tQKrQK = qk_tiled_mma.get_slice(aux_tidx).make_fragment_C(\n qk_tiled_mma.get_slice(aux_tidx).partition_shape_C(\n (self.BLK_Q, self.BLK_KV)\n )\n )\n cute.nvgpu.warpgroup.fence()\n SM90.wgmma_gemm_zero_acc(\n qk_tiled_mma,\n tQKrQK,\n tQKrQ[None, None, None, q_consumer_state.index],\n tQKrK[None, None, None, k_consumer_state.index],\n )\n cute.nvgpu.warpgroup.commit_group()\n cute.nvgpu.warpgroup.wait_group(0)\n\n k_pipeline.consumer_release(k_consumer_state)\n k_consumer_state.advance()\n q_pipeline.consumer_release(q_consumer_state)\n q_consumer_state.advance()\n\n if cutlass.const_expr(self.needs_alpha):\n alpha_pipeline.consumer_wait(alpha_consumer_state)\n if cutlass.const_expr(self.needs_beta):\n beta_pipeline.consumer_wait(beta_consumer_state)\n cute.arch.fence_view_async_shared()\n\n self.qk_and_kk_epi(\n tQKrQK,\n tKKrKK,\n tQKcMqk,\n tKKcMkk,\n sAlpha,\n sBeta,\n alpha_consumer_state.index,\n beta_consumer_state.index,\n is_final_block,\n B,\n scale,\n )\n\n kk_pipeline.producer_acquire(kk_producer_state)\n self._kk_store_and_inv(\n tKKrKK,\n kk_tiled_mma,\n aux_tidx,\n sKK_inv[None, None, kk_producer_state.index],\n sKK_opd[None, None, kk_producer_state.index],\n sBeta,\n beta_consumer_state.index,\n tKKcMkk,\n )\n cute.arch.fence_view_async_shared()\n kk_pipeline.producer_commit(kk_producer_state)\n kk_producer_state.advance()\n\n qk_pipeline.producer_acquire(qk_producer_state)\n self.qk_store(\n tQKrQK,\n sQK[None, None, qk_producer_state.index],\n qk_tiled_mma,\n aux_tidx,\n )\n cute.arch.fence_view_async_shared()\n qk_pipeline.producer_commit(qk_producer_state)\n qk_producer_state.advance()\n\n if cutlass.const_expr(self.needs_alpha):\n alpha_pipeline.consumer_release(alpha_consumer_state)\n alpha_consumer_state.advance()\n if cutlass.const_expr(self.needs_beta):\n beta_pipeline.consumer_release(beta_consumer_state)\n beta_consumer_state.advance()\n\n return (\n q_consumer_state,\n k_consumer_state,\n qk_producer_state,\n kk_producer_state,\n alpha_consumer_state,\n beta_consumer_state,\n )\n\n @cute.jit\n def run_aux_math_role(\n self,\n sQ_SD: cute.Tensor,\n sK_SD: cute.Tensor,\n sQK: cute.Tensor,\n sKK_inv: cute.Tensor,\n sKK_opd: cute.Tensor,\n sAlpha: cute.Tensor,\n sBeta: cute.Tensor,\n q_pipeline,\n k_pipeline,\n qk_pipeline,\n kk_pipeline,\n alpha_pipeline,\n beta_pipeline,\n work_desc: WorkDesc,\n scale: cutlass.Float32,\n math_tidx: cutlass.Int32,\n num_blocks: cutlass.Int32,\n ):\n aux_tidx = math_tidx % cutlass.Int32(128)\n\n qk_tiled_mma = cute.make_tiled_mma(\n cute.make_mma_atom(\n warpgroup.MmaF16BF16Op(\n self.dtype,\n self.acc_dtype,\n (self.BLK_Q, self.BLK_KV, 16),\n warpgroup.OperandSource.SMEM,\n cute.nvgpu.OperandMajorMode.K,\n cute.nvgpu.OperandMajorMode.K,\n )\n ),\n cute.make_layout((1, 1, 1)),\n )\n kk_tiled_mma = cute.make_tiled_mma(\n cute.make_mma_atom(\n warpgroup.MmaF16BF16Op(\n self.dtype,\n self.acc_dtype,\n (self.BLK_KV, self.BLK_KV, 16),\n warpgroup.OperandSource.SMEM,\n cute.nvgpu.OperandMajorMode.K,\n cute.nvgpu.OperandMajorMode.K,\n )\n ),\n cute.make_layout((1, 1, 1)),\n )\n\n qk_thr_mma = qk_tiled_mma.get_slice(aux_tidx)\n kk_thr_mma = kk_tiled_mma.get_slice(aux_tidx)\n\n tQKsQ = qk_thr_mma.partition_A(sQ_SD)\n tQKsK = qk_thr_mma.partition_B(sK_SD)\n tQKrQ = qk_thr_mma.make_fragment_A(tQKsQ)\n tQKrK = qk_thr_mma.make_fragment_B(tQKsK)\n\n tKKsA = kk_thr_mma.partition_A(sK_SD)\n tKKsB = kk_thr_mma.partition_B(sK_SD)\n tKKrA = kk_thr_mma.make_fragment_A(tKKsA)\n tKKrB = kk_thr_mma.make_fragment_B(tKKsB)\n\n cMqk = cute.make_identity_tensor((self.BLK_Q, self.BLK_KV))\n tQKcMqk = qk_thr_mma.partition_C(cMqk)\n tKKcMkk = kk_thr_mma.partition_C(cMqk)\n\n q_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.q_stage\n )\n k_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.k_stage\n )\n qk_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.qk_stage\n )\n kk_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.kk_stage\n )\n alpha_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.alpha_beta_stage\n )\n beta_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.alpha_beta_stage\n )\n\n for blk in cutlass.range(num_blocks - cutlass.Int32(1), unroll=1):\n (\n q_consumer_state,\n k_consumer_state,\n qk_producer_state,\n kk_producer_state,\n alpha_consumer_state,\n beta_consumer_state,\n ) = self.run_aux_loop_body(\n sQK,\n sKK_inv,\n sKK_opd,\n sAlpha,\n sBeta,\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n qk_pipeline,\n qk_producer_state,\n kk_pipeline,\n kk_producer_state,\n alpha_pipeline,\n alpha_consumer_state,\n beta_pipeline,\n beta_consumer_state,\n work_desc,\n scale,\n blk,\n False,\n qk_tiled_mma,\n kk_tiled_mma,\n tQKrQ,\n tQKrK,\n tKKrA,\n tKKrB,\n tQKcMqk,\n tKKcMkk,\n aux_tidx,\n )\n\n last_blk = num_blocks - cutlass.Int32(1)\n (\n q_consumer_state,\n k_consumer_state,\n qk_producer_state,\n kk_producer_state,\n alpha_consumer_state,\n beta_consumer_state,\n ) = self.run_aux_loop_body(\n sQK,\n sKK_inv,\n sKK_opd,\n sAlpha,\n sBeta,\n q_pipeline,\n q_consumer_state,\n k_pipeline,\n k_consumer_state,\n qk_pipeline,\n qk_producer_state,\n kk_pipeline,\n kk_producer_state,\n alpha_pipeline,\n alpha_consumer_state,\n beta_pipeline,\n beta_consumer_state,\n work_desc,\n scale,\n last_blk,\n True,\n qk_tiled_mma,\n kk_tiled_mma,\n tQKrQ,\n tQKrK,\n tKKrA,\n tKKrB,\n tQKcMqk,\n tKKcMkk,\n aux_tidx,\n )\n\n # ─── Kernel entry point ───────────────────────────────────────────────────\n\n @cute.jit\n def __call__(\n self,\n g_q: cute.Tensor,\n g_k: cute.Tensor,\n g_v: cute.Tensor,\n g_o: cute.Tensor,\n g_alpha: cute.Tensor,\n g_beta: cute.Tensor,\n g_state: cute.Tensor,\n g_init_state: cute.Tensor,\n g_state_indices: cute.Tensor,\n g_state_checkpoints: cute.Tensor,\n checkpoint_cu_starts: cute.Tensor,\n g_tensormaps: cute.Tensor,\n cu_seqlens: cute.Tensor,\n scale: cutlass.Float32,\n num_q_heads: cutlass.Int32,\n num_k_heads: cutlass.Int32,\n num_v_heads: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n num_seqs: cutlass.Int32,\n total_checkpoints: cutlass.Int32,\n checkpoint_every_n_tokens: cutlass.Int32,\n grid_x: int,\n stream,\n ):\n qkv_smem_layout_atom = warpgroup.make_smem_layout_atom(\n warpgroup.SmemLayoutAtomKind.K_SW128,\n self.dtype,\n )\n q_storage_layout = cute.coalesce(\n cute.tile_to_shape(\n qkv_smem_layout_atom,\n (self.BLK_Q, self.D, self.q_stage),\n order=(0, 1, 2),\n ),\n target_profile=(1, 1, 1),\n )\n q_smem_layout = cute.slice_(q_storage_layout, (None, None, 0))\n k_storage_layout_sd = cute.coalesce(\n cute.tile_to_shape(\n qkv_smem_layout_atom,\n (self.BLK_KV, self.D, self.k_stage),\n order=(0, 1, 2),\n ),\n target_profile=(1, 1, 1),\n )\n k_storage_layout_ds = cute.select(k_storage_layout_sd, [1, 0, 2])\n v_storage_layout_sd = cute.coalesce(\n cute.tile_to_shape(\n qkv_smem_layout_atom,\n (self.BLK_KV, self.D, self.v_stage),\n order=(0, 1, 2),\n ),\n target_profile=(1, 1, 1),\n )\n v_storage_layout_ds = cute.select(v_storage_layout_sd, [1, 0, 2])\n k_smem_layout = cute.slice_(k_storage_layout_ds, (None, None, 0))\n v_smem_layout = cute.slice_(v_storage_layout_ds, (None, None, 0))\n o_smem_layout_atom = warpgroup.make_smem_layout_atom(\n warpgroup.SmemLayoutAtomKind.MN_SW32,\n self.dtype,\n )\n o_storage_layout = cute.tile_to_shape(\n o_smem_layout_atom,\n (self.D, self.BLK_Q, self.o_stage),\n order=(1, 0, 2),\n )\n o_smem_layout = cute.slice_(o_storage_layout, (None, None, 0))\n\n tma_load_op = cpasync.CopyBulkTensorTileG2SOp()\n tma_atom_q, tma_tensor_q = cpasync.make_tiled_tma_atom(\n tma_load_op, g_q, q_smem_layout, (self.BLK_Q, self.D)\n )\n tma_atom_k, tma_tensor_k = cpasync.make_tiled_tma_atom(\n tma_load_op, g_k, k_smem_layout, (self.D, self.BLK_KV)\n )\n tma_atom_v, tma_tensor_v = cpasync.make_tiled_tma_atom(\n tma_load_op, g_v, v_smem_layout, (self.D, self.BLK_KV)\n )\n\n tma_store_op = cpasync.CopyBulkTensorTileS2GOp()\n tma_atom_o, tma_tensor_o = cpasync.make_tiled_tma_atom(\n tma_store_op, g_o, o_smem_layout, (self.D, self.BLK_Q)\n )\n\n dtype_bytes = self.dtype.width // 8\n self.tma_load_q_bytes = cute.size(q_smem_layout) * dtype_bytes\n self.tma_load_k_bytes = cute.size(k_smem_layout) * dtype_bytes\n self.tma_load_v_bytes = cute.size(v_smem_layout) * dtype_bytes\n\n qk_layout_atom = cute.make_layout((8, 8), stride=(8, 1))\n qk_storage_layout = cute.tile_to_shape(\n qk_layout_atom, (self.BLK_Q, self.BLK_KV, self.qk_stage), order=(0, 1, 2)\n )\n kk_storage_layout = cute.tile_to_shape(\n qk_layout_atom, (self.BLK_KV, self.BLK_KV, self.kk_stage), order=(0, 1, 2)\n )\n alpha_storage_layout = cute.make_layout(\n (self.BLK_Q, AlphaProcessor.NUM_CHANNELS, self.alpha_beta_stage)\n )\n beta_storage_layout = cute.make_layout((self.BLK_KV, self.alpha_beta_stage))\n\n @cute.struct\n class SharedStorage:\n q_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.q_stage * 2]\n k_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.k_stage * 2]\n v_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.v_stage * 2]\n o_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.o_stage * 2]\n qk_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.qk_stage * 2]\n kk_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.kk_stage * 2]\n alpha_mbar_ptr: cute.struct.MemRange[\n cutlass.Int64, self.alpha_beta_stage * 2\n ]\n beta_mbar_ptr: cute.struct.MemRange[\n cutlass.Int64, self.alpha_beta_stage * 2\n ]\n\n smem_q: cute.struct.Align[\n cute.struct.MemRange[self.dtype, cute.cosize(q_storage_layout)],\n 128,\n ]\n smem_k: cute.struct.Align[\n cute.struct.MemRange[self.dtype, cute.cosize(k_storage_layout_sd)],\n 128,\n ]\n smem_v: cute.struct.Align[\n cute.struct.MemRange[self.dtype, cute.cosize(v_storage_layout_sd)],\n 128,\n ]\n smem_qk: cute.struct.Align[\n cute.struct.MemRange[self.dtype, cute.cosize(qk_storage_layout)],\n 16,\n ]\n smem_kk: cute.struct.Align[\n cute.struct.MemRange[\n self.inverse_dtype, cute.cosize(kk_storage_layout)\n ],\n 16,\n ]\n smem_o: cute.struct.Align[\n cute.struct.MemRange[self.dtype, cute.cosize(o_storage_layout)],\n 128,\n ]\n smem_alpha: cute.struct.Align[\n cute.struct.MemRange[\n cutlass.Float32, cute.cosize(alpha_storage_layout)\n ],\n 16,\n ]\n smem_beta: cute.struct.Align[\n cute.struct.MemRange[cutlass.Float32, cute.cosize(beta_storage_layout)],\n 16,\n ]\n\n self.shared_storage = SharedStorage\n\n self.kernel(\n g_alpha,\n g_beta,\n tma_atom_q,\n tma_tensor_q,\n tma_atom_k,\n tma_tensor_k,\n tma_atom_v,\n tma_tensor_v,\n tma_atom_o,\n tma_tensor_o,\n g_state,\n g_init_state,\n g_state_indices,\n g_state_checkpoints,\n checkpoint_cu_starts,\n g_tensormaps,\n cu_seqlens,\n scale,\n num_q_heads,\n num_k_heads,\n num_v_heads,\n num_sab_heads,\n num_seqs,\n total_checkpoints,\n checkpoint_every_n_tokens,\n ).launch(\n grid=(grid_x, 1, 1),\n block=(512, 1, 1),\n max_number_threads=(512, 1, 1),\n stream=stream,\n min_blocks_per_mp=1,\n )\n\n @cute.kernel\n def kernel(\n self,\n g_alpha: cute.Tensor,\n g_beta: cute.Tensor,\n tma_atom_q: cute.CopyAtom,\n tma_tensor_q: cute.Tensor,\n tma_atom_k: cute.CopyAtom,\n tma_tensor_k: cute.Tensor,\n tma_atom_v: cute.CopyAtom,\n tma_tensor_v: cute.Tensor,\n tma_atom_o: cute.CopyAtom,\n tma_tensor_o: cute.Tensor,\n g_state: cute.Tensor,\n g_init_state: cute.Tensor,\n g_state_indices: cute.Tensor,\n g_state_checkpoints: cute.Tensor,\n checkpoint_cu_starts: cute.Tensor,\n g_tensormaps: cute.Tensor,\n cu_seqlens: cute.Tensor,\n scale: cutlass.Float32,\n num_q_heads: cutlass.Int32,\n num_k_heads: cutlass.Int32,\n num_v_heads: cutlass.Int32,\n num_sab_heads: cutlass.Int32,\n num_seqs: cutlass.Int32,\n total_checkpoints: cutlass.Int32,\n checkpoint_every_n_tokens: cutlass.Int32,\n ):\n NUM_LOAD_WARP_GROUPS = 1\n NUM_STATE_MMA_WARP_GROUPS = 2\n NUM_AUX_MMA_WARP_GROUPS = 1\n THREADS_PER_WARP_GROUP = 128\n WARPS_PER_WARP_GROUP = 4\n MIN_BLOCKS_PER_MP = 1\n MAX_THREADS_PER_BLOCK = (\n NUM_LOAD_WARP_GROUPS + NUM_STATE_MMA_WARP_GROUPS + NUM_AUX_MMA_WARP_GROUPS\n ) * THREADS_PER_WARP_GROUP\n (\n load_registers,\n state_mma_registers,\n aux_mma_registers,\n ) = self.get_register_requirements(\n MAX_THREADS_PER_BLOCK,\n MIN_BLOCKS_PER_MP,\n NUM_STATE_MMA_WARP_GROUPS,\n THREADS_PER_WARP_GROUP,\n )\n\n tidx, _, _ = cute.arch.thread_idx()\n warp_idx = cute.arch.make_warp_uniform(cute.arch.warp_idx())\n warp_group_idx = cute.arch.make_warp_uniform(\n tidx // cutlass.Int32(THREADS_PER_WARP_GROUP)\n )\n ldst_warp_role = cute.arch.make_warp_uniform(\n warp_idx % cutlass.Int32(WARPS_PER_WARP_GROUP)\n )\n\n if warp_idx == LoadStoreWarpRole.LOAD_QKV:\n cpasync.prefetch_descriptor(tma_atom_q)\n cpasync.prefetch_descriptor(tma_atom_k)\n cpasync.prefetch_descriptor(tma_atom_v)\n cpasync.prefetch_descriptor(tma_atom_o)\n\n work_desc = self.get_next_work(\n cu_seqlens,\n num_q_heads,\n num_v_heads,\n num_sab_heads,\n )\n tok_end = work_desc.tok_offset + work_desc.seq_len\n num_blocks = (\n work_desc.seq_len + cutlass.Int32(self.BLK_KV) - cutlass.Int32(1)\n ) // cutlass.Int32(self.BLK_KV)\n\n # math_tidx / wg_idx: valid for Math WG threads; LdSt WG gets negative values (unused)\n math_tidx = tidx - cutlass.Int32(THREADS_PER_WARP_GROUP)\n wg_idx = math_tidx // cutlass.Int32(THREADS_PER_WARP_GROUP)\n\n # ── Smem allocation ───────────────────────────────────────────────────\n allocator = cutlass.utils.SmemAllocator()\n storage = allocator.allocate(self.shared_storage)\n\n qkv_smem_layout_atom = warpgroup.make_smem_layout_atom(\n warpgroup.SmemLayoutAtomKind.K_SW128,\n self.dtype,\n )\n q_layout_sd = cute.coalesce(\n cute.tile_to_shape(\n qkv_smem_layout_atom,\n (self.BLK_Q, self.D, self.q_stage),\n order=(0, 1, 2),\n ),\n target_profile=(1, 1, 1),\n )\n sQ_SD = storage.smem_q.get_tensor(q_layout_sd.outer, swizzle=q_layout_sd.inner)\n\n k_layout_sd = cute.coalesce(\n cute.tile_to_shape(\n qkv_smem_layout_atom,\n (self.BLK_KV, self.D, self.k_stage),\n order=(0, 1, 2),\n ),\n target_profile=(1, 1, 1),\n )\n k_layout_ds = cute.select(k_layout_sd, [1, 0, 2])\n sK_SD = storage.smem_k.get_tensor(k_layout_sd.outer, swizzle=k_layout_sd.inner)\n sK_DS = storage.smem_k.get_tensor(k_layout_ds.outer, swizzle=k_layout_ds.inner)\n\n v_layout_sd = cute.coalesce(\n cute.tile_to_shape(\n qkv_smem_layout_atom,\n (self.BLK_KV, self.D, self.v_stage),\n order=(0, 1, 2),\n ),\n target_profile=(1, 1, 1),\n )\n v_layout_ds = cute.select(v_layout_sd, [1, 0, 2])\n sV_DS = storage.smem_v.get_tensor(v_layout_ds.outer, swizzle=v_layout_ds.inner)\n\n qk_layout_atom = cute.make_layout((8, 8), stride=(8, 1))\n qk_layout = cute.tile_to_shape(\n qk_layout_atom, (self.BLK_Q, self.BLK_KV, self.qk_stage), order=(0, 1, 2)\n )\n sQK = storage.smem_qk.get_tensor(qk_layout)\n\n kk_layout = cute.tile_to_shape(\n qk_layout_atom, (self.BLK_KV, self.BLK_KV, self.kk_stage), order=(0, 1, 2)\n )\n sKK_inv = storage.smem_kk.get_tensor(kk_layout)\n kk_opd_ptr = cute.recast_ptr(storage.smem_kk.data_ptr(), dtype=self.dtype)\n sKK_opd = cute.make_tensor(kk_opd_ptr, kk_layout)\n\n o_smem_layout_atom = warpgroup.make_smem_layout_atom(\n warpgroup.SmemLayoutAtomKind.MN_SW32,\n self.dtype,\n )\n o_layout = cute.tile_to_shape(\n o_smem_layout_atom,\n (self.D, self.BLK_Q, self.o_stage),\n order=(1, 0, 2),\n )\n sO = storage.smem_o.get_tensor(o_layout.outer, swizzle=o_layout.inner)\n alpha_layout = cute.make_layout(\n (self.BLK_Q, AlphaProcessor.NUM_CHANNELS, self.alpha_beta_stage)\n )\n sAlpha = storage.smem_alpha.get_tensor(alpha_layout)\n\n beta_layout = cute.make_layout((self.BLK_KV, self.alpha_beta_stage))\n sBeta = storage.smem_beta.get_tensor(beta_layout)\n\n load_producer_group = pipeline.CooperativeGroup(pipeline.Agent.Thread, 1)\n # PipelineTmaAsync release is signalled by one lane per consumer warp.\n qk_load_consumer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n (NUM_STATE_MMA_WARP_GROUPS + NUM_AUX_MMA_WARP_GROUPS)\n * WARPS_PER_WARP_GROUP,\n )\n v_consumer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n NUM_STATE_MMA_WARP_GROUPS * WARPS_PER_WARP_GROUP,\n )\n vector_producer_group = pipeline.CooperativeGroup(pipeline.Agent.Thread, 32)\n alpha_consumer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n (NUM_AUX_MMA_WARP_GROUPS + NUM_STATE_MMA_WARP_GROUPS)\n * THREADS_PER_WARP_GROUP,\n )\n beta_consumer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread, NUM_AUX_MMA_WARP_GROUPS * THREADS_PER_WARP_GROUP\n )\n o_producer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread, NUM_STATE_MMA_WARP_GROUPS * THREADS_PER_WARP_GROUP\n )\n o_consumer_group = pipeline.CooperativeGroup(pipeline.Agent.Thread, 32)\n q_pipeline = pipeline.PipelineTmaAsync.create(\n barrier_storage=storage.q_mbar_ptr.data_ptr(),\n num_stages=self.q_stage,\n producer_group=load_producer_group,\n consumer_group=qk_load_consumer_group,\n tx_count=self.tma_load_q_bytes,\n cta_layout_vmnk=cute.make_layout((1, 1, 1, 1)),\n )\n k_pipeline = pipeline.PipelineTmaAsync.create(\n barrier_storage=storage.k_mbar_ptr.data_ptr(),\n num_stages=self.k_stage,\n producer_group=load_producer_group,\n consumer_group=qk_load_consumer_group,\n tx_count=self.tma_load_k_bytes,\n cta_layout_vmnk=cute.make_layout((1, 1, 1, 1)),\n )\n v_pipeline = pipeline.PipelineTmaAsync.create(\n barrier_storage=storage.v_mbar_ptr.data_ptr(),\n num_stages=self.v_stage,\n producer_group=load_producer_group,\n consumer_group=v_consumer_group,\n tx_count=self.tma_load_v_bytes,\n cta_layout_vmnk=cute.make_layout((1, 1, 1, 1)),\n )\n o_pipeline = pipeline.PipelineAsync.create(\n barrier_storage=storage.o_mbar_ptr.data_ptr(),\n num_stages=self.o_stage,\n producer_group=o_producer_group,\n consumer_group=o_consumer_group,\n )\n qk_pipeline = pipeline.PipelineAsync.create(\n barrier_storage=storage.qk_mbar_ptr.data_ptr(),\n num_stages=self.qk_stage,\n producer_group=pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n NUM_AUX_MMA_WARP_GROUPS * THREADS_PER_WARP_GROUP,\n ),\n consumer_group=pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n NUM_STATE_MMA_WARP_GROUPS * THREADS_PER_WARP_GROUP,\n ),\n )\n kk_pipeline = pipeline.PipelineAsync.create(\n barrier_storage=storage.kk_mbar_ptr.data_ptr(),\n num_stages=self.kk_stage,\n producer_group=pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n NUM_AUX_MMA_WARP_GROUPS * THREADS_PER_WARP_GROUP,\n ),\n consumer_group=pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n NUM_STATE_MMA_WARP_GROUPS * THREADS_PER_WARP_GROUP,\n ),\n )\n alpha_pipeline = pipeline.PipelineAsync.create(\n barrier_storage=storage.alpha_mbar_ptr.data_ptr(),\n num_stages=self.alpha_beta_stage,\n producer_group=vector_producer_group,\n consumer_group=alpha_consumer_group,\n )\n beta_pipeline = pipeline.PipelineAsync.create(\n barrier_storage=storage.beta_mbar_ptr.data_ptr(),\n num_stages=self.alpha_beta_stage,\n producer_group=vector_producer_group,\n consumer_group=beta_consumer_group,\n )\n cute.arch.mbarrier_init_fence()\n cute.arch.sync_threads()\n\n if (\n work_desc.seq_len != cutlass.Int32(0)\n and warp_group_idx == WarpGroupRole.LDST\n ):\n cute.arch.setmaxregister_decrease(load_registers)\n if ldst_warp_role == LoadStoreWarpRole.LOAD_QKV:\n self.run_load_qkv_role(\n sQ_SD,\n sK_DS,\n sV_DS,\n tma_atom_q,\n tma_tensor_q,\n tma_atom_k,\n tma_tensor_k,\n tma_atom_v,\n tma_tensor_v,\n q_pipeline,\n k_pipeline,\n v_pipeline,\n num_blocks,\n work_desc.tok_offset,\n work_desc.q_head_idx(),\n work_desc.k_head_idx(num_q_heads, num_v_heads),\n work_desc.v_head_idx(),\n )\n elif ldst_warp_role == LoadStoreWarpRole.STORE_O:\n CollectiveStoreTma(self.BLK_Q, self.D).run(\n sO,\n tma_atom_o,\n tma_tensor_o,\n g_tensormaps,\n o_pipeline,\n num_blocks,\n work_desc,\n num_seqs,\n self.o_stage,\n num_q_heads,\n num_v_heads,\n )\n elif ldst_warp_role == LoadStoreWarpRole.LOAD_BETA:\n self.run_load_beta_role(\n sBeta,\n g_beta,\n beta_pipeline,\n num_blocks,\n work_desc.tok_offset,\n tok_end,\n work_desc.o_head_idx(num_q_heads, num_v_heads),\n num_sab_heads,\n )\n elif ldst_warp_role == LoadStoreWarpRole.LOAD_ALPHA:\n self.run_load_alpha_role(\n sAlpha,\n g_alpha,\n alpha_pipeline,\n scale,\n num_blocks,\n work_desc.tok_offset,\n tok_end,\n work_desc.o_head_idx(num_q_heads, num_v_heads),\n num_sab_heads,\n )\n elif work_desc.seq_len != cutlass.Int32(0):\n if warp_group_idx == WarpGroupRole.MATH_AUX:\n cute.arch.setmaxregister_decrease(aux_mma_registers)\n self.run_aux_math_role(\n sQ_SD,\n sK_SD,\n sQK,\n sKK_inv,\n sKK_opd,\n sAlpha,\n sBeta,\n q_pipeline,\n k_pipeline,\n qk_pipeline,\n kk_pipeline,\n alpha_pipeline,\n beta_pipeline,\n work_desc,\n scale,\n math_tidx,\n num_blocks,\n )\n else:\n cute.arch.setmaxregister_increase(state_mma_registers)\n self.run_state_math_role(\n sQ_SD,\n sK_SD,\n sK_DS,\n sV_DS,\n sQK,\n sKK_inv,\n sKK_opd,\n sO,\n sAlpha,\n q_pipeline,\n k_pipeline,\n v_pipeline,\n o_pipeline,\n qk_pipeline,\n kk_pipeline,\n alpha_pipeline,\n g_state,\n g_init_state,\n g_state_indices,\n g_state_checkpoints,\n checkpoint_cu_starts,\n work_desc,\n scale,\n wg_idx,\n math_tidx,\n num_blocks,\n num_q_heads,\n num_v_heads,\n num_sab_heads,\n num_seqs,\n total_checkpoints,\n checkpoint_every_n_tokens,\n )\n\n\n# ─── Public API ──────────────────────────────────────────────────────────────\n\n\ndef delta_rule_prefill_dsl_sm90(\n o: torch.Tensor, # (total_seqlen, num_o_heads, D) fp16/bf16, output\n state: torch.Tensor, # (num_seqs, num_sab_heads, D, D) fp32, output\n q: torch.Tensor, # (total_seqlen, num_q_heads, D)\n k: torch.Tensor, # (total_seqlen, num_k_heads, D)\n v: torch.Tensor, # (total_seqlen, num_v_heads, D)\n init_state: torch.Tensor | None, # (num_seqs, num_sab_heads, D, D) fp32, optional\n alpha: torch.Tensor | None,\n beta: torch.Tensor | None,\n cu_seqlens: torch.Tensor, # (num_seqs+1,) int64\n scale: float,\n state_checkpoints: torch.Tensor | None = None,\n checkpoint_cu_starts: torch.Tensor | None = None,\n checkpoint_every_n_tokens: int = 0,\n state_indices: torch.Tensor | None = None,\n):\n from cutlass.cute.runtime import from_dlpack\n import cuda.bindings.driver as cuda_driver\n\n D = q.shape[-1]\n\n num_seqs = cu_seqlens.shape[0] - 1\n num_q_heads = q.shape[1]\n num_k_heads = k.shape[1]\n num_v_heads = v.shape[1]\n num_sab_heads = max(num_q_heads, num_v_heads)\n\n if not _FullyFusedDeltaRuleSm90.can_implement(\n num_q_heads, num_k_heads, num_v_heads, D, q.element_size()\n ):\n raise RuntimeError(\"can_implement failed\")\n if D != 128:\n raise RuntimeError(f\"DSL kernel only supports D=128, got {D}\")\n\n needs_alpha = alpha is not None\n needs_beta = beta is not None\n needs_init_state = init_state is not None\n needs_checkpointing = checkpoint_every_n_tokens > 0\n use_state_indices = state_indices is not None\n kernel_dtype = {\n torch.float16: cutlass.Float16,\n torch.bfloat16: cutlass.BFloat16,\n }.get(q.dtype)\n if kernel_dtype is None:\n raise RuntimeError(f\"DSL kernel only supports fp16/bf16 inputs, got {q.dtype}\")\n\n if k.dtype != q.dtype or v.dtype != q.dtype or o.dtype != q.dtype:\n raise RuntimeError(\n f\"q/k/v/o dtypes must match, got {q.dtype}, {k.dtype}, {v.dtype}, {o.dtype}\"\n )\n if alpha is not None and alpha.dtype != torch.float32:\n raise RuntimeError(f\"alpha must have dtype torch.float32, got {alpha.dtype}\")\n if beta is not None and beta.dtype != torch.float32:\n raise RuntimeError(f\"beta must have dtype torch.float32, got {beta.dtype}\")\n if init_state is not None:\n state_dtype_to_cutlass(init_state.dtype)\n state_dtype_to_cutlass(state.dtype)\n if state_checkpoints is not None:\n state_dtype_to_cutlass(state_checkpoints.dtype)\n if not is_integer_dtype(cu_seqlens.dtype):\n raise RuntimeError(\n f\"cu_seqlens must have an integer dtype, got {cu_seqlens.dtype}\"\n )\n\n expected_state_tail = (num_sab_heads, D, D)\n for name, tensor in ((\"state\", state), (\"init_state\", init_state)):\n if tensor is None:\n continue\n if (\n not use_state_indices and tensor.shape != (num_seqs, *expected_state_tail)\n ) or (use_state_indices and tuple(tensor.shape[1:]) != expected_state_tail):\n raise RuntimeError(\n f\"{name} must have shape \"\n f\"{('[N_pool]' if use_state_indices else f'[{num_seqs}]')} + {expected_state_tail}, \"\n f\"got {tuple(tensor.shape)}\"\n )\n if use_state_indices and (\n not is_integer_dtype(state_indices.dtype) or state_indices.shape != (num_seqs,)\n ):\n raise RuntimeError(\n f\"state_indices must have shape {(num_seqs,)} and an integer dtype\"\n )\n\n for name, tensor in (\n (\"q\", q),\n (\"k\", k),\n (\"v\", v),\n (\"o\", o),\n (\"cu_seqlens\", cu_seqlens),\n ):\n if not tensor.is_contiguous():\n raise RuntimeError(f\"{name} must be contiguous\")\n for name, tensor in (\n (\"alpha\", alpha),\n (\"beta\", beta),\n (\"state_indices\", state_indices),\n ):\n if tensor is not None and not tensor.is_contiguous():\n raise RuntimeError(f\"{name} must be contiguous\")\n for name, tensor in ((\"state\", state), (\"init_state\", init_state)):\n if tensor is None:\n continue\n if not use_state_indices and not tensor.is_contiguous():\n raise RuntimeError(f\"{name} must be contiguous\")\n\n total_seqlen = q.shape[0]\n num_o_heads = o.shape[1]\n q_tma = q.as_strided(\n (total_seqlen, D, num_q_heads),\n (num_q_heads * D, 1, D),\n )\n k_tma = k.as_strided(\n (D, total_seqlen, num_k_heads),\n (1, num_k_heads * D, D),\n )\n v_tma = v.as_strided(\n (D, total_seqlen, num_v_heads),\n (1, num_v_heads * D, D),\n )\n o_tma = o.as_strided(\n (D, total_seqlen, num_o_heads),\n (1, num_o_heads * D, D),\n )\n total_checkpoints = state_checkpoints.shape[0] if needs_checkpointing else 1\n\n workspace_size = get_device_sm_count(q.device) * 128\n tensormaps_t = _get_cache_buf(\"gdn_prefill_tensormaps\", workspace_size, q.device)\n\n stream_val = torch.cuda.current_stream().cuda_stream\n stream = cuda_driver.CUstream(stream_val)\n\n enable_tvm_ffi = True\n if enable_tvm_ffi:\n from_dlpack = lambda *args, **kwargs: cute.runtime.from_dlpack(\n *args, **{**kwargs, \"enable_tvm_ffi\": True}\n )\n\n # Keep head counts and varlen extents runtime values across cached compiles.\n q_cute = from_dlpack(q_tma, assumed_align=16).mark_layout_dynamic(leading_dim=1)\n k_cute = from_dlpack(k_tma, assumed_align=16).mark_layout_dynamic(leading_dim=0)\n v_cute = from_dlpack(v_tma, assumed_align=16).mark_layout_dynamic(leading_dim=0)\n o_cute = from_dlpack(o_tma, assumed_align=16).mark_layout_dynamic(leading_dim=0)\n alpha_cute = (\n from_dlpack(alpha.reshape(-1), assumed_align=16).mark_layout_dynamic()\n if needs_alpha\n else None\n )\n beta_cute = (\n from_dlpack(beta.reshape(-1), assumed_align=16).mark_layout_dynamic()\n if needs_beta\n else None\n )\n state_cute = from_dlpack(state, assumed_align=16).mark_layout_dynamic()\n init_state_cute = (\n from_dlpack(init_state, assumed_align=16).mark_layout_dynamic()\n if needs_init_state\n else None\n )\n state_indices_cute = (\n from_dlpack(state_indices, assumed_align=4).mark_layout_dynamic()\n if use_state_indices\n else None\n )\n state_checkpoints_cute = (\n from_dlpack(\n state_checkpoints.reshape(-1), assumed_align=16\n ).mark_layout_dynamic()\n if needs_checkpointing\n else None\n )\n checkpoint_cu_cute = (\n from_dlpack(checkpoint_cu_starts, assumed_align=8).mark_layout_dynamic()\n if needs_checkpointing\n else None\n )\n tensormaps_cute = from_dlpack(tensormaps_t, assumed_align=128).mark_layout_dynamic()\n cu_cute = from_dlpack(cu_seqlens, assumed_align=8).mark_layout_dynamic()\n\n delta_rule_kernel = _FullyFusedDeltaRuleSm90(\n needs_alpha,\n needs_beta,\n needs_init_state,\n needs_checkpointing,\n kernel_dtype,\n initial_state_dtype=state_dtype_to_cutlass(\n init_state.dtype if needs_init_state else torch.float32\n ),\n state_dtype=state_dtype_to_cutlass(state.dtype),\n checkpoint_state_dtype=state_dtype_to_cutlass(\n state_checkpoints.dtype if needs_checkpointing else torch.float32\n ),\n use_state_indices=use_state_indices,\n cu_seqlens_dtype=cu_seqlens.dtype,\n state_indices_dtype=state_indices.dtype if use_state_indices else None,\n checkpoint_cu_starts_dtype=(\n checkpoint_cu_starts.dtype if needs_checkpointing else None\n ),\n state_inner_strides=(tuple(state.stride()[1:]) if use_state_indices else None),\n init_state_inner_strides=(\n tuple(init_state.stride()[1:])\n if use_state_indices and needs_init_state\n else None\n ),\n )\n\n kernel_args = (\n q_cute,\n k_cute,\n v_cute,\n o_cute,\n alpha_cute,\n beta_cute,\n state_cute,\n init_state_cute,\n state_indices_cute,\n state_checkpoints_cute,\n checkpoint_cu_cute,\n tensormaps_cute,\n cu_cute,\n cutlass.Float32(scale),\n cutlass.Int32(num_q_heads),\n cutlass.Int32(num_k_heads),\n cutlass.Int32(num_v_heads),\n cutlass.Int32(num_sab_heads),\n cutlass.Int32(num_seqs),\n cutlass.Int32(total_checkpoints),\n cutlass.Int32(checkpoint_every_n_tokens),\n num_seqs * num_sab_heads,\n stream,\n )\n compiled_delta_rule_kernel = cached_compile(\n delta_rule_kernel,\n *kernel_args,\n compile_options=(cute.GPUArch(\"sm_90a\"),),\n )\n compiled_delta_rule_kernel(*kernel_args)\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## 📌 Description\n\nCache SM90 and SM120 non-CP kernel objects and compile options, and construct CuTe tensor wrappers only during compilation. Replay compiled kernels through raw TVM-FFI arguments to remove repeated launch preparation from the eager path.\n\nfollow up of #4374 for non-CP launch path.\n\n## 🔍 Related Issues\n## 🚀 Pull Request Checklist\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc. -->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n\n## Summary by CodeRabbit\n\n* **Performance Improvements**\n * Improved prefill execution by reusing compiled device-specific kernels across calls.\n * Reduced repeated setup and conversion overhead, especially for workloads with recurring prefill operations.\n * Added optimized handling for supported SM90 and SM120 GPU architectures.\n* **Compatibility**\n * Existing public interfaces remain unchanged.\n\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1082,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"b5993208e1ff5b86330e449ef270de15033e048f"},"date":{"kind":"string","value":"2026-08-23T14:59:58-07:00"},"pr_number":{"kind":"number","value":4686,"string":"4,686"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/4686"},"title":{"kind":"string","value":"perf(gemm): optimize CuTe DSL W4A16 dense GEMM (#4686)"},"message":{"kind":"string","value":"perf(gemm): optimize CuTe DSL W4A16 dense GEMM (#4686)\n\n<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\n@humansand\n\nThis optimizes the SM100/SM103 CuTe DSL dense W4A16 `mm_bf16_fp4` path\nadded by #4466.\n\n- Compile the SM100/SM103 dense kernel at CuTe optimizer level 3 instead\nof its explicit level-2 override. SM12x compilation is unchanged.\n- Make raster direction a full autotune axis: every one of the 15\nstructural tile/cluster tactics now has both M-major and N-major\nvariants, for a 30-tactic Cartesian product.\n\nThe final review diff is limited to\n`flashinfer/gemm/gemm_bf16_fp4_cute_dsl.py`. The fail-closed CUPTI\nevidence harness is retained in commit\n[`100e9527`](https://github.com/flashinfer-ai/flashinfer/commit/100e95275d55280c110c66e9a4693b07b86ff4d4),\nwith its\n[orchestrator](https://github.com/flashinfer-ai/flashinfer/blob/100e95275d55280c110c66e9a4693b07b86ff4d4/benchmarks/bench_dense_w4a16_sm100.py)\nand\n[worker](https://github.com/flashinfer-ai/flashinfer/blob/100e95275d55280c110c66e9a4693b07b86ff4d4/benchmarks/bench_dense_w4a16_sm100_worker.py)\nintentionally absent from the final tree.\n\nThe dense kernel already retains the intended W4A16 architecture from\nthe shared MoE design: the tensor-wide FP32 weight scale is applied to\nthe FP32 accumulator in the epilogue, and the CTA uses two four-warp\ntransform groups with the full 65,536-register allocation. This PR does\nnot change those contracts, the public API, numerical ordering, warp\nspecialization, or pipeline stages.\n\n## 🔍 Related Issues\n\n- Tracked in #4561\n- Follow-up to #4466\n\n## ⏱️ Performance\n\n### Environment and workload\n\n- Image: `nvcr.io/nvidia/pytorch:26.05-py3`\n- Devbox: `c2`, namespace `infra`, host `hu-pdx-117`; 8 x NVIDIA B300\nSXM6 AC (SM103), measurements pinned to GPU 0\n- GPU 0: UUID `GPU-ee0843de-7ab2-7b46-8af4-1344b209180a`, 1100 W power\nlimit, 2032 MHz maximum SM clock\n- Driver: `590.48.01`\n- Python: `3.12.3`\n- PyTorch: `2.12.0a0+5aff3928d8.nv26.05`\n- PyTorch CUDA / system nvcc: `13.2` / `13.2.78`\n- FlashInfer Python: `0.6.18` (editable checkout)\n- `nvidia-cutlass-dsl`: `4.7.0`\n- `cupti-python`: `13.2.0`; `nvidia-cuda-cupti`: `13.2.86`;\n`cuda-bindings`: `13.2.0`\n- Baseline: `fb28d7242b3506a2348265962041acc1fb56cca4`\n- Benchmarked candidate: `100e95275d55280c110c66e9a4693b07b86ff4d4`;\nbenchmarked `flashinfer/gemm/gemm_bf16_fp4_cute_dsl.py` SHA-256\n`befff9328ff028e7ca44603b39c35036a2d673ef982791ab0bd1cb714d0f4355`\n- Minimal review head: `693d10862df7a793f7dd9d500ddece28d536d9a0`; final\n`flashinfer/gemm/gemm_bf16_fp4_cute_dsl.py` SHA-256\n`af8c20a81e472f4c30bb57d0f6f022f61452200079712bf5c3f82a2491141306`. The\ncleanup removes redundant Python constants/cache metadata and\nbenchmark-only tree changes; it preserves O3 and the exact fresh-cache\n30-tactic order.\n- Shapes: `(N,K)=(6656,19968)` and `(19968,6656)`, with\n`M=1,8,32,128,512,1024,2048,4096`\n\nThe first C1 B200 devbox was reclaimed during bring-up, and subsequent\nC1 requests could not get capacity. All retained measurements below are\ntherefore from one C2 B300/SM103 GPU; the discarded C1 bring-up number\nis not mixed into the table.\n\n### Method\n\n- Same-node `A1 upstream O2 -> B candidate O3 + 30 raster tactics -> A2\nupstream O2`, with the exact benchmarked candidate source between the\ntwo adjacent baseline arms.\n- Every shape and arm started a fresh worker process and a fresh\nshape-specific production autotune. This is required because\n`cupti.finalize()` is process-global teardown.\n- Weight construction/quantization, kernel compilation, autotuning,\noutput allocation, and correctness checks were outside the timed region.\n- Timing used CUDA graph + PDL, cold L2, 5 warmups, and 30 CUPTI\nsamples. The table reports the CUPTI median in microseconds.\n- `speedup = mean(A1, A2) / B`; values above `1.0x` are faster. Adjacent\nbaseline drift is reported separately.\n- Every candidate worker passed finite-output, FP32 reference, eager\nrepeatability, graph replay repeatability, and graph-versus-eager\nbitwise checks.\n\n### Raw CUPTI medians and derived speedups\n\n| Projection `(N,K)` | M | O2 A1 (us) | O3 + raster axis (us) | O2 A2\n(us) | Speedup |\n|:--|--:|--:|--:|--:|--:|\n| down `(6656,19968)` | 1 | 57.441 | 54.176 | 57.409 | 1.059962x |\n| down `(6656,19968)` | 8 | 57.313 | 54.145 | 57.361 | 1.058944x |\n| down `(6656,19968)` | 32 | 57.840 | 54.497 | 57.761 | 1.060623x |\n| down `(6656,19968)` | 128 | 58.353 | 55.089 | 58.305 | 1.058814x |\n| down `(6656,19968)` | 512 | 120.001 | 117.489 | 120.049 | 1.021585x |\n| down `(6656,19968)` | 1024 | 178.994 | 174.754 | 178.866 | 1.023894x |\n| down `(6656,19968)` | 2048 | 290.643 | 289.411 | 290.339 | 1.003731x |\n| down `(6656,19968)` | 4096 | 589.478 | 586.886 | 589.590 | 1.004513x |\n| up `(19968,6656)` | 1 | 40.577 | 39.232 | 40.369 | 1.031620x |\n| up `(19968,6656)` | 8 | 40.560 | 38.977 | 40.544 | 1.040422x |\n| up `(19968,6656)` | 32 | 40.737 | 39.393 | 40.608 | 1.032493x |\n| up `(19968,6656)` | 128 | 45.601 | 45.792 | 45.697 | 0.996866x |\n| up `(19968,6656)` | 512 | 104.769 | 103.473 | 104.641 | 1.011906x |\n| up `(19968,6656)` | 1024 | 182.130 | 175.714 | 178.738 | 1.026859x |\n| up `(19968,6656)` | 2048 | 305.635 | 298.787 | 305.587 | 1.022839x |\n| up `(19968,6656)` | 4096 | 614.486 | 599.638 | 613.894 | 1.024268x |\n\nSummary:\n\n- 16-shape geometric-mean speedup: `1.029759x`.\n- Range: `0.996866x`--`1.060623x`; 15/16 shapes improved and 13/16\nimproved by more than 1%.\n- Production autotuning selected N-major raster in 11/16 rows and\nretained M-major in 5/16, so neither direction is a safe global\nconstant.\n- The only slower row was up-projection M=128 at `0.996866x`, or 0.31%\nhigher latency, below the predefined 1% noise threshold.\n- A2/A1 baseline ratios ranged from `0.981376x` to `1.002105x`. The\nup-projection M=1024 outlier came from an upstream autotuner switch from\nN128 to N192; the candidate was faster than both baseline arms\n(`1.0365x` and `1.0172x`). The other 15 baseline ratios stayed within\n0.52% of one.\n\n### How much comes from O3?\n\nThe combined result should not be attributed entirely to O3 because\nproduction autotuning can select different structural tactics. Two\nisolated gates measured:\n\n- Fixed canonical tactic, eight rows spanning both projections and\n`M=1,128,1024,4096`: `1.0800x` geomean; a three-repeat down-projection\nM=128 sentinel measured `1.0985x`.\n- Production autotuning with the original structural search space, four\nrows:\n\n| Projection `(N,K)` | M | O3-only speedup |\n|:--|--:|--:|\n| down `(6656,19968)` | 128 | 1.050380x |\n| down `(6656,19968)` | 1024 | 1.019052x |\n| up `(19968,6656)` | 128 | 0.998767x |\n| up `(19968,6656)` | 1024 | 0.997945x |\n\nThe production-autotuned O3-only geomean was `1.016315x`. The expanded\nraster search supplies additional shape-dependent gains in the final\n30-tactic result.\n\n### Autotuning cost\n\nThe Cartesian raster axis deliberately increases cold first-use tuning\nwork. Across these 16 shapes, summed production-autotuner profile time\nwas `417.83 s` for 30 tactics versus `196.68 s` for the screened\n16-tactic space (`2.12x`). The final full-sweep orchestrator wall time\nwas `548.61 s`. Persisted tactic-cache hits do not repeat this search\ncost, and the broader space was chosen to cover real workloads beyond\nthese two projections.\n\n### Reproduction\n\nThe historical benchmark orchestrator records the command, environment,\nsource hash, selected tactic, pipeline/register/TMEM configuration,\ncorrectness results, per-sample timings, and worker logs in its output\ndirectory. Auto-mode tactic caches are namespaced by compile level,\ntransform-fragment configuration, and revision plus tracked-diff hash so\nan O2 or different-source winner cannot contaminate an O3 run.\n\nThe baselines require upstream's 15-tactic source, not merely\n`--compile-opt-level 2` on the candidate's 30-tactic source. The\nfollowing creates a detached worktree at the benchmark commit, where\nboth evidence scripts remain available, then runs exact\nupstream/candidate/upstream source in "},"path":{"kind":"string","value":"flashinfer/gemm/gemm_bf16_fp4_cute_dsl.py"},"language":{"kind":"string","value":"cute_dsl"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"# SPDX-FileCopyrightText: Copyright (c) 2025 by FlashInfer team.\n# SPDX-License-Identifier: Apache-2.0\n\"\"\"Architecture-specific CuTe-DSL backend for the BF16 x NVFP4 GEMM.\"\"\"\n\nimport functools\nfrom typing import Dict, List, Optional, Tuple, cast\n\nimport torch\n\nfrom ..autotuner import (\n AutoTuner,\n ConstraintSpec,\n DynamicTensorSpec,\n OptimizationProfile,\n TunableRunner,\n TuningConfig,\n)\nfrom ..fused_moe.utils import (\n get_hybrid_num_tokens_buckets,\n map_to_hybrid_bucket_uncapped,\n)\nfrom ..utils import _get_cache_buf, get_compute_capability, get_device_sm_count\nfrom .gemm_base import _check_cute_dsl_availability\nfrom .gemm_bf16_fp4 import _unswizzle_sf_128x4\n\n_BF16_FP4_ALPHA_ONE_CACHE: dict = {}\n\n\ndef _prepare_bf16_fp4_alpha(\n alpha: Optional[torch.Tensor], device: torch.device\n) -> torch.Tensor:\n \"\"\"Normalize ``alpha`` to a ``(1,) float32`` tensor for the kernel.\"\"\"\n if alpha is None:\n cached = _BF16_FP4_ALPHA_ONE_CACHE.get(device)\n if cached is None:\n cached = torch.tensor([1.0], dtype=torch.float32, device=device)\n _BF16_FP4_ALPHA_ONE_CACHE[device] = cached\n return cached\n if alpha.dim() == 0:\n return alpha.to(device=device, dtype=torch.float32).unsqueeze(0)\n return alpha.to(device=device, dtype=torch.float32).reshape(1)\n\n\ndef _select_bf16_fp4_tile_shape(\n m: int, n: int, k: int\n) -> Tuple[Tuple[int, int, int], Tuple[int, int, int]]:\n \"\"\"Pick a CTA tile shape AND MMA atom_layout for the cute-DSL bf16 x fp4 kernel.\n\n Returns ``(tile_shape_mnk, atom_layout)``.\n\n Tile shape selection:\n tile_M choice\n * M <= 16 (and tile_K=128 path): use tile_M=16 with atom_layout\n (1,2,1). Halves wasted M-rows vs tile_M=32, and a 1-M-warp\n layout removes the duplicate dequant that (2,2,1) suffers from.\n * 16 < M <= 32: use tile_M=32 with atom_layout (2,2,1). Smaller\n MMA + epilogue waste than tile_M=64.\n * M > 32: use tile_M=64 with atom_layout (2,2,1) -- standard tile,\n more rows to amortize across.\n\n tile_K choice\n * K % 128 == 0: tile_K=128 (halves K-tile count and barrier\n overhead).\n * Otherwise: tile_K=64.\n\n Why atom_layout differs:\n * (2,2,1) (default for tile_M >= 32): 4 MMA warps as 2 M x 2 N --\n well-tested cute layout, but the 2 M-warps redundantly dequant\n the same B values into their own register files (~50% waste in\n dequant compute).\n * (1,2,1) (used for tile_M=16): 2 MMA warps as 1 M x 2 N -- no\n M-warp duplication. Permutation_m = 16, so tile_M must be 16.\n \"\"\"\n tile_k = 128 if k % 128 == 0 else 64\n if m <= 16 and tile_k == 128:\n return ((16, 64, 128), (1, 2, 1))\n if m <= 32:\n return ((32, 64, tile_k), (2, 2, 1))\n return ((64, 64, tile_k), (2, 2, 1))\n\n\ndef _select_bf16_fp4_k_splits(\n m: int, n: int, k: int, tile_shape_mnk: Tuple[int, int, int], sm_count: int\n) -> int:\n \"\"\"Static split-K pick for the no-autotune fallback: only clear-win\n underfill grids get a split, closer calls are left to the autotuner.\"\"\"\n tile_m, tile_n, tile_k = tile_shape_mnk\n if tile_m != (16 if tile_k == 128 else 32):\n # Split only the tile shapes that the tactic space pairs with splits.\n return 1\n tiles = -(-m // tile_m) * -(-n // tile_n)\n if tiles * 3 > sm_count:\n return 1\n k_tiles = k // tile_k\n for splits in (8, 4, 2):\n if splits <= k_tiles and tiles * splits <= sm_count:\n return splits\n return 1\n\n\n# Stream-GEMV residency window (warps/SM): below the floor DRAM latency is\n# uncovered, far above the ceiling splits just multiply partial traffic.\n_GEMV_MIN_WARPS_PER_SM = 12\n_GEMV_MAX_WARPS_PER_SM = 96\n\n\ndef _bf16_fp4_gemv_knee_split(n: int, k: int, sm_count: int) -> int:\n \"\"\"Smallest K-split reaching ~20 warps/SM, where throughput saturates\n and deeper splits only add partial traffic; capped under one full wave\n (6 CTAs/SM = 1536-thread limit / 256) and at >= 4 K-tiles per split.\"\"\"\n ctas = -(-(n // 64) // 8)\n cap = max(1, min(int(0.95 * sm_count * 6 / ctas), (k // 16) // 4))\n return min(-(-20 * sm_count // (n // 64)), cap)\n\n\ndef _select_bf16_fp4_gemv_split(\n n: int, k: int, cc_major: int, sm_count: int\n) -> Optional[int]:\n \"\"\"m=1 no-autotune fallback pick: the stream GEMV where it applies,\n ``None`` for the MMA heuristic. Serving stacks do not tune every\n shape (vLLM never tunes the logits GEMM), so untuned m=1 matters.\"\"\"\n if cc_major != 12 or n % 64 != 0 or k // 16 < 4:\n return None\n split = _bf16_fp4_gemv_knee_split(n, k, sm_count)\n warps_per_sm = (n // 64) * split / sm_count\n if not _GEMV_MIN_WARPS_PER_SM <= warps_per_sm <= _GEMV_MAX_WARPS_PER_SM:\n return None\n return split\n\n\n_CUTE_DSL_MM_BF16_FP4_KERNEL_CACHE: dict = {}\n\n\ndef _get_cute_dsl_bf16_fp4_gemm(\n tile_shape_mnk: Tuple[int, int, int],\n a_dtype: torch.dtype,\n c_dtype: torch.dtype,\n atom_layout: Tuple[int, int, int] = (2, 2, 1),\n pipeline_depth: int = 1,\n use_fp16_mma: int = 1,\n enable_pdl: bool = True,\n tile_swizzle: int = 1,\n k_splits: int = 1,\n occupancy: int = 1,\n):\n # Normalize to a tuple (callers may pass a list) so the cache key is hashable.\n atom_layout = cast(Tuple[int, int, int], tuple(atom_layout))\n pipeline_depth = int(pipeline_depth)\n use_fp16_mma = int(use_fp16_mma)\n enable_pdl = bool(enable_pdl)\n tile_swizzle = int(tile_swizzle)\n k_splits = int(k_splits)\n occupancy = int(occupancy)\n cache_key = (\n tile_shape_mnk,\n a_dtype,\n c_dtype,\n atom_layout,\n pipeline_depth,\n use_fp16_mma,\n enable_pdl,\n tile_swizzle,\n k_splits,\n occupancy,\n )\n cached = _CUTE_DSL_MM_BF16_FP4_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n return cached\n\n _check_cute_dsl_availability()\n\n import cutlass\n import cutlass.cute as cute\n from flashinfer.cute_dsl.utils import get_max_active_clusters\n\n from .kernels.cute_dsl.dense_gemm_bf16_fp4_sm12x import (\n Sm12xDenseGemmBf16Fp4Kernel,\n )\n\n from ..cute_dsl.utils import torch_to_cutlass_dtype\n\n a_cutlass_dtype = torch_to_cutlass_dtype(a_dtype)\n c_cutlass_dtype = torch_to_cutlass_dtype(c_dtype)\n\n sym_m = cute.sym_int()\n sym_k = cute.sym_int()\n sym_n = cute.sym_int()\n sym_k_tiles = cute.sym_int()\n sym_n_packed = cute.sym_int()\n\n a_fake = cute.runtime.make_fake_compact_tensor(\n a_cutlass_dtype, (sym_m, sym_k), stride_order=(1, 0), assumed_align=16\n )\n b_packed_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (sym_k_tiles, sym_n_packed),\n stride_order=(1, 0),\n assumed_align=16,\n )\n b_sf_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_k_tiles, sym_n), stride_order=(1, 0), assumed_align=16\n )\n c_fake = cute.runtime.make_fake_compact_tensor(\n c_cutlass_dtype, (sym_m, sym_n), stride_order=(1, 0), assumed_align=16\n )\n sym_partial = cute.sym_int()\n partial_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32, (sym_partial,), assumed_align=16\n )\n alpha_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32, (1,), assumed_align=4\n )\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n\n gemm = Sm12xDenseGemmBf16Fp4Kernel(\n acc_dtype=cutlass.Float32,\n tile_shape_mnk=tile_shape_mnk,\n atom_layout=atom_layout,\n # At occupancy 3 the SMEM budget per CTA only fits 2 ab stages next\n # to the default 4-stage epilogue; a 2-stage epilogue keeps 3.\n epi_stage=2 if occupancy >= 3 else 4,\n pipeline_depth=pipeline_depth,\n use_fp16_mma=use_fp16_mma,\n enable_pdl=enable_pdl,\n tile_swizzle=tile_swizzle,\n k_splits=k_splits,\n occupancy=occupancy,\n )\n # The persistent grid launches occupancy CTAs per SM; the kernel's stage\n # budget (_compute_stages) shrinks SMEM per CTA so they co-reside.\n max_active_clusters = get_max_active_clusters(1) * occupancy\n\n compiled = cute.compile(\n gemm.wrapper,\n a_fake,\n b_packed_fake,\n b_sf_fake,\n c_fake,\n partial_fake,\n alpha_fake,\n 1, # l (batch)\n max_active_clusters,\n stream_fake,\n options=\"--opt-level 2 --enable-tvm-ffi\",\n )\n\n _CUTE_DSL_MM_BF16_FP4_KERNEL_CACHE[cache_key] = compiled\n return compiled\n\n\ndef _get_cute_dsl_bf16_fp4_gemv(\n splits: int,\n a_dtype: torch.dtype,\n c_dtype: torch.dtype,\n enable_pdl: bool = True,\n):\n \"\"\"Compile-cache the m=1 streaming GEMV (same call signature as the\n compiled MMA kernel, so the runner dispatches either transparently).\"\"\"\n splits = int(splits)\n enable_pdl = bool(enable_pdl)\n cache_key = (\"gemv\", splits, a_dtype, c_dtype, enable_pdl)\n cached = _CUTE_DSL_MM_BF16_FP4_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n return cached\n\n _check_cute_dsl_availability()\n\n import cutlass\n import cutlass.cute as cute\n\n from .kernels.cute_dsl.gemv_bf16_fp4_sm12x import GemvBf16Fp4Sm12x\n\n from ..cute_dsl.utils import torch_to_cutlass_dtype\n\n sym = [cute.sym_int() for _ in range(6)]\n a_fake = cute.runtime.make_fake_compact_tensor(\n torch_to_cutlass_dtype(a_dtype),\n (sym[0], sym[1]),\n stride_order=(1, 0),\n assumed_align=16,\n )\n b_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (sym[2], sym[3]), stride_order=(1, 0), assumed_align=16\n )\n sf_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym[2], sym[4]), stride_order=(1, 0), assumed_align=16\n )\n c_fake = cute.runtime.make_fake_compact_tensor(\n torch_to_cutlass_dtype(c_dtype),\n (sym[0], sym[4]),\n stride_order=(1, 0),\n assumed_align=16,\n )\n partial_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32, (sym[5],), assumed_align=16\n )\n alpha_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32, (1,), assumed_align=4\n )\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n\n compiled = cute.compile(\n GemvBf16Fp4Sm12x(splits=splits, enable_pdl=enable_pdl),\n a_fake,\n b_fake,\n sf_fake,\n c_fake,\n partial_fake,\n alpha_fake,\n stream_fake,\n options=\"--opt-level 2 --enable-tvm-ffi\",\n )\n\n _CUTE_DSL_MM_BF16_FP4_KERNEL_CACHE[cache_key] = compiled\n return compiled\n\n\ndef _e4m3_to_s0e5m3(sf_u8: torch.Tensor) -> torch.Tensor:\n \"\"\"Reformat a uint8 tensor of E4M3 scale bytes to S0E5M3 bytes.\n Used in cute-dsl backend for faster in-kernel scale decode.\n \"\"\"\n f16 = sf_u8.contiguous().view(torch.float8_e4m3fn).to(torch.float16)\n bits = f16.view(torch.int16).to(torch.int32) & 0xFFFF\n return ((bits >> 7) & 0xFF).to(torch.uint8)\n\n\n_CUTE_DSL_PACK_TILE_K: int = 16 # K-tile size = MMA K-block size\n_CUTE_DSL_PACK_TILE_N: int = 64 # N-tile size = kernel tile_N\n_CUTE_DSL_PACK_INTS_PER_TILE: int = 128 # int32s per (16K x 64N) repack block\n\n\ndef _cute_dsl_pack_fp4_weight(b: torch.Tensor) -> torch.Tensor:\n \"\"\"Repack a packed FP4 weight for the bf16 x fp4 cute-DSL kernel.\"\"\"\n if b.dtype != torch.uint8:\n b = b.view(torch.uint8)\n\n k_half, n = b.shape\n k = k_half * 2\n if k % _CUTE_DSL_PACK_TILE_K != 0:\n raise ValueError(f\"K must be a multiple of {_CUTE_DSL_PACK_TILE_K} (got K={k})\")\n if n % _CUTE_DSL_PACK_TILE_N != 0:\n raise ValueError(f\"N must be a multiple of {_CUTE_DSL_PACK_TILE_N} (got N={n})\")\n\n device = b.device\n k_tiles = k // _CUTE_DSL_PACK_TILE_K\n n_tiles = n // _CUTE_DSL_PACK_TILE_N\n k_half_per_tile = _CUTE_DSL_PACK_TILE_K // 2 # 8 packed K-rows per tile\n\n u32_pos = torch.arange(\n _CUTE_DSL_PACK_INTS_PER_TILE, device=device, dtype=torch.long\n )\n u32_idx_local = u32_pos % 2\n lane = (u32_pos // 2) % 32\n n_warp_idx = u32_pos // 64\n\n tc_col = lane // 4 # in [0, 8)\n tc_row_half = lane % 4 # tc_row = tc_row_half * 2 in {0, 2, 4, 6}\n base_n = n_warp_idx * 8 + tc_col # in [0, 16)\n\n byte_k_half_offset = torch.tensor([0, 4, 0, 4], device=device, dtype=torch.long)\n n_offset_stack = torch.tensor(\n [[0, 0, 16, 16], [32, 32, 48, 48]], device=device, dtype=torch.long\n )\n byte_n_offset = n_offset_stack[u32_idx_local] # (128, 4)\n\n # Source byte within the (8, 64) tile for each (u32_pos, byte_idx).\n k_half_in_tile = tc_row_half[:, None] + byte_k_half_offset[None, :] # (128, 4)\n n_in_tile = base_n[:, None] + byte_n_offset # (128, 4)\n within_idx = (k_half_in_tile * _CUTE_DSL_PACK_TILE_N + n_in_tile).reshape(\n -1\n ) # (512,) flat index into a row-major (8, 64) tile\n\n # (K/2, N) -> (K_tiles, 8, N_tiles, 64) -> (K_tiles, N_tiles, 8*64) so the\n # 512 source bytes of each tile are contiguous, then gather them in\n # (u32_pos, byte_idx) order.\n tile_bytes = (\n b.reshape(k_tiles, k_half_per_tile, n_tiles, _CUTE_DSL_PACK_TILE_N)\n .permute(0, 2, 1, 3)\n .reshape(k_tiles, n_tiles, k_half_per_tile * _CUTE_DSL_PACK_TILE_N)\n )\n gathered = tile_bytes[:, :, within_idx].reshape(\n k_tiles, n_tiles, _CUTE_DSL_PACK_INTS_PER_TILE, 4\n )\n\n # Each 4 consecutive bytes are one little-endian int32 (byte 0 = bits 0-7),\n # exactly what the kernel's 32-bit loads read -- reinterpret in place.\n return gathered.view(torch.int32).reshape(\n k_tiles, n_tiles * _CUTE_DSL_PACK_INTS_PER_TILE\n )\n\n\ndef _prepare_cute_dsl_sm12x(\n b: torch.Tensor,\n b_descale: torch.Tensor,\n alpha: Optional[torch.Tensor],\n block_size: int,\n) -> Tuple[torch.Tensor, torch.Tensor, Optional[torch.Tensor]]:\n \"\"\"cute-DSL-backend prep: repack the weight + unswizzle the SF.\n\n Produces the bespoke layout the cute-DSL kernel consumes:\n * weight: ``(K // 16, N * 2)`` int32 (see :func:`_cute_dsl_pack_fp4_weight`).\n * SF: ``(K // block_size, N)`` uint8 -- per-block scales reformatted to\n S0E5M3, the format the cute-DSL kernel decodes.\n ``alpha`` is passed through unchanged (the compute step normalizes it\n to a ``(1,) float32`` scalar). Pair the returned tensors with\n ``mm_bf16_fp4(a, b, b_descale, alpha, backend='cute-dsl')``.\n \"\"\"\n n = int(b.shape[0])\n k = int(b.shape[1]) * 2\n k_sf = k // block_size\n\n b_kn = b.t().contiguous()\n b_packed = _cute_dsl_pack_fp4_weight(b_kn) # (K//16, N*2) int32\n\n linear_sf = _unswizzle_sf_128x4(b_descale, n, k_sf) # (N, K_sf) uint8\n sf_ksf_n = linear_sf.t().contiguous() # (K_sf, N) uint8 (E4M3)\n sf_ksf_n = _e4m3_to_s0e5m3(sf_ksf_n) # -> S0E5M3\n return b_packed, sf_ksf_n, alpha\n\n\ndef _prepare_cute_dsl_sm100(\n b: torch.Tensor,\n b_descale: torch.Tensor,\n alpha: Optional[torch.Tensor],\n block_size: int,\n) -> Tuple[torch.Tensor, torch.Tensor, Optional[torch.Tensor]]:\n \"\"\"cute-DSL-backend prep: keep SF in swizzled layout.\n\n ``convert_sf_to_mma_layout`` only creates the six-dimensional strided view\n consumed by the SM100 TMA descriptor; it does not copy or linearize the\n canonical 128x4 scale-factor buffer.\n \"\"\"\n from ..cute_dsl.utils import convert_sf_to_mma_layout\n\n n = int(b.shape[0])\n k = int(b.shape[1]) * 2\n b_descale = b_descale.contiguous()\n weight_sf = convert_sf_to_mma_layout(\n b_descale,\n m=n,\n k=k,\n num_groups=1,\n sf_vec_size=block_size,\n )\n return b.contiguous(), weight_sf, alpha\n\n\ndef _prepare_cute_dsl(\n b: torch.Tensor,\n b_descale: torch.Tensor,\n alpha: Optional[torch.Tensor],\n block_size: int,\n) -> Tuple[torch.Tensor, torch.Tensor, Optional[torch.Tensor]]:\n \"\"\"Dispatch weight preparation to the architecture-specific DSL kernel.\"\"\"\n major, minor = get_compute_capability(b.device)\n if (major, minor) in ((10, 0), (10, 3)):\n return _prepare_cute_dsl_sm100(b, b_descale, alpha, block_size)\n elif major == 12:\n return _prepare_cute_dsl_sm12x(b, b_descale, alpha, block_size)\n else:\n raise NotImplementedError(\n f\"cute-dsl w4a16 GEMM only supports SM100/103 and SM12x; got {major}.{minor}\"\n )\n\n\n@functools.cache\ndef _bf16_fp4_cute_dsl_tactic_configs(\n n: int, k: int, sm_count: int\n) -> Tuple[\n Tuple[Tuple[int, int, int], Tuple[int, int, int], int, int, int, int, int, str],\n ...,\n]:\n \"\"\"Enumerate cute-DSL tactic configs for a given ``(N, K)``.\n\n Returns a tuple of ``(tile_shape_mnk, atom_layout, pipeline_depth,\n use_fp16_mma, tile_swizzle, k_splits, occupancy, kind)`` entries,\n where ``kind`` selects the kernel: ``\"mma\"`` (the dense GEMM, all\n fields live) or ``\"gemv\"`` (the m=1 streaming kernel, which only\n reads ``k_splits``). The gemv entries include device-derived splits,\n so a tactic index is only meaningful for the ``(n, k, sm_count)`` it\n was enumerated with.\n \"\"\"\n tile_k = 128 if k % 128 == 0 else 64\n\n # (tile_M, atom_layout) shapes the kernel is designed/validated for, at the\n # default tile_N=64; a tile_N=128 variant is added below for very large N.\n tile_m_atoms: List[Tuple[int, Tuple[int, int, int]]] = []\n if tile_k == 128:\n tile_m_atoms.append((16, (1, 2, 1)))\n tile_m_atoms.append((32, (2, 2, 1)))\n tile_m_atoms.append((64, (2, 2, 1)))\n\n configs: List[\n Tuple[Tuple[int, int, int], Tuple[int, int, int], int, int, int, int, int, str]\n ] = []\n seen = set()\n\n def add(tile_m, atom, pdepth, fp16, tile_n=64, tk=None, swz=1, splits=1, occ=1):\n cfg = (\n (tile_m, tile_n, tile_k if tk is None else tk),\n atom,\n pdepth,\n fp16,\n swz,\n splits,\n occ,\n \"mma\",\n )\n key = (cfg[0], cfg[1], pdepth, fp16, swz, splits, occ)\n if key not in seen:\n seen.add(key)\n configs.append(cfg)\n\n base_tile_m, base_atom = tile_m_atoms[0]\n add(base_tile_m, base_atom, 1, 1) # 0: baseline\n add(base_tile_m, base_atom, 0, 1) # no dequant prefetch (helps short-K)\n for tile_m, atom in tile_m_atoms[1:]:\n add(tile_m, atom, 1, 1)\n\n # Small-N grids underfill the GPU; offer them split-K variants.\n if n // 64 <= 256:\n k_tiles = k // tile_k\n for splits in (2, 4, 8):\n if splits <= k_tiles:\n add(base_tile_m, base_atom, 1, 1, splits=splits)\n\n # tile_N=128 halves the (m,n)-tile count but needs large wave count.\n if tile_k == 128 and n >= 12288 and n % 128 == 0:\n add(base_tile_m, base_atom, 1, 1, tile_n=128)\n\n # tile_K=64 has more ab stages, but requires larger problem size.\n if tile_k == 128 and n >= 8192:\n add(base_tile_m, base_atom, 1, 1, tile_n=64, tk=64)\n\n # tile_M=128 (taller M tile, atom (2,2,1)) -- the large-M *prefill* lever.\n if tile_k == 128:\n add(128, (2, 2, 1), 1, 1)\n\n # Threadblock swizzle (tile_swizzle=8) -- for large-M prefill.\n if tile_k == 128 and n * k >= 16 * 1024 * 1024:\n add(64, (2, 2, 1), 1, 1, swz=8)\n if tile_k == 128:\n add(128, (2, 2, 1), 1, 1, swz=8)\n\n # tile_N=128 (with tile_M=64, atom (2,2,1)) -- large shapes.\n if tile_k == 128 and n % 128 == 0 and n >= 4096:\n add(64, (2, 2, 1), 1, 1, tile_n=128, swz=8)\n add(64, (2, 2, 1), 1, 1, tile_n=128, swz=1)\n\n # occupancy=2: two co-resident CTAs per SM at half the ab_stage depth\n # (the kernel's occupancy note explains the trade). The 128-tile gate\n # fills two CTAs per SM on ~188-SM parts; 5080-class still qualifies.\n if tile_k == 128 and n // 64 >= 128:\n add(base_tile_m, base_atom, 1, 1, occ=2)\n add(base_tile_m, base_atom, 0, 1, occ=2)\n\n # occupancy=2 x split-K: grids too small to fill two CTAs per SM (the\n # down-proj class) get there by splitting K; the makespan gate decides\n # per device whether the pieces fit.\n if tile_k == 128 and n // 64 <= 256:\n k_tiles = k // tile_k\n for splits in (2, 4, 8):\n if splits <= k_tiles:\n add(base_tile_m, base_atom, 1, 1, splits=splits, occ=2)\n\n # occupancy=3: 9 resident warps per SM; needs the 2-stage epilogue to\n # keep 3 ab stages in SMEM (paired in _get_cute_dsl_bf16_fp4_gemm).\n if tile_k == 128 and n // 64 >= 128:\n add(base_tile_m, base_atom, 1, 1, occ=3)\n\n # Streaming GEMV for m=1 decode (SMEM-free, no tensor cores; see\n # GemvBf16Fp4Sm12x). splits shards K across grid.y for grid fill.\n if n % 64 == 0:\n k_tiles16 = k // 16\n gemv_splits = [s for s in (1, 2, 4, 8, 16, 32) if s * 4 <= k_tiles16]\n if gemv_splits:\n knee = _bf16_fp4_gemv_knee_split(n, k, sm_count)\n if knee not in gemv_splits:\n gemv_splits.append(knee)\n for splits in gemv_splits:\n configs.append(((1, 64, 16), (0, 0, 0), 0, 0, 1, splits, 1, \"gemv\"))\n\n return tuple(configs)\n\n\n_BF16_FP4_CUTE_DSL_TUNING_CONFIG = TuningConfig(\n dynamic_tensor_specs=(\n DynamicTensorSpec(\n (0,), # a_tensor_index\n (0,), # M dimension\n get_hybrid_num_tokens_buckets,\n map_to_hybrid_bucket_uncapped,\n ),\n ),\n constraint_specs=(\n ConstraintSpec(\n 5, # out_tensor_index follows M\n 0,\n lambda shapes: shapes[0][0],\n ),\n ),\n)\n\n\n_SM100_BF16_FP4_KERNEL_CACHE: Dict[Tuple, object] = {}\n\n_SM100_BF16_FP4_N_TILES = (8, 16, 32, 64, 128, 192)\n_SM100_BF16_FP4_K_TILE = 256\n_SM100_BF16_FP4_RASTER_ALONG_M = True\n\n\ndef _sm100_bf16_fp4_tactic_configs() -> List[Tuple]:\n \"\"\"Return the SM100 W4A16 tactics shared with the MoE GEMMs.\n\n Dense GEMM maps public output channels to the kernel M mode and public\n rows to its N mode. The 128x192x256 one-CTA tile is excluded because it\n cannot retain the two load and transform stages required by the kernel.\n \"\"\"\n tactics: List[Tuple] = []\n for route_tile in _SM100_BF16_FP4_N_TILES:\n for gemm_m, cluster_shape_mn in (\n (128, (1, 1)),\n (128, (2, 1)),\n (256, (2, 1)),\n ):\n if route_tile < 16 and gemm_m == 256:\n continue\n if route_tile == 192 and gemm_m == 128:\n continue\n tactics.append(\n (\n (gemm_m, route_tile, _SM100_BF16_FP4_K_TILE),\n cluster_shape_mn,\n _SM100_BF16_FP4_RASTER_ALONG_M,\n )\n )\n return tactics\n\n\n_SM100_BF16_FP4_TACTICS = tuple(_sm100_bf16_fp4_tactic_configs())\n\n_SM100_BF16_FP4_CUTE_DSL_TUNING_CONFIG = TuningConfig(\n dynamic_tensor_specs=(\n DynamicTensorSpec(\n (0,), # a_tensor_index\n (0,), # public M dimension\n get_hybrid_num_tokens_buckets,\n map_to_hybrid_bucket_uncapped,\n ),\n ),\n constraint_specs=(\n ConstraintSpec(\n 5, # out_tensor_index follows public M\n 0,\n lambda shapes: shapes[0][0],\n ),\n ),\n)\n\n\ndef _get_sm100_bf16_fp4_kernel(\n weight_ptr,\n weight_sf_ptr,\n activation_ptr,\n alpha_ptr,\n output_ptr,\n n: int,\n m: int,\n k: int,\n max_active_clusters: int,\n stream,\n enable_pdl: bool,\n mma_tiler_mnk: Tuple[int, int, int],\n cluster_shape_mn: Tuple[int, int],\n raster_along_m: bool,\n):\n \"\"\"Compile the SM100/103 dense W4A16 kernel for one tactic.\"\"\"\n import cutlass\n import cutlass.cute as cute\n\n from .kernels.cute_dsl.dense_gemm_bf16_fp4_sm100 import (\n Sm100DenseGemmBf16Fp4Kernel,\n )\n\n use_2cta_instrs = mma_tiler_mnk[0] == 256\n transform_fragment_size = 128 if k == mma_tiler_mnk[2] else 32\n cache_key = (\n mma_tiler_mnk,\n cluster_shape_mn,\n bool(raster_along_m),\n transform_fragment_size,\n int(max_active_clusters),\n bool(enable_pdl),\n )\n compiled = _SM100_BF16_FP4_KERNEL_CACHE.get(cache_key)\n if compiled is not None:\n return compiled\n\n kernel = Sm100DenseGemmBf16Fp4Kernel(\n acc_dtype=cutlass.Float32,\n use_2cta_instrs=use_2cta_instrs,\n mma_tiler_mnk=mma_tiler_mnk,\n cluster_shape_mn=cluster_shape_mn,\n enable_pdl=enable_pdl,\n raster_along_m=raster_along_m,\n transform_fragment_size=transform_fragment_size,\n )\n compiled = cute.compile(\n kernel.wrapper,\n weight_ptr,\n weight_sf_ptr,\n activation_ptr,\n alpha_ptr,\n output_ptr,\n n,\n m,\n k,\n max_active_clusters=max_active_clusters,\n stream=stream,\n options=\"--opt-level 2 --enable-tvm-ffi\",\n )\n _SM100_BF16_FP4_KERNEL_CACHE[cache_key] = compiled\n return compiled\n\n\ndef _launch_cute_dsl_sm100(\n a: torch.Tensor,\n b: torch.Tensor,\n b_descale: torch.Tensor,\n alpha_for_launch: torch.Tensor,\n out: torch.Tensor,\n tactic: Tuple,\n enable_pdl: bool,\n) -> torch.Tensor:\n \"\"\"Compile, cache, and launch one SM100 W4A16 tactic.\"\"\"\n import cutlass\n import cutlass.cute as cute\n\n from ..cute_dsl.utils import current_cuda_stream, get_max_active_clusters, make_ptr\n\n m, k = map(int, a.shape)\n n = int(b.shape[0])\n mma_tiler_mnk, cluster_shape_mn, raster_along_m = tactic\n cluster_size = int(cluster_shape_mn[0]) * int(cluster_shape_mn[1])\n for name, tensor, align in (\n (\"b\", b, 32),\n (\"b_descale\", b_descale, 16),\n (\"a\", a, 32),\n (\"alpha\", alpha_for_launch, 16),\n (\"out\", out, 32),\n ):\n if tensor.data_ptr() % align:\n raise ValueError(\n f\"SM100 cute-dsl requires a {align}-byte aligned {name}; \"\n f\"got address {tensor.data_ptr():`#x`}. Pass a freshly \"\n \"allocated contiguous tensor.\"\n )\n stream = current_cuda_stream()\n weight_ptr = make_ptr(\n cutlass.Float4E2M1FN, b.data_ptr(), cute.AddressSpace.gmem, assumed_align=32\n )\n weight_sf_ptr = make_ptr(\n cutlass.Float8E4M3FN,\n b_descale.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n activation_ptr = make_ptr(\n cutlass.BFloat16,\n a.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=32,\n )\n alpha_ptr = make_ptr(\n cutlass.Float32,\n alpha_for_launch.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n output_ptr = make_ptr(\n cutlass.BFloat16, out.data_ptr(), cute.AddressSpace.gmem, assumed_align=32\n )\n max_active_clusters = get_max_active_clusters(cluster_size)\n compiled = _get_sm100_bf16_fp4_kernel(\n weight_ptr,\n weight_sf_ptr,\n activation_ptr,\n alpha_ptr,\n output_ptr,\n n,\n m,\n k,\n max_active_clusters,\n stream,\n enable_pdl,\n mma_tiler_mnk,\n cluster_shape_mn,\n raster_along_m,\n )\n compiled(\n b.data_ptr(),\n b_descale.data_ptr(),\n a.data_ptr(),\n alpha_for_launch.data_ptr(),\n out.data_ptr(),\n n,\n m,\n k,\n stream,\n )\n return out\n\n\ndef _cute_dsl_sm100_bf16_fp4_runner(enable_pdl: bool = True) -> TunableRunner:\n \"\"\"Build the tunable runner for the native-layout SM100 W4A16 GEMM.\"\"\"\n\n class CuteDslSm100Bf16Fp4Runner(TunableRunner):\n def get_cache_key_extras(self, inputs: List[torch.Tensor]) -> tuple:\n _, b, _, _, out_dtype, _, block_size = inputs\n n = int(b.shape[0])\n k = int(b.shape[1]) * 2\n return (out_dtype, n, k, int(block_size), bool(enable_pdl))\n\n def get_valid_tactics(\n self,\n inputs: List[torch.Tensor],\n profile: OptimizationProfile,\n ) -> List[Tuple]:\n import cutlass\n\n from .kernels.cute_dsl.dense_gemm_bf16_fp4_sm100 import (\n Sm100DenseGemmBf16Fp4Kernel,\n )\n\n a, b, _, _, _, _, _ = inputs\n m, k = map(int, a.shape)\n n = int(b.shape[0])\n valid_tactics: List[Tuple] = []\n for tactic in _SM100_BF16_FP4_TACTICS:\n mma_tiler_mnk, cluster_shape_mn, _ = tactic\n if Sm100DenseGemmBf16Fp4Kernel.can_implement(\n mnkl=(n, m, k, 1),\n a_dtype=cutlass.Float4E2M1FN,\n b_dtype=cutlass.BFloat16,\n c_dtype=cutlass.BFloat16,\n a_major=\"k\",\n b_major=\"k\",\n c_major=\"m\",\n mma_tiler=mma_tiler_mnk,\n cluster_shape_mn=cluster_shape_mn,\n use_2cta_instrs=mma_tiler_mnk[0] == 256,\n ):\n valid_tactics.append(tactic)\n return valid_tactics\n\n def forward(\n self,\n inputs: List[torch.Tensor],\n tactic=-1,\n do_preparation: bool = False,\n **kwargs,\n ) -> torch.Tensor:\n a, b, b_descale, alpha_for_launch, _, out, _ = inputs\n if tactic == -1:\n valid = self.get_valid_tactics(inputs, None)\n if valid:\n tactic = valid[0]\n else:\n m, k = map(int, a.shape)\n raise ValueError(\n \"no SM100 cute-dsl w4a16 tactic supports \"\n f\"m={m}, n={int(b.shape[0])}, k={k}\"\n )\n return _launch_cute_dsl_sm100(\n a,\n b,\n b_descale,\n alpha_for_launch,\n out,\n tactic,\n enable_pdl,\n )\n\n return CuteDslSm100Bf16Fp4Runner()\n\n\ndef _compute_cute_dsl_sm100(\n a: torch.Tensor,\n b: torch.Tensor,\n b_descale: torch.Tensor,\n alpha: Optional[torch.Tensor],\n out_dtype: torch.dtype,\n out: Optional[torch.Tensor],\n block_size: int,\n enable_pdl: bool,\n) -> torch.Tensor:\n \"\"\"Launch the SM100 native-layout NVFP4 x BF16 GEMM.\"\"\"\n if a.device != b.device or a.device != b_descale.device:\n raise ValueError(\n \"a, b, and b_descale must be on the same CUDA device; got \"\n f\"{a.device}, {b.device}, and {b_descale.device}.\"\n )\n if not a.is_contiguous() or not b.is_contiguous():\n raise ValueError(\"SM100 cute-dsl requires contiguous a and b tensors.\")\n if a.dtype != torch.bfloat16:\n raise TypeError(\n f\"SM100 cute-dsl currently requires a bfloat16 activation; got {a.dtype}.\"\n )\n if b.dtype != torch.uint8:\n raise TypeError(\n \"SM100 cute-dsl expects the uint8 NVFP4 weight returned by \"\n \"prepare_bf16_fp4_weights(..., backend='cute-dsl'); \"\n f\"got {b.dtype}.\"\n )\n if out_dtype != torch.bfloat16:\n raise NotImplementedError(\n f\"SM100 cute-dsl currently requires a bfloat16 output; got {out_dtype}.\"\n )\n\n m, k = map(int, a.shape)\n n = int(b.shape[0])\n if int(b.shape[1]) * 2 != k:\n raise ValueError(\n f\"a.shape[1]={k} but b.shape={tuple(b.shape)} encodes K=\"\n f\"{int(b.shape[1]) * 2}\"\n )\n if out is None:\n out = torch.empty((m, n), device=a.device, dtype=out_dtype)\n else:\n if tuple(out.shape) != (m, n):\n raise ValueError(f\"out shape {tuple(out.shape)} != expected {(m, n)}\")\n if out.dtype != out_dtype:\n raise TypeError(f\"out dtype {out.dtype} != requested out_dtype {out_dtype}\")\n if out.device != a.device or not out.is_contiguous():\n raise ValueError(\n \"out must be contiguous and on the same device as a; got \"\n f\"device={out.device}, contiguous={out.is_contiguous()}.\"\n )\n\n alpha_for_launch = _prepare_bf16_fp4_alpha(alpha, a.device)\n tuner = AutoTuner.get()\n runner = _cute_dsl_sm100_bf16_fp4_runner(enable_pdl=enable_pdl)\n inputs = [a, b, b_descale, alpha_for_launch, out_dtype, out, block_size]\n chosen_runner, tactic = tuner.choose_one(\n \"bf16_fp4_cute_dsl_sm100_gemm\",\n [runner],\n _SM100_BF16_FP4_CUTE_DSL_TUNING_CONFIG,\n inputs,\n )\n chosen_runner(inputs=inputs, tactic=tactic)\n return out\n\n\ndef _cute_dsl_bf16_fp4_runner(enable_pdl: bool = True) -> TunableRunner:\n \"\"\"Build a ``CuteDslBf16Fp4Runner`` for the cute-DSL bf16 x fp4 GEMM.\"\"\"\n\n class CuteDslBf16Fp4Runner(TunableRunner):\n def get_cache_key_extras(self, inputs: List[torch.Tensor]) -> tuple:\n a, b, _, _, out_dtype, _, block_size = inputs\n n = int(b.shape[1]) // 2\n k = int(b.shape[0]) * int(block_size)\n # The config list holds device-derived gemv splits, so a tuned\n # index must not replay on a different SM count.\n return (out_dtype, n, k, get_device_sm_count(a.device))\n\n def get_valid_tactics(\n self,\n inputs: List[torch.Tensor],\n profile: OptimizationProfile,\n ) -> List[int]:\n a, b, _, _, _, _, block_size = inputs\n n = int(b.shape[1]) // 2\n k = int(b.shape[0]) * int(block_size)\n m_opt = int(profile.get_opt_shapes()[0][0])\n sm_count = get_device_sm_count(a.device)\n # GEMV is validated only on SM12x; the autotuner ranks by time\n # and would not catch a wrong-but-fast kernel elsewhere.\n gemv_ok = get_compute_capability(a.device)[0] == 12\n configs = _bf16_fp4_cute_dsl_tactic_configs(n, k, sm_count)\n\n def split_reduces_makespan(cfg) -> bool:\n # Offer a split only if it shrinks the last wave >= 25%: the\n # autotuner's warm-cache timing hides the partials cost, so it\n # cannot reject bad splits itself.\n splits = cfg[5]\n if splits == 1:\n return True\n tile_m, tile_n, _ = cfg[0]\n tiles = (-(-m_opt // tile_m)) * (-(-n // tile_n))\n # occupancy multiplies the co-resident CTA slots per SM, so\n # occ2 x split-K fits 2x the pieces in one wave.\n slots = sm_count * cfg[6]\n base_waves = -(-tiles // sm_count)\n split_waves = (-(-tiles * splits // slots)) / splits\n return split_waves <= 0.75 * base_waves\n\n def gemv_valid(cfg) -> bool:\n # The m buckets round up, so only runtime m == 1 lands in\n # the m_opt == 1 bucket.\n if m_opt != 1 or not gemv_ok:\n return False\n warps_per_sm = (n // 64) * cfg[5] / sm_count\n return _GEMV_MIN_WARPS_PER_SM <= warps_per_sm <= _GEMV_MAX_WARPS_PER_SM\n\n return [\n i\n for i, cfg in enumerate(configs)\n if (\n gemv_valid(cfg) if cfg[7] == \"gemv\" else split_reduces_makespan(cfg)\n )\n ]\n\n def forward(\n self,\n inputs: List[torch.Tensor],\n tactic: int = -1,\n do_preparation: bool = False,\n **kwargs,\n ) -> torch.Tensor:\n a, b, b_sf_u8, alpha_for_launch, out_dtype, out, block_size = inputs\n n = int(b.shape[1]) // 2\n k = int(b.shape[0]) * int(block_size)\n m = int(a.shape[0])\n cfg = (\n _bf16_fp4_cute_dsl_tactic_configs(n, k, get_device_sm_count(a.device))[\n tactic\n ]\n if tactic >= 0\n else None\n )\n splits: Optional[int] = None\n if cfg is not None and cfg[7] == \"gemv\":\n if m != 1:\n raise ValueError(f\"the gemv tactic requires m == 1, got m={m}\")\n splits = cfg[5]\n elif cfg is None and m == 1 and not do_preparation:\n # Prep calls run outside the autotuner's per-tactic exception\n # guard; a gemv failure there would abort the whole op.\n splits = _select_bf16_fp4_gemv_split(\n n,\n k,\n get_compute_capability(a.device)[0],\n get_device_sm_count(a.device),\n )\n if splits is not None:\n compiled = _get_cute_dsl_bf16_fp4_gemv(\n splits, a.dtype, out_dtype, enable_pdl=enable_pdl\n )\n if splits > 1:\n partial = _get_cache_buf(\n \"mm_bf16_fp4_split_k_partial\",\n splits * m * n * 4,\n a.device,\n ).view(torch.float32)\n else:\n partial = _get_cache_buf(\n \"mm_bf16_fp4_split_k_partial_dummy\", 16, a.device\n ).view(torch.float32)\n compiled(a, b, b_sf_u8, out, partial, alpha_for_launch)\n return out\n if tactic < 0:\n # Fallback == pre-autotuner heuristic (M-aware), default knobs.\n tile_shape_mnk, atom_layout = _select_bf16_fp4_tile_shape(m, n, k)\n pipeline_depth, use_fp16_mma, tile_swizzle, occupancy = 1, 1, 1, 1\n k_splits = _select_bf16_fp4_k_splits(\n m, n, k, tile_shape_mnk, get_device_sm_count(a.device)\n )\n else:\n (\n tile_shape_mnk,\n atom_layout,\n pipeline_depth,\n use_fp16_mma,\n tile_swizzle,\n k_splits,\n occupancy,\n ) = cfg[:7]\n compiled = _get_cute_dsl_bf16_fp4_gemm(\n tile_shape_mnk,\n a.dtype,\n out_dtype,\n atom_layout,\n pipeline_depth,\n use_fp16_mma,\n enable_pdl=enable_pdl,\n tile_swizzle=tile_swizzle,\n k_splits=k_splits,\n occupancy=occupancy,\n )\n if k_splits > 1:\n if k_splits > k // tile_shape_mnk[2]:\n raise ValueError(\n f\"k_splits={k_splits} exceeds the K-tile count for \"\n f\"k={k}, tile_k={tile_shape_mnk[2]}\"\n )\n # The compiled call launches the reduce kernel as well, so\n # ``out`` is final on return.\n partial = _get_cache_buf(\n \"mm_bf16_fp4_split_k_partial\",\n k_splits * m * n * 4,\n a.device,\n ).view(torch.float32)\n else:\n partial = _get_cache_buf(\n \"mm_bf16_fp4_split_k_partial_dummy\", 16, a.device\n ).view(torch.float32)\n compiled(a, b, b_sf_u8, out, partial, alpha_for_launch)\n return out\n\n return CuteDslBf16Fp4Runner()\n\n\ndef _compute_cute_dsl(\n a: torch.Tensor,\n b: torch.Tensor,\n b_descale: torch.Tensor,\n alpha: Optional[torch.Tensor],\n out_dtype: torch.dtype,\n out: Optional[torch.Tensor],\n block_size: int,\n enable_pdl: bool = True,\n) -> torch.Tensor:\n \"\"\"Dispatch to the SM100/103 or SM12x compiled Blackwell kernel.\n\n SM100 consumes the native ``(N, K // 2)`` uint8 NVFP4 weight and 128x4 SF.\n\n SM12x consumes the packed ``(K // 16, N * 2)`` int32 weight and\n ``(K // block_size, N)`` uint8 SF in S0E5M3 format (reformatted from FP8-E4M3\n by :func:`_e4m3_to_s0e5m3`) returned by :func:`_prepare_cute_dsl`.\n \"\"\"\n if get_compute_capability(a.device) in ((10, 0), (10, 3)):\n return _compute_cute_dsl_sm100(\n a,\n b,\n b_descale,\n alpha,\n out_dtype,\n out,\n block_size,\n enable_pdl,\n )\n\n if b.dtype != torch.int32:\n raise TypeError(\n f\"cute-dsl backend expects the packed int32 weight from \"\n f\"prepare_bf16_fp4_weights(..., backend='cute-dsl'); got {b.dtype}.\"\n )\n if out_dtype != a.dtype:\n raise NotImplementedError(\n f\"cute-dsl backend requires out_dtype == a.dtype (got \"\n f\"out_dtype={out_dtype}, a.dtype={a.dtype}). Use the cudnn \"\n f\"backend for a mismatched output dtype.\"\n )\n k_tiles = int(b.shape[0])\n n = int(b.shape[1]) // 2\n k = k_tiles * block_size\n m = int(a.shape[0])\n if a.shape[1] != k:\n raise ValueError(\n f\"a.shape[1]={a.shape[1]} but k inferred from prepared b.shape=\"\n f\"{tuple(b.shape)} is {k}\"\n )\n\n if out is None:\n out = torch.empty((m, n), device=a.device, dtype=out_dtype)\n else:\n if tuple(out.shape) != (m, n):\n raise ValueError(f\"out shape {tuple(out.shape)} != expected {(m, n)}\")\n if out.dtype != out_dtype:\n raise TypeError(f\"out dtype {out.dtype} != requested out_dtype {out_dtype}\")\n\n b_sf_u8 = b_descale.view(torch.uint8).contiguous()\n alpha_for_launch = _prepare_bf16_fp4_alpha(alpha, a.device)\n\n tuner = AutoTuner.get()\n runner = _cute_dsl_bf16_fp4_runner(enable_pdl=enable_pdl)\n inputs = [a, b, b_sf_u8, alpha_for_launch, out_dtype, out, block_size]\n chosen_runner, tactic = tuner.choose_one(\n \"bf16_fp4_cute_dsl_gemm\",\n [runner],\n _BF16_FP4_CUTE_DSL_TUNING_CONFIG,\n inputs,\n )\n chosen_runner(inputs=inputs, tactic=tactic)\n return out\n"},"after_code":{"kind":"string","value":"# SPDX-FileCopyrightText: Copyright (c) 2025 by FlashInfer team.\n# SPDX-License-Identifier: Apache-2.0\n\"\"\"Architecture-specific CuTe-DSL backend for the BF16 x NVFP4 GEMM.\"\"\"\n\nimport functools\nfrom typing import Dict, List, Optional, Tuple, cast\n\nimport torch\n\nfrom ..autotuner import (\n AutoTuner,\n ConstraintSpec,\n DynamicTensorSpec,\n OptimizationProfile,\n TunableRunner,\n TuningConfig,\n)\nfrom ..fused_moe.utils import (\n get_hybrid_num_tokens_buckets,\n map_to_hybrid_bucket_uncapped,\n)\nfrom ..utils import _get_cache_buf, get_compute_capability, get_device_sm_count\nfrom .gemm_base import _check_cute_dsl_availability\nfrom .gemm_bf16_fp4 import _unswizzle_sf_128x4\n\n_BF16_FP4_ALPHA_ONE_CACHE: dict = {}\n\n\ndef _prepare_bf16_fp4_alpha(\n alpha: Optional[torch.Tensor], device: torch.device\n) -> torch.Tensor:\n \"\"\"Normalize ``alpha`` to a ``(1,) float32`` tensor for the kernel.\"\"\"\n if alpha is None:\n cached = _BF16_FP4_ALPHA_ONE_CACHE.get(device)\n if cached is None:\n cached = torch.tensor([1.0], dtype=torch.float32, device=device)\n _BF16_FP4_ALPHA_ONE_CACHE[device] = cached\n return cached\n if alpha.dim() == 0:\n return alpha.to(device=device, dtype=torch.float32).unsqueeze(0)\n return alpha.to(device=device, dtype=torch.float32).reshape(1)\n\n\ndef _select_bf16_fp4_tile_shape(\n m: int, n: int, k: int\n) -> Tuple[Tuple[int, int, int], Tuple[int, int, int]]:\n \"\"\"Pick a CTA tile shape AND MMA atom_layout for the cute-DSL bf16 x fp4 kernel.\n\n Returns ``(tile_shape_mnk, atom_layout)``.\n\n Tile shape selection:\n tile_M choice\n * M <= 16 (and tile_K=128 path): use tile_M=16 with atom_layout\n (1,2,1). Halves wasted M-rows vs tile_M=32, and a 1-M-warp\n layout removes the duplicate dequant that (2,2,1) suffers from.\n * 16 < M <= 32: use tile_M=32 with atom_layout (2,2,1). Smaller\n MMA + epilogue waste than tile_M=64.\n * M > 32: use tile_M=64 with atom_layout (2,2,1) -- standard tile,\n more rows to amortize across.\n\n tile_K choice\n * K % 128 == 0: tile_K=128 (halves K-tile count and barrier\n overhead).\n * Otherwise: tile_K=64.\n\n Why atom_layout differs:\n * (2,2,1) (default for tile_M >= 32): 4 MMA warps as 2 M x 2 N --\n well-tested cute layout, but the 2 M-warps redundantly dequant\n the same B values into their own register files (~50% waste in\n dequant compute).\n * (1,2,1) (used for tile_M=16): 2 MMA warps as 1 M x 2 N -- no\n M-warp duplication. Permutation_m = 16, so tile_M must be 16.\n \"\"\"\n tile_k = 128 if k % 128 == 0 else 64\n if m <= 16 and tile_k == 128:\n return ((16, 64, 128), (1, 2, 1))\n if m <= 32:\n return ((32, 64, tile_k), (2, 2, 1))\n return ((64, 64, tile_k), (2, 2, 1))\n\n\ndef _select_bf16_fp4_k_splits(\n m: int, n: int, k: int, tile_shape_mnk: Tuple[int, int, int], sm_count: int\n) -> int:\n \"\"\"Static split-K pick for the no-autotune fallback: only clear-win\n underfill grids get a split, closer calls are left to the autotuner.\"\"\"\n tile_m, tile_n, tile_k = tile_shape_mnk\n if tile_m != (16 if tile_k == 128 else 32):\n # Split only the tile shapes that the tactic space pairs with splits.\n return 1\n tiles = -(-m // tile_m) * -(-n // tile_n)\n if tiles * 3 > sm_count:\n return 1\n k_tiles = k // tile_k\n for splits in (8, 4, 2):\n if splits <= k_tiles and tiles * splits <= sm_count:\n return splits\n return 1\n\n\n# Stream-GEMV residency window (warps/SM): below the floor DRAM latency is\n# uncovered, far above the ceiling splits just multiply partial traffic.\n_GEMV_MIN_WARPS_PER_SM = 12\n_GEMV_MAX_WARPS_PER_SM = 96\n\n\ndef _bf16_fp4_gemv_knee_split(n: int, k: int, sm_count: int) -> int:\n \"\"\"Smallest K-split reaching ~20 warps/SM, where throughput saturates\n and deeper splits only add partial traffic; capped under one full wave\n (6 CTAs/SM = 1536-thread limit / 256) and at >= 4 K-tiles per split.\"\"\"\n ctas = -(-(n // 64) // 8)\n cap = max(1, min(int(0.95 * sm_count * 6 / ctas), (k // 16) // 4))\n return min(-(-20 * sm_count // (n // 64)), cap)\n\n\ndef _select_bf16_fp4_gemv_split(\n n: int, k: int, cc_major: int, sm_count: int\n) -> Optional[int]:\n \"\"\"m=1 no-autotune fallback pick: the stream GEMV where it applies,\n ``None`` for the MMA heuristic. Serving stacks do not tune every\n shape (vLLM never tunes the logits GEMM), so untuned m=1 matters.\"\"\"\n if cc_major != 12 or n % 64 != 0 or k // 16 < 4:\n return None\n split = _bf16_fp4_gemv_knee_split(n, k, sm_count)\n warps_per_sm = (n // 64) * split / sm_count\n if not _GEMV_MIN_WARPS_PER_SM <= warps_per_sm <= _GEMV_MAX_WARPS_PER_SM:\n return None\n return split\n\n\n_CUTE_DSL_MM_BF16_FP4_KERNEL_CACHE: dict = {}\n\n\ndef _get_cute_dsl_bf16_fp4_gemm(\n tile_shape_mnk: Tuple[int, int, int],\n a_dtype: torch.dtype,\n c_dtype: torch.dtype,\n atom_layout: Tuple[int, int, int] = (2, 2, 1),\n pipeline_depth: int = 1,\n use_fp16_mma: int = 1,\n enable_pdl: bool = True,\n tile_swizzle: int = 1,\n k_splits: int = 1,\n occupancy: int = 1,\n):\n # Normalize to a tuple (callers may pass a list) so the cache key is hashable.\n atom_layout = cast(Tuple[int, int, int], tuple(atom_layout))\n pipeline_depth = int(pipeline_depth)\n use_fp16_mma = int(use_fp16_mma)\n enable_pdl = bool(enable_pdl)\n tile_swizzle = int(tile_swizzle)\n k_splits = int(k_splits)\n occupancy = int(occupancy)\n cache_key = (\n tile_shape_mnk,\n a_dtype,\n c_dtype,\n atom_layout,\n pipeline_depth,\n use_fp16_mma,\n enable_pdl,\n tile_swizzle,\n k_splits,\n occupancy,\n )\n cached = _CUTE_DSL_MM_BF16_FP4_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n return cached\n\n _check_cute_dsl_availability()\n\n import cutlass\n import cutlass.cute as cute\n from flashinfer.cute_dsl.utils import get_max_active_clusters\n\n from .kernels.cute_dsl.dense_gemm_bf16_fp4_sm12x import (\n Sm12xDenseGemmBf16Fp4Kernel,\n )\n\n from ..cute_dsl.utils import torch_to_cutlass_dtype\n\n a_cutlass_dtype = torch_to_cutlass_dtype(a_dtype)\n c_cutlass_dtype = torch_to_cutlass_dtype(c_dtype)\n\n sym_m = cute.sym_int()\n sym_k = cute.sym_int()\n sym_n = cute.sym_int()\n sym_k_tiles = cute.sym_int()\n sym_n_packed = cute.sym_int()\n\n a_fake = cute.runtime.make_fake_compact_tensor(\n a_cutlass_dtype, (sym_m, sym_k), stride_order=(1, 0), assumed_align=16\n )\n b_packed_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (sym_k_tiles, sym_n_packed),\n stride_order=(1, 0),\n assumed_align=16,\n )\n b_sf_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_k_tiles, sym_n), stride_order=(1, 0), assumed_align=16\n )\n c_fake = cute.runtime.make_fake_compact_tensor(\n c_cutlass_dtype, (sym_m, sym_n), stride_order=(1, 0), assumed_align=16\n )\n sym_partial = cute.sym_int()\n partial_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32, (sym_partial,), assumed_align=16\n )\n alpha_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32, (1,), assumed_align=4\n )\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n\n gemm = Sm12xDenseGemmBf16Fp4Kernel(\n acc_dtype=cutlass.Float32,\n tile_shape_mnk=tile_shape_mnk,\n atom_layout=atom_layout,\n # At occupancy 3 the SMEM budget per CTA only fits 2 ab stages next\n # to the default 4-stage epilogue; a 2-stage epilogue keeps 3.\n epi_stage=2 if occupancy >= 3 else 4,\n pipeline_depth=pipeline_depth,\n use_fp16_mma=use_fp16_mma,\n enable_pdl=enable_pdl,\n tile_swizzle=tile_swizzle,\n k_splits=k_splits,\n occupancy=occupancy,\n )\n # The persistent grid launches occupancy CTAs per SM; the kernel's stage\n # budget (_compute_stages) shrinks SMEM per CTA so they co-reside.\n max_active_clusters = get_max_active_clusters(1) * occupancy\n\n compiled = cute.compile(\n gemm.wrapper,\n a_fake,\n b_packed_fake,\n b_sf_fake,\n c_fake,\n partial_fake,\n alpha_fake,\n 1, # l (batch)\n max_active_clusters,\n stream_fake,\n options=\"--opt-level 2 --enable-tvm-ffi\",\n )\n\n _CUTE_DSL_MM_BF16_FP4_KERNEL_CACHE[cache_key] = compiled\n return compiled\n\n\ndef _get_cute_dsl_bf16_fp4_gemv(\n splits: int,\n a_dtype: torch.dtype,\n c_dtype: torch.dtype,\n enable_pdl: bool = True,\n):\n \"\"\"Compile-cache the m=1 streaming GEMV (same call signature as the\n compiled MMA kernel, so the runner dispatches either transparently).\"\"\"\n splits = int(splits)\n enable_pdl = bool(enable_pdl)\n cache_key = (\"gemv\", splits, a_dtype, c_dtype, enable_pdl)\n cached = _CUTE_DSL_MM_BF16_FP4_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n return cached\n\n _check_cute_dsl_availability()\n\n import cutlass\n import cutlass.cute as cute\n\n from .kernels.cute_dsl.gemv_bf16_fp4_sm12x import GemvBf16Fp4Sm12x\n\n from ..cute_dsl.utils import torch_to_cutlass_dtype\n\n sym = [cute.sym_int() for _ in range(6)]\n a_fake = cute.runtime.make_fake_compact_tensor(\n torch_to_cutlass_dtype(a_dtype),\n (sym[0], sym[1]),\n stride_order=(1, 0),\n assumed_align=16,\n )\n b_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (sym[2], sym[3]), stride_order=(1, 0), assumed_align=16\n )\n sf_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym[2], sym[4]), stride_order=(1, 0), assumed_align=16\n )\n c_fake = cute.runtime.make_fake_compact_tensor(\n torch_to_cutlass_dtype(c_dtype),\n (sym[0], sym[4]),\n stride_order=(1, 0),\n assumed_align=16,\n )\n partial_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32, (sym[5],), assumed_align=16\n )\n alpha_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32, (1,), assumed_align=4\n )\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n\n compiled = cute.compile(\n GemvBf16Fp4Sm12x(splits=splits, enable_pdl=enable_pdl),\n a_fake,\n b_fake,\n sf_fake,\n c_fake,\n partial_fake,\n alpha_fake,\n stream_fake,\n options=\"--opt-level 2 --enable-tvm-ffi\",\n )\n\n _CUTE_DSL_MM_BF16_FP4_KERNEL_CACHE[cache_key] = compiled\n return compiled\n\n\ndef _e4m3_to_s0e5m3(sf_u8: torch.Tensor) -> torch.Tensor:\n \"\"\"Reformat a uint8 tensor of E4M3 scale bytes to S0E5M3 bytes.\n Used in cute-dsl backend for faster in-kernel scale decode.\n \"\"\"\n f16 = sf_u8.contiguous().view(torch.float8_e4m3fn).to(torch.float16)\n bits = f16.view(torch.int16).to(torch.int32) & 0xFFFF\n return ((bits >> 7) & 0xFF).to(torch.uint8)\n\n\n_CUTE_DSL_PACK_TILE_K: int = 16 # K-tile size = MMA K-block size\n_CUTE_DSL_PACK_TILE_N: int = 64 # N-tile size = kernel tile_N\n_CUTE_DSL_PACK_INTS_PER_TILE: int = 128 # int32s per (16K x 64N) repack block\n\n\ndef _cute_dsl_pack_fp4_weight(b: torch.Tensor) -> torch.Tensor:\n \"\"\"Repack a packed FP4 weight for the bf16 x fp4 cute-DSL kernel.\"\"\"\n if b.dtype != torch.uint8:\n b = b.view(torch.uint8)\n\n k_half, n = b.shape\n k = k_half * 2\n if k % _CUTE_DSL_PACK_TILE_K != 0:\n raise ValueError(f\"K must be a multiple of {_CUTE_DSL_PACK_TILE_K} (got K={k})\")\n if n % _CUTE_DSL_PACK_TILE_N != 0:\n raise ValueError(f\"N must be a multiple of {_CUTE_DSL_PACK_TILE_N} (got N={n})\")\n\n device = b.device\n k_tiles = k // _CUTE_DSL_PACK_TILE_K\n n_tiles = n // _CUTE_DSL_PACK_TILE_N\n k_half_per_tile = _CUTE_DSL_PACK_TILE_K // 2 # 8 packed K-rows per tile\n\n u32_pos = torch.arange(\n _CUTE_DSL_PACK_INTS_PER_TILE, device=device, dtype=torch.long\n )\n u32_idx_local = u32_pos % 2\n lane = (u32_pos // 2) % 32\n n_warp_idx = u32_pos // 64\n\n tc_col = lane // 4 # in [0, 8)\n tc_row_half = lane % 4 # tc_row = tc_row_half * 2 in {0, 2, 4, 6}\n base_n = n_warp_idx * 8 + tc_col # in [0, 16)\n\n byte_k_half_offset = torch.tensor([0, 4, 0, 4], device=device, dtype=torch.long)\n n_offset_stack = torch.tensor(\n [[0, 0, 16, 16], [32, 32, 48, 48]], device=device, dtype=torch.long\n )\n byte_n_offset = n_offset_stack[u32_idx_local] # (128, 4)\n\n # Source byte within the (8, 64) tile for each (u32_pos, byte_idx).\n k_half_in_tile = tc_row_half[:, None] + byte_k_half_offset[None, :] # (128, 4)\n n_in_tile = base_n[:, None] + byte_n_offset # (128, 4)\n within_idx = (k_half_in_tile * _CUTE_DSL_PACK_TILE_N + n_in_tile).reshape(\n -1\n ) # (512,) flat index into a row-major (8, 64) tile\n\n # (K/2, N) -> (K_tiles, 8, N_tiles, 64) -> (K_tiles, N_tiles, 8*64) so the\n # 512 source bytes of each tile are contiguous, then gather them in\n # (u32_pos, byte_idx) order.\n tile_bytes = (\n b.reshape(k_tiles, k_half_per_tile, n_tiles, _CUTE_DSL_PACK_TILE_N)\n .permute(0, 2, 1, 3)\n .reshape(k_tiles, n_tiles, k_half_per_tile * _CUTE_DSL_PACK_TILE_N)\n )\n gathered = tile_bytes[:, :, within_idx].reshape(\n k_tiles, n_tiles, _CUTE_DSL_PACK_INTS_PER_TILE, 4\n )\n\n # Each 4 consecutive bytes are one little-endian int32 (byte 0 = bits 0-7),\n # exactly what the kernel's 32-bit loads read -- reinterpret in place.\n return gathered.view(torch.int32).reshape(\n k_tiles, n_tiles * _CUTE_DSL_PACK_INTS_PER_TILE\n )\n\n\ndef _prepare_cute_dsl_sm12x(\n b: torch.Tensor,\n b_descale: torch.Tensor,\n alpha: Optional[torch.Tensor],\n block_size: int,\n) -> Tuple[torch.Tensor, torch.Tensor, Optional[torch.Tensor]]:\n \"\"\"cute-DSL-backend prep: repack the weight + unswizzle the SF.\n\n Produces the bespoke layout the cute-DSL kernel consumes:\n * weight: ``(K // 16, N * 2)`` int32 (see :func:`_cute_dsl_pack_fp4_weight`).\n * SF: ``(K // block_size, N)`` uint8 -- per-block scales reformatted to\n S0E5M3, the format the cute-DSL kernel decodes.\n ``alpha`` is passed through unchanged (the compute step normalizes it\n to a ``(1,) float32`` scalar). Pair the returned tensors with\n ``mm_bf16_fp4(a, b, b_descale, alpha, backend='cute-dsl')``.\n \"\"\"\n n = int(b.shape[0])\n k = int(b.shape[1]) * 2\n k_sf = k // block_size\n\n b_kn = b.t().contiguous()\n b_packed = _cute_dsl_pack_fp4_weight(b_kn) # (K//16, N*2) int32\n\n linear_sf = _unswizzle_sf_128x4(b_descale, n, k_sf) # (N, K_sf) uint8\n sf_ksf_n = linear_sf.t().contiguous() # (K_sf, N) uint8 (E4M3)\n sf_ksf_n = _e4m3_to_s0e5m3(sf_ksf_n) # -> S0E5M3\n return b_packed, sf_ksf_n, alpha\n\n\ndef _prepare_cute_dsl_sm100(\n b: torch.Tensor,\n b_descale: torch.Tensor,\n alpha: Optional[torch.Tensor],\n block_size: int,\n) -> Tuple[torch.Tensor, torch.Tensor, Optional[torch.Tensor]]:\n \"\"\"cute-DSL-backend prep: keep SF in swizzled layout.\n\n ``convert_sf_to_mma_layout`` only creates the six-dimensional strided view\n consumed by the SM100 TMA descriptor; it does not copy or linearize the\n canonical 128x4 scale-factor buffer.\n \"\"\"\n from ..cute_dsl.utils import convert_sf_to_mma_layout\n\n n = int(b.shape[0])\n k = int(b.shape[1]) * 2\n b_descale = b_descale.contiguous()\n weight_sf = convert_sf_to_mma_layout(\n b_descale,\n m=n,\n k=k,\n num_groups=1,\n sf_vec_size=block_size,\n )\n return b.contiguous(), weight_sf, alpha\n\n\ndef _prepare_cute_dsl(\n b: torch.Tensor,\n b_descale: torch.Tensor,\n alpha: Optional[torch.Tensor],\n block_size: int,\n) -> Tuple[torch.Tensor, torch.Tensor, Optional[torch.Tensor]]:\n \"\"\"Dispatch weight preparation to the architecture-specific DSL kernel.\"\"\"\n major, minor = get_compute_capability(b.device)\n if (major, minor) in ((10, 0), (10, 3)):\n return _prepare_cute_dsl_sm100(b, b_descale, alpha, block_size)\n elif major == 12:\n return _prepare_cute_dsl_sm12x(b, b_descale, alpha, block_size)\n else:\n raise NotImplementedError(\n f\"cute-dsl w4a16 GEMM only supports SM100/103 and SM12x; got {major}.{minor}\"\n )\n\n\n@functools.cache\ndef _bf16_fp4_cute_dsl_tactic_configs(\n n: int, k: int, sm_count: int\n) -> Tuple[\n Tuple[Tuple[int, int, int], Tuple[int, int, int], int, int, int, int, int, str],\n ...,\n]:\n \"\"\"Enumerate cute-DSL tactic configs for a given ``(N, K)``.\n\n Returns a tuple of ``(tile_shape_mnk, atom_layout, pipeline_depth,\n use_fp16_mma, tile_swizzle, k_splits, occupancy, kind)`` entries,\n where ``kind`` selects the kernel: ``\"mma\"`` (the dense GEMM, all\n fields live) or ``\"gemv\"`` (the m=1 streaming kernel, which only\n reads ``k_splits``). The gemv entries include device-derived splits,\n so a tactic index is only meaningful for the ``(n, k, sm_count)`` it\n was enumerated with.\n \"\"\"\n tile_k = 128 if k % 128 == 0 else 64\n\n # (tile_M, atom_layout) shapes the kernel is designed/validated for, at the\n # default tile_N=64; a tile_N=128 variant is added below for very large N.\n tile_m_atoms: List[Tuple[int, Tuple[int, int, int]]] = []\n if tile_k == 128:\n tile_m_atoms.append((16, (1, 2, 1)))\n tile_m_atoms.append((32, (2, 2, 1)))\n tile_m_atoms.append((64, (2, 2, 1)))\n\n configs: List[\n Tuple[Tuple[int, int, int], Tuple[int, int, int], int, int, int, int, int, str]\n ] = []\n seen = set()\n\n def add(tile_m, atom, pdepth, fp16, tile_n=64, tk=None, swz=1, splits=1, occ=1):\n cfg = (\n (tile_m, tile_n, tile_k if tk is None else tk),\n atom,\n pdepth,\n fp16,\n swz,\n splits,\n occ,\n \"mma\",\n )\n key = (cfg[0], cfg[1], pdepth, fp16, swz, splits, occ)\n if key not in seen:\n seen.add(key)\n configs.append(cfg)\n\n base_tile_m, base_atom = tile_m_atoms[0]\n add(base_tile_m, base_atom, 1, 1) # 0: baseline\n add(base_tile_m, base_atom, 0, 1) # no dequant prefetch (helps short-K)\n for tile_m, atom in tile_m_atoms[1:]:\n add(tile_m, atom, 1, 1)\n\n # Small-N grids underfill the GPU; offer them split-K variants.\n if n // 64 <= 256:\n k_tiles = k // tile_k\n for splits in (2, 4, 8):\n if splits <= k_tiles:\n add(base_tile_m, base_atom, 1, 1, splits=splits)\n\n # tile_N=128 halves the (m,n)-tile count but needs large wave count.\n if tile_k == 128 and n >= 12288 and n % 128 == 0:\n add(base_tile_m, base_atom, 1, 1, tile_n=128)\n\n # tile_K=64 has more ab stages, but requires larger problem size.\n if tile_k == 128 and n >= 8192:\n add(base_tile_m, base_atom, 1, 1, tile_n=64, tk=64)\n\n # tile_M=128 (taller M tile, atom (2,2,1)) -- the large-M *prefill* lever.\n if tile_k == 128:\n add(128, (2, 2, 1), 1, 1)\n\n # Threadblock swizzle (tile_swizzle=8) -- for large-M prefill.\n if tile_k == 128 and n * k >= 16 * 1024 * 1024:\n add(64, (2, 2, 1), 1, 1, swz=8)\n if tile_k == 128:\n add(128, (2, 2, 1), 1, 1, swz=8)\n\n # tile_N=128 (with tile_M=64, atom (2,2,1)) -- large shapes.\n if tile_k == 128 and n % 128 == 0 and n >= 4096:\n add(64, (2, 2, 1), 1, 1, tile_n=128, swz=8)\n add(64, (2, 2, 1), 1, 1, tile_n=128, swz=1)\n\n # occupancy=2: two co-resident CTAs per SM at half the ab_stage depth\n # (the kernel's occupancy note explains the trade). The 128-tile gate\n # fills two CTAs per SM on ~188-SM parts; 5080-class still qualifies.\n if tile_k == 128 and n // 64 >= 128:\n add(base_tile_m, base_atom, 1, 1, occ=2)\n add(base_tile_m, base_atom, 0, 1, occ=2)\n\n # occupancy=2 x split-K: grids too small to fill two CTAs per SM (the\n # down-proj class) get there by splitting K; the makespan gate decides\n # per device whether the pieces fit.\n if tile_k == 128 and n // 64 <= 256:\n k_tiles = k // tile_k\n for splits in (2, 4, 8):\n if splits <= k_tiles:\n add(base_tile_m, base_atom, 1, 1, splits=splits, occ=2)\n\n # occupancy=3: 9 resident warps per SM; needs the 2-stage epilogue to\n # keep 3 ab stages in SMEM (paired in _get_cute_dsl_bf16_fp4_gemm).\n if tile_k == 128 and n // 64 >= 128:\n add(base_tile_m, base_atom, 1, 1, occ=3)\n\n # Streaming GEMV for m=1 decode (SMEM-free, no tensor cores; see\n # GemvBf16Fp4Sm12x). splits shards K across grid.y for grid fill.\n if n % 64 == 0:\n k_tiles16 = k // 16\n gemv_splits = [s for s in (1, 2, 4, 8, 16, 32) if s * 4 <= k_tiles16]\n if gemv_splits:\n knee = _bf16_fp4_gemv_knee_split(n, k, sm_count)\n if knee not in gemv_splits:\n gemv_splits.append(knee)\n for splits in gemv_splits:\n configs.append(((1, 64, 16), (0, 0, 0), 0, 0, 1, splits, 1, \"gemv\"))\n\n return tuple(configs)\n\n\n_BF16_FP4_CUTE_DSL_TUNING_CONFIG = TuningConfig(\n dynamic_tensor_specs=(\n DynamicTensorSpec(\n (0,), # a_tensor_index\n (0,), # M dimension\n get_hybrid_num_tokens_buckets,\n map_to_hybrid_bucket_uncapped,\n ),\n ),\n constraint_specs=(\n ConstraintSpec(\n 5, # out_tensor_index follows M\n 0,\n lambda shapes: shapes[0][0],\n ),\n ),\n)\n\n\n_SM100_BF16_FP4_KERNEL_CACHE: Dict[Tuple, object] = {}\n\n_SM100_BF16_FP4_N_TILES = (8, 16, 32, 64, 128, 192)\n_SM100_BF16_FP4_K_TILE = 256\n\n\ndef _sm100_bf16_fp4_tactic_configs() -> List[Tuple]:\n \"\"\"Return the SM100 W4A16 tactics shared with the MoE GEMMs.\n\n Dense GEMM maps public output channels to the kernel M mode and public\n rows to its N mode. The 128x192x256 one-CTA tile is excluded because it\n cannot retain the two load and transform stages required by the kernel.\n \"\"\"\n tactics: List[Tuple] = []\n for route_tile in _SM100_BF16_FP4_N_TILES:\n for gemm_m, cluster_shape_mn in (\n (128, (1, 1)),\n (128, (2, 1)),\n (256, (2, 1)),\n ):\n if route_tile < 16 and gemm_m == 256:\n continue\n if route_tile == 192 and gemm_m == 128:\n continue\n for raster_along_m in (True, False):\n tactics.append(\n (\n (gemm_m, route_tile, _SM100_BF16_FP4_K_TILE),\n cluster_shape_mn,\n raster_along_m,\n )\n )\n return tactics\n\n\n_SM100_BF16_FP4_TACTICS = tuple(_sm100_bf16_fp4_tactic_configs())\n\n_SM100_BF16_FP4_CUTE_DSL_TUNING_CONFIG = TuningConfig(\n dynamic_tensor_specs=(\n DynamicTensorSpec(\n (0,), # a_tensor_index\n (0,), # public M dimension\n get_hybrid_num_tokens_buckets,\n map_to_hybrid_bucket_uncapped,\n ),\n ),\n constraint_specs=(\n ConstraintSpec(\n 5, # out_tensor_index follows public M\n 0,\n lambda shapes: shapes[0][0],\n ),\n ),\n)\n\n\ndef _get_sm100_bf16_fp4_kernel(\n weight_ptr,\n weight_sf_ptr,\n activation_ptr,\n alpha_ptr,\n output_ptr,\n n: int,\n m: int,\n k: int,\n max_active_clusters: int,\n stream,\n enable_pdl: bool,\n mma_tiler_mnk: Tuple[int, int, int],\n cluster_shape_mn: Tuple[int, int],\n raster_along_m: bool,\n):\n \"\"\"Compile the SM100/103 dense W4A16 kernel for one tactic.\"\"\"\n import cutlass\n import cutlass.cute as cute\n\n from .kernels.cute_dsl.dense_gemm_bf16_fp4_sm100 import (\n Sm100DenseGemmBf16Fp4Kernel,\n )\n\n use_2cta_instrs = mma_tiler_mnk[0] == 256\n transform_fragment_size = 128 if k == mma_tiler_mnk[2] else 32\n cache_key = (\n mma_tiler_mnk,\n cluster_shape_mn,\n bool(raster_along_m),\n transform_fragment_size,\n int(max_active_clusters),\n bool(enable_pdl),\n )\n compiled = _SM100_BF16_FP4_KERNEL_CACHE.get(cache_key)\n if compiled is not None:\n return compiled\n\n kernel = Sm100DenseGemmBf16Fp4Kernel(\n acc_dtype=cutlass.Float32,\n use_2cta_instrs=use_2cta_instrs,\n mma_tiler_mnk=mma_tiler_mnk,\n cluster_shape_mn=cluster_shape_mn,\n enable_pdl=enable_pdl,\n raster_along_m=raster_along_m,\n transform_fragment_size=transform_fragment_size,\n )\n compiled = cute.compile(\n kernel.wrapper,\n weight_ptr,\n weight_sf_ptr,\n activation_ptr,\n alpha_ptr,\n output_ptr,\n n,\n m,\n k,\n max_active_clusters=max_active_clusters,\n stream=stream,\n options=\"--opt-level 3 --enable-tvm-ffi\",\n )\n _SM100_BF16_FP4_KERNEL_CACHE[cache_key] = compiled\n return compiled\n\n\ndef _launch_cute_dsl_sm100(\n a: torch.Tensor,\n b: torch.Tensor,\n b_descale: torch.Tensor,\n alpha_for_launch: torch.Tensor,\n out: torch.Tensor,\n tactic: Tuple,\n enable_pdl: bool,\n) -> torch.Tensor:\n \"\"\"Compile, cache, and launch one SM100 W4A16 tactic.\"\"\"\n import cutlass\n import cutlass.cute as cute\n\n from ..cute_dsl.utils import current_cuda_stream, get_max_active_clusters, make_ptr\n\n m, k = map(int, a.shape)\n n = int(b.shape[0])\n mma_tiler_mnk, cluster_shape_mn, raster_along_m = tactic\n cluster_size = int(cluster_shape_mn[0]) * int(cluster_shape_mn[1])\n for name, tensor, align in (\n (\"b\", b, 32),\n (\"b_descale\", b_descale, 16),\n (\"a\", a, 32),\n (\"alpha\", alpha_for_launch, 16),\n (\"out\", out, 32),\n ):\n if tensor.data_ptr() % align:\n raise ValueError(\n f\"SM100 cute-dsl requires a {align}-byte aligned {name}; \"\n f\"got address {tensor.data_ptr():`#x`}. Pass a freshly \"\n \"allocated contiguous tensor.\"\n )\n stream = current_cuda_stream()\n weight_ptr = make_ptr(\n cutlass.Float4E2M1FN, b.data_ptr(), cute.AddressSpace.gmem, assumed_align=32\n )\n weight_sf_ptr = make_ptr(\n cutlass.Float8E4M3FN,\n b_descale.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n activation_ptr = make_ptr(\n cutlass.BFloat16,\n a.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=32,\n )\n alpha_ptr = make_ptr(\n cutlass.Float32,\n alpha_for_launch.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n output_ptr = make_ptr(\n cutlass.BFloat16, out.data_ptr(), cute.AddressSpace.gmem, assumed_align=32\n )\n max_active_clusters = get_max_active_clusters(cluster_size)\n compiled = _get_sm100_bf16_fp4_kernel(\n weight_ptr,\n weight_sf_ptr,\n activation_ptr,\n alpha_ptr,\n output_ptr,\n n,\n m,\n k,\n max_active_clusters,\n stream,\n enable_pdl,\n mma_tiler_mnk,\n cluster_shape_mn,\n raster_along_m,\n )\n compiled(\n b.data_ptr(),\n b_descale.data_ptr(),\n a.data_ptr(),\n alpha_for_launch.data_ptr(),\n out.data_ptr(),\n n,\n m,\n k,\n stream,\n )\n return out\n\n\ndef _cute_dsl_sm100_bf16_fp4_runner(enable_pdl: bool = True) -> TunableRunner:\n \"\"\"Build the tunable runner for the native-layout SM100 W4A16 GEMM.\"\"\"\n\n class CuteDslSm100Bf16Fp4Runner(TunableRunner):\n def get_cache_key_extras(self, inputs: List[torch.Tensor]) -> tuple:\n _, b, _, _, out_dtype, _, block_size = inputs\n n = int(b.shape[0])\n k = int(b.shape[1]) * 2\n return (out_dtype, n, k, int(block_size), bool(enable_pdl))\n\n def get_valid_tactics(\n self,\n inputs: List[torch.Tensor],\n profile: OptimizationProfile,\n ) -> List[Tuple]:\n import cutlass\n\n from .kernels.cute_dsl.dense_gemm_bf16_fp4_sm100 import (\n Sm100DenseGemmBf16Fp4Kernel,\n )\n\n a, b, _, _, _, _, _ = inputs\n m, k = map(int, a.shape)\n n = int(b.shape[0])\n valid_tactics: List[Tuple] = []\n for tactic in _SM100_BF16_FP4_TACTICS:\n mma_tiler_mnk, cluster_shape_mn, _ = tactic\n if Sm100DenseGemmBf16Fp4Kernel.can_implement(\n mnkl=(n, m, k, 1),\n a_dtype=cutlass.Float4E2M1FN,\n b_dtype=cutlass.BFloat16,\n c_dtype=cutlass.BFloat16,\n a_major=\"k\",\n b_major=\"k\",\n c_major=\"m\",\n mma_tiler=mma_tiler_mnk,\n cluster_shape_mn=cluster_shape_mn,\n use_2cta_instrs=mma_tiler_mnk[0] == 256,\n ):\n valid_tactics.append(tactic)\n return valid_tactics\n\n def forward(\n self,\n inputs: List[torch.Tensor],\n tactic=-1,\n do_preparation: bool = False,\n **kwargs,\n ) -> torch.Tensor:\n a, b, b_descale, alpha_for_launch, _, out, _ = inputs\n if tactic == -1:\n valid = self.get_valid_tactics(inputs, None)\n if valid:\n tactic = valid[0]\n else:\n m, k = map(int, a.shape)\n raise ValueError(\n \"no SM100 cute-dsl w4a16 tactic supports \"\n f\"m={m}, n={int(b.shape[0])}, k={k}\"\n )\n return _launch_cute_dsl_sm100(\n a,\n b,\n b_descale,\n alpha_for_launch,\n out,\n tactic,\n enable_pdl,\n )\n\n return CuteDslSm100Bf16Fp4Runner()\n\n\ndef _compute_cute_dsl_sm100(\n a: torch.Tensor,\n b: torch.Tensor,\n b_descale: torch.Tensor,\n alpha: Optional[torch.Tensor],\n out_dtype: torch.dtype,\n out: Optional[torch.Tensor],\n block_size: int,\n enable_pdl: bool,\n) -> torch.Tensor:\n \"\"\"Launch the SM100 native-layout NVFP4 x BF16 GEMM.\"\"\"\n if a.device != b.device or a.device != b_descale.device:\n raise ValueError(\n \"a, b, and b_descale must be on the same CUDA device; got \"\n f\"{a.device}, {b.device}, and {b_descale.device}.\"\n )\n if not a.is_contiguous() or not b.is_contiguous():\n raise ValueError(\"SM100 cute-dsl requires contiguous a and b tensors.\")\n if a.dtype != torch.bfloat16:\n raise TypeError(\n f\"SM100 cute-dsl currently requires a bfloat16 activation; got {a.dtype}.\"\n )\n if b.dtype != torch.uint8:\n raise TypeError(\n \"SM100 cute-dsl expects the uint8 NVFP4 weight returned by \"\n \"prepare_bf16_fp4_weights(..., backend='cute-dsl'); \"\n f\"got {b.dtype}.\"\n )\n if out_dtype != torch.bfloat16:\n raise NotImplementedError(\n f\"SM100 cute-dsl currently requires a bfloat16 output; got {out_dtype}.\"\n )\n\n m, k = map(int, a.shape)\n n = int(b.shape[0])\n if int(b.shape[1]) * 2 != k:\n raise ValueError(\n f\"a.shape[1]={k} but b.shape={tuple(b.shape)} encodes K=\"\n f\"{int(b.shape[1]) * 2}\"\n )\n if out is None:\n out = torch.empty((m, n), device=a.device, dtype=out_dtype)\n else:\n if tuple(out.shape) != (m, n):\n raise ValueError(f\"out shape {tuple(out.shape)} != expected {(m, n)}\")\n if out.dtype != out_dtype:\n raise TypeError(f\"out dtype {out.dtype} != requested out_dtype {out_dtype}\")\n if out.device != a.device or not out.is_contiguous():\n raise ValueError(\n \"out must be contiguous and on the same device as a; got \"\n f\"device={out.device}, contiguous={out.is_contiguous()}.\"\n )\n\n alpha_for_launch = _prepare_bf16_fp4_alpha(alpha, a.device)\n tuner = AutoTuner.get()\n runner = _cute_dsl_sm100_bf16_fp4_runner(enable_pdl=enable_pdl)\n inputs = [a, b, b_descale, alpha_for_launch, out_dtype, out, block_size]\n chosen_runner, tactic = tuner.choose_one(\n \"bf16_fp4_cute_dsl_sm100_gemm\",\n [runner],\n _SM100_BF16_FP4_CUTE_DSL_TUNING_CONFIG,\n inputs,\n )\n chosen_runner(inputs=inputs, tactic=tactic)\n return out\n\n\ndef _cute_dsl_bf16_fp4_runner(enable_pdl: bool = True) -> TunableRunner:\n \"\"\"Build a ``CuteDslBf16Fp4Runner`` for the cute-DSL bf16 x fp4 GEMM.\"\"\"\n\n class CuteDslBf16Fp4Runner(TunableRunner):\n def get_cache_key_extras(self, inputs: List[torch.Tensor]) -> tuple:\n a, b, _, _, out_dtype, _, block_size = inputs\n n = int(b.shape[1]) // 2\n k = int(b.shape[0]) * int(block_size)\n # The config list holds device-derived gemv splits, so a tuned\n # index must not replay on a different SM count.\n return (out_dtype, n, k, get_device_sm_count(a.device))\n\n def get_valid_tactics(\n self,\n inputs: List[torch.Tensor],\n profile: OptimizationProfile,\n ) -> List[int]:\n a, b, _, _, _, _, block_size = inputs\n n = int(b.shape[1]) // 2\n k = int(b.shape[0]) * int(block_size)\n m_opt = int(profile.get_opt_shapes()[0][0])\n sm_count = get_device_sm_count(a.device)\n # GEMV is validated only on SM12x; the autotuner ranks by time\n # and would not catch a wrong-but-fast kernel elsewhere.\n gemv_ok = get_compute_capability(a.device)[0] == 12\n configs = _bf16_fp4_cute_dsl_tactic_configs(n, k, sm_count)\n\n def split_reduces_makespan(cfg) -> bool:\n # Offer a split only if it shrinks the last wave >= 25%: the\n # autotuner's warm-cache timing hides the partials cost, so it\n # cannot reject bad splits itself.\n splits = cfg[5]\n if splits == 1:\n return True\n tile_m, tile_n, _ = cfg[0]\n tiles = (-(-m_opt // tile_m)) * (-(-n // tile_n))\n # occupancy multiplies the co-resident CTA slots per SM, so\n # occ2 x split-K fits 2x the pieces in one wave.\n slots = sm_count * cfg[6]\n base_waves = -(-tiles // sm_count)\n split_waves = (-(-tiles * splits // slots)) / splits\n return split_waves <= 0.75 * base_waves\n\n def gemv_valid(cfg) -> bool:\n # The m buckets round up, so only runtime m == 1 lands in\n # the m_opt == 1 bucket.\n if m_opt != 1 or not gemv_ok:\n return False\n warps_per_sm = (n // 64) * cfg[5] / sm_count\n return _GEMV_MIN_WARPS_PER_SM <= warps_per_sm <= _GEMV_MAX_WARPS_PER_SM\n\n return [\n i\n for i, cfg in enumerate(configs)\n if (\n gemv_valid(cfg) if cfg[7] == \"gemv\" else split_reduces_makespan(cfg)\n )\n ]\n\n def forward(\n self,\n inputs: List[torch.Tensor],\n tactic: int = -1,\n do_preparation: bool = False,\n **kwargs,\n ) -> torch.Tensor:\n a, b, b_sf_u8, alpha_for_launch, out_dtype, out, block_size = inputs\n n = int(b.shape[1]) // 2\n k = int(b.shape[0]) * int(block_size)\n m = int(a.shape[0])\n cfg = (\n _bf16_fp4_cute_dsl_tactic_configs(n, k, get_device_sm_count(a.device))[\n tactic\n ]\n if tactic >= 0\n else None\n )\n splits: Optional[int] = None\n if cfg is not None and cfg[7] == \"gemv\":\n if m != 1:\n raise ValueError(f\"the gemv tactic requires m == 1, got m={m}\")\n splits = cfg[5]\n elif cfg is None and m == 1 and not do_preparation:\n # Prep calls run outside the autotuner's per-tactic exception\n # guard; a gemv failure there would abort the whole op.\n splits = _select_bf16_fp4_gemv_split(\n n,\n k,\n get_compute_capability(a.device)[0],\n get_device_sm_count(a.device),\n )\n if splits is not None:\n compiled = _get_cute_dsl_bf16_fp4_gemv(\n splits, a.dtype, out_dtype, enable_pdl=enable_pdl\n )\n if splits > 1:\n partial = _get_cache_buf(\n \"mm_bf16_fp4_split_k_partial\",\n splits * m * n * 4,\n a.device,\n ).view(torch.float32)\n else:\n partial = _get_cache_buf(\n \"mm_bf16_fp4_split_k_partial_dummy\", 16, a.device\n ).view(torch.float32)\n compiled(a, b, b_sf_u8, out, partial, alpha_for_launch)\n return out\n if tactic < 0:\n # Fallback == pre-autotuner heuristic (M-aware), default knobs.\n tile_shape_mnk, atom_layout = _select_bf16_fp4_tile_shape(m, n, k)\n pipeline_depth, use_fp16_mma, tile_swizzle, occupancy = 1, 1, 1, 1\n k_splits = _select_bf16_fp4_k_splits(\n m, n, k, tile_shape_mnk, get_device_sm_count(a.device)\n )\n else:\n (\n tile_shape_mnk,\n atom_layout,\n pipeline_depth,\n use_fp16_mma,\n tile_swizzle,\n k_splits,\n occupancy,\n ) = cfg[:7]\n compiled = _get_cute_dsl_bf16_fp4_gemm(\n tile_shape_mnk,\n a.dtype,\n out_dtype,\n atom_layout,\n pipeline_depth,\n use_fp16_mma,\n enable_pdl=enable_pdl,\n tile_swizzle=tile_swizzle,\n k_splits=k_splits,\n occupancy=occupancy,\n )\n if k_splits > 1:\n if k_splits > k // tile_shape_mnk[2]:\n raise ValueError(\n f\"k_splits={k_splits} exceeds the K-tile count for \"\n f\"k={k}, tile_k={tile_shape_mnk[2]}\"\n )\n # The compiled call launches the reduce kernel as well, so\n # ``out`` is final on return.\n partial = _get_cache_buf(\n \"mm_bf16_fp4_split_k_partial\",\n k_splits * m * n * 4,\n a.device,\n ).view(torch.float32)\n else:\n partial = _get_cache_buf(\n \"mm_bf16_fp4_split_k_partial_dummy\", 16, a.device\n ).view(torch.float32)\n compiled(a, b, b_sf_u8, out, partial, alpha_for_launch)\n return out\n\n return CuteDslBf16Fp4Runner()\n\n\ndef _compute_cute_dsl(\n a: torch.Tensor,\n b: torch.Tensor,\n b_descale: torch.Tensor,\n alpha: Optional[torch.Tensor],\n out_dtype: torch.dtype,\n out: Optional[torch.Tensor],\n block_size: int,\n enable_pdl: bool = True,\n) -> torch.Tensor:\n \"\"\"Dispatch to the SM100/103 or SM12x compiled Blackwell kernel.\n\n SM100 consumes the native ``(N, K // 2)`` uint8 NVFP4 weight and 128x4 SF.\n\n SM12x consumes the packed ``(K // 16, N * 2)`` int32 weight and\n ``(K // block_size, N)`` uint8 SF in S0E5M3 format (reformatted from FP8-E4M3\n by :func:`_e4m3_to_s0e5m3`) returned by :func:`_prepare_cute_dsl`.\n \"\"\"\n if get_compute_capability(a.device) in ((10, 0), (10, 3)):\n return _compute_cute_dsl_sm100(\n a,\n b,\n b_descale,\n alpha,\n out_dtype,\n out,\n block_size,\n enable_pdl,\n )\n\n if b.dtype != torch.int32:\n raise TypeError(\n f\"cute-dsl backend expects the packed int32 weight from \"\n f\"prepare_bf16_fp4_weights(..., backend='cute-dsl'); got {b.dtype}.\"\n )\n if out_dtype != a.dtype:\n raise NotImplementedError(\n f\"cute-dsl backend requires out_dtype == a.dtype (got \"\n f\"out_dtype={out_dtype}, a.dtype={a.dtype}). Use the cudnn \"\n f\"backend for a mismatched output dtype.\"\n )\n k_tiles = int(b.shape[0])\n n = int(b.shape[1]) // 2\n k = k_tiles * block_size\n m = int(a.shape[0])\n if a.shape[1] != k:\n raise ValueError(\n f\"a.shape[1]={a.shape[1]} but k inferred from prepared b.shape=\"\n f\"{tuple(b.shape)} is {k}\"\n )\n\n if out is None:\n out = torch.empty((m, n), device=a.device, dtype=out_dtype)\n else:\n if tuple(out.shape) != (m, n):\n raise ValueError(f\"out shape {tuple(out.shape)} != expected {(m, n)}\")\n if out.dtype != out_dtype:\n raise TypeError(f\"out dtype {out.dtype} != requested out_dtype {out_dtype}\")\n\n b_sf_u8 = b_descale.view(torch.uint8).contiguous()\n alpha_for_launch = _prepare_bf16_fp4_alpha(alpha, a.device)\n\n tuner = AutoTuner.get()\n runner = _cute_dsl_bf16_fp4_runner(enable_pdl=enable_pdl)\n inputs = [a, b, b_sf_u8, alpha_for_launch, out_dtype, out, block_size]\n chosen_runner, tactic = tuner.choose_one(\n \"bf16_fp4_cute_dsl_gemm\",\n [runner],\n _BF16_FP4_CUTE_DSL_TUNING_CONFIG,\n inputs,\n )\n chosen_runner(inputs=inputs, tactic=tactic)\n return out\n"},"diff":{"kind":"string","value":"--- flashinfer/gemm/gemm_bf16_fp4_cute_dsl.py\n+++ flashinfer/gemm/gemm_bf16_fp4_cute_dsl.py\n@@ -606,7 +606,6 @@\n \n _SM100_BF16_FP4_N_TILES = (8, 16, 32, 64, 128, 192)\n _SM100_BF16_FP4_K_TILE = 256\n-_SM100_BF16_FP4_RASTER_ALONG_M = True\n \n \n def _sm100_bf16_fp4_tactic_configs() -> List[Tuple]:\n@@ -627,13 +626,14 @@\n continue\n if route_tile == 192 and gemm_m == 128:\n continue\n- tactics.append(\n- (\n- (gemm_m, route_tile, _SM100_BF16_FP4_K_TILE),\n- cluster_shape_mn,\n- _SM100_BF16_FP4_RASTER_ALONG_M,\n+ for raster_along_m in (True, False):\n+ tactics.append(\n+ (\n+ (gemm_m, route_tile, _SM100_BF16_FP4_K_TILE),\n+ cluster_shape_mn,\n+ raster_along_m,\n+ )\n )\n- )\n return tactics\n \n \n@@ -717,7 +717,7 @@\n k,\n max_active_clusters=max_active_clusters,\n stream=stream,\n- options=\"--opt-level 2 --enable-tvm-ffi\",\n+ options=\"--opt-level 3 --enable-tvm-ffi\",\n )\n _SM100_BF16_FP4_KERNEL_CACHE[cache_key] = compiled\n return compiled"},"lines_added":{"kind":"number","value":8,"string":"8"},"lines_removed":{"kind":"number","value":8,"string":"8"},"files_in_commit":{"kind":"number","value":1,"string":"1"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["B200","B300","SM100","SM103"],"string":"[\n \"B200\",\n \"B300\",\n \"SM100\",\n \"SM103\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":["8 x","1.0x","1.059962x","1.058944x","1.060623x","1.058814x","1.021585x","1.023894x","1.003731x","1.004513x"],"string":"[\n \"8 x\",\n \"1.0x\",\n \"1.059962x\",\n \"1.058944x\",\n \"1.060623x\",\n \"1.058814x\",\n \"1.021585x\",\n \"1.023894x\",\n \"1.003731x\",\n \"1.004513x\"\n]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cute_dsl kernel file from flashinfer (flashinfer/gemm/gemm_bf16_fp4_cute_dsl.py).\n\nGoal: perf(gemm): optimize CuTe DSL W4A16 dense GEMM\nTarget hardware: B200, B300, SM100, SM103\nTarget models: unspecified\n\nCurrent file:\n```python\n# SPDX-FileCopyrightText: Copyright (c) 2025 by FlashInfer team.\n# SPDX-License-Identifier: Apache-2.0\n\"\"\"Architecture-specific CuTe-DSL backend for the BF16 x NVFP4 GEMM.\"\"\"\n\nimport functools\nfrom typing import Dict, List, Optional, Tuple, cast\n\nimport torch\n\nfrom ..autotuner import (\n AutoTuner,\n ConstraintSpec,\n DynamicTensorSpec,\n OptimizationProfile,\n TunableRunner,\n TuningConfig,\n)\nfrom ..fused_moe.utils import (\n get_hybrid_num_tokens_buckets,\n map_to_hybrid_bucket_uncapped,\n)\nfrom ..utils import _get_cache_buf, get_compute_capability, get_device_sm_count\nfrom .gemm_base import _check_cute_dsl_availability\nfrom .gemm_bf16_fp4 import _unswizzle_sf_128x4\n\n_BF16_FP4_ALPHA_ONE_CACHE: dict = {}\n\n\ndef _prepare_bf16_fp4_alpha(\n alpha: Optional[torch.Tensor], device: torch.device\n) -> torch.Tensor:\n \"\"\"Normalize ``alpha`` to a ``(1,) float32`` tensor for the kernel.\"\"\"\n if alpha is None:\n cached = _BF16_FP4_ALPHA_ONE_CACHE.get(device)\n if cached is None:\n cached = torch.tensor([1.0], dtype=torch.float32, device=device)\n _BF16_FP4_ALPHA_ONE_CACHE[device] = cached\n return cached\n if alpha.dim() == 0:\n return alpha.to(device=device, dtype=torch.float32).unsqueeze(0)\n return alpha.to(device=device, dtype=torch.float32).reshape(1)\n\n\ndef _select_bf16_fp4_tile_shape(\n m: int, n: int, k: int\n) -> Tuple[Tuple[int, int, int], Tuple[int, int, int]]:\n \"\"\"Pick a CTA tile shape AND MMA atom_layout for the cute-DSL bf16 x fp4 kernel.\n\n Returns ``(tile_shape_mnk, atom_layout)``.\n\n Tile shape selection:\n tile_M choice\n * M <= 16 (and tile_K=128 path): use tile_M=16 with atom_layout\n (1,2,1). Halves wasted M-rows vs tile_M=32, and a 1-M-warp\n layout removes the duplicate dequant that (2,2,1) suffers from.\n * 16 < M <= 32: use tile_M=32 with atom_layout (2,2,1). Smaller\n MMA + epilogue waste than tile_M=64.\n * M > 32: use tile_M=64 with atom_layout (2,2,1) -- standard tile,\n more rows to amortize across.\n\n tile_K choice\n * K % 128 == 0: tile_K=128 (halves K-tile count and barrier\n overhead).\n * Otherwise: tile_K=64.\n\n Why atom_layout differs:\n * (2,2,1) (default for tile_M >= 32): 4 MMA warps as 2 M x 2 N --\n well-tested cute layout, but the 2 M-warps redundantly dequant\n the same B values into their own register files (~50% waste in\n dequant compute).\n * (1,2,1) (used for tile_M=16): 2 MMA warps as 1 M x 2 N -- no\n M-warp duplication. Permutation_m = 16, so tile_M must be 16.\n \"\"\"\n tile_k = 128 if k % 128 == 0 else 64\n if m <= 16 and tile_k == 128:\n return ((16, 64, 128), (1, 2, 1))\n if m <= 32:\n return ((32, 64, tile_k), (2, 2, 1))\n return ((64, 64, tile_k), (2, 2, 1))\n\n\ndef _select_bf16_fp4_k_splits(\n m: int, n: int, k: int, tile_shape_mnk: Tuple[int, int, int], sm_count: int\n) -> int:\n \"\"\"Static split-K pick for the no-autotune fallback: only clear-win\n underfill grids get a split, closer calls are left to the autotuner.\"\"\"\n tile_m, tile_n, tile_k = tile_shape_mnk\n if tile_m != (16 if tile_k == 128 else 32):\n # Split only the tile shapes that the tactic space pairs with splits.\n return 1\n tiles = -(-m // tile_m) * -(-n // tile_n)\n if tiles * 3 > sm_count:\n return 1\n k_tiles = k // tile_k\n for splits in (8, 4, 2):\n if splits <= k_tiles and tiles * splits <= sm_count:\n return splits\n return 1\n\n\n# Stream-GEMV residency window (warps/SM): below the floor DRAM latency is\n# uncovered, far above the ceiling splits just multiply partial traffic.\n_GEMV_MIN_WARPS_PER_SM = 12\n_GEMV_MAX_WARPS_PER_SM = 96\n\n\ndef _bf16_fp4_gemv_knee_split(n: int, k: int, sm_count: int) -> int:\n \"\"\"Smallest K-split reaching ~20 warps/SM, where throughput saturates\n and deeper splits only add partial traffic; capped under one full wave\n (6 CTAs/SM = 1536-thread limit / 256) and at >= 4 K-tiles per split.\"\"\"\n ctas = -(-(n // 64) // 8)\n cap = max(1, min(int(0.95 * sm_count * 6 / ctas), (k // 16) // 4))\n return min(-(-20 * sm_count // (n // 64)), cap)\n\n\ndef _select_bf16_fp4_gemv_split(\n n: int, k: int, cc_major: int, sm_count: int\n) -> Optional[int]:\n \"\"\"m=1 no-autotune fallback pick: the stream GEMV where it applies,\n ``None`` for the MMA heuristic. Serving stacks do not tune every\n shape (vLLM never tunes the logits GEMM), so untuned m=1 matters.\"\"\"\n if cc_major != 12 or n % 64 != 0 or k // 16 < 4:\n return None\n split = _bf16_fp4_gemv_knee_split(n, k, sm_count)\n warps_per_sm = (n // 64) * split / sm_count\n if not _GEMV_MIN_WARPS_PER_SM <= warps_per_sm <= _GEMV_MAX_WARPS_PER_SM:\n return None\n return split\n\n\n_CUTE_DSL_MM_BF16_FP4_KERNEL_CACHE: dict = {}\n\n\ndef _get_cute_dsl_bf16_fp4_gemm(\n tile_shape_mnk: Tuple[int, int, int],\n a_dtype: torch.dtype,\n c_dtype: torch.dtype,\n atom_layout: Tuple[int, int, int] = (2, 2, 1),\n pipeline_depth: int = 1,\n use_fp16_mma: int = 1,\n enable_pdl: bool = True,\n tile_swizzle: int = 1,\n k_splits: int = 1,\n occupancy: int = 1,\n):\n # Normalize to a tuple (callers may pass a list) so the cache key is hashable.\n atom_layout = cast(Tuple[int, int, int], tuple(atom_layout))\n pipeline_depth = int(pipeline_depth)\n use_fp16_mma = int(use_fp16_mma)\n enable_pdl = bool(enable_pdl)\n tile_swizzle = int(tile_swizzle)\n k_splits = int(k_splits)\n occupancy = int(occupancy)\n cache_key = (\n tile_shape_mnk,\n a_dtype,\n c_dtype,\n atom_layout,\n pipeline_depth,\n use_fp16_mma,\n enable_pdl,\n tile_swizzle,\n k_splits,\n occupancy,\n )\n cached = _CUTE_DSL_MM_BF16_FP4_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n return cached\n\n _check_cute_dsl_availability()\n\n import cutlass\n import cutlass.cute as cute\n from flashinfer.cute_dsl.utils import get_max_active_clusters\n\n from .kernels.cute_dsl.dense_gemm_bf16_fp4_sm12x import (\n Sm12xDenseGemmBf16Fp4Kernel,\n )\n\n from ..cute_dsl.utils import torch_to_cutlass_dtype\n\n a_cutlass_dtype = torch_to_cutlass_dtype(a_dtype)\n c_cutlass_dtype = torch_to_cutlass_dtype(c_dtype)\n\n sym_m = cute.sym_int()\n sym_k = cute.sym_int()\n sym_n = cute.sym_int()\n sym_k_tiles = cute.sym_int()\n sym_n_packed = cute.sym_int()\n\n a_fake = cute.runtime.make_fake_compact_tensor(\n a_cutlass_dtype, (sym_m, sym_k), stride_order=(1, 0), assumed_align=16\n )\n b_packed_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (sym_k_tiles, sym_n_packed),\n stride_order=(1, 0),\n assumed_align=16,\n )\n b_sf_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_k_tiles, sym_n), stride_order=(1, 0), assumed_align=16\n )\n c_fake = cute.runtime.make_fake_compact_tensor(\n c_cutlass_dtype, (sym_m, sym_n), stride_order=(1, 0), assumed_align=16\n )\n sym_partial = cute.sym_int()\n partial_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32, (sym_partial,), assumed_align=16\n )\n alpha_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32, (1,), assumed_align=4\n )\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n\n gemm = Sm12xDenseGemmBf16Fp4Kernel(\n acc_dtype=cutlass.Float32,\n tile_shape_mnk=tile_shape_mnk,\n atom_layout=atom_layout,\n # At occupancy 3 the SMEM budget per CTA only fits 2 ab stages next\n # to the default 4-stage epilogue; a 2-stage epilogue keeps 3.\n epi_stage=2 if occupancy >= 3 else 4,\n pipeline_depth=pipeline_depth,\n use_fp16_mma=use_fp16_mma,\n enable_pdl=enable_pdl,\n tile_swizzle=tile_swizzle,\n k_splits=k_splits,\n occupancy=occupancy,\n )\n # The persistent grid launches occupancy CTAs per SM; the kernel's stage\n # budget (_compute_stages) shrinks SMEM per CTA so they co-reside.\n max_active_clusters = get_max_active_clusters(1) * occupancy\n\n compiled = cute.compile(\n gemm.wrapper,\n a_fake,\n b_packed_fake,\n b_sf_fake,\n c_fake,\n partial_fake,\n alpha_fake,\n 1, # l (batch)\n max_active_clusters,\n stream_fake,\n options=\"--opt-level 2 --enable-tvm-ffi\",\n )\n\n _CUTE_DSL_MM_BF16_FP4_KERNEL_CACHE[cache_key] = compiled\n return compiled\n\n\ndef _get_cute_dsl_bf16_fp4_gemv(\n splits: int,\n a_dtype: torch.dtype,\n c_dtype: torch.dtype,\n enable_pdl: bool = True,\n):\n \"\"\"Compile-cache the m=1 streaming GEMV (same call signature as the\n compiled MMA kernel, so the runner dispatches either transparently).\"\"\"\n splits = int(splits)\n enable_pdl = bool(enable_pdl)\n cache_key = (\"gemv\", splits, a_dtype, c_dtype, enable_pdl)\n cached = _CUTE_DSL_MM_BF16_FP4_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n return cached\n\n _check_cute_dsl_availability()\n\n import cutlass\n import cutlass.cute as cute\n\n from .kernels.cute_dsl.gemv_bf16_fp4_sm12x import GemvBf16Fp4Sm12x\n\n from ..cute_dsl.utils import torch_to_cutlass_dtype\n\n sym = [cute.sym_int() for _ in range(6)]\n a_fake = cute.runtime.make_fake_compact_tensor(\n torch_to_cutlass_dtype(a_dtype),\n (sym[0], sym[1]),\n stride_order=(1, 0),\n assumed_align=16,\n )\n b_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (sym[2], sym[3]), stride_order=(1, 0), assumed_align=16\n )\n sf_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym[2], sym[4]), stride_order=(1, 0), assumed_align=16\n )\n c_fake = cute.runtime.make_fake_compact_tensor(\n torch_to_cutlass_dtype(c_dtype),\n (sym[0], sym[4]),\n stride_order=(1, 0),\n assumed_align=16,\n )\n partial_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32, (sym[5],), assumed_align=16\n )\n alpha_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32, (1,), assumed_align=4\n )\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n\n compiled = cute.compile(\n GemvBf16Fp4Sm12x(splits=splits, enable_pdl=enable_pdl),\n a_fake,\n b_fake,\n sf_fake,\n c_fake,\n partial_fake,\n alpha_fake,\n stream_fake,\n options=\"--opt-level 2 --enable-tvm-ffi\",\n )\n\n _CUTE_DSL_MM_BF16_FP4_KERNEL_CACHE[cache_key] = compiled\n return compiled\n\n\ndef _e4m3_to_s0e5m3(sf_u8: torch.Tensor) -> torch.Tensor:\n \"\"\"Reformat a uint8 tensor of E4M3 scale bytes to S0E5M3 bytes.\n Used in cute-dsl backend for faster in-kernel scale decode.\n \"\"\"\n f16 = sf_u8.contiguous().view(torch.float8_e4m3fn).to(torch.float16)\n bits = f16.view(torch.int16).to(torch.int32) & 0xFFFF\n return ((bits >> 7) & 0xFF).to(torch.uint8)\n\n\n_CUTE_DSL_PACK_TILE_K: int = 16 # K-tile size = MMA K-block size\n_CUTE_DSL_PACK_TILE_N: int = 64 # N-tile size = kernel tile_N\n_CUTE_DSL_PACK_INTS_PER_TILE: int = 128 # int32s per (16K x 64N) repack block\n\n\ndef _cute_dsl_pack_fp4_weight(b: torch.Tensor) -> torch.Tensor:\n \"\"\"Repack a packed FP4 weight for the bf16 x fp4 cute-DSL kernel.\"\"\"\n if b.dtype != torch.uint8:\n b = b.view(torch.uint8)\n\n k_half, n = b.shape\n k = k_half * 2\n if k % _CUTE_DSL_PACK_TILE_K != 0:\n raise ValueError(f\"K must be a multiple of {_CUTE_DSL_PACK_TILE_K} (got K={k})\")\n if n % _CUTE_DSL_PACK_TILE_N != 0:\n raise ValueError(f\"N must be a multiple of {_CUTE_DSL_PACK_TILE_N} (got N={n})\")\n\n device = b.device\n k_tiles = k // _CUTE_DSL_PACK_TILE_K\n n_tiles = n // _CUTE_DSL_PACK_TILE_N\n k_half_per_tile = _CUTE_DSL_PACK_TILE_K // 2 # 8 packed K-rows per tile\n\n u32_pos = torch.arange(\n _CUTE_DSL_PACK_INTS_PER_TILE, device=device, dtype=torch.long\n )\n u32_idx_local = u32_pos % 2\n lane = (u32_pos // 2) % 32\n n_warp_idx = u32_pos // 64\n\n tc_col = lane // 4 # in [0, 8)\n tc_row_half = lane % 4 # tc_row = tc_row_half * 2 in {0, 2, 4, 6}\n base_n = n_warp_idx * 8 + tc_col # in [0, 16)\n\n byte_k_half_offset = torch.tensor([0, 4, 0, 4], device=device, dtype=torch.long)\n n_offset_stack = torch.tensor(\n [[0, 0, 16, 16], [32, 32, 48, 48]], device=device, dtype=torch.long\n )\n byte_n_offset = n_offset_stack[u32_idx_local] # (128, 4)\n\n # Source byte within the (8, 64) tile for each (u32_pos, byte_idx).\n k_half_in_tile = tc_row_half[:, None] + byte_k_half_offset[None, :] # (128, 4)\n n_in_tile = base_n[:, None] + byte_n_offset # (128, 4)\n within_idx = (k_half_in_tile * _CUTE_DSL_PACK_TILE_N + n_in_tile).reshape(\n -1\n ) # (512,) flat index into a row-major (8, 64) tile\n\n # (K/2, N) -> (K_tiles, 8, N_tiles, 64) -> (K_tiles, N_tiles, 8*64) so the\n # 512 source bytes of each tile are contiguous, then gather them in\n # (u32_pos, byte_idx) order.\n tile_bytes = (\n b.reshape(k_tiles, k_half_per_tile, n_tiles, _CUTE_DSL_PACK_TILE_N)\n .permute(0, 2, 1, 3)\n .reshape(k_tiles, n_tiles, k_half_per_tile * _CUTE_DSL_PACK_TILE_N)\n )\n gathered = tile_bytes[:, :, within_idx].reshape(\n k_tiles, n_tiles, _CUTE_DSL_PACK_INTS_PER_TILE, 4\n )\n\n # Each 4 consecutive bytes are one little-endian int32 (byte 0 = bits 0-7),\n # exactly what the kernel's 32-bit loads read -- reinterpret in place.\n return gathered.view(torch.int32).reshape(\n k_tiles, n_tiles * _CUTE_DSL_PACK_INTS_PER_TILE\n )\n\n\ndef _prepare_cute_dsl_sm12x(\n b: torch.Tensor,\n b_descale: torch.Tensor,\n alpha: Optional[torch.Tensor],\n block_size: int,\n) -> Tuple[torch.Tensor, torch.Tensor, Optional[torch.Tensor]]:\n \"\"\"cute-DSL-backend prep: repack the weight + unswizzle the SF.\n\n Produces the bespoke layout the cute-DSL kernel consumes:\n * weight: ``(K // 16, N * 2)`` int32 (see :func:`_cute_dsl_pack_fp4_weight`).\n * SF: ``(K // block_size, N)`` uint8 -- per-block scales reformatted to\n S0E5M3, the format the cute-DSL kernel decodes.\n ``alpha`` is passed through unchanged (the compute step normalizes it\n to a ``(1,) float32`` scalar). Pair the returned tensors with\n ``mm_bf16_fp4(a, b, b_descale, alpha, backend='cute-dsl')``.\n \"\"\"\n n = int(b.shape[0])\n k = int(b.shape[1]) * 2\n k_sf = k // block_size\n\n b_kn = b.t().contiguous()\n b_packed = _cute_dsl_pack_fp4_weight(b_kn) # (K//16, N*2) int32\n\n linear_sf = _unswizzle_sf_128x4(b_descale, n, k_sf) # (N, K_sf) uint8\n sf_ksf_n = linear_sf.t().contiguous() # (K_sf, N) uint8 (E4M3)\n sf_ksf_n = _e4m3_to_s0e5m3(sf_ksf_n) # -> S0E5M3\n return b_packed, sf_ksf_n, alpha\n\n\ndef _prepare_cute_dsl_sm100(\n b: torch.Tensor,\n b_descale: torch.Tensor,\n alpha: Optional[torch.Tensor],\n block_size: int,\n) -> Tuple[torch.Tensor, torch.Tensor, Optional[torch.Tensor]]:\n \"\"\"cute-DSL-backend prep: keep SF in swizzled layout.\n\n ``convert_sf_to_mma_layout`` only creates the six-dimensional strided view\n consumed by the SM100 TMA descriptor; it does not copy or linearize the\n canonical 128x4 scale-factor buffer.\n \"\"\"\n from ..cute_dsl.utils import convert_sf_to_mma_layout\n\n n = int(b.shape[0])\n k = int(b.shape[1]) * 2\n b_descale = b_descale.contiguous()\n weight_sf = convert_sf_to_mma_layout(\n b_descale,\n m=n,\n k=k,\n num_groups=1,\n sf_vec_size=block_size,\n )\n return b.contiguous(), weight_sf, alpha\n\n\ndef _prepare_cute_dsl(\n b: torch.Tensor,\n b_descale: torch.Tensor,\n alpha: Optional[torch.Tensor],\n block_size: int,\n) -> Tuple[torch.Tensor, torch.Tensor, Optional[torch.Tensor]]:\n \"\"\"Dispatch weight preparation to the architecture-specific DSL kernel.\"\"\"\n major, minor = get_compute_capability(b.device)\n if (major, minor) in ((10, 0), (10, 3)):\n return _prepare_cute_dsl_sm100(b, b_descale, alpha, block_size)\n elif major == 12:\n return _prepare_cute_dsl_sm12x(b, b_descale, alpha, block_size)\n else:\n raise NotImplementedError(\n f\"cute-dsl w4a16 GEMM only supports SM100/103 and SM12x; got {major}.{minor}\"\n )\n\n\n@functools.cache\ndef _bf16_fp4_cute_dsl_tactic_configs(\n n: int, k: int, sm_count: int\n) -> Tuple[\n Tuple[Tuple[int, int, int], Tuple[int, int, int], int, int, int, int, int, str],\n ...,\n]:\n \"\"\"Enumerate cute-DSL tactic configs for a given ``(N, K)``.\n\n Returns a tuple of ``(tile_shape_mnk, atom_layout, pipeline_depth,\n use_fp16_mma, tile_swizzle, k_splits, occupancy, kind)`` entries,\n where ``kind`` selects the kernel: ``\"mma\"`` (the dense GEMM, all\n fields live) or ``\"gemv\"`` (the m=1 streaming kernel, which only\n reads ``k_splits``). The gemv entries include device-derived splits,\n so a tactic index is only meaningful for the ``(n, k, sm_count)`` it\n was enumerated with.\n \"\"\"\n tile_k = 128 if k % 128 == 0 else 64\n\n # (tile_M, atom_layout) shapes the kernel is designed/validated for, at the\n # default tile_N=64; a tile_N=128 variant is added below for very large N.\n tile_m_atoms: List[Tuple[int, Tuple[int, int, int]]] = []\n if tile_k == 128:\n tile_m_atoms.append((16, (1, 2, 1)))\n tile_m_atoms.append((32, (2, 2, 1)))\n tile_m_atoms.append((64, (2, 2, 1)))\n\n configs: List[\n Tuple[Tuple[int, int, int], Tuple[int, int, int], int, int, int, int, int, str]\n ] = []\n seen = set()\n\n def add(tile_m, atom, pdepth, fp16, tile_n=64, tk=None, swz=1, splits=1, occ=1):\n cfg = (\n (tile_m, tile_n, tile_k if tk is None else tk),\n atom,\n pdepth,\n fp16,\n swz,\n splits,\n occ,\n \"mma\",\n )\n key = (cfg[0], cfg[1], pdepth, fp16, swz, splits, occ)\n if key not in seen:\n seen.add(key)\n configs.append(cfg)\n\n base_tile_m, base_atom = tile_m_atoms[0]\n add(base_tile_m, base_atom, 1, 1) # 0: baseline\n add(base_tile_m, base_atom, 0, 1) # no dequant prefetch (helps short-K)\n for tile_m, atom in tile_m_atoms[1:]:\n add(tile_m, atom, 1, 1)\n\n # Small-N grids underfill the GPU; offer them split-K variants.\n if n // 64 <= 256:\n k_tiles = k // tile_k\n for splits in (2, 4, 8):\n if splits <= k_tiles:\n add(base_tile_m, base_atom, 1, 1, splits=splits)\n\n # tile_N=128 halves the (m,n)-tile count but needs large wave count.\n if tile_k == 128 and n >= 12288 and n % 128 == 0:\n add(base_tile_m, base_atom, 1, 1, tile_n=128)\n\n # tile_K=64 has more ab stages, but requires larger problem size.\n if tile_k == 128 and n >= 8192:\n add(base_tile_m, base_atom, 1, 1, tile_n=64, tk=64)\n\n # tile_M=128 (taller M tile, atom (2,2,1)) -- the large-M *prefill* lever.\n if tile_k == 128:\n add(128, (2, 2, 1), 1, 1)\n\n # Threadblock swizzle (tile_swizzle=8) -- for large-M prefill.\n if tile_k == 128 and n * k >= 16 * 1024 * 1024:\n add(64, (2, 2, 1), 1, 1, swz=8)\n if tile_k == 128:\n add(128, (2, 2, 1), 1, 1, swz=8)\n\n # tile_N=128 (with tile_M=64, atom (2,2,1)) -- large shapes.\n if tile_k == 128 and n % 128 == 0 and n >= 4096:\n add(64, (2, 2, 1), 1, 1, tile_n=128, swz=8)\n add(64, (2, 2, 1), 1, 1, tile_n=128, swz=1)\n\n # occupancy=2: two co-resident CTAs per SM at half the ab_stage depth\n # (the kernel's occupancy note explains the trade). The 128-tile gate\n # fills two CTAs per SM on ~188-SM parts; 5080-class still qualifies.\n if tile_k == 128 and n // 64 >= 128:\n add(base_tile_m, base_atom, 1, 1, occ=2)\n add(base_tile_m, base_atom, 0, 1, occ=2)\n\n # occupancy=2 x split-K: grids too small to fill two CTAs per SM (the\n # down-proj class) get there by splitting K; the makespan gate decides\n # per device whether the pieces fit.\n if tile_k == 128 and n // 64 <= 256:\n k_tiles = k // tile_k\n for splits in (2, 4, 8):\n if splits <= k_tiles:\n add(base_tile_m, base_atom, 1, 1, splits=splits, occ=2)\n\n # occupancy=3: 9 resident warps per SM; needs the 2-stage epilogue to\n # keep 3 ab stages in SMEM (paired in _get_cute_dsl_bf16_fp4_gemm).\n if tile_k == 128 and n // 64 >= 128:\n add(base_tile_m, base_atom, 1, 1, occ=3)\n\n # Streaming GEMV for m=1 decode (SMEM-free, no tensor cores; see\n # GemvBf16Fp4Sm12x). splits shards K across grid.y for grid fill.\n if n % 64 == 0:\n k_tiles16 = k // 16\n gemv_splits = [s for s in (1, 2, 4, 8, 16, 32) if s * 4 <= k_tiles16]\n if gemv_splits:\n knee = _bf16_fp4_gemv_knee_split(n, k, sm_count)\n if knee not in gemv_splits:\n gemv_splits.append(knee)\n for splits in gemv_splits:\n configs.append(((1, 64, 16), (0, 0, 0), 0, 0, 1, splits, 1, \"gemv\"))\n\n return tuple(configs)\n\n\n_BF16_FP4_CUTE_DSL_TUNING_CONFIG = TuningConfig(\n dynamic_tensor_specs=(\n DynamicTensorSpec(\n (0,), # a_tensor_index\n (0,), # M dimension\n get_hybrid_num_tokens_buckets,\n map_to_hybrid_bucket_uncapped,\n ),\n ),\n constraint_specs=(\n ConstraintSpec(\n 5, # out_tensor_index follows M\n 0,\n lambda shapes: shapes[0][0],\n ),\n ),\n)\n\n\n_SM100_BF16_FP4_KERNEL_CACHE: Dict[Tuple, object] = {}\n\n_SM100_BF16_FP4_N_TILES = (8, 16, 32, 64, 128, 192)\n_SM100_BF16_FP4_K_TILE = 256\n_SM100_BF16_FP4_RASTER_ALONG_M = True\n\n\ndef _sm100_bf16_fp4_tactic_configs() -> List[Tuple]:\n \"\"\"Return the SM100 W4A16 tactics shared with the MoE GEMMs.\n\n Dense GEMM maps public output channels to the kernel M mode and public\n rows to its N mode. The 128x192x256 one-CTA tile is excluded because it\n cannot retain the two load and transform stages required by the kernel.\n \"\"\"\n tactics: List[Tuple] = []\n for route_tile in _SM100_BF16_FP4_N_TILES:\n for gemm_m, cluster_shape_mn in (\n (128, (1, 1)),\n (128, (2, 1)),\n (256, (2, 1)),\n ):\n if route_tile < 16 and gemm_m == 256:\n continue\n if route_tile == 192 and gemm_m == 128:\n continue\n tactics.append(\n (\n (gemm_m, route_tile, _SM100_BF16_FP4_K_TILE),\n cluster_shape_mn,\n _SM100_BF16_FP4_RASTER_ALONG_M,\n )\n )\n return tactics\n\n\n_SM100_BF16_FP4_TACTICS = tuple(_sm100_bf16_fp4_tactic_configs())\n\n_SM100_BF16_FP4_CUTE_DSL_TUNING_CONFIG = TuningConfig(\n dynamic_tensor_specs=(\n DynamicTensorSpec(\n (0,), # a_tensor_index\n (0,), # public M dimension\n get_hybrid_num_tokens_buckets,\n map_to_hybrid_bucket_uncapped,\n ),\n ),\n constraint_specs=(\n ConstraintSpec(\n 5, # out_tensor_index follows public M\n 0,\n lambda shapes: shapes[0][0],\n ),\n ),\n)\n\n\ndef _get_sm100_bf16_fp4_kernel(\n weight_ptr,\n weight_sf_ptr,\n activation_ptr,\n alpha_ptr,\n output_ptr,\n n: int,\n m: int,\n k: int,\n max_active_clusters: int,\n stream,\n enable_pdl: bool,\n mma_tiler_mnk: Tuple[int, int, int],\n cluster_shape_mn: Tuple[int, int],\n raster_along_m: bool,\n):\n \"\"\"Compile the SM100/103 dense W4A16 kernel for one tactic.\"\"\"\n import cutlass\n import cutlass.cute as cute\n\n from .kernels.cute_dsl.dense_gemm_bf16_fp4_sm100 import (\n Sm100DenseGemmBf16Fp4Kernel,\n )\n\n use_2cta_instrs = mma_tiler_mnk[0] == 256\n transform_fragment_size = 128 if k == mma_tiler_mnk[2] else 32\n cache_key = (\n mma_tiler_mnk,\n cluster_shape_mn,\n bool(raster_along_m),\n transform_fragment_size,\n int(max_active_clusters),\n bool(enable_pdl),\n )\n compiled = _SM100_BF16_FP4_KERNEL_CACHE.get(cache_key)\n if compiled is not None:\n return compiled\n\n kernel = Sm100DenseGemmBf16Fp4Kernel(\n acc_dtype=cutlass.Float32,\n use_2cta_instrs=use_2cta_instrs,\n mma_tiler_mnk=mma_tiler_mnk,\n cluster_shape_mn=cluster_shape_mn,\n enable_pdl=enable_pdl,\n raster_along_m=raster_along_m,\n transform_fragment_size=transform_fragment_size,\n )\n compiled = cute.compile(\n kernel.wrapper,\n weight_ptr,\n weight_sf_ptr,\n activation_ptr,\n alpha_ptr,\n output_ptr,\n n,\n m,\n k,\n max_active_clusters=max_active_clusters,\n stream=stream,\n options=\"--opt-level 2 --enable-tvm-ffi\",\n )\n _SM100_BF16_FP4_KERNEL_CACHE[cache_key] = compiled\n return compiled\n\n\ndef _launch_cute_dsl_sm100(\n a: torch.Tensor,\n b: torch.Tensor,\n b_descale: torch.Tensor,\n alpha_for_launch: torch.Tensor,\n out: torch.Tensor,\n tactic: Tuple,\n enable_pdl: bool,\n) -> torch.Tensor:\n \"\"\"Compile, cache, and launch one SM100 W4A16 tactic.\"\"\"\n import cutlass\n import cutlass.cute as cute\n\n from ..cute_dsl.utils import current_cuda_stream, get_max_active_clusters, make_ptr\n\n m, k = map(int, a.shape)\n n = int(b.shape[0])\n mma_tiler_mnk, cluster_shape_mn, raster_along_m = tactic\n cluster_size = int(cluster_shape_mn[0]) * int(cluster_shape_mn[1])\n for name, tensor, align in (\n (\"b\", b, 32),\n (\"b_descale\", b_descale, 16),\n (\"a\", a, 32),\n (\"alpha\", alpha_for_launch, 16),\n (\"out\", out, 32),\n ):\n if tensor.data_ptr() % align:\n raise ValueError(\n f\"SM100 cute-dsl requires a {align}-byte aligned {name}; \"\n f\"got address {tensor.data_ptr():`#x`}. Pass a freshly \"\n \"allocated contiguous tensor.\"\n )\n stream = current_cuda_stream()\n weight_ptr = make_ptr(\n cutlass.Float4E2M1FN, b.data_ptr(), cute.AddressSpace.gmem, assumed_align=32\n )\n weight_sf_ptr = make_ptr(\n cutlass.Float8E4M3FN,\n b_descale.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n activation_ptr = make_ptr(\n cutlass.BFloat16,\n a.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=32,\n )\n alpha_ptr = make_ptr(\n cutlass.Float32,\n alpha_for_launch.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n output_ptr = make_ptr(\n cutlass.BFloat16, out.data_ptr(), cute.AddressSpace.gmem, assumed_align=32\n )\n max_active_clusters = get_max_active_clusters(cluster_size)\n compiled = _get_sm100_bf16_fp4_kernel(\n weight_ptr,\n weight_sf_ptr,\n activation_ptr,\n alpha_ptr,\n output_ptr,\n n,\n m,\n k,\n max_active_clusters,\n stream,\n enable_pdl,\n mma_tiler_mnk,\n cluster_shape_mn,\n raster_along_m,\n )\n compiled(\n b.data_ptr(),\n b_descale.data_ptr(),\n a.data_ptr(),\n alpha_for_launch.data_ptr(),\n out.data_ptr(),\n n,\n m,\n k,\n stream,\n )\n return out\n\n\ndef _cute_dsl_sm100_bf16_fp4_runner(enable_pdl: bool = True) -> TunableRunner:\n \"\"\"Build the tunable runner for the native-layout SM100 W4A16 GEMM.\"\"\"\n\n class CuteDslSm100Bf16Fp4Runner(TunableRunner):\n def get_cache_key_extras(self, inputs: List[torch.Tensor]) -> tuple:\n _, b, _, _, out_dtype, _, block_size = inputs\n n = int(b.shape[0])\n k = int(b.shape[1]) * 2\n return (out_dtype, n, k, int(block_size), bool(enable_pdl))\n\n def get_valid_tactics(\n self,\n inputs: List[torch.Tensor],\n profile: OptimizationProfile,\n ) -> List[Tuple]:\n import cutlass\n\n from .kernels.cute_dsl.dense_gemm_bf16_fp4_sm100 import (\n Sm100DenseGemmBf16Fp4Kernel,\n )\n\n a, b, _, _, _, _, _ = inputs\n m, k = map(int, a.shape)\n n = int(b.shape[0])\n valid_tactics: List[Tuple] = []\n for tactic in _SM100_BF16_FP4_TACTICS:\n mma_tiler_mnk, cluster_shape_mn, _ = tactic\n if Sm100DenseGemmBf16Fp4Kernel.can_implement(\n mnkl=(n, m, k, 1),\n a_dtype=cutlass.Float4E2M1FN,\n b_dtype=cutlass.BFloat16,\n c_dtype=cutlass.BFloat16,\n a_major=\"k\",\n b_major=\"k\",\n c_major=\"m\",\n mma_tiler=mma_tiler_mnk,\n cluster_shape_mn=cluster_shape_mn,\n use_2cta_instrs=mma_tiler_mnk[0] == 256,\n ):\n valid_tactics.append(tactic)\n return valid_tactics\n\n def forward(\n self,\n inputs: List[torch.Tensor],\n tactic=-1,\n do_preparation: bool = False,\n **kwargs,\n ) -> torch.Tensor:\n a, b, b_descale, alpha_for_launch, _, out, _ = inputs\n if tactic == -1:\n valid = self.get_valid_tactics(inputs, None)\n if valid:\n tactic = valid[0]\n else:\n m, k = map(int, a.shape)\n raise ValueError(\n \"no SM100 cute-dsl w4a16 tactic supports \"\n f\"m={m}, n={int(b.shape[0])}, k={k}\"\n )\n return _launch_cute_dsl_sm100(\n a,\n b,\n b_descale,\n alpha_for_launch,\n out,\n tactic,\n enable_pdl,\n )\n\n return CuteDslSm100Bf16Fp4Runner()\n\n\ndef _compute_cute_dsl_sm100(\n a: torch.Tensor,\n b: torch.Tensor,\n b_descale: torch.Tensor,\n alpha: Optional[torch.Tensor],\n out_dtype: torch.dtype,\n out: Optional[torch.Tensor],\n block_size: int,\n enable_pdl: bool,\n) -> torch.Tensor:\n \"\"\"Launch the SM100 native-layout NVFP4 x BF16 GEMM.\"\"\"\n if a.device != b.device or a.device != b_descale.device:\n raise ValueError(\n \"a, b, and b_descale must be on the same CUDA device; got \"\n f\"{a.device}, {b.device}, and {b_descale.device}.\"\n )\n if not a.is_contiguous() or not b.is_contiguous():\n raise ValueError(\"SM100 cute-dsl requires contiguous a and b tensors.\")\n if a.dtype != torch.bfloat16:\n raise TypeError(\n f\"SM100 cute-dsl currently requires a bfloat16 activation; got {a.dtype}.\"\n )\n if b.dtype != torch.uint8:\n raise TypeError(\n \"SM100 cute-dsl expects the uint8 NVFP4 weight returned by \"\n \"prepare_bf16_fp4_weights(..., backend='cute-dsl'); \"\n f\"got {b.dtype}.\"\n )\n if out_dtype != torch.bfloat16:\n raise NotImplementedError(\n f\"SM100 cute-dsl currently requires a bfloat16 output; got {out_dtype}.\"\n )\n\n m, k = map(int, a.shape)\n n = int(b.shape[0])\n if int(b.shape[1]) * 2 != k:\n raise ValueError(\n f\"a.shape[1]={k} but b.shape={tuple(b.shape)} encodes K=\"\n f\"{int(b.shape[1]) * 2}\"\n )\n if out is None:\n out = torch.empty((m, n), device=a.device, dtype=out_dtype)\n else:\n if tuple(out.shape) != (m, n):\n raise ValueError(f\"out shape {tuple(out.shape)} != expected {(m, n)}\")\n if out.dtype != out_dtype:\n raise TypeError(f\"out dtype {out.dtype} != requested out_dtype {out_dtype}\")\n if out.device != a.device or not out.is_contiguous():\n raise ValueError(\n \"out must be contiguous and on the same device as a; got \"\n f\"device={out.device}, contiguous={out.is_contiguous()}.\"\n )\n\n alpha_for_launch = _prepare_bf16_fp4_alpha(alpha, a.device)\n tuner = AutoTuner.get()\n runner = _cute_dsl_sm100_bf16_fp4_runner(enable_pdl=enable_pdl)\n inputs = [a, b, b_descale, alpha_for_launch, out_dtype, out, block_size]\n chosen_runner, tactic = tuner.choose_one(\n \"bf16_fp4_cute_dsl_sm100_gemm\",\n [runner],\n _SM100_BF16_FP4_CUTE_DSL_TUNING_CONFIG,\n inputs,\n )\n chosen_runner(inputs=inputs, tactic=tactic)\n return out\n\n\ndef _cute_dsl_bf16_fp4_runner(enable_pdl: bool = True) -> TunableRunner:\n \"\"\"Build a ``CuteDslBf16Fp4Runner`` for the cute-DSL bf16 x fp4 GEMM.\"\"\"\n\n class CuteDslBf16Fp4Runner(TunableRunner):\n def get_cache_key_extras(self, inputs: List[torch.Tensor]) -> tuple:\n a, b, _, _, out_dtype, _, block_size = inputs\n n = int(b.shape[1]) // 2\n k = int(b.shape[0]) * int(block_size)\n # The config list holds device-derived gemv splits, so a tuned\n # index must not replay on a different SM count.\n return (out_dtype, n, k, get_device_sm_count(a.device))\n\n def get_valid_tactics(\n self,\n inputs: List[torch.Tensor],\n profile: OptimizationProfile,\n ) -> List[int]:\n a, b, _, _, _, _, block_size = inputs\n n = int(b.shape[1]) // 2\n k = int(b.shape[0]) * int(block_size)\n m_opt = int(profile.get_opt_shapes()[0][0])\n sm_count = get_device_sm_count(a.device)\n # GEMV is validated only on SM12x; the autotuner ranks by time\n # and would not catch a wrong-but-fast kernel elsewhere.\n gemv_ok = get_compute_capability(a.device)[0] == 12\n configs = _bf16_fp4_cute_dsl_tactic_configs(n, k, sm_count)\n\n def split_reduces_makespan(cfg) -> bool:\n # Offer a split only if it shrinks the last wave >= 25%: the\n # autotuner's warm-cache timing hides the partials cost, so it\n # cannot reject bad splits itself.\n splits = cfg[5]\n if splits == 1:\n return True\n tile_m, tile_n, _ = cfg[0]\n tiles = (-(-m_opt // tile_m)) * (-(-n // tile_n))\n # occupancy multiplies the co-resident CTA slots per SM, so\n # occ2 x split-K fits 2x the pieces in one wave.\n slots = sm_count * cfg[6]\n base_waves = -(-tiles // sm_count)\n split_waves = (-(-tiles * splits // slots)) / splits\n return split_waves <= 0.75 * base_waves\n\n def gemv_valid(cfg) -> bool:\n # The m buckets round up, so only runtime m == 1 lands in\n # the m_opt == 1 bucket.\n if m_opt != 1 or not gemv_ok:\n return False\n warps_per_sm = (n // 64) * cfg[5] / sm_count\n return _GEMV_MIN_WARPS_PER_SM <= warps_per_sm <= _GEMV_MAX_WARPS_PER_SM\n\n return [\n i\n for i, cfg in enumerate(configs)\n if (\n gemv_valid(cfg) if cfg[7] == \"gemv\" else split_reduces_makespan(cfg)\n )\n ]\n\n def forward(\n self,\n inputs: List[torch.Tensor],\n tactic: int = -1,\n do_preparation: bool = False,\n **kwargs,\n ) -> torch.Tensor:\n a, b, b_sf_u8, alpha_for_launch, out_dtype, out, block_size = inputs\n n = int(b.shape[1]) // 2\n k = int(b.shape[0]) * int(block_size)\n m = int(a.shape[0])\n cfg = (\n _bf16_fp4_cute_dsl_tactic_configs(n, k, get_device_sm_count(a.device))[\n tactic\n ]\n if tactic >= 0\n else None\n )\n splits: Optional[int] = None\n if cfg is not None and cfg[7] == \"gemv\":\n if m != 1:\n raise ValueError(f\"the gemv tactic requires m == 1, got m={m}\")\n splits = cfg[5]\n elif cfg is None and m == 1 and not do_preparation:\n # Prep calls run outside the autotuner's per-tactic exception\n # guard; a gemv failure there would abort the whole op.\n splits = _select_bf16_fp4_gemv_split(\n n,\n k,\n get_compute_capability(a.device)[0],\n get_device_sm_count(a.device),\n )\n if splits is not None:\n compiled = _get_cute_dsl_bf16_fp4_gemv(\n splits, a.dtype, out_dtype, enable_pdl=enable_pdl\n )\n if splits > 1:\n partial = _get_cache_buf(\n \"mm_bf16_fp4_split_k_partial\",\n splits * m * n * 4,\n a.device,\n ).view(torch.float32)\n else:\n partial = _get_cache_buf(\n \"mm_bf16_fp4_split_k_partial_dummy\", 16, a.device\n ).view(torch.float32)\n compiled(a, b, b_sf_u8, out, partial, alpha_for_launch)\n return out\n if tactic < 0:\n # Fallback == pre-autotuner heuristic (M-aware), default knobs.\n tile_shape_mnk, atom_layout = _select_bf16_fp4_tile_shape(m, n, k)\n pipeline_depth, use_fp16_mma, tile_swizzle, occupancy = 1, 1, 1, 1\n k_splits = _select_bf16_fp4_k_splits(\n m, n, k, tile_shape_mnk, get_device_sm_count(a.device)\n )\n else:\n (\n tile_shape_mnk,\n atom_layout,\n pipeline_depth,\n use_fp16_mma,\n tile_swizzle,\n k_splits,\n occupancy,\n ) = cfg[:7]\n compiled = _get_cute_dsl_bf16_fp4_gemm(\n tile_shape_mnk,\n a.dtype,\n out_dtype,\n atom_layout,\n pipeline_depth,\n use_fp16_mma,\n enable_pdl=enable_pdl,\n tile_swizzle=tile_swizzle,\n k_splits=k_splits,\n occupancy=occupancy,\n )\n if k_splits > 1:\n if k_splits > k // tile_shape_mnk[2]:\n raise ValueError(\n f\"k_splits={k_splits} exceeds the K-tile count for \"\n f\"k={k}, tile_k={tile_shape_mnk[2]}\"\n )\n # The compiled call launches the reduce kernel as well, so\n # ``out`` is final on return.\n partial = _get_cache_buf(\n \"mm_bf16_fp4_split_k_partial\",\n k_splits * m * n * 4,\n a.device,\n ).view(torch.float32)\n else:\n partial = _get_cache_buf(\n \"mm_bf16_fp4_split_k_partial_dummy\", 16, a.device\n ).view(torch.float32)\n compiled(a, b, b_sf_u8, out, partial, alpha_for_launch)\n return out\n\n return CuteDslBf16Fp4Runner()\n\n\ndef _compute_cute_dsl(\n a: torch.Tensor,\n b: torch.Tensor,\n b_descale: torch.Tensor,\n alpha: Optional[torch.Tensor],\n out_dtype: torch.dtype,\n out: Optional[torch.Tensor],\n block_size: int,\n enable_pdl: bool = True,\n) -> torch.Tensor:\n \"\"\"Dispatch to the SM100/103 or SM12x compiled Blackwell kernel.\n\n SM100 consumes the native ``(N, K // 2)`` uint8 NVFP4 weight and 128x4 SF.\n\n SM12x consumes the packed ``(K // 16, N * 2)`` int32 weight and\n ``(K // block_size, N)`` uint8 SF in S0E5M3 format (reformatted from FP8-E4M3\n by :func:`_e4m3_to_s0e5m3`) returned by :func:`_prepare_cute_dsl`.\n \"\"\"\n if get_compute_capability(a.device) in ((10, 0), (10, 3)):\n return _compute_cute_dsl_sm100(\n a,\n b,\n b_descale,\n alpha,\n out_dtype,\n out,\n block_size,\n enable_pdl,\n )\n\n if b.dtype != torch.int32:\n raise TypeError(\n f\"cute-dsl backend expects the packed int32 weight from \"\n f\"prepare_bf16_fp4_weights(..., backend='cute-dsl'); got {b.dtype}.\"\n )\n if out_dtype != a.dtype:\n raise NotImplementedError(\n f\"cute-dsl backend requires out_dtype == a.dtype (got \"\n f\"out_dtype={out_dtype}, a.dtype={a.dtype}). Use the cudnn \"\n f\"backend for a mismatched output dtype.\"\n )\n k_tiles = int(b.shape[0])\n n = int(b.shape[1]) // 2\n k = k_tiles * block_size\n m = int(a.shape[0])\n if a.shape[1] != k:\n raise ValueError(\n f\"a.shape[1]={a.shape[1]} but k inferred from prepared b.shape=\"\n f\"{tuple(b.shape)} is {k}\"\n )\n\n if out is None:\n out = torch.empty((m, n), device=a.device, dtype=out_dtype)\n else:\n if tuple(out.shape) != (m, n):\n raise ValueError(f\"out shape {tuple(out.shape)} != expected {(m, n)}\")\n if out.dtype != out_dtype:\n raise TypeError(f\"out dtype {out.dtype} != requested out_dtype {out_dtype}\")\n\n b_sf_u8 = b_descale.view(torch.uint8).contiguous()\n alpha_for_launch = _prepare_bf16_fp4_alpha(alpha, a.device)\n\n tuner = AutoTuner.get()\n runner = _cute_dsl_bf16_fp4_runner(enable_pdl=enable_pdl)\n inputs = [a, b, b_sf_u8, alpha_for_launch, out_dtype, out, block_size]\n chosen_runner, tactic = tuner.choose_one(\n \"bf16_fp4_cute_dsl_gemm\",\n [runner],\n _BF16_FP4_CUTE_DSL_TUNING_CONFIG,\n inputs,\n )\n chosen_runner(inputs=inputs, tactic=tactic)\n return out\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\n@humansand\n\nThis optimizes the SM100/SM103 CuTe DSL dense W4A16 `mm_bf16_fp4` path added by #4466.\n\n- Compile the SM100/SM103 dense kernel at CuTe optimizer level 3 instead of its explicit level-2 override. SM12x compilation is unchanged.\n- Make raster direction a full autotune axis: every one of the 15 structural tile/cluster tactics now has both M-major and N-major variants, for a 30-tactic Cartesian product.\n\nThe final review diff is limited to `flashinfer/gemm/gemm_bf16_fp4_cute_dsl.py`. The fail-closed CUPTI evidence harness is retained in commit [`100e9527`](https://github.com/flashinfer-ai/flashinfer/commit/100e95275d55280c110c66e9a4693b07b86ff4d4), with its [orchestrator](https://github.com/flashinfer-ai/flashinfer/blob/100e95275d55280c110c66e9a4693b07b86ff4d4/benchmarks/bench_dense_w4a16_sm100.py) and [worker](https://github.com/flashinfer-ai/flashinfer/blob/100e95275d55280c110c66e9a4693b07b86ff4d4/benchmarks/bench_dense_w4a16_sm100_worker.py) intentionally absent from the final tree.\n\nThe dense kernel already retains the intended W4A16 architecture from the shared MoE design: the tensor-wide FP32 weight scale is applied to the FP32 accumulator in the epilogue, and the CTA uses two four-warp transform groups with the full 65,536-register allocation. This PR does not change those contracts, the public API, numerical ordering, warp specialization, or pipeline stages.\n\n## 🔍 Related Issues\n\n- Tracked in #4561\n- Follow-up to #4466\n\n## ⏱️ Performance\n\n### Environment and workload\n\n- Image: `nvcr.io/nvidia/pytorch:26.05-py3`\n- Devbox: `c2`, namespace `infra`, host `hu-pdx-117`; 8 x NVIDIA B300 SXM6 AC (SM103), measurements pinned to GPU 0\n- GPU 0: UUID `GPU-ee0843de-7ab2-7b46-8af4-1344b209180a`, 1100 W power limit, 2032 MHz maximum SM clock\n- Driver: `590.48.01`\n- Python: `3.12.3`\n- PyTorch: `2.12.0a0+5aff3928d8.nv26.05`\n- PyTorch CUDA / system nvcc: `13.2` / `13.2.78`\n- FlashInfer Python: `0.6.18` (editable checkout)\n- `nvidia-cutlass-dsl`: `4.7.0`\n- `cupti-python`: `13.2.0`; `nvidia-cuda-cupti`: `13.2.86`; `cuda-bindings`: `13.2.0`\n- Baseline: `fb28d7242b3506a2348265962041acc1fb56cca4`\n- Benchmarked candidate: `100e95275d55280c110c66e9a4693b07b86ff4d4`; benchmarked `flashinfer/gemm/gemm_bf16_fp4_cute_dsl.py` SHA-256 `befff9328ff028e7ca44603b39c35036a2d673ef982791ab0bd1cb714d0f4355`\n- Minimal review head: `693d10862df7a793f7dd9d500ddece28d536d9a0`; final `flashinfer/gemm/gemm_bf16_fp4_cute_dsl.py` SHA-256 `af8c20a81e472f4c30bb57d0f6f022f61452200079712bf5c3f82a2491141306`. The cleanup removes redundant Python constants/cache metadata and benchmark-only tree changes; it preserves O3 and the exact fresh-cache 30-tactic order.\n- Shapes: `(N,K)=(6656,19968)` and `(19968,6656)`, with `M=1,8,32,128,512,1024,2048,4096`\n\nThe first C1 B200 devbox was reclaimed during bring-up, and subsequent C1 requests could not get capacity. All retained measurements below are therefore from one C2 B300/SM103 GPU; the discarded C1 bring-up number is not mixed into the table.\n\n### Method\n\n- Same-node `A1 upstream O2 -> B candidate O3 + 30 raster tactics -> A2 upstream O2`, with the exact benchmarked candidate source between the two adjacent baseline arms.\n- Every shape and arm started a fresh worker process and a fresh shape-specific production autotune. This is required because `cupti.finalize()` is process-global teardown.\n- Weight construction/quantization, kernel compilation, autotuning, output allocation, and correctness checks were outside the timed region.\n- Timing used CUDA graph + PDL, cold L2, 5 warmups, and 30 CUPTI samples. The table reports the CUPTI median in microseconds.\n- `speedup = mean(A1, A2) / B`; values above `1.0x` are faster. Adjacent baseline drift is reported separately.\n- Every candidate worker passed finite-output, FP32 reference, eager repeatability, graph replay repeatability, and graph-versus-eager bitwise checks.\n\n### Raw CUPTI medians and derived speedups\n\n| Projection `(N,K)` | M | O2 A1 (us) | O3 + raster axis (us) | O2 A2 (us) | Speedup |\n|:--|--:|--:|--:|--:|--:|\n| down `(6656,19968)` | 1 | 57.441 | 54.176 | 57.409 | 1.059962x |\n| down `(6656,19968)` | 8 | 57.313 | 54.145 | 57.361 | 1.058944x |\n| down `(6656,19968)` | 32 | 57.840 | 54.497 | 57.761 | 1.060623x |\n| down `(6656,19968)` | 128 | 58.353 | 55.089 | 58.305 | 1.058814x |\n| down `(6656,19968)` | 512 | 120.001 | 117.489 | 120.049 | 1.021585x |\n| down `(6656,19968)` | 1024 | 178.994 | 174.754 | 178.866 | 1.023894x |\n| down `(6656,19968)` | 2048 | 290.643 | 289.411 | 290.339 | 1.003731x |\n| down `(6656,19968)` | 4096 | 589.478 | 586.886 | 589.590 | 1.004513x |\n| up `(19968,6656)` | 1 | 40.577 | 39.232 | 40.369 | 1.031620x |\n| up `(19968,6656)` | 8 | 40.560 | 38.977 | 40.544 | 1.040422x |\n| up `(19968,6656)` | 32 | 40.737 | 39.393 | 40.608 | 1.032493x |\n| up `(19968,6656)` | 128 | 45.601 | 45.792 | 45.697 | 0.996866x |\n| up `(19968,6656)` | 512 | 104.769 | 103.473 | 104.641 | 1.011906x |\n| up `(19968,6656)` | 1024 | 182.130 | 175.714 | 178.738 | 1.026859x |\n| up `(19968,6656)` | 2048 | 305.635 | 298.787 | 305.587 | 1.022839x |\n| up `(19968,6656)` | 4096 | 614.486 | 599.638 | 613.894 | 1.024268x |\n\nSummary:\n\n- 16-shape geometric-mean speedup: `1.029759x`.\n- Range: `0.996866x`--`1.060623x`; 15/16 shapes improved and 13/16 improved by more than 1%.\n- Production autotuning selected N-major raster in 11/16 rows and retained M-major in 5/16, so neither direction is a safe global constant.\n- The only slower row was up-projection M=128 at `0.996866x`, or 0.31% higher latency, below the predefined 1% noise threshold.\n- A2/A1 baseline ratios ranged from `0.981376x` to `1.002105x`. The up-projection M=1024 outlier came from an upstream autotuner switch from N128 to N192; the candidate was faster than both baseline arms (`1.0365x` and `1.0172x`). The other 15 baseline ratios stayed within 0.52% of one.\n\n### How much comes from O3?\n\nThe combined result should not be attributed entirely to O3 because production autotuning can select different structural tactics. Two isolated gates measured:\n\n- Fixed canonical tactic, eight rows spanning both projections and `M=1,128,1024,4096`: `1.0800x` geomean; a three-repeat down-projection M=128 sentinel measured `1.0985x`.\n- Production autotuning with the original structural search space, four rows:\n\n| Projection `(N,K)` | M | O3-only speedup |\n|:--|--:|--:|\n| down `(6656,19968)` | 128 | 1.050380x |\n| down `(6656,19968)` | 1024 | 1.019052x |\n| up `(19968,6656)` | 128 | 0.998767x |\n| up `(19968,6656)` | 1024 | 0.997945x |\n\nThe production-autotuned O3-only geomean was `1.016315x`. The expanded raster search supplies additional shape-dependent gains in the final 30-tactic result.\n\n### Autotuning cost\n\nThe Cartesian raster axis deliberately increases cold first-use tuning work. Across these 16 shapes, summed production-autotuner profile time was `417.83 s` for 30 tactics versus `196.68 s` for the screened 16-tactic space (`2.12x`). The final full-sweep orchestrator wall time was `548.61 s`. Persisted tactic-cache hits do not repeat this search cost, and the broader space was chosen to cover real workloads beyond these two projections.\n\n### Reproduction\n\nThe historical benchmark orchestrator records the command, environment, source hash, selected tactic, pipeline/register/TMEM configuration, correctness results, per-sample timings, and worker logs in its output directory. Auto-mode tactic caches are namespaced by compile level, transform-fragment configuration, and revision plus tracked-diff hash so an O2 or different-source winner cannot contaminate an O3 run.\n\nThe baselines require upstream's 15-tactic source, not merely `--compile-opt-level 2` on the candidate's 30-tactic source. The following creates a detached worktree at the benchmark commit, where both evidence scripts remain available, then runs exact upstream/candidate/upstream source in distinct output directories. It does not add the scripts back to the final PR tree.\n\n```bash\ncd /hai-workspace/flashinfer-dense-w4a16-perf/flashinfer\nset -euo pipefail\n\ntask_candidate=100e95275d55280c110c66e9a4693b07b86ff4d4\ntask_base=fb28d7242b3506a2348265962041acc1fb56cca4\ntask_worktree=/hai-workspace/flashinfer-pr4686-benchmark\ntask_source=flashinfer/gemm/gemm_bf16_fp4_cute_dsl.py\ntask_results=/hai-workspace/flashinfer-dense-w4a16-pr-repro\n\ngit fetch https://github.com/flashinfer-ai/flashinfer.git pull/4686/head\ntest ! -e \"$task_worktree\"\ngit worktree add --detach \"$task_worktree\" \"$task_candidate\"\ncd \"$task_worktree\"\n\ntest \"$(git rev-parse HEAD)\" = \"$task_candidate\"\ntest -z \"$(git status --porcelain --untracked-files=all)\"\ntest ! -e \"$task_results\"\ntrap 'git restore --source \"$task_candidate\" -- \"$task_source\"' EXIT\n\nrun_arm() {\n task_label=$1\n task_opt=$2\n CUDA_VISIBLE_DEVICES=0 /usr/bin/python \\\n benchmarks/bench_dense_w4a16_sm100.py \\\n --output-dir \"$task_results/$task_label\" \\\n --suite pr4466 --label \"$task_label\" \\\n --repeats 1 --warmup 5 --iters 30 \\\n --m-values 1,8,32,128,512,1024,2048,4096 \\\n --cases ffn_down_full,ffn_up_full \\\n --arms graph_pdl_on --tactic-mode auto \\\n --compile-opt-level \"$task_opt\" \\\n --input-cache-dir \"$task_results/input-cache\"\n}\n\ngit restore --source \"$task_base\" -- \"$task_source\"\nrun_arm a1-upstream-o2 2\n\ngit restore --source \"$task_candidate\" -- \"$task_source\"\nrun_arm b-candidate-o3-raster 3\n\ngit restore --source \"$task_base\" -- \"$task_source\"\nrun_arm a2-upstream-o2 2\n\ngit restore --source \"$task_candidate\" -- \"$task_source\"\ngit diff --exit-code\n```\n\nRaw summary artifact checksums:\n\n```text\n927e440b61c7d3c1fdd90fa324483a7b42006445c2e8fda06ae04035aaf65ad2 combined-full-aba/a2-upstream-o2/summary.json (A1)\n227d54299d603bd724d3a49feafc6b99aca8a8ddceb9d3d656a1caa25a15751d raster-full-axis/summary.json (B)\n72b8fc466bdcd89041f57120d5dd0c576988eaeefc8b2c6927893a98ed62a279 combined-full-aba/a3-upstream-o2/summary.json (A2)\n```\n\nThe first path retains its earlier experiment label; chronologically it is the upstream arm immediately before the final 30-tactic candidate. The newly collected `a3-upstream-o2` arm closes the final A/B/A sequence.\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [ ] All tests are passing (`unittest`, etc.).\n\nFull-suite validation was not run. Targeted validation used the final minimal 30-tactic source at `693d10862df7a793f7dd9d500ddece28d536d9a0` on the B300/SM103 environment above:\n\n```bash\nCUDA_VISIBLE_DEVICES=0 python -m pytest -vv -s \\\n 'tests/gemm/test_mm_bf16_fp4.py::test_backend_preallocated_out[cute-dsl]' \\\n tests/gemm/test_mm_bf16_fp4.py::test_cute_dsl_every_tactic_matches_reference\n```\n\n```text\n3 passed, 1308 warnings in 30.90s\n```\n\nBoth parameterizations of the every-tactic test ran, exercising all 30 final tactics. The warnings were existing CuTe DSL deprecation warnings; the run reported no failure.\n\nThe benchmark harness retained at `100e9527` also passed a fresh production-auto SM103 smoke (`M=1, N=6656, K=19968`, graph + PDL, CUPTI): correctness passed, N-major tactic index 21 was selected, and the median was `54.081 us`.\n\nLocal source checks:\n\n```bash\npre-commit install\npre-commit run --all-files\npython3 -m py_compile flashinfer/gemm/gemm_bf16_fp4_cute_dsl.py\ngit diff --check\n```\n\n```text\npre-commit run --all-files: all applicable hooks passed\npy_compile: exit 0\ngit diff --check: exit 0\n```\n\nBoth historical harness scripts were also compiled successfully at `100e9527` before their scope-only removal.\n\n## Reviewer Notes\n\nPlease focus on the O3 compile change and whether the full raster Cartesian product is the right production search-space tradeoff.\n\nLimitations and untested scope:\n\n- Final performance and GPU tests cover one B300/SM103 GPU. The final source was not measured on B200/SM100 after the C1 devbox was reclaimed.\n- Performance was measured at `100e9527`. The final cleanup head was correctness-tested on GPU and preserves O3 plus the exact fresh-cache tactic order, but the full A/B/A performance sweep was not repeated after the scope-only cleanup.\n- The 30-tactic space costs about 2.12x as much to tune cold as the screened 16-tactic space across this suite.\n- Existing persisted 15-tactic selections remain valid but can bypass discovery of N-major variants until that development cache is re-primed; all reported measurements used fresh per-shape caches.\n- One shape moved slightly slower, but by less than the predefined 1% noise threshold; no regression or speedup is claimed for that row.\n- End-to-end model throughput and shapes outside the stated matrix were not measured.\n- The full repository test suite was not run. Public GPU CI was requested but remains authorization-gated; internal CI was not requested.\n\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": \"B300\", \"model\": null, \"shape\": \"N=6656,K=19968\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 57.441, \"optimized\": 54.176, \"stated_speedup\": 1.059962, \"speedup\": 1.0603}, {\"scope\": \"kernel\", \"hardware\": \"B300\", \"model\": null, \"shape\": \"N=6656,K=19968\", \"batch_size\": 8, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 57.313, \"optimized\": 54.145, \"stated_speedup\": 1.058944, \"speedup\": 1.0585}, {\"scope\": \"kernel\", \"hardware\": \"B300\", \"model\": null, \"shape\": \"N=6656,K=19968\", \"batch_size\": 32, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 57.84, \"optimized\": 54.497, \"stated_speedup\": 1.060623, \"speedup\": 1.0613}, {\"scope\": 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\"speedup\": 1.0985}, {\"scope\": \"kernel\", \"hardware\": \"B300\", \"model\": null, \"shape\": \"N=6656,K=19968\", \"batch_size\": 128, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.05038, \"speedup\": 1.05038}, {\"scope\": \"kernel\", \"hardware\": \"B300\", \"model\": null, \"shape\": \"N=6656,K=19968\", \"batch_size\": 1024, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.019052, \"speedup\": 1.019052}, {\"scope\": \"kernel\", \"hardware\": \"B300\", \"model\": null, \"shape\": \"N=19968,K=6656\", \"batch_size\": 128, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 0.998767, \"speedup\": 0.998767}, {\"scope\": \"kernel\", \"hardware\": \"B300\", \"model\": null, \"shape\": \"N=19968,K=6656\", \"batch_size\": 1024, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 0.997945, \"speedup\": 0.997945}]"},"kernel_speedup":{"kind":"number","value":1.0248,"string":"1.0248"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1083,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"6cbe7f17da27e3b8e497b9569aa7d1159313132f"},"date":{"kind":"string","value":"2026-08-19T19:20:33-07:00"},"pr_number":{"kind":"number","value":4587,"string":"4,587"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/4587"},"title":{"kind":"string","value":"feat(cake_backend): accelerate DeepSeek fused routing (#4587)"},"message":{"kind":"string","value":"feat(cake_backend): accelerate DeepSeek fused routing (#4587)\n\n| Shape\n([#4254](https://github.com/flashinfer-ai/flashinfer/issues/4254)) |\nB200 Cake/FlashInfer | GB300 Cake/FlashInfer (original) |\nCake/Sonic-derived exact graph (B200 / GB300; upstream native exact API\nunsupported) |\n| --- | ---: | ---: | ---: |\n| T1 E384 k1 G1 kg1 f32/f32 | 1.1829x | 1.5522x | 7.6589x / 9.3881x |\n| T16 E256 k2 G8 kg2 f16/f16 | 1.1059x | 1.3919x | 14.4118x / 18.3243x |\n| replay T1 E256 k4 G8 kg4 bf16 | 1.0440x | 1.3158x | 14.6593x /\n18.7105x |\n| replay T7 E256 k1 G1 kg1 bf16 | 1.1974x | 1.5469x | 11.8684x /\n15.6094x |\n| replay T8 E256 k1 G1 kg1 bf16 | 1.1974x | 1.5469x | 12.2237x /\n15.9063x |\n| replay T32 E256 k1 G1 kg1 bf16 | 1.2101x | 1.5469x | 12.5064x /\n16.5156x |\n| replay T64 E256 k1 G1 kg1 bf16 | 1.1948x | 1.5294x | 12.3636x /\n15.4710x |\n| embedded T1 | 1.0194x | 1.3086x | 10.0325x / 13.8889x |\n| embedded T4096 | 1.0478x | 1.2665x | 6.0657x / 7.0574x |\n| sample T1024 | 1.0492x | 1.3670x | 11.6803x / 13.6789x |\n| boundary T1 E2 k1 G1 kg1 f16/bf16 PDL-off | 1.1299x | 1.4225x | N/A /\nN/A |\n| boundary T64 E128 k1 G1 kg1 bf16/f16 PDL-off | 1.1329x | 1.4615x |\n11.4131x / 14.4923x |\n| boundary T2 E4 k2 G2 kg1 f32/f16 | 1.1231x | 1.5738x | N/A / N/A |\n| boundary T32 E96 k5 G3 kg2 f16/bf16 | 1.0778x | 1.3590x | N/A / N/A |\n| boundary T7/R64 E256 k8 G8 kg4 bf16/f32 PDL-off | 1.0206x | 1.2771x |\n13.2887x / 17.0361x |\n\n| Source benchmark | Value |\n| --- | --- |\n| Contract | FP32 sigmoid; selection-only bias; group top-2/group-top-k;\nexpert top-k; normalization of selected unbiased sigmoid weights;\noptional caller-owned replay |\n| FlashInfer baseline / Cake candidate |\n`27a5a2945a2af3a4aaa0d1f659c6933d411bdfed` /\n`a3f87eb28565eb8361c9a57a0750c15f0cab5f0c` |\n| Timing | `loom.bench.bench_gpu_time`; CUPTI cold-L2; 50 ms warmup; 300\nms window; three rotated arm orders; one complete routing invocation |\n| B200 evidence | Slurm `3764856`; 15/15 correct and above 1.0x; SHA256\n`c51261cdd9851996be379b745f6b7c5d51e68f0df8598c68d929aa77a28c51ef` |\n| GB300 evidence | OCI AGA Slurm `514553`; 15/15 correct and above 1.0x;\nSHA256\n`5b4ec42980fa310335584b5322a9771e44876e5beaac526a40529bd28e06451a` |\n| Sonic-MoE | `7396f3e604827d8186c2e16e64b28ee33d3defd0`; native exact\nDeepSeek router 0/15; derived exact CUDA Graph 12/15 supported and\ncorrect on each architecture |\n| Compute Sanitizer | B200 PDL off/on; synccheck 0 errors; memcheck 0\nerrors; each report SHA256\n`c79dadfead541e1080b70be963a5a17bf687850ced3ef49023896d84a22baed4` |\n| Post-merge Cake source gate | Cake\n`d182e68b993d628b5e8b59e96284637e3363897e`; B200 source export/check\nSHA256\n`d1d2a9fdd042c3555bf23059ff37f5f99aaff352e11b58fc001a21936e1dc48c`; GPU\ne2e passed; registered CUPTI regression `1.031x` |\n\n| SGLang integration | Value |\n| --- | --- |\n| PR |\n[sgl-project/sglang#35479](https://github.com/sgl-project/sglang/pull/35479)\n|\n| SGLang / FlashInfer Cake | `002a0610ffe70d0c41c9b93f54cbd652a6fd7a80`\n/ `a3f87eb28565eb8361c9a57a0750c15f0cab5f0c` |\n| B200 routing tests | `python -m pytest -q\ntest/registered/kernels/ops/moe/test_fused_topk_deepseek.py`; 146 passed\n|\n| B200 synthetic E2E protocol | 24-layer DeepSeek-V3 routing shape\nE256/G8/kg4/k8; ABBA; 2 warmups + 5 samples per server; input lengths\n7/31/127 |\n| B200 synthetic correctness | exact output token IDs; output logprobs\npass `atol=1e-4`; baseline `selected_backend=default`; candidate\n`selected_backend=cake` |\n| B200 synthetic evidence | Slurm `3764856`; SHA256\n`55d673ec330854143ddd57e21bce681d158a7e49b4cbf2332f893d953604957c` |\n| GB300 real-model protocol | 4x NVIDIA GB300; DeepSeek-V3-0324\n`e9b33add`; TP4/EP4; ABBA=`default,Cake,Cake,default`; 200 official\nGSM8K test questions; five-shot; temperature 0; 128 fixed 512-in/128-out\nserving requests; concurrency 16 |\n| GB300 server command | `python -m sglang.launch_server --model-path\n<DeepSeek-V3-0324-e9b33add> --trust-remote-code --tp 4 --ep 4\n--moe-runner-backend deep_gemm --fp8-gemm-backend flashinfer_trtllm\n--disable-shared-experts-fusion --cuda-graph-backend-decode disabled\n--cuda-graph-backend-prefill disabled --disable-flashinfer-autotune\n--disable-radix-cache --chunked-prefill-size 4096 --context-length 4096\n--max-running-requests 16 --random-seed 12345` |\n| GB300 GSM8K command | `python benchmark/gsm8k/bench_sglang.py\n--backend srt --data-path <official-test.jsonl> --num-shots 5\n--num-questions 200 --max-new-tokens 512 --temperature 0 --top-p 1\n--parallel 16` |\n| GB300 serving command | `python -m sglang.benchmark.serving --backend\nsglang --dataset-name random-ids --num-prompts 128 --random-input-len\n512 --random-output-len 128 --random-range-ratio 1 --request-rate inf\n--max-concurrency 16 --seed 42` |\n| GB300 GSM8K accuracy | default `193/200, 193/200` (96.5% median); Cake\n`191/200, 191/200` (95.5% median); invalid `0/200` in every arm; paired\nMcNemar exact p=`0.754, 0.727` versus the first default arm |\n| GB300 route proof | both default arms launched only\n`deepseek_v3_topk_kernel`; both Cake arms launched only\n`kernel_cake_deepseek_routing_grouped_k8g4_f32_f32`; each launch audit\nhad exact expert IDs and routing weights within `atol=rtol=1e-4` |\n| GB300 real-model evidence | OCI AGA Slurm `514454`; SHA256\n`ad36974732243993c6d84a2a8ee3430b6e21e87979abaddefcc8b55eea33fc16` |\n\n| B200 synthetic SGLang metric (ABBA median) | b1 speedup | b16 speedup\n| b64 speedup |\n| --- | ---: | ---: | ---: |\n| Client wall / output throughput | 0.9970x | 1.0001x | 0.9972x |\n| Per-request E2E latency | 0.9969x | 0.9957x | 1.0255x |\n| TTFT | 0.9882x | 1.0107x | 1.0136x |\n| TPOT | 1.0012x | 1.0022x | 1.0956x |\n\n| GB300 real DeepSeek-V3 ABBA metric | default / Cake median | Cake\nspeedup |\n| --- | ---: | ---: |\n| GSM8K wall latency | 275.259 / 283.131 s | 0.9722x |\n| GSM8K output throughput | 71.734 / 71.115 token/s | 0.9914x |\n| Serving request throughput | 0.54063 / 0.54117 req/s | 1.0010x |\n| Serving output throughput | 69.2005 / 69.2693 token/s | 1.0010x |\n| Mean E2E latency | 28045.81 / 28029.82 ms | 1.0006x |\n| Mean TTFT | 2326.10 / 2335.58 ms | 0.9959x |\n| Mean TPOT | 202.517 / 202.317 ms | 1.0010x |\n\n---------\n\nCo-authored-by: Yingyi Huang <averyh@nvidia.com>\nCo-authored-by: Zihao Ye <zihaoy@nvidia.com>"},"path":{"kind":"string","value":"csrc/fused_moe/noAuxTcKernels.cu"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"#include <cooperative_groups.h>\n#include <cooperative_groups/reduce.h>\n\n#include <cmath>\n\n#include \"flashinfer/trtllm/fused_moe/noAuxTcKernels.h\"\n#include \"moeTopKFuncs.cuh\"\n#include \"tensorrt_llm/common/cudaTypeUtils.cuh\"\n#include \"tensorrt_llm/common/envUtils.h\"\n#include \"tvm_ffi_utils.h\"\n\nusing tvm::ffi::Optional;\n\nnamespace cg = cooperative_groups;\nusing namespace tensorrt_llm::common;\n\nnamespace tensorrt_llm::kernels {\nstatic constexpr int WARP_SIZE = 32;\nstatic constexpr int NumKimiK2Experts = 384;\nstatic constexpr int NumDeepseekExperts = 256;\nstatic constexpr int MaxNumExpertsUnit = 128;\nstatic constexpr int NumTopGroupScores = 2;\nstatic constexpr int MaxNumTopExperts = 8;\nstatic constexpr int MaxNumTopGroups = 4;\n\nstatic __device__ inline float sigmoid_accurate(float x) { return 0.5f * tanhf(0.5f * x) + 0.5f; }\n\ntemplate <typename InputT, typename BiasT, typename OutputT, typename IdxT, int MaxNumExperts,\n bool UseGroups>\n__global__ void deepseek_v3_topk_kernel(InputT* scores, OutputT* topkValues, IdxT* topkIndices,\n BiasT* routingBias, int64_t const numTokens,\n int64_t const numGroup, int64_t const topkGroup,\n int64_t const topk, int64_t const numExperts,\n int64_t const numExpertsPerGroup,\n double const routedScalingFactor,\n int16_t* routingReplayOut) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"griddepcontrol.wait;\");\n#endif\n\n // declare shared memory structure\n // number of experts is bounded by number of threads\n __shared__ float __attribute((aligned(128))) smemScoreSigmoid[MaxNumExperts];\n __shared__ float __attribute((aligned(128))) smemScoreBias[MaxNumExperts];\n // number of expert groups is bounded by number of warps\n int constexpr NumWarps = MaxNumExperts / WARP_SIZE;\n __shared__ float __attribute((aligned(128))) smemGroupScores[NumWarps];\n\n // needed for warp reduce\n auto block = cg::this_thread_block();\n auto warp = cg::tiled_partition<WARP_SIZE>(block);\n\n // for the final reduction of weight norm, only some lanes need to participate\n int32_t laneIdx = threadIdx.x % WARP_SIZE;\n int32_t warpIdx = __shfl_sync(0xffffffff, threadIdx.x / WARP_SIZE, 0);\n\n if constexpr (UseGroups) {\n if (warpIdx >= numGroup) {\n return;\n }\n }\n\n // note that for invalid scores, we simply use a negative value:\n // they work well even with the compacted format used in topK, and\n // sigmoid / bias activated scores cannot be negative\n static constexpr float invalidScoreFloat = float{-INFINITY};\n const OutputT invalidScore = OutputT{invalidScoreFloat};\n\n // load bias already; each warp represents one expert group\n auto threadExpert = threadIdx.x;\n bool expertSelected = threadExpert < numExperts;\n if constexpr (UseGroups) {\n threadExpert = warpIdx * numExpertsPerGroup + laneIdx;\n expertSelected = laneIdx < numExpertsPerGroup;\n }\n\n auto scoreIdx = int64_t{blockIdx.x} * int64_t{numExperts} + threadExpert;\n auto biasVal = expertSelected ? static_cast<float>(routingBias[threadExpert]) : invalidScoreFloat;\n topkValues += blockIdx.x * topk;\n topkIndices += blockIdx.x * topk;\n\n // get our assigned thread score; each warp represents one expert group\n float score = expertSelected ? static_cast<float>(scores[scoreIdx]) : invalidScoreFloat;\n auto scoreSigmoid = sigmoid_accurate(score);\n // write the sigmoid score to shared for later use\n if (expertSelected) {\n smemScoreSigmoid[threadExpert] = scoreSigmoid;\n }\n\n // get the score with bias\n // note that with invalid values, because sigmoid is < 1 and bias is -1,\n // we must get a negative value, which is smaller than any valid value\n auto scoreBias = float{scoreSigmoid + float{biasVal}};\n\n if (expertSelected) {\n smemScoreBias[threadExpert] = scoreBias;\n }\n\n // registers for top group score reduction\n float topExpGroupScores[NumTopGroupScores];\n [[maybe_unused]] int32_t topExpGroupIdx[NumTopGroupScores];\n float topGroups[MaxNumTopGroups]; // bound of numGroup\n int32_t topGroupIdx[MaxNumTopGroups];\n float expertScoreGroup[MaxNumTopGroups];\n int32_t expertIdxGroup[MaxNumTopGroups];\n float topScores[MaxNumTopExperts]; // bound of topk\n int32_t topExperts[MaxNumTopExperts];\n\n if constexpr (UseGroups) {\n reduce_topk::reduceTopK(warp, topExpGroupScores, topExpGroupIdx, scoreBias, threadExpert,\n /* minValue */ invalidScoreFloat);\n\n // get the final group score and write it to shared\n if (laneIdx == 0) {\n auto groupScore = topExpGroupScores[0] + topExpGroupScores[1];\n smemGroupScores[warpIdx] = groupScore;\n }\n }\n\n // make group scores available to all warps\n __syncthreads();\n\n if constexpr (UseGroups) {\n if (warpIdx == 0) {\n // a single warp performs the selection of top groups, and goes on to select the final experts\n float groupScore = laneIdx < numGroup ? smemGroupScores[laneIdx] : invalidScoreFloat;\n\n reduce_topk::reduceTopK(warp, topGroups, topGroupIdx, groupScore, laneIdx,\n /* minValue */ invalidScoreFloat);\n\n // final expert selection: get relevant indexes and scores from shared\n\n#pragma unroll\n for (int ii = 0; ii < MaxNumTopGroups; ++ii) { // bound of numGroup\n // auto groupIdx = topGroupIdx[ii];\n auto groupIdx = (ii < topkGroup) ? topGroupIdx[ii] : 0;\n expertIdxGroup[ii] = groupIdx * numExpertsPerGroup + laneIdx;\n\n expertScoreGroup[ii] = (ii < topkGroup) && expertSelected\n ? smemScoreBias[expertIdxGroup[ii]]\n : invalidScoreFloat;\n }\n\n tensorrt_llm::kernels::reduce_topk::reduceTopK(warp, topScores, topExperts, expertScoreGroup,\n expertIdxGroup,\n /* minValue */ invalidScoreFloat, topk);\n }\n } else if constexpr (MaxNumExperts > MaxNumExpertsUnit) {\n // without groups, and the expert number is larger than MaxNumExpertsUnit,\n // we need to use multiple warps to calculate the intermediate topk results\n\n int constexpr NumExpertWarps = (MaxNumExperts - 1) / MaxNumExpertsUnit + 1;\n int constexpr NumInterTopK = NumExpertWarps * MaxNumTopExperts;\n __shared__ float __attribute((aligned(128))) smemInterTopScores[NumInterTopK];\n __shared__ int32_t __attribute((aligned(128))) smemInterTopExperts[NumInterTopK];\n if (warpIdx < NumExpertWarps) {\n int offset = warpIdx * WARP_SIZE * MaxNumTopGroups;\n#pragma unroll\n for (int ii = 0; ii < MaxNumTopGroups; ++ii) {\n auto expertIdx = ii * WARP_SIZE + laneIdx;\n expertIdxGroup[ii] = offset + expertIdx;\n expertScoreGroup[ii] =\n offset + expertIdx < numExperts ? smemScoreBias[offset + expertIdx] : invalidScoreFloat;\n }\n reduce_topk::reduceTopK(warp, topScores, topExperts, expertScoreGroup, expertIdxGroup,\n /* minValue */ invalidScoreFloat, topk);\n\n if (laneIdx < topk) {\n smemInterTopScores[warpIdx * MaxNumTopExperts + laneIdx] = topScores[laneIdx];\n smemInterTopExperts[warpIdx * MaxNumTopExperts + laneIdx] = topExperts[laneIdx];\n }\n }\n __syncthreads();\n if (warpIdx == 0) {\n int constexpr NumInterTopKPerThread = (NumInterTopK * NumExpertWarps - 1) / WARP_SIZE + 1;\n float intermidiateScore[NumInterTopKPerThread];\n int32_t intermidiateExpert[NumInterTopKPerThread];\n for (int i = laneIdx; i < NumInterTopKPerThread * WARP_SIZE; i += WARP_SIZE) {\n int ii = i / WARP_SIZE;\n if (i < NumInterTopK) {\n intermidiateScore[ii] = smemInterTopScores[i];\n intermidiateExpert[ii] = smemInterTopExperts[i];\n } else {\n intermidiateScore[ii] = invalidScoreFloat;\n intermidiateExpert[ii] = MaxNumExperts - 1;\n }\n }\n reduce_topk::reduceTopK(warp, topScores, topExperts, intermidiateScore, intermidiateExpert,\n /* minValue */ invalidScoreFloat, topk);\n }\n } else {\n // without groups, and the expert number is smaller than MaxNumExpertsUnit\n // each thread just takes `MaxNumTopGroups` experts\n if (warpIdx == 0) {\n#pragma unroll\n for (int ii = 0; ii < MaxNumTopGroups; ++ii) {\n auto expertIdx = ii * WARP_SIZE + laneIdx;\n expertIdxGroup[ii] = expertIdx;\n expertScoreGroup[ii] =\n expertIdx < numExperts ? smemScoreBias[expertIdx] : invalidScoreFloat;\n }\n reduce_topk::reduceTopK(warp, topScores, topExperts, expertScoreGroup, expertIdxGroup,\n /* minValue */ invalidScoreFloat, topk);\n }\n }\n\n if (warpIdx == 0) {\n // determine our lane's expert index and write to output\n int32_t expertIdx = laneIdx < topk ? topExperts[laneIdx] : MaxNumExperts - 1;\n // norm the value\n float scoreNorm = laneIdx < topk ? smemScoreSigmoid[expertIdx] : 0.F;\n auto redNorm = cg::reduce(warp, scoreNorm, cg::plus<float>{});\n auto finalScore = static_cast<OutputT>(scoreNorm * routedScalingFactor / (redNorm + 1e-20));\n // store the topk scores and experts to output\n if (laneIdx < topk) {\n topkValues[laneIdx] = static_cast<OutputT>(finalScore);\n topkIndices[laneIdx] = expertIdx;\n // Routing replay: record selected expert IDs per token\n if (routingReplayOut != nullptr) {\n routingReplayOut[blockIdx.x * topk + laneIdx] = static_cast<int16_t>(expertIdx);\n }\n }\n }\n\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"griddepcontrol.launch_dependents;\");\n#endif\n}\n\ntemplate <typename InputT, typename BiasT, typename OutputT, typename IdxT>\nvoid invokeNoAuxTc(InputT* scores, BiasT* bias, OutputT* topk_values, IdxT* topk_indices,\n int64_t const num_tokens, int64_t const num_experts, int64_t const n_group,\n int64_t const topk_group, int64_t const topk, double const routed_scaling_factor,\n bool const launch_with_pdl, cudaStream_t const stream,\n int16_t* routing_replay_out) {\n // Check if we can use the optimized deepseek_v3_topk_kernel\n bool const is_single_group = (n_group == 1) && (num_experts <= NumKimiK2Experts);\n\n int64_t const experts_per_group = num_experts / n_group;\n bool const is_multi_group = (n_group != 1) && (num_experts <= NumDeepseekExperts) &&\n (experts_per_group <= WARP_SIZE) &&\n (experts_per_group * topk_group <= MaxNumExpertsUnit);\n\n if (is_single_group || is_multi_group) {\n cudaLaunchConfig_t config;\n auto* kernel_instance =\n &deepseek_v3_topk_kernel<InputT, BiasT, OutputT, IdxT, NumDeepseekExperts, true>;\n int num_threads = NumDeepseekExperts;\n if (is_single_group) {\n if (num_experts > MaxNumExpertsUnit) {\n kernel_instance =\n &deepseek_v3_topk_kernel<InputT, BiasT, OutputT, IdxT, NumKimiK2Experts, false>;\n num_threads = NumKimiK2Experts;\n } else {\n kernel_instance =\n &deepseek_v3_topk_kernel<InputT, BiasT, OutputT, IdxT, MaxNumExpertsUnit, false>;\n num_threads = MaxNumExpertsUnit;\n }\n }\n\n config.gridDim = num_tokens;\n config.blockDim = num_threads;\n config.dynamicSmemBytes = 0;\n config.stream = stream;\n cudaLaunchAttribute attrs[1];\n attrs[0].id = cudaLaunchAttributeProgrammaticStreamSerialization;\n attrs[0].val.programmaticStreamSerializationAllowed = launch_with_pdl;\n config.numAttrs = 1;\n config.attrs = attrs;\n\n cudaLaunchKernelEx(&config, kernel_instance, scores, topk_values, topk_indices, bias,\n num_tokens, n_group, topk_group, topk, num_experts, num_experts / n_group,\n routed_scaling_factor, routing_replay_out);\n sync_check_cuda_error(stream);\n } else {\n // TODO: call the generic path (previous implementation) or signal unsupported config.\n TLLM_CHECK_WITH_INFO(false,\n \"invokeNoAuxTc: unsupported configuration (n_group=%ld, num_experts=%ld, \"\n \"topk_group=%ld). Please use \"\n \"original pytorch implementation.\",\n n_group, num_experts, topk_group);\n }\n}\n\n#define INSTANTIATE_NOAUX_TC(InputT, BiasT, OutputT, IdxT) \\\n template void invokeNoAuxTc<InputT, BiasT, OutputT, IdxT>( \\\n InputT * scores, BiasT * bias, OutputT * topk_values, IdxT * topk_indices, \\\n int64_t const num_tokens, int64_t const num_experts, int64_t const n_group, \\\n int64_t const topk_group, int64_t const topk, double const routed_scaling_factor, \\\n bool const launch_with_pdl, cudaStream_t const stream, int16_t* routing_replay_out);\n\nINSTANTIATE_NOAUX_TC(float, float, float, int32_t);\nINSTANTIATE_NOAUX_TC(float, half, float, int32_t);\n\nINSTANTIATE_NOAUX_TC(half, float, half, int32_t);\nINSTANTIATE_NOAUX_TC(half, half, half, int32_t);\n\n#ifdef ENABLE_BF16\nINSTANTIATE_NOAUX_TC(float, __nv_bfloat16, float, int32_t);\nINSTANTIATE_NOAUX_TC(half, __nv_bfloat16, half, int32_t);\n\nINSTANTIATE_NOAUX_TC(__nv_bfloat16, __nv_bfloat16, __nv_bfloat16, int32_t);\nINSTANTIATE_NOAUX_TC(__nv_bfloat16, float, __nv_bfloat16, int32_t);\nINSTANTIATE_NOAUX_TC(__nv_bfloat16, half, __nv_bfloat16, int32_t);\n#endif\n\n} // namespace tensorrt_llm::kernels\n\nnamespace flashinfer::trtllm_dsv3_fused_routing {\n// th::Tensor const& scores, th::Tensor const& bias, int64_t n_group,\n// int64_t topk_group, int64_t topk, double routed_scaling_factor\n// th::Tensor topk_values, th::Tensor topk_indices\n\nvoid NoAuxTc(TensorView scores, TensorView bias, int64_t n_group, int64_t topk_group, int64_t topk,\n double routed_scaling_factor, TensorView topk_values, TensorView topk_indices,\n bool launch_with_pdl, Optional<TensorView> routing_replay_out) {\n auto data_type = scores.dtype();\n auto bias_type = bias.dtype();\n\n auto input_size = scores.sizes();\n int64_t num_tokens = input_size[0];\n int64_t num_experts = input_size[1];\n\n TVM_FFI_ICHECK(input_size.size() == 2) << \"scores must be a 2D Tensor\";\n TVM_FFI_ICHECK((scores.device().device_type == kDLCUDA) && (bias.device().device_type == kDLCUDA))\n << \"scores and bias must be CUDA tensors\";\n TVM_FFI_ICHECK(scores.device().device_id == bias.device().device_id)\n << \"scores and bias must be on the same device\";\n TVM_FFI_ICHECK(bias.dim() == 1 && bias.numel() == num_experts)\n << \"bias must be 1D with length == number of experts (%ld)\";\n TVM_FFI_ICHECK(num_experts % n_group == 0) << \"num_experts should be divisible by n_group\";\n TVM_FFI_ICHECK(n_group <= 32)\n << \"n_group should be smaller than or equal to 32 for now\"; //@todo: remove this restriction\n // later\n TVM_FFI_ICHECK(topk <= 32)\n << \"topk should be smaller than or equal to 32 for now\"; //@todo: remove this restriction\n // later\n TVM_FFI_ICHECK(topk_values.dim() == 2) << \"topk_values must be a 2D Tensor\";\n TVM_FFI_ICHECK(topk_indices.dim() == 2) << \"topk_indices must be a 2D Tensor\";\n TVM_FFI_ICHECK(topk_values.sizes()[0] == num_tokens)\n << \"topk_values must have the same number of tokens as scores\";\n TVM_FFI_ICHECK(topk_indices.sizes()[0] == num_tokens)\n << \"topk_indices must have the same number of tokens as scores\";\n TVM_FFI_ICHECK(topk_values.sizes()[1] == topk)\n << \"topk_values must have the same number of topk as scores\";\n TVM_FFI_ICHECK(topk_indices.sizes()[1] == topk)\n << \"topk_indices must have the same number of topk as scores\";\n TVM_FFI_ICHECK(topk_values.dtype() == data_type)\n << \"topk_values must have the same dtype as scores\";\n TVM_FFI_ICHECK(encode_dlpack_dtype(topk_indices.dtype()) == int32_code)\n << \"topk_indices must be int32 dtype\";\n\n // Validate and extract routing_replay_out\n // NOTE: dim0 >= num_tokens is intentionally NOT checked — with CUDA graphs the buffer\n // is pre-allocated at maximum batch size and reused across steps with varying num_tokens.\n // The kernel only writes to indices [0, num_tokens), so a larger buffer is safe.\n constexpr int64_t int16_code_val = encode_dlpack_dtype(DLDataType{kDLInt, 16, 1});\n int16_t* replay_ptr = nullptr;\n if (routing_replay_out.has_value()) {\n auto replay = routing_replay_out.value();\n TVM_FFI_ICHECK(replay.device().device_type == kDLCUDA)\n << \"routing_replay_out must be a CUDA tensor\";\n TVM_FFI_ICHECK(replay.device().device_id == scores.device().device_id)\n << \"routing_replay_out must be on the same device as scores\";\n TVM_FFI_ICHECK(replay.ndim() == 2)\n << \"routing_replay_out must be a 2D Tensor [num_tokens, topk]\";\n TVM_FFI_ICHECK(replay.sizes()[1] == topk) << \"routing_replay_out dim1 must equal topk\";\n TVM_FFI_ICHECK(encode_dlpack_dtype(replay.dtype()) == int16_code_val)\n << \"routing_replay_out must be int16 dtype\";\n replay_ptr = reinterpret_cast<int16_t*>(replay.data_ptr());\n }\n\n auto stream = get_stream(scores.device());\n using namespace tensorrt_llm::kernels;\n switch (encode_dlpack_dtype(data_type)) {\n case float16_code:\n // Handle Float16\n switch (encode_dlpack_dtype(bias_type)) {\n case float16_code:\n invokeNoAuxTc<half, half, half, int32_t>(\n reinterpret_cast<half*>(scores.data_ptr()), reinterpret_cast<half*>(bias.data_ptr()),\n reinterpret_cast<half*>(topk_values.data_ptr()),\n reinterpret_cast<int32_t*>(topk_indices.data_ptr()), num_tokens, num_experts, n_group,\n topk_group, topk, routed_scaling_factor, launch_with_pdl, stream, replay_ptr);\n break;\n case float32_code:\n invokeNoAuxTc<half, float, half, int32_t>(\n reinterpret_cast<half*>(scores.data_ptr()), reinterpret_cast<float*>(bias.data_ptr()),\n reinterpret_cast<half*>(topk_values.data_ptr()),\n reinterpret_cast<int32_t*>(topk_indices.data_ptr()), num_tokens, num_experts, n_group,\n topk_group, topk, routed_scaling_factor, launch_with_pdl, stream, replay_ptr);\n break;\n case bfloat16_code:\n invokeNoAuxTc<half, __nv_bfloat16, half, int32_t>(\n reinterpret_cast<half*>(scores.data_ptr()),\n reinterpret_cast<__nv_bfloat16*>(bias.data_ptr()),\n reinterpret_cast<half*>(topk_values.data_ptr()),\n reinterpret_cast<int32_t*>(topk_indices.data_ptr()), num_tokens, num_experts, n_group,\n topk_group, topk, routed_scaling_factor, launch_with_pdl, stream, replay_ptr);\n break;\n default:\n throw std::invalid_argument(\n \"Invalid bias dtype, only supports float16, float32, and bfloat16\");\n break;\n }\n break;\n case float32_code:\n switch (encode_dlpack_dtype(bias_type)) {\n case float32_code:\n invokeNoAuxTc<float, float, float, int32_t>(\n reinterpret_cast<float*>(scores.data_ptr()),\n reinterpret_cast<float*>(bias.data_ptr()),\n reinterpret_cast<float*>(topk_values.data_ptr()),\n reinterpret_cast<int32_t*>(topk_indices.data_ptr()), num_tokens, num_experts, n_group,\n topk_group, topk, routed_scaling_factor, launch_with_pdl, stream, replay_ptr);\n break;\n case float16_code:\n invokeNoAuxTc<float, half, float, int32_t>(\n reinterpret_cast<float*>(scores.data_ptr()), reinterpret_cast<half*>(bias.data_ptr()),\n reinterpret_cast<float*>(topk_values.data_ptr()),\n reinterpret_cast<int32_t*>(topk_indices.data_ptr()), num_tokens, num_experts, n_group,\n topk_group, topk, routed_scaling_factor, launch_with_pdl, stream, replay_ptr);\n break;\n case bfloat16_code:\n invokeNoAuxTc<float, __nv_bfloat16, float, int32_t>(\n reinterpret_cast<float*>(scores.data_ptr()),\n reinterpret_cast<__nv_bfloat16*>(bias.data_ptr()),\n reinterpret_cast<float*>(topk_values.data_ptr()),\n reinterpret_cast<int32_t*>(topk_indices.data_ptr()), num_tokens, num_experts, n_group,\n topk_group, topk, routed_scaling_factor, launch_with_pdl, stream, replay_ptr);\n break;\n default:\n throw std::invalid_argument(\n \"Invalid bias dtype, only supports float16, float32, and bfloat16\");\n break;\n }\n break;\n case bfloat16_code:\n // Handle BFloat16\n switch (encode_dlpack_dtype(bias_type)) {\n case bfloat16_code:\n invokeNoAuxTc<__nv_bfloat16, __nv_bfloat16, __nv_bfloat16, int32_t>(\n reinterpret_cast<__nv_bfloat16*>(scores.data_ptr()),\n reinterpret_cast<__nv_bfloat16*>(bias.data_ptr()),\n reinterpret_cast<__nv_bfloat16*>(topk_values.data_ptr()),\n reinterpret_cast<int32_t*>(topk_indices.data_ptr()), num_tokens, num_experts, n_group,\n topk_group, topk, routed_scaling_factor, launch_with_pdl, stream, replay_ptr);\n break;\n case float16_code:\n invokeNoAuxTc<__nv_bfloat16, half, __nv_bfloat16, int32_t>(\n reinterpret_cast<__nv_bfloat16*>(scores.data_ptr()),\n reinterpret_cast<half*>(bias.data_ptr()),\n reinterpret_cast<__nv_bfloat16*>(topk_values.data_ptr()),\n reinterpret_cast<int32_t*>(topk_indices.data_ptr()), num_tokens, num_experts, n_group,\n topk_group, topk, routed_scaling_factor, launch_with_pdl, stream, replay_ptr);\n break;\n case float32_code:\n invokeNoAuxTc<__nv_bfloat16, float, __nv_bfloat16, int32_t>(\n reinterpret_cast<__nv_bfloat16*>(scores.data_ptr()),\n reinterpret_cast<float*>(bias.data_ptr()),\n reinterpret_cast<__nv_bfloat16*>(topk_values.data_ptr()),\n reinterpret_cast<int32_t*>(topk_indices.data_ptr()), num_tokens, num_experts, n_group,\n topk_group, topk, routed_scaling_factor, launch_with_pdl, stream, replay_ptr);\n break;\n default:\n throw std::invalid_argument(\n \"Invalid bias dtype, only supports bfloat16, float16, and float32\");\n break;\n }\n break;\n default:\n // Handle other data types\n throw std::invalid_argument(\"Invalid dtype, only supports float16, float32, and bfloat16\");\n break;\n }\n}\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(NoAuxTc, flashinfer::trtllm_dsv3_fused_routing::NoAuxTc);\n} // namespace flashinfer::trtllm_dsv3_fused_routing\n"},"after_code":{"kind":"string","value":"#include <cooperative_groups.h>\n#include <cooperative_groups/reduce.h>\n\n#include <cmath>\n\n#include \"flashinfer/trtllm/fused_moe/noAuxTcKernels.h\"\n#include \"moeTopKFuncs.cuh\"\n#include \"tensorrt_llm/common/cudaTypeUtils.cuh\"\n#include \"tensorrt_llm/common/envUtils.h\"\n#include \"tvm_ffi_utils.h\"\n\n#ifdef FLASHINFER_CAKE_BACKEND\n#include \"cake_deepseek_fused_routing/cake_deepseek_fused_routing_kernels.cu\"\n#include \"cake_deepseek_fused_routing_launch.cuh\"\n#endif\n\nusing tvm::ffi::Optional;\n\nnamespace cg = cooperative_groups;\nusing namespace tensorrt_llm::common;\n\nnamespace tensorrt_llm::kernels {\nstatic constexpr int WARP_SIZE = 32;\nstatic constexpr int NumKimiK2Experts = 384;\nstatic constexpr int NumDeepseekExperts = 256;\nstatic constexpr int MaxNumExpertsUnit = 128;\nstatic constexpr int NumTopGroupScores = 2;\nstatic constexpr int MaxNumTopExperts = 8;\nstatic constexpr int MaxNumTopGroups = 4;\n\nstatic __device__ inline float sigmoid_accurate(float x) { return 0.5f * tanhf(0.5f * x) + 0.5f; }\n\ntemplate <typename InputT, typename BiasT, typename OutputT, typename IdxT, int MaxNumExperts,\n bool UseGroups>\n__global__ void deepseek_v3_topk_kernel(InputT* scores, OutputT* topkValues, IdxT* topkIndices,\n BiasT* routingBias, int64_t const numTokens,\n int64_t const numGroup, int64_t const topkGroup,\n int64_t const topk, int64_t const numExperts,\n int64_t const numExpertsPerGroup,\n double const routedScalingFactor,\n int16_t* routingReplayOut) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"griddepcontrol.wait;\");\n#endif\n\n // declare shared memory structure\n // number of experts is bounded by number of threads\n __shared__ float __attribute((aligned(128))) smemScoreSigmoid[MaxNumExperts];\n __shared__ float __attribute((aligned(128))) smemScoreBias[MaxNumExperts];\n // number of expert groups is bounded by number of warps\n int constexpr NumWarps = MaxNumExperts / WARP_SIZE;\n __shared__ float __attribute((aligned(128))) smemGroupScores[NumWarps];\n\n // needed for warp reduce\n auto block = cg::this_thread_block();\n auto warp = cg::tiled_partition<WARP_SIZE>(block);\n\n // for the final reduction of weight norm, only some lanes need to participate\n int32_t laneIdx = threadIdx.x % WARP_SIZE;\n int32_t warpIdx = __shfl_sync(0xffffffff, threadIdx.x / WARP_SIZE, 0);\n\n if constexpr (UseGroups) {\n if (warpIdx >= numGroup) {\n return;\n }\n }\n\n // note that for invalid scores, we simply use a negative value:\n // they work well even with the compacted format used in topK, and\n // sigmoid / bias activated scores cannot be negative\n static constexpr float invalidScoreFloat = float{-INFINITY};\n const OutputT invalidScore = OutputT{invalidScoreFloat};\n\n // load bias already; each warp represents one expert group\n auto threadExpert = threadIdx.x;\n bool expertSelected = threadExpert < numExperts;\n if constexpr (UseGroups) {\n threadExpert = warpIdx * numExpertsPerGroup + laneIdx;\n expertSelected = laneIdx < numExpertsPerGroup;\n }\n\n auto scoreIdx = int64_t{blockIdx.x} * int64_t{numExperts} + threadExpert;\n auto biasVal = expertSelected ? static_cast<float>(routingBias[threadExpert]) : invalidScoreFloat;\n topkValues += blockIdx.x * topk;\n topkIndices += blockIdx.x * topk;\n\n // get our assigned thread score; each warp represents one expert group\n float score = expertSelected ? static_cast<float>(scores[scoreIdx]) : invalidScoreFloat;\n auto scoreSigmoid = sigmoid_accurate(score);\n // write the sigmoid score to shared for later use\n if (expertSelected) {\n smemScoreSigmoid[threadExpert] = scoreSigmoid;\n }\n\n // get the score with bias\n // note that with invalid values, because sigmoid is < 1 and bias is -1,\n // we must get a negative value, which is smaller than any valid value\n auto scoreBias = float{scoreSigmoid + float{biasVal}};\n\n if (expertSelected) {\n smemScoreBias[threadExpert] = scoreBias;\n }\n\n // registers for top group score reduction\n float topExpGroupScores[NumTopGroupScores];\n [[maybe_unused]] int32_t topExpGroupIdx[NumTopGroupScores];\n float topGroups[MaxNumTopGroups]; // bound of numGroup\n int32_t topGroupIdx[MaxNumTopGroups];\n float expertScoreGroup[MaxNumTopGroups];\n int32_t expertIdxGroup[MaxNumTopGroups];\n float topScores[MaxNumTopExperts]; // bound of topk\n int32_t topExperts[MaxNumTopExperts];\n\n if constexpr (UseGroups) {\n reduce_topk::reduceTopK(warp, topExpGroupScores, topExpGroupIdx, scoreBias, threadExpert,\n /* minValue */ invalidScoreFloat);\n\n // get the final group score and write it to shared\n if (laneIdx == 0) {\n auto groupScore = topExpGroupScores[0] + topExpGroupScores[1];\n smemGroupScores[warpIdx] = groupScore;\n }\n }\n\n // make group scores available to all warps\n __syncthreads();\n\n if constexpr (UseGroups) {\n if (warpIdx == 0) {\n // a single warp performs the selection of top groups, and goes on to select the final experts\n float groupScore = laneIdx < numGroup ? smemGroupScores[laneIdx] : invalidScoreFloat;\n\n reduce_topk::reduceTopK(warp, topGroups, topGroupIdx, groupScore, laneIdx,\n /* minValue */ invalidScoreFloat);\n\n // final expert selection: get relevant indexes and scores from shared\n\n#pragma unroll\n for (int ii = 0; ii < MaxNumTopGroups; ++ii) { // bound of numGroup\n // auto groupIdx = topGroupIdx[ii];\n auto groupIdx = (ii < topkGroup) ? topGroupIdx[ii] : 0;\n expertIdxGroup[ii] = groupIdx * numExpertsPerGroup + laneIdx;\n\n expertScoreGroup[ii] = (ii < topkGroup) && expertSelected\n ? smemScoreBias[expertIdxGroup[ii]]\n : invalidScoreFloat;\n }\n\n tensorrt_llm::kernels::reduce_topk::reduceTopK(warp, topScores, topExperts, expertScoreGroup,\n expertIdxGroup,\n /* minValue */ invalidScoreFloat, topk);\n }\n } else if constexpr (MaxNumExperts > MaxNumExpertsUnit) {\n // without groups, and the expert number is larger than MaxNumExpertsUnit,\n // we need to use multiple warps to calculate the intermediate topk results\n\n int constexpr NumExpertWarps = (MaxNumExperts - 1) / MaxNumExpertsUnit + 1;\n int constexpr NumInterTopK = NumExpertWarps * MaxNumTopExperts;\n __shared__ float __attribute((aligned(128))) smemInterTopScores[NumInterTopK];\n __shared__ int32_t __attribute((aligned(128))) smemInterTopExperts[NumInterTopK];\n if (warpIdx < NumExpertWarps) {\n int offset = warpIdx * WARP_SIZE * MaxNumTopGroups;\n#pragma unroll\n for (int ii = 0; ii < MaxNumTopGroups; ++ii) {\n auto expertIdx = ii * WARP_SIZE + laneIdx;\n expertIdxGroup[ii] = offset + expertIdx;\n expertScoreGroup[ii] =\n offset + expertIdx < numExperts ? smemScoreBias[offset + expertIdx] : invalidScoreFloat;\n }\n reduce_topk::reduceTopK(warp, topScores, topExperts, expertScoreGroup, expertIdxGroup,\n /* minValue */ invalidScoreFloat, topk);\n\n if (laneIdx < topk) {\n smemInterTopScores[warpIdx * MaxNumTopExperts + laneIdx] = topScores[laneIdx];\n smemInterTopExperts[warpIdx * MaxNumTopExperts + laneIdx] = topExperts[laneIdx];\n }\n }\n __syncthreads();\n if (warpIdx == 0) {\n int constexpr NumInterTopKPerThread = (NumInterTopK * NumExpertWarps - 1) / WARP_SIZE + 1;\n float intermidiateScore[NumInterTopKPerThread];\n int32_t intermidiateExpert[NumInterTopKPerThread];\n for (int i = laneIdx; i < NumInterTopKPerThread * WARP_SIZE; i += WARP_SIZE) {\n int ii = i / WARP_SIZE;\n if (i < NumInterTopK) {\n intermidiateScore[ii] = smemInterTopScores[i];\n intermidiateExpert[ii] = smemInterTopExperts[i];\n } else {\n intermidiateScore[ii] = invalidScoreFloat;\n intermidiateExpert[ii] = MaxNumExperts - 1;\n }\n }\n reduce_topk::reduceTopK(warp, topScores, topExperts, intermidiateScore, intermidiateExpert,\n /* minValue */ invalidScoreFloat, topk);\n }\n } else {\n // without groups, and the expert number is smaller than MaxNumExpertsUnit\n // each thread just takes `MaxNumTopGroups` experts\n if (warpIdx == 0) {\n#pragma unroll\n for (int ii = 0; ii < MaxNumTopGroups; ++ii) {\n auto expertIdx = ii * WARP_SIZE + laneIdx;\n expertIdxGroup[ii] = expertIdx;\n expertScoreGroup[ii] =\n expertIdx < numExperts ? smemScoreBias[expertIdx] : invalidScoreFloat;\n }\n reduce_topk::reduceTopK(warp, topScores, topExperts, expertScoreGroup, expertIdxGroup,\n /* minValue */ invalidScoreFloat, topk);\n }\n }\n\n if (warpIdx == 0) {\n // determine our lane's expert index and write to output\n int32_t expertIdx = laneIdx < topk ? topExperts[laneIdx] : MaxNumExperts - 1;\n // norm the value\n float scoreNorm = laneIdx < topk ? smemScoreSigmoid[expertIdx] : 0.F;\n auto redNorm = cg::reduce(warp, scoreNorm, cg::plus<float>{});\n auto finalScore = static_cast<OutputT>(scoreNorm * routedScalingFactor / (redNorm + 1e-20));\n // store the topk scores and experts to output\n if (laneIdx < topk) {\n topkValues[laneIdx] = static_cast<OutputT>(finalScore);\n topkIndices[laneIdx] = expertIdx;\n // Routing replay: record selected expert IDs per token\n if (routingReplayOut != nullptr) {\n routingReplayOut[blockIdx.x * topk + laneIdx] = static_cast<int16_t>(expertIdx);\n }\n }\n }\n\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"griddepcontrol.launch_dependents;\");\n#endif\n}\n\ntemplate <typename InputT, typename BiasT, typename OutputT, typename IdxT>\nvoid invokeNoAuxTc(InputT* scores, BiasT* bias, OutputT* topk_values, IdxT* topk_indices,\n int64_t const num_tokens, int64_t const num_experts, int64_t const n_group,\n int64_t const topk_group, int64_t const topk, double const routed_scaling_factor,\n bool const launch_with_pdl, cudaStream_t const stream,\n int16_t* routing_replay_out) {\n#ifdef FLASHINFER_CAKE_BACKEND\n bool const cake_common = num_tokens > 0 && num_experts > 0 && n_group > 0 &&\n num_experts % n_group == 0 && topk > 0 && topk <= 8 &&\n topk <= num_experts && topk_group > 0 && topk_group <= n_group &&\n topk_group * n_group >= topk;\n bool const cake_single_group = cake_common && (n_group == 1) && (num_experts <= NumKimiK2Experts);\n int64_t const cake_experts_per_group = n_group > 0 ? num_experts / n_group : 0;\n bool const cake_multi_group = cake_common && (n_group >= 2) && (n_group <= 8) &&\n (topk_group <= 4) && (num_experts <= NumDeepseekExperts) &&\n (cake_experts_per_group >= 2) &&\n (cake_experts_per_group <= WARP_SIZE) &&\n (cake_experts_per_group * topk_group <= MaxNumExpertsUnit);\n TLLM_CHECK_WITH_INFO(cake_single_group || cake_multi_group,\n \"invokeNoAuxTc: unsupported configuration (n_group=%ld, num_experts=%ld, \"\n \"topk_group=%ld). Please use original pytorch implementation.\",\n n_group, num_experts, topk_group);\n auto const status = flashinfer::cake_deepseek_fused_routing::launch<InputT, BiasT>(\n scores, bias, topk_values, topk_indices, routing_replay_out, num_tokens, num_experts, n_group,\n topk_group, topk, routed_scaling_factor, launch_with_pdl, stream);\n TLLM_CHECK_WITH_INFO(status == cudaSuccess, \"Cake fused routing launch failed: %s\",\n cudaGetErrorString(status));\n sync_check_cuda_error(stream);\n return;\n#endif\n\n // Check if we can use the optimized deepseek_v3_topk_kernel\n bool const is_single_group = (n_group == 1) && (num_experts <= NumKimiK2Experts);\n\n int64_t const experts_per_group = num_experts / n_group;\n bool const is_multi_group = (n_group != 1) && (num_experts <= NumDeepseekExperts) &&\n (experts_per_group <= WARP_SIZE) &&\n (experts_per_group * topk_group <= MaxNumExpertsUnit);\n\n if (is_single_group || is_multi_group) {\n cudaLaunchConfig_t config;\n auto* kernel_instance =\n &deepseek_v3_topk_kernel<InputT, BiasT, OutputT, IdxT, NumDeepseekExperts, true>;\n int num_threads = NumDeepseekExperts;\n if (is_single_group) {\n if (num_experts > MaxNumExpertsUnit) {\n kernel_instance =\n &deepseek_v3_topk_kernel<InputT, BiasT, OutputT, IdxT, NumKimiK2Experts, false>;\n num_threads = NumKimiK2Experts;\n } else {\n kernel_instance =\n &deepseek_v3_topk_kernel<InputT, BiasT, OutputT, IdxT, MaxNumExpertsUnit, false>;\n num_threads = MaxNumExpertsUnit;\n }\n }\n\n config.gridDim = num_tokens;\n config.blockDim = num_threads;\n config.dynamicSmemBytes = 0;\n config.stream = stream;\n cudaLaunchAttribute attrs[1];\n attrs[0].id = cudaLaunchAttributeProgrammaticStreamSerialization;\n attrs[0].val.programmaticStreamSerializationAllowed = launch_with_pdl;\n config.numAttrs = 1;\n config.attrs = attrs;\n\n cudaLaunchKernelEx(&config, kernel_instance, scores, topk_values, topk_indices, bias,\n num_tokens, n_group, topk_group, topk, num_experts, num_experts / n_group,\n routed_scaling_factor, routing_replay_out);\n sync_check_cuda_error(stream);\n } else {\n // TODO: call the generic path (previous implementation) or signal unsupported config.\n TLLM_CHECK_WITH_INFO(false,\n \"invokeNoAuxTc: unsupported configuration (n_group=%ld, num_experts=%ld, \"\n \"topk_group=%ld). Please use \"\n \"original pytorch implementation.\",\n n_group, num_experts, topk_group);\n }\n}\n\n#define INSTANTIATE_NOAUX_TC(InputT, BiasT, OutputT, IdxT) \\\n template void invokeNoAuxTc<InputT, BiasT, OutputT, IdxT>( \\\n InputT * scores, BiasT * bias, OutputT * topk_values, IdxT * topk_indices, \\\n int64_t const num_tokens, int64_t const num_experts, int64_t const n_group, \\\n int64_t const topk_group, int64_t const topk, double const routed_scaling_factor, \\\n bool const launch_with_pdl, cudaStream_t const stream, int16_t* routing_replay_out);\n\nINSTANTIATE_NOAUX_TC(float, float, float, int32_t);\nINSTANTIATE_NOAUX_TC(float, half, float, int32_t);\n\nINSTANTIATE_NOAUX_TC(half, float, half, int32_t);\nINSTANTIATE_NOAUX_TC(half, half, half, int32_t);\n\n#ifdef ENABLE_BF16\nINSTANTIATE_NOAUX_TC(float, __nv_bfloat16, float, int32_t);\nINSTANTIATE_NOAUX_TC(half, __nv_bfloat16, half, int32_t);\n\nINSTANTIATE_NOAUX_TC(__nv_bfloat16, __nv_bfloat16, __nv_bfloat16, int32_t);\nINSTANTIATE_NOAUX_TC(__nv_bfloat16, float, __nv_bfloat16, int32_t);\nINSTANTIATE_NOAUX_TC(__nv_bfloat16, half, __nv_bfloat16, int32_t);\n#endif\n\n} // namespace tensorrt_llm::kernels\n\nnamespace flashinfer::trtllm_dsv3_fused_routing {\n// th::Tensor const& scores, th::Tensor const& bias, int64_t n_group,\n// int64_t topk_group, int64_t topk, double routed_scaling_factor\n// th::Tensor topk_values, th::Tensor topk_indices\n\nvoid NoAuxTc(TensorView scores, TensorView bias, int64_t n_group, int64_t topk_group, int64_t topk,\n double routed_scaling_factor, TensorView topk_values, TensorView topk_indices,\n bool launch_with_pdl, Optional<TensorView> routing_replay_out) {\n auto data_type = scores.dtype();\n auto bias_type = bias.dtype();\n\n auto input_size = scores.sizes();\n int64_t num_tokens = input_size[0];\n int64_t num_experts = input_size[1];\n\n TVM_FFI_ICHECK(input_size.size() == 2) << \"scores must be a 2D Tensor\";\n TVM_FFI_ICHECK((scores.device().device_type == kDLCUDA) && (bias.device().device_type == kDLCUDA))\n << \"scores and bias must be CUDA tensors\";\n TVM_FFI_ICHECK(scores.device().device_id == bias.device().device_id)\n << \"scores and bias must be on the same device\";\n TVM_FFI_ICHECK(bias.dim() == 1 && bias.numel() == num_experts)\n << \"bias must be 1D with length == number of experts (%ld)\";\n TVM_FFI_ICHECK(num_experts % n_group == 0) << \"num_experts should be divisible by n_group\";\n TVM_FFI_ICHECK(n_group <= 32)\n << \"n_group should be smaller than or equal to 32 for now\"; //@todo: remove this restriction\n // later\n TVM_FFI_ICHECK(topk <= 32)\n << \"topk should be smaller than or equal to 32 for now\"; //@todo: remove this restriction\n // later\n TVM_FFI_ICHECK(topk_values.dim() == 2) << \"topk_values must be a 2D Tensor\";\n TVM_FFI_ICHECK(topk_indices.dim() == 2) << \"topk_indices must be a 2D Tensor\";\n TVM_FFI_ICHECK(topk_values.sizes()[0] == num_tokens)\n << \"topk_values must have the same number of tokens as scores\";\n TVM_FFI_ICHECK(topk_indices.sizes()[0] == num_tokens)\n << \"topk_indices must have the same number of tokens as scores\";\n TVM_FFI_ICHECK(topk_values.sizes()[1] == topk)\n << \"topk_values must have the same number of topk as scores\";\n TVM_FFI_ICHECK(topk_indices.sizes()[1] == topk)\n << \"topk_indices must have the same number of topk as scores\";\n TVM_FFI_ICHECK(topk_values.dtype() == data_type)\n << \"topk_values must have the same dtype as scores\";\n TVM_FFI_ICHECK(encode_dlpack_dtype(topk_indices.dtype()) == int32_code)\n << \"topk_indices must be int32 dtype\";\n\n // Validate and extract routing_replay_out\n // NOTE: dim0 >= num_tokens is intentionally NOT checked — with CUDA graphs the buffer\n // is pre-allocated at maximum batch size and reused across steps with varying num_tokens.\n // The kernel only writes to indices [0, num_tokens), so a larger buffer is safe.\n constexpr int64_t int16_code_val = encode_dlpack_dtype(DLDataType{kDLInt, 16, 1});\n int16_t* replay_ptr = nullptr;\n if (routing_replay_out.has_value()) {\n auto replay = routing_replay_out.value();\n TVM_FFI_ICHECK(replay.device().device_type == kDLCUDA)\n << \"routing_replay_out must be a CUDA tensor\";\n TVM_FFI_ICHECK(replay.device().device_id == scores.device().device_id)\n << \"routing_replay_out must be on the same device as scores\";\n TVM_FFI_ICHECK(replay.ndim() == 2)\n << \"routing_replay_out must be a 2D Tensor [num_tokens, topk]\";\n TVM_FFI_ICHECK(replay.sizes()[1] == topk) << \"routing_replay_out dim1 must equal topk\";\n TVM_FFI_ICHECK(encode_dlpack_dtype(replay.dtype()) == int16_code_val)\n << \"routing_replay_out must be int16 dtype\";\n replay_ptr = reinterpret_cast<int16_t*>(replay.data_ptr());\n }\n\n auto stream = get_stream(scores.device());\n using namespace tensorrt_llm::kernels;\n switch (encode_dlpack_dtype(data_type)) {\n case float16_code:\n // Handle Float16\n switch (encode_dlpack_dtype(bias_type)) {\n case float16_code:\n invokeNoAuxTc<half, half, half, int32_t>(\n reinterpret_cast<half*>(scores.data_ptr()), reinterpret_cast<half*>(bias.data_ptr()),\n reinterpret_cast<half*>(topk_values.data_ptr()),\n reinterpret_cast<int32_t*>(topk_indices.data_ptr()), num_tokens, num_experts, n_group,\n topk_group, topk, routed_scaling_factor, launch_with_pdl, stream, replay_ptr);\n break;\n case float32_code:\n invokeNoAuxTc<half, float, half, int32_t>(\n reinterpret_cast<half*>(scores.data_ptr()), reinterpret_cast<float*>(bias.data_ptr()),\n reinterpret_cast<half*>(topk_values.data_ptr()),\n reinterpret_cast<int32_t*>(topk_indices.data_ptr()), num_tokens, num_experts, n_group,\n topk_group, topk, routed_scaling_factor, launch_with_pdl, stream, replay_ptr);\n break;\n case bfloat16_code:\n invokeNoAuxTc<half, __nv_bfloat16, half, int32_t>(\n reinterpret_cast<half*>(scores.data_ptr()),\n reinterpret_cast<__nv_bfloat16*>(bias.data_ptr()),\n reinterpret_cast<half*>(topk_values.data_ptr()),\n reinterpret_cast<int32_t*>(topk_indices.data_ptr()), num_tokens, num_experts, n_group,\n topk_group, topk, routed_scaling_factor, launch_with_pdl, stream, replay_ptr);\n break;\n default:\n throw std::invalid_argument(\n \"Invalid bias dtype, only supports float16, float32, and bfloat16\");\n break;\n }\n break;\n case float32_code:\n switch (encode_dlpack_dtype(bias_type)) {\n case float32_code:\n invokeNoAuxTc<float, float, float, int32_t>(\n reinterpret_cast<float*>(scores.data_ptr()),\n reinterpret_cast<float*>(bias.data_ptr()),\n reinterpret_cast<float*>(topk_values.data_ptr()),\n reinterpret_cast<int32_t*>(topk_indices.data_ptr()), num_tokens, num_experts, n_group,\n topk_group, topk, routed_scaling_factor, launch_with_pdl, stream, replay_ptr);\n break;\n case float16_code:\n invokeNoAuxTc<float, half, float, int32_t>(\n reinterpret_cast<float*>(scores.data_ptr()), reinterpret_cast<half*>(bias.data_ptr()),\n reinterpret_cast<float*>(topk_values.data_ptr()),\n reinterpret_cast<int32_t*>(topk_indices.data_ptr()), num_tokens, num_experts, n_group,\n topk_group, topk, routed_scaling_factor, launch_with_pdl, stream, replay_ptr);\n break;\n case bfloat16_code:\n invokeNoAuxTc<float, __nv_bfloat16, float, int32_t>(\n reinterpret_cast<float*>(scores.data_ptr()),\n reinterpret_cast<__nv_bfloat16*>(bias.data_ptr()),\n reinterpret_cast<float*>(topk_values.data_ptr()),\n reinterpret_cast<int32_t*>(topk_indices.data_ptr()), num_tokens, num_experts, n_group,\n topk_group, topk, routed_scaling_factor, launch_with_pdl, stream, replay_ptr);\n break;\n default:\n throw std::invalid_argument(\n \"Invalid bias dtype, only supports float16, float32, and bfloat16\");\n break;\n }\n break;\n case bfloat16_code:\n // Handle BFloat16\n switch (encode_dlpack_dtype(bias_type)) {\n case bfloat16_code:\n invokeNoAuxTc<__nv_bfloat16, __nv_bfloat16, __nv_bfloat16, int32_t>(\n reinterpret_cast<__nv_bfloat16*>(scores.data_ptr()),\n reinterpret_cast<__nv_bfloat16*>(bias.data_ptr()),\n reinterpret_cast<__nv_bfloat16*>(topk_values.data_ptr()),\n reinterpret_cast<int32_t*>(topk_indices.data_ptr()), num_tokens, num_experts, n_group,\n topk_group, topk, routed_scaling_factor, launch_with_pdl, stream, replay_ptr);\n break;\n case float16_code:\n invokeNoAuxTc<__nv_bfloat16, half, __nv_bfloat16, int32_t>(\n reinterpret_cast<__nv_bfloat16*>(scores.data_ptr()),\n reinterpret_cast<half*>(bias.data_ptr()),\n reinterpret_cast<__nv_bfloat16*>(topk_values.data_ptr()),\n reinterpret_cast<int32_t*>(topk_indices.data_ptr()), num_tokens, num_experts, n_group,\n topk_group, topk, routed_scaling_factor, launch_with_pdl, stream, replay_ptr);\n break;\n case float32_code:\n invokeNoAuxTc<__nv_bfloat16, float, __nv_bfloat16, int32_t>(\n reinterpret_cast<__nv_bfloat16*>(scores.data_ptr()),\n reinterpret_cast<float*>(bias.data_ptr()),\n reinterpret_cast<__nv_bfloat16*>(topk_values.data_ptr()),\n reinterpret_cast<int32_t*>(topk_indices.data_ptr()), num_tokens, num_experts, n_group,\n topk_group, topk, routed_scaling_factor, launch_with_pdl, stream, replay_ptr);\n break;\n default:\n throw std::invalid_argument(\n \"Invalid bias dtype, only supports bfloat16, float16, and float32\");\n break;\n }\n break;\n default:\n // Handle other data types\n throw std::invalid_argument(\"Invalid dtype, only supports float16, float32, and bfloat16\");\n break;\n }\n}\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(NoAuxTc, flashinfer::trtllm_dsv3_fused_routing::NoAuxTc);\n} // namespace flashinfer::trtllm_dsv3_fused_routing\n"},"diff":{"kind":"string","value":"--- csrc/fused_moe/noAuxTcKernels.cu\n+++ csrc/fused_moe/noAuxTcKernels.cu\n@@ -8,6 +8,11 @@\n #include \"tensorrt_llm/common/cudaTypeUtils.cuh\"\n #include \"tensorrt_llm/common/envUtils.h\"\n #include \"tvm_ffi_utils.h\"\n+\n+#ifdef FLASHINFER_CAKE_BACKEND\n+#include \"cake_deepseek_fused_routing/cake_deepseek_fused_routing_kernels.cu\"\n+#include \"cake_deepseek_fused_routing_launch.cuh\"\n+#endif\n \n using tvm::ffi::Optional;\n \n@@ -233,6 +238,31 @@\n int64_t const topk_group, int64_t const topk, double const routed_scaling_factor,\n bool const launch_with_pdl, cudaStream_t const stream,\n int16_t* routing_replay_out) {\n+#ifdef FLASHINFER_CAKE_BACKEND\n+ bool const cake_common = num_tokens > 0 && num_experts > 0 && n_group > 0 &&\n+ num_experts % n_group == 0 && topk > 0 && topk <= 8 &&\n+ topk <= num_experts && topk_group > 0 && topk_group <= n_group &&\n+ topk_group * n_group >= topk;\n+ bool const cake_single_group = cake_common && (n_group == 1) && (num_experts <= NumKimiK2Experts);\n+ int64_t const cake_experts_per_group = n_group > 0 ? num_experts / n_group : 0;\n+ bool const cake_multi_group = cake_common && (n_group >= 2) && (n_group <= 8) &&\n+ (topk_group <= 4) && (num_experts <= NumDeepseekExperts) &&\n+ (cake_experts_per_group >= 2) &&\n+ (cake_experts_per_group <= WARP_SIZE) &&\n+ (cake_experts_per_group * topk_group <= MaxNumExpertsUnit);\n+ TLLM_CHECK_WITH_INFO(cake_single_group || cake_multi_group,\n+ \"invokeNoAuxTc: unsupported configuration (n_group=%ld, num_experts=%ld, \"\n+ \"topk_group=%ld). Please use original pytorch implementation.\",\n+ n_group, num_experts, topk_group);\n+ auto const status = flashinfer::cake_deepseek_fused_routing::launch<InputT, BiasT>(\n+ scores, bias, topk_values, topk_indices, routing_replay_out, num_tokens, num_experts, n_group,\n+ topk_group, topk, routed_scaling_factor, launch_with_pdl, stream);\n+ TLLM_CHECK_WITH_INFO(status == cudaSuccess, \"Cake fused routing launch failed: %s\",\n+ cudaGetErrorString(status));\n+ sync_check_cuda_error(stream);\n+ return;\n+#endif\n+\n // Check if we can use the optimized deepseek_v3_topk_kernel\n bool const is_single_group = (n_group == 1) && (num_experts <= NumKimiK2Experts);\n "},"lines_added":{"kind":"number","value":30,"string":"30"},"lines_removed":{"kind":"number","value":0,"string":"0"},"files_in_commit":{"kind":"number","value":3,"string":"3"},"models_mentioned":{"kind":"list like","value":["deepseek"],"string":"[\n \"deepseek\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["B200","GB300"],"string":"[\n \"B200\",\n \"GB300\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":["1.1829x","1.5522x","7.6589x","9.3881x","1.1059x","1.3919x","14.4118x","18.3243x","1.0440x","1.3158x"],"string":"[\n \"1.1829x\",\n \"1.5522x\",\n \"7.6589x\",\n \"9.3881x\",\n \"1.1059x\",\n \"1.3919x\",\n \"14.4118x\",\n \"18.3243x\",\n \"1.0440x\",\n \"1.3158x\"\n]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (csrc/fused_moe/noAuxTcKernels.cu).\n\nGoal: feat(cake_backend): accelerate DeepSeek fused routing\nTarget hardware: B200, GB300\nTarget models: deepseek\n\nCurrent file:\n```cuda\n#include <cooperative_groups.h>\n#include <cooperative_groups/reduce.h>\n\n#include <cmath>\n\n#include \"flashinfer/trtllm/fused_moe/noAuxTcKernels.h\"\n#include \"moeTopKFuncs.cuh\"\n#include \"tensorrt_llm/common/cudaTypeUtils.cuh\"\n#include \"tensorrt_llm/common/envUtils.h\"\n#include \"tvm_ffi_utils.h\"\n\nusing tvm::ffi::Optional;\n\nnamespace cg = cooperative_groups;\nusing namespace tensorrt_llm::common;\n\nnamespace tensorrt_llm::kernels {\nstatic constexpr int WARP_SIZE = 32;\nstatic constexpr int NumKimiK2Experts = 384;\nstatic constexpr int NumDeepseekExperts = 256;\nstatic constexpr int MaxNumExpertsUnit = 128;\nstatic constexpr int NumTopGroupScores = 2;\nstatic constexpr int MaxNumTopExperts = 8;\nstatic constexpr int MaxNumTopGroups = 4;\n\nstatic __device__ inline float sigmoid_accurate(float x) { return 0.5f * tanhf(0.5f * x) + 0.5f; }\n\ntemplate <typename InputT, typename BiasT, typename OutputT, typename IdxT, int MaxNumExperts,\n bool UseGroups>\n__global__ void deepseek_v3_topk_kernel(InputT* scores, OutputT* topkValues, IdxT* topkIndices,\n BiasT* routingBias, int64_t const numTokens,\n int64_t const numGroup, int64_t const topkGroup,\n int64_t const topk, int64_t const numExperts,\n int64_t const numExpertsPerGroup,\n double const routedScalingFactor,\n int16_t* routingReplayOut) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"griddepcontrol.wait;\");\n#endif\n\n // declare shared memory structure\n // number of experts is bounded by number of threads\n __shared__ float __attribute((aligned(128))) smemScoreSigmoid[MaxNumExperts];\n __shared__ float __attribute((aligned(128))) smemScoreBias[MaxNumExperts];\n // number of expert groups is bounded by number of warps\n int constexpr NumWarps = MaxNumExperts / WARP_SIZE;\n __shared__ float __attribute((aligned(128))) smemGroupScores[NumWarps];\n\n // needed for warp reduce\n auto block = cg::this_thread_block();\n auto warp = cg::tiled_partition<WARP_SIZE>(block);\n\n // for the final reduction of weight norm, only some lanes need to participate\n int32_t laneIdx = threadIdx.x % WARP_SIZE;\n int32_t warpIdx = __shfl_sync(0xffffffff, threadIdx.x / WARP_SIZE, 0);\n\n if constexpr (UseGroups) {\n if (warpIdx >= numGroup) {\n return;\n }\n }\n\n // note that for invalid scores, we simply use a negative value:\n // they work well even with the compacted format used in topK, and\n // sigmoid / bias activated scores cannot be negative\n static constexpr float invalidScoreFloat = float{-INFINITY};\n const OutputT invalidScore = OutputT{invalidScoreFloat};\n\n // load bias already; each warp represents one expert group\n auto threadExpert = threadIdx.x;\n bool expertSelected = threadExpert < numExperts;\n if constexpr (UseGroups) {\n threadExpert = warpIdx * numExpertsPerGroup + laneIdx;\n expertSelected = laneIdx < numExpertsPerGroup;\n }\n\n auto scoreIdx = int64_t{blockIdx.x} * int64_t{numExperts} + threadExpert;\n auto biasVal = expertSelected ? static_cast<float>(routingBias[threadExpert]) : invalidScoreFloat;\n topkValues += blockIdx.x * topk;\n topkIndices += blockIdx.x * topk;\n\n // get our assigned thread score; each warp represents one expert group\n float score = expertSelected ? static_cast<float>(scores[scoreIdx]) : invalidScoreFloat;\n auto scoreSigmoid = sigmoid_accurate(score);\n // write the sigmoid score to shared for later use\n if (expertSelected) {\n smemScoreSigmoid[threadExpert] = scoreSigmoid;\n }\n\n // get the score with bias\n // note that with invalid values, because sigmoid is < 1 and bias is -1,\n // we must get a negative value, which is smaller than any valid value\n auto scoreBias = float{scoreSigmoid + float{biasVal}};\n\n if (expertSelected) {\n smemScoreBias[threadExpert] = scoreBias;\n }\n\n // registers for top group score reduction\n float topExpGroupScores[NumTopGroupScores];\n [[maybe_unused]] int32_t topExpGroupIdx[NumTopGroupScores];\n float topGroups[MaxNumTopGroups]; // bound of numGroup\n int32_t topGroupIdx[MaxNumTopGroups];\n float expertScoreGroup[MaxNumTopGroups];\n int32_t expertIdxGroup[MaxNumTopGroups];\n float topScores[MaxNumTopExperts]; // bound of topk\n int32_t topExperts[MaxNumTopExperts];\n\n if constexpr (UseGroups) {\n reduce_topk::reduceTopK(warp, topExpGroupScores, topExpGroupIdx, scoreBias, threadExpert,\n /* minValue */ invalidScoreFloat);\n\n // get the final group score and write it to shared\n if (laneIdx == 0) {\n auto groupScore = topExpGroupScores[0] + topExpGroupScores[1];\n smemGroupScores[warpIdx] = groupScore;\n }\n }\n\n // make group scores available to all warps\n __syncthreads();\n\n if constexpr (UseGroups) {\n if (warpIdx == 0) {\n // a single warp performs the selection of top groups, and goes on to select the final experts\n float groupScore = laneIdx < numGroup ? smemGroupScores[laneIdx] : invalidScoreFloat;\n\n reduce_topk::reduceTopK(warp, topGroups, topGroupIdx, groupScore, laneIdx,\n /* minValue */ invalidScoreFloat);\n\n // final expert selection: get relevant indexes and scores from shared\n\n#pragma unroll\n for (int ii = 0; ii < MaxNumTopGroups; ++ii) { // bound of numGroup\n // auto groupIdx = topGroupIdx[ii];\n auto groupIdx = (ii < topkGroup) ? topGroupIdx[ii] : 0;\n expertIdxGroup[ii] = groupIdx * numExpertsPerGroup + laneIdx;\n\n expertScoreGroup[ii] = (ii < topkGroup) && expertSelected\n ? smemScoreBias[expertIdxGroup[ii]]\n : invalidScoreFloat;\n }\n\n tensorrt_llm::kernels::reduce_topk::reduceTopK(warp, topScores, topExperts, expertScoreGroup,\n expertIdxGroup,\n /* minValue */ invalidScoreFloat, topk);\n }\n } else if constexpr (MaxNumExperts > MaxNumExpertsUnit) {\n // without groups, and the expert number is larger than MaxNumExpertsUnit,\n // we need to use multiple warps to calculate the intermediate topk results\n\n int constexpr NumExpertWarps = (MaxNumExperts - 1) / MaxNumExpertsUnit + 1;\n int constexpr NumInterTopK = NumExpertWarps * MaxNumTopExperts;\n __shared__ float __attribute((aligned(128))) smemInterTopScores[NumInterTopK];\n __shared__ int32_t __attribute((aligned(128))) smemInterTopExperts[NumInterTopK];\n if (warpIdx < NumExpertWarps) {\n int offset = warpIdx * WARP_SIZE * MaxNumTopGroups;\n#pragma unroll\n for (int ii = 0; ii < MaxNumTopGroups; ++ii) {\n auto expertIdx = ii * WARP_SIZE + laneIdx;\n expertIdxGroup[ii] = offset + expertIdx;\n expertScoreGroup[ii] =\n offset + expertIdx < numExperts ? smemScoreBias[offset + expertIdx] : invalidScoreFloat;\n }\n reduce_topk::reduceTopK(warp, topScores, topExperts, expertScoreGroup, expertIdxGroup,\n /* minValue */ invalidScoreFloat, topk);\n\n if (laneIdx < topk) {\n smemInterTopScores[warpIdx * MaxNumTopExperts + laneIdx] = topScores[laneIdx];\n smemInterTopExperts[warpIdx * MaxNumTopExperts + laneIdx] = topExperts[laneIdx];\n }\n }\n __syncthreads();\n if (warpIdx == 0) {\n int constexpr NumInterTopKPerThread = (NumInterTopK * NumExpertWarps - 1) / WARP_SIZE + 1;\n float intermidiateScore[NumInterTopKPerThread];\n int32_t intermidiateExpert[NumInterTopKPerThread];\n for (int i = laneIdx; i < NumInterTopKPerThread * WARP_SIZE; i += WARP_SIZE) {\n int ii = i / WARP_SIZE;\n if (i < NumInterTopK) {\n intermidiateScore[ii] = smemInterTopScores[i];\n intermidiateExpert[ii] = smemInterTopExperts[i];\n } else {\n intermidiateScore[ii] = invalidScoreFloat;\n intermidiateExpert[ii] = MaxNumExperts - 1;\n }\n }\n reduce_topk::reduceTopK(warp, topScores, topExperts, intermidiateScore, intermidiateExpert,\n /* minValue */ invalidScoreFloat, topk);\n }\n } else {\n // without groups, and the expert number is smaller than MaxNumExpertsUnit\n // each thread just takes `MaxNumTopGroups` experts\n if (warpIdx == 0) {\n#pragma unroll\n for (int ii = 0; ii < MaxNumTopGroups; ++ii) {\n auto expertIdx = ii * WARP_SIZE + laneIdx;\n expertIdxGroup[ii] = expertIdx;\n expertScoreGroup[ii] =\n expertIdx < numExperts ? smemScoreBias[expertIdx] : invalidScoreFloat;\n }\n reduce_topk::reduceTopK(warp, topScores, topExperts, expertScoreGroup, expertIdxGroup,\n /* minValue */ invalidScoreFloat, topk);\n }\n }\n\n if (warpIdx == 0) {\n // determine our lane's expert index and write to output\n int32_t expertIdx = laneIdx < topk ? topExperts[laneIdx] : MaxNumExperts - 1;\n // norm the value\n float scoreNorm = laneIdx < topk ? smemScoreSigmoid[expertIdx] : 0.F;\n auto redNorm = cg::reduce(warp, scoreNorm, cg::plus<float>{});\n auto finalScore = static_cast<OutputT>(scoreNorm * routedScalingFactor / (redNorm + 1e-20));\n // store the topk scores and experts to output\n if (laneIdx < topk) {\n topkValues[laneIdx] = static_cast<OutputT>(finalScore);\n topkIndices[laneIdx] = expertIdx;\n // Routing replay: record selected expert IDs per token\n if (routingReplayOut != nullptr) {\n routingReplayOut[blockIdx.x * topk + laneIdx] = static_cast<int16_t>(expertIdx);\n }\n }\n }\n\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"griddepcontrol.launch_dependents;\");\n#endif\n}\n\ntemplate <typename InputT, typename BiasT, typename OutputT, typename IdxT>\nvoid invokeNoAuxTc(InputT* scores, BiasT* bias, OutputT* topk_values, IdxT* topk_indices,\n int64_t const num_tokens, int64_t const num_experts, int64_t const n_group,\n int64_t const topk_group, int64_t const topk, double const routed_scaling_factor,\n bool const launch_with_pdl, cudaStream_t const stream,\n int16_t* routing_replay_out) {\n // Check if we can use the optimized deepseek_v3_topk_kernel\n bool const is_single_group = (n_group == 1) && (num_experts <= NumKimiK2Experts);\n\n int64_t const experts_per_group = num_experts / n_group;\n bool const is_multi_group = (n_group != 1) && (num_experts <= NumDeepseekExperts) &&\n (experts_per_group <= WARP_SIZE) &&\n (experts_per_group * topk_group <= MaxNumExpertsUnit);\n\n if (is_single_group || is_multi_group) {\n cudaLaunchConfig_t config;\n auto* kernel_instance =\n &deepseek_v3_topk_kernel<InputT, BiasT, OutputT, IdxT, NumDeepseekExperts, true>;\n int num_threads = NumDeepseekExperts;\n if (is_single_group) {\n if (num_experts > MaxNumExpertsUnit) {\n kernel_instance =\n &deepseek_v3_topk_kernel<InputT, BiasT, OutputT, IdxT, NumKimiK2Experts, false>;\n num_threads = NumKimiK2Experts;\n } else {\n kernel_instance =\n &deepseek_v3_topk_kernel<InputT, BiasT, OutputT, IdxT, MaxNumExpertsUnit, false>;\n num_threads = MaxNumExpertsUnit;\n }\n }\n\n config.gridDim = num_tokens;\n config.blockDim = num_threads;\n config.dynamicSmemBytes = 0;\n config.stream = stream;\n cudaLaunchAttribute attrs[1];\n attrs[0].id = cudaLaunchAttributeProgrammaticStreamSerialization;\n attrs[0].val.programmaticStreamSerializationAllowed = launch_with_pdl;\n config.numAttrs = 1;\n config.attrs = attrs;\n\n cudaLaunchKernelEx(&config, kernel_instance, scores, topk_values, topk_indices, bias,\n num_tokens, n_group, topk_group, topk, num_experts, num_experts / n_group,\n routed_scaling_factor, routing_replay_out);\n sync_check_cuda_error(stream);\n } else {\n // TODO: call the generic path (previous implementation) or signal unsupported config.\n TLLM_CHECK_WITH_INFO(false,\n \"invokeNoAuxTc: unsupported configuration (n_group=%ld, num_experts=%ld, \"\n \"topk_group=%ld). Please use \"\n \"original pytorch implementation.\",\n n_group, num_experts, topk_group);\n }\n}\n\n#define INSTANTIATE_NOAUX_TC(InputT, BiasT, OutputT, IdxT) \\\n template void invokeNoAuxTc<InputT, BiasT, OutputT, IdxT>( \\\n InputT * scores, BiasT * bias, OutputT * topk_values, IdxT * topk_indices, \\\n int64_t const num_tokens, int64_t const num_experts, int64_t const n_group, \\\n int64_t const topk_group, int64_t const topk, double const routed_scaling_factor, \\\n bool const launch_with_pdl, cudaStream_t const stream, int16_t* routing_replay_out);\n\nINSTANTIATE_NOAUX_TC(float, float, float, int32_t);\nINSTANTIATE_NOAUX_TC(float, half, float, int32_t);\n\nINSTANTIATE_NOAUX_TC(half, float, half, int32_t);\nINSTANTIATE_NOAUX_TC(half, half, half, int32_t);\n\n#ifdef ENABLE_BF16\nINSTANTIATE_NOAUX_TC(float, __nv_bfloat16, float, int32_t);\nINSTANTIATE_NOAUX_TC(half, __nv_bfloat16, half, int32_t);\n\nINSTANTIATE_NOAUX_TC(__nv_bfloat16, __nv_bfloat16, __nv_bfloat16, int32_t);\nINSTANTIATE_NOAUX_TC(__nv_bfloat16, float, __nv_bfloat16, int32_t);\nINSTANTIATE_NOAUX_TC(__nv_bfloat16, half, __nv_bfloat16, int32_t);\n#endif\n\n} // namespace tensorrt_llm::kernels\n\nnamespace flashinfer::trtllm_dsv3_fused_routing {\n// th::Tensor const& scores, th::Tensor const& bias, int64_t n_group,\n// int64_t topk_group, int64_t topk, double routed_scaling_factor\n// th::Tensor topk_values, th::Tensor topk_indices\n\nvoid NoAuxTc(TensorView scores, TensorView bias, int64_t n_group, int64_t topk_group, int64_t topk,\n double routed_scaling_factor, TensorView topk_values, TensorView topk_indices,\n bool launch_with_pdl, Optional<TensorView> routing_replay_out) {\n auto data_type = scores.dtype();\n auto bias_type = bias.dtype();\n\n auto input_size = scores.sizes();\n int64_t num_tokens = input_size[0];\n int64_t num_experts = input_size[1];\n\n TVM_FFI_ICHECK(input_size.size() == 2) << \"scores must be a 2D Tensor\";\n TVM_FFI_ICHECK((scores.device().device_type == kDLCUDA) && (bias.device().device_type == kDLCUDA))\n << \"scores and bias must be CUDA tensors\";\n TVM_FFI_ICHECK(scores.device().device_id == bias.device().device_id)\n << \"scores and bias must be on the same device\";\n TVM_FFI_ICHECK(bias.dim() == 1 && bias.numel() == num_experts)\n << \"bias must be 1D with length == number of experts (%ld)\";\n TVM_FFI_ICHECK(num_experts % n_group == 0) << \"num_experts should be divisible by n_group\";\n TVM_FFI_ICHECK(n_group <= 32)\n << \"n_group should be smaller than or equal to 32 for now\"; //@todo: remove this restriction\n // later\n TVM_FFI_ICHECK(topk <= 32)\n << \"topk should be smaller than or equal to 32 for now\"; //@todo: remove this restriction\n // later\n TVM_FFI_ICHECK(topk_values.dim() == 2) << \"topk_values must be a 2D Tensor\";\n TVM_FFI_ICHECK(topk_indices.dim() == 2) << \"topk_indices must be a 2D Tensor\";\n TVM_FFI_ICHECK(topk_values.sizes()[0] == num_tokens)\n << \"topk_values must have the same number of tokens as scores\";\n TVM_FFI_ICHECK(topk_indices.sizes()[0] == num_tokens)\n << \"topk_indices must have the same number of tokens as scores\";\n TVM_FFI_ICHECK(topk_values.sizes()[1] == topk)\n << \"topk_values must have the same number of topk as scores\";\n TVM_FFI_ICHECK(topk_indices.sizes()[1] == topk)\n << \"topk_indices must have the same number of topk as scores\";\n TVM_FFI_ICHECK(topk_values.dtype() == data_type)\n << \"topk_values must have the same dtype as scores\";\n TVM_FFI_ICHECK(encode_dlpack_dtype(topk_indices.dtype()) == int32_code)\n << \"topk_indices must be int32 dtype\";\n\n // Validate and extract routing_replay_out\n // NOTE: dim0 >= num_tokens is intentionally NOT checked — with CUDA graphs the buffer\n // is pre-allocated at maximum batch size and reused across steps with varying num_tokens.\n // The kernel only writes to indices [0, num_tokens), so a larger buffer is safe.\n constexpr int64_t int16_code_val = encode_dlpack_dtype(DLDataType{kDLInt, 16, 1});\n int16_t* replay_ptr = nullptr;\n if (routing_replay_out.has_value()) {\n auto replay = routing_replay_out.value();\n TVM_FFI_ICHECK(replay.device().device_type == kDLCUDA)\n << \"routing_replay_out must be a CUDA tensor\";\n TVM_FFI_ICHECK(replay.device().device_id == scores.device().device_id)\n << \"routing_replay_out must be on the same device as scores\";\n TVM_FFI_ICHECK(replay.ndim() == 2)\n << \"routing_replay_out must be a 2D Tensor [num_tokens, topk]\";\n TVM_FFI_ICHECK(replay.sizes()[1] == topk) << \"routing_replay_out dim1 must equal topk\";\n TVM_FFI_ICHECK(encode_dlpack_dtype(replay.dtype()) == int16_code_val)\n << \"routing_replay_out must be int16 dtype\";\n replay_ptr = reinterpret_cast<int16_t*>(replay.data_ptr());\n }\n\n auto stream = get_stream(scores.device());\n using namespace tensorrt_llm::kernels;\n switch (encode_dlpack_dtype(data_type)) {\n case float16_code:\n // Handle Float16\n switch (encode_dlpack_dtype(bias_type)) {\n case float16_code:\n invokeNoAuxTc<half, half, half, int32_t>(\n reinterpret_cast<half*>(scores.data_ptr()), reinterpret_cast<half*>(bias.data_ptr()),\n reinterpret_cast<half*>(topk_values.data_ptr()),\n reinterpret_cast<int32_t*>(topk_indices.data_ptr()), num_tokens, num_experts, n_group,\n topk_group, topk, routed_scaling_factor, launch_with_pdl, stream, replay_ptr);\n break;\n case float32_code:\n invokeNoAuxTc<half, float, half, int32_t>(\n reinterpret_cast<half*>(scores.data_ptr()), reinterpret_cast<float*>(bias.data_ptr()),\n reinterpret_cast<half*>(topk_values.data_ptr()),\n reinterpret_cast<int32_t*>(topk_indices.data_ptr()), num_tokens, num_experts, n_group,\n topk_group, topk, routed_scaling_factor, launch_with_pdl, stream, replay_ptr);\n break;\n case bfloat16_code:\n invokeNoAuxTc<half, __nv_bfloat16, half, int32_t>(\n reinterpret_cast<half*>(scores.data_ptr()),\n reinterpret_cast<__nv_bfloat16*>(bias.data_ptr()),\n reinterpret_cast<half*>(topk_values.data_ptr()),\n reinterpret_cast<int32_t*>(topk_indices.data_ptr()), num_tokens, num_experts, n_group,\n topk_group, topk, routed_scaling_factor, launch_with_pdl, stream, replay_ptr);\n break;\n default:\n throw std::invalid_argument(\n \"Invalid bias dtype, only supports float16, float32, and bfloat16\");\n break;\n }\n break;\n case float32_code:\n switch (encode_dlpack_dtype(bias_type)) {\n case float32_code:\n invokeNoAuxTc<float, float, float, int32_t>(\n reinterpret_cast<float*>(scores.data_ptr()),\n reinterpret_cast<float*>(bias.data_ptr()),\n reinterpret_cast<float*>(topk_values.data_ptr()),\n reinterpret_cast<int32_t*>(topk_indices.data_ptr()), num_tokens, num_experts, n_group,\n topk_group, topk, routed_scaling_factor, launch_with_pdl, stream, replay_ptr);\n break;\n case float16_code:\n invokeNoAuxTc<float, half, float, int32_t>(\n reinterpret_cast<float*>(scores.data_ptr()), reinterpret_cast<half*>(bias.data_ptr()),\n reinterpret_cast<float*>(topk_values.data_ptr()),\n reinterpret_cast<int32_t*>(topk_indices.data_ptr()), num_tokens, num_experts, n_group,\n topk_group, topk, routed_scaling_factor, launch_with_pdl, stream, replay_ptr);\n break;\n case bfloat16_code:\n invokeNoAuxTc<float, __nv_bfloat16, float, int32_t>(\n reinterpret_cast<float*>(scores.data_ptr()),\n reinterpret_cast<__nv_bfloat16*>(bias.data_ptr()),\n reinterpret_cast<float*>(topk_values.data_ptr()),\n reinterpret_cast<int32_t*>(topk_indices.data_ptr()), num_tokens, num_experts, n_group,\n topk_group, topk, routed_scaling_factor, launch_with_pdl, stream, replay_ptr);\n break;\n default:\n throw std::invalid_argument(\n \"Invalid bias dtype, only supports float16, float32, and bfloat16\");\n break;\n }\n break;\n case bfloat16_code:\n // Handle BFloat16\n switch (encode_dlpack_dtype(bias_type)) {\n case bfloat16_code:\n invokeNoAuxTc<__nv_bfloat16, __nv_bfloat16, __nv_bfloat16, int32_t>(\n reinterpret_cast<__nv_bfloat16*>(scores.data_ptr()),\n reinterpret_cast<__nv_bfloat16*>(bias.data_ptr()),\n reinterpret_cast<__nv_bfloat16*>(topk_values.data_ptr()),\n reinterpret_cast<int32_t*>(topk_indices.data_ptr()), num_tokens, num_experts, n_group,\n topk_group, topk, routed_scaling_factor, launch_with_pdl, stream, replay_ptr);\n break;\n case float16_code:\n invokeNoAuxTc<__nv_bfloat16, half, __nv_bfloat16, int32_t>(\n reinterpret_cast<__nv_bfloat16*>(scores.data_ptr()),\n reinterpret_cast<half*>(bias.data_ptr()),\n reinterpret_cast<__nv_bfloat16*>(topk_values.data_ptr()),\n reinterpret_cast<int32_t*>(topk_indices.data_ptr()), num_tokens, num_experts, n_group,\n topk_group, topk, routed_scaling_factor, launch_with_pdl, stream, replay_ptr);\n break;\n case float32_code:\n invokeNoAuxTc<__nv_bfloat16, float, __nv_bfloat16, int32_t>(\n reinterpret_cast<__nv_bfloat16*>(scores.data_ptr()),\n reinterpret_cast<float*>(bias.data_ptr()),\n reinterpret_cast<__nv_bfloat16*>(topk_values.data_ptr()),\n reinterpret_cast<int32_t*>(topk_indices.data_ptr()), num_tokens, num_experts, n_group,\n topk_group, topk, routed_scaling_factor, launch_with_pdl, stream, replay_ptr);\n break;\n default:\n throw std::invalid_argument(\n \"Invalid bias dtype, only supports bfloat16, float16, and float32\");\n break;\n }\n break;\n default:\n // Handle other data types\n throw std::invalid_argument(\"Invalid dtype, only supports float16, float32, and bfloat16\");\n break;\n }\n}\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(NoAuxTc, flashinfer::trtllm_dsv3_fused_routing::NoAuxTc);\n} // namespace flashinfer::trtllm_dsv3_fused_routing\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"Developed by the **CAKE team**, the kernels in this PR **outperform** the relevant **SOTA baselines at the time of merge** on the **vast majority of performance benchmark shapes**, matching them otherwise.\n\n| Shape ([#4254](https://github.com/flashinfer-ai/flashinfer/issues/4254)) | B200 CAKE speedup vs FlashInfer baseline | GB300 CAKE speedup vs FlashInfer baseline (original) | CAKE speedup vs Sonic-derived exact graph (B200 / GB300; upstream native exact API unsupported) |\n| --- | ---: | ---: | ---: |\n| T1 E384 k1 G1 kg1 f32/f32 | 1.1829x | 1.5522x | 7.6589x / 9.3881x |\n| T16 E256 k2 G8 kg2 f16/f16 | 1.1059x | 1.3919x | 14.4118x / 18.3243x |\n| replay T1 E256 k4 G8 kg4 bf16 | 1.0440x | 1.3158x | 14.6593x / 18.7105x |\n| replay T7 E256 k1 G1 kg1 bf16 | 1.1974x | 1.5469x | 11.8684x / 15.6094x |\n| replay T8 E256 k1 G1 kg1 bf16 | 1.1974x | 1.5469x | 12.2237x / 15.9063x |\n| replay T32 E256 k1 G1 kg1 bf16 | 1.2101x | 1.5469x | 12.5064x / 16.5156x |\n| replay T64 E256 k1 G1 kg1 bf16 | 1.1948x | 1.5294x | 12.3636x / 15.4710x |\n| embedded T1 | 1.0194x | 1.3086x | 10.0325x / 13.8889x |\n| embedded T4096 | 1.0478x | 1.2665x | 6.0657x / 7.0574x |\n| sample T1024 | 1.0492x | 1.3670x | 11.6803x / 13.6789x |\n| boundary T1 E2 k1 G1 kg1 f16/bf16 PDL-off | 1.1299x | 1.4225x | N/A / N/A |\n| boundary T64 E128 k1 G1 kg1 bf16/f16 PDL-off | 1.1329x | 1.4615x | 11.4131x / 14.4923x |\n| boundary T2 E4 k2 G2 kg1 f32/f16 | 1.1231x | 1.5738x | N/A / N/A |\n| boundary T32 E96 k5 G3 kg2 f16/bf16 | 1.0778x | 1.3590x | N/A / N/A |\n| boundary T7/R64 E256 k8 G8 kg4 bf16/f32 PDL-off | 1.0206x | 1.2771x | 13.2887x / 17.0361x |\n\n| Source benchmark | Value |\n| --- | --- |\n| Contract | FP32 sigmoid; selection-only bias; group top-2/group-top-k; expert top-k; normalization of selected unbiased sigmoid weights; optional caller-owned replay |\n| FlashInfer baseline / Cake candidate | `27a5a2945a2af3a4aaa0d1f659c6933d411bdfed` / `a3f87eb28565eb8361c9a57a0750c15f0cab5f0c` |\n| Timing | the CAKE CUPTI benchmark harness; CUPTI cold-L2; 50 ms warmup; 300 ms window; three rotated arm orders; one complete routing invocation |\n| B200 evidence | Slurm `3764856`; 15/15 correct and above 1.0x; SHA256 `c51261cdd9851996be379b745f6b7c5d51e68f0df8598c68d929aa77a28c51ef` |\n| GB300 evidence | OCI AGA Slurm `514553`; 15/15 correct and above 1.0x; SHA256 `5b4ec42980fa310335584b5322a9771e44876e5beaac526a40529bd28e06451a` |\n| Sonic-MoE | `7396f3e604827d8186c2e16e64b28ee33d3defd0`; native exact DeepSeek router 0/15; derived exact CUDA Graph 12/15 supported and correct on each architecture |\n| Compute Sanitizer | B200 PDL off/on; synccheck 0 errors; memcheck 0 errors; each report SHA256 `c79dadfead541e1080b70be963a5a17bf687850ced3ef49023896d84a22baed4` |\n| Post-merge Cake source gate | Cake `d182e68b993d628b5e8b59e96284637e3363897e`; B200 source export/check SHA256 `d1d2a9fdd042c3555bf23059ff37f5f99aaff352e11b58fc001a21936e1dc48c`; GPU e2e passed; registered CUPTI regression `1.031x` |\n\n| SGLang integration | Value |\n| --- | --- |\n| PR | [sgl-project/sglang#35479](https://github.com/sgl-project/sglang/pull/35479) |\n| SGLang / FlashInfer Cake | `002a0610ffe70d0c41c9b93f54cbd652a6fd7a80` / `a3f87eb28565eb8361c9a57a0750c15f0cab5f0c` |\n| B200 routing tests | `python -m pytest -q test/registered/kernels/ops/moe/test_fused_topk_deepseek.py`; 146 passed |\n| B200 synthetic E2E protocol | 24-layer DeepSeek-V3 routing shape E256/G8/kg4/k8; ABBA; 2 warmups + 5 samples per server; input lengths 7/31/127 |\n| B200 synthetic correctness | exact output token IDs; output logprobs pass `atol=1e-4`; baseline `selected_backend=default`; candidate `selected_backend=cake` |\n| B200 synthetic evidence | Slurm `3764856`; SHA256 `55d673ec330854143ddd57e21bce681d158a7e49b4cbf2332f893d953604957c` |\n| GB300 real-model protocol | 4x NVIDIA GB300; DeepSeek-V3-0324 `e9b33add`; TP4/EP4; ABBA=`default,Cake,Cake,default`; 200 official GSM8K test questions; five-shot; temperature 0; 128 fixed 512-in/128-out serving requests; concurrency 16 |\n| GB300 server command | `python -m sglang.launch_server --model-path <DeepSeek-V3-0324-e9b33add> --trust-remote-code --tp 4 --ep 4 --moe-runner-backend deep_gemm --fp8-gemm-backend flashinfer_trtllm --disable-shared-experts-fusion --cuda-graph-backend-decode disabled --cuda-graph-backend-prefill disabled --disable-flashinfer-autotune --disable-radix-cache --chunked-prefill-size 4096 --context-length 4096 --max-running-requests 16 --random-seed 12345` |\n| GB300 GSM8K command | `python benchmark/gsm8k/bench_sglang.py --backend srt --data-path <official-test.jsonl> --num-shots 5 --num-questions 200 --max-new-tokens 512 --temperature 0 --top-p 1 --parallel 16` |\n| GB300 serving command | `python -m sglang.benchmark.serving --backend sglang --dataset-name random-ids --num-prompts 128 --random-input-len 512 --random-output-len 128 --random-range-ratio 1 --request-rate inf --max-concurrency 16 --seed 42` |\n| GB300 GSM8K accuracy | default `193/200, 193/200` (96.5% median); Cake `191/200, 191/200` (95.5% median); invalid `0/200` in every arm; paired McNemar exact p=`0.754, 0.727` versus the first default arm |\n| GB300 route proof | both default arms launched only `deepseek_v3_topk_kernel`; both Cake arms launched only `kernel_cake_deepseek_routing_grouped_k8g4_f32_f32`; each launch audit had exact expert IDs and routing weights within `atol=rtol=1e-4` |\n| GB300 real-model evidence | OCI AGA Slurm `514454`; SHA256 `ad36974732243993c6d84a2a8ee3430b6e21e87979abaddefcc8b55eea33fc16` |\n\n| B200 synthetic SGLang metric (ABBA median) | b1 speedup | b16 speedup | b64 speedup |\n| --- | ---: | ---: | ---: |\n| Client wall / output throughput | 0.9970x | 1.0001x | 0.9972x |\n| Per-request E2E latency | 0.9969x | 0.9957x | 1.0255x |\n| TTFT | 0.9882x | 1.0107x | 1.0136x |\n| TPOT | 1.0012x | 1.0022x | 1.0956x |\n\n| GB300 real DeepSeek-V3 ABBA metric | default / Cake median | Cake speedup |\n| --- | ---: | ---: |\n| GSM8K wall latency | 275.259 / 283.131 s | 0.9722x |\n| GSM8K output throughput | 71.734 / 71.115 token/s | 0.9914x |\n| Serving request throughput | 0.54063 / 0.54117 req/s | 1.0010x |\n| Serving output throughput | 69.2005 / 69.2693 token/s | 1.0010x |\n| Mean E2E latency | 28045.81 / 28029.82 ms | 1.0006x |\n| Mean TTFT | 2326.10 / 2335.58 ms | 0.9959x |\n| Mean TPOT | 202.517 / 202.317 ms | 1.0010x |\n\n\n<!-- cake-shared-references:start -->\n## References\n\nThe shared reference corpus for CAKE kernel development includes the following projects, documentation, and existing CAKE work:\n\n- **GPU programming and instructions:** [NVIDIA CUDA Programming Guide](https://docs.nvidia.com/cuda/cuda-programming-guide/index.html), [NVIDIA PTX ISA](https://docs.nvidia.com/cuda/parallel-thread-execution/), and gau-nernst's [tcgen05 tutorial](https://gau-nernst.github.io/tcgen05/) and [CUDA kernel examples](https://github.com/gau-nernst/learn-cuda).\n- **Kernel programming libraries and compilers:** [NVIDIA CUTLASS / CuTe](https://github.com/NVIDIA/cutlass), [Triton](https://github.com/triton-lang/triton), [TileLang](https://github.com/tile-ai/tilelang), [NVIDIA cuTile Python](https://github.com/NVIDIA/cutile-python), and [ThunderKittens](https://github.com/HazyResearch/ThunderKittens) ([ThunderKittens 2.0 techniques](https://hazyresearch.stanford.edu/blog/2026-02-19-tk-2)).\n- **Attention and inference:** [FlashAttention (including Hopper and CuTe implementations)](https://github.com/Dao-AILab/flash-attention), [FlashInfer, including its TRT-LLM kernel integration](https://github.com/flashinfer-ai/flashinfer), [Flash Linear Attention](https://github.com/fla-org/flash-linear-attention), [SageAttention](https://github.com/thu-ml/SageAttention), [FlashAttention-FP4](https://github.com/hao-ai-lab/flash-attention-fp4), and [FastVideo](https://github.com/hao-ai-lab/FastVideo).\n- **GEMM and MoE:** [DeepGEMM](https://github.com/deepseek-ai/DeepGEMM), [SonicMoE](https://github.com/Dao-AILab/sonic-moe), [Alpha-MoE](https://github.com/Aleph-Alpha/Alpha-MoE), and [Mixture of Kittens](https://github.com/cursor/mixture-of-kittens).\n- **Clustering and nearest-neighbor kernels:** [Flash K-Means](https://github.com/svg-project/flash-kmeans) and [FlashLib](https://github.com/FlashML-org/flashlib).\n- **Existing CAKE implementations and PRs:** [CAKE-generated kernel progress tracker and PR index (#4254)](https://github.com/flashinfer-ai/flashinfer/issues/4254).\n\nThese are corpus-level references. PR-specific implementation details, changes, and benchmark references are documented above.\n<!-- cake-shared-references:end -->\n\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"T1 E384 k1 G1 kg1 f32/f32\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.1829, \"speedup\": 1.1829}, {\"scope\": \"kernel\", \"hardware\": \"GB300\", \"model\": null, \"shape\": \"T1 E384 k1 G1 kg1 f32/f32\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.5522, \"speedup\": 1.5522}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"T16 E256 k2 G8 kg2 f16/f16\", \"batch_size\": 16, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 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\"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.2665, \"speedup\": 1.2665}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"sample T1024\", \"batch_size\": 1024, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.0492, \"speedup\": 1.0492}, {\"scope\": \"kernel\", \"hardware\": \"GB300\", \"model\": null, \"shape\": \"sample T1024\", \"batch_size\": 1024, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.367, \"speedup\": 1.367}]"},"kernel_speedup":{"kind":"number","value":1.2101,"string":"1.2101"},"e2e_speedup":{"kind":"number","value":1.0006,"string":"1.0006"}}},{"rowIdx":1084,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"7319c448b7a62fb8deb3de2c878794194cb23558"},"date":{"kind":"string","value":"2026-08-18T13:37:43-07:00"},"pr_number":{"kind":"number","value":4540,"string":"4,540"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/4540"},"title":{"kind":"string","value":"perf(moe): fold W4A16 SiTU reciprocals (#4540)"},"message":{"kind":"string","value":"perf(moe): fold W4A16 SiTU reciprocals (#4540)\n\n<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\n@humansand\n\nThis is a focused follow-up to #4394 and #4506 for the CuTe DSL W4A16\nSiTU path.\n\n- Preserve `situ_beta` as a Python scalar so the existing shared\n`situ_f32` helper folds its FP32 reciprocal while tracing.\n- Precompute the optional up-branch reciprocal with `f32_reciprocal`,\nthen replace both per-element divisions with multiplies.\n- Reuse the existing gate-only and gate-plus-up SiTU accuracy cases,\nwhich already exercise both reciprocal paths changed here.\n- Leave GeGLU, ordinary SwiGLU, ReLU2, GEMM2, routing, and finalize\nbehavior unchanged.\n\nThe reciprocal is derived from the FP32-rounded beta, matching the value\nused by the kernel's multiply-back step. Reciprocal multiplication is\ntolerance-equivalent to division, but is not guaranteed to be\nbitwise-identical.\n\n## 🔍 Related Issues\n\n- #4394\n- #4506\n\n## ⏱️ Performance\n\n### Environment and workload\n\n- Image: `nvcr.io/nvidia/pytorch:26.05-py3` (`linux/amd64` digest\n`sha256:ca73b4795f0d3ae27e9cd81b1b1f1b7fc6c0a129f7d51a359d2326e95af48a3d`)\n- Devbox: `c1`, host `B200-147`, 8 x NVIDIA B200; measurements pinned to\nGPU 0 at a 1000 W power limit\n- Driver: `580.126.09`\n- Python: `3.12.3`\n- PyTorch: `2.12.0a0+5aff3928d8.nv26.05`\n- PyTorch CUDA / system nvcc: `13.2` / `13.2` (`cuda_13.2.r13.2`,\ncompiler `37668154_0`)\n- FlashInfer: `0.6.18`\n- `nvidia-cutlass-dsl`: `4.7.0`\n- `cupti-python`: `13.3.1`\n- Baseline: `f4043ef18c92f38e0c70da76ca40b26d36318eed` (the #4394 merge\non `main`)\n- Candidate kernel: `093fd3d7d24fa01afa16445cae230e477335f3fc`\n- Workload: pre-routed W4A16 fused MoE, BF16 activations, NVFP4 weights,\n`E=896`, `topK=16`, `H=3584`, `I=3072`, `situ_beta=4.0`,\n`situ_linear_beta=25.0`\n\nThis is a Kimi-K3-shaped W4A16 derivative. It does not claim to use\nKimi-K3's native MXFP4 weight format.\n\n### Method\n\n- One fresh process per adjacent `A1 baseline -> B candidate -> A2\nbaseline` arm on the same GPU and node.\n- A1 generated a single autotune cache; B and A2 loaded it cache-only.\nThe selected tactic was then passed explicitly to every timed call, and\nexact A1/B/A2 tactic equality was validated for every shape.\n- Full weight construction and quantization, compilation, and autotuning\nwere outside the timed region.\n- CUDA-event timing used `use_cuda_graph=False`, `cold_l2_cache=True`,\n10 warmups, 50 measured samples per repeat, and 3 repeats per arm.\n- Every measured shape reported finite output.\n- Derived baseline latency is the median of the six A1+A2 repeat\nmedians. Candidate latency is the median of the three B repeat medians.\n`speedup = baseline / candidate`, so values above `1.0x` are faster.\n\nSelected tactics for both GEMMs were identical across A1/B/A2:\n\n| Tokens | Tactic per GEMM |\n|---:|:---|\n| 1, 8, 64, 512 | `((256, 16, 256), (2, 1), true)` |\n| 2048 | `((256, 64, 256), (2, 1), true)` |\n| 4096 | `((128, 128, 256), (2, 1), true)` |\n| 8192 | `((256, 192, 256), (2, 1), true)` |\n\n### Raw CUDA-event repeat medians\n\nAll values are milliseconds.\n\n| Tokens | A1 r1 | A1 r2 | A1 r3 | B r1 | B r2 | B r3 | A2 r1 | A2 r2 |\nA2 r3 |\n|---:|---:|---:|---:|---:|---:|---:|---:|---:|---:|\n| 1 | 0.109600 | 0.109760 | 0.110400 | 0.107648 | 0.108432 | 0.108384 |\n0.108448 | 0.108544 | 0.108560 |\n| 8 | 0.611312 | 0.611328 | 0.611328 | 0.607264 | 0.607264 | 0.607232 |\n0.610848 | 0.611360 | 0.610416 |\n| 64 | 4.231168 | 4.325312 | 4.294672 | 4.063312 | 4.272128 | 4.251680 |\n4.149184 | 4.296640 | 4.292672 |\n| 512 | 4.392864 | 4.448288 | 4.446208 | 4.432448 | 4.429984 | 4.433216\n| 4.437952 | 4.442624 | 4.438000 |\n| 2048 | 5.702688 | 5.713840 | 5.715040 | 5.338224 | 5.483472 | 5.453744\n| 5.466608 | 5.663840 | 5.660288 |\n| 4096 | 7.799760 | 7.794224 | 7.797776 | 6.896560 | 7.029232 | 7.144368\n| 7.370256 | 7.487568 | 7.549360 |\n| 8192 | 11.601920 | 11.608000 | 11.610096 | 10.840064 | 10.907632 |\n10.906624 | 11.527200 | 11.636208 | 11.628608 |\n\n### Derived CUDA-event results\n\n| Tokens | Baseline median (ms) | Candidate median (ms) | Speedup |\n|---:|---:|---:|---:|\n| 1 | 0.109080 | 0.108384 | 1.0064x |\n| 8 | 0.611320 | 0.607264 | 1.0067x |\n| 64 | 4.293672 | 4.251680 | 1.0099x |\n| 512 | 4.440312 | 4.432448 | 1.0018x |\n| 2048 | 5.683264 | 5.453744 | 1.0421x |\n| 4096 | 7.671792 | 7.029232 | 1.0914x |\n| 8192 | 11.609048 | 10.906624 | 1.0644x |\n\nThe 1-512-token changes are at or below 1% and are treated as noise. The\nmeasurable result is `1.0421x-1.0914x` at 2048-8192 tokens. At 4096\ntokens the two event-timed baseline arms drifted (`~7.798 ms` A1 versus\n`~7.488 ms` A2), but the candidate stayed below both arms; the separate\nCUPTI timing-backend spot-check below corroborates the direction.\n\n### CUPTI 4096-token spot-check\n\nThis used the same fixed tactic and cold-L2 path in fresh A1/B/A2\nprocesses, with 10 warmups and 50 samples per arm. CUPTI mode permits\none repeat per process.\n\n| Arm | Revision | Median (ms) |\n|:---|:---|---:|\n| A1 baseline | `f4043ef18c92f38e0c70da76ca40b26d36318eed` | 7.234587 |\n| B candidate | `093fd3d7d24fa01afa16445cae230e477335f3fc` | 6.889771 |\n| A2 baseline | `f4043ef18c92f38e0c70da76ca40b26d36318eed` | 7.367835 |\n| Bracketing baseline | median of A1 and A2 | 7.301211 |\n\nThe CUPTI spot-check shows a `1.0597x` speedup (`7.301211 / 6.889771`),\ncorresponding to 5.64% lower latency.\n\n### Reproduction commands\n\nThe benchmark harness is retained locally and in branch commit\n`ae6f92f5`, but is intentionally absent from the PR's final tree. The\nrun used the same script before a formatting-only `ruff format` pass. To\nrecover that equivalent harness from branch history, then verify that A1\nstarts without an existing tactic cache:\n\n```bash\ngit show ae6f92f5:benchmarks/bench_w4a16_situ.py \\\n > /hai-workspace/w4a16-situ-tools/bench_w4a16_situ.py\nmkdir -p /hai-workspace/w4a16-situ-results\ntest ! -e /hai-workspace/w4a16-situ-results/tactics.json\n```\n\nThe following are the exact CUDA-event arm commands:\n\n```bash\ncd /hai-workspace/flashinfer-baseline\nCUDA_VISIBLE_DEVICES=0 FLASHINFER_DISABLE_VERSION_CHECK=1 \\\nFLASHINFER_WORKSPACE_BASE=/hai-workspace/cache-baseline \\\nPYTHONPATH=/hai-workspace/flashinfer-baseline \\\npython3 /hai-workspace/w4a16-situ-tools/bench_w4a16_situ.py \\\n --arm A1-baseline \\\n --revision f4043ef18c92f38e0c70da76ca40b26d36318eed \\\n --tokens 1,8,64,512,2048,4096,8192 \\\n --warmup 10 --iters 50 --repeats 3 --timing event \\\n --autotune-cache /hai-workspace/w4a16-situ-results/tactics.json \\\n --json-out /hai-workspace/w4a16-situ-results/A1-baseline.json\n\ncd /hai-workspace/flashinfer-candidate\nCUDA_VISIBLE_DEVICES=0 FLASHINFER_DISABLE_VERSION_CHECK=1 \\\nFLASHINFER_WORKSPACE_BASE=/hai-workspace/cache-tests-candidate \\\nPYTHONPATH=/hai-workspace/flashinfer-candidate \\\npython3 /hai-workspace/w4a16-situ-tools/bench_w4a16_situ.py \\\n --arm B-candidate \\\n --revision 093fd3d7d24fa01afa16445cae230e477335f3fc \\\n --tokens 1,8,64,512,2048,4096,8192 \\\n --warmup 10 --iters 50 --repeats 3 --timing event \\\n --autotune-cache /hai-workspace/w4a16-situ-results/tactics.json \\\n --json-out /hai-workspace/w4a16-situ-results/B-candidate.json\n\ncd /hai-workspace/flashinfer-baseline\nCUDA_VISIBLE_DEVICES=0 FLASHINFER_DISABLE_VERSION_CHECK=1 \\\nFLASHINFER_WORKSPACE_BASE=/hai-workspace/cache-baseline \\\nPYTHONPATH=/hai-workspace/flashinfer-baseline \\\npython3 /hai-workspace/w4a16-situ-tools/bench_w4a16_situ.py \\\n --arm A2-baseline \\\n --revision f4043ef18c92f38e0c70da76ca40b26d36318eed \\\n --tokens 1,8,64,512,2048,4096,8192 \\\n --warmup 10 --iters 50 --repeats 3 --timing event \\\n --autotune-cache /hai-workspace/w4a16-situ-results/tactics.json \\\n --json-out /hai-workspace/w4a16-situ-results/A2-baseline.json\n```\n\nThe CUPTI commands changed only the arm/output labels and timing\narguments:\n\n```bash\ncd /hai-workspace/flashinfer-baseline\nCUDA_VISIBLE_DEVICES=0 FLASHINFER_DISABLE_VERSION_CHECK=1 \\\nFLASHINFER_WORKSPACE_BASE=/hai-workspace/cache-baseline \\\nPYTHONPATH=/hai-workspace/flashinfer-baseline \\\npython3 /hai-worksp"},"path":{"kind":"string","value":"flashinfer/fused_moe/cute_dsl/blackwell/moe_w4a16_kernel.py"},"language":{"kind":"string","value":"cute_dsl"},"license":{"kind":"string","value":"BSD-3-Clause"},"before_code":{"kind":"string","value":"# Copyright (c) 2025 - 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.\n# SPDX-License-Identifier: BSD-3-Clause\n\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions are met:\n\n# 1. Redistributions of source code must retain the above copyright notice, this\n# list of conditions and the following disclaimer.\n\n# 2. Redistributions in binary form must reproduce the above copyright notice,\n# this list of conditions and the following disclaimer in the documentation\n# and/or other materials provided with the distribution.\n\n# 3. Neither the name of the copyright holder nor the names of its\n# contributors may be used to endorse or promote products derived from\n# this software without specific prior written permission.\n\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n\"\"\"SM100 grouped GEMM for NVFP4 expert weights and BF16 activations.\n\nEach routed-row tile selects one expert through FlashInfer's MoE sort metadata.\nThe kernel decodes each 16-value E2M1 weight block and its E4M3 scale to BF16,\nthen executes BF16 tensor-core MMA with FP32 accumulation.\n\"\"\"\n\nfrom math import ceil, log2\nfrom typing import Optional, Union\n\nimport cuda.bindings.driver as cuda\nimport cutlass\nimport cutlass.cute as cute\nimport cutlass.pipeline as pipeline\nfrom cutlass.pipeline import pipeline_init_arrive, pipeline_init_wait\nimport cutlass.utils as utils\nimport cutlass.utils.blackwell_helpers as sm100_utils\nimport cutlass.utils.blockscaled_layout as blockscaled_utils\nimport cutlass.utils.mixed_input_helpers as mixed_input_utils\nfrom cutlass.utils.mixed_input_helpers import TransformMode\nfrom cutlass.cute.nvgpu import cpasync, tcgen05\n\nfrom flashinfer.tllm_enums import (\n ActivationType,\n DEFAULT_SWIGLU_ALPHA,\n DEFAULT_SWIGLU_BETA,\n DEFAULT_SWIGLU_LIMIT,\n)\n\nfrom ..moe_utils import validate_cute_dsl_moe_situ_config\nfrom .moe_w4a16_utils import decode_nvfp4_fragment_to_bf16\nfrom .utils import (\n blk_reduce_bf16,\n fmin,\n gelu_tanh_f32,\n griddepcontrol_launch_dependents,\n griddepcontrol_wait,\n situ_f32,\n tanh_f32,\n)\n\n\n_NVFP4_SCALE_GRANULARITY_M = 1\n_NVFP4_SCALE_GRANULARITY_K = 16\n_TMA_CACHE_HINT_EVICT_FIRST = 0x12F0000000000000\n_TMA_CACHE_HINT_EVICT_LAST = 0x14F0000000000000\n\n\nclass Sm100W4A16GroupedGemmKernel:\n \"\"\"Warp-specialized grouped GEMM for the W4A16 MoE pipeline.\"\"\"\n\n def __init__(\n self,\n acc_dtype: type[cutlass.Numeric],\n use_2cta_instrs: bool,\n mma_tiler_mnk: tuple[int, int, int],\n cluster_shape_mn: tuple[int, int],\n group_count: int,\n activation_type: Optional[int],\n swiglu_alpha: float,\n swiglu_beta: float,\n swiglu_limit: float,\n situ_beta: Optional[float],\n situ_linear_beta: Optional[float],\n use_fused_finalize: bool,\n enable_pdl: bool,\n use_clc_scheduler: bool,\n raster_along_m: bool,\n transform_fragment_size: int,\n ):\n \"\"\"Initialize the W4A16 grouped GEMM configuration.\"\"\"\n self.group_count = group_count\n self.acc_dtype = acc_dtype\n self.use_2cta_instrs = use_2cta_instrs\n self.cluster_shape_mn = cluster_shape_mn\n self.mma_tiler = mma_tiler_mnk\n if activation_type not in (\n None,\n ActivationType.Swiglu.value,\n ActivationType.GegluTanh.value,\n ActivationType.Relu2.value,\n ):\n raise ValueError(\n f\"unsupported W4A16 epilogue activation: {activation_type}\"\n )\n self.fuse_activation = activation_type is not None\n self.use_clc_scheduler = use_clc_scheduler\n self.raster_along_m = raster_along_m\n self.transform_fragment_size = transform_fragment_size\n if activation_type is None:\n if situ_beta is not None or situ_linear_beta is not None:\n raise ValueError(\"SiTU parameters require an activation\")\n else:\n validate_cute_dsl_moe_situ_config(\n ActivationType(activation_type), situ_beta, situ_linear_beta\n )\n self.activation_type = activation_type\n self.gated = activation_type in (\n ActivationType.Swiglu.value,\n ActivationType.GegluTanh.value,\n )\n self.swiglu_alpha = swiglu_alpha\n self.swiglu_beta = swiglu_beta\n self.swiglu_limit = swiglu_limit\n self.situ_beta = situ_beta\n self.situ_linear_beta = situ_linear_beta\n self.parameterized_swiglu = (\n swiglu_alpha != DEFAULT_SWIGLU_ALPHA\n or swiglu_beta != DEFAULT_SWIGLU_BETA\n or swiglu_limit != DEFAULT_SWIGLU_LIMIT\n )\n self.output_m_factor = 2 if self.gated else 1\n if self.gated and use_fused_finalize:\n raise ValueError(\n \"W4A16 fused finalize is only implemented for the non-gated epilogue\"\n )\n self.use_fused_finalize = use_fused_finalize\n self.enable_pdl = enable_pdl\n self.cta_group = (\n tcgen05.CtaGroup.TWO if self.use_2cta_instrs else tcgen05.CtaGroup.ONE\n )\n self.epilog_warp_id = (0, 1, 2, 3)\n self.mma_warp_id = 4\n self.schedule_warp_id = 5\n self.weight_tma_warp_id = 6\n self.activation_tma_warp_id = 7\n self.num_transform_warpgroups = 2\n self.transform_warp_id = tuple(range(8, 8 + 4 * self.num_transform_warpgroups))\n self.num_transform_warps = len(self.transform_warp_id)\n # Keep the role-control warpgroup on one absolute register target.\n # Transform warps retain the 128-register launch default.\n self.num_regs_epilogue_warps = 176\n self.num_regs_generic_warps = 80\n self.threads_per_cta = 32 * (\n max(\n (\n self.mma_warp_id,\n self.schedule_warp_id,\n self.weight_tma_warp_id,\n self.activation_tma_warp_id,\n *self.epilog_warp_id,\n *self.transform_warp_id,\n )\n )\n + 1\n )\n\n self.epilog_sync_barrier = pipeline.NamedBarrier(\n 1, 32 * len(self.epilog_warp_id)\n )\n self.tmem_ptr_sync_barrier = pipeline.NamedBarrier(2, self.threads_per_cta)\n self.sched_sync_barrier = pipeline.NamedBarrier(5, 32)\n\n self.smem_buffer_align_bytes = 1024\n\n def _setup_attributes(self):\n \"\"\"Derive static MMA, pipeline, and storage layouts from operand types.\"\"\"\n self.transform_a_source = mixed_input_utils.get_transform_a_source(\n self.a_major_mode\n )\n tiled_mma = sm100_utils.make_trivial_tiled_mma(\n self.mma_dtype,\n self.a_major_mode,\n self.b_major_mode,\n self.acc_dtype,\n self.cta_group,\n self.mma_tiler[:2],\n self.transform_a_source,\n )\n self.cta_tile_shape_mnk = (\n self.mma_tiler[0] // cute.size(tiled_mma.thr_id.shape),\n self.mma_tiler[1],\n self.mma_tiler[2],\n )\n self.mma_tiler_c = (\n self.mma_tiler[0] // self.output_m_factor,\n self.mma_tiler[1],\n self.mma_tiler[2],\n )\n self.cta_tile_shape_mnk_c = (\n self.cta_tile_shape_mnk[0] // self.output_m_factor,\n self.cta_tile_shape_mnk[1],\n self.cta_tile_shape_mnk[2],\n )\n self.cluster_layout_vmnk = cute.tiled_divide(\n cute.make_layout((*self.cluster_shape_mn, 1)),\n (tiled_mma.thr_id.shape,),\n )\n self.num_mcast_ctas_a = cute.size(self.cluster_layout_vmnk.shape[2])\n self.num_mcast_ctas_b = cute.size(self.cluster_layout_vmnk.shape[1])\n self.is_a_mcast = self.num_mcast_ctas_a > 1\n self.is_b_mcast = self.num_mcast_ctas_b > 1\n\n default_epi_tile = sm100_utils.compute_epilogue_tile_shape(\n self.cta_tile_shape_mnk,\n self.use_2cta_instrs,\n self.c_layout,\n self.c_dtype,\n )\n self.epi_tile = (\n (self.cta_tile_shape_mnk_c[0], default_epi_tile[1])\n if self.gated\n else default_epi_tile\n )\n self.epi_tile_n = cute.size(self.epi_tile[1])\n\n (\n self.num_load2trans_stage,\n self.num_trans2mma_stage,\n self.num_acc_stage,\n self.num_c_stage,\n self.num_tile_info_stage,\n self.num_acc_tmem_cols,\n self.num_a_tmem_cols,\n ) = self._compute_stages_and_tmem_cols(\n tiled_mma,\n self.mma_tiler,\n self.cta_tile_shape_mnk,\n self.epi_tile,\n self.a_dtype,\n self.b_dtype,\n self.c_dtype,\n self.c_layout,\n self.transform_a_source,\n self.smem_buffer_align_bytes,\n self.use_fused_finalize,\n self.use_clc_scheduler,\n )\n\n # TMEM allocation requires power-of-two column alignment.\n self.num_tmem_alloc_cols = cute.round_up(\n self.num_acc_tmem_cols + self.num_a_tmem_cols,\n cute.arch.get_min_tmem_alloc_cols(\"sm_100\"),\n )\n self.num_tmem_alloc_cols = 2 ** (ceil(log2(self.num_tmem_alloc_cols)))\n self.c_smem_layout_staged = sm100_utils.make_smem_layout_epi(\n self.c_dtype,\n self.c_layout,\n self.epi_tile,\n self.num_c_stage,\n )\n (\n self.smem_layout_a,\n self.smem_layout_a_transform,\n self.smem_layout_b,\n ) = mixed_input_utils.compute_smem_layout(\n tiled_mma,\n self.mma_tiler,\n self.a_dtype,\n self.b_dtype,\n self.num_load2trans_stage,\n self.num_trans2mma_stage,\n )\n scale_tile_shape = (\n self.cta_tile_shape_mnk[0],\n self.mma_tiler[2],\n )\n # The transform and TMA partitions use different logical views of the\n # same block-scaled shared-memory storage.\n scale_smem_layout = blockscaled_utils.make_smem_layout_sf(\n scale_tile_shape,\n _NVFP4_SCALE_GRANULARITY_K,\n self.num_load2trans_stage,\n )\n scale_smem_layout_per_stage = cute.slice_(scale_smem_layout, (None, None, 0))\n trivial_swizzle = cute.make_swizzle(0, 4, 3)\n self.smem_layout_scale_per_stage = cute.make_composed_layout(\n trivial_swizzle, 0, scale_smem_layout_per_stage\n )\n self.smem_layout_scale = cute.make_composed_layout(\n trivial_swizzle, 0, scale_smem_layout\n )\n self.smem_layout_scale_tma = blockscaled_utils.make_smem_layout_sfa(\n tiled_mma,\n self.mma_tiler,\n _NVFP4_SCALE_GRANULARITY_K,\n self.num_load2trans_stage,\n )\n\n @cute.jit\n def _setup_transform_partitions(\n self,\n tiled_mma: cute.TiledMma,\n copy_atom_a_input: cute.CopyAtom,\n copy_atom_a_transform: cute.CopyAtom,\n sA_transform_input: cute.Tensor,\n a_smem_layout_transform: cute.ComposedLayout,\n sA_transform: cute.Tensor,\n tCsS: cute.Tensor,\n accumulators: cute.Tensor,\n transform_tidx: cutlass.Int32,\n transform_group_idx: cutlass.Int32,\n ):\n if cutlass.const_expr(self.transform_a_source == tcgen05.OperandSource.TMEM):\n tmem_ptr_transform = cute.recast_ptr(\n accumulators.iterator + self.num_acc_tmem_cols,\n dtype=self.mma_dtype,\n )\n transform_destination = cute.make_tensor(\n tmem_ptr_transform,\n tiled_mma.make_fragment_A(a_smem_layout_transform.outer).layout,\n )\n else:\n transform_destination = sA_transform\n\n src_copy_a, dst_copy_a, tAsA_input, tAsA_transform = (\n mixed_input_utils.transform_partition(\n self.transform_a_source,\n TransformMode.ConvertScale,\n copy_atom_a_input,\n copy_atom_a_transform,\n sA_transform_input,\n transform_destination,\n transform_tidx,\n )\n )\n num_transform_blocks = cute.size(tAsA_input, mode=[3])\n assert num_transform_blocks % self.num_transform_warpgroups == 0, (\n \"A blocks must divide evenly across transform warpgroups\"\n )\n blocks_per_transform_group = (\n num_transform_blocks // self.num_transform_warpgroups\n )\n transform_group_tiler = (\n None,\n None,\n None,\n blocks_per_transform_group,\n None,\n )\n transform_group_coord = (\n None,\n None,\n None,\n (None, transform_group_idx),\n None,\n )\n tAsA_input = cute.logical_divide(tAsA_input, transform_group_tiler)[\n transform_group_coord\n ]\n tAsA_transform = cute.logical_divide(tAsA_transform, transform_group_tiler)[\n transform_group_coord\n ]\n\n a_stage_coord = (None,) * (cute.rank(tAsA_input) - 1) + (0,)\n tArA = cute.make_rmem_tensor(\n tAsA_input[a_stage_coord].shape,\n tAsA_input.element_type,\n )\n tArA_transform = cute.make_rmem_tensor(\n tAsA_input[a_stage_coord].shape,\n self.mma_dtype,\n )\n\n smem_thr_copy_S = src_copy_a.get_slice(transform_tidx)\n tSsS_trans = smem_thr_copy_S.partition_S(tCsS)\n tSsS_trans = cute.logical_divide(tSsS_trans, transform_group_tiler)[\n transform_group_coord\n ]\n scale_stage_coord = (None,) * (cute.rank(tSsS_trans) - 1) + (0,)\n tSsS_layout_per_stage = tSsS_trans[scale_stage_coord].layout\n tSrS_copy = cute.make_rmem_tensor(\n cute.filter_zeros(tSsS_layout_per_stage).shape,\n self.a_scale_dtype,\n )\n tSrS = cute.make_tensor(\n tSrS_copy.iterator,\n cute.make_layout(\n tSsS_layout_per_stage.shape,\n stride=tSrS_copy.layout.stride,\n ),\n )\n assert cute.size(tSrS, mode=[0]) == cute.size(tArA, mode=[0]), (\n \"tSrS and tArA have different leading dimension\"\n )\n assert cute.size(tSrS) == cute.size(tArA), \"tSrS and tArA have different shape\"\n\n transform_tiler_size = min(\n cute.size(cute.coalesce(tAsA_input.layout), mode=[0]),\n self.transform_fragment_size,\n )\n assert transform_tiler_size % _NVFP4_SCALE_GRANULARITY_K == 0, (\n \"transform fragment must cover whole NVFP4 scale blocks\"\n )\n transform_tiler = cute.make_layout(transform_tiler_size)\n tArA_load = cute.flat_divide(tArA, transform_tiler)\n tArA_load = cute.group_modes(tArA_load, 1, cute.rank(tArA_load))\n scale_tiler = cute.make_layout(\n transform_tiler_size // _NVFP4_SCALE_GRANULARITY_K\n )\n tSrS_load = cute.flat_divide(tSrS_copy, scale_tiler)\n tSrS_load = cute.group_modes(tSrS_load, 1, cute.rank(tSrS_load))\n tArA_transform_store = cute.flat_divide(tArA_transform, transform_tiler)\n tArA_transform_store = cute.group_modes(\n tArA_transform_store,\n 1,\n cute.rank(tArA_transform_store),\n )\n return (\n dst_copy_a,\n tAsA_input,\n tAsA_transform,\n tSsS_trans,\n tSrS_copy,\n tSrS_load,\n tArA_load,\n tArA_transform,\n tArA_transform_store,\n transform_tiler,\n )\n\n @cute.jit\n def _transform_tile(\n self,\n a_load2trans_pipeline: pipeline.PipelineTmaAsync,\n trans2mma_pipeline: pipeline.PipelineAsyncUmma,\n a_load2trans_consumer_state: pipeline.PipelineState,\n trans2mma_producer_state: pipeline.PipelineState,\n dst_copy_a: cute.CopyAtom,\n tAsA_input: cute.Tensor,\n tAsA_transform: cute.Tensor,\n tSsS_trans: cute.Tensor,\n tSrS_copy: cute.Tensor,\n tSrS_load: cute.Tensor,\n tArA_load: cute.Tensor,\n tArA_transform: cute.Tensor,\n tArA_transform_store: cute.Tensor,\n transform_tiler: cute.Layout,\n k_tile_cnt: cutlass.Int32,\n ) -> tuple[pipeline.PipelineState, pipeline.PipelineState]:\n a_load2trans_consumer_state.reset_count()\n peek_load2trans_full_status = cutlass.Boolean(1)\n if a_load2trans_consumer_state.count < k_tile_cnt:\n peek_load2trans_full_status = a_load2trans_pipeline.consumer_try_wait(\n a_load2trans_consumer_state\n )\n trans2mma_producer_state.reset_count()\n peek_trans2mma_empty_status = cutlass.Boolean(1)\n if trans2mma_producer_state.count < k_tile_cnt:\n peek_trans2mma_empty_status = trans2mma_pipeline.producer_try_acquire(\n trans2mma_producer_state\n )\n\n for _k_tile in cutlass.range(0, k_tile_cnt, 1, unroll=1):\n a_load2trans_pipeline.consumer_wait(\n a_load2trans_consumer_state,\n peek_load2trans_full_status,\n )\n a_stage_coord = (None,) * (cute.rank(tAsA_input) - 1) + (\n a_load2trans_consumer_state.index,\n )\n tAsA_input_slice = tAsA_input[a_stage_coord]\n tAsA_input_slice = cute.flat_divide(tAsA_input_slice, transform_tiler)\n tAsA_input_slice = cute.group_modes(\n tAsA_input_slice,\n 1,\n cute.rank(tAsA_input_slice),\n )\n trans2mma_pipeline.producer_acquire(\n trans2mma_producer_state,\n peek_trans2mma_empty_status,\n )\n scale_stage_coord = (None,) * (cute.rank(tSsS_trans) - 1) + (\n a_load2trans_consumer_state.index,\n )\n tSsS_slice = tSsS_trans[scale_stage_coord]\n tSsS_slice_filtered = cute.make_tensor(\n tSsS_slice.iterator,\n cute.filter_zeros(tSsS_slice.layout),\n )\n cute.autovec_copy(tSsS_slice_filtered, tSrS_copy)\n cur_a_load2trans_consumer_state = a_load2trans_consumer_state.clone()\n for idx in cutlass.range_constexpr(cute.size(tArA_load, mode=[1])):\n cute.autovec_copy(\n tAsA_input_slice[(None, idx)],\n tArA_load[(None, idx)],\n )\n if cutlass.const_expr(idx == cute.size(tArA_load, mode=[1]) - 1):\n a_load2trans_consumer_state.advance()\n if a_load2trans_consumer_state.count < k_tile_cnt:\n peek_load2trans_full_status = (\n a_load2trans_pipeline.consumer_try_wait(\n a_load2trans_consumer_state\n )\n )\n packed_fragment = cute.recast_tensor(\n tArA_load[(None, idx)], cutlass.Uint8\n ).load()\n scale_slice = tSrS_load[(None, idx)]\n scale_slice_compact = cute.make_tensor(\n scale_slice.iterator,\n cute.filter_zeros(scale_slice.layout),\n )\n scale_fragment = cute.recast_tensor(\n scale_slice_compact, cutlass.Uint8\n ).load()\n tensor_transformed = decode_nvfp4_fragment_to_bf16(\n packed_fragment,\n scale_fragment,\n )\n tArA_transform_store[(None, idx)].store(tensor_transformed)\n\n a_transform_stage_coord = (None,) * (cute.rank(tAsA_transform) - 1) + (\n trans2mma_producer_state.index,\n )\n mixed_input_utils.store_transformed_a(\n tArA_transform,\n tAsA_transform[a_transform_stage_coord],\n dst_copy_a,\n )\n if cutlass.const_expr(\n self.transform_a_source == tcgen05.OperandSource.TMEM\n ):\n cute.arch.fence_view_async_tmem_store()\n else:\n cute.arch.fence_proxy(\"async.shared\", space=\"cta\")\n a_load2trans_pipeline.consumer_release(cur_a_load2trans_consumer_state)\n trans2mma_pipeline.producer_commit(trans2mma_producer_state)\n trans2mma_producer_state.advance()\n if trans2mma_producer_state.count < k_tile_cnt:\n peek_trans2mma_empty_status = trans2mma_pipeline.producer_try_acquire(\n trans2mma_producer_state\n )\n\n return a_load2trans_consumer_state, trans2mma_producer_state\n\n @cute.jit\n def wrapper(\n self,\n weight_ptr: cute.Pointer,\n weight_sf_ptr: cute.Pointer,\n activation_ptr: cute.Pointer,\n tile_idx_to_expert_idx_ptr: cute.Pointer,\n tile_idx_to_mn_limit_ptr: cute.Pointer,\n num_non_exiting_tiles_ptr: cute.Pointer,\n alpha_ptr: cute.Pointer,\n output_ptr: cute.Pointer,\n permuted_idx_to_expanded_idx_ptr: Optional[cute.Pointer],\n token_final_scales_ptr: Optional[cute.Pointer],\n m: cutlass.Int64,\n n: cutlass.Int64,\n k: cutlass.Int64,\n num_tokens: cutlass.Int64,\n top_k: cutlass.Int64,\n max_active_clusters: cutlass.Constexpr,\n stream: cuda.CUstream,\n ):\n \"\"\"Build logical tensors over FlashInfer's packed NVFP4 storage.\"\"\"\n weights = cute.make_tensor(\n weight_ptr,\n cute.make_ordered_layout((m, k, self.group_count), order=(1, 0, 2)),\n )\n weight_sf = cute.make_tensor(\n weight_sf_ptr,\n blockscaled_utils.tile_atom_to_shape_SF(\n weights.shape, _NVFP4_SCALE_GRANULARITY_K\n ),\n )\n activations = cute.make_tensor(\n activation_ptr,\n cute.make_ordered_layout((n, k, 1), order=(1, 0, 2)),\n )\n output_m = m // self.output_m_factor\n output_layout = cute.make_ordered_layout((output_m, n, 1), order=(0, 1, 2))\n output = cute.make_tensor(output_ptr, output_layout)\n final_output = (\n cute.make_tensor(\n output_ptr,\n cute.make_ordered_layout((output_m, num_tokens, 1), order=(0, 1, 2)),\n )\n if cutlass.const_expr(self.use_fused_finalize)\n else output\n )\n num_route_tiles = n // self.mma_tiler[1]\n tile_idx_to_expert_idx = cute.make_tensor(\n tile_idx_to_expert_idx_ptr, cute.make_layout((num_route_tiles,))\n )\n tile_idx_to_mn_limit = cute.make_tensor(\n tile_idx_to_mn_limit_ptr, cute.make_layout((num_route_tiles,))\n )\n num_non_exiting_tiles = cute.make_tensor(\n num_non_exiting_tiles_ptr, cute.make_layout((1,))\n )\n alpha = cute.make_tensor(alpha_ptr, cute.make_layout((self.group_count,)))\n permuted_idx_to_expanded_idx = (\n cute.make_tensor(permuted_idx_to_expanded_idx_ptr, cute.make_layout((n,)))\n if cutlass.const_expr(self.use_fused_finalize)\n else None\n )\n token_final_scales = (\n cute.make_tensor(\n token_final_scales_ptr,\n cute.make_ordered_layout((num_tokens, top_k), order=(1, 0)),\n )\n if cutlass.const_expr(self.use_fused_finalize)\n else None\n )\n return self(\n weights,\n weight_sf,\n activations,\n tile_idx_to_expert_idx,\n tile_idx_to_mn_limit,\n num_non_exiting_tiles,\n alpha,\n output,\n final_output,\n permuted_idx_to_expanded_idx,\n token_final_scales,\n max_active_clusters,\n stream,\n )\n\n @cute.jit\n def __call__(\n self,\n a: cute.Tensor,\n a_scale: cute.Tensor,\n b: cute.Tensor,\n tile_idx_to_expert_idx: cute.Tensor,\n tile_idx_to_mn_limit: cute.Tensor,\n num_non_exiting_tiles: cute.Tensor,\n alpha: cute.Tensor,\n c: cute.Tensor,\n final_output: cute.Tensor,\n permuted_idx_to_expanded_idx: Optional[cute.Tensor],\n token_final_scales: Optional[cute.Tensor],\n max_active_clusters: cutlass.Constexpr,\n stream: cuda.CUstream,\n ):\n \"\"\"Configure and launch the grouped GEMM.\"\"\"\n self.a_dtype: type[cutlass.Numeric] = a.element_type\n self.a_scale_dtype: type[cutlass.Numeric] = a_scale.element_type\n self.b_dtype: type[cutlass.Numeric] = b.element_type\n self.c_dtype: type[cutlass.Numeric] = c.element_type\n self.mma_dtype = self.b_dtype\n\n self.a_major_mode = utils.LayoutEnum.from_tensor(a).mma_major_mode()\n self.b_major_mode = utils.LayoutEnum.from_tensor(b).mma_major_mode()\n self.c_layout = utils.LayoutEnum.from_tensor(c)\n\n if cutlass.const_expr(\n utils.LayoutEnum.from_tensor(a_scale).mma_major_mode()\n != cute.nvgpu.OperandMajorMode.K\n ):\n raise ValueError(\"scale_major_mode must be K-major\")\n\n self._setup_attributes()\n\n tiled_mma = sm100_utils.make_trivial_tiled_mma(\n self.mma_dtype,\n self.a_major_mode,\n self.b_major_mode,\n self.acc_dtype,\n self.cta_group,\n self.mma_tiler[:2],\n self.transform_a_source,\n )\n a_op = mixed_input_utils.get_tma_atom_kind(\n self.is_a_mcast, self.use_2cta_instrs, False\n )\n b_op = mixed_input_utils.get_tma_atom_kind(\n self.is_b_mcast, self.use_2cta_instrs, True\n )\n smem_layout_a_per_stage = cute.slice_(self.smem_layout_a, (None, None, None, 0))\n tma_atom_a, tma_tensor_a = cute.nvgpu.make_tiled_tma_atom_A(\n a_op,\n a,\n smem_layout_a_per_stage,\n self.mma_tiler,\n tiled_mma,\n self.cluster_layout_vmnk.shape,\n internal_type=(\n cutlass.TFloat32 if a.element_type is cutlass.Float32 else None\n ),\n )\n\n scale_smem_layout_for_tma = cute.slice_(\n self.smem_layout_scale_tma, (None, None, None, 0)\n )\n tma_atom_scale, tma_tensor_scale = cute.nvgpu.make_tiled_tma_atom_A(\n a_op,\n a_scale,\n scale_smem_layout_for_tma,\n self.mma_tiler,\n tiled_mma,\n self.cluster_layout_vmnk.shape,\n internal_type=cutlass.Int16,\n )\n\n smem_layout_b_per_stage = cute.slice_(self.smem_layout_b, (None, None, None, 0))\n tma_atom_b, tma_tensor_b = cute.nvgpu.make_tiled_tma_atom_B(\n b_op,\n b,\n smem_layout_b_per_stage,\n self.mma_tiler,\n tiled_mma,\n self.cluster_layout_vmnk.shape,\n internal_type=(\n cutlass.TFloat32 if b.element_type is cutlass.Float32 else None\n ),\n )\n\n a_copy_size = cute.size_in_bytes(self.a_dtype, smem_layout_a_per_stage)\n b_copy_size = cute.size_in_bytes(self.b_dtype, smem_layout_b_per_stage)\n a_scale_copy_size = cute.size_in_bytes(\n self.a_scale_dtype, self.smem_layout_scale_per_stage\n )\n\n self.num_tma_load_bytes_a_scale = a_copy_size + a_scale_copy_size\n self.num_tma_load_bytes_b = b_copy_size * cute.size(tiled_mma.thr_id.shape)\n self.tile_sched_params, grid = self._compute_grid(\n c,\n self.cta_tile_shape_mnk_c,\n self.cluster_shape_mn,\n max_active_clusters,\n self.use_clc_scheduler,\n self.raster_along_m,\n )\n\n epi_smem_layout = cute.slice_(self.c_smem_layout_staged, (None, None, 0))\n tma_atom_c, tma_tensor_c = cpasync.make_tiled_tma_atom(\n cpasync.CopyBulkTensorTileS2GOp(),\n c,\n epi_smem_layout,\n self.epi_tile,\n )\n\n @cute.struct\n class SharedStorage:\n # Routed-tile scheduling metadata.\n tile_info: cute.struct.MemRange[cutlass.Int32, 4 * self.num_tile_info_stage]\n a_load2trans_full_mbar_ptr: cute.struct.MemRange[\n cutlass.Int64, self.num_load2trans_stage\n ]\n a_load2trans_empty_mbar_ptr: cute.struct.MemRange[\n cutlass.Int64, self.num_load2trans_stage\n ]\n a_trans2mma_full_mbar_ptr: cute.struct.MemRange[\n cutlass.Int64, self.num_trans2mma_stage\n ]\n a_trans2mma_empty_mbar_ptr: cute.struct.MemRange[\n cutlass.Int64, self.num_trans2mma_stage\n ]\n b_load2mma_full_mbar_ptr: cute.struct.MemRange[\n cutlass.Int64, self.num_load2trans_stage\n ]\n b_load2mma_empty_mbar_ptr: cute.struct.MemRange[\n cutlass.Int64, self.num_load2trans_stage\n ]\n acc_full_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.num_acc_stage]\n acc_empty_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.num_acc_stage]\n tile_info_full_mbar_ptr: cute.struct.MemRange[\n cutlass.Int64, self.num_tile_info_stage\n ]\n tile_info_empty_mbar_ptr: cute.struct.MemRange[\n cutlass.Int64, self.num_tile_info_stage\n ]\n clc_mbar_ptr: cute.struct.MemRange[cutlass.Int64, 2]\n clc_response: cute.struct.Align[cute.struct.MemRange[cutlass.Int32, 4], 16]\n tmem_dealloc_mbar: cutlass.Int64\n tmem_holding_buf: cutlass.Int32\n\n self.shared_storage = SharedStorage\n\n self.kernel(\n tiled_mma,\n tma_atom_a,\n tma_tensor_a,\n tma_atom_scale,\n tma_tensor_scale,\n tma_atom_b,\n tma_tensor_b,\n tma_atom_c,\n tma_tensor_c,\n c,\n final_output,\n tile_idx_to_expert_idx,\n tile_idx_to_mn_limit,\n num_non_exiting_tiles,\n alpha,\n permuted_idx_to_expanded_idx,\n token_final_scales,\n self.group_count,\n self.cluster_layout_vmnk,\n self.smem_layout_a,\n self.smem_layout_scale,\n self.smem_layout_scale_tma,\n self.smem_layout_a_transform,\n self.smem_layout_b,\n self.c_smem_layout_staged,\n self.epi_tile,\n self.tile_sched_params,\n ).launch(\n grid=grid,\n block=[self.threads_per_cta, 1, 1],\n cluster=(*self.cluster_shape_mn, 1),\n min_blocks_per_mp=1,\n stream=stream,\n use_pdl=self.enable_pdl,\n )\n\n @cute.kernel\n def kernel(\n self,\n tiled_mma: cute.TiledMma,\n tma_atom_a: cute.CopyAtom,\n mA_mkl: cute.Tensor,\n tma_atom_s: cute.CopyAtom,\n mS_mkl: cute.Tensor,\n tma_atom_b: cute.CopyAtom,\n mB_nkl: cute.Tensor,\n tma_atom_c: cute.CopyAtom,\n mC_mnl: cute.Tensor,\n tensor_c: cute.Tensor,\n final_output: cute.Tensor,\n tile_idx_to_expert_idx: cute.Tensor,\n tile_idx_to_mn_limit: cute.Tensor,\n num_non_exiting_tiles: cute.Tensor,\n alpha: cute.Tensor,\n permuted_idx_to_expanded_idx: Optional[cute.Tensor],\n token_final_scales: Optional[cute.Tensor],\n group_count: cutlass.Constexpr[int],\n cluster_layout_vmnk: cute.Layout,\n a_smem_layout: cute.ComposedLayout,\n scale_smem_layout: cute.ComposedLayout,\n scale_tma_smem_layout: cute.Layout,\n a_smem_layout_transform: cute.ComposedLayout,\n b_smem_layout: cute.ComposedLayout,\n c_smem_layout_staged: cute.ComposedLayout,\n epi_tile: cute.Tile,\n tile_sched_params: Union[\n utils.ClcDynamicPersistentTileSchedulerParams,\n utils.PersistentTileSchedulerParams,\n ],\n ):\n \"\"\"Run the persistent W4A16 grouped GEMM.\"\"\"\n warp_idx = cute.arch.make_warp_uniform(cute.arch.warp_idx())\n tidx, _, _ = cute.arch.thread_idx()\n bidx, bidy, bidz = cute.arch.block_idx()\n # Prefetch TMA descriptors\n if warp_idx == self.epilog_warp_id[0]:\n cpasync.prefetch_descriptor(tma_atom_a)\n cpasync.prefetch_descriptor(tma_atom_b)\n cpasync.prefetch_descriptor(tma_atom_s)\n cpasync.prefetch_descriptor(tma_atom_c)\n\n use_2cta_instrs = cute.size(tiled_mma.thr_id.shape) == 2\n mma_tile_coord_v = bidx % cute.size(tiled_mma.thr_id.shape)\n is_leader_cta = mma_tile_coord_v == 0\n cta_rank_in_cluster = cute.arch.make_warp_uniform(\n cute.arch.block_idx_in_cluster()\n )\n is_first_cta_in_cluster = cta_rank_in_cluster == 0\n block_in_cluster_coord_vmnk = cluster_layout_vmnk.get_flat_coord(\n cta_rank_in_cluster\n )\n smem = utils.SmemAllocator()\n storage = smem.allocate(self.shared_storage)\n clc_response_ptr = storage.clc_response.data_ptr()\n\n # Initialize load2transform pipeline for the weight operand.\n transform_thread_idx = (\n tidx - 32 * self.transform_warp_id[0]\n if tidx >= 32 * self.transform_warp_id[0]\n else tidx\n )\n a_load2trans_pipeline = pipeline.PipelineTmaAsync.create(\n barrier_storage=storage.a_load2trans_full_mbar_ptr.data_ptr(),\n num_stages=self.num_load2trans_stage,\n producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread),\n consumer_group=pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n self.num_mcast_ctas_a * self.num_transform_warps,\n ),\n tx_count=self.num_tma_load_bytes_a_scale,\n cta_layout_vmnk=cluster_layout_vmnk,\n tidx=transform_thread_idx,\n mcast_mode_mn=(1, 0), # multicast for A will only happen on the M-mode\n defer_sync=True,\n )\n # Initialize transform2mma pipeline, which tracks the dependencies between the transformation\n # of A and MMA's consumption of transformed A\n cta_v_size = cute.size(cluster_layout_vmnk, mode=[0])\n trans2mma_pipeline = pipeline.PipelineAsyncUmma.create(\n barrier_storage=storage.a_trans2mma_full_mbar_ptr.data_ptr(),\n num_stages=self.num_trans2mma_stage,\n producer_group=pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n 32 * self.num_transform_warps * cta_v_size,\n ),\n consumer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread),\n cta_layout_vmnk=cluster_layout_vmnk,\n defer_sync=True,\n )\n # Initialize pipeline for tensor B load to MMA\n # MMA warp informs TMA warp to proceed to load next tile of B tensor\n b_load2mma_pipeline = pipeline.PipelineTmaUmma.create(\n barrier_storage=storage.b_load2mma_full_mbar_ptr.data_ptr(),\n num_stages=self.num_load2trans_stage,\n producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread),\n consumer_group=pipeline.CooperativeGroup(\n pipeline.Agent.Thread, self.num_mcast_ctas_b\n ),\n tx_count=self.num_tma_load_bytes_b,\n cta_layout_vmnk=cluster_layout_vmnk,\n mcast_mode_mn=(0, 1), # multicast for B will only happen on the N-mode\n defer_sync=True,\n )\n # Initialize accumulator pipeline, which tracks the dependencies between\n # MMA's computation of accumulators and epilogue warps' consumption of accumulators\n acc_pipeline = pipeline.PipelineUmmaAsync.create(\n barrier_storage=storage.acc_full_mbar_ptr.data_ptr(),\n num_stages=self.num_acc_stage,\n producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread),\n consumer_group=pipeline.CooperativeGroup(\n pipeline.Agent.Thread, cta_v_size * len(self.epilog_warp_id)\n ),\n cta_layout_vmnk=cluster_layout_vmnk,\n defer_sync=True,\n )\n # Initialize tile info pipeline, which tracks the dependencies between\n # tile scheduling warp and other warps\n # Every warp except the scheduler consumes routed-tile metadata.\n num_tile_info_pipeline_consumer_threads = self.threads_per_cta - 32\n tile_info_pipeline = pipeline.PipelineAsync.create(\n barrier_storage=storage.tile_info_full_mbar_ptr.data_ptr(),\n num_stages=self.num_tile_info_stage,\n producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread, 32 * 1),\n consumer_group=pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n num_tile_info_pipeline_consumer_threads,\n ),\n defer_sync=True,\n )\n clc_pipeline = None\n if cutlass.const_expr(self.use_clc_scheduler):\n clc_pipeline = pipeline.PipelineClcFetchAsync.create(\n barrier_storage=storage.clc_mbar_ptr.data_ptr(),\n num_stages=1,\n producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread),\n consumer_group=pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n 32 * cute.size(self.cluster_shape_mn),\n ),\n tx_count=16,\n cta_layout_vmnk=cluster_layout_vmnk,\n defer_sync=True,\n )\n\n # Tensor memory dealloc barrier init\n tmem = utils.TmemAllocator(\n storage.tmem_holding_buf.ptr,\n barrier_for_retrieve=self.tmem_ptr_sync_barrier,\n allocator_warp_id=self.epilog_warp_id[0],\n is_two_cta=use_2cta_instrs,\n two_cta_tmem_dealloc_mbar_ptr=storage.tmem_dealloc_mbar.ptr,\n )\n\n # Cluster arrive after barrier init\n pipeline_init_arrive(cluster_shape_mn=self.cluster_shape_mn, is_relaxed=True)\n\n # Setup smem tensor A/scale/B/C\n sC = smem.allocate_tensor(\n element_type=self.c_dtype,\n layout=c_smem_layout_staged.outer,\n byte_alignment=self.smem_buffer_align_bytes,\n swizzle=c_smem_layout_staged.inner,\n )\n # Fused finalize reuses the first C stage as a linear\n # [route, hidden] tile for descriptor-free bulk reduction. The bulk\n # reduction consumes raw contiguous bytes, so drop sC's pointer swizzle.\n sFinalize = (\n cute.make_tensor(\n cute.recast_ptr(sC.iterator),\n cute.make_layout(\n (self.epi_tile_n, self.cta_tile_shape_mnk[0]),\n stride=(self.cta_tile_shape_mnk[0], 1),\n ),\n )\n if cutlass.const_expr(self.use_fused_finalize)\n else None\n )\n sA_input = smem.allocate_tensor(\n element_type=self.a_dtype,\n layout=a_smem_layout.outer,\n byte_alignment=self.smem_buffer_align_bytes,\n swizzle=a_smem_layout.inner,\n )\n sS_input = smem.allocate_tensor(\n element_type=self.a_scale_dtype,\n layout=scale_smem_layout.outer,\n byte_alignment=self.smem_buffer_align_bytes,\n swizzle=scale_smem_layout.inner,\n )\n sS_tma = cute.make_tensor(sS_input.iterator, scale_tma_smem_layout)\n sA_transform_input = sA_input\n sS_transform_input = sS_input\n if cutlass.const_expr(self.gated):\n # Pair 16-row up/gate slices during decode so each epilogue warp\n # owns both operands in its 32 TMEM lanes.\n gated_row_layout = cute.make_layout(((16, 2), 4), stride=((1, 64), 16))\n sA_transform_input = cute.composition(\n sA_input,\n ((gated_row_layout, None), None, None, None),\n )\n sS_transform_input = cute.composition(\n sS_input,\n ((gated_row_layout, None), None, None),\n )\n sB_input = smem.allocate_tensor(\n element_type=self.b_dtype,\n layout=b_smem_layout.outer,\n byte_alignment=self.smem_buffer_align_bytes,\n swizzle=b_smem_layout.inner,\n )\n sA_transform = None\n # Get smem tensor for transformed A when transform_a_source is SMEM\n if cutlass.const_expr(self.transform_a_source == tcgen05.OperandSource.SMEM):\n sA_transform = smem.allocate_tensor(\n element_type=self.mma_dtype,\n layout=a_smem_layout_transform.outer,\n byte_alignment=self.smem_buffer_align_bytes,\n swizzle=a_smem_layout_transform.inner,\n )\n sFinalizeScale = (\n smem.allocate_tensor(\n element_type=cutlass.Float32,\n layout=cute.make_layout((self.epi_tile_n,)),\n byte_alignment=16,\n )\n if cutlass.const_expr(self.use_fused_finalize)\n else None\n )\n sTile_info = storage.tile_info.get_tensor(\n cute.make_layout((4, self.num_tile_info_stage), stride=(1, 4))\n )\n\n # Compute multicast mask for A/B buffer full\n a_full_mcast_mask = None\n b_full_mcast_mask = None\n s_full_mcast_mask = None\n if cutlass.const_expr(self.is_a_mcast or self.is_b_mcast or use_2cta_instrs):\n a_full_mcast_mask = cpasync.create_tma_multicast_mask(\n cluster_layout_vmnk, block_in_cluster_coord_vmnk, mcast_mode=2\n )\n # Scale tensor shares the same multicast mask as the A tensor\n s_full_mcast_mask = a_full_mcast_mask\n b_full_mcast_mask = cpasync.create_tma_multicast_mask(\n cluster_layout_vmnk, block_in_cluster_coord_vmnk, mcast_mode=1\n )\n\n # local_tile partition global tensors\n # (bM, bK, loopM, loopK, loopL)\n gA_mkl = cute.local_tile(\n mA_mkl, cute.slice_(self.mma_tiler, (None, 0, None)), (None, None, None)\n )\n # (bM, bK, loopM, loopK, loopL)\n gS_mkl = cute.local_tile(\n mS_mkl,\n cute.slice_(self.mma_tiler, (None, 0, None)),\n (None, None, None),\n )\n # (bN, bK, loopN, loopK, loopL)\n gB_nkl = cute.local_tile(\n mB_nkl, cute.slice_(self.mma_tiler, (0, None, None)), (None, None, None)\n )\n # (bM, bN, loopM, loopN, loopL)\n gC_mnl = cute.local_tile(\n mC_mnl,\n cute.slice_(self.mma_tiler_c, (None, None, 0)),\n (None, None, None),\n )\n gC_mnl_simt = cute.local_tile(\n tensor_c,\n cute.slice_(self.mma_tiler_c, (None, None, 0)),\n (None, None, None),\n )\n k_tile_cnt = cutlass.Int32(cute.size(gA_mkl, mode=[3]))\n\n # Partition global tensor for TiledMMA_A/B/C\n thr_mma = tiled_mma.get_slice(mma_tile_coord_v)\n # (MMA, MMA_M, MMA_K, loopM, loopK, loopL)\n tCgA = thr_mma.partition_A(gA_mkl)\n # (MMA, MMA_M, MMA_K, loopM, loopK, loopL)\n tCgS = thr_mma.partition_A(gS_mkl)\n # (MMA, MMA_N, MMA_K, loopN, loopK, loopL)\n tCgB = thr_mma.partition_B(gB_nkl)\n # (MMA, MMA_M, MMA_N, loopM, loopN, loopL)\n tCgC = thr_mma.partition_C(gC_mnl)\n tCgC_simt = thr_mma.partition_C(gC_mnl_simt)\n\n # Setup copy atom to load A from shared memory for further transformation\n copy_atom_a_input = cute.make_copy_atom(\n cute.nvgpu.CopyUniversalOp(), self.a_dtype, num_bits_per_copy=32\n )\n # Split complete NVFP4 blocks between two transform warpgroups.\n copy_atom_a_transform = cute.make_copy_atom(\n tcgen05.St32x32bOp(\n tcgen05.Repetition(8),\n tcgen05.Unpack.NONE,\n ),\n self.mma_dtype,\n )\n\n # Partition global/shared tensor for TMA load A/B\n # TMA load A partition_S/D\n a_cta_layout = cute.make_layout(\n cute.slice_(cluster_layout_vmnk, (0, 0, None, 0)).shape\n )\n # ((atom_v, rest_v), STAGE)\n # ((atom_v, rest_v), loopM, loopK, loopL)\n tAsA, tAgA = cpasync.tma_partition(\n tma_atom_a,\n block_in_cluster_coord_vmnk[2],\n a_cta_layout,\n cute.group_modes(sA_input, 0, 3),\n cute.group_modes(tCgA, 0, 3),\n )\n\n thr_mma_leader_cta = tiled_mma.get_slice(0)\n # (MMA, MMA_M, MMA_K, STAGE)\n tCsS = thr_mma_leader_cta.partition_A(sS_transform_input)\n tSsS, tSgS = cpasync.tma_partition(\n tma_atom_s,\n block_in_cluster_coord_vmnk[2],\n a_cta_layout,\n cute.group_modes(sS_tma, 0, 3),\n cute.group_modes(tCgS, 0, 3),\n )\n tSsS = cute.filter_zeros(tSsS)\n tSgS = cute.filter_zeros(tSgS)\n\n # TMA load B partition_S/D\n b_cta_layout = cute.make_layout(\n cute.slice_(cluster_layout_vmnk, (0, None, 0, 0)).shape\n )\n # ((atom_v, rest_v), STAGE)\n # ((atom_v, rest_v), loopM, loopK, loopL)\n tBsB, tBgB = cpasync.tma_partition(\n tma_atom_b,\n block_in_cluster_coord_vmnk[1],\n b_cta_layout,\n cute.group_modes(sB_input, 0, 3),\n cute.group_modes(tCgB, 0, 3),\n )\n\n # (MMA, MMA_N, MMA_K, STAGE)\n tCrB = tiled_mma.make_fragment_B(sB_input)\n # (MMA, MMA_M, MMA_N)\n acc_shape = tiled_mma.partition_shape_C(self.mma_tiler[:2])\n tCtAcc_fake = tiled_mma.make_fragment_C(\n cute.append(acc_shape, self.num_acc_stage)\n )\n\n # Cluster wait before TMEM alloc and ensure pipelines are ready.\n pipeline_init_wait(cluster_shape_mn=self.cluster_shape_mn)\n\n # TMEM allocation\n tmem.allocate(self.num_tmem_alloc_cols)\n tmem.wait_for_alloc()\n\n # Tile scheduling is independent of the preceding grid.\n if warp_idx == self.schedule_warp_id:\n cute.arch.setmaxregister_decrease(self.num_regs_generic_warps)\n tile_info_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.num_tile_info_stage\n )\n num_non_exiting_tiles_value = num_non_exiting_tiles[0]\n if cutlass.const_expr(self.use_clc_scheduler):\n tile_sched = utils.ClcDynamicPersistentTileScheduler.create(\n tile_sched_params,\n (bidx, bidy, bidz),\n cute.arch.grid_dim(),\n clc_response_ptr,\n )\n work_tile = tile_sched.initial_work_tile_info()\n clc_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.ProducerConsumer, 1\n )\n clc_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, 1\n )\n not_last_tile = cutlass.Boolean(1)\n while not_last_tile:\n tile_coord_mnl = work_tile.tile_idx\n route_tile_idx = tile_coord_mnl[1]\n is_routed_tile = work_tile.is_valid_tile and (\n route_tile_idx < num_non_exiting_tiles_value\n )\n\n if is_routed_tile or not work_tile.is_valid_tile:\n tile_info_pipeline.producer_acquire(tile_info_producer_state)\n\n if work_tile.is_valid_tile and is_first_cta_in_cluster:\n clc_pipeline.producer_acquire(clc_producer_state)\n tile_sched.advance_to_next_work(\n clc_pipeline.producer_get_barrier(clc_producer_state)\n )\n clc_producer_state.advance()\n\n if is_routed_tile or not work_tile.is_valid_tile:\n cur_sTile_info = sTile_info[\n (None, tile_info_producer_state.index)\n ]\n route_start = cutlass.Int32(-1)\n group_idx = cutlass.Int32(group_count)\n distance_to_boundary = cutlass.Int32(-1)\n if is_routed_tile:\n route_start = route_tile_idx * self.cta_tile_shape_mnk[1]\n group_idx = tile_idx_to_expert_idx[route_tile_idx]\n distance_to_boundary = (\n tile_idx_to_mn_limit[route_tile_idx] - route_start\n )\n with cute.arch.elect_one():\n cur_sTile_info[0] = tile_coord_mnl[0]\n cur_sTile_info[1] = route_start\n cur_sTile_info[2] = group_idx\n cur_sTile_info[3] = distance_to_boundary\n cute.arch.fence_proxy(\"async.shared\", space=\"cta\")\n self.sched_sync_barrier.arrive_and_wait()\n tile_info_pipeline.producer_commit(tile_info_producer_state)\n tile_info_producer_state.advance()\n\n if work_tile.is_valid_tile:\n clc_pipeline.consumer_wait(clc_consumer_state)\n work_tile = tile_sched.get_current_work()\n clc_pipeline.consumer_release(clc_consumer_state)\n clc_consumer_state.advance()\n else:\n not_last_tile = cutlass.Boolean(0)\n\n tile_info_pipeline.producer_tail(tile_info_producer_state)\n if is_first_cta_in_cluster:\n clc_pipeline.producer_tail(clc_producer_state)\n else:\n tile_sched = utils.StaticPersistentRuntimeTileScheduler.create(\n tile_sched_params,\n (bidx, bidy, bidz),\n cute.arch.grid_dim(),\n inner_mode=0 if self.raster_along_m else 1,\n )\n work_tile = tile_sched.initial_work_tile_info()\n not_last_tile = cutlass.Boolean(1)\n if cutlass.const_expr(self.raster_along_m):\n while not_last_tile:\n tile_info_pipeline.producer_acquire(tile_info_producer_state)\n cluster_tile_coord_mnl = work_tile.tile_idx\n cta_tile_coord_m = (\n cluster_tile_coord_mnl[0] * self.cluster_shape_mn[0]\n + block_in_cluster_coord_vmnk[1]\n * cute.size(tiled_mma.thr_id.shape)\n + block_in_cluster_coord_vmnk[0]\n )\n cta_tile_offset_n = block_in_cluster_coord_vmnk[2]\n route_tile_idx = (\n cluster_tile_coord_mnl[1] * self.cluster_shape_mn[1]\n + cta_tile_offset_n\n )\n not_last_tile = work_tile.is_valid_tile and (\n route_tile_idx < num_non_exiting_tiles_value\n )\n route_start = cutlass.Int32(-1)\n group_idx = cutlass.Int32(group_count)\n distance_to_boundary = cutlass.Int32(-1)\n if not_last_tile:\n route_start = route_tile_idx * self.cta_tile_shape_mnk[1]\n group_idx = tile_idx_to_expert_idx[route_tile_idx]\n distance_to_boundary = (\n tile_idx_to_mn_limit[route_tile_idx] - route_start\n )\n cur_sTile_info = sTile_info[\n (None, tile_info_producer_state.index)\n ]\n with cute.arch.elect_one():\n cur_sTile_info[0] = cta_tile_coord_m\n cur_sTile_info[1] = route_start\n cur_sTile_info[2] = group_idx\n cur_sTile_info[3] = distance_to_boundary\n cute.arch.fence_proxy(\"async.shared\", space=\"cta\")\n self.sched_sync_barrier.arrive_and_wait()\n tile_info_pipeline.producer_commit(tile_info_producer_state)\n tile_info_producer_state.advance()\n tile_sched.advance_to_next_work()\n work_tile = tile_sched.get_current_work()\n else:\n while not_last_tile:\n cluster_tile_coord_mnl = work_tile.tile_idx\n cta_tile_coord_m = (\n cluster_tile_coord_mnl[0] * self.cluster_shape_mn[0]\n + block_in_cluster_coord_vmnk[1]\n * cute.size(tiled_mma.thr_id.shape)\n + block_in_cluster_coord_vmnk[0]\n )\n cta_tile_offset_n = block_in_cluster_coord_vmnk[2]\n route_tile_idx = (\n cluster_tile_coord_mnl[1] * self.cluster_shape_mn[1]\n + cta_tile_offset_n\n )\n # The runtime scheduler leaves its outer mode unbounded.\n # With N as the inner mode, terminate on the finite M\n # extent and skip padded routed tiles within each M tile.\n has_work = work_tile.is_valid_tile and (\n cluster_tile_coord_mnl[0]\n < tile_sched_params.problem_layout_ncluster_mnl.shape[0]\n )\n is_routed_tile = has_work and (\n route_tile_idx < num_non_exiting_tiles_value\n )\n\n if is_routed_tile or not has_work:\n tile_info_pipeline.producer_acquire(\n tile_info_producer_state\n )\n route_start = cutlass.Int32(-1)\n group_idx = cutlass.Int32(group_count)\n distance_to_boundary = cutlass.Int32(-1)\n if is_routed_tile:\n route_start = (\n route_tile_idx * self.cta_tile_shape_mnk[1]\n )\n group_idx = tile_idx_to_expert_idx[route_tile_idx]\n distance_to_boundary = (\n tile_idx_to_mn_limit[route_tile_idx] - route_start\n )\n cur_sTile_info = sTile_info[\n (None, tile_info_producer_state.index)\n ]\n with cute.arch.elect_one():\n cur_sTile_info[0] = cta_tile_coord_m\n cur_sTile_info[1] = route_start\n cur_sTile_info[2] = group_idx\n cur_sTile_info[3] = distance_to_boundary\n cute.arch.fence_proxy(\"async.shared\", space=\"cta\")\n self.sched_sync_barrier.arrive_and_wait()\n tile_info_pipeline.producer_commit(tile_info_producer_state)\n tile_info_producer_state.advance()\n\n if has_work:\n tile_sched.advance_to_next_work()\n work_tile = tile_sched.get_current_work()\n else:\n not_last_tile = cutlass.Boolean(0)\n\n tile_info_pipeline.producer_tail(tile_info_producer_state)\n\n # The activation TMA warp is the only role that waits on the preceding grid.\n if warp_idx == self.activation_tma_warp_id:\n cute.arch.setmaxregister_decrease(self.num_regs_generic_warps)\n tile_info_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.num_tile_info_stage\n )\n tile_info_pipeline.consumer_wait(tile_info_consumer_state)\n work_tile = mixed_input_utils.make_contiguous_group_work_tile_info(\n group_count, sTile_info[(None, tile_info_consumer_state.index)]\n )\n cute.arch.fence_proxy(\n \"async.shared\",\n space=\"cta\",\n )\n tile_info_pipeline.consumer_release(tile_info_consumer_state)\n tile_info_consumer_state.advance()\n b_load2mma_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.num_load2trans_stage\n )\n if cutlass.const_expr(self.enable_pdl):\n griddepcontrol_wait()\n\n while work_tile.is_valid_tile:\n coord_n_offset = (\n (work_tile.coord_n, 0)\n if cutlass.const_expr(\n self.b_major_mode == cute.nvgpu.OperandMajorMode.MN\n )\n else (0, work_tile.coord_n)\n )\n tBgB_slice = cute.make_tensor(\n (\n tBgB.iterator[0] + coord_n_offset[0],\n coord_n_offset[1] + tBgB.iterator[1],\n ),\n cute.slice_(tBgB.layout, (None, 0, None, 0)),\n )\n\n b_load2mma_producer_state.reset_count()\n for _k_tile in cutlass.range(0, k_tile_cnt, 1, unroll=1):\n b_load2mma_pipeline.producer_acquire(b_load2mma_producer_state)\n cute.copy(\n tma_atom_b,\n tBgB_slice[(None, b_load2mma_producer_state.count)],\n tBsB[(None, b_load2mma_producer_state.index)],\n tma_bar_ptr=b_load2mma_pipeline.producer_get_barrier(\n b_load2mma_producer_state\n ),\n mcast_mask=b_full_mcast_mask,\n cache_policy=cutlass.Int64(_TMA_CACHE_HINT_EVICT_LAST),\n )\n b_load2mma_pipeline.producer_commit(b_load2mma_producer_state)\n b_load2mma_producer_state.advance()\n\n tile_info_pipeline.consumer_wait(tile_info_consumer_state)\n work_tile = mixed_input_utils.make_contiguous_group_work_tile_info(\n group_count, sTile_info[(None, tile_info_consumer_state.index)]\n )\n cute.arch.fence_proxy(\n \"async.shared\",\n space=\"cta\",\n )\n tile_info_pipeline.consumer_release(tile_info_consumer_state)\n tile_info_consumer_state.advance()\n b_load2mma_pipeline.producer_tail(b_load2mma_producer_state)\n\n # Static weight and scale loads can run before the activation is ready.\n if warp_idx == self.weight_tma_warp_id:\n cute.arch.setmaxregister_decrease(self.num_regs_generic_warps)\n tile_info_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.num_tile_info_stage\n )\n tile_info_pipeline.consumer_wait(tile_info_consumer_state)\n work_tile = mixed_input_utils.make_contiguous_group_work_tile_info(\n group_count, sTile_info[(None, tile_info_consumer_state.index)]\n )\n cute.arch.fence_proxy(\n \"async.shared\",\n space=\"cta\",\n )\n tile_info_pipeline.consumer_release(tile_info_consumer_state)\n tile_info_consumer_state.advance()\n a_load2trans_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.num_load2trans_stage\n )\n if cutlass.const_expr(self.enable_pdl and self.fuse_activation):\n with cute.arch.elect_one():\n griddepcontrol_launch_dependents()\n while work_tile.is_valid_tile:\n tAgA_slice = tAgA[\n (\n None,\n work_tile.cta_coord_m // cute.size(tiled_mma.thr_id.shape),\n None,\n work_tile.group_idx,\n )\n ]\n tSgS_slice = tSgS[\n (\n None,\n work_tile.cta_coord_m // cute.size(tiled_mma.thr_id.shape),\n None,\n work_tile.group_idx,\n )\n ]\n # Filter zeros in rest mode\n rest_filtered = cute.filter_zeros(tSgS_slice[(0, None)].layout)\n tSgS_slice_filtered = cute.make_tensor(\n tSgS_slice.iterator,\n cute.make_layout(\n (tSgS_slice.layout[0].shape, rest_filtered.shape),\n stride=(tSgS_slice.layout[0].stride, rest_filtered.stride),\n ),\n )\n\n a_load2trans_producer_state.reset_count()\n peek_load2trans_empty_status = cutlass.Boolean(1)\n if a_load2trans_producer_state.count < k_tile_cnt:\n peek_load2trans_empty_status = (\n a_load2trans_pipeline.producer_try_acquire(\n a_load2trans_producer_state\n )\n )\n for _k_tile in cutlass.range(0, k_tile_cnt, 1, unroll=1):\n a_load2trans_pipeline.producer_acquire(\n a_load2trans_producer_state,\n peek_load2trans_empty_status,\n )\n cute.copy(\n tma_atom_a,\n tAgA_slice[(None, a_load2trans_producer_state.count)],\n tAsA[(None, a_load2trans_producer_state.index)],\n tma_bar_ptr=a_load2trans_pipeline.producer_get_barrier(\n a_load2trans_producer_state\n ),\n mcast_mask=a_full_mcast_mask,\n cache_policy=cutlass.Int64(_TMA_CACHE_HINT_EVICT_FIRST),\n )\n cute.copy(\n tma_atom_s,\n tSgS_slice_filtered[(None, a_load2trans_producer_state.count)],\n tSsS[(None, a_load2trans_producer_state.index)],\n tma_bar_ptr=a_load2trans_pipeline.producer_get_barrier(\n a_load2trans_producer_state\n ),\n mcast_mask=s_full_mcast_mask,\n )\n a_load2trans_pipeline.producer_commit(a_load2trans_producer_state)\n a_load2trans_producer_state.advance()\n if a_load2trans_producer_state.count < k_tile_cnt:\n peek_load2trans_empty_status = (\n a_load2trans_pipeline.producer_try_acquire(\n a_load2trans_producer_state\n )\n )\n\n tile_info_pipeline.consumer_wait(tile_info_consumer_state)\n work_tile = mixed_input_utils.make_contiguous_group_work_tile_info(\n group_count, sTile_info[(None, tile_info_consumer_state.index)]\n )\n cute.arch.fence_proxy(\n \"async.shared\",\n space=\"cta\",\n )\n tile_info_pipeline.consumer_release(tile_info_consumer_state)\n tile_info_consumer_state.advance()\n\n a_load2trans_pipeline.producer_tail(a_load2trans_producer_state)\n\n # Specialized transform warps\n if warp_idx >= self.transform_warp_id[0]:\n transform_group_idx = (warp_idx - self.transform_warp_id[0]) // 4\n transform_local_tidx = tidx - 32 * (\n self.transform_warp_id[0] + transform_group_idx * 4\n )\n # Get the pointer to the TMEM buffer\n tmem_ptr = tmem.retrieve_ptr(self.acc_dtype)\n accumulators = cute.make_tensor(tmem_ptr, tCtAcc_fake.layout)\n\n (\n dst_copy_a,\n tAsA_input,\n tAsA_transform,\n tSsS_trans,\n tSrS_copy,\n tSrS_load,\n tArA_load,\n tArA_transform,\n tArA_transform_store,\n transform_tiler,\n ) = self._setup_transform_partitions(\n tiled_mma,\n copy_atom_a_input,\n copy_atom_a_transform,\n sA_transform_input,\n a_smem_layout_transform,\n sA_transform,\n tCsS,\n accumulators,\n transform_local_tidx,\n transform_group_idx,\n )\n\n tile_info_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.num_tile_info_stage\n )\n tile_info_pipeline.consumer_wait(tile_info_consumer_state)\n work_tile = mixed_input_utils.make_contiguous_group_work_tile_info(\n group_count, sTile_info[(None, tile_info_consumer_state.index)]\n )\n cute.arch.fence_proxy(\n \"async.shared\",\n space=\"cta\",\n )\n tile_info_pipeline.consumer_release(tile_info_consumer_state)\n tile_info_consumer_state.advance()\n a_load2trans_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer,\n self.num_load2trans_stage,\n )\n trans2mma_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer,\n self.num_trans2mma_stage,\n )\n while work_tile.is_valid_tile:\n (\n a_load2trans_consumer_state,\n trans2mma_producer_state,\n ) = self._transform_tile(\n a_load2trans_pipeline,\n trans2mma_pipeline,\n a_load2trans_consumer_state,\n trans2mma_producer_state,\n dst_copy_a,\n tAsA_input,\n tAsA_transform,\n tSsS_trans,\n tSrS_copy,\n tSrS_load,\n tArA_load,\n tArA_transform,\n tArA_transform_store,\n transform_tiler,\n k_tile_cnt,\n )\n # Advance to next tile\n tile_info_pipeline.consumer_wait(tile_info_consumer_state)\n work_tile = mixed_input_utils.make_contiguous_group_work_tile_info(\n group_count, sTile_info[(None, tile_info_consumer_state.index)]\n )\n cute.arch.fence_proxy(\n \"async.shared\",\n space=\"cta\",\n )\n tile_info_pipeline.consumer_release(tile_info_consumer_state)\n tile_info_consumer_state.advance()\n # Wait a_transform buffer empty\n trans2mma_pipeline.producer_tail(trans2mma_producer_state)\n\n # Specialized MMA warp\n if warp_idx == self.mma_warp_id:\n cute.arch.setmaxregister_decrease(self.num_regs_generic_warps)\n # Get the pointer to the TMEM buffer\n tmem_ptr = tmem.retrieve_ptr(self.acc_dtype)\n accumulators = cute.make_tensor(tmem_ptr, tCtAcc_fake.layout)\n if cutlass.const_expr(\n self.transform_a_source == tcgen05.OperandSource.TMEM\n ):\n tmem_ptr_transform = cute.recast_ptr(\n accumulators.iterator + self.num_acc_tmem_cols, dtype=self.mma_dtype\n )\n tCrA = cute.make_tensor(\n tmem_ptr_transform,\n tiled_mma.make_fragment_A(a_smem_layout_transform.outer).layout,\n )\n else:\n tCrA = tiled_mma.make_fragment_A(sA_transform)\n tCtAcc_base = accumulators\n # Persistent tile scheduling loop\n tile_info_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.num_tile_info_stage\n )\n tile_info_pipeline.consumer_wait(tile_info_consumer_state)\n work_tile = mixed_input_utils.make_contiguous_group_work_tile_info(\n group_count, sTile_info[(None, tile_info_consumer_state.index)]\n )\n cute.arch.fence_proxy(\n \"async.shared\",\n space=\"cta\",\n )\n tile_info_pipeline.consumer_release(tile_info_consumer_state)\n tile_info_consumer_state.advance()\n trans2mma_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.num_trans2mma_stage\n )\n b_load2mma_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.num_load2trans_stage\n )\n acc_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.num_acc_stage\n )\n while work_tile.is_valid_tile:\n # (MMA, MMA_M, MMA_N)\n tCtAcc = tCtAcc_base[(None, None, None, acc_producer_state.index)]\n b_load2mma_consumer_state.reset_count()\n trans2mma_consumer_state.reset_count()\n peek_trans2mma_full_status = cutlass.Boolean(1)\n if is_leader_cta:\n if trans2mma_consumer_state.count < k_tile_cnt:\n peek_trans2mma_full_status = (\n trans2mma_pipeline.consumer_try_wait(\n trans2mma_consumer_state\n )\n )\n acc_pipeline.producer_acquire(acc_producer_state)\n\n tiled_mma.set(tcgen05.Field.ACCUMULATE, False)\n # Mma mainloop\n for _k_tile in cutlass.range(0, k_tile_cnt, 1, unroll=1):\n trans2mma_pipeline.consumer_wait(\n trans2mma_consumer_state, peek_trans2mma_full_status\n )\n b_load2mma_pipeline.consumer_wait(b_load2mma_consumer_state)\n num_kblocks = cute.size(tCrA, mode=[2])\n for kblock_idx in cutlass.range(num_kblocks, unroll_full=True):\n kblock_coord_a = (\n None,\n None,\n kblock_idx,\n trans2mma_consumer_state.index,\n )\n kblock_coord_b = (\n None,\n None,\n kblock_idx,\n b_load2mma_consumer_state.index,\n )\n\n cute.gemm(\n tiled_mma,\n tCtAcc,\n tCrA[kblock_coord_a],\n tCrB[kblock_coord_b],\n tCtAcc,\n )\n # Enable accumulate on tCtAcc after first kblock\n tiled_mma.set(tcgen05.Field.ACCUMULATE, True)\n trans2mma_pipeline.consumer_release(trans2mma_consumer_state)\n b_load2mma_pipeline.consumer_release(b_load2mma_consumer_state)\n trans2mma_consumer_state.advance()\n b_load2mma_consumer_state.advance()\n peek_trans2mma_full_status = cutlass.Boolean(1)\n if trans2mma_consumer_state.count < k_tile_cnt:\n peek_trans2mma_full_status = (\n trans2mma_pipeline.consumer_try_wait(\n trans2mma_consumer_state\n )\n )\n # Async arrive accumulator buffer full\n acc_pipeline.producer_commit(acc_producer_state)\n acc_producer_state.advance()\n\n # Advance to next tile\n tile_info_pipeline.consumer_wait(tile_info_consumer_state)\n work_tile = mixed_input_utils.make_contiguous_group_work_tile_info(\n group_count, sTile_info[(None, tile_info_consumer_state.index)]\n )\n cute.arch.fence_proxy(\n \"async.shared\",\n space=\"cta\",\n )\n tile_info_pipeline.consumer_release(tile_info_consumer_state)\n tile_info_consumer_state.advance()\n # Wait for accumulator buffer empty\n acc_pipeline.producer_tail(acc_producer_state)\n\n # Specialized epilogue warps\n if warp_idx < self.mma_warp_id:\n cute.arch.setmaxregister_increase(self.num_regs_epilogue_warps)\n epi_tidx = tidx\n # Get the pointer to the TMEM buffer\n tmem_ptr = tmem.retrieve_ptr(self.acc_dtype)\n accumulators = cute.make_tensor(tmem_ptr, tCtAcc_fake.layout)\n tCtAcc_base = accumulators\n # Partition for epilogue\n tiled_copy_t2r, tTR_tAcc_base, tTR_rAcc = (\n mixed_input_utils.epilog_tmem_copy_and_partition(\n self.cta_tile_shape_mnk,\n self.c_layout,\n self.c_dtype,\n self.acc_dtype,\n epi_tidx,\n tCtAcc_base,\n tCgC,\n epi_tile,\n self.use_2cta_instrs,\n )\n )\n gated_tTR_tAcc_base = None\n gated_tiled_copy_t2r = None\n gated_tTR_identity_base = None\n gated_tTR_rAcc = None\n if cutlass.const_expr(self.gated):\n gated_epi_tile = (\n self.cta_tile_shape_mnk[0],\n self.epi_tile_n,\n )\n gated_copy_atom_t2r = sm100_utils.get_tmem_load_op(\n self.cta_tile_shape_mnk,\n self.c_layout,\n self.c_dtype,\n self.acc_dtype,\n gated_epi_tile,\n self.use_2cta_instrs,\n )\n gated_tAcc_epi = cute.flat_divide(\n tCtAcc_base[((None, None), 0, 0, None)],\n gated_epi_tile,\n )\n gated_tiled_copy_t2r = tcgen05.make_tmem_copy(\n gated_copy_atom_t2r,\n gated_tAcc_epi[(None, None, 0, 0, 0)],\n )\n gated_thr_copy_t2r = gated_tiled_copy_t2r.get_slice(epi_tidx)\n gated_tTR_tAcc_base = gated_thr_copy_t2r.partition_S(gated_tAcc_epi)\n gated_identity = cute.make_identity_tensor(self.cta_tile_shape_mnk[:2])\n gated_identity_epi = cute.flat_divide(gated_identity, gated_epi_tile)\n gated_tTR_identity_base = gated_thr_copy_t2r.partition_D(\n gated_identity_epi\n )\n gated_tTR_rAcc = cute.make_rmem_tensor(\n gated_tTR_identity_base[(None, None, None, 0, 0)].shape,\n self.acc_dtype,\n )\n tTR_rC = cute.make_rmem_tensor(tTR_rAcc.shape, self.c_dtype)\n tiled_copy_r2s, tRS_rC, tRS_sC = (\n mixed_input_utils.epilog_smem_copy_and_partition(\n self.c_layout,\n self.c_dtype,\n self.acc_dtype,\n tiled_copy_t2r,\n tTR_rC,\n epi_tidx,\n sC,\n )\n )\n (\n tma_atom_c,\n bSG_sC,\n bSG_gC_partitioned,\n simt_atom,\n tTR_gC_partitioned,\n ) = mixed_input_utils.epilog_gmem_copy_and_partition(\n self.c_dtype,\n epi_tidx,\n tma_atom_c,\n tiled_copy_t2r,\n tCgC,\n tCgC_simt,\n epi_tile,\n sC,\n )\n if cutlass.const_expr(self.gated):\n gC_epi = cute.local_tile(mC_mnl, epi_tile, (None, None, None))\n bSG_sC, bSG_gC_partitioned = cpasync.tma_partition(\n tma_atom_c,\n 0,\n cute.make_layout(1),\n cute.group_modes(sC, 0, 2),\n cute.group_modes(gC_epi, 0, 2),\n )\n\n # Predicates\n thr_mapping = cute.make_identity_tensor(\n (self.cta_tile_shape_mnk[0], self.cta_tile_shape_mnk[1])\n )\n thr_mapping_mn = cute.flat_divide(thr_mapping, epi_tile)\n thr_copy_t2r = tiled_copy_t2r.get_slice(epi_tidx)\n m_thr_offset = thr_copy_t2r.partition_D(thr_mapping_mn)\n m_thr_offset = cute.group_modes(m_thr_offset, 3, cute.rank(m_thr_offset))\n\n acc_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.num_acc_stage\n )\n\n c_producer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n 32 * len(self.epilog_warp_id),\n )\n c_pipeline = pipeline.PipelineTmaStore.create(\n num_stages=self.num_c_stage,\n producer_group=c_producer_group,\n )\n\n # Persistent tile scheduling loop\n tile_info_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.num_tile_info_stage\n )\n tile_info_pipeline.consumer_wait(tile_info_consumer_state)\n work_tile = mixed_input_utils.make_contiguous_group_work_tile_info(\n group_count, sTile_info[(None, tile_info_consumer_state.index)]\n )\n cute.arch.fence_proxy(\n \"async.shared\",\n space=\"cta\",\n )\n tile_info_pipeline.consumer_release(tile_info_consumer_state)\n tile_info_consumer_state.advance()\n num_prev_subtiles = cutlass.Int32(0)\n while work_tile.is_valid_tile:\n alpha_val = alpha[work_tile.group_idx]\n if cutlass.const_expr(self.gated):\n bSG_gC = bSG_gC_partitioned[(None, work_tile.cta_coord_m, None, 0)]\n else:\n bSG_gC = bSG_gC_partitioned[\n (\n None,\n None,\n None,\n work_tile.cta_coord_m // cute.size(tiled_mma.thr_id.shape),\n 0,\n 0,\n )\n ]\n tma_store_offset_coord = (\n (work_tile.coord_n, 0)\n if cutlass.const_expr(self.c_layout.is_n_major_c())\n else (0, work_tile.coord_n)\n )\n bSG_gC = cute.make_tensor(\n (\n tma_store_offset_coord[0] + bSG_gC.iterator[0],\n tma_store_offset_coord[1] + bSG_gC.iterator[1],\n ),\n bSG_gC.layout,\n )\n tTR_gC = tTR_gC_partitioned[\n (\n None,\n None,\n None,\n None,\n None,\n work_tile.cta_coord_m // cute.size(tiled_mma.thr_id.shape),\n 0,\n 0,\n )\n ]\n tTR_gC = cute.make_tensor(\n tTR_gC.iterator + (work_tile.coord_n * tensor_c.layout.stride[1]),\n tTR_gC.layout,\n )\n\n tTR_tAcc = tTR_tAcc_base[\n (None, None, None, None, None, acc_consumer_state.index)\n ]\n # Wait for accumulator buffer full\n acc_pipeline.consumer_wait(acc_consumer_state)\n if cutlass.const_expr(not self.gated):\n bSG_gC = cute.group_modes(bSG_gC, 1, cute.rank(bSG_gC))\n\n if cutlass.const_expr(self.gated):\n gated_tTR_tAcc = gated_tTR_tAcc_base[\n (None, None, None, None, None, acc_consumer_state.index)\n ]\n gated_subtile_cnt = cute.size(gated_tTR_tAcc.shape, mode=[4])\n gated_alpha_f32 = cutlass.Float32(alpha_val)\n swiglu_alpha = cutlass.Float32(self.swiglu_alpha)\n swiglu_beta = cutlass.Float32(self.swiglu_beta)\n swiglu_limit = cutlass.Float32(self.swiglu_limit)\n neg_swiglu_alpha_log2_e = -(\n swiglu_alpha * cutlass.Float32(1.4426950408889634)\n )\n for gated_subtile_idx in cutlass.range(gated_subtile_cnt):\n gated_tTR_tAcc_mn = gated_tTR_tAcc[\n (None, None, None, 0, gated_subtile_idx)\n ]\n cute.copy(\n gated_tiled_copy_t2r,\n gated_tTR_tAcc_mn,\n gated_tTR_rAcc,\n )\n if gated_subtile_idx == gated_subtile_cnt - 1:\n cute.arch.fence_view_async_tmem_load()\n with cute.arch.elect_one():\n acc_pipeline.consumer_release(acc_consumer_state)\n acc_consumer_state.advance()\n num_prev_subtiles += 1\n c_buffer = num_prev_subtiles % self.num_c_stage\n gated_identity_mn = gated_tTR_identity_base[\n (None, None, None, 0, gated_subtile_idx)\n ]\n up = cute.coalesce(\n cute.flatten(gated_tTR_rAcc[(None, 0, None)])\n ).load()\n gate = cute.coalesce(\n cute.flatten(gated_tTR_rAcc[(None, 1, None)])\n ).load()\n up_coords = cute.coalesce(\n cute.flatten(gated_identity_mn[(None, 0, None)])\n )\n up_size = cute.size(gated_tTR_rAcc[(None, 0, None)])\n for i in cutlass.range_constexpr(0, up_size, 2):\n up_pair = cute.arch.mul_packed_f32x2(\n (up[i], up[i + 1]),\n (gated_alpha_f32, gated_alpha_f32),\n )\n gate_pair = cute.arch.mul_packed_f32x2(\n (gate[i], gate[i + 1]),\n (gated_alpha_f32, gated_alpha_f32),\n )\n if cutlass.const_expr(\n self.activation_type == ActivationType.Swiglu.value\n and self.situ_beta is not None\n ):\n situ_beta = cutlass.Float32(self.situ_beta)\n situ_gate_pair = (\n situ_f32(gate_pair[0], situ_beta, fastmath=True),\n situ_f32(gate_pair[1], situ_beta, fastmath=True),\n )\n if cutlass.const_expr(\n self.situ_linear_beta is not None\n ):\n linear_beta = cutlass.Float32(self.situ_linear_beta)\n up_pair = (\n linear_beta\n * tanh_f32(\n up_pair[0] / linear_beta, fastmath=True\n ),\n linear_beta\n * tanh_f32(\n up_pair[1] / linear_beta, fastmath=True\n ),\n )\n result = cute.arch.mul_packed_f32x2(\n up_pair, situ_gate_pair\n )\n elif cutlass.const_expr(\n self.activation_type == ActivationType.GegluTanh.value\n ):\n result = cute.arch.mul_packed_f32x2(\n up_pair,\n (\n gelu_tanh_f32(gate_pair[0], fastmath=True),\n gelu_tanh_f32(gate_pair[1], fastmath=True),\n ),\n )\n elif cutlass.const_expr(\n self.activation_type == ActivationType.Swiglu.value\n ):\n if cutlass.const_expr(self.parameterized_swiglu):\n gate_pair = (\n fmin(gate_pair[0], swiglu_limit, nan=True),\n fmin(gate_pair[1], swiglu_limit, nan=True),\n )\n up_pair = (\n -fmin(\n -fmin(up_pair[0], swiglu_limit, nan=True),\n swiglu_limit,\n nan=True,\n ),\n -fmin(\n -fmin(up_pair[1], swiglu_limit, nan=True),\n swiglu_limit,\n nan=True,\n ),\n )\n gate_log2e = cute.arch.mul_packed_f32x2(\n gate_pair,\n (\n neg_swiglu_alpha_log2_e,\n neg_swiglu_alpha_log2_e,\n ),\n )\n sigmoid = cute.arch.add_packed_f32x2(\n (\n cute.math.exp2(gate_log2e[0], fastmath=True),\n cute.math.exp2(gate_log2e[1], fastmath=True),\n ),\n (1.0, 1.0),\n )\n sigmoid = (\n cute.arch.rcp_approx(sigmoid[0]),\n cute.arch.rcp_approx(sigmoid[1]),\n )\n silu = cute.arch.mul_packed_f32x2(gate_pair, sigmoid)\n if cutlass.const_expr(self.parameterized_swiglu):\n up_pair = cute.arch.add_packed_f32x2(\n up_pair, (swiglu_beta, swiglu_beta)\n )\n result = cute.arch.mul_packed_f32x2(up_pair, silu)\n\n coord_0 = up_coords[i]\n coord_1 = up_coords[i + 1]\n # Fold paired TMEM rows back into the reduced-M\n # output tile and keep the staged N coordinate local.\n output_m_0 = coord_0[0] // 32 * 16 + coord_0[0] % 16\n output_m_1 = coord_1[0] // 32 * 16 + coord_1[0] % 16\n output_n_0 = coord_0[1] % self.epi_tile_n\n output_n_1 = coord_1[1] % self.epi_tile_n\n sC[(output_m_0, output_n_0, c_buffer)] = self.c_dtype(\n result[0]\n )\n sC[(output_m_1, output_n_1, c_buffer)] = self.c_dtype(\n result[1]\n )\n\n cute.arch.fence_proxy(\"async.shared\", space=\"cta\")\n self.epilog_sync_barrier.arrive_and_wait()\n if warp_idx == self.epilog_warp_id[0]:\n cute.copy(\n tma_atom_c,\n bSG_sC[(None, c_buffer)],\n bSG_gC[\n (\n None,\n work_tile.coord_n // self.epi_tile_n\n + gated_subtile_idx,\n )\n ],\n )\n c_pipeline.producer_commit()\n c_pipeline.producer_acquire()\n self.epilog_sync_barrier.arrive_and_wait()\n\n tTR_tAcc = cute.group_modes(tTR_tAcc, 3, cute.rank(tTR_tAcc))\n tTR_gC = cute.group_modes(tTR_gC, 3, cute.rank(tTR_gC))\n tma_distance_to_boundary = work_tile.distance_to_boundary\n\n # Store accumulator to global memory in subtiles\n subtile_cnt = (\n 0\n if cutlass.const_expr(self.gated)\n else cute.size(tTR_tAcc.shape, mode=[3])\n )\n for subtile_idx in cutlass.range(subtile_cnt):\n # Load accumulator from tensor memory buffer to register\n tTR_tAcc_mn = tTR_tAcc[(None, None, None, subtile_idx)]\n cute.copy(tiled_copy_t2r, tTR_tAcc_mn, tTR_rAcc)\n if subtile_idx == subtile_cnt - 1:\n cute.arch.fence_view_async_tmem_load()\n with cute.arch.elect_one():\n acc_pipeline.consumer_release(acc_consumer_state)\n acc_consumer_state.advance()\n\n if cutlass.const_expr(self.fuse_activation):\n alpha_f32 = cutlass.Float32(alpha_val)\n acc_up = tTR_rAcc.load()\n for i in cutlass.range_constexpr(0, cute.size(tTR_rAcc), 2):\n value = cute.arch.mul_packed_f32x2(\n (acc_up[i], acc_up[i + 1]),\n (alpha_f32, alpha_f32),\n )\n relu = (\n cute.arch.fmax(value[0], cutlass.Float32(0.0)),\n cute.arch.fmax(value[1], cutlass.Float32(0.0)),\n )\n tTR_rAcc[i], tTR_rAcc[i + 1] = cute.arch.mul_packed_f32x2(\n relu, relu\n )\n if cutlass.const_expr(self.use_fused_finalize):\n finalize_thr_slice = m_thr_offset[\n (None, None, None, subtile_idx)\n ]\n top_k = token_final_scales.shape[1]\n finalize_scale_route = epi_tidx\n finalize_scale_route_in_tile = (\n subtile_idx * self.epi_tile_n + finalize_scale_route\n )\n if finalize_scale_route < self.epi_tile_n:\n finalize_scale_permuted_row = (\n work_tile.coord_n + finalize_scale_route_in_tile\n )\n finalize_scale_expanded_idx = permuted_idx_to_expanded_idx[\n finalize_scale_permuted_row\n ]\n finalize_scale_safe_idx = cutlass.max(\n finalize_scale_expanded_idx, cutlass.Int32(0)\n )\n finalize_scale_token_idx = finalize_scale_safe_idx // top_k\n finalize_scale_topk_idx = finalize_scale_safe_idx % top_k\n finalize_scale_is_valid = cutlass.Int32(\n finalize_scale_route_in_tile\n < work_tile.distance_to_boundary\n )\n finalize_token_scale = token_final_scales[\n (\n finalize_scale_token_idx * finalize_scale_is_valid,\n finalize_scale_topk_idx,\n )\n ]\n sFinalizeScale[finalize_scale_route] = (\n cutlass.Float32(alpha_val)\n * cutlass.Float32(finalize_token_scale)\n * cutlass.Float32(finalize_scale_is_valid)\n )\n\n cute.arch.fence_proxy(\"async.shared\", space=\"cta\")\n self.epilog_sync_barrier.arrive_and_wait()\n for i in cutlass.range(cute.size(tTR_rC), unroll_full=True):\n finalize_route = finalize_thr_slice[(i)][1]\n finalize_value = sFinalizeScale[\n finalize_route % self.epi_tile_n\n ] * cutlass.Float32(tTR_rAcc[i])\n sFinalize[\n (\n finalize_route % self.epi_tile_n,\n finalize_thr_slice[(i)][0],\n )\n ] = self.c_dtype(finalize_value)\n\n cute.arch.fence_proxy(\"async.shared\", space=\"cta\")\n self.epilog_sync_barrier.arrive_and_wait()\n\n reduce_route = epi_tidx\n reduce_route_in_tile = (\n subtile_idx * self.epi_tile_n + reduce_route\n )\n if (\n reduce_route < self.epi_tile_n\n and reduce_route_in_tile < work_tile.distance_to_boundary\n ):\n reduce_permuted_row = (\n work_tile.coord_n + reduce_route_in_tile\n )\n reduce_expanded_idx = permuted_idx_to_expanded_idx[\n reduce_permuted_row\n ]\n reduce_token_idx = reduce_expanded_idx // top_k\n hidden_base = (\n work_tile.cta_coord_m * self.cta_tile_shape_mnk[0]\n )\n valid_elements = (\n cutlass.Int64(final_output.shape[0]) - hidden_base\n )\n if valid_elements > 0:\n scatter_out = cute.domain_offset(\n (hidden_base, reduce_token_idx, 0), final_output\n )\n copy_elements = cutlass.Int32(\n cutlass.min(\n cutlass.Int64(self.cta_tile_shape_mnk[0]),\n valid_elements,\n )\n )\n blk_reduce_bf16(\n scatter_out,\n sFinalize[(reduce_route, None)],\n copy_elements * (self.c_dtype.width // 8),\n )\n\n cute.arch.cp_async_bulk_commit_group()\n cute.arch.cp_async_bulk_wait_group(0, read=True)\n self.epilog_sync_barrier.arrive_and_wait()\n elif tma_distance_to_boundary >= self.cta_tile_shape_mnk[1]:\n # Convert to C type\n acc_vec = tiled_copy_r2s.retile(tTR_rAcc).load()\n if cutlass.const_expr(not self.fuse_activation):\n acc_vec = cutlass.Float32(alpha_val) * acc_vec\n acc_vec = acc_vec.to(self.c_dtype)\n tRS_rC.store(acc_vec)\n num_prev_subtiles += 1\n c_buffer = num_prev_subtiles % self.num_c_stage\n # Store C to shared memory\n cute.copy(\n tiled_copy_r2s,\n tRS_rC,\n tRS_sC[(None, None, None, c_buffer)],\n )\n # Fence and barrier to make sure shared memory store is visible to TMA store\n cute.arch.fence_proxy(\n \"async.shared\",\n space=\"cta\",\n )\n self.epilog_sync_barrier.arrive_and_wait()\n # TMA store C to global memory\n if warp_idx == self.epilog_warp_id[0]:\n cute.copy(\n tma_atom_c,\n bSG_sC[(None, c_buffer)],\n bSG_gC[(None, subtile_idx)],\n )\n c_pipeline.producer_commit()\n c_pipeline.producer_acquire()\n self.epilog_sync_barrier.arrive_and_wait()\n else:\n # Convert to C type\n acc_vec = tTR_rAcc.load()\n if cutlass.const_expr(not self.fuse_activation):\n acc_vec = cutlass.Float32(alpha_val) * acc_vec\n acc_vec = acc_vec.to(self.c_dtype)\n tTR_rC.store(acc_vec)\n # Compute predicate for SIMT store\n tCpC = cute.make_rmem_tensor(\n cute.make_layout(tTR_rC.shape),\n cutlass.Boolean,\n )\n m_thr_slice = m_thr_offset[(None, None, None, subtile_idx)]\n for i in cutlass.range(cute.size(tCpC), unroll_full=True):\n tCpC[i] = (\n m_thr_slice[(i)][0]\n + work_tile.cta_coord_m * self.cta_tile_shape_mnk_c[0]\n < cute.size(tensor_c.shape[0])\n ) and (m_thr_slice[(i)][1] < work_tile.distance_to_boundary)\n # Store C to global memory\n cute.copy(\n simt_atom,\n cute.flatten(tTR_rC),\n cute.flatten(tTR_gC[(None, None, None, subtile_idx)]),\n pred=cute.flatten(tCpC),\n )\n # Advance to next tile\n tile_info_pipeline.consumer_wait(tile_info_consumer_state)\n work_tile = mixed_input_utils.make_contiguous_group_work_tile_info(\n group_count, sTile_info[(None, tile_info_consumer_state.index)]\n )\n cute.arch.fence_proxy(\n \"async.shared\",\n space=\"cta\",\n )\n tile_info_pipeline.consumer_release(tile_info_consumer_state)\n tile_info_consumer_state.advance()\n\n # Dealloc the tensor memory buffer\n tmem.relinquish_alloc_permit()\n self.epilog_sync_barrier.arrive_and_wait()\n tmem.free(tmem_ptr)\n if cutlass.const_expr(not self.use_fused_finalize):\n c_pipeline.producer_tail()\n\n if cutlass.const_expr(self.enable_pdl and not self.fuse_activation):\n if warp_idx == self.mma_warp_id:\n with cute.arch.elect_one():\n griddepcontrol_launch_dependents()\n\n @staticmethod\n def _compute_stages_and_tmem_cols(\n tiled_mma: cute.TiledMma,\n mma_tiler_mnk: tuple[int, int, int],\n cta_tile_shape_mnk: tuple[int, int, int],\n epi_tile: cute.Tile,\n a_dtype: type[cutlass.Numeric],\n b_dtype: type[cutlass.Numeric],\n c_dtype: type[cutlass.Numeric],\n c_layout: utils.LayoutEnum,\n transform_a_source: tcgen05.OperandSource,\n smem_buffer_align_bytes: int,\n use_fused_finalize: bool,\n use_clc_scheduler: bool,\n ) -> tuple[int, int, int, int, int, int, int]:\n \"\"\"Fit the load, transform, accumulator, and epilogue pipelines.\"\"\"\n # Compute tmem columns required for accumulator\n acc_shape = tiled_mma.partition_shape_C(mma_tiler_mnk[:2])\n tCtAcc_stage1 = tiled_mma.make_fragment_C(cute.append(acc_shape, 1))\n num_tmem_acc_col_per_stage = utils.get_num_tmem_alloc_cols(tCtAcc_stage1, True)\n # Heuristic to decide the number of stages for accumulator\n sm100_tmem_columns = cute.arch.get_max_tmem_alloc_cols(\"sm_100\")\n accumulator_stage_count = sm100_tmem_columns // num_tmem_acc_col_per_stage\n if transform_a_source == tcgen05.OperandSource.TMEM:\n if num_tmem_acc_col_per_stage < 256:\n accumulator_stage_count = 2\n else:\n accumulator_stage_count = 1\n # transformed A in 16bit, thus 1 tmem column could hold 2 elements\n num_elts_per_tmem_col = 32 // tiled_mma.op.a_dtype.width\n num_tmem_cols_a_per_stage = cute.round_up(\n (\n cta_tile_shape_mnk[2] // num_elts_per_tmem_col\n if transform_a_source == tcgen05.OperandSource.TMEM\n else 0\n ),\n 4,\n )\n\n bytes_per_pipeline_stage = 16\n # Limit how far CLC can claim work ahead of the consumer pipelines.\n num_tile_info_stage = 1 if use_clc_scheduler else 3\n tile_info_bytes = (\n cute.size_in_bytes(cute.Int32, cute.make_layout((4, num_tile_info_stage)))\n + bytes_per_pipeline_stage * num_tile_info_stage\n )\n\n c_stage_count = 1 if use_fused_finalize else 2\n c_smem_layout_staged_one = sm100_utils.make_smem_layout_epi(\n c_dtype,\n c_layout,\n epi_tile,\n 1,\n )\n c_bytes_per_stage = cute.size_in_bytes(c_dtype, c_smem_layout_staged_one)\n c_bytes = c_bytes_per_stage * c_stage_count\n finalize_metadata_bytes = (\n cute.size_in_bytes(\n cutlass.Float32,\n cute.make_layout((cute.size(epi_tile[1]),)),\n )\n if use_fused_finalize\n else 0\n )\n\n smem_capacity = utils.get_smem_capacity_in_bytes(\"sm_100\")\n a_scale_k_mode = max(cta_tile_shape_mnk[2] // _NVFP4_SCALE_GRANULARITY_K, 1)\n a_scale_m_mode = max(cta_tile_shape_mnk[0] // _NVFP4_SCALE_GRANULARITY_M, 1)\n a_scale_bytes_per_stage = cute.round_up(\n cute.size_in_bytes(\n tiled_mma.op.a_dtype,\n cute.make_layout((a_scale_m_mode, a_scale_k_mode)),\n ),\n smem_buffer_align_bytes,\n )\n carveout_smem_bytes = (\n bytes_per_pipeline_stage * accumulator_stage_count\n + c_bytes\n + finalize_metadata_bytes\n + tile_info_bytes\n )\n\n # Compute transform stages if A is in TMEM\n num_tmem_acc_cols = cute.round_up(\n accumulator_stage_count * num_tmem_acc_col_per_stage, 4\n )\n\n transform2mma_stage_count_a_source_tmem_potential = (\n (sm100_tmem_columns - num_tmem_acc_cols) // num_tmem_cols_a_per_stage\n if transform_a_source == tcgen05.OperandSource.TMEM\n else -1\n )\n if (\n transform_a_source == tcgen05.OperandSource.TMEM\n and transform2mma_stage_count_a_source_tmem_potential <= 0\n ):\n raise ValueError(\"Not enough TMEM capacity for selected tile size\")\n a_load_bytes_per_stage = cute.round_up(\n cute.size_in_bytes(\n a_dtype,\n cute.make_layout((cta_tile_shape_mnk[0], cta_tile_shape_mnk[2])),\n ),\n smem_buffer_align_bytes,\n )\n b_load_bytes_per_stage = cute.round_up(\n cute.size_in_bytes(\n b_dtype,\n cute.make_layout(\n (\n cta_tile_shape_mnk[1] // cute.size(tiled_mma.thr_id),\n cta_tile_shape_mnk[2],\n )\n ),\n ),\n smem_buffer_align_bytes,\n )\n ab_scale_load_bytes_per_stage = (\n a_load_bytes_per_stage\n + b_load_bytes_per_stage\n + a_scale_bytes_per_stage\n + 2 * bytes_per_pipeline_stage\n )\n a_transform_bytes_per_stage = (\n cute.round_up(\n cute.size_in_bytes(\n tiled_mma.op.a_dtype,\n cute.make_layout((cta_tile_shape_mnk[0], cta_tile_shape_mnk[2])),\n ),\n smem_buffer_align_bytes,\n )\n if transform_a_source == tcgen05.OperandSource.SMEM\n else 0\n )\n\n a_transform_bytes_per_stage = (\n a_transform_bytes_per_stage + bytes_per_pipeline_stage\n )\n transform2mma_stage_count_a_source_smem_potential = (\n smem_capacity - carveout_smem_bytes\n ) // (ab_scale_load_bytes_per_stage + a_transform_bytes_per_stage)\n transform2mma_stage_count = (\n min(\n transform2mma_stage_count_a_source_tmem_potential,\n transform2mma_stage_count_a_source_smem_potential,\n )\n if transform_a_source == tcgen05.OperandSource.TMEM\n else transform2mma_stage_count_a_source_smem_potential\n )\n load2transform_stage_count = (\n smem_capacity\n - carveout_smem_bytes\n - (transform2mma_stage_count * a_transform_bytes_per_stage)\n ) // ab_scale_load_bytes_per_stage\n if (\n load2transform_stage_count < 2\n or transform2mma_stage_count < 2\n or accumulator_stage_count < 1\n ):\n raise ValueError(\"Not enough SMEM or TMEM capacity for selected tile size\")\n num_tmem_a_cols = transform2mma_stage_count * num_tmem_cols_a_per_stage\n # Fused finalize reuses its single C stage as reduction scratch.\n if not use_fused_finalize:\n c_stage_count += (\n smem_capacity\n - carveout_smem_bytes\n - load2transform_stage_count * ab_scale_load_bytes_per_stage\n - transform2mma_stage_count * a_transform_bytes_per_stage\n ) // c_bytes_per_stage\n\n return (\n load2transform_stage_count,\n transform2mma_stage_count,\n accumulator_stage_count,\n c_stage_count,\n num_tile_info_stage,\n num_tmem_acc_cols,\n num_tmem_a_cols,\n )\n\n @staticmethod\n def _compute_grid(\n c: cute.Tensor,\n cta_tile_shape_mnk: tuple[int, int, int],\n cluster_shape_mn: tuple[int, int],\n max_active_clusters: cutlass.Constexpr,\n use_clc_scheduler: bool,\n raster_along_m: bool,\n ) -> tuple[\n Union[\n utils.ClcDynamicPersistentTileSchedulerParams,\n utils.PersistentTileSchedulerParams,\n ],\n tuple[int, int, int],\n ]:\n \"\"\"Build the persistent scheduler and launch grid.\"\"\"\n c_shape = cute.slice_(cta_tile_shape_mnk, (None, None, 0))\n gc = cute.zipped_divide(c, tiler=c_shape)\n num_ctas_mnl = gc[(0, (None, None, None))].shape\n cluster_shape_mnl = (*cluster_shape_mn, 1)\n\n if use_clc_scheduler:\n tile_sched_params = utils.ClcDynamicPersistentTileSchedulerParams(\n num_ctas_mnl, cluster_shape_mnl\n )\n grid = utils.ClcDynamicPersistentTileScheduler.get_grid_shape(\n tile_sched_params\n )\n else:\n tile_sched_params = utils.PersistentTileSchedulerParams(\n num_ctas_mnl,\n cluster_shape_mnl,\n raster_along_m=raster_along_m,\n )\n grid = (cluster_shape_mn[0], cluster_shape_mn[1], max_active_clusters)\n\n return tile_sched_params, grid\n\n @staticmethod\n def can_implement(\n mnkl: tuple[int, int, int, int],\n a_dtype: type[cutlass.Numeric],\n b_dtype: type[cutlass.Numeric],\n c_dtype: type[cutlass.Numeric],\n a_major: str,\n b_major: str,\n c_major: str,\n mma_tiler: tuple[int, int, int],\n cluster_shape_mn: tuple[int, int],\n use_2cta_instrs: bool,\n ) -> bool:\n \"\"\"Return whether the requested layout and tile shape are supported.\"\"\"\n m, n, k, _ = mnkl\n\n if not mixed_input_utils.is_valid_mma_tiler_and_cluster_shape(\n mma_tiler, cluster_shape_mn, use_2cta_instrs\n ):\n return False\n # Unlike the generic mixed-input kernel, W4A16 consumes multiple\n # 16-value NVFP4 scale blocks within each MMA K tile.\n if (\n k % _NVFP4_SCALE_GRANULARITY_K != 0\n or mma_tiler[2] % _NVFP4_SCALE_GRANULARITY_K != 0\n ):\n return False\n if not mixed_input_utils.is_valid_tensor_alignment(\n m,\n n,\n k,\n a_dtype,\n b_dtype,\n c_dtype,\n b_dtype,\n a_major,\n b_major,\n c_major,\n mma_tiler,\n use_2cta_instrs,\n cluster_shape_mn,\n _NVFP4_SCALE_GRANULARITY_M,\n _NVFP4_SCALE_GRANULARITY_K,\n ):\n return False\n return True\n"},"after_code":{"kind":"string","value":"# Copyright (c) 2025 - 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.\n# SPDX-License-Identifier: BSD-3-Clause\n\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions are met:\n\n# 1. Redistributions of source code must retain the above copyright notice, this\n# list of conditions and the following disclaimer.\n\n# 2. Redistributions in binary form must reproduce the above copyright notice,\n# this list of conditions and the following disclaimer in the documentation\n# and/or other materials provided with the distribution.\n\n# 3. Neither the name of the copyright holder nor the names of its\n# contributors may be used to endorse or promote products derived from\n# this software without specific prior written permission.\n\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n\"\"\"SM100 grouped GEMM for NVFP4 expert weights and BF16 activations.\n\nEach routed-row tile selects one expert through FlashInfer's MoE sort metadata.\nThe kernel decodes each 16-value E2M1 weight block and its E4M3 scale to BF16,\nthen executes BF16 tensor-core MMA with FP32 accumulation.\n\"\"\"\n\nfrom math import ceil, log2\nfrom typing import Optional, Union\n\nimport cuda.bindings.driver as cuda\nimport cutlass\nimport cutlass.cute as cute\nimport cutlass.pipeline as pipeline\nfrom cutlass.pipeline import pipeline_init_arrive, pipeline_init_wait\nimport cutlass.utils as utils\nimport cutlass.utils.blackwell_helpers as sm100_utils\nimport cutlass.utils.blockscaled_layout as blockscaled_utils\nimport cutlass.utils.mixed_input_helpers as mixed_input_utils\nfrom cutlass.utils.mixed_input_helpers import TransformMode\nfrom cutlass.cute.nvgpu import cpasync, tcgen05\n\nfrom flashinfer.tllm_enums import (\n ActivationType,\n DEFAULT_SWIGLU_ALPHA,\n DEFAULT_SWIGLU_BETA,\n DEFAULT_SWIGLU_LIMIT,\n)\n\nfrom ..moe_utils import validate_cute_dsl_moe_situ_config\nfrom .moe_w4a16_utils import decode_nvfp4_fragment_to_bf16\nfrom .utils import (\n blk_reduce_bf16,\n f32_reciprocal,\n fmin,\n gelu_tanh_f32,\n griddepcontrol_launch_dependents,\n griddepcontrol_wait,\n situ_f32,\n tanh_f32,\n)\n\n\n_NVFP4_SCALE_GRANULARITY_M = 1\n_NVFP4_SCALE_GRANULARITY_K = 16\n_TMA_CACHE_HINT_EVICT_FIRST = 0x12F0000000000000\n_TMA_CACHE_HINT_EVICT_LAST = 0x14F0000000000000\n\n\nclass Sm100W4A16GroupedGemmKernel:\n \"\"\"Warp-specialized grouped GEMM for the W4A16 MoE pipeline.\"\"\"\n\n def __init__(\n self,\n acc_dtype: type[cutlass.Numeric],\n use_2cta_instrs: bool,\n mma_tiler_mnk: tuple[int, int, int],\n cluster_shape_mn: tuple[int, int],\n group_count: int,\n activation_type: Optional[int],\n swiglu_alpha: float,\n swiglu_beta: float,\n swiglu_limit: float,\n situ_beta: Optional[float],\n situ_linear_beta: Optional[float],\n use_fused_finalize: bool,\n enable_pdl: bool,\n use_clc_scheduler: bool,\n raster_along_m: bool,\n transform_fragment_size: int,\n ):\n \"\"\"Initialize the W4A16 grouped GEMM configuration.\"\"\"\n self.group_count = group_count\n self.acc_dtype = acc_dtype\n self.use_2cta_instrs = use_2cta_instrs\n self.cluster_shape_mn = cluster_shape_mn\n self.mma_tiler = mma_tiler_mnk\n if activation_type not in (\n None,\n ActivationType.Swiglu.value,\n ActivationType.GegluTanh.value,\n ActivationType.Relu2.value,\n ):\n raise ValueError(\n f\"unsupported W4A16 epilogue activation: {activation_type}\"\n )\n self.fuse_activation = activation_type is not None\n self.use_clc_scheduler = use_clc_scheduler\n self.raster_along_m = raster_along_m\n self.transform_fragment_size = transform_fragment_size\n if activation_type is None:\n if situ_beta is not None or situ_linear_beta is not None:\n raise ValueError(\"SiTU parameters require an activation\")\n else:\n validate_cute_dsl_moe_situ_config(\n ActivationType(activation_type), situ_beta, situ_linear_beta\n )\n self.activation_type = activation_type\n self.gated = activation_type in (\n ActivationType.Swiglu.value,\n ActivationType.GegluTanh.value,\n )\n self.swiglu_alpha = swiglu_alpha\n self.swiglu_beta = swiglu_beta\n self.swiglu_limit = swiglu_limit\n self.situ_beta = situ_beta\n self.situ_linear_beta = situ_linear_beta\n self.parameterized_swiglu = (\n swiglu_alpha != DEFAULT_SWIGLU_ALPHA\n or swiglu_beta != DEFAULT_SWIGLU_BETA\n or swiglu_limit != DEFAULT_SWIGLU_LIMIT\n )\n self.output_m_factor = 2 if self.gated else 1\n if self.gated and use_fused_finalize:\n raise ValueError(\n \"W4A16 fused finalize is only implemented for the non-gated epilogue\"\n )\n self.use_fused_finalize = use_fused_finalize\n self.enable_pdl = enable_pdl\n self.cta_group = (\n tcgen05.CtaGroup.TWO if self.use_2cta_instrs else tcgen05.CtaGroup.ONE\n )\n self.epilog_warp_id = (0, 1, 2, 3)\n self.mma_warp_id = 4\n self.schedule_warp_id = 5\n self.weight_tma_warp_id = 6\n self.activation_tma_warp_id = 7\n self.num_transform_warpgroups = 2\n self.transform_warp_id = tuple(range(8, 8 + 4 * self.num_transform_warpgroups))\n self.num_transform_warps = len(self.transform_warp_id)\n # Keep the role-control warpgroup on one absolute register target.\n # Transform warps retain the 128-register launch default.\n self.num_regs_epilogue_warps = 176\n self.num_regs_generic_warps = 80\n self.threads_per_cta = 32 * (\n max(\n (\n self.mma_warp_id,\n self.schedule_warp_id,\n self.weight_tma_warp_id,\n self.activation_tma_warp_id,\n *self.epilog_warp_id,\n *self.transform_warp_id,\n )\n )\n + 1\n )\n\n self.epilog_sync_barrier = pipeline.NamedBarrier(\n 1, 32 * len(self.epilog_warp_id)\n )\n self.tmem_ptr_sync_barrier = pipeline.NamedBarrier(2, self.threads_per_cta)\n self.sched_sync_barrier = pipeline.NamedBarrier(5, 32)\n\n self.smem_buffer_align_bytes = 1024\n\n def _setup_attributes(self):\n \"\"\"Derive static MMA, pipeline, and storage layouts from operand types.\"\"\"\n self.transform_a_source = mixed_input_utils.get_transform_a_source(\n self.a_major_mode\n )\n tiled_mma = sm100_utils.make_trivial_tiled_mma(\n self.mma_dtype,\n self.a_major_mode,\n self.b_major_mode,\n self.acc_dtype,\n self.cta_group,\n self.mma_tiler[:2],\n self.transform_a_source,\n )\n self.cta_tile_shape_mnk = (\n self.mma_tiler[0] // cute.size(tiled_mma.thr_id.shape),\n self.mma_tiler[1],\n self.mma_tiler[2],\n )\n self.mma_tiler_c = (\n self.mma_tiler[0] // self.output_m_factor,\n self.mma_tiler[1],\n self.mma_tiler[2],\n )\n self.cta_tile_shape_mnk_c = (\n self.cta_tile_shape_mnk[0] // self.output_m_factor,\n self.cta_tile_shape_mnk[1],\n self.cta_tile_shape_mnk[2],\n )\n self.cluster_layout_vmnk = cute.tiled_divide(\n cute.make_layout((*self.cluster_shape_mn, 1)),\n (tiled_mma.thr_id.shape,),\n )\n self.num_mcast_ctas_a = cute.size(self.cluster_layout_vmnk.shape[2])\n self.num_mcast_ctas_b = cute.size(self.cluster_layout_vmnk.shape[1])\n self.is_a_mcast = self.num_mcast_ctas_a > 1\n self.is_b_mcast = self.num_mcast_ctas_b > 1\n\n default_epi_tile = sm100_utils.compute_epilogue_tile_shape(\n self.cta_tile_shape_mnk,\n self.use_2cta_instrs,\n self.c_layout,\n self.c_dtype,\n )\n self.epi_tile = (\n (self.cta_tile_shape_mnk_c[0], default_epi_tile[1])\n if self.gated\n else default_epi_tile\n )\n self.epi_tile_n = cute.size(self.epi_tile[1])\n\n (\n self.num_load2trans_stage,\n self.num_trans2mma_stage,\n self.num_acc_stage,\n self.num_c_stage,\n self.num_tile_info_stage,\n self.num_acc_tmem_cols,\n self.num_a_tmem_cols,\n ) = self._compute_stages_and_tmem_cols(\n tiled_mma,\n self.mma_tiler,\n self.cta_tile_shape_mnk,\n self.epi_tile,\n self.a_dtype,\n self.b_dtype,\n self.c_dtype,\n self.c_layout,\n self.transform_a_source,\n self.smem_buffer_align_bytes,\n self.use_fused_finalize,\n self.use_clc_scheduler,\n )\n\n # TMEM allocation requires power-of-two column alignment.\n self.num_tmem_alloc_cols = cute.round_up(\n self.num_acc_tmem_cols + self.num_a_tmem_cols,\n cute.arch.get_min_tmem_alloc_cols(\"sm_100\"),\n )\n self.num_tmem_alloc_cols = 2 ** (ceil(log2(self.num_tmem_alloc_cols)))\n self.c_smem_layout_staged = sm100_utils.make_smem_layout_epi(\n self.c_dtype,\n self.c_layout,\n self.epi_tile,\n self.num_c_stage,\n )\n (\n self.smem_layout_a,\n self.smem_layout_a_transform,\n self.smem_layout_b,\n ) = mixed_input_utils.compute_smem_layout(\n tiled_mma,\n self.mma_tiler,\n self.a_dtype,\n self.b_dtype,\n self.num_load2trans_stage,\n self.num_trans2mma_stage,\n )\n scale_tile_shape = (\n self.cta_tile_shape_mnk[0],\n self.mma_tiler[2],\n )\n # The transform and TMA partitions use different logical views of the\n # same block-scaled shared-memory storage.\n scale_smem_layout = blockscaled_utils.make_smem_layout_sf(\n scale_tile_shape,\n _NVFP4_SCALE_GRANULARITY_K,\n self.num_load2trans_stage,\n )\n scale_smem_layout_per_stage = cute.slice_(scale_smem_layout, (None, None, 0))\n trivial_swizzle = cute.make_swizzle(0, 4, 3)\n self.smem_layout_scale_per_stage = cute.make_composed_layout(\n trivial_swizzle, 0, scale_smem_layout_per_stage\n )\n self.smem_layout_scale = cute.make_composed_layout(\n trivial_swizzle, 0, scale_smem_layout\n )\n self.smem_layout_scale_tma = blockscaled_utils.make_smem_layout_sfa(\n tiled_mma,\n self.mma_tiler,\n _NVFP4_SCALE_GRANULARITY_K,\n self.num_load2trans_stage,\n )\n\n @cute.jit\n def _setup_transform_partitions(\n self,\n tiled_mma: cute.TiledMma,\n copy_atom_a_input: cute.CopyAtom,\n copy_atom_a_transform: cute.CopyAtom,\n sA_transform_input: cute.Tensor,\n a_smem_layout_transform: cute.ComposedLayout,\n sA_transform: cute.Tensor,\n tCsS: cute.Tensor,\n accumulators: cute.Tensor,\n transform_tidx: cutlass.Int32,\n transform_group_idx: cutlass.Int32,\n ):\n if cutlass.const_expr(self.transform_a_source == tcgen05.OperandSource.TMEM):\n tmem_ptr_transform = cute.recast_ptr(\n accumulators.iterator + self.num_acc_tmem_cols,\n dtype=self.mma_dtype,\n )\n transform_destination = cute.make_tensor(\n tmem_ptr_transform,\n tiled_mma.make_fragment_A(a_smem_layout_transform.outer).layout,\n )\n else:\n transform_destination = sA_transform\n\n src_copy_a, dst_copy_a, tAsA_input, tAsA_transform = (\n mixed_input_utils.transform_partition(\n self.transform_a_source,\n TransformMode.ConvertScale,\n copy_atom_a_input,\n copy_atom_a_transform,\n sA_transform_input,\n transform_destination,\n transform_tidx,\n )\n )\n num_transform_blocks = cute.size(tAsA_input, mode=[3])\n assert num_transform_blocks % self.num_transform_warpgroups == 0, (\n \"A blocks must divide evenly across transform warpgroups\"\n )\n blocks_per_transform_group = (\n num_transform_blocks // self.num_transform_warpgroups\n )\n transform_group_tiler = (\n None,\n None,\n None,\n blocks_per_transform_group,\n None,\n )\n transform_group_coord = (\n None,\n None,\n None,\n (None, transform_group_idx),\n None,\n )\n tAsA_input = cute.logical_divide(tAsA_input, transform_group_tiler)[\n transform_group_coord\n ]\n tAsA_transform = cute.logical_divide(tAsA_transform, transform_group_tiler)[\n transform_group_coord\n ]\n\n a_stage_coord = (None,) * (cute.rank(tAsA_input) - 1) + (0,)\n tArA = cute.make_rmem_tensor(\n tAsA_input[a_stage_coord].shape,\n tAsA_input.element_type,\n )\n tArA_transform = cute.make_rmem_tensor(\n tAsA_input[a_stage_coord].shape,\n self.mma_dtype,\n )\n\n smem_thr_copy_S = src_copy_a.get_slice(transform_tidx)\n tSsS_trans = smem_thr_copy_S.partition_S(tCsS)\n tSsS_trans = cute.logical_divide(tSsS_trans, transform_group_tiler)[\n transform_group_coord\n ]\n scale_stage_coord = (None,) * (cute.rank(tSsS_trans) - 1) + (0,)\n tSsS_layout_per_stage = tSsS_trans[scale_stage_coord].layout\n tSrS_copy = cute.make_rmem_tensor(\n cute.filter_zeros(tSsS_layout_per_stage).shape,\n self.a_scale_dtype,\n )\n tSrS = cute.make_tensor(\n tSrS_copy.iterator,\n cute.make_layout(\n tSsS_layout_per_stage.shape,\n stride=tSrS_copy.layout.stride,\n ),\n )\n assert cute.size(tSrS, mode=[0]) == cute.size(tArA, mode=[0]), (\n \"tSrS and tArA have different leading dimension\"\n )\n assert cute.size(tSrS) == cute.size(tArA), \"tSrS and tArA have different shape\"\n\n transform_tiler_size = min(\n cute.size(cute.coalesce(tAsA_input.layout), mode=[0]),\n self.transform_fragment_size,\n )\n assert transform_tiler_size % _NVFP4_SCALE_GRANULARITY_K == 0, (\n \"transform fragment must cover whole NVFP4 scale blocks\"\n )\n transform_tiler = cute.make_layout(transform_tiler_size)\n tArA_load = cute.flat_divide(tArA, transform_tiler)\n tArA_load = cute.group_modes(tArA_load, 1, cute.rank(tArA_load))\n scale_tiler = cute.make_layout(\n transform_tiler_size // _NVFP4_SCALE_GRANULARITY_K\n )\n tSrS_load = cute.flat_divide(tSrS_copy, scale_tiler)\n tSrS_load = cute.group_modes(tSrS_load, 1, cute.rank(tSrS_load))\n tArA_transform_store = cute.flat_divide(tArA_transform, transform_tiler)\n tArA_transform_store = cute.group_modes(\n tArA_transform_store,\n 1,\n cute.rank(tArA_transform_store),\n )\n return (\n dst_copy_a,\n tAsA_input,\n tAsA_transform,\n tSsS_trans,\n tSrS_copy,\n tSrS_load,\n tArA_load,\n tArA_transform,\n tArA_transform_store,\n transform_tiler,\n )\n\n @cute.jit\n def _transform_tile(\n self,\n a_load2trans_pipeline: pipeline.PipelineTmaAsync,\n trans2mma_pipeline: pipeline.PipelineAsyncUmma,\n a_load2trans_consumer_state: pipeline.PipelineState,\n trans2mma_producer_state: pipeline.PipelineState,\n dst_copy_a: cute.CopyAtom,\n tAsA_input: cute.Tensor,\n tAsA_transform: cute.Tensor,\n tSsS_trans: cute.Tensor,\n tSrS_copy: cute.Tensor,\n tSrS_load: cute.Tensor,\n tArA_load: cute.Tensor,\n tArA_transform: cute.Tensor,\n tArA_transform_store: cute.Tensor,\n transform_tiler: cute.Layout,\n k_tile_cnt: cutlass.Int32,\n ) -> tuple[pipeline.PipelineState, pipeline.PipelineState]:\n a_load2trans_consumer_state.reset_count()\n peek_load2trans_full_status = cutlass.Boolean(1)\n if a_load2trans_consumer_state.count < k_tile_cnt:\n peek_load2trans_full_status = a_load2trans_pipeline.consumer_try_wait(\n a_load2trans_consumer_state\n )\n trans2mma_producer_state.reset_count()\n peek_trans2mma_empty_status = cutlass.Boolean(1)\n if trans2mma_producer_state.count < k_tile_cnt:\n peek_trans2mma_empty_status = trans2mma_pipeline.producer_try_acquire(\n trans2mma_producer_state\n )\n\n for _k_tile in cutlass.range(0, k_tile_cnt, 1, unroll=1):\n a_load2trans_pipeline.consumer_wait(\n a_load2trans_consumer_state,\n peek_load2trans_full_status,\n )\n a_stage_coord = (None,) * (cute.rank(tAsA_input) - 1) + (\n a_load2trans_consumer_state.index,\n )\n tAsA_input_slice = tAsA_input[a_stage_coord]\n tAsA_input_slice = cute.flat_divide(tAsA_input_slice, transform_tiler)\n tAsA_input_slice = cute.group_modes(\n tAsA_input_slice,\n 1,\n cute.rank(tAsA_input_slice),\n )\n trans2mma_pipeline.producer_acquire(\n trans2mma_producer_state,\n peek_trans2mma_empty_status,\n )\n scale_stage_coord = (None,) * (cute.rank(tSsS_trans) - 1) + (\n a_load2trans_consumer_state.index,\n )\n tSsS_slice = tSsS_trans[scale_stage_coord]\n tSsS_slice_filtered = cute.make_tensor(\n tSsS_slice.iterator,\n cute.filter_zeros(tSsS_slice.layout),\n )\n cute.autovec_copy(tSsS_slice_filtered, tSrS_copy)\n cur_a_load2trans_consumer_state = a_load2trans_consumer_state.clone()\n for idx in cutlass.range_constexpr(cute.size(tArA_load, mode=[1])):\n cute.autovec_copy(\n tAsA_input_slice[(None, idx)],\n tArA_load[(None, idx)],\n )\n if cutlass.const_expr(idx == cute.size(tArA_load, mode=[1]) - 1):\n a_load2trans_consumer_state.advance()\n if a_load2trans_consumer_state.count < k_tile_cnt:\n peek_load2trans_full_status = (\n a_load2trans_pipeline.consumer_try_wait(\n a_load2trans_consumer_state\n )\n )\n packed_fragment = cute.recast_tensor(\n tArA_load[(None, idx)], cutlass.Uint8\n ).load()\n scale_slice = tSrS_load[(None, idx)]\n scale_slice_compact = cute.make_tensor(\n scale_slice.iterator,\n cute.filter_zeros(scale_slice.layout),\n )\n scale_fragment = cute.recast_tensor(\n scale_slice_compact, cutlass.Uint8\n ).load()\n tensor_transformed = decode_nvfp4_fragment_to_bf16(\n packed_fragment,\n scale_fragment,\n )\n tArA_transform_store[(None, idx)].store(tensor_transformed)\n\n a_transform_stage_coord = (None,) * (cute.rank(tAsA_transform) - 1) + (\n trans2mma_producer_state.index,\n )\n mixed_input_utils.store_transformed_a(\n tArA_transform,\n tAsA_transform[a_transform_stage_coord],\n dst_copy_a,\n )\n if cutlass.const_expr(\n self.transform_a_source == tcgen05.OperandSource.TMEM\n ):\n cute.arch.fence_view_async_tmem_store()\n else:\n cute.arch.fence_proxy(\"async.shared\", space=\"cta\")\n a_load2trans_pipeline.consumer_release(cur_a_load2trans_consumer_state)\n trans2mma_pipeline.producer_commit(trans2mma_producer_state)\n trans2mma_producer_state.advance()\n if trans2mma_producer_state.count < k_tile_cnt:\n peek_trans2mma_empty_status = trans2mma_pipeline.producer_try_acquire(\n trans2mma_producer_state\n )\n\n return a_load2trans_consumer_state, trans2mma_producer_state\n\n @cute.jit\n def wrapper(\n self,\n weight_ptr: cute.Pointer,\n weight_sf_ptr: cute.Pointer,\n activation_ptr: cute.Pointer,\n tile_idx_to_expert_idx_ptr: cute.Pointer,\n tile_idx_to_mn_limit_ptr: cute.Pointer,\n num_non_exiting_tiles_ptr: cute.Pointer,\n alpha_ptr: cute.Pointer,\n output_ptr: cute.Pointer,\n permuted_idx_to_expanded_idx_ptr: Optional[cute.Pointer],\n token_final_scales_ptr: Optional[cute.Pointer],\n m: cutlass.Int64,\n n: cutlass.Int64,\n k: cutlass.Int64,\n num_tokens: cutlass.Int64,\n top_k: cutlass.Int64,\n max_active_clusters: cutlass.Constexpr,\n stream: cuda.CUstream,\n ):\n \"\"\"Build logical tensors over FlashInfer's packed NVFP4 storage.\"\"\"\n weights = cute.make_tensor(\n weight_ptr,\n cute.make_ordered_layout((m, k, self.group_count), order=(1, 0, 2)),\n )\n weight_sf = cute.make_tensor(\n weight_sf_ptr,\n blockscaled_utils.tile_atom_to_shape_SF(\n weights.shape, _NVFP4_SCALE_GRANULARITY_K\n ),\n )\n activations = cute.make_tensor(\n activation_ptr,\n cute.make_ordered_layout((n, k, 1), order=(1, 0, 2)),\n )\n output_m = m // self.output_m_factor\n output_layout = cute.make_ordered_layout((output_m, n, 1), order=(0, 1, 2))\n output = cute.make_tensor(output_ptr, output_layout)\n final_output = (\n cute.make_tensor(\n output_ptr,\n cute.make_ordered_layout((output_m, num_tokens, 1), order=(0, 1, 2)),\n )\n if cutlass.const_expr(self.use_fused_finalize)\n else output\n )\n num_route_tiles = n // self.mma_tiler[1]\n tile_idx_to_expert_idx = cute.make_tensor(\n tile_idx_to_expert_idx_ptr, cute.make_layout((num_route_tiles,))\n )\n tile_idx_to_mn_limit = cute.make_tensor(\n tile_idx_to_mn_limit_ptr, cute.make_layout((num_route_tiles,))\n )\n num_non_exiting_tiles = cute.make_tensor(\n num_non_exiting_tiles_ptr, cute.make_layout((1,))\n )\n alpha = cute.make_tensor(alpha_ptr, cute.make_layout((self.group_count,)))\n permuted_idx_to_expanded_idx = (\n cute.make_tensor(permuted_idx_to_expanded_idx_ptr, cute.make_layout((n,)))\n if cutlass.const_expr(self.use_fused_finalize)\n else None\n )\n token_final_scales = (\n cute.make_tensor(\n token_final_scales_ptr,\n cute.make_ordered_layout((num_tokens, top_k), order=(1, 0)),\n )\n if cutlass.const_expr(self.use_fused_finalize)\n else None\n )\n return self(\n weights,\n weight_sf,\n activations,\n tile_idx_to_expert_idx,\n tile_idx_to_mn_limit,\n num_non_exiting_tiles,\n alpha,\n output,\n final_output,\n permuted_idx_to_expanded_idx,\n token_final_scales,\n max_active_clusters,\n stream,\n )\n\n @cute.jit\n def __call__(\n self,\n a: cute.Tensor,\n a_scale: cute.Tensor,\n b: cute.Tensor,\n tile_idx_to_expert_idx: cute.Tensor,\n tile_idx_to_mn_limit: cute.Tensor,\n num_non_exiting_tiles: cute.Tensor,\n alpha: cute.Tensor,\n c: cute.Tensor,\n final_output: cute.Tensor,\n permuted_idx_to_expanded_idx: Optional[cute.Tensor],\n token_final_scales: Optional[cute.Tensor],\n max_active_clusters: cutlass.Constexpr,\n stream: cuda.CUstream,\n ):\n \"\"\"Configure and launch the grouped GEMM.\"\"\"\n self.a_dtype: type[cutlass.Numeric] = a.element_type\n self.a_scale_dtype: type[cutlass.Numeric] = a_scale.element_type\n self.b_dtype: type[cutlass.Numeric] = b.element_type\n self.c_dtype: type[cutlass.Numeric] = c.element_type\n self.mma_dtype = self.b_dtype\n\n self.a_major_mode = utils.LayoutEnum.from_tensor(a).mma_major_mode()\n self.b_major_mode = utils.LayoutEnum.from_tensor(b).mma_major_mode()\n self.c_layout = utils.LayoutEnum.from_tensor(c)\n\n if cutlass.const_expr(\n utils.LayoutEnum.from_tensor(a_scale).mma_major_mode()\n != cute.nvgpu.OperandMajorMode.K\n ):\n raise ValueError(\"scale_major_mode must be K-major\")\n\n self._setup_attributes()\n\n tiled_mma = sm100_utils.make_trivial_tiled_mma(\n self.mma_dtype,\n self.a_major_mode,\n self.b_major_mode,\n self.acc_dtype,\n self.cta_group,\n self.mma_tiler[:2],\n self.transform_a_source,\n )\n a_op = mixed_input_utils.get_tma_atom_kind(\n self.is_a_mcast, self.use_2cta_instrs, False\n )\n b_op = mixed_input_utils.get_tma_atom_kind(\n self.is_b_mcast, self.use_2cta_instrs, True\n )\n smem_layout_a_per_stage = cute.slice_(self.smem_layout_a, (None, None, None, 0))\n tma_atom_a, tma_tensor_a = cute.nvgpu.make_tiled_tma_atom_A(\n a_op,\n a,\n smem_layout_a_per_stage,\n self.mma_tiler,\n tiled_mma,\n self.cluster_layout_vmnk.shape,\n internal_type=(\n cutlass.TFloat32 if a.element_type is cutlass.Float32 else None\n ),\n )\n\n scale_smem_layout_for_tma = cute.slice_(\n self.smem_layout_scale_tma, (None, None, None, 0)\n )\n tma_atom_scale, tma_tensor_scale = cute.nvgpu.make_tiled_tma_atom_A(\n a_op,\n a_scale,\n scale_smem_layout_for_tma,\n self.mma_tiler,\n tiled_mma,\n self.cluster_layout_vmnk.shape,\n internal_type=cutlass.Int16,\n )\n\n smem_layout_b_per_stage = cute.slice_(self.smem_layout_b, (None, None, None, 0))\n tma_atom_b, tma_tensor_b = cute.nvgpu.make_tiled_tma_atom_B(\n b_op,\n b,\n smem_layout_b_per_stage,\n self.mma_tiler,\n tiled_mma,\n self.cluster_layout_vmnk.shape,\n internal_type=(\n cutlass.TFloat32 if b.element_type is cutlass.Float32 else None\n ),\n )\n\n a_copy_size = cute.size_in_bytes(self.a_dtype, smem_layout_a_per_stage)\n b_copy_size = cute.size_in_bytes(self.b_dtype, smem_layout_b_per_stage)\n a_scale_copy_size = cute.size_in_bytes(\n self.a_scale_dtype, self.smem_layout_scale_per_stage\n )\n\n self.num_tma_load_bytes_a_scale = a_copy_size + a_scale_copy_size\n self.num_tma_load_bytes_b = b_copy_size * cute.size(tiled_mma.thr_id.shape)\n self.tile_sched_params, grid = self._compute_grid(\n c,\n self.cta_tile_shape_mnk_c,\n self.cluster_shape_mn,\n max_active_clusters,\n self.use_clc_scheduler,\n self.raster_along_m,\n )\n\n epi_smem_layout = cute.slice_(self.c_smem_layout_staged, (None, None, 0))\n tma_atom_c, tma_tensor_c = cpasync.make_tiled_tma_atom(\n cpasync.CopyBulkTensorTileS2GOp(),\n c,\n epi_smem_layout,\n self.epi_tile,\n )\n\n @cute.struct\n class SharedStorage:\n # Routed-tile scheduling metadata.\n tile_info: cute.struct.MemRange[cutlass.Int32, 4 * self.num_tile_info_stage]\n a_load2trans_full_mbar_ptr: cute.struct.MemRange[\n cutlass.Int64, self.num_load2trans_stage\n ]\n a_load2trans_empty_mbar_ptr: cute.struct.MemRange[\n cutlass.Int64, self.num_load2trans_stage\n ]\n a_trans2mma_full_mbar_ptr: cute.struct.MemRange[\n cutlass.Int64, self.num_trans2mma_stage\n ]\n a_trans2mma_empty_mbar_ptr: cute.struct.MemRange[\n cutlass.Int64, self.num_trans2mma_stage\n ]\n b_load2mma_full_mbar_ptr: cute.struct.MemRange[\n cutlass.Int64, self.num_load2trans_stage\n ]\n b_load2mma_empty_mbar_ptr: cute.struct.MemRange[\n cutlass.Int64, self.num_load2trans_stage\n ]\n acc_full_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.num_acc_stage]\n acc_empty_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.num_acc_stage]\n tile_info_full_mbar_ptr: cute.struct.MemRange[\n cutlass.Int64, self.num_tile_info_stage\n ]\n tile_info_empty_mbar_ptr: cute.struct.MemRange[\n cutlass.Int64, self.num_tile_info_stage\n ]\n clc_mbar_ptr: cute.struct.MemRange[cutlass.Int64, 2]\n clc_response: cute.struct.Align[cute.struct.MemRange[cutlass.Int32, 4], 16]\n tmem_dealloc_mbar: cutlass.Int64\n tmem_holding_buf: cutlass.Int32\n\n self.shared_storage = SharedStorage\n\n self.kernel(\n tiled_mma,\n tma_atom_a,\n tma_tensor_a,\n tma_atom_scale,\n tma_tensor_scale,\n tma_atom_b,\n tma_tensor_b,\n tma_atom_c,\n tma_tensor_c,\n c,\n final_output,\n tile_idx_to_expert_idx,\n tile_idx_to_mn_limit,\n num_non_exiting_tiles,\n alpha,\n permuted_idx_to_expanded_idx,\n token_final_scales,\n self.group_count,\n self.cluster_layout_vmnk,\n self.smem_layout_a,\n self.smem_layout_scale,\n self.smem_layout_scale_tma,\n self.smem_layout_a_transform,\n self.smem_layout_b,\n self.c_smem_layout_staged,\n self.epi_tile,\n self.tile_sched_params,\n ).launch(\n grid=grid,\n block=[self.threads_per_cta, 1, 1],\n cluster=(*self.cluster_shape_mn, 1),\n min_blocks_per_mp=1,\n stream=stream,\n use_pdl=self.enable_pdl,\n )\n\n @cute.kernel\n def kernel(\n self,\n tiled_mma: cute.TiledMma,\n tma_atom_a: cute.CopyAtom,\n mA_mkl: cute.Tensor,\n tma_atom_s: cute.CopyAtom,\n mS_mkl: cute.Tensor,\n tma_atom_b: cute.CopyAtom,\n mB_nkl: cute.Tensor,\n tma_atom_c: cute.CopyAtom,\n mC_mnl: cute.Tensor,\n tensor_c: cute.Tensor,\n final_output: cute.Tensor,\n tile_idx_to_expert_idx: cute.Tensor,\n tile_idx_to_mn_limit: cute.Tensor,\n num_non_exiting_tiles: cute.Tensor,\n alpha: cute.Tensor,\n permuted_idx_to_expanded_idx: Optional[cute.Tensor],\n token_final_scales: Optional[cute.Tensor],\n group_count: cutlass.Constexpr[int],\n cluster_layout_vmnk: cute.Layout,\n a_smem_layout: cute.ComposedLayout,\n scale_smem_layout: cute.ComposedLayout,\n scale_tma_smem_layout: cute.Layout,\n a_smem_layout_transform: cute.ComposedLayout,\n b_smem_layout: cute.ComposedLayout,\n c_smem_layout_staged: cute.ComposedLayout,\n epi_tile: cute.Tile,\n tile_sched_params: Union[\n utils.ClcDynamicPersistentTileSchedulerParams,\n utils.PersistentTileSchedulerParams,\n ],\n ):\n \"\"\"Run the persistent W4A16 grouped GEMM.\"\"\"\n warp_idx = cute.arch.make_warp_uniform(cute.arch.warp_idx())\n tidx, _, _ = cute.arch.thread_idx()\n bidx, bidy, bidz = cute.arch.block_idx()\n # Prefetch TMA descriptors\n if warp_idx == self.epilog_warp_id[0]:\n cpasync.prefetch_descriptor(tma_atom_a)\n cpasync.prefetch_descriptor(tma_atom_b)\n cpasync.prefetch_descriptor(tma_atom_s)\n cpasync.prefetch_descriptor(tma_atom_c)\n\n use_2cta_instrs = cute.size(tiled_mma.thr_id.shape) == 2\n mma_tile_coord_v = bidx % cute.size(tiled_mma.thr_id.shape)\n is_leader_cta = mma_tile_coord_v == 0\n cta_rank_in_cluster = cute.arch.make_warp_uniform(\n cute.arch.block_idx_in_cluster()\n )\n is_first_cta_in_cluster = cta_rank_in_cluster == 0\n block_in_cluster_coord_vmnk = cluster_layout_vmnk.get_flat_coord(\n cta_rank_in_cluster\n )\n smem = utils.SmemAllocator()\n storage = smem.allocate(self.shared_storage)\n clc_response_ptr = storage.clc_response.data_ptr()\n\n # Initialize load2transform pipeline for the weight operand.\n transform_thread_idx = (\n tidx - 32 * self.transform_warp_id[0]\n if tidx >= 32 * self.transform_warp_id[0]\n else tidx\n )\n a_load2trans_pipeline = pipeline.PipelineTmaAsync.create(\n barrier_storage=storage.a_load2trans_full_mbar_ptr.data_ptr(),\n num_stages=self.num_load2trans_stage,\n producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread),\n consumer_group=pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n self.num_mcast_ctas_a * self.num_transform_warps,\n ),\n tx_count=self.num_tma_load_bytes_a_scale,\n cta_layout_vmnk=cluster_layout_vmnk,\n tidx=transform_thread_idx,\n mcast_mode_mn=(1, 0), # multicast for A will only happen on the M-mode\n defer_sync=True,\n )\n # Initialize transform2mma pipeline, which tracks the dependencies between the transformation\n # of A and MMA's consumption of transformed A\n cta_v_size = cute.size(cluster_layout_vmnk, mode=[0])\n trans2mma_pipeline = pipeline.PipelineAsyncUmma.create(\n barrier_storage=storage.a_trans2mma_full_mbar_ptr.data_ptr(),\n num_stages=self.num_trans2mma_stage,\n producer_group=pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n 32 * self.num_transform_warps * cta_v_size,\n ),\n consumer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread),\n cta_layout_vmnk=cluster_layout_vmnk,\n defer_sync=True,\n )\n # Initialize pipeline for tensor B load to MMA\n # MMA warp informs TMA warp to proceed to load next tile of B tensor\n b_load2mma_pipeline = pipeline.PipelineTmaUmma.create(\n barrier_storage=storage.b_load2mma_full_mbar_ptr.data_ptr(),\n num_stages=self.num_load2trans_stage,\n producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread),\n consumer_group=pipeline.CooperativeGroup(\n pipeline.Agent.Thread, self.num_mcast_ctas_b\n ),\n tx_count=self.num_tma_load_bytes_b,\n cta_layout_vmnk=cluster_layout_vmnk,\n mcast_mode_mn=(0, 1), # multicast for B will only happen on the N-mode\n defer_sync=True,\n )\n # Initialize accumulator pipeline, which tracks the dependencies between\n # MMA's computation of accumulators and epilogue warps' consumption of accumulators\n acc_pipeline = pipeline.PipelineUmmaAsync.create(\n barrier_storage=storage.acc_full_mbar_ptr.data_ptr(),\n num_stages=self.num_acc_stage,\n producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread),\n consumer_group=pipeline.CooperativeGroup(\n pipeline.Agent.Thread, cta_v_size * len(self.epilog_warp_id)\n ),\n cta_layout_vmnk=cluster_layout_vmnk,\n defer_sync=True,\n )\n # Initialize tile info pipeline, which tracks the dependencies between\n # tile scheduling warp and other warps\n # Every warp except the scheduler consumes routed-tile metadata.\n num_tile_info_pipeline_consumer_threads = self.threads_per_cta - 32\n tile_info_pipeline = pipeline.PipelineAsync.create(\n barrier_storage=storage.tile_info_full_mbar_ptr.data_ptr(),\n num_stages=self.num_tile_info_stage,\n producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread, 32 * 1),\n consumer_group=pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n num_tile_info_pipeline_consumer_threads,\n ),\n defer_sync=True,\n )\n clc_pipeline = None\n if cutlass.const_expr(self.use_clc_scheduler):\n clc_pipeline = pipeline.PipelineClcFetchAsync.create(\n barrier_storage=storage.clc_mbar_ptr.data_ptr(),\n num_stages=1,\n producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread),\n consumer_group=pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n 32 * cute.size(self.cluster_shape_mn),\n ),\n tx_count=16,\n cta_layout_vmnk=cluster_layout_vmnk,\n defer_sync=True,\n )\n\n # Tensor memory dealloc barrier init\n tmem = utils.TmemAllocator(\n storage.tmem_holding_buf.ptr,\n barrier_for_retrieve=self.tmem_ptr_sync_barrier,\n allocator_warp_id=self.epilog_warp_id[0],\n is_two_cta=use_2cta_instrs,\n two_cta_tmem_dealloc_mbar_ptr=storage.tmem_dealloc_mbar.ptr,\n )\n\n # Cluster arrive after barrier init\n pipeline_init_arrive(cluster_shape_mn=self.cluster_shape_mn, is_relaxed=True)\n\n # Setup smem tensor A/scale/B/C\n sC = smem.allocate_tensor(\n element_type=self.c_dtype,\n layout=c_smem_layout_staged.outer,\n byte_alignment=self.smem_buffer_align_bytes,\n swizzle=c_smem_layout_staged.inner,\n )\n # Fused finalize reuses the first C stage as a linear\n # [route, hidden] tile for descriptor-free bulk reduction. The bulk\n # reduction consumes raw contiguous bytes, so drop sC's pointer swizzle.\n sFinalize = (\n cute.make_tensor(\n cute.recast_ptr(sC.iterator),\n cute.make_layout(\n (self.epi_tile_n, self.cta_tile_shape_mnk[0]),\n stride=(self.cta_tile_shape_mnk[0], 1),\n ),\n )\n if cutlass.const_expr(self.use_fused_finalize)\n else None\n )\n sA_input = smem.allocate_tensor(\n element_type=self.a_dtype,\n layout=a_smem_layout.outer,\n byte_alignment=self.smem_buffer_align_bytes,\n swizzle=a_smem_layout.inner,\n )\n sS_input = smem.allocate_tensor(\n element_type=self.a_scale_dtype,\n layout=scale_smem_layout.outer,\n byte_alignment=self.smem_buffer_align_bytes,\n swizzle=scale_smem_layout.inner,\n )\n sS_tma = cute.make_tensor(sS_input.iterator, scale_tma_smem_layout)\n sA_transform_input = sA_input\n sS_transform_input = sS_input\n if cutlass.const_expr(self.gated):\n # Pair 16-row up/gate slices during decode so each epilogue warp\n # owns both operands in its 32 TMEM lanes.\n gated_row_layout = cute.make_layout(((16, 2), 4), stride=((1, 64), 16))\n sA_transform_input = cute.composition(\n sA_input,\n ((gated_row_layout, None), None, None, None),\n )\n sS_transform_input = cute.composition(\n sS_input,\n ((gated_row_layout, None), None, None),\n )\n sB_input = smem.allocate_tensor(\n element_type=self.b_dtype,\n layout=b_smem_layout.outer,\n byte_alignment=self.smem_buffer_align_bytes,\n swizzle=b_smem_layout.inner,\n )\n sA_transform = None\n # Get smem tensor for transformed A when transform_a_source is SMEM\n if cutlass.const_expr(self.transform_a_source == tcgen05.OperandSource.SMEM):\n sA_transform = smem.allocate_tensor(\n element_type=self.mma_dtype,\n layout=a_smem_layout_transform.outer,\n byte_alignment=self.smem_buffer_align_bytes,\n swizzle=a_smem_layout_transform.inner,\n )\n sFinalizeScale = (\n smem.allocate_tensor(\n element_type=cutlass.Float32,\n layout=cute.make_layout((self.epi_tile_n,)),\n byte_alignment=16,\n )\n if cutlass.const_expr(self.use_fused_finalize)\n else None\n )\n sTile_info = storage.tile_info.get_tensor(\n cute.make_layout((4, self.num_tile_info_stage), stride=(1, 4))\n )\n\n # Compute multicast mask for A/B buffer full\n a_full_mcast_mask = None\n b_full_mcast_mask = None\n s_full_mcast_mask = None\n if cutlass.const_expr(self.is_a_mcast or self.is_b_mcast or use_2cta_instrs):\n a_full_mcast_mask = cpasync.create_tma_multicast_mask(\n cluster_layout_vmnk, block_in_cluster_coord_vmnk, mcast_mode=2\n )\n # Scale tensor shares the same multicast mask as the A tensor\n s_full_mcast_mask = a_full_mcast_mask\n b_full_mcast_mask = cpasync.create_tma_multicast_mask(\n cluster_layout_vmnk, block_in_cluster_coord_vmnk, mcast_mode=1\n )\n\n # local_tile partition global tensors\n # (bM, bK, loopM, loopK, loopL)\n gA_mkl = cute.local_tile(\n mA_mkl, cute.slice_(self.mma_tiler, (None, 0, None)), (None, None, None)\n )\n # (bM, bK, loopM, loopK, loopL)\n gS_mkl = cute.local_tile(\n mS_mkl,\n cute.slice_(self.mma_tiler, (None, 0, None)),\n (None, None, None),\n )\n # (bN, bK, loopN, loopK, loopL)\n gB_nkl = cute.local_tile(\n mB_nkl, cute.slice_(self.mma_tiler, (0, None, None)), (None, None, None)\n )\n # (bM, bN, loopM, loopN, loopL)\n gC_mnl = cute.local_tile(\n mC_mnl,\n cute.slice_(self.mma_tiler_c, (None, None, 0)),\n (None, None, None),\n )\n gC_mnl_simt = cute.local_tile(\n tensor_c,\n cute.slice_(self.mma_tiler_c, (None, None, 0)),\n (None, None, None),\n )\n k_tile_cnt = cutlass.Int32(cute.size(gA_mkl, mode=[3]))\n\n # Partition global tensor for TiledMMA_A/B/C\n thr_mma = tiled_mma.get_slice(mma_tile_coord_v)\n # (MMA, MMA_M, MMA_K, loopM, loopK, loopL)\n tCgA = thr_mma.partition_A(gA_mkl)\n # (MMA, MMA_M, MMA_K, loopM, loopK, loopL)\n tCgS = thr_mma.partition_A(gS_mkl)\n # (MMA, MMA_N, MMA_K, loopN, loopK, loopL)\n tCgB = thr_mma.partition_B(gB_nkl)\n # (MMA, MMA_M, MMA_N, loopM, loopN, loopL)\n tCgC = thr_mma.partition_C(gC_mnl)\n tCgC_simt = thr_mma.partition_C(gC_mnl_simt)\n\n # Setup copy atom to load A from shared memory for further transformation\n copy_atom_a_input = cute.make_copy_atom(\n cute.nvgpu.CopyUniversalOp(), self.a_dtype, num_bits_per_copy=32\n )\n # Split complete NVFP4 blocks between two transform warpgroups.\n copy_atom_a_transform = cute.make_copy_atom(\n tcgen05.St32x32bOp(\n tcgen05.Repetition(8),\n tcgen05.Unpack.NONE,\n ),\n self.mma_dtype,\n )\n\n # Partition global/shared tensor for TMA load A/B\n # TMA load A partition_S/D\n a_cta_layout = cute.make_layout(\n cute.slice_(cluster_layout_vmnk, (0, 0, None, 0)).shape\n )\n # ((atom_v, rest_v), STAGE)\n # ((atom_v, rest_v), loopM, loopK, loopL)\n tAsA, tAgA = cpasync.tma_partition(\n tma_atom_a,\n block_in_cluster_coord_vmnk[2],\n a_cta_layout,\n cute.group_modes(sA_input, 0, 3),\n cute.group_modes(tCgA, 0, 3),\n )\n\n thr_mma_leader_cta = tiled_mma.get_slice(0)\n # (MMA, MMA_M, MMA_K, STAGE)\n tCsS = thr_mma_leader_cta.partition_A(sS_transform_input)\n tSsS, tSgS = cpasync.tma_partition(\n tma_atom_s,\n block_in_cluster_coord_vmnk[2],\n a_cta_layout,\n cute.group_modes(sS_tma, 0, 3),\n cute.group_modes(tCgS, 0, 3),\n )\n tSsS = cute.filter_zeros(tSsS)\n tSgS = cute.filter_zeros(tSgS)\n\n # TMA load B partition_S/D\n b_cta_layout = cute.make_layout(\n cute.slice_(cluster_layout_vmnk, (0, None, 0, 0)).shape\n )\n # ((atom_v, rest_v), STAGE)\n # ((atom_v, rest_v), loopM, loopK, loopL)\n tBsB, tBgB = cpasync.tma_partition(\n tma_atom_b,\n block_in_cluster_coord_vmnk[1],\n b_cta_layout,\n cute.group_modes(sB_input, 0, 3),\n cute.group_modes(tCgB, 0, 3),\n )\n\n # (MMA, MMA_N, MMA_K, STAGE)\n tCrB = tiled_mma.make_fragment_B(sB_input)\n # (MMA, MMA_M, MMA_N)\n acc_shape = tiled_mma.partition_shape_C(self.mma_tiler[:2])\n tCtAcc_fake = tiled_mma.make_fragment_C(\n cute.append(acc_shape, self.num_acc_stage)\n )\n\n # Cluster wait before TMEM alloc and ensure pipelines are ready.\n pipeline_init_wait(cluster_shape_mn=self.cluster_shape_mn)\n\n # TMEM allocation\n tmem.allocate(self.num_tmem_alloc_cols)\n tmem.wait_for_alloc()\n\n # Tile scheduling is independent of the preceding grid.\n if warp_idx == self.schedule_warp_id:\n cute.arch.setmaxregister_decrease(self.num_regs_generic_warps)\n tile_info_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.num_tile_info_stage\n )\n num_non_exiting_tiles_value = num_non_exiting_tiles[0]\n if cutlass.const_expr(self.use_clc_scheduler):\n tile_sched = utils.ClcDynamicPersistentTileScheduler.create(\n tile_sched_params,\n (bidx, bidy, bidz),\n cute.arch.grid_dim(),\n clc_response_ptr,\n )\n work_tile = tile_sched.initial_work_tile_info()\n clc_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.ProducerConsumer, 1\n )\n clc_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, 1\n )\n not_last_tile = cutlass.Boolean(1)\n while not_last_tile:\n tile_coord_mnl = work_tile.tile_idx\n route_tile_idx = tile_coord_mnl[1]\n is_routed_tile = work_tile.is_valid_tile and (\n route_tile_idx < num_non_exiting_tiles_value\n )\n\n if is_routed_tile or not work_tile.is_valid_tile:\n tile_info_pipeline.producer_acquire(tile_info_producer_state)\n\n if work_tile.is_valid_tile and is_first_cta_in_cluster:\n clc_pipeline.producer_acquire(clc_producer_state)\n tile_sched.advance_to_next_work(\n clc_pipeline.producer_get_barrier(clc_producer_state)\n )\n clc_producer_state.advance()\n\n if is_routed_tile or not work_tile.is_valid_tile:\n cur_sTile_info = sTile_info[\n (None, tile_info_producer_state.index)\n ]\n route_start = cutlass.Int32(-1)\n group_idx = cutlass.Int32(group_count)\n distance_to_boundary = cutlass.Int32(-1)\n if is_routed_tile:\n route_start = route_tile_idx * self.cta_tile_shape_mnk[1]\n group_idx = tile_idx_to_expert_idx[route_tile_idx]\n distance_to_boundary = (\n tile_idx_to_mn_limit[route_tile_idx] - route_start\n )\n with cute.arch.elect_one():\n cur_sTile_info[0] = tile_coord_mnl[0]\n cur_sTile_info[1] = route_start\n cur_sTile_info[2] = group_idx\n cur_sTile_info[3] = distance_to_boundary\n cute.arch.fence_proxy(\"async.shared\", space=\"cta\")\n self.sched_sync_barrier.arrive_and_wait()\n tile_info_pipeline.producer_commit(tile_info_producer_state)\n tile_info_producer_state.advance()\n\n if work_tile.is_valid_tile:\n clc_pipeline.consumer_wait(clc_consumer_state)\n work_tile = tile_sched.get_current_work()\n clc_pipeline.consumer_release(clc_consumer_state)\n clc_consumer_state.advance()\n else:\n not_last_tile = cutlass.Boolean(0)\n\n tile_info_pipeline.producer_tail(tile_info_producer_state)\n if is_first_cta_in_cluster:\n clc_pipeline.producer_tail(clc_producer_state)\n else:\n tile_sched = utils.StaticPersistentRuntimeTileScheduler.create(\n tile_sched_params,\n (bidx, bidy, bidz),\n cute.arch.grid_dim(),\n inner_mode=0 if self.raster_along_m else 1,\n )\n work_tile = tile_sched.initial_work_tile_info()\n not_last_tile = cutlass.Boolean(1)\n if cutlass.const_expr(self.raster_along_m):\n while not_last_tile:\n tile_info_pipeline.producer_acquire(tile_info_producer_state)\n cluster_tile_coord_mnl = work_tile.tile_idx\n cta_tile_coord_m = (\n cluster_tile_coord_mnl[0] * self.cluster_shape_mn[0]\n + block_in_cluster_coord_vmnk[1]\n * cute.size(tiled_mma.thr_id.shape)\n + block_in_cluster_coord_vmnk[0]\n )\n cta_tile_offset_n = block_in_cluster_coord_vmnk[2]\n route_tile_idx = (\n cluster_tile_coord_mnl[1] * self.cluster_shape_mn[1]\n + cta_tile_offset_n\n )\n not_last_tile = work_tile.is_valid_tile and (\n route_tile_idx < num_non_exiting_tiles_value\n )\n route_start = cutlass.Int32(-1)\n group_idx = cutlass.Int32(group_count)\n distance_to_boundary = cutlass.Int32(-1)\n if not_last_tile:\n route_start = route_tile_idx * self.cta_tile_shape_mnk[1]\n group_idx = tile_idx_to_expert_idx[route_tile_idx]\n distance_to_boundary = (\n tile_idx_to_mn_limit[route_tile_idx] - route_start\n )\n cur_sTile_info = sTile_info[\n (None, tile_info_producer_state.index)\n ]\n with cute.arch.elect_one():\n cur_sTile_info[0] = cta_tile_coord_m\n cur_sTile_info[1] = route_start\n cur_sTile_info[2] = group_idx\n cur_sTile_info[3] = distance_to_boundary\n cute.arch.fence_proxy(\"async.shared\", space=\"cta\")\n self.sched_sync_barrier.arrive_and_wait()\n tile_info_pipeline.producer_commit(tile_info_producer_state)\n tile_info_producer_state.advance()\n tile_sched.advance_to_next_work()\n work_tile = tile_sched.get_current_work()\n else:\n while not_last_tile:\n cluster_tile_coord_mnl = work_tile.tile_idx\n cta_tile_coord_m = (\n cluster_tile_coord_mnl[0] * self.cluster_shape_mn[0]\n + block_in_cluster_coord_vmnk[1]\n * cute.size(tiled_mma.thr_id.shape)\n + block_in_cluster_coord_vmnk[0]\n )\n cta_tile_offset_n = block_in_cluster_coord_vmnk[2]\n route_tile_idx = (\n cluster_tile_coord_mnl[1] * self.cluster_shape_mn[1]\n + cta_tile_offset_n\n )\n # The runtime scheduler leaves its outer mode unbounded.\n # With N as the inner mode, terminate on the finite M\n # extent and skip padded routed tiles within each M tile.\n has_work = work_tile.is_valid_tile and (\n cluster_tile_coord_mnl[0]\n < tile_sched_params.problem_layout_ncluster_mnl.shape[0]\n )\n is_routed_tile = has_work and (\n route_tile_idx < num_non_exiting_tiles_value\n )\n\n if is_routed_tile or not has_work:\n tile_info_pipeline.producer_acquire(\n tile_info_producer_state\n )\n route_start = cutlass.Int32(-1)\n group_idx = cutlass.Int32(group_count)\n distance_to_boundary = cutlass.Int32(-1)\n if is_routed_tile:\n route_start = (\n route_tile_idx * self.cta_tile_shape_mnk[1]\n )\n group_idx = tile_idx_to_expert_idx[route_tile_idx]\n distance_to_boundary = (\n tile_idx_to_mn_limit[route_tile_idx] - route_start\n )\n cur_sTile_info = sTile_info[\n (None, tile_info_producer_state.index)\n ]\n with cute.arch.elect_one():\n cur_sTile_info[0] = cta_tile_coord_m\n cur_sTile_info[1] = route_start\n cur_sTile_info[2] = group_idx\n cur_sTile_info[3] = distance_to_boundary\n cute.arch.fence_proxy(\"async.shared\", space=\"cta\")\n self.sched_sync_barrier.arrive_and_wait()\n tile_info_pipeline.producer_commit(tile_info_producer_state)\n tile_info_producer_state.advance()\n\n if has_work:\n tile_sched.advance_to_next_work()\n work_tile = tile_sched.get_current_work()\n else:\n not_last_tile = cutlass.Boolean(0)\n\n tile_info_pipeline.producer_tail(tile_info_producer_state)\n\n # The activation TMA warp is the only role that waits on the preceding grid.\n if warp_idx == self.activation_tma_warp_id:\n cute.arch.setmaxregister_decrease(self.num_regs_generic_warps)\n tile_info_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.num_tile_info_stage\n )\n tile_info_pipeline.consumer_wait(tile_info_consumer_state)\n work_tile = mixed_input_utils.make_contiguous_group_work_tile_info(\n group_count, sTile_info[(None, tile_info_consumer_state.index)]\n )\n cute.arch.fence_proxy(\n \"async.shared\",\n space=\"cta\",\n )\n tile_info_pipeline.consumer_release(tile_info_consumer_state)\n tile_info_consumer_state.advance()\n b_load2mma_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.num_load2trans_stage\n )\n if cutlass.const_expr(self.enable_pdl):\n griddepcontrol_wait()\n\n while work_tile.is_valid_tile:\n coord_n_offset = (\n (work_tile.coord_n, 0)\n if cutlass.const_expr(\n self.b_major_mode == cute.nvgpu.OperandMajorMode.MN\n )\n else (0, work_tile.coord_n)\n )\n tBgB_slice = cute.make_tensor(\n (\n tBgB.iterator[0] + coord_n_offset[0],\n coord_n_offset[1] + tBgB.iterator[1],\n ),\n cute.slice_(tBgB.layout, (None, 0, None, 0)),\n )\n\n b_load2mma_producer_state.reset_count()\n for _k_tile in cutlass.range(0, k_tile_cnt, 1, unroll=1):\n b_load2mma_pipeline.producer_acquire(b_load2mma_producer_state)\n cute.copy(\n tma_atom_b,\n tBgB_slice[(None, b_load2mma_producer_state.count)],\n tBsB[(None, b_load2mma_producer_state.index)],\n tma_bar_ptr=b_load2mma_pipeline.producer_get_barrier(\n b_load2mma_producer_state\n ),\n mcast_mask=b_full_mcast_mask,\n cache_policy=cutlass.Int64(_TMA_CACHE_HINT_EVICT_LAST),\n )\n b_load2mma_pipeline.producer_commit(b_load2mma_producer_state)\n b_load2mma_producer_state.advance()\n\n tile_info_pipeline.consumer_wait(tile_info_consumer_state)\n work_tile = mixed_input_utils.make_contiguous_group_work_tile_info(\n group_count, sTile_info[(None, tile_info_consumer_state.index)]\n )\n cute.arch.fence_proxy(\n \"async.shared\",\n space=\"cta\",\n )\n tile_info_pipeline.consumer_release(tile_info_consumer_state)\n tile_info_consumer_state.advance()\n b_load2mma_pipeline.producer_tail(b_load2mma_producer_state)\n\n # Static weight and scale loads can run before the activation is ready.\n if warp_idx == self.weight_tma_warp_id:\n cute.arch.setmaxregister_decrease(self.num_regs_generic_warps)\n tile_info_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.num_tile_info_stage\n )\n tile_info_pipeline.consumer_wait(tile_info_consumer_state)\n work_tile = mixed_input_utils.make_contiguous_group_work_tile_info(\n group_count, sTile_info[(None, tile_info_consumer_state.index)]\n )\n cute.arch.fence_proxy(\n \"async.shared\",\n space=\"cta\",\n )\n tile_info_pipeline.consumer_release(tile_info_consumer_state)\n tile_info_consumer_state.advance()\n a_load2trans_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.num_load2trans_stage\n )\n if cutlass.const_expr(self.enable_pdl and self.fuse_activation):\n with cute.arch.elect_one():\n griddepcontrol_launch_dependents()\n while work_tile.is_valid_tile:\n tAgA_slice = tAgA[\n (\n None,\n work_tile.cta_coord_m // cute.size(tiled_mma.thr_id.shape),\n None,\n work_tile.group_idx,\n )\n ]\n tSgS_slice = tSgS[\n (\n None,\n work_tile.cta_coord_m // cute.size(tiled_mma.thr_id.shape),\n None,\n work_tile.group_idx,\n )\n ]\n # Filter zeros in rest mode\n rest_filtered = cute.filter_zeros(tSgS_slice[(0, None)].layout)\n tSgS_slice_filtered = cute.make_tensor(\n tSgS_slice.iterator,\n cute.make_layout(\n (tSgS_slice.layout[0].shape, rest_filtered.shape),\n stride=(tSgS_slice.layout[0].stride, rest_filtered.stride),\n ),\n )\n\n a_load2trans_producer_state.reset_count()\n peek_load2trans_empty_status = cutlass.Boolean(1)\n if a_load2trans_producer_state.count < k_tile_cnt:\n peek_load2trans_empty_status = (\n a_load2trans_pipeline.producer_try_acquire(\n a_load2trans_producer_state\n )\n )\n for _k_tile in cutlass.range(0, k_tile_cnt, 1, unroll=1):\n a_load2trans_pipeline.producer_acquire(\n a_load2trans_producer_state,\n peek_load2trans_empty_status,\n )\n cute.copy(\n tma_atom_a,\n tAgA_slice[(None, a_load2trans_producer_state.count)],\n tAsA[(None, a_load2trans_producer_state.index)],\n tma_bar_ptr=a_load2trans_pipeline.producer_get_barrier(\n a_load2trans_producer_state\n ),\n mcast_mask=a_full_mcast_mask,\n cache_policy=cutlass.Int64(_TMA_CACHE_HINT_EVICT_FIRST),\n )\n cute.copy(\n tma_atom_s,\n tSgS_slice_filtered[(None, a_load2trans_producer_state.count)],\n tSsS[(None, a_load2trans_producer_state.index)],\n tma_bar_ptr=a_load2trans_pipeline.producer_get_barrier(\n a_load2trans_producer_state\n ),\n mcast_mask=s_full_mcast_mask,\n )\n a_load2trans_pipeline.producer_commit(a_load2trans_producer_state)\n a_load2trans_producer_state.advance()\n if a_load2trans_producer_state.count < k_tile_cnt:\n peek_load2trans_empty_status = (\n a_load2trans_pipeline.producer_try_acquire(\n a_load2trans_producer_state\n )\n )\n\n tile_info_pipeline.consumer_wait(tile_info_consumer_state)\n work_tile = mixed_input_utils.make_contiguous_group_work_tile_info(\n group_count, sTile_info[(None, tile_info_consumer_state.index)]\n )\n cute.arch.fence_proxy(\n \"async.shared\",\n space=\"cta\",\n )\n tile_info_pipeline.consumer_release(tile_info_consumer_state)\n tile_info_consumer_state.advance()\n\n a_load2trans_pipeline.producer_tail(a_load2trans_producer_state)\n\n # Specialized transform warps\n if warp_idx >= self.transform_warp_id[0]:\n transform_group_idx = (warp_idx - self.transform_warp_id[0]) // 4\n transform_local_tidx = tidx - 32 * (\n self.transform_warp_id[0] + transform_group_idx * 4\n )\n # Get the pointer to the TMEM buffer\n tmem_ptr = tmem.retrieve_ptr(self.acc_dtype)\n accumulators = cute.make_tensor(tmem_ptr, tCtAcc_fake.layout)\n\n (\n dst_copy_a,\n tAsA_input,\n tAsA_transform,\n tSsS_trans,\n tSrS_copy,\n tSrS_load,\n tArA_load,\n tArA_transform,\n tArA_transform_store,\n transform_tiler,\n ) = self._setup_transform_partitions(\n tiled_mma,\n copy_atom_a_input,\n copy_atom_a_transform,\n sA_transform_input,\n a_smem_layout_transform,\n sA_transform,\n tCsS,\n accumulators,\n transform_local_tidx,\n transform_group_idx,\n )\n\n tile_info_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.num_tile_info_stage\n )\n tile_info_pipeline.consumer_wait(tile_info_consumer_state)\n work_tile = mixed_input_utils.make_contiguous_group_work_tile_info(\n group_count, sTile_info[(None, tile_info_consumer_state.index)]\n )\n cute.arch.fence_proxy(\n \"async.shared\",\n space=\"cta\",\n )\n tile_info_pipeline.consumer_release(tile_info_consumer_state)\n tile_info_consumer_state.advance()\n a_load2trans_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer,\n self.num_load2trans_stage,\n )\n trans2mma_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer,\n self.num_trans2mma_stage,\n )\n while work_tile.is_valid_tile:\n (\n a_load2trans_consumer_state,\n trans2mma_producer_state,\n ) = self._transform_tile(\n a_load2trans_pipeline,\n trans2mma_pipeline,\n a_load2trans_consumer_state,\n trans2mma_producer_state,\n dst_copy_a,\n tAsA_input,\n tAsA_transform,\n tSsS_trans,\n tSrS_copy,\n tSrS_load,\n tArA_load,\n tArA_transform,\n tArA_transform_store,\n transform_tiler,\n k_tile_cnt,\n )\n # Advance to next tile\n tile_info_pipeline.consumer_wait(tile_info_consumer_state)\n work_tile = mixed_input_utils.make_contiguous_group_work_tile_info(\n group_count, sTile_info[(None, tile_info_consumer_state.index)]\n )\n cute.arch.fence_proxy(\n \"async.shared\",\n space=\"cta\",\n )\n tile_info_pipeline.consumer_release(tile_info_consumer_state)\n tile_info_consumer_state.advance()\n # Wait a_transform buffer empty\n trans2mma_pipeline.producer_tail(trans2mma_producer_state)\n\n # Specialized MMA warp\n if warp_idx == self.mma_warp_id:\n cute.arch.setmaxregister_decrease(self.num_regs_generic_warps)\n # Get the pointer to the TMEM buffer\n tmem_ptr = tmem.retrieve_ptr(self.acc_dtype)\n accumulators = cute.make_tensor(tmem_ptr, tCtAcc_fake.layout)\n if cutlass.const_expr(\n self.transform_a_source == tcgen05.OperandSource.TMEM\n ):\n tmem_ptr_transform = cute.recast_ptr(\n accumulators.iterator + self.num_acc_tmem_cols, dtype=self.mma_dtype\n )\n tCrA = cute.make_tensor(\n tmem_ptr_transform,\n tiled_mma.make_fragment_A(a_smem_layout_transform.outer).layout,\n )\n else:\n tCrA = tiled_mma.make_fragment_A(sA_transform)\n tCtAcc_base = accumulators\n # Persistent tile scheduling loop\n tile_info_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.num_tile_info_stage\n )\n tile_info_pipeline.consumer_wait(tile_info_consumer_state)\n work_tile = mixed_input_utils.make_contiguous_group_work_tile_info(\n group_count, sTile_info[(None, tile_info_consumer_state.index)]\n )\n cute.arch.fence_proxy(\n \"async.shared\",\n space=\"cta\",\n )\n tile_info_pipeline.consumer_release(tile_info_consumer_state)\n tile_info_consumer_state.advance()\n trans2mma_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.num_trans2mma_stage\n )\n b_load2mma_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.num_load2trans_stage\n )\n acc_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.num_acc_stage\n )\n while work_tile.is_valid_tile:\n # (MMA, MMA_M, MMA_N)\n tCtAcc = tCtAcc_base[(None, None, None, acc_producer_state.index)]\n b_load2mma_consumer_state.reset_count()\n trans2mma_consumer_state.reset_count()\n peek_trans2mma_full_status = cutlass.Boolean(1)\n if is_leader_cta:\n if trans2mma_consumer_state.count < k_tile_cnt:\n peek_trans2mma_full_status = (\n trans2mma_pipeline.consumer_try_wait(\n trans2mma_consumer_state\n )\n )\n acc_pipeline.producer_acquire(acc_producer_state)\n\n tiled_mma.set(tcgen05.Field.ACCUMULATE, False)\n # Mma mainloop\n for _k_tile in cutlass.range(0, k_tile_cnt, 1, unroll=1):\n trans2mma_pipeline.consumer_wait(\n trans2mma_consumer_state, peek_trans2mma_full_status\n )\n b_load2mma_pipeline.consumer_wait(b_load2mma_consumer_state)\n num_kblocks = cute.size(tCrA, mode=[2])\n for kblock_idx in cutlass.range(num_kblocks, unroll_full=True):\n kblock_coord_a = (\n None,\n None,\n kblock_idx,\n trans2mma_consumer_state.index,\n )\n kblock_coord_b = (\n None,\n None,\n kblock_idx,\n b_load2mma_consumer_state.index,\n )\n\n cute.gemm(\n tiled_mma,\n tCtAcc,\n tCrA[kblock_coord_a],\n tCrB[kblock_coord_b],\n tCtAcc,\n )\n # Enable accumulate on tCtAcc after first kblock\n tiled_mma.set(tcgen05.Field.ACCUMULATE, True)\n trans2mma_pipeline.consumer_release(trans2mma_consumer_state)\n b_load2mma_pipeline.consumer_release(b_load2mma_consumer_state)\n trans2mma_consumer_state.advance()\n b_load2mma_consumer_state.advance()\n peek_trans2mma_full_status = cutlass.Boolean(1)\n if trans2mma_consumer_state.count < k_tile_cnt:\n peek_trans2mma_full_status = (\n trans2mma_pipeline.consumer_try_wait(\n trans2mma_consumer_state\n )\n )\n # Async arrive accumulator buffer full\n acc_pipeline.producer_commit(acc_producer_state)\n acc_producer_state.advance()\n\n # Advance to next tile\n tile_info_pipeline.consumer_wait(tile_info_consumer_state)\n work_tile = mixed_input_utils.make_contiguous_group_work_tile_info(\n group_count, sTile_info[(None, tile_info_consumer_state.index)]\n )\n cute.arch.fence_proxy(\n \"async.shared\",\n space=\"cta\",\n )\n tile_info_pipeline.consumer_release(tile_info_consumer_state)\n tile_info_consumer_state.advance()\n # Wait for accumulator buffer empty\n acc_pipeline.producer_tail(acc_producer_state)\n\n # Specialized epilogue warps\n if warp_idx < self.mma_warp_id:\n cute.arch.setmaxregister_increase(self.num_regs_epilogue_warps)\n epi_tidx = tidx\n # Get the pointer to the TMEM buffer\n tmem_ptr = tmem.retrieve_ptr(self.acc_dtype)\n accumulators = cute.make_tensor(tmem_ptr, tCtAcc_fake.layout)\n tCtAcc_base = accumulators\n # Partition for epilogue\n tiled_copy_t2r, tTR_tAcc_base, tTR_rAcc = (\n mixed_input_utils.epilog_tmem_copy_and_partition(\n self.cta_tile_shape_mnk,\n self.c_layout,\n self.c_dtype,\n self.acc_dtype,\n epi_tidx,\n tCtAcc_base,\n tCgC,\n epi_tile,\n self.use_2cta_instrs,\n )\n )\n gated_tTR_tAcc_base = None\n gated_tiled_copy_t2r = None\n gated_tTR_identity_base = None\n gated_tTR_rAcc = None\n if cutlass.const_expr(self.gated):\n gated_epi_tile = (\n self.cta_tile_shape_mnk[0],\n self.epi_tile_n,\n )\n gated_copy_atom_t2r = sm100_utils.get_tmem_load_op(\n self.cta_tile_shape_mnk,\n self.c_layout,\n self.c_dtype,\n self.acc_dtype,\n gated_epi_tile,\n self.use_2cta_instrs,\n )\n gated_tAcc_epi = cute.flat_divide(\n tCtAcc_base[((None, None), 0, 0, None)],\n gated_epi_tile,\n )\n gated_tiled_copy_t2r = tcgen05.make_tmem_copy(\n gated_copy_atom_t2r,\n gated_tAcc_epi[(None, None, 0, 0, 0)],\n )\n gated_thr_copy_t2r = gated_tiled_copy_t2r.get_slice(epi_tidx)\n gated_tTR_tAcc_base = gated_thr_copy_t2r.partition_S(gated_tAcc_epi)\n gated_identity = cute.make_identity_tensor(self.cta_tile_shape_mnk[:2])\n gated_identity_epi = cute.flat_divide(gated_identity, gated_epi_tile)\n gated_tTR_identity_base = gated_thr_copy_t2r.partition_D(\n gated_identity_epi\n )\n gated_tTR_rAcc = cute.make_rmem_tensor(\n gated_tTR_identity_base[(None, None, None, 0, 0)].shape,\n self.acc_dtype,\n )\n tTR_rC = cute.make_rmem_tensor(tTR_rAcc.shape, self.c_dtype)\n tiled_copy_r2s, tRS_rC, tRS_sC = (\n mixed_input_utils.epilog_smem_copy_and_partition(\n self.c_layout,\n self.c_dtype,\n self.acc_dtype,\n tiled_copy_t2r,\n tTR_rC,\n epi_tidx,\n sC,\n )\n )\n (\n tma_atom_c,\n bSG_sC,\n bSG_gC_partitioned,\n simt_atom,\n tTR_gC_partitioned,\n ) = mixed_input_utils.epilog_gmem_copy_and_partition(\n self.c_dtype,\n epi_tidx,\n tma_atom_c,\n tiled_copy_t2r,\n tCgC,\n tCgC_simt,\n epi_tile,\n sC,\n )\n if cutlass.const_expr(self.gated):\n gC_epi = cute.local_tile(mC_mnl, epi_tile, (None, None, None))\n bSG_sC, bSG_gC_partitioned = cpasync.tma_partition(\n tma_atom_c,\n 0,\n cute.make_layout(1),\n cute.group_modes(sC, 0, 2),\n cute.group_modes(gC_epi, 0, 2),\n )\n\n # Predicates\n thr_mapping = cute.make_identity_tensor(\n (self.cta_tile_shape_mnk[0], self.cta_tile_shape_mnk[1])\n )\n thr_mapping_mn = cute.flat_divide(thr_mapping, epi_tile)\n thr_copy_t2r = tiled_copy_t2r.get_slice(epi_tidx)\n m_thr_offset = thr_copy_t2r.partition_D(thr_mapping_mn)\n m_thr_offset = cute.group_modes(m_thr_offset, 3, cute.rank(m_thr_offset))\n\n acc_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.num_acc_stage\n )\n\n c_producer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n 32 * len(self.epilog_warp_id),\n )\n c_pipeline = pipeline.PipelineTmaStore.create(\n num_stages=self.num_c_stage,\n producer_group=c_producer_group,\n )\n\n # Persistent tile scheduling loop\n tile_info_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.num_tile_info_stage\n )\n tile_info_pipeline.consumer_wait(tile_info_consumer_state)\n work_tile = mixed_input_utils.make_contiguous_group_work_tile_info(\n group_count, sTile_info[(None, tile_info_consumer_state.index)]\n )\n cute.arch.fence_proxy(\n \"async.shared\",\n space=\"cta\",\n )\n tile_info_pipeline.consumer_release(tile_info_consumer_state)\n tile_info_consumer_state.advance()\n num_prev_subtiles = cutlass.Int32(0)\n while work_tile.is_valid_tile:\n alpha_val = alpha[work_tile.group_idx]\n if cutlass.const_expr(self.gated):\n bSG_gC = bSG_gC_partitioned[(None, work_tile.cta_coord_m, None, 0)]\n else:\n bSG_gC = bSG_gC_partitioned[\n (\n None,\n None,\n None,\n work_tile.cta_coord_m // cute.size(tiled_mma.thr_id.shape),\n 0,\n 0,\n )\n ]\n tma_store_offset_coord = (\n (work_tile.coord_n, 0)\n if cutlass.const_expr(self.c_layout.is_n_major_c())\n else (0, work_tile.coord_n)\n )\n bSG_gC = cute.make_tensor(\n (\n tma_store_offset_coord[0] + bSG_gC.iterator[0],\n tma_store_offset_coord[1] + bSG_gC.iterator[1],\n ),\n bSG_gC.layout,\n )\n tTR_gC = tTR_gC_partitioned[\n (\n None,\n None,\n None,\n None,\n None,\n work_tile.cta_coord_m // cute.size(tiled_mma.thr_id.shape),\n 0,\n 0,\n )\n ]\n tTR_gC = cute.make_tensor(\n tTR_gC.iterator + (work_tile.coord_n * tensor_c.layout.stride[1]),\n tTR_gC.layout,\n )\n\n tTR_tAcc = tTR_tAcc_base[\n (None, None, None, None, None, acc_consumer_state.index)\n ]\n # Wait for accumulator buffer full\n acc_pipeline.consumer_wait(acc_consumer_state)\n if cutlass.const_expr(not self.gated):\n bSG_gC = cute.group_modes(bSG_gC, 1, cute.rank(bSG_gC))\n\n if cutlass.const_expr(self.gated):\n gated_tTR_tAcc = gated_tTR_tAcc_base[\n (None, None, None, None, None, acc_consumer_state.index)\n ]\n gated_subtile_cnt = cute.size(gated_tTR_tAcc.shape, mode=[4])\n gated_alpha_f32 = cutlass.Float32(alpha_val)\n swiglu_alpha = cutlass.Float32(self.swiglu_alpha)\n swiglu_beta = cutlass.Float32(self.swiglu_beta)\n swiglu_limit = cutlass.Float32(self.swiglu_limit)\n neg_swiglu_alpha_log2_e = -(\n swiglu_alpha * cutlass.Float32(1.4426950408889634)\n )\n for gated_subtile_idx in cutlass.range(gated_subtile_cnt):\n gated_tTR_tAcc_mn = gated_tTR_tAcc[\n (None, None, None, 0, gated_subtile_idx)\n ]\n cute.copy(\n gated_tiled_copy_t2r,\n gated_tTR_tAcc_mn,\n gated_tTR_rAcc,\n )\n if gated_subtile_idx == gated_subtile_cnt - 1:\n cute.arch.fence_view_async_tmem_load()\n with cute.arch.elect_one():\n acc_pipeline.consumer_release(acc_consumer_state)\n acc_consumer_state.advance()\n num_prev_subtiles += 1\n c_buffer = num_prev_subtiles % self.num_c_stage\n gated_identity_mn = gated_tTR_identity_base[\n (None, None, None, 0, gated_subtile_idx)\n ]\n up = cute.coalesce(\n cute.flatten(gated_tTR_rAcc[(None, 0, None)])\n ).load()\n gate = cute.coalesce(\n cute.flatten(gated_tTR_rAcc[(None, 1, None)])\n ).load()\n up_coords = cute.coalesce(\n cute.flatten(gated_identity_mn[(None, 0, None)])\n )\n up_size = cute.size(gated_tTR_rAcc[(None, 0, None)])\n for i in cutlass.range_constexpr(0, up_size, 2):\n up_pair = cute.arch.mul_packed_f32x2(\n (up[i], up[i + 1]),\n (gated_alpha_f32, gated_alpha_f32),\n )\n gate_pair = cute.arch.mul_packed_f32x2(\n (gate[i], gate[i + 1]),\n (gated_alpha_f32, gated_alpha_f32),\n )\n if cutlass.const_expr(\n self.activation_type == ActivationType.Swiglu.value\n and self.situ_beta is not None\n ):\n # Keep the Python float so situ_f32 can fold\n # 1 / beta at trace time instead of emitting a\n # per-element div.rn.f32.\n situ_beta = self.situ_beta\n situ_gate_pair = (\n situ_f32(gate_pair[0], situ_beta, fastmath=True),\n situ_f32(gate_pair[1], situ_beta, fastmath=True),\n )\n if cutlass.const_expr(\n self.situ_linear_beta is not None\n ):\n linear_beta = cutlass.Float32(self.situ_linear_beta)\n inv_linear_beta = cutlass.Float32(\n f32_reciprocal(self.situ_linear_beta)\n )\n up_pair = (\n linear_beta\n * tanh_f32(\n up_pair[0] * inv_linear_beta, fastmath=True\n ),\n linear_beta\n * tanh_f32(\n up_pair[1] * inv_linear_beta, fastmath=True\n ),\n )\n result = cute.arch.mul_packed_f32x2(\n up_pair, situ_gate_pair\n )\n elif cutlass.const_expr(\n self.activation_type == ActivationType.GegluTanh.value\n ):\n result = cute.arch.mul_packed_f32x2(\n up_pair,\n (\n gelu_tanh_f32(gate_pair[0], fastmath=True),\n gelu_tanh_f32(gate_pair[1], fastmath=True),\n ),\n )\n elif cutlass.const_expr(\n self.activation_type == ActivationType.Swiglu.value\n ):\n if cutlass.const_expr(self.parameterized_swiglu):\n gate_pair = (\n fmin(gate_pair[0], swiglu_limit, nan=True),\n fmin(gate_pair[1], swiglu_limit, nan=True),\n )\n up_pair = (\n -fmin(\n -fmin(up_pair[0], swiglu_limit, nan=True),\n swiglu_limit,\n nan=True,\n ),\n -fmin(\n -fmin(up_pair[1], swiglu_limit, nan=True),\n swiglu_limit,\n nan=True,\n ),\n )\n gate_log2e = cute.arch.mul_packed_f32x2(\n gate_pair,\n (\n neg_swiglu_alpha_log2_e,\n neg_swiglu_alpha_log2_e,\n ),\n )\n sigmoid = cute.arch.add_packed_f32x2(\n (\n cute.math.exp2(gate_log2e[0], fastmath=True),\n cute.math.exp2(gate_log2e[1], fastmath=True),\n ),\n (1.0, 1.0),\n )\n sigmoid = (\n cute.arch.rcp_approx(sigmoid[0]),\n cute.arch.rcp_approx(sigmoid[1]),\n )\n silu = cute.arch.mul_packed_f32x2(gate_pair, sigmoid)\n if cutlass.const_expr(self.parameterized_swiglu):\n up_pair = cute.arch.add_packed_f32x2(\n up_pair, (swiglu_beta, swiglu_beta)\n )\n result = cute.arch.mul_packed_f32x2(up_pair, silu)\n\n coord_0 = up_coords[i]\n coord_1 = up_coords[i + 1]\n # Fold paired TMEM rows back into the reduced-M\n # output tile and keep the staged N coordinate local.\n output_m_0 = coord_0[0] // 32 * 16 + coord_0[0] % 16\n output_m_1 = coord_1[0] // 32 * 16 + coord_1[0] % 16\n output_n_0 = coord_0[1] % self.epi_tile_n\n output_n_1 = coord_1[1] % self.epi_tile_n\n sC[(output_m_0, output_n_0, c_buffer)] = self.c_dtype(\n result[0]\n )\n sC[(output_m_1, output_n_1, c_buffer)] = self.c_dtype(\n result[1]\n )\n\n cute.arch.fence_proxy(\"async.shared\", space=\"cta\")\n self.epilog_sync_barrier.arrive_and_wait()\n if warp_idx == self.epilog_warp_id[0]:\n cute.copy(\n tma_atom_c,\n bSG_sC[(None, c_buffer)],\n bSG_gC[\n (\n None,\n work_tile.coord_n // self.epi_tile_n\n + gated_subtile_idx,\n )\n ],\n )\n c_pipeline.producer_commit()\n c_pipeline.producer_acquire()\n self.epilog_sync_barrier.arrive_and_wait()\n\n tTR_tAcc = cute.group_modes(tTR_tAcc, 3, cute.rank(tTR_tAcc))\n tTR_gC = cute.group_modes(tTR_gC, 3, cute.rank(tTR_gC))\n tma_distance_to_boundary = work_tile.distance_to_boundary\n\n # Store accumulator to global memory in subtiles\n subtile_cnt = (\n 0\n if cutlass.const_expr(self.gated)\n else cute.size(tTR_tAcc.shape, mode=[3])\n )\n for subtile_idx in cutlass.range(subtile_cnt):\n # Load accumulator from tensor memory buffer to register\n tTR_tAcc_mn = tTR_tAcc[(None, None, None, subtile_idx)]\n cute.copy(tiled_copy_t2r, tTR_tAcc_mn, tTR_rAcc)\n if subtile_idx == subtile_cnt - 1:\n cute.arch.fence_view_async_tmem_load()\n with cute.arch.elect_one():\n acc_pipeline.consumer_release(acc_consumer_state)\n acc_consumer_state.advance()\n\n if cutlass.const_expr(self.fuse_activation):\n alpha_f32 = cutlass.Float32(alpha_val)\n acc_up = tTR_rAcc.load()\n for i in cutlass.range_constexpr(0, cute.size(tTR_rAcc), 2):\n value = cute.arch.mul_packed_f32x2(\n (acc_up[i], acc_up[i + 1]),\n (alpha_f32, alpha_f32),\n )\n relu = (\n cute.arch.fmax(value[0], cutlass.Float32(0.0)),\n cute.arch.fmax(value[1], cutlass.Float32(0.0)),\n )\n tTR_rAcc[i], tTR_rAcc[i + 1] = cute.arch.mul_packed_f32x2(\n relu, relu\n )\n if cutlass.const_expr(self.use_fused_finalize):\n finalize_thr_slice = m_thr_offset[\n (None, None, None, subtile_idx)\n ]\n top_k = token_final_scales.shape[1]\n finalize_scale_route = epi_tidx\n finalize_scale_route_in_tile = (\n subtile_idx * self.epi_tile_n + finalize_scale_route\n )\n if finalize_scale_route < self.epi_tile_n:\n finalize_scale_permuted_row = (\n work_tile.coord_n + finalize_scale_route_in_tile\n )\n finalize_scale_expanded_idx = permuted_idx_to_expanded_idx[\n finalize_scale_permuted_row\n ]\n finalize_scale_safe_idx = cutlass.max(\n finalize_scale_expanded_idx, cutlass.Int32(0)\n )\n finalize_scale_token_idx = finalize_scale_safe_idx // top_k\n finalize_scale_topk_idx = finalize_scale_safe_idx % top_k\n finalize_scale_is_valid = cutlass.Int32(\n finalize_scale_route_in_tile\n < work_tile.distance_to_boundary\n )\n finalize_token_scale = token_final_scales[\n (\n finalize_scale_token_idx * finalize_scale_is_valid,\n finalize_scale_topk_idx,\n )\n ]\n sFinalizeScale[finalize_scale_route] = (\n cutlass.Float32(alpha_val)\n * cutlass.Float32(finalize_token_scale)\n * cutlass.Float32(finalize_scale_is_valid)\n )\n\n cute.arch.fence_proxy(\"async.shared\", space=\"cta\")\n self.epilog_sync_barrier.arrive_and_wait()\n for i in cutlass.range(cute.size(tTR_rC), unroll_full=True):\n finalize_route = finalize_thr_slice[(i)][1]\n finalize_value = sFinalizeScale[\n finalize_route % self.epi_tile_n\n ] * cutlass.Float32(tTR_rAcc[i])\n sFinalize[\n (\n finalize_route % self.epi_tile_n,\n finalize_thr_slice[(i)][0],\n )\n ] = self.c_dtype(finalize_value)\n\n cute.arch.fence_proxy(\"async.shared\", space=\"cta\")\n self.epilog_sync_barrier.arrive_and_wait()\n\n reduce_route = epi_tidx\n reduce_route_in_tile = (\n subtile_idx * self.epi_tile_n + reduce_route\n )\n if (\n reduce_route < self.epi_tile_n\n and reduce_route_in_tile < work_tile.distance_to_boundary\n ):\n reduce_permuted_row = (\n work_tile.coord_n + reduce_route_in_tile\n )\n reduce_expanded_idx = permuted_idx_to_expanded_idx[\n reduce_permuted_row\n ]\n reduce_token_idx = reduce_expanded_idx // top_k\n hidden_base = (\n work_tile.cta_coord_m * self.cta_tile_shape_mnk[0]\n )\n valid_elements = (\n cutlass.Int64(final_output.shape[0]) - hidden_base\n )\n if valid_elements > 0:\n scatter_out = cute.domain_offset(\n (hidden_base, reduce_token_idx, 0), final_output\n )\n copy_elements = cutlass.Int32(\n cutlass.min(\n cutlass.Int64(self.cta_tile_shape_mnk[0]),\n valid_elements,\n )\n )\n blk_reduce_bf16(\n scatter_out,\n sFinalize[(reduce_route, None)],\n copy_elements * (self.c_dtype.width // 8),\n )\n\n cute.arch.cp_async_bulk_commit_group()\n cute.arch.cp_async_bulk_wait_group(0, read=True)\n self.epilog_sync_barrier.arrive_and_wait()\n elif tma_distance_to_boundary >= self.cta_tile_shape_mnk[1]:\n # Convert to C type\n acc_vec = tiled_copy_r2s.retile(tTR_rAcc).load()\n if cutlass.const_expr(not self.fuse_activation):\n acc_vec = cutlass.Float32(alpha_val) * acc_vec\n acc_vec = acc_vec.to(self.c_dtype)\n tRS_rC.store(acc_vec)\n num_prev_subtiles += 1\n c_buffer = num_prev_subtiles % self.num_c_stage\n # Store C to shared memory\n cute.copy(\n tiled_copy_r2s,\n tRS_rC,\n tRS_sC[(None, None, None, c_buffer)],\n )\n # Fence and barrier to make sure shared memory store is visible to TMA store\n cute.arch.fence_proxy(\n \"async.shared\",\n space=\"cta\",\n )\n self.epilog_sync_barrier.arrive_and_wait()\n # TMA store C to global memory\n if warp_idx == self.epilog_warp_id[0]:\n cute.copy(\n tma_atom_c,\n bSG_sC[(None, c_buffer)],\n bSG_gC[(None, subtile_idx)],\n )\n c_pipeline.producer_commit()\n c_pipeline.producer_acquire()\n self.epilog_sync_barrier.arrive_and_wait()\n else:\n # Convert to C type\n acc_vec = tTR_rAcc.load()\n if cutlass.const_expr(not self.fuse_activation):\n acc_vec = cutlass.Float32(alpha_val) * acc_vec\n acc_vec = acc_vec.to(self.c_dtype)\n tTR_rC.store(acc_vec)\n # Compute predicate for SIMT store\n tCpC = cute.make_rmem_tensor(\n cute.make_layout(tTR_rC.shape),\n cutlass.Boolean,\n )\n m_thr_slice = m_thr_offset[(None, None, None, subtile_idx)]\n for i in cutlass.range(cute.size(tCpC), unroll_full=True):\n tCpC[i] = (\n m_thr_slice[(i)][0]\n + work_tile.cta_coord_m * self.cta_tile_shape_mnk_c[0]\n < cute.size(tensor_c.shape[0])\n ) and (m_thr_slice[(i)][1] < work_tile.distance_to_boundary)\n # Store C to global memory\n cute.copy(\n simt_atom,\n cute.flatten(tTR_rC),\n cute.flatten(tTR_gC[(None, None, None, subtile_idx)]),\n pred=cute.flatten(tCpC),\n )\n # Advance to next tile\n tile_info_pipeline.consumer_wait(tile_info_consumer_state)\n work_tile = mixed_input_utils.make_contiguous_group_work_tile_info(\n group_count, sTile_info[(None, tile_info_consumer_state.index)]\n )\n cute.arch.fence_proxy(\n \"async.shared\",\n space=\"cta\",\n )\n tile_info_pipeline.consumer_release(tile_info_consumer_state)\n tile_info_consumer_state.advance()\n\n # Dealloc the tensor memory buffer\n tmem.relinquish_alloc_permit()\n self.epilog_sync_barrier.arrive_and_wait()\n tmem.free(tmem_ptr)\n if cutlass.const_expr(not self.use_fused_finalize):\n c_pipeline.producer_tail()\n\n if cutlass.const_expr(self.enable_pdl and not self.fuse_activation):\n if warp_idx == self.mma_warp_id:\n with cute.arch.elect_one():\n griddepcontrol_launch_dependents()\n\n @staticmethod\n def _compute_stages_and_tmem_cols(\n tiled_mma: cute.TiledMma,\n mma_tiler_mnk: tuple[int, int, int],\n cta_tile_shape_mnk: tuple[int, int, int],\n epi_tile: cute.Tile,\n a_dtype: type[cutlass.Numeric],\n b_dtype: type[cutlass.Numeric],\n c_dtype: type[cutlass.Numeric],\n c_layout: utils.LayoutEnum,\n transform_a_source: tcgen05.OperandSource,\n smem_buffer_align_bytes: int,\n use_fused_finalize: bool,\n use_clc_scheduler: bool,\n ) -> tuple[int, int, int, int, int, int, int]:\n \"\"\"Fit the load, transform, accumulator, and epilogue pipelines.\"\"\"\n # Compute tmem columns required for accumulator\n acc_shape = tiled_mma.partition_shape_C(mma_tiler_mnk[:2])\n tCtAcc_stage1 = tiled_mma.make_fragment_C(cute.append(acc_shape, 1))\n num_tmem_acc_col_per_stage = utils.get_num_tmem_alloc_cols(tCtAcc_stage1, True)\n # Heuristic to decide the number of stages for accumulator\n sm100_tmem_columns = cute.arch.get_max_tmem_alloc_cols(\"sm_100\")\n accumulator_stage_count = sm100_tmem_columns // num_tmem_acc_col_per_stage\n if transform_a_source == tcgen05.OperandSource.TMEM:\n if num_tmem_acc_col_per_stage < 256:\n accumulator_stage_count = 2\n else:\n accumulator_stage_count = 1\n # transformed A in 16bit, thus 1 tmem column could hold 2 elements\n num_elts_per_tmem_col = 32 // tiled_mma.op.a_dtype.width\n num_tmem_cols_a_per_stage = cute.round_up(\n (\n cta_tile_shape_mnk[2] // num_elts_per_tmem_col\n if transform_a_source == tcgen05.OperandSource.TMEM\n else 0\n ),\n 4,\n )\n\n bytes_per_pipeline_stage = 16\n # Limit how far CLC can claim work ahead of the consumer pipelines.\n num_tile_info_stage = 1 if use_clc_scheduler else 3\n tile_info_bytes = (\n cute.size_in_bytes(cute.Int32, cute.make_layout((4, num_tile_info_stage)))\n + bytes_per_pipeline_stage * num_tile_info_stage\n )\n\n c_stage_count = 1 if use_fused_finalize else 2\n c_smem_layout_staged_one = sm100_utils.make_smem_layout_epi(\n c_dtype,\n c_layout,\n epi_tile,\n 1,\n )\n c_bytes_per_stage = cute.size_in_bytes(c_dtype, c_smem_layout_staged_one)\n c_bytes = c_bytes_per_stage * c_stage_count\n finalize_metadata_bytes = (\n cute.size_in_bytes(\n cutlass.Float32,\n cute.make_layout((cute.size(epi_tile[1]),)),\n )\n if use_fused_finalize\n else 0\n )\n\n smem_capacity = utils.get_smem_capacity_in_bytes(\"sm_100\")\n a_scale_k_mode = max(cta_tile_shape_mnk[2] // _NVFP4_SCALE_GRANULARITY_K, 1)\n a_scale_m_mode = max(cta_tile_shape_mnk[0] // _NVFP4_SCALE_GRANULARITY_M, 1)\n a_scale_bytes_per_stage = cute.round_up(\n cute.size_in_bytes(\n tiled_mma.op.a_dtype,\n cute.make_layout((a_scale_m_mode, a_scale_k_mode)),\n ),\n smem_buffer_align_bytes,\n )\n carveout_smem_bytes = (\n bytes_per_pipeline_stage * accumulator_stage_count\n + c_bytes\n + finalize_metadata_bytes\n + tile_info_bytes\n )\n\n # Compute transform stages if A is in TMEM\n num_tmem_acc_cols = cute.round_up(\n accumulator_stage_count * num_tmem_acc_col_per_stage, 4\n )\n\n transform2mma_stage_count_a_source_tmem_potential = (\n (sm100_tmem_columns - num_tmem_acc_cols) // num_tmem_cols_a_per_stage\n if transform_a_source == tcgen05.OperandSource.TMEM\n else -1\n )\n if (\n transform_a_source == tcgen05.OperandSource.TMEM\n and transform2mma_stage_count_a_source_tmem_potential <= 0\n ):\n raise ValueError(\"Not enough TMEM capacity for selected tile size\")\n a_load_bytes_per_stage = cute.round_up(\n cute.size_in_bytes(\n a_dtype,\n cute.make_layout((cta_tile_shape_mnk[0], cta_tile_shape_mnk[2])),\n ),\n smem_buffer_align_bytes,\n )\n b_load_bytes_per_stage = cute.round_up(\n cute.size_in_bytes(\n b_dtype,\n cute.make_layout(\n (\n cta_tile_shape_mnk[1] // cute.size(tiled_mma.thr_id),\n cta_tile_shape_mnk[2],\n )\n ),\n ),\n smem_buffer_align_bytes,\n )\n ab_scale_load_bytes_per_stage = (\n a_load_bytes_per_stage\n + b_load_bytes_per_stage\n + a_scale_bytes_per_stage\n + 2 * bytes_per_pipeline_stage\n )\n a_transform_bytes_per_stage = (\n cute.round_up(\n cute.size_in_bytes(\n tiled_mma.op.a_dtype,\n cute.make_layout((cta_tile_shape_mnk[0], cta_tile_shape_mnk[2])),\n ),\n smem_buffer_align_bytes,\n )\n if transform_a_source == tcgen05.OperandSource.SMEM\n else 0\n )\n\n a_transform_bytes_per_stage = (\n a_transform_bytes_per_stage + bytes_per_pipeline_stage\n )\n transform2mma_stage_count_a_source_smem_potential = (\n smem_capacity - carveout_smem_bytes\n ) // (ab_scale_load_bytes_per_stage + a_transform_bytes_per_stage)\n transform2mma_stage_count = (\n min(\n transform2mma_stage_count_a_source_tmem_potential,\n transform2mma_stage_count_a_source_smem_potential,\n )\n if transform_a_source == tcgen05.OperandSource.TMEM\n else transform2mma_stage_count_a_source_smem_potential\n )\n load2transform_stage_count = (\n smem_capacity\n - carveout_smem_bytes\n - (transform2mma_stage_count * a_transform_bytes_per_stage)\n ) // ab_scale_load_bytes_per_stage\n if (\n load2transform_stage_count < 2\n or transform2mma_stage_count < 2\n or accumulator_stage_count < 1\n ):\n raise ValueError(\"Not enough SMEM or TMEM capacity for selected tile size\")\n num_tmem_a_cols = transform2mma_stage_count * num_tmem_cols_a_per_stage\n # Fused finalize reuses its single C stage as reduction scratch.\n if not use_fused_finalize:\n c_stage_count += (\n smem_capacity\n - carveout_smem_bytes\n - load2transform_stage_count * ab_scale_load_bytes_per_stage\n - transform2mma_stage_count * a_transform_bytes_per_stage\n ) // c_bytes_per_stage\n\n return (\n load2transform_stage_count,\n transform2mma_stage_count,\n accumulator_stage_count,\n c_stage_count,\n num_tile_info_stage,\n num_tmem_acc_cols,\n num_tmem_a_cols,\n )\n\n @staticmethod\n def _compute_grid(\n c: cute.Tensor,\n cta_tile_shape_mnk: tuple[int, int, int],\n cluster_shape_mn: tuple[int, int],\n max_active_clusters: cutlass.Constexpr,\n use_clc_scheduler: bool,\n raster_along_m: bool,\n ) -> tuple[\n Union[\n utils.ClcDynamicPersistentTileSchedulerParams,\n utils.PersistentTileSchedulerParams,\n ],\n tuple[int, int, int],\n ]:\n \"\"\"Build the persistent scheduler and launch grid.\"\"\"\n c_shape = cute.slice_(cta_tile_shape_mnk, (None, None, 0))\n gc = cute.zipped_divide(c, tiler=c_shape)\n num_ctas_mnl = gc[(0, (None, None, None))].shape\n cluster_shape_mnl = (*cluster_shape_mn, 1)\n\n if use_clc_scheduler:\n tile_sched_params = utils.ClcDynamicPersistentTileSchedulerParams(\n num_ctas_mnl, cluster_shape_mnl\n )\n grid = utils.ClcDynamicPersistentTileScheduler.get_grid_shape(\n tile_sched_params\n )\n else:\n tile_sched_params = utils.PersistentTileSchedulerParams(\n num_ctas_mnl,\n cluster_shape_mnl,\n raster_along_m=raster_along_m,\n )\n grid = (cluster_shape_mn[0], cluster_shape_mn[1], max_active_clusters)\n\n return tile_sched_params, grid\n\n @staticmethod\n def can_implement(\n mnkl: tuple[int, int, int, int],\n a_dtype: type[cutlass.Numeric],\n b_dtype: type[cutlass.Numeric],\n c_dtype: type[cutlass.Numeric],\n a_major: str,\n b_major: str,\n c_major: str,\n mma_tiler: tuple[int, int, int],\n cluster_shape_mn: tuple[int, int],\n use_2cta_instrs: bool,\n ) -> bool:\n \"\"\"Return whether the requested layout and tile shape are supported.\"\"\"\n m, n, k, _ = mnkl\n\n if not mixed_input_utils.is_valid_mma_tiler_and_cluster_shape(\n mma_tiler, cluster_shape_mn, use_2cta_instrs\n ):\n return False\n # Unlike the generic mixed-input kernel, W4A16 consumes multiple\n # 16-value NVFP4 scale blocks within each MMA K tile.\n if (\n k % _NVFP4_SCALE_GRANULARITY_K != 0\n or mma_tiler[2] % _NVFP4_SCALE_GRANULARITY_K != 0\n ):\n return False\n if not mixed_input_utils.is_valid_tensor_alignment(\n m,\n n,\n k,\n a_dtype,\n b_dtype,\n c_dtype,\n b_dtype,\n a_major,\n b_major,\n c_major,\n mma_tiler,\n use_2cta_instrs,\n cluster_shape_mn,\n _NVFP4_SCALE_GRANULARITY_M,\n _NVFP4_SCALE_GRANULARITY_K,\n ):\n return False\n return True\n"},"diff":{"kind":"string","value":"--- flashinfer/fused_moe/cute_dsl/blackwell/moe_w4a16_kernel.py\n+++ flashinfer/fused_moe/cute_dsl/blackwell/moe_w4a16_kernel.py\n@@ -59,6 +59,7 @@\n from .moe_w4a16_utils import decode_nvfp4_fragment_to_bf16\n from .utils import (\n blk_reduce_bf16,\n+ f32_reciprocal,\n fmin,\n gelu_tanh_f32,\n griddepcontrol_launch_dependents,\n@@ -1987,7 +1988,10 @@\n self.activation_type == ActivationType.Swiglu.value\n and self.situ_beta is not None\n ):\n- situ_beta = cutlass.Float32(self.situ_beta)\n+ # Keep the Python float so situ_f32 can fold\n+ # 1 / beta at trace time instead of emitting a\n+ # per-element div.rn.f32.\n+ situ_beta = self.situ_beta\n situ_gate_pair = (\n situ_f32(gate_pair[0], situ_beta, fastmath=True),\n situ_f32(gate_pair[1], situ_beta, fastmath=True),\n@@ -1996,14 +2000,17 @@\n self.situ_linear_beta is not None\n ):\n linear_beta = cutlass.Float32(self.situ_linear_beta)\n+ inv_linear_beta = cutlass.Float32(\n+ f32_reciprocal(self.situ_linear_beta)\n+ )\n up_pair = (\n linear_beta\n * tanh_f32(\n- up_pair[0] / linear_beta, fastmath=True\n+ up_pair[0] * inv_linear_beta, fastmath=True\n ),\n linear_beta\n * tanh_f32(\n- up_pair[1] / linear_beta, fastmath=True\n+ up_pair[1] * inv_linear_beta, fastmath=True\n ),\n )\n result = cute.arch.mul_packed_f32x2("},"lines_added":{"kind":"number","value":10,"string":"10"},"lines_removed":{"kind":"number","value":3,"string":"3"},"files_in_commit":{"kind":"number","value":1,"string":"1"},"models_mentioned":{"kind":"list like","value":["kimi"],"string":"[\n \"kimi\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["B200","B300","BLACKWELL","SM103"],"string":"[\n \"B200\",\n \"B300\",\n \"BLACKWELL\",\n \"SM103\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":["8 x","1.0x","1.0064x","1.0067x","1.0099x","1.0018x","1.0421x","1.0914x","1.0644x","1.0421x"],"string":"[\n \"8 x\",\n \"1.0x\",\n \"1.0064x\",\n \"1.0067x\",\n \"1.0099x\",\n \"1.0018x\",\n \"1.0421x\",\n \"1.0914x\",\n \"1.0644x\",\n \"1.0421x\"\n]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cute_dsl kernel file from flashinfer (flashinfer/fused_moe/cute_dsl/blackwell/moe_w4a16_kernel.py).\n\nGoal: perf(moe): fold W4A16 SiTU reciprocals\nTarget hardware: B200, B300, BLACKWELL, SM103\nTarget models: kimi\n\nCurrent file:\n```python\n# Copyright (c) 2025 - 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.\n# SPDX-License-Identifier: BSD-3-Clause\n\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions are met:\n\n# 1. Redistributions of source code must retain the above copyright notice, this\n# list of conditions and the following disclaimer.\n\n# 2. Redistributions in binary form must reproduce the above copyright notice,\n# this list of conditions and the following disclaimer in the documentation\n# and/or other materials provided with the distribution.\n\n# 3. Neither the name of the copyright holder nor the names of its\n# contributors may be used to endorse or promote products derived from\n# this software without specific prior written permission.\n\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n\"\"\"SM100 grouped GEMM for NVFP4 expert weights and BF16 activations.\n\nEach routed-row tile selects one expert through FlashInfer's MoE sort metadata.\nThe kernel decodes each 16-value E2M1 weight block and its E4M3 scale to BF16,\nthen executes BF16 tensor-core MMA with FP32 accumulation.\n\"\"\"\n\nfrom math import ceil, log2\nfrom typing import Optional, Union\n\nimport cuda.bindings.driver as cuda\nimport cutlass\nimport cutlass.cute as cute\nimport cutlass.pipeline as pipeline\nfrom cutlass.pipeline import pipeline_init_arrive, pipeline_init_wait\nimport cutlass.utils as utils\nimport cutlass.utils.blackwell_helpers as sm100_utils\nimport cutlass.utils.blockscaled_layout as blockscaled_utils\nimport cutlass.utils.mixed_input_helpers as mixed_input_utils\nfrom cutlass.utils.mixed_input_helpers import TransformMode\nfrom cutlass.cute.nvgpu import cpasync, tcgen05\n\nfrom flashinfer.tllm_enums import (\n ActivationType,\n DEFAULT_SWIGLU_ALPHA,\n DEFAULT_SWIGLU_BETA,\n DEFAULT_SWIGLU_LIMIT,\n)\n\nfrom ..moe_utils import validate_cute_dsl_moe_situ_config\nfrom .moe_w4a16_utils import decode_nvfp4_fragment_to_bf16\nfrom .utils import (\n blk_reduce_bf16,\n fmin,\n gelu_tanh_f32,\n griddepcontrol_launch_dependents,\n griddepcontrol_wait,\n situ_f32,\n tanh_f32,\n)\n\n\n_NVFP4_SCALE_GRANULARITY_M = 1\n_NVFP4_SCALE_GRANULARITY_K = 16\n_TMA_CACHE_HINT_EVICT_FIRST = 0x12F0000000000000\n_TMA_CACHE_HINT_EVICT_LAST = 0x14F0000000000000\n\n\nclass Sm100W4A16GroupedGemmKernel:\n \"\"\"Warp-specialized grouped GEMM for the W4A16 MoE pipeline.\"\"\"\n\n def __init__(\n self,\n acc_dtype: type[cutlass.Numeric],\n use_2cta_instrs: bool,\n mma_tiler_mnk: tuple[int, int, int],\n cluster_shape_mn: tuple[int, int],\n group_count: int,\n activation_type: Optional[int],\n swiglu_alpha: float,\n swiglu_beta: float,\n swiglu_limit: float,\n situ_beta: Optional[float],\n situ_linear_beta: Optional[float],\n use_fused_finalize: bool,\n enable_pdl: bool,\n use_clc_scheduler: bool,\n raster_along_m: bool,\n transform_fragment_size: int,\n ):\n \"\"\"Initialize the W4A16 grouped GEMM configuration.\"\"\"\n self.group_count = group_count\n self.acc_dtype = acc_dtype\n self.use_2cta_instrs = use_2cta_instrs\n self.cluster_shape_mn = cluster_shape_mn\n self.mma_tiler = mma_tiler_mnk\n if activation_type not in (\n None,\n ActivationType.Swiglu.value,\n ActivationType.GegluTanh.value,\n ActivationType.Relu2.value,\n ):\n raise ValueError(\n f\"unsupported W4A16 epilogue activation: {activation_type}\"\n )\n self.fuse_activation = activation_type is not None\n self.use_clc_scheduler = use_clc_scheduler\n self.raster_along_m = raster_along_m\n self.transform_fragment_size = transform_fragment_size\n if activation_type is None:\n if situ_beta is not None or situ_linear_beta is not None:\n raise ValueError(\"SiTU parameters require an activation\")\n else:\n validate_cute_dsl_moe_situ_config(\n ActivationType(activation_type), situ_beta, situ_linear_beta\n )\n self.activation_type = activation_type\n self.gated = activation_type in (\n ActivationType.Swiglu.value,\n ActivationType.GegluTanh.value,\n )\n self.swiglu_alpha = swiglu_alpha\n self.swiglu_beta = swiglu_beta\n self.swiglu_limit = swiglu_limit\n self.situ_beta = situ_beta\n self.situ_linear_beta = situ_linear_beta\n self.parameterized_swiglu = (\n swiglu_alpha != DEFAULT_SWIGLU_ALPHA\n or swiglu_beta != DEFAULT_SWIGLU_BETA\n or swiglu_limit != DEFAULT_SWIGLU_LIMIT\n )\n self.output_m_factor = 2 if self.gated else 1\n if self.gated and use_fused_finalize:\n raise ValueError(\n \"W4A16 fused finalize is only implemented for the non-gated epilogue\"\n )\n self.use_fused_finalize = use_fused_finalize\n self.enable_pdl = enable_pdl\n self.cta_group = (\n tcgen05.CtaGroup.TWO if self.use_2cta_instrs else tcgen05.CtaGroup.ONE\n )\n self.epilog_warp_id = (0, 1, 2, 3)\n self.mma_warp_id = 4\n self.schedule_warp_id = 5\n self.weight_tma_warp_id = 6\n self.activation_tma_warp_id = 7\n self.num_transform_warpgroups = 2\n self.transform_warp_id = tuple(range(8, 8 + 4 * self.num_transform_warpgroups))\n self.num_transform_warps = len(self.transform_warp_id)\n # Keep the role-control warpgroup on one absolute register target.\n # Transform warps retain the 128-register launch default.\n self.num_regs_epilogue_warps = 176\n self.num_regs_generic_warps = 80\n self.threads_per_cta = 32 * (\n max(\n (\n self.mma_warp_id,\n self.schedule_warp_id,\n self.weight_tma_warp_id,\n self.activation_tma_warp_id,\n *self.epilog_warp_id,\n *self.transform_warp_id,\n )\n )\n + 1\n )\n\n self.epilog_sync_barrier = pipeline.NamedBarrier(\n 1, 32 * len(self.epilog_warp_id)\n )\n self.tmem_ptr_sync_barrier = pipeline.NamedBarrier(2, self.threads_per_cta)\n self.sched_sync_barrier = pipeline.NamedBarrier(5, 32)\n\n self.smem_buffer_align_bytes = 1024\n\n def _setup_attributes(self):\n \"\"\"Derive static MMA, pipeline, and storage layouts from operand types.\"\"\"\n self.transform_a_source = mixed_input_utils.get_transform_a_source(\n self.a_major_mode\n )\n tiled_mma = sm100_utils.make_trivial_tiled_mma(\n self.mma_dtype,\n self.a_major_mode,\n self.b_major_mode,\n self.acc_dtype,\n self.cta_group,\n self.mma_tiler[:2],\n self.transform_a_source,\n )\n self.cta_tile_shape_mnk = (\n self.mma_tiler[0] // cute.size(tiled_mma.thr_id.shape),\n self.mma_tiler[1],\n self.mma_tiler[2],\n )\n self.mma_tiler_c = (\n self.mma_tiler[0] // self.output_m_factor,\n self.mma_tiler[1],\n self.mma_tiler[2],\n )\n self.cta_tile_shape_mnk_c = (\n self.cta_tile_shape_mnk[0] // self.output_m_factor,\n self.cta_tile_shape_mnk[1],\n self.cta_tile_shape_mnk[2],\n )\n self.cluster_layout_vmnk = cute.tiled_divide(\n cute.make_layout((*self.cluster_shape_mn, 1)),\n (tiled_mma.thr_id.shape,),\n )\n self.num_mcast_ctas_a = cute.size(self.cluster_layout_vmnk.shape[2])\n self.num_mcast_ctas_b = cute.size(self.cluster_layout_vmnk.shape[1])\n self.is_a_mcast = self.num_mcast_ctas_a > 1\n self.is_b_mcast = self.num_mcast_ctas_b > 1\n\n default_epi_tile = sm100_utils.compute_epilogue_tile_shape(\n self.cta_tile_shape_mnk,\n self.use_2cta_instrs,\n self.c_layout,\n self.c_dtype,\n )\n self.epi_tile = (\n (self.cta_tile_shape_mnk_c[0], default_epi_tile[1])\n if self.gated\n else default_epi_tile\n )\n self.epi_tile_n = cute.size(self.epi_tile[1])\n\n (\n self.num_load2trans_stage,\n self.num_trans2mma_stage,\n self.num_acc_stage,\n self.num_c_stage,\n self.num_tile_info_stage,\n self.num_acc_tmem_cols,\n self.num_a_tmem_cols,\n ) = self._compute_stages_and_tmem_cols(\n tiled_mma,\n self.mma_tiler,\n self.cta_tile_shape_mnk,\n self.epi_tile,\n self.a_dtype,\n self.b_dtype,\n self.c_dtype,\n self.c_layout,\n self.transform_a_source,\n self.smem_buffer_align_bytes,\n self.use_fused_finalize,\n self.use_clc_scheduler,\n )\n\n # TMEM allocation requires power-of-two column alignment.\n self.num_tmem_alloc_cols = cute.round_up(\n self.num_acc_tmem_cols + self.num_a_tmem_cols,\n cute.arch.get_min_tmem_alloc_cols(\"sm_100\"),\n )\n self.num_tmem_alloc_cols = 2 ** (ceil(log2(self.num_tmem_alloc_cols)))\n self.c_smem_layout_staged = sm100_utils.make_smem_layout_epi(\n self.c_dtype,\n self.c_layout,\n self.epi_tile,\n self.num_c_stage,\n )\n (\n self.smem_layout_a,\n self.smem_layout_a_transform,\n self.smem_layout_b,\n ) = mixed_input_utils.compute_smem_layout(\n tiled_mma,\n self.mma_tiler,\n self.a_dtype,\n self.b_dtype,\n self.num_load2trans_stage,\n self.num_trans2mma_stage,\n )\n scale_tile_shape = (\n self.cta_tile_shape_mnk[0],\n self.mma_tiler[2],\n )\n # The transform and TMA partitions use different logical views of the\n # same block-scaled shared-memory storage.\n scale_smem_layout = blockscaled_utils.make_smem_layout_sf(\n scale_tile_shape,\n _NVFP4_SCALE_GRANULARITY_K,\n self.num_load2trans_stage,\n )\n scale_smem_layout_per_stage = cute.slice_(scale_smem_layout, (None, None, 0))\n trivial_swizzle = cute.make_swizzle(0, 4, 3)\n self.smem_layout_scale_per_stage = cute.make_composed_layout(\n trivial_swizzle, 0, scale_smem_layout_per_stage\n )\n self.smem_layout_scale = cute.make_composed_layout(\n trivial_swizzle, 0, scale_smem_layout\n )\n self.smem_layout_scale_tma = blockscaled_utils.make_smem_layout_sfa(\n tiled_mma,\n self.mma_tiler,\n _NVFP4_SCALE_GRANULARITY_K,\n self.num_load2trans_stage,\n )\n\n @cute.jit\n def _setup_transform_partitions(\n self,\n tiled_mma: cute.TiledMma,\n copy_atom_a_input: cute.CopyAtom,\n copy_atom_a_transform: cute.CopyAtom,\n sA_transform_input: cute.Tensor,\n a_smem_layout_transform: cute.ComposedLayout,\n sA_transform: cute.Tensor,\n tCsS: cute.Tensor,\n accumulators: cute.Tensor,\n transform_tidx: cutlass.Int32,\n transform_group_idx: cutlass.Int32,\n ):\n if cutlass.const_expr(self.transform_a_source == tcgen05.OperandSource.TMEM):\n tmem_ptr_transform = cute.recast_ptr(\n accumulators.iterator + self.num_acc_tmem_cols,\n dtype=self.mma_dtype,\n )\n transform_destination = cute.make_tensor(\n tmem_ptr_transform,\n tiled_mma.make_fragment_A(a_smem_layout_transform.outer).layout,\n )\n else:\n transform_destination = sA_transform\n\n src_copy_a, dst_copy_a, tAsA_input, tAsA_transform = (\n mixed_input_utils.transform_partition(\n self.transform_a_source,\n TransformMode.ConvertScale,\n copy_atom_a_input,\n copy_atom_a_transform,\n sA_transform_input,\n transform_destination,\n transform_tidx,\n )\n )\n num_transform_blocks = cute.size(tAsA_input, mode=[3])\n assert num_transform_blocks % self.num_transform_warpgroups == 0, (\n \"A blocks must divide evenly across transform warpgroups\"\n )\n blocks_per_transform_group = (\n num_transform_blocks // self.num_transform_warpgroups\n )\n transform_group_tiler = (\n None,\n None,\n None,\n blocks_per_transform_group,\n None,\n )\n transform_group_coord = (\n None,\n None,\n None,\n (None, transform_group_idx),\n None,\n )\n tAsA_input = cute.logical_divide(tAsA_input, transform_group_tiler)[\n transform_group_coord\n ]\n tAsA_transform = cute.logical_divide(tAsA_transform, transform_group_tiler)[\n transform_group_coord\n ]\n\n a_stage_coord = (None,) * (cute.rank(tAsA_input) - 1) + (0,)\n tArA = cute.make_rmem_tensor(\n tAsA_input[a_stage_coord].shape,\n tAsA_input.element_type,\n )\n tArA_transform = cute.make_rmem_tensor(\n tAsA_input[a_stage_coord].shape,\n self.mma_dtype,\n )\n\n smem_thr_copy_S = src_copy_a.get_slice(transform_tidx)\n tSsS_trans = smem_thr_copy_S.partition_S(tCsS)\n tSsS_trans = cute.logical_divide(tSsS_trans, transform_group_tiler)[\n transform_group_coord\n ]\n scale_stage_coord = (None,) * (cute.rank(tSsS_trans) - 1) + (0,)\n tSsS_layout_per_stage = tSsS_trans[scale_stage_coord].layout\n tSrS_copy = cute.make_rmem_tensor(\n cute.filter_zeros(tSsS_layout_per_stage).shape,\n self.a_scale_dtype,\n )\n tSrS = cute.make_tensor(\n tSrS_copy.iterator,\n cute.make_layout(\n tSsS_layout_per_stage.shape,\n stride=tSrS_copy.layout.stride,\n ),\n )\n assert cute.size(tSrS, mode=[0]) == cute.size(tArA, mode=[0]), (\n \"tSrS and tArA have different leading dimension\"\n )\n assert cute.size(tSrS) == cute.size(tArA), \"tSrS and tArA have different shape\"\n\n transform_tiler_size = min(\n cute.size(cute.coalesce(tAsA_input.layout), mode=[0]),\n self.transform_fragment_size,\n )\n assert transform_tiler_size % _NVFP4_SCALE_GRANULARITY_K == 0, (\n \"transform fragment must cover whole NVFP4 scale blocks\"\n )\n transform_tiler = cute.make_layout(transform_tiler_size)\n tArA_load = cute.flat_divide(tArA, transform_tiler)\n tArA_load = cute.group_modes(tArA_load, 1, cute.rank(tArA_load))\n scale_tiler = cute.make_layout(\n transform_tiler_size // _NVFP4_SCALE_GRANULARITY_K\n )\n tSrS_load = cute.flat_divide(tSrS_copy, scale_tiler)\n tSrS_load = cute.group_modes(tSrS_load, 1, cute.rank(tSrS_load))\n tArA_transform_store = cute.flat_divide(tArA_transform, transform_tiler)\n tArA_transform_store = cute.group_modes(\n tArA_transform_store,\n 1,\n cute.rank(tArA_transform_store),\n )\n return (\n dst_copy_a,\n tAsA_input,\n tAsA_transform,\n tSsS_trans,\n tSrS_copy,\n tSrS_load,\n tArA_load,\n tArA_transform,\n tArA_transform_store,\n transform_tiler,\n )\n\n @cute.jit\n def _transform_tile(\n self,\n a_load2trans_pipeline: pipeline.PipelineTmaAsync,\n trans2mma_pipeline: pipeline.PipelineAsyncUmma,\n a_load2trans_consumer_state: pipeline.PipelineState,\n trans2mma_producer_state: pipeline.PipelineState,\n dst_copy_a: cute.CopyAtom,\n tAsA_input: cute.Tensor,\n tAsA_transform: cute.Tensor,\n tSsS_trans: cute.Tensor,\n tSrS_copy: cute.Tensor,\n tSrS_load: cute.Tensor,\n tArA_load: cute.Tensor,\n tArA_transform: cute.Tensor,\n tArA_transform_store: cute.Tensor,\n transform_tiler: cute.Layout,\n k_tile_cnt: cutlass.Int32,\n ) -> tuple[pipeline.PipelineState, pipeline.PipelineState]:\n a_load2trans_consumer_state.reset_count()\n peek_load2trans_full_status = cutlass.Boolean(1)\n if a_load2trans_consumer_state.count < k_tile_cnt:\n peek_load2trans_full_status = a_load2trans_pipeline.consumer_try_wait(\n a_load2trans_consumer_state\n )\n trans2mma_producer_state.reset_count()\n peek_trans2mma_empty_status = cutlass.Boolean(1)\n if trans2mma_producer_state.count < k_tile_cnt:\n peek_trans2mma_empty_status = trans2mma_pipeline.producer_try_acquire(\n trans2mma_producer_state\n )\n\n for _k_tile in cutlass.range(0, k_tile_cnt, 1, unroll=1):\n a_load2trans_pipeline.consumer_wait(\n a_load2trans_consumer_state,\n peek_load2trans_full_status,\n )\n a_stage_coord = (None,) * (cute.rank(tAsA_input) - 1) + (\n a_load2trans_consumer_state.index,\n )\n tAsA_input_slice = tAsA_input[a_stage_coord]\n tAsA_input_slice = cute.flat_divide(tAsA_input_slice, transform_tiler)\n tAsA_input_slice = cute.group_modes(\n tAsA_input_slice,\n 1,\n cute.rank(tAsA_input_slice),\n )\n trans2mma_pipeline.producer_acquire(\n trans2mma_producer_state,\n peek_trans2mma_empty_status,\n )\n scale_stage_coord = (None,) * (cute.rank(tSsS_trans) - 1) + (\n a_load2trans_consumer_state.index,\n )\n tSsS_slice = tSsS_trans[scale_stage_coord]\n tSsS_slice_filtered = cute.make_tensor(\n tSsS_slice.iterator,\n cute.filter_zeros(tSsS_slice.layout),\n )\n cute.autovec_copy(tSsS_slice_filtered, tSrS_copy)\n cur_a_load2trans_consumer_state = a_load2trans_consumer_state.clone()\n for idx in cutlass.range_constexpr(cute.size(tArA_load, mode=[1])):\n cute.autovec_copy(\n tAsA_input_slice[(None, idx)],\n tArA_load[(None, idx)],\n )\n if cutlass.const_expr(idx == cute.size(tArA_load, mode=[1]) - 1):\n a_load2trans_consumer_state.advance()\n if a_load2trans_consumer_state.count < k_tile_cnt:\n peek_load2trans_full_status = (\n a_load2trans_pipeline.consumer_try_wait(\n a_load2trans_consumer_state\n )\n )\n packed_fragment = cute.recast_tensor(\n tArA_load[(None, idx)], cutlass.Uint8\n ).load()\n scale_slice = tSrS_load[(None, idx)]\n scale_slice_compact = cute.make_tensor(\n scale_slice.iterator,\n cute.filter_zeros(scale_slice.layout),\n )\n scale_fragment = cute.recast_tensor(\n scale_slice_compact, cutlass.Uint8\n ).load()\n tensor_transformed = decode_nvfp4_fragment_to_bf16(\n packed_fragment,\n scale_fragment,\n )\n tArA_transform_store[(None, idx)].store(tensor_transformed)\n\n a_transform_stage_coord = (None,) * (cute.rank(tAsA_transform) - 1) + (\n trans2mma_producer_state.index,\n )\n mixed_input_utils.store_transformed_a(\n tArA_transform,\n tAsA_transform[a_transform_stage_coord],\n dst_copy_a,\n )\n if cutlass.const_expr(\n self.transform_a_source == tcgen05.OperandSource.TMEM\n ):\n cute.arch.fence_view_async_tmem_store()\n else:\n cute.arch.fence_proxy(\"async.shared\", space=\"cta\")\n a_load2trans_pipeline.consumer_release(cur_a_load2trans_consumer_state)\n trans2mma_pipeline.producer_commit(trans2mma_producer_state)\n trans2mma_producer_state.advance()\n if trans2mma_producer_state.count < k_tile_cnt:\n peek_trans2mma_empty_status = trans2mma_pipeline.producer_try_acquire(\n trans2mma_producer_state\n )\n\n return a_load2trans_consumer_state, trans2mma_producer_state\n\n @cute.jit\n def wrapper(\n self,\n weight_ptr: cute.Pointer,\n weight_sf_ptr: cute.Pointer,\n activation_ptr: cute.Pointer,\n tile_idx_to_expert_idx_ptr: cute.Pointer,\n tile_idx_to_mn_limit_ptr: cute.Pointer,\n num_non_exiting_tiles_ptr: cute.Pointer,\n alpha_ptr: cute.Pointer,\n output_ptr: cute.Pointer,\n permuted_idx_to_expanded_idx_ptr: Optional[cute.Pointer],\n token_final_scales_ptr: Optional[cute.Pointer],\n m: cutlass.Int64,\n n: cutlass.Int64,\n k: cutlass.Int64,\n num_tokens: cutlass.Int64,\n top_k: cutlass.Int64,\n max_active_clusters: cutlass.Constexpr,\n stream: cuda.CUstream,\n ):\n \"\"\"Build logical tensors over FlashInfer's packed NVFP4 storage.\"\"\"\n weights = cute.make_tensor(\n weight_ptr,\n cute.make_ordered_layout((m, k, self.group_count), order=(1, 0, 2)),\n )\n weight_sf = cute.make_tensor(\n weight_sf_ptr,\n blockscaled_utils.tile_atom_to_shape_SF(\n weights.shape, _NVFP4_SCALE_GRANULARITY_K\n ),\n )\n activations = cute.make_tensor(\n activation_ptr,\n cute.make_ordered_layout((n, k, 1), order=(1, 0, 2)),\n )\n output_m = m // self.output_m_factor\n output_layout = cute.make_ordered_layout((output_m, n, 1), order=(0, 1, 2))\n output = cute.make_tensor(output_ptr, output_layout)\n final_output = (\n cute.make_tensor(\n output_ptr,\n cute.make_ordered_layout((output_m, num_tokens, 1), order=(0, 1, 2)),\n )\n if cutlass.const_expr(self.use_fused_finalize)\n else output\n )\n num_route_tiles = n // self.mma_tiler[1]\n tile_idx_to_expert_idx = cute.make_tensor(\n tile_idx_to_expert_idx_ptr, cute.make_layout((num_route_tiles,))\n )\n tile_idx_to_mn_limit = cute.make_tensor(\n tile_idx_to_mn_limit_ptr, cute.make_layout((num_route_tiles,))\n )\n num_non_exiting_tiles = cute.make_tensor(\n num_non_exiting_tiles_ptr, cute.make_layout((1,))\n )\n alpha = cute.make_tensor(alpha_ptr, cute.make_layout((self.group_count,)))\n permuted_idx_to_expanded_idx = (\n cute.make_tensor(permuted_idx_to_expanded_idx_ptr, cute.make_layout((n,)))\n if cutlass.const_expr(self.use_fused_finalize)\n else None\n )\n token_final_scales = (\n cute.make_tensor(\n token_final_scales_ptr,\n cute.make_ordered_layout((num_tokens, top_k), order=(1, 0)),\n )\n if cutlass.const_expr(self.use_fused_finalize)\n else None\n )\n return self(\n weights,\n weight_sf,\n activations,\n tile_idx_to_expert_idx,\n tile_idx_to_mn_limit,\n num_non_exiting_tiles,\n alpha,\n output,\n final_output,\n permuted_idx_to_expanded_idx,\n token_final_scales,\n max_active_clusters,\n stream,\n )\n\n @cute.jit\n def __call__(\n self,\n a: cute.Tensor,\n a_scale: cute.Tensor,\n b: cute.Tensor,\n tile_idx_to_expert_idx: cute.Tensor,\n tile_idx_to_mn_limit: cute.Tensor,\n num_non_exiting_tiles: cute.Tensor,\n alpha: cute.Tensor,\n c: cute.Tensor,\n final_output: cute.Tensor,\n permuted_idx_to_expanded_idx: Optional[cute.Tensor],\n token_final_scales: Optional[cute.Tensor],\n max_active_clusters: cutlass.Constexpr,\n stream: cuda.CUstream,\n ):\n \"\"\"Configure and launch the grouped GEMM.\"\"\"\n self.a_dtype: type[cutlass.Numeric] = a.element_type\n self.a_scale_dtype: type[cutlass.Numeric] = a_scale.element_type\n self.b_dtype: type[cutlass.Numeric] = b.element_type\n self.c_dtype: type[cutlass.Numeric] = c.element_type\n self.mma_dtype = self.b_dtype\n\n self.a_major_mode = utils.LayoutEnum.from_tensor(a).mma_major_mode()\n self.b_major_mode = utils.LayoutEnum.from_tensor(b).mma_major_mode()\n self.c_layout = utils.LayoutEnum.from_tensor(c)\n\n if cutlass.const_expr(\n utils.LayoutEnum.from_tensor(a_scale).mma_major_mode()\n != cute.nvgpu.OperandMajorMode.K\n ):\n raise ValueError(\"scale_major_mode must be K-major\")\n\n self._setup_attributes()\n\n tiled_mma = sm100_utils.make_trivial_tiled_mma(\n self.mma_dtype,\n self.a_major_mode,\n self.b_major_mode,\n self.acc_dtype,\n self.cta_group,\n self.mma_tiler[:2],\n self.transform_a_source,\n )\n a_op = mixed_input_utils.get_tma_atom_kind(\n self.is_a_mcast, self.use_2cta_instrs, False\n )\n b_op = mixed_input_utils.get_tma_atom_kind(\n self.is_b_mcast, self.use_2cta_instrs, True\n )\n smem_layout_a_per_stage = cute.slice_(self.smem_layout_a, (None, None, None, 0))\n tma_atom_a, tma_tensor_a = cute.nvgpu.make_tiled_tma_atom_A(\n a_op,\n a,\n smem_layout_a_per_stage,\n self.mma_tiler,\n tiled_mma,\n self.cluster_layout_vmnk.shape,\n internal_type=(\n cutlass.TFloat32 if a.element_type is cutlass.Float32 else None\n ),\n )\n\n scale_smem_layout_for_tma = cute.slice_(\n self.smem_layout_scale_tma, (None, None, None, 0)\n )\n tma_atom_scale, tma_tensor_scale = cute.nvgpu.make_tiled_tma_atom_A(\n a_op,\n a_scale,\n scale_smem_layout_for_tma,\n self.mma_tiler,\n tiled_mma,\n self.cluster_layout_vmnk.shape,\n internal_type=cutlass.Int16,\n )\n\n smem_layout_b_per_stage = cute.slice_(self.smem_layout_b, (None, None, None, 0))\n tma_atom_b, tma_tensor_b = cute.nvgpu.make_tiled_tma_atom_B(\n b_op,\n b,\n smem_layout_b_per_stage,\n self.mma_tiler,\n tiled_mma,\n self.cluster_layout_vmnk.shape,\n internal_type=(\n cutlass.TFloat32 if b.element_type is cutlass.Float32 else None\n ),\n )\n\n a_copy_size = cute.size_in_bytes(self.a_dtype, smem_layout_a_per_stage)\n b_copy_size = cute.size_in_bytes(self.b_dtype, smem_layout_b_per_stage)\n a_scale_copy_size = cute.size_in_bytes(\n self.a_scale_dtype, self.smem_layout_scale_per_stage\n )\n\n self.num_tma_load_bytes_a_scale = a_copy_size + a_scale_copy_size\n self.num_tma_load_bytes_b = b_copy_size * cute.size(tiled_mma.thr_id.shape)\n self.tile_sched_params, grid = self._compute_grid(\n c,\n self.cta_tile_shape_mnk_c,\n self.cluster_shape_mn,\n max_active_clusters,\n self.use_clc_scheduler,\n self.raster_along_m,\n )\n\n epi_smem_layout = cute.slice_(self.c_smem_layout_staged, (None, None, 0))\n tma_atom_c, tma_tensor_c = cpasync.make_tiled_tma_atom(\n cpasync.CopyBulkTensorTileS2GOp(),\n c,\n epi_smem_layout,\n self.epi_tile,\n )\n\n @cute.struct\n class SharedStorage:\n # Routed-tile scheduling metadata.\n tile_info: cute.struct.MemRange[cutlass.Int32, 4 * self.num_tile_info_stage]\n a_load2trans_full_mbar_ptr: cute.struct.MemRange[\n cutlass.Int64, self.num_load2trans_stage\n ]\n a_load2trans_empty_mbar_ptr: cute.struct.MemRange[\n cutlass.Int64, self.num_load2trans_stage\n ]\n a_trans2mma_full_mbar_ptr: cute.struct.MemRange[\n cutlass.Int64, self.num_trans2mma_stage\n ]\n a_trans2mma_empty_mbar_ptr: cute.struct.MemRange[\n cutlass.Int64, self.num_trans2mma_stage\n ]\n b_load2mma_full_mbar_ptr: cute.struct.MemRange[\n cutlass.Int64, self.num_load2trans_stage\n ]\n b_load2mma_empty_mbar_ptr: cute.struct.MemRange[\n cutlass.Int64, self.num_load2trans_stage\n ]\n acc_full_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.num_acc_stage]\n acc_empty_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.num_acc_stage]\n tile_info_full_mbar_ptr: cute.struct.MemRange[\n cutlass.Int64, self.num_tile_info_stage\n ]\n tile_info_empty_mbar_ptr: cute.struct.MemRange[\n cutlass.Int64, self.num_tile_info_stage\n ]\n clc_mbar_ptr: cute.struct.MemRange[cutlass.Int64, 2]\n clc_response: cute.struct.Align[cute.struct.MemRange[cutlass.Int32, 4], 16]\n tmem_dealloc_mbar: cutlass.Int64\n tmem_holding_buf: cutlass.Int32\n\n self.shared_storage = SharedStorage\n\n self.kernel(\n tiled_mma,\n tma_atom_a,\n tma_tensor_a,\n tma_atom_scale,\n tma_tensor_scale,\n tma_atom_b,\n tma_tensor_b,\n tma_atom_c,\n tma_tensor_c,\n c,\n final_output,\n tile_idx_to_expert_idx,\n tile_idx_to_mn_limit,\n num_non_exiting_tiles,\n alpha,\n permuted_idx_to_expanded_idx,\n token_final_scales,\n self.group_count,\n self.cluster_layout_vmnk,\n self.smem_layout_a,\n self.smem_layout_scale,\n self.smem_layout_scale_tma,\n self.smem_layout_a_transform,\n self.smem_layout_b,\n self.c_smem_layout_staged,\n self.epi_tile,\n self.tile_sched_params,\n ).launch(\n grid=grid,\n block=[self.threads_per_cta, 1, 1],\n cluster=(*self.cluster_shape_mn, 1),\n min_blocks_per_mp=1,\n stream=stream,\n use_pdl=self.enable_pdl,\n )\n\n @cute.kernel\n def kernel(\n self,\n tiled_mma: cute.TiledMma,\n tma_atom_a: cute.CopyAtom,\n mA_mkl: cute.Tensor,\n tma_atom_s: cute.CopyAtom,\n mS_mkl: cute.Tensor,\n tma_atom_b: cute.CopyAtom,\n mB_nkl: cute.Tensor,\n tma_atom_c: cute.CopyAtom,\n mC_mnl: cute.Tensor,\n tensor_c: cute.Tensor,\n final_output: cute.Tensor,\n tile_idx_to_expert_idx: cute.Tensor,\n tile_idx_to_mn_limit: cute.Tensor,\n num_non_exiting_tiles: cute.Tensor,\n alpha: cute.Tensor,\n permuted_idx_to_expanded_idx: Optional[cute.Tensor],\n token_final_scales: Optional[cute.Tensor],\n group_count: cutlass.Constexpr[int],\n cluster_layout_vmnk: cute.Layout,\n a_smem_layout: cute.ComposedLayout,\n scale_smem_layout: cute.ComposedLayout,\n scale_tma_smem_layout: cute.Layout,\n a_smem_layout_transform: cute.ComposedLayout,\n b_smem_layout: cute.ComposedLayout,\n c_smem_layout_staged: cute.ComposedLayout,\n epi_tile: cute.Tile,\n tile_sched_params: Union[\n utils.ClcDynamicPersistentTileSchedulerParams,\n utils.PersistentTileSchedulerParams,\n ],\n ):\n \"\"\"Run the persistent W4A16 grouped GEMM.\"\"\"\n warp_idx = cute.arch.make_warp_uniform(cute.arch.warp_idx())\n tidx, _, _ = cute.arch.thread_idx()\n bidx, bidy, bidz = cute.arch.block_idx()\n # Prefetch TMA descriptors\n if warp_idx == self.epilog_warp_id[0]:\n cpasync.prefetch_descriptor(tma_atom_a)\n cpasync.prefetch_descriptor(tma_atom_b)\n cpasync.prefetch_descriptor(tma_atom_s)\n cpasync.prefetch_descriptor(tma_atom_c)\n\n use_2cta_instrs = cute.size(tiled_mma.thr_id.shape) == 2\n mma_tile_coord_v = bidx % cute.size(tiled_mma.thr_id.shape)\n is_leader_cta = mma_tile_coord_v == 0\n cta_rank_in_cluster = cute.arch.make_warp_uniform(\n cute.arch.block_idx_in_cluster()\n )\n is_first_cta_in_cluster = cta_rank_in_cluster == 0\n block_in_cluster_coord_vmnk = cluster_layout_vmnk.get_flat_coord(\n cta_rank_in_cluster\n )\n smem = utils.SmemAllocator()\n storage = smem.allocate(self.shared_storage)\n clc_response_ptr = storage.clc_response.data_ptr()\n\n # Initialize load2transform pipeline for the weight operand.\n transform_thread_idx = (\n tidx - 32 * self.transform_warp_id[0]\n if tidx >= 32 * self.transform_warp_id[0]\n else tidx\n )\n a_load2trans_pipeline = pipeline.PipelineTmaAsync.create(\n barrier_storage=storage.a_load2trans_full_mbar_ptr.data_ptr(),\n num_stages=self.num_load2trans_stage,\n producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread),\n consumer_group=pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n self.num_mcast_ctas_a * self.num_transform_warps,\n ),\n tx_count=self.num_tma_load_bytes_a_scale,\n cta_layout_vmnk=cluster_layout_vmnk,\n tidx=transform_thread_idx,\n mcast_mode_mn=(1, 0), # multicast for A will only happen on the M-mode\n defer_sync=True,\n )\n # Initialize transform2mma pipeline, which tracks the dependencies between the transformation\n # of A and MMA's consumption of transformed A\n cta_v_size = cute.size(cluster_layout_vmnk, mode=[0])\n trans2mma_pipeline = pipeline.PipelineAsyncUmma.create(\n barrier_storage=storage.a_trans2mma_full_mbar_ptr.data_ptr(),\n num_stages=self.num_trans2mma_stage,\n producer_group=pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n 32 * self.num_transform_warps * cta_v_size,\n ),\n consumer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread),\n cta_layout_vmnk=cluster_layout_vmnk,\n defer_sync=True,\n )\n # Initialize pipeline for tensor B load to MMA\n # MMA warp informs TMA warp to proceed to load next tile of B tensor\n b_load2mma_pipeline = pipeline.PipelineTmaUmma.create(\n barrier_storage=storage.b_load2mma_full_mbar_ptr.data_ptr(),\n num_stages=self.num_load2trans_stage,\n producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread),\n consumer_group=pipeline.CooperativeGroup(\n pipeline.Agent.Thread, self.num_mcast_ctas_b\n ),\n tx_count=self.num_tma_load_bytes_b,\n cta_layout_vmnk=cluster_layout_vmnk,\n mcast_mode_mn=(0, 1), # multicast for B will only happen on the N-mode\n defer_sync=True,\n )\n # Initialize accumulator pipeline, which tracks the dependencies between\n # MMA's computation of accumulators and epilogue warps' consumption of accumulators\n acc_pipeline = pipeline.PipelineUmmaAsync.create(\n barrier_storage=storage.acc_full_mbar_ptr.data_ptr(),\n num_stages=self.num_acc_stage,\n producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread),\n consumer_group=pipeline.CooperativeGroup(\n pipeline.Agent.Thread, cta_v_size * len(self.epilog_warp_id)\n ),\n cta_layout_vmnk=cluster_layout_vmnk,\n defer_sync=True,\n )\n # Initialize tile info pipeline, which tracks the dependencies between\n # tile scheduling warp and other warps\n # Every warp except the scheduler consumes routed-tile metadata.\n num_tile_info_pipeline_consumer_threads = self.threads_per_cta - 32\n tile_info_pipeline = pipeline.PipelineAsync.create(\n barrier_storage=storage.tile_info_full_mbar_ptr.data_ptr(),\n num_stages=self.num_tile_info_stage,\n producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread, 32 * 1),\n consumer_group=pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n num_tile_info_pipeline_consumer_threads,\n ),\n defer_sync=True,\n )\n clc_pipeline = None\n if cutlass.const_expr(self.use_clc_scheduler):\n clc_pipeline = pipeline.PipelineClcFetchAsync.create(\n barrier_storage=storage.clc_mbar_ptr.data_ptr(),\n num_stages=1,\n producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread),\n consumer_group=pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n 32 * cute.size(self.cluster_shape_mn),\n ),\n tx_count=16,\n cta_layout_vmnk=cluster_layout_vmnk,\n defer_sync=True,\n )\n\n # Tensor memory dealloc barrier init\n tmem = utils.TmemAllocator(\n storage.tmem_holding_buf.ptr,\n barrier_for_retrieve=self.tmem_ptr_sync_barrier,\n allocator_warp_id=self.epilog_warp_id[0],\n is_two_cta=use_2cta_instrs,\n two_cta_tmem_dealloc_mbar_ptr=storage.tmem_dealloc_mbar.ptr,\n )\n\n # Cluster arrive after barrier init\n pipeline_init_arrive(cluster_shape_mn=self.cluster_shape_mn, is_relaxed=True)\n\n # Setup smem tensor A/scale/B/C\n sC = smem.allocate_tensor(\n element_type=self.c_dtype,\n layout=c_smem_layout_staged.outer,\n byte_alignment=self.smem_buffer_align_bytes,\n swizzle=c_smem_layout_staged.inner,\n )\n # Fused finalize reuses the first C stage as a linear\n # [route, hidden] tile for descriptor-free bulk reduction. The bulk\n # reduction consumes raw contiguous bytes, so drop sC's pointer swizzle.\n sFinalize = (\n cute.make_tensor(\n cute.recast_ptr(sC.iterator),\n cute.make_layout(\n (self.epi_tile_n, self.cta_tile_shape_mnk[0]),\n stride=(self.cta_tile_shape_mnk[0], 1),\n ),\n )\n if cutlass.const_expr(self.use_fused_finalize)\n else None\n )\n sA_input = smem.allocate_tensor(\n element_type=self.a_dtype,\n layout=a_smem_layout.outer,\n byte_alignment=self.smem_buffer_align_bytes,\n swizzle=a_smem_layout.inner,\n )\n sS_input = smem.allocate_tensor(\n element_type=self.a_scale_dtype,\n layout=scale_smem_layout.outer,\n byte_alignment=self.smem_buffer_align_bytes,\n swizzle=scale_smem_layout.inner,\n )\n sS_tma = cute.make_tensor(sS_input.iterator, scale_tma_smem_layout)\n sA_transform_input = sA_input\n sS_transform_input = sS_input\n if cutlass.const_expr(self.gated):\n # Pair 16-row up/gate slices during decode so each epilogue warp\n # owns both operands in its 32 TMEM lanes.\n gated_row_layout = cute.make_layout(((16, 2), 4), stride=((1, 64), 16))\n sA_transform_input = cute.composition(\n sA_input,\n ((gated_row_layout, None), None, None, None),\n )\n sS_transform_input = cute.composition(\n sS_input,\n ((gated_row_layout, None), None, None),\n )\n sB_input = smem.allocate_tensor(\n element_type=self.b_dtype,\n layout=b_smem_layout.outer,\n byte_alignment=self.smem_buffer_align_bytes,\n swizzle=b_smem_layout.inner,\n )\n sA_transform = None\n # Get smem tensor for transformed A when transform_a_source is SMEM\n if cutlass.const_expr(self.transform_a_source == tcgen05.OperandSource.SMEM):\n sA_transform = smem.allocate_tensor(\n element_type=self.mma_dtype,\n layout=a_smem_layout_transform.outer,\n byte_alignment=self.smem_buffer_align_bytes,\n swizzle=a_smem_layout_transform.inner,\n )\n sFinalizeScale = (\n smem.allocate_tensor(\n element_type=cutlass.Float32,\n layout=cute.make_layout((self.epi_tile_n,)),\n byte_alignment=16,\n )\n if cutlass.const_expr(self.use_fused_finalize)\n else None\n )\n sTile_info = storage.tile_info.get_tensor(\n cute.make_layout((4, self.num_tile_info_stage), stride=(1, 4))\n )\n\n # Compute multicast mask for A/B buffer full\n a_full_mcast_mask = None\n b_full_mcast_mask = None\n s_full_mcast_mask = None\n if cutlass.const_expr(self.is_a_mcast or self.is_b_mcast or use_2cta_instrs):\n a_full_mcast_mask = cpasync.create_tma_multicast_mask(\n cluster_layout_vmnk, block_in_cluster_coord_vmnk, mcast_mode=2\n )\n # Scale tensor shares the same multicast mask as the A tensor\n s_full_mcast_mask = a_full_mcast_mask\n b_full_mcast_mask = cpasync.create_tma_multicast_mask(\n cluster_layout_vmnk, block_in_cluster_coord_vmnk, mcast_mode=1\n )\n\n # local_tile partition global tensors\n # (bM, bK, loopM, loopK, loopL)\n gA_mkl = cute.local_tile(\n mA_mkl, cute.slice_(self.mma_tiler, (None, 0, None)), (None, None, None)\n )\n # (bM, bK, loopM, loopK, loopL)\n gS_mkl = cute.local_tile(\n mS_mkl,\n cute.slice_(self.mma_tiler, (None, 0, None)),\n (None, None, None),\n )\n # (bN, bK, loopN, loopK, loopL)\n gB_nkl = cute.local_tile(\n mB_nkl, cute.slice_(self.mma_tiler, (0, None, None)), (None, None, None)\n )\n # (bM, bN, loopM, loopN, loopL)\n gC_mnl = cute.local_tile(\n mC_mnl,\n cute.slice_(self.mma_tiler_c, (None, None, 0)),\n (None, None, None),\n )\n gC_mnl_simt = cute.local_tile(\n tensor_c,\n cute.slice_(self.mma_tiler_c, (None, None, 0)),\n (None, None, None),\n )\n k_tile_cnt = cutlass.Int32(cute.size(gA_mkl, mode=[3]))\n\n # Partition global tensor for TiledMMA_A/B/C\n thr_mma = tiled_mma.get_slice(mma_tile_coord_v)\n # (MMA, MMA_M, MMA_K, loopM, loopK, loopL)\n tCgA = thr_mma.partition_A(gA_mkl)\n # (MMA, MMA_M, MMA_K, loopM, loopK, loopL)\n tCgS = thr_mma.partition_A(gS_mkl)\n # (MMA, MMA_N, MMA_K, loopN, loopK, loopL)\n tCgB = thr_mma.partition_B(gB_nkl)\n # (MMA, MMA_M, MMA_N, loopM, loopN, loopL)\n tCgC = thr_mma.partition_C(gC_mnl)\n tCgC_simt = thr_mma.partition_C(gC_mnl_simt)\n\n # Setup copy atom to load A from shared memory for further transformation\n copy_atom_a_input = cute.make_copy_atom(\n cute.nvgpu.CopyUniversalOp(), self.a_dtype, num_bits_per_copy=32\n )\n # Split complete NVFP4 blocks between two transform warpgroups.\n copy_atom_a_transform = cute.make_copy_atom(\n tcgen05.St32x32bOp(\n tcgen05.Repetition(8),\n tcgen05.Unpack.NONE,\n ),\n self.mma_dtype,\n )\n\n # Partition global/shared tensor for TMA load A/B\n # TMA load A partition_S/D\n a_cta_layout = cute.make_layout(\n cute.slice_(cluster_layout_vmnk, (0, 0, None, 0)).shape\n )\n # ((atom_v, rest_v), STAGE)\n # ((atom_v, rest_v), loopM, loopK, loopL)\n tAsA, tAgA = cpasync.tma_partition(\n tma_atom_a,\n block_in_cluster_coord_vmnk[2],\n a_cta_layout,\n cute.group_modes(sA_input, 0, 3),\n cute.group_modes(tCgA, 0, 3),\n )\n\n thr_mma_leader_cta = tiled_mma.get_slice(0)\n # (MMA, MMA_M, MMA_K, STAGE)\n tCsS = thr_mma_leader_cta.partition_A(sS_transform_input)\n tSsS, tSgS = cpasync.tma_partition(\n tma_atom_s,\n block_in_cluster_coord_vmnk[2],\n a_cta_layout,\n cute.group_modes(sS_tma, 0, 3),\n cute.group_modes(tCgS, 0, 3),\n )\n tSsS = cute.filter_zeros(tSsS)\n tSgS = cute.filter_zeros(tSgS)\n\n # TMA load B partition_S/D\n b_cta_layout = cute.make_layout(\n cute.slice_(cluster_layout_vmnk, (0, None, 0, 0)).shape\n )\n # ((atom_v, rest_v), STAGE)\n # ((atom_v, rest_v), loopM, loopK, loopL)\n tBsB, tBgB = cpasync.tma_partition(\n tma_atom_b,\n block_in_cluster_coord_vmnk[1],\n b_cta_layout,\n cute.group_modes(sB_input, 0, 3),\n cute.group_modes(tCgB, 0, 3),\n )\n\n # (MMA, MMA_N, MMA_K, STAGE)\n tCrB = tiled_mma.make_fragment_B(sB_input)\n # (MMA, MMA_M, MMA_N)\n acc_shape = tiled_mma.partition_shape_C(self.mma_tiler[:2])\n tCtAcc_fake = tiled_mma.make_fragment_C(\n cute.append(acc_shape, self.num_acc_stage)\n )\n\n # Cluster wait before TMEM alloc and ensure pipelines are ready.\n pipeline_init_wait(cluster_shape_mn=self.cluster_shape_mn)\n\n # TMEM allocation\n tmem.allocate(self.num_tmem_alloc_cols)\n tmem.wait_for_alloc()\n\n # Tile scheduling is independent of the preceding grid.\n if warp_idx == self.schedule_warp_id:\n cute.arch.setmaxregister_decrease(self.num_regs_generic_warps)\n tile_info_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.num_tile_info_stage\n )\n num_non_exiting_tiles_value = num_non_exiting_tiles[0]\n if cutlass.const_expr(self.use_clc_scheduler):\n tile_sched = utils.ClcDynamicPersistentTileScheduler.create(\n tile_sched_params,\n (bidx, bidy, bidz),\n cute.arch.grid_dim(),\n clc_response_ptr,\n )\n work_tile = tile_sched.initial_work_tile_info()\n clc_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.ProducerConsumer, 1\n )\n clc_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, 1\n )\n not_last_tile = cutlass.Boolean(1)\n while not_last_tile:\n tile_coord_mnl = work_tile.tile_idx\n route_tile_idx = tile_coord_mnl[1]\n is_routed_tile = work_tile.is_valid_tile and (\n route_tile_idx < num_non_exiting_tiles_value\n )\n\n if is_routed_tile or not work_tile.is_valid_tile:\n tile_info_pipeline.producer_acquire(tile_info_producer_state)\n\n if work_tile.is_valid_tile and is_first_cta_in_cluster:\n clc_pipeline.producer_acquire(clc_producer_state)\n tile_sched.advance_to_next_work(\n clc_pipeline.producer_get_barrier(clc_producer_state)\n )\n clc_producer_state.advance()\n\n if is_routed_tile or not work_tile.is_valid_tile:\n cur_sTile_info = sTile_info[\n (None, tile_info_producer_state.index)\n ]\n route_start = cutlass.Int32(-1)\n group_idx = cutlass.Int32(group_count)\n distance_to_boundary = cutlass.Int32(-1)\n if is_routed_tile:\n route_start = route_tile_idx * self.cta_tile_shape_mnk[1]\n group_idx = tile_idx_to_expert_idx[route_tile_idx]\n distance_to_boundary = (\n tile_idx_to_mn_limit[route_tile_idx] - route_start\n )\n with cute.arch.elect_one():\n cur_sTile_info[0] = tile_coord_mnl[0]\n cur_sTile_info[1] = route_start\n cur_sTile_info[2] = group_idx\n cur_sTile_info[3] = distance_to_boundary\n cute.arch.fence_proxy(\"async.shared\", space=\"cta\")\n self.sched_sync_barrier.arrive_and_wait()\n tile_info_pipeline.producer_commit(tile_info_producer_state)\n tile_info_producer_state.advance()\n\n if work_tile.is_valid_tile:\n clc_pipeline.consumer_wait(clc_consumer_state)\n work_tile = tile_sched.get_current_work()\n clc_pipeline.consumer_release(clc_consumer_state)\n clc_consumer_state.advance()\n else:\n not_last_tile = cutlass.Boolean(0)\n\n tile_info_pipeline.producer_tail(tile_info_producer_state)\n if is_first_cta_in_cluster:\n clc_pipeline.producer_tail(clc_producer_state)\n else:\n tile_sched = utils.StaticPersistentRuntimeTileScheduler.create(\n tile_sched_params,\n (bidx, bidy, bidz),\n cute.arch.grid_dim(),\n inner_mode=0 if self.raster_along_m else 1,\n )\n work_tile = tile_sched.initial_work_tile_info()\n not_last_tile = cutlass.Boolean(1)\n if cutlass.const_expr(self.raster_along_m):\n while not_last_tile:\n tile_info_pipeline.producer_acquire(tile_info_producer_state)\n cluster_tile_coord_mnl = work_tile.tile_idx\n cta_tile_coord_m = (\n cluster_tile_coord_mnl[0] * self.cluster_shape_mn[0]\n + block_in_cluster_coord_vmnk[1]\n * cute.size(tiled_mma.thr_id.shape)\n + block_in_cluster_coord_vmnk[0]\n )\n cta_tile_offset_n = block_in_cluster_coord_vmnk[2]\n route_tile_idx = (\n cluster_tile_coord_mnl[1] * self.cluster_shape_mn[1]\n + cta_tile_offset_n\n )\n not_last_tile = work_tile.is_valid_tile and (\n route_tile_idx < num_non_exiting_tiles_value\n )\n route_start = cutlass.Int32(-1)\n group_idx = cutlass.Int32(group_count)\n distance_to_boundary = cutlass.Int32(-1)\n if not_last_tile:\n route_start = route_tile_idx * self.cta_tile_shape_mnk[1]\n group_idx = tile_idx_to_expert_idx[route_tile_idx]\n distance_to_boundary = (\n tile_idx_to_mn_limit[route_tile_idx] - route_start\n )\n cur_sTile_info = sTile_info[\n (None, tile_info_producer_state.index)\n ]\n with cute.arch.elect_one():\n cur_sTile_info[0] = cta_tile_coord_m\n cur_sTile_info[1] = route_start\n cur_sTile_info[2] = group_idx\n cur_sTile_info[3] = distance_to_boundary\n cute.arch.fence_proxy(\"async.shared\", space=\"cta\")\n self.sched_sync_barrier.arrive_and_wait()\n tile_info_pipeline.producer_commit(tile_info_producer_state)\n tile_info_producer_state.advance()\n tile_sched.advance_to_next_work()\n work_tile = tile_sched.get_current_work()\n else:\n while not_last_tile:\n cluster_tile_coord_mnl = work_tile.tile_idx\n cta_tile_coord_m = (\n cluster_tile_coord_mnl[0] * self.cluster_shape_mn[0]\n + block_in_cluster_coord_vmnk[1]\n * cute.size(tiled_mma.thr_id.shape)\n + block_in_cluster_coord_vmnk[0]\n )\n cta_tile_offset_n = block_in_cluster_coord_vmnk[2]\n route_tile_idx = (\n cluster_tile_coord_mnl[1] * self.cluster_shape_mn[1]\n + cta_tile_offset_n\n )\n # The runtime scheduler leaves its outer mode unbounded.\n # With N as the inner mode, terminate on the finite M\n # extent and skip padded routed tiles within each M tile.\n has_work = work_tile.is_valid_tile and (\n cluster_tile_coord_mnl[0]\n < tile_sched_params.problem_layout_ncluster_mnl.shape[0]\n )\n is_routed_tile = has_work and (\n route_tile_idx < num_non_exiting_tiles_value\n )\n\n if is_routed_tile or not has_work:\n tile_info_pipeline.producer_acquire(\n tile_info_producer_state\n )\n route_start = cutlass.Int32(-1)\n group_idx = cutlass.Int32(group_count)\n distance_to_boundary = cutlass.Int32(-1)\n if is_routed_tile:\n route_start = (\n route_tile_idx * self.cta_tile_shape_mnk[1]\n )\n group_idx = tile_idx_to_expert_idx[route_tile_idx]\n distance_to_boundary = (\n tile_idx_to_mn_limit[route_tile_idx] - route_start\n )\n cur_sTile_info = sTile_info[\n (None, tile_info_producer_state.index)\n ]\n with cute.arch.elect_one():\n cur_sTile_info[0] = cta_tile_coord_m\n cur_sTile_info[1] = route_start\n cur_sTile_info[2] = group_idx\n cur_sTile_info[3] = distance_to_boundary\n cute.arch.fence_proxy(\"async.shared\", space=\"cta\")\n self.sched_sync_barrier.arrive_and_wait()\n tile_info_pipeline.producer_commit(tile_info_producer_state)\n tile_info_producer_state.advance()\n\n if has_work:\n tile_sched.advance_to_next_work()\n work_tile = tile_sched.get_current_work()\n else:\n not_last_tile = cutlass.Boolean(0)\n\n tile_info_pipeline.producer_tail(tile_info_producer_state)\n\n # The activation TMA warp is the only role that waits on the preceding grid.\n if warp_idx == self.activation_tma_warp_id:\n cute.arch.setmaxregister_decrease(self.num_regs_generic_warps)\n tile_info_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.num_tile_info_stage\n )\n tile_info_pipeline.consumer_wait(tile_info_consumer_state)\n work_tile = mixed_input_utils.make_contiguous_group_work_tile_info(\n group_count, sTile_info[(None, tile_info_consumer_state.index)]\n )\n cute.arch.fence_proxy(\n \"async.shared\",\n space=\"cta\",\n )\n tile_info_pipeline.consumer_release(tile_info_consumer_state)\n tile_info_consumer_state.advance()\n b_load2mma_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.num_load2trans_stage\n )\n if cutlass.const_expr(self.enable_pdl):\n griddepcontrol_wait()\n\n while work_tile.is_valid_tile:\n coord_n_offset = (\n (work_tile.coord_n, 0)\n if cutlass.const_expr(\n self.b_major_mode == cute.nvgpu.OperandMajorMode.MN\n )\n else (0, work_tile.coord_n)\n )\n tBgB_slice = cute.make_tensor(\n (\n tBgB.iterator[0] + coord_n_offset[0],\n coord_n_offset[1] + tBgB.iterator[1],\n ),\n cute.slice_(tBgB.layout, (None, 0, None, 0)),\n )\n\n b_load2mma_producer_state.reset_count()\n for _k_tile in cutlass.range(0, k_tile_cnt, 1, unroll=1):\n b_load2mma_pipeline.producer_acquire(b_load2mma_producer_state)\n cute.copy(\n tma_atom_b,\n tBgB_slice[(None, b_load2mma_producer_state.count)],\n tBsB[(None, b_load2mma_producer_state.index)],\n tma_bar_ptr=b_load2mma_pipeline.producer_get_barrier(\n b_load2mma_producer_state\n ),\n mcast_mask=b_full_mcast_mask,\n cache_policy=cutlass.Int64(_TMA_CACHE_HINT_EVICT_LAST),\n )\n b_load2mma_pipeline.producer_commit(b_load2mma_producer_state)\n b_load2mma_producer_state.advance()\n\n tile_info_pipeline.consumer_wait(tile_info_consumer_state)\n work_tile = mixed_input_utils.make_contiguous_group_work_tile_info(\n group_count, sTile_info[(None, tile_info_consumer_state.index)]\n )\n cute.arch.fence_proxy(\n \"async.shared\",\n space=\"cta\",\n )\n tile_info_pipeline.consumer_release(tile_info_consumer_state)\n tile_info_consumer_state.advance()\n b_load2mma_pipeline.producer_tail(b_load2mma_producer_state)\n\n # Static weight and scale loads can run before the activation is ready.\n if warp_idx == self.weight_tma_warp_id:\n cute.arch.setmaxregister_decrease(self.num_regs_generic_warps)\n tile_info_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.num_tile_info_stage\n )\n tile_info_pipeline.consumer_wait(tile_info_consumer_state)\n work_tile = mixed_input_utils.make_contiguous_group_work_tile_info(\n group_count, sTile_info[(None, tile_info_consumer_state.index)]\n )\n cute.arch.fence_proxy(\n \"async.shared\",\n space=\"cta\",\n )\n tile_info_pipeline.consumer_release(tile_info_consumer_state)\n tile_info_consumer_state.advance()\n a_load2trans_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.num_load2trans_stage\n )\n if cutlass.const_expr(self.enable_pdl and self.fuse_activation):\n with cute.arch.elect_one():\n griddepcontrol_launch_dependents()\n while work_tile.is_valid_tile:\n tAgA_slice = tAgA[\n (\n None,\n work_tile.cta_coord_m // cute.size(tiled_mma.thr_id.shape),\n None,\n work_tile.group_idx,\n )\n ]\n tSgS_slice = tSgS[\n (\n None,\n work_tile.cta_coord_m // cute.size(tiled_mma.thr_id.shape),\n None,\n work_tile.group_idx,\n )\n ]\n # Filter zeros in rest mode\n rest_filtered = cute.filter_zeros(tSgS_slice[(0, None)].layout)\n tSgS_slice_filtered = cute.make_tensor(\n tSgS_slice.iterator,\n cute.make_layout(\n (tSgS_slice.layout[0].shape, rest_filtered.shape),\n stride=(tSgS_slice.layout[0].stride, rest_filtered.stride),\n ),\n )\n\n a_load2trans_producer_state.reset_count()\n peek_load2trans_empty_status = cutlass.Boolean(1)\n if a_load2trans_producer_state.count < k_tile_cnt:\n peek_load2trans_empty_status = (\n a_load2trans_pipeline.producer_try_acquire(\n a_load2trans_producer_state\n )\n )\n for _k_tile in cutlass.range(0, k_tile_cnt, 1, unroll=1):\n a_load2trans_pipeline.producer_acquire(\n a_load2trans_producer_state,\n peek_load2trans_empty_status,\n )\n cute.copy(\n tma_atom_a,\n tAgA_slice[(None, a_load2trans_producer_state.count)],\n tAsA[(None, a_load2trans_producer_state.index)],\n tma_bar_ptr=a_load2trans_pipeline.producer_get_barrier(\n a_load2trans_producer_state\n ),\n mcast_mask=a_full_mcast_mask,\n cache_policy=cutlass.Int64(_TMA_CACHE_HINT_EVICT_FIRST),\n )\n cute.copy(\n tma_atom_s,\n tSgS_slice_filtered[(None, a_load2trans_producer_state.count)],\n tSsS[(None, a_load2trans_producer_state.index)],\n tma_bar_ptr=a_load2trans_pipeline.producer_get_barrier(\n a_load2trans_producer_state\n ),\n mcast_mask=s_full_mcast_mask,\n )\n a_load2trans_pipeline.producer_commit(a_load2trans_producer_state)\n a_load2trans_producer_state.advance()\n if a_load2trans_producer_state.count < k_tile_cnt:\n peek_load2trans_empty_status = (\n a_load2trans_pipeline.producer_try_acquire(\n a_load2trans_producer_state\n )\n )\n\n tile_info_pipeline.consumer_wait(tile_info_consumer_state)\n work_tile = mixed_input_utils.make_contiguous_group_work_tile_info(\n group_count, sTile_info[(None, tile_info_consumer_state.index)]\n )\n cute.arch.fence_proxy(\n \"async.shared\",\n space=\"cta\",\n )\n tile_info_pipeline.consumer_release(tile_info_consumer_state)\n tile_info_consumer_state.advance()\n\n a_load2trans_pipeline.producer_tail(a_load2trans_producer_state)\n\n # Specialized transform warps\n if warp_idx >= self.transform_warp_id[0]:\n transform_group_idx = (warp_idx - self.transform_warp_id[0]) // 4\n transform_local_tidx = tidx - 32 * (\n self.transform_warp_id[0] + transform_group_idx * 4\n )\n # Get the pointer to the TMEM buffer\n tmem_ptr = tmem.retrieve_ptr(self.acc_dtype)\n accumulators = cute.make_tensor(tmem_ptr, tCtAcc_fake.layout)\n\n (\n dst_copy_a,\n tAsA_input,\n tAsA_transform,\n tSsS_trans,\n tSrS_copy,\n tSrS_load,\n tArA_load,\n tArA_transform,\n tArA_transform_store,\n transform_tiler,\n ) = self._setup_transform_partitions(\n tiled_mma,\n copy_atom_a_input,\n copy_atom_a_transform,\n sA_transform_input,\n a_smem_layout_transform,\n sA_transform,\n tCsS,\n accumulators,\n transform_local_tidx,\n transform_group_idx,\n )\n\n tile_info_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.num_tile_info_stage\n )\n tile_info_pipeline.consumer_wait(tile_info_consumer_state)\n work_tile = mixed_input_utils.make_contiguous_group_work_tile_info(\n group_count, sTile_info[(None, tile_info_consumer_state.index)]\n )\n cute.arch.fence_proxy(\n \"async.shared\",\n space=\"cta\",\n )\n tile_info_pipeline.consumer_release(tile_info_consumer_state)\n tile_info_consumer_state.advance()\n a_load2trans_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer,\n self.num_load2trans_stage,\n )\n trans2mma_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer,\n self.num_trans2mma_stage,\n )\n while work_tile.is_valid_tile:\n (\n a_load2trans_consumer_state,\n trans2mma_producer_state,\n ) = self._transform_tile(\n a_load2trans_pipeline,\n trans2mma_pipeline,\n a_load2trans_consumer_state,\n trans2mma_producer_state,\n dst_copy_a,\n tAsA_input,\n tAsA_transform,\n tSsS_trans,\n tSrS_copy,\n tSrS_load,\n tArA_load,\n tArA_transform,\n tArA_transform_store,\n transform_tiler,\n k_tile_cnt,\n )\n # Advance to next tile\n tile_info_pipeline.consumer_wait(tile_info_consumer_state)\n work_tile = mixed_input_utils.make_contiguous_group_work_tile_info(\n group_count, sTile_info[(None, tile_info_consumer_state.index)]\n )\n cute.arch.fence_proxy(\n \"async.shared\",\n space=\"cta\",\n )\n tile_info_pipeline.consumer_release(tile_info_consumer_state)\n tile_info_consumer_state.advance()\n # Wait a_transform buffer empty\n trans2mma_pipeline.producer_tail(trans2mma_producer_state)\n\n # Specialized MMA warp\n if warp_idx == self.mma_warp_id:\n cute.arch.setmaxregister_decrease(self.num_regs_generic_warps)\n # Get the pointer to the TMEM buffer\n tmem_ptr = tmem.retrieve_ptr(self.acc_dtype)\n accumulators = cute.make_tensor(tmem_ptr, tCtAcc_fake.layout)\n if cutlass.const_expr(\n self.transform_a_source == tcgen05.OperandSource.TMEM\n ):\n tmem_ptr_transform = cute.recast_ptr(\n accumulators.iterator + self.num_acc_tmem_cols, dtype=self.mma_dtype\n )\n tCrA = cute.make_tensor(\n tmem_ptr_transform,\n tiled_mma.make_fragment_A(a_smem_layout_transform.outer).layout,\n )\n else:\n tCrA = tiled_mma.make_fragment_A(sA_transform)\n tCtAcc_base = accumulators\n # Persistent tile scheduling loop\n tile_info_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.num_tile_info_stage\n )\n tile_info_pipeline.consumer_wait(tile_info_consumer_state)\n work_tile = mixed_input_utils.make_contiguous_group_work_tile_info(\n group_count, sTile_info[(None, tile_info_consumer_state.index)]\n )\n cute.arch.fence_proxy(\n \"async.shared\",\n space=\"cta\",\n )\n tile_info_pipeline.consumer_release(tile_info_consumer_state)\n tile_info_consumer_state.advance()\n trans2mma_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.num_trans2mma_stage\n )\n b_load2mma_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.num_load2trans_stage\n )\n acc_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.num_acc_stage\n )\n while work_tile.is_valid_tile:\n # (MMA, MMA_M, MMA_N)\n tCtAcc = tCtAcc_base[(None, None, None, acc_producer_state.index)]\n b_load2mma_consumer_state.reset_count()\n trans2mma_consumer_state.reset_count()\n peek_trans2mma_full_status = cutlass.Boolean(1)\n if is_leader_cta:\n if trans2mma_consumer_state.count < k_tile_cnt:\n peek_trans2mma_full_status = (\n trans2mma_pipeline.consumer_try_wait(\n trans2mma_consumer_state\n )\n )\n acc_pipeline.producer_acquire(acc_producer_state)\n\n tiled_mma.set(tcgen05.Field.ACCUMULATE, False)\n # Mma mainloop\n for _k_tile in cutlass.range(0, k_tile_cnt, 1, unroll=1):\n trans2mma_pipeline.consumer_wait(\n trans2mma_consumer_state, peek_trans2mma_full_status\n )\n b_load2mma_pipeline.consumer_wait(b_load2mma_consumer_state)\n num_kblocks = cute.size(tCrA, mode=[2])\n for kblock_idx in cutlass.range(num_kblocks, unroll_full=True):\n kblock_coord_a = (\n None,\n None,\n kblock_idx,\n trans2mma_consumer_state.index,\n )\n kblock_coord_b = (\n None,\n None,\n kblock_idx,\n b_load2mma_consumer_state.index,\n )\n\n cute.gemm(\n tiled_mma,\n tCtAcc,\n tCrA[kblock_coord_a],\n tCrB[kblock_coord_b],\n tCtAcc,\n )\n # Enable accumulate on tCtAcc after first kblock\n tiled_mma.set(tcgen05.Field.ACCUMULATE, True)\n trans2mma_pipeline.consumer_release(trans2mma_consumer_state)\n b_load2mma_pipeline.consumer_release(b_load2mma_consumer_state)\n trans2mma_consumer_state.advance()\n b_load2mma_consumer_state.advance()\n peek_trans2mma_full_status = cutlass.Boolean(1)\n if trans2mma_consumer_state.count < k_tile_cnt:\n peek_trans2mma_full_status = (\n trans2mma_pipeline.consumer_try_wait(\n trans2mma_consumer_state\n )\n )\n # Async arrive accumulator buffer full\n acc_pipeline.producer_commit(acc_producer_state)\n acc_producer_state.advance()\n\n # Advance to next tile\n tile_info_pipeline.consumer_wait(tile_info_consumer_state)\n work_tile = mixed_input_utils.make_contiguous_group_work_tile_info(\n group_count, sTile_info[(None, tile_info_consumer_state.index)]\n )\n cute.arch.fence_proxy(\n \"async.shared\",\n space=\"cta\",\n )\n tile_info_pipeline.consumer_release(tile_info_consumer_state)\n tile_info_consumer_state.advance()\n # Wait for accumulator buffer empty\n acc_pipeline.producer_tail(acc_producer_state)\n\n # Specialized epilogue warps\n if warp_idx < self.mma_warp_id:\n cute.arch.setmaxregister_increase(self.num_regs_epilogue_warps)\n epi_tidx = tidx\n # Get the pointer to the TMEM buffer\n tmem_ptr = tmem.retrieve_ptr(self.acc_dtype)\n accumulators = cute.make_tensor(tmem_ptr, tCtAcc_fake.layout)\n tCtAcc_base = accumulators\n # Partition for epilogue\n tiled_copy_t2r, tTR_tAcc_base, tTR_rAcc = (\n mixed_input_utils.epilog_tmem_copy_and_partition(\n self.cta_tile_shape_mnk,\n self.c_layout,\n self.c_dtype,\n self.acc_dtype,\n epi_tidx,\n tCtAcc_base,\n tCgC,\n epi_tile,\n self.use_2cta_instrs,\n )\n )\n gated_tTR_tAcc_base = None\n gated_tiled_copy_t2r = None\n gated_tTR_identity_base = None\n gated_tTR_rAcc = None\n if cutlass.const_expr(self.gated):\n gated_epi_tile = (\n self.cta_tile_shape_mnk[0],\n self.epi_tile_n,\n )\n gated_copy_atom_t2r = sm100_utils.get_tmem_load_op(\n self.cta_tile_shape_mnk,\n self.c_layout,\n self.c_dtype,\n self.acc_dtype,\n gated_epi_tile,\n self.use_2cta_instrs,\n )\n gated_tAcc_epi = cute.flat_divide(\n tCtAcc_base[((None, None), 0, 0, None)],\n gated_epi_tile,\n )\n gated_tiled_copy_t2r = tcgen05.make_tmem_copy(\n gated_copy_atom_t2r,\n gated_tAcc_epi[(None, None, 0, 0, 0)],\n )\n gated_thr_copy_t2r = gated_tiled_copy_t2r.get_slice(epi_tidx)\n gated_tTR_tAcc_base = gated_thr_copy_t2r.partition_S(gated_tAcc_epi)\n gated_identity = cute.make_identity_tensor(self.cta_tile_shape_mnk[:2])\n gated_identity_epi = cute.flat_divide(gated_identity, gated_epi_tile)\n gated_tTR_identity_base = gated_thr_copy_t2r.partition_D(\n gated_identity_epi\n )\n gated_tTR_rAcc = cute.make_rmem_tensor(\n gated_tTR_identity_base[(None, None, None, 0, 0)].shape,\n self.acc_dtype,\n )\n tTR_rC = cute.make_rmem_tensor(tTR_rAcc.shape, self.c_dtype)\n tiled_copy_r2s, tRS_rC, tRS_sC = (\n mixed_input_utils.epilog_smem_copy_and_partition(\n self.c_layout,\n self.c_dtype,\n self.acc_dtype,\n tiled_copy_t2r,\n tTR_rC,\n epi_tidx,\n sC,\n )\n )\n (\n tma_atom_c,\n bSG_sC,\n bSG_gC_partitioned,\n simt_atom,\n tTR_gC_partitioned,\n ) = mixed_input_utils.epilog_gmem_copy_and_partition(\n self.c_dtype,\n epi_tidx,\n tma_atom_c,\n tiled_copy_t2r,\n tCgC,\n tCgC_simt,\n epi_tile,\n sC,\n )\n if cutlass.const_expr(self.gated):\n gC_epi = cute.local_tile(mC_mnl, epi_tile, (None, None, None))\n bSG_sC, bSG_gC_partitioned = cpasync.tma_partition(\n tma_atom_c,\n 0,\n cute.make_layout(1),\n cute.group_modes(sC, 0, 2),\n cute.group_modes(gC_epi, 0, 2),\n )\n\n # Predicates\n thr_mapping = cute.make_identity_tensor(\n (self.cta_tile_shape_mnk[0], self.cta_tile_shape_mnk[1])\n )\n thr_mapping_mn = cute.flat_divide(thr_mapping, epi_tile)\n thr_copy_t2r = tiled_copy_t2r.get_slice(epi_tidx)\n m_thr_offset = thr_copy_t2r.partition_D(thr_mapping_mn)\n m_thr_offset = cute.group_modes(m_thr_offset, 3, cute.rank(m_thr_offset))\n\n acc_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.num_acc_stage\n )\n\n c_producer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n 32 * len(self.epilog_warp_id),\n )\n c_pipeline = pipeline.PipelineTmaStore.create(\n num_stages=self.num_c_stage,\n producer_group=c_producer_group,\n )\n\n # Persistent tile scheduling loop\n tile_info_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.num_tile_info_stage\n )\n tile_info_pipeline.consumer_wait(tile_info_consumer_state)\n work_tile = mixed_input_utils.make_contiguous_group_work_tile_info(\n group_count, sTile_info[(None, tile_info_consumer_state.index)]\n )\n cute.arch.fence_proxy(\n \"async.shared\",\n space=\"cta\",\n )\n tile_info_pipeline.consumer_release(tile_info_consumer_state)\n tile_info_consumer_state.advance()\n num_prev_subtiles = cutlass.Int32(0)\n while work_tile.is_valid_tile:\n alpha_val = alpha[work_tile.group_idx]\n if cutlass.const_expr(self.gated):\n bSG_gC = bSG_gC_partitioned[(None, work_tile.cta_coord_m, None, 0)]\n else:\n bSG_gC = bSG_gC_partitioned[\n (\n None,\n None,\n None,\n work_tile.cta_coord_m // cute.size(tiled_mma.thr_id.shape),\n 0,\n 0,\n )\n ]\n tma_store_offset_coord = (\n (work_tile.coord_n, 0)\n if cutlass.const_expr(self.c_layout.is_n_major_c())\n else (0, work_tile.coord_n)\n )\n bSG_gC = cute.make_tensor(\n (\n tma_store_offset_coord[0] + bSG_gC.iterator[0],\n tma_store_offset_coord[1] + bSG_gC.iterator[1],\n ),\n bSG_gC.layout,\n )\n tTR_gC = tTR_gC_partitioned[\n (\n None,\n None,\n None,\n None,\n None,\n work_tile.cta_coord_m // cute.size(tiled_mma.thr_id.shape),\n 0,\n 0,\n )\n ]\n tTR_gC = cute.make_tensor(\n tTR_gC.iterator + (work_tile.coord_n * tensor_c.layout.stride[1]),\n tTR_gC.layout,\n )\n\n tTR_tAcc = tTR_tAcc_base[\n (None, None, None, None, None, acc_consumer_state.index)\n ]\n # Wait for accumulator buffer full\n acc_pipeline.consumer_wait(acc_consumer_state)\n if cutlass.const_expr(not self.gated):\n bSG_gC = cute.group_modes(bSG_gC, 1, cute.rank(bSG_gC))\n\n if cutlass.const_expr(self.gated):\n gated_tTR_tAcc = gated_tTR_tAcc_base[\n (None, None, None, None, None, acc_consumer_state.index)\n ]\n gated_subtile_cnt = cute.size(gated_tTR_tAcc.shape, mode=[4])\n gated_alpha_f32 = cutlass.Float32(alpha_val)\n swiglu_alpha = cutlass.Float32(self.swiglu_alpha)\n swiglu_beta = cutlass.Float32(self.swiglu_beta)\n swiglu_limit = cutlass.Float32(self.swiglu_limit)\n neg_swiglu_alpha_log2_e = -(\n swiglu_alpha * cutlass.Float32(1.4426950408889634)\n )\n for gated_subtile_idx in cutlass.range(gated_subtile_cnt):\n gated_tTR_tAcc_mn = gated_tTR_tAcc[\n (None, None, None, 0, gated_subtile_idx)\n ]\n cute.copy(\n gated_tiled_copy_t2r,\n gated_tTR_tAcc_mn,\n gated_tTR_rAcc,\n )\n if gated_subtile_idx == gated_subtile_cnt - 1:\n cute.arch.fence_view_async_tmem_load()\n with cute.arch.elect_one():\n acc_pipeline.consumer_release(acc_consumer_state)\n acc_consumer_state.advance()\n num_prev_subtiles += 1\n c_buffer = num_prev_subtiles % self.num_c_stage\n gated_identity_mn = gated_tTR_identity_base[\n (None, None, None, 0, gated_subtile_idx)\n ]\n up = cute.coalesce(\n cute.flatten(gated_tTR_rAcc[(None, 0, None)])\n ).load()\n gate = cute.coalesce(\n cute.flatten(gated_tTR_rAcc[(None, 1, None)])\n ).load()\n up_coords = cute.coalesce(\n cute.flatten(gated_identity_mn[(None, 0, None)])\n )\n up_size = cute.size(gated_tTR_rAcc[(None, 0, None)])\n for i in cutlass.range_constexpr(0, up_size, 2):\n up_pair = cute.arch.mul_packed_f32x2(\n (up[i], up[i + 1]),\n (gated_alpha_f32, gated_alpha_f32),\n )\n gate_pair = cute.arch.mul_packed_f32x2(\n (gate[i], gate[i + 1]),\n (gated_alpha_f32, gated_alpha_f32),\n )\n if cutlass.const_expr(\n self.activation_type == ActivationType.Swiglu.value\n and self.situ_beta is not None\n ):\n situ_beta = cutlass.Float32(self.situ_beta)\n situ_gate_pair = (\n situ_f32(gate_pair[0], situ_beta, fastmath=True),\n situ_f32(gate_pair[1], situ_beta, fastmath=True),\n )\n if cutlass.const_expr(\n self.situ_linear_beta is not None\n ):\n linear_beta = cutlass.Float32(self.situ_linear_beta)\n up_pair = (\n linear_beta\n * tanh_f32(\n up_pair[0] / linear_beta, fastmath=True\n ),\n linear_beta\n * tanh_f32(\n up_pair[1] / linear_beta, fastmath=True\n ),\n )\n result = cute.arch.mul_packed_f32x2(\n up_pair, situ_gate_pair\n )\n elif cutlass.const_expr(\n self.activation_type == ActivationType.GegluTanh.value\n ):\n result = cute.arch.mul_packed_f32x2(\n up_pair,\n (\n gelu_tanh_f32(gate_pair[0], fastmath=True),\n gelu_tanh_f32(gate_pair[1], fastmath=True),\n ),\n )\n elif cutlass.const_expr(\n self.activation_type == ActivationType.Swiglu.value\n ):\n if cutlass.const_expr(self.parameterized_swiglu):\n gate_pair = (\n fmin(gate_pair[0], swiglu_limit, nan=True),\n fmin(gate_pair[1], swiglu_limit, nan=True),\n )\n up_pair = (\n -fmin(\n -fmin(up_pair[0], swiglu_limit, nan=True),\n swiglu_limit,\n nan=True,\n ),\n -fmin(\n -fmin(up_pair[1], swiglu_limit, nan=True),\n swiglu_limit,\n nan=True,\n ),\n )\n gate_log2e = cute.arch.mul_packed_f32x2(\n gate_pair,\n (\n neg_swiglu_alpha_log2_e,\n neg_swiglu_alpha_log2_e,\n ),\n )\n sigmoid = cute.arch.add_packed_f32x2(\n (\n cute.math.exp2(gate_log2e[0], fastmath=True),\n cute.math.exp2(gate_log2e[1], fastmath=True),\n ),\n (1.0, 1.0),\n )\n sigmoid = (\n cute.arch.rcp_approx(sigmoid[0]),\n cute.arch.rcp_approx(sigmoid[1]),\n )\n silu = cute.arch.mul_packed_f32x2(gate_pair, sigmoid)\n if cutlass.const_expr(self.parameterized_swiglu):\n up_pair = cute.arch.add_packed_f32x2(\n up_pair, (swiglu_beta, swiglu_beta)\n )\n result = cute.arch.mul_packed_f32x2(up_pair, silu)\n\n coord_0 = up_coords[i]\n coord_1 = up_coords[i + 1]\n # Fold paired TMEM rows back into the reduced-M\n # output tile and keep the staged N coordinate local.\n output_m_0 = coord_0[0] // 32 * 16 + coord_0[0] % 16\n output_m_1 = coord_1[0] // 32 * 16 + coord_1[0] % 16\n output_n_0 = coord_0[1] % self.epi_tile_n\n output_n_1 = coord_1[1] % self.epi_tile_n\n sC[(output_m_0, output_n_0, c_buffer)] = self.c_dtype(\n result[0]\n )\n sC[(output_m_1, output_n_1, c_buffer)] = self.c_dtype(\n result[1]\n )\n\n cute.arch.fence_proxy(\"async.shared\", space=\"cta\")\n self.epilog_sync_barrier.arrive_and_wait()\n if warp_idx == self.epilog_warp_id[0]:\n cute.copy(\n tma_atom_c,\n bSG_sC[(None, c_buffer)],\n bSG_gC[\n (\n None,\n work_tile.coord_n // self.epi_tile_n\n + gated_subtile_idx,\n )\n ],\n )\n c_pipeline.producer_commit()\n c_pipeline.producer_acquire()\n self.epilog_sync_barrier.arrive_and_wait()\n\n tTR_tAcc = cute.group_modes(tTR_tAcc, 3, cute.rank(tTR_tAcc))\n tTR_gC = cute.group_modes(tTR_gC, 3, cute.rank(tTR_gC))\n tma_distance_to_boundary = work_tile.distance_to_boundary\n\n # Store accumulator to global memory in subtiles\n subtile_cnt = (\n 0\n if cutlass.const_expr(self.gated)\n else cute.size(tTR_tAcc.shape, mode=[3])\n )\n for subtile_idx in cutlass.range(subtile_cnt):\n # Load accumulator from tensor memory buffer to register\n tTR_tAcc_mn = tTR_tAcc[(None, None, None, subtile_idx)]\n cute.copy(tiled_copy_t2r, tTR_tAcc_mn, tTR_rAcc)\n if subtile_idx == subtile_cnt - 1:\n cute.arch.fence_view_async_tmem_load()\n with cute.arch.elect_one():\n acc_pipeline.consumer_release(acc_consumer_state)\n acc_consumer_state.advance()\n\n if cutlass.const_expr(self.fuse_activation):\n alpha_f32 = cutlass.Float32(alpha_val)\n acc_up = tTR_rAcc.load()\n for i in cutlass.range_constexpr(0, cute.size(tTR_rAcc), 2):\n value = cute.arch.mul_packed_f32x2(\n (acc_up[i], acc_up[i + 1]),\n (alpha_f32, alpha_f32),\n )\n relu = (\n cute.arch.fmax(value[0], cutlass.Float32(0.0)),\n cute.arch.fmax(value[1], cutlass.Float32(0.0)),\n )\n tTR_rAcc[i], tTR_rAcc[i + 1] = cute.arch.mul_packed_f32x2(\n relu, relu\n )\n if cutlass.const_expr(self.use_fused_finalize):\n finalize_thr_slice = m_thr_offset[\n (None, None, None, subtile_idx)\n ]\n top_k = token_final_scales.shape[1]\n finalize_scale_route = epi_tidx\n finalize_scale_route_in_tile = (\n subtile_idx * self.epi_tile_n + finalize_scale_route\n )\n if finalize_scale_route < self.epi_tile_n:\n finalize_scale_permuted_row = (\n work_tile.coord_n + finalize_scale_route_in_tile\n )\n finalize_scale_expanded_idx = permuted_idx_to_expanded_idx[\n finalize_scale_permuted_row\n ]\n finalize_scale_safe_idx = cutlass.max(\n finalize_scale_expanded_idx, cutlass.Int32(0)\n )\n finalize_scale_token_idx = finalize_scale_safe_idx // top_k\n finalize_scale_topk_idx = finalize_scale_safe_idx % top_k\n finalize_scale_is_valid = cutlass.Int32(\n finalize_scale_route_in_tile\n < work_tile.distance_to_boundary\n )\n finalize_token_scale = token_final_scales[\n (\n finalize_scale_token_idx * finalize_scale_is_valid,\n finalize_scale_topk_idx,\n )\n ]\n sFinalizeScale[finalize_scale_route] = (\n cutlass.Float32(alpha_val)\n * cutlass.Float32(finalize_token_scale)\n * cutlass.Float32(finalize_scale_is_valid)\n )\n\n cute.arch.fence_proxy(\"async.shared\", space=\"cta\")\n self.epilog_sync_barrier.arrive_and_wait()\n for i in cutlass.range(cute.size(tTR_rC), unroll_full=True):\n finalize_route = finalize_thr_slice[(i)][1]\n finalize_value = sFinalizeScale[\n finalize_route % self.epi_tile_n\n ] * cutlass.Float32(tTR_rAcc[i])\n sFinalize[\n (\n finalize_route % self.epi_tile_n,\n finalize_thr_slice[(i)][0],\n )\n ] = self.c_dtype(finalize_value)\n\n cute.arch.fence_proxy(\"async.shared\", space=\"cta\")\n self.epilog_sync_barrier.arrive_and_wait()\n\n reduce_route = epi_tidx\n reduce_route_in_tile = (\n subtile_idx * self.epi_tile_n + reduce_route\n )\n if (\n reduce_route < self.epi_tile_n\n and reduce_route_in_tile < work_tile.distance_to_boundary\n ):\n reduce_permuted_row = (\n work_tile.coord_n + reduce_route_in_tile\n )\n reduce_expanded_idx = permuted_idx_to_expanded_idx[\n reduce_permuted_row\n ]\n reduce_token_idx = reduce_expanded_idx // top_k\n hidden_base = (\n work_tile.cta_coord_m * self.cta_tile_shape_mnk[0]\n )\n valid_elements = (\n cutlass.Int64(final_output.shape[0]) - hidden_base\n )\n if valid_elements > 0:\n scatter_out = cute.domain_offset(\n (hidden_base, reduce_token_idx, 0), final_output\n )\n copy_elements = cutlass.Int32(\n cutlass.min(\n cutlass.Int64(self.cta_tile_shape_mnk[0]),\n valid_elements,\n )\n )\n blk_reduce_bf16(\n scatter_out,\n sFinalize[(reduce_route, None)],\n copy_elements * (self.c_dtype.width // 8),\n )\n\n cute.arch.cp_async_bulk_commit_group()\n cute.arch.cp_async_bulk_wait_group(0, read=True)\n self.epilog_sync_barrier.arrive_and_wait()\n elif tma_distance_to_boundary >= self.cta_tile_shape_mnk[1]:\n # Convert to C type\n acc_vec = tiled_copy_r2s.retile(tTR_rAcc).load()\n if cutlass.const_expr(not self.fuse_activation):\n acc_vec = cutlass.Float32(alpha_val) * acc_vec\n acc_vec = acc_vec.to(self.c_dtype)\n tRS_rC.store(acc_vec)\n num_prev_subtiles += 1\n c_buffer = num_prev_subtiles % self.num_c_stage\n # Store C to shared memory\n cute.copy(\n tiled_copy_r2s,\n tRS_rC,\n tRS_sC[(None, None, None, c_buffer)],\n )\n # Fence and barrier to make sure shared memory store is visible to TMA store\n cute.arch.fence_proxy(\n \"async.shared\",\n space=\"cta\",\n )\n self.epilog_sync_barrier.arrive_and_wait()\n # TMA store C to global memory\n if warp_idx == self.epilog_warp_id[0]:\n cute.copy(\n tma_atom_c,\n bSG_sC[(None, c_buffer)],\n bSG_gC[(None, subtile_idx)],\n )\n c_pipeline.producer_commit()\n c_pipeline.producer_acquire()\n self.epilog_sync_barrier.arrive_and_wait()\n else:\n # Convert to C type\n acc_vec = tTR_rAcc.load()\n if cutlass.const_expr(not self.fuse_activation):\n acc_vec = cutlass.Float32(alpha_val) * acc_vec\n acc_vec = acc_vec.to(self.c_dtype)\n tTR_rC.store(acc_vec)\n # Compute predicate for SIMT store\n tCpC = cute.make_rmem_tensor(\n cute.make_layout(tTR_rC.shape),\n cutlass.Boolean,\n )\n m_thr_slice = m_thr_offset[(None, None, None, subtile_idx)]\n for i in cutlass.range(cute.size(tCpC), unroll_full=True):\n tCpC[i] = (\n m_thr_slice[(i)][0]\n + work_tile.cta_coord_m * self.cta_tile_shape_mnk_c[0]\n < cute.size(tensor_c.shape[0])\n ) and (m_thr_slice[(i)][1] < work_tile.distance_to_boundary)\n # Store C to global memory\n cute.copy(\n simt_atom,\n cute.flatten(tTR_rC),\n cute.flatten(tTR_gC[(None, None, None, subtile_idx)]),\n pred=cute.flatten(tCpC),\n )\n # Advance to next tile\n tile_info_pipeline.consumer_wait(tile_info_consumer_state)\n work_tile = mixed_input_utils.make_contiguous_group_work_tile_info(\n group_count, sTile_info[(None, tile_info_consumer_state.index)]\n )\n cute.arch.fence_proxy(\n \"async.shared\",\n space=\"cta\",\n )\n tile_info_pipeline.consumer_release(tile_info_consumer_state)\n tile_info_consumer_state.advance()\n\n # Dealloc the tensor memory buffer\n tmem.relinquish_alloc_permit()\n self.epilog_sync_barrier.arrive_and_wait()\n tmem.free(tmem_ptr)\n if cutlass.const_expr(not self.use_fused_finalize):\n c_pipeline.producer_tail()\n\n if cutlass.const_expr(self.enable_pdl and not self.fuse_activation):\n if warp_idx == self.mma_warp_id:\n with cute.arch.elect_one():\n griddepcontrol_launch_dependents()\n\n @staticmethod\n def _compute_stages_and_tmem_cols(\n tiled_mma: cute.TiledMma,\n mma_tiler_mnk: tuple[int, int, int],\n cta_tile_shape_mnk: tuple[int, int, int],\n epi_tile: cute.Tile,\n a_dtype: type[cutlass.Numeric],\n b_dtype: type[cutlass.Numeric],\n c_dtype: type[cutlass.Numeric],\n c_layout: utils.LayoutEnum,\n transform_a_source: tcgen05.OperandSource,\n smem_buffer_align_bytes: int,\n use_fused_finalize: bool,\n use_clc_scheduler: bool,\n ) -> tuple[int, int, int, int, int, int, int]:\n \"\"\"Fit the load, transform, accumulator, and epilogue pipelines.\"\"\"\n # Compute tmem columns required for accumulator\n acc_shape = tiled_mma.partition_shape_C(mma_tiler_mnk[:2])\n tCtAcc_stage1 = tiled_mma.make_fragment_C(cute.append(acc_shape, 1))\n num_tmem_acc_col_per_stage = utils.get_num_tmem_alloc_cols(tCtAcc_stage1, True)\n # Heuristic to decide the number of stages for accumulator\n sm100_tmem_columns = cute.arch.get_max_tmem_alloc_cols(\"sm_100\")\n accumulator_stage_count = sm100_tmem_columns // num_tmem_acc_col_per_stage\n if transform_a_source == tcgen05.OperandSource.TMEM:\n if num_tmem_acc_col_per_stage < 256:\n accumulator_stage_count = 2\n else:\n accumulator_stage_count = 1\n # transformed A in 16bit, thus 1 tmem column could hold 2 elements\n num_elts_per_tmem_col = 32 // tiled_mma.op.a_dtype.width\n num_tmem_cols_a_per_stage = cute.round_up(\n (\n cta_tile_shape_mnk[2] // num_elts_per_tmem_col\n if transform_a_source == tcgen05.OperandSource.TMEM\n else 0\n ),\n 4,\n )\n\n bytes_per_pipeline_stage = 16\n # Limit how far CLC can claim work ahead of the consumer pipelines.\n num_tile_info_stage = 1 if use_clc_scheduler else 3\n tile_info_bytes = (\n cute.size_in_bytes(cute.Int32, cute.make_layout((4, num_tile_info_stage)))\n + bytes_per_pipeline_stage * num_tile_info_stage\n )\n\n c_stage_count = 1 if use_fused_finalize else 2\n c_smem_layout_staged_one = sm100_utils.make_smem_layout_epi(\n c_dtype,\n c_layout,\n epi_tile,\n 1,\n )\n c_bytes_per_stage = cute.size_in_bytes(c_dtype, c_smem_layout_staged_one)\n c_bytes = c_bytes_per_stage * c_stage_count\n finalize_metadata_bytes = (\n cute.size_in_bytes(\n cutlass.Float32,\n cute.make_layout((cute.size(epi_tile[1]),)),\n )\n if use_fused_finalize\n else 0\n )\n\n smem_capacity = utils.get_smem_capacity_in_bytes(\"sm_100\")\n a_scale_k_mode = max(cta_tile_shape_mnk[2] // _NVFP4_SCALE_GRANULARITY_K, 1)\n a_scale_m_mode = max(cta_tile_shape_mnk[0] // _NVFP4_SCALE_GRANULARITY_M, 1)\n a_scale_bytes_per_stage = cute.round_up(\n cute.size_in_bytes(\n tiled_mma.op.a_dtype,\n cute.make_layout((a_scale_m_mode, a_scale_k_mode)),\n ),\n smem_buffer_align_bytes,\n )\n carveout_smem_bytes = (\n bytes_per_pipeline_stage * accumulator_stage_count\n + c_bytes\n + finalize_metadata_bytes\n + tile_info_bytes\n )\n\n # Compute transform stages if A is in TMEM\n num_tmem_acc_cols = cute.round_up(\n accumulator_stage_count * num_tmem_acc_col_per_stage, 4\n )\n\n transform2mma_stage_count_a_source_tmem_potential = (\n (sm100_tmem_columns - num_tmem_acc_cols) // num_tmem_cols_a_per_stage\n if transform_a_source == tcgen05.OperandSource.TMEM\n else -1\n )\n if (\n transform_a_source == tcgen05.OperandSource.TMEM\n and transform2mma_stage_count_a_source_tmem_potential <= 0\n ):\n raise ValueError(\"Not enough TMEM capacity for selected tile size\")\n a_load_bytes_per_stage = cute.round_up(\n cute.size_in_bytes(\n a_dtype,\n cute.make_layout((cta_tile_shape_mnk[0], cta_tile_shape_mnk[2])),\n ),\n smem_buffer_align_bytes,\n )\n b_load_bytes_per_stage = cute.round_up(\n cute.size_in_bytes(\n b_dtype,\n cute.make_layout(\n (\n cta_tile_shape_mnk[1] // cute.size(tiled_mma.thr_id),\n cta_tile_shape_mnk[2],\n )\n ),\n ),\n smem_buffer_align_bytes,\n )\n ab_scale_load_bytes_per_stage = (\n a_load_bytes_per_stage\n + b_load_bytes_per_stage\n + a_scale_bytes_per_stage\n + 2 * bytes_per_pipeline_stage\n )\n a_transform_bytes_per_stage = (\n cute.round_up(\n cute.size_in_bytes(\n tiled_mma.op.a_dtype,\n cute.make_layout((cta_tile_shape_mnk[0], cta_tile_shape_mnk[2])),\n ),\n smem_buffer_align_bytes,\n )\n if transform_a_source == tcgen05.OperandSource.SMEM\n else 0\n )\n\n a_transform_bytes_per_stage = (\n a_transform_bytes_per_stage + bytes_per_pipeline_stage\n )\n transform2mma_stage_count_a_source_smem_potential = (\n smem_capacity - carveout_smem_bytes\n ) // (ab_scale_load_bytes_per_stage + a_transform_bytes_per_stage)\n transform2mma_stage_count = (\n min(\n transform2mma_stage_count_a_source_tmem_potential,\n transform2mma_stage_count_a_source_smem_potential,\n )\n if transform_a_source == tcgen05.OperandSource.TMEM\n else transform2mma_stage_count_a_source_smem_potential\n )\n load2transform_stage_count = (\n smem_capacity\n - carveout_smem_bytes\n - (transform2mma_stage_count * a_transform_bytes_per_stage)\n ) // ab_scale_load_bytes_per_stage\n if (\n load2transform_stage_count < 2\n or transform2mma_stage_count < 2\n or accumulator_stage_count < 1\n ):\n raise ValueError(\"Not enough SMEM or TMEM capacity for selected tile size\")\n num_tmem_a_cols = transform2mma_stage_count * num_tmem_cols_a_per_stage\n # Fused finalize reuses its single C stage as reduction scratch.\n if not use_fused_finalize:\n c_stage_count += (\n smem_capacity\n - carveout_smem_bytes\n - load2transform_stage_count * ab_scale_load_bytes_per_stage\n - transform2mma_stage_count * a_transform_bytes_per_stage\n ) // c_bytes_per_stage\n\n return (\n load2transform_stage_count,\n transform2mma_stage_count,\n accumulator_stage_count,\n c_stage_count,\n num_tile_info_stage,\n num_tmem_acc_cols,\n num_tmem_a_cols,\n )\n\n @staticmethod\n def _compute_grid(\n c: cute.Tensor,\n cta_tile_shape_mnk: tuple[int, int, int],\n cluster_shape_mn: tuple[int, int],\n max_active_clusters: cutlass.Constexpr,\n use_clc_scheduler: bool,\n raster_along_m: bool,\n ) -> tuple[\n Union[\n utils.ClcDynamicPersistentTileSchedulerParams,\n utils.PersistentTileSchedulerParams,\n ],\n tuple[int, int, int],\n ]:\n \"\"\"Build the persistent scheduler and launch grid.\"\"\"\n c_shape = cute.slice_(cta_tile_shape_mnk, (None, None, 0))\n gc = cute.zipped_divide(c, tiler=c_shape)\n num_ctas_mnl = gc[(0, (None, None, None))].shape\n cluster_shape_mnl = (*cluster_shape_mn, 1)\n\n if use_clc_scheduler:\n tile_sched_params = utils.ClcDynamicPersistentTileSchedulerParams(\n num_ctas_mnl, cluster_shape_mnl\n )\n grid = utils.ClcDynamicPersistentTileScheduler.get_grid_shape(\n tile_sched_params\n )\n else:\n tile_sched_params = utils.PersistentTileSchedulerParams(\n num_ctas_mnl,\n cluster_shape_mnl,\n raster_along_m=raster_along_m,\n )\n grid = (cluster_shape_mn[0], cluster_shape_mn[1], max_active_clusters)\n\n return tile_sched_params, grid\n\n @staticmethod\n def can_implement(\n mnkl: tuple[int, int, int, int],\n a_dtype: type[cutlass.Numeric],\n b_dtype: type[cutlass.Numeric],\n c_dtype: type[cutlass.Numeric],\n a_major: str,\n b_major: str,\n c_major: str,\n mma_tiler: tuple[int, int, int],\n cluster_shape_mn: tuple[int, int],\n use_2cta_instrs: bool,\n ) -> bool:\n \"\"\"Return whether the requested layout and tile shape are supported.\"\"\"\n m, n, k, _ = mnkl\n\n if not mixed_input_utils.is_valid_mma_tiler_and_cluster_shape(\n mma_tiler, cluster_shape_mn, use_2cta_instrs\n ):\n return False\n # Unlike the generic mixed-input kernel, W4A16 consumes multiple\n # 16-value NVFP4 scale blocks within each MMA K tile.\n if (\n k % _NVFP4_SCALE_GRANULARITY_K != 0\n or mma_tiler[2] % _NVFP4_SCALE_GRANULARITY_K != 0\n ):\n return False\n if not mixed_input_utils.is_valid_tensor_alignment(\n m,\n n,\n k,\n a_dtype,\n b_dtype,\n c_dtype,\n b_dtype,\n a_major,\n b_major,\n c_major,\n mma_tiler,\n use_2cta_instrs,\n cluster_shape_mn,\n _NVFP4_SCALE_GRANULARITY_M,\n _NVFP4_SCALE_GRANULARITY_K,\n ):\n return False\n return True\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\n@humansand\n\nThis is a focused follow-up to #4394 and #4506 for the CuTe DSL W4A16 SiTU path.\n\n- Preserve `situ_beta` as a Python scalar so the existing shared `situ_f32` helper folds its FP32 reciprocal while tracing.\n- Precompute the optional up-branch reciprocal with `f32_reciprocal`, then replace both per-element divisions with multiplies.\n- Reuse the existing gate-only and gate-plus-up SiTU accuracy cases, which already exercise both reciprocal paths changed here.\n- Leave GeGLU, ordinary SwiGLU, ReLU2, GEMM2, routing, and finalize behavior unchanged.\n\nThe reciprocal is derived from the FP32-rounded beta, matching the value used by the kernel's multiply-back step. Reciprocal multiplication is tolerance-equivalent to division, but is not guaranteed to be bitwise-identical.\n\n## 🔍 Related Issues\n\n- #4394\n- #4506\n\n## ⏱️ Performance\n\n### Environment and workload\n\n- Image: `nvcr.io/nvidia/pytorch:26.05-py3` (`linux/amd64` digest `sha256:ca73b4795f0d3ae27e9cd81b1b1f1b7fc6c0a129f7d51a359d2326e95af48a3d`)\n- Devbox: `c1`, host `B200-147`, 8 x NVIDIA B200; measurements pinned to GPU 0 at a 1000 W power limit\n- Driver: `580.126.09`\n- Python: `3.12.3`\n- PyTorch: `2.12.0a0+5aff3928d8.nv26.05`\n- PyTorch CUDA / system nvcc: `13.2` / `13.2` (`cuda_13.2.r13.2`, compiler `37668154_0`)\n- FlashInfer: `0.6.18`\n- `nvidia-cutlass-dsl`: `4.7.0`\n- `cupti-python`: `13.3.1`\n- Baseline: `f4043ef18c92f38e0c70da76ca40b26d36318eed` (the #4394 merge on `main`)\n- Candidate kernel: `093fd3d7d24fa01afa16445cae230e477335f3fc`\n- Workload: pre-routed W4A16 fused MoE, BF16 activations, NVFP4 weights, `E=896`, `topK=16`, `H=3584`, `I=3072`, `situ_beta=4.0`, `situ_linear_beta=25.0`\n\nThis is a Kimi-K3-shaped W4A16 derivative. It does not claim to use Kimi-K3's native MXFP4 weight format.\n\n### Method\n\n- One fresh process per adjacent `A1 baseline -> B candidate -> A2 baseline` arm on the same GPU and node.\n- A1 generated a single autotune cache; B and A2 loaded it cache-only. The selected tactic was then passed explicitly to every timed call, and exact A1/B/A2 tactic equality was validated for every shape.\n- Full weight construction and quantization, compilation, and autotuning were outside the timed region.\n- CUDA-event timing used `use_cuda_graph=False`, `cold_l2_cache=True`, 10 warmups, 50 measured samples per repeat, and 3 repeats per arm.\n- Every measured shape reported finite output.\n- Derived baseline latency is the median of the six A1+A2 repeat medians. Candidate latency is the median of the three B repeat medians. `speedup = baseline / candidate`, so values above `1.0x` are faster.\n\nSelected tactics for both GEMMs were identical across A1/B/A2:\n\n| Tokens | Tactic per GEMM |\n|---:|:---|\n| 1, 8, 64, 512 | `((256, 16, 256), (2, 1), true)` |\n| 2048 | `((256, 64, 256), (2, 1), true)` |\n| 4096 | `((128, 128, 256), (2, 1), true)` |\n| 8192 | `((256, 192, 256), (2, 1), true)` |\n\n### Raw CUDA-event repeat medians\n\nAll values are milliseconds.\n\n| Tokens | A1 r1 | A1 r2 | A1 r3 | B r1 | B r2 | B r3 | A2 r1 | A2 r2 | A2 r3 |\n|---:|---:|---:|---:|---:|---:|---:|---:|---:|---:|\n| 1 | 0.109600 | 0.109760 | 0.110400 | 0.107648 | 0.108432 | 0.108384 | 0.108448 | 0.108544 | 0.108560 |\n| 8 | 0.611312 | 0.611328 | 0.611328 | 0.607264 | 0.607264 | 0.607232 | 0.610848 | 0.611360 | 0.610416 |\n| 64 | 4.231168 | 4.325312 | 4.294672 | 4.063312 | 4.272128 | 4.251680 | 4.149184 | 4.296640 | 4.292672 |\n| 512 | 4.392864 | 4.448288 | 4.446208 | 4.432448 | 4.429984 | 4.433216 | 4.437952 | 4.442624 | 4.438000 |\n| 2048 | 5.702688 | 5.713840 | 5.715040 | 5.338224 | 5.483472 | 5.453744 | 5.466608 | 5.663840 | 5.660288 |\n| 4096 | 7.799760 | 7.794224 | 7.797776 | 6.896560 | 7.029232 | 7.144368 | 7.370256 | 7.487568 | 7.549360 |\n| 8192 | 11.601920 | 11.608000 | 11.610096 | 10.840064 | 10.907632 | 10.906624 | 11.527200 | 11.636208 | 11.628608 |\n\n### Derived CUDA-event results\n\n| Tokens | Baseline median (ms) | Candidate median (ms) | Speedup |\n|---:|---:|---:|---:|\n| 1 | 0.109080 | 0.108384 | 1.0064x |\n| 8 | 0.611320 | 0.607264 | 1.0067x |\n| 64 | 4.293672 | 4.251680 | 1.0099x |\n| 512 | 4.440312 | 4.432448 | 1.0018x |\n| 2048 | 5.683264 | 5.453744 | 1.0421x |\n| 4096 | 7.671792 | 7.029232 | 1.0914x |\n| 8192 | 11.609048 | 10.906624 | 1.0644x |\n\nThe 1-512-token changes are at or below 1% and are treated as noise. The measurable result is `1.0421x-1.0914x` at 2048-8192 tokens. At 4096 tokens the two event-timed baseline arms drifted (`~7.798 ms` A1 versus `~7.488 ms` A2), but the candidate stayed below both arms; the separate CUPTI timing-backend spot-check below corroborates the direction.\n\n### CUPTI 4096-token spot-check\n\nThis used the same fixed tactic and cold-L2 path in fresh A1/B/A2 processes, with 10 warmups and 50 samples per arm. CUPTI mode permits one repeat per process.\n\n| Arm | Revision | Median (ms) |\n|:---|:---|---:|\n| A1 baseline | `f4043ef18c92f38e0c70da76ca40b26d36318eed` | 7.234587 |\n| B candidate | `093fd3d7d24fa01afa16445cae230e477335f3fc` | 6.889771 |\n| A2 baseline | `f4043ef18c92f38e0c70da76ca40b26d36318eed` | 7.367835 |\n| Bracketing baseline | median of A1 and A2 | 7.301211 |\n\nThe CUPTI spot-check shows a `1.0597x` speedup (`7.301211 / 6.889771`), corresponding to 5.64% lower latency.\n\n### Reproduction commands\n\nThe benchmark harness is retained locally and in branch commit `ae6f92f5`, but is intentionally absent from the PR's final tree. The run used the same script before a formatting-only `ruff format` pass. To recover that equivalent harness from branch history, then verify that A1 starts without an existing tactic cache:\n\n```bash\ngit show ae6f92f5:benchmarks/bench_w4a16_situ.py \\\n > /hai-workspace/w4a16-situ-tools/bench_w4a16_situ.py\nmkdir -p /hai-workspace/w4a16-situ-results\ntest ! -e /hai-workspace/w4a16-situ-results/tactics.json\n```\n\nThe following are the exact CUDA-event arm commands:\n\n```bash\ncd /hai-workspace/flashinfer-baseline\nCUDA_VISIBLE_DEVICES=0 FLASHINFER_DISABLE_VERSION_CHECK=1 \\\nFLASHINFER_WORKSPACE_BASE=/hai-workspace/cache-baseline \\\nPYTHONPATH=/hai-workspace/flashinfer-baseline \\\npython3 /hai-workspace/w4a16-situ-tools/bench_w4a16_situ.py \\\n --arm A1-baseline \\\n --revision f4043ef18c92f38e0c70da76ca40b26d36318eed \\\n --tokens 1,8,64,512,2048,4096,8192 \\\n --warmup 10 --iters 50 --repeats 3 --timing event \\\n --autotune-cache /hai-workspace/w4a16-situ-results/tactics.json \\\n --json-out /hai-workspace/w4a16-situ-results/A1-baseline.json\n\ncd /hai-workspace/flashinfer-candidate\nCUDA_VISIBLE_DEVICES=0 FLASHINFER_DISABLE_VERSION_CHECK=1 \\\nFLASHINFER_WORKSPACE_BASE=/hai-workspace/cache-tests-candidate \\\nPYTHONPATH=/hai-workspace/flashinfer-candidate \\\npython3 /hai-workspace/w4a16-situ-tools/bench_w4a16_situ.py \\\n --arm B-candidate \\\n --revision 093fd3d7d24fa01afa16445cae230e477335f3fc \\\n --tokens 1,8,64,512,2048,4096,8192 \\\n --warmup 10 --iters 50 --repeats 3 --timing event \\\n --autotune-cache /hai-workspace/w4a16-situ-results/tactics.json \\\n --json-out /hai-workspace/w4a16-situ-results/B-candidate.json\n\ncd /hai-workspace/flashinfer-baseline\nCUDA_VISIBLE_DEVICES=0 FLASHINFER_DISABLE_VERSION_CHECK=1 \\\nFLASHINFER_WORKSPACE_BASE=/hai-workspace/cache-baseline \\\nPYTHONPATH=/hai-workspace/flashinfer-baseline \\\npython3 /hai-workspace/w4a16-situ-tools/bench_w4a16_situ.py \\\n --arm A2-baseline \\\n --revision f4043ef18c92f38e0c70da76ca40b26d36318eed \\\n --tokens 1,8,64,512,2048,4096,8192 \\\n --warmup 10 --iters 50 --repeats 3 --timing event \\\n --autotune-cache /hai-workspace/w4a16-situ-results/tactics.json \\\n --json-out /hai-workspace/w4a16-situ-results/A2-baseline.json\n```\n\nThe CUPTI commands changed only the arm/output labels and timing arguments:\n\n```bash\ncd /hai-workspace/flashinfer-baseline\nCUDA_VISIBLE_DEVICES=0 FLASHINFER_DISABLE_VERSION_CHECK=1 \\\nFLASHINFER_WORKSPACE_BASE=/hai-workspace/cache-baseline \\\nPYTHONPATH=/hai-workspace/flashinfer-baseline \\\npython3 /hai-workspace/w4a16-situ-tools/bench_w4a16_situ.py \\\n --arm A1-cupti \\\n --revision f4043ef18c92f38e0c70da76ca40b26d36318eed \\\n --tokens 4096 --warmup 10 --iters 50 --repeats 1 --timing cupti \\\n --autotune-cache /hai-workspace/w4a16-situ-results/tactics.json \\\n --json-out /hai-workspace/w4a16-situ-results/cupti-4096/A1.json\n\ncd /hai-workspace/flashinfer-candidate\nCUDA_VISIBLE_DEVICES=0 FLASHINFER_DISABLE_VERSION_CHECK=1 \\\nFLASHINFER_WORKSPACE_BASE=/hai-workspace/cache-tests-candidate \\\nPYTHONPATH=/hai-workspace/flashinfer-candidate \\\npython3 /hai-workspace/w4a16-situ-tools/bench_w4a16_situ.py \\\n --arm B-cupti \\\n --revision 093fd3d7d24fa01afa16445cae230e477335f3fc \\\n --tokens 4096 --warmup 10 --iters 50 --repeats 1 --timing cupti \\\n --autotune-cache /hai-workspace/w4a16-situ-results/tactics.json \\\n --json-out /hai-workspace/w4a16-situ-results/cupti-4096/B.json\n\ncd /hai-workspace/flashinfer-baseline\nCUDA_VISIBLE_DEVICES=0 FLASHINFER_DISABLE_VERSION_CHECK=1 \\\nFLASHINFER_WORKSPACE_BASE=/hai-workspace/cache-baseline \\\nPYTHONPATH=/hai-workspace/flashinfer-baseline \\\npython3 /hai-workspace/w4a16-situ-tools/bench_w4a16_situ.py \\\n --arm A2-cupti \\\n --revision f4043ef18c92f38e0c70da76ca40b26d36318eed \\\n --tokens 4096 --warmup 10 --iters 50 --repeats 1 --timing cupti \\\n --autotune-cache /hai-workspace/w4a16-situ-results/tactics.json \\\n --json-out /hai-workspace/w4a16-situ-results/cupti-4096/A2.json\n```\n\nRaw JSON artifact checksums:\n\n```text\n4fd5c520996a529dde48f7a9f2ddef757efbb2f51f297dc68478ed89b0418268 A1-baseline.json\n1447f556b1293e0a9472af9c066b7b9228a5a3bf2cfe3eea5e37e166e5e5d8d9 B-candidate.json\n3be3b8066ffe2662f89ad274ff06aecab2e89c02e083c4f69a4aabc441bdccc8 A2-baseline.json\n89c7416855d513228d8f4e93bf8d6d4cb87f72fa0e91674ee52213835e187e0e tactics.json\n1c8ca8e5f792a13b7bb1d6303ca089f6f2ffc7c322d5d3d580387b814a4c91ae cupti-4096/A1.json\n6baeda5a3294fb23ce73fb837d08dcee7356067bd1b21ec44faee19571187522 cupti-4096/B.json\n039afa49d9db2787182d096b5a818541ce26fd11ba0d1ad079dce8411acae979 cupti-4096/A2.json\n```\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [ ] All tests are passing (`unittest`, etc.).\n\nFull-suite validation was not run. Targeted validation used PR head `adcf4b123caaeda1fe589a722462c8beb75d7176` on one NVIDIA B300 SXM6 AC (SM103, driver `590.48.01`) per process:\n\n- CUDA 12.9: `flashinfer/flashinfer-ci-cu129:20260811-e673f7f`, Python 3.12.13, PyTorch 2.13.0+cu129, CuTe DSL 4.7.0\n- CUDA 13.0: `flashinfer/flashinfer-ci-cu130:20260811-e673f7f`, Python 3.12.13, PyTorch 2.13.0+cu130, CuTe DSL 4.7.0\n\nThe same targeted commands were run in both images from `/hai-workspace/flashinfer-pr4540`; `<stack>` was `cu129` or `cu130`:\n\n```bash\nCUDA_VISIBLE_DEVICES=0 FLASHINFER_DISABLE_VERSION_CHECK=1 \\\nFLASHINFER_WORKSPACE_BASE=/hai-workspace/cache-pr4540-<stack> \\\npython -m pytest -vv -s \\\n tests/moe/test_cute_dsl_fused_moe.py::TestCuteDslFusedMoeFunctional::test_situ_accuracy \\\n --tb=long\n\nCUDA_VISIBLE_DEVICES=0 FLASHINFER_DISABLE_VERSION_CHECK=1 \\\nFLASHINFER_WORKSPACE_BASE=/hai-workspace/cache-pr4540-<stack> \\\npython -m pytest -vv -s \\\n tests/moe/test_cute_dsl_fused_moe.py::TestCuteDslMoEWrapper::test_wrapper_with_autotune \\\n -k \"w4a16 and situ\" --tb=long\n```\n\n```text\nCUDA 12.9 functional SiTU matrix:\n6 passed, 337 warnings in 648.05s (0:10:48)\n\nCUDA 12.9 W4A16 SiTU wrapper/autotune:\n1 passed, 7 deselected, 1219 warnings in 52.98s\n\nCUDA 13.0 functional SiTU matrix:\n6 passed, 337 warnings in 1020.78s (0:17:00)\n\nCUDA 13.0 W4A16 SiTU wrapper/autotune:\n1 passed, 7 deselected, 1219 warnings in 51.78s\n```\n\nNo test-file change remains in the final diff. Existing coverage is sufficient for both W4A16 paths changed here:\n\n- `(1.75, None)` exercises the gate-only `situ_f32` path and its trace-time reciprocal.\n- `(0.8, 1.5)` exercises the gate path plus the optional up-branch reciprocal and both multiplication sites.\n- `test_wrapper_with_autotune[situ-w4a16]` covers wrapper propagation, autotuning, and compiled execution.\n\nThe warnings were CuTe DSL deprecation warnings; none of these runs reported a test failure.\n\nLocal source checks:\n\n```bash\npre-commit run --all-files\npre-commit run --files \\\n flashinfer/fused_moe/cute_dsl/blackwell/moe_w4a16_kernel.py \\\n tests/moe/test_cute_dsl_fused_moe.py\npython3 -m compileall -q \\\n flashinfer/fused_moe/cute_dsl/blackwell/moe_w4a16_kernel.py \\\n tests/moe/test_cute_dsl_fused_moe.py\ngit diff --check upstream/main...HEAD\n```\n\n```text\npre-commit run --all-files: all applicable hooks passed\nApplicable hooks passed:\n check-added-large-files, check-case-conflict, check-merge-conflict,\n end-of-file-fixer, mixed-line-ending, trailing-whitespace, remove-tabs,\n remove-crlf, mypy, ruff-check, ruff-format\nSkipped (no applicable files): check-symlinks, clang-format\ncompileall: exit 0\ngit diff --check: exit 0\n```\n\n## Reviewer Notes\n\nPlease focus on the trace-time scalar handling and the FP32 reciprocal contract. This follows the same mechanism as #4506, but changes only the W4A16 caller that #4394 introduced.\n\nLimitations and untested scope:\n\n- The performance workload is Kimi-K3-shaped W4A16 (BF16 activations and NVFP4 weights), not Kimi-K3's native MXFP4 weight format.\n- Measurements cover the pre-routed fused-MoE operator on one B200; routing and end-to-end model performance are out of scope.\n- Event-timing changes at or below 1% are treated as noise; no small-shape speedup is claimed.\n- Only the targeted SiTU accuracy and wrapper/autotune tests were run, not the full repository test suite.\n- By routing W4A16 through the shared `f32_reciprocal` helper, this follow-up inherits its limitation for positive Python betas that round to FP32 zero. No validation change is included here, and the production `4.0` / `25.0` betas are unaffected.\n\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"E=896,H=3584,I=3072,situ_beta=4.0,situ_linear_beta=25.0\", \"batch_size\": 2048, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 5.683264, \"optimized\": 5.453744, \"stated_speedup\": 1.0421, \"speedup\": 1.0421}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"E=896,H=3584,I=3072,situ_beta=4.0,situ_linear_beta=25.0\", \"batch_size\": 4096, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 7.671792, \"optimized\": 7.029232, \"stated_speedup\": 1.0914, \"speedup\": 1.0914}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"E=896,H=3584,I=3072,situ_beta=4.0,situ_linear_beta=25.0\", \"batch_size\": 8192, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 11.609048, \"optimized\": 10.906624, \"stated_speedup\": 1.0644, \"speedup\": 1.0644}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"E=896,H=3584,I=3072,situ_beta=4.0,situ_linear_beta=25.0\", \"batch_size\": 4096, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 7.301211, \"optimized\": 6.889771, \"stated_speedup\": 1.0597, \"speedup\": 1.0597}]"},"kernel_speedup":{"kind":"number","value":1.0621,"string":"1.0621"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1085,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"3f5acea9cf8a738724f7a07b4d8b1ae4a4fa25e5"},"date":{"kind":"string","value":"2026-08-14T13:39:52-07:00"},"pr_number":{"kind":"number","value":4506,"string":"4,506"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/4506"},"title":{"kind":"string","value":"perf(moe): fold the SiTU beta reciprocal in the CuTe DSL MoE epilogue (#4506)"},"message":{"kind":"string","value":"perf(moe): fold the SiTU beta reciprocal in the CuTe DSL MoE epilogue (#4506)\n\n`x / beta` in the SiTU gate and up branches lowers to a per-element\n`div.rn.f32`: folding it to `x * (1/beta)` is only legal when `1/beta`\nis\nexact, which the SiTU betas (e.g. Kimi-K3's 25.0) are not. Compute the\nreciprocal at trace time and multiply instead.\n\n`f32_reciprocal` derives it from the fp32 beta the kernel multiplies\nback in,\nso `x * inv_beta` stays consistent with `x / beta_f32`; taking the\nreciprocal\nof the unrounded Python float can differ by 1 ulp when beta is not\nfp32-exact.\n\nKimi-K3 MoE (E=896, topK=16, hidden=3584, intermediate=3072) on one B200\nat\n1000 W, NVFP4, pre-routed, autotuned, microseconds, best of 3 repeats of\n50 timed iters:\n\n| tokens | 1 | 8 | 64 | 512 | 2048 | 4096 | 8192 |\n|---|---|---|---|---|---|---|---|\n| SiTU before | 123 | 673 | 3167 | 4744 | 4779 | 4845 | 7826 |\n| SiTU after | 77 | 363 | 1734 | 2702 | 2914 | 3011 | 4992 |\n| SwiGLU | 75 | 360 | 1724 | 2677 | 2761 | 2998 | 4361 |\n\nSiTU now lands within 1-6% of SwiGLU on the same kernel through 4096\ntokens.\n\n`pytest tests/moe/test_cute_dsl_fused_moe.py -k situ` is unchanged (7\npassed,\n2 failed; both failures pre-exist on main)\n<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\n<!-- What does this PR do? Briefly describe the changes and why they’re\nneeded. -->\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the\npre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [ ] Tests have been added or updated as needed.\n- [ ] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc.\n-->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n## Summary by CodeRabbit\n\n* **Performance**\n* Improved SiTU activation calculations by replacing repeated division\nwith precomputed reciprocal multiplication.\n* Optimized both vectorized and scalar calculation paths while\npreserving existing behavior.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->"},"path":{"kind":"string","value":"flashinfer/fused_moe/cute_dsl/blackwell/utils.py"},"language":{"kind":"string","value":"cute_dsl"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"# Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.\n# SPDX-License-Identifier: Apache-2.0\n#\n# Licensed under the Apache License, Version 2.0 (the \"License\");\n# you may not use this file except in compliance with the License.\n# You may obtain a copy of the License at\n#\n# http://www.apache.org/licenses/LICENSE-2.0\n#\n# Unless required by applicable law or agreed to in writing, software\n# distributed under the License is distributed on an \"AS IS\" BASIS,\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n# See the License for the specific language governing permissions and\n# limitations under the License.\n\n# Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.\n# SPDX-License-Identifier: BSD-3-Clause\n\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions are met:\n\n# 1. Redistributions of source code must retain the above copyright notice, this\n# list of conditions and the following disclaimer.\n\n# 2. Redistributions in binary form must reproduce the above copyright notice,\n# this list of conditions and the following disclaimer in the documentation\n# and/or other materials provided with the distribution.\n\n# 3. Neither the name of the copyright holder nor the names of its\n# contributors may be used to endorse or promote products derived from\n# this software without specific prior written permission.\n\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n# This file is copied and modified from cutlass https://github.com/NVIDIA/cutlass/blob/main/python/CuTeDSL/cutlass/cute/core.py\n\nimport ctypes\nimport functools\nfrom typing import Union\n\nimport cutlass\nimport cutlass._mlir.dialects.cute as _cute_ir\nimport cutlass.cute as cute\nfrom cutlass._mlir import ir\nfrom cutlass._mlir.dialects import llvm, nvvm\nfrom cutlass.cute.typing import AddressSpace, Numeric, Pointer, Type\nfrom cutlass.cutlass_dsl import T, dsl_user_op\n\n\n# WAR for CuTeDSL make_ptr implementation\nclass _Pointer(Pointer):\n \"\"\"Represents a runtime pointer that can interoperate with various data structures,\n including numpy arrays and device memory.\n\n Args:\n pointer (int or pointer-like object): The pointer to the data.\n dtype (Type): Data type of the elements pointed to.\n mem_space (_cute_ir.AddressSpace, optional): Memory space where the pointer resides. Defaults to generic.\n assumed_align (int, optional): Alignment of the input pointer in bytes. Defaults to None.\n\n Attributes:\n _pointer: The underlying pointer.\n _dtype: Data type of the elements.\n _addr_space: Memory space of the pointer.\n _assumed_align: Alignment of the pointer in bytes.\n _desc: C-type descriptor for the pointer.\n _c_pointer: C-compatible pointer representation.\n \"\"\"\n\n def __init__(\n self,\n pointer,\n dtype,\n mem_space: _cute_ir.AddressSpace = _cute_ir.AddressSpace.generic,\n assumed_align=None,\n ):\n self._pointer = pointer\n self._dtype = dtype\n self._addr_space = mem_space\n\n if assumed_align is None:\n self._assumed_align = dtype.width // 8\n else:\n self._assumed_align = assumed_align\n\n self._desc = None\n self._c_pointer = None\n assert int(self._pointer) % self._assumed_align == 0, (\n f\"pointer must be {self._assumed_align} bytes aligned\"\n )\n\n def size_in_bytes(self) -> int:\n return ctypes.sizeof(ctypes.c_void_p(int(self._pointer)))\n\n def __get_mlir_types__(self):\n return [self.mlir_type]\n\n def __c_pointers__(self):\n if self._c_pointer is None:\n self._desc = ctypes.c_void_p(int(self._pointer))\n self._c_pointer = ctypes.addressof(self._desc)\n return [self._c_pointer]\n\n def __new_from_mlir_values__(self, values):\n assert len(values) == 1\n return values[0]\n\n # Move mlir Type out of __init__ to decouple with mlir Context\n @property\n def mlir_type(self) -> ir.Type:\n return _cute_ir.PtrType.get(\n self._dtype.mlir_type, self._addr_space, self._assumed_align\n )\n\n @property\n def dtype(self) -> Type[Numeric]:\n return self._dtype\n\n @property\n def memspace(self):\n return self._addr_space\n\n def align(self, min_align: int, *, loc=None, ip=None) -> Pointer:\n raise NotImplementedError(\"align is not supported in runtime\")\n\n def verify(self, expected_py_type):\n if expected_py_type is Pointer or (\n isinstance(expected_py_type, ir.Value) and expected_py_type.ty is Pointer\n ):\n return True\n\n return False\n\n def __str__(self) -> str:\n return f\"Ptr<0x{int(self._pointer):016x}@{self._addr_space}>\"\n\n def __repr__(self):\n return self.__str__()\n\n\ndef make_ptr(\n dtype: Type[Numeric],\n value: Union[int, ctypes._Pointer],\n mem_space: AddressSpace = AddressSpace.generic,\n assumed_align=None,\n) -> Pointer:\n \"\"\"Creates a pointer from a memory address.\n\n Args:\n dtype (Type[Numeric]): Data type of the pointer elements.\n value (Union[int, ctypes._Pointer]): Memory address as an integer or ctypes pointer.\n mem_space (AddressSpace, optional): Memory address space. Defaults to AddressSpace.generic.\n assumed_align (int, optional): Alignment in bytes. Defaults to None.\n\n Returns:\n Pointer: A pointer object.\n\n Example:\n ```python\n import numpy as np\n import ctypes\n from cutlass import Float32\n from cutlass.cute.runtime import make_ptr\n\n # Create a numpy array\n a = np.random.randn(16, 32).astype(np.float32)\n # Get pointer address as ctypes pointer\n ptr_address = a.ctypes.data_as(ctypes.POINTER(ctypes.c_float))\n # Create pointer from address\n y = make_ptr(cutlass.Float32, ptr_address)\n ```\n \"\"\"\n # check if value is int or ctypes.POINTER\n if isinstance(value, int):\n address_value = value\n elif isinstance(value, ctypes._Pointer):\n # get address value\n address_value = ctypes.cast(value, ctypes.c_void_p).value\n assert address_value is not None, \"Pointer address is None\"\n else:\n raise TypeError(\n f\"Expect int or ctypes.POINTER for value but got {type(value)=}\"\n )\n\n return _Pointer(address_value, dtype, mem_space, assumed_align=assumed_align)\n\n\ndef is_power_of_2(x: int) -> bool:\n return x > 0 and (x & (x - 1)) == 0\n\n\n@functools.lru_cache(maxsize=None)\ndef _nvvm_fmin_needs_res():\n import inspect\n\n return \"res\" in inspect.signature(nvvm.fmin).parameters\n\n\n@dsl_user_op\ndef fmin(\n a: Union[float, cutlass.Float32],\n b: Union[float, cutlass.Float32],\n *,\n nan=False,\n loc=None,\n ip=None,\n) -> cutlass.Float32:\n a_val = cutlass.Float32(a).ir_value(loc=loc, ip=ip)\n b_val = cutlass.Float32(b).ir_value(loc=loc, ip=ip)\n if _nvvm_fmin_needs_res():\n # CUDA 12: nvvm.fmin(res, a, b, ...)\n result = nvvm.fmin(T.f32(), a_val, b_val, nan=nan, loc=loc, ip=ip)\n else:\n # CUDA 13: nvvm.fmin(a, b, ...)\n result = nvvm.fmin(a_val, b_val, nan=nan, loc=loc, ip=ip)\n return cutlass.Float32(result)\n\n\ndef sigmoid_f32(\n a: Union[float, cutlass.Float32], fastmath: bool = False\n) -> Union[float, cutlass.Float32]:\n \"\"\"\n Compute the sigmoid of the input tensor.\n \"\"\"\n return cute.arch.rcp_approx(1.0 + cute.math.exp(-a, fastmath=fastmath))\n\n\ndef silu_f32(\n a: Union[float, cutlass.Float32], fastmath: bool = False\n) -> Union[float, cutlass.Float32]:\n \"\"\"\n Compute the silu of the input tensor.\n \"\"\"\n return a * sigmoid_f32(a, fastmath=fastmath)\n\n\ndef tanh_f32(\n a: Union[float, cutlass.Float32], fastmath: bool = False\n) -> Union[float, cutlass.Float32]:\n \"\"\"Compute tanh from the existing sigmoid primitive.\"\"\"\n return cutlass.Float32(2.0) * sigmoid_f32(\n cutlass.Float32(2.0) * a, fastmath=fastmath\n ) - cutlass.Float32(1.0)\n\n\ndef situ_f32(\n a: Union[float, cutlass.Float32],\n beta: Union[float, cutlass.Float32],\n fastmath: bool = False,\n) -> Union[float, cutlass.Float32]:\n \"\"\"Compute SiTU: beta * tanh(x / beta) * sigmoid(x).\"\"\"\n x = cutlass.Float32(a)\n beta_f32 = cutlass.Float32(beta)\n return (\n beta_f32\n * tanh_f32(x / beta_f32, fastmath=fastmath)\n * sigmoid_f32(x, fastmath=fastmath)\n )\n\n\ndef gelu_tanh_f32(\n a: Union[float, cutlass.Float32], fastmath: bool = False\n) -> Union[float, cutlass.Float32]:\n \"\"\"Compute GELU using the tanh approximation.\"\"\"\n x = cutlass.Float32(a)\n inner = cutlass.Float32(0.7978845608028654) * (\n x + cutlass.Float32(0.044715) * x * x * x\n )\n return (\n cutlass.Float32(0.5)\n * x\n * (cutlass.Float32(1.0) + tanh_f32(inner, fastmath=fastmath))\n )\n\n\n# TODO(zhichenj): try to move these to NVVM wrapper or helper functions\n@dsl_user_op\ndef vectorized_atomic_add_bf16x8(\n rOut_epi_packed, scatter_out_offset, loc=None, ip=None\n):\n llvm.inline_asm(\n None,\n [\n scatter_out_offset.iterator.llvm_ptr,\n llvm.bitcast(T.i32(), rOut_epi_packed[0, None].load().ir_value()),\n llvm.bitcast(T.i32(), rOut_epi_packed[1, None].load().ir_value()),\n llvm.bitcast(T.i32(), rOut_epi_packed[2, None].load().ir_value()),\n llvm.bitcast(T.i32(), rOut_epi_packed[3, None].load().ir_value()),\n ],\n \"red.global.v4.bf16x2.add.noftz [$0], {$1, $2, $3, $4};\",\n \"l,r,r,r,r\",\n has_side_effects=True,\n loc=loc,\n ip=ip,\n )\n\n\n@dsl_user_op\ndef vectorized_atomic_add_fp32x2(\n rOut_epi_packed, scatter_out_offset, loc=None, ip=None\n):\n llvm.inline_asm(\n None,\n [\n scatter_out_offset.iterator.llvm_ptr,\n rOut_epi_packed[0].ir_value(),\n rOut_epi_packed[1].ir_value(),\n ],\n \"red.global.v2.f32.add [$0], {$1, $2};\",\n \"l,f,f\",\n has_side_effects=True,\n loc=loc,\n ip=ip,\n )\n\n\n@dsl_user_op\ndef atomic_add_func(rOut_epi_packed, scatter_out_offset, loc=None, ip=None):\n if cutlass.const_expr(rOut_epi_packed.dtype == cutlass.Float32):\n llvm.inline_asm(\n None,\n [\n scatter_out_offset.iterator.llvm_ptr,\n rOut_epi_packed.ir_value(),\n ],\n \"red.global.add.f32 [$0], $1;\",\n \"l,f\",\n has_side_effects=True,\n loc=loc,\n ip=ip,\n )\n elif cutlass.const_expr(rOut_epi_packed.dtype == cutlass.BFloat16):\n llvm.inline_asm(\n None,\n [\n scatter_out_offset.iterator.llvm_ptr,\n llvm.bitcast(T.i16(), rOut_epi_packed.ir_value()),\n ],\n \"red.add.noftz.bf16 [$0], $1;\",\n \"l,h\",\n has_side_effects=True,\n loc=loc,\n ip=ip,\n )\n\n\n@dsl_user_op\ndef blk_copy(dst_gemm, src_smem, size, loc=None, ip=None):\n llvm.inline_asm(\n None,\n [\n dst_gemm.iterator.toint(loc=loc, ip=ip).ir_value(loc=loc, ip=ip),\n src_smem.iterator.toint(loc=loc, ip=ip).ir_value(loc=loc, ip=ip),\n size.ir_value(loc=loc, ip=ip),\n ],\n \"cp.async.bulk.global.shared::cta.bulk_group [$0], [$1], $2;\",\n \"l,r,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n\n@dsl_user_op\ndef blk_reduce_bf16(dst_gemm, src_smem, size, loc=None, ip=None):\n llvm.inline_asm(\n None,\n [\n dst_gemm.iterator.llvm_ptr,\n src_smem.iterator.llvm_ptr,\n size.ir_value(),\n ],\n \"cp.reduce.async.bulk.global.shared::cta.bulk_group.add.noftz.bf16 [$0], [$1], $2;\",\n \"l,l,r\",\n has_side_effects=True,\n loc=loc,\n ip=ip,\n )\n\n\n@dsl_user_op\ndef blk_reduce_fp32(dst_gemm, src_smem, size, loc=None, ip=None):\n llvm.inline_asm(\n None,\n [\n dst_gemm.iterator.llvm_ptr,\n src_smem.iterator.llvm_ptr,\n size.ir_value(),\n ],\n \"cp.reduce.async.bulk.global.shared::cta.bulk_group.add.f32 [$0], [$1], $2;\",\n \"l,l,r\",\n has_side_effects=True,\n loc=loc,\n ip=ip,\n )\n\n\n@dsl_user_op\ndef blk_reduce_fp16(dst_gemm, src_smem, size, loc=None, ip=None):\n llvm.inline_asm(\n None,\n [\n dst_gemm.iterator.llvm_ptr,\n src_smem.iterator.llvm_ptr,\n size.ir_value(),\n ],\n \"cp.reduce.async.bulk.global.shared::cta.bulk_group.noftz.f16 [$0], [$1], $2;\",\n \"l,l,r\",\n has_side_effects=True,\n loc=loc,\n ip=ip,\n )\n\n\n@dsl_user_op\ndef griddepcontrol_wait(*, loc=None, ip=None) -> None:\n \"\"\"\n This instruction is used to wait for the previous kernel's grid ending\n (all blocks of the previous kernel have finished and memflushed), i.e.,\n the instruction after this instruction will not be issued until the previous\n grid has finished.\n \"\"\"\n llvm.inline_asm(\n res=None,\n operands_=[],\n asm_string=\"griddepcontrol.wait;\",\n constraints=\"\",\n has_side_effects=True,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n\n@dsl_user_op\ndef griddepcontrol_launch_dependents(*, loc=None, ip=None) -> None:\n \"\"\"\n Issuing the launch_dependents instruction hints a dependent kernel to launch earlier.\n launch_dependents doesn't impact the functionality but the performance:\n Launching a dependent kernel too early can compete with current kernels,\n while launching too late can lead to a long latency.\n \"\"\"\n llvm.inline_asm(\n res=None,\n operands_=[],\n asm_string=\"griddepcontrol.launch_dependents;\",\n constraints=\"\",\n has_side_effects=True,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n"},"after_code":{"kind":"string","value":"# Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.\n# SPDX-License-Identifier: Apache-2.0\n#\n# Licensed under the Apache License, Version 2.0 (the \"License\");\n# you may not use this file except in compliance with the License.\n# You may obtain a copy of the License at\n#\n# http://www.apache.org/licenses/LICENSE-2.0\n#\n# Unless required by applicable law or agreed to in writing, software\n# distributed under the License is distributed on an \"AS IS\" BASIS,\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n# See the License for the specific language governing permissions and\n# limitations under the License.\n\n# Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.\n# SPDX-License-Identifier: BSD-3-Clause\n\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions are met:\n\n# 1. Redistributions of source code must retain the above copyright notice, this\n# list of conditions and the following disclaimer.\n\n# 2. Redistributions in binary form must reproduce the above copyright notice,\n# this list of conditions and the following disclaimer in the documentation\n# and/or other materials provided with the distribution.\n\n# 3. Neither the name of the copyright holder nor the names of its\n# contributors may be used to endorse or promote products derived from\n# this software without specific prior written permission.\n\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n# This file is copied and modified from cutlass https://github.com/NVIDIA/cutlass/blob/main/python/CuTeDSL/cutlass/cute/core.py\n\nimport ctypes\nimport functools\nfrom typing import Union\n\nimport cutlass\nimport cutlass._mlir.dialects.cute as _cute_ir\nimport cutlass.cute as cute\nfrom cutlass._mlir import ir\nfrom cutlass._mlir.dialects import llvm, nvvm\nfrom cutlass.cute.typing import AddressSpace, Numeric, Pointer, Type\nfrom cutlass.cutlass_dsl import T, dsl_user_op\n\n\n# WAR for CuTeDSL make_ptr implementation\nclass _Pointer(Pointer):\n \"\"\"Represents a runtime pointer that can interoperate with various data structures,\n including numpy arrays and device memory.\n\n Args:\n pointer (int or pointer-like object): The pointer to the data.\n dtype (Type): Data type of the elements pointed to.\n mem_space (_cute_ir.AddressSpace, optional): Memory space where the pointer resides. Defaults to generic.\n assumed_align (int, optional): Alignment of the input pointer in bytes. Defaults to None.\n\n Attributes:\n _pointer: The underlying pointer.\n _dtype: Data type of the elements.\n _addr_space: Memory space of the pointer.\n _assumed_align: Alignment of the pointer in bytes.\n _desc: C-type descriptor for the pointer.\n _c_pointer: C-compatible pointer representation.\n \"\"\"\n\n def __init__(\n self,\n pointer,\n dtype,\n mem_space: _cute_ir.AddressSpace = _cute_ir.AddressSpace.generic,\n assumed_align=None,\n ):\n self._pointer = pointer\n self._dtype = dtype\n self._addr_space = mem_space\n\n if assumed_align is None:\n self._assumed_align = dtype.width // 8\n else:\n self._assumed_align = assumed_align\n\n self._desc = None\n self._c_pointer = None\n assert int(self._pointer) % self._assumed_align == 0, (\n f\"pointer must be {self._assumed_align} bytes aligned\"\n )\n\n def size_in_bytes(self) -> int:\n return ctypes.sizeof(ctypes.c_void_p(int(self._pointer)))\n\n def __get_mlir_types__(self):\n return [self.mlir_type]\n\n def __c_pointers__(self):\n if self._c_pointer is None:\n self._desc = ctypes.c_void_p(int(self._pointer))\n self._c_pointer = ctypes.addressof(self._desc)\n return [self._c_pointer]\n\n def __new_from_mlir_values__(self, values):\n assert len(values) == 1\n return values[0]\n\n # Move mlir Type out of __init__ to decouple with mlir Context\n @property\n def mlir_type(self) -> ir.Type:\n return _cute_ir.PtrType.get(\n self._dtype.mlir_type, self._addr_space, self._assumed_align\n )\n\n @property\n def dtype(self) -> Type[Numeric]:\n return self._dtype\n\n @property\n def memspace(self):\n return self._addr_space\n\n def align(self, min_align: int, *, loc=None, ip=None) -> Pointer:\n raise NotImplementedError(\"align is not supported in runtime\")\n\n def verify(self, expected_py_type):\n if expected_py_type is Pointer or (\n isinstance(expected_py_type, ir.Value) and expected_py_type.ty is Pointer\n ):\n return True\n\n return False\n\n def __str__(self) -> str:\n return f\"Ptr<0x{int(self._pointer):016x}@{self._addr_space}>\"\n\n def __repr__(self):\n return self.__str__()\n\n\ndef make_ptr(\n dtype: Type[Numeric],\n value: Union[int, ctypes._Pointer],\n mem_space: AddressSpace = AddressSpace.generic,\n assumed_align=None,\n) -> Pointer:\n \"\"\"Creates a pointer from a memory address.\n\n Args:\n dtype (Type[Numeric]): Data type of the pointer elements.\n value (Union[int, ctypes._Pointer]): Memory address as an integer or ctypes pointer.\n mem_space (AddressSpace, optional): Memory address space. Defaults to AddressSpace.generic.\n assumed_align (int, optional): Alignment in bytes. Defaults to None.\n\n Returns:\n Pointer: A pointer object.\n\n Example:\n ```python\n import numpy as np\n import ctypes\n from cutlass import Float32\n from cutlass.cute.runtime import make_ptr\n\n # Create a numpy array\n a = np.random.randn(16, 32).astype(np.float32)\n # Get pointer address as ctypes pointer\n ptr_address = a.ctypes.data_as(ctypes.POINTER(ctypes.c_float))\n # Create pointer from address\n y = make_ptr(cutlass.Float32, ptr_address)\n ```\n \"\"\"\n # check if value is int or ctypes.POINTER\n if isinstance(value, int):\n address_value = value\n elif isinstance(value, ctypes._Pointer):\n # get address value\n address_value = ctypes.cast(value, ctypes.c_void_p).value\n assert address_value is not None, \"Pointer address is None\"\n else:\n raise TypeError(\n f\"Expect int or ctypes.POINTER for value but got {type(value)=}\"\n )\n\n return _Pointer(address_value, dtype, mem_space, assumed_align=assumed_align)\n\n\ndef is_power_of_2(x: int) -> bool:\n return x > 0 and (x & (x - 1)) == 0\n\n\n@functools.lru_cache(maxsize=None)\ndef _nvvm_fmin_needs_res():\n import inspect\n\n return \"res\" in inspect.signature(nvvm.fmin).parameters\n\n\n@dsl_user_op\ndef fmin(\n a: Union[float, cutlass.Float32],\n b: Union[float, cutlass.Float32],\n *,\n nan=False,\n loc=None,\n ip=None,\n) -> cutlass.Float32:\n a_val = cutlass.Float32(a).ir_value(loc=loc, ip=ip)\n b_val = cutlass.Float32(b).ir_value(loc=loc, ip=ip)\n if _nvvm_fmin_needs_res():\n # CUDA 12: nvvm.fmin(res, a, b, ...)\n result = nvvm.fmin(T.f32(), a_val, b_val, nan=nan, loc=loc, ip=ip)\n else:\n # CUDA 13: nvvm.fmin(a, b, ...)\n result = nvvm.fmin(a_val, b_val, nan=nan, loc=loc, ip=ip)\n return cutlass.Float32(result)\n\n\ndef sigmoid_f32(\n a: Union[float, cutlass.Float32], fastmath: bool = False\n) -> Union[float, cutlass.Float32]:\n \"\"\"\n Compute the sigmoid of the input tensor.\n \"\"\"\n return cute.arch.rcp_approx(1.0 + cute.math.exp(-a, fastmath=fastmath))\n\n\ndef silu_f32(\n a: Union[float, cutlass.Float32], fastmath: bool = False\n) -> Union[float, cutlass.Float32]:\n \"\"\"\n Compute the silu of the input tensor.\n \"\"\"\n return a * sigmoid_f32(a, fastmath=fastmath)\n\n\ndef tanh_f32(\n a: Union[float, cutlass.Float32], fastmath: bool = False\n) -> Union[float, cutlass.Float32]:\n \"\"\"Compute tanh from the existing sigmoid primitive.\"\"\"\n return cutlass.Float32(2.0) * sigmoid_f32(\n cutlass.Float32(2.0) * a, fastmath=fastmath\n ) - cutlass.Float32(1.0)\n\n\ndef f32_reciprocal(value: float) -> float:\n \"\"\"Return ``1 / fp32(value)``, rounded to fp32.\n\n The reciprocal must come from the same fp32 value the kernel multiplies back\n in. Taking it from the unrounded Python float instead can differ by 1 ulp for\n betas that are not fp32-exact. (f64 carries at least 2p+2 bits for p=24, so\n computing the quotient in f64 and rounding once to fp32 is correctly rounded.)\n \"\"\"\n beta_f32 = ctypes.c_float(float(value)).value\n return ctypes.c_float(1.0 / beta_f32).value\n\n\ndef situ_f32(\n a: Union[float, cutlass.Float32],\n beta: Union[float, cutlass.Float32],\n fastmath: bool = False,\n) -> Union[float, cutlass.Float32]:\n \"\"\"Compute SiTU: beta * tanh(x / beta) * sigmoid(x).\"\"\"\n x = cutlass.Float32(a)\n beta_f32 = cutlass.Float32(beta)\n # Multiply by the reciprocal: `x / beta` is a per-element div.rn.f32 the backend\n # cannot strength-reduce (1/25.0 is inexact) nor hoist (varying numerator).\n if isinstance(beta, (float, int)):\n inv_beta = cutlass.Float32(f32_reciprocal(beta))\n else:\n inv_beta = cutlass.Float32(1.0) / beta_f32\n return (\n beta_f32\n * tanh_f32(x * inv_beta, fastmath=fastmath)\n * sigmoid_f32(x, fastmath=fastmath)\n )\n\n\ndef gelu_tanh_f32(\n a: Union[float, cutlass.Float32], fastmath: bool = False\n) -> Union[float, cutlass.Float32]:\n \"\"\"Compute GELU using the tanh approximation.\"\"\"\n x = cutlass.Float32(a)\n inner = cutlass.Float32(0.7978845608028654) * (\n x + cutlass.Float32(0.044715) * x * x * x\n )\n return (\n cutlass.Float32(0.5)\n * x\n * (cutlass.Float32(1.0) + tanh_f32(inner, fastmath=fastmath))\n )\n\n\n# TODO(zhichenj): try to move these to NVVM wrapper or helper functions\n@dsl_user_op\ndef vectorized_atomic_add_bf16x8(\n rOut_epi_packed, scatter_out_offset, loc=None, ip=None\n):\n llvm.inline_asm(\n None,\n [\n scatter_out_offset.iterator.llvm_ptr,\n llvm.bitcast(T.i32(), rOut_epi_packed[0, None].load().ir_value()),\n llvm.bitcast(T.i32(), rOut_epi_packed[1, None].load().ir_value()),\n llvm.bitcast(T.i32(), rOut_epi_packed[2, None].load().ir_value()),\n llvm.bitcast(T.i32(), rOut_epi_packed[3, None].load().ir_value()),\n ],\n \"red.global.v4.bf16x2.add.noftz [$0], {$1, $2, $3, $4};\",\n \"l,r,r,r,r\",\n has_side_effects=True,\n loc=loc,\n ip=ip,\n )\n\n\n@dsl_user_op\ndef vectorized_atomic_add_fp32x2(\n rOut_epi_packed, scatter_out_offset, loc=None, ip=None\n):\n llvm.inline_asm(\n None,\n [\n scatter_out_offset.iterator.llvm_ptr,\n rOut_epi_packed[0].ir_value(),\n rOut_epi_packed[1].ir_value(),\n ],\n \"red.global.v2.f32.add [$0], {$1, $2};\",\n \"l,f,f\",\n has_side_effects=True,\n loc=loc,\n ip=ip,\n )\n\n\n@dsl_user_op\ndef atomic_add_func(rOut_epi_packed, scatter_out_offset, loc=None, ip=None):\n if cutlass.const_expr(rOut_epi_packed.dtype == cutlass.Float32):\n llvm.inline_asm(\n None,\n [\n scatter_out_offset.iterator.llvm_ptr,\n rOut_epi_packed.ir_value(),\n ],\n \"red.global.add.f32 [$0], $1;\",\n \"l,f\",\n has_side_effects=True,\n loc=loc,\n ip=ip,\n )\n elif cutlass.const_expr(rOut_epi_packed.dtype == cutlass.BFloat16):\n llvm.inline_asm(\n None,\n [\n scatter_out_offset.iterator.llvm_ptr,\n llvm.bitcast(T.i16(), rOut_epi_packed.ir_value()),\n ],\n \"red.add.noftz.bf16 [$0], $1;\",\n \"l,h\",\n has_side_effects=True,\n loc=loc,\n ip=ip,\n )\n\n\n@dsl_user_op\ndef blk_copy(dst_gemm, src_smem, size, loc=None, ip=None):\n llvm.inline_asm(\n None,\n [\n dst_gemm.iterator.toint(loc=loc, ip=ip).ir_value(loc=loc, ip=ip),\n src_smem.iterator.toint(loc=loc, ip=ip).ir_value(loc=loc, ip=ip),\n size.ir_value(loc=loc, ip=ip),\n ],\n \"cp.async.bulk.global.shared::cta.bulk_group [$0], [$1], $2;\",\n \"l,r,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n\n@dsl_user_op\ndef blk_reduce_bf16(dst_gemm, src_smem, size, loc=None, ip=None):\n llvm.inline_asm(\n None,\n [\n dst_gemm.iterator.llvm_ptr,\n src_smem.iterator.llvm_ptr,\n size.ir_value(),\n ],\n \"cp.reduce.async.bulk.global.shared::cta.bulk_group.add.noftz.bf16 [$0], [$1], $2;\",\n \"l,l,r\",\n has_side_effects=True,\n loc=loc,\n ip=ip,\n )\n\n\n@dsl_user_op\ndef blk_reduce_fp32(dst_gemm, src_smem, size, loc=None, ip=None):\n llvm.inline_asm(\n None,\n [\n dst_gemm.iterator.llvm_ptr,\n src_smem.iterator.llvm_ptr,\n size.ir_value(),\n ],\n \"cp.reduce.async.bulk.global.shared::cta.bulk_group.add.f32 [$0], [$1], $2;\",\n \"l,l,r\",\n has_side_effects=True,\n loc=loc,\n ip=ip,\n )\n\n\n@dsl_user_op\ndef blk_reduce_fp16(dst_gemm, src_smem, size, loc=None, ip=None):\n llvm.inline_asm(\n None,\n [\n dst_gemm.iterator.llvm_ptr,\n src_smem.iterator.llvm_ptr,\n size.ir_value(),\n ],\n \"cp.reduce.async.bulk.global.shared::cta.bulk_group.noftz.f16 [$0], [$1], $2;\",\n \"l,l,r\",\n has_side_effects=True,\n loc=loc,\n ip=ip,\n )\n\n\n@dsl_user_op\ndef griddepcontrol_wait(*, loc=None, ip=None) -> None:\n \"\"\"\n This instruction is used to wait for the previous kernel's grid ending\n (all blocks of the previous kernel have finished and memflushed), i.e.,\n the instruction after this instruction will not be issued until the previous\n grid has finished.\n \"\"\"\n llvm.inline_asm(\n res=None,\n operands_=[],\n asm_string=\"griddepcontrol.wait;\",\n constraints=\"\",\n has_side_effects=True,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n\n@dsl_user_op\ndef griddepcontrol_launch_dependents(*, loc=None, ip=None) -> None:\n \"\"\"\n Issuing the launch_dependents instruction hints a dependent kernel to launch earlier.\n launch_dependents doesn't impact the functionality but the performance:\n Launching a dependent kernel too early can compete with current kernels,\n while launching too late can lead to a long latency.\n \"\"\"\n llvm.inline_asm(\n res=None,\n operands_=[],\n asm_string=\"griddepcontrol.launch_dependents;\",\n constraints=\"\",\n has_side_effects=True,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n"},"diff":{"kind":"string","value":"--- flashinfer/fused_moe/cute_dsl/blackwell/utils.py\n+++ flashinfer/fused_moe/cute_dsl/blackwell/utils.py\n@@ -252,6 +252,18 @@\n ) - cutlass.Float32(1.0)\n \n \n+def f32_reciprocal(value: float) -> float:\n+ \"\"\"Return ``1 / fp32(value)``, rounded to fp32.\n+\n+ The reciprocal must come from the same fp32 value the kernel multiplies back\n+ in. Taking it from the unrounded Python float instead can differ by 1 ulp for\n+ betas that are not fp32-exact. (f64 carries at least 2p+2 bits for p=24, so\n+ computing the quotient in f64 and rounding once to fp32 is correctly rounded.)\n+ \"\"\"\n+ beta_f32 = ctypes.c_float(float(value)).value\n+ return ctypes.c_float(1.0 / beta_f32).value\n+\n+\n def situ_f32(\n a: Union[float, cutlass.Float32],\n beta: Union[float, cutlass.Float32],\n@@ -260,9 +272,15 @@\n \"\"\"Compute SiTU: beta * tanh(x / beta) * sigmoid(x).\"\"\"\n x = cutlass.Float32(a)\n beta_f32 = cutlass.Float32(beta)\n+ # Multiply by the reciprocal: `x / beta` is a per-element div.rn.f32 the backend\n+ # cannot strength-reduce (1/25.0 is inexact) nor hoist (varying numerator).\n+ if isinstance(beta, (float, int)):\n+ inv_beta = cutlass.Float32(f32_reciprocal(beta))\n+ else:\n+ inv_beta = cutlass.Float32(1.0) / beta_f32\n return (\n beta_f32\n- * tanh_f32(x / beta_f32, fastmath=fastmath)\n+ * tanh_f32(x * inv_beta, fastmath=fastmath)\n * sigmoid_f32(x, fastmath=fastmath)\n )\n "},"lines_added":{"kind":"number","value":19,"string":"19"},"lines_removed":{"kind":"number","value":1,"string":"1"},"files_in_commit":{"kind":"number","value":2,"string":"2"},"models_mentioned":{"kind":"list like","value":["kimi"],"string":"[\n \"kimi\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["B200","BLACKWELL"],"string":"[\n \"B200\",\n \"BLACKWELL\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cute_dsl kernel file from flashinfer (flashinfer/fused_moe/cute_dsl/blackwell/utils.py).\n\nGoal: perf(moe): fold the SiTU beta reciprocal in the CuTe DSL MoE epilogue\nTarget hardware: B200, BLACKWELL\nTarget models: kimi\n\nCurrent file:\n```python\n# Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.\n# SPDX-License-Identifier: Apache-2.0\n#\n# Licensed under the Apache License, Version 2.0 (the \"License\");\n# you may not use this file except in compliance with the License.\n# You may obtain a copy of the License at\n#\n# http://www.apache.org/licenses/LICENSE-2.0\n#\n# Unless required by applicable law or agreed to in writing, software\n# distributed under the License is distributed on an \"AS IS\" BASIS,\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n# See the License for the specific language governing permissions and\n# limitations under the License.\n\n# Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.\n# SPDX-License-Identifier: BSD-3-Clause\n\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions are met:\n\n# 1. Redistributions of source code must retain the above copyright notice, this\n# list of conditions and the following disclaimer.\n\n# 2. Redistributions in binary form must reproduce the above copyright notice,\n# this list of conditions and the following disclaimer in the documentation\n# and/or other materials provided with the distribution.\n\n# 3. Neither the name of the copyright holder nor the names of its\n# contributors may be used to endorse or promote products derived from\n# this software without specific prior written permission.\n\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n# This file is copied and modified from cutlass https://github.com/NVIDIA/cutlass/blob/main/python/CuTeDSL/cutlass/cute/core.py\n\nimport ctypes\nimport functools\nfrom typing import Union\n\nimport cutlass\nimport cutlass._mlir.dialects.cute as _cute_ir\nimport cutlass.cute as cute\nfrom cutlass._mlir import ir\nfrom cutlass._mlir.dialects import llvm, nvvm\nfrom cutlass.cute.typing import AddressSpace, Numeric, Pointer, Type\nfrom cutlass.cutlass_dsl import T, dsl_user_op\n\n\n# WAR for CuTeDSL make_ptr implementation\nclass _Pointer(Pointer):\n \"\"\"Represents a runtime pointer that can interoperate with various data structures,\n including numpy arrays and device memory.\n\n Args:\n pointer (int or pointer-like object): The pointer to the data.\n dtype (Type): Data type of the elements pointed to.\n mem_space (_cute_ir.AddressSpace, optional): Memory space where the pointer resides. Defaults to generic.\n assumed_align (int, optional): Alignment of the input pointer in bytes. Defaults to None.\n\n Attributes:\n _pointer: The underlying pointer.\n _dtype: Data type of the elements.\n _addr_space: Memory space of the pointer.\n _assumed_align: Alignment of the pointer in bytes.\n _desc: C-type descriptor for the pointer.\n _c_pointer: C-compatible pointer representation.\n \"\"\"\n\n def __init__(\n self,\n pointer,\n dtype,\n mem_space: _cute_ir.AddressSpace = _cute_ir.AddressSpace.generic,\n assumed_align=None,\n ):\n self._pointer = pointer\n self._dtype = dtype\n self._addr_space = mem_space\n\n if assumed_align is None:\n self._assumed_align = dtype.width // 8\n else:\n self._assumed_align = assumed_align\n\n self._desc = None\n self._c_pointer = None\n assert int(self._pointer) % self._assumed_align == 0, (\n f\"pointer must be {self._assumed_align} bytes aligned\"\n )\n\n def size_in_bytes(self) -> int:\n return ctypes.sizeof(ctypes.c_void_p(int(self._pointer)))\n\n def __get_mlir_types__(self):\n return [self.mlir_type]\n\n def __c_pointers__(self):\n if self._c_pointer is None:\n self._desc = ctypes.c_void_p(int(self._pointer))\n self._c_pointer = ctypes.addressof(self._desc)\n return [self._c_pointer]\n\n def __new_from_mlir_values__(self, values):\n assert len(values) == 1\n return values[0]\n\n # Move mlir Type out of __init__ to decouple with mlir Context\n @property\n def mlir_type(self) -> ir.Type:\n return _cute_ir.PtrType.get(\n self._dtype.mlir_type, self._addr_space, self._assumed_align\n )\n\n @property\n def dtype(self) -> Type[Numeric]:\n return self._dtype\n\n @property\n def memspace(self):\n return self._addr_space\n\n def align(self, min_align: int, *, loc=None, ip=None) -> Pointer:\n raise NotImplementedError(\"align is not supported in runtime\")\n\n def verify(self, expected_py_type):\n if expected_py_type is Pointer or (\n isinstance(expected_py_type, ir.Value) and expected_py_type.ty is Pointer\n ):\n return True\n\n return False\n\n def __str__(self) -> str:\n return f\"Ptr<0x{int(self._pointer):016x}@{self._addr_space}>\"\n\n def __repr__(self):\n return self.__str__()\n\n\ndef make_ptr(\n dtype: Type[Numeric],\n value: Union[int, ctypes._Pointer],\n mem_space: AddressSpace = AddressSpace.generic,\n assumed_align=None,\n) -> Pointer:\n \"\"\"Creates a pointer from a memory address.\n\n Args:\n dtype (Type[Numeric]): Data type of the pointer elements.\n value (Union[int, ctypes._Pointer]): Memory address as an integer or ctypes pointer.\n mem_space (AddressSpace, optional): Memory address space. Defaults to AddressSpace.generic.\n assumed_align (int, optional): Alignment in bytes. Defaults to None.\n\n Returns:\n Pointer: A pointer object.\n\n Example:\n ```python\n import numpy as np\n import ctypes\n from cutlass import Float32\n from cutlass.cute.runtime import make_ptr\n\n # Create a numpy array\n a = np.random.randn(16, 32).astype(np.float32)\n # Get pointer address as ctypes pointer\n ptr_address = a.ctypes.data_as(ctypes.POINTER(ctypes.c_float))\n # Create pointer from address\n y = make_ptr(cutlass.Float32, ptr_address)\n ```\n \"\"\"\n # check if value is int or ctypes.POINTER\n if isinstance(value, int):\n address_value = value\n elif isinstance(value, ctypes._Pointer):\n # get address value\n address_value = ctypes.cast(value, ctypes.c_void_p).value\n assert address_value is not None, \"Pointer address is None\"\n else:\n raise TypeError(\n f\"Expect int or ctypes.POINTER for value but got {type(value)=}\"\n )\n\n return _Pointer(address_value, dtype, mem_space, assumed_align=assumed_align)\n\n\ndef is_power_of_2(x: int) -> bool:\n return x > 0 and (x & (x - 1)) == 0\n\n\n@functools.lru_cache(maxsize=None)\ndef _nvvm_fmin_needs_res():\n import inspect\n\n return \"res\" in inspect.signature(nvvm.fmin).parameters\n\n\n@dsl_user_op\ndef fmin(\n a: Union[float, cutlass.Float32],\n b: Union[float, cutlass.Float32],\n *,\n nan=False,\n loc=None,\n ip=None,\n) -> cutlass.Float32:\n a_val = cutlass.Float32(a).ir_value(loc=loc, ip=ip)\n b_val = cutlass.Float32(b).ir_value(loc=loc, ip=ip)\n if _nvvm_fmin_needs_res():\n # CUDA 12: nvvm.fmin(res, a, b, ...)\n result = nvvm.fmin(T.f32(), a_val, b_val, nan=nan, loc=loc, ip=ip)\n else:\n # CUDA 13: nvvm.fmin(a, b, ...)\n result = nvvm.fmin(a_val, b_val, nan=nan, loc=loc, ip=ip)\n return cutlass.Float32(result)\n\n\ndef sigmoid_f32(\n a: Union[float, cutlass.Float32], fastmath: bool = False\n) -> Union[float, cutlass.Float32]:\n \"\"\"\n Compute the sigmoid of the input tensor.\n \"\"\"\n return cute.arch.rcp_approx(1.0 + cute.math.exp(-a, fastmath=fastmath))\n\n\ndef silu_f32(\n a: Union[float, cutlass.Float32], fastmath: bool = False\n) -> Union[float, cutlass.Float32]:\n \"\"\"\n Compute the silu of the input tensor.\n \"\"\"\n return a * sigmoid_f32(a, fastmath=fastmath)\n\n\ndef tanh_f32(\n a: Union[float, cutlass.Float32], fastmath: bool = False\n) -> Union[float, cutlass.Float32]:\n \"\"\"Compute tanh from the existing sigmoid primitive.\"\"\"\n return cutlass.Float32(2.0) * sigmoid_f32(\n cutlass.Float32(2.0) * a, fastmath=fastmath\n ) - cutlass.Float32(1.0)\n\n\ndef situ_f32(\n a: Union[float, cutlass.Float32],\n beta: Union[float, cutlass.Float32],\n fastmath: bool = False,\n) -> Union[float, cutlass.Float32]:\n \"\"\"Compute SiTU: beta * tanh(x / beta) * sigmoid(x).\"\"\"\n x = cutlass.Float32(a)\n beta_f32 = cutlass.Float32(beta)\n return (\n beta_f32\n * tanh_f32(x / beta_f32, fastmath=fastmath)\n * sigmoid_f32(x, fastmath=fastmath)\n )\n\n\ndef gelu_tanh_f32(\n a: Union[float, cutlass.Float32], fastmath: bool = False\n) -> Union[float, cutlass.Float32]:\n \"\"\"Compute GELU using the tanh approximation.\"\"\"\n x = cutlass.Float32(a)\n inner = cutlass.Float32(0.7978845608028654) * (\n x + cutlass.Float32(0.044715) * x * x * x\n )\n return (\n cutlass.Float32(0.5)\n * x\n * (cutlass.Float32(1.0) + tanh_f32(inner, fastmath=fastmath))\n )\n\n\n# TODO(zhichenj): try to move these to NVVM wrapper or helper functions\n@dsl_user_op\ndef vectorized_atomic_add_bf16x8(\n rOut_epi_packed, scatter_out_offset, loc=None, ip=None\n):\n llvm.inline_asm(\n None,\n [\n scatter_out_offset.iterator.llvm_ptr,\n llvm.bitcast(T.i32(), rOut_epi_packed[0, None].load().ir_value()),\n llvm.bitcast(T.i32(), rOut_epi_packed[1, None].load().ir_value()),\n llvm.bitcast(T.i32(), rOut_epi_packed[2, None].load().ir_value()),\n llvm.bitcast(T.i32(), rOut_epi_packed[3, None].load().ir_value()),\n ],\n \"red.global.v4.bf16x2.add.noftz [$0], {$1, $2, $3, $4};\",\n \"l,r,r,r,r\",\n has_side_effects=True,\n loc=loc,\n ip=ip,\n )\n\n\n@dsl_user_op\ndef vectorized_atomic_add_fp32x2(\n rOut_epi_packed, scatter_out_offset, loc=None, ip=None\n):\n llvm.inline_asm(\n None,\n [\n scatter_out_offset.iterator.llvm_ptr,\n rOut_epi_packed[0].ir_value(),\n rOut_epi_packed[1].ir_value(),\n ],\n \"red.global.v2.f32.add [$0], {$1, $2};\",\n \"l,f,f\",\n has_side_effects=True,\n loc=loc,\n ip=ip,\n )\n\n\n@dsl_user_op\ndef atomic_add_func(rOut_epi_packed, scatter_out_offset, loc=None, ip=None):\n if cutlass.const_expr(rOut_epi_packed.dtype == cutlass.Float32):\n llvm.inline_asm(\n None,\n [\n scatter_out_offset.iterator.llvm_ptr,\n rOut_epi_packed.ir_value(),\n ],\n \"red.global.add.f32 [$0], $1;\",\n \"l,f\",\n has_side_effects=True,\n loc=loc,\n ip=ip,\n )\n elif cutlass.const_expr(rOut_epi_packed.dtype == cutlass.BFloat16):\n llvm.inline_asm(\n None,\n [\n scatter_out_offset.iterator.llvm_ptr,\n llvm.bitcast(T.i16(), rOut_epi_packed.ir_value()),\n ],\n \"red.add.noftz.bf16 [$0], $1;\",\n \"l,h\",\n has_side_effects=True,\n loc=loc,\n ip=ip,\n )\n\n\n@dsl_user_op\ndef blk_copy(dst_gemm, src_smem, size, loc=None, ip=None):\n llvm.inline_asm(\n None,\n [\n dst_gemm.iterator.toint(loc=loc, ip=ip).ir_value(loc=loc, ip=ip),\n src_smem.iterator.toint(loc=loc, ip=ip).ir_value(loc=loc, ip=ip),\n size.ir_value(loc=loc, ip=ip),\n ],\n \"cp.async.bulk.global.shared::cta.bulk_group [$0], [$1], $2;\",\n \"l,r,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n\n@dsl_user_op\ndef blk_reduce_bf16(dst_gemm, src_smem, size, loc=None, ip=None):\n llvm.inline_asm(\n None,\n [\n dst_gemm.iterator.llvm_ptr,\n src_smem.iterator.llvm_ptr,\n size.ir_value(),\n ],\n \"cp.reduce.async.bulk.global.shared::cta.bulk_group.add.noftz.bf16 [$0], [$1], $2;\",\n \"l,l,r\",\n has_side_effects=True,\n loc=loc,\n ip=ip,\n )\n\n\n@dsl_user_op\ndef blk_reduce_fp32(dst_gemm, src_smem, size, loc=None, ip=None):\n llvm.inline_asm(\n None,\n [\n dst_gemm.iterator.llvm_ptr,\n src_smem.iterator.llvm_ptr,\n size.ir_value(),\n ],\n \"cp.reduce.async.bulk.global.shared::cta.bulk_group.add.f32 [$0], [$1], $2;\",\n \"l,l,r\",\n has_side_effects=True,\n loc=loc,\n ip=ip,\n )\n\n\n@dsl_user_op\ndef blk_reduce_fp16(dst_gemm, src_smem, size, loc=None, ip=None):\n llvm.inline_asm(\n None,\n [\n dst_gemm.iterator.llvm_ptr,\n src_smem.iterator.llvm_ptr,\n size.ir_value(),\n ],\n \"cp.reduce.async.bulk.global.shared::cta.bulk_group.noftz.f16 [$0], [$1], $2;\",\n \"l,l,r\",\n has_side_effects=True,\n loc=loc,\n ip=ip,\n )\n\n\n@dsl_user_op\ndef griddepcontrol_wait(*, loc=None, ip=None) -> None:\n \"\"\"\n This instruction is used to wait for the previous kernel's grid ending\n (all blocks of the previous kernel have finished and memflushed), i.e.,\n the instruction after this instruction will not be issued until the previous\n grid has finished.\n \"\"\"\n llvm.inline_asm(\n res=None,\n operands_=[],\n asm_string=\"griddepcontrol.wait;\",\n constraints=\"\",\n has_side_effects=True,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n\n@dsl_user_op\ndef griddepcontrol_launch_dependents(*, loc=None, ip=None) -> None:\n \"\"\"\n Issuing the launch_dependents instruction hints a dependent kernel to launch earlier.\n launch_dependents doesn't impact the functionality but the performance:\n Launching a dependent kernel too early can compete with current kernels,\n while launching too late can lead to a long latency.\n \"\"\"\n llvm.inline_asm(\n res=None,\n operands_=[],\n asm_string=\"griddepcontrol.launch_dependents;\",\n constraints=\"\",\n has_side_effects=True,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"`x / beta` in the SiTU gate and up branches lowers to a per-element\n`div.rn.f32`: folding it to `x * (1/beta)` is only legal when `1/beta` is\nexact, which the SiTU betas (e.g. Kimi-K3's 25.0) are not. Compute the\nreciprocal at trace time and multiply instead.\n\n`f32_reciprocal` derives it from the fp32 beta the kernel multiplies back in,\nso `x * inv_beta` stays consistent with `x / beta_f32`; taking the reciprocal\nof the unrounded Python float can differ by 1 ulp when beta is not fp32-exact.\n\nKimi-K3 MoE (E=896, topK=16, hidden=3584, intermediate=3072) on one B200 at\n1000 W, NVFP4, pre-routed, autotuned, microseconds, best of 3 repeats of\n50 timed iters:\n\n| tokens | 1 | 8 | 64 | 512 | 2048 | 4096 | 8192 |\n|---|---|---|---|---|---|---|---|\n| SiTU before | 123 | 673 | 3167 | 4744 | 4779 | 4845 | 7826 |\n| SiTU after | 77 | 363 | 1734 | 2702 | 2914 | 3011 | 4992 |\n| SwiGLU | 75 | 360 | 1724 | 2677 | 2761 | 2998 | 4361 |\n\nSiTU now lands within 1-6% of SwiGLU on the same kernel through 4096 tokens.\n\n`pytest tests/moe/test_cute_dsl_fused_moe.py -k situ` is unchanged (7 passed,\n2 failed; both failures pre-exist on main)\n<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\n<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [ ] Tests have been added or updated as needed.\n- [ ] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc. -->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n## Summary by CodeRabbit\n\n* **Performance**\n * Improved SiTU activation calculations by replacing repeated division with precomputed reciprocal multiplication.\n * Optimized both vectorized and scalar calculation paths while preserving existing behavior.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": \"Kimi-K3 MoE\", \"shape\": \"E=896,topK=16,hidden=3584,intermediate=3072\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 123, \"optimized\": 77, \"stated_speedup\": null, \"speedup\": 1.5974}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": \"Kimi-K3 MoE\", \"shape\": \"E=896,topK=16,hidden=3584,intermediate=3072\", \"batch_size\": 8, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 673, \"optimized\": 363, \"stated_speedup\": null, \"speedup\": 1.854}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": \"Kimi-K3 MoE\", \"shape\": \"E=896,topK=16,hidden=3584,intermediate=3072\", \"batch_size\": 64, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 3167, \"optimized\": 1734, \"stated_speedup\": null, \"speedup\": 1.8264}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": \"Kimi-K3 MoE\", \"shape\": \"E=896,topK=16,hidden=3584,intermediate=3072\", \"batch_size\": 512, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 4744, \"optimized\": 2702, \"stated_speedup\": null, \"speedup\": 1.7557}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": \"Kimi-K3 MoE\", \"shape\": \"E=896,topK=16,hidden=3584,intermediate=3072\", \"batch_size\": 2048, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 4779, \"optimized\": 2914, \"stated_speedup\": null, \"speedup\": 1.64}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": \"Kimi-K3 MoE\", \"shape\": \"E=896,topK=16,hidden=3584,intermediate=3072\", \"batch_size\": 4096, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 4845, \"optimized\": 3011, \"stated_speedup\": null, \"speedup\": 1.6091}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": \"Kimi-K3 MoE\", \"shape\": \"E=896,topK=16,hidden=3584,intermediate=3072\", \"batch_size\": 8192, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 7826, \"optimized\": 4992, \"stated_speedup\": null, \"speedup\": 1.5677}]"},"kernel_speedup":{"kind":"number","value":1.64,"string":"1.64"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1086,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"ba6bf4e5b63b299952afaa768c1caa863829f309"},"date":{"kind":"string","value":"2026-08-14T01:59:27+08:00"},"pr_number":{"kind":"number","value":4444,"string":"4,444"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/4444"},"title":{"kind":"string","value":"perf(gdn): reuse pretranspose kernels across pool capacity and stride (#4444)"},"message":{"kind":"string","value":"perf(gdn): reuse pretranspose kernels across pool capacity and stride (#4444)\n\n## 📌 Description\n\nMake the leading pool dimension of the GDN pretranspose path dynamic:\n\n- Treat pool capacity and `stride[0]` as runtime values.\n- Keep `HV/V/K` and inner strides compile-time static.\n- Remove pool capacity and leading stride from the compilation cache\nkey.\n- Preserve 64-bit pool-offset arithmetic.\n\nThis allows one compiled kernel to be reused across non-contiguous state\npools with different capacities and leading strides.\n\n## 🔍 Related Issues\n\nPartially addresses #4110.\n\n## 🚀 Pull Request Checklist\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit`.\n- [x] I have installed the hooks.\n- [x] I have run `pre-commit run --all-files`.\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All relevant tests are passing.\n\nValidated on H800/SM90a and RTX 5090/SM120, including non-contiguous\npools, compile reuse, and large 64-bit offsets. No steady-state\nregression was observed; cold compilation time was reduced by\napproximately 62%.\n\n## Reviewer Notes\n\nOnly the outer pool mode is dynamic. Inner dimensions and strides remain\nstatic for kernel specialization.\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n\n## Summary by CodeRabbit\n\n* **Performance**\n* Improved pretranspose kernel reuse across different pool capacities\nand outer memory layouts, reducing unnecessary recompilation.\n* Preserved separate handling for layouts with differing inner strides.\n\n* **Reliability**\n* Added validation to reject pool slot strides that are not properly\naligned for efficient data transfer.\n\n* **Tests**\n* Expanded coverage for cache reuse, layout variations, alignment\nvalidation, and environments where the optional kernel is unavailable.\n\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n\nSigned-off-by: 梁厚宏 <2695316095@qq.com>"},"path":{"kind":"string","value":"flashinfer/gdn_kernels/gdn_decode_pretranspose.py"},"language":{"kind":"string","value":"cute_dsl"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"\"\"\"\nCopyright (c) 2025 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nGated Delta Rule Decode Kernel - Pretranspose (V-major / K-last) Layout\n========================================================================\n\nCuTe-DSL implementation of GDN decode with state layout [B*HV, V, K].\nUses TMA pipelining and vectorized memory access for T=1 decode.\n\"\"\"\n\nimport functools\nfrom typing import Optional\n\nimport torch\nimport cutlass\nimport cutlass.cute as cute\nfrom cutlass.cute.nvgpu import cpasync\nfrom cutlass.cute.runtime import from_dlpack\nimport cuda.bindings.driver as cuda\n\n# ============================================================================\n# Constants for PRETRANSPOSE version ([B*HV, V, K])\n# ============================================================================\nTILE_V = 8\nTILE_K = 128\nNUM_STAGES = 2\nNUM_THREADS = 128 # 4 warps\nNUM_BLOCKS_PER_STATE = 8\n\n\n@cute.kernel\ndef gdn_decode_kernel_small_batch_pretranspose(\n tiled_copy_load: cute.TiledCopy,\n h0_source: cute.Tensor,\n smem_layout_staged: cute.Layout,\n vec_size: cutlass.Constexpr[int],\n num_v_tiles: cutlass.Constexpr[int],\n A_log: cute.Tensor, # [HV]\n a: cute.Tensor, # [B, T, HV]\n dt_bias: cute.Tensor, # [HV]\n q: cute.Tensor, # [B, T, H, K]\n k: cute.Tensor, # [B, T, H, K]\n v: cute.Tensor, # [B, T, HV, V]\n b: cute.Tensor, # [B, T, HV]\n o: cute.Tensor, # [B, T, HV, V] - output\n h0_indices: cute.Tensor, # [B] - initial state indices (read)\n h0_out_indices: cute.Tensor, # [B] - output state indices (write)\n cu_seqlens: cute.Tensor, # [B+1] - cumulative sequence lengths (for varlen)\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n use_pool_indexing: cutlass.Constexpr[bool] = False,\n):\n \"\"\"Each block uses pipeline to load one batch and vectorized writeback\"\"\"\n\n tidx, _, _ = cute.arch.thread_idx()\n lane_id = tidx % 32\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n block_idx, _, _ = cute.arch.block_idx()\n batch_idx = block_idx // NUM_BLOCKS_PER_STATE\n batch_inner = block_idx % NUM_BLOCKS_PER_STATE\n num_v_tiles_per_block = num_v_tiles // NUM_BLOCKS_PER_STATE\n i_n = batch_idx // HV\n i_hv = batch_idx % HV\n i_h = i_hv // (HV // H)\n i_t = 0\n\n smem = cutlass.utils.SmemAllocator()\n\n # ===================================================================\n # Allocate shared memory (using passed-in layout)\n # ===================================================================\n sData = smem.allocate_tensor(cutlass.Float32, smem_layout_staged, 128)\n\n # Allocate shared memory for output (size V) - use BFloat16 to match SGLang\n sOutput = smem.allocate_tensor(cutlass.BFloat16, cute.make_layout((V,)), 16)\n\n # Allocate shared memory for v values (size K, to reduce register usage)\n sV = smem.allocate_tensor(cutlass.Float32, cute.make_layout((V,)), 16)\n\n r_k = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n r_q = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n # r_v moved to shared memory (sV)\n r_h = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n # BF16 register tensors for vectorized q, k, v loading\n r_q_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n r_k_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n r_v_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n\n # Compute k_start for contiguous access pattern\n k_start = lane_id * vec_size\n\n # Read gate values from GMEM EARLY (before barrier, latency hidden during sync)\n r_A_log = cutlass.Float32(A_log[i_hv])\n r_a = cutlass.Float32(a[i_n, i_t, i_hv])\n r_dt_bias = cutlass.Float32(dt_bias[i_hv])\n r_b = cutlass.Float32(b[i_n, i_t, i_hv])\n\n cute.arch.barrier()\n\n # Compute state index: use pool indexing if enabled.\n if cutlass.const_expr(use_pool_indexing):\n # Widen pool indices to Int64 BEFORE they multiply ``stride[0]`` of\n # ``h0_source``. With Int32 indices, the per-slot element offset\n # ``pool_idx * stride[0]`` silently wraps once it exceeds INT32_MAX,\n # which makes the kernel issue loads/stores to unmapped global\n # addresses (illegal memory access). For example, the padded slot\n # stride 540672 used by vLLM for Qwen3.5-class GDN models crosses the\n # threshold at pool_idx >= ceil(2**31 / 540672) = 3972. See\n # ``tests/gdn/test_decode_pretranspose_noncontiguous_pool.py::\n # test_decode_pretranspose_pool_int64_offset`` for the regression test.\n pool_idx = cutlass.Int64(h0_indices[i_n])\n out_pool_idx = cutlass.Int64(h0_out_indices[i_n])\n # Redirect negative write indices to null buffer (slot 0)\n if out_pool_idx < 0:\n out_pool_idx = cutlass.Int64(0)\n else:\n pool_idx = 0\n out_pool_idx = 0\n\n if pool_idx >= 0:\n # Get current batch\n if cutlass.const_expr(use_pool_indexing):\n # h0_source layout: [pool_size, HV, V, K] (supports non-contiguous page stride)\n gSrc_batch = h0_source[(pool_idx, i_hv, None, None)] # (V, K)\n gDst = cute.local_tile(\n h0_source, (1, 1, TILE_V, TILE_K), (out_pool_idx, i_hv, None, 0)\n )\n else:\n # h0_source layout: [B*HV, V, K]\n state_idx = batch_idx\n gSrc_batch = h0_source[(state_idx, None, None)] # (V, K)\n gDst = cute.local_tile(h0_source, (1, TILE_V, TILE_K), (state_idx, None, 0))\n # Tile along V dimension\n gSrc = cute.local_tile(\n gSrc_batch, (TILE_V, TILE_K), (None, 0)\n ) # (TILE_V, TILE_K, num_v_tiles)\n\n # Partition for load\n thr_copy_load = tiled_copy_load.get_slice(tidx)\n\n # ===================================================================\n # Prefetch: All threads participate in cp.async load\n # ===================================================================\n start_v_tiles = batch_inner * num_v_tiles_per_block\n prefetch_count = cutlass.min(NUM_STAGES - 1, num_v_tiles_per_block)\n for v_tiles in range(start_v_tiles, start_v_tiles + prefetch_count):\n stage = (v_tiles - start_v_tiles) % NUM_STAGES\n\n gSrc_tile = gSrc[(None, None, v_tiles)]\n sData_stage = sData[(None, None, stage)]\n\n thr_gSrc = thr_copy_load.partition_S(gSrc_tile)\n thr_sData = thr_copy_load.partition_D(sData_stage)\n\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n # Load q, k into BF16 registers using autovec_copy (contiguous pattern)\n q_tile = cute.local_tile(q, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_id))\n k_tile = cute.local_tile(k, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_id))\n cute.autovec_copy(q_tile, r_q_bf16)\n cute.autovec_copy(k_tile, r_k_bf16)\n\n # Convert BF16 to FP32\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = cutlass.Float32(r_q_bf16[i])\n r_k[i] = cutlass.Float32(r_k_bf16[i])\n\n # Load v into BF16 registers using autovec_copy, convert to FP32, store to sV\n v_tile = cute.local_tile(v, (1, 1, 1, vec_size), (i_n, i_t, i_hv, lane_id))\n cute.autovec_copy(v_tile, r_v_bf16)\n for i in cutlass.range_constexpr(vec_size):\n sV[k_start + i] = cutlass.Float32(r_v_bf16[i])\n\n cute.arch.barrier() # Ensure all threads finish writing to sV\n\n # ===================================================================\n # Compute g and beta (scalar values)\n # ===================================================================\n r_g = 0.0\n r_beta = 0.0\n if lane_id == 0:\n x = r_a + r_dt_bias\n beta_x = softplus_beta * x\n softplus_x = 0.0\n\n if beta_x <= softplus_threshold:\n # softplus(x) = (1/beta) * log(1 + exp(beta*x))\n # Compute in Float32\n exp_beta_x = cute.exp(beta_x, fastmath=True)\n log_input = cutlass.Float32(1.0 + exp_beta_x)\n log_result = cutlass.Float32(cute.log(log_input, fastmath=True))\n softplus_x = cutlass.Float32(\n (cutlass.Float32(1.0) / softplus_beta) * log_result\n )\n else:\n softplus_x = x\n\n # Compute g = exp(A_log) * softplus_x\n r_g_value = -cute.exp(r_A_log, fastmath=True) * softplus_x\n\n # Compute beta = 1 / (1 + exp(-b))\n r_beta = 1.0 / (1.0 + cute.exp(-r_b, fastmath=True))\n\n # Store to scalar (Float32)\n r_g = cute.exp(r_g_value, fastmath=True)\n\n r_g = cute.arch.shuffle_sync(r_g, 0)\n r_beta = cute.arch.shuffle_sync(r_beta, 0)\n\n if use_qk_l2norm:\n # Compute L2 norm of q and k\n sum_q = 0.0\n sum_k = 0.0\n for i in cutlass.range_constexpr(vec_size):\n sum_q += r_q[i] * r_q[i]\n sum_k += r_k[i] * r_k[i]\n # Warp-level reduction using butterfly shuffle\n for offset in [16, 8, 4, 2, 1]:\n sum_q += cute.arch.shuffle_sync_bfly(\n sum_q, offset=offset, mask=-1, mask_and_clamp=31\n )\n sum_k += cute.arch.shuffle_sync_bfly(\n sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n inv_norm_q = cute.rsqrt(sum_q + 1e-6, fastmath=True)\n inv_norm_k = cute.rsqrt(sum_k + 1e-6, fastmath=True)\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = r_q[i] * inv_norm_q\n r_k[i] = r_k[i] * inv_norm_k\n\n # Apply scaling in Float32\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = r_q[i] * scale\n\n # ===================================================================\n # Mainloop: All threads participate\n # ===================================================================\n end_v_tiles = start_v_tiles + num_v_tiles_per_block\n for v_tiles in range(start_v_tiles, end_v_tiles):\n stage = (v_tiles - start_v_tiles) % NUM_STAGES\n\n # Step 1: Wait for current stage to complete\n cute.arch.cp_async_wait_group(0)\n cute.arch.barrier()\n\n # Step 2: Issue async load for next tile (after compute)\n next_v_tiles = v_tiles + prefetch_count\n if next_v_tiles < end_v_tiles:\n next_stage = (next_v_tiles - start_v_tiles) % NUM_STAGES\n\n gSrc_next = gSrc[(None, None, next_v_tiles)]\n sData_next = sData[(None, None, next_stage)]\n\n thr_gSrc = thr_copy_load.partition_S(gSrc_next)\n thr_sData = thr_copy_load.partition_D(sData_next)\n\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n # Step 3: Compute using data from current stage (contiguous access pattern)\n for row in cutlass.range_constexpr(0, TILE_V, 4):\n row_offset = tidx // 32\n sum_hk = 0.0\n\n # Load h from sData using 3D local_tile + autovec_copy (contiguous in K)\n sData_tile = cute.local_tile(\n sData, (1, vec_size, 1), (row + row_offset, lane_id, stage)\n )\n cute.autovec_copy(sData_tile, r_h)\n\n for i in cutlass.range_constexpr(vec_size):\n r_h[i] = r_h[i] * r_g\n sum_hk += r_h[i] * r_k[i]\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hk += cute.arch.shuffle_sync_bfly(\n sum_hk, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n v_new = sV[v_tiles * TILE_V + row + row_offset] - sum_hk\n v_new = v_new * r_beta\n\n sum_hq = 0.0\n for i in cutlass.range_constexpr(vec_size):\n r_h[i] += r_k[i] * v_new\n sum_hq += r_h[i] * r_q[i]\n\n # Write h to gDst using 4D local_tile + autovec_copy (contiguous in K)\n if cutlass.const_expr(use_pool_indexing):\n gDst_tile = cute.local_tile(\n gDst,\n (1, 1, 1, vec_size, 1),\n (0, 0, row + row_offset, lane_id, v_tiles),\n )\n else:\n gDst_tile = cute.local_tile(\n gDst,\n (1, 1, vec_size, 1),\n (0, row + row_offset, lane_id, v_tiles),\n )\n cute.autovec_copy(r_h, gDst_tile)\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n sum_hq, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n o_idx = v_tiles * TILE_V + row + row_offset\n if lane_id == 0 and o_idx < V:\n sOutput[o_idx] = cutlass.BFloat16(sum_hq)\n\n # ===================================================================\n # Final writeback: Copy output from shared memory to global memory\n # All threads write (V=128, NUM_THREADS=128)\n # ===================================================================\n cute.arch.barrier() # Ensure all writes to sOutput are complete\n if tidx >= start_v_tiles * TILE_V and tidx < end_v_tiles * TILE_V:\n o[(i_n, i_t, i_hv, tidx)] = sOutput[tidx]\n\n else:\n start_v_tiles = batch_inner * num_v_tiles_per_block\n end_v_tiles = start_v_tiles + num_v_tiles_per_block\n if tidx >= start_v_tiles * TILE_V and tidx < end_v_tiles * TILE_V:\n o[(i_n, i_t, i_hv, tidx)] = cutlass.BFloat16(0.0)\n\n\n@cute.kernel\ndef gdn_decode_kernel_big_batch_pretranspose(\n tiled_copy_load: cute.TiledCopy,\n h0_source: cute.Tensor,\n smem_layout_staged: cute.Layout,\n vec_size: cutlass.Constexpr[int],\n num_v_tiles: cutlass.Constexpr[int],\n A_log: cute.Tensor, # [HV]\n a: cute.Tensor, # [B, T, HV]\n dt_bias: cute.Tensor, # [HV]\n q: cute.Tensor, # [B, T, H, K]\n k: cute.Tensor, # [B, T, H, K]\n v: cute.Tensor, # [B, T, HV, V]\n b: cute.Tensor, # [B, T, HV]\n o: cute.Tensor, # [B, T, HV, V] - output\n h0_indices: cute.Tensor, # [B] - initial state indices (read)\n h0_out_indices: cute.Tensor, # [B] - output state indices (write)\n cu_seqlens: cute.Tensor, # [B+1] - cumulative sequence lengths (for varlen)\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n use_pool_indexing: cutlass.Constexpr[bool] = False,\n):\n \"\"\"Each block uses pipeline to load one batch and vectorized writeback\"\"\"\n\n tidx, _, _ = cute.arch.thread_idx()\n lane_id = tidx % 32\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n batch_idx, _, _ = cute.arch.block_idx()\n i_n = batch_idx // HV\n i_hv = batch_idx % HV\n i_h = i_hv // (HV // H)\n i_t = 0\n\n r_A_log = cutlass.Float32(A_log[i_hv])\n r_a = cutlass.Float32(a[i_n, i_t, i_hv])\n r_dt_bias = cutlass.Float32(dt_bias[i_hv])\n r_b = cutlass.Float32(b[i_n, i_t, i_hv])\n\n smem = cutlass.utils.SmemAllocator()\n\n # ===================================================================\n # Allocate shared memory (using passed-in layout)\n # ===================================================================\n sData = smem.allocate_tensor(cutlass.Float32, smem_layout_staged, 128)\n\n # Allocate shared memory for output (size V) - use BFloat16 to match SGLang\n sOutput = smem.allocate_tensor(cutlass.BFloat16, cute.make_layout((V,)), 16)\n\n # Allocate shared memory for v values (size K, to reduce register usage)\n sV = smem.allocate_tensor(cutlass.Float32, cute.make_layout((V,)), 16)\n\n r_k = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n r_q = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n # r_v moved to shared memory (sV)\n r_h = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n # BF16 register tensors for vectorized q, k, v loading\n r_q_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n r_k_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n r_v_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n\n # Compute k_start for contiguous access pattern\n k_start = lane_id * vec_size\n\n cute.arch.barrier()\n\n # Compute state index: use pool indexing if enabled.\n if cutlass.const_expr(use_pool_indexing):\n # Widen pool indices to Int64 BEFORE they multiply ``stride[0]`` of\n # ``h0_source``. With Int32 indices, the per-slot element offset\n # ``pool_idx * stride[0]`` silently wraps when it exceeds 2**31, which\n # makes the kernel issue loads/stores to unmapped global addresses\n # (illegal memory access). See the small-batch kernel above for the\n # full rationale.\n pool_idx = cutlass.Int64(h0_indices[i_n])\n out_pool_idx = cutlass.Int64(h0_out_indices[i_n])\n # Redirect negative write indices to null buffer (slot 0)\n if out_pool_idx < 0:\n out_pool_idx = cutlass.Int64(0)\n else:\n pool_idx = 0\n out_pool_idx = 0\n\n if pool_idx >= 0:\n # Get current state slice.\n if cutlass.const_expr(use_pool_indexing):\n # h0_source layout: [pool_size, HV, V, K] (supports non-contiguous page stride)\n gSrc_batch = h0_source[(pool_idx, i_hv, None, None)] # (V, K)\n gDst = cute.local_tile(\n h0_source, (1, 1, TILE_V, TILE_K), (out_pool_idx, i_hv, None, 0)\n )\n else:\n # h0_source layout: [B*HV, V, K]\n state_idx = batch_idx\n gSrc_batch = h0_source[(state_idx, None, None)] # (V, K)\n gDst = cute.local_tile(h0_source, (1, TILE_V, TILE_K), (state_idx, None, 0))\n # Tile along V dimension\n gSrc = cute.local_tile(\n gSrc_batch, (TILE_V, TILE_K), (None, 0)\n ) # (TILE_V, TILE_K, num_v_tiles)\n\n # Partition for load\n thr_copy_load = tiled_copy_load.get_slice(tidx)\n\n # ===================================================================\n # Prefetch: All threads participate in cp.async load\n # ===================================================================\n prefetch_count = cutlass.min(NUM_STAGES - 1, num_v_tiles)\n for v_tiles in range(prefetch_count):\n stage = v_tiles % NUM_STAGES\n\n gSrc_tile = gSrc[(None, None, v_tiles)]\n sData_stage = sData[(None, None, stage)]\n\n thr_gSrc = thr_copy_load.partition_S(gSrc_tile)\n thr_sData = thr_copy_load.partition_D(sData_stage)\n\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n # Load q, k into BF16 registers using autovec_copy (contiguous pattern)\n q_tile = cute.local_tile(q, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_id))\n k_tile = cute.local_tile(k, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_id))\n cute.autovec_copy(q_tile, r_q_bf16)\n cute.autovec_copy(k_tile, r_k_bf16)\n\n # Convert BF16 to FP32\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = cutlass.Float32(r_q_bf16[i])\n r_k[i] = cutlass.Float32(r_k_bf16[i])\n\n # Load v into BF16 registers using autovec_copy, convert to FP32, store to sV\n v_tile = cute.local_tile(v, (1, 1, 1, vec_size), (i_n, i_t, i_hv, lane_id))\n cute.autovec_copy(v_tile, r_v_bf16)\n for i in cutlass.range_constexpr(vec_size):\n sV[k_start + i] = cutlass.Float32(r_v_bf16[i])\n\n cute.arch.barrier() # Ensure all threads finish writing to sV\n\n # ===================================================================\n # Compute g and beta (scalar values)\n # ===================================================================\n r_g = 0.0\n r_beta = 0.0\n if lane_id == 0:\n x = r_a + r_dt_bias\n beta_x = softplus_beta * x\n softplus_x = 0.0\n\n if beta_x <= softplus_threshold:\n # softplus(x) = (1/beta) * log(1 + exp(beta*x))\n # Compute in Float32\n exp_beta_x = cute.exp(beta_x, fastmath=True)\n log_input = cutlass.Float32(1.0 + exp_beta_x)\n log_result = cutlass.Float32(cute.log(log_input, fastmath=True))\n softplus_x = cutlass.Float32(\n (cutlass.Float32(1.0) / softplus_beta) * log_result\n )\n else:\n softplus_x = x\n\n # Compute g = exp(A_log) * softplus_x\n r_g_value = -cute.exp(r_A_log, fastmath=True) * softplus_x\n\n # Compute beta = 1 / (1 + exp(-b))\n r_beta = 1.0 / (1.0 + cute.exp(-r_b, fastmath=True))\n\n # Store to scalar (Float32)\n r_g = cute.exp(r_g_value, fastmath=True)\n\n r_g = cute.arch.shuffle_sync(r_g, 0)\n r_beta = cute.arch.shuffle_sync(r_beta, 0)\n\n if use_qk_l2norm:\n # Compute L2 norm of q and k\n sum_q = 0.0\n sum_k = 0.0\n for i in cutlass.range_constexpr(vec_size):\n sum_q += r_q[i] * r_q[i]\n sum_k += r_k[i] * r_k[i]\n # Warp-level reduction using butterfly shuffle\n for offset in [16, 8, 4, 2, 1]:\n sum_q += cute.arch.shuffle_sync_bfly(\n sum_q, offset=offset, mask=-1, mask_and_clamp=31\n )\n sum_k += cute.arch.shuffle_sync_bfly(\n sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n inv_norm_q = cute.rsqrt(sum_q + 1e-6, fastmath=True)\n inv_norm_k = cute.rsqrt(sum_k + 1e-6, fastmath=True)\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = r_q[i] * inv_norm_q\n r_k[i] = r_k[i] * inv_norm_k\n\n # Apply scaling in Float32\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = r_q[i] * scale\n\n # ===================================================================\n # Mainloop: All threads participate\n # ===================================================================\n for v_tiles in range(num_v_tiles):\n stage = v_tiles % NUM_STAGES\n\n # Step 1: Wait for current stage to complete\n cute.arch.cp_async_wait_group(0)\n cute.arch.barrier()\n\n # Step 2: Issue async load for next tile (after compute)\n next_v_tiles = v_tiles + prefetch_count\n if next_v_tiles < num_v_tiles:\n next_stage = next_v_tiles % NUM_STAGES\n\n gSrc_next = gSrc[(None, None, next_v_tiles)]\n sData_next = sData[(None, None, next_stage)]\n\n thr_gSrc = thr_copy_load.partition_S(gSrc_next)\n thr_sData = thr_copy_load.partition_D(sData_next)\n\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n # Step 3: Compute using data from current stage (contiguous access pattern)\n for row in cutlass.range_constexpr(0, TILE_V, 4):\n row_offset = tidx // 32\n sum_hk = 0.0\n\n # Load h from sData using 3D local_tile + autovec_copy (contiguous in K)\n sData_tile = cute.local_tile(\n sData, (1, vec_size, 1), (row + row_offset, lane_id, stage)\n )\n cute.autovec_copy(sData_tile, r_h)\n\n for i in cutlass.range_constexpr(vec_size):\n r_h[i] = r_h[i] * r_g\n sum_hk += r_h[i] * r_k[i]\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hk += cute.arch.shuffle_sync_bfly(\n sum_hk, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n v_new = sV[v_tiles * TILE_V + row + row_offset] - sum_hk\n v_new = v_new * r_beta\n\n sum_hq = 0.0\n for i in cutlass.range_constexpr(vec_size):\n r_h[i] += r_k[i] * v_new\n sum_hq += r_h[i] * r_q[i]\n\n # Write h back to state.\n if cutlass.const_expr(use_pool_indexing):\n gDst_tile = cute.local_tile(\n gDst,\n (1, 1, 1, vec_size, 1),\n (0, 0, row + row_offset, lane_id, v_tiles),\n )\n else:\n gDst_tile = cute.local_tile(\n gDst,\n (1, 1, vec_size, 1),\n (0, row + row_offset, lane_id, v_tiles),\n )\n cute.autovec_copy(r_h, gDst_tile)\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n sum_hq, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n o_idx = v_tiles * TILE_V + row + row_offset\n if lane_id == 0 and o_idx < V:\n sOutput[o_idx] = cutlass.BFloat16(sum_hq)\n\n # ===================================================================\n # Final writeback: Copy output from shared memory to global memory\n # All threads write (V=128, NUM_THREADS=128)\n # ===================================================================\n cute.arch.barrier() # Ensure all writes to sOutput are complete\n\n if tidx < V:\n o[(i_n, i_t, i_hv, tidx)] = sOutput[tidx]\n\n else:\n if tidx < V:\n o[(i_n, i_t, i_hv, tidx)] = cutlass.BFloat16(0.0)\n\n\n@cute.jit\ndef run_gdn_decode_kernel_small_batch_pretranspose(\n h0_source: cute.Tensor, # [B*HV, K, V]\n A_log: cute.Tensor,\n a: cute.Tensor,\n dt_bias: cute.Tensor,\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n b: cute.Tensor,\n o: cute.Tensor,\n h0_indices: cute.Tensor,\n h0_out_indices: cute.Tensor,\n cu_seqlens: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n use_pool_indexing: cutlass.Constexpr[bool] = False,\n stream: cuda.CUstream = None,\n):\n \"\"\"Launch original pipelined kernel for small batch pretranspose.\"\"\"\n # h0_source:\n # - non-pool: (B*HV, V, K)\n # - pool: (pool_size, HV, V, K)\n if cutlass.const_expr(use_pool_indexing):\n v_dim = h0_source.layout.shape[2]\n k_dim = h0_source.layout.shape[3]\n else:\n v_dim = h0_source.layout.shape[1]\n k_dim = h0_source.layout.shape[2]\n # Grid size: use B*HV (actual batch) not h0_source.shape[0] (which may be pool_size*HV)\n B = cute.size(q.shape[0])\n grid_batch = B * HV\n\n # Create cp.async copy with cache-global mode (bypass L1)\n copy_atom = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n cutlass.Float32,\n num_bits_per_copy=128, # 4 elements per copy\n )\n\n # Thread layout: 4 rows × 32 threads/row = 128 threads\n thread_layout = cute.make_layout(\n (4, 32), # 4 rows, 32 threads/row\n stride=(32, 1),\n )\n val_layout = cute.make_layout((1, 4)) # Each thread handles 4 elements\n\n tiled_copy_load = cute.make_tiled_copy_tv(copy_atom, thread_layout, val_layout)\n\n num_v_tiles = cute.ceil_div(v_dim, TILE_V)\n v_dim * k_dim * 4 / 1024 / 1024\n\n vec_size = (\n TILE_K // 32\n ) # Each thread in a warp processes this many elements (always 4 for TILE_K=128)\n\n # Create SMEM layout\n smem_layout_staged = cute.make_layout(\n (TILE_V, TILE_K, NUM_STAGES), stride=(TILE_K, 1, TILE_V * TILE_K)\n )\n\n # sData: TILE_V * TILE_K * NUM_STAGES * 4 bytes (Float32)\n # sV: K * 4 bytes (Float32)\n # sOutput: V * 2 bytes (BFloat16)\n smem_bytes = 4 * TILE_V * TILE_K * NUM_STAGES + 4 * k_dim + 2 * v_dim + 32\n\n gdn_decode_kernel_small_batch_pretranspose(\n tiled_copy_load,\n h0_source,\n smem_layout_staged,\n vec_size,\n num_v_tiles,\n A_log,\n a,\n dt_bias,\n q,\n k,\n v,\n b,\n o,\n h0_indices,\n h0_out_indices,\n cu_seqlens,\n softplus_beta,\n softplus_threshold,\n scale,\n HV,\n T,\n H,\n K,\n V,\n use_initial_state,\n use_qk_l2norm,\n is_varlen,\n use_pool_indexing,\n ).launch(\n grid=(grid_batch * NUM_BLOCKS_PER_STATE, 1, 1),\n block=[NUM_THREADS, 1, 1],\n smem=smem_bytes,\n stream=stream,\n )\n\n\n@cute.jit\ndef run_gdn_decode_kernel_big_batch_pretranspose(\n h0_source: cute.Tensor, # [B*HV, K, V]\n A_log: cute.Tensor,\n a: cute.Tensor,\n dt_bias: cute.Tensor,\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n b: cute.Tensor,\n o: cute.Tensor,\n h0_indices: cute.Tensor,\n h0_out_indices: cute.Tensor,\n cu_seqlens: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n use_pool_indexing: cutlass.Constexpr[bool] = False,\n stream: cuda.CUstream = None,\n):\n if cutlass.const_expr(use_pool_indexing):\n v_dim = h0_source.layout.shape[2]\n k_dim = h0_source.layout.shape[3]\n else:\n v_dim = h0_source.layout.shape[1]\n k_dim = h0_source.layout.shape[2]\n B = cute.size(q.shape[0])\n grid_batch = B * HV\n\n # Create cp.async copy with cache-global mode (bypass L1)\n copy_atom = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n cutlass.Float32,\n num_bits_per_copy=128, # 4 elements per copy\n )\n\n # Thread layout: 4 rows × 32 threads/row = 128 threads\n thread_layout = cute.make_layout(\n (4, 32), # 4 rows, 32 threads/row\n stride=(32, 1),\n )\n val_layout = cute.make_layout((1, 4)) # Each thread handles 4 elements\n\n tiled_copy_load = cute.make_tiled_copy_tv(copy_atom, thread_layout, val_layout)\n\n num_v_tiles = cute.ceil_div(v_dim, TILE_V)\n v_dim * k_dim * 4 / 1024 / 1024\n\n vec_size = (\n TILE_K // 32\n ) # Each thread in a warp processes this many elements (always 4 for TILE_K=128)\n\n # Create SMEM layout\n smem_layout_staged = cute.make_layout(\n (TILE_V, TILE_K, NUM_STAGES), stride=(TILE_K, 1, TILE_V * TILE_K)\n )\n\n # sData: TILE_V * TILE_K * NUM_STAGES * 4 bytes (Float32)\n # sV: K * 4 bytes (Float32)\n # sOutput: V * 2 bytes (BFloat16)\n smem_bytes = 4 * TILE_V * TILE_K * NUM_STAGES + 4 * k_dim + 2 * v_dim + 32\n\n gdn_decode_kernel_big_batch_pretranspose(\n tiled_copy_load,\n h0_source,\n smem_layout_staged,\n vec_size,\n num_v_tiles,\n A_log,\n a,\n dt_bias,\n q,\n k,\n v,\n b,\n o,\n h0_indices,\n h0_out_indices,\n cu_seqlens,\n softplus_beta,\n softplus_threshold,\n scale,\n HV,\n T,\n H,\n K,\n V,\n use_initial_state,\n use_qk_l2norm,\n is_varlen,\n use_pool_indexing,\n ).launch(\n grid=(grid_batch, 1, 1),\n block=[NUM_THREADS, 1, 1],\n smem=smem_bytes,\n stream=stream,\n )\n\n\n# ============================================================================\n# Compilation cache and public entry point\n# ============================================================================\n\n\n@functools.cache\ndef _get_compiled_decode_kernel(\n T: int,\n H: int,\n HV: int,\n K: int,\n V: int,\n dtype: torch.dtype,\n scale: float,\n use_qk_l2norm: bool,\n use_pool_indexing: bool = False,\n pool_size: int = 0,\n stride0: int = 0,\n stride1: int = 0,\n stride2: int = 0,\n stride3: int = 0,\n):\n \"\"\"Cache compiled kernel for given configuration (pretranspose version).\"\"\"\n # This will be populated on first call\n return {}\n\n\ndef run_pretranspose_decode(\n h0_source: torch.Tensor,\n A_log: torch.Tensor,\n a: torch.Tensor,\n dt_bias: torch.Tensor,\n q: torch.Tensor,\n k: torch.Tensor,\n v: torch.Tensor,\n b: torch.Tensor,\n output: torch.Tensor,\n B: int,\n T: int,\n H: int,\n HV: int,\n K: int,\n V: int,\n scale: float,\n use_qk_l2norm: bool,\n use_pool_indexing: bool = False,\n initial_state_indices: Optional[torch.Tensor] = None,\n output_state_indices: Optional[torch.Tensor] = None,\n):\n \"\"\"Compile and execute the pretranspose decode kernel.\n\n Args:\n h0_source: State tensor of shape [B*HV, V, K], or [pool_size, HV, V, K]\n when use_pool_indexing=True.\n A_log, a, dt_bias, q, k, v, b: Input tensors.\n output: Pre-allocated output tensor [B, T, HV, V].\n B, T, H, HV, K, V: Dimension sizes.\n scale: Query scale factor.\n use_qk_l2norm: Whether to apply L2 normalization.\n use_pool_indexing: Whether to use pool-based indirect state indexing.\n initial_state_indices: Int32 indices into state pool, shape [B].\n Negative values indicate padding (kernel writes zeros).\n output_state_indices: Optional int32 indices for write destination, shape [B].\n When None, writes go to the same slot as initial_state_indices.\n \"\"\"\n # Compile kernel with TVM FFI (cached)\n if use_pool_indexing:\n pool_size = int(h0_source.shape[0])\n stride0, stride1, stride2, stride3 = tuple(int(x) for x in h0_source.stride())\n else:\n pool_size = stride0 = stride1 = stride2 = stride3 = 0\n cache_key = (\n T,\n H,\n HV,\n K,\n V,\n q.dtype,\n scale,\n use_qk_l2norm,\n use_pool_indexing,\n pool_size,\n stride0,\n stride1,\n stride2,\n stride3,\n )\n cache = _get_compiled_decode_kernel(*cache_key)\n\n aux_map = cache.setdefault(\"aux\", {})\n aux_key = (B, q.device)\n if aux_key not in aux_map:\n aux_map[aux_key] = (\n torch.zeros(B, dtype=torch.int32, device=q.device),\n torch.zeros(B + 1, dtype=torch.int32, device=q.device),\n )\n default_h0_indices, cu_seqlens = aux_map[aux_key]\n\n if use_pool_indexing and initial_state_indices is not None:\n h0_indices = initial_state_indices.to(torch.int32)\n else:\n h0_indices = default_h0_indices\n # Resolve output indices: default to same as read indices\n if use_pool_indexing and output_state_indices is not None:\n h0_out_indices = output_state_indices.to(torch.int32)\n else:\n h0_out_indices = h0_indices\n\n if \"compiled\" not in cache:\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n\n h0_source_tensor = from_dlpack(h0_source, assumed_align=16)\n if not use_pool_indexing:\n h0_source_tensor = h0_source_tensor.mark_compact_shape_dynamic(\n mode=0, stride_order=(0, 1, 2), divisibility=1\n )\n A_log_tensor = from_dlpack(A_log, assumed_align=16)\n # mark_layout_dynamic accepts non-compact packed q/k/v (SGLang fused QKV).\n a_tensor = from_dlpack(a, assumed_align=16).mark_layout_dynamic()\n dt_bias_tensor = from_dlpack(dt_bias, assumed_align=16)\n q_tensor = from_dlpack(q, assumed_align=16).mark_layout_dynamic()\n k_tensor = from_dlpack(k, assumed_align=16).mark_layout_dynamic()\n v_tensor = from_dlpack(v, assumed_align=16).mark_layout_dynamic()\n b_tensor = from_dlpack(b, assumed_align=16).mark_layout_dynamic()\n o_tensor = from_dlpack(output, assumed_align=16).mark_layout_dynamic()\n h0_indices_tensor = from_dlpack(\n h0_indices, assumed_align=16\n ).mark_layout_dynamic()\n h0_out_indices_tensor = from_dlpack(\n h0_out_indices, assumed_align=16\n ).mark_layout_dynamic()\n cu_seqlens_tensor = from_dlpack(\n cu_seqlens, assumed_align=16\n ).mark_layout_dynamic()\n\n # Always use 8-CTA architecture (benchmarks show it's better for all batch sizes)\n run_func = run_gdn_decode_kernel_small_batch_pretranspose\n\n # Use TVM FFI to reduce runtime overhead\n compiled = cute.compile(\n run_func,\n h0_source_tensor,\n A_log_tensor,\n a_tensor,\n dt_bias_tensor,\n q_tensor,\n k_tensor,\n v_tensor,\n b_tensor,\n o_tensor,\n h0_indices_tensor,\n h0_out_indices_tensor,\n cu_seqlens_tensor,\n softplus_beta=1.0,\n softplus_threshold=20.0,\n scale=scale,\n HV=HV,\n T=T,\n H=H,\n K=K,\n V=V,\n use_initial_state=True,\n use_qk_l2norm=use_qk_l2norm,\n use_pool_indexing=use_pool_indexing,\n is_varlen=False,\n stream=stream,\n options=\"--enable-tvm-ffi\",\n )\n cache[\"compiled\"] = compiled\n else:\n compiled = cache[\"compiled\"]\n\n # Run kernel directly with PyTorch tensors (no from_dlpack needed)\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n cache[\"compiled\"](\n h0_source,\n A_log,\n a,\n dt_bias,\n q,\n k,\n v,\n b,\n output,\n h0_indices,\n h0_out_indices,\n cu_seqlens,\n stream,\n )\n"},"after_code":{"kind":"string","value":"\"\"\"\nCopyright (c) 2025 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nGated Delta Rule Decode Kernel - Pretranspose (V-major / K-last) Layout\n========================================================================\n\nCuTe-DSL implementation of GDN decode with state layout [B*HV, V, K].\nUses TMA pipelining and vectorized memory access for T=1 decode.\n\"\"\"\n\nimport functools\nfrom typing import Optional\n\nimport torch\nimport cutlass\nimport cutlass.cute as cute\nfrom cutlass.cute.nvgpu import cpasync\nfrom cutlass.cute.runtime import from_dlpack\nimport cuda.bindings.driver as cuda\n\n# ============================================================================\n# Constants for PRETRANSPOSE version ([B*HV, V, K])\n# ============================================================================\nTILE_V = 8\nTILE_K = 128\nNUM_STAGES = 2\nNUM_THREADS = 128 # 4 warps\nNUM_BLOCKS_PER_STATE = 8\n\n\n@cute.kernel\ndef gdn_decode_kernel_small_batch_pretranspose(\n tiled_copy_load: cute.TiledCopy,\n h0_source: cute.Tensor,\n smem_layout_staged: cute.Layout,\n vec_size: cutlass.Constexpr[int],\n num_v_tiles: cutlass.Constexpr[int],\n A_log: cute.Tensor, # [HV]\n a: cute.Tensor, # [B, T, HV]\n dt_bias: cute.Tensor, # [HV]\n q: cute.Tensor, # [B, T, H, K]\n k: cute.Tensor, # [B, T, H, K]\n v: cute.Tensor, # [B, T, HV, V]\n b: cute.Tensor, # [B, T, HV]\n o: cute.Tensor, # [B, T, HV, V] - output\n h0_indices: cute.Tensor, # [B] - initial state indices (read)\n h0_out_indices: cute.Tensor, # [B] - output state indices (write)\n cu_seqlens: cute.Tensor, # [B+1] - cumulative sequence lengths (for varlen)\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n use_pool_indexing: cutlass.Constexpr[bool] = False,\n):\n \"\"\"Each block uses pipeline to load one batch and vectorized writeback\"\"\"\n\n tidx, _, _ = cute.arch.thread_idx()\n lane_id = tidx % 32\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n block_idx, _, _ = cute.arch.block_idx()\n batch_idx = block_idx // NUM_BLOCKS_PER_STATE\n batch_inner = block_idx % NUM_BLOCKS_PER_STATE\n num_v_tiles_per_block = num_v_tiles // NUM_BLOCKS_PER_STATE\n i_n = batch_idx // HV\n i_hv = batch_idx % HV\n i_h = i_hv // (HV // H)\n i_t = 0\n\n smem = cutlass.utils.SmemAllocator()\n\n # ===================================================================\n # Allocate shared memory (using passed-in layout)\n # ===================================================================\n sData = smem.allocate_tensor(cutlass.Float32, smem_layout_staged, 128)\n\n # Allocate shared memory for output (size V) - use BFloat16 to match SGLang\n sOutput = smem.allocate_tensor(cutlass.BFloat16, cute.make_layout((V,)), 16)\n\n # Allocate shared memory for v values (size K, to reduce register usage)\n sV = smem.allocate_tensor(cutlass.Float32, cute.make_layout((V,)), 16)\n\n r_k = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n r_q = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n # r_v moved to shared memory (sV)\n r_h = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n # BF16 register tensors for vectorized q, k, v loading\n r_q_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n r_k_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n r_v_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n\n # Compute k_start for contiguous access pattern\n k_start = lane_id * vec_size\n\n # Read gate values from GMEM EARLY (before barrier, latency hidden during sync)\n r_A_log = cutlass.Float32(A_log[i_hv])\n r_a = cutlass.Float32(a[i_n, i_t, i_hv])\n r_dt_bias = cutlass.Float32(dt_bias[i_hv])\n r_b = cutlass.Float32(b[i_n, i_t, i_hv])\n\n cute.arch.barrier()\n\n # Compute state index: use pool indexing if enabled.\n if cutlass.const_expr(use_pool_indexing):\n # Widen pool indices to Int64 BEFORE they multiply ``stride[0]`` of\n # ``h0_source``. With Int32 indices, the per-slot element offset\n # ``pool_idx * stride[0]`` silently wraps once it exceeds INT32_MAX,\n # which makes the kernel issue loads/stores to unmapped global\n # addresses (illegal memory access). For example, the padded slot\n # stride 540672 used by vLLM for Qwen3.5-class GDN models crosses the\n # threshold at pool_idx >= ceil(2**31 / 540672) = 3972. See\n # ``tests/gdn/test_decode_pretranspose_noncontiguous_pool.py::\n # test_decode_pretranspose_pool_int64_offset`` for the regression test.\n pool_idx = cutlass.Int64(h0_indices[i_n])\n out_pool_idx = cutlass.Int64(h0_out_indices[i_n])\n # Redirect negative write indices to null buffer (slot 0)\n if out_pool_idx < 0:\n out_pool_idx = cutlass.Int64(0)\n else:\n pool_idx = 0\n out_pool_idx = 0\n\n if pool_idx >= 0:\n # Get current batch\n if cutlass.const_expr(use_pool_indexing):\n # h0_source layout: [pool_size, HV, V, K] (supports non-contiguous page stride)\n gSrc_batch = h0_source[(pool_idx, i_hv, None, None)] # (V, K)\n gDst = cute.local_tile(\n h0_source, (1, 1, TILE_V, TILE_K), (out_pool_idx, i_hv, None, 0)\n )\n else:\n # h0_source layout: [B*HV, V, K]\n state_idx = batch_idx\n gSrc_batch = h0_source[(state_idx, None, None)] # (V, K)\n gDst = cute.local_tile(h0_source, (1, TILE_V, TILE_K), (state_idx, None, 0))\n # Tile along V dimension\n gSrc = cute.local_tile(\n gSrc_batch, (TILE_V, TILE_K), (None, 0)\n ) # (TILE_V, TILE_K, num_v_tiles)\n\n # Partition for load\n thr_copy_load = tiled_copy_load.get_slice(tidx)\n\n # ===================================================================\n # Prefetch: All threads participate in cp.async load\n # ===================================================================\n start_v_tiles = batch_inner * num_v_tiles_per_block\n prefetch_count = cutlass.min(NUM_STAGES - 1, num_v_tiles_per_block)\n for v_tiles in range(start_v_tiles, start_v_tiles + prefetch_count):\n stage = (v_tiles - start_v_tiles) % NUM_STAGES\n\n gSrc_tile = gSrc[(None, None, v_tiles)]\n sData_stage = sData[(None, None, stage)]\n\n thr_gSrc = thr_copy_load.partition_S(gSrc_tile)\n thr_sData = thr_copy_load.partition_D(sData_stage)\n\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n # Load q, k into BF16 registers using autovec_copy (contiguous pattern)\n q_tile = cute.local_tile(q, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_id))\n k_tile = cute.local_tile(k, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_id))\n cute.autovec_copy(q_tile, r_q_bf16)\n cute.autovec_copy(k_tile, r_k_bf16)\n\n # Convert BF16 to FP32\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = cutlass.Float32(r_q_bf16[i])\n r_k[i] = cutlass.Float32(r_k_bf16[i])\n\n # Load v into BF16 registers using autovec_copy, convert to FP32, store to sV\n v_tile = cute.local_tile(v, (1, 1, 1, vec_size), (i_n, i_t, i_hv, lane_id))\n cute.autovec_copy(v_tile, r_v_bf16)\n for i in cutlass.range_constexpr(vec_size):\n sV[k_start + i] = cutlass.Float32(r_v_bf16[i])\n\n cute.arch.barrier() # Ensure all threads finish writing to sV\n\n # ===================================================================\n # Compute g and beta (scalar values)\n # ===================================================================\n r_g = 0.0\n r_beta = 0.0\n if lane_id == 0:\n x = r_a + r_dt_bias\n beta_x = softplus_beta * x\n softplus_x = 0.0\n\n if beta_x <= softplus_threshold:\n # softplus(x) = (1/beta) * log(1 + exp(beta*x))\n # Compute in Float32\n exp_beta_x = cute.exp(beta_x, fastmath=True)\n log_input = cutlass.Float32(1.0 + exp_beta_x)\n log_result = cutlass.Float32(cute.log(log_input, fastmath=True))\n softplus_x = cutlass.Float32(\n (cutlass.Float32(1.0) / softplus_beta) * log_result\n )\n else:\n softplus_x = x\n\n # Compute g = exp(A_log) * softplus_x\n r_g_value = -cute.exp(r_A_log, fastmath=True) * softplus_x\n\n # Compute beta = 1 / (1 + exp(-b))\n r_beta = 1.0 / (1.0 + cute.exp(-r_b, fastmath=True))\n\n # Store to scalar (Float32)\n r_g = cute.exp(r_g_value, fastmath=True)\n\n r_g = cute.arch.shuffle_sync(r_g, 0)\n r_beta = cute.arch.shuffle_sync(r_beta, 0)\n\n if use_qk_l2norm:\n # Compute L2 norm of q and k\n sum_q = 0.0\n sum_k = 0.0\n for i in cutlass.range_constexpr(vec_size):\n sum_q += r_q[i] * r_q[i]\n sum_k += r_k[i] * r_k[i]\n # Warp-level reduction using butterfly shuffle\n for offset in [16, 8, 4, 2, 1]:\n sum_q += cute.arch.shuffle_sync_bfly(\n sum_q, offset=offset, mask=-1, mask_and_clamp=31\n )\n sum_k += cute.arch.shuffle_sync_bfly(\n sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n inv_norm_q = cute.rsqrt(sum_q + 1e-6, fastmath=True)\n inv_norm_k = cute.rsqrt(sum_k + 1e-6, fastmath=True)\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = r_q[i] * inv_norm_q\n r_k[i] = r_k[i] * inv_norm_k\n\n # Apply scaling in Float32\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = r_q[i] * scale\n\n # ===================================================================\n # Mainloop: All threads participate\n # ===================================================================\n end_v_tiles = start_v_tiles + num_v_tiles_per_block\n for v_tiles in range(start_v_tiles, end_v_tiles):\n stage = (v_tiles - start_v_tiles) % NUM_STAGES\n\n # Step 1: Wait for current stage to complete\n cute.arch.cp_async_wait_group(0)\n cute.arch.barrier()\n\n # Step 2: Issue async load for next tile (after compute)\n next_v_tiles = v_tiles + prefetch_count\n if next_v_tiles < end_v_tiles:\n next_stage = (next_v_tiles - start_v_tiles) % NUM_STAGES\n\n gSrc_next = gSrc[(None, None, next_v_tiles)]\n sData_next = sData[(None, None, next_stage)]\n\n thr_gSrc = thr_copy_load.partition_S(gSrc_next)\n thr_sData = thr_copy_load.partition_D(sData_next)\n\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n # Step 3: Compute using data from current stage (contiguous access pattern)\n for row in cutlass.range_constexpr(0, TILE_V, 4):\n row_offset = tidx // 32\n sum_hk = 0.0\n\n # Load h from sData using 3D local_tile + autovec_copy (contiguous in K)\n sData_tile = cute.local_tile(\n sData, (1, vec_size, 1), (row + row_offset, lane_id, stage)\n )\n cute.autovec_copy(sData_tile, r_h)\n\n for i in cutlass.range_constexpr(vec_size):\n r_h[i] = r_h[i] * r_g\n sum_hk += r_h[i] * r_k[i]\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hk += cute.arch.shuffle_sync_bfly(\n sum_hk, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n v_new = sV[v_tiles * TILE_V + row + row_offset] - sum_hk\n v_new = v_new * r_beta\n\n sum_hq = 0.0\n for i in cutlass.range_constexpr(vec_size):\n r_h[i] += r_k[i] * v_new\n sum_hq += r_h[i] * r_q[i]\n\n # Write h to gDst using 4D local_tile + autovec_copy (contiguous in K)\n if cutlass.const_expr(use_pool_indexing):\n gDst_tile = cute.local_tile(\n gDst,\n (1, 1, 1, vec_size, 1),\n (0, 0, row + row_offset, lane_id, v_tiles),\n )\n else:\n gDst_tile = cute.local_tile(\n gDst,\n (1, 1, vec_size, 1),\n (0, row + row_offset, lane_id, v_tiles),\n )\n cute.autovec_copy(r_h, gDst_tile)\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n sum_hq, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n o_idx = v_tiles * TILE_V + row + row_offset\n if lane_id == 0 and o_idx < V:\n sOutput[o_idx] = cutlass.BFloat16(sum_hq)\n\n # ===================================================================\n # Final writeback: Copy output from shared memory to global memory\n # All threads write (V=128, NUM_THREADS=128)\n # ===================================================================\n cute.arch.barrier() # Ensure all writes to sOutput are complete\n if tidx >= start_v_tiles * TILE_V and tidx < end_v_tiles * TILE_V:\n o[(i_n, i_t, i_hv, tidx)] = sOutput[tidx]\n\n else:\n start_v_tiles = batch_inner * num_v_tiles_per_block\n end_v_tiles = start_v_tiles + num_v_tiles_per_block\n if tidx >= start_v_tiles * TILE_V and tidx < end_v_tiles * TILE_V:\n o[(i_n, i_t, i_hv, tidx)] = cutlass.BFloat16(0.0)\n\n\n@cute.kernel\ndef gdn_decode_kernel_big_batch_pretranspose(\n tiled_copy_load: cute.TiledCopy,\n h0_source: cute.Tensor,\n smem_layout_staged: cute.Layout,\n vec_size: cutlass.Constexpr[int],\n num_v_tiles: cutlass.Constexpr[int],\n A_log: cute.Tensor, # [HV]\n a: cute.Tensor, # [B, T, HV]\n dt_bias: cute.Tensor, # [HV]\n q: cute.Tensor, # [B, T, H, K]\n k: cute.Tensor, # [B, T, H, K]\n v: cute.Tensor, # [B, T, HV, V]\n b: cute.Tensor, # [B, T, HV]\n o: cute.Tensor, # [B, T, HV, V] - output\n h0_indices: cute.Tensor, # [B] - initial state indices (read)\n h0_out_indices: cute.Tensor, # [B] - output state indices (write)\n cu_seqlens: cute.Tensor, # [B+1] - cumulative sequence lengths (for varlen)\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n use_pool_indexing: cutlass.Constexpr[bool] = False,\n):\n \"\"\"Each block uses pipeline to load one batch and vectorized writeback\"\"\"\n\n tidx, _, _ = cute.arch.thread_idx()\n lane_id = tidx % 32\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n batch_idx, _, _ = cute.arch.block_idx()\n i_n = batch_idx // HV\n i_hv = batch_idx % HV\n i_h = i_hv // (HV // H)\n i_t = 0\n\n r_A_log = cutlass.Float32(A_log[i_hv])\n r_a = cutlass.Float32(a[i_n, i_t, i_hv])\n r_dt_bias = cutlass.Float32(dt_bias[i_hv])\n r_b = cutlass.Float32(b[i_n, i_t, i_hv])\n\n smem = cutlass.utils.SmemAllocator()\n\n # ===================================================================\n # Allocate shared memory (using passed-in layout)\n # ===================================================================\n sData = smem.allocate_tensor(cutlass.Float32, smem_layout_staged, 128)\n\n # Allocate shared memory for output (size V) - use BFloat16 to match SGLang\n sOutput = smem.allocate_tensor(cutlass.BFloat16, cute.make_layout((V,)), 16)\n\n # Allocate shared memory for v values (size K, to reduce register usage)\n sV = smem.allocate_tensor(cutlass.Float32, cute.make_layout((V,)), 16)\n\n r_k = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n r_q = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n # r_v moved to shared memory (sV)\n r_h = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n # BF16 register tensors for vectorized q, k, v loading\n r_q_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n r_k_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n r_v_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n\n # Compute k_start for contiguous access pattern\n k_start = lane_id * vec_size\n\n cute.arch.barrier()\n\n # Compute state index: use pool indexing if enabled.\n if cutlass.const_expr(use_pool_indexing):\n # Widen pool indices to Int64 BEFORE they multiply ``stride[0]`` of\n # ``h0_source``. With Int32 indices, the per-slot element offset\n # ``pool_idx * stride[0]`` silently wraps when it exceeds 2**31, which\n # makes the kernel issue loads/stores to unmapped global addresses\n # (illegal memory access). See the small-batch kernel above for the\n # full rationale.\n pool_idx = cutlass.Int64(h0_indices[i_n])\n out_pool_idx = cutlass.Int64(h0_out_indices[i_n])\n # Redirect negative write indices to null buffer (slot 0)\n if out_pool_idx < 0:\n out_pool_idx = cutlass.Int64(0)\n else:\n pool_idx = 0\n out_pool_idx = 0\n\n if pool_idx >= 0:\n # Get current state slice.\n if cutlass.const_expr(use_pool_indexing):\n # h0_source layout: [pool_size, HV, V, K] (supports non-contiguous page stride)\n gSrc_batch = h0_source[(pool_idx, i_hv, None, None)] # (V, K)\n gDst = cute.local_tile(\n h0_source, (1, 1, TILE_V, TILE_K), (out_pool_idx, i_hv, None, 0)\n )\n else:\n # h0_source layout: [B*HV, V, K]\n state_idx = batch_idx\n gSrc_batch = h0_source[(state_idx, None, None)] # (V, K)\n gDst = cute.local_tile(h0_source, (1, TILE_V, TILE_K), (state_idx, None, 0))\n # Tile along V dimension\n gSrc = cute.local_tile(\n gSrc_batch, (TILE_V, TILE_K), (None, 0)\n ) # (TILE_V, TILE_K, num_v_tiles)\n\n # Partition for load\n thr_copy_load = tiled_copy_load.get_slice(tidx)\n\n # ===================================================================\n # Prefetch: All threads participate in cp.async load\n # ===================================================================\n prefetch_count = cutlass.min(NUM_STAGES - 1, num_v_tiles)\n for v_tiles in range(prefetch_count):\n stage = v_tiles % NUM_STAGES\n\n gSrc_tile = gSrc[(None, None, v_tiles)]\n sData_stage = sData[(None, None, stage)]\n\n thr_gSrc = thr_copy_load.partition_S(gSrc_tile)\n thr_sData = thr_copy_load.partition_D(sData_stage)\n\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n # Load q, k into BF16 registers using autovec_copy (contiguous pattern)\n q_tile = cute.local_tile(q, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_id))\n k_tile = cute.local_tile(k, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_id))\n cute.autovec_copy(q_tile, r_q_bf16)\n cute.autovec_copy(k_tile, r_k_bf16)\n\n # Convert BF16 to FP32\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = cutlass.Float32(r_q_bf16[i])\n r_k[i] = cutlass.Float32(r_k_bf16[i])\n\n # Load v into BF16 registers using autovec_copy, convert to FP32, store to sV\n v_tile = cute.local_tile(v, (1, 1, 1, vec_size), (i_n, i_t, i_hv, lane_id))\n cute.autovec_copy(v_tile, r_v_bf16)\n for i in cutlass.range_constexpr(vec_size):\n sV[k_start + i] = cutlass.Float32(r_v_bf16[i])\n\n cute.arch.barrier() # Ensure all threads finish writing to sV\n\n # ===================================================================\n # Compute g and beta (scalar values)\n # ===================================================================\n r_g = 0.0\n r_beta = 0.0\n if lane_id == 0:\n x = r_a + r_dt_bias\n beta_x = softplus_beta * x\n softplus_x = 0.0\n\n if beta_x <= softplus_threshold:\n # softplus(x) = (1/beta) * log(1 + exp(beta*x))\n # Compute in Float32\n exp_beta_x = cute.exp(beta_x, fastmath=True)\n log_input = cutlass.Float32(1.0 + exp_beta_x)\n log_result = cutlass.Float32(cute.log(log_input, fastmath=True))\n softplus_x = cutlass.Float32(\n (cutlass.Float32(1.0) / softplus_beta) * log_result\n )\n else:\n softplus_x = x\n\n # Compute g = exp(A_log) * softplus_x\n r_g_value = -cute.exp(r_A_log, fastmath=True) * softplus_x\n\n # Compute beta = 1 / (1 + exp(-b))\n r_beta = 1.0 / (1.0 + cute.exp(-r_b, fastmath=True))\n\n # Store to scalar (Float32)\n r_g = cute.exp(r_g_value, fastmath=True)\n\n r_g = cute.arch.shuffle_sync(r_g, 0)\n r_beta = cute.arch.shuffle_sync(r_beta, 0)\n\n if use_qk_l2norm:\n # Compute L2 norm of q and k\n sum_q = 0.0\n sum_k = 0.0\n for i in cutlass.range_constexpr(vec_size):\n sum_q += r_q[i] * r_q[i]\n sum_k += r_k[i] * r_k[i]\n # Warp-level reduction using butterfly shuffle\n for offset in [16, 8, 4, 2, 1]:\n sum_q += cute.arch.shuffle_sync_bfly(\n sum_q, offset=offset, mask=-1, mask_and_clamp=31\n )\n sum_k += cute.arch.shuffle_sync_bfly(\n sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n inv_norm_q = cute.rsqrt(sum_q + 1e-6, fastmath=True)\n inv_norm_k = cute.rsqrt(sum_k + 1e-6, fastmath=True)\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = r_q[i] * inv_norm_q\n r_k[i] = r_k[i] * inv_norm_k\n\n # Apply scaling in Float32\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = r_q[i] * scale\n\n # ===================================================================\n # Mainloop: All threads participate\n # ===================================================================\n for v_tiles in range(num_v_tiles):\n stage = v_tiles % NUM_STAGES\n\n # Step 1: Wait for current stage to complete\n cute.arch.cp_async_wait_group(0)\n cute.arch.barrier()\n\n # Step 2: Issue async load for next tile (after compute)\n next_v_tiles = v_tiles + prefetch_count\n if next_v_tiles < num_v_tiles:\n next_stage = next_v_tiles % NUM_STAGES\n\n gSrc_next = gSrc[(None, None, next_v_tiles)]\n sData_next = sData[(None, None, next_stage)]\n\n thr_gSrc = thr_copy_load.partition_S(gSrc_next)\n thr_sData = thr_copy_load.partition_D(sData_next)\n\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n # Step 3: Compute using data from current stage (contiguous access pattern)\n for row in cutlass.range_constexpr(0, TILE_V, 4):\n row_offset = tidx // 32\n sum_hk = 0.0\n\n # Load h from sData using 3D local_tile + autovec_copy (contiguous in K)\n sData_tile = cute.local_tile(\n sData, (1, vec_size, 1), (row + row_offset, lane_id, stage)\n )\n cute.autovec_copy(sData_tile, r_h)\n\n for i in cutlass.range_constexpr(vec_size):\n r_h[i] = r_h[i] * r_g\n sum_hk += r_h[i] * r_k[i]\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hk += cute.arch.shuffle_sync_bfly(\n sum_hk, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n v_new = sV[v_tiles * TILE_V + row + row_offset] - sum_hk\n v_new = v_new * r_beta\n\n sum_hq = 0.0\n for i in cutlass.range_constexpr(vec_size):\n r_h[i] += r_k[i] * v_new\n sum_hq += r_h[i] * r_q[i]\n\n # Write h back to state.\n if cutlass.const_expr(use_pool_indexing):\n gDst_tile = cute.local_tile(\n gDst,\n (1, 1, 1, vec_size, 1),\n (0, 0, row + row_offset, lane_id, v_tiles),\n )\n else:\n gDst_tile = cute.local_tile(\n gDst,\n (1, 1, vec_size, 1),\n (0, row + row_offset, lane_id, v_tiles),\n )\n cute.autovec_copy(r_h, gDst_tile)\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n sum_hq, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n o_idx = v_tiles * TILE_V + row + row_offset\n if lane_id == 0 and o_idx < V:\n sOutput[o_idx] = cutlass.BFloat16(sum_hq)\n\n # ===================================================================\n # Final writeback: Copy output from shared memory to global memory\n # All threads write (V=128, NUM_THREADS=128)\n # ===================================================================\n cute.arch.barrier() # Ensure all writes to sOutput are complete\n\n if tidx < V:\n o[(i_n, i_t, i_hv, tidx)] = sOutput[tidx]\n\n else:\n if tidx < V:\n o[(i_n, i_t, i_hv, tidx)] = cutlass.BFloat16(0.0)\n\n\n@cute.jit\ndef run_gdn_decode_kernel_small_batch_pretranspose(\n h0_source: cute.Tensor, # [B*HV, K, V]\n A_log: cute.Tensor,\n a: cute.Tensor,\n dt_bias: cute.Tensor,\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n b: cute.Tensor,\n o: cute.Tensor,\n h0_indices: cute.Tensor,\n h0_out_indices: cute.Tensor,\n cu_seqlens: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n use_pool_indexing: cutlass.Constexpr[bool] = False,\n stream: cuda.CUstream = None,\n):\n \"\"\"Launch original pipelined kernel for small batch pretranspose.\"\"\"\n # h0_source:\n # - non-pool: (B*HV, V, K)\n # - pool: (pool_size, HV, V, K)\n if cutlass.const_expr(use_pool_indexing):\n v_dim = h0_source.layout.shape[2]\n k_dim = h0_source.layout.shape[3]\n else:\n v_dim = h0_source.layout.shape[1]\n k_dim = h0_source.layout.shape[2]\n # Grid size: use B*HV (actual batch) not h0_source.shape[0] (which may be pool_size*HV)\n B = cute.size(q.shape[0])\n grid_batch = B * HV\n\n # Create cp.async copy with cache-global mode (bypass L1)\n copy_atom = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n cutlass.Float32,\n num_bits_per_copy=128, # 4 elements per copy\n )\n\n # Thread layout: 4 rows × 32 threads/row = 128 threads\n thread_layout = cute.make_layout(\n (4, 32), # 4 rows, 32 threads/row\n stride=(32, 1),\n )\n val_layout = cute.make_layout((1, 4)) # Each thread handles 4 elements\n\n tiled_copy_load = cute.make_tiled_copy_tv(copy_atom, thread_layout, val_layout)\n\n num_v_tiles = cute.ceil_div(v_dim, TILE_V)\n v_dim * k_dim * 4 / 1024 / 1024\n\n vec_size = (\n TILE_K // 32\n ) # Each thread in a warp processes this many elements (always 4 for TILE_K=128)\n\n # Create SMEM layout\n smem_layout_staged = cute.make_layout(\n (TILE_V, TILE_K, NUM_STAGES), stride=(TILE_K, 1, TILE_V * TILE_K)\n )\n\n # sData: TILE_V * TILE_K * NUM_STAGES * 4 bytes (Float32)\n # sV: K * 4 bytes (Float32)\n # sOutput: V * 2 bytes (BFloat16)\n smem_bytes = 4 * TILE_V * TILE_K * NUM_STAGES + 4 * k_dim + 2 * v_dim + 32\n\n gdn_decode_kernel_small_batch_pretranspose(\n tiled_copy_load,\n h0_source,\n smem_layout_staged,\n vec_size,\n num_v_tiles,\n A_log,\n a,\n dt_bias,\n q,\n k,\n v,\n b,\n o,\n h0_indices,\n h0_out_indices,\n cu_seqlens,\n softplus_beta,\n softplus_threshold,\n scale,\n HV,\n T,\n H,\n K,\n V,\n use_initial_state,\n use_qk_l2norm,\n is_varlen,\n use_pool_indexing,\n ).launch(\n grid=(grid_batch * NUM_BLOCKS_PER_STATE, 1, 1),\n block=[NUM_THREADS, 1, 1],\n smem=smem_bytes,\n stream=stream,\n )\n\n\n@cute.jit\ndef run_gdn_decode_kernel_big_batch_pretranspose(\n h0_source: cute.Tensor, # [B*HV, K, V]\n A_log: cute.Tensor,\n a: cute.Tensor,\n dt_bias: cute.Tensor,\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n b: cute.Tensor,\n o: cute.Tensor,\n h0_indices: cute.Tensor,\n h0_out_indices: cute.Tensor,\n cu_seqlens: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n use_pool_indexing: cutlass.Constexpr[bool] = False,\n stream: cuda.CUstream = None,\n):\n if cutlass.const_expr(use_pool_indexing):\n v_dim = h0_source.layout.shape[2]\n k_dim = h0_source.layout.shape[3]\n else:\n v_dim = h0_source.layout.shape[1]\n k_dim = h0_source.layout.shape[2]\n B = cute.size(q.shape[0])\n grid_batch = B * HV\n\n # Create cp.async copy with cache-global mode (bypass L1)\n copy_atom = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n cutlass.Float32,\n num_bits_per_copy=128, # 4 elements per copy\n )\n\n # Thread layout: 4 rows × 32 threads/row = 128 threads\n thread_layout = cute.make_layout(\n (4, 32), # 4 rows, 32 threads/row\n stride=(32, 1),\n )\n val_layout = cute.make_layout((1, 4)) # Each thread handles 4 elements\n\n tiled_copy_load = cute.make_tiled_copy_tv(copy_atom, thread_layout, val_layout)\n\n num_v_tiles = cute.ceil_div(v_dim, TILE_V)\n v_dim * k_dim * 4 / 1024 / 1024\n\n vec_size = (\n TILE_K // 32\n ) # Each thread in a warp processes this many elements (always 4 for TILE_K=128)\n\n # Create SMEM layout\n smem_layout_staged = cute.make_layout(\n (TILE_V, TILE_K, NUM_STAGES), stride=(TILE_K, 1, TILE_V * TILE_K)\n )\n\n # sData: TILE_V * TILE_K * NUM_STAGES * 4 bytes (Float32)\n # sV: K * 4 bytes (Float32)\n # sOutput: V * 2 bytes (BFloat16)\n smem_bytes = 4 * TILE_V * TILE_K * NUM_STAGES + 4 * k_dim + 2 * v_dim + 32\n\n gdn_decode_kernel_big_batch_pretranspose(\n tiled_copy_load,\n h0_source,\n smem_layout_staged,\n vec_size,\n num_v_tiles,\n A_log,\n a,\n dt_bias,\n q,\n k,\n v,\n b,\n o,\n h0_indices,\n h0_out_indices,\n cu_seqlens,\n softplus_beta,\n softplus_threshold,\n scale,\n HV,\n T,\n H,\n K,\n V,\n use_initial_state,\n use_qk_l2norm,\n is_varlen,\n use_pool_indexing,\n ).launch(\n grid=(grid_batch, 1, 1),\n block=[NUM_THREADS, 1, 1],\n smem=smem_bytes,\n stream=stream,\n )\n\n\n# ============================================================================\n# Compilation cache and public entry point\n# ============================================================================\n\n\n@functools.cache\ndef _get_compiled_decode_kernel(\n T: int,\n H: int,\n HV: int,\n K: int,\n V: int,\n dtype: torch.dtype,\n scale: float,\n use_qk_l2norm: bool,\n use_pool_indexing: bool = False,\n stride1: int = 0,\n stride2: int = 0,\n stride3: int = 0,\n):\n \"\"\"Cache compiled kernel for given configuration (pretranspose version).\"\"\"\n # This will be populated on first call\n return {}\n\n\ndef run_pretranspose_decode(\n h0_source: torch.Tensor,\n A_log: torch.Tensor,\n a: torch.Tensor,\n dt_bias: torch.Tensor,\n q: torch.Tensor,\n k: torch.Tensor,\n v: torch.Tensor,\n b: torch.Tensor,\n output: torch.Tensor,\n B: int,\n T: int,\n H: int,\n HV: int,\n K: int,\n V: int,\n scale: float,\n use_qk_l2norm: bool,\n use_pool_indexing: bool = False,\n initial_state_indices: Optional[torch.Tensor] = None,\n output_state_indices: Optional[torch.Tensor] = None,\n):\n \"\"\"Compile and execute the pretranspose decode kernel.\n\n Args:\n h0_source: State tensor of shape [B*HV, V, K], or [pool_size, HV, V, K]\n when use_pool_indexing=True.\n A_log, a, dt_bias, q, k, v, b: Input tensors.\n output: Pre-allocated output tensor [B, T, HV, V].\n B, T, H, HV, K, V: Dimension sizes.\n scale: Query scale factor.\n use_qk_l2norm: Whether to apply L2 normalization.\n use_pool_indexing: Whether to use pool-based indirect state indexing.\n initial_state_indices: Int32 indices into state pool, shape [B].\n Negative values indicate padding (kernel writes zeros).\n output_state_indices: Optional int32 indices for write destination, shape [B].\n When None, writes go to the same slot as initial_state_indices.\n \"\"\"\n # Compile kernel with TVM FFI (cached)\n if use_pool_indexing:\n stride0, stride1, stride2, stride3 = tuple(int(x) for x in h0_source.stride())\n assert stride0 % 4 == 0, (\n \"initial_state stride(0) must be a multiple of 4 FP32 elements \"\n f\"for 128-bit state copies, got stride(0)={stride0}\"\n )\n else:\n stride1 = stride2 = stride3 = 0\n cache_key = (\n T,\n H,\n HV,\n K,\n V,\n q.dtype,\n scale,\n use_qk_l2norm,\n use_pool_indexing,\n stride1,\n stride2,\n stride3,\n )\n cache = _get_compiled_decode_kernel(*cache_key)\n\n aux_map = cache.setdefault(\"aux\", {})\n aux_key = (B, q.device)\n if aux_key not in aux_map:\n aux_map[aux_key] = (\n torch.zeros(B, dtype=torch.int32, device=q.device),\n torch.zeros(B + 1, dtype=torch.int32, device=q.device),\n )\n default_h0_indices, cu_seqlens = aux_map[aux_key]\n\n if use_pool_indexing and initial_state_indices is not None:\n h0_indices = initial_state_indices.to(torch.int32)\n else:\n h0_indices = default_h0_indices\n # Resolve output indices: default to same as read indices\n if use_pool_indexing and output_state_indices is not None:\n h0_out_indices = output_state_indices.to(torch.int32)\n else:\n h0_out_indices = h0_indices\n\n if \"compiled\" not in cache:\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n\n if use_pool_indexing:\n # Pool capacity and the distance between slots do not affect codegen.\n # Keep the inner state layout static while accepting arbitrary pool\n # sizes and padded slot strides through the same compiled callable.\n sym_pool_size = cute.sym_int()\n sym_pool_stride0 = cute.sym_int64(divisibility=4)\n h0_source_tensor = cute.runtime.make_fake_tensor(\n cute.Float32,\n shape=(sym_pool_size, HV, V, K),\n stride=(sym_pool_stride0, stride1, stride2, stride3),\n assumed_align=16,\n )\n else:\n h0_source_tensor = from_dlpack(h0_source, assumed_align=16)\n h0_source_tensor = h0_source_tensor.mark_compact_shape_dynamic(\n mode=0, stride_order=(0, 1, 2), divisibility=1\n )\n A_log_tensor = from_dlpack(A_log, assumed_align=16)\n # mark_layout_dynamic accepts non-compact packed q/k/v (SGLang fused QKV).\n a_tensor = from_dlpack(a, assumed_align=16).mark_layout_dynamic()\n dt_bias_tensor = from_dlpack(dt_bias, assumed_align=16)\n q_tensor = from_dlpack(q, assumed_align=16).mark_layout_dynamic()\n k_tensor = from_dlpack(k, assumed_align=16).mark_layout_dynamic()\n v_tensor = from_dlpack(v, assumed_align=16).mark_layout_dynamic()\n b_tensor = from_dlpack(b, assumed_align=16).mark_layout_dynamic()\n o_tensor = from_dlpack(output, assumed_align=16).mark_layout_dynamic()\n h0_indices_tensor = from_dlpack(\n h0_indices, assumed_align=16\n ).mark_layout_dynamic()\n h0_out_indices_tensor = from_dlpack(\n h0_out_indices, assumed_align=16\n ).mark_layout_dynamic()\n cu_seqlens_tensor = from_dlpack(\n cu_seqlens, assumed_align=16\n ).mark_layout_dynamic()\n\n # Always use 8-CTA architecture (benchmarks show it's better for all batch sizes)\n run_func = run_gdn_decode_kernel_small_batch_pretranspose\n\n # Use TVM FFI to reduce runtime overhead\n compiled = cute.compile(\n run_func,\n h0_source_tensor,\n A_log_tensor,\n a_tensor,\n dt_bias_tensor,\n q_tensor,\n k_tensor,\n v_tensor,\n b_tensor,\n o_tensor,\n h0_indices_tensor,\n h0_out_indices_tensor,\n cu_seqlens_tensor,\n softplus_beta=1.0,\n softplus_threshold=20.0,\n scale=scale,\n HV=HV,\n T=T,\n H=H,\n K=K,\n V=V,\n use_initial_state=True,\n use_qk_l2norm=use_qk_l2norm,\n use_pool_indexing=use_pool_indexing,\n is_varlen=False,\n stream=stream,\n options=\"--enable-tvm-ffi\",\n )\n cache[\"compiled\"] = compiled\n else:\n compiled = cache[\"compiled\"]\n\n # Run kernel directly with PyTorch tensors (no from_dlpack needed)\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n cache[\"compiled\"](\n h0_source,\n A_log,\n a,\n dt_bias,\n q,\n k,\n v,\n b,\n output,\n h0_indices,\n h0_out_indices,\n cu_seqlens,\n stream,\n )\n"},"diff":{"kind":"string","value":"--- flashinfer/gdn_kernels/gdn_decode_pretranspose.py\n+++ flashinfer/gdn_kernels/gdn_decode_pretranspose.py\n@@ -905,8 +905,6 @@\n scale: float,\n use_qk_l2norm: bool,\n use_pool_indexing: bool = False,\n- pool_size: int = 0,\n- stride0: int = 0,\n stride1: int = 0,\n stride2: int = 0,\n stride3: int = 0,\n@@ -956,10 +954,13 @@\n \"\"\"\n # Compile kernel with TVM FFI (cached)\n if use_pool_indexing:\n- pool_size = int(h0_source.shape[0])\n stride0, stride1, stride2, stride3 = tuple(int(x) for x in h0_source.stride())\n+ assert stride0 % 4 == 0, (\n+ \"initial_state stride(0) must be a multiple of 4 FP32 elements \"\n+ f\"for 128-bit state copies, got stride(0)={stride0}\"\n+ )\n else:\n- pool_size = stride0 = stride1 = stride2 = stride3 = 0\n+ stride1 = stride2 = stride3 = 0\n cache_key = (\n T,\n H,\n@@ -970,8 +971,6 @@\n scale,\n use_qk_l2norm,\n use_pool_indexing,\n- pool_size,\n- stride0,\n stride1,\n stride2,\n stride3,\n@@ -1000,8 +999,20 @@\n if \"compiled\" not in cache:\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n \n- h0_source_tensor = from_dlpack(h0_source, assumed_align=16)\n- if not use_pool_indexing:\n+ if use_pool_indexing:\n+ # Pool capacity and the distance between slots do not affect codegen.\n+ # Keep the inner state layout static while accepting arbitrary pool\n+ # sizes and padded slot strides through the same compiled callable.\n+ sym_pool_size = cute.sym_int()\n+ sym_pool_stride0 = cute.sym_int64(divisibility=4)\n+ h0_source_tensor = cute.runtime.make_fake_tensor(\n+ cute.Float32,\n+ shape=(sym_pool_size, HV, V, K),\n+ stride=(sym_pool_stride0, stride1, stride2, stride3),\n+ assumed_align=16,\n+ )\n+ else:\n+ h0_source_tensor = from_dlpack(h0_source, assumed_align=16)\n h0_source_tensor = h0_source_tensor.mark_compact_shape_dynamic(\n mode=0, stride_order=(0, 1, 2), divisibility=1\n )"},"lines_added":{"kind":"number","value":19,"string":"19"},"lines_removed":{"kind":"number","value":8,"string":"8"},"files_in_commit":{"kind":"number","value":1,"string":"1"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["H800","RTX5090","SM120","SM90"],"string":"[\n \"H800\",\n \"RTX5090\",\n \"SM120\",\n \"SM90\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cute_dsl kernel file from flashinfer (flashinfer/gdn_kernels/gdn_decode_pretranspose.py).\n\nGoal: perf(gdn): reuse pretranspose kernels across pool capacity and stride\nTarget hardware: H800, RTX5090, SM120, SM90\nTarget models: unspecified\n\nCurrent file:\n```python\n\"\"\"\nCopyright (c) 2025 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nGated Delta Rule Decode Kernel - Pretranspose (V-major / K-last) Layout\n========================================================================\n\nCuTe-DSL implementation of GDN decode with state layout [B*HV, V, K].\nUses TMA pipelining and vectorized memory access for T=1 decode.\n\"\"\"\n\nimport functools\nfrom typing import Optional\n\nimport torch\nimport cutlass\nimport cutlass.cute as cute\nfrom cutlass.cute.nvgpu import cpasync\nfrom cutlass.cute.runtime import from_dlpack\nimport cuda.bindings.driver as cuda\n\n# ============================================================================\n# Constants for PRETRANSPOSE version ([B*HV, V, K])\n# ============================================================================\nTILE_V = 8\nTILE_K = 128\nNUM_STAGES = 2\nNUM_THREADS = 128 # 4 warps\nNUM_BLOCKS_PER_STATE = 8\n\n\n@cute.kernel\ndef gdn_decode_kernel_small_batch_pretranspose(\n tiled_copy_load: cute.TiledCopy,\n h0_source: cute.Tensor,\n smem_layout_staged: cute.Layout,\n vec_size: cutlass.Constexpr[int],\n num_v_tiles: cutlass.Constexpr[int],\n A_log: cute.Tensor, # [HV]\n a: cute.Tensor, # [B, T, HV]\n dt_bias: cute.Tensor, # [HV]\n q: cute.Tensor, # [B, T, H, K]\n k: cute.Tensor, # [B, T, H, K]\n v: cute.Tensor, # [B, T, HV, V]\n b: cute.Tensor, # [B, T, HV]\n o: cute.Tensor, # [B, T, HV, V] - output\n h0_indices: cute.Tensor, # [B] - initial state indices (read)\n h0_out_indices: cute.Tensor, # [B] - output state indices (write)\n cu_seqlens: cute.Tensor, # [B+1] - cumulative sequence lengths (for varlen)\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n use_pool_indexing: cutlass.Constexpr[bool] = False,\n):\n \"\"\"Each block uses pipeline to load one batch and vectorized writeback\"\"\"\n\n tidx, _, _ = cute.arch.thread_idx()\n lane_id = tidx % 32\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n block_idx, _, _ = cute.arch.block_idx()\n batch_idx = block_idx // NUM_BLOCKS_PER_STATE\n batch_inner = block_idx % NUM_BLOCKS_PER_STATE\n num_v_tiles_per_block = num_v_tiles // NUM_BLOCKS_PER_STATE\n i_n = batch_idx // HV\n i_hv = batch_idx % HV\n i_h = i_hv // (HV // H)\n i_t = 0\n\n smem = cutlass.utils.SmemAllocator()\n\n # ===================================================================\n # Allocate shared memory (using passed-in layout)\n # ===================================================================\n sData = smem.allocate_tensor(cutlass.Float32, smem_layout_staged, 128)\n\n # Allocate shared memory for output (size V) - use BFloat16 to match SGLang\n sOutput = smem.allocate_tensor(cutlass.BFloat16, cute.make_layout((V,)), 16)\n\n # Allocate shared memory for v values (size K, to reduce register usage)\n sV = smem.allocate_tensor(cutlass.Float32, cute.make_layout((V,)), 16)\n\n r_k = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n r_q = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n # r_v moved to shared memory (sV)\n r_h = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n # BF16 register tensors for vectorized q, k, v loading\n r_q_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n r_k_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n r_v_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n\n # Compute k_start for contiguous access pattern\n k_start = lane_id * vec_size\n\n # Read gate values from GMEM EARLY (before barrier, latency hidden during sync)\n r_A_log = cutlass.Float32(A_log[i_hv])\n r_a = cutlass.Float32(a[i_n, i_t, i_hv])\n r_dt_bias = cutlass.Float32(dt_bias[i_hv])\n r_b = cutlass.Float32(b[i_n, i_t, i_hv])\n\n cute.arch.barrier()\n\n # Compute state index: use pool indexing if enabled.\n if cutlass.const_expr(use_pool_indexing):\n # Widen pool indices to Int64 BEFORE they multiply ``stride[0]`` of\n # ``h0_source``. With Int32 indices, the per-slot element offset\n # ``pool_idx * stride[0]`` silently wraps once it exceeds INT32_MAX,\n # which makes the kernel issue loads/stores to unmapped global\n # addresses (illegal memory access). For example, the padded slot\n # stride 540672 used by vLLM for Qwen3.5-class GDN models crosses the\n # threshold at pool_idx >= ceil(2**31 / 540672) = 3972. See\n # ``tests/gdn/test_decode_pretranspose_noncontiguous_pool.py::\n # test_decode_pretranspose_pool_int64_offset`` for the regression test.\n pool_idx = cutlass.Int64(h0_indices[i_n])\n out_pool_idx = cutlass.Int64(h0_out_indices[i_n])\n # Redirect negative write indices to null buffer (slot 0)\n if out_pool_idx < 0:\n out_pool_idx = cutlass.Int64(0)\n else:\n pool_idx = 0\n out_pool_idx = 0\n\n if pool_idx >= 0:\n # Get current batch\n if cutlass.const_expr(use_pool_indexing):\n # h0_source layout: [pool_size, HV, V, K] (supports non-contiguous page stride)\n gSrc_batch = h0_source[(pool_idx, i_hv, None, None)] # (V, K)\n gDst = cute.local_tile(\n h0_source, (1, 1, TILE_V, TILE_K), (out_pool_idx, i_hv, None, 0)\n )\n else:\n # h0_source layout: [B*HV, V, K]\n state_idx = batch_idx\n gSrc_batch = h0_source[(state_idx, None, None)] # (V, K)\n gDst = cute.local_tile(h0_source, (1, TILE_V, TILE_K), (state_idx, None, 0))\n # Tile along V dimension\n gSrc = cute.local_tile(\n gSrc_batch, (TILE_V, TILE_K), (None, 0)\n ) # (TILE_V, TILE_K, num_v_tiles)\n\n # Partition for load\n thr_copy_load = tiled_copy_load.get_slice(tidx)\n\n # ===================================================================\n # Prefetch: All threads participate in cp.async load\n # ===================================================================\n start_v_tiles = batch_inner * num_v_tiles_per_block\n prefetch_count = cutlass.min(NUM_STAGES - 1, num_v_tiles_per_block)\n for v_tiles in range(start_v_tiles, start_v_tiles + prefetch_count):\n stage = (v_tiles - start_v_tiles) % NUM_STAGES\n\n gSrc_tile = gSrc[(None, None, v_tiles)]\n sData_stage = sData[(None, None, stage)]\n\n thr_gSrc = thr_copy_load.partition_S(gSrc_tile)\n thr_sData = thr_copy_load.partition_D(sData_stage)\n\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n # Load q, k into BF16 registers using autovec_copy (contiguous pattern)\n q_tile = cute.local_tile(q, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_id))\n k_tile = cute.local_tile(k, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_id))\n cute.autovec_copy(q_tile, r_q_bf16)\n cute.autovec_copy(k_tile, r_k_bf16)\n\n # Convert BF16 to FP32\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = cutlass.Float32(r_q_bf16[i])\n r_k[i] = cutlass.Float32(r_k_bf16[i])\n\n # Load v into BF16 registers using autovec_copy, convert to FP32, store to sV\n v_tile = cute.local_tile(v, (1, 1, 1, vec_size), (i_n, i_t, i_hv, lane_id))\n cute.autovec_copy(v_tile, r_v_bf16)\n for i in cutlass.range_constexpr(vec_size):\n sV[k_start + i] = cutlass.Float32(r_v_bf16[i])\n\n cute.arch.barrier() # Ensure all threads finish writing to sV\n\n # ===================================================================\n # Compute g and beta (scalar values)\n # ===================================================================\n r_g = 0.0\n r_beta = 0.0\n if lane_id == 0:\n x = r_a + r_dt_bias\n beta_x = softplus_beta * x\n softplus_x = 0.0\n\n if beta_x <= softplus_threshold:\n # softplus(x) = (1/beta) * log(1 + exp(beta*x))\n # Compute in Float32\n exp_beta_x = cute.exp(beta_x, fastmath=True)\n log_input = cutlass.Float32(1.0 + exp_beta_x)\n log_result = cutlass.Float32(cute.log(log_input, fastmath=True))\n softplus_x = cutlass.Float32(\n (cutlass.Float32(1.0) / softplus_beta) * log_result\n )\n else:\n softplus_x = x\n\n # Compute g = exp(A_log) * softplus_x\n r_g_value = -cute.exp(r_A_log, fastmath=True) * softplus_x\n\n # Compute beta = 1 / (1 + exp(-b))\n r_beta = 1.0 / (1.0 + cute.exp(-r_b, fastmath=True))\n\n # Store to scalar (Float32)\n r_g = cute.exp(r_g_value, fastmath=True)\n\n r_g = cute.arch.shuffle_sync(r_g, 0)\n r_beta = cute.arch.shuffle_sync(r_beta, 0)\n\n if use_qk_l2norm:\n # Compute L2 norm of q and k\n sum_q = 0.0\n sum_k = 0.0\n for i in cutlass.range_constexpr(vec_size):\n sum_q += r_q[i] * r_q[i]\n sum_k += r_k[i] * r_k[i]\n # Warp-level reduction using butterfly shuffle\n for offset in [16, 8, 4, 2, 1]:\n sum_q += cute.arch.shuffle_sync_bfly(\n sum_q, offset=offset, mask=-1, mask_and_clamp=31\n )\n sum_k += cute.arch.shuffle_sync_bfly(\n sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n inv_norm_q = cute.rsqrt(sum_q + 1e-6, fastmath=True)\n inv_norm_k = cute.rsqrt(sum_k + 1e-6, fastmath=True)\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = r_q[i] * inv_norm_q\n r_k[i] = r_k[i] * inv_norm_k\n\n # Apply scaling in Float32\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = r_q[i] * scale\n\n # ===================================================================\n # Mainloop: All threads participate\n # ===================================================================\n end_v_tiles = start_v_tiles + num_v_tiles_per_block\n for v_tiles in range(start_v_tiles, end_v_tiles):\n stage = (v_tiles - start_v_tiles) % NUM_STAGES\n\n # Step 1: Wait for current stage to complete\n cute.arch.cp_async_wait_group(0)\n cute.arch.barrier()\n\n # Step 2: Issue async load for next tile (after compute)\n next_v_tiles = v_tiles + prefetch_count\n if next_v_tiles < end_v_tiles:\n next_stage = (next_v_tiles - start_v_tiles) % NUM_STAGES\n\n gSrc_next = gSrc[(None, None, next_v_tiles)]\n sData_next = sData[(None, None, next_stage)]\n\n thr_gSrc = thr_copy_load.partition_S(gSrc_next)\n thr_sData = thr_copy_load.partition_D(sData_next)\n\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n # Step 3: Compute using data from current stage (contiguous access pattern)\n for row in cutlass.range_constexpr(0, TILE_V, 4):\n row_offset = tidx // 32\n sum_hk = 0.0\n\n # Load h from sData using 3D local_tile + autovec_copy (contiguous in K)\n sData_tile = cute.local_tile(\n sData, (1, vec_size, 1), (row + row_offset, lane_id, stage)\n )\n cute.autovec_copy(sData_tile, r_h)\n\n for i in cutlass.range_constexpr(vec_size):\n r_h[i] = r_h[i] * r_g\n sum_hk += r_h[i] * r_k[i]\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hk += cute.arch.shuffle_sync_bfly(\n sum_hk, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n v_new = sV[v_tiles * TILE_V + row + row_offset] - sum_hk\n v_new = v_new * r_beta\n\n sum_hq = 0.0\n for i in cutlass.range_constexpr(vec_size):\n r_h[i] += r_k[i] * v_new\n sum_hq += r_h[i] * r_q[i]\n\n # Write h to gDst using 4D local_tile + autovec_copy (contiguous in K)\n if cutlass.const_expr(use_pool_indexing):\n gDst_tile = cute.local_tile(\n gDst,\n (1, 1, 1, vec_size, 1),\n (0, 0, row + row_offset, lane_id, v_tiles),\n )\n else:\n gDst_tile = cute.local_tile(\n gDst,\n (1, 1, vec_size, 1),\n (0, row + row_offset, lane_id, v_tiles),\n )\n cute.autovec_copy(r_h, gDst_tile)\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n sum_hq, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n o_idx = v_tiles * TILE_V + row + row_offset\n if lane_id == 0 and o_idx < V:\n sOutput[o_idx] = cutlass.BFloat16(sum_hq)\n\n # ===================================================================\n # Final writeback: Copy output from shared memory to global memory\n # All threads write (V=128, NUM_THREADS=128)\n # ===================================================================\n cute.arch.barrier() # Ensure all writes to sOutput are complete\n if tidx >= start_v_tiles * TILE_V and tidx < end_v_tiles * TILE_V:\n o[(i_n, i_t, i_hv, tidx)] = sOutput[tidx]\n\n else:\n start_v_tiles = batch_inner * num_v_tiles_per_block\n end_v_tiles = start_v_tiles + num_v_tiles_per_block\n if tidx >= start_v_tiles * TILE_V and tidx < end_v_tiles * TILE_V:\n o[(i_n, i_t, i_hv, tidx)] = cutlass.BFloat16(0.0)\n\n\n@cute.kernel\ndef gdn_decode_kernel_big_batch_pretranspose(\n tiled_copy_load: cute.TiledCopy,\n h0_source: cute.Tensor,\n smem_layout_staged: cute.Layout,\n vec_size: cutlass.Constexpr[int],\n num_v_tiles: cutlass.Constexpr[int],\n A_log: cute.Tensor, # [HV]\n a: cute.Tensor, # [B, T, HV]\n dt_bias: cute.Tensor, # [HV]\n q: cute.Tensor, # [B, T, H, K]\n k: cute.Tensor, # [B, T, H, K]\n v: cute.Tensor, # [B, T, HV, V]\n b: cute.Tensor, # [B, T, HV]\n o: cute.Tensor, # [B, T, HV, V] - output\n h0_indices: cute.Tensor, # [B] - initial state indices (read)\n h0_out_indices: cute.Tensor, # [B] - output state indices (write)\n cu_seqlens: cute.Tensor, # [B+1] - cumulative sequence lengths (for varlen)\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n use_pool_indexing: cutlass.Constexpr[bool] = False,\n):\n \"\"\"Each block uses pipeline to load one batch and vectorized writeback\"\"\"\n\n tidx, _, _ = cute.arch.thread_idx()\n lane_id = tidx % 32\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n batch_idx, _, _ = cute.arch.block_idx()\n i_n = batch_idx // HV\n i_hv = batch_idx % HV\n i_h = i_hv // (HV // H)\n i_t = 0\n\n r_A_log = cutlass.Float32(A_log[i_hv])\n r_a = cutlass.Float32(a[i_n, i_t, i_hv])\n r_dt_bias = cutlass.Float32(dt_bias[i_hv])\n r_b = cutlass.Float32(b[i_n, i_t, i_hv])\n\n smem = cutlass.utils.SmemAllocator()\n\n # ===================================================================\n # Allocate shared memory (using passed-in layout)\n # ===================================================================\n sData = smem.allocate_tensor(cutlass.Float32, smem_layout_staged, 128)\n\n # Allocate shared memory for output (size V) - use BFloat16 to match SGLang\n sOutput = smem.allocate_tensor(cutlass.BFloat16, cute.make_layout((V,)), 16)\n\n # Allocate shared memory for v values (size K, to reduce register usage)\n sV = smem.allocate_tensor(cutlass.Float32, cute.make_layout((V,)), 16)\n\n r_k = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n r_q = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n # r_v moved to shared memory (sV)\n r_h = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n # BF16 register tensors for vectorized q, k, v loading\n r_q_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n r_k_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n r_v_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n\n # Compute k_start for contiguous access pattern\n k_start = lane_id * vec_size\n\n cute.arch.barrier()\n\n # Compute state index: use pool indexing if enabled.\n if cutlass.const_expr(use_pool_indexing):\n # Widen pool indices to Int64 BEFORE they multiply ``stride[0]`` of\n # ``h0_source``. With Int32 indices, the per-slot element offset\n # ``pool_idx * stride[0]`` silently wraps when it exceeds 2**31, which\n # makes the kernel issue loads/stores to unmapped global addresses\n # (illegal memory access). See the small-batch kernel above for the\n # full rationale.\n pool_idx = cutlass.Int64(h0_indices[i_n])\n out_pool_idx = cutlass.Int64(h0_out_indices[i_n])\n # Redirect negative write indices to null buffer (slot 0)\n if out_pool_idx < 0:\n out_pool_idx = cutlass.Int64(0)\n else:\n pool_idx = 0\n out_pool_idx = 0\n\n if pool_idx >= 0:\n # Get current state slice.\n if cutlass.const_expr(use_pool_indexing):\n # h0_source layout: [pool_size, HV, V, K] (supports non-contiguous page stride)\n gSrc_batch = h0_source[(pool_idx, i_hv, None, None)] # (V, K)\n gDst = cute.local_tile(\n h0_source, (1, 1, TILE_V, TILE_K), (out_pool_idx, i_hv, None, 0)\n )\n else:\n # h0_source layout: [B*HV, V, K]\n state_idx = batch_idx\n gSrc_batch = h0_source[(state_idx, None, None)] # (V, K)\n gDst = cute.local_tile(h0_source, (1, TILE_V, TILE_K), (state_idx, None, 0))\n # Tile along V dimension\n gSrc = cute.local_tile(\n gSrc_batch, (TILE_V, TILE_K), (None, 0)\n ) # (TILE_V, TILE_K, num_v_tiles)\n\n # Partition for load\n thr_copy_load = tiled_copy_load.get_slice(tidx)\n\n # ===================================================================\n # Prefetch: All threads participate in cp.async load\n # ===================================================================\n prefetch_count = cutlass.min(NUM_STAGES - 1, num_v_tiles)\n for v_tiles in range(prefetch_count):\n stage = v_tiles % NUM_STAGES\n\n gSrc_tile = gSrc[(None, None, v_tiles)]\n sData_stage = sData[(None, None, stage)]\n\n thr_gSrc = thr_copy_load.partition_S(gSrc_tile)\n thr_sData = thr_copy_load.partition_D(sData_stage)\n\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n # Load q, k into BF16 registers using autovec_copy (contiguous pattern)\n q_tile = cute.local_tile(q, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_id))\n k_tile = cute.local_tile(k, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_id))\n cute.autovec_copy(q_tile, r_q_bf16)\n cute.autovec_copy(k_tile, r_k_bf16)\n\n # Convert BF16 to FP32\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = cutlass.Float32(r_q_bf16[i])\n r_k[i] = cutlass.Float32(r_k_bf16[i])\n\n # Load v into BF16 registers using autovec_copy, convert to FP32, store to sV\n v_tile = cute.local_tile(v, (1, 1, 1, vec_size), (i_n, i_t, i_hv, lane_id))\n cute.autovec_copy(v_tile, r_v_bf16)\n for i in cutlass.range_constexpr(vec_size):\n sV[k_start + i] = cutlass.Float32(r_v_bf16[i])\n\n cute.arch.barrier() # Ensure all threads finish writing to sV\n\n # ===================================================================\n # Compute g and beta (scalar values)\n # ===================================================================\n r_g = 0.0\n r_beta = 0.0\n if lane_id == 0:\n x = r_a + r_dt_bias\n beta_x = softplus_beta * x\n softplus_x = 0.0\n\n if beta_x <= softplus_threshold:\n # softplus(x) = (1/beta) * log(1 + exp(beta*x))\n # Compute in Float32\n exp_beta_x = cute.exp(beta_x, fastmath=True)\n log_input = cutlass.Float32(1.0 + exp_beta_x)\n log_result = cutlass.Float32(cute.log(log_input, fastmath=True))\n softplus_x = cutlass.Float32(\n (cutlass.Float32(1.0) / softplus_beta) * log_result\n )\n else:\n softplus_x = x\n\n # Compute g = exp(A_log) * softplus_x\n r_g_value = -cute.exp(r_A_log, fastmath=True) * softplus_x\n\n # Compute beta = 1 / (1 + exp(-b))\n r_beta = 1.0 / (1.0 + cute.exp(-r_b, fastmath=True))\n\n # Store to scalar (Float32)\n r_g = cute.exp(r_g_value, fastmath=True)\n\n r_g = cute.arch.shuffle_sync(r_g, 0)\n r_beta = cute.arch.shuffle_sync(r_beta, 0)\n\n if use_qk_l2norm:\n # Compute L2 norm of q and k\n sum_q = 0.0\n sum_k = 0.0\n for i in cutlass.range_constexpr(vec_size):\n sum_q += r_q[i] * r_q[i]\n sum_k += r_k[i] * r_k[i]\n # Warp-level reduction using butterfly shuffle\n for offset in [16, 8, 4, 2, 1]:\n sum_q += cute.arch.shuffle_sync_bfly(\n sum_q, offset=offset, mask=-1, mask_and_clamp=31\n )\n sum_k += cute.arch.shuffle_sync_bfly(\n sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n inv_norm_q = cute.rsqrt(sum_q + 1e-6, fastmath=True)\n inv_norm_k = cute.rsqrt(sum_k + 1e-6, fastmath=True)\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = r_q[i] * inv_norm_q\n r_k[i] = r_k[i] * inv_norm_k\n\n # Apply scaling in Float32\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = r_q[i] * scale\n\n # ===================================================================\n # Mainloop: All threads participate\n # ===================================================================\n for v_tiles in range(num_v_tiles):\n stage = v_tiles % NUM_STAGES\n\n # Step 1: Wait for current stage to complete\n cute.arch.cp_async_wait_group(0)\n cute.arch.barrier()\n\n # Step 2: Issue async load for next tile (after compute)\n next_v_tiles = v_tiles + prefetch_count\n if next_v_tiles < num_v_tiles:\n next_stage = next_v_tiles % NUM_STAGES\n\n gSrc_next = gSrc[(None, None, next_v_tiles)]\n sData_next = sData[(None, None, next_stage)]\n\n thr_gSrc = thr_copy_load.partition_S(gSrc_next)\n thr_sData = thr_copy_load.partition_D(sData_next)\n\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n # Step 3: Compute using data from current stage (contiguous access pattern)\n for row in cutlass.range_constexpr(0, TILE_V, 4):\n row_offset = tidx // 32\n sum_hk = 0.0\n\n # Load h from sData using 3D local_tile + autovec_copy (contiguous in K)\n sData_tile = cute.local_tile(\n sData, (1, vec_size, 1), (row + row_offset, lane_id, stage)\n )\n cute.autovec_copy(sData_tile, r_h)\n\n for i in cutlass.range_constexpr(vec_size):\n r_h[i] = r_h[i] * r_g\n sum_hk += r_h[i] * r_k[i]\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hk += cute.arch.shuffle_sync_bfly(\n sum_hk, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n v_new = sV[v_tiles * TILE_V + row + row_offset] - sum_hk\n v_new = v_new * r_beta\n\n sum_hq = 0.0\n for i in cutlass.range_constexpr(vec_size):\n r_h[i] += r_k[i] * v_new\n sum_hq += r_h[i] * r_q[i]\n\n # Write h back to state.\n if cutlass.const_expr(use_pool_indexing):\n gDst_tile = cute.local_tile(\n gDst,\n (1, 1, 1, vec_size, 1),\n (0, 0, row + row_offset, lane_id, v_tiles),\n )\n else:\n gDst_tile = cute.local_tile(\n gDst,\n (1, 1, vec_size, 1),\n (0, row + row_offset, lane_id, v_tiles),\n )\n cute.autovec_copy(r_h, gDst_tile)\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n sum_hq, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n o_idx = v_tiles * TILE_V + row + row_offset\n if lane_id == 0 and o_idx < V:\n sOutput[o_idx] = cutlass.BFloat16(sum_hq)\n\n # ===================================================================\n # Final writeback: Copy output from shared memory to global memory\n # All threads write (V=128, NUM_THREADS=128)\n # ===================================================================\n cute.arch.barrier() # Ensure all writes to sOutput are complete\n\n if tidx < V:\n o[(i_n, i_t, i_hv, tidx)] = sOutput[tidx]\n\n else:\n if tidx < V:\n o[(i_n, i_t, i_hv, tidx)] = cutlass.BFloat16(0.0)\n\n\n@cute.jit\ndef run_gdn_decode_kernel_small_batch_pretranspose(\n h0_source: cute.Tensor, # [B*HV, K, V]\n A_log: cute.Tensor,\n a: cute.Tensor,\n dt_bias: cute.Tensor,\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n b: cute.Tensor,\n o: cute.Tensor,\n h0_indices: cute.Tensor,\n h0_out_indices: cute.Tensor,\n cu_seqlens: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n use_pool_indexing: cutlass.Constexpr[bool] = False,\n stream: cuda.CUstream = None,\n):\n \"\"\"Launch original pipelined kernel for small batch pretranspose.\"\"\"\n # h0_source:\n # - non-pool: (B*HV, V, K)\n # - pool: (pool_size, HV, V, K)\n if cutlass.const_expr(use_pool_indexing):\n v_dim = h0_source.layout.shape[2]\n k_dim = h0_source.layout.shape[3]\n else:\n v_dim = h0_source.layout.shape[1]\n k_dim = h0_source.layout.shape[2]\n # Grid size: use B*HV (actual batch) not h0_source.shape[0] (which may be pool_size*HV)\n B = cute.size(q.shape[0])\n grid_batch = B * HV\n\n # Create cp.async copy with cache-global mode (bypass L1)\n copy_atom = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n cutlass.Float32,\n num_bits_per_copy=128, # 4 elements per copy\n )\n\n # Thread layout: 4 rows × 32 threads/row = 128 threads\n thread_layout = cute.make_layout(\n (4, 32), # 4 rows, 32 threads/row\n stride=(32, 1),\n )\n val_layout = cute.make_layout((1, 4)) # Each thread handles 4 elements\n\n tiled_copy_load = cute.make_tiled_copy_tv(copy_atom, thread_layout, val_layout)\n\n num_v_tiles = cute.ceil_div(v_dim, TILE_V)\n v_dim * k_dim * 4 / 1024 / 1024\n\n vec_size = (\n TILE_K // 32\n ) # Each thread in a warp processes this many elements (always 4 for TILE_K=128)\n\n # Create SMEM layout\n smem_layout_staged = cute.make_layout(\n (TILE_V, TILE_K, NUM_STAGES), stride=(TILE_K, 1, TILE_V * TILE_K)\n )\n\n # sData: TILE_V * TILE_K * NUM_STAGES * 4 bytes (Float32)\n # sV: K * 4 bytes (Float32)\n # sOutput: V * 2 bytes (BFloat16)\n smem_bytes = 4 * TILE_V * TILE_K * NUM_STAGES + 4 * k_dim + 2 * v_dim + 32\n\n gdn_decode_kernel_small_batch_pretranspose(\n tiled_copy_load,\n h0_source,\n smem_layout_staged,\n vec_size,\n num_v_tiles,\n A_log,\n a,\n dt_bias,\n q,\n k,\n v,\n b,\n o,\n h0_indices,\n h0_out_indices,\n cu_seqlens,\n softplus_beta,\n softplus_threshold,\n scale,\n HV,\n T,\n H,\n K,\n V,\n use_initial_state,\n use_qk_l2norm,\n is_varlen,\n use_pool_indexing,\n ).launch(\n grid=(grid_batch * NUM_BLOCKS_PER_STATE, 1, 1),\n block=[NUM_THREADS, 1, 1],\n smem=smem_bytes,\n stream=stream,\n )\n\n\n@cute.jit\ndef run_gdn_decode_kernel_big_batch_pretranspose(\n h0_source: cute.Tensor, # [B*HV, K, V]\n A_log: cute.Tensor,\n a: cute.Tensor,\n dt_bias: cute.Tensor,\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n b: cute.Tensor,\n o: cute.Tensor,\n h0_indices: cute.Tensor,\n h0_out_indices: cute.Tensor,\n cu_seqlens: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n use_pool_indexing: cutlass.Constexpr[bool] = False,\n stream: cuda.CUstream = None,\n):\n if cutlass.const_expr(use_pool_indexing):\n v_dim = h0_source.layout.shape[2]\n k_dim = h0_source.layout.shape[3]\n else:\n v_dim = h0_source.layout.shape[1]\n k_dim = h0_source.layout.shape[2]\n B = cute.size(q.shape[0])\n grid_batch = B * HV\n\n # Create cp.async copy with cache-global mode (bypass L1)\n copy_atom = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n cutlass.Float32,\n num_bits_per_copy=128, # 4 elements per copy\n )\n\n # Thread layout: 4 rows × 32 threads/row = 128 threads\n thread_layout = cute.make_layout(\n (4, 32), # 4 rows, 32 threads/row\n stride=(32, 1),\n )\n val_layout = cute.make_layout((1, 4)) # Each thread handles 4 elements\n\n tiled_copy_load = cute.make_tiled_copy_tv(copy_atom, thread_layout, val_layout)\n\n num_v_tiles = cute.ceil_div(v_dim, TILE_V)\n v_dim * k_dim * 4 / 1024 / 1024\n\n vec_size = (\n TILE_K // 32\n ) # Each thread in a warp processes this many elements (always 4 for TILE_K=128)\n\n # Create SMEM layout\n smem_layout_staged = cute.make_layout(\n (TILE_V, TILE_K, NUM_STAGES), stride=(TILE_K, 1, TILE_V * TILE_K)\n )\n\n # sData: TILE_V * TILE_K * NUM_STAGES * 4 bytes (Float32)\n # sV: K * 4 bytes (Float32)\n # sOutput: V * 2 bytes (BFloat16)\n smem_bytes = 4 * TILE_V * TILE_K * NUM_STAGES + 4 * k_dim + 2 * v_dim + 32\n\n gdn_decode_kernel_big_batch_pretranspose(\n tiled_copy_load,\n h0_source,\n smem_layout_staged,\n vec_size,\n num_v_tiles,\n A_log,\n a,\n dt_bias,\n q,\n k,\n v,\n b,\n o,\n h0_indices,\n h0_out_indices,\n cu_seqlens,\n softplus_beta,\n softplus_threshold,\n scale,\n HV,\n T,\n H,\n K,\n V,\n use_initial_state,\n use_qk_l2norm,\n is_varlen,\n use_pool_indexing,\n ).launch(\n grid=(grid_batch, 1, 1),\n block=[NUM_THREADS, 1, 1],\n smem=smem_bytes,\n stream=stream,\n )\n\n\n# ============================================================================\n# Compilation cache and public entry point\n# ============================================================================\n\n\n@functools.cache\ndef _get_compiled_decode_kernel(\n T: int,\n H: int,\n HV: int,\n K: int,\n V: int,\n dtype: torch.dtype,\n scale: float,\n use_qk_l2norm: bool,\n use_pool_indexing: bool = False,\n pool_size: int = 0,\n stride0: int = 0,\n stride1: int = 0,\n stride2: int = 0,\n stride3: int = 0,\n):\n \"\"\"Cache compiled kernel for given configuration (pretranspose version).\"\"\"\n # This will be populated on first call\n return {}\n\n\ndef run_pretranspose_decode(\n h0_source: torch.Tensor,\n A_log: torch.Tensor,\n a: torch.Tensor,\n dt_bias: torch.Tensor,\n q: torch.Tensor,\n k: torch.Tensor,\n v: torch.Tensor,\n b: torch.Tensor,\n output: torch.Tensor,\n B: int,\n T: int,\n H: int,\n HV: int,\n K: int,\n V: int,\n scale: float,\n use_qk_l2norm: bool,\n use_pool_indexing: bool = False,\n initial_state_indices: Optional[torch.Tensor] = None,\n output_state_indices: Optional[torch.Tensor] = None,\n):\n \"\"\"Compile and execute the pretranspose decode kernel.\n\n Args:\n h0_source: State tensor of shape [B*HV, V, K], or [pool_size, HV, V, K]\n when use_pool_indexing=True.\n A_log, a, dt_bias, q, k, v, b: Input tensors.\n output: Pre-allocated output tensor [B, T, HV, V].\n B, T, H, HV, K, V: Dimension sizes.\n scale: Query scale factor.\n use_qk_l2norm: Whether to apply L2 normalization.\n use_pool_indexing: Whether to use pool-based indirect state indexing.\n initial_state_indices: Int32 indices into state pool, shape [B].\n Negative values indicate padding (kernel writes zeros).\n output_state_indices: Optional int32 indices for write destination, shape [B].\n When None, writes go to the same slot as initial_state_indices.\n \"\"\"\n # Compile kernel with TVM FFI (cached)\n if use_pool_indexing:\n pool_size = int(h0_source.shape[0])\n stride0, stride1, stride2, stride3 = tuple(int(x) for x in h0_source.stride())\n else:\n pool_size = stride0 = stride1 = stride2 = stride3 = 0\n cache_key = (\n T,\n H,\n HV,\n K,\n V,\n q.dtype,\n scale,\n use_qk_l2norm,\n use_pool_indexing,\n pool_size,\n stride0,\n stride1,\n stride2,\n stride3,\n )\n cache = _get_compiled_decode_kernel(*cache_key)\n\n aux_map = cache.setdefault(\"aux\", {})\n aux_key = (B, q.device)\n if aux_key not in aux_map:\n aux_map[aux_key] = (\n torch.zeros(B, dtype=torch.int32, device=q.device),\n torch.zeros(B + 1, dtype=torch.int32, device=q.device),\n )\n default_h0_indices, cu_seqlens = aux_map[aux_key]\n\n if use_pool_indexing and initial_state_indices is not None:\n h0_indices = initial_state_indices.to(torch.int32)\n else:\n h0_indices = default_h0_indices\n # Resolve output indices: default to same as read indices\n if use_pool_indexing and output_state_indices is not None:\n h0_out_indices = output_state_indices.to(torch.int32)\n else:\n h0_out_indices = h0_indices\n\n if \"compiled\" not in cache:\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n\n h0_source_tensor = from_dlpack(h0_source, assumed_align=16)\n if not use_pool_indexing:\n h0_source_tensor = h0_source_tensor.mark_compact_shape_dynamic(\n mode=0, stride_order=(0, 1, 2), divisibility=1\n )\n A_log_tensor = from_dlpack(A_log, assumed_align=16)\n # mark_layout_dynamic accepts non-compact packed q/k/v (SGLang fused QKV).\n a_tensor = from_dlpack(a, assumed_align=16).mark_layout_dynamic()\n dt_bias_tensor = from_dlpack(dt_bias, assumed_align=16)\n q_tensor = from_dlpack(q, assumed_align=16).mark_layout_dynamic()\n k_tensor = from_dlpack(k, assumed_align=16).mark_layout_dynamic()\n v_tensor = from_dlpack(v, assumed_align=16).mark_layout_dynamic()\n b_tensor = from_dlpack(b, assumed_align=16).mark_layout_dynamic()\n o_tensor = from_dlpack(output, assumed_align=16).mark_layout_dynamic()\n h0_indices_tensor = from_dlpack(\n h0_indices, assumed_align=16\n ).mark_layout_dynamic()\n h0_out_indices_tensor = from_dlpack(\n h0_out_indices, assumed_align=16\n ).mark_layout_dynamic()\n cu_seqlens_tensor = from_dlpack(\n cu_seqlens, assumed_align=16\n ).mark_layout_dynamic()\n\n # Always use 8-CTA architecture (benchmarks show it's better for all batch sizes)\n run_func = run_gdn_decode_kernel_small_batch_pretranspose\n\n # Use TVM FFI to reduce runtime overhead\n compiled = cute.compile(\n run_func,\n h0_source_tensor,\n A_log_tensor,\n a_tensor,\n dt_bias_tensor,\n q_tensor,\n k_tensor,\n v_tensor,\n b_tensor,\n o_tensor,\n h0_indices_tensor,\n h0_out_indices_tensor,\n cu_seqlens_tensor,\n softplus_beta=1.0,\n softplus_threshold=20.0,\n scale=scale,\n HV=HV,\n T=T,\n H=H,\n K=K,\n V=V,\n use_initial_state=True,\n use_qk_l2norm=use_qk_l2norm,\n use_pool_indexing=use_pool_indexing,\n is_varlen=False,\n stream=stream,\n options=\"--enable-tvm-ffi\",\n )\n cache[\"compiled\"] = compiled\n else:\n compiled = cache[\"compiled\"]\n\n # Run kernel directly with PyTorch tensors (no from_dlpack needed)\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n cache[\"compiled\"](\n h0_source,\n A_log,\n a,\n dt_bias,\n q,\n k,\n v,\n b,\n output,\n h0_indices,\n h0_out_indices,\n cu_seqlens,\n stream,\n )\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## 📌 Description\n\nMake the leading pool dimension of the GDN pretranspose path dynamic:\n\n- Treat pool capacity and `stride[0]` as runtime values.\n- Keep `HV/V/K` and inner strides compile-time static.\n- Remove pool capacity and leading stride from the compilation cache key.\n- Preserve 64-bit pool-offset arithmetic.\n\nThis allows one compiled kernel to be reused across non-contiguous state pools with different capacities and leading strides.\n\n## 🔍 Related Issues\n\nPartially addresses #4110.\n\n## 🚀 Pull Request Checklist\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit`.\n- [x] I have installed the hooks.\n- [x] I have run `pre-commit run --all-files`.\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All relevant tests are passing.\n\nValidated on H800/SM90a and RTX 5090/SM120, including non-contiguous pools, compile reuse, and large 64-bit offsets. No steady-state regression was observed; cold compilation time was reduced by approximately 62%.\n\n## Reviewer Notes\n\nOnly the outer pool mode is dynamic. Inner dimensions and strides remain static for kernel specialization.\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n\n## Summary by CodeRabbit\n\n* **Performance**\n * Improved pretranspose kernel reuse across different pool capacities and outer memory layouts, reducing unnecessary recompilation.\n * Preserved separate handling for layouts with differing inner strides.\n\n* **Reliability**\n * Added validation to reject pool slot strides that are not properly aligned for efficient data transfer.\n\n* **Tests**\n * Expanded coverage for cache reuse, layout variations, alignment validation, and environments where the optional kernel is unavailable.\n\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"e2e\", \"hardware\": \"H800/SM90a and RTX 5090/SM120\", \"model\": null, \"shape\": null, \"batch_size\": null, \"metric\": \"cold compilation time\", \"unit\": null, \"higher_is_better\": false, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.62, \"speedup\": 1.62}]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"number","value":1.62,"string":"1.62"}}},{"rowIdx":1087,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"53a1c3bd7a3f384d3a8fd1261cc99d80bcf9d188"},"date":{"kind":"string","value":"2026-08-12T20:56:49-07:00"},"pr_number":{"kind":"number","value":4038,"string":"4,038"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/4038"},"title":{"kind":"string","value":"perf(gemm): split-K, occupancy, and m=1 stream-GEMV decode tactics for mm_bf16_fp4 (#4038)"},"message":{"kind":"string","value":"perf(gemm): split-K, occupancy, and m=1 stream-GEMV decode tactics for mm_bf16_fp4 (#4038)\n\n## 📌 Description\n\n#3597 added `mm_bf16_fp4` (bf16 activations x nvfp4 weights) so vLLM can\nreplace Marlin, its default W4A16 backend, with a FlashInfer kernel; DGX\nSpark is the lead target. On decode shapes the kernel trailed Marlin for\ntwo reasons: small-n grids underfill the GPU, and at single-token\nbatches (m=1) too few resident warps per SM hide DRAM latency. This PR\naddresses both: m=1 decode beats or matches Marlin on every part we\nmeasured, and end-to-end serving of Qwen3.6-27B-NVFP4 flips from behind\nto ahead at batch 1 with no regression elsewhere.\n\n**What it does**\n\n- Adds split-K tactics (2/4/8 splits) to the autotuner space, offered\nonly when splitting shortens the grid's last wave by at least 25%.\nSplits write fp32 partials, and a PDL-chained reduce kernel sums them in\nfixed order, so results are deterministic run to run.\n- Adds occupancy tactics: 2 or 3 co-resident CTAs per SM trade pipeline\ndepth for latency hiding on weight-bound grids, plus occupancy 2\ncombined with split-K for narrow-n shapes.\n- Adds a streaming GEMV kernel (`gemv_bf16_fp4_sm12x.py`) for the\nbandwidth-bound m=1 case: no shared memory, no tensor cores, weights\nstream from global memory to registers with latency hidden by warp\ncount. It reads the same packed operands as the MMA kernel, so the\nautotuner picks between the two per shape.\n- Sizes GEMV split-K from the device: alongside the power-of-2 splits,\nthe menu carries a split targeting ~20 warps/SM (the measured saturation\npoint). Tactic indices become device-scoped, so the autotuner cache key\nnow carries the SM count.\n- Routes the no-autotune m=1 fallback onto the GEMV. Serving stacks do\nnot tune every shape (vLLM's warmup never captures the logits GEMM), so\nthe lm_head always takes this path.\n- Fixes kernel launch to pass no cluster dimensions: the boilerplate\n`cluster=[1,1,1]` routed launches through the cluster work distributor,\nwhose co-residency cap silently defeated the occupancy tactics on SM12x.\n\nNo public API changes. The one observable behavior change: untuned m=1\ncalls on SM12x now run the GEMV, whose output is bitwise different from\nthe MMA heuristic's but equally accurate and still deterministic.\n\n### Performance\n\n#### Split-K on the #3597 decode shapes (RTX PRO 6000 / DGX Spark / RTX\n5080)\n\nSingle-token decode GEMMs (m=1). The first table covers serving-class\nshapes (Llama-8B projection layers plus the #3597 example shape); the\nsecond covers #3597's own benchmark grid. Median GPU time over\nCUDA-graph replays with a cold L2 cache, as in serving. Baseline is\nvLLM's Marlin on the same GPU; FlashInfer runs with autotuning. Speedup\n= Marlin time / FlashInfer time. Each cell is a RTX PRO 6000 / DGX Spark\n/ RTX 5080 triple.\n\n| n x k | vs Marlin, before this PR | vs Marlin, with this PR |\n|--:|:--:|:--:|\n| 2048x7168 | 0.57 / 1.00 / 0.47 | **1.36** / **1.02** / **0.78** |\n| 4096x4096 | 0.75 / 0.91 / 0.90 | **1.06** / **1.00** / 0.90 |\n| 4096x14336 | 0.60 / 0.91 / 0.78 | **0.98** / **1.00** / 0.78 |\n| 14336x4096 | 0.97 / 1.00 / 0.86 | 0.97 / 1.00 / 0.86 |\n| 10304x2688 | 0.78 / 0.98 / 0.96 | 0.78 / 0.98 / 0.96 |\n\nThe same comparison over #3597's benchmark grid (4096x4096 appears in\nthe table above):\n\n| n x k | vs Marlin, before this PR | vs Marlin, with this PR |\n|--:|:--:|:--:|\n| 512x2048 | 2.09 / 0.95 / 0.95 | **4.48** / **1.43** / **2.30** |\n| 512x4096 | 1.19 / 0.70 / 0.56 | **3.61** / **1.26** / **1.88** |\n| 1024x2048 | 1.26 / 0.98 / 0.70 | **2.39** / **1.03** / **1.32** |\n| 1024x4096 | 0.99 / 0.86 / 0.49 | **2.72** / **1.04** / **1.21** |\n| 2048x512 | 1.86 / 1.25 / 1.19 | 1.86 / 1.25 / 1.19 |\n| 2048x1024 | 1.36 / 1.16 / 0.90 | **1.40** / 1.16 / **1.02** |\n| 2048x2048 | 1.17 / 1.11 / 0.70 | **1.72** / **1.02**\\* (1.11) /\n**0.97** |\n| 2048x4096 | 0.73 / 1.08 / 0.54 | **1.48** / **1.04**\\* (1.08) /\n**0.84** |\n| 4096x512 | 1.40 / 1.01 / 1.38 | 1.40 / **0.95**\\* (1.01) / 1.38 |\n| 4096x1024 | 1.41 / 0.93 / 1.18 | 1.41 / **0.95** / 1.18 |\n| 4096x2048 | 0.95 / 0.95 / 1.06 | 0.95 / **1.00** / 1.06 |\n| 131072x2048 | 0.98 / 0.97 / 0.90 | 0.98 / 0.97 / 0.90 |\n| 248320x2048 | 0.98 / 1.00 / 0.93 | 0.98 / 1.00 / 0.93 |\n\n- Bold marks the cells this PR changes (the tuner picks a new split-K\ntactic); unbolded picks perform as before.\n- \\* These three cells are tuner mis-picks, not kernel regressions: an\naccurate pick would keep #3597's pre-existing non-split config, and the\nvalue in parentheses is what that config achieves. The Reviewer Notes\nexplain the cause.\n- On the serving shapes, the RTX 5080 column stays below 1.0 even where\nthis PR helps. Profiling of the larger losses points to activation\nre-reads through L2, a separate problem from grid fill and out of scope\nhere.\n\n#### Qwen3.6-27B-NVFP4 decode GEMMs at m=1 (RTX 5080, DGX Spark)\n\nSame methodology as above; speedup = Marlin time / FlashInfer time.\n\n| GEMM (n x k) | RTX 5080 | DGX Spark |\n|--|:--:|:--:|\n| gate_up 34816x5120 | **1.03** | 1.00 |\n| down 5120x17408 | **1.03** | 1.00 |\n| lm_head 248320x5120 | **1.04**\\* | **1.04** |\n\n\\* Marlin's lm_head repack does not fit on the 16 GB RTX 5080, so this\ncell compares against the best in-tree MMA tactic. Spark ties at its\nbandwidth floor on the first two shapes.\n\n#### End-to-end vLLM serving of Qwen3.6-27B-NVFP4 (RTX PRO 6000)\n\nFull serving A/B, FlashInfer leg vs Marlin leg under identical settings,\naiperf output-token throughput, ratio = FlashInfer / Marlin: batch-1\ndecode 1.011x, low-concurrency speculative decode 1.08 to 1.11x ahead,\nand every other cell at parity within run-to-run noise (0.978 to 1.014x)\nwith no regression beyond it.\n\n## 🔍 Related Issues\n\nFollow-up to #3597.\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\nNew tests:\n\n- Every enumerated tactic (MMA and GEMV) is checked against a reference\nand for bit-exact run-to-run determinism.\n- Unit tests pin the fallback selectors' picks; one test drives\ntactic=-1 through the GEMV fallback end to end.\n- Full test file passes on RTX 5080, RTX PRO 6000, and GB10.\n\n## Reviewer Notes\n\n- Most gains require autotuning, which serving frameworks run at\nstartup. The no-autotune fallback picks match the tuner's choices on\nevery part we measured.\n- The autotuner times candidates with a warm L2 while decode serving\nruns cold, so it can over-rank split tactics; the 25% last-wave guard\ncompensates but does not fully close it (the three Spark cells in the\ngrid table). This measurement gap is general and deserves its own issue.\n- The fallback picks add JIT-compiled kernel variants per decode shape\nclass, cached in-process only; that cost amortizes to once per machine\nwhen this module adopts the #3874 CuTe-DSL disk cache, as #4029 did for\nthe sibling `mm_fp4` path. The GEMV's device-derived splits widen this\nsurface, so the follow-up is worth prioritizing.\n- Other FlashInfer cute-dsl kernels also pass `cluster=[1,1,1]` at\nlaunch and inherit the same co-residency cap; they are worth a separate\naudit.\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n- **New Features**\n- Added split-K support for bf16 × fp4 matrix multiplication to improve\nperformance across varying workloads.\n- Added a dedicated SM12x GEMV path for efficient single-row operations.\n- Added automatic tuning for split counts, occupancy, and\ndevice-specific execution strategies.\n- Added support for FP16 GEMV outputs and deterministic partial-result\nreduction.\n\n- **Bug F"},"path":{"kind":"string","value":"flashinfer/gemm/gemm_bf16_fp4_cute_dsl.py"},"language":{"kind":"string","value":"cute_dsl"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"# SPDX-FileCopyrightText: Copyright (c) 2025 by FlashInfer team.\n# SPDX-License-Identifier: Apache-2.0\n\"\"\"CuTe-DSL backend for the bf16 x fp4 GEMM (weight repack / kernel launch).\"\"\"\n\nfrom typing import List, Optional, Tuple, cast\n\nimport torch\n\nfrom ..autotuner import (\n AutoTuner,\n ConstraintSpec,\n DynamicTensorSpec,\n OptimizationProfile,\n TunableRunner,\n TuningConfig,\n)\nfrom ..fused_moe.utils import (\n get_hybrid_num_tokens_buckets,\n map_to_hybrid_bucket_uncapped,\n)\nfrom .gemm_base import _check_cute_dsl_availability\nfrom .gemm_bf16_fp4 import _unswizzle_sf_128x4\n\n_BF16_FP4_ALPHA_ONE_CACHE: dict = {}\n\n\ndef _prepare_bf16_fp4_alpha(\n alpha: Optional[torch.Tensor], device: torch.device\n) -> torch.Tensor:\n \"\"\"Normalize ``alpha`` to a ``(1,) float32`` tensor for the kernel.\"\"\"\n if alpha is None:\n cached = _BF16_FP4_ALPHA_ONE_CACHE.get(device)\n if cached is None:\n cached = torch.tensor([1.0], dtype=torch.float32, device=device)\n _BF16_FP4_ALPHA_ONE_CACHE[device] = cached\n return cached\n if alpha.dim() == 0:\n return alpha.to(device=device, dtype=torch.float32).unsqueeze(0)\n return alpha.to(device=device, dtype=torch.float32).reshape(1)\n\n\ndef _select_bf16_fp4_tile_shape(\n m: int, n: int, k: int\n) -> Tuple[Tuple[int, int, int], Tuple[int, int, int]]:\n \"\"\"Pick a CTA tile shape AND MMA atom_layout for the cute-DSL bf16 x fp4 kernel.\n\n Returns ``(tile_shape_mnk, atom_layout)``.\n\n Tile shape selection:\n tile_M choice\n * M <= 16 (and tile_K=128 path): use tile_M=16 with atom_layout\n (1,2,1). Halves wasted M-rows vs tile_M=32, and a 1-M-warp\n layout removes the duplicate dequant that (2,2,1) suffers from.\n * 16 < M <= 32: use tile_M=32 with atom_layout (2,2,1). Smaller\n MMA + epilogue waste than tile_M=64.\n * M > 32: use tile_M=64 with atom_layout (2,2,1) -- standard tile,\n more rows to amortize across.\n\n tile_K choice\n * K % 128 == 0: tile_K=128 (halves K-tile count and barrier\n overhead).\n * Otherwise: tile_K=64.\n\n Why atom_layout differs:\n * (2,2,1) (default for tile_M >= 32): 4 MMA warps as 2 M x 2 N --\n well-tested cute layout, but the 2 M-warps redundantly dequant\n the same B values into their own register files (~50% waste in\n dequant compute).\n * (1,2,1) (used for tile_M=16): 2 MMA warps as 1 M x 2 N -- no\n M-warp duplication. Permutation_m = 16, so tile_M must be 16.\n \"\"\"\n tile_k = 128 if k % 128 == 0 else 64\n if m <= 16 and tile_k == 128:\n return ((16, 64, 128), (1, 2, 1))\n if m <= 32:\n return ((32, 64, tile_k), (2, 2, 1))\n return ((64, 64, tile_k), (2, 2, 1))\n\n\n_CUTE_DSL_MM_BF16_FP4_KERNEL_CACHE: dict = {}\n\n\ndef _get_cute_dsl_bf16_fp4_gemm(\n tile_shape_mnk: Tuple[int, int, int],\n a_dtype: torch.dtype,\n c_dtype: torch.dtype,\n atom_layout: Tuple[int, int, int] = (2, 2, 1),\n pipeline_depth: int = 1,\n use_fp16_mma: int = 1,\n enable_pdl: bool = True,\n tile_swizzle: int = 1,\n):\n # Normalize to a tuple (callers may pass a list) so the cache key is hashable.\n atom_layout = cast(Tuple[int, int, int], tuple(atom_layout))\n pipeline_depth = int(pipeline_depth)\n use_fp16_mma = int(use_fp16_mma)\n enable_pdl = bool(enable_pdl)\n tile_swizzle = int(tile_swizzle)\n cache_key = (\n tile_shape_mnk,\n a_dtype,\n c_dtype,\n atom_layout,\n pipeline_depth,\n use_fp16_mma,\n enable_pdl,\n tile_swizzle,\n )\n cached = _CUTE_DSL_MM_BF16_FP4_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n return cached\n\n _check_cute_dsl_availability()\n\n import cutlass\n import cutlass.cute as cute\n from flashinfer.cute_dsl.utils import get_max_active_clusters\n\n from .kernels.cute_dsl.dense_gemm_bf16_fp4_blackwell import (\n BlackwellDenseGemmBf16Fp4Kernel,\n )\n\n from ..cute_dsl.utils import torch_to_cutlass_dtype\n\n a_cutlass_dtype = torch_to_cutlass_dtype(a_dtype)\n c_cutlass_dtype = torch_to_cutlass_dtype(c_dtype)\n\n sym_m = cute.sym_int()\n sym_k = cute.sym_int()\n sym_n = cute.sym_int()\n sym_k_tiles = cute.sym_int()\n sym_n_packed = cute.sym_int()\n\n a_fake = cute.runtime.make_fake_compact_tensor(\n a_cutlass_dtype, (sym_m, sym_k), stride_order=(1, 0), assumed_align=16\n )\n b_packed_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (sym_k_tiles, sym_n_packed),\n stride_order=(1, 0),\n assumed_align=16,\n )\n b_sf_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_k_tiles, sym_n), stride_order=(1, 0), assumed_align=16\n )\n c_fake = cute.runtime.make_fake_compact_tensor(\n c_cutlass_dtype, (sym_m, sym_n), stride_order=(1, 0), assumed_align=16\n )\n alpha_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32, (1,), assumed_align=4\n )\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n\n gemm = BlackwellDenseGemmBf16Fp4Kernel(\n acc_dtype=cutlass.Float32,\n tile_shape_mnk=tile_shape_mnk,\n atom_layout=atom_layout,\n pipeline_depth=pipeline_depth,\n use_fp16_mma=use_fp16_mma,\n enable_pdl=enable_pdl,\n tile_swizzle=tile_swizzle,\n )\n max_active_clusters = get_max_active_clusters(1)\n\n compiled = cute.compile(\n gemm.wrapper,\n a_fake,\n b_packed_fake,\n b_sf_fake,\n c_fake,\n alpha_fake,\n 1, # l (batch)\n max_active_clusters,\n stream_fake,\n options=\"--opt-level 2 --enable-tvm-ffi\",\n )\n\n _CUTE_DSL_MM_BF16_FP4_KERNEL_CACHE[cache_key] = compiled\n return compiled\n\n\ndef _e4m3_to_s0e5m3(sf_u8: torch.Tensor) -> torch.Tensor:\n \"\"\"Reformat a uint8 tensor of E4M3 scale bytes to S0E5M3 bytes.\n Used in cute-dsl backend for faster in-kernel scale decode.\n \"\"\"\n f16 = sf_u8.contiguous().view(torch.float8_e4m3fn).to(torch.float16)\n bits = f16.view(torch.int16).to(torch.int32) & 0xFFFF\n return ((bits >> 7) & 0xFF).to(torch.uint8)\n\n\n_CUTE_DSL_PACK_TILE_K: int = 16 # K-tile size = MMA K-block size\n_CUTE_DSL_PACK_TILE_N: int = 64 # N-tile size = kernel tile_N\n_CUTE_DSL_PACK_INTS_PER_TILE: int = 128 # int32s per (16K x 64N) repack block\n\n\ndef _cute_dsl_pack_fp4_weight(b: torch.Tensor) -> torch.Tensor:\n \"\"\"Repack a packed FP4 weight for the bf16 x fp4 cute-DSL kernel.\"\"\"\n if b.dtype != torch.uint8:\n b = b.view(torch.uint8)\n\n k_half, n = b.shape\n k = k_half * 2\n if k % _CUTE_DSL_PACK_TILE_K != 0:\n raise ValueError(f\"K must be a multiple of {_CUTE_DSL_PACK_TILE_K} (got K={k})\")\n if n % _CUTE_DSL_PACK_TILE_N != 0:\n raise ValueError(f\"N must be a multiple of {_CUTE_DSL_PACK_TILE_N} (got N={n})\")\n\n device = b.device\n k_tiles = k // _CUTE_DSL_PACK_TILE_K\n n_tiles = n // _CUTE_DSL_PACK_TILE_N\n k_half_per_tile = _CUTE_DSL_PACK_TILE_K // 2 # 8 packed K-rows per tile\n\n u32_pos = torch.arange(\n _CUTE_DSL_PACK_INTS_PER_TILE, device=device, dtype=torch.long\n )\n u32_idx_local = u32_pos % 2\n lane = (u32_pos // 2) % 32\n n_warp_idx = u32_pos // 64\n\n tc_col = lane // 4 # in [0, 8)\n tc_row_half = lane % 4 # tc_row = tc_row_half * 2 in {0, 2, 4, 6}\n base_n = n_warp_idx * 8 + tc_col # in [0, 16)\n\n byte_k_half_offset = torch.tensor([0, 4, 0, 4], device=device, dtype=torch.long)\n n_offset_stack = torch.tensor(\n [[0, 0, 16, 16], [32, 32, 48, 48]], device=device, dtype=torch.long\n )\n byte_n_offset = n_offset_stack[u32_idx_local] # (128, 4)\n\n # Source byte within the (8, 64) tile for each (u32_pos, byte_idx).\n k_half_in_tile = tc_row_half[:, None] + byte_k_half_offset[None, :] # (128, 4)\n n_in_tile = base_n[:, None] + byte_n_offset # (128, 4)\n within_idx = (k_half_in_tile * _CUTE_DSL_PACK_TILE_N + n_in_tile).reshape(\n -1\n ) # (512,) flat index into a row-major (8, 64) tile\n\n # (K/2, N) -> (K_tiles, 8, N_tiles, 64) -> (K_tiles, N_tiles, 8*64) so the\n # 512 source bytes of each tile are contiguous, then gather them in\n # (u32_pos, byte_idx) order.\n tile_bytes = (\n b.reshape(k_tiles, k_half_per_tile, n_tiles, _CUTE_DSL_PACK_TILE_N)\n .permute(0, 2, 1, 3)\n .reshape(k_tiles, n_tiles, k_half_per_tile * _CUTE_DSL_PACK_TILE_N)\n )\n gathered = tile_bytes[:, :, within_idx].reshape(\n k_tiles, n_tiles, _CUTE_DSL_PACK_INTS_PER_TILE, 4\n )\n\n # Each 4 consecutive bytes are one little-endian int32 (byte 0 = bits 0-7),\n # exactly what the kernel's 32-bit loads read -- reinterpret in place.\n return gathered.view(torch.int32).reshape(\n k_tiles, n_tiles * _CUTE_DSL_PACK_INTS_PER_TILE\n )\n\n\ndef _prepare_cute_dsl(\n b: torch.Tensor,\n b_descale: torch.Tensor,\n alpha: Optional[torch.Tensor],\n block_size: int,\n) -> Tuple[torch.Tensor, torch.Tensor, Optional[torch.Tensor]]:\n \"\"\"cute-DSL-backend prep: repack the weight + unswizzle the SF.\n\n Produces the bespoke layout the cute-DSL kernel consumes:\n * weight: ``(K // 16, N * 2)`` int32 (see :func:`_cute_dsl_pack_fp4_weight`).\n * SF: ``(K // block_size, N)`` uint8 -- per-block scales reformatted to\n S0E5M3, the format the cute-DSL kernel decodes.\n ``alpha`` is passed through unchanged (the compute step normalizes it\n to a ``(1,) float32`` scalar). Pair the returned tensors with\n ``mm_bf16_fp4(a, b, b_descale, alpha, backend='cute-dsl')``.\n \"\"\"\n n = int(b.shape[0])\n k = int(b.shape[1]) * 2\n k_sf = k // block_size\n\n b_kn = b.t().contiguous()\n b_packed = _cute_dsl_pack_fp4_weight(b_kn) # (K//16, N*2) int32\n\n linear_sf = _unswizzle_sf_128x4(b_descale, n, k_sf) # (N, K_sf) uint8\n sf_ksf_n = linear_sf.t().contiguous() # (K_sf, N) uint8 (E4M3)\n sf_ksf_n = _e4m3_to_s0e5m3(sf_ksf_n) # -> S0E5M3\n return b_packed, sf_ksf_n, alpha\n\n\ndef _bf16_fp4_cute_dsl_tactic_configs(\n n: int, k: int\n) -> List[Tuple[Tuple[int, int, int], Tuple[int, int, int], int, int, int]]:\n \"\"\"Enumerate cute-DSL tactic configs for a given ``(N, K)``.\n\n Returns a list of ``(tile_shape_mnk, atom_layout, pipeline_depth,\n use_fp16_mma)`` tuples.\n \"\"\"\n tile_k = 128 if k % 128 == 0 else 64\n\n # (tile_M, atom_layout) shapes the kernel is designed/validated for, at the\n # default tile_N=64; a tile_N=128 variant is added below for very large N.\n tile_m_atoms: List[Tuple[int, Tuple[int, int, int]]] = []\n if tile_k == 128:\n tile_m_atoms.append((16, (1, 2, 1)))\n tile_m_atoms.append((32, (2, 2, 1)))\n tile_m_atoms.append((64, (2, 2, 1)))\n\n configs: List[Tuple[Tuple[int, int, int], Tuple[int, int, int], int, int, int]] = []\n seen = set()\n\n def add(tile_m, atom, pdepth, fp16, tile_n=64, tk=None, swz=1):\n cfg = (\n (tile_m, tile_n, tile_k if tk is None else tk),\n atom,\n pdepth,\n fp16,\n swz,\n )\n key = (cfg[0], cfg[1], pdepth, fp16, swz)\n if key not in seen:\n seen.add(key)\n configs.append(cfg)\n\n base_tile_m, base_atom = tile_m_atoms[0]\n add(base_tile_m, base_atom, 1, 1) # 0: baseline\n add(base_tile_m, base_atom, 0, 1) # no dequant prefetch (helps short-K)\n for tile_m, atom in tile_m_atoms[1:]:\n add(tile_m, atom, 1, 1)\n\n # tile_N=128 halves the (m,n)-tile count but needs large wave count.\n if tile_k == 128 and n >= 12288 and n % 128 == 0:\n add(base_tile_m, base_atom, 1, 1, tile_n=128)\n\n # tile_K=64 has more ab stages, but requires larger problem size.\n if tile_k == 128 and n >= 8192:\n add(base_tile_m, base_atom, 1, 1, tile_n=64, tk=64)\n\n # tile_M=128 (taller M tile, atom (2,2,1)) -- the large-M *prefill* lever.\n if tile_k == 128:\n add(128, (2, 2, 1), 1, 1)\n\n # Threadblock swizzle (tile_swizzle=8) -- for large-M prefill.\n if tile_k == 128 and n * k >= 16 * 1024 * 1024:\n add(64, (2, 2, 1), 1, 1, swz=8)\n if tile_k == 128:\n add(128, (2, 2, 1), 1, 1, swz=8)\n\n # tile_N=128 (with tile_M=64, atom (2,2,1)) -- large shapes.\n if tile_k == 128 and n % 128 == 0 and n >= 4096:\n add(64, (2, 2, 1), 1, 1, tile_n=128, swz=8)\n add(64, (2, 2, 1), 1, 1, tile_n=128, swz=1)\n\n return configs\n\n\n_BF16_FP4_CUTE_DSL_TUNING_CONFIG = TuningConfig(\n dynamic_tensor_specs=(\n DynamicTensorSpec(\n (0,), # a_tensor_index\n (0,), # M dimension\n get_hybrid_num_tokens_buckets,\n map_to_hybrid_bucket_uncapped,\n ),\n ),\n constraint_specs=(\n ConstraintSpec(\n 5, # out_tensor_index follows M\n 0,\n lambda shapes: shapes[0][0],\n ),\n ),\n)\n\n\ndef _cute_dsl_bf16_fp4_runner(enable_pdl: bool = True) -> TunableRunner:\n \"\"\"Build a ``CuteDslBf16Fp4Runner`` for the cute-DSL bf16 x fp4 GEMM.\"\"\"\n\n class CuteDslBf16Fp4Runner(TunableRunner):\n def get_cache_key_extras(self, inputs: List[torch.Tensor]) -> tuple:\n a, b, _, _, out_dtype, _, block_size = inputs\n n = int(b.shape[1]) // 2\n k = int(b.shape[0]) * int(block_size)\n return (out_dtype, n, k)\n\n def get_valid_tactics(\n self,\n inputs: List[torch.Tensor],\n profile: OptimizationProfile,\n ) -> List[int]:\n _, b, _, _, _, _, block_size = inputs\n n = int(b.shape[1]) // 2\n k = int(b.shape[0]) * int(block_size)\n return list(range(len(_bf16_fp4_cute_dsl_tactic_configs(n, k))))\n\n def forward(\n self,\n inputs: List[torch.Tensor],\n tactic: int = -1,\n do_preparation: bool = False,\n **kwargs,\n ) -> torch.Tensor:\n a, b, b_sf_u8, alpha_for_launch, out_dtype, out, block_size = inputs\n n = int(b.shape[1]) // 2\n k = int(b.shape[0]) * int(block_size)\n m = int(a.shape[0])\n if tactic < 0:\n # Fallback == pre-autotuner heuristic (M-aware), default knobs.\n tile_shape_mnk, atom_layout = _select_bf16_fp4_tile_shape(m, n, k)\n pipeline_depth, use_fp16_mma, tile_swizzle = 1, 1, 1\n else:\n (\n tile_shape_mnk,\n atom_layout,\n pipeline_depth,\n use_fp16_mma,\n tile_swizzle,\n ) = _bf16_fp4_cute_dsl_tactic_configs(n, k)[tactic]\n compiled = _get_cute_dsl_bf16_fp4_gemm(\n tile_shape_mnk,\n a.dtype,\n out_dtype,\n atom_layout,\n pipeline_depth,\n use_fp16_mma,\n enable_pdl=enable_pdl,\n tile_swizzle=tile_swizzle,\n )\n compiled(a, b, b_sf_u8, out, alpha_for_launch)\n return out\n\n return CuteDslBf16Fp4Runner()\n\n\ndef _compute_cute_dsl(\n a: torch.Tensor,\n b: torch.Tensor,\n b_descale: torch.Tensor,\n alpha: Optional[torch.Tensor],\n out_dtype: torch.dtype,\n out: Optional[torch.Tensor],\n block_size: int,\n enable_pdl: bool = True,\n) -> torch.Tensor:\n \"\"\"cute-DSL-backend compute: dispatch to the compiled Blackwell kernel.\n\n ``b`` is the packed ``(K // 16, N * 2)`` int32 weight and\n ``b_descale`` the ``(K // block_size, N)`` uint8 SF in S0E5M3 format\n (reformatted from FP8-E4M3 by :func:`_e4m3_to_s0e5m3`) returned by\n :func:`_prepare_cute_dsl`.\n \"\"\"\n if b.dtype != torch.int32:\n raise TypeError(\n f\"cute-dsl backend expects the packed int32 weight from \"\n f\"prepare_bf16_fp4_weights(..., backend='cute-dsl'); got {b.dtype}.\"\n )\n if out_dtype != a.dtype:\n raise NotImplementedError(\n f\"cute-dsl backend requires out_dtype == a.dtype (got \"\n f\"out_dtype={out_dtype}, a.dtype={a.dtype}). Use the cudnn \"\n f\"backend for a mismatched output dtype.\"\n )\n k_tiles = int(b.shape[0])\n n = int(b.shape[1]) // 2\n k = k_tiles * block_size\n m = int(a.shape[0])\n if a.shape[1] != k:\n raise ValueError(\n f\"a.shape[1]={a.shape[1]} but k inferred from prepared b.shape=\"\n f\"{tuple(b.shape)} is {k}\"\n )\n\n if out is None:\n out = torch.empty((m, n), device=a.device, dtype=out_dtype)\n else:\n if tuple(out.shape) != (m, n):\n raise ValueError(f\"out shape {tuple(out.shape)} != expected {(m, n)}\")\n if out.dtype != out_dtype:\n raise TypeError(f\"out dtype {out.dtype} != requested out_dtype {out_dtype}\")\n\n b_sf_u8 = b_descale.view(torch.uint8).contiguous()\n alpha_for_launch = _prepare_bf16_fp4_alpha(alpha, a.device)\n\n tuner = AutoTuner.get()\n runner = _cute_dsl_bf16_fp4_runner(enable_pdl=enable_pdl)\n inputs = [a, b, b_sf_u8, alpha_for_launch, out_dtype, out, block_size]\n chosen_runner, tactic = tuner.choose_one(\n \"bf16_fp4_cute_dsl_gemm\",\n [runner],\n _BF16_FP4_CUTE_DSL_TUNING_CONFIG,\n inputs,\n )\n chosen_runner(inputs=inputs, tactic=tactic)\n return out\n"},"after_code":{"kind":"string","value":"# SPDX-FileCopyrightText: Copyright (c) 2025 by FlashInfer team.\n# SPDX-License-Identifier: Apache-2.0\n\"\"\"CuTe-DSL backend for the bf16 x fp4 GEMM (weight repack / kernel launch).\"\"\"\n\nimport functools\nfrom typing import List, Optional, Tuple, cast\n\nimport torch\n\nfrom ..autotuner import (\n AutoTuner,\n ConstraintSpec,\n DynamicTensorSpec,\n OptimizationProfile,\n TunableRunner,\n TuningConfig,\n)\nfrom ..fused_moe.utils import (\n get_hybrid_num_tokens_buckets,\n map_to_hybrid_bucket_uncapped,\n)\nfrom ..utils import _get_cache_buf, get_compute_capability, get_device_sm_count\nfrom .gemm_base import _check_cute_dsl_availability\nfrom .gemm_bf16_fp4 import _unswizzle_sf_128x4\n\n_BF16_FP4_ALPHA_ONE_CACHE: dict = {}\n\n\ndef _prepare_bf16_fp4_alpha(\n alpha: Optional[torch.Tensor], device: torch.device\n) -> torch.Tensor:\n \"\"\"Normalize ``alpha`` to a ``(1,) float32`` tensor for the kernel.\"\"\"\n if alpha is None:\n cached = _BF16_FP4_ALPHA_ONE_CACHE.get(device)\n if cached is None:\n cached = torch.tensor([1.0], dtype=torch.float32, device=device)\n _BF16_FP4_ALPHA_ONE_CACHE[device] = cached\n return cached\n if alpha.dim() == 0:\n return alpha.to(device=device, dtype=torch.float32).unsqueeze(0)\n return alpha.to(device=device, dtype=torch.float32).reshape(1)\n\n\ndef _select_bf16_fp4_tile_shape(\n m: int, n: int, k: int\n) -> Tuple[Tuple[int, int, int], Tuple[int, int, int]]:\n \"\"\"Pick a CTA tile shape AND MMA atom_layout for the cute-DSL bf16 x fp4 kernel.\n\n Returns ``(tile_shape_mnk, atom_layout)``.\n\n Tile shape selection:\n tile_M choice\n * M <= 16 (and tile_K=128 path): use tile_M=16 with atom_layout\n (1,2,1). Halves wasted M-rows vs tile_M=32, and a 1-M-warp\n layout removes the duplicate dequant that (2,2,1) suffers from.\n * 16 < M <= 32: use tile_M=32 with atom_layout (2,2,1). Smaller\n MMA + epilogue waste than tile_M=64.\n * M > 32: use tile_M=64 with atom_layout (2,2,1) -- standard tile,\n more rows to amortize across.\n\n tile_K choice\n * K % 128 == 0: tile_K=128 (halves K-tile count and barrier\n overhead).\n * Otherwise: tile_K=64.\n\n Why atom_layout differs:\n * (2,2,1) (default for tile_M >= 32): 4 MMA warps as 2 M x 2 N --\n well-tested cute layout, but the 2 M-warps redundantly dequant\n the same B values into their own register files (~50% waste in\n dequant compute).\n * (1,2,1) (used for tile_M=16): 2 MMA warps as 1 M x 2 N -- no\n M-warp duplication. Permutation_m = 16, so tile_M must be 16.\n \"\"\"\n tile_k = 128 if k % 128 == 0 else 64\n if m <= 16 and tile_k == 128:\n return ((16, 64, 128), (1, 2, 1))\n if m <= 32:\n return ((32, 64, tile_k), (2, 2, 1))\n return ((64, 64, tile_k), (2, 2, 1))\n\n\ndef _select_bf16_fp4_k_splits(\n m: int, n: int, k: int, tile_shape_mnk: Tuple[int, int, int], sm_count: int\n) -> int:\n \"\"\"Static split-K pick for the no-autotune fallback: only clear-win\n underfill grids get a split, closer calls are left to the autotuner.\"\"\"\n tile_m, tile_n, tile_k = tile_shape_mnk\n if tile_m != (16 if tile_k == 128 else 32):\n # Split only the tile shapes that the tactic space pairs with splits.\n return 1\n tiles = -(-m // tile_m) * -(-n // tile_n)\n if tiles * 3 > sm_count:\n return 1\n k_tiles = k // tile_k\n for splits in (8, 4, 2):\n if splits <= k_tiles and tiles * splits <= sm_count:\n return splits\n return 1\n\n\n# Stream-GEMV residency window (warps/SM): below the floor DRAM latency is\n# uncovered, far above the ceiling splits just multiply partial traffic.\n_GEMV_MIN_WARPS_PER_SM = 12\n_GEMV_MAX_WARPS_PER_SM = 96\n\n\ndef _bf16_fp4_gemv_knee_split(n: int, k: int, sm_count: int) -> int:\n \"\"\"Smallest K-split reaching ~20 warps/SM, where throughput saturates\n and deeper splits only add partial traffic; capped under one full wave\n (6 CTAs/SM = 1536-thread limit / 256) and at >= 4 K-tiles per split.\"\"\"\n ctas = -(-(n // 64) // 8)\n cap = max(1, min(int(0.95 * sm_count * 6 / ctas), (k // 16) // 4))\n return min(-(-20 * sm_count // (n // 64)), cap)\n\n\ndef _select_bf16_fp4_gemv_split(\n n: int, k: int, cc_major: int, sm_count: int\n) -> Optional[int]:\n \"\"\"m=1 no-autotune fallback pick: the stream GEMV where it applies,\n ``None`` for the MMA heuristic. Serving stacks do not tune every\n shape (vLLM never tunes the logits GEMM), so untuned m=1 matters.\"\"\"\n if cc_major != 12 or n % 64 != 0 or k // 16 < 4:\n return None\n split = _bf16_fp4_gemv_knee_split(n, k, sm_count)\n warps_per_sm = (n // 64) * split / sm_count\n if not _GEMV_MIN_WARPS_PER_SM <= warps_per_sm <= _GEMV_MAX_WARPS_PER_SM:\n return None\n return split\n\n\n_CUTE_DSL_MM_BF16_FP4_KERNEL_CACHE: dict = {}\n\n\ndef _get_cute_dsl_bf16_fp4_gemm(\n tile_shape_mnk: Tuple[int, int, int],\n a_dtype: torch.dtype,\n c_dtype: torch.dtype,\n atom_layout: Tuple[int, int, int] = (2, 2, 1),\n pipeline_depth: int = 1,\n use_fp16_mma: int = 1,\n enable_pdl: bool = True,\n tile_swizzle: int = 1,\n k_splits: int = 1,\n occupancy: int = 1,\n):\n # Normalize to a tuple (callers may pass a list) so the cache key is hashable.\n atom_layout = cast(Tuple[int, int, int], tuple(atom_layout))\n pipeline_depth = int(pipeline_depth)\n use_fp16_mma = int(use_fp16_mma)\n enable_pdl = bool(enable_pdl)\n tile_swizzle = int(tile_swizzle)\n k_splits = int(k_splits)\n occupancy = int(occupancy)\n cache_key = (\n tile_shape_mnk,\n a_dtype,\n c_dtype,\n atom_layout,\n pipeline_depth,\n use_fp16_mma,\n enable_pdl,\n tile_swizzle,\n k_splits,\n occupancy,\n )\n cached = _CUTE_DSL_MM_BF16_FP4_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n return cached\n\n _check_cute_dsl_availability()\n\n import cutlass\n import cutlass.cute as cute\n from flashinfer.cute_dsl.utils import get_max_active_clusters\n\n from .kernels.cute_dsl.dense_gemm_bf16_fp4_blackwell import (\n BlackwellDenseGemmBf16Fp4Kernel,\n )\n\n from ..cute_dsl.utils import torch_to_cutlass_dtype\n\n a_cutlass_dtype = torch_to_cutlass_dtype(a_dtype)\n c_cutlass_dtype = torch_to_cutlass_dtype(c_dtype)\n\n sym_m = cute.sym_int()\n sym_k = cute.sym_int()\n sym_n = cute.sym_int()\n sym_k_tiles = cute.sym_int()\n sym_n_packed = cute.sym_int()\n\n a_fake = cute.runtime.make_fake_compact_tensor(\n a_cutlass_dtype, (sym_m, sym_k), stride_order=(1, 0), assumed_align=16\n )\n b_packed_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (sym_k_tiles, sym_n_packed),\n stride_order=(1, 0),\n assumed_align=16,\n )\n b_sf_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_k_tiles, sym_n), stride_order=(1, 0), assumed_align=16\n )\n c_fake = cute.runtime.make_fake_compact_tensor(\n c_cutlass_dtype, (sym_m, sym_n), stride_order=(1, 0), assumed_align=16\n )\n sym_partial = cute.sym_int()\n partial_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32, (sym_partial,), assumed_align=16\n )\n alpha_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32, (1,), assumed_align=4\n )\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n\n gemm = BlackwellDenseGemmBf16Fp4Kernel(\n acc_dtype=cutlass.Float32,\n tile_shape_mnk=tile_shape_mnk,\n atom_layout=atom_layout,\n # At occupancy 3 the SMEM budget per CTA only fits 2 ab stages next\n # to the default 4-stage epilogue; a 2-stage epilogue keeps 3.\n epi_stage=2 if occupancy >= 3 else 4,\n pipeline_depth=pipeline_depth,\n use_fp16_mma=use_fp16_mma,\n enable_pdl=enable_pdl,\n tile_swizzle=tile_swizzle,\n k_splits=k_splits,\n occupancy=occupancy,\n )\n # The persistent grid launches occupancy CTAs per SM; the kernel's stage\n # budget (_compute_stages) shrinks SMEM per CTA so they co-reside.\n max_active_clusters = get_max_active_clusters(1) * occupancy\n\n compiled = cute.compile(\n gemm.wrapper,\n a_fake,\n b_packed_fake,\n b_sf_fake,\n c_fake,\n partial_fake,\n alpha_fake,\n 1, # l (batch)\n max_active_clusters,\n stream_fake,\n options=\"--opt-level 2 --enable-tvm-ffi\",\n )\n\n _CUTE_DSL_MM_BF16_FP4_KERNEL_CACHE[cache_key] = compiled\n return compiled\n\n\ndef _get_cute_dsl_bf16_fp4_gemv(\n splits: int,\n a_dtype: torch.dtype,\n c_dtype: torch.dtype,\n enable_pdl: bool = True,\n):\n \"\"\"Compile-cache the m=1 streaming GEMV (same call signature as the\n compiled MMA kernel, so the runner dispatches either transparently).\"\"\"\n splits = int(splits)\n enable_pdl = bool(enable_pdl)\n cache_key = (\"gemv\", splits, a_dtype, c_dtype, enable_pdl)\n cached = _CUTE_DSL_MM_BF16_FP4_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n return cached\n\n _check_cute_dsl_availability()\n\n import cutlass\n import cutlass.cute as cute\n\n from .kernels.cute_dsl.gemv_bf16_fp4_sm12x import GemvBf16Fp4Sm12x\n\n from ..cute_dsl.utils import torch_to_cutlass_dtype\n\n sym = [cute.sym_int() for _ in range(6)]\n a_fake = cute.runtime.make_fake_compact_tensor(\n torch_to_cutlass_dtype(a_dtype),\n (sym[0], sym[1]),\n stride_order=(1, 0),\n assumed_align=16,\n )\n b_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (sym[2], sym[3]), stride_order=(1, 0), assumed_align=16\n )\n sf_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym[2], sym[4]), stride_order=(1, 0), assumed_align=16\n )\n c_fake = cute.runtime.make_fake_compact_tensor(\n torch_to_cutlass_dtype(c_dtype),\n (sym[0], sym[4]),\n stride_order=(1, 0),\n assumed_align=16,\n )\n partial_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32, (sym[5],), assumed_align=16\n )\n alpha_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32, (1,), assumed_align=4\n )\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n\n compiled = cute.compile(\n GemvBf16Fp4Sm12x(splits=splits, enable_pdl=enable_pdl),\n a_fake,\n b_fake,\n sf_fake,\n c_fake,\n partial_fake,\n alpha_fake,\n stream_fake,\n options=\"--opt-level 2 --enable-tvm-ffi\",\n )\n\n _CUTE_DSL_MM_BF16_FP4_KERNEL_CACHE[cache_key] = compiled\n return compiled\n\n\ndef _e4m3_to_s0e5m3(sf_u8: torch.Tensor) -> torch.Tensor:\n \"\"\"Reformat a uint8 tensor of E4M3 scale bytes to S0E5M3 bytes.\n Used in cute-dsl backend for faster in-kernel scale decode.\n \"\"\"\n f16 = sf_u8.contiguous().view(torch.float8_e4m3fn).to(torch.float16)\n bits = f16.view(torch.int16).to(torch.int32) & 0xFFFF\n return ((bits >> 7) & 0xFF).to(torch.uint8)\n\n\n_CUTE_DSL_PACK_TILE_K: int = 16 # K-tile size = MMA K-block size\n_CUTE_DSL_PACK_TILE_N: int = 64 # N-tile size = kernel tile_N\n_CUTE_DSL_PACK_INTS_PER_TILE: int = 128 # int32s per (16K x 64N) repack block\n\n\ndef _cute_dsl_pack_fp4_weight(b: torch.Tensor) -> torch.Tensor:\n \"\"\"Repack a packed FP4 weight for the bf16 x fp4 cute-DSL kernel.\"\"\"\n if b.dtype != torch.uint8:\n b = b.view(torch.uint8)\n\n k_half, n = b.shape\n k = k_half * 2\n if k % _CUTE_DSL_PACK_TILE_K != 0:\n raise ValueError(f\"K must be a multiple of {_CUTE_DSL_PACK_TILE_K} (got K={k})\")\n if n % _CUTE_DSL_PACK_TILE_N != 0:\n raise ValueError(f\"N must be a multiple of {_CUTE_DSL_PACK_TILE_N} (got N={n})\")\n\n device = b.device\n k_tiles = k // _CUTE_DSL_PACK_TILE_K\n n_tiles = n // _CUTE_DSL_PACK_TILE_N\n k_half_per_tile = _CUTE_DSL_PACK_TILE_K // 2 # 8 packed K-rows per tile\n\n u32_pos = torch.arange(\n _CUTE_DSL_PACK_INTS_PER_TILE, device=device, dtype=torch.long\n )\n u32_idx_local = u32_pos % 2\n lane = (u32_pos // 2) % 32\n n_warp_idx = u32_pos // 64\n\n tc_col = lane // 4 # in [0, 8)\n tc_row_half = lane % 4 # tc_row = tc_row_half * 2 in {0, 2, 4, 6}\n base_n = n_warp_idx * 8 + tc_col # in [0, 16)\n\n byte_k_half_offset = torch.tensor([0, 4, 0, 4], device=device, dtype=torch.long)\n n_offset_stack = torch.tensor(\n [[0, 0, 16, 16], [32, 32, 48, 48]], device=device, dtype=torch.long\n )\n byte_n_offset = n_offset_stack[u32_idx_local] # (128, 4)\n\n # Source byte within the (8, 64) tile for each (u32_pos, byte_idx).\n k_half_in_tile = tc_row_half[:, None] + byte_k_half_offset[None, :] # (128, 4)\n n_in_tile = base_n[:, None] + byte_n_offset # (128, 4)\n within_idx = (k_half_in_tile * _CUTE_DSL_PACK_TILE_N + n_in_tile).reshape(\n -1\n ) # (512,) flat index into a row-major (8, 64) tile\n\n # (K/2, N) -> (K_tiles, 8, N_tiles, 64) -> (K_tiles, N_tiles, 8*64) so the\n # 512 source bytes of each tile are contiguous, then gather them in\n # (u32_pos, byte_idx) order.\n tile_bytes = (\n b.reshape(k_tiles, k_half_per_tile, n_tiles, _CUTE_DSL_PACK_TILE_N)\n .permute(0, 2, 1, 3)\n .reshape(k_tiles, n_tiles, k_half_per_tile * _CUTE_DSL_PACK_TILE_N)\n )\n gathered = tile_bytes[:, :, within_idx].reshape(\n k_tiles, n_tiles, _CUTE_DSL_PACK_INTS_PER_TILE, 4\n )\n\n # Each 4 consecutive bytes are one little-endian int32 (byte 0 = bits 0-7),\n # exactly what the kernel's 32-bit loads read -- reinterpret in place.\n return gathered.view(torch.int32).reshape(\n k_tiles, n_tiles * _CUTE_DSL_PACK_INTS_PER_TILE\n )\n\n\ndef _prepare_cute_dsl(\n b: torch.Tensor,\n b_descale: torch.Tensor,\n alpha: Optional[torch.Tensor],\n block_size: int,\n) -> Tuple[torch.Tensor, torch.Tensor, Optional[torch.Tensor]]:\n \"\"\"cute-DSL-backend prep: repack the weight + unswizzle the SF.\n\n Produces the bespoke layout the cute-DSL kernel consumes:\n * weight: ``(K // 16, N * 2)`` int32 (see :func:`_cute_dsl_pack_fp4_weight`).\n * SF: ``(K // block_size, N)`` uint8 -- per-block scales reformatted to\n S0E5M3, the format the cute-DSL kernel decodes.\n ``alpha`` is passed through unchanged (the compute step normalizes it\n to a ``(1,) float32`` scalar). Pair the returned tensors with\n ``mm_bf16_fp4(a, b, b_descale, alpha, backend='cute-dsl')``.\n \"\"\"\n n = int(b.shape[0])\n k = int(b.shape[1]) * 2\n k_sf = k // block_size\n\n b_kn = b.t().contiguous()\n b_packed = _cute_dsl_pack_fp4_weight(b_kn) # (K//16, N*2) int32\n\n linear_sf = _unswizzle_sf_128x4(b_descale, n, k_sf) # (N, K_sf) uint8\n sf_ksf_n = linear_sf.t().contiguous() # (K_sf, N) uint8 (E4M3)\n sf_ksf_n = _e4m3_to_s0e5m3(sf_ksf_n) # -> S0E5M3\n return b_packed, sf_ksf_n, alpha\n\n\n@functools.cache\ndef _bf16_fp4_cute_dsl_tactic_configs(\n n: int, k: int, sm_count: int\n) -> Tuple[\n Tuple[Tuple[int, int, int], Tuple[int, int, int], int, int, int, int, int, str],\n ...,\n]:\n \"\"\"Enumerate cute-DSL tactic configs for a given ``(N, K)``.\n\n Returns a tuple of ``(tile_shape_mnk, atom_layout, pipeline_depth,\n use_fp16_mma, tile_swizzle, k_splits, occupancy, kind)`` entries,\n where ``kind`` selects the kernel: ``\"mma\"`` (the dense GEMM, all\n fields live) or ``\"gemv\"`` (the m=1 streaming kernel, which only\n reads ``k_splits``). The gemv entries include device-derived splits,\n so a tactic index is only meaningful for the ``(n, k, sm_count)`` it\n was enumerated with.\n \"\"\"\n tile_k = 128 if k % 128 == 0 else 64\n\n # (tile_M, atom_layout) shapes the kernel is designed/validated for, at the\n # default tile_N=64; a tile_N=128 variant is added below for very large N.\n tile_m_atoms: List[Tuple[int, Tuple[int, int, int]]] = []\n if tile_k == 128:\n tile_m_atoms.append((16, (1, 2, 1)))\n tile_m_atoms.append((32, (2, 2, 1)))\n tile_m_atoms.append((64, (2, 2, 1)))\n\n configs: List[\n Tuple[Tuple[int, int, int], Tuple[int, int, int], int, int, int, int, int, str]\n ] = []\n seen = set()\n\n def add(tile_m, atom, pdepth, fp16, tile_n=64, tk=None, swz=1, splits=1, occ=1):\n cfg = (\n (tile_m, tile_n, tile_k if tk is None else tk),\n atom,\n pdepth,\n fp16,\n swz,\n splits,\n occ,\n \"mma\",\n )\n key = (cfg[0], cfg[1], pdepth, fp16, swz, splits, occ)\n if key not in seen:\n seen.add(key)\n configs.append(cfg)\n\n base_tile_m, base_atom = tile_m_atoms[0]\n add(base_tile_m, base_atom, 1, 1) # 0: baseline\n add(base_tile_m, base_atom, 0, 1) # no dequant prefetch (helps short-K)\n for tile_m, atom in tile_m_atoms[1:]:\n add(tile_m, atom, 1, 1)\n\n # Small-N grids underfill the GPU; offer them split-K variants.\n if n // 64 <= 256:\n k_tiles = k // tile_k\n for splits in (2, 4, 8):\n if splits <= k_tiles:\n add(base_tile_m, base_atom, 1, 1, splits=splits)\n\n # tile_N=128 halves the (m,n)-tile count but needs large wave count.\n if tile_k == 128 and n >= 12288 and n % 128 == 0:\n add(base_tile_m, base_atom, 1, 1, tile_n=128)\n\n # tile_K=64 has more ab stages, but requires larger problem size.\n if tile_k == 128 and n >= 8192:\n add(base_tile_m, base_atom, 1, 1, tile_n=64, tk=64)\n\n # tile_M=128 (taller M tile, atom (2,2,1)) -- the large-M *prefill* lever.\n if tile_k == 128:\n add(128, (2, 2, 1), 1, 1)\n\n # Threadblock swizzle (tile_swizzle=8) -- for large-M prefill.\n if tile_k == 128 and n * k >= 16 * 1024 * 1024:\n add(64, (2, 2, 1), 1, 1, swz=8)\n if tile_k == 128:\n add(128, (2, 2, 1), 1, 1, swz=8)\n\n # tile_N=128 (with tile_M=64, atom (2,2,1)) -- large shapes.\n if tile_k == 128 and n % 128 == 0 and n >= 4096:\n add(64, (2, 2, 1), 1, 1, tile_n=128, swz=8)\n add(64, (2, 2, 1), 1, 1, tile_n=128, swz=1)\n\n # occupancy=2: two co-resident CTAs per SM at half the ab_stage depth\n # (the kernel's occupancy note explains the trade). The 128-tile gate\n # fills two CTAs per SM on ~188-SM parts; 5080-class still qualifies.\n if tile_k == 128 and n // 64 >= 128:\n add(base_tile_m, base_atom, 1, 1, occ=2)\n add(base_tile_m, base_atom, 0, 1, occ=2)\n\n # occupancy=2 x split-K: grids too small to fill two CTAs per SM (the\n # down-proj class) get there by splitting K; the makespan gate decides\n # per device whether the pieces fit.\n if tile_k == 128 and n // 64 <= 256:\n k_tiles = k // tile_k\n for splits in (2, 4, 8):\n if splits <= k_tiles:\n add(base_tile_m, base_atom, 1, 1, splits=splits, occ=2)\n\n # occupancy=3: 9 resident warps per SM; needs the 2-stage epilogue to\n # keep 3 ab stages in SMEM (paired in _get_cute_dsl_bf16_fp4_gemm).\n if tile_k == 128 and n // 64 >= 128:\n add(base_tile_m, base_atom, 1, 1, occ=3)\n\n # Streaming GEMV for m=1 decode (SMEM-free, no tensor cores; see\n # GemvBf16Fp4Sm12x). splits shards K across grid.y for grid fill.\n if n % 64 == 0:\n k_tiles16 = k // 16\n gemv_splits = [s for s in (1, 2, 4, 8, 16, 32) if s * 4 <= k_tiles16]\n if gemv_splits:\n knee = _bf16_fp4_gemv_knee_split(n, k, sm_count)\n if knee not in gemv_splits:\n gemv_splits.append(knee)\n for splits in gemv_splits:\n configs.append(((1, 64, 16), (0, 0, 0), 0, 0, 1, splits, 1, \"gemv\"))\n\n return tuple(configs)\n\n\n_BF16_FP4_CUTE_DSL_TUNING_CONFIG = TuningConfig(\n dynamic_tensor_specs=(\n DynamicTensorSpec(\n (0,), # a_tensor_index\n (0,), # M dimension\n get_hybrid_num_tokens_buckets,\n map_to_hybrid_bucket_uncapped,\n ),\n ),\n constraint_specs=(\n ConstraintSpec(\n 5, # out_tensor_index follows M\n 0,\n lambda shapes: shapes[0][0],\n ),\n ),\n)\n\n\ndef _cute_dsl_bf16_fp4_runner(enable_pdl: bool = True) -> TunableRunner:\n \"\"\"Build a ``CuteDslBf16Fp4Runner`` for the cute-DSL bf16 x fp4 GEMM.\"\"\"\n\n class CuteDslBf16Fp4Runner(TunableRunner):\n def get_cache_key_extras(self, inputs: List[torch.Tensor]) -> tuple:\n a, b, _, _, out_dtype, _, block_size = inputs\n n = int(b.shape[1]) // 2\n k = int(b.shape[0]) * int(block_size)\n # The config list holds device-derived gemv splits, so a tuned\n # index must not replay on a different SM count.\n return (out_dtype, n, k, get_device_sm_count(a.device))\n\n def get_valid_tactics(\n self,\n inputs: List[torch.Tensor],\n profile: OptimizationProfile,\n ) -> List[int]:\n a, b, _, _, _, _, block_size = inputs\n n = int(b.shape[1]) // 2\n k = int(b.shape[0]) * int(block_size)\n m_opt = int(profile.get_opt_shapes()[0][0])\n sm_count = get_device_sm_count(a.device)\n # GEMV is validated only on SM12x; the autotuner ranks by time\n # and would not catch a wrong-but-fast kernel elsewhere.\n gemv_ok = get_compute_capability(a.device)[0] == 12\n configs = _bf16_fp4_cute_dsl_tactic_configs(n, k, sm_count)\n\n def split_reduces_makespan(cfg) -> bool:\n # Offer a split only if it shrinks the last wave >= 25%: the\n # autotuner's warm-cache timing hides the partials cost, so it\n # cannot reject bad splits itself.\n splits = cfg[5]\n if splits == 1:\n return True\n tile_m, tile_n, _ = cfg[0]\n tiles = (-(-m_opt // tile_m)) * (-(-n // tile_n))\n # occupancy multiplies the co-resident CTA slots per SM, so\n # occ2 x split-K fits 2x the pieces in one wave.\n slots = sm_count * cfg[6]\n base_waves = -(-tiles // sm_count)\n split_waves = (-(-tiles * splits // slots)) / splits\n return split_waves <= 0.75 * base_waves\n\n def gemv_valid(cfg) -> bool:\n # The m buckets round up, so only runtime m == 1 lands in\n # the m_opt == 1 bucket.\n if m_opt != 1 or not gemv_ok:\n return False\n warps_per_sm = (n // 64) * cfg[5] / sm_count\n return _GEMV_MIN_WARPS_PER_SM <= warps_per_sm <= _GEMV_MAX_WARPS_PER_SM\n\n return [\n i\n for i, cfg in enumerate(configs)\n if (\n gemv_valid(cfg) if cfg[7] == \"gemv\" else split_reduces_makespan(cfg)\n )\n ]\n\n def forward(\n self,\n inputs: List[torch.Tensor],\n tactic: int = -1,\n do_preparation: bool = False,\n **kwargs,\n ) -> torch.Tensor:\n a, b, b_sf_u8, alpha_for_launch, out_dtype, out, block_size = inputs\n n = int(b.shape[1]) // 2\n k = int(b.shape[0]) * int(block_size)\n m = int(a.shape[0])\n cfg = (\n _bf16_fp4_cute_dsl_tactic_configs(n, k, get_device_sm_count(a.device))[\n tactic\n ]\n if tactic >= 0\n else None\n )\n splits: Optional[int] = None\n if cfg is not None and cfg[7] == \"gemv\":\n if m != 1:\n raise ValueError(f\"the gemv tactic requires m == 1, got m={m}\")\n splits = cfg[5]\n elif cfg is None and m == 1 and not do_preparation:\n # Prep calls run outside the autotuner's per-tactic exception\n # guard; a gemv failure there would abort the whole op.\n splits = _select_bf16_fp4_gemv_split(\n n,\n k,\n get_compute_capability(a.device)[0],\n get_device_sm_count(a.device),\n )\n if splits is not None:\n compiled = _get_cute_dsl_bf16_fp4_gemv(\n splits, a.dtype, out_dtype, enable_pdl=enable_pdl\n )\n if splits > 1:\n partial = _get_cache_buf(\n \"mm_bf16_fp4_split_k_partial\",\n splits * m * n * 4,\n a.device,\n ).view(torch.float32)\n else:\n partial = _get_cache_buf(\n \"mm_bf16_fp4_split_k_partial_dummy\", 16, a.device\n ).view(torch.float32)\n compiled(a, b, b_sf_u8, out, partial, alpha_for_launch)\n return out\n if tactic < 0:\n # Fallback == pre-autotuner heuristic (M-aware), default knobs.\n tile_shape_mnk, atom_layout = _select_bf16_fp4_tile_shape(m, n, k)\n pipeline_depth, use_fp16_mma, tile_swizzle, occupancy = 1, 1, 1, 1\n k_splits = _select_bf16_fp4_k_splits(\n m, n, k, tile_shape_mnk, get_device_sm_count(a.device)\n )\n else:\n (\n tile_shape_mnk,\n atom_layout,\n pipeline_depth,\n use_fp16_mma,\n tile_swizzle,\n k_splits,\n occupancy,\n ) = cfg[:7]\n compiled = _get_cute_dsl_bf16_fp4_gemm(\n tile_shape_mnk,\n a.dtype,\n out_dtype,\n atom_layout,\n pipeline_depth,\n use_fp16_mma,\n enable_pdl=enable_pdl,\n tile_swizzle=tile_swizzle,\n k_splits=k_splits,\n occupancy=occupancy,\n )\n if k_splits > 1:\n if k_splits > k // tile_shape_mnk[2]:\n raise ValueError(\n f\"k_splits={k_splits} exceeds the K-tile count for \"\n f\"k={k}, tile_k={tile_shape_mnk[2]}\"\n )\n # The compiled call launches the reduce kernel as well, so\n # ``out`` is final on return.\n partial = _get_cache_buf(\n \"mm_bf16_fp4_split_k_partial\",\n k_splits * m * n * 4,\n a.device,\n ).view(torch.float32)\n else:\n partial = _get_cache_buf(\n \"mm_bf16_fp4_split_k_partial_dummy\", 16, a.device\n ).view(torch.float32)\n compiled(a, b, b_sf_u8, out, partial, alpha_for_launch)\n return out\n\n return CuteDslBf16Fp4Runner()\n\n\ndef _compute_cute_dsl(\n a: torch.Tensor,\n b: torch.Tensor,\n b_descale: torch.Tensor,\n alpha: Optional[torch.Tensor],\n out_dtype: torch.dtype,\n out: Optional[torch.Tensor],\n block_size: int,\n enable_pdl: bool = True,\n) -> torch.Tensor:\n \"\"\"cute-DSL-backend compute: dispatch to the compiled Blackwell kernel.\n\n ``b`` is the packed ``(K // 16, N * 2)`` int32 weight and\n ``b_descale`` the ``(K // block_size, N)`` uint8 SF in S0E5M3 format\n (reformatted from FP8-E4M3 by :func:`_e4m3_to_s0e5m3`) returned by\n :func:`_prepare_cute_dsl`.\n \"\"\"\n if b.dtype != torch.int32:\n raise TypeError(\n f\"cute-dsl backend expects the packed int32 weight from \"\n f\"prepare_bf16_fp4_weights(..., backend='cute-dsl'); got {b.dtype}.\"\n )\n if out_dtype != a.dtype:\n raise NotImplementedError(\n f\"cute-dsl backend requires out_dtype == a.dtype (got \"\n f\"out_dtype={out_dtype}, a.dtype={a.dtype}). Use the cudnn \"\n f\"backend for a mismatched output dtype.\"\n )\n k_tiles = int(b.shape[0])\n n = int(b.shape[1]) // 2\n k = k_tiles * block_size\n m = int(a.shape[0])\n if a.shape[1] != k:\n raise ValueError(\n f\"a.shape[1]={a.shape[1]} but k inferred from prepared b.shape=\"\n f\"{tuple(b.shape)} is {k}\"\n )\n\n if out is None:\n out = torch.empty((m, n), device=a.device, dtype=out_dtype)\n else:\n if tuple(out.shape) != (m, n):\n raise ValueError(f\"out shape {tuple(out.shape)} != expected {(m, n)}\")\n if out.dtype != out_dtype:\n raise TypeError(f\"out dtype {out.dtype} != requested out_dtype {out_dtype}\")\n\n b_sf_u8 = b_descale.view(torch.uint8).contiguous()\n alpha_for_launch = _prepare_bf16_fp4_alpha(alpha, a.device)\n\n tuner = AutoTuner.get()\n runner = _cute_dsl_bf16_fp4_runner(enable_pdl=enable_pdl)\n inputs = [a, b, b_sf_u8, alpha_for_launch, out_dtype, out, block_size]\n chosen_runner, tactic = tuner.choose_one(\n \"bf16_fp4_cute_dsl_gemm\",\n [runner],\n _BF16_FP4_CUTE_DSL_TUNING_CONFIG,\n inputs,\n )\n chosen_runner(inputs=inputs, tactic=tactic)\n return out\n"},"diff":{"kind":"string","value":"--- flashinfer/gemm/gemm_bf16_fp4_cute_dsl.py\n+++ flashinfer/gemm/gemm_bf16_fp4_cute_dsl.py\n@@ -2,6 +2,7 @@\n # SPDX-License-Identifier: Apache-2.0\n \"\"\"CuTe-DSL backend for the bf16 x fp4 GEMM (weight repack / kernel launch).\"\"\"\n \n+import functools\n from typing import List, Optional, Tuple, cast\n \n import torch\n@@ -18,6 +19,7 @@\n get_hybrid_num_tokens_buckets,\n map_to_hybrid_bucket_uncapped,\n )\n+from ..utils import _get_cache_buf, get_compute_capability, get_device_sm_count\n from .gemm_base import _check_cute_dsl_availability\n from .gemm_bf16_fp4 import _unswizzle_sf_128x4\n \n@@ -77,6 +79,55 @@\n return ((64, 64, tile_k), (2, 2, 1))\n \n \n+def _select_bf16_fp4_k_splits(\n+ m: int, n: int, k: int, tile_shape_mnk: Tuple[int, int, int], sm_count: int\n+) -> int:\n+ \"\"\"Static split-K pick for the no-autotune fallback: only clear-win\n+ underfill grids get a split, closer calls are left to the autotuner.\"\"\"\n+ tile_m, tile_n, tile_k = tile_shape_mnk\n+ if tile_m != (16 if tile_k == 128 else 32):\n+ # Split only the tile shapes that the tactic space pairs with splits.\n+ return 1\n+ tiles = -(-m // tile_m) * -(-n // tile_n)\n+ if tiles * 3 > sm_count:\n+ return 1\n+ k_tiles = k // tile_k\n+ for splits in (8, 4, 2):\n+ if splits <= k_tiles and tiles * splits <= sm_count:\n+ return splits\n+ return 1\n+\n+\n+# Stream-GEMV residency window (warps/SM): below the floor DRAM latency is\n+# uncovered, far above the ceiling splits just multiply partial traffic.\n+_GEMV_MIN_WARPS_PER_SM = 12\n+_GEMV_MAX_WARPS_PER_SM = 96\n+\n+\n+def _bf16_fp4_gemv_knee_split(n: int, k: int, sm_count: int) -> int:\n+ \"\"\"Smallest K-split reaching ~20 warps/SM, where throughput saturates\n+ and deeper splits only add partial traffic; capped under one full wave\n+ (6 CTAs/SM = 1536-thread limit / 256) and at >= 4 K-tiles per split.\"\"\"\n+ ctas = -(-(n // 64) // 8)\n+ cap = max(1, min(int(0.95 * sm_count * 6 / ctas), (k // 16) // 4))\n+ return min(-(-20 * sm_count // (n // 64)), cap)\n+\n+\n+def _select_bf16_fp4_gemv_split(\n+ n: int, k: int, cc_major: int, sm_count: int\n+) -> Optional[int]:\n+ \"\"\"m=1 no-autotune fallback pick: the stream GEMV where it applies,\n+ ``None`` for the MMA heuristic. Serving stacks do not tune every\n+ shape (vLLM never tunes the logits GEMM), so untuned m=1 matters.\"\"\"\n+ if cc_major != 12 or n % 64 != 0 or k // 16 < 4:\n+ return None\n+ split = _bf16_fp4_gemv_knee_split(n, k, sm_count)\n+ warps_per_sm = (n // 64) * split / sm_count\n+ if not _GEMV_MIN_WARPS_PER_SM <= warps_per_sm <= _GEMV_MAX_WARPS_PER_SM:\n+ return None\n+ return split\n+\n+\n _CUTE_DSL_MM_BF16_FP4_KERNEL_CACHE: dict = {}\n \n \n@@ -89,6 +140,8 @@\n use_fp16_mma: int = 1,\n enable_pdl: bool = True,\n tile_swizzle: int = 1,\n+ k_splits: int = 1,\n+ occupancy: int = 1,\n ):\n # Normalize to a tuple (callers may pass a list) so the cache key is hashable.\n atom_layout = cast(Tuple[int, int, int], tuple(atom_layout))\n@@ -96,6 +149,8 @@\n use_fp16_mma = int(use_fp16_mma)\n enable_pdl = bool(enable_pdl)\n tile_swizzle = int(tile_swizzle)\n+ k_splits = int(k_splits)\n+ occupancy = int(occupancy)\n cache_key = (\n tile_shape_mnk,\n a_dtype,\n@@ -105,6 +160,8 @@\n use_fp16_mma,\n enable_pdl,\n tile_swizzle,\n+ k_splits,\n+ occupancy,\n )\n cached = _CUTE_DSL_MM_BF16_FP4_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n@@ -146,6 +203,10 @@\n c_fake = cute.runtime.make_fake_compact_tensor(\n c_cutlass_dtype, (sym_m, sym_n), stride_order=(1, 0), assumed_align=16\n )\n+ sym_partial = cute.sym_int()\n+ partial_fake = cute.runtime.make_fake_compact_tensor(\n+ cutlass.Float32, (sym_partial,), assumed_align=16\n+ )\n alpha_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32, (1,), assumed_align=4\n )\n@@ -155,12 +216,19 @@\n acc_dtype=cutlass.Float32,\n tile_shape_mnk=tile_shape_mnk,\n atom_layout=atom_layout,\n+ # At occupancy 3 the SMEM budget per CTA only fits 2 ab stages next\n+ # to the default 4-stage epilogue; a 2-stage epilogue keeps 3.\n+ epi_stage=2 if occupancy >= 3 else 4,\n pipeline_depth=pipeline_depth,\n use_fp16_mma=use_fp16_mma,\n enable_pdl=enable_pdl,\n tile_swizzle=tile_swizzle,\n- )\n- max_active_clusters = get_max_active_clusters(1)\n+ k_splits=k_splits,\n+ occupancy=occupancy,\n+ )\n+ # The persistent grid launches occupancy CTAs per SM; the kernel's stage\n+ # budget (_compute_stages) shrinks SMEM per CTA so they co-reside.\n+ max_active_clusters = get_max_active_clusters(1) * occupancy\n \n compiled = cute.compile(\n gemm.wrapper,\n@@ -168,9 +236,77 @@\n b_packed_fake,\n b_sf_fake,\n c_fake,\n+ partial_fake,\n alpha_fake,\n 1, # l (batch)\n max_active_clusters,\n+ stream_fake,\n+ options=\"--opt-level 2 --enable-tvm-ffi\",\n+ )\n+\n+ _CUTE_DSL_MM_BF16_FP4_KERNEL_CACHE[cache_key] = compiled\n+ return compiled\n+\n+\n+def _get_cute_dsl_bf16_fp4_gemv(\n+ splits: int,\n+ a_dtype: torch.dtype,\n+ c_dtype: torch.dtype,\n+ enable_pdl: bool = True,\n+):\n+ \"\"\"Compile-cache the m=1 streaming GEMV (same call signature as the\n+ compiled MMA kernel, so the runner dispatches either transparently).\"\"\"\n+ splits = int(splits)\n+ enable_pdl = bool(enable_pdl)\n+ cache_key = (\"gemv\", splits, a_dtype, c_dtype, enable_pdl)\n+ cached = _CUTE_DSL_MM_BF16_FP4_KERNEL_CACHE.get(cache_key)\n+ if cached is not None:\n+ return cached\n+\n+ _check_cute_dsl_availability()\n+\n+ import cutlass\n+ import cutlass.cute as cute\n+\n+ from .kernels.cute_dsl.gemv_bf16_fp4_sm12x import GemvBf16Fp4Sm12x\n+\n+ from ..cute_dsl.utils import torch_to_cutlass_dtype\n+\n+ sym = [cute.sym_int() for _ in range(6)]\n+ a_fake = cute.runtime.make_fake_compact_tensor(\n+ torch_to_cutlass_dtype(a_dtype),\n+ (sym[0], sym[1]),\n+ stride_order=(1, 0),\n+ assumed_align=16,\n+ )\n+ b_fake = cute.runtime.make_fake_compact_tensor(\n+ cutlass.Int32, (sym[2], sym[3]), stride_order=(1, 0), assumed_align=16\n+ )\n+ sf_fake = cute.runtime.make_fake_compact_tensor(\n+ cutlass.Uint8, (sym[2], sym[4]), stride_order=(1, 0), assumed_align=16\n+ )\n+ c_fake = cute.runtime.make_fake_compact_tensor(\n+ torch_to_cutlass_dtype(c_dtype),\n+ (sym[0], sym[4]),\n+ stride_order=(1, 0),\n+ assumed_align=16,\n+ )\n+ partial_fake = cute.runtime.make_fake_compact_tensor(\n+ cutlass.Float32, (sym[5],), assumed_align=16\n+ )\n+ alpha_fake = cute.runtime.make_fake_compact_tensor(\n+ cutlass.Float32, (1,), assumed_align=4\n+ )\n+ stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n+\n+ compiled = cute.compile(\n+ GemvBf16Fp4Sm12x(splits=splits, enable_pdl=enable_pdl),\n+ a_fake,\n+ b_fake,\n+ sf_fake,\n+ c_fake,\n+ partial_fake,\n+ alpha_fake,\n stream_fake,\n options=\"--opt-level 2 --enable-tvm-ffi\",\n )\n@@ -282,13 +418,22 @@\n return b_packed, sf_ksf_n, alpha\n \n \n+@functools.cache\n def _bf16_fp4_cute_dsl_tactic_configs(\n- n: int, k: int\n-) -> List[Tuple[Tuple[int, int, int], Tuple[int, int, int], int, int, int]]:\n+ n: int, k: int, sm_count: int\n+) -> Tuple[\n+ Tuple[Tuple[int, int, int], Tuple[int, int, int], int, int, int, int, int, str],\n+ ...,\n+]:\n \"\"\"Enumerate cute-DSL tactic configs for a given ``(N, K)``.\n \n- Returns a list of ``(tile_shape_mnk, atom_layout, pipeline_depth,\n- use_fp16_mma)`` tuples.\n+ Returns a tuple of ``(tile_shape_mnk, atom_layout, pipeline_depth,\n+ use_fp16_mma, tile_swizzle, k_splits, occupancy, kind)`` entries,\n+ where ``kind`` selects the kernel: ``\"mma\"`` (the dense GEMM, all\n+ fields live) or ``\"gemv\"`` (the m=1 streaming kernel, which only\n+ reads ``k_splits``). The gemv entries include device-derived splits,\n+ so a tactic index is only meaningful for the ``(n, k, sm_count)`` it\n+ was enumerated with.\n \"\"\"\n tile_k = 128 if k % 128 == 0 else 64\n \n@@ -300,18 +445,23 @@\n tile_m_atoms.append((32, (2, 2, 1)))\n tile_m_atoms.append((64, (2, 2, 1)))\n \n- configs: List[Tuple[Tuple[int, int, int], Tuple[int, int, int], int, int, int]] = []\n+ configs: List[\n+ Tuple[Tuple[int, int, int], Tuple[int, int, int], int, int, int, int, int, str]\n+ ] = []\n seen = set()\n \n- def add(tile_m, atom, pdepth, fp16, tile_n=64, tk=None, swz=1):\n+ def add(tile_m, atom, pdepth, fp16, tile_n=64, tk=None, swz=1, splits=1, occ=1):\n cfg = (\n (tile_m, tile_n, tile_k if tk is None else tk),\n atom,\n pdepth,\n fp16,\n swz,\n+ splits,\n+ occ,\n+ \"mma\",\n )\n- key = (cfg[0], cfg[1], pdepth, fp16, swz)\n+ key = (cfg[0], cfg[1], pdepth, fp16, swz, splits, occ)\n if key not in seen:\n seen.add(key)\n configs.append(cfg)\n@@ -322,6 +472,13 @@\n for tile_m, atom in tile_m_atoms[1:]:\n add(tile_m, atom, 1, 1)\n \n+ # Small-N grids underfill the GPU; offer them split-K variants.\n+ if n // 64 <= 256:\n+ k_tiles = k // tile_k\n+ for splits in (2, 4, 8):\n+ if splits <= k_tiles:\n+ add(base_tile_m, base_atom, 1, 1, splits=splits)\n+\n # tile_N=128 halves the (m,n)-tile count but needs large wave count.\n if tile_k == 128 and n >= 12288 and n % 128 == 0:\n add(base_tile_m, base_atom, 1, 1, tile_n=128)\n@@ -345,7 +502,40 @@\n add(64, (2, 2, 1), 1, 1, tile_n=128, swz=8)\n add(64, (2, 2, 1), 1, 1, tile_n=128, swz=1)\n \n- return configs\n+ # occupancy=2: two co-resident CTAs per SM at half the ab_stage depth\n+ # (the kernel's occupancy note explains the trade). The 128-tile gate\n+ # fills two CTAs per SM on ~188-SM parts; 5080-class still qualifies.\n+ if tile_k == 128 and n // 64 >= 128:\n+ add(base_tile_m, base_atom, 1, 1, occ=2)\n+ add(base_tile_m, base_atom, 0, 1, occ=2)\n+\n+ # occupancy=2 x split-K: grids too small to fill two CTAs per SM (the\n+ # down-proj class) get there by splitting K; the makespan gate decides\n+ # per device whether the pieces fit.\n+ if tile_k == 128 and n // 64 <= 256:\n+ k_tiles = k // tile_k\n+ for splits in (2, 4, 8):\n+ if splits <= k_tiles:\n+ add(base_tile_m, base_atom, 1, 1, splits=splits, occ=2)\n+\n+ # occupancy=3: 9 resident warps per SM; needs the 2-stage epilogue to\n+ # keep 3 ab stages in SMEM (paired in _get_cute_dsl_bf16_fp4_gemm).\n+ if tile_k == 128 and n // 64 >= 128:\n+ add(base_tile_m, base_atom, 1, 1, occ=3)\n+\n+ # Streaming GEMV for m=1 decode (SMEM-free, no tensor cores; see\n+ # GemvBf16Fp4Sm12x). splits shards K across grid.y for grid fill.\n+ if n % 64 == 0:\n+ k_tiles16 = k // 16\n+ gemv_splits = [s for s in (1, 2, 4, 8, 16, 32) if s * 4 <= k_tiles16]\n+ if gemv_splits:\n+ knee = _bf16_fp4_gemv_knee_split(n, k, sm_count)\n+ if knee not in gemv_splits:\n+ gemv_splits.append(knee)\n+ for splits in gemv_splits:\n+ configs.append(((1, 64, 16), (0, 0, 0), 0, 0, 1, splits, 1, \"gemv\"))\n+\n+ return tuple(configs)\n \n \n _BF16_FP4_CUTE_DSL_TUNING_CONFIG = TuningConfig(\n@@ -375,17 +565,56 @@\n a, b, _, _, out_dtype, _, block_size = inputs\n n = int(b.shape[1]) // 2\n k = int(b.shape[0]) * int(block_size)\n- return (out_dtype, n, k)\n+ # The config list holds device-derived gemv splits, so a tuned\n+ # index must not replay on a different SM count.\n+ return (out_dtype, n, k, get_device_sm_count(a.device))\n \n def get_valid_tactics(\n self,\n inputs: List[torch.Tensor],\n profile: OptimizationProfile,\n ) -> List[int]:\n- _, b, _, _, _, _, block_size = inputs\n+ a, b, _, _, _, _, block_size = inputs\n n = int(b.shape[1]) // 2\n k = int(b.shape[0]) * int(block_size)\n- return list(range(len(_bf16_fp4_cute_dsl_tactic_configs(n, k))))\n+ m_opt = int(profile.get_opt_shapes()[0][0])\n+ sm_count = get_device_sm_count(a.device)\n+ # GEMV is validated only on SM12x; the autotuner ranks by time\n+ # and would not catch a wrong-but-fast kernel elsewhere.\n+ gemv_ok = get_compute_capability(a.device)[0] == 12\n+ configs = _bf16_fp4_cute_dsl_tactic_configs(n, k, sm_count)\n+\n+ def split_reduces_makespan(cfg) -> bool:\n+ # Offer a split only if it shrinks the last wave >= 25%: the\n+ # autotuner's warm-cache timing hides the partials cost, so it\n+ # cannot reject bad splits itself.\n+ splits = cfg[5]\n+ if splits == 1:\n+ return True\n+ tile_m, tile_n, _ = cfg[0]\n+ tiles = (-(-m_opt // tile_m)) * (-(-n // tile_n))\n+ # occupancy multiplies the co-resident CTA slots per SM, so\n+ # occ2 x split-K fits 2x the pieces in one wave.\n+ slots = sm_count * cfg[6]\n+ base_waves = -(-tiles // sm_count)\n+ split_waves = (-(-tiles * splits // slots)) / splits\n+ return split_waves <= 0.75 * base_waves\n+\n+ def gemv_valid(cfg) -> bool:\n+ # The m buckets round up, so only runtime m == 1 lands in\n+ # the m_opt == 1 bucket.\n+ if m_opt != 1 or not gemv_ok:\n+ return False\n+ warps_per_sm = (n // 64) * cfg[5] / sm_count\n+ return _GEMV_MIN_WARPS_PER_SM <= warps_per_sm <= _GEMV_MAX_WARPS_PER_SM\n+\n+ return [\n+ i\n+ for i, cfg in enumerate(configs)\n+ if (\n+ gemv_valid(cfg) if cfg[7] == \"gemv\" else split_reduces_makespan(cfg)\n+ )\n+ ]\n \n def forward(\n self,\n@@ -398,10 +627,50 @@\n n = int(b.shape[1]) // 2\n k = int(b.shape[0]) * int(block_size)\n m = int(a.shape[0])\n+ cfg = (\n+ _bf16_fp4_cute_dsl_tactic_configs(n, k, get_device_sm_count(a.device))[\n+ tactic\n+ ]\n+ if tactic >= 0\n+ else None\n+ )\n+ splits: Optional[int] = None\n+ if cfg is not None and cfg[7] == \"gemv\":\n+ if m != 1:\n+ raise ValueError(f\"the gemv tactic requires m == 1, got m={m}\")\n+ splits = cfg[5]\n+ elif cfg is None and m == 1 and not do_preparation:\n+ # Prep calls run outside the autotuner's per-tactic exception\n+ # guard; a gemv failure there would abort the whole op.\n+ splits = _select_bf16_fp4_gemv_split(\n+ n,\n+ k,\n+ get_compute_capability(a.device)[0],\n+ get_device_sm_count(a.device),\n+ )\n+ if splits is not None:\n+ compiled = _get_cute_dsl_bf16_fp4_gemv(\n+ splits, a.dtype, out_dtype, enable_pdl=enable_pdl\n+ )\n+ if splits > 1:\n+ partial = _get_cache_buf(\n+ \"mm_bf16_fp4_split_k_partial\",\n+ splits * m * n * 4,\n+ a.device,\n+ ).view(torch.float32)\n+ else:\n+ partial = _get_cache_buf(\n+ \"mm_bf16_fp4_split_k_partial_dummy\", 16, a.device\n+ ).view(torch.float32)\n+ compiled(a, b, b_sf_u8, out, partial, alpha_for_launch)\n+ return out\n if tactic < 0:\n # Fallback == pre-autotuner heuristic (M-aware), default knobs.\n tile_shape_mnk, atom_layout = _select_bf16_fp4_tile_shape(m, n, k)\n- pipeline_depth, use_fp16_mma, tile_swizzle = 1, 1, 1\n+ pipeline_depth, use_fp16_mma, tile_swizzle, occupancy = 1, 1, 1, 1\n+ k_splits = _select_bf16_fp4_k_splits(\n+ m, n, k, tile_shape_mnk, get_device_sm_count(a.device)\n+ )\n else:\n (\n tile_shape_mnk,\n@@ -409,7 +678,9 @@\n pipeline_depth,\n use_fp16_mma,\n tile_swizzle,\n- ) = _bf16_fp4_cute_dsl_tactic_configs(n, k)[tactic]\n+ k_splits,\n+ occupancy,\n+ ) = cfg[:7]\n compiled = _get_cute_dsl_bf16_fp4_gemm(\n tile_shape_mnk,\n a.dtype,\n@@ -419,8 +690,27 @@\n use_fp16_mma,\n enable_pdl=enable_pdl,\n tile_swizzle=tile_swizzle,\n+ k_splits=k_splits,\n+ occupancy=occupancy,\n )\n- compiled(a, b, b_sf_u8, out, alpha_for_launch)\n+ if k_splits > 1:\n+ if k_splits > k // tile_shape_mnk[2]:\n+ raise ValueError(\n+ f\"k_splits={k_splits} exceeds the K-tile count for \"\n+ f\"k={k}, tile_k={tile_shape_mnk[2]}\"\n+ )\n+ # The compiled call launches the reduce kernel as well, so\n+ # ``out`` is final on return.\n+ partial = _get_cache_buf(\n+ \"mm_bf16_fp4_split_k_partial\",\n+ k_splits * m * n * 4,\n+ a.device,\n+ ).view(torch.float32)\n+ else:\n+ partial = _get_cache_buf(\n+ \"mm_bf16_fp4_split_k_partial_dummy\", 16, a.device\n+ ).view(torch.float32)\n+ compiled(a, b, b_sf_u8, out, partial, alpha_for_launch)\n return out\n \n return CuteDslBf16Fp4Runner()"},"lines_added":{"kind":"number","value":306,"string":"306"},"lines_removed":{"kind":"number","value":16,"string":"16"},"files_in_commit":{"kind":"number","value":2,"string":"2"},"models_mentioned":{"kind":"list like","value":["qwen","llama"],"string":"[\n \"qwen\",\n \"llama\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["RTX5080"],"string":"[\n \"RTX5080\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":["1.011x","1.11x","1.014x"],"string":"[\n \"1.011x\",\n \"1.11x\",\n \"1.014x\"\n]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cute_dsl kernel file from flashinfer (flashinfer/gemm/gemm_bf16_fp4_cute_dsl.py).\n\nGoal: perf(gemm): split-K, occupancy, and m=1 stream-GEMV decode tactics for mm_bf16_fp4\nTarget hardware: RTX5080\nTarget models: qwen, llama\n\nCurrent file:\n```python\n# SPDX-FileCopyrightText: Copyright (c) 2025 by FlashInfer team.\n# SPDX-License-Identifier: Apache-2.0\n\"\"\"CuTe-DSL backend for the bf16 x fp4 GEMM (weight repack / kernel launch).\"\"\"\n\nfrom typing import List, Optional, Tuple, cast\n\nimport torch\n\nfrom ..autotuner import (\n AutoTuner,\n ConstraintSpec,\n DynamicTensorSpec,\n OptimizationProfile,\n TunableRunner,\n TuningConfig,\n)\nfrom ..fused_moe.utils import (\n get_hybrid_num_tokens_buckets,\n map_to_hybrid_bucket_uncapped,\n)\nfrom .gemm_base import _check_cute_dsl_availability\nfrom .gemm_bf16_fp4 import _unswizzle_sf_128x4\n\n_BF16_FP4_ALPHA_ONE_CACHE: dict = {}\n\n\ndef _prepare_bf16_fp4_alpha(\n alpha: Optional[torch.Tensor], device: torch.device\n) -> torch.Tensor:\n \"\"\"Normalize ``alpha`` to a ``(1,) float32`` tensor for the kernel.\"\"\"\n if alpha is None:\n cached = _BF16_FP4_ALPHA_ONE_CACHE.get(device)\n if cached is None:\n cached = torch.tensor([1.0], dtype=torch.float32, device=device)\n _BF16_FP4_ALPHA_ONE_CACHE[device] = cached\n return cached\n if alpha.dim() == 0:\n return alpha.to(device=device, dtype=torch.float32).unsqueeze(0)\n return alpha.to(device=device, dtype=torch.float32).reshape(1)\n\n\ndef _select_bf16_fp4_tile_shape(\n m: int, n: int, k: int\n) -> Tuple[Tuple[int, int, int], Tuple[int, int, int]]:\n \"\"\"Pick a CTA tile shape AND MMA atom_layout for the cute-DSL bf16 x fp4 kernel.\n\n Returns ``(tile_shape_mnk, atom_layout)``.\n\n Tile shape selection:\n tile_M choice\n * M <= 16 (and tile_K=128 path): use tile_M=16 with atom_layout\n (1,2,1). Halves wasted M-rows vs tile_M=32, and a 1-M-warp\n layout removes the duplicate dequant that (2,2,1) suffers from.\n * 16 < M <= 32: use tile_M=32 with atom_layout (2,2,1). Smaller\n MMA + epilogue waste than tile_M=64.\n * M > 32: use tile_M=64 with atom_layout (2,2,1) -- standard tile,\n more rows to amortize across.\n\n tile_K choice\n * K % 128 == 0: tile_K=128 (halves K-tile count and barrier\n overhead).\n * Otherwise: tile_K=64.\n\n Why atom_layout differs:\n * (2,2,1) (default for tile_M >= 32): 4 MMA warps as 2 M x 2 N --\n well-tested cute layout, but the 2 M-warps redundantly dequant\n the same B values into their own register files (~50% waste in\n dequant compute).\n * (1,2,1) (used for tile_M=16): 2 MMA warps as 1 M x 2 N -- no\n M-warp duplication. Permutation_m = 16, so tile_M must be 16.\n \"\"\"\n tile_k = 128 if k % 128 == 0 else 64\n if m <= 16 and tile_k == 128:\n return ((16, 64, 128), (1, 2, 1))\n if m <= 32:\n return ((32, 64, tile_k), (2, 2, 1))\n return ((64, 64, tile_k), (2, 2, 1))\n\n\n_CUTE_DSL_MM_BF16_FP4_KERNEL_CACHE: dict = {}\n\n\ndef _get_cute_dsl_bf16_fp4_gemm(\n tile_shape_mnk: Tuple[int, int, int],\n a_dtype: torch.dtype,\n c_dtype: torch.dtype,\n atom_layout: Tuple[int, int, int] = (2, 2, 1),\n pipeline_depth: int = 1,\n use_fp16_mma: int = 1,\n enable_pdl: bool = True,\n tile_swizzle: int = 1,\n):\n # Normalize to a tuple (callers may pass a list) so the cache key is hashable.\n atom_layout = cast(Tuple[int, int, int], tuple(atom_layout))\n pipeline_depth = int(pipeline_depth)\n use_fp16_mma = int(use_fp16_mma)\n enable_pdl = bool(enable_pdl)\n tile_swizzle = int(tile_swizzle)\n cache_key = (\n tile_shape_mnk,\n a_dtype,\n c_dtype,\n atom_layout,\n pipeline_depth,\n use_fp16_mma,\n enable_pdl,\n tile_swizzle,\n )\n cached = _CUTE_DSL_MM_BF16_FP4_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n return cached\n\n _check_cute_dsl_availability()\n\n import cutlass\n import cutlass.cute as cute\n from flashinfer.cute_dsl.utils import get_max_active_clusters\n\n from .kernels.cute_dsl.dense_gemm_bf16_fp4_blackwell import (\n BlackwellDenseGemmBf16Fp4Kernel,\n )\n\n from ..cute_dsl.utils import torch_to_cutlass_dtype\n\n a_cutlass_dtype = torch_to_cutlass_dtype(a_dtype)\n c_cutlass_dtype = torch_to_cutlass_dtype(c_dtype)\n\n sym_m = cute.sym_int()\n sym_k = cute.sym_int()\n sym_n = cute.sym_int()\n sym_k_tiles = cute.sym_int()\n sym_n_packed = cute.sym_int()\n\n a_fake = cute.runtime.make_fake_compact_tensor(\n a_cutlass_dtype, (sym_m, sym_k), stride_order=(1, 0), assumed_align=16\n )\n b_packed_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (sym_k_tiles, sym_n_packed),\n stride_order=(1, 0),\n assumed_align=16,\n )\n b_sf_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_k_tiles, sym_n), stride_order=(1, 0), assumed_align=16\n )\n c_fake = cute.runtime.make_fake_compact_tensor(\n c_cutlass_dtype, (sym_m, sym_n), stride_order=(1, 0), assumed_align=16\n )\n alpha_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32, (1,), assumed_align=4\n )\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n\n gemm = BlackwellDenseGemmBf16Fp4Kernel(\n acc_dtype=cutlass.Float32,\n tile_shape_mnk=tile_shape_mnk,\n atom_layout=atom_layout,\n pipeline_depth=pipeline_depth,\n use_fp16_mma=use_fp16_mma,\n enable_pdl=enable_pdl,\n tile_swizzle=tile_swizzle,\n )\n max_active_clusters = get_max_active_clusters(1)\n\n compiled = cute.compile(\n gemm.wrapper,\n a_fake,\n b_packed_fake,\n b_sf_fake,\n c_fake,\n alpha_fake,\n 1, # l (batch)\n max_active_clusters,\n stream_fake,\n options=\"--opt-level 2 --enable-tvm-ffi\",\n )\n\n _CUTE_DSL_MM_BF16_FP4_KERNEL_CACHE[cache_key] = compiled\n return compiled\n\n\ndef _e4m3_to_s0e5m3(sf_u8: torch.Tensor) -> torch.Tensor:\n \"\"\"Reformat a uint8 tensor of E4M3 scale bytes to S0E5M3 bytes.\n Used in cute-dsl backend for faster in-kernel scale decode.\n \"\"\"\n f16 = sf_u8.contiguous().view(torch.float8_e4m3fn).to(torch.float16)\n bits = f16.view(torch.int16).to(torch.int32) & 0xFFFF\n return ((bits >> 7) & 0xFF).to(torch.uint8)\n\n\n_CUTE_DSL_PACK_TILE_K: int = 16 # K-tile size = MMA K-block size\n_CUTE_DSL_PACK_TILE_N: int = 64 # N-tile size = kernel tile_N\n_CUTE_DSL_PACK_INTS_PER_TILE: int = 128 # int32s per (16K x 64N) repack block\n\n\ndef _cute_dsl_pack_fp4_weight(b: torch.Tensor) -> torch.Tensor:\n \"\"\"Repack a packed FP4 weight for the bf16 x fp4 cute-DSL kernel.\"\"\"\n if b.dtype != torch.uint8:\n b = b.view(torch.uint8)\n\n k_half, n = b.shape\n k = k_half * 2\n if k % _CUTE_DSL_PACK_TILE_K != 0:\n raise ValueError(f\"K must be a multiple of {_CUTE_DSL_PACK_TILE_K} (got K={k})\")\n if n % _CUTE_DSL_PACK_TILE_N != 0:\n raise ValueError(f\"N must be a multiple of {_CUTE_DSL_PACK_TILE_N} (got N={n})\")\n\n device = b.device\n k_tiles = k // _CUTE_DSL_PACK_TILE_K\n n_tiles = n // _CUTE_DSL_PACK_TILE_N\n k_half_per_tile = _CUTE_DSL_PACK_TILE_K // 2 # 8 packed K-rows per tile\n\n u32_pos = torch.arange(\n _CUTE_DSL_PACK_INTS_PER_TILE, device=device, dtype=torch.long\n )\n u32_idx_local = u32_pos % 2\n lane = (u32_pos // 2) % 32\n n_warp_idx = u32_pos // 64\n\n tc_col = lane // 4 # in [0, 8)\n tc_row_half = lane % 4 # tc_row = tc_row_half * 2 in {0, 2, 4, 6}\n base_n = n_warp_idx * 8 + tc_col # in [0, 16)\n\n byte_k_half_offset = torch.tensor([0, 4, 0, 4], device=device, dtype=torch.long)\n n_offset_stack = torch.tensor(\n [[0, 0, 16, 16], [32, 32, 48, 48]], device=device, dtype=torch.long\n )\n byte_n_offset = n_offset_stack[u32_idx_local] # (128, 4)\n\n # Source byte within the (8, 64) tile for each (u32_pos, byte_idx).\n k_half_in_tile = tc_row_half[:, None] + byte_k_half_offset[None, :] # (128, 4)\n n_in_tile = base_n[:, None] + byte_n_offset # (128, 4)\n within_idx = (k_half_in_tile * _CUTE_DSL_PACK_TILE_N + n_in_tile).reshape(\n -1\n ) # (512,) flat index into a row-major (8, 64) tile\n\n # (K/2, N) -> (K_tiles, 8, N_tiles, 64) -> (K_tiles, N_tiles, 8*64) so the\n # 512 source bytes of each tile are contiguous, then gather them in\n # (u32_pos, byte_idx) order.\n tile_bytes = (\n b.reshape(k_tiles, k_half_per_tile, n_tiles, _CUTE_DSL_PACK_TILE_N)\n .permute(0, 2, 1, 3)\n .reshape(k_tiles, n_tiles, k_half_per_tile * _CUTE_DSL_PACK_TILE_N)\n )\n gathered = tile_bytes[:, :, within_idx].reshape(\n k_tiles, n_tiles, _CUTE_DSL_PACK_INTS_PER_TILE, 4\n )\n\n # Each 4 consecutive bytes are one little-endian int32 (byte 0 = bits 0-7),\n # exactly what the kernel's 32-bit loads read -- reinterpret in place.\n return gathered.view(torch.int32).reshape(\n k_tiles, n_tiles * _CUTE_DSL_PACK_INTS_PER_TILE\n )\n\n\ndef _prepare_cute_dsl(\n b: torch.Tensor,\n b_descale: torch.Tensor,\n alpha: Optional[torch.Tensor],\n block_size: int,\n) -> Tuple[torch.Tensor, torch.Tensor, Optional[torch.Tensor]]:\n \"\"\"cute-DSL-backend prep: repack the weight + unswizzle the SF.\n\n Produces the bespoke layout the cute-DSL kernel consumes:\n * weight: ``(K // 16, N * 2)`` int32 (see :func:`_cute_dsl_pack_fp4_weight`).\n * SF: ``(K // block_size, N)`` uint8 -- per-block scales reformatted to\n S0E5M3, the format the cute-DSL kernel decodes.\n ``alpha`` is passed through unchanged (the compute step normalizes it\n to a ``(1,) float32`` scalar). Pair the returned tensors with\n ``mm_bf16_fp4(a, b, b_descale, alpha, backend='cute-dsl')``.\n \"\"\"\n n = int(b.shape[0])\n k = int(b.shape[1]) * 2\n k_sf = k // block_size\n\n b_kn = b.t().contiguous()\n b_packed = _cute_dsl_pack_fp4_weight(b_kn) # (K//16, N*2) int32\n\n linear_sf = _unswizzle_sf_128x4(b_descale, n, k_sf) # (N, K_sf) uint8\n sf_ksf_n = linear_sf.t().contiguous() # (K_sf, N) uint8 (E4M3)\n sf_ksf_n = _e4m3_to_s0e5m3(sf_ksf_n) # -> S0E5M3\n return b_packed, sf_ksf_n, alpha\n\n\ndef _bf16_fp4_cute_dsl_tactic_configs(\n n: int, k: int\n) -> List[Tuple[Tuple[int, int, int], Tuple[int, int, int], int, int, int]]:\n \"\"\"Enumerate cute-DSL tactic configs for a given ``(N, K)``.\n\n Returns a list of ``(tile_shape_mnk, atom_layout, pipeline_depth,\n use_fp16_mma)`` tuples.\n \"\"\"\n tile_k = 128 if k % 128 == 0 else 64\n\n # (tile_M, atom_layout) shapes the kernel is designed/validated for, at the\n # default tile_N=64; a tile_N=128 variant is added below for very large N.\n tile_m_atoms: List[Tuple[int, Tuple[int, int, int]]] = []\n if tile_k == 128:\n tile_m_atoms.append((16, (1, 2, 1)))\n tile_m_atoms.append((32, (2, 2, 1)))\n tile_m_atoms.append((64, (2, 2, 1)))\n\n configs: List[Tuple[Tuple[int, int, int], Tuple[int, int, int], int, int, int]] = []\n seen = set()\n\n def add(tile_m, atom, pdepth, fp16, tile_n=64, tk=None, swz=1):\n cfg = (\n (tile_m, tile_n, tile_k if tk is None else tk),\n atom,\n pdepth,\n fp16,\n swz,\n )\n key = (cfg[0], cfg[1], pdepth, fp16, swz)\n if key not in seen:\n seen.add(key)\n configs.append(cfg)\n\n base_tile_m, base_atom = tile_m_atoms[0]\n add(base_tile_m, base_atom, 1, 1) # 0: baseline\n add(base_tile_m, base_atom, 0, 1) # no dequant prefetch (helps short-K)\n for tile_m, atom in tile_m_atoms[1:]:\n add(tile_m, atom, 1, 1)\n\n # tile_N=128 halves the (m,n)-tile count but needs large wave count.\n if tile_k == 128 and n >= 12288 and n % 128 == 0:\n add(base_tile_m, base_atom, 1, 1, tile_n=128)\n\n # tile_K=64 has more ab stages, but requires larger problem size.\n if tile_k == 128 and n >= 8192:\n add(base_tile_m, base_atom, 1, 1, tile_n=64, tk=64)\n\n # tile_M=128 (taller M tile, atom (2,2,1)) -- the large-M *prefill* lever.\n if tile_k == 128:\n add(128, (2, 2, 1), 1, 1)\n\n # Threadblock swizzle (tile_swizzle=8) -- for large-M prefill.\n if tile_k == 128 and n * k >= 16 * 1024 * 1024:\n add(64, (2, 2, 1), 1, 1, swz=8)\n if tile_k == 128:\n add(128, (2, 2, 1), 1, 1, swz=8)\n\n # tile_N=128 (with tile_M=64, atom (2,2,1)) -- large shapes.\n if tile_k == 128 and n % 128 == 0 and n >= 4096:\n add(64, (2, 2, 1), 1, 1, tile_n=128, swz=8)\n add(64, (2, 2, 1), 1, 1, tile_n=128, swz=1)\n\n return configs\n\n\n_BF16_FP4_CUTE_DSL_TUNING_CONFIG = TuningConfig(\n dynamic_tensor_specs=(\n DynamicTensorSpec(\n (0,), # a_tensor_index\n (0,), # M dimension\n get_hybrid_num_tokens_buckets,\n map_to_hybrid_bucket_uncapped,\n ),\n ),\n constraint_specs=(\n ConstraintSpec(\n 5, # out_tensor_index follows M\n 0,\n lambda shapes: shapes[0][0],\n ),\n ),\n)\n\n\ndef _cute_dsl_bf16_fp4_runner(enable_pdl: bool = True) -> TunableRunner:\n \"\"\"Build a ``CuteDslBf16Fp4Runner`` for the cute-DSL bf16 x fp4 GEMM.\"\"\"\n\n class CuteDslBf16Fp4Runner(TunableRunner):\n def get_cache_key_extras(self, inputs: List[torch.Tensor]) -> tuple:\n a, b, _, _, out_dtype, _, block_size = inputs\n n = int(b.shape[1]) // 2\n k = int(b.shape[0]) * int(block_size)\n return (out_dtype, n, k)\n\n def get_valid_tactics(\n self,\n inputs: List[torch.Tensor],\n profile: OptimizationProfile,\n ) -> List[int]:\n _, b, _, _, _, _, block_size = inputs\n n = int(b.shape[1]) // 2\n k = int(b.shape[0]) * int(block_size)\n return list(range(len(_bf16_fp4_cute_dsl_tactic_configs(n, k))))\n\n def forward(\n self,\n inputs: List[torch.Tensor],\n tactic: int = -1,\n do_preparation: bool = False,\n **kwargs,\n ) -> torch.Tensor:\n a, b, b_sf_u8, alpha_for_launch, out_dtype, out, block_size = inputs\n n = int(b.shape[1]) // 2\n k = int(b.shape[0]) * int(block_size)\n m = int(a.shape[0])\n if tactic < 0:\n # Fallback == pre-autotuner heuristic (M-aware), default knobs.\n tile_shape_mnk, atom_layout = _select_bf16_fp4_tile_shape(m, n, k)\n pipeline_depth, use_fp16_mma, tile_swizzle = 1, 1, 1\n else:\n (\n tile_shape_mnk,\n atom_layout,\n pipeline_depth,\n use_fp16_mma,\n tile_swizzle,\n ) = _bf16_fp4_cute_dsl_tactic_configs(n, k)[tactic]\n compiled = _get_cute_dsl_bf16_fp4_gemm(\n tile_shape_mnk,\n a.dtype,\n out_dtype,\n atom_layout,\n pipeline_depth,\n use_fp16_mma,\n enable_pdl=enable_pdl,\n tile_swizzle=tile_swizzle,\n )\n compiled(a, b, b_sf_u8, out, alpha_for_launch)\n return out\n\n return CuteDslBf16Fp4Runner()\n\n\ndef _compute_cute_dsl(\n a: torch.Tensor,\n b: torch.Tensor,\n b_descale: torch.Tensor,\n alpha: Optional[torch.Tensor],\n out_dtype: torch.dtype,\n out: Optional[torch.Tensor],\n block_size: int,\n enable_pdl: bool = True,\n) -> torch.Tensor:\n \"\"\"cute-DSL-backend compute: dispatch to the compiled Blackwell kernel.\n\n ``b`` is the packed ``(K // 16, N * 2)`` int32 weight and\n ``b_descale`` the ``(K // block_size, N)`` uint8 SF in S0E5M3 format\n (reformatted from FP8-E4M3 by :func:`_e4m3_to_s0e5m3`) returned by\n :func:`_prepare_cute_dsl`.\n \"\"\"\n if b.dtype != torch.int32:\n raise TypeError(\n f\"cute-dsl backend expects the packed int32 weight from \"\n f\"prepare_bf16_fp4_weights(..., backend='cute-dsl'); got {b.dtype}.\"\n )\n if out_dtype != a.dtype:\n raise NotImplementedError(\n f\"cute-dsl backend requires out_dtype == a.dtype (got \"\n f\"out_dtype={out_dtype}, a.dtype={a.dtype}). Use the cudnn \"\n f\"backend for a mismatched output dtype.\"\n )\n k_tiles = int(b.shape[0])\n n = int(b.shape[1]) // 2\n k = k_tiles * block_size\n m = int(a.shape[0])\n if a.shape[1] != k:\n raise ValueError(\n f\"a.shape[1]={a.shape[1]} but k inferred from prepared b.shape=\"\n f\"{tuple(b.shape)} is {k}\"\n )\n\n if out is None:\n out = torch.empty((m, n), device=a.device, dtype=out_dtype)\n else:\n if tuple(out.shape) != (m, n):\n raise ValueError(f\"out shape {tuple(out.shape)} != expected {(m, n)}\")\n if out.dtype != out_dtype:\n raise TypeError(f\"out dtype {out.dtype} != requested out_dtype {out_dtype}\")\n\n b_sf_u8 = b_descale.view(torch.uint8).contiguous()\n alpha_for_launch = _prepare_bf16_fp4_alpha(alpha, a.device)\n\n tuner = AutoTuner.get()\n runner = _cute_dsl_bf16_fp4_runner(enable_pdl=enable_pdl)\n inputs = [a, b, b_sf_u8, alpha_for_launch, out_dtype, out, block_size]\n chosen_runner, tactic = tuner.choose_one(\n \"bf16_fp4_cute_dsl_gemm\",\n [runner],\n _BF16_FP4_CUTE_DSL_TUNING_CONFIG,\n inputs,\n )\n chosen_runner(inputs=inputs, tactic=tactic)\n return out\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## 📌 Description\n\n#3597 added `mm_bf16_fp4` (bf16 activations x nvfp4 weights) so vLLM can replace Marlin, its default W4A16 backend, with a FlashInfer kernel; DGX Spark is the lead target. On decode shapes the kernel trailed Marlin for two reasons: small-n grids underfill the GPU, and at single-token batches (m=1) too few resident warps per SM hide DRAM latency. This PR addresses both: m=1 decode beats or matches Marlin on every part we measured, and end-to-end serving of Qwen3.6-27B-NVFP4 flips from behind to ahead at batch 1 with no regression elsewhere.\n\n**What it does**\n\n- Adds split-K tactics (2/4/8 splits) to the autotuner space, offered only when splitting shortens the grid's last wave by at least 25%. Splits write fp32 partials, and a PDL-chained reduce kernel sums them in fixed order, so results are deterministic run to run.\n- Adds occupancy tactics: 2 or 3 co-resident CTAs per SM trade pipeline depth for latency hiding on weight-bound grids, plus occupancy 2 combined with split-K for narrow-n shapes.\n- Adds a streaming GEMV kernel (`gemv_bf16_fp4_sm12x.py`) for the bandwidth-bound m=1 case: no shared memory, no tensor cores, weights stream from global memory to registers with latency hidden by warp count. It reads the same packed operands as the MMA kernel, so the autotuner picks between the two per shape.\n- Sizes GEMV split-K from the device: alongside the power-of-2 splits, the menu carries a split targeting ~20 warps/SM (the measured saturation point). Tactic indices become device-scoped, so the autotuner cache key now carries the SM count.\n- Routes the no-autotune m=1 fallback onto the GEMV. Serving stacks do not tune every shape (vLLM's warmup never captures the logits GEMM), so the lm_head always takes this path.\n- Fixes kernel launch to pass no cluster dimensions: the boilerplate `cluster=[1,1,1]` routed launches through the cluster work distributor, whose co-residency cap silently defeated the occupancy tactics on SM12x.\n\nNo public API changes. The one observable behavior change: untuned m=1 calls on SM12x now run the GEMV, whose output is bitwise different from the MMA heuristic's but equally accurate and still deterministic.\n\n### Performance\n\n#### Split-K on the #3597 decode shapes (RTX PRO 6000 / DGX Spark / RTX 5080)\n\nSingle-token decode GEMMs (m=1). The first table covers serving-class shapes (Llama-8B projection layers plus the #3597 example shape); the second covers #3597's own benchmark grid. Median GPU time over CUDA-graph replays with a cold L2 cache, as in serving. Baseline is vLLM's Marlin on the same GPU; FlashInfer runs with autotuning. Speedup = Marlin time / FlashInfer time. Each cell is a RTX PRO 6000 / DGX Spark / RTX 5080 triple.\n\n| n x k | vs Marlin, before this PR | vs Marlin, with this PR |\n|--:|:--:|:--:|\n| 2048x7168 | 0.57 / 1.00 / 0.47 | **1.36** / **1.02** / **0.78** |\n| 4096x4096 | 0.75 / 0.91 / 0.90 | **1.06** / **1.00** / 0.90 |\n| 4096x14336 | 0.60 / 0.91 / 0.78 | **0.98** / **1.00** / 0.78 |\n| 14336x4096 | 0.97 / 1.00 / 0.86 | 0.97 / 1.00 / 0.86 |\n| 10304x2688 | 0.78 / 0.98 / 0.96 | 0.78 / 0.98 / 0.96 |\n\nThe same comparison over #3597's benchmark grid (4096x4096 appears in the table above):\n\n| n x k | vs Marlin, before this PR | vs Marlin, with this PR |\n|--:|:--:|:--:|\n| 512x2048 | 2.09 / 0.95 / 0.95 | **4.48** / **1.43** / **2.30** |\n| 512x4096 | 1.19 / 0.70 / 0.56 | **3.61** / **1.26** / **1.88** |\n| 1024x2048 | 1.26 / 0.98 / 0.70 | **2.39** / **1.03** / **1.32** |\n| 1024x4096 | 0.99 / 0.86 / 0.49 | **2.72** / **1.04** / **1.21** |\n| 2048x512 | 1.86 / 1.25 / 1.19 | 1.86 / 1.25 / 1.19 |\n| 2048x1024 | 1.36 / 1.16 / 0.90 | **1.40** / 1.16 / **1.02** |\n| 2048x2048 | 1.17 / 1.11 / 0.70 | **1.72** / **1.02**\\* (1.11) / **0.97** |\n| 2048x4096 | 0.73 / 1.08 / 0.54 | **1.48** / **1.04**\\* (1.08) / **0.84** |\n| 4096x512 | 1.40 / 1.01 / 1.38 | 1.40 / **0.95**\\* (1.01) / 1.38 |\n| 4096x1024 | 1.41 / 0.93 / 1.18 | 1.41 / **0.95** / 1.18 |\n| 4096x2048 | 0.95 / 0.95 / 1.06 | 0.95 / **1.00** / 1.06 |\n| 131072x2048 | 0.98 / 0.97 / 0.90 | 0.98 / 0.97 / 0.90 |\n| 248320x2048 | 0.98 / 1.00 / 0.93 | 0.98 / 1.00 / 0.93 |\n\n- Bold marks the cells this PR changes (the tuner picks a new split-K tactic); unbolded picks perform as before.\n- \\* These three cells are tuner mis-picks, not kernel regressions: an accurate pick would keep #3597's pre-existing non-split config, and the value in parentheses is what that config achieves. The Reviewer Notes explain the cause.\n- On the serving shapes, the RTX 5080 column stays below 1.0 even where this PR helps. Profiling of the larger losses points to activation re-reads through L2, a separate problem from grid fill and out of scope here.\n\n#### Qwen3.6-27B-NVFP4 decode GEMMs at m=1 (RTX 5080, DGX Spark)\n\nSame methodology as above; speedup = Marlin time / FlashInfer time.\n\n| GEMM (n x k) | RTX 5080 | DGX Spark |\n|--|:--:|:--:|\n| gate_up 34816x5120 | **1.03** | 1.00 |\n| down 5120x17408 | **1.03** | 1.00 |\n| lm_head 248320x5120 | **1.04**\\* | **1.04** |\n\n\\* Marlin's lm_head repack does not fit on the 16 GB RTX 5080, so this cell compares against the best in-tree MMA tactic. Spark ties at its bandwidth floor on the first two shapes.\n\n#### End-to-end vLLM serving of Qwen3.6-27B-NVFP4 (RTX PRO 6000)\n\nFull serving A/B, FlashInfer leg vs Marlin leg under identical settings, aiperf output-token throughput, ratio = FlashInfer / Marlin: batch-1 decode 1.011x, low-concurrency speculative decode 1.08 to 1.11x ahead, and every other cell at parity within run-to-run noise (0.978 to 1.014x) with no regression beyond it.\n\n## 🔍 Related Issues\n\nFollow-up to #3597.\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\nNew tests:\n\n- Every enumerated tactic (MMA and GEMV) is checked against a reference and for bit-exact run-to-run determinism.\n- Unit tests pin the fallback selectors' picks; one test drives tactic=-1 through the GEMV fallback end to end.\n- Full test file passes on RTX 5080, RTX PRO 6000, and GB10.\n\n## Reviewer Notes\n\n- Most gains require autotuning, which serving frameworks run at startup. The no-autotune fallback picks match the tuner's choices on every part we measured.\n- The autotuner times candidates with a warm L2 while decode serving runs cold, so it can over-rank split tactics; the 25% last-wave guard compensates but does not fully close it (the three Spark cells in the grid table). This measurement gap is general and deserves its own issue.\n- The fallback picks add JIT-compiled kernel variants per decode shape class, cached in-process only; that cost amortizes to once per machine when this module adopts the #3874 CuTe-DSL disk cache, as #4029 did for the sibling `mm_fp4` path. The GEMV's device-derived splits widen this surface, so the follow-up is worth prioritizing.\n- Other FlashInfer cute-dsl kernels also pass `cluster=[1,1,1]` at launch and inherit the same co-residency cap; they are worth a separate audit.\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n- **New Features**\n - Added split-K support for bf16 × fp4 matrix multiplication to improve performance across varying workloads.\n - Added a dedicated SM12x GEMV path for efficient single-row operations.\n - Added automatic tuning for split counts, occupancy, and device-specific execution strategies.\n - Added support for FP16 GEMV outputs and deterministic partial-result reduction.\n\n- **Bug Fixes**\n - Improved handling of GEMV and split-K fallback selection across supported shapes and GPU configurations.\n\n- **Tests**\n - Added coverage for accuracy, determinism, GEMV correctness, and split-K selection.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000\", \"model\": null, \"shape\": \"n=2048,k=7168\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 0.57, \"optimized\": 1.36, \"stated_speedup\": null, \"speedup\": 2.386}, {\"scope\": \"kernel\", \"hardware\": \"DGX Spark\", \"model\": null, \"shape\": \"n=2048,k=7168\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 1.0, \"optimized\": 1.02, \"stated_speedup\": null, \"speedup\": 1.02}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"n=2048,k=7168\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 0.47, \"optimized\": 0.78, \"stated_speedup\": null, \"speedup\": 1.6596}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000\", \"model\": null, \"shape\": \"n=4096,k=4096\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 0.75, \"optimized\": 1.06, \"stated_speedup\": null, \"speedup\": 1.4133}, {\"scope\": \"kernel\", \"hardware\": \"DGX Spark\", \"model\": null, \"shape\": \"n=4096,k=4096\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 0.91, \"optimized\": 1.0, \"stated_speedup\": null, \"speedup\": 1.0989}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"n=4096,k=4096\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 0.9, \"optimized\": 0.9, \"stated_speedup\": null, \"speedup\": 1.0}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000\", \"model\": null, \"shape\": \"n=4096,k=14336\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 0.6, \"optimized\": 0.98, \"stated_speedup\": null, \"speedup\": 1.6333}, {\"scope\": \"kernel\", \"hardware\": \"DGX Spark\", \"model\": null, \"shape\": \"n=4096,k=14336\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 0.91, \"optimized\": 1.0, \"stated_speedup\": null, \"speedup\": 1.0989}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"n=4096,k=14336\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 0.78, \"optimized\": 0.78, \"stated_speedup\": null, \"speedup\": 1.0}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000\", \"model\": null, \"shape\": \"n=512,k=2048\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 2.09, \"optimized\": 4.48, \"stated_speedup\": null, \"speedup\": 2.1435}, {\"scope\": \"kernel\", \"hardware\": \"DGX Spark\", \"model\": null, \"shape\": \"n=512,k=2048\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 0.95, \"optimized\": 1.43, \"stated_speedup\": null, \"speedup\": 1.5053}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"n=512,k=2048\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 0.95, \"optimized\": 2.3, \"stated_speedup\": null, \"speedup\": 2.4211}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000\", \"model\": null, \"shape\": \"n=512,k=4096\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 1.19, \"optimized\": 3.61, \"stated_speedup\": null, \"speedup\": 3.0336}, {\"scope\": \"kernel\", \"hardware\": \"DGX Spark\", \"model\": null, \"shape\": \"n=512,k=4096\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 0.7, \"optimized\": 1.26, \"stated_speedup\": null, \"speedup\": 1.8}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"n=512,k=4096\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 0.56, \"optimized\": 1.88, \"stated_speedup\": null, \"speedup\": 3.3571}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000\", \"model\": null, \"shape\": \"n=1024,k=2048\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 1.26, \"optimized\": 2.39, \"stated_speedup\": null, \"speedup\": 1.8968}, {\"scope\": \"kernel\", \"hardware\": \"DGX Spark\", \"model\": null, \"shape\": \"n=1024,k=2048\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 0.98, \"optimized\": 1.03, \"stated_speedup\": null, \"speedup\": 1.051}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"n=1024,k=2048\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 0.7, \"optimized\": 1.32, \"stated_speedup\": null, \"speedup\": 1.8857}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000\", \"model\": null, \"shape\": \"n=1024,k=4096\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 0.99, \"optimized\": 2.72, \"stated_speedup\": null, \"speedup\": 2.7475}, {\"scope\": \"kernel\", \"hardware\": \"DGX Spark\", \"model\": null, \"shape\": \"n=1024,k=4096\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 0.86, \"optimized\": 1.04, \"stated_speedup\": null, \"speedup\": 1.2093}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"n=1024,k=4096\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 0.49, \"optimized\": 1.21, \"stated_speedup\": null, \"speedup\": 2.4694}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000\", \"model\": null, \"shape\": \"n=2048,k=1024\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 1.36, \"optimized\": 1.4, \"stated_speedup\": null, \"speedup\": 1.0294}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"n=2048,k=1024\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 0.9, \"optimized\": 1.02, \"stated_speedup\": null, \"speedup\": 1.1333}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000\", \"model\": null, \"shape\": \"n=2048,k=2048\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 1.17, \"optimized\": 1.72, \"stated_speedup\": null, \"speedup\": 1.4701}, {\"scope\": \"kernel\", \"hardware\": \"DGX Spark\", \"model\": null, \"shape\": \"n=2048,k=2048\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 1.11, \"optimized\": 1.02, \"stated_speedup\": null, \"speedup\": 0.9189}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"n=2048,k=2048\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 0.7, \"optimized\": 0.97, \"stated_speedup\": null, \"speedup\": 1.3857}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000\", \"model\": null, \"shape\": \"n=2048,k=4096\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 0.73, \"optimized\": 1.48, \"stated_speedup\": null, \"speedup\": 2.0274}, {\"scope\": \"kernel\", \"hardware\": \"DGX Spark\", \"model\": null, \"shape\": \"n=2048,k=4096\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 1.08, \"optimized\": 1.04, \"stated_speedup\": null, \"speedup\": 0.963}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"n=2048,k=4096\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 0.54, \"optimized\": 0.84, \"stated_speedup\": null, \"speedup\": 1.5556}, {\"scope\": \"kernel\", \"hardware\": \"DGX Spark\", \"model\": null, \"shape\": \"n=4096,k=512\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 1.01, \"optimized\": 0.95, \"stated_speedup\": null, \"speedup\": 0.9406}, {\"scope\": \"kernel\", \"hardware\": \"DGX Spark\", \"model\": null, \"shape\": \"n=4096,k=1024\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 0.93, \"optimized\": 0.95, \"stated_speedup\": null, \"speedup\": 1.0215}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": \"Qwen3.6-27B-NVFP4\", \"shape\": \"n=34816,k=5120\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 1.0, \"optimized\": 1.03, \"stated_speedup\": null, \"speedup\": 1.03}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": \"Qwen3.6-27B-NVFP4\", \"shape\": \"n=5120,k=17408\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 1.0, \"optimized\": 1.03, \"stated_speedup\": null, \"speedup\": 1.03}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": \"Qwen3.6-27B-NVFP4\", \"shape\": \"n=248320,k=5120\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 1.0, \"optimized\": 1.04, \"stated_speedup\": null, \"speedup\": 1.04}, {\"scope\": \"kernel\", \"hardware\": \"DGX Spark\", \"model\": \"Qwen3.6-27B-NVFP4\", \"shape\": \"n=248320,k=5120\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 1.0, \"optimized\": 1.04, \"stated_speedup\": null, \"speedup\": 1.04}, {\"scope\": \"e2e\", \"hardware\": \"RTX PRO 6000\", \"model\": \"Qwen3.6-27B-NVFP4\", \"shape\": null, \"batch_size\": 1, \"metric\": \"throughput\", \"unit\": \"tok/s\", \"higher_is_better\": true, \"baseline\": 1.0, \"optimized\": 1.011, \"stated_speedup\": 1.011, \"speedup\": 1.011}, {\"scope\": \"e2e\", \"hardware\": \"RTX PRO 6000\", \"model\": \"Qwen3.6-27B-NVFP4\", \"shape\": null, \"batch_size\": null, \"metric\": \"throughput\", \"unit\": \"tok/s\", \"higher_is_better\": true, \"baseline\": 1.0, \"optimized\": 1.08, \"stated_speedup\": 1.08, \"speedup\": 1.08}, {\"scope\": \"e2e\", \"hardware\": \"RTX PRO 6000\", \"model\": \"Qwen3.6-27B-NVFP4\", \"shape\": null, \"batch_size\": null, \"metric\": \"throughput\", \"unit\": \"tok/s\", \"higher_is_better\": true, \"baseline\": 1.0, \"optimized\": 1.11, \"stated_speedup\": 1.11, \"speedup\": 1.11}]"},"kernel_speedup":{"kind":"number","value":1.3857,"string":"1.3857"},"e2e_speedup":{"kind":"number","value":1.08,"string":"1.08"}}},{"rowIdx":1088,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"53a1c3bd7a3f384d3a8fd1261cc99d80bcf9d188"},"date":{"kind":"string","value":"2026-08-12T20:56:49-07:00"},"pr_number":{"kind":"number","value":4038,"string":"4,038"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/4038"},"title":{"kind":"string","value":"perf(gemm): split-K, occupancy, and m=1 stream-GEMV decode tactics for mm_bf16_fp4 (#4038)"},"message":{"kind":"string","value":"perf(gemm): split-K, occupancy, and m=1 stream-GEMV decode tactics for mm_bf16_fp4 (#4038)\n\n## 📌 Description\n\n#3597 added `mm_bf16_fp4` (bf16 activations x nvfp4 weights) so vLLM can\nreplace Marlin, its default W4A16 backend, with a FlashInfer kernel; DGX\nSpark is the lead target. On decode shapes the kernel trailed Marlin for\ntwo reasons: small-n grids underfill the GPU, and at single-token\nbatches (m=1) too few resident warps per SM hide DRAM latency. This PR\naddresses both: m=1 decode beats or matches Marlin on every part we\nmeasured, and end-to-end serving of Qwen3.6-27B-NVFP4 flips from behind\nto ahead at batch 1 with no regression elsewhere.\n\n**What it does**\n\n- Adds split-K tactics (2/4/8 splits) to the autotuner space, offered\nonly when splitting shortens the grid's last wave by at least 25%.\nSplits write fp32 partials, and a PDL-chained reduce kernel sums them in\nfixed order, so results are deterministic run to run.\n- Adds occupancy tactics: 2 or 3 co-resident CTAs per SM trade pipeline\ndepth for latency hiding on weight-bound grids, plus occupancy 2\ncombined with split-K for narrow-n shapes.\n- Adds a streaming GEMV kernel (`gemv_bf16_fp4_sm12x.py`) for the\nbandwidth-bound m=1 case: no shared memory, no tensor cores, weights\nstream from global memory to registers with latency hidden by warp\ncount. It reads the same packed operands as the MMA kernel, so the\nautotuner picks between the two per shape.\n- Sizes GEMV split-K from the device: alongside the power-of-2 splits,\nthe menu carries a split targeting ~20 warps/SM (the measured saturation\npoint). Tactic indices become device-scoped, so the autotuner cache key\nnow carries the SM count.\n- Routes the no-autotune m=1 fallback onto the GEMV. Serving stacks do\nnot tune every shape (vLLM's warmup never captures the logits GEMM), so\nthe lm_head always takes this path.\n- Fixes kernel launch to pass no cluster dimensions: the boilerplate\n`cluster=[1,1,1]` routed launches through the cluster work distributor,\nwhose co-residency cap silently defeated the occupancy tactics on SM12x.\n\nNo public API changes. The one observable behavior change: untuned m=1\ncalls on SM12x now run the GEMV, whose output is bitwise different from\nthe MMA heuristic's but equally accurate and still deterministic.\n\n### Performance\n\n#### Split-K on the #3597 decode shapes (RTX PRO 6000 / DGX Spark / RTX\n5080)\n\nSingle-token decode GEMMs (m=1). The first table covers serving-class\nshapes (Llama-8B projection layers plus the #3597 example shape); the\nsecond covers #3597's own benchmark grid. Median GPU time over\nCUDA-graph replays with a cold L2 cache, as in serving. Baseline is\nvLLM's Marlin on the same GPU; FlashInfer runs with autotuning. Speedup\n= Marlin time / FlashInfer time. Each cell is a RTX PRO 6000 / DGX Spark\n/ RTX 5080 triple.\n\n| n x k | vs Marlin, before this PR | vs Marlin, with this PR |\n|--:|:--:|:--:|\n| 2048x7168 | 0.57 / 1.00 / 0.47 | **1.36** / **1.02** / **0.78** |\n| 4096x4096 | 0.75 / 0.91 / 0.90 | **1.06** / **1.00** / 0.90 |\n| 4096x14336 | 0.60 / 0.91 / 0.78 | **0.98** / **1.00** / 0.78 |\n| 14336x4096 | 0.97 / 1.00 / 0.86 | 0.97 / 1.00 / 0.86 |\n| 10304x2688 | 0.78 / 0.98 / 0.96 | 0.78 / 0.98 / 0.96 |\n\nThe same comparison over #3597's benchmark grid (4096x4096 appears in\nthe table above):\n\n| n x k | vs Marlin, before this PR | vs Marlin, with this PR |\n|--:|:--:|:--:|\n| 512x2048 | 2.09 / 0.95 / 0.95 | **4.48** / **1.43** / **2.30** |\n| 512x4096 | 1.19 / 0.70 / 0.56 | **3.61** / **1.26** / **1.88** |\n| 1024x2048 | 1.26 / 0.98 / 0.70 | **2.39** / **1.03** / **1.32** |\n| 1024x4096 | 0.99 / 0.86 / 0.49 | **2.72** / **1.04** / **1.21** |\n| 2048x512 | 1.86 / 1.25 / 1.19 | 1.86 / 1.25 / 1.19 |\n| 2048x1024 | 1.36 / 1.16 / 0.90 | **1.40** / 1.16 / **1.02** |\n| 2048x2048 | 1.17 / 1.11 / 0.70 | **1.72** / **1.02**\\* (1.11) /\n**0.97** |\n| 2048x4096 | 0.73 / 1.08 / 0.54 | **1.48** / **1.04**\\* (1.08) /\n**0.84** |\n| 4096x512 | 1.40 / 1.01 / 1.38 | 1.40 / **0.95**\\* (1.01) / 1.38 |\n| 4096x1024 | 1.41 / 0.93 / 1.18 | 1.41 / **0.95** / 1.18 |\n| 4096x2048 | 0.95 / 0.95 / 1.06 | 0.95 / **1.00** / 1.06 |\n| 131072x2048 | 0.98 / 0.97 / 0.90 | 0.98 / 0.97 / 0.90 |\n| 248320x2048 | 0.98 / 1.00 / 0.93 | 0.98 / 1.00 / 0.93 |\n\n- Bold marks the cells this PR changes (the tuner picks a new split-K\ntactic); unbolded picks perform as before.\n- \\* These three cells are tuner mis-picks, not kernel regressions: an\naccurate pick would keep #3597's pre-existing non-split config, and the\nvalue in parentheses is what that config achieves. The Reviewer Notes\nexplain the cause.\n- On the serving shapes, the RTX 5080 column stays below 1.0 even where\nthis PR helps. Profiling of the larger losses points to activation\nre-reads through L2, a separate problem from grid fill and out of scope\nhere.\n\n#### Qwen3.6-27B-NVFP4 decode GEMMs at m=1 (RTX 5080, DGX Spark)\n\nSame methodology as above; speedup = Marlin time / FlashInfer time.\n\n| GEMM (n x k) | RTX 5080 | DGX Spark |\n|--|:--:|:--:|\n| gate_up 34816x5120 | **1.03** | 1.00 |\n| down 5120x17408 | **1.03** | 1.00 |\n| lm_head 248320x5120 | **1.04**\\* | **1.04** |\n\n\\* Marlin's lm_head repack does not fit on the 16 GB RTX 5080, so this\ncell compares against the best in-tree MMA tactic. Spark ties at its\nbandwidth floor on the first two shapes.\n\n#### End-to-end vLLM serving of Qwen3.6-27B-NVFP4 (RTX PRO 6000)\n\nFull serving A/B, FlashInfer leg vs Marlin leg under identical settings,\naiperf output-token throughput, ratio = FlashInfer / Marlin: batch-1\ndecode 1.011x, low-concurrency speculative decode 1.08 to 1.11x ahead,\nand every other cell at parity within run-to-run noise (0.978 to 1.014x)\nwith no regression beyond it.\n\n## 🔍 Related Issues\n\nFollow-up to #3597.\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\nNew tests:\n\n- Every enumerated tactic (MMA and GEMV) is checked against a reference\nand for bit-exact run-to-run determinism.\n- Unit tests pin the fallback selectors' picks; one test drives\ntactic=-1 through the GEMV fallback end to end.\n- Full test file passes on RTX 5080, RTX PRO 6000, and GB10.\n\n## Reviewer Notes\n\n- Most gains require autotuning, which serving frameworks run at\nstartup. The no-autotune fallback picks match the tuner's choices on\nevery part we measured.\n- The autotuner times candidates with a warm L2 while decode serving\nruns cold, so it can over-rank split tactics; the 25% last-wave guard\ncompensates but does not fully close it (the three Spark cells in the\ngrid table). This measurement gap is general and deserves its own issue.\n- The fallback picks add JIT-compiled kernel variants per decode shape\nclass, cached in-process only; that cost amortizes to once per machine\nwhen this module adopts the #3874 CuTe-DSL disk cache, as #4029 did for\nthe sibling `mm_fp4` path. The GEMV's device-derived splits widen this\nsurface, so the follow-up is worth prioritizing.\n- Other FlashInfer cute-dsl kernels also pass `cluster=[1,1,1]` at\nlaunch and inherit the same co-residency cap; they are worth a separate\naudit.\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n- **New Features**\n- Added split-K support for bf16 × fp4 matrix multiplication to improve\nperformance across varying workloads.\n- Added a dedicated SM12x GEMV path for efficient single-row operations.\n- Added automatic tuning for split counts, occupancy, and\ndevice-specific execution strategies.\n- Added support for FP16 GEMV outputs and deterministic partial-result\nreduction.\n\n- **Bug F"},"path":{"kind":"string","value":"flashinfer/gemm/kernels/cute_dsl/dense_gemm_bf16_fp4_blackwell.py"},"language":{"kind":"string","value":"cute_dsl"},"license":{"kind":"string","value":"BSD-3-Clause"},"before_code":{"kind":"string","value":"# Copyright (c) 2025 - 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.\n# SPDX-License-Identifier: BSD-3-Clause\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions are met:\n#\n# 1. Redistributions of source code must retain the above copyright notice, this\n# list of conditions and the following disclaimer.\n#\n# 2. Redistributions in binary form must reproduce the above copyright notice,\n# this list of conditions and the following disclaimer in the documentation\n# and/or other materials provided with the distribution.\n#\n# 3. Neither the name of the copyright holder nor the names of its\n# contributors may be used to endorse or promote products derived from\n# this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n\"\"\"bf16 x fp4 dense GEMM for Blackwell (SM100/103/120/121).\n\nBuilt on top of ``dense_gemm_bf16_blackwell.py`` from cutlass examples at\nhttps://github.com/NVIDIA/cutlass/blob/main/examples/python/CuTeDSL/cute/blackwell_geforce/kernel/dense_gemm/dense_gemm.py\n\"\"\"\n\nfrom typing import Optional, Tuple, Type\n\nimport cuda.bindings.driver as cuda\n\nimport cutlass\nimport cutlass.cute as cute\nimport cutlass.pipeline as pipeline\nimport cutlass.utils as utils\nimport cutlass.utils.hopper_helpers as sm90_utils\nfrom cutlass import Float32, Int32, Uint32\n\nfrom ....cute_dsl.fp4_common import (\n cvt_s0e5m3_to_f16x2_broadcast,\n f16x2_to_f32x2,\n fp4_decode_4bytes,\n get_smem_ptr_as_int32,\n half2_mul,\n ld_shared_v2_u32,\n)\nfrom cutlass._mlir import ir\nfrom cutlass._mlir.dialects import llvm\nfrom cutlass._mlir.extras import types as T\nfrom cutlass.cutlass_dsl import dsl_user_op\n\n\n@dsl_user_op\ndef cvt_bf16x2_to_f16x2_via_f32(packed_bf16x2: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Packed bf16x2 (u32) -> f16x2 (u32) via f32 intermediate.\n\n Used by the fp16-MMA path (use_fp16_mma=1) to convert A's ldmatrix\n output (bf16 bit pattern from sA) to fp16 bit pattern for the fp16\n MMA inputs. Direct ``cvt.rn.f16x2.bf16x2`` is rejected by ptxas on\n sm_100a / CUDA 13.1; this packed via-f32 path is 4 PTX instrs per\n pair (mov.b32 unpack + 2x cvt.f32.bf16 + 1x cvt.rn.f16x2.f32).\n \"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(packed_bf16x2).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 b_lo, b_hi;\n .reg .f32 f_lo, f_hi;\n mov.b32 {b_lo, b_hi}, $1;\n cvt.f32.bf16 f_lo, b_lo;\n cvt.f32.bf16 f_hi, b_hi;\n cvt.rn.f16x2.f32 $0, f_hi, f_lo;\n }\n \"\"\",\n \"=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef f16x2_unpack(\n packed_h2: Uint32, *, loc=None, ip=None\n) -> Tuple[\"cutlass.Float16\", \"cutlass.Float16\"]:\n \"\"\"Unpack f16x2 (u32) into (f16_lo, f16_hi). Free at HW level --\n just a register-rename (mov.b32 {h_lo, h_hi}, packed). Used by the\n fp16-MMA path to bypass the f16->f32->bf16 cvt chain that the\n default bf16-MMA path needs after hmul2.\"\"\"\n from cutlass import Float16\n\n res = llvm.inline_asm(\n ir.Type.parse(\"!llvm.struct<(f16, f16)>\"),\n [Uint32(packed_h2).ir_value(loc=loc, ip=ip)],\n \"mov.b32 {$0, $1}, $2;\",\n \"=h,=h,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n return (\n Float16(llvm.extractvalue(T.f16(), res, [0], loc=loc, ip=ip)),\n Float16(llvm.extractvalue(T.f16(), res, [1], loc=loc, ip=ip)),\n )\n\n\n# FP4 weight packing constants (must match _cute_dsl_pack_fp4_weight in\n# flashinfer/gemm/gemm_bf16_fp4_cute_dsl.py).\n_PACK_TILE_K: cutlass.Constexpr = 16\n_PACK_TILE_N: cutlass.Constexpr = 64\n_PACK_INTS_PER_TILE: cutlass.Constexpr = 128 # 128 int32 per (16K x 64N) block\n\n\nclass BlackwellDenseGemmBf16Fp4Kernel:\n \"\"\"Warp-MMA dense GEMM for Blackwell, FP4-weight A bf16/fp16 input.\n\n A: (M, K, L) bf16/fp16.\n B: (K // 16, N * 2, L) int32 -- packed FP4 (see prepare).\n B_sf: (K // 16, N, L) uint8 -- per-group scales (S0E5M3).\n alpha: (1,) fp32 -- global scalar scale.\n C: (M, N, L) bf16/fp16; fp32 accumulator cast at write.\n\n \"\"\"\n\n GROUP_SIZE: cutlass.Constexpr = 16\n\n def __init__(\n self,\n acc_dtype,\n tile_shape_mnk,\n epi_stage: int = 4,\n pipeline_depth: int = 1,\n atom_layout: Tuple[int, int, int] = (2, 2, 1),\n epi_tile_override: Optional[Tuple[int, int]] = None,\n # 1 = fp16 MMA (default): MmaF16BF16Op uses Float16. Dequant writes\n # fp16 directly to tCrB (skipping the f16->f32->bf16 cvt chain\n # the bf16 path needs after hmul2). A is bf16 in SMEM ->\n # ldmatrix into bf16 staging fragment -> in-register packed\n # bf16->fp16 cvt -> fp16 tCrA. Slightly *more* accurate than\n # bf16 MMA for well-behaved inputs since fp16's 10-bit mantissa\n # beats bf16's 7-bit at the multiply step; accumulator stays\n # fp32 in both modes.\n # 0 = bf16 MMA: original path. Safer for workloads with very\n # large activation magnitudes (|A| > ~30000) since bf16's\n # wider exponent range avoids saturation in the A cvt.\n use_fp16_mma: int = 1,\n enable_pdl: bool = True,\n tile_swizzle: int = 1,\n raster_along_m: bool = True,\n ):\n \"\"\"bf16 x fp4 kernel.\n\n Args:\n acc_dtype: accumulator dtype (always Float32 for this kernel).\n tile_shape_mnk: CTA tile shape.\n epi_stage: TMA-store pipeline depth. Default 4 balances\n cross-tile overlap (epi_stage > 1 lets next-tile compute\n overlap with this-tile store) against SMEM available for\n ab_stage (deeper ab_stage hides TMA-load latency, which\n dominates the small-M shape's stalls). At M=4 with the\n default 64-CTA grid on 148 SMs, each SM gets at most\n one tile, so epi_stage > 1 doesn't help much locally;\n we keep 2-4 to preserve persistent-scheduler benefits\n at larger M.\n \"\"\"\n self.acc_dtype = acc_dtype\n self.cluster_shape_mnk = (1, 1, 1)\n self.tile_shape_mnk = tuple(tile_shape_mnk)\n self.epi_stage_target = int(epi_stage)\n if self.epi_stage_target < 1:\n raise ValueError(f\"epi_stage must be >= 1 (got {epi_stage})\")\n self.pipeline_depth = int(pipeline_depth)\n self.use_fp16_mma = int(use_fp16_mma)\n self.tile_swizzle = int(tile_swizzle)\n self.raster_along_m = bool(raster_along_m)\n self.enable_pdl = bool(enable_pdl)\n # Optional override for the epilogue tile shape.\n self.epi_tile_override = (\n tuple(epi_tile_override) if epi_tile_override is not None else None\n )\n self.tiled_mma = None\n # num_mcast_ctas_a / num_mcast_ctas_b are derived from the cluster\n # shape in __call__ before use; left unset here so their type is\n # inferred from that assignment (matches the sibling kernels).\n self.is_a_mcast = False\n self.is_b_mcast = False\n\n if self.tile_shape_mnk[1] % _PACK_TILE_N != 0:\n raise ValueError(\n f\"bf16 x fp4 requires tile_N % {_PACK_TILE_N} == 0 \"\n f\"(got tile_N={self.tile_shape_mnk[1]})\"\n )\n if self.tile_shape_mnk[2] % _PACK_TILE_K != 0:\n raise ValueError(\n f\"bf16 x fp4 requires tile_K % {_PACK_TILE_K} == 0 \"\n f\"(got tile_K={self.tile_shape_mnk[2]})\"\n )\n\n self.occupancy = 1\n # 2x2 atom layout: 4 MMA warps arranged as 2 M-warps x 2 N-warps.\n self.atom_layout = tuple(atom_layout)\n if self.atom_layout not in ((2, 2, 1), (1, 2, 1)):\n raise ValueError(\n f\"Unsupported atom_layout {self.atom_layout!r}; \"\n \"expected (2,2,1) or (1,2,1)\"\n )\n self.num_mma_warps = (\n self.atom_layout[0] * self.atom_layout[1] * self.atom_layout[2]\n )\n self.num_dma_warps = 1\n self.num_threads_per_warp = 32\n self.threads_per_cta = (\n self.num_mma_warps + self.num_dma_warps\n ) * self.num_threads_per_warp\n # SM100/103 expose >= SM120 SMEM/CTA\n self.smem_capacity = utils.get_smem_capacity_in_bytes(\"sm_120\")\n\n self.ab_stage = None\n self.epi_stage = None\n\n self.a_smem_layout_staged = None\n self.b_smem_layout_staged = None\n self.epi_smem_layout_staged = None\n self.buffer_align_bytes = 1024\n\n self.epilog_sync_barrier = pipeline.NamedBarrier(\n barrier_id=2,\n num_threads=self.num_mma_warps * self.num_threads_per_warp,\n )\n self.load_register_requirement = 40\n self.mma_register_requirement = 232\n\n def _setup_attributes(self):\n self.mma_inst_mnk = (16, 8, 16)\n # MmaF16BF16Op accepts ab_dtype in {Float16, BFloat16}. We pick via\n # b_compute_dtype so use_fp16_mma=1 swings the whole MMA to fp16\n # (both A and B fragments will be fp16-typed).\n op = cute.nvgpu.warp.MmaF16BF16Op(\n self.b_compute_dtype,\n self.acc_dtype,\n self.mma_inst_mnk,\n )\n tC = cute.make_layout(self.atom_layout)\n permutation_mnk = (\n self.atom_layout[0] * self.mma_inst_mnk[0],\n # *2 trick: each warp covers two atom-N tiles in one ldmatrix.x4\n self.atom_layout[1] * self.mma_inst_mnk[1] * 2,\n self.atom_layout[2] * self.mma_inst_mnk[2],\n )\n self.tiled_mma = cute.make_tiled_mma(\n op,\n tC,\n permutation_mnk=permutation_mnk,\n )\n\n self.cta_layout_mnk = cute.make_layout(self.cluster_shape_mnk)\n\n self.num_mcast_ctas_a = self.cluster_shape_mnk[1]\n self.num_mcast_ctas_b = self.cluster_shape_mnk[0]\n self.is_a_mcast = self.num_mcast_ctas_a > 1\n self.is_b_mcast = self.num_mcast_ctas_b > 1\n\n self.epi_tile = sm90_utils.compute_tile_shape_or_override(\n self.tile_shape_mnk,\n self.c_dtype,\n is_cooperative=False,\n epi_tile_override=self.epi_tile_override,\n )\n\n # B-side smem is packed int32 (4 bytes per logical FP4\n # pair). Stage budget uses int32 B + uint8 scales; bf16 phantom\n # layout is only used by partition_B/make_fragment_B.\n self.ab_stage, self.epi_stage = self._compute_stages(\n self.tile_shape_mnk,\n self.a_dtype,\n self.epi_tile,\n self.c_dtype,\n self.smem_capacity,\n self.occupancy,\n self.GROUP_SIZE,\n self.epi_stage_target,\n )\n\n if self.ab_stage == 0:\n raise RuntimeError(\n \"ab_stage == 0: not enough shared memory for this tile shape \"\n f\"({self.tile_shape_mnk}) at occupancy {self.occupancy}.\"\n )\n\n (\n self.a_smem_layout_staged,\n self.b_packed_smem_layout_staged,\n self.b_sf_smem_layout_staged,\n self.b_bf16_logical_layout,\n self.epi_smem_layout_staged,\n ) = self._make_smem_layouts(\n self.tile_shape_mnk,\n self.epi_tile,\n self.a_dtype,\n self.a_layout,\n self.b_compute_dtype,\n self.b_layout_compute,\n self.ab_stage,\n self.c_dtype,\n self.c_layout,\n self.epi_stage,\n self.GROUP_SIZE,\n )\n\n @cute.jit\n def __call__(\n self,\n a: cute.Tensor,\n b_packed: cute.Tensor,\n b_sf: cute.Tensor,\n c: cute.Tensor,\n alpha: cute.Tensor,\n max_active_clusters: cutlass.Constexpr,\n stream: cuda.CUstream,\n ):\n from cutlass import Float16\n\n self.a_dtype = a.element_type\n # MMA operand dtype: bf16 by default matches A, or fp16 when\n # use_fp16_mma=1 (lets us skip the f16->f32->bf16 cvt chain on B).\n if cutlass.const_expr(self.use_fp16_mma == 1):\n self.b_compute_dtype = Float16\n else:\n self.b_compute_dtype = a.element_type\n self.c_dtype = c.element_type\n\n self.a_layout = utils.LayoutEnum.from_tensor(a)\n self.b_layout_compute = utils.LayoutEnum.ROW_MAJOR\n self.c_layout = utils.LayoutEnum.from_tensor(c)\n\n if cutlass.const_expr(self.a_dtype.width != 16):\n raise TypeError(f\"a_dtype must be 16-bit (bf16/fp16), got {self.a_dtype}\")\n if cutlass.const_expr(self.a_dtype != self.c_dtype):\n raise TypeError(\n f\"a_dtype and c_dtype must match, got {self.a_dtype} vs {self.c_dtype}\"\n )\n\n self._setup_attributes()\n\n tma_atom_a, tma_tensor_a = self._make_tma_atoms_and_tensors(\n a,\n self.a_smem_layout_staged,\n (self.tile_shape_mnk[0], self.tile_shape_mnk[2]),\n 1,\n )\n\n # Packed B TMA: tile is (tile_K // 16, 2 * tile_N) int32.\n b_packed_tma_tile = (\n self.tile_shape_mnk[2] // _PACK_TILE_K,\n 2 * self.tile_shape_mnk[1],\n )\n tma_atom_b_packed, tma_tensor_b_packed = self._make_tma_atoms_and_tensors(\n b_packed,\n self.b_packed_smem_layout_staged,\n b_packed_tma_tile,\n 1,\n )\n\n # B scale TMA: tile is (tile_K // group_size, tile_N) uint8.\n # Small per-tile load -- this replaces ``tile_K // group_size``\n # gmem-direct loads per thread per K-block in the dequant path.\n b_sf_tma_tile = (\n self.tile_shape_mnk[2] // self.GROUP_SIZE,\n self.tile_shape_mnk[1],\n )\n tma_atom_b_sf, tma_tensor_b_sf = self._make_tma_atoms_and_tensors(\n b_sf,\n self.b_sf_smem_layout_staged,\n b_sf_tma_tile,\n 1,\n )\n\n tma_atom_c, tma_tensor_c = self._make_tma_store_atoms_and_tensors(\n c,\n self.epi_smem_layout_staged,\n self.epi_tile,\n )\n\n tile_sched_params, grid = self._compute_grid(\n c,\n self.tile_shape_mnk,\n max_active_clusters,\n self.tile_swizzle,\n self.raster_along_m,\n )\n\n @cute.struct\n class SharedStorage:\n mainloop_pipeline_array_ptr: cute.struct.MemRange[\n cutlass.Int64, self.ab_stage * 2\n ]\n sA: cute.struct.Align[\n cute.struct.MemRange[\n self.a_dtype, cute.cosize(self.a_smem_layout_staged)\n ],\n self.buffer_align_bytes,\n ]\n sB_packed: cute.struct.Align[\n cute.struct.MemRange[\n cutlass.Int32, cute.cosize(self.b_packed_smem_layout_staged)\n ],\n self.buffer_align_bytes,\n ]\n sB_sf: cute.struct.Align[\n cute.struct.MemRange[\n cutlass.Uint8, cute.cosize(self.b_sf_smem_layout_staged)\n ],\n self.buffer_align_bytes,\n ]\n sC: cute.struct.Align[\n cute.struct.MemRange[\n self.c_dtype, cute.cosize(self.epi_smem_layout_staged)\n ],\n self.buffer_align_bytes,\n ]\n\n self.shared_storage = SharedStorage\n\n self.kernel(\n tma_atom_a,\n tma_tensor_a,\n tma_atom_b_packed,\n tma_tensor_b_packed,\n tma_atom_b_sf,\n tma_tensor_b_sf,\n tma_atom_c,\n tma_tensor_c,\n alpha,\n self.tiled_mma,\n self.cta_layout_mnk,\n self.a_smem_layout_staged,\n self.b_packed_smem_layout_staged,\n self.b_sf_smem_layout_staged,\n self.b_bf16_logical_layout,\n self.epi_smem_layout_staged,\n tile_sched_params,\n ).launch(\n grid=grid,\n block=[self.threads_per_cta, 1, 1],\n cluster=[1, 1, 1],\n stream=stream,\n use_pdl=self.enable_pdl,\n )\n return\n\n @cute.kernel\n def kernel(\n self,\n tma_atom_a: cute.CopyAtom,\n mA_mkl: cute.Tensor,\n tma_atom_b_packed: cute.CopyAtom,\n mB_packed_kn: cute.Tensor,\n tma_atom_b_sf: cute.CopyAtom,\n mB_sf_kn: cute.Tensor,\n tma_atom_c: cute.CopyAtom,\n mC_mnl: cute.Tensor,\n mAlpha: cute.Tensor,\n tiled_mma: cute.TiledMma,\n cta_layout_mnk: cute.Layout,\n a_smem_layout_staged: cute.ComposedLayout,\n b_packed_smem_layout_staged: cute.Layout,\n b_sf_smem_layout_staged: cute.Layout,\n b_bf16_logical_layout: cute.ComposedLayout,\n epi_smem_layout_staged: cute.ComposedLayout,\n tile_sched_params: utils.PersistentTileSchedulerParams,\n ):\n tidx, _, _ = cute.arch.thread_idx()\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n\n # Prefetch TMA descriptors from warp 0.\n if warp_idx == 0:\n cute.nvgpu.cpasync.prefetch_descriptor(tma_atom_a)\n cute.nvgpu.cpasync.prefetch_descriptor(tma_atom_b_packed)\n cute.nvgpu.cpasync.prefetch_descriptor(tma_atom_b_sf)\n cute.nvgpu.cpasync.prefetch_descriptor(tma_atom_c)\n\n cta_rank_in_cluster = cute.arch.make_warp_uniform(\n cute.arch.block_idx_in_cluster()\n )\n cluster_coord_mnk = cta_layout_mnk.get_flat_coord(cta_rank_in_cluster)\n\n a_mcast_mask = cute.make_layout_image_mask(\n cta_layout_mnk, cluster_coord_mnk, mode=1\n )\n b_mcast_mask = cute.make_layout_image_mask(\n cta_layout_mnk, cluster_coord_mnk, mode=0\n )\n a_mcast_mask = a_mcast_mask if self.is_a_mcast else 0\n b_mcast_mask = b_mcast_mask if self.is_b_mcast else 0\n\n a_smem_layout = cute.slice_(a_smem_layout_staged, (None, None, 0))\n b_packed_smem_layout = cute.slice_(b_packed_smem_layout_staged, (None, None, 0))\n b_sf_smem_layout = cute.slice_(b_sf_smem_layout_staged, (None, None, 0))\n tma_copy_bytes = (\n cute.size_in_bytes(self.a_dtype, a_smem_layout)\n + cute.size_in_bytes(cutlass.Int32, b_packed_smem_layout)\n + cute.size_in_bytes(cutlass.Uint8, b_sf_smem_layout)\n )\n\n smem = cutlass.utils.SmemAllocator()\n storage = smem.allocate(self.shared_storage)\n\n mainloop_pipeline_array_ptr = storage.mainloop_pipeline_array_ptr.data_ptr()\n\n mainloop_pipeline_producer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread\n )\n mcast_size = self.num_mcast_ctas_a + self.num_mcast_ctas_b - 1\n consumer_arrive_cnt = mcast_size * self.num_mma_warps\n mainloop_pipeline_consumer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread, consumer_arrive_cnt\n )\n\n cta_layout_vmnk = cute.make_layout((1, *cta_layout_mnk.shape))\n mainloop_pipeline = pipeline.PipelineTmaAsync.create(\n num_stages=self.ab_stage,\n producer_group=mainloop_pipeline_producer_group,\n consumer_group=mainloop_pipeline_consumer_group,\n tx_count=tma_copy_bytes,\n barrier_storage=mainloop_pipeline_array_ptr,\n cta_layout_vmnk=cta_layout_vmnk,\n )\n\n if cute.size(self.cluster_shape_mnk) > 1:\n cute.arch.cluster_arrive_relaxed()\n\n sA = storage.sA.get_tensor(\n a_smem_layout_staged.outer, swizzle=a_smem_layout_staged.inner\n )\n # Both B-side tensors are plain (non-swizzled) staged layouts.\n sB_packed = storage.sB_packed.get_tensor(b_packed_smem_layout_staged)\n sB_sf = storage.sB_sf.get_tensor(b_sf_smem_layout_staged)\n sC = storage.sC.get_tensor(\n epi_smem_layout_staged.outer, swizzle=epi_smem_layout_staged.inner\n )\n\n gA_mkl = cute.local_tile(\n mA_mkl,\n cute.slice_(self.tile_shape_mnk, (None, 0, None)),\n (None, None, None),\n )\n # Packed B: (K // 16, N * 2, L); tile = (tile_K // 16, 2 * tile_N).\n b_packed_tile_shape = (\n self.tile_shape_mnk[2] // _PACK_TILE_K,\n 2 * self.tile_shape_mnk[1],\n )\n gB_packed_kn = cute.local_tile(\n mB_packed_kn,\n b_packed_tile_shape,\n (None, None, None),\n )\n # Scales: (K // 16, N, L); per-tile slice has shape\n # (tile_K // group_size, tile_N) = (tile_K // 16, tile_N). Dequant\n # indexes directly per K-block + per N-coord.\n gB_sf_kn = cute.local_tile(\n mB_sf_kn,\n (self.tile_shape_mnk[2] // self.GROUP_SIZE, self.tile_shape_mnk[1]),\n (None, None, None),\n )\n gC_mnl = cute.local_tile(\n mC_mnl,\n cute.slice_(self.tile_shape_mnk, (None, None, 0)),\n (None, None, None),\n )\n\n thr_mma = tiled_mma.get_slice(tidx)\n\n # TMA partition for A: (m, k) -> per-CTA partition.\n a_cta_layout = cute.make_layout(cute.slice_(cta_layout_mnk, (0, None, 0)).shape)\n a_cta_crd = cluster_coord_mnk[1]\n tAsA, tAgA = cute.nvgpu.cpasync.tma_partition(\n tma_atom_a,\n a_cta_crd,\n a_cta_layout,\n cute.group_modes(sA, 0, 2),\n cute.group_modes(gA_mkl, 0, 2),\n )\n\n # TMA partition for B (packed int32).\n b_cta_layout = cute.make_layout(cute.slice_(cta_layout_mnk, (None, 0, 0)).shape)\n b_cta_crd = cluster_coord_mnk[0]\n tBpacked_s, tBpacked_g = cute.nvgpu.cpasync.tma_partition(\n tma_atom_b_packed,\n b_cta_crd,\n b_cta_layout,\n cute.group_modes(sB_packed, 0, 2),\n cute.group_modes(gB_packed_kn, 0, 2),\n )\n\n # TMA partition for B_sf (uint8 scales). Shares the b_cta_crd\n # (no N multicast since cluster_shape_mnk = (1,1,1)).\n tBsf_s, tBsf_g = cute.nvgpu.cpasync.tma_partition(\n tma_atom_b_sf,\n b_cta_crd,\n b_cta_layout,\n cute.group_modes(sB_sf, 0, 2),\n cute.group_modes(gB_sf_kn, 0, 2),\n )\n\n # B partition uses a phantom bf16 layout on top of the sB_packed\n # int32 storage (recast pointer + bf16 logical layout). This\n # gives ``partition_B``/``make_fragment_B`` the right fragment\n # shape; the data is never read through this view -- we always\n # decode FP4 ourselves.\n sB_phantom = cute.make_tensor(\n cute.recast_ptr(sB_packed.iterator, dtype=self.b_compute_dtype),\n b_bf16_logical_layout,\n )\n tCsA = thr_mma.partition_A(sA)\n tCsB_phantom = thr_mma.partition_B(sB_phantom)\n tCrA = tiled_mma.make_fragment_A(tCsA[None, None, None, 0])\n tCrB = tiled_mma.make_fragment_B(tCsB_phantom[None, None, None, 0])\n\n tCgC = thr_mma.partition_C(gC_mnl)\n acc_shape = tCgC.shape[:3]\n accumulators = cute.make_rmem_tensor(acc_shape, self.acc_dtype)\n\n if cute.size(self.cluster_shape_mnk) > 1:\n cute.arch.cluster_wait()\n else:\n pipeline.sync(barrier_id=1)\n\n # PDL bookend (start): wait for the prior grid to finish so this\n # kernel's TMA loads see the producer kernel's writes.\n cute.arch.griddepcontrol_wait()\n\n k_tile_cnt = cute.size(gA_mkl, mode=[3])\n\n tile_sched = utils.StaticPersistentTileScheduler.create(\n tile_sched_params, cute.arch.block_idx(), cute.arch.grid_dim()\n )\n work_tile = tile_sched.initial_work_tile_info()\n\n mainloop_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.ab_stage\n )\n mainloop_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.ab_stage\n )\n\n # MMA warp group: warps [0, num_mma_warps) compute.\n if warp_idx < self.num_mma_warps:\n cute.arch.setmaxregister_increase(self.mma_register_requirement)\n\n num_k_blocks = cute.size(tCrA, mode=[2])\n\n # ldmatrix is only for A. B is filled in-register from sB_packed\n # via FP4 decode + per-group scale.\n #\n # use_fp16_mma=1: tCrA is fp16-typed (matches the fp16 MMA), but\n # sA is bf16 in SMEM. ldmatrix into a bf16 staging fragment,\n # then per-K-block convert bf16 -> fp16 in-register before MMA\n # reads tCrA. See the inline cvt at each ldmatrix site.\n from cutlass import BFloat16\n\n atom_copy_ldmatrix_A = cute.make_copy_atom(\n cute.nvgpu.warp.LdMatrix8x8x16bOp(self.a_layout.is_m_major_a(), 4),\n self.a_dtype,\n )\n smem_tiled_copy_A = cute.make_tiled_copy_A(atom_copy_ldmatrix_A, tiled_mma)\n thr_copy_ldmatrix_A = smem_tiled_copy_A.get_slice(tidx)\n tCsA_copy_view = thr_copy_ldmatrix_A.partition_S(sA)\n if cutlass.const_expr(self.use_fp16_mma == 1):\n tCrA_bf16 = cute.make_fragment_like(tCrA, BFloat16)\n tCrA_copy_view = thr_copy_ldmatrix_A.retile(tCrA_bf16)\n else:\n tCrA_bf16 = tCrA\n tCrA_copy_view = thr_copy_ldmatrix_A.retile(tCrA)\n\n alpha_val = Float32(mAlpha[Int32(0)])\n\n while work_tile.is_valid_tile:\n tile_coord_mnl = work_tile.tile_idx\n gC_mnl_slice = gC_mnl[(None, None, *tile_coord_mnl)]\n accumulators.fill(0.0)\n\n mainloop_consumer_state.reset_count()\n\n peek_ab_full_status = cutlass.Boolean(1)\n if mainloop_consumer_state.count < k_tile_cnt:\n peek_ab_full_status = mainloop_pipeline.consumer_try_wait(\n mainloop_consumer_state\n )\n\n mainloop_pipeline.consumer_wait(\n mainloop_consumer_state, peek_ab_full_status\n )\n tCsA_p = tCsA_copy_view[None, None, None, mainloop_consumer_state.index]\n\n # Prologue: prefetch tCrA[0] and tCrB[0] only when running with\n # pipeline_depth >= 1. With depth=0 the dequant for block k\n # happens inside the same iteration as gemm(k) -- no prefetch.\n if cutlass.const_expr(self.pipeline_depth >= 1):\n cute.copy(\n smem_tiled_copy_A,\n tCsA_p[None, None, 0],\n tCrA_copy_view[None, None, 0],\n )\n if cutlass.const_expr(self.use_fp16_mma == 1):\n self._cvt_a_bf16_to_fp16_one_k_block(tCrA, tCrA_bf16, 0)\n self._dequant_b_to_register(\n sB_packed,\n sB_sf,\n tCrB,\n tidx,\n mainloop_consumer_state.index,\n mainloop_consumer_state.count,\n 0,\n )\n\n for _k_tile in cutlass.range(0, k_tile_cnt - 1, 1, unroll=1):\n for k_block_idx in cutlass.range_constexpr(num_k_blocks):\n k_block_next = (\n 0 if k_block_idx + 1 == num_k_blocks else k_block_idx + 1\n )\n\n if cutlass.const_expr(self.pipeline_depth == 0):\n # No-prefetch: dequant(k) just before gemm(k),\n # all on the CURRENT K-tile's stage. Release +\n # advance + wait happens AFTER gemm of the last\n # block so we don't drop SMEM under our own read.\n cute.copy(\n smem_tiled_copy_A,\n tCsA_p[None, None, k_block_idx],\n tCrA_copy_view[None, None, k_block_idx],\n )\n if cutlass.const_expr(self.use_fp16_mma == 1):\n self._cvt_a_bf16_to_fp16_one_k_block(\n tCrA, tCrA_bf16, k_block_idx\n )\n self._dequant_b_to_register(\n sB_packed,\n sB_sf,\n tCrB,\n tidx,\n mainloop_consumer_state.index,\n mainloop_consumer_state.count,\n k_block_idx,\n )\n cute.gemm(\n tiled_mma,\n accumulators,\n tCrA[None, None, k_block_idx],\n tCrB[None, None, k_block_idx],\n accumulators,\n )\n if k_block_idx == num_k_blocks - 1:\n mainloop_pipeline.consumer_release(\n mainloop_consumer_state\n )\n mainloop_consumer_state.advance()\n peek_ab_full_status = cutlass.Boolean(1)\n peek_ab_full_status = (\n mainloop_pipeline.consumer_try_wait(\n mainloop_consumer_state\n )\n )\n tCsA_p = tCsA_copy_view[\n None, None, None, mainloop_consumer_state.index\n ]\n mainloop_pipeline.consumer_wait(\n mainloop_consumer_state, peek_ab_full_status\n )\n else:\n # 1-stage prefetch: dequant(k+1) while gemm(k).\n if k_block_idx == num_k_blocks - 1:\n mainloop_pipeline.consumer_release(\n mainloop_consumer_state\n )\n mainloop_consumer_state.advance()\n\n peek_ab_full_status = cutlass.Boolean(1)\n peek_ab_full_status = (\n mainloop_pipeline.consumer_try_wait(\n mainloop_consumer_state\n )\n )\n\n tCsA_p = tCsA_copy_view[\n None, None, None, mainloop_consumer_state.index\n ]\n mainloop_pipeline.consumer_wait(\n mainloop_consumer_state, peek_ab_full_status\n )\n\n cute.copy(\n smem_tiled_copy_A,\n tCsA_p[None, None, k_block_next],\n tCrA_copy_view[None, None, k_block_next],\n )\n if cutlass.const_expr(self.use_fp16_mma == 1):\n self._cvt_a_bf16_to_fp16_one_k_block(\n tCrA, tCrA_bf16, k_block_next\n )\n self._dequant_b_to_register(\n sB_packed,\n sB_sf,\n tCrB,\n tidx,\n mainloop_consumer_state.index,\n mainloop_consumer_state.count,\n k_block_next,\n )\n cute.gemm(\n tiled_mma,\n accumulators,\n tCrA[None, None, k_block_idx],\n tCrB[None, None, k_block_idx],\n accumulators,\n )\n # Hoist out last k_tile (no further loads after the last k_block)\n for k_block_idx in cutlass.range_constexpr(num_k_blocks):\n k_block_next = (\n 0 if k_block_idx + 1 == num_k_blocks else k_block_idx + 1\n )\n\n if cutlass.const_expr(self.pipeline_depth == 0):\n # No-prefetch path for last K-tile. Release happens\n # AFTER gemm of the last block (kernel exits then).\n cute.copy(\n smem_tiled_copy_A,\n tCsA_p[None, None, k_block_idx],\n tCrA_copy_view[None, None, k_block_idx],\n )\n if cutlass.const_expr(self.use_fp16_mma == 1):\n self._cvt_a_bf16_to_fp16_one_k_block(\n tCrA, tCrA_bf16, k_block_idx\n )\n self._dequant_b_to_register(\n sB_packed,\n sB_sf,\n tCrB,\n tidx,\n mainloop_consumer_state.index,\n mainloop_consumer_state.count,\n k_block_idx,\n )\n cute.gemm(\n tiled_mma,\n accumulators,\n tCrA[None, None, k_block_idx],\n tCrB[None, None, k_block_idx],\n accumulators,\n )\n if k_block_idx == num_k_blocks - 1:\n mainloop_pipeline.consumer_release(mainloop_consumer_state)\n mainloop_consumer_state.advance()\n else:\n # 1-stage prefetch path for last K-tile.\n if k_block_idx == num_k_blocks - 1:\n mainloop_pipeline.consumer_release(mainloop_consumer_state)\n mainloop_consumer_state.advance()\n\n if k_block_next > 0:\n cute.copy(\n smem_tiled_copy_A,\n tCsA_p[None, None, k_block_next],\n tCrA_copy_view[None, None, k_block_next],\n )\n if cutlass.const_expr(self.use_fp16_mma == 1):\n self._cvt_a_bf16_to_fp16_one_k_block(\n tCrA, tCrA_bf16, k_block_next\n )\n self._dequant_b_to_register(\n sB_packed,\n sB_sf,\n tCrB,\n tidx,\n mainloop_consumer_state.index,\n mainloop_consumer_state.count,\n k_block_next,\n )\n cute.gemm(\n tiled_mma,\n accumulators,\n tCrA[None, None, k_block_idx],\n tCrB[None, None, k_block_idx],\n accumulators,\n )\n\n # Epilogue: accumulator -> smem -> gmem via R2S (StMatrix.x4)\n # + TMA bulk store.\n copy_atom_r2s = sm90_utils.sm90_get_smem_store_op(\n self.c_layout,\n elem_ty_d=self.c_dtype,\n elem_ty_acc=self.acc_dtype,\n )\n\n copy_atom_C = cute.make_copy_atom(\n cute.nvgpu.warp.StMatrix8x8x16bOp(\n self.c_layout.is_m_major_c(),\n 4,\n ),\n self.c_dtype,\n )\n\n tiled_copy_C_Atom = cute.make_tiled_copy_C_atom(copy_atom_C, tiled_mma)\n\n tiled_copy_r2s = cute.make_tiled_copy_S(\n copy_atom_r2s,\n tiled_copy_C_Atom,\n )\n\n thr_copy_r2s = tiled_copy_r2s.get_slice(tidx)\n tRS_sD = thr_copy_r2s.partition_D(sC)\n tRS_rAcc = tiled_copy_r2s.retile(accumulators)\n\n rD_shape = cute.shape(thr_copy_r2s.partition_S(sC))\n tRS_rD_layout = cute.make_layout(rD_shape[:3])\n tRS_rD = cute.make_rmem_tensor(tRS_rD_layout.shape, self.acc_dtype)\n\n sepi_for_tma_partition = cute.group_modes(sC, 0, 2)\n tcgc_for_tma_partition = cute.zipped_divide(gC_mnl_slice, self.epi_tile)\n\n bSG_sD, bSG_gD = cute.nvgpu.cpasync.tma_partition(\n tma_atom_c,\n 0,\n cute.make_layout(1),\n sepi_for_tma_partition,\n tcgc_for_tma_partition,\n )\n\n # Epilogue: iterate (epi_m, epi_n) explicitly\n # and use (mma_m, mma_n) mode indexing into tRS_rAcc so\n # the loop works for any epi_tile_m / epi_tile_n. Also\n # supports OOB-iteration skipping when m_actual < tile_M.\n epi_rest_m = cute.size(tcgc_for_tma_partition, mode=[1, 0])\n epi_rest_n = cute.size(tcgc_for_tma_partition, mode=[1, 1])\n epi_tile_m = self.epi_tile[0]\n epi_tile_n = self.epi_tile[1]\n # mma_tile_{m,n} = per-mma-atom (M,N) size. tRS_rAcc has\n # shape (atom_v, mma_m, mma_n); modes 1, 2 give the atom\n # counts in M, N.\n mma_tile_m = self.tile_shape_mnk[0] // cute.size(tRS_rAcc, mode=[1])\n mma_tile_n = self.tile_shape_mnk[1] // cute.size(tRS_rAcc, mode=[2])\n MmaMPerEpiM = epi_tile_m // mma_tile_m\n MmaNPerEpiN = epi_tile_n // mma_tile_n\n\n tma_store_producer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n self.num_mma_warps * self.num_threads_per_warp,\n )\n tma_store_pipeline = pipeline.PipelineTmaStore.create(\n num_stages=self.epi_stage,\n producer_group=tma_store_producer_group,\n )\n\n # Skip OOB epilogue iterations when actual M < tile_M.\n m_actual = cute.size(mC_mnl, mode=[0])\n cta_m_offset = tile_coord_mnl[0] * Int32(self.tile_shape_mnk[0])\n\n # kept_count cycles in lockstep with the TMA-store pipeline.\n # epi_buffer = kept_count % num_stages stays in sync with\n # producer_commit/acquire calls, regardless of how many\n # iterations are skipped.\n kept_count = 0\n for epi_n in cutlass.range_constexpr(epi_rest_n):\n for epi_m in cutlass.range_constexpr(epi_rest_m):\n epi_m_global_start = cta_m_offset + Int32(epi_m * epi_tile_m)\n if epi_m_global_start < m_actual:\n # Copy this epi-tile's slice of acc -> tRS_rD\n # using b12x-style (mma_m, mma_n) indexing.\n for mma_n_in_epi in cutlass.range_constexpr(MmaNPerEpiN):\n for mma_m_in_epi in cutlass.range_constexpr(\n MmaMPerEpiM\n ):\n mma_n = epi_n * MmaNPerEpiN + mma_n_in_epi\n mma_m = epi_m * MmaMPerEpiM + mma_m_in_epi\n tRS_rD_slice = tRS_rD[\n (None, mma_m_in_epi, mma_n_in_epi)\n ]\n tRS_rAcc_slice = tRS_rAcc[(None, mma_m, mma_n)]\n for elem_idx in cutlass.range_constexpr(\n cute.size(tRS_rD_slice)\n ):\n tRS_rD_slice[elem_idx] = tRS_rAcc_slice[\n elem_idx\n ]\n\n tRS_rD_out = cute.make_rmem_tensor(\n tRS_rD_layout.shape, self.c_dtype\n )\n # Apply the global alpha here, once, on the\n # fp32 accumulator (hoisted out of the\n # per-K-block dequant): one rounding instead\n # of folding alpha into every B scale.\n acc_vec = tRS_rD.load()\n tRS_rD_out.store((alpha_val * acc_vec).to(self.c_dtype))\n\n epi_buffer = kept_count % cute.size(tRS_sD, mode=[3])\n cute.copy(\n tiled_copy_r2s,\n tRS_rD_out,\n tRS_sD[(None, None, None, epi_buffer)],\n )\n cute.arch.fence_proxy(\"async.shared\", space=\"cta\")\n self.epilog_sync_barrier.arrive_and_wait()\n\n if warp_idx == 0:\n cute.copy(\n tma_atom_c,\n bSG_sD[(None, epi_buffer)],\n bSG_gD[(None, (epi_m, epi_n))],\n )\n tma_store_pipeline.producer_commit()\n tma_store_pipeline.producer_acquire()\n kept_count = kept_count + 1\n\n tma_store_pipeline.producer_tail()\n\n tile_sched.advance_to_next_work()\n work_tile = tile_sched.get_current_work()\n # Single DMA warp: issues all 3 TMA descriptors (A, B_packed, B_sf)\n # back-to-back into the same stage barrier per K-tile.\n elif warp_idx == self.num_mma_warps:\n cute.arch.setmaxregister_decrease(self.load_register_requirement)\n while work_tile.is_valid_tile:\n tile_coord_mnl = work_tile.tile_idx\n tAgA_mkl = tAgA[(None, tile_coord_mnl[0], None, tile_coord_mnl[2])]\n tBpacked_g_kn = tBpacked_g[\n (None, None, tile_coord_mnl[1], tile_coord_mnl[2])\n ]\n tBsf_g_kn = tBsf_g[(None, None, tile_coord_mnl[1], tile_coord_mnl[2])]\n mainloop_producer_state.reset_count()\n for _k_tile in cutlass.range(0, k_tile_cnt, 1, unroll=1):\n mainloop_pipeline.producer_acquire(mainloop_producer_state)\n barrier_ptr = mainloop_pipeline.producer_get_barrier(\n mainloop_producer_state\n )\n\n tAgA_k = tAgA_mkl[(None, mainloop_producer_state.count)]\n tAsA_pipe = tAsA[(None, mainloop_producer_state.index)]\n cute.copy(\n tma_atom_a,\n tAgA_k,\n tAsA_pipe,\n tma_bar_ptr=barrier_ptr,\n mcast_mask=a_mcast_mask,\n )\n\n tBpacked_g_k = tBpacked_g_kn[(None, mainloop_producer_state.count)]\n tBpacked_s_pipe = tBpacked_s[(None, mainloop_producer_state.index)]\n cute.copy(\n tma_atom_b_packed,\n tBpacked_g_k,\n tBpacked_s_pipe,\n tma_bar_ptr=barrier_ptr,\n mcast_mask=b_mcast_mask,\n )\n\n tBsf_g_k = tBsf_g_kn[(None, mainloop_producer_state.count)]\n tBsf_s_pipe = tBsf_s[(None, mainloop_producer_state.index)]\n cute.copy(\n tma_atom_b_sf,\n tBsf_g_k,\n tBsf_s_pipe,\n tma_bar_ptr=barrier_ptr,\n mcast_mask=b_mcast_mask,\n )\n\n mainloop_pipeline.producer_commit(mainloop_producer_state)\n mainloop_producer_state.advance()\n tile_sched.advance_to_next_work()\n work_tile = tile_sched.get_current_work()\n mainloop_pipeline.producer_tail(mainloop_producer_state)\n cute.arch.griddepcontrol_launch_dependents()\n return\n\n @staticmethod\n def _compute_stages(\n tile_shape_mnk: Tuple[int, int, int],\n a_dtype: Type[cutlass.Numeric],\n epi_tile: Tuple[int, int],\n c_dtype: Type[cutlass.Numeric],\n smem_capacity: int,\n occupancy: int,\n group_size: int = 16,\n epi_stage: int = 4,\n ) -> Tuple[int, int]:\n \"\"\"Stage budget accounting for A + B (packed int32) + B_sf (uint8).\n\n Per (16K x 64N) packed block: 128 int32 = 512 bytes.\n Per (group_size K x tile_N N) scale block: tile_N bytes.\n \"\"\"\n c_bytes_per_stage = cute.size(epi_tile) * c_dtype.width // 8\n epi_bytes = c_bytes_per_stage * epi_stage\n\n a_shape = cute.slice_(tile_shape_mnk, (None, 0, None))\n a_bytes_per_stage = cute.size(a_shape) * a_dtype.width // 8\n\n # B side: packed int32, 128 int32 per (16K x 64N) block.\n packed_blocks_per_tile = (tile_shape_mnk[2] // _PACK_TILE_K) * (\n tile_shape_mnk[1] // _PACK_TILE_N\n )\n b_packed_bytes_per_stage = packed_blocks_per_tile * _PACK_INTS_PER_TILE * 4\n\n # Scale tile: 1 byte per (K-group, N). Small compared to B_packed.\n b_sf_bytes_per_stage = (tile_shape_mnk[2] // group_size) * tile_shape_mnk[1]\n\n ab_bytes_per_stage = (\n a_bytes_per_stage + b_packed_bytes_per_stage + b_sf_bytes_per_stage\n )\n mbar_helpers_bytes = 1024\n\n ab_stage = (\n (smem_capacity - occupancy * 1024) // occupancy\n - mbar_helpers_bytes\n - epi_bytes\n ) // ab_bytes_per_stage\n return ab_stage, epi_stage\n\n @staticmethod\n def _make_smem_layouts(\n tile_shape_mnk: Tuple[int, int, int],\n epi_tile: Tuple[int, int],\n a_dtype: Type[cutlass.Numeric],\n a_layout: cute.Layout,\n b_compute_dtype: Type[cutlass.Numeric],\n b_layout_compute: cute.Layout,\n ab_stage: int,\n c_dtype: Type[cutlass.Numeric],\n c_layout: cute.Layout,\n epi_stage: int,\n group_size: int,\n ):\n \"\"\"Returns (sA, sB_packed, sB_sf, b_bf16_phantom, sC) layouts.\n\n ``sB_packed_layout`` is a plain (non-swizzled) staged int32 layout\n ``(tile_K // 16, 2 * tile_N, ab_stage)``.\n\n ``sB_sf_layout`` is a plain staged uint8 layout\n ``(tile_K // group_size, tile_N, ab_stage)`` -- one byte per\n (K-group, N) cell. Loaded via TMA once per K-tile, read from\n SMEM in the dequant inner loop (replaces the gmem-direct path).\n\n ``b_bf16_logical_layout`` is the phantom bf16 layout used only by\n ``partition_B`` / ``make_fragment_B`` for fragment-shape\n determination -- there is no real bf16 SMEM allocation.\n \"\"\"\n a_smem_layout_staged = sm90_utils.make_smem_layout_a(\n a_layout,\n tile_shape_mnk,\n a_dtype,\n ab_stage,\n )\n\n # sB_packed: (tile_K // 16) rows x (2 * tile_N) int32 cols x stage.\n b_packed_smem_layout_staged = cute.make_ordered_layout(\n (\n tile_shape_mnk[2] // _PACK_TILE_K,\n 2 * tile_shape_mnk[1],\n ab_stage,\n ),\n order=(1, 0, 2),\n )\n\n # sB_sf: (tile_K // group_size) rows x tile_N uint8 cols x stage.\n # Order (1, 0, 2) -> N innermost (= contiguous load lane), K next,\n # stage outermost. Matches the gmem layout.\n b_sf_smem_layout_staged = cute.make_ordered_layout(\n (\n tile_shape_mnk[2] // group_size,\n tile_shape_mnk[1],\n ab_stage,\n ),\n order=(1, 0, 2),\n )\n\n # bf16 phantom layout for partition_B / make_fragment_B.\n b_bf16_logical_layout = sm90_utils.make_smem_layout_b(\n b_layout_compute,\n tile_shape_mnk,\n b_compute_dtype,\n ab_stage,\n )\n\n epi_smem_layout_staged = sm90_utils.make_smem_layout_epi(\n c_dtype,\n c_layout,\n epi_tile,\n epi_stage,\n )\n return (\n a_smem_layout_staged,\n b_packed_smem_layout_staged,\n b_sf_smem_layout_staged,\n b_bf16_logical_layout,\n epi_smem_layout_staged,\n )\n\n @staticmethod\n def _compute_grid(\n c: cute.Tensor,\n tile_shape_mnk: Tuple[int, int, int],\n max_active_clusters: cutlass.Constexpr,\n tile_swizzle: cutlass.Constexpr = 1,\n raster_along_m: cutlass.Constexpr = True,\n ):\n c_shape = cute.slice_(tile_shape_mnk, (None, None, 0))\n gc = cute.zipped_divide(c, tiler=c_shape)\n num_ctas_mnl = gc[(0, (None, None, None))].shape\n cluster_shape_mnl = (1, 1, 1)\n tile_sched_params = utils.PersistentTileSchedulerParams(\n num_ctas_mnl,\n cluster_shape_mnl,\n swizzle_size=tile_swizzle,\n raster_along_m=raster_along_m,\n )\n grid = utils.StaticPersistentTileScheduler.get_grid_shape(\n tile_sched_params, max_active_clusters\n )\n return tile_sched_params, grid\n\n @staticmethod\n def _make_tma_store_atoms_and_tensors(\n tensor_c: cute.Tensor,\n epi_smem_layout_staged: cute.ComposedLayout,\n epi_tile: Tuple[int, int],\n ) -> Tuple[cute.CopyAtom, cute.Tensor]:\n epi_smem_layout = cute.slice_(epi_smem_layout_staged, (None, None, 0))\n tma_atom_c, tma_tensor_c = cute.nvgpu.cpasync.make_tiled_tma_atom(\n cute.nvgpu.cpasync.CopyBulkTensorTileS2GOp(),\n tensor_c,\n epi_smem_layout,\n epi_tile,\n )\n return tma_atom_c, tma_tensor_c\n\n @staticmethod\n def _make_tma_atoms_and_tensors(\n tensor: cute.Tensor,\n smem_layout_staged: cute.ComposedLayout,\n smem_tile: Tuple[int, int],\n mcast_dim: int,\n ) -> Tuple[cute.CopyAtom, cute.Tensor]:\n op = (\n cute.nvgpu.cpasync.CopyBulkTensorTileG2SOp()\n if mcast_dim == 1\n else cute.nvgpu.cpasync.CopyBulkTensorTileG2SMulticastOp()\n )\n smem_layout = cute.slice_(smem_layout_staged, (None, None, 0))\n tma_atom, tma_tensor = cute.nvgpu.cpasync.make_tiled_tma_atom(\n op,\n tensor,\n smem_layout,\n smem_tile,\n num_multicast=mcast_dim,\n )\n return tma_atom, tma_tensor\n\n @cute.jit\n def _cvt_a_bf16_to_fp16_one_k_block(\n self,\n tCrA_dst,\n tCrA_bf16_src,\n k_block: cutlass.Constexpr,\n ):\n \"\"\"In-register bf16 -> fp16 cvt for one K-block of A.\n\n Recasts both fragments to Uint32 (each u32 packs 2 16-bit elems)\n and applies `cvt_bf16x2_to_f16x2_via_f32` per pair. The packed\n narrowing cvt (`cvt.rn.f16x2.f32`) combines what would be two\n scalar `cvt.rn.f16.f32` instructions if we used cute's default\n `.to(Float16)` lowering.\n\n bf16/f16 typed inline-asm constraints don't compile on sm_100a\n (NVVM rejects them), so we keep everything in Uint32 pair\n representation via cute.recast_tensor.\n \"\"\"\n bf_u32 = cute.recast_tensor(tCrA_bf16_src[None, None, k_block], Uint32)\n fp_u32 = cute.recast_tensor(tCrA_dst[None, None, k_block], Uint32)\n n_pairs = cute.size(bf_u32)\n for i in cutlass.range_constexpr(n_pairs):\n fp_u32[i] = cvt_bf16x2_to_f16x2_via_f32(Uint32(bf_u32[i]))\n\n @cute.jit\n def _dequant_b_to_register(\n self,\n sB_packed: cute.Tensor,\n sB_sf: cute.Tensor,\n tCrB: cute.Tensor,\n tidx: Int32,\n stage_idx: Int32,\n k_tile_idx: Int32,\n k_block_idx: cutlass.Constexpr,\n ):\n \"\"\"Decode 2 int32 per thread per K-block into 16 fp16 fragment slots.\n\n Per the MMA partition for atom_layout (2,2,1) + *2 on N:\n\n tc_row = (lane % 4) * 2 in {0, 2, 4, 6}\n tc_col = lane // 4 in [0, 8)\n n_warp_idx = warp_idx // 2 in {0, 1}\n base_n = n_warp_idx * 8 + tc_col in [0, 16)\n\n Each thread covers:\n K = {tc_row, tc_row+1, tc_row+8, tc_row+9}\n N = {base_n, base_n+16, base_n+32, base_n+48}\n\n Two int32s per K-block per thread; sB_packed offsets:\n u32_0 @ sB_packed[k_block_idx, n_warp_idx * 64 + lane * 2 + 0, stage]\n u32_1 @ sB_packed[k_block_idx, n_warp_idx * 64 + lane * 2 + 1, stage]\n\n Byte layout inside each int32 (see ``_cute_dsl_pack_fp4_weight`` in\n ``flashinfer/gemm/gemm_bf16_fp4_cute_dsl.py``):\n u32_0:\n byte 0: K=tc_row, tc_row+1 at N=base_n -> (mma_i=0,1, nn=0)\n byte 1: K=tc_row+8, tc_row+9 at N=base_n -> (mma_i=2,3, nn=0)\n byte 2: K=tc_row, tc_row+1 at N=base_n+16 -> (mma_i=0,1, nn=1)\n byte 3: K=tc_row+8, tc_row+9 at N=base_n+16 -> (mma_i=2,3, nn=1)\n u32_1 mirrors with N=base_n+32 and N=base_n+48 (nn=2, nn=3).\n \"\"\"\n lane = tidx % Int32(32)\n warp = tidx // Int32(32)\n # n_warp_idx maps warp -> N-stripe. With (2,2,1) the 4 warps are\n # arranged as 2 M-warps * 2 N-warps, so n_warp_idx = warp // 2.\n # With (1,2,1) there are 2 warps total (no M-warp dim), so each\n # warp is its own N-stripe: n_warp_idx = warp. In general\n # n_warp_idx = warp // atom_layout[0].\n n_warp_idx = warp // Int32(self.atom_layout[0])\n tc_col = lane // Int32(4)\n base_n_in_tile = n_warp_idx * Int32(8) + tc_col\n\n # tile_N is built from tile_N // 64 independent packed 64-N blocks.\n # The hand-coded byte->fragment mapping below covers exactly one such\n # 64-N block (4 nn slots); for tile_N=128 we loop it over both blocks.\n # Block n_blk lives at sB_packed int32 columns [n_blk*128, +128), sB_sf\n # N-rows [n_blk*64, +64), and writes tCrB nn in [n_blk*4, +4). For\n # tile_N=64 this loops once.\n num_n_blocks = cutlass.const_expr(self.tile_shape_mnk[1] // 64)\n\n # _write_hmul2 captures tCrB / k_block_idx; nn and mma-row passed per\n # write. fp16 MMA writes fp16 directly; bf16 MMA goes via fp32 (no\n # packed f16x2 -> bf16x2 cvt on sm_100a).\n if cutlass.const_expr(self.use_fp16_mma == 1):\n\n def _write_hmul2(h2, scale_h2, mma_i_low, nn):\n scaled_h2 = half2_mul(h2, scale_h2)\n f_lo, f_hi = f16x2_unpack(scaled_h2)\n tCrB[mma_i_low, nn, k_block_idx] = f_lo\n tCrB[mma_i_low + 1, nn, k_block_idx] = f_hi\n else:\n\n def _write_hmul2(h2, scale_h2, mma_i_low, nn):\n scaled_h2 = half2_mul(h2, scale_h2)\n f_lo, f_hi = f16x2_to_f32x2(scaled_h2)\n tCrB[mma_i_low, nn, k_block_idx] = f_lo.to(self.b_compute_dtype)\n tCrB[mma_i_low + 1, nn, k_block_idx] = f_hi.to(self.b_compute_dtype)\n\n for n_blk in cutlass.range_constexpr(num_n_blocks):\n n_col_off = Int32(n_blk * 128) # int32 column offset of this 64-N block\n n_sf_off = Int32(n_blk * 64) # SF N-row offset of this 64-N block\n nn0 = n_blk * 4 # base tCrB N-fragment slot for this block\n\n # Single ld.shared.v2.u32 (8-byte load): u32_pos_base is always even\n # (= n_blk*128 + n_warp*64 + lane*2), so the offset is 8-byte aligned.\n u32_pos_base = n_col_off + n_warp_idx * Int32(64) + lane * Int32(2)\n smem_addr_b = get_smem_ptr_as_int32(\n sB_packed, sB_packed.layout((k_block_idx, u32_pos_base, stage_idx))\n )\n u32_0, u32_1 = ld_shared_v2_u32(smem_addr_b)\n\n # Per-group scale loads (S0E5M3). 4 distinct N positions per block.\n sf_n = base_n_in_tile + n_sf_off\n sf_byte_0 = Uint32(sB_sf[k_block_idx, sf_n + Int32(0), stage_idx])\n sf_byte_1 = Uint32(sB_sf[k_block_idx, sf_n + Int32(16), stage_idx])\n sf_byte_2 = Uint32(sB_sf[k_block_idx, sf_n + Int32(32), stage_idx])\n sf_byte_3 = Uint32(sB_sf[k_block_idx, sf_n + Int32(48), stage_idx])\n\n h0_a, h0_b, h0_c, h0_d = fp4_decode_4bytes(u32_0)\n h1_a, h1_b, h1_c, h1_d = fp4_decode_4bytes(u32_1)\n\n # S0E5M3 scale -> f16x2 broadcast in one mul.lo.u32. alpha is\n # applied once in the epilogue, so the scale never needs an f32 form.\n sc_n0 = cvt_s0e5m3_to_f16x2_broadcast(sf_byte_0)\n sc_n1 = cvt_s0e5m3_to_f16x2_broadcast(sf_byte_1)\n sc_n2 = cvt_s0e5m3_to_f16x2_broadcast(sf_byte_2)\n sc_n3 = cvt_s0e5m3_to_f16x2_broadcast(sf_byte_3)\n _write_hmul2(h0_a, sc_n0, 0, nn0 + 0)\n _write_hmul2(h0_b, sc_n0, 2, nn0 + 0)\n _write_hmul2(h0_c, sc_n1, 0, nn0 + 1)\n _write_hmul2(h0_d, sc_n1, 2, nn0 + 1)\n _write_hmul2(h1_a, sc_n2, 0, nn0 + 2)\n _write_hmul2(h1_b, sc_n2, 2, nn0 + 2)\n _write_hmul2(h1_c, sc_n3, 0, nn0 + 3)\n _write_hmul2(h1_d, sc_n3, 2, nn0 + 3)\n\n @cute.jit\n def wrapper(\n self,\n mA: cute.Tensor,\n mB_packed: cute.Tensor,\n mB_sf: cute.Tensor,\n mC: cute.Tensor,\n mAlpha: cute.Tensor,\n l: cutlass.Constexpr,\n max_active_clusters: cutlass.Constexpr,\n current_stream,\n ):\n \"\"\"bf16 x fp4 wrapper for the FlashInfer compile interface.\n\n Args:\n mA: (m, k) input tensor A, bf16 or fp16.\n mB_packed: (k // 16, n * 2) int32 -- packed FP4.\n mB_sf: (k // 16, n) uint8 -- FP8-E4M3 per-group scales.\n mC: (m, n) output tensor C, bf16 or fp16.\n mAlpha: (1,) fp32 global scale.\n l: batch dimension (Constexpr); typically 1.\n max_active_clusters: Constexpr from get_max_active_clusters(1).\n current_stream: CUDA stream (TVM-FFI fake stream).\n \"\"\"\n m = cute.size(mA, mode=[0])\n k = cute.size(mA, mode=[1])\n n = cute.size(mC, mode=[1])\n k_tiles = k // _PACK_TILE_K\n n_packed = 2 * n\n k_sf_groups = k // self.GROUP_SIZE\n\n a_tensor = cute.make_tensor(\n mA.iterator,\n layout=cute.make_ordered_layout((m, k, l), order=(1, 0, 2)),\n )\n b_packed_tensor = cute.make_tensor(\n mB_packed.iterator,\n layout=cute.make_ordered_layout((k_tiles, n_packed, l), order=(1, 0, 2)),\n )\n b_sf_tensor = cute.make_tensor(\n mB_sf.iterator,\n layout=cute.make_ordered_layout((k_sf_groups, n, l), order=(1, 0, 2)),\n )\n c_tensor = cute.make_tensor(\n mC.iterator,\n layout=cute.make_ordered_layout((m, n, l), order=(1, 0, 2)),\n )\n\n self(\n a_tensor,\n b_packed_tensor,\n b_sf_tensor,\n c_tensor,\n mAlpha,\n max_active_clusters,\n current_stream,\n )\n"},"after_code":{"kind":"string","value":"# Copyright (c) 2025 - 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.\n# SPDX-License-Identifier: BSD-3-Clause\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions are met:\n#\n# 1. Redistributions of source code must retain the above copyright notice, this\n# list of conditions and the following disclaimer.\n#\n# 2. Redistributions in binary form must reproduce the above copyright notice,\n# this list of conditions and the following disclaimer in the documentation\n# and/or other materials provided with the distribution.\n#\n# 3. Neither the name of the copyright holder nor the names of its\n# contributors may be used to endorse or promote products derived from\n# this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n\"\"\"bf16 x fp4 dense GEMM for Blackwell (SM100/103/120/121).\n\nBuilt on top of ``dense_gemm_bf16_blackwell.py`` from cutlass examples at\nhttps://github.com/NVIDIA/cutlass/blob/main/examples/python/CuTeDSL/cute/blackwell_geforce/kernel/dense_gemm/dense_gemm.py\n\"\"\"\n\nfrom typing import Optional, Tuple, Type\n\nimport cuda.bindings.driver as cuda\n\nimport cutlass\nimport cutlass.cute as cute\nimport cutlass.pipeline as pipeline\nimport cutlass.utils as utils\nimport cutlass.utils.hopper_helpers as sm90_utils\nfrom cutlass import Float32, Int32, Uint32\n\nfrom ....cute_dsl.fp4_common import (\n cvt_s0e5m3_to_f16x2_broadcast,\n f16x2_to_f32x2,\n fp4_decode_4bytes,\n get_smem_ptr_as_int32,\n half2_mul,\n ld_shared_v2_u32,\n)\nfrom cutlass._mlir import ir\nfrom cutlass._mlir.dialects import llvm\nfrom cutlass._mlir.extras import types as T\nfrom cutlass.cutlass_dsl import dsl_user_op\n\n\n@dsl_user_op\ndef cvt_bf16x2_to_f16x2_via_f32(packed_bf16x2: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Packed bf16x2 (u32) -> f16x2 (u32) via f32 intermediate.\n\n Used by the fp16-MMA path (use_fp16_mma=1) to convert A's ldmatrix\n output (bf16 bit pattern from sA) to fp16 bit pattern for the fp16\n MMA inputs. Direct ``cvt.rn.f16x2.bf16x2`` is rejected by ptxas on\n sm_100a / CUDA 13.1; this packed via-f32 path is 4 PTX instrs per\n pair (mov.b32 unpack + 2x cvt.f32.bf16 + 1x cvt.rn.f16x2.f32).\n \"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(packed_bf16x2).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 b_lo, b_hi;\n .reg .f32 f_lo, f_hi;\n mov.b32 {b_lo, b_hi}, $1;\n cvt.f32.bf16 f_lo, b_lo;\n cvt.f32.bf16 f_hi, b_hi;\n cvt.rn.f16x2.f32 $0, f_hi, f_lo;\n }\n \"\"\",\n \"=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef f16x2_unpack(\n packed_h2: Uint32, *, loc=None, ip=None\n) -> Tuple[\"cutlass.Float16\", \"cutlass.Float16\"]:\n \"\"\"Unpack f16x2 (u32) into (f16_lo, f16_hi). Free at HW level --\n just a register-rename (mov.b32 {h_lo, h_hi}, packed). Used by the\n fp16-MMA path to bypass the f16->f32->bf16 cvt chain that the\n default bf16-MMA path needs after hmul2.\"\"\"\n from cutlass import Float16\n\n res = llvm.inline_asm(\n ir.Type.parse(\"!llvm.struct<(f16, f16)>\"),\n [Uint32(packed_h2).ir_value(loc=loc, ip=ip)],\n \"mov.b32 {$0, $1}, $2;\",\n \"=h,=h,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n return (\n Float16(llvm.extractvalue(T.f16(), res, [0], loc=loc, ip=ip)),\n Float16(llvm.extractvalue(T.f16(), res, [1], loc=loc, ip=ip)),\n )\n\n\n# FP4 weight packing constants (must match _cute_dsl_pack_fp4_weight in\n# flashinfer/gemm/gemm_bf16_fp4_cute_dsl.py).\n_PACK_TILE_K: cutlass.Constexpr = 16\n_PACK_TILE_N: cutlass.Constexpr = 64\n_PACK_INTS_PER_TILE: cutlass.Constexpr = 128 # 128 int32 per (16K x 64N) block\n\n\nclass BlackwellDenseGemmBf16Fp4Kernel:\n \"\"\"Warp-MMA dense GEMM for Blackwell, FP4-weight A bf16/fp16 input.\n\n A: (M, K, L) bf16/fp16.\n B: (K // 16, N * 2, L) int32 -- packed FP4 (see prepare).\n B_sf: (K // 16, N, L) uint8 -- per-group scales (S0E5M3).\n alpha: (1,) fp32 -- global scalar scale.\n C: (M, N, L) bf16/fp16; fp32 accumulator cast at write.\n\n \"\"\"\n\n GROUP_SIZE: cutlass.Constexpr = 16\n\n def __init__(\n self,\n acc_dtype,\n tile_shape_mnk,\n epi_stage: int = 4,\n pipeline_depth: int = 1,\n atom_layout: Tuple[int, int, int] = (2, 2, 1),\n epi_tile_override: Optional[Tuple[int, int]] = None,\n # 1 = fp16 MMA (default): MmaF16BF16Op uses Float16. Dequant writes\n # fp16 directly to tCrB (skipping the f16->f32->bf16 cvt chain\n # the bf16 path needs after hmul2). A is bf16 in SMEM ->\n # ldmatrix into bf16 staging fragment -> in-register packed\n # bf16->fp16 cvt -> fp16 tCrA. Slightly *more* accurate than\n # bf16 MMA for well-behaved inputs since fp16's 10-bit mantissa\n # beats bf16's 7-bit at the multiply step; accumulator stays\n # fp32 in both modes.\n # 0 = bf16 MMA: original path. Safer for workloads with very\n # large activation magnitudes (|A| > ~30000) since bf16's\n # wider exponent range avoids saturation in the A cvt.\n use_fp16_mma: int = 1,\n enable_pdl: bool = True,\n tile_swizzle: int = 1,\n raster_along_m: bool = True,\n k_splits: int = 1,\n occupancy: int = 1,\n ):\n \"\"\"bf16 x fp4 kernel.\n\n Args:\n acc_dtype: accumulator dtype (always Float32 for this kernel).\n tile_shape_mnk: CTA tile shape.\n epi_stage: TMA-store pipeline depth. Default 4 balances\n cross-tile overlap (epi_stage > 1 lets next-tile compute\n overlap with this-tile store) against SMEM available for\n ab_stage (deeper ab_stage hides TMA-load latency, which\n dominates the small-M shape's stalls). At M=4 with the\n default 64-CTA grid on 148 SMs, each SM gets at most\n one tile, so epi_stage > 1 doesn't help much locally;\n we keep 2-4 to preserve persistent-scheduler benefits\n at larger M.\n \"\"\"\n self.acc_dtype = acc_dtype\n self.cluster_shape_mnk = (1, 1, 1)\n self.tile_shape_mnk = tuple(tile_shape_mnk)\n self.epi_stage_target = int(epi_stage)\n if self.epi_stage_target < 1:\n raise ValueError(f\"epi_stage must be >= 1 (got {epi_stage})\")\n self.pipeline_depth = int(pipeline_depth)\n self.use_fp16_mma = int(use_fp16_mma)\n self.tile_swizzle = int(tile_swizzle)\n self.raster_along_m = bool(raster_along_m)\n self.enable_pdl = bool(enable_pdl)\n self.k_splits = int(k_splits)\n if self.k_splits < 1:\n raise ValueError(f\"k_splits must be >= 1 (got {k_splits})\")\n self.reduce_threads_per_cta = 256\n # Optional override for the epilogue tile shape.\n self.epi_tile_override = (\n tuple(epi_tile_override) if epi_tile_override is not None else None\n )\n self.tiled_mma = None\n # num_mcast_ctas_a / num_mcast_ctas_b are derived from the cluster\n # shape in __call__ before use; left unset here so their type is\n # inferred from that assignment (matches the sibling kernels).\n self.is_a_mcast = False\n self.is_b_mcast = False\n\n if self.tile_shape_mnk[1] % _PACK_TILE_N != 0:\n raise ValueError(\n f\"bf16 x fp4 requires tile_N % {_PACK_TILE_N} == 0 \"\n f\"(got tile_N={self.tile_shape_mnk[1]})\"\n )\n if self.tile_shape_mnk[2] % _PACK_TILE_K != 0:\n raise ValueError(\n f\"bf16 x fp4 requires tile_K % {_PACK_TILE_K} == 0 \"\n f\"(got tile_K={self.tile_shape_mnk[2]})\"\n )\n\n # occupancy > 1 splits the SMEM budget across co-resident CTAs:\n # ab_stage shrinks but resident warps multiply, which is what\n # weight-bound grids need to cover DRAM latency (_compute_stages).\n self.occupancy = int(occupancy)\n if self.occupancy < 1:\n raise ValueError(f\"occupancy must be >= 1 (got {occupancy})\")\n # 2x2 atom layout: 4 MMA warps arranged as 2 M-warps x 2 N-warps.\n self.atom_layout = tuple(atom_layout)\n if self.atom_layout not in ((2, 2, 1), (1, 2, 1)):\n raise ValueError(\n f\"Unsupported atom_layout {self.atom_layout!r}; \"\n \"expected (2,2,1) or (1,2,1)\"\n )\n self.num_mma_warps = (\n self.atom_layout[0] * self.atom_layout[1] * self.atom_layout[2]\n )\n self.num_dma_warps = 1\n self.num_threads_per_warp = 32\n self.threads_per_cta = (\n self.num_mma_warps + self.num_dma_warps\n ) * self.num_threads_per_warp\n # SM100/103 expose >= SM120 SMEM/CTA\n self.smem_capacity = utils.get_smem_capacity_in_bytes(\"sm_120\")\n\n self.ab_stage = None\n self.epi_stage = None\n\n self.a_smem_layout_staged = None\n self.b_smem_layout_staged = None\n self.epi_smem_layout_staged = None\n self.buffer_align_bytes = 1024\n\n self.epilog_sync_barrier = pipeline.NamedBarrier(\n barrier_id=2,\n num_threads=self.num_mma_warps * self.num_threads_per_warp,\n )\n self.load_register_requirement = 40\n self.mma_register_requirement = 232\n\n def _setup_attributes(self):\n self.mma_inst_mnk = (16, 8, 16)\n # MmaF16BF16Op accepts ab_dtype in {Float16, BFloat16}. We pick via\n # b_compute_dtype so use_fp16_mma=1 swings the whole MMA to fp16\n # (both A and B fragments will be fp16-typed).\n op = cute.nvgpu.warp.MmaF16BF16Op(\n self.b_compute_dtype,\n self.acc_dtype,\n self.mma_inst_mnk,\n )\n tC = cute.make_layout(self.atom_layout)\n permutation_mnk = (\n self.atom_layout[0] * self.mma_inst_mnk[0],\n # *2 trick: each warp covers two atom-N tiles in one ldmatrix.x4\n self.atom_layout[1] * self.mma_inst_mnk[1] * 2,\n self.atom_layout[2] * self.mma_inst_mnk[2],\n )\n self.tiled_mma = cute.make_tiled_mma(\n op,\n tC,\n permutation_mnk=permutation_mnk,\n )\n\n self.cta_layout_mnk = cute.make_layout(self.cluster_shape_mnk)\n\n self.num_mcast_ctas_a = self.cluster_shape_mnk[1]\n self.num_mcast_ctas_b = self.cluster_shape_mnk[0]\n self.is_a_mcast = self.num_mcast_ctas_a > 1\n self.is_b_mcast = self.num_mcast_ctas_b > 1\n\n self.epi_tile = sm90_utils.compute_tile_shape_or_override(\n self.tile_shape_mnk,\n self.c_dtype,\n is_cooperative=False,\n epi_tile_override=self.epi_tile_override,\n )\n\n # B-side smem is packed int32 (4 bytes per logical FP4\n # pair). Stage budget uses int32 B + uint8 scales; bf16 phantom\n # layout is only used by partition_B/make_fragment_B.\n self.ab_stage, self.epi_stage = self._compute_stages(\n self.tile_shape_mnk,\n self.a_dtype,\n self.epi_tile,\n self.c_dtype,\n self.smem_capacity,\n self.occupancy,\n self.GROUP_SIZE,\n self.epi_stage_target,\n )\n\n if self.ab_stage == 0:\n raise RuntimeError(\n \"ab_stage == 0: not enough shared memory for this tile shape \"\n f\"({self.tile_shape_mnk}) at occupancy {self.occupancy}.\"\n )\n\n (\n self.a_smem_layout_staged,\n self.b_packed_smem_layout_staged,\n self.b_sf_smem_layout_staged,\n self.b_bf16_logical_layout,\n self.epi_smem_layout_staged,\n ) = self._make_smem_layouts(\n self.tile_shape_mnk,\n self.epi_tile,\n self.a_dtype,\n self.a_layout,\n self.b_compute_dtype,\n self.b_layout_compute,\n self.ab_stage,\n self.c_dtype,\n self.c_layout,\n self.epi_stage,\n self.GROUP_SIZE,\n )\n\n @cute.jit\n def __call__(\n self,\n a: cute.Tensor,\n b_packed: cute.Tensor,\n b_sf: cute.Tensor,\n c: cute.Tensor,\n partial: cute.Tensor,\n alpha: cute.Tensor,\n max_active_clusters: cutlass.Constexpr,\n stream: cuda.CUstream,\n ):\n from cutlass import Float16\n\n self.a_dtype = a.element_type\n # MMA operand dtype: bf16 by default matches A, or fp16 when\n # use_fp16_mma=1 (lets us skip the f16->f32->bf16 cvt chain on B).\n if cutlass.const_expr(self.use_fp16_mma == 1):\n self.b_compute_dtype = Float16\n else:\n self.b_compute_dtype = a.element_type\n self.c_dtype = c.element_type\n\n self.a_layout = utils.LayoutEnum.from_tensor(a)\n self.b_layout_compute = utils.LayoutEnum.ROW_MAJOR\n self.c_layout = utils.LayoutEnum.from_tensor(c)\n\n if cutlass.const_expr(self.a_dtype.width != 16):\n raise TypeError(f\"a_dtype must be 16-bit (bf16/fp16), got {self.a_dtype}\")\n if cutlass.const_expr(self.a_dtype != self.c_dtype):\n raise TypeError(\n f\"a_dtype and c_dtype must match, got {self.a_dtype} vs {self.c_dtype}\"\n )\n\n self._setup_attributes()\n\n tma_atom_a, tma_tensor_a = self._make_tma_atoms_and_tensors(\n a,\n self.a_smem_layout_staged,\n (self.tile_shape_mnk[0], self.tile_shape_mnk[2]),\n 1,\n )\n\n # Packed B TMA: tile is (tile_K // 16, 2 * tile_N) int32.\n b_packed_tma_tile = (\n self.tile_shape_mnk[2] // _PACK_TILE_K,\n 2 * self.tile_shape_mnk[1],\n )\n tma_atom_b_packed, tma_tensor_b_packed = self._make_tma_atoms_and_tensors(\n b_packed,\n self.b_packed_smem_layout_staged,\n b_packed_tma_tile,\n 1,\n )\n\n # B scale TMA: tile is (tile_K // group_size, tile_N) uint8.\n # Small per-tile load -- this replaces ``tile_K // group_size``\n # gmem-direct loads per thread per K-block in the dequant path.\n b_sf_tma_tile = (\n self.tile_shape_mnk[2] // self.GROUP_SIZE,\n self.tile_shape_mnk[1],\n )\n tma_atom_b_sf, tma_tensor_b_sf = self._make_tma_atoms_and_tensors(\n b_sf,\n self.b_sf_smem_layout_staged,\n b_sf_tma_tile,\n 1,\n )\n\n tma_atom_c, tma_tensor_c = self._make_tma_store_atoms_and_tensors(\n c,\n self.epi_smem_layout_staged,\n self.epi_tile,\n )\n\n tile_sched_params, grid = self._compute_grid(\n c,\n self.tile_shape_mnk,\n max_active_clusters,\n self.tile_swizzle,\n self.raster_along_m,\n self.k_splits,\n )\n\n @cute.struct\n class SharedStorage:\n mainloop_pipeline_array_ptr: cute.struct.MemRange[\n cutlass.Int64, self.ab_stage * 2\n ]\n sA: cute.struct.Align[\n cute.struct.MemRange[\n self.a_dtype, cute.cosize(self.a_smem_layout_staged)\n ],\n self.buffer_align_bytes,\n ]\n sB_packed: cute.struct.Align[\n cute.struct.MemRange[\n cutlass.Int32, cute.cosize(self.b_packed_smem_layout_staged)\n ],\n self.buffer_align_bytes,\n ]\n sB_sf: cute.struct.Align[\n cute.struct.MemRange[\n cutlass.Uint8, cute.cosize(self.b_sf_smem_layout_staged)\n ],\n self.buffer_align_bytes,\n ]\n sC: cute.struct.Align[\n cute.struct.MemRange[\n self.c_dtype, cute.cosize(self.epi_smem_layout_staged)\n ],\n self.buffer_align_bytes,\n ]\n\n self.shared_storage = SharedStorage\n\n self.kernel(\n tma_atom_a,\n tma_tensor_a,\n tma_atom_b_packed,\n tma_tensor_b_packed,\n tma_atom_b_sf,\n tma_tensor_b_sf,\n tma_atom_c,\n tma_tensor_c,\n partial,\n alpha,\n self.tiled_mma,\n self.cta_layout_mnk,\n self.a_smem_layout_staged,\n self.b_packed_smem_layout_staged,\n self.b_sf_smem_layout_staged,\n self.b_bf16_logical_layout,\n self.epi_smem_layout_staged,\n tile_sched_params,\n ).launch(\n # No cluster dims: even a 1x1x1 cluster launch goes through the\n # cluster work distributor, whose co-residency cap (2/SM where 3\n # CTAs fit on SM12x) silently defeats occupancy > 2 tactics.\n grid=grid,\n block=[self.threads_per_cta, 1, 1],\n stream=stream,\n use_pdl=self.enable_pdl,\n )\n if cutlass.const_expr(self.k_splits > 1):\n self._launch_partial_reduce(c, partial, stream)\n return\n\n @cute.jit\n def _launch_partial_reduce(\n self,\n c: cute.Tensor,\n partial: cute.Tensor,\n stream: cuda.CUstream,\n ):\n \"\"\"Launch the split-K reduce, PDL-chained behind the GEMM grid.\"\"\"\n total = cute.size(c, mode=[0]) * cute.size(c, mode=[1])\n reduce_grid = (total + Int32(self.reduce_threads_per_cta) - Int32(1)) // Int32(\n self.reduce_threads_per_cta\n )\n self.kernel_partial_reduce(partial, c).launch(\n grid=[reduce_grid, 1, 1],\n block=[self.reduce_threads_per_cta, 1, 1],\n stream=stream,\n use_pdl=self.enable_pdl,\n )\n\n @cute.kernel\n def kernel_partial_reduce(\n self,\n mPartial: cute.Tensor,\n mC_mnl: cute.Tensor,\n ):\n \"\"\"Sum the fp32 partials into C, one element per thread, in fixed\n split order for determinism.\"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n bidx, _, _ = cute.arch.block_idx()\n\n cute.arch.griddepcontrol_wait()\n\n m_actual = cute.size(mC_mnl, mode=[0])\n n_actual = cute.size(mC_mnl, mode=[1])\n total = m_actual * n_actual\n mC_flat = cute.make_tensor(mC_mnl.iterator, cute.make_layout(total))\n\n idx = Int32(bidx) * Int32(self.reduce_threads_per_cta) + tidx\n if idx < total:\n acc_sum = Float32(0.0)\n for s in cutlass.range_constexpr(self.k_splits):\n acc_sum = acc_sum + Float32(mPartial[Int32(s) * total + idx])\n mC_flat[idx] = acc_sum.to(self.c_dtype)\n\n cute.arch.griddepcontrol_launch_dependents()\n return\n\n @cute.kernel\n def kernel(\n self,\n tma_atom_a: cute.CopyAtom,\n mA_mkl: cute.Tensor,\n tma_atom_b_packed: cute.CopyAtom,\n mB_packed_kn: cute.Tensor,\n tma_atom_b_sf: cute.CopyAtom,\n mB_sf_kn: cute.Tensor,\n tma_atom_c: cute.CopyAtom,\n mC_mnl: cute.Tensor,\n # fp32 split-K partials of shape (k_splits * m, n); an unused\n # dummy when k_splits == 1.\n mPartial: cute.Tensor,\n mAlpha: cute.Tensor,\n tiled_mma: cute.TiledMma,\n cta_layout_mnk: cute.Layout,\n a_smem_layout_staged: cute.ComposedLayout,\n b_packed_smem_layout_staged: cute.Layout,\n b_sf_smem_layout_staged: cute.Layout,\n b_bf16_logical_layout: cute.ComposedLayout,\n epi_smem_layout_staged: cute.ComposedLayout,\n tile_sched_params: utils.PersistentTileSchedulerParams,\n ):\n tidx, _, _ = cute.arch.thread_idx()\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n\n # Prefetch TMA descriptors from warp 0.\n if warp_idx == 0:\n cute.nvgpu.cpasync.prefetch_descriptor(tma_atom_a)\n cute.nvgpu.cpasync.prefetch_descriptor(tma_atom_b_packed)\n cute.nvgpu.cpasync.prefetch_descriptor(tma_atom_b_sf)\n cute.nvgpu.cpasync.prefetch_descriptor(tma_atom_c)\n\n cta_rank_in_cluster = cute.arch.make_warp_uniform(\n cute.arch.block_idx_in_cluster()\n )\n cluster_coord_mnk = cta_layout_mnk.get_flat_coord(cta_rank_in_cluster)\n\n a_mcast_mask = cute.make_layout_image_mask(\n cta_layout_mnk, cluster_coord_mnk, mode=1\n )\n b_mcast_mask = cute.make_layout_image_mask(\n cta_layout_mnk, cluster_coord_mnk, mode=0\n )\n a_mcast_mask = a_mcast_mask if self.is_a_mcast else 0\n b_mcast_mask = b_mcast_mask if self.is_b_mcast else 0\n\n a_smem_layout = cute.slice_(a_smem_layout_staged, (None, None, 0))\n b_packed_smem_layout = cute.slice_(b_packed_smem_layout_staged, (None, None, 0))\n b_sf_smem_layout = cute.slice_(b_sf_smem_layout_staged, (None, None, 0))\n tma_copy_bytes = (\n cute.size_in_bytes(self.a_dtype, a_smem_layout)\n + cute.size_in_bytes(cutlass.Int32, b_packed_smem_layout)\n + cute.size_in_bytes(cutlass.Uint8, b_sf_smem_layout)\n )\n\n smem = cutlass.utils.SmemAllocator()\n storage = smem.allocate(self.shared_storage)\n\n mainloop_pipeline_array_ptr = storage.mainloop_pipeline_array_ptr.data_ptr()\n\n mainloop_pipeline_producer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread\n )\n mcast_size = self.num_mcast_ctas_a + self.num_mcast_ctas_b - 1\n consumer_arrive_cnt = mcast_size * self.num_mma_warps\n mainloop_pipeline_consumer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread, consumer_arrive_cnt\n )\n\n cta_layout_vmnk = cute.make_layout((1, *cta_layout_mnk.shape))\n mainloop_pipeline = pipeline.PipelineTmaAsync.create(\n num_stages=self.ab_stage,\n producer_group=mainloop_pipeline_producer_group,\n consumer_group=mainloop_pipeline_consumer_group,\n tx_count=tma_copy_bytes,\n barrier_storage=mainloop_pipeline_array_ptr,\n cta_layout_vmnk=cta_layout_vmnk,\n )\n\n if cute.size(self.cluster_shape_mnk) > 1:\n cute.arch.cluster_arrive_relaxed()\n\n sA = storage.sA.get_tensor(\n a_smem_layout_staged.outer, swizzle=a_smem_layout_staged.inner\n )\n # Both B-side tensors are plain (non-swizzled) staged layouts.\n sB_packed = storage.sB_packed.get_tensor(b_packed_smem_layout_staged)\n sB_sf = storage.sB_sf.get_tensor(b_sf_smem_layout_staged)\n sC = storage.sC.get_tensor(\n epi_smem_layout_staged.outer, swizzle=epi_smem_layout_staged.inner\n )\n\n gA_mkl = cute.local_tile(\n mA_mkl,\n cute.slice_(self.tile_shape_mnk, (None, 0, None)),\n (None, None, None),\n )\n # Packed B: (K // 16, N * 2, L); tile = (tile_K // 16, 2 * tile_N).\n b_packed_tile_shape = (\n self.tile_shape_mnk[2] // _PACK_TILE_K,\n 2 * self.tile_shape_mnk[1],\n )\n gB_packed_kn = cute.local_tile(\n mB_packed_kn,\n b_packed_tile_shape,\n (None, None, None),\n )\n # Scales: (K // 16, N, L); per-tile slice has shape\n # (tile_K // group_size, tile_N) = (tile_K // 16, tile_N). Dequant\n # indexes directly per K-block + per N-coord.\n gB_sf_kn = cute.local_tile(\n mB_sf_kn,\n (self.tile_shape_mnk[2] // self.GROUP_SIZE, self.tile_shape_mnk[1]),\n (None, None, None),\n )\n gC_mnl = cute.local_tile(\n mC_mnl,\n cute.slice_(self.tile_shape_mnk, (None, None, 0)),\n (None, None, None),\n )\n\n thr_mma = tiled_mma.get_slice(tidx)\n\n # TMA partition for A: (m, k) -> per-CTA partition.\n a_cta_layout = cute.make_layout(cute.slice_(cta_layout_mnk, (0, None, 0)).shape)\n a_cta_crd = cluster_coord_mnk[1]\n tAsA, tAgA = cute.nvgpu.cpasync.tma_partition(\n tma_atom_a,\n a_cta_crd,\n a_cta_layout,\n cute.group_modes(sA, 0, 2),\n cute.group_modes(gA_mkl, 0, 2),\n )\n\n # TMA partition for B (packed int32).\n b_cta_layout = cute.make_layout(cute.slice_(cta_layout_mnk, (None, 0, 0)).shape)\n b_cta_crd = cluster_coord_mnk[0]\n tBpacked_s, tBpacked_g = cute.nvgpu.cpasync.tma_partition(\n tma_atom_b_packed,\n b_cta_crd,\n b_cta_layout,\n cute.group_modes(sB_packed, 0, 2),\n cute.group_modes(gB_packed_kn, 0, 2),\n )\n\n # TMA partition for B_sf (uint8 scales). Shares the b_cta_crd\n # (no N multicast since cluster_shape_mnk = (1,1,1)).\n tBsf_s, tBsf_g = cute.nvgpu.cpasync.tma_partition(\n tma_atom_b_sf,\n b_cta_crd,\n b_cta_layout,\n cute.group_modes(sB_sf, 0, 2),\n cute.group_modes(gB_sf_kn, 0, 2),\n )\n\n # B partition uses a phantom bf16 layout on top of the sB_packed\n # int32 storage (recast pointer + bf16 logical layout). This\n # gives ``partition_B``/``make_fragment_B`` the right fragment\n # shape; the data is never read through this view -- we always\n # decode FP4 ourselves.\n sB_phantom = cute.make_tensor(\n cute.recast_ptr(sB_packed.iterator, dtype=self.b_compute_dtype),\n b_bf16_logical_layout,\n )\n tCsA = thr_mma.partition_A(sA)\n tCsB_phantom = thr_mma.partition_B(sB_phantom)\n tCrA = tiled_mma.make_fragment_A(tCsA[None, None, None, 0])\n tCrB = tiled_mma.make_fragment_B(tCsB_phantom[None, None, None, 0])\n\n tCgC = thr_mma.partition_C(gC_mnl)\n acc_shape = tCgC.shape[:3]\n accumulators = cute.make_rmem_tensor(acc_shape, self.acc_dtype)\n\n if cute.size(self.cluster_shape_mnk) > 1:\n cute.arch.cluster_wait()\n else:\n pipeline.sync(barrier_id=1)\n\n # PDL bookend (start): wait for the prior grid to finish so this\n # kernel's TMA loads see the producer kernel's writes.\n cute.arch.griddepcontrol_wait()\n\n k_tile_cnt = cute.size(gA_mkl, mode=[3])\n\n tile_sched = utils.StaticPersistentTileScheduler.create(\n tile_sched_params, cute.arch.block_idx(), cute.arch.grid_dim()\n )\n work_tile = tile_sched.initial_work_tile_info()\n\n mainloop_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.ab_stage\n )\n mainloop_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.ab_stage\n )\n\n # MMA warp group: warps [0, num_mma_warps) compute.\n if warp_idx < self.num_mma_warps:\n cute.arch.setmaxregister_increase(self.mma_register_requirement)\n\n num_k_blocks = cute.size(tCrA, mode=[2])\n\n # ldmatrix is only for A. B is filled in-register from sB_packed\n # via FP4 decode + per-group scale.\n #\n # use_fp16_mma=1: tCrA is fp16-typed (matches the fp16 MMA), but\n # sA is bf16 in SMEM. ldmatrix into a bf16 staging fragment,\n # then per-K-block convert bf16 -> fp16 in-register before MMA\n # reads tCrA. See the inline cvt at each ldmatrix site.\n from cutlass import BFloat16\n\n atom_copy_ldmatrix_A = cute.make_copy_atom(\n cute.nvgpu.warp.LdMatrix8x8x16bOp(self.a_layout.is_m_major_a(), 4),\n self.a_dtype,\n )\n smem_tiled_copy_A = cute.make_tiled_copy_A(atom_copy_ldmatrix_A, tiled_mma)\n thr_copy_ldmatrix_A = smem_tiled_copy_A.get_slice(tidx)\n tCsA_copy_view = thr_copy_ldmatrix_A.partition_S(sA)\n if cutlass.const_expr(self.use_fp16_mma == 1):\n tCrA_bf16 = cute.make_fragment_like(tCrA, BFloat16)\n tCrA_copy_view = thr_copy_ldmatrix_A.retile(tCrA_bf16)\n else:\n tCrA_bf16 = tCrA\n tCrA_copy_view = thr_copy_ldmatrix_A.retile(tCrA)\n\n alpha_val = Float32(mAlpha[Int32(0)])\n\n if cutlass.const_expr(self.k_splits > 1):\n cC = cute.make_identity_tensor(\n cute.slice_(self.tile_shape_mnk, (None, None, 0))\n )\n tCcC = thr_mma.partition_C(cC)\n\n while work_tile.is_valid_tile:\n tile_coord_mnl = work_tile.tile_idx\n # k_splits <= k_tiles is checked at launch, so no split is empty.\n if cutlass.const_expr(self.k_splits > 1):\n tile_l, split_idx, k_start, k_len = self._split_work_krange(\n tile_coord_mnl[2], k_tile_cnt\n )\n else:\n tile_l = tile_coord_mnl[2]\n k_len = k_tile_cnt\n gC_mnl_slice = gC_mnl[\n (None, None, tile_coord_mnl[0], tile_coord_mnl[1], tile_l)\n ]\n accumulators.fill(0.0)\n\n mainloop_consumer_state.reset_count()\n\n peek_ab_full_status = cutlass.Boolean(1)\n if mainloop_consumer_state.count < k_len:\n peek_ab_full_status = mainloop_pipeline.consumer_try_wait(\n mainloop_consumer_state\n )\n\n mainloop_pipeline.consumer_wait(\n mainloop_consumer_state, peek_ab_full_status\n )\n tCsA_p = tCsA_copy_view[None, None, None, mainloop_consumer_state.index]\n\n # Prologue: prefetch tCrA[0] and tCrB[0] only when running with\n # pipeline_depth >= 1. With depth=0 the dequant for block k\n # happens inside the same iteration as gemm(k) -- no prefetch.\n if cutlass.const_expr(self.pipeline_depth >= 1):\n cute.copy(\n smem_tiled_copy_A,\n tCsA_p[None, None, 0],\n tCrA_copy_view[None, None, 0],\n )\n if cutlass.const_expr(self.use_fp16_mma == 1):\n self._cvt_a_bf16_to_fp16_one_k_block(tCrA, tCrA_bf16, 0)\n self._dequant_b_to_register(\n sB_packed,\n sB_sf,\n tCrB,\n tidx,\n mainloop_consumer_state.index,\n mainloop_consumer_state.count,\n 0,\n )\n\n for _k_tile in cutlass.range(0, k_len - 1, 1, unroll=1):\n for k_block_idx in cutlass.range_constexpr(num_k_blocks):\n k_block_next = (\n 0 if k_block_idx + 1 == num_k_blocks else k_block_idx + 1\n )\n\n if cutlass.const_expr(self.pipeline_depth == 0):\n # No-prefetch: dequant(k) just before gemm(k),\n # all on the CURRENT K-tile's stage. Release +\n # advance + wait happens AFTER gemm of the last\n # block so we don't drop SMEM under our own read.\n cute.copy(\n smem_tiled_copy_A,\n tCsA_p[None, None, k_block_idx],\n tCrA_copy_view[None, None, k_block_idx],\n )\n if cutlass.const_expr(self.use_fp16_mma == 1):\n self._cvt_a_bf16_to_fp16_one_k_block(\n tCrA, tCrA_bf16, k_block_idx\n )\n self._dequant_b_to_register(\n sB_packed,\n sB_sf,\n tCrB,\n tidx,\n mainloop_consumer_state.index,\n mainloop_consumer_state.count,\n k_block_idx,\n )\n cute.gemm(\n tiled_mma,\n accumulators,\n tCrA[None, None, k_block_idx],\n tCrB[None, None, k_block_idx],\n accumulators,\n )\n if k_block_idx == num_k_blocks - 1:\n mainloop_pipeline.consumer_release(\n mainloop_consumer_state\n )\n mainloop_consumer_state.advance()\n peek_ab_full_status = cutlass.Boolean(1)\n peek_ab_full_status = (\n mainloop_pipeline.consumer_try_wait(\n mainloop_consumer_state\n )\n )\n tCsA_p = tCsA_copy_view[\n None, None, None, mainloop_consumer_state.index\n ]\n mainloop_pipeline.consumer_wait(\n mainloop_consumer_state, peek_ab_full_status\n )\n else:\n # 1-stage prefetch: dequant(k+1) while gemm(k).\n if k_block_idx == num_k_blocks - 1:\n mainloop_pipeline.consumer_release(\n mainloop_consumer_state\n )\n mainloop_consumer_state.advance()\n\n peek_ab_full_status = cutlass.Boolean(1)\n peek_ab_full_status = (\n mainloop_pipeline.consumer_try_wait(\n mainloop_consumer_state\n )\n )\n\n tCsA_p = tCsA_copy_view[\n None, None, None, mainloop_consumer_state.index\n ]\n mainloop_pipeline.consumer_wait(\n mainloop_consumer_state, peek_ab_full_status\n )\n\n cute.copy(\n smem_tiled_copy_A,\n tCsA_p[None, None, k_block_next],\n tCrA_copy_view[None, None, k_block_next],\n )\n if cutlass.const_expr(self.use_fp16_mma == 1):\n self._cvt_a_bf16_to_fp16_one_k_block(\n tCrA, tCrA_bf16, k_block_next\n )\n self._dequant_b_to_register(\n sB_packed,\n sB_sf,\n tCrB,\n tidx,\n mainloop_consumer_state.index,\n mainloop_consumer_state.count,\n k_block_next,\n )\n cute.gemm(\n tiled_mma,\n accumulators,\n tCrA[None, None, k_block_idx],\n tCrB[None, None, k_block_idx],\n accumulators,\n )\n # Hoist out last k_tile (no further loads after the last k_block)\n for k_block_idx in cutlass.range_constexpr(num_k_blocks):\n k_block_next = (\n 0 if k_block_idx + 1 == num_k_blocks else k_block_idx + 1\n )\n\n if cutlass.const_expr(self.pipeline_depth == 0):\n # No-prefetch path for last K-tile. Release happens\n # AFTER gemm of the last block (kernel exits then).\n cute.copy(\n smem_tiled_copy_A,\n tCsA_p[None, None, k_block_idx],\n tCrA_copy_view[None, None, k_block_idx],\n )\n if cutlass.const_expr(self.use_fp16_mma == 1):\n self._cvt_a_bf16_to_fp16_one_k_block(\n tCrA, tCrA_bf16, k_block_idx\n )\n self._dequant_b_to_register(\n sB_packed,\n sB_sf,\n tCrB,\n tidx,\n mainloop_consumer_state.index,\n mainloop_consumer_state.count,\n k_block_idx,\n )\n cute.gemm(\n tiled_mma,\n accumulators,\n tCrA[None, None, k_block_idx],\n tCrB[None, None, k_block_idx],\n accumulators,\n )\n if k_block_idx == num_k_blocks - 1:\n mainloop_pipeline.consumer_release(mainloop_consumer_state)\n mainloop_consumer_state.advance()\n else:\n # 1-stage prefetch path for last K-tile.\n if k_block_idx == num_k_blocks - 1:\n mainloop_pipeline.consumer_release(mainloop_consumer_state)\n mainloop_consumer_state.advance()\n\n if k_block_next > 0:\n cute.copy(\n smem_tiled_copy_A,\n tCsA_p[None, None, k_block_next],\n tCrA_copy_view[None, None, k_block_next],\n )\n if cutlass.const_expr(self.use_fp16_mma == 1):\n self._cvt_a_bf16_to_fp16_one_k_block(\n tCrA, tCrA_bf16, k_block_next\n )\n self._dequant_b_to_register(\n sB_packed,\n sB_sf,\n tCrB,\n tidx,\n mainloop_consumer_state.index,\n mainloop_consumer_state.count,\n k_block_next,\n )\n cute.gemm(\n tiled_mma,\n accumulators,\n tCrA[None, None, k_block_idx],\n tCrB[None, None, k_block_idx],\n accumulators,\n )\n\n if cutlass.const_expr(self.k_splits > 1):\n # Store fp32 partials straight from registers; staging through\n # the output-dtype smem buffer would round each split early.\n m_actual = cute.size(mC_mnl, mode=[0])\n n_actual = cute.size(mC_mnl, mode=[1])\n cta_m_offset = tile_coord_mnl[0] * Int32(self.tile_shape_mnk[0])\n cta_n_offset = tile_coord_mnl[1] * Int32(self.tile_shape_mnk[1])\n for i in cutlass.range_constexpr(cute.size(accumulators)):\n r = cta_m_offset + Int32(tCcC[i][0])\n if r < m_actual:\n c = cta_n_offset + Int32(tCcC[i][1])\n mPartial[(split_idx * m_actual + r) * n_actual + c] = (\n alpha_val * accumulators[i]\n )\n\n else:\n copy_atom_r2s = sm90_utils.sm90_get_smem_store_op(\n self.c_layout,\n elem_ty_d=self.c_dtype,\n elem_ty_acc=self.acc_dtype,\n )\n\n copy_atom_C = cute.make_copy_atom(\n cute.nvgpu.warp.StMatrix8x8x16bOp(\n self.c_layout.is_m_major_c(),\n 4,\n ),\n self.c_dtype,\n )\n\n tiled_copy_C_Atom = cute.make_tiled_copy_C_atom(\n copy_atom_C, tiled_mma\n )\n\n tiled_copy_r2s = cute.make_tiled_copy_S(\n copy_atom_r2s,\n tiled_copy_C_Atom,\n )\n\n thr_copy_r2s = tiled_copy_r2s.get_slice(tidx)\n tRS_sD = thr_copy_r2s.partition_D(sC)\n tRS_rAcc = tiled_copy_r2s.retile(accumulators)\n\n rD_shape = cute.shape(thr_copy_r2s.partition_S(sC))\n tRS_rD_layout = cute.make_layout(rD_shape[:3])\n tRS_rD = cute.make_rmem_tensor(tRS_rD_layout.shape, self.acc_dtype)\n\n sepi_for_tma_partition = cute.group_modes(sC, 0, 2)\n tcgc_for_tma_partition = cute.zipped_divide(\n gC_mnl_slice, self.epi_tile\n )\n\n bSG_sD, bSG_gD = cute.nvgpu.cpasync.tma_partition(\n tma_atom_c,\n 0,\n cute.make_layout(1),\n sepi_for_tma_partition,\n tcgc_for_tma_partition,\n )\n\n # Index tRS_rAcc by (mma_m, mma_n) modes so the loop\n # works for any epi_tile shape.\n epi_rest_m = cute.size(tcgc_for_tma_partition, mode=[1, 0])\n epi_rest_n = cute.size(tcgc_for_tma_partition, mode=[1, 1])\n epi_tile_m = self.epi_tile[0]\n epi_tile_n = self.epi_tile[1]\n # tRS_rAcc holds one fragment per MMA-atom tile, so dividing\n # the CTA tile by the (mma_m, mma_n) mode extents gives the\n # per-atom tile size.\n mma_tile_m = self.tile_shape_mnk[0] // cute.size(tRS_rAcc, mode=[1])\n mma_tile_n = self.tile_shape_mnk[1] // cute.size(tRS_rAcc, mode=[2])\n MmaMPerEpiM = epi_tile_m // mma_tile_m\n MmaNPerEpiN = epi_tile_n // mma_tile_n\n\n tma_store_producer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n self.num_mma_warps * self.num_threads_per_warp,\n )\n tma_store_pipeline = pipeline.PipelineTmaStore.create(\n num_stages=self.epi_stage,\n producer_group=tma_store_producer_group,\n )\n\n m_actual = cute.size(mC_mnl, mode=[0])\n cta_m_offset = tile_coord_mnl[0] * Int32(self.tile_shape_mnk[0])\n\n # Skipped iterations must not advance the TMA-store pipeline,\n # so the stage index comes from kept_count rather than the\n # loop indices.\n kept_count = 0\n for epi_n in cutlass.range_constexpr(epi_rest_n):\n for epi_m in cutlass.range_constexpr(epi_rest_m):\n epi_m_global_start = cta_m_offset + Int32(\n epi_m * epi_tile_m\n )\n if epi_m_global_start < m_actual:\n for mma_n_in_epi in cutlass.range_constexpr(\n MmaNPerEpiN\n ):\n for mma_m_in_epi in cutlass.range_constexpr(\n MmaMPerEpiM\n ):\n mma_n = epi_n * MmaNPerEpiN + mma_n_in_epi\n mma_m = epi_m * MmaMPerEpiM + mma_m_in_epi\n tRS_rD_slice = tRS_rD[\n (None, mma_m_in_epi, mma_n_in_epi)\n ]\n tRS_rAcc_slice = tRS_rAcc[(None, mma_m, mma_n)]\n for elem_idx in cutlass.range_constexpr(\n cute.size(tRS_rD_slice)\n ):\n tRS_rD_slice[elem_idx] = tRS_rAcc_slice[\n elem_idx\n ]\n\n tRS_rD_out = cute.make_rmem_tensor(\n tRS_rD_layout.shape, self.c_dtype\n )\n acc_vec = tRS_rD.load()\n tRS_rD_out.store((alpha_val * acc_vec).to(self.c_dtype))\n\n epi_buffer = kept_count % cute.size(tRS_sD, mode=[3])\n cute.copy(\n tiled_copy_r2s,\n tRS_rD_out,\n tRS_sD[(None, None, None, epi_buffer)],\n )\n cute.arch.fence_proxy(\"async.shared\", space=\"cta\")\n self.epilog_sync_barrier.arrive_and_wait()\n\n if warp_idx == 0:\n cute.copy(\n tma_atom_c,\n bSG_sD[(None, epi_buffer)],\n bSG_gD[(None, (epi_m, epi_n))],\n )\n tma_store_pipeline.producer_commit()\n tma_store_pipeline.producer_acquire()\n kept_count = kept_count + 1\n\n tma_store_pipeline.producer_tail()\n\n tile_sched.advance_to_next_work()\n work_tile = tile_sched.get_current_work()\n # Single DMA warp: issues all 3 TMA descriptors (A, B_packed, B_sf)\n # back-to-back into the same stage barrier per K-tile.\n elif warp_idx == self.num_mma_warps:\n cute.arch.setmaxregister_decrease(self.load_register_requirement)\n while work_tile.is_valid_tile:\n tile_coord_mnl = work_tile.tile_idx\n if cutlass.const_expr(self.k_splits > 1):\n tile_l, split_idx, k_start, k_len = self._split_work_krange(\n tile_coord_mnl[2], k_tile_cnt\n )\n else:\n tile_l = tile_coord_mnl[2]\n k_start = Int32(0)\n k_len = k_tile_cnt\n tAgA_mkl = tAgA[(None, tile_coord_mnl[0], None, tile_l)]\n tBpacked_g_kn = tBpacked_g[(None, None, tile_coord_mnl[1], tile_l)]\n tBsf_g_kn = tBsf_g[(None, None, tile_coord_mnl[1], tile_l)]\n mainloop_producer_state.reset_count()\n for _k_tile in cutlass.range(0, k_len, 1, unroll=1):\n mainloop_pipeline.producer_acquire(mainloop_producer_state)\n barrier_ptr = mainloop_pipeline.producer_get_barrier(\n mainloop_producer_state\n )\n\n tAgA_k = tAgA_mkl[(None, k_start + mainloop_producer_state.count)]\n tAsA_pipe = tAsA[(None, mainloop_producer_state.index)]\n cute.copy(\n tma_atom_a,\n tAgA_k,\n tAsA_pipe,\n tma_bar_ptr=barrier_ptr,\n mcast_mask=a_mcast_mask,\n )\n\n tBpacked_g_k = tBpacked_g_kn[\n (None, k_start + mainloop_producer_state.count)\n ]\n tBpacked_s_pipe = tBpacked_s[(None, mainloop_producer_state.index)]\n cute.copy(\n tma_atom_b_packed,\n tBpacked_g_k,\n tBpacked_s_pipe,\n tma_bar_ptr=barrier_ptr,\n mcast_mask=b_mcast_mask,\n )\n\n tBsf_g_k = tBsf_g_kn[\n (None, k_start + mainloop_producer_state.count)\n ]\n tBsf_s_pipe = tBsf_s[(None, mainloop_producer_state.index)]\n cute.copy(\n tma_atom_b_sf,\n tBsf_g_k,\n tBsf_s_pipe,\n tma_bar_ptr=barrier_ptr,\n mcast_mask=b_mcast_mask,\n )\n\n mainloop_pipeline.producer_commit(mainloop_producer_state)\n mainloop_producer_state.advance()\n tile_sched.advance_to_next_work()\n work_tile = tile_sched.get_current_work()\n mainloop_pipeline.producer_tail(mainloop_producer_state)\n cute.arch.griddepcontrol_launch_dependents()\n return\n\n @staticmethod\n def _compute_stages(\n tile_shape_mnk: Tuple[int, int, int],\n a_dtype: Type[cutlass.Numeric],\n epi_tile: Tuple[int, int],\n c_dtype: Type[cutlass.Numeric],\n smem_capacity: int,\n occupancy: int,\n group_size: int = 16,\n epi_stage: int = 4,\n ) -> Tuple[int, int]:\n \"\"\"Stage budget accounting for A + B (packed int32) + B_sf (uint8).\n\n Per (16K x 64N) packed block: 128 int32 = 512 bytes.\n Per (group_size K x tile_N N) scale block: tile_N bytes.\n \"\"\"\n c_bytes_per_stage = cute.size(epi_tile) * c_dtype.width // 8\n epi_bytes = c_bytes_per_stage * epi_stage\n\n a_shape = cute.slice_(tile_shape_mnk, (None, 0, None))\n a_bytes_per_stage = cute.size(a_shape) * a_dtype.width // 8\n\n # B side: packed int32, 128 int32 per (16K x 64N) block.\n packed_blocks_per_tile = (tile_shape_mnk[2] // _PACK_TILE_K) * (\n tile_shape_mnk[1] // _PACK_TILE_N\n )\n b_packed_bytes_per_stage = packed_blocks_per_tile * _PACK_INTS_PER_TILE * 4\n\n # Scale tile: 1 byte per (K-group, N). Small compared to B_packed.\n b_sf_bytes_per_stage = (tile_shape_mnk[2] // group_size) * tile_shape_mnk[1]\n\n ab_bytes_per_stage = (\n a_bytes_per_stage + b_packed_bytes_per_stage + b_sf_bytes_per_stage\n )\n mbar_helpers_bytes = 1024\n\n ab_stage = (\n (smem_capacity - occupancy * 1024) // occupancy\n - mbar_helpers_bytes\n - epi_bytes\n ) // ab_bytes_per_stage\n return ab_stage, epi_stage\n\n @staticmethod\n def _make_smem_layouts(\n tile_shape_mnk: Tuple[int, int, int],\n epi_tile: Tuple[int, int],\n a_dtype: Type[cutlass.Numeric],\n a_layout: cute.Layout,\n b_compute_dtype: Type[cutlass.Numeric],\n b_layout_compute: cute.Layout,\n ab_stage: int,\n c_dtype: Type[cutlass.Numeric],\n c_layout: cute.Layout,\n epi_stage: int,\n group_size: int,\n ):\n \"\"\"Returns (sA, sB_packed, sB_sf, b_bf16_phantom, sC) layouts.\n\n ``sB_packed_layout`` is a plain (non-swizzled) staged int32 layout\n ``(tile_K // 16, 2 * tile_N, ab_stage)``.\n\n ``sB_sf_layout`` is a plain staged uint8 layout\n ``(tile_K // group_size, tile_N, ab_stage)`` -- one byte per\n (K-group, N) cell. Loaded via TMA once per K-tile, read from\n SMEM in the dequant inner loop (replaces the gmem-direct path).\n\n ``b_bf16_logical_layout`` is the phantom bf16 layout used only by\n ``partition_B`` / ``make_fragment_B`` for fragment-shape\n determination -- there is no real bf16 SMEM allocation.\n \"\"\"\n a_smem_layout_staged = sm90_utils.make_smem_layout_a(\n a_layout,\n tile_shape_mnk,\n a_dtype,\n ab_stage,\n )\n\n # sB_packed: (tile_K // 16) rows x (2 * tile_N) int32 cols x stage.\n b_packed_smem_layout_staged = cute.make_ordered_layout(\n (\n tile_shape_mnk[2] // _PACK_TILE_K,\n 2 * tile_shape_mnk[1],\n ab_stage,\n ),\n order=(1, 0, 2),\n )\n\n # sB_sf: (tile_K // group_size) rows x tile_N uint8 cols x stage.\n # Order (1, 0, 2) -> N innermost (= contiguous load lane), K next,\n # stage outermost. Matches the gmem layout.\n b_sf_smem_layout_staged = cute.make_ordered_layout(\n (\n tile_shape_mnk[2] // group_size,\n tile_shape_mnk[1],\n ab_stage,\n ),\n order=(1, 0, 2),\n )\n\n # bf16 phantom layout for partition_B / make_fragment_B.\n b_bf16_logical_layout = sm90_utils.make_smem_layout_b(\n b_layout_compute,\n tile_shape_mnk,\n b_compute_dtype,\n ab_stage,\n )\n\n epi_smem_layout_staged = sm90_utils.make_smem_layout_epi(\n c_dtype,\n c_layout,\n epi_tile,\n epi_stage,\n )\n return (\n a_smem_layout_staged,\n b_packed_smem_layout_staged,\n b_sf_smem_layout_staged,\n b_bf16_logical_layout,\n epi_smem_layout_staged,\n )\n\n @staticmethod\n def _compute_grid(\n c: cute.Tensor,\n tile_shape_mnk: Tuple[int, int, int],\n max_active_clusters: cutlass.Constexpr,\n tile_swizzle: cutlass.Constexpr = 1,\n raster_along_m: cutlass.Constexpr = True,\n k_splits: cutlass.Constexpr = 1,\n ):\n c_shape = cute.slice_(tile_shape_mnk, (None, None, 0))\n gc = cute.zipped_divide(c, tiler=c_shape)\n num_ctas_mnl = gc[(0, (None, None, None))].shape\n # Split-K reuses the scheduler's otherwise size-1 batch (L) mode.\n if cutlass.const_expr(k_splits > 1):\n num_ctas_mnl = (\n num_ctas_mnl[0],\n num_ctas_mnl[1],\n num_ctas_mnl[2] * k_splits,\n )\n cluster_shape_mnl = (1, 1, 1)\n tile_sched_params = utils.PersistentTileSchedulerParams(\n num_ctas_mnl,\n cluster_shape_mnl,\n swizzle_size=tile_swizzle,\n raster_along_m=raster_along_m,\n )\n grid = utils.StaticPersistentTileScheduler.get_grid_shape(\n tile_sched_params, max_active_clusters\n )\n return tile_sched_params, grid\n\n @staticmethod\n def _make_tma_store_atoms_and_tensors(\n tensor_c: cute.Tensor,\n epi_smem_layout_staged: cute.ComposedLayout,\n epi_tile: Tuple[int, int],\n ) -> Tuple[cute.CopyAtom, cute.Tensor]:\n epi_smem_layout = cute.slice_(epi_smem_layout_staged, (None, None, 0))\n tma_atom_c, tma_tensor_c = cute.nvgpu.cpasync.make_tiled_tma_atom(\n cute.nvgpu.cpasync.CopyBulkTensorTileS2GOp(),\n tensor_c,\n epi_smem_layout,\n epi_tile,\n )\n return tma_atom_c, tma_tensor_c\n\n @staticmethod\n def _make_tma_atoms_and_tensors(\n tensor: cute.Tensor,\n smem_layout_staged: cute.ComposedLayout,\n smem_tile: Tuple[int, int],\n mcast_dim: int,\n ) -> Tuple[cute.CopyAtom, cute.Tensor]:\n op = (\n cute.nvgpu.cpasync.CopyBulkTensorTileG2SOp()\n if mcast_dim == 1\n else cute.nvgpu.cpasync.CopyBulkTensorTileG2SMulticastOp()\n )\n smem_layout = cute.slice_(smem_layout_staged, (None, None, 0))\n tma_atom, tma_tensor = cute.nvgpu.cpasync.make_tiled_tma_atom(\n op,\n tensor,\n smem_layout,\n smem_tile,\n num_multicast=mcast_dim,\n )\n return tma_atom, tma_tensor\n\n @cute.jit\n def _split_work_krange(self, tile_coord_l, k_tile_cnt):\n \"\"\"Compute the balanced K-tile range of one split.\n\n Producer and consumer branches both call this so their ranges agree.\n \"\"\"\n split_idx = Int32(tile_coord_l) % Int32(self.k_splits)\n tile_l = Int32(tile_coord_l) // Int32(self.k_splits)\n k_start = split_idx * k_tile_cnt // Int32(self.k_splits)\n k_stop = (split_idx + Int32(1)) * k_tile_cnt // Int32(self.k_splits)\n return tile_l, split_idx, k_start, k_stop - k_start\n\n @cute.jit\n def _cvt_a_bf16_to_fp16_one_k_block(\n self,\n tCrA_dst,\n tCrA_bf16_src,\n k_block: cutlass.Constexpr,\n ):\n \"\"\"In-register bf16 -> fp16 cvt for one K-block of A.\n\n Recasts both fragments to Uint32 (each u32 packs 2 16-bit elems)\n and applies `cvt_bf16x2_to_f16x2_via_f32` per pair. The packed\n narrowing cvt (`cvt.rn.f16x2.f32`) combines what would be two\n scalar `cvt.rn.f16.f32` instructions if we used cute's default\n `.to(Float16)` lowering.\n\n bf16/f16 typed inline-asm constraints don't compile on sm_100a\n (NVVM rejects them), so we keep everything in Uint32 pair\n representation via cute.recast_tensor.\n \"\"\"\n bf_u32 = cute.recast_tensor(tCrA_bf16_src[None, None, k_block], Uint32)\n fp_u32 = cute.recast_tensor(tCrA_dst[None, None, k_block], Uint32)\n n_pairs = cute.size(bf_u32)\n for i in cutlass.range_constexpr(n_pairs):\n fp_u32[i] = cvt_bf16x2_to_f16x2_via_f32(Uint32(bf_u32[i]))\n\n @cute.jit\n def _dequant_b_to_register(\n self,\n sB_packed: cute.Tensor,\n sB_sf: cute.Tensor,\n tCrB: cute.Tensor,\n tidx: Int32,\n stage_idx: Int32,\n k_tile_idx: Int32,\n k_block_idx: cutlass.Constexpr,\n ):\n \"\"\"Decode 2 int32 per thread per K-block into 16 fp16 fragment slots.\n\n Per the MMA partition for atom_layout (2,2,1) + *2 on N:\n\n tc_row = (lane % 4) * 2 in {0, 2, 4, 6}\n tc_col = lane // 4 in [0, 8)\n n_warp_idx = warp_idx // 2 in {0, 1}\n base_n = n_warp_idx * 8 + tc_col in [0, 16)\n\n Each thread covers:\n K = {tc_row, tc_row+1, tc_row+8, tc_row+9}\n N = {base_n, base_n+16, base_n+32, base_n+48}\n\n Two int32s per K-block per thread; sB_packed offsets:\n u32_0 @ sB_packed[k_block_idx, n_warp_idx * 64 + lane * 2 + 0, stage]\n u32_1 @ sB_packed[k_block_idx, n_warp_idx * 64 + lane * 2 + 1, stage]\n\n Byte layout inside each int32 (see ``_cute_dsl_pack_fp4_weight`` in\n ``flashinfer/gemm/gemm_bf16_fp4_cute_dsl.py``):\n u32_0:\n byte 0: K=tc_row, tc_row+1 at N=base_n -> (mma_i=0,1, nn=0)\n byte 1: K=tc_row+8, tc_row+9 at N=base_n -> (mma_i=2,3, nn=0)\n byte 2: K=tc_row, tc_row+1 at N=base_n+16 -> (mma_i=0,1, nn=1)\n byte 3: K=tc_row+8, tc_row+9 at N=base_n+16 -> (mma_i=2,3, nn=1)\n u32_1 mirrors with N=base_n+32 and N=base_n+48 (nn=2, nn=3).\n \"\"\"\n lane = tidx % Int32(32)\n warp = tidx // Int32(32)\n # n_warp_idx maps warp -> N-stripe. With (2,2,1) the 4 warps are\n # arranged as 2 M-warps * 2 N-warps, so n_warp_idx = warp // 2.\n # With (1,2,1) there are 2 warps total (no M-warp dim), so each\n # warp is its own N-stripe: n_warp_idx = warp. In general\n # n_warp_idx = warp // atom_layout[0].\n n_warp_idx = warp // Int32(self.atom_layout[0])\n tc_col = lane // Int32(4)\n base_n_in_tile = n_warp_idx * Int32(8) + tc_col\n\n # tile_N is built from tile_N // 64 independent packed 64-N blocks.\n # The hand-coded byte->fragment mapping below covers exactly one such\n # 64-N block (4 nn slots); for tile_N=128 we loop it over both blocks.\n # Block n_blk lives at sB_packed int32 columns [n_blk*128, +128), sB_sf\n # N-rows [n_blk*64, +64), and writes tCrB nn in [n_blk*4, +4). For\n # tile_N=64 this loops once.\n num_n_blocks = cutlass.const_expr(self.tile_shape_mnk[1] // 64)\n\n # _write_hmul2 captures tCrB / k_block_idx; nn and mma-row passed per\n # write. fp16 MMA writes fp16 directly; bf16 MMA goes via fp32 (no\n # packed f16x2 -> bf16x2 cvt on sm_100a).\n if cutlass.const_expr(self.use_fp16_mma == 1):\n\n def _write_hmul2(h2, scale_h2, mma_i_low, nn):\n scaled_h2 = half2_mul(h2, scale_h2)\n f_lo, f_hi = f16x2_unpack(scaled_h2)\n tCrB[mma_i_low, nn, k_block_idx] = f_lo\n tCrB[mma_i_low + 1, nn, k_block_idx] = f_hi\n else:\n\n def _write_hmul2(h2, scale_h2, mma_i_low, nn):\n scaled_h2 = half2_mul(h2, scale_h2)\n f_lo, f_hi = f16x2_to_f32x2(scaled_h2)\n tCrB[mma_i_low, nn, k_block_idx] = f_lo.to(self.b_compute_dtype)\n tCrB[mma_i_low + 1, nn, k_block_idx] = f_hi.to(self.b_compute_dtype)\n\n for n_blk in cutlass.range_constexpr(num_n_blocks):\n n_col_off = Int32(n_blk * 128) # int32 column offset of this 64-N block\n n_sf_off = Int32(n_blk * 64) # SF N-row offset of this 64-N block\n nn0 = n_blk * 4 # base tCrB N-fragment slot for this block\n\n # Single ld.shared.v2.u32 (8-byte load): u32_pos_base is always even\n # (= n_blk*128 + n_warp*64 + lane*2), so the offset is 8-byte aligned.\n u32_pos_base = n_col_off + n_warp_idx * Int32(64) + lane * Int32(2)\n smem_addr_b = get_smem_ptr_as_int32(\n sB_packed, sB_packed.layout((k_block_idx, u32_pos_base, stage_idx))\n )\n u32_0, u32_1 = ld_shared_v2_u32(smem_addr_b)\n\n # Per-group scale loads (S0E5M3). 4 distinct N positions per block.\n sf_n = base_n_in_tile + n_sf_off\n sf_byte_0 = Uint32(sB_sf[k_block_idx, sf_n + Int32(0), stage_idx])\n sf_byte_1 = Uint32(sB_sf[k_block_idx, sf_n + Int32(16), stage_idx])\n sf_byte_2 = Uint32(sB_sf[k_block_idx, sf_n + Int32(32), stage_idx])\n sf_byte_3 = Uint32(sB_sf[k_block_idx, sf_n + Int32(48), stage_idx])\n\n h0_a, h0_b, h0_c, h0_d = fp4_decode_4bytes(u32_0)\n h1_a, h1_b, h1_c, h1_d = fp4_decode_4bytes(u32_1)\n\n # S0E5M3 scale -> f16x2 broadcast in one mul.lo.u32. alpha is\n # applied once in the epilogue, so the scale never needs an f32 form.\n sc_n0 = cvt_s0e5m3_to_f16x2_broadcast(sf_byte_0)\n sc_n1 = cvt_s0e5m3_to_f16x2_broadcast(sf_byte_1)\n sc_n2 = cvt_s0e5m3_to_f16x2_broadcast(sf_byte_2)\n sc_n3 = cvt_s0e5m3_to_f16x2_broadcast(sf_byte_3)\n _write_hmul2(h0_a, sc_n0, 0, nn0 + 0)\n _write_hmul2(h0_b, sc_n0, 2, nn0 + 0)\n _write_hmul2(h0_c, sc_n1, 0, nn0 + 1)\n _write_hmul2(h0_d, sc_n1, 2, nn0 + 1)\n _write_hmul2(h1_a, sc_n2, 0, nn0 + 2)\n _write_hmul2(h1_b, sc_n2, 2, nn0 + 2)\n _write_hmul2(h1_c, sc_n3, 0, nn0 + 3)\n _write_hmul2(h1_d, sc_n3, 2, nn0 + 3)\n\n @cute.jit\n def wrapper(\n self,\n mA: cute.Tensor,\n mB_packed: cute.Tensor,\n mB_sf: cute.Tensor,\n mC: cute.Tensor,\n mPartial: cute.Tensor,\n mAlpha: cute.Tensor,\n l: cutlass.Constexpr,\n max_active_clusters: cutlass.Constexpr,\n current_stream,\n ):\n \"\"\"bf16 x fp4 wrapper for the FlashInfer compile interface.\n\n Args:\n mA: (m, k) input tensor A, bf16 or fp16.\n mB_packed: (k // 16, n * 2) int32 -- packed FP4.\n mB_sf: (k // 16, n) uint8 -- FP8-E4M3 per-group scales.\n mC: (m, n) output tensor C, bf16 or fp16.\n mPartial: (k_splits * m * n,) fp32 split-K partials; a small\n unused dummy when k_splits == 1.\n mAlpha: (1,) fp32 global scale.\n l: batch dimension (Constexpr); typically 1.\n max_active_clusters: Constexpr from get_max_active_clusters(1).\n current_stream: CUDA stream (TVM-FFI fake stream).\n \"\"\"\n if cutlass.const_expr(self.k_splits > 1 and l != 1):\n raise ValueError(\"k_splits > 1 requires l == 1\")\n m = cute.size(mA, mode=[0])\n k = cute.size(mA, mode=[1])\n n = cute.size(mC, mode=[1])\n k_tiles = k // _PACK_TILE_K\n n_packed = 2 * n\n k_sf_groups = k // self.GROUP_SIZE\n\n a_tensor = cute.make_tensor(\n mA.iterator,\n layout=cute.make_ordered_layout((m, k, l), order=(1, 0, 2)),\n )\n b_packed_tensor = cute.make_tensor(\n mB_packed.iterator,\n layout=cute.make_ordered_layout((k_tiles, n_packed, l), order=(1, 0, 2)),\n )\n b_sf_tensor = cute.make_tensor(\n mB_sf.iterator,\n layout=cute.make_ordered_layout((k_sf_groups, n, l), order=(1, 0, 2)),\n )\n c_tensor = cute.make_tensor(\n mC.iterator,\n layout=cute.make_ordered_layout((m, n, l), order=(1, 0, 2)),\n )\n\n self(\n a_tensor,\n b_packed_tensor,\n b_sf_tensor,\n c_tensor,\n mPartial,\n mAlpha,\n max_active_clusters,\n current_stream,\n )\n"},"diff":{"kind":"string","value":"--- flashinfer/gemm/kernels/cute_dsl/dense_gemm_bf16_fp4_blackwell.py\n+++ flashinfer/gemm/kernels/cute_dsl/dense_gemm_bf16_fp4_blackwell.py\n@@ -161,6 +161,8 @@\n enable_pdl: bool = True,\n tile_swizzle: int = 1,\n raster_along_m: bool = True,\n+ k_splits: int = 1,\n+ occupancy: int = 1,\n ):\n \"\"\"bf16 x fp4 kernel.\n \n@@ -188,6 +190,10 @@\n self.tile_swizzle = int(tile_swizzle)\n self.raster_along_m = bool(raster_along_m)\n self.enable_pdl = bool(enable_pdl)\n+ self.k_splits = int(k_splits)\n+ if self.k_splits < 1:\n+ raise ValueError(f\"k_splits must be >= 1 (got {k_splits})\")\n+ self.reduce_threads_per_cta = 256\n # Optional override for the epilogue tile shape.\n self.epi_tile_override = (\n tuple(epi_tile_override) if epi_tile_override is not None else None\n@@ -210,7 +216,12 @@\n f\"(got tile_K={self.tile_shape_mnk[2]})\"\n )\n \n- self.occupancy = 1\n+ # occupancy > 1 splits the SMEM budget across co-resident CTAs:\n+ # ab_stage shrinks but resident warps multiply, which is what\n+ # weight-bound grids need to cover DRAM latency (_compute_stages).\n+ self.occupancy = int(occupancy)\n+ if self.occupancy < 1:\n+ raise ValueError(f\"occupancy must be >= 1 (got {occupancy})\")\n # 2x2 atom layout: 4 MMA warps arranged as 2 M-warps x 2 N-warps.\n self.atom_layout = tuple(atom_layout)\n if self.atom_layout not in ((2, 2, 1), (1, 2, 1)):\n@@ -328,6 +339,7 @@\n b_packed: cute.Tensor,\n b_sf: cute.Tensor,\n c: cute.Tensor,\n+ partial: cute.Tensor,\n alpha: cute.Tensor,\n max_active_clusters: cutlass.Constexpr,\n stream: cuda.CUstream,\n@@ -401,6 +413,7 @@\n max_active_clusters,\n self.tile_swizzle,\n self.raster_along_m,\n+ self.k_splits,\n )\n \n @cute.struct\n@@ -444,6 +457,7 @@\n tma_tensor_b_sf,\n tma_atom_c,\n tma_tensor_c,\n+ partial,\n alpha,\n self.tiled_mma,\n self.cta_layout_mnk,\n@@ -454,12 +468,63 @@\n self.epi_smem_layout_staged,\n tile_sched_params,\n ).launch(\n+ # No cluster dims: even a 1x1x1 cluster launch goes through the\n+ # cluster work distributor, whose co-residency cap (2/SM where 3\n+ # CTAs fit on SM12x) silently defeats occupancy > 2 tactics.\n grid=grid,\n block=[self.threads_per_cta, 1, 1],\n- cluster=[1, 1, 1],\n stream=stream,\n use_pdl=self.enable_pdl,\n )\n+ if cutlass.const_expr(self.k_splits > 1):\n+ self._launch_partial_reduce(c, partial, stream)\n+ return\n+\n+ @cute.jit\n+ def _launch_partial_reduce(\n+ self,\n+ c: cute.Tensor,\n+ partial: cute.Tensor,\n+ stream: cuda.CUstream,\n+ ):\n+ \"\"\"Launch the split-K reduce, PDL-chained behind the GEMM grid.\"\"\"\n+ total = cute.size(c, mode=[0]) * cute.size(c, mode=[1])\n+ reduce_grid = (total + Int32(self.reduce_threads_per_cta) - Int32(1)) // Int32(\n+ self.reduce_threads_per_cta\n+ )\n+ self.kernel_partial_reduce(partial, c).launch(\n+ grid=[reduce_grid, 1, 1],\n+ block=[self.reduce_threads_per_cta, 1, 1],\n+ stream=stream,\n+ use_pdl=self.enable_pdl,\n+ )\n+\n+ @cute.kernel\n+ def kernel_partial_reduce(\n+ self,\n+ mPartial: cute.Tensor,\n+ mC_mnl: cute.Tensor,\n+ ):\n+ \"\"\"Sum the fp32 partials into C, one element per thread, in fixed\n+ split order for determinism.\"\"\"\n+ tidx, _, _ = cute.arch.thread_idx()\n+ bidx, _, _ = cute.arch.block_idx()\n+\n+ cute.arch.griddepcontrol_wait()\n+\n+ m_actual = cute.size(mC_mnl, mode=[0])\n+ n_actual = cute.size(mC_mnl, mode=[1])\n+ total = m_actual * n_actual\n+ mC_flat = cute.make_tensor(mC_mnl.iterator, cute.make_layout(total))\n+\n+ idx = Int32(bidx) * Int32(self.reduce_threads_per_cta) + tidx\n+ if idx < total:\n+ acc_sum = Float32(0.0)\n+ for s in cutlass.range_constexpr(self.k_splits):\n+ acc_sum = acc_sum + Float32(mPartial[Int32(s) * total + idx])\n+ mC_flat[idx] = acc_sum.to(self.c_dtype)\n+\n+ cute.arch.griddepcontrol_launch_dependents()\n return\n \n @cute.kernel\n@@ -473,6 +538,9 @@\n mB_sf_kn: cute.Tensor,\n tma_atom_c: cute.CopyAtom,\n mC_mnl: cute.Tensor,\n+ # fp32 split-K partials of shape (k_splits * m, n); an unused\n+ # dummy when k_splits == 1.\n+ mPartial: cute.Tensor,\n mAlpha: cute.Tensor,\n tiled_mma: cute.TiledMma,\n cta_layout_mnk: cute.Layout,\n@@ -689,15 +757,31 @@\n \n alpha_val = Float32(mAlpha[Int32(0)])\n \n+ if cutlass.const_expr(self.k_splits > 1):\n+ cC = cute.make_identity_tensor(\n+ cute.slice_(self.tile_shape_mnk, (None, None, 0))\n+ )\n+ tCcC = thr_mma.partition_C(cC)\n+\n while work_tile.is_valid_tile:\n tile_coord_mnl = work_tile.tile_idx\n- gC_mnl_slice = gC_mnl[(None, None, *tile_coord_mnl)]\n+ # k_splits <= k_tiles is checked at launch, so no split is empty.\n+ if cutlass.const_expr(self.k_splits > 1):\n+ tile_l, split_idx, k_start, k_len = self._split_work_krange(\n+ tile_coord_mnl[2], k_tile_cnt\n+ )\n+ else:\n+ tile_l = tile_coord_mnl[2]\n+ k_len = k_tile_cnt\n+ gC_mnl_slice = gC_mnl[\n+ (None, None, tile_coord_mnl[0], tile_coord_mnl[1], tile_l)\n+ ]\n accumulators.fill(0.0)\n \n mainloop_consumer_state.reset_count()\n \n peek_ab_full_status = cutlass.Boolean(1)\n- if mainloop_consumer_state.count < k_tile_cnt:\n+ if mainloop_consumer_state.count < k_len:\n peek_ab_full_status = mainloop_pipeline.consumer_try_wait(\n mainloop_consumer_state\n )\n@@ -728,7 +812,7 @@\n 0,\n )\n \n- for _k_tile in cutlass.range(0, k_tile_cnt - 1, 1, unroll=1):\n+ for _k_tile in cutlass.range(0, k_len - 1, 1, unroll=1):\n for k_block_idx in cutlass.range_constexpr(num_k_blocks):\n k_block_next = (\n 0 if k_block_idx + 1 == num_k_blocks else k_block_idx + 1\n@@ -898,135 +982,147 @@\n accumulators,\n )\n \n- # Epilogue: accumulator -> smem -> gmem via R2S (StMatrix.x4)\n- # + TMA bulk store.\n- copy_atom_r2s = sm90_utils.sm90_get_smem_store_op(\n- self.c_layout,\n- elem_ty_d=self.c_dtype,\n- elem_ty_acc=self.acc_dtype,\n- )\n-\n- copy_atom_C = cute.make_copy_atom(\n- cute.nvgpu.warp.StMatrix8x8x16bOp(\n- self.c_layout.is_m_major_c(),\n- 4,\n- ),\n- self.c_dtype,\n- )\n-\n- tiled_copy_C_Atom = cute.make_tiled_copy_C_atom(copy_atom_C, tiled_mma)\n-\n- tiled_copy_r2s = cute.make_tiled_copy_S(\n- copy_atom_r2s,\n- tiled_copy_C_Atom,\n- )\n-\n- thr_copy_r2s = tiled_copy_r2s.get_slice(tidx)\n- tRS_sD = thr_copy_r2s.partition_D(sC)\n- tRS_rAcc = tiled_copy_r2s.retile(accumulators)\n-\n- rD_shape = cute.shape(thr_copy_r2s.partition_S(sC))\n- tRS_rD_layout = cute.make_layout(rD_shape[:3])\n- tRS_rD = cute.make_rmem_tensor(tRS_rD_layout.shape, self.acc_dtype)\n-\n- sepi_for_tma_partition = cute.group_modes(sC, 0, 2)\n- tcgc_for_tma_partition = cute.zipped_divide(gC_mnl_slice, self.epi_tile)\n-\n- bSG_sD, bSG_gD = cute.nvgpu.cpasync.tma_partition(\n- tma_atom_c,\n- 0,\n- cute.make_layout(1),\n- sepi_for_tma_partition,\n- tcgc_for_tma_partition,\n- )\n-\n- # Epilogue: iterate (epi_m, epi_n) explicitly\n- # and use (mma_m, mma_n) mode indexing into tRS_rAcc so\n- # the loop works for any epi_tile_m / epi_tile_n. Also\n- # supports OOB-iteration skipping when m_actual < tile_M.\n- epi_rest_m = cute.size(tcgc_for_tma_partition, mode=[1, 0])\n- epi_rest_n = cute.size(tcgc_for_tma_partition, mode=[1, 1])\n- epi_tile_m = self.epi_tile[0]\n- epi_tile_n = self.epi_tile[1]\n- # mma_tile_{m,n} = per-mma-atom (M,N) size. tRS_rAcc has\n- # shape (atom_v, mma_m, mma_n); modes 1, 2 give the atom\n- # counts in M, N.\n- mma_tile_m = self.tile_shape_mnk[0] // cute.size(tRS_rAcc, mode=[1])\n- mma_tile_n = self.tile_shape_mnk[1] // cute.size(tRS_rAcc, mode=[2])\n- MmaMPerEpiM = epi_tile_m // mma_tile_m\n- MmaNPerEpiN = epi_tile_n // mma_tile_n\n-\n- tma_store_producer_group = pipeline.CooperativeGroup(\n- pipeline.Agent.Thread,\n- self.num_mma_warps * self.num_threads_per_warp,\n- )\n- tma_store_pipeline = pipeline.PipelineTmaStore.create(\n- num_stages=self.epi_stage,\n- producer_group=tma_store_producer_group,\n- )\n-\n- # Skip OOB epilogue iterations when actual M < tile_M.\n- m_actual = cute.size(mC_mnl, mode=[0])\n- cta_m_offset = tile_coord_mnl[0] * Int32(self.tile_shape_mnk[0])\n-\n- # kept_count cycles in lockstep with the TMA-store pipeline.\n- # epi_buffer = kept_count % num_stages stays in sync with\n- # producer_commit/acquire calls, regardless of how many\n- # iterations are skipped.\n- kept_count = 0\n- for epi_n in cutlass.range_constexpr(epi_rest_n):\n- for epi_m in cutlass.range_constexpr(epi_rest_m):\n- epi_m_global_start = cta_m_offset + Int32(epi_m * epi_tile_m)\n- if epi_m_global_start < m_actual:\n- # Copy this epi-tile's slice of acc -> tRS_rD\n- # using b12x-style (mma_m, mma_n) indexing.\n- for mma_n_in_epi in cutlass.range_constexpr(MmaNPerEpiN):\n- for mma_m_in_epi in cutlass.range_constexpr(\n- MmaMPerEpiM\n+ if cutlass.const_expr(self.k_splits > 1):\n+ # Store fp32 partials straight from registers; staging through\n+ # the output-dtype smem buffer would round each split early.\n+ m_actual = cute.size(mC_mnl, mode=[0])\n+ n_actual = cute.size(mC_mnl, mode=[1])\n+ cta_m_offset = tile_coord_mnl[0] * Int32(self.tile_shape_mnk[0])\n+ cta_n_offset = tile_coord_mnl[1] * Int32(self.tile_shape_mnk[1])\n+ for i in cutlass.range_constexpr(cute.size(accumulators)):\n+ r = cta_m_offset + Int32(tCcC[i][0])\n+ if r < m_actual:\n+ c = cta_n_offset + Int32(tCcC[i][1])\n+ mPartial[(split_idx * m_actual + r) * n_actual + c] = (\n+ alpha_val * accumulators[i]\n+ )\n+\n+ else:\n+ copy_atom_r2s = sm90_utils.sm90_get_smem_store_op(\n+ self.c_layout,\n+ elem_ty_d=self.c_dtype,\n+ elem_ty_acc=self.acc_dtype,\n+ )\n+\n+ copy_atom_C = cute.make_copy_atom(\n+ cute.nvgpu.warp.StMatrix8x8x16bOp(\n+ self.c_layout.is_m_major_c(),\n+ 4,\n+ ),\n+ self.c_dtype,\n+ )\n+\n+ tiled_copy_C_Atom = cute.make_tiled_copy_C_atom(\n+ copy_atom_C, tiled_mma\n+ )\n+\n+ tiled_copy_r2s = cute.make_tiled_copy_S(\n+ copy_atom_r2s,\n+ tiled_copy_C_Atom,\n+ )\n+\n+ thr_copy_r2s = tiled_copy_r2s.get_slice(tidx)\n+ tRS_sD = thr_copy_r2s.partition_D(sC)\n+ tRS_rAcc = tiled_copy_r2s.retile(accumulators)\n+\n+ rD_shape = cute.shape(thr_copy_r2s.partition_S(sC))\n+ tRS_rD_layout = cute.make_layout(rD_shape[:3])\n+ tRS_rD = cute.make_rmem_tensor(tRS_rD_layout.shape, self.acc_dtype)\n+\n+ sepi_for_tma_partition = cute.group_modes(sC, 0, 2)\n+ tcgc_for_tma_partition = cute.zipped_divide(\n+ gC_mnl_slice, self.epi_tile\n+ )\n+\n+ bSG_sD, bSG_gD = cute.nvgpu.cpasync.tma_partition(\n+ tma_atom_c,\n+ 0,\n+ cute.make_layout(1),\n+ sepi_for_tma_partition,\n+ tcgc_for_tma_partition,\n+ )\n+\n+ # Index tRS_rAcc by (mma_m, mma_n) modes so the loop\n+ # works for any epi_tile shape.\n+ epi_rest_m = cute.size(tcgc_for_tma_partition, mode=[1, 0])\n+ epi_rest_n = cute.size(tcgc_for_tma_partition, mode=[1, 1])\n+ epi_tile_m = self.epi_tile[0]\n+ epi_tile_n = self.epi_tile[1]\n+ # tRS_rAcc holds one fragment per MMA-atom tile, so dividing\n+ # the CTA tile by the (mma_m, mma_n) mode extents gives the\n+ # per-atom tile size.\n+ mma_tile_m = self.tile_shape_mnk[0] // cute.size(tRS_rAcc, mode=[1])\n+ mma_tile_n = self.tile_shape_mnk[1] // cute.size(tRS_rAcc, mode=[2])\n+ MmaMPerEpiM = epi_tile_m // mma_tile_m\n+ MmaNPerEpiN = epi_tile_n // mma_tile_n\n+\n+ tma_store_producer_group = pipeline.CooperativeGroup(\n+ pipeline.Agent.Thread,\n+ self.num_mma_warps * self.num_threads_per_warp,\n+ )\n+ tma_store_pipeline = pipeline.PipelineTmaStore.create(\n+ num_stages=self.epi_stage,\n+ producer_group=tma_store_producer_group,\n+ )\n+\n+ m_actual = cute.size(mC_mnl, mode=[0])\n+ cta_m_offset = tile_coord_mnl[0] * Int32(self.tile_shape_mnk[0])\n+\n+ # Skipped iterations must not advance the TMA-store pipeline,\n+ # so the stage index comes from kept_count rather than the\n+ # loop indices.\n+ kept_count = 0\n+ for epi_n in cutlass.range_constexpr(epi_rest_n):\n+ for epi_m in cutlass.range_constexpr(epi_rest_m):\n+ epi_m_global_start = cta_m_offset + Int32(\n+ epi_m * epi_tile_m\n+ )\n+ if epi_m_global_start < m_actual:\n+ for mma_n_in_epi in cutlass.range_constexpr(\n+ MmaNPerEpiN\n ):\n- mma_n = epi_n * MmaNPerEpiN + mma_n_in_epi\n- mma_m = epi_m * MmaMPerEpiM + mma_m_in_epi\n- tRS_rD_slice = tRS_rD[\n- (None, mma_m_in_epi, mma_n_in_epi)\n- ]\n- tRS_rAcc_slice = tRS_rAcc[(None, mma_m, mma_n)]\n- for elem_idx in cutlass.range_constexpr(\n- cute.size(tRS_rD_slice)\n+ for mma_m_in_epi in cutlass.range_constexpr(\n+ MmaMPerEpiM\n ):\n- tRS_rD_slice[elem_idx] = tRS_rAcc_slice[\n- elem_idx\n+ mma_n = epi_n * MmaNPerEpiN + mma_n_in_epi\n+ mma_m = epi_m * MmaMPerEpiM + mma_m_in_epi\n+ tRS_rD_slice = tRS_rD[\n+ (None, mma_m_in_epi, mma_n_in_epi)\n ]\n-\n- tRS_rD_out = cute.make_rmem_tensor(\n- tRS_rD_layout.shape, self.c_dtype\n- )\n- # Apply the global alpha here, once, on the\n- # fp32 accumulator (hoisted out of the\n- # per-K-block dequant): one rounding instead\n- # of folding alpha into every B scale.\n- acc_vec = tRS_rD.load()\n- tRS_rD_out.store((alpha_val * acc_vec).to(self.c_dtype))\n-\n- epi_buffer = kept_count % cute.size(tRS_sD, mode=[3])\n- cute.copy(\n- tiled_copy_r2s,\n- tRS_rD_out,\n- tRS_sD[(None, None, None, epi_buffer)],\n- )\n- cute.arch.fence_proxy(\"async.shared\", space=\"cta\")\n- self.epilog_sync_barrier.arrive_and_wait()\n-\n- if warp_idx == 0:\n+ tRS_rAcc_slice = tRS_rAcc[(None, mma_m, mma_n)]\n+ for elem_idx in cutlass.range_constexpr(\n+ cute.size(tRS_rD_slice)\n+ ):\n+ tRS_rD_slice[elem_idx] = tRS_rAcc_slice[\n+ elem_idx\n+ ]\n+\n+ tRS_rD_out = cute.make_rmem_tensor(\n+ tRS_rD_layout.shape, self.c_dtype\n+ )\n+ acc_vec = tRS_rD.load()\n+ tRS_rD_out.store((alpha_val * acc_vec).to(self.c_dtype))\n+\n+ epi_buffer = kept_count % cute.size(tRS_sD, mode=[3])\n cute.copy(\n- tma_atom_c,\n- bSG_sD[(None, epi_buffer)],\n- bSG_gD[(None, (epi_m, epi_n))],\n+ tiled_copy_r2s,\n+ tRS_rD_out,\n+ tRS_sD[(None, None, None, epi_buffer)],\n )\n- tma_store_pipeline.producer_commit()\n- tma_store_pipeline.producer_acquire()\n- kept_count = kept_count + 1\n-\n- tma_store_pipeline.producer_tail()\n+ cute.arch.fence_proxy(\"async.shared\", space=\"cta\")\n+ self.epilog_sync_barrier.arrive_and_wait()\n+\n+ if warp_idx == 0:\n+ cute.copy(\n+ tma_atom_c,\n+ bSG_sD[(None, epi_buffer)],\n+ bSG_gD[(None, (epi_m, epi_n))],\n+ )\n+ tma_store_pipeline.producer_commit()\n+ tma_store_pipeline.producer_acquire()\n+ kept_count = kept_count + 1\n+\n+ tma_store_pipeline.producer_tail()\n \n tile_sched.advance_to_next_work()\n work_tile = tile_sched.get_current_work()\n@@ -1036,19 +1132,25 @@\n cute.arch.setmaxregister_decrease(self.load_register_requirement)\n while work_tile.is_valid_tile:\n tile_coord_mnl = work_tile.tile_idx\n- tAgA_mkl = tAgA[(None, tile_coord_mnl[0], None, tile_coord_mnl[2])]\n- tBpacked_g_kn = tBpacked_g[\n- (None, None, tile_coord_mnl[1], tile_coord_mnl[2])\n- ]\n- tBsf_g_kn = tBsf_g[(None, None, tile_coord_mnl[1], tile_coord_mnl[2])]\n+ if cutlass.const_expr(self.k_splits > 1):\n+ tile_l, split_idx, k_start, k_len = self._split_work_krange(\n+ tile_coord_mnl[2], k_tile_cnt\n+ )\n+ else:\n+ tile_l = tile_coord_mnl[2]\n+ k_start = Int32(0)\n+ k_len = k_tile_cnt\n+ tAgA_mkl = tAgA[(None, tile_coord_mnl[0], None, tile_l)]\n+ tBpacked_g_kn = tBpacked_g[(None, None, tile_coord_mnl[1], tile_l)]\n+ tBsf_g_kn = tBsf_g[(None, None, tile_coord_mnl[1], tile_l)]\n mainloop_producer_state.reset_count()\n- for _k_tile in cutlass.range(0, k_tile_cnt, 1, unroll=1):\n+ for _k_tile in cutlass.range(0, k_len, 1, unroll=1):\n mainloop_pipeline.producer_acquire(mainloop_producer_state)\n barrier_ptr = mainloop_pipeline.producer_get_barrier(\n mainloop_producer_state\n )\n \n- tAgA_k = tAgA_mkl[(None, mainloop_producer_state.count)]\n+ tAgA_k = tAgA_mkl[(None, k_start + mainloop_producer_state.count)]\n tAsA_pipe = tAsA[(None, mainloop_producer_state.index)]\n cute.copy(\n tma_atom_a,\n@@ -1058,7 +1160,9 @@\n mcast_mask=a_mcast_mask,\n )\n \n- tBpacked_g_k = tBpacked_g_kn[(None, mainloop_producer_state.count)]\n+ tBpacked_g_k = tBpacked_g_kn[\n+ (None, k_start + mainloop_producer_state.count)\n+ ]\n tBpacked_s_pipe = tBpacked_s[(None, mainloop_producer_state.index)]\n cute.copy(\n tma_atom_b_packed,\n@@ -1068,7 +1172,9 @@\n mcast_mask=b_mcast_mask,\n )\n \n- tBsf_g_k = tBsf_g_kn[(None, mainloop_producer_state.count)]\n+ tBsf_g_k = tBsf_g_kn[\n+ (None, k_start + mainloop_producer_state.count)\n+ ]\n tBsf_s_pipe = tBsf_s[(None, mainloop_producer_state.index)]\n cute.copy(\n tma_atom_b_sf,\n@@ -1215,10 +1321,18 @@\n max_active_clusters: cutlass.Constexpr,\n tile_swizzle: cutlass.Constexpr = 1,\n raster_along_m: cutlass.Constexpr = True,\n+ k_splits: cutlass.Constexpr = 1,\n ):\n c_shape = cute.slice_(tile_shape_mnk, (None, None, 0))\n gc = cute.zipped_divide(c, tiler=c_shape)\n num_ctas_mnl = gc[(0, (None, None, None))].shape\n+ # Split-K reuses the scheduler's otherwise size-1 batch (L) mode.\n+ if cutlass.const_expr(k_splits > 1):\n+ num_ctas_mnl = (\n+ num_ctas_mnl[0],\n+ num_ctas_mnl[1],\n+ num_ctas_mnl[2] * k_splits,\n+ )\n cluster_shape_mnl = (1, 1, 1)\n tile_sched_params = utils.PersistentTileSchedulerParams(\n num_ctas_mnl,\n@@ -1267,6 +1381,18 @@\n num_multicast=mcast_dim,\n )\n return tma_atom, tma_tensor\n+\n+ @cute.jit\n+ def _split_work_krange(self, tile_coord_l, k_tile_cnt):\n+ \"\"\"Compute the balanced K-tile range of one split.\n+\n+ Producer and consumer branches both call this so their ranges agree.\n+ \"\"\"\n+ split_idx = Int32(tile_coord_l) % Int32(self.k_splits)\n+ tile_l = Int32(tile_coord_l) // Int32(self.k_splits)\n+ k_start = split_idx * k_tile_cnt // Int32(self.k_splits)\n+ k_stop = (split_idx + Int32(1)) * k_tile_cnt // Int32(self.k_splits)\n+ return tile_l, split_idx, k_start, k_stop - k_start\n \n @cute.jit\n def _cvt_a_bf16_to_fp16_one_k_block(\n@@ -1412,6 +1538,7 @@\n mB_packed: cute.Tensor,\n mB_sf: cute.Tensor,\n mC: cute.Tensor,\n+ mPartial: cute.Tensor,\n mAlpha: cute.Tensor,\n l: cutlass.Constexpr,\n max_active_clusters: cutlass.Constexpr,\n@@ -1424,11 +1551,15 @@\n mB_packed: (k // 16, n * 2) int32 -- packed FP4.\n mB_sf: (k // 16, n) uint8 -- FP8-E4M3 per-group scales.\n mC: (m, n) output tensor C, bf16 or fp16.\n+ mPartial: (k_splits * m * n,) fp32 split-K partials; a small\n+ unused dummy when k_splits == 1.\n mAlpha: (1,) fp32 global scale.\n l: batch dimension (Constexpr); typically 1.\n max_active_clusters: Constexpr from get_max_active_clusters(1).\n current_stream: CUDA stream (TVM-FFI fake stream).\n \"\"\"\n+ if cutlass.const_expr(self.k_splits > 1 and l != 1):\n+ raise ValueError(\"k_splits > 1 requires l == 1\")\n m = cute.size(mA, mode=[0])\n k = cute.size(mA, mode=[1])\n n = cute.size(mC, mode=[1])\n@@ -1458,6 +1589,7 @@\n b_packed_tensor,\n b_sf_tensor,\n c_tensor,\n+ mPartial,\n mAlpha,\n max_active_clusters,\n current_stream,"},"lines_added":{"kind":"number","value":270,"string":"270"},"lines_removed":{"kind":"number","value":138,"string":"138"},"files_in_commit":{"kind":"number","value":2,"string":"2"},"models_mentioned":{"kind":"list like","value":["qwen","llama"],"string":"[\n \"qwen\",\n \"llama\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["RTX5080"],"string":"[\n \"RTX5080\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":["1.011x","1.11x","1.014x"],"string":"[\n \"1.011x\",\n \"1.11x\",\n \"1.014x\"\n]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cute_dsl kernel file from flashinfer (flashinfer/gemm/kernels/cute_dsl/dense_gemm_bf16_fp4_blackwell.py).\n\nGoal: perf(gemm): split-K, occupancy, and m=1 stream-GEMV decode tactics for mm_bf16_fp4\nTarget hardware: RTX5080\nTarget models: qwen, llama\n\nCurrent file:\n```python\n# Copyright (c) 2025 - 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.\n# SPDX-License-Identifier: BSD-3-Clause\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions are met:\n#\n# 1. Redistributions of source code must retain the above copyright notice, this\n# list of conditions and the following disclaimer.\n#\n# 2. Redistributions in binary form must reproduce the above copyright notice,\n# this list of conditions and the following disclaimer in the documentation\n# and/or other materials provided with the distribution.\n#\n# 3. Neither the name of the copyright holder nor the names of its\n# contributors may be used to endorse or promote products derived from\n# this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n\"\"\"bf16 x fp4 dense GEMM for Blackwell (SM100/103/120/121).\n\nBuilt on top of ``dense_gemm_bf16_blackwell.py`` from cutlass examples at\nhttps://github.com/NVIDIA/cutlass/blob/main/examples/python/CuTeDSL/cute/blackwell_geforce/kernel/dense_gemm/dense_gemm.py\n\"\"\"\n\nfrom typing import Optional, Tuple, Type\n\nimport cuda.bindings.driver as cuda\n\nimport cutlass\nimport cutlass.cute as cute\nimport cutlass.pipeline as pipeline\nimport cutlass.utils as utils\nimport cutlass.utils.hopper_helpers as sm90_utils\nfrom cutlass import Float32, Int32, Uint32\n\nfrom ....cute_dsl.fp4_common import (\n cvt_s0e5m3_to_f16x2_broadcast,\n f16x2_to_f32x2,\n fp4_decode_4bytes,\n get_smem_ptr_as_int32,\n half2_mul,\n ld_shared_v2_u32,\n)\nfrom cutlass._mlir import ir\nfrom cutlass._mlir.dialects import llvm\nfrom cutlass._mlir.extras import types as T\nfrom cutlass.cutlass_dsl import dsl_user_op\n\n\n@dsl_user_op\ndef cvt_bf16x2_to_f16x2_via_f32(packed_bf16x2: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Packed bf16x2 (u32) -> f16x2 (u32) via f32 intermediate.\n\n Used by the fp16-MMA path (use_fp16_mma=1) to convert A's ldmatrix\n output (bf16 bit pattern from sA) to fp16 bit pattern for the fp16\n MMA inputs. Direct ``cvt.rn.f16x2.bf16x2`` is rejected by ptxas on\n sm_100a / CUDA 13.1; this packed via-f32 path is 4 PTX instrs per\n pair (mov.b32 unpack + 2x cvt.f32.bf16 + 1x cvt.rn.f16x2.f32).\n \"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(packed_bf16x2).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 b_lo, b_hi;\n .reg .f32 f_lo, f_hi;\n mov.b32 {b_lo, b_hi}, $1;\n cvt.f32.bf16 f_lo, b_lo;\n cvt.f32.bf16 f_hi, b_hi;\n cvt.rn.f16x2.f32 $0, f_hi, f_lo;\n }\n \"\"\",\n \"=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef f16x2_unpack(\n packed_h2: Uint32, *, loc=None, ip=None\n) -> Tuple[\"cutlass.Float16\", \"cutlass.Float16\"]:\n \"\"\"Unpack f16x2 (u32) into (f16_lo, f16_hi). Free at HW level --\n just a register-rename (mov.b32 {h_lo, h_hi}, packed). Used by the\n fp16-MMA path to bypass the f16->f32->bf16 cvt chain that the\n default bf16-MMA path needs after hmul2.\"\"\"\n from cutlass import Float16\n\n res = llvm.inline_asm(\n ir.Type.parse(\"!llvm.struct<(f16, f16)>\"),\n [Uint32(packed_h2).ir_value(loc=loc, ip=ip)],\n \"mov.b32 {$0, $1}, $2;\",\n \"=h,=h,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n return (\n Float16(llvm.extractvalue(T.f16(), res, [0], loc=loc, ip=ip)),\n Float16(llvm.extractvalue(T.f16(), res, [1], loc=loc, ip=ip)),\n )\n\n\n# FP4 weight packing constants (must match _cute_dsl_pack_fp4_weight in\n# flashinfer/gemm/gemm_bf16_fp4_cute_dsl.py).\n_PACK_TILE_K: cutlass.Constexpr = 16\n_PACK_TILE_N: cutlass.Constexpr = 64\n_PACK_INTS_PER_TILE: cutlass.Constexpr = 128 # 128 int32 per (16K x 64N) block\n\n\nclass BlackwellDenseGemmBf16Fp4Kernel:\n \"\"\"Warp-MMA dense GEMM for Blackwell, FP4-weight A bf16/fp16 input.\n\n A: (M, K, L) bf16/fp16.\n B: (K // 16, N * 2, L) int32 -- packed FP4 (see prepare).\n B_sf: (K // 16, N, L) uint8 -- per-group scales (S0E5M3).\n alpha: (1,) fp32 -- global scalar scale.\n C: (M, N, L) bf16/fp16; fp32 accumulator cast at write.\n\n \"\"\"\n\n GROUP_SIZE: cutlass.Constexpr = 16\n\n def __init__(\n self,\n acc_dtype,\n tile_shape_mnk,\n epi_stage: int = 4,\n pipeline_depth: int = 1,\n atom_layout: Tuple[int, int, int] = (2, 2, 1),\n epi_tile_override: Optional[Tuple[int, int]] = None,\n # 1 = fp16 MMA (default): MmaF16BF16Op uses Float16. Dequant writes\n # fp16 directly to tCrB (skipping the f16->f32->bf16 cvt chain\n # the bf16 path needs after hmul2). A is bf16 in SMEM ->\n # ldmatrix into bf16 staging fragment -> in-register packed\n # bf16->fp16 cvt -> fp16 tCrA. Slightly *more* accurate than\n # bf16 MMA for well-behaved inputs since fp16's 10-bit mantissa\n # beats bf16's 7-bit at the multiply step; accumulator stays\n # fp32 in both modes.\n # 0 = bf16 MMA: original path. Safer for workloads with very\n # large activation magnitudes (|A| > ~30000) since bf16's\n # wider exponent range avoids saturation in the A cvt.\n use_fp16_mma: int = 1,\n enable_pdl: bool = True,\n tile_swizzle: int = 1,\n raster_along_m: bool = True,\n ):\n \"\"\"bf16 x fp4 kernel.\n\n Args:\n acc_dtype: accumulator dtype (always Float32 for this kernel).\n tile_shape_mnk: CTA tile shape.\n epi_stage: TMA-store pipeline depth. Default 4 balances\n cross-tile overlap (epi_stage > 1 lets next-tile compute\n overlap with this-tile store) against SMEM available for\n ab_stage (deeper ab_stage hides TMA-load latency, which\n dominates the small-M shape's stalls). At M=4 with the\n default 64-CTA grid on 148 SMs, each SM gets at most\n one tile, so epi_stage > 1 doesn't help much locally;\n we keep 2-4 to preserve persistent-scheduler benefits\n at larger M.\n \"\"\"\n self.acc_dtype = acc_dtype\n self.cluster_shape_mnk = (1, 1, 1)\n self.tile_shape_mnk = tuple(tile_shape_mnk)\n self.epi_stage_target = int(epi_stage)\n if self.epi_stage_target < 1:\n raise ValueError(f\"epi_stage must be >= 1 (got {epi_stage})\")\n self.pipeline_depth = int(pipeline_depth)\n self.use_fp16_mma = int(use_fp16_mma)\n self.tile_swizzle = int(tile_swizzle)\n self.raster_along_m = bool(raster_along_m)\n self.enable_pdl = bool(enable_pdl)\n # Optional override for the epilogue tile shape.\n self.epi_tile_override = (\n tuple(epi_tile_override) if epi_tile_override is not None else None\n )\n self.tiled_mma = None\n # num_mcast_ctas_a / num_mcast_ctas_b are derived from the cluster\n # shape in __call__ before use; left unset here so their type is\n # inferred from that assignment (matches the sibling kernels).\n self.is_a_mcast = False\n self.is_b_mcast = False\n\n if self.tile_shape_mnk[1] % _PACK_TILE_N != 0:\n raise ValueError(\n f\"bf16 x fp4 requires tile_N % {_PACK_TILE_N} == 0 \"\n f\"(got tile_N={self.tile_shape_mnk[1]})\"\n )\n if self.tile_shape_mnk[2] % _PACK_TILE_K != 0:\n raise ValueError(\n f\"bf16 x fp4 requires tile_K % {_PACK_TILE_K} == 0 \"\n f\"(got tile_K={self.tile_shape_mnk[2]})\"\n )\n\n self.occupancy = 1\n # 2x2 atom layout: 4 MMA warps arranged as 2 M-warps x 2 N-warps.\n self.atom_layout = tuple(atom_layout)\n if self.atom_layout not in ((2, 2, 1), (1, 2, 1)):\n raise ValueError(\n f\"Unsupported atom_layout {self.atom_layout!r}; \"\n \"expected (2,2,1) or (1,2,1)\"\n )\n self.num_mma_warps = (\n self.atom_layout[0] * self.atom_layout[1] * self.atom_layout[2]\n )\n self.num_dma_warps = 1\n self.num_threads_per_warp = 32\n self.threads_per_cta = (\n self.num_mma_warps + self.num_dma_warps\n ) * self.num_threads_per_warp\n # SM100/103 expose >= SM120 SMEM/CTA\n self.smem_capacity = utils.get_smem_capacity_in_bytes(\"sm_120\")\n\n self.ab_stage = None\n self.epi_stage = None\n\n self.a_smem_layout_staged = None\n self.b_smem_layout_staged = None\n self.epi_smem_layout_staged = None\n self.buffer_align_bytes = 1024\n\n self.epilog_sync_barrier = pipeline.NamedBarrier(\n barrier_id=2,\n num_threads=self.num_mma_warps * self.num_threads_per_warp,\n )\n self.load_register_requirement = 40\n self.mma_register_requirement = 232\n\n def _setup_attributes(self):\n self.mma_inst_mnk = (16, 8, 16)\n # MmaF16BF16Op accepts ab_dtype in {Float16, BFloat16}. We pick via\n # b_compute_dtype so use_fp16_mma=1 swings the whole MMA to fp16\n # (both A and B fragments will be fp16-typed).\n op = cute.nvgpu.warp.MmaF16BF16Op(\n self.b_compute_dtype,\n self.acc_dtype,\n self.mma_inst_mnk,\n )\n tC = cute.make_layout(self.atom_layout)\n permutation_mnk = (\n self.atom_layout[0] * self.mma_inst_mnk[0],\n # *2 trick: each warp covers two atom-N tiles in one ldmatrix.x4\n self.atom_layout[1] * self.mma_inst_mnk[1] * 2,\n self.atom_layout[2] * self.mma_inst_mnk[2],\n )\n self.tiled_mma = cute.make_tiled_mma(\n op,\n tC,\n permutation_mnk=permutation_mnk,\n )\n\n self.cta_layout_mnk = cute.make_layout(self.cluster_shape_mnk)\n\n self.num_mcast_ctas_a = self.cluster_shape_mnk[1]\n self.num_mcast_ctas_b = self.cluster_shape_mnk[0]\n self.is_a_mcast = self.num_mcast_ctas_a > 1\n self.is_b_mcast = self.num_mcast_ctas_b > 1\n\n self.epi_tile = sm90_utils.compute_tile_shape_or_override(\n self.tile_shape_mnk,\n self.c_dtype,\n is_cooperative=False,\n epi_tile_override=self.epi_tile_override,\n )\n\n # B-side smem is packed int32 (4 bytes per logical FP4\n # pair). Stage budget uses int32 B + uint8 scales; bf16 phantom\n # layout is only used by partition_B/make_fragment_B.\n self.ab_stage, self.epi_stage = self._compute_stages(\n self.tile_shape_mnk,\n self.a_dtype,\n self.epi_tile,\n self.c_dtype,\n self.smem_capacity,\n self.occupancy,\n self.GROUP_SIZE,\n self.epi_stage_target,\n )\n\n if self.ab_stage == 0:\n raise RuntimeError(\n \"ab_stage == 0: not enough shared memory for this tile shape \"\n f\"({self.tile_shape_mnk}) at occupancy {self.occupancy}.\"\n )\n\n (\n self.a_smem_layout_staged,\n self.b_packed_smem_layout_staged,\n self.b_sf_smem_layout_staged,\n self.b_bf16_logical_layout,\n self.epi_smem_layout_staged,\n ) = self._make_smem_layouts(\n self.tile_shape_mnk,\n self.epi_tile,\n self.a_dtype,\n self.a_layout,\n self.b_compute_dtype,\n self.b_layout_compute,\n self.ab_stage,\n self.c_dtype,\n self.c_layout,\n self.epi_stage,\n self.GROUP_SIZE,\n )\n\n @cute.jit\n def __call__(\n self,\n a: cute.Tensor,\n b_packed: cute.Tensor,\n b_sf: cute.Tensor,\n c: cute.Tensor,\n alpha: cute.Tensor,\n max_active_clusters: cutlass.Constexpr,\n stream: cuda.CUstream,\n ):\n from cutlass import Float16\n\n self.a_dtype = a.element_type\n # MMA operand dtype: bf16 by default matches A, or fp16 when\n # use_fp16_mma=1 (lets us skip the f16->f32->bf16 cvt chain on B).\n if cutlass.const_expr(self.use_fp16_mma == 1):\n self.b_compute_dtype = Float16\n else:\n self.b_compute_dtype = a.element_type\n self.c_dtype = c.element_type\n\n self.a_layout = utils.LayoutEnum.from_tensor(a)\n self.b_layout_compute = utils.LayoutEnum.ROW_MAJOR\n self.c_layout = utils.LayoutEnum.from_tensor(c)\n\n if cutlass.const_expr(self.a_dtype.width != 16):\n raise TypeError(f\"a_dtype must be 16-bit (bf16/fp16), got {self.a_dtype}\")\n if cutlass.const_expr(self.a_dtype != self.c_dtype):\n raise TypeError(\n f\"a_dtype and c_dtype must match, got {self.a_dtype} vs {self.c_dtype}\"\n )\n\n self._setup_attributes()\n\n tma_atom_a, tma_tensor_a = self._make_tma_atoms_and_tensors(\n a,\n self.a_smem_layout_staged,\n (self.tile_shape_mnk[0], self.tile_shape_mnk[2]),\n 1,\n )\n\n # Packed B TMA: tile is (tile_K // 16, 2 * tile_N) int32.\n b_packed_tma_tile = (\n self.tile_shape_mnk[2] // _PACK_TILE_K,\n 2 * self.tile_shape_mnk[1],\n )\n tma_atom_b_packed, tma_tensor_b_packed = self._make_tma_atoms_and_tensors(\n b_packed,\n self.b_packed_smem_layout_staged,\n b_packed_tma_tile,\n 1,\n )\n\n # B scale TMA: tile is (tile_K // group_size, tile_N) uint8.\n # Small per-tile load -- this replaces ``tile_K // group_size``\n # gmem-direct loads per thread per K-block in the dequant path.\n b_sf_tma_tile = (\n self.tile_shape_mnk[2] // self.GROUP_SIZE,\n self.tile_shape_mnk[1],\n )\n tma_atom_b_sf, tma_tensor_b_sf = self._make_tma_atoms_and_tensors(\n b_sf,\n self.b_sf_smem_layout_staged,\n b_sf_tma_tile,\n 1,\n )\n\n tma_atom_c, tma_tensor_c = self._make_tma_store_atoms_and_tensors(\n c,\n self.epi_smem_layout_staged,\n self.epi_tile,\n )\n\n tile_sched_params, grid = self._compute_grid(\n c,\n self.tile_shape_mnk,\n max_active_clusters,\n self.tile_swizzle,\n self.raster_along_m,\n )\n\n @cute.struct\n class SharedStorage:\n mainloop_pipeline_array_ptr: cute.struct.MemRange[\n cutlass.Int64, self.ab_stage * 2\n ]\n sA: cute.struct.Align[\n cute.struct.MemRange[\n self.a_dtype, cute.cosize(self.a_smem_layout_staged)\n ],\n self.buffer_align_bytes,\n ]\n sB_packed: cute.struct.Align[\n cute.struct.MemRange[\n cutlass.Int32, cute.cosize(self.b_packed_smem_layout_staged)\n ],\n self.buffer_align_bytes,\n ]\n sB_sf: cute.struct.Align[\n cute.struct.MemRange[\n cutlass.Uint8, cute.cosize(self.b_sf_smem_layout_staged)\n ],\n self.buffer_align_bytes,\n ]\n sC: cute.struct.Align[\n cute.struct.MemRange[\n self.c_dtype, cute.cosize(self.epi_smem_layout_staged)\n ],\n self.buffer_align_bytes,\n ]\n\n self.shared_storage = SharedStorage\n\n self.kernel(\n tma_atom_a,\n tma_tensor_a,\n tma_atom_b_packed,\n tma_tensor_b_packed,\n tma_atom_b_sf,\n tma_tensor_b_sf,\n tma_atom_c,\n tma_tensor_c,\n alpha,\n self.tiled_mma,\n self.cta_layout_mnk,\n self.a_smem_layout_staged,\n self.b_packed_smem_layout_staged,\n self.b_sf_smem_layout_staged,\n self.b_bf16_logical_layout,\n self.epi_smem_layout_staged,\n tile_sched_params,\n ).launch(\n grid=grid,\n block=[self.threads_per_cta, 1, 1],\n cluster=[1, 1, 1],\n stream=stream,\n use_pdl=self.enable_pdl,\n )\n return\n\n @cute.kernel\n def kernel(\n self,\n tma_atom_a: cute.CopyAtom,\n mA_mkl: cute.Tensor,\n tma_atom_b_packed: cute.CopyAtom,\n mB_packed_kn: cute.Tensor,\n tma_atom_b_sf: cute.CopyAtom,\n mB_sf_kn: cute.Tensor,\n tma_atom_c: cute.CopyAtom,\n mC_mnl: cute.Tensor,\n mAlpha: cute.Tensor,\n tiled_mma: cute.TiledMma,\n cta_layout_mnk: cute.Layout,\n a_smem_layout_staged: cute.ComposedLayout,\n b_packed_smem_layout_staged: cute.Layout,\n b_sf_smem_layout_staged: cute.Layout,\n b_bf16_logical_layout: cute.ComposedLayout,\n epi_smem_layout_staged: cute.ComposedLayout,\n tile_sched_params: utils.PersistentTileSchedulerParams,\n ):\n tidx, _, _ = cute.arch.thread_idx()\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n\n # Prefetch TMA descriptors from warp 0.\n if warp_idx == 0:\n cute.nvgpu.cpasync.prefetch_descriptor(tma_atom_a)\n cute.nvgpu.cpasync.prefetch_descriptor(tma_atom_b_packed)\n cute.nvgpu.cpasync.prefetch_descriptor(tma_atom_b_sf)\n cute.nvgpu.cpasync.prefetch_descriptor(tma_atom_c)\n\n cta_rank_in_cluster = cute.arch.make_warp_uniform(\n cute.arch.block_idx_in_cluster()\n )\n cluster_coord_mnk = cta_layout_mnk.get_flat_coord(cta_rank_in_cluster)\n\n a_mcast_mask = cute.make_layout_image_mask(\n cta_layout_mnk, cluster_coord_mnk, mode=1\n )\n b_mcast_mask = cute.make_layout_image_mask(\n cta_layout_mnk, cluster_coord_mnk, mode=0\n )\n a_mcast_mask = a_mcast_mask if self.is_a_mcast else 0\n b_mcast_mask = b_mcast_mask if self.is_b_mcast else 0\n\n a_smem_layout = cute.slice_(a_smem_layout_staged, (None, None, 0))\n b_packed_smem_layout = cute.slice_(b_packed_smem_layout_staged, (None, None, 0))\n b_sf_smem_layout = cute.slice_(b_sf_smem_layout_staged, (None, None, 0))\n tma_copy_bytes = (\n cute.size_in_bytes(self.a_dtype, a_smem_layout)\n + cute.size_in_bytes(cutlass.Int32, b_packed_smem_layout)\n + cute.size_in_bytes(cutlass.Uint8, b_sf_smem_layout)\n )\n\n smem = cutlass.utils.SmemAllocator()\n storage = smem.allocate(self.shared_storage)\n\n mainloop_pipeline_array_ptr = storage.mainloop_pipeline_array_ptr.data_ptr()\n\n mainloop_pipeline_producer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread\n )\n mcast_size = self.num_mcast_ctas_a + self.num_mcast_ctas_b - 1\n consumer_arrive_cnt = mcast_size * self.num_mma_warps\n mainloop_pipeline_consumer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread, consumer_arrive_cnt\n )\n\n cta_layout_vmnk = cute.make_layout((1, *cta_layout_mnk.shape))\n mainloop_pipeline = pipeline.PipelineTmaAsync.create(\n num_stages=self.ab_stage,\n producer_group=mainloop_pipeline_producer_group,\n consumer_group=mainloop_pipeline_consumer_group,\n tx_count=tma_copy_bytes,\n barrier_storage=mainloop_pipeline_array_ptr,\n cta_layout_vmnk=cta_layout_vmnk,\n )\n\n if cute.size(self.cluster_shape_mnk) > 1:\n cute.arch.cluster_arrive_relaxed()\n\n sA = storage.sA.get_tensor(\n a_smem_layout_staged.outer, swizzle=a_smem_layout_staged.inner\n )\n # Both B-side tensors are plain (non-swizzled) staged layouts.\n sB_packed = storage.sB_packed.get_tensor(b_packed_smem_layout_staged)\n sB_sf = storage.sB_sf.get_tensor(b_sf_smem_layout_staged)\n sC = storage.sC.get_tensor(\n epi_smem_layout_staged.outer, swizzle=epi_smem_layout_staged.inner\n )\n\n gA_mkl = cute.local_tile(\n mA_mkl,\n cute.slice_(self.tile_shape_mnk, (None, 0, None)),\n (None, None, None),\n )\n # Packed B: (K // 16, N * 2, L); tile = (tile_K // 16, 2 * tile_N).\n b_packed_tile_shape = (\n self.tile_shape_mnk[2] // _PACK_TILE_K,\n 2 * self.tile_shape_mnk[1],\n )\n gB_packed_kn = cute.local_tile(\n mB_packed_kn,\n b_packed_tile_shape,\n (None, None, None),\n )\n # Scales: (K // 16, N, L); per-tile slice has shape\n # (tile_K // group_size, tile_N) = (tile_K // 16, tile_N). Dequant\n # indexes directly per K-block + per N-coord.\n gB_sf_kn = cute.local_tile(\n mB_sf_kn,\n (self.tile_shape_mnk[2] // self.GROUP_SIZE, self.tile_shape_mnk[1]),\n (None, None, None),\n )\n gC_mnl = cute.local_tile(\n mC_mnl,\n cute.slice_(self.tile_shape_mnk, (None, None, 0)),\n (None, None, None),\n )\n\n thr_mma = tiled_mma.get_slice(tidx)\n\n # TMA partition for A: (m, k) -> per-CTA partition.\n a_cta_layout = cute.make_layout(cute.slice_(cta_layout_mnk, (0, None, 0)).shape)\n a_cta_crd = cluster_coord_mnk[1]\n tAsA, tAgA = cute.nvgpu.cpasync.tma_partition(\n tma_atom_a,\n a_cta_crd,\n a_cta_layout,\n cute.group_modes(sA, 0, 2),\n cute.group_modes(gA_mkl, 0, 2),\n )\n\n # TMA partition for B (packed int32).\n b_cta_layout = cute.make_layout(cute.slice_(cta_layout_mnk, (None, 0, 0)).shape)\n b_cta_crd = cluster_coord_mnk[0]\n tBpacked_s, tBpacked_g = cute.nvgpu.cpasync.tma_partition(\n tma_atom_b_packed,\n b_cta_crd,\n b_cta_layout,\n cute.group_modes(sB_packed, 0, 2),\n cute.group_modes(gB_packed_kn, 0, 2),\n )\n\n # TMA partition for B_sf (uint8 scales). Shares the b_cta_crd\n # (no N multicast since cluster_shape_mnk = (1,1,1)).\n tBsf_s, tBsf_g = cute.nvgpu.cpasync.tma_partition(\n tma_atom_b_sf,\n b_cta_crd,\n b_cta_layout,\n cute.group_modes(sB_sf, 0, 2),\n cute.group_modes(gB_sf_kn, 0, 2),\n )\n\n # B partition uses a phantom bf16 layout on top of the sB_packed\n # int32 storage (recast pointer + bf16 logical layout). This\n # gives ``partition_B``/``make_fragment_B`` the right fragment\n # shape; the data is never read through this view -- we always\n # decode FP4 ourselves.\n sB_phantom = cute.make_tensor(\n cute.recast_ptr(sB_packed.iterator, dtype=self.b_compute_dtype),\n b_bf16_logical_layout,\n )\n tCsA = thr_mma.partition_A(sA)\n tCsB_phantom = thr_mma.partition_B(sB_phantom)\n tCrA = tiled_mma.make_fragment_A(tCsA[None, None, None, 0])\n tCrB = tiled_mma.make_fragment_B(tCsB_phantom[None, None, None, 0])\n\n tCgC = thr_mma.partition_C(gC_mnl)\n acc_shape = tCgC.shape[:3]\n accumulators = cute.make_rmem_tensor(acc_shape, self.acc_dtype)\n\n if cute.size(self.cluster_shape_mnk) > 1:\n cute.arch.cluster_wait()\n else:\n pipeline.sync(barrier_id=1)\n\n # PDL bookend (start): wait for the prior grid to finish so this\n # kernel's TMA loads see the producer kernel's writes.\n cute.arch.griddepcontrol_wait()\n\n k_tile_cnt = cute.size(gA_mkl, mode=[3])\n\n tile_sched = utils.StaticPersistentTileScheduler.create(\n tile_sched_params, cute.arch.block_idx(), cute.arch.grid_dim()\n )\n work_tile = tile_sched.initial_work_tile_info()\n\n mainloop_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.ab_stage\n )\n mainloop_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.ab_stage\n )\n\n # MMA warp group: warps [0, num_mma_warps) compute.\n if warp_idx < self.num_mma_warps:\n cute.arch.setmaxregister_increase(self.mma_register_requirement)\n\n num_k_blocks = cute.size(tCrA, mode=[2])\n\n # ldmatrix is only for A. B is filled in-register from sB_packed\n # via FP4 decode + per-group scale.\n #\n # use_fp16_mma=1: tCrA is fp16-typed (matches the fp16 MMA), but\n # sA is bf16 in SMEM. ldmatrix into a bf16 staging fragment,\n # then per-K-block convert bf16 -> fp16 in-register before MMA\n # reads tCrA. See the inline cvt at each ldmatrix site.\n from cutlass import BFloat16\n\n atom_copy_ldmatrix_A = cute.make_copy_atom(\n cute.nvgpu.warp.LdMatrix8x8x16bOp(self.a_layout.is_m_major_a(), 4),\n self.a_dtype,\n )\n smem_tiled_copy_A = cute.make_tiled_copy_A(atom_copy_ldmatrix_A, tiled_mma)\n thr_copy_ldmatrix_A = smem_tiled_copy_A.get_slice(tidx)\n tCsA_copy_view = thr_copy_ldmatrix_A.partition_S(sA)\n if cutlass.const_expr(self.use_fp16_mma == 1):\n tCrA_bf16 = cute.make_fragment_like(tCrA, BFloat16)\n tCrA_copy_view = thr_copy_ldmatrix_A.retile(tCrA_bf16)\n else:\n tCrA_bf16 = tCrA\n tCrA_copy_view = thr_copy_ldmatrix_A.retile(tCrA)\n\n alpha_val = Float32(mAlpha[Int32(0)])\n\n while work_tile.is_valid_tile:\n tile_coord_mnl = work_tile.tile_idx\n gC_mnl_slice = gC_mnl[(None, None, *tile_coord_mnl)]\n accumulators.fill(0.0)\n\n mainloop_consumer_state.reset_count()\n\n peek_ab_full_status = cutlass.Boolean(1)\n if mainloop_consumer_state.count < k_tile_cnt:\n peek_ab_full_status = mainloop_pipeline.consumer_try_wait(\n mainloop_consumer_state\n )\n\n mainloop_pipeline.consumer_wait(\n mainloop_consumer_state, peek_ab_full_status\n )\n tCsA_p = tCsA_copy_view[None, None, None, mainloop_consumer_state.index]\n\n # Prologue: prefetch tCrA[0] and tCrB[0] only when running with\n # pipeline_depth >= 1. With depth=0 the dequant for block k\n # happens inside the same iteration as gemm(k) -- no prefetch.\n if cutlass.const_expr(self.pipeline_depth >= 1):\n cute.copy(\n smem_tiled_copy_A,\n tCsA_p[None, None, 0],\n tCrA_copy_view[None, None, 0],\n )\n if cutlass.const_expr(self.use_fp16_mma == 1):\n self._cvt_a_bf16_to_fp16_one_k_block(tCrA, tCrA_bf16, 0)\n self._dequant_b_to_register(\n sB_packed,\n sB_sf,\n tCrB,\n tidx,\n mainloop_consumer_state.index,\n mainloop_consumer_state.count,\n 0,\n )\n\n for _k_tile in cutlass.range(0, k_tile_cnt - 1, 1, unroll=1):\n for k_block_idx in cutlass.range_constexpr(num_k_blocks):\n k_block_next = (\n 0 if k_block_idx + 1 == num_k_blocks else k_block_idx + 1\n )\n\n if cutlass.const_expr(self.pipeline_depth == 0):\n # No-prefetch: dequant(k) just before gemm(k),\n # all on the CURRENT K-tile's stage. Release +\n # advance + wait happens AFTER gemm of the last\n # block so we don't drop SMEM under our own read.\n cute.copy(\n smem_tiled_copy_A,\n tCsA_p[None, None, k_block_idx],\n tCrA_copy_view[None, None, k_block_idx],\n )\n if cutlass.const_expr(self.use_fp16_mma == 1):\n self._cvt_a_bf16_to_fp16_one_k_block(\n tCrA, tCrA_bf16, k_block_idx\n )\n self._dequant_b_to_register(\n sB_packed,\n sB_sf,\n tCrB,\n tidx,\n mainloop_consumer_state.index,\n mainloop_consumer_state.count,\n k_block_idx,\n )\n cute.gemm(\n tiled_mma,\n accumulators,\n tCrA[None, None, k_block_idx],\n tCrB[None, None, k_block_idx],\n accumulators,\n )\n if k_block_idx == num_k_blocks - 1:\n mainloop_pipeline.consumer_release(\n mainloop_consumer_state\n )\n mainloop_consumer_state.advance()\n peek_ab_full_status = cutlass.Boolean(1)\n peek_ab_full_status = (\n mainloop_pipeline.consumer_try_wait(\n mainloop_consumer_state\n )\n )\n tCsA_p = tCsA_copy_view[\n None, None, None, mainloop_consumer_state.index\n ]\n mainloop_pipeline.consumer_wait(\n mainloop_consumer_state, peek_ab_full_status\n )\n else:\n # 1-stage prefetch: dequant(k+1) while gemm(k).\n if k_block_idx == num_k_blocks - 1:\n mainloop_pipeline.consumer_release(\n mainloop_consumer_state\n )\n mainloop_consumer_state.advance()\n\n peek_ab_full_status = cutlass.Boolean(1)\n peek_ab_full_status = (\n mainloop_pipeline.consumer_try_wait(\n mainloop_consumer_state\n )\n )\n\n tCsA_p = tCsA_copy_view[\n None, None, None, mainloop_consumer_state.index\n ]\n mainloop_pipeline.consumer_wait(\n mainloop_consumer_state, peek_ab_full_status\n )\n\n cute.copy(\n smem_tiled_copy_A,\n tCsA_p[None, None, k_block_next],\n tCrA_copy_view[None, None, k_block_next],\n )\n if cutlass.const_expr(self.use_fp16_mma == 1):\n self._cvt_a_bf16_to_fp16_one_k_block(\n tCrA, tCrA_bf16, k_block_next\n )\n self._dequant_b_to_register(\n sB_packed,\n sB_sf,\n tCrB,\n tidx,\n mainloop_consumer_state.index,\n mainloop_consumer_state.count,\n k_block_next,\n )\n cute.gemm(\n tiled_mma,\n accumulators,\n tCrA[None, None, k_block_idx],\n tCrB[None, None, k_block_idx],\n accumulators,\n )\n # Hoist out last k_tile (no further loads after the last k_block)\n for k_block_idx in cutlass.range_constexpr(num_k_blocks):\n k_block_next = (\n 0 if k_block_idx + 1 == num_k_blocks else k_block_idx + 1\n )\n\n if cutlass.const_expr(self.pipeline_depth == 0):\n # No-prefetch path for last K-tile. Release happens\n # AFTER gemm of the last block (kernel exits then).\n cute.copy(\n smem_tiled_copy_A,\n tCsA_p[None, None, k_block_idx],\n tCrA_copy_view[None, None, k_block_idx],\n )\n if cutlass.const_expr(self.use_fp16_mma == 1):\n self._cvt_a_bf16_to_fp16_one_k_block(\n tCrA, tCrA_bf16, k_block_idx\n )\n self._dequant_b_to_register(\n sB_packed,\n sB_sf,\n tCrB,\n tidx,\n mainloop_consumer_state.index,\n mainloop_consumer_state.count,\n k_block_idx,\n )\n cute.gemm(\n tiled_mma,\n accumulators,\n tCrA[None, None, k_block_idx],\n tCrB[None, None, k_block_idx],\n accumulators,\n )\n if k_block_idx == num_k_blocks - 1:\n mainloop_pipeline.consumer_release(mainloop_consumer_state)\n mainloop_consumer_state.advance()\n else:\n # 1-stage prefetch path for last K-tile.\n if k_block_idx == num_k_blocks - 1:\n mainloop_pipeline.consumer_release(mainloop_consumer_state)\n mainloop_consumer_state.advance()\n\n if k_block_next > 0:\n cute.copy(\n smem_tiled_copy_A,\n tCsA_p[None, None, k_block_next],\n tCrA_copy_view[None, None, k_block_next],\n )\n if cutlass.const_expr(self.use_fp16_mma == 1):\n self._cvt_a_bf16_to_fp16_one_k_block(\n tCrA, tCrA_bf16, k_block_next\n )\n self._dequant_b_to_register(\n sB_packed,\n sB_sf,\n tCrB,\n tidx,\n mainloop_consumer_state.index,\n mainloop_consumer_state.count,\n k_block_next,\n )\n cute.gemm(\n tiled_mma,\n accumulators,\n tCrA[None, None, k_block_idx],\n tCrB[None, None, k_block_idx],\n accumulators,\n )\n\n # Epilogue: accumulator -> smem -> gmem via R2S (StMatrix.x4)\n # + TMA bulk store.\n copy_atom_r2s = sm90_utils.sm90_get_smem_store_op(\n self.c_layout,\n elem_ty_d=self.c_dtype,\n elem_ty_acc=self.acc_dtype,\n )\n\n copy_atom_C = cute.make_copy_atom(\n cute.nvgpu.warp.StMatrix8x8x16bOp(\n self.c_layout.is_m_major_c(),\n 4,\n ),\n self.c_dtype,\n )\n\n tiled_copy_C_Atom = cute.make_tiled_copy_C_atom(copy_atom_C, tiled_mma)\n\n tiled_copy_r2s = cute.make_tiled_copy_S(\n copy_atom_r2s,\n tiled_copy_C_Atom,\n )\n\n thr_copy_r2s = tiled_copy_r2s.get_slice(tidx)\n tRS_sD = thr_copy_r2s.partition_D(sC)\n tRS_rAcc = tiled_copy_r2s.retile(accumulators)\n\n rD_shape = cute.shape(thr_copy_r2s.partition_S(sC))\n tRS_rD_layout = cute.make_layout(rD_shape[:3])\n tRS_rD = cute.make_rmem_tensor(tRS_rD_layout.shape, self.acc_dtype)\n\n sepi_for_tma_partition = cute.group_modes(sC, 0, 2)\n tcgc_for_tma_partition = cute.zipped_divide(gC_mnl_slice, self.epi_tile)\n\n bSG_sD, bSG_gD = cute.nvgpu.cpasync.tma_partition(\n tma_atom_c,\n 0,\n cute.make_layout(1),\n sepi_for_tma_partition,\n tcgc_for_tma_partition,\n )\n\n # Epilogue: iterate (epi_m, epi_n) explicitly\n # and use (mma_m, mma_n) mode indexing into tRS_rAcc so\n # the loop works for any epi_tile_m / epi_tile_n. Also\n # supports OOB-iteration skipping when m_actual < tile_M.\n epi_rest_m = cute.size(tcgc_for_tma_partition, mode=[1, 0])\n epi_rest_n = cute.size(tcgc_for_tma_partition, mode=[1, 1])\n epi_tile_m = self.epi_tile[0]\n epi_tile_n = self.epi_tile[1]\n # mma_tile_{m,n} = per-mma-atom (M,N) size. tRS_rAcc has\n # shape (atom_v, mma_m, mma_n); modes 1, 2 give the atom\n # counts in M, N.\n mma_tile_m = self.tile_shape_mnk[0] // cute.size(tRS_rAcc, mode=[1])\n mma_tile_n = self.tile_shape_mnk[1] // cute.size(tRS_rAcc, mode=[2])\n MmaMPerEpiM = epi_tile_m // mma_tile_m\n MmaNPerEpiN = epi_tile_n // mma_tile_n\n\n tma_store_producer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n self.num_mma_warps * self.num_threads_per_warp,\n )\n tma_store_pipeline = pipeline.PipelineTmaStore.create(\n num_stages=self.epi_stage,\n producer_group=tma_store_producer_group,\n )\n\n # Skip OOB epilogue iterations when actual M < tile_M.\n m_actual = cute.size(mC_mnl, mode=[0])\n cta_m_offset = tile_coord_mnl[0] * Int32(self.tile_shape_mnk[0])\n\n # kept_count cycles in lockstep with the TMA-store pipeline.\n # epi_buffer = kept_count % num_stages stays in sync with\n # producer_commit/acquire calls, regardless of how many\n # iterations are skipped.\n kept_count = 0\n for epi_n in cutlass.range_constexpr(epi_rest_n):\n for epi_m in cutlass.range_constexpr(epi_rest_m):\n epi_m_global_start = cta_m_offset + Int32(epi_m * epi_tile_m)\n if epi_m_global_start < m_actual:\n # Copy this epi-tile's slice of acc -> tRS_rD\n # using b12x-style (mma_m, mma_n) indexing.\n for mma_n_in_epi in cutlass.range_constexpr(MmaNPerEpiN):\n for mma_m_in_epi in cutlass.range_constexpr(\n MmaMPerEpiM\n ):\n mma_n = epi_n * MmaNPerEpiN + mma_n_in_epi\n mma_m = epi_m * MmaMPerEpiM + mma_m_in_epi\n tRS_rD_slice = tRS_rD[\n (None, mma_m_in_epi, mma_n_in_epi)\n ]\n tRS_rAcc_slice = tRS_rAcc[(None, mma_m, mma_n)]\n for elem_idx in cutlass.range_constexpr(\n cute.size(tRS_rD_slice)\n ):\n tRS_rD_slice[elem_idx] = tRS_rAcc_slice[\n elem_idx\n ]\n\n tRS_rD_out = cute.make_rmem_tensor(\n tRS_rD_layout.shape, self.c_dtype\n )\n # Apply the global alpha here, once, on the\n # fp32 accumulator (hoisted out of the\n # per-K-block dequant): one rounding instead\n # of folding alpha into every B scale.\n acc_vec = tRS_rD.load()\n tRS_rD_out.store((alpha_val * acc_vec).to(self.c_dtype))\n\n epi_buffer = kept_count % cute.size(tRS_sD, mode=[3])\n cute.copy(\n tiled_copy_r2s,\n tRS_rD_out,\n tRS_sD[(None, None, None, epi_buffer)],\n )\n cute.arch.fence_proxy(\"async.shared\", space=\"cta\")\n self.epilog_sync_barrier.arrive_and_wait()\n\n if warp_idx == 0:\n cute.copy(\n tma_atom_c,\n bSG_sD[(None, epi_buffer)],\n bSG_gD[(None, (epi_m, epi_n))],\n )\n tma_store_pipeline.producer_commit()\n tma_store_pipeline.producer_acquire()\n kept_count = kept_count + 1\n\n tma_store_pipeline.producer_tail()\n\n tile_sched.advance_to_next_work()\n work_tile = tile_sched.get_current_work()\n # Single DMA warp: issues all 3 TMA descriptors (A, B_packed, B_sf)\n # back-to-back into the same stage barrier per K-tile.\n elif warp_idx == self.num_mma_warps:\n cute.arch.setmaxregister_decrease(self.load_register_requirement)\n while work_tile.is_valid_tile:\n tile_coord_mnl = work_tile.tile_idx\n tAgA_mkl = tAgA[(None, tile_coord_mnl[0], None, tile_coord_mnl[2])]\n tBpacked_g_kn = tBpacked_g[\n (None, None, tile_coord_mnl[1], tile_coord_mnl[2])\n ]\n tBsf_g_kn = tBsf_g[(None, None, tile_coord_mnl[1], tile_coord_mnl[2])]\n mainloop_producer_state.reset_count()\n for _k_tile in cutlass.range(0, k_tile_cnt, 1, unroll=1):\n mainloop_pipeline.producer_acquire(mainloop_producer_state)\n barrier_ptr = mainloop_pipeline.producer_get_barrier(\n mainloop_producer_state\n )\n\n tAgA_k = tAgA_mkl[(None, mainloop_producer_state.count)]\n tAsA_pipe = tAsA[(None, mainloop_producer_state.index)]\n cute.copy(\n tma_atom_a,\n tAgA_k,\n tAsA_pipe,\n tma_bar_ptr=barrier_ptr,\n mcast_mask=a_mcast_mask,\n )\n\n tBpacked_g_k = tBpacked_g_kn[(None, mainloop_producer_state.count)]\n tBpacked_s_pipe = tBpacked_s[(None, mainloop_producer_state.index)]\n cute.copy(\n tma_atom_b_packed,\n tBpacked_g_k,\n tBpacked_s_pipe,\n tma_bar_ptr=barrier_ptr,\n mcast_mask=b_mcast_mask,\n )\n\n tBsf_g_k = tBsf_g_kn[(None, mainloop_producer_state.count)]\n tBsf_s_pipe = tBsf_s[(None, mainloop_producer_state.index)]\n cute.copy(\n tma_atom_b_sf,\n tBsf_g_k,\n tBsf_s_pipe,\n tma_bar_ptr=barrier_ptr,\n mcast_mask=b_mcast_mask,\n )\n\n mainloop_pipeline.producer_commit(mainloop_producer_state)\n mainloop_producer_state.advance()\n tile_sched.advance_to_next_work()\n work_tile = tile_sched.get_current_work()\n mainloop_pipeline.producer_tail(mainloop_producer_state)\n cute.arch.griddepcontrol_launch_dependents()\n return\n\n @staticmethod\n def _compute_stages(\n tile_shape_mnk: Tuple[int, int, int],\n a_dtype: Type[cutlass.Numeric],\n epi_tile: Tuple[int, int],\n c_dtype: Type[cutlass.Numeric],\n smem_capacity: int,\n occupancy: int,\n group_size: int = 16,\n epi_stage: int = 4,\n ) -> Tuple[int, int]:\n \"\"\"Stage budget accounting for A + B (packed int32) + B_sf (uint8).\n\n Per (16K x 64N) packed block: 128 int32 = 512 bytes.\n Per (group_size K x tile_N N) scale block: tile_N bytes.\n \"\"\"\n c_bytes_per_stage = cute.size(epi_tile) * c_dtype.width // 8\n epi_bytes = c_bytes_per_stage * epi_stage\n\n a_shape = cute.slice_(tile_shape_mnk, (None, 0, None))\n a_bytes_per_stage = cute.size(a_shape) * a_dtype.width // 8\n\n # B side: packed int32, 128 int32 per (16K x 64N) block.\n packed_blocks_per_tile = (tile_shape_mnk[2] // _PACK_TILE_K) * (\n tile_shape_mnk[1] // _PACK_TILE_N\n )\n b_packed_bytes_per_stage = packed_blocks_per_tile * _PACK_INTS_PER_TILE * 4\n\n # Scale tile: 1 byte per (K-group, N). Small compared to B_packed.\n b_sf_bytes_per_stage = (tile_shape_mnk[2] // group_size) * tile_shape_mnk[1]\n\n ab_bytes_per_stage = (\n a_bytes_per_stage + b_packed_bytes_per_stage + b_sf_bytes_per_stage\n )\n mbar_helpers_bytes = 1024\n\n ab_stage = (\n (smem_capacity - occupancy * 1024) // occupancy\n - mbar_helpers_bytes\n - epi_bytes\n ) // ab_bytes_per_stage\n return ab_stage, epi_stage\n\n @staticmethod\n def _make_smem_layouts(\n tile_shape_mnk: Tuple[int, int, int],\n epi_tile: Tuple[int, int],\n a_dtype: Type[cutlass.Numeric],\n a_layout: cute.Layout,\n b_compute_dtype: Type[cutlass.Numeric],\n b_layout_compute: cute.Layout,\n ab_stage: int,\n c_dtype: Type[cutlass.Numeric],\n c_layout: cute.Layout,\n epi_stage: int,\n group_size: int,\n ):\n \"\"\"Returns (sA, sB_packed, sB_sf, b_bf16_phantom, sC) layouts.\n\n ``sB_packed_layout`` is a plain (non-swizzled) staged int32 layout\n ``(tile_K // 16, 2 * tile_N, ab_stage)``.\n\n ``sB_sf_layout`` is a plain staged uint8 layout\n ``(tile_K // group_size, tile_N, ab_stage)`` -- one byte per\n (K-group, N) cell. Loaded via TMA once per K-tile, read from\n SMEM in the dequant inner loop (replaces the gmem-direct path).\n\n ``b_bf16_logical_layout`` is the phantom bf16 layout used only by\n ``partition_B`` / ``make_fragment_B`` for fragment-shape\n determination -- there is no real bf16 SMEM allocation.\n \"\"\"\n a_smem_layout_staged = sm90_utils.make_smem_layout_a(\n a_layout,\n tile_shape_mnk,\n a_dtype,\n ab_stage,\n )\n\n # sB_packed: (tile_K // 16) rows x (2 * tile_N) int32 cols x stage.\n b_packed_smem_layout_staged = cute.make_ordered_layout(\n (\n tile_shape_mnk[2] // _PACK_TILE_K,\n 2 * tile_shape_mnk[1],\n ab_stage,\n ),\n order=(1, 0, 2),\n )\n\n # sB_sf: (tile_K // group_size) rows x tile_N uint8 cols x stage.\n # Order (1, 0, 2) -> N innermost (= contiguous load lane), K next,\n # stage outermost. Matches the gmem layout.\n b_sf_smem_layout_staged = cute.make_ordered_layout(\n (\n tile_shape_mnk[2] // group_size,\n tile_shape_mnk[1],\n ab_stage,\n ),\n order=(1, 0, 2),\n )\n\n # bf16 phantom layout for partition_B / make_fragment_B.\n b_bf16_logical_layout = sm90_utils.make_smem_layout_b(\n b_layout_compute,\n tile_shape_mnk,\n b_compute_dtype,\n ab_stage,\n )\n\n epi_smem_layout_staged = sm90_utils.make_smem_layout_epi(\n c_dtype,\n c_layout,\n epi_tile,\n epi_stage,\n )\n return (\n a_smem_layout_staged,\n b_packed_smem_layout_staged,\n b_sf_smem_layout_staged,\n b_bf16_logical_layout,\n epi_smem_layout_staged,\n )\n\n @staticmethod\n def _compute_grid(\n c: cute.Tensor,\n tile_shape_mnk: Tuple[int, int, int],\n max_active_clusters: cutlass.Constexpr,\n tile_swizzle: cutlass.Constexpr = 1,\n raster_along_m: cutlass.Constexpr = True,\n ):\n c_shape = cute.slice_(tile_shape_mnk, (None, None, 0))\n gc = cute.zipped_divide(c, tiler=c_shape)\n num_ctas_mnl = gc[(0, (None, None, None))].shape\n cluster_shape_mnl = (1, 1, 1)\n tile_sched_params = utils.PersistentTileSchedulerParams(\n num_ctas_mnl,\n cluster_shape_mnl,\n swizzle_size=tile_swizzle,\n raster_along_m=raster_along_m,\n )\n grid = utils.StaticPersistentTileScheduler.get_grid_shape(\n tile_sched_params, max_active_clusters\n )\n return tile_sched_params, grid\n\n @staticmethod\n def _make_tma_store_atoms_and_tensors(\n tensor_c: cute.Tensor,\n epi_smem_layout_staged: cute.ComposedLayout,\n epi_tile: Tuple[int, int],\n ) -> Tuple[cute.CopyAtom, cute.Tensor]:\n epi_smem_layout = cute.slice_(epi_smem_layout_staged, (None, None, 0))\n tma_atom_c, tma_tensor_c = cute.nvgpu.cpasync.make_tiled_tma_atom(\n cute.nvgpu.cpasync.CopyBulkTensorTileS2GOp(),\n tensor_c,\n epi_smem_layout,\n epi_tile,\n )\n return tma_atom_c, tma_tensor_c\n\n @staticmethod\n def _make_tma_atoms_and_tensors(\n tensor: cute.Tensor,\n smem_layout_staged: cute.ComposedLayout,\n smem_tile: Tuple[int, int],\n mcast_dim: int,\n ) -> Tuple[cute.CopyAtom, cute.Tensor]:\n op = (\n cute.nvgpu.cpasync.CopyBulkTensorTileG2SOp()\n if mcast_dim == 1\n else cute.nvgpu.cpasync.CopyBulkTensorTileG2SMulticastOp()\n )\n smem_layout = cute.slice_(smem_layout_staged, (None, None, 0))\n tma_atom, tma_tensor = cute.nvgpu.cpasync.make_tiled_tma_atom(\n op,\n tensor,\n smem_layout,\n smem_tile,\n num_multicast=mcast_dim,\n )\n return tma_atom, tma_tensor\n\n @cute.jit\n def _cvt_a_bf16_to_fp16_one_k_block(\n self,\n tCrA_dst,\n tCrA_bf16_src,\n k_block: cutlass.Constexpr,\n ):\n \"\"\"In-register bf16 -> fp16 cvt for one K-block of A.\n\n Recasts both fragments to Uint32 (each u32 packs 2 16-bit elems)\n and applies `cvt_bf16x2_to_f16x2_via_f32` per pair. The packed\n narrowing cvt (`cvt.rn.f16x2.f32`) combines what would be two\n scalar `cvt.rn.f16.f32` instructions if we used cute's default\n `.to(Float16)` lowering.\n\n bf16/f16 typed inline-asm constraints don't compile on sm_100a\n (NVVM rejects them), so we keep everything in Uint32 pair\n representation via cute.recast_tensor.\n \"\"\"\n bf_u32 = cute.recast_tensor(tCrA_bf16_src[None, None, k_block], Uint32)\n fp_u32 = cute.recast_tensor(tCrA_dst[None, None, k_block], Uint32)\n n_pairs = cute.size(bf_u32)\n for i in cutlass.range_constexpr(n_pairs):\n fp_u32[i] = cvt_bf16x2_to_f16x2_via_f32(Uint32(bf_u32[i]))\n\n @cute.jit\n def _dequant_b_to_register(\n self,\n sB_packed: cute.Tensor,\n sB_sf: cute.Tensor,\n tCrB: cute.Tensor,\n tidx: Int32,\n stage_idx: Int32,\n k_tile_idx: Int32,\n k_block_idx: cutlass.Constexpr,\n ):\n \"\"\"Decode 2 int32 per thread per K-block into 16 fp16 fragment slots.\n\n Per the MMA partition for atom_layout (2,2,1) + *2 on N:\n\n tc_row = (lane % 4) * 2 in {0, 2, 4, 6}\n tc_col = lane // 4 in [0, 8)\n n_warp_idx = warp_idx // 2 in {0, 1}\n base_n = n_warp_idx * 8 + tc_col in [0, 16)\n\n Each thread covers:\n K = {tc_row, tc_row+1, tc_row+8, tc_row+9}\n N = {base_n, base_n+16, base_n+32, base_n+48}\n\n Two int32s per K-block per thread; sB_packed offsets:\n u32_0 @ sB_packed[k_block_idx, n_warp_idx * 64 + lane * 2 + 0, stage]\n u32_1 @ sB_packed[k_block_idx, n_warp_idx * 64 + lane * 2 + 1, stage]\n\n Byte layout inside each int32 (see ``_cute_dsl_pack_fp4_weight`` in\n ``flashinfer/gemm/gemm_bf16_fp4_cute_dsl.py``):\n u32_0:\n byte 0: K=tc_row, tc_row+1 at N=base_n -> (mma_i=0,1, nn=0)\n byte 1: K=tc_row+8, tc_row+9 at N=base_n -> (mma_i=2,3, nn=0)\n byte 2: K=tc_row, tc_row+1 at N=base_n+16 -> (mma_i=0,1, nn=1)\n byte 3: K=tc_row+8, tc_row+9 at N=base_n+16 -> (mma_i=2,3, nn=1)\n u32_1 mirrors with N=base_n+32 and N=base_n+48 (nn=2, nn=3).\n \"\"\"\n lane = tidx % Int32(32)\n warp = tidx // Int32(32)\n # n_warp_idx maps warp -> N-stripe. With (2,2,1) the 4 warps are\n # arranged as 2 M-warps * 2 N-warps, so n_warp_idx = warp // 2.\n # With (1,2,1) there are 2 warps total (no M-warp dim), so each\n # warp is its own N-stripe: n_warp_idx = warp. In general\n # n_warp_idx = warp // atom_layout[0].\n n_warp_idx = warp // Int32(self.atom_layout[0])\n tc_col = lane // Int32(4)\n base_n_in_tile = n_warp_idx * Int32(8) + tc_col\n\n # tile_N is built from tile_N // 64 independent packed 64-N blocks.\n # The hand-coded byte->fragment mapping below covers exactly one such\n # 64-N block (4 nn slots); for tile_N=128 we loop it over both blocks.\n # Block n_blk lives at sB_packed int32 columns [n_blk*128, +128), sB_sf\n # N-rows [n_blk*64, +64), and writes tCrB nn in [n_blk*4, +4). For\n # tile_N=64 this loops once.\n num_n_blocks = cutlass.const_expr(self.tile_shape_mnk[1] // 64)\n\n # _write_hmul2 captures tCrB / k_block_idx; nn and mma-row passed per\n # write. fp16 MMA writes fp16 directly; bf16 MMA goes via fp32 (no\n # packed f16x2 -> bf16x2 cvt on sm_100a).\n if cutlass.const_expr(self.use_fp16_mma == 1):\n\n def _write_hmul2(h2, scale_h2, mma_i_low, nn):\n scaled_h2 = half2_mul(h2, scale_h2)\n f_lo, f_hi = f16x2_unpack(scaled_h2)\n tCrB[mma_i_low, nn, k_block_idx] = f_lo\n tCrB[mma_i_low + 1, nn, k_block_idx] = f_hi\n else:\n\n def _write_hmul2(h2, scale_h2, mma_i_low, nn):\n scaled_h2 = half2_mul(h2, scale_h2)\n f_lo, f_hi = f16x2_to_f32x2(scaled_h2)\n tCrB[mma_i_low, nn, k_block_idx] = f_lo.to(self.b_compute_dtype)\n tCrB[mma_i_low + 1, nn, k_block_idx] = f_hi.to(self.b_compute_dtype)\n\n for n_blk in cutlass.range_constexpr(num_n_blocks):\n n_col_off = Int32(n_blk * 128) # int32 column offset of this 64-N block\n n_sf_off = Int32(n_blk * 64) # SF N-row offset of this 64-N block\n nn0 = n_blk * 4 # base tCrB N-fragment slot for this block\n\n # Single ld.shared.v2.u32 (8-byte load): u32_pos_base is always even\n # (= n_blk*128 + n_warp*64 + lane*2), so the offset is 8-byte aligned.\n u32_pos_base = n_col_off + n_warp_idx * Int32(64) + lane * Int32(2)\n smem_addr_b = get_smem_ptr_as_int32(\n sB_packed, sB_packed.layout((k_block_idx, u32_pos_base, stage_idx))\n )\n u32_0, u32_1 = ld_shared_v2_u32(smem_addr_b)\n\n # Per-group scale loads (S0E5M3). 4 distinct N positions per block.\n sf_n = base_n_in_tile + n_sf_off\n sf_byte_0 = Uint32(sB_sf[k_block_idx, sf_n + Int32(0), stage_idx])\n sf_byte_1 = Uint32(sB_sf[k_block_idx, sf_n + Int32(16), stage_idx])\n sf_byte_2 = Uint32(sB_sf[k_block_idx, sf_n + Int32(32), stage_idx])\n sf_byte_3 = Uint32(sB_sf[k_block_idx, sf_n + Int32(48), stage_idx])\n\n h0_a, h0_b, h0_c, h0_d = fp4_decode_4bytes(u32_0)\n h1_a, h1_b, h1_c, h1_d = fp4_decode_4bytes(u32_1)\n\n # S0E5M3 scale -> f16x2 broadcast in one mul.lo.u32. alpha is\n # applied once in the epilogue, so the scale never needs an f32 form.\n sc_n0 = cvt_s0e5m3_to_f16x2_broadcast(sf_byte_0)\n sc_n1 = cvt_s0e5m3_to_f16x2_broadcast(sf_byte_1)\n sc_n2 = cvt_s0e5m3_to_f16x2_broadcast(sf_byte_2)\n sc_n3 = cvt_s0e5m3_to_f16x2_broadcast(sf_byte_3)\n _write_hmul2(h0_a, sc_n0, 0, nn0 + 0)\n _write_hmul2(h0_b, sc_n0, 2, nn0 + 0)\n _write_hmul2(h0_c, sc_n1, 0, nn0 + 1)\n _write_hmul2(h0_d, sc_n1, 2, nn0 + 1)\n _write_hmul2(h1_a, sc_n2, 0, nn0 + 2)\n _write_hmul2(h1_b, sc_n2, 2, nn0 + 2)\n _write_hmul2(h1_c, sc_n3, 0, nn0 + 3)\n _write_hmul2(h1_d, sc_n3, 2, nn0 + 3)\n\n @cute.jit\n def wrapper(\n self,\n mA: cute.Tensor,\n mB_packed: cute.Tensor,\n mB_sf: cute.Tensor,\n mC: cute.Tensor,\n mAlpha: cute.Tensor,\n l: cutlass.Constexpr,\n max_active_clusters: cutlass.Constexpr,\n current_stream,\n ):\n \"\"\"bf16 x fp4 wrapper for the FlashInfer compile interface.\n\n Args:\n mA: (m, k) input tensor A, bf16 or fp16.\n mB_packed: (k // 16, n * 2) int32 -- packed FP4.\n mB_sf: (k // 16, n) uint8 -- FP8-E4M3 per-group scales.\n mC: (m, n) output tensor C, bf16 or fp16.\n mAlpha: (1,) fp32 global scale.\n l: batch dimension (Constexpr); typically 1.\n max_active_clusters: Constexpr from get_max_active_clusters(1).\n current_stream: CUDA stream (TVM-FFI fake stream).\n \"\"\"\n m = cute.size(mA, mode=[0])\n k = cute.size(mA, mode=[1])\n n = cute.size(mC, mode=[1])\n k_tiles = k // _PACK_TILE_K\n n_packed = 2 * n\n k_sf_groups = k // self.GROUP_SIZE\n\n a_tensor = cute.make_tensor(\n mA.iterator,\n layout=cute.make_ordered_layout((m, k, l), order=(1, 0, 2)),\n )\n b_packed_tensor = cute.make_tensor(\n mB_packed.iterator,\n layout=cute.make_ordered_layout((k_tiles, n_packed, l), order=(1, 0, 2)),\n )\n b_sf_tensor = cute.make_tensor(\n mB_sf.iterator,\n layout=cute.make_ordered_layout((k_sf_groups, n, l), order=(1, 0, 2)),\n )\n c_tensor = cute.make_tensor(\n mC.iterator,\n layout=cute.make_ordered_layout((m, n, l), order=(1, 0, 2)),\n )\n\n self(\n a_tensor,\n b_packed_tensor,\n b_sf_tensor,\n c_tensor,\n mAlpha,\n max_active_clusters,\n current_stream,\n )\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## 📌 Description\n\n#3597 added `mm_bf16_fp4` (bf16 activations x nvfp4 weights) so vLLM can replace Marlin, its default W4A16 backend, with a FlashInfer kernel; DGX Spark is the lead target. On decode shapes the kernel trailed Marlin for two reasons: small-n grids underfill the GPU, and at single-token batches (m=1) too few resident warps per SM hide DRAM latency. This PR addresses both: m=1 decode beats or matches Marlin on every part we measured, and end-to-end serving of Qwen3.6-27B-NVFP4 flips from behind to ahead at batch 1 with no regression elsewhere.\n\n**What it does**\n\n- Adds split-K tactics (2/4/8 splits) to the autotuner space, offered only when splitting shortens the grid's last wave by at least 25%. Splits write fp32 partials, and a PDL-chained reduce kernel sums them in fixed order, so results are deterministic run to run.\n- Adds occupancy tactics: 2 or 3 co-resident CTAs per SM trade pipeline depth for latency hiding on weight-bound grids, plus occupancy 2 combined with split-K for narrow-n shapes.\n- Adds a streaming GEMV kernel (`gemv_bf16_fp4_sm12x.py`) for the bandwidth-bound m=1 case: no shared memory, no tensor cores, weights stream from global memory to registers with latency hidden by warp count. It reads the same packed operands as the MMA kernel, so the autotuner picks between the two per shape.\n- Sizes GEMV split-K from the device: alongside the power-of-2 splits, the menu carries a split targeting ~20 warps/SM (the measured saturation point). Tactic indices become device-scoped, so the autotuner cache key now carries the SM count.\n- Routes the no-autotune m=1 fallback onto the GEMV. Serving stacks do not tune every shape (vLLM's warmup never captures the logits GEMM), so the lm_head always takes this path.\n- Fixes kernel launch to pass no cluster dimensions: the boilerplate `cluster=[1,1,1]` routed launches through the cluster work distributor, whose co-residency cap silently defeated the occupancy tactics on SM12x.\n\nNo public API changes. The one observable behavior change: untuned m=1 calls on SM12x now run the GEMV, whose output is bitwise different from the MMA heuristic's but equally accurate and still deterministic.\n\n### Performance\n\n#### Split-K on the #3597 decode shapes (RTX PRO 6000 / DGX Spark / RTX 5080)\n\nSingle-token decode GEMMs (m=1). The first table covers serving-class shapes (Llama-8B projection layers plus the #3597 example shape); the second covers #3597's own benchmark grid. Median GPU time over CUDA-graph replays with a cold L2 cache, as in serving. Baseline is vLLM's Marlin on the same GPU; FlashInfer runs with autotuning. Speedup = Marlin time / FlashInfer time. Each cell is a RTX PRO 6000 / DGX Spark / RTX 5080 triple.\n\n| n x k | vs Marlin, before this PR | vs Marlin, with this PR |\n|--:|:--:|:--:|\n| 2048x7168 | 0.57 / 1.00 / 0.47 | **1.36** / **1.02** / **0.78** |\n| 4096x4096 | 0.75 / 0.91 / 0.90 | **1.06** / **1.00** / 0.90 |\n| 4096x14336 | 0.60 / 0.91 / 0.78 | **0.98** / **1.00** / 0.78 |\n| 14336x4096 | 0.97 / 1.00 / 0.86 | 0.97 / 1.00 / 0.86 |\n| 10304x2688 | 0.78 / 0.98 / 0.96 | 0.78 / 0.98 / 0.96 |\n\nThe same comparison over #3597's benchmark grid (4096x4096 appears in the table above):\n\n| n x k | vs Marlin, before this PR | vs Marlin, with this PR |\n|--:|:--:|:--:|\n| 512x2048 | 2.09 / 0.95 / 0.95 | **4.48** / **1.43** / **2.30** |\n| 512x4096 | 1.19 / 0.70 / 0.56 | **3.61** / **1.26** / **1.88** |\n| 1024x2048 | 1.26 / 0.98 / 0.70 | **2.39** / **1.03** / **1.32** |\n| 1024x4096 | 0.99 / 0.86 / 0.49 | **2.72** / **1.04** / **1.21** |\n| 2048x512 | 1.86 / 1.25 / 1.19 | 1.86 / 1.25 / 1.19 |\n| 2048x1024 | 1.36 / 1.16 / 0.90 | **1.40** / 1.16 / **1.02** |\n| 2048x2048 | 1.17 / 1.11 / 0.70 | **1.72** / **1.02**\\* (1.11) / **0.97** |\n| 2048x4096 | 0.73 / 1.08 / 0.54 | **1.48** / **1.04**\\* (1.08) / **0.84** |\n| 4096x512 | 1.40 / 1.01 / 1.38 | 1.40 / **0.95**\\* (1.01) / 1.38 |\n| 4096x1024 | 1.41 / 0.93 / 1.18 | 1.41 / **0.95** / 1.18 |\n| 4096x2048 | 0.95 / 0.95 / 1.06 | 0.95 / **1.00** / 1.06 |\n| 131072x2048 | 0.98 / 0.97 / 0.90 | 0.98 / 0.97 / 0.90 |\n| 248320x2048 | 0.98 / 1.00 / 0.93 | 0.98 / 1.00 / 0.93 |\n\n- Bold marks the cells this PR changes (the tuner picks a new split-K tactic); unbolded picks perform as before.\n- \\* These three cells are tuner mis-picks, not kernel regressions: an accurate pick would keep #3597's pre-existing non-split config, and the value in parentheses is what that config achieves. The Reviewer Notes explain the cause.\n- On the serving shapes, the RTX 5080 column stays below 1.0 even where this PR helps. Profiling of the larger losses points to activation re-reads through L2, a separate problem from grid fill and out of scope here.\n\n#### Qwen3.6-27B-NVFP4 decode GEMMs at m=1 (RTX 5080, DGX Spark)\n\nSame methodology as above; speedup = Marlin time / FlashInfer time.\n\n| GEMM (n x k) | RTX 5080 | DGX Spark |\n|--|:--:|:--:|\n| gate_up 34816x5120 | **1.03** | 1.00 |\n| down 5120x17408 | **1.03** | 1.00 |\n| lm_head 248320x5120 | **1.04**\\* | **1.04** |\n\n\\* Marlin's lm_head repack does not fit on the 16 GB RTX 5080, so this cell compares against the best in-tree MMA tactic. Spark ties at its bandwidth floor on the first two shapes.\n\n#### End-to-end vLLM serving of Qwen3.6-27B-NVFP4 (RTX PRO 6000)\n\nFull serving A/B, FlashInfer leg vs Marlin leg under identical settings, aiperf output-token throughput, ratio = FlashInfer / Marlin: batch-1 decode 1.011x, low-concurrency speculative decode 1.08 to 1.11x ahead, and every other cell at parity within run-to-run noise (0.978 to 1.014x) with no regression beyond it.\n\n## 🔍 Related Issues\n\nFollow-up to #3597.\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\nNew tests:\n\n- Every enumerated tactic (MMA and GEMV) is checked against a reference and for bit-exact run-to-run determinism.\n- Unit tests pin the fallback selectors' picks; one test drives tactic=-1 through the GEMV fallback end to end.\n- Full test file passes on RTX 5080, RTX PRO 6000, and GB10.\n\n## Reviewer Notes\n\n- Most gains require autotuning, which serving frameworks run at startup. The no-autotune fallback picks match the tuner's choices on every part we measured.\n- The autotuner times candidates with a warm L2 while decode serving runs cold, so it can over-rank split tactics; the 25% last-wave guard compensates but does not fully close it (the three Spark cells in the grid table). This measurement gap is general and deserves its own issue.\n- The fallback picks add JIT-compiled kernel variants per decode shape class, cached in-process only; that cost amortizes to once per machine when this module adopts the #3874 CuTe-DSL disk cache, as #4029 did for the sibling `mm_fp4` path. The GEMV's device-derived splits widen this surface, so the follow-up is worth prioritizing.\n- Other FlashInfer cute-dsl kernels also pass `cluster=[1,1,1]` at launch and inherit the same co-residency cap; they are worth a separate audit.\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n- **New Features**\n - Added split-K support for bf16 × fp4 matrix multiplication to improve performance across varying workloads.\n - Added a dedicated SM12x GEMV path for efficient single-row operations.\n - Added automatic tuning for split counts, occupancy, and device-specific execution strategies.\n - Added support for FP16 GEMV outputs and deterministic partial-result reduction.\n\n- **Bug Fixes**\n - Improved handling of GEMV and split-K fallback selection across supported shapes and GPU configurations.\n\n- **Tests**\n - Added coverage for accuracy, determinism, GEMV correctness, and split-K selection.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000\", \"model\": null, \"shape\": \"n=2048,k=7168\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 0.57, \"optimized\": 1.36, \"stated_speedup\": null, \"speedup\": 2.386}, {\"scope\": \"kernel\", \"hardware\": \"DGX Spark\", \"model\": null, \"shape\": \"n=2048,k=7168\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 1.0, \"optimized\": 1.02, \"stated_speedup\": null, \"speedup\": 1.02}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"n=2048,k=7168\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 0.47, \"optimized\": 0.78, \"stated_speedup\": null, \"speedup\": 1.6596}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000\", \"model\": null, \"shape\": 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\"n=2048,k=1024\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 1.36, \"optimized\": 1.4, \"stated_speedup\": null, \"speedup\": 1.0294}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"n=2048,k=1024\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 0.9, \"optimized\": 1.02, \"stated_speedup\": null, \"speedup\": 1.1333}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000\", \"model\": null, \"shape\": \"n=2048,k=2048\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 1.17, \"optimized\": 1.72, \"stated_speedup\": null, \"speedup\": 1.4701}, {\"scope\": \"kernel\", \"hardware\": \"DGX Spark\", \"model\": null, \"shape\": \"n=2048,k=2048\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 1.11, \"optimized\": 1.02, \"stated_speedup\": null, \"speedup\": 0.9189}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"n=2048,k=2048\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 0.7, \"optimized\": 0.97, \"stated_speedup\": null, \"speedup\": 1.3857}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000\", \"model\": null, \"shape\": \"n=2048,k=4096\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 0.73, \"optimized\": 1.48, \"stated_speedup\": null, \"speedup\": 2.0274}, {\"scope\": \"kernel\", \"hardware\": \"DGX Spark\", \"model\": null, \"shape\": \"n=2048,k=4096\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 1.08, \"optimized\": 1.04, \"stated_speedup\": null, \"speedup\": 0.963}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"n=2048,k=4096\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 0.54, \"optimized\": 0.84, \"stated_speedup\": null, \"speedup\": 1.5556}, {\"scope\": \"kernel\", \"hardware\": \"DGX Spark\", \"model\": null, \"shape\": \"n=4096,k=512\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 1.01, \"optimized\": 0.95, \"stated_speedup\": null, \"speedup\": 0.9406}, {\"scope\": \"kernel\", \"hardware\": \"DGX Spark\", \"model\": null, \"shape\": \"n=4096,k=1024\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 0.93, \"optimized\": 0.95, \"stated_speedup\": null, \"speedup\": 1.0215}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": \"Qwen3.6-27B-NVFP4\", \"shape\": \"n=34816,k=5120\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 1.0, \"optimized\": 1.03, \"stated_speedup\": null, \"speedup\": 1.03}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": \"Qwen3.6-27B-NVFP4\", \"shape\": \"n=5120,k=17408\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 1.0, \"optimized\": 1.03, \"stated_speedup\": null, \"speedup\": 1.03}, {\"scope\": \"kernel\", \"hardware\": \"RTX 5080\", \"model\": \"Qwen3.6-27B-NVFP4\", \"shape\": \"n=248320,k=5120\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 1.0, \"optimized\": 1.04, \"stated_speedup\": null, \"speedup\": 1.04}, {\"scope\": \"kernel\", \"hardware\": \"DGX Spark\", \"model\": \"Qwen3.6-27B-NVFP4\", \"shape\": \"n=248320,k=5120\", \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 1.0, \"optimized\": 1.04, \"stated_speedup\": null, \"speedup\": 1.04}, {\"scope\": \"e2e\", \"hardware\": \"RTX PRO 6000\", \"model\": \"Qwen3.6-27B-NVFP4\", \"shape\": null, \"batch_size\": 1, \"metric\": \"throughput\", \"unit\": \"tok/s\", \"higher_is_better\": true, \"baseline\": 1.0, \"optimized\": 1.011, \"stated_speedup\": 1.011, \"speedup\": 1.011}, {\"scope\": \"e2e\", \"hardware\": \"RTX PRO 6000\", \"model\": \"Qwen3.6-27B-NVFP4\", \"shape\": null, \"batch_size\": null, \"metric\": \"throughput\", \"unit\": \"tok/s\", \"higher_is_better\": true, \"baseline\": 1.0, \"optimized\": 1.08, \"stated_speedup\": 1.08, \"speedup\": 1.08}, {\"scope\": \"e2e\", \"hardware\": \"RTX PRO 6000\", \"model\": \"Qwen3.6-27B-NVFP4\", \"shape\": null, \"batch_size\": null, \"metric\": \"throughput\", \"unit\": \"tok/s\", \"higher_is_better\": true, \"baseline\": 1.0, \"optimized\": 1.11, \"stated_speedup\": 1.11, \"speedup\": 1.11}]"},"kernel_speedup":{"kind":"number","value":1.3857,"string":"1.3857"},"e2e_speedup":{"kind":"number","value":1.08,"string":"1.08"}}},{"rowIdx":1089,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"e9fb62b74e47444eba83da71a573c9437e71cb3b"},"date":{"kind":"string","value":"2026-08-11T18:29:38+08:00"},"pr_number":{"kind":"number","value":3761,"string":"3,761"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/3761"},"title":{"kind":"string","value":"perf(moe): optimize CUTLASS fused MoE mem-bound kernels (#3761)"},"message":{"kind":"string","value":"perf(moe): optimize CUTLASS fused MoE mem-bound kernels (#3761)\n\n<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\n### Key Findings\n\nWe observed that the Triton implementation outperforms the FlashInfer\nCUTLASS fused MoE backend on Hopper for BF16 data types (#3521), and\nthus we started investigating kernel optimization opportunities related\nto the associated kernels. Here are some key findings regarding the\nhelper memory-bound kernels:\n* Lack of vectorization: In kernels such as `expandInputRowsKernel` and\n`doActivationKernel`, vectorization is not actually enabled. The\ngenerated SASS shows occurrences of four contiguous `LDG.E` instructions\nrather than a single `LDG.E.128`.\n* Inactive warp: The `doActivationKernel` is currently hardcoded to use\n256 threads per row. For workloads with small intermediate sizes, this\ncan be excessive and can result in inactive warps and suboptimal\noccupancy.\n\n### Changes Made\n\nThis PR improves the performance of the CUTLASS fused MoE\ninput-expansion and activation kernels.\n* Explicitly vectorize global/store in `expandInputRowsKernel` and\n`doActivationKernel`.\n* This did not work on `finalizeMoeRoutingKernel` as it was observed to\nincrease register usage and did not improve perf.\n* Select the activation kernel block size based on the work required per\nrow, which reduces inactive warps and improves occupancy for smaller\nintermediate dimensions (e.g., 768 for `Qwen/Qwen3-30B-A3B`). Also, cap\nthe grid size 8~32 blocks (which was constantly 8) per SM based on block\nsize. This limits unnecessary warp-scheduling pressure.\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n#3521\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the\npre-commit documentation](https://pre-commit.com/).\n\n## ⚡ Performance\n\n### SASS verification (SM100, CUDA 13.2)\n\n| row-data access | before (main) | after (this PR) |\n|---|---|---|\n| expandInputRows (bf16→bf16), per 16B copy | 4× `LDG.E` + 4× `STG.E` |\n1× `LDG.E.128` + 1× `STG.E.128` |\n| doActivation (bf16, Swiglu), per 16B of fc1/linear/bias | 4× `LDG.E`\neach | 1× `LDG.E.128` each |\n| doActivation (fp8 out, Swiglu), per 32B gemm vector | 8× `LDG.E` | 2×\n`LDG.E.128` |\n| doActivation (nvfp4 out, Swiglu), fp4 output + SF | unchanged (`STG.E`\npacked + `STG.E.U8`) | unchanged |\n\n### benchmarks/flashinfer_benchmark.py\n\n#### Setup\n* Single B100 (SM100), clocks locked at 1400 MHz SM / 4000 MHz mem, CUDA\n13.2\n * Autotune off so both builds run identical default GEMM tactics\n * Baseline = main @ 2e97a607d\n * Cell = median of per-pair speedups\n\n#### Result\n* Achieved up to 1.08x end-to-end speedup\n* No regression observed\n\n| case | M=1 | M=16 | M=128 | M=512 | M=2048 | M=8192 | M=16384 |\n|---|---|---|---|---|---|---|---|\n| qwen3_tp1 | 1.00x | 0.99x | 1.00x | 0.99x | 1.02x | 1.04x | 1.05x |\n| qwen3_tp2 | 1.01x | 1.00x | 1.01x | 1.01x | 1.04x | 1.05x | 1.05x |\n| qwen3_tp4 | 1.00x | 1.00x | 1.01x | 1.01x | 1.04x | 1.04x | 1.05x |\n| qwen3_tp2_fp8 | 1.00x | 1.03x | 1.00x | 1.02x | 1.02x | 1.04x | 1.05x\n|\n| qwen3_tp4_fp8 | 1.00x | 1.00x | 1.01x | 1.03x | 1.06x | **1.07x** |\n**1.07x** |\n| dsv3_nvfp4 | 1.01x | 1.03x | 1.04x | 1.06x | **1.08x** | 1.01x | 1.05x\n|\n| mixtral_tp4 (guard) | 1.00x | 1.00x | 1.00x | 1.00x | 1.01x | 1.02x |\n1.01x |\n\n### vLLM end-to-end benchmarking on H200x8\n\n#### Setup\n\n```\nvllm bench throughput --model Qwen/Qwen3-30B-A3B --dataset-name random --moe-backend <backend> -tp <tp>\n```\n\n#### Result\n\n| TP | main | this PR | gain | vs triton backend |\n|---:|---:|---:|---:|---:|\n| 1 | 41.52 | 42.09 | **+1.4%** | +1.5% |\n| 2 | 60.92 | 61.69 | **+1.3%** | −3.3% (was −4.5%) |\n| 4 | 69.36 | 71.51 | **+3.1%** | ~parity |\n| 8 | 74.17 | 75.74 | **+2.1%** | −2.4% |\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc.\n-->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n* **Performance**\n* Improved Mixture-of-Experts processing with vectorized memory\noperations for quantized, unquantized, and FP8 data paths.\n* Optimized activation workload distribution, memory access, and scaling\nacross available GPU resources.\n\n* **Bug Fixes**\n* Added validation for memory alignment in MoE inputs, outputs, and\nbiases.\n* Improved rounding utilities to support a broader range of integral\nvalues.\n\n* **Tests**\n* Added regression coverage confirming that improperly aligned inputs\nproduce a clear diagnostic.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n\n---------\n\nSigned-off-by: Haobin Guo <haobing@nvidia.com>"},"path":{"kind":"string","value":"csrc/nv_internal/include/tensorrt_llm/common/cudaUtils.h"},"language":{"kind":"string","value":"cpp"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights\n * reserved. SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#pragma once\n\n#include <cublasLt.h>\n#include <cublas_v2.h>\n#include <cuda.h>\n#include <cuda_runtime.h>\n#include <driver_types.h>\n\n#include <algorithm>\n#include <cassert>\n#include <cinttypes>\n#include <fstream>\n#include <iomanip>\n#include <memory>\n#include <optional>\n#include <sstream>\n#include <string>\n\n#include \"tensorrt_llm/common/cudaBf16Wrapper.h\"\n#include \"tensorrt_llm/common/cudaDriverWrapper.h\"\n#include \"tensorrt_llm/common/cudaFp8Utils.h\"\n#include \"tensorrt_llm/common/logger.h\"\n#include \"tensorrt_llm/common/tllmException.h\"\n#ifndef _WIN32 // Linux\n#include <sys/sysinfo.h>\n#endif // not WIN32\n#include <vector>\n#ifdef _WIN32 // Windows\n#include <windows.h>\n#undef ERROR // A Windows header file defines ERROR as 0, but it's used in our logger.h enum.\n // Logging breaks without this undef.\n#endif // WIN32\n\nnamespace tensorrt_llm::common {\n\n// workspace for cublas gemm : 32MB\n#define CUBLAS_WORKSPACE_SIZE 33554432\n\ntypedef struct __align__(4) {\n half x, y, z, w;\n}\n\nhalf4;\n\n/* **************************** type definition ***************************** */\n\nenum CublasDataType {\n FLOAT_DATATYPE = 0,\n HALF_DATATYPE = 1,\n BFLOAT16_DATATYPE = 2,\n INT8_DATATYPE = 3,\n FP8_DATATYPE = 4\n};\n\nenum TRTLLMCudaDataType { FP32 = 0, FP16 = 1, BF16 = 2, INT8 = 3, FP8 = 4 };\n\nenum class OperationType { FP32, FP16, BF16, INT8, FP8 };\n\n/* **************************** debug tools ********************************* */\nstatic char const* _cudaGetErrorEnum(cudaError_t error) { return cudaGetErrorString(error); }\n\nstatic char const* _cudaGetErrorEnum(cublasStatus_t error) {\n switch (error) {\n case CUBLAS_STATUS_SUCCESS:\n return \"CUBLAS_STATUS_SUCCESS\";\n\n case CUBLAS_STATUS_NOT_INITIALIZED:\n return \"CUBLAS_STATUS_NOT_INITIALIZED\";\n\n case CUBLAS_STATUS_ALLOC_FAILED:\n return \"CUBLAS_STATUS_ALLOC_FAILED\";\n\n case CUBLAS_STATUS_INVALID_VALUE:\n return \"CUBLAS_STATUS_INVALID_VALUE\";\n\n case CUBLAS_STATUS_ARCH_MISMATCH:\n return \"CUBLAS_STATUS_ARCH_MISMATCH\";\n\n case CUBLAS_STATUS_MAPPING_ERROR:\n return \"CUBLAS_STATUS_MAPPING_ERROR\";\n\n case CUBLAS_STATUS_EXECUTION_FAILED:\n return \"CUBLAS_STATUS_EXECUTION_FAILED\";\n\n case CUBLAS_STATUS_INTERNAL_ERROR:\n return \"CUBLAS_STATUS_INTERNAL_ERROR\";\n\n case CUBLAS_STATUS_NOT_SUPPORTED:\n return \"CUBLAS_STATUS_NOT_SUPPORTED\";\n\n case CUBLAS_STATUS_LICENSE_ERROR:\n return \"CUBLAS_STATUS_LICENSE_ERROR\";\n }\n return \"<unknown>\";\n}\n\ntemplate <typename T>\nvoid check(T ptr, char const* const func, char const* const file, int const line) {\n if (ptr) {\n throw TllmException(\n file, line,\n fmtstr(\"[TensorRT-LLM][ERROR] CUDA runtime error in %s: %s\", func, _cudaGetErrorEnum(ptr))\n .c_str());\n }\n}\n\ntemplate <typename T>\nvoid checkEx(T ptr, std::initializer_list<T> const& validReturns, char const* const func,\n char const* const file, int const line) {\n if (std::all_of(std::begin(validReturns), std::end(validReturns),\n [&ptr](T const& t) { return t != ptr; })) {\n throw TllmException(\n file, line,\n fmtstr(\"[TensorRT-LLM][ERROR] CUDA runtime error in %s: %s\", func, _cudaGetErrorEnum(ptr))\n .c_str());\n }\n}\n\n#define check_cuda_error(val) check((val), #val, __FILE__, __LINE__)\n#define check_cuda_error_2(val, file, line) check((val), #val, file, line)\n\ninline std::optional<bool> isCudaLaunchBlocking() {\n thread_local bool firstCall = true;\n thread_local std::optional<bool> result = std::nullopt;\n if (!firstCall) {\n char const* env = std::getenv(\"CUDA_LAUNCH_BLOCKING\");\n if (env != nullptr && std::string(env) == \"1\") {\n result = true;\n } else {\n result = false;\n }\n firstCall = false;\n }\n return result;\n}\n\ninline bool isCapturing(cudaStream_t stream) {\n cudaStreamCaptureStatus status;\n check_cuda_error(cudaStreamIsCapturing(stream, &status));\n return status == cudaStreamCaptureStatus::cudaStreamCaptureStatusActive;\n}\n\ninline bool doCheckError(cudaStream_t stream) {\n auto const cudaLaunchBlocking = isCudaLaunchBlocking();\n if (cudaLaunchBlocking.has_value() && cudaLaunchBlocking.value()) {\n return !isCapturing(stream);\n }\n\n#ifndef NDEBUG\n // Debug builds will sync when we're not capturing unless explicitly\n // disabled.\n bool const checkError = cudaLaunchBlocking.value_or(!isCapturing(stream));\n#else\n bool const checkError = cudaLaunchBlocking.value_or(false);\n#endif\n\n return checkError;\n}\n\ninline void syncAndCheck(cudaStream_t stream, char const* const file, int const line) {\n if (doCheckError(stream)) {\n cudaStreamSynchronize(stream);\n check(cudaGetLastError(), \"cudaGetLastError\", file, line);\n }\n}\n\n#define sync_check_cuda_error(stream) tensorrt_llm::common::syncAndCheck(stream, __FILE__, __LINE__)\n\n#define PRINT_FUNC_NAME_() \\\n do { \\\n std::cout << \"[TensorRT-LLM][CALL] \" << __FUNCTION__ << \" \" << std::endl; \\\n } while (0)\n\n// clang-format off\ntemplate<typename T> struct packed_type;\ntemplate <> struct packed_type<float> { using type = float; }; // we don't need to pack float by default\ntemplate <> struct packed_type<half> { using type = half2; };\n\n#ifdef ENABLE_BF16\ntemplate<>\nstruct packed_type<__nv_bfloat16> {\n using type = __nv_bfloat162;\n};\n#endif\n\n#ifdef ENABLE_FP8\ntemplate<>\nstruct packed_type<__nv_fp8_e4m3> {\n using type = __nv_fp8x2_e4m3;\n};\n#endif\n\ntemplate<typename T> struct num_elems;\ntemplate <> struct num_elems<float> { static constexpr int value = 1; };\ntemplate <> struct num_elems<float2> { static constexpr int value = 2; };\ntemplate <> struct num_elems<float4> { static constexpr int value = 4; };\ntemplate <> struct num_elems<half> { static constexpr int value = 1; };\ntemplate <> struct num_elems<half2> { static constexpr int value = 2; };\n#ifdef ENABLE_BF16\ntemplate <> struct num_elems<__nv_bfloat16> { static constexpr int value = 1; };\ntemplate <> struct num_elems<__nv_bfloat162> { static constexpr int value = 2; };\n#endif\n#ifdef ENABLE_FP8\ntemplate <> struct num_elems<__nv_fp8_e4m3> { static constexpr int value = 1; };\ntemplate <> struct num_elems<__nv_fp8x2_e4m3> { static constexpr int value = 2; };\n#endif\n\ntemplate<typename T, int num> struct packed_as;\ntemplate<typename T> struct packed_as<T, 1> { using type = T; };\ntemplate<> struct packed_as<half, 2> { using type = half2; };\ntemplate<> struct packed_as<float, 2> { using type = float2; };\ntemplate<> struct packed_as<int8_t, 2> { using type = int16_t; };\ntemplate<> struct packed_as<int32_t, 2> { using type = int2; };\ntemplate<> struct packed_as<half2, 1> { using type = half; };\ntemplate<> struct packed_as<float2, 1> { using type = float; };\n#ifdef ENABLE_BF16\ntemplate<> struct packed_as<__nv_bfloat16, 2> { using type = __nv_bfloat162; };\ntemplate<> struct packed_as<__nv_bfloat162, 1> { using type = __nv_bfloat16; };\n#endif\n#ifdef ENABLE_FP8\ntemplate<> struct packed_as<__nv_fp8_e4m3, 2> { using type = __nv_fp8x2_e4m3; };\ntemplate<> struct packed_as<__nv_fp8x2_e4m3, 1> { using type = __nv_fp8_e4m3; };\ntemplate<> struct packed_as<__nv_fp8_e5m2, 2> { using type = __nv_fp8x2_e5m2; };\ntemplate<> struct packed_as<__nv_fp8x2_e5m2, 1> { using type = __nv_fp8_e5m2; };\n#endif\n\ninline __device__ float2 operator*(float2 a, float2 b) { return make_float2(a.x * b.x, a.y * b.y); }\ninline __device__ float2 operator+(float2 a, float2 b) { return make_float2(a.x + b.x, a.y + b.y); }\ninline __device__ float2 operator-(float2 a, float2 b) { return make_float2(a.x - b.x, a.y - b.y); }\n\ninline __device__ float2 operator*(float2 a, float b) { return make_float2(a.x * b, a.y * b); }\ninline __device__ float2 operator+(float2 a, float b) { return make_float2(a.x + b, a.y + b); }\ninline __device__ float2 operator-(float2 a, float b) { return make_float2(a.x - b, a.y - b); }\n\n// clang-format on\n\ntemplate <typename T>\nstruct CudaDataType {};\n\ntemplate <>\nstruct CudaDataType<float> {\n static constexpr cudaDataType_t value = cudaDataType::CUDA_R_32F;\n};\n\ntemplate <>\nstruct CudaDataType<half> {\n static constexpr cudaDataType_t value = cudaDataType::CUDA_R_16F;\n};\n\n#ifdef ENABLE_BF16\ntemplate <>\nstruct CudaDataType<__nv_bfloat16> {\n static constexpr cudaDataType_t value = cudaDataType::CUDA_R_16BF;\n};\n#endif\n\ninline int getSMVersion() {\n int device{-1};\n check_cuda_error(cudaGetDevice(&device));\n int sm_major = 0;\n int sm_minor = 0;\n check_cuda_error(cudaDeviceGetAttribute(&sm_major, cudaDevAttrComputeCapabilityMajor, device));\n check_cuda_error(cudaDeviceGetAttribute(&sm_minor, cudaDevAttrComputeCapabilityMinor, device));\n return sm_major * 10 + sm_minor;\n}\n\ninline int getDevice() {\n int deviceID{0};\n check_cuda_error(cudaGetDevice(&deviceID));\n return deviceID;\n}\n\ninline int getDeviceCount() {\n int count{0};\n check_cuda_error(cudaGetDeviceCount(&count));\n return count;\n}\n\n/// @brief Identifies the memory type of the given pointer.\ntemplate <typename T>\ncudaMemoryType getPtrCudaMemoryType(T* ptr) {\n cudaPointerAttributes attributes{};\n check_cuda_error(cudaPointerGetAttributes(&attributes, ptr));\n return attributes.type;\n}\n\n/// Get the memory info\n/// \\return The free and total amount of memory in bytes\ninline std::tuple<size_t, size_t> getDeviceMemoryInfo(bool const useUvm) {\n if (useUvm) {\n size_t freeSysMem = 0;\n size_t totalSysMem = 0;\n#ifndef _WIN32 // Linux\n struct sysinfo info{};\n\n sysinfo(&info);\n totalSysMem = info.totalram * info.mem_unit;\n freeSysMem = info.freeram * info.mem_unit;\n#else // Windows\n MEMORYSTATUSEX memInfo;\n memInfo.dwLength = sizeof(memInfo);\n GlobalMemoryStatusEx(&memInfo);\n totalSysMem = memInfo.ullTotalPhys;\n freeSysMem = memInfo.ullAvailPhys;\n#endif // WIN32\n\n TLLM_LOG_INFO(\n \"Using UVM based system memory for KV cache, total memory %0.2f GB, available memory %0.2f \"\n \"GB\",\n ((double)totalSysMem / 1e9), ((double)freeSysMem / 1e9));\n return {freeSysMem, totalSysMem};\n }\n\n size_t free = 0;\n size_t total = 0;\n check_cuda_error(cudaMemGetInfo(&free, &total));\n TLLM_LOG_DEBUG(\"Using GPU memory for KV cache, total memory %0.2f GB, available memory %0.2f GB\",\n ((double)total / 1e9), ((double)free / 1e9));\n return {free, total};\n}\n\n/// @brief Gets the memory allocation granularity for the current device.\n///\n/// @return size_t The size of the smallest difference in memory size supported by the current\n/// device.\ninline size_t getAllocationGranularity() {\n auto const currentDevice = getDevice();\n ::CUmemAllocationProp prop = {};\n\n prop.type = ::CU_MEM_ALLOCATION_TYPE_PINNED;\n prop.location.type = ::CU_MEM_LOCATION_TYPE_DEVICE;\n prop.location.id = currentDevice;\n prop.requestedHandleTypes = ::CU_MEM_HANDLE_TYPE_NONE;\n\n // Get the minimum granularity supported for allocation with cuMemCreate()\n size_t granularity = 0;\n TLLM_CU_CHECK(\n cuMemGetAllocationGranularity(&granularity, &prop, CU_MEM_ALLOC_GRANULARITY_MINIMUM));\n return granularity;\n}\n\ninline int getMultiProcessorCount() {\n int nSM{0};\n int deviceID{0};\n check_cuda_error(cudaGetDevice(&deviceID));\n check_cuda_error(cudaDeviceGetAttribute(&nSM, cudaDevAttrMultiProcessorCount, deviceID));\n return nSM;\n}\n\ninline int getMaxSharedMemoryPerSM() {\n int nByteMaxSharedMemoryPerSM{0};\n int deviceID{0};\n check_cuda_error(cudaGetDevice(&deviceID));\n check_cuda_error(cudaDeviceGetAttribute(&nByteMaxSharedMemoryPerSM,\n cudaDevAttrMaxSharedMemoryPerMultiprocessor, deviceID));\n return nByteMaxSharedMemoryPerSM;\n}\n\ninline int getMaxSharedMemoryPerBlockOptin() {\n int nByteMaxSharedMemoryPerBlockOptin{0};\n int deviceID{0};\n check_cuda_error(cudaGetDevice(&deviceID));\n check_cuda_error(cudaDeviceGetAttribute(&nByteMaxSharedMemoryPerBlockOptin,\n cudaDevAttrMaxSharedMemoryPerBlockOptin, deviceID));\n return nByteMaxSharedMemoryPerBlockOptin;\n}\n\ntemplate <typename T1, typename T2>\ninline size_t divUp(T1 const& a, T2 const& b) {\n auto const tmp_a = static_cast<size_t>(a);\n auto const tmp_b = static_cast<size_t>(b);\n return (tmp_a + tmp_b - 1) / tmp_b;\n}\n\ninline int roundUp(int a, int b) { return divUp(a, b) * b; }\n\ntemplate <typename T, typename U, typename = std::enable_if_t<std::is_integral<T>::value>,\n typename = std::enable_if_t<std::is_integral<U>::value>>\nauto constexpr ceilDiv(T numerator, U denominator) {\n return (numerator + denominator - 1) / denominator;\n}\n\ntemplate <typename T>\nvoid printArrayInfo(T const* ptr, uint64_t nElement = 1, std::string name = \"\",\n bool const bPrintElement = false) {\n if (ptr == nullptr) {\n TLLM_LOG_WARNING(\"%s is an nullptr, skip!\", name.c_str());\n return;\n }\n cudaDeviceSynchronize();\n check_cuda_error(cudaGetLastError());\n\n bool const isDevicePtr = (getPtrCudaMemoryType(ptr) == cudaMemoryTypeDevice);\n size_t sizeInByte = sizeof(T) * nElement;\n TLLM_LOG_TRACE(\"addr=%p, location=%s, sizeof(T)=%lu, nElement=%d, sizeInByte=%lu\\n\", ptr,\n (isDevicePtr ? \"Device\" : \"Host\"), sizeof(T), nElement, sizeInByte);\n T* tmp = const_cast<T*>(ptr);\n std::vector<T> tmpVec; // For device pointer\n if (isDevicePtr) {\n tmpVec.resize(nElement);\n tmp = tmpVec.data();\n check_cuda_error(cudaMemcpy(tmp, ptr, sizeInByte, cudaMemcpyDeviceToHost));\n cudaDeviceSynchronize();\n }\n\n size_t nInf = 0;\n size_t nNaN = 0;\n size_t nZero = 0;\n double sum = 0.0;\n double sqrSum = 0.0;\n double absSum = 0.0;\n float allMax = -1.0e6f;\n float allMin = 1.0e6f;\n float allSad = 0.0f; // Sum Abs of Difference, to distinguish A and its transpose\n float old = 0.0f;\n for (uint64_t i = 0; i < nElement; i++) {\n float val = (float)tmp[i];\n\n if (std::isinf(val)) {\n nInf++;\n continue;\n }\n if (std::isnan(val)) {\n nNaN++;\n continue;\n }\n nZero += (val == 0.0f);\n sum += val;\n sqrSum += val * val;\n absSum += expf(val);\n allMax = std::max(allMax, val);\n allMin = std::min(allMin, val);\n allSad += abs(val - old);\n old = val;\n }\n float avg = sum / nElement;\n float std = sqrtf(sqrSum / nElement - avg * avg);\n\n TLLM_LOG_INFO(\"%s\", name.c_str());\n TLLM_LOG_INFO(\"size=%u, nInf=%zu, nNaN=%zu, nZero=%zu\", nElement, nInf, nNaN, nZero);\n TLLM_LOG_INFO(\"avg=%f, absSum: %f, std=%f, max=%f, min=%f, sad=%f\", avg, absSum, std, allMax,\n allMin, allSad);\n\n if (bPrintElement) {\n uint64_t constexpr nHead = 5;\n std::stringstream ss;\n ss << std::setw(10) << std::fixed << std::setprecision(3);\n for (uint64_t i = 0; i < std::min(nElement, nHead); ++i) {\n ss << (float)tmp[i] << \", \";\n }\n if (nElement > nHead) {\n ss << \" ... \";\n for (uint64_t i = nElement - nHead; i < nElement; ++i) {\n ss << (float)tmp[i] << \", \";\n }\n }\n TLLM_LOG_INFO(\"%s\", ss.str().c_str());\n }\n cudaDeviceSynchronize();\n check_cuda_error(cudaGetLastError());\n}\n\ntemplate void printArrayInfo(float const* ptr, uint64_t nElement, std::string name,\n bool const bPrintElement);\ntemplate void printArrayInfo(half const* ptr, uint64_t nElement, std::string name,\n bool const bPrintElement);\n#ifdef ENABLE_BF16\ntemplate void printArrayInfo(__nv_bfloat16 const* ptr, uint64_t nElement, std::string name,\n bool const bPrintElement);\n#endif\n#ifdef ENABLE_FP8\ntemplate void printArrayInfo(__nv_fp8_e4m3 const* ptr, uint64_t nElement, std::string name,\n bool const bPrintElement);\n#endif\ntemplate void printArrayInfo(uint32_t const* ptr, uint64_t nElement, std::string name,\n bool const bPrintElement);\ntemplate void printArrayInfo(uint64_t const* ptr, uint64_t nElement, std::string name,\n bool const bPrintElement);\ntemplate void printArrayInfo(int const* ptr, uint64_t nElement, std::string name,\n bool const bPrintElement);\ntemplate void printArrayInfo(uint8_t const* ptr, uint64_t nElement, std::string name,\n bool const bPrintElement);\n\ntemplate <typename T>\nvoid printToStream(T const* ptr, int const nElement, FILE* strm) {\n bool const split_rows = (strm == stdout);\n if (ptr == nullptr) {\n TLLM_LOG_WARNING(\"Nullptr, skip!\\n\");\n return;\n }\n std::vector<T> tmp(nElement, 0);\n check_cuda_error(cudaMemcpy(tmp.data(), ptr, sizeof(T) * nElement, cudaMemcpyDeviceToHost));\n for (int i = 0; i < nElement; ++i) {\n fprintf(strm, \"%f, \", static_cast<float>(tmp[i]));\n if (split_rows && ((i + 1) % 10) == 0) fprintf(strm, \"\\n\");\n }\n if (!split_rows || (nElement % 10) != 0) {\n fprintf(strm, \"\\n\");\n }\n}\n\ntemplate <typename T>\nvoid printToScreen(T const* ptr, int const nElement) {\n printToStream(ptr, nElement, stdout);\n}\n\ntemplate <typename T>\nvoid print2dToStream(T const* ptr, int const nRow, int const nCol, int const nStride, FILE* strm) {\n if (ptr == nullptr) {\n TLLM_LOG_WARNING(\"Nullptr, skip!\\n\");\n return;\n }\n for (int ri = 0; ri < nRow; ++ri) {\n T const* tmp = ptr + ri * nStride;\n printToStream(tmp, nCol, strm);\n }\n fprintf(strm, \"\\n\");\n}\n\ntemplate <typename T>\nvoid print2dToScreen(T const* ptr, int const nRow, int const nCol, int const nStride) {\n print2dToStream(ptr, nRow, nCol, nStride, stdout);\n}\n\ntemplate <typename T>\nvoid print2dToFile(std::string fname, T const* ptr, int const nRow, int const nCol,\n int const nStride) {\n FILE* fp = fopen(fname.c_str(), \"wt\");\n if (fp != nullptr) {\n print2dToStream(ptr, nRow, nCol, nStride, fp);\n fclose(fp);\n }\n}\n\n__host__ __device__ inline void print_float_(float x) { printf(\"%7.3f \", x); }\n\n__host__ __device__ inline void print_element_(float x) { print_float_(x); }\n\n__host__ __device__ inline void print_element_(half x) { print_float_((float)x); }\n\n#ifdef ENABLE_BF16\n__host__ __device__ inline void print_element_(__nv_bfloat16 x) { print_float_((float)x); }\n#endif\n\n#ifdef ENABLE_FP8\n__host__ __device__ inline void print_element_(__nv_fp8_e4m3 x) { print_float_((float)x); }\n#endif\n\n__host__ __device__ inline void print_element_(uint8_t ui) {\n printf(\"%7\" PRIu32 \" \", (unsigned int)ui);\n}\n\n__host__ __device__ inline void print_element_(uint32_t ul) { printf(\"%7\" PRIu32 \" \", ul); }\n\n__host__ __device__ inline void print_element_(uint64_t ull) { printf(\"%7\" PRIu64 \" \", ull); }\n\n__host__ __device__ inline void print_element_(int32_t il) { printf(\"%7\" PRId32 \" \", il); }\n\n__host__ __device__ inline void print_element_(int64_t ill) { printf(\"%7\" PRId64 \" \", ill); }\n\ntemplate <typename T>\n__host__ __device__ inline void print_elements(T const* ptr, int nRow, int nCol, int nStride) {\n for (int iRow = -1; iRow < nRow; ++iRow) {\n if (iRow >= 0) {\n printf(\"%07d|\", iRow);\n } else {\n printf(\" |\"); // heading row\n }\n for (int iCol = 0; iCol < nCol; iCol += 1) {\n if (iRow >= 0) {\n print_element_(ptr[iRow * nStride + iCol]);\n } else {\n printf(\"%7d|\", iCol); // heading colume\n }\n }\n printf(\"\\n\");\n }\n printf(\"\\n\");\n}\n\ntemplate <typename T>\ninline void printMatrix(T const* ptr, int nRow, int nCol, int nStride) {\n // `nRow` is length of row dimension\n // `nStride` is length of column dimension\n // `nCol` (<= nStride) is length for print per row\n if (ptr == nullptr) {\n TLLM_LOG_WARNING(\"Nullptr, skip!\\n\");\n return;\n }\n cudaDeviceSynchronize();\n check_cuda_error(cudaGetLastError());\n\n bool const isDevicePtr = (getPtrCudaMemoryType(ptr) == cudaMemoryTypeDevice);\n size_t sizeInByte = sizeof(T) * nRow * nStride;\n TLLM_LOG_TRACE(\"addr=%p, location=%s, sizeof(T)=%lu, nRow=%d, nStride=%d, sizeInByte=%lu\\n\", ptr,\n (isDevicePtr ? \"Device\" : \"Host\"), sizeof(T), nRow, nStride, sizeInByte);\n if (isDevicePtr) {\n std::vector<T> tmpVec;\n tmpVec.resize(nRow * nStride);\n T* tmp = tmpVec.data();\n check_cuda_error(cudaMemcpy(tmp, ptr, sizeInByte, cudaMemcpyDeviceToHost));\n cudaDeviceSynchronize();\n check_cuda_error(cudaGetLastError());\n print_elements(tmp, nRow, nCol, nStride);\n } else {\n print_elements(ptr, nRow, nCol, nStride);\n }\n}\n\ntemplate void printMatrix(float const* ptr, int nRow, int nCol, int nStride);\ntemplate void printMatrix(half const* ptr, int nRow, int nCol, int nStride);\n#ifdef ENABLE_BF16\ntemplate void printMatrix(__nv_bfloat16 const* ptr, int nRow, int nCol, int nStride);\n#endif\n#ifdef ENABLE_FP8\ntemplate void printMatrix(__nv_fp8_e4m3 const* ptr, int nRow, int nCol, int nStride);\n#endif\ntemplate void printMatrix(uint32_t const* ptr, int nRow, int nCol, int nStride);\ntemplate void printMatrix(uint64_t const* ptr, int nRow, int nCol, int nStride);\ntemplate void printMatrix(int const* ptr, int nRow, int nCol, int nStride);\ntemplate void printMatrix(uint8_t const* ptr, int nRow, int nCol, int nStride);\n\ntemplate <typename T>\n__device__ inline void printMatrixDevice(T const* ptr, int nRow, int nCol, int nStride) {\n // `nRow` is length of row dimension\n // `nStride` is length of column dimension\n // `nCol` (<= nStride) is length for print per row\n // Can be called inside kernels by one single thread\n if (ptr == nullptr) {\n printf(\"Nullptr, skip!\\n\");\n return;\n }\n size_t sizeInByte = sizeof(T) * nRow * nStride;\n printf(\"addr=%p, sizeof(T)=%lu, nRow=%d, nStride=%d, sizeInByte=%lu\\n\", ptr, sizeof(T), nRow,\n nStride, sizeInByte);\n print_elements(ptr, nRow, nCol, nStride);\n}\n\ntemplate __device__ void printMatrixDevice(float const* ptr, int nRow, int nCol, int nStride);\ntemplate __device__ void printMatrixDevice(half const* ptr, int nRow, int nCol, int nStride);\n#ifdef ENABLE_BF16\ntemplate __device__ void printMatrixDevice(__nv_bfloat16 const* ptr, int nRow, int nCol,\n int nStride);\n#endif\n#ifdef ENABLE_FP8\ntemplate __device__ void printMatrixDevice(__nv_fp8_e4m3 const* ptr, int nRow, int nCol,\n int nStride);\n#endif\ntemplate __device__ void printMatrixDevice(uint32_t const* ptr, int nRow, int nCol, int nStride);\ntemplate __device__ void printMatrixDevice(uint64_t const* ptr, int nRow, int nCol, int nStride);\ntemplate __device__ void printMatrixDevice(int const* ptr, int nRow, int nCol, int nStride);\ntemplate __device__ void printMatrixDevice(uint8_t const* ptr, int nRow, int nCol, int nStride);\n\n#ifndef CUDA_CALL\n#define CUDA_CALL(answer) \\\n { \\\n gpuAssert((answer), __FILE__, __LINE__); \\\n }\n\ninline void gpuAssert(cudaError_t code, char const* file, int line, bool abort = true) {\n if (code != cudaSuccess) {\n fprintf(stderr, \"CUDA error: %s @ %s:%d\\n\", cudaGetErrorString(code), file, line);\n if (abort) exit(code);\n }\n}\n\ninline void gpuAssert(CUresult code, char const* file, int line, bool abort = true) {\n if (code != CUresult::CUDA_SUCCESS) {\n char const* buf = \"Unknown error\";\n assert(cuGetErrorString(code, &buf) == CUresult::CUDA_SUCCESS);\n fprintf(stderr, \"Driver API error: %s @ %s:%d\\n\", buf, file, line);\n if (abort) exit(code);\n }\n}\n#endif\n\ntemplate <typename T>\nstruct UpperType;\n\ntemplate <>\nstruct UpperType<int8_t> {\n using Type = int;\n};\n\ntemplate <>\nstruct UpperType<uint32_t> {\n using Type = uint32_t;\n};\n\ntemplate <>\nstruct UpperType<int> {\n using Type = int;\n};\n\ntemplate <>\nstruct UpperType<__nv_bfloat16> {\n using Type = double;\n};\n\ntemplate <>\nstruct UpperType<half> {\n using Type = double;\n};\n\ntemplate <>\nstruct UpperType<float> {\n using Type = double;\n};\n\nextern \"C\" {\n__device__ uint32_t __nvvm_get_smem_pointer(void* ptr);\n}\n\n__forceinline__ __device__ void issue_stas(uint32_t dist_barrier_ptr, uint32_t dist_buffer_ptr,\n uint32_t d0) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900) && (__CUDACC_VER_MAJOR__ >= 12))\n asm volatile(\"st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.b32 [%0], %2, [%1];\\n\\t\"\n :\n : \"r\"(dist_buffer_ptr), \"r\"(dist_barrier_ptr), \"r\"(d0));\n#endif\n}\n\n__forceinline__ __device__ void issue_stas(uint32_t dist_barrier_ptr, uint32_t dist_buffer_ptr,\n uint64_t d0) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900) && (__CUDACC_VER_MAJOR__ >= 12))\n asm volatile(\"st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.b64 [%0], %2, [%1];\\n\\t\"\n :\n : \"r\"(dist_buffer_ptr), \"r\"(dist_barrier_ptr), \"l\"(d0));\n#endif\n}\n\n__forceinline__ __device__ void issue_stas(uint32_t dist_barrier_ptr, uint32_t dist_buffer_ptr,\n uint32_t d0, uint32_t d1) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900) && (__CUDACC_VER_MAJOR__ >= 12))\n asm volatile(\n \"st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.v2.b32 [%0], {%2, %3}, [%1];\\n\\t\"\n :\n : \"r\"(dist_buffer_ptr), \"r\"(dist_barrier_ptr), \"r\"(d0), \"r\"(d1));\n#endif\n}\n\n__forceinline__ __device__ void issue_stas(uint32_t dist_barrier_ptr, uint32_t dist_buffer_ptr,\n uint32_t d0, uint32_t d1, uint32_t d2, uint32_t d3) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900) && (__CUDACC_VER_MAJOR__ >= 12))\n asm volatile(\n \"st.async.shared::cluster.mbarrier::complete_tx::bytes.v4.b32 [%0], {%2, %3, %4, %5}, \"\n \"[%1];\\n\\t\"\n :\n : \"r\"(dist_buffer_ptr), \"r\"(dist_barrier_ptr), \"r\"(d0), \"r\"(d1), \"r\"(d2), \"r\"(d3));\n#endif\n}\n\ninline __device__ uint32_t elect_one_sync() {\n uint32_t pred = 0;\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900) && (__CUDACC_VER_MAJOR__ >= 12))\n#if (defined(__CUDA_ARCH_FEAT_SM90_ALL))\n uint32_t laneid = 0;\n asm volatile(\n \"\\n\\\n {\\n\\\n .reg .b32 %rx;\\n\\\n .reg .pred %px;\\n\\\n elect.sync %rx|%px, %2;\\n\\\n @%px mov.s32 %1, 1;\\n\\\n mov.s32 %0, %rx;\\n\\\n }\\n\\\n \"\n : \"+r\"(laneid), \"+r\"(pred)\n : \"r\"(0xFFFFFFFF));\n#endif\n#endif\n return pred;\n}\n\n__forceinline__ __device__ uint32_t get_smem_pointer(void const* ptr) {\n return __nvvm_get_smem_pointer(const_cast<void*>(ptr));\n}\n\n__forceinline__ __device__ void bar_create(void* bar_ptr, int init_count) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n unsigned smem_ptr = get_smem_pointer(bar_ptr);\n\n asm volatile(\n \"{\\n\\t\"\n \"mbarrier.init.shared.b64 [%1], %0; \\n\\t\"\n \"}\"\n :\n : \"r\"(init_count), \"r\"(smem_ptr));\n#endif\n}\n\nstruct Arrive_wait {\n public:\n __forceinline__ __device__ Arrive_wait() { bar_base_ = NULL; }\n\n __forceinline__ __device__ Arrive_wait(uint64_t* bar_base, int id = 0) {\n bar_base_ = bar_base;\n id_ = id;\n }\n\n __forceinline__ __device__ int bar_peek(int id, unsigned int bar_phase) {\n uint32_t result32{};\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n auto* bar_ptr = bar_base_ + id;\n unsigned smem_ptr = get_smem_pointer(bar_ptr);\n asm volatile(\n \"{\\n\\t\"\n \".reg .pred P1; \\n\\t\"\n \"mbarrier.try_wait.parity.shared.b64 P1, [%1], %2; \\n\\t\"\n \"selp.b32 %0, 1, 0, P1; \\n\\t\"\n \"}\"\n : \"=r\"(result32)\n : \"r\"(smem_ptr), \"r\"(bar_phase));\n#endif\n return result32;\n }\n\n __forceinline__ __device__ int bar_peek(int id, unsigned int bar_phase, int pred) {\n uint32_t result32{};\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n auto* bar_ptr = bar_base_ + id;\n unsigned smem_ptr = get_smem_pointer(bar_ptr);\n asm volatile(\n \"{\\n\\t\"\n \".reg .pred P1; \\n\\t\"\n \".reg .pred P2;\\n\\t\"\n \"setp.eq.u32 P2, %3, 1;\\n\\t\"\n \"@P2 mbarrier.try_wait.parity.shared.b64 P1, [%1], %2; \\n\\t\"\n \"selp.b32 %0, 1, 0, P1; \\n\\t\"\n \"}\"\n : \"=r\"(result32)\n : \"r\"(smem_ptr), \"r\"(bar_phase), \"r\"(pred));\n#endif\n return result32;\n }\n\n __forceinline__ __device__ void bar_wait(int id, unsigned int bar_phase) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n auto* bar_ptr = bar_base_ + id;\n unsigned smem_ptr = get_smem_pointer(bar_ptr);\n asm volatile(\n \"{\\n\\t\"\n \".reg .pred P1; \\n\\t\"\n \"LAB_WAIT: \\n\\t\"\n \"mbarrier.try_wait.parity.acquire.cta.shared::cta.b64 P1, [%0], %1; \\n\\t\"\n \"@P1 bra.uni DONE; \\n\\t\"\n \"bra.uni LAB_WAIT; \\n\\t\"\n \"DONE: \\n\\t\"\n \"}\"\n :\n : \"r\"(smem_ptr), \"r\"(bar_phase));\n#endif\n }\n\n __forceinline__ __device__ void bar_arrive_dsmem(int const& id) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n auto* bar_ptr = bar_base_ + id;\n asm volatile(\n \"{\\n\\t\"\n \"mbarrier.arrive.b64 _, [%0];\\n\\t\"\n \"}\"\n :\n : \"l\"(bar_ptr));\n#endif\n }\n\n __forceinline__ __device__ void bar_arrive_dsmem(int const& id, uint32_t const& pred) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n asm volatile(\n \"{\\n\\t\"\n \" .reg .pred p;\\n\\t\"\n \" .reg .s64 addr;\\n\\t\"\n \" .reg .b64 tmp;\\n\\t\"\n \" setp.eq.u32 p, %2, 1;\\n\\t\"\n \" mul.wide.s32 tmp, %0, 8;\\n\\t\"\n \" add.s64 addr, tmp, %1;\\n\\t\"\n \"@p mbarrier.arrive.b64 _, [addr];\\n\\t\"\n \"}\"\n :\n : \"r\"(id), \"l\"(bar_base_), \"r\"(pred));\n#endif\n }\n\n // Sets up the base address for arrival with the correct ctaid in cga\n __forceinline__ __device__ void set_bar_base_dsmem(uint32_t const& cta_id) {\n bar_base_ = reinterpret_cast<uint64_t*>(\n (reinterpret_cast<uintptr_t>(bar_base_) & 0xFFFFFFFFF0FFFFFFULL) + (cta_id << 24));\n }\n\n __forceinline__ __device__ void bar_arrive_normal(int id, bool flag = true) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n if (flag == true) {\n uint64_t* bar_ptr = reinterpret_cast<uint64_t*>(bar_base_ + id);\n unsigned smem_ptr = get_smem_pointer(bar_ptr);\n asm volatile(\n \"{\\n\\t\"\n \".reg .b64 state; \\n\\t\"\n \"mbarrier.arrive.shared.b64 state, [%0];\\n\\t\"\n \"}\"\n :\n : \"r\"(smem_ptr));\n }\n#endif\n }\n\n __forceinline__ __device__ void bar_arrive_set_transactioncnt(int id, int expected_copy_bytes) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n auto* bar_ptr = bar_base_ + id;\n unsigned smem_ptr = get_smem_pointer(bar_ptr);\n asm volatile(\n \"{\\n\\t\"\n \"mbarrier.arrive.expect_tx.shared.b64 _, [%0], %1; \\n\\t\"\n \"}\"\n :\n : \"r\"(smem_ptr), \"r\"(expected_copy_bytes));\n#endif\n }\n\n __forceinline__ __device__ void bar_arrive_set_transactioncnt(int id, int expected_copy_bytes,\n uint32_t pred) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n auto* bar_ptr = bar_base_ + id;\n unsigned smem_ptr = get_smem_pointer(bar_ptr);\n asm volatile(\n \"{\\n\\t\"\n \".reg .pred p;\\n\\t\"\n \"setp.eq.u32 p, %2, 1;\\n\\t\"\n \"@p mbarrier.arrive.expect_tx.shared.b64 _, [%0], %1; \\n\\t\"\n \"}\"\n :\n : \"r\"(smem_ptr), \"r\"(expected_copy_bytes), \"r\"(pred));\n#endif\n }\n\n __forceinline__ __device__ uint64_t* bar_base() { return bar_base_; }\n\n __forceinline__ __device__ uint64_t* get_bar_addr(int id) { return bar_base_ + id; }\n\n private:\n // smem barrier base pointer\n uint64_t* bar_base_;\n // barrier id\n int id_;\n};\n\n__forceinline__ __device__ void cga_sync() {\n#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 900\n asm volatile(\"barrier.cluster.sync;\\n\" : :);\n#endif\n}\n\n__forceinline__ __device__ void cga_arrive() {\n#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 900\n asm volatile(\"barrier.cluster.arrive.aligned;\\n\" : :);\n#endif\n}\n\n__forceinline__ __device__ void cga_wait() {\n#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 900\n asm volatile(\"barrier.cluster.wait.aligned;\\n\" : :);\n#endif\n}\n\ninline __device__ void fence_view_async_shared() {\n // only compiles on sm90+\n\n#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 900\n asm volatile(\"fence.proxy.async.shared::cta;\\n\" : :);\n#endif\n}\n\ntemplate <typename T>\n__forceinline__ __device__ T* get_DSMEM_ptr(T* localAddress, uint32_t destCtaId) {\n T* dsmemAddress = reinterpret_cast<T*>(\n ((unsigned long long int)localAddress & 0xFFFFFFFFF0FFFFFFULL) + (destCtaId << 24));\n return dsmemAddress;\n}\n\ntemplate <typename T>\n__forceinline__ __device__ void write_DSMEM_Address(T* localAddress, uint32_t destCtaId, T val) {\n T* dsmemAddress = get_DSMEM_ptr(localAddress, destCtaId);\n *dsmemAddress = val;\n}\n\n__forceinline__ __device__ void arrive_barrier(uint64_t* p_barrier, uint32_t arrive_cnt = 1) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n asm volatile(\"{mbarrier.arrive.shared.b64 _, [%0],%1;\\n\\t}\"\n :\n : \"l\"(p_barrier), \"r\"(arrive_cnt));\n#endif\n}\n\n__forceinline__ __device__ void arrive_DSMEM_barrier(uint64_t* p_barrier, uint32_t ctaid) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n uint64_t* p_barrier_remote = get_DSMEM_ptr(p_barrier, ctaid);\n asm volatile(\"{mbarrier.arrive.b64 _, [%0];\\n\\t}\" : : \"l\"(p_barrier_remote));\n#endif\n}\n\n__forceinline__ __device__ void arrive_DSMEM_barrier_and_set_tx_cnt(uint64_t* p_barrier,\n uint32_t ctaid,\n uint32_t expected_copy_bytes) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n uint32_t p_bar =\n static_cast<uint32_t>(reinterpret_cast<uintptr_t>(get_DSMEM_ptr(p_barrier, ctaid)));\n asm volatile(\"{mbarrier.arrive.expect_tx.b64 _, [%0], %1; \\n\\t}\" ::\"r\"(p_bar),\n \"r\"(expected_copy_bytes));\n#endif\n}\n\ntemplate <bool barSetTxCnt = true>\n__forceinline__ __device__ void stas(uint32_t* p_data, uint64_t* p_barrier, uint32_t ctaid,\n uint32_t const& wrdat) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n if (barSetTxCnt) arrive_DSMEM_barrier_and_set_tx_cnt(p_barrier, ctaid, sizeof(uint32_t));\n uint32_t buffer_ptr = static_cast<uint32_t>(reinterpret_cast<uintptr_t>(p_data));\n uint32_t barrier_ptr = static_cast<uint32_t>(reinterpret_cast<uintptr_t>(p_barrier));\n\n uint32_t buffer_ptr_, barrier_ptr_;\n asm volatile(\n \"{\\n\\t\"\n \"setctarank.shared.u32 %0, %2, %4;\\n\\t\"\n \"setctarank.shared.u32 %1, %3, %4;\\n\\t\"\n \"}\"\n : \"=r\"(buffer_ptr_), \"=r\"(barrier_ptr_)\n : \"r\"(buffer_ptr), \"r\"(barrier_ptr), \"r\"(ctaid));\n issue_stas(buffer_ptr_, barrier_ptr_, wrdat);\n#endif\n}\n\ntemplate <bool barSetTxCnt = true>\n__forceinline__ __device__ void stas(uint64_t* p_data, uint64_t* p_barrier, uint32_t ctaid,\n uint64_t const& wrdat) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n if (barSetTxCnt) arrive_DSMEM_barrier_and_set_tx_cnt(p_barrier, ctaid, sizeof(uint64_t));\n uint32_t buffer_ptr = static_cast<uint32_t>(reinterpret_cast<uintptr_t>(p_data));\n uint32_t barrier_ptr = static_cast<uint32_t>(reinterpret_cast<uintptr_t>(p_barrier));\n\n uint32_t buffer_ptr_, barrier_ptr_;\n asm volatile(\n \"{\\n\\t\"\n \"setctarank.shared.u32 %0, %2, %4;\\n\\t\"\n \"setctarank.shared.u32 %1, %3, %4;\\n\\t\"\n \"}\"\n : \"=r\"(buffer_ptr_), \"=r\"(barrier_ptr_)\n : \"r\"(buffer_ptr), \"r\"(barrier_ptr), \"r\"(ctaid));\n issue_stas(buffer_ptr_, barrier_ptr_, wrdat);\n#endif\n}\n\ntemplate <bool barSetTxCnt = true>\n__forceinline__ __device__ void stas(uint64_t* p_data, uint64_t* p_barrier, uint32_t ctaid,\n uint32_t const wrdat0, uint32_t const wrdat1,\n uint32_t const wrdat2, uint32_t const wrdat3) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n if (barSetTxCnt) arrive_DSMEM_barrier_and_set_tx_cnt(p_barrier, ctaid, 4 * sizeof(uint32_t));\n uint32_t buffer_ptr = static_cast<uint32_t>(reinterpret_cast<uintptr_t>(p_data));\n uint32_t barrier_ptr = static_cast<uint32_t>(reinterpret_cast<uintptr_t>(p_barrier));\n\n uint32_t buffer_ptr_, barrier_ptr_;\n asm volatile(\n \"{\\n\\t\"\n \"setctarank.shared.u32 %0, %2, %4;\\n\\t\"\n \"setctarank.shared.u32 %1, %3, %4;\\n\\t\"\n \"}\"\n : \"=r\"(buffer_ptr_), \"=r\"(barrier_ptr_)\n : \"r\"(buffer_ptr), \"r\"(barrier_ptr), \"r\"(ctaid));\n issue_stas(buffer_ptr_, barrier_ptr_, wrdat0, wrdat1, wrdat2, wrdat3);\n#endif\n}\n\ntemplate <bool barSetTxCnt = true, bool assumeAligned = true, typename T = void>\n__forceinline__ __device__ void stas(T* p_data, uint64_t* p_barrier, uint32_t ctaid,\n T const& wrdat) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n static_assert(sizeof(T) % 4 == 0);\n if (barSetTxCnt) arrive_DSMEM_barrier_and_set_tx_cnt(p_barrier, ctaid, sizeof(T));\n\n uint32_t buffer_ptr = static_cast<uint32_t>(reinterpret_cast<uintptr_t>(p_data));\n uint32_t barrier_ptr = static_cast<uint32_t>(reinterpret_cast<uintptr_t>(p_barrier));\n\n uint32_t buffer_ptr_, barrier_ptr_;\n asm volatile(\n \"{\\n\\t\"\n \"setctarank.shared.u32 %0, %2, %4;\\n\\t\"\n \"setctarank.shared.u32 %1, %3, %4;\\n\\t\"\n \"}\"\n : \"=r\"(buffer_ptr_), \"=r\"(barrier_ptr_)\n : \"r\"(buffer_ptr), \"r\"(barrier_ptr), \"r\"(ctaid));\n\n uint32_t const* p_wrdat_b32 = reinterpret_cast<uint32_t const*>(&wrdat);\n\n for (uint32_t offset = 0; offset < sizeof(T);) {\n if constexpr (assumeAligned) {\n if (offset + 16 <= sizeof(T)) {\n // Use write_async_v4_b32\n issue_stas(buffer_ptr_ + offset, barrier_ptr_, p_wrdat_b32[offset / 4],\n p_wrdat_b32[offset / 4 + 1], p_wrdat_b32[offset / 4 + 2],\n p_wrdat_b32[offset / 4 + 3]);\n offset += 16;\n } else if (offset + 8 <= sizeof(T) && (buffer_ptr + offset) % 8 == 0) {\n // Use write_async_v2_b32\n issue_stas(buffer_ptr + offset, barrier_ptr_, p_wrdat_b32[offset / 4],\n p_wrdat_b32[offset / 4 + 1]);\n offset += 8;\n } else {\n issue_stas(buffer_ptr + offset, barrier_ptr_, p_wrdat_b32[offset / 4]);\n offset += 4;\n }\n } else {\n issue_stas(buffer_ptr + offset, barrier_ptr_, p_wrdat_b32[offset / 4]);\n offset += 4;\n }\n }\n#endif\n}\n\nstruct OrderedMutex {\n uint64_t barriers[2];\n\n __device__ void init(int tid0, int threads0, int threads1) {\n if (tid0) {\n bar_create(&barriers[0], threads0);\n bar_create(&barriers[1], threads1);\n }\n }\n\n OrderedMutex() = default;\n OrderedMutex(OrderedMutex const& other) = delete;\n};\n\nclass OrderedMutexAccessor {\n public:\n struct State {\n int phase = 0;\n };\n\n private:\n int _phase;\n int _id;\n Arrive_wait _barriers;\n\n public:\n __device__ OrderedMutexAccessor(OrderedMutex& m, int id, State state)\n : _phase(state.phase), _id(id), _barriers(m.barriers) {}\n\n __device__ void arrive() { _barriers.bar_arrive_normal(_id); }\n\n __device__ void wait() {\n _barriers.bar_wait(_id ^ 1, _phase);\n _phase ^= 1;\n }\n\n __device__ State exportState() { return {.phase = _phase}; }\n};\n\ntemplate <typename T, T VALUE>\nstruct ConstExprWrapper {\n static constexpr T value = VALUE;\n};\n\ntemplate <int VALUE>\nusing Int = ConstExprWrapper<int, VALUE>;\n\ntemplate <bool VALUE>\nusing Bool = ConstExprWrapper<bool, VALUE>;\n\ntemplate <bool VALUE>\nusing ConstBool = ConstExprWrapper<bool, VALUE>;\n\ntemplate <typename T>\nstruct TmaDescType;\n\ntemplate <>\nstruct TmaDescType<__nv_bfloat16> {\n static constexpr auto value = CUtensorMapDataType_enum::CU_TENSOR_MAP_DATA_TYPE_BFLOAT16;\n};\n\ntemplate <>\nstruct TmaDescType<float> {\n static constexpr auto value = CUtensorMapDataType_enum::CU_TENSOR_MAP_DATA_TYPE_FLOAT32;\n};\n\n#define DEFINE_MEMBER_CHECKER(member) \\\n template <typename T, typename V = bool> \\\n struct has_##member : std::false_type {}; \\\n template <typename T> \\\n struct has_##member< \\\n T, typename std::enable_if<!std::is_same<decltype(std::declval<T>().member), void>::value, \\\n bool>::type> : std::true_type {};\n\n#define HAS_MEMBER(C, member) has_##member<C>::value\n\nDEFINE_MEMBER_CHECKER(output)\nDEFINE_MEMBER_CHECKER(residual)\nDEFINE_MEMBER_CHECKER(bias)\nDEFINE_MEMBER_CHECKER(deq)\nDEFINE_MEMBER_CHECKER(qua)\nDEFINE_MEMBER_CHECKER(high_preciecion_normed_output)\n\n} // namespace tensorrt_llm::common\n\n/*\n * Macros compliant with TensorRT coding conventions\n */\n#define TLLM_CUDA_CHECK(stat) \\\n do { \\\n tensorrt_llm::common::check((stat), #stat, __FILE__, __LINE__); \\\n } while (0)\n\n// We use singleton memory pool and the order of destructors depends on the compiler implementation.\n// We find that the cudaFree/cudaFreeHost is called after cudaruntime destruction on Windows. There\n// will be an cudaErrorCudartUnloading error. However, it is safe to ignore this error because the\n// cuda runtime is already exited, we are no more worried about the memory leaks.\n#define TLLM_CUDA_CHECK_FREE_RESOURCE(stat) \\\n do { \\\n tensorrt_llm::common::checkEx((stat), {cudaSuccess, cudaErrorCudartUnloading}, #stat, \\\n __FILE__, __LINE__); \\\n } while (0)\n"},"after_code":{"kind":"string","value":"/*\n * SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights\n * reserved. SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#pragma once\n\n#include <cublasLt.h>\n#include <cublas_v2.h>\n#include <cuda.h>\n#include <cuda_runtime.h>\n#include <driver_types.h>\n\n#include <algorithm>\n#include <cassert>\n#include <cinttypes>\n#include <fstream>\n#include <iomanip>\n#include <memory>\n#include <optional>\n#include <sstream>\n#include <string>\n\n#include \"tensorrt_llm/common/cudaBf16Wrapper.h\"\n#include \"tensorrt_llm/common/cudaDriverWrapper.h\"\n#include \"tensorrt_llm/common/cudaFp8Utils.h\"\n#include \"tensorrt_llm/common/logger.h\"\n#include \"tensorrt_llm/common/tllmException.h\"\n#ifndef _WIN32 // Linux\n#include <sys/sysinfo.h>\n#endif // not WIN32\n#include <vector>\n#ifdef _WIN32 // Windows\n#include <windows.h>\n#undef ERROR // A Windows header file defines ERROR as 0, but it's used in our logger.h enum.\n // Logging breaks without this undef.\n#endif // WIN32\n\nnamespace tensorrt_llm::common {\n\n// workspace for cublas gemm : 32MB\n#define CUBLAS_WORKSPACE_SIZE 33554432\n\ntypedef struct __align__(4) {\n half x, y, z, w;\n}\n\nhalf4;\n\n/* **************************** type definition ***************************** */\n\nenum CublasDataType {\n FLOAT_DATATYPE = 0,\n HALF_DATATYPE = 1,\n BFLOAT16_DATATYPE = 2,\n INT8_DATATYPE = 3,\n FP8_DATATYPE = 4\n};\n\nenum TRTLLMCudaDataType { FP32 = 0, FP16 = 1, BF16 = 2, INT8 = 3, FP8 = 4 };\n\nenum class OperationType { FP32, FP16, BF16, INT8, FP8 };\n\n/* **************************** debug tools ********************************* */\nstatic char const* _cudaGetErrorEnum(cudaError_t error) { return cudaGetErrorString(error); }\n\nstatic char const* _cudaGetErrorEnum(cublasStatus_t error) {\n switch (error) {\n case CUBLAS_STATUS_SUCCESS:\n return \"CUBLAS_STATUS_SUCCESS\";\n\n case CUBLAS_STATUS_NOT_INITIALIZED:\n return \"CUBLAS_STATUS_NOT_INITIALIZED\";\n\n case CUBLAS_STATUS_ALLOC_FAILED:\n return \"CUBLAS_STATUS_ALLOC_FAILED\";\n\n case CUBLAS_STATUS_INVALID_VALUE:\n return \"CUBLAS_STATUS_INVALID_VALUE\";\n\n case CUBLAS_STATUS_ARCH_MISMATCH:\n return \"CUBLAS_STATUS_ARCH_MISMATCH\";\n\n case CUBLAS_STATUS_MAPPING_ERROR:\n return \"CUBLAS_STATUS_MAPPING_ERROR\";\n\n case CUBLAS_STATUS_EXECUTION_FAILED:\n return \"CUBLAS_STATUS_EXECUTION_FAILED\";\n\n case CUBLAS_STATUS_INTERNAL_ERROR:\n return \"CUBLAS_STATUS_INTERNAL_ERROR\";\n\n case CUBLAS_STATUS_NOT_SUPPORTED:\n return \"CUBLAS_STATUS_NOT_SUPPORTED\";\n\n case CUBLAS_STATUS_LICENSE_ERROR:\n return \"CUBLAS_STATUS_LICENSE_ERROR\";\n }\n return \"<unknown>\";\n}\n\ntemplate <typename T>\nvoid check(T ptr, char const* const func, char const* const file, int const line) {\n if (ptr) {\n throw TllmException(\n file, line,\n fmtstr(\"[TensorRT-LLM][ERROR] CUDA runtime error in %s: %s\", func, _cudaGetErrorEnum(ptr))\n .c_str());\n }\n}\n\ntemplate <typename T>\nvoid checkEx(T ptr, std::initializer_list<T> const& validReturns, char const* const func,\n char const* const file, int const line) {\n if (std::all_of(std::begin(validReturns), std::end(validReturns),\n [&ptr](T const& t) { return t != ptr; })) {\n throw TllmException(\n file, line,\n fmtstr(\"[TensorRT-LLM][ERROR] CUDA runtime error in %s: %s\", func, _cudaGetErrorEnum(ptr))\n .c_str());\n }\n}\n\n#define check_cuda_error(val) check((val), #val, __FILE__, __LINE__)\n#define check_cuda_error_2(val, file, line) check((val), #val, file, line)\n\ninline std::optional<bool> isCudaLaunchBlocking() {\n thread_local bool firstCall = true;\n thread_local std::optional<bool> result = std::nullopt;\n if (!firstCall) {\n char const* env = std::getenv(\"CUDA_LAUNCH_BLOCKING\");\n if (env != nullptr && std::string(env) == \"1\") {\n result = true;\n } else {\n result = false;\n }\n firstCall = false;\n }\n return result;\n}\n\ninline bool isCapturing(cudaStream_t stream) {\n cudaStreamCaptureStatus status;\n check_cuda_error(cudaStreamIsCapturing(stream, &status));\n return status == cudaStreamCaptureStatus::cudaStreamCaptureStatusActive;\n}\n\ninline bool doCheckError(cudaStream_t stream) {\n auto const cudaLaunchBlocking = isCudaLaunchBlocking();\n if (cudaLaunchBlocking.has_value() && cudaLaunchBlocking.value()) {\n return !isCapturing(stream);\n }\n\n#ifndef NDEBUG\n // Debug builds will sync when we're not capturing unless explicitly\n // disabled.\n bool const checkError = cudaLaunchBlocking.value_or(!isCapturing(stream));\n#else\n bool const checkError = cudaLaunchBlocking.value_or(false);\n#endif\n\n return checkError;\n}\n\ninline void syncAndCheck(cudaStream_t stream, char const* const file, int const line) {\n if (doCheckError(stream)) {\n cudaStreamSynchronize(stream);\n check(cudaGetLastError(), \"cudaGetLastError\", file, line);\n }\n}\n\n#define sync_check_cuda_error(stream) tensorrt_llm::common::syncAndCheck(stream, __FILE__, __LINE__)\n\n#define PRINT_FUNC_NAME_() \\\n do { \\\n std::cout << \"[TensorRT-LLM][CALL] \" << __FUNCTION__ << \" \" << std::endl; \\\n } while (0)\n\n// clang-format off\ntemplate<typename T> struct packed_type;\ntemplate <> struct packed_type<float> { using type = float; }; // we don't need to pack float by default\ntemplate <> struct packed_type<half> { using type = half2; };\n\n#ifdef ENABLE_BF16\ntemplate<>\nstruct packed_type<__nv_bfloat16> {\n using type = __nv_bfloat162;\n};\n#endif\n\n#ifdef ENABLE_FP8\ntemplate<>\nstruct packed_type<__nv_fp8_e4m3> {\n using type = __nv_fp8x2_e4m3;\n};\n#endif\n\ntemplate<typename T> struct num_elems;\ntemplate <> struct num_elems<float> { static constexpr int value = 1; };\ntemplate <> struct num_elems<float2> { static constexpr int value = 2; };\ntemplate <> struct num_elems<float4> { static constexpr int value = 4; };\ntemplate <> struct num_elems<half> { static constexpr int value = 1; };\ntemplate <> struct num_elems<half2> { static constexpr int value = 2; };\n#ifdef ENABLE_BF16\ntemplate <> struct num_elems<__nv_bfloat16> { static constexpr int value = 1; };\ntemplate <> struct num_elems<__nv_bfloat162> { static constexpr int value = 2; };\n#endif\n#ifdef ENABLE_FP8\ntemplate <> struct num_elems<__nv_fp8_e4m3> { static constexpr int value = 1; };\ntemplate <> struct num_elems<__nv_fp8x2_e4m3> { static constexpr int value = 2; };\n#endif\n\ntemplate<typename T, int num> struct packed_as;\ntemplate<typename T> struct packed_as<T, 1> { using type = T; };\ntemplate<> struct packed_as<half, 2> { using type = half2; };\ntemplate<> struct packed_as<float, 2> { using type = float2; };\ntemplate<> struct packed_as<int8_t, 2> { using type = int16_t; };\ntemplate<> struct packed_as<int32_t, 2> { using type = int2; };\ntemplate<> struct packed_as<half2, 1> { using type = half; };\ntemplate<> struct packed_as<float2, 1> { using type = float; };\n#ifdef ENABLE_BF16\ntemplate<> struct packed_as<__nv_bfloat16, 2> { using type = __nv_bfloat162; };\ntemplate<> struct packed_as<__nv_bfloat162, 1> { using type = __nv_bfloat16; };\n#endif\n#ifdef ENABLE_FP8\ntemplate<> struct packed_as<__nv_fp8_e4m3, 2> { using type = __nv_fp8x2_e4m3; };\ntemplate<> struct packed_as<__nv_fp8x2_e4m3, 1> { using type = __nv_fp8_e4m3; };\ntemplate<> struct packed_as<__nv_fp8_e5m2, 2> { using type = __nv_fp8x2_e5m2; };\ntemplate<> struct packed_as<__nv_fp8x2_e5m2, 1> { using type = __nv_fp8_e5m2; };\n#endif\n\ninline __device__ float2 operator*(float2 a, float2 b) { return make_float2(a.x * b.x, a.y * b.y); }\ninline __device__ float2 operator+(float2 a, float2 b) { return make_float2(a.x + b.x, a.y + b.y); }\ninline __device__ float2 operator-(float2 a, float2 b) { return make_float2(a.x - b.x, a.y - b.y); }\n\ninline __device__ float2 operator*(float2 a, float b) { return make_float2(a.x * b, a.y * b); }\ninline __device__ float2 operator+(float2 a, float b) { return make_float2(a.x + b, a.y + b); }\ninline __device__ float2 operator-(float2 a, float b) { return make_float2(a.x - b, a.y - b); }\n\n// clang-format on\n\ntemplate <typename T>\nstruct CudaDataType {};\n\ntemplate <>\nstruct CudaDataType<float> {\n static constexpr cudaDataType_t value = cudaDataType::CUDA_R_32F;\n};\n\ntemplate <>\nstruct CudaDataType<half> {\n static constexpr cudaDataType_t value = cudaDataType::CUDA_R_16F;\n};\n\n#ifdef ENABLE_BF16\ntemplate <>\nstruct CudaDataType<__nv_bfloat16> {\n static constexpr cudaDataType_t value = cudaDataType::CUDA_R_16BF;\n};\n#endif\n\ninline int getSMVersion() {\n int device{-1};\n check_cuda_error(cudaGetDevice(&device));\n int sm_major = 0;\n int sm_minor = 0;\n check_cuda_error(cudaDeviceGetAttribute(&sm_major, cudaDevAttrComputeCapabilityMajor, device));\n check_cuda_error(cudaDeviceGetAttribute(&sm_minor, cudaDevAttrComputeCapabilityMinor, device));\n return sm_major * 10 + sm_minor;\n}\n\ninline int getDevice() {\n int deviceID{0};\n check_cuda_error(cudaGetDevice(&deviceID));\n return deviceID;\n}\n\ninline int getDeviceCount() {\n int count{0};\n check_cuda_error(cudaGetDeviceCount(&count));\n return count;\n}\n\n/// @brief Identifies the memory type of the given pointer.\ntemplate <typename T>\ncudaMemoryType getPtrCudaMemoryType(T* ptr) {\n cudaPointerAttributes attributes{};\n check_cuda_error(cudaPointerGetAttributes(&attributes, ptr));\n return attributes.type;\n}\n\n/// Get the memory info\n/// \\return The free and total amount of memory in bytes\ninline std::tuple<size_t, size_t> getDeviceMemoryInfo(bool const useUvm) {\n if (useUvm) {\n size_t freeSysMem = 0;\n size_t totalSysMem = 0;\n#ifndef _WIN32 // Linux\n struct sysinfo info{};\n\n sysinfo(&info);\n totalSysMem = info.totalram * info.mem_unit;\n freeSysMem = info.freeram * info.mem_unit;\n#else // Windows\n MEMORYSTATUSEX memInfo;\n memInfo.dwLength = sizeof(memInfo);\n GlobalMemoryStatusEx(&memInfo);\n totalSysMem = memInfo.ullTotalPhys;\n freeSysMem = memInfo.ullAvailPhys;\n#endif // WIN32\n\n TLLM_LOG_INFO(\n \"Using UVM based system memory for KV cache, total memory %0.2f GB, available memory %0.2f \"\n \"GB\",\n ((double)totalSysMem / 1e9), ((double)freeSysMem / 1e9));\n return {freeSysMem, totalSysMem};\n }\n\n size_t free = 0;\n size_t total = 0;\n check_cuda_error(cudaMemGetInfo(&free, &total));\n TLLM_LOG_DEBUG(\"Using GPU memory for KV cache, total memory %0.2f GB, available memory %0.2f GB\",\n ((double)total / 1e9), ((double)free / 1e9));\n return {free, total};\n}\n\n/// @brief Gets the memory allocation granularity for the current device.\n///\n/// @return size_t The size of the smallest difference in memory size supported by the current\n/// device.\ninline size_t getAllocationGranularity() {\n auto const currentDevice = getDevice();\n ::CUmemAllocationProp prop = {};\n\n prop.type = ::CU_MEM_ALLOCATION_TYPE_PINNED;\n prop.location.type = ::CU_MEM_LOCATION_TYPE_DEVICE;\n prop.location.id = currentDevice;\n prop.requestedHandleTypes = ::CU_MEM_HANDLE_TYPE_NONE;\n\n // Get the minimum granularity supported for allocation with cuMemCreate()\n size_t granularity = 0;\n TLLM_CU_CHECK(\n cuMemGetAllocationGranularity(&granularity, &prop, CU_MEM_ALLOC_GRANULARITY_MINIMUM));\n return granularity;\n}\n\ninline int getMultiProcessorCount() {\n int nSM{0};\n int deviceID{0};\n check_cuda_error(cudaGetDevice(&deviceID));\n check_cuda_error(cudaDeviceGetAttribute(&nSM, cudaDevAttrMultiProcessorCount, deviceID));\n return nSM;\n}\n\ninline int getMaxSharedMemoryPerSM() {\n int nByteMaxSharedMemoryPerSM{0};\n int deviceID{0};\n check_cuda_error(cudaGetDevice(&deviceID));\n check_cuda_error(cudaDeviceGetAttribute(&nByteMaxSharedMemoryPerSM,\n cudaDevAttrMaxSharedMemoryPerMultiprocessor, deviceID));\n return nByteMaxSharedMemoryPerSM;\n}\n\ninline int getMaxSharedMemoryPerBlockOptin() {\n int nByteMaxSharedMemoryPerBlockOptin{0};\n int deviceID{0};\n check_cuda_error(cudaGetDevice(&deviceID));\n check_cuda_error(cudaDeviceGetAttribute(&nByteMaxSharedMemoryPerBlockOptin,\n cudaDevAttrMaxSharedMemoryPerBlockOptin, deviceID));\n return nByteMaxSharedMemoryPerBlockOptin;\n}\n\ntemplate <typename T1, typename T2>\ninline size_t divUp(T1 const& a, T2 const& b) {\n auto const tmp_a = static_cast<size_t>(a);\n auto const tmp_b = static_cast<size_t>(b);\n return (tmp_a + tmp_b - 1) / tmp_b;\n}\n\ntemplate <typename T, typename U, typename = std::enable_if_t<std::is_integral<T>::value>,\n typename = std::enable_if_t<std::is_integral<U>::value>>\nauto constexpr ceilDiv(T numerator, U denominator) {\n return (numerator + denominator - 1) / denominator;\n}\n\ntemplate <typename T, typename U, typename = std::enable_if_t<std::is_integral<T>::value>,\n typename = std::enable_if_t<std::is_integral<U>::value>>\nauto constexpr roundUp(T numerator, U denominator) {\n return ceilDiv(numerator, denominator) * denominator;\n}\n\ntemplate <typename T>\nvoid printArrayInfo(T const* ptr, uint64_t nElement = 1, std::string name = \"\",\n bool const bPrintElement = false) {\n if (ptr == nullptr) {\n TLLM_LOG_WARNING(\"%s is an nullptr, skip!\", name.c_str());\n return;\n }\n cudaDeviceSynchronize();\n check_cuda_error(cudaGetLastError());\n\n bool const isDevicePtr = (getPtrCudaMemoryType(ptr) == cudaMemoryTypeDevice);\n size_t sizeInByte = sizeof(T) * nElement;\n TLLM_LOG_TRACE(\"addr=%p, location=%s, sizeof(T)=%lu, nElement=%d, sizeInByte=%lu\\n\", ptr,\n (isDevicePtr ? \"Device\" : \"Host\"), sizeof(T), nElement, sizeInByte);\n T* tmp = const_cast<T*>(ptr);\n std::vector<T> tmpVec; // For device pointer\n if (isDevicePtr) {\n tmpVec.resize(nElement);\n tmp = tmpVec.data();\n check_cuda_error(cudaMemcpy(tmp, ptr, sizeInByte, cudaMemcpyDeviceToHost));\n cudaDeviceSynchronize();\n }\n\n size_t nInf = 0;\n size_t nNaN = 0;\n size_t nZero = 0;\n double sum = 0.0;\n double sqrSum = 0.0;\n double absSum = 0.0;\n float allMax = -1.0e6f;\n float allMin = 1.0e6f;\n float allSad = 0.0f; // Sum Abs of Difference, to distinguish A and its transpose\n float old = 0.0f;\n for (uint64_t i = 0; i < nElement; i++) {\n float val = (float)tmp[i];\n\n if (std::isinf(val)) {\n nInf++;\n continue;\n }\n if (std::isnan(val)) {\n nNaN++;\n continue;\n }\n nZero += (val == 0.0f);\n sum += val;\n sqrSum += val * val;\n absSum += expf(val);\n allMax = std::max(allMax, val);\n allMin = std::min(allMin, val);\n allSad += abs(val - old);\n old = val;\n }\n float avg = sum / nElement;\n float std = sqrtf(sqrSum / nElement - avg * avg);\n\n TLLM_LOG_INFO(\"%s\", name.c_str());\n TLLM_LOG_INFO(\"size=%u, nInf=%zu, nNaN=%zu, nZero=%zu\", nElement, nInf, nNaN, nZero);\n TLLM_LOG_INFO(\"avg=%f, absSum: %f, std=%f, max=%f, min=%f, sad=%f\", avg, absSum, std, allMax,\n allMin, allSad);\n\n if (bPrintElement) {\n uint64_t constexpr nHead = 5;\n std::stringstream ss;\n ss << std::setw(10) << std::fixed << std::setprecision(3);\n for (uint64_t i = 0; i < std::min(nElement, nHead); ++i) {\n ss << (float)tmp[i] << \", \";\n }\n if (nElement > nHead) {\n ss << \" ... \";\n for (uint64_t i = nElement - nHead; i < nElement; ++i) {\n ss << (float)tmp[i] << \", \";\n }\n }\n TLLM_LOG_INFO(\"%s\", ss.str().c_str());\n }\n cudaDeviceSynchronize();\n check_cuda_error(cudaGetLastError());\n}\n\ntemplate void printArrayInfo(float const* ptr, uint64_t nElement, std::string name,\n bool const bPrintElement);\ntemplate void printArrayInfo(half const* ptr, uint64_t nElement, std::string name,\n bool const bPrintElement);\n#ifdef ENABLE_BF16\ntemplate void printArrayInfo(__nv_bfloat16 const* ptr, uint64_t nElement, std::string name,\n bool const bPrintElement);\n#endif\n#ifdef ENABLE_FP8\ntemplate void printArrayInfo(__nv_fp8_e4m3 const* ptr, uint64_t nElement, std::string name,\n bool const bPrintElement);\n#endif\ntemplate void printArrayInfo(uint32_t const* ptr, uint64_t nElement, std::string name,\n bool const bPrintElement);\ntemplate void printArrayInfo(uint64_t const* ptr, uint64_t nElement, std::string name,\n bool const bPrintElement);\ntemplate void printArrayInfo(int const* ptr, uint64_t nElement, std::string name,\n bool const bPrintElement);\ntemplate void printArrayInfo(uint8_t const* ptr, uint64_t nElement, std::string name,\n bool const bPrintElement);\n\ntemplate <typename T>\nvoid printToStream(T const* ptr, int const nElement, FILE* strm) {\n bool const split_rows = (strm == stdout);\n if (ptr == nullptr) {\n TLLM_LOG_WARNING(\"Nullptr, skip!\\n\");\n return;\n }\n std::vector<T> tmp(nElement, 0);\n check_cuda_error(cudaMemcpy(tmp.data(), ptr, sizeof(T) * nElement, cudaMemcpyDeviceToHost));\n for (int i = 0; i < nElement; ++i) {\n fprintf(strm, \"%f, \", static_cast<float>(tmp[i]));\n if (split_rows && ((i + 1) % 10) == 0) fprintf(strm, \"\\n\");\n }\n if (!split_rows || (nElement % 10) != 0) {\n fprintf(strm, \"\\n\");\n }\n}\n\ntemplate <typename T>\nvoid printToScreen(T const* ptr, int const nElement) {\n printToStream(ptr, nElement, stdout);\n}\n\ntemplate <typename T>\nvoid print2dToStream(T const* ptr, int const nRow, int const nCol, int const nStride, FILE* strm) {\n if (ptr == nullptr) {\n TLLM_LOG_WARNING(\"Nullptr, skip!\\n\");\n return;\n }\n for (int ri = 0; ri < nRow; ++ri) {\n T const* tmp = ptr + ri * nStride;\n printToStream(tmp, nCol, strm);\n }\n fprintf(strm, \"\\n\");\n}\n\ntemplate <typename T>\nvoid print2dToScreen(T const* ptr, int const nRow, int const nCol, int const nStride) {\n print2dToStream(ptr, nRow, nCol, nStride, stdout);\n}\n\ntemplate <typename T>\nvoid print2dToFile(std::string fname, T const* ptr, int const nRow, int const nCol,\n int const nStride) {\n FILE* fp = fopen(fname.c_str(), \"wt\");\n if (fp != nullptr) {\n print2dToStream(ptr, nRow, nCol, nStride, fp);\n fclose(fp);\n }\n}\n\n__host__ __device__ inline void print_float_(float x) { printf(\"%7.3f \", x); }\n\n__host__ __device__ inline void print_element_(float x) { print_float_(x); }\n\n__host__ __device__ inline void print_element_(half x) { print_float_((float)x); }\n\n#ifdef ENABLE_BF16\n__host__ __device__ inline void print_element_(__nv_bfloat16 x) { print_float_((float)x); }\n#endif\n\n#ifdef ENABLE_FP8\n__host__ __device__ inline void print_element_(__nv_fp8_e4m3 x) { print_float_((float)x); }\n#endif\n\n__host__ __device__ inline void print_element_(uint8_t ui) {\n printf(\"%7\" PRIu32 \" \", (unsigned int)ui);\n}\n\n__host__ __device__ inline void print_element_(uint32_t ul) { printf(\"%7\" PRIu32 \" \", ul); }\n\n__host__ __device__ inline void print_element_(uint64_t ull) { printf(\"%7\" PRIu64 \" \", ull); }\n\n__host__ __device__ inline void print_element_(int32_t il) { printf(\"%7\" PRId32 \" \", il); }\n\n__host__ __device__ inline void print_element_(int64_t ill) { printf(\"%7\" PRId64 \" \", ill); }\n\ntemplate <typename T>\n__host__ __device__ inline void print_elements(T const* ptr, int nRow, int nCol, int nStride) {\n for (int iRow = -1; iRow < nRow; ++iRow) {\n if (iRow >= 0) {\n printf(\"%07d|\", iRow);\n } else {\n printf(\" |\"); // heading row\n }\n for (int iCol = 0; iCol < nCol; iCol += 1) {\n if (iRow >= 0) {\n print_element_(ptr[iRow * nStride + iCol]);\n } else {\n printf(\"%7d|\", iCol); // heading colume\n }\n }\n printf(\"\\n\");\n }\n printf(\"\\n\");\n}\n\ntemplate <typename T>\ninline void printMatrix(T const* ptr, int nRow, int nCol, int nStride) {\n // `nRow` is length of row dimension\n // `nStride` is length of column dimension\n // `nCol` (<= nStride) is length for print per row\n if (ptr == nullptr) {\n TLLM_LOG_WARNING(\"Nullptr, skip!\\n\");\n return;\n }\n cudaDeviceSynchronize();\n check_cuda_error(cudaGetLastError());\n\n bool const isDevicePtr = (getPtrCudaMemoryType(ptr) == cudaMemoryTypeDevice);\n size_t sizeInByte = sizeof(T) * nRow * nStride;\n TLLM_LOG_TRACE(\"addr=%p, location=%s, sizeof(T)=%lu, nRow=%d, nStride=%d, sizeInByte=%lu\\n\", ptr,\n (isDevicePtr ? \"Device\" : \"Host\"), sizeof(T), nRow, nStride, sizeInByte);\n if (isDevicePtr) {\n std::vector<T> tmpVec;\n tmpVec.resize(nRow * nStride);\n T* tmp = tmpVec.data();\n check_cuda_error(cudaMemcpy(tmp, ptr, sizeInByte, cudaMemcpyDeviceToHost));\n cudaDeviceSynchronize();\n check_cuda_error(cudaGetLastError());\n print_elements(tmp, nRow, nCol, nStride);\n } else {\n print_elements(ptr, nRow, nCol, nStride);\n }\n}\n\ntemplate void printMatrix(float const* ptr, int nRow, int nCol, int nStride);\ntemplate void printMatrix(half const* ptr, int nRow, int nCol, int nStride);\n#ifdef ENABLE_BF16\ntemplate void printMatrix(__nv_bfloat16 const* ptr, int nRow, int nCol, int nStride);\n#endif\n#ifdef ENABLE_FP8\ntemplate void printMatrix(__nv_fp8_e4m3 const* ptr, int nRow, int nCol, int nStride);\n#endif\ntemplate void printMatrix(uint32_t const* ptr, int nRow, int nCol, int nStride);\ntemplate void printMatrix(uint64_t const* ptr, int nRow, int nCol, int nStride);\ntemplate void printMatrix(int const* ptr, int nRow, int nCol, int nStride);\ntemplate void printMatrix(uint8_t const* ptr, int nRow, int nCol, int nStride);\n\ntemplate <typename T>\n__device__ inline void printMatrixDevice(T const* ptr, int nRow, int nCol, int nStride) {\n // `nRow` is length of row dimension\n // `nStride` is length of column dimension\n // `nCol` (<= nStride) is length for print per row\n // Can be called inside kernels by one single thread\n if (ptr == nullptr) {\n printf(\"Nullptr, skip!\\n\");\n return;\n }\n size_t sizeInByte = sizeof(T) * nRow * nStride;\n printf(\"addr=%p, sizeof(T)=%lu, nRow=%d, nStride=%d, sizeInByte=%lu\\n\", ptr, sizeof(T), nRow,\n nStride, sizeInByte);\n print_elements(ptr, nRow, nCol, nStride);\n}\n\ntemplate __device__ void printMatrixDevice(float const* ptr, int nRow, int nCol, int nStride);\ntemplate __device__ void printMatrixDevice(half const* ptr, int nRow, int nCol, int nStride);\n#ifdef ENABLE_BF16\ntemplate __device__ void printMatrixDevice(__nv_bfloat16 const* ptr, int nRow, int nCol,\n int nStride);\n#endif\n#ifdef ENABLE_FP8\ntemplate __device__ void printMatrixDevice(__nv_fp8_e4m3 const* ptr, int nRow, int nCol,\n int nStride);\n#endif\ntemplate __device__ void printMatrixDevice(uint32_t const* ptr, int nRow, int nCol, int nStride);\ntemplate __device__ void printMatrixDevice(uint64_t const* ptr, int nRow, int nCol, int nStride);\ntemplate __device__ void printMatrixDevice(int const* ptr, int nRow, int nCol, int nStride);\ntemplate __device__ void printMatrixDevice(uint8_t const* ptr, int nRow, int nCol, int nStride);\n\n#ifndef CUDA_CALL\n#define CUDA_CALL(answer) \\\n { \\\n gpuAssert((answer), __FILE__, __LINE__); \\\n }\n\ninline void gpuAssert(cudaError_t code, char const* file, int line, bool abort = true) {\n if (code != cudaSuccess) {\n fprintf(stderr, \"CUDA error: %s @ %s:%d\\n\", cudaGetErrorString(code), file, line);\n if (abort) exit(code);\n }\n}\n\ninline void gpuAssert(CUresult code, char const* file, int line, bool abort = true) {\n if (code != CUresult::CUDA_SUCCESS) {\n char const* buf = \"Unknown error\";\n assert(cuGetErrorString(code, &buf) == CUresult::CUDA_SUCCESS);\n fprintf(stderr, \"Driver API error: %s @ %s:%d\\n\", buf, file, line);\n if (abort) exit(code);\n }\n}\n#endif\n\ntemplate <typename T>\nstruct UpperType;\n\ntemplate <>\nstruct UpperType<int8_t> {\n using Type = int;\n};\n\ntemplate <>\nstruct UpperType<uint32_t> {\n using Type = uint32_t;\n};\n\ntemplate <>\nstruct UpperType<int> {\n using Type = int;\n};\n\ntemplate <>\nstruct UpperType<__nv_bfloat16> {\n using Type = double;\n};\n\ntemplate <>\nstruct UpperType<half> {\n using Type = double;\n};\n\ntemplate <>\nstruct UpperType<float> {\n using Type = double;\n};\n\nextern \"C\" {\n__device__ uint32_t __nvvm_get_smem_pointer(void* ptr);\n}\n\n__forceinline__ __device__ void issue_stas(uint32_t dist_barrier_ptr, uint32_t dist_buffer_ptr,\n uint32_t d0) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900) && (__CUDACC_VER_MAJOR__ >= 12))\n asm volatile(\"st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.b32 [%0], %2, [%1];\\n\\t\"\n :\n : \"r\"(dist_buffer_ptr), \"r\"(dist_barrier_ptr), \"r\"(d0));\n#endif\n}\n\n__forceinline__ __device__ void issue_stas(uint32_t dist_barrier_ptr, uint32_t dist_buffer_ptr,\n uint64_t d0) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900) && (__CUDACC_VER_MAJOR__ >= 12))\n asm volatile(\"st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.b64 [%0], %2, [%1];\\n\\t\"\n :\n : \"r\"(dist_buffer_ptr), \"r\"(dist_barrier_ptr), \"l\"(d0));\n#endif\n}\n\n__forceinline__ __device__ void issue_stas(uint32_t dist_barrier_ptr, uint32_t dist_buffer_ptr,\n uint32_t d0, uint32_t d1) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900) && (__CUDACC_VER_MAJOR__ >= 12))\n asm volatile(\n \"st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.v2.b32 [%0], {%2, %3}, [%1];\\n\\t\"\n :\n : \"r\"(dist_buffer_ptr), \"r\"(dist_barrier_ptr), \"r\"(d0), \"r\"(d1));\n#endif\n}\n\n__forceinline__ __device__ void issue_stas(uint32_t dist_barrier_ptr, uint32_t dist_buffer_ptr,\n uint32_t d0, uint32_t d1, uint32_t d2, uint32_t d3) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900) && (__CUDACC_VER_MAJOR__ >= 12))\n asm volatile(\n \"st.async.shared::cluster.mbarrier::complete_tx::bytes.v4.b32 [%0], {%2, %3, %4, %5}, \"\n \"[%1];\\n\\t\"\n :\n : \"r\"(dist_buffer_ptr), \"r\"(dist_barrier_ptr), \"r\"(d0), \"r\"(d1), \"r\"(d2), \"r\"(d3));\n#endif\n}\n\ninline __device__ uint32_t elect_one_sync() {\n uint32_t pred = 0;\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900) && (__CUDACC_VER_MAJOR__ >= 12))\n#if (defined(__CUDA_ARCH_FEAT_SM90_ALL))\n uint32_t laneid = 0;\n asm volatile(\n \"\\n\\\n {\\n\\\n .reg .b32 %rx;\\n\\\n .reg .pred %px;\\n\\\n elect.sync %rx|%px, %2;\\n\\\n @%px mov.s32 %1, 1;\\n\\\n mov.s32 %0, %rx;\\n\\\n }\\n\\\n \"\n : \"+r\"(laneid), \"+r\"(pred)\n : \"r\"(0xFFFFFFFF));\n#endif\n#endif\n return pred;\n}\n\n__forceinline__ __device__ uint32_t get_smem_pointer(void const* ptr) {\n return __nvvm_get_smem_pointer(const_cast<void*>(ptr));\n}\n\n__forceinline__ __device__ void bar_create(void* bar_ptr, int init_count) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n unsigned smem_ptr = get_smem_pointer(bar_ptr);\n\n asm volatile(\n \"{\\n\\t\"\n \"mbarrier.init.shared.b64 [%1], %0; \\n\\t\"\n \"}\"\n :\n : \"r\"(init_count), \"r\"(smem_ptr));\n#endif\n}\n\nstruct Arrive_wait {\n public:\n __forceinline__ __device__ Arrive_wait() { bar_base_ = NULL; }\n\n __forceinline__ __device__ Arrive_wait(uint64_t* bar_base, int id = 0) {\n bar_base_ = bar_base;\n id_ = id;\n }\n\n __forceinline__ __device__ int bar_peek(int id, unsigned int bar_phase) {\n uint32_t result32{};\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n auto* bar_ptr = bar_base_ + id;\n unsigned smem_ptr = get_smem_pointer(bar_ptr);\n asm volatile(\n \"{\\n\\t\"\n \".reg .pred P1; \\n\\t\"\n \"mbarrier.try_wait.parity.shared.b64 P1, [%1], %2; \\n\\t\"\n \"selp.b32 %0, 1, 0, P1; \\n\\t\"\n \"}\"\n : \"=r\"(result32)\n : \"r\"(smem_ptr), \"r\"(bar_phase));\n#endif\n return result32;\n }\n\n __forceinline__ __device__ int bar_peek(int id, unsigned int bar_phase, int pred) {\n uint32_t result32{};\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n auto* bar_ptr = bar_base_ + id;\n unsigned smem_ptr = get_smem_pointer(bar_ptr);\n asm volatile(\n \"{\\n\\t\"\n \".reg .pred P1; \\n\\t\"\n \".reg .pred P2;\\n\\t\"\n \"setp.eq.u32 P2, %3, 1;\\n\\t\"\n \"@P2 mbarrier.try_wait.parity.shared.b64 P1, [%1], %2; \\n\\t\"\n \"selp.b32 %0, 1, 0, P1; \\n\\t\"\n \"}\"\n : \"=r\"(result32)\n : \"r\"(smem_ptr), \"r\"(bar_phase), \"r\"(pred));\n#endif\n return result32;\n }\n\n __forceinline__ __device__ void bar_wait(int id, unsigned int bar_phase) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n auto* bar_ptr = bar_base_ + id;\n unsigned smem_ptr = get_smem_pointer(bar_ptr);\n asm volatile(\n \"{\\n\\t\"\n \".reg .pred P1; \\n\\t\"\n \"LAB_WAIT: \\n\\t\"\n \"mbarrier.try_wait.parity.acquire.cta.shared::cta.b64 P1, [%0], %1; \\n\\t\"\n \"@P1 bra.uni DONE; \\n\\t\"\n \"bra.uni LAB_WAIT; \\n\\t\"\n \"DONE: \\n\\t\"\n \"}\"\n :\n : \"r\"(smem_ptr), \"r\"(bar_phase));\n#endif\n }\n\n __forceinline__ __device__ void bar_arrive_dsmem(int const& id) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n auto* bar_ptr = bar_base_ + id;\n asm volatile(\n \"{\\n\\t\"\n \"mbarrier.arrive.b64 _, [%0];\\n\\t\"\n \"}\"\n :\n : \"l\"(bar_ptr));\n#endif\n }\n\n __forceinline__ __device__ void bar_arrive_dsmem(int const& id, uint32_t const& pred) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n asm volatile(\n \"{\\n\\t\"\n \" .reg .pred p;\\n\\t\"\n \" .reg .s64 addr;\\n\\t\"\n \" .reg .b64 tmp;\\n\\t\"\n \" setp.eq.u32 p, %2, 1;\\n\\t\"\n \" mul.wide.s32 tmp, %0, 8;\\n\\t\"\n \" add.s64 addr, tmp, %1;\\n\\t\"\n \"@p mbarrier.arrive.b64 _, [addr];\\n\\t\"\n \"}\"\n :\n : \"r\"(id), \"l\"(bar_base_), \"r\"(pred));\n#endif\n }\n\n // Sets up the base address for arrival with the correct ctaid in cga\n __forceinline__ __device__ void set_bar_base_dsmem(uint32_t const& cta_id) {\n bar_base_ = reinterpret_cast<uint64_t*>(\n (reinterpret_cast<uintptr_t>(bar_base_) & 0xFFFFFFFFF0FFFFFFULL) + (cta_id << 24));\n }\n\n __forceinline__ __device__ void bar_arrive_normal(int id, bool flag = true) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n if (flag == true) {\n uint64_t* bar_ptr = reinterpret_cast<uint64_t*>(bar_base_ + id);\n unsigned smem_ptr = get_smem_pointer(bar_ptr);\n asm volatile(\n \"{\\n\\t\"\n \".reg .b64 state; \\n\\t\"\n \"mbarrier.arrive.shared.b64 state, [%0];\\n\\t\"\n \"}\"\n :\n : \"r\"(smem_ptr));\n }\n#endif\n }\n\n __forceinline__ __device__ void bar_arrive_set_transactioncnt(int id, int expected_copy_bytes) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n auto* bar_ptr = bar_base_ + id;\n unsigned smem_ptr = get_smem_pointer(bar_ptr);\n asm volatile(\n \"{\\n\\t\"\n \"mbarrier.arrive.expect_tx.shared.b64 _, [%0], %1; \\n\\t\"\n \"}\"\n :\n : \"r\"(smem_ptr), \"r\"(expected_copy_bytes));\n#endif\n }\n\n __forceinline__ __device__ void bar_arrive_set_transactioncnt(int id, int expected_copy_bytes,\n uint32_t pred) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n auto* bar_ptr = bar_base_ + id;\n unsigned smem_ptr = get_smem_pointer(bar_ptr);\n asm volatile(\n \"{\\n\\t\"\n \".reg .pred p;\\n\\t\"\n \"setp.eq.u32 p, %2, 1;\\n\\t\"\n \"@p mbarrier.arrive.expect_tx.shared.b64 _, [%0], %1; \\n\\t\"\n \"}\"\n :\n : \"r\"(smem_ptr), \"r\"(expected_copy_bytes), \"r\"(pred));\n#endif\n }\n\n __forceinline__ __device__ uint64_t* bar_base() { return bar_base_; }\n\n __forceinline__ __device__ uint64_t* get_bar_addr(int id) { return bar_base_ + id; }\n\n private:\n // smem barrier base pointer\n uint64_t* bar_base_;\n // barrier id\n int id_;\n};\n\n__forceinline__ __device__ void cga_sync() {\n#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 900\n asm volatile(\"barrier.cluster.sync;\\n\" : :);\n#endif\n}\n\n__forceinline__ __device__ void cga_arrive() {\n#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 900\n asm volatile(\"barrier.cluster.arrive.aligned;\\n\" : :);\n#endif\n}\n\n__forceinline__ __device__ void cga_wait() {\n#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 900\n asm volatile(\"barrier.cluster.wait.aligned;\\n\" : :);\n#endif\n}\n\ninline __device__ void fence_view_async_shared() {\n // only compiles on sm90+\n\n#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 900\n asm volatile(\"fence.proxy.async.shared::cta;\\n\" : :);\n#endif\n}\n\ntemplate <typename T>\n__forceinline__ __device__ T* get_DSMEM_ptr(T* localAddress, uint32_t destCtaId) {\n T* dsmemAddress = reinterpret_cast<T*>(\n ((unsigned long long int)localAddress & 0xFFFFFFFFF0FFFFFFULL) + (destCtaId << 24));\n return dsmemAddress;\n}\n\ntemplate <typename T>\n__forceinline__ __device__ void write_DSMEM_Address(T* localAddress, uint32_t destCtaId, T val) {\n T* dsmemAddress = get_DSMEM_ptr(localAddress, destCtaId);\n *dsmemAddress = val;\n}\n\n__forceinline__ __device__ void arrive_barrier(uint64_t* p_barrier, uint32_t arrive_cnt = 1) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n asm volatile(\"{mbarrier.arrive.shared.b64 _, [%0],%1;\\n\\t}\"\n :\n : \"l\"(p_barrier), \"r\"(arrive_cnt));\n#endif\n}\n\n__forceinline__ __device__ void arrive_DSMEM_barrier(uint64_t* p_barrier, uint32_t ctaid) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n uint64_t* p_barrier_remote = get_DSMEM_ptr(p_barrier, ctaid);\n asm volatile(\"{mbarrier.arrive.b64 _, [%0];\\n\\t}\" : : \"l\"(p_barrier_remote));\n#endif\n}\n\n__forceinline__ __device__ void arrive_DSMEM_barrier_and_set_tx_cnt(uint64_t* p_barrier,\n uint32_t ctaid,\n uint32_t expected_copy_bytes) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n uint32_t p_bar =\n static_cast<uint32_t>(reinterpret_cast<uintptr_t>(get_DSMEM_ptr(p_barrier, ctaid)));\n asm volatile(\"{mbarrier.arrive.expect_tx.b64 _, [%0], %1; \\n\\t}\" ::\"r\"(p_bar),\n \"r\"(expected_copy_bytes));\n#endif\n}\n\ntemplate <bool barSetTxCnt = true>\n__forceinline__ __device__ void stas(uint32_t* p_data, uint64_t* p_barrier, uint32_t ctaid,\n uint32_t const& wrdat) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n if (barSetTxCnt) arrive_DSMEM_barrier_and_set_tx_cnt(p_barrier, ctaid, sizeof(uint32_t));\n uint32_t buffer_ptr = static_cast<uint32_t>(reinterpret_cast<uintptr_t>(p_data));\n uint32_t barrier_ptr = static_cast<uint32_t>(reinterpret_cast<uintptr_t>(p_barrier));\n\n uint32_t buffer_ptr_, barrier_ptr_;\n asm volatile(\n \"{\\n\\t\"\n \"setctarank.shared.u32 %0, %2, %4;\\n\\t\"\n \"setctarank.shared.u32 %1, %3, %4;\\n\\t\"\n \"}\"\n : \"=r\"(buffer_ptr_), \"=r\"(barrier_ptr_)\n : \"r\"(buffer_ptr), \"r\"(barrier_ptr), \"r\"(ctaid));\n issue_stas(buffer_ptr_, barrier_ptr_, wrdat);\n#endif\n}\n\ntemplate <bool barSetTxCnt = true>\n__forceinline__ __device__ void stas(uint64_t* p_data, uint64_t* p_barrier, uint32_t ctaid,\n uint64_t const& wrdat) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n if (barSetTxCnt) arrive_DSMEM_barrier_and_set_tx_cnt(p_barrier, ctaid, sizeof(uint64_t));\n uint32_t buffer_ptr = static_cast<uint32_t>(reinterpret_cast<uintptr_t>(p_data));\n uint32_t barrier_ptr = static_cast<uint32_t>(reinterpret_cast<uintptr_t>(p_barrier));\n\n uint32_t buffer_ptr_, barrier_ptr_;\n asm volatile(\n \"{\\n\\t\"\n \"setctarank.shared.u32 %0, %2, %4;\\n\\t\"\n \"setctarank.shared.u32 %1, %3, %4;\\n\\t\"\n \"}\"\n : \"=r\"(buffer_ptr_), \"=r\"(barrier_ptr_)\n : \"r\"(buffer_ptr), \"r\"(barrier_ptr), \"r\"(ctaid));\n issue_stas(buffer_ptr_, barrier_ptr_, wrdat);\n#endif\n}\n\ntemplate <bool barSetTxCnt = true>\n__forceinline__ __device__ void stas(uint64_t* p_data, uint64_t* p_barrier, uint32_t ctaid,\n uint32_t const wrdat0, uint32_t const wrdat1,\n uint32_t const wrdat2, uint32_t const wrdat3) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n if (barSetTxCnt) arrive_DSMEM_barrier_and_set_tx_cnt(p_barrier, ctaid, 4 * sizeof(uint32_t));\n uint32_t buffer_ptr = static_cast<uint32_t>(reinterpret_cast<uintptr_t>(p_data));\n uint32_t barrier_ptr = static_cast<uint32_t>(reinterpret_cast<uintptr_t>(p_barrier));\n\n uint32_t buffer_ptr_, barrier_ptr_;\n asm volatile(\n \"{\\n\\t\"\n \"setctarank.shared.u32 %0, %2, %4;\\n\\t\"\n \"setctarank.shared.u32 %1, %3, %4;\\n\\t\"\n \"}\"\n : \"=r\"(buffer_ptr_), \"=r\"(barrier_ptr_)\n : \"r\"(buffer_ptr), \"r\"(barrier_ptr), \"r\"(ctaid));\n issue_stas(buffer_ptr_, barrier_ptr_, wrdat0, wrdat1, wrdat2, wrdat3);\n#endif\n}\n\ntemplate <bool barSetTxCnt = true, bool assumeAligned = true, typename T = void>\n__forceinline__ __device__ void stas(T* p_data, uint64_t* p_barrier, uint32_t ctaid,\n T const& wrdat) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n static_assert(sizeof(T) % 4 == 0);\n if (barSetTxCnt) arrive_DSMEM_barrier_and_set_tx_cnt(p_barrier, ctaid, sizeof(T));\n\n uint32_t buffer_ptr = static_cast<uint32_t>(reinterpret_cast<uintptr_t>(p_data));\n uint32_t barrier_ptr = static_cast<uint32_t>(reinterpret_cast<uintptr_t>(p_barrier));\n\n uint32_t buffer_ptr_, barrier_ptr_;\n asm volatile(\n \"{\\n\\t\"\n \"setctarank.shared.u32 %0, %2, %4;\\n\\t\"\n \"setctarank.shared.u32 %1, %3, %4;\\n\\t\"\n \"}\"\n : \"=r\"(buffer_ptr_), \"=r\"(barrier_ptr_)\n : \"r\"(buffer_ptr), \"r\"(barrier_ptr), \"r\"(ctaid));\n\n uint32_t const* p_wrdat_b32 = reinterpret_cast<uint32_t const*>(&wrdat);\n\n for (uint32_t offset = 0; offset < sizeof(T);) {\n if constexpr (assumeAligned) {\n if (offset + 16 <= sizeof(T)) {\n // Use write_async_v4_b32\n issue_stas(buffer_ptr_ + offset, barrier_ptr_, p_wrdat_b32[offset / 4],\n p_wrdat_b32[offset / 4 + 1], p_wrdat_b32[offset / 4 + 2],\n p_wrdat_b32[offset / 4 + 3]);\n offset += 16;\n } else if (offset + 8 <= sizeof(T) && (buffer_ptr + offset) % 8 == 0) {\n // Use write_async_v2_b32\n issue_stas(buffer_ptr + offset, barrier_ptr_, p_wrdat_b32[offset / 4],\n p_wrdat_b32[offset / 4 + 1]);\n offset += 8;\n } else {\n issue_stas(buffer_ptr + offset, barrier_ptr_, p_wrdat_b32[offset / 4]);\n offset += 4;\n }\n } else {\n issue_stas(buffer_ptr + offset, barrier_ptr_, p_wrdat_b32[offset / 4]);\n offset += 4;\n }\n }\n#endif\n}\n\nstruct OrderedMutex {\n uint64_t barriers[2];\n\n __device__ void init(int tid0, int threads0, int threads1) {\n if (tid0) {\n bar_create(&barriers[0], threads0);\n bar_create(&barriers[1], threads1);\n }\n }\n\n OrderedMutex() = default;\n OrderedMutex(OrderedMutex const& other) = delete;\n};\n\nclass OrderedMutexAccessor {\n public:\n struct State {\n int phase = 0;\n };\n\n private:\n int _phase;\n int _id;\n Arrive_wait _barriers;\n\n public:\n __device__ OrderedMutexAccessor(OrderedMutex& m, int id, State state)\n : _phase(state.phase), _id(id), _barriers(m.barriers) {}\n\n __device__ void arrive() { _barriers.bar_arrive_normal(_id); }\n\n __device__ void wait() {\n _barriers.bar_wait(_id ^ 1, _phase);\n _phase ^= 1;\n }\n\n __device__ State exportState() { return {.phase = _phase}; }\n};\n\ntemplate <typename T, T VALUE>\nstruct ConstExprWrapper {\n static constexpr T value = VALUE;\n};\n\ntemplate <int VALUE>\nusing Int = ConstExprWrapper<int, VALUE>;\n\ntemplate <bool VALUE>\nusing Bool = ConstExprWrapper<bool, VALUE>;\n\ntemplate <bool VALUE>\nusing ConstBool = ConstExprWrapper<bool, VALUE>;\n\ntemplate <typename T>\nstruct TmaDescType;\n\ntemplate <>\nstruct TmaDescType<__nv_bfloat16> {\n static constexpr auto value = CUtensorMapDataType_enum::CU_TENSOR_MAP_DATA_TYPE_BFLOAT16;\n};\n\ntemplate <>\nstruct TmaDescType<float> {\n static constexpr auto value = CUtensorMapDataType_enum::CU_TENSOR_MAP_DATA_TYPE_FLOAT32;\n};\n\n#define DEFINE_MEMBER_CHECKER(member) \\\n template <typename T, typename V = bool> \\\n struct has_##member : std::false_type {}; \\\n template <typename T> \\\n struct has_##member< \\\n T, typename std::enable_if<!std::is_same<decltype(std::declval<T>().member), void>::value, \\\n bool>::type> : std::true_type {};\n\n#define HAS_MEMBER(C, member) has_##member<C>::value\n\nDEFINE_MEMBER_CHECKER(output)\nDEFINE_MEMBER_CHECKER(residual)\nDEFINE_MEMBER_CHECKER(bias)\nDEFINE_MEMBER_CHECKER(deq)\nDEFINE_MEMBER_CHECKER(qua)\nDEFINE_MEMBER_CHECKER(high_preciecion_normed_output)\n\n} // namespace tensorrt_llm::common\n\n/*\n * Macros compliant with TensorRT coding conventions\n */\n#define TLLM_CUDA_CHECK(stat) \\\n do { \\\n tensorrt_llm::common::check((stat), #stat, __FILE__, __LINE__); \\\n } while (0)\n\n// We use singleton memory pool and the order of destructors depends on the compiler implementation.\n// We find that the cudaFree/cudaFreeHost is called after cudaruntime destruction on Windows. There\n// will be an cudaErrorCudartUnloading error. However, it is safe to ignore this error because the\n// cuda runtime is already exited, we are no more worried about the memory leaks.\n#define TLLM_CUDA_CHECK_FREE_RESOURCE(stat) \\\n do { \\\n tensorrt_llm::common::checkEx((stat), {cudaSuccess, cudaErrorCudartUnloading}, #stat, \\\n __FILE__, __LINE__); \\\n } while (0)\n"},"diff":{"kind":"string","value":"--- csrc/nv_internal/include/tensorrt_llm/common/cudaUtils.h\n+++ csrc/nv_internal/include/tensorrt_llm/common/cudaUtils.h\n@@ -388,12 +388,16 @@\n return (tmp_a + tmp_b - 1) / tmp_b;\n }\n \n-inline int roundUp(int a, int b) { return divUp(a, b) * b; }\n-\n template <typename T, typename U, typename = std::enable_if_t<std::is_integral<T>::value>,\n typename = std::enable_if_t<std::is_integral<U>::value>>\n auto constexpr ceilDiv(T numerator, U denominator) {\n return (numerator + denominator - 1) / denominator;\n+}\n+\n+template <typename T, typename U, typename = std::enable_if_t<std::is_integral<T>::value>,\n+ typename = std::enable_if_t<std::is_integral<U>::value>>\n+auto constexpr roundUp(T numerator, U denominator) {\n+ return ceilDiv(numerator, denominator) * denominator;\n }\n \n template <typename T>"},"lines_added":{"kind":"number","value":6,"string":"6"},"lines_removed":{"kind":"number","value":2,"string":"2"},"files_in_commit":{"kind":"number","value":3,"string":"3"},"models_mentioned":{"kind":"list like","value":["deepseek","qwen","mixtral"],"string":"[\n \"deepseek\",\n \"qwen\",\n \"mixtral\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["HOPPER","SM100"],"string":"[\n \"HOPPER\",\n \"SM100\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":["4×","4×","1×","1×","4×","1×","8×","2×","1.08x","1.00x"],"string":"[\n \"4×\",\n \"4×\",\n \"1×\",\n \"1×\",\n \"4×\",\n \"1×\",\n \"8×\",\n \"2×\",\n \"1.08x\",\n \"1.00x\"\n]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cpp kernel file from flashinfer (csrc/nv_internal/include/tensorrt_llm/common/cudaUtils.h).\n\nGoal: perf(moe): optimize CUTLASS fused MoE mem-bound kernels\nTarget hardware: HOPPER, SM100\nTarget models: deepseek, qwen, mixtral\n\nCurrent file:\n```cpp\n/*\n * SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights\n * reserved. SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#pragma once\n\n#include <cublasLt.h>\n#include <cublas_v2.h>\n#include <cuda.h>\n#include <cuda_runtime.h>\n#include <driver_types.h>\n\n#include <algorithm>\n#include <cassert>\n#include <cinttypes>\n#include <fstream>\n#include <iomanip>\n#include <memory>\n#include <optional>\n#include <sstream>\n#include <string>\n\n#include \"tensorrt_llm/common/cudaBf16Wrapper.h\"\n#include \"tensorrt_llm/common/cudaDriverWrapper.h\"\n#include \"tensorrt_llm/common/cudaFp8Utils.h\"\n#include \"tensorrt_llm/common/logger.h\"\n#include \"tensorrt_llm/common/tllmException.h\"\n#ifndef _WIN32 // Linux\n#include <sys/sysinfo.h>\n#endif // not WIN32\n#include <vector>\n#ifdef _WIN32 // Windows\n#include <windows.h>\n#undef ERROR // A Windows header file defines ERROR as 0, but it's used in our logger.h enum.\n // Logging breaks without this undef.\n#endif // WIN32\n\nnamespace tensorrt_llm::common {\n\n// workspace for cublas gemm : 32MB\n#define CUBLAS_WORKSPACE_SIZE 33554432\n\ntypedef struct __align__(4) {\n half x, y, z, w;\n}\n\nhalf4;\n\n/* **************************** type definition ***************************** */\n\nenum CublasDataType {\n FLOAT_DATATYPE = 0,\n HALF_DATATYPE = 1,\n BFLOAT16_DATATYPE = 2,\n INT8_DATATYPE = 3,\n FP8_DATATYPE = 4\n};\n\nenum TRTLLMCudaDataType { FP32 = 0, FP16 = 1, BF16 = 2, INT8 = 3, FP8 = 4 };\n\nenum class OperationType { FP32, FP16, BF16, INT8, FP8 };\n\n/* **************************** debug tools ********************************* */\nstatic char const* _cudaGetErrorEnum(cudaError_t error) { return cudaGetErrorString(error); }\n\nstatic char const* _cudaGetErrorEnum(cublasStatus_t error) {\n switch (error) {\n case CUBLAS_STATUS_SUCCESS:\n return \"CUBLAS_STATUS_SUCCESS\";\n\n case CUBLAS_STATUS_NOT_INITIALIZED:\n return \"CUBLAS_STATUS_NOT_INITIALIZED\";\n\n case CUBLAS_STATUS_ALLOC_FAILED:\n return \"CUBLAS_STATUS_ALLOC_FAILED\";\n\n case CUBLAS_STATUS_INVALID_VALUE:\n return \"CUBLAS_STATUS_INVALID_VALUE\";\n\n case CUBLAS_STATUS_ARCH_MISMATCH:\n return \"CUBLAS_STATUS_ARCH_MISMATCH\";\n\n case CUBLAS_STATUS_MAPPING_ERROR:\n return \"CUBLAS_STATUS_MAPPING_ERROR\";\n\n case CUBLAS_STATUS_EXECUTION_FAILED:\n return \"CUBLAS_STATUS_EXECUTION_FAILED\";\n\n case CUBLAS_STATUS_INTERNAL_ERROR:\n return \"CUBLAS_STATUS_INTERNAL_ERROR\";\n\n case CUBLAS_STATUS_NOT_SUPPORTED:\n return \"CUBLAS_STATUS_NOT_SUPPORTED\";\n\n case CUBLAS_STATUS_LICENSE_ERROR:\n return \"CUBLAS_STATUS_LICENSE_ERROR\";\n }\n return \"<unknown>\";\n}\n\ntemplate <typename T>\nvoid check(T ptr, char const* const func, char const* const file, int const line) {\n if (ptr) {\n throw TllmException(\n file, line,\n fmtstr(\"[TensorRT-LLM][ERROR] CUDA runtime error in %s: %s\", func, _cudaGetErrorEnum(ptr))\n .c_str());\n }\n}\n\ntemplate <typename T>\nvoid checkEx(T ptr, std::initializer_list<T> const& validReturns, char const* const func,\n char const* const file, int const line) {\n if (std::all_of(std::begin(validReturns), std::end(validReturns),\n [&ptr](T const& t) { return t != ptr; })) {\n throw TllmException(\n file, line,\n fmtstr(\"[TensorRT-LLM][ERROR] CUDA runtime error in %s: %s\", func, _cudaGetErrorEnum(ptr))\n .c_str());\n }\n}\n\n#define check_cuda_error(val) check((val), #val, __FILE__, __LINE__)\n#define check_cuda_error_2(val, file, line) check((val), #val, file, line)\n\ninline std::optional<bool> isCudaLaunchBlocking() {\n thread_local bool firstCall = true;\n thread_local std::optional<bool> result = std::nullopt;\n if (!firstCall) {\n char const* env = std::getenv(\"CUDA_LAUNCH_BLOCKING\");\n if (env != nullptr && std::string(env) == \"1\") {\n result = true;\n } else {\n result = false;\n }\n firstCall = false;\n }\n return result;\n}\n\ninline bool isCapturing(cudaStream_t stream) {\n cudaStreamCaptureStatus status;\n check_cuda_error(cudaStreamIsCapturing(stream, &status));\n return status == cudaStreamCaptureStatus::cudaStreamCaptureStatusActive;\n}\n\ninline bool doCheckError(cudaStream_t stream) {\n auto const cudaLaunchBlocking = isCudaLaunchBlocking();\n if (cudaLaunchBlocking.has_value() && cudaLaunchBlocking.value()) {\n return !isCapturing(stream);\n }\n\n#ifndef NDEBUG\n // Debug builds will sync when we're not capturing unless explicitly\n // disabled.\n bool const checkError = cudaLaunchBlocking.value_or(!isCapturing(stream));\n#else\n bool const checkError = cudaLaunchBlocking.value_or(false);\n#endif\n\n return checkError;\n}\n\ninline void syncAndCheck(cudaStream_t stream, char const* const file, int const line) {\n if (doCheckError(stream)) {\n cudaStreamSynchronize(stream);\n check(cudaGetLastError(), \"cudaGetLastError\", file, line);\n }\n}\n\n#define sync_check_cuda_error(stream) tensorrt_llm::common::syncAndCheck(stream, __FILE__, __LINE__)\n\n#define PRINT_FUNC_NAME_() \\\n do { \\\n std::cout << \"[TensorRT-LLM][CALL] \" << __FUNCTION__ << \" \" << std::endl; \\\n } while (0)\n\n// clang-format off\ntemplate<typename T> struct packed_type;\ntemplate <> struct packed_type<float> { using type = float; }; // we don't need to pack float by default\ntemplate <> struct packed_type<half> { using type = half2; };\n\n#ifdef ENABLE_BF16\ntemplate<>\nstruct packed_type<__nv_bfloat16> {\n using type = __nv_bfloat162;\n};\n#endif\n\n#ifdef ENABLE_FP8\ntemplate<>\nstruct packed_type<__nv_fp8_e4m3> {\n using type = __nv_fp8x2_e4m3;\n};\n#endif\n\ntemplate<typename T> struct num_elems;\ntemplate <> struct num_elems<float> { static constexpr int value = 1; };\ntemplate <> struct num_elems<float2> { static constexpr int value = 2; };\ntemplate <> struct num_elems<float4> { static constexpr int value = 4; };\ntemplate <> struct num_elems<half> { static constexpr int value = 1; };\ntemplate <> struct num_elems<half2> { static constexpr int value = 2; };\n#ifdef ENABLE_BF16\ntemplate <> struct num_elems<__nv_bfloat16> { static constexpr int value = 1; };\ntemplate <> struct num_elems<__nv_bfloat162> { static constexpr int value = 2; };\n#endif\n#ifdef ENABLE_FP8\ntemplate <> struct num_elems<__nv_fp8_e4m3> { static constexpr int value = 1; };\ntemplate <> struct num_elems<__nv_fp8x2_e4m3> { static constexpr int value = 2; };\n#endif\n\ntemplate<typename T, int num> struct packed_as;\ntemplate<typename T> struct packed_as<T, 1> { using type = T; };\ntemplate<> struct packed_as<half, 2> { using type = half2; };\ntemplate<> struct packed_as<float, 2> { using type = float2; };\ntemplate<> struct packed_as<int8_t, 2> { using type = int16_t; };\ntemplate<> struct packed_as<int32_t, 2> { using type = int2; };\ntemplate<> struct packed_as<half2, 1> { using type = half; };\ntemplate<> struct packed_as<float2, 1> { using type = float; };\n#ifdef ENABLE_BF16\ntemplate<> struct packed_as<__nv_bfloat16, 2> { using type = __nv_bfloat162; };\ntemplate<> struct packed_as<__nv_bfloat162, 1> { using type = __nv_bfloat16; };\n#endif\n#ifdef ENABLE_FP8\ntemplate<> struct packed_as<__nv_fp8_e4m3, 2> { using type = __nv_fp8x2_e4m3; };\ntemplate<> struct packed_as<__nv_fp8x2_e4m3, 1> { using type = __nv_fp8_e4m3; };\ntemplate<> struct packed_as<__nv_fp8_e5m2, 2> { using type = __nv_fp8x2_e5m2; };\ntemplate<> struct packed_as<__nv_fp8x2_e5m2, 1> { using type = __nv_fp8_e5m2; };\n#endif\n\ninline __device__ float2 operator*(float2 a, float2 b) { return make_float2(a.x * b.x, a.y * b.y); }\ninline __device__ float2 operator+(float2 a, float2 b) { return make_float2(a.x + b.x, a.y + b.y); }\ninline __device__ float2 operator-(float2 a, float2 b) { return make_float2(a.x - b.x, a.y - b.y); }\n\ninline __device__ float2 operator*(float2 a, float b) { return make_float2(a.x * b, a.y * b); }\ninline __device__ float2 operator+(float2 a, float b) { return make_float2(a.x + b, a.y + b); }\ninline __device__ float2 operator-(float2 a, float b) { return make_float2(a.x - b, a.y - b); }\n\n// clang-format on\n\ntemplate <typename T>\nstruct CudaDataType {};\n\ntemplate <>\nstruct CudaDataType<float> {\n static constexpr cudaDataType_t value = cudaDataType::CUDA_R_32F;\n};\n\ntemplate <>\nstruct CudaDataType<half> {\n static constexpr cudaDataType_t value = cudaDataType::CUDA_R_16F;\n};\n\n#ifdef ENABLE_BF16\ntemplate <>\nstruct CudaDataType<__nv_bfloat16> {\n static constexpr cudaDataType_t value = cudaDataType::CUDA_R_16BF;\n};\n#endif\n\ninline int getSMVersion() {\n int device{-1};\n check_cuda_error(cudaGetDevice(&device));\n int sm_major = 0;\n int sm_minor = 0;\n check_cuda_error(cudaDeviceGetAttribute(&sm_major, cudaDevAttrComputeCapabilityMajor, device));\n check_cuda_error(cudaDeviceGetAttribute(&sm_minor, cudaDevAttrComputeCapabilityMinor, device));\n return sm_major * 10 + sm_minor;\n}\n\ninline int getDevice() {\n int deviceID{0};\n check_cuda_error(cudaGetDevice(&deviceID));\n return deviceID;\n}\n\ninline int getDeviceCount() {\n int count{0};\n check_cuda_error(cudaGetDeviceCount(&count));\n return count;\n}\n\n/// @brief Identifies the memory type of the given pointer.\ntemplate <typename T>\ncudaMemoryType getPtrCudaMemoryType(T* ptr) {\n cudaPointerAttributes attributes{};\n check_cuda_error(cudaPointerGetAttributes(&attributes, ptr));\n return attributes.type;\n}\n\n/// Get the memory info\n/// \\return The free and total amount of memory in bytes\ninline std::tuple<size_t, size_t> getDeviceMemoryInfo(bool const useUvm) {\n if (useUvm) {\n size_t freeSysMem = 0;\n size_t totalSysMem = 0;\n#ifndef _WIN32 // Linux\n struct sysinfo info{};\n\n sysinfo(&info);\n totalSysMem = info.totalram * info.mem_unit;\n freeSysMem = info.freeram * info.mem_unit;\n#else // Windows\n MEMORYSTATUSEX memInfo;\n memInfo.dwLength = sizeof(memInfo);\n GlobalMemoryStatusEx(&memInfo);\n totalSysMem = memInfo.ullTotalPhys;\n freeSysMem = memInfo.ullAvailPhys;\n#endif // WIN32\n\n TLLM_LOG_INFO(\n \"Using UVM based system memory for KV cache, total memory %0.2f GB, available memory %0.2f \"\n \"GB\",\n ((double)totalSysMem / 1e9), ((double)freeSysMem / 1e9));\n return {freeSysMem, totalSysMem};\n }\n\n size_t free = 0;\n size_t total = 0;\n check_cuda_error(cudaMemGetInfo(&free, &total));\n TLLM_LOG_DEBUG(\"Using GPU memory for KV cache, total memory %0.2f GB, available memory %0.2f GB\",\n ((double)total / 1e9), ((double)free / 1e9));\n return {free, total};\n}\n\n/// @brief Gets the memory allocation granularity for the current device.\n///\n/// @return size_t The size of the smallest difference in memory size supported by the current\n/// device.\ninline size_t getAllocationGranularity() {\n auto const currentDevice = getDevice();\n ::CUmemAllocationProp prop = {};\n\n prop.type = ::CU_MEM_ALLOCATION_TYPE_PINNED;\n prop.location.type = ::CU_MEM_LOCATION_TYPE_DEVICE;\n prop.location.id = currentDevice;\n prop.requestedHandleTypes = ::CU_MEM_HANDLE_TYPE_NONE;\n\n // Get the minimum granularity supported for allocation with cuMemCreate()\n size_t granularity = 0;\n TLLM_CU_CHECK(\n cuMemGetAllocationGranularity(&granularity, &prop, CU_MEM_ALLOC_GRANULARITY_MINIMUM));\n return granularity;\n}\n\ninline int getMultiProcessorCount() {\n int nSM{0};\n int deviceID{0};\n check_cuda_error(cudaGetDevice(&deviceID));\n check_cuda_error(cudaDeviceGetAttribute(&nSM, cudaDevAttrMultiProcessorCount, deviceID));\n return nSM;\n}\n\ninline int getMaxSharedMemoryPerSM() {\n int nByteMaxSharedMemoryPerSM{0};\n int deviceID{0};\n check_cuda_error(cudaGetDevice(&deviceID));\n check_cuda_error(cudaDeviceGetAttribute(&nByteMaxSharedMemoryPerSM,\n cudaDevAttrMaxSharedMemoryPerMultiprocessor, deviceID));\n return nByteMaxSharedMemoryPerSM;\n}\n\ninline int getMaxSharedMemoryPerBlockOptin() {\n int nByteMaxSharedMemoryPerBlockOptin{0};\n int deviceID{0};\n check_cuda_error(cudaGetDevice(&deviceID));\n check_cuda_error(cudaDeviceGetAttribute(&nByteMaxSharedMemoryPerBlockOptin,\n cudaDevAttrMaxSharedMemoryPerBlockOptin, deviceID));\n return nByteMaxSharedMemoryPerBlockOptin;\n}\n\ntemplate <typename T1, typename T2>\ninline size_t divUp(T1 const& a, T2 const& b) {\n auto const tmp_a = static_cast<size_t>(a);\n auto const tmp_b = static_cast<size_t>(b);\n return (tmp_a + tmp_b - 1) / tmp_b;\n}\n\ninline int roundUp(int a, int b) { return divUp(a, b) * b; }\n\ntemplate <typename T, typename U, typename = std::enable_if_t<std::is_integral<T>::value>,\n typename = std::enable_if_t<std::is_integral<U>::value>>\nauto constexpr ceilDiv(T numerator, U denominator) {\n return (numerator + denominator - 1) / denominator;\n}\n\ntemplate <typename T>\nvoid printArrayInfo(T const* ptr, uint64_t nElement = 1, std::string name = \"\",\n bool const bPrintElement = false) {\n if (ptr == nullptr) {\n TLLM_LOG_WARNING(\"%s is an nullptr, skip!\", name.c_str());\n return;\n }\n cudaDeviceSynchronize();\n check_cuda_error(cudaGetLastError());\n\n bool const isDevicePtr = (getPtrCudaMemoryType(ptr) == cudaMemoryTypeDevice);\n size_t sizeInByte = sizeof(T) * nElement;\n TLLM_LOG_TRACE(\"addr=%p, location=%s, sizeof(T)=%lu, nElement=%d, sizeInByte=%lu\\n\", ptr,\n (isDevicePtr ? \"Device\" : \"Host\"), sizeof(T), nElement, sizeInByte);\n T* tmp = const_cast<T*>(ptr);\n std::vector<T> tmpVec; // For device pointer\n if (isDevicePtr) {\n tmpVec.resize(nElement);\n tmp = tmpVec.data();\n check_cuda_error(cudaMemcpy(tmp, ptr, sizeInByte, cudaMemcpyDeviceToHost));\n cudaDeviceSynchronize();\n }\n\n size_t nInf = 0;\n size_t nNaN = 0;\n size_t nZero = 0;\n double sum = 0.0;\n double sqrSum = 0.0;\n double absSum = 0.0;\n float allMax = -1.0e6f;\n float allMin = 1.0e6f;\n float allSad = 0.0f; // Sum Abs of Difference, to distinguish A and its transpose\n float old = 0.0f;\n for (uint64_t i = 0; i < nElement; i++) {\n float val = (float)tmp[i];\n\n if (std::isinf(val)) {\n nInf++;\n continue;\n }\n if (std::isnan(val)) {\n nNaN++;\n continue;\n }\n nZero += (val == 0.0f);\n sum += val;\n sqrSum += val * val;\n absSum += expf(val);\n allMax = std::max(allMax, val);\n allMin = std::min(allMin, val);\n allSad += abs(val - old);\n old = val;\n }\n float avg = sum / nElement;\n float std = sqrtf(sqrSum / nElement - avg * avg);\n\n TLLM_LOG_INFO(\"%s\", name.c_str());\n TLLM_LOG_INFO(\"size=%u, nInf=%zu, nNaN=%zu, nZero=%zu\", nElement, nInf, nNaN, nZero);\n TLLM_LOG_INFO(\"avg=%f, absSum: %f, std=%f, max=%f, min=%f, sad=%f\", avg, absSum, std, allMax,\n allMin, allSad);\n\n if (bPrintElement) {\n uint64_t constexpr nHead = 5;\n std::stringstream ss;\n ss << std::setw(10) << std::fixed << std::setprecision(3);\n for (uint64_t i = 0; i < std::min(nElement, nHead); ++i) {\n ss << (float)tmp[i] << \", \";\n }\n if (nElement > nHead) {\n ss << \" ... \";\n for (uint64_t i = nElement - nHead; i < nElement; ++i) {\n ss << (float)tmp[i] << \", \";\n }\n }\n TLLM_LOG_INFO(\"%s\", ss.str().c_str());\n }\n cudaDeviceSynchronize();\n check_cuda_error(cudaGetLastError());\n}\n\ntemplate void printArrayInfo(float const* ptr, uint64_t nElement, std::string name,\n bool const bPrintElement);\ntemplate void printArrayInfo(half const* ptr, uint64_t nElement, std::string name,\n bool const bPrintElement);\n#ifdef ENABLE_BF16\ntemplate void printArrayInfo(__nv_bfloat16 const* ptr, uint64_t nElement, std::string name,\n bool const bPrintElement);\n#endif\n#ifdef ENABLE_FP8\ntemplate void printArrayInfo(__nv_fp8_e4m3 const* ptr, uint64_t nElement, std::string name,\n bool const bPrintElement);\n#endif\ntemplate void printArrayInfo(uint32_t const* ptr, uint64_t nElement, std::string name,\n bool const bPrintElement);\ntemplate void printArrayInfo(uint64_t const* ptr, uint64_t nElement, std::string name,\n bool const bPrintElement);\ntemplate void printArrayInfo(int const* ptr, uint64_t nElement, std::string name,\n bool const bPrintElement);\ntemplate void printArrayInfo(uint8_t const* ptr, uint64_t nElement, std::string name,\n bool const bPrintElement);\n\ntemplate <typename T>\nvoid printToStream(T const* ptr, int const nElement, FILE* strm) {\n bool const split_rows = (strm == stdout);\n if (ptr == nullptr) {\n TLLM_LOG_WARNING(\"Nullptr, skip!\\n\");\n return;\n }\n std::vector<T> tmp(nElement, 0);\n check_cuda_error(cudaMemcpy(tmp.data(), ptr, sizeof(T) * nElement, cudaMemcpyDeviceToHost));\n for (int i = 0; i < nElement; ++i) {\n fprintf(strm, \"%f, \", static_cast<float>(tmp[i]));\n if (split_rows && ((i + 1) % 10) == 0) fprintf(strm, \"\\n\");\n }\n if (!split_rows || (nElement % 10) != 0) {\n fprintf(strm, \"\\n\");\n }\n}\n\ntemplate <typename T>\nvoid printToScreen(T const* ptr, int const nElement) {\n printToStream(ptr, nElement, stdout);\n}\n\ntemplate <typename T>\nvoid print2dToStream(T const* ptr, int const nRow, int const nCol, int const nStride, FILE* strm) {\n if (ptr == nullptr) {\n TLLM_LOG_WARNING(\"Nullptr, skip!\\n\");\n return;\n }\n for (int ri = 0; ri < nRow; ++ri) {\n T const* tmp = ptr + ri * nStride;\n printToStream(tmp, nCol, strm);\n }\n fprintf(strm, \"\\n\");\n}\n\ntemplate <typename T>\nvoid print2dToScreen(T const* ptr, int const nRow, int const nCol, int const nStride) {\n print2dToStream(ptr, nRow, nCol, nStride, stdout);\n}\n\ntemplate <typename T>\nvoid print2dToFile(std::string fname, T const* ptr, int const nRow, int const nCol,\n int const nStride) {\n FILE* fp = fopen(fname.c_str(), \"wt\");\n if (fp != nullptr) {\n print2dToStream(ptr, nRow, nCol, nStride, fp);\n fclose(fp);\n }\n}\n\n__host__ __device__ inline void print_float_(float x) { printf(\"%7.3f \", x); }\n\n__host__ __device__ inline void print_element_(float x) { print_float_(x); }\n\n__host__ __device__ inline void print_element_(half x) { print_float_((float)x); }\n\n#ifdef ENABLE_BF16\n__host__ __device__ inline void print_element_(__nv_bfloat16 x) { print_float_((float)x); }\n#endif\n\n#ifdef ENABLE_FP8\n__host__ __device__ inline void print_element_(__nv_fp8_e4m3 x) { print_float_((float)x); }\n#endif\n\n__host__ __device__ inline void print_element_(uint8_t ui) {\n printf(\"%7\" PRIu32 \" \", (unsigned int)ui);\n}\n\n__host__ __device__ inline void print_element_(uint32_t ul) { printf(\"%7\" PRIu32 \" \", ul); }\n\n__host__ __device__ inline void print_element_(uint64_t ull) { printf(\"%7\" PRIu64 \" \", ull); }\n\n__host__ __device__ inline void print_element_(int32_t il) { printf(\"%7\" PRId32 \" \", il); }\n\n__host__ __device__ inline void print_element_(int64_t ill) { printf(\"%7\" PRId64 \" \", ill); }\n\ntemplate <typename T>\n__host__ __device__ inline void print_elements(T const* ptr, int nRow, int nCol, int nStride) {\n for (int iRow = -1; iRow < nRow; ++iRow) {\n if (iRow >= 0) {\n printf(\"%07d|\", iRow);\n } else {\n printf(\" |\"); // heading row\n }\n for (int iCol = 0; iCol < nCol; iCol += 1) {\n if (iRow >= 0) {\n print_element_(ptr[iRow * nStride + iCol]);\n } else {\n printf(\"%7d|\", iCol); // heading colume\n }\n }\n printf(\"\\n\");\n }\n printf(\"\\n\");\n}\n\ntemplate <typename T>\ninline void printMatrix(T const* ptr, int nRow, int nCol, int nStride) {\n // `nRow` is length of row dimension\n // `nStride` is length of column dimension\n // `nCol` (<= nStride) is length for print per row\n if (ptr == nullptr) {\n TLLM_LOG_WARNING(\"Nullptr, skip!\\n\");\n return;\n }\n cudaDeviceSynchronize();\n check_cuda_error(cudaGetLastError());\n\n bool const isDevicePtr = (getPtrCudaMemoryType(ptr) == cudaMemoryTypeDevice);\n size_t sizeInByte = sizeof(T) * nRow * nStride;\n TLLM_LOG_TRACE(\"addr=%p, location=%s, sizeof(T)=%lu, nRow=%d, nStride=%d, sizeInByte=%lu\\n\", ptr,\n (isDevicePtr ? \"Device\" : \"Host\"), sizeof(T), nRow, nStride, sizeInByte);\n if (isDevicePtr) {\n std::vector<T> tmpVec;\n tmpVec.resize(nRow * nStride);\n T* tmp = tmpVec.data();\n check_cuda_error(cudaMemcpy(tmp, ptr, sizeInByte, cudaMemcpyDeviceToHost));\n cudaDeviceSynchronize();\n check_cuda_error(cudaGetLastError());\n print_elements(tmp, nRow, nCol, nStride);\n } else {\n print_elements(ptr, nRow, nCol, nStride);\n }\n}\n\ntemplate void printMatrix(float const* ptr, int nRow, int nCol, int nStride);\ntemplate void printMatrix(half const* ptr, int nRow, int nCol, int nStride);\n#ifdef ENABLE_BF16\ntemplate void printMatrix(__nv_bfloat16 const* ptr, int nRow, int nCol, int nStride);\n#endif\n#ifdef ENABLE_FP8\ntemplate void printMatrix(__nv_fp8_e4m3 const* ptr, int nRow, int nCol, int nStride);\n#endif\ntemplate void printMatrix(uint32_t const* ptr, int nRow, int nCol, int nStride);\ntemplate void printMatrix(uint64_t const* ptr, int nRow, int nCol, int nStride);\ntemplate void printMatrix(int const* ptr, int nRow, int nCol, int nStride);\ntemplate void printMatrix(uint8_t const* ptr, int nRow, int nCol, int nStride);\n\ntemplate <typename T>\n__device__ inline void printMatrixDevice(T const* ptr, int nRow, int nCol, int nStride) {\n // `nRow` is length of row dimension\n // `nStride` is length of column dimension\n // `nCol` (<= nStride) is length for print per row\n // Can be called inside kernels by one single thread\n if (ptr == nullptr) {\n printf(\"Nullptr, skip!\\n\");\n return;\n }\n size_t sizeInByte = sizeof(T) * nRow * nStride;\n printf(\"addr=%p, sizeof(T)=%lu, nRow=%d, nStride=%d, sizeInByte=%lu\\n\", ptr, sizeof(T), nRow,\n nStride, sizeInByte);\n print_elements(ptr, nRow, nCol, nStride);\n}\n\ntemplate __device__ void printMatrixDevice(float const* ptr, int nRow, int nCol, int nStride);\ntemplate __device__ void printMatrixDevice(half const* ptr, int nRow, int nCol, int nStride);\n#ifdef ENABLE_BF16\ntemplate __device__ void printMatrixDevice(__nv_bfloat16 const* ptr, int nRow, int nCol,\n int nStride);\n#endif\n#ifdef ENABLE_FP8\ntemplate __device__ void printMatrixDevice(__nv_fp8_e4m3 const* ptr, int nRow, int nCol,\n int nStride);\n#endif\ntemplate __device__ void printMatrixDevice(uint32_t const* ptr, int nRow, int nCol, int nStride);\ntemplate __device__ void printMatrixDevice(uint64_t const* ptr, int nRow, int nCol, int nStride);\ntemplate __device__ void printMatrixDevice(int const* ptr, int nRow, int nCol, int nStride);\ntemplate __device__ void printMatrixDevice(uint8_t const* ptr, int nRow, int nCol, int nStride);\n\n#ifndef CUDA_CALL\n#define CUDA_CALL(answer) \\\n { \\\n gpuAssert((answer), __FILE__, __LINE__); \\\n }\n\ninline void gpuAssert(cudaError_t code, char const* file, int line, bool abort = true) {\n if (code != cudaSuccess) {\n fprintf(stderr, \"CUDA error: %s @ %s:%d\\n\", cudaGetErrorString(code), file, line);\n if (abort) exit(code);\n }\n}\n\ninline void gpuAssert(CUresult code, char const* file, int line, bool abort = true) {\n if (code != CUresult::CUDA_SUCCESS) {\n char const* buf = \"Unknown error\";\n assert(cuGetErrorString(code, &buf) == CUresult::CUDA_SUCCESS);\n fprintf(stderr, \"Driver API error: %s @ %s:%d\\n\", buf, file, line);\n if (abort) exit(code);\n }\n}\n#endif\n\ntemplate <typename T>\nstruct UpperType;\n\ntemplate <>\nstruct UpperType<int8_t> {\n using Type = int;\n};\n\ntemplate <>\nstruct UpperType<uint32_t> {\n using Type = uint32_t;\n};\n\ntemplate <>\nstruct UpperType<int> {\n using Type = int;\n};\n\ntemplate <>\nstruct UpperType<__nv_bfloat16> {\n using Type = double;\n};\n\ntemplate <>\nstruct UpperType<half> {\n using Type = double;\n};\n\ntemplate <>\nstruct UpperType<float> {\n using Type = double;\n};\n\nextern \"C\" {\n__device__ uint32_t __nvvm_get_smem_pointer(void* ptr);\n}\n\n__forceinline__ __device__ void issue_stas(uint32_t dist_barrier_ptr, uint32_t dist_buffer_ptr,\n uint32_t d0) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900) && (__CUDACC_VER_MAJOR__ >= 12))\n asm volatile(\"st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.b32 [%0], %2, [%1];\\n\\t\"\n :\n : \"r\"(dist_buffer_ptr), \"r\"(dist_barrier_ptr), \"r\"(d0));\n#endif\n}\n\n__forceinline__ __device__ void issue_stas(uint32_t dist_barrier_ptr, uint32_t dist_buffer_ptr,\n uint64_t d0) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900) && (__CUDACC_VER_MAJOR__ >= 12))\n asm volatile(\"st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.b64 [%0], %2, [%1];\\n\\t\"\n :\n : \"r\"(dist_buffer_ptr), \"r\"(dist_barrier_ptr), \"l\"(d0));\n#endif\n}\n\n__forceinline__ __device__ void issue_stas(uint32_t dist_barrier_ptr, uint32_t dist_buffer_ptr,\n uint32_t d0, uint32_t d1) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900) && (__CUDACC_VER_MAJOR__ >= 12))\n asm volatile(\n \"st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.v2.b32 [%0], {%2, %3}, [%1];\\n\\t\"\n :\n : \"r\"(dist_buffer_ptr), \"r\"(dist_barrier_ptr), \"r\"(d0), \"r\"(d1));\n#endif\n}\n\n__forceinline__ __device__ void issue_stas(uint32_t dist_barrier_ptr, uint32_t dist_buffer_ptr,\n uint32_t d0, uint32_t d1, uint32_t d2, uint32_t d3) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900) && (__CUDACC_VER_MAJOR__ >= 12))\n asm volatile(\n \"st.async.shared::cluster.mbarrier::complete_tx::bytes.v4.b32 [%0], {%2, %3, %4, %5}, \"\n \"[%1];\\n\\t\"\n :\n : \"r\"(dist_buffer_ptr), \"r\"(dist_barrier_ptr), \"r\"(d0), \"r\"(d1), \"r\"(d2), \"r\"(d3));\n#endif\n}\n\ninline __device__ uint32_t elect_one_sync() {\n uint32_t pred = 0;\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900) && (__CUDACC_VER_MAJOR__ >= 12))\n#if (defined(__CUDA_ARCH_FEAT_SM90_ALL))\n uint32_t laneid = 0;\n asm volatile(\n \"\\n\\\n {\\n\\\n .reg .b32 %rx;\\n\\\n .reg .pred %px;\\n\\\n elect.sync %rx|%px, %2;\\n\\\n @%px mov.s32 %1, 1;\\n\\\n mov.s32 %0, %rx;\\n\\\n }\\n\\\n \"\n : \"+r\"(laneid), \"+r\"(pred)\n : \"r\"(0xFFFFFFFF));\n#endif\n#endif\n return pred;\n}\n\n__forceinline__ __device__ uint32_t get_smem_pointer(void const* ptr) {\n return __nvvm_get_smem_pointer(const_cast<void*>(ptr));\n}\n\n__forceinline__ __device__ void bar_create(void* bar_ptr, int init_count) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n unsigned smem_ptr = get_smem_pointer(bar_ptr);\n\n asm volatile(\n \"{\\n\\t\"\n \"mbarrier.init.shared.b64 [%1], %0; \\n\\t\"\n \"}\"\n :\n : \"r\"(init_count), \"r\"(smem_ptr));\n#endif\n}\n\nstruct Arrive_wait {\n public:\n __forceinline__ __device__ Arrive_wait() { bar_base_ = NULL; }\n\n __forceinline__ __device__ Arrive_wait(uint64_t* bar_base, int id = 0) {\n bar_base_ = bar_base;\n id_ = id;\n }\n\n __forceinline__ __device__ int bar_peek(int id, unsigned int bar_phase) {\n uint32_t result32{};\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n auto* bar_ptr = bar_base_ + id;\n unsigned smem_ptr = get_smem_pointer(bar_ptr);\n asm volatile(\n \"{\\n\\t\"\n \".reg .pred P1; \\n\\t\"\n \"mbarrier.try_wait.parity.shared.b64 P1, [%1], %2; \\n\\t\"\n \"selp.b32 %0, 1, 0, P1; \\n\\t\"\n \"}\"\n : \"=r\"(result32)\n : \"r\"(smem_ptr), \"r\"(bar_phase));\n#endif\n return result32;\n }\n\n __forceinline__ __device__ int bar_peek(int id, unsigned int bar_phase, int pred) {\n uint32_t result32{};\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n auto* bar_ptr = bar_base_ + id;\n unsigned smem_ptr = get_smem_pointer(bar_ptr);\n asm volatile(\n \"{\\n\\t\"\n \".reg .pred P1; \\n\\t\"\n \".reg .pred P2;\\n\\t\"\n \"setp.eq.u32 P2, %3, 1;\\n\\t\"\n \"@P2 mbarrier.try_wait.parity.shared.b64 P1, [%1], %2; \\n\\t\"\n \"selp.b32 %0, 1, 0, P1; \\n\\t\"\n \"}\"\n : \"=r\"(result32)\n : \"r\"(smem_ptr), \"r\"(bar_phase), \"r\"(pred));\n#endif\n return result32;\n }\n\n __forceinline__ __device__ void bar_wait(int id, unsigned int bar_phase) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n auto* bar_ptr = bar_base_ + id;\n unsigned smem_ptr = get_smem_pointer(bar_ptr);\n asm volatile(\n \"{\\n\\t\"\n \".reg .pred P1; \\n\\t\"\n \"LAB_WAIT: \\n\\t\"\n \"mbarrier.try_wait.parity.acquire.cta.shared::cta.b64 P1, [%0], %1; \\n\\t\"\n \"@P1 bra.uni DONE; \\n\\t\"\n \"bra.uni LAB_WAIT; \\n\\t\"\n \"DONE: \\n\\t\"\n \"}\"\n :\n : \"r\"(smem_ptr), \"r\"(bar_phase));\n#endif\n }\n\n __forceinline__ __device__ void bar_arrive_dsmem(int const& id) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n auto* bar_ptr = bar_base_ + id;\n asm volatile(\n \"{\\n\\t\"\n \"mbarrier.arrive.b64 _, [%0];\\n\\t\"\n \"}\"\n :\n : \"l\"(bar_ptr));\n#endif\n }\n\n __forceinline__ __device__ void bar_arrive_dsmem(int const& id, uint32_t const& pred) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n asm volatile(\n \"{\\n\\t\"\n \" .reg .pred p;\\n\\t\"\n \" .reg .s64 addr;\\n\\t\"\n \" .reg .b64 tmp;\\n\\t\"\n \" setp.eq.u32 p, %2, 1;\\n\\t\"\n \" mul.wide.s32 tmp, %0, 8;\\n\\t\"\n \" add.s64 addr, tmp, %1;\\n\\t\"\n \"@p mbarrier.arrive.b64 _, [addr];\\n\\t\"\n \"}\"\n :\n : \"r\"(id), \"l\"(bar_base_), \"r\"(pred));\n#endif\n }\n\n // Sets up the base address for arrival with the correct ctaid in cga\n __forceinline__ __device__ void set_bar_base_dsmem(uint32_t const& cta_id) {\n bar_base_ = reinterpret_cast<uint64_t*>(\n (reinterpret_cast<uintptr_t>(bar_base_) & 0xFFFFFFFFF0FFFFFFULL) + (cta_id << 24));\n }\n\n __forceinline__ __device__ void bar_arrive_normal(int id, bool flag = true) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n if (flag == true) {\n uint64_t* bar_ptr = reinterpret_cast<uint64_t*>(bar_base_ + id);\n unsigned smem_ptr = get_smem_pointer(bar_ptr);\n asm volatile(\n \"{\\n\\t\"\n \".reg .b64 state; \\n\\t\"\n \"mbarrier.arrive.shared.b64 state, [%0];\\n\\t\"\n \"}\"\n :\n : \"r\"(smem_ptr));\n }\n#endif\n }\n\n __forceinline__ __device__ void bar_arrive_set_transactioncnt(int id, int expected_copy_bytes) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n auto* bar_ptr = bar_base_ + id;\n unsigned smem_ptr = get_smem_pointer(bar_ptr);\n asm volatile(\n \"{\\n\\t\"\n \"mbarrier.arrive.expect_tx.shared.b64 _, [%0], %1; \\n\\t\"\n \"}\"\n :\n : \"r\"(smem_ptr), \"r\"(expected_copy_bytes));\n#endif\n }\n\n __forceinline__ __device__ void bar_arrive_set_transactioncnt(int id, int expected_copy_bytes,\n uint32_t pred) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n auto* bar_ptr = bar_base_ + id;\n unsigned smem_ptr = get_smem_pointer(bar_ptr);\n asm volatile(\n \"{\\n\\t\"\n \".reg .pred p;\\n\\t\"\n \"setp.eq.u32 p, %2, 1;\\n\\t\"\n \"@p mbarrier.arrive.expect_tx.shared.b64 _, [%0], %1; \\n\\t\"\n \"}\"\n :\n : \"r\"(smem_ptr), \"r\"(expected_copy_bytes), \"r\"(pred));\n#endif\n }\n\n __forceinline__ __device__ uint64_t* bar_base() { return bar_base_; }\n\n __forceinline__ __device__ uint64_t* get_bar_addr(int id) { return bar_base_ + id; }\n\n private:\n // smem barrier base pointer\n uint64_t* bar_base_;\n // barrier id\n int id_;\n};\n\n__forceinline__ __device__ void cga_sync() {\n#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 900\n asm volatile(\"barrier.cluster.sync;\\n\" : :);\n#endif\n}\n\n__forceinline__ __device__ void cga_arrive() {\n#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 900\n asm volatile(\"barrier.cluster.arrive.aligned;\\n\" : :);\n#endif\n}\n\n__forceinline__ __device__ void cga_wait() {\n#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 900\n asm volatile(\"barrier.cluster.wait.aligned;\\n\" : :);\n#endif\n}\n\ninline __device__ void fence_view_async_shared() {\n // only compiles on sm90+\n\n#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 900\n asm volatile(\"fence.proxy.async.shared::cta;\\n\" : :);\n#endif\n}\n\ntemplate <typename T>\n__forceinline__ __device__ T* get_DSMEM_ptr(T* localAddress, uint32_t destCtaId) {\n T* dsmemAddress = reinterpret_cast<T*>(\n ((unsigned long long int)localAddress & 0xFFFFFFFFF0FFFFFFULL) + (destCtaId << 24));\n return dsmemAddress;\n}\n\ntemplate <typename T>\n__forceinline__ __device__ void write_DSMEM_Address(T* localAddress, uint32_t destCtaId, T val) {\n T* dsmemAddress = get_DSMEM_ptr(localAddress, destCtaId);\n *dsmemAddress = val;\n}\n\n__forceinline__ __device__ void arrive_barrier(uint64_t* p_barrier, uint32_t arrive_cnt = 1) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n asm volatile(\"{mbarrier.arrive.shared.b64 _, [%0],%1;\\n\\t}\"\n :\n : \"l\"(p_barrier), \"r\"(arrive_cnt));\n#endif\n}\n\n__forceinline__ __device__ void arrive_DSMEM_barrier(uint64_t* p_barrier, uint32_t ctaid) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n uint64_t* p_barrier_remote = get_DSMEM_ptr(p_barrier, ctaid);\n asm volatile(\"{mbarrier.arrive.b64 _, [%0];\\n\\t}\" : : \"l\"(p_barrier_remote));\n#endif\n}\n\n__forceinline__ __device__ void arrive_DSMEM_barrier_and_set_tx_cnt(uint64_t* p_barrier,\n uint32_t ctaid,\n uint32_t expected_copy_bytes) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n uint32_t p_bar =\n static_cast<uint32_t>(reinterpret_cast<uintptr_t>(get_DSMEM_ptr(p_barrier, ctaid)));\n asm volatile(\"{mbarrier.arrive.expect_tx.b64 _, [%0], %1; \\n\\t}\" ::\"r\"(p_bar),\n \"r\"(expected_copy_bytes));\n#endif\n}\n\ntemplate <bool barSetTxCnt = true>\n__forceinline__ __device__ void stas(uint32_t* p_data, uint64_t* p_barrier, uint32_t ctaid,\n uint32_t const& wrdat) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n if (barSetTxCnt) arrive_DSMEM_barrier_and_set_tx_cnt(p_barrier, ctaid, sizeof(uint32_t));\n uint32_t buffer_ptr = static_cast<uint32_t>(reinterpret_cast<uintptr_t>(p_data));\n uint32_t barrier_ptr = static_cast<uint32_t>(reinterpret_cast<uintptr_t>(p_barrier));\n\n uint32_t buffer_ptr_, barrier_ptr_;\n asm volatile(\n \"{\\n\\t\"\n \"setctarank.shared.u32 %0, %2, %4;\\n\\t\"\n \"setctarank.shared.u32 %1, %3, %4;\\n\\t\"\n \"}\"\n : \"=r\"(buffer_ptr_), \"=r\"(barrier_ptr_)\n : \"r\"(buffer_ptr), \"r\"(barrier_ptr), \"r\"(ctaid));\n issue_stas(buffer_ptr_, barrier_ptr_, wrdat);\n#endif\n}\n\ntemplate <bool barSetTxCnt = true>\n__forceinline__ __device__ void stas(uint64_t* p_data, uint64_t* p_barrier, uint32_t ctaid,\n uint64_t const& wrdat) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n if (barSetTxCnt) arrive_DSMEM_barrier_and_set_tx_cnt(p_barrier, ctaid, sizeof(uint64_t));\n uint32_t buffer_ptr = static_cast<uint32_t>(reinterpret_cast<uintptr_t>(p_data));\n uint32_t barrier_ptr = static_cast<uint32_t>(reinterpret_cast<uintptr_t>(p_barrier));\n\n uint32_t buffer_ptr_, barrier_ptr_;\n asm volatile(\n \"{\\n\\t\"\n \"setctarank.shared.u32 %0, %2, %4;\\n\\t\"\n \"setctarank.shared.u32 %1, %3, %4;\\n\\t\"\n \"}\"\n : \"=r\"(buffer_ptr_), \"=r\"(barrier_ptr_)\n : \"r\"(buffer_ptr), \"r\"(barrier_ptr), \"r\"(ctaid));\n issue_stas(buffer_ptr_, barrier_ptr_, wrdat);\n#endif\n}\n\ntemplate <bool barSetTxCnt = true>\n__forceinline__ __device__ void stas(uint64_t* p_data, uint64_t* p_barrier, uint32_t ctaid,\n uint32_t const wrdat0, uint32_t const wrdat1,\n uint32_t const wrdat2, uint32_t const wrdat3) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n if (barSetTxCnt) arrive_DSMEM_barrier_and_set_tx_cnt(p_barrier, ctaid, 4 * sizeof(uint32_t));\n uint32_t buffer_ptr = static_cast<uint32_t>(reinterpret_cast<uintptr_t>(p_data));\n uint32_t barrier_ptr = static_cast<uint32_t>(reinterpret_cast<uintptr_t>(p_barrier));\n\n uint32_t buffer_ptr_, barrier_ptr_;\n asm volatile(\n \"{\\n\\t\"\n \"setctarank.shared.u32 %0, %2, %4;\\n\\t\"\n \"setctarank.shared.u32 %1, %3, %4;\\n\\t\"\n \"}\"\n : \"=r\"(buffer_ptr_), \"=r\"(barrier_ptr_)\n : \"r\"(buffer_ptr), \"r\"(barrier_ptr), \"r\"(ctaid));\n issue_stas(buffer_ptr_, barrier_ptr_, wrdat0, wrdat1, wrdat2, wrdat3);\n#endif\n}\n\ntemplate <bool barSetTxCnt = true, bool assumeAligned = true, typename T = void>\n__forceinline__ __device__ void stas(T* p_data, uint64_t* p_barrier, uint32_t ctaid,\n T const& wrdat) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n static_assert(sizeof(T) % 4 == 0);\n if (barSetTxCnt) arrive_DSMEM_barrier_and_set_tx_cnt(p_barrier, ctaid, sizeof(T));\n\n uint32_t buffer_ptr = static_cast<uint32_t>(reinterpret_cast<uintptr_t>(p_data));\n uint32_t barrier_ptr = static_cast<uint32_t>(reinterpret_cast<uintptr_t>(p_barrier));\n\n uint32_t buffer_ptr_, barrier_ptr_;\n asm volatile(\n \"{\\n\\t\"\n \"setctarank.shared.u32 %0, %2, %4;\\n\\t\"\n \"setctarank.shared.u32 %1, %3, %4;\\n\\t\"\n \"}\"\n : \"=r\"(buffer_ptr_), \"=r\"(barrier_ptr_)\n : \"r\"(buffer_ptr), \"r\"(barrier_ptr), \"r\"(ctaid));\n\n uint32_t const* p_wrdat_b32 = reinterpret_cast<uint32_t const*>(&wrdat);\n\n for (uint32_t offset = 0; offset < sizeof(T);) {\n if constexpr (assumeAligned) {\n if (offset + 16 <= sizeof(T)) {\n // Use write_async_v4_b32\n issue_stas(buffer_ptr_ + offset, barrier_ptr_, p_wrdat_b32[offset / 4],\n p_wrdat_b32[offset / 4 + 1], p_wrdat_b32[offset / 4 + 2],\n p_wrdat_b32[offset / 4 + 3]);\n offset += 16;\n } else if (offset + 8 <= sizeof(T) && (buffer_ptr + offset) % 8 == 0) {\n // Use write_async_v2_b32\n issue_stas(buffer_ptr + offset, barrier_ptr_, p_wrdat_b32[offset / 4],\n p_wrdat_b32[offset / 4 + 1]);\n offset += 8;\n } else {\n issue_stas(buffer_ptr + offset, barrier_ptr_, p_wrdat_b32[offset / 4]);\n offset += 4;\n }\n } else {\n issue_stas(buffer_ptr + offset, barrier_ptr_, p_wrdat_b32[offset / 4]);\n offset += 4;\n }\n }\n#endif\n}\n\nstruct OrderedMutex {\n uint64_t barriers[2];\n\n __device__ void init(int tid0, int threads0, int threads1) {\n if (tid0) {\n bar_create(&barriers[0], threads0);\n bar_create(&barriers[1], threads1);\n }\n }\n\n OrderedMutex() = default;\n OrderedMutex(OrderedMutex const& other) = delete;\n};\n\nclass OrderedMutexAccessor {\n public:\n struct State {\n int phase = 0;\n };\n\n private:\n int _phase;\n int _id;\n Arrive_wait _barriers;\n\n public:\n __device__ OrderedMutexAccessor(OrderedMutex& m, int id, State state)\n : _phase(state.phase), _id(id), _barriers(m.barriers) {}\n\n __device__ void arrive() { _barriers.bar_arrive_normal(_id); }\n\n __device__ void wait() {\n _barriers.bar_wait(_id ^ 1, _phase);\n _phase ^= 1;\n }\n\n __device__ State exportState() { return {.phase = _phase}; }\n};\n\ntemplate <typename T, T VALUE>\nstruct ConstExprWrapper {\n static constexpr T value = VALUE;\n};\n\ntemplate <int VALUE>\nusing Int = ConstExprWrapper<int, VALUE>;\n\ntemplate <bool VALUE>\nusing Bool = ConstExprWrapper<bool, VALUE>;\n\ntemplate <bool VALUE>\nusing ConstBool = ConstExprWrapper<bool, VALUE>;\n\ntemplate <typename T>\nstruct TmaDescType;\n\ntemplate <>\nstruct TmaDescType<__nv_bfloat16> {\n static constexpr auto value = CUtensorMapDataType_enum::CU_TENSOR_MAP_DATA_TYPE_BFLOAT16;\n};\n\ntemplate <>\nstruct TmaDescType<float> {\n static constexpr auto value = CUtensorMapDataType_enum::CU_TENSOR_MAP_DATA_TYPE_FLOAT32;\n};\n\n#define DEFINE_MEMBER_CHECKER(member) \\\n template <typename T, typename V = bool> \\\n struct has_##member : std::false_type {}; \\\n template <typename T> \\\n struct has_##member< \\\n T, typename std::enable_if<!std::is_same<decltype(std::declval<T>().member), void>::value, \\\n bool>::type> : std::true_type {};\n\n#define HAS_MEMBER(C, member) has_##member<C>::value\n\nDEFINE_MEMBER_CHECKER(output)\nDEFINE_MEMBER_CHECKER(residual)\nDEFINE_MEMBER_CHECKER(bias)\nDEFINE_MEMBER_CHECKER(deq)\nDEFINE_MEMBER_CHECKER(qua)\nDEFINE_MEMBER_CHECKER(high_preciecion_normed_output)\n\n} // namespace tensorrt_llm::common\n\n/*\n * Macros compliant with TensorRT coding conventions\n */\n#define TLLM_CUDA_CHECK(stat) \\\n do { \\\n tensorrt_llm::common::check((stat), #stat, __FILE__, __LINE__); \\\n } while (0)\n\n// We use singleton memory pool and the order of destructors depends on the compiler implementation.\n// We find that the cudaFree/cudaFreeHost is called after cudaruntime destruction on Windows. There\n// will be an cudaErrorCudartUnloading error. However, it is safe to ignore this error because the\n// cuda runtime is already exited, we are no more worried about the memory leaks.\n#define TLLM_CUDA_CHECK_FREE_RESOURCE(stat) \\\n do { \\\n tensorrt_llm::common::checkEx((stat), {cudaSuccess, cudaErrorCudartUnloading}, #stat, \\\n __FILE__, __LINE__); \\\n } while (0)\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\n### Key Findings\n\nWe observed that the Triton implementation outperforms the FlashInfer CUTLASS fused MoE backend on Hopper for BF16 data types (#3521), and thus we started investigating kernel optimization opportunities related to the associated kernels. Here are some key findings regarding the helper memory-bound kernels:\n* Lack of vectorization: In kernels such as `expandInputRowsKernel` and `doActivationKernel`, vectorization is not actually enabled. The generated SASS shows occurrences of four contiguous `LDG.E` instructions rather than a single `LDG.E.128`.\n* Inactive warp: The `doActivationKernel` is currently hardcoded to use 256 threads per row. For workloads with small intermediate sizes, this can be excessive and can result in inactive warps and suboptimal occupancy.\n\n### Changes Made\n\nThis PR improves the performance of the CUTLASS fused MoE input-expansion and activation kernels.\n * Explicitly vectorize global/store in `expandInputRowsKernel` and `doActivationKernel`.\n * This did not work on `finalizeMoeRoutingKernel` as it was observed to increase register usage and did not improve perf.\n * Select the activation kernel block size based on the work required per row, which reduces inactive warps and improves occupancy for smaller intermediate dimensions (e.g., 768 for `Qwen/Qwen3-30B-A3B`). Also, cap the grid size 8~32 blocks (which was constantly 8) per SM based on block size. This limits unnecessary warp-scheduling pressure.\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n#3521\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## ⚡ Performance\n\n### SASS verification (SM100, CUDA 13.2)\n\n| row-data access | before (main) | after (this PR) |\n|---|---|---|\n| expandInputRows (bf16→bf16), per 16B copy | 4× `LDG.E` + 4× `STG.E` | 1× `LDG.E.128` + 1× `STG.E.128` |\n| doActivation (bf16, Swiglu), per 16B of fc1/linear/bias | 4× `LDG.E` each | 1× `LDG.E.128` each |\n| doActivation (fp8 out, Swiglu), per 32B gemm vector | 8× `LDG.E` | 2× `LDG.E.128` |\n| doActivation (nvfp4 out, Swiglu), fp4 output + SF | unchanged (`STG.E` packed + `STG.E.U8`) | unchanged |\n\n### benchmarks/flashinfer_benchmark.py\n\n#### Setup\n * Single B100 (SM100), clocks locked at 1400 MHz SM / 4000 MHz mem, CUDA 13.2\n * Autotune off so both builds run identical default GEMM tactics\n * Baseline = main @ 2e97a607d\n * Cell = median of per-pair speedups\n\n#### Result\n* Achieved up to 1.08x end-to-end speedup\n* No regression observed\n\n| case | M=1 | M=16 | M=128 | M=512 | M=2048 | M=8192 | M=16384 |\n|---|---|---|---|---|---|---|---|\n| qwen3_tp1 | 1.00x | 0.99x | 1.00x | 0.99x | 1.02x | 1.04x | 1.05x |\n| qwen3_tp2 | 1.01x | 1.00x | 1.01x | 1.01x | 1.04x | 1.05x | 1.05x |\n| qwen3_tp4 | 1.00x | 1.00x | 1.01x | 1.01x | 1.04x | 1.04x | 1.05x |\n| qwen3_tp2_fp8 | 1.00x | 1.03x | 1.00x | 1.02x | 1.02x | 1.04x | 1.05x |\n| qwen3_tp4_fp8 | 1.00x | 1.00x | 1.01x | 1.03x | 1.06x | **1.07x** | **1.07x** |\n| dsv3_nvfp4 | 1.01x | 1.03x | 1.04x | 1.06x | **1.08x** | 1.01x | 1.05x |\n| mixtral_tp4 (guard) | 1.00x | 1.00x | 1.00x | 1.00x | 1.01x | 1.02x | 1.01x |\n\n### vLLM end-to-end benchmarking on H200x8\n\n#### Setup\n\n```\nvllm bench throughput --model Qwen/Qwen3-30B-A3B --dataset-name random --moe-backend <backend> -tp <tp>\n```\n\n#### Result\n\n| TP | main | this PR | gain | vs triton backend |\n|---:|---:|---:|---:|---:|\n| 1 | 41.52 | 42.09 | **+1.4%** | +1.5% |\n| 2 | 60.92 | 61.69 | **+1.3%** | −3.3% (was −4.5%) |\n| 4 | 69.36 | 71.51 | **+3.1%** | ~parity |\n| 8 | 74.17 | 75.74 | **+2.1%** | −2.4% |\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc. -->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n* **Performance**\n * Improved Mixture-of-Experts processing with vectorized memory operations for quantized, unquantized, and FP8 data paths.\n * Optimized activation workload distribution, memory access, and scaling across available GPU resources.\n\n* **Bug Fixes**\n * Added validation for memory alignment in MoE inputs, outputs, and biases.\n * Improved rounding utilities to support a broader range of integral values.\n\n* **Tests**\n * Added regression coverage confirming that improperly aligned inputs produce a clear diagnostic.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"e2e\", \"hardware\": \"B100\", \"model\": \"qwen3_tp1\", \"shape\": null, \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 1.0, \"optimized\": 1.0, \"stated_speedup\": 1.0, \"speedup\": 1.0}, {\"scope\": \"e2e\", \"hardware\": \"B100\", \"model\": \"qwen3_tp1\", \"shape\": null, \"batch_size\": 16, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 0.99, \"optimized\": 0.99, \"stated_speedup\": 0.99, \"speedup\": 1.0}, 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\"unit\": null, \"higher_is_better\": true, \"baseline\": 1.08, \"optimized\": 1.08, \"stated_speedup\": 1.08, \"speedup\": 1.0}, {\"scope\": \"e2e\", \"hardware\": \"B100\", \"model\": \"dsv3_nvfp4\", \"shape\": null, \"batch_size\": 8192, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 1.01, \"optimized\": 1.01, \"stated_speedup\": 1.01, \"speedup\": 1.0}, {\"scope\": \"e2e\", \"hardware\": \"B100\", \"model\": \"dsv3_nvfp4\", \"shape\": null, \"batch_size\": 16384, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 1.05, \"optimized\": 1.05, \"stated_speedup\": 1.05, \"speedup\": 1.0}, {\"scope\": \"e2e\", \"hardware\": \"B100\", \"model\": \"mixtral_tp4 (guard)\", \"shape\": null, \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 1.0, \"optimized\": 1.0, \"stated_speedup\": 1.0, \"speedup\": 1.0}, {\"scope\": \"e2e\", \"hardware\": \"B100\", \"model\": \"mixtral_tp4 (guard)\", \"shape\": null, \"batch_size\": 16, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 1.0, \"optimized\": 1.0, \"stated_speedup\": 1.0, \"speedup\": 1.0}, {\"scope\": \"e2e\", \"hardware\": \"B100\", \"model\": \"mixtral_tp4 (guard)\", \"shape\": null, \"batch_size\": 128, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 1.0, \"optimized\": 1.0, \"stated_speedup\": 1.0, \"speedup\": 1.0}, {\"scope\": \"e2e\", \"hardware\": \"B100\", \"model\": \"mixtral_tp4 (guard)\", \"shape\": null, \"batch_size\": 512, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 1.0, \"optimized\": 1.0, \"stated_speedup\": 1.0, \"speedup\": 1.0}, {\"scope\": \"e2e\", \"hardware\": \"B100\", \"model\": \"mixtral_tp4 (guard)\", \"shape\": null, \"batch_size\": 2048, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 1.01, \"optimized\": 1.01, \"stated_speedup\": 1.01, \"speedup\": 1.0}, {\"scope\": \"e2e\", \"hardware\": \"B100\", \"model\": \"mixtral_tp4 (guard)\", \"shape\": null, \"batch_size\": 8192, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 1.02, \"optimized\": 1.02, \"stated_speedup\": 1.02, \"speedup\": 1.0}, {\"scope\": \"e2e\", \"hardware\": \"B100\", \"model\": \"mixtral_tp4 (guard)\", \"shape\": null, \"batch_size\": 16384, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 1.01, \"optimized\": 1.01, \"stated_speedup\": 1.01, \"speedup\": 1.0}, {\"scope\": \"e2e\", \"hardware\": \"H200\", \"model\": \"Qwen/Qwen3-30B-A3B\", \"shape\": null, \"batch_size\": null, \"metric\": \"throughput\", \"unit\": \"tok/s\", \"higher_is_better\": true, \"baseline\": 41.52, \"optimized\": 42.09, \"stated_speedup\": 1.014, \"speedup\": 1.0137}, {\"scope\": \"e2e\", \"hardware\": \"H200\", \"model\": \"Qwen/Qwen3-30B-A3B\", \"shape\": null, \"batch_size\": null, \"metric\": \"throughput\", \"unit\": \"tok/s\", \"higher_is_better\": true, \"baseline\": 60.92, \"optimized\": 61.69, \"stated_speedup\": 1.013, \"speedup\": 1.0126}, {\"scope\": \"e2e\", \"hardware\": \"H200\", \"model\": \"Qwen/Qwen3-30B-A3B\", \"shape\": null, \"batch_size\": null, \"metric\": \"throughput\", \"unit\": \"tok/s\", \"higher_is_better\": true, \"baseline\": 69.36, \"optimized\": 71.51, \"stated_speedup\": 1.031, \"speedup\": 1.031}, {\"scope\": \"e2e\", \"hardware\": \"H200\", \"model\": \"Qwen/Qwen3-30B-A3B\", \"shape\": null, \"batch_size\": null, \"metric\": \"throughput\", \"unit\": \"tok/s\", \"higher_is_better\": true, \"baseline\": 74.17, \"optimized\": 75.74, \"stated_speedup\": 1.021, \"speedup\": 1.0212}]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"number","value":1,"string":"1"}}},{"rowIdx":1090,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"e9fb62b74e47444eba83da71a573c9437e71cb3b"},"date":{"kind":"string","value":"2026-08-11T18:29:38+08:00"},"pr_number":{"kind":"number","value":3761,"string":"3,761"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/3761"},"title":{"kind":"string","value":"perf(moe): optimize CUTLASS fused MoE mem-bound kernels (#3761)"},"message":{"kind":"string","value":"perf(moe): optimize CUTLASS fused MoE mem-bound kernels (#3761)\n\n<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\n### Key Findings\n\nWe observed that the Triton implementation outperforms the FlashInfer\nCUTLASS fused MoE backend on Hopper for BF16 data types (#3521), and\nthus we started investigating kernel optimization opportunities related\nto the associated kernels. Here are some key findings regarding the\nhelper memory-bound kernels:\n* Lack of vectorization: In kernels such as `expandInputRowsKernel` and\n`doActivationKernel`, vectorization is not actually enabled. The\ngenerated SASS shows occurrences of four contiguous `LDG.E` instructions\nrather than a single `LDG.E.128`.\n* Inactive warp: The `doActivationKernel` is currently hardcoded to use\n256 threads per row. For workloads with small intermediate sizes, this\ncan be excessive and can result in inactive warps and suboptimal\noccupancy.\n\n### Changes Made\n\nThis PR improves the performance of the CUTLASS fused MoE\ninput-expansion and activation kernels.\n* Explicitly vectorize global/store in `expandInputRowsKernel` and\n`doActivationKernel`.\n* This did not work on `finalizeMoeRoutingKernel` as it was observed to\nincrease register usage and did not improve perf.\n* Select the activation kernel block size based on the work required per\nrow, which reduces inactive warps and improves occupancy for smaller\nintermediate dimensions (e.g., 768 for `Qwen/Qwen3-30B-A3B`). Also, cap\nthe grid size 8~32 blocks (which was constantly 8) per SM based on block\nsize. This limits unnecessary warp-scheduling pressure.\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n#3521\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the\npre-commit documentation](https://pre-commit.com/).\n\n## ⚡ Performance\n\n### SASS verification (SM100, CUDA 13.2)\n\n| row-data access | before (main) | after (this PR) |\n|---|---|---|\n| expandInputRows (bf16→bf16), per 16B copy | 4× `LDG.E` + 4× `STG.E` |\n1× `LDG.E.128` + 1× `STG.E.128` |\n| doActivation (bf16, Swiglu), per 16B of fc1/linear/bias | 4× `LDG.E`\neach | 1× `LDG.E.128` each |\n| doActivation (fp8 out, Swiglu), per 32B gemm vector | 8× `LDG.E` | 2×\n`LDG.E.128` |\n| doActivation (nvfp4 out, Swiglu), fp4 output + SF | unchanged (`STG.E`\npacked + `STG.E.U8`) | unchanged |\n\n### benchmarks/flashinfer_benchmark.py\n\n#### Setup\n* Single B100 (SM100), clocks locked at 1400 MHz SM / 4000 MHz mem, CUDA\n13.2\n * Autotune off so both builds run identical default GEMM tactics\n * Baseline = main @ 2e97a607d\n * Cell = median of per-pair speedups\n\n#### Result\n* Achieved up to 1.08x end-to-end speedup\n* No regression observed\n\n| case | M=1 | M=16 | M=128 | M=512 | M=2048 | M=8192 | M=16384 |\n|---|---|---|---|---|---|---|---|\n| qwen3_tp1 | 1.00x | 0.99x | 1.00x | 0.99x | 1.02x | 1.04x | 1.05x |\n| qwen3_tp2 | 1.01x | 1.00x | 1.01x | 1.01x | 1.04x | 1.05x | 1.05x |\n| qwen3_tp4 | 1.00x | 1.00x | 1.01x | 1.01x | 1.04x | 1.04x | 1.05x |\n| qwen3_tp2_fp8 | 1.00x | 1.03x | 1.00x | 1.02x | 1.02x | 1.04x | 1.05x\n|\n| qwen3_tp4_fp8 | 1.00x | 1.00x | 1.01x | 1.03x | 1.06x | **1.07x** |\n**1.07x** |\n| dsv3_nvfp4 | 1.01x | 1.03x | 1.04x | 1.06x | **1.08x** | 1.01x | 1.05x\n|\n| mixtral_tp4 (guard) | 1.00x | 1.00x | 1.00x | 1.00x | 1.01x | 1.02x |\n1.01x |\n\n### vLLM end-to-end benchmarking on H200x8\n\n#### Setup\n\n```\nvllm bench throughput --model Qwen/Qwen3-30B-A3B --dataset-name random --moe-backend <backend> -tp <tp>\n```\n\n#### Result\n\n| TP | main | this PR | gain | vs triton backend |\n|---:|---:|---:|---:|---:|\n| 1 | 41.52 | 42.09 | **+1.4%** | +1.5% |\n| 2 | 60.92 | 61.69 | **+1.3%** | −3.3% (was −4.5%) |\n| 4 | 69.36 | 71.51 | **+3.1%** | ~parity |\n| 8 | 74.17 | 75.74 | **+2.1%** | −2.4% |\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc.\n-->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n* **Performance**\n* Improved Mixture-of-Experts processing with vectorized memory\noperations for quantized, unquantized, and FP8 data paths.\n* Optimized activation workload distribution, memory access, and scaling\nacross available GPU resources.\n\n* **Bug Fixes**\n* Added validation for memory alignment in MoE inputs, outputs, and\nbiases.\n* Improved rounding utilities to support a broader range of integral\nvalues.\n\n* **Tests**\n* Added regression coverage confirming that improperly aligned inputs\nproduce a clear diagnostic.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n\n---------\n\nSigned-off-by: Haobin Guo <haobing@nvidia.com>"},"path":{"kind":"string","value":"include/flashinfer/trtllm/common/cudaUtils.h"},"language":{"kind":"string","value":"cpp"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights\n * reserved. SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#pragma once\n\n// #include \"tensorrt_llm/common/cudaBf16Wrapper.h\"\n// #include \"tensorrt_llm/common/cudaDriverWrapper.h\"\n// #include \"tensorrt_llm/common/cudaFp8Utils.h\"\n// #include \"tensorrt_llm/common/logger.h\"\n// #include \"tensorrt_llm/common/tllmException.h\"\n\n#include <cublasLt.h>\n#include <cublas_v2.h>\n#include <cuda.h>\n#include <cuda_runtime.h>\n#include <driver_types.h>\n#ifdef ENABLE_FP8\n#include <cuda_fp8.h>\n#endif\n\n#include <algorithm>\n#include <cassert>\n#include <cinttypes>\n#include <cstdlib>\n#include <fstream>\n#include <iomanip>\n#include <memory>\n#include <optional>\n#include <sstream>\n#include <string>\n\n#include \"../../exception.h\"\n\n// #ifndef _WIN32 // Linux\n// #include <sys/sysinfo.h>\n// #endif // not WIN32\n// #include <vector>\n// #ifdef _WIN32 // Windows\n// #include <windows.h>\n// #undef ERROR // A Windows header file defines ERROR as 0, but it's used in our logger.h enum.\n// Logging breaks without\n// // this undef.\n// #endif // WIN32\n\nnamespace tensorrt_llm::common {\n\n// // workspace for cublas gemm : 32MB\n// #define CUBLAS_WORKSPACE_SIZE 33554432\n\n// typedef struct __align__(4)\n// {\n// half x, y, z, w;\n// }\n\n// half4;\n\n// /* **************************** type definition ***************************** */\n\n// enum CublasDataType\n// {\n// FLOAT_DATATYPE = 0,\n// HALF_DATATYPE = 1,\n// BFLOAT16_DATATYPE = 2,\n// INT8_DATATYPE = 3,\n// FP8_DATATYPE = 4\n// };\n\n// enum TRTLLMCudaDataType\n// {\n// FP32 = 0,\n// FP16 = 1,\n// BF16 = 2,\n// INT8 = 3,\n// FP8 = 4\n// };\n\n// enum class OperationType\n// {\n// FP32,\n// FP16,\n// BF16,\n// INT8,\n// FP8\n// };\n\n/* **************************** debug tools ********************************* */\n\ninline std::optional<bool> isCudaLaunchBlocking() {\n thread_local bool firstCall = true;\n thread_local std::optional<bool> result = std::nullopt;\n if (firstCall) {\n char const* env = std::getenv(\"CUDA_LAUNCH_BLOCKING\");\n if (env != nullptr && std::string(env) == \"1\") {\n result = true;\n } else {\n result = false;\n }\n firstCall = false;\n }\n return result;\n}\n\ninline std::optional<bool> isCapturing(cudaStream_t stream) {\n cudaStreamCaptureStatus status;\n FLASHINFER_CHECK(cudaStreamIsCapturing(stream, &status) == cudaSuccess,\n \"CUDA error in cudaStreamIsCapturing\");\n return status == cudaStreamCaptureStatus::cudaStreamCaptureStatusActive;\n}\n\ninline bool doCheckError(cudaStream_t stream) {\n auto const cudaLaunchBlocking = isCudaLaunchBlocking();\n if (cudaLaunchBlocking.has_value() && cudaLaunchBlocking.value()) {\n return !isCapturing(stream);\n }\n\n#ifndef NDEBUG\n // Debug builds will sync when we're not capturing unless explicitly\n // disabled.\n bool const checkError = cudaLaunchBlocking.value_or(!isCapturing(stream));\n#else\n bool const checkError = cudaLaunchBlocking.value_or(false);\n#endif\n\n return checkError;\n}\n\ninline void syncAndCheck(cudaStream_t stream, char const* const file, int const line) {\n if (doCheckError(stream)) {\n cudaStreamSynchronize(stream);\n auto error = cudaGetLastError();\n FLASHINFER_CHECK(error == cudaSuccess, \"CUDA error in %s: %s\", file, cudaGetErrorString(error));\n }\n}\n\n#define sync_check_cuda_error(stream) tensorrt_llm::common::syncAndCheck(stream, __FILE__, __LINE__)\n\ntemplate <typename T1, typename T2>\ninline size_t divUp(T1 const& a, T2 const& b) {\n auto const tmp_a = static_cast<size_t>(a);\n auto const tmp_b = static_cast<size_t>(b);\n return (tmp_a + tmp_b - 1) / tmp_b;\n}\n\ninline int roundUp(int a, int b) { return divUp(a, b) * b; }\n\ntemplate <typename T, typename U, typename = std::enable_if_t<std::is_integral<T>::value>,\n typename = std::enable_if_t<std::is_integral<U>::value>>\nauto constexpr ceilDiv(T numerator, U denominator) {\n return (numerator + denominator - 1) / denominator;\n}\n\ntemplate <typename T>\nstruct num_elems;\ntemplate <>\nstruct num_elems<float> {\n static constexpr int value = 1;\n};\ntemplate <>\nstruct num_elems<float2> {\n static constexpr int value = 2;\n};\ntemplate <>\nstruct num_elems<float4> {\n static constexpr int value = 4;\n};\ntemplate <>\nstruct num_elems<half> {\n static constexpr int value = 1;\n};\ntemplate <>\nstruct num_elems<half2> {\n static constexpr int value = 2;\n};\n#ifdef ENABLE_BF16\ntemplate <>\nstruct num_elems<__nv_bfloat16> {\n static constexpr int value = 1;\n};\ntemplate <>\nstruct num_elems<__nv_bfloat162> {\n static constexpr int value = 2;\n};\n#endif\n#ifdef ENABLE_FP8\ntemplate <>\nstruct num_elems<__nv_fp8_e4m3> {\n static constexpr int value = 1;\n};\ntemplate <>\nstruct num_elems<__nv_fp8x2_e4m3> {\n static constexpr int value = 2;\n};\n#endif\n\ntemplate <typename T, int num>\nstruct packed_as;\ntemplate <typename T>\nstruct packed_as<T, 1> {\n using type = T;\n};\ntemplate <>\nstruct packed_as<half, 2> {\n using type = half2;\n};\ntemplate <>\nstruct packed_as<float, 2> {\n using type = float2;\n};\ntemplate <>\nstruct packed_as<int8_t, 2> {\n using type = int16_t;\n};\ntemplate <>\nstruct packed_as<int32_t, 2> {\n using type = int2;\n};\ntemplate <>\nstruct packed_as<half2, 1> {\n using type = half;\n};\ntemplate <>\nstruct packed_as<float2, 1> {\n using type = float;\n};\n#ifdef ENABLE_BF16\ntemplate <>\nstruct packed_as<__nv_bfloat16, 2> {\n using type = __nv_bfloat162;\n};\ntemplate <>\nstruct packed_as<__nv_bfloat162, 1> {\n using type = __nv_bfloat16;\n};\n#endif\n#ifdef ENABLE_FP8\ntemplate <>\nstruct packed_as<__nv_fp8_e4m3, 2> {\n using type = __nv_fp8x2_e4m3;\n};\ntemplate <>\nstruct packed_as<__nv_fp8x2_e4m3, 1> {\n using type = __nv_fp8_e4m3;\n};\ntemplate <>\nstruct packed_as<__nv_fp8_e5m2, 2> {\n using type = __nv_fp8x2_e5m2;\n};\ntemplate <>\nstruct packed_as<__nv_fp8x2_e5m2, 1> {\n using type = __nv_fp8_e5m2;\n};\n#endif\n\ninline __device__ float2 operator*(float2 a, float2 b) { return make_float2(a.x * b.x, a.y * b.y); }\ninline __device__ float2 operator+(float2 a, float2 b) { return make_float2(a.x + b.x, a.y + b.y); }\ninline __device__ float2 operator-(float2 a, float2 b) { return make_float2(a.x - b.x, a.y - b.y); }\n\ninline __device__ float2 operator*(float2 a, float b) { return make_float2(a.x * b, a.y * b); }\ninline __device__ float2 operator+(float2 a, float b) { return make_float2(a.x + b, a.y + b); }\ninline __device__ float2 operator-(float2 a, float b) { return make_float2(a.x - b, a.y - b); }\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n// Device query helpers — thin wrappers around CUDA runtime queries.\n////////////////////////////////////////////////////////////////////////////////////////////////////\n\ninline int getSMVersion() {\n int device{-1};\n FLASHINFER_CHECK(cudaGetDevice(&device) == cudaSuccess, \"cudaGetDevice failed\");\n int sm_major = 0;\n int sm_minor = 0;\n FLASHINFER_CHECK(\n cudaDeviceGetAttribute(&sm_major, cudaDevAttrComputeCapabilityMajor, device) == cudaSuccess,\n \"cudaDeviceGetAttribute(ComputeCapabilityMajor) failed\");\n FLASHINFER_CHECK(\n cudaDeviceGetAttribute(&sm_minor, cudaDevAttrComputeCapabilityMinor, device) == cudaSuccess,\n \"cudaDeviceGetAttribute(ComputeCapabilityMinor) failed\");\n return sm_major * 10 + sm_minor;\n}\n\ninline int getMultiProcessorCount() {\n int device{-1};\n FLASHINFER_CHECK(cudaGetDevice(&device) == cudaSuccess, \"cudaGetDevice failed\");\n int count = 0;\n FLASHINFER_CHECK(\n cudaDeviceGetAttribute(&count, cudaDevAttrMultiProcessorCount, device) == cudaSuccess,\n \"cudaDeviceGetAttribute(MultiProcessorCount) failed\");\n return count;\n}\n\n} // namespace tensorrt_llm::common\n"},"after_code":{"kind":"string","value":"/*\n * SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights\n * reserved. SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#pragma once\n\n// #include \"tensorrt_llm/common/cudaBf16Wrapper.h\"\n// #include \"tensorrt_llm/common/cudaDriverWrapper.h\"\n// #include \"tensorrt_llm/common/cudaFp8Utils.h\"\n// #include \"tensorrt_llm/common/logger.h\"\n// #include \"tensorrt_llm/common/tllmException.h\"\n\n#include <cublasLt.h>\n#include <cublas_v2.h>\n#include <cuda.h>\n#include <cuda_runtime.h>\n#include <driver_types.h>\n#ifdef ENABLE_FP8\n#include <cuda_fp8.h>\n#endif\n\n#include <algorithm>\n#include <cassert>\n#include <cinttypes>\n#include <cstdlib>\n#include <fstream>\n#include <iomanip>\n#include <memory>\n#include <optional>\n#include <sstream>\n#include <string>\n\n#include \"../../exception.h\"\n\n// #ifndef _WIN32 // Linux\n// #include <sys/sysinfo.h>\n// #endif // not WIN32\n// #include <vector>\n// #ifdef _WIN32 // Windows\n// #include <windows.h>\n// #undef ERROR // A Windows header file defines ERROR as 0, but it's used in our logger.h enum.\n// Logging breaks without\n// // this undef.\n// #endif // WIN32\n\nnamespace tensorrt_llm::common {\n\n// // workspace for cublas gemm : 32MB\n// #define CUBLAS_WORKSPACE_SIZE 33554432\n\n// typedef struct __align__(4)\n// {\n// half x, y, z, w;\n// }\n\n// half4;\n\n// /* **************************** type definition ***************************** */\n\n// enum CublasDataType\n// {\n// FLOAT_DATATYPE = 0,\n// HALF_DATATYPE = 1,\n// BFLOAT16_DATATYPE = 2,\n// INT8_DATATYPE = 3,\n// FP8_DATATYPE = 4\n// };\n\n// enum TRTLLMCudaDataType\n// {\n// FP32 = 0,\n// FP16 = 1,\n// BF16 = 2,\n// INT8 = 3,\n// FP8 = 4\n// };\n\n// enum class OperationType\n// {\n// FP32,\n// FP16,\n// BF16,\n// INT8,\n// FP8\n// };\n\n/* **************************** debug tools ********************************* */\n\ninline std::optional<bool> isCudaLaunchBlocking() {\n thread_local bool firstCall = true;\n thread_local std::optional<bool> result = std::nullopt;\n if (firstCall) {\n char const* env = std::getenv(\"CUDA_LAUNCH_BLOCKING\");\n if (env != nullptr && std::string(env) == \"1\") {\n result = true;\n } else {\n result = false;\n }\n firstCall = false;\n }\n return result;\n}\n\ninline std::optional<bool> isCapturing(cudaStream_t stream) {\n cudaStreamCaptureStatus status;\n FLASHINFER_CHECK(cudaStreamIsCapturing(stream, &status) == cudaSuccess,\n \"CUDA error in cudaStreamIsCapturing\");\n return status == cudaStreamCaptureStatus::cudaStreamCaptureStatusActive;\n}\n\ninline bool doCheckError(cudaStream_t stream) {\n auto const cudaLaunchBlocking = isCudaLaunchBlocking();\n if (cudaLaunchBlocking.has_value() && cudaLaunchBlocking.value()) {\n return !isCapturing(stream);\n }\n\n#ifndef NDEBUG\n // Debug builds will sync when we're not capturing unless explicitly\n // disabled.\n bool const checkError = cudaLaunchBlocking.value_or(!isCapturing(stream));\n#else\n bool const checkError = cudaLaunchBlocking.value_or(false);\n#endif\n\n return checkError;\n}\n\ninline void syncAndCheck(cudaStream_t stream, char const* const file, int const line) {\n if (doCheckError(stream)) {\n cudaStreamSynchronize(stream);\n auto error = cudaGetLastError();\n FLASHINFER_CHECK(error == cudaSuccess, \"CUDA error in %s: %s\", file, cudaGetErrorString(error));\n }\n}\n\n#define sync_check_cuda_error(stream) tensorrt_llm::common::syncAndCheck(stream, __FILE__, __LINE__)\n\ntemplate <typename T1, typename T2>\ninline size_t divUp(T1 const& a, T2 const& b) {\n auto const tmp_a = static_cast<size_t>(a);\n auto const tmp_b = static_cast<size_t>(b);\n return (tmp_a + tmp_b - 1) / tmp_b;\n}\n\ntemplate <typename T, typename U, typename = std::enable_if_t<std::is_integral<T>::value>,\n typename = std::enable_if_t<std::is_integral<U>::value>>\nauto constexpr ceilDiv(T numerator, U denominator) {\n return (numerator + denominator - 1) / denominator;\n}\n\ntemplate <typename T, typename U, typename = std::enable_if_t<std::is_integral<T>::value>,\n typename = std::enable_if_t<std::is_integral<U>::value>>\nauto constexpr roundUp(T numerator, U denominator) {\n return ceilDiv(numerator, denominator) * denominator;\n}\n\ntemplate <typename T>\nstruct num_elems;\ntemplate <>\nstruct num_elems<float> {\n static constexpr int value = 1;\n};\ntemplate <>\nstruct num_elems<float2> {\n static constexpr int value = 2;\n};\ntemplate <>\nstruct num_elems<float4> {\n static constexpr int value = 4;\n};\ntemplate <>\nstruct num_elems<half> {\n static constexpr int value = 1;\n};\ntemplate <>\nstruct num_elems<half2> {\n static constexpr int value = 2;\n};\n#ifdef ENABLE_BF16\ntemplate <>\nstruct num_elems<__nv_bfloat16> {\n static constexpr int value = 1;\n};\ntemplate <>\nstruct num_elems<__nv_bfloat162> {\n static constexpr int value = 2;\n};\n#endif\n#ifdef ENABLE_FP8\ntemplate <>\nstruct num_elems<__nv_fp8_e4m3> {\n static constexpr int value = 1;\n};\ntemplate <>\nstruct num_elems<__nv_fp8x2_e4m3> {\n static constexpr int value = 2;\n};\n#endif\n\ntemplate <typename T, int num>\nstruct packed_as;\ntemplate <typename T>\nstruct packed_as<T, 1> {\n using type = T;\n};\ntemplate <>\nstruct packed_as<half, 2> {\n using type = half2;\n};\ntemplate <>\nstruct packed_as<float, 2> {\n using type = float2;\n};\ntemplate <>\nstruct packed_as<int8_t, 2> {\n using type = int16_t;\n};\ntemplate <>\nstruct packed_as<int32_t, 2> {\n using type = int2;\n};\ntemplate <>\nstruct packed_as<half2, 1> {\n using type = half;\n};\ntemplate <>\nstruct packed_as<float2, 1> {\n using type = float;\n};\n#ifdef ENABLE_BF16\ntemplate <>\nstruct packed_as<__nv_bfloat16, 2> {\n using type = __nv_bfloat162;\n};\ntemplate <>\nstruct packed_as<__nv_bfloat162, 1> {\n using type = __nv_bfloat16;\n};\n#endif\n#ifdef ENABLE_FP8\ntemplate <>\nstruct packed_as<__nv_fp8_e4m3, 2> {\n using type = __nv_fp8x2_e4m3;\n};\ntemplate <>\nstruct packed_as<__nv_fp8x2_e4m3, 1> {\n using type = __nv_fp8_e4m3;\n};\ntemplate <>\nstruct packed_as<__nv_fp8_e5m2, 2> {\n using type = __nv_fp8x2_e5m2;\n};\ntemplate <>\nstruct packed_as<__nv_fp8x2_e5m2, 1> {\n using type = __nv_fp8_e5m2;\n};\n#endif\n\ninline __device__ float2 operator*(float2 a, float2 b) { return make_float2(a.x * b.x, a.y * b.y); }\ninline __device__ float2 operator+(float2 a, float2 b) { return make_float2(a.x + b.x, a.y + b.y); }\ninline __device__ float2 operator-(float2 a, float2 b) { return make_float2(a.x - b.x, a.y - b.y); }\n\ninline __device__ float2 operator*(float2 a, float b) { return make_float2(a.x * b, a.y * b); }\ninline __device__ float2 operator+(float2 a, float b) { return make_float2(a.x + b, a.y + b); }\ninline __device__ float2 operator-(float2 a, float b) { return make_float2(a.x - b, a.y - b); }\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n// Device query helpers — thin wrappers around CUDA runtime queries.\n////////////////////////////////////////////////////////////////////////////////////////////////////\n\ninline int getSMVersion() {\n int device{-1};\n FLASHINFER_CHECK(cudaGetDevice(&device) == cudaSuccess, \"cudaGetDevice failed\");\n int sm_major = 0;\n int sm_minor = 0;\n FLASHINFER_CHECK(\n cudaDeviceGetAttribute(&sm_major, cudaDevAttrComputeCapabilityMajor, device) == cudaSuccess,\n \"cudaDeviceGetAttribute(ComputeCapabilityMajor) failed\");\n FLASHINFER_CHECK(\n cudaDeviceGetAttribute(&sm_minor, cudaDevAttrComputeCapabilityMinor, device) == cudaSuccess,\n \"cudaDeviceGetAttribute(ComputeCapabilityMinor) failed\");\n return sm_major * 10 + sm_minor;\n}\n\ninline int getMultiProcessorCount() {\n int device{-1};\n FLASHINFER_CHECK(cudaGetDevice(&device) == cudaSuccess, \"cudaGetDevice failed\");\n int count = 0;\n FLASHINFER_CHECK(\n cudaDeviceGetAttribute(&count, cudaDevAttrMultiProcessorCount, device) == cudaSuccess,\n \"cudaDeviceGetAttribute(MultiProcessorCount) failed\");\n return count;\n}\n\n} // namespace tensorrt_llm::common\n"},"diff":{"kind":"string","value":"--- include/flashinfer/trtllm/common/cudaUtils.h\n+++ include/flashinfer/trtllm/common/cudaUtils.h\n@@ -154,12 +154,16 @@\n return (tmp_a + tmp_b - 1) / tmp_b;\n }\n \n-inline int roundUp(int a, int b) { return divUp(a, b) * b; }\n-\n template <typename T, typename U, typename = std::enable_if_t<std::is_integral<T>::value>,\n typename = std::enable_if_t<std::is_integral<U>::value>>\n auto constexpr ceilDiv(T numerator, U denominator) {\n return (numerator + denominator - 1) / denominator;\n+}\n+\n+template <typename T, typename U, typename = std::enable_if_t<std::is_integral<T>::value>,\n+ typename = std::enable_if_t<std::is_integral<U>::value>>\n+auto constexpr roundUp(T numerator, U denominator) {\n+ return ceilDiv(numerator, denominator) * denominator;\n }\n \n template <typename T>"},"lines_added":{"kind":"number","value":6,"string":"6"},"lines_removed":{"kind":"number","value":2,"string":"2"},"files_in_commit":{"kind":"number","value":3,"string":"3"},"models_mentioned":{"kind":"list like","value":["deepseek","qwen","mixtral"],"string":"[\n \"deepseek\",\n \"qwen\",\n \"mixtral\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["HOPPER","SM100"],"string":"[\n \"HOPPER\",\n \"SM100\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":["4×","4×","1×","1×","4×","1×","8×","2×","1.08x","1.00x"],"string":"[\n \"4×\",\n \"4×\",\n \"1×\",\n \"1×\",\n \"4×\",\n \"1×\",\n \"8×\",\n \"2×\",\n \"1.08x\",\n \"1.00x\"\n]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cpp kernel file from flashinfer (include/flashinfer/trtllm/common/cudaUtils.h).\n\nGoal: perf(moe): optimize CUTLASS fused MoE mem-bound kernels\nTarget hardware: HOPPER, SM100\nTarget models: deepseek, qwen, mixtral\n\nCurrent file:\n```cpp\n/*\n * SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights\n * reserved. SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#pragma once\n\n// #include \"tensorrt_llm/common/cudaBf16Wrapper.h\"\n// #include \"tensorrt_llm/common/cudaDriverWrapper.h\"\n// #include \"tensorrt_llm/common/cudaFp8Utils.h\"\n// #include \"tensorrt_llm/common/logger.h\"\n// #include \"tensorrt_llm/common/tllmException.h\"\n\n#include <cublasLt.h>\n#include <cublas_v2.h>\n#include <cuda.h>\n#include <cuda_runtime.h>\n#include <driver_types.h>\n#ifdef ENABLE_FP8\n#include <cuda_fp8.h>\n#endif\n\n#include <algorithm>\n#include <cassert>\n#include <cinttypes>\n#include <cstdlib>\n#include <fstream>\n#include <iomanip>\n#include <memory>\n#include <optional>\n#include <sstream>\n#include <string>\n\n#include \"../../exception.h\"\n\n// #ifndef _WIN32 // Linux\n// #include <sys/sysinfo.h>\n// #endif // not WIN32\n// #include <vector>\n// #ifdef _WIN32 // Windows\n// #include <windows.h>\n// #undef ERROR // A Windows header file defines ERROR as 0, but it's used in our logger.h enum.\n// Logging breaks without\n// // this undef.\n// #endif // WIN32\n\nnamespace tensorrt_llm::common {\n\n// // workspace for cublas gemm : 32MB\n// #define CUBLAS_WORKSPACE_SIZE 33554432\n\n// typedef struct __align__(4)\n// {\n// half x, y, z, w;\n// }\n\n// half4;\n\n// /* **************************** type definition ***************************** */\n\n// enum CublasDataType\n// {\n// FLOAT_DATATYPE = 0,\n// HALF_DATATYPE = 1,\n// BFLOAT16_DATATYPE = 2,\n// INT8_DATATYPE = 3,\n// FP8_DATATYPE = 4\n// };\n\n// enum TRTLLMCudaDataType\n// {\n// FP32 = 0,\n// FP16 = 1,\n// BF16 = 2,\n// INT8 = 3,\n// FP8 = 4\n// };\n\n// enum class OperationType\n// {\n// FP32,\n// FP16,\n// BF16,\n// INT8,\n// FP8\n// };\n\n/* **************************** debug tools ********************************* */\n\ninline std::optional<bool> isCudaLaunchBlocking() {\n thread_local bool firstCall = true;\n thread_local std::optional<bool> result = std::nullopt;\n if (firstCall) {\n char const* env = std::getenv(\"CUDA_LAUNCH_BLOCKING\");\n if (env != nullptr && std::string(env) == \"1\") {\n result = true;\n } else {\n result = false;\n }\n firstCall = false;\n }\n return result;\n}\n\ninline std::optional<bool> isCapturing(cudaStream_t stream) {\n cudaStreamCaptureStatus status;\n FLASHINFER_CHECK(cudaStreamIsCapturing(stream, &status) == cudaSuccess,\n \"CUDA error in cudaStreamIsCapturing\");\n return status == cudaStreamCaptureStatus::cudaStreamCaptureStatusActive;\n}\n\ninline bool doCheckError(cudaStream_t stream) {\n auto const cudaLaunchBlocking = isCudaLaunchBlocking();\n if (cudaLaunchBlocking.has_value() && cudaLaunchBlocking.value()) {\n return !isCapturing(stream);\n }\n\n#ifndef NDEBUG\n // Debug builds will sync when we're not capturing unless explicitly\n // disabled.\n bool const checkError = cudaLaunchBlocking.value_or(!isCapturing(stream));\n#else\n bool const checkError = cudaLaunchBlocking.value_or(false);\n#endif\n\n return checkError;\n}\n\ninline void syncAndCheck(cudaStream_t stream, char const* const file, int const line) {\n if (doCheckError(stream)) {\n cudaStreamSynchronize(stream);\n auto error = cudaGetLastError();\n FLASHINFER_CHECK(error == cudaSuccess, \"CUDA error in %s: %s\", file, cudaGetErrorString(error));\n }\n}\n\n#define sync_check_cuda_error(stream) tensorrt_llm::common::syncAndCheck(stream, __FILE__, __LINE__)\n\ntemplate <typename T1, typename T2>\ninline size_t divUp(T1 const& a, T2 const& b) {\n auto const tmp_a = static_cast<size_t>(a);\n auto const tmp_b = static_cast<size_t>(b);\n return (tmp_a + tmp_b - 1) / tmp_b;\n}\n\ninline int roundUp(int a, int b) { return divUp(a, b) * b; }\n\ntemplate <typename T, typename U, typename = std::enable_if_t<std::is_integral<T>::value>,\n typename = std::enable_if_t<std::is_integral<U>::value>>\nauto constexpr ceilDiv(T numerator, U denominator) {\n return (numerator + denominator - 1) / denominator;\n}\n\ntemplate <typename T>\nstruct num_elems;\ntemplate <>\nstruct num_elems<float> {\n static constexpr int value = 1;\n};\ntemplate <>\nstruct num_elems<float2> {\n static constexpr int value = 2;\n};\ntemplate <>\nstruct num_elems<float4> {\n static constexpr int value = 4;\n};\ntemplate <>\nstruct num_elems<half> {\n static constexpr int value = 1;\n};\ntemplate <>\nstruct num_elems<half2> {\n static constexpr int value = 2;\n};\n#ifdef ENABLE_BF16\ntemplate <>\nstruct num_elems<__nv_bfloat16> {\n static constexpr int value = 1;\n};\ntemplate <>\nstruct num_elems<__nv_bfloat162> {\n static constexpr int value = 2;\n};\n#endif\n#ifdef ENABLE_FP8\ntemplate <>\nstruct num_elems<__nv_fp8_e4m3> {\n static constexpr int value = 1;\n};\ntemplate <>\nstruct num_elems<__nv_fp8x2_e4m3> {\n static constexpr int value = 2;\n};\n#endif\n\ntemplate <typename T, int num>\nstruct packed_as;\ntemplate <typename T>\nstruct packed_as<T, 1> {\n using type = T;\n};\ntemplate <>\nstruct packed_as<half, 2> {\n using type = half2;\n};\ntemplate <>\nstruct packed_as<float, 2> {\n using type = float2;\n};\ntemplate <>\nstruct packed_as<int8_t, 2> {\n using type = int16_t;\n};\ntemplate <>\nstruct packed_as<int32_t, 2> {\n using type = int2;\n};\ntemplate <>\nstruct packed_as<half2, 1> {\n using type = half;\n};\ntemplate <>\nstruct packed_as<float2, 1> {\n using type = float;\n};\n#ifdef ENABLE_BF16\ntemplate <>\nstruct packed_as<__nv_bfloat16, 2> {\n using type = __nv_bfloat162;\n};\ntemplate <>\nstruct packed_as<__nv_bfloat162, 1> {\n using type = __nv_bfloat16;\n};\n#endif\n#ifdef ENABLE_FP8\ntemplate <>\nstruct packed_as<__nv_fp8_e4m3, 2> {\n using type = __nv_fp8x2_e4m3;\n};\ntemplate <>\nstruct packed_as<__nv_fp8x2_e4m3, 1> {\n using type = __nv_fp8_e4m3;\n};\ntemplate <>\nstruct packed_as<__nv_fp8_e5m2, 2> {\n using type = __nv_fp8x2_e5m2;\n};\ntemplate <>\nstruct packed_as<__nv_fp8x2_e5m2, 1> {\n using type = __nv_fp8_e5m2;\n};\n#endif\n\ninline __device__ float2 operator*(float2 a, float2 b) { return make_float2(a.x * b.x, a.y * b.y); }\ninline __device__ float2 operator+(float2 a, float2 b) { return make_float2(a.x + b.x, a.y + b.y); }\ninline __device__ float2 operator-(float2 a, float2 b) { return make_float2(a.x - b.x, a.y - b.y); }\n\ninline __device__ float2 operator*(float2 a, float b) { return make_float2(a.x * b, a.y * b); }\ninline __device__ float2 operator+(float2 a, float b) { return make_float2(a.x + b, a.y + b); }\ninline __device__ float2 operator-(float2 a, float b) { return make_float2(a.x - b, a.y - b); }\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n// Device query helpers — thin wrappers around CUDA runtime queries.\n////////////////////////////////////////////////////////////////////////////////////////////////////\n\ninline int getSMVersion() {\n int device{-1};\n FLASHINFER_CHECK(cudaGetDevice(&device) == cudaSuccess, \"cudaGetDevice failed\");\n int sm_major = 0;\n int sm_minor = 0;\n FLASHINFER_CHECK(\n cudaDeviceGetAttribute(&sm_major, cudaDevAttrComputeCapabilityMajor, device) == cudaSuccess,\n \"cudaDeviceGetAttribute(ComputeCapabilityMajor) failed\");\n FLASHINFER_CHECK(\n cudaDeviceGetAttribute(&sm_minor, cudaDevAttrComputeCapabilityMinor, device) == cudaSuccess,\n \"cudaDeviceGetAttribute(ComputeCapabilityMinor) failed\");\n return sm_major * 10 + sm_minor;\n}\n\ninline int getMultiProcessorCount() {\n int device{-1};\n FLASHINFER_CHECK(cudaGetDevice(&device) == cudaSuccess, \"cudaGetDevice failed\");\n int count = 0;\n FLASHINFER_CHECK(\n cudaDeviceGetAttribute(&count, cudaDevAttrMultiProcessorCount, device) == cudaSuccess,\n \"cudaDeviceGetAttribute(MultiProcessorCount) failed\");\n return count;\n}\n\n} // namespace tensorrt_llm::common\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\n### Key Findings\n\nWe observed that the Triton implementation outperforms the FlashInfer CUTLASS fused MoE backend on Hopper for BF16 data types (#3521), and thus we started investigating kernel optimization opportunities related to the associated kernels. Here are some key findings regarding the helper memory-bound kernels:\n* Lack of vectorization: In kernels such as `expandInputRowsKernel` and `doActivationKernel`, vectorization is not actually enabled. The generated SASS shows occurrences of four contiguous `LDG.E` instructions rather than a single `LDG.E.128`.\n* Inactive warp: The `doActivationKernel` is currently hardcoded to use 256 threads per row. For workloads with small intermediate sizes, this can be excessive and can result in inactive warps and suboptimal occupancy.\n\n### Changes Made\n\nThis PR improves the performance of the CUTLASS fused MoE input-expansion and activation kernels.\n * Explicitly vectorize global/store in `expandInputRowsKernel` and `doActivationKernel`.\n * This did not work on `finalizeMoeRoutingKernel` as it was observed to increase register usage and did not improve perf.\n * Select the activation kernel block size based on the work required per row, which reduces inactive warps and improves occupancy for smaller intermediate dimensions (e.g., 768 for `Qwen/Qwen3-30B-A3B`). Also, cap the grid size 8~32 blocks (which was constantly 8) per SM based on block size. This limits unnecessary warp-scheduling pressure.\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n#3521\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## ⚡ Performance\n\n### SASS verification (SM100, CUDA 13.2)\n\n| row-data access | before (main) | after (this PR) |\n|---|---|---|\n| expandInputRows (bf16→bf16), per 16B copy | 4× `LDG.E` + 4× `STG.E` | 1× `LDG.E.128` + 1× `STG.E.128` |\n| doActivation (bf16, Swiglu), per 16B of fc1/linear/bias | 4× `LDG.E` each | 1× `LDG.E.128` each |\n| doActivation (fp8 out, Swiglu), per 32B gemm vector | 8× `LDG.E` | 2× `LDG.E.128` |\n| doActivation (nvfp4 out, Swiglu), fp4 output + SF | unchanged (`STG.E` packed + `STG.E.U8`) | unchanged |\n\n### benchmarks/flashinfer_benchmark.py\n\n#### Setup\n * Single B100 (SM100), clocks locked at 1400 MHz SM / 4000 MHz mem, CUDA 13.2\n * Autotune off so both builds run identical default GEMM tactics\n * Baseline = main @ 2e97a607d\n * Cell = median of per-pair speedups\n\n#### Result\n* Achieved up to 1.08x end-to-end speedup\n* No regression observed\n\n| case | M=1 | M=16 | M=128 | M=512 | M=2048 | M=8192 | M=16384 |\n|---|---|---|---|---|---|---|---|\n| qwen3_tp1 | 1.00x | 0.99x | 1.00x | 0.99x | 1.02x | 1.04x | 1.05x |\n| qwen3_tp2 | 1.01x | 1.00x | 1.01x | 1.01x | 1.04x | 1.05x | 1.05x |\n| qwen3_tp4 | 1.00x | 1.00x | 1.01x | 1.01x | 1.04x | 1.04x | 1.05x |\n| qwen3_tp2_fp8 | 1.00x | 1.03x | 1.00x | 1.02x | 1.02x | 1.04x | 1.05x |\n| qwen3_tp4_fp8 | 1.00x | 1.00x | 1.01x | 1.03x | 1.06x | **1.07x** | **1.07x** |\n| dsv3_nvfp4 | 1.01x | 1.03x | 1.04x | 1.06x | **1.08x** | 1.01x | 1.05x |\n| mixtral_tp4 (guard) | 1.00x | 1.00x | 1.00x | 1.00x | 1.01x | 1.02x | 1.01x |\n\n### vLLM end-to-end benchmarking on H200x8\n\n#### Setup\n\n```\nvllm bench throughput --model Qwen/Qwen3-30B-A3B --dataset-name random --moe-backend <backend> -tp <tp>\n```\n\n#### Result\n\n| TP | main | this PR | gain | vs triton backend |\n|---:|---:|---:|---:|---:|\n| 1 | 41.52 | 42.09 | **+1.4%** | +1.5% |\n| 2 | 60.92 | 61.69 | **+1.3%** | −3.3% (was −4.5%) |\n| 4 | 69.36 | 71.51 | **+3.1%** | ~parity |\n| 8 | 74.17 | 75.74 | **+2.1%** | −2.4% |\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc. -->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n* **Performance**\n * Improved Mixture-of-Experts processing with vectorized memory operations for quantized, unquantized, and FP8 data paths.\n * Optimized activation workload distribution, memory access, and scaling across available GPU resources.\n\n* **Bug Fixes**\n * Added validation for memory alignment in MoE inputs, outputs, and biases.\n * Improved rounding utilities to support a broader range of integral values.\n\n* **Tests**\n * Added regression coverage confirming that improperly aligned inputs produce a clear diagnostic.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"e2e\", \"hardware\": \"B100\", \"model\": \"qwen3_tp1\", \"shape\": null, \"batch_size\": 1, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 1.0, \"optimized\": 1.0, \"stated_speedup\": 1.0, \"speedup\": 1.0}, {\"scope\": \"e2e\", \"hardware\": \"B100\", \"model\": \"qwen3_tp1\", \"shape\": null, \"batch_size\": 16, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 0.99, \"optimized\": 0.99, \"stated_speedup\": 0.99, \"speedup\": 1.0}, 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\"stated_speedup\": 1.01, \"speedup\": 1.0}, {\"scope\": \"e2e\", \"hardware\": \"B100\", \"model\": \"mixtral_tp4 (guard)\", \"shape\": null, \"batch_size\": 8192, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 1.02, \"optimized\": 1.02, \"stated_speedup\": 1.02, \"speedup\": 1.0}, {\"scope\": \"e2e\", \"hardware\": \"B100\", \"model\": \"mixtral_tp4 (guard)\", \"shape\": null, \"batch_size\": 16384, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": 1.01, \"optimized\": 1.01, \"stated_speedup\": 1.01, \"speedup\": 1.0}, {\"scope\": \"e2e\", \"hardware\": \"H200\", \"model\": \"Qwen/Qwen3-30B-A3B\", \"shape\": null, \"batch_size\": null, \"metric\": \"throughput\", \"unit\": \"tok/s\", \"higher_is_better\": true, \"baseline\": 41.52, \"optimized\": 42.09, \"stated_speedup\": 1.014, \"speedup\": 1.0137}, {\"scope\": \"e2e\", \"hardware\": \"H200\", \"model\": \"Qwen/Qwen3-30B-A3B\", \"shape\": null, \"batch_size\": null, \"metric\": \"throughput\", \"unit\": \"tok/s\", \"higher_is_better\": true, \"baseline\": 60.92, \"optimized\": 61.69, \"stated_speedup\": 1.013, \"speedup\": 1.0126}, {\"scope\": \"e2e\", \"hardware\": \"H200\", \"model\": \"Qwen/Qwen3-30B-A3B\", \"shape\": null, \"batch_size\": null, \"metric\": \"throughput\", \"unit\": \"tok/s\", \"higher_is_better\": true, \"baseline\": 69.36, \"optimized\": 71.51, \"stated_speedup\": 1.031, \"speedup\": 1.031}, {\"scope\": \"e2e\", \"hardware\": \"H200\", \"model\": \"Qwen/Qwen3-30B-A3B\", \"shape\": null, \"batch_size\": null, \"metric\": \"throughput\", \"unit\": \"tok/s\", \"higher_is_better\": true, \"baseline\": 74.17, \"optimized\": 75.74, \"stated_speedup\": 1.021, \"speedup\": 1.0212}]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"number","value":1,"string":"1"}}},{"rowIdx":1091,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"f527314b25b9701a4d23ba0bf89e225be62780a0"},"date":{"kind":"string","value":"2026-08-11T01:05:12-04:00"},"pr_number":{"kind":"number","value":4416,"string":"4,416"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/4416"},"title":{"kind":"string","value":"perf(norm): speed up fused add RMSNorm FP4 quantization (#4416)"},"message":{"kind":"string","value":"perf(norm): speed up fused add RMSNorm FP4 quantization (#4416)\n\n<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\n This PR improves the fused add + RMSNorm + FP4 quantization kernel by:\n\n - Deriving row parallelism from the number of FP4 scale-factor blocks.\n- Using vectorized shared-memory loads and packed BF16/FP16 operations\nfor the block-size-16 single-CTA path.\n\n## Benchmark\n\n BF16, block size 16, E4M3 scales, swizzled scale layout, CUDA Graph.\n\n Shapes:\n\n - M: 1–1024, powers of two\n - H: 1024–7168, step 1024\n - 77 shapes per GPU\n\nThe unfused baseline includes both the Inductor-compiled add + RMSNorm\nand the CUDA FP4 conversion.\n\n## 🔍 Related Issues\n\nvs. unfused\n<img width=\"1740\" height=\"675\"\nalt=\"fp4-full-current-vs-unfused-20260808\"\nsrc=\"https://github.com/user-attachments/assets/bb6b68c3-4ba9-42f5-8b8c-9031661fd505\"\n/>\n\n\nvs. main change\n<img width=\"1740\" height=\"675\" alt=\"fp4-full-current-vs-main-20260808\"\nsrc=\"https://github.com/user-attachments/assets/4d005223-64ef-4883-8faa-7be89fe2cc75\"\n/>\n\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [ ] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [ ] I have installed the hooks with `pre-commit install`.\n- [ ] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the\npre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [ ] Tests have been added or updated as needed.\n- [ ] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc.\n-->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n## Performance\n* Improved NVFP4 RMSNorm quantization efficiency through faster packed\ndata processing.\n* Reduced unnecessary shared-memory conversions for improved execution\nspeed.\n\n## Compatibility\n* Improved support for varying block sizes and workload dimensions.\n* Enhanced handling of FP16 and BF16 input data.\n* Added support for offline launch-configuration selection.\n\n## Reliability\n* Improved resource sizing for threads, clusters, and shared memory.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->"},"path":{"kind":"string","value":"flashinfer/cute_dsl/add_rmsnorm_fp4quant.py"},"language":{"kind":"string","value":"cute_dsl"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"\"\"\"\nCopyright (c) 2025 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nFused Add + RMSNorm + FP4 Quantization using CuTe-DSL\n======================================================\n\nHigh-performance fused kernel for element-wise addition followed by RMS normalization\nand FP4 quantization. Supports both NVFP4 (block_size=16, E4M3 scales) and MXFP4\n(block_size=32, UE8M0 scales) formats.\n\nOperation:\n 1. residual = residual + input (in-place update)\n 2. output = (residual / sqrt(mean(residual²) + eps)) * weight\n 3. quantize output to FP4\n\nThe residual tensor is modified in-place to contain the fused value (input + residual).\n\n\"\"\"\n\nimport functools\nfrom typing import Callable, Tuple, Union\n\nimport cutlass\nimport cutlass.cute as cute\nimport torch\nfrom cutlass import Float32, Int32, Int64, Uint32, Uint64, Uint8\nfrom cutlass.cutlass_dsl import T, dsl_user_op\nfrom cutlass._mlir.dialects import llvm\n\nfrom .utils import require_cute_dsl_arch as _require_cute_dsl_arch_for\n\nfrom ..api_logging import flashinfer_api\nfrom ..trace.templates.norm import add_rmsnorm_fp4quant_trace_dispatch\nfrom ..utils import device_support_pdl\nfrom .fp4_common import (\n # Constants\n FLOAT4_E2M1_MAX,\n FLOAT8_E4M3_MAX,\n COPY_BITS,\n # Architecture detection\n get_sm_version,\n # PTX intrinsics - basic ops\n st_global_u64,\n get_ptr_as_int64,\n rcp_approx_ftz,\n fmin_f32,\n fmax_f32,\n # Half2 SIMD intrinsics\n hmax2,\n hmax_to_f32,\n # BFloat2 SIMD intrinsics\n bfloat2_hmax2,\n bfloat2_hmax_to_f32,\n # FP8 and FP4 conversion\n cvt_f32x2_to_half2,\n cvt_f32_to_e4m3,\n fp8_e4m3_to_f32_and_rcp,\n cvt_f32_to_ue8m0,\n ue8m0_to_output_scale,\n # Reduction utilities\n row_reduce,\n # Predicate utility\n predicate_k,\n # Helper functions for SF block processing\n load_8_half2,\n half2_mul_8,\n bfloat2_mul_8,\n half2_max_abs_8,\n bfloat2_max_abs_8,\n half2_to_float16,\n bfloat2_to_float16,\n quantize_and_pack_16,\n # Helper functions for Float32 shared memory processing\n load_f32_16_from_smem,\n compute_y_and_max_abs_f32,\n)\n\n\n# =============================================================================\n# Helpers for optional normed (bf16/fp16) output\n# =============================================================================\n\n\n@dsl_user_op\ndef cvt_f32x2_to_bfloat2(a: Float32, b: Float32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Pack two float32 values into a bfloat2 (uint32 containing two bf16 values).\n\n Uses cvt.rn.bf16.f32 for each value, then packs into a single uint32.\n Mirrors cvt_f32x2_to_half2 in fp4_common.py.\n \"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [\n Float32(a).ir_value(loc=loc, ip=ip),\n Float32(b).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b16 h0, h1;\n cvt.rn.bf16.f32 h0, $1;\n cvt.rn.bf16.f32 h1, $2;\n mov.b32 $0, {h0, h1};\n }\n \"\"\",\n \"=r,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@cute.jit\ndef _store_y_norm_16(\n mN: cute.Tensor,\n y_f32: cute.Tensor,\n row_offset: Int32,\n col_offset: Int32,\n H: int,\n is_fp16: bool,\n):\n \"\"\"Store 16 normalized float32 values as fp16/bf16 to global memory.\n\n mN is a flat 1D tensor viewed as row-major (M, H). Uses 4x 64-bit stores\n (each packing 4 16-bit elements).\n \"\"\"\n for j in cutlass.range_constexpr(4):\n if cutlass.const_expr(is_fp16):\n lo = cvt_f32x2_to_half2(y_f32[4 * j], y_f32[4 * j + 1])\n hi = cvt_f32x2_to_half2(y_f32[4 * j + 2], y_f32[4 * j + 3])\n else:\n lo = cvt_f32x2_to_bfloat2(y_f32[4 * j], y_f32[4 * j + 1])\n hi = cvt_f32x2_to_bfloat2(y_f32[4 * j + 2], y_f32[4 * j + 3])\n packed64 = (Uint64(hi) << Uint64(32)) | Uint64(lo)\n ptr = get_ptr_as_int64(mN, row_offset * H + col_offset + Int32(4 * j))\n st_global_u64(ptr, packed64)\n\n\n# =============================================================================\n# CuTe-DSL Kernel Class\n# =============================================================================\n\n\nclass AddRMSNormFP4QuantKernel:\n \"\"\"\n Fused Add + RMSNorm + FP4 Quantization Kernel.\n\n Computes:\n 1. residual = input + residual (in-place update)\n 2. y = RMSNorm(residual) * weight\n 3. quantize y to FP4\n\n The residual tensor is modified in-place.\n Supports both NVFP4 (block_size=16) and MXFP4 (block_size=32) formats.\n \"\"\"\n\n def __init__(\n self,\n dtype: cutlass.Numeric,\n H: int,\n block_size: int,\n output_swizzled: bool,\n is_fp16: bool,\n sm_version: int | None = None,\n scale_format: str | None = None,\n output_both_sf_layouts: bool = False,\n output_norm: bool = False,\n ):\n self.dtype = dtype\n self.H = H\n self.block_size = block_size\n self.output_swizzled = output_swizzled\n self.is_fp16 = is_fp16\n self.sm_version = sm_version if sm_version is not None else get_sm_version()\n self.output_both_sf_layouts = output_both_sf_layouts\n self.output_norm = output_norm\n\n if scale_format is None:\n self.scale_format = \"ue8m0\" if block_size == 32 else \"e4m3\"\n else:\n self.scale_format = scale_format\n\n assert block_size in (16, 32), f\"block_size must be 16 or 32, got {block_size}\"\n assert self.scale_format in (\"e4m3\", \"ue8m0\"), (\n \"scale_format must be 'e4m3' or 'ue8m0'\"\n )\n\n self.cluster_n = self._compute_cluster_n(H, dtype, self.sm_version)\n self.H_per_cta = H // self.cluster_n\n\n self.threads_per_row = self._compute_threads_per_row(self.H_per_cta)\n self.num_threads = self._compute_num_threads(self.H_per_cta)\n self.rows_per_block = self.num_threads // self.threads_per_row\n self.warps_per_row = max(self.threads_per_row // 32, 1)\n\n elem_bytes = dtype.width // 8\n self.vec_size = COPY_BITS // 8 // elem_bytes\n self.num_vec_blocks = max(\n 1,\n (self.H_per_cta // self.vec_size + self.threads_per_row - 1)\n // self.threads_per_row,\n )\n self.cols_per_tile = self.vec_size * self.num_vec_blocks * self.threads_per_row\n\n self.num_sf_blocks_per_row = H // block_size\n\n # Need swizzle params if output_swizzled or output_both_sf_layouts\n if output_swizzled or output_both_sf_layouts:\n num_col_vecs = H // block_size\n self.num_k_tiles = (num_col_vecs + 3) // 4\n self.k_tile_stride = 512\n\n @staticmethod\n def _compute_cluster_n(H: int, dtype: cutlass.Numeric, sm_version: int) -> int:\n \"\"\"Compute optimal cluster size based on H and device shared memory.\n\n Dynamically determines the minimum cluster_n that fits within the\n device's shared memory limit, making it compatible with different\n GPU architectures (e.g., SM100 with 228KB vs SM120 with 128KB).\n \"\"\"\n if sm_version < 90:\n return 1\n\n props = torch.cuda.get_device_properties(torch.cuda.current_device())\n max_smem_bytes = props.shared_memory_per_block_optin\n elem_size = dtype.width // 8\n\n for cluster_n in [1, 2, 4, 8, 16]:\n if H % cluster_n != 0:\n continue\n smem_needed = AddRMSNormFP4QuantKernel._estimate_smem_bytes(\n H, cluster_n, elem_size\n )\n if smem_needed <= max_smem_bytes:\n return cluster_n\n\n return 16\n\n @staticmethod\n def _compute_threads_per_row(H_per_cta: int) -> int:\n \"\"\"Compute optimal threads per row.\"\"\"\n if H_per_cta <= 64:\n return 8\n elif H_per_cta <= 128:\n return 16\n elif H_per_cta <= 3072:\n return 32\n elif H_per_cta <= 6144:\n return 64\n elif H_per_cta <= 16384:\n return 128\n else:\n return 256\n\n @staticmethod\n def _compute_num_threads(H_per_cta: int) -> int:\n \"\"\"Compute total threads per block.\"\"\"\n return 128 if H_per_cta <= 16384 else 256\n\n @staticmethod\n def _estimate_smem_bytes(H: int, cluster_n: int, elem_size: int) -> int:\n \"\"\"Estimate shared memory bytes needed for given configuration.\n\n This is used to dynamically determine cluster_n based on device\n shared memory limits.\n \"\"\"\n H_per_cta = H // cluster_n\n threads_per_row = AddRMSNormFP4QuantKernel._compute_threads_per_row(H_per_cta)\n num_threads = AddRMSNormFP4QuantKernel._compute_num_threads(H_per_cta)\n rows_per_block = num_threads // threads_per_row\n warps_per_row = max(threads_per_row // 32, 1)\n\n vec_size = COPY_BITS // 8 // elem_size\n num_vec_blocks = max(\n 1, (H_per_cta // vec_size + threads_per_row - 1) // threads_per_row\n )\n cols_per_tile = vec_size * num_vec_blocks * threads_per_row\n\n tile_bytes = rows_per_block * cols_per_tile * elem_size\n\n if cluster_n == 1:\n # 4 tiles: sX, sR, sW, sH + reduction buffer\n return 4 * tile_bytes + rows_per_block * warps_per_row * 4\n else:\n # 2 tiles: sX, sR + larger reduction buffer + mbarrier\n return 2 * tile_bytes + rows_per_block * warps_per_row * cluster_n * 4 + 8\n\n @staticmethod\n def _make_tv_layout(\n threads_per_row: int,\n rows_per_block: int,\n vec_size: int,\n num_vec_blocks: int,\n ) -> tuple:\n \"\"\"Create Thread-Value layout for coalesced vectorized memory access.\"\"\"\n shape = (\n (threads_per_row, rows_per_block),\n (vec_size, num_vec_blocks),\n )\n stride = (\n (vec_size * rows_per_block, 1),\n (rows_per_block, rows_per_block * vec_size * threads_per_row),\n )\n return shape, stride\n\n def _smem_size_in_bytes(self) -> int:\n \"\"\"Calculate shared memory requirement.\"\"\"\n elem_size = self.dtype.width // 8\n x_tile_bytes = self.rows_per_block * self.cols_per_tile * elem_size\n r_tile_bytes = self.rows_per_block * self.cols_per_tile * elem_size\n\n if self.cluster_n == 1:\n w_tile_bytes = self.rows_per_block * self.cols_per_tile * elem_size\n h_tile_bytes = self.rows_per_block * self.cols_per_tile * elem_size\n reduction_bytes = self.rows_per_block * self.warps_per_row * 4\n else:\n w_tile_bytes = 0\n h_tile_bytes = 0\n reduction_bytes = (\n self.rows_per_block * self.warps_per_row * self.cluster_n * 4\n )\n\n mbar_bytes = 8 if self.cluster_n > 1 else 0\n\n return (\n x_tile_bytes\n + r_tile_bytes\n + w_tile_bytes\n + h_tile_bytes\n + reduction_bytes\n + mbar_bytes\n )\n\n @cute.jit\n def __call__(\n self,\n mX: cute.Tensor,\n mR: cute.Tensor,\n mW: cute.Tensor,\n mY: cute.Tensor,\n mS: cute.Tensor,\n mS_unswizzled: cute.Tensor,\n mYNorm: cute.Tensor,\n mGlobalScale: cute.Tensor,\n M: Int32,\n eps: Float32,\n enable_pdl: cutlass.Constexpr[bool],\n stream,\n ):\n \"\"\"Host function to launch the kernel.\n\n Takes tensors directly via TVM-FFI.\n - mX: Input tensor, shape (M, H), row-major (read-only)\n - mR: Residual tensor, shape (M, H), row-major (modified in-place to input + residual)\n - mW: Weight tensor, shape (H,)\n - mY: Output FP4 tensor, shape (M, H // 2), row-major (packed)\n - mS: Scale factor tensor, shape depends on swizzle mode\n - mS_unswizzled: Unswizzled scale factor tensor (used when output_both_sf_layouts=True)\n - mYNorm: Optional normed output tensor, flat 1D view of (M, H), same dtype as\n input (only written when output_norm=True; pass any dummy tensor otherwise)\n - mGlobalScale: Global scale tensor, shape (1,), float32\n \"\"\"\n\n tv_shape, tv_stride = self._make_tv_layout(\n self.threads_per_row,\n self.rows_per_block,\n self.vec_size,\n self.num_vec_blocks,\n )\n tv_layout = cute.make_layout(tv_shape, stride=tv_stride)\n tiler_mn = (self.rows_per_block, self.cols_per_tile)\n\n self.kernel(\n mX,\n mR,\n mW,\n mY,\n mS,\n mS_unswizzled,\n mYNorm,\n mGlobalScale,\n M,\n eps,\n enable_pdl,\n tv_layout,\n tiler_mn,\n ).launch(\n grid=[cute.ceil_div(M, self.rows_per_block), self.cluster_n, 1],\n block=[self.num_threads, 1, 1],\n cluster=[1, self.cluster_n, 1]\n if cutlass.const_expr(self.cluster_n > 1)\n else None,\n smem=self._smem_size_in_bytes(),\n stream=stream,\n use_pdl=enable_pdl,\n )\n\n @cute.kernel\n def kernel(\n self,\n mX: cute.Tensor,\n mR: cute.Tensor,\n mW: cute.Tensor,\n mY: cute.Tensor,\n mS: cute.Tensor,\n mS_unswizzled: cute.Tensor,\n mYNorm: cute.Tensor,\n mGlobalScale: cute.Tensor,\n M: Int32,\n eps: Float32,\n enable_pdl: cutlass.Constexpr[bool],\n tv_layout: cute.Layout,\n tiler_mn: cute.Shape,\n ):\n \"\"\"Device kernel with cluster sync and Half2 SIMD.\n\n Performs:\n 1. h = input + residual (writes h back to mR in-place)\n 2. y = h * rstd * w / global_scale = rmsnorm(h, w) / global_scale\n 3. quantizes y to FP4\n\n mGlobalScale contains the global scale value. The kernel reads it and\n computes 1/global_scale, which is multiplied with rstd to apply:\n y = h * rstd * w / global_scale = rmsnorm(h, w) / global_scale\n \"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n\n if enable_pdl:\n cute.arch.griddepcontrol_wait()\n bidx, _, _ = cute.arch.block_idx()\n\n H = self.H\n block_size = self.block_size\n num_sf_blocks_per_row = self.num_sf_blocks_per_row\n is_fp16 = self.is_fp16\n cluster_n = self.cluster_n\n\n if cutlass.const_expr(cluster_n > 1):\n cluster_y = cute.arch.block_idx()[1]\n else:\n cluster_y = cutlass.const_expr(0)\n\n threads_per_row = tv_layout.shape[0][0]\n warps_per_row = max(threads_per_row // 32, 1)\n rows_per_block = tiler_mn[0]\n\n lane_in_row = tidx % threads_per_row\n row_in_block = tidx // threads_per_row\n\n fp4_max_rcp = rcp_approx_ftz(Float32(FLOAT4_E2M1_MAX))\n\n # Allocate shared memory\n smem = cutlass.utils.SmemAllocator()\n\n sX = smem.allocate_tensor(\n mX.element_type,\n cute.make_ordered_layout(tiler_mn, order=(1, 0)),\n byte_alignment=16,\n )\n\n sR = smem.allocate_tensor(\n mR.element_type,\n cute.make_ordered_layout(tiler_mn, order=(1, 0)),\n byte_alignment=16,\n )\n\n if cutlass.const_expr(cluster_n == 1):\n sW = smem.allocate_tensor(\n mW.element_type,\n cute.make_ordered_layout(tiler_mn, order=(1, 0)),\n byte_alignment=16,\n )\n sH = smem.allocate_tensor(\n mX.element_type,\n cute.make_ordered_layout(tiler_mn, order=(1, 0)),\n byte_alignment=16,\n )\n\n if cutlass.const_expr(cluster_n == 1):\n reduction_buffer = smem.allocate_tensor(\n Float32,\n cute.make_layout((rows_per_block, warps_per_row)),\n byte_alignment=4,\n )\n mbar_ptr = None\n else:\n reduction_buffer = smem.allocate_tensor(\n Float32,\n cute.make_layout((rows_per_block, (warps_per_row, cluster_n))),\n byte_alignment=4,\n )\n mbar_ptr = smem.allocate_array(Int64, num_elems=1)\n\n # Initialize cluster\n if cutlass.const_expr(cluster_n > 1):\n if tidx == 0:\n cute.arch.mbarrier_init(mbar_ptr, 1)\n cute.arch.mbarrier_init_fence()\n cute.arch.cluster_arrive_relaxed()\n cute.arch.cluster_wait()\n\n # Create identity tensor\n idX = cute.make_identity_tensor(mX.shape)\n\n gX = cute.local_tile(mX, tiler_mn, (bidx, cluster_y))\n gR = cute.local_tile(mR, tiler_mn, (bidx, cluster_y))\n cX = cute.local_tile(idX, tiler_mn, (bidx, cluster_y))\n\n if cutlass.const_expr(cluster_n == 1):\n mW_expanded_layout = cute.prepend(\n mW.layout, cute.make_layout((tiler_mn[0],), stride=(0,))\n )\n mW_2d = cute.make_tensor(mW.iterator, mW_expanded_layout)\n gW = cute.local_tile(mW_2d, tiler_mn, (0, cluster_y))\n\n # TiledCopy for loads\n copy_atom_load_async = cute.make_copy_atom(\n cute.nvgpu.cpasync.CopyG2SOp(),\n mX.element_type,\n num_bits_per_copy=COPY_BITS,\n )\n\n # TiledCopy for stores (to write h back to residual)\n copy_atom_store = cute.make_copy_atom(\n cute.nvgpu.CopyUniversalOp(),\n mR.element_type,\n num_bits_per_copy=COPY_BITS,\n )\n\n tiled_copy_load = cute.make_tiled_copy(\n copy_atom_load_async, tv_layout, tiler_mn\n )\n tiled_copy_store = cute.make_tiled_copy(copy_atom_store, tv_layout, tiler_mn)\n\n thr_copy_X = tiled_copy_load.get_slice(tidx)\n thr_copy_R = tiled_copy_load.get_slice(tidx)\n thr_copy_R_store = tiled_copy_store.get_slice(tidx)\n\n tXgX = thr_copy_X.partition_S(gX)\n tXsX = thr_copy_X.partition_D(sX)\n tRgR = thr_copy_R.partition_S(gR)\n tRsR = thr_copy_R.partition_D(sR)\n tXcX = thr_copy_X.partition_S(cX)\n\n # Output partition for writing h back to residual (in-place update)\n tRgO = thr_copy_R_store.partition_D(gR)\n\n if cutlass.const_expr(cluster_n == 1):\n thr_copy_W = tiled_copy_load.get_slice(tidx)\n tWgW = thr_copy_W.partition_S(gW)\n tWsW = thr_copy_W.partition_D(sW)\n tHsH = thr_copy_X.partition_D(sH)\n\n tXrX = cute.make_fragment_like(tXgX)\n tRrR = cute.make_fragment_like(tRgR)\n tRrO = cute.make_fragment_like(tRgO) # Register fragment for residual output\n\n # Bounds checking\n tXpX = predicate_k(tXcX, limit=H)\n row_coord = tXcX[(0, 0), 0, 0]\n row_in_bounds = row_coord[0] < M\n\n # Phase 1: Async copy\n if row_in_bounds:\n cute.copy(copy_atom_load_async, tXgX, tXsX, pred=tXpX)\n cute.copy(copy_atom_load_async, tRgR, tRsR, pred=tXpX)\n\n if cutlass.const_expr(cluster_n == 1):\n cute.copy(copy_atom_load_async, tWgW, tWsW, pred=tXpX)\n\n cute.arch.cp_async_commit_group()\n cute.arch.cp_async_wait_group(0)\n\n # Phase 2: h = x + r and sum of squares\n cute.autovec_copy(tXsX, tXrX)\n cute.autovec_copy(tRsR, tRrR)\n\n x_vals = tXrX.load().to(Float32)\n r_vals = tRrR.load().to(Float32)\n\n h_vals = x_vals + r_vals\n h_sq = h_vals * h_vals\n\n # Store h to residual output registers (for in-place update of residual)\n tRrO.store(h_vals.to(self.dtype))\n\n if cutlass.const_expr(cluster_n == 1):\n h_elem = h_vals.to(mX.element_type)\n tHsH.store(h_elem)\n\n sum_sq = row_reduce(\n h_sq,\n cute.ReductionOp.ADD,\n threads_per_row,\n reduction_buffer,\n mbar_ptr,\n cluster_n,\n Float32(0.0),\n )\n\n mean_sq = sum_sq / H\n rstd = cute.math.rsqrt(mean_sq + eps, fastmath=True)\n\n # Read global_scale from device memory (CUDA graph compatible)\n # Note: global_scale is incorporated into the block scale, NOT applied to input\n global_scale_val = mGlobalScale[0]\n\n if cutlass.const_expr(cluster_n > 1):\n cute.arch.cluster_arrive_relaxed()\n cute.arch.cluster_wait()\n else:\n cute.arch.barrier()\n\n # Write h back to residual tensor (in-place update: residual = input + residual)\n if row_in_bounds:\n cute.copy(copy_atom_store, tRrO, tRgO, pred=tXpX)\n\n # In cluster mode, Phase 3 reads from mR across the FULL hidden dimension,\n # including slices written by other CTAs. We must ensure all CTAs' global\n # memory writes are visible before any CTA proceeds to Phase 3.\n if cutlass.const_expr(cluster_n > 1):\n cute.arch.fence_acq_rel_cluster()\n cute.arch.cluster_arrive_relaxed()\n cute.arch.cluster_wait()\n\n actual_row_idx = bidx * rows_per_block + row_in_block\n\n # Phase 3: RMSNorm + Quantize\n if actual_row_idx < M:\n num_sf_per_thread = (\n num_sf_blocks_per_row + threads_per_row - 1\n ) // threads_per_row\n\n for sf_iter in range(num_sf_per_thread):\n sf_idx = lane_in_row + sf_iter * threads_per_row\n\n if sf_idx < num_sf_blocks_per_row:\n block_start = sf_idx * block_size\n\n if cutlass.const_expr(block_size == 16):\n if cutlass.const_expr(cluster_n == 1):\n # Shared memory path - use helper functions\n h_f32 = load_f32_16_from_smem(sH, row_in_block, block_start)\n w_f32 = load_f32_16_from_smem(sW, row_in_block, block_start)\n y_f32, max_abs = compute_y_and_max_abs_f32(\n h_f32, w_f32, rstd\n )\n\n # E4M3: global_scale is incorporated into block scale\n scale_float = global_scale_val * max_abs * fp4_max_rcp\n scale_float = fmin_f32(\n scale_float, Float32(FLOAT8_E4M3_MAX)\n )\n scale_fp8_u32 = cvt_f32_to_e4m3(scale_float)\n scale_fp8 = Uint8(scale_fp8_u32 & Uint32(0xFF))\n inv_scale = (\n fp8_e4m3_to_f32_and_rcp(scale_fp8_u32)\n * global_scale_val\n )\n\n if cutlass.const_expr(self.output_both_sf_layouts):\n inner_k_idx = sf_idx % Int32(4)\n inner_m_idx = (actual_row_idx % Int32(128)) // Int32(32)\n outer_m_idx = actual_row_idx % Int32(32)\n k_tile_idx = sf_idx // Int32(4)\n m_tile_idx = actual_row_idx // Int32(128)\n m_tile_stride = self.num_k_tiles * self.k_tile_stride\n swizzled_offset = (\n m_tile_idx * m_tile_stride\n + k_tile_idx * self.k_tile_stride\n + outer_m_idx * Int32(16)\n + inner_m_idx * Int32(4)\n + inner_k_idx\n )\n mS[swizzled_offset] = scale_fp8\n mS_unswizzled[actual_row_idx, sf_idx] = scale_fp8\n elif cutlass.const_expr(self.output_swizzled):\n inner_k_idx = sf_idx % Int32(4)\n inner_m_idx = (actual_row_idx % Int32(128)) // Int32(32)\n outer_m_idx = actual_row_idx % Int32(32)\n k_tile_idx = sf_idx // Int32(4)\n m_tile_idx = actual_row_idx // Int32(128)\n m_tile_stride = self.num_k_tiles * self.k_tile_stride\n swizzled_offset = (\n m_tile_idx * m_tile_stride\n + k_tile_idx * self.k_tile_stride\n + outer_m_idx * Int32(16)\n + inner_m_idx * Int32(4)\n + inner_k_idx\n )\n mS[swizzled_offset] = scale_fp8\n else:\n mS[actual_row_idx, sf_idx] = scale_fp8\n\n packed64 = quantize_and_pack_16(y_f32, inv_scale)\n out_offset = block_start // 2\n out_ptr = get_ptr_as_int64(\n mY, actual_row_idx * (H // 2) + out_offset\n )\n st_global_u64(out_ptr, packed64)\n\n if cutlass.const_expr(self.output_norm):\n _store_y_norm_16(\n mYNorm,\n y_f32,\n actual_row_idx,\n block_start,\n H,\n is_fp16,\n )\n\n else:\n # Global memory path (cluster mode) - use helper functions\n # mR contains h = x + r, so load from mR\n h_h2, w_h2 = load_8_half2(\n mR, mW, actual_row_idx, block_start, H\n )\n\n if cutlass.const_expr(is_fp16):\n hw_h2 = half2_mul_8(h_h2, w_h2)\n max_hw = half2_max_abs_8(hw_h2)\n max_xw = hmax_to_f32(max_hw)\n y_f32 = half2_to_float16(hw_h2, rstd)\n else:\n hw_h2 = bfloat2_mul_8(h_h2, w_h2)\n max_hw = bfloat2_max_abs_8(hw_h2)\n max_xw = bfloat2_hmax_to_f32(max_hw)\n y_f32 = bfloat2_to_float16(hw_h2, rstd)\n\n max_abs = max_xw * rstd\n\n # E4M3: global_scale is incorporated into block scale\n scale_float = global_scale_val * max_abs * fp4_max_rcp\n scale_float = fmin_f32(\n scale_float, Float32(FLOAT8_E4M3_MAX)\n )\n scale_fp8_u32 = cvt_f32_to_e4m3(scale_float)\n scale_fp8 = Uint8(scale_fp8_u32 & Uint32(0xFF))\n inv_scale = (\n fp8_e4m3_to_f32_and_rcp(scale_fp8_u32)\n * global_scale_val\n )\n\n if cutlass.const_expr(self.output_both_sf_layouts):\n inner_k_idx = sf_idx % Int32(4)\n inner_m_idx = (actual_row_idx % Int32(128)) // Int32(32)\n outer_m_idx = actual_row_idx % Int32(32)\n k_tile_idx = sf_idx // Int32(4)\n m_tile_idx = actual_row_idx // Int32(128)\n m_tile_stride = self.num_k_tiles * self.k_tile_stride\n swizzled_offset = (\n m_tile_idx * m_tile_stride\n + k_tile_idx * self.k_tile_stride\n + outer_m_idx * Int32(16)\n + inner_m_idx * Int32(4)\n + inner_k_idx\n )\n mS[swizzled_offset] = scale_fp8\n mS_unswizzled[actual_row_idx, sf_idx] = scale_fp8\n elif cutlass.const_expr(self.output_swizzled):\n inner_k_idx = sf_idx % Int32(4)\n inner_m_idx = (actual_row_idx % Int32(128)) // Int32(32)\n outer_m_idx = actual_row_idx % Int32(32)\n k_tile_idx = sf_idx // Int32(4)\n m_tile_idx = actual_row_idx // Int32(128)\n m_tile_stride = self.num_k_tiles * self.k_tile_stride\n swizzled_offset = (\n m_tile_idx * m_tile_stride\n + k_tile_idx * self.k_tile_stride\n + outer_m_idx * Int32(16)\n + inner_m_idx * Int32(4)\n + inner_k_idx\n )\n mS[swizzled_offset] = scale_fp8\n else:\n mS[actual_row_idx, sf_idx] = scale_fp8\n\n packed64 = quantize_and_pack_16(y_f32, inv_scale)\n out_offset = block_start // 2\n out_ptr = get_ptr_as_int64(\n mY, actual_row_idx * (H // 2) + out_offset\n )\n st_global_u64(out_ptr, packed64)\n\n if cutlass.const_expr(self.output_norm):\n _store_y_norm_16(\n mYNorm,\n y_f32,\n actual_row_idx,\n block_start,\n H,\n is_fp16,\n )\n\n else:\n # block_size == 32 (MXFP4) - process in two chunks of 16\n if cutlass.const_expr(cluster_n == 1):\n # Shared memory path - use helper functions\n # Load and compute first 16 elements\n h_f32_c0 = load_f32_16_from_smem(\n sH, row_in_block, block_start\n )\n w_f32_c0 = load_f32_16_from_smem(\n sW, row_in_block, block_start\n )\n y_f32_c0, max_abs_c0 = compute_y_and_max_abs_f32(\n h_f32_c0, w_f32_c0, rstd\n )\n\n # Load and compute second 16 elements\n h_f32_c1 = load_f32_16_from_smem(\n sH, row_in_block, block_start + Int32(16)\n )\n w_f32_c1 = load_f32_16_from_smem(\n sW, row_in_block, block_start + Int32(16)\n )\n y_f32_c1, max_abs_c1 = compute_y_and_max_abs_f32(\n h_f32_c1, w_f32_c1, rstd\n )\n\n # Combine max_abs from both chunks\n max_abs = fmax_f32(max_abs_c0, max_abs_c1)\n\n # Compute scale factor (E4M3 or UE8M0)\n if cutlass.const_expr(self.scale_format == \"ue8m0\"):\n scale_float = max_abs * fp4_max_rcp\n scale_ue8m0 = cvt_f32_to_ue8m0(scale_float)\n scale_u8 = Uint8(scale_ue8m0 & Uint32(0xFF))\n inv_scale = ue8m0_to_output_scale(scale_ue8m0)\n else:\n scale_float = global_scale_val * max_abs * fp4_max_rcp\n scale_float = fmin_f32(\n scale_float, Float32(FLOAT8_E4M3_MAX)\n )\n scale_fp8_u32 = cvt_f32_to_e4m3(scale_float)\n scale_u8 = Uint8(scale_fp8_u32 & Uint32(0xFF))\n inv_scale = (\n fp8_e4m3_to_f32_and_rcp(scale_fp8_u32)\n * global_scale_val\n )\n\n if cutlass.const_expr(self.output_both_sf_layouts):\n inner_k_idx = sf_idx % Int32(4)\n inner_m_idx = (actual_row_idx % Int32(128)) // Int32(32)\n outer_m_idx = actual_row_idx % Int32(32)\n k_tile_idx = sf_idx // Int32(4)\n m_tile_idx = actual_row_idx // Int32(128)\n m_tile_stride = self.num_k_tiles * self.k_tile_stride\n swizzled_offset = (\n m_tile_idx * m_tile_stride\n + k_tile_idx * self.k_tile_stride\n + outer_m_idx * Int32(16)\n + inner_m_idx * Int32(4)\n + inner_k_idx\n )\n mS[swizzled_offset] = scale_u8\n mS_unswizzled[actual_row_idx, sf_idx] = scale_u8\n elif cutlass.const_expr(self.output_swizzled):\n inner_k_idx = sf_idx % Int32(4)\n inner_m_idx = (actual_row_idx % Int32(128)) // Int32(32)\n outer_m_idx = actual_row_idx % Int32(32)\n k_tile_idx = sf_idx // Int32(4)\n m_tile_idx = actual_row_idx // Int32(128)\n m_tile_stride = self.num_k_tiles * self.k_tile_stride\n swizzled_offset = (\n m_tile_idx * m_tile_stride\n + k_tile_idx * self.k_tile_stride\n + outer_m_idx * Int32(16)\n + inner_m_idx * Int32(4)\n + inner_k_idx\n )\n mS[swizzled_offset] = scale_u8\n else:\n mS[actual_row_idx, sf_idx] = scale_u8\n\n # Quantize and store both chunks\n packed64_c0 = quantize_and_pack_16(y_f32_c0, inv_scale)\n packed64_c1 = quantize_and_pack_16(y_f32_c1, inv_scale)\n\n fp4_offset = actual_row_idx * (H // 2) + sf_idx * (\n block_size // 2\n )\n fp4_ptr_0 = get_ptr_as_int64(mY, fp4_offset)\n fp4_ptr_1 = get_ptr_as_int64(mY, fp4_offset + Int32(8))\n st_global_u64(fp4_ptr_0, packed64_c0)\n st_global_u64(fp4_ptr_1, packed64_c1)\n\n if cutlass.const_expr(self.output_norm):\n _store_y_norm_16(\n mYNorm,\n y_f32_c0,\n actual_row_idx,\n block_start,\n H,\n is_fp16,\n )\n _store_y_norm_16(\n mYNorm,\n y_f32_c1,\n actual_row_idx,\n block_start + Int32(16),\n H,\n is_fp16,\n )\n\n else:\n # Global memory path (cluster mode) - use helper functions\n # mR contains h = x + r, load in two chunks\n h_h2_c0, w_h2_c0 = load_8_half2(\n mR, mW, actual_row_idx, block_start, H\n )\n h_h2_c1, w_h2_c1 = load_8_half2(\n mR, mW, actual_row_idx, block_start + Int32(16), H\n )\n\n if cutlass.const_expr(is_fp16):\n hw_h2_c0 = half2_mul_8(h_h2_c0, w_h2_c0)\n hw_h2_c1 = half2_mul_8(h_h2_c1, w_h2_c1)\n max_c0_h2 = half2_max_abs_8(hw_h2_c0)\n max_c1_h2 = half2_max_abs_8(hw_h2_c1)\n max_hw = hmax2(max_c0_h2, max_c1_h2)\n max_xw = hmax_to_f32(max_hw)\n y_f32_c0 = half2_to_float16(hw_h2_c0, rstd)\n y_f32_c1 = half2_to_float16(hw_h2_c1, rstd)\n else:\n hw_h2_c0 = bfloat2_mul_8(h_h2_c0, w_h2_c0)\n hw_h2_c1 = bfloat2_mul_8(h_h2_c1, w_h2_c1)\n max_c0_h2 = bfloat2_max_abs_8(hw_h2_c0)\n max_c1_h2 = bfloat2_max_abs_8(hw_h2_c1)\n max_hw = bfloat2_hmax2(max_c0_h2, max_c1_h2)\n max_xw = bfloat2_hmax_to_f32(max_hw)\n y_f32_c0 = bfloat2_to_float16(hw_h2_c0, rstd)\n y_f32_c1 = bfloat2_to_float16(hw_h2_c1, rstd)\n\n max_abs = max_xw * rstd\n\n # Compute scale factor (E4M3 or UE8M0)\n if cutlass.const_expr(self.scale_format == \"ue8m0\"):\n scale_float = max_abs * fp4_max_rcp\n scale_ue8m0 = cvt_f32_to_ue8m0(scale_float)\n scale_u8 = Uint8(scale_ue8m0 & Uint32(0xFF))\n inv_scale = ue8m0_to_output_scale(scale_ue8m0)\n else:\n scale_float = global_scale_val * max_abs * fp4_max_rcp\n scale_float = fmin_f32(\n scale_float, Float32(FLOAT8_E4M3_MAX)\n )\n scale_fp8_u32 = cvt_f32_to_e4m3(scale_float)\n scale_u8 = Uint8(scale_fp8_u32 & Uint32(0xFF))\n inv_scale = (\n fp8_e4m3_to_f32_and_rcp(scale_fp8_u32)\n * global_scale_val\n )\n\n if cutlass.const_expr(self.output_both_sf_layouts):\n inner_k_idx = sf_idx % Int32(4)\n inner_m_idx = (actual_row_idx % Int32(128)) // Int32(32)\n outer_m_idx = actual_row_idx % Int32(32)\n k_tile_idx = sf_idx // Int32(4)\n m_tile_idx = actual_row_idx // Int32(128)\n m_tile_stride = self.num_k_tiles * self.k_tile_stride\n swizzled_offset = (\n m_tile_idx * m_tile_stride\n + k_tile_idx * self.k_tile_stride\n + outer_m_idx * Int32(16)\n + inner_m_idx * Int32(4)\n + inner_k_idx\n )\n mS[swizzled_offset] = scale_u8\n mS_unswizzled[actual_row_idx, sf_idx] = scale_u8\n elif cutlass.const_expr(self.output_swizzled):\n inner_k_idx = sf_idx % Int32(4)\n inner_m_idx = (actual_row_idx % Int32(128)) // Int32(32)\n outer_m_idx = actual_row_idx % Int32(32)\n k_tile_idx = sf_idx // Int32(4)\n m_tile_idx = actual_row_idx // Int32(128)\n m_tile_stride = self.num_k_tiles * self.k_tile_stride\n swizzled_offset = (\n m_tile_idx * m_tile_stride\n + k_tile_idx * self.k_tile_stride\n + outer_m_idx * Int32(16)\n + inner_m_idx * Int32(4)\n + inner_k_idx\n )\n mS[swizzled_offset] = scale_u8\n else:\n mS[actual_row_idx, sf_idx] = scale_u8\n\n # Quantize and store both chunks\n packed64_c0 = quantize_and_pack_16(y_f32_c0, inv_scale)\n packed64_c1 = quantize_and_pack_16(y_f32_c1, inv_scale)\n\n fp4_offset = actual_row_idx * (H // 2) + sf_idx * (\n block_size // 2\n )\n fp4_ptr_0 = get_ptr_as_int64(mY, fp4_offset)\n fp4_ptr_1 = get_ptr_as_int64(mY, fp4_offset + Int32(8))\n st_global_u64(fp4_ptr_0, packed64_c0)\n st_global_u64(fp4_ptr_1, packed64_c1)\n\n if cutlass.const_expr(self.output_norm):\n _store_y_norm_16(\n mYNorm,\n y_f32_c0,\n actual_row_idx,\n block_start,\n H,\n is_fp16,\n )\n _store_y_norm_16(\n mYNorm,\n y_f32_c1,\n actual_row_idx,\n block_start + Int32(16),\n H,\n is_fp16,\n )\n\n if enable_pdl:\n cute.arch.griddepcontrol_launch_dependents()\n\n\n# =============================================================================\n# PyTorch API Functions\n# =============================================================================\n\n\n@functools.cache\ndef _get_compiled_kernel(\n hidden_size: int,\n block_size: int,\n is_fp16: bool,\n sm_version: int,\n scale_format: str,\n is_sf_swizzled_layout: bool,\n output_both_sf_layouts: bool = False,\n enable_pdl: bool = False,\n output_norm: bool = False,\n) -> Callable:\n \"\"\"\n Get a compiled kernel closure that takes torch.Tensor directly.\n\n Uses TVM-FFI for efficient tensor passing without manual pointer construction.\n \"\"\"\n cutlass_dtype = cutlass.Float16 if is_fp16 else cutlass.BFloat16\n\n kernel_obj = AddRMSNormFP4QuantKernel(\n dtype=cutlass_dtype,\n H=hidden_size,\n block_size=block_size,\n output_swizzled=is_sf_swizzled_layout,\n is_fp16=is_fp16,\n sm_version=sm_version,\n scale_format=scale_format,\n output_both_sf_layouts=output_both_sf_layouts,\n output_norm=output_norm,\n )\n\n # Use symbolic size for dynamic M dimension\n sym_m = cute.sym_int()\n\n # Create fake tensors for compilation with TVM-FFI\n # Use stride_order=(1, 0) for row-major layout and assumed_align=128 for async copy\n x_fake = cute.runtime.make_fake_compact_tensor(\n cutlass_dtype, (sym_m, hidden_size), stride_order=(1, 0), assumed_align=128\n )\n r_fake = cute.runtime.make_fake_compact_tensor(\n cutlass_dtype, (sym_m, hidden_size), stride_order=(1, 0), assumed_align=128\n )\n w_fake = cute.runtime.make_fake_compact_tensor(\n cutlass_dtype, (hidden_size,), assumed_align=128\n )\n y_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_m, hidden_size // 2), stride_order=(1, 0), assumed_align=128\n )\n\n # Scale factor tensor layout depends on swizzle mode or output_both_sf_layouts\n if is_sf_swizzled_layout or output_both_sf_layouts:\n # For swizzled mode, use 1D layout - the swizzle pattern is computed in kernel\n # Size is: num_m_tiles * num_k_tiles * 512, which is independent of M\n # Use a separate symbolic variable for this size\n sym_swizzled_size = cute.sym_int()\n s_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_swizzled_size,), assumed_align=128\n )\n else:\n # For non-swizzled mode, use 2D row-major layout\n s_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (sym_m, hidden_size // block_size),\n stride_order=(1, 0),\n assumed_align=128,\n )\n\n # Unswizzled scale factor tensor (always 2D row-major, used when output_both_sf_layouts=True)\n s_unswizzled_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (sym_m, hidden_size // block_size),\n stride_order=(1, 0),\n assumed_align=128,\n )\n\n # Optional normed output tensor (flat 1D view of (M, hidden_size)).\n # Uses an independent symbolic size so a small dummy tensor can be passed\n # when output_norm=False (the kernel never touches it in that case).\n sym_ynorm_size = cute.sym_int()\n ynorm_fake = cute.runtime.make_fake_compact_tensor(\n cutlass_dtype, (sym_ynorm_size,), assumed_align=16\n )\n\n # Create fake stream that uses environment stream at runtime\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n\n # Global scale fake tensor (shape [1], float32)\n global_scale_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32, (1,), assumed_align=4\n )\n\n # Compile with TVM-FFI enabled\n compiled_kernel = cute.compile(\n kernel_obj,\n x_fake,\n r_fake,\n w_fake,\n y_fake,\n s_fake,\n s_unswizzled_fake,\n ynorm_fake,\n global_scale_fake,\n Int32(1), # Dummy M\n Float32(1e-6), # Dummy eps\n enable_pdl,\n stream_fake,\n options=\"--enable-tvm-ffi\",\n )\n\n def tensor_api(\n x: torch.Tensor,\n r: torch.Tensor,\n w: torch.Tensor,\n y: torch.Tensor,\n s: torch.Tensor,\n s_unswizzled: torch.Tensor,\n y_norm: torch.Tensor,\n global_scale: torch.Tensor,\n M: int,\n eps: float,\n ) -> None:\n \"\"\"Runtime API that passes torch tensors directly via TVM-FFI.\"\"\"\n nonlocal compiled_kernel\n # For swizzled mode or output_both_sf_layouts, flatten the scale tensor to 1D\n s_tensor = (\n s.flatten()\n if (is_sf_swizzled_layout or output_both_sf_layouts)\n else s.contiguous()\n )\n # View y as uint8 since kernel expects uint8 but caller may pass float4_e2m1fn_x2\n y_uint8 = y.view(torch.uint8)\n compiled_kernel(\n x,\n r,\n w,\n y_uint8,\n s_tensor,\n s_unswizzled.contiguous(),\n y_norm,\n global_scale,\n M,\n eps,\n )\n\n return tensor_api\n\n\n@flashinfer_api(trace=add_rmsnorm_fp4quant_trace_dispatch)\ndef add_rmsnorm_fp4quant(\n input: torch.Tensor,\n residual: torch.Tensor,\n weight: torch.Tensor,\n y_fp4: torch.Tensor | None = None,\n block_scale: torch.Tensor | None = None,\n global_scale: torch.Tensor | None = None,\n eps: float = 1e-6,\n block_size: int = 16,\n scale_format: str | None = None,\n is_sf_swizzled_layout: bool = False,\n output_both_sf_layouts: bool = False,\n block_scale_unswizzled: torch.Tensor | None = None,\n enable_pdl: bool | None = None,\n y_out: torch.Tensor | None = None,\n) -> Union[\n Tuple[torch.Tensor, torch.Tensor], Tuple[torch.Tensor, torch.Tensor, torch.Tensor]\n]:\n \"\"\"\n Fused Add + RMS normalization + FP4 quantization using CuTe-DSL.\n\n Computes:\n 1. ``residual = residual + input`` (in-place update)\n 2. ``y = RMSNorm(residual) * weight``\n 3. Optionally applies global scaling (``y = y / global_scale``)\n 4. Quantizes ``y`` to FP4\n\n The residual tensor is modified in-place to contain the fused value.\n\n Parameters\n ----------\n input : torch.Tensor\n Input tensor, shape ``(batch_size, hidden_size)`` or ``(batch_size, seq_len, hidden_size)``.\n Must be ``torch.float16`` or ``torch.bfloat16``. Read-only.\n residual : torch.Tensor\n Residual tensor. Must have the same shape and dtype as ``input``.\n **Modified in-place** to contain ``residual + input``.\n weight : torch.Tensor\n Weight tensor for RMSNorm, shape ``(hidden_size,)``.\n Must have the same dtype as input.\n y_fp4 : torch.Tensor, optional\n Output tensor for quantized values in FP4_E2M1 format with dtype\n ``torch.float4_e2m1fn_x2``.\n Shape must be ``(batch_size, hidden_size // 2)`` or matching 3D input.\n If ``None``, will be allocated automatically.\n block_scale : torch.Tensor, optional\n Output tensor for per-block scale factors.\n\n - If ``is_sf_swizzled_layout=False`` and ``output_both_sf_layouts=False``: row-major\n layout with shape ``(batch_size, hidden_size // block_size)`` or matching 3D input.\n - If ``is_sf_swizzled_layout=True`` or ``output_both_sf_layouts=True``: swizzled layout\n for efficient tensor core access, with shape\n ``(batch_size * hidden_size // block_size,)`` flattened.\n The swizzle pattern uses 128x4 tiles where scales are arranged as:\n ``[m_tile][k_tile][outer_m (32)][inner_m (4)][inner_k (4)]``.\n\n Dtype should be ``torch.float8_e4m3fn`` for E4M3 format or ``torch.uint8``\n for UE8M0 format. If ``None``, will be allocated automatically.\n global_scale : torch.Tensor, optional\n Global scale factor tensor of shape ``(1,)`` with dtype ``torch.float32``.\n If provided, the RMSNorm output is divided by this value before quantization:\n ``y = rmsnorm(h, w) / global_scale`` where ``h = input + residual``.\n This is used for NVFP4 format where a pre-computed global scale lifts\n per-block scales into optimal dynamic range.\n If ``None``, no global scaling is applied (equivalent to global_scale=1.0).\n eps : float\n Epsilon for numerical stability in RMSNorm. Default is ``1e-6``.\n block_size : int\n Number of elements per quantization block. Default is ``16``.\n\n - ``16``: NVFP4 format with E4M3 scale factors\n - ``32``: MXFP4 format with UE8M0 scale factors\n scale_format : str, optional\n Scale factor format: ``\"e4m3\"`` or ``\"ue8m0\"``.\n If ``None``, auto-selects based on ``block_size``:\n ``\"e4m3\"`` for block_size=16, ``\"ue8m0\"`` for block_size=32.\n is_sf_swizzled_layout : bool\n If ``True``, output scale factors in swizzled layout optimized for\n tensor core GEMM operations. The swizzle uses 128x4 tiles with the pattern:\n ``[m_tile_idx * k_tiles * 512 + k_tile_idx * 512 + outer_m * 16 + inner_m * 4 + inner_k]``\n where ``outer_m = row % 32``, ``inner_m = (row % 128) // 32``, etc.\n Default is ``False`` (row-major layout).\n Note: This parameter is ignored when ``output_both_sf_layouts=True``.\n output_both_sf_layouts : bool\n If ``True``, return both swizzled and unswizzled scale factors.\n When enabled, ``block_scale`` contains the swizzled layout and\n ``block_scale_unswizzled`` contains the row-major layout.\n This overrides ``is_sf_swizzled_layout``.\n Default is ``False``.\n block_scale_unswizzled : torch.Tensor, optional\n Output tensor for unswizzled per-block scale factors (row-major layout).\n Only used when ``output_both_sf_layouts=True``.\n Shape is ``(batch_size, hidden_size // block_size)`` or matching 3D input.\n Dtype should be ``torch.float8_e4m3fn`` for E4M3 format or ``torch.uint8``\n for UE8M0 format. If ``None``, will be allocated automatically when\n ``output_both_sf_layouts=True``.\n enable_pdl : bool, optional\n Whether to launch with Programmatic Dependent Launch (PDL). When\n ``None`` (default) or ``True``, PDL is enabled only if the current\n device supports it (probed via :func:`device_support_pdl`). Pass\n ``False`` to force-disable. See\n https://docs.nvidia.com/cuda/cuda-c-programming-guide/#programmatic-dependent-launch-and-synchronization\n y_out : torch.Tensor, optional\n Optional output tensor for the normed (pre-quantization) values\n ``y = RMSNorm(input + residual) * weight`` in the input dtype\n (fp16/bf16). Shape must be ``(batch_size, hidden_size)`` or matching\n 3D input, contiguous. **Written in place**; the return value of this\n function is unchanged (same tuple arity as without ``y_out``).\n When ``None`` (default), the normed values are not materialized and\n the generated kernel is identical to the baseline (the presence of\n ``y_out`` is a compile-time specialization).\n\n Returns\n -------\n Union[Tuple[torch.Tensor, torch.Tensor], Tuple[torch.Tensor, torch.Tensor, torch.Tensor]]\n When ``output_both_sf_layouts=False``:\n A tuple of ``(y_fp4, block_scale)``:\n\n - ``y_fp4``: Quantized FP4 values packed as uint8.\n - ``block_scale``: Per-block scale factors (swizzled or row-major based on\n ``is_sf_swizzled_layout``).\n\n When ``output_both_sf_layouts=True``:\n A tuple of ``(y_fp4, block_scale, block_scale_unswizzled)``:\n\n - ``y_fp4``: Quantized FP4 values packed as uint8.\n - ``block_scale``: Per-block scale factors in swizzled layout.\n - ``block_scale_unswizzled``: Per-block scale factors in row-major layout.\n\n Notes\n -----\n - Requires SM100+ (Blackwell) for FP4 quantization PTX intrinsics.\n - For block_size=16 (NVFP4): uses E4M3 scale factors (max value 448.0).\n - For block_size=32 (MXFP4): uses UE8M0 scale factors (power-of-2 scales).\n - FP4 E2M1 format has a max representable value of 6.0.\n \"\"\"\n _require_cute_dsl_arch_for(input.device)\n is_3d = input.dim() == 3\n if is_3d:\n B, S, H = input.shape\n input_2d = input.view(B * S, H).contiguous()\n residual_2d = residual.view(B * S, H).contiguous()\n else:\n input_2d = input\n residual_2d = residual\n\n batch_size, hidden_size = input_2d.shape\n dtype = input.dtype\n\n assert hidden_size % block_size == 0, \"hidden_size must be divisible by block_size\"\n assert hidden_size >= 64, \"hidden_size must be >= 64\"\n assert block_size in [16, 32], \"block_size must be 16 or 32\"\n\n is_fp16 = dtype == torch.float16\n actual_scale_format = (\n scale_format if scale_format else (\"ue8m0\" if block_size == 32 else \"e4m3\")\n )\n sm_version = get_sm_version(input.device)\n\n if enable_pdl is None or enable_pdl:\n enable_pdl = device_support_pdl(input.device)\n\n # Determine scale dtype based on format\n scale_dtype = torch.uint8 if actual_scale_format == \"ue8m0\" else torch.float8_e4m3fn\n num_sf_blocks_per_row = hidden_size // block_size\n\n # Allocate output tensors if not provided\n if y_fp4 is None:\n if is_3d:\n y_fp4 = torch.empty(\n (B, S, hidden_size // 2),\n dtype=torch.float4_e2m1fn_x2,\n device=input.device,\n )\n else:\n y_fp4 = torch.empty(\n (batch_size, hidden_size // 2),\n dtype=torch.float4_e2m1fn_x2,\n device=input.device,\n )\n\n if block_scale is None:\n # When output_both_sf_layouts=True, block_scale is always swizzled\n if is_sf_swizzled_layout or output_both_sf_layouts:\n # Swizzled layout: flattened with 128x4 tile pattern\n num_m_tiles = (batch_size + 127) // 128\n num_k_tiles = (num_sf_blocks_per_row + 3) // 4\n k_tile_stride = 512\n swizzled_size = num_m_tiles * num_k_tiles * k_tile_stride\n block_scale = torch.empty(\n (swizzled_size,), dtype=scale_dtype, device=input.device\n )\n else:\n if is_3d:\n block_scale = torch.empty(\n (B, S, num_sf_blocks_per_row),\n dtype=scale_dtype,\n device=input.device,\n )\n else:\n block_scale = torch.empty(\n (batch_size, num_sf_blocks_per_row),\n dtype=scale_dtype,\n device=input.device,\n )\n\n # Allocate unswizzled scale factor tensor\n # When output_both_sf_layouts=False, we still need a correctly-shaped tensor\n # for TVM-FFI validation, even though the kernel won't write to it\n if block_scale_unswizzled is None:\n if is_3d:\n block_scale_unswizzled = torch.empty(\n (B, S, num_sf_blocks_per_row),\n dtype=scale_dtype,\n device=input.device,\n )\n else:\n block_scale_unswizzled = torch.empty(\n (batch_size, num_sf_blocks_per_row),\n dtype=scale_dtype,\n device=input.device,\n )\n\n # Get 2D views for kernel\n if is_3d:\n y_fp4_2d = y_fp4.view(B * S, -1)\n block_scale_2d = (\n block_scale.view(B * S, -1)\n if not (is_sf_swizzled_layout or output_both_sf_layouts)\n else block_scale\n )\n # Always convert to 2D for kernel call\n block_scale_unswizzled_2d = block_scale_unswizzled.view(B * S, -1)\n else:\n y_fp4_2d = y_fp4\n block_scale_2d = block_scale\n block_scale_unswizzled_2d = block_scale_unswizzled\n\n # Create global_scale tensor if not provided (1.0 = no scaling)\n if global_scale is None:\n global_scale = torch.ones(1, dtype=torch.float32, device=input.device)\n\n # Optional normed (bf16/fp16) output — compile-time specialization\n output_norm = y_out is not None\n weight_contig = weight.contiguous()\n if output_norm:\n assert y_out.dtype == dtype, (\n f\"y_out dtype {y_out.dtype} must match input dtype {dtype}\"\n )\n assert y_out.device == input.device, (\n f\"y_out device {y_out.device} must match input device {input.device}\"\n )\n assert y_out.is_contiguous(), \"y_out must be contiguous\"\n assert y_out.shape == input.shape, (\n f\"y_out shape {tuple(y_out.shape)} must match the input shape \"\n f\"{tuple(input.shape)} (same (batch, hidden) or 3D layout)\"\n )\n assert y_out.data_ptr() % 16 == 0, \"y_out must be 16-byte aligned\"\n y_norm_arg = y_out.view(-1)\n else:\n # Dummy tensor; the kernel never reads or writes it when\n # output_norm=False (the store is compiled out).\n y_norm_arg = weight_contig\n\n tensor_api = _get_compiled_kernel(\n hidden_size,\n block_size,\n is_fp16,\n sm_version,\n actual_scale_format,\n is_sf_swizzled_layout,\n output_both_sf_layouts,\n enable_pdl,\n output_norm,\n )\n tensor_api(\n input_2d.contiguous(),\n residual_2d.contiguous(),\n weight_contig,\n y_fp4_2d,\n block_scale_2d.view(torch.uint8),\n block_scale_unswizzled_2d.view(torch.uint8),\n y_norm_arg,\n global_scale.contiguous(),\n batch_size,\n eps,\n )\n\n if output_both_sf_layouts:\n return y_fp4, block_scale, block_scale_unswizzled\n else:\n return y_fp4, block_scale\n\n\n__all__ = [\n \"AddRMSNormFP4QuantKernel\",\n \"add_rmsnorm_fp4quant\",\n \"get_sm_version\",\n]\n"},"after_code":{"kind":"string","value":"\"\"\"\nCopyright (c) 2025 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nFused Add + RMSNorm + FP4 Quantization using CuTe-DSL\n======================================================\n\nHigh-performance fused kernel for element-wise addition followed by RMS normalization\nand FP4 quantization. Supports both NVFP4 (block_size=16, E4M3 scales) and MXFP4\n(block_size=32, UE8M0 scales) formats.\n\nOperation:\n 1. residual = residual + input (in-place update)\n 2. output = (residual / sqrt(mean(residual²) + eps)) * weight\n 3. quantize output to FP4\n\nThe residual tensor is modified in-place to contain the fused value (input + residual).\n\n\"\"\"\n\nimport functools\nfrom typing import Callable, Tuple, Union\n\nimport cutlass\nimport cutlass.cute as cute\nimport torch\nfrom cutlass import Float32, Int32, Int64, Uint32, Uint64, Uint8\nfrom cutlass.cutlass_dsl import T, dsl_user_op\nfrom cutlass._mlir.dialects import llvm\n\nfrom .utils import require_cute_dsl_arch as _require_cute_dsl_arch_for\n\nfrom ..api_logging import flashinfer_api\nfrom ..trace.templates.norm import add_rmsnorm_fp4quant_trace_dispatch\nfrom ..utils import device_support_pdl\nfrom .fp4_common import (\n # Constants\n FLOAT4_E2M1_MAX,\n FLOAT8_E4M3_MAX,\n COPY_BITS,\n # Architecture detection\n get_sm_version,\n # PTX intrinsics - basic ops\n st_global_u64,\n get_ptr_as_int64,\n get_smem_ptr_as_int32,\n ld_shared_v4_u32,\n rcp_approx_ftz,\n fmin_f32,\n fmax_f32,\n # Half2 SIMD intrinsics\n hmax2,\n hmax_to_f32,\n # BFloat2 SIMD intrinsics\n bfloat2_hmax2,\n bfloat2_hmax_to_f32,\n # FP8 and FP4 conversion\n cvt_f32x2_to_half2,\n cvt_f32_to_e4m3,\n fp8_e4m3_to_f32_and_rcp,\n cvt_f32_to_ue8m0,\n ue8m0_to_output_scale,\n # Reduction utilities\n row_reduce,\n # Predicate utility\n predicate_k,\n # Helper functions for SF block processing\n load_8_half2,\n half2_mul_8,\n bfloat2_mul_8,\n half2_max_abs_8,\n bfloat2_max_abs_8,\n half2_to_float16,\n bfloat2_to_float16,\n quantize_and_pack_16,\n # Helper functions for Float32 shared memory processing\n load_f32_16_from_smem,\n compute_y_and_max_abs_f32,\n)\n\n\n@cute.jit\ndef _load_8_half2_from_smem(\n sX: cute.Tensor,\n sW: cute.Tensor,\n row_idx: Int32,\n col_offset: Int32,\n row_stride: int,\n):\n \"\"\"Load 16 packed fp16/bf16 values from each shared-memory tile.\"\"\"\n x_h2 = cute.make_rmem_tensor((8,), Uint32)\n w_h2 = cute.make_rmem_tensor((8,), Uint32)\n base = row_idx * row_stride + col_offset\n\n x_addr0 = get_smem_ptr_as_int32(sX, base)\n x_addr1 = get_smem_ptr_as_int32(sX, base + Int32(8))\n x_h2[0], x_h2[1], x_h2[2], x_h2[3] = ld_shared_v4_u32(x_addr0)\n x_h2[4], x_h2[5], x_h2[6], x_h2[7] = ld_shared_v4_u32(x_addr1)\n\n w_addr0 = get_smem_ptr_as_int32(sW, base)\n w_addr1 = get_smem_ptr_as_int32(sW, base + Int32(8))\n w_h2[0], w_h2[1], w_h2[2], w_h2[3] = ld_shared_v4_u32(w_addr0)\n w_h2[4], w_h2[5], w_h2[6], w_h2[7] = ld_shared_v4_u32(w_addr1)\n return x_h2, w_h2\n\n\n# =============================================================================\n# Helpers for optional normed (bf16/fp16) output\n# =============================================================================\n\n\n@dsl_user_op\ndef cvt_f32x2_to_bfloat2(a: Float32, b: Float32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Pack two float32 values into a bfloat2 (uint32 containing two bf16 values).\n\n Uses cvt.rn.bf16.f32 for each value, then packs into a single uint32.\n Mirrors cvt_f32x2_to_half2 in fp4_common.py.\n \"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [\n Float32(a).ir_value(loc=loc, ip=ip),\n Float32(b).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b16 h0, h1;\n cvt.rn.bf16.f32 h0, $1;\n cvt.rn.bf16.f32 h1, $2;\n mov.b32 $0, {h0, h1};\n }\n \"\"\",\n \"=r,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@cute.jit\ndef _store_y_norm_16(\n mN: cute.Tensor,\n y_f32: cute.Tensor,\n row_offset: Int32,\n col_offset: Int32,\n H: int,\n is_fp16: bool,\n):\n \"\"\"Store 16 normalized float32 values as fp16/bf16 to global memory.\n\n mN is a flat 1D tensor viewed as row-major (M, H). Uses 4x 64-bit stores\n (each packing 4 16-bit elements).\n \"\"\"\n for j in cutlass.range_constexpr(4):\n if cutlass.const_expr(is_fp16):\n lo = cvt_f32x2_to_half2(y_f32[4 * j], y_f32[4 * j + 1])\n hi = cvt_f32x2_to_half2(y_f32[4 * j + 2], y_f32[4 * j + 3])\n else:\n lo = cvt_f32x2_to_bfloat2(y_f32[4 * j], y_f32[4 * j + 1])\n hi = cvt_f32x2_to_bfloat2(y_f32[4 * j + 2], y_f32[4 * j + 3])\n packed64 = (Uint64(hi) << Uint64(32)) | Uint64(lo)\n ptr = get_ptr_as_int64(mN, row_offset * H + col_offset + Int32(4 * j))\n st_global_u64(ptr, packed64)\n\n\n# =============================================================================\n# CuTe-DSL Kernel Class\n# =============================================================================\n\n\nclass AddRMSNormFP4QuantKernel:\n \"\"\"\n Fused Add + RMSNorm + FP4 Quantization Kernel.\n\n Computes:\n 1. residual = input + residual (in-place update)\n 2. y = RMSNorm(residual) * weight\n 3. quantize y to FP4\n\n The residual tensor is modified in-place.\n Supports both NVFP4 (block_size=16) and MXFP4 (block_size=32) formats.\n \"\"\"\n\n # Offline sweep-tuned launch overrides. Unlisted configurations use the\n # general scale-block heuristic below.\n # (sm_version, H, block_size, is_fp16):\n # (cluster_n, threads_per_row, num_threads)\n _KNOB_LUT = {\n (103, 1024, 16, False): (1, 64, 256),\n }\n\n def __init__(\n self,\n dtype: cutlass.Numeric,\n H: int,\n block_size: int,\n output_swizzled: bool,\n is_fp16: bool,\n sm_version: int | None = None,\n scale_format: str | None = None,\n output_both_sf_layouts: bool = False,\n output_norm: bool = False,\n ):\n self.dtype = dtype\n self.H = H\n self.block_size = block_size\n self.output_swizzled = output_swizzled\n self.is_fp16 = is_fp16\n self.sm_version = sm_version if sm_version is not None else get_sm_version()\n self.output_both_sf_layouts = output_both_sf_layouts\n self.output_norm = output_norm\n\n if scale_format is None:\n self.scale_format = \"ue8m0\" if block_size == 32 else \"e4m3\"\n else:\n self.scale_format = scale_format\n\n assert block_size in (16, 32), f\"block_size must be 16 or 32, got {block_size}\"\n assert self.scale_format in (\"e4m3\", \"ue8m0\"), (\n \"scale_format must be 'e4m3' or 'ue8m0'\"\n )\n\n knobs = self._select_knobs(H, block_size, is_fp16, self.sm_version)\n if knobs is None:\n self.cluster_n = self._compute_cluster_n(\n H, dtype, self.sm_version, block_size\n )\n self.H_per_cta = H // self.cluster_n\n self.threads_per_row = self._compute_threads_per_row(\n self.H_per_cta, block_size\n )\n self.num_threads = self._compute_num_threads(self.threads_per_row)\n else:\n self.cluster_n, self.threads_per_row, self.num_threads = knobs\n self.H_per_cta = H // self.cluster_n\n\n self.rows_per_block = self.num_threads // self.threads_per_row\n self.warps_per_row = max(self.threads_per_row // 32, 1)\n\n elem_bytes = dtype.width // 8\n self.vec_size = COPY_BITS // 8 // elem_bytes\n self.num_vec_blocks = max(\n 1,\n (self.H_per_cta // self.vec_size + self.threads_per_row - 1)\n // self.threads_per_row,\n )\n self.cols_per_tile = self.vec_size * self.num_vec_blocks * self.threads_per_row\n\n self.num_sf_blocks_per_row = H // block_size\n\n # Need swizzle params if output_swizzled or output_both_sf_layouts\n if output_swizzled or output_both_sf_layouts:\n num_col_vecs = H // block_size\n self.num_k_tiles = (num_col_vecs + 3) // 4\n self.k_tile_stride = 512\n\n @staticmethod\n def _compute_cluster_n(\n H: int, dtype: cutlass.Numeric, sm_version: int, block_size: int\n ) -> int:\n \"\"\"Compute optimal cluster size based on H and device shared memory.\n\n Dynamically determines the minimum cluster_n that fits within the\n device's shared memory limit, making it compatible with different\n GPU architectures (e.g., SM100 with 228KB vs SM120 with 128KB).\n \"\"\"\n if sm_version < 90:\n return 1\n\n props = torch.cuda.get_device_properties(torch.cuda.current_device())\n max_smem_bytes = props.shared_memory_per_block_optin\n elem_size = dtype.width // 8\n\n for cluster_n in [1, 2, 4, 8, 16]:\n if H % cluster_n != 0:\n continue\n smem_needed = AddRMSNormFP4QuantKernel._estimate_smem_bytes(\n H, cluster_n, elem_size, block_size\n )\n if smem_needed <= max_smem_bytes:\n return cluster_n\n\n return 16\n\n @staticmethod\n def _compute_threads_per_row(H_per_cta: int, block_size: int) -> int:\n \"\"\"Assign one warp per 32 scale-factor blocks, capped at 8 warps.\"\"\"\n num_sf_blocks = H_per_cta // block_size\n return min(((num_sf_blocks + 31) // 32) * 32, 256)\n\n @staticmethod\n def _compute_num_threads(threads_per_row: int) -> int:\n \"\"\"Use multiple rows per block while keeping a 128-thread target.\"\"\"\n rows_per_block = max(1, 128 // threads_per_row)\n return rows_per_block * threads_per_row\n\n @staticmethod\n def _select_knobs(\n H: int,\n block_size: int,\n is_fp16: bool,\n sm_version: int,\n ) -> tuple[int, int, int] | None:\n \"\"\"Return an offline-tuned launch, if one is available.\"\"\"\n return AddRMSNormFP4QuantKernel._KNOB_LUT.get(\n (sm_version, H, block_size, is_fp16)\n )\n\n @staticmethod\n def _estimate_smem_bytes(\n H: int, cluster_n: int, elem_size: int, block_size: int\n ) -> int:\n \"\"\"Estimate shared memory bytes needed for given configuration.\n\n This is used to dynamically determine cluster_n based on device\n shared memory limits.\n \"\"\"\n H_per_cta = H // cluster_n\n threads_per_row = AddRMSNormFP4QuantKernel._compute_threads_per_row(\n H_per_cta, block_size\n )\n num_threads = AddRMSNormFP4QuantKernel._compute_num_threads(threads_per_row)\n rows_per_block = num_threads // threads_per_row\n warps_per_row = max(threads_per_row // 32, 1)\n\n vec_size = COPY_BITS // 8 // elem_size\n num_vec_blocks = max(\n 1, (H_per_cta // vec_size + threads_per_row - 1) // threads_per_row\n )\n cols_per_tile = vec_size * num_vec_blocks * threads_per_row\n\n tile_bytes = rows_per_block * cols_per_tile * elem_size\n\n if cluster_n == 1:\n # 4 tiles: sX, sR, sW, sH + reduction buffer\n return 4 * tile_bytes + rows_per_block * warps_per_row * 4\n else:\n # 2 tiles: sX, sR + larger reduction buffer + mbarrier\n return 2 * tile_bytes + rows_per_block * warps_per_row * cluster_n * 4 + 8\n\n @staticmethod\n def _make_tv_layout(\n threads_per_row: int,\n rows_per_block: int,\n vec_size: int,\n num_vec_blocks: int,\n ) -> tuple:\n \"\"\"Create Thread-Value layout for coalesced vectorized memory access.\"\"\"\n shape = (\n (threads_per_row, rows_per_block),\n (vec_size, num_vec_blocks),\n )\n stride = (\n (vec_size * rows_per_block, 1),\n (rows_per_block, rows_per_block * vec_size * threads_per_row),\n )\n return shape, stride\n\n def _smem_size_in_bytes(self) -> int:\n \"\"\"Calculate shared memory requirement.\"\"\"\n elem_size = self.dtype.width // 8\n x_tile_bytes = self.rows_per_block * self.cols_per_tile * elem_size\n r_tile_bytes = self.rows_per_block * self.cols_per_tile * elem_size\n\n if self.cluster_n == 1:\n w_tile_bytes = self.rows_per_block * self.cols_per_tile * elem_size\n h_tile_bytes = self.rows_per_block * self.cols_per_tile * elem_size\n reduction_bytes = self.rows_per_block * self.warps_per_row * 4\n else:\n w_tile_bytes = 0\n h_tile_bytes = 0\n reduction_bytes = (\n self.rows_per_block * self.warps_per_row * self.cluster_n * 4\n )\n\n mbar_bytes = 8 if self.cluster_n > 1 else 0\n\n return (\n x_tile_bytes\n + r_tile_bytes\n + w_tile_bytes\n + h_tile_bytes\n + reduction_bytes\n + mbar_bytes\n )\n\n @cute.jit\n def __call__(\n self,\n mX: cute.Tensor,\n mR: cute.Tensor,\n mW: cute.Tensor,\n mY: cute.Tensor,\n mS: cute.Tensor,\n mS_unswizzled: cute.Tensor,\n mYNorm: cute.Tensor,\n mGlobalScale: cute.Tensor,\n M: Int32,\n eps: Float32,\n enable_pdl: cutlass.Constexpr[bool],\n stream,\n ):\n \"\"\"Host function to launch the kernel.\n\n Takes tensors directly via TVM-FFI.\n - mX: Input tensor, shape (M, H), row-major (read-only)\n - mR: Residual tensor, shape (M, H), row-major (modified in-place to input + residual)\n - mW: Weight tensor, shape (H,)\n - mY: Output FP4 tensor, shape (M, H // 2), row-major (packed)\n - mS: Scale factor tensor, shape depends on swizzle mode\n - mS_unswizzled: Unswizzled scale factor tensor (used when output_both_sf_layouts=True)\n - mYNorm: Optional normed output tensor, flat 1D view of (M, H), same dtype as\n input (only written when output_norm=True; pass any dummy tensor otherwise)\n - mGlobalScale: Global scale tensor, shape (1,), float32\n \"\"\"\n\n tv_shape, tv_stride = self._make_tv_layout(\n self.threads_per_row,\n self.rows_per_block,\n self.vec_size,\n self.num_vec_blocks,\n )\n tv_layout = cute.make_layout(tv_shape, stride=tv_stride)\n tiler_mn = (self.rows_per_block, self.cols_per_tile)\n\n self.kernel(\n mX,\n mR,\n mW,\n mY,\n mS,\n mS_unswizzled,\n mYNorm,\n mGlobalScale,\n M,\n eps,\n enable_pdl,\n tv_layout,\n tiler_mn,\n ).launch(\n grid=[cute.ceil_div(M, self.rows_per_block), self.cluster_n, 1],\n block=[self.num_threads, 1, 1],\n cluster=[1, self.cluster_n, 1]\n if cutlass.const_expr(self.cluster_n > 1)\n else None,\n smem=self._smem_size_in_bytes(),\n stream=stream,\n use_pdl=enable_pdl,\n )\n\n @cute.kernel\n def kernel(\n self,\n mX: cute.Tensor,\n mR: cute.Tensor,\n mW: cute.Tensor,\n mY: cute.Tensor,\n mS: cute.Tensor,\n mS_unswizzled: cute.Tensor,\n mYNorm: cute.Tensor,\n mGlobalScale: cute.Tensor,\n M: Int32,\n eps: Float32,\n enable_pdl: cutlass.Constexpr[bool],\n tv_layout: cute.Layout,\n tiler_mn: cute.Shape,\n ):\n \"\"\"Device kernel with cluster sync and Half2 SIMD.\n\n Performs:\n 1. h = input + residual (writes h back to mR in-place)\n 2. y = h * rstd * w / global_scale = rmsnorm(h, w) / global_scale\n 3. quantizes y to FP4\n\n mGlobalScale contains the global scale value. The kernel reads it and\n computes 1/global_scale, which is multiplied with rstd to apply:\n y = h * rstd * w / global_scale = rmsnorm(h, w) / global_scale\n \"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n\n if enable_pdl:\n cute.arch.griddepcontrol_wait()\n bidx, _, _ = cute.arch.block_idx()\n\n H = self.H\n block_size = self.block_size\n num_sf_blocks_per_row = self.num_sf_blocks_per_row\n is_fp16 = self.is_fp16\n cluster_n = self.cluster_n\n\n if cutlass.const_expr(cluster_n > 1):\n cluster_y = cute.arch.block_idx()[1]\n else:\n cluster_y = cutlass.const_expr(0)\n\n threads_per_row = tv_layout.shape[0][0]\n warps_per_row = max(threads_per_row // 32, 1)\n rows_per_block = tiler_mn[0]\n\n lane_in_row = tidx % threads_per_row\n row_in_block = tidx // threads_per_row\n\n fp4_max_rcp = rcp_approx_ftz(Float32(FLOAT4_E2M1_MAX))\n\n # Allocate shared memory\n smem = cutlass.utils.SmemAllocator()\n\n sX = smem.allocate_tensor(\n mX.element_type,\n cute.make_ordered_layout(tiler_mn, order=(1, 0)),\n byte_alignment=16,\n )\n\n sR = smem.allocate_tensor(\n mR.element_type,\n cute.make_ordered_layout(tiler_mn, order=(1, 0)),\n byte_alignment=16,\n )\n\n if cutlass.const_expr(cluster_n == 1):\n sW = smem.allocate_tensor(\n mW.element_type,\n cute.make_ordered_layout(tiler_mn, order=(1, 0)),\n byte_alignment=16,\n )\n sH = smem.allocate_tensor(\n mX.element_type,\n cute.make_ordered_layout(tiler_mn, order=(1, 0)),\n byte_alignment=16,\n )\n\n if cutlass.const_expr(cluster_n == 1):\n reduction_buffer = smem.allocate_tensor(\n Float32,\n cute.make_layout((rows_per_block, warps_per_row)),\n byte_alignment=4,\n )\n mbar_ptr = None\n else:\n reduction_buffer = smem.allocate_tensor(\n Float32,\n cute.make_layout((rows_per_block, (warps_per_row, cluster_n))),\n byte_alignment=4,\n )\n mbar_ptr = smem.allocate_array(Int64, num_elems=1)\n\n # Initialize cluster\n if cutlass.const_expr(cluster_n > 1):\n if tidx == 0:\n cute.arch.mbarrier_init(mbar_ptr, 1)\n cute.arch.mbarrier_init_fence()\n cute.arch.cluster_arrive_relaxed()\n cute.arch.cluster_wait()\n\n # Create identity tensor\n idX = cute.make_identity_tensor(mX.shape)\n\n gX = cute.local_tile(mX, tiler_mn, (bidx, cluster_y))\n gR = cute.local_tile(mR, tiler_mn, (bidx, cluster_y))\n cX = cute.local_tile(idX, tiler_mn, (bidx, cluster_y))\n\n if cutlass.const_expr(cluster_n == 1):\n mW_expanded_layout = cute.prepend(\n mW.layout, cute.make_layout((tiler_mn[0],), stride=(0,))\n )\n mW_2d = cute.make_tensor(mW.iterator, mW_expanded_layout)\n gW = cute.local_tile(mW_2d, tiler_mn, (0, cluster_y))\n\n # TiledCopy for loads\n copy_atom_load_async = cute.make_copy_atom(\n cute.nvgpu.cpasync.CopyG2SOp(),\n mX.element_type,\n num_bits_per_copy=COPY_BITS,\n )\n\n # TiledCopy for stores (to write h back to residual)\n copy_atom_store = cute.make_copy_atom(\n cute.nvgpu.CopyUniversalOp(),\n mR.element_type,\n num_bits_per_copy=COPY_BITS,\n )\n\n tiled_copy_load = cute.make_tiled_copy(\n copy_atom_load_async, tv_layout, tiler_mn\n )\n tiled_copy_store = cute.make_tiled_copy(copy_atom_store, tv_layout, tiler_mn)\n\n thr_copy_X = tiled_copy_load.get_slice(tidx)\n thr_copy_R = tiled_copy_load.get_slice(tidx)\n thr_copy_R_store = tiled_copy_store.get_slice(tidx)\n\n tXgX = thr_copy_X.partition_S(gX)\n tXsX = thr_copy_X.partition_D(sX)\n tRgR = thr_copy_R.partition_S(gR)\n tRsR = thr_copy_R.partition_D(sR)\n tXcX = thr_copy_X.partition_S(cX)\n\n # Output partition for writing h back to residual (in-place update)\n tRgO = thr_copy_R_store.partition_D(gR)\n\n if cutlass.const_expr(cluster_n == 1):\n thr_copy_W = tiled_copy_load.get_slice(tidx)\n tWgW = thr_copy_W.partition_S(gW)\n tWsW = thr_copy_W.partition_D(sW)\n tHsH = thr_copy_X.partition_D(sH)\n\n tXrX = cute.make_fragment_like(tXgX)\n tRrR = cute.make_fragment_like(tRgR)\n tRrO = cute.make_fragment_like(tRgO) # Register fragment for residual output\n\n # Bounds checking\n tXpX = predicate_k(tXcX, limit=H)\n row_coord = tXcX[(0, 0), 0, 0]\n row_in_bounds = row_coord[0] < M\n\n # Phase 1: Async copy\n if row_in_bounds:\n cute.copy(copy_atom_load_async, tXgX, tXsX, pred=tXpX)\n cute.copy(copy_atom_load_async, tRgR, tRsR, pred=tXpX)\n\n if cutlass.const_expr(cluster_n == 1):\n cute.copy(copy_atom_load_async, tWgW, tWsW, pred=tXpX)\n\n cute.arch.cp_async_commit_group()\n cute.arch.cp_async_wait_group(0)\n\n # Phase 2: h = x + r and sum of squares\n cute.autovec_copy(tXsX, tXrX)\n cute.autovec_copy(tRsR, tRrR)\n\n x_vals = tXrX.load().to(Float32)\n r_vals = tRrR.load().to(Float32)\n\n h_vals = x_vals + r_vals\n h_sq = h_vals * h_vals\n\n # Store h to residual output registers (for in-place update of residual)\n tRrO.store(h_vals.to(self.dtype))\n\n if cutlass.const_expr(cluster_n == 1):\n h_elem = h_vals.to(mX.element_type)\n tHsH.store(h_elem)\n\n sum_sq = row_reduce(\n h_sq,\n cute.ReductionOp.ADD,\n threads_per_row,\n reduction_buffer,\n mbar_ptr,\n cluster_n,\n Float32(0.0),\n )\n\n mean_sq = sum_sq / H\n rstd = cute.math.rsqrt(mean_sq + eps, fastmath=True)\n\n # Read global_scale from device memory (CUDA graph compatible)\n # Note: global_scale is incorporated into the block scale, NOT applied to input\n global_scale_val = mGlobalScale[0]\n\n if cutlass.const_expr(cluster_n > 1):\n cute.arch.cluster_arrive_relaxed()\n cute.arch.cluster_wait()\n else:\n cute.arch.barrier()\n\n # Write h back to residual tensor (in-place update: residual = input + residual)\n if row_in_bounds:\n cute.copy(copy_atom_store, tRrO, tRgO, pred=tXpX)\n\n # In cluster mode, Phase 3 reads from mR across the FULL hidden dimension,\n # including slices written by other CTAs. We must ensure all CTAs' global\n # memory writes are visible before any CTA proceeds to Phase 3.\n if cutlass.const_expr(cluster_n > 1):\n cute.arch.fence_acq_rel_cluster()\n cute.arch.cluster_arrive_relaxed()\n cute.arch.cluster_wait()\n\n actual_row_idx = bidx * rows_per_block + row_in_block\n\n # Phase 3: RMSNorm + Quantize\n if actual_row_idx < M:\n num_sf_per_thread = (\n num_sf_blocks_per_row + threads_per_row - 1\n ) // threads_per_row\n\n for sf_iter in range(num_sf_per_thread):\n sf_idx = lane_in_row + sf_iter * threads_per_row\n\n if sf_idx < num_sf_blocks_per_row:\n block_start = sf_idx * block_size\n\n if cutlass.const_expr(block_size == 16):\n if cutlass.const_expr(cluster_n == 1):\n h_h2, w_h2 = _load_8_half2_from_smem(\n sH,\n sW,\n row_in_block,\n block_start,\n self.cols_per_tile,\n )\n if cutlass.const_expr(is_fp16):\n h_f32 = half2_to_float16(h_h2, Float32(1.0))\n w_f32 = half2_to_float16(w_h2, Float32(1.0))\n else:\n h_f32 = bfloat2_to_float16(h_h2, Float32(1.0))\n w_f32 = bfloat2_to_float16(w_h2, Float32(1.0))\n y_f32, max_abs = compute_y_and_max_abs_f32(\n h_f32, w_f32, rstd\n )\n\n # E4M3: global_scale is incorporated into block scale\n scale_float = global_scale_val * max_abs * fp4_max_rcp\n scale_float = fmin_f32(\n scale_float, Float32(FLOAT8_E4M3_MAX)\n )\n scale_fp8_u32 = cvt_f32_to_e4m3(scale_float)\n scale_fp8 = Uint8(scale_fp8_u32 & Uint32(0xFF))\n inv_scale = (\n fp8_e4m3_to_f32_and_rcp(scale_fp8_u32)\n * global_scale_val\n )\n\n if cutlass.const_expr(self.output_both_sf_layouts):\n inner_k_idx = sf_idx % Int32(4)\n inner_m_idx = (actual_row_idx % Int32(128)) // Int32(32)\n outer_m_idx = actual_row_idx % Int32(32)\n k_tile_idx = sf_idx // Int32(4)\n m_tile_idx = actual_row_idx // Int32(128)\n m_tile_stride = self.num_k_tiles * self.k_tile_stride\n swizzled_offset = (\n m_tile_idx * m_tile_stride\n + k_tile_idx * self.k_tile_stride\n + outer_m_idx * Int32(16)\n + inner_m_idx * Int32(4)\n + inner_k_idx\n )\n mS[swizzled_offset] = scale_fp8\n mS_unswizzled[actual_row_idx, sf_idx] = scale_fp8\n elif cutlass.const_expr(self.output_swizzled):\n inner_k_idx = sf_idx % Int32(4)\n inner_m_idx = (actual_row_idx % Int32(128)) // Int32(32)\n outer_m_idx = actual_row_idx % Int32(32)\n k_tile_idx = sf_idx // Int32(4)\n m_tile_idx = actual_row_idx // Int32(128)\n m_tile_stride = self.num_k_tiles * self.k_tile_stride\n swizzled_offset = (\n m_tile_idx * m_tile_stride\n + k_tile_idx * self.k_tile_stride\n + outer_m_idx * Int32(16)\n + inner_m_idx * Int32(4)\n + inner_k_idx\n )\n mS[swizzled_offset] = scale_fp8\n else:\n mS[actual_row_idx, sf_idx] = scale_fp8\n\n packed64 = quantize_and_pack_16(y_f32, inv_scale)\n out_offset = block_start // 2\n out_ptr = get_ptr_as_int64(\n mY, actual_row_idx * (H // 2) + out_offset\n )\n st_global_u64(out_ptr, packed64)\n\n if cutlass.const_expr(self.output_norm):\n _store_y_norm_16(\n mYNorm,\n y_f32,\n actual_row_idx,\n block_start,\n H,\n is_fp16,\n )\n\n else:\n # Global memory path (cluster mode) - use helper functions\n # mR contains h = x + r, so load from mR\n h_h2, w_h2 = load_8_half2(\n mR, mW, actual_row_idx, block_start, H\n )\n\n if cutlass.const_expr(is_fp16):\n hw_h2 = half2_mul_8(h_h2, w_h2)\n max_hw = half2_max_abs_8(hw_h2)\n max_xw = hmax_to_f32(max_hw)\n y_f32 = half2_to_float16(hw_h2, rstd)\n else:\n hw_h2 = bfloat2_mul_8(h_h2, w_h2)\n max_hw = bfloat2_max_abs_8(hw_h2)\n max_xw = bfloat2_hmax_to_f32(max_hw)\n y_f32 = bfloat2_to_float16(hw_h2, rstd)\n\n max_abs = max_xw * rstd\n\n # E4M3: global_scale is incorporated into block scale\n scale_float = global_scale_val * max_abs * fp4_max_rcp\n scale_float = fmin_f32(\n scale_float, Float32(FLOAT8_E4M3_MAX)\n )\n scale_fp8_u32 = cvt_f32_to_e4m3(scale_float)\n scale_fp8 = Uint8(scale_fp8_u32 & Uint32(0xFF))\n inv_scale = (\n fp8_e4m3_to_f32_and_rcp(scale_fp8_u32)\n * global_scale_val\n )\n\n if cutlass.const_expr(self.output_both_sf_layouts):\n inner_k_idx = sf_idx % Int32(4)\n inner_m_idx = (actual_row_idx % Int32(128)) // Int32(32)\n outer_m_idx = actual_row_idx % Int32(32)\n k_tile_idx = sf_idx // Int32(4)\n m_tile_idx = actual_row_idx // Int32(128)\n m_tile_stride = self.num_k_tiles * self.k_tile_stride\n swizzled_offset = (\n m_tile_idx * m_tile_stride\n + k_tile_idx * self.k_tile_stride\n + outer_m_idx * Int32(16)\n + inner_m_idx * Int32(4)\n + inner_k_idx\n )\n mS[swizzled_offset] = scale_fp8\n mS_unswizzled[actual_row_idx, sf_idx] = scale_fp8\n elif cutlass.const_expr(self.output_swizzled):\n inner_k_idx = sf_idx % Int32(4)\n inner_m_idx = (actual_row_idx % Int32(128)) // Int32(32)\n outer_m_idx = actual_row_idx % Int32(32)\n k_tile_idx = sf_idx // Int32(4)\n m_tile_idx = actual_row_idx // Int32(128)\n m_tile_stride = self.num_k_tiles * self.k_tile_stride\n swizzled_offset = (\n m_tile_idx * m_tile_stride\n + k_tile_idx * self.k_tile_stride\n + outer_m_idx * Int32(16)\n + inner_m_idx * Int32(4)\n + inner_k_idx\n )\n mS[swizzled_offset] = scale_fp8\n else:\n mS[actual_row_idx, sf_idx] = scale_fp8\n\n packed64 = quantize_and_pack_16(y_f32, inv_scale)\n out_offset = block_start // 2\n out_ptr = get_ptr_as_int64(\n mY, actual_row_idx * (H // 2) + out_offset\n )\n st_global_u64(out_ptr, packed64)\n\n if cutlass.const_expr(self.output_norm):\n _store_y_norm_16(\n mYNorm,\n y_f32,\n actual_row_idx,\n block_start,\n H,\n is_fp16,\n )\n\n else:\n # block_size == 32 (MXFP4) - process in two chunks of 16\n if cutlass.const_expr(cluster_n == 1):\n # Shared memory path - use helper functions\n # Load and compute first 16 elements\n h_f32_c0 = load_f32_16_from_smem(\n sH, row_in_block, block_start\n )\n w_f32_c0 = load_f32_16_from_smem(\n sW, row_in_block, block_start\n )\n y_f32_c0, max_abs_c0 = compute_y_and_max_abs_f32(\n h_f32_c0, w_f32_c0, rstd\n )\n\n # Load and compute second 16 elements\n h_f32_c1 = load_f32_16_from_smem(\n sH, row_in_block, block_start + Int32(16)\n )\n w_f32_c1 = load_f32_16_from_smem(\n sW, row_in_block, block_start + Int32(16)\n )\n y_f32_c1, max_abs_c1 = compute_y_and_max_abs_f32(\n h_f32_c1, w_f32_c1, rstd\n )\n\n # Combine max_abs from both chunks\n max_abs = fmax_f32(max_abs_c0, max_abs_c1)\n\n # Compute scale factor (E4M3 or UE8M0)\n if cutlass.const_expr(self.scale_format == \"ue8m0\"):\n scale_float = max_abs * fp4_max_rcp\n scale_ue8m0 = cvt_f32_to_ue8m0(scale_float)\n scale_u8 = Uint8(scale_ue8m0 & Uint32(0xFF))\n inv_scale = ue8m0_to_output_scale(scale_ue8m0)\n else:\n scale_float = global_scale_val * max_abs * fp4_max_rcp\n scale_float = fmin_f32(\n scale_float, Float32(FLOAT8_E4M3_MAX)\n )\n scale_fp8_u32 = cvt_f32_to_e4m3(scale_float)\n scale_u8 = Uint8(scale_fp8_u32 & Uint32(0xFF))\n inv_scale = (\n fp8_e4m3_to_f32_and_rcp(scale_fp8_u32)\n * global_scale_val\n )\n\n if cutlass.const_expr(self.output_both_sf_layouts):\n inner_k_idx = sf_idx % Int32(4)\n inner_m_idx = (actual_row_idx % Int32(128)) // Int32(32)\n outer_m_idx = actual_row_idx % Int32(32)\n k_tile_idx = sf_idx // Int32(4)\n m_tile_idx = actual_row_idx // Int32(128)\n m_tile_stride = self.num_k_tiles * self.k_tile_stride\n swizzled_offset = (\n m_tile_idx * m_tile_stride\n + k_tile_idx * self.k_tile_stride\n + outer_m_idx * Int32(16)\n + inner_m_idx * Int32(4)\n + inner_k_idx\n )\n mS[swizzled_offset] = scale_u8\n mS_unswizzled[actual_row_idx, sf_idx] = scale_u8\n elif cutlass.const_expr(self.output_swizzled):\n inner_k_idx = sf_idx % Int32(4)\n inner_m_idx = (actual_row_idx % Int32(128)) // Int32(32)\n outer_m_idx = actual_row_idx % Int32(32)\n k_tile_idx = sf_idx // Int32(4)\n m_tile_idx = actual_row_idx // Int32(128)\n m_tile_stride = self.num_k_tiles * self.k_tile_stride\n swizzled_offset = (\n m_tile_idx * m_tile_stride\n + k_tile_idx * self.k_tile_stride\n + outer_m_idx * Int32(16)\n + inner_m_idx * Int32(4)\n + inner_k_idx\n )\n mS[swizzled_offset] = scale_u8\n else:\n mS[actual_row_idx, sf_idx] = scale_u8\n\n # Quantize and store both chunks\n packed64_c0 = quantize_and_pack_16(y_f32_c0, inv_scale)\n packed64_c1 = quantize_and_pack_16(y_f32_c1, inv_scale)\n\n fp4_offset = actual_row_idx * (H // 2) + sf_idx * (\n block_size // 2\n )\n fp4_ptr_0 = get_ptr_as_int64(mY, fp4_offset)\n fp4_ptr_1 = get_ptr_as_int64(mY, fp4_offset + Int32(8))\n st_global_u64(fp4_ptr_0, packed64_c0)\n st_global_u64(fp4_ptr_1, packed64_c1)\n\n if cutlass.const_expr(self.output_norm):\n _store_y_norm_16(\n mYNorm,\n y_f32_c0,\n actual_row_idx,\n block_start,\n H,\n is_fp16,\n )\n _store_y_norm_16(\n mYNorm,\n y_f32_c1,\n actual_row_idx,\n block_start + Int32(16),\n H,\n is_fp16,\n )\n\n else:\n # Global memory path (cluster mode) - use helper functions\n # mR contains h = x + r, load in two chunks\n h_h2_c0, w_h2_c0 = load_8_half2(\n mR, mW, actual_row_idx, block_start, H\n )\n h_h2_c1, w_h2_c1 = load_8_half2(\n mR, mW, actual_row_idx, block_start + Int32(16), H\n )\n\n if cutlass.const_expr(is_fp16):\n hw_h2_c0 = half2_mul_8(h_h2_c0, w_h2_c0)\n hw_h2_c1 = half2_mul_8(h_h2_c1, w_h2_c1)\n max_c0_h2 = half2_max_abs_8(hw_h2_c0)\n max_c1_h2 = half2_max_abs_8(hw_h2_c1)\n max_hw = hmax2(max_c0_h2, max_c1_h2)\n max_xw = hmax_to_f32(max_hw)\n y_f32_c0 = half2_to_float16(hw_h2_c0, rstd)\n y_f32_c1 = half2_to_float16(hw_h2_c1, rstd)\n else:\n hw_h2_c0 = bfloat2_mul_8(h_h2_c0, w_h2_c0)\n hw_h2_c1 = bfloat2_mul_8(h_h2_c1, w_h2_c1)\n max_c0_h2 = bfloat2_max_abs_8(hw_h2_c0)\n max_c1_h2 = bfloat2_max_abs_8(hw_h2_c1)\n max_hw = bfloat2_hmax2(max_c0_h2, max_c1_h2)\n max_xw = bfloat2_hmax_to_f32(max_hw)\n y_f32_c0 = bfloat2_to_float16(hw_h2_c0, rstd)\n y_f32_c1 = bfloat2_to_float16(hw_h2_c1, rstd)\n\n max_abs = max_xw * rstd\n\n # Compute scale factor (E4M3 or UE8M0)\n if cutlass.const_expr(self.scale_format == \"ue8m0\"):\n scale_float = max_abs * fp4_max_rcp\n scale_ue8m0 = cvt_f32_to_ue8m0(scale_float)\n scale_u8 = Uint8(scale_ue8m0 & Uint32(0xFF))\n inv_scale = ue8m0_to_output_scale(scale_ue8m0)\n else:\n scale_float = global_scale_val * max_abs * fp4_max_rcp\n scale_float = fmin_f32(\n scale_float, Float32(FLOAT8_E4M3_MAX)\n )\n scale_fp8_u32 = cvt_f32_to_e4m3(scale_float)\n scale_u8 = Uint8(scale_fp8_u32 & Uint32(0xFF))\n inv_scale = (\n fp8_e4m3_to_f32_and_rcp(scale_fp8_u32)\n * global_scale_val\n )\n\n if cutlass.const_expr(self.output_both_sf_layouts):\n inner_k_idx = sf_idx % Int32(4)\n inner_m_idx = (actual_row_idx % Int32(128)) // Int32(32)\n outer_m_idx = actual_row_idx % Int32(32)\n k_tile_idx = sf_idx // Int32(4)\n m_tile_idx = actual_row_idx // Int32(128)\n m_tile_stride = self.num_k_tiles * self.k_tile_stride\n swizzled_offset = (\n m_tile_idx * m_tile_stride\n + k_tile_idx * self.k_tile_stride\n + outer_m_idx * Int32(16)\n + inner_m_idx * Int32(4)\n + inner_k_idx\n )\n mS[swizzled_offset] = scale_u8\n mS_unswizzled[actual_row_idx, sf_idx] = scale_u8\n elif cutlass.const_expr(self.output_swizzled):\n inner_k_idx = sf_idx % Int32(4)\n inner_m_idx = (actual_row_idx % Int32(128)) // Int32(32)\n outer_m_idx = actual_row_idx % Int32(32)\n k_tile_idx = sf_idx // Int32(4)\n m_tile_idx = actual_row_idx // Int32(128)\n m_tile_stride = self.num_k_tiles * self.k_tile_stride\n swizzled_offset = (\n m_tile_idx * m_tile_stride\n + k_tile_idx * self.k_tile_stride\n + outer_m_idx * Int32(16)\n + inner_m_idx * Int32(4)\n + inner_k_idx\n )\n mS[swizzled_offset] = scale_u8\n else:\n mS[actual_row_idx, sf_idx] = scale_u8\n\n # Quantize and store both chunks\n packed64_c0 = quantize_and_pack_16(y_f32_c0, inv_scale)\n packed64_c1 = quantize_and_pack_16(y_f32_c1, inv_scale)\n\n fp4_offset = actual_row_idx * (H // 2) + sf_idx * (\n block_size // 2\n )\n fp4_ptr_0 = get_ptr_as_int64(mY, fp4_offset)\n fp4_ptr_1 = get_ptr_as_int64(mY, fp4_offset + Int32(8))\n st_global_u64(fp4_ptr_0, packed64_c0)\n st_global_u64(fp4_ptr_1, packed64_c1)\n\n if cutlass.const_expr(self.output_norm):\n _store_y_norm_16(\n mYNorm,\n y_f32_c0,\n actual_row_idx,\n block_start,\n H,\n is_fp16,\n )\n _store_y_norm_16(\n mYNorm,\n y_f32_c1,\n actual_row_idx,\n block_start + Int32(16),\n H,\n is_fp16,\n )\n\n if enable_pdl:\n cute.arch.griddepcontrol_launch_dependents()\n\n\n# =============================================================================\n# PyTorch API Functions\n# =============================================================================\n\n\n@functools.cache\ndef _get_compiled_kernel(\n hidden_size: int,\n block_size: int,\n is_fp16: bool,\n sm_version: int,\n scale_format: str,\n is_sf_swizzled_layout: bool,\n output_both_sf_layouts: bool = False,\n enable_pdl: bool = False,\n output_norm: bool = False,\n) -> Callable:\n \"\"\"\n Get a compiled kernel closure that takes torch.Tensor directly.\n\n Uses TVM-FFI for efficient tensor passing without manual pointer construction.\n \"\"\"\n cutlass_dtype = cutlass.Float16 if is_fp16 else cutlass.BFloat16\n\n kernel_obj = AddRMSNormFP4QuantKernel(\n dtype=cutlass_dtype,\n H=hidden_size,\n block_size=block_size,\n output_swizzled=is_sf_swizzled_layout,\n is_fp16=is_fp16,\n sm_version=sm_version,\n scale_format=scale_format,\n output_both_sf_layouts=output_both_sf_layouts,\n output_norm=output_norm,\n )\n\n # Use symbolic size for dynamic M dimension\n sym_m = cute.sym_int()\n\n # Create fake tensors for compilation with TVM-FFI\n # Use stride_order=(1, 0) for row-major layout and assumed_align=128 for async copy\n x_fake = cute.runtime.make_fake_compact_tensor(\n cutlass_dtype, (sym_m, hidden_size), stride_order=(1, 0), assumed_align=128\n )\n r_fake = cute.runtime.make_fake_compact_tensor(\n cutlass_dtype, (sym_m, hidden_size), stride_order=(1, 0), assumed_align=128\n )\n w_fake = cute.runtime.make_fake_compact_tensor(\n cutlass_dtype, (hidden_size,), assumed_align=128\n )\n y_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_m, hidden_size // 2), stride_order=(1, 0), assumed_align=128\n )\n\n # Scale factor tensor layout depends on swizzle mode or output_both_sf_layouts\n if is_sf_swizzled_layout or output_both_sf_layouts:\n # For swizzled mode, use 1D layout - the swizzle pattern is computed in kernel\n # Size is: num_m_tiles * num_k_tiles * 512, which is independent of M\n # Use a separate symbolic variable for this size\n sym_swizzled_size = cute.sym_int()\n s_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_swizzled_size,), assumed_align=128\n )\n else:\n # For non-swizzled mode, use 2D row-major layout\n s_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (sym_m, hidden_size // block_size),\n stride_order=(1, 0),\n assumed_align=128,\n )\n\n # Unswizzled scale factor tensor (always 2D row-major, used when output_both_sf_layouts=True)\n s_unswizzled_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (sym_m, hidden_size // block_size),\n stride_order=(1, 0),\n assumed_align=128,\n )\n\n # Optional normed output tensor (flat 1D view of (M, hidden_size)).\n # Uses an independent symbolic size so a small dummy tensor can be passed\n # when output_norm=False (the kernel never touches it in that case).\n sym_ynorm_size = cute.sym_int()\n ynorm_fake = cute.runtime.make_fake_compact_tensor(\n cutlass_dtype, (sym_ynorm_size,), assumed_align=16\n )\n\n # Create fake stream that uses environment stream at runtime\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n\n # Global scale fake tensor (shape [1], float32)\n global_scale_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32, (1,), assumed_align=4\n )\n\n # Compile with TVM-FFI enabled\n compiled_kernel = cute.compile(\n kernel_obj,\n x_fake,\n r_fake,\n w_fake,\n y_fake,\n s_fake,\n s_unswizzled_fake,\n ynorm_fake,\n global_scale_fake,\n Int32(1), # Dummy M\n Float32(1e-6), # Dummy eps\n enable_pdl,\n stream_fake,\n options=\"--enable-tvm-ffi\",\n )\n\n def tensor_api(\n x: torch.Tensor,\n r: torch.Tensor,\n w: torch.Tensor,\n y: torch.Tensor,\n s: torch.Tensor,\n s_unswizzled: torch.Tensor,\n y_norm: torch.Tensor,\n global_scale: torch.Tensor,\n M: int,\n eps: float,\n ) -> None:\n \"\"\"Runtime API that passes torch tensors directly via TVM-FFI.\"\"\"\n nonlocal compiled_kernel\n # For swizzled mode or output_both_sf_layouts, flatten the scale tensor to 1D\n s_tensor = (\n s.flatten()\n if (is_sf_swizzled_layout or output_both_sf_layouts)\n else s.contiguous()\n )\n # View y as uint8 since kernel expects uint8 but caller may pass float4_e2m1fn_x2\n y_uint8 = y.view(torch.uint8)\n compiled_kernel(\n x,\n r,\n w,\n y_uint8,\n s_tensor,\n s_unswizzled.contiguous(),\n y_norm,\n global_scale,\n M,\n eps,\n )\n\n return tensor_api\n\n\n@flashinfer_api(trace=add_rmsnorm_fp4quant_trace_dispatch)\ndef add_rmsnorm_fp4quant(\n input: torch.Tensor,\n residual: torch.Tensor,\n weight: torch.Tensor,\n y_fp4: torch.Tensor | None = None,\n block_scale: torch.Tensor | None = None,\n global_scale: torch.Tensor | None = None,\n eps: float = 1e-6,\n block_size: int = 16,\n scale_format: str | None = None,\n is_sf_swizzled_layout: bool = False,\n output_both_sf_layouts: bool = False,\n block_scale_unswizzled: torch.Tensor | None = None,\n enable_pdl: bool | None = None,\n y_out: torch.Tensor | None = None,\n) -> Union[\n Tuple[torch.Tensor, torch.Tensor], Tuple[torch.Tensor, torch.Tensor, torch.Tensor]\n]:\n \"\"\"\n Fused Add + RMS normalization + FP4 quantization using CuTe-DSL.\n\n Computes:\n 1. ``residual = residual + input`` (in-place update)\n 2. ``y = RMSNorm(residual) * weight``\n 3. Optionally applies global scaling (``y = y / global_scale``)\n 4. Quantizes ``y`` to FP4\n\n The residual tensor is modified in-place to contain the fused value.\n\n Parameters\n ----------\n input : torch.Tensor\n Input tensor, shape ``(batch_size, hidden_size)`` or ``(batch_size, seq_len, hidden_size)``.\n Must be ``torch.float16`` or ``torch.bfloat16``. Read-only.\n residual : torch.Tensor\n Residual tensor. Must have the same shape and dtype as ``input``.\n **Modified in-place** to contain ``residual + input``.\n weight : torch.Tensor\n Weight tensor for RMSNorm, shape ``(hidden_size,)``.\n Must have the same dtype as input.\n y_fp4 : torch.Tensor, optional\n Output tensor for quantized values in FP4_E2M1 format with dtype\n ``torch.float4_e2m1fn_x2``.\n Shape must be ``(batch_size, hidden_size // 2)`` or matching 3D input.\n If ``None``, will be allocated automatically.\n block_scale : torch.Tensor, optional\n Output tensor for per-block scale factors.\n\n - If ``is_sf_swizzled_layout=False`` and ``output_both_sf_layouts=False``: row-major\n layout with shape ``(batch_size, hidden_size // block_size)`` or matching 3D input.\n - If ``is_sf_swizzled_layout=True`` or ``output_both_sf_layouts=True``: swizzled layout\n for efficient tensor core access, with shape\n ``(batch_size * hidden_size // block_size,)`` flattened.\n The swizzle pattern uses 128x4 tiles where scales are arranged as:\n ``[m_tile][k_tile][outer_m (32)][inner_m (4)][inner_k (4)]``.\n\n Dtype should be ``torch.float8_e4m3fn`` for E4M3 format or ``torch.uint8``\n for UE8M0 format. If ``None``, will be allocated automatically.\n global_scale : torch.Tensor, optional\n Global scale factor tensor of shape ``(1,)`` with dtype ``torch.float32``.\n If provided, the RMSNorm output is divided by this value before quantization:\n ``y = rmsnorm(h, w) / global_scale`` where ``h = input + residual``.\n This is used for NVFP4 format where a pre-computed global scale lifts\n per-block scales into optimal dynamic range.\n If ``None``, no global scaling is applied (equivalent to global_scale=1.0).\n eps : float\n Epsilon for numerical stability in RMSNorm. Default is ``1e-6``.\n block_size : int\n Number of elements per quantization block. Default is ``16``.\n\n - ``16``: NVFP4 format with E4M3 scale factors\n - ``32``: MXFP4 format with UE8M0 scale factors\n scale_format : str, optional\n Scale factor format: ``\"e4m3\"`` or ``\"ue8m0\"``.\n If ``None``, auto-selects based on ``block_size``:\n ``\"e4m3\"`` for block_size=16, ``\"ue8m0\"`` for block_size=32.\n is_sf_swizzled_layout : bool\n If ``True``, output scale factors in swizzled layout optimized for\n tensor core GEMM operations. The swizzle uses 128x4 tiles with the pattern:\n ``[m_tile_idx * k_tiles * 512 + k_tile_idx * 512 + outer_m * 16 + inner_m * 4 + inner_k]``\n where ``outer_m = row % 32``, ``inner_m = (row % 128) // 32``, etc.\n Default is ``False`` (row-major layout).\n Note: This parameter is ignored when ``output_both_sf_layouts=True``.\n output_both_sf_layouts : bool\n If ``True``, return both swizzled and unswizzled scale factors.\n When enabled, ``block_scale`` contains the swizzled layout and\n ``block_scale_unswizzled`` contains the row-major layout.\n This overrides ``is_sf_swizzled_layout``.\n Default is ``False``.\n block_scale_unswizzled : torch.Tensor, optional\n Output tensor for unswizzled per-block scale factors (row-major layout).\n Only used when ``output_both_sf_layouts=True``.\n Shape is ``(batch_size, hidden_size // block_size)`` or matching 3D input.\n Dtype should be ``torch.float8_e4m3fn`` for E4M3 format or ``torch.uint8``\n for UE8M0 format. If ``None``, will be allocated automatically when\n ``output_both_sf_layouts=True``.\n enable_pdl : bool, optional\n Whether to launch with Programmatic Dependent Launch (PDL). When\n ``None`` (default) or ``True``, PDL is enabled only if the current\n device supports it (probed via :func:`device_support_pdl`). Pass\n ``False`` to force-disable. See\n https://docs.nvidia.com/cuda/cuda-c-programming-guide/#programmatic-dependent-launch-and-synchronization\n y_out : torch.Tensor, optional\n Optional output tensor for the normed (pre-quantization) values\n ``y = RMSNorm(input + residual) * weight`` in the input dtype\n (fp16/bf16). Shape must be ``(batch_size, hidden_size)`` or matching\n 3D input, contiguous. **Written in place**; the return value of this\n function is unchanged (same tuple arity as without ``y_out``).\n When ``None`` (default), the normed values are not materialized and\n the generated kernel is identical to the baseline (the presence of\n ``y_out`` is a compile-time specialization).\n\n Returns\n -------\n Union[Tuple[torch.Tensor, torch.Tensor], Tuple[torch.Tensor, torch.Tensor, torch.Tensor]]\n When ``output_both_sf_layouts=False``:\n A tuple of ``(y_fp4, block_scale)``:\n\n - ``y_fp4``: Quantized FP4 values packed as uint8.\n - ``block_scale``: Per-block scale factors (swizzled or row-major based on\n ``is_sf_swizzled_layout``).\n\n When ``output_both_sf_layouts=True``:\n A tuple of ``(y_fp4, block_scale, block_scale_unswizzled)``:\n\n - ``y_fp4``: Quantized FP4 values packed as uint8.\n - ``block_scale``: Per-block scale factors in swizzled layout.\n - ``block_scale_unswizzled``: Per-block scale factors in row-major layout.\n\n Notes\n -----\n - Requires SM100+ (Blackwell) for FP4 quantization PTX intrinsics.\n - For block_size=16 (NVFP4): uses E4M3 scale factors (max value 448.0).\n - For block_size=32 (MXFP4): uses UE8M0 scale factors (power-of-2 scales).\n - FP4 E2M1 format has a max representable value of 6.0.\n \"\"\"\n _require_cute_dsl_arch_for(input.device)\n is_3d = input.dim() == 3\n if is_3d:\n B, S, H = input.shape\n input_2d = input.view(B * S, H).contiguous()\n residual_2d = residual.view(B * S, H).contiguous()\n else:\n input_2d = input\n residual_2d = residual\n\n batch_size, hidden_size = input_2d.shape\n dtype = input.dtype\n\n assert hidden_size % block_size == 0, \"hidden_size must be divisible by block_size\"\n assert hidden_size >= 64, \"hidden_size must be >= 64\"\n assert block_size in [16, 32], \"block_size must be 16 or 32\"\n\n is_fp16 = dtype == torch.float16\n actual_scale_format = (\n scale_format if scale_format else (\"ue8m0\" if block_size == 32 else \"e4m3\")\n )\n sm_version = get_sm_version(input.device)\n\n if enable_pdl is None or enable_pdl:\n enable_pdl = device_support_pdl(input.device)\n\n # Determine scale dtype based on format\n scale_dtype = torch.uint8 if actual_scale_format == \"ue8m0\" else torch.float8_e4m3fn\n num_sf_blocks_per_row = hidden_size // block_size\n\n # Allocate output tensors if not provided\n if y_fp4 is None:\n if is_3d:\n y_fp4 = torch.empty(\n (B, S, hidden_size // 2),\n dtype=torch.float4_e2m1fn_x2,\n device=input.device,\n )\n else:\n y_fp4 = torch.empty(\n (batch_size, hidden_size // 2),\n dtype=torch.float4_e2m1fn_x2,\n device=input.device,\n )\n\n if block_scale is None:\n # When output_both_sf_layouts=True, block_scale is always swizzled\n if is_sf_swizzled_layout or output_both_sf_layouts:\n # Swizzled layout: flattened with 128x4 tile pattern\n num_m_tiles = (batch_size + 127) // 128\n num_k_tiles = (num_sf_blocks_per_row + 3) // 4\n k_tile_stride = 512\n swizzled_size = num_m_tiles * num_k_tiles * k_tile_stride\n block_scale = torch.empty(\n (swizzled_size,), dtype=scale_dtype, device=input.device\n )\n else:\n if is_3d:\n block_scale = torch.empty(\n (B, S, num_sf_blocks_per_row),\n dtype=scale_dtype,\n device=input.device,\n )\n else:\n block_scale = torch.empty(\n (batch_size, num_sf_blocks_per_row),\n dtype=scale_dtype,\n device=input.device,\n )\n\n # Allocate unswizzled scale factor tensor\n # When output_both_sf_layouts=False, we still need a correctly-shaped tensor\n # for TVM-FFI validation, even though the kernel won't write to it\n if block_scale_unswizzled is None:\n if is_3d:\n block_scale_unswizzled = torch.empty(\n (B, S, num_sf_blocks_per_row),\n dtype=scale_dtype,\n device=input.device,\n )\n else:\n block_scale_unswizzled = torch.empty(\n (batch_size, num_sf_blocks_per_row),\n dtype=scale_dtype,\n device=input.device,\n )\n\n # Get 2D views for kernel\n if is_3d:\n y_fp4_2d = y_fp4.view(B * S, -1)\n block_scale_2d = (\n block_scale.view(B * S, -1)\n if not (is_sf_swizzled_layout or output_both_sf_layouts)\n else block_scale\n )\n # Always convert to 2D for kernel call\n block_scale_unswizzled_2d = block_scale_unswizzled.view(B * S, -1)\n else:\n y_fp4_2d = y_fp4\n block_scale_2d = block_scale\n block_scale_unswizzled_2d = block_scale_unswizzled\n\n # Create global_scale tensor if not provided (1.0 = no scaling)\n if global_scale is None:\n global_scale = torch.ones(1, dtype=torch.float32, device=input.device)\n\n # Optional normed (bf16/fp16) output — compile-time specialization\n output_norm = y_out is not None\n weight_contig = weight.contiguous()\n if output_norm:\n assert y_out.dtype == dtype, (\n f\"y_out dtype {y_out.dtype} must match input dtype {dtype}\"\n )\n assert y_out.device == input.device, (\n f\"y_out device {y_out.device} must match input device {input.device}\"\n )\n assert y_out.is_contiguous(), \"y_out must be contiguous\"\n assert y_out.shape == input.shape, (\n f\"y_out shape {tuple(y_out.shape)} must match the input shape \"\n f\"{tuple(input.shape)} (same (batch, hidden) or 3D layout)\"\n )\n assert y_out.data_ptr() % 16 == 0, \"y_out must be 16-byte aligned\"\n y_norm_arg = y_out.view(-1)\n else:\n # Dummy tensor; the kernel never reads or writes it when\n # output_norm=False (the store is compiled out).\n y_norm_arg = weight_contig\n\n tensor_api = _get_compiled_kernel(\n hidden_size,\n block_size,\n is_fp16,\n sm_version,\n actual_scale_format,\n is_sf_swizzled_layout,\n output_both_sf_layouts,\n enable_pdl,\n output_norm,\n )\n tensor_api(\n input_2d.contiguous(),\n residual_2d.contiguous(),\n weight_contig,\n y_fp4_2d,\n block_scale_2d.view(torch.uint8),\n block_scale_unswizzled_2d.view(torch.uint8),\n y_norm_arg,\n global_scale.contiguous(),\n batch_size,\n eps,\n )\n\n if output_both_sf_layouts:\n return y_fp4, block_scale, block_scale_unswizzled\n else:\n return y_fp4, block_scale\n\n\n__all__ = [\n \"AddRMSNormFP4QuantKernel\",\n \"add_rmsnorm_fp4quant\",\n \"get_sm_version\",\n]\n"},"diff":{"kind":"string","value":"--- flashinfer/cute_dsl/add_rmsnorm_fp4quant.py\n+++ flashinfer/cute_dsl/add_rmsnorm_fp4quant.py\n@@ -54,6 +54,8 @@\n # PTX intrinsics - basic ops\n st_global_u64,\n get_ptr_as_int64,\n+ get_smem_ptr_as_int32,\n+ ld_shared_v4_u32,\n rcp_approx_ftz,\n fmin_f32,\n fmax_f32,\n@@ -88,6 +90,31 @@\n )\n \n \n+@cute.jit\n+def _load_8_half2_from_smem(\n+ sX: cute.Tensor,\n+ sW: cute.Tensor,\n+ row_idx: Int32,\n+ col_offset: Int32,\n+ row_stride: int,\n+):\n+ \"\"\"Load 16 packed fp16/bf16 values from each shared-memory tile.\"\"\"\n+ x_h2 = cute.make_rmem_tensor((8,), Uint32)\n+ w_h2 = cute.make_rmem_tensor((8,), Uint32)\n+ base = row_idx * row_stride + col_offset\n+\n+ x_addr0 = get_smem_ptr_as_int32(sX, base)\n+ x_addr1 = get_smem_ptr_as_int32(sX, base + Int32(8))\n+ x_h2[0], x_h2[1], x_h2[2], x_h2[3] = ld_shared_v4_u32(x_addr0)\n+ x_h2[4], x_h2[5], x_h2[6], x_h2[7] = ld_shared_v4_u32(x_addr1)\n+\n+ w_addr0 = get_smem_ptr_as_int32(sW, base)\n+ w_addr1 = get_smem_ptr_as_int32(sW, base + Int32(8))\n+ w_h2[0], w_h2[1], w_h2[2], w_h2[3] = ld_shared_v4_u32(w_addr0)\n+ w_h2[4], w_h2[5], w_h2[6], w_h2[7] = ld_shared_v4_u32(w_addr1)\n+ return x_h2, w_h2\n+\n+\n # =============================================================================\n # Helpers for optional normed (bf16/fp16) output\n # =============================================================================\n@@ -167,6 +194,14 @@\n Supports both NVFP4 (block_size=16) and MXFP4 (block_size=32) formats.\n \"\"\"\n \n+ # Offline sweep-tuned launch overrides. Unlisted configurations use the\n+ # general scale-block heuristic below.\n+ # (sm_version, H, block_size, is_fp16):\n+ # (cluster_n, threads_per_row, num_threads)\n+ _KNOB_LUT = {\n+ (103, 1024, 16, False): (1, 64, 256),\n+ }\n+\n def __init__(\n self,\n dtype: cutlass.Numeric,\n@@ -198,11 +233,20 @@\n \"scale_format must be 'e4m3' or 'ue8m0'\"\n )\n \n- self.cluster_n = self._compute_cluster_n(H, dtype, self.sm_version)\n- self.H_per_cta = H // self.cluster_n\n-\n- self.threads_per_row = self._compute_threads_per_row(self.H_per_cta)\n- self.num_threads = self._compute_num_threads(self.H_per_cta)\n+ knobs = self._select_knobs(H, block_size, is_fp16, self.sm_version)\n+ if knobs is None:\n+ self.cluster_n = self._compute_cluster_n(\n+ H, dtype, self.sm_version, block_size\n+ )\n+ self.H_per_cta = H // self.cluster_n\n+ self.threads_per_row = self._compute_threads_per_row(\n+ self.H_per_cta, block_size\n+ )\n+ self.num_threads = self._compute_num_threads(self.threads_per_row)\n+ else:\n+ self.cluster_n, self.threads_per_row, self.num_threads = knobs\n+ self.H_per_cta = H // self.cluster_n\n+\n self.rows_per_block = self.num_threads // self.threads_per_row\n self.warps_per_row = max(self.threads_per_row // 32, 1)\n \n@@ -224,7 +268,9 @@\n self.k_tile_stride = 512\n \n @staticmethod\n- def _compute_cluster_n(H: int, dtype: cutlass.Numeric, sm_version: int) -> int:\n+ def _compute_cluster_n(\n+ H: int, dtype: cutlass.Numeric, sm_version: int, block_size: int\n+ ) -> int:\n \"\"\"Compute optimal cluster size based on H and device shared memory.\n \n Dynamically determines the minimum cluster_n that fits within the\n@@ -242,7 +288,7 @@\n if H % cluster_n != 0:\n continue\n smem_needed = AddRMSNormFP4QuantKernel._estimate_smem_bytes(\n- H, cluster_n, elem_size\n+ H, cluster_n, elem_size, block_size\n )\n if smem_needed <= max_smem_bytes:\n return cluster_n\n@@ -250,36 +296,43 @@\n return 16\n \n @staticmethod\n- def _compute_threads_per_row(H_per_cta: int) -> int:\n- \"\"\"Compute optimal threads per row.\"\"\"\n- if H_per_cta <= 64:\n- return 8\n- elif H_per_cta <= 128:\n- return 16\n- elif H_per_cta <= 3072:\n- return 32\n- elif H_per_cta <= 6144:\n- return 64\n- elif H_per_cta <= 16384:\n- return 128\n- else:\n- return 256\n+ def _compute_threads_per_row(H_per_cta: int, block_size: int) -> int:\n+ \"\"\"Assign one warp per 32 scale-factor blocks, capped at 8 warps.\"\"\"\n+ num_sf_blocks = H_per_cta // block_size\n+ return min(((num_sf_blocks + 31) // 32) * 32, 256)\n \n @staticmethod\n- def _compute_num_threads(H_per_cta: int) -> int:\n- \"\"\"Compute total threads per block.\"\"\"\n- return 128 if H_per_cta <= 16384 else 256\n+ def _compute_num_threads(threads_per_row: int) -> int:\n+ \"\"\"Use multiple rows per block while keeping a 128-thread target.\"\"\"\n+ rows_per_block = max(1, 128 // threads_per_row)\n+ return rows_per_block * threads_per_row\n \n @staticmethod\n- def _estimate_smem_bytes(H: int, cluster_n: int, elem_size: int) -> int:\n+ def _select_knobs(\n+ H: int,\n+ block_size: int,\n+ is_fp16: bool,\n+ sm_version: int,\n+ ) -> tuple[int, int, int] | None:\n+ \"\"\"Return an offline-tuned launch, if one is available.\"\"\"\n+ return AddRMSNormFP4QuantKernel._KNOB_LUT.get(\n+ (sm_version, H, block_size, is_fp16)\n+ )\n+\n+ @staticmethod\n+ def _estimate_smem_bytes(\n+ H: int, cluster_n: int, elem_size: int, block_size: int\n+ ) -> int:\n \"\"\"Estimate shared memory bytes needed for given configuration.\n \n This is used to dynamically determine cluster_n based on device\n shared memory limits.\n \"\"\"\n H_per_cta = H // cluster_n\n- threads_per_row = AddRMSNormFP4QuantKernel._compute_threads_per_row(H_per_cta)\n- num_threads = AddRMSNormFP4QuantKernel._compute_num_threads(H_per_cta)\n+ threads_per_row = AddRMSNormFP4QuantKernel._compute_threads_per_row(\n+ H_per_cta, block_size\n+ )\n+ num_threads = AddRMSNormFP4QuantKernel._compute_num_threads(threads_per_row)\n rows_per_block = num_threads // threads_per_row\n warps_per_row = max(threads_per_row // 32, 1)\n \n@@ -652,9 +705,19 @@\n \n if cutlass.const_expr(block_size == 16):\n if cutlass.const_expr(cluster_n == 1):\n- # Shared memory path - use helper functions\n- h_f32 = load_f32_16_from_smem(sH, row_in_block, block_start)\n- w_f32 = load_f32_16_from_smem(sW, row_in_block, block_start)\n+ h_h2, w_h2 = _load_8_half2_from_smem(\n+ sH,\n+ sW,\n+ row_in_block,\n+ block_start,\n+ self.cols_per_tile,\n+ )\n+ if cutlass.const_expr(is_fp16):\n+ h_f32 = half2_to_float16(h_h2, Float32(1.0))\n+ w_f32 = half2_to_float16(w_h2, Float32(1.0))\n+ else:\n+ h_f32 = bfloat2_to_float16(h_h2, Float32(1.0))\n+ w_f32 = bfloat2_to_float16(w_h2, Float32(1.0))\n y_f32, max_abs = compute_y_and_max_abs_f32(\n h_f32, w_f32, rstd\n )"},"lines_added":{"kind":"number","value":93,"string":"93"},"lines_removed":{"kind":"number","value":30,"string":"30"},"files_in_commit":{"kind":"number","value":1,"string":"1"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cute_dsl kernel file from flashinfer (flashinfer/cute_dsl/add_rmsnorm_fp4quant.py).\n\nGoal: perf(norm): speed up fused add RMSNorm FP4 quantization\nTarget hardware: unspecified\nTarget models: unspecified\n\nCurrent file:\n```python\n\"\"\"\nCopyright (c) 2025 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nFused Add + RMSNorm + FP4 Quantization using CuTe-DSL\n======================================================\n\nHigh-performance fused kernel for element-wise addition followed by RMS normalization\nand FP4 quantization. Supports both NVFP4 (block_size=16, E4M3 scales) and MXFP4\n(block_size=32, UE8M0 scales) formats.\n\nOperation:\n 1. residual = residual + input (in-place update)\n 2. output = (residual / sqrt(mean(residual²) + eps)) * weight\n 3. quantize output to FP4\n\nThe residual tensor is modified in-place to contain the fused value (input + residual).\n\n\"\"\"\n\nimport functools\nfrom typing import Callable, Tuple, Union\n\nimport cutlass\nimport cutlass.cute as cute\nimport torch\nfrom cutlass import Float32, Int32, Int64, Uint32, Uint64, Uint8\nfrom cutlass.cutlass_dsl import T, dsl_user_op\nfrom cutlass._mlir.dialects import llvm\n\nfrom .utils import require_cute_dsl_arch as _require_cute_dsl_arch_for\n\nfrom ..api_logging import flashinfer_api\nfrom ..trace.templates.norm import add_rmsnorm_fp4quant_trace_dispatch\nfrom ..utils import device_support_pdl\nfrom .fp4_common import (\n # Constants\n FLOAT4_E2M1_MAX,\n FLOAT8_E4M3_MAX,\n COPY_BITS,\n # Architecture detection\n get_sm_version,\n # PTX intrinsics - basic ops\n st_global_u64,\n get_ptr_as_int64,\n rcp_approx_ftz,\n fmin_f32,\n fmax_f32,\n # Half2 SIMD intrinsics\n hmax2,\n hmax_to_f32,\n # BFloat2 SIMD intrinsics\n bfloat2_hmax2,\n bfloat2_hmax_to_f32,\n # FP8 and FP4 conversion\n cvt_f32x2_to_half2,\n cvt_f32_to_e4m3,\n fp8_e4m3_to_f32_and_rcp,\n cvt_f32_to_ue8m0,\n ue8m0_to_output_scale,\n # Reduction utilities\n row_reduce,\n # Predicate utility\n predicate_k,\n # Helper functions for SF block processing\n load_8_half2,\n half2_mul_8,\n bfloat2_mul_8,\n half2_max_abs_8,\n bfloat2_max_abs_8,\n half2_to_float16,\n bfloat2_to_float16,\n quantize_and_pack_16,\n # Helper functions for Float32 shared memory processing\n load_f32_16_from_smem,\n compute_y_and_max_abs_f32,\n)\n\n\n# =============================================================================\n# Helpers for optional normed (bf16/fp16) output\n# =============================================================================\n\n\n@dsl_user_op\ndef cvt_f32x2_to_bfloat2(a: Float32, b: Float32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Pack two float32 values into a bfloat2 (uint32 containing two bf16 values).\n\n Uses cvt.rn.bf16.f32 for each value, then packs into a single uint32.\n Mirrors cvt_f32x2_to_half2 in fp4_common.py.\n \"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [\n Float32(a).ir_value(loc=loc, ip=ip),\n Float32(b).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b16 h0, h1;\n cvt.rn.bf16.f32 h0, $1;\n cvt.rn.bf16.f32 h1, $2;\n mov.b32 $0, {h0, h1};\n }\n \"\"\",\n \"=r,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@cute.jit\ndef _store_y_norm_16(\n mN: cute.Tensor,\n y_f32: cute.Tensor,\n row_offset: Int32,\n col_offset: Int32,\n H: int,\n is_fp16: bool,\n):\n \"\"\"Store 16 normalized float32 values as fp16/bf16 to global memory.\n\n mN is a flat 1D tensor viewed as row-major (M, H). Uses 4x 64-bit stores\n (each packing 4 16-bit elements).\n \"\"\"\n for j in cutlass.range_constexpr(4):\n if cutlass.const_expr(is_fp16):\n lo = cvt_f32x2_to_half2(y_f32[4 * j], y_f32[4 * j + 1])\n hi = cvt_f32x2_to_half2(y_f32[4 * j + 2], y_f32[4 * j + 3])\n else:\n lo = cvt_f32x2_to_bfloat2(y_f32[4 * j], y_f32[4 * j + 1])\n hi = cvt_f32x2_to_bfloat2(y_f32[4 * j + 2], y_f32[4 * j + 3])\n packed64 = (Uint64(hi) << Uint64(32)) | Uint64(lo)\n ptr = get_ptr_as_int64(mN, row_offset * H + col_offset + Int32(4 * j))\n st_global_u64(ptr, packed64)\n\n\n# =============================================================================\n# CuTe-DSL Kernel Class\n# =============================================================================\n\n\nclass AddRMSNormFP4QuantKernel:\n \"\"\"\n Fused Add + RMSNorm + FP4 Quantization Kernel.\n\n Computes:\n 1. residual = input + residual (in-place update)\n 2. y = RMSNorm(residual) * weight\n 3. quantize y to FP4\n\n The residual tensor is modified in-place.\n Supports both NVFP4 (block_size=16) and MXFP4 (block_size=32) formats.\n \"\"\"\n\n def __init__(\n self,\n dtype: cutlass.Numeric,\n H: int,\n block_size: int,\n output_swizzled: bool,\n is_fp16: bool,\n sm_version: int | None = None,\n scale_format: str | None = None,\n output_both_sf_layouts: bool = False,\n output_norm: bool = False,\n ):\n self.dtype = dtype\n self.H = H\n self.block_size = block_size\n self.output_swizzled = output_swizzled\n self.is_fp16 = is_fp16\n self.sm_version = sm_version if sm_version is not None else get_sm_version()\n self.output_both_sf_layouts = output_both_sf_layouts\n self.output_norm = output_norm\n\n if scale_format is None:\n self.scale_format = \"ue8m0\" if block_size == 32 else \"e4m3\"\n else:\n self.scale_format = scale_format\n\n assert block_size in (16, 32), f\"block_size must be 16 or 32, got {block_size}\"\n assert self.scale_format in (\"e4m3\", \"ue8m0\"), (\n \"scale_format must be 'e4m3' or 'ue8m0'\"\n )\n\n self.cluster_n = self._compute_cluster_n(H, dtype, self.sm_version)\n self.H_per_cta = H // self.cluster_n\n\n self.threads_per_row = self._compute_threads_per_row(self.H_per_cta)\n self.num_threads = self._compute_num_threads(self.H_per_cta)\n self.rows_per_block = self.num_threads // self.threads_per_row\n self.warps_per_row = max(self.threads_per_row // 32, 1)\n\n elem_bytes = dtype.width // 8\n self.vec_size = COPY_BITS // 8 // elem_bytes\n self.num_vec_blocks = max(\n 1,\n (self.H_per_cta // self.vec_size + self.threads_per_row - 1)\n // self.threads_per_row,\n )\n self.cols_per_tile = self.vec_size * self.num_vec_blocks * self.threads_per_row\n\n self.num_sf_blocks_per_row = H // block_size\n\n # Need swizzle params if output_swizzled or output_both_sf_layouts\n if output_swizzled or output_both_sf_layouts:\n num_col_vecs = H // block_size\n self.num_k_tiles = (num_col_vecs + 3) // 4\n self.k_tile_stride = 512\n\n @staticmethod\n def _compute_cluster_n(H: int, dtype: cutlass.Numeric, sm_version: int) -> int:\n \"\"\"Compute optimal cluster size based on H and device shared memory.\n\n Dynamically determines the minimum cluster_n that fits within the\n device's shared memory limit, making it compatible with different\n GPU architectures (e.g., SM100 with 228KB vs SM120 with 128KB).\n \"\"\"\n if sm_version < 90:\n return 1\n\n props = torch.cuda.get_device_properties(torch.cuda.current_device())\n max_smem_bytes = props.shared_memory_per_block_optin\n elem_size = dtype.width // 8\n\n for cluster_n in [1, 2, 4, 8, 16]:\n if H % cluster_n != 0:\n continue\n smem_needed = AddRMSNormFP4QuantKernel._estimate_smem_bytes(\n H, cluster_n, elem_size\n )\n if smem_needed <= max_smem_bytes:\n return cluster_n\n\n return 16\n\n @staticmethod\n def _compute_threads_per_row(H_per_cta: int) -> int:\n \"\"\"Compute optimal threads per row.\"\"\"\n if H_per_cta <= 64:\n return 8\n elif H_per_cta <= 128:\n return 16\n elif H_per_cta <= 3072:\n return 32\n elif H_per_cta <= 6144:\n return 64\n elif H_per_cta <= 16384:\n return 128\n else:\n return 256\n\n @staticmethod\n def _compute_num_threads(H_per_cta: int) -> int:\n \"\"\"Compute total threads per block.\"\"\"\n return 128 if H_per_cta <= 16384 else 256\n\n @staticmethod\n def _estimate_smem_bytes(H: int, cluster_n: int, elem_size: int) -> int:\n \"\"\"Estimate shared memory bytes needed for given configuration.\n\n This is used to dynamically determine cluster_n based on device\n shared memory limits.\n \"\"\"\n H_per_cta = H // cluster_n\n threads_per_row = AddRMSNormFP4QuantKernel._compute_threads_per_row(H_per_cta)\n num_threads = AddRMSNormFP4QuantKernel._compute_num_threads(H_per_cta)\n rows_per_block = num_threads // threads_per_row\n warps_per_row = max(threads_per_row // 32, 1)\n\n vec_size = COPY_BITS // 8 // elem_size\n num_vec_blocks = max(\n 1, (H_per_cta // vec_size + threads_per_row - 1) // threads_per_row\n )\n cols_per_tile = vec_size * num_vec_blocks * threads_per_row\n\n tile_bytes = rows_per_block * cols_per_tile * elem_size\n\n if cluster_n == 1:\n # 4 tiles: sX, sR, sW, sH + reduction buffer\n return 4 * tile_bytes + rows_per_block * warps_per_row * 4\n else:\n # 2 tiles: sX, sR + larger reduction buffer + mbarrier\n return 2 * tile_bytes + rows_per_block * warps_per_row * cluster_n * 4 + 8\n\n @staticmethod\n def _make_tv_layout(\n threads_per_row: int,\n rows_per_block: int,\n vec_size: int,\n num_vec_blocks: int,\n ) -> tuple:\n \"\"\"Create Thread-Value layout for coalesced vectorized memory access.\"\"\"\n shape = (\n (threads_per_row, rows_per_block),\n (vec_size, num_vec_blocks),\n )\n stride = (\n (vec_size * rows_per_block, 1),\n (rows_per_block, rows_per_block * vec_size * threads_per_row),\n )\n return shape, stride\n\n def _smem_size_in_bytes(self) -> int:\n \"\"\"Calculate shared memory requirement.\"\"\"\n elem_size = self.dtype.width // 8\n x_tile_bytes = self.rows_per_block * self.cols_per_tile * elem_size\n r_tile_bytes = self.rows_per_block * self.cols_per_tile * elem_size\n\n if self.cluster_n == 1:\n w_tile_bytes = self.rows_per_block * self.cols_per_tile * elem_size\n h_tile_bytes = self.rows_per_block * self.cols_per_tile * elem_size\n reduction_bytes = self.rows_per_block * self.warps_per_row * 4\n else:\n w_tile_bytes = 0\n h_tile_bytes = 0\n reduction_bytes = (\n self.rows_per_block * self.warps_per_row * self.cluster_n * 4\n )\n\n mbar_bytes = 8 if self.cluster_n > 1 else 0\n\n return (\n x_tile_bytes\n + r_tile_bytes\n + w_tile_bytes\n + h_tile_bytes\n + reduction_bytes\n + mbar_bytes\n )\n\n @cute.jit\n def __call__(\n self,\n mX: cute.Tensor,\n mR: cute.Tensor,\n mW: cute.Tensor,\n mY: cute.Tensor,\n mS: cute.Tensor,\n mS_unswizzled: cute.Tensor,\n mYNorm: cute.Tensor,\n mGlobalScale: cute.Tensor,\n M: Int32,\n eps: Float32,\n enable_pdl: cutlass.Constexpr[bool],\n stream,\n ):\n \"\"\"Host function to launch the kernel.\n\n Takes tensors directly via TVM-FFI.\n - mX: Input tensor, shape (M, H), row-major (read-only)\n - mR: Residual tensor, shape (M, H), row-major (modified in-place to input + residual)\n - mW: Weight tensor, shape (H,)\n - mY: Output FP4 tensor, shape (M, H // 2), row-major (packed)\n - mS: Scale factor tensor, shape depends on swizzle mode\n - mS_unswizzled: Unswizzled scale factor tensor (used when output_both_sf_layouts=True)\n - mYNorm: Optional normed output tensor, flat 1D view of (M, H), same dtype as\n input (only written when output_norm=True; pass any dummy tensor otherwise)\n - mGlobalScale: Global scale tensor, shape (1,), float32\n \"\"\"\n\n tv_shape, tv_stride = self._make_tv_layout(\n self.threads_per_row,\n self.rows_per_block,\n self.vec_size,\n self.num_vec_blocks,\n )\n tv_layout = cute.make_layout(tv_shape, stride=tv_stride)\n tiler_mn = (self.rows_per_block, self.cols_per_tile)\n\n self.kernel(\n mX,\n mR,\n mW,\n mY,\n mS,\n mS_unswizzled,\n mYNorm,\n mGlobalScale,\n M,\n eps,\n enable_pdl,\n tv_layout,\n tiler_mn,\n ).launch(\n grid=[cute.ceil_div(M, self.rows_per_block), self.cluster_n, 1],\n block=[self.num_threads, 1, 1],\n cluster=[1, self.cluster_n, 1]\n if cutlass.const_expr(self.cluster_n > 1)\n else None,\n smem=self._smem_size_in_bytes(),\n stream=stream,\n use_pdl=enable_pdl,\n )\n\n @cute.kernel\n def kernel(\n self,\n mX: cute.Tensor,\n mR: cute.Tensor,\n mW: cute.Tensor,\n mY: cute.Tensor,\n mS: cute.Tensor,\n mS_unswizzled: cute.Tensor,\n mYNorm: cute.Tensor,\n mGlobalScale: cute.Tensor,\n M: Int32,\n eps: Float32,\n enable_pdl: cutlass.Constexpr[bool],\n tv_layout: cute.Layout,\n tiler_mn: cute.Shape,\n ):\n \"\"\"Device kernel with cluster sync and Half2 SIMD.\n\n Performs:\n 1. h = input + residual (writes h back to mR in-place)\n 2. y = h * rstd * w / global_scale = rmsnorm(h, w) / global_scale\n 3. quantizes y to FP4\n\n mGlobalScale contains the global scale value. The kernel reads it and\n computes 1/global_scale, which is multiplied with rstd to apply:\n y = h * rstd * w / global_scale = rmsnorm(h, w) / global_scale\n \"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n\n if enable_pdl:\n cute.arch.griddepcontrol_wait()\n bidx, _, _ = cute.arch.block_idx()\n\n H = self.H\n block_size = self.block_size\n num_sf_blocks_per_row = self.num_sf_blocks_per_row\n is_fp16 = self.is_fp16\n cluster_n = self.cluster_n\n\n if cutlass.const_expr(cluster_n > 1):\n cluster_y = cute.arch.block_idx()[1]\n else:\n cluster_y = cutlass.const_expr(0)\n\n threads_per_row = tv_layout.shape[0][0]\n warps_per_row = max(threads_per_row // 32, 1)\n rows_per_block = tiler_mn[0]\n\n lane_in_row = tidx % threads_per_row\n row_in_block = tidx // threads_per_row\n\n fp4_max_rcp = rcp_approx_ftz(Float32(FLOAT4_E2M1_MAX))\n\n # Allocate shared memory\n smem = cutlass.utils.SmemAllocator()\n\n sX = smem.allocate_tensor(\n mX.element_type,\n cute.make_ordered_layout(tiler_mn, order=(1, 0)),\n byte_alignment=16,\n )\n\n sR = smem.allocate_tensor(\n mR.element_type,\n cute.make_ordered_layout(tiler_mn, order=(1, 0)),\n byte_alignment=16,\n )\n\n if cutlass.const_expr(cluster_n == 1):\n sW = smem.allocate_tensor(\n mW.element_type,\n cute.make_ordered_layout(tiler_mn, order=(1, 0)),\n byte_alignment=16,\n )\n sH = smem.allocate_tensor(\n mX.element_type,\n cute.make_ordered_layout(tiler_mn, order=(1, 0)),\n byte_alignment=16,\n )\n\n if cutlass.const_expr(cluster_n == 1):\n reduction_buffer = smem.allocate_tensor(\n Float32,\n cute.make_layout((rows_per_block, warps_per_row)),\n byte_alignment=4,\n )\n mbar_ptr = None\n else:\n reduction_buffer = smem.allocate_tensor(\n Float32,\n cute.make_layout((rows_per_block, (warps_per_row, cluster_n))),\n byte_alignment=4,\n )\n mbar_ptr = smem.allocate_array(Int64, num_elems=1)\n\n # Initialize cluster\n if cutlass.const_expr(cluster_n > 1):\n if tidx == 0:\n cute.arch.mbarrier_init(mbar_ptr, 1)\n cute.arch.mbarrier_init_fence()\n cute.arch.cluster_arrive_relaxed()\n cute.arch.cluster_wait()\n\n # Create identity tensor\n idX = cute.make_identity_tensor(mX.shape)\n\n gX = cute.local_tile(mX, tiler_mn, (bidx, cluster_y))\n gR = cute.local_tile(mR, tiler_mn, (bidx, cluster_y))\n cX = cute.local_tile(idX, tiler_mn, (bidx, cluster_y))\n\n if cutlass.const_expr(cluster_n == 1):\n mW_expanded_layout = cute.prepend(\n mW.layout, cute.make_layout((tiler_mn[0],), stride=(0,))\n )\n mW_2d = cute.make_tensor(mW.iterator, mW_expanded_layout)\n gW = cute.local_tile(mW_2d, tiler_mn, (0, cluster_y))\n\n # TiledCopy for loads\n copy_atom_load_async = cute.make_copy_atom(\n cute.nvgpu.cpasync.CopyG2SOp(),\n mX.element_type,\n num_bits_per_copy=COPY_BITS,\n )\n\n # TiledCopy for stores (to write h back to residual)\n copy_atom_store = cute.make_copy_atom(\n cute.nvgpu.CopyUniversalOp(),\n mR.element_type,\n num_bits_per_copy=COPY_BITS,\n )\n\n tiled_copy_load = cute.make_tiled_copy(\n copy_atom_load_async, tv_layout, tiler_mn\n )\n tiled_copy_store = cute.make_tiled_copy(copy_atom_store, tv_layout, tiler_mn)\n\n thr_copy_X = tiled_copy_load.get_slice(tidx)\n thr_copy_R = tiled_copy_load.get_slice(tidx)\n thr_copy_R_store = tiled_copy_store.get_slice(tidx)\n\n tXgX = thr_copy_X.partition_S(gX)\n tXsX = thr_copy_X.partition_D(sX)\n tRgR = thr_copy_R.partition_S(gR)\n tRsR = thr_copy_R.partition_D(sR)\n tXcX = thr_copy_X.partition_S(cX)\n\n # Output partition for writing h back to residual (in-place update)\n tRgO = thr_copy_R_store.partition_D(gR)\n\n if cutlass.const_expr(cluster_n == 1):\n thr_copy_W = tiled_copy_load.get_slice(tidx)\n tWgW = thr_copy_W.partition_S(gW)\n tWsW = thr_copy_W.partition_D(sW)\n tHsH = thr_copy_X.partition_D(sH)\n\n tXrX = cute.make_fragment_like(tXgX)\n tRrR = cute.make_fragment_like(tRgR)\n tRrO = cute.make_fragment_like(tRgO) # Register fragment for residual output\n\n # Bounds checking\n tXpX = predicate_k(tXcX, limit=H)\n row_coord = tXcX[(0, 0), 0, 0]\n row_in_bounds = row_coord[0] < M\n\n # Phase 1: Async copy\n if row_in_bounds:\n cute.copy(copy_atom_load_async, tXgX, tXsX, pred=tXpX)\n cute.copy(copy_atom_load_async, tRgR, tRsR, pred=tXpX)\n\n if cutlass.const_expr(cluster_n == 1):\n cute.copy(copy_atom_load_async, tWgW, tWsW, pred=tXpX)\n\n cute.arch.cp_async_commit_group()\n cute.arch.cp_async_wait_group(0)\n\n # Phase 2: h = x + r and sum of squares\n cute.autovec_copy(tXsX, tXrX)\n cute.autovec_copy(tRsR, tRrR)\n\n x_vals = tXrX.load().to(Float32)\n r_vals = tRrR.load().to(Float32)\n\n h_vals = x_vals + r_vals\n h_sq = h_vals * h_vals\n\n # Store h to residual output registers (for in-place update of residual)\n tRrO.store(h_vals.to(self.dtype))\n\n if cutlass.const_expr(cluster_n == 1):\n h_elem = h_vals.to(mX.element_type)\n tHsH.store(h_elem)\n\n sum_sq = row_reduce(\n h_sq,\n cute.ReductionOp.ADD,\n threads_per_row,\n reduction_buffer,\n mbar_ptr,\n cluster_n,\n Float32(0.0),\n )\n\n mean_sq = sum_sq / H\n rstd = cute.math.rsqrt(mean_sq + eps, fastmath=True)\n\n # Read global_scale from device memory (CUDA graph compatible)\n # Note: global_scale is incorporated into the block scale, NOT applied to input\n global_scale_val = mGlobalScale[0]\n\n if cutlass.const_expr(cluster_n > 1):\n cute.arch.cluster_arrive_relaxed()\n cute.arch.cluster_wait()\n else:\n cute.arch.barrier()\n\n # Write h back to residual tensor (in-place update: residual = input + residual)\n if row_in_bounds:\n cute.copy(copy_atom_store, tRrO, tRgO, pred=tXpX)\n\n # In cluster mode, Phase 3 reads from mR across the FULL hidden dimension,\n # including slices written by other CTAs. We must ensure all CTAs' global\n # memory writes are visible before any CTA proceeds to Phase 3.\n if cutlass.const_expr(cluster_n > 1):\n cute.arch.fence_acq_rel_cluster()\n cute.arch.cluster_arrive_relaxed()\n cute.arch.cluster_wait()\n\n actual_row_idx = bidx * rows_per_block + row_in_block\n\n # Phase 3: RMSNorm + Quantize\n if actual_row_idx < M:\n num_sf_per_thread = (\n num_sf_blocks_per_row + threads_per_row - 1\n ) // threads_per_row\n\n for sf_iter in range(num_sf_per_thread):\n sf_idx = lane_in_row + sf_iter * threads_per_row\n\n if sf_idx < num_sf_blocks_per_row:\n block_start = sf_idx * block_size\n\n if cutlass.const_expr(block_size == 16):\n if cutlass.const_expr(cluster_n == 1):\n # Shared memory path - use helper functions\n h_f32 = load_f32_16_from_smem(sH, row_in_block, block_start)\n w_f32 = load_f32_16_from_smem(sW, row_in_block, block_start)\n y_f32, max_abs = compute_y_and_max_abs_f32(\n h_f32, w_f32, rstd\n )\n\n # E4M3: global_scale is incorporated into block scale\n scale_float = global_scale_val * max_abs * fp4_max_rcp\n scale_float = fmin_f32(\n scale_float, Float32(FLOAT8_E4M3_MAX)\n )\n scale_fp8_u32 = cvt_f32_to_e4m3(scale_float)\n scale_fp8 = Uint8(scale_fp8_u32 & Uint32(0xFF))\n inv_scale = (\n fp8_e4m3_to_f32_and_rcp(scale_fp8_u32)\n * global_scale_val\n )\n\n if cutlass.const_expr(self.output_both_sf_layouts):\n inner_k_idx = sf_idx % Int32(4)\n inner_m_idx = (actual_row_idx % Int32(128)) // Int32(32)\n outer_m_idx = actual_row_idx % Int32(32)\n k_tile_idx = sf_idx // Int32(4)\n m_tile_idx = actual_row_idx // Int32(128)\n m_tile_stride = self.num_k_tiles * self.k_tile_stride\n swizzled_offset = (\n m_tile_idx * m_tile_stride\n + k_tile_idx * self.k_tile_stride\n + outer_m_idx * Int32(16)\n + inner_m_idx * Int32(4)\n + inner_k_idx\n )\n mS[swizzled_offset] = scale_fp8\n mS_unswizzled[actual_row_idx, sf_idx] = scale_fp8\n elif cutlass.const_expr(self.output_swizzled):\n inner_k_idx = sf_idx % Int32(4)\n inner_m_idx = (actual_row_idx % Int32(128)) // Int32(32)\n outer_m_idx = actual_row_idx % Int32(32)\n k_tile_idx = sf_idx // Int32(4)\n m_tile_idx = actual_row_idx // Int32(128)\n m_tile_stride = self.num_k_tiles * self.k_tile_stride\n swizzled_offset = (\n m_tile_idx * m_tile_stride\n + k_tile_idx * self.k_tile_stride\n + outer_m_idx * Int32(16)\n + inner_m_idx * Int32(4)\n + inner_k_idx\n )\n mS[swizzled_offset] = scale_fp8\n else:\n mS[actual_row_idx, sf_idx] = scale_fp8\n\n packed64 = quantize_and_pack_16(y_f32, inv_scale)\n out_offset = block_start // 2\n out_ptr = get_ptr_as_int64(\n mY, actual_row_idx * (H // 2) + out_offset\n )\n st_global_u64(out_ptr, packed64)\n\n if cutlass.const_expr(self.output_norm):\n _store_y_norm_16(\n mYNorm,\n y_f32,\n actual_row_idx,\n block_start,\n H,\n is_fp16,\n )\n\n else:\n # Global memory path (cluster mode) - use helper functions\n # mR contains h = x + r, so load from mR\n h_h2, w_h2 = load_8_half2(\n mR, mW, actual_row_idx, block_start, H\n )\n\n if cutlass.const_expr(is_fp16):\n hw_h2 = half2_mul_8(h_h2, w_h2)\n max_hw = half2_max_abs_8(hw_h2)\n max_xw = hmax_to_f32(max_hw)\n y_f32 = half2_to_float16(hw_h2, rstd)\n else:\n hw_h2 = bfloat2_mul_8(h_h2, w_h2)\n max_hw = bfloat2_max_abs_8(hw_h2)\n max_xw = bfloat2_hmax_to_f32(max_hw)\n y_f32 = bfloat2_to_float16(hw_h2, rstd)\n\n max_abs = max_xw * rstd\n\n # E4M3: global_scale is incorporated into block scale\n scale_float = global_scale_val * max_abs * fp4_max_rcp\n scale_float = fmin_f32(\n scale_float, Float32(FLOAT8_E4M3_MAX)\n )\n scale_fp8_u32 = cvt_f32_to_e4m3(scale_float)\n scale_fp8 = Uint8(scale_fp8_u32 & Uint32(0xFF))\n inv_scale = (\n fp8_e4m3_to_f32_and_rcp(scale_fp8_u32)\n * global_scale_val\n )\n\n if cutlass.const_expr(self.output_both_sf_layouts):\n inner_k_idx = sf_idx % Int32(4)\n inner_m_idx = (actual_row_idx % Int32(128)) // Int32(32)\n outer_m_idx = actual_row_idx % Int32(32)\n k_tile_idx = sf_idx // Int32(4)\n m_tile_idx = actual_row_idx // Int32(128)\n m_tile_stride = self.num_k_tiles * self.k_tile_stride\n swizzled_offset = (\n m_tile_idx * m_tile_stride\n + k_tile_idx * self.k_tile_stride\n + outer_m_idx * Int32(16)\n + inner_m_idx * Int32(4)\n + inner_k_idx\n )\n mS[swizzled_offset] = scale_fp8\n mS_unswizzled[actual_row_idx, sf_idx] = scale_fp8\n elif cutlass.const_expr(self.output_swizzled):\n inner_k_idx = sf_idx % Int32(4)\n inner_m_idx = (actual_row_idx % Int32(128)) // Int32(32)\n outer_m_idx = actual_row_idx % Int32(32)\n k_tile_idx = sf_idx // Int32(4)\n m_tile_idx = actual_row_idx // Int32(128)\n m_tile_stride = self.num_k_tiles * self.k_tile_stride\n swizzled_offset = (\n m_tile_idx * m_tile_stride\n + k_tile_idx * self.k_tile_stride\n + outer_m_idx * Int32(16)\n + inner_m_idx * Int32(4)\n + inner_k_idx\n )\n mS[swizzled_offset] = scale_fp8\n else:\n mS[actual_row_idx, sf_idx] = scale_fp8\n\n packed64 = quantize_and_pack_16(y_f32, inv_scale)\n out_offset = block_start // 2\n out_ptr = get_ptr_as_int64(\n mY, actual_row_idx * (H // 2) + out_offset\n )\n st_global_u64(out_ptr, packed64)\n\n if cutlass.const_expr(self.output_norm):\n _store_y_norm_16(\n mYNorm,\n y_f32,\n actual_row_idx,\n block_start,\n H,\n is_fp16,\n )\n\n else:\n # block_size == 32 (MXFP4) - process in two chunks of 16\n if cutlass.const_expr(cluster_n == 1):\n # Shared memory path - use helper functions\n # Load and compute first 16 elements\n h_f32_c0 = load_f32_16_from_smem(\n sH, row_in_block, block_start\n )\n w_f32_c0 = load_f32_16_from_smem(\n sW, row_in_block, block_start\n )\n y_f32_c0, max_abs_c0 = compute_y_and_max_abs_f32(\n h_f32_c0, w_f32_c0, rstd\n )\n\n # Load and compute second 16 elements\n h_f32_c1 = load_f32_16_from_smem(\n sH, row_in_block, block_start + Int32(16)\n )\n w_f32_c1 = load_f32_16_from_smem(\n sW, row_in_block, block_start + Int32(16)\n )\n y_f32_c1, max_abs_c1 = compute_y_and_max_abs_f32(\n h_f32_c1, w_f32_c1, rstd\n )\n\n # Combine max_abs from both chunks\n max_abs = fmax_f32(max_abs_c0, max_abs_c1)\n\n # Compute scale factor (E4M3 or UE8M0)\n if cutlass.const_expr(self.scale_format == \"ue8m0\"):\n scale_float = max_abs * fp4_max_rcp\n scale_ue8m0 = cvt_f32_to_ue8m0(scale_float)\n scale_u8 = Uint8(scale_ue8m0 & Uint32(0xFF))\n inv_scale = ue8m0_to_output_scale(scale_ue8m0)\n else:\n scale_float = global_scale_val * max_abs * fp4_max_rcp\n scale_float = fmin_f32(\n scale_float, Float32(FLOAT8_E4M3_MAX)\n )\n scale_fp8_u32 = cvt_f32_to_e4m3(scale_float)\n scale_u8 = Uint8(scale_fp8_u32 & Uint32(0xFF))\n inv_scale = (\n fp8_e4m3_to_f32_and_rcp(scale_fp8_u32)\n * global_scale_val\n )\n\n if cutlass.const_expr(self.output_both_sf_layouts):\n inner_k_idx = sf_idx % Int32(4)\n inner_m_idx = (actual_row_idx % Int32(128)) // Int32(32)\n outer_m_idx = actual_row_idx % Int32(32)\n k_tile_idx = sf_idx // Int32(4)\n m_tile_idx = actual_row_idx // Int32(128)\n m_tile_stride = self.num_k_tiles * self.k_tile_stride\n swizzled_offset = (\n m_tile_idx * m_tile_stride\n + k_tile_idx * self.k_tile_stride\n + outer_m_idx * Int32(16)\n + inner_m_idx * Int32(4)\n + inner_k_idx\n )\n mS[swizzled_offset] = scale_u8\n mS_unswizzled[actual_row_idx, sf_idx] = scale_u8\n elif cutlass.const_expr(self.output_swizzled):\n inner_k_idx = sf_idx % Int32(4)\n inner_m_idx = (actual_row_idx % Int32(128)) // Int32(32)\n outer_m_idx = actual_row_idx % Int32(32)\n k_tile_idx = sf_idx // Int32(4)\n m_tile_idx = actual_row_idx // Int32(128)\n m_tile_stride = self.num_k_tiles * self.k_tile_stride\n swizzled_offset = (\n m_tile_idx * m_tile_stride\n + k_tile_idx * self.k_tile_stride\n + outer_m_idx * Int32(16)\n + inner_m_idx * Int32(4)\n + inner_k_idx\n )\n mS[swizzled_offset] = scale_u8\n else:\n mS[actual_row_idx, sf_idx] = scale_u8\n\n # Quantize and store both chunks\n packed64_c0 = quantize_and_pack_16(y_f32_c0, inv_scale)\n packed64_c1 = quantize_and_pack_16(y_f32_c1, inv_scale)\n\n fp4_offset = actual_row_idx * (H // 2) + sf_idx * (\n block_size // 2\n )\n fp4_ptr_0 = get_ptr_as_int64(mY, fp4_offset)\n fp4_ptr_1 = get_ptr_as_int64(mY, fp4_offset + Int32(8))\n st_global_u64(fp4_ptr_0, packed64_c0)\n st_global_u64(fp4_ptr_1, packed64_c1)\n\n if cutlass.const_expr(self.output_norm):\n _store_y_norm_16(\n mYNorm,\n y_f32_c0,\n actual_row_idx,\n block_start,\n H,\n is_fp16,\n )\n _store_y_norm_16(\n mYNorm,\n y_f32_c1,\n actual_row_idx,\n block_start + Int32(16),\n H,\n is_fp16,\n )\n\n else:\n # Global memory path (cluster mode) - use helper functions\n # mR contains h = x + r, load in two chunks\n h_h2_c0, w_h2_c0 = load_8_half2(\n mR, mW, actual_row_idx, block_start, H\n )\n h_h2_c1, w_h2_c1 = load_8_half2(\n mR, mW, actual_row_idx, block_start + Int32(16), H\n )\n\n if cutlass.const_expr(is_fp16):\n hw_h2_c0 = half2_mul_8(h_h2_c0, w_h2_c0)\n hw_h2_c1 = half2_mul_8(h_h2_c1, w_h2_c1)\n max_c0_h2 = half2_max_abs_8(hw_h2_c0)\n max_c1_h2 = half2_max_abs_8(hw_h2_c1)\n max_hw = hmax2(max_c0_h2, max_c1_h2)\n max_xw = hmax_to_f32(max_hw)\n y_f32_c0 = half2_to_float16(hw_h2_c0, rstd)\n y_f32_c1 = half2_to_float16(hw_h2_c1, rstd)\n else:\n hw_h2_c0 = bfloat2_mul_8(h_h2_c0, w_h2_c0)\n hw_h2_c1 = bfloat2_mul_8(h_h2_c1, w_h2_c1)\n max_c0_h2 = bfloat2_max_abs_8(hw_h2_c0)\n max_c1_h2 = bfloat2_max_abs_8(hw_h2_c1)\n max_hw = bfloat2_hmax2(max_c0_h2, max_c1_h2)\n max_xw = bfloat2_hmax_to_f32(max_hw)\n y_f32_c0 = bfloat2_to_float16(hw_h2_c0, rstd)\n y_f32_c1 = bfloat2_to_float16(hw_h2_c1, rstd)\n\n max_abs = max_xw * rstd\n\n # Compute scale factor (E4M3 or UE8M0)\n if cutlass.const_expr(self.scale_format == \"ue8m0\"):\n scale_float = max_abs * fp4_max_rcp\n scale_ue8m0 = cvt_f32_to_ue8m0(scale_float)\n scale_u8 = Uint8(scale_ue8m0 & Uint32(0xFF))\n inv_scale = ue8m0_to_output_scale(scale_ue8m0)\n else:\n scale_float = global_scale_val * max_abs * fp4_max_rcp\n scale_float = fmin_f32(\n scale_float, Float32(FLOAT8_E4M3_MAX)\n )\n scale_fp8_u32 = cvt_f32_to_e4m3(scale_float)\n scale_u8 = Uint8(scale_fp8_u32 & Uint32(0xFF))\n inv_scale = (\n fp8_e4m3_to_f32_and_rcp(scale_fp8_u32)\n * global_scale_val\n )\n\n if cutlass.const_expr(self.output_both_sf_layouts):\n inner_k_idx = sf_idx % Int32(4)\n inner_m_idx = (actual_row_idx % Int32(128)) // Int32(32)\n outer_m_idx = actual_row_idx % Int32(32)\n k_tile_idx = sf_idx // Int32(4)\n m_tile_idx = actual_row_idx // Int32(128)\n m_tile_stride = self.num_k_tiles * self.k_tile_stride\n swizzled_offset = (\n m_tile_idx * m_tile_stride\n + k_tile_idx * self.k_tile_stride\n + outer_m_idx * Int32(16)\n + inner_m_idx * Int32(4)\n + inner_k_idx\n )\n mS[swizzled_offset] = scale_u8\n mS_unswizzled[actual_row_idx, sf_idx] = scale_u8\n elif cutlass.const_expr(self.output_swizzled):\n inner_k_idx = sf_idx % Int32(4)\n inner_m_idx = (actual_row_idx % Int32(128)) // Int32(32)\n outer_m_idx = actual_row_idx % Int32(32)\n k_tile_idx = sf_idx // Int32(4)\n m_tile_idx = actual_row_idx // Int32(128)\n m_tile_stride = self.num_k_tiles * self.k_tile_stride\n swizzled_offset = (\n m_tile_idx * m_tile_stride\n + k_tile_idx * self.k_tile_stride\n + outer_m_idx * Int32(16)\n + inner_m_idx * Int32(4)\n + inner_k_idx\n )\n mS[swizzled_offset] = scale_u8\n else:\n mS[actual_row_idx, sf_idx] = scale_u8\n\n # Quantize and store both chunks\n packed64_c0 = quantize_and_pack_16(y_f32_c0, inv_scale)\n packed64_c1 = quantize_and_pack_16(y_f32_c1, inv_scale)\n\n fp4_offset = actual_row_idx * (H // 2) + sf_idx * (\n block_size // 2\n )\n fp4_ptr_0 = get_ptr_as_int64(mY, fp4_offset)\n fp4_ptr_1 = get_ptr_as_int64(mY, fp4_offset + Int32(8))\n st_global_u64(fp4_ptr_0, packed64_c0)\n st_global_u64(fp4_ptr_1, packed64_c1)\n\n if cutlass.const_expr(self.output_norm):\n _store_y_norm_16(\n mYNorm,\n y_f32_c0,\n actual_row_idx,\n block_start,\n H,\n is_fp16,\n )\n _store_y_norm_16(\n mYNorm,\n y_f32_c1,\n actual_row_idx,\n block_start + Int32(16),\n H,\n is_fp16,\n )\n\n if enable_pdl:\n cute.arch.griddepcontrol_launch_dependents()\n\n\n# =============================================================================\n# PyTorch API Functions\n# =============================================================================\n\n\n@functools.cache\ndef _get_compiled_kernel(\n hidden_size: int,\n block_size: int,\n is_fp16: bool,\n sm_version: int,\n scale_format: str,\n is_sf_swizzled_layout: bool,\n output_both_sf_layouts: bool = False,\n enable_pdl: bool = False,\n output_norm: bool = False,\n) -> Callable:\n \"\"\"\n Get a compiled kernel closure that takes torch.Tensor directly.\n\n Uses TVM-FFI for efficient tensor passing without manual pointer construction.\n \"\"\"\n cutlass_dtype = cutlass.Float16 if is_fp16 else cutlass.BFloat16\n\n kernel_obj = AddRMSNormFP4QuantKernel(\n dtype=cutlass_dtype,\n H=hidden_size,\n block_size=block_size,\n output_swizzled=is_sf_swizzled_layout,\n is_fp16=is_fp16,\n sm_version=sm_version,\n scale_format=scale_format,\n output_both_sf_layouts=output_both_sf_layouts,\n output_norm=output_norm,\n )\n\n # Use symbolic size for dynamic M dimension\n sym_m = cute.sym_int()\n\n # Create fake tensors for compilation with TVM-FFI\n # Use stride_order=(1, 0) for row-major layout and assumed_align=128 for async copy\n x_fake = cute.runtime.make_fake_compact_tensor(\n cutlass_dtype, (sym_m, hidden_size), stride_order=(1, 0), assumed_align=128\n )\n r_fake = cute.runtime.make_fake_compact_tensor(\n cutlass_dtype, (sym_m, hidden_size), stride_order=(1, 0), assumed_align=128\n )\n w_fake = cute.runtime.make_fake_compact_tensor(\n cutlass_dtype, (hidden_size,), assumed_align=128\n )\n y_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_m, hidden_size // 2), stride_order=(1, 0), assumed_align=128\n )\n\n # Scale factor tensor layout depends on swizzle mode or output_both_sf_layouts\n if is_sf_swizzled_layout or output_both_sf_layouts:\n # For swizzled mode, use 1D layout - the swizzle pattern is computed in kernel\n # Size is: num_m_tiles * num_k_tiles * 512, which is independent of M\n # Use a separate symbolic variable for this size\n sym_swizzled_size = cute.sym_int()\n s_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_swizzled_size,), assumed_align=128\n )\n else:\n # For non-swizzled mode, use 2D row-major layout\n s_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (sym_m, hidden_size // block_size),\n stride_order=(1, 0),\n assumed_align=128,\n )\n\n # Unswizzled scale factor tensor (always 2D row-major, used when output_both_sf_layouts=True)\n s_unswizzled_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (sym_m, hidden_size // block_size),\n stride_order=(1, 0),\n assumed_align=128,\n )\n\n # Optional normed output tensor (flat 1D view of (M, hidden_size)).\n # Uses an independent symbolic size so a small dummy tensor can be passed\n # when output_norm=False (the kernel never touches it in that case).\n sym_ynorm_size = cute.sym_int()\n ynorm_fake = cute.runtime.make_fake_compact_tensor(\n cutlass_dtype, (sym_ynorm_size,), assumed_align=16\n )\n\n # Create fake stream that uses environment stream at runtime\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n\n # Global scale fake tensor (shape [1], float32)\n global_scale_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32, (1,), assumed_align=4\n )\n\n # Compile with TVM-FFI enabled\n compiled_kernel = cute.compile(\n kernel_obj,\n x_fake,\n r_fake,\n w_fake,\n y_fake,\n s_fake,\n s_unswizzled_fake,\n ynorm_fake,\n global_scale_fake,\n Int32(1), # Dummy M\n Float32(1e-6), # Dummy eps\n enable_pdl,\n stream_fake,\n options=\"--enable-tvm-ffi\",\n )\n\n def tensor_api(\n x: torch.Tensor,\n r: torch.Tensor,\n w: torch.Tensor,\n y: torch.Tensor,\n s: torch.Tensor,\n s_unswizzled: torch.Tensor,\n y_norm: torch.Tensor,\n global_scale: torch.Tensor,\n M: int,\n eps: float,\n ) -> None:\n \"\"\"Runtime API that passes torch tensors directly via TVM-FFI.\"\"\"\n nonlocal compiled_kernel\n # For swizzled mode or output_both_sf_layouts, flatten the scale tensor to 1D\n s_tensor = (\n s.flatten()\n if (is_sf_swizzled_layout or output_both_sf_layouts)\n else s.contiguous()\n )\n # View y as uint8 since kernel expects uint8 but caller may pass float4_e2m1fn_x2\n y_uint8 = y.view(torch.uint8)\n compiled_kernel(\n x,\n r,\n w,\n y_uint8,\n s_tensor,\n s_unswizzled.contiguous(),\n y_norm,\n global_scale,\n M,\n eps,\n )\n\n return tensor_api\n\n\n@flashinfer_api(trace=add_rmsnorm_fp4quant_trace_dispatch)\ndef add_rmsnorm_fp4quant(\n input: torch.Tensor,\n residual: torch.Tensor,\n weight: torch.Tensor,\n y_fp4: torch.Tensor | None = None,\n block_scale: torch.Tensor | None = None,\n global_scale: torch.Tensor | None = None,\n eps: float = 1e-6,\n block_size: int = 16,\n scale_format: str | None = None,\n is_sf_swizzled_layout: bool = False,\n output_both_sf_layouts: bool = False,\n block_scale_unswizzled: torch.Tensor | None = None,\n enable_pdl: bool | None = None,\n y_out: torch.Tensor | None = None,\n) -> Union[\n Tuple[torch.Tensor, torch.Tensor], Tuple[torch.Tensor, torch.Tensor, torch.Tensor]\n]:\n \"\"\"\n Fused Add + RMS normalization + FP4 quantization using CuTe-DSL.\n\n Computes:\n 1. ``residual = residual + input`` (in-place update)\n 2. ``y = RMSNorm(residual) * weight``\n 3. Optionally applies global scaling (``y = y / global_scale``)\n 4. Quantizes ``y`` to FP4\n\n The residual tensor is modified in-place to contain the fused value.\n\n Parameters\n ----------\n input : torch.Tensor\n Input tensor, shape ``(batch_size, hidden_size)`` or ``(batch_size, seq_len, hidden_size)``.\n Must be ``torch.float16`` or ``torch.bfloat16``. Read-only.\n residual : torch.Tensor\n Residual tensor. Must have the same shape and dtype as ``input``.\n **Modified in-place** to contain ``residual + input``.\n weight : torch.Tensor\n Weight tensor for RMSNorm, shape ``(hidden_size,)``.\n Must have the same dtype as input.\n y_fp4 : torch.Tensor, optional\n Output tensor for quantized values in FP4_E2M1 format with dtype\n ``torch.float4_e2m1fn_x2``.\n Shape must be ``(batch_size, hidden_size // 2)`` or matching 3D input.\n If ``None``, will be allocated automatically.\n block_scale : torch.Tensor, optional\n Output tensor for per-block scale factors.\n\n - If ``is_sf_swizzled_layout=False`` and ``output_both_sf_layouts=False``: row-major\n layout with shape ``(batch_size, hidden_size // block_size)`` or matching 3D input.\n - If ``is_sf_swizzled_layout=True`` or ``output_both_sf_layouts=True``: swizzled layout\n for efficient tensor core access, with shape\n ``(batch_size * hidden_size // block_size,)`` flattened.\n The swizzle pattern uses 128x4 tiles where scales are arranged as:\n ``[m_tile][k_tile][outer_m (32)][inner_m (4)][inner_k (4)]``.\n\n Dtype should be ``torch.float8_e4m3fn`` for E4M3 format or ``torch.uint8``\n for UE8M0 format. If ``None``, will be allocated automatically.\n global_scale : torch.Tensor, optional\n Global scale factor tensor of shape ``(1,)`` with dtype ``torch.float32``.\n If provided, the RMSNorm output is divided by this value before quantization:\n ``y = rmsnorm(h, w) / global_scale`` where ``h = input + residual``.\n This is used for NVFP4 format where a pre-computed global scale lifts\n per-block scales into optimal dynamic range.\n If ``None``, no global scaling is applied (equivalent to global_scale=1.0).\n eps : float\n Epsilon for numerical stability in RMSNorm. Default is ``1e-6``.\n block_size : int\n Number of elements per quantization block. Default is ``16``.\n\n - ``16``: NVFP4 format with E4M3 scale factors\n - ``32``: MXFP4 format with UE8M0 scale factors\n scale_format : str, optional\n Scale factor format: ``\"e4m3\"`` or ``\"ue8m0\"``.\n If ``None``, auto-selects based on ``block_size``:\n ``\"e4m3\"`` for block_size=16, ``\"ue8m0\"`` for block_size=32.\n is_sf_swizzled_layout : bool\n If ``True``, output scale factors in swizzled layout optimized for\n tensor core GEMM operations. The swizzle uses 128x4 tiles with the pattern:\n ``[m_tile_idx * k_tiles * 512 + k_tile_idx * 512 + outer_m * 16 + inner_m * 4 + inner_k]``\n where ``outer_m = row % 32``, ``inner_m = (row % 128) // 32``, etc.\n Default is ``False`` (row-major layout).\n Note: This parameter is ignored when ``output_both_sf_layouts=True``.\n output_both_sf_layouts : bool\n If ``True``, return both swizzled and unswizzled scale factors.\n When enabled, ``block_scale`` contains the swizzled layout and\n ``block_scale_unswizzled`` contains the row-major layout.\n This overrides ``is_sf_swizzled_layout``.\n Default is ``False``.\n block_scale_unswizzled : torch.Tensor, optional\n Output tensor for unswizzled per-block scale factors (row-major layout).\n Only used when ``output_both_sf_layouts=True``.\n Shape is ``(batch_size, hidden_size // block_size)`` or matching 3D input.\n Dtype should be ``torch.float8_e4m3fn`` for E4M3 format or ``torch.uint8``\n for UE8M0 format. If ``None``, will be allocated automatically when\n ``output_both_sf_layouts=True``.\n enable_pdl : bool, optional\n Whether to launch with Programmatic Dependent Launch (PDL). When\n ``None`` (default) or ``True``, PDL is enabled only if the current\n device supports it (probed via :func:`device_support_pdl`). Pass\n ``False`` to force-disable. See\n https://docs.nvidia.com/cuda/cuda-c-programming-guide/#programmatic-dependent-launch-and-synchronization\n y_out : torch.Tensor, optional\n Optional output tensor for the normed (pre-quantization) values\n ``y = RMSNorm(input + residual) * weight`` in the input dtype\n (fp16/bf16). Shape must be ``(batch_size, hidden_size)`` or matching\n 3D input, contiguous. **Written in place**; the return value of this\n function is unchanged (same tuple arity as without ``y_out``).\n When ``None`` (default), the normed values are not materialized and\n the generated kernel is identical to the baseline (the presence of\n ``y_out`` is a compile-time specialization).\n\n Returns\n -------\n Union[Tuple[torch.Tensor, torch.Tensor], Tuple[torch.Tensor, torch.Tensor, torch.Tensor]]\n When ``output_both_sf_layouts=False``:\n A tuple of ``(y_fp4, block_scale)``:\n\n - ``y_fp4``: Quantized FP4 values packed as uint8.\n - ``block_scale``: Per-block scale factors (swizzled or row-major based on\n ``is_sf_swizzled_layout``).\n\n When ``output_both_sf_layouts=True``:\n A tuple of ``(y_fp4, block_scale, block_scale_unswizzled)``:\n\n - ``y_fp4``: Quantized FP4 values packed as uint8.\n - ``block_scale``: Per-block scale factors in swizzled layout.\n - ``block_scale_unswizzled``: Per-block scale factors in row-major layout.\n\n Notes\n -----\n - Requires SM100+ (Blackwell) for FP4 quantization PTX intrinsics.\n - For block_size=16 (NVFP4): uses E4M3 scale factors (max value 448.0).\n - For block_size=32 (MXFP4): uses UE8M0 scale factors (power-of-2 scales).\n - FP4 E2M1 format has a max representable value of 6.0.\n \"\"\"\n _require_cute_dsl_arch_for(input.device)\n is_3d = input.dim() == 3\n if is_3d:\n B, S, H = input.shape\n input_2d = input.view(B * S, H).contiguous()\n residual_2d = residual.view(B * S, H).contiguous()\n else:\n input_2d = input\n residual_2d = residual\n\n batch_size, hidden_size = input_2d.shape\n dtype = input.dtype\n\n assert hidden_size % block_size == 0, \"hidden_size must be divisible by block_size\"\n assert hidden_size >= 64, \"hidden_size must be >= 64\"\n assert block_size in [16, 32], \"block_size must be 16 or 32\"\n\n is_fp16 = dtype == torch.float16\n actual_scale_format = (\n scale_format if scale_format else (\"ue8m0\" if block_size == 32 else \"e4m3\")\n )\n sm_version = get_sm_version(input.device)\n\n if enable_pdl is None or enable_pdl:\n enable_pdl = device_support_pdl(input.device)\n\n # Determine scale dtype based on format\n scale_dtype = torch.uint8 if actual_scale_format == \"ue8m0\" else torch.float8_e4m3fn\n num_sf_blocks_per_row = hidden_size // block_size\n\n # Allocate output tensors if not provided\n if y_fp4 is None:\n if is_3d:\n y_fp4 = torch.empty(\n (B, S, hidden_size // 2),\n dtype=torch.float4_e2m1fn_x2,\n device=input.device,\n )\n else:\n y_fp4 = torch.empty(\n (batch_size, hidden_size // 2),\n dtype=torch.float4_e2m1fn_x2,\n device=input.device,\n )\n\n if block_scale is None:\n # When output_both_sf_layouts=True, block_scale is always swizzled\n if is_sf_swizzled_layout or output_both_sf_layouts:\n # Swizzled layout: flattened with 128x4 tile pattern\n num_m_tiles = (batch_size + 127) // 128\n num_k_tiles = (num_sf_blocks_per_row + 3) // 4\n k_tile_stride = 512\n swizzled_size = num_m_tiles * num_k_tiles * k_tile_stride\n block_scale = torch.empty(\n (swizzled_size,), dtype=scale_dtype, device=input.device\n )\n else:\n if is_3d:\n block_scale = torch.empty(\n (B, S, num_sf_blocks_per_row),\n dtype=scale_dtype,\n device=input.device,\n )\n else:\n block_scale = torch.empty(\n (batch_size, num_sf_blocks_per_row),\n dtype=scale_dtype,\n device=input.device,\n )\n\n # Allocate unswizzled scale factor tensor\n # When output_both_sf_layouts=False, we still need a correctly-shaped tensor\n # for TVM-FFI validation, even though the kernel won't write to it\n if block_scale_unswizzled is None:\n if is_3d:\n block_scale_unswizzled = torch.empty(\n (B, S, num_sf_blocks_per_row),\n dtype=scale_dtype,\n device=input.device,\n )\n else:\n block_scale_unswizzled = torch.empty(\n (batch_size, num_sf_blocks_per_row),\n dtype=scale_dtype,\n device=input.device,\n )\n\n # Get 2D views for kernel\n if is_3d:\n y_fp4_2d = y_fp4.view(B * S, -1)\n block_scale_2d = (\n block_scale.view(B * S, -1)\n if not (is_sf_swizzled_layout or output_both_sf_layouts)\n else block_scale\n )\n # Always convert to 2D for kernel call\n block_scale_unswizzled_2d = block_scale_unswizzled.view(B * S, -1)\n else:\n y_fp4_2d = y_fp4\n block_scale_2d = block_scale\n block_scale_unswizzled_2d = block_scale_unswizzled\n\n # Create global_scale tensor if not provided (1.0 = no scaling)\n if global_scale is None:\n global_scale = torch.ones(1, dtype=torch.float32, device=input.device)\n\n # Optional normed (bf16/fp16) output — compile-time specialization\n output_norm = y_out is not None\n weight_contig = weight.contiguous()\n if output_norm:\n assert y_out.dtype == dtype, (\n f\"y_out dtype {y_out.dtype} must match input dtype {dtype}\"\n )\n assert y_out.device == input.device, (\n f\"y_out device {y_out.device} must match input device {input.device}\"\n )\n assert y_out.is_contiguous(), \"y_out must be contiguous\"\n assert y_out.shape == input.shape, (\n f\"y_out shape {tuple(y_out.shape)} must match the input shape \"\n f\"{tuple(input.shape)} (same (batch, hidden) or 3D layout)\"\n )\n assert y_out.data_ptr() % 16 == 0, \"y_out must be 16-byte aligned\"\n y_norm_arg = y_out.view(-1)\n else:\n # Dummy tensor; the kernel never reads or writes it when\n # output_norm=False (the store is compiled out).\n y_norm_arg = weight_contig\n\n tensor_api = _get_compiled_kernel(\n hidden_size,\n block_size,\n is_fp16,\n sm_version,\n actual_scale_format,\n is_sf_swizzled_layout,\n output_both_sf_layouts,\n enable_pdl,\n output_norm,\n )\n tensor_api(\n input_2d.contiguous(),\n residual_2d.contiguous(),\n weight_contig,\n y_fp4_2d,\n block_scale_2d.view(torch.uint8),\n block_scale_unswizzled_2d.view(torch.uint8),\n y_norm_arg,\n global_scale.contiguous(),\n batch_size,\n eps,\n )\n\n if output_both_sf_layouts:\n return y_fp4, block_scale, block_scale_unswizzled\n else:\n return y_fp4, block_scale\n\n\n__all__ = [\n \"AddRMSNormFP4QuantKernel\",\n \"add_rmsnorm_fp4quant\",\n \"get_sm_version\",\n]\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\n This PR improves the fused add + RMSNorm + FP4 quantization kernel by:\n\n - Deriving row parallelism from the number of FP4 scale-factor blocks.\n - Using vectorized shared-memory loads and packed BF16/FP16 operations for the block-size-16 single-CTA path.\n\n## Benchmark\n\n BF16, block size 16, E4M3 scales, swizzled scale layout, CUDA Graph.\n\n Shapes:\n\n - M: 1–1024, powers of two\n - H: 1024–7168, step 1024\n - 77 shapes per GPU\n\n The unfused baseline includes both the Inductor-compiled add + RMSNorm and the CUDA FP4 conversion.\n\n## 🔍 Related Issues\n\nvs. unfused\n<img width=\"1740\" height=\"675\" alt=\"fp4-full-current-vs-unfused-20260808\" src=\"https://github.com/user-attachments/assets/bb6b68c3-4ba9-42f5-8b8c-9031661fd505\" />\n\n\nvs. main change\n<img width=\"1740\" height=\"675\" alt=\"fp4-full-current-vs-main-20260808\" src=\"https://github.com/user-attachments/assets/4d005223-64ef-4883-8faa-7be89fe2cc75\" />\n\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [ ] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [ ] I have installed the hooks with `pre-commit install`.\n- [ ] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [ ] Tests have been added or updated as needed.\n- [ ] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc. -->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n## Performance\n* Improved NVFP4 RMSNorm quantization efficiency through faster packed data processing.\n* Reduced unnecessary shared-memory conversions for improved execution speed.\n\n## Compatibility\n* Improved support for varying block sizes and workload dimensions.\n* Enhanced handling of FP16 and BF16 input data.\n* Added support for offline launch-configuration selection.\n\n## Reliability\n* Improved resource sizing for threads, clusters, and shared memory.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1092,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"29196cf437778906c72630dc5d9850de547501de"},"date":{"kind":"string","value":"2026-08-08T23:41:33+08:00"},"pr_number":{"kind":"number","value":4331,"string":"4,331"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/4331"},"title":{"kind":"string","value":"perf(moe): persist b12x MoE CuTe-DSL kernels to the disk cache (#4331)"},"message":{"kind":"string","value":"perf(moe): persist b12x MoE CuTe-DSL kernels to the disk cache (#4331)\n\n## 📌 Description\n\nRolls the on-disk CuTe-DSL kernel cache out to the three sm12x NVFP4\nfused-MoE kernels (micro,\nstatic, dynamic), addressing #4317. The infrastructure landed in #3874 /\n#4029; @bkryu noted in\n#4317 that it still had to reach individual kernels and that the core\nteam lacked bandwidth, so this\napplies it to b12x MoE.\n\nFollows the rollout note in `docs/design_docs/cute_dsl_kernel_cache.md`:\neach `cute.compile` becomes\na closure passed to `build_and_load_cute_dsl_kernel`. The three\ncache-key tuples become named\nfunctions so both cache levels derive from one source of truth, and the\nartifact name appends a\ndigest of that tuple — the keys hold floats and `None` (`swiglu_*`), and\n`1.5` / `-1.5` both sanitize\nto `1_5`, so a formatted name would not be injective.\n\nAs in the existing adopters, the kernels now compile against\n`make_fake_stream(use_tvm_ffi_env_stream=True)`, so TVM-FFI supplies the\ncaller's current stream and\nthe two launch sites no longer pass one (compiled signatures: 24 / 24 /\n32 parameters).\n\n**Not covered:** the direct-micro kernel\n(`compile_direct_micro_kernel`), which this module started\ndispatching to recently. It compiles without `--enable-tvm-ffi` and\nlaunches through the DSL rather\nthan a TVM-FFI callable, so caching it is a separate change — #4317 is\nonly partly closed by this PR.\n\n### Measured — GB10 (sm_121), DSL 4.6.0, five kernel shapes per process\n\n| process | total compile + load |\n|---|---:|\n| before, two runs | 17.92 s / 17.95 s |\n| after, cold first run | 18.91 s |\n| after, two later runs | **0.130 s / 0.134 s** (~135×) |\n\nWarm, per kernel: dynamic 7.7 s → 1 ms; static 3.2 s → 1 ms; micro\n2.3–3.2 s → 1 ms (the first warm\nkernel pays 0.13 s of one-off module setup). The cold run costs a few\npercent for the export.\nArtifacts are 161–262 KB each.\n\n## 🔍 Related Issues\n\n#4317 (partly — see the scope note above). Builds on the cache\ninfrastructure from #3874 and #4029.\n\n## 🚀 Pull Request Checklist\n\n### ✅ Pre-commit Checks\n\n- [x] `pre-commit` installed.\n- [x] Hooks installed.\n- [x] `pre-commit run` on the two changed files: all hooks pass, no\nfiles modified. (I ran it\nfile-scoped rather than `--all-files`, since the remaining hooks are\nrepo-wide.)\n\n## 🧪 Tests\n\n- [x] Tests added.\n- [x] The new tests pass; see the caveat below for what does not run on\nmy hardware.\n\n- New `tests/moe/test_b12x_moe_kernel_cache.py`: 61 naming-contract\ntests — signature coverage,\nper-argument perturbation, symbol safety, cross-family collision —\nreplicating\n`tests/jit/test_cute_dsl_cache.py` as the design doc asks of new\nadopters (happy to fold them into\n that file instead if you would rather keep all adopters together).\n- Also checked on the same host: a corrupt artifact and a read-only\ncache directory each fall back to\ncompiling with a warning, and editing a key source invalidates the\nmodule and recompiles it once.\n\n**Not verified — please check on sm120 hardware.**\n`tests/moe/test_b12x_fused_moe.py`'s numerical\ntests do not run on my GB10: the nvcc reference ops fail to build (`CUDA\ncompiler and CUDA toolkit\nheaders are incompatible`). The suite gives an identical `142 failed, 15\npassed` — the same 142 test\nids — on unmodified `main` and on this branch, so I have no accuracy\nsignal either way. All timings\nabove are compile/load time; steady-state kernel performance should be\nunchanged, since it is the\nsame binary.\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n* **New Features**\n* Added shared on-disk caching for static, micro, and dynamic MoE\nkernels.\n * Improved cache invalidation when source dependencies change.\n* Kernel launches now automatically use the caller’s active CUDA stream.\n\n* **Tests**\n* Added comprehensive coverage for cache-key completeness, naming\nstability, symbol safety, and uniqueness across kernel types.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n\nSigned-off-by: Han-Yin Chang <nick20350@gmail.com>\nCo-authored-by: Claude Opus 5 <noreply@anthropic.com>\nCo-authored-by: Brian K. Ryu <bryu@nvidia.com>"},"path":{"kind":"string","value":"flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_dispatch.py"},"language":{"kind":"string","value":"cute_dsl"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"\"\"\"SM120/SM121 MoE dispatch layer — workspace, compilation, and launch.\n\nPorted from b12x's integration/tp_moe.py. Supports micro (tiny decode),\nstatic (decode), and dynamic (prefill) backends with token-count-based\nselection.\n\"\"\"\n\nfrom __future__ import annotations\n\nimport os\nimport weakref\nfrom dataclasses import dataclass\nfrom typing import Any, Dict, Optional, Tuple, Union\n\nimport cutlass\nimport cutlass.cute as cute\nimport torch\n\nfrom flashinfer.cute_dsl.utils import (\n convert_sf_from_mma_layout,\n convert_sf_to_mma_layout,\n current_cuda_stream,\n get_max_active_clusters,\n get_num_sm,\n make_ptr,\n)\nfrom .moe_activation import SWIGLUOAI_UNINTERLEAVE, is_gated_activation\nfrom .moe_direct_micro_kernel import (\n MoEDirectMicroKernel,\n build_direct_micro_kernel,\n compile_direct_micro_kernel,\n compiled_direct_micro_accepts_block_dim,\n)\nfrom .moe_dynamic_kernel import (\n _MAX_SHARED_INPUT_TOPK,\n _TASK_SLICE_CHUNK,\n MoEDynamicKernel,\n)\nfrom .moe_micro_kernel import MoEMicroKernel\nfrom .moe_static_kernel import MoEStaticKernel\nfrom .moe_w4a16_fp4_helpers import swizzle_block_scale\nfrom .moe_w4a16_host import (\n _W4A16_ALLOWED_ROUTED_SIZES,\n max_packed_route_slots,\n packed_gemm_scratch_elements,\n route_pack_numel_capacity,\n unswizzle_block_scale,\n validate_activation,\n)\nfrom .moe_w4a16_kernel import run_w4a16_moe\nfrom .moe_w4a16_prepare import (\n W4A16PackedWeights,\n _normalize_source_format,\n prepare_w4a16_packed_weights,\n)\n\n# ---------------------------------------------------------------------------\n# Constants\n# ---------------------------------------------------------------------------\n_NVFP4_BLOCK_SIZE = 16\n_LEVEL_TILE_M = 128\n_LEVEL_TILE_N = 128\n# Must equal the kernel's task materialization granularity or the task\n# queue is mis-sized.\n_DYNAMIC_SLICE_CHUNK = _TASK_SLICE_CHUNK\nSF_VEC_SIZE = 16\n_FORCE_MOE_W4A16_ENV = \"FLASHINFER_B12X_FORCE_MOE_W4A16\"\n_MICRO_SHARE_INPUT_ACROSS_EXPERTS = (\n os.environ.get(\"FLASHINFER_B12X_MICRO_SHARE_INPUT\", \"1\") != \"0\"\n)\n\n# Micro kernel cutover thresholds (routed pairs)\n_MICRO_COMPACT_CUTOVER_PAIRS = 20\n_MICRO_COMPACT_CUTOVER_PAIRS_MULTI_TOPK = 40\n# The micro kernel's per-token staging assumes decode-sized batches.\n_MICRO_MAX_TOKENS = 8\n# Direct micro takes the smallest decode batches ahead of the MMA micro\n# kernel, and only at small intermediate sizes where its CUDA-core dots\n# keep up with per-token work. Measured on GB10, pending other GPUs.\n_DIRECT_MICRO_CUTOVER_PAIRS = 32\n_DIRECT_MICRO_MAX_N = 512\n# Test/bench hook: force one backend (\"direct_micro\", \"micro\", \"static\",\n# \"dynamic\"). Deliberately module-level (a monkeypatch target), not an env var.\n_FORCED_BACKEND: str | None = None\n_STATIC_COMPACT_CUTOVER_PAIRS_DEFAULT = 640\n_STATIC_COMPACT_CUTOVER_PAIRS = _STATIC_COMPACT_CUTOVER_PAIRS_DEFAULT\n_STATIC_COMPACT_CUTOVER_PAIRS_CACHE: Dict[str, int] = {}\n\n# MAC (max active clusters) tuning ladders from b12x decode profiling.\n# Each entry is (max_routed_rows, optimal_mac).\n_MICRO_MAC_LADDER: Tuple[Tuple[int, int], ...] = (\n (2, 84),\n (4, 127),\n (8, 107),\n (10, 84),\n (16, 63),\n (20, 84),\n)\n_STATIC_MAC_LADDER: Tuple[Tuple[int, int], ...] = (\n (24, 148),\n (32, 169),\n (40, 132),\n (48, 149),\n (64, 134),\n (80, 175),\n (96, 171),\n (120, 125),\n (128, 130),\n (160, 171),\n (192, 166),\n (256, 141),\n (320, 158),\n (512, 175),\n (640, 188),\n)\n# Workloads at or below the static cutover (640 routed pairs by default)\n# take the static kernel, so only the 1024 entry is normally reachable.\n_DYNAMIC_MAC_LADDER: Tuple[Tuple[int, int], ...] = (\n (640, 188),\n (1024, 147),\n)\n\n\ndef _lookup_mac_ladder(\n ladder: Tuple[Tuple[int, int], ...], routed_rows: int\n) -> int | None:\n \"\"\"Look up optimal MAC from a tuning ladder. Returns None if no match.\"\"\"\n for end_rows, mac in ladder:\n if routed_rows <= end_rows:\n return mac\n return None\n\n\ndef _align_up(value: int, alignment: int) -> int:\n return ((value + alignment - 1) // alignment) * alignment\n\n\n# The kernels index the packed activation and scale planes with 32-bit\n# offsets, so reject any workspace plane large enough to overflow them.\n_RUNTIME_MEMREF_LIMIT = (1 << 31) - 1\n\n\ndef _check_memref_limit(name: str, elements: int) -> None:\n if elements > _RUNTIME_MEMREF_LIMIT:\n raise ValueError(\n f\"{name} needs {elements} elements, which exceeds the 2^31-1 \"\n \"runtime memref limit. Reduce the token chunk or expert count \"\n \"for this launch.\"\n )\n\n\ndef _first_env(*names: str) -> str | None:\n for name in names:\n value = os.environ.get(name)\n if value is not None:\n return value\n return None\n\n\ndef _normalize_activation_precision(activation_precision: str) -> str:\n \"\"\"Normalize public activation-precision names to internal modes.\"\"\"\n if os.environ.get(_FORCE_MOE_W4A16_ENV, \"0\") == \"1\":\n return \"bf16\"\n\n normalized = str(activation_precision).lower()\n aliases = {\n \"fp4\": \"fp4\",\n \"nvfp4\": \"fp4\",\n \"w4a4\": \"fp4\",\n \"bf16\": \"bf16\",\n \"w4a16\": \"bf16\",\n }\n try:\n return aliases[normalized]\n except KeyError as exc:\n raise ValueError(\n \"activation_precision must be 'fp4' or 'bf16' \"\n f\"(got {activation_precision!r}).\"\n ) from exc\n\n\ndef _normalize_quant_mode(\n quant_mode: str | None = None,\n activation_precision: str | None = None,\n) -> str:\n \"\"\"Normalize public quantization names to the dispatch mode.\"\"\"\n if os.environ.get(_FORCE_MOE_W4A16_ENV, \"0\") == \"1\":\n return \"w4a16\"\n if quant_mode is None:\n activation_precision = _normalize_activation_precision(\n activation_precision or \"fp4\"\n )\n return \"w4a16\" if activation_precision == \"bf16\" else \"nvfp4\"\n\n normalized = str(quant_mode).lower()\n aliases = {\n \"fp4\": \"nvfp4\",\n \"nvfp4\": \"nvfp4\",\n \"w4a4\": \"nvfp4\",\n \"bf16\": \"w4a16\",\n \"w4a16\": \"w4a16\",\n }\n try:\n return aliases[normalized]\n except KeyError as exc:\n raise ValueError(\n f\"quant_mode must be 'nvfp4'/'w4a4' or 'w4a16' (got {quant_mode!r}).\"\n ) from exc\n\n\ndef _activation_precision_from_quant_mode(quant_mode: str) -> str:\n return \"bf16\" if _normalize_quant_mode(quant_mode) == \"w4a16\" else \"fp4\"\n\n\ndef _normalize_source_format_for_quant_mode(source_format: str, quant_mode: str) -> str:\n normalized = _normalize_source_format(source_format)\n if quant_mode == \"nvfp4\" and normalized == \"compressed_tensors\":\n raise ValueError(\n \"source_format='compressed_tensors' requires quant_mode='w4a16'.\"\n )\n return normalized\n\n\ndef _is_w4a16(activation_precision: str) -> bool:\n return _normalize_activation_precision(activation_precision) == \"bf16\"\n\n\ndef _level_tile_n(activation_precision: str = \"fp4\") -> int:\n if _is_w4a16(activation_precision):\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 tile selector\"\n )\n return _LEVEL_TILE_N\n\n\ndef _select_dynamic_tile_m(\n routed_rows: int,\n num_experts: int,\n activation: str = \"silu\",\n) -> int:\n \"\"\"Pick the dynamic kernel's M-tile from routed rows per expert.\n\n Small tiles cut per-expert tail padding for sparse routing; 128 amortizes\n best for dense prefill (crossovers measured on gated NVFP4). Workspace\n sizing and the kernel build must both derive the tile from this function,\n or the scratch is mis-sized for what the kernel indexes.\n \"\"\"\n if not is_gated_activation(activation):\n return _LEVEL_TILE_M\n routed_rows = max(1, int(routed_rows))\n num_experts = max(1, int(num_experts))\n if routed_rows < 15 * num_experts:\n return 16\n if routed_rows < 48 * num_experts:\n return 32\n if routed_rows < 96 * num_experts:\n return 64\n return _LEVEL_TILE_M\n\n\ndef _get_static_compact_cutover_pairs(activation_precision: str = \"fp4\") -> int:\n activation_precision = _normalize_activation_precision(activation_precision)\n cached = _STATIC_COMPACT_CUTOVER_PAIRS_CACHE.get(activation_precision)\n if cached is not None:\n return cached\n\n cutover_names: tuple[str, ...] = (\n \"FLASHINFER_B12X_STATIC_COMPACT_CUTOVER_PAIRS\",\n \"B12X_STATIC_COMPACT_CUTOVER_PAIRS\",\n \"B12X_DYNAMIC_STATIC_CUTOVER_PAIRS\",\n \"B12X_LEVEL10_STATIC_CUTOVER_PAIRS\",\n )\n cutover = _first_env(*cutover_names)\n if cutover is None:\n cached = _STATIC_COMPACT_CUTOVER_PAIRS_DEFAULT\n else:\n cached = max(0, int(cutover))\n _STATIC_COMPACT_CUTOVER_PAIRS_CACHE[activation_precision] = cached\n return cached\n\n\ndef _select_moe_mma_tiler_mn(\n routed_rows: int,\n n: int,\n *,\n resident_clusters: int | None = None,\n) -> Tuple[int, int]:\n \"\"\"Select optimal MoE tile shape based on routed rows and N dimension.\n\n Uses narrower 64x128 tiles when routed_rows <= 128 and default 128x128\n would leave SMs idle.\n \"\"\"\n sm_count = get_num_sm(torch.device(\"cuda\"))\n coarse_tile = (128, 128)\n if routed_rows <= 32 and n <= 256:\n return (64, 128)\n if resident_clusters is not None and resident_clusters < sm_count:\n return coarse_tile\n coarse_tiles = ((routed_rows + coarse_tile[0] - 1) // coarse_tile[0]) * (\n (n + coarse_tile[1] - 1) // coarse_tile[1]\n )\n # Single-token decode often lands exactly on the \"half the machine\"\n # boundary. Keeping the coarse 128x128 tile there leaves the M dimension\n # badly underfilled, so take the narrow 64x128 tile inclusive of equality.\n if routed_rows <= 64 or (\n routed_rows <= 128 and coarse_tiles <= max(1, sm_count // 2)\n ):\n return (64, 128)\n return (128, 128)\n\n\ndef _as_grouped_scale_view(\n scale_storage: torch.Tensor,\n rows: int,\n cols: int,\n) -> torch.Tensor:\n \"\"\"Create 6D MMA-compatible scale factor view from swizzled storage.\"\"\"\n batch = scale_storage.shape[0]\n rows_padded = _align_up(rows, 128)\n cols_padded = _align_up(cols // SF_VEC_SIZE, 4)\n sf = scale_storage.view(torch.float8_e4m3fn)\n sf = sf.view(batch, rows_padded // 128, cols_padded // 4, 32, 4, 4)\n return sf.permute(3, 4, 1, 5, 2, 0)\n\n\n# ---------------------------------------------------------------------------\n# Workspace\n# ---------------------------------------------------------------------------\n@dataclass(kw_only=True)\nclass Sm120StaticMoEWorkspace:\n \"\"\"Scratch buffers for one SM120 static MoE launch.\"\"\"\n\n state_E: int\n weight_E: int\n max_rows: int\n k: int\n n: int\n num_topk: int\n device: torch.device\n activation_precision: str\n\n # Buffers\n row_counts: torch.Tensor # [state_E] int32\n token_map: torch.Tensor # [state_E, max_rows] int32\n token_weights: torch.Tensor # [state_E, max_rows] float32\n packed_input: torch.Tensor # [state_E, max_rows, k//2] uint8\n packed_input_scale: torch.Tensor # [state_E, rows_pad_k, cols_pad_k] uint8\n barrier_count: torch.Tensor # [1] int32\n barrier_epoch: torch.Tensor # [1] int32\n active_expert_count: torch.Tensor # [1] int32\n weight_expert_ids: torch.Tensor # [state_E] int32\n global_to_local_expert: torch.Tensor # [weight_E] int32\n compact_topk_ids: torch.Tensor # [state_E] int32, for micro kernel pre-pass\n\n # Views (set after allocation)\n packed_a_view: torch.Tensor | None = None\n sfa_ptr: object = None\n packed_a_flat: torch.Tensor | None = None\n scale_flat: torch.Tensor | None = None\n\n # Direct micro planes (allocated only when the shape can take that path).\n dm_barrier_count: torch.Tensor | None = None\n dm_barrier_epoch: torch.Tensor | None = None\n dm_intermediate: torch.Tensor | None = None\n dm_input_gs: torch.Tensor | None = None\n dm_down_input_scale: torch.Tensor | None = None\n\n\ndef _direct_micro_candidate(k: int, n: int, num_topk: int, weight_E: int) -> bool:\n \"\"\"Whether any m in the tiny-decode band can run the direct micro kernel.\"\"\"\n return any(\n MoEDirectMicroKernel.is_supported(m, k, n, num_topk, weight_E)\n for m in range(1, _MICRO_MAX_TOKENS + 1)\n )\n\n\ndef allocate_sm120_static_workspace(\n *,\n state_E: int,\n weight_E: int,\n max_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation_precision: str = \"fp4\",\n) -> Sm120StaticMoEWorkspace:\n \"\"\"Allocate workspace buffers for the SM120 static MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"allocate_sm120_static_workspace only supports quant_mode='nvfp4'; \"\n \"use allocate_sm120_moe_workspace(..., quant_mode='w4a16') for W4A16.\"\n )\n\n rows_pad_k = _align_up(max_rows, 128)\n cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n _check_memref_limit(\"static packed_input\", state_E * max_rows * (k // 2))\n _check_memref_limit(\"static packed_input_scale\", state_E * rows_pad_k * cols_pad_k)\n packed_input = torch.empty(\n state_E, max_rows, k // 2, dtype=torch.uint8, device=device\n )\n\n workspace = Sm120StaticMoEWorkspace(\n state_E=state_E,\n weight_E=weight_E,\n max_rows=max_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation_precision=activation_precision,\n row_counts=torch.zeros(state_E, dtype=torch.int32, device=device),\n token_map=torch.zeros(state_E, max_rows, dtype=torch.int32, device=device),\n token_weights=torch.zeros(\n state_E, max_rows, dtype=torch.float32, device=device\n ),\n packed_input=packed_input,\n packed_input_scale=torch.empty(\n state_E, rows_pad_k, cols_pad_k, dtype=torch.uint8, device=device\n ),\n barrier_count=torch.zeros(1, dtype=torch.int32, device=device),\n barrier_epoch=torch.zeros(1, dtype=torch.int32, device=device),\n active_expert_count=torch.zeros(1, dtype=torch.int32, device=device),\n weight_expert_ids=torch.arange(state_E, dtype=torch.int32, device=device),\n global_to_local_expert=torch.empty(weight_E, dtype=torch.int32, device=device),\n compact_topk_ids=torch.empty(\n max(state_E, max_rows), dtype=torch.int32, device=device\n ),\n )\n\n # Finalize views\n sf_dtype = cutlass.Float8E4M3FN\n workspace.packed_a_view = workspace.packed_input.permute(1, 2, 0).view(\n torch.float4_e2m1fn_x2\n )\n workspace.packed_a_flat = workspace.packed_input.view(-1)\n workspace.scale_flat = workspace.packed_input_scale.view(-1)\n workspace.sfa_ptr = make_ptr(\n sf_dtype,\n workspace.packed_input_scale.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n\n # Direct micro reads weights by global expert id, so its planes are only\n # useful without EP remapping.\n if state_E == weight_E and _direct_micro_candidate(k, n, num_topk, weight_E):\n dm_rows = min(max_rows, _MICRO_MAX_TOKENS * num_topk)\n # The epoch-based barriers restore their slots after each launch, so\n # the zeroed allocation is the only reset needed (graph-replay safe).\n dm_slots = dm_rows + _MICRO_MAX_TOKENS * 16\n fc2_n_chunks = (n // 2 + 127) // 128\n # The fused kernel binds the intermediate as m * num_topk *\n # fc2_n_chunks * 128 u32 words; size for the largest supported m.\n dm_inter = _MICRO_MAX_TOKENS * num_topk * fc2_n_chunks * 128\n workspace.dm_barrier_count = torch.zeros(\n dm_slots, dtype=torch.int32, device=device\n )\n workspace.dm_barrier_epoch = torch.zeros(\n dm_slots, dtype=torch.int32, device=device\n )\n workspace.dm_intermediate = torch.empty(\n dm_inter, dtype=torch.float32, device=device\n )\n workspace.dm_input_gs = torch.empty(\n weight_E, dtype=torch.float32, device=device\n )\n workspace.dm_down_input_scale = torch.empty(\n weight_E, dtype=torch.float32, device=device\n )\n return workspace\n\n\n# ---------------------------------------------------------------------------\n# Weight views\n# ---------------------------------------------------------------------------\n@dataclass\nclass _WeightViews:\n w13_fp4: object = None\n down_fp4: object = None\n sfb_w13_ptr: object = None\n sfb_down_ptr: object = None\n w1_alpha: torch.Tensor | None = None\n w2_alpha: torch.Tensor | None = None\n w1_storage: torch.Tensor | None = None\n w1_scale_storage: torch.Tensor | None = None\n w2_storage: torch.Tensor | None = None\n w2_scale_storage: torch.Tensor | None = None\n _w13_sf_storage: torch.Tensor | None = None\n _down_sf_storage: torch.Tensor | None = None\n\n\ndef _register_cache_eviction(cache: Dict, key: Tuple, *source_tensors) -> None:\n \"\"\"Evict ``key`` when a source weight tensor is collected, so the cache\n follows the weights' lifetime instead of growing for the whole process.\n \"\"\"\n for tensor in source_tensors:\n if tensor is not None:\n weakref.finalize(tensor, cache.pop, key, None)\n\n\n_WEIGHT_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_weight_views(\n w1_fp4: torch.Tensor,\n w1_blockscale: torch.Tensor,\n w2_fp4: torch.Tensor,\n w2_blockscale: torch.Tensor,\n w1_alphas: torch.Tensor,\n w2_alphas: torch.Tensor,\n n: int,\n k: int,\n activation_precision: str = \"fp4\",\n) -> _WeightViews:\n \"\"\"Create permuted weight views for the static kernel.\n\n The kernel expects concatenated w13 data with shape [2*n, k//2, E]\n via a single TMA descriptor.\n \"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n tile_n = _level_tile_n(activation_precision)\n # The kernel splits w13 into gate/up halves by tile index. This only works\n # when the boundary between halves lands on a tile-aligned column.\n if n % tile_n != 0:\n raise ValueError(\n f\"intermediate_size ({n}) must be a multiple of {tile_n} \"\n f\"for the SM120 MoE kernel's gate/up tile split.\"\n )\n\n key = (\n activation_precision,\n w1_fp4.data_ptr(),\n w1_blockscale.data_ptr(),\n w1_alphas.data_ptr(),\n w2_fp4.data_ptr(),\n w2_blockscale.data_ptr(),\n w2_alphas.data_ptr(),\n )\n cached = _WEIGHT_CACHE.get(key)\n if cached is None:\n # Cache the fresh buffers (scale factors + fp32 alphas).\n w1_rows = w1_fp4.shape[1] # 2*n for gated, n for non-gated\n cached = (\n convert_sf_from_mma_layout(\n w1_blockscale, m=w1_rows, k=k, num_groups=w1_fp4.shape[0]\n ).contiguous(),\n convert_sf_from_mma_layout(\n w2_blockscale, m=k, k=n, num_groups=w2_fp4.shape[0]\n ).contiguous(),\n w1_alphas.contiguous().to(torch.float32),\n w2_alphas.contiguous().to(torch.float32),\n )\n _WEIGHT_CACHE[key] = cached\n _register_cache_eviction(\n _WEIGHT_CACHE,\n key,\n w1_fp4,\n w1_blockscale,\n w1_alphas,\n w2_fp4,\n w2_blockscale,\n w2_alphas,\n )\n w13_sf_contiguous, down_sf_contiguous, w1_alpha, w2_alpha = cached\n\n # Permute [E, w1_rows, k//2] -> [w1_rows, k//2, E] (view, no copy).\n sf_dtype = cutlass.Float8E4M3FN\n w13 = w1_fp4.permute(1, 2, 0)\n down = w2_fp4.permute(1, 2, 0)\n return _WeightViews(\n w13_fp4=w13.view(torch.float4_e2m1fn_x2),\n down_fp4=down.view(torch.float4_e2m1fn_x2),\n sfb_w13_ptr=make_ptr(\n sf_dtype,\n w13_sf_contiguous.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n ),\n sfb_down_ptr=make_ptr(\n sf_dtype,\n down_sf_contiguous.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n ),\n w1_alpha=w1_alpha,\n w2_alpha=w2_alpha,\n w1_storage=w1_fp4,\n w1_scale_storage=w13_sf_contiguous,\n w2_storage=w2_fp4,\n w2_scale_storage=down_sf_contiguous,\n _w13_sf_storage=w13_sf_contiguous,\n _down_sf_storage=down_sf_contiguous,\n )\n\n\n# ---------------------------------------------------------------------------\n# Kernel compilation cache\n# ---------------------------------------------------------------------------\n_STATIC_KERNEL_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_static_kernel(\n state_E: int,\n weight_E: int,\n m: int,\n k: int,\n n: int,\n num_topk: int,\n max_rows: int,\n *,\n topk_ids_dtype: torch.dtype = torch.int32,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n mac_override: int | None = None,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n):\n \"\"\"Compile (or retrieve cached) the SM120 static MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 static compiler\"\n )\n sf_vec_size = 16\n sm_count = get_num_sm(torch.device(\"cuda\"))\n mac = (\n mac_override\n if mac_override is not None\n else min(get_max_active_clusters(1), sm_count)\n )\n\n # Select tile size based on actual routed rows\n routed_rows = m * num_topk\n mma_tiler_mn = (128, 128)\n if activation_precision == \"fp4\" and num_topk > 1:\n mma_tiler_mn = _select_moe_mma_tiler_mn(routed_rows, n, resident_clusters=mac)\n\n cache_key = (\n \"static\",\n activation_precision,\n state_E,\n weight_E,\n m,\n k,\n n,\n num_topk,\n max_rows,\n mac,\n mma_tiler_mn,\n topk_ids_dtype,\n input_scales_are_reciprocal,\n fast_math,\n activation,\n swiglu_alpha,\n swiglu_beta,\n swiglu_limit,\n )\n cached = _STATIC_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n return cached\n\n ab_dtype = cutlass.Float4E2M1FN\n weight_dtype = cutlass.Float4E2M1FN\n sf_dtype = cutlass.Float8E4M3FN\n a_dtype = cutlass.BFloat16\n alpha_dtype = cutlass.Float32\n\n output_tile_count_n = max(1, (n + mma_tiler_mn[1] - 1) // mma_tiler_mn[1])\n kernel: Any = MoEStaticKernel(\n sf_vec_size=sf_vec_size,\n mma_tiler_mn=mma_tiler_mn,\n output_tile_count_n=output_tile_count_n,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n )\n\n is_gated = is_gated_activation(activation)\n w1_rows = (2 if is_gated else 1) * n # 2*n for gated, n for non-gated\n\n rows_pad_k = _align_up(max_rows, 128)\n cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n\n # Build fake tensors for compilation\n a_input_fake = cute.runtime.make_fake_compact_tensor(\n a_dtype,\n (m, k),\n stride_order=(1, 0),\n assumed_align=16,\n )\n topk_ids_cutlass_dtype = (\n cutlass.Int32 if topk_ids_dtype == torch.int32 else cutlass.Int64\n )\n topk_ids_align = 4 if topk_ids_dtype == torch.int32 else 8\n topk_ids_fake = cute.runtime.make_fake_compact_tensor(\n topk_ids_cutlass_dtype,\n (m * num_topk,),\n assumed_align=topk_ids_align,\n )\n topk_weights_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32,\n (m * num_topk,),\n assumed_align=4,\n )\n packed_a_fake = cute.runtime.make_fake_compact_tensor(\n ab_dtype,\n (max_rows, k, state_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfa_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n packed_a_storage_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (state_E * max_rows * (k // 2),),\n assumed_align=16,\n )\n scale_storage_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (state_E * rows_pad_k * cols_pad_k,),\n assumed_align=16,\n )\n barrier_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n barrier_epoch_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n b_w13_fake = cute.runtime.make_fake_compact_tensor(\n weight_dtype,\n (w1_rows, k, weight_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_w13_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n b_down_fake = cute.runtime.make_fake_compact_tensor(\n weight_dtype,\n (k, n, weight_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_down_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n row_counts_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E,),\n assumed_align=4,\n )\n active_expert_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n weight_expert_ids_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E,),\n assumed_align=4,\n )\n global_to_local_expert_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (weight_E,),\n assumed_align=4,\n )\n input_gs_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n down_alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n global_scale_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n scatter_fake = cute.runtime.make_fake_compact_tensor(\n a_dtype,\n (m, k),\n stride_order=(1, 0),\n assumed_align=16,\n )\n token_map_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E, max_rows),\n stride_order=(1, 0),\n assumed_align=4,\n )\n token_weights_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (state_E, max_rows),\n stride_order=(1, 0),\n assumed_align=16,\n )\n compiled = cute.compile(\n kernel,\n a_input_fake,\n topk_ids_fake,\n topk_weights_fake,\n packed_a_fake,\n sfa_fake,\n packed_a_storage_fake,\n scale_storage_fake,\n barrier_count_fake,\n barrier_epoch_fake,\n b_w13_fake,\n sfb_w13_fake,\n b_down_fake,\n sfb_down_fake,\n row_counts_fake,\n active_expert_count_fake,\n weight_expert_ids_fake,\n global_to_local_expert_fake,\n input_gs_fake,\n alpha_fake,\n down_alpha_fake,\n global_scale_fake,\n scatter_fake,\n token_map_fake,\n token_weights_fake,\n mac,\n current_cuda_stream(),\n options=\"--opt-level 2 --enable-tvm-ffi\",\n )\n\n result = (compiled, mac)\n _STATIC_KERNEL_CACHE[cache_key] = result\n return result\n\n\n_MICRO_KERNEL_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_micro_kernel(\n state_E: int,\n weight_E: int,\n m: int,\n k: int,\n n: int,\n num_topk: int,\n max_rows: int,\n *,\n topk_ids_dtype: torch.dtype = torch.int32,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n share_input_across_experts: bool = False,\n share_expert_scales: bool = False,\n single_token: bool = False,\n mac_override: int | None = None,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n):\n \"\"\"Compile (or retrieve cached) the SM120 micro MoE kernel.\"\"\"\n sf_vec_size = 16\n sm_count = get_num_sm(torch.device(\"cuda\"))\n mac = (\n mac_override\n if mac_override is not None\n else min(get_max_active_clusters(1), sm_count)\n )\n\n # Micro always selects tile from routed rows (not just for multi-topk)\n routed_rows = m * num_topk\n mma_tiler_mn = _select_moe_mma_tiler_mn(routed_rows, n)\n\n cache_key = (\n \"micro\",\n state_E,\n weight_E,\n m,\n k,\n n,\n num_topk,\n max_rows,\n mac,\n mma_tiler_mn,\n topk_ids_dtype,\n input_scales_are_reciprocal,\n fast_math,\n share_input_across_experts,\n share_expert_scales,\n single_token,\n activation,\n swiglu_alpha,\n swiglu_beta,\n swiglu_limit,\n )\n cached = _MICRO_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n return cached\n\n ab_dtype = cutlass.Float4E2M1FN\n sf_dtype = cutlass.Float8E4M3FN\n a_dtype = cutlass.BFloat16\n alpha_dtype = cutlass.Float32\n\n kernel = MoEMicroKernel(\n sf_vec_size=sf_vec_size,\n mma_tiler_mn=mma_tiler_mn,\n output_tile_count_n=max(1, (n + mma_tiler_mn[1] - 1) // mma_tiler_mn[1]),\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n share_input_across_experts=share_input_across_experts,\n share_expert_scales=share_expert_scales,\n single_token=single_token,\n )\n\n is_gated = is_gated_activation(activation)\n w1_rows = (2 if is_gated else 1) * n\n\n rows_pad_k = _align_up(max_rows, 128)\n cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n\n # Build fake tensors for compilation (identical to static kernel)\n a_input_fake = cute.runtime.make_fake_compact_tensor(\n a_dtype,\n (m, k),\n stride_order=(1, 0),\n assumed_align=16,\n )\n topk_ids_cutlass_dtype = (\n cutlass.Int32 if topk_ids_dtype == torch.int32 else cutlass.Int64\n )\n topk_ids_align = 4 if topk_ids_dtype == torch.int32 else 8\n topk_ids_fake = cute.runtime.make_fake_compact_tensor(\n topk_ids_cutlass_dtype,\n (m * num_topk,),\n assumed_align=topk_ids_align,\n )\n topk_weights_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32,\n (m * num_topk,),\n assumed_align=4,\n )\n packed_a_fake = cute.runtime.make_fake_compact_tensor(\n ab_dtype,\n (max_rows, k, state_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfa_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n packed_a_storage_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (state_E * max_rows * (k // 2),),\n assumed_align=16,\n )\n scale_storage_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (state_E * rows_pad_k * cols_pad_k,),\n assumed_align=16,\n )\n barrier_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n barrier_epoch_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n b_w13_fake = cute.runtime.make_fake_compact_tensor(\n ab_dtype,\n (w1_rows, k, weight_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_w13_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n b_down_fake = cute.runtime.make_fake_compact_tensor(\n ab_dtype,\n (k, n, weight_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_down_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n row_counts_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E,),\n assumed_align=4,\n )\n active_expert_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n weight_expert_ids_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E,),\n assumed_align=4,\n )\n global_to_local_expert_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (weight_E,),\n assumed_align=4,\n )\n input_gs_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n down_alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n global_scale_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n scatter_fake = cute.runtime.make_fake_compact_tensor(\n a_dtype,\n (m, k),\n stride_order=(1, 0),\n assumed_align=16,\n )\n token_map_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E, max_rows),\n stride_order=(1, 0),\n assumed_align=4,\n )\n token_weights_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (state_E, max_rows),\n stride_order=(1, 0),\n assumed_align=16,\n )\n compiled = cute.compile(\n kernel,\n a_input_fake,\n topk_ids_fake,\n topk_weights_fake,\n packed_a_fake,\n sfa_fake,\n packed_a_storage_fake,\n scale_storage_fake,\n barrier_count_fake,\n barrier_epoch_fake,\n b_w13_fake,\n sfb_w13_fake,\n b_down_fake,\n sfb_down_fake,\n row_counts_fake,\n active_expert_count_fake,\n weight_expert_ids_fake,\n global_to_local_expert_fake,\n input_gs_fake,\n alpha_fake,\n down_alpha_fake,\n global_scale_fake,\n scatter_fake,\n token_map_fake,\n token_weights_fake,\n mac,\n current_cuda_stream(),\n options=\"--opt-level 2 --enable-tvm-ffi\",\n )\n\n result = (compiled, mac)\n _MICRO_KERNEL_CACHE[cache_key] = result\n return result\n\n\n# The launch cache skips the per-launch build/configure; the kernel cache\n# dedupes compiles across keys that configure to the same artifact\n# (m=2..8 differ only in grid_x).\n_DIRECT_MICRO_LAUNCH_CACHE: Dict[Tuple, Tuple] = {}\n_DIRECT_MICRO_KERNEL_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_direct_micro_kernel(\n weight_E: int,\n m: int,\n k: int,\n n: int,\n num_topk: int,\n *,\n topk_ids_dtype: torch.dtype = torch.int32,\n fast_math: bool = True,\n share_input_across_experts: bool = False,\n share_expert_scales: bool = False,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n device: torch.device | None = None,\n):\n \"\"\"Compile (or retrieve cached) the SM120 direct micro MoE kernel.\n\n Returns (compiled, grid_x, accepts_block_dim).\n \"\"\"\n if activation != SWIGLUOAI_UNINTERLEAVE:\n # The kernel constructor only accepts configurable swiglu parameters\n # for swigluoai; other activations use its normalized defaults\n # (accept-and-ignore, matching the MMA kernels).\n swiglu_alpha = None\n swiglu_beta = None\n swiglu_limit = None\n launch_key = (\n weight_E,\n m,\n k,\n n,\n num_topk,\n topk_ids_dtype,\n fast_math,\n share_input_across_experts,\n share_expert_scales,\n activation,\n swiglu_alpha,\n swiglu_beta,\n swiglu_limit,\n str(_canonical_cuda_device(device)) if device is not None else None,\n )\n cached = _DIRECT_MICRO_LAUNCH_CACHE.get(launch_key)\n if cached is not None:\n return cached\n kernel = build_direct_micro_kernel(\n weight_E,\n m,\n k,\n n,\n num_topk,\n activation=activation,\n fast_math=fast_math,\n share_input_across_experts=share_input_across_experts,\n share_expert_scales=share_expert_scales,\n single_token=m == 1,\n swiglu_limit=swiglu_limit,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n device=device,\n )\n compile_key = (\"direct_micro\", kernel.__cache_key__, topk_ids_dtype)\n entry = _DIRECT_MICRO_KERNEL_CACHE.get(compile_key)\n if entry is None:\n compiled = compile_direct_micro_kernel(kernel, topk_ids_dtype=topk_ids_dtype)\n # Register pressure can cap the launchable CTA below the fused body's\n # 512 threads; probe once per compiled kernel.\n accepts = compiled_direct_micro_accepts_block_dim(\n compiled, kernel.launch_block_dim\n )\n entry = (compiled, accepts)\n _DIRECT_MICRO_KERNEL_CACHE[compile_key] = entry\n compiled, accepts = entry\n cached = (compiled, kernel.grid_x, accepts)\n _DIRECT_MICRO_LAUNCH_CACHE[launch_key] = cached\n return cached\n\n\n# ---------------------------------------------------------------------------\n# Launch\n# ---------------------------------------------------------------------------\ndef _expand_to_experts(t: torch.Tensor, num_experts: int) -> torch.Tensor:\n \"\"\"Broadcast a scalar or [1] tensor to [num_experts], always fp32.\n\n Both branches must cast: the kernels are compiled against fp32 fake\n tensors for every per-expert scale.\n \"\"\"\n if t.numel() == 1:\n return t.to(torch.float32).expand(num_experts).contiguous()\n return t.contiguous().to(torch.float32)\n\n\ndef launch_sm120_static_moe(\n *,\n workspace: Sm120StaticMoEWorkspace,\n weights: _WeightViews,\n a: torch.Tensor,\n topk_ids: torch.Tensor,\n topk_weights: torch.Tensor,\n input_gs: torch.Tensor,\n down_input_scale: torch.Tensor,\n scatter_output: torch.Tensor,\n num_experts: int,\n num_tokens: int,\n k: int,\n n: int,\n top_k: int,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n) -> torch.Tensor:\n \"\"\"Launch the SM120 static, micro, or direct micro MoE kernel.\n\n The direct micro kernel takes tiny decode batches (m <= 8, routed_rows\n < 64) when it supports the shape, the MMA micro kernel takes the rest of\n its band (routed_rows <= 20-40), and the static kernel takes the rest.\n The MMA micro path runs a Triton pre-pass to compact routing IDs before\n launching; direct micro routes on global expert ids directly.\n \"\"\"\n _check_memref_limit(\"scatter_output\", scatter_output.numel())\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 static launcher\"\n )\n\n # Flatten routing tensors\n flat_ids = topk_ids.view(-1).to(torch.int32)\n flat_weights = topk_weights.view(-1).to(torch.float32)\n routed_rows = num_tokens * top_k\n\n # Capture whether input_gs was a single shared scalar BEFORE expansion:\n # the m=1 relu2 shared-input micro optimization only applies when every\n # expert sees the same FC1-input global scale.\n input_gs_is_shared = input_gs.numel() == 1\n down_input_scale_is_shared = down_input_scale.numel() == 1\n\n # Broadcast scalar scales to per-expert [E] tensors\n input_gs = _expand_to_experts(input_gs, num_experts)\n down_input_scale = _expand_to_experts(down_input_scale, num_experts)\n\n # Shared-scale flags let compact W4A4 micro match the ReLU2 single-token\n # specialization.\n share_input_across_experts = (\n activation == \"relu2\"\n and num_tokens == 1\n and input_gs_is_shared\n and _MICRO_SHARE_INPUT_ACROSS_EXPERTS\n )\n share_expert_scales = (\n activation == \"relu2\" and input_gs_is_shared and down_input_scale_is_shared\n )\n\n # Direct micro takes its band before the MMA micro decision. It reads\n # weights by global expert id, so EP shapes keep the compact path.\n use_direct_micro = (\n activation_precision == \"fp4\"\n and workspace.state_E == num_experts\n and workspace.dm_barrier_count is not None\n and workspace.dm_barrier_count.numel() >= routed_rows + num_tokens * 16\n and num_tokens <= _MICRO_MAX_TOKENS\n and routed_rows < _DIRECT_MICRO_CUTOVER_PAIRS\n and n <= _DIRECT_MICRO_MAX_N\n and MoEDirectMicroKernel.is_supported(num_tokens, k, n, top_k, num_experts)\n )\n if _FORCED_BACKEND is not None:\n if _FORCED_BACKEND == \"direct_micro\":\n if workspace.dm_barrier_count is None or not (\n MoEDirectMicroKernel.is_supported(num_tokens, k, n, top_k, num_experts)\n ):\n raise ValueError(\n \"forced direct_micro backend cannot run this shape \"\n f\"(m={num_tokens}, k={k}, n={n}, top_k={top_k})\"\n )\n if workspace.dm_barrier_count.numel() < routed_rows + num_tokens * 16:\n raise ValueError(\n \"forced direct_micro backend exceeds the workspace barrier \"\n f\"capacity ({workspace.dm_barrier_count.numel()} slots < \"\n f\"{routed_rows} routed rows + {num_tokens * 16})\"\n )\n use_direct_micro = True\n else:\n use_direct_micro = False\n if use_direct_micro:\n compiled, grid_x, block_ok = _get_direct_micro_kernel(\n num_experts,\n num_tokens,\n k,\n n,\n top_k,\n topk_ids_dtype=flat_ids.dtype,\n fast_math=fast_math,\n share_input_across_experts=share_input_across_experts,\n share_expert_scales=share_expert_scales,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n device=a.device,\n )\n if not block_ok:\n if _FORCED_BACKEND == \"direct_micro\":\n raise RuntimeError(\"compiled direct micro MoE kernel cannot launch\")\n use_direct_micro = False\n if use_direct_micro:\n # The kernel takes multiplier-form scales only; invert reciprocal\n # inputs into the persistent workspace planes (zeros stay zero,\n # matching the MMA kernels).\n if input_scales_are_reciprocal:\n workspace.dm_input_gs.copy_(\n torch.where(input_gs != 0, 1.0 / input_gs, input_gs)\n )\n workspace.dm_down_input_scale.copy_(\n torch.where(\n down_input_scale != 0, 1.0 / down_input_scale, down_input_scale\n )\n )\n launch_gs = workspace.dm_input_gs\n launch_down = workspace.dm_down_input_scale\n else:\n launch_gs = input_gs\n launch_down = down_input_scale\n MoEDirectMicroKernel.launch(\n compiled,\n x=a,\n w1_fp4=weights.w1_storage,\n w1_blockscale=weights.w1_scale_storage,\n w1_alphas=weights.w1_alpha,\n a1_gscale=launch_gs,\n a2_gscale=launch_down,\n inter_fp32=workspace.dm_intermediate,\n w2_fp4=weights.w2_storage,\n w2_blockscale=weights.w2_scale_storage,\n w2_alphas=weights.w2_alpha,\n topk_ids=flat_ids,\n topk_weights=flat_weights,\n out=scatter_output,\n barrier_count=workspace.dm_barrier_count,\n barrier_epoch=workspace.dm_barrier_epoch,\n m=num_tokens,\n grid_x=grid_x,\n )\n return scatter_output\n\n # Decide micro vs static\n micro_cutover = _MICRO_COMPACT_CUTOVER_PAIRS\n if top_k > 1:\n micro_cutover = _MICRO_COMPACT_CUTOVER_PAIRS_MULTI_TOPK\n use_micro = (\n activation_precision == \"fp4\"\n and num_tokens <= _MICRO_MAX_TOKENS\n and routed_rows <= micro_cutover\n )\n if _FORCED_BACKEND is not None:\n if _FORCED_BACKEND == \"micro\":\n # Forced mode raises on correctness violations, never falls back.\n if num_tokens > _MICRO_MAX_TOKENS:\n raise ValueError(\n f\"forced micro backend supports at most {_MICRO_MAX_TOKENS} \"\n f\"tokens (got {num_tokens})\"\n )\n if flat_ids.numel() > workspace.compact_topk_ids.numel():\n raise ValueError(\n \"forced micro backend exceeds the workspace compact-id \"\n f\"capacity ({workspace.compact_topk_ids.numel()} < \"\n f\"{flat_ids.numel()})\"\n )\n use_micro = True\n else:\n use_micro = False\n\n sm_count = get_num_sm(torch.device(\"cuda\"))\n base_mac = min(get_max_active_clusters(1), sm_count)\n tuned_static_mac = _lookup_mac_ladder(_STATIC_MAC_LADDER, routed_rows)\n static_mac = min(tuned_static_mac or base_mac, base_mac)\n if activation_precision == \"fp4\" and not use_micro and routed_rows < 40:\n static_mac = min(static_mac, 64)\n\n if use_micro:\n assert flat_ids.numel() <= workspace.compact_topk_ids.numel(), (\n f\"compact_topk_ids buffer too small: \"\n f\"{workspace.compact_topk_ids.numel()} < {flat_ids.numel()}\"\n )\n # Single-token ReLU2 is non-gated, so the micro kernel can launch on\n # the routed expert ids directly. Gated SiLU still goes through the\n # compact id buffer so the kernel can map compact launch ids back to\n # the physical gate/up weight experts.\n if num_tokens == 1 and activation == \"relu2\":\n launch_ids = flat_ids\n elif num_tokens == 1:\n compact_ids = workspace.compact_topk_ids[: flat_ids.numel()]\n compact_ids.copy_(\n torch.arange(\n flat_ids.numel(),\n device=flat_ids.device,\n dtype=torch.int32,\n )\n )\n workspace.weight_expert_ids[: flat_ids.numel()].copy_(\n flat_ids.to(torch.int32)\n )\n workspace.active_expert_count.fill_(flat_ids.numel())\n launch_ids = compact_ids\n else:\n compact_ids = workspace.compact_topk_ids[: flat_ids.numel()]\n from .triton_compact import compact_topk_ids as _triton_compact_topk_ids\n\n _triton_compact_topk_ids(\n flat_ids,\n compact_ids,\n workspace.weight_expert_ids,\n workspace.active_expert_count,\n )\n launch_ids = compact_ids\n # Select micro MAC: min of tuned ladder, work tiles, and hardware limit.\n micro_work_tiles = max(1, routed_rows * max(1, (n + 128 - 1) // 128))\n tuned_mac = _lookup_mac_ladder(_MICRO_MAC_LADDER, routed_rows)\n micro_mac = min(tuned_mac or base_mac, micro_work_tiles, base_mac)\n compiled, mac = _get_micro_kernel(\n workspace.state_E,\n num_experts,\n num_tokens,\n k,\n n,\n top_k,\n workspace.max_rows,\n topk_ids_dtype=launch_ids.dtype,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n share_input_across_experts=share_input_across_experts,\n share_expert_scales=share_expert_scales,\n single_token=num_tokens == 1,\n mac_override=micro_mac,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n )\n else:\n compiled, mac = _get_static_kernel(\n workspace.state_E,\n num_experts,\n num_tokens,\n k,\n n,\n top_k,\n workspace.max_rows,\n topk_ids_dtype=torch.int32,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n mac_override=static_mac,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n activation_precision=activation_precision,\n )\n launch_ids = flat_ids\n\n # Pointer arguments must be passed as raw ints (data_ptr()) at runtime.\n runtime_args: Tuple[Any, ...] = (\n a,\n launch_ids,\n flat_weights,\n workspace.packed_a_view,\n workspace.packed_input_scale.data_ptr(),\n workspace.packed_a_flat,\n workspace.scale_flat,\n workspace.barrier_count,\n workspace.barrier_epoch,\n weights.w13_fp4,\n weights._w13_sf_storage.data_ptr(),\n weights.down_fp4,\n weights._down_sf_storage.data_ptr(),\n workspace.row_counts,\n workspace.active_expert_count,\n workspace.weight_expert_ids,\n workspace.global_to_local_expert,\n input_gs,\n weights.w1_alpha,\n weights.w2_alpha,\n down_input_scale,\n scatter_output,\n workspace.token_map,\n workspace.token_weights,\n )\n compiled(*runtime_args, current_cuda_stream())\n\n return scatter_output\n\n\n# ==========================================================================\n# Dynamic backend\n# ==========================================================================\n\n\ndef select_sm120_moe_backend(\n *,\n num_tokens: int,\n num_topk: int,\n activation_precision: str = \"fp4\",\n quant_mode: str | None = None,\n) -> str:\n \"\"\"Pick static or dynamic backend based on routed-pair count.\"\"\"\n mode = _normalize_quant_mode(quant_mode, activation_precision)\n if mode == \"w4a16\":\n return \"w4a16\"\n if _FORCED_BACKEND == \"dynamic\":\n return \"dynamic\"\n if _FORCED_BACKEND in (\"static\", \"micro\", \"direct_micro\"):\n # Both micro variants launch through the static workspace path.\n return \"static\"\n routed_rows = num_tokens * num_topk\n if routed_rows <= _get_static_compact_cutover_pairs(\"fp4\"):\n return \"static\"\n return \"dynamic\"\n\n\n# ---------------------------------------------------------------------------\n# Dynamic workspace\n# ---------------------------------------------------------------------------\n@dataclass(kw_only=True)\nclass Sm120DynamicMoEWorkspace:\n \"\"\"Scratch buffers for one SM120 dynamic MoE launch.\"\"\"\n\n state_E: int\n weight_E: int\n max_rows: int\n k: int\n n: int\n num_topk: int\n device: torch.device\n activation_precision: str\n\n # Core buffers\n row_counts: torch.Tensor\n token_map: torch.Tensor\n token_weights: torch.Tensor\n packed_input: torch.Tensor\n packed_input_scale: torch.Tensor\n barrier_count: torch.Tensor\n barrier_epoch: torch.Tensor\n\n # Dynamic-specific\n routed_rows_capacity: int\n physical_tiles_capacity: int\n task_capacity: int\n # The M-tile the geometry above was sized for; launches must build the\n # kernel with the same tile.\n tile_m: int = _LEVEL_TILE_M\n expert_write_rows: torch.Tensor\n expert_tile_base: torch.Tensor\n pair_head: torch.Tensor\n task_head: torch.Tensor\n task_tail: torch.Tensor\n task_expert: torch.Tensor\n task_valid_rows: torch.Tensor\n\n # Views\n packed_a_view: torch.Tensor | None = None\n sfa_ptr: object = None\n packed_a_flat: torch.Tensor | None = None\n scale_flat: torch.Tensor | None = None\n\n\ndef _dynamic_task_geometry(\n state_E: int,\n n: int,\n routed_rows: int,\n *,\n tile_m: int = _LEVEL_TILE_M,\n tile_n: int = _LEVEL_TILE_N,\n):\n \"\"\"Compute task queue dimensions from problem geometry.\n\n Each active expert can introduce at most one additional physical tile\n beyond the base count (due to per-expert tail padding). The task queue\n holds one entry per (m_tile, slice_group) pair — NOT multiplied by E.\n \"\"\"\n routed_rows = max(1, routed_rows)\n base_m_tiles = _align_up(routed_rows, tile_m) // tile_m\n active_expert_upper_bound = min(state_E, routed_rows)\n max_m_tiles = max(1, base_m_tiles + active_expert_upper_bound - 1)\n gate_tile_cnt = max(1, (n + tile_n - 1) // tile_n)\n slice_groups = max(\n 1, (gate_tile_cnt + _DYNAMIC_SLICE_CHUNK - 1) // _DYNAMIC_SLICE_CHUNK\n )\n max_tasks = max_m_tiles * slice_groups\n return max_m_tiles, gate_tile_cnt, max_tasks\n\n\ndef allocate_sm120_dynamic_workspace(\n *,\n state_E: int,\n weight_E: int,\n routed_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation_precision: str = \"fp4\",\n activation: str = \"silu\",\n) -> Sm120DynamicMoEWorkspace:\n \"\"\"Allocate workspace buffers for the SM120 dynamic MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"allocate_sm120_dynamic_workspace only supports quant_mode='nvfp4'; \"\n \"use allocate_sm120_moe_workspace(..., quant_mode='w4a16') for W4A16.\"\n )\n tile_m = _select_dynamic_tile_m(routed_rows, state_E, activation)\n physical_tiles, _, max_tasks = _dynamic_task_geometry(\n state_E,\n n,\n routed_rows,\n tile_m=tile_m,\n tile_n=_level_tile_n(activation_precision),\n )\n rows_padded = physical_tiles * tile_m\n # The kernel addresses activation scales in 128-row SF atoms regardless of\n # tile_m, so the scale plane must cover the last partial atom.\n scale_rows = _align_up(rows_padded, 128)\n cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n _check_memref_limit(\"dynamic packed_input\", rows_padded * (k // 2))\n _check_memref_limit(\"dynamic packed_input_scale\", scale_rows * cols_pad_k)\n packed_input = torch.empty(1, rows_padded, k // 2, dtype=torch.uint8, device=device)\n\n workspace = Sm120DynamicMoEWorkspace(\n state_E=state_E,\n weight_E=weight_E,\n max_rows=rows_padded,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation_precision=activation_precision,\n routed_rows_capacity=routed_rows,\n physical_tiles_capacity=physical_tiles,\n task_capacity=max_tasks,\n tile_m=tile_m,\n row_counts=torch.zeros(state_E, dtype=torch.int32, device=device),\n token_map=torch.zeros(rows_padded, dtype=torch.int32, device=device),\n token_weights=torch.zeros(rows_padded, dtype=torch.float32, device=device),\n packed_input=packed_input,\n packed_input_scale=torch.empty(\n scale_rows, cols_pad_k, dtype=torch.uint8, device=device\n ),\n barrier_count=torch.zeros(1, dtype=torch.int32, device=device),\n barrier_epoch=torch.zeros(1, dtype=torch.int32, device=device),\n expert_write_rows=torch.zeros(state_E, dtype=torch.int32, device=device),\n expert_tile_base=torch.zeros(state_E + 1, dtype=torch.int32, device=device),\n pair_head=torch.zeros(1, dtype=torch.int32, device=device),\n task_head=torch.zeros(1, dtype=torch.int32, device=device),\n task_tail=torch.zeros(1, dtype=torch.int32, device=device),\n task_expert=torch.zeros(max_tasks, dtype=torch.int32, device=device),\n task_valid_rows=torch.zeros(max_tasks, dtype=torch.int32, device=device),\n )\n\n # Finalize views\n sf_dtype = cutlass.Float8E4M3FN\n workspace.packed_a_view = workspace.packed_input.permute(1, 2, 0).view(\n torch.float4_e2m1fn_x2\n )\n workspace.packed_a_flat = workspace.packed_input.view(-1)\n workspace.scale_flat = workspace.packed_input_scale.view(-1)\n workspace.sfa_ptr = make_ptr(\n sf_dtype,\n workspace.packed_input_scale.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n return workspace\n\n\n# ---------------------------------------------------------------------------\n# Dynamic kernel compilation\n# ---------------------------------------------------------------------------\n\n\nclass _DynamicMoELaunch:\n \"\"\"Thin JIT wrapper that makes num_tokens and max_rows runtime Int32.\"\"\"\n\n def __init__(self, kernel, k, num_topk, activation_precision: str = \"fp4\"):\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 dynamic launcher wrapper\"\n )\n self._kernel = kernel\n self._k = k\n self._packed_storage_cols = k // 2\n self._num_topk = num_topk\n self._cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n\n @cute.jit\n def __call__(\n self,\n a_ptr: cute.Pointer,\n topk_ids_ptr: cute.Pointer,\n topk_weights_ptr: cute.Pointer,\n packed_a_ptr: cute.Pointer,\n sfa_ptr: cute.Pointer,\n packed_a_storage_ptr: cute.Pointer,\n scale_storage_ptr: cute.Pointer,\n barrier_count: cute.Tensor,\n barrier_epoch: cute.Tensor,\n pair_head: cute.Tensor,\n task_head: cute.Tensor,\n task_tail: cute.Tensor,\n task_expert_ptr: cute.Pointer,\n task_valid_rows_ptr: cute.Pointer,\n b_w13: cute.Tensor,\n sfb_w13_ptr: cute.Pointer,\n b_down: cute.Tensor,\n sfb_down_ptr: cute.Pointer,\n row_counts: cute.Tensor,\n expert_write_rows: cute.Tensor,\n expert_tile_base: cute.Tensor,\n input_global_scale: cute.Tensor,\n alpha: cute.Tensor,\n down_alpha: cute.Tensor,\n global_scale: cute.Tensor,\n scatter_ptr: cute.Pointer,\n token_map_ptr: cute.Pointer,\n token_weights_ptr: cute.Pointer,\n num_tokens: cutlass.Int32,\n max_rows: cutlass.Int32,\n rows_padded: cutlass.Int32,\n max_tasks: cutlass.Int32,\n max_active_clusters: cutlass.Constexpr,\n stream,\n ):\n a_input = cute.make_tensor(\n a_ptr, layout=cute.make_layout((num_tokens, self._k), stride=(self._k, 1))\n )\n topk_ids = cute.make_tensor(\n topk_ids_ptr,\n layout=cute.make_layout((num_tokens * self._num_topk,), stride=(1,)),\n )\n topk_weights_t = cute.make_tensor(\n topk_weights_ptr,\n layout=cute.make_layout((num_tokens * self._num_topk,), stride=(1,)),\n )\n scatter_output = cute.make_tensor(\n scatter_ptr,\n layout=cute.make_layout((num_tokens, self._k), stride=(self._k, 1)),\n )\n packed_a = cute.make_tensor(\n packed_a_ptr,\n layout=cute.make_layout(\n (rows_padded, self._k, 1), stride=(self._k, 1, rows_padded * self._k)\n ),\n )\n packed_a_storage = cute.make_tensor(\n packed_a_storage_ptr,\n layout=cute.make_layout(\n (rows_padded * self._packed_storage_cols,), stride=(1,)\n ),\n )\n # Activation scales live in 128-row SF atoms; the plane is allocated\n # through the last partial atom even when rows_padded is not aligned.\n scale_rows = ((rows_padded + 127) // 128) * 128\n scale_storage = cute.make_tensor(\n scale_storage_ptr,\n layout=cute.make_layout((scale_rows * self._cols_pad_k,), stride=(1,)),\n )\n token_map = cute.make_tensor(\n token_map_ptr, layout=cute.make_layout((rows_padded,), stride=(1,))\n )\n token_weights_t = cute.make_tensor(\n token_weights_ptr, layout=cute.make_layout((rows_padded,), stride=(1,))\n )\n task_expert = cute.make_tensor(\n task_expert_ptr, layout=cute.make_layout((max_tasks,), stride=(1,))\n )\n task_valid_rows = cute.make_tensor(\n task_valid_rows_ptr, layout=cute.make_layout((max_tasks,), stride=(1,))\n )\n self._kernel(\n a_input,\n topk_ids,\n topk_weights_t,\n packed_a,\n sfa_ptr,\n packed_a_storage,\n scale_storage,\n barrier_count,\n barrier_epoch,\n pair_head,\n task_head,\n task_tail,\n task_expert,\n task_valid_rows,\n b_w13,\n sfb_w13_ptr,\n b_down,\n sfb_down_ptr,\n row_counts,\n expert_write_rows,\n expert_tile_base,\n input_global_scale,\n alpha,\n down_alpha,\n global_scale,\n scatter_output,\n token_map,\n token_weights_t,\n max_active_clusters=max_active_clusters,\n stream=stream,\n )\n\n\n_DYNAMIC_KERNEL_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_dynamic_kernel(\n E: int,\n m: int,\n k: int,\n n: int,\n num_topk: int,\n max_rows: int,\n *,\n topk_ids_dtype: torch.dtype = torch.int32,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n share_input_across_experts: bool = False,\n tile_m: int = _LEVEL_TILE_M,\n):\n \"\"\"Compile (or retrieve cached) the SM120 dynamic MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 dynamic compiler\"\n )\n # Both dynamic implementations reserve 32 route slots per token for the\n # shared-input fast path. Larger top-k values remain correct by using the\n # generic per-route producer instead.\n share_input_across_experts = bool(\n share_input_across_experts\n and activation_precision == \"fp4\"\n and num_topk <= _MAX_SHARED_INPUT_TOPK\n )\n sf_vec_size = 16\n sm_count = get_num_sm(torch.device(\"cuda\"))\n base_mac = min(get_max_active_clusters(1), sm_count)\n tuned_mac = _lookup_mac_ladder(_DYNAMIC_MAC_LADDER, m * num_topk)\n mac = min(tuned_mac or base_mac, base_mac)\n # tile_m comes from the workspace's shared selection so the kernel's task\n # and scale indexing matches the allocated scratch geometry.\n mma_tiler_mn = (tile_m, _level_tile_n(activation_precision))\n\n cache_key = (\n \"dynamic\",\n activation_precision,\n E,\n k,\n n,\n num_topk,\n mac,\n mma_tiler_mn,\n topk_ids_dtype,\n input_scales_are_reciprocal,\n fast_math,\n activation,\n swiglu_alpha,\n swiglu_beta,\n swiglu_limit,\n share_input_across_experts,\n )\n cached = _DYNAMIC_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n return cached\n\n is_gated = is_gated_activation(activation)\n w1_rows = (2 if is_gated else 1) * n\n\n scratch_dtype = cutlass.Float4E2M1FN\n weight_dtype = cutlass.Float4E2M1FN\n sf_dtype = cutlass.Float8E4M3FN\n a_dtype = cutlass.BFloat16\n alpha_dtype = cutlass.Float32\n\n kernel: Any = MoEDynamicKernel(\n sf_vec_size=sf_vec_size,\n mma_tiler_mn=mma_tiler_mn,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n share_input_across_experts=share_input_across_experts,\n hidden_size=k,\n intermediate_size=n,\n num_topk=num_topk,\n )\n launch = _DynamicMoELaunch(\n kernel,\n k=k,\n num_topk=num_topk,\n activation_precision=activation_precision,\n )\n\n topk_ids_cutlass_dtype = (\n cutlass.Int32 if topk_ids_dtype == torch.int32 else cutlass.Int64\n )\n topk_ids_align = 4 if topk_ids_dtype == torch.int32 else 8\n\n # Runtime-shaped tensors passed as pointers\n a_input_fake = make_ptr(a_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n topk_ids_fake = make_ptr(\n topk_ids_cutlass_dtype,\n topk_ids_align,\n cute.AddressSpace.gmem,\n assumed_align=topk_ids_align,\n )\n topk_weights_fake = make_ptr(\n cutlass.Float32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n packed_a_fake = make_ptr(\n scratch_dtype, 16, cute.AddressSpace.gmem, assumed_align=16\n )\n sfa_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n packed_a_storage_fake = make_ptr(\n cutlass.Uint8, 16, cute.AddressSpace.gmem, assumed_align=16\n )\n scale_storage_fake = make_ptr(\n cutlass.Uint8, 16, cute.AddressSpace.gmem, assumed_align=16\n )\n\n barrier_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n barrier_epoch_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n pair_head_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n task_head_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n task_tail_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n\n task_expert_fake = make_ptr(\n cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n task_valid_rows_fake = make_ptr(\n cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n\n b_w13_fake = cute.runtime.make_fake_compact_tensor(\n weight_dtype,\n (w1_rows, k, E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_w13_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n b_down_fake = cute.runtime.make_fake_compact_tensor(\n weight_dtype,\n (k, n, E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_down_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n row_counts_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (E,), assumed_align=4\n )\n expert_write_rows_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (E,), assumed_align=4\n )\n expert_tile_base_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (E + 1,), assumed_align=4\n )\n input_gs_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype, (E,), assumed_align=16\n )\n alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype, (E,), assumed_align=16\n )\n down_alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype, (E,), assumed_align=16\n )\n global_scale_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype, (E,), assumed_align=16\n )\n scatter_fake = make_ptr(a_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n token_map_fake = make_ptr(cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4)\n token_weights_fake = make_ptr(\n alpha_dtype, 16, cute.AddressSpace.gmem, assumed_align=16\n )\n\n compiled = cute.compile(\n launch,\n a_input_fake,\n topk_ids_fake,\n topk_weights_fake,\n packed_a_fake,\n sfa_fake,\n packed_a_storage_fake,\n scale_storage_fake,\n barrier_count_fake,\n barrier_epoch_fake,\n pair_head_fake,\n task_head_fake,\n task_tail_fake,\n task_expert_fake,\n task_valid_rows_fake,\n b_w13_fake,\n sfb_w13_fake,\n b_down_fake,\n sfb_down_fake,\n row_counts_fake,\n expert_write_rows_fake,\n expert_tile_base_fake,\n input_gs_fake,\n alpha_fake,\n down_alpha_fake,\n global_scale_fake,\n scatter_fake,\n token_map_fake,\n token_weights_fake,\n 1,\n 1,\n 1,\n 1, # runtime Int32 placeholders\n mac,\n current_cuda_stream(),\n options=\"--opt-level 2 --enable-tvm-ffi\",\n )\n\n result = (compiled, mac)\n _DYNAMIC_KERNEL_CACHE[cache_key] = result\n return result\n\n\n# ---------------------------------------------------------------------------\n# Dynamic launch\n# ---------------------------------------------------------------------------\ndef launch_sm120_dynamic_moe(\n *,\n workspace: Sm120DynamicMoEWorkspace,\n weights: _WeightViews,\n a: torch.Tensor,\n topk_ids: torch.Tensor,\n topk_weights: torch.Tensor,\n input_gs: torch.Tensor,\n down_input_scale: torch.Tensor,\n scatter_output: torch.Tensor,\n num_experts: int,\n num_tokens: int,\n k: int,\n n: int,\n top_k: int,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n) -> torch.Tensor:\n \"\"\"Launch the SM120 dynamic MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 dynamic launcher\"\n )\n _check_memref_limit(\"scatter_output\", scatter_output.numel())\n flat_ids = topk_ids.view(-1).to(torch.int32)\n flat_weights = topk_weights.view(-1).to(torch.float32)\n input_gs_is_shared = input_gs.numel() == 1\n\n # Broadcast scalar scales to per-expert [E] tensors\n input_gs = _expand_to_experts(input_gs, num_experts)\n down_input_scale = _expand_to_experts(down_input_scale, num_experts)\n\n compiled, mac = _get_dynamic_kernel(\n num_experts,\n num_tokens,\n k,\n n,\n top_k,\n workspace.max_rows,\n topk_ids_dtype=torch.int32,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n activation_precision=activation_precision,\n share_input_across_experts=input_gs_is_shared,\n tile_m=workspace.tile_m,\n )\n\n # Dynamic kernel: runtime-shaped args are DataPointer (pass data_ptr()),\n # fixed-shape args are Tensor (pass torch tensor directly).\n runtime_args: Tuple[Any, ...] = (\n a.data_ptr(),\n flat_ids.data_ptr(),\n flat_weights.data_ptr(),\n workspace.packed_a_view.data_ptr(),\n workspace.packed_input_scale.data_ptr(),\n workspace.packed_a_flat.data_ptr(),\n workspace.scale_flat.data_ptr(),\n workspace.barrier_count,\n workspace.barrier_epoch,\n workspace.pair_head,\n workspace.task_head,\n workspace.task_tail,\n workspace.task_expert.data_ptr(),\n workspace.task_valid_rows.data_ptr(),\n weights.w13_fp4,\n weights._w13_sf_storage.data_ptr(),\n weights.down_fp4,\n weights._down_sf_storage.data_ptr(),\n workspace.row_counts,\n workspace.expert_write_rows,\n workspace.expert_tile_base,\n input_gs,\n weights.w1_alpha,\n weights.w2_alpha,\n down_input_scale,\n scatter_output.data_ptr(),\n workspace.token_map.data_ptr(),\n workspace.token_weights.data_ptr(),\n num_tokens,\n workspace.max_rows,\n workspace.physical_tiles_capacity * workspace.tile_m,\n workspace.task_capacity,\n )\n compiled(*runtime_args, current_cuda_stream())\n\n return scatter_output\n\n\n# ==========================================================================\n# W4A16 route-packing implementation\n# ==========================================================================\n@dataclass(kw_only=True)\nclass Sm120W4A16MoEWorkspace:\n \"\"\"Scratch buffers for the SM120 W4A16 MoE path.\"\"\"\n\n state_E: int\n weight_E: int\n max_rows: int\n k: int\n n: int\n num_topk: int\n device: torch.device\n activation: str\n activation_precision: str\n quant_mode: str\n routed_rows_capacity: int\n route_num_experts: int\n\n intermediate_cache13: torch.Tensor\n intermediate_cache2: torch.Tensor\n fc1_c_tmp: torch.Tensor\n fc2_c_tmp: torch.Tensor\n packed_route_indices: torch.Tensor\n block_expert_ids: torch.Tensor\n packed_route_count: torch.Tensor\n expert_offsets: torch.Tensor\n expert_map: torch.Tensor | None = None\n\n\ndef _is_cuda_graph_capturing() -> bool:\n try:\n return bool(torch.cuda.is_current_stream_capturing())\n except Exception:\n return False\n\n\ndef _canonical_cuda_device(device: torch.device) -> torch.device:\n device = torch.device(device)\n if device.type == \"cuda\" and device.index is None:\n return torch.device(\"cuda\", torch.cuda.current_device())\n return device\n\n\ndef _w4a16_workspace_geometry(\n *,\n routed_rows: int,\n route_num_experts: int,\n num_topk: int,\n k: int,\n n: int,\n is_gated: bool,\n device: torch.device,\n) -> tuple[int, int, int, int, int]:\n route_slots = 1\n route_blocks = 1\n fc1_c_tmp_elements = 1\n fc2_c_tmp_elements = 1\n fc1_cols = (2 if is_gated else 1) * int(n)\n sms = get_num_sm(device)\n # Size the route buffers for the power-of-2 capacity so route packing keeps\n # a single triton specialization across token counts.\n routed_rows_capacity = route_pack_numel_capacity(\n int(routed_rows), topk=int(num_topk)\n )\n for block_size in _W4A16_ALLOWED_ROUTED_SIZES:\n slots = max_packed_route_slots(\n routed_rows_capacity,\n int(block_size),\n int(route_num_experts),\n )\n blocks = (slots + int(block_size) - 1) // int(block_size)\n route_slots = max(route_slots, slots)\n route_blocks = max(route_blocks, blocks)\n fc1_c_tmp_elements = max(\n fc1_c_tmp_elements,\n packed_gemm_scratch_elements(\n size_n=fc1_cols,\n route_slots=slots,\n moe_block_size=int(block_size),\n sms=sms,\n ),\n )\n fc2_c_tmp_elements = max(\n fc2_c_tmp_elements,\n packed_gemm_scratch_elements(\n size_n=int(k),\n route_slots=slots,\n moe_block_size=int(block_size),\n sms=sms,\n ),\n )\n return (\n route_slots,\n route_blocks,\n fc1_c_tmp_elements,\n fc2_c_tmp_elements,\n fc1_cols,\n )\n\n\ndef _make_w4a16_expert_map(\n *,\n state_E: int,\n weight_E: int,\n device: torch.device,\n) -> torch.Tensor | None:\n if int(state_E) == int(weight_E):\n return None\n if int(state_E) > int(weight_E):\n raise ValueError(\"num_local_experts cannot exceed num_experts\")\n expert_map = torch.empty((int(weight_E),), dtype=torch.int32, device=device)\n expert_map.fill_(-1)\n expert_map[: int(state_E)].copy_(\n torch.arange(int(state_E), dtype=torch.int32, device=device)\n )\n return expert_map\n\n\ndef _allocate_sm120_w4a16_workspace(\n *,\n state_E: int,\n weight_E: int,\n routed_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation: str = \"silu\",\n) -> Sm120W4A16MoEWorkspace:\n is_gated = validate_activation(activation)\n routed_rows = max(1, int(routed_rows))\n route_num_experts = int(weight_E) if int(state_E) != int(weight_E) else int(state_E)\n (\n route_slots,\n route_blocks,\n fc1_c_tmp_elements,\n fc2_c_tmp_elements,\n fc1_cols,\n ) = _w4a16_workspace_geometry(\n routed_rows=routed_rows,\n route_num_experts=route_num_experts,\n num_topk=num_topk,\n k=k,\n n=n,\n is_gated=is_gated,\n device=device,\n )\n return Sm120W4A16MoEWorkspace(\n state_E=int(state_E),\n weight_E=int(weight_E),\n max_rows=routed_rows,\n k=int(k),\n n=int(n),\n num_topk=int(num_topk),\n device=device,\n activation=activation,\n activation_precision=\"bf16\",\n quant_mode=\"w4a16\",\n routed_rows_capacity=routed_rows,\n route_num_experts=route_num_experts,\n intermediate_cache13=torch.empty(\n (routed_rows * max(fc1_cols, int(k)),),\n dtype=torch.bfloat16,\n device=device,\n ),\n intermediate_cache2=torch.empty(\n (routed_rows, int(n)),\n dtype=torch.bfloat16,\n device=device,\n ),\n fc1_c_tmp=torch.empty(\n (fc1_c_tmp_elements,),\n dtype=torch.float32,\n device=device,\n ),\n fc2_c_tmp=torch.empty(\n (fc2_c_tmp_elements,),\n dtype=torch.float32,\n device=device,\n ),\n packed_route_indices=torch.empty(\n (route_slots,),\n dtype=torch.int32,\n device=device,\n ),\n block_expert_ids=torch.empty(\n (route_blocks,),\n dtype=torch.int32,\n device=device,\n ),\n packed_route_count=torch.empty((1,), dtype=torch.int32, device=device),\n expert_offsets=torch.empty(\n (route_num_experts + 1,),\n dtype=torch.int32,\n device=device,\n ),\n expert_map=_make_w4a16_expert_map(\n state_E=state_E,\n weight_E=weight_E,\n device=device,\n ),\n )\n\n\n_W4A16_WEIGHT_CACHE: Dict[Tuple, W4A16PackedWeights] = {}\n\n\ndef _get_w4a16_packed_weights(\n *,\n w1_weight: torch.Tensor,\n w1_weight_sf: torch.Tensor,\n w1_alpha: torch.Tensor,\n w2_weight: torch.Tensor,\n w2_weight_sf: torch.Tensor,\n w2_alpha: torch.Tensor,\n activation: str,\n params_dtype: torch.dtype,\n source_format: str = \"modelopt\",\n) -> W4A16PackedWeights:\n key = (\n activation,\n params_dtype,\n source_format,\n tuple(w1_weight.shape),\n tuple(w1_weight_sf.shape),\n tuple(w1_alpha.shape),\n tuple(w2_weight.shape),\n tuple(w2_weight_sf.shape),\n tuple(w2_alpha.shape),\n w1_weight.data_ptr(),\n w1_weight_sf.data_ptr(),\n w1_alpha.data_ptr(),\n w2_weight.data_ptr(),\n w2_weight_sf.data_ptr(),\n w2_alpha.data_ptr(),\n )\n cached = _W4A16_WEIGHT_CACHE.get(key)\n if cached is not None:\n return cached\n if _is_cuda_graph_capturing():\n raise RuntimeError(\n \"W4A16 packed weights are not initialized for CUDA graph capture; \"\n \"run once before capture so the prepared weights are cached.\"\n )\n prepared = prepare_w4a16_packed_weights(\n w1_weight,\n w1_weight_sf,\n w1_alpha,\n w2_weight,\n w2_weight_sf,\n w2_alpha,\n activation=activation,\n params_dtype=params_dtype,\n source_format=source_format,\n )\n _W4A16_WEIGHT_CACHE[key] = prepared\n _register_cache_eviction(\n _W4A16_WEIGHT_CACHE,\n key,\n w1_weight,\n w1_weight_sf,\n w1_alpha,\n w2_weight,\n w2_weight_sf,\n w2_alpha,\n )\n return prepared\n\n\ndef _validate_w4a16_workspace(\n workspace: Sm120W4A16MoEWorkspace,\n *,\n state_E: int,\n weight_E: int,\n routed_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation: str,\n) -> None:\n validate_activation(activation)\n if workspace.state_E != int(state_E) or workspace.weight_E != int(weight_E):\n raise ValueError(\"pre-allocated W4A16 workspace expert geometry mismatch\")\n if workspace.k != int(k) or workspace.n != int(n):\n raise ValueError(\"pre-allocated W4A16 workspace hidden geometry mismatch\")\n if workspace.num_topk != int(num_topk):\n raise ValueError(\"pre-allocated W4A16 workspace top-k mismatch\")\n if getattr(workspace, \"activation\", None) != activation:\n raise ValueError(\"pre-allocated W4A16 workspace activation mismatch\")\n if _canonical_cuda_device(workspace.device) != _canonical_cuda_device(device):\n raise ValueError(\n f\"pre-allocated W4A16 workspace is on {workspace.device}, expected {device}\"\n )\n if workspace.routed_rows_capacity < max(1, int(routed_rows)):\n raise ValueError(\n \"pre-allocated W4A16 workspace is too small for the requested \"\n f\"routed rows ({workspace.routed_rows_capacity} < {routed_rows})\"\n )\n\n\ndef _launch_sm120_w4a16_moe(\n *,\n a: torch.Tensor,\n topk_ids: torch.Tensor,\n topk_weights: torch.Tensor,\n w1_weight: torch.Tensor,\n w1_weight_sf: torch.Tensor,\n w1_alpha: torch.Tensor,\n w2_weight: torch.Tensor,\n w2_weight_sf: torch.Tensor,\n w2_alpha: torch.Tensor,\n num_experts: int,\n top_k: int,\n num_local_experts: int,\n scatter_output: torch.Tensor,\n fast_math: bool = True,\n activation: str = \"silu\",\n source_format: str = \"modelopt\",\n _workspace=None,\n _prepared_weights=None,\n) -> torch.Tensor:\n prepared = (\n _prepared_weights\n if isinstance(_prepared_weights, W4A16PackedWeights)\n else _get_w4a16_packed_weights(\n w1_weight=w1_weight,\n w1_weight_sf=w1_weight_sf,\n w1_alpha=w1_alpha,\n w2_weight=w2_weight,\n w2_weight_sf=w2_weight_sf,\n w2_alpha=w2_alpha,\n activation=activation,\n params_dtype=a.dtype,\n source_format=source_format,\n )\n )\n if int(prepared.num_experts) != int(num_local_experts):\n raise ValueError(\"num_local_experts must match w1_weight.shape[0] for W4A16.\")\n num_tokens = int(topk_ids.size(0))\n routed_rows = num_tokens * int(top_k)\n k = int(a.size(1))\n n = int(prepared.intermediate_size)\n\n if _workspace is None:\n workspace = _get_cached_workspace(\n backend=\"w4a16\",\n state_E=num_local_experts,\n weight_E=num_experts,\n routed_rows=routed_rows,\n k=k,\n n=n,\n num_topk=top_k,\n device=a.device,\n quant_mode=\"w4a16\",\n activation=activation,\n )\n else:\n workspace = _workspace\n if not isinstance(workspace, Sm120W4A16MoEWorkspace):\n raise TypeError(\"expected a W4A16 workspace for quant_mode='w4a16'\")\n _validate_w4a16_workspace(\n workspace,\n state_E=num_local_experts,\n weight_E=num_experts,\n routed_rows=routed_rows,\n k=k,\n n=n,\n num_topk=top_k,\n device=a.device,\n activation=activation,\n )\n\n return run_w4a16_moe(\n a,\n prepared,\n topk_weights,\n topk_ids,\n activation=activation,\n intermediate_cache13=workspace.intermediate_cache13,\n intermediate_cache2=workspace.intermediate_cache2,\n output=scatter_output,\n fc1_c_tmp=workspace.fc1_c_tmp,\n fc2_c_tmp=workspace.fc2_c_tmp,\n packed_route_indices=workspace.packed_route_indices,\n block_expert_ids=workspace.block_expert_ids,\n packed_route_count=workspace.packed_route_count,\n expert_offsets=workspace.expert_offsets,\n expert_map=workspace.expert_map,\n fast_math=fast_math,\n )\n\n\n# ==========================================================================\n# Workspace cache (for functional API path)\n# ==========================================================================\n\n_Sm120Workspace = Union[\n Sm120StaticMoEWorkspace,\n Sm120DynamicMoEWorkspace,\n Sm120W4A16MoEWorkspace,\n]\n\n# Stores the workspace with the largest capacity seen per key and never\n# shrinks within a process. clear_sm120_moe_caches() releases everything.\n_WORKSPACE_CACHE: Dict[Tuple, _Sm120Workspace] = {}\n\n\ndef clear_sm120_moe_caches() -> None:\n \"\"\"Release every module-level SM12x MoE cache.\n\n References held by callers are unaffected.\n \"\"\"\n _WORKSPACE_CACHE.clear()\n _WEIGHT_CACHE.clear()\n _W4A16_WEIGHT_CACHE.clear()\n _PADDED_WEIGHT_CACHE.clear()\n _STATIC_KERNEL_CACHE.clear()\n _MICRO_KERNEL_CACHE.clear()\n _DIRECT_MICRO_LAUNCH_CACHE.clear()\n _DIRECT_MICRO_KERNEL_CACHE.clear()\n _DYNAMIC_KERNEL_CACHE.clear()\n\n\ndef allocate_sm120_moe_workspace(\n *,\n state_E: int,\n weight_E: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n max_rows: int | None = None,\n routed_rows: int | None = None,\n quant_mode: str | None = None,\n activation_precision: str | None = None,\n backend: str | None = None,\n activation: str = \"silu\",\n) -> _Sm120Workspace:\n \"\"\"Allocate the right SM120 MoE workspace from a quantization mode.\"\"\"\n mode = _normalize_quant_mode(quant_mode, activation_precision)\n capacity_rows = routed_rows if routed_rows is not None else max_rows\n if capacity_rows is None:\n raise ValueError(\"routed_rows or max_rows is required\")\n capacity_rows = max(1, int(capacity_rows))\n device = torch.device(device)\n\n if mode == \"w4a16\":\n if backend not in (None, \"w4a16\"):\n raise ValueError(\"quant_mode='w4a16' does not use static/dynamic backend\")\n return _allocate_sm120_w4a16_workspace(\n state_E=state_E,\n weight_E=weight_E,\n routed_rows=capacity_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation=activation,\n )\n\n activation_precision = \"fp4\"\n if backend is None:\n backend = select_sm120_moe_backend(\n num_tokens=max(\n 1, (capacity_rows + max(1, int(num_topk)) - 1) // max(1, int(num_topk))\n ),\n num_topk=int(num_topk),\n activation_precision=activation_precision,\n )\n if backend == \"dynamic\":\n return allocate_sm120_dynamic_workspace(\n state_E=state_E,\n weight_E=weight_E,\n routed_rows=capacity_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation_precision=activation_precision,\n activation=activation,\n )\n if backend == \"static\":\n return allocate_sm120_static_workspace(\n state_E=state_E,\n weight_E=weight_E,\n max_rows=capacity_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation_precision=activation_precision,\n )\n raise ValueError(f\"unsupported SM120 MoE backend {backend!r}\")\n\n\ndef _get_cached_workspace(\n *,\n backend: str,\n state_E: int,\n weight_E: int,\n routed_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation_precision: str = \"fp4\",\n quant_mode: str | None = None,\n activation: str = \"silu\",\n) -> _Sm120Workspace:\n \"\"\"Get or allocate a cached workspace for the given problem shape.\n\n Reuses the cached workspace if it has enough capacity for the requested\n routed_rows. For static workspaces, max_rows is the direct capacity.\n For dynamic workspaces, routed_rows_capacity is used because the dynamic\n geometry (physical tiles, task queue slots) depends on the original\n routed_rows, not just max_rows.\n \"\"\"\n quant_mode = _normalize_quant_mode(quant_mode, activation_precision)\n activation_precision = _activation_precision_from_quant_mode(quant_mode)\n # Key dynamic workspaces on the tile band of this call's routed_rows; a\n # larger cached workspace must not pin small calls to its 128 tile.\n tile_m = (\n _select_dynamic_tile_m(max(1, routed_rows), state_E, activation)\n if backend == \"dynamic\" and quant_mode != \"w4a16\"\n else None\n )\n cache_key = (\n state_E,\n weight_E,\n k,\n n,\n num_topk,\n str(device),\n backend,\n quant_mode,\n activation,\n tile_m,\n )\n cached = _WORKSPACE_CACHE.get(cache_key)\n\n if cached is not None:\n if isinstance(cached, Sm120DynamicMoEWorkspace):\n if cached.routed_rows_capacity >= max(1, routed_rows):\n assert tile_m is None or cached.tile_m == tile_m\n return cached\n elif isinstance(cached, Sm120W4A16MoEWorkspace):\n if cached.routed_rows_capacity >= max(1, routed_rows):\n return cached\n else:\n if cached.max_rows >= max(1, routed_rows):\n return cached\n\n if quant_mode == \"w4a16\" and _is_cuda_graph_capturing():\n raise RuntimeError(\n \"W4A16 workspace is not initialized for CUDA graph capture; \"\n \"provide a preallocated workspace from \"\n \"allocate_sm120_moe_workspace(..., quant_mode='w4a16') or warm the \"\n \"functional path before capture.\"\n )\n workspace = allocate_sm120_moe_workspace(\n state_E=state_E,\n weight_E=weight_E,\n routed_rows=routed_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n quant_mode=quant_mode,\n activation_precision=activation_precision,\n backend=backend,\n activation=activation,\n )\n\n _WORKSPACE_CACHE[cache_key] = workspace\n return workspace\n\n\n# ==========================================================================\n# Unified dispatch\n# ==========================================================================\n_PADDED_WEIGHT_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _pad_intermediate_to_tile(\n w1_weight,\n w1_weight_sf,\n w2_weight,\n w2_weight_sf,\n fc2_input_scale,\n n,\n tile,\n h,\n num_experts,\n is_gated,\n):\n \"\"\"Zero-pad NVFP4 weights + scale factors so the intermediate size is a\n multiple of ``tile`` (gate/up tile-split requirement); padded channels are\n zero, so the result is numerically identical.\n \"\"\"\n n_pad = ((n + tile - 1) // tile) * tile\n if n_pad == n:\n return w1_weight, w1_weight_sf, w2_weight, w2_weight_sf, fc2_input_scale, n\n E = int(num_experts)\n fc2_input_scale_src = fc2_input_scale\n key = (\n n,\n tile,\n h,\n E,\n bool(is_gated),\n w1_weight.data_ptr(),\n w1_weight_sf.data_ptr(),\n w2_weight.data_ptr(),\n w2_weight_sf.data_ptr(),\n fc2_input_scale_src.data_ptr() if fc2_input_scale_src is not None else 0,\n )\n cached = _PADDED_WEIGHT_CACHE.get(key)\n if cached is not None:\n return cached\n\n def mma_to_logical(sf, m, k):\n sw = convert_sf_from_mma_layout(sf, m=m, k=k, num_groups=E)\n m_pad = ((m + 127) // 128) * 128\n sw = sw.reshape(E, m_pad, -1)\n cb = (k + SF_VEC_SIZE - 1) // SF_VEC_SIZE\n return torch.stack(\n [unswizzle_block_scale(sw[e], rows=m, cols_blocks=cb) for e in range(E)], 0\n )\n\n def logical_to_mma(log, m, k):\n sw = torch.stack([swizzle_block_scale(log[e]) for e in range(E)], 0)\n sw2d = sw.reshape(E * sw.shape[1], sw.shape[2]).to(torch.float8_e4m3fn)\n return convert_sf_to_mma_layout(sw2d, m=m, k=k, num_groups=E)\n\n def pad_dim(t, dim, old, new):\n if new == old:\n return t\n shp = list(t.shape)\n shp[dim] = new - old\n return torch.cat([t, t.new_zeros(shp)], dim=dim)\n\n if is_gated:\n # w1 packs [up(0:n), gate(n:2n)] rows; pad each half so the split stays\n # tile-aligned, then re-concat.\n up, gate = w1_weight[:, :n, :], w1_weight[:, n : 2 * n, :]\n w1p = torch.cat([pad_dim(up, 1, n, n_pad), pad_dim(gate, 1, n, n_pad)], dim=1)\n log1 = mma_to_logical(w1_weight_sf, m=2 * n, k=h)\n up_sf, gate_sf = log1[:, :n, :], log1[:, n : 2 * n, :]\n log1p = torch.cat(\n [pad_dim(up_sf, 1, n, n_pad), pad_dim(gate_sf, 1, n, n_pad)], dim=1\n )\n w1_sf_p = logical_to_mma(log1p, m=2 * n_pad, k=h)\n else:\n w1p = pad_dim(w1_weight, 1, n, n_pad)\n log1 = mma_to_logical(w1_weight_sf, m=n, k=h)\n w1_sf_p = logical_to_mma(pad_dim(log1, 1, n, n_pad), m=n_pad, k=h)\n\n # w2 reduces over the intermediate dim: pad its packed columns + SF columns.\n w2p = pad_dim(w2_weight, 2, n // 2, n_pad // 2)\n log2 = mma_to_logical(w2_weight_sf, m=h, k=n)\n cb_n = (n + SF_VEC_SIZE - 1) // SF_VEC_SIZE\n cb_np = (n_pad + SF_VEC_SIZE - 1) // SF_VEC_SIZE\n w2_sf_p = logical_to_mma(pad_dim(log2, 2, cb_n, cb_np), m=h, k=n_pad)\n\n if fc2_input_scale_src is not None and fc2_input_scale_src.numel() == n:\n fc2_input_scale = pad_dim(fc2_input_scale_src, 0, n, n_pad)\n result = (w1p, w1_sf_p, w2p, w2_sf_p, fc2_input_scale, n_pad)\n _PADDED_WEIGHT_CACHE[key] = result\n _register_cache_eviction(\n _PADDED_WEIGHT_CACHE,\n key,\n w1_weight,\n w1_weight_sf,\n w2_weight,\n w2_weight_sf,\n fc2_input_scale_src,\n )\n return result\n\n\ndef launch_sm120_moe(\n *,\n a: torch.Tensor,\n topk_ids: torch.Tensor,\n topk_weights: torch.Tensor,\n w1_weight: torch.Tensor,\n w1_weight_sf: torch.Tensor,\n w1_alpha: torch.Tensor,\n fc2_input_scale: Optional[torch.Tensor] = None,\n input_global_scale: Optional[torch.Tensor] = None,\n w2_weight: torch.Tensor,\n w2_weight_sf: torch.Tensor,\n w2_alpha: torch.Tensor,\n num_experts: int,\n top_k: int,\n num_local_experts: int,\n scatter_output: torch.Tensor,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n quant_mode: str | None = None,\n source_format: str = \"modelopt\",\n _workspace=None,\n _weight_views=None,\n _prepared_weights=None,\n) -> torch.Tensor:\n \"\"\"Unified SM120 MoE dispatch — selects static or dynamic by token count.\n\n input_global_scale overrides w1_alpha as the FC1 input-quant scale and\n is folded into the multiplier internally. With _weight_views supplied,\n w1_alpha must already contain the fold.\n\n Optional _workspace and _weight_views can be pre-allocated and reused\n across calls to avoid per-call allocation overhead (wrapper path).\n When not provided (functional API path), a module-level workspace cache\n is used to avoid re-allocating on every call.\n \"\"\"\n quant_mode = _normalize_quant_mode(quant_mode, activation_precision)\n source_format = _normalize_source_format_for_quant_mode(source_format, quant_mode)\n activation_precision = _activation_precision_from_quant_mode(quant_mode)\n\n num_tokens = topk_ids.size(0)\n k = a.size(1) # hidden_size\n is_gated = is_gated_activation(activation)\n # w1_weight.size(1) is 2*n for gated or n for non-gated\n intermediate_size = w1_weight.size(1) // 2 if is_gated else w1_weight.size(1)\n n = intermediate_size\n\n # NVFP4 kernels need padded intermediate size.\n if quant_mode != \"w4a16\" and n % _LEVEL_TILE_N != 0 and _weight_views is None:\n (\n w1_weight,\n w1_weight_sf,\n w2_weight,\n w2_weight_sf,\n fc2_input_scale,\n n,\n ) = _pad_intermediate_to_tile(\n w1_weight,\n w1_weight_sf,\n w2_weight,\n w2_weight_sf,\n fc2_input_scale,\n n,\n _LEVEL_TILE_N,\n k,\n w1_weight.size(0),\n is_gated,\n )\n\n routed_rows = num_tokens * top_k\n\n if quant_mode == \"w4a16\":\n return _launch_sm120_w4a16_moe(\n a=a,\n topk_ids=topk_ids,\n topk_weights=topk_weights,\n w1_weight=w1_weight,\n w1_weight_sf=w1_weight_sf,\n w1_alpha=w1_alpha,\n w2_weight=w2_weight,\n w2_weight_sf=w2_weight_sf,\n w2_alpha=w2_alpha,\n num_experts=num_experts,\n top_k=top_k,\n num_local_experts=num_local_experts,\n scatter_output=scatter_output,\n fast_math=fast_math,\n activation=activation,\n source_format=source_format,\n _workspace=_workspace,\n _prepared_weights=_prepared_weights,\n )\n\n if fc2_input_scale is None:\n raise ValueError(\"fc2_input_scale is required when quant_mode='nvfp4'.\")\n down_input_scale = fc2_input_scale\n if input_global_scale is not None:\n input_gs = input_global_scale\n if _weight_views is None:\n # Alpha must carry input_gs back or the output magnitude is wrong.\n # The wrapper folds before building _weight_views; don't fold twice.\n w1_alpha = (\n w1_alpha.to(torch.float32) * input_global_scale.to(torch.float32)\n ).contiguous()\n else:\n input_gs = w1_alpha\n\n weights = (\n _weight_views\n if _weight_views is not None\n else _get_weight_views(\n w1_fp4=w1_weight,\n w1_blockscale=w1_weight_sf,\n w2_fp4=w2_weight,\n w2_blockscale=w2_weight_sf,\n w1_alphas=w1_alpha,\n w2_alphas=w2_alpha,\n n=n,\n k=k,\n activation_precision=activation_precision,\n )\n )\n\n # Resolve workspace and backend selection.\n # When a pre-allocated workspace is provided (CUDA graph wrapper path),\n # infer the backend from the workspace type so they stay in sync —\n # the caller already committed to a backend at allocation time.\n if _workspace is not None:\n workspace = _workspace\n workspace_activation_precision = getattr(\n workspace, \"activation_precision\", activation_precision\n )\n if workspace_activation_precision != activation_precision:\n raise ValueError(\n \"pre-allocated workspace activation_precision does not match \"\n f\"requested activation_precision={activation_precision!r}.\"\n )\n if isinstance(workspace, Sm120DynamicMoEWorkspace):\n if num_local_experts != num_experts:\n raise ValueError(\n \"pre-allocated dynamic SM120 MoE workspace requires \"\n \"num_local_experts == num_experts because dynamic expert \"\n \"buffers are indexed by global topk ids.\"\n )\n # A pre-allocated dynamic workspace keeps its stored tile_m even\n # for smaller calls; its geometry was sized for that tile.\n backend = \"dynamic\"\n else:\n backend = \"static\"\n else:\n backend = select_sm120_moe_backend(\n num_tokens=num_tokens,\n num_topk=top_k,\n activation_precision=activation_precision,\n )\n # The dynamic kernel indexes row_counts/expert_write_rows directly with\n # topk_ids but those buffers are sized with num_local_experts. Unless\n # num_local_experts == num_experts, fall back to the static backend which\n # has global-to-local expert remapping.\n if backend == \"dynamic\" and num_local_experts != num_experts:\n backend = \"static\"\n workspace = _get_cached_workspace(\n backend=backend,\n state_E=num_local_experts,\n weight_E=num_experts,\n routed_rows=routed_rows,\n k=k,\n n=n,\n num_topk=top_k,\n device=a.device,\n activation_precision=activation_precision,\n quant_mode=quant_mode,\n activation=activation,\n )\n\n if backend == \"dynamic\":\n return launch_sm120_dynamic_moe(\n workspace=workspace,\n weights=weights,\n a=a,\n topk_ids=topk_ids,\n topk_weights=topk_weights,\n input_gs=input_gs,\n down_input_scale=down_input_scale,\n scatter_output=scatter_output,\n num_experts=num_experts,\n num_tokens=num_tokens,\n k=k,\n n=n,\n top_k=top_k,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n activation_precision=activation_precision,\n )\n else:\n return launch_sm120_static_moe(\n workspace=workspace,\n weights=weights,\n a=a,\n topk_ids=topk_ids,\n topk_weights=topk_weights,\n input_gs=input_gs,\n down_input_scale=down_input_scale,\n scatter_output=scatter_output,\n num_experts=num_experts,\n num_tokens=num_tokens,\n k=k,\n n=n,\n top_k=top_k,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n activation_precision=activation_precision,\n )\n"},"after_code":{"kind":"string","value":"\"\"\"SM120/SM121 MoE dispatch layer — workspace, compilation, and launch.\n\nPorted from b12x's integration/tp_moe.py. Supports micro (tiny decode),\nstatic (decode), and dynamic (prefill) backends with token-count-based\nselection.\n\"\"\"\n\nfrom __future__ import annotations\n\nimport hashlib\nimport os\nimport weakref\nfrom dataclasses import dataclass\nfrom typing import Any, Dict, Optional, Tuple, Union\n\nimport cutlass\nimport cutlass.cute as cute\nimport torch\n\nfrom flashinfer.cute_dsl.utils import (\n convert_sf_from_mma_layout,\n convert_sf_to_mma_layout,\n get_max_active_clusters,\n get_num_sm,\n make_ptr,\n)\nfrom flashinfer.jit.cute_dsl_core import build_and_load_cute_dsl_kernel\nfrom .moe_activation import SWIGLUOAI_UNINTERLEAVE, is_gated_activation\nfrom .moe_direct_micro_kernel import (\n MoEDirectMicroKernel,\n build_direct_micro_kernel,\n compile_direct_micro_kernel,\n compiled_direct_micro_accepts_block_dim,\n)\nfrom .moe_dynamic_kernel import (\n _MAX_SHARED_INPUT_TOPK,\n _TASK_SLICE_CHUNK,\n MoEDynamicKernel,\n)\nfrom .moe_micro_kernel import MoEMicroKernel\nfrom .moe_static_kernel import MoEStaticKernel\nfrom .moe_w4a16_fp4_helpers import swizzle_block_scale\nfrom .moe_w4a16_host import (\n _W4A16_ALLOWED_ROUTED_SIZES,\n max_packed_route_slots,\n packed_gemm_scratch_elements,\n route_pack_numel_capacity,\n unswizzle_block_scale,\n validate_activation,\n)\nfrom .moe_w4a16_kernel import run_w4a16_moe\nfrom .moe_w4a16_prepare import (\n W4A16PackedWeights,\n _normalize_source_format,\n prepare_w4a16_packed_weights,\n)\n\n# ---------------------------------------------------------------------------\n# Constants\n# ---------------------------------------------------------------------------\n_NVFP4_BLOCK_SIZE = 16\n_LEVEL_TILE_M = 128\n_LEVEL_TILE_N = 128\n# Must equal the kernel's task materialization granularity or the task\n# queue is mis-sized.\n_DYNAMIC_SLICE_CHUNK = _TASK_SLICE_CHUNK\nSF_VEC_SIZE = 16\n_FORCE_MOE_W4A16_ENV = \"FLASHINFER_B12X_FORCE_MOE_W4A16\"\n_MICRO_SHARE_INPUT_ACROSS_EXPERTS = (\n os.environ.get(\"FLASHINFER_B12X_MICRO_SHARE_INPUT\", \"1\") != \"0\"\n)\n\n# Micro kernel cutover thresholds (routed pairs)\n_MICRO_COMPACT_CUTOVER_PAIRS = 20\n_MICRO_COMPACT_CUTOVER_PAIRS_MULTI_TOPK = 40\n# The micro kernel's per-token staging assumes decode-sized batches.\n_MICRO_MAX_TOKENS = 8\n# Direct micro takes the smallest decode batches ahead of the MMA micro\n# kernel, and only at small intermediate sizes where its CUDA-core dots\n# keep up with per-token work. Measured on GB10, pending other GPUs.\n_DIRECT_MICRO_CUTOVER_PAIRS = 32\n_DIRECT_MICRO_MAX_N = 512\n# Test/bench hook: force one backend (\"direct_micro\", \"micro\", \"static\",\n# \"dynamic\"). Deliberately module-level (a monkeypatch target), not an env var.\n_FORCED_BACKEND: str | None = None\n_STATIC_COMPACT_CUTOVER_PAIRS_DEFAULT = 640\n_STATIC_COMPACT_CUTOVER_PAIRS = _STATIC_COMPACT_CUTOVER_PAIRS_DEFAULT\n_STATIC_COMPACT_CUTOVER_PAIRS_CACHE: Dict[str, int] = {}\n\n# MAC (max active clusters) tuning ladders from b12x decode profiling.\n# Each entry is (max_routed_rows, optimal_mac).\n_MICRO_MAC_LADDER: Tuple[Tuple[int, int], ...] = (\n (2, 84),\n (4, 127),\n (8, 107),\n (10, 84),\n (16, 63),\n (20, 84),\n)\n_STATIC_MAC_LADDER: Tuple[Tuple[int, int], ...] = (\n (24, 148),\n (32, 169),\n (40, 132),\n (48, 149),\n (64, 134),\n (80, 175),\n (96, 171),\n (120, 125),\n (128, 130),\n (160, 171),\n (192, 166),\n (256, 141),\n (320, 158),\n (512, 175),\n (640, 188),\n)\n# Workloads at or below the static cutover (640 routed pairs by default)\n# take the static kernel, so only the 1024 entry is normally reachable.\n_DYNAMIC_MAC_LADDER: Tuple[Tuple[int, int], ...] = (\n (640, 188),\n (1024, 147),\n)\n\n\ndef _lookup_mac_ladder(\n ladder: Tuple[Tuple[int, int], ...], routed_rows: int\n) -> int | None:\n \"\"\"Look up optimal MAC from a tuning ladder. Returns None if no match.\"\"\"\n for end_rows, mac in ladder:\n if routed_rows <= end_rows:\n return mac\n return None\n\n\ndef _align_up(value: int, alignment: int) -> int:\n return ((value + alignment - 1) // alignment) * alignment\n\n\n# The kernels index the packed activation and scale planes with 32-bit\n# offsets, so reject any workspace plane large enough to overflow them.\n_RUNTIME_MEMREF_LIMIT = (1 << 31) - 1\n\n\ndef _check_memref_limit(name: str, elements: int) -> None:\n if elements > _RUNTIME_MEMREF_LIMIT:\n raise ValueError(\n f\"{name} needs {elements} elements, which exceeds the 2^31-1 \"\n \"runtime memref limit. Reduce the token chunk or expert count \"\n \"for this launch.\"\n )\n\n\ndef _first_env(*names: str) -> str | None:\n for name in names:\n value = os.environ.get(name)\n if value is not None:\n return value\n return None\n\n\ndef _normalize_activation_precision(activation_precision: str) -> str:\n \"\"\"Normalize public activation-precision names to internal modes.\"\"\"\n if os.environ.get(_FORCE_MOE_W4A16_ENV, \"0\") == \"1\":\n return \"bf16\"\n\n normalized = str(activation_precision).lower()\n aliases = {\n \"fp4\": \"fp4\",\n \"nvfp4\": \"fp4\",\n \"w4a4\": \"fp4\",\n \"bf16\": \"bf16\",\n \"w4a16\": \"bf16\",\n }\n try:\n return aliases[normalized]\n except KeyError as exc:\n raise ValueError(\n \"activation_precision must be 'fp4' or 'bf16' \"\n f\"(got {activation_precision!r}).\"\n ) from exc\n\n\ndef _normalize_quant_mode(\n quant_mode: str | None = None,\n activation_precision: str | None = None,\n) -> str:\n \"\"\"Normalize public quantization names to the dispatch mode.\"\"\"\n if os.environ.get(_FORCE_MOE_W4A16_ENV, \"0\") == \"1\":\n return \"w4a16\"\n if quant_mode is None:\n activation_precision = _normalize_activation_precision(\n activation_precision or \"fp4\"\n )\n return \"w4a16\" if activation_precision == \"bf16\" else \"nvfp4\"\n\n normalized = str(quant_mode).lower()\n aliases = {\n \"fp4\": \"nvfp4\",\n \"nvfp4\": \"nvfp4\",\n \"w4a4\": \"nvfp4\",\n \"bf16\": \"w4a16\",\n \"w4a16\": \"w4a16\",\n }\n try:\n return aliases[normalized]\n except KeyError as exc:\n raise ValueError(\n f\"quant_mode must be 'nvfp4'/'w4a4' or 'w4a16' (got {quant_mode!r}).\"\n ) from exc\n\n\ndef _activation_precision_from_quant_mode(quant_mode: str) -> str:\n return \"bf16\" if _normalize_quant_mode(quant_mode) == \"w4a16\" else \"fp4\"\n\n\ndef _normalize_source_format_for_quant_mode(source_format: str, quant_mode: str) -> str:\n normalized = _normalize_source_format(source_format)\n if quant_mode == \"nvfp4\" and normalized == \"compressed_tensors\":\n raise ValueError(\n \"source_format='compressed_tensors' requires quant_mode='w4a16'.\"\n )\n return normalized\n\n\ndef _is_w4a16(activation_precision: str) -> bool:\n return _normalize_activation_precision(activation_precision) == \"bf16\"\n\n\ndef _level_tile_n(activation_precision: str = \"fp4\") -> int:\n if _is_w4a16(activation_precision):\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 tile selector\"\n )\n return _LEVEL_TILE_N\n\n\ndef _select_dynamic_tile_m(\n routed_rows: int,\n num_experts: int,\n activation: str = \"silu\",\n) -> int:\n \"\"\"Pick the dynamic kernel's M-tile from routed rows per expert.\n\n Small tiles cut per-expert tail padding for sparse routing; 128 amortizes\n best for dense prefill (crossovers measured on gated NVFP4). Workspace\n sizing and the kernel build must both derive the tile from this function,\n or the scratch is mis-sized for what the kernel indexes.\n \"\"\"\n if not is_gated_activation(activation):\n return _LEVEL_TILE_M\n routed_rows = max(1, int(routed_rows))\n num_experts = max(1, int(num_experts))\n if routed_rows < 15 * num_experts:\n return 16\n if routed_rows < 48 * num_experts:\n return 32\n if routed_rows < 96 * num_experts:\n return 64\n return _LEVEL_TILE_M\n\n\ndef _get_static_compact_cutover_pairs(activation_precision: str = \"fp4\") -> int:\n activation_precision = _normalize_activation_precision(activation_precision)\n cached = _STATIC_COMPACT_CUTOVER_PAIRS_CACHE.get(activation_precision)\n if cached is not None:\n return cached\n\n cutover_names: tuple[str, ...] = (\n \"FLASHINFER_B12X_STATIC_COMPACT_CUTOVER_PAIRS\",\n \"B12X_STATIC_COMPACT_CUTOVER_PAIRS\",\n \"B12X_DYNAMIC_STATIC_CUTOVER_PAIRS\",\n \"B12X_LEVEL10_STATIC_CUTOVER_PAIRS\",\n )\n cutover = _first_env(*cutover_names)\n if cutover is None:\n cached = _STATIC_COMPACT_CUTOVER_PAIRS_DEFAULT\n else:\n cached = max(0, int(cutover))\n _STATIC_COMPACT_CUTOVER_PAIRS_CACHE[activation_precision] = cached\n return cached\n\n\ndef _select_moe_mma_tiler_mn(\n routed_rows: int,\n n: int,\n *,\n resident_clusters: int | None = None,\n) -> Tuple[int, int]:\n \"\"\"Select optimal MoE tile shape based on routed rows and N dimension.\n\n Uses narrower 64x128 tiles when routed_rows <= 128 and default 128x128\n would leave SMs idle.\n \"\"\"\n sm_count = get_num_sm(torch.device(\"cuda\"))\n coarse_tile = (128, 128)\n if routed_rows <= 32 and n <= 256:\n return (64, 128)\n if resident_clusters is not None and resident_clusters < sm_count:\n return coarse_tile\n coarse_tiles = ((routed_rows + coarse_tile[0] - 1) // coarse_tile[0]) * (\n (n + coarse_tile[1] - 1) // coarse_tile[1]\n )\n # Single-token decode often lands exactly on the \"half the machine\"\n # boundary. Keeping the coarse 128x128 tile there leaves the M dimension\n # badly underfilled, so take the narrow 64x128 tile inclusive of equality.\n if routed_rows <= 64 or (\n routed_rows <= 128 and coarse_tiles <= max(1, sm_count // 2)\n ):\n return (64, 128)\n return (128, 128)\n\n\ndef _as_grouped_scale_view(\n scale_storage: torch.Tensor,\n rows: int,\n cols: int,\n) -> torch.Tensor:\n \"\"\"Create 6D MMA-compatible scale factor view from swizzled storage.\"\"\"\n batch = scale_storage.shape[0]\n rows_padded = _align_up(rows, 128)\n cols_padded = _align_up(cols // SF_VEC_SIZE, 4)\n sf = scale_storage.view(torch.float8_e4m3fn)\n sf = sf.view(batch, rows_padded // 128, cols_padded // 4, 32, 4, 4)\n return sf.permute(3, 4, 1, 5, 2, 0)\n\n\n# ---------------------------------------------------------------------------\n# Workspace\n# ---------------------------------------------------------------------------\n@dataclass(kw_only=True)\nclass Sm120StaticMoEWorkspace:\n \"\"\"Scratch buffers for one SM120 static MoE launch.\"\"\"\n\n state_E: int\n weight_E: int\n max_rows: int\n k: int\n n: int\n num_topk: int\n device: torch.device\n activation_precision: str\n\n # Buffers\n row_counts: torch.Tensor # [state_E] int32\n token_map: torch.Tensor # [state_E, max_rows] int32\n token_weights: torch.Tensor # [state_E, max_rows] float32\n packed_input: torch.Tensor # [state_E, max_rows, k//2] uint8\n packed_input_scale: torch.Tensor # [state_E, rows_pad_k, cols_pad_k] uint8\n barrier_count: torch.Tensor # [1] int32\n barrier_epoch: torch.Tensor # [1] int32\n active_expert_count: torch.Tensor # [1] int32\n weight_expert_ids: torch.Tensor # [state_E] int32\n global_to_local_expert: torch.Tensor # [weight_E] int32\n compact_topk_ids: torch.Tensor # [state_E] int32, for micro kernel pre-pass\n\n # Views (set after allocation)\n packed_a_view: torch.Tensor | None = None\n sfa_ptr: object = None\n packed_a_flat: torch.Tensor | None = None\n scale_flat: torch.Tensor | None = None\n\n # Direct micro planes (allocated only when the shape can take that path).\n dm_barrier_count: torch.Tensor | None = None\n dm_barrier_epoch: torch.Tensor | None = None\n dm_intermediate: torch.Tensor | None = None\n dm_input_gs: torch.Tensor | None = None\n dm_down_input_scale: torch.Tensor | None = None\n\n\ndef _direct_micro_candidate(k: int, n: int, num_topk: int, weight_E: int) -> bool:\n \"\"\"Whether any m in the tiny-decode band can run the direct micro kernel.\"\"\"\n return any(\n MoEDirectMicroKernel.is_supported(m, k, n, num_topk, weight_E)\n for m in range(1, _MICRO_MAX_TOKENS + 1)\n )\n\n\ndef allocate_sm120_static_workspace(\n *,\n state_E: int,\n weight_E: int,\n max_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation_precision: str = \"fp4\",\n) -> Sm120StaticMoEWorkspace:\n \"\"\"Allocate workspace buffers for the SM120 static MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"allocate_sm120_static_workspace only supports quant_mode='nvfp4'; \"\n \"use allocate_sm120_moe_workspace(..., quant_mode='w4a16') for W4A16.\"\n )\n\n rows_pad_k = _align_up(max_rows, 128)\n cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n _check_memref_limit(\"static packed_input\", state_E * max_rows * (k // 2))\n _check_memref_limit(\"static packed_input_scale\", state_E * rows_pad_k * cols_pad_k)\n packed_input = torch.empty(\n state_E, max_rows, k // 2, dtype=torch.uint8, device=device\n )\n\n workspace = Sm120StaticMoEWorkspace(\n state_E=state_E,\n weight_E=weight_E,\n max_rows=max_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation_precision=activation_precision,\n row_counts=torch.zeros(state_E, dtype=torch.int32, device=device),\n token_map=torch.zeros(state_E, max_rows, dtype=torch.int32, device=device),\n token_weights=torch.zeros(\n state_E, max_rows, dtype=torch.float32, device=device\n ),\n packed_input=packed_input,\n packed_input_scale=torch.empty(\n state_E, rows_pad_k, cols_pad_k, dtype=torch.uint8, device=device\n ),\n barrier_count=torch.zeros(1, dtype=torch.int32, device=device),\n barrier_epoch=torch.zeros(1, dtype=torch.int32, device=device),\n active_expert_count=torch.zeros(1, dtype=torch.int32, device=device),\n weight_expert_ids=torch.arange(state_E, dtype=torch.int32, device=device),\n global_to_local_expert=torch.empty(weight_E, dtype=torch.int32, device=device),\n compact_topk_ids=torch.empty(\n max(state_E, max_rows), dtype=torch.int32, device=device\n ),\n )\n\n # Finalize views\n sf_dtype = cutlass.Float8E4M3FN\n workspace.packed_a_view = workspace.packed_input.permute(1, 2, 0).view(\n torch.float4_e2m1fn_x2\n )\n workspace.packed_a_flat = workspace.packed_input.view(-1)\n workspace.scale_flat = workspace.packed_input_scale.view(-1)\n workspace.sfa_ptr = make_ptr(\n sf_dtype,\n workspace.packed_input_scale.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n\n # Direct micro reads weights by global expert id, so its planes are only\n # useful without EP remapping.\n if state_E == weight_E and _direct_micro_candidate(k, n, num_topk, weight_E):\n dm_rows = min(max_rows, _MICRO_MAX_TOKENS * num_topk)\n # The epoch-based barriers restore their slots after each launch, so\n # the zeroed allocation is the only reset needed (graph-replay safe).\n dm_slots = dm_rows + _MICRO_MAX_TOKENS * 16\n fc2_n_chunks = (n // 2 + 127) // 128\n # The fused kernel binds the intermediate as m * num_topk *\n # fc2_n_chunks * 128 u32 words; size for the largest supported m.\n dm_inter = _MICRO_MAX_TOKENS * num_topk * fc2_n_chunks * 128\n workspace.dm_barrier_count = torch.zeros(\n dm_slots, dtype=torch.int32, device=device\n )\n workspace.dm_barrier_epoch = torch.zeros(\n dm_slots, dtype=torch.int32, device=device\n )\n workspace.dm_intermediate = torch.empty(\n dm_inter, dtype=torch.float32, device=device\n )\n workspace.dm_input_gs = torch.empty(\n weight_E, dtype=torch.float32, device=device\n )\n workspace.dm_down_input_scale = torch.empty(\n weight_E, dtype=torch.float32, device=device\n )\n return workspace\n\n\n# ---------------------------------------------------------------------------\n# Weight views\n# ---------------------------------------------------------------------------\n@dataclass\nclass _WeightViews:\n w13_fp4: object = None\n down_fp4: object = None\n sfb_w13_ptr: object = None\n sfb_down_ptr: object = None\n w1_alpha: torch.Tensor | None = None\n w2_alpha: torch.Tensor | None = None\n w1_storage: torch.Tensor | None = None\n w1_scale_storage: torch.Tensor | None = None\n w2_storage: torch.Tensor | None = None\n w2_scale_storage: torch.Tensor | None = None\n _w13_sf_storage: torch.Tensor | None = None\n _down_sf_storage: torch.Tensor | None = None\n\n\ndef _register_cache_eviction(cache: Dict, key: Tuple, *source_tensors) -> None:\n \"\"\"Evict ``key`` when a source weight tensor is collected, so the cache\n follows the weights' lifetime instead of growing for the whole process.\n \"\"\"\n for tensor in source_tensors:\n if tensor is not None:\n weakref.finalize(tensor, cache.pop, key, None)\n\n\n_WEIGHT_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_weight_views(\n w1_fp4: torch.Tensor,\n w1_blockscale: torch.Tensor,\n w2_fp4: torch.Tensor,\n w2_blockscale: torch.Tensor,\n w1_alphas: torch.Tensor,\n w2_alphas: torch.Tensor,\n n: int,\n k: int,\n activation_precision: str = \"fp4\",\n) -> _WeightViews:\n \"\"\"Create permuted weight views for the static kernel.\n\n The kernel expects concatenated w13 data with shape [2*n, k//2, E]\n via a single TMA descriptor.\n \"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n tile_n = _level_tile_n(activation_precision)\n # The kernel splits w13 into gate/up halves by tile index. This only works\n # when the boundary between halves lands on a tile-aligned column.\n if n % tile_n != 0:\n raise ValueError(\n f\"intermediate_size ({n}) must be a multiple of {tile_n} \"\n f\"for the SM120 MoE kernel's gate/up tile split.\"\n )\n\n key = (\n activation_precision,\n w1_fp4.data_ptr(),\n w1_blockscale.data_ptr(),\n w1_alphas.data_ptr(),\n w2_fp4.data_ptr(),\n w2_blockscale.data_ptr(),\n w2_alphas.data_ptr(),\n )\n cached = _WEIGHT_CACHE.get(key)\n if cached is None:\n # Cache the fresh buffers (scale factors + fp32 alphas).\n w1_rows = w1_fp4.shape[1] # 2*n for gated, n for non-gated\n cached = (\n convert_sf_from_mma_layout(\n w1_blockscale, m=w1_rows, k=k, num_groups=w1_fp4.shape[0]\n ).contiguous(),\n convert_sf_from_mma_layout(\n w2_blockscale, m=k, k=n, num_groups=w2_fp4.shape[0]\n ).contiguous(),\n w1_alphas.contiguous().to(torch.float32),\n w2_alphas.contiguous().to(torch.float32),\n )\n _WEIGHT_CACHE[key] = cached\n _register_cache_eviction(\n _WEIGHT_CACHE,\n key,\n w1_fp4,\n w1_blockscale,\n w1_alphas,\n w2_fp4,\n w2_blockscale,\n w2_alphas,\n )\n w13_sf_contiguous, down_sf_contiguous, w1_alpha, w2_alpha = cached\n\n # Permute [E, w1_rows, k//2] -> [w1_rows, k//2, E] (view, no copy).\n sf_dtype = cutlass.Float8E4M3FN\n w13 = w1_fp4.permute(1, 2, 0)\n down = w2_fp4.permute(1, 2, 0)\n return _WeightViews(\n w13_fp4=w13.view(torch.float4_e2m1fn_x2),\n down_fp4=down.view(torch.float4_e2m1fn_x2),\n sfb_w13_ptr=make_ptr(\n sf_dtype,\n w13_sf_contiguous.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n ),\n sfb_down_ptr=make_ptr(\n sf_dtype,\n down_sf_contiguous.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n ),\n w1_alpha=w1_alpha,\n w2_alpha=w2_alpha,\n w1_storage=w1_fp4,\n w1_scale_storage=w13_sf_contiguous,\n w2_storage=w2_fp4,\n w2_scale_storage=down_sf_contiguous,\n _w13_sf_storage=w13_sf_contiguous,\n _down_sf_storage=down_sf_contiguous,\n )\n\n\n# ---------------------------------------------------------------------------\n# Kernel compilation cache\n#\n# The three kernels below are compiled through the shared on-disk CuTe-DSL\n# cache (#3874, #4029; docs/design_docs/cute_dsl_kernel_cache.md), so a fresh\n# process JITLinks an exported ``.o`` instead of re-running the MLIR pipeline.\n# The in-process dicts stay as the level-1 memoization the design describes.\n# ---------------------------------------------------------------------------\n_CUTE_DSL_MODULE = \"b12x_moe\"\n\n\ndef _kernel_source_files() -> Tuple[str, ...]:\n \"\"\"Source files whose content invalidates the on-disk kernel cache.\n\n Every module contributing device code to the three kernels compiled here:\n the kernel bodies, the shared activation and FP4 device helpers, and the\n SM120 layout builders and block-scaled mainloop they are built from.\n \"\"\"\n from flashinfer.cute_dsl import fp4_common\n from flashinfer.cute_dsl import utils as cute_dsl_utils\n from flashinfer.gemm.kernels import dense_blockscaled_gemm_sm120_b12x\n\n from . import (\n moe_activation,\n moe_dynamic_kernel,\n moe_micro_kernel,\n moe_static_kernel,\n )\n\n return (\n __file__,\n moe_activation.__file__,\n moe_static_kernel.__file__,\n moe_micro_kernel.__file__,\n moe_dynamic_kernel.__file__,\n cute_dsl_utils.__file__,\n fp4_common.__file__,\n dense_blockscaled_gemm_sm120_b12x.__file__,\n )\n\n\ndef _disk_kernel_name(prefix: str, cache_key: Tuple) -> str:\n \"\"\"On-disk specialization name for an in-process kernel cache key.\n\n The name is the *sole* per-kernel cache key — the module ``meta.json``\n guards only module-wide facts (arch, DSL stack, source hashes) — so it has\n to be injective in every codegen parameter. It is therefore derived from\n the very tuple that keys the in-process cache: a readable shape prefix for\n humans browsing ``cached_ops/``, plus a digest of the exact tuple.\n\n The digest, rather than a formatted field list, is what makes the mapping\n injective: the keys contain floats and ``None`` (``swiglu_alpha`` /\n ``swiglu_beta`` / ``swiglu_limit``) whose textual forms would collide once\n sanitized into a filename (``1.5`` and ``-1.5`` both sanitize to ``1_5``).\n \"\"\"\n digest = hashlib.sha256(repr(cache_key).encode()).hexdigest()[:16]\n return f\"{prefix}_{digest}\"\n\n\ndef _static_kernel_cache_key(\n *,\n activation_precision: str,\n state_E: int,\n weight_E: int,\n m: int,\n k: int,\n n: int,\n num_topk: int,\n max_rows: int,\n mac: int,\n mma_tiler_mn: Tuple[int, int],\n topk_ids_dtype: torch.dtype,\n input_scales_are_reciprocal: bool,\n fast_math: bool,\n activation: str,\n swiglu_alpha: float,\n swiglu_beta: float,\n swiglu_limit: float | None,\n) -> Tuple:\n \"\"\"The static kernel's cache key: every parameter affecting its codegen.\n\n Single source of truth for both cache levels — the in-process dict and,\n through :func:`_disk_kernel_name`, the on-disk artifact name.\n \"\"\"\n return (\n \"static\",\n activation_precision,\n state_E,\n weight_E,\n m,\n k,\n n,\n num_topk,\n max_rows,\n mac,\n mma_tiler_mn,\n topk_ids_dtype,\n input_scales_are_reciprocal,\n fast_math,\n activation,\n swiglu_alpha,\n swiglu_beta,\n swiglu_limit,\n )\n\n\ndef _micro_kernel_cache_key(\n *,\n state_E: int,\n weight_E: int,\n m: int,\n k: int,\n n: int,\n num_topk: int,\n max_rows: int,\n mac: int,\n mma_tiler_mn: Tuple[int, int],\n topk_ids_dtype: torch.dtype,\n input_scales_are_reciprocal: bool,\n fast_math: bool,\n share_input_across_experts: bool,\n share_expert_scales: bool,\n single_token: bool,\n activation: str,\n swiglu_alpha: float,\n swiglu_beta: float,\n swiglu_limit: float | None,\n) -> Tuple:\n \"\"\"The micro kernel's cache key (see :func:`_static_kernel_cache_key`).\"\"\"\n return (\n \"micro\",\n state_E,\n weight_E,\n m,\n k,\n n,\n num_topk,\n max_rows,\n mac,\n mma_tiler_mn,\n topk_ids_dtype,\n input_scales_are_reciprocal,\n fast_math,\n share_input_across_experts,\n share_expert_scales,\n single_token,\n activation,\n swiglu_alpha,\n swiglu_beta,\n swiglu_limit,\n )\n\n\ndef _dynamic_kernel_cache_key(\n *,\n activation_precision: str,\n E: int,\n k: int,\n n: int,\n num_topk: int,\n mac: int,\n mma_tiler_mn: Tuple[int, int],\n topk_ids_dtype: torch.dtype,\n input_scales_are_reciprocal: bool,\n fast_math: bool,\n activation: str,\n swiglu_alpha: float,\n swiglu_beta: float,\n swiglu_limit: float | None,\n share_input_across_experts: bool,\n) -> Tuple:\n \"\"\"The dynamic kernel's cache key (see :func:`_static_kernel_cache_key`).\n\n Deliberately free of ``m`` / ``max_rows``: the dynamic kernel takes its\n runtime-shaped operands as pointers, so one artifact serves every batch\n size.\n \"\"\"\n return (\n \"dynamic\",\n activation_precision,\n E,\n k,\n n,\n num_topk,\n mac,\n mma_tiler_mn,\n topk_ids_dtype,\n input_scales_are_reciprocal,\n fast_math,\n activation,\n swiglu_alpha,\n swiglu_beta,\n swiglu_limit,\n share_input_across_experts,\n )\n\n\n_STATIC_KERNEL_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_static_kernel(\n state_E: int,\n weight_E: int,\n m: int,\n k: int,\n n: int,\n num_topk: int,\n max_rows: int,\n *,\n topk_ids_dtype: torch.dtype = torch.int32,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n mac_override: int | None = None,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n):\n \"\"\"Compile (or retrieve cached) the SM120 static MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 static compiler\"\n )\n sf_vec_size = 16\n sm_count = get_num_sm(torch.device(\"cuda\"))\n mac = (\n mac_override\n if mac_override is not None\n else min(get_max_active_clusters(1), sm_count)\n )\n\n # Select tile size based on actual routed rows\n routed_rows = m * num_topk\n mma_tiler_mn = (128, 128)\n if activation_precision == \"fp4\" and num_topk > 1:\n mma_tiler_mn = _select_moe_mma_tiler_mn(routed_rows, n, resident_clusters=mac)\n\n cache_key = _static_kernel_cache_key(\n activation_precision=activation_precision,\n state_E=state_E,\n weight_E=weight_E,\n m=m,\n k=k,\n n=n,\n num_topk=num_topk,\n max_rows=max_rows,\n mac=mac,\n mma_tiler_mn=mma_tiler_mn,\n topk_ids_dtype=topk_ids_dtype,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n )\n cached = _STATIC_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n return cached\n\n ab_dtype = cutlass.Float4E2M1FN\n weight_dtype = cutlass.Float4E2M1FN\n sf_dtype = cutlass.Float8E4M3FN\n a_dtype = cutlass.BFloat16\n alpha_dtype = cutlass.Float32\n\n output_tile_count_n = max(1, (n + mma_tiler_mn[1] - 1) // mma_tiler_mn[1])\n kernel: Any = MoEStaticKernel(\n sf_vec_size=sf_vec_size,\n mma_tiler_mn=mma_tiler_mn,\n output_tile_count_n=output_tile_count_n,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n )\n\n is_gated = is_gated_activation(activation)\n w1_rows = (2 if is_gated else 1) * n # 2*n for gated, n for non-gated\n\n rows_pad_k = _align_up(max_rows, 128)\n cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n\n # Build fake tensors for compilation\n a_input_fake = cute.runtime.make_fake_compact_tensor(\n a_dtype,\n (m, k),\n stride_order=(1, 0),\n assumed_align=16,\n )\n topk_ids_cutlass_dtype = (\n cutlass.Int32 if topk_ids_dtype == torch.int32 else cutlass.Int64\n )\n topk_ids_align = 4 if topk_ids_dtype == torch.int32 else 8\n topk_ids_fake = cute.runtime.make_fake_compact_tensor(\n topk_ids_cutlass_dtype,\n (m * num_topk,),\n assumed_align=topk_ids_align,\n )\n topk_weights_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32,\n (m * num_topk,),\n assumed_align=4,\n )\n packed_a_fake = cute.runtime.make_fake_compact_tensor(\n ab_dtype,\n (max_rows, k, state_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfa_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n packed_a_storage_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (state_E * max_rows * (k // 2),),\n assumed_align=16,\n )\n scale_storage_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (state_E * rows_pad_k * cols_pad_k,),\n assumed_align=16,\n )\n barrier_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n barrier_epoch_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n b_w13_fake = cute.runtime.make_fake_compact_tensor(\n weight_dtype,\n (w1_rows, k, weight_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_w13_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n b_down_fake = cute.runtime.make_fake_compact_tensor(\n weight_dtype,\n (k, n, weight_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_down_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n row_counts_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E,),\n assumed_align=4,\n )\n active_expert_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n weight_expert_ids_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E,),\n assumed_align=4,\n )\n global_to_local_expert_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (weight_E,),\n assumed_align=4,\n )\n input_gs_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n down_alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n global_scale_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n scatter_fake = cute.runtime.make_fake_compact_tensor(\n a_dtype,\n (m, k),\n stride_order=(1, 0),\n assumed_align=16,\n )\n token_map_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E, max_rows),\n stride_order=(1, 0),\n assumed_align=4,\n )\n token_weights_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (state_E, max_rows),\n stride_order=(1, 0),\n assumed_align=16,\n )\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n compiled = build_and_load_cute_dsl_kernel(\n _CUTE_DSL_MODULE,\n _disk_kernel_name(f\"static_m{m}_k{k}_n{n}_t{num_topk}_r{max_rows}\", cache_key),\n lambda: cute.compile(\n kernel,\n a_input_fake,\n topk_ids_fake,\n topk_weights_fake,\n packed_a_fake,\n sfa_fake,\n packed_a_storage_fake,\n scale_storage_fake,\n barrier_count_fake,\n barrier_epoch_fake,\n b_w13_fake,\n sfb_w13_fake,\n b_down_fake,\n sfb_down_fake,\n row_counts_fake,\n active_expert_count_fake,\n weight_expert_ids_fake,\n global_to_local_expert_fake,\n input_gs_fake,\n alpha_fake,\n down_alpha_fake,\n global_scale_fake,\n scatter_fake,\n token_map_fake,\n token_weights_fake,\n mac,\n stream_fake,\n options=\"--opt-level 2 --enable-tvm-ffi\",\n ),\n extra_key_files=_kernel_source_files(),\n )\n\n result = (compiled, mac)\n _STATIC_KERNEL_CACHE[cache_key] = result\n return result\n\n\n_MICRO_KERNEL_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_micro_kernel(\n state_E: int,\n weight_E: int,\n m: int,\n k: int,\n n: int,\n num_topk: int,\n max_rows: int,\n *,\n topk_ids_dtype: torch.dtype = torch.int32,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n share_input_across_experts: bool = False,\n share_expert_scales: bool = False,\n single_token: bool = False,\n mac_override: int | None = None,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n):\n \"\"\"Compile (or retrieve cached) the SM120 micro MoE kernel.\"\"\"\n sf_vec_size = 16\n sm_count = get_num_sm(torch.device(\"cuda\"))\n mac = (\n mac_override\n if mac_override is not None\n else min(get_max_active_clusters(1), sm_count)\n )\n\n # Micro always selects tile from routed rows (not just for multi-topk)\n routed_rows = m * num_topk\n mma_tiler_mn = _select_moe_mma_tiler_mn(routed_rows, n)\n\n cache_key = _micro_kernel_cache_key(\n state_E=state_E,\n weight_E=weight_E,\n m=m,\n k=k,\n n=n,\n num_topk=num_topk,\n max_rows=max_rows,\n mac=mac,\n mma_tiler_mn=mma_tiler_mn,\n topk_ids_dtype=topk_ids_dtype,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n share_input_across_experts=share_input_across_experts,\n share_expert_scales=share_expert_scales,\n single_token=single_token,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n )\n cached = _MICRO_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n return cached\n\n ab_dtype = cutlass.Float4E2M1FN\n sf_dtype = cutlass.Float8E4M3FN\n a_dtype = cutlass.BFloat16\n alpha_dtype = cutlass.Float32\n\n kernel = MoEMicroKernel(\n sf_vec_size=sf_vec_size,\n mma_tiler_mn=mma_tiler_mn,\n output_tile_count_n=max(1, (n + mma_tiler_mn[1] - 1) // mma_tiler_mn[1]),\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n share_input_across_experts=share_input_across_experts,\n share_expert_scales=share_expert_scales,\n single_token=single_token,\n )\n\n is_gated = is_gated_activation(activation)\n w1_rows = (2 if is_gated else 1) * n\n\n rows_pad_k = _align_up(max_rows, 128)\n cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n\n # Build fake tensors for compilation (identical to static kernel)\n a_input_fake = cute.runtime.make_fake_compact_tensor(\n a_dtype,\n (m, k),\n stride_order=(1, 0),\n assumed_align=16,\n )\n topk_ids_cutlass_dtype = (\n cutlass.Int32 if topk_ids_dtype == torch.int32 else cutlass.Int64\n )\n topk_ids_align = 4 if topk_ids_dtype == torch.int32 else 8\n topk_ids_fake = cute.runtime.make_fake_compact_tensor(\n topk_ids_cutlass_dtype,\n (m * num_topk,),\n assumed_align=topk_ids_align,\n )\n topk_weights_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32,\n (m * num_topk,),\n assumed_align=4,\n )\n packed_a_fake = cute.runtime.make_fake_compact_tensor(\n ab_dtype,\n (max_rows, k, state_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfa_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n packed_a_storage_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (state_E * max_rows * (k // 2),),\n assumed_align=16,\n )\n scale_storage_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (state_E * rows_pad_k * cols_pad_k,),\n assumed_align=16,\n )\n barrier_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n barrier_epoch_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n b_w13_fake = cute.runtime.make_fake_compact_tensor(\n ab_dtype,\n (w1_rows, k, weight_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_w13_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n b_down_fake = cute.runtime.make_fake_compact_tensor(\n ab_dtype,\n (k, n, weight_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_down_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n row_counts_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E,),\n assumed_align=4,\n )\n active_expert_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n weight_expert_ids_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E,),\n assumed_align=4,\n )\n global_to_local_expert_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (weight_E,),\n assumed_align=4,\n )\n input_gs_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n down_alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n global_scale_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n scatter_fake = cute.runtime.make_fake_compact_tensor(\n a_dtype,\n (m, k),\n stride_order=(1, 0),\n assumed_align=16,\n )\n token_map_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E, max_rows),\n stride_order=(1, 0),\n assumed_align=4,\n )\n token_weights_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (state_E, max_rows),\n stride_order=(1, 0),\n assumed_align=16,\n )\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n compiled = build_and_load_cute_dsl_kernel(\n _CUTE_DSL_MODULE,\n _disk_kernel_name(f\"micro_m{m}_k{k}_n{n}_t{num_topk}_r{max_rows}\", cache_key),\n lambda: cute.compile(\n kernel,\n a_input_fake,\n topk_ids_fake,\n topk_weights_fake,\n packed_a_fake,\n sfa_fake,\n packed_a_storage_fake,\n scale_storage_fake,\n barrier_count_fake,\n barrier_epoch_fake,\n b_w13_fake,\n sfb_w13_fake,\n b_down_fake,\n sfb_down_fake,\n row_counts_fake,\n active_expert_count_fake,\n weight_expert_ids_fake,\n global_to_local_expert_fake,\n input_gs_fake,\n alpha_fake,\n down_alpha_fake,\n global_scale_fake,\n scatter_fake,\n token_map_fake,\n token_weights_fake,\n mac,\n stream_fake,\n options=\"--opt-level 2 --enable-tvm-ffi\",\n ),\n extra_key_files=_kernel_source_files(),\n )\n\n result = (compiled, mac)\n _MICRO_KERNEL_CACHE[cache_key] = result\n return result\n\n\n# The launch cache skips the per-launch build/configure; the kernel cache\n# dedupes compiles across keys that configure to the same artifact\n# (m=2..8 differ only in grid_x).\n_DIRECT_MICRO_LAUNCH_CACHE: Dict[Tuple, Tuple] = {}\n_DIRECT_MICRO_KERNEL_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_direct_micro_kernel(\n weight_E: int,\n m: int,\n k: int,\n n: int,\n num_topk: int,\n *,\n topk_ids_dtype: torch.dtype = torch.int32,\n fast_math: bool = True,\n share_input_across_experts: bool = False,\n share_expert_scales: bool = False,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n device: torch.device | None = None,\n):\n \"\"\"Compile (or retrieve cached) the SM120 direct micro MoE kernel.\n\n Returns (compiled, grid_x, accepts_block_dim).\n \"\"\"\n if activation != SWIGLUOAI_UNINTERLEAVE:\n # The kernel constructor only accepts configurable swiglu parameters\n # for swigluoai; other activations use its normalized defaults\n # (accept-and-ignore, matching the MMA kernels).\n swiglu_alpha = None\n swiglu_beta = None\n swiglu_limit = None\n launch_key = (\n weight_E,\n m,\n k,\n n,\n num_topk,\n topk_ids_dtype,\n fast_math,\n share_input_across_experts,\n share_expert_scales,\n activation,\n swiglu_alpha,\n swiglu_beta,\n swiglu_limit,\n str(_canonical_cuda_device(device)) if device is not None else None,\n )\n cached = _DIRECT_MICRO_LAUNCH_CACHE.get(launch_key)\n if cached is not None:\n return cached\n kernel = build_direct_micro_kernel(\n weight_E,\n m,\n k,\n n,\n num_topk,\n activation=activation,\n fast_math=fast_math,\n share_input_across_experts=share_input_across_experts,\n share_expert_scales=share_expert_scales,\n single_token=m == 1,\n swiglu_limit=swiglu_limit,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n device=device,\n )\n compile_key = (\"direct_micro\", kernel.__cache_key__, topk_ids_dtype)\n entry = _DIRECT_MICRO_KERNEL_CACHE.get(compile_key)\n if entry is None:\n compiled = compile_direct_micro_kernel(kernel, topk_ids_dtype=topk_ids_dtype)\n # Register pressure can cap the launchable CTA below the fused body's\n # 512 threads; probe once per compiled kernel.\n accepts = compiled_direct_micro_accepts_block_dim(\n compiled, kernel.launch_block_dim\n )\n entry = (compiled, accepts)\n _DIRECT_MICRO_KERNEL_CACHE[compile_key] = entry\n compiled, accepts = entry\n cached = (compiled, kernel.grid_x, accepts)\n _DIRECT_MICRO_LAUNCH_CACHE[launch_key] = cached\n return cached\n\n\n# ---------------------------------------------------------------------------\n# Launch\n# ---------------------------------------------------------------------------\ndef _expand_to_experts(t: torch.Tensor, num_experts: int) -> torch.Tensor:\n \"\"\"Broadcast a scalar or [1] tensor to [num_experts], always fp32.\n\n Both branches must cast: the kernels are compiled against fp32 fake\n tensors for every per-expert scale.\n \"\"\"\n if t.numel() == 1:\n return t.to(torch.float32).expand(num_experts).contiguous()\n return t.contiguous().to(torch.float32)\n\n\ndef launch_sm120_static_moe(\n *,\n workspace: Sm120StaticMoEWorkspace,\n weights: _WeightViews,\n a: torch.Tensor,\n topk_ids: torch.Tensor,\n topk_weights: torch.Tensor,\n input_gs: torch.Tensor,\n down_input_scale: torch.Tensor,\n scatter_output: torch.Tensor,\n num_experts: int,\n num_tokens: int,\n k: int,\n n: int,\n top_k: int,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n) -> torch.Tensor:\n \"\"\"Launch the SM120 static, micro, or direct micro MoE kernel.\n\n The direct micro kernel takes tiny decode batches (m <= 8, routed_rows\n < 64) when it supports the shape, the MMA micro kernel takes the rest of\n its band (routed_rows <= 20-40), and the static kernel takes the rest.\n The MMA micro path runs a Triton pre-pass to compact routing IDs before\n launching; direct micro routes on global expert ids directly.\n \"\"\"\n _check_memref_limit(\"scatter_output\", scatter_output.numel())\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 static launcher\"\n )\n\n # Flatten routing tensors\n flat_ids = topk_ids.view(-1).to(torch.int32)\n flat_weights = topk_weights.view(-1).to(torch.float32)\n routed_rows = num_tokens * top_k\n\n # Capture whether input_gs was a single shared scalar BEFORE expansion:\n # the m=1 relu2 shared-input micro optimization only applies when every\n # expert sees the same FC1-input global scale.\n input_gs_is_shared = input_gs.numel() == 1\n down_input_scale_is_shared = down_input_scale.numel() == 1\n\n # Broadcast scalar scales to per-expert [E] tensors\n input_gs = _expand_to_experts(input_gs, num_experts)\n down_input_scale = _expand_to_experts(down_input_scale, num_experts)\n\n # Shared-scale flags let compact W4A4 micro match the ReLU2 single-token\n # specialization.\n share_input_across_experts = (\n activation == \"relu2\"\n and num_tokens == 1\n and input_gs_is_shared\n and _MICRO_SHARE_INPUT_ACROSS_EXPERTS\n )\n share_expert_scales = (\n activation == \"relu2\" and input_gs_is_shared and down_input_scale_is_shared\n )\n\n # Direct micro takes its band before the MMA micro decision. It reads\n # weights by global expert id, so EP shapes keep the compact path.\n use_direct_micro = (\n activation_precision == \"fp4\"\n and workspace.state_E == num_experts\n and workspace.dm_barrier_count is not None\n and workspace.dm_barrier_count.numel() >= routed_rows + num_tokens * 16\n and num_tokens <= _MICRO_MAX_TOKENS\n and routed_rows < _DIRECT_MICRO_CUTOVER_PAIRS\n and n <= _DIRECT_MICRO_MAX_N\n and MoEDirectMicroKernel.is_supported(num_tokens, k, n, top_k, num_experts)\n )\n if _FORCED_BACKEND is not None:\n if _FORCED_BACKEND == \"direct_micro\":\n if workspace.dm_barrier_count is None or not (\n MoEDirectMicroKernel.is_supported(num_tokens, k, n, top_k, num_experts)\n ):\n raise ValueError(\n \"forced direct_micro backend cannot run this shape \"\n f\"(m={num_tokens}, k={k}, n={n}, top_k={top_k})\"\n )\n if workspace.dm_barrier_count.numel() < routed_rows + num_tokens * 16:\n raise ValueError(\n \"forced direct_micro backend exceeds the workspace barrier \"\n f\"capacity ({workspace.dm_barrier_count.numel()} slots < \"\n f\"{routed_rows} routed rows + {num_tokens * 16})\"\n )\n use_direct_micro = True\n else:\n use_direct_micro = False\n if use_direct_micro:\n compiled, grid_x, block_ok = _get_direct_micro_kernel(\n num_experts,\n num_tokens,\n k,\n n,\n top_k,\n topk_ids_dtype=flat_ids.dtype,\n fast_math=fast_math,\n share_input_across_experts=share_input_across_experts,\n share_expert_scales=share_expert_scales,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n device=a.device,\n )\n if not block_ok:\n if _FORCED_BACKEND == \"direct_micro\":\n raise RuntimeError(\"compiled direct micro MoE kernel cannot launch\")\n use_direct_micro = False\n if use_direct_micro:\n # The kernel takes multiplier-form scales only; invert reciprocal\n # inputs into the persistent workspace planes (zeros stay zero,\n # matching the MMA kernels).\n if input_scales_are_reciprocal:\n workspace.dm_input_gs.copy_(\n torch.where(input_gs != 0, 1.0 / input_gs, input_gs)\n )\n workspace.dm_down_input_scale.copy_(\n torch.where(\n down_input_scale != 0, 1.0 / down_input_scale, down_input_scale\n )\n )\n launch_gs = workspace.dm_input_gs\n launch_down = workspace.dm_down_input_scale\n else:\n launch_gs = input_gs\n launch_down = down_input_scale\n MoEDirectMicroKernel.launch(\n compiled,\n x=a,\n w1_fp4=weights.w1_storage,\n w1_blockscale=weights.w1_scale_storage,\n w1_alphas=weights.w1_alpha,\n a1_gscale=launch_gs,\n a2_gscale=launch_down,\n inter_fp32=workspace.dm_intermediate,\n w2_fp4=weights.w2_storage,\n w2_blockscale=weights.w2_scale_storage,\n w2_alphas=weights.w2_alpha,\n topk_ids=flat_ids,\n topk_weights=flat_weights,\n out=scatter_output,\n barrier_count=workspace.dm_barrier_count,\n barrier_epoch=workspace.dm_barrier_epoch,\n m=num_tokens,\n grid_x=grid_x,\n )\n return scatter_output\n\n # Decide micro vs static\n micro_cutover = _MICRO_COMPACT_CUTOVER_PAIRS\n if top_k > 1:\n micro_cutover = _MICRO_COMPACT_CUTOVER_PAIRS_MULTI_TOPK\n use_micro = (\n activation_precision == \"fp4\"\n and num_tokens <= _MICRO_MAX_TOKENS\n and routed_rows <= micro_cutover\n )\n if _FORCED_BACKEND is not None:\n if _FORCED_BACKEND == \"micro\":\n # Forced mode raises on correctness violations, never falls back.\n if num_tokens > _MICRO_MAX_TOKENS:\n raise ValueError(\n f\"forced micro backend supports at most {_MICRO_MAX_TOKENS} \"\n f\"tokens (got {num_tokens})\"\n )\n if flat_ids.numel() > workspace.compact_topk_ids.numel():\n raise ValueError(\n \"forced micro backend exceeds the workspace compact-id \"\n f\"capacity ({workspace.compact_topk_ids.numel()} < \"\n f\"{flat_ids.numel()})\"\n )\n use_micro = True\n else:\n use_micro = False\n\n sm_count = get_num_sm(torch.device(\"cuda\"))\n base_mac = min(get_max_active_clusters(1), sm_count)\n tuned_static_mac = _lookup_mac_ladder(_STATIC_MAC_LADDER, routed_rows)\n static_mac = min(tuned_static_mac or base_mac, base_mac)\n if activation_precision == \"fp4\" and not use_micro and routed_rows < 40:\n static_mac = min(static_mac, 64)\n\n if use_micro:\n assert flat_ids.numel() <= workspace.compact_topk_ids.numel(), (\n f\"compact_topk_ids buffer too small: \"\n f\"{workspace.compact_topk_ids.numel()} < {flat_ids.numel()}\"\n )\n # Single-token ReLU2 is non-gated, so the micro kernel can launch on\n # the routed expert ids directly. Gated SiLU still goes through the\n # compact id buffer so the kernel can map compact launch ids back to\n # the physical gate/up weight experts.\n if num_tokens == 1 and activation == \"relu2\":\n launch_ids = flat_ids\n elif num_tokens == 1:\n compact_ids = workspace.compact_topk_ids[: flat_ids.numel()]\n compact_ids.copy_(\n torch.arange(\n flat_ids.numel(),\n device=flat_ids.device,\n dtype=torch.int32,\n )\n )\n workspace.weight_expert_ids[: flat_ids.numel()].copy_(\n flat_ids.to(torch.int32)\n )\n workspace.active_expert_count.fill_(flat_ids.numel())\n launch_ids = compact_ids\n else:\n compact_ids = workspace.compact_topk_ids[: flat_ids.numel()]\n from .triton_compact import compact_topk_ids as _triton_compact_topk_ids\n\n _triton_compact_topk_ids(\n flat_ids,\n compact_ids,\n workspace.weight_expert_ids,\n workspace.active_expert_count,\n )\n launch_ids = compact_ids\n # Select micro MAC: min of tuned ladder, work tiles, and hardware limit.\n micro_work_tiles = max(1, routed_rows * max(1, (n + 128 - 1) // 128))\n tuned_mac = _lookup_mac_ladder(_MICRO_MAC_LADDER, routed_rows)\n micro_mac = min(tuned_mac or base_mac, micro_work_tiles, base_mac)\n compiled, mac = _get_micro_kernel(\n workspace.state_E,\n num_experts,\n num_tokens,\n k,\n n,\n top_k,\n workspace.max_rows,\n topk_ids_dtype=launch_ids.dtype,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n share_input_across_experts=share_input_across_experts,\n share_expert_scales=share_expert_scales,\n single_token=num_tokens == 1,\n mac_override=micro_mac,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n )\n else:\n compiled, mac = _get_static_kernel(\n workspace.state_E,\n num_experts,\n num_tokens,\n k,\n n,\n top_k,\n workspace.max_rows,\n topk_ids_dtype=torch.int32,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n mac_override=static_mac,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n activation_precision=activation_precision,\n )\n launch_ids = flat_ids\n\n # Pointer arguments must be passed as raw ints (data_ptr()) at runtime.\n # No stream argument: the kernels compile against\n # ``make_fake_stream(use_tvm_ffi_env_stream=True)``, so TVM-FFI supplies\n # the caller's current stream and the parameter is absent from the\n # compiled signature.\n runtime_args: Tuple[Any, ...] = (\n a,\n launch_ids,\n flat_weights,\n workspace.packed_a_view,\n workspace.packed_input_scale.data_ptr(),\n workspace.packed_a_flat,\n workspace.scale_flat,\n workspace.barrier_count,\n workspace.barrier_epoch,\n weights.w13_fp4,\n weights._w13_sf_storage.data_ptr(),\n weights.down_fp4,\n weights._down_sf_storage.data_ptr(),\n workspace.row_counts,\n workspace.active_expert_count,\n workspace.weight_expert_ids,\n workspace.global_to_local_expert,\n input_gs,\n weights.w1_alpha,\n weights.w2_alpha,\n down_input_scale,\n scatter_output,\n workspace.token_map,\n workspace.token_weights,\n )\n compiled(*runtime_args)\n\n return scatter_output\n\n\n# ==========================================================================\n# Dynamic backend\n# ==========================================================================\n\n\ndef select_sm120_moe_backend(\n *,\n num_tokens: int,\n num_topk: int,\n activation_precision: str = \"fp4\",\n quant_mode: str | None = None,\n) -> str:\n \"\"\"Pick static or dynamic backend based on routed-pair count.\"\"\"\n mode = _normalize_quant_mode(quant_mode, activation_precision)\n if mode == \"w4a16\":\n return \"w4a16\"\n if _FORCED_BACKEND == \"dynamic\":\n return \"dynamic\"\n if _FORCED_BACKEND in (\"static\", \"micro\", \"direct_micro\"):\n # Both micro variants launch through the static workspace path.\n return \"static\"\n routed_rows = num_tokens * num_topk\n if routed_rows <= _get_static_compact_cutover_pairs(\"fp4\"):\n return \"static\"\n return \"dynamic\"\n\n\n# ---------------------------------------------------------------------------\n# Dynamic workspace\n# ---------------------------------------------------------------------------\n@dataclass(kw_only=True)\nclass Sm120DynamicMoEWorkspace:\n \"\"\"Scratch buffers for one SM120 dynamic MoE launch.\"\"\"\n\n state_E: int\n weight_E: int\n max_rows: int\n k: int\n n: int\n num_topk: int\n device: torch.device\n activation_precision: str\n\n # Core buffers\n row_counts: torch.Tensor\n token_map: torch.Tensor\n token_weights: torch.Tensor\n packed_input: torch.Tensor\n packed_input_scale: torch.Tensor\n barrier_count: torch.Tensor\n barrier_epoch: torch.Tensor\n\n # Dynamic-specific\n routed_rows_capacity: int\n physical_tiles_capacity: int\n task_capacity: int\n # The M-tile the geometry above was sized for; launches must build the\n # kernel with the same tile.\n tile_m: int = _LEVEL_TILE_M\n expert_write_rows: torch.Tensor\n expert_tile_base: torch.Tensor\n pair_head: torch.Tensor\n task_head: torch.Tensor\n task_tail: torch.Tensor\n task_expert: torch.Tensor\n task_valid_rows: torch.Tensor\n\n # Views\n packed_a_view: torch.Tensor | None = None\n sfa_ptr: object = None\n packed_a_flat: torch.Tensor | None = None\n scale_flat: torch.Tensor | None = None\n\n\ndef _dynamic_task_geometry(\n state_E: int,\n n: int,\n routed_rows: int,\n *,\n tile_m: int = _LEVEL_TILE_M,\n tile_n: int = _LEVEL_TILE_N,\n):\n \"\"\"Compute task queue dimensions from problem geometry.\n\n Each active expert can introduce at most one additional physical tile\n beyond the base count (due to per-expert tail padding). The task queue\n holds one entry per (m_tile, slice_group) pair — NOT multiplied by E.\n \"\"\"\n routed_rows = max(1, routed_rows)\n base_m_tiles = _align_up(routed_rows, tile_m) // tile_m\n active_expert_upper_bound = min(state_E, routed_rows)\n max_m_tiles = max(1, base_m_tiles + active_expert_upper_bound - 1)\n gate_tile_cnt = max(1, (n + tile_n - 1) // tile_n)\n slice_groups = max(\n 1, (gate_tile_cnt + _DYNAMIC_SLICE_CHUNK - 1) // _DYNAMIC_SLICE_CHUNK\n )\n max_tasks = max_m_tiles * slice_groups\n return max_m_tiles, gate_tile_cnt, max_tasks\n\n\ndef allocate_sm120_dynamic_workspace(\n *,\n state_E: int,\n weight_E: int,\n routed_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation_precision: str = \"fp4\",\n activation: str = \"silu\",\n) -> Sm120DynamicMoEWorkspace:\n \"\"\"Allocate workspace buffers for the SM120 dynamic MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"allocate_sm120_dynamic_workspace only supports quant_mode='nvfp4'; \"\n \"use allocate_sm120_moe_workspace(..., quant_mode='w4a16') for W4A16.\"\n )\n tile_m = _select_dynamic_tile_m(routed_rows, state_E, activation)\n physical_tiles, _, max_tasks = _dynamic_task_geometry(\n state_E,\n n,\n routed_rows,\n tile_m=tile_m,\n tile_n=_level_tile_n(activation_precision),\n )\n rows_padded = physical_tiles * tile_m\n # The kernel addresses activation scales in 128-row SF atoms regardless of\n # tile_m, so the scale plane must cover the last partial atom.\n scale_rows = _align_up(rows_padded, 128)\n cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n _check_memref_limit(\"dynamic packed_input\", rows_padded * (k // 2))\n _check_memref_limit(\"dynamic packed_input_scale\", scale_rows * cols_pad_k)\n packed_input = torch.empty(1, rows_padded, k // 2, dtype=torch.uint8, device=device)\n\n workspace = Sm120DynamicMoEWorkspace(\n state_E=state_E,\n weight_E=weight_E,\n max_rows=rows_padded,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation_precision=activation_precision,\n routed_rows_capacity=routed_rows,\n physical_tiles_capacity=physical_tiles,\n task_capacity=max_tasks,\n tile_m=tile_m,\n row_counts=torch.zeros(state_E, dtype=torch.int32, device=device),\n token_map=torch.zeros(rows_padded, dtype=torch.int32, device=device),\n token_weights=torch.zeros(rows_padded, dtype=torch.float32, device=device),\n packed_input=packed_input,\n packed_input_scale=torch.empty(\n scale_rows, cols_pad_k, dtype=torch.uint8, device=device\n ),\n barrier_count=torch.zeros(1, dtype=torch.int32, device=device),\n barrier_epoch=torch.zeros(1, dtype=torch.int32, device=device),\n expert_write_rows=torch.zeros(state_E, dtype=torch.int32, device=device),\n expert_tile_base=torch.zeros(state_E + 1, dtype=torch.int32, device=device),\n pair_head=torch.zeros(1, dtype=torch.int32, device=device),\n task_head=torch.zeros(1, dtype=torch.int32, device=device),\n task_tail=torch.zeros(1, dtype=torch.int32, device=device),\n task_expert=torch.zeros(max_tasks, dtype=torch.int32, device=device),\n task_valid_rows=torch.zeros(max_tasks, dtype=torch.int32, device=device),\n )\n\n # Finalize views\n sf_dtype = cutlass.Float8E4M3FN\n workspace.packed_a_view = workspace.packed_input.permute(1, 2, 0).view(\n torch.float4_e2m1fn_x2\n )\n workspace.packed_a_flat = workspace.packed_input.view(-1)\n workspace.scale_flat = workspace.packed_input_scale.view(-1)\n workspace.sfa_ptr = make_ptr(\n sf_dtype,\n workspace.packed_input_scale.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n return workspace\n\n\n# ---------------------------------------------------------------------------\n# Dynamic kernel compilation\n# ---------------------------------------------------------------------------\n\n\nclass _DynamicMoELaunch:\n \"\"\"Thin JIT wrapper that makes num_tokens and max_rows runtime Int32.\"\"\"\n\n def __init__(self, kernel, k, num_topk, activation_precision: str = \"fp4\"):\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 dynamic launcher wrapper\"\n )\n self._kernel = kernel\n self._k = k\n self._packed_storage_cols = k // 2\n self._num_topk = num_topk\n self._cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n\n @cute.jit\n def __call__(\n self,\n a_ptr: cute.Pointer,\n topk_ids_ptr: cute.Pointer,\n topk_weights_ptr: cute.Pointer,\n packed_a_ptr: cute.Pointer,\n sfa_ptr: cute.Pointer,\n packed_a_storage_ptr: cute.Pointer,\n scale_storage_ptr: cute.Pointer,\n barrier_count: cute.Tensor,\n barrier_epoch: cute.Tensor,\n pair_head: cute.Tensor,\n task_head: cute.Tensor,\n task_tail: cute.Tensor,\n task_expert_ptr: cute.Pointer,\n task_valid_rows_ptr: cute.Pointer,\n b_w13: cute.Tensor,\n sfb_w13_ptr: cute.Pointer,\n b_down: cute.Tensor,\n sfb_down_ptr: cute.Pointer,\n row_counts: cute.Tensor,\n expert_write_rows: cute.Tensor,\n expert_tile_base: cute.Tensor,\n input_global_scale: cute.Tensor,\n alpha: cute.Tensor,\n down_alpha: cute.Tensor,\n global_scale: cute.Tensor,\n scatter_ptr: cute.Pointer,\n token_map_ptr: cute.Pointer,\n token_weights_ptr: cute.Pointer,\n num_tokens: cutlass.Int32,\n max_rows: cutlass.Int32,\n rows_padded: cutlass.Int32,\n max_tasks: cutlass.Int32,\n max_active_clusters: cutlass.Constexpr,\n stream,\n ):\n a_input = cute.make_tensor(\n a_ptr, layout=cute.make_layout((num_tokens, self._k), stride=(self._k, 1))\n )\n topk_ids = cute.make_tensor(\n topk_ids_ptr,\n layout=cute.make_layout((num_tokens * self._num_topk,), stride=(1,)),\n )\n topk_weights_t = cute.make_tensor(\n topk_weights_ptr,\n layout=cute.make_layout((num_tokens * self._num_topk,), stride=(1,)),\n )\n scatter_output = cute.make_tensor(\n scatter_ptr,\n layout=cute.make_layout((num_tokens, self._k), stride=(self._k, 1)),\n )\n packed_a = cute.make_tensor(\n packed_a_ptr,\n layout=cute.make_layout(\n (rows_padded, self._k, 1), stride=(self._k, 1, rows_padded * self._k)\n ),\n )\n packed_a_storage = cute.make_tensor(\n packed_a_storage_ptr,\n layout=cute.make_layout(\n (rows_padded * self._packed_storage_cols,), stride=(1,)\n ),\n )\n # Activation scales live in 128-row SF atoms; the plane is allocated\n # through the last partial atom even when rows_padded is not aligned.\n scale_rows = ((rows_padded + 127) // 128) * 128\n scale_storage = cute.make_tensor(\n scale_storage_ptr,\n layout=cute.make_layout((scale_rows * self._cols_pad_k,), stride=(1,)),\n )\n token_map = cute.make_tensor(\n token_map_ptr, layout=cute.make_layout((rows_padded,), stride=(1,))\n )\n token_weights_t = cute.make_tensor(\n token_weights_ptr, layout=cute.make_layout((rows_padded,), stride=(1,))\n )\n task_expert = cute.make_tensor(\n task_expert_ptr, layout=cute.make_layout((max_tasks,), stride=(1,))\n )\n task_valid_rows = cute.make_tensor(\n task_valid_rows_ptr, layout=cute.make_layout((max_tasks,), stride=(1,))\n )\n self._kernel(\n a_input,\n topk_ids,\n topk_weights_t,\n packed_a,\n sfa_ptr,\n packed_a_storage,\n scale_storage,\n barrier_count,\n barrier_epoch,\n pair_head,\n task_head,\n task_tail,\n task_expert,\n task_valid_rows,\n b_w13,\n sfb_w13_ptr,\n b_down,\n sfb_down_ptr,\n row_counts,\n expert_write_rows,\n expert_tile_base,\n input_global_scale,\n alpha,\n down_alpha,\n global_scale,\n scatter_output,\n token_map,\n token_weights_t,\n max_active_clusters=max_active_clusters,\n stream=stream,\n )\n\n\n_DYNAMIC_KERNEL_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_dynamic_kernel(\n E: int,\n m: int,\n k: int,\n n: int,\n num_topk: int,\n max_rows: int,\n *,\n topk_ids_dtype: torch.dtype = torch.int32,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n share_input_across_experts: bool = False,\n tile_m: int = _LEVEL_TILE_M,\n):\n \"\"\"Compile (or retrieve cached) the SM120 dynamic MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 dynamic compiler\"\n )\n # Both dynamic implementations reserve 32 route slots per token for the\n # shared-input fast path. Larger top-k values remain correct by using the\n # generic per-route producer instead.\n share_input_across_experts = bool(\n share_input_across_experts\n and activation_precision == \"fp4\"\n and num_topk <= _MAX_SHARED_INPUT_TOPK\n )\n sf_vec_size = 16\n sm_count = get_num_sm(torch.device(\"cuda\"))\n base_mac = min(get_max_active_clusters(1), sm_count)\n tuned_mac = _lookup_mac_ladder(_DYNAMIC_MAC_LADDER, m * num_topk)\n mac = min(tuned_mac or base_mac, base_mac)\n # tile_m comes from the workspace's shared selection so the kernel's task\n # and scale indexing matches the allocated scratch geometry.\n mma_tiler_mn = (tile_m, _level_tile_n(activation_precision))\n\n cache_key = _dynamic_kernel_cache_key(\n activation_precision=activation_precision,\n E=E,\n k=k,\n n=n,\n num_topk=num_topk,\n mac=mac,\n mma_tiler_mn=mma_tiler_mn,\n topk_ids_dtype=topk_ids_dtype,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n share_input_across_experts=share_input_across_experts,\n )\n cached = _DYNAMIC_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n return cached\n\n is_gated = is_gated_activation(activation)\n w1_rows = (2 if is_gated else 1) * n\n\n scratch_dtype = cutlass.Float4E2M1FN\n weight_dtype = cutlass.Float4E2M1FN\n sf_dtype = cutlass.Float8E4M3FN\n a_dtype = cutlass.BFloat16\n alpha_dtype = cutlass.Float32\n\n kernel: Any = MoEDynamicKernel(\n sf_vec_size=sf_vec_size,\n mma_tiler_mn=mma_tiler_mn,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n share_input_across_experts=share_input_across_experts,\n hidden_size=k,\n intermediate_size=n,\n num_topk=num_topk,\n )\n launch = _DynamicMoELaunch(\n kernel,\n k=k,\n num_topk=num_topk,\n activation_precision=activation_precision,\n )\n\n topk_ids_cutlass_dtype = (\n cutlass.Int32 if topk_ids_dtype == torch.int32 else cutlass.Int64\n )\n topk_ids_align = 4 if topk_ids_dtype == torch.int32 else 8\n\n # Runtime-shaped tensors passed as pointers\n a_input_fake = make_ptr(a_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n topk_ids_fake = make_ptr(\n topk_ids_cutlass_dtype,\n topk_ids_align,\n cute.AddressSpace.gmem,\n assumed_align=topk_ids_align,\n )\n topk_weights_fake = make_ptr(\n cutlass.Float32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n packed_a_fake = make_ptr(\n scratch_dtype, 16, cute.AddressSpace.gmem, assumed_align=16\n )\n sfa_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n packed_a_storage_fake = make_ptr(\n cutlass.Uint8, 16, cute.AddressSpace.gmem, assumed_align=16\n )\n scale_storage_fake = make_ptr(\n cutlass.Uint8, 16, cute.AddressSpace.gmem, assumed_align=16\n )\n\n barrier_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n barrier_epoch_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n pair_head_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n task_head_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n task_tail_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n\n task_expert_fake = make_ptr(\n cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n task_valid_rows_fake = make_ptr(\n cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n\n b_w13_fake = cute.runtime.make_fake_compact_tensor(\n weight_dtype,\n (w1_rows, k, E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_w13_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n b_down_fake = cute.runtime.make_fake_compact_tensor(\n weight_dtype,\n (k, n, E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_down_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n row_counts_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (E,), assumed_align=4\n )\n expert_write_rows_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (E,), assumed_align=4\n )\n expert_tile_base_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (E + 1,), assumed_align=4\n )\n input_gs_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype, (E,), assumed_align=16\n )\n alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype, (E,), assumed_align=16\n )\n down_alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype, (E,), assumed_align=16\n )\n global_scale_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype, (E,), assumed_align=16\n )\n scatter_fake = make_ptr(a_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n token_map_fake = make_ptr(cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4)\n token_weights_fake = make_ptr(\n alpha_dtype, 16, cute.AddressSpace.gmem, assumed_align=16\n )\n\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n compiled = build_and_load_cute_dsl_kernel(\n _CUTE_DSL_MODULE,\n _disk_kernel_name(f\"dynamic_e{E}_k{k}_n{n}_t{num_topk}\", cache_key),\n lambda: cute.compile(\n launch,\n a_input_fake,\n topk_ids_fake,\n topk_weights_fake,\n packed_a_fake,\n sfa_fake,\n packed_a_storage_fake,\n scale_storage_fake,\n barrier_count_fake,\n barrier_epoch_fake,\n pair_head_fake,\n task_head_fake,\n task_tail_fake,\n task_expert_fake,\n task_valid_rows_fake,\n b_w13_fake,\n sfb_w13_fake,\n b_down_fake,\n sfb_down_fake,\n row_counts_fake,\n expert_write_rows_fake,\n expert_tile_base_fake,\n input_gs_fake,\n alpha_fake,\n down_alpha_fake,\n global_scale_fake,\n scatter_fake,\n token_map_fake,\n token_weights_fake,\n 1,\n 1,\n 1,\n 1, # runtime Int32 placeholders\n mac,\n stream_fake,\n options=\"--opt-level 2 --enable-tvm-ffi\",\n ),\n extra_key_files=_kernel_source_files(),\n )\n\n result = (compiled, mac)\n _DYNAMIC_KERNEL_CACHE[cache_key] = result\n return result\n\n\n# ---------------------------------------------------------------------------\n# Dynamic launch\n# ---------------------------------------------------------------------------\ndef launch_sm120_dynamic_moe(\n *,\n workspace: Sm120DynamicMoEWorkspace,\n weights: _WeightViews,\n a: torch.Tensor,\n topk_ids: torch.Tensor,\n topk_weights: torch.Tensor,\n input_gs: torch.Tensor,\n down_input_scale: torch.Tensor,\n scatter_output: torch.Tensor,\n num_experts: int,\n num_tokens: int,\n k: int,\n n: int,\n top_k: int,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n) -> torch.Tensor:\n \"\"\"Launch the SM120 dynamic MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 dynamic launcher\"\n )\n _check_memref_limit(\"scatter_output\", scatter_output.numel())\n flat_ids = topk_ids.view(-1).to(torch.int32)\n flat_weights = topk_weights.view(-1).to(torch.float32)\n input_gs_is_shared = input_gs.numel() == 1\n\n # Broadcast scalar scales to per-expert [E] tensors\n input_gs = _expand_to_experts(input_gs, num_experts)\n down_input_scale = _expand_to_experts(down_input_scale, num_experts)\n\n compiled, mac = _get_dynamic_kernel(\n num_experts,\n num_tokens,\n k,\n n,\n top_k,\n workspace.max_rows,\n topk_ids_dtype=torch.int32,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n activation_precision=activation_precision,\n share_input_across_experts=input_gs_is_shared,\n tile_m=workspace.tile_m,\n )\n\n # Dynamic kernel: runtime-shaped args are DataPointer (pass data_ptr()),\n # fixed-shape args are Tensor (pass torch tensor directly). No stream\n # argument -- see the note in launch_sm120_static_moe.\n runtime_args: Tuple[Any, ...] = (\n a.data_ptr(),\n flat_ids.data_ptr(),\n flat_weights.data_ptr(),\n workspace.packed_a_view.data_ptr(),\n workspace.packed_input_scale.data_ptr(),\n workspace.packed_a_flat.data_ptr(),\n workspace.scale_flat.data_ptr(),\n workspace.barrier_count,\n workspace.barrier_epoch,\n workspace.pair_head,\n workspace.task_head,\n workspace.task_tail,\n workspace.task_expert.data_ptr(),\n workspace.task_valid_rows.data_ptr(),\n weights.w13_fp4,\n weights._w13_sf_storage.data_ptr(),\n weights.down_fp4,\n weights._down_sf_storage.data_ptr(),\n workspace.row_counts,\n workspace.expert_write_rows,\n workspace.expert_tile_base,\n input_gs,\n weights.w1_alpha,\n weights.w2_alpha,\n down_input_scale,\n scatter_output.data_ptr(),\n workspace.token_map.data_ptr(),\n workspace.token_weights.data_ptr(),\n num_tokens,\n workspace.max_rows,\n workspace.physical_tiles_capacity * workspace.tile_m,\n workspace.task_capacity,\n )\n compiled(*runtime_args)\n\n return scatter_output\n\n\n# ==========================================================================\n# W4A16 route-packing implementation\n# ==========================================================================\n@dataclass(kw_only=True)\nclass Sm120W4A16MoEWorkspace:\n \"\"\"Scratch buffers for the SM120 W4A16 MoE path.\"\"\"\n\n state_E: int\n weight_E: int\n max_rows: int\n k: int\n n: int\n num_topk: int\n device: torch.device\n activation: str\n activation_precision: str\n quant_mode: str\n routed_rows_capacity: int\n route_num_experts: int\n\n intermediate_cache13: torch.Tensor\n intermediate_cache2: torch.Tensor\n fc1_c_tmp: torch.Tensor\n fc2_c_tmp: torch.Tensor\n packed_route_indices: torch.Tensor\n block_expert_ids: torch.Tensor\n packed_route_count: torch.Tensor\n expert_offsets: torch.Tensor\n expert_map: torch.Tensor | None = None\n\n\ndef _is_cuda_graph_capturing() -> bool:\n try:\n return bool(torch.cuda.is_current_stream_capturing())\n except Exception:\n return False\n\n\ndef _canonical_cuda_device(device: torch.device) -> torch.device:\n device = torch.device(device)\n if device.type == \"cuda\" and device.index is None:\n return torch.device(\"cuda\", torch.cuda.current_device())\n return device\n\n\ndef _w4a16_workspace_geometry(\n *,\n routed_rows: int,\n route_num_experts: int,\n num_topk: int,\n k: int,\n n: int,\n is_gated: bool,\n device: torch.device,\n) -> tuple[int, int, int, int, int]:\n route_slots = 1\n route_blocks = 1\n fc1_c_tmp_elements = 1\n fc2_c_tmp_elements = 1\n fc1_cols = (2 if is_gated else 1) * int(n)\n sms = get_num_sm(device)\n # Size the route buffers for the power-of-2 capacity so route packing keeps\n # a single triton specialization across token counts.\n routed_rows_capacity = route_pack_numel_capacity(\n int(routed_rows), topk=int(num_topk)\n )\n for block_size in _W4A16_ALLOWED_ROUTED_SIZES:\n slots = max_packed_route_slots(\n routed_rows_capacity,\n int(block_size),\n int(route_num_experts),\n )\n blocks = (slots + int(block_size) - 1) // int(block_size)\n route_slots = max(route_slots, slots)\n route_blocks = max(route_blocks, blocks)\n fc1_c_tmp_elements = max(\n fc1_c_tmp_elements,\n packed_gemm_scratch_elements(\n size_n=fc1_cols,\n route_slots=slots,\n moe_block_size=int(block_size),\n sms=sms,\n ),\n )\n fc2_c_tmp_elements = max(\n fc2_c_tmp_elements,\n packed_gemm_scratch_elements(\n size_n=int(k),\n route_slots=slots,\n moe_block_size=int(block_size),\n sms=sms,\n ),\n )\n return (\n route_slots,\n route_blocks,\n fc1_c_tmp_elements,\n fc2_c_tmp_elements,\n fc1_cols,\n )\n\n\ndef _make_w4a16_expert_map(\n *,\n state_E: int,\n weight_E: int,\n device: torch.device,\n) -> torch.Tensor | None:\n if int(state_E) == int(weight_E):\n return None\n if int(state_E) > int(weight_E):\n raise ValueError(\"num_local_experts cannot exceed num_experts\")\n expert_map = torch.empty((int(weight_E),), dtype=torch.int32, device=device)\n expert_map.fill_(-1)\n expert_map[: int(state_E)].copy_(\n torch.arange(int(state_E), dtype=torch.int32, device=device)\n )\n return expert_map\n\n\ndef _allocate_sm120_w4a16_workspace(\n *,\n state_E: int,\n weight_E: int,\n routed_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation: str = \"silu\",\n) -> Sm120W4A16MoEWorkspace:\n is_gated = validate_activation(activation)\n routed_rows = max(1, int(routed_rows))\n route_num_experts = int(weight_E) if int(state_E) != int(weight_E) else int(state_E)\n (\n route_slots,\n route_blocks,\n fc1_c_tmp_elements,\n fc2_c_tmp_elements,\n fc1_cols,\n ) = _w4a16_workspace_geometry(\n routed_rows=routed_rows,\n route_num_experts=route_num_experts,\n num_topk=num_topk,\n k=k,\n n=n,\n is_gated=is_gated,\n device=device,\n )\n return Sm120W4A16MoEWorkspace(\n state_E=int(state_E),\n weight_E=int(weight_E),\n max_rows=routed_rows,\n k=int(k),\n n=int(n),\n num_topk=int(num_topk),\n device=device,\n activation=activation,\n activation_precision=\"bf16\",\n quant_mode=\"w4a16\",\n routed_rows_capacity=routed_rows,\n route_num_experts=route_num_experts,\n intermediate_cache13=torch.empty(\n (routed_rows * max(fc1_cols, int(k)),),\n dtype=torch.bfloat16,\n device=device,\n ),\n intermediate_cache2=torch.empty(\n (routed_rows, int(n)),\n dtype=torch.bfloat16,\n device=device,\n ),\n fc1_c_tmp=torch.empty(\n (fc1_c_tmp_elements,),\n dtype=torch.float32,\n device=device,\n ),\n fc2_c_tmp=torch.empty(\n (fc2_c_tmp_elements,),\n dtype=torch.float32,\n device=device,\n ),\n packed_route_indices=torch.empty(\n (route_slots,),\n dtype=torch.int32,\n device=device,\n ),\n block_expert_ids=torch.empty(\n (route_blocks,),\n dtype=torch.int32,\n device=device,\n ),\n packed_route_count=torch.empty((1,), dtype=torch.int32, device=device),\n expert_offsets=torch.empty(\n (route_num_experts + 1,),\n dtype=torch.int32,\n device=device,\n ),\n expert_map=_make_w4a16_expert_map(\n state_E=state_E,\n weight_E=weight_E,\n device=device,\n ),\n )\n\n\n_W4A16_WEIGHT_CACHE: Dict[Tuple, W4A16PackedWeights] = {}\n\n\ndef _get_w4a16_packed_weights(\n *,\n w1_weight: torch.Tensor,\n w1_weight_sf: torch.Tensor,\n w1_alpha: torch.Tensor,\n w2_weight: torch.Tensor,\n w2_weight_sf: torch.Tensor,\n w2_alpha: torch.Tensor,\n activation: str,\n params_dtype: torch.dtype,\n source_format: str = \"modelopt\",\n) -> W4A16PackedWeights:\n key = (\n activation,\n params_dtype,\n source_format,\n tuple(w1_weight.shape),\n tuple(w1_weight_sf.shape),\n tuple(w1_alpha.shape),\n tuple(w2_weight.shape),\n tuple(w2_weight_sf.shape),\n tuple(w2_alpha.shape),\n w1_weight.data_ptr(),\n w1_weight_sf.data_ptr(),\n w1_alpha.data_ptr(),\n w2_weight.data_ptr(),\n w2_weight_sf.data_ptr(),\n w2_alpha.data_ptr(),\n )\n cached = _W4A16_WEIGHT_CACHE.get(key)\n if cached is not None:\n return cached\n if _is_cuda_graph_capturing():\n raise RuntimeError(\n \"W4A16 packed weights are not initialized for CUDA graph capture; \"\n \"run once before capture so the prepared weights are cached.\"\n )\n prepared = prepare_w4a16_packed_weights(\n w1_weight,\n w1_weight_sf,\n w1_alpha,\n w2_weight,\n w2_weight_sf,\n w2_alpha,\n activation=activation,\n params_dtype=params_dtype,\n source_format=source_format,\n )\n _W4A16_WEIGHT_CACHE[key] = prepared\n _register_cache_eviction(\n _W4A16_WEIGHT_CACHE,\n key,\n w1_weight,\n w1_weight_sf,\n w1_alpha,\n w2_weight,\n w2_weight_sf,\n w2_alpha,\n )\n return prepared\n\n\ndef _validate_w4a16_workspace(\n workspace: Sm120W4A16MoEWorkspace,\n *,\n state_E: int,\n weight_E: int,\n routed_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation: str,\n) -> None:\n validate_activation(activation)\n if workspace.state_E != int(state_E) or workspace.weight_E != int(weight_E):\n raise ValueError(\"pre-allocated W4A16 workspace expert geometry mismatch\")\n if workspace.k != int(k) or workspace.n != int(n):\n raise ValueError(\"pre-allocated W4A16 workspace hidden geometry mismatch\")\n if workspace.num_topk != int(num_topk):\n raise ValueError(\"pre-allocated W4A16 workspace top-k mismatch\")\n if getattr(workspace, \"activation\", None) != activation:\n raise ValueError(\"pre-allocated W4A16 workspace activation mismatch\")\n if _canonical_cuda_device(workspace.device) != _canonical_cuda_device(device):\n raise ValueError(\n f\"pre-allocated W4A16 workspace is on {workspace.device}, expected {device}\"\n )\n if workspace.routed_rows_capacity < max(1, int(routed_rows)):\n raise ValueError(\n \"pre-allocated W4A16 workspace is too small for the requested \"\n f\"routed rows ({workspace.routed_rows_capacity} < {routed_rows})\"\n )\n\n\ndef _launch_sm120_w4a16_moe(\n *,\n a: torch.Tensor,\n topk_ids: torch.Tensor,\n topk_weights: torch.Tensor,\n w1_weight: torch.Tensor,\n w1_weight_sf: torch.Tensor,\n w1_alpha: torch.Tensor,\n w2_weight: torch.Tensor,\n w2_weight_sf: torch.Tensor,\n w2_alpha: torch.Tensor,\n num_experts: int,\n top_k: int,\n num_local_experts: int,\n scatter_output: torch.Tensor,\n fast_math: bool = True,\n activation: str = \"silu\",\n source_format: str = \"modelopt\",\n _workspace=None,\n _prepared_weights=None,\n) -> torch.Tensor:\n prepared = (\n _prepared_weights\n if isinstance(_prepared_weights, W4A16PackedWeights)\n else _get_w4a16_packed_weights(\n w1_weight=w1_weight,\n w1_weight_sf=w1_weight_sf,\n w1_alpha=w1_alpha,\n w2_weight=w2_weight,\n w2_weight_sf=w2_weight_sf,\n w2_alpha=w2_alpha,\n activation=activation,\n params_dtype=a.dtype,\n source_format=source_format,\n )\n )\n if int(prepared.num_experts) != int(num_local_experts):\n raise ValueError(\"num_local_experts must match w1_weight.shape[0] for W4A16.\")\n num_tokens = int(topk_ids.size(0))\n routed_rows = num_tokens * int(top_k)\n k = int(a.size(1))\n n = int(prepared.intermediate_size)\n\n if _workspace is None:\n workspace = _get_cached_workspace(\n backend=\"w4a16\",\n state_E=num_local_experts,\n weight_E=num_experts,\n routed_rows=routed_rows,\n k=k,\n n=n,\n num_topk=top_k,\n device=a.device,\n quant_mode=\"w4a16\",\n activation=activation,\n )\n else:\n workspace = _workspace\n if not isinstance(workspace, Sm120W4A16MoEWorkspace):\n raise TypeError(\"expected a W4A16 workspace for quant_mode='w4a16'\")\n _validate_w4a16_workspace(\n workspace,\n state_E=num_local_experts,\n weight_E=num_experts,\n routed_rows=routed_rows,\n k=k,\n n=n,\n num_topk=top_k,\n device=a.device,\n activation=activation,\n )\n\n return run_w4a16_moe(\n a,\n prepared,\n topk_weights,\n topk_ids,\n activation=activation,\n intermediate_cache13=workspace.intermediate_cache13,\n intermediate_cache2=workspace.intermediate_cache2,\n output=scatter_output,\n fc1_c_tmp=workspace.fc1_c_tmp,\n fc2_c_tmp=workspace.fc2_c_tmp,\n packed_route_indices=workspace.packed_route_indices,\n block_expert_ids=workspace.block_expert_ids,\n packed_route_count=workspace.packed_route_count,\n expert_offsets=workspace.expert_offsets,\n expert_map=workspace.expert_map,\n fast_math=fast_math,\n )\n\n\n# ==========================================================================\n# Workspace cache (for functional API path)\n# ==========================================================================\n\n_Sm120Workspace = Union[\n Sm120StaticMoEWorkspace,\n Sm120DynamicMoEWorkspace,\n Sm120W4A16MoEWorkspace,\n]\n\n# Stores the workspace with the largest capacity seen per key and never\n# shrinks within a process. clear_sm120_moe_caches() releases everything.\n_WORKSPACE_CACHE: Dict[Tuple, _Sm120Workspace] = {}\n\n\ndef clear_sm120_moe_caches() -> None:\n \"\"\"Release every module-level SM12x MoE cache.\n\n References held by callers are unaffected.\n \"\"\"\n _WORKSPACE_CACHE.clear()\n _WEIGHT_CACHE.clear()\n _W4A16_WEIGHT_CACHE.clear()\n _PADDED_WEIGHT_CACHE.clear()\n _STATIC_KERNEL_CACHE.clear()\n _MICRO_KERNEL_CACHE.clear()\n _DIRECT_MICRO_LAUNCH_CACHE.clear()\n _DIRECT_MICRO_KERNEL_CACHE.clear()\n _DYNAMIC_KERNEL_CACHE.clear()\n\n\ndef allocate_sm120_moe_workspace(\n *,\n state_E: int,\n weight_E: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n max_rows: int | None = None,\n routed_rows: int | None = None,\n quant_mode: str | None = None,\n activation_precision: str | None = None,\n backend: str | None = None,\n activation: str = \"silu\",\n) -> _Sm120Workspace:\n \"\"\"Allocate the right SM120 MoE workspace from a quantization mode.\"\"\"\n mode = _normalize_quant_mode(quant_mode, activation_precision)\n capacity_rows = routed_rows if routed_rows is not None else max_rows\n if capacity_rows is None:\n raise ValueError(\"routed_rows or max_rows is required\")\n capacity_rows = max(1, int(capacity_rows))\n device = torch.device(device)\n\n if mode == \"w4a16\":\n if backend not in (None, \"w4a16\"):\n raise ValueError(\"quant_mode='w4a16' does not use static/dynamic backend\")\n return _allocate_sm120_w4a16_workspace(\n state_E=state_E,\n weight_E=weight_E,\n routed_rows=capacity_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation=activation,\n )\n\n activation_precision = \"fp4\"\n if backend is None:\n backend = select_sm120_moe_backend(\n num_tokens=max(\n 1, (capacity_rows + max(1, int(num_topk)) - 1) // max(1, int(num_topk))\n ),\n num_topk=int(num_topk),\n activation_precision=activation_precision,\n )\n if backend == \"dynamic\":\n return allocate_sm120_dynamic_workspace(\n state_E=state_E,\n weight_E=weight_E,\n routed_rows=capacity_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation_precision=activation_precision,\n activation=activation,\n )\n if backend == \"static\":\n return allocate_sm120_static_workspace(\n state_E=state_E,\n weight_E=weight_E,\n max_rows=capacity_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation_precision=activation_precision,\n )\n raise ValueError(f\"unsupported SM120 MoE backend {backend!r}\")\n\n\ndef _get_cached_workspace(\n *,\n backend: str,\n state_E: int,\n weight_E: int,\n routed_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation_precision: str = \"fp4\",\n quant_mode: str | None = None,\n activation: str = \"silu\",\n) -> _Sm120Workspace:\n \"\"\"Get or allocate a cached workspace for the given problem shape.\n\n Reuses the cached workspace if it has enough capacity for the requested\n routed_rows. For static workspaces, max_rows is the direct capacity.\n For dynamic workspaces, routed_rows_capacity is used because the dynamic\n geometry (physical tiles, task queue slots) depends on the original\n routed_rows, not just max_rows.\n \"\"\"\n quant_mode = _normalize_quant_mode(quant_mode, activation_precision)\n activation_precision = _activation_precision_from_quant_mode(quant_mode)\n # Key dynamic workspaces on the tile band of this call's routed_rows; a\n # larger cached workspace must not pin small calls to its 128 tile.\n tile_m = (\n _select_dynamic_tile_m(max(1, routed_rows), state_E, activation)\n if backend == \"dynamic\" and quant_mode != \"w4a16\"\n else None\n )\n cache_key = (\n state_E,\n weight_E,\n k,\n n,\n num_topk,\n str(device),\n backend,\n quant_mode,\n activation,\n tile_m,\n )\n cached = _WORKSPACE_CACHE.get(cache_key)\n\n if cached is not None:\n if isinstance(cached, Sm120DynamicMoEWorkspace):\n if cached.routed_rows_capacity >= max(1, routed_rows):\n assert tile_m is None or cached.tile_m == tile_m\n return cached\n elif isinstance(cached, Sm120W4A16MoEWorkspace):\n if cached.routed_rows_capacity >= max(1, routed_rows):\n return cached\n else:\n if cached.max_rows >= max(1, routed_rows):\n return cached\n\n if quant_mode == \"w4a16\" and _is_cuda_graph_capturing():\n raise RuntimeError(\n \"W4A16 workspace is not initialized for CUDA graph capture; \"\n \"provide a preallocated workspace from \"\n \"allocate_sm120_moe_workspace(..., quant_mode='w4a16') or warm the \"\n \"functional path before capture.\"\n )\n workspace = allocate_sm120_moe_workspace(\n state_E=state_E,\n weight_E=weight_E,\n routed_rows=routed_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n quant_mode=quant_mode,\n activation_precision=activation_precision,\n backend=backend,\n activation=activation,\n )\n\n _WORKSPACE_CACHE[cache_key] = workspace\n return workspace\n\n\n# ==========================================================================\n# Unified dispatch\n# ==========================================================================\n_PADDED_WEIGHT_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _pad_intermediate_to_tile(\n w1_weight,\n w1_weight_sf,\n w2_weight,\n w2_weight_sf,\n fc2_input_scale,\n n,\n tile,\n h,\n num_experts,\n is_gated,\n):\n \"\"\"Zero-pad NVFP4 weights + scale factors so the intermediate size is a\n multiple of ``tile`` (gate/up tile-split requirement); padded channels are\n zero, so the result is numerically identical.\n \"\"\"\n n_pad = ((n + tile - 1) // tile) * tile\n if n_pad == n:\n return w1_weight, w1_weight_sf, w2_weight, w2_weight_sf, fc2_input_scale, n\n E = int(num_experts)\n fc2_input_scale_src = fc2_input_scale\n key = (\n n,\n tile,\n h,\n E,\n bool(is_gated),\n w1_weight.data_ptr(),\n w1_weight_sf.data_ptr(),\n w2_weight.data_ptr(),\n w2_weight_sf.data_ptr(),\n fc2_input_scale_src.data_ptr() if fc2_input_scale_src is not None else 0,\n )\n cached = _PADDED_WEIGHT_CACHE.get(key)\n if cached is not None:\n return cached\n\n def mma_to_logical(sf, m, k):\n sw = convert_sf_from_mma_layout(sf, m=m, k=k, num_groups=E)\n m_pad = ((m + 127) // 128) * 128\n sw = sw.reshape(E, m_pad, -1)\n cb = (k + SF_VEC_SIZE - 1) // SF_VEC_SIZE\n return torch.stack(\n [unswizzle_block_scale(sw[e], rows=m, cols_blocks=cb) for e in range(E)], 0\n )\n\n def logical_to_mma(log, m, k):\n sw = torch.stack([swizzle_block_scale(log[e]) for e in range(E)], 0)\n sw2d = sw.reshape(E * sw.shape[1], sw.shape[2]).to(torch.float8_e4m3fn)\n return convert_sf_to_mma_layout(sw2d, m=m, k=k, num_groups=E)\n\n def pad_dim(t, dim, old, new):\n if new == old:\n return t\n shp = list(t.shape)\n shp[dim] = new - old\n return torch.cat([t, t.new_zeros(shp)], dim=dim)\n\n if is_gated:\n # w1 packs [up(0:n), gate(n:2n)] rows; pad each half so the split stays\n # tile-aligned, then re-concat.\n up, gate = w1_weight[:, :n, :], w1_weight[:, n : 2 * n, :]\n w1p = torch.cat([pad_dim(up, 1, n, n_pad), pad_dim(gate, 1, n, n_pad)], dim=1)\n log1 = mma_to_logical(w1_weight_sf, m=2 * n, k=h)\n up_sf, gate_sf = log1[:, :n, :], log1[:, n : 2 * n, :]\n log1p = torch.cat(\n [pad_dim(up_sf, 1, n, n_pad), pad_dim(gate_sf, 1, n, n_pad)], dim=1\n )\n w1_sf_p = logical_to_mma(log1p, m=2 * n_pad, k=h)\n else:\n w1p = pad_dim(w1_weight, 1, n, n_pad)\n log1 = mma_to_logical(w1_weight_sf, m=n, k=h)\n w1_sf_p = logical_to_mma(pad_dim(log1, 1, n, n_pad), m=n_pad, k=h)\n\n # w2 reduces over the intermediate dim: pad its packed columns + SF columns.\n w2p = pad_dim(w2_weight, 2, n // 2, n_pad // 2)\n log2 = mma_to_logical(w2_weight_sf, m=h, k=n)\n cb_n = (n + SF_VEC_SIZE - 1) // SF_VEC_SIZE\n cb_np = (n_pad + SF_VEC_SIZE - 1) // SF_VEC_SIZE\n w2_sf_p = logical_to_mma(pad_dim(log2, 2, cb_n, cb_np), m=h, k=n_pad)\n\n if fc2_input_scale_src is not None and fc2_input_scale_src.numel() == n:\n fc2_input_scale = pad_dim(fc2_input_scale_src, 0, n, n_pad)\n result = (w1p, w1_sf_p, w2p, w2_sf_p, fc2_input_scale, n_pad)\n _PADDED_WEIGHT_CACHE[key] = result\n _register_cache_eviction(\n _PADDED_WEIGHT_CACHE,\n key,\n w1_weight,\n w1_weight_sf,\n w2_weight,\n w2_weight_sf,\n fc2_input_scale_src,\n )\n return result\n\n\ndef launch_sm120_moe(\n *,\n a: torch.Tensor,\n topk_ids: torch.Tensor,\n topk_weights: torch.Tensor,\n w1_weight: torch.Tensor,\n w1_weight_sf: torch.Tensor,\n w1_alpha: torch.Tensor,\n fc2_input_scale: Optional[torch.Tensor] = None,\n input_global_scale: Optional[torch.Tensor] = None,\n w2_weight: torch.Tensor,\n w2_weight_sf: torch.Tensor,\n w2_alpha: torch.Tensor,\n num_experts: int,\n top_k: int,\n num_local_experts: int,\n scatter_output: torch.Tensor,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n quant_mode: str | None = None,\n source_format: str = \"modelopt\",\n _workspace=None,\n _weight_views=None,\n _prepared_weights=None,\n) -> torch.Tensor:\n \"\"\"Unified SM120 MoE dispatch — selects static or dynamic by token count.\n\n input_global_scale overrides w1_alpha as the FC1 input-quant scale and\n is folded into the multiplier internally. With _weight_views supplied,\n w1_alpha must already contain the fold.\n\n Optional _workspace and _weight_views can be pre-allocated and reused\n across calls to avoid per-call allocation overhead (wrapper path).\n When not provided (functional API path), a module-level workspace cache\n is used to avoid re-allocating on every call.\n \"\"\"\n quant_mode = _normalize_quant_mode(quant_mode, activation_precision)\n source_format = _normalize_source_format_for_quant_mode(source_format, quant_mode)\n activation_precision = _activation_precision_from_quant_mode(quant_mode)\n\n num_tokens = topk_ids.size(0)\n k = a.size(1) # hidden_size\n is_gated = is_gated_activation(activation)\n # w1_weight.size(1) is 2*n for gated or n for non-gated\n intermediate_size = w1_weight.size(1) // 2 if is_gated else w1_weight.size(1)\n n = intermediate_size\n\n # NVFP4 kernels need padded intermediate size.\n if quant_mode != \"w4a16\" and n % _LEVEL_TILE_N != 0 and _weight_views is None:\n (\n w1_weight,\n w1_weight_sf,\n w2_weight,\n w2_weight_sf,\n fc2_input_scale,\n n,\n ) = _pad_intermediate_to_tile(\n w1_weight,\n w1_weight_sf,\n w2_weight,\n w2_weight_sf,\n fc2_input_scale,\n n,\n _LEVEL_TILE_N,\n k,\n w1_weight.size(0),\n is_gated,\n )\n\n routed_rows = num_tokens * top_k\n\n if quant_mode == \"w4a16\":\n return _launch_sm120_w4a16_moe(\n a=a,\n topk_ids=topk_ids,\n topk_weights=topk_weights,\n w1_weight=w1_weight,\n w1_weight_sf=w1_weight_sf,\n w1_alpha=w1_alpha,\n w2_weight=w2_weight,\n w2_weight_sf=w2_weight_sf,\n w2_alpha=w2_alpha,\n num_experts=num_experts,\n top_k=top_k,\n num_local_experts=num_local_experts,\n scatter_output=scatter_output,\n fast_math=fast_math,\n activation=activation,\n source_format=source_format,\n _workspace=_workspace,\n _prepared_weights=_prepared_weights,\n )\n\n if fc2_input_scale is None:\n raise ValueError(\"fc2_input_scale is required when quant_mode='nvfp4'.\")\n down_input_scale = fc2_input_scale\n if input_global_scale is not None:\n input_gs = input_global_scale\n if _weight_views is None:\n # Alpha must carry input_gs back or the output magnitude is wrong.\n # The wrapper folds before building _weight_views; don't fold twice.\n w1_alpha = (\n w1_alpha.to(torch.float32) * input_global_scale.to(torch.float32)\n ).contiguous()\n else:\n input_gs = w1_alpha\n\n weights = (\n _weight_views\n if _weight_views is not None\n else _get_weight_views(\n w1_fp4=w1_weight,\n w1_blockscale=w1_weight_sf,\n w2_fp4=w2_weight,\n w2_blockscale=w2_weight_sf,\n w1_alphas=w1_alpha,\n w2_alphas=w2_alpha,\n n=n,\n k=k,\n activation_precision=activation_precision,\n )\n )\n\n # Resolve workspace and backend selection.\n # When a pre-allocated workspace is provided (CUDA graph wrapper path),\n # infer the backend from the workspace type so they stay in sync —\n # the caller already committed to a backend at allocation time.\n if _workspace is not None:\n workspace = _workspace\n workspace_activation_precision = getattr(\n workspace, \"activation_precision\", activation_precision\n )\n if workspace_activation_precision != activation_precision:\n raise ValueError(\n \"pre-allocated workspace activation_precision does not match \"\n f\"requested activation_precision={activation_precision!r}.\"\n )\n if isinstance(workspace, Sm120DynamicMoEWorkspace):\n if num_local_experts != num_experts:\n raise ValueError(\n \"pre-allocated dynamic SM120 MoE workspace requires \"\n \"num_local_experts == num_experts because dynamic expert \"\n \"buffers are indexed by global topk ids.\"\n )\n # A pre-allocated dynamic workspace keeps its stored tile_m even\n # for smaller calls; its geometry was sized for that tile.\n backend = \"dynamic\"\n else:\n backend = \"static\"\n else:\n backend = select_sm120_moe_backend(\n num_tokens=num_tokens,\n num_topk=top_k,\n activation_precision=activation_precision,\n )\n # The dynamic kernel indexes row_counts/expert_write_rows directly with\n # topk_ids but those buffers are sized with num_local_experts. Unless\n # num_local_experts == num_experts, fall back to the static backend which\n # has global-to-local expert remapping.\n if backend == \"dynamic\" and num_local_experts != num_experts:\n backend = \"static\"\n workspace = _get_cached_workspace(\n backend=backend,\n state_E=num_local_experts,\n weight_E=num_experts,\n routed_rows=routed_rows,\n k=k,\n n=n,\n num_topk=top_k,\n device=a.device,\n activation_precision=activation_precision,\n quant_mode=quant_mode,\n activation=activation,\n )\n\n if backend == \"dynamic\":\n return launch_sm120_dynamic_moe(\n workspace=workspace,\n weights=weights,\n a=a,\n topk_ids=topk_ids,\n topk_weights=topk_weights,\n input_gs=input_gs,\n down_input_scale=down_input_scale,\n scatter_output=scatter_output,\n num_experts=num_experts,\n num_tokens=num_tokens,\n k=k,\n n=n,\n top_k=top_k,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n activation_precision=activation_precision,\n )\n else:\n return launch_sm120_static_moe(\n workspace=workspace,\n weights=weights,\n a=a,\n topk_ids=topk_ids,\n topk_weights=topk_weights,\n input_gs=input_gs,\n down_input_scale=down_input_scale,\n scatter_output=scatter_output,\n num_experts=num_experts,\n num_tokens=num_tokens,\n k=k,\n n=n,\n top_k=top_k,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n activation_precision=activation_precision,\n )\n"},"diff":{"kind":"string","value":"--- flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_dispatch.py\n+++ flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_dispatch.py\n@@ -7,6 +7,7 @@\n \n from __future__ import annotations\n \n+import hashlib\n import os\n import weakref\n from dataclasses import dataclass\n@@ -19,11 +20,11 @@\n from flashinfer.cute_dsl.utils import (\n convert_sf_from_mma_layout,\n convert_sf_to_mma_layout,\n- current_cuda_stream,\n get_max_active_clusters,\n get_num_sm,\n make_ptr,\n )\n+from flashinfer.jit.cute_dsl_core import build_and_load_cute_dsl_kernel\n from .moe_activation import SWIGLUOAI_UNINTERLEAVE, is_gated_activation\n from .moe_direct_micro_kernel import (\n MoEDirectMicroKernel,\n@@ -597,7 +598,201 @@\n \n # ---------------------------------------------------------------------------\n # Kernel compilation cache\n+#\n+# The three kernels below are compiled through the shared on-disk CuTe-DSL\n+# cache (#3874, #4029; docs/design_docs/cute_dsl_kernel_cache.md), so a fresh\n+# process JITLinks an exported ``.o`` instead of re-running the MLIR pipeline.\n+# The in-process dicts stay as the level-1 memoization the design describes.\n # ---------------------------------------------------------------------------\n+_CUTE_DSL_MODULE = \"b12x_moe\"\n+\n+\n+def _kernel_source_files() -> Tuple[str, ...]:\n+ \"\"\"Source files whose content invalidates the on-disk kernel cache.\n+\n+ Every module contributing device code to the three kernels compiled here:\n+ the kernel bodies, the shared activation and FP4 device helpers, and the\n+ SM120 layout builders and block-scaled mainloop they are built from.\n+ \"\"\"\n+ from flashinfer.cute_dsl import fp4_common\n+ from flashinfer.cute_dsl import utils as cute_dsl_utils\n+ from flashinfer.gemm.kernels import dense_blockscaled_gemm_sm120_b12x\n+\n+ from . import (\n+ moe_activation,\n+ moe_dynamic_kernel,\n+ moe_micro_kernel,\n+ moe_static_kernel,\n+ )\n+\n+ return (\n+ __file__,\n+ moe_activation.__file__,\n+ moe_static_kernel.__file__,\n+ moe_micro_kernel.__file__,\n+ moe_dynamic_kernel.__file__,\n+ cute_dsl_utils.__file__,\n+ fp4_common.__file__,\n+ dense_blockscaled_gemm_sm120_b12x.__file__,\n+ )\n+\n+\n+def _disk_kernel_name(prefix: str, cache_key: Tuple) -> str:\n+ \"\"\"On-disk specialization name for an in-process kernel cache key.\n+\n+ The name is the *sole* per-kernel cache key — the module ``meta.json``\n+ guards only module-wide facts (arch, DSL stack, source hashes) — so it has\n+ to be injective in every codegen parameter. It is therefore derived from\n+ the very tuple that keys the in-process cache: a readable shape prefix for\n+ humans browsing ``cached_ops/``, plus a digest of the exact tuple.\n+\n+ The digest, rather than a formatted field list, is what makes the mapping\n+ injective: the keys contain floats and ``None`` (``swiglu_alpha`` /\n+ ``swiglu_beta`` / ``swiglu_limit``) whose textual forms would collide once\n+ sanitized into a filename (``1.5`` and ``-1.5`` both sanitize to ``1_5``).\n+ \"\"\"\n+ digest = hashlib.sha256(repr(cache_key).encode()).hexdigest()[:16]\n+ return f\"{prefix}_{digest}\"\n+\n+\n+def _static_kernel_cache_key(\n+ *,\n+ activation_precision: str,\n+ state_E: int,\n+ weight_E: int,\n+ m: int,\n+ k: int,\n+ n: int,\n+ num_topk: int,\n+ max_rows: int,\n+ mac: int,\n+ mma_tiler_mn: Tuple[int, int],\n+ topk_ids_dtype: torch.dtype,\n+ input_scales_are_reciprocal: bool,\n+ fast_math: bool,\n+ activation: str,\n+ swiglu_alpha: float,\n+ swiglu_beta: float,\n+ swiglu_limit: float | None,\n+) -> Tuple:\n+ \"\"\"The static kernel's cache key: every parameter affecting its codegen.\n+\n+ Single source of truth for both cache levels — the in-process dict and,\n+ through :func:`_disk_kernel_name`, the on-disk artifact name.\n+ \"\"\"\n+ return (\n+ \"static\",\n+ activation_precision,\n+ state_E,\n+ weight_E,\n+ m,\n+ k,\n+ n,\n+ num_topk,\n+ max_rows,\n+ mac,\n+ mma_tiler_mn,\n+ topk_ids_dtype,\n+ input_scales_are_reciprocal,\n+ fast_math,\n+ activation,\n+ swiglu_alpha,\n+ swiglu_beta,\n+ swiglu_limit,\n+ )\n+\n+\n+def _micro_kernel_cache_key(\n+ *,\n+ state_E: int,\n+ weight_E: int,\n+ m: int,\n+ k: int,\n+ n: int,\n+ num_topk: int,\n+ max_rows: int,\n+ mac: int,\n+ mma_tiler_mn: Tuple[int, int],\n+ topk_ids_dtype: torch.dtype,\n+ input_scales_are_reciprocal: bool,\n+ fast_math: bool,\n+ share_input_across_experts: bool,\n+ share_expert_scales: bool,\n+ single_token: bool,\n+ activation: str,\n+ swiglu_alpha: float,\n+ swiglu_beta: float,\n+ swiglu_limit: float | None,\n+) -> Tuple:\n+ \"\"\"The micro kernel's cache key (see :func:`_static_kernel_cache_key`).\"\"\"\n+ return (\n+ \"micro\",\n+ state_E,\n+ weight_E,\n+ m,\n+ k,\n+ n,\n+ num_topk,\n+ max_rows,\n+ mac,\n+ mma_tiler_mn,\n+ topk_ids_dtype,\n+ input_scales_are_reciprocal,\n+ fast_math,\n+ share_input_across_experts,\n+ share_expert_scales,\n+ single_token,\n+ activation,\n+ swiglu_alpha,\n+ swiglu_beta,\n+ swiglu_limit,\n+ )\n+\n+\n+def _dynamic_kernel_cache_key(\n+ *,\n+ activation_precision: str,\n+ E: int,\n+ k: int,\n+ n: int,\n+ num_topk: int,\n+ mac: int,\n+ mma_tiler_mn: Tuple[int, int],\n+ topk_ids_dtype: torch.dtype,\n+ input_scales_are_reciprocal: bool,\n+ fast_math: bool,\n+ activation: str,\n+ swiglu_alpha: float,\n+ swiglu_beta: float,\n+ swiglu_limit: float | None,\n+ share_input_across_experts: bool,\n+) -> Tuple:\n+ \"\"\"The dynamic kernel's cache key (see :func:`_static_kernel_cache_key`).\n+\n+ Deliberately free of ``m`` / ``max_rows``: the dynamic kernel takes its\n+ runtime-shaped operands as pointers, so one artifact serves every batch\n+ size.\n+ \"\"\"\n+ return (\n+ \"dynamic\",\n+ activation_precision,\n+ E,\n+ k,\n+ n,\n+ num_topk,\n+ mac,\n+ mma_tiler_mn,\n+ topk_ids_dtype,\n+ input_scales_are_reciprocal,\n+ fast_math,\n+ activation,\n+ swiglu_alpha,\n+ swiglu_beta,\n+ swiglu_limit,\n+ share_input_across_experts,\n+ )\n+\n+\n _STATIC_KERNEL_CACHE: Dict[Tuple, Tuple] = {}\n \n \n@@ -640,25 +835,24 @@\n if activation_precision == \"fp4\" and num_topk > 1:\n mma_tiler_mn = _select_moe_mma_tiler_mn(routed_rows, n, resident_clusters=mac)\n \n- cache_key = (\n- \"static\",\n- activation_precision,\n- state_E,\n- weight_E,\n- m,\n- k,\n- n,\n- num_topk,\n- max_rows,\n- mac,\n- mma_tiler_mn,\n- topk_ids_dtype,\n- input_scales_are_reciprocal,\n- fast_math,\n- activation,\n- swiglu_alpha,\n- swiglu_beta,\n- swiglu_limit,\n+ cache_key = _static_kernel_cache_key(\n+ activation_precision=activation_precision,\n+ state_E=state_E,\n+ weight_E=weight_E,\n+ m=m,\n+ k=k,\n+ n=n,\n+ num_topk=num_topk,\n+ max_rows=max_rows,\n+ mac=mac,\n+ mma_tiler_mn=mma_tiler_mn,\n+ topk_ids_dtype=topk_ids_dtype,\n+ input_scales_are_reciprocal=input_scales_are_reciprocal,\n+ fast_math=fast_math,\n+ activation=activation,\n+ swiglu_alpha=swiglu_alpha,\n+ swiglu_beta=swiglu_beta,\n+ swiglu_limit=swiglu_limit,\n )\n cached = _STATIC_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n@@ -809,35 +1003,41 @@\n stride_order=(1, 0),\n assumed_align=16,\n )\n- compiled = cute.compile(\n- kernel,\n- a_input_fake,\n- topk_ids_fake,\n- topk_weights_fake,\n- packed_a_fake,\n- sfa_fake,\n- packed_a_storage_fake,\n- scale_storage_fake,\n- barrier_count_fake,\n- barrier_epoch_fake,\n- b_w13_fake,\n- sfb_w13_fake,\n- b_down_fake,\n- sfb_down_fake,\n- row_counts_fake,\n- active_expert_count_fake,\n- weight_expert_ids_fake,\n- global_to_local_expert_fake,\n- input_gs_fake,\n- alpha_fake,\n- down_alpha_fake,\n- global_scale_fake,\n- scatter_fake,\n- token_map_fake,\n- token_weights_fake,\n- mac,\n- current_cuda_stream(),\n- options=\"--opt-level 2 --enable-tvm-ffi\",\n+ stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n+ compiled = build_and_load_cute_dsl_kernel(\n+ _CUTE_DSL_MODULE,\n+ _disk_kernel_name(f\"static_m{m}_k{k}_n{n}_t{num_topk}_r{max_rows}\", cache_key),\n+ lambda: cute.compile(\n+ kernel,\n+ a_input_fake,\n+ topk_ids_fake,\n+ topk_weights_fake,\n+ packed_a_fake,\n+ sfa_fake,\n+ packed_a_storage_fake,\n+ scale_storage_fake,\n+ barrier_count_fake,\n+ barrier_epoch_fake,\n+ b_w13_fake,\n+ sfb_w13_fake,\n+ b_down_fake,\n+ sfb_down_fake,\n+ row_counts_fake,\n+ active_expert_count_fake,\n+ weight_expert_ids_fake,\n+ global_to_local_expert_fake,\n+ input_gs_fake,\n+ alpha_fake,\n+ down_alpha_fake,\n+ global_scale_fake,\n+ scatter_fake,\n+ token_map_fake,\n+ token_weights_fake,\n+ mac,\n+ stream_fake,\n+ options=\"--opt-level 2 --enable-tvm-ffi\",\n+ ),\n+ extra_key_files=_kernel_source_files(),\n )\n \n result = (compiled, mac)\n@@ -882,27 +1082,26 @@\n routed_rows = m * num_topk\n mma_tiler_mn = _select_moe_mma_tiler_mn(routed_rows, n)\n \n- cache_key = (\n- \"micro\",\n- state_E,\n- weight_E,\n- m,\n- k,\n- n,\n- num_topk,\n- max_rows,\n- mac,\n- mma_tiler_mn,\n- topk_ids_dtype,\n- input_scales_are_reciprocal,\n- fast_math,\n- share_input_across_experts,\n- share_expert_scales,\n- single_token,\n- activation,\n- swiglu_alpha,\n- swiglu_beta,\n- swiglu_limit,\n+ cache_key = _micro_kernel_cache_key(\n+ state_E=state_E,\n+ weight_E=weight_E,\n+ m=m,\n+ k=k,\n+ n=n,\n+ num_topk=num_topk,\n+ max_rows=max_rows,\n+ mac=mac,\n+ mma_tiler_mn=mma_tiler_mn,\n+ topk_ids_dtype=topk_ids_dtype,\n+ input_scales_are_reciprocal=input_scales_are_reciprocal,\n+ fast_math=fast_math,\n+ share_input_across_experts=share_input_across_experts,\n+ share_expert_scales=share_expert_scales,\n+ single_token=single_token,\n+ activation=activation,\n+ swiglu_alpha=swiglu_alpha,\n+ swiglu_beta=swiglu_beta,\n+ swiglu_limit=swiglu_limit,\n )\n cached = _MICRO_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n@@ -1054,35 +1253,41 @@\n stride_order=(1, 0),\n assumed_align=16,\n )\n- compiled = cute.compile(\n- kernel,\n- a_input_fake,\n- topk_ids_fake,\n- topk_weights_fake,\n- packed_a_fake,\n- sfa_fake,\n- packed_a_storage_fake,\n- scale_storage_fake,\n- barrier_count_fake,\n- barrier_epoch_fake,\n- b_w13_fake,\n- sfb_w13_fake,\n- b_down_fake,\n- sfb_down_fake,\n- row_counts_fake,\n- active_expert_count_fake,\n- weight_expert_ids_fake,\n- global_to_local_expert_fake,\n- input_gs_fake,\n- alpha_fake,\n- down_alpha_fake,\n- global_scale_fake,\n- scatter_fake,\n- token_map_fake,\n- token_weights_fake,\n- mac,\n- current_cuda_stream(),\n- options=\"--opt-level 2 --enable-tvm-ffi\",\n+ stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n+ compiled = build_and_load_cute_dsl_kernel(\n+ _CUTE_DSL_MODULE,\n+ _disk_kernel_name(f\"micro_m{m}_k{k}_n{n}_t{num_topk}_r{max_rows}\", cache_key),\n+ lambda: cute.compile(\n+ kernel,\n+ a_input_fake,\n+ topk_ids_fake,\n+ topk_weights_fake,\n+ packed_a_fake,\n+ sfa_fake,\n+ packed_a_storage_fake,\n+ scale_storage_fake,\n+ barrier_count_fake,\n+ barrier_epoch_fake,\n+ b_w13_fake,\n+ sfb_w13_fake,\n+ b_down_fake,\n+ sfb_down_fake,\n+ row_counts_fake,\n+ active_expert_count_fake,\n+ weight_expert_ids_fake,\n+ global_to_local_expert_fake,\n+ input_gs_fake,\n+ alpha_fake,\n+ down_alpha_fake,\n+ global_scale_fake,\n+ scatter_fake,\n+ token_map_fake,\n+ token_weights_fake,\n+ mac,\n+ stream_fake,\n+ options=\"--opt-level 2 --enable-tvm-ffi\",\n+ ),\n+ extra_key_files=_kernel_source_files(),\n )\n \n result = (compiled, mac)\n@@ -1463,6 +1668,10 @@\n launch_ids = flat_ids\n \n # Pointer arguments must be passed as raw ints (data_ptr()) at runtime.\n+ # No stream argument: the kernels compile against\n+ # ``make_fake_stream(use_tvm_ffi_env_stream=True)``, so TVM-FFI supplies\n+ # the caller's current stream and the parameter is absent from the\n+ # compiled signature.\n runtime_args: Tuple[Any, ...] = (\n a,\n launch_ids,\n@@ -1489,7 +1698,7 @@\n workspace.token_map,\n workspace.token_weights,\n )\n- compiled(*runtime_args, current_cuda_stream())\n+ compiled(*runtime_args)\n \n return scatter_output\n \n@@ -1860,23 +2069,22 @@\n # and scale indexing matches the allocated scratch geometry.\n mma_tiler_mn = (tile_m, _level_tile_n(activation_precision))\n \n- cache_key = (\n- \"dynamic\",\n- activation_precision,\n- E,\n- k,\n- n,\n- num_topk,\n- mac,\n- mma_tiler_mn,\n- topk_ids_dtype,\n- input_scales_are_reciprocal,\n- fast_math,\n- activation,\n- swiglu_alpha,\n- swiglu_beta,\n- swiglu_limit,\n- share_input_across_experts,\n+ cache_key = _dynamic_kernel_cache_key(\n+ activation_precision=activation_precision,\n+ E=E,\n+ k=k,\n+ n=n,\n+ num_topk=num_topk,\n+ mac=mac,\n+ mma_tiler_mn=mma_tiler_mn,\n+ topk_ids_dtype=topk_ids_dtype,\n+ input_scales_are_reciprocal=input_scales_are_reciprocal,\n+ fast_math=fast_math,\n+ activation=activation,\n+ swiglu_alpha=swiglu_alpha,\n+ swiglu_beta=swiglu_beta,\n+ swiglu_limit=swiglu_limit,\n+ share_input_across_experts=share_input_across_experts,\n )\n cached = _DYNAMIC_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n@@ -2003,43 +2211,49 @@\n alpha_dtype, 16, cute.AddressSpace.gmem, assumed_align=16\n )\n \n- compiled = cute.compile(\n- launch,\n- a_input_fake,\n- topk_ids_fake,\n- topk_weights_fake,\n- packed_a_fake,\n- sfa_fake,\n- packed_a_storage_fake,\n- scale_storage_fake,\n- barrier_count_fake,\n- barrier_epoch_fake,\n- pair_head_fake,\n- task_head_fake,\n- task_tail_fake,\n- task_expert_fake,\n- task_valid_rows_fake,\n- b_w13_fake,\n- sfb_w13_fake,\n- b_down_fake,\n- sfb_down_fake,\n- row_counts_fake,\n- expert_write_rows_fake,\n- expert_tile_base_fake,\n- input_gs_fake,\n- alpha_fake,\n- down_alpha_fake,\n- global_scale_fake,\n- scatter_fake,\n- token_map_fake,\n- token_weights_fake,\n- 1,\n- 1,\n- 1,\n- 1, # runtime Int32 placeholders\n- mac,\n- current_cuda_stream(),\n- options=\"--opt-level 2 --enable-tvm-ffi\",\n+ stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n+ compiled = build_and_load_cute_dsl_kernel(\n+ _CUTE_DSL_MODULE,\n+ _disk_kernel_name(f\"dynamic_e{E}_k{k}_n{n}_t{num_topk}\", cache_key),\n+ lambda: cute.compile(\n+ launch,\n+ a_input_fake,\n+ topk_ids_fake,\n+ topk_weights_fake,\n+ packed_a_fake,\n+ sfa_fake,\n+ packed_a_storage_fake,\n+ scale_storage_fake,\n+ barrier_count_fake,\n+ barrier_epoch_fake,\n+ pair_head_fake,\n+ task_head_fake,\n+ task_tail_fake,\n+ task_expert_fake,\n+ task_valid_rows_fake,\n+ b_w13_fake,\n+ sfb_w13_fake,\n+ b_down_fake,\n+ sfb_down_fake,\n+ row_counts_fake,\n+ expert_write_rows_fake,\n+ expert_tile_base_fake,\n+ input_gs_fake,\n+ alpha_fake,\n+ down_alpha_fake,\n+ global_scale_fake,\n+ scatter_fake,\n+ token_map_fake,\n+ token_weights_fake,\n+ 1,\n+ 1,\n+ 1,\n+ 1, # runtime Int32 placeholders\n+ mac,\n+ stream_fake,\n+ options=\"--opt-level 2 --enable-tvm-ffi\",\n+ ),\n+ extra_key_files=_kernel_source_files(),\n )\n \n result = (compiled, mac)\n@@ -2108,7 +2322,8 @@\n )\n \n # Dynamic kernel: runtime-shaped args are DataPointer (pass data_ptr()),\n- # fixed-shape args are Tensor (pass torch tensor directly).\n+ # fixed-shape args are Tensor (pass torch tensor directly). No stream\n+ # argument -- see the note in launch_sm120_static_moe.\n runtime_args: Tuple[Any, ...] = (\n a.data_ptr(),\n flat_ids.data_ptr(),\n@@ -2143,7 +2358,7 @@\n workspace.physical_tiles_capacity * workspace.tile_m,\n workspace.task_capacity,\n )\n- compiled(*runtime_args, current_cuda_stream())\n+ compiled(*runtime_args)\n \n return scatter_output\n "},"lines_added":{"kind":"number","value":371,"string":"371"},"lines_removed":{"kind":"number","value":156,"string":"156"},"files_in_commit":{"kind":"number","value":1,"string":"1"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["SM120","SM121"],"string":"[\n \"SM120\",\n \"SM121\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":["135×"],"string":"[\n \"135×\"\n]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cute_dsl kernel file from flashinfer (flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_dispatch.py).\n\nGoal: perf(moe): persist b12x MoE CuTe-DSL kernels to the disk cache\nTarget hardware: SM120, SM121\nTarget models: unspecified\n\nCurrent file:\n```python\n\"\"\"SM120/SM121 MoE dispatch layer — workspace, compilation, and launch.\n\nPorted from b12x's integration/tp_moe.py. Supports micro (tiny decode),\nstatic (decode), and dynamic (prefill) backends with token-count-based\nselection.\n\"\"\"\n\nfrom __future__ import annotations\n\nimport os\nimport weakref\nfrom dataclasses import dataclass\nfrom typing import Any, Dict, Optional, Tuple, Union\n\nimport cutlass\nimport cutlass.cute as cute\nimport torch\n\nfrom flashinfer.cute_dsl.utils import (\n convert_sf_from_mma_layout,\n convert_sf_to_mma_layout,\n current_cuda_stream,\n get_max_active_clusters,\n get_num_sm,\n make_ptr,\n)\nfrom .moe_activation import SWIGLUOAI_UNINTERLEAVE, is_gated_activation\nfrom .moe_direct_micro_kernel import (\n MoEDirectMicroKernel,\n build_direct_micro_kernel,\n compile_direct_micro_kernel,\n compiled_direct_micro_accepts_block_dim,\n)\nfrom .moe_dynamic_kernel import (\n _MAX_SHARED_INPUT_TOPK,\n _TASK_SLICE_CHUNK,\n MoEDynamicKernel,\n)\nfrom .moe_micro_kernel import MoEMicroKernel\nfrom .moe_static_kernel import MoEStaticKernel\nfrom .moe_w4a16_fp4_helpers import swizzle_block_scale\nfrom .moe_w4a16_host import (\n _W4A16_ALLOWED_ROUTED_SIZES,\n max_packed_route_slots,\n packed_gemm_scratch_elements,\n route_pack_numel_capacity,\n unswizzle_block_scale,\n validate_activation,\n)\nfrom .moe_w4a16_kernel import run_w4a16_moe\nfrom .moe_w4a16_prepare import (\n W4A16PackedWeights,\n _normalize_source_format,\n prepare_w4a16_packed_weights,\n)\n\n# ---------------------------------------------------------------------------\n# Constants\n# ---------------------------------------------------------------------------\n_NVFP4_BLOCK_SIZE = 16\n_LEVEL_TILE_M = 128\n_LEVEL_TILE_N = 128\n# Must equal the kernel's task materialization granularity or the task\n# queue is mis-sized.\n_DYNAMIC_SLICE_CHUNK = _TASK_SLICE_CHUNK\nSF_VEC_SIZE = 16\n_FORCE_MOE_W4A16_ENV = \"FLASHINFER_B12X_FORCE_MOE_W4A16\"\n_MICRO_SHARE_INPUT_ACROSS_EXPERTS = (\n os.environ.get(\"FLASHINFER_B12X_MICRO_SHARE_INPUT\", \"1\") != \"0\"\n)\n\n# Micro kernel cutover thresholds (routed pairs)\n_MICRO_COMPACT_CUTOVER_PAIRS = 20\n_MICRO_COMPACT_CUTOVER_PAIRS_MULTI_TOPK = 40\n# The micro kernel's per-token staging assumes decode-sized batches.\n_MICRO_MAX_TOKENS = 8\n# Direct micro takes the smallest decode batches ahead of the MMA micro\n# kernel, and only at small intermediate sizes where its CUDA-core dots\n# keep up with per-token work. Measured on GB10, pending other GPUs.\n_DIRECT_MICRO_CUTOVER_PAIRS = 32\n_DIRECT_MICRO_MAX_N = 512\n# Test/bench hook: force one backend (\"direct_micro\", \"micro\", \"static\",\n# \"dynamic\"). Deliberately module-level (a monkeypatch target), not an env var.\n_FORCED_BACKEND: str | None = None\n_STATIC_COMPACT_CUTOVER_PAIRS_DEFAULT = 640\n_STATIC_COMPACT_CUTOVER_PAIRS = _STATIC_COMPACT_CUTOVER_PAIRS_DEFAULT\n_STATIC_COMPACT_CUTOVER_PAIRS_CACHE: Dict[str, int] = {}\n\n# MAC (max active clusters) tuning ladders from b12x decode profiling.\n# Each entry is (max_routed_rows, optimal_mac).\n_MICRO_MAC_LADDER: Tuple[Tuple[int, int], ...] = (\n (2, 84),\n (4, 127),\n (8, 107),\n (10, 84),\n (16, 63),\n (20, 84),\n)\n_STATIC_MAC_LADDER: Tuple[Tuple[int, int], ...] = (\n (24, 148),\n (32, 169),\n (40, 132),\n (48, 149),\n (64, 134),\n (80, 175),\n (96, 171),\n (120, 125),\n (128, 130),\n (160, 171),\n (192, 166),\n (256, 141),\n (320, 158),\n (512, 175),\n (640, 188),\n)\n# Workloads at or below the static cutover (640 routed pairs by default)\n# take the static kernel, so only the 1024 entry is normally reachable.\n_DYNAMIC_MAC_LADDER: Tuple[Tuple[int, int], ...] = (\n (640, 188),\n (1024, 147),\n)\n\n\ndef _lookup_mac_ladder(\n ladder: Tuple[Tuple[int, int], ...], routed_rows: int\n) -> int | None:\n \"\"\"Look up optimal MAC from a tuning ladder. Returns None if no match.\"\"\"\n for end_rows, mac in ladder:\n if routed_rows <= end_rows:\n return mac\n return None\n\n\ndef _align_up(value: int, alignment: int) -> int:\n return ((value + alignment - 1) // alignment) * alignment\n\n\n# The kernels index the packed activation and scale planes with 32-bit\n# offsets, so reject any workspace plane large enough to overflow them.\n_RUNTIME_MEMREF_LIMIT = (1 << 31) - 1\n\n\ndef _check_memref_limit(name: str, elements: int) -> None:\n if elements > _RUNTIME_MEMREF_LIMIT:\n raise ValueError(\n f\"{name} needs {elements} elements, which exceeds the 2^31-1 \"\n \"runtime memref limit. Reduce the token chunk or expert count \"\n \"for this launch.\"\n )\n\n\ndef _first_env(*names: str) -> str | None:\n for name in names:\n value = os.environ.get(name)\n if value is not None:\n return value\n return None\n\n\ndef _normalize_activation_precision(activation_precision: str) -> str:\n \"\"\"Normalize public activation-precision names to internal modes.\"\"\"\n if os.environ.get(_FORCE_MOE_W4A16_ENV, \"0\") == \"1\":\n return \"bf16\"\n\n normalized = str(activation_precision).lower()\n aliases = {\n \"fp4\": \"fp4\",\n \"nvfp4\": \"fp4\",\n \"w4a4\": \"fp4\",\n \"bf16\": \"bf16\",\n \"w4a16\": \"bf16\",\n }\n try:\n return aliases[normalized]\n except KeyError as exc:\n raise ValueError(\n \"activation_precision must be 'fp4' or 'bf16' \"\n f\"(got {activation_precision!r}).\"\n ) from exc\n\n\ndef _normalize_quant_mode(\n quant_mode: str | None = None,\n activation_precision: str | None = None,\n) -> str:\n \"\"\"Normalize public quantization names to the dispatch mode.\"\"\"\n if os.environ.get(_FORCE_MOE_W4A16_ENV, \"0\") == \"1\":\n return \"w4a16\"\n if quant_mode is None:\n activation_precision = _normalize_activation_precision(\n activation_precision or \"fp4\"\n )\n return \"w4a16\" if activation_precision == \"bf16\" else \"nvfp4\"\n\n normalized = str(quant_mode).lower()\n aliases = {\n \"fp4\": \"nvfp4\",\n \"nvfp4\": \"nvfp4\",\n \"w4a4\": \"nvfp4\",\n \"bf16\": \"w4a16\",\n \"w4a16\": \"w4a16\",\n }\n try:\n return aliases[normalized]\n except KeyError as exc:\n raise ValueError(\n f\"quant_mode must be 'nvfp4'/'w4a4' or 'w4a16' (got {quant_mode!r}).\"\n ) from exc\n\n\ndef _activation_precision_from_quant_mode(quant_mode: str) -> str:\n return \"bf16\" if _normalize_quant_mode(quant_mode) == \"w4a16\" else \"fp4\"\n\n\ndef _normalize_source_format_for_quant_mode(source_format: str, quant_mode: str) -> str:\n normalized = _normalize_source_format(source_format)\n if quant_mode == \"nvfp4\" and normalized == \"compressed_tensors\":\n raise ValueError(\n \"source_format='compressed_tensors' requires quant_mode='w4a16'.\"\n )\n return normalized\n\n\ndef _is_w4a16(activation_precision: str) -> bool:\n return _normalize_activation_precision(activation_precision) == \"bf16\"\n\n\ndef _level_tile_n(activation_precision: str = \"fp4\") -> int:\n if _is_w4a16(activation_precision):\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 tile selector\"\n )\n return _LEVEL_TILE_N\n\n\ndef _select_dynamic_tile_m(\n routed_rows: int,\n num_experts: int,\n activation: str = \"silu\",\n) -> int:\n \"\"\"Pick the dynamic kernel's M-tile from routed rows per expert.\n\n Small tiles cut per-expert tail padding for sparse routing; 128 amortizes\n best for dense prefill (crossovers measured on gated NVFP4). Workspace\n sizing and the kernel build must both derive the tile from this function,\n or the scratch is mis-sized for what the kernel indexes.\n \"\"\"\n if not is_gated_activation(activation):\n return _LEVEL_TILE_M\n routed_rows = max(1, int(routed_rows))\n num_experts = max(1, int(num_experts))\n if routed_rows < 15 * num_experts:\n return 16\n if routed_rows < 48 * num_experts:\n return 32\n if routed_rows < 96 * num_experts:\n return 64\n return _LEVEL_TILE_M\n\n\ndef _get_static_compact_cutover_pairs(activation_precision: str = \"fp4\") -> int:\n activation_precision = _normalize_activation_precision(activation_precision)\n cached = _STATIC_COMPACT_CUTOVER_PAIRS_CACHE.get(activation_precision)\n if cached is not None:\n return cached\n\n cutover_names: tuple[str, ...] = (\n \"FLASHINFER_B12X_STATIC_COMPACT_CUTOVER_PAIRS\",\n \"B12X_STATIC_COMPACT_CUTOVER_PAIRS\",\n \"B12X_DYNAMIC_STATIC_CUTOVER_PAIRS\",\n \"B12X_LEVEL10_STATIC_CUTOVER_PAIRS\",\n )\n cutover = _first_env(*cutover_names)\n if cutover is None:\n cached = _STATIC_COMPACT_CUTOVER_PAIRS_DEFAULT\n else:\n cached = max(0, int(cutover))\n _STATIC_COMPACT_CUTOVER_PAIRS_CACHE[activation_precision] = cached\n return cached\n\n\ndef _select_moe_mma_tiler_mn(\n routed_rows: int,\n n: int,\n *,\n resident_clusters: int | None = None,\n) -> Tuple[int, int]:\n \"\"\"Select optimal MoE tile shape based on routed rows and N dimension.\n\n Uses narrower 64x128 tiles when routed_rows <= 128 and default 128x128\n would leave SMs idle.\n \"\"\"\n sm_count = get_num_sm(torch.device(\"cuda\"))\n coarse_tile = (128, 128)\n if routed_rows <= 32 and n <= 256:\n return (64, 128)\n if resident_clusters is not None and resident_clusters < sm_count:\n return coarse_tile\n coarse_tiles = ((routed_rows + coarse_tile[0] - 1) // coarse_tile[0]) * (\n (n + coarse_tile[1] - 1) // coarse_tile[1]\n )\n # Single-token decode often lands exactly on the \"half the machine\"\n # boundary. Keeping the coarse 128x128 tile there leaves the M dimension\n # badly underfilled, so take the narrow 64x128 tile inclusive of equality.\n if routed_rows <= 64 or (\n routed_rows <= 128 and coarse_tiles <= max(1, sm_count // 2)\n ):\n return (64, 128)\n return (128, 128)\n\n\ndef _as_grouped_scale_view(\n scale_storage: torch.Tensor,\n rows: int,\n cols: int,\n) -> torch.Tensor:\n \"\"\"Create 6D MMA-compatible scale factor view from swizzled storage.\"\"\"\n batch = scale_storage.shape[0]\n rows_padded = _align_up(rows, 128)\n cols_padded = _align_up(cols // SF_VEC_SIZE, 4)\n sf = scale_storage.view(torch.float8_e4m3fn)\n sf = sf.view(batch, rows_padded // 128, cols_padded // 4, 32, 4, 4)\n return sf.permute(3, 4, 1, 5, 2, 0)\n\n\n# ---------------------------------------------------------------------------\n# Workspace\n# ---------------------------------------------------------------------------\n@dataclass(kw_only=True)\nclass Sm120StaticMoEWorkspace:\n \"\"\"Scratch buffers for one SM120 static MoE launch.\"\"\"\n\n state_E: int\n weight_E: int\n max_rows: int\n k: int\n n: int\n num_topk: int\n device: torch.device\n activation_precision: str\n\n # Buffers\n row_counts: torch.Tensor # [state_E] int32\n token_map: torch.Tensor # [state_E, max_rows] int32\n token_weights: torch.Tensor # [state_E, max_rows] float32\n packed_input: torch.Tensor # [state_E, max_rows, k//2] uint8\n packed_input_scale: torch.Tensor # [state_E, rows_pad_k, cols_pad_k] uint8\n barrier_count: torch.Tensor # [1] int32\n barrier_epoch: torch.Tensor # [1] int32\n active_expert_count: torch.Tensor # [1] int32\n weight_expert_ids: torch.Tensor # [state_E] int32\n global_to_local_expert: torch.Tensor # [weight_E] int32\n compact_topk_ids: torch.Tensor # [state_E] int32, for micro kernel pre-pass\n\n # Views (set after allocation)\n packed_a_view: torch.Tensor | None = None\n sfa_ptr: object = None\n packed_a_flat: torch.Tensor | None = None\n scale_flat: torch.Tensor | None = None\n\n # Direct micro planes (allocated only when the shape can take that path).\n dm_barrier_count: torch.Tensor | None = None\n dm_barrier_epoch: torch.Tensor | None = None\n dm_intermediate: torch.Tensor | None = None\n dm_input_gs: torch.Tensor | None = None\n dm_down_input_scale: torch.Tensor | None = None\n\n\ndef _direct_micro_candidate(k: int, n: int, num_topk: int, weight_E: int) -> bool:\n \"\"\"Whether any m in the tiny-decode band can run the direct micro kernel.\"\"\"\n return any(\n MoEDirectMicroKernel.is_supported(m, k, n, num_topk, weight_E)\n for m in range(1, _MICRO_MAX_TOKENS + 1)\n )\n\n\ndef allocate_sm120_static_workspace(\n *,\n state_E: int,\n weight_E: int,\n max_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation_precision: str = \"fp4\",\n) -> Sm120StaticMoEWorkspace:\n \"\"\"Allocate workspace buffers for the SM120 static MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"allocate_sm120_static_workspace only supports quant_mode='nvfp4'; \"\n \"use allocate_sm120_moe_workspace(..., quant_mode='w4a16') for W4A16.\"\n )\n\n rows_pad_k = _align_up(max_rows, 128)\n cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n _check_memref_limit(\"static packed_input\", state_E * max_rows * (k // 2))\n _check_memref_limit(\"static packed_input_scale\", state_E * rows_pad_k * cols_pad_k)\n packed_input = torch.empty(\n state_E, max_rows, k // 2, dtype=torch.uint8, device=device\n )\n\n workspace = Sm120StaticMoEWorkspace(\n state_E=state_E,\n weight_E=weight_E,\n max_rows=max_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation_precision=activation_precision,\n row_counts=torch.zeros(state_E, dtype=torch.int32, device=device),\n token_map=torch.zeros(state_E, max_rows, dtype=torch.int32, device=device),\n token_weights=torch.zeros(\n state_E, max_rows, dtype=torch.float32, device=device\n ),\n packed_input=packed_input,\n packed_input_scale=torch.empty(\n state_E, rows_pad_k, cols_pad_k, dtype=torch.uint8, device=device\n ),\n barrier_count=torch.zeros(1, dtype=torch.int32, device=device),\n barrier_epoch=torch.zeros(1, dtype=torch.int32, device=device),\n active_expert_count=torch.zeros(1, dtype=torch.int32, device=device),\n weight_expert_ids=torch.arange(state_E, dtype=torch.int32, device=device),\n global_to_local_expert=torch.empty(weight_E, dtype=torch.int32, device=device),\n compact_topk_ids=torch.empty(\n max(state_E, max_rows), dtype=torch.int32, device=device\n ),\n )\n\n # Finalize views\n sf_dtype = cutlass.Float8E4M3FN\n workspace.packed_a_view = workspace.packed_input.permute(1, 2, 0).view(\n torch.float4_e2m1fn_x2\n )\n workspace.packed_a_flat = workspace.packed_input.view(-1)\n workspace.scale_flat = workspace.packed_input_scale.view(-1)\n workspace.sfa_ptr = make_ptr(\n sf_dtype,\n workspace.packed_input_scale.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n\n # Direct micro reads weights by global expert id, so its planes are only\n # useful without EP remapping.\n if state_E == weight_E and _direct_micro_candidate(k, n, num_topk, weight_E):\n dm_rows = min(max_rows, _MICRO_MAX_TOKENS * num_topk)\n # The epoch-based barriers restore their slots after each launch, so\n # the zeroed allocation is the only reset needed (graph-replay safe).\n dm_slots = dm_rows + _MICRO_MAX_TOKENS * 16\n fc2_n_chunks = (n // 2 + 127) // 128\n # The fused kernel binds the intermediate as m * num_topk *\n # fc2_n_chunks * 128 u32 words; size for the largest supported m.\n dm_inter = _MICRO_MAX_TOKENS * num_topk * fc2_n_chunks * 128\n workspace.dm_barrier_count = torch.zeros(\n dm_slots, dtype=torch.int32, device=device\n )\n workspace.dm_barrier_epoch = torch.zeros(\n dm_slots, dtype=torch.int32, device=device\n )\n workspace.dm_intermediate = torch.empty(\n dm_inter, dtype=torch.float32, device=device\n )\n workspace.dm_input_gs = torch.empty(\n weight_E, dtype=torch.float32, device=device\n )\n workspace.dm_down_input_scale = torch.empty(\n weight_E, dtype=torch.float32, device=device\n )\n return workspace\n\n\n# ---------------------------------------------------------------------------\n# Weight views\n# ---------------------------------------------------------------------------\n@dataclass\nclass _WeightViews:\n w13_fp4: object = None\n down_fp4: object = None\n sfb_w13_ptr: object = None\n sfb_down_ptr: object = None\n w1_alpha: torch.Tensor | None = None\n w2_alpha: torch.Tensor | None = None\n w1_storage: torch.Tensor | None = None\n w1_scale_storage: torch.Tensor | None = None\n w2_storage: torch.Tensor | None = None\n w2_scale_storage: torch.Tensor | None = None\n _w13_sf_storage: torch.Tensor | None = None\n _down_sf_storage: torch.Tensor | None = None\n\n\ndef _register_cache_eviction(cache: Dict, key: Tuple, *source_tensors) -> None:\n \"\"\"Evict ``key`` when a source weight tensor is collected, so the cache\n follows the weights' lifetime instead of growing for the whole process.\n \"\"\"\n for tensor in source_tensors:\n if tensor is not None:\n weakref.finalize(tensor, cache.pop, key, None)\n\n\n_WEIGHT_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_weight_views(\n w1_fp4: torch.Tensor,\n w1_blockscale: torch.Tensor,\n w2_fp4: torch.Tensor,\n w2_blockscale: torch.Tensor,\n w1_alphas: torch.Tensor,\n w2_alphas: torch.Tensor,\n n: int,\n k: int,\n activation_precision: str = \"fp4\",\n) -> _WeightViews:\n \"\"\"Create permuted weight views for the static kernel.\n\n The kernel expects concatenated w13 data with shape [2*n, k//2, E]\n via a single TMA descriptor.\n \"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n tile_n = _level_tile_n(activation_precision)\n # The kernel splits w13 into gate/up halves by tile index. This only works\n # when the boundary between halves lands on a tile-aligned column.\n if n % tile_n != 0:\n raise ValueError(\n f\"intermediate_size ({n}) must be a multiple of {tile_n} \"\n f\"for the SM120 MoE kernel's gate/up tile split.\"\n )\n\n key = (\n activation_precision,\n w1_fp4.data_ptr(),\n w1_blockscale.data_ptr(),\n w1_alphas.data_ptr(),\n w2_fp4.data_ptr(),\n w2_blockscale.data_ptr(),\n w2_alphas.data_ptr(),\n )\n cached = _WEIGHT_CACHE.get(key)\n if cached is None:\n # Cache the fresh buffers (scale factors + fp32 alphas).\n w1_rows = w1_fp4.shape[1] # 2*n for gated, n for non-gated\n cached = (\n convert_sf_from_mma_layout(\n w1_blockscale, m=w1_rows, k=k, num_groups=w1_fp4.shape[0]\n ).contiguous(),\n convert_sf_from_mma_layout(\n w2_blockscale, m=k, k=n, num_groups=w2_fp4.shape[0]\n ).contiguous(),\n w1_alphas.contiguous().to(torch.float32),\n w2_alphas.contiguous().to(torch.float32),\n )\n _WEIGHT_CACHE[key] = cached\n _register_cache_eviction(\n _WEIGHT_CACHE,\n key,\n w1_fp4,\n w1_blockscale,\n w1_alphas,\n w2_fp4,\n w2_blockscale,\n w2_alphas,\n )\n w13_sf_contiguous, down_sf_contiguous, w1_alpha, w2_alpha = cached\n\n # Permute [E, w1_rows, k//2] -> [w1_rows, k//2, E] (view, no copy).\n sf_dtype = cutlass.Float8E4M3FN\n w13 = w1_fp4.permute(1, 2, 0)\n down = w2_fp4.permute(1, 2, 0)\n return _WeightViews(\n w13_fp4=w13.view(torch.float4_e2m1fn_x2),\n down_fp4=down.view(torch.float4_e2m1fn_x2),\n sfb_w13_ptr=make_ptr(\n sf_dtype,\n w13_sf_contiguous.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n ),\n sfb_down_ptr=make_ptr(\n sf_dtype,\n down_sf_contiguous.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n ),\n w1_alpha=w1_alpha,\n w2_alpha=w2_alpha,\n w1_storage=w1_fp4,\n w1_scale_storage=w13_sf_contiguous,\n w2_storage=w2_fp4,\n w2_scale_storage=down_sf_contiguous,\n _w13_sf_storage=w13_sf_contiguous,\n _down_sf_storage=down_sf_contiguous,\n )\n\n\n# ---------------------------------------------------------------------------\n# Kernel compilation cache\n# ---------------------------------------------------------------------------\n_STATIC_KERNEL_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_static_kernel(\n state_E: int,\n weight_E: int,\n m: int,\n k: int,\n n: int,\n num_topk: int,\n max_rows: int,\n *,\n topk_ids_dtype: torch.dtype = torch.int32,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n mac_override: int | None = None,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n):\n \"\"\"Compile (or retrieve cached) the SM120 static MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 static compiler\"\n )\n sf_vec_size = 16\n sm_count = get_num_sm(torch.device(\"cuda\"))\n mac = (\n mac_override\n if mac_override is not None\n else min(get_max_active_clusters(1), sm_count)\n )\n\n # Select tile size based on actual routed rows\n routed_rows = m * num_topk\n mma_tiler_mn = (128, 128)\n if activation_precision == \"fp4\" and num_topk > 1:\n mma_tiler_mn = _select_moe_mma_tiler_mn(routed_rows, n, resident_clusters=mac)\n\n cache_key = (\n \"static\",\n activation_precision,\n state_E,\n weight_E,\n m,\n k,\n n,\n num_topk,\n max_rows,\n mac,\n mma_tiler_mn,\n topk_ids_dtype,\n input_scales_are_reciprocal,\n fast_math,\n activation,\n swiglu_alpha,\n swiglu_beta,\n swiglu_limit,\n )\n cached = _STATIC_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n return cached\n\n ab_dtype = cutlass.Float4E2M1FN\n weight_dtype = cutlass.Float4E2M1FN\n sf_dtype = cutlass.Float8E4M3FN\n a_dtype = cutlass.BFloat16\n alpha_dtype = cutlass.Float32\n\n output_tile_count_n = max(1, (n + mma_tiler_mn[1] - 1) // mma_tiler_mn[1])\n kernel: Any = MoEStaticKernel(\n sf_vec_size=sf_vec_size,\n mma_tiler_mn=mma_tiler_mn,\n output_tile_count_n=output_tile_count_n,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n )\n\n is_gated = is_gated_activation(activation)\n w1_rows = (2 if is_gated else 1) * n # 2*n for gated, n for non-gated\n\n rows_pad_k = _align_up(max_rows, 128)\n cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n\n # Build fake tensors for compilation\n a_input_fake = cute.runtime.make_fake_compact_tensor(\n a_dtype,\n (m, k),\n stride_order=(1, 0),\n assumed_align=16,\n )\n topk_ids_cutlass_dtype = (\n cutlass.Int32 if topk_ids_dtype == torch.int32 else cutlass.Int64\n )\n topk_ids_align = 4 if topk_ids_dtype == torch.int32 else 8\n topk_ids_fake = cute.runtime.make_fake_compact_tensor(\n topk_ids_cutlass_dtype,\n (m * num_topk,),\n assumed_align=topk_ids_align,\n )\n topk_weights_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32,\n (m * num_topk,),\n assumed_align=4,\n )\n packed_a_fake = cute.runtime.make_fake_compact_tensor(\n ab_dtype,\n (max_rows, k, state_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfa_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n packed_a_storage_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (state_E * max_rows * (k // 2),),\n assumed_align=16,\n )\n scale_storage_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (state_E * rows_pad_k * cols_pad_k,),\n assumed_align=16,\n )\n barrier_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n barrier_epoch_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n b_w13_fake = cute.runtime.make_fake_compact_tensor(\n weight_dtype,\n (w1_rows, k, weight_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_w13_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n b_down_fake = cute.runtime.make_fake_compact_tensor(\n weight_dtype,\n (k, n, weight_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_down_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n row_counts_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E,),\n assumed_align=4,\n )\n active_expert_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n weight_expert_ids_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E,),\n assumed_align=4,\n )\n global_to_local_expert_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (weight_E,),\n assumed_align=4,\n )\n input_gs_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n down_alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n global_scale_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n scatter_fake = cute.runtime.make_fake_compact_tensor(\n a_dtype,\n (m, k),\n stride_order=(1, 0),\n assumed_align=16,\n )\n token_map_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E, max_rows),\n stride_order=(1, 0),\n assumed_align=4,\n )\n token_weights_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (state_E, max_rows),\n stride_order=(1, 0),\n assumed_align=16,\n )\n compiled = cute.compile(\n kernel,\n a_input_fake,\n topk_ids_fake,\n topk_weights_fake,\n packed_a_fake,\n sfa_fake,\n packed_a_storage_fake,\n scale_storage_fake,\n barrier_count_fake,\n barrier_epoch_fake,\n b_w13_fake,\n sfb_w13_fake,\n b_down_fake,\n sfb_down_fake,\n row_counts_fake,\n active_expert_count_fake,\n weight_expert_ids_fake,\n global_to_local_expert_fake,\n input_gs_fake,\n alpha_fake,\n down_alpha_fake,\n global_scale_fake,\n scatter_fake,\n token_map_fake,\n token_weights_fake,\n mac,\n current_cuda_stream(),\n options=\"--opt-level 2 --enable-tvm-ffi\",\n )\n\n result = (compiled, mac)\n _STATIC_KERNEL_CACHE[cache_key] = result\n return result\n\n\n_MICRO_KERNEL_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_micro_kernel(\n state_E: int,\n weight_E: int,\n m: int,\n k: int,\n n: int,\n num_topk: int,\n max_rows: int,\n *,\n topk_ids_dtype: torch.dtype = torch.int32,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n share_input_across_experts: bool = False,\n share_expert_scales: bool = False,\n single_token: bool = False,\n mac_override: int | None = None,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n):\n \"\"\"Compile (or retrieve cached) the SM120 micro MoE kernel.\"\"\"\n sf_vec_size = 16\n sm_count = get_num_sm(torch.device(\"cuda\"))\n mac = (\n mac_override\n if mac_override is not None\n else min(get_max_active_clusters(1), sm_count)\n )\n\n # Micro always selects tile from routed rows (not just for multi-topk)\n routed_rows = m * num_topk\n mma_tiler_mn = _select_moe_mma_tiler_mn(routed_rows, n)\n\n cache_key = (\n \"micro\",\n state_E,\n weight_E,\n m,\n k,\n n,\n num_topk,\n max_rows,\n mac,\n mma_tiler_mn,\n topk_ids_dtype,\n input_scales_are_reciprocal,\n fast_math,\n share_input_across_experts,\n share_expert_scales,\n single_token,\n activation,\n swiglu_alpha,\n swiglu_beta,\n swiglu_limit,\n )\n cached = _MICRO_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n return cached\n\n ab_dtype = cutlass.Float4E2M1FN\n sf_dtype = cutlass.Float8E4M3FN\n a_dtype = cutlass.BFloat16\n alpha_dtype = cutlass.Float32\n\n kernel = MoEMicroKernel(\n sf_vec_size=sf_vec_size,\n mma_tiler_mn=mma_tiler_mn,\n output_tile_count_n=max(1, (n + mma_tiler_mn[1] - 1) // mma_tiler_mn[1]),\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n share_input_across_experts=share_input_across_experts,\n share_expert_scales=share_expert_scales,\n single_token=single_token,\n )\n\n is_gated = is_gated_activation(activation)\n w1_rows = (2 if is_gated else 1) * n\n\n rows_pad_k = _align_up(max_rows, 128)\n cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n\n # Build fake tensors for compilation (identical to static kernel)\n a_input_fake = cute.runtime.make_fake_compact_tensor(\n a_dtype,\n (m, k),\n stride_order=(1, 0),\n assumed_align=16,\n )\n topk_ids_cutlass_dtype = (\n cutlass.Int32 if topk_ids_dtype == torch.int32 else cutlass.Int64\n )\n topk_ids_align = 4 if topk_ids_dtype == torch.int32 else 8\n topk_ids_fake = cute.runtime.make_fake_compact_tensor(\n topk_ids_cutlass_dtype,\n (m * num_topk,),\n assumed_align=topk_ids_align,\n )\n topk_weights_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32,\n (m * num_topk,),\n assumed_align=4,\n )\n packed_a_fake = cute.runtime.make_fake_compact_tensor(\n ab_dtype,\n (max_rows, k, state_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfa_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n packed_a_storage_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (state_E * max_rows * (k // 2),),\n assumed_align=16,\n )\n scale_storage_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (state_E * rows_pad_k * cols_pad_k,),\n assumed_align=16,\n )\n barrier_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n barrier_epoch_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n b_w13_fake = cute.runtime.make_fake_compact_tensor(\n ab_dtype,\n (w1_rows, k, weight_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_w13_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n b_down_fake = cute.runtime.make_fake_compact_tensor(\n ab_dtype,\n (k, n, weight_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_down_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n row_counts_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E,),\n assumed_align=4,\n )\n active_expert_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n weight_expert_ids_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E,),\n assumed_align=4,\n )\n global_to_local_expert_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (weight_E,),\n assumed_align=4,\n )\n input_gs_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n down_alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n global_scale_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n scatter_fake = cute.runtime.make_fake_compact_tensor(\n a_dtype,\n (m, k),\n stride_order=(1, 0),\n assumed_align=16,\n )\n token_map_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E, max_rows),\n stride_order=(1, 0),\n assumed_align=4,\n )\n token_weights_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (state_E, max_rows),\n stride_order=(1, 0),\n assumed_align=16,\n )\n compiled = cute.compile(\n kernel,\n a_input_fake,\n topk_ids_fake,\n topk_weights_fake,\n packed_a_fake,\n sfa_fake,\n packed_a_storage_fake,\n scale_storage_fake,\n barrier_count_fake,\n barrier_epoch_fake,\n b_w13_fake,\n sfb_w13_fake,\n b_down_fake,\n sfb_down_fake,\n row_counts_fake,\n active_expert_count_fake,\n weight_expert_ids_fake,\n global_to_local_expert_fake,\n input_gs_fake,\n alpha_fake,\n down_alpha_fake,\n global_scale_fake,\n scatter_fake,\n token_map_fake,\n token_weights_fake,\n mac,\n current_cuda_stream(),\n options=\"--opt-level 2 --enable-tvm-ffi\",\n )\n\n result = (compiled, mac)\n _MICRO_KERNEL_CACHE[cache_key] = result\n return result\n\n\n# The launch cache skips the per-launch build/configure; the kernel cache\n# dedupes compiles across keys that configure to the same artifact\n# (m=2..8 differ only in grid_x).\n_DIRECT_MICRO_LAUNCH_CACHE: Dict[Tuple, Tuple] = {}\n_DIRECT_MICRO_KERNEL_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_direct_micro_kernel(\n weight_E: int,\n m: int,\n k: int,\n n: int,\n num_topk: int,\n *,\n topk_ids_dtype: torch.dtype = torch.int32,\n fast_math: bool = True,\n share_input_across_experts: bool = False,\n share_expert_scales: bool = False,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n device: torch.device | None = None,\n):\n \"\"\"Compile (or retrieve cached) the SM120 direct micro MoE kernel.\n\n Returns (compiled, grid_x, accepts_block_dim).\n \"\"\"\n if activation != SWIGLUOAI_UNINTERLEAVE:\n # The kernel constructor only accepts configurable swiglu parameters\n # for swigluoai; other activations use its normalized defaults\n # (accept-and-ignore, matching the MMA kernels).\n swiglu_alpha = None\n swiglu_beta = None\n swiglu_limit = None\n launch_key = (\n weight_E,\n m,\n k,\n n,\n num_topk,\n topk_ids_dtype,\n fast_math,\n share_input_across_experts,\n share_expert_scales,\n activation,\n swiglu_alpha,\n swiglu_beta,\n swiglu_limit,\n str(_canonical_cuda_device(device)) if device is not None else None,\n )\n cached = _DIRECT_MICRO_LAUNCH_CACHE.get(launch_key)\n if cached is not None:\n return cached\n kernel = build_direct_micro_kernel(\n weight_E,\n m,\n k,\n n,\n num_topk,\n activation=activation,\n fast_math=fast_math,\n share_input_across_experts=share_input_across_experts,\n share_expert_scales=share_expert_scales,\n single_token=m == 1,\n swiglu_limit=swiglu_limit,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n device=device,\n )\n compile_key = (\"direct_micro\", kernel.__cache_key__, topk_ids_dtype)\n entry = _DIRECT_MICRO_KERNEL_CACHE.get(compile_key)\n if entry is None:\n compiled = compile_direct_micro_kernel(kernel, topk_ids_dtype=topk_ids_dtype)\n # Register pressure can cap the launchable CTA below the fused body's\n # 512 threads; probe once per compiled kernel.\n accepts = compiled_direct_micro_accepts_block_dim(\n compiled, kernel.launch_block_dim\n )\n entry = (compiled, accepts)\n _DIRECT_MICRO_KERNEL_CACHE[compile_key] = entry\n compiled, accepts = entry\n cached = (compiled, kernel.grid_x, accepts)\n _DIRECT_MICRO_LAUNCH_CACHE[launch_key] = cached\n return cached\n\n\n# ---------------------------------------------------------------------------\n# Launch\n# ---------------------------------------------------------------------------\ndef _expand_to_experts(t: torch.Tensor, num_experts: int) -> torch.Tensor:\n \"\"\"Broadcast a scalar or [1] tensor to [num_experts], always fp32.\n\n Both branches must cast: the kernels are compiled against fp32 fake\n tensors for every per-expert scale.\n \"\"\"\n if t.numel() == 1:\n return t.to(torch.float32).expand(num_experts).contiguous()\n return t.contiguous().to(torch.float32)\n\n\ndef launch_sm120_static_moe(\n *,\n workspace: Sm120StaticMoEWorkspace,\n weights: _WeightViews,\n a: torch.Tensor,\n topk_ids: torch.Tensor,\n topk_weights: torch.Tensor,\n input_gs: torch.Tensor,\n down_input_scale: torch.Tensor,\n scatter_output: torch.Tensor,\n num_experts: int,\n num_tokens: int,\n k: int,\n n: int,\n top_k: int,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n) -> torch.Tensor:\n \"\"\"Launch the SM120 static, micro, or direct micro MoE kernel.\n\n The direct micro kernel takes tiny decode batches (m <= 8, routed_rows\n < 64) when it supports the shape, the MMA micro kernel takes the rest of\n its band (routed_rows <= 20-40), and the static kernel takes the rest.\n The MMA micro path runs a Triton pre-pass to compact routing IDs before\n launching; direct micro routes on global expert ids directly.\n \"\"\"\n _check_memref_limit(\"scatter_output\", scatter_output.numel())\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 static launcher\"\n )\n\n # Flatten routing tensors\n flat_ids = topk_ids.view(-1).to(torch.int32)\n flat_weights = topk_weights.view(-1).to(torch.float32)\n routed_rows = num_tokens * top_k\n\n # Capture whether input_gs was a single shared scalar BEFORE expansion:\n # the m=1 relu2 shared-input micro optimization only applies when every\n # expert sees the same FC1-input global scale.\n input_gs_is_shared = input_gs.numel() == 1\n down_input_scale_is_shared = down_input_scale.numel() == 1\n\n # Broadcast scalar scales to per-expert [E] tensors\n input_gs = _expand_to_experts(input_gs, num_experts)\n down_input_scale = _expand_to_experts(down_input_scale, num_experts)\n\n # Shared-scale flags let compact W4A4 micro match the ReLU2 single-token\n # specialization.\n share_input_across_experts = (\n activation == \"relu2\"\n and num_tokens == 1\n and input_gs_is_shared\n and _MICRO_SHARE_INPUT_ACROSS_EXPERTS\n )\n share_expert_scales = (\n activation == \"relu2\" and input_gs_is_shared and down_input_scale_is_shared\n )\n\n # Direct micro takes its band before the MMA micro decision. It reads\n # weights by global expert id, so EP shapes keep the compact path.\n use_direct_micro = (\n activation_precision == \"fp4\"\n and workspace.state_E == num_experts\n and workspace.dm_barrier_count is not None\n and workspace.dm_barrier_count.numel() >= routed_rows + num_tokens * 16\n and num_tokens <= _MICRO_MAX_TOKENS\n and routed_rows < _DIRECT_MICRO_CUTOVER_PAIRS\n and n <= _DIRECT_MICRO_MAX_N\n and MoEDirectMicroKernel.is_supported(num_tokens, k, n, top_k, num_experts)\n )\n if _FORCED_BACKEND is not None:\n if _FORCED_BACKEND == \"direct_micro\":\n if workspace.dm_barrier_count is None or not (\n MoEDirectMicroKernel.is_supported(num_tokens, k, n, top_k, num_experts)\n ):\n raise ValueError(\n \"forced direct_micro backend cannot run this shape \"\n f\"(m={num_tokens}, k={k}, n={n}, top_k={top_k})\"\n )\n if workspace.dm_barrier_count.numel() < routed_rows + num_tokens * 16:\n raise ValueError(\n \"forced direct_micro backend exceeds the workspace barrier \"\n f\"capacity ({workspace.dm_barrier_count.numel()} slots < \"\n f\"{routed_rows} routed rows + {num_tokens * 16})\"\n )\n use_direct_micro = True\n else:\n use_direct_micro = False\n if use_direct_micro:\n compiled, grid_x, block_ok = _get_direct_micro_kernel(\n num_experts,\n num_tokens,\n k,\n n,\n top_k,\n topk_ids_dtype=flat_ids.dtype,\n fast_math=fast_math,\n share_input_across_experts=share_input_across_experts,\n share_expert_scales=share_expert_scales,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n device=a.device,\n )\n if not block_ok:\n if _FORCED_BACKEND == \"direct_micro\":\n raise RuntimeError(\"compiled direct micro MoE kernel cannot launch\")\n use_direct_micro = False\n if use_direct_micro:\n # The kernel takes multiplier-form scales only; invert reciprocal\n # inputs into the persistent workspace planes (zeros stay zero,\n # matching the MMA kernels).\n if input_scales_are_reciprocal:\n workspace.dm_input_gs.copy_(\n torch.where(input_gs != 0, 1.0 / input_gs, input_gs)\n )\n workspace.dm_down_input_scale.copy_(\n torch.where(\n down_input_scale != 0, 1.0 / down_input_scale, down_input_scale\n )\n )\n launch_gs = workspace.dm_input_gs\n launch_down = workspace.dm_down_input_scale\n else:\n launch_gs = input_gs\n launch_down = down_input_scale\n MoEDirectMicroKernel.launch(\n compiled,\n x=a,\n w1_fp4=weights.w1_storage,\n w1_blockscale=weights.w1_scale_storage,\n w1_alphas=weights.w1_alpha,\n a1_gscale=launch_gs,\n a2_gscale=launch_down,\n inter_fp32=workspace.dm_intermediate,\n w2_fp4=weights.w2_storage,\n w2_blockscale=weights.w2_scale_storage,\n w2_alphas=weights.w2_alpha,\n topk_ids=flat_ids,\n topk_weights=flat_weights,\n out=scatter_output,\n barrier_count=workspace.dm_barrier_count,\n barrier_epoch=workspace.dm_barrier_epoch,\n m=num_tokens,\n grid_x=grid_x,\n )\n return scatter_output\n\n # Decide micro vs static\n micro_cutover = _MICRO_COMPACT_CUTOVER_PAIRS\n if top_k > 1:\n micro_cutover = _MICRO_COMPACT_CUTOVER_PAIRS_MULTI_TOPK\n use_micro = (\n activation_precision == \"fp4\"\n and num_tokens <= _MICRO_MAX_TOKENS\n and routed_rows <= micro_cutover\n )\n if _FORCED_BACKEND is not None:\n if _FORCED_BACKEND == \"micro\":\n # Forced mode raises on correctness violations, never falls back.\n if num_tokens > _MICRO_MAX_TOKENS:\n raise ValueError(\n f\"forced micro backend supports at most {_MICRO_MAX_TOKENS} \"\n f\"tokens (got {num_tokens})\"\n )\n if flat_ids.numel() > workspace.compact_topk_ids.numel():\n raise ValueError(\n \"forced micro backend exceeds the workspace compact-id \"\n f\"capacity ({workspace.compact_topk_ids.numel()} < \"\n f\"{flat_ids.numel()})\"\n )\n use_micro = True\n else:\n use_micro = False\n\n sm_count = get_num_sm(torch.device(\"cuda\"))\n base_mac = min(get_max_active_clusters(1), sm_count)\n tuned_static_mac = _lookup_mac_ladder(_STATIC_MAC_LADDER, routed_rows)\n static_mac = min(tuned_static_mac or base_mac, base_mac)\n if activation_precision == \"fp4\" and not use_micro and routed_rows < 40:\n static_mac = min(static_mac, 64)\n\n if use_micro:\n assert flat_ids.numel() <= workspace.compact_topk_ids.numel(), (\n f\"compact_topk_ids buffer too small: \"\n f\"{workspace.compact_topk_ids.numel()} < {flat_ids.numel()}\"\n )\n # Single-token ReLU2 is non-gated, so the micro kernel can launch on\n # the routed expert ids directly. Gated SiLU still goes through the\n # compact id buffer so the kernel can map compact launch ids back to\n # the physical gate/up weight experts.\n if num_tokens == 1 and activation == \"relu2\":\n launch_ids = flat_ids\n elif num_tokens == 1:\n compact_ids = workspace.compact_topk_ids[: flat_ids.numel()]\n compact_ids.copy_(\n torch.arange(\n flat_ids.numel(),\n device=flat_ids.device,\n dtype=torch.int32,\n )\n )\n workspace.weight_expert_ids[: flat_ids.numel()].copy_(\n flat_ids.to(torch.int32)\n )\n workspace.active_expert_count.fill_(flat_ids.numel())\n launch_ids = compact_ids\n else:\n compact_ids = workspace.compact_topk_ids[: flat_ids.numel()]\n from .triton_compact import compact_topk_ids as _triton_compact_topk_ids\n\n _triton_compact_topk_ids(\n flat_ids,\n compact_ids,\n workspace.weight_expert_ids,\n workspace.active_expert_count,\n )\n launch_ids = compact_ids\n # Select micro MAC: min of tuned ladder, work tiles, and hardware limit.\n micro_work_tiles = max(1, routed_rows * max(1, (n + 128 - 1) // 128))\n tuned_mac = _lookup_mac_ladder(_MICRO_MAC_LADDER, routed_rows)\n micro_mac = min(tuned_mac or base_mac, micro_work_tiles, base_mac)\n compiled, mac = _get_micro_kernel(\n workspace.state_E,\n num_experts,\n num_tokens,\n k,\n n,\n top_k,\n workspace.max_rows,\n topk_ids_dtype=launch_ids.dtype,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n share_input_across_experts=share_input_across_experts,\n share_expert_scales=share_expert_scales,\n single_token=num_tokens == 1,\n mac_override=micro_mac,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n )\n else:\n compiled, mac = _get_static_kernel(\n workspace.state_E,\n num_experts,\n num_tokens,\n k,\n n,\n top_k,\n workspace.max_rows,\n topk_ids_dtype=torch.int32,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n mac_override=static_mac,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n activation_precision=activation_precision,\n )\n launch_ids = flat_ids\n\n # Pointer arguments must be passed as raw ints (data_ptr()) at runtime.\n runtime_args: Tuple[Any, ...] = (\n a,\n launch_ids,\n flat_weights,\n workspace.packed_a_view,\n workspace.packed_input_scale.data_ptr(),\n workspace.packed_a_flat,\n workspace.scale_flat,\n workspace.barrier_count,\n workspace.barrier_epoch,\n weights.w13_fp4,\n weights._w13_sf_storage.data_ptr(),\n weights.down_fp4,\n weights._down_sf_storage.data_ptr(),\n workspace.row_counts,\n workspace.active_expert_count,\n workspace.weight_expert_ids,\n workspace.global_to_local_expert,\n input_gs,\n weights.w1_alpha,\n weights.w2_alpha,\n down_input_scale,\n scatter_output,\n workspace.token_map,\n workspace.token_weights,\n )\n compiled(*runtime_args, current_cuda_stream())\n\n return scatter_output\n\n\n# ==========================================================================\n# Dynamic backend\n# ==========================================================================\n\n\ndef select_sm120_moe_backend(\n *,\n num_tokens: int,\n num_topk: int,\n activation_precision: str = \"fp4\",\n quant_mode: str | None = None,\n) -> str:\n \"\"\"Pick static or dynamic backend based on routed-pair count.\"\"\"\n mode = _normalize_quant_mode(quant_mode, activation_precision)\n if mode == \"w4a16\":\n return \"w4a16\"\n if _FORCED_BACKEND == \"dynamic\":\n return \"dynamic\"\n if _FORCED_BACKEND in (\"static\", \"micro\", \"direct_micro\"):\n # Both micro variants launch through the static workspace path.\n return \"static\"\n routed_rows = num_tokens * num_topk\n if routed_rows <= _get_static_compact_cutover_pairs(\"fp4\"):\n return \"static\"\n return \"dynamic\"\n\n\n# ---------------------------------------------------------------------------\n# Dynamic workspace\n# ---------------------------------------------------------------------------\n@dataclass(kw_only=True)\nclass Sm120DynamicMoEWorkspace:\n \"\"\"Scratch buffers for one SM120 dynamic MoE launch.\"\"\"\n\n state_E: int\n weight_E: int\n max_rows: int\n k: int\n n: int\n num_topk: int\n device: torch.device\n activation_precision: str\n\n # Core buffers\n row_counts: torch.Tensor\n token_map: torch.Tensor\n token_weights: torch.Tensor\n packed_input: torch.Tensor\n packed_input_scale: torch.Tensor\n barrier_count: torch.Tensor\n barrier_epoch: torch.Tensor\n\n # Dynamic-specific\n routed_rows_capacity: int\n physical_tiles_capacity: int\n task_capacity: int\n # The M-tile the geometry above was sized for; launches must build the\n # kernel with the same tile.\n tile_m: int = _LEVEL_TILE_M\n expert_write_rows: torch.Tensor\n expert_tile_base: torch.Tensor\n pair_head: torch.Tensor\n task_head: torch.Tensor\n task_tail: torch.Tensor\n task_expert: torch.Tensor\n task_valid_rows: torch.Tensor\n\n # Views\n packed_a_view: torch.Tensor | None = None\n sfa_ptr: object = None\n packed_a_flat: torch.Tensor | None = None\n scale_flat: torch.Tensor | None = None\n\n\ndef _dynamic_task_geometry(\n state_E: int,\n n: int,\n routed_rows: int,\n *,\n tile_m: int = _LEVEL_TILE_M,\n tile_n: int = _LEVEL_TILE_N,\n):\n \"\"\"Compute task queue dimensions from problem geometry.\n\n Each active expert can introduce at most one additional physical tile\n beyond the base count (due to per-expert tail padding). The task queue\n holds one entry per (m_tile, slice_group) pair — NOT multiplied by E.\n \"\"\"\n routed_rows = max(1, routed_rows)\n base_m_tiles = _align_up(routed_rows, tile_m) // tile_m\n active_expert_upper_bound = min(state_E, routed_rows)\n max_m_tiles = max(1, base_m_tiles + active_expert_upper_bound - 1)\n gate_tile_cnt = max(1, (n + tile_n - 1) // tile_n)\n slice_groups = max(\n 1, (gate_tile_cnt + _DYNAMIC_SLICE_CHUNK - 1) // _DYNAMIC_SLICE_CHUNK\n )\n max_tasks = max_m_tiles * slice_groups\n return max_m_tiles, gate_tile_cnt, max_tasks\n\n\ndef allocate_sm120_dynamic_workspace(\n *,\n state_E: int,\n weight_E: int,\n routed_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation_precision: str = \"fp4\",\n activation: str = \"silu\",\n) -> Sm120DynamicMoEWorkspace:\n \"\"\"Allocate workspace buffers for the SM120 dynamic MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"allocate_sm120_dynamic_workspace only supports quant_mode='nvfp4'; \"\n \"use allocate_sm120_moe_workspace(..., quant_mode='w4a16') for W4A16.\"\n )\n tile_m = _select_dynamic_tile_m(routed_rows, state_E, activation)\n physical_tiles, _, max_tasks = _dynamic_task_geometry(\n state_E,\n n,\n routed_rows,\n tile_m=tile_m,\n tile_n=_level_tile_n(activation_precision),\n )\n rows_padded = physical_tiles * tile_m\n # The kernel addresses activation scales in 128-row SF atoms regardless of\n # tile_m, so the scale plane must cover the last partial atom.\n scale_rows = _align_up(rows_padded, 128)\n cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n _check_memref_limit(\"dynamic packed_input\", rows_padded * (k // 2))\n _check_memref_limit(\"dynamic packed_input_scale\", scale_rows * cols_pad_k)\n packed_input = torch.empty(1, rows_padded, k // 2, dtype=torch.uint8, device=device)\n\n workspace = Sm120DynamicMoEWorkspace(\n state_E=state_E,\n weight_E=weight_E,\n max_rows=rows_padded,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation_precision=activation_precision,\n routed_rows_capacity=routed_rows,\n physical_tiles_capacity=physical_tiles,\n task_capacity=max_tasks,\n tile_m=tile_m,\n row_counts=torch.zeros(state_E, dtype=torch.int32, device=device),\n token_map=torch.zeros(rows_padded, dtype=torch.int32, device=device),\n token_weights=torch.zeros(rows_padded, dtype=torch.float32, device=device),\n packed_input=packed_input,\n packed_input_scale=torch.empty(\n scale_rows, cols_pad_k, dtype=torch.uint8, device=device\n ),\n barrier_count=torch.zeros(1, dtype=torch.int32, device=device),\n barrier_epoch=torch.zeros(1, dtype=torch.int32, device=device),\n expert_write_rows=torch.zeros(state_E, dtype=torch.int32, device=device),\n expert_tile_base=torch.zeros(state_E + 1, dtype=torch.int32, device=device),\n pair_head=torch.zeros(1, dtype=torch.int32, device=device),\n task_head=torch.zeros(1, dtype=torch.int32, device=device),\n task_tail=torch.zeros(1, dtype=torch.int32, device=device),\n task_expert=torch.zeros(max_tasks, dtype=torch.int32, device=device),\n task_valid_rows=torch.zeros(max_tasks, dtype=torch.int32, device=device),\n )\n\n # Finalize views\n sf_dtype = cutlass.Float8E4M3FN\n workspace.packed_a_view = workspace.packed_input.permute(1, 2, 0).view(\n torch.float4_e2m1fn_x2\n )\n workspace.packed_a_flat = workspace.packed_input.view(-1)\n workspace.scale_flat = workspace.packed_input_scale.view(-1)\n workspace.sfa_ptr = make_ptr(\n sf_dtype,\n workspace.packed_input_scale.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n return workspace\n\n\n# ---------------------------------------------------------------------------\n# Dynamic kernel compilation\n# ---------------------------------------------------------------------------\n\n\nclass _DynamicMoELaunch:\n \"\"\"Thin JIT wrapper that makes num_tokens and max_rows runtime Int32.\"\"\"\n\n def __init__(self, kernel, k, num_topk, activation_precision: str = \"fp4\"):\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 dynamic launcher wrapper\"\n )\n self._kernel = kernel\n self._k = k\n self._packed_storage_cols = k // 2\n self._num_topk = num_topk\n self._cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n\n @cute.jit\n def __call__(\n self,\n a_ptr: cute.Pointer,\n topk_ids_ptr: cute.Pointer,\n topk_weights_ptr: cute.Pointer,\n packed_a_ptr: cute.Pointer,\n sfa_ptr: cute.Pointer,\n packed_a_storage_ptr: cute.Pointer,\n scale_storage_ptr: cute.Pointer,\n barrier_count: cute.Tensor,\n barrier_epoch: cute.Tensor,\n pair_head: cute.Tensor,\n task_head: cute.Tensor,\n task_tail: cute.Tensor,\n task_expert_ptr: cute.Pointer,\n task_valid_rows_ptr: cute.Pointer,\n b_w13: cute.Tensor,\n sfb_w13_ptr: cute.Pointer,\n b_down: cute.Tensor,\n sfb_down_ptr: cute.Pointer,\n row_counts: cute.Tensor,\n expert_write_rows: cute.Tensor,\n expert_tile_base: cute.Tensor,\n input_global_scale: cute.Tensor,\n alpha: cute.Tensor,\n down_alpha: cute.Tensor,\n global_scale: cute.Tensor,\n scatter_ptr: cute.Pointer,\n token_map_ptr: cute.Pointer,\n token_weights_ptr: cute.Pointer,\n num_tokens: cutlass.Int32,\n max_rows: cutlass.Int32,\n rows_padded: cutlass.Int32,\n max_tasks: cutlass.Int32,\n max_active_clusters: cutlass.Constexpr,\n stream,\n ):\n a_input = cute.make_tensor(\n a_ptr, layout=cute.make_layout((num_tokens, self._k), stride=(self._k, 1))\n )\n topk_ids = cute.make_tensor(\n topk_ids_ptr,\n layout=cute.make_layout((num_tokens * self._num_topk,), stride=(1,)),\n )\n topk_weights_t = cute.make_tensor(\n topk_weights_ptr,\n layout=cute.make_layout((num_tokens * self._num_topk,), stride=(1,)),\n )\n scatter_output = cute.make_tensor(\n scatter_ptr,\n layout=cute.make_layout((num_tokens, self._k), stride=(self._k, 1)),\n )\n packed_a = cute.make_tensor(\n packed_a_ptr,\n layout=cute.make_layout(\n (rows_padded, self._k, 1), stride=(self._k, 1, rows_padded * self._k)\n ),\n )\n packed_a_storage = cute.make_tensor(\n packed_a_storage_ptr,\n layout=cute.make_layout(\n (rows_padded * self._packed_storage_cols,), stride=(1,)\n ),\n )\n # Activation scales live in 128-row SF atoms; the plane is allocated\n # through the last partial atom even when rows_padded is not aligned.\n scale_rows = ((rows_padded + 127) // 128) * 128\n scale_storage = cute.make_tensor(\n scale_storage_ptr,\n layout=cute.make_layout((scale_rows * self._cols_pad_k,), stride=(1,)),\n )\n token_map = cute.make_tensor(\n token_map_ptr, layout=cute.make_layout((rows_padded,), stride=(1,))\n )\n token_weights_t = cute.make_tensor(\n token_weights_ptr, layout=cute.make_layout((rows_padded,), stride=(1,))\n )\n task_expert = cute.make_tensor(\n task_expert_ptr, layout=cute.make_layout((max_tasks,), stride=(1,))\n )\n task_valid_rows = cute.make_tensor(\n task_valid_rows_ptr, layout=cute.make_layout((max_tasks,), stride=(1,))\n )\n self._kernel(\n a_input,\n topk_ids,\n topk_weights_t,\n packed_a,\n sfa_ptr,\n packed_a_storage,\n scale_storage,\n barrier_count,\n barrier_epoch,\n pair_head,\n task_head,\n task_tail,\n task_expert,\n task_valid_rows,\n b_w13,\n sfb_w13_ptr,\n b_down,\n sfb_down_ptr,\n row_counts,\n expert_write_rows,\n expert_tile_base,\n input_global_scale,\n alpha,\n down_alpha,\n global_scale,\n scatter_output,\n token_map,\n token_weights_t,\n max_active_clusters=max_active_clusters,\n stream=stream,\n )\n\n\n_DYNAMIC_KERNEL_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_dynamic_kernel(\n E: int,\n m: int,\n k: int,\n n: int,\n num_topk: int,\n max_rows: int,\n *,\n topk_ids_dtype: torch.dtype = torch.int32,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n share_input_across_experts: bool = False,\n tile_m: int = _LEVEL_TILE_M,\n):\n \"\"\"Compile (or retrieve cached) the SM120 dynamic MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 dynamic compiler\"\n )\n # Both dynamic implementations reserve 32 route slots per token for the\n # shared-input fast path. Larger top-k values remain correct by using the\n # generic per-route producer instead.\n share_input_across_experts = bool(\n share_input_across_experts\n and activation_precision == \"fp4\"\n and num_topk <= _MAX_SHARED_INPUT_TOPK\n )\n sf_vec_size = 16\n sm_count = get_num_sm(torch.device(\"cuda\"))\n base_mac = min(get_max_active_clusters(1), sm_count)\n tuned_mac = _lookup_mac_ladder(_DYNAMIC_MAC_LADDER, m * num_topk)\n mac = min(tuned_mac or base_mac, base_mac)\n # tile_m comes from the workspace's shared selection so the kernel's task\n # and scale indexing matches the allocated scratch geometry.\n mma_tiler_mn = (tile_m, _level_tile_n(activation_precision))\n\n cache_key = (\n \"dynamic\",\n activation_precision,\n E,\n k,\n n,\n num_topk,\n mac,\n mma_tiler_mn,\n topk_ids_dtype,\n input_scales_are_reciprocal,\n fast_math,\n activation,\n swiglu_alpha,\n swiglu_beta,\n swiglu_limit,\n share_input_across_experts,\n )\n cached = _DYNAMIC_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n return cached\n\n is_gated = is_gated_activation(activation)\n w1_rows = (2 if is_gated else 1) * n\n\n scratch_dtype = cutlass.Float4E2M1FN\n weight_dtype = cutlass.Float4E2M1FN\n sf_dtype = cutlass.Float8E4M3FN\n a_dtype = cutlass.BFloat16\n alpha_dtype = cutlass.Float32\n\n kernel: Any = MoEDynamicKernel(\n sf_vec_size=sf_vec_size,\n mma_tiler_mn=mma_tiler_mn,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n share_input_across_experts=share_input_across_experts,\n hidden_size=k,\n intermediate_size=n,\n num_topk=num_topk,\n )\n launch = _DynamicMoELaunch(\n kernel,\n k=k,\n num_topk=num_topk,\n activation_precision=activation_precision,\n )\n\n topk_ids_cutlass_dtype = (\n cutlass.Int32 if topk_ids_dtype == torch.int32 else cutlass.Int64\n )\n topk_ids_align = 4 if topk_ids_dtype == torch.int32 else 8\n\n # Runtime-shaped tensors passed as pointers\n a_input_fake = make_ptr(a_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n topk_ids_fake = make_ptr(\n topk_ids_cutlass_dtype,\n topk_ids_align,\n cute.AddressSpace.gmem,\n assumed_align=topk_ids_align,\n )\n topk_weights_fake = make_ptr(\n cutlass.Float32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n packed_a_fake = make_ptr(\n scratch_dtype, 16, cute.AddressSpace.gmem, assumed_align=16\n )\n sfa_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n packed_a_storage_fake = make_ptr(\n cutlass.Uint8, 16, cute.AddressSpace.gmem, assumed_align=16\n )\n scale_storage_fake = make_ptr(\n cutlass.Uint8, 16, cute.AddressSpace.gmem, assumed_align=16\n )\n\n barrier_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n barrier_epoch_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n pair_head_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n task_head_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n task_tail_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n\n task_expert_fake = make_ptr(\n cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n task_valid_rows_fake = make_ptr(\n cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n\n b_w13_fake = cute.runtime.make_fake_compact_tensor(\n weight_dtype,\n (w1_rows, k, E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_w13_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n b_down_fake = cute.runtime.make_fake_compact_tensor(\n weight_dtype,\n (k, n, E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_down_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n row_counts_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (E,), assumed_align=4\n )\n expert_write_rows_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (E,), assumed_align=4\n )\n expert_tile_base_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (E + 1,), assumed_align=4\n )\n input_gs_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype, (E,), assumed_align=16\n )\n alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype, (E,), assumed_align=16\n )\n down_alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype, (E,), assumed_align=16\n )\n global_scale_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype, (E,), assumed_align=16\n )\n scatter_fake = make_ptr(a_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n token_map_fake = make_ptr(cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4)\n token_weights_fake = make_ptr(\n alpha_dtype, 16, cute.AddressSpace.gmem, assumed_align=16\n )\n\n compiled = cute.compile(\n launch,\n a_input_fake,\n topk_ids_fake,\n topk_weights_fake,\n packed_a_fake,\n sfa_fake,\n packed_a_storage_fake,\n scale_storage_fake,\n barrier_count_fake,\n barrier_epoch_fake,\n pair_head_fake,\n task_head_fake,\n task_tail_fake,\n task_expert_fake,\n task_valid_rows_fake,\n b_w13_fake,\n sfb_w13_fake,\n b_down_fake,\n sfb_down_fake,\n row_counts_fake,\n expert_write_rows_fake,\n expert_tile_base_fake,\n input_gs_fake,\n alpha_fake,\n down_alpha_fake,\n global_scale_fake,\n scatter_fake,\n token_map_fake,\n token_weights_fake,\n 1,\n 1,\n 1,\n 1, # runtime Int32 placeholders\n mac,\n current_cuda_stream(),\n options=\"--opt-level 2 --enable-tvm-ffi\",\n )\n\n result = (compiled, mac)\n _DYNAMIC_KERNEL_CACHE[cache_key] = result\n return result\n\n\n# ---------------------------------------------------------------------------\n# Dynamic launch\n# ---------------------------------------------------------------------------\ndef launch_sm120_dynamic_moe(\n *,\n workspace: Sm120DynamicMoEWorkspace,\n weights: _WeightViews,\n a: torch.Tensor,\n topk_ids: torch.Tensor,\n topk_weights: torch.Tensor,\n input_gs: torch.Tensor,\n down_input_scale: torch.Tensor,\n scatter_output: torch.Tensor,\n num_experts: int,\n num_tokens: int,\n k: int,\n n: int,\n top_k: int,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n) -> torch.Tensor:\n \"\"\"Launch the SM120 dynamic MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 dynamic launcher\"\n )\n _check_memref_limit(\"scatter_output\", scatter_output.numel())\n flat_ids = topk_ids.view(-1).to(torch.int32)\n flat_weights = topk_weights.view(-1).to(torch.float32)\n input_gs_is_shared = input_gs.numel() == 1\n\n # Broadcast scalar scales to per-expert [E] tensors\n input_gs = _expand_to_experts(input_gs, num_experts)\n down_input_scale = _expand_to_experts(down_input_scale, num_experts)\n\n compiled, mac = _get_dynamic_kernel(\n num_experts,\n num_tokens,\n k,\n n,\n top_k,\n workspace.max_rows,\n topk_ids_dtype=torch.int32,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n activation_precision=activation_precision,\n share_input_across_experts=input_gs_is_shared,\n tile_m=workspace.tile_m,\n )\n\n # Dynamic kernel: runtime-shaped args are DataPointer (pass data_ptr()),\n # fixed-shape args are Tensor (pass torch tensor directly).\n runtime_args: Tuple[Any, ...] = (\n a.data_ptr(),\n flat_ids.data_ptr(),\n flat_weights.data_ptr(),\n workspace.packed_a_view.data_ptr(),\n workspace.packed_input_scale.data_ptr(),\n workspace.packed_a_flat.data_ptr(),\n workspace.scale_flat.data_ptr(),\n workspace.barrier_count,\n workspace.barrier_epoch,\n workspace.pair_head,\n workspace.task_head,\n workspace.task_tail,\n workspace.task_expert.data_ptr(),\n workspace.task_valid_rows.data_ptr(),\n weights.w13_fp4,\n weights._w13_sf_storage.data_ptr(),\n weights.down_fp4,\n weights._down_sf_storage.data_ptr(),\n workspace.row_counts,\n workspace.expert_write_rows,\n workspace.expert_tile_base,\n input_gs,\n weights.w1_alpha,\n weights.w2_alpha,\n down_input_scale,\n scatter_output.data_ptr(),\n workspace.token_map.data_ptr(),\n workspace.token_weights.data_ptr(),\n num_tokens,\n workspace.max_rows,\n workspace.physical_tiles_capacity * workspace.tile_m,\n workspace.task_capacity,\n )\n compiled(*runtime_args, current_cuda_stream())\n\n return scatter_output\n\n\n# ==========================================================================\n# W4A16 route-packing implementation\n# ==========================================================================\n@dataclass(kw_only=True)\nclass Sm120W4A16MoEWorkspace:\n \"\"\"Scratch buffers for the SM120 W4A16 MoE path.\"\"\"\n\n state_E: int\n weight_E: int\n max_rows: int\n k: int\n n: int\n num_topk: int\n device: torch.device\n activation: str\n activation_precision: str\n quant_mode: str\n routed_rows_capacity: int\n route_num_experts: int\n\n intermediate_cache13: torch.Tensor\n intermediate_cache2: torch.Tensor\n fc1_c_tmp: torch.Tensor\n fc2_c_tmp: torch.Tensor\n packed_route_indices: torch.Tensor\n block_expert_ids: torch.Tensor\n packed_route_count: torch.Tensor\n expert_offsets: torch.Tensor\n expert_map: torch.Tensor | None = None\n\n\ndef _is_cuda_graph_capturing() -> bool:\n try:\n return bool(torch.cuda.is_current_stream_capturing())\n except Exception:\n return False\n\n\ndef _canonical_cuda_device(device: torch.device) -> torch.device:\n device = torch.device(device)\n if device.type == \"cuda\" and device.index is None:\n return torch.device(\"cuda\", torch.cuda.current_device())\n return device\n\n\ndef _w4a16_workspace_geometry(\n *,\n routed_rows: int,\n route_num_experts: int,\n num_topk: int,\n k: int,\n n: int,\n is_gated: bool,\n device: torch.device,\n) -> tuple[int, int, int, int, int]:\n route_slots = 1\n route_blocks = 1\n fc1_c_tmp_elements = 1\n fc2_c_tmp_elements = 1\n fc1_cols = (2 if is_gated else 1) * int(n)\n sms = get_num_sm(device)\n # Size the route buffers for the power-of-2 capacity so route packing keeps\n # a single triton specialization across token counts.\n routed_rows_capacity = route_pack_numel_capacity(\n int(routed_rows), topk=int(num_topk)\n )\n for block_size in _W4A16_ALLOWED_ROUTED_SIZES:\n slots = max_packed_route_slots(\n routed_rows_capacity,\n int(block_size),\n int(route_num_experts),\n )\n blocks = (slots + int(block_size) - 1) // int(block_size)\n route_slots = max(route_slots, slots)\n route_blocks = max(route_blocks, blocks)\n fc1_c_tmp_elements = max(\n fc1_c_tmp_elements,\n packed_gemm_scratch_elements(\n size_n=fc1_cols,\n route_slots=slots,\n moe_block_size=int(block_size),\n sms=sms,\n ),\n )\n fc2_c_tmp_elements = max(\n fc2_c_tmp_elements,\n packed_gemm_scratch_elements(\n size_n=int(k),\n route_slots=slots,\n moe_block_size=int(block_size),\n sms=sms,\n ),\n )\n return (\n route_slots,\n route_blocks,\n fc1_c_tmp_elements,\n fc2_c_tmp_elements,\n fc1_cols,\n )\n\n\ndef _make_w4a16_expert_map(\n *,\n state_E: int,\n weight_E: int,\n device: torch.device,\n) -> torch.Tensor | None:\n if int(state_E) == int(weight_E):\n return None\n if int(state_E) > int(weight_E):\n raise ValueError(\"num_local_experts cannot exceed num_experts\")\n expert_map = torch.empty((int(weight_E),), dtype=torch.int32, device=device)\n expert_map.fill_(-1)\n expert_map[: int(state_E)].copy_(\n torch.arange(int(state_E), dtype=torch.int32, device=device)\n )\n return expert_map\n\n\ndef _allocate_sm120_w4a16_workspace(\n *,\n state_E: int,\n weight_E: int,\n routed_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation: str = \"silu\",\n) -> Sm120W4A16MoEWorkspace:\n is_gated = validate_activation(activation)\n routed_rows = max(1, int(routed_rows))\n route_num_experts = int(weight_E) if int(state_E) != int(weight_E) else int(state_E)\n (\n route_slots,\n route_blocks,\n fc1_c_tmp_elements,\n fc2_c_tmp_elements,\n fc1_cols,\n ) = _w4a16_workspace_geometry(\n routed_rows=routed_rows,\n route_num_experts=route_num_experts,\n num_topk=num_topk,\n k=k,\n n=n,\n is_gated=is_gated,\n device=device,\n )\n return Sm120W4A16MoEWorkspace(\n state_E=int(state_E),\n weight_E=int(weight_E),\n max_rows=routed_rows,\n k=int(k),\n n=int(n),\n num_topk=int(num_topk),\n device=device,\n activation=activation,\n activation_precision=\"bf16\",\n quant_mode=\"w4a16\",\n routed_rows_capacity=routed_rows,\n route_num_experts=route_num_experts,\n intermediate_cache13=torch.empty(\n (routed_rows * max(fc1_cols, int(k)),),\n dtype=torch.bfloat16,\n device=device,\n ),\n intermediate_cache2=torch.empty(\n (routed_rows, int(n)),\n dtype=torch.bfloat16,\n device=device,\n ),\n fc1_c_tmp=torch.empty(\n (fc1_c_tmp_elements,),\n dtype=torch.float32,\n device=device,\n ),\n fc2_c_tmp=torch.empty(\n (fc2_c_tmp_elements,),\n dtype=torch.float32,\n device=device,\n ),\n packed_route_indices=torch.empty(\n (route_slots,),\n dtype=torch.int32,\n device=device,\n ),\n block_expert_ids=torch.empty(\n (route_blocks,),\n dtype=torch.int32,\n device=device,\n ),\n packed_route_count=torch.empty((1,), dtype=torch.int32, device=device),\n expert_offsets=torch.empty(\n (route_num_experts + 1,),\n dtype=torch.int32,\n device=device,\n ),\n expert_map=_make_w4a16_expert_map(\n state_E=state_E,\n weight_E=weight_E,\n device=device,\n ),\n )\n\n\n_W4A16_WEIGHT_CACHE: Dict[Tuple, W4A16PackedWeights] = {}\n\n\ndef _get_w4a16_packed_weights(\n *,\n w1_weight: torch.Tensor,\n w1_weight_sf: torch.Tensor,\n w1_alpha: torch.Tensor,\n w2_weight: torch.Tensor,\n w2_weight_sf: torch.Tensor,\n w2_alpha: torch.Tensor,\n activation: str,\n params_dtype: torch.dtype,\n source_format: str = \"modelopt\",\n) -> W4A16PackedWeights:\n key = (\n activation,\n params_dtype,\n source_format,\n tuple(w1_weight.shape),\n tuple(w1_weight_sf.shape),\n tuple(w1_alpha.shape),\n tuple(w2_weight.shape),\n tuple(w2_weight_sf.shape),\n tuple(w2_alpha.shape),\n w1_weight.data_ptr(),\n w1_weight_sf.data_ptr(),\n w1_alpha.data_ptr(),\n w2_weight.data_ptr(),\n w2_weight_sf.data_ptr(),\n w2_alpha.data_ptr(),\n )\n cached = _W4A16_WEIGHT_CACHE.get(key)\n if cached is not None:\n return cached\n if _is_cuda_graph_capturing():\n raise RuntimeError(\n \"W4A16 packed weights are not initialized for CUDA graph capture; \"\n \"run once before capture so the prepared weights are cached.\"\n )\n prepared = prepare_w4a16_packed_weights(\n w1_weight,\n w1_weight_sf,\n w1_alpha,\n w2_weight,\n w2_weight_sf,\n w2_alpha,\n activation=activation,\n params_dtype=params_dtype,\n source_format=source_format,\n )\n _W4A16_WEIGHT_CACHE[key] = prepared\n _register_cache_eviction(\n _W4A16_WEIGHT_CACHE,\n key,\n w1_weight,\n w1_weight_sf,\n w1_alpha,\n w2_weight,\n w2_weight_sf,\n w2_alpha,\n )\n return prepared\n\n\ndef _validate_w4a16_workspace(\n workspace: Sm120W4A16MoEWorkspace,\n *,\n state_E: int,\n weight_E: int,\n routed_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation: str,\n) -> None:\n validate_activation(activation)\n if workspace.state_E != int(state_E) or workspace.weight_E != int(weight_E):\n raise ValueError(\"pre-allocated W4A16 workspace expert geometry mismatch\")\n if workspace.k != int(k) or workspace.n != int(n):\n raise ValueError(\"pre-allocated W4A16 workspace hidden geometry mismatch\")\n if workspace.num_topk != int(num_topk):\n raise ValueError(\"pre-allocated W4A16 workspace top-k mismatch\")\n if getattr(workspace, \"activation\", None) != activation:\n raise ValueError(\"pre-allocated W4A16 workspace activation mismatch\")\n if _canonical_cuda_device(workspace.device) != _canonical_cuda_device(device):\n raise ValueError(\n f\"pre-allocated W4A16 workspace is on {workspace.device}, expected {device}\"\n )\n if workspace.routed_rows_capacity < max(1, int(routed_rows)):\n raise ValueError(\n \"pre-allocated W4A16 workspace is too small for the requested \"\n f\"routed rows ({workspace.routed_rows_capacity} < {routed_rows})\"\n )\n\n\ndef _launch_sm120_w4a16_moe(\n *,\n a: torch.Tensor,\n topk_ids: torch.Tensor,\n topk_weights: torch.Tensor,\n w1_weight: torch.Tensor,\n w1_weight_sf: torch.Tensor,\n w1_alpha: torch.Tensor,\n w2_weight: torch.Tensor,\n w2_weight_sf: torch.Tensor,\n w2_alpha: torch.Tensor,\n num_experts: int,\n top_k: int,\n num_local_experts: int,\n scatter_output: torch.Tensor,\n fast_math: bool = True,\n activation: str = \"silu\",\n source_format: str = \"modelopt\",\n _workspace=None,\n _prepared_weights=None,\n) -> torch.Tensor:\n prepared = (\n _prepared_weights\n if isinstance(_prepared_weights, W4A16PackedWeights)\n else _get_w4a16_packed_weights(\n w1_weight=w1_weight,\n w1_weight_sf=w1_weight_sf,\n w1_alpha=w1_alpha,\n w2_weight=w2_weight,\n w2_weight_sf=w2_weight_sf,\n w2_alpha=w2_alpha,\n activation=activation,\n params_dtype=a.dtype,\n source_format=source_format,\n )\n )\n if int(prepared.num_experts) != int(num_local_experts):\n raise ValueError(\"num_local_experts must match w1_weight.shape[0] for W4A16.\")\n num_tokens = int(topk_ids.size(0))\n routed_rows = num_tokens * int(top_k)\n k = int(a.size(1))\n n = int(prepared.intermediate_size)\n\n if _workspace is None:\n workspace = _get_cached_workspace(\n backend=\"w4a16\",\n state_E=num_local_experts,\n weight_E=num_experts,\n routed_rows=routed_rows,\n k=k,\n n=n,\n num_topk=top_k,\n device=a.device,\n quant_mode=\"w4a16\",\n activation=activation,\n )\n else:\n workspace = _workspace\n if not isinstance(workspace, Sm120W4A16MoEWorkspace):\n raise TypeError(\"expected a W4A16 workspace for quant_mode='w4a16'\")\n _validate_w4a16_workspace(\n workspace,\n state_E=num_local_experts,\n weight_E=num_experts,\n routed_rows=routed_rows,\n k=k,\n n=n,\n num_topk=top_k,\n device=a.device,\n activation=activation,\n )\n\n return run_w4a16_moe(\n a,\n prepared,\n topk_weights,\n topk_ids,\n activation=activation,\n intermediate_cache13=workspace.intermediate_cache13,\n intermediate_cache2=workspace.intermediate_cache2,\n output=scatter_output,\n fc1_c_tmp=workspace.fc1_c_tmp,\n fc2_c_tmp=workspace.fc2_c_tmp,\n packed_route_indices=workspace.packed_route_indices,\n block_expert_ids=workspace.block_expert_ids,\n packed_route_count=workspace.packed_route_count,\n expert_offsets=workspace.expert_offsets,\n expert_map=workspace.expert_map,\n fast_math=fast_math,\n )\n\n\n# ==========================================================================\n# Workspace cache (for functional API path)\n# ==========================================================================\n\n_Sm120Workspace = Union[\n Sm120StaticMoEWorkspace,\n Sm120DynamicMoEWorkspace,\n Sm120W4A16MoEWorkspace,\n]\n\n# Stores the workspace with the largest capacity seen per key and never\n# shrinks within a process. clear_sm120_moe_caches() releases everything.\n_WORKSPACE_CACHE: Dict[Tuple, _Sm120Workspace] = {}\n\n\ndef clear_sm120_moe_caches() -> None:\n \"\"\"Release every module-level SM12x MoE cache.\n\n References held by callers are unaffected.\n \"\"\"\n _WORKSPACE_CACHE.clear()\n _WEIGHT_CACHE.clear()\n _W4A16_WEIGHT_CACHE.clear()\n _PADDED_WEIGHT_CACHE.clear()\n _STATIC_KERNEL_CACHE.clear()\n _MICRO_KERNEL_CACHE.clear()\n _DIRECT_MICRO_LAUNCH_CACHE.clear()\n _DIRECT_MICRO_KERNEL_CACHE.clear()\n _DYNAMIC_KERNEL_CACHE.clear()\n\n\ndef allocate_sm120_moe_workspace(\n *,\n state_E: int,\n weight_E: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n max_rows: int | None = None,\n routed_rows: int | None = None,\n quant_mode: str | None = None,\n activation_precision: str | None = None,\n backend: str | None = None,\n activation: str = \"silu\",\n) -> _Sm120Workspace:\n \"\"\"Allocate the right SM120 MoE workspace from a quantization mode.\"\"\"\n mode = _normalize_quant_mode(quant_mode, activation_precision)\n capacity_rows = routed_rows if routed_rows is not None else max_rows\n if capacity_rows is None:\n raise ValueError(\"routed_rows or max_rows is required\")\n capacity_rows = max(1, int(capacity_rows))\n device = torch.device(device)\n\n if mode == \"w4a16\":\n if backend not in (None, \"w4a16\"):\n raise ValueError(\"quant_mode='w4a16' does not use static/dynamic backend\")\n return _allocate_sm120_w4a16_workspace(\n state_E=state_E,\n weight_E=weight_E,\n routed_rows=capacity_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation=activation,\n )\n\n activation_precision = \"fp4\"\n if backend is None:\n backend = select_sm120_moe_backend(\n num_tokens=max(\n 1, (capacity_rows + max(1, int(num_topk)) - 1) // max(1, int(num_topk))\n ),\n num_topk=int(num_topk),\n activation_precision=activation_precision,\n )\n if backend == \"dynamic\":\n return allocate_sm120_dynamic_workspace(\n state_E=state_E,\n weight_E=weight_E,\n routed_rows=capacity_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation_precision=activation_precision,\n activation=activation,\n )\n if backend == \"static\":\n return allocate_sm120_static_workspace(\n state_E=state_E,\n weight_E=weight_E,\n max_rows=capacity_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation_precision=activation_precision,\n )\n raise ValueError(f\"unsupported SM120 MoE backend {backend!r}\")\n\n\ndef _get_cached_workspace(\n *,\n backend: str,\n state_E: int,\n weight_E: int,\n routed_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation_precision: str = \"fp4\",\n quant_mode: str | None = None,\n activation: str = \"silu\",\n) -> _Sm120Workspace:\n \"\"\"Get or allocate a cached workspace for the given problem shape.\n\n Reuses the cached workspace if it has enough capacity for the requested\n routed_rows. For static workspaces, max_rows is the direct capacity.\n For dynamic workspaces, routed_rows_capacity is used because the dynamic\n geometry (physical tiles, task queue slots) depends on the original\n routed_rows, not just max_rows.\n \"\"\"\n quant_mode = _normalize_quant_mode(quant_mode, activation_precision)\n activation_precision = _activation_precision_from_quant_mode(quant_mode)\n # Key dynamic workspaces on the tile band of this call's routed_rows; a\n # larger cached workspace must not pin small calls to its 128 tile.\n tile_m = (\n _select_dynamic_tile_m(max(1, routed_rows), state_E, activation)\n if backend == \"dynamic\" and quant_mode != \"w4a16\"\n else None\n )\n cache_key = (\n state_E,\n weight_E,\n k,\n n,\n num_topk,\n str(device),\n backend,\n quant_mode,\n activation,\n tile_m,\n )\n cached = _WORKSPACE_CACHE.get(cache_key)\n\n if cached is not None:\n if isinstance(cached, Sm120DynamicMoEWorkspace):\n if cached.routed_rows_capacity >= max(1, routed_rows):\n assert tile_m is None or cached.tile_m == tile_m\n return cached\n elif isinstance(cached, Sm120W4A16MoEWorkspace):\n if cached.routed_rows_capacity >= max(1, routed_rows):\n return cached\n else:\n if cached.max_rows >= max(1, routed_rows):\n return cached\n\n if quant_mode == \"w4a16\" and _is_cuda_graph_capturing():\n raise RuntimeError(\n \"W4A16 workspace is not initialized for CUDA graph capture; \"\n \"provide a preallocated workspace from \"\n \"allocate_sm120_moe_workspace(..., quant_mode='w4a16') or warm the \"\n \"functional path before capture.\"\n )\n workspace = allocate_sm120_moe_workspace(\n state_E=state_E,\n weight_E=weight_E,\n routed_rows=routed_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n quant_mode=quant_mode,\n activation_precision=activation_precision,\n backend=backend,\n activation=activation,\n )\n\n _WORKSPACE_CACHE[cache_key] = workspace\n return workspace\n\n\n# ==========================================================================\n# Unified dispatch\n# ==========================================================================\n_PADDED_WEIGHT_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _pad_intermediate_to_tile(\n w1_weight,\n w1_weight_sf,\n w2_weight,\n w2_weight_sf,\n fc2_input_scale,\n n,\n tile,\n h,\n num_experts,\n is_gated,\n):\n \"\"\"Zero-pad NVFP4 weights + scale factors so the intermediate size is a\n multiple of ``tile`` (gate/up tile-split requirement); padded channels are\n zero, so the result is numerically identical.\n \"\"\"\n n_pad = ((n + tile - 1) // tile) * tile\n if n_pad == n:\n return w1_weight, w1_weight_sf, w2_weight, w2_weight_sf, fc2_input_scale, n\n E = int(num_experts)\n fc2_input_scale_src = fc2_input_scale\n key = (\n n,\n tile,\n h,\n E,\n bool(is_gated),\n w1_weight.data_ptr(),\n w1_weight_sf.data_ptr(),\n w2_weight.data_ptr(),\n w2_weight_sf.data_ptr(),\n fc2_input_scale_src.data_ptr() if fc2_input_scale_src is not None else 0,\n )\n cached = _PADDED_WEIGHT_CACHE.get(key)\n if cached is not None:\n return cached\n\n def mma_to_logical(sf, m, k):\n sw = convert_sf_from_mma_layout(sf, m=m, k=k, num_groups=E)\n m_pad = ((m + 127) // 128) * 128\n sw = sw.reshape(E, m_pad, -1)\n cb = (k + SF_VEC_SIZE - 1) // SF_VEC_SIZE\n return torch.stack(\n [unswizzle_block_scale(sw[e], rows=m, cols_blocks=cb) for e in range(E)], 0\n )\n\n def logical_to_mma(log, m, k):\n sw = torch.stack([swizzle_block_scale(log[e]) for e in range(E)], 0)\n sw2d = sw.reshape(E * sw.shape[1], sw.shape[2]).to(torch.float8_e4m3fn)\n return convert_sf_to_mma_layout(sw2d, m=m, k=k, num_groups=E)\n\n def pad_dim(t, dim, old, new):\n if new == old:\n return t\n shp = list(t.shape)\n shp[dim] = new - old\n return torch.cat([t, t.new_zeros(shp)], dim=dim)\n\n if is_gated:\n # w1 packs [up(0:n), gate(n:2n)] rows; pad each half so the split stays\n # tile-aligned, then re-concat.\n up, gate = w1_weight[:, :n, :], w1_weight[:, n : 2 * n, :]\n w1p = torch.cat([pad_dim(up, 1, n, n_pad), pad_dim(gate, 1, n, n_pad)], dim=1)\n log1 = mma_to_logical(w1_weight_sf, m=2 * n, k=h)\n up_sf, gate_sf = log1[:, :n, :], log1[:, n : 2 * n, :]\n log1p = torch.cat(\n [pad_dim(up_sf, 1, n, n_pad), pad_dim(gate_sf, 1, n, n_pad)], dim=1\n )\n w1_sf_p = logical_to_mma(log1p, m=2 * n_pad, k=h)\n else:\n w1p = pad_dim(w1_weight, 1, n, n_pad)\n log1 = mma_to_logical(w1_weight_sf, m=n, k=h)\n w1_sf_p = logical_to_mma(pad_dim(log1, 1, n, n_pad), m=n_pad, k=h)\n\n # w2 reduces over the intermediate dim: pad its packed columns + SF columns.\n w2p = pad_dim(w2_weight, 2, n // 2, n_pad // 2)\n log2 = mma_to_logical(w2_weight_sf, m=h, k=n)\n cb_n = (n + SF_VEC_SIZE - 1) // SF_VEC_SIZE\n cb_np = (n_pad + SF_VEC_SIZE - 1) // SF_VEC_SIZE\n w2_sf_p = logical_to_mma(pad_dim(log2, 2, cb_n, cb_np), m=h, k=n_pad)\n\n if fc2_input_scale_src is not None and fc2_input_scale_src.numel() == n:\n fc2_input_scale = pad_dim(fc2_input_scale_src, 0, n, n_pad)\n result = (w1p, w1_sf_p, w2p, w2_sf_p, fc2_input_scale, n_pad)\n _PADDED_WEIGHT_CACHE[key] = result\n _register_cache_eviction(\n _PADDED_WEIGHT_CACHE,\n key,\n w1_weight,\n w1_weight_sf,\n w2_weight,\n w2_weight_sf,\n fc2_input_scale_src,\n )\n return result\n\n\ndef launch_sm120_moe(\n *,\n a: torch.Tensor,\n topk_ids: torch.Tensor,\n topk_weights: torch.Tensor,\n w1_weight: torch.Tensor,\n w1_weight_sf: torch.Tensor,\n w1_alpha: torch.Tensor,\n fc2_input_scale: Optional[torch.Tensor] = None,\n input_global_scale: Optional[torch.Tensor] = None,\n w2_weight: torch.Tensor,\n w2_weight_sf: torch.Tensor,\n w2_alpha: torch.Tensor,\n num_experts: int,\n top_k: int,\n num_local_experts: int,\n scatter_output: torch.Tensor,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n quant_mode: str | None = None,\n source_format: str = \"modelopt\",\n _workspace=None,\n _weight_views=None,\n _prepared_weights=None,\n) -> torch.Tensor:\n \"\"\"Unified SM120 MoE dispatch — selects static or dynamic by token count.\n\n input_global_scale overrides w1_alpha as the FC1 input-quant scale and\n is folded into the multiplier internally. With _weight_views supplied,\n w1_alpha must already contain the fold.\n\n Optional _workspace and _weight_views can be pre-allocated and reused\n across calls to avoid per-call allocation overhead (wrapper path).\n When not provided (functional API path), a module-level workspace cache\n is used to avoid re-allocating on every call.\n \"\"\"\n quant_mode = _normalize_quant_mode(quant_mode, activation_precision)\n source_format = _normalize_source_format_for_quant_mode(source_format, quant_mode)\n activation_precision = _activation_precision_from_quant_mode(quant_mode)\n\n num_tokens = topk_ids.size(0)\n k = a.size(1) # hidden_size\n is_gated = is_gated_activation(activation)\n # w1_weight.size(1) is 2*n for gated or n for non-gated\n intermediate_size = w1_weight.size(1) // 2 if is_gated else w1_weight.size(1)\n n = intermediate_size\n\n # NVFP4 kernels need padded intermediate size.\n if quant_mode != \"w4a16\" and n % _LEVEL_TILE_N != 0 and _weight_views is None:\n (\n w1_weight,\n w1_weight_sf,\n w2_weight,\n w2_weight_sf,\n fc2_input_scale,\n n,\n ) = _pad_intermediate_to_tile(\n w1_weight,\n w1_weight_sf,\n w2_weight,\n w2_weight_sf,\n fc2_input_scale,\n n,\n _LEVEL_TILE_N,\n k,\n w1_weight.size(0),\n is_gated,\n )\n\n routed_rows = num_tokens * top_k\n\n if quant_mode == \"w4a16\":\n return _launch_sm120_w4a16_moe(\n a=a,\n topk_ids=topk_ids,\n topk_weights=topk_weights,\n w1_weight=w1_weight,\n w1_weight_sf=w1_weight_sf,\n w1_alpha=w1_alpha,\n w2_weight=w2_weight,\n w2_weight_sf=w2_weight_sf,\n w2_alpha=w2_alpha,\n num_experts=num_experts,\n top_k=top_k,\n num_local_experts=num_local_experts,\n scatter_output=scatter_output,\n fast_math=fast_math,\n activation=activation,\n source_format=source_format,\n _workspace=_workspace,\n _prepared_weights=_prepared_weights,\n )\n\n if fc2_input_scale is None:\n raise ValueError(\"fc2_input_scale is required when quant_mode='nvfp4'.\")\n down_input_scale = fc2_input_scale\n if input_global_scale is not None:\n input_gs = input_global_scale\n if _weight_views is None:\n # Alpha must carry input_gs back or the output magnitude is wrong.\n # The wrapper folds before building _weight_views; don't fold twice.\n w1_alpha = (\n w1_alpha.to(torch.float32) * input_global_scale.to(torch.float32)\n ).contiguous()\n else:\n input_gs = w1_alpha\n\n weights = (\n _weight_views\n if _weight_views is not None\n else _get_weight_views(\n w1_fp4=w1_weight,\n w1_blockscale=w1_weight_sf,\n w2_fp4=w2_weight,\n w2_blockscale=w2_weight_sf,\n w1_alphas=w1_alpha,\n w2_alphas=w2_alpha,\n n=n,\n k=k,\n activation_precision=activation_precision,\n )\n )\n\n # Resolve workspace and backend selection.\n # When a pre-allocated workspace is provided (CUDA graph wrapper path),\n # infer the backend from the workspace type so they stay in sync —\n # the caller already committed to a backend at allocation time.\n if _workspace is not None:\n workspace = _workspace\n workspace_activation_precision = getattr(\n workspace, \"activation_precision\", activation_precision\n )\n if workspace_activation_precision != activation_precision:\n raise ValueError(\n \"pre-allocated workspace activation_precision does not match \"\n f\"requested activation_precision={activation_precision!r}.\"\n )\n if isinstance(workspace, Sm120DynamicMoEWorkspace):\n if num_local_experts != num_experts:\n raise ValueError(\n \"pre-allocated dynamic SM120 MoE workspace requires \"\n \"num_local_experts == num_experts because dynamic expert \"\n \"buffers are indexed by global topk ids.\"\n )\n # A pre-allocated dynamic workspace keeps its stored tile_m even\n # for smaller calls; its geometry was sized for that tile.\n backend = \"dynamic\"\n else:\n backend = \"static\"\n else:\n backend = select_sm120_moe_backend(\n num_tokens=num_tokens,\n num_topk=top_k,\n activation_precision=activation_precision,\n )\n # The dynamic kernel indexes row_counts/expert_write_rows directly with\n # topk_ids but those buffers are sized with num_local_experts. Unless\n # num_local_experts == num_experts, fall back to the static backend which\n # has global-to-local expert remapping.\n if backend == \"dynamic\" and num_local_experts != num_experts:\n backend = \"static\"\n workspace = _get_cached_workspace(\n backend=backend,\n state_E=num_local_experts,\n weight_E=num_experts,\n routed_rows=routed_rows,\n k=k,\n n=n,\n num_topk=top_k,\n device=a.device,\n activation_precision=activation_precision,\n quant_mode=quant_mode,\n activation=activation,\n )\n\n if backend == \"dynamic\":\n return launch_sm120_dynamic_moe(\n workspace=workspace,\n weights=weights,\n a=a,\n topk_ids=topk_ids,\n topk_weights=topk_weights,\n input_gs=input_gs,\n down_input_scale=down_input_scale,\n scatter_output=scatter_output,\n num_experts=num_experts,\n num_tokens=num_tokens,\n k=k,\n n=n,\n top_k=top_k,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n activation_precision=activation_precision,\n )\n else:\n return launch_sm120_static_moe(\n workspace=workspace,\n weights=weights,\n a=a,\n topk_ids=topk_ids,\n topk_weights=topk_weights,\n input_gs=input_gs,\n down_input_scale=down_input_scale,\n scatter_output=scatter_output,\n num_experts=num_experts,\n num_tokens=num_tokens,\n k=k,\n n=n,\n top_k=top_k,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n activation_precision=activation_precision,\n )\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## 📌 Description\n\nRolls the on-disk CuTe-DSL kernel cache out to the three sm12x NVFP4 fused-MoE kernels (micro,\nstatic, dynamic), addressing #4317. The infrastructure landed in #3874 / #4029; @bkryu noted in\n#4317 that it still had to reach individual kernels and that the core team lacked bandwidth, so this\napplies it to b12x MoE.\n\nFollows the rollout note in `docs/design_docs/cute_dsl_kernel_cache.md`: each `cute.compile` becomes\na closure passed to `build_and_load_cute_dsl_kernel`. The three cache-key tuples become named\nfunctions so both cache levels derive from one source of truth, and the artifact name appends a\ndigest of that tuple — the keys hold floats and `None` (`swiglu_*`), and `1.5` / `-1.5` both sanitize\nto `1_5`, so a formatted name would not be injective.\n\nAs in the existing adopters, the kernels now compile against\n`make_fake_stream(use_tvm_ffi_env_stream=True)`, so TVM-FFI supplies the caller's current stream and\nthe two launch sites no longer pass one (compiled signatures: 24 / 24 / 32 parameters).\n\n**Not covered:** the direct-micro kernel (`compile_direct_micro_kernel`), which this module started\ndispatching to recently. It compiles without `--enable-tvm-ffi` and launches through the DSL rather\nthan a TVM-FFI callable, so caching it is a separate change — #4317 is only partly closed by this PR.\n\n### Measured — GB10 (sm_121), DSL 4.6.0, five kernel shapes per process\n\n| process | total compile + load |\n|---|---:|\n| before, two runs | 17.92 s / 17.95 s |\n| after, cold first run | 18.91 s |\n| after, two later runs | **0.130 s / 0.134 s** (~135×) |\n\nWarm, per kernel: dynamic 7.7 s → 1 ms; static 3.2 s → 1 ms; micro 2.3–3.2 s → 1 ms (the first warm\nkernel pays 0.13 s of one-off module setup). The cold run costs a few percent for the export.\nArtifacts are 161–262 KB each.\n\n## 🔍 Related Issues\n\n#4317 (partly — see the scope note above). Builds on the cache infrastructure from #3874 and #4029.\n\n## 🚀 Pull Request Checklist\n\n### ✅ Pre-commit Checks\n\n- [x] `pre-commit` installed.\n- [x] Hooks installed.\n- [x] `pre-commit run` on the two changed files: all hooks pass, no files modified. (I ran it\n file-scoped rather than `--all-files`, since the remaining hooks are repo-wide.)\n\n## 🧪 Tests\n\n- [x] Tests added.\n- [x] The new tests pass; see the caveat below for what does not run on my hardware.\n\n- New `tests/moe/test_b12x_moe_kernel_cache.py`: 61 naming-contract tests — signature coverage,\n per-argument perturbation, symbol safety, cross-family collision — replicating\n `tests/jit/test_cute_dsl_cache.py` as the design doc asks of new adopters (happy to fold them into\n that file instead if you would rather keep all adopters together).\n- Also checked on the same host: a corrupt artifact and a read-only cache directory each fall back to\n compiling with a warning, and editing a key source invalidates the module and recompiles it once.\n\n**Not verified — please check on sm120 hardware.** `tests/moe/test_b12x_fused_moe.py`'s numerical\ntests do not run on my GB10: the nvcc reference ops fail to build (`CUDA compiler and CUDA toolkit\nheaders are incompatible`). The suite gives an identical `142 failed, 15 passed` — the same 142 test\nids — on unmodified `main` and on this branch, so I have no accuracy signal either way. All timings\nabove are compile/load time; steady-state kernel performance should be unchanged, since it is the\nsame binary.\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n* **New Features**\n * Added shared on-disk caching for static, micro, and dynamic MoE kernels.\n * Improved cache invalidation when source dependencies change.\n * Kernel launches now automatically use the caller’s active CUDA stream.\n\n* **Tests**\n * Added comprehensive coverage for cache-key completeness, naming stability, symbol safety, and uniqueness across kernel types.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"e2e\", \"hardware\": \"GB10\", \"model\": null, \"shape\": null, \"batch_size\": null, \"metric\": \"compile + load time\", \"unit\": \"s\", \"higher_is_better\": false, \"baseline\": 17.92, \"optimized\": 0.13, \"stated_speedup\": 135, \"speedup\": 137.8462}, {\"scope\": \"e2e\", \"hardware\": \"GB10\", \"model\": null, \"shape\": null, \"batch_size\": null, \"metric\": \"compile + load time\", \"unit\": \"s\", \"higher_is_better\": false, \"baseline\": 17.95, \"optimized\": 0.134, \"stated_speedup\": 135, \"speedup\": 133.9552}]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"number","value":135.9007,"string":"135.9007"}}},{"rowIdx":1093,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"553c2280a88581c7ede39aa571a54d1232854b81"},"date":{"kind":"string","value":"2026-08-07T18:17:26+08:00"},"pr_number":{"kind":"number","value":4329,"string":"4,329"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/4329"},"title":{"kind":"string","value":"feat: optimize gated SM12x dynamic NVFP4 MoE (#4329)"},"message":{"kind":"string","value":"feat: optimize gated SM12x dynamic NVFP4 MoE (#4329)\n\nRoute gated activations through the optimized branch-paired dynamic\nkernel while preserving the generic fallback for non-gated activations.\nSupport SiLU, GELU-tanh, and SwiGLU-OAI without an environment toggle.\n\n<!-- .github/pull_request_template.md -->\n## 📌 Description\n\nThis PR integrates an optimized branch-paired dynamic NVFP4 MoE kernel\nfor gated activations on Blackwell SM12x into the regular FlashInfer\nCuTeDSL dispatch path.\n\n### What changed\n\n- Split the dynamic MoE implementation into:\n - `_moe_dynamic/generic.py`: the existing generic fallback.\n - `_moe_dynamic/gated.py`: the optimized gated implementation.\n- Dispatch `silu`, `gelu_tanh`, and `swigluoai_uninterleave` to the\noptimized gated kernel.\n- Preserve the generic dynamic path for non-gated activations such as\n`relu2`.\n- Pair the gate and up projections in the N64 FC1 dataflow to reduce\nstaging and accumulator lifetimes.\n- Preserve the tuned explicit inline-PTX reciprocal path for SiLU.\n- Reuse the canonical activation formulas for GELU-tanh and SwiGLU-OAI\nwhile keeping them on the optimized gated dataflow.\n- Keep FC2 on the non-gated execution path.\n- Keep the public `MoEDynamicKernel` API unchanged.\n- Enable the optimized path through normal activation-based dispatch\nwithout an environment-variable switch.\n\n### Why\n\nA gated MoE FC1 computes two projections:\n\n```text\noutput = activation(gate_projection) * up_projection\n```\n\nThe previous generic dynamic implementation handled the two branches\nwithout exploiting their shared scheduling structure.\n\nThe new implementation pairs the gate and up branch work in the dynamic\nN64 kernel. This shortens intermediate lifetimes and reduces staging\noverhead while preserving the existing routing, NVFP4 quantization, FC2,\nand scatter behavior.\n\nThe top-level activation dispatch selects the gated implementation. The\ninternal `is_gated` distinction is still required because the same\nkernel object participates in both stages:\n\n- FC1 is gated and uses the paired gate/up path.\n- FC2 is not gated and continues to use the regular projection path.\n\n### Correctness\n\nValidated on an SM120 Blackwell GPU against the BF16 reference with:\n\n```text\nM = 384\nH = 256\nI = 512\nE = 8\ntopk = 2\n```\n\n| Activation | Result | Finite output |\n| --- | ---: | ---: |\n| `silu` | 100% within the existing NVFP4 tolerance | Yes |\n| `gelu_tanh` | 100% within the existing NVFP4 tolerance | Yes |\n| `swigluoai_uninterleave` | 100% within the existing NVFP4 tolerance |\nYes |\n\nNo NaN or Inf values were observed.\n\nStatic validation also passed:\n\n```text\nruff check\nruff format --check\npython -m py_compile\n```\n\n### Performance\n\nThe benchmark compares this PR against the native FlashInfer CuTeDSL\nimplementation at the PR's current upstream base. No kernel overlay or\nenvironment-variable kernel override was used.\n\nCompared revisions:\n\n- Upstream base: `d7e390c17844f493db23320cb7952375f03bc6c4`\n- PR head: `594ca394c9328db582a689591392e13adcab092b`\n\nBenchmark environment:\n\n- GPU: NVIDIA RTX PRO 5000 72GB Blackwell, SM120\n- PyTorch 2.11.0+cu130 and CuTeDSL 4.6.1\n- CUDA Graph event timing\n- 192 MiB L2 flush before every timed replay\n- Warmup / iterations / repeats: 5 / 50 / 5\n- 22 token-count points from M=1 to M=8192\n- Qwen3.5-122B uses a 100-file routing trace replay\n- Qwen3.5-35B and Qwen3.5-397B use seeded random unique top-k routing\n- M<96 uses the existing static/micro backend; M>=96 uses the dynamic\nbackend changed by this PR\n\nBoth revisions were measured on the same GPU with the same benchmark\ncommand and protocol. Each revision used an isolated JIT/cache\ndirectory. Lower latency is better.\n\n| Model configuration | M | Upstream native CuTeDSL (us) | This PR (us)\n| Latency reduction |\n| --- | ---: | ---: | ---: | ---: |\n| Qwen3.5-35B TP1 | 4096 | 1012.692 | 586.782 | 42.06% |\n| Qwen3.5-35B TP1 | 8192 | 1749.317 | 927.645 | 46.97% |\n| Qwen3.5-122B TP2 | 4096 | 1461.020 | 938.726 | 35.75% |\n| Qwen3.5-122B TP2 | 8192 | 2517.957 | 1441.407 | 42.75% |\n| Qwen3.5-122B TP4 | 4096 | 932.632 | 639.082 | 31.48% |\n| Qwen3.5-122B TP4 | 8192 | 1618.032 | 1027.254 | 36.51% |\n| Qwen3.5-397B TP4 | 4096 | 1829.354 | 1626.127 | 11.11% |\n| Qwen3.5-397B TP4 | 8192 | 3064.157 | 2453.747 | 19.92% |\n| Qwen3.5-397B TP8 | 4096 | 1285.750 | 1112.290 | 13.49% |\n| Qwen3.5-397B TP8 | 8192 | 2330.589 | 1856.785 | 20.33% |\n\nGeometric-mean latency reduction across the sweep:\n\n| Model configuration | All 22 M points | Dynamic path, M>=96 |\n| --- | ---: | ---: |\n| Qwen3.5-35B TP1 | 20.24% | 31.74% |\n| Qwen3.5-122B TP2 | 17.12% | 27.17% |\n| Qwen3.5-122B TP4 | 12.71% | 20.43% |\n| Qwen3.5-397B TP4 | 3.88% | 6.49% |\n| Qwen3.5-397B TP8 | 4.83% | 8.15% |\n\nThe static/micro M<96 subset changed by only -0.19% to +0.22% across the\nfive configurations, consistent with measurement noise on the unchanged\npath. The larger full-sweep gains therefore come from the dynamic path\ntargeted by this PR.\n## 🔍 Related Issues\n\nN/A\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used my preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see the\n[pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\nPlease pay particular attention to:\n\n- The activation-based dispatch boundary between the generic and gated\nimplementations.\n- The distinction between top-level gated-kernel selection and internal\nFC1/FC2 `is_gated` behavior.\n- SiLU's explicit inline-PTX reciprocal emission path.\n- Correctness of the GELU-tanh and SwiGLU-OAI activation formulas inside\nthe optimized gated dataflow.\n\nThe non-gated fallback and public `MoEDynamicKernel` interface are\nintentionally unchanged.\n\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n* **New Features**\n* Added dynamic fused Mixture-of-Experts support for Blackwell\nSM120/SM121 GPUs.\n* Added NVFP4 processing with routed-token packing, quantization, expert\ncomputation, and weighted output scattering.\n* Added support for gated and non-gated activations, including SiLU,\nSwiGLU, ReLU2, GELU-tanh, and SwiGLU-OAI variants.\n* Added configurable fast math, scaling, cross-expert input sharing, and\nSwiGLU parameters.\n\n* **Refactor**\n * Unified dynamic MoE kernel selection across activation types.\n * Added automatic fallback for unsupported shapes and configurations.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n\n---------\n\nCo-authored-by: EricChen02 <EricChen02@users.noreply.github.com>"},"path":{"kind":"string","value":"flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_dispatch.py"},"language":{"kind":"string","value":"cute_dsl"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"\"\"\"SM120/SM121 MoE dispatch layer — workspace, compilation, and launch.\n\nPorted from b12x's integration/tp_moe.py. Supports micro (tiny decode),\nstatic (decode), and dynamic (prefill) backends with token-count-based\nselection.\n\"\"\"\n\nfrom __future__ import annotations\n\nimport os\nimport weakref\nfrom dataclasses import dataclass\nfrom typing import Any, Dict, Optional, Tuple, Union\n\nimport cutlass\nimport cutlass.cute as cute\nimport torch\n\nfrom flashinfer.cute_dsl.utils import (\n convert_sf_from_mma_layout,\n convert_sf_to_mma_layout,\n current_cuda_stream,\n get_max_active_clusters,\n get_num_sm,\n make_ptr,\n)\nfrom .moe_activation import SWIGLUOAI_UNINTERLEAVE, is_gated_activation\nfrom .moe_direct_micro_kernel import (\n MoEDirectMicroKernel,\n build_direct_micro_kernel,\n compile_direct_micro_kernel,\n compiled_direct_micro_accepts_block_dim,\n)\nfrom .moe_dynamic_kernel import _TASK_SLICE_CHUNK, MoEDynamicKernel\nfrom .moe_micro_kernel import MoEMicroKernel\nfrom .moe_static_kernel import MoEStaticKernel\nfrom .moe_w4a16_fp4_helpers import swizzle_block_scale\nfrom .moe_w4a16_host import (\n _W4A16_ALLOWED_ROUTED_SIZES,\n max_packed_route_slots,\n packed_gemm_scratch_elements,\n route_pack_numel_capacity,\n unswizzle_block_scale,\n validate_activation,\n)\nfrom .moe_w4a16_kernel import run_w4a16_moe\nfrom .moe_w4a16_prepare import (\n W4A16PackedWeights,\n _normalize_source_format,\n prepare_w4a16_packed_weights,\n)\n\n# ---------------------------------------------------------------------------\n# Constants\n# ---------------------------------------------------------------------------\n_NVFP4_BLOCK_SIZE = 16\n_LEVEL_TILE_M = 128\n_LEVEL_TILE_N = 128\n# Must equal the kernel's task materialization granularity or the task\n# queue is mis-sized.\n_DYNAMIC_SLICE_CHUNK = _TASK_SLICE_CHUNK\nSF_VEC_SIZE = 16\n_FORCE_MOE_W4A16_ENV = \"FLASHINFER_B12X_FORCE_MOE_W4A16\"\n_MICRO_SHARE_INPUT_ACROSS_EXPERTS = (\n os.environ.get(\"FLASHINFER_B12X_MICRO_SHARE_INPUT\", \"1\") != \"0\"\n)\n\n# Micro kernel cutover thresholds (routed pairs)\n_MICRO_COMPACT_CUTOVER_PAIRS = 20\n_MICRO_COMPACT_CUTOVER_PAIRS_MULTI_TOPK = 40\n# The micro kernel's per-token staging assumes decode-sized batches.\n_MICRO_MAX_TOKENS = 8\n# Direct micro takes the smallest decode batches ahead of the MMA micro\n# kernel, and only at small intermediate sizes where its CUDA-core dots\n# keep up with per-token work. Measured on GB10, pending other GPUs.\n_DIRECT_MICRO_CUTOVER_PAIRS = 32\n_DIRECT_MICRO_MAX_N = 512\n# Test/bench hook: force one backend (\"direct_micro\", \"micro\", \"static\",\n# \"dynamic\"). Deliberately module-level (a monkeypatch target), not an env var.\n_FORCED_BACKEND: str | None = None\n_STATIC_COMPACT_CUTOVER_PAIRS_DEFAULT = 640\n_STATIC_COMPACT_CUTOVER_PAIRS = _STATIC_COMPACT_CUTOVER_PAIRS_DEFAULT\n_STATIC_COMPACT_CUTOVER_PAIRS_CACHE: Dict[str, int] = {}\n\n# MAC (max active clusters) tuning ladders from b12x decode profiling.\n# Each entry is (max_routed_rows, optimal_mac).\n_MICRO_MAC_LADDER: Tuple[Tuple[int, int], ...] = (\n (2, 84),\n (4, 127),\n (8, 107),\n (10, 84),\n (16, 63),\n (20, 84),\n)\n_STATIC_MAC_LADDER: Tuple[Tuple[int, int], ...] = (\n (24, 148),\n (32, 169),\n (40, 132),\n (48, 149),\n (64, 134),\n (80, 175),\n (96, 171),\n (120, 125),\n (128, 130),\n (160, 171),\n (192, 166),\n (256, 141),\n (320, 158),\n (512, 175),\n (640, 188),\n)\n# Workloads at or below the static cutover (640 routed pairs by default)\n# take the static kernel, so only the 1024 entry is normally reachable.\n_DYNAMIC_MAC_LADDER: Tuple[Tuple[int, int], ...] = (\n (640, 188),\n (1024, 147),\n)\n\n\ndef _lookup_mac_ladder(\n ladder: Tuple[Tuple[int, int], ...], routed_rows: int\n) -> int | None:\n \"\"\"Look up optimal MAC from a tuning ladder. Returns None if no match.\"\"\"\n for end_rows, mac in ladder:\n if routed_rows <= end_rows:\n return mac\n return None\n\n\ndef _align_up(value: int, alignment: int) -> int:\n return ((value + alignment - 1) // alignment) * alignment\n\n\n# The kernels index the packed activation and scale planes with 32-bit\n# offsets, so reject any workspace plane large enough to overflow them.\n_RUNTIME_MEMREF_LIMIT = (1 << 31) - 1\n\n\ndef _check_memref_limit(name: str, elements: int) -> None:\n if elements > _RUNTIME_MEMREF_LIMIT:\n raise ValueError(\n f\"{name} needs {elements} elements, which exceeds the 2^31-1 \"\n \"runtime memref limit. Reduce the token chunk or expert count \"\n \"for this launch.\"\n )\n\n\ndef _first_env(*names: str) -> str | None:\n for name in names:\n value = os.environ.get(name)\n if value is not None:\n return value\n return None\n\n\ndef _normalize_activation_precision(activation_precision: str) -> str:\n \"\"\"Normalize public activation-precision names to internal modes.\"\"\"\n if os.environ.get(_FORCE_MOE_W4A16_ENV, \"0\") == \"1\":\n return \"bf16\"\n\n normalized = str(activation_precision).lower()\n aliases = {\n \"fp4\": \"fp4\",\n \"nvfp4\": \"fp4\",\n \"w4a4\": \"fp4\",\n \"bf16\": \"bf16\",\n \"w4a16\": \"bf16\",\n }\n try:\n return aliases[normalized]\n except KeyError as exc:\n raise ValueError(\n \"activation_precision must be 'fp4' or 'bf16' \"\n f\"(got {activation_precision!r}).\"\n ) from exc\n\n\ndef _normalize_quant_mode(\n quant_mode: str | None = None,\n activation_precision: str | None = None,\n) -> str:\n \"\"\"Normalize public quantization names to the dispatch mode.\"\"\"\n if os.environ.get(_FORCE_MOE_W4A16_ENV, \"0\") == \"1\":\n return \"w4a16\"\n if quant_mode is None:\n activation_precision = _normalize_activation_precision(\n activation_precision or \"fp4\"\n )\n return \"w4a16\" if activation_precision == \"bf16\" else \"nvfp4\"\n\n normalized = str(quant_mode).lower()\n aliases = {\n \"fp4\": \"nvfp4\",\n \"nvfp4\": \"nvfp4\",\n \"w4a4\": \"nvfp4\",\n \"bf16\": \"w4a16\",\n \"w4a16\": \"w4a16\",\n }\n try:\n return aliases[normalized]\n except KeyError as exc:\n raise ValueError(\n f\"quant_mode must be 'nvfp4'/'w4a4' or 'w4a16' (got {quant_mode!r}).\"\n ) from exc\n\n\ndef _activation_precision_from_quant_mode(quant_mode: str) -> str:\n return \"bf16\" if _normalize_quant_mode(quant_mode) == \"w4a16\" else \"fp4\"\n\n\ndef _normalize_source_format_for_quant_mode(source_format: str, quant_mode: str) -> str:\n normalized = _normalize_source_format(source_format)\n if quant_mode == \"nvfp4\" and normalized == \"compressed_tensors\":\n raise ValueError(\n \"source_format='compressed_tensors' requires quant_mode='w4a16'.\"\n )\n return normalized\n\n\ndef _is_w4a16(activation_precision: str) -> bool:\n return _normalize_activation_precision(activation_precision) == \"bf16\"\n\n\ndef _level_tile_n(activation_precision: str = \"fp4\") -> int:\n if _is_w4a16(activation_precision):\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 tile selector\"\n )\n return _LEVEL_TILE_N\n\n\ndef _select_dynamic_tile_m(\n routed_rows: int,\n num_experts: int,\n activation: str = \"silu\",\n) -> int:\n \"\"\"Pick the dynamic kernel's M-tile from routed rows per expert.\n\n Small tiles cut per-expert tail padding for sparse routing; 128 amortizes\n best for dense prefill (crossovers measured on gated NVFP4). Workspace\n sizing and the kernel build must both derive the tile from this function,\n or the scratch is mis-sized for what the kernel indexes.\n \"\"\"\n if not is_gated_activation(activation):\n return _LEVEL_TILE_M\n routed_rows = max(1, int(routed_rows))\n num_experts = max(1, int(num_experts))\n if routed_rows < 15 * num_experts:\n return 16\n if routed_rows < 48 * num_experts:\n return 32\n if routed_rows < 96 * num_experts:\n return 64\n return _LEVEL_TILE_M\n\n\ndef _get_static_compact_cutover_pairs(activation_precision: str = \"fp4\") -> int:\n activation_precision = _normalize_activation_precision(activation_precision)\n cached = _STATIC_COMPACT_CUTOVER_PAIRS_CACHE.get(activation_precision)\n if cached is not None:\n return cached\n\n cutover_names: tuple[str, ...] = (\n \"FLASHINFER_B12X_STATIC_COMPACT_CUTOVER_PAIRS\",\n \"B12X_STATIC_COMPACT_CUTOVER_PAIRS\",\n \"B12X_DYNAMIC_STATIC_CUTOVER_PAIRS\",\n \"B12X_LEVEL10_STATIC_CUTOVER_PAIRS\",\n )\n cutover = _first_env(*cutover_names)\n if cutover is None:\n cached = _STATIC_COMPACT_CUTOVER_PAIRS_DEFAULT\n else:\n cached = max(0, int(cutover))\n _STATIC_COMPACT_CUTOVER_PAIRS_CACHE[activation_precision] = cached\n return cached\n\n\ndef _select_moe_mma_tiler_mn(\n routed_rows: int,\n n: int,\n *,\n resident_clusters: int | None = None,\n) -> Tuple[int, int]:\n \"\"\"Select optimal MoE tile shape based on routed rows and N dimension.\n\n Uses narrower 64x128 tiles when routed_rows <= 128 and default 128x128\n would leave SMs idle.\n \"\"\"\n sm_count = get_num_sm(torch.device(\"cuda\"))\n coarse_tile = (128, 128)\n if routed_rows <= 32 and n <= 256:\n return (64, 128)\n if resident_clusters is not None and resident_clusters < sm_count:\n return coarse_tile\n coarse_tiles = ((routed_rows + coarse_tile[0] - 1) // coarse_tile[0]) * (\n (n + coarse_tile[1] - 1) // coarse_tile[1]\n )\n # Single-token decode often lands exactly on the \"half the machine\"\n # boundary. Keeping the coarse 128x128 tile there leaves the M dimension\n # badly underfilled, so take the narrow 64x128 tile inclusive of equality.\n if routed_rows <= 64 or (\n routed_rows <= 128 and coarse_tiles <= max(1, sm_count // 2)\n ):\n return (64, 128)\n return (128, 128)\n\n\ndef _as_grouped_scale_view(\n scale_storage: torch.Tensor,\n rows: int,\n cols: int,\n) -> torch.Tensor:\n \"\"\"Create 6D MMA-compatible scale factor view from swizzled storage.\"\"\"\n batch = scale_storage.shape[0]\n rows_padded = _align_up(rows, 128)\n cols_padded = _align_up(cols // SF_VEC_SIZE, 4)\n sf = scale_storage.view(torch.float8_e4m3fn)\n sf = sf.view(batch, rows_padded // 128, cols_padded // 4, 32, 4, 4)\n return sf.permute(3, 4, 1, 5, 2, 0)\n\n\n# ---------------------------------------------------------------------------\n# Workspace\n# ---------------------------------------------------------------------------\n@dataclass(kw_only=True)\nclass Sm120StaticMoEWorkspace:\n \"\"\"Scratch buffers for one SM120 static MoE launch.\"\"\"\n\n state_E: int\n weight_E: int\n max_rows: int\n k: int\n n: int\n num_topk: int\n device: torch.device\n activation_precision: str\n\n # Buffers\n row_counts: torch.Tensor # [state_E] int32\n token_map: torch.Tensor # [state_E, max_rows] int32\n token_weights: torch.Tensor # [state_E, max_rows] float32\n packed_input: torch.Tensor # [state_E, max_rows, k//2] uint8\n packed_input_scale: torch.Tensor # [state_E, rows_pad_k, cols_pad_k] uint8\n barrier_count: torch.Tensor # [1] int32\n barrier_epoch: torch.Tensor # [1] int32\n active_expert_count: torch.Tensor # [1] int32\n weight_expert_ids: torch.Tensor # [state_E] int32\n global_to_local_expert: torch.Tensor # [weight_E] int32\n compact_topk_ids: torch.Tensor # [state_E] int32, for micro kernel pre-pass\n\n # Views (set after allocation)\n packed_a_view: torch.Tensor | None = None\n sfa_ptr: object = None\n packed_a_flat: torch.Tensor | None = None\n scale_flat: torch.Tensor | None = None\n\n # Direct micro planes (allocated only when the shape can take that path).\n dm_barrier_count: torch.Tensor | None = None\n dm_barrier_epoch: torch.Tensor | None = None\n dm_intermediate: torch.Tensor | None = None\n dm_input_gs: torch.Tensor | None = None\n dm_down_input_scale: torch.Tensor | None = None\n\n\ndef _direct_micro_candidate(k: int, n: int, num_topk: int, weight_E: int) -> bool:\n \"\"\"Whether any m in the tiny-decode band can run the direct micro kernel.\"\"\"\n return any(\n MoEDirectMicroKernel.is_supported(m, k, n, num_topk, weight_E)\n for m in range(1, _MICRO_MAX_TOKENS + 1)\n )\n\n\ndef allocate_sm120_static_workspace(\n *,\n state_E: int,\n weight_E: int,\n max_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation_precision: str = \"fp4\",\n) -> Sm120StaticMoEWorkspace:\n \"\"\"Allocate workspace buffers for the SM120 static MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"allocate_sm120_static_workspace only supports quant_mode='nvfp4'; \"\n \"use allocate_sm120_moe_workspace(..., quant_mode='w4a16') for W4A16.\"\n )\n\n rows_pad_k = _align_up(max_rows, 128)\n cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n _check_memref_limit(\"static packed_input\", state_E * max_rows * (k // 2))\n _check_memref_limit(\"static packed_input_scale\", state_E * rows_pad_k * cols_pad_k)\n packed_input = torch.empty(\n state_E, max_rows, k // 2, dtype=torch.uint8, device=device\n )\n\n workspace = Sm120StaticMoEWorkspace(\n state_E=state_E,\n weight_E=weight_E,\n max_rows=max_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation_precision=activation_precision,\n row_counts=torch.zeros(state_E, dtype=torch.int32, device=device),\n token_map=torch.zeros(state_E, max_rows, dtype=torch.int32, device=device),\n token_weights=torch.zeros(\n state_E, max_rows, dtype=torch.float32, device=device\n ),\n packed_input=packed_input,\n packed_input_scale=torch.empty(\n state_E, rows_pad_k, cols_pad_k, dtype=torch.uint8, device=device\n ),\n barrier_count=torch.zeros(1, dtype=torch.int32, device=device),\n barrier_epoch=torch.zeros(1, dtype=torch.int32, device=device),\n active_expert_count=torch.zeros(1, dtype=torch.int32, device=device),\n weight_expert_ids=torch.arange(state_E, dtype=torch.int32, device=device),\n global_to_local_expert=torch.empty(weight_E, dtype=torch.int32, device=device),\n compact_topk_ids=torch.empty(\n max(state_E, max_rows), dtype=torch.int32, device=device\n ),\n )\n\n # Finalize views\n sf_dtype = cutlass.Float8E4M3FN\n workspace.packed_a_view = workspace.packed_input.permute(1, 2, 0).view(\n torch.float4_e2m1fn_x2\n )\n workspace.packed_a_flat = workspace.packed_input.view(-1)\n workspace.scale_flat = workspace.packed_input_scale.view(-1)\n workspace.sfa_ptr = make_ptr(\n sf_dtype,\n workspace.packed_input_scale.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n\n # Direct micro reads weights by global expert id, so its planes are only\n # useful without EP remapping.\n if state_E == weight_E and _direct_micro_candidate(k, n, num_topk, weight_E):\n dm_rows = min(max_rows, _MICRO_MAX_TOKENS * num_topk)\n # The epoch-based barriers restore their slots after each launch, so\n # the zeroed allocation is the only reset needed (graph-replay safe).\n dm_slots = dm_rows + _MICRO_MAX_TOKENS * 16\n fc2_n_chunks = (n // 2 + 127) // 128\n # The fused kernel binds the intermediate as m * num_topk *\n # fc2_n_chunks * 128 u32 words; size for the largest supported m.\n dm_inter = _MICRO_MAX_TOKENS * num_topk * fc2_n_chunks * 128\n workspace.dm_barrier_count = torch.zeros(\n dm_slots, dtype=torch.int32, device=device\n )\n workspace.dm_barrier_epoch = torch.zeros(\n dm_slots, dtype=torch.int32, device=device\n )\n workspace.dm_intermediate = torch.empty(\n dm_inter, dtype=torch.float32, device=device\n )\n workspace.dm_input_gs = torch.empty(\n weight_E, dtype=torch.float32, device=device\n )\n workspace.dm_down_input_scale = torch.empty(\n weight_E, dtype=torch.float32, device=device\n )\n return workspace\n\n\n# ---------------------------------------------------------------------------\n# Weight views\n# ---------------------------------------------------------------------------\n@dataclass\nclass _WeightViews:\n w13_fp4: object = None\n down_fp4: object = None\n sfb_w13_ptr: object = None\n sfb_down_ptr: object = None\n w1_alpha: torch.Tensor | None = None\n w2_alpha: torch.Tensor | None = None\n w1_storage: torch.Tensor | None = None\n w1_scale_storage: torch.Tensor | None = None\n w2_storage: torch.Tensor | None = None\n w2_scale_storage: torch.Tensor | None = None\n _w13_sf_storage: torch.Tensor | None = None\n _down_sf_storage: torch.Tensor | None = None\n\n\ndef _register_cache_eviction(cache: Dict, key: Tuple, *source_tensors) -> None:\n \"\"\"Evict ``key`` when a source weight tensor is collected, so the cache\n follows the weights' lifetime instead of growing for the whole process.\n \"\"\"\n for tensor in source_tensors:\n if tensor is not None:\n weakref.finalize(tensor, cache.pop, key, None)\n\n\n_WEIGHT_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_weight_views(\n w1_fp4: torch.Tensor,\n w1_blockscale: torch.Tensor,\n w2_fp4: torch.Tensor,\n w2_blockscale: torch.Tensor,\n w1_alphas: torch.Tensor,\n w2_alphas: torch.Tensor,\n n: int,\n k: int,\n activation_precision: str = \"fp4\",\n) -> _WeightViews:\n \"\"\"Create permuted weight views for the static kernel.\n\n The kernel expects concatenated w13 data with shape [2*n, k//2, E]\n via a single TMA descriptor.\n \"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n tile_n = _level_tile_n(activation_precision)\n # The kernel splits w13 into gate/up halves by tile index. This only works\n # when the boundary between halves lands on a tile-aligned column.\n if n % tile_n != 0:\n raise ValueError(\n f\"intermediate_size ({n}) must be a multiple of {tile_n} \"\n f\"for the SM120 MoE kernel's gate/up tile split.\"\n )\n\n key = (\n activation_precision,\n w1_fp4.data_ptr(),\n w1_blockscale.data_ptr(),\n w1_alphas.data_ptr(),\n w2_fp4.data_ptr(),\n w2_blockscale.data_ptr(),\n w2_alphas.data_ptr(),\n )\n cached = _WEIGHT_CACHE.get(key)\n if cached is None:\n # Cache the fresh buffers (scale factors + fp32 alphas).\n w1_rows = w1_fp4.shape[1] # 2*n for gated, n for non-gated\n cached = (\n convert_sf_from_mma_layout(\n w1_blockscale, m=w1_rows, k=k, num_groups=w1_fp4.shape[0]\n ).contiguous(),\n convert_sf_from_mma_layout(\n w2_blockscale, m=k, k=n, num_groups=w2_fp4.shape[0]\n ).contiguous(),\n w1_alphas.contiguous().to(torch.float32),\n w2_alphas.contiguous().to(torch.float32),\n )\n _WEIGHT_CACHE[key] = cached\n _register_cache_eviction(\n _WEIGHT_CACHE,\n key,\n w1_fp4,\n w1_blockscale,\n w1_alphas,\n w2_fp4,\n w2_blockscale,\n w2_alphas,\n )\n w13_sf_contiguous, down_sf_contiguous, w1_alpha, w2_alpha = cached\n\n # Permute [E, w1_rows, k//2] -> [w1_rows, k//2, E] (view, no copy).\n sf_dtype = cutlass.Float8E4M3FN\n w13 = w1_fp4.permute(1, 2, 0)\n down = w2_fp4.permute(1, 2, 0)\n return _WeightViews(\n w13_fp4=w13.view(torch.float4_e2m1fn_x2),\n down_fp4=down.view(torch.float4_e2m1fn_x2),\n sfb_w13_ptr=make_ptr(\n sf_dtype,\n w13_sf_contiguous.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n ),\n sfb_down_ptr=make_ptr(\n sf_dtype,\n down_sf_contiguous.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n ),\n w1_alpha=w1_alpha,\n w2_alpha=w2_alpha,\n w1_storage=w1_fp4,\n w1_scale_storage=w13_sf_contiguous,\n w2_storage=w2_fp4,\n w2_scale_storage=down_sf_contiguous,\n _w13_sf_storage=w13_sf_contiguous,\n _down_sf_storage=down_sf_contiguous,\n )\n\n\n# ---------------------------------------------------------------------------\n# Kernel compilation cache\n# ---------------------------------------------------------------------------\n_STATIC_KERNEL_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_static_kernel(\n state_E: int,\n weight_E: int,\n m: int,\n k: int,\n n: int,\n num_topk: int,\n max_rows: int,\n *,\n topk_ids_dtype: torch.dtype = torch.int32,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n mac_override: int | None = None,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n):\n \"\"\"Compile (or retrieve cached) the SM120 static MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 static compiler\"\n )\n sf_vec_size = 16\n sm_count = get_num_sm(torch.device(\"cuda\"))\n mac = (\n mac_override\n if mac_override is not None\n else min(get_max_active_clusters(1), sm_count)\n )\n\n # Select tile size based on actual routed rows\n routed_rows = m * num_topk\n mma_tiler_mn = (128, 128)\n if activation_precision == \"fp4\" and num_topk > 1:\n mma_tiler_mn = _select_moe_mma_tiler_mn(routed_rows, n, resident_clusters=mac)\n\n cache_key = (\n \"static\",\n activation_precision,\n state_E,\n weight_E,\n m,\n k,\n n,\n num_topk,\n max_rows,\n mac,\n mma_tiler_mn,\n topk_ids_dtype,\n input_scales_are_reciprocal,\n fast_math,\n activation,\n swiglu_alpha,\n swiglu_beta,\n swiglu_limit,\n )\n cached = _STATIC_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n return cached\n\n ab_dtype = cutlass.Float4E2M1FN\n weight_dtype = cutlass.Float4E2M1FN\n sf_dtype = cutlass.Float8E4M3FN\n a_dtype = cutlass.BFloat16\n alpha_dtype = cutlass.Float32\n\n output_tile_count_n = max(1, (n + mma_tiler_mn[1] - 1) // mma_tiler_mn[1])\n kernel: Any = MoEStaticKernel(\n sf_vec_size=sf_vec_size,\n mma_tiler_mn=mma_tiler_mn,\n output_tile_count_n=output_tile_count_n,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n )\n\n is_gated = is_gated_activation(activation)\n w1_rows = (2 if is_gated else 1) * n # 2*n for gated, n for non-gated\n\n rows_pad_k = _align_up(max_rows, 128)\n cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n\n # Build fake tensors for compilation\n a_input_fake = cute.runtime.make_fake_compact_tensor(\n a_dtype,\n (m, k),\n stride_order=(1, 0),\n assumed_align=16,\n )\n topk_ids_cutlass_dtype = (\n cutlass.Int32 if topk_ids_dtype == torch.int32 else cutlass.Int64\n )\n topk_ids_align = 4 if topk_ids_dtype == torch.int32 else 8\n topk_ids_fake = cute.runtime.make_fake_compact_tensor(\n topk_ids_cutlass_dtype,\n (m * num_topk,),\n assumed_align=topk_ids_align,\n )\n topk_weights_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32,\n (m * num_topk,),\n assumed_align=4,\n )\n packed_a_fake = cute.runtime.make_fake_compact_tensor(\n ab_dtype,\n (max_rows, k, state_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfa_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n packed_a_storage_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (state_E * max_rows * (k // 2),),\n assumed_align=16,\n )\n scale_storage_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (state_E * rows_pad_k * cols_pad_k,),\n assumed_align=16,\n )\n barrier_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n barrier_epoch_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n b_w13_fake = cute.runtime.make_fake_compact_tensor(\n weight_dtype,\n (w1_rows, k, weight_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_w13_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n b_down_fake = cute.runtime.make_fake_compact_tensor(\n weight_dtype,\n (k, n, weight_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_down_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n row_counts_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E,),\n assumed_align=4,\n )\n active_expert_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n weight_expert_ids_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E,),\n assumed_align=4,\n )\n global_to_local_expert_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (weight_E,),\n assumed_align=4,\n )\n input_gs_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n down_alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n global_scale_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n scatter_fake = cute.runtime.make_fake_compact_tensor(\n a_dtype,\n (m, k),\n stride_order=(1, 0),\n assumed_align=16,\n )\n token_map_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E, max_rows),\n stride_order=(1, 0),\n assumed_align=4,\n )\n token_weights_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (state_E, max_rows),\n stride_order=(1, 0),\n assumed_align=16,\n )\n compiled = cute.compile(\n kernel,\n a_input_fake,\n topk_ids_fake,\n topk_weights_fake,\n packed_a_fake,\n sfa_fake,\n packed_a_storage_fake,\n scale_storage_fake,\n barrier_count_fake,\n barrier_epoch_fake,\n b_w13_fake,\n sfb_w13_fake,\n b_down_fake,\n sfb_down_fake,\n row_counts_fake,\n active_expert_count_fake,\n weight_expert_ids_fake,\n global_to_local_expert_fake,\n input_gs_fake,\n alpha_fake,\n down_alpha_fake,\n global_scale_fake,\n scatter_fake,\n token_map_fake,\n token_weights_fake,\n mac,\n current_cuda_stream(),\n options=\"--opt-level 2 --enable-tvm-ffi\",\n )\n\n result = (compiled, mac)\n _STATIC_KERNEL_CACHE[cache_key] = result\n return result\n\n\n_MICRO_KERNEL_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_micro_kernel(\n state_E: int,\n weight_E: int,\n m: int,\n k: int,\n n: int,\n num_topk: int,\n max_rows: int,\n *,\n topk_ids_dtype: torch.dtype = torch.int32,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n share_input_across_experts: bool = False,\n share_expert_scales: bool = False,\n single_token: bool = False,\n mac_override: int | None = None,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n):\n \"\"\"Compile (or retrieve cached) the SM120 micro MoE kernel.\"\"\"\n sf_vec_size = 16\n sm_count = get_num_sm(torch.device(\"cuda\"))\n mac = (\n mac_override\n if mac_override is not None\n else min(get_max_active_clusters(1), sm_count)\n )\n\n # Micro always selects tile from routed rows (not just for multi-topk)\n routed_rows = m * num_topk\n mma_tiler_mn = _select_moe_mma_tiler_mn(routed_rows, n)\n\n cache_key = (\n \"micro\",\n state_E,\n weight_E,\n m,\n k,\n n,\n num_topk,\n max_rows,\n mac,\n mma_tiler_mn,\n topk_ids_dtype,\n input_scales_are_reciprocal,\n fast_math,\n share_input_across_experts,\n share_expert_scales,\n single_token,\n activation,\n swiglu_alpha,\n swiglu_beta,\n swiglu_limit,\n )\n cached = _MICRO_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n return cached\n\n ab_dtype = cutlass.Float4E2M1FN\n sf_dtype = cutlass.Float8E4M3FN\n a_dtype = cutlass.BFloat16\n alpha_dtype = cutlass.Float32\n\n kernel = MoEMicroKernel(\n sf_vec_size=sf_vec_size,\n mma_tiler_mn=mma_tiler_mn,\n output_tile_count_n=max(1, (n + mma_tiler_mn[1] - 1) // mma_tiler_mn[1]),\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n share_input_across_experts=share_input_across_experts,\n share_expert_scales=share_expert_scales,\n single_token=single_token,\n )\n\n is_gated = is_gated_activation(activation)\n w1_rows = (2 if is_gated else 1) * n\n\n rows_pad_k = _align_up(max_rows, 128)\n cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n\n # Build fake tensors for compilation (identical to static kernel)\n a_input_fake = cute.runtime.make_fake_compact_tensor(\n a_dtype,\n (m, k),\n stride_order=(1, 0),\n assumed_align=16,\n )\n topk_ids_cutlass_dtype = (\n cutlass.Int32 if topk_ids_dtype == torch.int32 else cutlass.Int64\n )\n topk_ids_align = 4 if topk_ids_dtype == torch.int32 else 8\n topk_ids_fake = cute.runtime.make_fake_compact_tensor(\n topk_ids_cutlass_dtype,\n (m * num_topk,),\n assumed_align=topk_ids_align,\n )\n topk_weights_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32,\n (m * num_topk,),\n assumed_align=4,\n )\n packed_a_fake = cute.runtime.make_fake_compact_tensor(\n ab_dtype,\n (max_rows, k, state_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfa_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n packed_a_storage_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (state_E * max_rows * (k // 2),),\n assumed_align=16,\n )\n scale_storage_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (state_E * rows_pad_k * cols_pad_k,),\n assumed_align=16,\n )\n barrier_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n barrier_epoch_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n b_w13_fake = cute.runtime.make_fake_compact_tensor(\n ab_dtype,\n (w1_rows, k, weight_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_w13_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n b_down_fake = cute.runtime.make_fake_compact_tensor(\n ab_dtype,\n (k, n, weight_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_down_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n row_counts_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E,),\n assumed_align=4,\n )\n active_expert_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n weight_expert_ids_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E,),\n assumed_align=4,\n )\n global_to_local_expert_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (weight_E,),\n assumed_align=4,\n )\n input_gs_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n down_alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n global_scale_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n scatter_fake = cute.runtime.make_fake_compact_tensor(\n a_dtype,\n (m, k),\n stride_order=(1, 0),\n assumed_align=16,\n )\n token_map_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E, max_rows),\n stride_order=(1, 0),\n assumed_align=4,\n )\n token_weights_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (state_E, max_rows),\n stride_order=(1, 0),\n assumed_align=16,\n )\n compiled = cute.compile(\n kernel,\n a_input_fake,\n topk_ids_fake,\n topk_weights_fake,\n packed_a_fake,\n sfa_fake,\n packed_a_storage_fake,\n scale_storage_fake,\n barrier_count_fake,\n barrier_epoch_fake,\n b_w13_fake,\n sfb_w13_fake,\n b_down_fake,\n sfb_down_fake,\n row_counts_fake,\n active_expert_count_fake,\n weight_expert_ids_fake,\n global_to_local_expert_fake,\n input_gs_fake,\n alpha_fake,\n down_alpha_fake,\n global_scale_fake,\n scatter_fake,\n token_map_fake,\n token_weights_fake,\n mac,\n current_cuda_stream(),\n options=\"--opt-level 2 --enable-tvm-ffi\",\n )\n\n result = (compiled, mac)\n _MICRO_KERNEL_CACHE[cache_key] = result\n return result\n\n\n# The launch cache skips the per-launch build/configure; the kernel cache\n# dedupes compiles across keys that configure to the same artifact\n# (m=2..8 differ only in grid_x).\n_DIRECT_MICRO_LAUNCH_CACHE: Dict[Tuple, Tuple] = {}\n_DIRECT_MICRO_KERNEL_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_direct_micro_kernel(\n weight_E: int,\n m: int,\n k: int,\n n: int,\n num_topk: int,\n *,\n topk_ids_dtype: torch.dtype = torch.int32,\n fast_math: bool = True,\n share_input_across_experts: bool = False,\n share_expert_scales: bool = False,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n device: torch.device | None = None,\n):\n \"\"\"Compile (or retrieve cached) the SM120 direct micro MoE kernel.\n\n Returns (compiled, grid_x, accepts_block_dim).\n \"\"\"\n if activation != SWIGLUOAI_UNINTERLEAVE:\n # The kernel constructor only accepts configurable swiglu parameters\n # for swigluoai; other activations use its normalized defaults\n # (accept-and-ignore, matching the MMA kernels).\n swiglu_alpha = None\n swiglu_beta = None\n swiglu_limit = None\n launch_key = (\n weight_E,\n m,\n k,\n n,\n num_topk,\n topk_ids_dtype,\n fast_math,\n share_input_across_experts,\n share_expert_scales,\n activation,\n swiglu_alpha,\n swiglu_beta,\n swiglu_limit,\n str(_canonical_cuda_device(device)) if device is not None else None,\n )\n cached = _DIRECT_MICRO_LAUNCH_CACHE.get(launch_key)\n if cached is not None:\n return cached\n kernel = build_direct_micro_kernel(\n weight_E,\n m,\n k,\n n,\n num_topk,\n activation=activation,\n fast_math=fast_math,\n share_input_across_experts=share_input_across_experts,\n share_expert_scales=share_expert_scales,\n single_token=m == 1,\n swiglu_limit=swiglu_limit,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n device=device,\n )\n compile_key = (\"direct_micro\", kernel.__cache_key__, topk_ids_dtype)\n entry = _DIRECT_MICRO_KERNEL_CACHE.get(compile_key)\n if entry is None:\n compiled = compile_direct_micro_kernel(kernel, topk_ids_dtype=topk_ids_dtype)\n # Register pressure can cap the launchable CTA below the fused body's\n # 512 threads; probe once per compiled kernel.\n accepts = compiled_direct_micro_accepts_block_dim(\n compiled, kernel.launch_block_dim\n )\n entry = (compiled, accepts)\n _DIRECT_MICRO_KERNEL_CACHE[compile_key] = entry\n compiled, accepts = entry\n cached = (compiled, kernel.grid_x, accepts)\n _DIRECT_MICRO_LAUNCH_CACHE[launch_key] = cached\n return cached\n\n\n# ---------------------------------------------------------------------------\n# Launch\n# ---------------------------------------------------------------------------\ndef _expand_to_experts(t: torch.Tensor, num_experts: int) -> torch.Tensor:\n \"\"\"Broadcast a scalar or [1] tensor to [num_experts], always fp32.\n\n Both branches must cast: the kernels are compiled against fp32 fake\n tensors for every per-expert scale.\n \"\"\"\n if t.numel() == 1:\n return t.to(torch.float32).expand(num_experts).contiguous()\n return t.contiguous().to(torch.float32)\n\n\ndef launch_sm120_static_moe(\n *,\n workspace: Sm120StaticMoEWorkspace,\n weights: _WeightViews,\n a: torch.Tensor,\n topk_ids: torch.Tensor,\n topk_weights: torch.Tensor,\n input_gs: torch.Tensor,\n down_input_scale: torch.Tensor,\n scatter_output: torch.Tensor,\n num_experts: int,\n num_tokens: int,\n k: int,\n n: int,\n top_k: int,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n) -> torch.Tensor:\n \"\"\"Launch the SM120 static, micro, or direct micro MoE kernel.\n\n The direct micro kernel takes tiny decode batches (m <= 8, routed_rows\n < 64) when it supports the shape, the MMA micro kernel takes the rest of\n its band (routed_rows <= 20-40), and the static kernel takes the rest.\n The MMA micro path runs a Triton pre-pass to compact routing IDs before\n launching; direct micro routes on global expert ids directly.\n \"\"\"\n _check_memref_limit(\"scatter_output\", scatter_output.numel())\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 static launcher\"\n )\n\n # Flatten routing tensors\n flat_ids = topk_ids.view(-1).to(torch.int32)\n flat_weights = topk_weights.view(-1).to(torch.float32)\n routed_rows = num_tokens * top_k\n\n # Capture whether input_gs was a single shared scalar BEFORE expansion:\n # the m=1 relu2 shared-input micro optimization only applies when every\n # expert sees the same FC1-input global scale.\n input_gs_is_shared = input_gs.numel() == 1\n down_input_scale_is_shared = down_input_scale.numel() == 1\n\n # Broadcast scalar scales to per-expert [E] tensors\n input_gs = _expand_to_experts(input_gs, num_experts)\n down_input_scale = _expand_to_experts(down_input_scale, num_experts)\n\n # Shared-scale flags let compact W4A4 micro match the ReLU2 single-token\n # specialization.\n share_input_across_experts = (\n activation == \"relu2\"\n and num_tokens == 1\n and input_gs_is_shared\n and _MICRO_SHARE_INPUT_ACROSS_EXPERTS\n )\n share_expert_scales = (\n activation == \"relu2\" and input_gs_is_shared and down_input_scale_is_shared\n )\n\n # Direct micro takes its band before the MMA micro decision. It reads\n # weights by global expert id, so EP shapes keep the compact path.\n use_direct_micro = (\n activation_precision == \"fp4\"\n and workspace.state_E == num_experts\n and workspace.dm_barrier_count is not None\n and workspace.dm_barrier_count.numel() >= routed_rows + num_tokens * 16\n and num_tokens <= _MICRO_MAX_TOKENS\n and routed_rows < _DIRECT_MICRO_CUTOVER_PAIRS\n and n <= _DIRECT_MICRO_MAX_N\n and MoEDirectMicroKernel.is_supported(num_tokens, k, n, top_k, num_experts)\n )\n if _FORCED_BACKEND is not None:\n if _FORCED_BACKEND == \"direct_micro\":\n if workspace.dm_barrier_count is None or not (\n MoEDirectMicroKernel.is_supported(num_tokens, k, n, top_k, num_experts)\n ):\n raise ValueError(\n \"forced direct_micro backend cannot run this shape \"\n f\"(m={num_tokens}, k={k}, n={n}, top_k={top_k})\"\n )\n if workspace.dm_barrier_count.numel() < routed_rows + num_tokens * 16:\n raise ValueError(\n \"forced direct_micro backend exceeds the workspace barrier \"\n f\"capacity ({workspace.dm_barrier_count.numel()} slots < \"\n f\"{routed_rows} routed rows + {num_tokens * 16})\"\n )\n use_direct_micro = True\n else:\n use_direct_micro = False\n if use_direct_micro:\n compiled, grid_x, block_ok = _get_direct_micro_kernel(\n num_experts,\n num_tokens,\n k,\n n,\n top_k,\n topk_ids_dtype=flat_ids.dtype,\n fast_math=fast_math,\n share_input_across_experts=share_input_across_experts,\n share_expert_scales=share_expert_scales,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n device=a.device,\n )\n if not block_ok:\n if _FORCED_BACKEND == \"direct_micro\":\n raise RuntimeError(\"compiled direct micro MoE kernel cannot launch\")\n use_direct_micro = False\n if use_direct_micro:\n # The kernel takes multiplier-form scales only; invert reciprocal\n # inputs into the persistent workspace planes (zeros stay zero,\n # matching the MMA kernels).\n if input_scales_are_reciprocal:\n workspace.dm_input_gs.copy_(\n torch.where(input_gs != 0, 1.0 / input_gs, input_gs)\n )\n workspace.dm_down_input_scale.copy_(\n torch.where(\n down_input_scale != 0, 1.0 / down_input_scale, down_input_scale\n )\n )\n launch_gs = workspace.dm_input_gs\n launch_down = workspace.dm_down_input_scale\n else:\n launch_gs = input_gs\n launch_down = down_input_scale\n MoEDirectMicroKernel.launch(\n compiled,\n x=a,\n w1_fp4=weights.w1_storage,\n w1_blockscale=weights.w1_scale_storage,\n w1_alphas=weights.w1_alpha,\n a1_gscale=launch_gs,\n a2_gscale=launch_down,\n inter_fp32=workspace.dm_intermediate,\n w2_fp4=weights.w2_storage,\n w2_blockscale=weights.w2_scale_storage,\n w2_alphas=weights.w2_alpha,\n topk_ids=flat_ids,\n topk_weights=flat_weights,\n out=scatter_output,\n barrier_count=workspace.dm_barrier_count,\n barrier_epoch=workspace.dm_barrier_epoch,\n m=num_tokens,\n grid_x=grid_x,\n )\n return scatter_output\n\n # Decide micro vs static\n micro_cutover = _MICRO_COMPACT_CUTOVER_PAIRS\n if top_k > 1:\n micro_cutover = _MICRO_COMPACT_CUTOVER_PAIRS_MULTI_TOPK\n use_micro = (\n activation_precision == \"fp4\"\n and num_tokens <= _MICRO_MAX_TOKENS\n and routed_rows <= micro_cutover\n )\n if _FORCED_BACKEND is not None:\n if _FORCED_BACKEND == \"micro\":\n # Forced mode raises on correctness violations, never falls back.\n if num_tokens > _MICRO_MAX_TOKENS:\n raise ValueError(\n f\"forced micro backend supports at most {_MICRO_MAX_TOKENS} \"\n f\"tokens (got {num_tokens})\"\n )\n if flat_ids.numel() > workspace.compact_topk_ids.numel():\n raise ValueError(\n \"forced micro backend exceeds the workspace compact-id \"\n f\"capacity ({workspace.compact_topk_ids.numel()} < \"\n f\"{flat_ids.numel()})\"\n )\n use_micro = True\n else:\n use_micro = False\n\n sm_count = get_num_sm(torch.device(\"cuda\"))\n base_mac = min(get_max_active_clusters(1), sm_count)\n tuned_static_mac = _lookup_mac_ladder(_STATIC_MAC_LADDER, routed_rows)\n static_mac = min(tuned_static_mac or base_mac, base_mac)\n if activation_precision == \"fp4\" and not use_micro and routed_rows < 40:\n static_mac = min(static_mac, 64)\n\n if use_micro:\n assert flat_ids.numel() <= workspace.compact_topk_ids.numel(), (\n f\"compact_topk_ids buffer too small: \"\n f\"{workspace.compact_topk_ids.numel()} < {flat_ids.numel()}\"\n )\n # Single-token ReLU2 is non-gated, so the micro kernel can launch on\n # the routed expert ids directly. Gated SiLU still goes through the\n # compact id buffer so the kernel can map compact launch ids back to\n # the physical gate/up weight experts.\n if num_tokens == 1 and activation == \"relu2\":\n launch_ids = flat_ids\n elif num_tokens == 1:\n compact_ids = workspace.compact_topk_ids[: flat_ids.numel()]\n compact_ids.copy_(\n torch.arange(\n flat_ids.numel(),\n device=flat_ids.device,\n dtype=torch.int32,\n )\n )\n workspace.weight_expert_ids[: flat_ids.numel()].copy_(\n flat_ids.to(torch.int32)\n )\n workspace.active_expert_count.fill_(flat_ids.numel())\n launch_ids = compact_ids\n else:\n compact_ids = workspace.compact_topk_ids[: flat_ids.numel()]\n from .triton_compact import compact_topk_ids as _triton_compact_topk_ids\n\n _triton_compact_topk_ids(\n flat_ids,\n compact_ids,\n workspace.weight_expert_ids,\n workspace.active_expert_count,\n )\n launch_ids = compact_ids\n # Select micro MAC: min of tuned ladder, work tiles, and hardware limit.\n micro_work_tiles = max(1, routed_rows * max(1, (n + 128 - 1) // 128))\n tuned_mac = _lookup_mac_ladder(_MICRO_MAC_LADDER, routed_rows)\n micro_mac = min(tuned_mac or base_mac, micro_work_tiles, base_mac)\n compiled, mac = _get_micro_kernel(\n workspace.state_E,\n num_experts,\n num_tokens,\n k,\n n,\n top_k,\n workspace.max_rows,\n topk_ids_dtype=launch_ids.dtype,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n share_input_across_experts=share_input_across_experts,\n share_expert_scales=share_expert_scales,\n single_token=num_tokens == 1,\n mac_override=micro_mac,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n )\n else:\n compiled, mac = _get_static_kernel(\n workspace.state_E,\n num_experts,\n num_tokens,\n k,\n n,\n top_k,\n workspace.max_rows,\n topk_ids_dtype=torch.int32,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n mac_override=static_mac,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n activation_precision=activation_precision,\n )\n launch_ids = flat_ids\n\n # Pointer arguments must be passed as raw ints (data_ptr()) at runtime.\n runtime_args: Tuple[Any, ...] = (\n a,\n launch_ids,\n flat_weights,\n workspace.packed_a_view,\n workspace.packed_input_scale.data_ptr(),\n workspace.packed_a_flat,\n workspace.scale_flat,\n workspace.barrier_count,\n workspace.barrier_epoch,\n weights.w13_fp4,\n weights._w13_sf_storage.data_ptr(),\n weights.down_fp4,\n weights._down_sf_storage.data_ptr(),\n workspace.row_counts,\n workspace.active_expert_count,\n workspace.weight_expert_ids,\n workspace.global_to_local_expert,\n input_gs,\n weights.w1_alpha,\n weights.w2_alpha,\n down_input_scale,\n scatter_output,\n workspace.token_map,\n workspace.token_weights,\n )\n compiled(*runtime_args, current_cuda_stream())\n\n return scatter_output\n\n\n# ==========================================================================\n# Dynamic backend\n# ==========================================================================\n\n\ndef select_sm120_moe_backend(\n *,\n num_tokens: int,\n num_topk: int,\n activation_precision: str = \"fp4\",\n quant_mode: str | None = None,\n) -> str:\n \"\"\"Pick static or dynamic backend based on routed-pair count.\"\"\"\n mode = _normalize_quant_mode(quant_mode, activation_precision)\n if mode == \"w4a16\":\n return \"w4a16\"\n if _FORCED_BACKEND == \"dynamic\":\n return \"dynamic\"\n if _FORCED_BACKEND in (\"static\", \"micro\", \"direct_micro\"):\n # Both micro variants launch through the static workspace path.\n return \"static\"\n routed_rows = num_tokens * num_topk\n if routed_rows <= _get_static_compact_cutover_pairs(\"fp4\"):\n return \"static\"\n return \"dynamic\"\n\n\n# ---------------------------------------------------------------------------\n# Dynamic workspace\n# ---------------------------------------------------------------------------\n@dataclass(kw_only=True)\nclass Sm120DynamicMoEWorkspace:\n \"\"\"Scratch buffers for one SM120 dynamic MoE launch.\"\"\"\n\n state_E: int\n weight_E: int\n max_rows: int\n k: int\n n: int\n num_topk: int\n device: torch.device\n activation_precision: str\n\n # Core buffers\n row_counts: torch.Tensor\n token_map: torch.Tensor\n token_weights: torch.Tensor\n packed_input: torch.Tensor\n packed_input_scale: torch.Tensor\n barrier_count: torch.Tensor\n barrier_epoch: torch.Tensor\n\n # Dynamic-specific\n routed_rows_capacity: int\n physical_tiles_capacity: int\n task_capacity: int\n # The M-tile the geometry above was sized for; launches must build the\n # kernel with the same tile.\n tile_m: int = _LEVEL_TILE_M\n expert_write_rows: torch.Tensor\n expert_tile_base: torch.Tensor\n pair_head: torch.Tensor\n task_head: torch.Tensor\n task_tail: torch.Tensor\n task_expert: torch.Tensor\n task_valid_rows: torch.Tensor\n\n # Views\n packed_a_view: torch.Tensor | None = None\n sfa_ptr: object = None\n packed_a_flat: torch.Tensor | None = None\n scale_flat: torch.Tensor | None = None\n\n\ndef _dynamic_task_geometry(\n state_E: int,\n n: int,\n routed_rows: int,\n *,\n tile_m: int = _LEVEL_TILE_M,\n tile_n: int = _LEVEL_TILE_N,\n):\n \"\"\"Compute task queue dimensions from problem geometry.\n\n Each active expert can introduce at most one additional physical tile\n beyond the base count (due to per-expert tail padding). The task queue\n holds one entry per (m_tile, slice_group) pair — NOT multiplied by E.\n \"\"\"\n routed_rows = max(1, routed_rows)\n base_m_tiles = _align_up(routed_rows, tile_m) // tile_m\n active_expert_upper_bound = min(state_E, routed_rows)\n max_m_tiles = max(1, base_m_tiles + active_expert_upper_bound - 1)\n gate_tile_cnt = max(1, (n + tile_n - 1) // tile_n)\n slice_groups = max(\n 1, (gate_tile_cnt + _DYNAMIC_SLICE_CHUNK - 1) // _DYNAMIC_SLICE_CHUNK\n )\n max_tasks = max_m_tiles * slice_groups\n return max_m_tiles, gate_tile_cnt, max_tasks\n\n\ndef allocate_sm120_dynamic_workspace(\n *,\n state_E: int,\n weight_E: int,\n routed_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation_precision: str = \"fp4\",\n activation: str = \"silu\",\n) -> Sm120DynamicMoEWorkspace:\n \"\"\"Allocate workspace buffers for the SM120 dynamic MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"allocate_sm120_dynamic_workspace only supports quant_mode='nvfp4'; \"\n \"use allocate_sm120_moe_workspace(..., quant_mode='w4a16') for W4A16.\"\n )\n tile_m = _select_dynamic_tile_m(routed_rows, state_E, activation)\n physical_tiles, _, max_tasks = _dynamic_task_geometry(\n state_E,\n n,\n routed_rows,\n tile_m=tile_m,\n tile_n=_level_tile_n(activation_precision),\n )\n rows_padded = physical_tiles * tile_m\n # The kernel addresses activation scales in 128-row SF atoms regardless of\n # tile_m, so the scale plane must cover the last partial atom.\n scale_rows = _align_up(rows_padded, 128)\n cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n _check_memref_limit(\"dynamic packed_input\", rows_padded * (k // 2))\n _check_memref_limit(\"dynamic packed_input_scale\", scale_rows * cols_pad_k)\n packed_input = torch.empty(1, rows_padded, k // 2, dtype=torch.uint8, device=device)\n\n workspace = Sm120DynamicMoEWorkspace(\n state_E=state_E,\n weight_E=weight_E,\n max_rows=rows_padded,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation_precision=activation_precision,\n routed_rows_capacity=routed_rows,\n physical_tiles_capacity=physical_tiles,\n task_capacity=max_tasks,\n tile_m=tile_m,\n row_counts=torch.zeros(state_E, dtype=torch.int32, device=device),\n token_map=torch.zeros(rows_padded, dtype=torch.int32, device=device),\n token_weights=torch.zeros(rows_padded, dtype=torch.float32, device=device),\n packed_input=packed_input,\n packed_input_scale=torch.empty(\n scale_rows, cols_pad_k, dtype=torch.uint8, device=device\n ),\n barrier_count=torch.zeros(1, dtype=torch.int32, device=device),\n barrier_epoch=torch.zeros(1, dtype=torch.int32, device=device),\n expert_write_rows=torch.zeros(state_E, dtype=torch.int32, device=device),\n expert_tile_base=torch.zeros(state_E + 1, dtype=torch.int32, device=device),\n pair_head=torch.zeros(1, dtype=torch.int32, device=device),\n task_head=torch.zeros(1, dtype=torch.int32, device=device),\n task_tail=torch.zeros(1, dtype=torch.int32, device=device),\n task_expert=torch.zeros(max_tasks, dtype=torch.int32, device=device),\n task_valid_rows=torch.zeros(max_tasks, dtype=torch.int32, device=device),\n )\n\n # Finalize views\n sf_dtype = cutlass.Float8E4M3FN\n workspace.packed_a_view = workspace.packed_input.permute(1, 2, 0).view(\n torch.float4_e2m1fn_x2\n )\n workspace.packed_a_flat = workspace.packed_input.view(-1)\n workspace.scale_flat = workspace.packed_input_scale.view(-1)\n workspace.sfa_ptr = make_ptr(\n sf_dtype,\n workspace.packed_input_scale.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n return workspace\n\n\n# ---------------------------------------------------------------------------\n# Dynamic kernel compilation\n# ---------------------------------------------------------------------------\n\n\nclass _DynamicMoELaunch:\n \"\"\"Thin JIT wrapper that makes num_tokens and max_rows runtime Int32.\"\"\"\n\n def __init__(self, kernel, k, num_topk, activation_precision: str = \"fp4\"):\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 dynamic launcher wrapper\"\n )\n self._kernel = kernel\n self._k = k\n self._packed_storage_cols = k // 2\n self._num_topk = num_topk\n self._cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n\n @cute.jit\n def __call__(\n self,\n a_ptr: cute.Pointer,\n topk_ids_ptr: cute.Pointer,\n topk_weights_ptr: cute.Pointer,\n packed_a_ptr: cute.Pointer,\n sfa_ptr: cute.Pointer,\n packed_a_storage_ptr: cute.Pointer,\n scale_storage_ptr: cute.Pointer,\n barrier_count: cute.Tensor,\n barrier_epoch: cute.Tensor,\n pair_head: cute.Tensor,\n task_head: cute.Tensor,\n task_tail: cute.Tensor,\n task_expert_ptr: cute.Pointer,\n task_valid_rows_ptr: cute.Pointer,\n b_w13: cute.Tensor,\n sfb_w13_ptr: cute.Pointer,\n b_down: cute.Tensor,\n sfb_down_ptr: cute.Pointer,\n row_counts: cute.Tensor,\n expert_write_rows: cute.Tensor,\n expert_tile_base: cute.Tensor,\n input_global_scale: cute.Tensor,\n alpha: cute.Tensor,\n down_alpha: cute.Tensor,\n global_scale: cute.Tensor,\n scatter_ptr: cute.Pointer,\n token_map_ptr: cute.Pointer,\n token_weights_ptr: cute.Pointer,\n num_tokens: cutlass.Int32,\n max_rows: cutlass.Int32,\n rows_padded: cutlass.Int32,\n max_tasks: cutlass.Int32,\n max_active_clusters: cutlass.Constexpr,\n stream,\n ):\n a_input = cute.make_tensor(\n a_ptr, layout=cute.make_layout((num_tokens, self._k), stride=(self._k, 1))\n )\n topk_ids = cute.make_tensor(\n topk_ids_ptr,\n layout=cute.make_layout((num_tokens * self._num_topk,), stride=(1,)),\n )\n topk_weights_t = cute.make_tensor(\n topk_weights_ptr,\n layout=cute.make_layout((num_tokens * self._num_topk,), stride=(1,)),\n )\n scatter_output = cute.make_tensor(\n scatter_ptr,\n layout=cute.make_layout((num_tokens, self._k), stride=(self._k, 1)),\n )\n packed_a = cute.make_tensor(\n packed_a_ptr,\n layout=cute.make_layout(\n (rows_padded, self._k, 1), stride=(self._k, 1, rows_padded * self._k)\n ),\n )\n packed_a_storage = cute.make_tensor(\n packed_a_storage_ptr,\n layout=cute.make_layout(\n (rows_padded * self._packed_storage_cols,), stride=(1,)\n ),\n )\n # Activation scales live in 128-row SF atoms; the plane is allocated\n # through the last partial atom even when rows_padded is not aligned.\n scale_rows = ((rows_padded + 127) // 128) * 128\n scale_storage = cute.make_tensor(\n scale_storage_ptr,\n layout=cute.make_layout((scale_rows * self._cols_pad_k,), stride=(1,)),\n )\n token_map = cute.make_tensor(\n token_map_ptr, layout=cute.make_layout((rows_padded,), stride=(1,))\n )\n token_weights_t = cute.make_tensor(\n token_weights_ptr, layout=cute.make_layout((rows_padded,), stride=(1,))\n )\n task_expert = cute.make_tensor(\n task_expert_ptr, layout=cute.make_layout((max_tasks,), stride=(1,))\n )\n task_valid_rows = cute.make_tensor(\n task_valid_rows_ptr, layout=cute.make_layout((max_tasks,), stride=(1,))\n )\n self._kernel(\n a_input,\n topk_ids,\n topk_weights_t,\n packed_a,\n sfa_ptr,\n packed_a_storage,\n scale_storage,\n barrier_count,\n barrier_epoch,\n pair_head,\n task_head,\n task_tail,\n task_expert,\n task_valid_rows,\n b_w13,\n sfb_w13_ptr,\n b_down,\n sfb_down_ptr,\n row_counts,\n expert_write_rows,\n expert_tile_base,\n input_global_scale,\n alpha,\n down_alpha,\n global_scale,\n scatter_output,\n token_map,\n token_weights_t,\n max_active_clusters=max_active_clusters,\n stream=stream,\n )\n\n\n_DYNAMIC_KERNEL_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_dynamic_kernel(\n E: int,\n m: int,\n k: int,\n n: int,\n num_topk: int,\n max_rows: int,\n *,\n topk_ids_dtype: torch.dtype = torch.int32,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n share_input_across_experts: bool = False,\n tile_m: int = _LEVEL_TILE_M,\n):\n \"\"\"Compile (or retrieve cached) the SM120 dynamic MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 dynamic compiler\"\n )\n share_input_across_experts = bool(\n share_input_across_experts and activation_precision == \"fp4\"\n )\n sf_vec_size = 16\n sm_count = get_num_sm(torch.device(\"cuda\"))\n base_mac = min(get_max_active_clusters(1), sm_count)\n tuned_mac = _lookup_mac_ladder(_DYNAMIC_MAC_LADDER, m * num_topk)\n mac = min(tuned_mac or base_mac, base_mac)\n # tile_m comes from the workspace's shared selection so the kernel's task\n # and scale indexing matches the allocated scratch geometry.\n mma_tiler_mn = (tile_m, _level_tile_n(activation_precision))\n\n cache_key = (\n \"dynamic\",\n activation_precision,\n E,\n k,\n n,\n num_topk,\n mac,\n mma_tiler_mn,\n topk_ids_dtype,\n input_scales_are_reciprocal,\n fast_math,\n activation,\n swiglu_alpha,\n swiglu_beta,\n swiglu_limit,\n share_input_across_experts,\n )\n cached = _DYNAMIC_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n return cached\n\n is_gated = is_gated_activation(activation)\n w1_rows = (2 if is_gated else 1) * n\n\n scratch_dtype = cutlass.Float4E2M1FN\n weight_dtype = cutlass.Float4E2M1FN\n sf_dtype = cutlass.Float8E4M3FN\n a_dtype = cutlass.BFloat16\n alpha_dtype = cutlass.Float32\n\n kernel: Any = MoEDynamicKernel(\n sf_vec_size=sf_vec_size,\n mma_tiler_mn=mma_tiler_mn,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n share_input_across_experts=share_input_across_experts,\n )\n launch = _DynamicMoELaunch(\n kernel,\n k=k,\n num_topk=num_topk,\n activation_precision=activation_precision,\n )\n\n topk_ids_cutlass_dtype = (\n cutlass.Int32 if topk_ids_dtype == torch.int32 else cutlass.Int64\n )\n topk_ids_align = 4 if topk_ids_dtype == torch.int32 else 8\n\n # Runtime-shaped tensors passed as pointers\n a_input_fake = make_ptr(a_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n topk_ids_fake = make_ptr(\n topk_ids_cutlass_dtype,\n topk_ids_align,\n cute.AddressSpace.gmem,\n assumed_align=topk_ids_align,\n )\n topk_weights_fake = make_ptr(\n cutlass.Float32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n packed_a_fake = make_ptr(\n scratch_dtype, 16, cute.AddressSpace.gmem, assumed_align=16\n )\n sfa_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n packed_a_storage_fake = make_ptr(\n cutlass.Uint8, 16, cute.AddressSpace.gmem, assumed_align=16\n )\n scale_storage_fake = make_ptr(\n cutlass.Uint8, 16, cute.AddressSpace.gmem, assumed_align=16\n )\n\n barrier_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n barrier_epoch_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n pair_head_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n task_head_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n task_tail_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n\n task_expert_fake = make_ptr(\n cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n task_valid_rows_fake = make_ptr(\n cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n\n b_w13_fake = cute.runtime.make_fake_compact_tensor(\n weight_dtype,\n (w1_rows, k, E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_w13_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n b_down_fake = cute.runtime.make_fake_compact_tensor(\n weight_dtype,\n (k, n, E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_down_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n row_counts_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (E,), assumed_align=4\n )\n expert_write_rows_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (E,), assumed_align=4\n )\n expert_tile_base_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (E + 1,), assumed_align=4\n )\n input_gs_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype, (E,), assumed_align=16\n )\n alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype, (E,), assumed_align=16\n )\n down_alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype, (E,), assumed_align=16\n )\n global_scale_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype, (E,), assumed_align=16\n )\n scatter_fake = make_ptr(a_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n token_map_fake = make_ptr(cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4)\n token_weights_fake = make_ptr(\n alpha_dtype, 16, cute.AddressSpace.gmem, assumed_align=16\n )\n\n compiled = cute.compile(\n launch,\n a_input_fake,\n topk_ids_fake,\n topk_weights_fake,\n packed_a_fake,\n sfa_fake,\n packed_a_storage_fake,\n scale_storage_fake,\n barrier_count_fake,\n barrier_epoch_fake,\n pair_head_fake,\n task_head_fake,\n task_tail_fake,\n task_expert_fake,\n task_valid_rows_fake,\n b_w13_fake,\n sfb_w13_fake,\n b_down_fake,\n sfb_down_fake,\n row_counts_fake,\n expert_write_rows_fake,\n expert_tile_base_fake,\n input_gs_fake,\n alpha_fake,\n down_alpha_fake,\n global_scale_fake,\n scatter_fake,\n token_map_fake,\n token_weights_fake,\n 1,\n 1,\n 1,\n 1, # runtime Int32 placeholders\n mac,\n current_cuda_stream(),\n options=\"--opt-level 2 --enable-tvm-ffi\",\n )\n\n result = (compiled, mac)\n _DYNAMIC_KERNEL_CACHE[cache_key] = result\n return result\n\n\n# ---------------------------------------------------------------------------\n# Dynamic launch\n# ---------------------------------------------------------------------------\ndef launch_sm120_dynamic_moe(\n *,\n workspace: Sm120DynamicMoEWorkspace,\n weights: _WeightViews,\n a: torch.Tensor,\n topk_ids: torch.Tensor,\n topk_weights: torch.Tensor,\n input_gs: torch.Tensor,\n down_input_scale: torch.Tensor,\n scatter_output: torch.Tensor,\n num_experts: int,\n num_tokens: int,\n k: int,\n n: int,\n top_k: int,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n) -> torch.Tensor:\n \"\"\"Launch the SM120 dynamic MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 dynamic launcher\"\n )\n _check_memref_limit(\"scatter_output\", scatter_output.numel())\n flat_ids = topk_ids.view(-1).to(torch.int32)\n flat_weights = topk_weights.view(-1).to(torch.float32)\n input_gs_is_shared = input_gs.numel() == 1\n\n # Broadcast scalar scales to per-expert [E] tensors\n input_gs = _expand_to_experts(input_gs, num_experts)\n down_input_scale = _expand_to_experts(down_input_scale, num_experts)\n\n compiled, mac = _get_dynamic_kernel(\n num_experts,\n num_tokens,\n k,\n n,\n top_k,\n workspace.max_rows,\n topk_ids_dtype=torch.int32,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n activation_precision=activation_precision,\n share_input_across_experts=input_gs_is_shared,\n tile_m=workspace.tile_m,\n )\n\n # Dynamic kernel: runtime-shaped args are DataPointer (pass data_ptr()),\n # fixed-shape args are Tensor (pass torch tensor directly).\n runtime_args: Tuple[Any, ...] = (\n a.data_ptr(),\n flat_ids.data_ptr(),\n flat_weights.data_ptr(),\n workspace.packed_a_view.data_ptr(),\n workspace.packed_input_scale.data_ptr(),\n workspace.packed_a_flat.data_ptr(),\n workspace.scale_flat.data_ptr(),\n workspace.barrier_count,\n workspace.barrier_epoch,\n workspace.pair_head,\n workspace.task_head,\n workspace.task_tail,\n workspace.task_expert.data_ptr(),\n workspace.task_valid_rows.data_ptr(),\n weights.w13_fp4,\n weights._w13_sf_storage.data_ptr(),\n weights.down_fp4,\n weights._down_sf_storage.data_ptr(),\n workspace.row_counts,\n workspace.expert_write_rows,\n workspace.expert_tile_base,\n input_gs,\n weights.w1_alpha,\n weights.w2_alpha,\n down_input_scale,\n scatter_output.data_ptr(),\n workspace.token_map.data_ptr(),\n workspace.token_weights.data_ptr(),\n num_tokens,\n workspace.max_rows,\n workspace.physical_tiles_capacity * workspace.tile_m,\n workspace.task_capacity,\n )\n compiled(*runtime_args, current_cuda_stream())\n\n return scatter_output\n\n\n# ==========================================================================\n# W4A16 route-packing implementation\n# ==========================================================================\n@dataclass(kw_only=True)\nclass Sm120W4A16MoEWorkspace:\n \"\"\"Scratch buffers for the SM120 W4A16 MoE path.\"\"\"\n\n state_E: int\n weight_E: int\n max_rows: int\n k: int\n n: int\n num_topk: int\n device: torch.device\n activation: str\n activation_precision: str\n quant_mode: str\n routed_rows_capacity: int\n route_num_experts: int\n\n intermediate_cache13: torch.Tensor\n intermediate_cache2: torch.Tensor\n fc1_c_tmp: torch.Tensor\n fc2_c_tmp: torch.Tensor\n packed_route_indices: torch.Tensor\n block_expert_ids: torch.Tensor\n packed_route_count: torch.Tensor\n expert_offsets: torch.Tensor\n expert_map: torch.Tensor | None = None\n\n\ndef _is_cuda_graph_capturing() -> bool:\n try:\n return bool(torch.cuda.is_current_stream_capturing())\n except Exception:\n return False\n\n\ndef _canonical_cuda_device(device: torch.device) -> torch.device:\n device = torch.device(device)\n if device.type == \"cuda\" and device.index is None:\n return torch.device(\"cuda\", torch.cuda.current_device())\n return device\n\n\ndef _w4a16_workspace_geometry(\n *,\n routed_rows: int,\n route_num_experts: int,\n num_topk: int,\n k: int,\n n: int,\n is_gated: bool,\n device: torch.device,\n) -> tuple[int, int, int, int, int]:\n route_slots = 1\n route_blocks = 1\n fc1_c_tmp_elements = 1\n fc2_c_tmp_elements = 1\n fc1_cols = (2 if is_gated else 1) * int(n)\n sms = get_num_sm(device)\n # Size the route buffers for the power-of-2 capacity so route packing keeps\n # a single triton specialization across token counts.\n routed_rows_capacity = route_pack_numel_capacity(\n int(routed_rows), topk=int(num_topk)\n )\n for block_size in _W4A16_ALLOWED_ROUTED_SIZES:\n slots = max_packed_route_slots(\n routed_rows_capacity,\n int(block_size),\n int(route_num_experts),\n )\n blocks = (slots + int(block_size) - 1) // int(block_size)\n route_slots = max(route_slots, slots)\n route_blocks = max(route_blocks, blocks)\n fc1_c_tmp_elements = max(\n fc1_c_tmp_elements,\n packed_gemm_scratch_elements(\n size_n=fc1_cols,\n route_slots=slots,\n moe_block_size=int(block_size),\n sms=sms,\n ),\n )\n fc2_c_tmp_elements = max(\n fc2_c_tmp_elements,\n packed_gemm_scratch_elements(\n size_n=int(k),\n route_slots=slots,\n moe_block_size=int(block_size),\n sms=sms,\n ),\n )\n return (\n route_slots,\n route_blocks,\n fc1_c_tmp_elements,\n fc2_c_tmp_elements,\n fc1_cols,\n )\n\n\ndef _make_w4a16_expert_map(\n *,\n state_E: int,\n weight_E: int,\n device: torch.device,\n) -> torch.Tensor | None:\n if int(state_E) == int(weight_E):\n return None\n if int(state_E) > int(weight_E):\n raise ValueError(\"num_local_experts cannot exceed num_experts\")\n expert_map = torch.empty((int(weight_E),), dtype=torch.int32, device=device)\n expert_map.fill_(-1)\n expert_map[: int(state_E)].copy_(\n torch.arange(int(state_E), dtype=torch.int32, device=device)\n )\n return expert_map\n\n\ndef _allocate_sm120_w4a16_workspace(\n *,\n state_E: int,\n weight_E: int,\n routed_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation: str = \"silu\",\n) -> Sm120W4A16MoEWorkspace:\n is_gated = validate_activation(activation)\n routed_rows = max(1, int(routed_rows))\n route_num_experts = int(weight_E) if int(state_E) != int(weight_E) else int(state_E)\n (\n route_slots,\n route_blocks,\n fc1_c_tmp_elements,\n fc2_c_tmp_elements,\n fc1_cols,\n ) = _w4a16_workspace_geometry(\n routed_rows=routed_rows,\n route_num_experts=route_num_experts,\n num_topk=num_topk,\n k=k,\n n=n,\n is_gated=is_gated,\n device=device,\n )\n return Sm120W4A16MoEWorkspace(\n state_E=int(state_E),\n weight_E=int(weight_E),\n max_rows=routed_rows,\n k=int(k),\n n=int(n),\n num_topk=int(num_topk),\n device=device,\n activation=activation,\n activation_precision=\"bf16\",\n quant_mode=\"w4a16\",\n routed_rows_capacity=routed_rows,\n route_num_experts=route_num_experts,\n intermediate_cache13=torch.empty(\n (routed_rows * max(fc1_cols, int(k)),),\n dtype=torch.bfloat16,\n device=device,\n ),\n intermediate_cache2=torch.empty(\n (routed_rows, int(n)),\n dtype=torch.bfloat16,\n device=device,\n ),\n fc1_c_tmp=torch.empty(\n (fc1_c_tmp_elements,),\n dtype=torch.float32,\n device=device,\n ),\n fc2_c_tmp=torch.empty(\n (fc2_c_tmp_elements,),\n dtype=torch.float32,\n device=device,\n ),\n packed_route_indices=torch.empty(\n (route_slots,),\n dtype=torch.int32,\n device=device,\n ),\n block_expert_ids=torch.empty(\n (route_blocks,),\n dtype=torch.int32,\n device=device,\n ),\n packed_route_count=torch.empty((1,), dtype=torch.int32, device=device),\n expert_offsets=torch.empty(\n (route_num_experts + 1,),\n dtype=torch.int32,\n device=device,\n ),\n expert_map=_make_w4a16_expert_map(\n state_E=state_E,\n weight_E=weight_E,\n device=device,\n ),\n )\n\n\n_W4A16_WEIGHT_CACHE: Dict[Tuple, W4A16PackedWeights] = {}\n\n\ndef _get_w4a16_packed_weights(\n *,\n w1_weight: torch.Tensor,\n w1_weight_sf: torch.Tensor,\n w1_alpha: torch.Tensor,\n w2_weight: torch.Tensor,\n w2_weight_sf: torch.Tensor,\n w2_alpha: torch.Tensor,\n activation: str,\n params_dtype: torch.dtype,\n source_format: str = \"modelopt\",\n) -> W4A16PackedWeights:\n key = (\n activation,\n params_dtype,\n source_format,\n tuple(w1_weight.shape),\n tuple(w1_weight_sf.shape),\n tuple(w1_alpha.shape),\n tuple(w2_weight.shape),\n tuple(w2_weight_sf.shape),\n tuple(w2_alpha.shape),\n w1_weight.data_ptr(),\n w1_weight_sf.data_ptr(),\n w1_alpha.data_ptr(),\n w2_weight.data_ptr(),\n w2_weight_sf.data_ptr(),\n w2_alpha.data_ptr(),\n )\n cached = _W4A16_WEIGHT_CACHE.get(key)\n if cached is not None:\n return cached\n if _is_cuda_graph_capturing():\n raise RuntimeError(\n \"W4A16 packed weights are not initialized for CUDA graph capture; \"\n \"run once before capture so the prepared weights are cached.\"\n )\n prepared = prepare_w4a16_packed_weights(\n w1_weight,\n w1_weight_sf,\n w1_alpha,\n w2_weight,\n w2_weight_sf,\n w2_alpha,\n activation=activation,\n params_dtype=params_dtype,\n source_format=source_format,\n )\n _W4A16_WEIGHT_CACHE[key] = prepared\n _register_cache_eviction(\n _W4A16_WEIGHT_CACHE,\n key,\n w1_weight,\n w1_weight_sf,\n w1_alpha,\n w2_weight,\n w2_weight_sf,\n w2_alpha,\n )\n return prepared\n\n\ndef _validate_w4a16_workspace(\n workspace: Sm120W4A16MoEWorkspace,\n *,\n state_E: int,\n weight_E: int,\n routed_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation: str,\n) -> None:\n validate_activation(activation)\n if workspace.state_E != int(state_E) or workspace.weight_E != int(weight_E):\n raise ValueError(\"pre-allocated W4A16 workspace expert geometry mismatch\")\n if workspace.k != int(k) or workspace.n != int(n):\n raise ValueError(\"pre-allocated W4A16 workspace hidden geometry mismatch\")\n if workspace.num_topk != int(num_topk):\n raise ValueError(\"pre-allocated W4A16 workspace top-k mismatch\")\n if getattr(workspace, \"activation\", None) != activation:\n raise ValueError(\"pre-allocated W4A16 workspace activation mismatch\")\n if _canonical_cuda_device(workspace.device) != _canonical_cuda_device(device):\n raise ValueError(\n f\"pre-allocated W4A16 workspace is on {workspace.device}, expected {device}\"\n )\n if workspace.routed_rows_capacity < max(1, int(routed_rows)):\n raise ValueError(\n \"pre-allocated W4A16 workspace is too small for the requested \"\n f\"routed rows ({workspace.routed_rows_capacity} < {routed_rows})\"\n )\n\n\ndef _launch_sm120_w4a16_moe(\n *,\n a: torch.Tensor,\n topk_ids: torch.Tensor,\n topk_weights: torch.Tensor,\n w1_weight: torch.Tensor,\n w1_weight_sf: torch.Tensor,\n w1_alpha: torch.Tensor,\n w2_weight: torch.Tensor,\n w2_weight_sf: torch.Tensor,\n w2_alpha: torch.Tensor,\n num_experts: int,\n top_k: int,\n num_local_experts: int,\n scatter_output: torch.Tensor,\n fast_math: bool = True,\n activation: str = \"silu\",\n source_format: str = \"modelopt\",\n _workspace=None,\n _prepared_weights=None,\n) -> torch.Tensor:\n prepared = (\n _prepared_weights\n if isinstance(_prepared_weights, W4A16PackedWeights)\n else _get_w4a16_packed_weights(\n w1_weight=w1_weight,\n w1_weight_sf=w1_weight_sf,\n w1_alpha=w1_alpha,\n w2_weight=w2_weight,\n w2_weight_sf=w2_weight_sf,\n w2_alpha=w2_alpha,\n activation=activation,\n params_dtype=a.dtype,\n source_format=source_format,\n )\n )\n if int(prepared.num_experts) != int(num_local_experts):\n raise ValueError(\"num_local_experts must match w1_weight.shape[0] for W4A16.\")\n num_tokens = int(topk_ids.size(0))\n routed_rows = num_tokens * int(top_k)\n k = int(a.size(1))\n n = int(prepared.intermediate_size)\n\n if _workspace is None:\n workspace = _get_cached_workspace(\n backend=\"w4a16\",\n state_E=num_local_experts,\n weight_E=num_experts,\n routed_rows=routed_rows,\n k=k,\n n=n,\n num_topk=top_k,\n device=a.device,\n quant_mode=\"w4a16\",\n activation=activation,\n )\n else:\n workspace = _workspace\n if not isinstance(workspace, Sm120W4A16MoEWorkspace):\n raise TypeError(\"expected a W4A16 workspace for quant_mode='w4a16'\")\n _validate_w4a16_workspace(\n workspace,\n state_E=num_local_experts,\n weight_E=num_experts,\n routed_rows=routed_rows,\n k=k,\n n=n,\n num_topk=top_k,\n device=a.device,\n activation=activation,\n )\n\n return run_w4a16_moe(\n a,\n prepared,\n topk_weights,\n topk_ids,\n activation=activation,\n intermediate_cache13=workspace.intermediate_cache13,\n intermediate_cache2=workspace.intermediate_cache2,\n output=scatter_output,\n fc1_c_tmp=workspace.fc1_c_tmp,\n fc2_c_tmp=workspace.fc2_c_tmp,\n packed_route_indices=workspace.packed_route_indices,\n block_expert_ids=workspace.block_expert_ids,\n packed_route_count=workspace.packed_route_count,\n expert_offsets=workspace.expert_offsets,\n expert_map=workspace.expert_map,\n fast_math=fast_math,\n )\n\n\n# ==========================================================================\n# Workspace cache (for functional API path)\n# ==========================================================================\n\n_Sm120Workspace = Union[\n Sm120StaticMoEWorkspace,\n Sm120DynamicMoEWorkspace,\n Sm120W4A16MoEWorkspace,\n]\n\n# Stores the workspace with the largest capacity seen per key and never\n# shrinks within a process. clear_sm120_moe_caches() releases everything.\n_WORKSPACE_CACHE: Dict[Tuple, _Sm120Workspace] = {}\n\n\ndef clear_sm120_moe_caches() -> None:\n \"\"\"Release every module-level SM12x MoE cache.\n\n References held by callers are unaffected.\n \"\"\"\n _WORKSPACE_CACHE.clear()\n _WEIGHT_CACHE.clear()\n _W4A16_WEIGHT_CACHE.clear()\n _PADDED_WEIGHT_CACHE.clear()\n _STATIC_KERNEL_CACHE.clear()\n _MICRO_KERNEL_CACHE.clear()\n _DIRECT_MICRO_LAUNCH_CACHE.clear()\n _DIRECT_MICRO_KERNEL_CACHE.clear()\n _DYNAMIC_KERNEL_CACHE.clear()\n\n\ndef allocate_sm120_moe_workspace(\n *,\n state_E: int,\n weight_E: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n max_rows: int | None = None,\n routed_rows: int | None = None,\n quant_mode: str | None = None,\n activation_precision: str | None = None,\n backend: str | None = None,\n activation: str = \"silu\",\n) -> _Sm120Workspace:\n \"\"\"Allocate the right SM120 MoE workspace from a quantization mode.\"\"\"\n mode = _normalize_quant_mode(quant_mode, activation_precision)\n capacity_rows = routed_rows if routed_rows is not None else max_rows\n if capacity_rows is None:\n raise ValueError(\"routed_rows or max_rows is required\")\n capacity_rows = max(1, int(capacity_rows))\n device = torch.device(device)\n\n if mode == \"w4a16\":\n if backend not in (None, \"w4a16\"):\n raise ValueError(\"quant_mode='w4a16' does not use static/dynamic backend\")\n return _allocate_sm120_w4a16_workspace(\n state_E=state_E,\n weight_E=weight_E,\n routed_rows=capacity_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation=activation,\n )\n\n activation_precision = \"fp4\"\n if backend is None:\n backend = select_sm120_moe_backend(\n num_tokens=max(\n 1, (capacity_rows + max(1, int(num_topk)) - 1) // max(1, int(num_topk))\n ),\n num_topk=int(num_topk),\n activation_precision=activation_precision,\n )\n if backend == \"dynamic\":\n return allocate_sm120_dynamic_workspace(\n state_E=state_E,\n weight_E=weight_E,\n routed_rows=capacity_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation_precision=activation_precision,\n activation=activation,\n )\n if backend == \"static\":\n return allocate_sm120_static_workspace(\n state_E=state_E,\n weight_E=weight_E,\n max_rows=capacity_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation_precision=activation_precision,\n )\n raise ValueError(f\"unsupported SM120 MoE backend {backend!r}\")\n\n\ndef _get_cached_workspace(\n *,\n backend: str,\n state_E: int,\n weight_E: int,\n routed_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation_precision: str = \"fp4\",\n quant_mode: str | None = None,\n activation: str = \"silu\",\n) -> _Sm120Workspace:\n \"\"\"Get or allocate a cached workspace for the given problem shape.\n\n Reuses the cached workspace if it has enough capacity for the requested\n routed_rows. For static workspaces, max_rows is the direct capacity.\n For dynamic workspaces, routed_rows_capacity is used because the dynamic\n geometry (physical tiles, task queue slots) depends on the original\n routed_rows, not just max_rows.\n \"\"\"\n quant_mode = _normalize_quant_mode(quant_mode, activation_precision)\n activation_precision = _activation_precision_from_quant_mode(quant_mode)\n # Key dynamic workspaces on the tile band of this call's routed_rows; a\n # larger cached workspace must not pin small calls to its 128 tile.\n tile_m = (\n _select_dynamic_tile_m(max(1, routed_rows), state_E, activation)\n if backend == \"dynamic\" and quant_mode != \"w4a16\"\n else None\n )\n cache_key = (\n state_E,\n weight_E,\n k,\n n,\n num_topk,\n str(device),\n backend,\n quant_mode,\n activation,\n tile_m,\n )\n cached = _WORKSPACE_CACHE.get(cache_key)\n\n if cached is not None:\n if isinstance(cached, Sm120DynamicMoEWorkspace):\n if cached.routed_rows_capacity >= max(1, routed_rows):\n assert tile_m is None or cached.tile_m == tile_m\n return cached\n elif isinstance(cached, Sm120W4A16MoEWorkspace):\n if cached.routed_rows_capacity >= max(1, routed_rows):\n return cached\n else:\n if cached.max_rows >= max(1, routed_rows):\n return cached\n\n if quant_mode == \"w4a16\" and _is_cuda_graph_capturing():\n raise RuntimeError(\n \"W4A16 workspace is not initialized for CUDA graph capture; \"\n \"provide a preallocated workspace from \"\n \"allocate_sm120_moe_workspace(..., quant_mode='w4a16') or warm the \"\n \"functional path before capture.\"\n )\n workspace = allocate_sm120_moe_workspace(\n state_E=state_E,\n weight_E=weight_E,\n routed_rows=routed_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n quant_mode=quant_mode,\n activation_precision=activation_precision,\n backend=backend,\n activation=activation,\n )\n\n _WORKSPACE_CACHE[cache_key] = workspace\n return workspace\n\n\n# ==========================================================================\n# Unified dispatch\n# ==========================================================================\n_PADDED_WEIGHT_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _pad_intermediate_to_tile(\n w1_weight,\n w1_weight_sf,\n w2_weight,\n w2_weight_sf,\n fc2_input_scale,\n n,\n tile,\n h,\n num_experts,\n is_gated,\n):\n \"\"\"Zero-pad NVFP4 weights + scale factors so the intermediate size is a\n multiple of ``tile`` (gate/up tile-split requirement); padded channels are\n zero, so the result is numerically identical.\n \"\"\"\n n_pad = ((n + tile - 1) // tile) * tile\n if n_pad == n:\n return w1_weight, w1_weight_sf, w2_weight, w2_weight_sf, fc2_input_scale, n\n E = int(num_experts)\n fc2_input_scale_src = fc2_input_scale\n key = (\n n,\n tile,\n h,\n E,\n bool(is_gated),\n w1_weight.data_ptr(),\n w1_weight_sf.data_ptr(),\n w2_weight.data_ptr(),\n w2_weight_sf.data_ptr(),\n fc2_input_scale_src.data_ptr() if fc2_input_scale_src is not None else 0,\n )\n cached = _PADDED_WEIGHT_CACHE.get(key)\n if cached is not None:\n return cached\n\n def mma_to_logical(sf, m, k):\n sw = convert_sf_from_mma_layout(sf, m=m, k=k, num_groups=E)\n m_pad = ((m + 127) // 128) * 128\n sw = sw.reshape(E, m_pad, -1)\n cb = (k + SF_VEC_SIZE - 1) // SF_VEC_SIZE\n return torch.stack(\n [unswizzle_block_scale(sw[e], rows=m, cols_blocks=cb) for e in range(E)], 0\n )\n\n def logical_to_mma(log, m, k):\n sw = torch.stack([swizzle_block_scale(log[e]) for e in range(E)], 0)\n sw2d = sw.reshape(E * sw.shape[1], sw.shape[2]).to(torch.float8_e4m3fn)\n return convert_sf_to_mma_layout(sw2d, m=m, k=k, num_groups=E)\n\n def pad_dim(t, dim, old, new):\n if new == old:\n return t\n shp = list(t.shape)\n shp[dim] = new - old\n return torch.cat([t, t.new_zeros(shp)], dim=dim)\n\n if is_gated:\n # w1 packs [up(0:n), gate(n:2n)] rows; pad each half so the split stays\n # tile-aligned, then re-concat.\n up, gate = w1_weight[:, :n, :], w1_weight[:, n : 2 * n, :]\n w1p = torch.cat([pad_dim(up, 1, n, n_pad), pad_dim(gate, 1, n, n_pad)], dim=1)\n log1 = mma_to_logical(w1_weight_sf, m=2 * n, k=h)\n up_sf, gate_sf = log1[:, :n, :], log1[:, n : 2 * n, :]\n log1p = torch.cat(\n [pad_dim(up_sf, 1, n, n_pad), pad_dim(gate_sf, 1, n, n_pad)], dim=1\n )\n w1_sf_p = logical_to_mma(log1p, m=2 * n_pad, k=h)\n else:\n w1p = pad_dim(w1_weight, 1, n, n_pad)\n log1 = mma_to_logical(w1_weight_sf, m=n, k=h)\n w1_sf_p = logical_to_mma(pad_dim(log1, 1, n, n_pad), m=n_pad, k=h)\n\n # w2 reduces over the intermediate dim: pad its packed columns + SF columns.\n w2p = pad_dim(w2_weight, 2, n // 2, n_pad // 2)\n log2 = mma_to_logical(w2_weight_sf, m=h, k=n)\n cb_n = (n + SF_VEC_SIZE - 1) // SF_VEC_SIZE\n cb_np = (n_pad + SF_VEC_SIZE - 1) // SF_VEC_SIZE\n w2_sf_p = logical_to_mma(pad_dim(log2, 2, cb_n, cb_np), m=h, k=n_pad)\n\n if fc2_input_scale_src is not None and fc2_input_scale_src.numel() == n:\n fc2_input_scale = pad_dim(fc2_input_scale_src, 0, n, n_pad)\n result = (w1p, w1_sf_p, w2p, w2_sf_p, fc2_input_scale, n_pad)\n _PADDED_WEIGHT_CACHE[key] = result\n _register_cache_eviction(\n _PADDED_WEIGHT_CACHE,\n key,\n w1_weight,\n w1_weight_sf,\n w2_weight,\n w2_weight_sf,\n fc2_input_scale_src,\n )\n return result\n\n\ndef launch_sm120_moe(\n *,\n a: torch.Tensor,\n topk_ids: torch.Tensor,\n topk_weights: torch.Tensor,\n w1_weight: torch.Tensor,\n w1_weight_sf: torch.Tensor,\n w1_alpha: torch.Tensor,\n fc2_input_scale: Optional[torch.Tensor] = None,\n input_global_scale: Optional[torch.Tensor] = None,\n w2_weight: torch.Tensor,\n w2_weight_sf: torch.Tensor,\n w2_alpha: torch.Tensor,\n num_experts: int,\n top_k: int,\n num_local_experts: int,\n scatter_output: torch.Tensor,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n quant_mode: str | None = None,\n source_format: str = \"modelopt\",\n _workspace=None,\n _weight_views=None,\n _prepared_weights=None,\n) -> torch.Tensor:\n \"\"\"Unified SM120 MoE dispatch — selects static or dynamic by token count.\n\n input_global_scale overrides w1_alpha as the FC1 input-quant scale and\n is folded into the multiplier internally. With _weight_views supplied,\n w1_alpha must already contain the fold.\n\n Optional _workspace and _weight_views can be pre-allocated and reused\n across calls to avoid per-call allocation overhead (wrapper path).\n When not provided (functional API path), a module-level workspace cache\n is used to avoid re-allocating on every call.\n \"\"\"\n quant_mode = _normalize_quant_mode(quant_mode, activation_precision)\n source_format = _normalize_source_format_for_quant_mode(source_format, quant_mode)\n activation_precision = _activation_precision_from_quant_mode(quant_mode)\n\n num_tokens = topk_ids.size(0)\n k = a.size(1) # hidden_size\n is_gated = is_gated_activation(activation)\n # w1_weight.size(1) is 2*n for gated or n for non-gated\n intermediate_size = w1_weight.size(1) // 2 if is_gated else w1_weight.size(1)\n n = intermediate_size\n\n # NVFP4 kernels need padded intermediate size.\n if quant_mode != \"w4a16\" and n % _LEVEL_TILE_N != 0 and _weight_views is None:\n (\n w1_weight,\n w1_weight_sf,\n w2_weight,\n w2_weight_sf,\n fc2_input_scale,\n n,\n ) = _pad_intermediate_to_tile(\n w1_weight,\n w1_weight_sf,\n w2_weight,\n w2_weight_sf,\n fc2_input_scale,\n n,\n _LEVEL_TILE_N,\n k,\n w1_weight.size(0),\n is_gated,\n )\n\n routed_rows = num_tokens * top_k\n\n if quant_mode == \"w4a16\":\n return _launch_sm120_w4a16_moe(\n a=a,\n topk_ids=topk_ids,\n topk_weights=topk_weights,\n w1_weight=w1_weight,\n w1_weight_sf=w1_weight_sf,\n w1_alpha=w1_alpha,\n w2_weight=w2_weight,\n w2_weight_sf=w2_weight_sf,\n w2_alpha=w2_alpha,\n num_experts=num_experts,\n top_k=top_k,\n num_local_experts=num_local_experts,\n scatter_output=scatter_output,\n fast_math=fast_math,\n activation=activation,\n source_format=source_format,\n _workspace=_workspace,\n _prepared_weights=_prepared_weights,\n )\n\n if fc2_input_scale is None:\n raise ValueError(\"fc2_input_scale is required when quant_mode='nvfp4'.\")\n down_input_scale = fc2_input_scale\n if input_global_scale is not None:\n input_gs = input_global_scale\n if _weight_views is None:\n # Alpha must carry input_gs back or the output magnitude is wrong.\n # The wrapper folds before building _weight_views; don't fold twice.\n w1_alpha = (\n w1_alpha.to(torch.float32) * input_global_scale.to(torch.float32)\n ).contiguous()\n else:\n input_gs = w1_alpha\n\n weights = (\n _weight_views\n if _weight_views is not None\n else _get_weight_views(\n w1_fp4=w1_weight,\n w1_blockscale=w1_weight_sf,\n w2_fp4=w2_weight,\n w2_blockscale=w2_weight_sf,\n w1_alphas=w1_alpha,\n w2_alphas=w2_alpha,\n n=n,\n k=k,\n activation_precision=activation_precision,\n )\n )\n\n # Resolve workspace and backend selection.\n # When a pre-allocated workspace is provided (CUDA graph wrapper path),\n # infer the backend from the workspace type so they stay in sync —\n # the caller already committed to a backend at allocation time.\n if _workspace is not None:\n workspace = _workspace\n workspace_activation_precision = getattr(\n workspace, \"activation_precision\", activation_precision\n )\n if workspace_activation_precision != activation_precision:\n raise ValueError(\n \"pre-allocated workspace activation_precision does not match \"\n f\"requested activation_precision={activation_precision!r}.\"\n )\n if isinstance(workspace, Sm120DynamicMoEWorkspace):\n if num_local_experts != num_experts:\n raise ValueError(\n \"pre-allocated dynamic SM120 MoE workspace requires \"\n \"num_local_experts == num_experts because dynamic expert \"\n \"buffers are indexed by global topk ids.\"\n )\n # A pre-allocated dynamic workspace keeps its stored tile_m even\n # for smaller calls; its geometry was sized for that tile.\n backend = \"dynamic\"\n else:\n backend = \"static\"\n else:\n backend = select_sm120_moe_backend(\n num_tokens=num_tokens,\n num_topk=top_k,\n activation_precision=activation_precision,\n )\n # The dynamic kernel indexes row_counts/expert_write_rows directly with\n # topk_ids but those buffers are sized with num_local_experts. Unless\n # num_local_experts == num_experts, fall back to the static backend which\n # has global-to-local expert remapping.\n if backend == \"dynamic\" and num_local_experts != num_experts:\n backend = \"static\"\n workspace = _get_cached_workspace(\n backend=backend,\n state_E=num_local_experts,\n weight_E=num_experts,\n routed_rows=routed_rows,\n k=k,\n n=n,\n num_topk=top_k,\n device=a.device,\n activation_precision=activation_precision,\n quant_mode=quant_mode,\n activation=activation,\n )\n\n if backend == \"dynamic\":\n return launch_sm120_dynamic_moe(\n workspace=workspace,\n weights=weights,\n a=a,\n topk_ids=topk_ids,\n topk_weights=topk_weights,\n input_gs=input_gs,\n down_input_scale=down_input_scale,\n scatter_output=scatter_output,\n num_experts=num_experts,\n num_tokens=num_tokens,\n k=k,\n n=n,\n top_k=top_k,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n activation_precision=activation_precision,\n )\n else:\n return launch_sm120_static_moe(\n workspace=workspace,\n weights=weights,\n a=a,\n topk_ids=topk_ids,\n topk_weights=topk_weights,\n input_gs=input_gs,\n down_input_scale=down_input_scale,\n scatter_output=scatter_output,\n num_experts=num_experts,\n num_tokens=num_tokens,\n k=k,\n n=n,\n top_k=top_k,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n activation_precision=activation_precision,\n )\n"},"after_code":{"kind":"string","value":"\"\"\"SM120/SM121 MoE dispatch layer — workspace, compilation, and launch.\n\nPorted from b12x's integration/tp_moe.py. Supports micro (tiny decode),\nstatic (decode), and dynamic (prefill) backends with token-count-based\nselection.\n\"\"\"\n\nfrom __future__ import annotations\n\nimport os\nimport weakref\nfrom dataclasses import dataclass\nfrom typing import Any, Dict, Optional, Tuple, Union\n\nimport cutlass\nimport cutlass.cute as cute\nimport torch\n\nfrom flashinfer.cute_dsl.utils import (\n convert_sf_from_mma_layout,\n convert_sf_to_mma_layout,\n current_cuda_stream,\n get_max_active_clusters,\n get_num_sm,\n make_ptr,\n)\nfrom .moe_activation import SWIGLUOAI_UNINTERLEAVE, is_gated_activation\nfrom .moe_direct_micro_kernel import (\n MoEDirectMicroKernel,\n build_direct_micro_kernel,\n compile_direct_micro_kernel,\n compiled_direct_micro_accepts_block_dim,\n)\nfrom .moe_dynamic_kernel import (\n _MAX_SHARED_INPUT_TOPK,\n _TASK_SLICE_CHUNK,\n MoEDynamicKernel,\n)\nfrom .moe_micro_kernel import MoEMicroKernel\nfrom .moe_static_kernel import MoEStaticKernel\nfrom .moe_w4a16_fp4_helpers import swizzle_block_scale\nfrom .moe_w4a16_host import (\n _W4A16_ALLOWED_ROUTED_SIZES,\n max_packed_route_slots,\n packed_gemm_scratch_elements,\n route_pack_numel_capacity,\n unswizzle_block_scale,\n validate_activation,\n)\nfrom .moe_w4a16_kernel import run_w4a16_moe\nfrom .moe_w4a16_prepare import (\n W4A16PackedWeights,\n _normalize_source_format,\n prepare_w4a16_packed_weights,\n)\n\n# ---------------------------------------------------------------------------\n# Constants\n# ---------------------------------------------------------------------------\n_NVFP4_BLOCK_SIZE = 16\n_LEVEL_TILE_M = 128\n_LEVEL_TILE_N = 128\n# Must equal the kernel's task materialization granularity or the task\n# queue is mis-sized.\n_DYNAMIC_SLICE_CHUNK = _TASK_SLICE_CHUNK\nSF_VEC_SIZE = 16\n_FORCE_MOE_W4A16_ENV = \"FLASHINFER_B12X_FORCE_MOE_W4A16\"\n_MICRO_SHARE_INPUT_ACROSS_EXPERTS = (\n os.environ.get(\"FLASHINFER_B12X_MICRO_SHARE_INPUT\", \"1\") != \"0\"\n)\n\n# Micro kernel cutover thresholds (routed pairs)\n_MICRO_COMPACT_CUTOVER_PAIRS = 20\n_MICRO_COMPACT_CUTOVER_PAIRS_MULTI_TOPK = 40\n# The micro kernel's per-token staging assumes decode-sized batches.\n_MICRO_MAX_TOKENS = 8\n# Direct micro takes the smallest decode batches ahead of the MMA micro\n# kernel, and only at small intermediate sizes where its CUDA-core dots\n# keep up with per-token work. Measured on GB10, pending other GPUs.\n_DIRECT_MICRO_CUTOVER_PAIRS = 32\n_DIRECT_MICRO_MAX_N = 512\n# Test/bench hook: force one backend (\"direct_micro\", \"micro\", \"static\",\n# \"dynamic\"). Deliberately module-level (a monkeypatch target), not an env var.\n_FORCED_BACKEND: str | None = None\n_STATIC_COMPACT_CUTOVER_PAIRS_DEFAULT = 640\n_STATIC_COMPACT_CUTOVER_PAIRS = _STATIC_COMPACT_CUTOVER_PAIRS_DEFAULT\n_STATIC_COMPACT_CUTOVER_PAIRS_CACHE: Dict[str, int] = {}\n\n# MAC (max active clusters) tuning ladders from b12x decode profiling.\n# Each entry is (max_routed_rows, optimal_mac).\n_MICRO_MAC_LADDER: Tuple[Tuple[int, int], ...] = (\n (2, 84),\n (4, 127),\n (8, 107),\n (10, 84),\n (16, 63),\n (20, 84),\n)\n_STATIC_MAC_LADDER: Tuple[Tuple[int, int], ...] = (\n (24, 148),\n (32, 169),\n (40, 132),\n (48, 149),\n (64, 134),\n (80, 175),\n (96, 171),\n (120, 125),\n (128, 130),\n (160, 171),\n (192, 166),\n (256, 141),\n (320, 158),\n (512, 175),\n (640, 188),\n)\n# Workloads at or below the static cutover (640 routed pairs by default)\n# take the static kernel, so only the 1024 entry is normally reachable.\n_DYNAMIC_MAC_LADDER: Tuple[Tuple[int, int], ...] = (\n (640, 188),\n (1024, 147),\n)\n\n\ndef _lookup_mac_ladder(\n ladder: Tuple[Tuple[int, int], ...], routed_rows: int\n) -> int | None:\n \"\"\"Look up optimal MAC from a tuning ladder. Returns None if no match.\"\"\"\n for end_rows, mac in ladder:\n if routed_rows <= end_rows:\n return mac\n return None\n\n\ndef _align_up(value: int, alignment: int) -> int:\n return ((value + alignment - 1) // alignment) * alignment\n\n\n# The kernels index the packed activation and scale planes with 32-bit\n# offsets, so reject any workspace plane large enough to overflow them.\n_RUNTIME_MEMREF_LIMIT = (1 << 31) - 1\n\n\ndef _check_memref_limit(name: str, elements: int) -> None:\n if elements > _RUNTIME_MEMREF_LIMIT:\n raise ValueError(\n f\"{name} needs {elements} elements, which exceeds the 2^31-1 \"\n \"runtime memref limit. Reduce the token chunk or expert count \"\n \"for this launch.\"\n )\n\n\ndef _first_env(*names: str) -> str | None:\n for name in names:\n value = os.environ.get(name)\n if value is not None:\n return value\n return None\n\n\ndef _normalize_activation_precision(activation_precision: str) -> str:\n \"\"\"Normalize public activation-precision names to internal modes.\"\"\"\n if os.environ.get(_FORCE_MOE_W4A16_ENV, \"0\") == \"1\":\n return \"bf16\"\n\n normalized = str(activation_precision).lower()\n aliases = {\n \"fp4\": \"fp4\",\n \"nvfp4\": \"fp4\",\n \"w4a4\": \"fp4\",\n \"bf16\": \"bf16\",\n \"w4a16\": \"bf16\",\n }\n try:\n return aliases[normalized]\n except KeyError as exc:\n raise ValueError(\n \"activation_precision must be 'fp4' or 'bf16' \"\n f\"(got {activation_precision!r}).\"\n ) from exc\n\n\ndef _normalize_quant_mode(\n quant_mode: str | None = None,\n activation_precision: str | None = None,\n) -> str:\n \"\"\"Normalize public quantization names to the dispatch mode.\"\"\"\n if os.environ.get(_FORCE_MOE_W4A16_ENV, \"0\") == \"1\":\n return \"w4a16\"\n if quant_mode is None:\n activation_precision = _normalize_activation_precision(\n activation_precision or \"fp4\"\n )\n return \"w4a16\" if activation_precision == \"bf16\" else \"nvfp4\"\n\n normalized = str(quant_mode).lower()\n aliases = {\n \"fp4\": \"nvfp4\",\n \"nvfp4\": \"nvfp4\",\n \"w4a4\": \"nvfp4\",\n \"bf16\": \"w4a16\",\n \"w4a16\": \"w4a16\",\n }\n try:\n return aliases[normalized]\n except KeyError as exc:\n raise ValueError(\n f\"quant_mode must be 'nvfp4'/'w4a4' or 'w4a16' (got {quant_mode!r}).\"\n ) from exc\n\n\ndef _activation_precision_from_quant_mode(quant_mode: str) -> str:\n return \"bf16\" if _normalize_quant_mode(quant_mode) == \"w4a16\" else \"fp4\"\n\n\ndef _normalize_source_format_for_quant_mode(source_format: str, quant_mode: str) -> str:\n normalized = _normalize_source_format(source_format)\n if quant_mode == \"nvfp4\" and normalized == \"compressed_tensors\":\n raise ValueError(\n \"source_format='compressed_tensors' requires quant_mode='w4a16'.\"\n )\n return normalized\n\n\ndef _is_w4a16(activation_precision: str) -> bool:\n return _normalize_activation_precision(activation_precision) == \"bf16\"\n\n\ndef _level_tile_n(activation_precision: str = \"fp4\") -> int:\n if _is_w4a16(activation_precision):\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 tile selector\"\n )\n return _LEVEL_TILE_N\n\n\ndef _select_dynamic_tile_m(\n routed_rows: int,\n num_experts: int,\n activation: str = \"silu\",\n) -> int:\n \"\"\"Pick the dynamic kernel's M-tile from routed rows per expert.\n\n Small tiles cut per-expert tail padding for sparse routing; 128 amortizes\n best for dense prefill (crossovers measured on gated NVFP4). Workspace\n sizing and the kernel build must both derive the tile from this function,\n or the scratch is mis-sized for what the kernel indexes.\n \"\"\"\n if not is_gated_activation(activation):\n return _LEVEL_TILE_M\n routed_rows = max(1, int(routed_rows))\n num_experts = max(1, int(num_experts))\n if routed_rows < 15 * num_experts:\n return 16\n if routed_rows < 48 * num_experts:\n return 32\n if routed_rows < 96 * num_experts:\n return 64\n return _LEVEL_TILE_M\n\n\ndef _get_static_compact_cutover_pairs(activation_precision: str = \"fp4\") -> int:\n activation_precision = _normalize_activation_precision(activation_precision)\n cached = _STATIC_COMPACT_CUTOVER_PAIRS_CACHE.get(activation_precision)\n if cached is not None:\n return cached\n\n cutover_names: tuple[str, ...] = (\n \"FLASHINFER_B12X_STATIC_COMPACT_CUTOVER_PAIRS\",\n \"B12X_STATIC_COMPACT_CUTOVER_PAIRS\",\n \"B12X_DYNAMIC_STATIC_CUTOVER_PAIRS\",\n \"B12X_LEVEL10_STATIC_CUTOVER_PAIRS\",\n )\n cutover = _first_env(*cutover_names)\n if cutover is None:\n cached = _STATIC_COMPACT_CUTOVER_PAIRS_DEFAULT\n else:\n cached = max(0, int(cutover))\n _STATIC_COMPACT_CUTOVER_PAIRS_CACHE[activation_precision] = cached\n return cached\n\n\ndef _select_moe_mma_tiler_mn(\n routed_rows: int,\n n: int,\n *,\n resident_clusters: int | None = None,\n) -> Tuple[int, int]:\n \"\"\"Select optimal MoE tile shape based on routed rows and N dimension.\n\n Uses narrower 64x128 tiles when routed_rows <= 128 and default 128x128\n would leave SMs idle.\n \"\"\"\n sm_count = get_num_sm(torch.device(\"cuda\"))\n coarse_tile = (128, 128)\n if routed_rows <= 32 and n <= 256:\n return (64, 128)\n if resident_clusters is not None and resident_clusters < sm_count:\n return coarse_tile\n coarse_tiles = ((routed_rows + coarse_tile[0] - 1) // coarse_tile[0]) * (\n (n + coarse_tile[1] - 1) // coarse_tile[1]\n )\n # Single-token decode often lands exactly on the \"half the machine\"\n # boundary. Keeping the coarse 128x128 tile there leaves the M dimension\n # badly underfilled, so take the narrow 64x128 tile inclusive of equality.\n if routed_rows <= 64 or (\n routed_rows <= 128 and coarse_tiles <= max(1, sm_count // 2)\n ):\n return (64, 128)\n return (128, 128)\n\n\ndef _as_grouped_scale_view(\n scale_storage: torch.Tensor,\n rows: int,\n cols: int,\n) -> torch.Tensor:\n \"\"\"Create 6D MMA-compatible scale factor view from swizzled storage.\"\"\"\n batch = scale_storage.shape[0]\n rows_padded = _align_up(rows, 128)\n cols_padded = _align_up(cols // SF_VEC_SIZE, 4)\n sf = scale_storage.view(torch.float8_e4m3fn)\n sf = sf.view(batch, rows_padded // 128, cols_padded // 4, 32, 4, 4)\n return sf.permute(3, 4, 1, 5, 2, 0)\n\n\n# ---------------------------------------------------------------------------\n# Workspace\n# ---------------------------------------------------------------------------\n@dataclass(kw_only=True)\nclass Sm120StaticMoEWorkspace:\n \"\"\"Scratch buffers for one SM120 static MoE launch.\"\"\"\n\n state_E: int\n weight_E: int\n max_rows: int\n k: int\n n: int\n num_topk: int\n device: torch.device\n activation_precision: str\n\n # Buffers\n row_counts: torch.Tensor # [state_E] int32\n token_map: torch.Tensor # [state_E, max_rows] int32\n token_weights: torch.Tensor # [state_E, max_rows] float32\n packed_input: torch.Tensor # [state_E, max_rows, k//2] uint8\n packed_input_scale: torch.Tensor # [state_E, rows_pad_k, cols_pad_k] uint8\n barrier_count: torch.Tensor # [1] int32\n barrier_epoch: torch.Tensor # [1] int32\n active_expert_count: torch.Tensor # [1] int32\n weight_expert_ids: torch.Tensor # [state_E] int32\n global_to_local_expert: torch.Tensor # [weight_E] int32\n compact_topk_ids: torch.Tensor # [state_E] int32, for micro kernel pre-pass\n\n # Views (set after allocation)\n packed_a_view: torch.Tensor | None = None\n sfa_ptr: object = None\n packed_a_flat: torch.Tensor | None = None\n scale_flat: torch.Tensor | None = None\n\n # Direct micro planes (allocated only when the shape can take that path).\n dm_barrier_count: torch.Tensor | None = None\n dm_barrier_epoch: torch.Tensor | None = None\n dm_intermediate: torch.Tensor | None = None\n dm_input_gs: torch.Tensor | None = None\n dm_down_input_scale: torch.Tensor | None = None\n\n\ndef _direct_micro_candidate(k: int, n: int, num_topk: int, weight_E: int) -> bool:\n \"\"\"Whether any m in the tiny-decode band can run the direct micro kernel.\"\"\"\n return any(\n MoEDirectMicroKernel.is_supported(m, k, n, num_topk, weight_E)\n for m in range(1, _MICRO_MAX_TOKENS + 1)\n )\n\n\ndef allocate_sm120_static_workspace(\n *,\n state_E: int,\n weight_E: int,\n max_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation_precision: str = \"fp4\",\n) -> Sm120StaticMoEWorkspace:\n \"\"\"Allocate workspace buffers for the SM120 static MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"allocate_sm120_static_workspace only supports quant_mode='nvfp4'; \"\n \"use allocate_sm120_moe_workspace(..., quant_mode='w4a16') for W4A16.\"\n )\n\n rows_pad_k = _align_up(max_rows, 128)\n cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n _check_memref_limit(\"static packed_input\", state_E * max_rows * (k // 2))\n _check_memref_limit(\"static packed_input_scale\", state_E * rows_pad_k * cols_pad_k)\n packed_input = torch.empty(\n state_E, max_rows, k // 2, dtype=torch.uint8, device=device\n )\n\n workspace = Sm120StaticMoEWorkspace(\n state_E=state_E,\n weight_E=weight_E,\n max_rows=max_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation_precision=activation_precision,\n row_counts=torch.zeros(state_E, dtype=torch.int32, device=device),\n token_map=torch.zeros(state_E, max_rows, dtype=torch.int32, device=device),\n token_weights=torch.zeros(\n state_E, max_rows, dtype=torch.float32, device=device\n ),\n packed_input=packed_input,\n packed_input_scale=torch.empty(\n state_E, rows_pad_k, cols_pad_k, dtype=torch.uint8, device=device\n ),\n barrier_count=torch.zeros(1, dtype=torch.int32, device=device),\n barrier_epoch=torch.zeros(1, dtype=torch.int32, device=device),\n active_expert_count=torch.zeros(1, dtype=torch.int32, device=device),\n weight_expert_ids=torch.arange(state_E, dtype=torch.int32, device=device),\n global_to_local_expert=torch.empty(weight_E, dtype=torch.int32, device=device),\n compact_topk_ids=torch.empty(\n max(state_E, max_rows), dtype=torch.int32, device=device\n ),\n )\n\n # Finalize views\n sf_dtype = cutlass.Float8E4M3FN\n workspace.packed_a_view = workspace.packed_input.permute(1, 2, 0).view(\n torch.float4_e2m1fn_x2\n )\n workspace.packed_a_flat = workspace.packed_input.view(-1)\n workspace.scale_flat = workspace.packed_input_scale.view(-1)\n workspace.sfa_ptr = make_ptr(\n sf_dtype,\n workspace.packed_input_scale.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n\n # Direct micro reads weights by global expert id, so its planes are only\n # useful without EP remapping.\n if state_E == weight_E and _direct_micro_candidate(k, n, num_topk, weight_E):\n dm_rows = min(max_rows, _MICRO_MAX_TOKENS * num_topk)\n # The epoch-based barriers restore their slots after each launch, so\n # the zeroed allocation is the only reset needed (graph-replay safe).\n dm_slots = dm_rows + _MICRO_MAX_TOKENS * 16\n fc2_n_chunks = (n // 2 + 127) // 128\n # The fused kernel binds the intermediate as m * num_topk *\n # fc2_n_chunks * 128 u32 words; size for the largest supported m.\n dm_inter = _MICRO_MAX_TOKENS * num_topk * fc2_n_chunks * 128\n workspace.dm_barrier_count = torch.zeros(\n dm_slots, dtype=torch.int32, device=device\n )\n workspace.dm_barrier_epoch = torch.zeros(\n dm_slots, dtype=torch.int32, device=device\n )\n workspace.dm_intermediate = torch.empty(\n dm_inter, dtype=torch.float32, device=device\n )\n workspace.dm_input_gs = torch.empty(\n weight_E, dtype=torch.float32, device=device\n )\n workspace.dm_down_input_scale = torch.empty(\n weight_E, dtype=torch.float32, device=device\n )\n return workspace\n\n\n# ---------------------------------------------------------------------------\n# Weight views\n# ---------------------------------------------------------------------------\n@dataclass\nclass _WeightViews:\n w13_fp4: object = None\n down_fp4: object = None\n sfb_w13_ptr: object = None\n sfb_down_ptr: object = None\n w1_alpha: torch.Tensor | None = None\n w2_alpha: torch.Tensor | None = None\n w1_storage: torch.Tensor | None = None\n w1_scale_storage: torch.Tensor | None = None\n w2_storage: torch.Tensor | None = None\n w2_scale_storage: torch.Tensor | None = None\n _w13_sf_storage: torch.Tensor | None = None\n _down_sf_storage: torch.Tensor | None = None\n\n\ndef _register_cache_eviction(cache: Dict, key: Tuple, *source_tensors) -> None:\n \"\"\"Evict ``key`` when a source weight tensor is collected, so the cache\n follows the weights' lifetime instead of growing for the whole process.\n \"\"\"\n for tensor in source_tensors:\n if tensor is not None:\n weakref.finalize(tensor, cache.pop, key, None)\n\n\n_WEIGHT_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_weight_views(\n w1_fp4: torch.Tensor,\n w1_blockscale: torch.Tensor,\n w2_fp4: torch.Tensor,\n w2_blockscale: torch.Tensor,\n w1_alphas: torch.Tensor,\n w2_alphas: torch.Tensor,\n n: int,\n k: int,\n activation_precision: str = \"fp4\",\n) -> _WeightViews:\n \"\"\"Create permuted weight views for the static kernel.\n\n The kernel expects concatenated w13 data with shape [2*n, k//2, E]\n via a single TMA descriptor.\n \"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n tile_n = _level_tile_n(activation_precision)\n # The kernel splits w13 into gate/up halves by tile index. This only works\n # when the boundary between halves lands on a tile-aligned column.\n if n % tile_n != 0:\n raise ValueError(\n f\"intermediate_size ({n}) must be a multiple of {tile_n} \"\n f\"for the SM120 MoE kernel's gate/up tile split.\"\n )\n\n key = (\n activation_precision,\n w1_fp4.data_ptr(),\n w1_blockscale.data_ptr(),\n w1_alphas.data_ptr(),\n w2_fp4.data_ptr(),\n w2_blockscale.data_ptr(),\n w2_alphas.data_ptr(),\n )\n cached = _WEIGHT_CACHE.get(key)\n if cached is None:\n # Cache the fresh buffers (scale factors + fp32 alphas).\n w1_rows = w1_fp4.shape[1] # 2*n for gated, n for non-gated\n cached = (\n convert_sf_from_mma_layout(\n w1_blockscale, m=w1_rows, k=k, num_groups=w1_fp4.shape[0]\n ).contiguous(),\n convert_sf_from_mma_layout(\n w2_blockscale, m=k, k=n, num_groups=w2_fp4.shape[0]\n ).contiguous(),\n w1_alphas.contiguous().to(torch.float32),\n w2_alphas.contiguous().to(torch.float32),\n )\n _WEIGHT_CACHE[key] = cached\n _register_cache_eviction(\n _WEIGHT_CACHE,\n key,\n w1_fp4,\n w1_blockscale,\n w1_alphas,\n w2_fp4,\n w2_blockscale,\n w2_alphas,\n )\n w13_sf_contiguous, down_sf_contiguous, w1_alpha, w2_alpha = cached\n\n # Permute [E, w1_rows, k//2] -> [w1_rows, k//2, E] (view, no copy).\n sf_dtype = cutlass.Float8E4M3FN\n w13 = w1_fp4.permute(1, 2, 0)\n down = w2_fp4.permute(1, 2, 0)\n return _WeightViews(\n w13_fp4=w13.view(torch.float4_e2m1fn_x2),\n down_fp4=down.view(torch.float4_e2m1fn_x2),\n sfb_w13_ptr=make_ptr(\n sf_dtype,\n w13_sf_contiguous.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n ),\n sfb_down_ptr=make_ptr(\n sf_dtype,\n down_sf_contiguous.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n ),\n w1_alpha=w1_alpha,\n w2_alpha=w2_alpha,\n w1_storage=w1_fp4,\n w1_scale_storage=w13_sf_contiguous,\n w2_storage=w2_fp4,\n w2_scale_storage=down_sf_contiguous,\n _w13_sf_storage=w13_sf_contiguous,\n _down_sf_storage=down_sf_contiguous,\n )\n\n\n# ---------------------------------------------------------------------------\n# Kernel compilation cache\n# ---------------------------------------------------------------------------\n_STATIC_KERNEL_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_static_kernel(\n state_E: int,\n weight_E: int,\n m: int,\n k: int,\n n: int,\n num_topk: int,\n max_rows: int,\n *,\n topk_ids_dtype: torch.dtype = torch.int32,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n mac_override: int | None = None,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n):\n \"\"\"Compile (or retrieve cached) the SM120 static MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 static compiler\"\n )\n sf_vec_size = 16\n sm_count = get_num_sm(torch.device(\"cuda\"))\n mac = (\n mac_override\n if mac_override is not None\n else min(get_max_active_clusters(1), sm_count)\n )\n\n # Select tile size based on actual routed rows\n routed_rows = m * num_topk\n mma_tiler_mn = (128, 128)\n if activation_precision == \"fp4\" and num_topk > 1:\n mma_tiler_mn = _select_moe_mma_tiler_mn(routed_rows, n, resident_clusters=mac)\n\n cache_key = (\n \"static\",\n activation_precision,\n state_E,\n weight_E,\n m,\n k,\n n,\n num_topk,\n max_rows,\n mac,\n mma_tiler_mn,\n topk_ids_dtype,\n input_scales_are_reciprocal,\n fast_math,\n activation,\n swiglu_alpha,\n swiglu_beta,\n swiglu_limit,\n )\n cached = _STATIC_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n return cached\n\n ab_dtype = cutlass.Float4E2M1FN\n weight_dtype = cutlass.Float4E2M1FN\n sf_dtype = cutlass.Float8E4M3FN\n a_dtype = cutlass.BFloat16\n alpha_dtype = cutlass.Float32\n\n output_tile_count_n = max(1, (n + mma_tiler_mn[1] - 1) // mma_tiler_mn[1])\n kernel: Any = MoEStaticKernel(\n sf_vec_size=sf_vec_size,\n mma_tiler_mn=mma_tiler_mn,\n output_tile_count_n=output_tile_count_n,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n )\n\n is_gated = is_gated_activation(activation)\n w1_rows = (2 if is_gated else 1) * n # 2*n for gated, n for non-gated\n\n rows_pad_k = _align_up(max_rows, 128)\n cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n\n # Build fake tensors for compilation\n a_input_fake = cute.runtime.make_fake_compact_tensor(\n a_dtype,\n (m, k),\n stride_order=(1, 0),\n assumed_align=16,\n )\n topk_ids_cutlass_dtype = (\n cutlass.Int32 if topk_ids_dtype == torch.int32 else cutlass.Int64\n )\n topk_ids_align = 4 if topk_ids_dtype == torch.int32 else 8\n topk_ids_fake = cute.runtime.make_fake_compact_tensor(\n topk_ids_cutlass_dtype,\n (m * num_topk,),\n assumed_align=topk_ids_align,\n )\n topk_weights_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32,\n (m * num_topk,),\n assumed_align=4,\n )\n packed_a_fake = cute.runtime.make_fake_compact_tensor(\n ab_dtype,\n (max_rows, k, state_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfa_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n packed_a_storage_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (state_E * max_rows * (k // 2),),\n assumed_align=16,\n )\n scale_storage_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (state_E * rows_pad_k * cols_pad_k,),\n assumed_align=16,\n )\n barrier_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n barrier_epoch_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n b_w13_fake = cute.runtime.make_fake_compact_tensor(\n weight_dtype,\n (w1_rows, k, weight_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_w13_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n b_down_fake = cute.runtime.make_fake_compact_tensor(\n weight_dtype,\n (k, n, weight_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_down_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n row_counts_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E,),\n assumed_align=4,\n )\n active_expert_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n weight_expert_ids_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E,),\n assumed_align=4,\n )\n global_to_local_expert_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (weight_E,),\n assumed_align=4,\n )\n input_gs_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n down_alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n global_scale_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n scatter_fake = cute.runtime.make_fake_compact_tensor(\n a_dtype,\n (m, k),\n stride_order=(1, 0),\n assumed_align=16,\n )\n token_map_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E, max_rows),\n stride_order=(1, 0),\n assumed_align=4,\n )\n token_weights_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (state_E, max_rows),\n stride_order=(1, 0),\n assumed_align=16,\n )\n compiled = cute.compile(\n kernel,\n a_input_fake,\n topk_ids_fake,\n topk_weights_fake,\n packed_a_fake,\n sfa_fake,\n packed_a_storage_fake,\n scale_storage_fake,\n barrier_count_fake,\n barrier_epoch_fake,\n b_w13_fake,\n sfb_w13_fake,\n b_down_fake,\n sfb_down_fake,\n row_counts_fake,\n active_expert_count_fake,\n weight_expert_ids_fake,\n global_to_local_expert_fake,\n input_gs_fake,\n alpha_fake,\n down_alpha_fake,\n global_scale_fake,\n scatter_fake,\n token_map_fake,\n token_weights_fake,\n mac,\n current_cuda_stream(),\n options=\"--opt-level 2 --enable-tvm-ffi\",\n )\n\n result = (compiled, mac)\n _STATIC_KERNEL_CACHE[cache_key] = result\n return result\n\n\n_MICRO_KERNEL_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_micro_kernel(\n state_E: int,\n weight_E: int,\n m: int,\n k: int,\n n: int,\n num_topk: int,\n max_rows: int,\n *,\n topk_ids_dtype: torch.dtype = torch.int32,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n share_input_across_experts: bool = False,\n share_expert_scales: bool = False,\n single_token: bool = False,\n mac_override: int | None = None,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n):\n \"\"\"Compile (or retrieve cached) the SM120 micro MoE kernel.\"\"\"\n sf_vec_size = 16\n sm_count = get_num_sm(torch.device(\"cuda\"))\n mac = (\n mac_override\n if mac_override is not None\n else min(get_max_active_clusters(1), sm_count)\n )\n\n # Micro always selects tile from routed rows (not just for multi-topk)\n routed_rows = m * num_topk\n mma_tiler_mn = _select_moe_mma_tiler_mn(routed_rows, n)\n\n cache_key = (\n \"micro\",\n state_E,\n weight_E,\n m,\n k,\n n,\n num_topk,\n max_rows,\n mac,\n mma_tiler_mn,\n topk_ids_dtype,\n input_scales_are_reciprocal,\n fast_math,\n share_input_across_experts,\n share_expert_scales,\n single_token,\n activation,\n swiglu_alpha,\n swiglu_beta,\n swiglu_limit,\n )\n cached = _MICRO_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n return cached\n\n ab_dtype = cutlass.Float4E2M1FN\n sf_dtype = cutlass.Float8E4M3FN\n a_dtype = cutlass.BFloat16\n alpha_dtype = cutlass.Float32\n\n kernel = MoEMicroKernel(\n sf_vec_size=sf_vec_size,\n mma_tiler_mn=mma_tiler_mn,\n output_tile_count_n=max(1, (n + mma_tiler_mn[1] - 1) // mma_tiler_mn[1]),\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n share_input_across_experts=share_input_across_experts,\n share_expert_scales=share_expert_scales,\n single_token=single_token,\n )\n\n is_gated = is_gated_activation(activation)\n w1_rows = (2 if is_gated else 1) * n\n\n rows_pad_k = _align_up(max_rows, 128)\n cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n\n # Build fake tensors for compilation (identical to static kernel)\n a_input_fake = cute.runtime.make_fake_compact_tensor(\n a_dtype,\n (m, k),\n stride_order=(1, 0),\n assumed_align=16,\n )\n topk_ids_cutlass_dtype = (\n cutlass.Int32 if topk_ids_dtype == torch.int32 else cutlass.Int64\n )\n topk_ids_align = 4 if topk_ids_dtype == torch.int32 else 8\n topk_ids_fake = cute.runtime.make_fake_compact_tensor(\n topk_ids_cutlass_dtype,\n (m * num_topk,),\n assumed_align=topk_ids_align,\n )\n topk_weights_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32,\n (m * num_topk,),\n assumed_align=4,\n )\n packed_a_fake = cute.runtime.make_fake_compact_tensor(\n ab_dtype,\n (max_rows, k, state_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfa_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n packed_a_storage_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (state_E * max_rows * (k // 2),),\n assumed_align=16,\n )\n scale_storage_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (state_E * rows_pad_k * cols_pad_k,),\n assumed_align=16,\n )\n barrier_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n barrier_epoch_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n b_w13_fake = cute.runtime.make_fake_compact_tensor(\n ab_dtype,\n (w1_rows, k, weight_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_w13_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n b_down_fake = cute.runtime.make_fake_compact_tensor(\n ab_dtype,\n (k, n, weight_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_down_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n row_counts_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E,),\n assumed_align=4,\n )\n active_expert_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n weight_expert_ids_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E,),\n assumed_align=4,\n )\n global_to_local_expert_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (weight_E,),\n assumed_align=4,\n )\n input_gs_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n down_alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n global_scale_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n scatter_fake = cute.runtime.make_fake_compact_tensor(\n a_dtype,\n (m, k),\n stride_order=(1, 0),\n assumed_align=16,\n )\n token_map_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E, max_rows),\n stride_order=(1, 0),\n assumed_align=4,\n )\n token_weights_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (state_E, max_rows),\n stride_order=(1, 0),\n assumed_align=16,\n )\n compiled = cute.compile(\n kernel,\n a_input_fake,\n topk_ids_fake,\n topk_weights_fake,\n packed_a_fake,\n sfa_fake,\n packed_a_storage_fake,\n scale_storage_fake,\n barrier_count_fake,\n barrier_epoch_fake,\n b_w13_fake,\n sfb_w13_fake,\n b_down_fake,\n sfb_down_fake,\n row_counts_fake,\n active_expert_count_fake,\n weight_expert_ids_fake,\n global_to_local_expert_fake,\n input_gs_fake,\n alpha_fake,\n down_alpha_fake,\n global_scale_fake,\n scatter_fake,\n token_map_fake,\n token_weights_fake,\n mac,\n current_cuda_stream(),\n options=\"--opt-level 2 --enable-tvm-ffi\",\n )\n\n result = (compiled, mac)\n _MICRO_KERNEL_CACHE[cache_key] = result\n return result\n\n\n# The launch cache skips the per-launch build/configure; the kernel cache\n# dedupes compiles across keys that configure to the same artifact\n# (m=2..8 differ only in grid_x).\n_DIRECT_MICRO_LAUNCH_CACHE: Dict[Tuple, Tuple] = {}\n_DIRECT_MICRO_KERNEL_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_direct_micro_kernel(\n weight_E: int,\n m: int,\n k: int,\n n: int,\n num_topk: int,\n *,\n topk_ids_dtype: torch.dtype = torch.int32,\n fast_math: bool = True,\n share_input_across_experts: bool = False,\n share_expert_scales: bool = False,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n device: torch.device | None = None,\n):\n \"\"\"Compile (or retrieve cached) the SM120 direct micro MoE kernel.\n\n Returns (compiled, grid_x, accepts_block_dim).\n \"\"\"\n if activation != SWIGLUOAI_UNINTERLEAVE:\n # The kernel constructor only accepts configurable swiglu parameters\n # for swigluoai; other activations use its normalized defaults\n # (accept-and-ignore, matching the MMA kernels).\n swiglu_alpha = None\n swiglu_beta = None\n swiglu_limit = None\n launch_key = (\n weight_E,\n m,\n k,\n n,\n num_topk,\n topk_ids_dtype,\n fast_math,\n share_input_across_experts,\n share_expert_scales,\n activation,\n swiglu_alpha,\n swiglu_beta,\n swiglu_limit,\n str(_canonical_cuda_device(device)) if device is not None else None,\n )\n cached = _DIRECT_MICRO_LAUNCH_CACHE.get(launch_key)\n if cached is not None:\n return cached\n kernel = build_direct_micro_kernel(\n weight_E,\n m,\n k,\n n,\n num_topk,\n activation=activation,\n fast_math=fast_math,\n share_input_across_experts=share_input_across_experts,\n share_expert_scales=share_expert_scales,\n single_token=m == 1,\n swiglu_limit=swiglu_limit,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n device=device,\n )\n compile_key = (\"direct_micro\", kernel.__cache_key__, topk_ids_dtype)\n entry = _DIRECT_MICRO_KERNEL_CACHE.get(compile_key)\n if entry is None:\n compiled = compile_direct_micro_kernel(kernel, topk_ids_dtype=topk_ids_dtype)\n # Register pressure can cap the launchable CTA below the fused body's\n # 512 threads; probe once per compiled kernel.\n accepts = compiled_direct_micro_accepts_block_dim(\n compiled, kernel.launch_block_dim\n )\n entry = (compiled, accepts)\n _DIRECT_MICRO_KERNEL_CACHE[compile_key] = entry\n compiled, accepts = entry\n cached = (compiled, kernel.grid_x, accepts)\n _DIRECT_MICRO_LAUNCH_CACHE[launch_key] = cached\n return cached\n\n\n# ---------------------------------------------------------------------------\n# Launch\n# ---------------------------------------------------------------------------\ndef _expand_to_experts(t: torch.Tensor, num_experts: int) -> torch.Tensor:\n \"\"\"Broadcast a scalar or [1] tensor to [num_experts], always fp32.\n\n Both branches must cast: the kernels are compiled against fp32 fake\n tensors for every per-expert scale.\n \"\"\"\n if t.numel() == 1:\n return t.to(torch.float32).expand(num_experts).contiguous()\n return t.contiguous().to(torch.float32)\n\n\ndef launch_sm120_static_moe(\n *,\n workspace: Sm120StaticMoEWorkspace,\n weights: _WeightViews,\n a: torch.Tensor,\n topk_ids: torch.Tensor,\n topk_weights: torch.Tensor,\n input_gs: torch.Tensor,\n down_input_scale: torch.Tensor,\n scatter_output: torch.Tensor,\n num_experts: int,\n num_tokens: int,\n k: int,\n n: int,\n top_k: int,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n) -> torch.Tensor:\n \"\"\"Launch the SM120 static, micro, or direct micro MoE kernel.\n\n The direct micro kernel takes tiny decode batches (m <= 8, routed_rows\n < 64) when it supports the shape, the MMA micro kernel takes the rest of\n its band (routed_rows <= 20-40), and the static kernel takes the rest.\n The MMA micro path runs a Triton pre-pass to compact routing IDs before\n launching; direct micro routes on global expert ids directly.\n \"\"\"\n _check_memref_limit(\"scatter_output\", scatter_output.numel())\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 static launcher\"\n )\n\n # Flatten routing tensors\n flat_ids = topk_ids.view(-1).to(torch.int32)\n flat_weights = topk_weights.view(-1).to(torch.float32)\n routed_rows = num_tokens * top_k\n\n # Capture whether input_gs was a single shared scalar BEFORE expansion:\n # the m=1 relu2 shared-input micro optimization only applies when every\n # expert sees the same FC1-input global scale.\n input_gs_is_shared = input_gs.numel() == 1\n down_input_scale_is_shared = down_input_scale.numel() == 1\n\n # Broadcast scalar scales to per-expert [E] tensors\n input_gs = _expand_to_experts(input_gs, num_experts)\n down_input_scale = _expand_to_experts(down_input_scale, num_experts)\n\n # Shared-scale flags let compact W4A4 micro match the ReLU2 single-token\n # specialization.\n share_input_across_experts = (\n activation == \"relu2\"\n and num_tokens == 1\n and input_gs_is_shared\n and _MICRO_SHARE_INPUT_ACROSS_EXPERTS\n )\n share_expert_scales = (\n activation == \"relu2\" and input_gs_is_shared and down_input_scale_is_shared\n )\n\n # Direct micro takes its band before the MMA micro decision. It reads\n # weights by global expert id, so EP shapes keep the compact path.\n use_direct_micro = (\n activation_precision == \"fp4\"\n and workspace.state_E == num_experts\n and workspace.dm_barrier_count is not None\n and workspace.dm_barrier_count.numel() >= routed_rows + num_tokens * 16\n and num_tokens <= _MICRO_MAX_TOKENS\n and routed_rows < _DIRECT_MICRO_CUTOVER_PAIRS\n and n <= _DIRECT_MICRO_MAX_N\n and MoEDirectMicroKernel.is_supported(num_tokens, k, n, top_k, num_experts)\n )\n if _FORCED_BACKEND is not None:\n if _FORCED_BACKEND == \"direct_micro\":\n if workspace.dm_barrier_count is None or not (\n MoEDirectMicroKernel.is_supported(num_tokens, k, n, top_k, num_experts)\n ):\n raise ValueError(\n \"forced direct_micro backend cannot run this shape \"\n f\"(m={num_tokens}, k={k}, n={n}, top_k={top_k})\"\n )\n if workspace.dm_barrier_count.numel() < routed_rows + num_tokens * 16:\n raise ValueError(\n \"forced direct_micro backend exceeds the workspace barrier \"\n f\"capacity ({workspace.dm_barrier_count.numel()} slots < \"\n f\"{routed_rows} routed rows + {num_tokens * 16})\"\n )\n use_direct_micro = True\n else:\n use_direct_micro = False\n if use_direct_micro:\n compiled, grid_x, block_ok = _get_direct_micro_kernel(\n num_experts,\n num_tokens,\n k,\n n,\n top_k,\n topk_ids_dtype=flat_ids.dtype,\n fast_math=fast_math,\n share_input_across_experts=share_input_across_experts,\n share_expert_scales=share_expert_scales,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n device=a.device,\n )\n if not block_ok:\n if _FORCED_BACKEND == \"direct_micro\":\n raise RuntimeError(\"compiled direct micro MoE kernel cannot launch\")\n use_direct_micro = False\n if use_direct_micro:\n # The kernel takes multiplier-form scales only; invert reciprocal\n # inputs into the persistent workspace planes (zeros stay zero,\n # matching the MMA kernels).\n if input_scales_are_reciprocal:\n workspace.dm_input_gs.copy_(\n torch.where(input_gs != 0, 1.0 / input_gs, input_gs)\n )\n workspace.dm_down_input_scale.copy_(\n torch.where(\n down_input_scale != 0, 1.0 / down_input_scale, down_input_scale\n )\n )\n launch_gs = workspace.dm_input_gs\n launch_down = workspace.dm_down_input_scale\n else:\n launch_gs = input_gs\n launch_down = down_input_scale\n MoEDirectMicroKernel.launch(\n compiled,\n x=a,\n w1_fp4=weights.w1_storage,\n w1_blockscale=weights.w1_scale_storage,\n w1_alphas=weights.w1_alpha,\n a1_gscale=launch_gs,\n a2_gscale=launch_down,\n inter_fp32=workspace.dm_intermediate,\n w2_fp4=weights.w2_storage,\n w2_blockscale=weights.w2_scale_storage,\n w2_alphas=weights.w2_alpha,\n topk_ids=flat_ids,\n topk_weights=flat_weights,\n out=scatter_output,\n barrier_count=workspace.dm_barrier_count,\n barrier_epoch=workspace.dm_barrier_epoch,\n m=num_tokens,\n grid_x=grid_x,\n )\n return scatter_output\n\n # Decide micro vs static\n micro_cutover = _MICRO_COMPACT_CUTOVER_PAIRS\n if top_k > 1:\n micro_cutover = _MICRO_COMPACT_CUTOVER_PAIRS_MULTI_TOPK\n use_micro = (\n activation_precision == \"fp4\"\n and num_tokens <= _MICRO_MAX_TOKENS\n and routed_rows <= micro_cutover\n )\n if _FORCED_BACKEND is not None:\n if _FORCED_BACKEND == \"micro\":\n # Forced mode raises on correctness violations, never falls back.\n if num_tokens > _MICRO_MAX_TOKENS:\n raise ValueError(\n f\"forced micro backend supports at most {_MICRO_MAX_TOKENS} \"\n f\"tokens (got {num_tokens})\"\n )\n if flat_ids.numel() > workspace.compact_topk_ids.numel():\n raise ValueError(\n \"forced micro backend exceeds the workspace compact-id \"\n f\"capacity ({workspace.compact_topk_ids.numel()} < \"\n f\"{flat_ids.numel()})\"\n )\n use_micro = True\n else:\n use_micro = False\n\n sm_count = get_num_sm(torch.device(\"cuda\"))\n base_mac = min(get_max_active_clusters(1), sm_count)\n tuned_static_mac = _lookup_mac_ladder(_STATIC_MAC_LADDER, routed_rows)\n static_mac = min(tuned_static_mac or base_mac, base_mac)\n if activation_precision == \"fp4\" and not use_micro and routed_rows < 40:\n static_mac = min(static_mac, 64)\n\n if use_micro:\n assert flat_ids.numel() <= workspace.compact_topk_ids.numel(), (\n f\"compact_topk_ids buffer too small: \"\n f\"{workspace.compact_topk_ids.numel()} < {flat_ids.numel()}\"\n )\n # Single-token ReLU2 is non-gated, so the micro kernel can launch on\n # the routed expert ids directly. Gated SiLU still goes through the\n # compact id buffer so the kernel can map compact launch ids back to\n # the physical gate/up weight experts.\n if num_tokens == 1 and activation == \"relu2\":\n launch_ids = flat_ids\n elif num_tokens == 1:\n compact_ids = workspace.compact_topk_ids[: flat_ids.numel()]\n compact_ids.copy_(\n torch.arange(\n flat_ids.numel(),\n device=flat_ids.device,\n dtype=torch.int32,\n )\n )\n workspace.weight_expert_ids[: flat_ids.numel()].copy_(\n flat_ids.to(torch.int32)\n )\n workspace.active_expert_count.fill_(flat_ids.numel())\n launch_ids = compact_ids\n else:\n compact_ids = workspace.compact_topk_ids[: flat_ids.numel()]\n from .triton_compact import compact_topk_ids as _triton_compact_topk_ids\n\n _triton_compact_topk_ids(\n flat_ids,\n compact_ids,\n workspace.weight_expert_ids,\n workspace.active_expert_count,\n )\n launch_ids = compact_ids\n # Select micro MAC: min of tuned ladder, work tiles, and hardware limit.\n micro_work_tiles = max(1, routed_rows * max(1, (n + 128 - 1) // 128))\n tuned_mac = _lookup_mac_ladder(_MICRO_MAC_LADDER, routed_rows)\n micro_mac = min(tuned_mac or base_mac, micro_work_tiles, base_mac)\n compiled, mac = _get_micro_kernel(\n workspace.state_E,\n num_experts,\n num_tokens,\n k,\n n,\n top_k,\n workspace.max_rows,\n topk_ids_dtype=launch_ids.dtype,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n share_input_across_experts=share_input_across_experts,\n share_expert_scales=share_expert_scales,\n single_token=num_tokens == 1,\n mac_override=micro_mac,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n )\n else:\n compiled, mac = _get_static_kernel(\n workspace.state_E,\n num_experts,\n num_tokens,\n k,\n n,\n top_k,\n workspace.max_rows,\n topk_ids_dtype=torch.int32,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n mac_override=static_mac,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n activation_precision=activation_precision,\n )\n launch_ids = flat_ids\n\n # Pointer arguments must be passed as raw ints (data_ptr()) at runtime.\n runtime_args: Tuple[Any, ...] = (\n a,\n launch_ids,\n flat_weights,\n workspace.packed_a_view,\n workspace.packed_input_scale.data_ptr(),\n workspace.packed_a_flat,\n workspace.scale_flat,\n workspace.barrier_count,\n workspace.barrier_epoch,\n weights.w13_fp4,\n weights._w13_sf_storage.data_ptr(),\n weights.down_fp4,\n weights._down_sf_storage.data_ptr(),\n workspace.row_counts,\n workspace.active_expert_count,\n workspace.weight_expert_ids,\n workspace.global_to_local_expert,\n input_gs,\n weights.w1_alpha,\n weights.w2_alpha,\n down_input_scale,\n scatter_output,\n workspace.token_map,\n workspace.token_weights,\n )\n compiled(*runtime_args, current_cuda_stream())\n\n return scatter_output\n\n\n# ==========================================================================\n# Dynamic backend\n# ==========================================================================\n\n\ndef select_sm120_moe_backend(\n *,\n num_tokens: int,\n num_topk: int,\n activation_precision: str = \"fp4\",\n quant_mode: str | None = None,\n) -> str:\n \"\"\"Pick static or dynamic backend based on routed-pair count.\"\"\"\n mode = _normalize_quant_mode(quant_mode, activation_precision)\n if mode == \"w4a16\":\n return \"w4a16\"\n if _FORCED_BACKEND == \"dynamic\":\n return \"dynamic\"\n if _FORCED_BACKEND in (\"static\", \"micro\", \"direct_micro\"):\n # Both micro variants launch through the static workspace path.\n return \"static\"\n routed_rows = num_tokens * num_topk\n if routed_rows <= _get_static_compact_cutover_pairs(\"fp4\"):\n return \"static\"\n return \"dynamic\"\n\n\n# ---------------------------------------------------------------------------\n# Dynamic workspace\n# ---------------------------------------------------------------------------\n@dataclass(kw_only=True)\nclass Sm120DynamicMoEWorkspace:\n \"\"\"Scratch buffers for one SM120 dynamic MoE launch.\"\"\"\n\n state_E: int\n weight_E: int\n max_rows: int\n k: int\n n: int\n num_topk: int\n device: torch.device\n activation_precision: str\n\n # Core buffers\n row_counts: torch.Tensor\n token_map: torch.Tensor\n token_weights: torch.Tensor\n packed_input: torch.Tensor\n packed_input_scale: torch.Tensor\n barrier_count: torch.Tensor\n barrier_epoch: torch.Tensor\n\n # Dynamic-specific\n routed_rows_capacity: int\n physical_tiles_capacity: int\n task_capacity: int\n # The M-tile the geometry above was sized for; launches must build the\n # kernel with the same tile.\n tile_m: int = _LEVEL_TILE_M\n expert_write_rows: torch.Tensor\n expert_tile_base: torch.Tensor\n pair_head: torch.Tensor\n task_head: torch.Tensor\n task_tail: torch.Tensor\n task_expert: torch.Tensor\n task_valid_rows: torch.Tensor\n\n # Views\n packed_a_view: torch.Tensor | None = None\n sfa_ptr: object = None\n packed_a_flat: torch.Tensor | None = None\n scale_flat: torch.Tensor | None = None\n\n\ndef _dynamic_task_geometry(\n state_E: int,\n n: int,\n routed_rows: int,\n *,\n tile_m: int = _LEVEL_TILE_M,\n tile_n: int = _LEVEL_TILE_N,\n):\n \"\"\"Compute task queue dimensions from problem geometry.\n\n Each active expert can introduce at most one additional physical tile\n beyond the base count (due to per-expert tail padding). The task queue\n holds one entry per (m_tile, slice_group) pair — NOT multiplied by E.\n \"\"\"\n routed_rows = max(1, routed_rows)\n base_m_tiles = _align_up(routed_rows, tile_m) // tile_m\n active_expert_upper_bound = min(state_E, routed_rows)\n max_m_tiles = max(1, base_m_tiles + active_expert_upper_bound - 1)\n gate_tile_cnt = max(1, (n + tile_n - 1) // tile_n)\n slice_groups = max(\n 1, (gate_tile_cnt + _DYNAMIC_SLICE_CHUNK - 1) // _DYNAMIC_SLICE_CHUNK\n )\n max_tasks = max_m_tiles * slice_groups\n return max_m_tiles, gate_tile_cnt, max_tasks\n\n\ndef allocate_sm120_dynamic_workspace(\n *,\n state_E: int,\n weight_E: int,\n routed_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation_precision: str = \"fp4\",\n activation: str = \"silu\",\n) -> Sm120DynamicMoEWorkspace:\n \"\"\"Allocate workspace buffers for the SM120 dynamic MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"allocate_sm120_dynamic_workspace only supports quant_mode='nvfp4'; \"\n \"use allocate_sm120_moe_workspace(..., quant_mode='w4a16') for W4A16.\"\n )\n tile_m = _select_dynamic_tile_m(routed_rows, state_E, activation)\n physical_tiles, _, max_tasks = _dynamic_task_geometry(\n state_E,\n n,\n routed_rows,\n tile_m=tile_m,\n tile_n=_level_tile_n(activation_precision),\n )\n rows_padded = physical_tiles * tile_m\n # The kernel addresses activation scales in 128-row SF atoms regardless of\n # tile_m, so the scale plane must cover the last partial atom.\n scale_rows = _align_up(rows_padded, 128)\n cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n _check_memref_limit(\"dynamic packed_input\", rows_padded * (k // 2))\n _check_memref_limit(\"dynamic packed_input_scale\", scale_rows * cols_pad_k)\n packed_input = torch.empty(1, rows_padded, k // 2, dtype=torch.uint8, device=device)\n\n workspace = Sm120DynamicMoEWorkspace(\n state_E=state_E,\n weight_E=weight_E,\n max_rows=rows_padded,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation_precision=activation_precision,\n routed_rows_capacity=routed_rows,\n physical_tiles_capacity=physical_tiles,\n task_capacity=max_tasks,\n tile_m=tile_m,\n row_counts=torch.zeros(state_E, dtype=torch.int32, device=device),\n token_map=torch.zeros(rows_padded, dtype=torch.int32, device=device),\n token_weights=torch.zeros(rows_padded, dtype=torch.float32, device=device),\n packed_input=packed_input,\n packed_input_scale=torch.empty(\n scale_rows, cols_pad_k, dtype=torch.uint8, device=device\n ),\n barrier_count=torch.zeros(1, dtype=torch.int32, device=device),\n barrier_epoch=torch.zeros(1, dtype=torch.int32, device=device),\n expert_write_rows=torch.zeros(state_E, dtype=torch.int32, device=device),\n expert_tile_base=torch.zeros(state_E + 1, dtype=torch.int32, device=device),\n pair_head=torch.zeros(1, dtype=torch.int32, device=device),\n task_head=torch.zeros(1, dtype=torch.int32, device=device),\n task_tail=torch.zeros(1, dtype=torch.int32, device=device),\n task_expert=torch.zeros(max_tasks, dtype=torch.int32, device=device),\n task_valid_rows=torch.zeros(max_tasks, dtype=torch.int32, device=device),\n )\n\n # Finalize views\n sf_dtype = cutlass.Float8E4M3FN\n workspace.packed_a_view = workspace.packed_input.permute(1, 2, 0).view(\n torch.float4_e2m1fn_x2\n )\n workspace.packed_a_flat = workspace.packed_input.view(-1)\n workspace.scale_flat = workspace.packed_input_scale.view(-1)\n workspace.sfa_ptr = make_ptr(\n sf_dtype,\n workspace.packed_input_scale.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n return workspace\n\n\n# ---------------------------------------------------------------------------\n# Dynamic kernel compilation\n# ---------------------------------------------------------------------------\n\n\nclass _DynamicMoELaunch:\n \"\"\"Thin JIT wrapper that makes num_tokens and max_rows runtime Int32.\"\"\"\n\n def __init__(self, kernel, k, num_topk, activation_precision: str = \"fp4\"):\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 dynamic launcher wrapper\"\n )\n self._kernel = kernel\n self._k = k\n self._packed_storage_cols = k // 2\n self._num_topk = num_topk\n self._cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n\n @cute.jit\n def __call__(\n self,\n a_ptr: cute.Pointer,\n topk_ids_ptr: cute.Pointer,\n topk_weights_ptr: cute.Pointer,\n packed_a_ptr: cute.Pointer,\n sfa_ptr: cute.Pointer,\n packed_a_storage_ptr: cute.Pointer,\n scale_storage_ptr: cute.Pointer,\n barrier_count: cute.Tensor,\n barrier_epoch: cute.Tensor,\n pair_head: cute.Tensor,\n task_head: cute.Tensor,\n task_tail: cute.Tensor,\n task_expert_ptr: cute.Pointer,\n task_valid_rows_ptr: cute.Pointer,\n b_w13: cute.Tensor,\n sfb_w13_ptr: cute.Pointer,\n b_down: cute.Tensor,\n sfb_down_ptr: cute.Pointer,\n row_counts: cute.Tensor,\n expert_write_rows: cute.Tensor,\n expert_tile_base: cute.Tensor,\n input_global_scale: cute.Tensor,\n alpha: cute.Tensor,\n down_alpha: cute.Tensor,\n global_scale: cute.Tensor,\n scatter_ptr: cute.Pointer,\n token_map_ptr: cute.Pointer,\n token_weights_ptr: cute.Pointer,\n num_tokens: cutlass.Int32,\n max_rows: cutlass.Int32,\n rows_padded: cutlass.Int32,\n max_tasks: cutlass.Int32,\n max_active_clusters: cutlass.Constexpr,\n stream,\n ):\n a_input = cute.make_tensor(\n a_ptr, layout=cute.make_layout((num_tokens, self._k), stride=(self._k, 1))\n )\n topk_ids = cute.make_tensor(\n topk_ids_ptr,\n layout=cute.make_layout((num_tokens * self._num_topk,), stride=(1,)),\n )\n topk_weights_t = cute.make_tensor(\n topk_weights_ptr,\n layout=cute.make_layout((num_tokens * self._num_topk,), stride=(1,)),\n )\n scatter_output = cute.make_tensor(\n scatter_ptr,\n layout=cute.make_layout((num_tokens, self._k), stride=(self._k, 1)),\n )\n packed_a = cute.make_tensor(\n packed_a_ptr,\n layout=cute.make_layout(\n (rows_padded, self._k, 1), stride=(self._k, 1, rows_padded * self._k)\n ),\n )\n packed_a_storage = cute.make_tensor(\n packed_a_storage_ptr,\n layout=cute.make_layout(\n (rows_padded * self._packed_storage_cols,), stride=(1,)\n ),\n )\n # Activation scales live in 128-row SF atoms; the plane is allocated\n # through the last partial atom even when rows_padded is not aligned.\n scale_rows = ((rows_padded + 127) // 128) * 128\n scale_storage = cute.make_tensor(\n scale_storage_ptr,\n layout=cute.make_layout((scale_rows * self._cols_pad_k,), stride=(1,)),\n )\n token_map = cute.make_tensor(\n token_map_ptr, layout=cute.make_layout((rows_padded,), stride=(1,))\n )\n token_weights_t = cute.make_tensor(\n token_weights_ptr, layout=cute.make_layout((rows_padded,), stride=(1,))\n )\n task_expert = cute.make_tensor(\n task_expert_ptr, layout=cute.make_layout((max_tasks,), stride=(1,))\n )\n task_valid_rows = cute.make_tensor(\n task_valid_rows_ptr, layout=cute.make_layout((max_tasks,), stride=(1,))\n )\n self._kernel(\n a_input,\n topk_ids,\n topk_weights_t,\n packed_a,\n sfa_ptr,\n packed_a_storage,\n scale_storage,\n barrier_count,\n barrier_epoch,\n pair_head,\n task_head,\n task_tail,\n task_expert,\n task_valid_rows,\n b_w13,\n sfb_w13_ptr,\n b_down,\n sfb_down_ptr,\n row_counts,\n expert_write_rows,\n expert_tile_base,\n input_global_scale,\n alpha,\n down_alpha,\n global_scale,\n scatter_output,\n token_map,\n token_weights_t,\n max_active_clusters=max_active_clusters,\n stream=stream,\n )\n\n\n_DYNAMIC_KERNEL_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_dynamic_kernel(\n E: int,\n m: int,\n k: int,\n n: int,\n num_topk: int,\n max_rows: int,\n *,\n topk_ids_dtype: torch.dtype = torch.int32,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n share_input_across_experts: bool = False,\n tile_m: int = _LEVEL_TILE_M,\n):\n \"\"\"Compile (or retrieve cached) the SM120 dynamic MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 dynamic compiler\"\n )\n # Both dynamic implementations reserve 32 route slots per token for the\n # shared-input fast path. Larger top-k values remain correct by using the\n # generic per-route producer instead.\n share_input_across_experts = bool(\n share_input_across_experts\n and activation_precision == \"fp4\"\n and num_topk <= _MAX_SHARED_INPUT_TOPK\n )\n sf_vec_size = 16\n sm_count = get_num_sm(torch.device(\"cuda\"))\n base_mac = min(get_max_active_clusters(1), sm_count)\n tuned_mac = _lookup_mac_ladder(_DYNAMIC_MAC_LADDER, m * num_topk)\n mac = min(tuned_mac or base_mac, base_mac)\n # tile_m comes from the workspace's shared selection so the kernel's task\n # and scale indexing matches the allocated scratch geometry.\n mma_tiler_mn = (tile_m, _level_tile_n(activation_precision))\n\n cache_key = (\n \"dynamic\",\n activation_precision,\n E,\n k,\n n,\n num_topk,\n mac,\n mma_tiler_mn,\n topk_ids_dtype,\n input_scales_are_reciprocal,\n fast_math,\n activation,\n swiglu_alpha,\n swiglu_beta,\n swiglu_limit,\n share_input_across_experts,\n )\n cached = _DYNAMIC_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n return cached\n\n is_gated = is_gated_activation(activation)\n w1_rows = (2 if is_gated else 1) * n\n\n scratch_dtype = cutlass.Float4E2M1FN\n weight_dtype = cutlass.Float4E2M1FN\n sf_dtype = cutlass.Float8E4M3FN\n a_dtype = cutlass.BFloat16\n alpha_dtype = cutlass.Float32\n\n kernel: Any = MoEDynamicKernel(\n sf_vec_size=sf_vec_size,\n mma_tiler_mn=mma_tiler_mn,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n share_input_across_experts=share_input_across_experts,\n hidden_size=k,\n intermediate_size=n,\n num_topk=num_topk,\n )\n launch = _DynamicMoELaunch(\n kernel,\n k=k,\n num_topk=num_topk,\n activation_precision=activation_precision,\n )\n\n topk_ids_cutlass_dtype = (\n cutlass.Int32 if topk_ids_dtype == torch.int32 else cutlass.Int64\n )\n topk_ids_align = 4 if topk_ids_dtype == torch.int32 else 8\n\n # Runtime-shaped tensors passed as pointers\n a_input_fake = make_ptr(a_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n topk_ids_fake = make_ptr(\n topk_ids_cutlass_dtype,\n topk_ids_align,\n cute.AddressSpace.gmem,\n assumed_align=topk_ids_align,\n )\n topk_weights_fake = make_ptr(\n cutlass.Float32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n packed_a_fake = make_ptr(\n scratch_dtype, 16, cute.AddressSpace.gmem, assumed_align=16\n )\n sfa_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n packed_a_storage_fake = make_ptr(\n cutlass.Uint8, 16, cute.AddressSpace.gmem, assumed_align=16\n )\n scale_storage_fake = make_ptr(\n cutlass.Uint8, 16, cute.AddressSpace.gmem, assumed_align=16\n )\n\n barrier_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n barrier_epoch_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n pair_head_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n task_head_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n task_tail_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n\n task_expert_fake = make_ptr(\n cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n task_valid_rows_fake = make_ptr(\n cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n\n b_w13_fake = cute.runtime.make_fake_compact_tensor(\n weight_dtype,\n (w1_rows, k, E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_w13_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n b_down_fake = cute.runtime.make_fake_compact_tensor(\n weight_dtype,\n (k, n, E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_down_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n row_counts_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (E,), assumed_align=4\n )\n expert_write_rows_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (E,), assumed_align=4\n )\n expert_tile_base_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (E + 1,), assumed_align=4\n )\n input_gs_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype, (E,), assumed_align=16\n )\n alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype, (E,), assumed_align=16\n )\n down_alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype, (E,), assumed_align=16\n )\n global_scale_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype, (E,), assumed_align=16\n )\n scatter_fake = make_ptr(a_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n token_map_fake = make_ptr(cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4)\n token_weights_fake = make_ptr(\n alpha_dtype, 16, cute.AddressSpace.gmem, assumed_align=16\n )\n\n compiled = cute.compile(\n launch,\n a_input_fake,\n topk_ids_fake,\n topk_weights_fake,\n packed_a_fake,\n sfa_fake,\n packed_a_storage_fake,\n scale_storage_fake,\n barrier_count_fake,\n barrier_epoch_fake,\n pair_head_fake,\n task_head_fake,\n task_tail_fake,\n task_expert_fake,\n task_valid_rows_fake,\n b_w13_fake,\n sfb_w13_fake,\n b_down_fake,\n sfb_down_fake,\n row_counts_fake,\n expert_write_rows_fake,\n expert_tile_base_fake,\n input_gs_fake,\n alpha_fake,\n down_alpha_fake,\n global_scale_fake,\n scatter_fake,\n token_map_fake,\n token_weights_fake,\n 1,\n 1,\n 1,\n 1, # runtime Int32 placeholders\n mac,\n current_cuda_stream(),\n options=\"--opt-level 2 --enable-tvm-ffi\",\n )\n\n result = (compiled, mac)\n _DYNAMIC_KERNEL_CACHE[cache_key] = result\n return result\n\n\n# ---------------------------------------------------------------------------\n# Dynamic launch\n# ---------------------------------------------------------------------------\ndef launch_sm120_dynamic_moe(\n *,\n workspace: Sm120DynamicMoEWorkspace,\n weights: _WeightViews,\n a: torch.Tensor,\n topk_ids: torch.Tensor,\n topk_weights: torch.Tensor,\n input_gs: torch.Tensor,\n down_input_scale: torch.Tensor,\n scatter_output: torch.Tensor,\n num_experts: int,\n num_tokens: int,\n k: int,\n n: int,\n top_k: int,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n) -> torch.Tensor:\n \"\"\"Launch the SM120 dynamic MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 dynamic launcher\"\n )\n _check_memref_limit(\"scatter_output\", scatter_output.numel())\n flat_ids = topk_ids.view(-1).to(torch.int32)\n flat_weights = topk_weights.view(-1).to(torch.float32)\n input_gs_is_shared = input_gs.numel() == 1\n\n # Broadcast scalar scales to per-expert [E] tensors\n input_gs = _expand_to_experts(input_gs, num_experts)\n down_input_scale = _expand_to_experts(down_input_scale, num_experts)\n\n compiled, mac = _get_dynamic_kernel(\n num_experts,\n num_tokens,\n k,\n n,\n top_k,\n workspace.max_rows,\n topk_ids_dtype=torch.int32,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n activation_precision=activation_precision,\n share_input_across_experts=input_gs_is_shared,\n tile_m=workspace.tile_m,\n )\n\n # Dynamic kernel: runtime-shaped args are DataPointer (pass data_ptr()),\n # fixed-shape args are Tensor (pass torch tensor directly).\n runtime_args: Tuple[Any, ...] = (\n a.data_ptr(),\n flat_ids.data_ptr(),\n flat_weights.data_ptr(),\n workspace.packed_a_view.data_ptr(),\n workspace.packed_input_scale.data_ptr(),\n workspace.packed_a_flat.data_ptr(),\n workspace.scale_flat.data_ptr(),\n workspace.barrier_count,\n workspace.barrier_epoch,\n workspace.pair_head,\n workspace.task_head,\n workspace.task_tail,\n workspace.task_expert.data_ptr(),\n workspace.task_valid_rows.data_ptr(),\n weights.w13_fp4,\n weights._w13_sf_storage.data_ptr(),\n weights.down_fp4,\n weights._down_sf_storage.data_ptr(),\n workspace.row_counts,\n workspace.expert_write_rows,\n workspace.expert_tile_base,\n input_gs,\n weights.w1_alpha,\n weights.w2_alpha,\n down_input_scale,\n scatter_output.data_ptr(),\n workspace.token_map.data_ptr(),\n workspace.token_weights.data_ptr(),\n num_tokens,\n workspace.max_rows,\n workspace.physical_tiles_capacity * workspace.tile_m,\n workspace.task_capacity,\n )\n compiled(*runtime_args, current_cuda_stream())\n\n return scatter_output\n\n\n# ==========================================================================\n# W4A16 route-packing implementation\n# ==========================================================================\n@dataclass(kw_only=True)\nclass Sm120W4A16MoEWorkspace:\n \"\"\"Scratch buffers for the SM120 W4A16 MoE path.\"\"\"\n\n state_E: int\n weight_E: int\n max_rows: int\n k: int\n n: int\n num_topk: int\n device: torch.device\n activation: str\n activation_precision: str\n quant_mode: str\n routed_rows_capacity: int\n route_num_experts: int\n\n intermediate_cache13: torch.Tensor\n intermediate_cache2: torch.Tensor\n fc1_c_tmp: torch.Tensor\n fc2_c_tmp: torch.Tensor\n packed_route_indices: torch.Tensor\n block_expert_ids: torch.Tensor\n packed_route_count: torch.Tensor\n expert_offsets: torch.Tensor\n expert_map: torch.Tensor | None = None\n\n\ndef _is_cuda_graph_capturing() -> bool:\n try:\n return bool(torch.cuda.is_current_stream_capturing())\n except Exception:\n return False\n\n\ndef _canonical_cuda_device(device: torch.device) -> torch.device:\n device = torch.device(device)\n if device.type == \"cuda\" and device.index is None:\n return torch.device(\"cuda\", torch.cuda.current_device())\n return device\n\n\ndef _w4a16_workspace_geometry(\n *,\n routed_rows: int,\n route_num_experts: int,\n num_topk: int,\n k: int,\n n: int,\n is_gated: bool,\n device: torch.device,\n) -> tuple[int, int, int, int, int]:\n route_slots = 1\n route_blocks = 1\n fc1_c_tmp_elements = 1\n fc2_c_tmp_elements = 1\n fc1_cols = (2 if is_gated else 1) * int(n)\n sms = get_num_sm(device)\n # Size the route buffers for the power-of-2 capacity so route packing keeps\n # a single triton specialization across token counts.\n routed_rows_capacity = route_pack_numel_capacity(\n int(routed_rows), topk=int(num_topk)\n )\n for block_size in _W4A16_ALLOWED_ROUTED_SIZES:\n slots = max_packed_route_slots(\n routed_rows_capacity,\n int(block_size),\n int(route_num_experts),\n )\n blocks = (slots + int(block_size) - 1) // int(block_size)\n route_slots = max(route_slots, slots)\n route_blocks = max(route_blocks, blocks)\n fc1_c_tmp_elements = max(\n fc1_c_tmp_elements,\n packed_gemm_scratch_elements(\n size_n=fc1_cols,\n route_slots=slots,\n moe_block_size=int(block_size),\n sms=sms,\n ),\n )\n fc2_c_tmp_elements = max(\n fc2_c_tmp_elements,\n packed_gemm_scratch_elements(\n size_n=int(k),\n route_slots=slots,\n moe_block_size=int(block_size),\n sms=sms,\n ),\n )\n return (\n route_slots,\n route_blocks,\n fc1_c_tmp_elements,\n fc2_c_tmp_elements,\n fc1_cols,\n )\n\n\ndef _make_w4a16_expert_map(\n *,\n state_E: int,\n weight_E: int,\n device: torch.device,\n) -> torch.Tensor | None:\n if int(state_E) == int(weight_E):\n return None\n if int(state_E) > int(weight_E):\n raise ValueError(\"num_local_experts cannot exceed num_experts\")\n expert_map = torch.empty((int(weight_E),), dtype=torch.int32, device=device)\n expert_map.fill_(-1)\n expert_map[: int(state_E)].copy_(\n torch.arange(int(state_E), dtype=torch.int32, device=device)\n )\n return expert_map\n\n\ndef _allocate_sm120_w4a16_workspace(\n *,\n state_E: int,\n weight_E: int,\n routed_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation: str = \"silu\",\n) -> Sm120W4A16MoEWorkspace:\n is_gated = validate_activation(activation)\n routed_rows = max(1, int(routed_rows))\n route_num_experts = int(weight_E) if int(state_E) != int(weight_E) else int(state_E)\n (\n route_slots,\n route_blocks,\n fc1_c_tmp_elements,\n fc2_c_tmp_elements,\n fc1_cols,\n ) = _w4a16_workspace_geometry(\n routed_rows=routed_rows,\n route_num_experts=route_num_experts,\n num_topk=num_topk,\n k=k,\n n=n,\n is_gated=is_gated,\n device=device,\n )\n return Sm120W4A16MoEWorkspace(\n state_E=int(state_E),\n weight_E=int(weight_E),\n max_rows=routed_rows,\n k=int(k),\n n=int(n),\n num_topk=int(num_topk),\n device=device,\n activation=activation,\n activation_precision=\"bf16\",\n quant_mode=\"w4a16\",\n routed_rows_capacity=routed_rows,\n route_num_experts=route_num_experts,\n intermediate_cache13=torch.empty(\n (routed_rows * max(fc1_cols, int(k)),),\n dtype=torch.bfloat16,\n device=device,\n ),\n intermediate_cache2=torch.empty(\n (routed_rows, int(n)),\n dtype=torch.bfloat16,\n device=device,\n ),\n fc1_c_tmp=torch.empty(\n (fc1_c_tmp_elements,),\n dtype=torch.float32,\n device=device,\n ),\n fc2_c_tmp=torch.empty(\n (fc2_c_tmp_elements,),\n dtype=torch.float32,\n device=device,\n ),\n packed_route_indices=torch.empty(\n (route_slots,),\n dtype=torch.int32,\n device=device,\n ),\n block_expert_ids=torch.empty(\n (route_blocks,),\n dtype=torch.int32,\n device=device,\n ),\n packed_route_count=torch.empty((1,), dtype=torch.int32, device=device),\n expert_offsets=torch.empty(\n (route_num_experts + 1,),\n dtype=torch.int32,\n device=device,\n ),\n expert_map=_make_w4a16_expert_map(\n state_E=state_E,\n weight_E=weight_E,\n device=device,\n ),\n )\n\n\n_W4A16_WEIGHT_CACHE: Dict[Tuple, W4A16PackedWeights] = {}\n\n\ndef _get_w4a16_packed_weights(\n *,\n w1_weight: torch.Tensor,\n w1_weight_sf: torch.Tensor,\n w1_alpha: torch.Tensor,\n w2_weight: torch.Tensor,\n w2_weight_sf: torch.Tensor,\n w2_alpha: torch.Tensor,\n activation: str,\n params_dtype: torch.dtype,\n source_format: str = \"modelopt\",\n) -> W4A16PackedWeights:\n key = (\n activation,\n params_dtype,\n source_format,\n tuple(w1_weight.shape),\n tuple(w1_weight_sf.shape),\n tuple(w1_alpha.shape),\n tuple(w2_weight.shape),\n tuple(w2_weight_sf.shape),\n tuple(w2_alpha.shape),\n w1_weight.data_ptr(),\n w1_weight_sf.data_ptr(),\n w1_alpha.data_ptr(),\n w2_weight.data_ptr(),\n w2_weight_sf.data_ptr(),\n w2_alpha.data_ptr(),\n )\n cached = _W4A16_WEIGHT_CACHE.get(key)\n if cached is not None:\n return cached\n if _is_cuda_graph_capturing():\n raise RuntimeError(\n \"W4A16 packed weights are not initialized for CUDA graph capture; \"\n \"run once before capture so the prepared weights are cached.\"\n )\n prepared = prepare_w4a16_packed_weights(\n w1_weight,\n w1_weight_sf,\n w1_alpha,\n w2_weight,\n w2_weight_sf,\n w2_alpha,\n activation=activation,\n params_dtype=params_dtype,\n source_format=source_format,\n )\n _W4A16_WEIGHT_CACHE[key] = prepared\n _register_cache_eviction(\n _W4A16_WEIGHT_CACHE,\n key,\n w1_weight,\n w1_weight_sf,\n w1_alpha,\n w2_weight,\n w2_weight_sf,\n w2_alpha,\n )\n return prepared\n\n\ndef _validate_w4a16_workspace(\n workspace: Sm120W4A16MoEWorkspace,\n *,\n state_E: int,\n weight_E: int,\n routed_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation: str,\n) -> None:\n validate_activation(activation)\n if workspace.state_E != int(state_E) or workspace.weight_E != int(weight_E):\n raise ValueError(\"pre-allocated W4A16 workspace expert geometry mismatch\")\n if workspace.k != int(k) or workspace.n != int(n):\n raise ValueError(\"pre-allocated W4A16 workspace hidden geometry mismatch\")\n if workspace.num_topk != int(num_topk):\n raise ValueError(\"pre-allocated W4A16 workspace top-k mismatch\")\n if getattr(workspace, \"activation\", None) != activation:\n raise ValueError(\"pre-allocated W4A16 workspace activation mismatch\")\n if _canonical_cuda_device(workspace.device) != _canonical_cuda_device(device):\n raise ValueError(\n f\"pre-allocated W4A16 workspace is on {workspace.device}, expected {device}\"\n )\n if workspace.routed_rows_capacity < max(1, int(routed_rows)):\n raise ValueError(\n \"pre-allocated W4A16 workspace is too small for the requested \"\n f\"routed rows ({workspace.routed_rows_capacity} < {routed_rows})\"\n )\n\n\ndef _launch_sm120_w4a16_moe(\n *,\n a: torch.Tensor,\n topk_ids: torch.Tensor,\n topk_weights: torch.Tensor,\n w1_weight: torch.Tensor,\n w1_weight_sf: torch.Tensor,\n w1_alpha: torch.Tensor,\n w2_weight: torch.Tensor,\n w2_weight_sf: torch.Tensor,\n w2_alpha: torch.Tensor,\n num_experts: int,\n top_k: int,\n num_local_experts: int,\n scatter_output: torch.Tensor,\n fast_math: bool = True,\n activation: str = \"silu\",\n source_format: str = \"modelopt\",\n _workspace=None,\n _prepared_weights=None,\n) -> torch.Tensor:\n prepared = (\n _prepared_weights\n if isinstance(_prepared_weights, W4A16PackedWeights)\n else _get_w4a16_packed_weights(\n w1_weight=w1_weight,\n w1_weight_sf=w1_weight_sf,\n w1_alpha=w1_alpha,\n w2_weight=w2_weight,\n w2_weight_sf=w2_weight_sf,\n w2_alpha=w2_alpha,\n activation=activation,\n params_dtype=a.dtype,\n source_format=source_format,\n )\n )\n if int(prepared.num_experts) != int(num_local_experts):\n raise ValueError(\"num_local_experts must match w1_weight.shape[0] for W4A16.\")\n num_tokens = int(topk_ids.size(0))\n routed_rows = num_tokens * int(top_k)\n k = int(a.size(1))\n n = int(prepared.intermediate_size)\n\n if _workspace is None:\n workspace = _get_cached_workspace(\n backend=\"w4a16\",\n state_E=num_local_experts,\n weight_E=num_experts,\n routed_rows=routed_rows,\n k=k,\n n=n,\n num_topk=top_k,\n device=a.device,\n quant_mode=\"w4a16\",\n activation=activation,\n )\n else:\n workspace = _workspace\n if not isinstance(workspace, Sm120W4A16MoEWorkspace):\n raise TypeError(\"expected a W4A16 workspace for quant_mode='w4a16'\")\n _validate_w4a16_workspace(\n workspace,\n state_E=num_local_experts,\n weight_E=num_experts,\n routed_rows=routed_rows,\n k=k,\n n=n,\n num_topk=top_k,\n device=a.device,\n activation=activation,\n )\n\n return run_w4a16_moe(\n a,\n prepared,\n topk_weights,\n topk_ids,\n activation=activation,\n intermediate_cache13=workspace.intermediate_cache13,\n intermediate_cache2=workspace.intermediate_cache2,\n output=scatter_output,\n fc1_c_tmp=workspace.fc1_c_tmp,\n fc2_c_tmp=workspace.fc2_c_tmp,\n packed_route_indices=workspace.packed_route_indices,\n block_expert_ids=workspace.block_expert_ids,\n packed_route_count=workspace.packed_route_count,\n expert_offsets=workspace.expert_offsets,\n expert_map=workspace.expert_map,\n fast_math=fast_math,\n )\n\n\n# ==========================================================================\n# Workspace cache (for functional API path)\n# ==========================================================================\n\n_Sm120Workspace = Union[\n Sm120StaticMoEWorkspace,\n Sm120DynamicMoEWorkspace,\n Sm120W4A16MoEWorkspace,\n]\n\n# Stores the workspace with the largest capacity seen per key and never\n# shrinks within a process. clear_sm120_moe_caches() releases everything.\n_WORKSPACE_CACHE: Dict[Tuple, _Sm120Workspace] = {}\n\n\ndef clear_sm120_moe_caches() -> None:\n \"\"\"Release every module-level SM12x MoE cache.\n\n References held by callers are unaffected.\n \"\"\"\n _WORKSPACE_CACHE.clear()\n _WEIGHT_CACHE.clear()\n _W4A16_WEIGHT_CACHE.clear()\n _PADDED_WEIGHT_CACHE.clear()\n _STATIC_KERNEL_CACHE.clear()\n _MICRO_KERNEL_CACHE.clear()\n _DIRECT_MICRO_LAUNCH_CACHE.clear()\n _DIRECT_MICRO_KERNEL_CACHE.clear()\n _DYNAMIC_KERNEL_CACHE.clear()\n\n\ndef allocate_sm120_moe_workspace(\n *,\n state_E: int,\n weight_E: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n max_rows: int | None = None,\n routed_rows: int | None = None,\n quant_mode: str | None = None,\n activation_precision: str | None = None,\n backend: str | None = None,\n activation: str = \"silu\",\n) -> _Sm120Workspace:\n \"\"\"Allocate the right SM120 MoE workspace from a quantization mode.\"\"\"\n mode = _normalize_quant_mode(quant_mode, activation_precision)\n capacity_rows = routed_rows if routed_rows is not None else max_rows\n if capacity_rows is None:\n raise ValueError(\"routed_rows or max_rows is required\")\n capacity_rows = max(1, int(capacity_rows))\n device = torch.device(device)\n\n if mode == \"w4a16\":\n if backend not in (None, \"w4a16\"):\n raise ValueError(\"quant_mode='w4a16' does not use static/dynamic backend\")\n return _allocate_sm120_w4a16_workspace(\n state_E=state_E,\n weight_E=weight_E,\n routed_rows=capacity_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation=activation,\n )\n\n activation_precision = \"fp4\"\n if backend is None:\n backend = select_sm120_moe_backend(\n num_tokens=max(\n 1, (capacity_rows + max(1, int(num_topk)) - 1) // max(1, int(num_topk))\n ),\n num_topk=int(num_topk),\n activation_precision=activation_precision,\n )\n if backend == \"dynamic\":\n return allocate_sm120_dynamic_workspace(\n state_E=state_E,\n weight_E=weight_E,\n routed_rows=capacity_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation_precision=activation_precision,\n activation=activation,\n )\n if backend == \"static\":\n return allocate_sm120_static_workspace(\n state_E=state_E,\n weight_E=weight_E,\n max_rows=capacity_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation_precision=activation_precision,\n )\n raise ValueError(f\"unsupported SM120 MoE backend {backend!r}\")\n\n\ndef _get_cached_workspace(\n *,\n backend: str,\n state_E: int,\n weight_E: int,\n routed_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation_precision: str = \"fp4\",\n quant_mode: str | None = None,\n activation: str = \"silu\",\n) -> _Sm120Workspace:\n \"\"\"Get or allocate a cached workspace for the given problem shape.\n\n Reuses the cached workspace if it has enough capacity for the requested\n routed_rows. For static workspaces, max_rows is the direct capacity.\n For dynamic workspaces, routed_rows_capacity is used because the dynamic\n geometry (physical tiles, task queue slots) depends on the original\n routed_rows, not just max_rows.\n \"\"\"\n quant_mode = _normalize_quant_mode(quant_mode, activation_precision)\n activation_precision = _activation_precision_from_quant_mode(quant_mode)\n # Key dynamic workspaces on the tile band of this call's routed_rows; a\n # larger cached workspace must not pin small calls to its 128 tile.\n tile_m = (\n _select_dynamic_tile_m(max(1, routed_rows), state_E, activation)\n if backend == \"dynamic\" and quant_mode != \"w4a16\"\n else None\n )\n cache_key = (\n state_E,\n weight_E,\n k,\n n,\n num_topk,\n str(device),\n backend,\n quant_mode,\n activation,\n tile_m,\n )\n cached = _WORKSPACE_CACHE.get(cache_key)\n\n if cached is not None:\n if isinstance(cached, Sm120DynamicMoEWorkspace):\n if cached.routed_rows_capacity >= max(1, routed_rows):\n assert tile_m is None or cached.tile_m == tile_m\n return cached\n elif isinstance(cached, Sm120W4A16MoEWorkspace):\n if cached.routed_rows_capacity >= max(1, routed_rows):\n return cached\n else:\n if cached.max_rows >= max(1, routed_rows):\n return cached\n\n if quant_mode == \"w4a16\" and _is_cuda_graph_capturing():\n raise RuntimeError(\n \"W4A16 workspace is not initialized for CUDA graph capture; \"\n \"provide a preallocated workspace from \"\n \"allocate_sm120_moe_workspace(..., quant_mode='w4a16') or warm the \"\n \"functional path before capture.\"\n )\n workspace = allocate_sm120_moe_workspace(\n state_E=state_E,\n weight_E=weight_E,\n routed_rows=routed_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n quant_mode=quant_mode,\n activation_precision=activation_precision,\n backend=backend,\n activation=activation,\n )\n\n _WORKSPACE_CACHE[cache_key] = workspace\n return workspace\n\n\n# ==========================================================================\n# Unified dispatch\n# ==========================================================================\n_PADDED_WEIGHT_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _pad_intermediate_to_tile(\n w1_weight,\n w1_weight_sf,\n w2_weight,\n w2_weight_sf,\n fc2_input_scale,\n n,\n tile,\n h,\n num_experts,\n is_gated,\n):\n \"\"\"Zero-pad NVFP4 weights + scale factors so the intermediate size is a\n multiple of ``tile`` (gate/up tile-split requirement); padded channels are\n zero, so the result is numerically identical.\n \"\"\"\n n_pad = ((n + tile - 1) // tile) * tile\n if n_pad == n:\n return w1_weight, w1_weight_sf, w2_weight, w2_weight_sf, fc2_input_scale, n\n E = int(num_experts)\n fc2_input_scale_src = fc2_input_scale\n key = (\n n,\n tile,\n h,\n E,\n bool(is_gated),\n w1_weight.data_ptr(),\n w1_weight_sf.data_ptr(),\n w2_weight.data_ptr(),\n w2_weight_sf.data_ptr(),\n fc2_input_scale_src.data_ptr() if fc2_input_scale_src is not None else 0,\n )\n cached = _PADDED_WEIGHT_CACHE.get(key)\n if cached is not None:\n return cached\n\n def mma_to_logical(sf, m, k):\n sw = convert_sf_from_mma_layout(sf, m=m, k=k, num_groups=E)\n m_pad = ((m + 127) // 128) * 128\n sw = sw.reshape(E, m_pad, -1)\n cb = (k + SF_VEC_SIZE - 1) // SF_VEC_SIZE\n return torch.stack(\n [unswizzle_block_scale(sw[e], rows=m, cols_blocks=cb) for e in range(E)], 0\n )\n\n def logical_to_mma(log, m, k):\n sw = torch.stack([swizzle_block_scale(log[e]) for e in range(E)], 0)\n sw2d = sw.reshape(E * sw.shape[1], sw.shape[2]).to(torch.float8_e4m3fn)\n return convert_sf_to_mma_layout(sw2d, m=m, k=k, num_groups=E)\n\n def pad_dim(t, dim, old, new):\n if new == old:\n return t\n shp = list(t.shape)\n shp[dim] = new - old\n return torch.cat([t, t.new_zeros(shp)], dim=dim)\n\n if is_gated:\n # w1 packs [up(0:n), gate(n:2n)] rows; pad each half so the split stays\n # tile-aligned, then re-concat.\n up, gate = w1_weight[:, :n, :], w1_weight[:, n : 2 * n, :]\n w1p = torch.cat([pad_dim(up, 1, n, n_pad), pad_dim(gate, 1, n, n_pad)], dim=1)\n log1 = mma_to_logical(w1_weight_sf, m=2 * n, k=h)\n up_sf, gate_sf = log1[:, :n, :], log1[:, n : 2 * n, :]\n log1p = torch.cat(\n [pad_dim(up_sf, 1, n, n_pad), pad_dim(gate_sf, 1, n, n_pad)], dim=1\n )\n w1_sf_p = logical_to_mma(log1p, m=2 * n_pad, k=h)\n else:\n w1p = pad_dim(w1_weight, 1, n, n_pad)\n log1 = mma_to_logical(w1_weight_sf, m=n, k=h)\n w1_sf_p = logical_to_mma(pad_dim(log1, 1, n, n_pad), m=n_pad, k=h)\n\n # w2 reduces over the intermediate dim: pad its packed columns + SF columns.\n w2p = pad_dim(w2_weight, 2, n // 2, n_pad // 2)\n log2 = mma_to_logical(w2_weight_sf, m=h, k=n)\n cb_n = (n + SF_VEC_SIZE - 1) // SF_VEC_SIZE\n cb_np = (n_pad + SF_VEC_SIZE - 1) // SF_VEC_SIZE\n w2_sf_p = logical_to_mma(pad_dim(log2, 2, cb_n, cb_np), m=h, k=n_pad)\n\n if fc2_input_scale_src is not None and fc2_input_scale_src.numel() == n:\n fc2_input_scale = pad_dim(fc2_input_scale_src, 0, n, n_pad)\n result = (w1p, w1_sf_p, w2p, w2_sf_p, fc2_input_scale, n_pad)\n _PADDED_WEIGHT_CACHE[key] = result\n _register_cache_eviction(\n _PADDED_WEIGHT_CACHE,\n key,\n w1_weight,\n w1_weight_sf,\n w2_weight,\n w2_weight_sf,\n fc2_input_scale_src,\n )\n return result\n\n\ndef launch_sm120_moe(\n *,\n a: torch.Tensor,\n topk_ids: torch.Tensor,\n topk_weights: torch.Tensor,\n w1_weight: torch.Tensor,\n w1_weight_sf: torch.Tensor,\n w1_alpha: torch.Tensor,\n fc2_input_scale: Optional[torch.Tensor] = None,\n input_global_scale: Optional[torch.Tensor] = None,\n w2_weight: torch.Tensor,\n w2_weight_sf: torch.Tensor,\n w2_alpha: torch.Tensor,\n num_experts: int,\n top_k: int,\n num_local_experts: int,\n scatter_output: torch.Tensor,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n quant_mode: str | None = None,\n source_format: str = \"modelopt\",\n _workspace=None,\n _weight_views=None,\n _prepared_weights=None,\n) -> torch.Tensor:\n \"\"\"Unified SM120 MoE dispatch — selects static or dynamic by token count.\n\n input_global_scale overrides w1_alpha as the FC1 input-quant scale and\n is folded into the multiplier internally. With _weight_views supplied,\n w1_alpha must already contain the fold.\n\n Optional _workspace and _weight_views can be pre-allocated and reused\n across calls to avoid per-call allocation overhead (wrapper path).\n When not provided (functional API path), a module-level workspace cache\n is used to avoid re-allocating on every call.\n \"\"\"\n quant_mode = _normalize_quant_mode(quant_mode, activation_precision)\n source_format = _normalize_source_format_for_quant_mode(source_format, quant_mode)\n activation_precision = _activation_precision_from_quant_mode(quant_mode)\n\n num_tokens = topk_ids.size(0)\n k = a.size(1) # hidden_size\n is_gated = is_gated_activation(activation)\n # w1_weight.size(1) is 2*n for gated or n for non-gated\n intermediate_size = w1_weight.size(1) // 2 if is_gated else w1_weight.size(1)\n n = intermediate_size\n\n # NVFP4 kernels need padded intermediate size.\n if quant_mode != \"w4a16\" and n % _LEVEL_TILE_N != 0 and _weight_views is None:\n (\n w1_weight,\n w1_weight_sf,\n w2_weight,\n w2_weight_sf,\n fc2_input_scale,\n n,\n ) = _pad_intermediate_to_tile(\n w1_weight,\n w1_weight_sf,\n w2_weight,\n w2_weight_sf,\n fc2_input_scale,\n n,\n _LEVEL_TILE_N,\n k,\n w1_weight.size(0),\n is_gated,\n )\n\n routed_rows = num_tokens * top_k\n\n if quant_mode == \"w4a16\":\n return _launch_sm120_w4a16_moe(\n a=a,\n topk_ids=topk_ids,\n topk_weights=topk_weights,\n w1_weight=w1_weight,\n w1_weight_sf=w1_weight_sf,\n w1_alpha=w1_alpha,\n w2_weight=w2_weight,\n w2_weight_sf=w2_weight_sf,\n w2_alpha=w2_alpha,\n num_experts=num_experts,\n top_k=top_k,\n num_local_experts=num_local_experts,\n scatter_output=scatter_output,\n fast_math=fast_math,\n activation=activation,\n source_format=source_format,\n _workspace=_workspace,\n _prepared_weights=_prepared_weights,\n )\n\n if fc2_input_scale is None:\n raise ValueError(\"fc2_input_scale is required when quant_mode='nvfp4'.\")\n down_input_scale = fc2_input_scale\n if input_global_scale is not None:\n input_gs = input_global_scale\n if _weight_views is None:\n # Alpha must carry input_gs back or the output magnitude is wrong.\n # The wrapper folds before building _weight_views; don't fold twice.\n w1_alpha = (\n w1_alpha.to(torch.float32) * input_global_scale.to(torch.float32)\n ).contiguous()\n else:\n input_gs = w1_alpha\n\n weights = (\n _weight_views\n if _weight_views is not None\n else _get_weight_views(\n w1_fp4=w1_weight,\n w1_blockscale=w1_weight_sf,\n w2_fp4=w2_weight,\n w2_blockscale=w2_weight_sf,\n w1_alphas=w1_alpha,\n w2_alphas=w2_alpha,\n n=n,\n k=k,\n activation_precision=activation_precision,\n )\n )\n\n # Resolve workspace and backend selection.\n # When a pre-allocated workspace is provided (CUDA graph wrapper path),\n # infer the backend from the workspace type so they stay in sync —\n # the caller already committed to a backend at allocation time.\n if _workspace is not None:\n workspace = _workspace\n workspace_activation_precision = getattr(\n workspace, \"activation_precision\", activation_precision\n )\n if workspace_activation_precision != activation_precision:\n raise ValueError(\n \"pre-allocated workspace activation_precision does not match \"\n f\"requested activation_precision={activation_precision!r}.\"\n )\n if isinstance(workspace, Sm120DynamicMoEWorkspace):\n if num_local_experts != num_experts:\n raise ValueError(\n \"pre-allocated dynamic SM120 MoE workspace requires \"\n \"num_local_experts == num_experts because dynamic expert \"\n \"buffers are indexed by global topk ids.\"\n )\n # A pre-allocated dynamic workspace keeps its stored tile_m even\n # for smaller calls; its geometry was sized for that tile.\n backend = \"dynamic\"\n else:\n backend = \"static\"\n else:\n backend = select_sm120_moe_backend(\n num_tokens=num_tokens,\n num_topk=top_k,\n activation_precision=activation_precision,\n )\n # The dynamic kernel indexes row_counts/expert_write_rows directly with\n # topk_ids but those buffers are sized with num_local_experts. Unless\n # num_local_experts == num_experts, fall back to the static backend which\n # has global-to-local expert remapping.\n if backend == \"dynamic\" and num_local_experts != num_experts:\n backend = \"static\"\n workspace = _get_cached_workspace(\n backend=backend,\n state_E=num_local_experts,\n weight_E=num_experts,\n routed_rows=routed_rows,\n k=k,\n n=n,\n num_topk=top_k,\n device=a.device,\n activation_precision=activation_precision,\n quant_mode=quant_mode,\n activation=activation,\n )\n\n if backend == \"dynamic\":\n return launch_sm120_dynamic_moe(\n workspace=workspace,\n weights=weights,\n a=a,\n topk_ids=topk_ids,\n topk_weights=topk_weights,\n input_gs=input_gs,\n down_input_scale=down_input_scale,\n scatter_output=scatter_output,\n num_experts=num_experts,\n num_tokens=num_tokens,\n k=k,\n n=n,\n top_k=top_k,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n activation_precision=activation_precision,\n )\n else:\n return launch_sm120_static_moe(\n workspace=workspace,\n weights=weights,\n a=a,\n topk_ids=topk_ids,\n topk_weights=topk_weights,\n input_gs=input_gs,\n down_input_scale=down_input_scale,\n scatter_output=scatter_output,\n num_experts=num_experts,\n num_tokens=num_tokens,\n k=k,\n n=n,\n top_k=top_k,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n activation_precision=activation_precision,\n )\n"},"diff":{"kind":"string","value":"--- flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_dispatch.py\n+++ flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_dispatch.py\n@@ -31,7 +31,11 @@\n compile_direct_micro_kernel,\n compiled_direct_micro_accepts_block_dim,\n )\n-from .moe_dynamic_kernel import _TASK_SLICE_CHUNK, MoEDynamicKernel\n+from .moe_dynamic_kernel import (\n+ _MAX_SHARED_INPUT_TOPK,\n+ _TASK_SLICE_CHUNK,\n+ MoEDynamicKernel,\n+)\n from .moe_micro_kernel import MoEMicroKernel\n from .moe_static_kernel import MoEStaticKernel\n from .moe_w4a16_fp4_helpers import swizzle_block_scale\n@@ -1839,8 +1843,13 @@\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 dynamic compiler\"\n )\n+ # Both dynamic implementations reserve 32 route slots per token for the\n+ # shared-input fast path. Larger top-k values remain correct by using the\n+ # generic per-route producer instead.\n share_input_across_experts = bool(\n- share_input_across_experts and activation_precision == \"fp4\"\n+ share_input_across_experts\n+ and activation_precision == \"fp4\"\n+ and num_topk <= _MAX_SHARED_INPUT_TOPK\n )\n sf_vec_size = 16\n sm_count = get_num_sm(torch.device(\"cuda\"))\n@@ -1892,6 +1901,9 @@\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n share_input_across_experts=share_input_across_experts,\n+ hidden_size=k,\n+ intermediate_size=n,\n+ num_topk=num_topk,\n )\n launch = _DynamicMoELaunch(\n kernel,"},"lines_added":{"kind":"number","value":14,"string":"14"},"lines_removed":{"kind":"number","value":2,"string":"2"},"files_in_commit":{"kind":"number","value":2,"string":"2"},"models_mentioned":{"kind":"list like","value":["qwen"],"string":"[\n \"qwen\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["BLACKWELL","SM120","SM121"],"string":"[\n \"BLACKWELL\",\n \"SM120\",\n \"SM121\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cute_dsl kernel file from flashinfer (flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_dispatch.py).\n\nGoal: feat: optimize gated SM12x dynamic NVFP4 MoE\nTarget hardware: BLACKWELL, SM120, SM121\nTarget models: qwen\n\nCurrent file:\n```python\n\"\"\"SM120/SM121 MoE dispatch layer — workspace, compilation, and launch.\n\nPorted from b12x's integration/tp_moe.py. Supports micro (tiny decode),\nstatic (decode), and dynamic (prefill) backends with token-count-based\nselection.\n\"\"\"\n\nfrom __future__ import annotations\n\nimport os\nimport weakref\nfrom dataclasses import dataclass\nfrom typing import Any, Dict, Optional, Tuple, Union\n\nimport cutlass\nimport cutlass.cute as cute\nimport torch\n\nfrom flashinfer.cute_dsl.utils import (\n convert_sf_from_mma_layout,\n convert_sf_to_mma_layout,\n current_cuda_stream,\n get_max_active_clusters,\n get_num_sm,\n make_ptr,\n)\nfrom .moe_activation import SWIGLUOAI_UNINTERLEAVE, is_gated_activation\nfrom .moe_direct_micro_kernel import (\n MoEDirectMicroKernel,\n build_direct_micro_kernel,\n compile_direct_micro_kernel,\n compiled_direct_micro_accepts_block_dim,\n)\nfrom .moe_dynamic_kernel import _TASK_SLICE_CHUNK, MoEDynamicKernel\nfrom .moe_micro_kernel import MoEMicroKernel\nfrom .moe_static_kernel import MoEStaticKernel\nfrom .moe_w4a16_fp4_helpers import swizzle_block_scale\nfrom .moe_w4a16_host import (\n _W4A16_ALLOWED_ROUTED_SIZES,\n max_packed_route_slots,\n packed_gemm_scratch_elements,\n route_pack_numel_capacity,\n unswizzle_block_scale,\n validate_activation,\n)\nfrom .moe_w4a16_kernel import run_w4a16_moe\nfrom .moe_w4a16_prepare import (\n W4A16PackedWeights,\n _normalize_source_format,\n prepare_w4a16_packed_weights,\n)\n\n# ---------------------------------------------------------------------------\n# Constants\n# ---------------------------------------------------------------------------\n_NVFP4_BLOCK_SIZE = 16\n_LEVEL_TILE_M = 128\n_LEVEL_TILE_N = 128\n# Must equal the kernel's task materialization granularity or the task\n# queue is mis-sized.\n_DYNAMIC_SLICE_CHUNK = _TASK_SLICE_CHUNK\nSF_VEC_SIZE = 16\n_FORCE_MOE_W4A16_ENV = \"FLASHINFER_B12X_FORCE_MOE_W4A16\"\n_MICRO_SHARE_INPUT_ACROSS_EXPERTS = (\n os.environ.get(\"FLASHINFER_B12X_MICRO_SHARE_INPUT\", \"1\") != \"0\"\n)\n\n# Micro kernel cutover thresholds (routed pairs)\n_MICRO_COMPACT_CUTOVER_PAIRS = 20\n_MICRO_COMPACT_CUTOVER_PAIRS_MULTI_TOPK = 40\n# The micro kernel's per-token staging assumes decode-sized batches.\n_MICRO_MAX_TOKENS = 8\n# Direct micro takes the smallest decode batches ahead of the MMA micro\n# kernel, and only at small intermediate sizes where its CUDA-core dots\n# keep up with per-token work. Measured on GB10, pending other GPUs.\n_DIRECT_MICRO_CUTOVER_PAIRS = 32\n_DIRECT_MICRO_MAX_N = 512\n# Test/bench hook: force one backend (\"direct_micro\", \"micro\", \"static\",\n# \"dynamic\"). Deliberately module-level (a monkeypatch target), not an env var.\n_FORCED_BACKEND: str | None = None\n_STATIC_COMPACT_CUTOVER_PAIRS_DEFAULT = 640\n_STATIC_COMPACT_CUTOVER_PAIRS = _STATIC_COMPACT_CUTOVER_PAIRS_DEFAULT\n_STATIC_COMPACT_CUTOVER_PAIRS_CACHE: Dict[str, int] = {}\n\n# MAC (max active clusters) tuning ladders from b12x decode profiling.\n# Each entry is (max_routed_rows, optimal_mac).\n_MICRO_MAC_LADDER: Tuple[Tuple[int, int], ...] = (\n (2, 84),\n (4, 127),\n (8, 107),\n (10, 84),\n (16, 63),\n (20, 84),\n)\n_STATIC_MAC_LADDER: Tuple[Tuple[int, int], ...] = (\n (24, 148),\n (32, 169),\n (40, 132),\n (48, 149),\n (64, 134),\n (80, 175),\n (96, 171),\n (120, 125),\n (128, 130),\n (160, 171),\n (192, 166),\n (256, 141),\n (320, 158),\n (512, 175),\n (640, 188),\n)\n# Workloads at or below the static cutover (640 routed pairs by default)\n# take the static kernel, so only the 1024 entry is normally reachable.\n_DYNAMIC_MAC_LADDER: Tuple[Tuple[int, int], ...] = (\n (640, 188),\n (1024, 147),\n)\n\n\ndef _lookup_mac_ladder(\n ladder: Tuple[Tuple[int, int], ...], routed_rows: int\n) -> int | None:\n \"\"\"Look up optimal MAC from a tuning ladder. Returns None if no match.\"\"\"\n for end_rows, mac in ladder:\n if routed_rows <= end_rows:\n return mac\n return None\n\n\ndef _align_up(value: int, alignment: int) -> int:\n return ((value + alignment - 1) // alignment) * alignment\n\n\n# The kernels index the packed activation and scale planes with 32-bit\n# offsets, so reject any workspace plane large enough to overflow them.\n_RUNTIME_MEMREF_LIMIT = (1 << 31) - 1\n\n\ndef _check_memref_limit(name: str, elements: int) -> None:\n if elements > _RUNTIME_MEMREF_LIMIT:\n raise ValueError(\n f\"{name} needs {elements} elements, which exceeds the 2^31-1 \"\n \"runtime memref limit. Reduce the token chunk or expert count \"\n \"for this launch.\"\n )\n\n\ndef _first_env(*names: str) -> str | None:\n for name in names:\n value = os.environ.get(name)\n if value is not None:\n return value\n return None\n\n\ndef _normalize_activation_precision(activation_precision: str) -> str:\n \"\"\"Normalize public activation-precision names to internal modes.\"\"\"\n if os.environ.get(_FORCE_MOE_W4A16_ENV, \"0\") == \"1\":\n return \"bf16\"\n\n normalized = str(activation_precision).lower()\n aliases = {\n \"fp4\": \"fp4\",\n \"nvfp4\": \"fp4\",\n \"w4a4\": \"fp4\",\n \"bf16\": \"bf16\",\n \"w4a16\": \"bf16\",\n }\n try:\n return aliases[normalized]\n except KeyError as exc:\n raise ValueError(\n \"activation_precision must be 'fp4' or 'bf16' \"\n f\"(got {activation_precision!r}).\"\n ) from exc\n\n\ndef _normalize_quant_mode(\n quant_mode: str | None = None,\n activation_precision: str | None = None,\n) -> str:\n \"\"\"Normalize public quantization names to the dispatch mode.\"\"\"\n if os.environ.get(_FORCE_MOE_W4A16_ENV, \"0\") == \"1\":\n return \"w4a16\"\n if quant_mode is None:\n activation_precision = _normalize_activation_precision(\n activation_precision or \"fp4\"\n )\n return \"w4a16\" if activation_precision == \"bf16\" else \"nvfp4\"\n\n normalized = str(quant_mode).lower()\n aliases = {\n \"fp4\": \"nvfp4\",\n \"nvfp4\": \"nvfp4\",\n \"w4a4\": \"nvfp4\",\n \"bf16\": \"w4a16\",\n \"w4a16\": \"w4a16\",\n }\n try:\n return aliases[normalized]\n except KeyError as exc:\n raise ValueError(\n f\"quant_mode must be 'nvfp4'/'w4a4' or 'w4a16' (got {quant_mode!r}).\"\n ) from exc\n\n\ndef _activation_precision_from_quant_mode(quant_mode: str) -> str:\n return \"bf16\" if _normalize_quant_mode(quant_mode) == \"w4a16\" else \"fp4\"\n\n\ndef _normalize_source_format_for_quant_mode(source_format: str, quant_mode: str) -> str:\n normalized = _normalize_source_format(source_format)\n if quant_mode == \"nvfp4\" and normalized == \"compressed_tensors\":\n raise ValueError(\n \"source_format='compressed_tensors' requires quant_mode='w4a16'.\"\n )\n return normalized\n\n\ndef _is_w4a16(activation_precision: str) -> bool:\n return _normalize_activation_precision(activation_precision) == \"bf16\"\n\n\ndef _level_tile_n(activation_precision: str = \"fp4\") -> int:\n if _is_w4a16(activation_precision):\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 tile selector\"\n )\n return _LEVEL_TILE_N\n\n\ndef _select_dynamic_tile_m(\n routed_rows: int,\n num_experts: int,\n activation: str = \"silu\",\n) -> int:\n \"\"\"Pick the dynamic kernel's M-tile from routed rows per expert.\n\n Small tiles cut per-expert tail padding for sparse routing; 128 amortizes\n best for dense prefill (crossovers measured on gated NVFP4). Workspace\n sizing and the kernel build must both derive the tile from this function,\n or the scratch is mis-sized for what the kernel indexes.\n \"\"\"\n if not is_gated_activation(activation):\n return _LEVEL_TILE_M\n routed_rows = max(1, int(routed_rows))\n num_experts = max(1, int(num_experts))\n if routed_rows < 15 * num_experts:\n return 16\n if routed_rows < 48 * num_experts:\n return 32\n if routed_rows < 96 * num_experts:\n return 64\n return _LEVEL_TILE_M\n\n\ndef _get_static_compact_cutover_pairs(activation_precision: str = \"fp4\") -> int:\n activation_precision = _normalize_activation_precision(activation_precision)\n cached = _STATIC_COMPACT_CUTOVER_PAIRS_CACHE.get(activation_precision)\n if cached is not None:\n return cached\n\n cutover_names: tuple[str, ...] = (\n \"FLASHINFER_B12X_STATIC_COMPACT_CUTOVER_PAIRS\",\n \"B12X_STATIC_COMPACT_CUTOVER_PAIRS\",\n \"B12X_DYNAMIC_STATIC_CUTOVER_PAIRS\",\n \"B12X_LEVEL10_STATIC_CUTOVER_PAIRS\",\n )\n cutover = _first_env(*cutover_names)\n if cutover is None:\n cached = _STATIC_COMPACT_CUTOVER_PAIRS_DEFAULT\n else:\n cached = max(0, int(cutover))\n _STATIC_COMPACT_CUTOVER_PAIRS_CACHE[activation_precision] = cached\n return cached\n\n\ndef _select_moe_mma_tiler_mn(\n routed_rows: int,\n n: int,\n *,\n resident_clusters: int | None = None,\n) -> Tuple[int, int]:\n \"\"\"Select optimal MoE tile shape based on routed rows and N dimension.\n\n Uses narrower 64x128 tiles when routed_rows <= 128 and default 128x128\n would leave SMs idle.\n \"\"\"\n sm_count = get_num_sm(torch.device(\"cuda\"))\n coarse_tile = (128, 128)\n if routed_rows <= 32 and n <= 256:\n return (64, 128)\n if resident_clusters is not None and resident_clusters < sm_count:\n return coarse_tile\n coarse_tiles = ((routed_rows + coarse_tile[0] - 1) // coarse_tile[0]) * (\n (n + coarse_tile[1] - 1) // coarse_tile[1]\n )\n # Single-token decode often lands exactly on the \"half the machine\"\n # boundary. Keeping the coarse 128x128 tile there leaves the M dimension\n # badly underfilled, so take the narrow 64x128 tile inclusive of equality.\n if routed_rows <= 64 or (\n routed_rows <= 128 and coarse_tiles <= max(1, sm_count // 2)\n ):\n return (64, 128)\n return (128, 128)\n\n\ndef _as_grouped_scale_view(\n scale_storage: torch.Tensor,\n rows: int,\n cols: int,\n) -> torch.Tensor:\n \"\"\"Create 6D MMA-compatible scale factor view from swizzled storage.\"\"\"\n batch = scale_storage.shape[0]\n rows_padded = _align_up(rows, 128)\n cols_padded = _align_up(cols // SF_VEC_SIZE, 4)\n sf = scale_storage.view(torch.float8_e4m3fn)\n sf = sf.view(batch, rows_padded // 128, cols_padded // 4, 32, 4, 4)\n return sf.permute(3, 4, 1, 5, 2, 0)\n\n\n# ---------------------------------------------------------------------------\n# Workspace\n# ---------------------------------------------------------------------------\n@dataclass(kw_only=True)\nclass Sm120StaticMoEWorkspace:\n \"\"\"Scratch buffers for one SM120 static MoE launch.\"\"\"\n\n state_E: int\n weight_E: int\n max_rows: int\n k: int\n n: int\n num_topk: int\n device: torch.device\n activation_precision: str\n\n # Buffers\n row_counts: torch.Tensor # [state_E] int32\n token_map: torch.Tensor # [state_E, max_rows] int32\n token_weights: torch.Tensor # [state_E, max_rows] float32\n packed_input: torch.Tensor # [state_E, max_rows, k//2] uint8\n packed_input_scale: torch.Tensor # [state_E, rows_pad_k, cols_pad_k] uint8\n barrier_count: torch.Tensor # [1] int32\n barrier_epoch: torch.Tensor # [1] int32\n active_expert_count: torch.Tensor # [1] int32\n weight_expert_ids: torch.Tensor # [state_E] int32\n global_to_local_expert: torch.Tensor # [weight_E] int32\n compact_topk_ids: torch.Tensor # [state_E] int32, for micro kernel pre-pass\n\n # Views (set after allocation)\n packed_a_view: torch.Tensor | None = None\n sfa_ptr: object = None\n packed_a_flat: torch.Tensor | None = None\n scale_flat: torch.Tensor | None = None\n\n # Direct micro planes (allocated only when the shape can take that path).\n dm_barrier_count: torch.Tensor | None = None\n dm_barrier_epoch: torch.Tensor | None = None\n dm_intermediate: torch.Tensor | None = None\n dm_input_gs: torch.Tensor | None = None\n dm_down_input_scale: torch.Tensor | None = None\n\n\ndef _direct_micro_candidate(k: int, n: int, num_topk: int, weight_E: int) -> bool:\n \"\"\"Whether any m in the tiny-decode band can run the direct micro kernel.\"\"\"\n return any(\n MoEDirectMicroKernel.is_supported(m, k, n, num_topk, weight_E)\n for m in range(1, _MICRO_MAX_TOKENS + 1)\n )\n\n\ndef allocate_sm120_static_workspace(\n *,\n state_E: int,\n weight_E: int,\n max_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation_precision: str = \"fp4\",\n) -> Sm120StaticMoEWorkspace:\n \"\"\"Allocate workspace buffers for the SM120 static MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"allocate_sm120_static_workspace only supports quant_mode='nvfp4'; \"\n \"use allocate_sm120_moe_workspace(..., quant_mode='w4a16') for W4A16.\"\n )\n\n rows_pad_k = _align_up(max_rows, 128)\n cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n _check_memref_limit(\"static packed_input\", state_E * max_rows * (k // 2))\n _check_memref_limit(\"static packed_input_scale\", state_E * rows_pad_k * cols_pad_k)\n packed_input = torch.empty(\n state_E, max_rows, k // 2, dtype=torch.uint8, device=device\n )\n\n workspace = Sm120StaticMoEWorkspace(\n state_E=state_E,\n weight_E=weight_E,\n max_rows=max_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation_precision=activation_precision,\n row_counts=torch.zeros(state_E, dtype=torch.int32, device=device),\n token_map=torch.zeros(state_E, max_rows, dtype=torch.int32, device=device),\n token_weights=torch.zeros(\n state_E, max_rows, dtype=torch.float32, device=device\n ),\n packed_input=packed_input,\n packed_input_scale=torch.empty(\n state_E, rows_pad_k, cols_pad_k, dtype=torch.uint8, device=device\n ),\n barrier_count=torch.zeros(1, dtype=torch.int32, device=device),\n barrier_epoch=torch.zeros(1, dtype=torch.int32, device=device),\n active_expert_count=torch.zeros(1, dtype=torch.int32, device=device),\n weight_expert_ids=torch.arange(state_E, dtype=torch.int32, device=device),\n global_to_local_expert=torch.empty(weight_E, dtype=torch.int32, device=device),\n compact_topk_ids=torch.empty(\n max(state_E, max_rows), dtype=torch.int32, device=device\n ),\n )\n\n # Finalize views\n sf_dtype = cutlass.Float8E4M3FN\n workspace.packed_a_view = workspace.packed_input.permute(1, 2, 0).view(\n torch.float4_e2m1fn_x2\n )\n workspace.packed_a_flat = workspace.packed_input.view(-1)\n workspace.scale_flat = workspace.packed_input_scale.view(-1)\n workspace.sfa_ptr = make_ptr(\n sf_dtype,\n workspace.packed_input_scale.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n\n # Direct micro reads weights by global expert id, so its planes are only\n # useful without EP remapping.\n if state_E == weight_E and _direct_micro_candidate(k, n, num_topk, weight_E):\n dm_rows = min(max_rows, _MICRO_MAX_TOKENS * num_topk)\n # The epoch-based barriers restore their slots after each launch, so\n # the zeroed allocation is the only reset needed (graph-replay safe).\n dm_slots = dm_rows + _MICRO_MAX_TOKENS * 16\n fc2_n_chunks = (n // 2 + 127) // 128\n # The fused kernel binds the intermediate as m * num_topk *\n # fc2_n_chunks * 128 u32 words; size for the largest supported m.\n dm_inter = _MICRO_MAX_TOKENS * num_topk * fc2_n_chunks * 128\n workspace.dm_barrier_count = torch.zeros(\n dm_slots, dtype=torch.int32, device=device\n )\n workspace.dm_barrier_epoch = torch.zeros(\n dm_slots, dtype=torch.int32, device=device\n )\n workspace.dm_intermediate = torch.empty(\n dm_inter, dtype=torch.float32, device=device\n )\n workspace.dm_input_gs = torch.empty(\n weight_E, dtype=torch.float32, device=device\n )\n workspace.dm_down_input_scale = torch.empty(\n weight_E, dtype=torch.float32, device=device\n )\n return workspace\n\n\n# ---------------------------------------------------------------------------\n# Weight views\n# ---------------------------------------------------------------------------\n@dataclass\nclass _WeightViews:\n w13_fp4: object = None\n down_fp4: object = None\n sfb_w13_ptr: object = None\n sfb_down_ptr: object = None\n w1_alpha: torch.Tensor | None = None\n w2_alpha: torch.Tensor | None = None\n w1_storage: torch.Tensor | None = None\n w1_scale_storage: torch.Tensor | None = None\n w2_storage: torch.Tensor | None = None\n w2_scale_storage: torch.Tensor | None = None\n _w13_sf_storage: torch.Tensor | None = None\n _down_sf_storage: torch.Tensor | None = None\n\n\ndef _register_cache_eviction(cache: Dict, key: Tuple, *source_tensors) -> None:\n \"\"\"Evict ``key`` when a source weight tensor is collected, so the cache\n follows the weights' lifetime instead of growing for the whole process.\n \"\"\"\n for tensor in source_tensors:\n if tensor is not None:\n weakref.finalize(tensor, cache.pop, key, None)\n\n\n_WEIGHT_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_weight_views(\n w1_fp4: torch.Tensor,\n w1_blockscale: torch.Tensor,\n w2_fp4: torch.Tensor,\n w2_blockscale: torch.Tensor,\n w1_alphas: torch.Tensor,\n w2_alphas: torch.Tensor,\n n: int,\n k: int,\n activation_precision: str = \"fp4\",\n) -> _WeightViews:\n \"\"\"Create permuted weight views for the static kernel.\n\n The kernel expects concatenated w13 data with shape [2*n, k//2, E]\n via a single TMA descriptor.\n \"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n tile_n = _level_tile_n(activation_precision)\n # The kernel splits w13 into gate/up halves by tile index. This only works\n # when the boundary between halves lands on a tile-aligned column.\n if n % tile_n != 0:\n raise ValueError(\n f\"intermediate_size ({n}) must be a multiple of {tile_n} \"\n f\"for the SM120 MoE kernel's gate/up tile split.\"\n )\n\n key = (\n activation_precision,\n w1_fp4.data_ptr(),\n w1_blockscale.data_ptr(),\n w1_alphas.data_ptr(),\n w2_fp4.data_ptr(),\n w2_blockscale.data_ptr(),\n w2_alphas.data_ptr(),\n )\n cached = _WEIGHT_CACHE.get(key)\n if cached is None:\n # Cache the fresh buffers (scale factors + fp32 alphas).\n w1_rows = w1_fp4.shape[1] # 2*n for gated, n for non-gated\n cached = (\n convert_sf_from_mma_layout(\n w1_blockscale, m=w1_rows, k=k, num_groups=w1_fp4.shape[0]\n ).contiguous(),\n convert_sf_from_mma_layout(\n w2_blockscale, m=k, k=n, num_groups=w2_fp4.shape[0]\n ).contiguous(),\n w1_alphas.contiguous().to(torch.float32),\n w2_alphas.contiguous().to(torch.float32),\n )\n _WEIGHT_CACHE[key] = cached\n _register_cache_eviction(\n _WEIGHT_CACHE,\n key,\n w1_fp4,\n w1_blockscale,\n w1_alphas,\n w2_fp4,\n w2_blockscale,\n w2_alphas,\n )\n w13_sf_contiguous, down_sf_contiguous, w1_alpha, w2_alpha = cached\n\n # Permute [E, w1_rows, k//2] -> [w1_rows, k//2, E] (view, no copy).\n sf_dtype = cutlass.Float8E4M3FN\n w13 = w1_fp4.permute(1, 2, 0)\n down = w2_fp4.permute(1, 2, 0)\n return _WeightViews(\n w13_fp4=w13.view(torch.float4_e2m1fn_x2),\n down_fp4=down.view(torch.float4_e2m1fn_x2),\n sfb_w13_ptr=make_ptr(\n sf_dtype,\n w13_sf_contiguous.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n ),\n sfb_down_ptr=make_ptr(\n sf_dtype,\n down_sf_contiguous.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n ),\n w1_alpha=w1_alpha,\n w2_alpha=w2_alpha,\n w1_storage=w1_fp4,\n w1_scale_storage=w13_sf_contiguous,\n w2_storage=w2_fp4,\n w2_scale_storage=down_sf_contiguous,\n _w13_sf_storage=w13_sf_contiguous,\n _down_sf_storage=down_sf_contiguous,\n )\n\n\n# ---------------------------------------------------------------------------\n# Kernel compilation cache\n# ---------------------------------------------------------------------------\n_STATIC_KERNEL_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_static_kernel(\n state_E: int,\n weight_E: int,\n m: int,\n k: int,\n n: int,\n num_topk: int,\n max_rows: int,\n *,\n topk_ids_dtype: torch.dtype = torch.int32,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n mac_override: int | None = None,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n):\n \"\"\"Compile (or retrieve cached) the SM120 static MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 static compiler\"\n )\n sf_vec_size = 16\n sm_count = get_num_sm(torch.device(\"cuda\"))\n mac = (\n mac_override\n if mac_override is not None\n else min(get_max_active_clusters(1), sm_count)\n )\n\n # Select tile size based on actual routed rows\n routed_rows = m * num_topk\n mma_tiler_mn = (128, 128)\n if activation_precision == \"fp4\" and num_topk > 1:\n mma_tiler_mn = _select_moe_mma_tiler_mn(routed_rows, n, resident_clusters=mac)\n\n cache_key = (\n \"static\",\n activation_precision,\n state_E,\n weight_E,\n m,\n k,\n n,\n num_topk,\n max_rows,\n mac,\n mma_tiler_mn,\n topk_ids_dtype,\n input_scales_are_reciprocal,\n fast_math,\n activation,\n swiglu_alpha,\n swiglu_beta,\n swiglu_limit,\n )\n cached = _STATIC_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n return cached\n\n ab_dtype = cutlass.Float4E2M1FN\n weight_dtype = cutlass.Float4E2M1FN\n sf_dtype = cutlass.Float8E4M3FN\n a_dtype = cutlass.BFloat16\n alpha_dtype = cutlass.Float32\n\n output_tile_count_n = max(1, (n + mma_tiler_mn[1] - 1) // mma_tiler_mn[1])\n kernel: Any = MoEStaticKernel(\n sf_vec_size=sf_vec_size,\n mma_tiler_mn=mma_tiler_mn,\n output_tile_count_n=output_tile_count_n,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n )\n\n is_gated = is_gated_activation(activation)\n w1_rows = (2 if is_gated else 1) * n # 2*n for gated, n for non-gated\n\n rows_pad_k = _align_up(max_rows, 128)\n cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n\n # Build fake tensors for compilation\n a_input_fake = cute.runtime.make_fake_compact_tensor(\n a_dtype,\n (m, k),\n stride_order=(1, 0),\n assumed_align=16,\n )\n topk_ids_cutlass_dtype = (\n cutlass.Int32 if topk_ids_dtype == torch.int32 else cutlass.Int64\n )\n topk_ids_align = 4 if topk_ids_dtype == torch.int32 else 8\n topk_ids_fake = cute.runtime.make_fake_compact_tensor(\n topk_ids_cutlass_dtype,\n (m * num_topk,),\n assumed_align=topk_ids_align,\n )\n topk_weights_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32,\n (m * num_topk,),\n assumed_align=4,\n )\n packed_a_fake = cute.runtime.make_fake_compact_tensor(\n ab_dtype,\n (max_rows, k, state_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfa_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n packed_a_storage_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (state_E * max_rows * (k // 2),),\n assumed_align=16,\n )\n scale_storage_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (state_E * rows_pad_k * cols_pad_k,),\n assumed_align=16,\n )\n barrier_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n barrier_epoch_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n b_w13_fake = cute.runtime.make_fake_compact_tensor(\n weight_dtype,\n (w1_rows, k, weight_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_w13_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n b_down_fake = cute.runtime.make_fake_compact_tensor(\n weight_dtype,\n (k, n, weight_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_down_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n row_counts_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E,),\n assumed_align=4,\n )\n active_expert_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n weight_expert_ids_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E,),\n assumed_align=4,\n )\n global_to_local_expert_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (weight_E,),\n assumed_align=4,\n )\n input_gs_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n down_alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n global_scale_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n scatter_fake = cute.runtime.make_fake_compact_tensor(\n a_dtype,\n (m, k),\n stride_order=(1, 0),\n assumed_align=16,\n )\n token_map_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E, max_rows),\n stride_order=(1, 0),\n assumed_align=4,\n )\n token_weights_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (state_E, max_rows),\n stride_order=(1, 0),\n assumed_align=16,\n )\n compiled = cute.compile(\n kernel,\n a_input_fake,\n topk_ids_fake,\n topk_weights_fake,\n packed_a_fake,\n sfa_fake,\n packed_a_storage_fake,\n scale_storage_fake,\n barrier_count_fake,\n barrier_epoch_fake,\n b_w13_fake,\n sfb_w13_fake,\n b_down_fake,\n sfb_down_fake,\n row_counts_fake,\n active_expert_count_fake,\n weight_expert_ids_fake,\n global_to_local_expert_fake,\n input_gs_fake,\n alpha_fake,\n down_alpha_fake,\n global_scale_fake,\n scatter_fake,\n token_map_fake,\n token_weights_fake,\n mac,\n current_cuda_stream(),\n options=\"--opt-level 2 --enable-tvm-ffi\",\n )\n\n result = (compiled, mac)\n _STATIC_KERNEL_CACHE[cache_key] = result\n return result\n\n\n_MICRO_KERNEL_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_micro_kernel(\n state_E: int,\n weight_E: int,\n m: int,\n k: int,\n n: int,\n num_topk: int,\n max_rows: int,\n *,\n topk_ids_dtype: torch.dtype = torch.int32,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n share_input_across_experts: bool = False,\n share_expert_scales: bool = False,\n single_token: bool = False,\n mac_override: int | None = None,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n):\n \"\"\"Compile (or retrieve cached) the SM120 micro MoE kernel.\"\"\"\n sf_vec_size = 16\n sm_count = get_num_sm(torch.device(\"cuda\"))\n mac = (\n mac_override\n if mac_override is not None\n else min(get_max_active_clusters(1), sm_count)\n )\n\n # Micro always selects tile from routed rows (not just for multi-topk)\n routed_rows = m * num_topk\n mma_tiler_mn = _select_moe_mma_tiler_mn(routed_rows, n)\n\n cache_key = (\n \"micro\",\n state_E,\n weight_E,\n m,\n k,\n n,\n num_topk,\n max_rows,\n mac,\n mma_tiler_mn,\n topk_ids_dtype,\n input_scales_are_reciprocal,\n fast_math,\n share_input_across_experts,\n share_expert_scales,\n single_token,\n activation,\n swiglu_alpha,\n swiglu_beta,\n swiglu_limit,\n )\n cached = _MICRO_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n return cached\n\n ab_dtype = cutlass.Float4E2M1FN\n sf_dtype = cutlass.Float8E4M3FN\n a_dtype = cutlass.BFloat16\n alpha_dtype = cutlass.Float32\n\n kernel = MoEMicroKernel(\n sf_vec_size=sf_vec_size,\n mma_tiler_mn=mma_tiler_mn,\n output_tile_count_n=max(1, (n + mma_tiler_mn[1] - 1) // mma_tiler_mn[1]),\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n share_input_across_experts=share_input_across_experts,\n share_expert_scales=share_expert_scales,\n single_token=single_token,\n )\n\n is_gated = is_gated_activation(activation)\n w1_rows = (2 if is_gated else 1) * n\n\n rows_pad_k = _align_up(max_rows, 128)\n cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n\n # Build fake tensors for compilation (identical to static kernel)\n a_input_fake = cute.runtime.make_fake_compact_tensor(\n a_dtype,\n (m, k),\n stride_order=(1, 0),\n assumed_align=16,\n )\n topk_ids_cutlass_dtype = (\n cutlass.Int32 if topk_ids_dtype == torch.int32 else cutlass.Int64\n )\n topk_ids_align = 4 if topk_ids_dtype == torch.int32 else 8\n topk_ids_fake = cute.runtime.make_fake_compact_tensor(\n topk_ids_cutlass_dtype,\n (m * num_topk,),\n assumed_align=topk_ids_align,\n )\n topk_weights_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32,\n (m * num_topk,),\n assumed_align=4,\n )\n packed_a_fake = cute.runtime.make_fake_compact_tensor(\n ab_dtype,\n (max_rows, k, state_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfa_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n packed_a_storage_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (state_E * max_rows * (k // 2),),\n assumed_align=16,\n )\n scale_storage_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (state_E * rows_pad_k * cols_pad_k,),\n assumed_align=16,\n )\n barrier_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n barrier_epoch_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n b_w13_fake = cute.runtime.make_fake_compact_tensor(\n ab_dtype,\n (w1_rows, k, weight_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_w13_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n b_down_fake = cute.runtime.make_fake_compact_tensor(\n ab_dtype,\n (k, n, weight_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_down_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n row_counts_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E,),\n assumed_align=4,\n )\n active_expert_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n weight_expert_ids_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E,),\n assumed_align=4,\n )\n global_to_local_expert_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (weight_E,),\n assumed_align=4,\n )\n input_gs_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n down_alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n global_scale_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n scatter_fake = cute.runtime.make_fake_compact_tensor(\n a_dtype,\n (m, k),\n stride_order=(1, 0),\n assumed_align=16,\n )\n token_map_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E, max_rows),\n stride_order=(1, 0),\n assumed_align=4,\n )\n token_weights_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (state_E, max_rows),\n stride_order=(1, 0),\n assumed_align=16,\n )\n compiled = cute.compile(\n kernel,\n a_input_fake,\n topk_ids_fake,\n topk_weights_fake,\n packed_a_fake,\n sfa_fake,\n packed_a_storage_fake,\n scale_storage_fake,\n barrier_count_fake,\n barrier_epoch_fake,\n b_w13_fake,\n sfb_w13_fake,\n b_down_fake,\n sfb_down_fake,\n row_counts_fake,\n active_expert_count_fake,\n weight_expert_ids_fake,\n global_to_local_expert_fake,\n input_gs_fake,\n alpha_fake,\n down_alpha_fake,\n global_scale_fake,\n scatter_fake,\n token_map_fake,\n token_weights_fake,\n mac,\n current_cuda_stream(),\n options=\"--opt-level 2 --enable-tvm-ffi\",\n )\n\n result = (compiled, mac)\n _MICRO_KERNEL_CACHE[cache_key] = result\n return result\n\n\n# The launch cache skips the per-launch build/configure; the kernel cache\n# dedupes compiles across keys that configure to the same artifact\n# (m=2..8 differ only in grid_x).\n_DIRECT_MICRO_LAUNCH_CACHE: Dict[Tuple, Tuple] = {}\n_DIRECT_MICRO_KERNEL_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_direct_micro_kernel(\n weight_E: int,\n m: int,\n k: int,\n n: int,\n num_topk: int,\n *,\n topk_ids_dtype: torch.dtype = torch.int32,\n fast_math: bool = True,\n share_input_across_experts: bool = False,\n share_expert_scales: bool = False,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n device: torch.device | None = None,\n):\n \"\"\"Compile (or retrieve cached) the SM120 direct micro MoE kernel.\n\n Returns (compiled, grid_x, accepts_block_dim).\n \"\"\"\n if activation != SWIGLUOAI_UNINTERLEAVE:\n # The kernel constructor only accepts configurable swiglu parameters\n # for swigluoai; other activations use its normalized defaults\n # (accept-and-ignore, matching the MMA kernels).\n swiglu_alpha = None\n swiglu_beta = None\n swiglu_limit = None\n launch_key = (\n weight_E,\n m,\n k,\n n,\n num_topk,\n topk_ids_dtype,\n fast_math,\n share_input_across_experts,\n share_expert_scales,\n activation,\n swiglu_alpha,\n swiglu_beta,\n swiglu_limit,\n str(_canonical_cuda_device(device)) if device is not None else None,\n )\n cached = _DIRECT_MICRO_LAUNCH_CACHE.get(launch_key)\n if cached is not None:\n return cached\n kernel = build_direct_micro_kernel(\n weight_E,\n m,\n k,\n n,\n num_topk,\n activation=activation,\n fast_math=fast_math,\n share_input_across_experts=share_input_across_experts,\n share_expert_scales=share_expert_scales,\n single_token=m == 1,\n swiglu_limit=swiglu_limit,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n device=device,\n )\n compile_key = (\"direct_micro\", kernel.__cache_key__, topk_ids_dtype)\n entry = _DIRECT_MICRO_KERNEL_CACHE.get(compile_key)\n if entry is None:\n compiled = compile_direct_micro_kernel(kernel, topk_ids_dtype=topk_ids_dtype)\n # Register pressure can cap the launchable CTA below the fused body's\n # 512 threads; probe once per compiled kernel.\n accepts = compiled_direct_micro_accepts_block_dim(\n compiled, kernel.launch_block_dim\n )\n entry = (compiled, accepts)\n _DIRECT_MICRO_KERNEL_CACHE[compile_key] = entry\n compiled, accepts = entry\n cached = (compiled, kernel.grid_x, accepts)\n _DIRECT_MICRO_LAUNCH_CACHE[launch_key] = cached\n return cached\n\n\n# ---------------------------------------------------------------------------\n# Launch\n# ---------------------------------------------------------------------------\ndef _expand_to_experts(t: torch.Tensor, num_experts: int) -> torch.Tensor:\n \"\"\"Broadcast a scalar or [1] tensor to [num_experts], always fp32.\n\n Both branches must cast: the kernels are compiled against fp32 fake\n tensors for every per-expert scale.\n \"\"\"\n if t.numel() == 1:\n return t.to(torch.float32).expand(num_experts).contiguous()\n return t.contiguous().to(torch.float32)\n\n\ndef launch_sm120_static_moe(\n *,\n workspace: Sm120StaticMoEWorkspace,\n weights: _WeightViews,\n a: torch.Tensor,\n topk_ids: torch.Tensor,\n topk_weights: torch.Tensor,\n input_gs: torch.Tensor,\n down_input_scale: torch.Tensor,\n scatter_output: torch.Tensor,\n num_experts: int,\n num_tokens: int,\n k: int,\n n: int,\n top_k: int,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n) -> torch.Tensor:\n \"\"\"Launch the SM120 static, micro, or direct micro MoE kernel.\n\n The direct micro kernel takes tiny decode batches (m <= 8, routed_rows\n < 64) when it supports the shape, the MMA micro kernel takes the rest of\n its band (routed_rows <= 20-40), and the static kernel takes the rest.\n The MMA micro path runs a Triton pre-pass to compact routing IDs before\n launching; direct micro routes on global expert ids directly.\n \"\"\"\n _check_memref_limit(\"scatter_output\", scatter_output.numel())\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 static launcher\"\n )\n\n # Flatten routing tensors\n flat_ids = topk_ids.view(-1).to(torch.int32)\n flat_weights = topk_weights.view(-1).to(torch.float32)\n routed_rows = num_tokens * top_k\n\n # Capture whether input_gs was a single shared scalar BEFORE expansion:\n # the m=1 relu2 shared-input micro optimization only applies when every\n # expert sees the same FC1-input global scale.\n input_gs_is_shared = input_gs.numel() == 1\n down_input_scale_is_shared = down_input_scale.numel() == 1\n\n # Broadcast scalar scales to per-expert [E] tensors\n input_gs = _expand_to_experts(input_gs, num_experts)\n down_input_scale = _expand_to_experts(down_input_scale, num_experts)\n\n # Shared-scale flags let compact W4A4 micro match the ReLU2 single-token\n # specialization.\n share_input_across_experts = (\n activation == \"relu2\"\n and num_tokens == 1\n and input_gs_is_shared\n and _MICRO_SHARE_INPUT_ACROSS_EXPERTS\n )\n share_expert_scales = (\n activation == \"relu2\" and input_gs_is_shared and down_input_scale_is_shared\n )\n\n # Direct micro takes its band before the MMA micro decision. It reads\n # weights by global expert id, so EP shapes keep the compact path.\n use_direct_micro = (\n activation_precision == \"fp4\"\n and workspace.state_E == num_experts\n and workspace.dm_barrier_count is not None\n and workspace.dm_barrier_count.numel() >= routed_rows + num_tokens * 16\n and num_tokens <= _MICRO_MAX_TOKENS\n and routed_rows < _DIRECT_MICRO_CUTOVER_PAIRS\n and n <= _DIRECT_MICRO_MAX_N\n and MoEDirectMicroKernel.is_supported(num_tokens, k, n, top_k, num_experts)\n )\n if _FORCED_BACKEND is not None:\n if _FORCED_BACKEND == \"direct_micro\":\n if workspace.dm_barrier_count is None or not (\n MoEDirectMicroKernel.is_supported(num_tokens, k, n, top_k, num_experts)\n ):\n raise ValueError(\n \"forced direct_micro backend cannot run this shape \"\n f\"(m={num_tokens}, k={k}, n={n}, top_k={top_k})\"\n )\n if workspace.dm_barrier_count.numel() < routed_rows + num_tokens * 16:\n raise ValueError(\n \"forced direct_micro backend exceeds the workspace barrier \"\n f\"capacity ({workspace.dm_barrier_count.numel()} slots < \"\n f\"{routed_rows} routed rows + {num_tokens * 16})\"\n )\n use_direct_micro = True\n else:\n use_direct_micro = False\n if use_direct_micro:\n compiled, grid_x, block_ok = _get_direct_micro_kernel(\n num_experts,\n num_tokens,\n k,\n n,\n top_k,\n topk_ids_dtype=flat_ids.dtype,\n fast_math=fast_math,\n share_input_across_experts=share_input_across_experts,\n share_expert_scales=share_expert_scales,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n device=a.device,\n )\n if not block_ok:\n if _FORCED_BACKEND == \"direct_micro\":\n raise RuntimeError(\"compiled direct micro MoE kernel cannot launch\")\n use_direct_micro = False\n if use_direct_micro:\n # The kernel takes multiplier-form scales only; invert reciprocal\n # inputs into the persistent workspace planes (zeros stay zero,\n # matching the MMA kernels).\n if input_scales_are_reciprocal:\n workspace.dm_input_gs.copy_(\n torch.where(input_gs != 0, 1.0 / input_gs, input_gs)\n )\n workspace.dm_down_input_scale.copy_(\n torch.where(\n down_input_scale != 0, 1.0 / down_input_scale, down_input_scale\n )\n )\n launch_gs = workspace.dm_input_gs\n launch_down = workspace.dm_down_input_scale\n else:\n launch_gs = input_gs\n launch_down = down_input_scale\n MoEDirectMicroKernel.launch(\n compiled,\n x=a,\n w1_fp4=weights.w1_storage,\n w1_blockscale=weights.w1_scale_storage,\n w1_alphas=weights.w1_alpha,\n a1_gscale=launch_gs,\n a2_gscale=launch_down,\n inter_fp32=workspace.dm_intermediate,\n w2_fp4=weights.w2_storage,\n w2_blockscale=weights.w2_scale_storage,\n w2_alphas=weights.w2_alpha,\n topk_ids=flat_ids,\n topk_weights=flat_weights,\n out=scatter_output,\n barrier_count=workspace.dm_barrier_count,\n barrier_epoch=workspace.dm_barrier_epoch,\n m=num_tokens,\n grid_x=grid_x,\n )\n return scatter_output\n\n # Decide micro vs static\n micro_cutover = _MICRO_COMPACT_CUTOVER_PAIRS\n if top_k > 1:\n micro_cutover = _MICRO_COMPACT_CUTOVER_PAIRS_MULTI_TOPK\n use_micro = (\n activation_precision == \"fp4\"\n and num_tokens <= _MICRO_MAX_TOKENS\n and routed_rows <= micro_cutover\n )\n if _FORCED_BACKEND is not None:\n if _FORCED_BACKEND == \"micro\":\n # Forced mode raises on correctness violations, never falls back.\n if num_tokens > _MICRO_MAX_TOKENS:\n raise ValueError(\n f\"forced micro backend supports at most {_MICRO_MAX_TOKENS} \"\n f\"tokens (got {num_tokens})\"\n )\n if flat_ids.numel() > workspace.compact_topk_ids.numel():\n raise ValueError(\n \"forced micro backend exceeds the workspace compact-id \"\n f\"capacity ({workspace.compact_topk_ids.numel()} < \"\n f\"{flat_ids.numel()})\"\n )\n use_micro = True\n else:\n use_micro = False\n\n sm_count = get_num_sm(torch.device(\"cuda\"))\n base_mac = min(get_max_active_clusters(1), sm_count)\n tuned_static_mac = _lookup_mac_ladder(_STATIC_MAC_LADDER, routed_rows)\n static_mac = min(tuned_static_mac or base_mac, base_mac)\n if activation_precision == \"fp4\" and not use_micro and routed_rows < 40:\n static_mac = min(static_mac, 64)\n\n if use_micro:\n assert flat_ids.numel() <= workspace.compact_topk_ids.numel(), (\n f\"compact_topk_ids buffer too small: \"\n f\"{workspace.compact_topk_ids.numel()} < {flat_ids.numel()}\"\n )\n # Single-token ReLU2 is non-gated, so the micro kernel can launch on\n # the routed expert ids directly. Gated SiLU still goes through the\n # compact id buffer so the kernel can map compact launch ids back to\n # the physical gate/up weight experts.\n if num_tokens == 1 and activation == \"relu2\":\n launch_ids = flat_ids\n elif num_tokens == 1:\n compact_ids = workspace.compact_topk_ids[: flat_ids.numel()]\n compact_ids.copy_(\n torch.arange(\n flat_ids.numel(),\n device=flat_ids.device,\n dtype=torch.int32,\n )\n )\n workspace.weight_expert_ids[: flat_ids.numel()].copy_(\n flat_ids.to(torch.int32)\n )\n workspace.active_expert_count.fill_(flat_ids.numel())\n launch_ids = compact_ids\n else:\n compact_ids = workspace.compact_topk_ids[: flat_ids.numel()]\n from .triton_compact import compact_topk_ids as _triton_compact_topk_ids\n\n _triton_compact_topk_ids(\n flat_ids,\n compact_ids,\n workspace.weight_expert_ids,\n workspace.active_expert_count,\n )\n launch_ids = compact_ids\n # Select micro MAC: min of tuned ladder, work tiles, and hardware limit.\n micro_work_tiles = max(1, routed_rows * max(1, (n + 128 - 1) // 128))\n tuned_mac = _lookup_mac_ladder(_MICRO_MAC_LADDER, routed_rows)\n micro_mac = min(tuned_mac or base_mac, micro_work_tiles, base_mac)\n compiled, mac = _get_micro_kernel(\n workspace.state_E,\n num_experts,\n num_tokens,\n k,\n n,\n top_k,\n workspace.max_rows,\n topk_ids_dtype=launch_ids.dtype,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n share_input_across_experts=share_input_across_experts,\n share_expert_scales=share_expert_scales,\n single_token=num_tokens == 1,\n mac_override=micro_mac,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n )\n else:\n compiled, mac = _get_static_kernel(\n workspace.state_E,\n num_experts,\n num_tokens,\n k,\n n,\n top_k,\n workspace.max_rows,\n topk_ids_dtype=torch.int32,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n mac_override=static_mac,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n activation_precision=activation_precision,\n )\n launch_ids = flat_ids\n\n # Pointer arguments must be passed as raw ints (data_ptr()) at runtime.\n runtime_args: Tuple[Any, ...] = (\n a,\n launch_ids,\n flat_weights,\n workspace.packed_a_view,\n workspace.packed_input_scale.data_ptr(),\n workspace.packed_a_flat,\n workspace.scale_flat,\n workspace.barrier_count,\n workspace.barrier_epoch,\n weights.w13_fp4,\n weights._w13_sf_storage.data_ptr(),\n weights.down_fp4,\n weights._down_sf_storage.data_ptr(),\n workspace.row_counts,\n workspace.active_expert_count,\n workspace.weight_expert_ids,\n workspace.global_to_local_expert,\n input_gs,\n weights.w1_alpha,\n weights.w2_alpha,\n down_input_scale,\n scatter_output,\n workspace.token_map,\n workspace.token_weights,\n )\n compiled(*runtime_args, current_cuda_stream())\n\n return scatter_output\n\n\n# ==========================================================================\n# Dynamic backend\n# ==========================================================================\n\n\ndef select_sm120_moe_backend(\n *,\n num_tokens: int,\n num_topk: int,\n activation_precision: str = \"fp4\",\n quant_mode: str | None = None,\n) -> str:\n \"\"\"Pick static or dynamic backend based on routed-pair count.\"\"\"\n mode = _normalize_quant_mode(quant_mode, activation_precision)\n if mode == \"w4a16\":\n return \"w4a16\"\n if _FORCED_BACKEND == \"dynamic\":\n return \"dynamic\"\n if _FORCED_BACKEND in (\"static\", \"micro\", \"direct_micro\"):\n # Both micro variants launch through the static workspace path.\n return \"static\"\n routed_rows = num_tokens * num_topk\n if routed_rows <= _get_static_compact_cutover_pairs(\"fp4\"):\n return \"static\"\n return \"dynamic\"\n\n\n# ---------------------------------------------------------------------------\n# Dynamic workspace\n# ---------------------------------------------------------------------------\n@dataclass(kw_only=True)\nclass Sm120DynamicMoEWorkspace:\n \"\"\"Scratch buffers for one SM120 dynamic MoE launch.\"\"\"\n\n state_E: int\n weight_E: int\n max_rows: int\n k: int\n n: int\n num_topk: int\n device: torch.device\n activation_precision: str\n\n # Core buffers\n row_counts: torch.Tensor\n token_map: torch.Tensor\n token_weights: torch.Tensor\n packed_input: torch.Tensor\n packed_input_scale: torch.Tensor\n barrier_count: torch.Tensor\n barrier_epoch: torch.Tensor\n\n # Dynamic-specific\n routed_rows_capacity: int\n physical_tiles_capacity: int\n task_capacity: int\n # The M-tile the geometry above was sized for; launches must build the\n # kernel with the same tile.\n tile_m: int = _LEVEL_TILE_M\n expert_write_rows: torch.Tensor\n expert_tile_base: torch.Tensor\n pair_head: torch.Tensor\n task_head: torch.Tensor\n task_tail: torch.Tensor\n task_expert: torch.Tensor\n task_valid_rows: torch.Tensor\n\n # Views\n packed_a_view: torch.Tensor | None = None\n sfa_ptr: object = None\n packed_a_flat: torch.Tensor | None = None\n scale_flat: torch.Tensor | None = None\n\n\ndef _dynamic_task_geometry(\n state_E: int,\n n: int,\n routed_rows: int,\n *,\n tile_m: int = _LEVEL_TILE_M,\n tile_n: int = _LEVEL_TILE_N,\n):\n \"\"\"Compute task queue dimensions from problem geometry.\n\n Each active expert can introduce at most one additional physical tile\n beyond the base count (due to per-expert tail padding). The task queue\n holds one entry per (m_tile, slice_group) pair — NOT multiplied by E.\n \"\"\"\n routed_rows = max(1, routed_rows)\n base_m_tiles = _align_up(routed_rows, tile_m) // tile_m\n active_expert_upper_bound = min(state_E, routed_rows)\n max_m_tiles = max(1, base_m_tiles + active_expert_upper_bound - 1)\n gate_tile_cnt = max(1, (n + tile_n - 1) // tile_n)\n slice_groups = max(\n 1, (gate_tile_cnt + _DYNAMIC_SLICE_CHUNK - 1) // _DYNAMIC_SLICE_CHUNK\n )\n max_tasks = max_m_tiles * slice_groups\n return max_m_tiles, gate_tile_cnt, max_tasks\n\n\ndef allocate_sm120_dynamic_workspace(\n *,\n state_E: int,\n weight_E: int,\n routed_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation_precision: str = \"fp4\",\n activation: str = \"silu\",\n) -> Sm120DynamicMoEWorkspace:\n \"\"\"Allocate workspace buffers for the SM120 dynamic MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"allocate_sm120_dynamic_workspace only supports quant_mode='nvfp4'; \"\n \"use allocate_sm120_moe_workspace(..., quant_mode='w4a16') for W4A16.\"\n )\n tile_m = _select_dynamic_tile_m(routed_rows, state_E, activation)\n physical_tiles, _, max_tasks = _dynamic_task_geometry(\n state_E,\n n,\n routed_rows,\n tile_m=tile_m,\n tile_n=_level_tile_n(activation_precision),\n )\n rows_padded = physical_tiles * tile_m\n # The kernel addresses activation scales in 128-row SF atoms regardless of\n # tile_m, so the scale plane must cover the last partial atom.\n scale_rows = _align_up(rows_padded, 128)\n cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n _check_memref_limit(\"dynamic packed_input\", rows_padded * (k // 2))\n _check_memref_limit(\"dynamic packed_input_scale\", scale_rows * cols_pad_k)\n packed_input = torch.empty(1, rows_padded, k // 2, dtype=torch.uint8, device=device)\n\n workspace = Sm120DynamicMoEWorkspace(\n state_E=state_E,\n weight_E=weight_E,\n max_rows=rows_padded,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation_precision=activation_precision,\n routed_rows_capacity=routed_rows,\n physical_tiles_capacity=physical_tiles,\n task_capacity=max_tasks,\n tile_m=tile_m,\n row_counts=torch.zeros(state_E, dtype=torch.int32, device=device),\n token_map=torch.zeros(rows_padded, dtype=torch.int32, device=device),\n token_weights=torch.zeros(rows_padded, dtype=torch.float32, device=device),\n packed_input=packed_input,\n packed_input_scale=torch.empty(\n scale_rows, cols_pad_k, dtype=torch.uint8, device=device\n ),\n barrier_count=torch.zeros(1, dtype=torch.int32, device=device),\n barrier_epoch=torch.zeros(1, dtype=torch.int32, device=device),\n expert_write_rows=torch.zeros(state_E, dtype=torch.int32, device=device),\n expert_tile_base=torch.zeros(state_E + 1, dtype=torch.int32, device=device),\n pair_head=torch.zeros(1, dtype=torch.int32, device=device),\n task_head=torch.zeros(1, dtype=torch.int32, device=device),\n task_tail=torch.zeros(1, dtype=torch.int32, device=device),\n task_expert=torch.zeros(max_tasks, dtype=torch.int32, device=device),\n task_valid_rows=torch.zeros(max_tasks, dtype=torch.int32, device=device),\n )\n\n # Finalize views\n sf_dtype = cutlass.Float8E4M3FN\n workspace.packed_a_view = workspace.packed_input.permute(1, 2, 0).view(\n torch.float4_e2m1fn_x2\n )\n workspace.packed_a_flat = workspace.packed_input.view(-1)\n workspace.scale_flat = workspace.packed_input_scale.view(-1)\n workspace.sfa_ptr = make_ptr(\n sf_dtype,\n workspace.packed_input_scale.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n return workspace\n\n\n# ---------------------------------------------------------------------------\n# Dynamic kernel compilation\n# ---------------------------------------------------------------------------\n\n\nclass _DynamicMoELaunch:\n \"\"\"Thin JIT wrapper that makes num_tokens and max_rows runtime Int32.\"\"\"\n\n def __init__(self, kernel, k, num_topk, activation_precision: str = \"fp4\"):\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 dynamic launcher wrapper\"\n )\n self._kernel = kernel\n self._k = k\n self._packed_storage_cols = k // 2\n self._num_topk = num_topk\n self._cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n\n @cute.jit\n def __call__(\n self,\n a_ptr: cute.Pointer,\n topk_ids_ptr: cute.Pointer,\n topk_weights_ptr: cute.Pointer,\n packed_a_ptr: cute.Pointer,\n sfa_ptr: cute.Pointer,\n packed_a_storage_ptr: cute.Pointer,\n scale_storage_ptr: cute.Pointer,\n barrier_count: cute.Tensor,\n barrier_epoch: cute.Tensor,\n pair_head: cute.Tensor,\n task_head: cute.Tensor,\n task_tail: cute.Tensor,\n task_expert_ptr: cute.Pointer,\n task_valid_rows_ptr: cute.Pointer,\n b_w13: cute.Tensor,\n sfb_w13_ptr: cute.Pointer,\n b_down: cute.Tensor,\n sfb_down_ptr: cute.Pointer,\n row_counts: cute.Tensor,\n expert_write_rows: cute.Tensor,\n expert_tile_base: cute.Tensor,\n input_global_scale: cute.Tensor,\n alpha: cute.Tensor,\n down_alpha: cute.Tensor,\n global_scale: cute.Tensor,\n scatter_ptr: cute.Pointer,\n token_map_ptr: cute.Pointer,\n token_weights_ptr: cute.Pointer,\n num_tokens: cutlass.Int32,\n max_rows: cutlass.Int32,\n rows_padded: cutlass.Int32,\n max_tasks: cutlass.Int32,\n max_active_clusters: cutlass.Constexpr,\n stream,\n ):\n a_input = cute.make_tensor(\n a_ptr, layout=cute.make_layout((num_tokens, self._k), stride=(self._k, 1))\n )\n topk_ids = cute.make_tensor(\n topk_ids_ptr,\n layout=cute.make_layout((num_tokens * self._num_topk,), stride=(1,)),\n )\n topk_weights_t = cute.make_tensor(\n topk_weights_ptr,\n layout=cute.make_layout((num_tokens * self._num_topk,), stride=(1,)),\n )\n scatter_output = cute.make_tensor(\n scatter_ptr,\n layout=cute.make_layout((num_tokens, self._k), stride=(self._k, 1)),\n )\n packed_a = cute.make_tensor(\n packed_a_ptr,\n layout=cute.make_layout(\n (rows_padded, self._k, 1), stride=(self._k, 1, rows_padded * self._k)\n ),\n )\n packed_a_storage = cute.make_tensor(\n packed_a_storage_ptr,\n layout=cute.make_layout(\n (rows_padded * self._packed_storage_cols,), stride=(1,)\n ),\n )\n # Activation scales live in 128-row SF atoms; the plane is allocated\n # through the last partial atom even when rows_padded is not aligned.\n scale_rows = ((rows_padded + 127) // 128) * 128\n scale_storage = cute.make_tensor(\n scale_storage_ptr,\n layout=cute.make_layout((scale_rows * self._cols_pad_k,), stride=(1,)),\n )\n token_map = cute.make_tensor(\n token_map_ptr, layout=cute.make_layout((rows_padded,), stride=(1,))\n )\n token_weights_t = cute.make_tensor(\n token_weights_ptr, layout=cute.make_layout((rows_padded,), stride=(1,))\n )\n task_expert = cute.make_tensor(\n task_expert_ptr, layout=cute.make_layout((max_tasks,), stride=(1,))\n )\n task_valid_rows = cute.make_tensor(\n task_valid_rows_ptr, layout=cute.make_layout((max_tasks,), stride=(1,))\n )\n self._kernel(\n a_input,\n topk_ids,\n topk_weights_t,\n packed_a,\n sfa_ptr,\n packed_a_storage,\n scale_storage,\n barrier_count,\n barrier_epoch,\n pair_head,\n task_head,\n task_tail,\n task_expert,\n task_valid_rows,\n b_w13,\n sfb_w13_ptr,\n b_down,\n sfb_down_ptr,\n row_counts,\n expert_write_rows,\n expert_tile_base,\n input_global_scale,\n alpha,\n down_alpha,\n global_scale,\n scatter_output,\n token_map,\n token_weights_t,\n max_active_clusters=max_active_clusters,\n stream=stream,\n )\n\n\n_DYNAMIC_KERNEL_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_dynamic_kernel(\n E: int,\n m: int,\n k: int,\n n: int,\n num_topk: int,\n max_rows: int,\n *,\n topk_ids_dtype: torch.dtype = torch.int32,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n share_input_across_experts: bool = False,\n tile_m: int = _LEVEL_TILE_M,\n):\n \"\"\"Compile (or retrieve cached) the SM120 dynamic MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 dynamic compiler\"\n )\n share_input_across_experts = bool(\n share_input_across_experts and activation_precision == \"fp4\"\n )\n sf_vec_size = 16\n sm_count = get_num_sm(torch.device(\"cuda\"))\n base_mac = min(get_max_active_clusters(1), sm_count)\n tuned_mac = _lookup_mac_ladder(_DYNAMIC_MAC_LADDER, m * num_topk)\n mac = min(tuned_mac or base_mac, base_mac)\n # tile_m comes from the workspace's shared selection so the kernel's task\n # and scale indexing matches the allocated scratch geometry.\n mma_tiler_mn = (tile_m, _level_tile_n(activation_precision))\n\n cache_key = (\n \"dynamic\",\n activation_precision,\n E,\n k,\n n,\n num_topk,\n mac,\n mma_tiler_mn,\n topk_ids_dtype,\n input_scales_are_reciprocal,\n fast_math,\n activation,\n swiglu_alpha,\n swiglu_beta,\n swiglu_limit,\n share_input_across_experts,\n )\n cached = _DYNAMIC_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n return cached\n\n is_gated = is_gated_activation(activation)\n w1_rows = (2 if is_gated else 1) * n\n\n scratch_dtype = cutlass.Float4E2M1FN\n weight_dtype = cutlass.Float4E2M1FN\n sf_dtype = cutlass.Float8E4M3FN\n a_dtype = cutlass.BFloat16\n alpha_dtype = cutlass.Float32\n\n kernel: Any = MoEDynamicKernel(\n sf_vec_size=sf_vec_size,\n mma_tiler_mn=mma_tiler_mn,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n share_input_across_experts=share_input_across_experts,\n )\n launch = _DynamicMoELaunch(\n kernel,\n k=k,\n num_topk=num_topk,\n activation_precision=activation_precision,\n )\n\n topk_ids_cutlass_dtype = (\n cutlass.Int32 if topk_ids_dtype == torch.int32 else cutlass.Int64\n )\n topk_ids_align = 4 if topk_ids_dtype == torch.int32 else 8\n\n # Runtime-shaped tensors passed as pointers\n a_input_fake = make_ptr(a_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n topk_ids_fake = make_ptr(\n topk_ids_cutlass_dtype,\n topk_ids_align,\n cute.AddressSpace.gmem,\n assumed_align=topk_ids_align,\n )\n topk_weights_fake = make_ptr(\n cutlass.Float32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n packed_a_fake = make_ptr(\n scratch_dtype, 16, cute.AddressSpace.gmem, assumed_align=16\n )\n sfa_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n packed_a_storage_fake = make_ptr(\n cutlass.Uint8, 16, cute.AddressSpace.gmem, assumed_align=16\n )\n scale_storage_fake = make_ptr(\n cutlass.Uint8, 16, cute.AddressSpace.gmem, assumed_align=16\n )\n\n barrier_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n barrier_epoch_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n pair_head_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n task_head_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n task_tail_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n\n task_expert_fake = make_ptr(\n cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n task_valid_rows_fake = make_ptr(\n cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n\n b_w13_fake = cute.runtime.make_fake_compact_tensor(\n weight_dtype,\n (w1_rows, k, E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_w13_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n b_down_fake = cute.runtime.make_fake_compact_tensor(\n weight_dtype,\n (k, n, E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_down_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n row_counts_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (E,), assumed_align=4\n )\n expert_write_rows_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (E,), assumed_align=4\n )\n expert_tile_base_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (E + 1,), assumed_align=4\n )\n input_gs_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype, (E,), assumed_align=16\n )\n alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype, (E,), assumed_align=16\n )\n down_alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype, (E,), assumed_align=16\n )\n global_scale_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype, (E,), assumed_align=16\n )\n scatter_fake = make_ptr(a_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n token_map_fake = make_ptr(cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4)\n token_weights_fake = make_ptr(\n alpha_dtype, 16, cute.AddressSpace.gmem, assumed_align=16\n )\n\n compiled = cute.compile(\n launch,\n a_input_fake,\n topk_ids_fake,\n topk_weights_fake,\n packed_a_fake,\n sfa_fake,\n packed_a_storage_fake,\n scale_storage_fake,\n barrier_count_fake,\n barrier_epoch_fake,\n pair_head_fake,\n task_head_fake,\n task_tail_fake,\n task_expert_fake,\n task_valid_rows_fake,\n b_w13_fake,\n sfb_w13_fake,\n b_down_fake,\n sfb_down_fake,\n row_counts_fake,\n expert_write_rows_fake,\n expert_tile_base_fake,\n input_gs_fake,\n alpha_fake,\n down_alpha_fake,\n global_scale_fake,\n scatter_fake,\n token_map_fake,\n token_weights_fake,\n 1,\n 1,\n 1,\n 1, # runtime Int32 placeholders\n mac,\n current_cuda_stream(),\n options=\"--opt-level 2 --enable-tvm-ffi\",\n )\n\n result = (compiled, mac)\n _DYNAMIC_KERNEL_CACHE[cache_key] = result\n return result\n\n\n# ---------------------------------------------------------------------------\n# Dynamic launch\n# ---------------------------------------------------------------------------\ndef launch_sm120_dynamic_moe(\n *,\n workspace: Sm120DynamicMoEWorkspace,\n weights: _WeightViews,\n a: torch.Tensor,\n topk_ids: torch.Tensor,\n topk_weights: torch.Tensor,\n input_gs: torch.Tensor,\n down_input_scale: torch.Tensor,\n scatter_output: torch.Tensor,\n num_experts: int,\n num_tokens: int,\n k: int,\n n: int,\n top_k: int,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n) -> torch.Tensor:\n \"\"\"Launch the SM120 dynamic MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 dynamic launcher\"\n )\n _check_memref_limit(\"scatter_output\", scatter_output.numel())\n flat_ids = topk_ids.view(-1).to(torch.int32)\n flat_weights = topk_weights.view(-1).to(torch.float32)\n input_gs_is_shared = input_gs.numel() == 1\n\n # Broadcast scalar scales to per-expert [E] tensors\n input_gs = _expand_to_experts(input_gs, num_experts)\n down_input_scale = _expand_to_experts(down_input_scale, num_experts)\n\n compiled, mac = _get_dynamic_kernel(\n num_experts,\n num_tokens,\n k,\n n,\n top_k,\n workspace.max_rows,\n topk_ids_dtype=torch.int32,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n activation_precision=activation_precision,\n share_input_across_experts=input_gs_is_shared,\n tile_m=workspace.tile_m,\n )\n\n # Dynamic kernel: runtime-shaped args are DataPointer (pass data_ptr()),\n # fixed-shape args are Tensor (pass torch tensor directly).\n runtime_args: Tuple[Any, ...] = (\n a.data_ptr(),\n flat_ids.data_ptr(),\n flat_weights.data_ptr(),\n workspace.packed_a_view.data_ptr(),\n workspace.packed_input_scale.data_ptr(),\n workspace.packed_a_flat.data_ptr(),\n workspace.scale_flat.data_ptr(),\n workspace.barrier_count,\n workspace.barrier_epoch,\n workspace.pair_head,\n workspace.task_head,\n workspace.task_tail,\n workspace.task_expert.data_ptr(),\n workspace.task_valid_rows.data_ptr(),\n weights.w13_fp4,\n weights._w13_sf_storage.data_ptr(),\n weights.down_fp4,\n weights._down_sf_storage.data_ptr(),\n workspace.row_counts,\n workspace.expert_write_rows,\n workspace.expert_tile_base,\n input_gs,\n weights.w1_alpha,\n weights.w2_alpha,\n down_input_scale,\n scatter_output.data_ptr(),\n workspace.token_map.data_ptr(),\n workspace.token_weights.data_ptr(),\n num_tokens,\n workspace.max_rows,\n workspace.physical_tiles_capacity * workspace.tile_m,\n workspace.task_capacity,\n )\n compiled(*runtime_args, current_cuda_stream())\n\n return scatter_output\n\n\n# ==========================================================================\n# W4A16 route-packing implementation\n# ==========================================================================\n@dataclass(kw_only=True)\nclass Sm120W4A16MoEWorkspace:\n \"\"\"Scratch buffers for the SM120 W4A16 MoE path.\"\"\"\n\n state_E: int\n weight_E: int\n max_rows: int\n k: int\n n: int\n num_topk: int\n device: torch.device\n activation: str\n activation_precision: str\n quant_mode: str\n routed_rows_capacity: int\n route_num_experts: int\n\n intermediate_cache13: torch.Tensor\n intermediate_cache2: torch.Tensor\n fc1_c_tmp: torch.Tensor\n fc2_c_tmp: torch.Tensor\n packed_route_indices: torch.Tensor\n block_expert_ids: torch.Tensor\n packed_route_count: torch.Tensor\n expert_offsets: torch.Tensor\n expert_map: torch.Tensor | None = None\n\n\ndef _is_cuda_graph_capturing() -> bool:\n try:\n return bool(torch.cuda.is_current_stream_capturing())\n except Exception:\n return False\n\n\ndef _canonical_cuda_device(device: torch.device) -> torch.device:\n device = torch.device(device)\n if device.type == \"cuda\" and device.index is None:\n return torch.device(\"cuda\", torch.cuda.current_device())\n return device\n\n\ndef _w4a16_workspace_geometry(\n *,\n routed_rows: int,\n route_num_experts: int,\n num_topk: int,\n k: int,\n n: int,\n is_gated: bool,\n device: torch.device,\n) -> tuple[int, int, int, int, int]:\n route_slots = 1\n route_blocks = 1\n fc1_c_tmp_elements = 1\n fc2_c_tmp_elements = 1\n fc1_cols = (2 if is_gated else 1) * int(n)\n sms = get_num_sm(device)\n # Size the route buffers for the power-of-2 capacity so route packing keeps\n # a single triton specialization across token counts.\n routed_rows_capacity = route_pack_numel_capacity(\n int(routed_rows), topk=int(num_topk)\n )\n for block_size in _W4A16_ALLOWED_ROUTED_SIZES:\n slots = max_packed_route_slots(\n routed_rows_capacity,\n int(block_size),\n int(route_num_experts),\n )\n blocks = (slots + int(block_size) - 1) // int(block_size)\n route_slots = max(route_slots, slots)\n route_blocks = max(route_blocks, blocks)\n fc1_c_tmp_elements = max(\n fc1_c_tmp_elements,\n packed_gemm_scratch_elements(\n size_n=fc1_cols,\n route_slots=slots,\n moe_block_size=int(block_size),\n sms=sms,\n ),\n )\n fc2_c_tmp_elements = max(\n fc2_c_tmp_elements,\n packed_gemm_scratch_elements(\n size_n=int(k),\n route_slots=slots,\n moe_block_size=int(block_size),\n sms=sms,\n ),\n )\n return (\n route_slots,\n route_blocks,\n fc1_c_tmp_elements,\n fc2_c_tmp_elements,\n fc1_cols,\n )\n\n\ndef _make_w4a16_expert_map(\n *,\n state_E: int,\n weight_E: int,\n device: torch.device,\n) -> torch.Tensor | None:\n if int(state_E) == int(weight_E):\n return None\n if int(state_E) > int(weight_E):\n raise ValueError(\"num_local_experts cannot exceed num_experts\")\n expert_map = torch.empty((int(weight_E),), dtype=torch.int32, device=device)\n expert_map.fill_(-1)\n expert_map[: int(state_E)].copy_(\n torch.arange(int(state_E), dtype=torch.int32, device=device)\n )\n return expert_map\n\n\ndef _allocate_sm120_w4a16_workspace(\n *,\n state_E: int,\n weight_E: int,\n routed_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation: str = \"silu\",\n) -> Sm120W4A16MoEWorkspace:\n is_gated = validate_activation(activation)\n routed_rows = max(1, int(routed_rows))\n route_num_experts = int(weight_E) if int(state_E) != int(weight_E) else int(state_E)\n (\n route_slots,\n route_blocks,\n fc1_c_tmp_elements,\n fc2_c_tmp_elements,\n fc1_cols,\n ) = _w4a16_workspace_geometry(\n routed_rows=routed_rows,\n route_num_experts=route_num_experts,\n num_topk=num_topk,\n k=k,\n n=n,\n is_gated=is_gated,\n device=device,\n )\n return Sm120W4A16MoEWorkspace(\n state_E=int(state_E),\n weight_E=int(weight_E),\n max_rows=routed_rows,\n k=int(k),\n n=int(n),\n num_topk=int(num_topk),\n device=device,\n activation=activation,\n activation_precision=\"bf16\",\n quant_mode=\"w4a16\",\n routed_rows_capacity=routed_rows,\n route_num_experts=route_num_experts,\n intermediate_cache13=torch.empty(\n (routed_rows * max(fc1_cols, int(k)),),\n dtype=torch.bfloat16,\n device=device,\n ),\n intermediate_cache2=torch.empty(\n (routed_rows, int(n)),\n dtype=torch.bfloat16,\n device=device,\n ),\n fc1_c_tmp=torch.empty(\n (fc1_c_tmp_elements,),\n dtype=torch.float32,\n device=device,\n ),\n fc2_c_tmp=torch.empty(\n (fc2_c_tmp_elements,),\n dtype=torch.float32,\n device=device,\n ),\n packed_route_indices=torch.empty(\n (route_slots,),\n dtype=torch.int32,\n device=device,\n ),\n block_expert_ids=torch.empty(\n (route_blocks,),\n dtype=torch.int32,\n device=device,\n ),\n packed_route_count=torch.empty((1,), dtype=torch.int32, device=device),\n expert_offsets=torch.empty(\n (route_num_experts + 1,),\n dtype=torch.int32,\n device=device,\n ),\n expert_map=_make_w4a16_expert_map(\n state_E=state_E,\n weight_E=weight_E,\n device=device,\n ),\n )\n\n\n_W4A16_WEIGHT_CACHE: Dict[Tuple, W4A16PackedWeights] = {}\n\n\ndef _get_w4a16_packed_weights(\n *,\n w1_weight: torch.Tensor,\n w1_weight_sf: torch.Tensor,\n w1_alpha: torch.Tensor,\n w2_weight: torch.Tensor,\n w2_weight_sf: torch.Tensor,\n w2_alpha: torch.Tensor,\n activation: str,\n params_dtype: torch.dtype,\n source_format: str = \"modelopt\",\n) -> W4A16PackedWeights:\n key = (\n activation,\n params_dtype,\n source_format,\n tuple(w1_weight.shape),\n tuple(w1_weight_sf.shape),\n tuple(w1_alpha.shape),\n tuple(w2_weight.shape),\n tuple(w2_weight_sf.shape),\n tuple(w2_alpha.shape),\n w1_weight.data_ptr(),\n w1_weight_sf.data_ptr(),\n w1_alpha.data_ptr(),\n w2_weight.data_ptr(),\n w2_weight_sf.data_ptr(),\n w2_alpha.data_ptr(),\n )\n cached = _W4A16_WEIGHT_CACHE.get(key)\n if cached is not None:\n return cached\n if _is_cuda_graph_capturing():\n raise RuntimeError(\n \"W4A16 packed weights are not initialized for CUDA graph capture; \"\n \"run once before capture so the prepared weights are cached.\"\n )\n prepared = prepare_w4a16_packed_weights(\n w1_weight,\n w1_weight_sf,\n w1_alpha,\n w2_weight,\n w2_weight_sf,\n w2_alpha,\n activation=activation,\n params_dtype=params_dtype,\n source_format=source_format,\n )\n _W4A16_WEIGHT_CACHE[key] = prepared\n _register_cache_eviction(\n _W4A16_WEIGHT_CACHE,\n key,\n w1_weight,\n w1_weight_sf,\n w1_alpha,\n w2_weight,\n w2_weight_sf,\n w2_alpha,\n )\n return prepared\n\n\ndef _validate_w4a16_workspace(\n workspace: Sm120W4A16MoEWorkspace,\n *,\n state_E: int,\n weight_E: int,\n routed_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation: str,\n) -> None:\n validate_activation(activation)\n if workspace.state_E != int(state_E) or workspace.weight_E != int(weight_E):\n raise ValueError(\"pre-allocated W4A16 workspace expert geometry mismatch\")\n if workspace.k != int(k) or workspace.n != int(n):\n raise ValueError(\"pre-allocated W4A16 workspace hidden geometry mismatch\")\n if workspace.num_topk != int(num_topk):\n raise ValueError(\"pre-allocated W4A16 workspace top-k mismatch\")\n if getattr(workspace, \"activation\", None) != activation:\n raise ValueError(\"pre-allocated W4A16 workspace activation mismatch\")\n if _canonical_cuda_device(workspace.device) != _canonical_cuda_device(device):\n raise ValueError(\n f\"pre-allocated W4A16 workspace is on {workspace.device}, expected {device}\"\n )\n if workspace.routed_rows_capacity < max(1, int(routed_rows)):\n raise ValueError(\n \"pre-allocated W4A16 workspace is too small for the requested \"\n f\"routed rows ({workspace.routed_rows_capacity} < {routed_rows})\"\n )\n\n\ndef _launch_sm120_w4a16_moe(\n *,\n a: torch.Tensor,\n topk_ids: torch.Tensor,\n topk_weights: torch.Tensor,\n w1_weight: torch.Tensor,\n w1_weight_sf: torch.Tensor,\n w1_alpha: torch.Tensor,\n w2_weight: torch.Tensor,\n w2_weight_sf: torch.Tensor,\n w2_alpha: torch.Tensor,\n num_experts: int,\n top_k: int,\n num_local_experts: int,\n scatter_output: torch.Tensor,\n fast_math: bool = True,\n activation: str = \"silu\",\n source_format: str = \"modelopt\",\n _workspace=None,\n _prepared_weights=None,\n) -> torch.Tensor:\n prepared = (\n _prepared_weights\n if isinstance(_prepared_weights, W4A16PackedWeights)\n else _get_w4a16_packed_weights(\n w1_weight=w1_weight,\n w1_weight_sf=w1_weight_sf,\n w1_alpha=w1_alpha,\n w2_weight=w2_weight,\n w2_weight_sf=w2_weight_sf,\n w2_alpha=w2_alpha,\n activation=activation,\n params_dtype=a.dtype,\n source_format=source_format,\n )\n )\n if int(prepared.num_experts) != int(num_local_experts):\n raise ValueError(\"num_local_experts must match w1_weight.shape[0] for W4A16.\")\n num_tokens = int(topk_ids.size(0))\n routed_rows = num_tokens * int(top_k)\n k = int(a.size(1))\n n = int(prepared.intermediate_size)\n\n if _workspace is None:\n workspace = _get_cached_workspace(\n backend=\"w4a16\",\n state_E=num_local_experts,\n weight_E=num_experts,\n routed_rows=routed_rows,\n k=k,\n n=n,\n num_topk=top_k,\n device=a.device,\n quant_mode=\"w4a16\",\n activation=activation,\n )\n else:\n workspace = _workspace\n if not isinstance(workspace, Sm120W4A16MoEWorkspace):\n raise TypeError(\"expected a W4A16 workspace for quant_mode='w4a16'\")\n _validate_w4a16_workspace(\n workspace,\n state_E=num_local_experts,\n weight_E=num_experts,\n routed_rows=routed_rows,\n k=k,\n n=n,\n num_topk=top_k,\n device=a.device,\n activation=activation,\n )\n\n return run_w4a16_moe(\n a,\n prepared,\n topk_weights,\n topk_ids,\n activation=activation,\n intermediate_cache13=workspace.intermediate_cache13,\n intermediate_cache2=workspace.intermediate_cache2,\n output=scatter_output,\n fc1_c_tmp=workspace.fc1_c_tmp,\n fc2_c_tmp=workspace.fc2_c_tmp,\n packed_route_indices=workspace.packed_route_indices,\n block_expert_ids=workspace.block_expert_ids,\n packed_route_count=workspace.packed_route_count,\n expert_offsets=workspace.expert_offsets,\n expert_map=workspace.expert_map,\n fast_math=fast_math,\n )\n\n\n# ==========================================================================\n# Workspace cache (for functional API path)\n# ==========================================================================\n\n_Sm120Workspace = Union[\n Sm120StaticMoEWorkspace,\n Sm120DynamicMoEWorkspace,\n Sm120W4A16MoEWorkspace,\n]\n\n# Stores the workspace with the largest capacity seen per key and never\n# shrinks within a process. clear_sm120_moe_caches() releases everything.\n_WORKSPACE_CACHE: Dict[Tuple, _Sm120Workspace] = {}\n\n\ndef clear_sm120_moe_caches() -> None:\n \"\"\"Release every module-level SM12x MoE cache.\n\n References held by callers are unaffected.\n \"\"\"\n _WORKSPACE_CACHE.clear()\n _WEIGHT_CACHE.clear()\n _W4A16_WEIGHT_CACHE.clear()\n _PADDED_WEIGHT_CACHE.clear()\n _STATIC_KERNEL_CACHE.clear()\n _MICRO_KERNEL_CACHE.clear()\n _DIRECT_MICRO_LAUNCH_CACHE.clear()\n _DIRECT_MICRO_KERNEL_CACHE.clear()\n _DYNAMIC_KERNEL_CACHE.clear()\n\n\ndef allocate_sm120_moe_workspace(\n *,\n state_E: int,\n weight_E: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n max_rows: int | None = None,\n routed_rows: int | None = None,\n quant_mode: str | None = None,\n activation_precision: str | None = None,\n backend: str | None = None,\n activation: str = \"silu\",\n) -> _Sm120Workspace:\n \"\"\"Allocate the right SM120 MoE workspace from a quantization mode.\"\"\"\n mode = _normalize_quant_mode(quant_mode, activation_precision)\n capacity_rows = routed_rows if routed_rows is not None else max_rows\n if capacity_rows is None:\n raise ValueError(\"routed_rows or max_rows is required\")\n capacity_rows = max(1, int(capacity_rows))\n device = torch.device(device)\n\n if mode == \"w4a16\":\n if backend not in (None, \"w4a16\"):\n raise ValueError(\"quant_mode='w4a16' does not use static/dynamic backend\")\n return _allocate_sm120_w4a16_workspace(\n state_E=state_E,\n weight_E=weight_E,\n routed_rows=capacity_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation=activation,\n )\n\n activation_precision = \"fp4\"\n if backend is None:\n backend = select_sm120_moe_backend(\n num_tokens=max(\n 1, (capacity_rows + max(1, int(num_topk)) - 1) // max(1, int(num_topk))\n ),\n num_topk=int(num_topk),\n activation_precision=activation_precision,\n )\n if backend == \"dynamic\":\n return allocate_sm120_dynamic_workspace(\n state_E=state_E,\n weight_E=weight_E,\n routed_rows=capacity_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation_precision=activation_precision,\n activation=activation,\n )\n if backend == \"static\":\n return allocate_sm120_static_workspace(\n state_E=state_E,\n weight_E=weight_E,\n max_rows=capacity_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation_precision=activation_precision,\n )\n raise ValueError(f\"unsupported SM120 MoE backend {backend!r}\")\n\n\ndef _get_cached_workspace(\n *,\n backend: str,\n state_E: int,\n weight_E: int,\n routed_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation_precision: str = \"fp4\",\n quant_mode: str | None = None,\n activation: str = \"silu\",\n) -> _Sm120Workspace:\n \"\"\"Get or allocate a cached workspace for the given problem shape.\n\n Reuses the cached workspace if it has enough capacity for the requested\n routed_rows. For static workspaces, max_rows is the direct capacity.\n For dynamic workspaces, routed_rows_capacity is used because the dynamic\n geometry (physical tiles, task queue slots) depends on the original\n routed_rows, not just max_rows.\n \"\"\"\n quant_mode = _normalize_quant_mode(quant_mode, activation_precision)\n activation_precision = _activation_precision_from_quant_mode(quant_mode)\n # Key dynamic workspaces on the tile band of this call's routed_rows; a\n # larger cached workspace must not pin small calls to its 128 tile.\n tile_m = (\n _select_dynamic_tile_m(max(1, routed_rows), state_E, activation)\n if backend == \"dynamic\" and quant_mode != \"w4a16\"\n else None\n )\n cache_key = (\n state_E,\n weight_E,\n k,\n n,\n num_topk,\n str(device),\n backend,\n quant_mode,\n activation,\n tile_m,\n )\n cached = _WORKSPACE_CACHE.get(cache_key)\n\n if cached is not None:\n if isinstance(cached, Sm120DynamicMoEWorkspace):\n if cached.routed_rows_capacity >= max(1, routed_rows):\n assert tile_m is None or cached.tile_m == tile_m\n return cached\n elif isinstance(cached, Sm120W4A16MoEWorkspace):\n if cached.routed_rows_capacity >= max(1, routed_rows):\n return cached\n else:\n if cached.max_rows >= max(1, routed_rows):\n return cached\n\n if quant_mode == \"w4a16\" and _is_cuda_graph_capturing():\n raise RuntimeError(\n \"W4A16 workspace is not initialized for CUDA graph capture; \"\n \"provide a preallocated workspace from \"\n \"allocate_sm120_moe_workspace(..., quant_mode='w4a16') or warm the \"\n \"functional path before capture.\"\n )\n workspace = allocate_sm120_moe_workspace(\n state_E=state_E,\n weight_E=weight_E,\n routed_rows=routed_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n quant_mode=quant_mode,\n activation_precision=activation_precision,\n backend=backend,\n activation=activation,\n )\n\n _WORKSPACE_CACHE[cache_key] = workspace\n return workspace\n\n\n# ==========================================================================\n# Unified dispatch\n# ==========================================================================\n_PADDED_WEIGHT_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _pad_intermediate_to_tile(\n w1_weight,\n w1_weight_sf,\n w2_weight,\n w2_weight_sf,\n fc2_input_scale,\n n,\n tile,\n h,\n num_experts,\n is_gated,\n):\n \"\"\"Zero-pad NVFP4 weights + scale factors so the intermediate size is a\n multiple of ``tile`` (gate/up tile-split requirement); padded channels are\n zero, so the result is numerically identical.\n \"\"\"\n n_pad = ((n + tile - 1) // tile) * tile\n if n_pad == n:\n return w1_weight, w1_weight_sf, w2_weight, w2_weight_sf, fc2_input_scale, n\n E = int(num_experts)\n fc2_input_scale_src = fc2_input_scale\n key = (\n n,\n tile,\n h,\n E,\n bool(is_gated),\n w1_weight.data_ptr(),\n w1_weight_sf.data_ptr(),\n w2_weight.data_ptr(),\n w2_weight_sf.data_ptr(),\n fc2_input_scale_src.data_ptr() if fc2_input_scale_src is not None else 0,\n )\n cached = _PADDED_WEIGHT_CACHE.get(key)\n if cached is not None:\n return cached\n\n def mma_to_logical(sf, m, k):\n sw = convert_sf_from_mma_layout(sf, m=m, k=k, num_groups=E)\n m_pad = ((m + 127) // 128) * 128\n sw = sw.reshape(E, m_pad, -1)\n cb = (k + SF_VEC_SIZE - 1) // SF_VEC_SIZE\n return torch.stack(\n [unswizzle_block_scale(sw[e], rows=m, cols_blocks=cb) for e in range(E)], 0\n )\n\n def logical_to_mma(log, m, k):\n sw = torch.stack([swizzle_block_scale(log[e]) for e in range(E)], 0)\n sw2d = sw.reshape(E * sw.shape[1], sw.shape[2]).to(torch.float8_e4m3fn)\n return convert_sf_to_mma_layout(sw2d, m=m, k=k, num_groups=E)\n\n def pad_dim(t, dim, old, new):\n if new == old:\n return t\n shp = list(t.shape)\n shp[dim] = new - old\n return torch.cat([t, t.new_zeros(shp)], dim=dim)\n\n if is_gated:\n # w1 packs [up(0:n), gate(n:2n)] rows; pad each half so the split stays\n # tile-aligned, then re-concat.\n up, gate = w1_weight[:, :n, :], w1_weight[:, n : 2 * n, :]\n w1p = torch.cat([pad_dim(up, 1, n, n_pad), pad_dim(gate, 1, n, n_pad)], dim=1)\n log1 = mma_to_logical(w1_weight_sf, m=2 * n, k=h)\n up_sf, gate_sf = log1[:, :n, :], log1[:, n : 2 * n, :]\n log1p = torch.cat(\n [pad_dim(up_sf, 1, n, n_pad), pad_dim(gate_sf, 1, n, n_pad)], dim=1\n )\n w1_sf_p = logical_to_mma(log1p, m=2 * n_pad, k=h)\n else:\n w1p = pad_dim(w1_weight, 1, n, n_pad)\n log1 = mma_to_logical(w1_weight_sf, m=n, k=h)\n w1_sf_p = logical_to_mma(pad_dim(log1, 1, n, n_pad), m=n_pad, k=h)\n\n # w2 reduces over the intermediate dim: pad its packed columns + SF columns.\n w2p = pad_dim(w2_weight, 2, n // 2, n_pad // 2)\n log2 = mma_to_logical(w2_weight_sf, m=h, k=n)\n cb_n = (n + SF_VEC_SIZE - 1) // SF_VEC_SIZE\n cb_np = (n_pad + SF_VEC_SIZE - 1) // SF_VEC_SIZE\n w2_sf_p = logical_to_mma(pad_dim(log2, 2, cb_n, cb_np), m=h, k=n_pad)\n\n if fc2_input_scale_src is not None and fc2_input_scale_src.numel() == n:\n fc2_input_scale = pad_dim(fc2_input_scale_src, 0, n, n_pad)\n result = (w1p, w1_sf_p, w2p, w2_sf_p, fc2_input_scale, n_pad)\n _PADDED_WEIGHT_CACHE[key] = result\n _register_cache_eviction(\n _PADDED_WEIGHT_CACHE,\n key,\n w1_weight,\n w1_weight_sf,\n w2_weight,\n w2_weight_sf,\n fc2_input_scale_src,\n )\n return result\n\n\ndef launch_sm120_moe(\n *,\n a: torch.Tensor,\n topk_ids: torch.Tensor,\n topk_weights: torch.Tensor,\n w1_weight: torch.Tensor,\n w1_weight_sf: torch.Tensor,\n w1_alpha: torch.Tensor,\n fc2_input_scale: Optional[torch.Tensor] = None,\n input_global_scale: Optional[torch.Tensor] = None,\n w2_weight: torch.Tensor,\n w2_weight_sf: torch.Tensor,\n w2_alpha: torch.Tensor,\n num_experts: int,\n top_k: int,\n num_local_experts: int,\n scatter_output: torch.Tensor,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n quant_mode: str | None = None,\n source_format: str = \"modelopt\",\n _workspace=None,\n _weight_views=None,\n _prepared_weights=None,\n) -> torch.Tensor:\n \"\"\"Unified SM120 MoE dispatch — selects static or dynamic by token count.\n\n input_global_scale overrides w1_alpha as the FC1 input-quant scale and\n is folded into the multiplier internally. With _weight_views supplied,\n w1_alpha must already contain the fold.\n\n Optional _workspace and _weight_views can be pre-allocated and reused\n across calls to avoid per-call allocation overhead (wrapper path).\n When not provided (functional API path), a module-level workspace cache\n is used to avoid re-allocating on every call.\n \"\"\"\n quant_mode = _normalize_quant_mode(quant_mode, activation_precision)\n source_format = _normalize_source_format_for_quant_mode(source_format, quant_mode)\n activation_precision = _activation_precision_from_quant_mode(quant_mode)\n\n num_tokens = topk_ids.size(0)\n k = a.size(1) # hidden_size\n is_gated = is_gated_activation(activation)\n # w1_weight.size(1) is 2*n for gated or n for non-gated\n intermediate_size = w1_weight.size(1) // 2 if is_gated else w1_weight.size(1)\n n = intermediate_size\n\n # NVFP4 kernels need padded intermediate size.\n if quant_mode != \"w4a16\" and n % _LEVEL_TILE_N != 0 and _weight_views is None:\n (\n w1_weight,\n w1_weight_sf,\n w2_weight,\n w2_weight_sf,\n fc2_input_scale,\n n,\n ) = _pad_intermediate_to_tile(\n w1_weight,\n w1_weight_sf,\n w2_weight,\n w2_weight_sf,\n fc2_input_scale,\n n,\n _LEVEL_TILE_N,\n k,\n w1_weight.size(0),\n is_gated,\n )\n\n routed_rows = num_tokens * top_k\n\n if quant_mode == \"w4a16\":\n return _launch_sm120_w4a16_moe(\n a=a,\n topk_ids=topk_ids,\n topk_weights=topk_weights,\n w1_weight=w1_weight,\n w1_weight_sf=w1_weight_sf,\n w1_alpha=w1_alpha,\n w2_weight=w2_weight,\n w2_weight_sf=w2_weight_sf,\n w2_alpha=w2_alpha,\n num_experts=num_experts,\n top_k=top_k,\n num_local_experts=num_local_experts,\n scatter_output=scatter_output,\n fast_math=fast_math,\n activation=activation,\n source_format=source_format,\n _workspace=_workspace,\n _prepared_weights=_prepared_weights,\n )\n\n if fc2_input_scale is None:\n raise ValueError(\"fc2_input_scale is required when quant_mode='nvfp4'.\")\n down_input_scale = fc2_input_scale\n if input_global_scale is not None:\n input_gs = input_global_scale\n if _weight_views is None:\n # Alpha must carry input_gs back or the output magnitude is wrong.\n # The wrapper folds before building _weight_views; don't fold twice.\n w1_alpha = (\n w1_alpha.to(torch.float32) * input_global_scale.to(torch.float32)\n ).contiguous()\n else:\n input_gs = w1_alpha\n\n weights = (\n _weight_views\n if _weight_views is not None\n else _get_weight_views(\n w1_fp4=w1_weight,\n w1_blockscale=w1_weight_sf,\n w2_fp4=w2_weight,\n w2_blockscale=w2_weight_sf,\n w1_alphas=w1_alpha,\n w2_alphas=w2_alpha,\n n=n,\n k=k,\n activation_precision=activation_precision,\n )\n )\n\n # Resolve workspace and backend selection.\n # When a pre-allocated workspace is provided (CUDA graph wrapper path),\n # infer the backend from the workspace type so they stay in sync —\n # the caller already committed to a backend at allocation time.\n if _workspace is not None:\n workspace = _workspace\n workspace_activation_precision = getattr(\n workspace, \"activation_precision\", activation_precision\n )\n if workspace_activation_precision != activation_precision:\n raise ValueError(\n \"pre-allocated workspace activation_precision does not match \"\n f\"requested activation_precision={activation_precision!r}.\"\n )\n if isinstance(workspace, Sm120DynamicMoEWorkspace):\n if num_local_experts != num_experts:\n raise ValueError(\n \"pre-allocated dynamic SM120 MoE workspace requires \"\n \"num_local_experts == num_experts because dynamic expert \"\n \"buffers are indexed by global topk ids.\"\n )\n # A pre-allocated dynamic workspace keeps its stored tile_m even\n # for smaller calls; its geometry was sized for that tile.\n backend = \"dynamic\"\n else:\n backend = \"static\"\n else:\n backend = select_sm120_moe_backend(\n num_tokens=num_tokens,\n num_topk=top_k,\n activation_precision=activation_precision,\n )\n # The dynamic kernel indexes row_counts/expert_write_rows directly with\n # topk_ids but those buffers are sized with num_local_experts. Unless\n # num_local_experts == num_experts, fall back to the static backend which\n # has global-to-local expert remapping.\n if backend == \"dynamic\" and num_local_experts != num_experts:\n backend = \"static\"\n workspace = _get_cached_workspace(\n backend=backend,\n state_E=num_local_experts,\n weight_E=num_experts,\n routed_rows=routed_rows,\n k=k,\n n=n,\n num_topk=top_k,\n device=a.device,\n activation_precision=activation_precision,\n quant_mode=quant_mode,\n activation=activation,\n )\n\n if backend == \"dynamic\":\n return launch_sm120_dynamic_moe(\n workspace=workspace,\n weights=weights,\n a=a,\n topk_ids=topk_ids,\n topk_weights=topk_weights,\n input_gs=input_gs,\n down_input_scale=down_input_scale,\n scatter_output=scatter_output,\n num_experts=num_experts,\n num_tokens=num_tokens,\n k=k,\n n=n,\n top_k=top_k,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n activation_precision=activation_precision,\n )\n else:\n return launch_sm120_static_moe(\n workspace=workspace,\n weights=weights,\n a=a,\n topk_ids=topk_ids,\n topk_weights=topk_weights,\n input_gs=input_gs,\n down_input_scale=down_input_scale,\n scatter_output=scatter_output,\n num_experts=num_experts,\n num_tokens=num_tokens,\n k=k,\n n=n,\n top_k=top_k,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n activation_precision=activation_precision,\n )\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"Route gated activations through the optimized branch-paired dynamic kernel while preserving the generic fallback for non-gated activations. Support SiLU, GELU-tanh, and SwiGLU-OAI without an environment toggle.\n\n<!-- .github/pull_request_template.md -->\n## 📌 Description\n\nThis PR integrates an optimized branch-paired dynamic NVFP4 MoE kernel for gated activations on Blackwell SM12x into the regular FlashInfer CuTeDSL dispatch path.\n\n### What changed\n\n- Split the dynamic MoE implementation into:\n - `_moe_dynamic/generic.py`: the existing generic fallback.\n - `_moe_dynamic/gated.py`: the optimized gated implementation.\n- Dispatch `silu`, `gelu_tanh`, and `swigluoai_uninterleave` to the optimized gated kernel.\n- Preserve the generic dynamic path for non-gated activations such as `relu2`.\n- Pair the gate and up projections in the N64 FC1 dataflow to reduce staging and accumulator lifetimes.\n- Preserve the tuned explicit inline-PTX reciprocal path for SiLU.\n- Reuse the canonical activation formulas for GELU-tanh and SwiGLU-OAI while keeping them on the optimized gated dataflow.\n- Keep FC2 on the non-gated execution path.\n- Keep the public `MoEDynamicKernel` API unchanged.\n- Enable the optimized path through normal activation-based dispatch without an environment-variable switch.\n\n### Why\n\nA gated MoE FC1 computes two projections:\n\n```text\noutput = activation(gate_projection) * up_projection\n```\n\nThe previous generic dynamic implementation handled the two branches without exploiting their shared scheduling structure.\n\nThe new implementation pairs the gate and up branch work in the dynamic N64 kernel. This shortens intermediate lifetimes and reduces staging overhead while preserving the existing routing, NVFP4 quantization, FC2, and scatter behavior.\n\nThe top-level activation dispatch selects the gated implementation. The internal `is_gated` distinction is still required because the same kernel object participates in both stages:\n\n- FC1 is gated and uses the paired gate/up path.\n- FC2 is not gated and continues to use the regular projection path.\n\n### Correctness\n\nValidated on an SM120 Blackwell GPU against the BF16 reference with:\n\n```text\nM = 384\nH = 256\nI = 512\nE = 8\ntopk = 2\n```\n\n| Activation | Result | Finite output |\n| --- | ---: | ---: |\n| `silu` | 100% within the existing NVFP4 tolerance | Yes |\n| `gelu_tanh` | 100% within the existing NVFP4 tolerance | Yes |\n| `swigluoai_uninterleave` | 100% within the existing NVFP4 tolerance | Yes |\n\nNo NaN or Inf values were observed.\n\nStatic validation also passed:\n\n```text\nruff check\nruff format --check\npython -m py_compile\n```\n\n### Performance\n\nThe benchmark compares this PR against the native FlashInfer CuTeDSL implementation at the PR's current upstream base. No kernel overlay or environment-variable kernel override was used.\n\nCompared revisions:\n\n- Upstream base: `d7e390c17844f493db23320cb7952375f03bc6c4`\n- PR head: `594ca394c9328db582a689591392e13adcab092b`\n\nBenchmark environment:\n\n- GPU: NVIDIA RTX PRO 5000 72GB Blackwell, SM120\n- PyTorch 2.11.0+cu130 and CuTeDSL 4.6.1\n- CUDA Graph event timing\n- 192 MiB L2 flush before every timed replay\n- Warmup / iterations / repeats: 5 / 50 / 5\n- 22 token-count points from M=1 to M=8192\n- Qwen3.5-122B uses a 100-file routing trace replay\n- Qwen3.5-35B and Qwen3.5-397B use seeded random unique top-k routing\n- M<96 uses the existing static/micro backend; M>=96 uses the dynamic backend changed by this PR\n\nBoth revisions were measured on the same GPU with the same benchmark command and protocol. Each revision used an isolated JIT/cache directory. Lower latency is better.\n\n| Model configuration | M | Upstream native CuTeDSL (us) | This PR (us) | Latency reduction |\n| --- | ---: | ---: | ---: | ---: |\n| Qwen3.5-35B TP1 | 4096 | 1012.692 | 586.782 | 42.06% |\n| Qwen3.5-35B TP1 | 8192 | 1749.317 | 927.645 | 46.97% |\n| Qwen3.5-122B TP2 | 4096 | 1461.020 | 938.726 | 35.75% |\n| Qwen3.5-122B TP2 | 8192 | 2517.957 | 1441.407 | 42.75% |\n| Qwen3.5-122B TP4 | 4096 | 932.632 | 639.082 | 31.48% |\n| Qwen3.5-122B TP4 | 8192 | 1618.032 | 1027.254 | 36.51% |\n| Qwen3.5-397B TP4 | 4096 | 1829.354 | 1626.127 | 11.11% |\n| Qwen3.5-397B TP4 | 8192 | 3064.157 | 2453.747 | 19.92% |\n| Qwen3.5-397B TP8 | 4096 | 1285.750 | 1112.290 | 13.49% |\n| Qwen3.5-397B TP8 | 8192 | 2330.589 | 1856.785 | 20.33% |\n\nGeometric-mean latency reduction across the sweep:\n\n| Model configuration | All 22 M points | Dynamic path, M>=96 |\n| --- | ---: | ---: |\n| Qwen3.5-35B TP1 | 20.24% | 31.74% |\n| Qwen3.5-122B TP2 | 17.12% | 27.17% |\n| Qwen3.5-122B TP4 | 12.71% | 20.43% |\n| Qwen3.5-397B TP4 | 3.88% | 6.49% |\n| Qwen3.5-397B TP8 | 4.83% | 8.15% |\n\nThe static/micro M<96 subset changed by only -0.19% to +0.22% across the five configurations, consistent with measurement noise on the unchanged path. The larger full-sweep gains therefore come from the dynamic path targeted by this PR.\n## 🔍 Related Issues\n\nN/A\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used my preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see the [pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\nPlease pay particular attention to:\n\n- The activation-based dispatch boundary between the generic and gated implementations.\n- The distinction between top-level gated-kernel selection and internal FC1/FC2 `is_gated` behavior.\n- SiLU's explicit inline-PTX reciprocal emission path.\n- Correctness of the GELU-tanh and SwiGLU-OAI activation formulas inside the optimized gated dataflow.\n\nThe non-gated fallback and public `MoEDynamicKernel` interface are intentionally unchanged.\n\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n* **New Features**\n * Added dynamic fused Mixture-of-Experts support for Blackwell SM120/SM121 GPUs.\n * Added NVFP4 processing with routed-token packing, quantization, expert computation, and weighted output scattering.\n * Added support for gated and non-gated activations, including SiLU, SwiGLU, ReLU2, GELU-tanh, and SwiGLU-OAI variants.\n * Added configurable fast math, scaling, cross-expert input sharing, and SwiGLU parameters.\n\n* **Refactor**\n * Unified dynamic MoE kernel selection across activation types.\n * Added automatic fallback for unsupported shapes and configurations.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"e2e\", \"hardware\": \"NVIDIA RTX PRO 5000 72GB Blackwell, SM120\", \"model\": \"Qwen3.5-35B TP1\", \"shape\": null, \"batch_size\": 4096, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 1012.692, \"optimized\": 586.782, \"stated_speedup\": null, \"speedup\": 1.7258}, {\"scope\": \"e2e\", \"hardware\": \"NVIDIA RTX PRO 5000 72GB Blackwell, SM120\", \"model\": \"Qwen3.5-35B TP1\", \"shape\": null, \"batch_size\": 8192, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 1749.317, \"optimized\": 927.645, \"stated_speedup\": null, \"speedup\": 1.8858}, {\"scope\": \"e2e\", \"hardware\": \"NVIDIA RTX PRO 5000 72GB Blackwell, SM120\", \"model\": \"Qwen3.5-122B TP2\", \"shape\": null, \"batch_size\": 4096, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 1461.02, \"optimized\": 938.726, \"stated_speedup\": null, \"speedup\": 1.5564}, {\"scope\": \"e2e\", \"hardware\": \"NVIDIA RTX PRO 5000 72GB Blackwell, SM120\", \"model\": \"Qwen3.5-122B TP2\", \"shape\": null, \"batch_size\": 8192, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 2517.957, \"optimized\": 1441.407, \"stated_speedup\": null, \"speedup\": 1.7469}, {\"scope\": \"e2e\", \"hardware\": \"NVIDIA RTX PRO 5000 72GB Blackwell, SM120\", \"model\": \"Qwen3.5-122B TP4\", \"shape\": null, \"batch_size\": 4096, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 932.632, \"optimized\": 639.082, \"stated_speedup\": null, \"speedup\": 1.4593}, {\"scope\": \"e2e\", \"hardware\": \"NVIDIA RTX PRO 5000 72GB Blackwell, SM120\", \"model\": \"Qwen3.5-122B TP4\", \"shape\": null, \"batch_size\": 8192, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 1618.032, \"optimized\": 1027.254, \"stated_speedup\": null, \"speedup\": 1.5751}, {\"scope\": \"e2e\", \"hardware\": \"NVIDIA RTX PRO 5000 72GB Blackwell, SM120\", \"model\": \"Qwen3.5-397B TP4\", \"shape\": null, \"batch_size\": 4096, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 1829.354, \"optimized\": 1626.127, \"stated_speedup\": null, \"speedup\": 1.125}, {\"scope\": \"e2e\", \"hardware\": \"NVIDIA RTX PRO 5000 72GB Blackwell, SM120\", \"model\": \"Qwen3.5-397B TP4\", \"shape\": null, \"batch_size\": 8192, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 3064.157, \"optimized\": 2453.747, \"stated_speedup\": null, \"speedup\": 1.2488}, {\"scope\": \"e2e\", \"hardware\": \"NVIDIA RTX PRO 5000 72GB Blackwell, SM120\", \"model\": \"Qwen3.5-397B TP8\", \"shape\": null, \"batch_size\": 4096, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 1285.75, \"optimized\": 1112.29, \"stated_speedup\": null, \"speedup\": 1.1559}, {\"scope\": \"e2e\", \"hardware\": \"NVIDIA RTX PRO 5000 72GB Blackwell, SM120\", \"model\": \"Qwen3.5-397B TP8\", \"shape\": null, \"batch_size\": 8192, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 2330.589, \"optimized\": 1856.785, \"stated_speedup\": null, \"speedup\": 1.2552}]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"number","value":1.5078,"string":"1.5078"}}},{"rowIdx":1094,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"d9c97ac13247a30f5bbc29d39f88d6a415bb7dca"},"date":{"kind":"string","value":"2026-08-05T10:19:40-07:00"},"pr_number":{"kind":"number","value":4295,"string":"4,295"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/4295"},"title":{"kind":"string","value":"perf(topk): skip output index sort for tie-break selection (#4295)"},"message":{"kind":"string","value":"perf(topk): skip output index sort for tie-break selection (#4295)\n\n<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\n@humansand\n\nFollow-up to #3095.\n\n`tie_break` determines which equal-valued elements are selected at the\ntop-k boundary. Today, requesting a tie-break also promotes the public\n`deterministic` flag, which runs the index-ordering finalizer even\nthough the default API output is unsorted.\n\nThis PR separates deterministic selection from deterministic output\nordering:\n\n- tie-break modes still use deterministic filtered selection so\n`SMALL`/`LARGE` choose the intended boundary indices;\n- the shared `FinalizeTopKIndicesKernel` always finalizes/remaps\nindices, with `SORT_LOCAL_INDICES` as the compile-time switch for its\noptional local-index radix sort;\n- explicit `deterministic=True` retains the existing CUB index sort and\nrepeatable output order;\n- tie-break with `deterministic=False` skips the finalizer entirely for\nplain Top-K, while page-table/ragged transforms run only the required\nremapping work;\n- `can_use_clusters_topk` now receives `tie_break` and rejects tie-break\nmodes at the same early-exit boundary as `dsa_graph_safe`;\n- API documentation, exact-set/remapping tests, and the Top-K benchmark\ndriver reflect that tie-breaking controls selection, not output order.\n\n`sorted=True` remains unchanged and still requests descending value\norder.\n\n#### `sorted` and `deterministic` use different sort keys\n\nThese options are independent and should not be conflated:\n\n| Option | Contract | Sort key/order |\n|---|---|---|\n| `sorted=True` | Return the selected top-k elements in score order,\nmatching `torch.topk(..., sorted=True)` | value descending, carrying the\ncorresponding index |\n| `deterministic=True` | Make selection and output ordering repeatable\nfor a fixed input and system | on the filtered path, local/original\nindex ascending, carrying the corresponding value |\n\nThe deterministic filtered-path index sort is a canonicalization step;\nit does **not** imply descending score order. If both options are\nenabled, FlashInfer first establishes deterministic index order and then\napplies a stable descending value sort. Equal values therefore retain\nthe deterministic prior order. For page-table and ragged transforms,\nlocal indices are canonicalized before remapping, so the returned mapped\nIDs are not necessarily numerically sorted.\n\n`tie_break` is separate from both: it controls which equal-valued\nelements are selected at the top-k boundary, not the final output order.\n\n### Performance\n\nBoth sides used the same final benchmark driver and ran on the same\nphysical GPU (`CUDA_VISIBLE_DEVICES=2`) in the `flashinfer-pr4048-cu132`\ndevbox from the `hell` queue. Speedup is `BEFORE / AFTER`.\n\n| Environment | Value |\n|---|---|\n| GPU | NVIDIA B200 (`sm100`) |\n| CUDA toolkit | 13.2.1 |\n| PyTorch | 2.13.0+cu132 |\n| Driver | 580.126.09 |\n| CUPTI Python/native | 13.2.0 / 13.2.75 |\n| FlashInfer source version | 0.6.17 |\n| BEFORE | `upstream/main` at `668a1ba1ca86432c79f6adad37ecfce8d06ec083`\n|\n| AFTER | `89c649679af75792b2cad1020c91b41bf2262adc` |\n| Timing | CUPTI activity timing, no CUDA graph replay, cold L2, 10 dry\nruns, 100 measured iterations, median |\n\nThe shared timer supports CUPTI with and without CUDA graphs. A control\nsweep with CUPTI + CUDA graphs + cold-L2 reproduced the same\nillegal-memory-access failure on both upstream `main` and this branch at\nthe first 128K page-table row, so it is not specific to this PR's kernel\nchanges. The final benchmark follows existing FlashInfer CUPTI\nmicrobenchmarks by using `enable_cupti=True` with\n`use_cuda_graph=False`; no benchmark-specific environment, global, or\nCLI escape hatch remains.\n\nCommands:\n\n```bash\nexport CUDA_VISIBLE_DEVICES=2\n\npython benchmarks/bench_topk.py \\\n --op dsa_topk \\\n --dtype bf16 \\\n --dsa-input-pattern dsa_relu \\\n --dsa-case all \\\n --dsa-topk 2048 \\\n --tie-break\n\npython benchmarks/bench_topk.py \\\n --op varlen \\\n --dtype bf16 \\\n --length-dist causal \\\n --varlen-k 2048 \\\n --varlen-q-len 128 \\\n --tie-break\n```\n\nSummary (geometric mean across cases):\n\n| Suite | Tie-break | Geomean speedup | Case range |\n|---|---:|---:|---:|\n| DSA Top-K | small | **1.141x** | 1.123x–1.182x |\n| DSA Top-K | large | **1.135x** | 1.071x–1.170x |\n| Varlen page-table | small | **1.080x** | 1.034x–1.145x |\n| Varlen page-table | large | **1.078x** | 1.035x–1.139x |\n| Varlen ragged | small | **1.121x** | 1.061x–1.186x |\n| Varlen ragged | large | **1.119x** | 1.061x–1.195x |\n\nDSA Top-K results (latency in µs):\n\n| Case | Small BEFORE | Small AFTER | Speedup | Large BEFORE | Large\nAFTER | Speedup |\n|---|---:|---:|---:|---:|---:|---:|\n| `decode_b1_q1_l128k` | 83.17 | 74.08 | **1.123x** | 84.54 | 72.24 |\n**1.170x** |\n| `decode_b8_q1_l64k` | 80.69 | 68.29 | **1.182x** | 79.04 | 67.86 |\n**1.165x** |\n| `decode_b32_q1_l128k` | 90.56 | 80.51 | **1.125x** | 85.92 | 80.19 |\n**1.071x** |\n| `prefill_b1_q128_l128k` | 91.41 | 80.51 | **1.135x** | 91.33 | 80.43 |\n**1.136x** |\n\nVariable-length transform results (latency in µs):\n\n| Transform | Rows | Max length | Small BEFORE | Small AFTER | Speedup |\nLarge BEFORE | Large AFTER | Speedup |\n|---|---:|---:|---:|---:|---:|---:|---:|---:|\n| page-table | 512 | 16,384 | 49.06 | 42.85 | **1.145x** | 49.09 | 43.10\n| **1.139x** |\n| ragged | 512 | 16,384 | 47.87 | 40.35 | **1.186x** | 48.10 | 40.26 |\n**1.195x** |\n| page-table | 512 | 65,536 | 86.38 | 79.07 | **1.092x** | 87.66 | 80.67\n| **1.087x** |\n| ragged | 512 | 65,536 | 84.80 | 75.50 | **1.123x** | 85.39 | 76.99 |\n**1.109x** |\n| page-table | 512 | 131,072 | 99.63 | 92.54 | **1.077x** | 99.92 |\n92.80 | **1.077x** |\n| ragged | 512 | 131,072 | 98.61 | 89.41 | **1.103x** | 98.75 | 89.68 |\n**1.101x** |\n| page-table | 2,048 | 16,384 | 172.29 | 157.33 | **1.095x** | 173.63 |\n158.94 | **1.092x** |\n| ragged | 2,048 | 16,384 | 170.30 | 144.35 | **1.180x** | 171.66 |\n145.87 | **1.177x** |\n| page-table | 2,048 | 65,536 | 442.69 | 424.46 | **1.043x** | 444.54 |\n426.35 | **1.043x** |\n| ragged | 2,048 | 65,536 | 437.07 | 405.06 | **1.079x** | 438.82 |\n406.80 | **1.079x** |\n| page-table | 2,048 | 131,072 | 565.89 | 547.06 | **1.034x** | 568.35 |\n548.93 | **1.035x** |\n| ragged | 2,048 | 131,072 | 558.54 | 526.56 | **1.061x** | 561.33 |\n529.02 | **1.061x** |\n\n<details>\n<summary>Raw BEFORE output: DSA Top-K</summary>\n\n```text\n====================================================================================================\ndsa_topk: DeepSeek DSA-like indexer top-k workload (dtype=BF16, deterministic=False, dsa_pattern=dsa_relu, k=2048, tie_break=True)\nNOTE: tie-break columns use deterministic=False; slowdowns use the non-deterministic baseline\n====================================================================================================\n case rows seq_len k | FlashInfer FlashInfer(det) DetSlowdown FlashInfer(tie-small) TieSmallSlowdown FlashInfer(tie-large) TieLargeSlowdown torch.topk Speedup\n------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------\n decode_b1_q1_l128k 1 131072 2048 | 40.90us n/a n/a 83.17us 2.03x 84.54us 2.07x 75.44us 1.84x\n decode_b8_q1_l64k 8 65536 2048 | 40.75us n/a n/a 80.69us 1.98x 79.04us 1.94x 82.86us 2.03x\n decode_b32_q1_l128k 32 131072 2048 | 45.66us n/a n/a 90.56us 1.98x 85.92us 1.88x 112.77us 2.47x\n prefill_b1_q128_l128k 128 131072 2048 | 82.61us n/a n/a 91.41us 1.11x 91.33us 1.11x 197.28us 2.39x\n```\n\n</details>\n\n<details>\n<summary>"},"path":{"kind":"string","value":"csrc/topk.cu"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * Copyright (c) 2024 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include <flashinfer/sampling.cuh>\n#include <flashinfer/topk.cuh>\n\n#include \"tvm_ffi_utils.h\"\n\nusing namespace flashinfer;\n\nusing tvm::ffi::Optional;\n\ninline sampling::TopKTieBreak ParseTopKTieBreak(int64_t tie_break) {\n switch (tie_break) {\n case 0:\n return sampling::TopKTieBreak::None;\n case 1:\n return sampling::TopKTieBreak::Small;\n case 2:\n return sampling::TopKTieBreak::Large;\n default:\n TVM_FFI_ICHECK(false)\n << \"Invalid tie_break mode \" << tie_break\n << \", expected 0 (none), 1 (prefer small indices), or 2 (prefer large indices)\";\n return sampling::TopKTieBreak::None;\n }\n}\n\nvoid radix_topk(TensorView input, TensorView output_indices, TensorView output_values,\n Optional<TensorView> maybe_row_states_buffer, int64_t top_k, bool sorted_output,\n bool deterministic, int64_t tie_break, bool dsa_graph_safe) {\n CHECK_INPUT(input);\n CHECK_INPUT(output_indices);\n CHECK_INPUT(output_values);\n CHECK_DIM(2, input); // input: (batch_size, d)\n CHECK_DIM(2, output_indices); // output_indices: (batch_size, top_k)\n CHECK_DIM(2, output_values); // output_values: (batch_size, top_k)\n\n unsigned int batch_size = input.size(0);\n unsigned int d = input.size(1);\n\n cudaSetDevice(input.device().device_id);\n auto stream = get_stream(input.device());\n\n cudaError_t status;\n auto dtype = input.dtype();\n sampling::TopKTieBreak tie_break_mode = ParseTopKTieBreak(tie_break);\n if (tie_break_mode != sampling::TopKTieBreak::None) {\n deterministic = true;\n }\n // Get row_states_buffer if provided (for multi-CTA path)\n sampling::RadixRowState* row_states_ptr = nullptr;\n if (maybe_row_states_buffer.has_value()) {\n row_states_ptr =\n static_cast<sampling::RadixRowState*>(maybe_row_states_buffer.value().data_ptr());\n }\n\n // Use unified dispatch with heuristics to choose between FilteredTopK and RadixTopK\n DISPATCH_DLPACK_DTYPE_TO_CTYPE_FP32_FP16(dtype, c_type, [&] {\n status = sampling::TopKDispatch<c_type, int32_t>(\n static_cast<c_type*>(input.data_ptr()), static_cast<int32_t*>(output_indices.data_ptr()),\n static_cast<c_type*>(output_values.data_ptr()), batch_size, static_cast<uint32_t>(top_k), d,\n row_states_ptr, sorted_output, deterministic, tie_break_mode, stream, dsa_graph_safe);\n return true;\n });\n\n TVM_FFI_ICHECK(status == cudaSuccess)\n << \"TopK failed with error code \" << cudaGetErrorString(status);\n}\n\nvoid radix_topk_page_table_transform(TensorView input, TensorView output_page_table,\n TensorView src_page_table,\n Optional<TensorView> maybe_row_to_batch, TensorView lengths,\n Optional<TensorView> maybe_row_states_buffer, int64_t top_k,\n bool deterministic, int64_t tie_break, bool dsa_graph_safe,\n Optional<TensorView> maybe_row_starts,\n Optional<TensorView> maybe_page_table_row_starts) {\n CHECK_INPUT(input);\n CHECK_INPUT(output_page_table);\n CHECK_INPUT(src_page_table);\n CHECK_INPUT(lengths);\n CHECK_DIM(2, input); // input: (num_rows, max_len)\n CHECK_DIM(2, output_page_table); // output_page_table: (num_rows, top_k)\n CHECK_DIM(2, src_page_table); // src_page_table: (batch_size, max_len)\n CHECK_DIM(1, lengths); // lengths: (num_rows,)\n if (maybe_row_starts.has_value()) {\n CHECK_INPUT(maybe_row_starts.value());\n CHECK_DIM(1, maybe_row_starts.value());\n }\n if (maybe_page_table_row_starts.has_value()) {\n CHECK_INPUT(maybe_page_table_row_starts.value());\n CHECK_DIM(1, maybe_page_table_row_starts.value());\n }\n\n unsigned int num_rows = input.size(0);\n unsigned int max_len = input.size(1);\n int64_t src_stride = src_page_table.stride(0);\n\n cudaSetDevice(input.device().device_id);\n auto stream = get_stream(input.device());\n\n cudaError_t status;\n auto dtype = input.dtype();\n sampling::TopKTieBreak tie_break_mode = ParseTopKTieBreak(tie_break);\n if (tie_break_mode != sampling::TopKTieBreak::None) {\n deterministic = true;\n }\n\n sampling::RadixRowState* row_states_ptr = nullptr;\n if (maybe_row_states_buffer.has_value()) {\n row_states_ptr =\n static_cast<sampling::RadixRowState*>(maybe_row_states_buffer.value().data_ptr());\n }\n\n int32_t* row_to_batch_ptr = nullptr;\n if (maybe_row_to_batch.has_value()) {\n row_to_batch_ptr = static_cast<int32_t*>(maybe_row_to_batch.value().data_ptr());\n }\n int32_t* row_starts_ptr = nullptr;\n if (maybe_row_starts.has_value()) {\n TVM_FFI_ICHECK(static_cast<unsigned int>(maybe_row_starts.value().size(0)) == num_rows)\n << \"row_starts must have shape (num_rows,)\";\n row_starts_ptr = static_cast<int32_t*>(maybe_row_starts.value().data_ptr());\n }\n int32_t* page_table_row_starts_ptr = nullptr;\n if (maybe_page_table_row_starts.has_value()) {\n TVM_FFI_ICHECK(static_cast<unsigned int>(maybe_page_table_row_starts.value().size(0)) ==\n num_rows)\n << \"page_table_row_starts must have shape (num_rows,)\";\n page_table_row_starts_ptr =\n static_cast<int32_t*>(maybe_page_table_row_starts.value().data_ptr());\n }\n\n // Use unified dispatch with heuristics to choose between FilteredTopK and RadixTopK\n DISPATCH_DLPACK_DTYPE_TO_CTYPE_FP32_FP16(dtype, c_type, [&] {\n status = sampling::TopKPageTableTransformDispatch<c_type, int32_t>(\n static_cast<c_type*>(input.data_ptr()), static_cast<int32_t*>(output_page_table.data_ptr()),\n static_cast<const int32_t*>(src_page_table.data_ptr()), src_stride,\n static_cast<int32_t*>(lengths.data_ptr()), row_starts_ptr, row_to_batch_ptr, num_rows,\n static_cast<uint32_t>(top_k), max_len, row_states_ptr, deterministic, tie_break_mode,\n stream, dsa_graph_safe, page_table_row_starts_ptr);\n return true;\n });\n\n TVM_FFI_ICHECK(status == cudaSuccess)\n << \"TopKPageTableTransform failed with error code \" << cudaGetErrorString(status);\n}\n\nvoid radix_topk_ragged_transform(TensorView input, TensorView output_indices, TensorView offsets,\n TensorView lengths, Optional<TensorView> maybe_row_states_buffer,\n int64_t top_k, bool deterministic, int64_t tie_break,\n bool dsa_graph_safe, Optional<TensorView> maybe_row_starts) {\n CHECK_INPUT(input);\n CHECK_INPUT(output_indices);\n CHECK_INPUT(offsets);\n CHECK_INPUT(lengths);\n CHECK_DIM(2, input); // input: (num_rows, max_len)\n CHECK_DIM(2, output_indices); // output_indices: (num_rows, top_k)\n CHECK_DIM(1, offsets); // offsets: (num_rows,)\n CHECK_DIM(1, lengths); // lengths: (num_rows,)\n if (maybe_row_starts.has_value()) {\n CHECK_INPUT(maybe_row_starts.value());\n CHECK_DIM(1, maybe_row_starts.value());\n }\n\n unsigned int num_rows = input.size(0);\n unsigned int max_len = input.size(1);\n\n cudaSetDevice(input.device().device_id);\n auto stream = get_stream(input.device());\n\n cudaError_t status;\n auto dtype = input.dtype();\n sampling::TopKTieBreak tie_break_mode = ParseTopKTieBreak(tie_break);\n if (tie_break_mode != sampling::TopKTieBreak::None) {\n deterministic = true;\n }\n\n sampling::RadixRowState* row_states_ptr = nullptr;\n if (maybe_row_states_buffer.has_value()) {\n row_states_ptr =\n static_cast<sampling::RadixRowState*>(maybe_row_states_buffer.value().data_ptr());\n }\n int32_t* row_starts_ptr = nullptr;\n if (maybe_row_starts.has_value()) {\n TVM_FFI_ICHECK(static_cast<unsigned int>(maybe_row_starts.value().size(0)) == num_rows)\n << \"row_starts must have shape (num_rows,)\";\n row_starts_ptr = static_cast<int32_t*>(maybe_row_starts.value().data_ptr());\n }\n\n // Use unified dispatch with heuristics to choose between FilteredTopK and RadixTopK\n DISPATCH_DLPACK_DTYPE_TO_CTYPE_FP32_FP16(dtype, c_type, [&] {\n status = sampling::TopKRaggedTransformDispatch<c_type, int32_t>(\n static_cast<c_type*>(input.data_ptr()), static_cast<int32_t*>(output_indices.data_ptr()),\n static_cast<const int32_t*>(offsets.data_ptr()), static_cast<int32_t*>(lengths.data_ptr()),\n row_starts_ptr, num_rows, static_cast<uint32_t>(top_k), max_len, row_states_ptr,\n deterministic, tie_break_mode, stream, dsa_graph_safe);\n return true;\n });\n\n TVM_FFI_ICHECK(status == cudaSuccess)\n << \"TopKRaggedTransform failed with error code \" << cudaGetErrorString(status);\n}\n\nbool can_implement_filtered_topk() { return sampling::CanImplementFilteredTopK(); }\n"},"after_code":{"kind":"string","value":"/*\n * Copyright (c) 2024 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include <flashinfer/sampling.cuh>\n#include <flashinfer/topk.cuh>\n\n#include \"tvm_ffi_utils.h\"\n\nusing namespace flashinfer;\n\nusing tvm::ffi::Optional;\n\ninline sampling::TopKTieBreak ParseTopKTieBreak(int64_t tie_break) {\n switch (tie_break) {\n case 0:\n return sampling::TopKTieBreak::None;\n case 1:\n return sampling::TopKTieBreak::Small;\n case 2:\n return sampling::TopKTieBreak::Large;\n default:\n TVM_FFI_ICHECK(false)\n << \"Invalid tie_break mode \" << tie_break\n << \", expected 0 (none), 1 (prefer small indices), or 2 (prefer large indices)\";\n return sampling::TopKTieBreak::None;\n }\n}\n\nvoid radix_topk(TensorView input, TensorView output_indices, TensorView output_values,\n Optional<TensorView> maybe_row_states_buffer, int64_t top_k, bool sorted_output,\n bool deterministic, int64_t tie_break, bool dsa_graph_safe) {\n CHECK_INPUT(input);\n CHECK_INPUT(output_indices);\n CHECK_INPUT(output_values);\n CHECK_DIM(2, input); // input: (batch_size, d)\n CHECK_DIM(2, output_indices); // output_indices: (batch_size, top_k)\n CHECK_DIM(2, output_values); // output_values: (batch_size, top_k)\n\n unsigned int batch_size = input.size(0);\n unsigned int d = input.size(1);\n\n cudaSetDevice(input.device().device_id);\n auto stream = get_stream(input.device());\n\n cudaError_t status;\n auto dtype = input.dtype();\n sampling::TopKTieBreak tie_break_mode = ParseTopKTieBreak(tie_break);\n // Get row_states_buffer if provided (for multi-CTA path)\n sampling::RadixRowState* row_states_ptr = nullptr;\n if (maybe_row_states_buffer.has_value()) {\n row_states_ptr =\n static_cast<sampling::RadixRowState*>(maybe_row_states_buffer.value().data_ptr());\n }\n\n // Use unified dispatch with heuristics to choose between FilteredTopK and RadixTopK\n DISPATCH_DLPACK_DTYPE_TO_CTYPE_FP32_FP16(dtype, c_type, [&] {\n status = sampling::TopKDispatch<c_type, int32_t>(\n static_cast<c_type*>(input.data_ptr()), static_cast<int32_t*>(output_indices.data_ptr()),\n static_cast<c_type*>(output_values.data_ptr()), batch_size, static_cast<uint32_t>(top_k), d,\n row_states_ptr, sorted_output, deterministic, tie_break_mode, stream, dsa_graph_safe);\n return true;\n });\n\n TVM_FFI_ICHECK(status == cudaSuccess)\n << \"TopK failed with error code \" << cudaGetErrorString(status);\n}\n\nvoid radix_topk_page_table_transform(TensorView input, TensorView output_page_table,\n TensorView src_page_table,\n Optional<TensorView> maybe_row_to_batch, TensorView lengths,\n Optional<TensorView> maybe_row_states_buffer, int64_t top_k,\n bool deterministic, int64_t tie_break, bool dsa_graph_safe,\n Optional<TensorView> maybe_row_starts,\n Optional<TensorView> maybe_page_table_row_starts) {\n CHECK_INPUT(input);\n CHECK_INPUT(output_page_table);\n CHECK_INPUT(src_page_table);\n CHECK_INPUT(lengths);\n CHECK_DIM(2, input); // input: (num_rows, max_len)\n CHECK_DIM(2, output_page_table); // output_page_table: (num_rows, top_k)\n CHECK_DIM(2, src_page_table); // src_page_table: (batch_size, max_len)\n CHECK_DIM(1, lengths); // lengths: (num_rows,)\n if (maybe_row_starts.has_value()) {\n CHECK_INPUT(maybe_row_starts.value());\n CHECK_DIM(1, maybe_row_starts.value());\n }\n if (maybe_page_table_row_starts.has_value()) {\n CHECK_INPUT(maybe_page_table_row_starts.value());\n CHECK_DIM(1, maybe_page_table_row_starts.value());\n }\n\n unsigned int num_rows = input.size(0);\n unsigned int max_len = input.size(1);\n int64_t src_stride = src_page_table.stride(0);\n\n cudaSetDevice(input.device().device_id);\n auto stream = get_stream(input.device());\n\n cudaError_t status;\n auto dtype = input.dtype();\n sampling::TopKTieBreak tie_break_mode = ParseTopKTieBreak(tie_break);\n\n sampling::RadixRowState* row_states_ptr = nullptr;\n if (maybe_row_states_buffer.has_value()) {\n row_states_ptr =\n static_cast<sampling::RadixRowState*>(maybe_row_states_buffer.value().data_ptr());\n }\n\n int32_t* row_to_batch_ptr = nullptr;\n if (maybe_row_to_batch.has_value()) {\n row_to_batch_ptr = static_cast<int32_t*>(maybe_row_to_batch.value().data_ptr());\n }\n int32_t* row_starts_ptr = nullptr;\n if (maybe_row_starts.has_value()) {\n TVM_FFI_ICHECK(static_cast<unsigned int>(maybe_row_starts.value().size(0)) == num_rows)\n << \"row_starts must have shape (num_rows,)\";\n row_starts_ptr = static_cast<int32_t*>(maybe_row_starts.value().data_ptr());\n }\n int32_t* page_table_row_starts_ptr = nullptr;\n if (maybe_page_table_row_starts.has_value()) {\n TVM_FFI_ICHECK(static_cast<unsigned int>(maybe_page_table_row_starts.value().size(0)) ==\n num_rows)\n << \"page_table_row_starts must have shape (num_rows,)\";\n page_table_row_starts_ptr =\n static_cast<int32_t*>(maybe_page_table_row_starts.value().data_ptr());\n }\n\n // Use unified dispatch with heuristics to choose between FilteredTopK and RadixTopK\n DISPATCH_DLPACK_DTYPE_TO_CTYPE_FP32_FP16(dtype, c_type, [&] {\n status = sampling::TopKPageTableTransformDispatch<c_type, int32_t>(\n static_cast<c_type*>(input.data_ptr()), static_cast<int32_t*>(output_page_table.data_ptr()),\n static_cast<const int32_t*>(src_page_table.data_ptr()), src_stride,\n static_cast<int32_t*>(lengths.data_ptr()), row_starts_ptr, row_to_batch_ptr, num_rows,\n static_cast<uint32_t>(top_k), max_len, row_states_ptr, deterministic, tie_break_mode,\n stream, dsa_graph_safe, page_table_row_starts_ptr);\n return true;\n });\n\n TVM_FFI_ICHECK(status == cudaSuccess)\n << \"TopKPageTableTransform failed with error code \" << cudaGetErrorString(status);\n}\n\nvoid radix_topk_ragged_transform(TensorView input, TensorView output_indices, TensorView offsets,\n TensorView lengths, Optional<TensorView> maybe_row_states_buffer,\n int64_t top_k, bool deterministic, int64_t tie_break,\n bool dsa_graph_safe, Optional<TensorView> maybe_row_starts) {\n CHECK_INPUT(input);\n CHECK_INPUT(output_indices);\n CHECK_INPUT(offsets);\n CHECK_INPUT(lengths);\n CHECK_DIM(2, input); // input: (num_rows, max_len)\n CHECK_DIM(2, output_indices); // output_indices: (num_rows, top_k)\n CHECK_DIM(1, offsets); // offsets: (num_rows,)\n CHECK_DIM(1, lengths); // lengths: (num_rows,)\n if (maybe_row_starts.has_value()) {\n CHECK_INPUT(maybe_row_starts.value());\n CHECK_DIM(1, maybe_row_starts.value());\n }\n\n unsigned int num_rows = input.size(0);\n unsigned int max_len = input.size(1);\n\n cudaSetDevice(input.device().device_id);\n auto stream = get_stream(input.device());\n\n cudaError_t status;\n auto dtype = input.dtype();\n sampling::TopKTieBreak tie_break_mode = ParseTopKTieBreak(tie_break);\n\n sampling::RadixRowState* row_states_ptr = nullptr;\n if (maybe_row_states_buffer.has_value()) {\n row_states_ptr =\n static_cast<sampling::RadixRowState*>(maybe_row_states_buffer.value().data_ptr());\n }\n int32_t* row_starts_ptr = nullptr;\n if (maybe_row_starts.has_value()) {\n TVM_FFI_ICHECK(static_cast<unsigned int>(maybe_row_starts.value().size(0)) == num_rows)\n << \"row_starts must have shape (num_rows,)\";\n row_starts_ptr = static_cast<int32_t*>(maybe_row_starts.value().data_ptr());\n }\n\n // Use unified dispatch with heuristics to choose between FilteredTopK and RadixTopK\n DISPATCH_DLPACK_DTYPE_TO_CTYPE_FP32_FP16(dtype, c_type, [&] {\n status = sampling::TopKRaggedTransformDispatch<c_type, int32_t>(\n static_cast<c_type*>(input.data_ptr()), static_cast<int32_t*>(output_indices.data_ptr()),\n static_cast<const int32_t*>(offsets.data_ptr()), static_cast<int32_t*>(lengths.data_ptr()),\n row_starts_ptr, num_rows, static_cast<uint32_t>(top_k), max_len, row_states_ptr,\n deterministic, tie_break_mode, stream, dsa_graph_safe);\n return true;\n });\n\n TVM_FFI_ICHECK(status == cudaSuccess)\n << \"TopKRaggedTransform failed with error code \" << cudaGetErrorString(status);\n}\n\nbool can_implement_filtered_topk() { return sampling::CanImplementFilteredTopK(); }\n"},"diff":{"kind":"string","value":"--- csrc/topk.cu\n+++ csrc/topk.cu\n@@ -57,9 +57,6 @@\n cudaError_t status;\n auto dtype = input.dtype();\n sampling::TopKTieBreak tie_break_mode = ParseTopKTieBreak(tie_break);\n- if (tie_break_mode != sampling::TopKTieBreak::None) {\n- deterministic = true;\n- }\n // Get row_states_buffer if provided (for multi-CTA path)\n sampling::RadixRowState* row_states_ptr = nullptr;\n if (maybe_row_states_buffer.has_value()) {\n@@ -114,9 +111,6 @@\n cudaError_t status;\n auto dtype = input.dtype();\n sampling::TopKTieBreak tie_break_mode = ParseTopKTieBreak(tie_break);\n- if (tie_break_mode != sampling::TopKTieBreak::None) {\n- deterministic = true;\n- }\n \n sampling::RadixRowState* row_states_ptr = nullptr;\n if (maybe_row_states_buffer.has_value()) {\n@@ -184,9 +178,6 @@\n cudaError_t status;\n auto dtype = input.dtype();\n sampling::TopKTieBreak tie_break_mode = ParseTopKTieBreak(tie_break);\n- if (tie_break_mode != sampling::TopKTieBreak::None) {\n- deterministic = true;\n- }\n \n sampling::RadixRowState* row_states_ptr = nullptr;\n if (maybe_row_states_buffer.has_value()) {"},"lines_added":{"kind":"number","value":0,"string":"0"},"lines_removed":{"kind":"number","value":9,"string":"9"},"files_in_commit":{"kind":"number","value":3,"string":"3"},"models_mentioned":{"kind":"list like","value":["deepseek"],"string":"[\n \"deepseek\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["B200","SM100"],"string":"[\n \"B200\",\n \"SM100\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":["1.141x","1.123x","1.182x","1.135x","1.071x","1.170x","1.080x","1.034x","1.145x","1.078x"],"string":"[\n \"1.141x\",\n \"1.123x\",\n \"1.182x\",\n \"1.135x\",\n \"1.071x\",\n \"1.170x\",\n \"1.080x\",\n \"1.034x\",\n \"1.145x\",\n \"1.078x\"\n]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (csrc/topk.cu).\n\nGoal: perf(topk): skip output index sort for tie-break selection\nTarget hardware: B200, SM100\nTarget models: deepseek\n\nCurrent file:\n```cuda\n/*\n * Copyright (c) 2024 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include <flashinfer/sampling.cuh>\n#include <flashinfer/topk.cuh>\n\n#include \"tvm_ffi_utils.h\"\n\nusing namespace flashinfer;\n\nusing tvm::ffi::Optional;\n\ninline sampling::TopKTieBreak ParseTopKTieBreak(int64_t tie_break) {\n switch (tie_break) {\n case 0:\n return sampling::TopKTieBreak::None;\n case 1:\n return sampling::TopKTieBreak::Small;\n case 2:\n return sampling::TopKTieBreak::Large;\n default:\n TVM_FFI_ICHECK(false)\n << \"Invalid tie_break mode \" << tie_break\n << \", expected 0 (none), 1 (prefer small indices), or 2 (prefer large indices)\";\n return sampling::TopKTieBreak::None;\n }\n}\n\nvoid radix_topk(TensorView input, TensorView output_indices, TensorView output_values,\n Optional<TensorView> maybe_row_states_buffer, int64_t top_k, bool sorted_output,\n bool deterministic, int64_t tie_break, bool dsa_graph_safe) {\n CHECK_INPUT(input);\n CHECK_INPUT(output_indices);\n CHECK_INPUT(output_values);\n CHECK_DIM(2, input); // input: (batch_size, d)\n CHECK_DIM(2, output_indices); // output_indices: (batch_size, top_k)\n CHECK_DIM(2, output_values); // output_values: (batch_size, top_k)\n\n unsigned int batch_size = input.size(0);\n unsigned int d = input.size(1);\n\n cudaSetDevice(input.device().device_id);\n auto stream = get_stream(input.device());\n\n cudaError_t status;\n auto dtype = input.dtype();\n sampling::TopKTieBreak tie_break_mode = ParseTopKTieBreak(tie_break);\n if (tie_break_mode != sampling::TopKTieBreak::None) {\n deterministic = true;\n }\n // Get row_states_buffer if provided (for multi-CTA path)\n sampling::RadixRowState* row_states_ptr = nullptr;\n if (maybe_row_states_buffer.has_value()) {\n row_states_ptr =\n static_cast<sampling::RadixRowState*>(maybe_row_states_buffer.value().data_ptr());\n }\n\n // Use unified dispatch with heuristics to choose between FilteredTopK and RadixTopK\n DISPATCH_DLPACK_DTYPE_TO_CTYPE_FP32_FP16(dtype, c_type, [&] {\n status = sampling::TopKDispatch<c_type, int32_t>(\n static_cast<c_type*>(input.data_ptr()), static_cast<int32_t*>(output_indices.data_ptr()),\n static_cast<c_type*>(output_values.data_ptr()), batch_size, static_cast<uint32_t>(top_k), d,\n row_states_ptr, sorted_output, deterministic, tie_break_mode, stream, dsa_graph_safe);\n return true;\n });\n\n TVM_FFI_ICHECK(status == cudaSuccess)\n << \"TopK failed with error code \" << cudaGetErrorString(status);\n}\n\nvoid radix_topk_page_table_transform(TensorView input, TensorView output_page_table,\n TensorView src_page_table,\n Optional<TensorView> maybe_row_to_batch, TensorView lengths,\n Optional<TensorView> maybe_row_states_buffer, int64_t top_k,\n bool deterministic, int64_t tie_break, bool dsa_graph_safe,\n Optional<TensorView> maybe_row_starts,\n Optional<TensorView> maybe_page_table_row_starts) {\n CHECK_INPUT(input);\n CHECK_INPUT(output_page_table);\n CHECK_INPUT(src_page_table);\n CHECK_INPUT(lengths);\n CHECK_DIM(2, input); // input: (num_rows, max_len)\n CHECK_DIM(2, output_page_table); // output_page_table: (num_rows, top_k)\n CHECK_DIM(2, src_page_table); // src_page_table: (batch_size, max_len)\n CHECK_DIM(1, lengths); // lengths: (num_rows,)\n if (maybe_row_starts.has_value()) {\n CHECK_INPUT(maybe_row_starts.value());\n CHECK_DIM(1, maybe_row_starts.value());\n }\n if (maybe_page_table_row_starts.has_value()) {\n CHECK_INPUT(maybe_page_table_row_starts.value());\n CHECK_DIM(1, maybe_page_table_row_starts.value());\n }\n\n unsigned int num_rows = input.size(0);\n unsigned int max_len = input.size(1);\n int64_t src_stride = src_page_table.stride(0);\n\n cudaSetDevice(input.device().device_id);\n auto stream = get_stream(input.device());\n\n cudaError_t status;\n auto dtype = input.dtype();\n sampling::TopKTieBreak tie_break_mode = ParseTopKTieBreak(tie_break);\n if (tie_break_mode != sampling::TopKTieBreak::None) {\n deterministic = true;\n }\n\n sampling::RadixRowState* row_states_ptr = nullptr;\n if (maybe_row_states_buffer.has_value()) {\n row_states_ptr =\n static_cast<sampling::RadixRowState*>(maybe_row_states_buffer.value().data_ptr());\n }\n\n int32_t* row_to_batch_ptr = nullptr;\n if (maybe_row_to_batch.has_value()) {\n row_to_batch_ptr = static_cast<int32_t*>(maybe_row_to_batch.value().data_ptr());\n }\n int32_t* row_starts_ptr = nullptr;\n if (maybe_row_starts.has_value()) {\n TVM_FFI_ICHECK(static_cast<unsigned int>(maybe_row_starts.value().size(0)) == num_rows)\n << \"row_starts must have shape (num_rows,)\";\n row_starts_ptr = static_cast<int32_t*>(maybe_row_starts.value().data_ptr());\n }\n int32_t* page_table_row_starts_ptr = nullptr;\n if (maybe_page_table_row_starts.has_value()) {\n TVM_FFI_ICHECK(static_cast<unsigned int>(maybe_page_table_row_starts.value().size(0)) ==\n num_rows)\n << \"page_table_row_starts must have shape (num_rows,)\";\n page_table_row_starts_ptr =\n static_cast<int32_t*>(maybe_page_table_row_starts.value().data_ptr());\n }\n\n // Use unified dispatch with heuristics to choose between FilteredTopK and RadixTopK\n DISPATCH_DLPACK_DTYPE_TO_CTYPE_FP32_FP16(dtype, c_type, [&] {\n status = sampling::TopKPageTableTransformDispatch<c_type, int32_t>(\n static_cast<c_type*>(input.data_ptr()), static_cast<int32_t*>(output_page_table.data_ptr()),\n static_cast<const int32_t*>(src_page_table.data_ptr()), src_stride,\n static_cast<int32_t*>(lengths.data_ptr()), row_starts_ptr, row_to_batch_ptr, num_rows,\n static_cast<uint32_t>(top_k), max_len, row_states_ptr, deterministic, tie_break_mode,\n stream, dsa_graph_safe, page_table_row_starts_ptr);\n return true;\n });\n\n TVM_FFI_ICHECK(status == cudaSuccess)\n << \"TopKPageTableTransform failed with error code \" << cudaGetErrorString(status);\n}\n\nvoid radix_topk_ragged_transform(TensorView input, TensorView output_indices, TensorView offsets,\n TensorView lengths, Optional<TensorView> maybe_row_states_buffer,\n int64_t top_k, bool deterministic, int64_t tie_break,\n bool dsa_graph_safe, Optional<TensorView> maybe_row_starts) {\n CHECK_INPUT(input);\n CHECK_INPUT(output_indices);\n CHECK_INPUT(offsets);\n CHECK_INPUT(lengths);\n CHECK_DIM(2, input); // input: (num_rows, max_len)\n CHECK_DIM(2, output_indices); // output_indices: (num_rows, top_k)\n CHECK_DIM(1, offsets); // offsets: (num_rows,)\n CHECK_DIM(1, lengths); // lengths: (num_rows,)\n if (maybe_row_starts.has_value()) {\n CHECK_INPUT(maybe_row_starts.value());\n CHECK_DIM(1, maybe_row_starts.value());\n }\n\n unsigned int num_rows = input.size(0);\n unsigned int max_len = input.size(1);\n\n cudaSetDevice(input.device().device_id);\n auto stream = get_stream(input.device());\n\n cudaError_t status;\n auto dtype = input.dtype();\n sampling::TopKTieBreak tie_break_mode = ParseTopKTieBreak(tie_break);\n if (tie_break_mode != sampling::TopKTieBreak::None) {\n deterministic = true;\n }\n\n sampling::RadixRowState* row_states_ptr = nullptr;\n if (maybe_row_states_buffer.has_value()) {\n row_states_ptr =\n static_cast<sampling::RadixRowState*>(maybe_row_states_buffer.value().data_ptr());\n }\n int32_t* row_starts_ptr = nullptr;\n if (maybe_row_starts.has_value()) {\n TVM_FFI_ICHECK(static_cast<unsigned int>(maybe_row_starts.value().size(0)) == num_rows)\n << \"row_starts must have shape (num_rows,)\";\n row_starts_ptr = static_cast<int32_t*>(maybe_row_starts.value().data_ptr());\n }\n\n // Use unified dispatch with heuristics to choose between FilteredTopK and RadixTopK\n DISPATCH_DLPACK_DTYPE_TO_CTYPE_FP32_FP16(dtype, c_type, [&] {\n status = sampling::TopKRaggedTransformDispatch<c_type, int32_t>(\n static_cast<c_type*>(input.data_ptr()), static_cast<int32_t*>(output_indices.data_ptr()),\n static_cast<const int32_t*>(offsets.data_ptr()), static_cast<int32_t*>(lengths.data_ptr()),\n row_starts_ptr, num_rows, static_cast<uint32_t>(top_k), max_len, row_states_ptr,\n deterministic, tie_break_mode, stream, dsa_graph_safe);\n return true;\n });\n\n TVM_FFI_ICHECK(status == cudaSuccess)\n << \"TopKRaggedTransform failed with error code \" << cudaGetErrorString(status);\n}\n\nbool can_implement_filtered_topk() { return sampling::CanImplementFilteredTopK(); }\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\n@humansand\n\nFollow-up to #3095.\n\n`tie_break` determines which equal-valued elements are selected at the top-k boundary. Today, requesting a tie-break also promotes the public `deterministic` flag, which runs the index-ordering finalizer even though the default API output is unsorted.\n\nThis PR separates deterministic selection from deterministic output ordering:\n\n- tie-break modes still use deterministic filtered selection so `SMALL`/`LARGE` choose the intended boundary indices;\n- the shared `FinalizeTopKIndicesKernel` always finalizes/remaps indices, with `SORT_LOCAL_INDICES` as the compile-time switch for its optional local-index radix sort;\n- explicit `deterministic=True` retains the existing CUB index sort and repeatable output order;\n- tie-break with `deterministic=False` skips the finalizer entirely for plain Top-K, while page-table/ragged transforms run only the required remapping work;\n- `can_use_clusters_topk` now receives `tie_break` and rejects tie-break modes at the same early-exit boundary as `dsa_graph_safe`;\n- API documentation, exact-set/remapping tests, and the Top-K benchmark driver reflect that tie-breaking controls selection, not output order.\n\n`sorted=True` remains unchanged and still requests descending value order.\n\n#### `sorted` and `deterministic` use different sort keys\n\nThese options are independent and should not be conflated:\n\n| Option | Contract | Sort key/order |\n|---|---|---|\n| `sorted=True` | Return the selected top-k elements in score order, matching `torch.topk(..., sorted=True)` | value descending, carrying the corresponding index |\n| `deterministic=True` | Make selection and output ordering repeatable for a fixed input and system | on the filtered path, local/original index ascending, carrying the corresponding value |\n\nThe deterministic filtered-path index sort is a canonicalization step; it does **not** imply descending score order. If both options are enabled, FlashInfer first establishes deterministic index order and then applies a stable descending value sort. Equal values therefore retain the deterministic prior order. For page-table and ragged transforms, local indices are canonicalized before remapping, so the returned mapped IDs are not necessarily numerically sorted.\n\n`tie_break` is separate from both: it controls which equal-valued elements are selected at the top-k boundary, not the final output order.\n\n### Performance\n\nBoth sides used the same final benchmark driver and ran on the same physical GPU (`CUDA_VISIBLE_DEVICES=2`) in the `flashinfer-pr4048-cu132` devbox from the `hell` queue. Speedup is `BEFORE / AFTER`.\n\n| Environment | Value |\n|---|---|\n| GPU | NVIDIA B200 (`sm100`) |\n| CUDA toolkit | 13.2.1 |\n| PyTorch | 2.13.0+cu132 |\n| Driver | 580.126.09 |\n| CUPTI Python/native | 13.2.0 / 13.2.75 |\n| FlashInfer source version | 0.6.17 |\n| BEFORE | `upstream/main` at `668a1ba1ca86432c79f6adad37ecfce8d06ec083` |\n| AFTER | `89c649679af75792b2cad1020c91b41bf2262adc` |\n| Timing | CUPTI activity timing, no CUDA graph replay, cold L2, 10 dry runs, 100 measured iterations, median |\n\nThe shared timer supports CUPTI with and without CUDA graphs. A control sweep with CUPTI + CUDA graphs + cold-L2 reproduced the same illegal-memory-access failure on both upstream `main` and this branch at the first 128K page-table row, so it is not specific to this PR's kernel changes. The final benchmark follows existing FlashInfer CUPTI microbenchmarks by using `enable_cupti=True` with `use_cuda_graph=False`; no benchmark-specific environment, global, or CLI escape hatch remains.\n\nCommands:\n\n```bash\nexport CUDA_VISIBLE_DEVICES=2\n\npython benchmarks/bench_topk.py \\\n --op dsa_topk \\\n --dtype bf16 \\\n --dsa-input-pattern dsa_relu \\\n --dsa-case all \\\n --dsa-topk 2048 \\\n --tie-break\n\npython benchmarks/bench_topk.py \\\n --op varlen \\\n --dtype bf16 \\\n --length-dist causal \\\n --varlen-k 2048 \\\n --varlen-q-len 128 \\\n --tie-break\n```\n\nSummary (geometric mean across cases):\n\n| Suite | Tie-break | Geomean speedup | Case range |\n|---|---:|---:|---:|\n| DSA Top-K | small | **1.141x** | 1.123x–1.182x |\n| DSA Top-K | large | **1.135x** | 1.071x–1.170x |\n| Varlen page-table | small | **1.080x** | 1.034x–1.145x |\n| Varlen page-table | large | **1.078x** | 1.035x–1.139x |\n| Varlen ragged | small | **1.121x** | 1.061x–1.186x |\n| Varlen ragged | large | **1.119x** | 1.061x–1.195x |\n\nDSA Top-K results (latency in µs):\n\n| Case | Small BEFORE | Small AFTER | Speedup | Large BEFORE | Large AFTER | Speedup |\n|---|---:|---:|---:|---:|---:|---:|\n| `decode_b1_q1_l128k` | 83.17 | 74.08 | **1.123x** | 84.54 | 72.24 | **1.170x** |\n| `decode_b8_q1_l64k` | 80.69 | 68.29 | **1.182x** | 79.04 | 67.86 | **1.165x** |\n| `decode_b32_q1_l128k` | 90.56 | 80.51 | **1.125x** | 85.92 | 80.19 | **1.071x** |\n| `prefill_b1_q128_l128k` | 91.41 | 80.51 | **1.135x** | 91.33 | 80.43 | **1.136x** |\n\nVariable-length transform results (latency in µs):\n\n| Transform | Rows | Max length | Small BEFORE | Small AFTER | Speedup | Large BEFORE | Large AFTER | Speedup |\n|---|---:|---:|---:|---:|---:|---:|---:|---:|\n| page-table | 512 | 16,384 | 49.06 | 42.85 | **1.145x** | 49.09 | 43.10 | **1.139x** |\n| ragged | 512 | 16,384 | 47.87 | 40.35 | **1.186x** | 48.10 | 40.26 | **1.195x** |\n| page-table | 512 | 65,536 | 86.38 | 79.07 | **1.092x** | 87.66 | 80.67 | **1.087x** |\n| ragged | 512 | 65,536 | 84.80 | 75.50 | **1.123x** | 85.39 | 76.99 | **1.109x** |\n| page-table | 512 | 131,072 | 99.63 | 92.54 | **1.077x** | 99.92 | 92.80 | **1.077x** |\n| ragged | 512 | 131,072 | 98.61 | 89.41 | **1.103x** | 98.75 | 89.68 | **1.101x** |\n| page-table | 2,048 | 16,384 | 172.29 | 157.33 | **1.095x** | 173.63 | 158.94 | **1.092x** |\n| ragged | 2,048 | 16,384 | 170.30 | 144.35 | **1.180x** | 171.66 | 145.87 | **1.177x** |\n| page-table | 2,048 | 65,536 | 442.69 | 424.46 | **1.043x** | 444.54 | 426.35 | **1.043x** |\n| ragged | 2,048 | 65,536 | 437.07 | 405.06 | **1.079x** | 438.82 | 406.80 | **1.079x** |\n| page-table | 2,048 | 131,072 | 565.89 | 547.06 | **1.034x** | 568.35 | 548.93 | **1.035x** |\n| ragged | 2,048 | 131,072 | 558.54 | 526.56 | **1.061x** | 561.33 | 529.02 | **1.061x** |\n\n<details>\n<summary>Raw BEFORE output: DSA Top-K</summary>\n\n```text\n====================================================================================================\ndsa_topk: DeepSeek DSA-like indexer top-k workload (dtype=BF16, deterministic=False, dsa_pattern=dsa_relu, k=2048, tie_break=True)\nNOTE: tie-break columns use deterministic=False; slowdowns use the non-deterministic baseline\n====================================================================================================\n case rows seq_len k | FlashInfer FlashInfer(det) DetSlowdown FlashInfer(tie-small) TieSmallSlowdown FlashInfer(tie-large) TieLargeSlowdown torch.topk Speedup\n------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------\n decode_b1_q1_l128k 1 131072 2048 | 40.90us n/a n/a 83.17us 2.03x 84.54us 2.07x 75.44us 1.84x\n decode_b8_q1_l64k 8 65536 2048 | 40.75us n/a n/a 80.69us 1.98x 79.04us 1.94x 82.86us 2.03x\n decode_b32_q1_l128k 32 131072 2048 | 45.66us n/a n/a 90.56us 1.98x 85.92us 1.88x 112.77us 2.47x\n prefill_b1_q128_l128k 128 131072 2048 | 82.61us n/a n/a 91.41us 1.11x 91.33us 1.11x 197.28us 2.39x\n```\n\n</details>\n\n<details>\n<summary>Raw AFTER output: DSA Top-K</summary>\n\n```text\n====================================================================================================\ndsa_topk: DeepSeek DSA-like indexer top-k workload (dtype=BF16, deterministic=False, dsa_pattern=dsa_relu, k=2048, tie_break=True)\nNOTE: tie-break columns use deterministic=False; slowdowns use the non-deterministic baseline\n====================================================================================================\n case rows seq_len k | FlashInfer FlashInfer(det) DetSlowdown FlashInfer(tie-small) TieSmallSlowdown FlashInfer(tie-large) TieLargeSlowdown torch.topk Speedup\n------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------\n decode_b1_q1_l128k 1 131072 2048 | 41.02us n/a n/a 74.08us 1.81x 72.24us 1.76x 73.60us 1.79x\n decode_b8_q1_l64k 8 65536 2048 | 40.69us n/a n/a 68.29us 1.68x 67.86us 1.67x 82.58us 2.03x\n decode_b32_q1_l128k 32 131072 2048 | 45.89us n/a n/a 80.51us 1.75x 80.19us 1.75x 112.69us 2.46x\n prefill_b1_q128_l128k 128 131072 2048 | 82.59us n/a n/a 80.51us 0.97x 80.43us 0.97x 198.18us 2.40x\n```\n\n</details>\n\n<details>\n<summary>Raw BEFORE output: variable-length transforms</summary>\n\n```text\n====================================================================================================\nvarlen: Variable-length segment top-k transforms (production-realistic) (dtype=BF16, length_dist=causal, k=2048, deterministic=False, tie_break=True)\nNOTE: lengths model per-row valid windows; decode = independent context lengths, prefill(causal) = monotonic growth within a request (q_len=128)\nNOTE: torch(mask) masks invalid positions once (outside timing) then torch.topk, isolating selection cost vs the length-aware kernel\nNOTE: tie-break columns use deterministic=False; slowdowns use the non-deterministic baseline\nNOTE: Clusters column omitted under deterministic/tie-break (clusters requires the non-deterministic path)\n====================================================================================================\n regime dist transform rows reqs max_len k | len_min len_mean len_max triv% | FlashInfer FlashInfer(det) DetSlowdown FlashInfer(tie-small) TieSmallSlowdown FlashInfer(tie-large) TieLargeSlowdown torch(mask) Speedup\n--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------\n prefill causal page_table 512 4 16384 2048 | 375 7109.2 12411 25.0% | 30.34us n/a n/a 49.06us 1.62x 49.09us 1.62x 153.26us 5.05x\n prefill causal ragged 512 4 16384 2048 | 375 7109.2 12411 25.0% | 27.33us n/a n/a 47.87us 1.75x 48.10us 1.76x 152.34us 5.57x\n prefill causal page_table 512 4 65536 2048 | 2039 22253.8 37156 2.0% | 65.44us n/a n/a 86.38us 1.32x 87.66us 1.34x 308.99us 4.72x\n prefill causal ragged 512 4 65536 2048 | 2039 22253.8 37156 2.0% | 60.43us n/a n/a 84.80us 1.40x 85.39us 1.41x 309.34us 5.12x\n prefill causal page_table 512 4 131072 2048 | 524 33177.8 101452 25.0% | 152.19us n/a n/a 99.63us 0.65x 99.92us 0.66x 592.27us 3.89x\n prefill causal ragged 512 4 131072 2048 | 524 33177.8 101452 25.0% | 144.70us n/a n/a 98.61us 0.68x 98.75us 0.68x 591.23us 4.09x\n prefill causal page_table 2048 16 16384 2048 | 416 7917.1 15346 12.5% | 122.30us n/a n/a 172.29us 1.41x 173.63us 1.42x 366.67us 3.00x\n prefill causal ragged 2048 16 16384 2048 | 416 7917.1 15346 12.5% | 111.49us n/a n/a 170.30us 1.53x 171.66us 1.54x 367.58us 3.30x\n prefill causal page_table 2048 16 65536 2048 | 7804 36260.2 63720 0.0% | 318.27us n/a n/a 442.69us 1.39x 444.54us 1.40x 1114.34us 3.50x\n prefill causal ragged 2048 16 65536 2048 | 7804 36260.2 63720 0.0% | 298.85us n/a n/a 437.07us 1.46x 438.82us 1.47x 1114.48us 3.73x\n prefill causal page_table 2048 16 131072 2048 | 7095 60508.9 124975 0.0% | 870.77us n/a n/a 565.89us 0.65x 568.35us 0.65x 2000.19us 2.30x\n prefill causal ragged 2048 16 131072 2048 | 7095 60508.9 124975 0.0% | 849.74us n/a n/a 558.54us 0.66x 561.33us 0.66x 2001.38us 2.36x\n```\n\n</details>\n\n<details>\n<summary>Raw AFTER output: variable-length transforms</summary>\n\n```text\n====================================================================================================\nvarlen: Variable-length segment top-k transforms (production-realistic) (dtype=BF16, length_dist=causal, k=2048, deterministic=False, tie_break=True)\nNOTE: lengths model per-row valid windows; decode = independent context lengths, prefill(causal) = monotonic growth within a request (q_len=128)\nNOTE: torch(mask) masks invalid positions once (outside timing) then torch.topk, isolating selection cost vs the length-aware kernel\nNOTE: tie-break columns use deterministic=False; slowdowns use the non-deterministic baseline\nNOTE: Clusters column omitted under deterministic/tie-break (clusters requires the non-deterministic path)\n====================================================================================================\n regime dist transform rows reqs max_len k | len_min len_mean len_max triv% | FlashInfer FlashInfer(det) DetSlowdown FlashInfer(tie-small) TieSmallSlowdown FlashInfer(tie-large) TieLargeSlowdown torch(mask) Speedup\n--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------\n prefill causal page_table 512 4 16384 2048 | 375 7109.2 12411 25.0% | 30.30us n/a n/a 42.85us 1.41x 43.10us 1.42x 153.52us 5.07x\n prefill causal ragged 512 4 16384 2048 | 375 7109.2 12411 25.0% | 27.39us n/a n/a 40.35us 1.47x 40.26us 1.47x 152.86us 5.58x\n prefill causal page_table 512 4 65536 2048 | 2039 22253.8 37156 2.0% | 65.34us n/a n/a 79.07us 1.21x 80.67us 1.23x 309.01us 4.73x\n prefill causal ragged 512 4 65536 2048 | 2039 22253.8 37156 2.0% | 60.45us n/a n/a 75.50us 1.25x 76.99us 1.27x 310.05us 5.13x\n prefill causal page_table 512 4 131072 2048 | 524 33177.8 101452 25.0% | 152.22us n/a n/a 92.54us 0.61x 92.80us 0.61x 591.52us 3.89x\n prefill causal ragged 512 4 131072 2048 | 524 33177.8 101452 25.0% | 144.75us n/a n/a 89.41us 0.62x 89.68us 0.62x 591.46us 4.09x\n prefill causal page_table 2048 16 16384 2048 | 416 7917.1 15346 12.5% | 122.27us n/a n/a 157.33us 1.29x 158.94us 1.30x 366.85us 3.00x\n prefill causal ragged 2048 16 16384 2048 | 416 7917.1 15346 12.5% | 111.52us n/a n/a 144.35us 1.29x 145.87us 1.31x 366.70us 3.29x\n prefill causal page_table 2048 16 65536 2048 | 7804 36260.2 63720 0.0% | 318.19us n/a n/a 424.46us 1.33x 426.35us 1.34x 1113.92us 3.50x\n prefill causal ragged 2048 16 65536 2048 | 7804 36260.2 63720 0.0% | 298.83us n/a n/a 405.06us 1.36x 406.80us 1.36x 1114.29us 3.73x\n prefill causal page_table 2048 16 131072 2048 | 7095 60508.9 124975 0.0% | 870.80us n/a n/a 547.06us 0.63x 548.93us 0.63x 1999.70us 2.30x\n prefill causal ragged 2048 16 131072 2048 | 7095 60508.9 124975 0.0% | 849.66us n/a n/a 526.56us 0.62x 529.02us 0.62x 2000.72us 2.35x\n```\n\n</details>\n\n## 🔍 Related Issues\n\n- Follow-up to #3095.\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used my preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n```text\npython -m pytest -q tests/utils/test_topk.py\n1396 passed, 2 warnings in 75.78s\n\npre-commit run --all-files\nall hooks passed\n```\n\nCoverage includes:\n\n- unordered exact-set checks for `SMALL`/`LARGE` tie-break output;\n- an explicit clusters override that verifies tie-break modes take the filtered path;\n- page-table/ragged transforms with non-identity remapping;\n- explicit `deterministic=True` ordering for plain and transform APIs;\n- BF16 long-context filtered Top-K at 128K sequence length and `k=2048`.\n\n## Reviewer Notes\n\nThe intended contract is:\n\n- `tie_break` controls deterministic boundary selection only;\n- `deterministic=True` additionally requests repeatable output ordering;\n- `sorted=True` continues to request descending value order.\n\nThe key implementation detail is keeping `DETERMINISTIC` for filtered selection. The shared `FinalizeTopKIndicesKernel` always performs final mapping/writeback; `SORT_LOCAL_INDICES` independently controls its pre-writeback CUB sort. Transformed tie-break outputs retain the remap path with sorting disabled, while plain tie-break output skips the finalizer entirely.\n\nThe benchmark driver keeps CUPTI enabled and disables CUDA graph replay, matching other FlashInfer CUPTI microbenchmarks. This avoids adding a benchmark-global variable, environment setting, or CLI fallback solely for this workload.\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n* **Behavior Updates**\n * Tie-breaking and deterministic ordering are now controlled independently.\n * Selecting a tie-break option no longer automatically enables deterministic execution.\n * Deterministic mode provides consistent index ordering; tie-breaking alone does not guarantee output order.\n * Clustered execution avoids unsupported tie-break and graph-safe combinations.\n * Page-table and ragged Top-K transformations preserve correct ordering and index mappings.\n\n* **Benchmarking**\n * Top-K benchmarks now provide more consistent timing comparisons against the nondeterministic baseline.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": \"NVIDIA B200\", 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\"transform=ragged,rows=2048,max_len=16384,k=2048\", \"batch_size\": 2048, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 170.3, \"optimized\": 144.35, \"stated_speedup\": 1.18, \"speedup\": 1.1798}, {\"scope\": \"kernel\", \"hardware\": \"NVIDIA B200\", \"model\": null, \"shape\": \"transform=ragged,rows=2048,max_len=16384,k=2048\", \"batch_size\": 2048, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 171.66, \"optimized\": 145.87, \"stated_speedup\": 1.177, \"speedup\": 1.1768}, {\"scope\": \"kernel\", \"hardware\": \"NVIDIA B200\", \"model\": null, \"shape\": \"transform=page-table,rows=2048,max_len=65536,k=2048\", \"batch_size\": 2048, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 442.69, \"optimized\": 424.46, \"stated_speedup\": 1.043, \"speedup\": 1.0429}, {\"scope\": \"kernel\", \"hardware\": \"NVIDIA B200\", \"model\": null, \"shape\": \"transform=page-table,rows=2048,max_len=65536,k=2048\", \"batch_size\": 2048, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 444.54, \"optimized\": 426.35, \"stated_speedup\": 1.043, \"speedup\": 1.0427}, {\"scope\": \"kernel\", \"hardware\": \"NVIDIA B200\", \"model\": null, \"shape\": \"transform=ragged,rows=2048,max_len=65536,k=2048\", \"batch_size\": 2048, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 437.07, \"optimized\": 405.06, \"stated_speedup\": 1.079, \"speedup\": 1.079}, {\"scope\": \"kernel\", \"hardware\": \"NVIDIA B200\", \"model\": null, \"shape\": \"transform=ragged,rows=2048,max_len=65536,k=2048\", \"batch_size\": 2048, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 438.82, \"optimized\": 406.8, \"stated_speedup\": 1.079, \"speedup\": 1.0787}, {\"scope\": \"kernel\", \"hardware\": \"NVIDIA B200\", \"model\": null, \"shape\": \"transform=page-table,rows=2048,max_len=131072,k=2048\", \"batch_size\": 2048, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 565.89, \"optimized\": 547.06, \"stated_speedup\": 1.034, \"speedup\": 1.0344}, {\"scope\": \"kernel\", \"hardware\": \"NVIDIA B200\", \"model\": null, \"shape\": \"transform=page-table,rows=2048,max_len=131072,k=2048\", \"batch_size\": 2048, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 568.35, \"optimized\": 548.93, \"stated_speedup\": 1.035, \"speedup\": 1.0354}, {\"scope\": \"kernel\", \"hardware\": \"NVIDIA B200\", \"model\": null, \"shape\": \"transform=ragged,rows=2048,max_len=131072,k=2048\", \"batch_size\": 2048, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 558.54, \"optimized\": 526.56, \"stated_speedup\": 1.061, \"speedup\": 1.0607}, {\"scope\": \"kernel\", \"hardware\": \"NVIDIA B200\", \"model\": null, \"shape\": \"transform=ragged,rows=2048,max_len=131072,k=2048\", \"batch_size\": 2048, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 561.33, \"optimized\": 529.02, \"stated_speedup\": 1.061, \"speedup\": 1.0611}]"},"kernel_speedup":{"kind":"number","value":1.102,"string":"1.102"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1095,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"67f76379a145f19793896394974e29e610cda912"},"date":{"kind":"string","value":"2026-08-04T15:17:59+08:00"},"pr_number":{"kind":"number","value":4210,"string":"4,210"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/4210"},"title":{"kind":"string","value":"perf: remove NVFP4 TMA input padding copy (#4210)"},"message":{"kind":"string","value":"perf: remove NVFP4 TMA input padding copy (#4210)\n\n## 📌 Description\n\nRemove the temporary padded input allocation and full-tensor copy from\nthe CuTe DSL NVFP4 TMA path. The TMA tensor map now describes the\nphysical `M` rows and relies on G2S TMA out-of-bounds zero fill for row\ntiles that extend into the padded scale layout. The FP4 output remains\nbounded by `M`, while padded scale rows are still explicitly zeroed.\n\nThis keeps the existing TMA pipeline and 128x4 scale layout while\neliminating the non-128-aligned `M` copy cliff.\n\n### B200 performance\n\nConfiguration: NVIDIA B200, BF16 input, `K=4096`, 128x4 scale layout,\nPDL enabled, eager/no CUDA Graph, cold L2, CUPTI timing. Each value is\nthe median of three runs with 20 warmups and 100 measured iterations per\nrun.\n\n| M | Aligned to 128 | TMA + input copy (µs) | Vectorized (µs) | This PR\n(µs) |\n|---:|:---:|---:|---:|---:|\n| 32283 | No | 212.446 | 62.399 | **59.248** |\n| 32384 | Yes | 59.072 | 62.399 | **59.312** |\n| 32386 | No | 213.054 | 62.367 | **59.151** |\n| 32512 | Yes | 59.375 | 62.431 | **59.184** |\n| 32621 | No | 213.581 | 62.031 | **59.423** |\n| 32640 | Yes | 59.455 | 62.031 | **59.392** |\n| 32733 | No | 213.902 | 62.080 | **59.407** |\n| 32768 | Yes | 59.439 | 61.967 | **59.552** |\n\nFor non-aligned 32K shapes, this reduces API GPU time by 72.1%–72.2%\nversus TMA with the padded input copy and is 4.2%–5.2% faster than the\nvectorized path. For aligned shapes, it stays within ±0.41% of the\nprevious TMA path and is 3.9%–5.2% faster than vectorized. `M=6326/6400`\nremains on the existing vectorized heuristic and is unaffected by this\nTMA change.\n\nReproduction template:\n\n```bash\nFLASHINFER_NVFP4_QUANTIZE_USE_TMA=1 python3 benchmarks/flashinfer_benchmark.py --routine nvfp4_quantize --backends cute-dsl --m 32283 --k 4096 --input_dtype bfloat16 --global_scale 1.0 --sf_layout 128x4 --sf_vec_size 16 --enable_pdl --no_cuda_graph --dry_run_iters 20 --num_iters 100 --refcheck -vv\n```\n\n## 🔍 Related Issues\n\nRelated to #3905.\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [ ] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see the\n[pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] Relevant B200 validation is passing: FP16/BF16 partial- and\nfully-OOB cross-path checks, nonzero-sentinel padding-scale checks, and\n`compute-sanitizer --tool memcheck` (`ERROR SUMMARY: 0 errors`).\n\n## Reviewer Notes\n\nThe TMA descriptor uses the physical `M`, but the kernel intentionally\ncontinues through `padded_M` to initialize the scale layout. The focused\nregression case uses `M=8193`, which produces one partial TMA tile\nfollowed by seven fully-OOB tiles before the 128-row scale boundary.\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n* **Bug Fixes**\n* Improved NVFP4 quantization for inputs whose row count requires\npadding.\n* Ensured out-of-bounds padded rows are automatically zero-filled during\nTMA processing.\n* Preserved correct quantization results and scale factors for valid\nrows.\n\n* **Tests**\n* Added coverage for non-aligned row counts and verified zero values in\npadded rows.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->"},"path":{"kind":"string","value":"flashinfer/quantization/kernels/nvfp4_quantize.py"},"language":{"kind":"string","value":"cute_dsl"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"\"\"\"\nCopyright (c) 2025 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nNVFP4 Quantization using CuTe-DSL\n=================================\n\nNVFP4 quantization kernel using CuTe-DSL.\nSupports multiple scale factor layouts: swizzled 128x4, swizzled 8x4, and linear.\n\nDual-path optimization following the MXFP4 pattern:\n- Linear layout: flat SF-block iteration for 100% thread utilization\n- Swizzled layout: row-based iteration with multi-row / column-loop paths\n\nKey differences from MXFP4:\n- sf_vec_size=16 (vs 32 for MXFP4)\n- E4M3 scale factors (vs UE8M0 for MXFP4)\n- User-provided global_scale (vs auto-computed for MXFP4)\n- 3 layouts: 128x4, 8x4, linear (vs 128x4, linear for MXFP4)\n\"\"\"\n\nimport functools\nfrom typing import Callable, Tuple, Union, cast\n\nimport cutlass\nimport cutlass.cute as cute\nimport cutlass.cute.nvgpu.cpasync as cpasync\nimport cutlass.pipeline as pipeline\nfrom cutlass.pipeline import pipeline_init_arrive, pipeline_init_wait\nimport torch\nfrom cutlass import Float32, Int32, Int64, Uint8\n\nfrom ...api_logging import flashinfer_api\nfrom ...jit.cute_dsl_core import build_and_load_cute_dsl_kernel\nfrom ...cute_dsl.fp4_common import (\n block_reduce,\n fdiv_rn,\n fmax_f32,\n fmin_f32,\n get_ptr_as_int64,\n ld_global_v4_u32,\n rcp_approx_ftz,\n st_global_u64,\n warp_reduce,\n)\nfrom ...cute_dsl.utils import get_num_sm\nfrom ..nvfp4_quantization_utils import (\n NVFP44Over6Config,\n current_nvfp4_4over6_config,\n env_flag_enabled as _env_flag_enabled,\n)\nfrom ..quantization_cute_dsl_utils import (\n FLOAT32_MAX,\n NVFP4_SF_VEC_SIZE,\n WARP_SIZE,\n ROW_TILE_SIZE,\n compute_sf_index_swizzled_128x4_gpu,\n compute_sf_index_swizzled_8x4_gpu,\n compute_sf_index_linear_gpu,\n half2_max_abs_8 as half2_max_abs_8_fn,\n bfloat2_max_abs_8 as bfloat2_max_abs_8_fn,\n hmax_reduce_to_f32,\n bfloat2_hmax_reduce_to_f32,\n half2x8_to_e2m1x16_packed,\n bfloat2x8_to_e2m1x16_packed,\n process_nvfp4_block_half,\n process_nvfp4_block_bfloat,\n process_nvfp4_block_fp8,\n process_nvfp4_silu_block_half,\n process_nvfp4_silu_block_bfloat,\n)\n\nSF_LAYOUT_128x4 = 0\nSF_LAYOUT_8x4 = 1\nSF_LAYOUT_LINEAR = 2\n\n# Blocks per SM for occupancy target\n_BLOCKS_PER_SM = 4\n\n# Maximum threads per block\n_MAX_THREADS_PER_BLOCK = 1024\n\n# Thread count bounds for swizzled kernel\n_MIN_THREADS = 128\n_MAX_THREADS = 512\n\n# Linear kernel: fixed 16 warps (512 threads), 1 SF block per thread\n_LINEAR_WARPS_PER_BLOCK = 16\n_LINEAR_SF_BLOCKS_PER_TB = _LINEAR_WARPS_PER_BLOCK * WARP_SIZE # 512\n\n\ndef _compute_optimal_threads(K: int) -> int:\n \"\"\"\n Compute optimal thread count for 100% utilization in the swizzled kernel.\n\n For NVFP4, each thread processes 1 SF block (16 elements), so:\n threads_per_row = K / 16\n\n We want num_threads to be a multiple of threads_per_row so that\n rows_per_block = num_threads / threads_per_row is an integer.\n\n We prefer LARGER thread counts (up to _MAX_THREADS) for better occupancy.\n\n If threads_per_row > _MAX_THREADS, we use _MAX_THREADS with a column loop.\n\n Args:\n K: Number of columns (must be divisible by 16)\n\n Returns:\n Optimal number of threads per block\n \"\"\"\n threads_per_row = K // NVFP4_SF_VEC_SIZE # K / 16\n\n if threads_per_row > _MAX_THREADS:\n # Column loop mode: use maximum threads\n return _MAX_THREADS\n\n # Find largest multiple of threads_per_row in [_MIN_THREADS, _MAX_THREADS]\n largest = (_MAX_THREADS // threads_per_row) * threads_per_row\n if largest >= _MIN_THREADS:\n return largest\n\n # If largest multiple is below _MIN_THREADS, use smallest valid one\n candidate = threads_per_row\n while candidate < _MIN_THREADS:\n candidate += threads_per_row\n if candidate <= _MAX_THREADS:\n return candidate\n\n # Fallback (shouldn't happen for reasonable K)\n return _MAX_THREADS\n\n\n@cute.jit\ndef _dispatch_process_nvfp4_block(\n row_input,\n elem_base: Int32,\n global_scale: Float32,\n row_amax: Float32,\n K: int,\n is_bfloat16: bool,\n is_fp8: bool,\n silu_and_mul: bool,\n disable_fp4_quant_fast_math: bool,\n nvfp4_4over6_config: NVFP44Over6Config | None,\n):\n \"\"\"Dispatch one NVFP4 block by dtype and optional SwiGLU fusion.\"\"\"\n if cutlass.const_expr(silu_and_mul):\n if cutlass.const_expr(is_bfloat16):\n return process_nvfp4_silu_block_bfloat(\n row_input,\n elem_base,\n Int32(K),\n global_scale,\n disable_fp4_quant_fast_math,\n nvfp4_4over6_config,\n row_amax,\n )\n else:\n return process_nvfp4_silu_block_half(\n row_input,\n elem_base,\n Int32(K),\n global_scale,\n disable_fp4_quant_fast_math,\n nvfp4_4over6_config,\n row_amax,\n )\n else:\n if cutlass.const_expr(is_fp8):\n return process_nvfp4_block_fp8(\n row_input, elem_base, global_scale, disable_fp4_quant_fast_math\n )\n elif cutlass.const_expr(is_bfloat16):\n return process_nvfp4_block_bfloat(\n row_input,\n elem_base,\n global_scale,\n disable_fp4_quant_fast_math,\n nvfp4_4over6_config,\n row_amax,\n )\n else:\n return process_nvfp4_block_half(\n row_input,\n elem_base,\n global_scale,\n disable_fp4_quant_fast_math,\n nvfp4_4over6_config,\n row_amax,\n )\n\n\n# =============================================================================\n# CuTe-DSL Kernel Class for Linear Layout — Flat SF-Block Iteration\n# =============================================================================\n\n\nclass NVFP4QuantizeLinearKernel:\n \"\"\"\n NVFP4 quantization kernel optimized for LINEAR layout.\n\n Uses flat SF-block iteration for efficient memory access. Row and\n column indices are derived from the flat SF index via integer division.\n\n No padding passes are needed since for linear layout:\n - padded_m == m (no row padding)\n - padded_sf_cols == num_sf_blocks_per_row (no column padding)\n\n This kernel is M-agnostic: M-dependent values are passed at runtime.\n Each thread handles one SF block (16 elements).\n \"\"\"\n\n WARPS_PER_BLOCK = _LINEAR_WARPS_PER_BLOCK\n SF_BLOCKS_PER_TB = _LINEAR_SF_BLOCKS_PER_TB\n\n def __init__(\n self,\n dtype: cutlass.Numeric,\n K: int,\n enable_pdl: bool = False,\n disable_fp4_quant_fast_math: bool = False,\n nvfp4_4over6_config: NVFP44Over6Config | None = None,\n silu_and_mul: bool = False,\n ):\n self.dtype = dtype\n self.K = K\n self.is_bfloat16 = dtype == cutlass.BFloat16\n self.is_fp8 = dtype == cutlass.Float8E4M3FN\n self.enable_pdl = enable_pdl\n self.disable_fp4_quant_fast_math = disable_fp4_quant_fast_math\n self.nvfp4_4over6_config = nvfp4_4over6_config\n # SwiGLU uses a 2*K-wide input and does not support FP8.\n self.silu_and_mul = silu_and_mul\n assert not (silu_and_mul and self.is_fp8), (\n \"SwiGLU fusion does not support fp8 input\"\n )\n\n assert K % NVFP4_SF_VEC_SIZE == 0\n self.num_sf_blocks_per_row = K // NVFP4_SF_VEC_SIZE\n\n @cute.jit\n def _process_block(\n self, row_input, elem_base: Int32, global_scale: Float32, row_amax: Float32\n ):\n \"\"\"Quantize one 16-element block, optionally fusing silu(gate) * up.\n\n For the SwiGLU path the up block sits self.K columns after the gate\n block in the same (2*K-wide) input row.\n \"\"\"\n return _dispatch_process_nvfp4_block(\n row_input,\n elem_base,\n global_scale,\n row_amax,\n self.K,\n self.is_bfloat16,\n self.is_fp8,\n self.silu_and_mul,\n self.disable_fp4_quant_fast_math,\n self.nvfp4_4over6_config,\n )\n\n @cute.jit\n def __call__(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n M: Int32,\n total_sf_blocks: Int32,\n num_blocks: Int32,\n global_scale: Union[Float32, cute.Tensor],\n stream,\n ):\n threads_per_block = self.WARPS_PER_BLOCK * WARP_SIZE\n\n self.kernel(mInput, mOutput, mScales, M, total_sf_blocks, global_scale).launch(\n grid=[num_blocks, 1, 1],\n block=[threads_per_block, 1, 1],\n max_number_threads=[_MAX_THREADS_PER_BLOCK, 1, 1],\n min_blocks_per_mp=_BLOCKS_PER_SM,\n stream=stream,\n use_pdl=self.enable_pdl,\n )\n\n @cute.kernel\n def kernel(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n M: Int32,\n total_sf_blocks: Int32,\n global_scale: Union[Float32, cute.Tensor],\n ):\n \"\"\"\n NVFP4 quantization with flat SF-block iteration for linear layout.\n\n Each thread handles one SF block (16 elements). Row and column\n indices are derived from the flat SF index.\n \"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n bidx, _, _ = cute.arch.block_idx()\n grid_dim_x, _, _ = cute.arch.grid_dim()\n\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_wait()\n\n # Device scales stay pointer-loaded; host scales arrive as launch arguments.\n if cutlass.const_expr(isinstance(global_scale, cute.Tensor)):\n global_scale_value = Float32(global_scale[Int32(0)])\n else:\n global_scale_value = global_scale\n row_amax = Float32(0.0)\n\n num_sf_blocks_per_row = self.num_sf_blocks_per_row\n sf_blocks_per_tb = self.SF_BLOCKS_PER_TB\n stride = grid_dim_x * sf_blocks_per_tb\n\n # Flat SF-block iteration\n sf_idx = bidx * sf_blocks_per_tb + tidx\n\n while sf_idx < total_sf_blocks:\n row_idx = sf_idx // num_sf_blocks_per_row\n col_idx = sf_idx % num_sf_blocks_per_row\n\n elem_base = col_idx * NVFP4_SF_VEC_SIZE\n row_input = mInput[row_idx, None]\n\n # Apply optional SwiGLU and quantize the block.\n scale_fp8, packed64 = self._process_block(\n row_input, elem_base, global_scale_value, row_amax\n )\n\n # Write scale factor using linear indexing\n sf_offset = compute_sf_index_linear_gpu(\n row_idx, col_idx, num_sf_blocks_per_row\n )\n mScales[sf_offset] = scale_fp8\n\n # Store 8 bytes (16 FP4 values = 1 x st.global.u64)\n row_output = mOutput[row_idx, None]\n out_base = col_idx * (NVFP4_SF_VEC_SIZE // 2)\n out_ptr = get_ptr_as_int64(row_output, out_base)\n st_global_u64(out_ptr, packed64)\n\n sf_idx = sf_idx + stride\n\n # PDL: Signal that dependent kernels can start early\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_launch_dependents()\n\n\n# =============================================================================\n# CuTe-DSL Kernel Class for Swizzled Layout — Row-Based Iteration\n# =============================================================================\n\n\nclass NVFP4QuantizeSwizzledKernel:\n \"\"\"\n NVFP4 quantization kernel optimized for SWIZZLED (128x4 or 8x4) layout.\n\n Key optimizations:\n - Multi-row processing: threads process multiple rows per block when K is small\n - Row-based iteration with grid-stride loop\n - Padding row fast path - only zero out scale factors\n\n Thread utilization optimization:\n - Dynamic thread count based on K for 100% thread utilization\n - For small K: Multiple rows processed per block iteration\n - For large K: Single row with column loop\n\n For NVFP4, each thread processes 1 SF block (16 elements) independently,\n so threads_per_row = num_sf_blocks_per_row = K/16.\n\n This kernel is M-agnostic: M-dependent values (M, padded_M) are passed\n at runtime.\n \"\"\"\n\n def __init__(\n self,\n dtype: cutlass.Numeric,\n K: int,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool = False,\n disable_fp4_quant_fast_math: bool = False,\n nvfp4_4over6_config: NVFP44Over6Config | None = None,\n silu_and_mul: bool = False,\n ):\n self.dtype = dtype\n self.K = K\n self.is_bfloat16 = dtype == cutlass.BFloat16\n self.is_fp8 = dtype == cutlass.Float8E4M3FN\n self.enable_pdl = enable_pdl\n self.disable_fp4_quant_fast_math = disable_fp4_quant_fast_math\n self.nvfp4_4over6_config = nvfp4_4over6_config\n self.sf_layout = sf_layout\n self.sf_is_128x4 = sf_layout == SF_LAYOUT_128x4\n self.sf_is_8x4 = sf_layout == SF_LAYOUT_8x4\n # SwiGLU uses a 2*K-wide input and does not support FP8.\n self.silu_and_mul = silu_and_mul\n assert not (silu_and_mul and self.is_fp8), (\n \"SwiGLU fusion does not support fp8 input\"\n )\n\n assert K % NVFP4_SF_VEC_SIZE == 0\n self.num_sf_blocks_per_row = K // NVFP4_SF_VEC_SIZE\n self.padded_sf_cols = ((self.num_sf_blocks_per_row + 3) // 4) * 4\n\n # Compute optimal thread count for 100% utilization\n self.num_threads = _compute_optimal_threads(K)\n self.threads_per_row = self.num_sf_blocks_per_row # 1 thread per SF block\n\n # Multi-row processing constants (compile-time)\n if self.threads_per_row <= self.num_threads:\n self.rows_per_block = self.num_threads // self.threads_per_row\n self.needs_col_loop = False\n else:\n self.rows_per_block = 1\n self.needs_col_loop = True\n\n @cute.jit\n def _compute_sf_offset(\n self, row_idx: Int32, col_idx: Int32, padded_cols: Int32\n ) -> Int32:\n \"\"\"Compute scale factor offset based on layout (compile-time dispatch).\"\"\"\n if cutlass.const_expr(self.sf_is_128x4):\n return compute_sf_index_swizzled_128x4_gpu(row_idx, col_idx, padded_cols)\n else:\n return compute_sf_index_swizzled_8x4_gpu(row_idx, col_idx, padded_cols)\n\n @cute.jit\n def _process_block(\n self, row_input, elem_base: Int32, global_scale: Float32, row_amax: Float32\n ):\n \"\"\"Quantize one 16-element block, optionally fusing silu(gate) * up.\n\n For the SwiGLU path the up block sits self.K columns after the gate\n block in the same (2*K-wide) input row.\n \"\"\"\n return _dispatch_process_nvfp4_block(\n row_input,\n elem_base,\n global_scale,\n row_amax,\n self.K,\n self.is_bfloat16,\n self.is_fp8,\n self.silu_and_mul,\n self.disable_fp4_quant_fast_math,\n self.nvfp4_4over6_config,\n )\n\n @cute.jit\n def __call__(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n M: Int32,\n padded_M: Int32,\n num_blocks: Int32,\n global_scale: Union[Float32, cute.Tensor],\n stream,\n ):\n self.kernel(mInput, mOutput, mScales, M, padded_M, global_scale).launch(\n grid=[num_blocks, 1, 1],\n block=[self.num_threads, 1, 1],\n max_number_threads=[_MAX_THREADS_PER_BLOCK, 1, 1],\n min_blocks_per_mp=_BLOCKS_PER_SM,\n stream=stream,\n use_pdl=self.enable_pdl,\n )\n\n @cute.kernel\n def kernel(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n M: Int32,\n padded_M: Int32,\n global_scale: Union[Float32, cute.Tensor],\n ):\n \"\"\"\n Row-based kernel for swizzled layout.\n\n When K is small: each block processes multiple rows simultaneously.\n When K is large: each block processes one row with column loop.\n \"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n bidx, _, _ = cute.arch.block_idx()\n grid_dim_x, _, _ = cute.arch.grid_dim()\n\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_wait()\n\n # Device scales stay pointer-loaded; host scales arrive as launch arguments.\n if cutlass.const_expr(isinstance(global_scale, cute.Tensor)):\n global_scale_value = Float32(global_scale[Int32(0)])\n else:\n global_scale_value = global_scale\n row_amax = Float32(0.0)\n\n # Compile-time constants\n num_sf_blocks_per_row = self.num_sf_blocks_per_row\n padded_sf_cols = self.padded_sf_cols\n threads_per_row = self.threads_per_row\n rows_per_block = self.rows_per_block\n\n if cutlass.const_expr(self.needs_col_loop):\n # Large K path: single row per block iteration with column loop\n # Each thread maps to one SF block; threads stride over columns\n num_threads = self.num_threads\n\n row_idx = bidx\n while row_idx < padded_M:\n is_padding_row = row_idx >= M\n\n if is_padding_row:\n # Fast path: padding row - only zero out scale factors\n sf_col_idx = tidx\n while sf_col_idx < padded_sf_cols:\n sf_offset = self._compute_sf_offset(\n row_idx, sf_col_idx, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n sf_col_idx = sf_col_idx + num_threads\n else:\n # Normal path: process actual data row with column loop\n sf_col_idx = tidx\n while sf_col_idx < num_sf_blocks_per_row:\n elem_base = sf_col_idx * NVFP4_SF_VEC_SIZE\n row_input = mInput[row_idx, None]\n\n # Apply optional SwiGLU and quantize the block.\n scale_fp8, packed64 = self._process_block(\n row_input, elem_base, global_scale_value, row_amax\n )\n\n # Write scale factor using swizzled indexing\n sf_offset = self._compute_sf_offset(\n row_idx, sf_col_idx, padded_sf_cols\n )\n mScales[sf_offset] = scale_fp8\n\n # Store 8 bytes (16 FP4 values = 1 x st.global.u64)\n row_output = mOutput[row_idx, None]\n out_base = sf_col_idx * (NVFP4_SF_VEC_SIZE // 2)\n out_ptr = get_ptr_as_int64(row_output, out_base)\n st_global_u64(out_ptr, packed64)\n\n sf_col_idx = sf_col_idx + num_threads\n\n # Handle padding columns for this row\n sf_col_idx = num_sf_blocks_per_row + tidx\n while sf_col_idx < padded_sf_cols:\n sf_offset = self._compute_sf_offset(\n row_idx, sf_col_idx, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n sf_col_idx = sf_col_idx + num_threads\n\n row_idx = row_idx + grid_dim_x\n else:\n # Small K path: multi-row processing\n # Thread mapping: tidx -> (row_in_block, sf_idx_in_row)\n row_in_block = tidx // threads_per_row\n sf_idx_in_row = tidx % threads_per_row\n\n # Grid-stride loop over row batches\n row_batch_idx = bidx\n # Initialize row_idx before while loop (CuTe DSL requires variables\n # modified in while loops to be defined before the loop)\n row_idx = row_batch_idx * rows_per_block + row_in_block\n while row_batch_idx * rows_per_block < padded_M:\n if row_idx < padded_M:\n is_padding_row = row_idx >= M\n\n if is_padding_row:\n # Fast path: padding row - zero out ALL padded_sf_cols\n # Thread-stride loop since padded_sf_cols may exceed\n # threads_per_row (e.g. K=32: threads_per_row=2,\n # padded_sf_cols=4)\n local_sf_idx = sf_idx_in_row\n while local_sf_idx < padded_sf_cols:\n sf_offset = self._compute_sf_offset(\n row_idx, local_sf_idx, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n local_sf_idx = local_sf_idx + threads_per_row\n else:\n # Normal path: process actual data\n if sf_idx_in_row < num_sf_blocks_per_row:\n elem_base = sf_idx_in_row * NVFP4_SF_VEC_SIZE\n row_input = mInput[row_idx, None]\n\n # Apply optional SwiGLU and quantize the block.\n scale_fp8, packed64 = self._process_block(\n row_input, elem_base, global_scale_value, row_amax\n )\n\n # Write scale factor using swizzled indexing\n sf_offset = self._compute_sf_offset(\n row_idx, sf_idx_in_row, padded_sf_cols\n )\n mScales[sf_offset] = scale_fp8\n\n # Store 8 bytes (16 FP4 values = 1 x st.global.u64)\n row_output = mOutput[row_idx, None]\n out_base = sf_idx_in_row * (NVFP4_SF_VEC_SIZE // 2)\n out_ptr = get_ptr_as_int64(row_output, out_base)\n st_global_u64(out_ptr, packed64)\n\n # Handle padding SF columns for this row\n # Thread-stride loop starting from first padding column\n if cutlass.const_expr(\n self.num_sf_blocks_per_row != self.padded_sf_cols\n ):\n pad_col = num_sf_blocks_per_row + sf_idx_in_row\n while pad_col < padded_sf_cols:\n sf_offset = self._compute_sf_offset(\n row_idx, pad_col, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n pad_col = pad_col + threads_per_row\n\n row_batch_idx = row_batch_idx + grid_dim_x\n # Update row_idx for next iteration\n row_idx = row_batch_idx * rows_per_block + row_in_block\n\n # PDL: Signal that dependent kernels can start early\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_launch_dependents()\n\n\n# =============================================================================\n# CuTe-DSL Kernel Class for Per-Token Activation Quantization\n# =============================================================================\n\n\n_PER_TOKEN_THREADS = 128\n_PER_TOKEN_WARPS = _PER_TOKEN_THREADS // WARP_SIZE\n\n\nclass NVFP4QuantizePerTokenKernel:\n \"\"\"\n One CTA per token row. The first pass reduces the row amax, then the\n second pass reuses the regular NVFP4 block quantizer with that row's\n global encode scale.\n \"\"\"\n\n def __init__(\n self,\n dtype: cutlass.Numeric,\n K: int,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool = False,\n disable_fp4_quant_fast_math: bool = False,\n nvfp4_4over6_config: NVFP44Over6Config | None = None,\n ):\n self.dtype = dtype\n self.K = K\n self.is_bfloat16 = dtype == cutlass.BFloat16\n self.enable_pdl = enable_pdl\n self.disable_fp4_quant_fast_math = disable_fp4_quant_fast_math\n self.nvfp4_4over6_config = nvfp4_4over6_config\n self.sf_layout = sf_layout\n self.sf_is_128x4 = sf_layout == SF_LAYOUT_128x4\n self.sf_is_8x4 = sf_layout == SF_LAYOUT_8x4\n\n assert dtype != cutlass.Float8E4M3FN, (\n \"per-token NVFP4 does not support FP8 input\"\n )\n assert K % NVFP4_SF_VEC_SIZE == 0\n self.num_sf_blocks_per_row = K // NVFP4_SF_VEC_SIZE\n if sf_layout == SF_LAYOUT_LINEAR:\n self.padded_sf_cols = self.num_sf_blocks_per_row\n else:\n self.padded_sf_cols = ((self.num_sf_blocks_per_row + 3) // 4) * 4\n\n @cute.jit\n def _compute_sf_offset(\n self, row_idx: Int32, col_idx: Int32, padded_cols: Int32\n ) -> Int32:\n if cutlass.const_expr(self.sf_is_128x4):\n return compute_sf_index_swizzled_128x4_gpu(row_idx, col_idx, padded_cols)\n else:\n if cutlass.const_expr(self.sf_is_8x4):\n return compute_sf_index_swizzled_8x4_gpu(row_idx, col_idx, padded_cols)\n else:\n return compute_sf_index_linear_gpu(row_idx, col_idx, padded_cols)\n\n @cute.jit\n def _row_scales(\n self, row_amax: Float32, global_scale_inv: Float32\n ) -> Tuple[Float32, Float32]:\n global_encode_scale = Float32(0.0)\n per_token_scale = Float32(0.0)\n if cutlass.const_expr(self.disable_fp4_quant_fast_math):\n global_scale = fdiv_rn(Float32(1.0), global_scale_inv)\n if row_amax == Float32(0.0):\n per_token_scale = Float32(0.0)\n if cutlass.const_expr(self.nvfp4_4over6_config is not None):\n global_encode_scale = Float32(0.0)\n else:\n global_encode_scale = Float32(FLOAT32_MAX)\n else:\n row_encode_scale = fmin_f32(\n fdiv_rn(global_scale, row_amax), Float32(FLOAT32_MAX)\n )\n if row_encode_scale != Float32(0.0):\n global_encode_scale = row_encode_scale\n else:\n global_encode_scale = Float32(1.0)\n per_token_scale = fdiv_rn(Float32(1.0), global_encode_scale)\n else:\n if row_amax == Float32(0.0):\n per_token_scale = Float32(0.0)\n if cutlass.const_expr(self.nvfp4_4over6_config is not None):\n global_encode_scale = Float32(0.0)\n else:\n global_encode_scale = Float32(FLOAT32_MAX)\n else:\n per_token_scale = row_amax * global_scale_inv\n global_encode_scale = rcp_approx_ftz(per_token_scale)\n return global_encode_scale, per_token_scale\n\n @cute.jit\n def __call__(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n mPerTokenScale: cute.Tensor,\n M: Int32,\n mGlobalScaleInv: cute.Tensor,\n stream,\n ):\n self.kernel(\n mInput, mOutput, mScales, mPerTokenScale, M, mGlobalScaleInv\n ).launch(\n grid=[M, 1, 1],\n block=[_PER_TOKEN_THREADS, 1, 1],\n max_number_threads=[_MAX_THREADS_PER_BLOCK, 1, 1],\n min_blocks_per_mp=_BLOCKS_PER_SM,\n stream=stream,\n use_pdl=self.enable_pdl,\n )\n\n @cute.kernel\n def kernel(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n mPerTokenScale: cute.Tensor,\n M: Int32,\n mGlobalScaleInv: cute.Tensor,\n ):\n tidx, _, _ = cute.arch.thread_idx()\n bidx, _, _ = cute.arch.block_idx()\n\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_wait()\n\n smem = cutlass.utils.SmemAllocator()\n reduction_buffer = smem.allocate_tensor(\n Float32,\n cute.make_layout((1, _PER_TOKEN_WARPS)),\n byte_alignment=4,\n )\n\n row_idx = bidx\n num_sf_blocks_per_row = self.num_sf_blocks_per_row\n padded_sf_cols = self.padded_sf_cols\n # Build the row views from 64-bit byte addresses. Slicing with\n # mInput[row_idx, None] computes the row offset row_idx * K in\n # Int32, which wraps once row_idx * K exceeds 2**31 - 1 (reached by\n # the MoE per-token intermediate, e.g. M=851456 x K=2688) and makes\n # the loads fault.\n input_row_addr = get_ptr_as_int64(mInput, Int32(0)) + Int64(row_idx) * Int64(\n self.K * (mInput.element_type.width // 8)\n )\n row_input = cute.make_tensor(\n cute.make_ptr(\n mInput.element_type,\n input_row_addr,\n cute.AddressSpace.gmem,\n assumed_align=16,\n ),\n cute.make_layout((self.K,)),\n )\n output_row_addr = get_ptr_as_int64(mOutput, Int32(0)) + Int64(row_idx) * Int64(\n self.K // 2\n )\n row_output = cute.make_tensor(\n cute.make_ptr(\n mOutput.element_type,\n output_row_addr,\n cute.AddressSpace.gmem,\n assumed_align=8,\n ),\n cute.make_layout((self.K // 2,)),\n )\n\n local_amax = Float32(0.0)\n sf_col_idx = tidx\n while sf_col_idx < num_sf_blocks_per_row:\n elem_base = sf_col_idx * NVFP4_SF_VEC_SIZE\n ptr0 = get_ptr_as_int64(row_input, elem_base)\n ptr1 = get_ptr_as_int64(row_input, elem_base + Int32(8))\n h0, h1, h2, h3 = ld_global_v4_u32(ptr0)\n h4, h5, h6, h7 = ld_global_v4_u32(ptr1)\n if cutlass.const_expr(self.is_bfloat16):\n block_max_h2 = bfloat2_max_abs_8_fn(h0, h1, h2, h3, h4, h5, h6, h7)\n block_max = bfloat2_hmax_reduce_to_f32(block_max_h2)\n else:\n block_max_h2 = half2_max_abs_8_fn(h0, h1, h2, h3, h4, h5, h6, h7)\n block_max = hmax_reduce_to_f32(block_max_h2)\n local_amax = fmax_f32(local_amax, block_max)\n sf_col_idx = sf_col_idx + Int32(_PER_TOKEN_THREADS)\n\n warp_amax = warp_reduce(local_amax, fmax_f32)\n row_amax = block_reduce(warp_amax, fmax_f32, reduction_buffer, Float32(0.0))\n global_scale_inv = Float32(mGlobalScaleInv[Int32(0)])\n global_encode_scale, per_token_scale = self._row_scales(\n row_amax, global_scale_inv\n )\n if tidx == Int32(0):\n mPerTokenScale[row_idx] = per_token_scale\n cute.arch.barrier()\n\n sf_col_idx = tidx\n while sf_col_idx < num_sf_blocks_per_row:\n elem_base = sf_col_idx * NVFP4_SF_VEC_SIZE\n if cutlass.const_expr(self.is_bfloat16):\n scale_fp8, packed64 = process_nvfp4_block_bfloat(\n row_input,\n elem_base,\n global_encode_scale,\n self.disable_fp4_quant_fast_math,\n self.nvfp4_4over6_config,\n row_amax,\n )\n else:\n scale_fp8, packed64 = process_nvfp4_block_half(\n row_input,\n elem_base,\n global_encode_scale,\n self.disable_fp4_quant_fast_math,\n self.nvfp4_4over6_config,\n row_amax,\n )\n\n sf_offset = self._compute_sf_offset(row_idx, sf_col_idx, padded_sf_cols)\n mScales[sf_offset] = scale_fp8\n\n out_base = sf_col_idx * Int32(NVFP4_SF_VEC_SIZE // 2)\n out_ptr = get_ptr_as_int64(row_output, out_base)\n st_global_u64(out_ptr, packed64)\n\n sf_col_idx = sf_col_idx + Int32(_PER_TOKEN_THREADS)\n\n if cutlass.const_expr(self.sf_layout != SF_LAYOUT_LINEAR):\n sf_col_idx = num_sf_blocks_per_row + tidx\n while sf_col_idx < padded_sf_cols:\n sf_offset = self._compute_sf_offset(row_idx, sf_col_idx, padded_sf_cols)\n mScales[sf_offset] = Uint8(0)\n sf_col_idx = sf_col_idx + Int32(_PER_TOKEN_THREADS)\n\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_launch_dependents()\n\n\n# =============================================================================\n# CuTe-DSL TMA Kernel Class for NVFP4\n# =============================================================================\n\n_TMA_ROW_TILE = 16\n_TMA_COL_TILE = 64 # Per-warp column tile\n_TMA_NUM_CONSUMER_WARPS = 8\n_TMA_NUM_STAGES = 4\n_TMA_COLS_PER_STAGE = _TMA_NUM_CONSUMER_WARPS * _TMA_COL_TILE # 512\n\n\ndef _round_up(x: int, d: int) -> int:\n return ((x + d - 1) // d) * d\n\n\nclass NVFP4QuantizeTMAKernel:\n \"\"\"\n TMA-based NVFP4 quantization kernel with pipelined producer-consumer\n warp specialization, matching the CUDA TMA kernel architecture.\n\n Architecture (matches csrc/nv_internal/.../quantization.cuh):\n - 1 producer warp (warp 0) issues TMA G2S loads into staged SMEM buffers\n - 8 consumer warps (warps 1-8) read from SMEM, quantize, write to GMEM\n - PipelineTmaAsync manages multi-stage buffering (4 stages)\n - Each TMA tile: [16, 512] = 16 rows x 8 warps x 64 cols per warp\n - Each consumer warp: 4 threads/row x 8 rows/warp, 2 row iterations\n - Each thread: 16 elements (1 SF block) via 2 x ld.shared.v4.u32\n - Grid-stride loop over row tiles, inner loop over K/512 col chunks\n\n Effective when M >= 1024 and K is a multiple of 512.\n \"\"\"\n\n def __init__(\n self,\n dtype: cutlass.Numeric,\n K: int,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool = False,\n disable_fp4_quant_fast_math: bool = False,\n ):\n self.dtype = dtype\n self.K = K\n self.is_bfloat16 = dtype == cutlass.BFloat16\n self.is_fp8 = dtype == cutlass.Float8E4M3FN\n self.enable_pdl = enable_pdl\n self.disable_fp4_quant_fast_math = disable_fp4_quant_fast_math\n self.sf_layout = sf_layout\n self.sf_is_128x4 = sf_layout == SF_LAYOUT_128x4\n self.sf_is_8x4 = sf_layout == SF_LAYOUT_8x4\n\n assert not self.is_fp8, \"FP8 input not yet supported for TMA kernel\"\n assert K % _TMA_COLS_PER_STAGE == 0, (\n f\"K ({K}) must be a multiple of {_TMA_COLS_PER_STAGE} for TMA kernel\"\n )\n\n self.num_sf_blocks_per_row = K // NVFP4_SF_VEC_SIZE\n self.num_col_chunks = K // _TMA_COLS_PER_STAGE\n\n if sf_layout == SF_LAYOUT_LINEAR:\n self.padded_sf_cols = self.num_sf_blocks_per_row\n elif sf_layout == SF_LAYOUT_8x4:\n self.padded_sf_cols = ((self.num_sf_blocks_per_row + 3) // 4) * 4\n else:\n self.padded_sf_cols = ((self.num_sf_blocks_per_row + 3) // 4) * 4\n\n self.num_consumer_warps = _TMA_NUM_CONSUMER_WARPS # 8\n self.num_stages = _TMA_NUM_STAGES\n self.producer_warp_id = 0 # Warp 0 is producer (matches CUDA kernel)\n self.threads_per_cta = 32 * (self.num_consumer_warps + 1) # 288\n self.rows_per_block = _TMA_ROW_TILE\n self.buffer_align_bytes = 1024\n self.cluster_shape_mn = (1, 1)\n self.elems_per_stage = _TMA_ROW_TILE * _TMA_COLS_PER_STAGE # 8192\n\n # Thread indexing constants (matches CUDA TmaKernelTraitsTwoBytes)\n self.THREADS_PER_ROW = 4 # laneIdx % 4\n self.ROWS_PER_WARP = 8 # 32 / 4\n self.ELTS_PER_THREAD = NVFP4_SF_VEC_SIZE # 16\n\n @cute.jit\n def _compute_sf_offset(\n self, row_idx: Int32, col_idx: Int32, padded_cols: Int32\n ) -> Int32:\n if cutlass.const_expr(self.sf_is_128x4):\n return compute_sf_index_swizzled_128x4_gpu(row_idx, col_idx, padded_cols)\n else:\n if cutlass.const_expr(self.sf_is_8x4):\n return compute_sf_index_swizzled_8x4_gpu(row_idx, col_idx, padded_cols)\n else:\n return compute_sf_index_linear_gpu(row_idx, col_idx, padded_cols)\n\n @cute.jit\n def _quantize_sf_block(\n self,\n h0: cutlass.Uint32,\n h1: cutlass.Uint32,\n h2: cutlass.Uint32,\n h3: cutlass.Uint32,\n h4: cutlass.Uint32,\n h5: cutlass.Uint32,\n h6: cutlass.Uint32,\n h7: cutlass.Uint32,\n global_row: Int32,\n sf_col: Int32,\n global_scale: Float32,\n M: Int32,\n padded_M: Int32,\n padded_sf_cols: Int32,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n ):\n \"\"\"Quantize one 16-element SF block and write results to GMEM.\"\"\"\n from ...cute_dsl.fp4_common import (\n cvt_f32_to_e4m3,\n nvfp4_compute_output_scale,\n nvfp4_compute_output_scale_rn,\n nvfp4_scale_from_amax_rn,\n rcp_approx_ftz,\n )\n\n if global_row < padded_M:\n is_padding_row = global_row >= M\n\n if is_padding_row:\n sf_offset = self._compute_sf_offset(global_row, sf_col, padded_sf_cols)\n mScales[sf_offset] = Uint8(0)\n else:\n if cutlass.const_expr(self.is_bfloat16):\n block_max_h2 = bfloat2_max_abs_8_fn(h0, h1, h2, h3, h4, h5, h6, h7)\n block_max = bfloat2_hmax_reduce_to_f32(block_max_h2)\n else:\n block_max_h2 = half2_max_abs_8_fn(h0, h1, h2, h3, h4, h5, h6, h7)\n block_max = hmax_reduce_to_f32(block_max_h2)\n\n if cutlass.const_expr(self.disable_fp4_quant_fast_math):\n scale_float = nvfp4_scale_from_amax_rn(block_max, global_scale)\n else:\n fp4_max_rcp = rcp_approx_ftz(Float32(6.0))\n scale_float = global_scale * (block_max * fp4_max_rcp)\n scale_fp8_u32 = cvt_f32_to_e4m3(scale_float)\n scale_fp8 = Uint8(scale_fp8_u32 & cutlass.Uint32(0xFF))\n\n if cutlass.const_expr(self.disable_fp4_quant_fast_math):\n output_scale = nvfp4_compute_output_scale_rn(\n scale_fp8_u32, global_scale, block_max\n )\n else:\n output_scale = nvfp4_compute_output_scale(\n scale_fp8_u32, global_scale\n )\n\n if cutlass.const_expr(self.is_bfloat16):\n packed64 = bfloat2x8_to_e2m1x16_packed(\n h0, h1, h2, h3, h4, h5, h6, h7, output_scale\n )\n else:\n packed64 = half2x8_to_e2m1x16_packed(\n h0, h1, h2, h3, h4, h5, h6, h7, output_scale\n )\n\n sf_offset = self._compute_sf_offset(global_row, sf_col, padded_sf_cols)\n mScales[sf_offset] = scale_fp8\n\n row_output = mOutput[global_row, None]\n out_base = sf_col * Int32(NVFP4_SF_VEC_SIZE // 2)\n out_ptr = get_ptr_as_int64(row_output, out_base)\n st_global_u64(out_ptr, packed64)\n\n @cute.jit\n def __call__(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n M: Int32,\n padded_M: Int32,\n num_blocks: Int32,\n global_scale: Union[Float32, cute.Tensor],\n stream,\n ):\n # 3D global tensor: [padded_M, K/64, 64] so each warp's 64-col\n # stripe is the contiguous innermost dimension, matching the CUDA\n # TMA kernel's 3D tensor map.\n gInput = cute.make_tensor(\n mInput.iterator,\n cute.make_layout(\n (padded_M, self.K // _TMA_COL_TILE, _TMA_COL_TILE),\n stride=(self.K, _TMA_COL_TILE, 1),\n ),\n )\n\n # SMEM layout per stage: [rows=16, warps=8, cols_per_warp=64]\n # with SWIZZLE_128B applied. Within each warp's [16, 64] tile the\n # row stride is 64 elems = 128 bytes, putting row bits in the S=3\n # range of the swizzle so different rows map to different banks.\n smem_swizzle = cute.make_swizzle(3, 4, 3) # SWIZZLE_128B for 2B types\n smem_outer_single = cute.make_layout(\n (_TMA_ROW_TILE, _TMA_NUM_CONSUMER_WARPS, _TMA_COL_TILE),\n stride=(_TMA_COL_TILE, _TMA_ROW_TILE * _TMA_COL_TILE, 1),\n )\n smem_single_composed = cute.make_composed_layout(\n smem_swizzle, 0, smem_outer_single\n )\n\n cta_tiler = (_TMA_ROW_TILE, _TMA_NUM_CONSUMER_WARPS, _TMA_COL_TILE)\n tma_atom, tma_tensor = cpasync.make_tiled_tma_atom(\n cpasync.CopyBulkTensorTileG2SOp(),\n gInput,\n smem_single_composed,\n cta_tiler,\n )\n\n total_smem_elems = self.elems_per_stage * self.num_stages\n # Staged outer layout (no swizzle — swizzle passed separately)\n smem_outer_staged = cute.make_layout(\n (_TMA_ROW_TILE, _TMA_NUM_CONSUMER_WARPS, _TMA_COL_TILE, self.num_stages),\n stride=(\n _TMA_COL_TILE,\n _TMA_ROW_TILE * _TMA_COL_TILE,\n 1,\n self.elems_per_stage,\n ),\n )\n # Flat layout for manual-swizzle consumer reads\n smem_layout_flat = cute.make_layout((total_smem_elems,))\n\n self.num_tma_load_bytes = cute.size_in_bytes(self.dtype, smem_outer_single)\n\n @cute.struct\n class SharedStorage:\n load_full_mbar: cute.struct.MemRange[cutlass.Int64, self.num_stages]\n load_empty_mbar: cute.struct.MemRange[cutlass.Int64, self.num_stages]\n smem_data: cute.struct.Align[\n cute.struct.MemRange[self.dtype, total_smem_elems],\n self.buffer_align_bytes,\n ]\n\n self.shared_storage = SharedStorage\n\n self.kernel(\n tma_atom,\n tma_tensor,\n mOutput,\n mScales,\n M,\n padded_M,\n global_scale,\n smem_outer_staged,\n smem_swizzle,\n smem_layout_flat,\n ).launch(\n grid=[num_blocks, 1, 1],\n block=[self.threads_per_cta, 1, 1],\n max_number_threads=[\n self.threads_per_cta,\n 1,\n 1,\n ], # __launch_bounds__(288, 2)\n min_blocks_per_mp=2,\n cluster=(*self.cluster_shape_mn, 1),\n stream=stream,\n use_pdl=self.enable_pdl,\n )\n\n @cute.kernel\n def kernel(\n self,\n tma_atom: cute.CopyAtom,\n gInput_tma: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n M: Int32,\n padded_M: Int32,\n global_scale: Union[Float32, cute.Tensor],\n smem_outer_staged: cute.Layout,\n smem_swizzle: cute.Swizzle,\n smem_layout_flat: cute.Layout,\n ):\n from ...cute_dsl.fp4_common import (\n get_smem_ptr_as_int32,\n ld_shared_v4_u32,\n )\n\n tidx, _, _ = cute.arch.thread_idx()\n bidx, _, _ = cute.arch.block_idx()\n grid_dim_x, _, _ = cute.arch.grid_dim()\n\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_wait()\n\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n lane_idx = tidx % 32\n\n # Device scales stay pointer-loaded; host scales arrive as launch arguments.\n if cutlass.const_expr(isinstance(global_scale, cute.Tensor)):\n global_scale_value = Float32(global_scale[Int32(0)])\n else:\n global_scale_value = global_scale\n padded_sf_cols = self.padded_sf_cols\n num_sf_blocks_per_row = self.num_sf_blocks_per_row\n num_col_chunks = self.num_col_chunks\n elems_per_stage = self.elems_per_stage\n\n # ---- SMEM allocation ----\n smem = cutlass.utils.SmemAllocator()\n storage = smem.allocate(self.shared_storage)\n\n load_mbar_ptr = storage.load_full_mbar.data_ptr()\n # Swizzled tensor for TMA partition (address-space-correct writes)\n sData_staged = storage.smem_data.get_tensor(\n smem_outer_staged, swizzle=smem_swizzle\n )\n # Flat tensor for manual-swizzle consumer reads\n sData_flat = storage.smem_data.get_tensor(smem_layout_flat)\n\n # ---- Pipeline setup ----\n load_pipeline = pipeline.PipelineTmaAsync.create(\n barrier_storage=load_mbar_ptr,\n num_stages=self.num_stages,\n producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread, 1),\n consumer_group=pipeline.CooperativeGroup(\n pipeline.Agent.Thread, self.num_consumer_warps\n ),\n tx_count=self.num_tma_load_bytes,\n cta_layout_vmnk=cute.tiled_divide(\n cute.make_layout((*self.cluster_shape_mn, 1)), (1,)\n ),\n defer_sync=True,\n )\n\n pipeline_init_arrive(cluster_shape_mn=self.cluster_shape_mn, is_relaxed=True)\n pipeline_init_wait(cluster_shape_mn=self.cluster_shape_mn)\n\n # ---- TMA partition (3D: rows x warps x cols_per_warp) ----\n gSrc_tiled = cute.local_tile(\n gInput_tma,\n (_TMA_ROW_TILE, _TMA_NUM_CONSUMER_WARPS, _TMA_COL_TILE),\n (None, None, None),\n )\n tAsA, tAgA = cpasync.tma_partition(\n tma_atom,\n 0,\n cute.make_layout(1),\n cute.group_modes(sData_staged, 0, 3), # Group 3 tile modes\n cute.group_modes(gSrc_tiled, 0, 3),\n )\n\n num_row_tiles = cute.ceil_div(padded_M, _TMA_ROW_TILE)\n\n # ---- Consumer thread indexing (matches CUDA TmaKernelTraitsTwoBytes) ----\n # 4 threads per row, 8 rows per warp, 2 row iterations per stage\n col_idx_local = lane_idx % Int32(self.THREADS_PER_ROW)\n row_idx_local = lane_idx // Int32(self.THREADS_PER_ROW)\n\n # ======== Producer warp (warp 0) ========\n if warp_idx == self.producer_warp_id:\n producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.num_stages\n )\n\n row_tile_idx = bidx\n while row_tile_idx < num_row_tiles:\n col_chunk = Int32(0)\n while col_chunk < num_col_chunks:\n load_pipeline.producer_acquire(producer_state)\n\n cute.copy(\n tma_atom,\n tAgA[(None, row_tile_idx, col_chunk, 0)],\n tAsA[(None, producer_state.index)],\n tma_bar_ptr=load_pipeline.producer_get_barrier(producer_state),\n )\n\n producer_state.advance()\n col_chunk = col_chunk + Int32(1)\n\n row_tile_idx = row_tile_idx + grid_dim_x\n\n load_pipeline.producer_tail(producer_state)\n\n # ======== Consumer warps (warps 1-8) ========\n if warp_idx > 0:\n consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.num_stages\n )\n\n # 0-indexed consumer warp id\n consumer_warp_idx = warp_idx - Int32(1)\n\n # Pre-compute warp tile base offset (constant per warp)\n # SMEM 3D layout: [rows=16, warps=8, cols=64] per stage\n # stride: [64, 1024, 1] → warp tile base = warp * 1024\n warp_tile_elems = _TMA_ROW_TILE * _TMA_COL_TILE # 1024\n warp_tile_base = consumer_warp_idx * Int32(warp_tile_elems)\n\n # Float4 base position for this thread (0, 2, 4, 6)\n f4_base = col_idx_local * Int32(2)\n\n # Global column offset for SF index: warp's column within K\n base_col_in_stage = consumer_warp_idx * Int32(\n _TMA_COL_TILE\n ) + col_idx_local * Int32(self.ELTS_PER_THREAD)\n\n row_tile_idx = bidx\n while row_tile_idx < num_row_tiles:\n base_row = row_tile_idx * Int32(_TMA_ROW_TILE)\n\n col_chunk = Int32(0)\n while col_chunk < num_col_chunks:\n load_pipeline.consumer_wait(consumer_state)\n stage = consumer_state.index\n\n # ---- Read ALL SMEM data with SWIZZLE_128B addressing ----\n # Within each warp's [16,64] tile, the XOR pattern matches\n # CUDA's load_input_vec: float4_idx ^= row & 7\n # Physical elem offset in warp tile for (row, float4 f):\n # row * 64 + (f ^ (row & 7)) * 8\n stage_base = stage * Int32(elems_per_stage)\n\n # Row iteration 0 (row_idx_local = 0..7)\n r0_xor = row_idx_local & Int32(7)\n r0_f4_0 = f4_base ^ r0_xor\n r0_f4_1 = (f4_base + Int32(1)) ^ r0_xor\n r0_row_base = (\n stage_base\n + warp_tile_base\n + row_idx_local * Int32(_TMA_COL_TILE)\n )\n r0_addr_0 = get_smem_ptr_as_int32(\n sData_flat, r0_row_base + r0_f4_0 * Int32(8)\n )\n r0_addr_1 = get_smem_ptr_as_int32(\n sData_flat, r0_row_base + r0_f4_1 * Int32(8)\n )\n r0_h0, r0_h1, r0_h2, r0_h3 = ld_shared_v4_u32(r0_addr_0)\n r0_h4, r0_h5, r0_h6, r0_h7 = ld_shared_v4_u32(r0_addr_1)\n\n # Row iteration 1 (row = row_idx_local + 8)\n r1_row = row_idx_local + Int32(self.ROWS_PER_WARP)\n r1_xor = r1_row & Int32(7)\n r1_f4_0 = f4_base ^ r1_xor\n r1_f4_1 = (f4_base + Int32(1)) ^ r1_xor\n r1_row_base = (\n stage_base + warp_tile_base + r1_row * Int32(_TMA_COL_TILE)\n )\n r1_addr_0 = get_smem_ptr_as_int32(\n sData_flat, r1_row_base + r1_f4_0 * Int32(8)\n )\n r1_addr_1 = get_smem_ptr_as_int32(\n sData_flat, r1_row_base + r1_f4_1 * Int32(8)\n )\n r1_h0, r1_h1, r1_h2, r1_h3 = ld_shared_v4_u32(r1_addr_0)\n r1_h4, r1_h5, r1_h6, r1_h7 = ld_shared_v4_u32(r1_addr_1)\n\n # ---- Quantize and write: both row iterations ----\n # Global column base for SF index computation\n global_col_base = col_chunk * Int32(_TMA_COLS_PER_STAGE)\n sf_col = (global_col_base + base_col_in_stage) // Int32(\n NVFP4_SF_VEC_SIZE\n )\n\n # Row iteration 0\n global_row_0 = base_row + row_idx_local\n self._quantize_sf_block(\n r0_h0,\n r0_h1,\n r0_h2,\n r0_h3,\n r0_h4,\n r0_h5,\n r0_h6,\n r0_h7,\n global_row_0,\n sf_col,\n global_scale_value,\n M,\n padded_M,\n padded_sf_cols,\n mOutput,\n mScales,\n )\n\n # Row iteration 1\n global_row_1 = base_row + row_idx_local + Int32(self.ROWS_PER_WARP)\n self._quantize_sf_block(\n r1_h0,\n r1_h1,\n r1_h2,\n r1_h3,\n r1_h4,\n r1_h5,\n r1_h6,\n r1_h7,\n global_row_1,\n sf_col,\n global_scale_value,\n M,\n padded_M,\n padded_sf_cols,\n mOutput,\n mScales,\n )\n\n # ---- Release pipeline after all work (matches CUDA pattern) ----\n load_pipeline.consumer_release(consumer_state)\n consumer_state.advance()\n\n col_chunk = col_chunk + Int32(1)\n\n # Zero padding SF columns for swizzled layouts\n if cutlass.const_expr(self.sf_layout != SF_LAYOUT_LINEAR):\n consumer_tid = (warp_idx - Int32(1)) * Int32(32) + lane_idx\n if consumer_tid < _TMA_ROW_TILE:\n pad_row_idx = base_row + consumer_tid\n if pad_row_idx < padded_M:\n padding_sf = Int32(num_sf_blocks_per_row)\n while padding_sf < padded_sf_cols:\n sf_offset = self._compute_sf_offset(\n pad_row_idx, padding_sf, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n padding_sf = padding_sf + Int32(1)\n\n row_tile_idx = row_tile_idx + grid_dim_x\n\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_launch_dependents()\n\n\n# =============================================================================\n# PyTorch Integration with TVM-FFI\n# =============================================================================\n\n\ndef _kernel_source_files() -> Tuple[str, ...]:\n \"\"\"Source files whose content invalidates the on-disk kernel cache.\"\"\"\n from ...cute_dsl import fp4_common\n from .. import quantization_cute_dsl_utils\n\n return (__file__, fp4_common.__file__, quantization_cute_dsl_utils.__file__)\n\n\n_CUTE_DSL_MODULE = \"nvfp4_quantize\"\n\n\ndef _nvfp4_kernel_name(\n variant: str,\n dtype_key: str,\n K: int,\n sf_layout: int,\n enable_pdl: bool,\n disable_fp4_quant_fast_math: bool,\n silu_and_mul: bool,\n nvfp4_4over6_config: NVFP44Over6Config | None = None,\n global_scale_is_tensor: bool = True,\n) -> str:\n \"\"\"Specialization name within the nvfp4_quantize module, encoding every\n parameter that affects codegen.\n \"\"\"\n name = f\"{variant}_{dtype_key}_k{K}_sf{sf_layout}_pdl{int(enable_pdl)}\"\n if not global_scale_is_tensor:\n name += \"_host_sf\"\n if silu_and_mul:\n name += \"_silu\"\n if disable_fp4_quant_fast_math:\n name += \"_nofastmath\"\n if nvfp4_4over6_config is not None:\n cfg = nvfp4_4over6_config\n err_mode = getattr(cfg.err_mode, \"name\", cfg.err_mode)\n name += f\"_4over6_{cfg.e4m3_max}_{err_mode}_{int(cfg.err_use_fast_math)}\"\n return name\n\n\n@functools.cache\ndef _get_compiled_kernel_nvfp4(\n dtype_key: str,\n K: int,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool = False,\n disable_fp4_quant_fast_math: bool = False,\n nvfp4_4over6_config: NVFP44Over6Config | None = None,\n silu_and_mul: bool = False,\n global_scale_is_tensor: bool = True,\n) -> Tuple[Callable, int]:\n \"\"\"\n Get or compile NVFP4 kernel with TVM-FFI.\n\n Cached by (K, dtype_key, sf_layout, pdl, silu_and_mul,\n global_scale_is_tensor) - M-agnostic, device-independent compilation.\n\n Args:\n dtype_key: One of \"float16\", \"bfloat16\", \"float8_e4m3fn\".\n silu_and_mul: When True, fuse silu(gate) * up; the input row is 2 * K\n wide (gate then up concatenated) while the output stays K wide.\n global_scale_is_tensor: Whether the global scale is passed as a device\n tensor or a host-side scalar kernel argument.\n\n Returns:\n For linear layout: (compiled_kernel, sf_blocks_per_tb)\n For swizzled layout: (compiled_kernel, rows_per_block)\n \"\"\"\n _dtype_map = {\n \"float16\": cutlass.Float16,\n \"bfloat16\": cutlass.BFloat16,\n \"float8_e4m3fn\": cutlass.Float8E4M3FN,\n }\n cutlass_dtype = _dtype_map[dtype_key]\n\n # Use symbolic M for dynamic batch sizes\n sym_m = cute.sym_int()\n sym_scale_size = cute.sym_int()\n\n # Fused inputs have 2*K columns; outputs remain K-wide.\n input_cols = 2 * K if silu_and_mul else K\n\n # Common fake tensors\n input_fake = cute.runtime.make_fake_compact_tensor(\n cutlass_dtype, (sym_m, input_cols), stride_order=(1, 0), assumed_align=16\n )\n output_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_m, K // 2), stride_order=(1, 0), assumed_align=16\n )\n scales_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_scale_size,), assumed_align=16\n )\n global_scale_fake = (\n cute.runtime.make_fake_compact_tensor(cutlass.Float32, (1,), assumed_align=4)\n if global_scale_is_tensor\n else Float32(1.0)\n )\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n\n if sf_layout == SF_LAYOUT_LINEAR:\n linear_obj = NVFP4QuantizeLinearKernel(\n cutlass_dtype,\n K,\n enable_pdl,\n disable_fp4_quant_fast_math,\n nvfp4_4over6_config,\n silu_and_mul=silu_and_mul,\n )\n\n compiled_kernel = build_and_load_cute_dsl_kernel(\n _CUTE_DSL_MODULE,\n _nvfp4_kernel_name(\n \"linear\",\n dtype_key,\n K,\n sf_layout,\n enable_pdl,\n disable_fp4_quant_fast_math,\n silu_and_mul,\n nvfp4_4over6_config,\n global_scale_is_tensor,\n ),\n lambda: cute.compile(\n linear_obj,\n input_fake,\n output_fake,\n scales_fake,\n Int32(1), # Dummy M\n Int32(1), # Dummy total_sf_blocks\n Int32(1), # Dummy num_blocks\n global_scale_fake,\n stream_fake,\n options=\"--enable-tvm-ffi\",\n ),\n extra_key_files=_kernel_source_files(),\n )\n\n return compiled_kernel, linear_obj.SF_BLOCKS_PER_TB\n else:\n swizzled_obj = NVFP4QuantizeSwizzledKernel(\n cutlass_dtype,\n K,\n sf_layout=sf_layout,\n enable_pdl=enable_pdl,\n disable_fp4_quant_fast_math=disable_fp4_quant_fast_math,\n nvfp4_4over6_config=nvfp4_4over6_config,\n silu_and_mul=silu_and_mul,\n )\n\n compiled_kernel = build_and_load_cute_dsl_kernel(\n _CUTE_DSL_MODULE,\n _nvfp4_kernel_name(\n \"swizzled\",\n dtype_key,\n K,\n sf_layout,\n enable_pdl,\n disable_fp4_quant_fast_math,\n silu_and_mul,\n nvfp4_4over6_config,\n global_scale_is_tensor,\n ),\n lambda: cute.compile(\n swizzled_obj,\n input_fake,\n output_fake,\n scales_fake,\n Int32(1), # Dummy M\n Int32(128), # Dummy padded_M\n Int32(1), # Dummy num_blocks\n global_scale_fake,\n stream_fake,\n options=\"--enable-tvm-ffi\",\n ),\n extra_key_files=_kernel_source_files(),\n )\n\n return compiled_kernel, swizzled_obj.rows_per_block\n\n\n@functools.cache\ndef _get_compiled_kernel_nvfp4_per_token(\n dtype_key: str,\n K: int,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool = False,\n disable_fp4_quant_fast_math: bool = False,\n nvfp4_4over6_config: NVFP44Over6Config | None = None,\n) -> Callable:\n _dtype_map = {\n \"float16\": cutlass.Float16,\n \"bfloat16\": cutlass.BFloat16,\n }\n cutlass_dtype = _dtype_map[dtype_key]\n\n sym_m = cute.sym_int()\n sym_scale_size = cute.sym_int()\n\n input_fake = cute.runtime.make_fake_compact_tensor(\n cutlass_dtype, (sym_m, K), stride_order=(1, 0), assumed_align=16\n )\n output_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_m, K // 2), stride_order=(1, 0), assumed_align=16\n )\n scales_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_scale_size,), assumed_align=16\n )\n per_token_scale_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32, (sym_m,), assumed_align=4\n )\n global_scale_inv_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32, (1,), assumed_align=4\n )\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n\n kernel_obj = NVFP4QuantizePerTokenKernel(\n cutlass_dtype,\n K,\n sf_layout=sf_layout,\n enable_pdl=enable_pdl,\n disable_fp4_quant_fast_math=disable_fp4_quant_fast_math,\n nvfp4_4over6_config=nvfp4_4over6_config,\n )\n\n return build_and_load_cute_dsl_kernel(\n _CUTE_DSL_MODULE,\n _nvfp4_kernel_name(\n \"per_token\",\n dtype_key,\n K,\n sf_layout,\n enable_pdl,\n disable_fp4_quant_fast_math,\n silu_and_mul=False,\n nvfp4_4over6_config=nvfp4_4over6_config,\n ),\n lambda: cute.compile(\n kernel_obj,\n input_fake,\n output_fake,\n scales_fake,\n per_token_scale_fake,\n Int32(1),\n global_scale_inv_fake,\n stream_fake,\n options=\"--enable-tvm-ffi\",\n ),\n extra_key_files=_kernel_source_files(),\n )\n\n\n_TMA_MIN_M = 1024\n_TMA_LOG2_MK_THRESHOLD = 25\n\n\ndef _should_use_tma(m: int, k: int, dtype: torch.dtype) -> bool:\n \"\"\"TODO: disabled TMA for now due to perf sweep showing the vectorized-load\n kernel is as fast/at parity.\n\n Set ``FLASHINFER_NVFP4_QUANTIZE_USE_TMA=1`` to re-enable the heuristic for\n re-tuning on other hardware.\n \"\"\"\n if not _env_flag_enabled(\"FLASHINFER_NVFP4_QUANTIZE_USE_TMA\"):\n return False\n if dtype == torch.float8_e4m3fn:\n return False\n if k % _TMA_COLS_PER_STAGE != 0:\n return False\n if m < _TMA_MIN_M:\n return False\n # Use log2(M) + log2(K) threshold for the crossover point\n return m.bit_length() - 1 + k.bit_length() - 1 >= _TMA_LOG2_MK_THRESHOLD\n\n\n@functools.cache\ndef _get_compiled_kernel_nvfp4_tma(\n dtype_key: str,\n K: int,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool = False,\n disable_fp4_quant_fast_math: bool = False,\n global_scale_is_tensor: bool = True,\n) -> Tuple[Callable, int]:\n \"\"\"\n Get or compile TMA-based NVFP4 kernel with TVM-FFI.\n\n Cached by (K, dtype_key, sf_layout, pdl, global_scale_is_tensor).\n \"\"\"\n _dtype_map = {\n \"float16\": cutlass.Float16,\n \"bfloat16\": cutlass.BFloat16,\n }\n cutlass_dtype = _dtype_map[dtype_key]\n kernel_obj = NVFP4QuantizeTMAKernel(\n cutlass_dtype,\n K,\n sf_layout=sf_layout,\n enable_pdl=enable_pdl,\n disable_fp4_quant_fast_math=disable_fp4_quant_fast_math,\n )\n\n sym_m = cute.sym_int()\n sym_padded_m = cute.sym_int()\n\n input_fake = cute.runtime.make_fake_compact_tensor(\n cutlass_dtype, (sym_padded_m, K), stride_order=(1, 0), assumed_align=16\n )\n output_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_m, K // 2), stride_order=(1, 0), assumed_align=16\n )\n sym_scale_size = cute.sym_int()\n scales_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_scale_size,), assumed_align=16\n )\n global_scale_fake = (\n cute.runtime.make_fake_compact_tensor(cutlass.Float32, (1,), assumed_align=4)\n if global_scale_is_tensor\n else Float32(1.0)\n )\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n\n compiled_kernel = build_and_load_cute_dsl_kernel(\n _CUTE_DSL_MODULE,\n _nvfp4_kernel_name(\n \"tma\",\n dtype_key,\n K,\n sf_layout,\n enable_pdl,\n disable_fp4_quant_fast_math,\n silu_and_mul=False,\n global_scale_is_tensor=global_scale_is_tensor,\n ),\n lambda: cute.compile(\n kernel_obj,\n input_fake,\n output_fake,\n scales_fake,\n Int32(1), # Dummy M\n Int32(1024), # Dummy padded_M\n Int32(1), # Dummy num_blocks\n global_scale_fake,\n stream_fake,\n options=\"--enable-tvm-ffi\",\n ),\n extra_key_files=_kernel_source_files(),\n )\n\n return compiled_kernel, kernel_obj.rows_per_block\n\n\n@flashinfer_api\ndef nvfp4_quantize_cute_dsl(\n input: torch.Tensor,\n global_scale: float | torch.Tensor,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool | None = None,\n) -> Tuple[torch.Tensor, torch.Tensor]:\n r\"\"\"Quantize input tensor to NVFP4 format using the CuTe-DSL kernel.\n\n GPU implementation matching :func:`flashinfer.quantization.nvfp4_quantize`:\n\n - E4M3 scale factors (FP8)\n - E2M1 output format (4-bit, 2 values per byte)\n - Supports 128x4, 8x4, and linear scale-factor layouts\n - ``sf_vec_size = 16``\n\n The kernel is compiled separately for host-scalar and device-tensor\n global scales and handles varying ``M`` (batch size) at runtime without\n recompilation.\n\n Parameters\n ----------\n input : torch.Tensor\n Input tensor of shape ``[M, K]`` with dtype\n fp16/bf16/float8_e4m3fn.\n global_scale : float or torch.Tensor\n Host-side NVFP4 global scale factor. A single-element tensor is also\n accepted for backward compatibility.\n sf_layout : int\n Scale-factor layout (``0=128x4``, ``1=8x4``, ``2=linear``).\n enable_pdl : bool, optional\n Whether to enable Programmatic Dependent Launch. Auto-detected\n from device capability (SM >= 9.0) when ``None``.\n\n Returns\n -------\n Tuple[torch.Tensor, torch.Tensor]\n ``(fp4_tensor, scale_tensor)`` where ``fp4_tensor`` is the\n quantized tensor of shape ``[M, K/2]`` with dtype ``uint8`` and\n ``scale_tensor`` holds the E4M3 scale factors (``uint8``) reshaped\n to ``[padded_rows, K/16]``.\n \"\"\"\n from ...utils import device_support_pdl\n\n _valid_sf_layouts = (SF_LAYOUT_128x4, SF_LAYOUT_8x4, SF_LAYOUT_LINEAR)\n assert sf_layout in _valid_sf_layouts, (\n f\"sf_layout must be one of {_valid_sf_layouts}, got {sf_layout}\"\n )\n _supported_dtypes = (torch.float16, torch.bfloat16, torch.float8_e4m3fn)\n assert input.dtype in _supported_dtypes, (\n f\"Input dtype must be one of {_supported_dtypes}, got {input.dtype}\"\n )\n assert input.is_cuda, \"Input must be on CUDA device\"\n\n enable_pdl = device_support_pdl(input.device) if enable_pdl is not False else False\n\n if input.dim() > 2:\n m = input.numel() // input.shape[-1]\n k = input.shape[-1]\n input = input.reshape(m, k)\n else:\n m, k = input.shape\n\n assert k % NVFP4_SF_VEC_SIZE == 0, (\n f\"K ({k}) must be divisible by NVFP4_SF_VEC_SIZE={NVFP4_SF_VEC_SIZE}\"\n )\n\n input = input.contiguous()\n\n _torch_to_dtype_key = {\n torch.float16: \"float16\",\n torch.bfloat16: \"bfloat16\",\n torch.float8_e4m3fn: \"float8_e4m3fn\",\n }\n dtype_key = _torch_to_dtype_key[input.dtype]\n\n # Never call .item() on a device scale: that would synchronize the stream\n # and make this path illegal during CUDA graph capture.\n global_scale_is_tensor = isinstance(global_scale, torch.Tensor)\n if global_scale_is_tensor:\n global_scale_arg = (\n cast(torch.Tensor, global_scale)\n .float()\n .reshape(1)\n .contiguous()\n .to(input.device)\n )\n else:\n global_scale_arg = float(global_scale)\n\n num_sm = get_num_sm(input.device)\n\n num_sf_blocks_per_row = k // NVFP4_SF_VEC_SIZE\n\n disable_fp4_quant_fast_math = _env_flag_enabled(\n \"FLASHINFER_DISABLE_FP4_QUANT_FAST_MATH\"\n )\n nvfp4_4over6_config = current_nvfp4_4over6_config()\n if nvfp4_4over6_config is not None and input.dtype == torch.float8_e4m3fn:\n raise ValueError(\"FLASHINFER_NVFP4_4OVER6 requires fp16 or bf16 input\")\n use_tma = _should_use_tma(m, k, input.dtype) and nvfp4_4over6_config is None\n\n if use_tma:\n tma_row_tile = _TMA_ROW_TILE\n if sf_layout == SF_LAYOUT_LINEAR:\n padded_m = _round_up(m, tma_row_tile)\n padded_sf_cols = num_sf_blocks_per_row\n elif sf_layout == SF_LAYOUT_8x4:\n padded_m = _round_up(m, max(tma_row_tile, 8))\n padded_sf_cols = ((num_sf_blocks_per_row + 3) // 4) * 4\n else:\n padded_m = _round_up(m, max(tma_row_tile, ROW_TILE_SIZE))\n padded_sf_cols = ((num_sf_blocks_per_row + 3) // 4) * 4\n\n scale_output_size = padded_m * padded_sf_cols\n\n kernel_fn, rows_per_block = _get_compiled_kernel_nvfp4_tma(\n dtype_key,\n k,\n sf_layout,\n enable_pdl,\n disable_fp4_quant_fast_math,\n global_scale_is_tensor,\n )\n\n # Match CUDA TMA kernel: grid = min(row_tiles, SM_count * 2)\n tma_target_grid = num_sm * 2\n num_blocks = min(\n (padded_m + rows_per_block - 1) // rows_per_block, tma_target_grid\n )\n\n input_padded = input\n if padded_m > m:\n input_padded = torch.zeros(\n padded_m, k, dtype=input.dtype, device=input.device\n )\n input_padded[:m, :] = input\n\n fp4_output = torch.empty(m, k // 2, dtype=torch.uint8, device=input.device)\n scale_output = torch.empty(\n scale_output_size, dtype=torch.uint8, device=input.device\n )\n\n kernel_fn(\n input_padded,\n fp4_output,\n scale_output,\n m,\n padded_m,\n num_blocks,\n global_scale_arg,\n )\n\n if sf_layout == SF_LAYOUT_LINEAR:\n scale_output = scale_output[: m * num_sf_blocks_per_row]\n\n # Reshape using padded_sf_cols for swizzled layouts (the buffer is\n # physically padded and stores data in swizzled order). For linear\n # layout the padding is already trimmed above.\n scale_output = scale_output.reshape(-1, padded_sf_cols)\n\n return fp4_output, scale_output\n\n # Non-TMA path: dual-path dispatch\n # Get or compile kernel (device-independent)\n kernel_fn, block_unit = _get_compiled_kernel_nvfp4(\n dtype_key,\n k,\n sf_layout,\n enable_pdl,\n disable_fp4_quant_fast_math,\n nvfp4_4over6_config,\n global_scale_is_tensor=global_scale_is_tensor,\n )\n\n target_grid = num_sm * _BLOCKS_PER_SM\n\n if sf_layout == SF_LAYOUT_LINEAR:\n padded_m = m\n padded_sf_cols = num_sf_blocks_per_row\n total_sf_blocks = m * num_sf_blocks_per_row\n scale_output_size = total_sf_blocks\n\n sf_blocks_per_tb = block_unit\n num_blocks = min(\n (total_sf_blocks + sf_blocks_per_tb - 1) // sf_blocks_per_tb,\n target_grid,\n )\n\n fp4_output = torch.empty(m, k // 2, dtype=torch.uint8, device=input.device)\n scale_output = torch.empty(\n scale_output_size, dtype=torch.uint8, device=input.device\n )\n\n kernel_fn(\n input,\n fp4_output,\n scale_output,\n m,\n total_sf_blocks,\n num_blocks,\n global_scale_arg,\n )\n else:\n if sf_layout == SF_LAYOUT_8x4:\n row_tile_size = 8\n else:\n row_tile_size = ROW_TILE_SIZE # 128\n padded_m = ((m + row_tile_size - 1) // row_tile_size) * row_tile_size\n padded_sf_cols = ((num_sf_blocks_per_row + 3) // 4) * 4\n scale_output_size = padded_m * padded_sf_cols\n\n rows_per_block = block_unit\n num_blocks = min(\n (padded_m + rows_per_block - 1) // rows_per_block,\n target_grid,\n )\n\n fp4_output = torch.empty(m, k // 2, dtype=torch.uint8, device=input.device)\n scale_output = torch.empty(\n scale_output_size, dtype=torch.uint8, device=input.device\n )\n\n kernel_fn(\n input,\n fp4_output,\n scale_output,\n m,\n padded_m,\n num_blocks,\n global_scale_arg,\n )\n\n # Reshape using padded_sf_cols: for swizzled layouts the buffer includes\n # column padding; for linear layout padded_sf_cols == num_sf_blocks_per_row.\n scale_output = scale_output.reshape(-1, padded_sf_cols)\n\n return fp4_output, scale_output\n\n\ndef silu_and_mul_nvfp4_quantize_cute_dsl(\n input: torch.Tensor,\n global_scale: torch.Tensor,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool | None = None,\n) -> Tuple[torch.Tensor, torch.Tensor]:\n r\"\"\"Apply SwiGLU and NVFP4 quantization using CuTe-DSL.\n\n Computes ``silu(input[..., :K]) * input[..., K:]`` before quantization.\n\n Parameters\n ----------\n input : torch.Tensor\n FP16/BF16 tensor of shape ``[..., 2K]``. Leading dimensions are\n flattened into M.\n global_scale : torch.Tensor\n Float32 scale of shape ``[1]``.\n sf_layout : int\n Scale layout: 0 for 128x4, 1 for 8x4, or 2 for linear.\n enable_pdl : bool, optional\n Enable Programmatic Dependent Launch. Auto-detected when None.\n\n Returns\n -------\n Tuple[torch.Tensor, torch.Tensor]\n Packed FP4 values of shape ``[M, K/2]`` and their uint8 E4M3 scales.\n \"\"\"\n from ...utils import device_support_pdl\n\n _valid_sf_layouts = (SF_LAYOUT_128x4, SF_LAYOUT_8x4, SF_LAYOUT_LINEAR)\n assert sf_layout in _valid_sf_layouts, (\n f\"sf_layout must be one of {_valid_sf_layouts}, got {sf_layout}\"\n )\n _supported_dtypes = (torch.float16, torch.bfloat16)\n assert input.dtype in _supported_dtypes, (\n f\"SwiGLU NVFP4 input dtype must be one of {_supported_dtypes}, \"\n f\"got {input.dtype}\"\n )\n assert input.is_cuda, \"Input must be on CUDA device\"\n\n enable_pdl = device_support_pdl(input.device) if enable_pdl is not False else False\n\n # Flatten leading dimensions into M.\n input_cols = input.shape[-1]\n assert input_cols % 2 == 0, (\n \"the last dimension must be even (gate and up concatenated)\"\n )\n k = input_cols // 2\n assert k % NVFP4_SF_VEC_SIZE == 0, (\n f\"K ({k}) must be divisible by NVFP4_SF_VEC_SIZE={NVFP4_SF_VEC_SIZE}\"\n )\n # Multiply leading dimensions so zero-width inputs remain valid.\n m = 1\n for dim in input.shape[:-1]:\n m *= int(dim)\n\n # Return empty outputs without compiling or launching.\n if m == 0 or k == 0:\n num_sf_blocks_per_row = k // NVFP4_SF_VEC_SIZE\n if sf_layout == SF_LAYOUT_LINEAR:\n padded_sf_cols = num_sf_blocks_per_row\n else:\n padded_sf_cols = ((num_sf_blocks_per_row + 3) // 4) * 4\n return (\n torch.empty((m, k // 2), dtype=torch.uint8, device=input.device),\n torch.empty((m, padded_sf_cols), dtype=torch.uint8, device=input.device),\n )\n\n input = input.reshape(m, input_cols)\n input = input.contiguous()\n # Clone storage-offset views that violate the kernel's 16-byte alignment.\n if input.data_ptr() % 16 != 0:\n input = input.clone()\n\n _torch_to_dtype_key = {\n torch.float16: \"float16\",\n torch.bfloat16: \"bfloat16\",\n }\n dtype_key = _torch_to_dtype_key[input.dtype]\n\n if isinstance(global_scale, torch.Tensor):\n global_scale_tensor = (\n global_scale.float().reshape(1).contiguous().to(input.device)\n )\n else:\n global_scale_tensor = torch.tensor(\n [float(global_scale)], dtype=torch.float32, device=input.device\n )\n\n num_sm = get_num_sm(input.device)\n num_sf_blocks_per_row = k // NVFP4_SF_VEC_SIZE\n\n disable_fp4_quant_fast_math = _env_flag_enabled(\n \"FLASHINFER_DISABLE_FP4_QUANT_FAST_MATH\"\n )\n nvfp4_4over6_config = current_nvfp4_4over6_config()\n\n # SwiGLU fusion uses the non-TMA vectorized-load kernels only.\n kernel_fn, block_unit = _get_compiled_kernel_nvfp4(\n dtype_key,\n k,\n sf_layout,\n enable_pdl,\n disable_fp4_quant_fast_math,\n nvfp4_4over6_config,\n silu_and_mul=True,\n )\n\n target_grid = num_sm * _BLOCKS_PER_SM\n\n if sf_layout == SF_LAYOUT_LINEAR:\n padded_sf_cols = num_sf_blocks_per_row\n total_sf_blocks = m * num_sf_blocks_per_row\n scale_output_size = total_sf_blocks\n\n sf_blocks_per_tb = block_unit\n num_blocks = min(\n (total_sf_blocks + sf_blocks_per_tb - 1) // sf_blocks_per_tb,\n target_grid,\n )\n\n fp4_output = torch.empty(m, k // 2, dtype=torch.uint8, device=input.device)\n scale_output = torch.empty(\n scale_output_size, dtype=torch.uint8, device=input.device\n )\n\n kernel_fn(\n input,\n fp4_output,\n scale_output,\n m,\n total_sf_blocks,\n num_blocks,\n global_scale_tensor,\n )\n else:\n if sf_layout == SF_LAYOUT_8x4:\n row_tile_size = 8\n else:\n row_tile_size = ROW_TILE_SIZE # 128\n padded_m = ((m + row_tile_size - 1) // row_tile_size) * row_tile_size\n padded_sf_cols = ((num_sf_blocks_per_row + 3) // 4) * 4\n scale_output_size = padded_m * padded_sf_cols\n\n rows_per_block = block_unit\n num_blocks = min(\n (padded_m + rows_per_block - 1) // rows_per_block,\n target_grid,\n )\n\n fp4_output = torch.empty(m, k // 2, dtype=torch.uint8, device=input.device)\n scale_output = torch.empty(\n scale_output_size, dtype=torch.uint8, device=input.device\n )\n\n kernel_fn(\n input,\n fp4_output,\n scale_output,\n m,\n padded_m,\n num_blocks,\n global_scale_tensor,\n )\n\n # Return scales in their layout-specific 2D shape.\n scale_output = scale_output.reshape(-1, padded_sf_cols)\n\n return fp4_output, scale_output\n\n\n@flashinfer_api\ndef nvfp4_quantize_per_token_cute_dsl(\n input: torch.Tensor,\n global_scale_inv: torch.Tensor,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool | None = None,\n) -> Tuple[torch.Tensor, torch.Tensor, torch.Tensor]:\n r\"\"\"Per-token NVFP4 activation quantization using the CuTe-DSL kernel.\n\n Unlike :func:`nvfp4_quantize_cute_dsl`, which applies a single global\n scale, this variant computes one quantization scale **per row (token)** of\n the activation. Each row is scaled independently so that its largest\n magnitude maps to the NVFP4 dynamic range, and the resulting per-token\n scale is returned alongside the packed FP4 output and the E4M3 block\n scale factors.\n\n - E4M3 block scale factors (FP8), ``sf_vec_size = 16``\n - E2M1 output format (4-bit, 2 values per byte)\n - Supports 128x4, 8x4, and linear scale-factor layouts\n\n The kernel is compiled once per ``(K, dtype, sf_layout, pdl)`` tuple and\n handles varying ``M`` (number of tokens) at runtime without recompilation.\n\n Parameters\n ----------\n input : torch.Tensor\n 2-D activation tensor of shape ``[M, K]`` with dtype fp16/bf16. ``K``\n must be divisible by ``NVFP4_SF_VEC_SIZE`` (16).\n global_scale_inv : torch.Tensor\n Scalar tensor (``float32``) holding the inverse global scale applied on\n top of the per-token scale. A Python ``float`` is also accepted and\n wrapped into a tensor internally.\n sf_layout : int\n Scale-factor layout (``0=128x4``, ``1=8x4``, ``2=linear``).\n enable_pdl : bool, optional\n Whether to enable Programmatic Dependent Launch. Auto-detected from\n device capability (SM >= 9.0) when ``None``; pass ``False`` to force it\n off.\n\n Returns\n -------\n Tuple[torch.Tensor, torch.Tensor, torch.Tensor]\n ``(fp4_output, scale_output, per_token_scale)`` where:\n\n - ``fp4_output`` is the packed quantized tensor of shape ``[M, K/2]``\n with dtype ``uint8`` (two E2M1 values per byte).\n - ``scale_output`` holds the E4M3 block scale factors (``uint8``)\n reshaped to ``[padded_rows, padded_sf_cols]``. The padding depends on\n ``sf_layout``: ``linear`` keeps ``M`` rows, while ``128x4`` / ``8x4``\n pad rows and columns up to the layout tile.\n - ``per_token_scale`` is the per-row quantization scale of shape\n ``[M]`` with dtype ``float32``.\n \"\"\"\n from ...utils import device_support_pdl\n\n _valid_sf_layouts = (SF_LAYOUT_128x4, SF_LAYOUT_8x4, SF_LAYOUT_LINEAR)\n assert sf_layout in _valid_sf_layouts, (\n f\"sf_layout must be one of {_valid_sf_layouts}, got {sf_layout}\"\n )\n _supported_dtypes = (torch.float16, torch.bfloat16)\n assert input.dtype in _supported_dtypes, (\n f\"Per-token NVFP4 input dtype must be one of {_supported_dtypes}, got {input.dtype}\"\n )\n assert input.is_cuda, \"Input must be on CUDA device\"\n assert input.dim() == 2, \"Per-token NVFP4 quantization expects a 2D input\"\n\n enable_pdl = device_support_pdl(input.device) if enable_pdl is not False else False\n input = input.contiguous()\n m, k = input.shape\n assert k % NVFP4_SF_VEC_SIZE == 0, (\n f\"K ({k}) must be divisible by NVFP4_SF_VEC_SIZE={NVFP4_SF_VEC_SIZE}\"\n )\n\n _torch_to_dtype_key = {\n torch.float16: \"float16\",\n torch.bfloat16: \"bfloat16\",\n }\n dtype_key = _torch_to_dtype_key[input.dtype]\n\n if isinstance(global_scale_inv, torch.Tensor):\n global_scale_inv_tensor = (\n global_scale_inv.float().reshape(1).contiguous().to(input.device)\n )\n else:\n global_scale_inv_tensor = torch.tensor(\n [float(global_scale_inv)], dtype=torch.float32, device=input.device\n )\n\n num_sf_blocks_per_row = k // NVFP4_SF_VEC_SIZE\n if sf_layout == SF_LAYOUT_LINEAR:\n padded_m = m\n padded_sf_cols = num_sf_blocks_per_row\n elif sf_layout == SF_LAYOUT_8x4:\n padded_m = _round_up(m, 8)\n padded_sf_cols = ((num_sf_blocks_per_row + 3) // 4) * 4\n else:\n padded_m = _round_up(m, ROW_TILE_SIZE)\n padded_sf_cols = ((num_sf_blocks_per_row + 3) // 4) * 4\n\n disable_fp4_quant_fast_math = _env_flag_enabled(\n \"FLASHINFER_DISABLE_FP4_QUANT_FAST_MATH\"\n )\n nvfp4_4over6_config = current_nvfp4_4over6_config()\n\n kernel_fn = _get_compiled_kernel_nvfp4_per_token(\n dtype_key,\n k,\n sf_layout,\n enable_pdl,\n disable_fp4_quant_fast_math,\n nvfp4_4over6_config,\n )\n\n fp4_output = torch.empty(m, k // 2, dtype=torch.uint8, device=input.device)\n scale_output = torch.zeros(\n padded_m * padded_sf_cols, dtype=torch.uint8, device=input.device\n )\n per_token_scale = torch.empty(m, dtype=torch.float32, device=input.device)\n\n kernel_fn(\n input,\n fp4_output,\n scale_output,\n per_token_scale,\n m,\n global_scale_inv_tensor,\n )\n\n scale_output = scale_output.reshape(-1, padded_sf_cols)\n return fp4_output, scale_output, per_token_scale\n\n\n__all__ = [\n \"SF_LAYOUT_128x4\",\n \"SF_LAYOUT_8x4\",\n \"SF_LAYOUT_LINEAR\",\n \"NVFP4QuantizeLinearKernel\",\n \"NVFP4QuantizeSwizzledKernel\",\n \"NVFP4QuantizePerTokenKernel\",\n \"NVFP4QuantizeTMAKernel\",\n \"nvfp4_quantize_cute_dsl\",\n \"silu_and_mul_nvfp4_quantize_cute_dsl\",\n \"nvfp4_quantize_per_token_cute_dsl\",\n \"_get_compiled_kernel_nvfp4\",\n \"_get_compiled_kernel_nvfp4_per_token\",\n \"_get_compiled_kernel_nvfp4_tma\",\n]\n"},"after_code":{"kind":"string","value":"\"\"\"\nCopyright (c) 2025 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nNVFP4 Quantization using CuTe-DSL\n=================================\n\nNVFP4 quantization kernel using CuTe-DSL.\nSupports multiple scale factor layouts: swizzled 128x4, swizzled 8x4, and linear.\n\nDual-path optimization following the MXFP4 pattern:\n- Linear layout: flat SF-block iteration for 100% thread utilization\n- Swizzled layout: row-based iteration with multi-row / column-loop paths\n\nKey differences from MXFP4:\n- sf_vec_size=16 (vs 32 for MXFP4)\n- E4M3 scale factors (vs UE8M0 for MXFP4)\n- User-provided global_scale (vs auto-computed for MXFP4)\n- 3 layouts: 128x4, 8x4, linear (vs 128x4, linear for MXFP4)\n\"\"\"\n\nimport functools\nfrom typing import Callable, Tuple, Union, cast\n\nimport cutlass\nimport cutlass.cute as cute\nimport cutlass.cute.nvgpu.cpasync as cpasync\nimport cutlass.pipeline as pipeline\nfrom cutlass.pipeline import pipeline_init_arrive, pipeline_init_wait\nimport torch\nfrom cutlass import Float32, Int32, Int64, Uint8\n\nfrom ...api_logging import flashinfer_api\nfrom ...jit.cute_dsl_core import build_and_load_cute_dsl_kernel\nfrom ...cute_dsl.fp4_common import (\n block_reduce,\n fdiv_rn,\n fmax_f32,\n fmin_f32,\n get_ptr_as_int64,\n ld_global_v4_u32,\n rcp_approx_ftz,\n st_global_u64,\n warp_reduce,\n)\nfrom ...cute_dsl.utils import get_num_sm\nfrom ..nvfp4_quantization_utils import (\n NVFP44Over6Config,\n current_nvfp4_4over6_config,\n env_flag_enabled as _env_flag_enabled,\n)\nfrom ..quantization_cute_dsl_utils import (\n FLOAT32_MAX,\n NVFP4_SF_VEC_SIZE,\n WARP_SIZE,\n ROW_TILE_SIZE,\n compute_sf_index_swizzled_128x4_gpu,\n compute_sf_index_swizzled_8x4_gpu,\n compute_sf_index_linear_gpu,\n half2_max_abs_8 as half2_max_abs_8_fn,\n bfloat2_max_abs_8 as bfloat2_max_abs_8_fn,\n hmax_reduce_to_f32,\n bfloat2_hmax_reduce_to_f32,\n half2x8_to_e2m1x16_packed,\n bfloat2x8_to_e2m1x16_packed,\n process_nvfp4_block_half,\n process_nvfp4_block_bfloat,\n process_nvfp4_block_fp8,\n process_nvfp4_silu_block_half,\n process_nvfp4_silu_block_bfloat,\n)\n\nSF_LAYOUT_128x4 = 0\nSF_LAYOUT_8x4 = 1\nSF_LAYOUT_LINEAR = 2\n\n# Blocks per SM for occupancy target\n_BLOCKS_PER_SM = 4\n\n# Maximum threads per block\n_MAX_THREADS_PER_BLOCK = 1024\n\n# Thread count bounds for swizzled kernel\n_MIN_THREADS = 128\n_MAX_THREADS = 512\n\n# Linear kernel: fixed 16 warps (512 threads), 1 SF block per thread\n_LINEAR_WARPS_PER_BLOCK = 16\n_LINEAR_SF_BLOCKS_PER_TB = _LINEAR_WARPS_PER_BLOCK * WARP_SIZE # 512\n\n\ndef _compute_optimal_threads(K: int) -> int:\n \"\"\"\n Compute optimal thread count for 100% utilization in the swizzled kernel.\n\n For NVFP4, each thread processes 1 SF block (16 elements), so:\n threads_per_row = K / 16\n\n We want num_threads to be a multiple of threads_per_row so that\n rows_per_block = num_threads / threads_per_row is an integer.\n\n We prefer LARGER thread counts (up to _MAX_THREADS) for better occupancy.\n\n If threads_per_row > _MAX_THREADS, we use _MAX_THREADS with a column loop.\n\n Args:\n K: Number of columns (must be divisible by 16)\n\n Returns:\n Optimal number of threads per block\n \"\"\"\n threads_per_row = K // NVFP4_SF_VEC_SIZE # K / 16\n\n if threads_per_row > _MAX_THREADS:\n # Column loop mode: use maximum threads\n return _MAX_THREADS\n\n # Find largest multiple of threads_per_row in [_MIN_THREADS, _MAX_THREADS]\n largest = (_MAX_THREADS // threads_per_row) * threads_per_row\n if largest >= _MIN_THREADS:\n return largest\n\n # If largest multiple is below _MIN_THREADS, use smallest valid one\n candidate = threads_per_row\n while candidate < _MIN_THREADS:\n candidate += threads_per_row\n if candidate <= _MAX_THREADS:\n return candidate\n\n # Fallback (shouldn't happen for reasonable K)\n return _MAX_THREADS\n\n\n@cute.jit\ndef _dispatch_process_nvfp4_block(\n row_input,\n elem_base: Int32,\n global_scale: Float32,\n row_amax: Float32,\n K: int,\n is_bfloat16: bool,\n is_fp8: bool,\n silu_and_mul: bool,\n disable_fp4_quant_fast_math: bool,\n nvfp4_4over6_config: NVFP44Over6Config | None,\n):\n \"\"\"Dispatch one NVFP4 block by dtype and optional SwiGLU fusion.\"\"\"\n if cutlass.const_expr(silu_and_mul):\n if cutlass.const_expr(is_bfloat16):\n return process_nvfp4_silu_block_bfloat(\n row_input,\n elem_base,\n Int32(K),\n global_scale,\n disable_fp4_quant_fast_math,\n nvfp4_4over6_config,\n row_amax,\n )\n else:\n return process_nvfp4_silu_block_half(\n row_input,\n elem_base,\n Int32(K),\n global_scale,\n disable_fp4_quant_fast_math,\n nvfp4_4over6_config,\n row_amax,\n )\n else:\n if cutlass.const_expr(is_fp8):\n return process_nvfp4_block_fp8(\n row_input, elem_base, global_scale, disable_fp4_quant_fast_math\n )\n elif cutlass.const_expr(is_bfloat16):\n return process_nvfp4_block_bfloat(\n row_input,\n elem_base,\n global_scale,\n disable_fp4_quant_fast_math,\n nvfp4_4over6_config,\n row_amax,\n )\n else:\n return process_nvfp4_block_half(\n row_input,\n elem_base,\n global_scale,\n disable_fp4_quant_fast_math,\n nvfp4_4over6_config,\n row_amax,\n )\n\n\n# =============================================================================\n# CuTe-DSL Kernel Class for Linear Layout — Flat SF-Block Iteration\n# =============================================================================\n\n\nclass NVFP4QuantizeLinearKernel:\n \"\"\"\n NVFP4 quantization kernel optimized for LINEAR layout.\n\n Uses flat SF-block iteration for efficient memory access. Row and\n column indices are derived from the flat SF index via integer division.\n\n No padding passes are needed since for linear layout:\n - padded_m == m (no row padding)\n - padded_sf_cols == num_sf_blocks_per_row (no column padding)\n\n This kernel is M-agnostic: M-dependent values are passed at runtime.\n Each thread handles one SF block (16 elements).\n \"\"\"\n\n WARPS_PER_BLOCK = _LINEAR_WARPS_PER_BLOCK\n SF_BLOCKS_PER_TB = _LINEAR_SF_BLOCKS_PER_TB\n\n def __init__(\n self,\n dtype: cutlass.Numeric,\n K: int,\n enable_pdl: bool = False,\n disable_fp4_quant_fast_math: bool = False,\n nvfp4_4over6_config: NVFP44Over6Config | None = None,\n silu_and_mul: bool = False,\n ):\n self.dtype = dtype\n self.K = K\n self.is_bfloat16 = dtype == cutlass.BFloat16\n self.is_fp8 = dtype == cutlass.Float8E4M3FN\n self.enable_pdl = enable_pdl\n self.disable_fp4_quant_fast_math = disable_fp4_quant_fast_math\n self.nvfp4_4over6_config = nvfp4_4over6_config\n # SwiGLU uses a 2*K-wide input and does not support FP8.\n self.silu_and_mul = silu_and_mul\n assert not (silu_and_mul and self.is_fp8), (\n \"SwiGLU fusion does not support fp8 input\"\n )\n\n assert K % NVFP4_SF_VEC_SIZE == 0\n self.num_sf_blocks_per_row = K // NVFP4_SF_VEC_SIZE\n\n @cute.jit\n def _process_block(\n self, row_input, elem_base: Int32, global_scale: Float32, row_amax: Float32\n ):\n \"\"\"Quantize one 16-element block, optionally fusing silu(gate) * up.\n\n For the SwiGLU path the up block sits self.K columns after the gate\n block in the same (2*K-wide) input row.\n \"\"\"\n return _dispatch_process_nvfp4_block(\n row_input,\n elem_base,\n global_scale,\n row_amax,\n self.K,\n self.is_bfloat16,\n self.is_fp8,\n self.silu_and_mul,\n self.disable_fp4_quant_fast_math,\n self.nvfp4_4over6_config,\n )\n\n @cute.jit\n def __call__(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n M: Int32,\n total_sf_blocks: Int32,\n num_blocks: Int32,\n global_scale: Union[Float32, cute.Tensor],\n stream,\n ):\n threads_per_block = self.WARPS_PER_BLOCK * WARP_SIZE\n\n self.kernel(mInput, mOutput, mScales, M, total_sf_blocks, global_scale).launch(\n grid=[num_blocks, 1, 1],\n block=[threads_per_block, 1, 1],\n max_number_threads=[_MAX_THREADS_PER_BLOCK, 1, 1],\n min_blocks_per_mp=_BLOCKS_PER_SM,\n stream=stream,\n use_pdl=self.enable_pdl,\n )\n\n @cute.kernel\n def kernel(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n M: Int32,\n total_sf_blocks: Int32,\n global_scale: Union[Float32, cute.Tensor],\n ):\n \"\"\"\n NVFP4 quantization with flat SF-block iteration for linear layout.\n\n Each thread handles one SF block (16 elements). Row and column\n indices are derived from the flat SF index.\n \"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n bidx, _, _ = cute.arch.block_idx()\n grid_dim_x, _, _ = cute.arch.grid_dim()\n\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_wait()\n\n # Device scales stay pointer-loaded; host scales arrive as launch arguments.\n if cutlass.const_expr(isinstance(global_scale, cute.Tensor)):\n global_scale_value = Float32(global_scale[Int32(0)])\n else:\n global_scale_value = global_scale\n row_amax = Float32(0.0)\n\n num_sf_blocks_per_row = self.num_sf_blocks_per_row\n sf_blocks_per_tb = self.SF_BLOCKS_PER_TB\n stride = grid_dim_x * sf_blocks_per_tb\n\n # Flat SF-block iteration\n sf_idx = bidx * sf_blocks_per_tb + tidx\n\n while sf_idx < total_sf_blocks:\n row_idx = sf_idx // num_sf_blocks_per_row\n col_idx = sf_idx % num_sf_blocks_per_row\n\n elem_base = col_idx * NVFP4_SF_VEC_SIZE\n row_input = mInput[row_idx, None]\n\n # Apply optional SwiGLU and quantize the block.\n scale_fp8, packed64 = self._process_block(\n row_input, elem_base, global_scale_value, row_amax\n )\n\n # Write scale factor using linear indexing\n sf_offset = compute_sf_index_linear_gpu(\n row_idx, col_idx, num_sf_blocks_per_row\n )\n mScales[sf_offset] = scale_fp8\n\n # Store 8 bytes (16 FP4 values = 1 x st.global.u64)\n row_output = mOutput[row_idx, None]\n out_base = col_idx * (NVFP4_SF_VEC_SIZE // 2)\n out_ptr = get_ptr_as_int64(row_output, out_base)\n st_global_u64(out_ptr, packed64)\n\n sf_idx = sf_idx + stride\n\n # PDL: Signal that dependent kernels can start early\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_launch_dependents()\n\n\n# =============================================================================\n# CuTe-DSL Kernel Class for Swizzled Layout — Row-Based Iteration\n# =============================================================================\n\n\nclass NVFP4QuantizeSwizzledKernel:\n \"\"\"\n NVFP4 quantization kernel optimized for SWIZZLED (128x4 or 8x4) layout.\n\n Key optimizations:\n - Multi-row processing: threads process multiple rows per block when K is small\n - Row-based iteration with grid-stride loop\n - Padding row fast path - only zero out scale factors\n\n Thread utilization optimization:\n - Dynamic thread count based on K for 100% thread utilization\n - For small K: Multiple rows processed per block iteration\n - For large K: Single row with column loop\n\n For NVFP4, each thread processes 1 SF block (16 elements) independently,\n so threads_per_row = num_sf_blocks_per_row = K/16.\n\n This kernel is M-agnostic: M-dependent values (M, padded_M) are passed\n at runtime.\n \"\"\"\n\n def __init__(\n self,\n dtype: cutlass.Numeric,\n K: int,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool = False,\n disable_fp4_quant_fast_math: bool = False,\n nvfp4_4over6_config: NVFP44Over6Config | None = None,\n silu_and_mul: bool = False,\n ):\n self.dtype = dtype\n self.K = K\n self.is_bfloat16 = dtype == cutlass.BFloat16\n self.is_fp8 = dtype == cutlass.Float8E4M3FN\n self.enable_pdl = enable_pdl\n self.disable_fp4_quant_fast_math = disable_fp4_quant_fast_math\n self.nvfp4_4over6_config = nvfp4_4over6_config\n self.sf_layout = sf_layout\n self.sf_is_128x4 = sf_layout == SF_LAYOUT_128x4\n self.sf_is_8x4 = sf_layout == SF_LAYOUT_8x4\n # SwiGLU uses a 2*K-wide input and does not support FP8.\n self.silu_and_mul = silu_and_mul\n assert not (silu_and_mul and self.is_fp8), (\n \"SwiGLU fusion does not support fp8 input\"\n )\n\n assert K % NVFP4_SF_VEC_SIZE == 0\n self.num_sf_blocks_per_row = K // NVFP4_SF_VEC_SIZE\n self.padded_sf_cols = ((self.num_sf_blocks_per_row + 3) // 4) * 4\n\n # Compute optimal thread count for 100% utilization\n self.num_threads = _compute_optimal_threads(K)\n self.threads_per_row = self.num_sf_blocks_per_row # 1 thread per SF block\n\n # Multi-row processing constants (compile-time)\n if self.threads_per_row <= self.num_threads:\n self.rows_per_block = self.num_threads // self.threads_per_row\n self.needs_col_loop = False\n else:\n self.rows_per_block = 1\n self.needs_col_loop = True\n\n @cute.jit\n def _compute_sf_offset(\n self, row_idx: Int32, col_idx: Int32, padded_cols: Int32\n ) -> Int32:\n \"\"\"Compute scale factor offset based on layout (compile-time dispatch).\"\"\"\n if cutlass.const_expr(self.sf_is_128x4):\n return compute_sf_index_swizzled_128x4_gpu(row_idx, col_idx, padded_cols)\n else:\n return compute_sf_index_swizzled_8x4_gpu(row_idx, col_idx, padded_cols)\n\n @cute.jit\n def _process_block(\n self, row_input, elem_base: Int32, global_scale: Float32, row_amax: Float32\n ):\n \"\"\"Quantize one 16-element block, optionally fusing silu(gate) * up.\n\n For the SwiGLU path the up block sits self.K columns after the gate\n block in the same (2*K-wide) input row.\n \"\"\"\n return _dispatch_process_nvfp4_block(\n row_input,\n elem_base,\n global_scale,\n row_amax,\n self.K,\n self.is_bfloat16,\n self.is_fp8,\n self.silu_and_mul,\n self.disable_fp4_quant_fast_math,\n self.nvfp4_4over6_config,\n )\n\n @cute.jit\n def __call__(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n M: Int32,\n padded_M: Int32,\n num_blocks: Int32,\n global_scale: Union[Float32, cute.Tensor],\n stream,\n ):\n self.kernel(mInput, mOutput, mScales, M, padded_M, global_scale).launch(\n grid=[num_blocks, 1, 1],\n block=[self.num_threads, 1, 1],\n max_number_threads=[_MAX_THREADS_PER_BLOCK, 1, 1],\n min_blocks_per_mp=_BLOCKS_PER_SM,\n stream=stream,\n use_pdl=self.enable_pdl,\n )\n\n @cute.kernel\n def kernel(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n M: Int32,\n padded_M: Int32,\n global_scale: Union[Float32, cute.Tensor],\n ):\n \"\"\"\n Row-based kernel for swizzled layout.\n\n When K is small: each block processes multiple rows simultaneously.\n When K is large: each block processes one row with column loop.\n \"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n bidx, _, _ = cute.arch.block_idx()\n grid_dim_x, _, _ = cute.arch.grid_dim()\n\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_wait()\n\n # Device scales stay pointer-loaded; host scales arrive as launch arguments.\n if cutlass.const_expr(isinstance(global_scale, cute.Tensor)):\n global_scale_value = Float32(global_scale[Int32(0)])\n else:\n global_scale_value = global_scale\n row_amax = Float32(0.0)\n\n # Compile-time constants\n num_sf_blocks_per_row = self.num_sf_blocks_per_row\n padded_sf_cols = self.padded_sf_cols\n threads_per_row = self.threads_per_row\n rows_per_block = self.rows_per_block\n\n if cutlass.const_expr(self.needs_col_loop):\n # Large K path: single row per block iteration with column loop\n # Each thread maps to one SF block; threads stride over columns\n num_threads = self.num_threads\n\n row_idx = bidx\n while row_idx < padded_M:\n is_padding_row = row_idx >= M\n\n if is_padding_row:\n # Fast path: padding row - only zero out scale factors\n sf_col_idx = tidx\n while sf_col_idx < padded_sf_cols:\n sf_offset = self._compute_sf_offset(\n row_idx, sf_col_idx, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n sf_col_idx = sf_col_idx + num_threads\n else:\n # Normal path: process actual data row with column loop\n sf_col_idx = tidx\n while sf_col_idx < num_sf_blocks_per_row:\n elem_base = sf_col_idx * NVFP4_SF_VEC_SIZE\n row_input = mInput[row_idx, None]\n\n # Apply optional SwiGLU and quantize the block.\n scale_fp8, packed64 = self._process_block(\n row_input, elem_base, global_scale_value, row_amax\n )\n\n # Write scale factor using swizzled indexing\n sf_offset = self._compute_sf_offset(\n row_idx, sf_col_idx, padded_sf_cols\n )\n mScales[sf_offset] = scale_fp8\n\n # Store 8 bytes (16 FP4 values = 1 x st.global.u64)\n row_output = mOutput[row_idx, None]\n out_base = sf_col_idx * (NVFP4_SF_VEC_SIZE // 2)\n out_ptr = get_ptr_as_int64(row_output, out_base)\n st_global_u64(out_ptr, packed64)\n\n sf_col_idx = sf_col_idx + num_threads\n\n # Handle padding columns for this row\n sf_col_idx = num_sf_blocks_per_row + tidx\n while sf_col_idx < padded_sf_cols:\n sf_offset = self._compute_sf_offset(\n row_idx, sf_col_idx, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n sf_col_idx = sf_col_idx + num_threads\n\n row_idx = row_idx + grid_dim_x\n else:\n # Small K path: multi-row processing\n # Thread mapping: tidx -> (row_in_block, sf_idx_in_row)\n row_in_block = tidx // threads_per_row\n sf_idx_in_row = tidx % threads_per_row\n\n # Grid-stride loop over row batches\n row_batch_idx = bidx\n # Initialize row_idx before while loop (CuTe DSL requires variables\n # modified in while loops to be defined before the loop)\n row_idx = row_batch_idx * rows_per_block + row_in_block\n while row_batch_idx * rows_per_block < padded_M:\n if row_idx < padded_M:\n is_padding_row = row_idx >= M\n\n if is_padding_row:\n # Fast path: padding row - zero out ALL padded_sf_cols\n # Thread-stride loop since padded_sf_cols may exceed\n # threads_per_row (e.g. K=32: threads_per_row=2,\n # padded_sf_cols=4)\n local_sf_idx = sf_idx_in_row\n while local_sf_idx < padded_sf_cols:\n sf_offset = self._compute_sf_offset(\n row_idx, local_sf_idx, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n local_sf_idx = local_sf_idx + threads_per_row\n else:\n # Normal path: process actual data\n if sf_idx_in_row < num_sf_blocks_per_row:\n elem_base = sf_idx_in_row * NVFP4_SF_VEC_SIZE\n row_input = mInput[row_idx, None]\n\n # Apply optional SwiGLU and quantize the block.\n scale_fp8, packed64 = self._process_block(\n row_input, elem_base, global_scale_value, row_amax\n )\n\n # Write scale factor using swizzled indexing\n sf_offset = self._compute_sf_offset(\n row_idx, sf_idx_in_row, padded_sf_cols\n )\n mScales[sf_offset] = scale_fp8\n\n # Store 8 bytes (16 FP4 values = 1 x st.global.u64)\n row_output = mOutput[row_idx, None]\n out_base = sf_idx_in_row * (NVFP4_SF_VEC_SIZE // 2)\n out_ptr = get_ptr_as_int64(row_output, out_base)\n st_global_u64(out_ptr, packed64)\n\n # Handle padding SF columns for this row\n # Thread-stride loop starting from first padding column\n if cutlass.const_expr(\n self.num_sf_blocks_per_row != self.padded_sf_cols\n ):\n pad_col = num_sf_blocks_per_row + sf_idx_in_row\n while pad_col < padded_sf_cols:\n sf_offset = self._compute_sf_offset(\n row_idx, pad_col, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n pad_col = pad_col + threads_per_row\n\n row_batch_idx = row_batch_idx + grid_dim_x\n # Update row_idx for next iteration\n row_idx = row_batch_idx * rows_per_block + row_in_block\n\n # PDL: Signal that dependent kernels can start early\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_launch_dependents()\n\n\n# =============================================================================\n# CuTe-DSL Kernel Class for Per-Token Activation Quantization\n# =============================================================================\n\n\n_PER_TOKEN_THREADS = 128\n_PER_TOKEN_WARPS = _PER_TOKEN_THREADS // WARP_SIZE\n\n\nclass NVFP4QuantizePerTokenKernel:\n \"\"\"\n One CTA per token row. The first pass reduces the row amax, then the\n second pass reuses the regular NVFP4 block quantizer with that row's\n global encode scale.\n \"\"\"\n\n def __init__(\n self,\n dtype: cutlass.Numeric,\n K: int,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool = False,\n disable_fp4_quant_fast_math: bool = False,\n nvfp4_4over6_config: NVFP44Over6Config | None = None,\n ):\n self.dtype = dtype\n self.K = K\n self.is_bfloat16 = dtype == cutlass.BFloat16\n self.enable_pdl = enable_pdl\n self.disable_fp4_quant_fast_math = disable_fp4_quant_fast_math\n self.nvfp4_4over6_config = nvfp4_4over6_config\n self.sf_layout = sf_layout\n self.sf_is_128x4 = sf_layout == SF_LAYOUT_128x4\n self.sf_is_8x4 = sf_layout == SF_LAYOUT_8x4\n\n assert dtype != cutlass.Float8E4M3FN, (\n \"per-token NVFP4 does not support FP8 input\"\n )\n assert K % NVFP4_SF_VEC_SIZE == 0\n self.num_sf_blocks_per_row = K // NVFP4_SF_VEC_SIZE\n if sf_layout == SF_LAYOUT_LINEAR:\n self.padded_sf_cols = self.num_sf_blocks_per_row\n else:\n self.padded_sf_cols = ((self.num_sf_blocks_per_row + 3) // 4) * 4\n\n @cute.jit\n def _compute_sf_offset(\n self, row_idx: Int32, col_idx: Int32, padded_cols: Int32\n ) -> Int32:\n if cutlass.const_expr(self.sf_is_128x4):\n return compute_sf_index_swizzled_128x4_gpu(row_idx, col_idx, padded_cols)\n else:\n if cutlass.const_expr(self.sf_is_8x4):\n return compute_sf_index_swizzled_8x4_gpu(row_idx, col_idx, padded_cols)\n else:\n return compute_sf_index_linear_gpu(row_idx, col_idx, padded_cols)\n\n @cute.jit\n def _row_scales(\n self, row_amax: Float32, global_scale_inv: Float32\n ) -> Tuple[Float32, Float32]:\n global_encode_scale = Float32(0.0)\n per_token_scale = Float32(0.0)\n if cutlass.const_expr(self.disable_fp4_quant_fast_math):\n global_scale = fdiv_rn(Float32(1.0), global_scale_inv)\n if row_amax == Float32(0.0):\n per_token_scale = Float32(0.0)\n if cutlass.const_expr(self.nvfp4_4over6_config is not None):\n global_encode_scale = Float32(0.0)\n else:\n global_encode_scale = Float32(FLOAT32_MAX)\n else:\n row_encode_scale = fmin_f32(\n fdiv_rn(global_scale, row_amax), Float32(FLOAT32_MAX)\n )\n if row_encode_scale != Float32(0.0):\n global_encode_scale = row_encode_scale\n else:\n global_encode_scale = Float32(1.0)\n per_token_scale = fdiv_rn(Float32(1.0), global_encode_scale)\n else:\n if row_amax == Float32(0.0):\n per_token_scale = Float32(0.0)\n if cutlass.const_expr(self.nvfp4_4over6_config is not None):\n global_encode_scale = Float32(0.0)\n else:\n global_encode_scale = Float32(FLOAT32_MAX)\n else:\n per_token_scale = row_amax * global_scale_inv\n global_encode_scale = rcp_approx_ftz(per_token_scale)\n return global_encode_scale, per_token_scale\n\n @cute.jit\n def __call__(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n mPerTokenScale: cute.Tensor,\n M: Int32,\n mGlobalScaleInv: cute.Tensor,\n stream,\n ):\n self.kernel(\n mInput, mOutput, mScales, mPerTokenScale, M, mGlobalScaleInv\n ).launch(\n grid=[M, 1, 1],\n block=[_PER_TOKEN_THREADS, 1, 1],\n max_number_threads=[_MAX_THREADS_PER_BLOCK, 1, 1],\n min_blocks_per_mp=_BLOCKS_PER_SM,\n stream=stream,\n use_pdl=self.enable_pdl,\n )\n\n @cute.kernel\n def kernel(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n mPerTokenScale: cute.Tensor,\n M: Int32,\n mGlobalScaleInv: cute.Tensor,\n ):\n tidx, _, _ = cute.arch.thread_idx()\n bidx, _, _ = cute.arch.block_idx()\n\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_wait()\n\n smem = cutlass.utils.SmemAllocator()\n reduction_buffer = smem.allocate_tensor(\n Float32,\n cute.make_layout((1, _PER_TOKEN_WARPS)),\n byte_alignment=4,\n )\n\n row_idx = bidx\n num_sf_blocks_per_row = self.num_sf_blocks_per_row\n padded_sf_cols = self.padded_sf_cols\n # Build the row views from 64-bit byte addresses. Slicing with\n # mInput[row_idx, None] computes the row offset row_idx * K in\n # Int32, which wraps once row_idx * K exceeds 2**31 - 1 (reached by\n # the MoE per-token intermediate, e.g. M=851456 x K=2688) and makes\n # the loads fault.\n input_row_addr = get_ptr_as_int64(mInput, Int32(0)) + Int64(row_idx) * Int64(\n self.K * (mInput.element_type.width // 8)\n )\n row_input = cute.make_tensor(\n cute.make_ptr(\n mInput.element_type,\n input_row_addr,\n cute.AddressSpace.gmem,\n assumed_align=16,\n ),\n cute.make_layout((self.K,)),\n )\n output_row_addr = get_ptr_as_int64(mOutput, Int32(0)) + Int64(row_idx) * Int64(\n self.K // 2\n )\n row_output = cute.make_tensor(\n cute.make_ptr(\n mOutput.element_type,\n output_row_addr,\n cute.AddressSpace.gmem,\n assumed_align=8,\n ),\n cute.make_layout((self.K // 2,)),\n )\n\n local_amax = Float32(0.0)\n sf_col_idx = tidx\n while sf_col_idx < num_sf_blocks_per_row:\n elem_base = sf_col_idx * NVFP4_SF_VEC_SIZE\n ptr0 = get_ptr_as_int64(row_input, elem_base)\n ptr1 = get_ptr_as_int64(row_input, elem_base + Int32(8))\n h0, h1, h2, h3 = ld_global_v4_u32(ptr0)\n h4, h5, h6, h7 = ld_global_v4_u32(ptr1)\n if cutlass.const_expr(self.is_bfloat16):\n block_max_h2 = bfloat2_max_abs_8_fn(h0, h1, h2, h3, h4, h5, h6, h7)\n block_max = bfloat2_hmax_reduce_to_f32(block_max_h2)\n else:\n block_max_h2 = half2_max_abs_8_fn(h0, h1, h2, h3, h4, h5, h6, h7)\n block_max = hmax_reduce_to_f32(block_max_h2)\n local_amax = fmax_f32(local_amax, block_max)\n sf_col_idx = sf_col_idx + Int32(_PER_TOKEN_THREADS)\n\n warp_amax = warp_reduce(local_amax, fmax_f32)\n row_amax = block_reduce(warp_amax, fmax_f32, reduction_buffer, Float32(0.0))\n global_scale_inv = Float32(mGlobalScaleInv[Int32(0)])\n global_encode_scale, per_token_scale = self._row_scales(\n row_amax, global_scale_inv\n )\n if tidx == Int32(0):\n mPerTokenScale[row_idx] = per_token_scale\n cute.arch.barrier()\n\n sf_col_idx = tidx\n while sf_col_idx < num_sf_blocks_per_row:\n elem_base = sf_col_idx * NVFP4_SF_VEC_SIZE\n if cutlass.const_expr(self.is_bfloat16):\n scale_fp8, packed64 = process_nvfp4_block_bfloat(\n row_input,\n elem_base,\n global_encode_scale,\n self.disable_fp4_quant_fast_math,\n self.nvfp4_4over6_config,\n row_amax,\n )\n else:\n scale_fp8, packed64 = process_nvfp4_block_half(\n row_input,\n elem_base,\n global_encode_scale,\n self.disable_fp4_quant_fast_math,\n self.nvfp4_4over6_config,\n row_amax,\n )\n\n sf_offset = self._compute_sf_offset(row_idx, sf_col_idx, padded_sf_cols)\n mScales[sf_offset] = scale_fp8\n\n out_base = sf_col_idx * Int32(NVFP4_SF_VEC_SIZE // 2)\n out_ptr = get_ptr_as_int64(row_output, out_base)\n st_global_u64(out_ptr, packed64)\n\n sf_col_idx = sf_col_idx + Int32(_PER_TOKEN_THREADS)\n\n if cutlass.const_expr(self.sf_layout != SF_LAYOUT_LINEAR):\n sf_col_idx = num_sf_blocks_per_row + tidx\n while sf_col_idx < padded_sf_cols:\n sf_offset = self._compute_sf_offset(row_idx, sf_col_idx, padded_sf_cols)\n mScales[sf_offset] = Uint8(0)\n sf_col_idx = sf_col_idx + Int32(_PER_TOKEN_THREADS)\n\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_launch_dependents()\n\n\n# =============================================================================\n# CuTe-DSL TMA Kernel Class for NVFP4\n# =============================================================================\n\n_TMA_ROW_TILE = 16\n_TMA_COL_TILE = 64 # Per-warp column tile\n_TMA_NUM_CONSUMER_WARPS = 8\n_TMA_NUM_STAGES = 4\n_TMA_COLS_PER_STAGE = _TMA_NUM_CONSUMER_WARPS * _TMA_COL_TILE # 512\n\n\ndef _round_up(x: int, d: int) -> int:\n return ((x + d - 1) // d) * d\n\n\nclass NVFP4QuantizeTMAKernel:\n \"\"\"\n TMA-based NVFP4 quantization kernel with pipelined producer-consumer\n warp specialization, matching the CUDA TMA kernel architecture.\n\n Architecture (matches csrc/nv_internal/.../quantization.cuh):\n - 1 producer warp (warp 0) issues TMA G2S loads into staged SMEM buffers\n - 8 consumer warps (warps 1-8) read from SMEM, quantize, write to GMEM\n - PipelineTmaAsync manages multi-stage buffering (4 stages)\n - Each TMA tile: [16, 512] = 16 rows x 8 warps x 64 cols per warp\n - Each consumer warp: 4 threads/row x 8 rows/warp, 2 row iterations\n - Each thread: 16 elements (1 SF block) via 2 x ld.shared.v4.u32\n - Grid-stride loop over row tiles, inner loop over K/512 col chunks\n\n Effective when M >= 1024 and K is a multiple of 512.\n \"\"\"\n\n def __init__(\n self,\n dtype: cutlass.Numeric,\n K: int,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool = False,\n disable_fp4_quant_fast_math: bool = False,\n ):\n self.dtype = dtype\n self.K = K\n self.is_bfloat16 = dtype == cutlass.BFloat16\n self.is_fp8 = dtype == cutlass.Float8E4M3FN\n self.enable_pdl = enable_pdl\n self.disable_fp4_quant_fast_math = disable_fp4_quant_fast_math\n self.sf_layout = sf_layout\n self.sf_is_128x4 = sf_layout == SF_LAYOUT_128x4\n self.sf_is_8x4 = sf_layout == SF_LAYOUT_8x4\n\n assert not self.is_fp8, \"FP8 input not yet supported for TMA kernel\"\n assert K % _TMA_COLS_PER_STAGE == 0, (\n f\"K ({K}) must be a multiple of {_TMA_COLS_PER_STAGE} for TMA kernel\"\n )\n\n self.num_sf_blocks_per_row = K // NVFP4_SF_VEC_SIZE\n self.num_col_chunks = K // _TMA_COLS_PER_STAGE\n\n if sf_layout == SF_LAYOUT_LINEAR:\n self.padded_sf_cols = self.num_sf_blocks_per_row\n elif sf_layout == SF_LAYOUT_8x4:\n self.padded_sf_cols = ((self.num_sf_blocks_per_row + 3) // 4) * 4\n else:\n self.padded_sf_cols = ((self.num_sf_blocks_per_row + 3) // 4) * 4\n\n self.num_consumer_warps = _TMA_NUM_CONSUMER_WARPS # 8\n self.num_stages = _TMA_NUM_STAGES\n self.producer_warp_id = 0 # Warp 0 is producer (matches CUDA kernel)\n self.threads_per_cta = 32 * (self.num_consumer_warps + 1) # 288\n self.rows_per_block = _TMA_ROW_TILE\n self.buffer_align_bytes = 1024\n self.cluster_shape_mn = (1, 1)\n self.elems_per_stage = _TMA_ROW_TILE * _TMA_COLS_PER_STAGE # 8192\n\n # Thread indexing constants (matches CUDA TmaKernelTraitsTwoBytes)\n self.THREADS_PER_ROW = 4 # laneIdx % 4\n self.ROWS_PER_WARP = 8 # 32 / 4\n self.ELTS_PER_THREAD = NVFP4_SF_VEC_SIZE # 16\n\n @cute.jit\n def _compute_sf_offset(\n self, row_idx: Int32, col_idx: Int32, padded_cols: Int32\n ) -> Int32:\n if cutlass.const_expr(self.sf_is_128x4):\n return compute_sf_index_swizzled_128x4_gpu(row_idx, col_idx, padded_cols)\n else:\n if cutlass.const_expr(self.sf_is_8x4):\n return compute_sf_index_swizzled_8x4_gpu(row_idx, col_idx, padded_cols)\n else:\n return compute_sf_index_linear_gpu(row_idx, col_idx, padded_cols)\n\n @cute.jit\n def _quantize_sf_block(\n self,\n h0: cutlass.Uint32,\n h1: cutlass.Uint32,\n h2: cutlass.Uint32,\n h3: cutlass.Uint32,\n h4: cutlass.Uint32,\n h5: cutlass.Uint32,\n h6: cutlass.Uint32,\n h7: cutlass.Uint32,\n global_row: Int32,\n sf_col: Int32,\n global_scale: Float32,\n M: Int32,\n padded_M: Int32,\n padded_sf_cols: Int32,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n ):\n \"\"\"Quantize one 16-element SF block and write results to GMEM.\"\"\"\n from ...cute_dsl.fp4_common import (\n cvt_f32_to_e4m3,\n nvfp4_compute_output_scale,\n nvfp4_compute_output_scale_rn,\n nvfp4_scale_from_amax_rn,\n rcp_approx_ftz,\n )\n\n if global_row < padded_M:\n is_padding_row = global_row >= M\n\n if is_padding_row:\n sf_offset = self._compute_sf_offset(global_row, sf_col, padded_sf_cols)\n mScales[sf_offset] = Uint8(0)\n else:\n if cutlass.const_expr(self.is_bfloat16):\n block_max_h2 = bfloat2_max_abs_8_fn(h0, h1, h2, h3, h4, h5, h6, h7)\n block_max = bfloat2_hmax_reduce_to_f32(block_max_h2)\n else:\n block_max_h2 = half2_max_abs_8_fn(h0, h1, h2, h3, h4, h5, h6, h7)\n block_max = hmax_reduce_to_f32(block_max_h2)\n\n if cutlass.const_expr(self.disable_fp4_quant_fast_math):\n scale_float = nvfp4_scale_from_amax_rn(block_max, global_scale)\n else:\n fp4_max_rcp = rcp_approx_ftz(Float32(6.0))\n scale_float = global_scale * (block_max * fp4_max_rcp)\n scale_fp8_u32 = cvt_f32_to_e4m3(scale_float)\n scale_fp8 = Uint8(scale_fp8_u32 & cutlass.Uint32(0xFF))\n\n if cutlass.const_expr(self.disable_fp4_quant_fast_math):\n output_scale = nvfp4_compute_output_scale_rn(\n scale_fp8_u32, global_scale, block_max\n )\n else:\n output_scale = nvfp4_compute_output_scale(\n scale_fp8_u32, global_scale\n )\n\n if cutlass.const_expr(self.is_bfloat16):\n packed64 = bfloat2x8_to_e2m1x16_packed(\n h0, h1, h2, h3, h4, h5, h6, h7, output_scale\n )\n else:\n packed64 = half2x8_to_e2m1x16_packed(\n h0, h1, h2, h3, h4, h5, h6, h7, output_scale\n )\n\n sf_offset = self._compute_sf_offset(global_row, sf_col, padded_sf_cols)\n mScales[sf_offset] = scale_fp8\n\n row_output = mOutput[global_row, None]\n out_base = sf_col * Int32(NVFP4_SF_VEC_SIZE // 2)\n out_ptr = get_ptr_as_int64(row_output, out_base)\n st_global_u64(out_ptr, packed64)\n\n @cute.jit\n def __call__(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n M: Int32,\n padded_M: Int32,\n num_blocks: Int32,\n global_scale: Union[Float32, cute.Tensor],\n stream,\n ):\n # TMA zero-fills rows beyond the physical input extent while the kernel\n # visits padded_M rows required by the scale layout.\n gInput = cute.make_tensor(\n mInput.iterator,\n cute.make_layout(\n (M, self.K // _TMA_COL_TILE, _TMA_COL_TILE),\n stride=(self.K, _TMA_COL_TILE, 1),\n ),\n )\n\n # SMEM layout per stage: [rows=16, warps=8, cols_per_warp=64]\n # with SWIZZLE_128B applied. Within each warp's [16, 64] tile the\n # row stride is 64 elems = 128 bytes, putting row bits in the S=3\n # range of the swizzle so different rows map to different banks.\n smem_swizzle = cute.make_swizzle(3, 4, 3) # SWIZZLE_128B for 2B types\n smem_outer_single = cute.make_layout(\n (_TMA_ROW_TILE, _TMA_NUM_CONSUMER_WARPS, _TMA_COL_TILE),\n stride=(_TMA_COL_TILE, _TMA_ROW_TILE * _TMA_COL_TILE, 1),\n )\n smem_single_composed = cute.make_composed_layout(\n smem_swizzle, 0, smem_outer_single\n )\n\n cta_tiler = (_TMA_ROW_TILE, _TMA_NUM_CONSUMER_WARPS, _TMA_COL_TILE)\n tma_atom, tma_tensor = cpasync.make_tiled_tma_atom(\n cpasync.CopyBulkTensorTileG2SOp(),\n gInput,\n smem_single_composed,\n cta_tiler,\n )\n\n total_smem_elems = self.elems_per_stage * self.num_stages\n # Staged outer layout (no swizzle — swizzle passed separately)\n smem_outer_staged = cute.make_layout(\n (_TMA_ROW_TILE, _TMA_NUM_CONSUMER_WARPS, _TMA_COL_TILE, self.num_stages),\n stride=(\n _TMA_COL_TILE,\n _TMA_ROW_TILE * _TMA_COL_TILE,\n 1,\n self.elems_per_stage,\n ),\n )\n # Flat layout for manual-swizzle consumer reads\n smem_layout_flat = cute.make_layout((total_smem_elems,))\n\n self.num_tma_load_bytes = cute.size_in_bytes(self.dtype, smem_outer_single)\n\n @cute.struct\n class SharedStorage:\n load_full_mbar: cute.struct.MemRange[cutlass.Int64, self.num_stages]\n load_empty_mbar: cute.struct.MemRange[cutlass.Int64, self.num_stages]\n smem_data: cute.struct.Align[\n cute.struct.MemRange[self.dtype, total_smem_elems],\n self.buffer_align_bytes,\n ]\n\n self.shared_storage = SharedStorage\n\n self.kernel(\n tma_atom,\n tma_tensor,\n mOutput,\n mScales,\n M,\n padded_M,\n global_scale,\n smem_outer_staged,\n smem_swizzle,\n smem_layout_flat,\n ).launch(\n grid=[num_blocks, 1, 1],\n block=[self.threads_per_cta, 1, 1],\n max_number_threads=[\n self.threads_per_cta,\n 1,\n 1,\n ], # __launch_bounds__(288, 2)\n min_blocks_per_mp=2,\n cluster=(*self.cluster_shape_mn, 1),\n stream=stream,\n use_pdl=self.enable_pdl,\n )\n\n @cute.kernel\n def kernel(\n self,\n tma_atom: cute.CopyAtom,\n gInput_tma: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n M: Int32,\n padded_M: Int32,\n global_scale: Union[Float32, cute.Tensor],\n smem_outer_staged: cute.Layout,\n smem_swizzle: cute.Swizzle,\n smem_layout_flat: cute.Layout,\n ):\n from ...cute_dsl.fp4_common import (\n get_smem_ptr_as_int32,\n ld_shared_v4_u32,\n )\n\n tidx, _, _ = cute.arch.thread_idx()\n bidx, _, _ = cute.arch.block_idx()\n grid_dim_x, _, _ = cute.arch.grid_dim()\n\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_wait()\n\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n lane_idx = tidx % 32\n\n # Device scales stay pointer-loaded; host scales arrive as launch arguments.\n if cutlass.const_expr(isinstance(global_scale, cute.Tensor)):\n global_scale_value = Float32(global_scale[Int32(0)])\n else:\n global_scale_value = global_scale\n padded_sf_cols = self.padded_sf_cols\n num_sf_blocks_per_row = self.num_sf_blocks_per_row\n num_col_chunks = self.num_col_chunks\n elems_per_stage = self.elems_per_stage\n\n # ---- SMEM allocation ----\n smem = cutlass.utils.SmemAllocator()\n storage = smem.allocate(self.shared_storage)\n\n load_mbar_ptr = storage.load_full_mbar.data_ptr()\n # Swizzled tensor for TMA partition (address-space-correct writes)\n sData_staged = storage.smem_data.get_tensor(\n smem_outer_staged, swizzle=smem_swizzle\n )\n # Flat tensor for manual-swizzle consumer reads\n sData_flat = storage.smem_data.get_tensor(smem_layout_flat)\n\n # ---- Pipeline setup ----\n load_pipeline = pipeline.PipelineTmaAsync.create(\n barrier_storage=load_mbar_ptr,\n num_stages=self.num_stages,\n producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread, 1),\n consumer_group=pipeline.CooperativeGroup(\n pipeline.Agent.Thread, self.num_consumer_warps\n ),\n tx_count=self.num_tma_load_bytes,\n cta_layout_vmnk=cute.tiled_divide(\n cute.make_layout((*self.cluster_shape_mn, 1)), (1,)\n ),\n defer_sync=True,\n )\n\n pipeline_init_arrive(cluster_shape_mn=self.cluster_shape_mn, is_relaxed=True)\n pipeline_init_wait(cluster_shape_mn=self.cluster_shape_mn)\n\n # ---- TMA partition (3D: rows x warps x cols_per_warp) ----\n gSrc_tiled = cute.local_tile(\n gInput_tma,\n (_TMA_ROW_TILE, _TMA_NUM_CONSUMER_WARPS, _TMA_COL_TILE),\n (None, None, None),\n )\n tAsA, tAgA = cpasync.tma_partition(\n tma_atom,\n 0,\n cute.make_layout(1),\n cute.group_modes(sData_staged, 0, 3), # Group 3 tile modes\n cute.group_modes(gSrc_tiled, 0, 3),\n )\n\n num_row_tiles = cute.ceil_div(padded_M, _TMA_ROW_TILE)\n\n # ---- Consumer thread indexing (matches CUDA TmaKernelTraitsTwoBytes) ----\n # 4 threads per row, 8 rows per warp, 2 row iterations per stage\n col_idx_local = lane_idx % Int32(self.THREADS_PER_ROW)\n row_idx_local = lane_idx // Int32(self.THREADS_PER_ROW)\n\n # ======== Producer warp (warp 0) ========\n if warp_idx == self.producer_warp_id:\n producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.num_stages\n )\n\n row_tile_idx = bidx\n while row_tile_idx < num_row_tiles:\n col_chunk = Int32(0)\n while col_chunk < num_col_chunks:\n load_pipeline.producer_acquire(producer_state)\n\n cute.copy(\n tma_atom,\n tAgA[(None, row_tile_idx, col_chunk, 0)],\n tAsA[(None, producer_state.index)],\n tma_bar_ptr=load_pipeline.producer_get_barrier(producer_state),\n )\n\n producer_state.advance()\n col_chunk = col_chunk + Int32(1)\n\n row_tile_idx = row_tile_idx + grid_dim_x\n\n load_pipeline.producer_tail(producer_state)\n\n # ======== Consumer warps (warps 1-8) ========\n if warp_idx > 0:\n consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.num_stages\n )\n\n # 0-indexed consumer warp id\n consumer_warp_idx = warp_idx - Int32(1)\n\n # Pre-compute warp tile base offset (constant per warp)\n # SMEM 3D layout: [rows=16, warps=8, cols=64] per stage\n # stride: [64, 1024, 1] → warp tile base = warp * 1024\n warp_tile_elems = _TMA_ROW_TILE * _TMA_COL_TILE # 1024\n warp_tile_base = consumer_warp_idx * Int32(warp_tile_elems)\n\n # Float4 base position for this thread (0, 2, 4, 6)\n f4_base = col_idx_local * Int32(2)\n\n # Global column offset for SF index: warp's column within K\n base_col_in_stage = consumer_warp_idx * Int32(\n _TMA_COL_TILE\n ) + col_idx_local * Int32(self.ELTS_PER_THREAD)\n\n row_tile_idx = bidx\n while row_tile_idx < num_row_tiles:\n base_row = row_tile_idx * Int32(_TMA_ROW_TILE)\n\n col_chunk = Int32(0)\n while col_chunk < num_col_chunks:\n load_pipeline.consumer_wait(consumer_state)\n stage = consumer_state.index\n\n # ---- Read ALL SMEM data with SWIZZLE_128B addressing ----\n # Within each warp's [16,64] tile, the XOR pattern matches\n # CUDA's load_input_vec: float4_idx ^= row & 7\n # Physical elem offset in warp tile for (row, float4 f):\n # row * 64 + (f ^ (row & 7)) * 8\n stage_base = stage * Int32(elems_per_stage)\n\n # Row iteration 0 (row_idx_local = 0..7)\n r0_xor = row_idx_local & Int32(7)\n r0_f4_0 = f4_base ^ r0_xor\n r0_f4_1 = (f4_base + Int32(1)) ^ r0_xor\n r0_row_base = (\n stage_base\n + warp_tile_base\n + row_idx_local * Int32(_TMA_COL_TILE)\n )\n r0_addr_0 = get_smem_ptr_as_int32(\n sData_flat, r0_row_base + r0_f4_0 * Int32(8)\n )\n r0_addr_1 = get_smem_ptr_as_int32(\n sData_flat, r0_row_base + r0_f4_1 * Int32(8)\n )\n r0_h0, r0_h1, r0_h2, r0_h3 = ld_shared_v4_u32(r0_addr_0)\n r0_h4, r0_h5, r0_h6, r0_h7 = ld_shared_v4_u32(r0_addr_1)\n\n # Row iteration 1 (row = row_idx_local + 8)\n r1_row = row_idx_local + Int32(self.ROWS_PER_WARP)\n r1_xor = r1_row & Int32(7)\n r1_f4_0 = f4_base ^ r1_xor\n r1_f4_1 = (f4_base + Int32(1)) ^ r1_xor\n r1_row_base = (\n stage_base + warp_tile_base + r1_row * Int32(_TMA_COL_TILE)\n )\n r1_addr_0 = get_smem_ptr_as_int32(\n sData_flat, r1_row_base + r1_f4_0 * Int32(8)\n )\n r1_addr_1 = get_smem_ptr_as_int32(\n sData_flat, r1_row_base + r1_f4_1 * Int32(8)\n )\n r1_h0, r1_h1, r1_h2, r1_h3 = ld_shared_v4_u32(r1_addr_0)\n r1_h4, r1_h5, r1_h6, r1_h7 = ld_shared_v4_u32(r1_addr_1)\n\n # ---- Quantize and write: both row iterations ----\n # Global column base for SF index computation\n global_col_base = col_chunk * Int32(_TMA_COLS_PER_STAGE)\n sf_col = (global_col_base + base_col_in_stage) // Int32(\n NVFP4_SF_VEC_SIZE\n )\n\n # Row iteration 0\n global_row_0 = base_row + row_idx_local\n self._quantize_sf_block(\n r0_h0,\n r0_h1,\n r0_h2,\n r0_h3,\n r0_h4,\n r0_h5,\n r0_h6,\n r0_h7,\n global_row_0,\n sf_col,\n global_scale_value,\n M,\n padded_M,\n padded_sf_cols,\n mOutput,\n mScales,\n )\n\n # Row iteration 1\n global_row_1 = base_row + row_idx_local + Int32(self.ROWS_PER_WARP)\n self._quantize_sf_block(\n r1_h0,\n r1_h1,\n r1_h2,\n r1_h3,\n r1_h4,\n r1_h5,\n r1_h6,\n r1_h7,\n global_row_1,\n sf_col,\n global_scale_value,\n M,\n padded_M,\n padded_sf_cols,\n mOutput,\n mScales,\n )\n\n # ---- Release pipeline after all work (matches CUDA pattern) ----\n load_pipeline.consumer_release(consumer_state)\n consumer_state.advance()\n\n col_chunk = col_chunk + Int32(1)\n\n # Zero padding SF columns for swizzled layouts\n if cutlass.const_expr(self.sf_layout != SF_LAYOUT_LINEAR):\n consumer_tid = (warp_idx - Int32(1)) * Int32(32) + lane_idx\n if consumer_tid < _TMA_ROW_TILE:\n pad_row_idx = base_row + consumer_tid\n if pad_row_idx < padded_M:\n padding_sf = Int32(num_sf_blocks_per_row)\n while padding_sf < padded_sf_cols:\n sf_offset = self._compute_sf_offset(\n pad_row_idx, padding_sf, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n padding_sf = padding_sf + Int32(1)\n\n row_tile_idx = row_tile_idx + grid_dim_x\n\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_launch_dependents()\n\n\n# =============================================================================\n# PyTorch Integration with TVM-FFI\n# =============================================================================\n\n\ndef _kernel_source_files() -> Tuple[str, ...]:\n \"\"\"Source files whose content invalidates the on-disk kernel cache.\"\"\"\n from ...cute_dsl import fp4_common\n from .. import quantization_cute_dsl_utils\n\n return (__file__, fp4_common.__file__, quantization_cute_dsl_utils.__file__)\n\n\n_CUTE_DSL_MODULE = \"nvfp4_quantize\"\n\n\ndef _nvfp4_kernel_name(\n variant: str,\n dtype_key: str,\n K: int,\n sf_layout: int,\n enable_pdl: bool,\n disable_fp4_quant_fast_math: bool,\n silu_and_mul: bool,\n nvfp4_4over6_config: NVFP44Over6Config | None = None,\n global_scale_is_tensor: bool = True,\n) -> str:\n \"\"\"Specialization name within the nvfp4_quantize module, encoding every\n parameter that affects codegen.\n \"\"\"\n name = f\"{variant}_{dtype_key}_k{K}_sf{sf_layout}_pdl{int(enable_pdl)}\"\n if not global_scale_is_tensor:\n name += \"_host_sf\"\n if silu_and_mul:\n name += \"_silu\"\n if disable_fp4_quant_fast_math:\n name += \"_nofastmath\"\n if nvfp4_4over6_config is not None:\n cfg = nvfp4_4over6_config\n err_mode = getattr(cfg.err_mode, \"name\", cfg.err_mode)\n name += f\"_4over6_{cfg.e4m3_max}_{err_mode}_{int(cfg.err_use_fast_math)}\"\n return name\n\n\n@functools.cache\ndef _get_compiled_kernel_nvfp4(\n dtype_key: str,\n K: int,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool = False,\n disable_fp4_quant_fast_math: bool = False,\n nvfp4_4over6_config: NVFP44Over6Config | None = None,\n silu_and_mul: bool = False,\n global_scale_is_tensor: bool = True,\n) -> Tuple[Callable, int]:\n \"\"\"\n Get or compile NVFP4 kernel with TVM-FFI.\n\n Cached by (K, dtype_key, sf_layout, pdl, silu_and_mul,\n global_scale_is_tensor) - M-agnostic, device-independent compilation.\n\n Args:\n dtype_key: One of \"float16\", \"bfloat16\", \"float8_e4m3fn\".\n silu_and_mul: When True, fuse silu(gate) * up; the input row is 2 * K\n wide (gate then up concatenated) while the output stays K wide.\n global_scale_is_tensor: Whether the global scale is passed as a device\n tensor or a host-side scalar kernel argument.\n\n Returns:\n For linear layout: (compiled_kernel, sf_blocks_per_tb)\n For swizzled layout: (compiled_kernel, rows_per_block)\n \"\"\"\n _dtype_map = {\n \"float16\": cutlass.Float16,\n \"bfloat16\": cutlass.BFloat16,\n \"float8_e4m3fn\": cutlass.Float8E4M3FN,\n }\n cutlass_dtype = _dtype_map[dtype_key]\n\n # Use symbolic M for dynamic batch sizes\n sym_m = cute.sym_int()\n sym_scale_size = cute.sym_int()\n\n # Fused inputs have 2*K columns; outputs remain K-wide.\n input_cols = 2 * K if silu_and_mul else K\n\n # Common fake tensors\n input_fake = cute.runtime.make_fake_compact_tensor(\n cutlass_dtype, (sym_m, input_cols), stride_order=(1, 0), assumed_align=16\n )\n output_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_m, K // 2), stride_order=(1, 0), assumed_align=16\n )\n scales_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_scale_size,), assumed_align=16\n )\n global_scale_fake = (\n cute.runtime.make_fake_compact_tensor(cutlass.Float32, (1,), assumed_align=4)\n if global_scale_is_tensor\n else Float32(1.0)\n )\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n\n if sf_layout == SF_LAYOUT_LINEAR:\n linear_obj = NVFP4QuantizeLinearKernel(\n cutlass_dtype,\n K,\n enable_pdl,\n disable_fp4_quant_fast_math,\n nvfp4_4over6_config,\n silu_and_mul=silu_and_mul,\n )\n\n compiled_kernel = build_and_load_cute_dsl_kernel(\n _CUTE_DSL_MODULE,\n _nvfp4_kernel_name(\n \"linear\",\n dtype_key,\n K,\n sf_layout,\n enable_pdl,\n disable_fp4_quant_fast_math,\n silu_and_mul,\n nvfp4_4over6_config,\n global_scale_is_tensor,\n ),\n lambda: cute.compile(\n linear_obj,\n input_fake,\n output_fake,\n scales_fake,\n Int32(1), # Dummy M\n Int32(1), # Dummy total_sf_blocks\n Int32(1), # Dummy num_blocks\n global_scale_fake,\n stream_fake,\n options=\"--enable-tvm-ffi\",\n ),\n extra_key_files=_kernel_source_files(),\n )\n\n return compiled_kernel, linear_obj.SF_BLOCKS_PER_TB\n else:\n swizzled_obj = NVFP4QuantizeSwizzledKernel(\n cutlass_dtype,\n K,\n sf_layout=sf_layout,\n enable_pdl=enable_pdl,\n disable_fp4_quant_fast_math=disable_fp4_quant_fast_math,\n nvfp4_4over6_config=nvfp4_4over6_config,\n silu_and_mul=silu_and_mul,\n )\n\n compiled_kernel = build_and_load_cute_dsl_kernel(\n _CUTE_DSL_MODULE,\n _nvfp4_kernel_name(\n \"swizzled\",\n dtype_key,\n K,\n sf_layout,\n enable_pdl,\n disable_fp4_quant_fast_math,\n silu_and_mul,\n nvfp4_4over6_config,\n global_scale_is_tensor,\n ),\n lambda: cute.compile(\n swizzled_obj,\n input_fake,\n output_fake,\n scales_fake,\n Int32(1), # Dummy M\n Int32(128), # Dummy padded_M\n Int32(1), # Dummy num_blocks\n global_scale_fake,\n stream_fake,\n options=\"--enable-tvm-ffi\",\n ),\n extra_key_files=_kernel_source_files(),\n )\n\n return compiled_kernel, swizzled_obj.rows_per_block\n\n\n@functools.cache\ndef _get_compiled_kernel_nvfp4_per_token(\n dtype_key: str,\n K: int,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool = False,\n disable_fp4_quant_fast_math: bool = False,\n nvfp4_4over6_config: NVFP44Over6Config | None = None,\n) -> Callable:\n _dtype_map = {\n \"float16\": cutlass.Float16,\n \"bfloat16\": cutlass.BFloat16,\n }\n cutlass_dtype = _dtype_map[dtype_key]\n\n sym_m = cute.sym_int()\n sym_scale_size = cute.sym_int()\n\n input_fake = cute.runtime.make_fake_compact_tensor(\n cutlass_dtype, (sym_m, K), stride_order=(1, 0), assumed_align=16\n )\n output_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_m, K // 2), stride_order=(1, 0), assumed_align=16\n )\n scales_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_scale_size,), assumed_align=16\n )\n per_token_scale_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32, (sym_m,), assumed_align=4\n )\n global_scale_inv_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32, (1,), assumed_align=4\n )\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n\n kernel_obj = NVFP4QuantizePerTokenKernel(\n cutlass_dtype,\n K,\n sf_layout=sf_layout,\n enable_pdl=enable_pdl,\n disable_fp4_quant_fast_math=disable_fp4_quant_fast_math,\n nvfp4_4over6_config=nvfp4_4over6_config,\n )\n\n return build_and_load_cute_dsl_kernel(\n _CUTE_DSL_MODULE,\n _nvfp4_kernel_name(\n \"per_token\",\n dtype_key,\n K,\n sf_layout,\n enable_pdl,\n disable_fp4_quant_fast_math,\n silu_and_mul=False,\n nvfp4_4over6_config=nvfp4_4over6_config,\n ),\n lambda: cute.compile(\n kernel_obj,\n input_fake,\n output_fake,\n scales_fake,\n per_token_scale_fake,\n Int32(1),\n global_scale_inv_fake,\n stream_fake,\n options=\"--enable-tvm-ffi\",\n ),\n extra_key_files=_kernel_source_files(),\n )\n\n\n_TMA_MIN_M = 1024\n_TMA_LOG2_MK_THRESHOLD = 25\n\n\ndef _should_use_tma(m: int, k: int, dtype: torch.dtype) -> bool:\n \"\"\"TODO: disabled TMA for now due to perf sweep showing the vectorized-load\n kernel is as fast/at parity.\n\n Set ``FLASHINFER_NVFP4_QUANTIZE_USE_TMA=1`` to re-enable the heuristic for\n re-tuning on other hardware.\n \"\"\"\n if not _env_flag_enabled(\"FLASHINFER_NVFP4_QUANTIZE_USE_TMA\"):\n return False\n if dtype == torch.float8_e4m3fn:\n return False\n if k % _TMA_COLS_PER_STAGE != 0:\n return False\n if m < _TMA_MIN_M:\n return False\n # Use log2(M) + log2(K) threshold for the crossover point\n return m.bit_length() - 1 + k.bit_length() - 1 >= _TMA_LOG2_MK_THRESHOLD\n\n\n@functools.cache\ndef _get_compiled_kernel_nvfp4_tma(\n dtype_key: str,\n K: int,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool = False,\n disable_fp4_quant_fast_math: bool = False,\n global_scale_is_tensor: bool = True,\n) -> Tuple[Callable, int]:\n \"\"\"\n Get or compile TMA-based NVFP4 kernel with TVM-FFI.\n\n Cached by (K, dtype_key, sf_layout, pdl, global_scale_is_tensor).\n \"\"\"\n _dtype_map = {\n \"float16\": cutlass.Float16,\n \"bfloat16\": cutlass.BFloat16,\n }\n cutlass_dtype = _dtype_map[dtype_key]\n kernel_obj = NVFP4QuantizeTMAKernel(\n cutlass_dtype,\n K,\n sf_layout=sf_layout,\n enable_pdl=enable_pdl,\n disable_fp4_quant_fast_math=disable_fp4_quant_fast_math,\n )\n\n sym_m = cute.sym_int()\n\n input_fake = cute.runtime.make_fake_compact_tensor(\n cutlass_dtype, (sym_m, K), stride_order=(1, 0), assumed_align=16\n )\n output_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_m, K // 2), stride_order=(1, 0), assumed_align=16\n )\n sym_scale_size = cute.sym_int()\n scales_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_scale_size,), assumed_align=16\n )\n global_scale_fake = (\n cute.runtime.make_fake_compact_tensor(cutlass.Float32, (1,), assumed_align=4)\n if global_scale_is_tensor\n else Float32(1.0)\n )\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n\n compiled_kernel = build_and_load_cute_dsl_kernel(\n _CUTE_DSL_MODULE,\n _nvfp4_kernel_name(\n \"tma\",\n dtype_key,\n K,\n sf_layout,\n enable_pdl,\n disable_fp4_quant_fast_math,\n silu_and_mul=False,\n global_scale_is_tensor=global_scale_is_tensor,\n ),\n lambda: cute.compile(\n kernel_obj,\n input_fake,\n output_fake,\n scales_fake,\n Int32(1), # Dummy M\n Int32(1024), # Dummy padded_M\n Int32(1), # Dummy num_blocks\n global_scale_fake,\n stream_fake,\n options=\"--enable-tvm-ffi\",\n ),\n extra_key_files=_kernel_source_files(),\n )\n\n return compiled_kernel, kernel_obj.rows_per_block\n\n\n@flashinfer_api\ndef nvfp4_quantize_cute_dsl(\n input: torch.Tensor,\n global_scale: float | torch.Tensor,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool | None = None,\n) -> Tuple[torch.Tensor, torch.Tensor]:\n r\"\"\"Quantize input tensor to NVFP4 format using the CuTe-DSL kernel.\n\n GPU implementation matching :func:`flashinfer.quantization.nvfp4_quantize`:\n\n - E4M3 scale factors (FP8)\n - E2M1 output format (4-bit, 2 values per byte)\n - Supports 128x4, 8x4, and linear scale-factor layouts\n - ``sf_vec_size = 16``\n\n The kernel is compiled separately for host-scalar and device-tensor\n global scales and handles varying ``M`` (batch size) at runtime without\n recompilation.\n\n Parameters\n ----------\n input : torch.Tensor\n Input tensor of shape ``[M, K]`` with dtype\n fp16/bf16/float8_e4m3fn.\n global_scale : float or torch.Tensor\n Host-side NVFP4 global scale factor. A single-element tensor is also\n accepted for backward compatibility.\n sf_layout : int\n Scale-factor layout (``0=128x4``, ``1=8x4``, ``2=linear``).\n enable_pdl : bool, optional\n Whether to enable Programmatic Dependent Launch. Auto-detected\n from device capability (SM >= 9.0) when ``None``.\n\n Returns\n -------\n Tuple[torch.Tensor, torch.Tensor]\n ``(fp4_tensor, scale_tensor)`` where ``fp4_tensor`` is the\n quantized tensor of shape ``[M, K/2]`` with dtype ``uint8`` and\n ``scale_tensor`` holds the E4M3 scale factors (``uint8``) reshaped\n to ``[padded_rows, K/16]``.\n \"\"\"\n from ...utils import device_support_pdl\n\n _valid_sf_layouts = (SF_LAYOUT_128x4, SF_LAYOUT_8x4, SF_LAYOUT_LINEAR)\n assert sf_layout in _valid_sf_layouts, (\n f\"sf_layout must be one of {_valid_sf_layouts}, got {sf_layout}\"\n )\n _supported_dtypes = (torch.float16, torch.bfloat16, torch.float8_e4m3fn)\n assert input.dtype in _supported_dtypes, (\n f\"Input dtype must be one of {_supported_dtypes}, got {input.dtype}\"\n )\n assert input.is_cuda, \"Input must be on CUDA device\"\n\n enable_pdl = device_support_pdl(input.device) if enable_pdl is not False else False\n\n if input.dim() > 2:\n m = input.numel() // input.shape[-1]\n k = input.shape[-1]\n input = input.reshape(m, k)\n else:\n m, k = input.shape\n\n assert k % NVFP4_SF_VEC_SIZE == 0, (\n f\"K ({k}) must be divisible by NVFP4_SF_VEC_SIZE={NVFP4_SF_VEC_SIZE}\"\n )\n\n input = input.contiguous()\n\n _torch_to_dtype_key = {\n torch.float16: \"float16\",\n torch.bfloat16: \"bfloat16\",\n torch.float8_e4m3fn: \"float8_e4m3fn\",\n }\n dtype_key = _torch_to_dtype_key[input.dtype]\n\n # Never call .item() on a device scale: that would synchronize the stream\n # and make this path illegal during CUDA graph capture.\n global_scale_is_tensor = isinstance(global_scale, torch.Tensor)\n if global_scale_is_tensor:\n global_scale_arg = (\n cast(torch.Tensor, global_scale)\n .float()\n .reshape(1)\n .contiguous()\n .to(input.device)\n )\n else:\n global_scale_arg = float(global_scale)\n\n num_sm = get_num_sm(input.device)\n\n num_sf_blocks_per_row = k // NVFP4_SF_VEC_SIZE\n\n disable_fp4_quant_fast_math = _env_flag_enabled(\n \"FLASHINFER_DISABLE_FP4_QUANT_FAST_MATH\"\n )\n nvfp4_4over6_config = current_nvfp4_4over6_config()\n if nvfp4_4over6_config is not None and input.dtype == torch.float8_e4m3fn:\n raise ValueError(\"FLASHINFER_NVFP4_4OVER6 requires fp16 or bf16 input\")\n use_tma = _should_use_tma(m, k, input.dtype) and nvfp4_4over6_config is None\n\n if use_tma:\n tma_row_tile = _TMA_ROW_TILE\n if sf_layout == SF_LAYOUT_LINEAR:\n padded_m = _round_up(m, tma_row_tile)\n padded_sf_cols = num_sf_blocks_per_row\n elif sf_layout == SF_LAYOUT_8x4:\n padded_m = _round_up(m, max(tma_row_tile, 8))\n padded_sf_cols = ((num_sf_blocks_per_row + 3) // 4) * 4\n else:\n padded_m = _round_up(m, max(tma_row_tile, ROW_TILE_SIZE))\n padded_sf_cols = ((num_sf_blocks_per_row + 3) // 4) * 4\n\n scale_output_size = padded_m * padded_sf_cols\n\n kernel_fn, rows_per_block = _get_compiled_kernel_nvfp4_tma(\n dtype_key,\n k,\n sf_layout,\n enable_pdl,\n disable_fp4_quant_fast_math,\n global_scale_is_tensor,\n )\n\n # Match CUDA TMA kernel: grid = min(row_tiles, SM_count * 2)\n tma_target_grid = num_sm * 2\n num_blocks = min(\n (padded_m + rows_per_block - 1) // rows_per_block, tma_target_grid\n )\n\n fp4_output = torch.empty(m, k // 2, dtype=torch.uint8, device=input.device)\n scale_output = torch.empty(\n scale_output_size, dtype=torch.uint8, device=input.device\n )\n\n kernel_fn(\n input,\n fp4_output,\n scale_output,\n m,\n padded_m,\n num_blocks,\n global_scale_arg,\n )\n\n if sf_layout == SF_LAYOUT_LINEAR:\n scale_output = scale_output[: m * num_sf_blocks_per_row]\n\n # Reshape using padded_sf_cols for swizzled layouts (the buffer is\n # physically padded and stores data in swizzled order). For linear\n # layout the padding is already trimmed above.\n scale_output = scale_output.reshape(-1, padded_sf_cols)\n\n return fp4_output, scale_output\n\n # Non-TMA path: dual-path dispatch\n # Get or compile kernel (device-independent)\n kernel_fn, block_unit = _get_compiled_kernel_nvfp4(\n dtype_key,\n k,\n sf_layout,\n enable_pdl,\n disable_fp4_quant_fast_math,\n nvfp4_4over6_config,\n global_scale_is_tensor=global_scale_is_tensor,\n )\n\n target_grid = num_sm * _BLOCKS_PER_SM\n\n if sf_layout == SF_LAYOUT_LINEAR:\n padded_m = m\n padded_sf_cols = num_sf_blocks_per_row\n total_sf_blocks = m * num_sf_blocks_per_row\n scale_output_size = total_sf_blocks\n\n sf_blocks_per_tb = block_unit\n num_blocks = min(\n (total_sf_blocks + sf_blocks_per_tb - 1) // sf_blocks_per_tb,\n target_grid,\n )\n\n fp4_output = torch.empty(m, k // 2, dtype=torch.uint8, device=input.device)\n scale_output = torch.empty(\n scale_output_size, dtype=torch.uint8, device=input.device\n )\n\n kernel_fn(\n input,\n fp4_output,\n scale_output,\n m,\n total_sf_blocks,\n num_blocks,\n global_scale_arg,\n )\n else:\n if sf_layout == SF_LAYOUT_8x4:\n row_tile_size = 8\n else:\n row_tile_size = ROW_TILE_SIZE # 128\n padded_m = ((m + row_tile_size - 1) // row_tile_size) * row_tile_size\n padded_sf_cols = ((num_sf_blocks_per_row + 3) // 4) * 4\n scale_output_size = padded_m * padded_sf_cols\n\n rows_per_block = block_unit\n num_blocks = min(\n (padded_m + rows_per_block - 1) // rows_per_block,\n target_grid,\n )\n\n fp4_output = torch.empty(m, k // 2, dtype=torch.uint8, device=input.device)\n scale_output = torch.empty(\n scale_output_size, dtype=torch.uint8, device=input.device\n )\n\n kernel_fn(\n input,\n fp4_output,\n scale_output,\n m,\n padded_m,\n num_blocks,\n global_scale_arg,\n )\n\n # Reshape using padded_sf_cols: for swizzled layouts the buffer includes\n # column padding; for linear layout padded_sf_cols == num_sf_blocks_per_row.\n scale_output = scale_output.reshape(-1, padded_sf_cols)\n\n return fp4_output, scale_output\n\n\ndef silu_and_mul_nvfp4_quantize_cute_dsl(\n input: torch.Tensor,\n global_scale: torch.Tensor,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool | None = None,\n) -> Tuple[torch.Tensor, torch.Tensor]:\n r\"\"\"Apply SwiGLU and NVFP4 quantization using CuTe-DSL.\n\n Computes ``silu(input[..., :K]) * input[..., K:]`` before quantization.\n\n Parameters\n ----------\n input : torch.Tensor\n FP16/BF16 tensor of shape ``[..., 2K]``. Leading dimensions are\n flattened into M.\n global_scale : torch.Tensor\n Float32 scale of shape ``[1]``.\n sf_layout : int\n Scale layout: 0 for 128x4, 1 for 8x4, or 2 for linear.\n enable_pdl : bool, optional\n Enable Programmatic Dependent Launch. Auto-detected when None.\n\n Returns\n -------\n Tuple[torch.Tensor, torch.Tensor]\n Packed FP4 values of shape ``[M, K/2]`` and their uint8 E4M3 scales.\n \"\"\"\n from ...utils import device_support_pdl\n\n _valid_sf_layouts = (SF_LAYOUT_128x4, SF_LAYOUT_8x4, SF_LAYOUT_LINEAR)\n assert sf_layout in _valid_sf_layouts, (\n f\"sf_layout must be one of {_valid_sf_layouts}, got {sf_layout}\"\n )\n _supported_dtypes = (torch.float16, torch.bfloat16)\n assert input.dtype in _supported_dtypes, (\n f\"SwiGLU NVFP4 input dtype must be one of {_supported_dtypes}, \"\n f\"got {input.dtype}\"\n )\n assert input.is_cuda, \"Input must be on CUDA device\"\n\n enable_pdl = device_support_pdl(input.device) if enable_pdl is not False else False\n\n # Flatten leading dimensions into M.\n input_cols = input.shape[-1]\n assert input_cols % 2 == 0, (\n \"the last dimension must be even (gate and up concatenated)\"\n )\n k = input_cols // 2\n assert k % NVFP4_SF_VEC_SIZE == 0, (\n f\"K ({k}) must be divisible by NVFP4_SF_VEC_SIZE={NVFP4_SF_VEC_SIZE}\"\n )\n # Multiply leading dimensions so zero-width inputs remain valid.\n m = 1\n for dim in input.shape[:-1]:\n m *= int(dim)\n\n # Return empty outputs without compiling or launching.\n if m == 0 or k == 0:\n num_sf_blocks_per_row = k // NVFP4_SF_VEC_SIZE\n if sf_layout == SF_LAYOUT_LINEAR:\n padded_sf_cols = num_sf_blocks_per_row\n else:\n padded_sf_cols = ((num_sf_blocks_per_row + 3) // 4) * 4\n return (\n torch.empty((m, k // 2), dtype=torch.uint8, device=input.device),\n torch.empty((m, padded_sf_cols), dtype=torch.uint8, device=input.device),\n )\n\n input = input.reshape(m, input_cols)\n input = input.contiguous()\n # Clone storage-offset views that violate the kernel's 16-byte alignment.\n if input.data_ptr() % 16 != 0:\n input = input.clone()\n\n _torch_to_dtype_key = {\n torch.float16: \"float16\",\n torch.bfloat16: \"bfloat16\",\n }\n dtype_key = _torch_to_dtype_key[input.dtype]\n\n if isinstance(global_scale, torch.Tensor):\n global_scale_tensor = (\n global_scale.float().reshape(1).contiguous().to(input.device)\n )\n else:\n global_scale_tensor = torch.tensor(\n [float(global_scale)], dtype=torch.float32, device=input.device\n )\n\n num_sm = get_num_sm(input.device)\n num_sf_blocks_per_row = k // NVFP4_SF_VEC_SIZE\n\n disable_fp4_quant_fast_math = _env_flag_enabled(\n \"FLASHINFER_DISABLE_FP4_QUANT_FAST_MATH\"\n )\n nvfp4_4over6_config = current_nvfp4_4over6_config()\n\n # SwiGLU fusion uses the non-TMA vectorized-load kernels only.\n kernel_fn, block_unit = _get_compiled_kernel_nvfp4(\n dtype_key,\n k,\n sf_layout,\n enable_pdl,\n disable_fp4_quant_fast_math,\n nvfp4_4over6_config,\n silu_and_mul=True,\n )\n\n target_grid = num_sm * _BLOCKS_PER_SM\n\n if sf_layout == SF_LAYOUT_LINEAR:\n padded_sf_cols = num_sf_blocks_per_row\n total_sf_blocks = m * num_sf_blocks_per_row\n scale_output_size = total_sf_blocks\n\n sf_blocks_per_tb = block_unit\n num_blocks = min(\n (total_sf_blocks + sf_blocks_per_tb - 1) // sf_blocks_per_tb,\n target_grid,\n )\n\n fp4_output = torch.empty(m, k // 2, dtype=torch.uint8, device=input.device)\n scale_output = torch.empty(\n scale_output_size, dtype=torch.uint8, device=input.device\n )\n\n kernel_fn(\n input,\n fp4_output,\n scale_output,\n m,\n total_sf_blocks,\n num_blocks,\n global_scale_tensor,\n )\n else:\n if sf_layout == SF_LAYOUT_8x4:\n row_tile_size = 8\n else:\n row_tile_size = ROW_TILE_SIZE # 128\n padded_m = ((m + row_tile_size - 1) // row_tile_size) * row_tile_size\n padded_sf_cols = ((num_sf_blocks_per_row + 3) // 4) * 4\n scale_output_size = padded_m * padded_sf_cols\n\n rows_per_block = block_unit\n num_blocks = min(\n (padded_m + rows_per_block - 1) // rows_per_block,\n target_grid,\n )\n\n fp4_output = torch.empty(m, k // 2, dtype=torch.uint8, device=input.device)\n scale_output = torch.empty(\n scale_output_size, dtype=torch.uint8, device=input.device\n )\n\n kernel_fn(\n input,\n fp4_output,\n scale_output,\n m,\n padded_m,\n num_blocks,\n global_scale_tensor,\n )\n\n # Return scales in their layout-specific 2D shape.\n scale_output = scale_output.reshape(-1, padded_sf_cols)\n\n return fp4_output, scale_output\n\n\n@flashinfer_api\ndef nvfp4_quantize_per_token_cute_dsl(\n input: torch.Tensor,\n global_scale_inv: torch.Tensor,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool | None = None,\n) -> Tuple[torch.Tensor, torch.Tensor, torch.Tensor]:\n r\"\"\"Per-token NVFP4 activation quantization using the CuTe-DSL kernel.\n\n Unlike :func:`nvfp4_quantize_cute_dsl`, which applies a single global\n scale, this variant computes one quantization scale **per row (token)** of\n the activation. Each row is scaled independently so that its largest\n magnitude maps to the NVFP4 dynamic range, and the resulting per-token\n scale is returned alongside the packed FP4 output and the E4M3 block\n scale factors.\n\n - E4M3 block scale factors (FP8), ``sf_vec_size = 16``\n - E2M1 output format (4-bit, 2 values per byte)\n - Supports 128x4, 8x4, and linear scale-factor layouts\n\n The kernel is compiled once per ``(K, dtype, sf_layout, pdl)`` tuple and\n handles varying ``M`` (number of tokens) at runtime without recompilation.\n\n Parameters\n ----------\n input : torch.Tensor\n 2-D activation tensor of shape ``[M, K]`` with dtype fp16/bf16. ``K``\n must be divisible by ``NVFP4_SF_VEC_SIZE`` (16).\n global_scale_inv : torch.Tensor\n Scalar tensor (``float32``) holding the inverse global scale applied on\n top of the per-token scale. A Python ``float`` is also accepted and\n wrapped into a tensor internally.\n sf_layout : int\n Scale-factor layout (``0=128x4``, ``1=8x4``, ``2=linear``).\n enable_pdl : bool, optional\n Whether to enable Programmatic Dependent Launch. Auto-detected from\n device capability (SM >= 9.0) when ``None``; pass ``False`` to force it\n off.\n\n Returns\n -------\n Tuple[torch.Tensor, torch.Tensor, torch.Tensor]\n ``(fp4_output, scale_output, per_token_scale)`` where:\n\n - ``fp4_output`` is the packed quantized tensor of shape ``[M, K/2]``\n with dtype ``uint8`` (two E2M1 values per byte).\n - ``scale_output`` holds the E4M3 block scale factors (``uint8``)\n reshaped to ``[padded_rows, padded_sf_cols]``. The padding depends on\n ``sf_layout``: ``linear`` keeps ``M`` rows, while ``128x4`` / ``8x4``\n pad rows and columns up to the layout tile.\n - ``per_token_scale`` is the per-row quantization scale of shape\n ``[M]`` with dtype ``float32``.\n \"\"\"\n from ...utils import device_support_pdl\n\n _valid_sf_layouts = (SF_LAYOUT_128x4, SF_LAYOUT_8x4, SF_LAYOUT_LINEAR)\n assert sf_layout in _valid_sf_layouts, (\n f\"sf_layout must be one of {_valid_sf_layouts}, got {sf_layout}\"\n )\n _supported_dtypes = (torch.float16, torch.bfloat16)\n assert input.dtype in _supported_dtypes, (\n f\"Per-token NVFP4 input dtype must be one of {_supported_dtypes}, got {input.dtype}\"\n )\n assert input.is_cuda, \"Input must be on CUDA device\"\n assert input.dim() == 2, \"Per-token NVFP4 quantization expects a 2D input\"\n\n enable_pdl = device_support_pdl(input.device) if enable_pdl is not False else False\n input = input.contiguous()\n m, k = input.shape\n assert k % NVFP4_SF_VEC_SIZE == 0, (\n f\"K ({k}) must be divisible by NVFP4_SF_VEC_SIZE={NVFP4_SF_VEC_SIZE}\"\n )\n\n _torch_to_dtype_key = {\n torch.float16: \"float16\",\n torch.bfloat16: \"bfloat16\",\n }\n dtype_key = _torch_to_dtype_key[input.dtype]\n\n if isinstance(global_scale_inv, torch.Tensor):\n global_scale_inv_tensor = (\n global_scale_inv.float().reshape(1).contiguous().to(input.device)\n )\n else:\n global_scale_inv_tensor = torch.tensor(\n [float(global_scale_inv)], dtype=torch.float32, device=input.device\n )\n\n num_sf_blocks_per_row = k // NVFP4_SF_VEC_SIZE\n if sf_layout == SF_LAYOUT_LINEAR:\n padded_m = m\n padded_sf_cols = num_sf_blocks_per_row\n elif sf_layout == SF_LAYOUT_8x4:\n padded_m = _round_up(m, 8)\n padded_sf_cols = ((num_sf_blocks_per_row + 3) // 4) * 4\n else:\n padded_m = _round_up(m, ROW_TILE_SIZE)\n padded_sf_cols = ((num_sf_blocks_per_row + 3) // 4) * 4\n\n disable_fp4_quant_fast_math = _env_flag_enabled(\n \"FLASHINFER_DISABLE_FP4_QUANT_FAST_MATH\"\n )\n nvfp4_4over6_config = current_nvfp4_4over6_config()\n\n kernel_fn = _get_compiled_kernel_nvfp4_per_token(\n dtype_key,\n k,\n sf_layout,\n enable_pdl,\n disable_fp4_quant_fast_math,\n nvfp4_4over6_config,\n )\n\n fp4_output = torch.empty(m, k // 2, dtype=torch.uint8, device=input.device)\n scale_output = torch.zeros(\n padded_m * padded_sf_cols, dtype=torch.uint8, device=input.device\n )\n per_token_scale = torch.empty(m, dtype=torch.float32, device=input.device)\n\n kernel_fn(\n input,\n fp4_output,\n scale_output,\n per_token_scale,\n m,\n global_scale_inv_tensor,\n )\n\n scale_output = scale_output.reshape(-1, padded_sf_cols)\n return fp4_output, scale_output, per_token_scale\n\n\n__all__ = [\n \"SF_LAYOUT_128x4\",\n \"SF_LAYOUT_8x4\",\n \"SF_LAYOUT_LINEAR\",\n \"NVFP4QuantizeLinearKernel\",\n \"NVFP4QuantizeSwizzledKernel\",\n \"NVFP4QuantizePerTokenKernel\",\n \"NVFP4QuantizeTMAKernel\",\n \"nvfp4_quantize_cute_dsl\",\n \"silu_and_mul_nvfp4_quantize_cute_dsl\",\n \"nvfp4_quantize_per_token_cute_dsl\",\n \"_get_compiled_kernel_nvfp4\",\n \"_get_compiled_kernel_nvfp4_per_token\",\n \"_get_compiled_kernel_nvfp4_tma\",\n]\n"},"diff":{"kind":"string","value":"--- flashinfer/quantization/kernels/nvfp4_quantize.py\n+++ flashinfer/quantization/kernels/nvfp4_quantize.py\n@@ -1065,13 +1065,12 @@\n global_scale: Union[Float32, cute.Tensor],\n stream,\n ):\n- # 3D global tensor: [padded_M, K/64, 64] so each warp's 64-col\n- # stripe is the contiguous innermost dimension, matching the CUDA\n- # TMA kernel's 3D tensor map.\n+ # TMA zero-fills rows beyond the physical input extent while the kernel\n+ # visits padded_M rows required by the scale layout.\n gInput = cute.make_tensor(\n mInput.iterator,\n cute.make_layout(\n- (padded_M, self.K // _TMA_COL_TILE, _TMA_COL_TILE),\n+ (M, self.K // _TMA_COL_TILE, _TMA_COL_TILE),\n stride=(self.K, _TMA_COL_TILE, 1),\n ),\n )\n@@ -1721,10 +1720,9 @@\n )\n \n sym_m = cute.sym_int()\n- sym_padded_m = cute.sym_int()\n \n input_fake = cute.runtime.make_fake_compact_tensor(\n- cutlass_dtype, (sym_padded_m, K), stride_order=(1, 0), assumed_align=16\n+ cutlass_dtype, (sym_m, K), stride_order=(1, 0), assumed_align=16\n )\n output_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_m, K // 2), stride_order=(1, 0), assumed_align=16\n@@ -1901,20 +1899,13 @@\n (padded_m + rows_per_block - 1) // rows_per_block, tma_target_grid\n )\n \n- input_padded = input\n- if padded_m > m:\n- input_padded = torch.zeros(\n- padded_m, k, dtype=input.dtype, device=input.device\n- )\n- input_padded[:m, :] = input\n-\n fp4_output = torch.empty(m, k // 2, dtype=torch.uint8, device=input.device)\n scale_output = torch.empty(\n scale_output_size, dtype=torch.uint8, device=input.device\n )\n \n kernel_fn(\n- input_padded,\n+ input,\n fp4_output,\n scale_output,\n m,"},"lines_added":{"kind":"number","value":5,"string":"5"},"lines_removed":{"kind":"number","value":14,"string":"14"},"files_in_commit":{"kind":"number","value":1,"string":"1"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["B200"],"string":"[\n \"B200\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cute_dsl kernel file from flashinfer (flashinfer/quantization/kernels/nvfp4_quantize.py).\n\nGoal: perf: remove NVFP4 TMA input padding copy\nTarget hardware: B200\nTarget models: unspecified\n\nCurrent file:\n```python\n\"\"\"\nCopyright (c) 2025 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nNVFP4 Quantization using CuTe-DSL\n=================================\n\nNVFP4 quantization kernel using CuTe-DSL.\nSupports multiple scale factor layouts: swizzled 128x4, swizzled 8x4, and linear.\n\nDual-path optimization following the MXFP4 pattern:\n- Linear layout: flat SF-block iteration for 100% thread utilization\n- Swizzled layout: row-based iteration with multi-row / column-loop paths\n\nKey differences from MXFP4:\n- sf_vec_size=16 (vs 32 for MXFP4)\n- E4M3 scale factors (vs UE8M0 for MXFP4)\n- User-provided global_scale (vs auto-computed for MXFP4)\n- 3 layouts: 128x4, 8x4, linear (vs 128x4, linear for MXFP4)\n\"\"\"\n\nimport functools\nfrom typing import Callable, Tuple, Union, cast\n\nimport cutlass\nimport cutlass.cute as cute\nimport cutlass.cute.nvgpu.cpasync as cpasync\nimport cutlass.pipeline as pipeline\nfrom cutlass.pipeline import pipeline_init_arrive, pipeline_init_wait\nimport torch\nfrom cutlass import Float32, Int32, Int64, Uint8\n\nfrom ...api_logging import flashinfer_api\nfrom ...jit.cute_dsl_core import build_and_load_cute_dsl_kernel\nfrom ...cute_dsl.fp4_common import (\n block_reduce,\n fdiv_rn,\n fmax_f32,\n fmin_f32,\n get_ptr_as_int64,\n ld_global_v4_u32,\n rcp_approx_ftz,\n st_global_u64,\n warp_reduce,\n)\nfrom ...cute_dsl.utils import get_num_sm\nfrom ..nvfp4_quantization_utils import (\n NVFP44Over6Config,\n current_nvfp4_4over6_config,\n env_flag_enabled as _env_flag_enabled,\n)\nfrom ..quantization_cute_dsl_utils import (\n FLOAT32_MAX,\n NVFP4_SF_VEC_SIZE,\n WARP_SIZE,\n ROW_TILE_SIZE,\n compute_sf_index_swizzled_128x4_gpu,\n compute_sf_index_swizzled_8x4_gpu,\n compute_sf_index_linear_gpu,\n half2_max_abs_8 as half2_max_abs_8_fn,\n bfloat2_max_abs_8 as bfloat2_max_abs_8_fn,\n hmax_reduce_to_f32,\n bfloat2_hmax_reduce_to_f32,\n half2x8_to_e2m1x16_packed,\n bfloat2x8_to_e2m1x16_packed,\n process_nvfp4_block_half,\n process_nvfp4_block_bfloat,\n process_nvfp4_block_fp8,\n process_nvfp4_silu_block_half,\n process_nvfp4_silu_block_bfloat,\n)\n\nSF_LAYOUT_128x4 = 0\nSF_LAYOUT_8x4 = 1\nSF_LAYOUT_LINEAR = 2\n\n# Blocks per SM for occupancy target\n_BLOCKS_PER_SM = 4\n\n# Maximum threads per block\n_MAX_THREADS_PER_BLOCK = 1024\n\n# Thread count bounds for swizzled kernel\n_MIN_THREADS = 128\n_MAX_THREADS = 512\n\n# Linear kernel: fixed 16 warps (512 threads), 1 SF block per thread\n_LINEAR_WARPS_PER_BLOCK = 16\n_LINEAR_SF_BLOCKS_PER_TB = _LINEAR_WARPS_PER_BLOCK * WARP_SIZE # 512\n\n\ndef _compute_optimal_threads(K: int) -> int:\n \"\"\"\n Compute optimal thread count for 100% utilization in the swizzled kernel.\n\n For NVFP4, each thread processes 1 SF block (16 elements), so:\n threads_per_row = K / 16\n\n We want num_threads to be a multiple of threads_per_row so that\n rows_per_block = num_threads / threads_per_row is an integer.\n\n We prefer LARGER thread counts (up to _MAX_THREADS) for better occupancy.\n\n If threads_per_row > _MAX_THREADS, we use _MAX_THREADS with a column loop.\n\n Args:\n K: Number of columns (must be divisible by 16)\n\n Returns:\n Optimal number of threads per block\n \"\"\"\n threads_per_row = K // NVFP4_SF_VEC_SIZE # K / 16\n\n if threads_per_row > _MAX_THREADS:\n # Column loop mode: use maximum threads\n return _MAX_THREADS\n\n # Find largest multiple of threads_per_row in [_MIN_THREADS, _MAX_THREADS]\n largest = (_MAX_THREADS // threads_per_row) * threads_per_row\n if largest >= _MIN_THREADS:\n return largest\n\n # If largest multiple is below _MIN_THREADS, use smallest valid one\n candidate = threads_per_row\n while candidate < _MIN_THREADS:\n candidate += threads_per_row\n if candidate <= _MAX_THREADS:\n return candidate\n\n # Fallback (shouldn't happen for reasonable K)\n return _MAX_THREADS\n\n\n@cute.jit\ndef _dispatch_process_nvfp4_block(\n row_input,\n elem_base: Int32,\n global_scale: Float32,\n row_amax: Float32,\n K: int,\n is_bfloat16: bool,\n is_fp8: bool,\n silu_and_mul: bool,\n disable_fp4_quant_fast_math: bool,\n nvfp4_4over6_config: NVFP44Over6Config | None,\n):\n \"\"\"Dispatch one NVFP4 block by dtype and optional SwiGLU fusion.\"\"\"\n if cutlass.const_expr(silu_and_mul):\n if cutlass.const_expr(is_bfloat16):\n return process_nvfp4_silu_block_bfloat(\n row_input,\n elem_base,\n Int32(K),\n global_scale,\n disable_fp4_quant_fast_math,\n nvfp4_4over6_config,\n row_amax,\n )\n else:\n return process_nvfp4_silu_block_half(\n row_input,\n elem_base,\n Int32(K),\n global_scale,\n disable_fp4_quant_fast_math,\n nvfp4_4over6_config,\n row_amax,\n )\n else:\n if cutlass.const_expr(is_fp8):\n return process_nvfp4_block_fp8(\n row_input, elem_base, global_scale, disable_fp4_quant_fast_math\n )\n elif cutlass.const_expr(is_bfloat16):\n return process_nvfp4_block_bfloat(\n row_input,\n elem_base,\n global_scale,\n disable_fp4_quant_fast_math,\n nvfp4_4over6_config,\n row_amax,\n )\n else:\n return process_nvfp4_block_half(\n row_input,\n elem_base,\n global_scale,\n disable_fp4_quant_fast_math,\n nvfp4_4over6_config,\n row_amax,\n )\n\n\n# =============================================================================\n# CuTe-DSL Kernel Class for Linear Layout — Flat SF-Block Iteration\n# =============================================================================\n\n\nclass NVFP4QuantizeLinearKernel:\n \"\"\"\n NVFP4 quantization kernel optimized for LINEAR layout.\n\n Uses flat SF-block iteration for efficient memory access. Row and\n column indices are derived from the flat SF index via integer division.\n\n No padding passes are needed since for linear layout:\n - padded_m == m (no row padding)\n - padded_sf_cols == num_sf_blocks_per_row (no column padding)\n\n This kernel is M-agnostic: M-dependent values are passed at runtime.\n Each thread handles one SF block (16 elements).\n \"\"\"\n\n WARPS_PER_BLOCK = _LINEAR_WARPS_PER_BLOCK\n SF_BLOCKS_PER_TB = _LINEAR_SF_BLOCKS_PER_TB\n\n def __init__(\n self,\n dtype: cutlass.Numeric,\n K: int,\n enable_pdl: bool = False,\n disable_fp4_quant_fast_math: bool = False,\n nvfp4_4over6_config: NVFP44Over6Config | None = None,\n silu_and_mul: bool = False,\n ):\n self.dtype = dtype\n self.K = K\n self.is_bfloat16 = dtype == cutlass.BFloat16\n self.is_fp8 = dtype == cutlass.Float8E4M3FN\n self.enable_pdl = enable_pdl\n self.disable_fp4_quant_fast_math = disable_fp4_quant_fast_math\n self.nvfp4_4over6_config = nvfp4_4over6_config\n # SwiGLU uses a 2*K-wide input and does not support FP8.\n self.silu_and_mul = silu_and_mul\n assert not (silu_and_mul and self.is_fp8), (\n \"SwiGLU fusion does not support fp8 input\"\n )\n\n assert K % NVFP4_SF_VEC_SIZE == 0\n self.num_sf_blocks_per_row = K // NVFP4_SF_VEC_SIZE\n\n @cute.jit\n def _process_block(\n self, row_input, elem_base: Int32, global_scale: Float32, row_amax: Float32\n ):\n \"\"\"Quantize one 16-element block, optionally fusing silu(gate) * up.\n\n For the SwiGLU path the up block sits self.K columns after the gate\n block in the same (2*K-wide) input row.\n \"\"\"\n return _dispatch_process_nvfp4_block(\n row_input,\n elem_base,\n global_scale,\n row_amax,\n self.K,\n self.is_bfloat16,\n self.is_fp8,\n self.silu_and_mul,\n self.disable_fp4_quant_fast_math,\n self.nvfp4_4over6_config,\n )\n\n @cute.jit\n def __call__(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n M: Int32,\n total_sf_blocks: Int32,\n num_blocks: Int32,\n global_scale: Union[Float32, cute.Tensor],\n stream,\n ):\n threads_per_block = self.WARPS_PER_BLOCK * WARP_SIZE\n\n self.kernel(mInput, mOutput, mScales, M, total_sf_blocks, global_scale).launch(\n grid=[num_blocks, 1, 1],\n block=[threads_per_block, 1, 1],\n max_number_threads=[_MAX_THREADS_PER_BLOCK, 1, 1],\n min_blocks_per_mp=_BLOCKS_PER_SM,\n stream=stream,\n use_pdl=self.enable_pdl,\n )\n\n @cute.kernel\n def kernel(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n M: Int32,\n total_sf_blocks: Int32,\n global_scale: Union[Float32, cute.Tensor],\n ):\n \"\"\"\n NVFP4 quantization with flat SF-block iteration for linear layout.\n\n Each thread handles one SF block (16 elements). Row and column\n indices are derived from the flat SF index.\n \"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n bidx, _, _ = cute.arch.block_idx()\n grid_dim_x, _, _ = cute.arch.grid_dim()\n\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_wait()\n\n # Device scales stay pointer-loaded; host scales arrive as launch arguments.\n if cutlass.const_expr(isinstance(global_scale, cute.Tensor)):\n global_scale_value = Float32(global_scale[Int32(0)])\n else:\n global_scale_value = global_scale\n row_amax = Float32(0.0)\n\n num_sf_blocks_per_row = self.num_sf_blocks_per_row\n sf_blocks_per_tb = self.SF_BLOCKS_PER_TB\n stride = grid_dim_x * sf_blocks_per_tb\n\n # Flat SF-block iteration\n sf_idx = bidx * sf_blocks_per_tb + tidx\n\n while sf_idx < total_sf_blocks:\n row_idx = sf_idx // num_sf_blocks_per_row\n col_idx = sf_idx % num_sf_blocks_per_row\n\n elem_base = col_idx * NVFP4_SF_VEC_SIZE\n row_input = mInput[row_idx, None]\n\n # Apply optional SwiGLU and quantize the block.\n scale_fp8, packed64 = self._process_block(\n row_input, elem_base, global_scale_value, row_amax\n )\n\n # Write scale factor using linear indexing\n sf_offset = compute_sf_index_linear_gpu(\n row_idx, col_idx, num_sf_blocks_per_row\n )\n mScales[sf_offset] = scale_fp8\n\n # Store 8 bytes (16 FP4 values = 1 x st.global.u64)\n row_output = mOutput[row_idx, None]\n out_base = col_idx * (NVFP4_SF_VEC_SIZE // 2)\n out_ptr = get_ptr_as_int64(row_output, out_base)\n st_global_u64(out_ptr, packed64)\n\n sf_idx = sf_idx + stride\n\n # PDL: Signal that dependent kernels can start early\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_launch_dependents()\n\n\n# =============================================================================\n# CuTe-DSL Kernel Class for Swizzled Layout — Row-Based Iteration\n# =============================================================================\n\n\nclass NVFP4QuantizeSwizzledKernel:\n \"\"\"\n NVFP4 quantization kernel optimized for SWIZZLED (128x4 or 8x4) layout.\n\n Key optimizations:\n - Multi-row processing: threads process multiple rows per block when K is small\n - Row-based iteration with grid-stride loop\n - Padding row fast path - only zero out scale factors\n\n Thread utilization optimization:\n - Dynamic thread count based on K for 100% thread utilization\n - For small K: Multiple rows processed per block iteration\n - For large K: Single row with column loop\n\n For NVFP4, each thread processes 1 SF block (16 elements) independently,\n so threads_per_row = num_sf_blocks_per_row = K/16.\n\n This kernel is M-agnostic: M-dependent values (M, padded_M) are passed\n at runtime.\n \"\"\"\n\n def __init__(\n self,\n dtype: cutlass.Numeric,\n K: int,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool = False,\n disable_fp4_quant_fast_math: bool = False,\n nvfp4_4over6_config: NVFP44Over6Config | None = None,\n silu_and_mul: bool = False,\n ):\n self.dtype = dtype\n self.K = K\n self.is_bfloat16 = dtype == cutlass.BFloat16\n self.is_fp8 = dtype == cutlass.Float8E4M3FN\n self.enable_pdl = enable_pdl\n self.disable_fp4_quant_fast_math = disable_fp4_quant_fast_math\n self.nvfp4_4over6_config = nvfp4_4over6_config\n self.sf_layout = sf_layout\n self.sf_is_128x4 = sf_layout == SF_LAYOUT_128x4\n self.sf_is_8x4 = sf_layout == SF_LAYOUT_8x4\n # SwiGLU uses a 2*K-wide input and does not support FP8.\n self.silu_and_mul = silu_and_mul\n assert not (silu_and_mul and self.is_fp8), (\n \"SwiGLU fusion does not support fp8 input\"\n )\n\n assert K % NVFP4_SF_VEC_SIZE == 0\n self.num_sf_blocks_per_row = K // NVFP4_SF_VEC_SIZE\n self.padded_sf_cols = ((self.num_sf_blocks_per_row + 3) // 4) * 4\n\n # Compute optimal thread count for 100% utilization\n self.num_threads = _compute_optimal_threads(K)\n self.threads_per_row = self.num_sf_blocks_per_row # 1 thread per SF block\n\n # Multi-row processing constants (compile-time)\n if self.threads_per_row <= self.num_threads:\n self.rows_per_block = self.num_threads // self.threads_per_row\n self.needs_col_loop = False\n else:\n self.rows_per_block = 1\n self.needs_col_loop = True\n\n @cute.jit\n def _compute_sf_offset(\n self, row_idx: Int32, col_idx: Int32, padded_cols: Int32\n ) -> Int32:\n \"\"\"Compute scale factor offset based on layout (compile-time dispatch).\"\"\"\n if cutlass.const_expr(self.sf_is_128x4):\n return compute_sf_index_swizzled_128x4_gpu(row_idx, col_idx, padded_cols)\n else:\n return compute_sf_index_swizzled_8x4_gpu(row_idx, col_idx, padded_cols)\n\n @cute.jit\n def _process_block(\n self, row_input, elem_base: Int32, global_scale: Float32, row_amax: Float32\n ):\n \"\"\"Quantize one 16-element block, optionally fusing silu(gate) * up.\n\n For the SwiGLU path the up block sits self.K columns after the gate\n block in the same (2*K-wide) input row.\n \"\"\"\n return _dispatch_process_nvfp4_block(\n row_input,\n elem_base,\n global_scale,\n row_amax,\n self.K,\n self.is_bfloat16,\n self.is_fp8,\n self.silu_and_mul,\n self.disable_fp4_quant_fast_math,\n self.nvfp4_4over6_config,\n )\n\n @cute.jit\n def __call__(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n M: Int32,\n padded_M: Int32,\n num_blocks: Int32,\n global_scale: Union[Float32, cute.Tensor],\n stream,\n ):\n self.kernel(mInput, mOutput, mScales, M, padded_M, global_scale).launch(\n grid=[num_blocks, 1, 1],\n block=[self.num_threads, 1, 1],\n max_number_threads=[_MAX_THREADS_PER_BLOCK, 1, 1],\n min_blocks_per_mp=_BLOCKS_PER_SM,\n stream=stream,\n use_pdl=self.enable_pdl,\n )\n\n @cute.kernel\n def kernel(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n M: Int32,\n padded_M: Int32,\n global_scale: Union[Float32, cute.Tensor],\n ):\n \"\"\"\n Row-based kernel for swizzled layout.\n\n When K is small: each block processes multiple rows simultaneously.\n When K is large: each block processes one row with column loop.\n \"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n bidx, _, _ = cute.arch.block_idx()\n grid_dim_x, _, _ = cute.arch.grid_dim()\n\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_wait()\n\n # Device scales stay pointer-loaded; host scales arrive as launch arguments.\n if cutlass.const_expr(isinstance(global_scale, cute.Tensor)):\n global_scale_value = Float32(global_scale[Int32(0)])\n else:\n global_scale_value = global_scale\n row_amax = Float32(0.0)\n\n # Compile-time constants\n num_sf_blocks_per_row = self.num_sf_blocks_per_row\n padded_sf_cols = self.padded_sf_cols\n threads_per_row = self.threads_per_row\n rows_per_block = self.rows_per_block\n\n if cutlass.const_expr(self.needs_col_loop):\n # Large K path: single row per block iteration with column loop\n # Each thread maps to one SF block; threads stride over columns\n num_threads = self.num_threads\n\n row_idx = bidx\n while row_idx < padded_M:\n is_padding_row = row_idx >= M\n\n if is_padding_row:\n # Fast path: padding row - only zero out scale factors\n sf_col_idx = tidx\n while sf_col_idx < padded_sf_cols:\n sf_offset = self._compute_sf_offset(\n row_idx, sf_col_idx, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n sf_col_idx = sf_col_idx + num_threads\n else:\n # Normal path: process actual data row with column loop\n sf_col_idx = tidx\n while sf_col_idx < num_sf_blocks_per_row:\n elem_base = sf_col_idx * NVFP4_SF_VEC_SIZE\n row_input = mInput[row_idx, None]\n\n # Apply optional SwiGLU and quantize the block.\n scale_fp8, packed64 = self._process_block(\n row_input, elem_base, global_scale_value, row_amax\n )\n\n # Write scale factor using swizzled indexing\n sf_offset = self._compute_sf_offset(\n row_idx, sf_col_idx, padded_sf_cols\n )\n mScales[sf_offset] = scale_fp8\n\n # Store 8 bytes (16 FP4 values = 1 x st.global.u64)\n row_output = mOutput[row_idx, None]\n out_base = sf_col_idx * (NVFP4_SF_VEC_SIZE // 2)\n out_ptr = get_ptr_as_int64(row_output, out_base)\n st_global_u64(out_ptr, packed64)\n\n sf_col_idx = sf_col_idx + num_threads\n\n # Handle padding columns for this row\n sf_col_idx = num_sf_blocks_per_row + tidx\n while sf_col_idx < padded_sf_cols:\n sf_offset = self._compute_sf_offset(\n row_idx, sf_col_idx, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n sf_col_idx = sf_col_idx + num_threads\n\n row_idx = row_idx + grid_dim_x\n else:\n # Small K path: multi-row processing\n # Thread mapping: tidx -> (row_in_block, sf_idx_in_row)\n row_in_block = tidx // threads_per_row\n sf_idx_in_row = tidx % threads_per_row\n\n # Grid-stride loop over row batches\n row_batch_idx = bidx\n # Initialize row_idx before while loop (CuTe DSL requires variables\n # modified in while loops to be defined before the loop)\n row_idx = row_batch_idx * rows_per_block + row_in_block\n while row_batch_idx * rows_per_block < padded_M:\n if row_idx < padded_M:\n is_padding_row = row_idx >= M\n\n if is_padding_row:\n # Fast path: padding row - zero out ALL padded_sf_cols\n # Thread-stride loop since padded_sf_cols may exceed\n # threads_per_row (e.g. K=32: threads_per_row=2,\n # padded_sf_cols=4)\n local_sf_idx = sf_idx_in_row\n while local_sf_idx < padded_sf_cols:\n sf_offset = self._compute_sf_offset(\n row_idx, local_sf_idx, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n local_sf_idx = local_sf_idx + threads_per_row\n else:\n # Normal path: process actual data\n if sf_idx_in_row < num_sf_blocks_per_row:\n elem_base = sf_idx_in_row * NVFP4_SF_VEC_SIZE\n row_input = mInput[row_idx, None]\n\n # Apply optional SwiGLU and quantize the block.\n scale_fp8, packed64 = self._process_block(\n row_input, elem_base, global_scale_value, row_amax\n )\n\n # Write scale factor using swizzled indexing\n sf_offset = self._compute_sf_offset(\n row_idx, sf_idx_in_row, padded_sf_cols\n )\n mScales[sf_offset] = scale_fp8\n\n # Store 8 bytes (16 FP4 values = 1 x st.global.u64)\n row_output = mOutput[row_idx, None]\n out_base = sf_idx_in_row * (NVFP4_SF_VEC_SIZE // 2)\n out_ptr = get_ptr_as_int64(row_output, out_base)\n st_global_u64(out_ptr, packed64)\n\n # Handle padding SF columns for this row\n # Thread-stride loop starting from first padding column\n if cutlass.const_expr(\n self.num_sf_blocks_per_row != self.padded_sf_cols\n ):\n pad_col = num_sf_blocks_per_row + sf_idx_in_row\n while pad_col < padded_sf_cols:\n sf_offset = self._compute_sf_offset(\n row_idx, pad_col, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n pad_col = pad_col + threads_per_row\n\n row_batch_idx = row_batch_idx + grid_dim_x\n # Update row_idx for next iteration\n row_idx = row_batch_idx * rows_per_block + row_in_block\n\n # PDL: Signal that dependent kernels can start early\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_launch_dependents()\n\n\n# =============================================================================\n# CuTe-DSL Kernel Class for Per-Token Activation Quantization\n# =============================================================================\n\n\n_PER_TOKEN_THREADS = 128\n_PER_TOKEN_WARPS = _PER_TOKEN_THREADS // WARP_SIZE\n\n\nclass NVFP4QuantizePerTokenKernel:\n \"\"\"\n One CTA per token row. The first pass reduces the row amax, then the\n second pass reuses the regular NVFP4 block quantizer with that row's\n global encode scale.\n \"\"\"\n\n def __init__(\n self,\n dtype: cutlass.Numeric,\n K: int,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool = False,\n disable_fp4_quant_fast_math: bool = False,\n nvfp4_4over6_config: NVFP44Over6Config | None = None,\n ):\n self.dtype = dtype\n self.K = K\n self.is_bfloat16 = dtype == cutlass.BFloat16\n self.enable_pdl = enable_pdl\n self.disable_fp4_quant_fast_math = disable_fp4_quant_fast_math\n self.nvfp4_4over6_config = nvfp4_4over6_config\n self.sf_layout = sf_layout\n self.sf_is_128x4 = sf_layout == SF_LAYOUT_128x4\n self.sf_is_8x4 = sf_layout == SF_LAYOUT_8x4\n\n assert dtype != cutlass.Float8E4M3FN, (\n \"per-token NVFP4 does not support FP8 input\"\n )\n assert K % NVFP4_SF_VEC_SIZE == 0\n self.num_sf_blocks_per_row = K // NVFP4_SF_VEC_SIZE\n if sf_layout == SF_LAYOUT_LINEAR:\n self.padded_sf_cols = self.num_sf_blocks_per_row\n else:\n self.padded_sf_cols = ((self.num_sf_blocks_per_row + 3) // 4) * 4\n\n @cute.jit\n def _compute_sf_offset(\n self, row_idx: Int32, col_idx: Int32, padded_cols: Int32\n ) -> Int32:\n if cutlass.const_expr(self.sf_is_128x4):\n return compute_sf_index_swizzled_128x4_gpu(row_idx, col_idx, padded_cols)\n else:\n if cutlass.const_expr(self.sf_is_8x4):\n return compute_sf_index_swizzled_8x4_gpu(row_idx, col_idx, padded_cols)\n else:\n return compute_sf_index_linear_gpu(row_idx, col_idx, padded_cols)\n\n @cute.jit\n def _row_scales(\n self, row_amax: Float32, global_scale_inv: Float32\n ) -> Tuple[Float32, Float32]:\n global_encode_scale = Float32(0.0)\n per_token_scale = Float32(0.0)\n if cutlass.const_expr(self.disable_fp4_quant_fast_math):\n global_scale = fdiv_rn(Float32(1.0), global_scale_inv)\n if row_amax == Float32(0.0):\n per_token_scale = Float32(0.0)\n if cutlass.const_expr(self.nvfp4_4over6_config is not None):\n global_encode_scale = Float32(0.0)\n else:\n global_encode_scale = Float32(FLOAT32_MAX)\n else:\n row_encode_scale = fmin_f32(\n fdiv_rn(global_scale, row_amax), Float32(FLOAT32_MAX)\n )\n if row_encode_scale != Float32(0.0):\n global_encode_scale = row_encode_scale\n else:\n global_encode_scale = Float32(1.0)\n per_token_scale = fdiv_rn(Float32(1.0), global_encode_scale)\n else:\n if row_amax == Float32(0.0):\n per_token_scale = Float32(0.0)\n if cutlass.const_expr(self.nvfp4_4over6_config is not None):\n global_encode_scale = Float32(0.0)\n else:\n global_encode_scale = Float32(FLOAT32_MAX)\n else:\n per_token_scale = row_amax * global_scale_inv\n global_encode_scale = rcp_approx_ftz(per_token_scale)\n return global_encode_scale, per_token_scale\n\n @cute.jit\n def __call__(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n mPerTokenScale: cute.Tensor,\n M: Int32,\n mGlobalScaleInv: cute.Tensor,\n stream,\n ):\n self.kernel(\n mInput, mOutput, mScales, mPerTokenScale, M, mGlobalScaleInv\n ).launch(\n grid=[M, 1, 1],\n block=[_PER_TOKEN_THREADS, 1, 1],\n max_number_threads=[_MAX_THREADS_PER_BLOCK, 1, 1],\n min_blocks_per_mp=_BLOCKS_PER_SM,\n stream=stream,\n use_pdl=self.enable_pdl,\n )\n\n @cute.kernel\n def kernel(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n mPerTokenScale: cute.Tensor,\n M: Int32,\n mGlobalScaleInv: cute.Tensor,\n ):\n tidx, _, _ = cute.arch.thread_idx()\n bidx, _, _ = cute.arch.block_idx()\n\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_wait()\n\n smem = cutlass.utils.SmemAllocator()\n reduction_buffer = smem.allocate_tensor(\n Float32,\n cute.make_layout((1, _PER_TOKEN_WARPS)),\n byte_alignment=4,\n )\n\n row_idx = bidx\n num_sf_blocks_per_row = self.num_sf_blocks_per_row\n padded_sf_cols = self.padded_sf_cols\n # Build the row views from 64-bit byte addresses. Slicing with\n # mInput[row_idx, None] computes the row offset row_idx * K in\n # Int32, which wraps once row_idx * K exceeds 2**31 - 1 (reached by\n # the MoE per-token intermediate, e.g. M=851456 x K=2688) and makes\n # the loads fault.\n input_row_addr = get_ptr_as_int64(mInput, Int32(0)) + Int64(row_idx) * Int64(\n self.K * (mInput.element_type.width // 8)\n )\n row_input = cute.make_tensor(\n cute.make_ptr(\n mInput.element_type,\n input_row_addr,\n cute.AddressSpace.gmem,\n assumed_align=16,\n ),\n cute.make_layout((self.K,)),\n )\n output_row_addr = get_ptr_as_int64(mOutput, Int32(0)) + Int64(row_idx) * Int64(\n self.K // 2\n )\n row_output = cute.make_tensor(\n cute.make_ptr(\n mOutput.element_type,\n output_row_addr,\n cute.AddressSpace.gmem,\n assumed_align=8,\n ),\n cute.make_layout((self.K // 2,)),\n )\n\n local_amax = Float32(0.0)\n sf_col_idx = tidx\n while sf_col_idx < num_sf_blocks_per_row:\n elem_base = sf_col_idx * NVFP4_SF_VEC_SIZE\n ptr0 = get_ptr_as_int64(row_input, elem_base)\n ptr1 = get_ptr_as_int64(row_input, elem_base + Int32(8))\n h0, h1, h2, h3 = ld_global_v4_u32(ptr0)\n h4, h5, h6, h7 = ld_global_v4_u32(ptr1)\n if cutlass.const_expr(self.is_bfloat16):\n block_max_h2 = bfloat2_max_abs_8_fn(h0, h1, h2, h3, h4, h5, h6, h7)\n block_max = bfloat2_hmax_reduce_to_f32(block_max_h2)\n else:\n block_max_h2 = half2_max_abs_8_fn(h0, h1, h2, h3, h4, h5, h6, h7)\n block_max = hmax_reduce_to_f32(block_max_h2)\n local_amax = fmax_f32(local_amax, block_max)\n sf_col_idx = sf_col_idx + Int32(_PER_TOKEN_THREADS)\n\n warp_amax = warp_reduce(local_amax, fmax_f32)\n row_amax = block_reduce(warp_amax, fmax_f32, reduction_buffer, Float32(0.0))\n global_scale_inv = Float32(mGlobalScaleInv[Int32(0)])\n global_encode_scale, per_token_scale = self._row_scales(\n row_amax, global_scale_inv\n )\n if tidx == Int32(0):\n mPerTokenScale[row_idx] = per_token_scale\n cute.arch.barrier()\n\n sf_col_idx = tidx\n while sf_col_idx < num_sf_blocks_per_row:\n elem_base = sf_col_idx * NVFP4_SF_VEC_SIZE\n if cutlass.const_expr(self.is_bfloat16):\n scale_fp8, packed64 = process_nvfp4_block_bfloat(\n row_input,\n elem_base,\n global_encode_scale,\n self.disable_fp4_quant_fast_math,\n self.nvfp4_4over6_config,\n row_amax,\n )\n else:\n scale_fp8, packed64 = process_nvfp4_block_half(\n row_input,\n elem_base,\n global_encode_scale,\n self.disable_fp4_quant_fast_math,\n self.nvfp4_4over6_config,\n row_amax,\n )\n\n sf_offset = self._compute_sf_offset(row_idx, sf_col_idx, padded_sf_cols)\n mScales[sf_offset] = scale_fp8\n\n out_base = sf_col_idx * Int32(NVFP4_SF_VEC_SIZE // 2)\n out_ptr = get_ptr_as_int64(row_output, out_base)\n st_global_u64(out_ptr, packed64)\n\n sf_col_idx = sf_col_idx + Int32(_PER_TOKEN_THREADS)\n\n if cutlass.const_expr(self.sf_layout != SF_LAYOUT_LINEAR):\n sf_col_idx = num_sf_blocks_per_row + tidx\n while sf_col_idx < padded_sf_cols:\n sf_offset = self._compute_sf_offset(row_idx, sf_col_idx, padded_sf_cols)\n mScales[sf_offset] = Uint8(0)\n sf_col_idx = sf_col_idx + Int32(_PER_TOKEN_THREADS)\n\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_launch_dependents()\n\n\n# =============================================================================\n# CuTe-DSL TMA Kernel Class for NVFP4\n# =============================================================================\n\n_TMA_ROW_TILE = 16\n_TMA_COL_TILE = 64 # Per-warp column tile\n_TMA_NUM_CONSUMER_WARPS = 8\n_TMA_NUM_STAGES = 4\n_TMA_COLS_PER_STAGE = _TMA_NUM_CONSUMER_WARPS * _TMA_COL_TILE # 512\n\n\ndef _round_up(x: int, d: int) -> int:\n return ((x + d - 1) // d) * d\n\n\nclass NVFP4QuantizeTMAKernel:\n \"\"\"\n TMA-based NVFP4 quantization kernel with pipelined producer-consumer\n warp specialization, matching the CUDA TMA kernel architecture.\n\n Architecture (matches csrc/nv_internal/.../quantization.cuh):\n - 1 producer warp (warp 0) issues TMA G2S loads into staged SMEM buffers\n - 8 consumer warps (warps 1-8) read from SMEM, quantize, write to GMEM\n - PipelineTmaAsync manages multi-stage buffering (4 stages)\n - Each TMA tile: [16, 512] = 16 rows x 8 warps x 64 cols per warp\n - Each consumer warp: 4 threads/row x 8 rows/warp, 2 row iterations\n - Each thread: 16 elements (1 SF block) via 2 x ld.shared.v4.u32\n - Grid-stride loop over row tiles, inner loop over K/512 col chunks\n\n Effective when M >= 1024 and K is a multiple of 512.\n \"\"\"\n\n def __init__(\n self,\n dtype: cutlass.Numeric,\n K: int,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool = False,\n disable_fp4_quant_fast_math: bool = False,\n ):\n self.dtype = dtype\n self.K = K\n self.is_bfloat16 = dtype == cutlass.BFloat16\n self.is_fp8 = dtype == cutlass.Float8E4M3FN\n self.enable_pdl = enable_pdl\n self.disable_fp4_quant_fast_math = disable_fp4_quant_fast_math\n self.sf_layout = sf_layout\n self.sf_is_128x4 = sf_layout == SF_LAYOUT_128x4\n self.sf_is_8x4 = sf_layout == SF_LAYOUT_8x4\n\n assert not self.is_fp8, \"FP8 input not yet supported for TMA kernel\"\n assert K % _TMA_COLS_PER_STAGE == 0, (\n f\"K ({K}) must be a multiple of {_TMA_COLS_PER_STAGE} for TMA kernel\"\n )\n\n self.num_sf_blocks_per_row = K // NVFP4_SF_VEC_SIZE\n self.num_col_chunks = K // _TMA_COLS_PER_STAGE\n\n if sf_layout == SF_LAYOUT_LINEAR:\n self.padded_sf_cols = self.num_sf_blocks_per_row\n elif sf_layout == SF_LAYOUT_8x4:\n self.padded_sf_cols = ((self.num_sf_blocks_per_row + 3) // 4) * 4\n else:\n self.padded_sf_cols = ((self.num_sf_blocks_per_row + 3) // 4) * 4\n\n self.num_consumer_warps = _TMA_NUM_CONSUMER_WARPS # 8\n self.num_stages = _TMA_NUM_STAGES\n self.producer_warp_id = 0 # Warp 0 is producer (matches CUDA kernel)\n self.threads_per_cta = 32 * (self.num_consumer_warps + 1) # 288\n self.rows_per_block = _TMA_ROW_TILE\n self.buffer_align_bytes = 1024\n self.cluster_shape_mn = (1, 1)\n self.elems_per_stage = _TMA_ROW_TILE * _TMA_COLS_PER_STAGE # 8192\n\n # Thread indexing constants (matches CUDA TmaKernelTraitsTwoBytes)\n self.THREADS_PER_ROW = 4 # laneIdx % 4\n self.ROWS_PER_WARP = 8 # 32 / 4\n self.ELTS_PER_THREAD = NVFP4_SF_VEC_SIZE # 16\n\n @cute.jit\n def _compute_sf_offset(\n self, row_idx: Int32, col_idx: Int32, padded_cols: Int32\n ) -> Int32:\n if cutlass.const_expr(self.sf_is_128x4):\n return compute_sf_index_swizzled_128x4_gpu(row_idx, col_idx, padded_cols)\n else:\n if cutlass.const_expr(self.sf_is_8x4):\n return compute_sf_index_swizzled_8x4_gpu(row_idx, col_idx, padded_cols)\n else:\n return compute_sf_index_linear_gpu(row_idx, col_idx, padded_cols)\n\n @cute.jit\n def _quantize_sf_block(\n self,\n h0: cutlass.Uint32,\n h1: cutlass.Uint32,\n h2: cutlass.Uint32,\n h3: cutlass.Uint32,\n h4: cutlass.Uint32,\n h5: cutlass.Uint32,\n h6: cutlass.Uint32,\n h7: cutlass.Uint32,\n global_row: Int32,\n sf_col: Int32,\n global_scale: Float32,\n M: Int32,\n padded_M: Int32,\n padded_sf_cols: Int32,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n ):\n \"\"\"Quantize one 16-element SF block and write results to GMEM.\"\"\"\n from ...cute_dsl.fp4_common import (\n cvt_f32_to_e4m3,\n nvfp4_compute_output_scale,\n nvfp4_compute_output_scale_rn,\n nvfp4_scale_from_amax_rn,\n rcp_approx_ftz,\n )\n\n if global_row < padded_M:\n is_padding_row = global_row >= M\n\n if is_padding_row:\n sf_offset = self._compute_sf_offset(global_row, sf_col, padded_sf_cols)\n mScales[sf_offset] = Uint8(0)\n else:\n if cutlass.const_expr(self.is_bfloat16):\n block_max_h2 = bfloat2_max_abs_8_fn(h0, h1, h2, h3, h4, h5, h6, h7)\n block_max = bfloat2_hmax_reduce_to_f32(block_max_h2)\n else:\n block_max_h2 = half2_max_abs_8_fn(h0, h1, h2, h3, h4, h5, h6, h7)\n block_max = hmax_reduce_to_f32(block_max_h2)\n\n if cutlass.const_expr(self.disable_fp4_quant_fast_math):\n scale_float = nvfp4_scale_from_amax_rn(block_max, global_scale)\n else:\n fp4_max_rcp = rcp_approx_ftz(Float32(6.0))\n scale_float = global_scale * (block_max * fp4_max_rcp)\n scale_fp8_u32 = cvt_f32_to_e4m3(scale_float)\n scale_fp8 = Uint8(scale_fp8_u32 & cutlass.Uint32(0xFF))\n\n if cutlass.const_expr(self.disable_fp4_quant_fast_math):\n output_scale = nvfp4_compute_output_scale_rn(\n scale_fp8_u32, global_scale, block_max\n )\n else:\n output_scale = nvfp4_compute_output_scale(\n scale_fp8_u32, global_scale\n )\n\n if cutlass.const_expr(self.is_bfloat16):\n packed64 = bfloat2x8_to_e2m1x16_packed(\n h0, h1, h2, h3, h4, h5, h6, h7, output_scale\n )\n else:\n packed64 = half2x8_to_e2m1x16_packed(\n h0, h1, h2, h3, h4, h5, h6, h7, output_scale\n )\n\n sf_offset = self._compute_sf_offset(global_row, sf_col, padded_sf_cols)\n mScales[sf_offset] = scale_fp8\n\n row_output = mOutput[global_row, None]\n out_base = sf_col * Int32(NVFP4_SF_VEC_SIZE // 2)\n out_ptr = get_ptr_as_int64(row_output, out_base)\n st_global_u64(out_ptr, packed64)\n\n @cute.jit\n def __call__(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n M: Int32,\n padded_M: Int32,\n num_blocks: Int32,\n global_scale: Union[Float32, cute.Tensor],\n stream,\n ):\n # 3D global tensor: [padded_M, K/64, 64] so each warp's 64-col\n # stripe is the contiguous innermost dimension, matching the CUDA\n # TMA kernel's 3D tensor map.\n gInput = cute.make_tensor(\n mInput.iterator,\n cute.make_layout(\n (padded_M, self.K // _TMA_COL_TILE, _TMA_COL_TILE),\n stride=(self.K, _TMA_COL_TILE, 1),\n ),\n )\n\n # SMEM layout per stage: [rows=16, warps=8, cols_per_warp=64]\n # with SWIZZLE_128B applied. Within each warp's [16, 64] tile the\n # row stride is 64 elems = 128 bytes, putting row bits in the S=3\n # range of the swizzle so different rows map to different banks.\n smem_swizzle = cute.make_swizzle(3, 4, 3) # SWIZZLE_128B for 2B types\n smem_outer_single = cute.make_layout(\n (_TMA_ROW_TILE, _TMA_NUM_CONSUMER_WARPS, _TMA_COL_TILE),\n stride=(_TMA_COL_TILE, _TMA_ROW_TILE * _TMA_COL_TILE, 1),\n )\n smem_single_composed = cute.make_composed_layout(\n smem_swizzle, 0, smem_outer_single\n )\n\n cta_tiler = (_TMA_ROW_TILE, _TMA_NUM_CONSUMER_WARPS, _TMA_COL_TILE)\n tma_atom, tma_tensor = cpasync.make_tiled_tma_atom(\n cpasync.CopyBulkTensorTileG2SOp(),\n gInput,\n smem_single_composed,\n cta_tiler,\n )\n\n total_smem_elems = self.elems_per_stage * self.num_stages\n # Staged outer layout (no swizzle — swizzle passed separately)\n smem_outer_staged = cute.make_layout(\n (_TMA_ROW_TILE, _TMA_NUM_CONSUMER_WARPS, _TMA_COL_TILE, self.num_stages),\n stride=(\n _TMA_COL_TILE,\n _TMA_ROW_TILE * _TMA_COL_TILE,\n 1,\n self.elems_per_stage,\n ),\n )\n # Flat layout for manual-swizzle consumer reads\n smem_layout_flat = cute.make_layout((total_smem_elems,))\n\n self.num_tma_load_bytes = cute.size_in_bytes(self.dtype, smem_outer_single)\n\n @cute.struct\n class SharedStorage:\n load_full_mbar: cute.struct.MemRange[cutlass.Int64, self.num_stages]\n load_empty_mbar: cute.struct.MemRange[cutlass.Int64, self.num_stages]\n smem_data: cute.struct.Align[\n cute.struct.MemRange[self.dtype, total_smem_elems],\n self.buffer_align_bytes,\n ]\n\n self.shared_storage = SharedStorage\n\n self.kernel(\n tma_atom,\n tma_tensor,\n mOutput,\n mScales,\n M,\n padded_M,\n global_scale,\n smem_outer_staged,\n smem_swizzle,\n smem_layout_flat,\n ).launch(\n grid=[num_blocks, 1, 1],\n block=[self.threads_per_cta, 1, 1],\n max_number_threads=[\n self.threads_per_cta,\n 1,\n 1,\n ], # __launch_bounds__(288, 2)\n min_blocks_per_mp=2,\n cluster=(*self.cluster_shape_mn, 1),\n stream=stream,\n use_pdl=self.enable_pdl,\n )\n\n @cute.kernel\n def kernel(\n self,\n tma_atom: cute.CopyAtom,\n gInput_tma: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n M: Int32,\n padded_M: Int32,\n global_scale: Union[Float32, cute.Tensor],\n smem_outer_staged: cute.Layout,\n smem_swizzle: cute.Swizzle,\n smem_layout_flat: cute.Layout,\n ):\n from ...cute_dsl.fp4_common import (\n get_smem_ptr_as_int32,\n ld_shared_v4_u32,\n )\n\n tidx, _, _ = cute.arch.thread_idx()\n bidx, _, _ = cute.arch.block_idx()\n grid_dim_x, _, _ = cute.arch.grid_dim()\n\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_wait()\n\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n lane_idx = tidx % 32\n\n # Device scales stay pointer-loaded; host scales arrive as launch arguments.\n if cutlass.const_expr(isinstance(global_scale, cute.Tensor)):\n global_scale_value = Float32(global_scale[Int32(0)])\n else:\n global_scale_value = global_scale\n padded_sf_cols = self.padded_sf_cols\n num_sf_blocks_per_row = self.num_sf_blocks_per_row\n num_col_chunks = self.num_col_chunks\n elems_per_stage = self.elems_per_stage\n\n # ---- SMEM allocation ----\n smem = cutlass.utils.SmemAllocator()\n storage = smem.allocate(self.shared_storage)\n\n load_mbar_ptr = storage.load_full_mbar.data_ptr()\n # Swizzled tensor for TMA partition (address-space-correct writes)\n sData_staged = storage.smem_data.get_tensor(\n smem_outer_staged, swizzle=smem_swizzle\n )\n # Flat tensor for manual-swizzle consumer reads\n sData_flat = storage.smem_data.get_tensor(smem_layout_flat)\n\n # ---- Pipeline setup ----\n load_pipeline = pipeline.PipelineTmaAsync.create(\n barrier_storage=load_mbar_ptr,\n num_stages=self.num_stages,\n producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread, 1),\n consumer_group=pipeline.CooperativeGroup(\n pipeline.Agent.Thread, self.num_consumer_warps\n ),\n tx_count=self.num_tma_load_bytes,\n cta_layout_vmnk=cute.tiled_divide(\n cute.make_layout((*self.cluster_shape_mn, 1)), (1,)\n ),\n defer_sync=True,\n )\n\n pipeline_init_arrive(cluster_shape_mn=self.cluster_shape_mn, is_relaxed=True)\n pipeline_init_wait(cluster_shape_mn=self.cluster_shape_mn)\n\n # ---- TMA partition (3D: rows x warps x cols_per_warp) ----\n gSrc_tiled = cute.local_tile(\n gInput_tma,\n (_TMA_ROW_TILE, _TMA_NUM_CONSUMER_WARPS, _TMA_COL_TILE),\n (None, None, None),\n )\n tAsA, tAgA = cpasync.tma_partition(\n tma_atom,\n 0,\n cute.make_layout(1),\n cute.group_modes(sData_staged, 0, 3), # Group 3 tile modes\n cute.group_modes(gSrc_tiled, 0, 3),\n )\n\n num_row_tiles = cute.ceil_div(padded_M, _TMA_ROW_TILE)\n\n # ---- Consumer thread indexing (matches CUDA TmaKernelTraitsTwoBytes) ----\n # 4 threads per row, 8 rows per warp, 2 row iterations per stage\n col_idx_local = lane_idx % Int32(self.THREADS_PER_ROW)\n row_idx_local = lane_idx // Int32(self.THREADS_PER_ROW)\n\n # ======== Producer warp (warp 0) ========\n if warp_idx == self.producer_warp_id:\n producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.num_stages\n )\n\n row_tile_idx = bidx\n while row_tile_idx < num_row_tiles:\n col_chunk = Int32(0)\n while col_chunk < num_col_chunks:\n load_pipeline.producer_acquire(producer_state)\n\n cute.copy(\n tma_atom,\n tAgA[(None, row_tile_idx, col_chunk, 0)],\n tAsA[(None, producer_state.index)],\n tma_bar_ptr=load_pipeline.producer_get_barrier(producer_state),\n )\n\n producer_state.advance()\n col_chunk = col_chunk + Int32(1)\n\n row_tile_idx = row_tile_idx + grid_dim_x\n\n load_pipeline.producer_tail(producer_state)\n\n # ======== Consumer warps (warps 1-8) ========\n if warp_idx > 0:\n consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.num_stages\n )\n\n # 0-indexed consumer warp id\n consumer_warp_idx = warp_idx - Int32(1)\n\n # Pre-compute warp tile base offset (constant per warp)\n # SMEM 3D layout: [rows=16, warps=8, cols=64] per stage\n # stride: [64, 1024, 1] → warp tile base = warp * 1024\n warp_tile_elems = _TMA_ROW_TILE * _TMA_COL_TILE # 1024\n warp_tile_base = consumer_warp_idx * Int32(warp_tile_elems)\n\n # Float4 base position for this thread (0, 2, 4, 6)\n f4_base = col_idx_local * Int32(2)\n\n # Global column offset for SF index: warp's column within K\n base_col_in_stage = consumer_warp_idx * Int32(\n _TMA_COL_TILE\n ) + col_idx_local * Int32(self.ELTS_PER_THREAD)\n\n row_tile_idx = bidx\n while row_tile_idx < num_row_tiles:\n base_row = row_tile_idx * Int32(_TMA_ROW_TILE)\n\n col_chunk = Int32(0)\n while col_chunk < num_col_chunks:\n load_pipeline.consumer_wait(consumer_state)\n stage = consumer_state.index\n\n # ---- Read ALL SMEM data with SWIZZLE_128B addressing ----\n # Within each warp's [16,64] tile, the XOR pattern matches\n # CUDA's load_input_vec: float4_idx ^= row & 7\n # Physical elem offset in warp tile for (row, float4 f):\n # row * 64 + (f ^ (row & 7)) * 8\n stage_base = stage * Int32(elems_per_stage)\n\n # Row iteration 0 (row_idx_local = 0..7)\n r0_xor = row_idx_local & Int32(7)\n r0_f4_0 = f4_base ^ r0_xor\n r0_f4_1 = (f4_base + Int32(1)) ^ r0_xor\n r0_row_base = (\n stage_base\n + warp_tile_base\n + row_idx_local * Int32(_TMA_COL_TILE)\n )\n r0_addr_0 = get_smem_ptr_as_int32(\n sData_flat, r0_row_base + r0_f4_0 * Int32(8)\n )\n r0_addr_1 = get_smem_ptr_as_int32(\n sData_flat, r0_row_base + r0_f4_1 * Int32(8)\n )\n r0_h0, r0_h1, r0_h2, r0_h3 = ld_shared_v4_u32(r0_addr_0)\n r0_h4, r0_h5, r0_h6, r0_h7 = ld_shared_v4_u32(r0_addr_1)\n\n # Row iteration 1 (row = row_idx_local + 8)\n r1_row = row_idx_local + Int32(self.ROWS_PER_WARP)\n r1_xor = r1_row & Int32(7)\n r1_f4_0 = f4_base ^ r1_xor\n r1_f4_1 = (f4_base + Int32(1)) ^ r1_xor\n r1_row_base = (\n stage_base + warp_tile_base + r1_row * Int32(_TMA_COL_TILE)\n )\n r1_addr_0 = get_smem_ptr_as_int32(\n sData_flat, r1_row_base + r1_f4_0 * Int32(8)\n )\n r1_addr_1 = get_smem_ptr_as_int32(\n sData_flat, r1_row_base + r1_f4_1 * Int32(8)\n )\n r1_h0, r1_h1, r1_h2, r1_h3 = ld_shared_v4_u32(r1_addr_0)\n r1_h4, r1_h5, r1_h6, r1_h7 = ld_shared_v4_u32(r1_addr_1)\n\n # ---- Quantize and write: both row iterations ----\n # Global column base for SF index computation\n global_col_base = col_chunk * Int32(_TMA_COLS_PER_STAGE)\n sf_col = (global_col_base + base_col_in_stage) // Int32(\n NVFP4_SF_VEC_SIZE\n )\n\n # Row iteration 0\n global_row_0 = base_row + row_idx_local\n self._quantize_sf_block(\n r0_h0,\n r0_h1,\n r0_h2,\n r0_h3,\n r0_h4,\n r0_h5,\n r0_h6,\n r0_h7,\n global_row_0,\n sf_col,\n global_scale_value,\n M,\n padded_M,\n padded_sf_cols,\n mOutput,\n mScales,\n )\n\n # Row iteration 1\n global_row_1 = base_row + row_idx_local + Int32(self.ROWS_PER_WARP)\n self._quantize_sf_block(\n r1_h0,\n r1_h1,\n r1_h2,\n r1_h3,\n r1_h4,\n r1_h5,\n r1_h6,\n r1_h7,\n global_row_1,\n sf_col,\n global_scale_value,\n M,\n padded_M,\n padded_sf_cols,\n mOutput,\n mScales,\n )\n\n # ---- Release pipeline after all work (matches CUDA pattern) ----\n load_pipeline.consumer_release(consumer_state)\n consumer_state.advance()\n\n col_chunk = col_chunk + Int32(1)\n\n # Zero padding SF columns for swizzled layouts\n if cutlass.const_expr(self.sf_layout != SF_LAYOUT_LINEAR):\n consumer_tid = (warp_idx - Int32(1)) * Int32(32) + lane_idx\n if consumer_tid < _TMA_ROW_TILE:\n pad_row_idx = base_row + consumer_tid\n if pad_row_idx < padded_M:\n padding_sf = Int32(num_sf_blocks_per_row)\n while padding_sf < padded_sf_cols:\n sf_offset = self._compute_sf_offset(\n pad_row_idx, padding_sf, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n padding_sf = padding_sf + Int32(1)\n\n row_tile_idx = row_tile_idx + grid_dim_x\n\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_launch_dependents()\n\n\n# =============================================================================\n# PyTorch Integration with TVM-FFI\n# =============================================================================\n\n\ndef _kernel_source_files() -> Tuple[str, ...]:\n \"\"\"Source files whose content invalidates the on-disk kernel cache.\"\"\"\n from ...cute_dsl import fp4_common\n from .. import quantization_cute_dsl_utils\n\n return (__file__, fp4_common.__file__, quantization_cute_dsl_utils.__file__)\n\n\n_CUTE_DSL_MODULE = \"nvfp4_quantize\"\n\n\ndef _nvfp4_kernel_name(\n variant: str,\n dtype_key: str,\n K: int,\n sf_layout: int,\n enable_pdl: bool,\n disable_fp4_quant_fast_math: bool,\n silu_and_mul: bool,\n nvfp4_4over6_config: NVFP44Over6Config | None = None,\n global_scale_is_tensor: bool = True,\n) -> str:\n \"\"\"Specialization name within the nvfp4_quantize module, encoding every\n parameter that affects codegen.\n \"\"\"\n name = f\"{variant}_{dtype_key}_k{K}_sf{sf_layout}_pdl{int(enable_pdl)}\"\n if not global_scale_is_tensor:\n name += \"_host_sf\"\n if silu_and_mul:\n name += \"_silu\"\n if disable_fp4_quant_fast_math:\n name += \"_nofastmath\"\n if nvfp4_4over6_config is not None:\n cfg = nvfp4_4over6_config\n err_mode = getattr(cfg.err_mode, \"name\", cfg.err_mode)\n name += f\"_4over6_{cfg.e4m3_max}_{err_mode}_{int(cfg.err_use_fast_math)}\"\n return name\n\n\n@functools.cache\ndef _get_compiled_kernel_nvfp4(\n dtype_key: str,\n K: int,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool = False,\n disable_fp4_quant_fast_math: bool = False,\n nvfp4_4over6_config: NVFP44Over6Config | None = None,\n silu_and_mul: bool = False,\n global_scale_is_tensor: bool = True,\n) -> Tuple[Callable, int]:\n \"\"\"\n Get or compile NVFP4 kernel with TVM-FFI.\n\n Cached by (K, dtype_key, sf_layout, pdl, silu_and_mul,\n global_scale_is_tensor) - M-agnostic, device-independent compilation.\n\n Args:\n dtype_key: One of \"float16\", \"bfloat16\", \"float8_e4m3fn\".\n silu_and_mul: When True, fuse silu(gate) * up; the input row is 2 * K\n wide (gate then up concatenated) while the output stays K wide.\n global_scale_is_tensor: Whether the global scale is passed as a device\n tensor or a host-side scalar kernel argument.\n\n Returns:\n For linear layout: (compiled_kernel, sf_blocks_per_tb)\n For swizzled layout: (compiled_kernel, rows_per_block)\n \"\"\"\n _dtype_map = {\n \"float16\": cutlass.Float16,\n \"bfloat16\": cutlass.BFloat16,\n \"float8_e4m3fn\": cutlass.Float8E4M3FN,\n }\n cutlass_dtype = _dtype_map[dtype_key]\n\n # Use symbolic M for dynamic batch sizes\n sym_m = cute.sym_int()\n sym_scale_size = cute.sym_int()\n\n # Fused inputs have 2*K columns; outputs remain K-wide.\n input_cols = 2 * K if silu_and_mul else K\n\n # Common fake tensors\n input_fake = cute.runtime.make_fake_compact_tensor(\n cutlass_dtype, (sym_m, input_cols), stride_order=(1, 0), assumed_align=16\n )\n output_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_m, K // 2), stride_order=(1, 0), assumed_align=16\n )\n scales_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_scale_size,), assumed_align=16\n )\n global_scale_fake = (\n cute.runtime.make_fake_compact_tensor(cutlass.Float32, (1,), assumed_align=4)\n if global_scale_is_tensor\n else Float32(1.0)\n )\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n\n if sf_layout == SF_LAYOUT_LINEAR:\n linear_obj = NVFP4QuantizeLinearKernel(\n cutlass_dtype,\n K,\n enable_pdl,\n disable_fp4_quant_fast_math,\n nvfp4_4over6_config,\n silu_and_mul=silu_and_mul,\n )\n\n compiled_kernel = build_and_load_cute_dsl_kernel(\n _CUTE_DSL_MODULE,\n _nvfp4_kernel_name(\n \"linear\",\n dtype_key,\n K,\n sf_layout,\n enable_pdl,\n disable_fp4_quant_fast_math,\n silu_and_mul,\n nvfp4_4over6_config,\n global_scale_is_tensor,\n ),\n lambda: cute.compile(\n linear_obj,\n input_fake,\n output_fake,\n scales_fake,\n Int32(1), # Dummy M\n Int32(1), # Dummy total_sf_blocks\n Int32(1), # Dummy num_blocks\n global_scale_fake,\n stream_fake,\n options=\"--enable-tvm-ffi\",\n ),\n extra_key_files=_kernel_source_files(),\n )\n\n return compiled_kernel, linear_obj.SF_BLOCKS_PER_TB\n else:\n swizzled_obj = NVFP4QuantizeSwizzledKernel(\n cutlass_dtype,\n K,\n sf_layout=sf_layout,\n enable_pdl=enable_pdl,\n disable_fp4_quant_fast_math=disable_fp4_quant_fast_math,\n nvfp4_4over6_config=nvfp4_4over6_config,\n silu_and_mul=silu_and_mul,\n )\n\n compiled_kernel = build_and_load_cute_dsl_kernel(\n _CUTE_DSL_MODULE,\n _nvfp4_kernel_name(\n \"swizzled\",\n dtype_key,\n K,\n sf_layout,\n enable_pdl,\n disable_fp4_quant_fast_math,\n silu_and_mul,\n nvfp4_4over6_config,\n global_scale_is_tensor,\n ),\n lambda: cute.compile(\n swizzled_obj,\n input_fake,\n output_fake,\n scales_fake,\n Int32(1), # Dummy M\n Int32(128), # Dummy padded_M\n Int32(1), # Dummy num_blocks\n global_scale_fake,\n stream_fake,\n options=\"--enable-tvm-ffi\",\n ),\n extra_key_files=_kernel_source_files(),\n )\n\n return compiled_kernel, swizzled_obj.rows_per_block\n\n\n@functools.cache\ndef _get_compiled_kernel_nvfp4_per_token(\n dtype_key: str,\n K: int,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool = False,\n disable_fp4_quant_fast_math: bool = False,\n nvfp4_4over6_config: NVFP44Over6Config | None = None,\n) -> Callable:\n _dtype_map = {\n \"float16\": cutlass.Float16,\n \"bfloat16\": cutlass.BFloat16,\n }\n cutlass_dtype = _dtype_map[dtype_key]\n\n sym_m = cute.sym_int()\n sym_scale_size = cute.sym_int()\n\n input_fake = cute.runtime.make_fake_compact_tensor(\n cutlass_dtype, (sym_m, K), stride_order=(1, 0), assumed_align=16\n )\n output_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_m, K // 2), stride_order=(1, 0), assumed_align=16\n )\n scales_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_scale_size,), assumed_align=16\n )\n per_token_scale_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32, (sym_m,), assumed_align=4\n )\n global_scale_inv_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32, (1,), assumed_align=4\n )\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n\n kernel_obj = NVFP4QuantizePerTokenKernel(\n cutlass_dtype,\n K,\n sf_layout=sf_layout,\n enable_pdl=enable_pdl,\n disable_fp4_quant_fast_math=disable_fp4_quant_fast_math,\n nvfp4_4over6_config=nvfp4_4over6_config,\n )\n\n return build_and_load_cute_dsl_kernel(\n _CUTE_DSL_MODULE,\n _nvfp4_kernel_name(\n \"per_token\",\n dtype_key,\n K,\n sf_layout,\n enable_pdl,\n disable_fp4_quant_fast_math,\n silu_and_mul=False,\n nvfp4_4over6_config=nvfp4_4over6_config,\n ),\n lambda: cute.compile(\n kernel_obj,\n input_fake,\n output_fake,\n scales_fake,\n per_token_scale_fake,\n Int32(1),\n global_scale_inv_fake,\n stream_fake,\n options=\"--enable-tvm-ffi\",\n ),\n extra_key_files=_kernel_source_files(),\n )\n\n\n_TMA_MIN_M = 1024\n_TMA_LOG2_MK_THRESHOLD = 25\n\n\ndef _should_use_tma(m: int, k: int, dtype: torch.dtype) -> bool:\n \"\"\"TODO: disabled TMA for now due to perf sweep showing the vectorized-load\n kernel is as fast/at parity.\n\n Set ``FLASHINFER_NVFP4_QUANTIZE_USE_TMA=1`` to re-enable the heuristic for\n re-tuning on other hardware.\n \"\"\"\n if not _env_flag_enabled(\"FLASHINFER_NVFP4_QUANTIZE_USE_TMA\"):\n return False\n if dtype == torch.float8_e4m3fn:\n return False\n if k % _TMA_COLS_PER_STAGE != 0:\n return False\n if m < _TMA_MIN_M:\n return False\n # Use log2(M) + log2(K) threshold for the crossover point\n return m.bit_length() - 1 + k.bit_length() - 1 >= _TMA_LOG2_MK_THRESHOLD\n\n\n@functools.cache\ndef _get_compiled_kernel_nvfp4_tma(\n dtype_key: str,\n K: int,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool = False,\n disable_fp4_quant_fast_math: bool = False,\n global_scale_is_tensor: bool = True,\n) -> Tuple[Callable, int]:\n \"\"\"\n Get or compile TMA-based NVFP4 kernel with TVM-FFI.\n\n Cached by (K, dtype_key, sf_layout, pdl, global_scale_is_tensor).\n \"\"\"\n _dtype_map = {\n \"float16\": cutlass.Float16,\n \"bfloat16\": cutlass.BFloat16,\n }\n cutlass_dtype = _dtype_map[dtype_key]\n kernel_obj = NVFP4QuantizeTMAKernel(\n cutlass_dtype,\n K,\n sf_layout=sf_layout,\n enable_pdl=enable_pdl,\n disable_fp4_quant_fast_math=disable_fp4_quant_fast_math,\n )\n\n sym_m = cute.sym_int()\n sym_padded_m = cute.sym_int()\n\n input_fake = cute.runtime.make_fake_compact_tensor(\n cutlass_dtype, (sym_padded_m, K), stride_order=(1, 0), assumed_align=16\n )\n output_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_m, K // 2), stride_order=(1, 0), assumed_align=16\n )\n sym_scale_size = cute.sym_int()\n scales_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_scale_size,), assumed_align=16\n )\n global_scale_fake = (\n cute.runtime.make_fake_compact_tensor(cutlass.Float32, (1,), assumed_align=4)\n if global_scale_is_tensor\n else Float32(1.0)\n )\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n\n compiled_kernel = build_and_load_cute_dsl_kernel(\n _CUTE_DSL_MODULE,\n _nvfp4_kernel_name(\n \"tma\",\n dtype_key,\n K,\n sf_layout,\n enable_pdl,\n disable_fp4_quant_fast_math,\n silu_and_mul=False,\n global_scale_is_tensor=global_scale_is_tensor,\n ),\n lambda: cute.compile(\n kernel_obj,\n input_fake,\n output_fake,\n scales_fake,\n Int32(1), # Dummy M\n Int32(1024), # Dummy padded_M\n Int32(1), # Dummy num_blocks\n global_scale_fake,\n stream_fake,\n options=\"--enable-tvm-ffi\",\n ),\n extra_key_files=_kernel_source_files(),\n )\n\n return compiled_kernel, kernel_obj.rows_per_block\n\n\n@flashinfer_api\ndef nvfp4_quantize_cute_dsl(\n input: torch.Tensor,\n global_scale: float | torch.Tensor,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool | None = None,\n) -> Tuple[torch.Tensor, torch.Tensor]:\n r\"\"\"Quantize input tensor to NVFP4 format using the CuTe-DSL kernel.\n\n GPU implementation matching :func:`flashinfer.quantization.nvfp4_quantize`:\n\n - E4M3 scale factors (FP8)\n - E2M1 output format (4-bit, 2 values per byte)\n - Supports 128x4, 8x4, and linear scale-factor layouts\n - ``sf_vec_size = 16``\n\n The kernel is compiled separately for host-scalar and device-tensor\n global scales and handles varying ``M`` (batch size) at runtime without\n recompilation.\n\n Parameters\n ----------\n input : torch.Tensor\n Input tensor of shape ``[M, K]`` with dtype\n fp16/bf16/float8_e4m3fn.\n global_scale : float or torch.Tensor\n Host-side NVFP4 global scale factor. A single-element tensor is also\n accepted for backward compatibility.\n sf_layout : int\n Scale-factor layout (``0=128x4``, ``1=8x4``, ``2=linear``).\n enable_pdl : bool, optional\n Whether to enable Programmatic Dependent Launch. Auto-detected\n from device capability (SM >= 9.0) when ``None``.\n\n Returns\n -------\n Tuple[torch.Tensor, torch.Tensor]\n ``(fp4_tensor, scale_tensor)`` where ``fp4_tensor`` is the\n quantized tensor of shape ``[M, K/2]`` with dtype ``uint8`` and\n ``scale_tensor`` holds the E4M3 scale factors (``uint8``) reshaped\n to ``[padded_rows, K/16]``.\n \"\"\"\n from ...utils import device_support_pdl\n\n _valid_sf_layouts = (SF_LAYOUT_128x4, SF_LAYOUT_8x4, SF_LAYOUT_LINEAR)\n assert sf_layout in _valid_sf_layouts, (\n f\"sf_layout must be one of {_valid_sf_layouts}, got {sf_layout}\"\n )\n _supported_dtypes = (torch.float16, torch.bfloat16, torch.float8_e4m3fn)\n assert input.dtype in _supported_dtypes, (\n f\"Input dtype must be one of {_supported_dtypes}, got {input.dtype}\"\n )\n assert input.is_cuda, \"Input must be on CUDA device\"\n\n enable_pdl = device_support_pdl(input.device) if enable_pdl is not False else False\n\n if input.dim() > 2:\n m = input.numel() // input.shape[-1]\n k = input.shape[-1]\n input = input.reshape(m, k)\n else:\n m, k = input.shape\n\n assert k % NVFP4_SF_VEC_SIZE == 0, (\n f\"K ({k}) must be divisible by NVFP4_SF_VEC_SIZE={NVFP4_SF_VEC_SIZE}\"\n )\n\n input = input.contiguous()\n\n _torch_to_dtype_key = {\n torch.float16: \"float16\",\n torch.bfloat16: \"bfloat16\",\n torch.float8_e4m3fn: \"float8_e4m3fn\",\n }\n dtype_key = _torch_to_dtype_key[input.dtype]\n\n # Never call .item() on a device scale: that would synchronize the stream\n # and make this path illegal during CUDA graph capture.\n global_scale_is_tensor = isinstance(global_scale, torch.Tensor)\n if global_scale_is_tensor:\n global_scale_arg = (\n cast(torch.Tensor, global_scale)\n .float()\n .reshape(1)\n .contiguous()\n .to(input.device)\n )\n else:\n global_scale_arg = float(global_scale)\n\n num_sm = get_num_sm(input.device)\n\n num_sf_blocks_per_row = k // NVFP4_SF_VEC_SIZE\n\n disable_fp4_quant_fast_math = _env_flag_enabled(\n \"FLASHINFER_DISABLE_FP4_QUANT_FAST_MATH\"\n )\n nvfp4_4over6_config = current_nvfp4_4over6_config()\n if nvfp4_4over6_config is not None and input.dtype == torch.float8_e4m3fn:\n raise ValueError(\"FLASHINFER_NVFP4_4OVER6 requires fp16 or bf16 input\")\n use_tma = _should_use_tma(m, k, input.dtype) and nvfp4_4over6_config is None\n\n if use_tma:\n tma_row_tile = _TMA_ROW_TILE\n if sf_layout == SF_LAYOUT_LINEAR:\n padded_m = _round_up(m, tma_row_tile)\n padded_sf_cols = num_sf_blocks_per_row\n elif sf_layout == SF_LAYOUT_8x4:\n padded_m = _round_up(m, max(tma_row_tile, 8))\n padded_sf_cols = ((num_sf_blocks_per_row + 3) // 4) * 4\n else:\n padded_m = _round_up(m, max(tma_row_tile, ROW_TILE_SIZE))\n padded_sf_cols = ((num_sf_blocks_per_row + 3) // 4) * 4\n\n scale_output_size = padded_m * padded_sf_cols\n\n kernel_fn, rows_per_block = _get_compiled_kernel_nvfp4_tma(\n dtype_key,\n k,\n sf_layout,\n enable_pdl,\n disable_fp4_quant_fast_math,\n global_scale_is_tensor,\n )\n\n # Match CUDA TMA kernel: grid = min(row_tiles, SM_count * 2)\n tma_target_grid = num_sm * 2\n num_blocks = min(\n (padded_m + rows_per_block - 1) // rows_per_block, tma_target_grid\n )\n\n input_padded = input\n if padded_m > m:\n input_padded = torch.zeros(\n padded_m, k, dtype=input.dtype, device=input.device\n )\n input_padded[:m, :] = input\n\n fp4_output = torch.empty(m, k // 2, dtype=torch.uint8, device=input.device)\n scale_output = torch.empty(\n scale_output_size, dtype=torch.uint8, device=input.device\n )\n\n kernel_fn(\n input_padded,\n fp4_output,\n scale_output,\n m,\n padded_m,\n num_blocks,\n global_scale_arg,\n )\n\n if sf_layout == SF_LAYOUT_LINEAR:\n scale_output = scale_output[: m * num_sf_blocks_per_row]\n\n # Reshape using padded_sf_cols for swizzled layouts (the buffer is\n # physically padded and stores data in swizzled order). For linear\n # layout the padding is already trimmed above.\n scale_output = scale_output.reshape(-1, padded_sf_cols)\n\n return fp4_output, scale_output\n\n # Non-TMA path: dual-path dispatch\n # Get or compile kernel (device-independent)\n kernel_fn, block_unit = _get_compiled_kernel_nvfp4(\n dtype_key,\n k,\n sf_layout,\n enable_pdl,\n disable_fp4_quant_fast_math,\n nvfp4_4over6_config,\n global_scale_is_tensor=global_scale_is_tensor,\n )\n\n target_grid = num_sm * _BLOCKS_PER_SM\n\n if sf_layout == SF_LAYOUT_LINEAR:\n padded_m = m\n padded_sf_cols = num_sf_blocks_per_row\n total_sf_blocks = m * num_sf_blocks_per_row\n scale_output_size = total_sf_blocks\n\n sf_blocks_per_tb = block_unit\n num_blocks = min(\n (total_sf_blocks + sf_blocks_per_tb - 1) // sf_blocks_per_tb,\n target_grid,\n )\n\n fp4_output = torch.empty(m, k // 2, dtype=torch.uint8, device=input.device)\n scale_output = torch.empty(\n scale_output_size, dtype=torch.uint8, device=input.device\n )\n\n kernel_fn(\n input,\n fp4_output,\n scale_output,\n m,\n total_sf_blocks,\n num_blocks,\n global_scale_arg,\n )\n else:\n if sf_layout == SF_LAYOUT_8x4:\n row_tile_size = 8\n else:\n row_tile_size = ROW_TILE_SIZE # 128\n padded_m = ((m + row_tile_size - 1) // row_tile_size) * row_tile_size\n padded_sf_cols = ((num_sf_blocks_per_row + 3) // 4) * 4\n scale_output_size = padded_m * padded_sf_cols\n\n rows_per_block = block_unit\n num_blocks = min(\n (padded_m + rows_per_block - 1) // rows_per_block,\n target_grid,\n )\n\n fp4_output = torch.empty(m, k // 2, dtype=torch.uint8, device=input.device)\n scale_output = torch.empty(\n scale_output_size, dtype=torch.uint8, device=input.device\n )\n\n kernel_fn(\n input,\n fp4_output,\n scale_output,\n m,\n padded_m,\n num_blocks,\n global_scale_arg,\n )\n\n # Reshape using padded_sf_cols: for swizzled layouts the buffer includes\n # column padding; for linear layout padded_sf_cols == num_sf_blocks_per_row.\n scale_output = scale_output.reshape(-1, padded_sf_cols)\n\n return fp4_output, scale_output\n\n\ndef silu_and_mul_nvfp4_quantize_cute_dsl(\n input: torch.Tensor,\n global_scale: torch.Tensor,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool | None = None,\n) -> Tuple[torch.Tensor, torch.Tensor]:\n r\"\"\"Apply SwiGLU and NVFP4 quantization using CuTe-DSL.\n\n Computes ``silu(input[..., :K]) * input[..., K:]`` before quantization.\n\n Parameters\n ----------\n input : torch.Tensor\n FP16/BF16 tensor of shape ``[..., 2K]``. Leading dimensions are\n flattened into M.\n global_scale : torch.Tensor\n Float32 scale of shape ``[1]``.\n sf_layout : int\n Scale layout: 0 for 128x4, 1 for 8x4, or 2 for linear.\n enable_pdl : bool, optional\n Enable Programmatic Dependent Launch. Auto-detected when None.\n\n Returns\n -------\n Tuple[torch.Tensor, torch.Tensor]\n Packed FP4 values of shape ``[M, K/2]`` and their uint8 E4M3 scales.\n \"\"\"\n from ...utils import device_support_pdl\n\n _valid_sf_layouts = (SF_LAYOUT_128x4, SF_LAYOUT_8x4, SF_LAYOUT_LINEAR)\n assert sf_layout in _valid_sf_layouts, (\n f\"sf_layout must be one of {_valid_sf_layouts}, got {sf_layout}\"\n )\n _supported_dtypes = (torch.float16, torch.bfloat16)\n assert input.dtype in _supported_dtypes, (\n f\"SwiGLU NVFP4 input dtype must be one of {_supported_dtypes}, \"\n f\"got {input.dtype}\"\n )\n assert input.is_cuda, \"Input must be on CUDA device\"\n\n enable_pdl = device_support_pdl(input.device) if enable_pdl is not False else False\n\n # Flatten leading dimensions into M.\n input_cols = input.shape[-1]\n assert input_cols % 2 == 0, (\n \"the last dimension must be even (gate and up concatenated)\"\n )\n k = input_cols // 2\n assert k % NVFP4_SF_VEC_SIZE == 0, (\n f\"K ({k}) must be divisible by NVFP4_SF_VEC_SIZE={NVFP4_SF_VEC_SIZE}\"\n )\n # Multiply leading dimensions so zero-width inputs remain valid.\n m = 1\n for dim in input.shape[:-1]:\n m *= int(dim)\n\n # Return empty outputs without compiling or launching.\n if m == 0 or k == 0:\n num_sf_blocks_per_row = k // NVFP4_SF_VEC_SIZE\n if sf_layout == SF_LAYOUT_LINEAR:\n padded_sf_cols = num_sf_blocks_per_row\n else:\n padded_sf_cols = ((num_sf_blocks_per_row + 3) // 4) * 4\n return (\n torch.empty((m, k // 2), dtype=torch.uint8, device=input.device),\n torch.empty((m, padded_sf_cols), dtype=torch.uint8, device=input.device),\n )\n\n input = input.reshape(m, input_cols)\n input = input.contiguous()\n # Clone storage-offset views that violate the kernel's 16-byte alignment.\n if input.data_ptr() % 16 != 0:\n input = input.clone()\n\n _torch_to_dtype_key = {\n torch.float16: \"float16\",\n torch.bfloat16: \"bfloat16\",\n }\n dtype_key = _torch_to_dtype_key[input.dtype]\n\n if isinstance(global_scale, torch.Tensor):\n global_scale_tensor = (\n global_scale.float().reshape(1).contiguous().to(input.device)\n )\n else:\n global_scale_tensor = torch.tensor(\n [float(global_scale)], dtype=torch.float32, device=input.device\n )\n\n num_sm = get_num_sm(input.device)\n num_sf_blocks_per_row = k // NVFP4_SF_VEC_SIZE\n\n disable_fp4_quant_fast_math = _env_flag_enabled(\n \"FLASHINFER_DISABLE_FP4_QUANT_FAST_MATH\"\n )\n nvfp4_4over6_config = current_nvfp4_4over6_config()\n\n # SwiGLU fusion uses the non-TMA vectorized-load kernels only.\n kernel_fn, block_unit = _get_compiled_kernel_nvfp4(\n dtype_key,\n k,\n sf_layout,\n enable_pdl,\n disable_fp4_quant_fast_math,\n nvfp4_4over6_config,\n silu_and_mul=True,\n )\n\n target_grid = num_sm * _BLOCKS_PER_SM\n\n if sf_layout == SF_LAYOUT_LINEAR:\n padded_sf_cols = num_sf_blocks_per_row\n total_sf_blocks = m * num_sf_blocks_per_row\n scale_output_size = total_sf_blocks\n\n sf_blocks_per_tb = block_unit\n num_blocks = min(\n (total_sf_blocks + sf_blocks_per_tb - 1) // sf_blocks_per_tb,\n target_grid,\n )\n\n fp4_output = torch.empty(m, k // 2, dtype=torch.uint8, device=input.device)\n scale_output = torch.empty(\n scale_output_size, dtype=torch.uint8, device=input.device\n )\n\n kernel_fn(\n input,\n fp4_output,\n scale_output,\n m,\n total_sf_blocks,\n num_blocks,\n global_scale_tensor,\n )\n else:\n if sf_layout == SF_LAYOUT_8x4:\n row_tile_size = 8\n else:\n row_tile_size = ROW_TILE_SIZE # 128\n padded_m = ((m + row_tile_size - 1) // row_tile_size) * row_tile_size\n padded_sf_cols = ((num_sf_blocks_per_row + 3) // 4) * 4\n scale_output_size = padded_m * padded_sf_cols\n\n rows_per_block = block_unit\n num_blocks = min(\n (padded_m + rows_per_block - 1) // rows_per_block,\n target_grid,\n )\n\n fp4_output = torch.empty(m, k // 2, dtype=torch.uint8, device=input.device)\n scale_output = torch.empty(\n scale_output_size, dtype=torch.uint8, device=input.device\n )\n\n kernel_fn(\n input,\n fp4_output,\n scale_output,\n m,\n padded_m,\n num_blocks,\n global_scale_tensor,\n )\n\n # Return scales in their layout-specific 2D shape.\n scale_output = scale_output.reshape(-1, padded_sf_cols)\n\n return fp4_output, scale_output\n\n\n@flashinfer_api\ndef nvfp4_quantize_per_token_cute_dsl(\n input: torch.Tensor,\n global_scale_inv: torch.Tensor,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool | None = None,\n) -> Tuple[torch.Tensor, torch.Tensor, torch.Tensor]:\n r\"\"\"Per-token NVFP4 activation quantization using the CuTe-DSL kernel.\n\n Unlike :func:`nvfp4_quantize_cute_dsl`, which applies a single global\n scale, this variant computes one quantization scale **per row (token)** of\n the activation. Each row is scaled independently so that its largest\n magnitude maps to the NVFP4 dynamic range, and the resulting per-token\n scale is returned alongside the packed FP4 output and the E4M3 block\n scale factors.\n\n - E4M3 block scale factors (FP8), ``sf_vec_size = 16``\n - E2M1 output format (4-bit, 2 values per byte)\n - Supports 128x4, 8x4, and linear scale-factor layouts\n\n The kernel is compiled once per ``(K, dtype, sf_layout, pdl)`` tuple and\n handles varying ``M`` (number of tokens) at runtime without recompilation.\n\n Parameters\n ----------\n input : torch.Tensor\n 2-D activation tensor of shape ``[M, K]`` with dtype fp16/bf16. ``K``\n must be divisible by ``NVFP4_SF_VEC_SIZE`` (16).\n global_scale_inv : torch.Tensor\n Scalar tensor (``float32``) holding the inverse global scale applied on\n top of the per-token scale. A Python ``float`` is also accepted and\n wrapped into a tensor internally.\n sf_layout : int\n Scale-factor layout (``0=128x4``, ``1=8x4``, ``2=linear``).\n enable_pdl : bool, optional\n Whether to enable Programmatic Dependent Launch. Auto-detected from\n device capability (SM >= 9.0) when ``None``; pass ``False`` to force it\n off.\n\n Returns\n -------\n Tuple[torch.Tensor, torch.Tensor, torch.Tensor]\n ``(fp4_output, scale_output, per_token_scale)`` where:\n\n - ``fp4_output`` is the packed quantized tensor of shape ``[M, K/2]``\n with dtype ``uint8`` (two E2M1 values per byte).\n - ``scale_output`` holds the E4M3 block scale factors (``uint8``)\n reshaped to ``[padded_rows, padded_sf_cols]``. The padding depends on\n ``sf_layout``: ``linear`` keeps ``M`` rows, while ``128x4`` / ``8x4``\n pad rows and columns up to the layout tile.\n - ``per_token_scale`` is the per-row quantization scale of shape\n ``[M]`` with dtype ``float32``.\n \"\"\"\n from ...utils import device_support_pdl\n\n _valid_sf_layouts = (SF_LAYOUT_128x4, SF_LAYOUT_8x4, SF_LAYOUT_LINEAR)\n assert sf_layout in _valid_sf_layouts, (\n f\"sf_layout must be one of {_valid_sf_layouts}, got {sf_layout}\"\n )\n _supported_dtypes = (torch.float16, torch.bfloat16)\n assert input.dtype in _supported_dtypes, (\n f\"Per-token NVFP4 input dtype must be one of {_supported_dtypes}, got {input.dtype}\"\n )\n assert input.is_cuda, \"Input must be on CUDA device\"\n assert input.dim() == 2, \"Per-token NVFP4 quantization expects a 2D input\"\n\n enable_pdl = device_support_pdl(input.device) if enable_pdl is not False else False\n input = input.contiguous()\n m, k = input.shape\n assert k % NVFP4_SF_VEC_SIZE == 0, (\n f\"K ({k}) must be divisible by NVFP4_SF_VEC_SIZE={NVFP4_SF_VEC_SIZE}\"\n )\n\n _torch_to_dtype_key = {\n torch.float16: \"float16\",\n torch.bfloat16: \"bfloat16\",\n }\n dtype_key = _torch_to_dtype_key[input.dtype]\n\n if isinstance(global_scale_inv, torch.Tensor):\n global_scale_inv_tensor = (\n global_scale_inv.float().reshape(1).contiguous().to(input.device)\n )\n else:\n global_scale_inv_tensor = torch.tensor(\n [float(global_scale_inv)], dtype=torch.float32, device=input.device\n )\n\n num_sf_blocks_per_row = k // NVFP4_SF_VEC_SIZE\n if sf_layout == SF_LAYOUT_LINEAR:\n padded_m = m\n padded_sf_cols = num_sf_blocks_per_row\n elif sf_layout == SF_LAYOUT_8x4:\n padded_m = _round_up(m, 8)\n padded_sf_cols = ((num_sf_blocks_per_row + 3) // 4) * 4\n else:\n padded_m = _round_up(m, ROW_TILE_SIZE)\n padded_sf_cols = ((num_sf_blocks_per_row + 3) // 4) * 4\n\n disable_fp4_quant_fast_math = _env_flag_enabled(\n \"FLASHINFER_DISABLE_FP4_QUANT_FAST_MATH\"\n )\n nvfp4_4over6_config = current_nvfp4_4over6_config()\n\n kernel_fn = _get_compiled_kernel_nvfp4_per_token(\n dtype_key,\n k,\n sf_layout,\n enable_pdl,\n disable_fp4_quant_fast_math,\n nvfp4_4over6_config,\n )\n\n fp4_output = torch.empty(m, k // 2, dtype=torch.uint8, device=input.device)\n scale_output = torch.zeros(\n padded_m * padded_sf_cols, dtype=torch.uint8, device=input.device\n )\n per_token_scale = torch.empty(m, dtype=torch.float32, device=input.device)\n\n kernel_fn(\n input,\n fp4_output,\n scale_output,\n per_token_scale,\n m,\n global_scale_inv_tensor,\n )\n\n scale_output = scale_output.reshape(-1, padded_sf_cols)\n return fp4_output, scale_output, per_token_scale\n\n\n__all__ = [\n \"SF_LAYOUT_128x4\",\n \"SF_LAYOUT_8x4\",\n \"SF_LAYOUT_LINEAR\",\n \"NVFP4QuantizeLinearKernel\",\n \"NVFP4QuantizeSwizzledKernel\",\n \"NVFP4QuantizePerTokenKernel\",\n \"NVFP4QuantizeTMAKernel\",\n \"nvfp4_quantize_cute_dsl\",\n \"silu_and_mul_nvfp4_quantize_cute_dsl\",\n \"nvfp4_quantize_per_token_cute_dsl\",\n \"_get_compiled_kernel_nvfp4\",\n \"_get_compiled_kernel_nvfp4_per_token\",\n \"_get_compiled_kernel_nvfp4_tma\",\n]\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## 📌 Description\n\nRemove the temporary padded input allocation and full-tensor copy from the CuTe DSL NVFP4 TMA path. The TMA tensor map now describes the physical `M` rows and relies on G2S TMA out-of-bounds zero fill for row tiles that extend into the padded scale layout. The FP4 output remains bounded by `M`, while padded scale rows are still explicitly zeroed.\n\nThis keeps the existing TMA pipeline and 128x4 scale layout while eliminating the non-128-aligned `M` copy cliff.\n\n### B200 performance\n\nConfiguration: NVIDIA B200, BF16 input, `K=4096`, 128x4 scale layout, PDL enabled, eager/no CUDA Graph, cold L2, CUPTI timing. Each value is the median of three runs with 20 warmups and 100 measured iterations per run.\n\n| M | Aligned to 128 | TMA + input copy (µs) | Vectorized (µs) | This PR (µs) |\n|---:|:---:|---:|---:|---:|\n| 32283 | No | 212.446 | 62.399 | **59.248** |\n| 32384 | Yes | 59.072 | 62.399 | **59.312** |\n| 32386 | No | 213.054 | 62.367 | **59.151** |\n| 32512 | Yes | 59.375 | 62.431 | **59.184** |\n| 32621 | No | 213.581 | 62.031 | **59.423** |\n| 32640 | Yes | 59.455 | 62.031 | **59.392** |\n| 32733 | No | 213.902 | 62.080 | **59.407** |\n| 32768 | Yes | 59.439 | 61.967 | **59.552** |\n\nFor non-aligned 32K shapes, this reduces API GPU time by 72.1%–72.2% versus TMA with the padded input copy and is 4.2%–5.2% faster than the vectorized path. For aligned shapes, it stays within ±0.41% of the previous TMA path and is 3.9%–5.2% faster than vectorized. `M=6326/6400` remains on the existing vectorized heuristic and is unaffected by this TMA change.\n\nReproduction template:\n\n```bash\nFLASHINFER_NVFP4_QUANTIZE_USE_TMA=1 python3 benchmarks/flashinfer_benchmark.py --routine nvfp4_quantize --backends cute-dsl --m 32283 --k 4096 --input_dtype bfloat16 --global_scale 1.0 --sf_layout 128x4 --sf_vec_size 16 --enable_pdl --no_cuda_graph --dry_run_iters 20 --num_iters 100 --refcheck -vv\n```\n\n## 🔍 Related Issues\n\nRelated to #3905.\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [ ] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see the [pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] Relevant B200 validation is passing: FP16/BF16 partial- and fully-OOB cross-path checks, nonzero-sentinel padding-scale checks, and `compute-sanitizer --tool memcheck` (`ERROR SUMMARY: 0 errors`).\n\n## Reviewer Notes\n\nThe TMA descriptor uses the physical `M`, but the kernel intentionally continues through `padded_M` to initialize the scale layout. The focused regression case uses `M=8193`, which produces one partial TMA tile followed by seven fully-OOB tiles before the 128-row scale boundary.\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n* **Bug Fixes**\n * Improved NVFP4 quantization for inputs whose row count requires padding.\n * Ensured out-of-bounds padded rows are automatically zero-filled during TMA processing.\n * Preserved correct quantization results and scale factors for valid rows.\n\n* **Tests**\n * Added coverage for non-aligned row counts and verified zero values in padded rows.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"K=4096\", \"batch_size\": 32283, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 212.446, \"optimized\": 59.248, \"stated_speedup\": null, \"speedup\": 3.5857}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"K=4096\", \"batch_size\": 32384, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 59.072, \"optimized\": 59.312, \"stated_speedup\": null, \"speedup\": 0.996}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"K=4096\", \"batch_size\": 32386, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 213.054, \"optimized\": 59.151, \"stated_speedup\": null, \"speedup\": 3.6019}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"K=4096\", \"batch_size\": 32512, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 59.375, \"optimized\": 59.184, \"stated_speedup\": null, \"speedup\": 1.0032}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"K=4096\", \"batch_size\": 32621, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 213.581, \"optimized\": 59.423, \"stated_speedup\": null, \"speedup\": 3.5942}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"K=4096\", \"batch_size\": 32640, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 59.455, \"optimized\": 59.392, \"stated_speedup\": null, \"speedup\": 1.0011}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"K=4096\", \"batch_size\": 32733, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 213.902, \"optimized\": 59.407, \"stated_speedup\": null, \"speedup\": 3.6006}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"K=4096\", \"batch_size\": 32768, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 59.439, \"optimized\": 59.552, \"stated_speedup\": null, \"speedup\": 0.9981}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"K=4096\", \"batch_size\": 32283, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 62.399, \"optimized\": 59.248, \"stated_speedup\": 1.052, \"speedup\": 1.0532}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"K=4096\", \"batch_size\": 32386, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 62.367, \"optimized\": 59.151, \"stated_speedup\": 1.052, \"speedup\": 1.0544}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"K=4096\", \"batch_size\": 32621, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 62.031, \"optimized\": 59.423, \"stated_speedup\": 1.042, \"speedup\": 1.0439}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"K=4096\", \"batch_size\": 32733, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 62.08, \"optimized\": 59.407, \"stated_speedup\": 1.042, \"speedup\": 1.045}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"K=4096\", \"batch_size\": 32768, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 61.967, \"optimized\": 59.552, \"stated_speedup\": 1.04, \"speedup\": 1.0406}]"},"kernel_speedup":{"kind":"number","value":1.045,"string":"1.045"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1096,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"496cc1dac3adefb26cb599bd74e2d5efe3a8fcd7"},"date":{"kind":"string","value":"2026-08-03T22:00:20-04:00"},"pr_number":{"kind":"number","value":3523,"string":"3,523"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/3523"},"title":{"kind":"string","value":"perf: remove dead cudaGetDeviceProperties in sm120 groupwise GEMM (#3523)"},"message":{"kind":"string","value":"perf: remove dead cudaGetDeviceProperties in sm120 groupwise GEMM (#3523)\n\n<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\n`CutlassGroupwiseScaledGEMMSM120`\n(`include/flashinfer/gemm/gemm_groupwise_sm120.cuh`) calls\n`cudaGetDevice` + `cudaGetDeviceProperties` on every invocation, but the\nresulting `device_id` and `props` are never read afterwards — the values\nare dead (a capability check appears to have been removed, leaving the\nexpensive query behind).\n\n`cudaGetDeviceProperties` is a synchronous call costing ~1.7 ms/call on\nH200 (CUDA 12.8), so this dead query adds ~1.7 ms to every FP8 groupwise\nGEMM dispatch for no benefit. This PR removes the five dead lines. No\nbehavior change — the values were unused.\n## 🔍 Related Issues\n\n<!-- none -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the\npre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [ ] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\nPure dead-code removal: `device_id` and `props` are not referenced\nanywhere after the query in this function (verified by grep over the\nfile). No functional change.\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n\n## Summary by CodeRabbit\n\n* **Refactor**\n* Optimized internal device compatibility validation for GPU compute\noperations, streamlining the pre-launch capability checking process\nwithout affecting user-facing functionality.\n\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n\nSigned-off-by: Jiading Gai <jiadingg@amazon.com>"},"path":{"kind":"string","value":"include/flashinfer/gemm/gemm_groupwise_sm120.cuh"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * Copyright (c) 2025 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_GEMM_GEMM_GROUPWISE_SM120_CUH_\n#define FLASHINFER_GEMM_GEMM_GROUPWISE_SM120_CUH_\n\n#include <flashinfer/allocator.h>\n\n#include <cassert>\n#include <iostream>\n#include <iterator>\n#include <type_traits>\n#include <typeinfo>\n\n#include \"cutlass/cutlass.h\"\n#include \"cutlass/detail/blockwise_scale_layout.hpp\"\n#include \"cutlass/epilogue/collective/collective_builder.hpp\"\n#include \"cutlass/gemm/collective/collective_builder.hpp\"\n#include \"cutlass/gemm/device/gemm_universal_adapter.h\"\n#include \"cutlass/gemm/kernel/gemm_universal.hpp\"\n#include \"cutlass/util/packed_stride.hpp\"\n\nnamespace flashinfer {\nnamespace gemm {\n\n// SM120 uses Cooperative schedule with 128x128x128 tile shape\ntemplate <int ScaleGranularityM, int ScaleGranularityN, int ScaleGranularityK, bool ScaleMajorK,\n typename DTypeIn, typename DTypeOut>\ncudaError_t CutlassGroupwiseScaledGEMMSM120(void* float_buffer, size_t float_buffer_size_in_bytes,\n DTypeIn* A_ptr, DTypeIn* B_ptr, float* SFA_ptr,\n float* SFB_ptr, DTypeOut* D_ptr, int m, int n, int k,\n int l, cudaStream_t stream) {\n // SM120/SM121 only supports these specific scale granularities\n static_assert(ScaleGranularityM == 1 || ScaleGranularityM == 128,\n \"SM120/SM121 only supports ScaleGranularityM = 1 or 128\");\n static_assert(ScaleGranularityN == 128, \"SM120/SM121 only supports ScaleGranularityN = 128\");\n static_assert(ScaleGranularityK == 128, \"SM120/SM121 only supports ScaleGranularityK = 128\");\n#if defined(CUTLASS_ARCH_MMA_SM120_SUPPORTED) || defined(CUTLASS_ARCH_MMA_SM121_SUPPORTED)\n using namespace cute;\n\n using ElementA = DTypeIn;\n using LayoutA = cutlass::layout::RowMajor;\n constexpr int AlignmentA = 128 / cutlass::sizeof_bits<ElementA>::value;\n\n using ElementB = DTypeIn;\n using LayoutB = cutlass::layout::ColumnMajor;\n constexpr int AlignmentB = 128 / cutlass::sizeof_bits<ElementB>::value;\n\n using ElementC = DTypeOut;\n using LayoutC = cutlass::layout::RowMajor;\n constexpr int AlignmentC = 128 / cutlass::sizeof_bits<ElementC>::value;\n\n using ElementD = ElementC;\n using LayoutD = LayoutC;\n constexpr int AlignmentD = AlignmentC;\n\n using ElementAccumulator = float;\n using ElementCompute = float;\n\n // SM120 uses fixed 128x128x128 tile shape (Cooperative schedule)\n // TODO (yongwww): add PingPong schedule (64x128x128)\n using MmaTileShape_MNK = Shape<_128, _128, _128>;\n using ClusterShape_MNK = Shape<_1, _1, _1>;\n\n // SM120's Sm120BlockwiseScaleConfig takes UMMA::Major parameters based on ScaleMajorK\n using ScaleConfig = std::conditional_t<\n ScaleMajorK,\n cutlass::detail::Sm120BlockwiseScaleConfig<ScaleGranularityM, ScaleGranularityN,\n ScaleGranularityK, UMMA::Major::K, UMMA::Major::K>,\n cutlass::detail::Sm120BlockwiseScaleConfig<ScaleGranularityM, ScaleGranularityN,\n ScaleGranularityK, UMMA::Major::MN,\n UMMA::Major::MN>>;\n\n // Use decltype like SM100 does for consistency\n using LayoutSFA = decltype(ScaleConfig::deduce_layoutSFA());\n using LayoutSFB = decltype(ScaleConfig::deduce_layoutSFB());\n\n using CollectiveEpilogue = typename cutlass::epilogue::collective::CollectiveBuilder<\n cutlass::arch::Sm120, cutlass::arch::OpClassTensorOp, MmaTileShape_MNK, ClusterShape_MNK,\n cutlass::epilogue::collective::EpilogueTileAuto, ElementAccumulator, ElementCompute, ElementC,\n LayoutC, AlignmentC, ElementD, LayoutD, AlignmentD,\n cutlass::epilogue::collective::EpilogueScheduleAuto>::CollectiveOp;\n\n // SM120 uses automatic stage count with epilogue carveout\n using StageCount = cutlass::gemm::collective::StageCountAutoCarveout<static_cast<int>(\n sizeof(typename CollectiveEpilogue::SharedStorage))>;\n\n using CollectiveMainloop = typename cutlass::gemm::collective::CollectiveBuilder<\n cutlass::arch::Sm120, cutlass::arch::OpClassTensorOp, ElementA,\n cute::tuple<LayoutA, LayoutSFA>, AlignmentA, ElementB, cute::tuple<LayoutB, LayoutSFB>,\n AlignmentB, ElementAccumulator, MmaTileShape_MNK, ClusterShape_MNK, StageCount,\n cutlass::gemm::KernelScheduleSm120Blockwise>::CollectiveOp;\n\n using GemmKernel =\n cutlass::gemm::kernel::GemmUniversal<Shape<int, int, int, int>, CollectiveMainloop,\n CollectiveEpilogue, void>;\n\n using Gemm = cutlass::gemm::device::GemmUniversalAdapter<GemmKernel>;\n\n using StrideA = typename Gemm::GemmKernel::StrideA;\n using StrideB = typename Gemm::GemmKernel::StrideB;\n using StrideC = typename Gemm::GemmKernel::StrideC;\n using StrideD = typename Gemm::GemmKernel::StrideD;\n\n auto stride_A = cutlass::make_cute_packed_stride(StrideA{}, cute::make_shape(m, k, l));\n auto stride_B = cutlass::make_cute_packed_stride(StrideB{}, cute::make_shape(n, k, l));\n auto stride_C = cutlass::make_cute_packed_stride(StrideC{}, cute::make_shape(m, n, l));\n auto stride_D = cutlass::make_cute_packed_stride(StrideD{}, cute::make_shape(m, n, l));\n\n auto layout_SFA = ScaleConfig::tile_atom_to_shape_SFA(cute::make_shape(m, n, k, l));\n auto layout_SFB = ScaleConfig::tile_atom_to_shape_SFB(cute::make_shape(m, n, k, l));\n\n // For beta=0 case, C and D can be the same buffer\n DTypeOut* C_ptr = D_ptr; // Use D as both input and output when beta=0\n\n typename Gemm::Arguments arguments{\n cutlass::gemm::GemmUniversalMode::kGemm,\n {m, n, k, l},\n {A_ptr, stride_A, B_ptr, stride_B, SFA_ptr, layout_SFA, SFB_ptr, layout_SFB},\n {{}, C_ptr, stride_C, D_ptr, stride_D}}; // C and D point to same buffer when beta=0\n\n // Set alpha and beta for the epilogue\n arguments.epilogue.thread.alpha = 1.0f;\n arguments.epilogue.thread.beta = 0.0f;\n\n // Check device compute capability first\n int device_id = 0;\n cudaGetDevice(&device_id);\n cudaDeviceProp props;\n cudaGetDeviceProperties(&props, device_id);\n\n Gemm gemm;\n\n cutlass::Status status = gemm.can_implement(arguments);\n if (status != cutlass::Status::kSuccess) {\n return cudaErrorNotSupported;\n }\n\n size_t workspace_size = Gemm::get_workspace_size(arguments);\n\n if (workspace_size > float_buffer_size_in_bytes) {\n return cudaErrorInsufficientDriver;\n }\n\n // Pass workspace pointer only if needed\n void* kernel_workspace = nullptr;\n if (workspace_size > 0) { // Only provide a pointer if workspace is actually needed\n kernel_workspace = float_buffer;\n }\n\n status = gemm.initialize(arguments, kernel_workspace);\n if (status != cutlass::Status::kSuccess) {\n // Don't continue if initialization failed\n return cudaErrorNotSupported;\n }\n\n status = gemm.run(stream);\n if (status != cutlass::Status::kSuccess) {\n return cudaErrorUnknown;\n }\n\n return cudaSuccess;\n#else\n return cudaErrorNotSupported;\n#endif\n}\n\n} // namespace gemm\n} // namespace flashinfer\n\n#endif // FLASHINFER_GEMM_GEMM_GROUPWISE_SM120_CUH_\n"},"after_code":{"kind":"string","value":"/*\n * Copyright (c) 2025 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_GEMM_GEMM_GROUPWISE_SM120_CUH_\n#define FLASHINFER_GEMM_GEMM_GROUPWISE_SM120_CUH_\n\n#include <flashinfer/allocator.h>\n\n#include <cassert>\n#include <iostream>\n#include <iterator>\n#include <type_traits>\n#include <typeinfo>\n\n#include \"cutlass/cutlass.h\"\n#include \"cutlass/detail/blockwise_scale_layout.hpp\"\n#include \"cutlass/epilogue/collective/collective_builder.hpp\"\n#include \"cutlass/gemm/collective/collective_builder.hpp\"\n#include \"cutlass/gemm/device/gemm_universal_adapter.h\"\n#include \"cutlass/gemm/kernel/gemm_universal.hpp\"\n#include \"cutlass/util/packed_stride.hpp\"\n\nnamespace flashinfer {\nnamespace gemm {\n\n// SM120 uses Cooperative schedule with 128x128x128 tile shape\ntemplate <int ScaleGranularityM, int ScaleGranularityN, int ScaleGranularityK, bool ScaleMajorK,\n typename DTypeIn, typename DTypeOut>\ncudaError_t CutlassGroupwiseScaledGEMMSM120(void* float_buffer, size_t float_buffer_size_in_bytes,\n DTypeIn* A_ptr, DTypeIn* B_ptr, float* SFA_ptr,\n float* SFB_ptr, DTypeOut* D_ptr, int m, int n, int k,\n int l, cudaStream_t stream) {\n // SM120/SM121 only supports these specific scale granularities\n static_assert(ScaleGranularityM == 1 || ScaleGranularityM == 128,\n \"SM120/SM121 only supports ScaleGranularityM = 1 or 128\");\n static_assert(ScaleGranularityN == 128, \"SM120/SM121 only supports ScaleGranularityN = 128\");\n static_assert(ScaleGranularityK == 128, \"SM120/SM121 only supports ScaleGranularityK = 128\");\n#if defined(CUTLASS_ARCH_MMA_SM120_SUPPORTED) || defined(CUTLASS_ARCH_MMA_SM121_SUPPORTED)\n using namespace cute;\n\n using ElementA = DTypeIn;\n using LayoutA = cutlass::layout::RowMajor;\n constexpr int AlignmentA = 128 / cutlass::sizeof_bits<ElementA>::value;\n\n using ElementB = DTypeIn;\n using LayoutB = cutlass::layout::ColumnMajor;\n constexpr int AlignmentB = 128 / cutlass::sizeof_bits<ElementB>::value;\n\n using ElementC = DTypeOut;\n using LayoutC = cutlass::layout::RowMajor;\n constexpr int AlignmentC = 128 / cutlass::sizeof_bits<ElementC>::value;\n\n using ElementD = ElementC;\n using LayoutD = LayoutC;\n constexpr int AlignmentD = AlignmentC;\n\n using ElementAccumulator = float;\n using ElementCompute = float;\n\n // SM120 uses fixed 128x128x128 tile shape (Cooperative schedule)\n // TODO (yongwww): add PingPong schedule (64x128x128)\n using MmaTileShape_MNK = Shape<_128, _128, _128>;\n using ClusterShape_MNK = Shape<_1, _1, _1>;\n\n // SM120's Sm120BlockwiseScaleConfig takes UMMA::Major parameters based on ScaleMajorK\n using ScaleConfig = std::conditional_t<\n ScaleMajorK,\n cutlass::detail::Sm120BlockwiseScaleConfig<ScaleGranularityM, ScaleGranularityN,\n ScaleGranularityK, UMMA::Major::K, UMMA::Major::K>,\n cutlass::detail::Sm120BlockwiseScaleConfig<ScaleGranularityM, ScaleGranularityN,\n ScaleGranularityK, UMMA::Major::MN,\n UMMA::Major::MN>>;\n\n // Use decltype like SM100 does for consistency\n using LayoutSFA = decltype(ScaleConfig::deduce_layoutSFA());\n using LayoutSFB = decltype(ScaleConfig::deduce_layoutSFB());\n\n using CollectiveEpilogue = typename cutlass::epilogue::collective::CollectiveBuilder<\n cutlass::arch::Sm120, cutlass::arch::OpClassTensorOp, MmaTileShape_MNK, ClusterShape_MNK,\n cutlass::epilogue::collective::EpilogueTileAuto, ElementAccumulator, ElementCompute, ElementC,\n LayoutC, AlignmentC, ElementD, LayoutD, AlignmentD,\n cutlass::epilogue::collective::EpilogueScheduleAuto>::CollectiveOp;\n\n // SM120 uses automatic stage count with epilogue carveout\n using StageCount = cutlass::gemm::collective::StageCountAutoCarveout<static_cast<int>(\n sizeof(typename CollectiveEpilogue::SharedStorage))>;\n\n using CollectiveMainloop = typename cutlass::gemm::collective::CollectiveBuilder<\n cutlass::arch::Sm120, cutlass::arch::OpClassTensorOp, ElementA,\n cute::tuple<LayoutA, LayoutSFA>, AlignmentA, ElementB, cute::tuple<LayoutB, LayoutSFB>,\n AlignmentB, ElementAccumulator, MmaTileShape_MNK, ClusterShape_MNK, StageCount,\n cutlass::gemm::KernelScheduleSm120Blockwise>::CollectiveOp;\n\n using GemmKernel =\n cutlass::gemm::kernel::GemmUniversal<Shape<int, int, int, int>, CollectiveMainloop,\n CollectiveEpilogue, void>;\n\n using Gemm = cutlass::gemm::device::GemmUniversalAdapter<GemmKernel>;\n\n using StrideA = typename Gemm::GemmKernel::StrideA;\n using StrideB = typename Gemm::GemmKernel::StrideB;\n using StrideC = typename Gemm::GemmKernel::StrideC;\n using StrideD = typename Gemm::GemmKernel::StrideD;\n\n auto stride_A = cutlass::make_cute_packed_stride(StrideA{}, cute::make_shape(m, k, l));\n auto stride_B = cutlass::make_cute_packed_stride(StrideB{}, cute::make_shape(n, k, l));\n auto stride_C = cutlass::make_cute_packed_stride(StrideC{}, cute::make_shape(m, n, l));\n auto stride_D = cutlass::make_cute_packed_stride(StrideD{}, cute::make_shape(m, n, l));\n\n auto layout_SFA = ScaleConfig::tile_atom_to_shape_SFA(cute::make_shape(m, n, k, l));\n auto layout_SFB = ScaleConfig::tile_atom_to_shape_SFB(cute::make_shape(m, n, k, l));\n\n // For beta=0 case, C and D can be the same buffer\n DTypeOut* C_ptr = D_ptr; // Use D as both input and output when beta=0\n\n typename Gemm::Arguments arguments{\n cutlass::gemm::GemmUniversalMode::kGemm,\n {m, n, k, l},\n {A_ptr, stride_A, B_ptr, stride_B, SFA_ptr, layout_SFA, SFB_ptr, layout_SFB},\n {{}, C_ptr, stride_C, D_ptr, stride_D}}; // C and D point to same buffer when beta=0\n\n // Set alpha and beta for the epilogue\n arguments.epilogue.thread.alpha = 1.0f;\n arguments.epilogue.thread.beta = 0.0f;\n\n Gemm gemm;\n\n cutlass::Status status = gemm.can_implement(arguments);\n if (status != cutlass::Status::kSuccess) {\n return cudaErrorNotSupported;\n }\n\n size_t workspace_size = Gemm::get_workspace_size(arguments);\n\n if (workspace_size > float_buffer_size_in_bytes) {\n return cudaErrorInsufficientDriver;\n }\n\n // Pass workspace pointer only if needed\n void* kernel_workspace = nullptr;\n if (workspace_size > 0) { // Only provide a pointer if workspace is actually needed\n kernel_workspace = float_buffer;\n }\n\n status = gemm.initialize(arguments, kernel_workspace);\n if (status != cutlass::Status::kSuccess) {\n // Don't continue if initialization failed\n return cudaErrorNotSupported;\n }\n\n status = gemm.run(stream);\n if (status != cutlass::Status::kSuccess) {\n return cudaErrorUnknown;\n }\n\n return cudaSuccess;\n#else\n return cudaErrorNotSupported;\n#endif\n}\n\n} // namespace gemm\n} // namespace flashinfer\n\n#endif // FLASHINFER_GEMM_GEMM_GROUPWISE_SM120_CUH_\n"},"diff":{"kind":"string","value":"--- include/flashinfer/gemm/gemm_groupwise_sm120.cuh\n+++ include/flashinfer/gemm/gemm_groupwise_sm120.cuh\n@@ -135,12 +135,6 @@\n arguments.epilogue.thread.alpha = 1.0f;\n arguments.epilogue.thread.beta = 0.0f;\n \n- // Check device compute capability first\n- int device_id = 0;\n- cudaGetDevice(&device_id);\n- cudaDeviceProp props;\n- cudaGetDeviceProperties(&props, device_id);\n-\n Gemm gemm;\n \n cutlass::Status status = gemm.can_implement(arguments);"},"lines_added":{"kind":"number","value":0,"string":"0"},"lines_removed":{"kind":"number","value":6,"string":"6"},"files_in_commit":{"kind":"number","value":1,"string":"1"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["H200","SM120"],"string":"[\n \"H200\",\n \"SM120\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (include/flashinfer/gemm/gemm_groupwise_sm120.cuh).\n\nGoal: perf: remove dead cudaGetDeviceProperties in sm120 groupwise GEMM\nTarget hardware: H200, SM120\nTarget models: unspecified\n\nCurrent file:\n```cuda\n/*\n * Copyright (c) 2025 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_GEMM_GEMM_GROUPWISE_SM120_CUH_\n#define FLASHINFER_GEMM_GEMM_GROUPWISE_SM120_CUH_\n\n#include <flashinfer/allocator.h>\n\n#include <cassert>\n#include <iostream>\n#include <iterator>\n#include <type_traits>\n#include <typeinfo>\n\n#include \"cutlass/cutlass.h\"\n#include \"cutlass/detail/blockwise_scale_layout.hpp\"\n#include \"cutlass/epilogue/collective/collective_builder.hpp\"\n#include \"cutlass/gemm/collective/collective_builder.hpp\"\n#include \"cutlass/gemm/device/gemm_universal_adapter.h\"\n#include \"cutlass/gemm/kernel/gemm_universal.hpp\"\n#include \"cutlass/util/packed_stride.hpp\"\n\nnamespace flashinfer {\nnamespace gemm {\n\n// SM120 uses Cooperative schedule with 128x128x128 tile shape\ntemplate <int ScaleGranularityM, int ScaleGranularityN, int ScaleGranularityK, bool ScaleMajorK,\n typename DTypeIn, typename DTypeOut>\ncudaError_t CutlassGroupwiseScaledGEMMSM120(void* float_buffer, size_t float_buffer_size_in_bytes,\n DTypeIn* A_ptr, DTypeIn* B_ptr, float* SFA_ptr,\n float* SFB_ptr, DTypeOut* D_ptr, int m, int n, int k,\n int l, cudaStream_t stream) {\n // SM120/SM121 only supports these specific scale granularities\n static_assert(ScaleGranularityM == 1 || ScaleGranularityM == 128,\n \"SM120/SM121 only supports ScaleGranularityM = 1 or 128\");\n static_assert(ScaleGranularityN == 128, \"SM120/SM121 only supports ScaleGranularityN = 128\");\n static_assert(ScaleGranularityK == 128, \"SM120/SM121 only supports ScaleGranularityK = 128\");\n#if defined(CUTLASS_ARCH_MMA_SM120_SUPPORTED) || defined(CUTLASS_ARCH_MMA_SM121_SUPPORTED)\n using namespace cute;\n\n using ElementA = DTypeIn;\n using LayoutA = cutlass::layout::RowMajor;\n constexpr int AlignmentA = 128 / cutlass::sizeof_bits<ElementA>::value;\n\n using ElementB = DTypeIn;\n using LayoutB = cutlass::layout::ColumnMajor;\n constexpr int AlignmentB = 128 / cutlass::sizeof_bits<ElementB>::value;\n\n using ElementC = DTypeOut;\n using LayoutC = cutlass::layout::RowMajor;\n constexpr int AlignmentC = 128 / cutlass::sizeof_bits<ElementC>::value;\n\n using ElementD = ElementC;\n using LayoutD = LayoutC;\n constexpr int AlignmentD = AlignmentC;\n\n using ElementAccumulator = float;\n using ElementCompute = float;\n\n // SM120 uses fixed 128x128x128 tile shape (Cooperative schedule)\n // TODO (yongwww): add PingPong schedule (64x128x128)\n using MmaTileShape_MNK = Shape<_128, _128, _128>;\n using ClusterShape_MNK = Shape<_1, _1, _1>;\n\n // SM120's Sm120BlockwiseScaleConfig takes UMMA::Major parameters based on ScaleMajorK\n using ScaleConfig = std::conditional_t<\n ScaleMajorK,\n cutlass::detail::Sm120BlockwiseScaleConfig<ScaleGranularityM, ScaleGranularityN,\n ScaleGranularityK, UMMA::Major::K, UMMA::Major::K>,\n cutlass::detail::Sm120BlockwiseScaleConfig<ScaleGranularityM, ScaleGranularityN,\n ScaleGranularityK, UMMA::Major::MN,\n UMMA::Major::MN>>;\n\n // Use decltype like SM100 does for consistency\n using LayoutSFA = decltype(ScaleConfig::deduce_layoutSFA());\n using LayoutSFB = decltype(ScaleConfig::deduce_layoutSFB());\n\n using CollectiveEpilogue = typename cutlass::epilogue::collective::CollectiveBuilder<\n cutlass::arch::Sm120, cutlass::arch::OpClassTensorOp, MmaTileShape_MNK, ClusterShape_MNK,\n cutlass::epilogue::collective::EpilogueTileAuto, ElementAccumulator, ElementCompute, ElementC,\n LayoutC, AlignmentC, ElementD, LayoutD, AlignmentD,\n cutlass::epilogue::collective::EpilogueScheduleAuto>::CollectiveOp;\n\n // SM120 uses automatic stage count with epilogue carveout\n using StageCount = cutlass::gemm::collective::StageCountAutoCarveout<static_cast<int>(\n sizeof(typename CollectiveEpilogue::SharedStorage))>;\n\n using CollectiveMainloop = typename cutlass::gemm::collective::CollectiveBuilder<\n cutlass::arch::Sm120, cutlass::arch::OpClassTensorOp, ElementA,\n cute::tuple<LayoutA, LayoutSFA>, AlignmentA, ElementB, cute::tuple<LayoutB, LayoutSFB>,\n AlignmentB, ElementAccumulator, MmaTileShape_MNK, ClusterShape_MNK, StageCount,\n cutlass::gemm::KernelScheduleSm120Blockwise>::CollectiveOp;\n\n using GemmKernel =\n cutlass::gemm::kernel::GemmUniversal<Shape<int, int, int, int>, CollectiveMainloop,\n CollectiveEpilogue, void>;\n\n using Gemm = cutlass::gemm::device::GemmUniversalAdapter<GemmKernel>;\n\n using StrideA = typename Gemm::GemmKernel::StrideA;\n using StrideB = typename Gemm::GemmKernel::StrideB;\n using StrideC = typename Gemm::GemmKernel::StrideC;\n using StrideD = typename Gemm::GemmKernel::StrideD;\n\n auto stride_A = cutlass::make_cute_packed_stride(StrideA{}, cute::make_shape(m, k, l));\n auto stride_B = cutlass::make_cute_packed_stride(StrideB{}, cute::make_shape(n, k, l));\n auto stride_C = cutlass::make_cute_packed_stride(StrideC{}, cute::make_shape(m, n, l));\n auto stride_D = cutlass::make_cute_packed_stride(StrideD{}, cute::make_shape(m, n, l));\n\n auto layout_SFA = ScaleConfig::tile_atom_to_shape_SFA(cute::make_shape(m, n, k, l));\n auto layout_SFB = ScaleConfig::tile_atom_to_shape_SFB(cute::make_shape(m, n, k, l));\n\n // For beta=0 case, C and D can be the same buffer\n DTypeOut* C_ptr = D_ptr; // Use D as both input and output when beta=0\n\n typename Gemm::Arguments arguments{\n cutlass::gemm::GemmUniversalMode::kGemm,\n {m, n, k, l},\n {A_ptr, stride_A, B_ptr, stride_B, SFA_ptr, layout_SFA, SFB_ptr, layout_SFB},\n {{}, C_ptr, stride_C, D_ptr, stride_D}}; // C and D point to same buffer when beta=0\n\n // Set alpha and beta for the epilogue\n arguments.epilogue.thread.alpha = 1.0f;\n arguments.epilogue.thread.beta = 0.0f;\n\n // Check device compute capability first\n int device_id = 0;\n cudaGetDevice(&device_id);\n cudaDeviceProp props;\n cudaGetDeviceProperties(&props, device_id);\n\n Gemm gemm;\n\n cutlass::Status status = gemm.can_implement(arguments);\n if (status != cutlass::Status::kSuccess) {\n return cudaErrorNotSupported;\n }\n\n size_t workspace_size = Gemm::get_workspace_size(arguments);\n\n if (workspace_size > float_buffer_size_in_bytes) {\n return cudaErrorInsufficientDriver;\n }\n\n // Pass workspace pointer only if needed\n void* kernel_workspace = nullptr;\n if (workspace_size > 0) { // Only provide a pointer if workspace is actually needed\n kernel_workspace = float_buffer;\n }\n\n status = gemm.initialize(arguments, kernel_workspace);\n if (status != cutlass::Status::kSuccess) {\n // Don't continue if initialization failed\n return cudaErrorNotSupported;\n }\n\n status = gemm.run(stream);\n if (status != cutlass::Status::kSuccess) {\n return cudaErrorUnknown;\n }\n\n return cudaSuccess;\n#else\n return cudaErrorNotSupported;\n#endif\n}\n\n} // namespace gemm\n} // namespace flashinfer\n\n#endif // FLASHINFER_GEMM_GEMM_GROUPWISE_SM120_CUH_\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\n`CutlassGroupwiseScaledGEMMSM120` (`include/flashinfer/gemm/gemm_groupwise_sm120.cuh`) calls `cudaGetDevice` + `cudaGetDeviceProperties` on every invocation, but the resulting `device_id` and `props` are never read afterwards — the values are dead (a capability check appears to have been removed, leaving the expensive query behind).\n\n`cudaGetDeviceProperties` is a synchronous call costing ~1.7 ms/call on H200 (CUDA 12.8), so this dead query adds ~1.7 ms to every FP8 groupwise GEMM dispatch for no benefit. This PR removes the five dead lines. No behavior change — the values were unused.\n## 🔍 Related Issues\n\n<!-- none -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [ ] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\nPure dead-code removal: `device_id` and `props` are not referenced anywhere after the query in this function (verified by grep over the file). No functional change.\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n\n## Summary by CodeRabbit\n\n* **Refactor**\n * Optimized internal device compatibility validation for GPU compute operations, streamlining the pre-launch capability checking process without affecting user-facing functionality.\n\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1097,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"5a4b54bed1dfe6f112cd4ec9bc196da517369f46"},"date":{"kind":"string","value":"2026-08-03T14:43:37-07:00"},"pr_number":{"kind":"number","value":4285,"string":"4,285"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/4285"},"title":{"kind":"string","value":"perf(moe): sync SM12x NVFP4 fused-MoE kernels to b12x HEAD (#4285)"},"message":{"kind":"string","value":"perf(moe): sync SM12x NVFP4 fused-MoE kernels to b12x HEAD (#4285)\n\n## 📌 Description\n\nSyncs the SM12x NVFP4 (W4A4) fused-MoE kernels behind `b12x_fused_moe`\nand `B12xMoEWrapper` with upstream\n[b12x](https://github.com/local-inference-lab/sparkinfer) at `f9be272`,\nreaching backend parity.\n\nThe module now has four kernels. `MoEDirectMicroKernel` takes the\nsmallest decode batches, `MoEMicroKernel` and `MoEStaticKernel` cover\nthe rest of decode with tile assignments fixed at launch, and\n`MoEDynamicKernel` covers prefill by distributing tiles through an\nin-kernel work queue.\n\nChanges:\n\n- Adopt upstream's current `MoEDirectMicroKernel`, replacing a stale\ncopy in `moe_direct_micro_kernel.py` that was never routed to. It reads\nthe top-k ids directly, so the smallest batches skip the routing\npre-pass that dominates their runtime, and it now supports gelu_tanh.\n- Let `MoEDynamicKernel` use tiles smaller than 128 rows, so sparse\nrouting stops padding every expert up to 128.\n- Launch all kernels cooperatively. They synchronize the whole grid\nbetween phases, which deadlocks if concurrent work keeps part of the\ngrid off the GPU.\n- Simplify `MoEDynamicKernel`'s work queue and size its pipeline stages\nfrom the real shared-memory footprint.\n- Vectorize `MoEStaticKernel`'s scatter epilogue and refresh the decode\ntile heuristics.\n- Restrict the fast FP4 quantizer to gated activations, since relu2's\nsquared outputs need the exact one.\n\nPublic API and behavior changes: none.\n\n## 📊 Performance\n\nVersus main, measured over 38 target-model MoE shapes on three GPUs.\nGeomean speedup per shape group:\n\n| shape group | DGX Spark | RTX 5080 | RTX Pro 6000 SE |\n|---|---|---|---|\n| decode, batch 1-2 | 1.06x | 1.30x | 1.40x |\n| decode, batch 4-40 | 1.00x | 1.00x | 1.00x |\n| prefill, batch 512-2048 | 1.10x | 1.10x | 1.09x |\n| prefill, batch 8192 | 1.00x | 1.00x | 1.00x |\n\n- The batch 1-2 gains come from the new `MoEDirectMicroKernel`; the\nshapes it serves win up to 2.3x.\n- The prefill gains come from `MoEDynamicKernel` picking tiles smaller\nthan 128 rows; those shapes win up to 1.26x.\n\n## 🔍 Related Issues\n\n#4223 (item 2).\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n## 🧪 Tests\n\n- On SM121 (DGX Spark GB10): `tests/moe/test_b12x_fused_moe.py` (157\ncases) and `tests/moe/test_unified_moe_b12x.py` (58 cases) pass,\nincluding tests that force each backend and a test that a smaller tile\nis picked again after a large-batch call.\n\n## Reviewer Notes\n\nDeviations from the b12x source, beyond import plumbing:\n\n- gelu_tanh added to `MoEDirectMicroKernel`, matching the activation\ncoverage of the module's other kernels.\n- The module's API accepts reciprocal-form scales but upstream's kernel\nonly takes multipliers, so dispatch inverts them before launch.\n- `MoEDirectMicroKernel`'s cutover is re-measured: upstream's only\nalternative is its counterpart of `MoEDynamicKernel`, while here it\ncompetes with `MoEMicroKernel` and `MoEStaticKernel`.\n- Upstream sizes scratch and builds the kernel together inside one plan\nobject, so their tile sizes always match. FlashInfer has no plan object,\nso the workspace cache is keyed by tile size to give the same guarantee.\n\n🤖 Generated with [Claude Code](https://claude.com/claude-code)\n\n---------\n\nCo-authored-by: Claude Fable 5 <noreply@anthropic.com>\nCo-authored-by: Brian K. Ryu <bryu@nvidia.com>"},"path":{"kind":"string","value":"flashinfer/cute_dsl/fp4_common.py"},"language":{"kind":"string","value":"cute_dsl"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"\"\"\"\nCopyright (c) 2025 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nCommon utilities for FP4 quantization kernels using CuTe-DSL.\n\nThis module contains shared PTX intrinsics, helper functions, and reduction\nutilities used by both rmsnorm_fp4quant.py and add_rmsnorm_fp4quant.py.\n\"\"\"\n\nimport functools\nimport math\nimport operator\nfrom typing import Callable, Tuple\n\nimport cutlass\nimport cutlass.cute as cute\nimport torch\nfrom cutlass import Float32, Int32, Int64, Uint8, Uint32, Uint64\nfrom cutlass.cutlass_dsl import T, dsl_user_op\nfrom cutlass._mlir import ir\nfrom cutlass._mlir.dialects import llvm\n\n\n# =============================================================================\n# Constants\n# =============================================================================\n\nFLOAT4_E2M1_MAX = 6.0 # Maximum value representable in FP4 E2M1\nFLOAT8_E4M3_MAX = 448.0 # Maximum value representable in FP8 E4M3\nSF_VEC_SIZE = 16 # Elements per scale factor block\nCOPY_BITS = 128 # 128-bit vectorized loads\n\n\n# =============================================================================\n# Architecture Detection\n# =============================================================================\n\n\n@functools.lru_cache(maxsize=16)\ndef get_sm_version(device: int | torch.device | str | None = None) -> int:\n \"\"\"Get the SM version of a CUDA device.\n\n Args:\n device: CUDA device to query. Can be an int (device index), torch.device,\n device string (e.g., 'cuda:0'), or None to use current device.\n\n Returns:\n SM version as an integer (e.g., 100 for SM100).\n \"\"\"\n if not torch.cuda.is_available():\n return 80\n if device is None:\n device = torch.cuda.current_device()\n props = torch.cuda.get_device_properties(device)\n return props.major * 10 + props.minor\n\n\n# =============================================================================\n# PTX Intrinsics - Cluster Operations\n# =============================================================================\n\n\n@dsl_user_op\ndef set_block_rank(\n smem_ptr: cute.Pointer, peer_cta_rank_in_cluster: Int32, *, loc=None, ip=None\n) -> Int32:\n \"\"\"Map smem pointer to address at another CTA rank in the cluster.\"\"\"\n smem_ptr_i32 = smem_ptr.toint(loc=loc, ip=ip).ir_value()\n return Int32(\n llvm.inline_asm(\n T.i32(),\n [smem_ptr_i32, peer_cta_rank_in_cluster.ir_value()],\n \"mapa.shared::cluster.u32 $0, $1, $2;\",\n \"=r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef store_shared_remote(\n val: Float32,\n smem_ptr: cute.Pointer,\n mbar_ptr: cute.Pointer,\n peer_cta_rank_in_cluster: Int32,\n *,\n loc=None,\n ip=None,\n) -> None:\n \"\"\"Store Float32 value to shared memory on a remote CTA in the cluster.\"\"\"\n remote_smem_ptr_i32 = set_block_rank(\n smem_ptr, peer_cta_rank_in_cluster, loc=loc, ip=ip\n ).ir_value()\n remote_mbar_ptr_i32 = set_block_rank(\n mbar_ptr, peer_cta_rank_in_cluster, loc=loc, ip=ip\n ).ir_value()\n llvm.inline_asm(\n None,\n [remote_smem_ptr_i32, val.ir_value(loc=loc, ip=ip), remote_mbar_ptr_i32],\n \"st.async.shared::cluster.mbarrier::complete_tx::bytes.f32 [$0], $1, [$2];\",\n \"r,f,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n\n\n@dsl_user_op\ndef elem_pointer(x: cute.Tensor, coord, *, loc=None, ip=None) -> cute.Pointer:\n \"\"\"Get pointer to element at coordinate in tensor.\"\"\"\n return x.iterator + cute.crd2idx(coord, x.layout, loc=loc, ip=ip)\n\n\n# =============================================================================\n# PTX Intrinsics - 128-bit Vectorized Global Loads/Stores\n# =============================================================================\n\n\n@dsl_user_op\ndef ld_global_v4_u32(\n base_ptr: Int64, *, loc=None, ip=None\n) -> Tuple[Uint32, Uint32, Uint32, Uint32]:\n \"\"\"Load 128 bits (4 x uint32) from global memory.\"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.i32(), T.i32(), T.i32(), T.i32()]),\n [Int64(base_ptr).ir_value(loc=loc, ip=ip)],\n \"ld.global.v4.u32 {$0, $1, $2, $3}, [$4];\",\n \"=r,=r,=r,=r,l\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n v0 = llvm.extractvalue(T.i32(), result, [0], loc=loc, ip=ip)\n v1 = llvm.extractvalue(T.i32(), result, [1], loc=loc, ip=ip)\n v2 = llvm.extractvalue(T.i32(), result, [2], loc=loc, ip=ip)\n v3 = llvm.extractvalue(T.i32(), result, [3], loc=loc, ip=ip)\n\n return Uint32(v0), Uint32(v1), Uint32(v2), Uint32(v3)\n\n\n@dsl_user_op\ndef ld_v4_u32(\n base_ptr: Int64, *, loc=None, ip=None\n) -> Tuple[Uint32, Uint32, Uint32, Uint32]:\n \"\"\"Load 128 bits (4 x uint32) using generic addressing (works for GMEM and SMEM).\"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.i32(), T.i32(), T.i32(), T.i32()]),\n [Int64(base_ptr).ir_value(loc=loc, ip=ip)],\n \"ld.v4.u32 {$0, $1, $2, $3}, [$4];\",\n \"=r,=r,=r,=r,l\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n v0 = llvm.extractvalue(T.i32(), result, [0], loc=loc, ip=ip)\n v1 = llvm.extractvalue(T.i32(), result, [1], loc=loc, ip=ip)\n v2 = llvm.extractvalue(T.i32(), result, [2], loc=loc, ip=ip)\n v3 = llvm.extractvalue(T.i32(), result, [3], loc=loc, ip=ip)\n\n return Uint32(v0), Uint32(v1), Uint32(v2), Uint32(v3)\n\n\n@dsl_user_op\ndef ld_global_nc_u32(base_ptr: Int64, *, loc=None, ip=None) -> Uint32:\n \"\"\"Load 32 bits from global memory through the non-coherent cache.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Int64(base_ptr).ir_value(loc=loc, ip=ip)],\n \"ld.global.nc.u32 $0, [$1];\",\n \"=r,l\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef ld_global_nc_v4_u32(\n base_ptr: Int64, *, loc=None, ip=None\n) -> Tuple[Uint32, Uint32, Uint32, Uint32]:\n \"\"\"Load 128 bits from global memory through the non-coherent cache.\"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.i32(), T.i32(), T.i32(), T.i32()]),\n [Int64(base_ptr).ir_value(loc=loc, ip=ip)],\n \"ld.global.nc.v4.u32 {$0, $1, $2, $3}, [$4];\",\n \"=r,=r,=r,=r,l\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n return (\n Uint32(llvm.extractvalue(T.i32(), result, [0], loc=loc, ip=ip)),\n Uint32(llvm.extractvalue(T.i32(), result, [1], loc=loc, ip=ip)),\n Uint32(llvm.extractvalue(T.i32(), result, [2], loc=loc, ip=ip)),\n Uint32(llvm.extractvalue(T.i32(), result, [3], loc=loc, ip=ip)),\n )\n\n\n@dsl_user_op\ndef st_global_u64(base_ptr: Int64, value: Uint64, *, loc=None, ip=None):\n \"\"\"Store 64 bits to global memory.\"\"\"\n llvm.inline_asm(\n None,\n [\n Int64(base_ptr).ir_value(loc=loc, ip=ip),\n Uint64(value).ir_value(loc=loc, ip=ip),\n ],\n \"st.global.u64 [$0], $1;\",\n \"l,l\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n\n\n@dsl_user_op\ndef st_global_u32(base_ptr: Int64, value: Uint32, *, loc=None, ip=None):\n \"\"\"Store 32 bits to global memory.\"\"\"\n llvm.inline_asm(\n None,\n [\n Int64(base_ptr).ir_value(loc=loc, ip=ip),\n Uint32(value).ir_value(loc=loc, ip=ip),\n ],\n \"st.global.u32 [$0], $1;\",\n \"l,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n\n\n@dsl_user_op\ndef get_ptr_as_int64(tensor: cute.Tensor, offset: Int32, *, loc=None, ip=None) -> Int64:\n \"\"\"Get the memory address of tensor[offset] as Int64.\n\n WARNING: This uses ptrtoint which strips address space information.\n For SMEM tensors, the resulting Int64 is a raw SMEM offset that does NOT\n work with generic-addressing loads (ld.v4.u32). Use only with explicit\n address-space loads (ld.global.*) or for global memory tensors.\n \"\"\"\n elem_ptr = tensor.iterator + Int32(offset)\n ptr_int = llvm.ptrtoint(T.i64(), elem_ptr.llvm_ptr, loc=loc, ip=ip)\n return Int64(ptr_int)\n\n\n@dsl_user_op\ndef get_smem_ptr_as_int32(\n tensor: cute.Tensor, offset: Int32, *, loc=None, ip=None\n) -> Int32:\n \"\"\"Get the shared-memory byte address of tensor[offset] as Int32.\n\n Uses Pointer.toint() which preserves the SMEM address space (addrspace 3),\n returning a 32-bit SMEM address suitable for ld.shared.* instructions.\n \"\"\"\n elem_ptr = tensor.iterator + Int32(offset)\n return elem_ptr.toint(loc=loc, ip=ip)\n\n\n@dsl_user_op\ndef ld_shared_v2_u32(smem_addr: Int32, *, loc=None, ip=None) -> Tuple[Uint32, Uint32]:\n \"\"\"Load 64 bits (2 x uint32) from shared memory via ld.shared.v2.u32.\n\n Args:\n smem_addr: 32-bit shared memory address (from get_smem_ptr_as_int32).\n Caller is responsible for ensuring 8-byte alignment.\n\n Returns:\n 2 Uint32 values (8 bytes total).\n \"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.i32(), T.i32()]),\n [Int32(smem_addr).ir_value(loc=loc, ip=ip)],\n \"ld.shared.v2.u32 {$0, $1}, [$2];\",\n \"=r,=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n v0 = llvm.extractvalue(T.i32(), result, [0], loc=loc, ip=ip)\n v1 = llvm.extractvalue(T.i32(), result, [1], loc=loc, ip=ip)\n return Uint32(v0), Uint32(v1)\n\n\n@dsl_user_op\ndef ld_shared_v4_u32(\n smem_addr: Int32, *, loc=None, ip=None\n) -> Tuple[Uint32, Uint32, Uint32, Uint32]:\n \"\"\"Load 128 bits (4 x uint32) from shared memory via ld.shared.v4.u32.\n\n Args:\n smem_addr: 32-bit shared memory address (from get_smem_ptr_as_int32).\n\n Returns:\n 4 Uint32 values (16 bytes total, e.g. 8 packed fp16 elements).\n \"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.i32(), T.i32(), T.i32(), T.i32()]),\n [Int32(smem_addr).ir_value(loc=loc, ip=ip)],\n \"ld.shared.v4.u32 {$0, $1, $2, $3}, [$4];\",\n \"=r,=r,=r,=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n v0 = llvm.extractvalue(T.i32(), result, [0], loc=loc, ip=ip)\n v1 = llvm.extractvalue(T.i32(), result, [1], loc=loc, ip=ip)\n v2 = llvm.extractvalue(T.i32(), result, [2], loc=loc, ip=ip)\n v3 = llvm.extractvalue(T.i32(), result, [3], loc=loc, ip=ip)\n return Uint32(v0), Uint32(v1), Uint32(v2), Uint32(v3)\n\n\n@dsl_user_op\ndef pack_16bit_to_u32(lo, hi, *, loc=None, ip=None) -> Uint32:\n \"\"\"Pack two 16-bit scalar values (fp16 or bf16) into one Uint32 (half2/bfloat2).\n\n Uses PTX mov.b32 to bitwise-pack two 16-bit register values into a single\n 32-bit register, suitable for half2/bfloat2 SIMD operations.\n \"\"\"\n lo_ir = lo.ir_value(loc=loc, ip=ip)\n hi_ir = hi.ir_value(loc=loc, ip=ip)\n lo_i16 = llvm.bitcast(T.i16(), lo_ir, loc=loc, ip=ip)\n hi_i16 = llvm.bitcast(T.i16(), hi_ir, loc=loc, ip=ip)\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [lo_i16, hi_i16],\n \"mov.b32 $0, {$1, $2};\",\n \"=r,h,h\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n# =============================================================================\n# PTX Intrinsics - Math Operations\n# =============================================================================\n\n\n@dsl_user_op\ndef rcp_approx_ftz(a: Float32, *, loc=None, ip=None) -> Float32:\n \"\"\"Fast reciprocal using PTX rcp.approx.ftz.f32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Float32(a).ir_value(loc=loc, ip=ip)],\n \"rcp.approx.ftz.f32 $0, $1;\",\n \"=f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef rcp_rn(a: Float32, *, loc=None, ip=None) -> Float32:\n \"\"\"Round-to-nearest reciprocal using PTX div.rn.f32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Float32(a).ir_value(loc=loc, ip=ip)],\n \"div.rn.f32 $0, 0f3F800000, $1;\",\n \"=f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef fadd_rn(a: Float32, b: Float32, loc=None, ip=None) -> Float32:\n \"\"\"Round-to-nearest float32 addition.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Float32(a).ir_value(loc=loc, ip=ip), Float32(b).ir_value(loc=loc, ip=ip)],\n \"add.rn.f32 $0, $1, $2;\",\n \"=f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef fsub_rn(a: Float32, b: Float32, loc=None, ip=None) -> Float32:\n \"\"\"Round-to-nearest float32 subtraction.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Float32(a).ir_value(loc=loc, ip=ip), Float32(b).ir_value(loc=loc, ip=ip)],\n \"sub.rn.f32 $0, $1, $2;\",\n \"=f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef fmul_rn(a: Float32, b: Float32, loc=None, ip=None) -> Float32:\n \"\"\"Round-to-nearest float32 multiplication.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Float32(a).ir_value(loc=loc, ip=ip), Float32(b).ir_value(loc=loc, ip=ip)],\n \"mul.rn.f32 $0, $1, $2;\",\n \"=f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef fdiv_rn(a: Float32, b: Float32, loc=None, ip=None) -> Float32:\n \"\"\"Round-to-nearest float32 division.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Float32(a).ir_value(loc=loc, ip=ip), Float32(b).ir_value(loc=loc, ip=ip)],\n \"div.rn.f32 $0, $1, $2;\",\n \"=f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef fmin_f32(a: Float32, b: Float32, *, loc=None, ip=None) -> Float32:\n \"\"\"Compute min of two float32 values using PTX min.f32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Float32(a).ir_value(loc=loc, ip=ip), Float32(b).ir_value(loc=loc, ip=ip)],\n \"min.f32 $0, $1, $2;\",\n \"=f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef fmax_f32(a: Float32, b: Float32, *, loc=None, ip=None) -> Float32:\n \"\"\"Compute max of two float32 values using PTX max.f32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Float32(a).ir_value(loc=loc, ip=ip), Float32(b).ir_value(loc=loc, ip=ip)],\n \"max.f32 $0, $1, $2;\",\n \"=f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef fabs_f32(a: Float32, *, loc=None, ip=None) -> Float32:\n \"\"\"Compute absolute value of float32 using PTX abs.f32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Float32(a).ir_value(loc=loc, ip=ip)],\n \"abs.f32 $0, $1;\",\n \"=f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n# =============================================================================\n# Half2 SIMD Intrinsics\n# =============================================================================\n\n\n@dsl_user_op\ndef half2_mul(a: Uint32, b: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Multiply two Half2 values element-wise: (a.x*b.x, a.y*b.y).\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(a).ir_value(loc=loc, ip=ip), Uint32(b).ir_value(loc=loc, ip=ip)],\n \"mul.f16x2 $0, $1, $2;\",\n \"=r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef hadd2(a: Uint32, b: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Add two Half2 values element-wise: (a.x+b.x, a.y+b.y).\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(a).ir_value(loc=loc, ip=ip), Uint32(b).ir_value(loc=loc, ip=ip)],\n \"add.f16x2 $0, $1, $2;\",\n \"=r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef habs2(x: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Half2 absolute value - clears sign bits of both fp16 values.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(x).ir_value(loc=loc, ip=ip)],\n \"and.b32 $0, $1, 0x7FFF7FFF;\",\n \"=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef hmax2(a: Uint32, b: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Half2 max - element-wise max of 2 fp16 pairs.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(a).ir_value(loc=loc, ip=ip), Uint32(b).ir_value(loc=loc, ip=ip)],\n \"max.f16x2 $0, $1, $2;\",\n \"=r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef hmax_to_f32(x: Uint32, *, loc=None, ip=None) -> Float32:\n \"\"\"Extract max of 2 fp16 values in half2 as float32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Uint32(x).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 h0, h1;\n .reg .f32 f0, f1;\n mov.b32 {h0, h1}, $1;\n cvt.f32.f16 f0, h0;\n cvt.f32.f16 f1, h1;\n max.f32 $0, f0, f1;\n }\n \"\"\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef half2_to_float2_scaled(\n h2: Uint32, scale: Float32, *, loc=None, ip=None\n) -> Tuple[Float32, Float32]:\n \"\"\"Convert half2 to float2 AND multiply by scale.\"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.f32(), T.f32()]),\n [Uint32(h2).ir_value(loc=loc, ip=ip), Float32(scale).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 h0, h1;\n .reg .f32 f0, f1;\n mov.b32 {h0, h1}, $2;\n cvt.f32.f16 f0, h0;\n cvt.f32.f16 f1, h1;\n mul.f32 $0, f0, $3;\n mul.f32 $1, f1, $3;\n }\n \"\"\",\n \"=f,=f,r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n f0 = llvm.extractvalue(T.f32(), result, [0], loc=loc, ip=ip)\n f1 = llvm.extractvalue(T.f32(), result, [1], loc=loc, ip=ip)\n\n return Float32(f0), Float32(f1)\n\n\n# =============================================================================\n# BFloat2 SIMD Intrinsics\n# =============================================================================\n\n\n@dsl_user_op\ndef bfloat2_mul(a: Uint32, b: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Multiply two BFloat2 values element-wise: (a.x*b.x, a.y*b.y).\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(a).ir_value(loc=loc, ip=ip), Uint32(b).ir_value(loc=loc, ip=ip)],\n \"mul.bf16x2 $0, $1, $2;\",\n \"=r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef bfloat2_add(a: Uint32, b: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Add two BFloat2 values element-wise: (a.x+b.x, a.y+b.y).\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(a).ir_value(loc=loc, ip=ip), Uint32(b).ir_value(loc=loc, ip=ip)],\n \"add.bf16x2 $0, $1, $2;\",\n \"=r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef bfloat2_habs2(x: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"BFloat16x2 absolute value - clears sign bits of both bf16 values.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(x).ir_value(loc=loc, ip=ip)],\n \"and.b32 $0, $1, 0x7FFF7FFF;\",\n \"=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef bfloat2_hmax2(a: Uint32, b: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"BFloat16x2 max - element-wise max of 2 bf16 pairs.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(a).ir_value(loc=loc, ip=ip), Uint32(b).ir_value(loc=loc, ip=ip)],\n \"max.bf16x2 $0, $1, $2;\",\n \"=r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef bfloat2_hmax_to_f32(x: Uint32, *, loc=None, ip=None) -> Float32:\n \"\"\"Extract max of 2 bf16 values in bfloat2 as float32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Uint32(x).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b32 lo, hi;\n .reg .f32 f0, f1;\n and.b32 lo, $1, 0xFFFF;\n shr.b32 hi, $1, 16;\n shl.b32 lo, lo, 16;\n shl.b32 hi, hi, 16;\n mov.b32 f0, lo;\n mov.b32 f1, hi;\n max.f32 $0, f0, f1;\n }\n \"\"\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef bfloat2_to_float2_scaled(\n bf2: Uint32, scale: Float32, *, loc=None, ip=None\n) -> Tuple[Float32, Float32]:\n \"\"\"Convert bfloat16x2 to float2 AND multiply by scale.\"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.f32(), T.f32()]),\n [Uint32(bf2).ir_value(loc=loc, ip=ip), Float32(scale).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b32 lo, hi;\n .reg .f32 f0, f1;\n and.b32 lo, $2, 0xFFFF;\n shr.b32 hi, $2, 16;\n shl.b32 lo, lo, 16;\n shl.b32 hi, hi, 16;\n mov.b32 f0, lo;\n mov.b32 f1, hi;\n mul.f32 $0, f0, $3;\n mul.f32 $1, f1, $3;\n }\n \"\"\",\n \"=f,=f,r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n f0 = llvm.extractvalue(T.f32(), result, [0], loc=loc, ip=ip)\n f1 = llvm.extractvalue(T.f32(), result, [1], loc=loc, ip=ip)\n\n return Float32(f0), Float32(f1)\n\n\n# =============================================================================\n# FP8 E4M3 Intrinsics\n# =============================================================================\n\n\n@dsl_user_op\ndef cvt_f32_to_e4m3(a: Float32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Convert float32 to E4M3 using native cvt.rn.satfinite.e4m3x2.f32.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Float32(a).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 fp8_pair;\n .reg .f32 zero;\n mov.f32 zero, 0f00000000;\n cvt.rn.satfinite.e4m3x2.f32 fp8_pair, zero, $1;\n cvt.u32.u16 $0, fp8_pair;\n }\n \"\"\",\n \"=r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef cvt_e4m3x4_to_f32x4(\n packed: Uint32, *, loc=None, ip=None\n) -> tuple[Float32, Float32, Float32, Float32]:\n \"\"\"Convert 4 packed E4M3 bytes (in a uint32) to 4 float32 values.\n\n Uses e4m3x2 → f16x2 → f32 conversion path (SM89+/PTX ISA 7.8+).\n Input: uint32 containing bytes [b0, b1, b2, b3] (low to high).\n Output: (f0, f1, f2, f3) as Float32.\n \"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.f32(), T.f32(), T.f32(), T.f32()]),\n [Uint32(packed).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 pair_lo, pair_hi;\n .reg .b32 h2_lo, h2_hi;\n .reg .b16 h0, h1, h2, h3;\n mov.b32 {pair_lo, pair_hi}, $4;\n cvt.rn.f16x2.e4m3x2 h2_lo, pair_lo;\n cvt.rn.f16x2.e4m3x2 h2_hi, pair_hi;\n mov.b32 {h0, h1}, h2_lo;\n mov.b32 {h2, h3}, h2_hi;\n cvt.f32.f16 $0, h0;\n cvt.f32.f16 $1, h1;\n cvt.f32.f16 $2, h2;\n cvt.f32.f16 $3, h3;\n }\n \"\"\",\n \"=f,=f,=f,=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n f0 = llvm.extractvalue(T.f32(), result, [0], loc=loc, ip=ip)\n f1 = llvm.extractvalue(T.f32(), result, [1], loc=loc, ip=ip)\n f2 = llvm.extractvalue(T.f32(), result, [2], loc=loc, ip=ip)\n f3 = llvm.extractvalue(T.f32(), result, [3], loc=loc, ip=ip)\n\n return Float32(f0), Float32(f1), Float32(f2), Float32(f3)\n\n\n@dsl_user_op\ndef cvt_f32x2_to_half2(a: Float32, b: Float32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Pack two float32 values into a half2 (uint32 containing two fp16 values).\n\n Uses cvt.rn.f16.f32 for each value, then packs into a single uint32.\n Matches __float22half2_rn() behavior in CUDA.\n \"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [\n Float32(a).ir_value(loc=loc, ip=ip),\n Float32(b).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b16 h0, h1;\n cvt.rn.f16.f32 h0, $1;\n cvt.rn.f16.f32 h1, $2;\n mov.b32 $0, {h0, h1};\n }\n \"\"\",\n \"=r,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef cvt_f32x2_to_bfloat2(a: Float32, b: Float32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Pack two float32 values into the low and high bfloat16 lanes, respectively.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [\n Float32(a).ir_value(loc=loc, ip=ip),\n Float32(b).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b16 h0, h1;\n cvt.rn.bf16.f32 h0, $1;\n cvt.rn.bf16.f32 h1, $2;\n mov.b32 $0, {h0, h1};\n }\n \"\"\",\n \"=r,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef fp8_e4m3_to_f32_and_rcp(fp8_val: Uint32, *, loc=None, ip=None) -> Float32:\n \"\"\"Convert FP8 E4M3 to float32 AND compute reciprocal (0 stays 0).\n\n Uses the hardware conversion instruction, which is exact for every\n finite e4m3 value, including subnormals, and matches how the tensor\n core decodes the same byte.\n \"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Uint32(fp8_val).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .pred p_zero;\n .reg .b16 fp8_pair;\n .reg .b32 h2_32;\n .reg .b16 h_lo, h_hi;\n .reg .f32 fp8_float, result;\n\n cvt.u16.u32 fp8_pair, $1;\n cvt.rn.f16x2.e4m3x2 h2_32, fp8_pair;\n mov.b32 {h_lo, h_hi}, h2_32;\n cvt.f32.f16 fp8_float, h_lo;\n rcp.approx.ftz.f32 result, fp8_float;\n setp.eq.f32 p_zero, fp8_float, 0f00000000;\n selp.f32 $0, 0f00000000, result, p_zero;\n }\n \"\"\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef nvfp4_compute_output_scale(\n fp8_val: Uint32, global_scale: Float32, *, loc=None, ip=None\n) -> Float32:\n \"\"\"Compute NVFP4 output_scale matching the CUDA kernel exactly.\n\n Converts E4M3 scale factor to float via hardware f16x2 path, then computes\n rcp(float_scale * rcp(global_scale)). Returns 0 when scale is zero.\n\n This matches quantization_utils.cuh:\n SFValue = static_cast<float>(tmp);\n outputScale = rcp_approx(SFValue * rcp_approx(SFScaleVal));\n \"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [\n Uint32(fp8_val).ir_value(loc=loc, ip=ip),\n Float32(global_scale).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .pred p_zero;\n .reg .b16 fp8_pair;\n .reg .b32 h2_32;\n .reg .b16 h_lo, h_hi;\n .reg .f32 scale_f32, rcp_gs, product, result;\n\n cvt.u16.u32 fp8_pair, $1;\n cvt.rn.f16x2.e4m3x2 h2_32, fp8_pair;\n mov.b32 {h_lo, h_hi}, h2_32;\n cvt.f32.f16 scale_f32, h_lo;\n\n rcp.approx.ftz.f32 rcp_gs, $2;\n mul.f32 product, scale_f32, rcp_gs;\n rcp.approx.ftz.f32 result, product;\n\n setp.eq.f32 p_zero, scale_f32, 0f00000000;\n selp.f32 $0, 0f00000000, result, p_zero;\n }\n \"\"\",\n \"=f,r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef nvfp4_compute_output_scale_rn(\n fp8_val: Uint32, global_scale: Float32, block_amax: Float32, *, loc=None, ip=None\n) -> Float32:\n \"\"\"Compute TE-exact NVFP4 output scale when FP4 quant fast math is disabled.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [\n Uint32(fp8_val).ir_value(loc=loc, ip=ip),\n Float32(global_scale).ir_value(loc=loc, ip=ip),\n Float32(block_amax).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .pred p_zero;\n .reg .b16 fp8_pair;\n .reg .b32 h2_32;\n .reg .b16 h_lo, h_hi;\n .reg .f32 scale_f32, rcp_gs, product, result, max_f32;\n\n cvt.u16.u32 fp8_pair, $1;\n cvt.rn.f16x2.e4m3x2 h2_32, fp8_pair;\n mov.b32 {h_lo, h_hi}, h2_32;\n cvt.f32.f16 scale_f32, h_lo;\n\n div.rn.f32 rcp_gs, 0f3F800000, $2;\n mul.rn.f32 product, scale_f32, rcp_gs;\n div.rn.f32 result, 0f3F800000, product;\n mov.b32 max_f32, 0x7F7FFFFF;\n min.f32 result, result, max_f32;\n\n setp.eq.f32 p_zero, $3, 0f00000000;\n selp.f32 $0, 0f00000000, result, p_zero;\n }\n \"\"\",\n \"=f,r,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n# =============================================================================\n# UE8M0 Intrinsics (for MXFP4)\n# =============================================================================\n\n\n@dsl_user_op\ndef cvt_f32_to_ue8m0(max_val: Float32, *, loc=None, ip=None) -> Uint32:\n \"\"\"\n Convert float32 max value to UE8M0 scale factor.\n\n UE8M0 is unsigned 8-bit exponent-only format:\n - value = 2^(ue8m0 - 127)\n - ue8m0 = ceil(log2(max_val)) + 127\n\n Uses lg2.approx.f32 for fast log2 approximation.\n Uses cvt.rpi (round towards positive infinity, i.e., ceiling).\n Returns value clamped to [0, 255].\n \"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Float32(max_val).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .pred p_zero, p_neg, p_ovf;\n .reg .f32 log2_val;\n .reg .s32 exp_int, result;\n\n // Check for zero/negative\n setp.le.f32 p_zero, $1, 0f00000000;\n\n // Compute ceil(log2(max_val)) using cvt.rpi (round towards +inf)\n lg2.approx.f32 log2_val, $1;\n cvt.rpi.s32.f32 exp_int, log2_val;\n\n // Add bias and clamp to [0, 255]\n add.s32 result, exp_int, 127;\n setp.lt.s32 p_neg, result, 0;\n setp.gt.s32 p_ovf, result, 255;\n selp.s32 result, 0, result, p_neg;\n selp.s32 result, 255, result, p_ovf;\n selp.s32 $0, 0, result, p_zero;\n }\n \"\"\",\n \"=r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef ue8m0_to_output_scale(ue8m0_val: Uint32, *, loc=None, ip=None) -> Float32:\n \"\"\"\n Convert UE8M0 to output_scale for MXFP4 quantization.\n\n UE8M0 value = 2^(ue8m0 - 127)\n Returns 1 / 2^(ue8m0 - 127) = 2^(127 - ue8m0)\n \"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Uint32(ue8m0_val).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .pred p_zero;\n .reg .s32 neg_exp;\n .reg .f32 neg_exp_f, result;\n\n // Check for zero\n setp.eq.u32 p_zero, $1, 0;\n\n // Compute 2^(127 - ue8m0) = 1 / 2^(ue8m0 - 127)\n sub.s32 neg_exp, 127, $1;\n cvt.rn.f32.s32 neg_exp_f, neg_exp;\n ex2.approx.f32 result, neg_exp_f;\n selp.f32 $0, 0f00000000, result, p_zero;\n }\n \"\"\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n# =============================================================================\n# E2M1 Conversion\n# =============================================================================\n\n\n@dsl_user_op\ndef cvt_e2m1x8_f32(\n v0: Float32,\n v1: Float32,\n v2: Float32,\n v3: Float32,\n v4: Float32,\n v5: Float32,\n v6: Float32,\n v7: Float32,\n *,\n loc=None,\n ip=None,\n) -> Uint32:\n \"\"\"Convert eight float32 values to eight E2M1 (4-bit) values packed into uint32.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [\n Float32(v0).ir_value(loc=loc, ip=ip),\n Float32(v1).ir_value(loc=loc, ip=ip),\n Float32(v2).ir_value(loc=loc, ip=ip),\n Float32(v3).ir_value(loc=loc, ip=ip),\n Float32(v4).ir_value(loc=loc, ip=ip),\n Float32(v5).ir_value(loc=loc, ip=ip),\n Float32(v6).ir_value(loc=loc, ip=ip),\n Float32(v7).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b8 byte0, byte1, byte2, byte3;\n cvt.rn.satfinite.e2m1x2.f32 byte0, $2, $1;\n cvt.rn.satfinite.e2m1x2.f32 byte1, $4, $3;\n cvt.rn.satfinite.e2m1x2.f32 byte2, $6, $5;\n cvt.rn.satfinite.e2m1x2.f32 byte3, $8, $7;\n mov.b32 $0, {byte0, byte1, byte2, byte3};\n }\n \"\"\",\n \"=r,f,f,f,f,f,f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n# =============================================================================\n# Warp, Block, and Cluster Reduction Utilities\n# =============================================================================\n\n\n@cute.jit\ndef warp_reduce(val, op, width: cutlass.Constexpr[int] = 32):\n \"\"\"Reduce across threads in a warp using butterfly shuffle.\"\"\"\n if cutlass.const_expr(isinstance(val, cute.TensorSSA)):\n res = cute.make_rmem_tensor(val.shape, val.dtype)\n res.store(val)\n for i in cutlass.range_constexpr(cute.size(val.shape)):\n res[i] = warp_reduce(res[i], op, width)\n return res.load()\n else:\n for i in cutlass.range_constexpr(int(math.log2(width))):\n val = op(val, cute.arch.shuffle_sync_bfly(val, offset=1 << i))\n return val\n\n\n@cute.jit\ndef block_reduce(\n val: Float32,\n op: Callable,\n reduction_buffer: cute.Tensor,\n init_val: Float32,\n) -> Float32:\n \"\"\"Block reduction across multiple warps using shared memory.\"\"\"\n lane_idx = cute.arch.lane_idx()\n warp_idx = cute.arch.warp_idx()\n warps_per_row = cute.size(reduction_buffer.shape[1])\n row_idx = warp_idx // warps_per_row\n col_idx = warp_idx % warps_per_row\n\n if lane_idx == 0:\n reduction_buffer[row_idx, col_idx] = val\n cute.arch.barrier()\n\n block_reduce_val = init_val\n if lane_idx < warps_per_row:\n block_reduce_val = reduction_buffer[row_idx, lane_idx]\n return warp_reduce(block_reduce_val, op)\n\n\n@cute.jit\ndef cluster_reduce(\n val: Float32,\n op: Callable,\n reduction_buffer: cute.Tensor,\n mbar_ptr: cute.Pointer,\n cluster_n: cutlass.Constexpr[int],\n init_val: Float32,\n) -> Float32:\n \"\"\"Cluster reduction across multiple CTAs using mbarrier.\"\"\"\n cta_rank_in_cluster = cute.arch.block_idx_in_cluster()\n lane_idx = cute.arch.lane_idx()\n warp_idx = cute.arch.warp_idx()\n\n rows_per_block = reduction_buffer.shape[0]\n warps_per_row = reduction_buffer.shape[1][0]\n\n row_idx = warp_idx // warps_per_row\n col_idx = warp_idx % warps_per_row\n\n # Warp 0 sets up mbarrier transaction count\n if warp_idx == 0:\n with cute.arch.elect_one():\n num_warps = rows_per_block * warps_per_row\n expected_bytes = num_warps * cluster_n * 4\n cute.arch.mbarrier_arrive_and_expect_tx(mbar_ptr, expected_bytes)\n\n # Each lane < cluster_n writes to a different CTA's shared memory\n if lane_idx < cluster_n:\n store_shared_remote(\n val,\n elem_pointer(reduction_buffer, (row_idx, (col_idx, cta_rank_in_cluster))),\n mbar_ptr,\n peer_cta_rank_in_cluster=lane_idx,\n )\n\n # Wait for all cluster writes\n cute.arch.mbarrier_wait(mbar_ptr, phase=0)\n\n # Reduce across all values\n num_total = warps_per_row * cluster_n\n num_iter = cute.ceil_div(num_total, 32)\n\n block_reduce_val = init_val\n for i in cutlass.range_constexpr(num_iter):\n idx = lane_idx + i * 32\n if idx < num_total:\n block_reduce_val = op(block_reduce_val, reduction_buffer[row_idx, idx])\n\n return warp_reduce(block_reduce_val, op)\n\n\n@cute.jit\ndef row_reduce(\n x: cute.TensorSSA,\n op: cute.ReductionOp,\n threads_per_row: cutlass.Constexpr[int],\n reduction_buffer: cute.Tensor,\n mbar_ptr,\n cluster_n: cutlass.Constexpr[int],\n init_val: Float32,\n):\n \"\"\"Row reduction with optional cluster support.\"\"\"\n local_val = x.reduce(op, init_val=init_val, reduction_profile=0)\n\n warp_op = {\n cute.ReductionOp.ADD: operator.add,\n cute.ReductionOp.MAX: cute.arch.fmax,\n }[op]\n warp_width = min(threads_per_row, 32)\n warp_val = warp_reduce(local_val, warp_op, width=warp_width)\n\n warps_per_row = max(threads_per_row // 32, 1)\n\n if cutlass.const_expr(warps_per_row > 1 or cluster_n > 1):\n if cutlass.const_expr(cluster_n == 1):\n return block_reduce(warp_val, warp_op, reduction_buffer, init_val)\n else:\n return cluster_reduce(\n warp_val, warp_op, reduction_buffer, mbar_ptr, cluster_n, init_val\n )\n else:\n return warp_val\n\n\n# =============================================================================\n# Predicate Utility\n# =============================================================================\n\n\n@cute.jit\ndef predicate_k(tXcX: cute.Tensor, limit: int) -> cute.Tensor:\n \"\"\"Create predicate tensor for bounds checking.\"\"\"\n tXpX = cute.make_rmem_tensor(\n cute.make_layout(\n (\n cute.size(tXcX, mode=[0, 1]),\n cute.size(tXcX, mode=[1]),\n cute.size(tXcX, mode=[2]),\n ),\n stride=(cute.size(tXcX, mode=[2]), 0, 1),\n ),\n cutlass.Boolean,\n )\n for rest_v in cutlass.range_constexpr(tXpX.shape[0]):\n for rest_k in cutlass.range_constexpr(tXpX.shape[2]):\n tXpX[rest_v, 0, rest_k] = cute.elem_less(\n tXcX[(0, rest_v), 0, rest_k][1], limit\n )\n return tXpX\n\n\n# =============================================================================\n# Helper Functions for SF Block Processing (block_size=16)\n# =============================================================================\n\n\n@cute.jit\ndef load_8_half2(\n mX: cute.Tensor, mW: cute.Tensor, row_offset: Int32, col_offset: Int32, H: int\n):\n \"\"\"Load 16 elements (8 half2 pairs) of X and W from global memory.\n\n Returns:\n x_h2: rmem_tensor of shape (8,) containing X as half2\n w_h2: rmem_tensor of shape (8,) containing W as half2\n \"\"\"\n x_h2 = cute.make_rmem_tensor((8,), Uint32)\n w_h2 = cute.make_rmem_tensor((8,), Uint32)\n\n # Load X (2 x 128-bit loads = 16 elements)\n x_ptr0 = get_ptr_as_int64(mX, row_offset * H + col_offset)\n x_ptr1 = get_ptr_as_int64(mX, row_offset * H + col_offset + Int32(8))\n x_h2[0], x_h2[1], x_h2[2], x_h2[3] = ld_global_v4_u32(x_ptr0)\n x_h2[4], x_h2[5], x_h2[6], x_h2[7] = ld_global_v4_u32(x_ptr1)\n\n # Load W (2 x 128-bit loads = 16 elements)\n w_ptr0 = get_ptr_as_int64(mW, col_offset)\n w_ptr1 = get_ptr_as_int64(mW, col_offset + Int32(8))\n w_h2[0], w_h2[1], w_h2[2], w_h2[3] = ld_global_v4_u32(w_ptr0)\n w_h2[4], w_h2[5], w_h2[6], w_h2[7] = ld_global_v4_u32(w_ptr1)\n\n return x_h2, w_h2\n\n\n@cute.jit\ndef half2_mul_8(x_h2: cute.Tensor, w_h2: cute.Tensor) -> cute.Tensor:\n \"\"\"Multiply 8 half2 pairs element-wise.\"\"\"\n xw_h2 = cute.make_rmem_tensor((8,), Uint32)\n for i in cutlass.range_constexpr(8):\n xw_h2[i] = half2_mul(x_h2[i], w_h2[i])\n return xw_h2\n\n\n@cute.jit\ndef bfloat2_mul_8(x_h2: cute.Tensor, w_h2: cute.Tensor) -> cute.Tensor:\n \"\"\"Multiply 8 bfloat2 pairs element-wise.\"\"\"\n xw_h2 = cute.make_rmem_tensor((8,), Uint32)\n for i in cutlass.range_constexpr(8):\n xw_h2[i] = bfloat2_mul(x_h2[i], w_h2[i])\n return xw_h2\n\n\n@cute.jit\ndef half2_max_abs_8(xw_h2: cute.Tensor) -> Uint32:\n \"\"\"Compute max absolute value across 8 half2 values using tree reduction.\"\"\"\n # Compute abs for all 8 values\n abs_h2 = cute.make_rmem_tensor((8,), Uint32)\n for i in cutlass.range_constexpr(8):\n abs_h2[i] = habs2(xw_h2[i])\n\n # Tree reduction: 8 -> 4 -> 2 -> 1\n max_01 = hmax2(abs_h2[0], abs_h2[1])\n max_23 = hmax2(abs_h2[2], abs_h2[3])\n max_45 = hmax2(abs_h2[4], abs_h2[5])\n max_67 = hmax2(abs_h2[6], abs_h2[7])\n max_0123 = hmax2(max_01, max_23)\n max_4567 = hmax2(max_45, max_67)\n return hmax2(max_0123, max_4567)\n\n\n@cute.jit\ndef bfloat2_max_abs_8(xw_h2: cute.Tensor) -> Uint32:\n \"\"\"Compute max absolute value across 8 bfloat2 values using tree reduction.\"\"\"\n # Compute abs for all 8 values\n abs_h2 = cute.make_rmem_tensor((8,), Uint32)\n for i in cutlass.range_constexpr(8):\n abs_h2[i] = bfloat2_habs2(xw_h2[i])\n\n # Tree reduction: 8 -> 4 -> 2 -> 1\n max_01 = bfloat2_hmax2(abs_h2[0], abs_h2[1])\n max_23 = bfloat2_hmax2(abs_h2[2], abs_h2[3])\n max_45 = bfloat2_hmax2(abs_h2[4], abs_h2[5])\n max_67 = bfloat2_hmax2(abs_h2[6], abs_h2[7])\n max_0123 = bfloat2_hmax2(max_01, max_23)\n max_4567 = bfloat2_hmax2(max_45, max_67)\n return bfloat2_hmax2(max_0123, max_4567)\n\n\n@cute.jit\ndef half2_to_float16(xw_h2: cute.Tensor, scale: Float32) -> cute.Tensor:\n \"\"\"Convert 8 half2 to 16 float32 with scaling.\"\"\"\n y_f32 = cute.make_rmem_tensor((16,), Float32)\n for i in cutlass.range_constexpr(8):\n y_f32[i * 2], y_f32[i * 2 + 1] = half2_to_float2_scaled(xw_h2[i], scale)\n return y_f32\n\n\n@cute.jit\ndef bfloat2_to_float16(xw_h2: cute.Tensor, scale: Float32) -> cute.Tensor:\n \"\"\"Convert 8 bfloat2 to 16 float32 with scaling.\"\"\"\n y_f32 = cute.make_rmem_tensor((16,), Float32)\n for i in cutlass.range_constexpr(8):\n y_f32[i * 2], y_f32[i * 2 + 1] = bfloat2_to_float2_scaled(xw_h2[i], scale)\n return y_f32\n\n\n@cute.jit\ndef quantize_and_pack_16(y_f32: cute.Tensor, inv_scale: Float32) -> Uint64:\n \"\"\"Quantize 16 float32 values to FP4 and pack into uint64.\"\"\"\n # Scale values\n q = cute.make_rmem_tensor((16,), Float32)\n for i in cutlass.range_constexpr(16):\n q[i] = y_f32[i] * inv_scale\n\n # Convert to E2M1 and pack\n packed_lo = cvt_e2m1x8_f32(q[0], q[1], q[2], q[3], q[4], q[5], q[6], q[7])\n packed_hi = cvt_e2m1x8_f32(q[8], q[9], q[10], q[11], q[12], q[13], q[14], q[15])\n return (Uint64(packed_hi) << Uint64(32)) | Uint64(packed_lo)\n\n\n# =============================================================================\n# Helper Functions for Float32 SF Block Processing\n# =============================================================================\n\n\n@cute.jit\ndef load_f32_16_from_smem(\n sH: cute.Tensor, row_idx: Int32, col_offset: Int32\n) -> cute.Tensor:\n \"\"\"Load 16 Float32 values from shared memory.\"\"\"\n h_f32 = cute.make_rmem_tensor((16,), Float32)\n for i in cutlass.range_constexpr(16):\n h_f32[i] = Float32(sH[row_idx, col_offset + i])\n return h_f32\n\n\n@cute.jit\ndef compute_y_and_max_abs_f32(\n h_f32: cute.Tensor, w_f32: cute.Tensor, rstd: Float32\n) -> Tuple[cute.Tensor, Float32]:\n \"\"\"Compute y = h * rstd * w and max_abs for 16 Float32 values.\"\"\"\n y_f32 = cute.make_rmem_tensor((16,), Float32)\n\n # Compute y and track max_abs\n y_f32[0] = h_f32[0] * rstd * w_f32[0]\n max_abs = fabs_f32(y_f32[0])\n\n for i in cutlass.range_constexpr(1, 16):\n y_f32[i] = h_f32[i] * rstd * w_f32[i]\n max_abs = fmax_f32(max_abs, fabs_f32(y_f32[i]))\n\n return y_f32, max_abs\n\n\n# =============================================================================\n# PTX intrinsics used by SM120 MoE kernels\n# =============================================================================\n\n\n@dsl_user_op\ndef st_global_f32(base_ptr: Int64, value: Float32, *, loc=None, ip=None):\n \"\"\"Store 32-bit float to global memory.\"\"\"\n llvm.inline_asm(\n None,\n [\n Int64(base_ptr).ir_value(loc=loc, ip=ip),\n Float32(value).ir_value(loc=loc, ip=ip),\n ],\n \"st.global.f32 [$0], $1;\",\n \"l,f\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n\n\n@dsl_user_op\ndef st_global_i32(addr: Int64, val: Int32, *, loc=None, ip=None):\n \"\"\"Store int32 to global memory.\"\"\"\n llvm.inline_asm(\n None,\n [\n Int64(addr).ir_value(loc=loc, ip=ip),\n Int32(val).ir_value(loc=loc, ip=ip),\n ],\n \"st.global.s32 [$0], $1;\",\n \"l,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n\n\n@dsl_user_op\ndef st_global_v4_u32(\n base_ptr: Int64,\n v0: Uint32,\n v1: Uint32,\n v2: Uint32,\n v3: Uint32,\n *,\n loc=None,\n ip=None,\n):\n \"\"\"Store 128 bits to global memory as four uint32 words.\"\"\"\n llvm.inline_asm(\n None,\n [\n Int64(base_ptr).ir_value(loc=loc, ip=ip),\n Uint32(v0).ir_value(loc=loc, ip=ip),\n Uint32(v1).ir_value(loc=loc, ip=ip),\n Uint32(v2).ir_value(loc=loc, ip=ip),\n Uint32(v3).ir_value(loc=loc, ip=ip),\n ],\n \"st.global.v4.u32 [$0], {$1, $2, $3, $4};\",\n \"l,r,r,r,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n\n# =============================================================================\n# PTX Intrinsics — Shared Memory Operations\n# =============================================================================\n\n\n@dsl_user_op\ndef shared_ptr_to_u32(ptr: cute.Pointer, *, loc=None, ip=None) -> Int32:\n \"\"\"Convert an address-space-3 shared-memory pointer to a u32 address.\"\"\"\n return Int32(llvm.ptrtoint(T.i32(), ptr.llvm_ptr, loc=loc, ip=ip))\n\n\n@dsl_user_op\ndef ld_shared_i32_relaxed(addr: Int32, *, loc=None, ip=None) -> Int32:\n \"\"\"Load int32 from shared memory when CSE/reordering is acceptable.\"\"\"\n return Int32(\n llvm.inline_asm(\n T.i32(),\n [Int32(addr).ir_value(loc=loc, ip=ip)],\n \"ld.shared.s32 $0, [$1];\",\n \"=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef st_shared_i32(addr: Int32, val: Int32, *, loc=None, ip=None):\n \"\"\"Store int32 to shared memory at a 32-bit byte address.\"\"\"\n llvm.inline_asm(\n None,\n [\n Int32(addr).ir_value(loc=loc, ip=ip),\n Int32(val).ir_value(loc=loc, ip=ip),\n ],\n \"st.shared.s32 [$0], $1;\",\n \"r,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n\n@dsl_user_op\ndef ld_shared_f32(addr: Int32, *, loc=None, ip=None) -> Float32:\n \"\"\"Load float32 from shared memory at a 32-bit byte address.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Int32(addr).ir_value(loc=loc, ip=ip)],\n \"ld.shared.f32 $0, [$1];\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef st_shared_f32(addr: Int32, val: Float32, *, loc=None, ip=None):\n \"\"\"Store float32 to shared memory at a 32-bit byte address.\"\"\"\n llvm.inline_asm(\n None,\n [\n Int32(addr).ir_value(loc=loc, ip=ip),\n Float32(val).ir_value(loc=loc, ip=ip),\n ],\n \"st.shared.f32 [$0], $1;\",\n \"r,f\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n\n@dsl_user_op\ndef st_shared_u8(smem_addr: Int32, value: Uint8, *, loc=None, ip=None):\n \"\"\"Store 8 bits to shared memory. smem_addr is a u32 shared-memory address.\"\"\"\n llvm.inline_asm(\n None,\n [\n Int32(smem_addr).ir_value(loc=loc, ip=ip),\n Uint8(value).ir_value(loc=loc, ip=ip),\n ],\n \"st.shared.u8 [$0], $1;\",\n \"r,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n\n\n# =============================================================================\n# PTX Intrinsics — Global Atomics\n# =============================================================================\n\n\n@dsl_user_op\ndef atomic_add_global_i32(addr: Int64, val: Int32, *, loc=None, ip=None) -> Int32:\n \"\"\"Global memory int32 atomic add. Returns old value.\"\"\"\n return Int32(\n llvm.inline_asm(\n T.i32(),\n [\n Int64(addr).ir_value(loc=loc, ip=ip),\n Int32(val).ir_value(loc=loc, ip=ip),\n ],\n \"atom.global.add.s32 $0, [$1], $2;\",\n \"=r,l,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef atomic_cas_global_i32(\n addr: Int64, compare: Int32, value: Int32, *, loc=None, ip=None\n) -> Int32:\n \"\"\"Global memory int32 atomic compare-and-swap. Returns old value.\"\"\"\n return Int32(\n llvm.inline_asm(\n T.i32(),\n [\n Int64(addr).ir_value(loc=loc, ip=ip),\n Int32(compare).ir_value(loc=loc, ip=ip),\n Int32(value).ir_value(loc=loc, ip=ip),\n ],\n \"atom.global.cas.b32 $0, [$1], $2, $3;\",\n \"=r,l,r,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef ld_global_acquire_i32(addr: Int64, *, loc=None, ip=None) -> Int32:\n \"\"\"Load int32 from global memory with acquire semantics.\"\"\"\n return Int32(\n llvm.inline_asm(\n T.i32(),\n [Int64(addr).ir_value(loc=loc, ip=ip)],\n \"ld.global.acquire.gpu.s32 $0, [$1];\",\n \"=r,l\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef st_global_release_i32(addr: Int64, val: Int32, *, loc=None, ip=None):\n \"\"\"Store int32 to global memory with release semantics.\"\"\"\n llvm.inline_asm(\n None,\n [\n Int64(addr).ir_value(loc=loc, ip=ip),\n Int32(val).ir_value(loc=loc, ip=ip),\n ],\n \"st.global.release.gpu.s32 [$0], $1;\",\n \"l,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n\n@dsl_user_op\ndef spin_wait_global_eq_i32(addr: Int64, expected: Int32, *, loc=None, ip=None):\n \"\"\"Spin while *addr == expected, then continue with acquire semantics.\"\"\"\n llvm.inline_asm(\n None,\n [\n Int64(addr).ir_value(loc=loc, ip=ip),\n Int32(expected).ir_value(loc=loc, ip=ip),\n ],\n \"{\\n\"\n \".reg .pred %p0;\\n\"\n \".reg .s32 %val;\\n\"\n \"spin_loop:\\n\"\n \" ld.global.acquire.gpu.s32 %val, [$0];\\n\"\n \" setp.eq.s32 %p0, %val, $1;\\n\"\n \" @%p0 bra spin_loop;\\n\"\n \"}\",\n \"l,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n\n@dsl_user_op\ndef threadfence(*, loc=None, ip=None):\n \"\"\"Emit a global-memory fence.\"\"\"\n llvm.inline_asm(\n None,\n [],\n \"membar.gl;\",\n \"\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n\n# =============================================================================\n# PTX Intrinsics — Scatter Atomics (BF16)\n# =============================================================================\n\n\n@dsl_user_op\ndef scatter_add_bf16x2(addr: Int64, val0_f32, val1_f32, *, loc=None, ip=None):\n \"\"\"BF16x2 atomic reduction add to global memory.\n\n Packs two f32 values into bf16x2 via cvt.rn.satfinite, then does\n red.relaxed.gpu.global.add.noftz.bf16x2.\n \"\"\"\n llvm.inline_asm(\n None,\n [\n Int64(addr).ir_value(loc=loc, ip=ip),\n val0_f32.ir_value(loc=loc, ip=ip),\n val1_f32.ir_value(loc=loc, ip=ip),\n ],\n \"{ .reg .b32 packed;\"\n \" cvt.rn.satfinite.bf16x2.f32 packed, $2, $1;\"\n \" red.relaxed.gpu.global.add.noftz.bf16x2 [$0], packed; }\",\n \"l,f,f\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n\n\n@dsl_user_op\ndef scatter_add_v4_bf16x2(\n addr: Int64, v0, v1, v2, v3, v4, v5, v6, v7, *, loc=None, ip=None\n):\n \"\"\"Vectorized BF16x2 atomic reduction of 8 f32 values.\"\"\"\n llvm.inline_asm(\n None,\n [\n Int64(addr).ir_value(loc=loc, ip=ip),\n v0.ir_value(loc=loc, ip=ip),\n v1.ir_value(loc=loc, ip=ip),\n v2.ir_value(loc=loc, ip=ip),\n v3.ir_value(loc=loc, ip=ip),\n v4.ir_value(loc=loc, ip=ip),\n v5.ir_value(loc=loc, ip=ip),\n v6.ir_value(loc=loc, ip=ip),\n v7.ir_value(loc=loc, ip=ip),\n ],\n \"{ .reg .b32 p0,p1,p2,p3;\"\n \" cvt.rn.satfinite.bf16x2.f32 p0, $2, $1;\"\n \" cvt.rn.satfinite.bf16x2.f32 p1, $4, $3;\"\n \" cvt.rn.satfinite.bf16x2.f32 p2, $6, $5;\"\n \" cvt.rn.satfinite.bf16x2.f32 p3, $8, $7;\"\n \" red.global.add.noftz.v4.bf16x2 [$0], {p0, p1, p2, p3}; }\",\n \"l,f,f,f,f,f,f,f,f\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n\n# =============================================================================\n# FP8 Conversion — Non-reciprocal version\n# =============================================================================\n\n\n@dsl_user_op\ndef fp8_e4m3_to_f32(fp8_val: Uint32, *, loc=None, ip=None) -> Float32:\n \"\"\"Convert FP8 E4M3 to float32.\n\n Uses the hardware conversion instruction, which is exact for every\n finite e4m3 value, including subnormals, and matches how the tensor\n core decodes the same byte.\n \"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Uint32(fp8_val).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 fp8_pair;\n .reg .b32 h2_32;\n .reg .b16 h_lo, h_hi;\n\n cvt.u16.u32 fp8_pair, $1;\n cvt.rn.f16x2.e4m3x2 h2_32, fp8_pair;\n mov.b32 {h_lo, h_hi}, h2_32;\n cvt.f32.f16 $0, h_lo;\n }\n \"\"\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef nvfp4_scale_from_amax(\n block_amax: Float32, global_scale: Float32, *, loc=None, ip=None\n) -> Float32:\n \"\"\"Compute the NVFP4 block scale from an amax and global scale.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [\n Float32(block_amax).ir_value(loc=loc, ip=ip),\n Float32(global_scale).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .f64 amax_d, gs_d, q_d, six_d;\n cvt.f64.f32 amax_d, $1;\n cvt.f64.f32 gs_d, $2;\n mov.f64 six_d, 0d4018000000000000;\n mul.rn.f64 q_d, amax_d, gs_d;\n div.rn.f64 q_d, q_d, six_d;\n cvt.rn.f32.f64 $0, q_d;\n }\n \"\"\",\n \"=f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef nvfp4_scale_from_amax_rn(\n block_amax: Float32, global_scale: Float32, *, loc=None, ip=None\n) -> Float32:\n \"\"\"Compute NVFP4 block scale with round-to-nearest FP32 operations.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [\n Float32(block_amax).ir_value(loc=loc, ip=ip),\n Float32(global_scale).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .pred p_zero;\n .reg .f32 scale_mul, result;\n setp.eq.f32 p_zero, $1, 0f00000000;\n mul.rn.f32 scale_mul, $2, 0f3E2AAAAB;\n mul.rn.f32 result, $1, scale_mul;\n selp.f32 $0, 0f00000000, result, p_zero;\n }\n \"\"\",\n \"=f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef cvt_e4m3x2_to_f16x2_pair(\n packed_u32: Uint32, *, loc=None, ip=None\n) -> Tuple[Uint32, Uint32]:\n \"\"\"Decode 4 packed E4M3 bytes into two f16x2 registers.\"\"\"\n res = llvm.inline_asm(\n ir.Type.parse(\"!llvm.struct<(i32, i32)>\"),\n [Uint32(packed_u32).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 b16_01, b16_23;\n .reg .b32 hi32;\n cvt.u16.u32 b16_01, $2;\n shr.b32 hi32, $2, 16;\n cvt.u16.u32 b16_23, hi32;\n cvt.rn.f16x2.e4m3x2 $0, b16_01;\n cvt.rn.f16x2.e4m3x2 $1, b16_23;\n }\n \"\"\",\n \"=r,=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n return (\n Uint32(llvm.extractvalue(T.i32(), res, [0], loc=loc, ip=ip)),\n Uint32(llvm.extractvalue(T.i32(), res, [1], loc=loc, ip=ip)),\n )\n\n\n@dsl_user_op\ndef f16x2_to_f32x2(packed_h2: Uint32, *, loc=None, ip=None) -> Tuple[Float32, Float32]:\n \"\"\"Unpack one f16x2 register into two f32 values.\"\"\"\n res = llvm.inline_asm(\n ir.Type.parse(\"!llvm.struct<(f32, f32)>\"),\n [Uint32(packed_h2).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 lo, hi;\n mov.b32 {lo, hi}, $2;\n cvt.f32.f16 $0, lo;\n cvt.f32.f16 $1, hi;\n }\n \"\"\",\n \"=f,=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n return (\n Float32(llvm.extractvalue(T.f32(), res, [0], loc=loc, ip=ip)),\n Float32(llvm.extractvalue(T.f32(), res, [1], loc=loc, ip=ip)),\n )\n\n\n@dsl_user_op\ndef cvt_e4m3_to_f32_via_f16(fp8_val: Uint32, *, loc=None, ip=None) -> Float32:\n \"\"\"Convert one E4M3 byte to f32 through native E4M3-to-f16 conversion.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Uint32(fp8_val).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 fp8_pair;\n .reg .b32 h2;\n .reg .b16 lo, hi;\n cvt.u16.u32 fp8_pair, $1;\n cvt.rn.f16x2.e4m3x2 h2, fp8_pair;\n mov.b32 {lo, hi}, h2;\n cvt.f32.f16 $0, lo;\n }\n \"\"\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef cvt_s0e5m3_to_f16x2_broadcast(fp8_val: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Convert one S0E5M3 scale byte to an f16x2 with the scale in both lanes.\n\n S0E5M3 (sign-0, 5-exp, 3-mantissa) is a host-side reformat of the per-block\n E4M3 scale, rebiased to fp16's bias (exp 7->15, i.e. byte += 0x40) so the\n bits line up with fp16 directly: ``f16(byte) = byte << 7`` (exp -> bits 14-10,\n the 3 mantissa bits -> bits 9-7, low mantissa and sign = 0). Broadcasting to\n both f16x2 lanes is then ``byte * 0x00800080`` = ``(byte<<7) | (byte<<23)`` --\n a single ``mul.lo.u32`` (the two shifted copies never overlap, so the mul is\n exactly the OR). Replaces the 3-op E4M3 path (cvt.u16 + cvt.f16x2.e4m3x2 +\n prmt) with 1 op, and the per-block scale stays 1 byte (memory-neutral).\n Numerically exact for normal E4M3 scales (both formats carry 3 mantissa bits).\n \"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(fp8_val).ir_value(loc=loc, ip=ip)],\n \"mul.lo.u32 $0, $1, 0x00800080;\",\n \"=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef fp4_decode_4bytes(\n packed_u32: Uint32, *, loc=None, ip=None\n) -> Tuple[Uint32, Uint32, Uint32, Uint32]:\n \"\"\"Decode 4 packed FP4 bytes into four f16x2 registers.\"\"\"\n res = llvm.inline_asm(\n ir.Type.parse(\"!llvm.struct<(i32, i32, i32, i32)>\"),\n [Uint32(packed_u32).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b8 byte0, byte1, byte2, byte3;\n mov.b32 {byte0, byte1, byte2, byte3}, $4;\n cvt.rn.f16x2.e2m1x2 $0, byte0;\n cvt.rn.f16x2.e2m1x2 $1, byte1;\n cvt.rn.f16x2.e2m1x2 $2, byte2;\n cvt.rn.f16x2.e2m1x2 $3, byte3;\n }\n \"\"\",\n \"=r,=r,=r,=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n return (\n Uint32(llvm.extractvalue(T.i32(), res, [0], loc=loc, ip=ip)),\n Uint32(llvm.extractvalue(T.i32(), res, [1], loc=loc, ip=ip)),\n Uint32(llvm.extractvalue(T.i32(), res, [2], loc=loc, ip=ip)),\n Uint32(llvm.extractvalue(T.i32(), res, [3], loc=loc, ip=ip)),\n )\n\n\n@dsl_user_op\ndef fp4_decode_2(byte_val: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Decode one FP4 byte into one f16x2 register.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(byte_val).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b8 b0;\n cvt.u8.u32 b0, $1;\n cvt.rn.f16x2.e2m1x2 $0, b0;\n }\n \"\"\",\n \"=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef cvt_fp32x2_to_e2m1x2(v0: Float32, v1: Float32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Convert two f32 values into one packed E2M1 byte.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [\n Float32(v0).ir_value(loc=loc, ip=ip),\n Float32(v1).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b8 b;\n cvt.rn.satfinite.e2m1x2.f32 b, $2, $1;\n cvt.u32.u8 $0, b;\n }\n \"\"\",\n \"=r,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@cute.jit\ndef quant_dequant_2(\n v0: Float32, v1: Float32, sf_f32: Float32, eff_scale: Float32\n) -> Tuple[Float32, Float32]:\n \"\"\"Quantize/dequantize two values through FP4.\"\"\"\n inv_scale = Float32(1.0) / eff_scale\n fp4_byte = cvt_fp32x2_to_e2m1x2(v0 * inv_scale, v1 * inv_scale)\n h2 = fp4_decode_2(fp4_byte)\n f0, f1 = f16x2_to_f32x2(h2)\n return f0 * sf_f32, f1 * sf_f32\n\n\n@dsl_user_op\ndef fp4_dot4_sum(\n u_packed: Uint32,\n x0: Uint32,\n x1: Uint32,\n x2: Uint32,\n x3: Uint32,\n *,\n loc=None,\n ip=None,\n) -> Float32:\n \"\"\"Decode 4 FP4 bytes and dot with four f16x2 inputs.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [\n Uint32(u_packed).ir_value(loc=loc, ip=ip),\n Uint32(x0).ir_value(loc=loc, ip=ip),\n Uint32(x1).ir_value(loc=loc, ip=ip),\n Uint32(x2).ir_value(loc=loc, ip=ip),\n Uint32(x3).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b8 b0, b1, b2, b3;\n .reg .b32 h0, h1, h2, h3;\n .reg .f16x2 acc;\n .reg .b16 lo, hi;\n .reg .f32 flo, fhi;\n mov.b32 {b0, b1, b2, b3}, $1;\n cvt.rn.f16x2.e2m1x2 h0, b0;\n cvt.rn.f16x2.e2m1x2 h1, b1;\n cvt.rn.f16x2.e2m1x2 h2, b2;\n cvt.rn.f16x2.e2m1x2 h3, b3;\n mov.b32 acc, 0;\n fma.rn.f16x2 acc, h0, $2, acc;\n fma.rn.f16x2 acc, h1, $3, acc;\n fma.rn.f16x2 acc, h2, $4, acc;\n fma.rn.f16x2 acc, h3, $5, acc;\n mov.b32 {lo, hi}, acc;\n cvt.f32.f16 flo, lo;\n cvt.f32.f16 fhi, hi;\n add.f32 $0, flo, fhi;\n }\n \"\"\",\n \"=f,r,r,r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef fp4_dot8_sum(\n u_a: Uint32,\n u_b: Uint32,\n x0: Uint32,\n x1: Uint32,\n x2: Uint32,\n x3: Uint32,\n x4: Uint32,\n x5: Uint32,\n x6: Uint32,\n x7: Uint32,\n *,\n loc=None,\n ip=None,\n) -> Float32:\n \"\"\"Decode 8 FP4 bytes and dot with eight f16x2 inputs.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [\n Uint32(u_a).ir_value(loc=loc, ip=ip),\n Uint32(u_b).ir_value(loc=loc, ip=ip),\n Uint32(x0).ir_value(loc=loc, ip=ip),\n Uint32(x1).ir_value(loc=loc, ip=ip),\n Uint32(x2).ir_value(loc=loc, ip=ip),\n Uint32(x3).ir_value(loc=loc, ip=ip),\n Uint32(x4).ir_value(loc=loc, ip=ip),\n Uint32(x5).ir_value(loc=loc, ip=ip),\n Uint32(x6).ir_value(loc=loc, ip=ip),\n Uint32(x7).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b8 a0, a1, a2, a3;\n .reg .b8 b0, b1, b2, b3;\n .reg .b32 h0, h1, h2, h3, h4, h5, h6, h7;\n .reg .f16x2 acc;\n .reg .b16 lo, hi;\n .reg .f32 flo, fhi;\n mov.b32 {a0, a1, a2, a3}, $1;\n mov.b32 {b0, b1, b2, b3}, $2;\n cvt.rn.f16x2.e2m1x2 h0, a0;\n cvt.rn.f16x2.e2m1x2 h1, a1;\n cvt.rn.f16x2.e2m1x2 h2, a2;\n cvt.rn.f16x2.e2m1x2 h3, a3;\n cvt.rn.f16x2.e2m1x2 h4, b0;\n cvt.rn.f16x2.e2m1x2 h5, b1;\n cvt.rn.f16x2.e2m1x2 h6, b2;\n cvt.rn.f16x2.e2m1x2 h7, b3;\n mov.b32 acc, 0;\n fma.rn.f16x2 acc, h0, $3, acc;\n fma.rn.f16x2 acc, h1, $4, acc;\n fma.rn.f16x2 acc, h2, $5, acc;\n fma.rn.f16x2 acc, h3, $6, acc;\n fma.rn.f16x2 acc, h4, $7, acc;\n fma.rn.f16x2 acc, h5, $8, acc;\n fma.rn.f16x2 acc, h6, $9, acc;\n fma.rn.f16x2 acc, h7, $10, acc;\n mov.b32 {lo, hi}, acc;\n cvt.f32.f16 flo, lo;\n cvt.f32.f16 fhi, hi;\n add.f32 $0, flo, fhi;\n }\n \"\"\",\n \"=f,r,r,r,r,r,r,r,r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@cute.jit\ndef _f16x2_dot_sum_f32acc(a_h2: Uint32, b_h2: Uint32) -> Float32:\n a0, a1 = f16x2_to_f32x2(a_h2)\n b0, b1 = f16x2_to_f32x2(b_h2)\n return a0 * b0 + a1 * b1\n\n\n@cute.jit\ndef fp4_dot4_sum_f32acc(\n u_packed: Uint32,\n x0: Uint32,\n x1: Uint32,\n x2: Uint32,\n x3: Uint32,\n) -> Float32:\n \"\"\"Decode FP4 then accumulate a 4-byte dot product in f32.\"\"\"\n h0, h1, h2, h3 = fp4_decode_4bytes(u_packed)\n return (\n _f16x2_dot_sum_f32acc(h0, x0)\n + _f16x2_dot_sum_f32acc(h1, x1)\n + _f16x2_dot_sum_f32acc(h2, x2)\n + _f16x2_dot_sum_f32acc(h3, x3)\n )\n\n\n@cute.jit\ndef fp4_dot8_sum_f32acc(\n u_a: Uint32,\n u_b: Uint32,\n x0: Uint32,\n x1: Uint32,\n x2: Uint32,\n x3: Uint32,\n x4: Uint32,\n x5: Uint32,\n x6: Uint32,\n x7: Uint32,\n) -> Float32:\n \"\"\"Decode FP4 then accumulate an 8-byte dot product in f32.\"\"\"\n h0, h1, h2, h3 = fp4_decode_4bytes(u_a)\n h4, h5, h6, h7 = fp4_decode_4bytes(u_b)\n return (\n _f16x2_dot_sum_f32acc(h0, x0)\n + _f16x2_dot_sum_f32acc(h1, x1)\n + _f16x2_dot_sum_f32acc(h2, x2)\n + _f16x2_dot_sum_f32acc(h3, x3)\n + _f16x2_dot_sum_f32acc(h4, x4)\n + _f16x2_dot_sum_f32acc(h5, x5)\n + _f16x2_dot_sum_f32acc(h6, x6)\n + _f16x2_dot_sum_f32acc(h7, x7)\n )\n\n\n@dsl_user_op\ndef pack_f32x2_to_f16x2(a: Float32, b: Float32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Pack two f32 values into one f16x2 register.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [\n Float32(a).ir_value(loc=loc, ip=ip),\n Float32(b).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b16 lo, hi;\n cvt.rn.f16.f32 lo, $1;\n cvt.rn.f16.f32 hi, $2;\n mov.b32 $0, {lo, hi};\n }\n \"\"\",\n \"=r,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n# =============================================================================\n# FP4 Quantization — Fast approximate path\n# =============================================================================\n\n\n@cute.jit\ndef quantize_and_pack_16_fast(y_f32: cute.Tensor, inv_scale: Float32) -> Uint64:\n \"\"\"Fast approximate FP4 quantize/pack for 16 float32 values.\"\"\"\n q = cute.make_rmem_tensor((16,), Float32)\n for i in cutlass.range_constexpr(16):\n q[i] = y_f32[i] * inv_scale\n\n packed_lo = cvt_e2m1x8_f32(q[0], q[1], q[2], q[3], q[4], q[5], q[6], q[7])\n packed_hi = cvt_e2m1x8_f32(q[8], q[9], q[10], q[11], q[12], q[13], q[14], q[15])\n return (Uint64(packed_hi) << Uint64(32)) | Uint64(packed_lo)\n\n\n# =============================================================================\n# FP4 Block Quantization Helpers (for MoE kernels)\n# =============================================================================\n\n\n@cute.jit\ndef quantize_block_fp4(\n values: cute.Tensor,\n max_abs: Float32,\n global_scale_val: Float32,\n) -> Tuple[Uint64, Uint8]:\n \"\"\"Quantize 16 float32 values to packed FP4 + e4m3 scale byte.\n\n Given 16 values and their pre-computed max_abs, derives the NVFP4 block\n scale, quantizes to FP4, and packs into a uint64. Returns\n (packed_fp4_u64, scale_byte).\n \"\"\"\n scale_float = max_abs / (Float32(FLOAT4_E2M1_MAX) * global_scale_val)\n scale_float = fmin_f32(scale_float, Float32(FLOAT8_E4M3_MAX))\n scale_u32 = cvt_f32_to_e4m3(scale_float)\n scale_byte = Uint8(scale_u32 & Uint32(0xFF))\n quantized_scale = fp8_e4m3_to_f32(scale_u32)\n packed64 = Uint64(0)\n if quantized_scale != Float32(0.0) and global_scale_val != Float32(0.0):\n # 1/(qs*gs): precise counterpart of the fast path's rcp(qs)*rcp(gs).\n packed64 = quantize_and_pack_16(\n values, Float32(1.0) / (quantized_scale * global_scale_val)\n )\n return packed64, scale_byte\n\n\n@cute.jit\ndef quantize_block_fp4_fast(\n values: cute.Tensor,\n max_abs: Float32,\n global_scale_val: Float32,\n) -> Tuple[Uint64, Uint8]:\n \"\"\"Fast approximate FP4 block quantization using reciprocal/vector path.\"\"\"\n scale_u32 = Uint32(0)\n scale_byte = Uint8(0)\n packed64 = Uint64(0)\n if global_scale_val != Float32(0.0):\n fp4_max_rcp = rcp_approx_ftz(Float32(FLOAT4_E2M1_MAX))\n gs_recip = rcp_approx_ftz(global_scale_val)\n scale_float = gs_recip * (max_abs * fp4_max_rcp)\n scale_float = fmin_f32(scale_float, Float32(FLOAT8_E4M3_MAX))\n scale_u32 = cvt_f32_to_e4m3(scale_float)\n scale_byte = Uint8(scale_u32 & Uint32(0xFF))\n inv_quantized_scale = fp8_e4m3_to_f32_and_rcp(scale_u32)\n if inv_quantized_scale != Float32(0.0):\n packed64 = quantize_and_pack_16_fast(values, inv_quantized_scale * gs_recip)\n return packed64, scale_byte\n\n\n@cute.jit\ndef max_abs_16(values: cute.Tensor) -> Float32:\n \"\"\"Compute the maximum absolute value of 16 float32 values.\"\"\"\n result = fabs_f32(values[0])\n for i in cutlass.range_constexpr(1, 16):\n result = fmax_f32(result, fabs_f32(values[i]))\n return result\n\n\n@cute.jit\ndef silu_mul_16(\n gate: cute.Tensor,\n up: cute.Tensor,\n) -> cute.Tensor:\n \"\"\"Fused SiLU(gate) * up for 16 float32 element pairs.\n\n Used in MoE kernel epilogue to fuse the activation function\n between GEMM1 and GEMM2, avoiding the gmem round-trip.\n \"\"\"\n out = cute.make_rmem_tensor((16,), Float32)\n for i in cutlass.range_constexpr(16):\n g = gate[i]\n sigmoid_g = cute.arch.rcp_approx(\n Float32(1.0) + cute.math.exp(-g, fastmath=False)\n )\n out[i] = g * sigmoid_g * up[i]\n return out\n\n\n@cute.jit\ndef silu_mul_quantize_block_fp4(\n gate: cute.Tensor,\n up: cute.Tensor,\n global_scale_val: Float32,\n) -> Tuple[Uint64, Uint8]:\n \"\"\"Fused SiLU(gate)*up + FP4 quantize for 16 element pairs.\"\"\"\n activated = silu_mul_16(gate, up)\n block_max = max_abs_16(activated)\n return quantize_block_fp4(activated, block_max, global_scale_val)\n\n\n# =============================================================================\n# ReLU2 Activation — ReLU(x)² for non-gated MoE (Nemotron-Super)\n# =============================================================================\n\n\n@cute.jit\ndef relu2_16(x: cute.Tensor) -> cute.Tensor:\n \"\"\"Compute ReLU²(x) = max(0, x)² for 16 float32 values.\"\"\"\n out = cute.make_rmem_tensor((16,), Float32)\n for i in cutlass.range_constexpr(16):\n v = fmax_f32(x[i], Float32(0.0))\n out[i] = v * v\n return out\n\n\n@cute.jit\ndef relu2_quantize_block_fp4(\n x: cute.Tensor,\n global_scale_val: Float32,\n) -> Tuple[Uint64, Uint8]:\n \"\"\"Fused ReLU² + FP4 quantize for 16 float32 values.\"\"\"\n activated = relu2_16(x)\n block_max = max_abs_16(activated)\n return quantize_block_fp4(activated, block_max, global_scale_val)\n"},"after_code":{"kind":"string","value":"\"\"\"\nCopyright (c) 2025 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nCommon utilities for FP4 quantization kernels using CuTe-DSL.\n\nThis module contains shared PTX intrinsics, helper functions, and reduction\nutilities used by both rmsnorm_fp4quant.py and add_rmsnorm_fp4quant.py.\n\"\"\"\n\nimport functools\nimport math\nimport operator\nfrom typing import Callable, Tuple\n\nimport cutlass\nimport cutlass.cute as cute\nimport torch\nfrom cutlass import Float32, Int32, Int64, Uint8, Uint32, Uint64\nfrom cutlass.cutlass_dsl import T, dsl_user_op\nfrom cutlass._mlir import ir\nfrom cutlass._mlir.dialects import llvm\n\n\n# =============================================================================\n# Constants\n# =============================================================================\n\nFLOAT4_E2M1_MAX = 6.0 # Maximum value representable in FP4 E2M1\nFLOAT8_E4M3_MAX = 448.0 # Maximum value representable in FP8 E4M3\nSF_VEC_SIZE = 16 # Elements per scale factor block\nCOPY_BITS = 128 # 128-bit vectorized loads\n\n\n# =============================================================================\n# Architecture Detection\n# =============================================================================\n\n\n@functools.lru_cache(maxsize=16)\ndef get_sm_version(device: int | torch.device | str | None = None) -> int:\n \"\"\"Get the SM version of a CUDA device.\n\n Args:\n device: CUDA device to query. Can be an int (device index), torch.device,\n device string (e.g., 'cuda:0'), or None to use current device.\n\n Returns:\n SM version as an integer (e.g., 100 for SM100).\n \"\"\"\n if not torch.cuda.is_available():\n return 80\n if device is None:\n device = torch.cuda.current_device()\n props = torch.cuda.get_device_properties(device)\n return props.major * 10 + props.minor\n\n\n# =============================================================================\n# PTX Intrinsics - Cluster Operations\n# =============================================================================\n\n\n@dsl_user_op\ndef set_block_rank(\n smem_ptr: cute.Pointer, peer_cta_rank_in_cluster: Int32, *, loc=None, ip=None\n) -> Int32:\n \"\"\"Map smem pointer to address at another CTA rank in the cluster.\"\"\"\n smem_ptr_i32 = smem_ptr.toint(loc=loc, ip=ip).ir_value()\n return Int32(\n llvm.inline_asm(\n T.i32(),\n [smem_ptr_i32, peer_cta_rank_in_cluster.ir_value()],\n \"mapa.shared::cluster.u32 $0, $1, $2;\",\n \"=r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef store_shared_remote(\n val: Float32,\n smem_ptr: cute.Pointer,\n mbar_ptr: cute.Pointer,\n peer_cta_rank_in_cluster: Int32,\n *,\n loc=None,\n ip=None,\n) -> None:\n \"\"\"Store Float32 value to shared memory on a remote CTA in the cluster.\"\"\"\n remote_smem_ptr_i32 = set_block_rank(\n smem_ptr, peer_cta_rank_in_cluster, loc=loc, ip=ip\n ).ir_value()\n remote_mbar_ptr_i32 = set_block_rank(\n mbar_ptr, peer_cta_rank_in_cluster, loc=loc, ip=ip\n ).ir_value()\n llvm.inline_asm(\n None,\n [remote_smem_ptr_i32, val.ir_value(loc=loc, ip=ip), remote_mbar_ptr_i32],\n \"st.async.shared::cluster.mbarrier::complete_tx::bytes.f32 [$0], $1, [$2];\",\n \"r,f,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n\n\n@dsl_user_op\ndef elem_pointer(x: cute.Tensor, coord, *, loc=None, ip=None) -> cute.Pointer:\n \"\"\"Get pointer to element at coordinate in tensor.\"\"\"\n return x.iterator + cute.crd2idx(coord, x.layout, loc=loc, ip=ip)\n\n\n# =============================================================================\n# PTX Intrinsics - 128-bit Vectorized Global Loads/Stores\n# =============================================================================\n\n\n@dsl_user_op\ndef ld_global_v4_u32(\n base_ptr: Int64, *, loc=None, ip=None\n) -> Tuple[Uint32, Uint32, Uint32, Uint32]:\n \"\"\"Load 128 bits (4 x uint32) from global memory.\"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.i32(), T.i32(), T.i32(), T.i32()]),\n [Int64(base_ptr).ir_value(loc=loc, ip=ip)],\n \"ld.global.v4.u32 {$0, $1, $2, $3}, [$4];\",\n \"=r,=r,=r,=r,l\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n v0 = llvm.extractvalue(T.i32(), result, [0], loc=loc, ip=ip)\n v1 = llvm.extractvalue(T.i32(), result, [1], loc=loc, ip=ip)\n v2 = llvm.extractvalue(T.i32(), result, [2], loc=loc, ip=ip)\n v3 = llvm.extractvalue(T.i32(), result, [3], loc=loc, ip=ip)\n\n return Uint32(v0), Uint32(v1), Uint32(v2), Uint32(v3)\n\n\n@dsl_user_op\ndef ld_v4_u32(\n base_ptr: Int64, *, loc=None, ip=None\n) -> Tuple[Uint32, Uint32, Uint32, Uint32]:\n \"\"\"Load 128 bits (4 x uint32) using generic addressing (works for GMEM and SMEM).\"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.i32(), T.i32(), T.i32(), T.i32()]),\n [Int64(base_ptr).ir_value(loc=loc, ip=ip)],\n \"ld.v4.u32 {$0, $1, $2, $3}, [$4];\",\n \"=r,=r,=r,=r,l\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n v0 = llvm.extractvalue(T.i32(), result, [0], loc=loc, ip=ip)\n v1 = llvm.extractvalue(T.i32(), result, [1], loc=loc, ip=ip)\n v2 = llvm.extractvalue(T.i32(), result, [2], loc=loc, ip=ip)\n v3 = llvm.extractvalue(T.i32(), result, [3], loc=loc, ip=ip)\n\n return Uint32(v0), Uint32(v1), Uint32(v2), Uint32(v3)\n\n\n@dsl_user_op\ndef ld_global_nc_u32(base_ptr: Int64, *, loc=None, ip=None) -> Uint32:\n \"\"\"Load 32 bits from global memory through the non-coherent cache.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Int64(base_ptr).ir_value(loc=loc, ip=ip)],\n \"ld.global.nc.u32 $0, [$1];\",\n \"=r,l\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef ld_global_nc_v4_u32(\n base_ptr: Int64, *, loc=None, ip=None\n) -> Tuple[Uint32, Uint32, Uint32, Uint32]:\n \"\"\"Load 128 bits from global memory through the non-coherent cache.\"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.i32(), T.i32(), T.i32(), T.i32()]),\n [Int64(base_ptr).ir_value(loc=loc, ip=ip)],\n \"ld.global.nc.v4.u32 {$0, $1, $2, $3}, [$4];\",\n \"=r,=r,=r,=r,l\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n return (\n Uint32(llvm.extractvalue(T.i32(), result, [0], loc=loc, ip=ip)),\n Uint32(llvm.extractvalue(T.i32(), result, [1], loc=loc, ip=ip)),\n Uint32(llvm.extractvalue(T.i32(), result, [2], loc=loc, ip=ip)),\n Uint32(llvm.extractvalue(T.i32(), result, [3], loc=loc, ip=ip)),\n )\n\n\n@dsl_user_op\ndef prefetch_global_l2(base_ptr: Int64, *, loc=None, ip=None) -> None:\n \"\"\"Prefetch a global memory line into L2.\"\"\"\n llvm.inline_asm(\n None,\n [Int64(base_ptr).ir_value(loc=loc, ip=ip)],\n \"prefetch.global.L2 [$0];\",\n \"l\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n\n@dsl_user_op\ndef st_global_u64(base_ptr: Int64, value: Uint64, *, loc=None, ip=None):\n \"\"\"Store 64 bits to global memory.\"\"\"\n llvm.inline_asm(\n None,\n [\n Int64(base_ptr).ir_value(loc=loc, ip=ip),\n Uint64(value).ir_value(loc=loc, ip=ip),\n ],\n \"st.global.u64 [$0], $1;\",\n \"l,l\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n\n\n@dsl_user_op\ndef st_global_u32(base_ptr: Int64, value: Uint32, *, loc=None, ip=None):\n \"\"\"Store 32 bits to global memory.\"\"\"\n llvm.inline_asm(\n None,\n [\n Int64(base_ptr).ir_value(loc=loc, ip=ip),\n Uint32(value).ir_value(loc=loc, ip=ip),\n ],\n \"st.global.u32 [$0], $1;\",\n \"l,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n\n\n@dsl_user_op\ndef get_ptr_as_int64(tensor: cute.Tensor, offset, *, loc=None, ip=None) -> Int64:\n \"\"\"Get the memory address of tensor[offset] as Int64.\n\n ``offset`` may be Int32 or Int64 and is added to the iterator unchanged,\n so 64-bit offsets are not truncated.\n\n WARNING: This uses ptrtoint which strips address space information.\n For SMEM tensors, the resulting Int64 is a raw SMEM offset that does NOT\n work with generic-addressing loads (ld.v4.u32). Use only with explicit\n address-space loads (ld.global.*) or for global memory tensors.\n \"\"\"\n elem_ptr = tensor.iterator + offset\n ptr_int = llvm.ptrtoint(T.i64(), elem_ptr.llvm_ptr, loc=loc, ip=ip)\n return Int64(ptr_int)\n\n\n@dsl_user_op\ndef get_smem_ptr_as_int32(\n tensor: cute.Tensor, offset: Int32, *, loc=None, ip=None\n) -> Int32:\n \"\"\"Get the shared-memory byte address of tensor[offset] as Int32.\n\n Uses Pointer.toint() which preserves the SMEM address space (addrspace 3),\n returning a 32-bit SMEM address suitable for ld.shared.* instructions.\n \"\"\"\n elem_ptr = tensor.iterator + Int32(offset)\n return elem_ptr.toint(loc=loc, ip=ip)\n\n\n@dsl_user_op\ndef ld_shared_v2_u32(smem_addr: Int32, *, loc=None, ip=None) -> Tuple[Uint32, Uint32]:\n \"\"\"Load 64 bits (2 x uint32) from shared memory via ld.shared.v2.u32.\n\n Args:\n smem_addr: 32-bit shared memory address (from get_smem_ptr_as_int32).\n Caller is responsible for ensuring 8-byte alignment.\n\n Returns:\n 2 Uint32 values (8 bytes total).\n \"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.i32(), T.i32()]),\n [Int32(smem_addr).ir_value(loc=loc, ip=ip)],\n \"ld.shared.v2.u32 {$0, $1}, [$2];\",\n \"=r,=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n v0 = llvm.extractvalue(T.i32(), result, [0], loc=loc, ip=ip)\n v1 = llvm.extractvalue(T.i32(), result, [1], loc=loc, ip=ip)\n return Uint32(v0), Uint32(v1)\n\n\n@dsl_user_op\ndef ld_shared_v4_u32(\n smem_addr: Int32, *, loc=None, ip=None\n) -> Tuple[Uint32, Uint32, Uint32, Uint32]:\n \"\"\"Load 128 bits (4 x uint32) from shared memory via ld.shared.v4.u32.\n\n Args:\n smem_addr: 32-bit shared memory address (from get_smem_ptr_as_int32).\n\n Returns:\n 4 Uint32 values (16 bytes total, e.g. 8 packed fp16 elements).\n \"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.i32(), T.i32(), T.i32(), T.i32()]),\n [Int32(smem_addr).ir_value(loc=loc, ip=ip)],\n \"ld.shared.v4.u32 {$0, $1, $2, $3}, [$4];\",\n \"=r,=r,=r,=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n v0 = llvm.extractvalue(T.i32(), result, [0], loc=loc, ip=ip)\n v1 = llvm.extractvalue(T.i32(), result, [1], loc=loc, ip=ip)\n v2 = llvm.extractvalue(T.i32(), result, [2], loc=loc, ip=ip)\n v3 = llvm.extractvalue(T.i32(), result, [3], loc=loc, ip=ip)\n return Uint32(v0), Uint32(v1), Uint32(v2), Uint32(v3)\n\n\n@dsl_user_op\ndef pack_16bit_to_u32(lo, hi, *, loc=None, ip=None) -> Uint32:\n \"\"\"Pack two 16-bit scalar values (fp16 or bf16) into one Uint32 (half2/bfloat2).\n\n Uses PTX mov.b32 to bitwise-pack two 16-bit register values into a single\n 32-bit register, suitable for half2/bfloat2 SIMD operations.\n \"\"\"\n lo_ir = lo.ir_value(loc=loc, ip=ip)\n hi_ir = hi.ir_value(loc=loc, ip=ip)\n lo_i16 = llvm.bitcast(T.i16(), lo_ir, loc=loc, ip=ip)\n hi_i16 = llvm.bitcast(T.i16(), hi_ir, loc=loc, ip=ip)\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [lo_i16, hi_i16],\n \"mov.b32 $0, {$1, $2};\",\n \"=r,h,h\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n# =============================================================================\n# PTX Intrinsics - Math Operations\n# =============================================================================\n\n\n@dsl_user_op\ndef rcp_approx_ftz(a: Float32, *, loc=None, ip=None) -> Float32:\n \"\"\"Fast reciprocal using PTX rcp.approx.ftz.f32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Float32(a).ir_value(loc=loc, ip=ip)],\n \"rcp.approx.ftz.f32 $0, $1;\",\n \"=f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef rcp_rn(a: Float32, *, loc=None, ip=None) -> Float32:\n \"\"\"Round-to-nearest reciprocal using PTX div.rn.f32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Float32(a).ir_value(loc=loc, ip=ip)],\n \"div.rn.f32 $0, 0f3F800000, $1;\",\n \"=f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef fadd_rn(a: Float32, b: Float32, loc=None, ip=None) -> Float32:\n \"\"\"Round-to-nearest float32 addition.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Float32(a).ir_value(loc=loc, ip=ip), Float32(b).ir_value(loc=loc, ip=ip)],\n \"add.rn.f32 $0, $1, $2;\",\n \"=f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef fsub_rn(a: Float32, b: Float32, loc=None, ip=None) -> Float32:\n \"\"\"Round-to-nearest float32 subtraction.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Float32(a).ir_value(loc=loc, ip=ip), Float32(b).ir_value(loc=loc, ip=ip)],\n \"sub.rn.f32 $0, $1, $2;\",\n \"=f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef fmul_rn(a: Float32, b: Float32, loc=None, ip=None) -> Float32:\n \"\"\"Round-to-nearest float32 multiplication.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Float32(a).ir_value(loc=loc, ip=ip), Float32(b).ir_value(loc=loc, ip=ip)],\n \"mul.rn.f32 $0, $1, $2;\",\n \"=f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef fdiv_rn(a: Float32, b: Float32, loc=None, ip=None) -> Float32:\n \"\"\"Round-to-nearest float32 division.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Float32(a).ir_value(loc=loc, ip=ip), Float32(b).ir_value(loc=loc, ip=ip)],\n \"div.rn.f32 $0, $1, $2;\",\n \"=f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef fmin_f32(a: Float32, b: Float32, *, loc=None, ip=None) -> Float32:\n \"\"\"Compute min of two float32 values using PTX min.f32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Float32(a).ir_value(loc=loc, ip=ip), Float32(b).ir_value(loc=loc, ip=ip)],\n \"min.f32 $0, $1, $2;\",\n \"=f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef fmax_f32(a: Float32, b: Float32, *, loc=None, ip=None) -> Float32:\n \"\"\"Compute max of two float32 values using PTX max.f32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Float32(a).ir_value(loc=loc, ip=ip), Float32(b).ir_value(loc=loc, ip=ip)],\n \"max.f32 $0, $1, $2;\",\n \"=f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef fabs_f32(a: Float32, *, loc=None, ip=None) -> Float32:\n \"\"\"Compute absolute value of float32 using PTX abs.f32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Float32(a).ir_value(loc=loc, ip=ip)],\n \"abs.f32 $0, $1;\",\n \"=f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n# =============================================================================\n# Half2 SIMD Intrinsics\n# =============================================================================\n\n\n@dsl_user_op\ndef half2_mul(a: Uint32, b: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Multiply two Half2 values element-wise: (a.x*b.x, a.y*b.y).\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(a).ir_value(loc=loc, ip=ip), Uint32(b).ir_value(loc=loc, ip=ip)],\n \"mul.f16x2 $0, $1, $2;\",\n \"=r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef hadd2(a: Uint32, b: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Add two Half2 values element-wise: (a.x+b.x, a.y+b.y).\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(a).ir_value(loc=loc, ip=ip), Uint32(b).ir_value(loc=loc, ip=ip)],\n \"add.f16x2 $0, $1, $2;\",\n \"=r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef habs2(x: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Half2 absolute value - clears sign bits of both fp16 values.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(x).ir_value(loc=loc, ip=ip)],\n \"and.b32 $0, $1, 0x7FFF7FFF;\",\n \"=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef hmax2(a: Uint32, b: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Half2 max - element-wise max of 2 fp16 pairs.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(a).ir_value(loc=loc, ip=ip), Uint32(b).ir_value(loc=loc, ip=ip)],\n \"max.f16x2 $0, $1, $2;\",\n \"=r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef hmax_to_f32(x: Uint32, *, loc=None, ip=None) -> Float32:\n \"\"\"Extract max of 2 fp16 values in half2 as float32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Uint32(x).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 h0, h1;\n .reg .f32 f0, f1;\n mov.b32 {h0, h1}, $1;\n cvt.f32.f16 f0, h0;\n cvt.f32.f16 f1, h1;\n max.f32 $0, f0, f1;\n }\n \"\"\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef half2_to_float2_scaled(\n h2: Uint32, scale: Float32, *, loc=None, ip=None\n) -> Tuple[Float32, Float32]:\n \"\"\"Convert half2 to float2 AND multiply by scale.\"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.f32(), T.f32()]),\n [Uint32(h2).ir_value(loc=loc, ip=ip), Float32(scale).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 h0, h1;\n .reg .f32 f0, f1;\n mov.b32 {h0, h1}, $2;\n cvt.f32.f16 f0, h0;\n cvt.f32.f16 f1, h1;\n mul.f32 $0, f0, $3;\n mul.f32 $1, f1, $3;\n }\n \"\"\",\n \"=f,=f,r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n f0 = llvm.extractvalue(T.f32(), result, [0], loc=loc, ip=ip)\n f1 = llvm.extractvalue(T.f32(), result, [1], loc=loc, ip=ip)\n\n return Float32(f0), Float32(f1)\n\n\n# =============================================================================\n# BFloat2 SIMD Intrinsics\n# =============================================================================\n\n\n@dsl_user_op\ndef bfloat2_mul(a: Uint32, b: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Multiply two BFloat2 values element-wise: (a.x*b.x, a.y*b.y).\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(a).ir_value(loc=loc, ip=ip), Uint32(b).ir_value(loc=loc, ip=ip)],\n \"mul.bf16x2 $0, $1, $2;\",\n \"=r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef bfloat2_add(a: Uint32, b: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Add two BFloat2 values element-wise: (a.x+b.x, a.y+b.y).\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(a).ir_value(loc=loc, ip=ip), Uint32(b).ir_value(loc=loc, ip=ip)],\n \"add.bf16x2 $0, $1, $2;\",\n \"=r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef bfloat2_habs2(x: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"BFloat16x2 absolute value - clears sign bits of both bf16 values.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(x).ir_value(loc=loc, ip=ip)],\n \"and.b32 $0, $1, 0x7FFF7FFF;\",\n \"=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef bfloat2_hmax2(a: Uint32, b: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"BFloat16x2 max - element-wise max of 2 bf16 pairs.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(a).ir_value(loc=loc, ip=ip), Uint32(b).ir_value(loc=loc, ip=ip)],\n \"max.bf16x2 $0, $1, $2;\",\n \"=r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef bfloat2_hmax_to_f32(x: Uint32, *, loc=None, ip=None) -> Float32:\n \"\"\"Extract max of 2 bf16 values in bfloat2 as float32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Uint32(x).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b32 lo, hi;\n .reg .f32 f0, f1;\n and.b32 lo, $1, 0xFFFF;\n shr.b32 hi, $1, 16;\n shl.b32 lo, lo, 16;\n shl.b32 hi, hi, 16;\n mov.b32 f0, lo;\n mov.b32 f1, hi;\n max.f32 $0, f0, f1;\n }\n \"\"\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef bfloat2_to_float2_scaled(\n bf2: Uint32, scale: Float32, *, loc=None, ip=None\n) -> Tuple[Float32, Float32]:\n \"\"\"Convert bfloat16x2 to float2 AND multiply by scale.\"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.f32(), T.f32()]),\n [Uint32(bf2).ir_value(loc=loc, ip=ip), Float32(scale).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b32 lo, hi;\n .reg .f32 f0, f1;\n and.b32 lo, $2, 0xFFFF;\n shr.b32 hi, $2, 16;\n shl.b32 lo, lo, 16;\n shl.b32 hi, hi, 16;\n mov.b32 f0, lo;\n mov.b32 f1, hi;\n mul.f32 $0, f0, $3;\n mul.f32 $1, f1, $3;\n }\n \"\"\",\n \"=f,=f,r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n f0 = llvm.extractvalue(T.f32(), result, [0], loc=loc, ip=ip)\n f1 = llvm.extractvalue(T.f32(), result, [1], loc=loc, ip=ip)\n\n return Float32(f0), Float32(f1)\n\n\n# =============================================================================\n# FP8 E4M3 Intrinsics\n# =============================================================================\n\n\n@dsl_user_op\ndef cvt_f32_to_e4m3(a: Float32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Convert float32 to E4M3 using native cvt.rn.satfinite.e4m3x2.f32.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Float32(a).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 fp8_pair;\n .reg .f32 zero;\n mov.f32 zero, 0f00000000;\n cvt.rn.satfinite.e4m3x2.f32 fp8_pair, zero, $1;\n cvt.u32.u16 $0, fp8_pair;\n }\n \"\"\",\n \"=r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef cvt_e4m3x4_to_f32x4(\n packed: Uint32, *, loc=None, ip=None\n) -> tuple[Float32, Float32, Float32, Float32]:\n \"\"\"Convert 4 packed E4M3 bytes (in a uint32) to 4 float32 values.\n\n Uses e4m3x2 → f16x2 → f32 conversion path (SM89+/PTX ISA 7.8+).\n Input: uint32 containing bytes [b0, b1, b2, b3] (low to high).\n Output: (f0, f1, f2, f3) as Float32.\n \"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.f32(), T.f32(), T.f32(), T.f32()]),\n [Uint32(packed).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 pair_lo, pair_hi;\n .reg .b32 h2_lo, h2_hi;\n .reg .b16 h0, h1, h2, h3;\n mov.b32 {pair_lo, pair_hi}, $4;\n cvt.rn.f16x2.e4m3x2 h2_lo, pair_lo;\n cvt.rn.f16x2.e4m3x2 h2_hi, pair_hi;\n mov.b32 {h0, h1}, h2_lo;\n mov.b32 {h2, h3}, h2_hi;\n cvt.f32.f16 $0, h0;\n cvt.f32.f16 $1, h1;\n cvt.f32.f16 $2, h2;\n cvt.f32.f16 $3, h3;\n }\n \"\"\",\n \"=f,=f,=f,=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n f0 = llvm.extractvalue(T.f32(), result, [0], loc=loc, ip=ip)\n f1 = llvm.extractvalue(T.f32(), result, [1], loc=loc, ip=ip)\n f2 = llvm.extractvalue(T.f32(), result, [2], loc=loc, ip=ip)\n f3 = llvm.extractvalue(T.f32(), result, [3], loc=loc, ip=ip)\n\n return Float32(f0), Float32(f1), Float32(f2), Float32(f3)\n\n\n@dsl_user_op\ndef cvt_f32x2_to_half2(a: Float32, b: Float32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Pack two float32 values into a half2 (uint32 containing two fp16 values).\n\n Uses cvt.rn.f16.f32 for each value, then packs into a single uint32.\n Matches __float22half2_rn() behavior in CUDA.\n \"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [\n Float32(a).ir_value(loc=loc, ip=ip),\n Float32(b).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b16 h0, h1;\n cvt.rn.f16.f32 h0, $1;\n cvt.rn.f16.f32 h1, $2;\n mov.b32 $0, {h0, h1};\n }\n \"\"\",\n \"=r,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef cvt_f32x2_to_bfloat2(a: Float32, b: Float32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Pack two float32 values into the low and high bfloat16 lanes, respectively.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [\n Float32(a).ir_value(loc=loc, ip=ip),\n Float32(b).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b16 h0, h1;\n cvt.rn.bf16.f32 h0, $1;\n cvt.rn.bf16.f32 h1, $2;\n mov.b32 $0, {h0, h1};\n }\n \"\"\",\n \"=r,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef fp8_e4m3_to_f32_and_rcp(fp8_val: Uint32, *, loc=None, ip=None) -> Float32:\n \"\"\"Convert FP8 E4M3 to float32 AND compute reciprocal (0 stays 0).\n\n Uses the hardware conversion instruction, which is exact for every\n finite e4m3 value, including subnormals, and matches how the tensor\n core decodes the same byte.\n \"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Uint32(fp8_val).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .pred p_zero;\n .reg .b16 fp8_pair;\n .reg .b32 h2_32;\n .reg .b16 h_lo, h_hi;\n .reg .f32 fp8_float, result;\n\n cvt.u16.u32 fp8_pair, $1;\n cvt.rn.f16x2.e4m3x2 h2_32, fp8_pair;\n mov.b32 {h_lo, h_hi}, h2_32;\n cvt.f32.f16 fp8_float, h_lo;\n rcp.approx.ftz.f32 result, fp8_float;\n setp.eq.f32 p_zero, fp8_float, 0f00000000;\n selp.f32 $0, 0f00000000, result, p_zero;\n }\n \"\"\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef nvfp4_compute_output_scale(\n fp8_val: Uint32, global_scale: Float32, *, loc=None, ip=None\n) -> Float32:\n \"\"\"Compute NVFP4 output_scale matching the CUDA kernel exactly.\n\n Converts E4M3 scale factor to float via hardware f16x2 path, then computes\n rcp(float_scale * rcp(global_scale)). Returns 0 when scale is zero.\n\n This matches quantization_utils.cuh:\n SFValue = static_cast<float>(tmp);\n outputScale = rcp_approx(SFValue * rcp_approx(SFScaleVal));\n \"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [\n Uint32(fp8_val).ir_value(loc=loc, ip=ip),\n Float32(global_scale).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .pred p_zero;\n .reg .b16 fp8_pair;\n .reg .b32 h2_32;\n .reg .b16 h_lo, h_hi;\n .reg .f32 scale_f32, rcp_gs, product, result;\n\n cvt.u16.u32 fp8_pair, $1;\n cvt.rn.f16x2.e4m3x2 h2_32, fp8_pair;\n mov.b32 {h_lo, h_hi}, h2_32;\n cvt.f32.f16 scale_f32, h_lo;\n\n rcp.approx.ftz.f32 rcp_gs, $2;\n mul.f32 product, scale_f32, rcp_gs;\n rcp.approx.ftz.f32 result, product;\n\n setp.eq.f32 p_zero, scale_f32, 0f00000000;\n selp.f32 $0, 0f00000000, result, p_zero;\n }\n \"\"\",\n \"=f,r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef nvfp4_compute_output_scale_rn(\n fp8_val: Uint32, global_scale: Float32, block_amax: Float32, *, loc=None, ip=None\n) -> Float32:\n \"\"\"Compute TE-exact NVFP4 output scale when FP4 quant fast math is disabled.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [\n Uint32(fp8_val).ir_value(loc=loc, ip=ip),\n Float32(global_scale).ir_value(loc=loc, ip=ip),\n Float32(block_amax).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .pred p_zero;\n .reg .b16 fp8_pair;\n .reg .b32 h2_32;\n .reg .b16 h_lo, h_hi;\n .reg .f32 scale_f32, rcp_gs, product, result, max_f32;\n\n cvt.u16.u32 fp8_pair, $1;\n cvt.rn.f16x2.e4m3x2 h2_32, fp8_pair;\n mov.b32 {h_lo, h_hi}, h2_32;\n cvt.f32.f16 scale_f32, h_lo;\n\n div.rn.f32 rcp_gs, 0f3F800000, $2;\n mul.rn.f32 product, scale_f32, rcp_gs;\n div.rn.f32 result, 0f3F800000, product;\n mov.b32 max_f32, 0x7F7FFFFF;\n min.f32 result, result, max_f32;\n\n setp.eq.f32 p_zero, $3, 0f00000000;\n selp.f32 $0, 0f00000000, result, p_zero;\n }\n \"\"\",\n \"=f,r,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n# =============================================================================\n# UE8M0 Intrinsics (for MXFP4)\n# =============================================================================\n\n\n@dsl_user_op\ndef cvt_f32_to_ue8m0(max_val: Float32, *, loc=None, ip=None) -> Uint32:\n \"\"\"\n Convert float32 max value to UE8M0 scale factor.\n\n UE8M0 is unsigned 8-bit exponent-only format:\n - value = 2^(ue8m0 - 127)\n - ue8m0 = ceil(log2(max_val)) + 127\n\n Uses lg2.approx.f32 for fast log2 approximation.\n Uses cvt.rpi (round towards positive infinity, i.e., ceiling).\n Returns value clamped to [0, 255].\n \"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Float32(max_val).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .pred p_zero, p_neg, p_ovf;\n .reg .f32 log2_val;\n .reg .s32 exp_int, result;\n\n // Check for zero/negative\n setp.le.f32 p_zero, $1, 0f00000000;\n\n // Compute ceil(log2(max_val)) using cvt.rpi (round towards +inf)\n lg2.approx.f32 log2_val, $1;\n cvt.rpi.s32.f32 exp_int, log2_val;\n\n // Add bias and clamp to [0, 255]\n add.s32 result, exp_int, 127;\n setp.lt.s32 p_neg, result, 0;\n setp.gt.s32 p_ovf, result, 255;\n selp.s32 result, 0, result, p_neg;\n selp.s32 result, 255, result, p_ovf;\n selp.s32 $0, 0, result, p_zero;\n }\n \"\"\",\n \"=r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef ue8m0_to_output_scale(ue8m0_val: Uint32, *, loc=None, ip=None) -> Float32:\n \"\"\"\n Convert UE8M0 to output_scale for MXFP4 quantization.\n\n UE8M0 value = 2^(ue8m0 - 127)\n Returns 1 / 2^(ue8m0 - 127) = 2^(127 - ue8m0)\n \"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Uint32(ue8m0_val).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .pred p_zero;\n .reg .s32 neg_exp;\n .reg .f32 neg_exp_f, result;\n\n // Check for zero\n setp.eq.u32 p_zero, $1, 0;\n\n // Compute 2^(127 - ue8m0) = 1 / 2^(ue8m0 - 127)\n sub.s32 neg_exp, 127, $1;\n cvt.rn.f32.s32 neg_exp_f, neg_exp;\n ex2.approx.f32 result, neg_exp_f;\n selp.f32 $0, 0f00000000, result, p_zero;\n }\n \"\"\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef pow2_ceil_ue8m0(\n scale: Float32,\n *,\n loc=None,\n ip=None,\n) -> Tuple[Float32, Uint32]:\n \"\"\"Round a positive FP32 ``scale`` up to a power of two, bit-exactly.\n\n Returns ``(rounded_fp32, ue8m0_byte)`` with ``ue8m0_byte`` the biased\n exponent of the rounded value. Unlike ``cvt_f32_to_ue8m0``, this matches\n the fp8_quant.cuh and scale_convert.cuh fp32_to_ue8m0 references\n bit-for-bit.\n \"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.f32(), T.i32()]),\n [Float32(scale).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .pred p_mant;\n .reg .b32 bits, mant;\n\n // bits = __float_as_uint(scale)\n mov.b32 bits, $2;\n // mant = bits & 0x007FFFFF (mantissa field)\n and.b32 mant, bits, 8388607;\n setp.ne.u32 p_mant, mant, 0;\n // if (mant) bits = (bits + 0x00800000) & 0x7F800000\n @p_mant add.u32 bits, bits, 8388608;\n @p_mant and.b32 bits, bits, 2139095040;\n // rounded fp32 scale = __uint_as_float(bits)\n mov.b32 $0, bits;\n // ue8m0 = (bits >> 23) & 0xFF\n bfe.u32 $1, bits, 23, 8;\n }\n \"\"\",\n \"=f,=r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n rounded = llvm.extractvalue(T.f32(), result, [0], loc=loc, ip=ip)\n ue8m0 = llvm.extractvalue(T.i32(), result, [1], loc=loc, ip=ip)\n return Float32(rounded), Uint32(ue8m0)\n\n\n@dsl_user_op\ndef cvt_e8m0_to_f32(e8m0_val: Uint32, *, loc=None, ip=None) -> Float32:\n \"\"\"Convert a single E8M0 scale byte to its true f32 value 2**(byte-127).\n\n Byte 0 maps to 0.0.\n \"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Uint32(e8m0_val).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .pred p0;\n .reg .u32 b0;\n .reg .s32 e0;\n .reg .f32 ef0;\n and.b32 b0, $1, 0x000000ff;\n setp.eq.u32 p0, b0, 0;\n cvt.s32.u32 e0, b0;\n sub.s32 e0, e0, 127;\n cvt.rn.f32.s32 ef0, e0;\n ex2.approx.f32 $0, ef0;\n selp.f32 $0, 0f00000000, $0, p0;\n }\n \"\"\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef cvt_e8m0x4_to_f32x4(\n packed: Uint32, *, loc=None, ip=None\n) -> Tuple[Float32, Float32, Float32, Float32]:\n \"\"\"Decode 4 E8M0 scale bytes (packed u32) to 4 x true f32 (2**(byte-127)).\"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.f32(), T.f32(), T.f32(), T.f32()]),\n [Uint32(packed).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .pred p0, p1, p2, p3;\n .reg .u32 b0, b1, b2, b3;\n .reg .s32 e0, e1, e2, e3;\n .reg .f32 ef0, ef1, ef2, ef3;\n and.b32 b0, $4, 0x000000ff;\n shr.u32 b1, $4, 8;\n and.b32 b1, b1, 0x000000ff;\n shr.u32 b2, $4, 16;\n and.b32 b2, b2, 0x000000ff;\n shr.u32 b3, $4, 24;\n setp.eq.u32 p0, b0, 0;\n setp.eq.u32 p1, b1, 0;\n setp.eq.u32 p2, b2, 0;\n setp.eq.u32 p3, b3, 0;\n cvt.s32.u32 e0, b0;\n cvt.s32.u32 e1, b1;\n cvt.s32.u32 e2, b2;\n cvt.s32.u32 e3, b3;\n sub.s32 e0, e0, 127;\n sub.s32 e1, e1, 127;\n sub.s32 e2, e2, 127;\n sub.s32 e3, e3, 127;\n cvt.rn.f32.s32 ef0, e0;\n cvt.rn.f32.s32 ef1, e1;\n cvt.rn.f32.s32 ef2, e2;\n cvt.rn.f32.s32 ef3, e3;\n ex2.approx.f32 $0, ef0;\n ex2.approx.f32 $1, ef1;\n ex2.approx.f32 $2, ef2;\n ex2.approx.f32 $3, ef3;\n selp.f32 $0, 0f00000000, $0, p0;\n selp.f32 $1, 0f00000000, $1, p1;\n selp.f32 $2, 0f00000000, $2, p2;\n selp.f32 $3, 0f00000000, $3, p3;\n }\n \"\"\",\n \"=f,=f,=f,=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n return (\n Float32(llvm.extractvalue(T.f32(), result, [0], loc=loc, ip=ip)),\n Float32(llvm.extractvalue(T.f32(), result, [1], loc=loc, ip=ip)),\n Float32(llvm.extractvalue(T.f32(), result, [2], loc=loc, ip=ip)),\n Float32(llvm.extractvalue(T.f32(), result, [3], loc=loc, ip=ip)),\n )\n\n\n# =============================================================================\n# E2M1 Conversion\n# =============================================================================\n\n\n@dsl_user_op\ndef cvt_e2m1x8_f32(\n v0: Float32,\n v1: Float32,\n v2: Float32,\n v3: Float32,\n v4: Float32,\n v5: Float32,\n v6: Float32,\n v7: Float32,\n *,\n loc=None,\n ip=None,\n) -> Uint32:\n \"\"\"Convert eight float32 values to eight E2M1 (4-bit) values packed into uint32.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [\n Float32(v0).ir_value(loc=loc, ip=ip),\n Float32(v1).ir_value(loc=loc, ip=ip),\n Float32(v2).ir_value(loc=loc, ip=ip),\n Float32(v3).ir_value(loc=loc, ip=ip),\n Float32(v4).ir_value(loc=loc, ip=ip),\n Float32(v5).ir_value(loc=loc, ip=ip),\n Float32(v6).ir_value(loc=loc, ip=ip),\n Float32(v7).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b8 byte0, byte1, byte2, byte3;\n cvt.rn.satfinite.e2m1x2.f32 byte0, $2, $1;\n cvt.rn.satfinite.e2m1x2.f32 byte1, $4, $3;\n cvt.rn.satfinite.e2m1x2.f32 byte2, $6, $5;\n cvt.rn.satfinite.e2m1x2.f32 byte3, $8, $7;\n mov.b32 $0, {byte0, byte1, byte2, byte3};\n }\n \"\"\",\n \"=r,f,f,f,f,f,f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n# =============================================================================\n# Warp, Block, and Cluster Reduction Utilities\n# =============================================================================\n\n\n@cute.jit\ndef warp_reduce(val, op, width: cutlass.Constexpr[int] = 32):\n \"\"\"Reduce across threads in a warp using butterfly shuffle.\"\"\"\n if cutlass.const_expr(isinstance(val, cute.TensorSSA)):\n res = cute.make_rmem_tensor(val.shape, val.dtype)\n res.store(val)\n for i in cutlass.range_constexpr(cute.size(val.shape)):\n res[i] = warp_reduce(res[i], op, width)\n return res.load()\n else:\n for i in cutlass.range_constexpr(int(math.log2(width))):\n val = op(val, cute.arch.shuffle_sync_bfly(val, offset=1 << i))\n return val\n\n\n@cute.jit\ndef block_reduce(\n val: Float32,\n op: Callable,\n reduction_buffer: cute.Tensor,\n init_val: Float32,\n) -> Float32:\n \"\"\"Block reduction across multiple warps using shared memory.\"\"\"\n lane_idx = cute.arch.lane_idx()\n warp_idx = cute.arch.warp_idx()\n warps_per_row = cute.size(reduction_buffer.shape[1])\n row_idx = warp_idx // warps_per_row\n col_idx = warp_idx % warps_per_row\n\n if lane_idx == 0:\n reduction_buffer[row_idx, col_idx] = val\n cute.arch.barrier()\n\n block_reduce_val = init_val\n if lane_idx < warps_per_row:\n block_reduce_val = reduction_buffer[row_idx, lane_idx]\n return warp_reduce(block_reduce_val, op)\n\n\n@cute.jit\ndef cluster_reduce(\n val: Float32,\n op: Callable,\n reduction_buffer: cute.Tensor,\n mbar_ptr: cute.Pointer,\n cluster_n: cutlass.Constexpr[int],\n init_val: Float32,\n) -> Float32:\n \"\"\"Cluster reduction across multiple CTAs using mbarrier.\"\"\"\n cta_rank_in_cluster = cute.arch.block_idx_in_cluster()\n lane_idx = cute.arch.lane_idx()\n warp_idx = cute.arch.warp_idx()\n\n rows_per_block = reduction_buffer.shape[0]\n warps_per_row = reduction_buffer.shape[1][0]\n\n row_idx = warp_idx // warps_per_row\n col_idx = warp_idx % warps_per_row\n\n # Warp 0 sets up mbarrier transaction count\n if warp_idx == 0:\n with cute.arch.elect_one():\n num_warps = rows_per_block * warps_per_row\n expected_bytes = num_warps * cluster_n * 4\n cute.arch.mbarrier_arrive_and_expect_tx(mbar_ptr, expected_bytes)\n\n # Each lane < cluster_n writes to a different CTA's shared memory\n if lane_idx < cluster_n:\n store_shared_remote(\n val,\n elem_pointer(reduction_buffer, (row_idx, (col_idx, cta_rank_in_cluster))),\n mbar_ptr,\n peer_cta_rank_in_cluster=lane_idx,\n )\n\n # Wait for all cluster writes\n cute.arch.mbarrier_wait(mbar_ptr, phase=0)\n\n # Reduce across all values\n num_total = warps_per_row * cluster_n\n num_iter = cute.ceil_div(num_total, 32)\n\n block_reduce_val = init_val\n for i in cutlass.range_constexpr(num_iter):\n idx = lane_idx + i * 32\n if idx < num_total:\n block_reduce_val = op(block_reduce_val, reduction_buffer[row_idx, idx])\n\n return warp_reduce(block_reduce_val, op)\n\n\n@cute.jit\ndef row_reduce(\n x: cute.TensorSSA,\n op: cute.ReductionOp,\n threads_per_row: cutlass.Constexpr[int],\n reduction_buffer: cute.Tensor,\n mbar_ptr,\n cluster_n: cutlass.Constexpr[int],\n init_val: Float32,\n):\n \"\"\"Row reduction with optional cluster support.\"\"\"\n local_val = x.reduce(op, init_val=init_val, reduction_profile=0)\n\n warp_op = {\n cute.ReductionOp.ADD: operator.add,\n cute.ReductionOp.MAX: cute.arch.fmax,\n }[op]\n warp_width = min(threads_per_row, 32)\n warp_val = warp_reduce(local_val, warp_op, width=warp_width)\n\n warps_per_row = max(threads_per_row // 32, 1)\n\n if cutlass.const_expr(warps_per_row > 1 or cluster_n > 1):\n if cutlass.const_expr(cluster_n == 1):\n return block_reduce(warp_val, warp_op, reduction_buffer, init_val)\n else:\n return cluster_reduce(\n warp_val, warp_op, reduction_buffer, mbar_ptr, cluster_n, init_val\n )\n else:\n return warp_val\n\n\n# =============================================================================\n# Predicate Utility\n# =============================================================================\n\n\n@cute.jit\ndef predicate_k(tXcX: cute.Tensor, limit: int) -> cute.Tensor:\n \"\"\"Create predicate tensor for bounds checking.\"\"\"\n tXpX = cute.make_rmem_tensor(\n cute.make_layout(\n (\n cute.size(tXcX, mode=[0, 1]),\n cute.size(tXcX, mode=[1]),\n cute.size(tXcX, mode=[2]),\n ),\n stride=(cute.size(tXcX, mode=[2]), 0, 1),\n ),\n cutlass.Boolean,\n )\n for rest_v in cutlass.range_constexpr(tXpX.shape[0]):\n for rest_k in cutlass.range_constexpr(tXpX.shape[2]):\n tXpX[rest_v, 0, rest_k] = cute.elem_less(\n tXcX[(0, rest_v), 0, rest_k][1], limit\n )\n return tXpX\n\n\n# =============================================================================\n# Helper Functions for SF Block Processing (block_size=16)\n# =============================================================================\n\n\n@cute.jit\ndef load_8_half2(\n mX: cute.Tensor, mW: cute.Tensor, row_offset: Int32, col_offset: Int32, H: int\n):\n \"\"\"Load 16 elements (8 half2 pairs) of X and W from global memory.\n\n Returns:\n x_h2: rmem_tensor of shape (8,) containing X as half2\n w_h2: rmem_tensor of shape (8,) containing W as half2\n \"\"\"\n x_h2 = cute.make_rmem_tensor((8,), Uint32)\n w_h2 = cute.make_rmem_tensor((8,), Uint32)\n\n # Load X (2 x 128-bit loads = 16 elements)\n x_ptr0 = get_ptr_as_int64(mX, row_offset * H + col_offset)\n x_ptr1 = get_ptr_as_int64(mX, row_offset * H + col_offset + Int32(8))\n x_h2[0], x_h2[1], x_h2[2], x_h2[3] = ld_global_v4_u32(x_ptr0)\n x_h2[4], x_h2[5], x_h2[6], x_h2[7] = ld_global_v4_u32(x_ptr1)\n\n # Load W (2 x 128-bit loads = 16 elements)\n w_ptr0 = get_ptr_as_int64(mW, col_offset)\n w_ptr1 = get_ptr_as_int64(mW, col_offset + Int32(8))\n w_h2[0], w_h2[1], w_h2[2], w_h2[3] = ld_global_v4_u32(w_ptr0)\n w_h2[4], w_h2[5], w_h2[6], w_h2[7] = ld_global_v4_u32(w_ptr1)\n\n return x_h2, w_h2\n\n\n@cute.jit\ndef half2_mul_8(x_h2: cute.Tensor, w_h2: cute.Tensor) -> cute.Tensor:\n \"\"\"Multiply 8 half2 pairs element-wise.\"\"\"\n xw_h2 = cute.make_rmem_tensor((8,), Uint32)\n for i in cutlass.range_constexpr(8):\n xw_h2[i] = half2_mul(x_h2[i], w_h2[i])\n return xw_h2\n\n\n@cute.jit\ndef bfloat2_mul_8(x_h2: cute.Tensor, w_h2: cute.Tensor) -> cute.Tensor:\n \"\"\"Multiply 8 bfloat2 pairs element-wise.\"\"\"\n xw_h2 = cute.make_rmem_tensor((8,), Uint32)\n for i in cutlass.range_constexpr(8):\n xw_h2[i] = bfloat2_mul(x_h2[i], w_h2[i])\n return xw_h2\n\n\n@cute.jit\ndef half2_max_abs_8(xw_h2: cute.Tensor) -> Uint32:\n \"\"\"Compute max absolute value across 8 half2 values using tree reduction.\"\"\"\n # Compute abs for all 8 values\n abs_h2 = cute.make_rmem_tensor((8,), Uint32)\n for i in cutlass.range_constexpr(8):\n abs_h2[i] = habs2(xw_h2[i])\n\n # Tree reduction: 8 -> 4 -> 2 -> 1\n max_01 = hmax2(abs_h2[0], abs_h2[1])\n max_23 = hmax2(abs_h2[2], abs_h2[3])\n max_45 = hmax2(abs_h2[4], abs_h2[5])\n max_67 = hmax2(abs_h2[6], abs_h2[7])\n max_0123 = hmax2(max_01, max_23)\n max_4567 = hmax2(max_45, max_67)\n return hmax2(max_0123, max_4567)\n\n\n@cute.jit\ndef bfloat2_max_abs_8(xw_h2: cute.Tensor) -> Uint32:\n \"\"\"Compute max absolute value across 8 bfloat2 values using tree reduction.\"\"\"\n # Compute abs for all 8 values\n abs_h2 = cute.make_rmem_tensor((8,), Uint32)\n for i in cutlass.range_constexpr(8):\n abs_h2[i] = bfloat2_habs2(xw_h2[i])\n\n # Tree reduction: 8 -> 4 -> 2 -> 1\n max_01 = bfloat2_hmax2(abs_h2[0], abs_h2[1])\n max_23 = bfloat2_hmax2(abs_h2[2], abs_h2[3])\n max_45 = bfloat2_hmax2(abs_h2[4], abs_h2[5])\n max_67 = bfloat2_hmax2(abs_h2[6], abs_h2[7])\n max_0123 = bfloat2_hmax2(max_01, max_23)\n max_4567 = bfloat2_hmax2(max_45, max_67)\n return bfloat2_hmax2(max_0123, max_4567)\n\n\n@cute.jit\ndef half2_to_float16(xw_h2: cute.Tensor, scale: Float32) -> cute.Tensor:\n \"\"\"Convert 8 half2 to 16 float32 with scaling.\"\"\"\n y_f32 = cute.make_rmem_tensor((16,), Float32)\n for i in cutlass.range_constexpr(8):\n y_f32[i * 2], y_f32[i * 2 + 1] = half2_to_float2_scaled(xw_h2[i], scale)\n return y_f32\n\n\n@cute.jit\ndef bfloat2_to_float16(xw_h2: cute.Tensor, scale: Float32) -> cute.Tensor:\n \"\"\"Convert 8 bfloat2 to 16 float32 with scaling.\"\"\"\n y_f32 = cute.make_rmem_tensor((16,), Float32)\n for i in cutlass.range_constexpr(8):\n y_f32[i * 2], y_f32[i * 2 + 1] = bfloat2_to_float2_scaled(xw_h2[i], scale)\n return y_f32\n\n\n@cute.jit\ndef quantize_and_pack_16(y_f32: cute.Tensor, inv_scale: Float32) -> Uint64:\n \"\"\"Quantize 16 float32 values to FP4 and pack into uint64.\"\"\"\n # Scale values\n q = cute.make_rmem_tensor((16,), Float32)\n for i in cutlass.range_constexpr(16):\n q[i] = y_f32[i] * inv_scale\n\n # Convert to E2M1 and pack\n packed_lo = cvt_e2m1x8_f32(q[0], q[1], q[2], q[3], q[4], q[5], q[6], q[7])\n packed_hi = cvt_e2m1x8_f32(q[8], q[9], q[10], q[11], q[12], q[13], q[14], q[15])\n return (Uint64(packed_hi) << Uint64(32)) | Uint64(packed_lo)\n\n\n# =============================================================================\n# Helper Functions for Float32 SF Block Processing\n# =============================================================================\n\n\n@cute.jit\ndef load_f32_16_from_smem(\n sH: cute.Tensor, row_idx: Int32, col_offset: Int32\n) -> cute.Tensor:\n \"\"\"Load 16 Float32 values from shared memory.\"\"\"\n h_f32 = cute.make_rmem_tensor((16,), Float32)\n for i in cutlass.range_constexpr(16):\n h_f32[i] = Float32(sH[row_idx, col_offset + i])\n return h_f32\n\n\n@cute.jit\ndef compute_y_and_max_abs_f32(\n h_f32: cute.Tensor, w_f32: cute.Tensor, rstd: Float32\n) -> Tuple[cute.Tensor, Float32]:\n \"\"\"Compute y = h * rstd * w and max_abs for 16 Float32 values.\"\"\"\n y_f32 = cute.make_rmem_tensor((16,), Float32)\n\n # Compute y and track max_abs\n y_f32[0] = h_f32[0] * rstd * w_f32[0]\n max_abs = fabs_f32(y_f32[0])\n\n for i in cutlass.range_constexpr(1, 16):\n y_f32[i] = h_f32[i] * rstd * w_f32[i]\n max_abs = fmax_f32(max_abs, fabs_f32(y_f32[i]))\n\n return y_f32, max_abs\n\n\n# =============================================================================\n# PTX intrinsics used by SM120 MoE kernels\n# =============================================================================\n\n\n@dsl_user_op\ndef st_global_f32(base_ptr: Int64, value: Float32, *, loc=None, ip=None):\n \"\"\"Store 32-bit float to global memory.\"\"\"\n llvm.inline_asm(\n None,\n [\n Int64(base_ptr).ir_value(loc=loc, ip=ip),\n Float32(value).ir_value(loc=loc, ip=ip),\n ],\n \"st.global.f32 [$0], $1;\",\n \"l,f\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n\n\n@dsl_user_op\ndef st_global_i32(addr: Int64, val: Int32, *, loc=None, ip=None):\n \"\"\"Store int32 to global memory.\"\"\"\n llvm.inline_asm(\n None,\n [\n Int64(addr).ir_value(loc=loc, ip=ip),\n Int32(val).ir_value(loc=loc, ip=ip),\n ],\n \"st.global.s32 [$0], $1;\",\n \"l,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n\n\n@dsl_user_op\ndef st_global_v4_u32(\n base_ptr: Int64,\n v0: Uint32,\n v1: Uint32,\n v2: Uint32,\n v3: Uint32,\n *,\n loc=None,\n ip=None,\n):\n \"\"\"Store 128 bits to global memory as four uint32 words.\"\"\"\n llvm.inline_asm(\n None,\n [\n Int64(base_ptr).ir_value(loc=loc, ip=ip),\n Uint32(v0).ir_value(loc=loc, ip=ip),\n Uint32(v1).ir_value(loc=loc, ip=ip),\n Uint32(v2).ir_value(loc=loc, ip=ip),\n Uint32(v3).ir_value(loc=loc, ip=ip),\n ],\n \"st.global.v4.u32 [$0], {$1, $2, $3, $4};\",\n \"l,r,r,r,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n\n# =============================================================================\n# PTX Intrinsics — Shared Memory Operations\n# =============================================================================\n\n\n@dsl_user_op\ndef shared_ptr_to_u32(ptr: cute.Pointer, *, loc=None, ip=None) -> Int32:\n \"\"\"Convert an address-space-3 shared-memory pointer to a u32 address.\"\"\"\n return Int32(llvm.ptrtoint(T.i32(), ptr.llvm_ptr, loc=loc, ip=ip))\n\n\n@dsl_user_op\ndef ld_shared_i32_relaxed(addr: Int32, *, loc=None, ip=None) -> Int32:\n \"\"\"Load int32 from shared memory when CSE/reordering is acceptable.\"\"\"\n return Int32(\n llvm.inline_asm(\n T.i32(),\n [Int32(addr).ir_value(loc=loc, ip=ip)],\n \"ld.shared.s32 $0, [$1];\",\n \"=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef st_shared_i32(addr: Int32, val: Int32, *, loc=None, ip=None):\n \"\"\"Store int32 to shared memory at a 32-bit byte address.\"\"\"\n llvm.inline_asm(\n None,\n [\n Int32(addr).ir_value(loc=loc, ip=ip),\n Int32(val).ir_value(loc=loc, ip=ip),\n ],\n \"st.shared.s32 [$0], $1;\",\n \"r,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n\n@dsl_user_op\ndef ld_shared_f32(addr: Int32, *, loc=None, ip=None) -> Float32:\n \"\"\"Load float32 from shared memory at a 32-bit byte address.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Int32(addr).ir_value(loc=loc, ip=ip)],\n \"ld.shared.f32 $0, [$1];\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef st_shared_f32(addr: Int32, val: Float32, *, loc=None, ip=None):\n \"\"\"Store float32 to shared memory at a 32-bit byte address.\"\"\"\n llvm.inline_asm(\n None,\n [\n Int32(addr).ir_value(loc=loc, ip=ip),\n Float32(val).ir_value(loc=loc, ip=ip),\n ],\n \"st.shared.f32 [$0], $1;\",\n \"r,f\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n\n@dsl_user_op\ndef st_shared_u8(smem_addr: Int32, value: Uint8, *, loc=None, ip=None):\n \"\"\"Store 8 bits to shared memory. smem_addr is a u32 shared-memory address.\"\"\"\n llvm.inline_asm(\n None,\n [\n Int32(smem_addr).ir_value(loc=loc, ip=ip),\n Uint8(value).ir_value(loc=loc, ip=ip),\n ],\n \"st.shared.u8 [$0], $1;\",\n \"r,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n\n\n# =============================================================================\n# PTX Intrinsics — Global Atomics\n# =============================================================================\n\n\n@dsl_user_op\ndef atomic_add_global_i32(addr: Int64, val: Int32, *, loc=None, ip=None) -> Int32:\n \"\"\"Global memory int32 atomic add. Returns old value.\"\"\"\n return Int32(\n llvm.inline_asm(\n T.i32(),\n [\n Int64(addr).ir_value(loc=loc, ip=ip),\n Int32(val).ir_value(loc=loc, ip=ip),\n ],\n \"atom.global.add.s32 $0, [$1], $2;\",\n \"=r,l,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef atomic_cas_global_i32(\n addr: Int64, compare: Int32, value: Int32, *, loc=None, ip=None\n) -> Int32:\n \"\"\"Global memory int32 atomic compare-and-swap. Returns old value.\"\"\"\n return Int32(\n llvm.inline_asm(\n T.i32(),\n [\n Int64(addr).ir_value(loc=loc, ip=ip),\n Int32(compare).ir_value(loc=loc, ip=ip),\n Int32(value).ir_value(loc=loc, ip=ip),\n ],\n \"atom.global.cas.b32 $0, [$1], $2, $3;\",\n \"=r,l,r,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef ld_global_acquire_i32(addr: Int64, *, loc=None, ip=None) -> Int32:\n \"\"\"Load int32 from global memory with acquire semantics.\"\"\"\n return Int32(\n llvm.inline_asm(\n T.i32(),\n [Int64(addr).ir_value(loc=loc, ip=ip)],\n \"ld.global.acquire.gpu.s32 $0, [$1];\",\n \"=r,l\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef st_global_release_i32(addr: Int64, val: Int32, *, loc=None, ip=None):\n \"\"\"Store int32 to global memory with release semantics.\"\"\"\n llvm.inline_asm(\n None,\n [\n Int64(addr).ir_value(loc=loc, ip=ip),\n Int32(val).ir_value(loc=loc, ip=ip),\n ],\n \"st.global.release.gpu.s32 [$0], $1;\",\n \"l,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n\n@dsl_user_op\ndef spin_wait_global_eq_i32(addr: Int64, expected: Int32, *, loc=None, ip=None):\n \"\"\"Spin while *addr == expected, then continue with acquire semantics.\"\"\"\n llvm.inline_asm(\n None,\n [\n Int64(addr).ir_value(loc=loc, ip=ip),\n Int32(expected).ir_value(loc=loc, ip=ip),\n ],\n \"{\\n\"\n \".reg .pred %p0;\\n\"\n \".reg .s32 %val;\\n\"\n \"spin_loop:\\n\"\n \" ld.global.acquire.gpu.s32 %val, [$0];\\n\"\n \" setp.eq.s32 %p0, %val, $1;\\n\"\n \" @%p0 bra spin_loop;\\n\"\n \"}\",\n \"l,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n\n@dsl_user_op\ndef threadfence(*, loc=None, ip=None):\n \"\"\"Emit a global-memory fence.\"\"\"\n llvm.inline_asm(\n None,\n [],\n \"membar.gl;\",\n \"\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n\n# =============================================================================\n# PTX Intrinsics — Scatter Atomics (BF16)\n# =============================================================================\n\n\n@dsl_user_op\ndef scatter_add_bf16x2(addr: Int64, val0_f32, val1_f32, *, loc=None, ip=None):\n \"\"\"BF16x2 atomic reduction add to global memory.\n\n Packs two f32 values into bf16x2 via cvt.rn.satfinite, then does\n red.relaxed.gpu.global.add.noftz.bf16x2.\n \"\"\"\n llvm.inline_asm(\n None,\n [\n Int64(addr).ir_value(loc=loc, ip=ip),\n val0_f32.ir_value(loc=loc, ip=ip),\n val1_f32.ir_value(loc=loc, ip=ip),\n ],\n \"{ .reg .b32 packed;\"\n \" cvt.rn.satfinite.bf16x2.f32 packed, $2, $1;\"\n \" red.relaxed.gpu.global.add.noftz.bf16x2 [$0], packed; }\",\n \"l,f,f\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n\n\n@dsl_user_op\ndef scatter_add_v4_bf16x2(\n addr: Int64, v0, v1, v2, v3, v4, v5, v6, v7, *, loc=None, ip=None\n):\n \"\"\"Vectorized BF16x2 atomic reduction of 8 f32 values.\"\"\"\n llvm.inline_asm(\n None,\n [\n Int64(addr).ir_value(loc=loc, ip=ip),\n v0.ir_value(loc=loc, ip=ip),\n v1.ir_value(loc=loc, ip=ip),\n v2.ir_value(loc=loc, ip=ip),\n v3.ir_value(loc=loc, ip=ip),\n v4.ir_value(loc=loc, ip=ip),\n v5.ir_value(loc=loc, ip=ip),\n v6.ir_value(loc=loc, ip=ip),\n v7.ir_value(loc=loc, ip=ip),\n ],\n \"{ .reg .b32 p0,p1,p2,p3;\"\n \" cvt.rn.satfinite.bf16x2.f32 p0, $2, $1;\"\n \" cvt.rn.satfinite.bf16x2.f32 p1, $4, $3;\"\n \" cvt.rn.satfinite.bf16x2.f32 p2, $6, $5;\"\n \" cvt.rn.satfinite.bf16x2.f32 p3, $8, $7;\"\n \" red.global.add.noftz.v4.bf16x2 [$0], {p0, p1, p2, p3}; }\",\n \"l,f,f,f,f,f,f,f,f\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n\n# =============================================================================\n# FP8 Conversion — Non-reciprocal version\n# =============================================================================\n\n\n@dsl_user_op\ndef fp8_e4m3_to_f32(fp8_val: Uint32, *, loc=None, ip=None) -> Float32:\n \"\"\"Convert FP8 E4M3 to float32.\n\n Uses the hardware conversion instruction, which is exact for every\n finite e4m3 value, including subnormals, and matches how the tensor\n core decodes the same byte.\n \"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Uint32(fp8_val).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 fp8_pair;\n .reg .b32 h2_32;\n .reg .b16 h_lo, h_hi;\n\n cvt.u16.u32 fp8_pair, $1;\n cvt.rn.f16x2.e4m3x2 h2_32, fp8_pair;\n mov.b32 {h_lo, h_hi}, h2_32;\n cvt.f32.f16 $0, h_lo;\n }\n \"\"\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef nvfp4_scale_from_amax(\n block_amax: Float32, global_scale: Float32, *, loc=None, ip=None\n) -> Float32:\n \"\"\"Compute the NVFP4 block scale from an amax and global scale.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [\n Float32(block_amax).ir_value(loc=loc, ip=ip),\n Float32(global_scale).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .f64 amax_d, gs_d, q_d, six_d;\n cvt.f64.f32 amax_d, $1;\n cvt.f64.f32 gs_d, $2;\n mov.f64 six_d, 0d4018000000000000;\n mul.rn.f64 q_d, amax_d, gs_d;\n div.rn.f64 q_d, q_d, six_d;\n cvt.rn.f32.f64 $0, q_d;\n }\n \"\"\",\n \"=f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef nvfp4_scale_from_amax_rn(\n block_amax: Float32, global_scale: Float32, *, loc=None, ip=None\n) -> Float32:\n \"\"\"Compute NVFP4 block scale with round-to-nearest FP32 operations.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [\n Float32(block_amax).ir_value(loc=loc, ip=ip),\n Float32(global_scale).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .pred p_zero;\n .reg .f32 scale_mul, result;\n setp.eq.f32 p_zero, $1, 0f00000000;\n mul.rn.f32 scale_mul, $2, 0f3E2AAAAB;\n mul.rn.f32 result, $1, scale_mul;\n selp.f32 $0, 0f00000000, result, p_zero;\n }\n \"\"\",\n \"=f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef cvt_e4m3x2_to_f16x2_pair(\n packed_u32: Uint32, *, loc=None, ip=None\n) -> Tuple[Uint32, Uint32]:\n \"\"\"Decode 4 packed E4M3 bytes into two f16x2 registers.\"\"\"\n res = llvm.inline_asm(\n ir.Type.parse(\"!llvm.struct<(i32, i32)>\"),\n [Uint32(packed_u32).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 b16_01, b16_23;\n .reg .b32 hi32;\n cvt.u16.u32 b16_01, $2;\n shr.b32 hi32, $2, 16;\n cvt.u16.u32 b16_23, hi32;\n cvt.rn.f16x2.e4m3x2 $0, b16_01;\n cvt.rn.f16x2.e4m3x2 $1, b16_23;\n }\n \"\"\",\n \"=r,=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n return (\n Uint32(llvm.extractvalue(T.i32(), res, [0], loc=loc, ip=ip)),\n Uint32(llvm.extractvalue(T.i32(), res, [1], loc=loc, ip=ip)),\n )\n\n\n@dsl_user_op\ndef f16x2_to_f32x2(packed_h2: Uint32, *, loc=None, ip=None) -> Tuple[Float32, Float32]:\n \"\"\"Unpack one f16x2 register into two f32 values.\"\"\"\n res = llvm.inline_asm(\n ir.Type.parse(\"!llvm.struct<(f32, f32)>\"),\n [Uint32(packed_h2).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 lo, hi;\n mov.b32 {lo, hi}, $2;\n cvt.f32.f16 $0, lo;\n cvt.f32.f16 $1, hi;\n }\n \"\"\",\n \"=f,=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n return (\n Float32(llvm.extractvalue(T.f32(), res, [0], loc=loc, ip=ip)),\n Float32(llvm.extractvalue(T.f32(), res, [1], loc=loc, ip=ip)),\n )\n\n\n@dsl_user_op\ndef cvt_e4m3_to_f32_via_f16(fp8_val: Uint32, *, loc=None, ip=None) -> Float32:\n \"\"\"Convert one E4M3 byte to f32 through native E4M3-to-f16 conversion.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Uint32(fp8_val).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 fp8_pair;\n .reg .b32 h2;\n .reg .b16 lo, hi;\n cvt.u16.u32 fp8_pair, $1;\n cvt.rn.f16x2.e4m3x2 h2, fp8_pair;\n mov.b32 {lo, hi}, h2;\n cvt.f32.f16 $0, lo;\n }\n \"\"\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef cvt_w4a16_packed_e4m3_scale_to_f32(\n packed_byte: Uint32, *, loc=None, ip=None\n) -> Float32:\n \"\"\"Scalar mirror of packed_dequant_e4m3x4_to_bfloat2x2 for W4A16 scales.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Uint32(packed_byte).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b32 bits, tmp;\n .reg .b16 bf;\n and.b32 bits, $1, 0x80;\n shl.b32 bits, bits, 7;\n and.b32 tmp, $1, 0x7f;\n shl.b32 tmp, tmp, 4;\n or.b32 bits, bits, tmp;\n cvt.u16.u32 bf, bits;\n cvt.f32.bf16 $0, bf;\n }\n \"\"\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef cvt_s0e5m3_to_f16x2_broadcast(fp8_val: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Convert one S0E5M3 scale byte to an f16x2 with the scale in both lanes.\n\n S0E5M3 (sign-0, 5-exp, 3-mantissa) is a host-side reformat of the per-block\n E4M3 scale, rebiased to fp16's bias (exp 7->15, i.e. byte += 0x40) so the\n bits line up with fp16 directly: ``f16(byte) = byte << 7`` (exp -> bits 14-10,\n the 3 mantissa bits -> bits 9-7, low mantissa and sign = 0). Broadcasting to\n both f16x2 lanes is then ``byte * 0x00800080`` = ``(byte<<7) | (byte<<23)`` --\n a single ``mul.lo.u32`` (the two shifted copies never overlap, so the mul is\n exactly the OR). Replaces the 3-op E4M3 path (cvt.u16 + cvt.f16x2.e4m3x2 +\n prmt) with 1 op, and the per-block scale stays 1 byte (memory-neutral).\n Numerically exact for normal E4M3 scales (both formats carry 3 mantissa bits).\n \"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(fp8_val).ir_value(loc=loc, ip=ip)],\n \"mul.lo.u32 $0, $1, 0x00800080;\",\n \"=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef fp4_decode_4bytes(\n packed_u32: Uint32, *, loc=None, ip=None\n) -> Tuple[Uint32, Uint32, Uint32, Uint32]:\n \"\"\"Decode 4 packed FP4 bytes into four f16x2 registers.\"\"\"\n res = llvm.inline_asm(\n ir.Type.parse(\"!llvm.struct<(i32, i32, i32, i32)>\"),\n [Uint32(packed_u32).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b8 byte0, byte1, byte2, byte3;\n mov.b32 {byte0, byte1, byte2, byte3}, $4;\n cvt.rn.f16x2.e2m1x2 $0, byte0;\n cvt.rn.f16x2.e2m1x2 $1, byte1;\n cvt.rn.f16x2.e2m1x2 $2, byte2;\n cvt.rn.f16x2.e2m1x2 $3, byte3;\n }\n \"\"\",\n \"=r,=r,=r,=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n return (\n Uint32(llvm.extractvalue(T.i32(), res, [0], loc=loc, ip=ip)),\n Uint32(llvm.extractvalue(T.i32(), res, [1], loc=loc, ip=ip)),\n Uint32(llvm.extractvalue(T.i32(), res, [2], loc=loc, ip=ip)),\n Uint32(llvm.extractvalue(T.i32(), res, [3], loc=loc, ip=ip)),\n )\n\n\n@dsl_user_op\ndef fp4_decode_2(byte_val: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Decode one FP4 byte into one f16x2 register.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(byte_val).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b8 b0;\n cvt.u8.u32 b0, $1;\n cvt.rn.f16x2.e2m1x2 $0, b0;\n }\n \"\"\",\n \"=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef cvt_fp32x2_to_e2m1x2(v0: Float32, v1: Float32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Convert two f32 values into one packed E2M1 byte.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [\n Float32(v0).ir_value(loc=loc, ip=ip),\n Float32(v1).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b8 b;\n cvt.rn.satfinite.e2m1x2.f32 b, $2, $1;\n cvt.u32.u8 $0, b;\n }\n \"\"\",\n \"=r,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@cute.jit\ndef quant_dequant_2(\n v0: Float32, v1: Float32, sf_f32: Float32, eff_scale: Float32\n) -> Tuple[Float32, Float32]:\n \"\"\"Quantize/dequantize two values through FP4.\"\"\"\n inv_scale = Float32(1.0) / eff_scale\n fp4_byte = cvt_fp32x2_to_e2m1x2(v0 * inv_scale, v1 * inv_scale)\n h2 = fp4_decode_2(fp4_byte)\n f0, f1 = f16x2_to_f32x2(h2)\n return f0 * sf_f32, f1 * sf_f32\n\n\n@cute.jit\ndef mx_scale_from_amax32(amax: Float32) -> Tuple[Float32, Float32]:\n \"\"\"Per-32 MXFP8 block scale from a precomputed amax.\n\n Returns ``(scale, inv_scale)`` with ``scale = pow2_ceil(amax/448)``\n (zero amax yields (0, 0), silencing the block).\n \"\"\"\n rounded, byte = pow2_ceil_ue8m0(amax * Float32(1.0 / FLOAT8_E4M3_MAX))\n inv_scale = ue8m0_to_output_scale(byte)\n return rounded, inv_scale\n\n\n@cute.jit\ndef quant_dequant_e4m3_2(\n v0: Float32,\n v1: Float32,\n inv_scale: Float32,\n scale: Float32,\n) -> Tuple[Float32, Float32]:\n \"\"\"Quantize-dequantize a pair through E4M3 with a power-of-two block scale.\n\n Keeps a8_mx decode numerics matched to the w4a8 prefill activation\n quantizer.\n \"\"\"\n q0 = fp8_e4m3_to_f32(cvt_f32_to_e4m3(v0 * inv_scale)) * scale\n q1 = fp8_e4m3_to_f32(cvt_f32_to_e4m3(v1 * inv_scale)) * scale\n return q0, q1\n\n\n@dsl_user_op\ndef fp4_dot4_sum(\n u_packed: Uint32,\n x0: Uint32,\n x1: Uint32,\n x2: Uint32,\n x3: Uint32,\n *,\n loc=None,\n ip=None,\n) -> Float32:\n \"\"\"Decode 4 FP4 bytes and dot with four f16x2 inputs.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [\n Uint32(u_packed).ir_value(loc=loc, ip=ip),\n Uint32(x0).ir_value(loc=loc, ip=ip),\n Uint32(x1).ir_value(loc=loc, ip=ip),\n Uint32(x2).ir_value(loc=loc, ip=ip),\n Uint32(x3).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b8 b0, b1, b2, b3;\n .reg .b32 h0, h1, h2, h3;\n .reg .f16x2 acc;\n .reg .b16 lo, hi;\n .reg .f32 flo, fhi;\n mov.b32 {b0, b1, b2, b3}, $1;\n cvt.rn.f16x2.e2m1x2 h0, b0;\n cvt.rn.f16x2.e2m1x2 h1, b1;\n cvt.rn.f16x2.e2m1x2 h2, b2;\n cvt.rn.f16x2.e2m1x2 h3, b3;\n mov.b32 acc, 0;\n fma.rn.f16x2 acc, h0, $2, acc;\n fma.rn.f16x2 acc, h1, $3, acc;\n fma.rn.f16x2 acc, h2, $4, acc;\n fma.rn.f16x2 acc, h3, $5, acc;\n mov.b32 {lo, hi}, acc;\n cvt.f32.f16 flo, lo;\n cvt.f32.f16 fhi, hi;\n add.f32 $0, flo, fhi;\n }\n \"\"\",\n \"=f,r,r,r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef fp4_dot8_sum(\n u_a: Uint32,\n u_b: Uint32,\n x0: Uint32,\n x1: Uint32,\n x2: Uint32,\n x3: Uint32,\n x4: Uint32,\n x5: Uint32,\n x6: Uint32,\n x7: Uint32,\n *,\n loc=None,\n ip=None,\n) -> Float32:\n \"\"\"Decode 8 FP4 bytes and dot with eight f16x2 inputs.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [\n Uint32(u_a).ir_value(loc=loc, ip=ip),\n Uint32(u_b).ir_value(loc=loc, ip=ip),\n Uint32(x0).ir_value(loc=loc, ip=ip),\n Uint32(x1).ir_value(loc=loc, ip=ip),\n Uint32(x2).ir_value(loc=loc, ip=ip),\n Uint32(x3).ir_value(loc=loc, ip=ip),\n Uint32(x4).ir_value(loc=loc, ip=ip),\n Uint32(x5).ir_value(loc=loc, ip=ip),\n Uint32(x6).ir_value(loc=loc, ip=ip),\n Uint32(x7).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b8 a0, a1, a2, a3;\n .reg .b8 b0, b1, b2, b3;\n .reg .b32 h0, h1, h2, h3, h4, h5, h6, h7;\n .reg .f16x2 acc;\n .reg .b16 lo, hi;\n .reg .f32 flo, fhi;\n mov.b32 {a0, a1, a2, a3}, $1;\n mov.b32 {b0, b1, b2, b3}, $2;\n cvt.rn.f16x2.e2m1x2 h0, a0;\n cvt.rn.f16x2.e2m1x2 h1, a1;\n cvt.rn.f16x2.e2m1x2 h2, a2;\n cvt.rn.f16x2.e2m1x2 h3, a3;\n cvt.rn.f16x2.e2m1x2 h4, b0;\n cvt.rn.f16x2.e2m1x2 h5, b1;\n cvt.rn.f16x2.e2m1x2 h6, b2;\n cvt.rn.f16x2.e2m1x2 h7, b3;\n mov.b32 acc, 0;\n fma.rn.f16x2 acc, h0, $3, acc;\n fma.rn.f16x2 acc, h1, $4, acc;\n fma.rn.f16x2 acc, h2, $5, acc;\n fma.rn.f16x2 acc, h3, $6, acc;\n fma.rn.f16x2 acc, h4, $7, acc;\n fma.rn.f16x2 acc, h5, $8, acc;\n fma.rn.f16x2 acc, h6, $9, acc;\n fma.rn.f16x2 acc, h7, $10, acc;\n mov.b32 {lo, hi}, acc;\n cvt.f32.f16 flo, lo;\n cvt.f32.f16 fhi, hi;\n add.f32 $0, flo, fhi;\n }\n \"\"\",\n \"=f,r,r,r,r,r,r,r,r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@cute.jit\ndef _f16x2_dot_sum_f32acc(a_h2: Uint32, b_h2: Uint32) -> Float32:\n a0, a1 = f16x2_to_f32x2(a_h2)\n b0, b1 = f16x2_to_f32x2(b_h2)\n return a0 * b0 + a1 * b1\n\n\n@cute.jit\ndef fp4_dot4_sum_f32acc(\n u_packed: Uint32,\n x0: Uint32,\n x1: Uint32,\n x2: Uint32,\n x3: Uint32,\n) -> Float32:\n \"\"\"Decode FP4 then accumulate a 4-byte dot product in f32.\"\"\"\n h0, h1, h2, h3 = fp4_decode_4bytes(u_packed)\n return (\n _f16x2_dot_sum_f32acc(h0, x0)\n + _f16x2_dot_sum_f32acc(h1, x1)\n + _f16x2_dot_sum_f32acc(h2, x2)\n + _f16x2_dot_sum_f32acc(h3, x3)\n )\n\n\n@cute.jit\ndef fp4_dot8_sum_f32acc(\n u_a: Uint32,\n u_b: Uint32,\n x0: Uint32,\n x1: Uint32,\n x2: Uint32,\n x3: Uint32,\n x4: Uint32,\n x5: Uint32,\n x6: Uint32,\n x7: Uint32,\n) -> Float32:\n \"\"\"Decode FP4 then accumulate an 8-byte dot product in f32.\"\"\"\n h0, h1, h2, h3 = fp4_decode_4bytes(u_a)\n h4, h5, h6, h7 = fp4_decode_4bytes(u_b)\n return (\n _f16x2_dot_sum_f32acc(h0, x0)\n + _f16x2_dot_sum_f32acc(h1, x1)\n + _f16x2_dot_sum_f32acc(h2, x2)\n + _f16x2_dot_sum_f32acc(h3, x3)\n + _f16x2_dot_sum_f32acc(h4, x4)\n + _f16x2_dot_sum_f32acc(h5, x5)\n + _f16x2_dot_sum_f32acc(h6, x6)\n + _f16x2_dot_sum_f32acc(h7, x7)\n )\n\n\n@dsl_user_op\ndef pack_f32x2_to_f16x2(a: Float32, b: Float32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Pack two f32 values into one f16x2 register.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [\n Float32(a).ir_value(loc=loc, ip=ip),\n Float32(b).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b16 lo, hi;\n cvt.rn.f16.f32 lo, $1;\n cvt.rn.f16.f32 hi, $2;\n mov.b32 $0, {lo, hi};\n }\n \"\"\",\n \"=r,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n# =============================================================================\n# FP4 Quantization — Fast approximate path\n# =============================================================================\n\n\n@cute.jit\ndef quantize_and_pack_16_fast(y_f32: cute.Tensor, inv_scale: Float32) -> Uint64:\n \"\"\"Fast approximate FP4 quantize/pack for 16 float32 values.\"\"\"\n q = cute.make_rmem_tensor((16,), Float32)\n for i in cutlass.range_constexpr(16):\n q[i] = y_f32[i] * inv_scale\n\n packed_lo = cvt_e2m1x8_f32(q[0], q[1], q[2], q[3], q[4], q[5], q[6], q[7])\n packed_hi = cvt_e2m1x8_f32(q[8], q[9], q[10], q[11], q[12], q[13], q[14], q[15])\n return (Uint64(packed_hi) << Uint64(32)) | Uint64(packed_lo)\n\n\n# =============================================================================\n# FP4 Block Quantization Helpers (for MoE kernels)\n# =============================================================================\n\n\n@cute.jit\ndef quantize_block_fp4(\n values: cute.Tensor,\n max_abs: Float32,\n global_scale_val: Float32,\n) -> Tuple[Uint64, Uint8]:\n \"\"\"Quantize 16 float32 values to packed FP4 + e4m3 scale byte.\n\n Given 16 values and their pre-computed max_abs, derives the NVFP4 block\n scale, quantizes to FP4, and packs into a uint64. Returns\n (packed_fp4_u64, scale_byte).\n \"\"\"\n scale_float = max_abs / (Float32(FLOAT4_E2M1_MAX) * global_scale_val)\n scale_float = fmin_f32(scale_float, Float32(FLOAT8_E4M3_MAX))\n scale_u32 = cvt_f32_to_e4m3(scale_float)\n scale_byte = Uint8(scale_u32 & Uint32(0xFF))\n quantized_scale = fp8_e4m3_to_f32(scale_u32)\n packed64 = Uint64(0)\n if quantized_scale != Float32(0.0) and global_scale_val != Float32(0.0):\n # 1/(qs*gs): precise counterpart of the fast path's rcp(qs)*rcp(gs).\n packed64 = quantize_and_pack_16(\n values, Float32(1.0) / (quantized_scale * global_scale_val)\n )\n return packed64, scale_byte\n\n\n@cute.jit\ndef quantize_block_fp4_fast(\n values: cute.Tensor,\n max_abs: Float32,\n global_scale_val: Float32,\n) -> Tuple[Uint64, Uint8]:\n \"\"\"Fast approximate FP4 block quantization using reciprocal/vector path.\"\"\"\n scale_u32 = Uint32(0)\n scale_byte = Uint8(0)\n packed64 = Uint64(0)\n if global_scale_val != Float32(0.0):\n fp4_max_rcp = rcp_approx_ftz(Float32(FLOAT4_E2M1_MAX))\n gs_recip = rcp_approx_ftz(global_scale_val)\n scale_float = gs_recip * (max_abs * fp4_max_rcp)\n scale_float = fmin_f32(scale_float, Float32(FLOAT8_E4M3_MAX))\n scale_u32 = cvt_f32_to_e4m3(scale_float)\n scale_byte = Uint8(scale_u32 & Uint32(0xFF))\n inv_quantized_scale = fp8_e4m3_to_f32_and_rcp(scale_u32)\n if inv_quantized_scale != Float32(0.0):\n packed64 = quantize_and_pack_16_fast(values, inv_quantized_scale * gs_recip)\n return packed64, scale_byte\n\n\n@cute.jit\ndef max_abs_16(values: cute.Tensor) -> Float32:\n \"\"\"Compute the maximum absolute value of 16 float32 values.\"\"\"\n result = fabs_f32(values[0])\n for i in cutlass.range_constexpr(1, 16):\n result = fmax_f32(result, fabs_f32(values[i]))\n return result\n\n\n@cute.jit\ndef silu_mul_16(\n gate: cute.Tensor,\n up: cute.Tensor,\n) -> cute.Tensor:\n \"\"\"Fused SiLU(gate) * up for 16 float32 element pairs.\n\n Used in MoE kernel epilogue to fuse the activation function\n between GEMM1 and GEMM2, avoiding the gmem round-trip.\n \"\"\"\n out = cute.make_rmem_tensor((16,), Float32)\n for i in cutlass.range_constexpr(16):\n g = gate[i]\n sigmoid_g = cute.arch.rcp_approx(\n Float32(1.0) + cute.math.exp(-g, fastmath=False)\n )\n out[i] = g * sigmoid_g * up[i]\n return out\n\n\n@cute.jit\ndef silu_mul_quantize_block_fp4(\n gate: cute.Tensor,\n up: cute.Tensor,\n global_scale_val: Float32,\n) -> Tuple[Uint64, Uint8]:\n \"\"\"Fused SiLU(gate)*up + FP4 quantize for 16 element pairs.\"\"\"\n activated = silu_mul_16(gate, up)\n block_max = max_abs_16(activated)\n return quantize_block_fp4(activated, block_max, global_scale_val)\n\n\n# =============================================================================\n# ReLU2 Activation — ReLU(x)² for non-gated MoE (Nemotron-Super)\n# =============================================================================\n\n\n@cute.jit\ndef relu2_16(x: cute.Tensor) -> cute.Tensor:\n \"\"\"Compute ReLU²(x) = max(0, x)² for 16 float32 values.\"\"\"\n out = cute.make_rmem_tensor((16,), Float32)\n for i in cutlass.range_constexpr(16):\n v = fmax_f32(x[i], Float32(0.0))\n out[i] = v * v\n return out\n\n\n@cute.jit\ndef relu2_quantize_block_fp4(\n x: cute.Tensor,\n global_scale_val: Float32,\n) -> Tuple[Uint64, Uint8]:\n \"\"\"Fused ReLU² + FP4 quantize for 16 float32 values.\"\"\"\n activated = relu2_16(x)\n block_max = max_abs_16(activated)\n return quantize_block_fp4(activated, block_max, global_scale_val)\n"},"diff":{"kind":"string","value":"--- flashinfer/cute_dsl/fp4_common.py\n+++ flashinfer/cute_dsl/fp4_common.py\n@@ -223,6 +223,22 @@\n \n \n @dsl_user_op\n+def prefetch_global_l2(base_ptr: Int64, *, loc=None, ip=None) -> None:\n+ \"\"\"Prefetch a global memory line into L2.\"\"\"\n+ llvm.inline_asm(\n+ None,\n+ [Int64(base_ptr).ir_value(loc=loc, ip=ip)],\n+ \"prefetch.global.L2 [$0];\",\n+ \"l\",\n+ has_side_effects=True,\n+ is_align_stack=False,\n+ asm_dialect=llvm.AsmDialect.AD_ATT,\n+ loc=loc,\n+ ip=ip,\n+ )\n+\n+\n+@dsl_user_op\n def st_global_u64(base_ptr: Int64, value: Uint64, *, loc=None, ip=None):\n \"\"\"Store 64 bits to global memory.\"\"\"\n llvm.inline_asm(\n@@ -257,15 +273,18 @@\n \n \n @dsl_user_op\n-def get_ptr_as_int64(tensor: cute.Tensor, offset: Int32, *, loc=None, ip=None) -> Int64:\n+def get_ptr_as_int64(tensor: cute.Tensor, offset, *, loc=None, ip=None) -> Int64:\n \"\"\"Get the memory address of tensor[offset] as Int64.\n+\n+ ``offset`` may be Int32 or Int64 and is added to the iterator unchanged,\n+ so 64-bit offsets are not truncated.\n \n WARNING: This uses ptrtoint which strips address space information.\n For SMEM tensors, the resulting Int64 is a raw SMEM offset that does NOT\n work with generic-addressing loads (ld.v4.u32). Use only with explicit\n address-space loads (ld.global.*) or for global memory tensors.\n \"\"\"\n- elem_ptr = tensor.iterator + Int32(offset)\n+ elem_ptr = tensor.iterator + offset\n ptr_int = llvm.ptrtoint(T.i64(), elem_ptr.llvm_ptr, loc=loc, ip=ip)\n return Int64(ptr_int)\n \n@@ -1133,6 +1152,150 @@\n )\n \n \n+@dsl_user_op\n+def pow2_ceil_ue8m0(\n+ scale: Float32,\n+ *,\n+ loc=None,\n+ ip=None,\n+) -> Tuple[Float32, Uint32]:\n+ \"\"\"Round a positive FP32 ``scale`` up to a power of two, bit-exactly.\n+\n+ Returns ``(rounded_fp32, ue8m0_byte)`` with ``ue8m0_byte`` the biased\n+ exponent of the rounded value. Unlike ``cvt_f32_to_ue8m0``, this matches\n+ the fp8_quant.cuh and scale_convert.cuh fp32_to_ue8m0 references\n+ bit-for-bit.\n+ \"\"\"\n+ result = llvm.inline_asm(\n+ llvm.StructType.get_literal([T.f32(), T.i32()]),\n+ [Float32(scale).ir_value(loc=loc, ip=ip)],\n+ \"\"\"\n+ {\n+ .reg .pred p_mant;\n+ .reg .b32 bits, mant;\n+\n+ // bits = __float_as_uint(scale)\n+ mov.b32 bits, $2;\n+ // mant = bits & 0x007FFFFF (mantissa field)\n+ and.b32 mant, bits, 8388607;\n+ setp.ne.u32 p_mant, mant, 0;\n+ // if (mant) bits = (bits + 0x00800000) & 0x7F800000\n+ @p_mant add.u32 bits, bits, 8388608;\n+ @p_mant and.b32 bits, bits, 2139095040;\n+ // rounded fp32 scale = __uint_as_float(bits)\n+ mov.b32 $0, bits;\n+ // ue8m0 = (bits >> 23) & 0xFF\n+ bfe.u32 $1, bits, 23, 8;\n+ }\n+ \"\"\",\n+ \"=f,=r,f\",\n+ has_side_effects=False,\n+ is_align_stack=False,\n+ asm_dialect=llvm.AsmDialect.AD_ATT,\n+ loc=loc,\n+ ip=ip,\n+ )\n+ rounded = llvm.extractvalue(T.f32(), result, [0], loc=loc, ip=ip)\n+ ue8m0 = llvm.extractvalue(T.i32(), result, [1], loc=loc, ip=ip)\n+ return Float32(rounded), Uint32(ue8m0)\n+\n+\n+@dsl_user_op\n+def cvt_e8m0_to_f32(e8m0_val: Uint32, *, loc=None, ip=None) -> Float32:\n+ \"\"\"Convert a single E8M0 scale byte to its true f32 value 2**(byte-127).\n+\n+ Byte 0 maps to 0.0.\n+ \"\"\"\n+ return Float32(\n+ llvm.inline_asm(\n+ T.f32(),\n+ [Uint32(e8m0_val).ir_value(loc=loc, ip=ip)],\n+ \"\"\"\n+ {\n+ .reg .pred p0;\n+ .reg .u32 b0;\n+ .reg .s32 e0;\n+ .reg .f32 ef0;\n+ and.b32 b0, $1, 0x000000ff;\n+ setp.eq.u32 p0, b0, 0;\n+ cvt.s32.u32 e0, b0;\n+ sub.s32 e0, e0, 127;\n+ cvt.rn.f32.s32 ef0, e0;\n+ ex2.approx.f32 $0, ef0;\n+ selp.f32 $0, 0f00000000, $0, p0;\n+ }\n+ \"\"\",\n+ \"=f,r\",\n+ has_side_effects=False,\n+ is_align_stack=False,\n+ asm_dialect=llvm.AsmDialect.AD_ATT,\n+ loc=loc,\n+ ip=ip,\n+ )\n+ )\n+\n+\n+@dsl_user_op\n+def cvt_e8m0x4_to_f32x4(\n+ packed: Uint32, *, loc=None, ip=None\n+) -> Tuple[Float32, Float32, Float32, Float32]:\n+ \"\"\"Decode 4 E8M0 scale bytes (packed u32) to 4 x true f32 (2**(byte-127)).\"\"\"\n+ result = llvm.inline_asm(\n+ llvm.StructType.get_literal([T.f32(), T.f32(), T.f32(), T.f32()]),\n+ [Uint32(packed).ir_value(loc=loc, ip=ip)],\n+ \"\"\"\n+ {\n+ .reg .pred p0, p1, p2, p3;\n+ .reg .u32 b0, b1, b2, b3;\n+ .reg .s32 e0, e1, e2, e3;\n+ .reg .f32 ef0, ef1, ef2, ef3;\n+ and.b32 b0, $4, 0x000000ff;\n+ shr.u32 b1, $4, 8;\n+ and.b32 b1, b1, 0x000000ff;\n+ shr.u32 b2, $4, 16;\n+ and.b32 b2, b2, 0x000000ff;\n+ shr.u32 b3, $4, 24;\n+ setp.eq.u32 p0, b0, 0;\n+ setp.eq.u32 p1, b1, 0;\n+ setp.eq.u32 p2, b2, 0;\n+ setp.eq.u32 p3, b3, 0;\n+ cvt.s32.u32 e0, b0;\n+ cvt.s32.u32 e1, b1;\n+ cvt.s32.u32 e2, b2;\n+ cvt.s32.u32 e3, b3;\n+ sub.s32 e0, e0, 127;\n+ sub.s32 e1, e1, 127;\n+ sub.s32 e2, e2, 127;\n+ sub.s32 e3, e3, 127;\n+ cvt.rn.f32.s32 ef0, e0;\n+ cvt.rn.f32.s32 ef1, e1;\n+ cvt.rn.f32.s32 ef2, e2;\n+ cvt.rn.f32.s32 ef3, e3;\n+ ex2.approx.f32 $0, ef0;\n+ ex2.approx.f32 $1, ef1;\n+ ex2.approx.f32 $2, ef2;\n+ ex2.approx.f32 $3, ef3;\n+ selp.f32 $0, 0f00000000, $0, p0;\n+ selp.f32 $1, 0f00000000, $1, p1;\n+ selp.f32 $2, 0f00000000, $2, p2;\n+ selp.f32 $3, 0f00000000, $3, p3;\n+ }\n+ \"\"\",\n+ \"=f,=f,=f,=f,r\",\n+ has_side_effects=False,\n+ is_align_stack=False,\n+ asm_dialect=llvm.AsmDialect.AD_ATT,\n+ loc=loc,\n+ ip=ip,\n+ )\n+ return (\n+ Float32(llvm.extractvalue(T.f32(), result, [0], loc=loc, ip=ip)),\n+ Float32(llvm.extractvalue(T.f32(), result, [1], loc=loc, ip=ip)),\n+ Float32(llvm.extractvalue(T.f32(), result, [2], loc=loc, ip=ip)),\n+ Float32(llvm.extractvalue(T.f32(), result, [3], loc=loc, ip=ip)),\n+ )\n+\n+\n # =============================================================================\n # E2M1 Conversion\n # =============================================================================\n@@ -2044,6 +2207,38 @@\n \n \n @dsl_user_op\n+def cvt_w4a16_packed_e4m3_scale_to_f32(\n+ packed_byte: Uint32, *, loc=None, ip=None\n+) -> Float32:\n+ \"\"\"Scalar mirror of packed_dequant_e4m3x4_to_bfloat2x2 for W4A16 scales.\"\"\"\n+ return Float32(\n+ llvm.inline_asm(\n+ T.f32(),\n+ [Uint32(packed_byte).ir_value(loc=loc, ip=ip)],\n+ \"\"\"\n+ {\n+ .reg .b32 bits, tmp;\n+ .reg .b16 bf;\n+ and.b32 bits, $1, 0x80;\n+ shl.b32 bits, bits, 7;\n+ and.b32 tmp, $1, 0x7f;\n+ shl.b32 tmp, tmp, 4;\n+ or.b32 bits, bits, tmp;\n+ cvt.u16.u32 bf, bits;\n+ cvt.f32.bf16 $0, bf;\n+ }\n+ \"\"\",\n+ \"=f,r\",\n+ has_side_effects=False,\n+ is_align_stack=False,\n+ asm_dialect=llvm.AsmDialect.AD_ATT,\n+ loc=loc,\n+ ip=ip,\n+ )\n+ )\n+\n+\n+@dsl_user_op\n def cvt_s0e5m3_to_f16x2_broadcast(fp8_val: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Convert one S0E5M3 scale byte to an f16x2 with the scale in both lanes.\n \n@@ -2166,6 +2361,35 @@\n h2 = fp4_decode_2(fp4_byte)\n f0, f1 = f16x2_to_f32x2(h2)\n return f0 * sf_f32, f1 * sf_f32\n+\n+\n+@cute.jit\n+def mx_scale_from_amax32(amax: Float32) -> Tuple[Float32, Float32]:\n+ \"\"\"Per-32 MXFP8 block scale from a precomputed amax.\n+\n+ Returns ``(scale, inv_scale)`` with ``scale = pow2_ceil(amax/448)``\n+ (zero amax yields (0, 0), silencing the block).\n+ \"\"\"\n+ rounded, byte = pow2_ceil_ue8m0(amax * Float32(1.0 / FLOAT8_E4M3_MAX))\n+ inv_scale = ue8m0_to_output_scale(byte)\n+ return rounded, inv_scale\n+\n+\n+@cute.jit\n+def quant_dequant_e4m3_2(\n+ v0: Float32,\n+ v1: Float32,\n+ inv_scale: Float32,\n+ scale: Float32,\n+) -> Tuple[Float32, Float32]:\n+ \"\"\"Quantize-dequantize a pair through E4M3 with a power-of-two block scale.\n+\n+ Keeps a8_mx decode numerics matched to the w4a8 prefill activation\n+ quantizer.\n+ \"\"\"\n+ q0 = fp8_e4m3_to_f32(cvt_f32_to_e4m3(v0 * inv_scale)) * scale\n+ q1 = fp8_e4m3_to_f32(cvt_f32_to_e4m3(v1 * inv_scale)) * scale\n+ return q0, q1\n \n \n @dsl_user_op"},"lines_added":{"kind":"number","value":226,"string":"226"},"lines_removed":{"kind":"number","value":2,"string":"2"},"files_in_commit":{"kind":"number","value":8,"string":"8"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["RTX5080","SM121"],"string":"[\n \"RTX5080\",\n \"SM121\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":["1.06x","1.30x","1.40x","1.00x","1.00x","1.00x","1.10x","1.10x","1.09x","1.00x"],"string":"[\n \"1.06x\",\n \"1.30x\",\n \"1.40x\",\n \"1.00x\",\n \"1.00x\",\n \"1.00x\",\n \"1.10x\",\n \"1.10x\",\n \"1.09x\",\n \"1.00x\"\n]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cute_dsl kernel file from flashinfer (flashinfer/cute_dsl/fp4_common.py).\n\nGoal: perf(moe): sync SM12x NVFP4 fused-MoE kernels to b12x HEAD\nTarget hardware: RTX5080, SM121\nTarget models: unspecified\n\nCurrent file:\n```python\n\"\"\"\nCopyright (c) 2025 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nCommon utilities for FP4 quantization kernels using CuTe-DSL.\n\nThis module contains shared PTX intrinsics, helper functions, and reduction\nutilities used by both rmsnorm_fp4quant.py and add_rmsnorm_fp4quant.py.\n\"\"\"\n\nimport functools\nimport math\nimport operator\nfrom typing import Callable, Tuple\n\nimport cutlass\nimport cutlass.cute as cute\nimport torch\nfrom cutlass import Float32, Int32, Int64, Uint8, Uint32, Uint64\nfrom cutlass.cutlass_dsl import T, dsl_user_op\nfrom cutlass._mlir import ir\nfrom cutlass._mlir.dialects import llvm\n\n\n# =============================================================================\n# Constants\n# =============================================================================\n\nFLOAT4_E2M1_MAX = 6.0 # Maximum value representable in FP4 E2M1\nFLOAT8_E4M3_MAX = 448.0 # Maximum value representable in FP8 E4M3\nSF_VEC_SIZE = 16 # Elements per scale factor block\nCOPY_BITS = 128 # 128-bit vectorized loads\n\n\n# =============================================================================\n# Architecture Detection\n# =============================================================================\n\n\n@functools.lru_cache(maxsize=16)\ndef get_sm_version(device: int | torch.device | str | None = None) -> int:\n \"\"\"Get the SM version of a CUDA device.\n\n Args:\n device: CUDA device to query. Can be an int (device index), torch.device,\n device string (e.g., 'cuda:0'), or None to use current device.\n\n Returns:\n SM version as an integer (e.g., 100 for SM100).\n \"\"\"\n if not torch.cuda.is_available():\n return 80\n if device is None:\n device = torch.cuda.current_device()\n props = torch.cuda.get_device_properties(device)\n return props.major * 10 + props.minor\n\n\n# =============================================================================\n# PTX Intrinsics - Cluster Operations\n# =============================================================================\n\n\n@dsl_user_op\ndef set_block_rank(\n smem_ptr: cute.Pointer, peer_cta_rank_in_cluster: Int32, *, loc=None, ip=None\n) -> Int32:\n \"\"\"Map smem pointer to address at another CTA rank in the cluster.\"\"\"\n smem_ptr_i32 = smem_ptr.toint(loc=loc, ip=ip).ir_value()\n return Int32(\n llvm.inline_asm(\n T.i32(),\n [smem_ptr_i32, peer_cta_rank_in_cluster.ir_value()],\n \"mapa.shared::cluster.u32 $0, $1, $2;\",\n \"=r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef store_shared_remote(\n val: Float32,\n smem_ptr: cute.Pointer,\n mbar_ptr: cute.Pointer,\n peer_cta_rank_in_cluster: Int32,\n *,\n loc=None,\n ip=None,\n) -> None:\n \"\"\"Store Float32 value to shared memory on a remote CTA in the cluster.\"\"\"\n remote_smem_ptr_i32 = set_block_rank(\n smem_ptr, peer_cta_rank_in_cluster, loc=loc, ip=ip\n ).ir_value()\n remote_mbar_ptr_i32 = set_block_rank(\n mbar_ptr, peer_cta_rank_in_cluster, loc=loc, ip=ip\n ).ir_value()\n llvm.inline_asm(\n None,\n [remote_smem_ptr_i32, val.ir_value(loc=loc, ip=ip), remote_mbar_ptr_i32],\n \"st.async.shared::cluster.mbarrier::complete_tx::bytes.f32 [$0], $1, [$2];\",\n \"r,f,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n\n\n@dsl_user_op\ndef elem_pointer(x: cute.Tensor, coord, *, loc=None, ip=None) -> cute.Pointer:\n \"\"\"Get pointer to element at coordinate in tensor.\"\"\"\n return x.iterator + cute.crd2idx(coord, x.layout, loc=loc, ip=ip)\n\n\n# =============================================================================\n# PTX Intrinsics - 128-bit Vectorized Global Loads/Stores\n# =============================================================================\n\n\n@dsl_user_op\ndef ld_global_v4_u32(\n base_ptr: Int64, *, loc=None, ip=None\n) -> Tuple[Uint32, Uint32, Uint32, Uint32]:\n \"\"\"Load 128 bits (4 x uint32) from global memory.\"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.i32(), T.i32(), T.i32(), T.i32()]),\n [Int64(base_ptr).ir_value(loc=loc, ip=ip)],\n \"ld.global.v4.u32 {$0, $1, $2, $3}, [$4];\",\n \"=r,=r,=r,=r,l\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n v0 = llvm.extractvalue(T.i32(), result, [0], loc=loc, ip=ip)\n v1 = llvm.extractvalue(T.i32(), result, [1], loc=loc, ip=ip)\n v2 = llvm.extractvalue(T.i32(), result, [2], loc=loc, ip=ip)\n v3 = llvm.extractvalue(T.i32(), result, [3], loc=loc, ip=ip)\n\n return Uint32(v0), Uint32(v1), Uint32(v2), Uint32(v3)\n\n\n@dsl_user_op\ndef ld_v4_u32(\n base_ptr: Int64, *, loc=None, ip=None\n) -> Tuple[Uint32, Uint32, Uint32, Uint32]:\n \"\"\"Load 128 bits (4 x uint32) using generic addressing (works for GMEM and SMEM).\"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.i32(), T.i32(), T.i32(), T.i32()]),\n [Int64(base_ptr).ir_value(loc=loc, ip=ip)],\n \"ld.v4.u32 {$0, $1, $2, $3}, [$4];\",\n \"=r,=r,=r,=r,l\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n v0 = llvm.extractvalue(T.i32(), result, [0], loc=loc, ip=ip)\n v1 = llvm.extractvalue(T.i32(), result, [1], loc=loc, ip=ip)\n v2 = llvm.extractvalue(T.i32(), result, [2], loc=loc, ip=ip)\n v3 = llvm.extractvalue(T.i32(), result, [3], loc=loc, ip=ip)\n\n return Uint32(v0), Uint32(v1), Uint32(v2), Uint32(v3)\n\n\n@dsl_user_op\ndef ld_global_nc_u32(base_ptr: Int64, *, loc=None, ip=None) -> Uint32:\n \"\"\"Load 32 bits from global memory through the non-coherent cache.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Int64(base_ptr).ir_value(loc=loc, ip=ip)],\n \"ld.global.nc.u32 $0, [$1];\",\n \"=r,l\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef ld_global_nc_v4_u32(\n base_ptr: Int64, *, loc=None, ip=None\n) -> Tuple[Uint32, Uint32, Uint32, Uint32]:\n \"\"\"Load 128 bits from global memory through the non-coherent cache.\"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.i32(), T.i32(), T.i32(), T.i32()]),\n [Int64(base_ptr).ir_value(loc=loc, ip=ip)],\n \"ld.global.nc.v4.u32 {$0, $1, $2, $3}, [$4];\",\n \"=r,=r,=r,=r,l\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n return (\n Uint32(llvm.extractvalue(T.i32(), result, [0], loc=loc, ip=ip)),\n Uint32(llvm.extractvalue(T.i32(), result, [1], loc=loc, ip=ip)),\n Uint32(llvm.extractvalue(T.i32(), result, [2], loc=loc, ip=ip)),\n Uint32(llvm.extractvalue(T.i32(), result, [3], loc=loc, ip=ip)),\n )\n\n\n@dsl_user_op\ndef st_global_u64(base_ptr: Int64, value: Uint64, *, loc=None, ip=None):\n \"\"\"Store 64 bits to global memory.\"\"\"\n llvm.inline_asm(\n None,\n [\n Int64(base_ptr).ir_value(loc=loc, ip=ip),\n Uint64(value).ir_value(loc=loc, ip=ip),\n ],\n \"st.global.u64 [$0], $1;\",\n \"l,l\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n\n\n@dsl_user_op\ndef st_global_u32(base_ptr: Int64, value: Uint32, *, loc=None, ip=None):\n \"\"\"Store 32 bits to global memory.\"\"\"\n llvm.inline_asm(\n None,\n [\n Int64(base_ptr).ir_value(loc=loc, ip=ip),\n Uint32(value).ir_value(loc=loc, ip=ip),\n ],\n \"st.global.u32 [$0], $1;\",\n \"l,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n\n\n@dsl_user_op\ndef get_ptr_as_int64(tensor: cute.Tensor, offset: Int32, *, loc=None, ip=None) -> Int64:\n \"\"\"Get the memory address of tensor[offset] as Int64.\n\n WARNING: This uses ptrtoint which strips address space information.\n For SMEM tensors, the resulting Int64 is a raw SMEM offset that does NOT\n work with generic-addressing loads (ld.v4.u32). Use only with explicit\n address-space loads (ld.global.*) or for global memory tensors.\n \"\"\"\n elem_ptr = tensor.iterator + Int32(offset)\n ptr_int = llvm.ptrtoint(T.i64(), elem_ptr.llvm_ptr, loc=loc, ip=ip)\n return Int64(ptr_int)\n\n\n@dsl_user_op\ndef get_smem_ptr_as_int32(\n tensor: cute.Tensor, offset: Int32, *, loc=None, ip=None\n) -> Int32:\n \"\"\"Get the shared-memory byte address of tensor[offset] as Int32.\n\n Uses Pointer.toint() which preserves the SMEM address space (addrspace 3),\n returning a 32-bit SMEM address suitable for ld.shared.* instructions.\n \"\"\"\n elem_ptr = tensor.iterator + Int32(offset)\n return elem_ptr.toint(loc=loc, ip=ip)\n\n\n@dsl_user_op\ndef ld_shared_v2_u32(smem_addr: Int32, *, loc=None, ip=None) -> Tuple[Uint32, Uint32]:\n \"\"\"Load 64 bits (2 x uint32) from shared memory via ld.shared.v2.u32.\n\n Args:\n smem_addr: 32-bit shared memory address (from get_smem_ptr_as_int32).\n Caller is responsible for ensuring 8-byte alignment.\n\n Returns:\n 2 Uint32 values (8 bytes total).\n \"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.i32(), T.i32()]),\n [Int32(smem_addr).ir_value(loc=loc, ip=ip)],\n \"ld.shared.v2.u32 {$0, $1}, [$2];\",\n \"=r,=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n v0 = llvm.extractvalue(T.i32(), result, [0], loc=loc, ip=ip)\n v1 = llvm.extractvalue(T.i32(), result, [1], loc=loc, ip=ip)\n return Uint32(v0), Uint32(v1)\n\n\n@dsl_user_op\ndef ld_shared_v4_u32(\n smem_addr: Int32, *, loc=None, ip=None\n) -> Tuple[Uint32, Uint32, Uint32, Uint32]:\n \"\"\"Load 128 bits (4 x uint32) from shared memory via ld.shared.v4.u32.\n\n Args:\n smem_addr: 32-bit shared memory address (from get_smem_ptr_as_int32).\n\n Returns:\n 4 Uint32 values (16 bytes total, e.g. 8 packed fp16 elements).\n \"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.i32(), T.i32(), T.i32(), T.i32()]),\n [Int32(smem_addr).ir_value(loc=loc, ip=ip)],\n \"ld.shared.v4.u32 {$0, $1, $2, $3}, [$4];\",\n \"=r,=r,=r,=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n v0 = llvm.extractvalue(T.i32(), result, [0], loc=loc, ip=ip)\n v1 = llvm.extractvalue(T.i32(), result, [1], loc=loc, ip=ip)\n v2 = llvm.extractvalue(T.i32(), result, [2], loc=loc, ip=ip)\n v3 = llvm.extractvalue(T.i32(), result, [3], loc=loc, ip=ip)\n return Uint32(v0), Uint32(v1), Uint32(v2), Uint32(v3)\n\n\n@dsl_user_op\ndef pack_16bit_to_u32(lo, hi, *, loc=None, ip=None) -> Uint32:\n \"\"\"Pack two 16-bit scalar values (fp16 or bf16) into one Uint32 (half2/bfloat2).\n\n Uses PTX mov.b32 to bitwise-pack two 16-bit register values into a single\n 32-bit register, suitable for half2/bfloat2 SIMD operations.\n \"\"\"\n lo_ir = lo.ir_value(loc=loc, ip=ip)\n hi_ir = hi.ir_value(loc=loc, ip=ip)\n lo_i16 = llvm.bitcast(T.i16(), lo_ir, loc=loc, ip=ip)\n hi_i16 = llvm.bitcast(T.i16(), hi_ir, loc=loc, ip=ip)\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [lo_i16, hi_i16],\n \"mov.b32 $0, {$1, $2};\",\n \"=r,h,h\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n# =============================================================================\n# PTX Intrinsics - Math Operations\n# =============================================================================\n\n\n@dsl_user_op\ndef rcp_approx_ftz(a: Float32, *, loc=None, ip=None) -> Float32:\n \"\"\"Fast reciprocal using PTX rcp.approx.ftz.f32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Float32(a).ir_value(loc=loc, ip=ip)],\n \"rcp.approx.ftz.f32 $0, $1;\",\n \"=f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef rcp_rn(a: Float32, *, loc=None, ip=None) -> Float32:\n \"\"\"Round-to-nearest reciprocal using PTX div.rn.f32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Float32(a).ir_value(loc=loc, ip=ip)],\n \"div.rn.f32 $0, 0f3F800000, $1;\",\n \"=f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef fadd_rn(a: Float32, b: Float32, loc=None, ip=None) -> Float32:\n \"\"\"Round-to-nearest float32 addition.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Float32(a).ir_value(loc=loc, ip=ip), Float32(b).ir_value(loc=loc, ip=ip)],\n \"add.rn.f32 $0, $1, $2;\",\n \"=f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef fsub_rn(a: Float32, b: Float32, loc=None, ip=None) -> Float32:\n \"\"\"Round-to-nearest float32 subtraction.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Float32(a).ir_value(loc=loc, ip=ip), Float32(b).ir_value(loc=loc, ip=ip)],\n \"sub.rn.f32 $0, $1, $2;\",\n \"=f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef fmul_rn(a: Float32, b: Float32, loc=None, ip=None) -> Float32:\n \"\"\"Round-to-nearest float32 multiplication.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Float32(a).ir_value(loc=loc, ip=ip), Float32(b).ir_value(loc=loc, ip=ip)],\n \"mul.rn.f32 $0, $1, $2;\",\n \"=f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef fdiv_rn(a: Float32, b: Float32, loc=None, ip=None) -> Float32:\n \"\"\"Round-to-nearest float32 division.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Float32(a).ir_value(loc=loc, ip=ip), Float32(b).ir_value(loc=loc, ip=ip)],\n \"div.rn.f32 $0, $1, $2;\",\n \"=f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef fmin_f32(a: Float32, b: Float32, *, loc=None, ip=None) -> Float32:\n \"\"\"Compute min of two float32 values using PTX min.f32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Float32(a).ir_value(loc=loc, ip=ip), Float32(b).ir_value(loc=loc, ip=ip)],\n \"min.f32 $0, $1, $2;\",\n \"=f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef fmax_f32(a: Float32, b: Float32, *, loc=None, ip=None) -> Float32:\n \"\"\"Compute max of two float32 values using PTX max.f32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Float32(a).ir_value(loc=loc, ip=ip), Float32(b).ir_value(loc=loc, ip=ip)],\n \"max.f32 $0, $1, $2;\",\n \"=f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef fabs_f32(a: Float32, *, loc=None, ip=None) -> Float32:\n \"\"\"Compute absolute value of float32 using PTX abs.f32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Float32(a).ir_value(loc=loc, ip=ip)],\n \"abs.f32 $0, $1;\",\n \"=f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n# =============================================================================\n# Half2 SIMD Intrinsics\n# =============================================================================\n\n\n@dsl_user_op\ndef half2_mul(a: Uint32, b: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Multiply two Half2 values element-wise: (a.x*b.x, a.y*b.y).\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(a).ir_value(loc=loc, ip=ip), Uint32(b).ir_value(loc=loc, ip=ip)],\n \"mul.f16x2 $0, $1, $2;\",\n \"=r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef hadd2(a: Uint32, b: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Add two Half2 values element-wise: (a.x+b.x, a.y+b.y).\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(a).ir_value(loc=loc, ip=ip), Uint32(b).ir_value(loc=loc, ip=ip)],\n \"add.f16x2 $0, $1, $2;\",\n \"=r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef habs2(x: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Half2 absolute value - clears sign bits of both fp16 values.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(x).ir_value(loc=loc, ip=ip)],\n \"and.b32 $0, $1, 0x7FFF7FFF;\",\n \"=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef hmax2(a: Uint32, b: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Half2 max - element-wise max of 2 fp16 pairs.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(a).ir_value(loc=loc, ip=ip), Uint32(b).ir_value(loc=loc, ip=ip)],\n \"max.f16x2 $0, $1, $2;\",\n \"=r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef hmax_to_f32(x: Uint32, *, loc=None, ip=None) -> Float32:\n \"\"\"Extract max of 2 fp16 values in half2 as float32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Uint32(x).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 h0, h1;\n .reg .f32 f0, f1;\n mov.b32 {h0, h1}, $1;\n cvt.f32.f16 f0, h0;\n cvt.f32.f16 f1, h1;\n max.f32 $0, f0, f1;\n }\n \"\"\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef half2_to_float2_scaled(\n h2: Uint32, scale: Float32, *, loc=None, ip=None\n) -> Tuple[Float32, Float32]:\n \"\"\"Convert half2 to float2 AND multiply by scale.\"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.f32(), T.f32()]),\n [Uint32(h2).ir_value(loc=loc, ip=ip), Float32(scale).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 h0, h1;\n .reg .f32 f0, f1;\n mov.b32 {h0, h1}, $2;\n cvt.f32.f16 f0, h0;\n cvt.f32.f16 f1, h1;\n mul.f32 $0, f0, $3;\n mul.f32 $1, f1, $3;\n }\n \"\"\",\n \"=f,=f,r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n f0 = llvm.extractvalue(T.f32(), result, [0], loc=loc, ip=ip)\n f1 = llvm.extractvalue(T.f32(), result, [1], loc=loc, ip=ip)\n\n return Float32(f0), Float32(f1)\n\n\n# =============================================================================\n# BFloat2 SIMD Intrinsics\n# =============================================================================\n\n\n@dsl_user_op\ndef bfloat2_mul(a: Uint32, b: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Multiply two BFloat2 values element-wise: (a.x*b.x, a.y*b.y).\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(a).ir_value(loc=loc, ip=ip), Uint32(b).ir_value(loc=loc, ip=ip)],\n \"mul.bf16x2 $0, $1, $2;\",\n \"=r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef bfloat2_add(a: Uint32, b: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Add two BFloat2 values element-wise: (a.x+b.x, a.y+b.y).\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(a).ir_value(loc=loc, ip=ip), Uint32(b).ir_value(loc=loc, ip=ip)],\n \"add.bf16x2 $0, $1, $2;\",\n \"=r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef bfloat2_habs2(x: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"BFloat16x2 absolute value - clears sign bits of both bf16 values.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(x).ir_value(loc=loc, ip=ip)],\n \"and.b32 $0, $1, 0x7FFF7FFF;\",\n \"=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef bfloat2_hmax2(a: Uint32, b: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"BFloat16x2 max - element-wise max of 2 bf16 pairs.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(a).ir_value(loc=loc, ip=ip), Uint32(b).ir_value(loc=loc, ip=ip)],\n \"max.bf16x2 $0, $1, $2;\",\n \"=r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef bfloat2_hmax_to_f32(x: Uint32, *, loc=None, ip=None) -> Float32:\n \"\"\"Extract max of 2 bf16 values in bfloat2 as float32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Uint32(x).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b32 lo, hi;\n .reg .f32 f0, f1;\n and.b32 lo, $1, 0xFFFF;\n shr.b32 hi, $1, 16;\n shl.b32 lo, lo, 16;\n shl.b32 hi, hi, 16;\n mov.b32 f0, lo;\n mov.b32 f1, hi;\n max.f32 $0, f0, f1;\n }\n \"\"\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef bfloat2_to_float2_scaled(\n bf2: Uint32, scale: Float32, *, loc=None, ip=None\n) -> Tuple[Float32, Float32]:\n \"\"\"Convert bfloat16x2 to float2 AND multiply by scale.\"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.f32(), T.f32()]),\n [Uint32(bf2).ir_value(loc=loc, ip=ip), Float32(scale).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b32 lo, hi;\n .reg .f32 f0, f1;\n and.b32 lo, $2, 0xFFFF;\n shr.b32 hi, $2, 16;\n shl.b32 lo, lo, 16;\n shl.b32 hi, hi, 16;\n mov.b32 f0, lo;\n mov.b32 f1, hi;\n mul.f32 $0, f0, $3;\n mul.f32 $1, f1, $3;\n }\n \"\"\",\n \"=f,=f,r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n f0 = llvm.extractvalue(T.f32(), result, [0], loc=loc, ip=ip)\n f1 = llvm.extractvalue(T.f32(), result, [1], loc=loc, ip=ip)\n\n return Float32(f0), Float32(f1)\n\n\n# =============================================================================\n# FP8 E4M3 Intrinsics\n# =============================================================================\n\n\n@dsl_user_op\ndef cvt_f32_to_e4m3(a: Float32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Convert float32 to E4M3 using native cvt.rn.satfinite.e4m3x2.f32.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Float32(a).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 fp8_pair;\n .reg .f32 zero;\n mov.f32 zero, 0f00000000;\n cvt.rn.satfinite.e4m3x2.f32 fp8_pair, zero, $1;\n cvt.u32.u16 $0, fp8_pair;\n }\n \"\"\",\n \"=r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef cvt_e4m3x4_to_f32x4(\n packed: Uint32, *, loc=None, ip=None\n) -> tuple[Float32, Float32, Float32, Float32]:\n \"\"\"Convert 4 packed E4M3 bytes (in a uint32) to 4 float32 values.\n\n Uses e4m3x2 → f16x2 → f32 conversion path (SM89+/PTX ISA 7.8+).\n Input: uint32 containing bytes [b0, b1, b2, b3] (low to high).\n Output: (f0, f1, f2, f3) as Float32.\n \"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.f32(), T.f32(), T.f32(), T.f32()]),\n [Uint32(packed).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 pair_lo, pair_hi;\n .reg .b32 h2_lo, h2_hi;\n .reg .b16 h0, h1, h2, h3;\n mov.b32 {pair_lo, pair_hi}, $4;\n cvt.rn.f16x2.e4m3x2 h2_lo, pair_lo;\n cvt.rn.f16x2.e4m3x2 h2_hi, pair_hi;\n mov.b32 {h0, h1}, h2_lo;\n mov.b32 {h2, h3}, h2_hi;\n cvt.f32.f16 $0, h0;\n cvt.f32.f16 $1, h1;\n cvt.f32.f16 $2, h2;\n cvt.f32.f16 $3, h3;\n }\n \"\"\",\n \"=f,=f,=f,=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n f0 = llvm.extractvalue(T.f32(), result, [0], loc=loc, ip=ip)\n f1 = llvm.extractvalue(T.f32(), result, [1], loc=loc, ip=ip)\n f2 = llvm.extractvalue(T.f32(), result, [2], loc=loc, ip=ip)\n f3 = llvm.extractvalue(T.f32(), result, [3], loc=loc, ip=ip)\n\n return Float32(f0), Float32(f1), Float32(f2), Float32(f3)\n\n\n@dsl_user_op\ndef cvt_f32x2_to_half2(a: Float32, b: Float32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Pack two float32 values into a half2 (uint32 containing two fp16 values).\n\n Uses cvt.rn.f16.f32 for each value, then packs into a single uint32.\n Matches __float22half2_rn() behavior in CUDA.\n \"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [\n Float32(a).ir_value(loc=loc, ip=ip),\n Float32(b).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b16 h0, h1;\n cvt.rn.f16.f32 h0, $1;\n cvt.rn.f16.f32 h1, $2;\n mov.b32 $0, {h0, h1};\n }\n \"\"\",\n \"=r,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef cvt_f32x2_to_bfloat2(a: Float32, b: Float32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Pack two float32 values into the low and high bfloat16 lanes, respectively.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [\n Float32(a).ir_value(loc=loc, ip=ip),\n Float32(b).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b16 h0, h1;\n cvt.rn.bf16.f32 h0, $1;\n cvt.rn.bf16.f32 h1, $2;\n mov.b32 $0, {h0, h1};\n }\n \"\"\",\n \"=r,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef fp8_e4m3_to_f32_and_rcp(fp8_val: Uint32, *, loc=None, ip=None) -> Float32:\n \"\"\"Convert FP8 E4M3 to float32 AND compute reciprocal (0 stays 0).\n\n Uses the hardware conversion instruction, which is exact for every\n finite e4m3 value, including subnormals, and matches how the tensor\n core decodes the same byte.\n \"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Uint32(fp8_val).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .pred p_zero;\n .reg .b16 fp8_pair;\n .reg .b32 h2_32;\n .reg .b16 h_lo, h_hi;\n .reg .f32 fp8_float, result;\n\n cvt.u16.u32 fp8_pair, $1;\n cvt.rn.f16x2.e4m3x2 h2_32, fp8_pair;\n mov.b32 {h_lo, h_hi}, h2_32;\n cvt.f32.f16 fp8_float, h_lo;\n rcp.approx.ftz.f32 result, fp8_float;\n setp.eq.f32 p_zero, fp8_float, 0f00000000;\n selp.f32 $0, 0f00000000, result, p_zero;\n }\n \"\"\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef nvfp4_compute_output_scale(\n fp8_val: Uint32, global_scale: Float32, *, loc=None, ip=None\n) -> Float32:\n \"\"\"Compute NVFP4 output_scale matching the CUDA kernel exactly.\n\n Converts E4M3 scale factor to float via hardware f16x2 path, then computes\n rcp(float_scale * rcp(global_scale)). Returns 0 when scale is zero.\n\n This matches quantization_utils.cuh:\n SFValue = static_cast<float>(tmp);\n outputScale = rcp_approx(SFValue * rcp_approx(SFScaleVal));\n \"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [\n Uint32(fp8_val).ir_value(loc=loc, ip=ip),\n Float32(global_scale).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .pred p_zero;\n .reg .b16 fp8_pair;\n .reg .b32 h2_32;\n .reg .b16 h_lo, h_hi;\n .reg .f32 scale_f32, rcp_gs, product, result;\n\n cvt.u16.u32 fp8_pair, $1;\n cvt.rn.f16x2.e4m3x2 h2_32, fp8_pair;\n mov.b32 {h_lo, h_hi}, h2_32;\n cvt.f32.f16 scale_f32, h_lo;\n\n rcp.approx.ftz.f32 rcp_gs, $2;\n mul.f32 product, scale_f32, rcp_gs;\n rcp.approx.ftz.f32 result, product;\n\n setp.eq.f32 p_zero, scale_f32, 0f00000000;\n selp.f32 $0, 0f00000000, result, p_zero;\n }\n \"\"\",\n \"=f,r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef nvfp4_compute_output_scale_rn(\n fp8_val: Uint32, global_scale: Float32, block_amax: Float32, *, loc=None, ip=None\n) -> Float32:\n \"\"\"Compute TE-exact NVFP4 output scale when FP4 quant fast math is disabled.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [\n Uint32(fp8_val).ir_value(loc=loc, ip=ip),\n Float32(global_scale).ir_value(loc=loc, ip=ip),\n Float32(block_amax).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .pred p_zero;\n .reg .b16 fp8_pair;\n .reg .b32 h2_32;\n .reg .b16 h_lo, h_hi;\n .reg .f32 scale_f32, rcp_gs, product, result, max_f32;\n\n cvt.u16.u32 fp8_pair, $1;\n cvt.rn.f16x2.e4m3x2 h2_32, fp8_pair;\n mov.b32 {h_lo, h_hi}, h2_32;\n cvt.f32.f16 scale_f32, h_lo;\n\n div.rn.f32 rcp_gs, 0f3F800000, $2;\n mul.rn.f32 product, scale_f32, rcp_gs;\n div.rn.f32 result, 0f3F800000, product;\n mov.b32 max_f32, 0x7F7FFFFF;\n min.f32 result, result, max_f32;\n\n setp.eq.f32 p_zero, $3, 0f00000000;\n selp.f32 $0, 0f00000000, result, p_zero;\n }\n \"\"\",\n \"=f,r,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n# =============================================================================\n# UE8M0 Intrinsics (for MXFP4)\n# =============================================================================\n\n\n@dsl_user_op\ndef cvt_f32_to_ue8m0(max_val: Float32, *, loc=None, ip=None) -> Uint32:\n \"\"\"\n Convert float32 max value to UE8M0 scale factor.\n\n UE8M0 is unsigned 8-bit exponent-only format:\n - value = 2^(ue8m0 - 127)\n - ue8m0 = ceil(log2(max_val)) + 127\n\n Uses lg2.approx.f32 for fast log2 approximation.\n Uses cvt.rpi (round towards positive infinity, i.e., ceiling).\n Returns value clamped to [0, 255].\n \"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Float32(max_val).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .pred p_zero, p_neg, p_ovf;\n .reg .f32 log2_val;\n .reg .s32 exp_int, result;\n\n // Check for zero/negative\n setp.le.f32 p_zero, $1, 0f00000000;\n\n // Compute ceil(log2(max_val)) using cvt.rpi (round towards +inf)\n lg2.approx.f32 log2_val, $1;\n cvt.rpi.s32.f32 exp_int, log2_val;\n\n // Add bias and clamp to [0, 255]\n add.s32 result, exp_int, 127;\n setp.lt.s32 p_neg, result, 0;\n setp.gt.s32 p_ovf, result, 255;\n selp.s32 result, 0, result, p_neg;\n selp.s32 result, 255, result, p_ovf;\n selp.s32 $0, 0, result, p_zero;\n }\n \"\"\",\n \"=r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef ue8m0_to_output_scale(ue8m0_val: Uint32, *, loc=None, ip=None) -> Float32:\n \"\"\"\n Convert UE8M0 to output_scale for MXFP4 quantization.\n\n UE8M0 value = 2^(ue8m0 - 127)\n Returns 1 / 2^(ue8m0 - 127) = 2^(127 - ue8m0)\n \"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Uint32(ue8m0_val).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .pred p_zero;\n .reg .s32 neg_exp;\n .reg .f32 neg_exp_f, result;\n\n // Check for zero\n setp.eq.u32 p_zero, $1, 0;\n\n // Compute 2^(127 - ue8m0) = 1 / 2^(ue8m0 - 127)\n sub.s32 neg_exp, 127, $1;\n cvt.rn.f32.s32 neg_exp_f, neg_exp;\n ex2.approx.f32 result, neg_exp_f;\n selp.f32 $0, 0f00000000, result, p_zero;\n }\n \"\"\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n# =============================================================================\n# E2M1 Conversion\n# =============================================================================\n\n\n@dsl_user_op\ndef cvt_e2m1x8_f32(\n v0: Float32,\n v1: Float32,\n v2: Float32,\n v3: Float32,\n v4: Float32,\n v5: Float32,\n v6: Float32,\n v7: Float32,\n *,\n loc=None,\n ip=None,\n) -> Uint32:\n \"\"\"Convert eight float32 values to eight E2M1 (4-bit) values packed into uint32.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [\n Float32(v0).ir_value(loc=loc, ip=ip),\n Float32(v1).ir_value(loc=loc, ip=ip),\n Float32(v2).ir_value(loc=loc, ip=ip),\n Float32(v3).ir_value(loc=loc, ip=ip),\n Float32(v4).ir_value(loc=loc, ip=ip),\n Float32(v5).ir_value(loc=loc, ip=ip),\n Float32(v6).ir_value(loc=loc, ip=ip),\n Float32(v7).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b8 byte0, byte1, byte2, byte3;\n cvt.rn.satfinite.e2m1x2.f32 byte0, $2, $1;\n cvt.rn.satfinite.e2m1x2.f32 byte1, $4, $3;\n cvt.rn.satfinite.e2m1x2.f32 byte2, $6, $5;\n cvt.rn.satfinite.e2m1x2.f32 byte3, $8, $7;\n mov.b32 $0, {byte0, byte1, byte2, byte3};\n }\n \"\"\",\n \"=r,f,f,f,f,f,f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n# =============================================================================\n# Warp, Block, and Cluster Reduction Utilities\n# =============================================================================\n\n\n@cute.jit\ndef warp_reduce(val, op, width: cutlass.Constexpr[int] = 32):\n \"\"\"Reduce across threads in a warp using butterfly shuffle.\"\"\"\n if cutlass.const_expr(isinstance(val, cute.TensorSSA)):\n res = cute.make_rmem_tensor(val.shape, val.dtype)\n res.store(val)\n for i in cutlass.range_constexpr(cute.size(val.shape)):\n res[i] = warp_reduce(res[i], op, width)\n return res.load()\n else:\n for i in cutlass.range_constexpr(int(math.log2(width))):\n val = op(val, cute.arch.shuffle_sync_bfly(val, offset=1 << i))\n return val\n\n\n@cute.jit\ndef block_reduce(\n val: Float32,\n op: Callable,\n reduction_buffer: cute.Tensor,\n init_val: Float32,\n) -> Float32:\n \"\"\"Block reduction across multiple warps using shared memory.\"\"\"\n lane_idx = cute.arch.lane_idx()\n warp_idx = cute.arch.warp_idx()\n warps_per_row = cute.size(reduction_buffer.shape[1])\n row_idx = warp_idx // warps_per_row\n col_idx = warp_idx % warps_per_row\n\n if lane_idx == 0:\n reduction_buffer[row_idx, col_idx] = val\n cute.arch.barrier()\n\n block_reduce_val = init_val\n if lane_idx < warps_per_row:\n block_reduce_val = reduction_buffer[row_idx, lane_idx]\n return warp_reduce(block_reduce_val, op)\n\n\n@cute.jit\ndef cluster_reduce(\n val: Float32,\n op: Callable,\n reduction_buffer: cute.Tensor,\n mbar_ptr: cute.Pointer,\n cluster_n: cutlass.Constexpr[int],\n init_val: Float32,\n) -> Float32:\n \"\"\"Cluster reduction across multiple CTAs using mbarrier.\"\"\"\n cta_rank_in_cluster = cute.arch.block_idx_in_cluster()\n lane_idx = cute.arch.lane_idx()\n warp_idx = cute.arch.warp_idx()\n\n rows_per_block = reduction_buffer.shape[0]\n warps_per_row = reduction_buffer.shape[1][0]\n\n row_idx = warp_idx // warps_per_row\n col_idx = warp_idx % warps_per_row\n\n # Warp 0 sets up mbarrier transaction count\n if warp_idx == 0:\n with cute.arch.elect_one():\n num_warps = rows_per_block * warps_per_row\n expected_bytes = num_warps * cluster_n * 4\n cute.arch.mbarrier_arrive_and_expect_tx(mbar_ptr, expected_bytes)\n\n # Each lane < cluster_n writes to a different CTA's shared memory\n if lane_idx < cluster_n:\n store_shared_remote(\n val,\n elem_pointer(reduction_buffer, (row_idx, (col_idx, cta_rank_in_cluster))),\n mbar_ptr,\n peer_cta_rank_in_cluster=lane_idx,\n )\n\n # Wait for all cluster writes\n cute.arch.mbarrier_wait(mbar_ptr, phase=0)\n\n # Reduce across all values\n num_total = warps_per_row * cluster_n\n num_iter = cute.ceil_div(num_total, 32)\n\n block_reduce_val = init_val\n for i in cutlass.range_constexpr(num_iter):\n idx = lane_idx + i * 32\n if idx < num_total:\n block_reduce_val = op(block_reduce_val, reduction_buffer[row_idx, idx])\n\n return warp_reduce(block_reduce_val, op)\n\n\n@cute.jit\ndef row_reduce(\n x: cute.TensorSSA,\n op: cute.ReductionOp,\n threads_per_row: cutlass.Constexpr[int],\n reduction_buffer: cute.Tensor,\n mbar_ptr,\n cluster_n: cutlass.Constexpr[int],\n init_val: Float32,\n):\n \"\"\"Row reduction with optional cluster support.\"\"\"\n local_val = x.reduce(op, init_val=init_val, reduction_profile=0)\n\n warp_op = {\n cute.ReductionOp.ADD: operator.add,\n cute.ReductionOp.MAX: cute.arch.fmax,\n }[op]\n warp_width = min(threads_per_row, 32)\n warp_val = warp_reduce(local_val, warp_op, width=warp_width)\n\n warps_per_row = max(threads_per_row // 32, 1)\n\n if cutlass.const_expr(warps_per_row > 1 or cluster_n > 1):\n if cutlass.const_expr(cluster_n == 1):\n return block_reduce(warp_val, warp_op, reduction_buffer, init_val)\n else:\n return cluster_reduce(\n warp_val, warp_op, reduction_buffer, mbar_ptr, cluster_n, init_val\n )\n else:\n return warp_val\n\n\n# =============================================================================\n# Predicate Utility\n# =============================================================================\n\n\n@cute.jit\ndef predicate_k(tXcX: cute.Tensor, limit: int) -> cute.Tensor:\n \"\"\"Create predicate tensor for bounds checking.\"\"\"\n tXpX = cute.make_rmem_tensor(\n cute.make_layout(\n (\n cute.size(tXcX, mode=[0, 1]),\n cute.size(tXcX, mode=[1]),\n cute.size(tXcX, mode=[2]),\n ),\n stride=(cute.size(tXcX, mode=[2]), 0, 1),\n ),\n cutlass.Boolean,\n )\n for rest_v in cutlass.range_constexpr(tXpX.shape[0]):\n for rest_k in cutlass.range_constexpr(tXpX.shape[2]):\n tXpX[rest_v, 0, rest_k] = cute.elem_less(\n tXcX[(0, rest_v), 0, rest_k][1], limit\n )\n return tXpX\n\n\n# =============================================================================\n# Helper Functions for SF Block Processing (block_size=16)\n# =============================================================================\n\n\n@cute.jit\ndef load_8_half2(\n mX: cute.Tensor, mW: cute.Tensor, row_offset: Int32, col_offset: Int32, H: int\n):\n \"\"\"Load 16 elements (8 half2 pairs) of X and W from global memory.\n\n Returns:\n x_h2: rmem_tensor of shape (8,) containing X as half2\n w_h2: rmem_tensor of shape (8,) containing W as half2\n \"\"\"\n x_h2 = cute.make_rmem_tensor((8,), Uint32)\n w_h2 = cute.make_rmem_tensor((8,), Uint32)\n\n # Load X (2 x 128-bit loads = 16 elements)\n x_ptr0 = get_ptr_as_int64(mX, row_offset * H + col_offset)\n x_ptr1 = get_ptr_as_int64(mX, row_offset * H + col_offset + Int32(8))\n x_h2[0], x_h2[1], x_h2[2], x_h2[3] = ld_global_v4_u32(x_ptr0)\n x_h2[4], x_h2[5], x_h2[6], x_h2[7] = ld_global_v4_u32(x_ptr1)\n\n # Load W (2 x 128-bit loads = 16 elements)\n w_ptr0 = get_ptr_as_int64(mW, col_offset)\n w_ptr1 = get_ptr_as_int64(mW, col_offset + Int32(8))\n w_h2[0], w_h2[1], w_h2[2], w_h2[3] = ld_global_v4_u32(w_ptr0)\n w_h2[4], w_h2[5], w_h2[6], w_h2[7] = ld_global_v4_u32(w_ptr1)\n\n return x_h2, w_h2\n\n\n@cute.jit\ndef half2_mul_8(x_h2: cute.Tensor, w_h2: cute.Tensor) -> cute.Tensor:\n \"\"\"Multiply 8 half2 pairs element-wise.\"\"\"\n xw_h2 = cute.make_rmem_tensor((8,), Uint32)\n for i in cutlass.range_constexpr(8):\n xw_h2[i] = half2_mul(x_h2[i], w_h2[i])\n return xw_h2\n\n\n@cute.jit\ndef bfloat2_mul_8(x_h2: cute.Tensor, w_h2: cute.Tensor) -> cute.Tensor:\n \"\"\"Multiply 8 bfloat2 pairs element-wise.\"\"\"\n xw_h2 = cute.make_rmem_tensor((8,), Uint32)\n for i in cutlass.range_constexpr(8):\n xw_h2[i] = bfloat2_mul(x_h2[i], w_h2[i])\n return xw_h2\n\n\n@cute.jit\ndef half2_max_abs_8(xw_h2: cute.Tensor) -> Uint32:\n \"\"\"Compute max absolute value across 8 half2 values using tree reduction.\"\"\"\n # Compute abs for all 8 values\n abs_h2 = cute.make_rmem_tensor((8,), Uint32)\n for i in cutlass.range_constexpr(8):\n abs_h2[i] = habs2(xw_h2[i])\n\n # Tree reduction: 8 -> 4 -> 2 -> 1\n max_01 = hmax2(abs_h2[0], abs_h2[1])\n max_23 = hmax2(abs_h2[2], abs_h2[3])\n max_45 = hmax2(abs_h2[4], abs_h2[5])\n max_67 = hmax2(abs_h2[6], abs_h2[7])\n max_0123 = hmax2(max_01, max_23)\n max_4567 = hmax2(max_45, max_67)\n return hmax2(max_0123, max_4567)\n\n\n@cute.jit\ndef bfloat2_max_abs_8(xw_h2: cute.Tensor) -> Uint32:\n \"\"\"Compute max absolute value across 8 bfloat2 values using tree reduction.\"\"\"\n # Compute abs for all 8 values\n abs_h2 = cute.make_rmem_tensor((8,), Uint32)\n for i in cutlass.range_constexpr(8):\n abs_h2[i] = bfloat2_habs2(xw_h2[i])\n\n # Tree reduction: 8 -> 4 -> 2 -> 1\n max_01 = bfloat2_hmax2(abs_h2[0], abs_h2[1])\n max_23 = bfloat2_hmax2(abs_h2[2], abs_h2[3])\n max_45 = bfloat2_hmax2(abs_h2[4], abs_h2[5])\n max_67 = bfloat2_hmax2(abs_h2[6], abs_h2[7])\n max_0123 = bfloat2_hmax2(max_01, max_23)\n max_4567 = bfloat2_hmax2(max_45, max_67)\n return bfloat2_hmax2(max_0123, max_4567)\n\n\n@cute.jit\ndef half2_to_float16(xw_h2: cute.Tensor, scale: Float32) -> cute.Tensor:\n \"\"\"Convert 8 half2 to 16 float32 with scaling.\"\"\"\n y_f32 = cute.make_rmem_tensor((16,), Float32)\n for i in cutlass.range_constexpr(8):\n y_f32[i * 2], y_f32[i * 2 + 1] = half2_to_float2_scaled(xw_h2[i], scale)\n return y_f32\n\n\n@cute.jit\ndef bfloat2_to_float16(xw_h2: cute.Tensor, scale: Float32) -> cute.Tensor:\n \"\"\"Convert 8 bfloat2 to 16 float32 with scaling.\"\"\"\n y_f32 = cute.make_rmem_tensor((16,), Float32)\n for i in cutlass.range_constexpr(8):\n y_f32[i * 2], y_f32[i * 2 + 1] = bfloat2_to_float2_scaled(xw_h2[i], scale)\n return y_f32\n\n\n@cute.jit\ndef quantize_and_pack_16(y_f32: cute.Tensor, inv_scale: Float32) -> Uint64:\n \"\"\"Quantize 16 float32 values to FP4 and pack into uint64.\"\"\"\n # Scale values\n q = cute.make_rmem_tensor((16,), Float32)\n for i in cutlass.range_constexpr(16):\n q[i] = y_f32[i] * inv_scale\n\n # Convert to E2M1 and pack\n packed_lo = cvt_e2m1x8_f32(q[0], q[1], q[2], q[3], q[4], q[5], q[6], q[7])\n packed_hi = cvt_e2m1x8_f32(q[8], q[9], q[10], q[11], q[12], q[13], q[14], q[15])\n return (Uint64(packed_hi) << Uint64(32)) | Uint64(packed_lo)\n\n\n# =============================================================================\n# Helper Functions for Float32 SF Block Processing\n# =============================================================================\n\n\n@cute.jit\ndef load_f32_16_from_smem(\n sH: cute.Tensor, row_idx: Int32, col_offset: Int32\n) -> cute.Tensor:\n \"\"\"Load 16 Float32 values from shared memory.\"\"\"\n h_f32 = cute.make_rmem_tensor((16,), Float32)\n for i in cutlass.range_constexpr(16):\n h_f32[i] = Float32(sH[row_idx, col_offset + i])\n return h_f32\n\n\n@cute.jit\ndef compute_y_and_max_abs_f32(\n h_f32: cute.Tensor, w_f32: cute.Tensor, rstd: Float32\n) -> Tuple[cute.Tensor, Float32]:\n \"\"\"Compute y = h * rstd * w and max_abs for 16 Float32 values.\"\"\"\n y_f32 = cute.make_rmem_tensor((16,), Float32)\n\n # Compute y and track max_abs\n y_f32[0] = h_f32[0] * rstd * w_f32[0]\n max_abs = fabs_f32(y_f32[0])\n\n for i in cutlass.range_constexpr(1, 16):\n y_f32[i] = h_f32[i] * rstd * w_f32[i]\n max_abs = fmax_f32(max_abs, fabs_f32(y_f32[i]))\n\n return y_f32, max_abs\n\n\n# =============================================================================\n# PTX intrinsics used by SM120 MoE kernels\n# =============================================================================\n\n\n@dsl_user_op\ndef st_global_f32(base_ptr: Int64, value: Float32, *, loc=None, ip=None):\n \"\"\"Store 32-bit float to global memory.\"\"\"\n llvm.inline_asm(\n None,\n [\n Int64(base_ptr).ir_value(loc=loc, ip=ip),\n Float32(value).ir_value(loc=loc, ip=ip),\n ],\n \"st.global.f32 [$0], $1;\",\n \"l,f\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n\n\n@dsl_user_op\ndef st_global_i32(addr: Int64, val: Int32, *, loc=None, ip=None):\n \"\"\"Store int32 to global memory.\"\"\"\n llvm.inline_asm(\n None,\n [\n Int64(addr).ir_value(loc=loc, ip=ip),\n Int32(val).ir_value(loc=loc, ip=ip),\n ],\n \"st.global.s32 [$0], $1;\",\n \"l,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n\n\n@dsl_user_op\ndef st_global_v4_u32(\n base_ptr: Int64,\n v0: Uint32,\n v1: Uint32,\n v2: Uint32,\n v3: Uint32,\n *,\n loc=None,\n ip=None,\n):\n \"\"\"Store 128 bits to global memory as four uint32 words.\"\"\"\n llvm.inline_asm(\n None,\n [\n Int64(base_ptr).ir_value(loc=loc, ip=ip),\n Uint32(v0).ir_value(loc=loc, ip=ip),\n Uint32(v1).ir_value(loc=loc, ip=ip),\n Uint32(v2).ir_value(loc=loc, ip=ip),\n Uint32(v3).ir_value(loc=loc, ip=ip),\n ],\n \"st.global.v4.u32 [$0], {$1, $2, $3, $4};\",\n \"l,r,r,r,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n\n# =============================================================================\n# PTX Intrinsics — Shared Memory Operations\n# =============================================================================\n\n\n@dsl_user_op\ndef shared_ptr_to_u32(ptr: cute.Pointer, *, loc=None, ip=None) -> Int32:\n \"\"\"Convert an address-space-3 shared-memory pointer to a u32 address.\"\"\"\n return Int32(llvm.ptrtoint(T.i32(), ptr.llvm_ptr, loc=loc, ip=ip))\n\n\n@dsl_user_op\ndef ld_shared_i32_relaxed(addr: Int32, *, loc=None, ip=None) -> Int32:\n \"\"\"Load int32 from shared memory when CSE/reordering is acceptable.\"\"\"\n return Int32(\n llvm.inline_asm(\n T.i32(),\n [Int32(addr).ir_value(loc=loc, ip=ip)],\n \"ld.shared.s32 $0, [$1];\",\n \"=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef st_shared_i32(addr: Int32, val: Int32, *, loc=None, ip=None):\n \"\"\"Store int32 to shared memory at a 32-bit byte address.\"\"\"\n llvm.inline_asm(\n None,\n [\n Int32(addr).ir_value(loc=loc, ip=ip),\n Int32(val).ir_value(loc=loc, ip=ip),\n ],\n \"st.shared.s32 [$0], $1;\",\n \"r,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n\n@dsl_user_op\ndef ld_shared_f32(addr: Int32, *, loc=None, ip=None) -> Float32:\n \"\"\"Load float32 from shared memory at a 32-bit byte address.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Int32(addr).ir_value(loc=loc, ip=ip)],\n \"ld.shared.f32 $0, [$1];\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef st_shared_f32(addr: Int32, val: Float32, *, loc=None, ip=None):\n \"\"\"Store float32 to shared memory at a 32-bit byte address.\"\"\"\n llvm.inline_asm(\n None,\n [\n Int32(addr).ir_value(loc=loc, ip=ip),\n Float32(val).ir_value(loc=loc, ip=ip),\n ],\n \"st.shared.f32 [$0], $1;\",\n \"r,f\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n\n@dsl_user_op\ndef st_shared_u8(smem_addr: Int32, value: Uint8, *, loc=None, ip=None):\n \"\"\"Store 8 bits to shared memory. smem_addr is a u32 shared-memory address.\"\"\"\n llvm.inline_asm(\n None,\n [\n Int32(smem_addr).ir_value(loc=loc, ip=ip),\n Uint8(value).ir_value(loc=loc, ip=ip),\n ],\n \"st.shared.u8 [$0], $1;\",\n \"r,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n\n\n# =============================================================================\n# PTX Intrinsics — Global Atomics\n# =============================================================================\n\n\n@dsl_user_op\ndef atomic_add_global_i32(addr: Int64, val: Int32, *, loc=None, ip=None) -> Int32:\n \"\"\"Global memory int32 atomic add. Returns old value.\"\"\"\n return Int32(\n llvm.inline_asm(\n T.i32(),\n [\n Int64(addr).ir_value(loc=loc, ip=ip),\n Int32(val).ir_value(loc=loc, ip=ip),\n ],\n \"atom.global.add.s32 $0, [$1], $2;\",\n \"=r,l,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef atomic_cas_global_i32(\n addr: Int64, compare: Int32, value: Int32, *, loc=None, ip=None\n) -> Int32:\n \"\"\"Global memory int32 atomic compare-and-swap. Returns old value.\"\"\"\n return Int32(\n llvm.inline_asm(\n T.i32(),\n [\n Int64(addr).ir_value(loc=loc, ip=ip),\n Int32(compare).ir_value(loc=loc, ip=ip),\n Int32(value).ir_value(loc=loc, ip=ip),\n ],\n \"atom.global.cas.b32 $0, [$1], $2, $3;\",\n \"=r,l,r,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef ld_global_acquire_i32(addr: Int64, *, loc=None, ip=None) -> Int32:\n \"\"\"Load int32 from global memory with acquire semantics.\"\"\"\n return Int32(\n llvm.inline_asm(\n T.i32(),\n [Int64(addr).ir_value(loc=loc, ip=ip)],\n \"ld.global.acquire.gpu.s32 $0, [$1];\",\n \"=r,l\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef st_global_release_i32(addr: Int64, val: Int32, *, loc=None, ip=None):\n \"\"\"Store int32 to global memory with release semantics.\"\"\"\n llvm.inline_asm(\n None,\n [\n Int64(addr).ir_value(loc=loc, ip=ip),\n Int32(val).ir_value(loc=loc, ip=ip),\n ],\n \"st.global.release.gpu.s32 [$0], $1;\",\n \"l,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n\n@dsl_user_op\ndef spin_wait_global_eq_i32(addr: Int64, expected: Int32, *, loc=None, ip=None):\n \"\"\"Spin while *addr == expected, then continue with acquire semantics.\"\"\"\n llvm.inline_asm(\n None,\n [\n Int64(addr).ir_value(loc=loc, ip=ip),\n Int32(expected).ir_value(loc=loc, ip=ip),\n ],\n \"{\\n\"\n \".reg .pred %p0;\\n\"\n \".reg .s32 %val;\\n\"\n \"spin_loop:\\n\"\n \" ld.global.acquire.gpu.s32 %val, [$0];\\n\"\n \" setp.eq.s32 %p0, %val, $1;\\n\"\n \" @%p0 bra spin_loop;\\n\"\n \"}\",\n \"l,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n\n@dsl_user_op\ndef threadfence(*, loc=None, ip=None):\n \"\"\"Emit a global-memory fence.\"\"\"\n llvm.inline_asm(\n None,\n [],\n \"membar.gl;\",\n \"\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n\n# =============================================================================\n# PTX Intrinsics — Scatter Atomics (BF16)\n# =============================================================================\n\n\n@dsl_user_op\ndef scatter_add_bf16x2(addr: Int64, val0_f32, val1_f32, *, loc=None, ip=None):\n \"\"\"BF16x2 atomic reduction add to global memory.\n\n Packs two f32 values into bf16x2 via cvt.rn.satfinite, then does\n red.relaxed.gpu.global.add.noftz.bf16x2.\n \"\"\"\n llvm.inline_asm(\n None,\n [\n Int64(addr).ir_value(loc=loc, ip=ip),\n val0_f32.ir_value(loc=loc, ip=ip),\n val1_f32.ir_value(loc=loc, ip=ip),\n ],\n \"{ .reg .b32 packed;\"\n \" cvt.rn.satfinite.bf16x2.f32 packed, $2, $1;\"\n \" red.relaxed.gpu.global.add.noftz.bf16x2 [$0], packed; }\",\n \"l,f,f\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n\n\n@dsl_user_op\ndef scatter_add_v4_bf16x2(\n addr: Int64, v0, v1, v2, v3, v4, v5, v6, v7, *, loc=None, ip=None\n):\n \"\"\"Vectorized BF16x2 atomic reduction of 8 f32 values.\"\"\"\n llvm.inline_asm(\n None,\n [\n Int64(addr).ir_value(loc=loc, ip=ip),\n v0.ir_value(loc=loc, ip=ip),\n v1.ir_value(loc=loc, ip=ip),\n v2.ir_value(loc=loc, ip=ip),\n v3.ir_value(loc=loc, ip=ip),\n v4.ir_value(loc=loc, ip=ip),\n v5.ir_value(loc=loc, ip=ip),\n v6.ir_value(loc=loc, ip=ip),\n v7.ir_value(loc=loc, ip=ip),\n ],\n \"{ .reg .b32 p0,p1,p2,p3;\"\n \" cvt.rn.satfinite.bf16x2.f32 p0, $2, $1;\"\n \" cvt.rn.satfinite.bf16x2.f32 p1, $4, $3;\"\n \" cvt.rn.satfinite.bf16x2.f32 p2, $6, $5;\"\n \" cvt.rn.satfinite.bf16x2.f32 p3, $8, $7;\"\n \" red.global.add.noftz.v4.bf16x2 [$0], {p0, p1, p2, p3}; }\",\n \"l,f,f,f,f,f,f,f,f\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n\n# =============================================================================\n# FP8 Conversion — Non-reciprocal version\n# =============================================================================\n\n\n@dsl_user_op\ndef fp8_e4m3_to_f32(fp8_val: Uint32, *, loc=None, ip=None) -> Float32:\n \"\"\"Convert FP8 E4M3 to float32.\n\n Uses the hardware conversion instruction, which is exact for every\n finite e4m3 value, including subnormals, and matches how the tensor\n core decodes the same byte.\n \"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Uint32(fp8_val).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 fp8_pair;\n .reg .b32 h2_32;\n .reg .b16 h_lo, h_hi;\n\n cvt.u16.u32 fp8_pair, $1;\n cvt.rn.f16x2.e4m3x2 h2_32, fp8_pair;\n mov.b32 {h_lo, h_hi}, h2_32;\n cvt.f32.f16 $0, h_lo;\n }\n \"\"\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef nvfp4_scale_from_amax(\n block_amax: Float32, global_scale: Float32, *, loc=None, ip=None\n) -> Float32:\n \"\"\"Compute the NVFP4 block scale from an amax and global scale.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [\n Float32(block_amax).ir_value(loc=loc, ip=ip),\n Float32(global_scale).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .f64 amax_d, gs_d, q_d, six_d;\n cvt.f64.f32 amax_d, $1;\n cvt.f64.f32 gs_d, $2;\n mov.f64 six_d, 0d4018000000000000;\n mul.rn.f64 q_d, amax_d, gs_d;\n div.rn.f64 q_d, q_d, six_d;\n cvt.rn.f32.f64 $0, q_d;\n }\n \"\"\",\n \"=f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef nvfp4_scale_from_amax_rn(\n block_amax: Float32, global_scale: Float32, *, loc=None, ip=None\n) -> Float32:\n \"\"\"Compute NVFP4 block scale with round-to-nearest FP32 operations.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [\n Float32(block_amax).ir_value(loc=loc, ip=ip),\n Float32(global_scale).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .pred p_zero;\n .reg .f32 scale_mul, result;\n setp.eq.f32 p_zero, $1, 0f00000000;\n mul.rn.f32 scale_mul, $2, 0f3E2AAAAB;\n mul.rn.f32 result, $1, scale_mul;\n selp.f32 $0, 0f00000000, result, p_zero;\n }\n \"\"\",\n \"=f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef cvt_e4m3x2_to_f16x2_pair(\n packed_u32: Uint32, *, loc=None, ip=None\n) -> Tuple[Uint32, Uint32]:\n \"\"\"Decode 4 packed E4M3 bytes into two f16x2 registers.\"\"\"\n res = llvm.inline_asm(\n ir.Type.parse(\"!llvm.struct<(i32, i32)>\"),\n [Uint32(packed_u32).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 b16_01, b16_23;\n .reg .b32 hi32;\n cvt.u16.u32 b16_01, $2;\n shr.b32 hi32, $2, 16;\n cvt.u16.u32 b16_23, hi32;\n cvt.rn.f16x2.e4m3x2 $0, b16_01;\n cvt.rn.f16x2.e4m3x2 $1, b16_23;\n }\n \"\"\",\n \"=r,=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n return (\n Uint32(llvm.extractvalue(T.i32(), res, [0], loc=loc, ip=ip)),\n Uint32(llvm.extractvalue(T.i32(), res, [1], loc=loc, ip=ip)),\n )\n\n\n@dsl_user_op\ndef f16x2_to_f32x2(packed_h2: Uint32, *, loc=None, ip=None) -> Tuple[Float32, Float32]:\n \"\"\"Unpack one f16x2 register into two f32 values.\"\"\"\n res = llvm.inline_asm(\n ir.Type.parse(\"!llvm.struct<(f32, f32)>\"),\n [Uint32(packed_h2).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 lo, hi;\n mov.b32 {lo, hi}, $2;\n cvt.f32.f16 $0, lo;\n cvt.f32.f16 $1, hi;\n }\n \"\"\",\n \"=f,=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n return (\n Float32(llvm.extractvalue(T.f32(), res, [0], loc=loc, ip=ip)),\n Float32(llvm.extractvalue(T.f32(), res, [1], loc=loc, ip=ip)),\n )\n\n\n@dsl_user_op\ndef cvt_e4m3_to_f32_via_f16(fp8_val: Uint32, *, loc=None, ip=None) -> Float32:\n \"\"\"Convert one E4M3 byte to f32 through native E4M3-to-f16 conversion.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Uint32(fp8_val).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 fp8_pair;\n .reg .b32 h2;\n .reg .b16 lo, hi;\n cvt.u16.u32 fp8_pair, $1;\n cvt.rn.f16x2.e4m3x2 h2, fp8_pair;\n mov.b32 {lo, hi}, h2;\n cvt.f32.f16 $0, lo;\n }\n \"\"\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef cvt_s0e5m3_to_f16x2_broadcast(fp8_val: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Convert one S0E5M3 scale byte to an f16x2 with the scale in both lanes.\n\n S0E5M3 (sign-0, 5-exp, 3-mantissa) is a host-side reformat of the per-block\n E4M3 scale, rebiased to fp16's bias (exp 7->15, i.e. byte += 0x40) so the\n bits line up with fp16 directly: ``f16(byte) = byte << 7`` (exp -> bits 14-10,\n the 3 mantissa bits -> bits 9-7, low mantissa and sign = 0). Broadcasting to\n both f16x2 lanes is then ``byte * 0x00800080`` = ``(byte<<7) | (byte<<23)`` --\n a single ``mul.lo.u32`` (the two shifted copies never overlap, so the mul is\n exactly the OR). Replaces the 3-op E4M3 path (cvt.u16 + cvt.f16x2.e4m3x2 +\n prmt) with 1 op, and the per-block scale stays 1 byte (memory-neutral).\n Numerically exact for normal E4M3 scales (both formats carry 3 mantissa bits).\n \"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(fp8_val).ir_value(loc=loc, ip=ip)],\n \"mul.lo.u32 $0, $1, 0x00800080;\",\n \"=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef fp4_decode_4bytes(\n packed_u32: Uint32, *, loc=None, ip=None\n) -> Tuple[Uint32, Uint32, Uint32, Uint32]:\n \"\"\"Decode 4 packed FP4 bytes into four f16x2 registers.\"\"\"\n res = llvm.inline_asm(\n ir.Type.parse(\"!llvm.struct<(i32, i32, i32, i32)>\"),\n [Uint32(packed_u32).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b8 byte0, byte1, byte2, byte3;\n mov.b32 {byte0, byte1, byte2, byte3}, $4;\n cvt.rn.f16x2.e2m1x2 $0, byte0;\n cvt.rn.f16x2.e2m1x2 $1, byte1;\n cvt.rn.f16x2.e2m1x2 $2, byte2;\n cvt.rn.f16x2.e2m1x2 $3, byte3;\n }\n \"\"\",\n \"=r,=r,=r,=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n return (\n Uint32(llvm.extractvalue(T.i32(), res, [0], loc=loc, ip=ip)),\n Uint32(llvm.extractvalue(T.i32(), res, [1], loc=loc, ip=ip)),\n Uint32(llvm.extractvalue(T.i32(), res, [2], loc=loc, ip=ip)),\n Uint32(llvm.extractvalue(T.i32(), res, [3], loc=loc, ip=ip)),\n )\n\n\n@dsl_user_op\ndef fp4_decode_2(byte_val: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Decode one FP4 byte into one f16x2 register.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(byte_val).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b8 b0;\n cvt.u8.u32 b0, $1;\n cvt.rn.f16x2.e2m1x2 $0, b0;\n }\n \"\"\",\n \"=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef cvt_fp32x2_to_e2m1x2(v0: Float32, v1: Float32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Convert two f32 values into one packed E2M1 byte.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [\n Float32(v0).ir_value(loc=loc, ip=ip),\n Float32(v1).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b8 b;\n cvt.rn.satfinite.e2m1x2.f32 b, $2, $1;\n cvt.u32.u8 $0, b;\n }\n \"\"\",\n \"=r,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@cute.jit\ndef quant_dequant_2(\n v0: Float32, v1: Float32, sf_f32: Float32, eff_scale: Float32\n) -> Tuple[Float32, Float32]:\n \"\"\"Quantize/dequantize two values through FP4.\"\"\"\n inv_scale = Float32(1.0) / eff_scale\n fp4_byte = cvt_fp32x2_to_e2m1x2(v0 * inv_scale, v1 * inv_scale)\n h2 = fp4_decode_2(fp4_byte)\n f0, f1 = f16x2_to_f32x2(h2)\n return f0 * sf_f32, f1 * sf_f32\n\n\n@dsl_user_op\ndef fp4_dot4_sum(\n u_packed: Uint32,\n x0: Uint32,\n x1: Uint32,\n x2: Uint32,\n x3: Uint32,\n *,\n loc=None,\n ip=None,\n) -> Float32:\n \"\"\"Decode 4 FP4 bytes and dot with four f16x2 inputs.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [\n Uint32(u_packed).ir_value(loc=loc, ip=ip),\n Uint32(x0).ir_value(loc=loc, ip=ip),\n Uint32(x1).ir_value(loc=loc, ip=ip),\n Uint32(x2).ir_value(loc=loc, ip=ip),\n Uint32(x3).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b8 b0, b1, b2, b3;\n .reg .b32 h0, h1, h2, h3;\n .reg .f16x2 acc;\n .reg .b16 lo, hi;\n .reg .f32 flo, fhi;\n mov.b32 {b0, b1, b2, b3}, $1;\n cvt.rn.f16x2.e2m1x2 h0, b0;\n cvt.rn.f16x2.e2m1x2 h1, b1;\n cvt.rn.f16x2.e2m1x2 h2, b2;\n cvt.rn.f16x2.e2m1x2 h3, b3;\n mov.b32 acc, 0;\n fma.rn.f16x2 acc, h0, $2, acc;\n fma.rn.f16x2 acc, h1, $3, acc;\n fma.rn.f16x2 acc, h2, $4, acc;\n fma.rn.f16x2 acc, h3, $5, acc;\n mov.b32 {lo, hi}, acc;\n cvt.f32.f16 flo, lo;\n cvt.f32.f16 fhi, hi;\n add.f32 $0, flo, fhi;\n }\n \"\"\",\n \"=f,r,r,r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef fp4_dot8_sum(\n u_a: Uint32,\n u_b: Uint32,\n x0: Uint32,\n x1: Uint32,\n x2: Uint32,\n x3: Uint32,\n x4: Uint32,\n x5: Uint32,\n x6: Uint32,\n x7: Uint32,\n *,\n loc=None,\n ip=None,\n) -> Float32:\n \"\"\"Decode 8 FP4 bytes and dot with eight f16x2 inputs.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [\n Uint32(u_a).ir_value(loc=loc, ip=ip),\n Uint32(u_b).ir_value(loc=loc, ip=ip),\n Uint32(x0).ir_value(loc=loc, ip=ip),\n Uint32(x1).ir_value(loc=loc, ip=ip),\n Uint32(x2).ir_value(loc=loc, ip=ip),\n Uint32(x3).ir_value(loc=loc, ip=ip),\n Uint32(x4).ir_value(loc=loc, ip=ip),\n Uint32(x5).ir_value(loc=loc, ip=ip),\n Uint32(x6).ir_value(loc=loc, ip=ip),\n Uint32(x7).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b8 a0, a1, a2, a3;\n .reg .b8 b0, b1, b2, b3;\n .reg .b32 h0, h1, h2, h3, h4, h5, h6, h7;\n .reg .f16x2 acc;\n .reg .b16 lo, hi;\n .reg .f32 flo, fhi;\n mov.b32 {a0, a1, a2, a3}, $1;\n mov.b32 {b0, b1, b2, b3}, $2;\n cvt.rn.f16x2.e2m1x2 h0, a0;\n cvt.rn.f16x2.e2m1x2 h1, a1;\n cvt.rn.f16x2.e2m1x2 h2, a2;\n cvt.rn.f16x2.e2m1x2 h3, a3;\n cvt.rn.f16x2.e2m1x2 h4, b0;\n cvt.rn.f16x2.e2m1x2 h5, b1;\n cvt.rn.f16x2.e2m1x2 h6, b2;\n cvt.rn.f16x2.e2m1x2 h7, b3;\n mov.b32 acc, 0;\n fma.rn.f16x2 acc, h0, $3, acc;\n fma.rn.f16x2 acc, h1, $4, acc;\n fma.rn.f16x2 acc, h2, $5, acc;\n fma.rn.f16x2 acc, h3, $6, acc;\n fma.rn.f16x2 acc, h4, $7, acc;\n fma.rn.f16x2 acc, h5, $8, acc;\n fma.rn.f16x2 acc, h6, $9, acc;\n fma.rn.f16x2 acc, h7, $10, acc;\n mov.b32 {lo, hi}, acc;\n cvt.f32.f16 flo, lo;\n cvt.f32.f16 fhi, hi;\n add.f32 $0, flo, fhi;\n }\n \"\"\",\n \"=f,r,r,r,r,r,r,r,r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@cute.jit\ndef _f16x2_dot_sum_f32acc(a_h2: Uint32, b_h2: Uint32) -> Float32:\n a0, a1 = f16x2_to_f32x2(a_h2)\n b0, b1 = f16x2_to_f32x2(b_h2)\n return a0 * b0 + a1 * b1\n\n\n@cute.jit\ndef fp4_dot4_sum_f32acc(\n u_packed: Uint32,\n x0: Uint32,\n x1: Uint32,\n x2: Uint32,\n x3: Uint32,\n) -> Float32:\n \"\"\"Decode FP4 then accumulate a 4-byte dot product in f32.\"\"\"\n h0, h1, h2, h3 = fp4_decode_4bytes(u_packed)\n return (\n _f16x2_dot_sum_f32acc(h0, x0)\n + _f16x2_dot_sum_f32acc(h1, x1)\n + _f16x2_dot_sum_f32acc(h2, x2)\n + _f16x2_dot_sum_f32acc(h3, x3)\n )\n\n\n@cute.jit\ndef fp4_dot8_sum_f32acc(\n u_a: Uint32,\n u_b: Uint32,\n x0: Uint32,\n x1: Uint32,\n x2: Uint32,\n x3: Uint32,\n x4: Uint32,\n x5: Uint32,\n x6: Uint32,\n x7: Uint32,\n) -> Float32:\n \"\"\"Decode FP4 then accumulate an 8-byte dot product in f32.\"\"\"\n h0, h1, h2, h3 = fp4_decode_4bytes(u_a)\n h4, h5, h6, h7 = fp4_decode_4bytes(u_b)\n return (\n _f16x2_dot_sum_f32acc(h0, x0)\n + _f16x2_dot_sum_f32acc(h1, x1)\n + _f16x2_dot_sum_f32acc(h2, x2)\n + _f16x2_dot_sum_f32acc(h3, x3)\n + _f16x2_dot_sum_f32acc(h4, x4)\n + _f16x2_dot_sum_f32acc(h5, x5)\n + _f16x2_dot_sum_f32acc(h6, x6)\n + _f16x2_dot_sum_f32acc(h7, x7)\n )\n\n\n@dsl_user_op\ndef pack_f32x2_to_f16x2(a: Float32, b: Float32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Pack two f32 values into one f16x2 register.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [\n Float32(a).ir_value(loc=loc, ip=ip),\n Float32(b).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b16 lo, hi;\n cvt.rn.f16.f32 lo, $1;\n cvt.rn.f16.f32 hi, $2;\n mov.b32 $0, {lo, hi};\n }\n \"\"\",\n \"=r,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n# =============================================================================\n# FP4 Quantization — Fast approximate path\n# =============================================================================\n\n\n@cute.jit\ndef quantize_and_pack_16_fast(y_f32: cute.Tensor, inv_scale: Float32) -> Uint64:\n \"\"\"Fast approximate FP4 quantize/pack for 16 float32 values.\"\"\"\n q = cute.make_rmem_tensor((16,), Float32)\n for i in cutlass.range_constexpr(16):\n q[i] = y_f32[i] * inv_scale\n\n packed_lo = cvt_e2m1x8_f32(q[0], q[1], q[2], q[3], q[4], q[5], q[6], q[7])\n packed_hi = cvt_e2m1x8_f32(q[8], q[9], q[10], q[11], q[12], q[13], q[14], q[15])\n return (Uint64(packed_hi) << Uint64(32)) | Uint64(packed_lo)\n\n\n# =============================================================================\n# FP4 Block Quantization Helpers (for MoE kernels)\n# =============================================================================\n\n\n@cute.jit\ndef quantize_block_fp4(\n values: cute.Tensor,\n max_abs: Float32,\n global_scale_val: Float32,\n) -> Tuple[Uint64, Uint8]:\n \"\"\"Quantize 16 float32 values to packed FP4 + e4m3 scale byte.\n\n Given 16 values and their pre-computed max_abs, derives the NVFP4 block\n scale, quantizes to FP4, and packs into a uint64. Returns\n (packed_fp4_u64, scale_byte).\n \"\"\"\n scale_float = max_abs / (Float32(FLOAT4_E2M1_MAX) * global_scale_val)\n scale_float = fmin_f32(scale_float, Float32(FLOAT8_E4M3_MAX))\n scale_u32 = cvt_f32_to_e4m3(scale_float)\n scale_byte = Uint8(scale_u32 & Uint32(0xFF))\n quantized_scale = fp8_e4m3_to_f32(scale_u32)\n packed64 = Uint64(0)\n if quantized_scale != Float32(0.0) and global_scale_val != Float32(0.0):\n # 1/(qs*gs): precise counterpart of the fast path's rcp(qs)*rcp(gs).\n packed64 = quantize_and_pack_16(\n values, Float32(1.0) / (quantized_scale * global_scale_val)\n )\n return packed64, scale_byte\n\n\n@cute.jit\ndef quantize_block_fp4_fast(\n values: cute.Tensor,\n max_abs: Float32,\n global_scale_val: Float32,\n) -> Tuple[Uint64, Uint8]:\n \"\"\"Fast approximate FP4 block quantization using reciprocal/vector path.\"\"\"\n scale_u32 = Uint32(0)\n scale_byte = Uint8(0)\n packed64 = Uint64(0)\n if global_scale_val != Float32(0.0):\n fp4_max_rcp = rcp_approx_ftz(Float32(FLOAT4_E2M1_MAX))\n gs_recip = rcp_approx_ftz(global_scale_val)\n scale_float = gs_recip * (max_abs * fp4_max_rcp)\n scale_float = fmin_f32(scale_float, Float32(FLOAT8_E4M3_MAX))\n scale_u32 = cvt_f32_to_e4m3(scale_float)\n scale_byte = Uint8(scale_u32 & Uint32(0xFF))\n inv_quantized_scale = fp8_e4m3_to_f32_and_rcp(scale_u32)\n if inv_quantized_scale != Float32(0.0):\n packed64 = quantize_and_pack_16_fast(values, inv_quantized_scale * gs_recip)\n return packed64, scale_byte\n\n\n@cute.jit\ndef max_abs_16(values: cute.Tensor) -> Float32:\n \"\"\"Compute the maximum absolute value of 16 float32 values.\"\"\"\n result = fabs_f32(values[0])\n for i in cutlass.range_constexpr(1, 16):\n result = fmax_f32(result, fabs_f32(values[i]))\n return result\n\n\n@cute.jit\ndef silu_mul_16(\n gate: cute.Tensor,\n up: cute.Tensor,\n) -> cute.Tensor:\n \"\"\"Fused SiLU(gate) * up for 16 float32 element pairs.\n\n Used in MoE kernel epilogue to fuse the activation function\n between GEMM1 and GEMM2, avoiding the gmem round-trip.\n \"\"\"\n out = cute.make_rmem_tensor((16,), Float32)\n for i in cutlass.range_constexpr(16):\n g = gate[i]\n sigmoid_g = cute.arch.rcp_approx(\n Float32(1.0) + cute.math.exp(-g, fastmath=False)\n )\n out[i] = g * sigmoid_g * up[i]\n return out\n\n\n@cute.jit\ndef silu_mul_quantize_block_fp4(\n gate: cute.Tensor,\n up: cute.Tensor,\n global_scale_val: Float32,\n) -> Tuple[Uint64, Uint8]:\n \"\"\"Fused SiLU(gate)*up + FP4 quantize for 16 element pairs.\"\"\"\n activated = silu_mul_16(gate, up)\n block_max = max_abs_16(activated)\n return quantize_block_fp4(activated, block_max, global_scale_val)\n\n\n# =============================================================================\n# ReLU2 Activation — ReLU(x)² for non-gated MoE (Nemotron-Super)\n# =============================================================================\n\n\n@cute.jit\ndef relu2_16(x: cute.Tensor) -> cute.Tensor:\n \"\"\"Compute ReLU²(x) = max(0, x)² for 16 float32 values.\"\"\"\n out = cute.make_rmem_tensor((16,), Float32)\n for i in cutlass.range_constexpr(16):\n v = fmax_f32(x[i], Float32(0.0))\n out[i] = v * v\n return out\n\n\n@cute.jit\ndef relu2_quantize_block_fp4(\n x: cute.Tensor,\n global_scale_val: Float32,\n) -> Tuple[Uint64, Uint8]:\n \"\"\"Fused ReLU² + FP4 quantize for 16 float32 values.\"\"\"\n activated = relu2_16(x)\n block_max = max_abs_16(activated)\n return quantize_block_fp4(activated, block_max, global_scale_val)\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## 📌 Description\n\nSyncs the SM12x NVFP4 (W4A4) fused-MoE kernels behind `b12x_fused_moe` and `B12xMoEWrapper` with upstream [b12x](https://github.com/local-inference-lab/sparkinfer) at `f9be272`, reaching backend parity.\n\nThe module now has four kernels. `MoEDirectMicroKernel` takes the smallest decode batches, `MoEMicroKernel` and `MoEStaticKernel` cover the rest of decode with tile assignments fixed at launch, and `MoEDynamicKernel` covers prefill by distributing tiles through an in-kernel work queue.\n\nChanges:\n\n- Adopt upstream's current `MoEDirectMicroKernel`, replacing a stale copy in `moe_direct_micro_kernel.py` that was never routed to. It reads the top-k ids directly, so the smallest batches skip the routing pre-pass that dominates their runtime, and it now supports gelu_tanh.\n- Let `MoEDynamicKernel` use tiles smaller than 128 rows, so sparse routing stops padding every expert up to 128.\n- Launch all kernels cooperatively. They synchronize the whole grid between phases, which deadlocks if concurrent work keeps part of the grid off the GPU.\n- Simplify `MoEDynamicKernel`'s work queue and size its pipeline stages from the real shared-memory footprint.\n- Vectorize `MoEStaticKernel`'s scatter epilogue and refresh the decode tile heuristics.\n- Restrict the fast FP4 quantizer to gated activations, since relu2's squared outputs need the exact one.\n\nPublic API and behavior changes: none.\n\n## 📊 Performance\n\nVersus main, measured over 38 target-model MoE shapes on three GPUs. Geomean speedup per shape group:\n\n| shape group | DGX Spark | RTX 5080 | RTX Pro 6000 SE |\n|---|---|---|---|\n| decode, batch 1-2 | 1.06x | 1.30x | 1.40x |\n| decode, batch 4-40 | 1.00x | 1.00x | 1.00x |\n| prefill, batch 512-2048 | 1.10x | 1.10x | 1.09x |\n| prefill, batch 8192 | 1.00x | 1.00x | 1.00x |\n\n- The batch 1-2 gains come from the new `MoEDirectMicroKernel`; the shapes it serves win up to 2.3x.\n- The prefill gains come from `MoEDynamicKernel` picking tiles smaller than 128 rows; those shapes win up to 1.26x.\n\n## 🔍 Related Issues\n\n#4223 (item 2).\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n## 🧪 Tests\n\n- On SM121 (DGX Spark GB10): `tests/moe/test_b12x_fused_moe.py` (157 cases) and `tests/moe/test_unified_moe_b12x.py` (58 cases) pass, including tests that force each backend and a test that a smaller tile is picked again after a large-batch call.\n\n## Reviewer Notes\n\nDeviations from the b12x source, beyond import plumbing:\n\n- gelu_tanh added to `MoEDirectMicroKernel`, matching the activation coverage of the module's other kernels.\n- The module's API accepts reciprocal-form scales but upstream's kernel only takes multipliers, so dispatch inverts them before launch.\n- `MoEDirectMicroKernel`'s cutover is re-measured: upstream's only alternative is its counterpart of `MoEDynamicKernel`, while here it competes with `MoEMicroKernel` and `MoEStaticKernel`.\n- Upstream sizes scratch and builds the kernel together inside one plan object, so their tile sizes always match. FlashInfer has no plan object, so the workspace cache is keyed by tile size to give the same guarantee.\n\n🤖 Generated with [Claude Code](https://claude.com/claude-code)\n\n"},"gains":{"kind":"string","value":"[{\"scope\": \"e2e\", \"hardware\": \"DGX Spark\", \"model\": null, \"shape\": \"decode, batch 1-2\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.06, \"speedup\": 1.06}, {\"scope\": \"e2e\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"decode, batch 1-2\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.3, \"speedup\": 1.3}, {\"scope\": \"e2e\", \"hardware\": \"RTX Pro 6000 SE\", \"model\": null, \"shape\": \"decode, batch 1-2\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.4, \"speedup\": 1.4}, {\"scope\": \"e2e\", \"hardware\": \"DGX Spark\", \"model\": null, \"shape\": \"decode, batch 4-40\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.0, \"speedup\": 1.0}, {\"scope\": \"e2e\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"decode, batch 4-40\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.0, \"speedup\": 1.0}, {\"scope\": \"e2e\", \"hardware\": \"RTX Pro 6000 SE\", \"model\": null, \"shape\": \"decode, batch 4-40\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.0, \"speedup\": 1.0}, {\"scope\": \"e2e\", \"hardware\": \"DGX Spark\", \"model\": null, \"shape\": \"prefill, batch 512-2048\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.1, \"speedup\": 1.1}, {\"scope\": \"e2e\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"prefill, batch 512-2048\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.1, \"speedup\": 1.1}, {\"scope\": \"e2e\", \"hardware\": \"RTX Pro 6000 SE\", \"model\": null, \"shape\": \"prefill, batch 512-2048\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.09, \"speedup\": 1.09}, {\"scope\": \"e2e\", \"hardware\": \"DGX Spark\", \"model\": null, \"shape\": \"prefill, batch 8192\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.0, \"speedup\": 1.0}, {\"scope\": \"e2e\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"prefill, batch 8192\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.0, \"speedup\": 1.0}, {\"scope\": \"e2e\", \"hardware\": \"RTX Pro 6000 SE\", \"model\": null, \"shape\": \"prefill, batch 8192\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.0, \"speedup\": 1.0}]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"number","value":1.03,"string":"1.03"}}},{"rowIdx":1098,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"5a4b54bed1dfe6f112cd4ec9bc196da517369f46"},"date":{"kind":"string","value":"2026-08-03T14:43:37-07:00"},"pr_number":{"kind":"number","value":4285,"string":"4,285"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/4285"},"title":{"kind":"string","value":"perf(moe): sync SM12x NVFP4 fused-MoE kernels to b12x HEAD (#4285)"},"message":{"kind":"string","value":"perf(moe): sync SM12x NVFP4 fused-MoE kernels to b12x HEAD (#4285)\n\n## 📌 Description\n\nSyncs the SM12x NVFP4 (W4A4) fused-MoE kernels behind `b12x_fused_moe`\nand `B12xMoEWrapper` with upstream\n[b12x](https://github.com/local-inference-lab/sparkinfer) at `f9be272`,\nreaching backend parity.\n\nThe module now has four kernels. `MoEDirectMicroKernel` takes the\nsmallest decode batches, `MoEMicroKernel` and `MoEStaticKernel` cover\nthe rest of decode with tile assignments fixed at launch, and\n`MoEDynamicKernel` covers prefill by distributing tiles through an\nin-kernel work queue.\n\nChanges:\n\n- Adopt upstream's current `MoEDirectMicroKernel`, replacing a stale\ncopy in `moe_direct_micro_kernel.py` that was never routed to. It reads\nthe top-k ids directly, so the smallest batches skip the routing\npre-pass that dominates their runtime, and it now supports gelu_tanh.\n- Let `MoEDynamicKernel` use tiles smaller than 128 rows, so sparse\nrouting stops padding every expert up to 128.\n- Launch all kernels cooperatively. They synchronize the whole grid\nbetween phases, which deadlocks if concurrent work keeps part of the\ngrid off the GPU.\n- Simplify `MoEDynamicKernel`'s work queue and size its pipeline stages\nfrom the real shared-memory footprint.\n- Vectorize `MoEStaticKernel`'s scatter epilogue and refresh the decode\ntile heuristics.\n- Restrict the fast FP4 quantizer to gated activations, since relu2's\nsquared outputs need the exact one.\n\nPublic API and behavior changes: none.\n\n## 📊 Performance\n\nVersus main, measured over 38 target-model MoE shapes on three GPUs.\nGeomean speedup per shape group:\n\n| shape group | DGX Spark | RTX 5080 | RTX Pro 6000 SE |\n|---|---|---|---|\n| decode, batch 1-2 | 1.06x | 1.30x | 1.40x |\n| decode, batch 4-40 | 1.00x | 1.00x | 1.00x |\n| prefill, batch 512-2048 | 1.10x | 1.10x | 1.09x |\n| prefill, batch 8192 | 1.00x | 1.00x | 1.00x |\n\n- The batch 1-2 gains come from the new `MoEDirectMicroKernel`; the\nshapes it serves win up to 2.3x.\n- The prefill gains come from `MoEDynamicKernel` picking tiles smaller\nthan 128 rows; those shapes win up to 1.26x.\n\n## 🔍 Related Issues\n\n#4223 (item 2).\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n## 🧪 Tests\n\n- On SM121 (DGX Spark GB10): `tests/moe/test_b12x_fused_moe.py` (157\ncases) and `tests/moe/test_unified_moe_b12x.py` (58 cases) pass,\nincluding tests that force each backend and a test that a smaller tile\nis picked again after a large-batch call.\n\n## Reviewer Notes\n\nDeviations from the b12x source, beyond import plumbing:\n\n- gelu_tanh added to `MoEDirectMicroKernel`, matching the activation\ncoverage of the module's other kernels.\n- The module's API accepts reciprocal-form scales but upstream's kernel\nonly takes multipliers, so dispatch inverts them before launch.\n- `MoEDirectMicroKernel`'s cutover is re-measured: upstream's only\nalternative is its counterpart of `MoEDynamicKernel`, while here it\ncompetes with `MoEMicroKernel` and `MoEStaticKernel`.\n- Upstream sizes scratch and builds the kernel together inside one plan\nobject, so their tile sizes always match. FlashInfer has no plan object,\nso the workspace cache is keyed by tile size to give the same guarantee.\n\n🤖 Generated with [Claude Code](https://claude.com/claude-code)\n\n---------\n\nCo-authored-by: Claude Fable 5 <noreply@anthropic.com>\nCo-authored-by: Brian K. Ryu <bryu@nvidia.com>"},"path":{"kind":"string","value":"flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_activation.py"},"language":{"kind":"string","value":"cute_dsl"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"\"\"\"Activation helper functions for the b12x fused-MoE kernels.\"\"\"\n\nfrom __future__ import annotations\n\nimport cutlass\nimport cutlass.cute as cute\nfrom cutlass import Float32\n\nfrom flashinfer.cute_dsl.fp4_common import fmax_f32, fmin_f32\n\n\ndef is_gated_activation(activation: str) -> bool:\n return activation in (\"silu\", \"gelu_tanh\", \"swigluoai_uninterleave\")\n\n\ndef gated_activation_f32(\n g,\n u,\n *,\n activation: str,\n limit: float | None,\n alpha: float,\n beta: float,\n fast_math: bool,\n):\n \"\"\"Return ``act(gate) * up_term`` (Float32) for a gated MoE activation.\n\n - silu: ``g*sigmoid(g)*u``\n - gelu_tanh: ``g*sigmoid(2z)*u`` (tanh-approx GELU, sigmoid(2z) == 0.5*(1+tanh(z)),\n z = 0.7978845608*(g + 0.044715*g^3))\n - swigluoai: ``g*sigmoid(alpha*g)*(u+beta)``, clamped when ``limit`` is set\n \"\"\"\n if cutlass.const_expr(activation == \"swigluoai_uninterleave\"):\n if cutlass.const_expr(limit is not None):\n lim = Float32(limit)\n g = fmin_f32(g, lim)\n u = fmax_f32(fmin_f32(u, lim), Float32(-limit))\n sig_arg = Float32(alpha) * g\n up_term = u + Float32(beta)\n elif cutlass.const_expr(activation == \"gelu_tanh\"):\n # Standard tanh-approximation GELU.\n sig_arg = Float32(2.0 * 0.7978845608028654) * (\n g + Float32(0.044715) * g * g * g\n )\n up_term = u\n else:\n sig_arg = g\n up_term = u\n sigmoid_g = cute.arch.rcp_approx(\n Float32(1.0) + cute.math.exp(-sig_arg, fastmath=fast_math)\n )\n return g * sigmoid_g * up_term\n"},"after_code":{"kind":"string","value":"\"\"\"Activation helper functions and metadata for the b12x fused-MoE kernels.\"\"\"\n\nfrom __future__ import annotations\n\nimport math\n\nimport cutlass\nimport cutlass.cute as cute\nfrom cutlass import Float32\n\nfrom flashinfer.cute_dsl.fp4_common import fmax_f32, fmin_f32\n\n\nSWIGLUOAI_UNINTERLEAVE = \"swigluoai_uninterleave\"\nSWIGLUOAI_DEFAULT_LIMIT = 7.0\nSWIGLUOAI_DEFAULT_ALPHA = 1.702\nSWIGLUOAI_DEFAULT_BETA = 1.0\n\nSUPPORTED_MOE_ACTIVATIONS = frozenset(\n {\"silu\", \"gelu_tanh\", \"relu2\", SWIGLUOAI_UNINTERLEAVE}\n)\nGATED_MOE_ACTIVATIONS = frozenset({\"silu\", \"gelu_tanh\", SWIGLUOAI_UNINTERLEAVE})\n\n\ndef normalize_moe_activation(activation: str) -> str:\n activation = str(activation)\n if activation not in SUPPORTED_MOE_ACTIVATIONS:\n raise ValueError(f\"unsupported activation {activation!r}\")\n return activation\n\n\ndef is_gated_moe_activation(activation: str) -> bool:\n return normalize_moe_activation(activation) in GATED_MOE_ACTIVATIONS\n\n\ndef normalize_swiglu_limit_for_activation(\n activation: str,\n swiglu_limit: float | None,\n) -> float | None:\n activation = normalize_moe_activation(activation)\n if swiglu_limit is None:\n return SWIGLUOAI_DEFAULT_LIMIT if activation == SWIGLUOAI_UNINTERLEAVE else None\n if activation not in GATED_MOE_ACTIVATIONS:\n raise ValueError(\"swiglu_limit requires a gated MoE activation\")\n limit = float(swiglu_limit)\n if not math.isfinite(limit) or limit <= 0.0:\n raise ValueError(f\"swiglu_limit must be positive and finite, got {limit}\")\n return limit\n\n\ndef normalize_swiglu_alpha_for_activation(\n activation: str,\n swiglu_alpha: float | None,\n) -> float:\n activation = normalize_moe_activation(activation)\n if activation != SWIGLUOAI_UNINTERLEAVE:\n # Accept the module default so callers can pass it unconditionally.\n if swiglu_alpha is not None and float(swiglu_alpha) not in (\n 1.0,\n SWIGLUOAI_DEFAULT_ALPHA,\n ):\n raise ValueError(\n \"swiglu_alpha is only configurable for swigluoai_uninterleave\"\n )\n return 1.0\n alpha = SWIGLUOAI_DEFAULT_ALPHA if swiglu_alpha is None else float(swiglu_alpha)\n if not math.isfinite(alpha):\n raise ValueError(f\"swiglu_alpha must be finite, got {alpha}\")\n return alpha\n\n\ndef normalize_swiglu_beta_for_activation(\n activation: str,\n swiglu_beta: float | None,\n) -> float:\n activation = normalize_moe_activation(activation)\n if activation != SWIGLUOAI_UNINTERLEAVE:\n # Accept the module default so callers can pass it unconditionally.\n if swiglu_beta is not None and float(swiglu_beta) not in (\n 0.0,\n SWIGLUOAI_DEFAULT_BETA,\n ):\n raise ValueError(\n \"swiglu_beta is only configurable for swigluoai_uninterleave\"\n )\n return 0.0\n beta = SWIGLUOAI_DEFAULT_BETA if swiglu_beta is None else float(swiglu_beta)\n if not math.isfinite(beta):\n raise ValueError(f\"swiglu_beta must be finite, got {beta}\")\n return beta\n\n\ndef is_gated_activation(activation: str) -> bool:\n return activation in GATED_MOE_ACTIVATIONS\n\n\ndef gated_activation_f32(\n g,\n u,\n *,\n activation: str,\n limit: float | None,\n alpha: float,\n beta: float,\n fast_math: bool,\n):\n \"\"\"Return ``act(gate) * up_term`` (Float32) for a gated MoE activation.\n\n - silu: ``g*sigmoid(g)*u``\n - gelu_tanh: ``g*sigmoid(2z)*u`` (tanh-approx GELU, sigmoid(2z) == 0.5*(1+tanh(z)),\n z = 0.7978845608*(g + 0.044715*g^3))\n - swigluoai: ``g*sigmoid(alpha*g)*(u+beta)``, clamped when ``limit`` is set\n \"\"\"\n if cutlass.const_expr(activation == \"swigluoai_uninterleave\"):\n if cutlass.const_expr(limit is not None):\n lim = Float32(limit)\n g = fmin_f32(g, lim)\n u = fmax_f32(fmin_f32(u, lim), Float32(-limit))\n sig_arg = Float32(alpha) * g\n up_term = u + Float32(beta)\n elif cutlass.const_expr(activation == \"gelu_tanh\"):\n # Standard tanh-approximation GELU.\n sig_arg = Float32(2.0 * 0.7978845608028654) * (\n g + Float32(0.044715) * g * g * g\n )\n up_term = u\n else:\n sig_arg = g\n up_term = u\n sigmoid_g = cute.arch.rcp_approx(\n Float32(1.0) + cute.math.exp(-sig_arg, fastmath=fast_math)\n )\n return g * sigmoid_g * up_term\n"},"diff":{"kind":"string","value":"--- flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_activation.py\n+++ flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_activation.py\n@@ -1,6 +1,8 @@\n-\"\"\"Activation helper functions for the b12x fused-MoE kernels.\"\"\"\n+\"\"\"Activation helper functions and metadata for the b12x fused-MoE kernels.\"\"\"\n \n from __future__ import annotations\n+\n+import math\n \n import cutlass\n import cutlass.cute as cute\n@@ -9,8 +11,87 @@\n from flashinfer.cute_dsl.fp4_common import fmax_f32, fmin_f32\n \n \n+SWIGLUOAI_UNINTERLEAVE = \"swigluoai_uninterleave\"\n+SWIGLUOAI_DEFAULT_LIMIT = 7.0\n+SWIGLUOAI_DEFAULT_ALPHA = 1.702\n+SWIGLUOAI_DEFAULT_BETA = 1.0\n+\n+SUPPORTED_MOE_ACTIVATIONS = frozenset(\n+ {\"silu\", \"gelu_tanh\", \"relu2\", SWIGLUOAI_UNINTERLEAVE}\n+)\n+GATED_MOE_ACTIVATIONS = frozenset({\"silu\", \"gelu_tanh\", SWIGLUOAI_UNINTERLEAVE})\n+\n+\n+def normalize_moe_activation(activation: str) -> str:\n+ activation = str(activation)\n+ if activation not in SUPPORTED_MOE_ACTIVATIONS:\n+ raise ValueError(f\"unsupported activation {activation!r}\")\n+ return activation\n+\n+\n+def is_gated_moe_activation(activation: str) -> bool:\n+ return normalize_moe_activation(activation) in GATED_MOE_ACTIVATIONS\n+\n+\n+def normalize_swiglu_limit_for_activation(\n+ activation: str,\n+ swiglu_limit: float | None,\n+) -> float | None:\n+ activation = normalize_moe_activation(activation)\n+ if swiglu_limit is None:\n+ return SWIGLUOAI_DEFAULT_LIMIT if activation == SWIGLUOAI_UNINTERLEAVE else None\n+ if activation not in GATED_MOE_ACTIVATIONS:\n+ raise ValueError(\"swiglu_limit requires a gated MoE activation\")\n+ limit = float(swiglu_limit)\n+ if not math.isfinite(limit) or limit <= 0.0:\n+ raise ValueError(f\"swiglu_limit must be positive and finite, got {limit}\")\n+ return limit\n+\n+\n+def normalize_swiglu_alpha_for_activation(\n+ activation: str,\n+ swiglu_alpha: float | None,\n+) -> float:\n+ activation = normalize_moe_activation(activation)\n+ if activation != SWIGLUOAI_UNINTERLEAVE:\n+ # Accept the module default so callers can pass it unconditionally.\n+ if swiglu_alpha is not None and float(swiglu_alpha) not in (\n+ 1.0,\n+ SWIGLUOAI_DEFAULT_ALPHA,\n+ ):\n+ raise ValueError(\n+ \"swiglu_alpha is only configurable for swigluoai_uninterleave\"\n+ )\n+ return 1.0\n+ alpha = SWIGLUOAI_DEFAULT_ALPHA if swiglu_alpha is None else float(swiglu_alpha)\n+ if not math.isfinite(alpha):\n+ raise ValueError(f\"swiglu_alpha must be finite, got {alpha}\")\n+ return alpha\n+\n+\n+def normalize_swiglu_beta_for_activation(\n+ activation: str,\n+ swiglu_beta: float | None,\n+) -> float:\n+ activation = normalize_moe_activation(activation)\n+ if activation != SWIGLUOAI_UNINTERLEAVE:\n+ # Accept the module default so callers can pass it unconditionally.\n+ if swiglu_beta is not None and float(swiglu_beta) not in (\n+ 0.0,\n+ SWIGLUOAI_DEFAULT_BETA,\n+ ):\n+ raise ValueError(\n+ \"swiglu_beta is only configurable for swigluoai_uninterleave\"\n+ )\n+ return 0.0\n+ beta = SWIGLUOAI_DEFAULT_BETA if swiglu_beta is None else float(swiglu_beta)\n+ if not math.isfinite(beta):\n+ raise ValueError(f\"swiglu_beta must be finite, got {beta}\")\n+ return beta\n+\n+\n def is_gated_activation(activation: str) -> bool:\n- return activation in (\"silu\", \"gelu_tanh\", \"swigluoai_uninterleave\")\n+ return activation in GATED_MOE_ACTIVATIONS\n \n \n def gated_activation_f32("},"lines_added":{"kind":"number","value":83,"string":"83"},"lines_removed":{"kind":"number","value":2,"string":"2"},"files_in_commit":{"kind":"number","value":8,"string":"8"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["RTX5080","SM121"],"string":"[\n \"RTX5080\",\n \"SM121\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":["1.06x","1.30x","1.40x","1.00x","1.00x","1.00x","1.10x","1.10x","1.09x","1.00x"],"string":"[\n \"1.06x\",\n \"1.30x\",\n \"1.40x\",\n \"1.00x\",\n \"1.00x\",\n \"1.00x\",\n \"1.10x\",\n \"1.10x\",\n \"1.09x\",\n \"1.00x\"\n]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cute_dsl kernel file from flashinfer (flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_activation.py).\n\nGoal: perf(moe): sync SM12x NVFP4 fused-MoE kernels to b12x HEAD\nTarget hardware: RTX5080, SM121\nTarget models: unspecified\n\nCurrent file:\n```python\n\"\"\"Activation helper functions for the b12x fused-MoE kernels.\"\"\"\n\nfrom __future__ import annotations\n\nimport cutlass\nimport cutlass.cute as cute\nfrom cutlass import Float32\n\nfrom flashinfer.cute_dsl.fp4_common import fmax_f32, fmin_f32\n\n\ndef is_gated_activation(activation: str) -> bool:\n return activation in (\"silu\", \"gelu_tanh\", \"swigluoai_uninterleave\")\n\n\ndef gated_activation_f32(\n g,\n u,\n *,\n activation: str,\n limit: float | None,\n alpha: float,\n beta: float,\n fast_math: bool,\n):\n \"\"\"Return ``act(gate) * up_term`` (Float32) for a gated MoE activation.\n\n - silu: ``g*sigmoid(g)*u``\n - gelu_tanh: ``g*sigmoid(2z)*u`` (tanh-approx GELU, sigmoid(2z) == 0.5*(1+tanh(z)),\n z = 0.7978845608*(g + 0.044715*g^3))\n - swigluoai: ``g*sigmoid(alpha*g)*(u+beta)``, clamped when ``limit`` is set\n \"\"\"\n if cutlass.const_expr(activation == \"swigluoai_uninterleave\"):\n if cutlass.const_expr(limit is not None):\n lim = Float32(limit)\n g = fmin_f32(g, lim)\n u = fmax_f32(fmin_f32(u, lim), Float32(-limit))\n sig_arg = Float32(alpha) * g\n up_term = u + Float32(beta)\n elif cutlass.const_expr(activation == \"gelu_tanh\"):\n # Standard tanh-approximation GELU.\n sig_arg = Float32(2.0 * 0.7978845608028654) * (\n g + Float32(0.044715) * g * g * g\n )\n up_term = u\n else:\n sig_arg = g\n up_term = u\n sigmoid_g = cute.arch.rcp_approx(\n Float32(1.0) + cute.math.exp(-sig_arg, fastmath=fast_math)\n )\n return g * sigmoid_g * up_term\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## 📌 Description\n\nSyncs the SM12x NVFP4 (W4A4) fused-MoE kernels behind `b12x_fused_moe` and `B12xMoEWrapper` with upstream [b12x](https://github.com/local-inference-lab/sparkinfer) at `f9be272`, reaching backend parity.\n\nThe module now has four kernels. `MoEDirectMicroKernel` takes the smallest decode batches, `MoEMicroKernel` and `MoEStaticKernel` cover the rest of decode with tile assignments fixed at launch, and `MoEDynamicKernel` covers prefill by distributing tiles through an in-kernel work queue.\n\nChanges:\n\n- Adopt upstream's current `MoEDirectMicroKernel`, replacing a stale copy in `moe_direct_micro_kernel.py` that was never routed to. It reads the top-k ids directly, so the smallest batches skip the routing pre-pass that dominates their runtime, and it now supports gelu_tanh.\n- Let `MoEDynamicKernel` use tiles smaller than 128 rows, so sparse routing stops padding every expert up to 128.\n- Launch all kernels cooperatively. They synchronize the whole grid between phases, which deadlocks if concurrent work keeps part of the grid off the GPU.\n- Simplify `MoEDynamicKernel`'s work queue and size its pipeline stages from the real shared-memory footprint.\n- Vectorize `MoEStaticKernel`'s scatter epilogue and refresh the decode tile heuristics.\n- Restrict the fast FP4 quantizer to gated activations, since relu2's squared outputs need the exact one.\n\nPublic API and behavior changes: none.\n\n## 📊 Performance\n\nVersus main, measured over 38 target-model MoE shapes on three GPUs. Geomean speedup per shape group:\n\n| shape group | DGX Spark | RTX 5080 | RTX Pro 6000 SE |\n|---|---|---|---|\n| decode, batch 1-2 | 1.06x | 1.30x | 1.40x |\n| decode, batch 4-40 | 1.00x | 1.00x | 1.00x |\n| prefill, batch 512-2048 | 1.10x | 1.10x | 1.09x |\n| prefill, batch 8192 | 1.00x | 1.00x | 1.00x |\n\n- The batch 1-2 gains come from the new `MoEDirectMicroKernel`; the shapes it serves win up to 2.3x.\n- The prefill gains come from `MoEDynamicKernel` picking tiles smaller than 128 rows; those shapes win up to 1.26x.\n\n## 🔍 Related Issues\n\n#4223 (item 2).\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n## 🧪 Tests\n\n- On SM121 (DGX Spark GB10): `tests/moe/test_b12x_fused_moe.py` (157 cases) and `tests/moe/test_unified_moe_b12x.py` (58 cases) pass, including tests that force each backend and a test that a smaller tile is picked again after a large-batch call.\n\n## Reviewer Notes\n\nDeviations from the b12x source, beyond import plumbing:\n\n- gelu_tanh added to `MoEDirectMicroKernel`, matching the activation coverage of the module's other kernels.\n- The module's API accepts reciprocal-form scales but upstream's kernel only takes multipliers, so dispatch inverts them before launch.\n- `MoEDirectMicroKernel`'s cutover is re-measured: upstream's only alternative is its counterpart of `MoEDynamicKernel`, while here it competes with `MoEMicroKernel` and `MoEStaticKernel`.\n- Upstream sizes scratch and builds the kernel together inside one plan object, so their tile sizes always match. FlashInfer has no plan object, so the workspace cache is keyed by tile size to give the same guarantee.\n\n🤖 Generated with [Claude Code](https://claude.com/claude-code)\n\n"},"gains":{"kind":"string","value":"[{\"scope\": \"e2e\", \"hardware\": \"DGX Spark\", \"model\": null, \"shape\": \"decode, batch 1-2\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.06, \"speedup\": 1.06}, {\"scope\": \"e2e\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"decode, batch 1-2\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.3, \"speedup\": 1.3}, {\"scope\": \"e2e\", \"hardware\": \"RTX Pro 6000 SE\", \"model\": null, \"shape\": \"decode, batch 1-2\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.4, \"speedup\": 1.4}, {\"scope\": \"e2e\", \"hardware\": \"DGX Spark\", \"model\": null, \"shape\": \"decode, batch 4-40\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.0, \"speedup\": 1.0}, {\"scope\": \"e2e\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"decode, batch 4-40\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.0, \"speedup\": 1.0}, {\"scope\": \"e2e\", \"hardware\": \"RTX Pro 6000 SE\", \"model\": null, \"shape\": \"decode, batch 4-40\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.0, \"speedup\": 1.0}, {\"scope\": \"e2e\", \"hardware\": \"DGX Spark\", \"model\": null, \"shape\": \"prefill, batch 512-2048\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.1, \"speedup\": 1.1}, {\"scope\": \"e2e\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"prefill, batch 512-2048\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.1, \"speedup\": 1.1}, {\"scope\": \"e2e\", \"hardware\": \"RTX Pro 6000 SE\", \"model\": null, \"shape\": \"prefill, batch 512-2048\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.09, \"speedup\": 1.09}, {\"scope\": \"e2e\", \"hardware\": \"DGX Spark\", \"model\": null, \"shape\": \"prefill, batch 8192\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.0, \"speedup\": 1.0}, {\"scope\": \"e2e\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"prefill, batch 8192\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.0, \"speedup\": 1.0}, {\"scope\": \"e2e\", \"hardware\": \"RTX Pro 6000 SE\", \"model\": null, \"shape\": \"prefill, batch 8192\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.0, \"speedup\": 1.0}]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"number","value":1.03,"string":"1.03"}}},{"rowIdx":1099,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"5a4b54bed1dfe6f112cd4ec9bc196da517369f46"},"date":{"kind":"string","value":"2026-08-03T14:43:37-07:00"},"pr_number":{"kind":"number","value":4285,"string":"4,285"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/4285"},"title":{"kind":"string","value":"perf(moe): sync SM12x NVFP4 fused-MoE kernels to b12x HEAD (#4285)"},"message":{"kind":"string","value":"perf(moe): sync SM12x NVFP4 fused-MoE kernels to b12x HEAD (#4285)\n\n## 📌 Description\n\nSyncs the SM12x NVFP4 (W4A4) fused-MoE kernels behind `b12x_fused_moe`\nand `B12xMoEWrapper` with upstream\n[b12x](https://github.com/local-inference-lab/sparkinfer) at `f9be272`,\nreaching backend parity.\n\nThe module now has four kernels. `MoEDirectMicroKernel` takes the\nsmallest decode batches, `MoEMicroKernel` and `MoEStaticKernel` cover\nthe rest of decode with tile assignments fixed at launch, and\n`MoEDynamicKernel` covers prefill by distributing tiles through an\nin-kernel work queue.\n\nChanges:\n\n- Adopt upstream's current `MoEDirectMicroKernel`, replacing a stale\ncopy in `moe_direct_micro_kernel.py` that was never routed to. It reads\nthe top-k ids directly, so the smallest batches skip the routing\npre-pass that dominates their runtime, and it now supports gelu_tanh.\n- Let `MoEDynamicKernel` use tiles smaller than 128 rows, so sparse\nrouting stops padding every expert up to 128.\n- Launch all kernels cooperatively. They synchronize the whole grid\nbetween phases, which deadlocks if concurrent work keeps part of the\ngrid off the GPU.\n- Simplify `MoEDynamicKernel`'s work queue and size its pipeline stages\nfrom the real shared-memory footprint.\n- Vectorize `MoEStaticKernel`'s scatter epilogue and refresh the decode\ntile heuristics.\n- Restrict the fast FP4 quantizer to gated activations, since relu2's\nsquared outputs need the exact one.\n\nPublic API and behavior changes: none.\n\n## 📊 Performance\n\nVersus main, measured over 38 target-model MoE shapes on three GPUs.\nGeomean speedup per shape group:\n\n| shape group | DGX Spark | RTX 5080 | RTX Pro 6000 SE |\n|---|---|---|---|\n| decode, batch 1-2 | 1.06x | 1.30x | 1.40x |\n| decode, batch 4-40 | 1.00x | 1.00x | 1.00x |\n| prefill, batch 512-2048 | 1.10x | 1.10x | 1.09x |\n| prefill, batch 8192 | 1.00x | 1.00x | 1.00x |\n\n- The batch 1-2 gains come from the new `MoEDirectMicroKernel`; the\nshapes it serves win up to 2.3x.\n- The prefill gains come from `MoEDynamicKernel` picking tiles smaller\nthan 128 rows; those shapes win up to 1.26x.\n\n## 🔍 Related Issues\n\n#4223 (item 2).\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n## 🧪 Tests\n\n- On SM121 (DGX Spark GB10): `tests/moe/test_b12x_fused_moe.py` (157\ncases) and `tests/moe/test_unified_moe_b12x.py` (58 cases) pass,\nincluding tests that force each backend and a test that a smaller tile\nis picked again after a large-batch call.\n\n## Reviewer Notes\n\nDeviations from the b12x source, beyond import plumbing:\n\n- gelu_tanh added to `MoEDirectMicroKernel`, matching the activation\ncoverage of the module's other kernels.\n- The module's API accepts reciprocal-form scales but upstream's kernel\nonly takes multipliers, so dispatch inverts them before launch.\n- `MoEDirectMicroKernel`'s cutover is re-measured: upstream's only\nalternative is its counterpart of `MoEDynamicKernel`, while here it\ncompetes with `MoEMicroKernel` and `MoEStaticKernel`.\n- Upstream sizes scratch and builds the kernel together inside one plan\nobject, so their tile sizes always match. FlashInfer has no plan object,\nso the workspace cache is keyed by tile size to give the same guarantee.\n\n🤖 Generated with [Claude Code](https://claude.com/claude-code)\n\n---------\n\nCo-authored-by: Claude Fable 5 <noreply@anthropic.com>\nCo-authored-by: Brian K. Ryu <bryu@nvidia.com>"},"path":{"kind":"string","value":"flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_dispatch.py"},"language":{"kind":"string","value":"cute_dsl"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"\"\"\"SM120/SM121 MoE dispatch layer — workspace, compilation, and launch.\n\nPorted from b12x's integration/tp_moe.py. Supports micro (tiny decode),\nstatic (decode), and dynamic (prefill) backends with token-count-based\nselection.\n\"\"\"\n\nfrom __future__ import annotations\n\nimport os\nimport weakref\nfrom dataclasses import dataclass\nfrom typing import Any, Dict, Optional, Tuple, Union\n\nimport cutlass\nimport cutlass.cute as cute\nimport torch\n\nfrom flashinfer.cute_dsl.utils import (\n convert_sf_from_mma_layout,\n convert_sf_to_mma_layout,\n current_cuda_stream,\n get_max_active_clusters,\n get_num_sm,\n make_ptr,\n)\nfrom .moe_activation import is_gated_activation\nfrom .moe_dynamic_kernel import MoEDynamicKernel\nfrom .moe_micro_kernel import MoEMicroKernel\nfrom .moe_static_kernel import MoEStaticKernel\nfrom .moe_w4a16_fp4_helpers import swizzle_block_scale\nfrom .moe_w4a16_host import (\n _W4A16_ALLOWED_ROUTED_SIZES,\n max_packed_route_slots,\n packed_gemm_scratch_elements,\n unswizzle_block_scale,\n validate_activation,\n)\nfrom .moe_w4a16_kernel import run_w4a16_moe\nfrom .moe_w4a16_prepare import (\n W4A16PackedWeights,\n _normalize_source_format,\n prepare_w4a16_packed_weights,\n)\n\n# ---------------------------------------------------------------------------\n# Constants\n# ---------------------------------------------------------------------------\n_NVFP4_BLOCK_SIZE = 16\n_LEVEL_TILE_M = 128\n_LEVEL_TILE_N = 128\n_DYNAMIC_SLICE_CHUNK = 1\nSF_VEC_SIZE = 16\n_FORCE_MOE_W4A16_ENV = \"FLASHINFER_B12X_FORCE_MOE_W4A16\"\n_MICRO_SHARE_INPUT_ACROSS_EXPERTS = (\n os.environ.get(\"FLASHINFER_B12X_MICRO_SHARE_INPUT\", \"1\") != \"0\"\n)\n\n# Micro kernel cutover thresholds (routed pairs)\n_MICRO_COMPACT_CUTOVER_PAIRS = 20\n_MICRO_COMPACT_CUTOVER_PAIRS_MULTI_TOPK = 40\n_STATIC_COMPACT_CUTOVER_PAIRS_DEFAULT = 640\n_STATIC_COMPACT_CUTOVER_PAIRS = _STATIC_COMPACT_CUTOVER_PAIRS_DEFAULT\n_STATIC_COMPACT_CUTOVER_PAIRS_CACHE: Dict[str, int] = {}\n\n# MAC (max active clusters) tuning ladders from b12x decode profiling.\n# Each entry is (max_routed_rows, optimal_mac).\n_MICRO_MAC_LADDER: Tuple[Tuple[int, int], ...] = (\n (2, 84),\n (4, 127),\n (8, 107),\n (10, 84),\n (16, 63),\n (20, 84),\n)\n_STATIC_MAC_LADDER: Tuple[Tuple[int, int], ...] = (\n (24, 148),\n (32, 169),\n (40, 132),\n (48, 149),\n (64, 134),\n (80, 175),\n (96, 171),\n (120, 125),\n (128, 130),\n (160, 171),\n (192, 166),\n (256, 141),\n (320, 158),\n (512, 175),\n (640, 188),\n)\n\n\ndef _lookup_mac_ladder(\n ladder: Tuple[Tuple[int, int], ...], routed_rows: int\n) -> int | None:\n \"\"\"Look up optimal MAC from a tuning ladder. Returns None if no match.\"\"\"\n for end_rows, mac in ladder:\n if routed_rows <= end_rows:\n return mac\n return None\n\n\ndef _align_up(value: int, alignment: int) -> int:\n return ((value + alignment - 1) // alignment) * alignment\n\n\ndef _first_env(*names: str) -> str | None:\n for name in names:\n value = os.environ.get(name)\n if value is not None:\n return value\n return None\n\n\ndef _normalize_activation_precision(activation_precision: str) -> str:\n \"\"\"Normalize public activation-precision names to internal modes.\"\"\"\n if os.environ.get(_FORCE_MOE_W4A16_ENV, \"0\") == \"1\":\n return \"bf16\"\n\n normalized = str(activation_precision).lower()\n aliases = {\n \"fp4\": \"fp4\",\n \"nvfp4\": \"fp4\",\n \"w4a4\": \"fp4\",\n \"bf16\": \"bf16\",\n \"w4a16\": \"bf16\",\n }\n try:\n return aliases[normalized]\n except KeyError as exc:\n raise ValueError(\n \"activation_precision must be 'fp4' or 'bf16' \"\n f\"(got {activation_precision!r}).\"\n ) from exc\n\n\ndef _normalize_quant_mode(\n quant_mode: str | None = None,\n activation_precision: str | None = None,\n) -> str:\n \"\"\"Normalize public quantization names to the dispatch mode.\"\"\"\n if os.environ.get(_FORCE_MOE_W4A16_ENV, \"0\") == \"1\":\n return \"w4a16\"\n if quant_mode is None:\n activation_precision = _normalize_activation_precision(\n activation_precision or \"fp4\"\n )\n return \"w4a16\" if activation_precision == \"bf16\" else \"nvfp4\"\n\n normalized = str(quant_mode).lower()\n aliases = {\n \"fp4\": \"nvfp4\",\n \"nvfp4\": \"nvfp4\",\n \"w4a4\": \"nvfp4\",\n \"bf16\": \"w4a16\",\n \"w4a16\": \"w4a16\",\n }\n try:\n return aliases[normalized]\n except KeyError as exc:\n raise ValueError(\n f\"quant_mode must be 'nvfp4'/'w4a4' or 'w4a16' (got {quant_mode!r}).\"\n ) from exc\n\n\ndef _activation_precision_from_quant_mode(quant_mode: str) -> str:\n return \"bf16\" if _normalize_quant_mode(quant_mode) == \"w4a16\" else \"fp4\"\n\n\ndef _normalize_source_format_for_quant_mode(source_format: str, quant_mode: str) -> str:\n normalized = _normalize_source_format(source_format)\n if quant_mode == \"nvfp4\" and normalized == \"compressed_tensors\":\n raise ValueError(\n \"source_format='compressed_tensors' requires quant_mode='w4a16'.\"\n )\n return normalized\n\n\ndef _is_w4a16(activation_precision: str) -> bool:\n return _normalize_activation_precision(activation_precision) == \"bf16\"\n\n\ndef _level_tile_m(activation_precision: str = \"fp4\") -> int:\n if _is_w4a16(activation_precision):\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 tile selector\"\n )\n return _LEVEL_TILE_M\n\n\ndef _level_tile_n(activation_precision: str = \"fp4\") -> int:\n if _is_w4a16(activation_precision):\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 tile selector\"\n )\n return _LEVEL_TILE_N\n\n\ndef _get_static_compact_cutover_pairs(activation_precision: str = \"fp4\") -> int:\n activation_precision = _normalize_activation_precision(activation_precision)\n cached = _STATIC_COMPACT_CUTOVER_PAIRS_CACHE.get(activation_precision)\n if cached is not None:\n return cached\n\n cutover_names: tuple[str, ...] = (\n \"FLASHINFER_B12X_STATIC_COMPACT_CUTOVER_PAIRS\",\n \"B12X_STATIC_COMPACT_CUTOVER_PAIRS\",\n \"B12X_DYNAMIC_STATIC_CUTOVER_PAIRS\",\n \"B12X_LEVEL10_STATIC_CUTOVER_PAIRS\",\n )\n cutover = _first_env(*cutover_names)\n if cutover is None:\n cached = _STATIC_COMPACT_CUTOVER_PAIRS_DEFAULT\n else:\n cached = max(0, int(cutover))\n _STATIC_COMPACT_CUTOVER_PAIRS_CACHE[activation_precision] = cached\n return cached\n\n\ndef _select_moe_mma_tiler_mn(routed_rows: int, n: int) -> Tuple[int, int]:\n \"\"\"Select optimal MoE tile shape based on routed rows and N dimension.\n\n Uses narrower 64x128 tiles when routed_rows <= 128 and default 128x128\n would leave SMs idle.\n \"\"\"\n sm_count = get_num_sm(torch.device(\"cuda\"))\n coarse_tile = (128, 128)\n coarse_tiles = ((routed_rows + coarse_tile[0] - 1) // coarse_tile[0]) * (\n (n + coarse_tile[1] - 1) // coarse_tile[1]\n )\n # Single-token decode often lands exactly on the \"half the machine\"\n # boundary. Keeping the coarse 128x128 tile there leaves the M dimension\n # badly underfilled, so take the narrow 64x128 tile inclusive of equality.\n if routed_rows <= 128 and coarse_tiles <= max(1, sm_count // 2):\n return (64, 128)\n return (128, 128)\n\n\ndef _as_grouped_scale_view(\n scale_storage: torch.Tensor,\n rows: int,\n cols: int,\n) -> torch.Tensor:\n \"\"\"Create 6D MMA-compatible scale factor view from swizzled storage.\"\"\"\n batch = scale_storage.shape[0]\n rows_padded = _align_up(rows, 128)\n cols_padded = _align_up(cols // SF_VEC_SIZE, 4)\n sf = scale_storage.view(torch.float8_e4m3fn)\n sf = sf.view(batch, rows_padded // 128, cols_padded // 4, 32, 4, 4)\n return sf.permute(3, 4, 1, 5, 2, 0)\n\n\n# ---------------------------------------------------------------------------\n# Workspace\n# ---------------------------------------------------------------------------\n@dataclass(kw_only=True)\nclass Sm120StaticMoEWorkspace:\n \"\"\"Scratch buffers for one SM120 static MoE launch.\"\"\"\n\n state_E: int\n weight_E: int\n max_rows: int\n k: int\n n: int\n num_topk: int\n device: torch.device\n activation_precision: str\n\n # Buffers\n row_counts: torch.Tensor # [state_E] int32\n token_map: torch.Tensor # [state_E, max_rows] int32\n token_weights: torch.Tensor # [state_E, max_rows] float32\n packed_input: torch.Tensor # [state_E, max_rows, k//2] uint8\n packed_input_scale: torch.Tensor # [state_E, rows_pad_k, cols_pad_k] uint8\n barrier_count: torch.Tensor # [1] int32\n barrier_epoch: torch.Tensor # [1] int32\n active_expert_count: torch.Tensor # [1] int32\n weight_expert_ids: torch.Tensor # [state_E] int32\n global_to_local_expert: torch.Tensor # [weight_E] int32\n compact_topk_ids: torch.Tensor # [state_E] int32, for micro kernel pre-pass\n\n # Views (set after allocation)\n packed_a_view: torch.Tensor | None = None\n sfa_ptr: object = None\n packed_a_flat: torch.Tensor | None = None\n scale_flat: torch.Tensor | None = None\n\n\ndef allocate_sm120_static_workspace(\n *,\n state_E: int,\n weight_E: int,\n max_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation_precision: str = \"fp4\",\n) -> Sm120StaticMoEWorkspace:\n \"\"\"Allocate workspace buffers for the SM120 static MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"allocate_sm120_static_workspace only supports quant_mode='nvfp4'; \"\n \"use allocate_sm120_moe_workspace(..., quant_mode='w4a16') for W4A16.\"\n )\n\n rows_pad_k = _align_up(max_rows, 128)\n cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n packed_input = torch.empty(\n state_E, max_rows, k // 2, dtype=torch.uint8, device=device\n )\n\n workspace = Sm120StaticMoEWorkspace(\n state_E=state_E,\n weight_E=weight_E,\n max_rows=max_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation_precision=activation_precision,\n row_counts=torch.zeros(state_E, dtype=torch.int32, device=device),\n token_map=torch.zeros(state_E, max_rows, dtype=torch.int32, device=device),\n token_weights=torch.zeros(\n state_E, max_rows, dtype=torch.float32, device=device\n ),\n packed_input=packed_input,\n packed_input_scale=torch.empty(\n state_E, rows_pad_k, cols_pad_k, dtype=torch.uint8, device=device\n ),\n barrier_count=torch.zeros(1, dtype=torch.int32, device=device),\n barrier_epoch=torch.zeros(1, dtype=torch.int32, device=device),\n active_expert_count=torch.zeros(1, dtype=torch.int32, device=device),\n weight_expert_ids=torch.arange(state_E, dtype=torch.int32, device=device),\n global_to_local_expert=torch.empty(weight_E, dtype=torch.int32, device=device),\n compact_topk_ids=torch.empty(\n max(state_E, max_rows), dtype=torch.int32, device=device\n ),\n )\n\n # Finalize views\n sf_dtype = cutlass.Float8E4M3FN\n workspace.packed_a_view = workspace.packed_input.permute(1, 2, 0).view(\n torch.float4_e2m1fn_x2\n )\n workspace.packed_a_flat = workspace.packed_input.view(-1)\n workspace.scale_flat = workspace.packed_input_scale.view(-1)\n workspace.sfa_ptr = make_ptr(\n sf_dtype,\n workspace.packed_input_scale.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n return workspace\n\n\n# ---------------------------------------------------------------------------\n# Weight views\n# ---------------------------------------------------------------------------\n@dataclass\nclass _WeightViews:\n w13_fp4: object = None\n down_fp4: object = None\n sfb_w13_ptr: object = None\n sfb_down_ptr: object = None\n w1_alpha: torch.Tensor | None = None\n w2_alpha: torch.Tensor | None = None\n w1_storage: torch.Tensor | None = None\n w1_scale_storage: torch.Tensor | None = None\n w2_storage: torch.Tensor | None = None\n w2_scale_storage: torch.Tensor | None = None\n _w13_sf_storage: torch.Tensor | None = None\n _down_sf_storage: torch.Tensor | None = None\n\n\ndef _register_cache_eviction(cache: Dict, key: Tuple, *source_tensors) -> None:\n \"\"\"Evict ``key`` when a source weight tensor is collected, so the cache\n follows the weights' lifetime instead of growing for the whole process.\n \"\"\"\n for tensor in source_tensors:\n if tensor is not None:\n weakref.finalize(tensor, cache.pop, key, None)\n\n\n_WEIGHT_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_weight_views(\n w1_fp4: torch.Tensor,\n w1_blockscale: torch.Tensor,\n w2_fp4: torch.Tensor,\n w2_blockscale: torch.Tensor,\n w1_alphas: torch.Tensor,\n w2_alphas: torch.Tensor,\n n: int,\n k: int,\n activation_precision: str = \"fp4\",\n) -> _WeightViews:\n \"\"\"Create permuted weight views for the static kernel.\n\n The kernel expects concatenated w13 data with shape [2*n, k//2, E]\n via a single TMA descriptor.\n \"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n tile_n = _level_tile_n(activation_precision)\n # The kernel splits w13 into gate/up halves by tile index. This only works\n # when the boundary between halves lands on a tile-aligned column.\n if n % tile_n != 0:\n raise ValueError(\n f\"intermediate_size ({n}) must be a multiple of {tile_n} \"\n f\"for the SM120 MoE kernel's gate/up tile split.\"\n )\n\n key = (\n activation_precision,\n w1_fp4.data_ptr(),\n w1_blockscale.data_ptr(),\n w1_alphas.data_ptr(),\n w2_fp4.data_ptr(),\n w2_blockscale.data_ptr(),\n w2_alphas.data_ptr(),\n )\n cached = _WEIGHT_CACHE.get(key)\n if cached is None:\n # Cache the fresh buffers (scale factors + fp32 alphas).\n w1_rows = w1_fp4.shape[1] # 2*n for gated, n for non-gated\n cached = (\n convert_sf_from_mma_layout(\n w1_blockscale, m=w1_rows, k=k, num_groups=w1_fp4.shape[0]\n ).contiguous(),\n convert_sf_from_mma_layout(\n w2_blockscale, m=k, k=n, num_groups=w2_fp4.shape[0]\n ).contiguous(),\n w1_alphas.contiguous().to(torch.float32),\n w2_alphas.contiguous().to(torch.float32),\n )\n _WEIGHT_CACHE[key] = cached\n _register_cache_eviction(\n _WEIGHT_CACHE,\n key,\n w1_fp4,\n w1_blockscale,\n w1_alphas,\n w2_fp4,\n w2_blockscale,\n w2_alphas,\n )\n w13_sf_contiguous, down_sf_contiguous, w1_alpha, w2_alpha = cached\n\n # Permute [E, w1_rows, k//2] -> [w1_rows, k//2, E] (view, no copy).\n sf_dtype = cutlass.Float8E4M3FN\n w13 = w1_fp4.permute(1, 2, 0)\n down = w2_fp4.permute(1, 2, 0)\n return _WeightViews(\n w13_fp4=w13.view(torch.float4_e2m1fn_x2),\n down_fp4=down.view(torch.float4_e2m1fn_x2),\n sfb_w13_ptr=make_ptr(\n sf_dtype,\n w13_sf_contiguous.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n ),\n sfb_down_ptr=make_ptr(\n sf_dtype,\n down_sf_contiguous.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n ),\n w1_alpha=w1_alpha,\n w2_alpha=w2_alpha,\n w1_storage=w1_fp4,\n w1_scale_storage=w13_sf_contiguous,\n w2_storage=w2_fp4,\n w2_scale_storage=down_sf_contiguous,\n _w13_sf_storage=w13_sf_contiguous,\n _down_sf_storage=down_sf_contiguous,\n )\n\n\n# ---------------------------------------------------------------------------\n# Kernel compilation cache\n# ---------------------------------------------------------------------------\n_STATIC_KERNEL_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_static_kernel(\n state_E: int,\n weight_E: int,\n m: int,\n k: int,\n n: int,\n num_topk: int,\n max_rows: int,\n *,\n topk_ids_dtype: torch.dtype = torch.int32,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n mac_override: int | None = None,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n):\n \"\"\"Compile (or retrieve cached) the SM120 static MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 static compiler\"\n )\n sf_vec_size = 16\n sm_count = get_num_sm(torch.device(\"cuda\"))\n mac = (\n mac_override\n if mac_override is not None\n else min(get_max_active_clusters(1), sm_count)\n )\n\n # Select tile size based on actual routed rows\n routed_rows = m * num_topk\n mma_tiler_mn = (128, 128)\n if activation_precision == \"fp4\" and num_topk > 1:\n mma_tiler_mn = _select_moe_mma_tiler_mn(routed_rows, n)\n\n cache_key = (\n \"static\",\n activation_precision,\n state_E,\n weight_E,\n m,\n k,\n n,\n num_topk,\n max_rows,\n mac,\n mma_tiler_mn,\n topk_ids_dtype,\n input_scales_are_reciprocal,\n fast_math,\n activation,\n swiglu_alpha,\n swiglu_beta,\n swiglu_limit,\n )\n cached = _STATIC_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n return cached\n\n ab_dtype = cutlass.Float4E2M1FN\n weight_dtype = cutlass.Float4E2M1FN\n sf_dtype = cutlass.Float8E4M3FN\n a_dtype = cutlass.BFloat16\n alpha_dtype = cutlass.Float32\n\n output_tile_count_n = max(1, (n + mma_tiler_mn[1] - 1) // mma_tiler_mn[1])\n kernel: Any = MoEStaticKernel(\n sf_vec_size=sf_vec_size,\n mma_tiler_mn=mma_tiler_mn,\n output_tile_count_n=output_tile_count_n,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n )\n\n is_gated = is_gated_activation(activation)\n w1_rows = (2 if is_gated else 1) * n # 2*n for gated, n for non-gated\n\n rows_pad_k = _align_up(max_rows, 128)\n cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n\n # Build fake tensors for compilation\n a_input_fake = cute.runtime.make_fake_compact_tensor(\n a_dtype,\n (m, k),\n stride_order=(1, 0),\n assumed_align=16,\n )\n topk_ids_cutlass_dtype = (\n cutlass.Int32 if topk_ids_dtype == torch.int32 else cutlass.Int64\n )\n topk_ids_align = 4 if topk_ids_dtype == torch.int32 else 8\n topk_ids_fake = cute.runtime.make_fake_compact_tensor(\n topk_ids_cutlass_dtype,\n (m * num_topk,),\n assumed_align=topk_ids_align,\n )\n topk_weights_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32,\n (m * num_topk,),\n assumed_align=4,\n )\n packed_a_fake = cute.runtime.make_fake_compact_tensor(\n ab_dtype,\n (max_rows, k, state_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfa_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n packed_a_storage_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (state_E * max_rows * (k // 2),),\n assumed_align=16,\n )\n scale_storage_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (state_E * rows_pad_k * cols_pad_k,),\n assumed_align=16,\n )\n barrier_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n barrier_epoch_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n b_w13_fake = cute.runtime.make_fake_compact_tensor(\n weight_dtype,\n (w1_rows, k, weight_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_w13_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n b_down_fake = cute.runtime.make_fake_compact_tensor(\n weight_dtype,\n (k, n, weight_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_down_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n row_counts_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E,),\n assumed_align=4,\n )\n active_expert_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n weight_expert_ids_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E,),\n assumed_align=4,\n )\n global_to_local_expert_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (weight_E,),\n assumed_align=4,\n )\n input_gs_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n down_alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n global_scale_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n scatter_fake = cute.runtime.make_fake_compact_tensor(\n a_dtype,\n (m, k),\n stride_order=(1, 0),\n assumed_align=16,\n )\n token_map_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E, max_rows),\n stride_order=(1, 0),\n assumed_align=4,\n )\n token_weights_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (state_E, max_rows),\n stride_order=(1, 0),\n assumed_align=16,\n )\n compiled = cute.compile(\n kernel,\n a_input_fake,\n topk_ids_fake,\n topk_weights_fake,\n packed_a_fake,\n sfa_fake,\n packed_a_storage_fake,\n scale_storage_fake,\n barrier_count_fake,\n barrier_epoch_fake,\n b_w13_fake,\n sfb_w13_fake,\n b_down_fake,\n sfb_down_fake,\n row_counts_fake,\n active_expert_count_fake,\n weight_expert_ids_fake,\n global_to_local_expert_fake,\n input_gs_fake,\n alpha_fake,\n down_alpha_fake,\n global_scale_fake,\n scatter_fake,\n token_map_fake,\n token_weights_fake,\n mac,\n current_cuda_stream(),\n options=\"--opt-level 2 --enable-tvm-ffi\",\n )\n\n result = (compiled, mac)\n _STATIC_KERNEL_CACHE[cache_key] = result\n return result\n\n\n_MICRO_KERNEL_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_micro_kernel(\n state_E: int,\n weight_E: int,\n m: int,\n k: int,\n n: int,\n num_topk: int,\n max_rows: int,\n *,\n topk_ids_dtype: torch.dtype = torch.int32,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n share_input_across_experts: bool = False,\n share_expert_scales: bool = False,\n single_token: bool = False,\n mac_override: int | None = None,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n):\n \"\"\"Compile (or retrieve cached) the SM120 micro MoE kernel.\"\"\"\n sf_vec_size = 16\n sm_count = get_num_sm(torch.device(\"cuda\"))\n mac = (\n mac_override\n if mac_override is not None\n else min(get_max_active_clusters(1), sm_count)\n )\n\n # Micro always selects tile from routed rows (not just for multi-topk)\n routed_rows = m * num_topk\n mma_tiler_mn = _select_moe_mma_tiler_mn(routed_rows, n)\n\n cache_key = (\n \"micro\",\n state_E,\n weight_E,\n m,\n k,\n n,\n num_topk,\n max_rows,\n mac,\n mma_tiler_mn,\n topk_ids_dtype,\n input_scales_are_reciprocal,\n fast_math,\n share_input_across_experts,\n share_expert_scales,\n single_token,\n activation,\n swiglu_alpha,\n swiglu_beta,\n swiglu_limit,\n )\n cached = _MICRO_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n return cached\n\n ab_dtype = cutlass.Float4E2M1FN\n sf_dtype = cutlass.Float8E4M3FN\n a_dtype = cutlass.BFloat16\n alpha_dtype = cutlass.Float32\n\n kernel = MoEMicroKernel(\n sf_vec_size=sf_vec_size,\n mma_tiler_mn=mma_tiler_mn,\n output_tile_count_n=max(1, (n + mma_tiler_mn[1] - 1) // mma_tiler_mn[1]),\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n share_input_across_experts=share_input_across_experts,\n share_expert_scales=share_expert_scales,\n single_token=single_token,\n )\n\n is_gated = is_gated_activation(activation)\n w1_rows = (2 if is_gated else 1) * n\n\n rows_pad_k = _align_up(max_rows, 128)\n cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n\n # Build fake tensors for compilation (identical to static kernel)\n a_input_fake = cute.runtime.make_fake_compact_tensor(\n a_dtype,\n (m, k),\n stride_order=(1, 0),\n assumed_align=16,\n )\n topk_ids_cutlass_dtype = (\n cutlass.Int32 if topk_ids_dtype == torch.int32 else cutlass.Int64\n )\n topk_ids_align = 4 if topk_ids_dtype == torch.int32 else 8\n topk_ids_fake = cute.runtime.make_fake_compact_tensor(\n topk_ids_cutlass_dtype,\n (m * num_topk,),\n assumed_align=topk_ids_align,\n )\n topk_weights_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32,\n (m * num_topk,),\n assumed_align=4,\n )\n packed_a_fake = cute.runtime.make_fake_compact_tensor(\n ab_dtype,\n (max_rows, k, state_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfa_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n packed_a_storage_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (state_E * max_rows * (k // 2),),\n assumed_align=16,\n )\n scale_storage_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (state_E * rows_pad_k * cols_pad_k,),\n assumed_align=16,\n )\n barrier_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n barrier_epoch_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n b_w13_fake = cute.runtime.make_fake_compact_tensor(\n ab_dtype,\n (w1_rows, k, weight_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_w13_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n b_down_fake = cute.runtime.make_fake_compact_tensor(\n ab_dtype,\n (k, n, weight_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_down_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n row_counts_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E,),\n assumed_align=4,\n )\n active_expert_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n weight_expert_ids_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E,),\n assumed_align=4,\n )\n global_to_local_expert_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (weight_E,),\n assumed_align=4,\n )\n input_gs_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n down_alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n global_scale_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n scatter_fake = cute.runtime.make_fake_compact_tensor(\n a_dtype,\n (m, k),\n stride_order=(1, 0),\n assumed_align=16,\n )\n token_map_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E, max_rows),\n stride_order=(1, 0),\n assumed_align=4,\n )\n token_weights_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (state_E, max_rows),\n stride_order=(1, 0),\n assumed_align=16,\n )\n compiled = cute.compile(\n kernel,\n a_input_fake,\n topk_ids_fake,\n topk_weights_fake,\n packed_a_fake,\n sfa_fake,\n packed_a_storage_fake,\n scale_storage_fake,\n barrier_count_fake,\n barrier_epoch_fake,\n b_w13_fake,\n sfb_w13_fake,\n b_down_fake,\n sfb_down_fake,\n row_counts_fake,\n active_expert_count_fake,\n weight_expert_ids_fake,\n global_to_local_expert_fake,\n input_gs_fake,\n alpha_fake,\n down_alpha_fake,\n global_scale_fake,\n scatter_fake,\n token_map_fake,\n token_weights_fake,\n mac,\n current_cuda_stream(),\n options=\"--opt-level 2 --enable-tvm-ffi\",\n )\n\n result = (compiled, mac)\n _MICRO_KERNEL_CACHE[cache_key] = result\n return result\n\n\n# ---------------------------------------------------------------------------\n# Launch\n# ---------------------------------------------------------------------------\ndef _expand_to_experts(t: torch.Tensor, num_experts: int) -> torch.Tensor:\n \"\"\"Broadcast a scalar or [1] tensor to [num_experts], always fp32.\n\n Both branches must cast: the kernels are compiled against fp32 fake\n tensors for every per-expert scale.\n \"\"\"\n if t.numel() == 1:\n return t.to(torch.float32).expand(num_experts).contiguous()\n return t.contiguous().to(torch.float32)\n\n\ndef launch_sm120_static_moe(\n *,\n workspace: Sm120StaticMoEWorkspace,\n weights: _WeightViews,\n a: torch.Tensor,\n topk_ids: torch.Tensor,\n topk_weights: torch.Tensor,\n input_gs: torch.Tensor,\n down_input_scale: torch.Tensor,\n scatter_output: torch.Tensor,\n num_experts: int,\n num_tokens: int,\n k: int,\n n: int,\n top_k: int,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n) -> torch.Tensor:\n \"\"\"Launch the SM120 static or micro MoE kernel.\n\n Selects the micro kernel for tiny decode batches (routed_rows <= 20-40)\n and the static kernel otherwise. The micro path runs a Triton pre-pass\n to compact routing IDs before launching.\n \"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 static launcher\"\n )\n\n # Flatten routing tensors\n flat_ids = topk_ids.view(-1).to(torch.int32)\n flat_weights = topk_weights.view(-1).to(torch.float32)\n routed_rows = num_tokens * top_k\n\n # Capture whether input_gs was a single shared scalar BEFORE expansion:\n # the m=1 relu2 shared-input micro optimization only applies when every\n # expert sees the same FC1-input global scale.\n input_gs_is_shared = input_gs.numel() == 1\n down_input_scale_is_shared = down_input_scale.numel() == 1\n\n # Broadcast scalar scales to per-expert [E] tensors\n input_gs = _expand_to_experts(input_gs, num_experts)\n down_input_scale = _expand_to_experts(down_input_scale, num_experts)\n\n # Decide micro vs static\n micro_cutover = _MICRO_COMPACT_CUTOVER_PAIRS\n if top_k > 1:\n micro_cutover = _MICRO_COMPACT_CUTOVER_PAIRS_MULTI_TOPK\n use_micro = activation_precision == \"fp4\" and routed_rows <= micro_cutover\n\n sm_count = get_num_sm(torch.device(\"cuda\"))\n base_mac = min(get_max_active_clusters(1), sm_count)\n tuned_static_mac = _lookup_mac_ladder(_STATIC_MAC_LADDER, routed_rows)\n static_mac = min(tuned_static_mac or base_mac, base_mac)\n if activation_precision == \"fp4\" and not use_micro and routed_rows < 40:\n static_mac = min(static_mac, 64)\n\n # Shared-scale flags let compact W4A4 micro match the ReLU2 single-token\n # specialization.\n share_input_across_experts = (\n activation == \"relu2\"\n and num_tokens == 1\n and input_gs_is_shared\n and _MICRO_SHARE_INPUT_ACROSS_EXPERTS\n )\n share_expert_scales = (\n activation == \"relu2\" and input_gs_is_shared and down_input_scale_is_shared\n )\n\n if use_micro:\n assert flat_ids.numel() <= workspace.compact_topk_ids.numel(), (\n f\"compact_topk_ids buffer too small: \"\n f\"{workspace.compact_topk_ids.numel()} < {flat_ids.numel()}\"\n )\n # Single-token ReLU2 is non-gated, so the micro kernel can launch on\n # the routed expert ids directly. Gated SiLU still goes through the\n # compact id buffer so the kernel can map compact launch ids back to\n # the physical gate/up weight experts.\n if num_tokens == 1 and activation == \"relu2\":\n launch_ids = flat_ids\n elif num_tokens == 1:\n compact_ids = workspace.compact_topk_ids[: flat_ids.numel()]\n compact_ids.copy_(\n torch.arange(\n flat_ids.numel(),\n device=flat_ids.device,\n dtype=torch.int32,\n )\n )\n workspace.weight_expert_ids[: flat_ids.numel()].copy_(\n flat_ids.to(torch.int32)\n )\n workspace.active_expert_count.fill_(flat_ids.numel())\n launch_ids = compact_ids\n else:\n compact_ids = workspace.compact_topk_ids[: flat_ids.numel()]\n from .triton_compact import compact_topk_ids as _triton_compact_topk_ids\n\n _triton_compact_topk_ids(\n flat_ids,\n compact_ids,\n workspace.weight_expert_ids,\n workspace.active_expert_count,\n )\n launch_ids = compact_ids\n # Select micro MAC: min of tuned ladder, work tiles, and hardware limit.\n micro_work_tiles = max(1, routed_rows * max(1, (n + 128 - 1) // 128))\n tuned_mac = _lookup_mac_ladder(_MICRO_MAC_LADDER, routed_rows)\n micro_mac = min(tuned_mac or base_mac, micro_work_tiles, base_mac)\n compiled, mac = _get_micro_kernel(\n workspace.state_E,\n num_experts,\n num_tokens,\n k,\n n,\n top_k,\n workspace.max_rows,\n topk_ids_dtype=launch_ids.dtype,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n share_input_across_experts=share_input_across_experts,\n share_expert_scales=share_expert_scales,\n single_token=num_tokens == 1,\n mac_override=micro_mac,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n )\n else:\n compiled, mac = _get_static_kernel(\n workspace.state_E,\n num_experts,\n num_tokens,\n k,\n n,\n top_k,\n workspace.max_rows,\n topk_ids_dtype=torch.int32,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n mac_override=static_mac,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n activation_precision=activation_precision,\n )\n launch_ids = flat_ids\n\n # Pointer arguments must be passed as raw ints (data_ptr()) at runtime.\n runtime_args: Tuple[Any, ...] = (\n a,\n launch_ids,\n flat_weights,\n workspace.packed_a_view,\n workspace.packed_input_scale.data_ptr(),\n workspace.packed_a_flat,\n workspace.scale_flat,\n workspace.barrier_count,\n workspace.barrier_epoch,\n weights.w13_fp4,\n weights._w13_sf_storage.data_ptr(),\n weights.down_fp4,\n weights._down_sf_storage.data_ptr(),\n workspace.row_counts,\n workspace.active_expert_count,\n workspace.weight_expert_ids,\n workspace.global_to_local_expert,\n input_gs,\n weights.w1_alpha,\n weights.w2_alpha,\n down_input_scale,\n scatter_output,\n workspace.token_map,\n workspace.token_weights,\n )\n compiled(*runtime_args, current_cuda_stream())\n\n return scatter_output\n\n\n# ==========================================================================\n# Dynamic backend\n# ==========================================================================\n\n\ndef select_sm120_moe_backend(\n *,\n num_tokens: int,\n num_topk: int,\n activation_precision: str = \"fp4\",\n quant_mode: str | None = None,\n) -> str:\n \"\"\"Pick static or dynamic backend based on routed-pair count.\"\"\"\n mode = _normalize_quant_mode(quant_mode, activation_precision)\n if mode == \"w4a16\":\n return \"w4a16\"\n routed_rows = num_tokens * num_topk\n if routed_rows <= _get_static_compact_cutover_pairs(\"fp4\"):\n return \"static\"\n return \"dynamic\"\n\n\n# ---------------------------------------------------------------------------\n# Dynamic workspace\n# ---------------------------------------------------------------------------\n@dataclass(kw_only=True)\nclass Sm120DynamicMoEWorkspace:\n \"\"\"Scratch buffers for one SM120 dynamic MoE launch.\"\"\"\n\n state_E: int\n weight_E: int\n max_rows: int\n k: int\n n: int\n num_topk: int\n device: torch.device\n activation_precision: str\n\n # Core buffers\n row_counts: torch.Tensor\n token_map: torch.Tensor\n token_weights: torch.Tensor\n packed_input: torch.Tensor\n packed_input_scale: torch.Tensor\n barrier_count: torch.Tensor\n barrier_epoch: torch.Tensor\n\n # Dynamic-specific\n routed_rows_capacity: int\n physical_tiles_capacity: int\n task_capacity: int\n expert_write_rows: torch.Tensor\n expert_tile_base: torch.Tensor\n pair_head: torch.Tensor\n producers_done_count: torch.Tensor\n all_work_published: torch.Tensor\n task_head: torch.Tensor\n task_tail: torch.Tensor\n task_ready: torch.Tensor\n task_expert: torch.Tensor\n task_m_tile: torch.Tensor\n task_slice_begin: torch.Tensor\n task_slice_count: torch.Tensor\n task_valid_rows: torch.Tensor\n tile_write_count: torch.Tensor\n\n # Views\n packed_a_view: torch.Tensor | None = None\n sfa_ptr: object = None\n packed_a_flat: torch.Tensor | None = None\n scale_flat: torch.Tensor | None = None\n\n\ndef _dynamic_task_geometry(\n state_E: int,\n n: int,\n routed_rows: int,\n *,\n tile_m: int = _LEVEL_TILE_M,\n tile_n: int = _LEVEL_TILE_N,\n):\n \"\"\"Compute task queue dimensions from problem geometry.\n\n Each active expert can introduce at most one additional physical tile\n beyond the base count (due to per-expert tail padding). The task queue\n holds one entry per (m_tile, slice_group) pair — NOT multiplied by E.\n \"\"\"\n routed_rows = max(1, routed_rows)\n base_m_tiles = _align_up(routed_rows, tile_m) // tile_m\n active_expert_upper_bound = min(state_E, routed_rows)\n max_m_tiles = max(1, base_m_tiles + active_expert_upper_bound - 1)\n gate_tile_cnt = max(1, (n + tile_n - 1) // tile_n)\n slice_groups = max(\n 1, (gate_tile_cnt + _DYNAMIC_SLICE_CHUNK - 1) // _DYNAMIC_SLICE_CHUNK\n )\n max_tasks = max_m_tiles * slice_groups\n return max_m_tiles, gate_tile_cnt, max_tasks\n\n\ndef allocate_sm120_dynamic_workspace(\n *,\n state_E: int,\n weight_E: int,\n routed_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation_precision: str = \"fp4\",\n) -> Sm120DynamicMoEWorkspace:\n \"\"\"Allocate workspace buffers for the SM120 dynamic MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"allocate_sm120_dynamic_workspace only supports quant_mode='nvfp4'; \"\n \"use allocate_sm120_moe_workspace(..., quant_mode='w4a16') for W4A16.\"\n )\n tile_m = _level_tile_m(activation_precision)\n physical_tiles, _, max_tasks = _dynamic_task_geometry(\n state_E,\n n,\n routed_rows,\n tile_m=tile_m,\n tile_n=_level_tile_n(activation_precision),\n )\n rows_padded = physical_tiles * tile_m\n cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n packed_input = torch.empty(1, rows_padded, k // 2, dtype=torch.uint8, device=device)\n\n workspace = Sm120DynamicMoEWorkspace(\n state_E=state_E,\n weight_E=weight_E,\n max_rows=rows_padded,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation_precision=activation_precision,\n routed_rows_capacity=routed_rows,\n physical_tiles_capacity=physical_tiles,\n task_capacity=max_tasks,\n row_counts=torch.zeros(state_E, dtype=torch.int32, device=device),\n token_map=torch.zeros(rows_padded, dtype=torch.int32, device=device),\n token_weights=torch.zeros(rows_padded, dtype=torch.float32, device=device),\n packed_input=packed_input,\n packed_input_scale=torch.empty(\n rows_padded, cols_pad_k, dtype=torch.uint8, device=device\n ),\n barrier_count=torch.zeros(1, dtype=torch.int32, device=device),\n barrier_epoch=torch.zeros(1, dtype=torch.int32, device=device),\n expert_write_rows=torch.zeros(state_E, dtype=torch.int32, device=device),\n expert_tile_base=torch.zeros(state_E + 1, dtype=torch.int32, device=device),\n pair_head=torch.zeros(1, dtype=torch.int32, device=device),\n producers_done_count=torch.zeros(1, dtype=torch.int32, device=device),\n all_work_published=torch.zeros(1, dtype=torch.int32, device=device),\n task_head=torch.zeros(1, dtype=torch.int32, device=device),\n task_tail=torch.zeros(1, dtype=torch.int32, device=device),\n task_ready=torch.zeros(max_tasks, dtype=torch.int32, device=device),\n task_expert=torch.zeros(max_tasks, dtype=torch.int32, device=device),\n task_m_tile=torch.zeros(max_tasks, dtype=torch.int32, device=device),\n task_slice_begin=torch.zeros(max_tasks, dtype=torch.int32, device=device),\n task_slice_count=torch.zeros(max_tasks, dtype=torch.int32, device=device),\n task_valid_rows=torch.zeros(max_tasks, dtype=torch.int32, device=device),\n tile_write_count=torch.zeros(physical_tiles, dtype=torch.int32, device=device),\n )\n\n # Finalize views\n sf_dtype = cutlass.Float8E4M3FN\n workspace.packed_a_view = workspace.packed_input.permute(1, 2, 0).view(\n torch.float4_e2m1fn_x2\n )\n workspace.packed_a_flat = workspace.packed_input.view(-1)\n workspace.scale_flat = workspace.packed_input_scale.view(-1)\n workspace.sfa_ptr = make_ptr(\n sf_dtype,\n workspace.packed_input_scale.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n return workspace\n\n\n# ---------------------------------------------------------------------------\n# Dynamic kernel compilation\n# ---------------------------------------------------------------------------\n\n\nclass _DynamicMoELaunch:\n \"\"\"Thin JIT wrapper that makes num_tokens and max_rows runtime Int32.\"\"\"\n\n def __init__(self, kernel, k, num_topk, activation_precision: str = \"fp4\"):\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 dynamic launcher wrapper\"\n )\n self._kernel = kernel\n self._k = k\n self._packed_storage_cols = k // 2\n self._num_topk = num_topk\n self._cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n\n @cute.jit\n def __call__(\n self,\n a_ptr: cute.Pointer,\n topk_ids_ptr: cute.Pointer,\n topk_weights_ptr: cute.Pointer,\n packed_a_ptr: cute.Pointer,\n sfa_ptr: cute.Pointer,\n packed_a_storage_ptr: cute.Pointer,\n scale_storage_ptr: cute.Pointer,\n barrier_count: cute.Tensor,\n barrier_epoch: cute.Tensor,\n pair_head: cute.Tensor,\n producers_done_count: cute.Tensor,\n all_work_published: cute.Tensor,\n task_head: cute.Tensor,\n task_tail: cute.Tensor,\n task_ready_ptr: cute.Pointer,\n task_expert_ptr: cute.Pointer,\n task_m_tile_ptr: cute.Pointer,\n task_slice_begin_ptr: cute.Pointer,\n task_slice_count_ptr: cute.Pointer,\n task_valid_rows_ptr: cute.Pointer,\n tile_write_count_ptr: cute.Pointer,\n b_w13: cute.Tensor,\n sfb_w13_ptr: cute.Pointer,\n b_down: cute.Tensor,\n sfb_down_ptr: cute.Pointer,\n row_counts: cute.Tensor,\n expert_write_rows: cute.Tensor,\n expert_tile_base: cute.Tensor,\n input_global_scale: cute.Tensor,\n alpha: cute.Tensor,\n down_alpha: cute.Tensor,\n global_scale: cute.Tensor,\n scatter_ptr: cute.Pointer,\n token_map_ptr: cute.Pointer,\n token_weights_ptr: cute.Pointer,\n num_tokens: cutlass.Int32,\n max_rows: cutlass.Int32,\n rows_padded: cutlass.Int32,\n max_tasks: cutlass.Int32,\n max_phys_tiles: cutlass.Int32,\n max_active_clusters: cutlass.Constexpr,\n stream,\n ):\n a_input = cute.make_tensor(\n a_ptr, layout=cute.make_layout((num_tokens, self._k), stride=(self._k, 1))\n )\n topk_ids = cute.make_tensor(\n topk_ids_ptr,\n layout=cute.make_layout((num_tokens * self._num_topk,), stride=(1,)),\n )\n topk_weights_t = cute.make_tensor(\n topk_weights_ptr,\n layout=cute.make_layout((num_tokens * self._num_topk,), stride=(1,)),\n )\n scatter_output = cute.make_tensor(\n scatter_ptr,\n layout=cute.make_layout((num_tokens, self._k), stride=(self._k, 1)),\n )\n packed_a = cute.make_tensor(\n packed_a_ptr,\n layout=cute.make_layout(\n (rows_padded, self._k, 1), stride=(self._k, 1, rows_padded * self._k)\n ),\n )\n packed_a_storage = cute.make_tensor(\n packed_a_storage_ptr,\n layout=cute.make_layout(\n (rows_padded * self._packed_storage_cols,), stride=(1,)\n ),\n )\n scale_storage = cute.make_tensor(\n scale_storage_ptr,\n layout=cute.make_layout((rows_padded * self._cols_pad_k,), stride=(1,)),\n )\n token_map = cute.make_tensor(\n token_map_ptr, layout=cute.make_layout((rows_padded,), stride=(1,))\n )\n token_weights_t = cute.make_tensor(\n token_weights_ptr, layout=cute.make_layout((rows_padded,), stride=(1,))\n )\n task_ready = cute.make_tensor(\n task_ready_ptr, layout=cute.make_layout((max_tasks,), stride=(1,))\n )\n task_expert = cute.make_tensor(\n task_expert_ptr, layout=cute.make_layout((max_tasks,), stride=(1,))\n )\n task_m_tile = cute.make_tensor(\n task_m_tile_ptr, layout=cute.make_layout((max_tasks,), stride=(1,))\n )\n task_slice_begin = cute.make_tensor(\n task_slice_begin_ptr, layout=cute.make_layout((max_tasks,), stride=(1,))\n )\n task_slice_count = cute.make_tensor(\n task_slice_count_ptr, layout=cute.make_layout((max_tasks,), stride=(1,))\n )\n task_valid_rows = cute.make_tensor(\n task_valid_rows_ptr, layout=cute.make_layout((max_tasks,), stride=(1,))\n )\n tile_write_count = cute.make_tensor(\n tile_write_count_ptr,\n layout=cute.make_layout((max_phys_tiles,), stride=(1,)),\n )\n self._kernel(\n a_input,\n topk_ids,\n topk_weights_t,\n packed_a,\n sfa_ptr,\n packed_a_storage,\n scale_storage,\n barrier_count,\n barrier_epoch,\n pair_head,\n producers_done_count,\n all_work_published,\n task_head,\n task_tail,\n task_ready,\n task_expert,\n task_m_tile,\n task_slice_begin,\n task_slice_count,\n task_valid_rows,\n tile_write_count,\n b_w13,\n sfb_w13_ptr,\n b_down,\n sfb_down_ptr,\n row_counts,\n expert_write_rows,\n expert_tile_base,\n input_global_scale,\n alpha,\n down_alpha,\n global_scale,\n scatter_output,\n token_map,\n token_weights_t,\n max_active_clusters=max_active_clusters,\n stream=stream,\n )\n\n\n_DYNAMIC_KERNEL_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_dynamic_kernel(\n E: int,\n m: int,\n k: int,\n n: int,\n num_topk: int,\n max_rows: int,\n *,\n topk_ids_dtype: torch.dtype = torch.int32,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n share_input_across_experts: bool = False,\n):\n \"\"\"Compile (or retrieve cached) the SM120 dynamic MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 dynamic compiler\"\n )\n share_input_across_experts = bool(\n share_input_across_experts and activation_precision == \"fp4\"\n )\n sf_vec_size = 16\n sm_count = get_num_sm(torch.device(\"cuda\"))\n mac = min(get_max_active_clusters(1), sm_count)\n mma_tiler_mn = (\n _level_tile_m(activation_precision),\n _level_tile_n(activation_precision),\n )\n\n cache_key = (\n \"dynamic\",\n activation_precision,\n E,\n k,\n n,\n num_topk,\n mac,\n mma_tiler_mn,\n topk_ids_dtype,\n input_scales_are_reciprocal,\n fast_math,\n activation,\n swiglu_alpha,\n swiglu_beta,\n swiglu_limit,\n share_input_across_experts,\n )\n cached = _DYNAMIC_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n return cached\n\n is_gated = is_gated_activation(activation)\n w1_rows = (2 if is_gated else 1) * n\n\n scratch_dtype = cutlass.Float4E2M1FN\n weight_dtype = cutlass.Float4E2M1FN\n sf_dtype = cutlass.Float8E4M3FN\n a_dtype = cutlass.BFloat16\n alpha_dtype = cutlass.Float32\n\n kernel: Any = MoEDynamicKernel(\n sf_vec_size=sf_vec_size,\n mma_tiler_mn=mma_tiler_mn,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n share_input_across_experts=share_input_across_experts,\n )\n launch = _DynamicMoELaunch(\n kernel,\n k=k,\n num_topk=num_topk,\n activation_precision=activation_precision,\n )\n\n topk_ids_cutlass_dtype = (\n cutlass.Int32 if topk_ids_dtype == torch.int32 else cutlass.Int64\n )\n topk_ids_align = 4 if topk_ids_dtype == torch.int32 else 8\n\n # Runtime-shaped tensors passed as pointers\n a_input_fake = make_ptr(a_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n topk_ids_fake = make_ptr(\n topk_ids_cutlass_dtype,\n topk_ids_align,\n cute.AddressSpace.gmem,\n assumed_align=topk_ids_align,\n )\n topk_weights_fake = make_ptr(\n cutlass.Float32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n packed_a_fake = make_ptr(\n scratch_dtype, 16, cute.AddressSpace.gmem, assumed_align=16\n )\n sfa_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n packed_a_storage_fake = make_ptr(\n cutlass.Uint8, 16, cute.AddressSpace.gmem, assumed_align=16\n )\n scale_storage_fake = make_ptr(\n cutlass.Uint8, 16, cute.AddressSpace.gmem, assumed_align=16\n )\n\n barrier_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n barrier_epoch_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n pair_head_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n producers_done_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n all_work_published_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n task_head_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n task_tail_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n\n task_ready_fake = make_ptr(\n cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n task_expert_fake = make_ptr(\n cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n task_m_tile_fake = make_ptr(\n cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n task_slice_begin_fake = make_ptr(\n cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n task_slice_count_fake = make_ptr(\n cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n task_valid_rows_fake = make_ptr(\n cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n tile_write_count_fake = make_ptr(\n cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n\n b_w13_fake = cute.runtime.make_fake_compact_tensor(\n weight_dtype,\n (w1_rows, k, E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_w13_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n b_down_fake = cute.runtime.make_fake_compact_tensor(\n weight_dtype,\n (k, n, E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_down_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n row_counts_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (E,), assumed_align=4\n )\n expert_write_rows_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (E,), assumed_align=4\n )\n expert_tile_base_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (E + 1,), assumed_align=4\n )\n input_gs_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype, (E,), assumed_align=16\n )\n alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype, (E,), assumed_align=16\n )\n down_alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype, (E,), assumed_align=16\n )\n global_scale_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype, (E,), assumed_align=16\n )\n scatter_fake = make_ptr(a_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n token_map_fake = make_ptr(cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4)\n token_weights_fake = make_ptr(\n alpha_dtype, 16, cute.AddressSpace.gmem, assumed_align=16\n )\n\n compiled = cute.compile(\n launch,\n a_input_fake,\n topk_ids_fake,\n topk_weights_fake,\n packed_a_fake,\n sfa_fake,\n packed_a_storage_fake,\n scale_storage_fake,\n barrier_count_fake,\n barrier_epoch_fake,\n pair_head_fake,\n producers_done_count_fake,\n all_work_published_fake,\n task_head_fake,\n task_tail_fake,\n task_ready_fake,\n task_expert_fake,\n task_m_tile_fake,\n task_slice_begin_fake,\n task_slice_count_fake,\n task_valid_rows_fake,\n tile_write_count_fake,\n b_w13_fake,\n sfb_w13_fake,\n b_down_fake,\n sfb_down_fake,\n row_counts_fake,\n expert_write_rows_fake,\n expert_tile_base_fake,\n input_gs_fake,\n alpha_fake,\n down_alpha_fake,\n global_scale_fake,\n scatter_fake,\n token_map_fake,\n token_weights_fake,\n 1,\n 1,\n 1,\n 1,\n 1, # runtime Int32 placeholders\n mac,\n current_cuda_stream(),\n options=\"--opt-level 2 --enable-tvm-ffi\",\n )\n\n result = (compiled, mac)\n _DYNAMIC_KERNEL_CACHE[cache_key] = result\n return result\n\n\n# ---------------------------------------------------------------------------\n# Dynamic launch\n# ---------------------------------------------------------------------------\ndef launch_sm120_dynamic_moe(\n *,\n workspace: Sm120DynamicMoEWorkspace,\n weights: _WeightViews,\n a: torch.Tensor,\n topk_ids: torch.Tensor,\n topk_weights: torch.Tensor,\n input_gs: torch.Tensor,\n down_input_scale: torch.Tensor,\n scatter_output: torch.Tensor,\n num_experts: int,\n num_tokens: int,\n k: int,\n n: int,\n top_k: int,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n) -> torch.Tensor:\n \"\"\"Launch the SM120 dynamic MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 dynamic launcher\"\n )\n flat_ids = topk_ids.view(-1).to(torch.int32)\n flat_weights = topk_weights.view(-1).to(torch.float32)\n input_gs_is_shared = input_gs.numel() == 1\n\n # Broadcast scalar scales to per-expert [E] tensors\n input_gs = _expand_to_experts(input_gs, num_experts)\n down_input_scale = _expand_to_experts(down_input_scale, num_experts)\n\n compiled, mac = _get_dynamic_kernel(\n num_experts,\n num_tokens,\n k,\n n,\n top_k,\n workspace.max_rows,\n topk_ids_dtype=torch.int32,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n activation_precision=activation_precision,\n share_input_across_experts=input_gs_is_shared,\n )\n\n # Dynamic kernel: runtime-shaped args are DataPointer (pass data_ptr()),\n # fixed-shape args are Tensor (pass torch tensor directly).\n runtime_args: Tuple[Any, ...] = (\n a.data_ptr(),\n flat_ids.data_ptr(),\n flat_weights.data_ptr(),\n workspace.packed_a_view.data_ptr(),\n workspace.packed_input_scale.data_ptr(),\n workspace.packed_a_flat.data_ptr(),\n workspace.scale_flat.data_ptr(),\n workspace.barrier_count,\n workspace.barrier_epoch,\n workspace.pair_head,\n workspace.producers_done_count,\n workspace.all_work_published,\n workspace.task_head,\n workspace.task_tail,\n workspace.task_ready.data_ptr(),\n workspace.task_expert.data_ptr(),\n workspace.task_m_tile.data_ptr(),\n workspace.task_slice_begin.data_ptr(),\n workspace.task_slice_count.data_ptr(),\n workspace.task_valid_rows.data_ptr(),\n workspace.tile_write_count.data_ptr(),\n weights.w13_fp4,\n weights._w13_sf_storage.data_ptr(),\n weights.down_fp4,\n weights._down_sf_storage.data_ptr(),\n workspace.row_counts,\n workspace.expert_write_rows,\n workspace.expert_tile_base,\n input_gs,\n weights.w1_alpha,\n weights.w2_alpha,\n down_input_scale,\n scatter_output.data_ptr(),\n workspace.token_map.data_ptr(),\n workspace.token_weights.data_ptr(),\n num_tokens,\n workspace.max_rows,\n workspace.physical_tiles_capacity * _level_tile_m(activation_precision),\n workspace.task_capacity,\n workspace.physical_tiles_capacity,\n )\n compiled(*runtime_args, current_cuda_stream())\n\n return scatter_output\n\n\n# ==========================================================================\n# W4A16 route-packing implementation\n# ==========================================================================\n@dataclass(kw_only=True)\nclass Sm120W4A16MoEWorkspace:\n \"\"\"Scratch buffers for the SM120 W4A16 MoE path.\"\"\"\n\n state_E: int\n weight_E: int\n max_rows: int\n k: int\n n: int\n num_topk: int\n device: torch.device\n activation: str\n activation_precision: str\n quant_mode: str\n routed_rows_capacity: int\n route_num_experts: int\n\n intermediate_cache13: torch.Tensor\n intermediate_cache2: torch.Tensor\n fc1_c_tmp: torch.Tensor\n fc2_c_tmp: torch.Tensor\n packed_route_indices: torch.Tensor\n block_expert_ids: torch.Tensor\n packed_route_count: torch.Tensor\n expert_offsets: torch.Tensor\n expert_map: torch.Tensor | None = None\n\n\ndef _is_cuda_graph_capturing() -> bool:\n try:\n return bool(torch.cuda.is_current_stream_capturing())\n except Exception:\n return False\n\n\ndef _canonical_cuda_device(device: torch.device) -> torch.device:\n device = torch.device(device)\n if device.type == \"cuda\" and device.index is None:\n return torch.device(\"cuda\", torch.cuda.current_device())\n return device\n\n\ndef _w4a16_workspace_geometry(\n *,\n routed_rows: int,\n route_num_experts: int,\n k: int,\n n: int,\n is_gated: bool,\n device: torch.device,\n) -> tuple[int, int, int, int, int]:\n route_slots = 1\n route_blocks = 1\n fc1_c_tmp_elements = 1\n fc2_c_tmp_elements = 1\n fc1_cols = (2 if is_gated else 1) * int(n)\n sms = get_num_sm(device)\n for block_size in _W4A16_ALLOWED_ROUTED_SIZES:\n slots = max_packed_route_slots(\n int(routed_rows),\n int(block_size),\n int(route_num_experts),\n )\n blocks = (slots + int(block_size) - 1) // int(block_size)\n route_slots = max(route_slots, slots)\n route_blocks = max(route_blocks, blocks)\n fc1_c_tmp_elements = max(\n fc1_c_tmp_elements,\n packed_gemm_scratch_elements(\n size_n=fc1_cols,\n route_slots=slots,\n moe_block_size=int(block_size),\n sms=sms,\n ),\n )\n fc2_c_tmp_elements = max(\n fc2_c_tmp_elements,\n packed_gemm_scratch_elements(\n size_n=int(k),\n route_slots=slots,\n moe_block_size=int(block_size),\n sms=sms,\n ),\n )\n return (\n route_slots,\n route_blocks,\n fc1_c_tmp_elements,\n fc2_c_tmp_elements,\n fc1_cols,\n )\n\n\ndef _make_w4a16_expert_map(\n *,\n state_E: int,\n weight_E: int,\n device: torch.device,\n) -> torch.Tensor | None:\n if int(state_E) == int(weight_E):\n return None\n if int(state_E) > int(weight_E):\n raise ValueError(\"num_local_experts cannot exceed num_experts\")\n expert_map = torch.empty((int(weight_E),), dtype=torch.int32, device=device)\n expert_map.fill_(-1)\n expert_map[: int(state_E)].copy_(\n torch.arange(int(state_E), dtype=torch.int32, device=device)\n )\n return expert_map\n\n\ndef _allocate_sm120_w4a16_workspace(\n *,\n state_E: int,\n weight_E: int,\n routed_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation: str = \"silu\",\n) -> Sm120W4A16MoEWorkspace:\n is_gated = validate_activation(activation)\n routed_rows = max(1, int(routed_rows))\n route_num_experts = int(weight_E) if int(state_E) != int(weight_E) else int(state_E)\n (\n route_slots,\n route_blocks,\n fc1_c_tmp_elements,\n fc2_c_tmp_elements,\n fc1_cols,\n ) = _w4a16_workspace_geometry(\n routed_rows=routed_rows,\n route_num_experts=route_num_experts,\n k=k,\n n=n,\n is_gated=is_gated,\n device=device,\n )\n return Sm120W4A16MoEWorkspace(\n state_E=int(state_E),\n weight_E=int(weight_E),\n max_rows=routed_rows,\n k=int(k),\n n=int(n),\n num_topk=int(num_topk),\n device=device,\n activation=activation,\n activation_precision=\"bf16\",\n quant_mode=\"w4a16\",\n routed_rows_capacity=routed_rows,\n route_num_experts=route_num_experts,\n intermediate_cache13=torch.empty(\n (routed_rows * max(fc1_cols, int(k)),),\n dtype=torch.bfloat16,\n device=device,\n ),\n intermediate_cache2=torch.empty(\n (routed_rows, int(n)),\n dtype=torch.bfloat16,\n device=device,\n ),\n fc1_c_tmp=torch.empty(\n (fc1_c_tmp_elements,),\n dtype=torch.float32,\n device=device,\n ),\n fc2_c_tmp=torch.empty(\n (fc2_c_tmp_elements,),\n dtype=torch.float32,\n device=device,\n ),\n packed_route_indices=torch.empty(\n (route_slots,),\n dtype=torch.int32,\n device=device,\n ),\n block_expert_ids=torch.empty(\n (route_blocks,),\n dtype=torch.int32,\n device=device,\n ),\n packed_route_count=torch.empty((1,), dtype=torch.int32, device=device),\n expert_offsets=torch.empty(\n (route_num_experts + 1,),\n dtype=torch.int32,\n device=device,\n ),\n expert_map=_make_w4a16_expert_map(\n state_E=state_E,\n weight_E=weight_E,\n device=device,\n ),\n )\n\n\n_W4A16_WEIGHT_CACHE: Dict[Tuple, W4A16PackedWeights] = {}\n\n\ndef _get_w4a16_packed_weights(\n *,\n w1_weight: torch.Tensor,\n w1_weight_sf: torch.Tensor,\n w1_alpha: torch.Tensor,\n w2_weight: torch.Tensor,\n w2_weight_sf: torch.Tensor,\n w2_alpha: torch.Tensor,\n activation: str,\n params_dtype: torch.dtype,\n source_format: str = \"modelopt\",\n) -> W4A16PackedWeights:\n key = (\n activation,\n params_dtype,\n source_format,\n tuple(w1_weight.shape),\n tuple(w1_weight_sf.shape),\n tuple(w1_alpha.shape),\n tuple(w2_weight.shape),\n tuple(w2_weight_sf.shape),\n tuple(w2_alpha.shape),\n w1_weight.data_ptr(),\n w1_weight_sf.data_ptr(),\n w1_alpha.data_ptr(),\n w2_weight.data_ptr(),\n w2_weight_sf.data_ptr(),\n w2_alpha.data_ptr(),\n )\n cached = _W4A16_WEIGHT_CACHE.get(key)\n if cached is not None:\n return cached\n if _is_cuda_graph_capturing():\n raise RuntimeError(\n \"W4A16 packed weights are not initialized for CUDA graph capture; \"\n \"run once before capture so the prepared weights are cached.\"\n )\n prepared = prepare_w4a16_packed_weights(\n w1_weight,\n w1_weight_sf,\n w1_alpha,\n w2_weight,\n w2_weight_sf,\n w2_alpha,\n activation=activation,\n params_dtype=params_dtype,\n source_format=source_format,\n )\n _W4A16_WEIGHT_CACHE[key] = prepared\n _register_cache_eviction(\n _W4A16_WEIGHT_CACHE,\n key,\n w1_weight,\n w1_weight_sf,\n w1_alpha,\n w2_weight,\n w2_weight_sf,\n w2_alpha,\n )\n return prepared\n\n\ndef _validate_w4a16_workspace(\n workspace: Sm120W4A16MoEWorkspace,\n *,\n state_E: int,\n weight_E: int,\n routed_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation: str,\n) -> None:\n validate_activation(activation)\n if workspace.state_E != int(state_E) or workspace.weight_E != int(weight_E):\n raise ValueError(\"pre-allocated W4A16 workspace expert geometry mismatch\")\n if workspace.k != int(k) or workspace.n != int(n):\n raise ValueError(\"pre-allocated W4A16 workspace hidden geometry mismatch\")\n if workspace.num_topk != int(num_topk):\n raise ValueError(\"pre-allocated W4A16 workspace top-k mismatch\")\n if getattr(workspace, \"activation\", None) != activation:\n raise ValueError(\"pre-allocated W4A16 workspace activation mismatch\")\n if _canonical_cuda_device(workspace.device) != _canonical_cuda_device(device):\n raise ValueError(\n f\"pre-allocated W4A16 workspace is on {workspace.device}, expected {device}\"\n )\n if workspace.routed_rows_capacity < max(1, int(routed_rows)):\n raise ValueError(\n \"pre-allocated W4A16 workspace is too small for the requested \"\n f\"routed rows ({workspace.routed_rows_capacity} < {routed_rows})\"\n )\n\n\ndef _launch_sm120_w4a16_moe(\n *,\n a: torch.Tensor,\n topk_ids: torch.Tensor,\n topk_weights: torch.Tensor,\n w1_weight: torch.Tensor,\n w1_weight_sf: torch.Tensor,\n w1_alpha: torch.Tensor,\n w2_weight: torch.Tensor,\n w2_weight_sf: torch.Tensor,\n w2_alpha: torch.Tensor,\n num_experts: int,\n top_k: int,\n num_local_experts: int,\n scatter_output: torch.Tensor,\n fast_math: bool = True,\n activation: str = \"silu\",\n source_format: str = \"modelopt\",\n _workspace=None,\n _prepared_weights=None,\n) -> torch.Tensor:\n prepared = (\n _prepared_weights\n if isinstance(_prepared_weights, W4A16PackedWeights)\n else _get_w4a16_packed_weights(\n w1_weight=w1_weight,\n w1_weight_sf=w1_weight_sf,\n w1_alpha=w1_alpha,\n w2_weight=w2_weight,\n w2_weight_sf=w2_weight_sf,\n w2_alpha=w2_alpha,\n activation=activation,\n params_dtype=a.dtype,\n source_format=source_format,\n )\n )\n if int(prepared.num_experts) != int(num_local_experts):\n raise ValueError(\"num_local_experts must match w1_weight.shape[0] for W4A16.\")\n num_tokens = int(topk_ids.size(0))\n routed_rows = num_tokens * int(top_k)\n k = int(a.size(1))\n n = int(prepared.intermediate_size)\n\n if _workspace is None:\n workspace = _get_cached_workspace(\n backend=\"w4a16\",\n state_E=num_local_experts,\n weight_E=num_experts,\n routed_rows=routed_rows,\n k=k,\n n=n,\n num_topk=top_k,\n device=a.device,\n quant_mode=\"w4a16\",\n activation=activation,\n )\n else:\n workspace = _workspace\n if not isinstance(workspace, Sm120W4A16MoEWorkspace):\n raise TypeError(\"expected a W4A16 workspace for quant_mode='w4a16'\")\n _validate_w4a16_workspace(\n workspace,\n state_E=num_local_experts,\n weight_E=num_experts,\n routed_rows=routed_rows,\n k=k,\n n=n,\n num_topk=top_k,\n device=a.device,\n activation=activation,\n )\n\n return run_w4a16_moe(\n a,\n prepared,\n topk_weights,\n topk_ids,\n activation=activation,\n intermediate_cache13=workspace.intermediate_cache13,\n intermediate_cache2=workspace.intermediate_cache2,\n output=scatter_output,\n fc1_c_tmp=workspace.fc1_c_tmp,\n fc2_c_tmp=workspace.fc2_c_tmp,\n packed_route_indices=workspace.packed_route_indices,\n block_expert_ids=workspace.block_expert_ids,\n packed_route_count=workspace.packed_route_count,\n expert_offsets=workspace.expert_offsets,\n expert_map=workspace.expert_map,\n fast_math=fast_math,\n )\n\n\n# ==========================================================================\n# Workspace cache (for functional API path)\n# ==========================================================================\n\n_Sm120Workspace = Union[\n Sm120StaticMoEWorkspace,\n Sm120DynamicMoEWorkspace,\n Sm120W4A16MoEWorkspace,\n]\n\n# Keyed by (state_E, weight_E, k, n, top_k, device, backend).\n# Stores the workspace with the largest max_rows seen for each key.\n# Grows monotonically — never shrinks within a process.\n_WORKSPACE_CACHE: Dict[Tuple, _Sm120Workspace] = {}\n\n\ndef allocate_sm120_moe_workspace(\n *,\n state_E: int,\n weight_E: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n max_rows: int | None = None,\n routed_rows: int | None = None,\n quant_mode: str | None = None,\n activation_precision: str | None = None,\n backend: str | None = None,\n activation: str = \"silu\",\n) -> _Sm120Workspace:\n \"\"\"Allocate the right SM120 MoE workspace from a quantization mode.\"\"\"\n mode = _normalize_quant_mode(quant_mode, activation_precision)\n capacity_rows = routed_rows if routed_rows is not None else max_rows\n if capacity_rows is None:\n raise ValueError(\"routed_rows or max_rows is required\")\n capacity_rows = max(1, int(capacity_rows))\n device = torch.device(device)\n\n if mode == \"w4a16\":\n if backend not in (None, \"w4a16\"):\n raise ValueError(\"quant_mode='w4a16' does not use static/dynamic backend\")\n return _allocate_sm120_w4a16_workspace(\n state_E=state_E,\n weight_E=weight_E,\n routed_rows=capacity_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation=activation,\n )\n\n activation_precision = \"fp4\"\n if backend is None:\n backend = select_sm120_moe_backend(\n num_tokens=max(\n 1, (capacity_rows + max(1, int(num_topk)) - 1) // max(1, int(num_topk))\n ),\n num_topk=int(num_topk),\n activation_precision=activation_precision,\n )\n if backend == \"dynamic\":\n return allocate_sm120_dynamic_workspace(\n state_E=state_E,\n weight_E=weight_E,\n routed_rows=capacity_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation_precision=activation_precision,\n )\n if backend == \"static\":\n return allocate_sm120_static_workspace(\n state_E=state_E,\n weight_E=weight_E,\n max_rows=capacity_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation_precision=activation_precision,\n )\n raise ValueError(f\"unsupported SM120 MoE backend {backend!r}\")\n\n\ndef _get_cached_workspace(\n *,\n backend: str,\n state_E: int,\n weight_E: int,\n routed_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation_precision: str = \"fp4\",\n quant_mode: str | None = None,\n activation: str = \"silu\",\n) -> _Sm120Workspace:\n \"\"\"Get or allocate a cached workspace for the given problem shape.\n\n Reuses the cached workspace if it has enough capacity for the requested\n routed_rows. For static workspaces, max_rows is the direct capacity.\n For dynamic workspaces, routed_rows_capacity is used because the dynamic\n geometry (physical tiles, task queue slots) depends on the original\n routed_rows, not just max_rows.\n \"\"\"\n quant_mode = _normalize_quant_mode(quant_mode, activation_precision)\n activation_precision = _activation_precision_from_quant_mode(quant_mode)\n cache_key = (\n state_E,\n weight_E,\n k,\n n,\n num_topk,\n str(device),\n backend,\n quant_mode,\n activation,\n )\n cached = _WORKSPACE_CACHE.get(cache_key)\n\n if cached is not None:\n if isinstance(cached, (Sm120DynamicMoEWorkspace, Sm120W4A16MoEWorkspace)):\n if cached.routed_rows_capacity >= max(1, routed_rows): # type: ignore[union-attr]\n return cached\n else:\n if cached.max_rows >= max(1, routed_rows):\n return cached\n\n if quant_mode == \"w4a16\" and _is_cuda_graph_capturing():\n raise RuntimeError(\n \"W4A16 workspace is not initialized for CUDA graph capture; \"\n \"provide a preallocated workspace from \"\n \"allocate_sm120_moe_workspace(..., quant_mode='w4a16') or warm the \"\n \"functional path before capture.\"\n )\n workspace = allocate_sm120_moe_workspace(\n state_E=state_E,\n weight_E=weight_E,\n routed_rows=routed_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n quant_mode=quant_mode,\n activation_precision=activation_precision,\n backend=backend,\n activation=activation,\n )\n\n _WORKSPACE_CACHE[cache_key] = workspace\n return workspace\n\n\n# ==========================================================================\n# Unified dispatch\n# ==========================================================================\n_PADDED_WEIGHT_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _pad_intermediate_to_tile(\n w1_weight,\n w1_weight_sf,\n w2_weight,\n w2_weight_sf,\n fc2_input_scale,\n n,\n tile,\n h,\n num_experts,\n is_gated,\n):\n \"\"\"Zero-pad NVFP4 weights + scale factors so the intermediate size is a\n multiple of ``tile`` (gate/up tile-split requirement); padded channels are\n zero, so the result is numerically identical.\n \"\"\"\n n_pad = ((n + tile - 1) // tile) * tile\n if n_pad == n:\n return w1_weight, w1_weight_sf, w2_weight, w2_weight_sf, fc2_input_scale, n\n E = int(num_experts)\n fc2_input_scale_src = fc2_input_scale\n key = (\n n,\n tile,\n h,\n E,\n bool(is_gated),\n w1_weight.data_ptr(),\n w1_weight_sf.data_ptr(),\n w2_weight.data_ptr(),\n w2_weight_sf.data_ptr(),\n fc2_input_scale_src.data_ptr() if fc2_input_scale_src is not None else 0,\n )\n cached = _PADDED_WEIGHT_CACHE.get(key)\n if cached is not None:\n return cached\n\n def mma_to_logical(sf, m, k):\n sw = convert_sf_from_mma_layout(sf, m=m, k=k, num_groups=E)\n m_pad = ((m + 127) // 128) * 128\n sw = sw.reshape(E, m_pad, -1)\n cb = (k + SF_VEC_SIZE - 1) // SF_VEC_SIZE\n return torch.stack(\n [unswizzle_block_scale(sw[e], rows=m, cols_blocks=cb) for e in range(E)], 0\n )\n\n def logical_to_mma(log, m, k):\n sw = torch.stack([swizzle_block_scale(log[e]) for e in range(E)], 0)\n sw2d = sw.reshape(E * sw.shape[1], sw.shape[2]).to(torch.float8_e4m3fn)\n return convert_sf_to_mma_layout(sw2d, m=m, k=k, num_groups=E)\n\n def pad_dim(t, dim, old, new):\n if new == old:\n return t\n shp = list(t.shape)\n shp[dim] = new - old\n return torch.cat([t, t.new_zeros(shp)], dim=dim)\n\n if is_gated:\n # w1 packs [up(0:n), gate(n:2n)] rows; pad each half so the split stays\n # tile-aligned, then re-concat.\n up, gate = w1_weight[:, :n, :], w1_weight[:, n : 2 * n, :]\n w1p = torch.cat([pad_dim(up, 1, n, n_pad), pad_dim(gate, 1, n, n_pad)], dim=1)\n log1 = mma_to_logical(w1_weight_sf, m=2 * n, k=h)\n up_sf, gate_sf = log1[:, :n, :], log1[:, n : 2 * n, :]\n log1p = torch.cat(\n [pad_dim(up_sf, 1, n, n_pad), pad_dim(gate_sf, 1, n, n_pad)], dim=1\n )\n w1_sf_p = logical_to_mma(log1p, m=2 * n_pad, k=h)\n else:\n w1p = pad_dim(w1_weight, 1, n, n_pad)\n log1 = mma_to_logical(w1_weight_sf, m=n, k=h)\n w1_sf_p = logical_to_mma(pad_dim(log1, 1, n, n_pad), m=n_pad, k=h)\n\n # w2 reduces over the intermediate dim: pad its packed columns + SF columns.\n w2p = pad_dim(w2_weight, 2, n // 2, n_pad // 2)\n log2 = mma_to_logical(w2_weight_sf, m=h, k=n)\n cb_n = (n + SF_VEC_SIZE - 1) // SF_VEC_SIZE\n cb_np = (n_pad + SF_VEC_SIZE - 1) // SF_VEC_SIZE\n w2_sf_p = logical_to_mma(pad_dim(log2, 2, cb_n, cb_np), m=h, k=n_pad)\n\n if fc2_input_scale_src is not None and fc2_input_scale_src.numel() == n:\n fc2_input_scale = pad_dim(fc2_input_scale_src, 0, n, n_pad)\n result = (w1p, w1_sf_p, w2p, w2_sf_p, fc2_input_scale, n_pad)\n _PADDED_WEIGHT_CACHE[key] = result\n _register_cache_eviction(\n _PADDED_WEIGHT_CACHE,\n key,\n w1_weight,\n w1_weight_sf,\n w2_weight,\n w2_weight_sf,\n fc2_input_scale_src,\n )\n return result\n\n\ndef launch_sm120_moe(\n *,\n a: torch.Tensor,\n topk_ids: torch.Tensor,\n topk_weights: torch.Tensor,\n w1_weight: torch.Tensor,\n w1_weight_sf: torch.Tensor,\n w1_alpha: torch.Tensor,\n fc2_input_scale: Optional[torch.Tensor] = None,\n input_global_scale: Optional[torch.Tensor] = None,\n w2_weight: torch.Tensor,\n w2_weight_sf: torch.Tensor,\n w2_alpha: torch.Tensor,\n num_experts: int,\n top_k: int,\n num_local_experts: int,\n scatter_output: torch.Tensor,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n quant_mode: str | None = None,\n source_format: str = \"modelopt\",\n _workspace=None,\n _weight_views=None,\n _prepared_weights=None,\n) -> torch.Tensor:\n \"\"\"Unified SM120 MoE dispatch — selects static or dynamic by token count.\n\n input_global_scale overrides w1_alpha as the FC1 input-quant scale and\n is folded into the multiplier internally. With _weight_views supplied,\n w1_alpha must already contain the fold.\n\n Optional _workspace and _weight_views can be pre-allocated and reused\n across calls to avoid per-call allocation overhead (wrapper path).\n When not provided (functional API path), a module-level workspace cache\n is used to avoid re-allocating on every call.\n \"\"\"\n quant_mode = _normalize_quant_mode(quant_mode, activation_precision)\n source_format = _normalize_source_format_for_quant_mode(source_format, quant_mode)\n activation_precision = _activation_precision_from_quant_mode(quant_mode)\n\n num_tokens = topk_ids.size(0)\n k = a.size(1) # hidden_size\n is_gated = is_gated_activation(activation)\n # w1_weight.size(1) is 2*n for gated or n for non-gated\n intermediate_size = w1_weight.size(1) // 2 if is_gated else w1_weight.size(1)\n n = intermediate_size\n\n # NVFP4 kernels need padded intermediate size.\n if quant_mode != \"w4a16\" and n % _LEVEL_TILE_N != 0 and _weight_views is None:\n (\n w1_weight,\n w1_weight_sf,\n w2_weight,\n w2_weight_sf,\n fc2_input_scale,\n n,\n ) = _pad_intermediate_to_tile(\n w1_weight,\n w1_weight_sf,\n w2_weight,\n w2_weight_sf,\n fc2_input_scale,\n n,\n _LEVEL_TILE_N,\n k,\n w1_weight.size(0),\n is_gated,\n )\n\n routed_rows = num_tokens * top_k\n\n if quant_mode == \"w4a16\":\n return _launch_sm120_w4a16_moe(\n a=a,\n topk_ids=topk_ids,\n topk_weights=topk_weights,\n w1_weight=w1_weight,\n w1_weight_sf=w1_weight_sf,\n w1_alpha=w1_alpha,\n w2_weight=w2_weight,\n w2_weight_sf=w2_weight_sf,\n w2_alpha=w2_alpha,\n num_experts=num_experts,\n top_k=top_k,\n num_local_experts=num_local_experts,\n scatter_output=scatter_output,\n fast_math=fast_math,\n activation=activation,\n source_format=source_format,\n _workspace=_workspace,\n _prepared_weights=_prepared_weights,\n )\n\n if fc2_input_scale is None:\n raise ValueError(\"fc2_input_scale is required when quant_mode='nvfp4'.\")\n down_input_scale = fc2_input_scale\n if input_global_scale is not None:\n input_gs = input_global_scale\n if _weight_views is None:\n # Alpha must carry input_gs back or the output magnitude is wrong.\n # The wrapper folds before building _weight_views; don't fold twice.\n w1_alpha = (\n w1_alpha.to(torch.float32) * input_global_scale.to(torch.float32)\n ).contiguous()\n else:\n input_gs = w1_alpha\n\n weights = (\n _weight_views\n if _weight_views is not None\n else _get_weight_views(\n w1_fp4=w1_weight,\n w1_blockscale=w1_weight_sf,\n w2_fp4=w2_weight,\n w2_blockscale=w2_weight_sf,\n w1_alphas=w1_alpha,\n w2_alphas=w2_alpha,\n n=n,\n k=k,\n activation_precision=activation_precision,\n )\n )\n\n # Resolve workspace and backend selection.\n # When a pre-allocated workspace is provided (CUDA graph wrapper path),\n # infer the backend from the workspace type so they stay in sync —\n # the caller already committed to a backend at allocation time.\n if _workspace is not None:\n workspace = _workspace\n workspace_activation_precision = getattr(\n workspace, \"activation_precision\", activation_precision\n )\n if workspace_activation_precision != activation_precision:\n raise ValueError(\n \"pre-allocated workspace activation_precision does not match \"\n f\"requested activation_precision={activation_precision!r}.\"\n )\n if isinstance(workspace, Sm120DynamicMoEWorkspace):\n if num_local_experts != num_experts:\n raise ValueError(\n \"pre-allocated dynamic SM120 MoE workspace requires \"\n \"num_local_experts == num_experts because dynamic expert \"\n \"buffers are indexed by global topk ids.\"\n )\n backend = \"dynamic\"\n else:\n backend = \"static\"\n else:\n backend = select_sm120_moe_backend(\n num_tokens=num_tokens,\n num_topk=top_k,\n activation_precision=activation_precision,\n )\n # The dynamic kernel indexes row_counts/expert_write_rows directly with\n # topk_ids but those buffers are sized with num_local_experts. Unless\n # num_local_experts == num_experts, fall back to the static backend which\n # has global-to-local expert remapping.\n if backend == \"dynamic\" and num_local_experts != num_experts:\n backend = \"static\"\n workspace = _get_cached_workspace(\n backend=backend,\n state_E=num_local_experts,\n weight_E=num_experts,\n routed_rows=routed_rows,\n k=k,\n n=n,\n num_topk=top_k,\n device=a.device,\n activation_precision=activation_precision,\n quant_mode=quant_mode,\n activation=activation,\n )\n\n if backend == \"dynamic\":\n return launch_sm120_dynamic_moe(\n workspace=workspace,\n weights=weights,\n a=a,\n topk_ids=topk_ids,\n topk_weights=topk_weights,\n input_gs=input_gs,\n down_input_scale=down_input_scale,\n scatter_output=scatter_output,\n num_experts=num_experts,\n num_tokens=num_tokens,\n k=k,\n n=n,\n top_k=top_k,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n activation_precision=activation_precision,\n )\n else:\n return launch_sm120_static_moe(\n workspace=workspace,\n weights=weights,\n a=a,\n topk_ids=topk_ids,\n topk_weights=topk_weights,\n input_gs=input_gs,\n down_input_scale=down_input_scale,\n scatter_output=scatter_output,\n num_experts=num_experts,\n num_tokens=num_tokens,\n k=k,\n n=n,\n top_k=top_k,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n activation_precision=activation_precision,\n )\n"},"after_code":{"kind":"string","value":"\"\"\"SM120/SM121 MoE dispatch layer — workspace, compilation, and launch.\n\nPorted from b12x's integration/tp_moe.py. Supports micro (tiny decode),\nstatic (decode), and dynamic (prefill) backends with token-count-based\nselection.\n\"\"\"\n\nfrom __future__ import annotations\n\nimport os\nimport weakref\nfrom dataclasses import dataclass\nfrom typing import Any, Dict, Optional, Tuple, Union\n\nimport cutlass\nimport cutlass.cute as cute\nimport torch\n\nfrom flashinfer.cute_dsl.utils import (\n convert_sf_from_mma_layout,\n convert_sf_to_mma_layout,\n current_cuda_stream,\n get_max_active_clusters,\n get_num_sm,\n make_ptr,\n)\nfrom .moe_activation import SWIGLUOAI_UNINTERLEAVE, is_gated_activation\nfrom .moe_direct_micro_kernel import (\n MoEDirectMicroKernel,\n build_direct_micro_kernel,\n compile_direct_micro_kernel,\n compiled_direct_micro_accepts_block_dim,\n)\nfrom .moe_dynamic_kernel import _TASK_SLICE_CHUNK, MoEDynamicKernel\nfrom .moe_micro_kernel import MoEMicroKernel\nfrom .moe_static_kernel import MoEStaticKernel\nfrom .moe_w4a16_fp4_helpers import swizzle_block_scale\nfrom .moe_w4a16_host import (\n _W4A16_ALLOWED_ROUTED_SIZES,\n max_packed_route_slots,\n packed_gemm_scratch_elements,\n unswizzle_block_scale,\n validate_activation,\n)\nfrom .moe_w4a16_kernel import run_w4a16_moe\nfrom .moe_w4a16_prepare import (\n W4A16PackedWeights,\n _normalize_source_format,\n prepare_w4a16_packed_weights,\n)\n\n# ---------------------------------------------------------------------------\n# Constants\n# ---------------------------------------------------------------------------\n_NVFP4_BLOCK_SIZE = 16\n_LEVEL_TILE_M = 128\n_LEVEL_TILE_N = 128\n# Must equal the kernel's task materialization granularity or the task\n# queue is mis-sized.\n_DYNAMIC_SLICE_CHUNK = _TASK_SLICE_CHUNK\nSF_VEC_SIZE = 16\n_FORCE_MOE_W4A16_ENV = \"FLASHINFER_B12X_FORCE_MOE_W4A16\"\n_MICRO_SHARE_INPUT_ACROSS_EXPERTS = (\n os.environ.get(\"FLASHINFER_B12X_MICRO_SHARE_INPUT\", \"1\") != \"0\"\n)\n\n# Micro kernel cutover thresholds (routed pairs)\n_MICRO_COMPACT_CUTOVER_PAIRS = 20\n_MICRO_COMPACT_CUTOVER_PAIRS_MULTI_TOPK = 40\n# The micro kernel's per-token staging assumes decode-sized batches.\n_MICRO_MAX_TOKENS = 8\n# Direct micro takes the smallest decode batches ahead of the MMA micro\n# kernel, and only at small intermediate sizes where its CUDA-core dots\n# keep up with per-token work. Measured on GB10, pending other GPUs.\n_DIRECT_MICRO_CUTOVER_PAIRS = 32\n_DIRECT_MICRO_MAX_N = 512\n# Test/bench hook: force one backend (\"direct_micro\", \"micro\", \"static\",\n# \"dynamic\"). Deliberately module-level (a monkeypatch target), not an env var.\n_FORCED_BACKEND: str | None = None\n_STATIC_COMPACT_CUTOVER_PAIRS_DEFAULT = 640\n_STATIC_COMPACT_CUTOVER_PAIRS = _STATIC_COMPACT_CUTOVER_PAIRS_DEFAULT\n_STATIC_COMPACT_CUTOVER_PAIRS_CACHE: Dict[str, int] = {}\n\n# MAC (max active clusters) tuning ladders from b12x decode profiling.\n# Each entry is (max_routed_rows, optimal_mac).\n_MICRO_MAC_LADDER: Tuple[Tuple[int, int], ...] = (\n (2, 84),\n (4, 127),\n (8, 107),\n (10, 84),\n (16, 63),\n (20, 84),\n)\n_STATIC_MAC_LADDER: Tuple[Tuple[int, int], ...] = (\n (24, 148),\n (32, 169),\n (40, 132),\n (48, 149),\n (64, 134),\n (80, 175),\n (96, 171),\n (120, 125),\n (128, 130),\n (160, 171),\n (192, 166),\n (256, 141),\n (320, 158),\n (512, 175),\n (640, 188),\n)\n# Workloads at or below the static cutover (640 routed pairs by default)\n# take the static kernel, so only the 1024 entry is normally reachable.\n_DYNAMIC_MAC_LADDER: Tuple[Tuple[int, int], ...] = (\n (640, 188),\n (1024, 147),\n)\n\n\ndef _lookup_mac_ladder(\n ladder: Tuple[Tuple[int, int], ...], routed_rows: int\n) -> int | None:\n \"\"\"Look up optimal MAC from a tuning ladder. Returns None if no match.\"\"\"\n for end_rows, mac in ladder:\n if routed_rows <= end_rows:\n return mac\n return None\n\n\ndef _align_up(value: int, alignment: int) -> int:\n return ((value + alignment - 1) // alignment) * alignment\n\n\n# The kernels index the packed activation and scale planes with 32-bit\n# offsets, so reject any workspace plane large enough to overflow them.\n_RUNTIME_MEMREF_LIMIT = (1 << 31) - 1\n\n\ndef _check_memref_limit(name: str, elements: int) -> None:\n if elements > _RUNTIME_MEMREF_LIMIT:\n raise ValueError(\n f\"{name} needs {elements} elements, which exceeds the 2^31-1 \"\n \"runtime memref limit. Reduce the token chunk or expert count \"\n \"for this launch.\"\n )\n\n\ndef _first_env(*names: str) -> str | None:\n for name in names:\n value = os.environ.get(name)\n if value is not None:\n return value\n return None\n\n\ndef _normalize_activation_precision(activation_precision: str) -> str:\n \"\"\"Normalize public activation-precision names to internal modes.\"\"\"\n if os.environ.get(_FORCE_MOE_W4A16_ENV, \"0\") == \"1\":\n return \"bf16\"\n\n normalized = str(activation_precision).lower()\n aliases = {\n \"fp4\": \"fp4\",\n \"nvfp4\": \"fp4\",\n \"w4a4\": \"fp4\",\n \"bf16\": \"bf16\",\n \"w4a16\": \"bf16\",\n }\n try:\n return aliases[normalized]\n except KeyError as exc:\n raise ValueError(\n \"activation_precision must be 'fp4' or 'bf16' \"\n f\"(got {activation_precision!r}).\"\n ) from exc\n\n\ndef _normalize_quant_mode(\n quant_mode: str | None = None,\n activation_precision: str | None = None,\n) -> str:\n \"\"\"Normalize public quantization names to the dispatch mode.\"\"\"\n if os.environ.get(_FORCE_MOE_W4A16_ENV, \"0\") == \"1\":\n return \"w4a16\"\n if quant_mode is None:\n activation_precision = _normalize_activation_precision(\n activation_precision or \"fp4\"\n )\n return \"w4a16\" if activation_precision == \"bf16\" else \"nvfp4\"\n\n normalized = str(quant_mode).lower()\n aliases = {\n \"fp4\": \"nvfp4\",\n \"nvfp4\": \"nvfp4\",\n \"w4a4\": \"nvfp4\",\n \"bf16\": \"w4a16\",\n \"w4a16\": \"w4a16\",\n }\n try:\n return aliases[normalized]\n except KeyError as exc:\n raise ValueError(\n f\"quant_mode must be 'nvfp4'/'w4a4' or 'w4a16' (got {quant_mode!r}).\"\n ) from exc\n\n\ndef _activation_precision_from_quant_mode(quant_mode: str) -> str:\n return \"bf16\" if _normalize_quant_mode(quant_mode) == \"w4a16\" else \"fp4\"\n\n\ndef _normalize_source_format_for_quant_mode(source_format: str, quant_mode: str) -> str:\n normalized = _normalize_source_format(source_format)\n if quant_mode == \"nvfp4\" and normalized == \"compressed_tensors\":\n raise ValueError(\n \"source_format='compressed_tensors' requires quant_mode='w4a16'.\"\n )\n return normalized\n\n\ndef _is_w4a16(activation_precision: str) -> bool:\n return _normalize_activation_precision(activation_precision) == \"bf16\"\n\n\ndef _level_tile_n(activation_precision: str = \"fp4\") -> int:\n if _is_w4a16(activation_precision):\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 tile selector\"\n )\n return _LEVEL_TILE_N\n\n\ndef _select_dynamic_tile_m(\n routed_rows: int,\n num_experts: int,\n activation: str = \"silu\",\n) -> int:\n \"\"\"Pick the dynamic kernel's M-tile from routed rows per expert.\n\n Small tiles cut per-expert tail padding for sparse routing; 128 amortizes\n best for dense prefill (crossovers measured on gated NVFP4). Workspace\n sizing and the kernel build must both derive the tile from this function,\n or the scratch is mis-sized for what the kernel indexes.\n \"\"\"\n if not is_gated_activation(activation):\n return _LEVEL_TILE_M\n routed_rows = max(1, int(routed_rows))\n num_experts = max(1, int(num_experts))\n if routed_rows < 15 * num_experts:\n return 16\n if routed_rows < 48 * num_experts:\n return 32\n if routed_rows < 96 * num_experts:\n return 64\n return _LEVEL_TILE_M\n\n\ndef _get_static_compact_cutover_pairs(activation_precision: str = \"fp4\") -> int:\n activation_precision = _normalize_activation_precision(activation_precision)\n cached = _STATIC_COMPACT_CUTOVER_PAIRS_CACHE.get(activation_precision)\n if cached is not None:\n return cached\n\n cutover_names: tuple[str, ...] = (\n \"FLASHINFER_B12X_STATIC_COMPACT_CUTOVER_PAIRS\",\n \"B12X_STATIC_COMPACT_CUTOVER_PAIRS\",\n \"B12X_DYNAMIC_STATIC_CUTOVER_PAIRS\",\n \"B12X_LEVEL10_STATIC_CUTOVER_PAIRS\",\n )\n cutover = _first_env(*cutover_names)\n if cutover is None:\n cached = _STATIC_COMPACT_CUTOVER_PAIRS_DEFAULT\n else:\n cached = max(0, int(cutover))\n _STATIC_COMPACT_CUTOVER_PAIRS_CACHE[activation_precision] = cached\n return cached\n\n\ndef _select_moe_mma_tiler_mn(\n routed_rows: int,\n n: int,\n *,\n resident_clusters: int | None = None,\n) -> Tuple[int, int]:\n \"\"\"Select optimal MoE tile shape based on routed rows and N dimension.\n\n Uses narrower 64x128 tiles when routed_rows <= 128 and default 128x128\n would leave SMs idle.\n \"\"\"\n sm_count = get_num_sm(torch.device(\"cuda\"))\n coarse_tile = (128, 128)\n if routed_rows <= 32 and n <= 256:\n return (64, 128)\n if resident_clusters is not None and resident_clusters < sm_count:\n return coarse_tile\n coarse_tiles = ((routed_rows + coarse_tile[0] - 1) // coarse_tile[0]) * (\n (n + coarse_tile[1] - 1) // coarse_tile[1]\n )\n # Single-token decode often lands exactly on the \"half the machine\"\n # boundary. Keeping the coarse 128x128 tile there leaves the M dimension\n # badly underfilled, so take the narrow 64x128 tile inclusive of equality.\n if routed_rows <= 64 or (\n routed_rows <= 128 and coarse_tiles <= max(1, sm_count // 2)\n ):\n return (64, 128)\n return (128, 128)\n\n\ndef _as_grouped_scale_view(\n scale_storage: torch.Tensor,\n rows: int,\n cols: int,\n) -> torch.Tensor:\n \"\"\"Create 6D MMA-compatible scale factor view from swizzled storage.\"\"\"\n batch = scale_storage.shape[0]\n rows_padded = _align_up(rows, 128)\n cols_padded = _align_up(cols // SF_VEC_SIZE, 4)\n sf = scale_storage.view(torch.float8_e4m3fn)\n sf = sf.view(batch, rows_padded // 128, cols_padded // 4, 32, 4, 4)\n return sf.permute(3, 4, 1, 5, 2, 0)\n\n\n# ---------------------------------------------------------------------------\n# Workspace\n# ---------------------------------------------------------------------------\n@dataclass(kw_only=True)\nclass Sm120StaticMoEWorkspace:\n \"\"\"Scratch buffers for one SM120 static MoE launch.\"\"\"\n\n state_E: int\n weight_E: int\n max_rows: int\n k: int\n n: int\n num_topk: int\n device: torch.device\n activation_precision: str\n\n # Buffers\n row_counts: torch.Tensor # [state_E] int32\n token_map: torch.Tensor # [state_E, max_rows] int32\n token_weights: torch.Tensor # [state_E, max_rows] float32\n packed_input: torch.Tensor # [state_E, max_rows, k//2] uint8\n packed_input_scale: torch.Tensor # [state_E, rows_pad_k, cols_pad_k] uint8\n barrier_count: torch.Tensor # [1] int32\n barrier_epoch: torch.Tensor # [1] int32\n active_expert_count: torch.Tensor # [1] int32\n weight_expert_ids: torch.Tensor # [state_E] int32\n global_to_local_expert: torch.Tensor # [weight_E] int32\n compact_topk_ids: torch.Tensor # [state_E] int32, for micro kernel pre-pass\n\n # Views (set after allocation)\n packed_a_view: torch.Tensor | None = None\n sfa_ptr: object = None\n packed_a_flat: torch.Tensor | None = None\n scale_flat: torch.Tensor | None = None\n\n # Direct micro planes (allocated only when the shape can take that path).\n dm_barrier_count: torch.Tensor | None = None\n dm_barrier_epoch: torch.Tensor | None = None\n dm_intermediate: torch.Tensor | None = None\n dm_input_gs: torch.Tensor | None = None\n dm_down_input_scale: torch.Tensor | None = None\n\n\ndef _direct_micro_candidate(k: int, n: int, num_topk: int, weight_E: int) -> bool:\n \"\"\"Whether any m in the tiny-decode band can run the direct micro kernel.\"\"\"\n return any(\n MoEDirectMicroKernel.is_supported(m, k, n, num_topk, weight_E)\n for m in range(1, _MICRO_MAX_TOKENS + 1)\n )\n\n\ndef allocate_sm120_static_workspace(\n *,\n state_E: int,\n weight_E: int,\n max_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation_precision: str = \"fp4\",\n) -> Sm120StaticMoEWorkspace:\n \"\"\"Allocate workspace buffers for the SM120 static MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"allocate_sm120_static_workspace only supports quant_mode='nvfp4'; \"\n \"use allocate_sm120_moe_workspace(..., quant_mode='w4a16') for W4A16.\"\n )\n\n rows_pad_k = _align_up(max_rows, 128)\n cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n _check_memref_limit(\"static packed_input\", state_E * max_rows * (k // 2))\n _check_memref_limit(\"static packed_input_scale\", state_E * rows_pad_k * cols_pad_k)\n packed_input = torch.empty(\n state_E, max_rows, k // 2, dtype=torch.uint8, device=device\n )\n\n workspace = Sm120StaticMoEWorkspace(\n state_E=state_E,\n weight_E=weight_E,\n max_rows=max_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation_precision=activation_precision,\n row_counts=torch.zeros(state_E, dtype=torch.int32, device=device),\n token_map=torch.zeros(state_E, max_rows, dtype=torch.int32, device=device),\n token_weights=torch.zeros(\n state_E, max_rows, dtype=torch.float32, device=device\n ),\n packed_input=packed_input,\n packed_input_scale=torch.empty(\n state_E, rows_pad_k, cols_pad_k, dtype=torch.uint8, device=device\n ),\n barrier_count=torch.zeros(1, dtype=torch.int32, device=device),\n barrier_epoch=torch.zeros(1, dtype=torch.int32, device=device),\n active_expert_count=torch.zeros(1, dtype=torch.int32, device=device),\n weight_expert_ids=torch.arange(state_E, dtype=torch.int32, device=device),\n global_to_local_expert=torch.empty(weight_E, dtype=torch.int32, device=device),\n compact_topk_ids=torch.empty(\n max(state_E, max_rows), dtype=torch.int32, device=device\n ),\n )\n\n # Finalize views\n sf_dtype = cutlass.Float8E4M3FN\n workspace.packed_a_view = workspace.packed_input.permute(1, 2, 0).view(\n torch.float4_e2m1fn_x2\n )\n workspace.packed_a_flat = workspace.packed_input.view(-1)\n workspace.scale_flat = workspace.packed_input_scale.view(-1)\n workspace.sfa_ptr = make_ptr(\n sf_dtype,\n workspace.packed_input_scale.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n\n # Direct micro reads weights by global expert id, so its planes are only\n # useful without EP remapping.\n if state_E == weight_E and _direct_micro_candidate(k, n, num_topk, weight_E):\n dm_rows = min(max_rows, _MICRO_MAX_TOKENS * num_topk)\n # The epoch-based barriers restore their slots after each launch, so\n # the zeroed allocation is the only reset needed (graph-replay safe).\n dm_slots = dm_rows + _MICRO_MAX_TOKENS * 16\n fc2_n_chunks = (n // 2 + 127) // 128\n # The fused kernel binds the intermediate as m * num_topk *\n # fc2_n_chunks * 128 u32 words; size for the largest supported m.\n dm_inter = _MICRO_MAX_TOKENS * num_topk * fc2_n_chunks * 128\n workspace.dm_barrier_count = torch.zeros(\n dm_slots, dtype=torch.int32, device=device\n )\n workspace.dm_barrier_epoch = torch.zeros(\n dm_slots, dtype=torch.int32, device=device\n )\n workspace.dm_intermediate = torch.empty(\n dm_inter, dtype=torch.float32, device=device\n )\n workspace.dm_input_gs = torch.empty(\n weight_E, dtype=torch.float32, device=device\n )\n workspace.dm_down_input_scale = torch.empty(\n weight_E, dtype=torch.float32, device=device\n )\n return workspace\n\n\n# ---------------------------------------------------------------------------\n# Weight views\n# ---------------------------------------------------------------------------\n@dataclass\nclass _WeightViews:\n w13_fp4: object = None\n down_fp4: object = None\n sfb_w13_ptr: object = None\n sfb_down_ptr: object = None\n w1_alpha: torch.Tensor | None = None\n w2_alpha: torch.Tensor | None = None\n w1_storage: torch.Tensor | None = None\n w1_scale_storage: torch.Tensor | None = None\n w2_storage: torch.Tensor | None = None\n w2_scale_storage: torch.Tensor | None = None\n _w13_sf_storage: torch.Tensor | None = None\n _down_sf_storage: torch.Tensor | None = None\n\n\ndef _register_cache_eviction(cache: Dict, key: Tuple, *source_tensors) -> None:\n \"\"\"Evict ``key`` when a source weight tensor is collected, so the cache\n follows the weights' lifetime instead of growing for the whole process.\n \"\"\"\n for tensor in source_tensors:\n if tensor is not None:\n weakref.finalize(tensor, cache.pop, key, None)\n\n\n_WEIGHT_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_weight_views(\n w1_fp4: torch.Tensor,\n w1_blockscale: torch.Tensor,\n w2_fp4: torch.Tensor,\n w2_blockscale: torch.Tensor,\n w1_alphas: torch.Tensor,\n w2_alphas: torch.Tensor,\n n: int,\n k: int,\n activation_precision: str = \"fp4\",\n) -> _WeightViews:\n \"\"\"Create permuted weight views for the static kernel.\n\n The kernel expects concatenated w13 data with shape [2*n, k//2, E]\n via a single TMA descriptor.\n \"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n tile_n = _level_tile_n(activation_precision)\n # The kernel splits w13 into gate/up halves by tile index. This only works\n # when the boundary between halves lands on a tile-aligned column.\n if n % tile_n != 0:\n raise ValueError(\n f\"intermediate_size ({n}) must be a multiple of {tile_n} \"\n f\"for the SM120 MoE kernel's gate/up tile split.\"\n )\n\n key = (\n activation_precision,\n w1_fp4.data_ptr(),\n w1_blockscale.data_ptr(),\n w1_alphas.data_ptr(),\n w2_fp4.data_ptr(),\n w2_blockscale.data_ptr(),\n w2_alphas.data_ptr(),\n )\n cached = _WEIGHT_CACHE.get(key)\n if cached is None:\n # Cache the fresh buffers (scale factors + fp32 alphas).\n w1_rows = w1_fp4.shape[1] # 2*n for gated, n for non-gated\n cached = (\n convert_sf_from_mma_layout(\n w1_blockscale, m=w1_rows, k=k, num_groups=w1_fp4.shape[0]\n ).contiguous(),\n convert_sf_from_mma_layout(\n w2_blockscale, m=k, k=n, num_groups=w2_fp4.shape[0]\n ).contiguous(),\n w1_alphas.contiguous().to(torch.float32),\n w2_alphas.contiguous().to(torch.float32),\n )\n _WEIGHT_CACHE[key] = cached\n _register_cache_eviction(\n _WEIGHT_CACHE,\n key,\n w1_fp4,\n w1_blockscale,\n w1_alphas,\n w2_fp4,\n w2_blockscale,\n w2_alphas,\n )\n w13_sf_contiguous, down_sf_contiguous, w1_alpha, w2_alpha = cached\n\n # Permute [E, w1_rows, k//2] -> [w1_rows, k//2, E] (view, no copy).\n sf_dtype = cutlass.Float8E4M3FN\n w13 = w1_fp4.permute(1, 2, 0)\n down = w2_fp4.permute(1, 2, 0)\n return _WeightViews(\n w13_fp4=w13.view(torch.float4_e2m1fn_x2),\n down_fp4=down.view(torch.float4_e2m1fn_x2),\n sfb_w13_ptr=make_ptr(\n sf_dtype,\n w13_sf_contiguous.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n ),\n sfb_down_ptr=make_ptr(\n sf_dtype,\n down_sf_contiguous.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n ),\n w1_alpha=w1_alpha,\n w2_alpha=w2_alpha,\n w1_storage=w1_fp4,\n w1_scale_storage=w13_sf_contiguous,\n w2_storage=w2_fp4,\n w2_scale_storage=down_sf_contiguous,\n _w13_sf_storage=w13_sf_contiguous,\n _down_sf_storage=down_sf_contiguous,\n )\n\n\n# ---------------------------------------------------------------------------\n# Kernel compilation cache\n# ---------------------------------------------------------------------------\n_STATIC_KERNEL_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_static_kernel(\n state_E: int,\n weight_E: int,\n m: int,\n k: int,\n n: int,\n num_topk: int,\n max_rows: int,\n *,\n topk_ids_dtype: torch.dtype = torch.int32,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n mac_override: int | None = None,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n):\n \"\"\"Compile (or retrieve cached) the SM120 static MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 static compiler\"\n )\n sf_vec_size = 16\n sm_count = get_num_sm(torch.device(\"cuda\"))\n mac = (\n mac_override\n if mac_override is not None\n else min(get_max_active_clusters(1), sm_count)\n )\n\n # Select tile size based on actual routed rows\n routed_rows = m * num_topk\n mma_tiler_mn = (128, 128)\n if activation_precision == \"fp4\" and num_topk > 1:\n mma_tiler_mn = _select_moe_mma_tiler_mn(routed_rows, n, resident_clusters=mac)\n\n cache_key = (\n \"static\",\n activation_precision,\n state_E,\n weight_E,\n m,\n k,\n n,\n num_topk,\n max_rows,\n mac,\n mma_tiler_mn,\n topk_ids_dtype,\n input_scales_are_reciprocal,\n fast_math,\n activation,\n swiglu_alpha,\n swiglu_beta,\n swiglu_limit,\n )\n cached = _STATIC_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n return cached\n\n ab_dtype = cutlass.Float4E2M1FN\n weight_dtype = cutlass.Float4E2M1FN\n sf_dtype = cutlass.Float8E4M3FN\n a_dtype = cutlass.BFloat16\n alpha_dtype = cutlass.Float32\n\n output_tile_count_n = max(1, (n + mma_tiler_mn[1] - 1) // mma_tiler_mn[1])\n kernel: Any = MoEStaticKernel(\n sf_vec_size=sf_vec_size,\n mma_tiler_mn=mma_tiler_mn,\n output_tile_count_n=output_tile_count_n,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n )\n\n is_gated = is_gated_activation(activation)\n w1_rows = (2 if is_gated else 1) * n # 2*n for gated, n for non-gated\n\n rows_pad_k = _align_up(max_rows, 128)\n cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n\n # Build fake tensors for compilation\n a_input_fake = cute.runtime.make_fake_compact_tensor(\n a_dtype,\n (m, k),\n stride_order=(1, 0),\n assumed_align=16,\n )\n topk_ids_cutlass_dtype = (\n cutlass.Int32 if topk_ids_dtype == torch.int32 else cutlass.Int64\n )\n topk_ids_align = 4 if topk_ids_dtype == torch.int32 else 8\n topk_ids_fake = cute.runtime.make_fake_compact_tensor(\n topk_ids_cutlass_dtype,\n (m * num_topk,),\n assumed_align=topk_ids_align,\n )\n topk_weights_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32,\n (m * num_topk,),\n assumed_align=4,\n )\n packed_a_fake = cute.runtime.make_fake_compact_tensor(\n ab_dtype,\n (max_rows, k, state_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfa_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n packed_a_storage_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (state_E * max_rows * (k // 2),),\n assumed_align=16,\n )\n scale_storage_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (state_E * rows_pad_k * cols_pad_k,),\n assumed_align=16,\n )\n barrier_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n barrier_epoch_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n b_w13_fake = cute.runtime.make_fake_compact_tensor(\n weight_dtype,\n (w1_rows, k, weight_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_w13_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n b_down_fake = cute.runtime.make_fake_compact_tensor(\n weight_dtype,\n (k, n, weight_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_down_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n row_counts_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E,),\n assumed_align=4,\n )\n active_expert_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n weight_expert_ids_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E,),\n assumed_align=4,\n )\n global_to_local_expert_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (weight_E,),\n assumed_align=4,\n )\n input_gs_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n down_alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n global_scale_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n scatter_fake = cute.runtime.make_fake_compact_tensor(\n a_dtype,\n (m, k),\n stride_order=(1, 0),\n assumed_align=16,\n )\n token_map_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E, max_rows),\n stride_order=(1, 0),\n assumed_align=4,\n )\n token_weights_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (state_E, max_rows),\n stride_order=(1, 0),\n assumed_align=16,\n )\n compiled = cute.compile(\n kernel,\n a_input_fake,\n topk_ids_fake,\n topk_weights_fake,\n packed_a_fake,\n sfa_fake,\n packed_a_storage_fake,\n scale_storage_fake,\n barrier_count_fake,\n barrier_epoch_fake,\n b_w13_fake,\n sfb_w13_fake,\n b_down_fake,\n sfb_down_fake,\n row_counts_fake,\n active_expert_count_fake,\n weight_expert_ids_fake,\n global_to_local_expert_fake,\n input_gs_fake,\n alpha_fake,\n down_alpha_fake,\n global_scale_fake,\n scatter_fake,\n token_map_fake,\n token_weights_fake,\n mac,\n current_cuda_stream(),\n options=\"--opt-level 2 --enable-tvm-ffi\",\n )\n\n result = (compiled, mac)\n _STATIC_KERNEL_CACHE[cache_key] = result\n return result\n\n\n_MICRO_KERNEL_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_micro_kernel(\n state_E: int,\n weight_E: int,\n m: int,\n k: int,\n n: int,\n num_topk: int,\n max_rows: int,\n *,\n topk_ids_dtype: torch.dtype = torch.int32,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n share_input_across_experts: bool = False,\n share_expert_scales: bool = False,\n single_token: bool = False,\n mac_override: int | None = None,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n):\n \"\"\"Compile (or retrieve cached) the SM120 micro MoE kernel.\"\"\"\n sf_vec_size = 16\n sm_count = get_num_sm(torch.device(\"cuda\"))\n mac = (\n mac_override\n if mac_override is not None\n else min(get_max_active_clusters(1), sm_count)\n )\n\n # Micro always selects tile from routed rows (not just for multi-topk)\n routed_rows = m * num_topk\n mma_tiler_mn = _select_moe_mma_tiler_mn(routed_rows, n)\n\n cache_key = (\n \"micro\",\n state_E,\n weight_E,\n m,\n k,\n n,\n num_topk,\n max_rows,\n mac,\n mma_tiler_mn,\n topk_ids_dtype,\n input_scales_are_reciprocal,\n fast_math,\n share_input_across_experts,\n share_expert_scales,\n single_token,\n activation,\n swiglu_alpha,\n swiglu_beta,\n swiglu_limit,\n )\n cached = _MICRO_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n return cached\n\n ab_dtype = cutlass.Float4E2M1FN\n sf_dtype = cutlass.Float8E4M3FN\n a_dtype = cutlass.BFloat16\n alpha_dtype = cutlass.Float32\n\n kernel = MoEMicroKernel(\n sf_vec_size=sf_vec_size,\n mma_tiler_mn=mma_tiler_mn,\n output_tile_count_n=max(1, (n + mma_tiler_mn[1] - 1) // mma_tiler_mn[1]),\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n share_input_across_experts=share_input_across_experts,\n share_expert_scales=share_expert_scales,\n single_token=single_token,\n )\n\n is_gated = is_gated_activation(activation)\n w1_rows = (2 if is_gated else 1) * n\n\n rows_pad_k = _align_up(max_rows, 128)\n cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n\n # Build fake tensors for compilation (identical to static kernel)\n a_input_fake = cute.runtime.make_fake_compact_tensor(\n a_dtype,\n (m, k),\n stride_order=(1, 0),\n assumed_align=16,\n )\n topk_ids_cutlass_dtype = (\n cutlass.Int32 if topk_ids_dtype == torch.int32 else cutlass.Int64\n )\n topk_ids_align = 4 if topk_ids_dtype == torch.int32 else 8\n topk_ids_fake = cute.runtime.make_fake_compact_tensor(\n topk_ids_cutlass_dtype,\n (m * num_topk,),\n assumed_align=topk_ids_align,\n )\n topk_weights_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32,\n (m * num_topk,),\n assumed_align=4,\n )\n packed_a_fake = cute.runtime.make_fake_compact_tensor(\n ab_dtype,\n (max_rows, k, state_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfa_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n packed_a_storage_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (state_E * max_rows * (k // 2),),\n assumed_align=16,\n )\n scale_storage_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (state_E * rows_pad_k * cols_pad_k,),\n assumed_align=16,\n )\n barrier_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n barrier_epoch_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n b_w13_fake = cute.runtime.make_fake_compact_tensor(\n ab_dtype,\n (w1_rows, k, weight_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_w13_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n b_down_fake = cute.runtime.make_fake_compact_tensor(\n ab_dtype,\n (k, n, weight_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_down_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n row_counts_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E,),\n assumed_align=4,\n )\n active_expert_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n weight_expert_ids_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E,),\n assumed_align=4,\n )\n global_to_local_expert_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (weight_E,),\n assumed_align=4,\n )\n input_gs_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n down_alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n global_scale_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n scatter_fake = cute.runtime.make_fake_compact_tensor(\n a_dtype,\n (m, k),\n stride_order=(1, 0),\n assumed_align=16,\n )\n token_map_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E, max_rows),\n stride_order=(1, 0),\n assumed_align=4,\n )\n token_weights_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (state_E, max_rows),\n stride_order=(1, 0),\n assumed_align=16,\n )\n compiled = cute.compile(\n kernel,\n a_input_fake,\n topk_ids_fake,\n topk_weights_fake,\n packed_a_fake,\n sfa_fake,\n packed_a_storage_fake,\n scale_storage_fake,\n barrier_count_fake,\n barrier_epoch_fake,\n b_w13_fake,\n sfb_w13_fake,\n b_down_fake,\n sfb_down_fake,\n row_counts_fake,\n active_expert_count_fake,\n weight_expert_ids_fake,\n global_to_local_expert_fake,\n input_gs_fake,\n alpha_fake,\n down_alpha_fake,\n global_scale_fake,\n scatter_fake,\n token_map_fake,\n token_weights_fake,\n mac,\n current_cuda_stream(),\n options=\"--opt-level 2 --enable-tvm-ffi\",\n )\n\n result = (compiled, mac)\n _MICRO_KERNEL_CACHE[cache_key] = result\n return result\n\n\n# The launch cache skips the per-launch build/configure; the kernel cache\n# dedupes compiles across keys that configure to the same artifact\n# (m=2..8 differ only in grid_x).\n_DIRECT_MICRO_LAUNCH_CACHE: Dict[Tuple, Tuple] = {}\n_DIRECT_MICRO_KERNEL_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_direct_micro_kernel(\n weight_E: int,\n m: int,\n k: int,\n n: int,\n num_topk: int,\n *,\n topk_ids_dtype: torch.dtype = torch.int32,\n fast_math: bool = True,\n share_input_across_experts: bool = False,\n share_expert_scales: bool = False,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n device: torch.device | None = None,\n):\n \"\"\"Compile (or retrieve cached) the SM120 direct micro MoE kernel.\n\n Returns (compiled, grid_x, accepts_block_dim).\n \"\"\"\n if activation != SWIGLUOAI_UNINTERLEAVE:\n # The kernel constructor only accepts configurable swiglu parameters\n # for swigluoai; other activations use its normalized defaults\n # (accept-and-ignore, matching the MMA kernels).\n swiglu_alpha = None\n swiglu_beta = None\n swiglu_limit = None\n launch_key = (\n weight_E,\n m,\n k,\n n,\n num_topk,\n topk_ids_dtype,\n fast_math,\n share_input_across_experts,\n share_expert_scales,\n activation,\n swiglu_alpha,\n swiglu_beta,\n swiglu_limit,\n str(_canonical_cuda_device(device)) if device is not None else None,\n )\n cached = _DIRECT_MICRO_LAUNCH_CACHE.get(launch_key)\n if cached is not None:\n return cached\n kernel = build_direct_micro_kernel(\n weight_E,\n m,\n k,\n n,\n num_topk,\n activation=activation,\n fast_math=fast_math,\n share_input_across_experts=share_input_across_experts,\n share_expert_scales=share_expert_scales,\n single_token=m == 1,\n swiglu_limit=swiglu_limit,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n device=device,\n )\n compile_key = (\"direct_micro\", kernel.__cache_key__, topk_ids_dtype)\n entry = _DIRECT_MICRO_KERNEL_CACHE.get(compile_key)\n if entry is None:\n compiled = compile_direct_micro_kernel(kernel, topk_ids_dtype=topk_ids_dtype)\n # Register pressure can cap the launchable CTA below the fused body's\n # 512 threads; probe once per compiled kernel.\n accepts = compiled_direct_micro_accepts_block_dim(\n compiled, kernel.launch_block_dim\n )\n entry = (compiled, accepts)\n _DIRECT_MICRO_KERNEL_CACHE[compile_key] = entry\n compiled, accepts = entry\n cached = (compiled, kernel.grid_x, accepts)\n _DIRECT_MICRO_LAUNCH_CACHE[launch_key] = cached\n return cached\n\n\n# ---------------------------------------------------------------------------\n# Launch\n# ---------------------------------------------------------------------------\ndef _expand_to_experts(t: torch.Tensor, num_experts: int) -> torch.Tensor:\n \"\"\"Broadcast a scalar or [1] tensor to [num_experts], always fp32.\n\n Both branches must cast: the kernels are compiled against fp32 fake\n tensors for every per-expert scale.\n \"\"\"\n if t.numel() == 1:\n return t.to(torch.float32).expand(num_experts).contiguous()\n return t.contiguous().to(torch.float32)\n\n\ndef launch_sm120_static_moe(\n *,\n workspace: Sm120StaticMoEWorkspace,\n weights: _WeightViews,\n a: torch.Tensor,\n topk_ids: torch.Tensor,\n topk_weights: torch.Tensor,\n input_gs: torch.Tensor,\n down_input_scale: torch.Tensor,\n scatter_output: torch.Tensor,\n num_experts: int,\n num_tokens: int,\n k: int,\n n: int,\n top_k: int,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n) -> torch.Tensor:\n \"\"\"Launch the SM120 static, micro, or direct micro MoE kernel.\n\n The direct micro kernel takes tiny decode batches (m <= 8, routed_rows\n < 64) when it supports the shape, the MMA micro kernel takes the rest of\n its band (routed_rows <= 20-40), and the static kernel takes the rest.\n The MMA micro path runs a Triton pre-pass to compact routing IDs before\n launching; direct micro routes on global expert ids directly.\n \"\"\"\n _check_memref_limit(\"scatter_output\", scatter_output.numel())\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 static launcher\"\n )\n\n # Flatten routing tensors\n flat_ids = topk_ids.view(-1).to(torch.int32)\n flat_weights = topk_weights.view(-1).to(torch.float32)\n routed_rows = num_tokens * top_k\n\n # Capture whether input_gs was a single shared scalar BEFORE expansion:\n # the m=1 relu2 shared-input micro optimization only applies when every\n # expert sees the same FC1-input global scale.\n input_gs_is_shared = input_gs.numel() == 1\n down_input_scale_is_shared = down_input_scale.numel() == 1\n\n # Broadcast scalar scales to per-expert [E] tensors\n input_gs = _expand_to_experts(input_gs, num_experts)\n down_input_scale = _expand_to_experts(down_input_scale, num_experts)\n\n # Shared-scale flags let compact W4A4 micro match the ReLU2 single-token\n # specialization.\n share_input_across_experts = (\n activation == \"relu2\"\n and num_tokens == 1\n and input_gs_is_shared\n and _MICRO_SHARE_INPUT_ACROSS_EXPERTS\n )\n share_expert_scales = (\n activation == \"relu2\" and input_gs_is_shared and down_input_scale_is_shared\n )\n\n # Direct micro takes its band before the MMA micro decision. It reads\n # weights by global expert id, so EP shapes keep the compact path.\n use_direct_micro = (\n activation_precision == \"fp4\"\n and workspace.state_E == num_experts\n and workspace.dm_barrier_count is not None\n and workspace.dm_barrier_count.numel() >= routed_rows + num_tokens * 16\n and num_tokens <= _MICRO_MAX_TOKENS\n and routed_rows < _DIRECT_MICRO_CUTOVER_PAIRS\n and n <= _DIRECT_MICRO_MAX_N\n and MoEDirectMicroKernel.is_supported(num_tokens, k, n, top_k, num_experts)\n )\n if _FORCED_BACKEND is not None:\n if _FORCED_BACKEND == \"direct_micro\":\n if workspace.dm_barrier_count is None or not (\n MoEDirectMicroKernel.is_supported(num_tokens, k, n, top_k, num_experts)\n ):\n raise ValueError(\n \"forced direct_micro backend cannot run this shape \"\n f\"(m={num_tokens}, k={k}, n={n}, top_k={top_k})\"\n )\n if workspace.dm_barrier_count.numel() < routed_rows + num_tokens * 16:\n raise ValueError(\n \"forced direct_micro backend exceeds the workspace barrier \"\n f\"capacity ({workspace.dm_barrier_count.numel()} slots < \"\n f\"{routed_rows} routed rows + {num_tokens * 16})\"\n )\n use_direct_micro = True\n else:\n use_direct_micro = False\n if use_direct_micro:\n compiled, grid_x, block_ok = _get_direct_micro_kernel(\n num_experts,\n num_tokens,\n k,\n n,\n top_k,\n topk_ids_dtype=flat_ids.dtype,\n fast_math=fast_math,\n share_input_across_experts=share_input_across_experts,\n share_expert_scales=share_expert_scales,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n device=a.device,\n )\n if not block_ok:\n if _FORCED_BACKEND == \"direct_micro\":\n raise RuntimeError(\"compiled direct micro MoE kernel cannot launch\")\n use_direct_micro = False\n if use_direct_micro:\n # The kernel takes multiplier-form scales only; invert reciprocal\n # inputs into the persistent workspace planes (zeros stay zero,\n # matching the MMA kernels).\n if input_scales_are_reciprocal:\n workspace.dm_input_gs.copy_(\n torch.where(input_gs != 0, 1.0 / input_gs, input_gs)\n )\n workspace.dm_down_input_scale.copy_(\n torch.where(\n down_input_scale != 0, 1.0 / down_input_scale, down_input_scale\n )\n )\n launch_gs = workspace.dm_input_gs\n launch_down = workspace.dm_down_input_scale\n else:\n launch_gs = input_gs\n launch_down = down_input_scale\n MoEDirectMicroKernel.launch(\n compiled,\n x=a,\n w1_fp4=weights.w1_storage,\n w1_blockscale=weights.w1_scale_storage,\n w1_alphas=weights.w1_alpha,\n a1_gscale=launch_gs,\n a2_gscale=launch_down,\n inter_fp32=workspace.dm_intermediate,\n w2_fp4=weights.w2_storage,\n w2_blockscale=weights.w2_scale_storage,\n w2_alphas=weights.w2_alpha,\n topk_ids=flat_ids,\n topk_weights=flat_weights,\n out=scatter_output,\n barrier_count=workspace.dm_barrier_count,\n barrier_epoch=workspace.dm_barrier_epoch,\n m=num_tokens,\n grid_x=grid_x,\n )\n return scatter_output\n\n # Decide micro vs static\n micro_cutover = _MICRO_COMPACT_CUTOVER_PAIRS\n if top_k > 1:\n micro_cutover = _MICRO_COMPACT_CUTOVER_PAIRS_MULTI_TOPK\n use_micro = (\n activation_precision == \"fp4\"\n and num_tokens <= _MICRO_MAX_TOKENS\n and routed_rows <= micro_cutover\n )\n if _FORCED_BACKEND is not None:\n if _FORCED_BACKEND == \"micro\":\n # Forced mode raises on correctness violations, never falls back.\n if num_tokens > _MICRO_MAX_TOKENS:\n raise ValueError(\n f\"forced micro backend supports at most {_MICRO_MAX_TOKENS} \"\n f\"tokens (got {num_tokens})\"\n )\n if flat_ids.numel() > workspace.compact_topk_ids.numel():\n raise ValueError(\n \"forced micro backend exceeds the workspace compact-id \"\n f\"capacity ({workspace.compact_topk_ids.numel()} < \"\n f\"{flat_ids.numel()})\"\n )\n use_micro = True\n else:\n use_micro = False\n\n sm_count = get_num_sm(torch.device(\"cuda\"))\n base_mac = min(get_max_active_clusters(1), sm_count)\n tuned_static_mac = _lookup_mac_ladder(_STATIC_MAC_LADDER, routed_rows)\n static_mac = min(tuned_static_mac or base_mac, base_mac)\n if activation_precision == \"fp4\" and not use_micro and routed_rows < 40:\n static_mac = min(static_mac, 64)\n\n if use_micro:\n assert flat_ids.numel() <= workspace.compact_topk_ids.numel(), (\n f\"compact_topk_ids buffer too small: \"\n f\"{workspace.compact_topk_ids.numel()} < {flat_ids.numel()}\"\n )\n # Single-token ReLU2 is non-gated, so the micro kernel can launch on\n # the routed expert ids directly. Gated SiLU still goes through the\n # compact id buffer so the kernel can map compact launch ids back to\n # the physical gate/up weight experts.\n if num_tokens == 1 and activation == \"relu2\":\n launch_ids = flat_ids\n elif num_tokens == 1:\n compact_ids = workspace.compact_topk_ids[: flat_ids.numel()]\n compact_ids.copy_(\n torch.arange(\n flat_ids.numel(),\n device=flat_ids.device,\n dtype=torch.int32,\n )\n )\n workspace.weight_expert_ids[: flat_ids.numel()].copy_(\n flat_ids.to(torch.int32)\n )\n workspace.active_expert_count.fill_(flat_ids.numel())\n launch_ids = compact_ids\n else:\n compact_ids = workspace.compact_topk_ids[: flat_ids.numel()]\n from .triton_compact import compact_topk_ids as _triton_compact_topk_ids\n\n _triton_compact_topk_ids(\n flat_ids,\n compact_ids,\n workspace.weight_expert_ids,\n workspace.active_expert_count,\n )\n launch_ids = compact_ids\n # Select micro MAC: min of tuned ladder, work tiles, and hardware limit.\n micro_work_tiles = max(1, routed_rows * max(1, (n + 128 - 1) // 128))\n tuned_mac = _lookup_mac_ladder(_MICRO_MAC_LADDER, routed_rows)\n micro_mac = min(tuned_mac or base_mac, micro_work_tiles, base_mac)\n compiled, mac = _get_micro_kernel(\n workspace.state_E,\n num_experts,\n num_tokens,\n k,\n n,\n top_k,\n workspace.max_rows,\n topk_ids_dtype=launch_ids.dtype,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n share_input_across_experts=share_input_across_experts,\n share_expert_scales=share_expert_scales,\n single_token=num_tokens == 1,\n mac_override=micro_mac,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n )\n else:\n compiled, mac = _get_static_kernel(\n workspace.state_E,\n num_experts,\n num_tokens,\n k,\n n,\n top_k,\n workspace.max_rows,\n topk_ids_dtype=torch.int32,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n mac_override=static_mac,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n activation_precision=activation_precision,\n )\n launch_ids = flat_ids\n\n # Pointer arguments must be passed as raw ints (data_ptr()) at runtime.\n runtime_args: Tuple[Any, ...] = (\n a,\n launch_ids,\n flat_weights,\n workspace.packed_a_view,\n workspace.packed_input_scale.data_ptr(),\n workspace.packed_a_flat,\n workspace.scale_flat,\n workspace.barrier_count,\n workspace.barrier_epoch,\n weights.w13_fp4,\n weights._w13_sf_storage.data_ptr(),\n weights.down_fp4,\n weights._down_sf_storage.data_ptr(),\n workspace.row_counts,\n workspace.active_expert_count,\n workspace.weight_expert_ids,\n workspace.global_to_local_expert,\n input_gs,\n weights.w1_alpha,\n weights.w2_alpha,\n down_input_scale,\n scatter_output,\n workspace.token_map,\n workspace.token_weights,\n )\n compiled(*runtime_args, current_cuda_stream())\n\n return scatter_output\n\n\n# ==========================================================================\n# Dynamic backend\n# ==========================================================================\n\n\ndef select_sm120_moe_backend(\n *,\n num_tokens: int,\n num_topk: int,\n activation_precision: str = \"fp4\",\n quant_mode: str | None = None,\n) -> str:\n \"\"\"Pick static or dynamic backend based on routed-pair count.\"\"\"\n mode = _normalize_quant_mode(quant_mode, activation_precision)\n if mode == \"w4a16\":\n return \"w4a16\"\n if _FORCED_BACKEND == \"dynamic\":\n return \"dynamic\"\n if _FORCED_BACKEND in (\"static\", \"micro\", \"direct_micro\"):\n # Both micro variants launch through the static workspace path.\n return \"static\"\n routed_rows = num_tokens * num_topk\n if routed_rows <= _get_static_compact_cutover_pairs(\"fp4\"):\n return \"static\"\n return \"dynamic\"\n\n\n# ---------------------------------------------------------------------------\n# Dynamic workspace\n# ---------------------------------------------------------------------------\n@dataclass(kw_only=True)\nclass Sm120DynamicMoEWorkspace:\n \"\"\"Scratch buffers for one SM120 dynamic MoE launch.\"\"\"\n\n state_E: int\n weight_E: int\n max_rows: int\n k: int\n n: int\n num_topk: int\n device: torch.device\n activation_precision: str\n\n # Core buffers\n row_counts: torch.Tensor\n token_map: torch.Tensor\n token_weights: torch.Tensor\n packed_input: torch.Tensor\n packed_input_scale: torch.Tensor\n barrier_count: torch.Tensor\n barrier_epoch: torch.Tensor\n\n # Dynamic-specific\n routed_rows_capacity: int\n physical_tiles_capacity: int\n task_capacity: int\n # The M-tile the geometry above was sized for; launches must build the\n # kernel with the same tile.\n tile_m: int = _LEVEL_TILE_M\n expert_write_rows: torch.Tensor\n expert_tile_base: torch.Tensor\n pair_head: torch.Tensor\n task_head: torch.Tensor\n task_tail: torch.Tensor\n task_expert: torch.Tensor\n task_valid_rows: torch.Tensor\n\n # Views\n packed_a_view: torch.Tensor | None = None\n sfa_ptr: object = None\n packed_a_flat: torch.Tensor | None = None\n scale_flat: torch.Tensor | None = None\n\n\ndef _dynamic_task_geometry(\n state_E: int,\n n: int,\n routed_rows: int,\n *,\n tile_m: int = _LEVEL_TILE_M,\n tile_n: int = _LEVEL_TILE_N,\n):\n \"\"\"Compute task queue dimensions from problem geometry.\n\n Each active expert can introduce at most one additional physical tile\n beyond the base count (due to per-expert tail padding). The task queue\n holds one entry per (m_tile, slice_group) pair — NOT multiplied by E.\n \"\"\"\n routed_rows = max(1, routed_rows)\n base_m_tiles = _align_up(routed_rows, tile_m) // tile_m\n active_expert_upper_bound = min(state_E, routed_rows)\n max_m_tiles = max(1, base_m_tiles + active_expert_upper_bound - 1)\n gate_tile_cnt = max(1, (n + tile_n - 1) // tile_n)\n slice_groups = max(\n 1, (gate_tile_cnt + _DYNAMIC_SLICE_CHUNK - 1) // _DYNAMIC_SLICE_CHUNK\n )\n max_tasks = max_m_tiles * slice_groups\n return max_m_tiles, gate_tile_cnt, max_tasks\n\n\ndef allocate_sm120_dynamic_workspace(\n *,\n state_E: int,\n weight_E: int,\n routed_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation_precision: str = \"fp4\",\n activation: str = \"silu\",\n) -> Sm120DynamicMoEWorkspace:\n \"\"\"Allocate workspace buffers for the SM120 dynamic MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"allocate_sm120_dynamic_workspace only supports quant_mode='nvfp4'; \"\n \"use allocate_sm120_moe_workspace(..., quant_mode='w4a16') for W4A16.\"\n )\n tile_m = _select_dynamic_tile_m(routed_rows, state_E, activation)\n physical_tiles, _, max_tasks = _dynamic_task_geometry(\n state_E,\n n,\n routed_rows,\n tile_m=tile_m,\n tile_n=_level_tile_n(activation_precision),\n )\n rows_padded = physical_tiles * tile_m\n # The kernel addresses activation scales in 128-row SF atoms regardless of\n # tile_m, so the scale plane must cover the last partial atom.\n scale_rows = _align_up(rows_padded, 128)\n cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n _check_memref_limit(\"dynamic packed_input\", rows_padded * (k // 2))\n _check_memref_limit(\"dynamic packed_input_scale\", scale_rows * cols_pad_k)\n packed_input = torch.empty(1, rows_padded, k // 2, dtype=torch.uint8, device=device)\n\n workspace = Sm120DynamicMoEWorkspace(\n state_E=state_E,\n weight_E=weight_E,\n max_rows=rows_padded,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation_precision=activation_precision,\n routed_rows_capacity=routed_rows,\n physical_tiles_capacity=physical_tiles,\n task_capacity=max_tasks,\n tile_m=tile_m,\n row_counts=torch.zeros(state_E, dtype=torch.int32, device=device),\n token_map=torch.zeros(rows_padded, dtype=torch.int32, device=device),\n token_weights=torch.zeros(rows_padded, dtype=torch.float32, device=device),\n packed_input=packed_input,\n packed_input_scale=torch.empty(\n scale_rows, cols_pad_k, dtype=torch.uint8, device=device\n ),\n barrier_count=torch.zeros(1, dtype=torch.int32, device=device),\n barrier_epoch=torch.zeros(1, dtype=torch.int32, device=device),\n expert_write_rows=torch.zeros(state_E, dtype=torch.int32, device=device),\n expert_tile_base=torch.zeros(state_E + 1, dtype=torch.int32, device=device),\n pair_head=torch.zeros(1, dtype=torch.int32, device=device),\n task_head=torch.zeros(1, dtype=torch.int32, device=device),\n task_tail=torch.zeros(1, dtype=torch.int32, device=device),\n task_expert=torch.zeros(max_tasks, dtype=torch.int32, device=device),\n task_valid_rows=torch.zeros(max_tasks, dtype=torch.int32, device=device),\n )\n\n # Finalize views\n sf_dtype = cutlass.Float8E4M3FN\n workspace.packed_a_view = workspace.packed_input.permute(1, 2, 0).view(\n torch.float4_e2m1fn_x2\n )\n workspace.packed_a_flat = workspace.packed_input.view(-1)\n workspace.scale_flat = workspace.packed_input_scale.view(-1)\n workspace.sfa_ptr = make_ptr(\n sf_dtype,\n workspace.packed_input_scale.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n return workspace\n\n\n# ---------------------------------------------------------------------------\n# Dynamic kernel compilation\n# ---------------------------------------------------------------------------\n\n\nclass _DynamicMoELaunch:\n \"\"\"Thin JIT wrapper that makes num_tokens and max_rows runtime Int32.\"\"\"\n\n def __init__(self, kernel, k, num_topk, activation_precision: str = \"fp4\"):\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 dynamic launcher wrapper\"\n )\n self._kernel = kernel\n self._k = k\n self._packed_storage_cols = k // 2\n self._num_topk = num_topk\n self._cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n\n @cute.jit\n def __call__(\n self,\n a_ptr: cute.Pointer,\n topk_ids_ptr: cute.Pointer,\n topk_weights_ptr: cute.Pointer,\n packed_a_ptr: cute.Pointer,\n sfa_ptr: cute.Pointer,\n packed_a_storage_ptr: cute.Pointer,\n scale_storage_ptr: cute.Pointer,\n barrier_count: cute.Tensor,\n barrier_epoch: cute.Tensor,\n pair_head: cute.Tensor,\n task_head: cute.Tensor,\n task_tail: cute.Tensor,\n task_expert_ptr: cute.Pointer,\n task_valid_rows_ptr: cute.Pointer,\n b_w13: cute.Tensor,\n sfb_w13_ptr: cute.Pointer,\n b_down: cute.Tensor,\n sfb_down_ptr: cute.Pointer,\n row_counts: cute.Tensor,\n expert_write_rows: cute.Tensor,\n expert_tile_base: cute.Tensor,\n input_global_scale: cute.Tensor,\n alpha: cute.Tensor,\n down_alpha: cute.Tensor,\n global_scale: cute.Tensor,\n scatter_ptr: cute.Pointer,\n token_map_ptr: cute.Pointer,\n token_weights_ptr: cute.Pointer,\n num_tokens: cutlass.Int32,\n max_rows: cutlass.Int32,\n rows_padded: cutlass.Int32,\n max_tasks: cutlass.Int32,\n max_active_clusters: cutlass.Constexpr,\n stream,\n ):\n a_input = cute.make_tensor(\n a_ptr, layout=cute.make_layout((num_tokens, self._k), stride=(self._k, 1))\n )\n topk_ids = cute.make_tensor(\n topk_ids_ptr,\n layout=cute.make_layout((num_tokens * self._num_topk,), stride=(1,)),\n )\n topk_weights_t = cute.make_tensor(\n topk_weights_ptr,\n layout=cute.make_layout((num_tokens * self._num_topk,), stride=(1,)),\n )\n scatter_output = cute.make_tensor(\n scatter_ptr,\n layout=cute.make_layout((num_tokens, self._k), stride=(self._k, 1)),\n )\n packed_a = cute.make_tensor(\n packed_a_ptr,\n layout=cute.make_layout(\n (rows_padded, self._k, 1), stride=(self._k, 1, rows_padded * self._k)\n ),\n )\n packed_a_storage = cute.make_tensor(\n packed_a_storage_ptr,\n layout=cute.make_layout(\n (rows_padded * self._packed_storage_cols,), stride=(1,)\n ),\n )\n # Activation scales live in 128-row SF atoms; the plane is allocated\n # through the last partial atom even when rows_padded is not aligned.\n scale_rows = ((rows_padded + 127) // 128) * 128\n scale_storage = cute.make_tensor(\n scale_storage_ptr,\n layout=cute.make_layout((scale_rows * self._cols_pad_k,), stride=(1,)),\n )\n token_map = cute.make_tensor(\n token_map_ptr, layout=cute.make_layout((rows_padded,), stride=(1,))\n )\n token_weights_t = cute.make_tensor(\n token_weights_ptr, layout=cute.make_layout((rows_padded,), stride=(1,))\n )\n task_expert = cute.make_tensor(\n task_expert_ptr, layout=cute.make_layout((max_tasks,), stride=(1,))\n )\n task_valid_rows = cute.make_tensor(\n task_valid_rows_ptr, layout=cute.make_layout((max_tasks,), stride=(1,))\n )\n self._kernel(\n a_input,\n topk_ids,\n topk_weights_t,\n packed_a,\n sfa_ptr,\n packed_a_storage,\n scale_storage,\n barrier_count,\n barrier_epoch,\n pair_head,\n task_head,\n task_tail,\n task_expert,\n task_valid_rows,\n b_w13,\n sfb_w13_ptr,\n b_down,\n sfb_down_ptr,\n row_counts,\n expert_write_rows,\n expert_tile_base,\n input_global_scale,\n alpha,\n down_alpha,\n global_scale,\n scatter_output,\n token_map,\n token_weights_t,\n max_active_clusters=max_active_clusters,\n stream=stream,\n )\n\n\n_DYNAMIC_KERNEL_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_dynamic_kernel(\n E: int,\n m: int,\n k: int,\n n: int,\n num_topk: int,\n max_rows: int,\n *,\n topk_ids_dtype: torch.dtype = torch.int32,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n share_input_across_experts: bool = False,\n tile_m: int = _LEVEL_TILE_M,\n):\n \"\"\"Compile (or retrieve cached) the SM120 dynamic MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 dynamic compiler\"\n )\n share_input_across_experts = bool(\n share_input_across_experts and activation_precision == \"fp4\"\n )\n sf_vec_size = 16\n sm_count = get_num_sm(torch.device(\"cuda\"))\n base_mac = min(get_max_active_clusters(1), sm_count)\n tuned_mac = _lookup_mac_ladder(_DYNAMIC_MAC_LADDER, m * num_topk)\n mac = min(tuned_mac or base_mac, base_mac)\n # tile_m comes from the workspace's shared selection so the kernel's task\n # and scale indexing matches the allocated scratch geometry.\n mma_tiler_mn = (tile_m, _level_tile_n(activation_precision))\n\n cache_key = (\n \"dynamic\",\n activation_precision,\n E,\n k,\n n,\n num_topk,\n mac,\n mma_tiler_mn,\n topk_ids_dtype,\n input_scales_are_reciprocal,\n fast_math,\n activation,\n swiglu_alpha,\n swiglu_beta,\n swiglu_limit,\n share_input_across_experts,\n )\n cached = _DYNAMIC_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n return cached\n\n is_gated = is_gated_activation(activation)\n w1_rows = (2 if is_gated else 1) * n\n\n scratch_dtype = cutlass.Float4E2M1FN\n weight_dtype = cutlass.Float4E2M1FN\n sf_dtype = cutlass.Float8E4M3FN\n a_dtype = cutlass.BFloat16\n alpha_dtype = cutlass.Float32\n\n kernel: Any = MoEDynamicKernel(\n sf_vec_size=sf_vec_size,\n mma_tiler_mn=mma_tiler_mn,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n share_input_across_experts=share_input_across_experts,\n )\n launch = _DynamicMoELaunch(\n kernel,\n k=k,\n num_topk=num_topk,\n activation_precision=activation_precision,\n )\n\n topk_ids_cutlass_dtype = (\n cutlass.Int32 if topk_ids_dtype == torch.int32 else cutlass.Int64\n )\n topk_ids_align = 4 if topk_ids_dtype == torch.int32 else 8\n\n # Runtime-shaped tensors passed as pointers\n a_input_fake = make_ptr(a_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n topk_ids_fake = make_ptr(\n topk_ids_cutlass_dtype,\n topk_ids_align,\n cute.AddressSpace.gmem,\n assumed_align=topk_ids_align,\n )\n topk_weights_fake = make_ptr(\n cutlass.Float32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n packed_a_fake = make_ptr(\n scratch_dtype, 16, cute.AddressSpace.gmem, assumed_align=16\n )\n sfa_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n packed_a_storage_fake = make_ptr(\n cutlass.Uint8, 16, cute.AddressSpace.gmem, assumed_align=16\n )\n scale_storage_fake = make_ptr(\n cutlass.Uint8, 16, cute.AddressSpace.gmem, assumed_align=16\n )\n\n barrier_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n barrier_epoch_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n pair_head_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n task_head_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n task_tail_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n\n task_expert_fake = make_ptr(\n cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n task_valid_rows_fake = make_ptr(\n cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n\n b_w13_fake = cute.runtime.make_fake_compact_tensor(\n weight_dtype,\n (w1_rows, k, E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_w13_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n b_down_fake = cute.runtime.make_fake_compact_tensor(\n weight_dtype,\n (k, n, E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_down_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n row_counts_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (E,), assumed_align=4\n )\n expert_write_rows_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (E,), assumed_align=4\n )\n expert_tile_base_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (E + 1,), assumed_align=4\n )\n input_gs_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype, (E,), assumed_align=16\n )\n alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype, (E,), assumed_align=16\n )\n down_alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype, (E,), assumed_align=16\n )\n global_scale_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype, (E,), assumed_align=16\n )\n scatter_fake = make_ptr(a_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n token_map_fake = make_ptr(cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4)\n token_weights_fake = make_ptr(\n alpha_dtype, 16, cute.AddressSpace.gmem, assumed_align=16\n )\n\n compiled = cute.compile(\n launch,\n a_input_fake,\n topk_ids_fake,\n topk_weights_fake,\n packed_a_fake,\n sfa_fake,\n packed_a_storage_fake,\n scale_storage_fake,\n barrier_count_fake,\n barrier_epoch_fake,\n pair_head_fake,\n task_head_fake,\n task_tail_fake,\n task_expert_fake,\n task_valid_rows_fake,\n b_w13_fake,\n sfb_w13_fake,\n b_down_fake,\n sfb_down_fake,\n row_counts_fake,\n expert_write_rows_fake,\n expert_tile_base_fake,\n input_gs_fake,\n alpha_fake,\n down_alpha_fake,\n global_scale_fake,\n scatter_fake,\n token_map_fake,\n token_weights_fake,\n 1,\n 1,\n 1,\n 1, # runtime Int32 placeholders\n mac,\n current_cuda_stream(),\n options=\"--opt-level 2 --enable-tvm-ffi\",\n )\n\n result = (compiled, mac)\n _DYNAMIC_KERNEL_CACHE[cache_key] = result\n return result\n\n\n# ---------------------------------------------------------------------------\n# Dynamic launch\n# ---------------------------------------------------------------------------\ndef launch_sm120_dynamic_moe(\n *,\n workspace: Sm120DynamicMoEWorkspace,\n weights: _WeightViews,\n a: torch.Tensor,\n topk_ids: torch.Tensor,\n topk_weights: torch.Tensor,\n input_gs: torch.Tensor,\n down_input_scale: torch.Tensor,\n scatter_output: torch.Tensor,\n num_experts: int,\n num_tokens: int,\n k: int,\n n: int,\n top_k: int,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n) -> torch.Tensor:\n \"\"\"Launch the SM120 dynamic MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 dynamic launcher\"\n )\n _check_memref_limit(\"scatter_output\", scatter_output.numel())\n flat_ids = topk_ids.view(-1).to(torch.int32)\n flat_weights = topk_weights.view(-1).to(torch.float32)\n input_gs_is_shared = input_gs.numel() == 1\n\n # Broadcast scalar scales to per-expert [E] tensors\n input_gs = _expand_to_experts(input_gs, num_experts)\n down_input_scale = _expand_to_experts(down_input_scale, num_experts)\n\n compiled, mac = _get_dynamic_kernel(\n num_experts,\n num_tokens,\n k,\n n,\n top_k,\n workspace.max_rows,\n topk_ids_dtype=torch.int32,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n activation_precision=activation_precision,\n share_input_across_experts=input_gs_is_shared,\n tile_m=workspace.tile_m,\n )\n\n # Dynamic kernel: runtime-shaped args are DataPointer (pass data_ptr()),\n # fixed-shape args are Tensor (pass torch tensor directly).\n runtime_args: Tuple[Any, ...] = (\n a.data_ptr(),\n flat_ids.data_ptr(),\n flat_weights.data_ptr(),\n workspace.packed_a_view.data_ptr(),\n workspace.packed_input_scale.data_ptr(),\n workspace.packed_a_flat.data_ptr(),\n workspace.scale_flat.data_ptr(),\n workspace.barrier_count,\n workspace.barrier_epoch,\n workspace.pair_head,\n workspace.task_head,\n workspace.task_tail,\n workspace.task_expert.data_ptr(),\n workspace.task_valid_rows.data_ptr(),\n weights.w13_fp4,\n weights._w13_sf_storage.data_ptr(),\n weights.down_fp4,\n weights._down_sf_storage.data_ptr(),\n workspace.row_counts,\n workspace.expert_write_rows,\n workspace.expert_tile_base,\n input_gs,\n weights.w1_alpha,\n weights.w2_alpha,\n down_input_scale,\n scatter_output.data_ptr(),\n workspace.token_map.data_ptr(),\n workspace.token_weights.data_ptr(),\n num_tokens,\n workspace.max_rows,\n workspace.physical_tiles_capacity * workspace.tile_m,\n workspace.task_capacity,\n )\n compiled(*runtime_args, current_cuda_stream())\n\n return scatter_output\n\n\n# ==========================================================================\n# W4A16 route-packing implementation\n# ==========================================================================\n@dataclass(kw_only=True)\nclass Sm120W4A16MoEWorkspace:\n \"\"\"Scratch buffers for the SM120 W4A16 MoE path.\"\"\"\n\n state_E: int\n weight_E: int\n max_rows: int\n k: int\n n: int\n num_topk: int\n device: torch.device\n activation: str\n activation_precision: str\n quant_mode: str\n routed_rows_capacity: int\n route_num_experts: int\n\n intermediate_cache13: torch.Tensor\n intermediate_cache2: torch.Tensor\n fc1_c_tmp: torch.Tensor\n fc2_c_tmp: torch.Tensor\n packed_route_indices: torch.Tensor\n block_expert_ids: torch.Tensor\n packed_route_count: torch.Tensor\n expert_offsets: torch.Tensor\n expert_map: torch.Tensor | None = None\n\n\ndef _is_cuda_graph_capturing() -> bool:\n try:\n return bool(torch.cuda.is_current_stream_capturing())\n except Exception:\n return False\n\n\ndef _canonical_cuda_device(device: torch.device) -> torch.device:\n device = torch.device(device)\n if device.type == \"cuda\" and device.index is None:\n return torch.device(\"cuda\", torch.cuda.current_device())\n return device\n\n\ndef _w4a16_workspace_geometry(\n *,\n routed_rows: int,\n route_num_experts: int,\n k: int,\n n: int,\n is_gated: bool,\n device: torch.device,\n) -> tuple[int, int, int, int, int]:\n route_slots = 1\n route_blocks = 1\n fc1_c_tmp_elements = 1\n fc2_c_tmp_elements = 1\n fc1_cols = (2 if is_gated else 1) * int(n)\n sms = get_num_sm(device)\n for block_size in _W4A16_ALLOWED_ROUTED_SIZES:\n slots = max_packed_route_slots(\n int(routed_rows),\n int(block_size),\n int(route_num_experts),\n )\n blocks = (slots + int(block_size) - 1) // int(block_size)\n route_slots = max(route_slots, slots)\n route_blocks = max(route_blocks, blocks)\n fc1_c_tmp_elements = max(\n fc1_c_tmp_elements,\n packed_gemm_scratch_elements(\n size_n=fc1_cols,\n route_slots=slots,\n moe_block_size=int(block_size),\n sms=sms,\n ),\n )\n fc2_c_tmp_elements = max(\n fc2_c_tmp_elements,\n packed_gemm_scratch_elements(\n size_n=int(k),\n route_slots=slots,\n moe_block_size=int(block_size),\n sms=sms,\n ),\n )\n return (\n route_slots,\n route_blocks,\n fc1_c_tmp_elements,\n fc2_c_tmp_elements,\n fc1_cols,\n )\n\n\ndef _make_w4a16_expert_map(\n *,\n state_E: int,\n weight_E: int,\n device: torch.device,\n) -> torch.Tensor | None:\n if int(state_E) == int(weight_E):\n return None\n if int(state_E) > int(weight_E):\n raise ValueError(\"num_local_experts cannot exceed num_experts\")\n expert_map = torch.empty((int(weight_E),), dtype=torch.int32, device=device)\n expert_map.fill_(-1)\n expert_map[: int(state_E)].copy_(\n torch.arange(int(state_E), dtype=torch.int32, device=device)\n )\n return expert_map\n\n\ndef _allocate_sm120_w4a16_workspace(\n *,\n state_E: int,\n weight_E: int,\n routed_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation: str = \"silu\",\n) -> Sm120W4A16MoEWorkspace:\n is_gated = validate_activation(activation)\n routed_rows = max(1, int(routed_rows))\n route_num_experts = int(weight_E) if int(state_E) != int(weight_E) else int(state_E)\n (\n route_slots,\n route_blocks,\n fc1_c_tmp_elements,\n fc2_c_tmp_elements,\n fc1_cols,\n ) = _w4a16_workspace_geometry(\n routed_rows=routed_rows,\n route_num_experts=route_num_experts,\n k=k,\n n=n,\n is_gated=is_gated,\n device=device,\n )\n return Sm120W4A16MoEWorkspace(\n state_E=int(state_E),\n weight_E=int(weight_E),\n max_rows=routed_rows,\n k=int(k),\n n=int(n),\n num_topk=int(num_topk),\n device=device,\n activation=activation,\n activation_precision=\"bf16\",\n quant_mode=\"w4a16\",\n routed_rows_capacity=routed_rows,\n route_num_experts=route_num_experts,\n intermediate_cache13=torch.empty(\n (routed_rows * max(fc1_cols, int(k)),),\n dtype=torch.bfloat16,\n device=device,\n ),\n intermediate_cache2=torch.empty(\n (routed_rows, int(n)),\n dtype=torch.bfloat16,\n device=device,\n ),\n fc1_c_tmp=torch.empty(\n (fc1_c_tmp_elements,),\n dtype=torch.float32,\n device=device,\n ),\n fc2_c_tmp=torch.empty(\n (fc2_c_tmp_elements,),\n dtype=torch.float32,\n device=device,\n ),\n packed_route_indices=torch.empty(\n (route_slots,),\n dtype=torch.int32,\n device=device,\n ),\n block_expert_ids=torch.empty(\n (route_blocks,),\n dtype=torch.int32,\n device=device,\n ),\n packed_route_count=torch.empty((1,), dtype=torch.int32, device=device),\n expert_offsets=torch.empty(\n (route_num_experts + 1,),\n dtype=torch.int32,\n device=device,\n ),\n expert_map=_make_w4a16_expert_map(\n state_E=state_E,\n weight_E=weight_E,\n device=device,\n ),\n )\n\n\n_W4A16_WEIGHT_CACHE: Dict[Tuple, W4A16PackedWeights] = {}\n\n\ndef _get_w4a16_packed_weights(\n *,\n w1_weight: torch.Tensor,\n w1_weight_sf: torch.Tensor,\n w1_alpha: torch.Tensor,\n w2_weight: torch.Tensor,\n w2_weight_sf: torch.Tensor,\n w2_alpha: torch.Tensor,\n activation: str,\n params_dtype: torch.dtype,\n source_format: str = \"modelopt\",\n) -> W4A16PackedWeights:\n key = (\n activation,\n params_dtype,\n source_format,\n tuple(w1_weight.shape),\n tuple(w1_weight_sf.shape),\n tuple(w1_alpha.shape),\n tuple(w2_weight.shape),\n tuple(w2_weight_sf.shape),\n tuple(w2_alpha.shape),\n w1_weight.data_ptr(),\n w1_weight_sf.data_ptr(),\n w1_alpha.data_ptr(),\n w2_weight.data_ptr(),\n w2_weight_sf.data_ptr(),\n w2_alpha.data_ptr(),\n )\n cached = _W4A16_WEIGHT_CACHE.get(key)\n if cached is not None:\n return cached\n if _is_cuda_graph_capturing():\n raise RuntimeError(\n \"W4A16 packed weights are not initialized for CUDA graph capture; \"\n \"run once before capture so the prepared weights are cached.\"\n )\n prepared = prepare_w4a16_packed_weights(\n w1_weight,\n w1_weight_sf,\n w1_alpha,\n w2_weight,\n w2_weight_sf,\n w2_alpha,\n activation=activation,\n params_dtype=params_dtype,\n source_format=source_format,\n )\n _W4A16_WEIGHT_CACHE[key] = prepared\n _register_cache_eviction(\n _W4A16_WEIGHT_CACHE,\n key,\n w1_weight,\n w1_weight_sf,\n w1_alpha,\n w2_weight,\n w2_weight_sf,\n w2_alpha,\n )\n return prepared\n\n\ndef _validate_w4a16_workspace(\n workspace: Sm120W4A16MoEWorkspace,\n *,\n state_E: int,\n weight_E: int,\n routed_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation: str,\n) -> None:\n validate_activation(activation)\n if workspace.state_E != int(state_E) or workspace.weight_E != int(weight_E):\n raise ValueError(\"pre-allocated W4A16 workspace expert geometry mismatch\")\n if workspace.k != int(k) or workspace.n != int(n):\n raise ValueError(\"pre-allocated W4A16 workspace hidden geometry mismatch\")\n if workspace.num_topk != int(num_topk):\n raise ValueError(\"pre-allocated W4A16 workspace top-k mismatch\")\n if getattr(workspace, \"activation\", None) != activation:\n raise ValueError(\"pre-allocated W4A16 workspace activation mismatch\")\n if _canonical_cuda_device(workspace.device) != _canonical_cuda_device(device):\n raise ValueError(\n f\"pre-allocated W4A16 workspace is on {workspace.device}, expected {device}\"\n )\n if workspace.routed_rows_capacity < max(1, int(routed_rows)):\n raise ValueError(\n \"pre-allocated W4A16 workspace is too small for the requested \"\n f\"routed rows ({workspace.routed_rows_capacity} < {routed_rows})\"\n )\n\n\ndef _launch_sm120_w4a16_moe(\n *,\n a: torch.Tensor,\n topk_ids: torch.Tensor,\n topk_weights: torch.Tensor,\n w1_weight: torch.Tensor,\n w1_weight_sf: torch.Tensor,\n w1_alpha: torch.Tensor,\n w2_weight: torch.Tensor,\n w2_weight_sf: torch.Tensor,\n w2_alpha: torch.Tensor,\n num_experts: int,\n top_k: int,\n num_local_experts: int,\n scatter_output: torch.Tensor,\n fast_math: bool = True,\n activation: str = \"silu\",\n source_format: str = \"modelopt\",\n _workspace=None,\n _prepared_weights=None,\n) -> torch.Tensor:\n prepared = (\n _prepared_weights\n if isinstance(_prepared_weights, W4A16PackedWeights)\n else _get_w4a16_packed_weights(\n w1_weight=w1_weight,\n w1_weight_sf=w1_weight_sf,\n w1_alpha=w1_alpha,\n w2_weight=w2_weight,\n w2_weight_sf=w2_weight_sf,\n w2_alpha=w2_alpha,\n activation=activation,\n params_dtype=a.dtype,\n source_format=source_format,\n )\n )\n if int(prepared.num_experts) != int(num_local_experts):\n raise ValueError(\"num_local_experts must match w1_weight.shape[0] for W4A16.\")\n num_tokens = int(topk_ids.size(0))\n routed_rows = num_tokens * int(top_k)\n k = int(a.size(1))\n n = int(prepared.intermediate_size)\n\n if _workspace is None:\n workspace = _get_cached_workspace(\n backend=\"w4a16\",\n state_E=num_local_experts,\n weight_E=num_experts,\n routed_rows=routed_rows,\n k=k,\n n=n,\n num_topk=top_k,\n device=a.device,\n quant_mode=\"w4a16\",\n activation=activation,\n )\n else:\n workspace = _workspace\n if not isinstance(workspace, Sm120W4A16MoEWorkspace):\n raise TypeError(\"expected a W4A16 workspace for quant_mode='w4a16'\")\n _validate_w4a16_workspace(\n workspace,\n state_E=num_local_experts,\n weight_E=num_experts,\n routed_rows=routed_rows,\n k=k,\n n=n,\n num_topk=top_k,\n device=a.device,\n activation=activation,\n )\n\n return run_w4a16_moe(\n a,\n prepared,\n topk_weights,\n topk_ids,\n activation=activation,\n intermediate_cache13=workspace.intermediate_cache13,\n intermediate_cache2=workspace.intermediate_cache2,\n output=scatter_output,\n fc1_c_tmp=workspace.fc1_c_tmp,\n fc2_c_tmp=workspace.fc2_c_tmp,\n packed_route_indices=workspace.packed_route_indices,\n block_expert_ids=workspace.block_expert_ids,\n packed_route_count=workspace.packed_route_count,\n expert_offsets=workspace.expert_offsets,\n expert_map=workspace.expert_map,\n fast_math=fast_math,\n )\n\n\n# ==========================================================================\n# Workspace cache (for functional API path)\n# ==========================================================================\n\n_Sm120Workspace = Union[\n Sm120StaticMoEWorkspace,\n Sm120DynamicMoEWorkspace,\n Sm120W4A16MoEWorkspace,\n]\n\n# Stores the workspace with the largest capacity seen per key and never\n# shrinks within a process. clear_sm120_moe_caches() releases everything.\n_WORKSPACE_CACHE: Dict[Tuple, _Sm120Workspace] = {}\n\n\ndef clear_sm120_moe_caches() -> None:\n \"\"\"Release every module-level SM12x MoE cache.\n\n References held by callers are unaffected.\n \"\"\"\n _WORKSPACE_CACHE.clear()\n _WEIGHT_CACHE.clear()\n _W4A16_WEIGHT_CACHE.clear()\n _PADDED_WEIGHT_CACHE.clear()\n _STATIC_KERNEL_CACHE.clear()\n _MICRO_KERNEL_CACHE.clear()\n _DIRECT_MICRO_LAUNCH_CACHE.clear()\n _DIRECT_MICRO_KERNEL_CACHE.clear()\n _DYNAMIC_KERNEL_CACHE.clear()\n\n\ndef allocate_sm120_moe_workspace(\n *,\n state_E: int,\n weight_E: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n max_rows: int | None = None,\n routed_rows: int | None = None,\n quant_mode: str | None = None,\n activation_precision: str | None = None,\n backend: str | None = None,\n activation: str = \"silu\",\n) -> _Sm120Workspace:\n \"\"\"Allocate the right SM120 MoE workspace from a quantization mode.\"\"\"\n mode = _normalize_quant_mode(quant_mode, activation_precision)\n capacity_rows = routed_rows if routed_rows is not None else max_rows\n if capacity_rows is None:\n raise ValueError(\"routed_rows or max_rows is required\")\n capacity_rows = max(1, int(capacity_rows))\n device = torch.device(device)\n\n if mode == \"w4a16\":\n if backend not in (None, \"w4a16\"):\n raise ValueError(\"quant_mode='w4a16' does not use static/dynamic backend\")\n return _allocate_sm120_w4a16_workspace(\n state_E=state_E,\n weight_E=weight_E,\n routed_rows=capacity_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation=activation,\n )\n\n activation_precision = \"fp4\"\n if backend is None:\n backend = select_sm120_moe_backend(\n num_tokens=max(\n 1, (capacity_rows + max(1, int(num_topk)) - 1) // max(1, int(num_topk))\n ),\n num_topk=int(num_topk),\n activation_precision=activation_precision,\n )\n if backend == \"dynamic\":\n return allocate_sm120_dynamic_workspace(\n state_E=state_E,\n weight_E=weight_E,\n routed_rows=capacity_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation_precision=activation_precision,\n activation=activation,\n )\n if backend == \"static\":\n return allocate_sm120_static_workspace(\n state_E=state_E,\n weight_E=weight_E,\n max_rows=capacity_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation_precision=activation_precision,\n )\n raise ValueError(f\"unsupported SM120 MoE backend {backend!r}\")\n\n\ndef _get_cached_workspace(\n *,\n backend: str,\n state_E: int,\n weight_E: int,\n routed_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation_precision: str = \"fp4\",\n quant_mode: str | None = None,\n activation: str = \"silu\",\n) -> _Sm120Workspace:\n \"\"\"Get or allocate a cached workspace for the given problem shape.\n\n Reuses the cached workspace if it has enough capacity for the requested\n routed_rows. For static workspaces, max_rows is the direct capacity.\n For dynamic workspaces, routed_rows_capacity is used because the dynamic\n geometry (physical tiles, task queue slots) depends on the original\n routed_rows, not just max_rows.\n \"\"\"\n quant_mode = _normalize_quant_mode(quant_mode, activation_precision)\n activation_precision = _activation_precision_from_quant_mode(quant_mode)\n # Key dynamic workspaces on the tile band of this call's routed_rows; a\n # larger cached workspace must not pin small calls to its 128 tile.\n tile_m = (\n _select_dynamic_tile_m(max(1, routed_rows), state_E, activation)\n if backend == \"dynamic\" and quant_mode != \"w4a16\"\n else None\n )\n cache_key = (\n state_E,\n weight_E,\n k,\n n,\n num_topk,\n str(device),\n backend,\n quant_mode,\n activation,\n tile_m,\n )\n cached = _WORKSPACE_CACHE.get(cache_key)\n\n if cached is not None:\n if isinstance(cached, Sm120DynamicMoEWorkspace):\n if cached.routed_rows_capacity >= max(1, routed_rows):\n assert tile_m is None or cached.tile_m == tile_m\n return cached\n elif isinstance(cached, Sm120W4A16MoEWorkspace):\n if cached.routed_rows_capacity >= max(1, routed_rows):\n return cached\n else:\n if cached.max_rows >= max(1, routed_rows):\n return cached\n\n if quant_mode == \"w4a16\" and _is_cuda_graph_capturing():\n raise RuntimeError(\n \"W4A16 workspace is not initialized for CUDA graph capture; \"\n \"provide a preallocated workspace from \"\n \"allocate_sm120_moe_workspace(..., quant_mode='w4a16') or warm the \"\n \"functional path before capture.\"\n )\n workspace = allocate_sm120_moe_workspace(\n state_E=state_E,\n weight_E=weight_E,\n routed_rows=routed_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n quant_mode=quant_mode,\n activation_precision=activation_precision,\n backend=backend,\n activation=activation,\n )\n\n _WORKSPACE_CACHE[cache_key] = workspace\n return workspace\n\n\n# ==========================================================================\n# Unified dispatch\n# ==========================================================================\n_PADDED_WEIGHT_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _pad_intermediate_to_tile(\n w1_weight,\n w1_weight_sf,\n w2_weight,\n w2_weight_sf,\n fc2_input_scale,\n n,\n tile,\n h,\n num_experts,\n is_gated,\n):\n \"\"\"Zero-pad NVFP4 weights + scale factors so the intermediate size is a\n multiple of ``tile`` (gate/up tile-split requirement); padded channels are\n zero, so the result is numerically identical.\n \"\"\"\n n_pad = ((n + tile - 1) // tile) * tile\n if n_pad == n:\n return w1_weight, w1_weight_sf, w2_weight, w2_weight_sf, fc2_input_scale, n\n E = int(num_experts)\n fc2_input_scale_src = fc2_input_scale\n key = (\n n,\n tile,\n h,\n E,\n bool(is_gated),\n w1_weight.data_ptr(),\n w1_weight_sf.data_ptr(),\n w2_weight.data_ptr(),\n w2_weight_sf.data_ptr(),\n fc2_input_scale_src.data_ptr() if fc2_input_scale_src is not None else 0,\n )\n cached = _PADDED_WEIGHT_CACHE.get(key)\n if cached is not None:\n return cached\n\n def mma_to_logical(sf, m, k):\n sw = convert_sf_from_mma_layout(sf, m=m, k=k, num_groups=E)\n m_pad = ((m + 127) // 128) * 128\n sw = sw.reshape(E, m_pad, -1)\n cb = (k + SF_VEC_SIZE - 1) // SF_VEC_SIZE\n return torch.stack(\n [unswizzle_block_scale(sw[e], rows=m, cols_blocks=cb) for e in range(E)], 0\n )\n\n def logical_to_mma(log, m, k):\n sw = torch.stack([swizzle_block_scale(log[e]) for e in range(E)], 0)\n sw2d = sw.reshape(E * sw.shape[1], sw.shape[2]).to(torch.float8_e4m3fn)\n return convert_sf_to_mma_layout(sw2d, m=m, k=k, num_groups=E)\n\n def pad_dim(t, dim, old, new):\n if new == old:\n return t\n shp = list(t.shape)\n shp[dim] = new - old\n return torch.cat([t, t.new_zeros(shp)], dim=dim)\n\n if is_gated:\n # w1 packs [up(0:n), gate(n:2n)] rows; pad each half so the split stays\n # tile-aligned, then re-concat.\n up, gate = w1_weight[:, :n, :], w1_weight[:, n : 2 * n, :]\n w1p = torch.cat([pad_dim(up, 1, n, n_pad), pad_dim(gate, 1, n, n_pad)], dim=1)\n log1 = mma_to_logical(w1_weight_sf, m=2 * n, k=h)\n up_sf, gate_sf = log1[:, :n, :], log1[:, n : 2 * n, :]\n log1p = torch.cat(\n [pad_dim(up_sf, 1, n, n_pad), pad_dim(gate_sf, 1, n, n_pad)], dim=1\n )\n w1_sf_p = logical_to_mma(log1p, m=2 * n_pad, k=h)\n else:\n w1p = pad_dim(w1_weight, 1, n, n_pad)\n log1 = mma_to_logical(w1_weight_sf, m=n, k=h)\n w1_sf_p = logical_to_mma(pad_dim(log1, 1, n, n_pad), m=n_pad, k=h)\n\n # w2 reduces over the intermediate dim: pad its packed columns + SF columns.\n w2p = pad_dim(w2_weight, 2, n // 2, n_pad // 2)\n log2 = mma_to_logical(w2_weight_sf, m=h, k=n)\n cb_n = (n + SF_VEC_SIZE - 1) // SF_VEC_SIZE\n cb_np = (n_pad + SF_VEC_SIZE - 1) // SF_VEC_SIZE\n w2_sf_p = logical_to_mma(pad_dim(log2, 2, cb_n, cb_np), m=h, k=n_pad)\n\n if fc2_input_scale_src is not None and fc2_input_scale_src.numel() == n:\n fc2_input_scale = pad_dim(fc2_input_scale_src, 0, n, n_pad)\n result = (w1p, w1_sf_p, w2p, w2_sf_p, fc2_input_scale, n_pad)\n _PADDED_WEIGHT_CACHE[key] = result\n _register_cache_eviction(\n _PADDED_WEIGHT_CACHE,\n key,\n w1_weight,\n w1_weight_sf,\n w2_weight,\n w2_weight_sf,\n fc2_input_scale_src,\n )\n return result\n\n\ndef launch_sm120_moe(\n *,\n a: torch.Tensor,\n topk_ids: torch.Tensor,\n topk_weights: torch.Tensor,\n w1_weight: torch.Tensor,\n w1_weight_sf: torch.Tensor,\n w1_alpha: torch.Tensor,\n fc2_input_scale: Optional[torch.Tensor] = None,\n input_global_scale: Optional[torch.Tensor] = None,\n w2_weight: torch.Tensor,\n w2_weight_sf: torch.Tensor,\n w2_alpha: torch.Tensor,\n num_experts: int,\n top_k: int,\n num_local_experts: int,\n scatter_output: torch.Tensor,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n quant_mode: str | None = None,\n source_format: str = \"modelopt\",\n _workspace=None,\n _weight_views=None,\n _prepared_weights=None,\n) -> torch.Tensor:\n \"\"\"Unified SM120 MoE dispatch — selects static or dynamic by token count.\n\n input_global_scale overrides w1_alpha as the FC1 input-quant scale and\n is folded into the multiplier internally. With _weight_views supplied,\n w1_alpha must already contain the fold.\n\n Optional _workspace and _weight_views can be pre-allocated and reused\n across calls to avoid per-call allocation overhead (wrapper path).\n When not provided (functional API path), a module-level workspace cache\n is used to avoid re-allocating on every call.\n \"\"\"\n quant_mode = _normalize_quant_mode(quant_mode, activation_precision)\n source_format = _normalize_source_format_for_quant_mode(source_format, quant_mode)\n activation_precision = _activation_precision_from_quant_mode(quant_mode)\n\n num_tokens = topk_ids.size(0)\n k = a.size(1) # hidden_size\n is_gated = is_gated_activation(activation)\n # w1_weight.size(1) is 2*n for gated or n for non-gated\n intermediate_size = w1_weight.size(1) // 2 if is_gated else w1_weight.size(1)\n n = intermediate_size\n\n # NVFP4 kernels need padded intermediate size.\n if quant_mode != \"w4a16\" and n % _LEVEL_TILE_N != 0 and _weight_views is None:\n (\n w1_weight,\n w1_weight_sf,\n w2_weight,\n w2_weight_sf,\n fc2_input_scale,\n n,\n ) = _pad_intermediate_to_tile(\n w1_weight,\n w1_weight_sf,\n w2_weight,\n w2_weight_sf,\n fc2_input_scale,\n n,\n _LEVEL_TILE_N,\n k,\n w1_weight.size(0),\n is_gated,\n )\n\n routed_rows = num_tokens * top_k\n\n if quant_mode == \"w4a16\":\n return _launch_sm120_w4a16_moe(\n a=a,\n topk_ids=topk_ids,\n topk_weights=topk_weights,\n w1_weight=w1_weight,\n w1_weight_sf=w1_weight_sf,\n w1_alpha=w1_alpha,\n w2_weight=w2_weight,\n w2_weight_sf=w2_weight_sf,\n w2_alpha=w2_alpha,\n num_experts=num_experts,\n top_k=top_k,\n num_local_experts=num_local_experts,\n scatter_output=scatter_output,\n fast_math=fast_math,\n activation=activation,\n source_format=source_format,\n _workspace=_workspace,\n _prepared_weights=_prepared_weights,\n )\n\n if fc2_input_scale is None:\n raise ValueError(\"fc2_input_scale is required when quant_mode='nvfp4'.\")\n down_input_scale = fc2_input_scale\n if input_global_scale is not None:\n input_gs = input_global_scale\n if _weight_views is None:\n # Alpha must carry input_gs back or the output magnitude is wrong.\n # The wrapper folds before building _weight_views; don't fold twice.\n w1_alpha = (\n w1_alpha.to(torch.float32) * input_global_scale.to(torch.float32)\n ).contiguous()\n else:\n input_gs = w1_alpha\n\n weights = (\n _weight_views\n if _weight_views is not None\n else _get_weight_views(\n w1_fp4=w1_weight,\n w1_blockscale=w1_weight_sf,\n w2_fp4=w2_weight,\n w2_blockscale=w2_weight_sf,\n w1_alphas=w1_alpha,\n w2_alphas=w2_alpha,\n n=n,\n k=k,\n activation_precision=activation_precision,\n )\n )\n\n # Resolve workspace and backend selection.\n # When a pre-allocated workspace is provided (CUDA graph wrapper path),\n # infer the backend from the workspace type so they stay in sync —\n # the caller already committed to a backend at allocation time.\n if _workspace is not None:\n workspace = _workspace\n workspace_activation_precision = getattr(\n workspace, \"activation_precision\", activation_precision\n )\n if workspace_activation_precision != activation_precision:\n raise ValueError(\n \"pre-allocated workspace activation_precision does not match \"\n f\"requested activation_precision={activation_precision!r}.\"\n )\n if isinstance(workspace, Sm120DynamicMoEWorkspace):\n if num_local_experts != num_experts:\n raise ValueError(\n \"pre-allocated dynamic SM120 MoE workspace requires \"\n \"num_local_experts == num_experts because dynamic expert \"\n \"buffers are indexed by global topk ids.\"\n )\n # A pre-allocated dynamic workspace keeps its stored tile_m even\n # for smaller calls; its geometry was sized for that tile.\n backend = \"dynamic\"\n else:\n backend = \"static\"\n else:\n backend = select_sm120_moe_backend(\n num_tokens=num_tokens,\n num_topk=top_k,\n activation_precision=activation_precision,\n )\n # The dynamic kernel indexes row_counts/expert_write_rows directly with\n # topk_ids but those buffers are sized with num_local_experts. Unless\n # num_local_experts == num_experts, fall back to the static backend which\n # has global-to-local expert remapping.\n if backend == \"dynamic\" and num_local_experts != num_experts:\n backend = \"static\"\n workspace = _get_cached_workspace(\n backend=backend,\n state_E=num_local_experts,\n weight_E=num_experts,\n routed_rows=routed_rows,\n k=k,\n n=n,\n num_topk=top_k,\n device=a.device,\n activation_precision=activation_precision,\n quant_mode=quant_mode,\n activation=activation,\n )\n\n if backend == \"dynamic\":\n return launch_sm120_dynamic_moe(\n workspace=workspace,\n weights=weights,\n a=a,\n topk_ids=topk_ids,\n topk_weights=topk_weights,\n input_gs=input_gs,\n down_input_scale=down_input_scale,\n scatter_output=scatter_output,\n num_experts=num_experts,\n num_tokens=num_tokens,\n k=k,\n n=n,\n top_k=top_k,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n activation_precision=activation_precision,\n )\n else:\n return launch_sm120_static_moe(\n workspace=workspace,\n weights=weights,\n a=a,\n topk_ids=topk_ids,\n topk_weights=topk_weights,\n input_gs=input_gs,\n down_input_scale=down_input_scale,\n scatter_output=scatter_output,\n num_experts=num_experts,\n num_tokens=num_tokens,\n k=k,\n n=n,\n top_k=top_k,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n activation_precision=activation_precision,\n )\n"},"diff":{"kind":"string","value":"--- flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_dispatch.py\n+++ flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_dispatch.py\n@@ -24,8 +24,14 @@\n get_num_sm,\n make_ptr,\n )\n-from .moe_activation import is_gated_activation\n-from .moe_dynamic_kernel import MoEDynamicKernel\n+from .moe_activation import SWIGLUOAI_UNINTERLEAVE, is_gated_activation\n+from .moe_direct_micro_kernel import (\n+ MoEDirectMicroKernel,\n+ build_direct_micro_kernel,\n+ compile_direct_micro_kernel,\n+ compiled_direct_micro_accepts_block_dim,\n+)\n+from .moe_dynamic_kernel import _TASK_SLICE_CHUNK, MoEDynamicKernel\n from .moe_micro_kernel import MoEMicroKernel\n from .moe_static_kernel import MoEStaticKernel\n from .moe_w4a16_fp4_helpers import swizzle_block_scale\n@@ -49,7 +55,9 @@\n _NVFP4_BLOCK_SIZE = 16\n _LEVEL_TILE_M = 128\n _LEVEL_TILE_N = 128\n-_DYNAMIC_SLICE_CHUNK = 1\n+# Must equal the kernel's task materialization granularity or the task\n+# queue is mis-sized.\n+_DYNAMIC_SLICE_CHUNK = _TASK_SLICE_CHUNK\n SF_VEC_SIZE = 16\n _FORCE_MOE_W4A16_ENV = \"FLASHINFER_B12X_FORCE_MOE_W4A16\"\n _MICRO_SHARE_INPUT_ACROSS_EXPERTS = (\n@@ -59,6 +67,16 @@\n # Micro kernel cutover thresholds (routed pairs)\n _MICRO_COMPACT_CUTOVER_PAIRS = 20\n _MICRO_COMPACT_CUTOVER_PAIRS_MULTI_TOPK = 40\n+# The micro kernel's per-token staging assumes decode-sized batches.\n+_MICRO_MAX_TOKENS = 8\n+# Direct micro takes the smallest decode batches ahead of the MMA micro\n+# kernel, and only at small intermediate sizes where its CUDA-core dots\n+# keep up with per-token work. Measured on GB10, pending other GPUs.\n+_DIRECT_MICRO_CUTOVER_PAIRS = 32\n+_DIRECT_MICRO_MAX_N = 512\n+# Test/bench hook: force one backend (\"direct_micro\", \"micro\", \"static\",\n+# \"dynamic\"). Deliberately module-level (a monkeypatch target), not an env var.\n+_FORCED_BACKEND: str | None = None\n _STATIC_COMPACT_CUTOVER_PAIRS_DEFAULT = 640\n _STATIC_COMPACT_CUTOVER_PAIRS = _STATIC_COMPACT_CUTOVER_PAIRS_DEFAULT\n _STATIC_COMPACT_CUTOVER_PAIRS_CACHE: Dict[str, int] = {}\n@@ -90,6 +108,12 @@\n (512, 175),\n (640, 188),\n )\n+# Workloads at or below the static cutover (640 routed pairs by default)\n+# take the static kernel, so only the 1024 entry is normally reachable.\n+_DYNAMIC_MAC_LADDER: Tuple[Tuple[int, int], ...] = (\n+ (640, 188),\n+ (1024, 147),\n+)\n \n \n def _lookup_mac_ladder(\n@@ -104,6 +128,20 @@\n \n def _align_up(value: int, alignment: int) -> int:\n return ((value + alignment - 1) // alignment) * alignment\n+\n+\n+# The kernels index the packed activation and scale planes with 32-bit\n+# offsets, so reject any workspace plane large enough to overflow them.\n+_RUNTIME_MEMREF_LIMIT = (1 << 31) - 1\n+\n+\n+def _check_memref_limit(name: str, elements: int) -> None:\n+ if elements > _RUNTIME_MEMREF_LIMIT:\n+ raise ValueError(\n+ f\"{name} needs {elements} elements, which exceeds the 2^31-1 \"\n+ \"runtime memref limit. Reduce the token chunk or expert count \"\n+ \"for this launch.\"\n+ )\n \n \n def _first_env(*names: str) -> str | None:\n@@ -182,20 +220,37 @@\n return _normalize_activation_precision(activation_precision) == \"bf16\"\n \n \n-def _level_tile_m(activation_precision: str = \"fp4\") -> int:\n- if _is_w4a16(activation_precision):\n- raise ValueError(\n- \"internal routing error: quant_mode='w4a16' reached the NVFP4 tile selector\"\n- )\n- return _LEVEL_TILE_M\n-\n-\n def _level_tile_n(activation_precision: str = \"fp4\") -> int:\n if _is_w4a16(activation_precision):\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 tile selector\"\n )\n return _LEVEL_TILE_N\n+\n+\n+def _select_dynamic_tile_m(\n+ routed_rows: int,\n+ num_experts: int,\n+ activation: str = \"silu\",\n+) -> int:\n+ \"\"\"Pick the dynamic kernel's M-tile from routed rows per expert.\n+\n+ Small tiles cut per-expert tail padding for sparse routing; 128 amortizes\n+ best for dense prefill (crossovers measured on gated NVFP4). Workspace\n+ sizing and the kernel build must both derive the tile from this function,\n+ or the scratch is mis-sized for what the kernel indexes.\n+ \"\"\"\n+ if not is_gated_activation(activation):\n+ return _LEVEL_TILE_M\n+ routed_rows = max(1, int(routed_rows))\n+ num_experts = max(1, int(num_experts))\n+ if routed_rows < 15 * num_experts:\n+ return 16\n+ if routed_rows < 48 * num_experts:\n+ return 32\n+ if routed_rows < 96 * num_experts:\n+ return 64\n+ return _LEVEL_TILE_M\n \n \n def _get_static_compact_cutover_pairs(activation_precision: str = \"fp4\") -> int:\n@@ -219,7 +274,12 @@\n return cached\n \n \n-def _select_moe_mma_tiler_mn(routed_rows: int, n: int) -> Tuple[int, int]:\n+def _select_moe_mma_tiler_mn(\n+ routed_rows: int,\n+ n: int,\n+ *,\n+ resident_clusters: int | None = None,\n+) -> Tuple[int, int]:\n \"\"\"Select optimal MoE tile shape based on routed rows and N dimension.\n \n Uses narrower 64x128 tiles when routed_rows <= 128 and default 128x128\n@@ -227,13 +287,19 @@\n \"\"\"\n sm_count = get_num_sm(torch.device(\"cuda\"))\n coarse_tile = (128, 128)\n+ if routed_rows <= 32 and n <= 256:\n+ return (64, 128)\n+ if resident_clusters is not None and resident_clusters < sm_count:\n+ return coarse_tile\n coarse_tiles = ((routed_rows + coarse_tile[0] - 1) // coarse_tile[0]) * (\n (n + coarse_tile[1] - 1) // coarse_tile[1]\n )\n # Single-token decode often lands exactly on the \"half the machine\"\n # boundary. Keeping the coarse 128x128 tile there leaves the M dimension\n # badly underfilled, so take the narrow 64x128 tile inclusive of equality.\n- if routed_rows <= 128 and coarse_tiles <= max(1, sm_count // 2):\n+ if routed_rows <= 64 or (\n+ routed_rows <= 128 and coarse_tiles <= max(1, sm_count // 2)\n+ ):\n return (64, 128)\n return (128, 128)\n \n@@ -286,6 +352,21 @@\n sfa_ptr: object = None\n packed_a_flat: torch.Tensor | None = None\n scale_flat: torch.Tensor | None = None\n+\n+ # Direct micro planes (allocated only when the shape can take that path).\n+ dm_barrier_count: torch.Tensor | None = None\n+ dm_barrier_epoch: torch.Tensor | None = None\n+ dm_intermediate: torch.Tensor | None = None\n+ dm_input_gs: torch.Tensor | None = None\n+ dm_down_input_scale: torch.Tensor | None = None\n+\n+\n+def _direct_micro_candidate(k: int, n: int, num_topk: int, weight_E: int) -> bool:\n+ \"\"\"Whether any m in the tiny-decode band can run the direct micro kernel.\"\"\"\n+ return any(\n+ MoEDirectMicroKernel.is_supported(m, k, n, num_topk, weight_E)\n+ for m in range(1, _MICRO_MAX_TOKENS + 1)\n+ )\n \n \n def allocate_sm120_static_workspace(\n@@ -309,6 +390,8 @@\n \n rows_pad_k = _align_up(max_rows, 128)\n cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n+ _check_memref_limit(\"static packed_input\", state_E * max_rows * (k // 2))\n+ _check_memref_limit(\"static packed_input_scale\", state_E * rows_pad_k * cols_pad_k)\n packed_input = torch.empty(\n state_E, max_rows, k // 2, dtype=torch.uint8, device=device\n )\n@@ -354,6 +437,33 @@\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n+\n+ # Direct micro reads weights by global expert id, so its planes are only\n+ # useful without EP remapping.\n+ if state_E == weight_E and _direct_micro_candidate(k, n, num_topk, weight_E):\n+ dm_rows = min(max_rows, _MICRO_MAX_TOKENS * num_topk)\n+ # The epoch-based barriers restore their slots after each launch, so\n+ # the zeroed allocation is the only reset needed (graph-replay safe).\n+ dm_slots = dm_rows + _MICRO_MAX_TOKENS * 16\n+ fc2_n_chunks = (n // 2 + 127) // 128\n+ # The fused kernel binds the intermediate as m * num_topk *\n+ # fc2_n_chunks * 128 u32 words; size for the largest supported m.\n+ dm_inter = _MICRO_MAX_TOKENS * num_topk * fc2_n_chunks * 128\n+ workspace.dm_barrier_count = torch.zeros(\n+ dm_slots, dtype=torch.int32, device=device\n+ )\n+ workspace.dm_barrier_epoch = torch.zeros(\n+ dm_slots, dtype=torch.int32, device=device\n+ )\n+ workspace.dm_intermediate = torch.empty(\n+ dm_inter, dtype=torch.float32, device=device\n+ )\n+ workspace.dm_input_gs = torch.empty(\n+ weight_E, dtype=torch.float32, device=device\n+ )\n+ workspace.dm_down_input_scale = torch.empty(\n+ weight_E, dtype=torch.float32, device=device\n+ )\n return workspace\n \n \n@@ -523,7 +633,7 @@\n routed_rows = m * num_topk\n mma_tiler_mn = (128, 128)\n if activation_precision == \"fp4\" and num_topk > 1:\n- mma_tiler_mn = _select_moe_mma_tiler_mn(routed_rows, n)\n+ mma_tiler_mn = _select_moe_mma_tiler_mn(routed_rows, n, resident_clusters=mac)\n \n cache_key = (\n \"static\",\n@@ -975,6 +1085,93 @@\n return result\n \n \n+# The launch cache skips the per-launch build/configure; the kernel cache\n+# dedupes compiles across keys that configure to the same artifact\n+# (m=2..8 differ only in grid_x).\n+_DIRECT_MICRO_LAUNCH_CACHE: Dict[Tuple, Tuple] = {}\n+_DIRECT_MICRO_KERNEL_CACHE: Dict[Tuple, Tuple] = {}\n+\n+\n+def _get_direct_micro_kernel(\n+ weight_E: int,\n+ m: int,\n+ k: int,\n+ n: int,\n+ num_topk: int,\n+ *,\n+ topk_ids_dtype: torch.dtype = torch.int32,\n+ fast_math: bool = True,\n+ share_input_across_experts: bool = False,\n+ share_expert_scales: bool = False,\n+ activation: str = \"silu\",\n+ swiglu_alpha: float = 1.702,\n+ swiglu_beta: float = 1.0,\n+ swiglu_limit: float | None = None,\n+ device: torch.device | None = None,\n+):\n+ \"\"\"Compile (or retrieve cached) the SM120 direct micro MoE kernel.\n+\n+ Returns (compiled, grid_x, accepts_block_dim).\n+ \"\"\"\n+ if activation != SWIGLUOAI_UNINTERLEAVE:\n+ # The kernel constructor only accepts configurable swiglu parameters\n+ # for swigluoai; other activations use its normalized defaults\n+ # (accept-and-ignore, matching the MMA kernels).\n+ swiglu_alpha = None\n+ swiglu_beta = None\n+ swiglu_limit = None\n+ launch_key = (\n+ weight_E,\n+ m,\n+ k,\n+ n,\n+ num_topk,\n+ topk_ids_dtype,\n+ fast_math,\n+ share_input_across_experts,\n+ share_expert_scales,\n+ activation,\n+ swiglu_alpha,\n+ swiglu_beta,\n+ swiglu_limit,\n+ str(_canonical_cuda_device(device)) if device is not None else None,\n+ )\n+ cached = _DIRECT_MICRO_LAUNCH_CACHE.get(launch_key)\n+ if cached is not None:\n+ return cached\n+ kernel = build_direct_micro_kernel(\n+ weight_E,\n+ m,\n+ k,\n+ n,\n+ num_topk,\n+ activation=activation,\n+ fast_math=fast_math,\n+ share_input_across_experts=share_input_across_experts,\n+ share_expert_scales=share_expert_scales,\n+ single_token=m == 1,\n+ swiglu_limit=swiglu_limit,\n+ swiglu_alpha=swiglu_alpha,\n+ swiglu_beta=swiglu_beta,\n+ device=device,\n+ )\n+ compile_key = (\"direct_micro\", kernel.__cache_key__, topk_ids_dtype)\n+ entry = _DIRECT_MICRO_KERNEL_CACHE.get(compile_key)\n+ if entry is None:\n+ compiled = compile_direct_micro_kernel(kernel, topk_ids_dtype=topk_ids_dtype)\n+ # Register pressure can cap the launchable CTA below the fused body's\n+ # 512 threads; probe once per compiled kernel.\n+ accepts = compiled_direct_micro_accepts_block_dim(\n+ compiled, kernel.launch_block_dim\n+ )\n+ entry = (compiled, accepts)\n+ _DIRECT_MICRO_KERNEL_CACHE[compile_key] = entry\n+ compiled, accepts = entry\n+ cached = (compiled, kernel.grid_x, accepts)\n+ _DIRECT_MICRO_LAUNCH_CACHE[launch_key] = cached\n+ return cached\n+\n+\n # ---------------------------------------------------------------------------\n # Launch\n # ---------------------------------------------------------------------------\n@@ -1012,12 +1209,15 @@\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n ) -> torch.Tensor:\n- \"\"\"Launch the SM120 static or micro MoE kernel.\n-\n- Selects the micro kernel for tiny decode batches (routed_rows <= 20-40)\n- and the static kernel otherwise. The micro path runs a Triton pre-pass\n- to compact routing IDs before launching.\n+ \"\"\"Launch the SM120 static, micro, or direct micro MoE kernel.\n+\n+ The direct micro kernel takes tiny decode batches (m <= 8, routed_rows\n+ < 64) when it supports the shape, the MMA micro kernel takes the rest of\n+ its band (routed_rows <= 20-40), and the static kernel takes the rest.\n+ The MMA micro path runs a Triton pre-pass to compact routing IDs before\n+ launching; direct micro routes on global expert ids directly.\n \"\"\"\n+ _check_memref_limit(\"scatter_output\", scatter_output.numel())\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n@@ -1038,19 +1238,6 @@\n # Broadcast scalar scales to per-expert [E] tensors\n input_gs = _expand_to_experts(input_gs, num_experts)\n down_input_scale = _expand_to_experts(down_input_scale, num_experts)\n-\n- # Decide micro vs static\n- micro_cutover = _MICRO_COMPACT_CUTOVER_PAIRS\n- if top_k > 1:\n- micro_cutover = _MICRO_COMPACT_CUTOVER_PAIRS_MULTI_TOPK\n- use_micro = activation_precision == \"fp4\" and routed_rows <= micro_cutover\n-\n- sm_count = get_num_sm(torch.device(\"cuda\"))\n- base_mac = min(get_max_active_clusters(1), sm_count)\n- tuned_static_mac = _lookup_mac_ladder(_STATIC_MAC_LADDER, routed_rows)\n- static_mac = min(tuned_static_mac or base_mac, base_mac)\n- if activation_precision == \"fp4\" and not use_micro and routed_rows < 40:\n- static_mac = min(static_mac, 64)\n \n # Shared-scale flags let compact W4A4 micro match the ReLU2 single-token\n # specialization.\n@@ -1063,6 +1250,131 @@\n share_expert_scales = (\n activation == \"relu2\" and input_gs_is_shared and down_input_scale_is_shared\n )\n+\n+ # Direct micro takes its band before the MMA micro decision. It reads\n+ # weights by global expert id, so EP shapes keep the compact path.\n+ use_direct_micro = (\n+ activation_precision == \"fp4\"\n+ and workspace.state_E == num_experts\n+ and workspace.dm_barrier_count is not None\n+ and workspace.dm_barrier_count.numel() >= routed_rows + num_tokens * 16\n+ and num_tokens <= _MICRO_MAX_TOKENS\n+ and routed_rows < _DIRECT_MICRO_CUTOVER_PAIRS\n+ and n <= _DIRECT_MICRO_MAX_N\n+ and MoEDirectMicroKernel.is_supported(num_tokens, k, n, top_k, num_experts)\n+ )\n+ if _FORCED_BACKEND is not None:\n+ if _FORCED_BACKEND == \"direct_micro\":\n+ if workspace.dm_barrier_count is None or not (\n+ MoEDirectMicroKernel.is_supported(num_tokens, k, n, top_k, num_experts)\n+ ):\n+ raise ValueError(\n+ \"forced direct_micro backend cannot run this shape \"\n+ f\"(m={num_tokens}, k={k}, n={n}, top_k={top_k})\"\n+ )\n+ if workspace.dm_barrier_count.numel() < routed_rows + num_tokens * 16:\n+ raise ValueError(\n+ \"forced direct_micro backend exceeds the workspace barrier \"\n+ f\"capacity ({workspace.dm_barrier_count.numel()} slots < \"\n+ f\"{routed_rows} routed rows + {num_tokens * 16})\"\n+ )\n+ use_direct_micro = True\n+ else:\n+ use_direct_micro = False\n+ if use_direct_micro:\n+ compiled, grid_x, block_ok = _get_direct_micro_kernel(\n+ num_experts,\n+ num_tokens,\n+ k,\n+ n,\n+ top_k,\n+ topk_ids_dtype=flat_ids.dtype,\n+ fast_math=fast_math,\n+ share_input_across_experts=share_input_across_experts,\n+ share_expert_scales=share_expert_scales,\n+ activation=activation,\n+ swiglu_alpha=swiglu_alpha,\n+ swiglu_beta=swiglu_beta,\n+ swiglu_limit=swiglu_limit,\n+ device=a.device,\n+ )\n+ if not block_ok:\n+ if _FORCED_BACKEND == \"direct_micro\":\n+ raise RuntimeError(\"compiled direct micro MoE kernel cannot launch\")\n+ use_direct_micro = False\n+ if use_direct_micro:\n+ # The kernel takes multiplier-form scales only; invert reciprocal\n+ # inputs into the persistent workspace planes (zeros stay zero,\n+ # matching the MMA kernels).\n+ if input_scales_are_reciprocal:\n+ workspace.dm_input_gs.copy_(\n+ torch.where(input_gs != 0, 1.0 / input_gs, input_gs)\n+ )\n+ workspace.dm_down_input_scale.copy_(\n+ torch.where(\n+ down_input_scale != 0, 1.0 / down_input_scale, down_input_scale\n+ )\n+ )\n+ launch_gs = workspace.dm_input_gs\n+ launch_down = workspace.dm_down_input_scale\n+ else:\n+ launch_gs = input_gs\n+ launch_down = down_input_scale\n+ MoEDirectMicroKernel.launch(\n+ compiled,\n+ x=a,\n+ w1_fp4=weights.w1_storage,\n+ w1_blockscale=weights.w1_scale_storage,\n+ w1_alphas=weights.w1_alpha,\n+ a1_gscale=launch_gs,\n+ a2_gscale=launch_down,\n+ inter_fp32=workspace.dm_intermediate,\n+ w2_fp4=weights.w2_storage,\n+ w2_blockscale=weights.w2_scale_storage,\n+ w2_alphas=weights.w2_alpha,\n+ topk_ids=flat_ids,\n+ topk_weights=flat_weights,\n+ out=scatter_output,\n+ barrier_count=workspace.dm_barrier_count,\n+ barrier_epoch=workspace.dm_barrier_epoch,\n+ m=num_tokens,\n+ grid_x=grid_x,\n+ )\n+ return scatter_output\n+\n+ # Decide micro vs static\n+ micro_cutover = _MICRO_COMPACT_CUTOVER_PAIRS\n+ if top_k > 1:\n+ micro_cutover = _MICRO_COMPACT_CUTOVER_PAIRS_MULTI_TOPK\n+ use_micro = (\n+ activation_precision == \"fp4\"\n+ and num_tokens <= _MICRO_MAX_TOKENS\n+ and routed_rows <= micro_cutover\n+ )\n+ if _FORCED_BACKEND is not None:\n+ if _FORCED_BACKEND == \"micro\":\n+ # Forced mode raises on correctness violations, never falls back.\n+ if num_tokens > _MICRO_MAX_TOKENS:\n+ raise ValueError(\n+ f\"forced micro backend supports at most {_MICRO_MAX_TOKENS} \"\n+ f\"tokens (got {num_tokens})\"\n+ )\n+ if flat_ids.numel() > workspace.compact_topk_ids.numel():\n+ raise ValueError(\n+ \"forced micro backend exceeds the workspace compact-id \"\n+ f\"capacity ({workspace.compact_topk_ids.numel()} < \"\n+ f\"{flat_ids.numel()})\"\n+ )\n+ use_micro = True\n+ else:\n+ use_micro = False\n+\n+ sm_count = get_num_sm(torch.device(\"cuda\"))\n+ base_mac = min(get_max_active_clusters(1), sm_count)\n+ tuned_static_mac = _lookup_mac_ladder(_STATIC_MAC_LADDER, routed_rows)\n+ static_mac = min(tuned_static_mac or base_mac, base_mac)\n+ if activation_precision == \"fp4\" and not use_micro and routed_rows < 40:\n+ static_mac = min(static_mac, 64)\n \n if use_micro:\n assert flat_ids.numel() <= workspace.compact_topk_ids.numel(), (\n@@ -1193,6 +1505,11 @@\n mode = _normalize_quant_mode(quant_mode, activation_precision)\n if mode == \"w4a16\":\n return \"w4a16\"\n+ if _FORCED_BACKEND == \"dynamic\":\n+ return \"dynamic\"\n+ if _FORCED_BACKEND in (\"static\", \"micro\", \"direct_micro\"):\n+ # Both micro variants launch through the static workspace path.\n+ return \"static\"\n routed_rows = num_tokens * num_topk\n if routed_rows <= _get_static_compact_cutover_pairs(\"fp4\"):\n return \"static\"\n@@ -1228,20 +1545,16 @@\n routed_rows_capacity: int\n physical_tiles_capacity: int\n task_capacity: int\n+ # The M-tile the geometry above was sized for; launches must build the\n+ # kernel with the same tile.\n+ tile_m: int = _LEVEL_TILE_M\n expert_write_rows: torch.Tensor\n expert_tile_base: torch.Tensor\n pair_head: torch.Tensor\n- producers_done_count: torch.Tensor\n- all_work_published: torch.Tensor\n task_head: torch.Tensor\n task_tail: torch.Tensor\n- task_ready: torch.Tensor\n task_expert: torch.Tensor\n- task_m_tile: torch.Tensor\n- task_slice_begin: torch.Tensor\n- task_slice_count: torch.Tensor\n task_valid_rows: torch.Tensor\n- tile_write_count: torch.Tensor\n \n # Views\n packed_a_view: torch.Tensor | None = None\n@@ -1286,6 +1599,7 @@\n num_topk: int,\n device: torch.device,\n activation_precision: str = \"fp4\",\n+ activation: str = \"silu\",\n ) -> Sm120DynamicMoEWorkspace:\n \"\"\"Allocate workspace buffers for the SM120 dynamic MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n@@ -1294,7 +1608,7 @@\n \"allocate_sm120_dynamic_workspace only supports quant_mode='nvfp4'; \"\n \"use allocate_sm120_moe_workspace(..., quant_mode='w4a16') for W4A16.\"\n )\n- tile_m = _level_tile_m(activation_precision)\n+ tile_m = _select_dynamic_tile_m(routed_rows, state_E, activation)\n physical_tiles, _, max_tasks = _dynamic_task_geometry(\n state_E,\n n,\n@@ -1303,7 +1617,12 @@\n tile_n=_level_tile_n(activation_precision),\n )\n rows_padded = physical_tiles * tile_m\n+ # The kernel addresses activation scales in 128-row SF atoms regardless of\n+ # tile_m, so the scale plane must cover the last partial atom.\n+ scale_rows = _align_up(rows_padded, 128)\n cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n+ _check_memref_limit(\"dynamic packed_input\", rows_padded * (k // 2))\n+ _check_memref_limit(\"dynamic packed_input_scale\", scale_rows * cols_pad_k)\n packed_input = torch.empty(1, rows_padded, k // 2, dtype=torch.uint8, device=device)\n \n workspace = Sm120DynamicMoEWorkspace(\n@@ -1318,29 +1637,23 @@\n routed_rows_capacity=routed_rows,\n physical_tiles_capacity=physical_tiles,\n task_capacity=max_tasks,\n+ tile_m=tile_m,\n row_counts=torch.zeros(state_E, dtype=torch.int32, device=device),\n token_map=torch.zeros(rows_padded, dtype=torch.int32, device=device),\n token_weights=torch.zeros(rows_padded, dtype=torch.float32, device=device),\n packed_input=packed_input,\n packed_input_scale=torch.empty(\n- rows_padded, cols_pad_k, dtype=torch.uint8, device=device\n+ scale_rows, cols_pad_k, dtype=torch.uint8, device=device\n ),\n barrier_count=torch.zeros(1, dtype=torch.int32, device=device),\n barrier_epoch=torch.zeros(1, dtype=torch.int32, device=device),\n expert_write_rows=torch.zeros(state_E, dtype=torch.int32, device=device),\n expert_tile_base=torch.zeros(state_E + 1, dtype=torch.int32, device=device),\n pair_head=torch.zeros(1, dtype=torch.int32, device=device),\n- producers_done_count=torch.zeros(1, dtype=torch.int32, device=device),\n- all_work_published=torch.zeros(1, dtype=torch.int32, device=device),\n task_head=torch.zeros(1, dtype=torch.int32, device=device),\n task_tail=torch.zeros(1, dtype=torch.int32, device=device),\n- task_ready=torch.zeros(max_tasks, dtype=torch.int32, device=device),\n task_expert=torch.zeros(max_tasks, dtype=torch.int32, device=device),\n- task_m_tile=torch.zeros(max_tasks, dtype=torch.int32, device=device),\n- task_slice_begin=torch.zeros(max_tasks, dtype=torch.int32, device=device),\n- task_slice_count=torch.zeros(max_tasks, dtype=torch.int32, device=device),\n task_valid_rows=torch.zeros(max_tasks, dtype=torch.int32, device=device),\n- tile_write_count=torch.zeros(physical_tiles, dtype=torch.int32, device=device),\n )\n \n # Finalize views\n@@ -1392,17 +1705,10 @@\n barrier_count: cute.Tensor,\n barrier_epoch: cute.Tensor,\n pair_head: cute.Tensor,\n- producers_done_count: cute.Tensor,\n- all_work_published: cute.Tensor,\n task_head: cute.Tensor,\n task_tail: cute.Tensor,\n- task_ready_ptr: cute.Pointer,\n task_expert_ptr: cute.Pointer,\n- task_m_tile_ptr: cute.Pointer,\n- task_slice_begin_ptr: cute.Pointer,\n- task_slice_count_ptr: cute.Pointer,\n task_valid_rows_ptr: cute.Pointer,\n- tile_write_count_ptr: cute.Pointer,\n b_w13: cute.Tensor,\n sfb_w13_ptr: cute.Pointer,\n b_down: cute.Tensor,\n@@ -1421,7 +1727,6 @@\n max_rows: cutlass.Int32,\n rows_padded: cutlass.Int32,\n max_tasks: cutlass.Int32,\n- max_phys_tiles: cutlass.Int32,\n max_active_clusters: cutlass.Constexpr,\n stream,\n ):\n@@ -1452,9 +1757,12 @@\n (rows_padded * self._packed_storage_cols,), stride=(1,)\n ),\n )\n+ # Activation scales live in 128-row SF atoms; the plane is allocated\n+ # through the last partial atom even when rows_padded is not aligned.\n+ scale_rows = ((rows_padded + 127) // 128) * 128\n scale_storage = cute.make_tensor(\n scale_storage_ptr,\n- layout=cute.make_layout((rows_padded * self._cols_pad_k,), stride=(1,)),\n+ layout=cute.make_layout((scale_rows * self._cols_pad_k,), stride=(1,)),\n )\n token_map = cute.make_tensor(\n token_map_ptr, layout=cute.make_layout((rows_padded,), stride=(1,))\n@@ -1462,27 +1770,11 @@\n token_weights_t = cute.make_tensor(\n token_weights_ptr, layout=cute.make_layout((rows_padded,), stride=(1,))\n )\n- task_ready = cute.make_tensor(\n- task_ready_ptr, layout=cute.make_layout((max_tasks,), stride=(1,))\n- )\n task_expert = cute.make_tensor(\n task_expert_ptr, layout=cute.make_layout((max_tasks,), stride=(1,))\n )\n- task_m_tile = cute.make_tensor(\n- task_m_tile_ptr, layout=cute.make_layout((max_tasks,), stride=(1,))\n- )\n- task_slice_begin = cute.make_tensor(\n- task_slice_begin_ptr, layout=cute.make_layout((max_tasks,), stride=(1,))\n- )\n- task_slice_count = cute.make_tensor(\n- task_slice_count_ptr, layout=cute.make_layout((max_tasks,), stride=(1,))\n- )\n task_valid_rows = cute.make_tensor(\n task_valid_rows_ptr, layout=cute.make_layout((max_tasks,), stride=(1,))\n- )\n- tile_write_count = cute.make_tensor(\n- tile_write_count_ptr,\n- layout=cute.make_layout((max_phys_tiles,), stride=(1,)),\n )\n self._kernel(\n a_input,\n@@ -1495,17 +1787,10 @@\n barrier_count,\n barrier_epoch,\n pair_head,\n- producers_done_count,\n- all_work_published,\n task_head,\n task_tail,\n- task_ready,\n task_expert,\n- task_m_tile,\n- task_slice_begin,\n- task_slice_count,\n task_valid_rows,\n- tile_write_count,\n b_w13,\n sfb_w13_ptr,\n b_down,\n@@ -1545,6 +1830,7 @@\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n share_input_across_experts: bool = False,\n+ tile_m: int = _LEVEL_TILE_M,\n ):\n \"\"\"Compile (or retrieve cached) the SM120 dynamic MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n@@ -1557,11 +1843,12 @@\n )\n sf_vec_size = 16\n sm_count = get_num_sm(torch.device(\"cuda\"))\n- mac = min(get_max_active_clusters(1), sm_count)\n- mma_tiler_mn = (\n- _level_tile_m(activation_precision),\n- _level_tile_n(activation_precision),\n- )\n+ base_mac = min(get_max_active_clusters(1), sm_count)\n+ tuned_mac = _lookup_mac_ladder(_DYNAMIC_MAC_LADDER, m * num_topk)\n+ mac = min(tuned_mac or base_mac, base_mac)\n+ # tile_m comes from the workspace's shared selection so the kernel's task\n+ # and scale indexing matches the allocated scratch geometry.\n+ mma_tiler_mn = (tile_m, _level_tile_n(activation_precision))\n \n cache_key = (\n \"dynamic\",\n@@ -1648,12 +1935,6 @@\n pair_head_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n- producers_done_count_fake = cute.runtime.make_fake_compact_tensor(\n- cutlass.Int32, (1,), assumed_align=4\n- )\n- all_work_published_fake = cute.runtime.make_fake_compact_tensor(\n- cutlass.Int32, (1,), assumed_align=4\n- )\n task_head_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n@@ -1661,25 +1942,10 @@\n cutlass.Int32, (1,), assumed_align=4\n )\n \n- task_ready_fake = make_ptr(\n- cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4\n- )\n task_expert_fake = make_ptr(\n cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n- task_m_tile_fake = make_ptr(\n- cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4\n- )\n- task_slice_begin_fake = make_ptr(\n- cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4\n- )\n- task_slice_count_fake = make_ptr(\n- cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4\n- )\n task_valid_rows_fake = make_ptr(\n- cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4\n- )\n- tile_write_count_fake = make_ptr(\n cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n \n@@ -1736,17 +2002,10 @@\n barrier_count_fake,\n barrier_epoch_fake,\n pair_head_fake,\n- producers_done_count_fake,\n- all_work_published_fake,\n task_head_fake,\n task_tail_fake,\n- task_ready_fake,\n task_expert_fake,\n- task_m_tile_fake,\n- task_slice_begin_fake,\n- task_slice_count_fake,\n task_valid_rows_fake,\n- tile_write_count_fake,\n b_w13_fake,\n sfb_w13_fake,\n b_down_fake,\n@@ -1761,7 +2020,6 @@\n scatter_fake,\n token_map_fake,\n token_weights_fake,\n- 1,\n 1,\n 1,\n 1,\n@@ -1808,6 +2066,7 @@\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 dynamic launcher\"\n )\n+ _check_memref_limit(\"scatter_output\", scatter_output.numel())\n flat_ids = topk_ids.view(-1).to(torch.int32)\n flat_weights = topk_weights.view(-1).to(torch.float32)\n input_gs_is_shared = input_gs.numel() == 1\n@@ -1832,6 +2091,7 @@\n swiglu_limit=swiglu_limit,\n activation_precision=activation_precision,\n share_input_across_experts=input_gs_is_shared,\n+ tile_m=workspace.tile_m,\n )\n \n # Dynamic kernel: runtime-shaped args are DataPointer (pass data_ptr()),\n@@ -1847,17 +2107,10 @@\n workspace.barrier_count,\n workspace.barrier_epoch,\n workspace.pair_head,\n- workspace.producers_done_count,\n- workspace.all_work_published,\n workspace.task_head,\n workspace.task_tail,\n- workspace.task_ready.data_ptr(),\n workspace.task_expert.data_ptr(),\n- workspace.task_m_tile.data_ptr(),\n- workspace.task_slice_begin.data_ptr(),\n- workspace.task_slice_count.data_ptr(),\n workspace.task_valid_rows.data_ptr(),\n- workspace.tile_write_count.data_ptr(),\n weights.w13_fp4,\n weights._w13_sf_storage.data_ptr(),\n weights.down_fp4,\n@@ -1874,9 +2127,8 @@\n workspace.token_weights.data_ptr(),\n num_tokens,\n workspace.max_rows,\n- workspace.physical_tiles_capacity * _level_tile_m(activation_precision),\n+ workspace.physical_tiles_capacity * workspace.tile_m,\n workspace.task_capacity,\n- workspace.physical_tiles_capacity,\n )\n compiled(*runtime_args, current_cuda_stream())\n \n@@ -2281,10 +2533,25 @@\n Sm120W4A16MoEWorkspace,\n ]\n \n-# Keyed by (state_E, weight_E, k, n, top_k, device, backend).\n-# Stores the workspace with the largest max_rows seen for each key.\n-# Grows monotonically — never shrinks within a process.\n+# Stores the workspace with the largest capacity seen per key and never\n+# shrinks within a process. clear_sm120_moe_caches() releases everything.\n _WORKSPACE_CACHE: Dict[Tuple, _Sm120Workspace] = {}\n+\n+\n+def clear_sm120_moe_caches() -> None:\n+ \"\"\"Release every module-level SM12x MoE cache.\n+\n+ References held by callers are unaffected.\n+ \"\"\"\n+ _WORKSPACE_CACHE.clear()\n+ _WEIGHT_CACHE.clear()\n+ _W4A16_WEIGHT_CACHE.clear()\n+ _PADDED_WEIGHT_CACHE.clear()\n+ _STATIC_KERNEL_CACHE.clear()\n+ _MICRO_KERNEL_CACHE.clear()\n+ _DIRECT_MICRO_LAUNCH_CACHE.clear()\n+ _DIRECT_MICRO_KERNEL_CACHE.clear()\n+ _DYNAMIC_KERNEL_CACHE.clear()\n \n \n def allocate_sm120_moe_workspace(\n@@ -2343,6 +2610,7 @@\n num_topk=num_topk,\n device=device,\n activation_precision=activation_precision,\n+ activation=activation,\n )\n if backend == \"static\":\n return allocate_sm120_static_workspace(\n@@ -2382,6 +2650,13 @@\n \"\"\"\n quant_mode = _normalize_quant_mode(quant_mode, activation_precision)\n activation_precision = _activation_precision_from_quant_mode(quant_mode)\n+ # Key dynamic workspaces on the tile band of this call's routed_rows; a\n+ # larger cached workspace must not pin small calls to its 128 tile.\n+ tile_m = (\n+ _select_dynamic_tile_m(max(1, routed_rows), state_E, activation)\n+ if backend == \"dynamic\" and quant_mode != \"w4a16\"\n+ else None\n+ )\n cache_key = (\n state_E,\n weight_E,\n@@ -2392,12 +2667,17 @@\n backend,\n quant_mode,\n activation,\n+ tile_m,\n )\n cached = _WORKSPACE_CACHE.get(cache_key)\n \n if cached is not None:\n- if isinstance(cached, (Sm120DynamicMoEWorkspace, Sm120W4A16MoEWorkspace)):\n- if cached.routed_rows_capacity >= max(1, routed_rows): # type: ignore[union-attr]\n+ if isinstance(cached, Sm120DynamicMoEWorkspace):\n+ if cached.routed_rows_capacity >= max(1, routed_rows):\n+ assert tile_m is None or cached.tile_m == tile_m\n+ return cached\n+ elif isinstance(cached, Sm120W4A16MoEWorkspace):\n+ if cached.routed_rows_capacity >= max(1, routed_rows):\n return cached\n else:\n if cached.max_rows >= max(1, routed_rows):\n@@ -2680,6 +2960,8 @@\n \"num_local_experts == num_experts because dynamic expert \"\n \"buffers are indexed by global topk ids.\"\n )\n+ # A pre-allocated dynamic workspace keeps its stored tile_m even\n+ # for smaller calls; its geometry was sized for that tile.\n backend = \"dynamic\"\n else:\n backend = \"static\""},"lines_added":{"kind":"number","value":410,"string":"410"},"lines_removed":{"kind":"number","value":128,"string":"128"},"files_in_commit":{"kind":"number","value":8,"string":"8"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["RTX5080","SM121"],"string":"[\n \"RTX5080\",\n \"SM121\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":["1.06x","1.30x","1.40x","1.00x","1.00x","1.00x","1.10x","1.10x","1.09x","1.00x"],"string":"[\n \"1.06x\",\n \"1.30x\",\n \"1.40x\",\n \"1.00x\",\n \"1.00x\",\n \"1.00x\",\n \"1.10x\",\n \"1.10x\",\n \"1.09x\",\n \"1.00x\"\n]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cute_dsl kernel file from flashinfer (flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_dispatch.py).\n\nGoal: perf(moe): sync SM12x NVFP4 fused-MoE kernels to b12x HEAD\nTarget hardware: RTX5080, SM121\nTarget models: unspecified\n\nCurrent file:\n```python\n\"\"\"SM120/SM121 MoE dispatch layer — workspace, compilation, and launch.\n\nPorted from b12x's integration/tp_moe.py. Supports micro (tiny decode),\nstatic (decode), and dynamic (prefill) backends with token-count-based\nselection.\n\"\"\"\n\nfrom __future__ import annotations\n\nimport os\nimport weakref\nfrom dataclasses import dataclass\nfrom typing import Any, Dict, Optional, Tuple, Union\n\nimport cutlass\nimport cutlass.cute as cute\nimport torch\n\nfrom flashinfer.cute_dsl.utils import (\n convert_sf_from_mma_layout,\n convert_sf_to_mma_layout,\n current_cuda_stream,\n get_max_active_clusters,\n get_num_sm,\n make_ptr,\n)\nfrom .moe_activation import is_gated_activation\nfrom .moe_dynamic_kernel import MoEDynamicKernel\nfrom .moe_micro_kernel import MoEMicroKernel\nfrom .moe_static_kernel import MoEStaticKernel\nfrom .moe_w4a16_fp4_helpers import swizzle_block_scale\nfrom .moe_w4a16_host import (\n _W4A16_ALLOWED_ROUTED_SIZES,\n max_packed_route_slots,\n packed_gemm_scratch_elements,\n unswizzle_block_scale,\n validate_activation,\n)\nfrom .moe_w4a16_kernel import run_w4a16_moe\nfrom .moe_w4a16_prepare import (\n W4A16PackedWeights,\n _normalize_source_format,\n prepare_w4a16_packed_weights,\n)\n\n# ---------------------------------------------------------------------------\n# Constants\n# ---------------------------------------------------------------------------\n_NVFP4_BLOCK_SIZE = 16\n_LEVEL_TILE_M = 128\n_LEVEL_TILE_N = 128\n_DYNAMIC_SLICE_CHUNK = 1\nSF_VEC_SIZE = 16\n_FORCE_MOE_W4A16_ENV = \"FLASHINFER_B12X_FORCE_MOE_W4A16\"\n_MICRO_SHARE_INPUT_ACROSS_EXPERTS = (\n os.environ.get(\"FLASHINFER_B12X_MICRO_SHARE_INPUT\", \"1\") != \"0\"\n)\n\n# Micro kernel cutover thresholds (routed pairs)\n_MICRO_COMPACT_CUTOVER_PAIRS = 20\n_MICRO_COMPACT_CUTOVER_PAIRS_MULTI_TOPK = 40\n_STATIC_COMPACT_CUTOVER_PAIRS_DEFAULT = 640\n_STATIC_COMPACT_CUTOVER_PAIRS = _STATIC_COMPACT_CUTOVER_PAIRS_DEFAULT\n_STATIC_COMPACT_CUTOVER_PAIRS_CACHE: Dict[str, int] = {}\n\n# MAC (max active clusters) tuning ladders from b12x decode profiling.\n# Each entry is (max_routed_rows, optimal_mac).\n_MICRO_MAC_LADDER: Tuple[Tuple[int, int], ...] = (\n (2, 84),\n (4, 127),\n (8, 107),\n (10, 84),\n (16, 63),\n (20, 84),\n)\n_STATIC_MAC_LADDER: Tuple[Tuple[int, int], ...] = (\n (24, 148),\n (32, 169),\n (40, 132),\n (48, 149),\n (64, 134),\n (80, 175),\n (96, 171),\n (120, 125),\n (128, 130),\n (160, 171),\n (192, 166),\n (256, 141),\n (320, 158),\n (512, 175),\n (640, 188),\n)\n\n\ndef _lookup_mac_ladder(\n ladder: Tuple[Tuple[int, int], ...], routed_rows: int\n) -> int | None:\n \"\"\"Look up optimal MAC from a tuning ladder. Returns None if no match.\"\"\"\n for end_rows, mac in ladder:\n if routed_rows <= end_rows:\n return mac\n return None\n\n\ndef _align_up(value: int, alignment: int) -> int:\n return ((value + alignment - 1) // alignment) * alignment\n\n\ndef _first_env(*names: str) -> str | None:\n for name in names:\n value = os.environ.get(name)\n if value is not None:\n return value\n return None\n\n\ndef _normalize_activation_precision(activation_precision: str) -> str:\n \"\"\"Normalize public activation-precision names to internal modes.\"\"\"\n if os.environ.get(_FORCE_MOE_W4A16_ENV, \"0\") == \"1\":\n return \"bf16\"\n\n normalized = str(activation_precision).lower()\n aliases = {\n \"fp4\": \"fp4\",\n \"nvfp4\": \"fp4\",\n \"w4a4\": \"fp4\",\n \"bf16\": \"bf16\",\n \"w4a16\": \"bf16\",\n }\n try:\n return aliases[normalized]\n except KeyError as exc:\n raise ValueError(\n \"activation_precision must be 'fp4' or 'bf16' \"\n f\"(got {activation_precision!r}).\"\n ) from exc\n\n\ndef _normalize_quant_mode(\n quant_mode: str | None = None,\n activation_precision: str | None = None,\n) -> str:\n \"\"\"Normalize public quantization names to the dispatch mode.\"\"\"\n if os.environ.get(_FORCE_MOE_W4A16_ENV, \"0\") == \"1\":\n return \"w4a16\"\n if quant_mode is None:\n activation_precision = _normalize_activation_precision(\n activation_precision or \"fp4\"\n )\n return \"w4a16\" if activation_precision == \"bf16\" else \"nvfp4\"\n\n normalized = str(quant_mode).lower()\n aliases = {\n \"fp4\": \"nvfp4\",\n \"nvfp4\": \"nvfp4\",\n \"w4a4\": \"nvfp4\",\n \"bf16\": \"w4a16\",\n \"w4a16\": \"w4a16\",\n }\n try:\n return aliases[normalized]\n except KeyError as exc:\n raise ValueError(\n f\"quant_mode must be 'nvfp4'/'w4a4' or 'w4a16' (got {quant_mode!r}).\"\n ) from exc\n\n\ndef _activation_precision_from_quant_mode(quant_mode: str) -> str:\n return \"bf16\" if _normalize_quant_mode(quant_mode) == \"w4a16\" else \"fp4\"\n\n\ndef _normalize_source_format_for_quant_mode(source_format: str, quant_mode: str) -> str:\n normalized = _normalize_source_format(source_format)\n if quant_mode == \"nvfp4\" and normalized == \"compressed_tensors\":\n raise ValueError(\n \"source_format='compressed_tensors' requires quant_mode='w4a16'.\"\n )\n return normalized\n\n\ndef _is_w4a16(activation_precision: str) -> bool:\n return _normalize_activation_precision(activation_precision) == \"bf16\"\n\n\ndef _level_tile_m(activation_precision: str = \"fp4\") -> int:\n if _is_w4a16(activation_precision):\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 tile selector\"\n )\n return _LEVEL_TILE_M\n\n\ndef _level_tile_n(activation_precision: str = \"fp4\") -> int:\n if _is_w4a16(activation_precision):\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 tile selector\"\n )\n return _LEVEL_TILE_N\n\n\ndef _get_static_compact_cutover_pairs(activation_precision: str = \"fp4\") -> int:\n activation_precision = _normalize_activation_precision(activation_precision)\n cached = _STATIC_COMPACT_CUTOVER_PAIRS_CACHE.get(activation_precision)\n if cached is not None:\n return cached\n\n cutover_names: tuple[str, ...] = (\n \"FLASHINFER_B12X_STATIC_COMPACT_CUTOVER_PAIRS\",\n \"B12X_STATIC_COMPACT_CUTOVER_PAIRS\",\n \"B12X_DYNAMIC_STATIC_CUTOVER_PAIRS\",\n \"B12X_LEVEL10_STATIC_CUTOVER_PAIRS\",\n )\n cutover = _first_env(*cutover_names)\n if cutover is None:\n cached = _STATIC_COMPACT_CUTOVER_PAIRS_DEFAULT\n else:\n cached = max(0, int(cutover))\n _STATIC_COMPACT_CUTOVER_PAIRS_CACHE[activation_precision] = cached\n return cached\n\n\ndef _select_moe_mma_tiler_mn(routed_rows: int, n: int) -> Tuple[int, int]:\n \"\"\"Select optimal MoE tile shape based on routed rows and N dimension.\n\n Uses narrower 64x128 tiles when routed_rows <= 128 and default 128x128\n would leave SMs idle.\n \"\"\"\n sm_count = get_num_sm(torch.device(\"cuda\"))\n coarse_tile = (128, 128)\n coarse_tiles = ((routed_rows + coarse_tile[0] - 1) // coarse_tile[0]) * (\n (n + coarse_tile[1] - 1) // coarse_tile[1]\n )\n # Single-token decode often lands exactly on the \"half the machine\"\n # boundary. Keeping the coarse 128x128 tile there leaves the M dimension\n # badly underfilled, so take the narrow 64x128 tile inclusive of equality.\n if routed_rows <= 128 and coarse_tiles <= max(1, sm_count // 2):\n return (64, 128)\n return (128, 128)\n\n\ndef _as_grouped_scale_view(\n scale_storage: torch.Tensor,\n rows: int,\n cols: int,\n) -> torch.Tensor:\n \"\"\"Create 6D MMA-compatible scale factor view from swizzled storage.\"\"\"\n batch = scale_storage.shape[0]\n rows_padded = _align_up(rows, 128)\n cols_padded = _align_up(cols // SF_VEC_SIZE, 4)\n sf = scale_storage.view(torch.float8_e4m3fn)\n sf = sf.view(batch, rows_padded // 128, cols_padded // 4, 32, 4, 4)\n return sf.permute(3, 4, 1, 5, 2, 0)\n\n\n# ---------------------------------------------------------------------------\n# Workspace\n# ---------------------------------------------------------------------------\n@dataclass(kw_only=True)\nclass Sm120StaticMoEWorkspace:\n \"\"\"Scratch buffers for one SM120 static MoE launch.\"\"\"\n\n state_E: int\n weight_E: int\n max_rows: int\n k: int\n n: int\n num_topk: int\n device: torch.device\n activation_precision: str\n\n # Buffers\n row_counts: torch.Tensor # [state_E] int32\n token_map: torch.Tensor # [state_E, max_rows] int32\n token_weights: torch.Tensor # [state_E, max_rows] float32\n packed_input: torch.Tensor # [state_E, max_rows, k//2] uint8\n packed_input_scale: torch.Tensor # [state_E, rows_pad_k, cols_pad_k] uint8\n barrier_count: torch.Tensor # [1] int32\n barrier_epoch: torch.Tensor # [1] int32\n active_expert_count: torch.Tensor # [1] int32\n weight_expert_ids: torch.Tensor # [state_E] int32\n global_to_local_expert: torch.Tensor # [weight_E] int32\n compact_topk_ids: torch.Tensor # [state_E] int32, for micro kernel pre-pass\n\n # Views (set after allocation)\n packed_a_view: torch.Tensor | None = None\n sfa_ptr: object = None\n packed_a_flat: torch.Tensor | None = None\n scale_flat: torch.Tensor | None = None\n\n\ndef allocate_sm120_static_workspace(\n *,\n state_E: int,\n weight_E: int,\n max_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation_precision: str = \"fp4\",\n) -> Sm120StaticMoEWorkspace:\n \"\"\"Allocate workspace buffers for the SM120 static MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"allocate_sm120_static_workspace only supports quant_mode='nvfp4'; \"\n \"use allocate_sm120_moe_workspace(..., quant_mode='w4a16') for W4A16.\"\n )\n\n rows_pad_k = _align_up(max_rows, 128)\n cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n packed_input = torch.empty(\n state_E, max_rows, k // 2, dtype=torch.uint8, device=device\n )\n\n workspace = Sm120StaticMoEWorkspace(\n state_E=state_E,\n weight_E=weight_E,\n max_rows=max_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation_precision=activation_precision,\n row_counts=torch.zeros(state_E, dtype=torch.int32, device=device),\n token_map=torch.zeros(state_E, max_rows, dtype=torch.int32, device=device),\n token_weights=torch.zeros(\n state_E, max_rows, dtype=torch.float32, device=device\n ),\n packed_input=packed_input,\n packed_input_scale=torch.empty(\n state_E, rows_pad_k, cols_pad_k, dtype=torch.uint8, device=device\n ),\n barrier_count=torch.zeros(1, dtype=torch.int32, device=device),\n barrier_epoch=torch.zeros(1, dtype=torch.int32, device=device),\n active_expert_count=torch.zeros(1, dtype=torch.int32, device=device),\n weight_expert_ids=torch.arange(state_E, dtype=torch.int32, device=device),\n global_to_local_expert=torch.empty(weight_E, dtype=torch.int32, device=device),\n compact_topk_ids=torch.empty(\n max(state_E, max_rows), dtype=torch.int32, device=device\n ),\n )\n\n # Finalize views\n sf_dtype = cutlass.Float8E4M3FN\n workspace.packed_a_view = workspace.packed_input.permute(1, 2, 0).view(\n torch.float4_e2m1fn_x2\n )\n workspace.packed_a_flat = workspace.packed_input.view(-1)\n workspace.scale_flat = workspace.packed_input_scale.view(-1)\n workspace.sfa_ptr = make_ptr(\n sf_dtype,\n workspace.packed_input_scale.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n return workspace\n\n\n# ---------------------------------------------------------------------------\n# Weight views\n# ---------------------------------------------------------------------------\n@dataclass\nclass _WeightViews:\n w13_fp4: object = None\n down_fp4: object = None\n sfb_w13_ptr: object = None\n sfb_down_ptr: object = None\n w1_alpha: torch.Tensor | None = None\n w2_alpha: torch.Tensor | None = None\n w1_storage: torch.Tensor | None = None\n w1_scale_storage: torch.Tensor | None = None\n w2_storage: torch.Tensor | None = None\n w2_scale_storage: torch.Tensor | None = None\n _w13_sf_storage: torch.Tensor | None = None\n _down_sf_storage: torch.Tensor | None = None\n\n\ndef _register_cache_eviction(cache: Dict, key: Tuple, *source_tensors) -> None:\n \"\"\"Evict ``key`` when a source weight tensor is collected, so the cache\n follows the weights' lifetime instead of growing for the whole process.\n \"\"\"\n for tensor in source_tensors:\n if tensor is not None:\n weakref.finalize(tensor, cache.pop, key, None)\n\n\n_WEIGHT_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_weight_views(\n w1_fp4: torch.Tensor,\n w1_blockscale: torch.Tensor,\n w2_fp4: torch.Tensor,\n w2_blockscale: torch.Tensor,\n w1_alphas: torch.Tensor,\n w2_alphas: torch.Tensor,\n n: int,\n k: int,\n activation_precision: str = \"fp4\",\n) -> _WeightViews:\n \"\"\"Create permuted weight views for the static kernel.\n\n The kernel expects concatenated w13 data with shape [2*n, k//2, E]\n via a single TMA descriptor.\n \"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n tile_n = _level_tile_n(activation_precision)\n # The kernel splits w13 into gate/up halves by tile index. This only works\n # when the boundary between halves lands on a tile-aligned column.\n if n % tile_n != 0:\n raise ValueError(\n f\"intermediate_size ({n}) must be a multiple of {tile_n} \"\n f\"for the SM120 MoE kernel's gate/up tile split.\"\n )\n\n key = (\n activation_precision,\n w1_fp4.data_ptr(),\n w1_blockscale.data_ptr(),\n w1_alphas.data_ptr(),\n w2_fp4.data_ptr(),\n w2_blockscale.data_ptr(),\n w2_alphas.data_ptr(),\n )\n cached = _WEIGHT_CACHE.get(key)\n if cached is None:\n # Cache the fresh buffers (scale factors + fp32 alphas).\n w1_rows = w1_fp4.shape[1] # 2*n for gated, n for non-gated\n cached = (\n convert_sf_from_mma_layout(\n w1_blockscale, m=w1_rows, k=k, num_groups=w1_fp4.shape[0]\n ).contiguous(),\n convert_sf_from_mma_layout(\n w2_blockscale, m=k, k=n, num_groups=w2_fp4.shape[0]\n ).contiguous(),\n w1_alphas.contiguous().to(torch.float32),\n w2_alphas.contiguous().to(torch.float32),\n )\n _WEIGHT_CACHE[key] = cached\n _register_cache_eviction(\n _WEIGHT_CACHE,\n key,\n w1_fp4,\n w1_blockscale,\n w1_alphas,\n w2_fp4,\n w2_blockscale,\n w2_alphas,\n )\n w13_sf_contiguous, down_sf_contiguous, w1_alpha, w2_alpha = cached\n\n # Permute [E, w1_rows, k//2] -> [w1_rows, k//2, E] (view, no copy).\n sf_dtype = cutlass.Float8E4M3FN\n w13 = w1_fp4.permute(1, 2, 0)\n down = w2_fp4.permute(1, 2, 0)\n return _WeightViews(\n w13_fp4=w13.view(torch.float4_e2m1fn_x2),\n down_fp4=down.view(torch.float4_e2m1fn_x2),\n sfb_w13_ptr=make_ptr(\n sf_dtype,\n w13_sf_contiguous.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n ),\n sfb_down_ptr=make_ptr(\n sf_dtype,\n down_sf_contiguous.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n ),\n w1_alpha=w1_alpha,\n w2_alpha=w2_alpha,\n w1_storage=w1_fp4,\n w1_scale_storage=w13_sf_contiguous,\n w2_storage=w2_fp4,\n w2_scale_storage=down_sf_contiguous,\n _w13_sf_storage=w13_sf_contiguous,\n _down_sf_storage=down_sf_contiguous,\n )\n\n\n# ---------------------------------------------------------------------------\n# Kernel compilation cache\n# ---------------------------------------------------------------------------\n_STATIC_KERNEL_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_static_kernel(\n state_E: int,\n weight_E: int,\n m: int,\n k: int,\n n: int,\n num_topk: int,\n max_rows: int,\n *,\n topk_ids_dtype: torch.dtype = torch.int32,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n mac_override: int | None = None,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n):\n \"\"\"Compile (or retrieve cached) the SM120 static MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 static compiler\"\n )\n sf_vec_size = 16\n sm_count = get_num_sm(torch.device(\"cuda\"))\n mac = (\n mac_override\n if mac_override is not None\n else min(get_max_active_clusters(1), sm_count)\n )\n\n # Select tile size based on actual routed rows\n routed_rows = m * num_topk\n mma_tiler_mn = (128, 128)\n if activation_precision == \"fp4\" and num_topk > 1:\n mma_tiler_mn = _select_moe_mma_tiler_mn(routed_rows, n)\n\n cache_key = (\n \"static\",\n activation_precision,\n state_E,\n weight_E,\n m,\n k,\n n,\n num_topk,\n max_rows,\n mac,\n mma_tiler_mn,\n topk_ids_dtype,\n input_scales_are_reciprocal,\n fast_math,\n activation,\n swiglu_alpha,\n swiglu_beta,\n swiglu_limit,\n )\n cached = _STATIC_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n return cached\n\n ab_dtype = cutlass.Float4E2M1FN\n weight_dtype = cutlass.Float4E2M1FN\n sf_dtype = cutlass.Float8E4M3FN\n a_dtype = cutlass.BFloat16\n alpha_dtype = cutlass.Float32\n\n output_tile_count_n = max(1, (n + mma_tiler_mn[1] - 1) // mma_tiler_mn[1])\n kernel: Any = MoEStaticKernel(\n sf_vec_size=sf_vec_size,\n mma_tiler_mn=mma_tiler_mn,\n output_tile_count_n=output_tile_count_n,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n )\n\n is_gated = is_gated_activation(activation)\n w1_rows = (2 if is_gated else 1) * n # 2*n for gated, n for non-gated\n\n rows_pad_k = _align_up(max_rows, 128)\n cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n\n # Build fake tensors for compilation\n a_input_fake = cute.runtime.make_fake_compact_tensor(\n a_dtype,\n (m, k),\n stride_order=(1, 0),\n assumed_align=16,\n )\n topk_ids_cutlass_dtype = (\n cutlass.Int32 if topk_ids_dtype == torch.int32 else cutlass.Int64\n )\n topk_ids_align = 4 if topk_ids_dtype == torch.int32 else 8\n topk_ids_fake = cute.runtime.make_fake_compact_tensor(\n topk_ids_cutlass_dtype,\n (m * num_topk,),\n assumed_align=topk_ids_align,\n )\n topk_weights_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32,\n (m * num_topk,),\n assumed_align=4,\n )\n packed_a_fake = cute.runtime.make_fake_compact_tensor(\n ab_dtype,\n (max_rows, k, state_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfa_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n packed_a_storage_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (state_E * max_rows * (k // 2),),\n assumed_align=16,\n )\n scale_storage_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (state_E * rows_pad_k * cols_pad_k,),\n assumed_align=16,\n )\n barrier_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n barrier_epoch_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n b_w13_fake = cute.runtime.make_fake_compact_tensor(\n weight_dtype,\n (w1_rows, k, weight_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_w13_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n b_down_fake = cute.runtime.make_fake_compact_tensor(\n weight_dtype,\n (k, n, weight_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_down_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n row_counts_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E,),\n assumed_align=4,\n )\n active_expert_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n weight_expert_ids_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E,),\n assumed_align=4,\n )\n global_to_local_expert_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (weight_E,),\n assumed_align=4,\n )\n input_gs_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n down_alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n global_scale_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n scatter_fake = cute.runtime.make_fake_compact_tensor(\n a_dtype,\n (m, k),\n stride_order=(1, 0),\n assumed_align=16,\n )\n token_map_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E, max_rows),\n stride_order=(1, 0),\n assumed_align=4,\n )\n token_weights_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (state_E, max_rows),\n stride_order=(1, 0),\n assumed_align=16,\n )\n compiled = cute.compile(\n kernel,\n a_input_fake,\n topk_ids_fake,\n topk_weights_fake,\n packed_a_fake,\n sfa_fake,\n packed_a_storage_fake,\n scale_storage_fake,\n barrier_count_fake,\n barrier_epoch_fake,\n b_w13_fake,\n sfb_w13_fake,\n b_down_fake,\n sfb_down_fake,\n row_counts_fake,\n active_expert_count_fake,\n weight_expert_ids_fake,\n global_to_local_expert_fake,\n input_gs_fake,\n alpha_fake,\n down_alpha_fake,\n global_scale_fake,\n scatter_fake,\n token_map_fake,\n token_weights_fake,\n mac,\n current_cuda_stream(),\n options=\"--opt-level 2 --enable-tvm-ffi\",\n )\n\n result = (compiled, mac)\n _STATIC_KERNEL_CACHE[cache_key] = result\n return result\n\n\n_MICRO_KERNEL_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_micro_kernel(\n state_E: int,\n weight_E: int,\n m: int,\n k: int,\n n: int,\n num_topk: int,\n max_rows: int,\n *,\n topk_ids_dtype: torch.dtype = torch.int32,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n share_input_across_experts: bool = False,\n share_expert_scales: bool = False,\n single_token: bool = False,\n mac_override: int | None = None,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n):\n \"\"\"Compile (or retrieve cached) the SM120 micro MoE kernel.\"\"\"\n sf_vec_size = 16\n sm_count = get_num_sm(torch.device(\"cuda\"))\n mac = (\n mac_override\n if mac_override is not None\n else min(get_max_active_clusters(1), sm_count)\n )\n\n # Micro always selects tile from routed rows (not just for multi-topk)\n routed_rows = m * num_topk\n mma_tiler_mn = _select_moe_mma_tiler_mn(routed_rows, n)\n\n cache_key = (\n \"micro\",\n state_E,\n weight_E,\n m,\n k,\n n,\n num_topk,\n max_rows,\n mac,\n mma_tiler_mn,\n topk_ids_dtype,\n input_scales_are_reciprocal,\n fast_math,\n share_input_across_experts,\n share_expert_scales,\n single_token,\n activation,\n swiglu_alpha,\n swiglu_beta,\n swiglu_limit,\n )\n cached = _MICRO_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n return cached\n\n ab_dtype = cutlass.Float4E2M1FN\n sf_dtype = cutlass.Float8E4M3FN\n a_dtype = cutlass.BFloat16\n alpha_dtype = cutlass.Float32\n\n kernel = MoEMicroKernel(\n sf_vec_size=sf_vec_size,\n mma_tiler_mn=mma_tiler_mn,\n output_tile_count_n=max(1, (n + mma_tiler_mn[1] - 1) // mma_tiler_mn[1]),\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n share_input_across_experts=share_input_across_experts,\n share_expert_scales=share_expert_scales,\n single_token=single_token,\n )\n\n is_gated = is_gated_activation(activation)\n w1_rows = (2 if is_gated else 1) * n\n\n rows_pad_k = _align_up(max_rows, 128)\n cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n\n # Build fake tensors for compilation (identical to static kernel)\n a_input_fake = cute.runtime.make_fake_compact_tensor(\n a_dtype,\n (m, k),\n stride_order=(1, 0),\n assumed_align=16,\n )\n topk_ids_cutlass_dtype = (\n cutlass.Int32 if topk_ids_dtype == torch.int32 else cutlass.Int64\n )\n topk_ids_align = 4 if topk_ids_dtype == torch.int32 else 8\n topk_ids_fake = cute.runtime.make_fake_compact_tensor(\n topk_ids_cutlass_dtype,\n (m * num_topk,),\n assumed_align=topk_ids_align,\n )\n topk_weights_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32,\n (m * num_topk,),\n assumed_align=4,\n )\n packed_a_fake = cute.runtime.make_fake_compact_tensor(\n ab_dtype,\n (max_rows, k, state_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfa_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n packed_a_storage_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (state_E * max_rows * (k // 2),),\n assumed_align=16,\n )\n scale_storage_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8,\n (state_E * rows_pad_k * cols_pad_k,),\n assumed_align=16,\n )\n barrier_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n barrier_epoch_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n b_w13_fake = cute.runtime.make_fake_compact_tensor(\n ab_dtype,\n (w1_rows, k, weight_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_w13_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n b_down_fake = cute.runtime.make_fake_compact_tensor(\n ab_dtype,\n (k, n, weight_E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_down_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n row_counts_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E,),\n assumed_align=4,\n )\n active_expert_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (1,),\n assumed_align=4,\n )\n weight_expert_ids_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E,),\n assumed_align=4,\n )\n global_to_local_expert_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (weight_E,),\n assumed_align=4,\n )\n input_gs_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n down_alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n global_scale_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (weight_E,),\n assumed_align=16,\n )\n scatter_fake = cute.runtime.make_fake_compact_tensor(\n a_dtype,\n (m, k),\n stride_order=(1, 0),\n assumed_align=16,\n )\n token_map_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32,\n (state_E, max_rows),\n stride_order=(1, 0),\n assumed_align=4,\n )\n token_weights_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype,\n (state_E, max_rows),\n stride_order=(1, 0),\n assumed_align=16,\n )\n compiled = cute.compile(\n kernel,\n a_input_fake,\n topk_ids_fake,\n topk_weights_fake,\n packed_a_fake,\n sfa_fake,\n packed_a_storage_fake,\n scale_storage_fake,\n barrier_count_fake,\n barrier_epoch_fake,\n b_w13_fake,\n sfb_w13_fake,\n b_down_fake,\n sfb_down_fake,\n row_counts_fake,\n active_expert_count_fake,\n weight_expert_ids_fake,\n global_to_local_expert_fake,\n input_gs_fake,\n alpha_fake,\n down_alpha_fake,\n global_scale_fake,\n scatter_fake,\n token_map_fake,\n token_weights_fake,\n mac,\n current_cuda_stream(),\n options=\"--opt-level 2 --enable-tvm-ffi\",\n )\n\n result = (compiled, mac)\n _MICRO_KERNEL_CACHE[cache_key] = result\n return result\n\n\n# ---------------------------------------------------------------------------\n# Launch\n# ---------------------------------------------------------------------------\ndef _expand_to_experts(t: torch.Tensor, num_experts: int) -> torch.Tensor:\n \"\"\"Broadcast a scalar or [1] tensor to [num_experts], always fp32.\n\n Both branches must cast: the kernels are compiled against fp32 fake\n tensors for every per-expert scale.\n \"\"\"\n if t.numel() == 1:\n return t.to(torch.float32).expand(num_experts).contiguous()\n return t.contiguous().to(torch.float32)\n\n\ndef launch_sm120_static_moe(\n *,\n workspace: Sm120StaticMoEWorkspace,\n weights: _WeightViews,\n a: torch.Tensor,\n topk_ids: torch.Tensor,\n topk_weights: torch.Tensor,\n input_gs: torch.Tensor,\n down_input_scale: torch.Tensor,\n scatter_output: torch.Tensor,\n num_experts: int,\n num_tokens: int,\n k: int,\n n: int,\n top_k: int,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n) -> torch.Tensor:\n \"\"\"Launch the SM120 static or micro MoE kernel.\n\n Selects the micro kernel for tiny decode batches (routed_rows <= 20-40)\n and the static kernel otherwise. The micro path runs a Triton pre-pass\n to compact routing IDs before launching.\n \"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 static launcher\"\n )\n\n # Flatten routing tensors\n flat_ids = topk_ids.view(-1).to(torch.int32)\n flat_weights = topk_weights.view(-1).to(torch.float32)\n routed_rows = num_tokens * top_k\n\n # Capture whether input_gs was a single shared scalar BEFORE expansion:\n # the m=1 relu2 shared-input micro optimization only applies when every\n # expert sees the same FC1-input global scale.\n input_gs_is_shared = input_gs.numel() == 1\n down_input_scale_is_shared = down_input_scale.numel() == 1\n\n # Broadcast scalar scales to per-expert [E] tensors\n input_gs = _expand_to_experts(input_gs, num_experts)\n down_input_scale = _expand_to_experts(down_input_scale, num_experts)\n\n # Decide micro vs static\n micro_cutover = _MICRO_COMPACT_CUTOVER_PAIRS\n if top_k > 1:\n micro_cutover = _MICRO_COMPACT_CUTOVER_PAIRS_MULTI_TOPK\n use_micro = activation_precision == \"fp4\" and routed_rows <= micro_cutover\n\n sm_count = get_num_sm(torch.device(\"cuda\"))\n base_mac = min(get_max_active_clusters(1), sm_count)\n tuned_static_mac = _lookup_mac_ladder(_STATIC_MAC_LADDER, routed_rows)\n static_mac = min(tuned_static_mac or base_mac, base_mac)\n if activation_precision == \"fp4\" and not use_micro and routed_rows < 40:\n static_mac = min(static_mac, 64)\n\n # Shared-scale flags let compact W4A4 micro match the ReLU2 single-token\n # specialization.\n share_input_across_experts = (\n activation == \"relu2\"\n and num_tokens == 1\n and input_gs_is_shared\n and _MICRO_SHARE_INPUT_ACROSS_EXPERTS\n )\n share_expert_scales = (\n activation == \"relu2\" and input_gs_is_shared and down_input_scale_is_shared\n )\n\n if use_micro:\n assert flat_ids.numel() <= workspace.compact_topk_ids.numel(), (\n f\"compact_topk_ids buffer too small: \"\n f\"{workspace.compact_topk_ids.numel()} < {flat_ids.numel()}\"\n )\n # Single-token ReLU2 is non-gated, so the micro kernel can launch on\n # the routed expert ids directly. Gated SiLU still goes through the\n # compact id buffer so the kernel can map compact launch ids back to\n # the physical gate/up weight experts.\n if num_tokens == 1 and activation == \"relu2\":\n launch_ids = flat_ids\n elif num_tokens == 1:\n compact_ids = workspace.compact_topk_ids[: flat_ids.numel()]\n compact_ids.copy_(\n torch.arange(\n flat_ids.numel(),\n device=flat_ids.device,\n dtype=torch.int32,\n )\n )\n workspace.weight_expert_ids[: flat_ids.numel()].copy_(\n flat_ids.to(torch.int32)\n )\n workspace.active_expert_count.fill_(flat_ids.numel())\n launch_ids = compact_ids\n else:\n compact_ids = workspace.compact_topk_ids[: flat_ids.numel()]\n from .triton_compact import compact_topk_ids as _triton_compact_topk_ids\n\n _triton_compact_topk_ids(\n flat_ids,\n compact_ids,\n workspace.weight_expert_ids,\n workspace.active_expert_count,\n )\n launch_ids = compact_ids\n # Select micro MAC: min of tuned ladder, work tiles, and hardware limit.\n micro_work_tiles = max(1, routed_rows * max(1, (n + 128 - 1) // 128))\n tuned_mac = _lookup_mac_ladder(_MICRO_MAC_LADDER, routed_rows)\n micro_mac = min(tuned_mac or base_mac, micro_work_tiles, base_mac)\n compiled, mac = _get_micro_kernel(\n workspace.state_E,\n num_experts,\n num_tokens,\n k,\n n,\n top_k,\n workspace.max_rows,\n topk_ids_dtype=launch_ids.dtype,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n share_input_across_experts=share_input_across_experts,\n share_expert_scales=share_expert_scales,\n single_token=num_tokens == 1,\n mac_override=micro_mac,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n )\n else:\n compiled, mac = _get_static_kernel(\n workspace.state_E,\n num_experts,\n num_tokens,\n k,\n n,\n top_k,\n workspace.max_rows,\n topk_ids_dtype=torch.int32,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n mac_override=static_mac,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n activation_precision=activation_precision,\n )\n launch_ids = flat_ids\n\n # Pointer arguments must be passed as raw ints (data_ptr()) at runtime.\n runtime_args: Tuple[Any, ...] = (\n a,\n launch_ids,\n flat_weights,\n workspace.packed_a_view,\n workspace.packed_input_scale.data_ptr(),\n workspace.packed_a_flat,\n workspace.scale_flat,\n workspace.barrier_count,\n workspace.barrier_epoch,\n weights.w13_fp4,\n weights._w13_sf_storage.data_ptr(),\n weights.down_fp4,\n weights._down_sf_storage.data_ptr(),\n workspace.row_counts,\n workspace.active_expert_count,\n workspace.weight_expert_ids,\n workspace.global_to_local_expert,\n input_gs,\n weights.w1_alpha,\n weights.w2_alpha,\n down_input_scale,\n scatter_output,\n workspace.token_map,\n workspace.token_weights,\n )\n compiled(*runtime_args, current_cuda_stream())\n\n return scatter_output\n\n\n# ==========================================================================\n# Dynamic backend\n# ==========================================================================\n\n\ndef select_sm120_moe_backend(\n *,\n num_tokens: int,\n num_topk: int,\n activation_precision: str = \"fp4\",\n quant_mode: str | None = None,\n) -> str:\n \"\"\"Pick static or dynamic backend based on routed-pair count.\"\"\"\n mode = _normalize_quant_mode(quant_mode, activation_precision)\n if mode == \"w4a16\":\n return \"w4a16\"\n routed_rows = num_tokens * num_topk\n if routed_rows <= _get_static_compact_cutover_pairs(\"fp4\"):\n return \"static\"\n return \"dynamic\"\n\n\n# ---------------------------------------------------------------------------\n# Dynamic workspace\n# ---------------------------------------------------------------------------\n@dataclass(kw_only=True)\nclass Sm120DynamicMoEWorkspace:\n \"\"\"Scratch buffers for one SM120 dynamic MoE launch.\"\"\"\n\n state_E: int\n weight_E: int\n max_rows: int\n k: int\n n: int\n num_topk: int\n device: torch.device\n activation_precision: str\n\n # Core buffers\n row_counts: torch.Tensor\n token_map: torch.Tensor\n token_weights: torch.Tensor\n packed_input: torch.Tensor\n packed_input_scale: torch.Tensor\n barrier_count: torch.Tensor\n barrier_epoch: torch.Tensor\n\n # Dynamic-specific\n routed_rows_capacity: int\n physical_tiles_capacity: int\n task_capacity: int\n expert_write_rows: torch.Tensor\n expert_tile_base: torch.Tensor\n pair_head: torch.Tensor\n producers_done_count: torch.Tensor\n all_work_published: torch.Tensor\n task_head: torch.Tensor\n task_tail: torch.Tensor\n task_ready: torch.Tensor\n task_expert: torch.Tensor\n task_m_tile: torch.Tensor\n task_slice_begin: torch.Tensor\n task_slice_count: torch.Tensor\n task_valid_rows: torch.Tensor\n tile_write_count: torch.Tensor\n\n # Views\n packed_a_view: torch.Tensor | None = None\n sfa_ptr: object = None\n packed_a_flat: torch.Tensor | None = None\n scale_flat: torch.Tensor | None = None\n\n\ndef _dynamic_task_geometry(\n state_E: int,\n n: int,\n routed_rows: int,\n *,\n tile_m: int = _LEVEL_TILE_M,\n tile_n: int = _LEVEL_TILE_N,\n):\n \"\"\"Compute task queue dimensions from problem geometry.\n\n Each active expert can introduce at most one additional physical tile\n beyond the base count (due to per-expert tail padding). The task queue\n holds one entry per (m_tile, slice_group) pair — NOT multiplied by E.\n \"\"\"\n routed_rows = max(1, routed_rows)\n base_m_tiles = _align_up(routed_rows, tile_m) // tile_m\n active_expert_upper_bound = min(state_E, routed_rows)\n max_m_tiles = max(1, base_m_tiles + active_expert_upper_bound - 1)\n gate_tile_cnt = max(1, (n + tile_n - 1) // tile_n)\n slice_groups = max(\n 1, (gate_tile_cnt + _DYNAMIC_SLICE_CHUNK - 1) // _DYNAMIC_SLICE_CHUNK\n )\n max_tasks = max_m_tiles * slice_groups\n return max_m_tiles, gate_tile_cnt, max_tasks\n\n\ndef allocate_sm120_dynamic_workspace(\n *,\n state_E: int,\n weight_E: int,\n routed_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation_precision: str = \"fp4\",\n) -> Sm120DynamicMoEWorkspace:\n \"\"\"Allocate workspace buffers for the SM120 dynamic MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"allocate_sm120_dynamic_workspace only supports quant_mode='nvfp4'; \"\n \"use allocate_sm120_moe_workspace(..., quant_mode='w4a16') for W4A16.\"\n )\n tile_m = _level_tile_m(activation_precision)\n physical_tiles, _, max_tasks = _dynamic_task_geometry(\n state_E,\n n,\n routed_rows,\n tile_m=tile_m,\n tile_n=_level_tile_n(activation_precision),\n )\n rows_padded = physical_tiles * tile_m\n cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n packed_input = torch.empty(1, rows_padded, k // 2, dtype=torch.uint8, device=device)\n\n workspace = Sm120DynamicMoEWorkspace(\n state_E=state_E,\n weight_E=weight_E,\n max_rows=rows_padded,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation_precision=activation_precision,\n routed_rows_capacity=routed_rows,\n physical_tiles_capacity=physical_tiles,\n task_capacity=max_tasks,\n row_counts=torch.zeros(state_E, dtype=torch.int32, device=device),\n token_map=torch.zeros(rows_padded, dtype=torch.int32, device=device),\n token_weights=torch.zeros(rows_padded, dtype=torch.float32, device=device),\n packed_input=packed_input,\n packed_input_scale=torch.empty(\n rows_padded, cols_pad_k, dtype=torch.uint8, device=device\n ),\n barrier_count=torch.zeros(1, dtype=torch.int32, device=device),\n barrier_epoch=torch.zeros(1, dtype=torch.int32, device=device),\n expert_write_rows=torch.zeros(state_E, dtype=torch.int32, device=device),\n expert_tile_base=torch.zeros(state_E + 1, dtype=torch.int32, device=device),\n pair_head=torch.zeros(1, dtype=torch.int32, device=device),\n producers_done_count=torch.zeros(1, dtype=torch.int32, device=device),\n all_work_published=torch.zeros(1, dtype=torch.int32, device=device),\n task_head=torch.zeros(1, dtype=torch.int32, device=device),\n task_tail=torch.zeros(1, dtype=torch.int32, device=device),\n task_ready=torch.zeros(max_tasks, dtype=torch.int32, device=device),\n task_expert=torch.zeros(max_tasks, dtype=torch.int32, device=device),\n task_m_tile=torch.zeros(max_tasks, dtype=torch.int32, device=device),\n task_slice_begin=torch.zeros(max_tasks, dtype=torch.int32, device=device),\n task_slice_count=torch.zeros(max_tasks, dtype=torch.int32, device=device),\n task_valid_rows=torch.zeros(max_tasks, dtype=torch.int32, device=device),\n tile_write_count=torch.zeros(physical_tiles, dtype=torch.int32, device=device),\n )\n\n # Finalize views\n sf_dtype = cutlass.Float8E4M3FN\n workspace.packed_a_view = workspace.packed_input.permute(1, 2, 0).view(\n torch.float4_e2m1fn_x2\n )\n workspace.packed_a_flat = workspace.packed_input.view(-1)\n workspace.scale_flat = workspace.packed_input_scale.view(-1)\n workspace.sfa_ptr = make_ptr(\n sf_dtype,\n workspace.packed_input_scale.data_ptr(),\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n return workspace\n\n\n# ---------------------------------------------------------------------------\n# Dynamic kernel compilation\n# ---------------------------------------------------------------------------\n\n\nclass _DynamicMoELaunch:\n \"\"\"Thin JIT wrapper that makes num_tokens and max_rows runtime Int32.\"\"\"\n\n def __init__(self, kernel, k, num_topk, activation_precision: str = \"fp4\"):\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 dynamic launcher wrapper\"\n )\n self._kernel = kernel\n self._k = k\n self._packed_storage_cols = k // 2\n self._num_topk = num_topk\n self._cols_pad_k = _align_up(k // _NVFP4_BLOCK_SIZE, 4)\n\n @cute.jit\n def __call__(\n self,\n a_ptr: cute.Pointer,\n topk_ids_ptr: cute.Pointer,\n topk_weights_ptr: cute.Pointer,\n packed_a_ptr: cute.Pointer,\n sfa_ptr: cute.Pointer,\n packed_a_storage_ptr: cute.Pointer,\n scale_storage_ptr: cute.Pointer,\n barrier_count: cute.Tensor,\n barrier_epoch: cute.Tensor,\n pair_head: cute.Tensor,\n producers_done_count: cute.Tensor,\n all_work_published: cute.Tensor,\n task_head: cute.Tensor,\n task_tail: cute.Tensor,\n task_ready_ptr: cute.Pointer,\n task_expert_ptr: cute.Pointer,\n task_m_tile_ptr: cute.Pointer,\n task_slice_begin_ptr: cute.Pointer,\n task_slice_count_ptr: cute.Pointer,\n task_valid_rows_ptr: cute.Pointer,\n tile_write_count_ptr: cute.Pointer,\n b_w13: cute.Tensor,\n sfb_w13_ptr: cute.Pointer,\n b_down: cute.Tensor,\n sfb_down_ptr: cute.Pointer,\n row_counts: cute.Tensor,\n expert_write_rows: cute.Tensor,\n expert_tile_base: cute.Tensor,\n input_global_scale: cute.Tensor,\n alpha: cute.Tensor,\n down_alpha: cute.Tensor,\n global_scale: cute.Tensor,\n scatter_ptr: cute.Pointer,\n token_map_ptr: cute.Pointer,\n token_weights_ptr: cute.Pointer,\n num_tokens: cutlass.Int32,\n max_rows: cutlass.Int32,\n rows_padded: cutlass.Int32,\n max_tasks: cutlass.Int32,\n max_phys_tiles: cutlass.Int32,\n max_active_clusters: cutlass.Constexpr,\n stream,\n ):\n a_input = cute.make_tensor(\n a_ptr, layout=cute.make_layout((num_tokens, self._k), stride=(self._k, 1))\n )\n topk_ids = cute.make_tensor(\n topk_ids_ptr,\n layout=cute.make_layout((num_tokens * self._num_topk,), stride=(1,)),\n )\n topk_weights_t = cute.make_tensor(\n topk_weights_ptr,\n layout=cute.make_layout((num_tokens * self._num_topk,), stride=(1,)),\n )\n scatter_output = cute.make_tensor(\n scatter_ptr,\n layout=cute.make_layout((num_tokens, self._k), stride=(self._k, 1)),\n )\n packed_a = cute.make_tensor(\n packed_a_ptr,\n layout=cute.make_layout(\n (rows_padded, self._k, 1), stride=(self._k, 1, rows_padded * self._k)\n ),\n )\n packed_a_storage = cute.make_tensor(\n packed_a_storage_ptr,\n layout=cute.make_layout(\n (rows_padded * self._packed_storage_cols,), stride=(1,)\n ),\n )\n scale_storage = cute.make_tensor(\n scale_storage_ptr,\n layout=cute.make_layout((rows_padded * self._cols_pad_k,), stride=(1,)),\n )\n token_map = cute.make_tensor(\n token_map_ptr, layout=cute.make_layout((rows_padded,), stride=(1,))\n )\n token_weights_t = cute.make_tensor(\n token_weights_ptr, layout=cute.make_layout((rows_padded,), stride=(1,))\n )\n task_ready = cute.make_tensor(\n task_ready_ptr, layout=cute.make_layout((max_tasks,), stride=(1,))\n )\n task_expert = cute.make_tensor(\n task_expert_ptr, layout=cute.make_layout((max_tasks,), stride=(1,))\n )\n task_m_tile = cute.make_tensor(\n task_m_tile_ptr, layout=cute.make_layout((max_tasks,), stride=(1,))\n )\n task_slice_begin = cute.make_tensor(\n task_slice_begin_ptr, layout=cute.make_layout((max_tasks,), stride=(1,))\n )\n task_slice_count = cute.make_tensor(\n task_slice_count_ptr, layout=cute.make_layout((max_tasks,), stride=(1,))\n )\n task_valid_rows = cute.make_tensor(\n task_valid_rows_ptr, layout=cute.make_layout((max_tasks,), stride=(1,))\n )\n tile_write_count = cute.make_tensor(\n tile_write_count_ptr,\n layout=cute.make_layout((max_phys_tiles,), stride=(1,)),\n )\n self._kernel(\n a_input,\n topk_ids,\n topk_weights_t,\n packed_a,\n sfa_ptr,\n packed_a_storage,\n scale_storage,\n barrier_count,\n barrier_epoch,\n pair_head,\n producers_done_count,\n all_work_published,\n task_head,\n task_tail,\n task_ready,\n task_expert,\n task_m_tile,\n task_slice_begin,\n task_slice_count,\n task_valid_rows,\n tile_write_count,\n b_w13,\n sfb_w13_ptr,\n b_down,\n sfb_down_ptr,\n row_counts,\n expert_write_rows,\n expert_tile_base,\n input_global_scale,\n alpha,\n down_alpha,\n global_scale,\n scatter_output,\n token_map,\n token_weights_t,\n max_active_clusters=max_active_clusters,\n stream=stream,\n )\n\n\n_DYNAMIC_KERNEL_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _get_dynamic_kernel(\n E: int,\n m: int,\n k: int,\n n: int,\n num_topk: int,\n max_rows: int,\n *,\n topk_ids_dtype: torch.dtype = torch.int32,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n share_input_across_experts: bool = False,\n):\n \"\"\"Compile (or retrieve cached) the SM120 dynamic MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 dynamic compiler\"\n )\n share_input_across_experts = bool(\n share_input_across_experts and activation_precision == \"fp4\"\n )\n sf_vec_size = 16\n sm_count = get_num_sm(torch.device(\"cuda\"))\n mac = min(get_max_active_clusters(1), sm_count)\n mma_tiler_mn = (\n _level_tile_m(activation_precision),\n _level_tile_n(activation_precision),\n )\n\n cache_key = (\n \"dynamic\",\n activation_precision,\n E,\n k,\n n,\n num_topk,\n mac,\n mma_tiler_mn,\n topk_ids_dtype,\n input_scales_are_reciprocal,\n fast_math,\n activation,\n swiglu_alpha,\n swiglu_beta,\n swiglu_limit,\n share_input_across_experts,\n )\n cached = _DYNAMIC_KERNEL_CACHE.get(cache_key)\n if cached is not None:\n return cached\n\n is_gated = is_gated_activation(activation)\n w1_rows = (2 if is_gated else 1) * n\n\n scratch_dtype = cutlass.Float4E2M1FN\n weight_dtype = cutlass.Float4E2M1FN\n sf_dtype = cutlass.Float8E4M3FN\n a_dtype = cutlass.BFloat16\n alpha_dtype = cutlass.Float32\n\n kernel: Any = MoEDynamicKernel(\n sf_vec_size=sf_vec_size,\n mma_tiler_mn=mma_tiler_mn,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n share_input_across_experts=share_input_across_experts,\n )\n launch = _DynamicMoELaunch(\n kernel,\n k=k,\n num_topk=num_topk,\n activation_precision=activation_precision,\n )\n\n topk_ids_cutlass_dtype = (\n cutlass.Int32 if topk_ids_dtype == torch.int32 else cutlass.Int64\n )\n topk_ids_align = 4 if topk_ids_dtype == torch.int32 else 8\n\n # Runtime-shaped tensors passed as pointers\n a_input_fake = make_ptr(a_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n topk_ids_fake = make_ptr(\n topk_ids_cutlass_dtype,\n topk_ids_align,\n cute.AddressSpace.gmem,\n assumed_align=topk_ids_align,\n )\n topk_weights_fake = make_ptr(\n cutlass.Float32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n packed_a_fake = make_ptr(\n scratch_dtype, 16, cute.AddressSpace.gmem, assumed_align=16\n )\n sfa_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n packed_a_storage_fake = make_ptr(\n cutlass.Uint8, 16, cute.AddressSpace.gmem, assumed_align=16\n )\n scale_storage_fake = make_ptr(\n cutlass.Uint8, 16, cute.AddressSpace.gmem, assumed_align=16\n )\n\n barrier_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n barrier_epoch_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n pair_head_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n producers_done_count_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n all_work_published_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n task_head_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n task_tail_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (1,), assumed_align=4\n )\n\n task_ready_fake = make_ptr(\n cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n task_expert_fake = make_ptr(\n cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n task_m_tile_fake = make_ptr(\n cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n task_slice_begin_fake = make_ptr(\n cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n task_slice_count_fake = make_ptr(\n cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n task_valid_rows_fake = make_ptr(\n cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n tile_write_count_fake = make_ptr(\n cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4\n )\n\n b_w13_fake = cute.runtime.make_fake_compact_tensor(\n weight_dtype,\n (w1_rows, k, E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_w13_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n b_down_fake = cute.runtime.make_fake_compact_tensor(\n weight_dtype,\n (k, n, E),\n stride_order=(1, 0, 2),\n assumed_align=16,\n )\n sfb_down_fake = make_ptr(sf_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n row_counts_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (E,), assumed_align=4\n )\n expert_write_rows_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (E,), assumed_align=4\n )\n expert_tile_base_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Int32, (E + 1,), assumed_align=4\n )\n input_gs_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype, (E,), assumed_align=16\n )\n alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype, (E,), assumed_align=16\n )\n down_alpha_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype, (E,), assumed_align=16\n )\n global_scale_fake = cute.runtime.make_fake_compact_tensor(\n alpha_dtype, (E,), assumed_align=16\n )\n scatter_fake = make_ptr(a_dtype, 16, cute.AddressSpace.gmem, assumed_align=16)\n token_map_fake = make_ptr(cutlass.Int32, 4, cute.AddressSpace.gmem, assumed_align=4)\n token_weights_fake = make_ptr(\n alpha_dtype, 16, cute.AddressSpace.gmem, assumed_align=16\n )\n\n compiled = cute.compile(\n launch,\n a_input_fake,\n topk_ids_fake,\n topk_weights_fake,\n packed_a_fake,\n sfa_fake,\n packed_a_storage_fake,\n scale_storage_fake,\n barrier_count_fake,\n barrier_epoch_fake,\n pair_head_fake,\n producers_done_count_fake,\n all_work_published_fake,\n task_head_fake,\n task_tail_fake,\n task_ready_fake,\n task_expert_fake,\n task_m_tile_fake,\n task_slice_begin_fake,\n task_slice_count_fake,\n task_valid_rows_fake,\n tile_write_count_fake,\n b_w13_fake,\n sfb_w13_fake,\n b_down_fake,\n sfb_down_fake,\n row_counts_fake,\n expert_write_rows_fake,\n expert_tile_base_fake,\n input_gs_fake,\n alpha_fake,\n down_alpha_fake,\n global_scale_fake,\n scatter_fake,\n token_map_fake,\n token_weights_fake,\n 1,\n 1,\n 1,\n 1,\n 1, # runtime Int32 placeholders\n mac,\n current_cuda_stream(),\n options=\"--opt-level 2 --enable-tvm-ffi\",\n )\n\n result = (compiled, mac)\n _DYNAMIC_KERNEL_CACHE[cache_key] = result\n return result\n\n\n# ---------------------------------------------------------------------------\n# Dynamic launch\n# ---------------------------------------------------------------------------\ndef launch_sm120_dynamic_moe(\n *,\n workspace: Sm120DynamicMoEWorkspace,\n weights: _WeightViews,\n a: torch.Tensor,\n topk_ids: torch.Tensor,\n topk_weights: torch.Tensor,\n input_gs: torch.Tensor,\n down_input_scale: torch.Tensor,\n scatter_output: torch.Tensor,\n num_experts: int,\n num_tokens: int,\n k: int,\n n: int,\n top_k: int,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n) -> torch.Tensor:\n \"\"\"Launch the SM120 dynamic MoE kernel.\"\"\"\n activation_precision = _normalize_activation_precision(activation_precision)\n if activation_precision == \"bf16\":\n raise ValueError(\n \"internal routing error: quant_mode='w4a16' reached the NVFP4 dynamic launcher\"\n )\n flat_ids = topk_ids.view(-1).to(torch.int32)\n flat_weights = topk_weights.view(-1).to(torch.float32)\n input_gs_is_shared = input_gs.numel() == 1\n\n # Broadcast scalar scales to per-expert [E] tensors\n input_gs = _expand_to_experts(input_gs, num_experts)\n down_input_scale = _expand_to_experts(down_input_scale, num_experts)\n\n compiled, mac = _get_dynamic_kernel(\n num_experts,\n num_tokens,\n k,\n n,\n top_k,\n workspace.max_rows,\n topk_ids_dtype=torch.int32,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n activation_precision=activation_precision,\n share_input_across_experts=input_gs_is_shared,\n )\n\n # Dynamic kernel: runtime-shaped args are DataPointer (pass data_ptr()),\n # fixed-shape args are Tensor (pass torch tensor directly).\n runtime_args: Tuple[Any, ...] = (\n a.data_ptr(),\n flat_ids.data_ptr(),\n flat_weights.data_ptr(),\n workspace.packed_a_view.data_ptr(),\n workspace.packed_input_scale.data_ptr(),\n workspace.packed_a_flat.data_ptr(),\n workspace.scale_flat.data_ptr(),\n workspace.barrier_count,\n workspace.barrier_epoch,\n workspace.pair_head,\n workspace.producers_done_count,\n workspace.all_work_published,\n workspace.task_head,\n workspace.task_tail,\n workspace.task_ready.data_ptr(),\n workspace.task_expert.data_ptr(),\n workspace.task_m_tile.data_ptr(),\n workspace.task_slice_begin.data_ptr(),\n workspace.task_slice_count.data_ptr(),\n workspace.task_valid_rows.data_ptr(),\n workspace.tile_write_count.data_ptr(),\n weights.w13_fp4,\n weights._w13_sf_storage.data_ptr(),\n weights.down_fp4,\n weights._down_sf_storage.data_ptr(),\n workspace.row_counts,\n workspace.expert_write_rows,\n workspace.expert_tile_base,\n input_gs,\n weights.w1_alpha,\n weights.w2_alpha,\n down_input_scale,\n scatter_output.data_ptr(),\n workspace.token_map.data_ptr(),\n workspace.token_weights.data_ptr(),\n num_tokens,\n workspace.max_rows,\n workspace.physical_tiles_capacity * _level_tile_m(activation_precision),\n workspace.task_capacity,\n workspace.physical_tiles_capacity,\n )\n compiled(*runtime_args, current_cuda_stream())\n\n return scatter_output\n\n\n# ==========================================================================\n# W4A16 route-packing implementation\n# ==========================================================================\n@dataclass(kw_only=True)\nclass Sm120W4A16MoEWorkspace:\n \"\"\"Scratch buffers for the SM120 W4A16 MoE path.\"\"\"\n\n state_E: int\n weight_E: int\n max_rows: int\n k: int\n n: int\n num_topk: int\n device: torch.device\n activation: str\n activation_precision: str\n quant_mode: str\n routed_rows_capacity: int\n route_num_experts: int\n\n intermediate_cache13: torch.Tensor\n intermediate_cache2: torch.Tensor\n fc1_c_tmp: torch.Tensor\n fc2_c_tmp: torch.Tensor\n packed_route_indices: torch.Tensor\n block_expert_ids: torch.Tensor\n packed_route_count: torch.Tensor\n expert_offsets: torch.Tensor\n expert_map: torch.Tensor | None = None\n\n\ndef _is_cuda_graph_capturing() -> bool:\n try:\n return bool(torch.cuda.is_current_stream_capturing())\n except Exception:\n return False\n\n\ndef _canonical_cuda_device(device: torch.device) -> torch.device:\n device = torch.device(device)\n if device.type == \"cuda\" and device.index is None:\n return torch.device(\"cuda\", torch.cuda.current_device())\n return device\n\n\ndef _w4a16_workspace_geometry(\n *,\n routed_rows: int,\n route_num_experts: int,\n k: int,\n n: int,\n is_gated: bool,\n device: torch.device,\n) -> tuple[int, int, int, int, int]:\n route_slots = 1\n route_blocks = 1\n fc1_c_tmp_elements = 1\n fc2_c_tmp_elements = 1\n fc1_cols = (2 if is_gated else 1) * int(n)\n sms = get_num_sm(device)\n for block_size in _W4A16_ALLOWED_ROUTED_SIZES:\n slots = max_packed_route_slots(\n int(routed_rows),\n int(block_size),\n int(route_num_experts),\n )\n blocks = (slots + int(block_size) - 1) // int(block_size)\n route_slots = max(route_slots, slots)\n route_blocks = max(route_blocks, blocks)\n fc1_c_tmp_elements = max(\n fc1_c_tmp_elements,\n packed_gemm_scratch_elements(\n size_n=fc1_cols,\n route_slots=slots,\n moe_block_size=int(block_size),\n sms=sms,\n ),\n )\n fc2_c_tmp_elements = max(\n fc2_c_tmp_elements,\n packed_gemm_scratch_elements(\n size_n=int(k),\n route_slots=slots,\n moe_block_size=int(block_size),\n sms=sms,\n ),\n )\n return (\n route_slots,\n route_blocks,\n fc1_c_tmp_elements,\n fc2_c_tmp_elements,\n fc1_cols,\n )\n\n\ndef _make_w4a16_expert_map(\n *,\n state_E: int,\n weight_E: int,\n device: torch.device,\n) -> torch.Tensor | None:\n if int(state_E) == int(weight_E):\n return None\n if int(state_E) > int(weight_E):\n raise ValueError(\"num_local_experts cannot exceed num_experts\")\n expert_map = torch.empty((int(weight_E),), dtype=torch.int32, device=device)\n expert_map.fill_(-1)\n expert_map[: int(state_E)].copy_(\n torch.arange(int(state_E), dtype=torch.int32, device=device)\n )\n return expert_map\n\n\ndef _allocate_sm120_w4a16_workspace(\n *,\n state_E: int,\n weight_E: int,\n routed_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation: str = \"silu\",\n) -> Sm120W4A16MoEWorkspace:\n is_gated = validate_activation(activation)\n routed_rows = max(1, int(routed_rows))\n route_num_experts = int(weight_E) if int(state_E) != int(weight_E) else int(state_E)\n (\n route_slots,\n route_blocks,\n fc1_c_tmp_elements,\n fc2_c_tmp_elements,\n fc1_cols,\n ) = _w4a16_workspace_geometry(\n routed_rows=routed_rows,\n route_num_experts=route_num_experts,\n k=k,\n n=n,\n is_gated=is_gated,\n device=device,\n )\n return Sm120W4A16MoEWorkspace(\n state_E=int(state_E),\n weight_E=int(weight_E),\n max_rows=routed_rows,\n k=int(k),\n n=int(n),\n num_topk=int(num_topk),\n device=device,\n activation=activation,\n activation_precision=\"bf16\",\n quant_mode=\"w4a16\",\n routed_rows_capacity=routed_rows,\n route_num_experts=route_num_experts,\n intermediate_cache13=torch.empty(\n (routed_rows * max(fc1_cols, int(k)),),\n dtype=torch.bfloat16,\n device=device,\n ),\n intermediate_cache2=torch.empty(\n (routed_rows, int(n)),\n dtype=torch.bfloat16,\n device=device,\n ),\n fc1_c_tmp=torch.empty(\n (fc1_c_tmp_elements,),\n dtype=torch.float32,\n device=device,\n ),\n fc2_c_tmp=torch.empty(\n (fc2_c_tmp_elements,),\n dtype=torch.float32,\n device=device,\n ),\n packed_route_indices=torch.empty(\n (route_slots,),\n dtype=torch.int32,\n device=device,\n ),\n block_expert_ids=torch.empty(\n (route_blocks,),\n dtype=torch.int32,\n device=device,\n ),\n packed_route_count=torch.empty((1,), dtype=torch.int32, device=device),\n expert_offsets=torch.empty(\n (route_num_experts + 1,),\n dtype=torch.int32,\n device=device,\n ),\n expert_map=_make_w4a16_expert_map(\n state_E=state_E,\n weight_E=weight_E,\n device=device,\n ),\n )\n\n\n_W4A16_WEIGHT_CACHE: Dict[Tuple, W4A16PackedWeights] = {}\n\n\ndef _get_w4a16_packed_weights(\n *,\n w1_weight: torch.Tensor,\n w1_weight_sf: torch.Tensor,\n w1_alpha: torch.Tensor,\n w2_weight: torch.Tensor,\n w2_weight_sf: torch.Tensor,\n w2_alpha: torch.Tensor,\n activation: str,\n params_dtype: torch.dtype,\n source_format: str = \"modelopt\",\n) -> W4A16PackedWeights:\n key = (\n activation,\n params_dtype,\n source_format,\n tuple(w1_weight.shape),\n tuple(w1_weight_sf.shape),\n tuple(w1_alpha.shape),\n tuple(w2_weight.shape),\n tuple(w2_weight_sf.shape),\n tuple(w2_alpha.shape),\n w1_weight.data_ptr(),\n w1_weight_sf.data_ptr(),\n w1_alpha.data_ptr(),\n w2_weight.data_ptr(),\n w2_weight_sf.data_ptr(),\n w2_alpha.data_ptr(),\n )\n cached = _W4A16_WEIGHT_CACHE.get(key)\n if cached is not None:\n return cached\n if _is_cuda_graph_capturing():\n raise RuntimeError(\n \"W4A16 packed weights are not initialized for CUDA graph capture; \"\n \"run once before capture so the prepared weights are cached.\"\n )\n prepared = prepare_w4a16_packed_weights(\n w1_weight,\n w1_weight_sf,\n w1_alpha,\n w2_weight,\n w2_weight_sf,\n w2_alpha,\n activation=activation,\n params_dtype=params_dtype,\n source_format=source_format,\n )\n _W4A16_WEIGHT_CACHE[key] = prepared\n _register_cache_eviction(\n _W4A16_WEIGHT_CACHE,\n key,\n w1_weight,\n w1_weight_sf,\n w1_alpha,\n w2_weight,\n w2_weight_sf,\n w2_alpha,\n )\n return prepared\n\n\ndef _validate_w4a16_workspace(\n workspace: Sm120W4A16MoEWorkspace,\n *,\n state_E: int,\n weight_E: int,\n routed_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation: str,\n) -> None:\n validate_activation(activation)\n if workspace.state_E != int(state_E) or workspace.weight_E != int(weight_E):\n raise ValueError(\"pre-allocated W4A16 workspace expert geometry mismatch\")\n if workspace.k != int(k) or workspace.n != int(n):\n raise ValueError(\"pre-allocated W4A16 workspace hidden geometry mismatch\")\n if workspace.num_topk != int(num_topk):\n raise ValueError(\"pre-allocated W4A16 workspace top-k mismatch\")\n if getattr(workspace, \"activation\", None) != activation:\n raise ValueError(\"pre-allocated W4A16 workspace activation mismatch\")\n if _canonical_cuda_device(workspace.device) != _canonical_cuda_device(device):\n raise ValueError(\n f\"pre-allocated W4A16 workspace is on {workspace.device}, expected {device}\"\n )\n if workspace.routed_rows_capacity < max(1, int(routed_rows)):\n raise ValueError(\n \"pre-allocated W4A16 workspace is too small for the requested \"\n f\"routed rows ({workspace.routed_rows_capacity} < {routed_rows})\"\n )\n\n\ndef _launch_sm120_w4a16_moe(\n *,\n a: torch.Tensor,\n topk_ids: torch.Tensor,\n topk_weights: torch.Tensor,\n w1_weight: torch.Tensor,\n w1_weight_sf: torch.Tensor,\n w1_alpha: torch.Tensor,\n w2_weight: torch.Tensor,\n w2_weight_sf: torch.Tensor,\n w2_alpha: torch.Tensor,\n num_experts: int,\n top_k: int,\n num_local_experts: int,\n scatter_output: torch.Tensor,\n fast_math: bool = True,\n activation: str = \"silu\",\n source_format: str = \"modelopt\",\n _workspace=None,\n _prepared_weights=None,\n) -> torch.Tensor:\n prepared = (\n _prepared_weights\n if isinstance(_prepared_weights, W4A16PackedWeights)\n else _get_w4a16_packed_weights(\n w1_weight=w1_weight,\n w1_weight_sf=w1_weight_sf,\n w1_alpha=w1_alpha,\n w2_weight=w2_weight,\n w2_weight_sf=w2_weight_sf,\n w2_alpha=w2_alpha,\n activation=activation,\n params_dtype=a.dtype,\n source_format=source_format,\n )\n )\n if int(prepared.num_experts) != int(num_local_experts):\n raise ValueError(\"num_local_experts must match w1_weight.shape[0] for W4A16.\")\n num_tokens = int(topk_ids.size(0))\n routed_rows = num_tokens * int(top_k)\n k = int(a.size(1))\n n = int(prepared.intermediate_size)\n\n if _workspace is None:\n workspace = _get_cached_workspace(\n backend=\"w4a16\",\n state_E=num_local_experts,\n weight_E=num_experts,\n routed_rows=routed_rows,\n k=k,\n n=n,\n num_topk=top_k,\n device=a.device,\n quant_mode=\"w4a16\",\n activation=activation,\n )\n else:\n workspace = _workspace\n if not isinstance(workspace, Sm120W4A16MoEWorkspace):\n raise TypeError(\"expected a W4A16 workspace for quant_mode='w4a16'\")\n _validate_w4a16_workspace(\n workspace,\n state_E=num_local_experts,\n weight_E=num_experts,\n routed_rows=routed_rows,\n k=k,\n n=n,\n num_topk=top_k,\n device=a.device,\n activation=activation,\n )\n\n return run_w4a16_moe(\n a,\n prepared,\n topk_weights,\n topk_ids,\n activation=activation,\n intermediate_cache13=workspace.intermediate_cache13,\n intermediate_cache2=workspace.intermediate_cache2,\n output=scatter_output,\n fc1_c_tmp=workspace.fc1_c_tmp,\n fc2_c_tmp=workspace.fc2_c_tmp,\n packed_route_indices=workspace.packed_route_indices,\n block_expert_ids=workspace.block_expert_ids,\n packed_route_count=workspace.packed_route_count,\n expert_offsets=workspace.expert_offsets,\n expert_map=workspace.expert_map,\n fast_math=fast_math,\n )\n\n\n# ==========================================================================\n# Workspace cache (for functional API path)\n# ==========================================================================\n\n_Sm120Workspace = Union[\n Sm120StaticMoEWorkspace,\n Sm120DynamicMoEWorkspace,\n Sm120W4A16MoEWorkspace,\n]\n\n# Keyed by (state_E, weight_E, k, n, top_k, device, backend).\n# Stores the workspace with the largest max_rows seen for each key.\n# Grows monotonically — never shrinks within a process.\n_WORKSPACE_CACHE: Dict[Tuple, _Sm120Workspace] = {}\n\n\ndef allocate_sm120_moe_workspace(\n *,\n state_E: int,\n weight_E: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n max_rows: int | None = None,\n routed_rows: int | None = None,\n quant_mode: str | None = None,\n activation_precision: str | None = None,\n backend: str | None = None,\n activation: str = \"silu\",\n) -> _Sm120Workspace:\n \"\"\"Allocate the right SM120 MoE workspace from a quantization mode.\"\"\"\n mode = _normalize_quant_mode(quant_mode, activation_precision)\n capacity_rows = routed_rows if routed_rows is not None else max_rows\n if capacity_rows is None:\n raise ValueError(\"routed_rows or max_rows is required\")\n capacity_rows = max(1, int(capacity_rows))\n device = torch.device(device)\n\n if mode == \"w4a16\":\n if backend not in (None, \"w4a16\"):\n raise ValueError(\"quant_mode='w4a16' does not use static/dynamic backend\")\n return _allocate_sm120_w4a16_workspace(\n state_E=state_E,\n weight_E=weight_E,\n routed_rows=capacity_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation=activation,\n )\n\n activation_precision = \"fp4\"\n if backend is None:\n backend = select_sm120_moe_backend(\n num_tokens=max(\n 1, (capacity_rows + max(1, int(num_topk)) - 1) // max(1, int(num_topk))\n ),\n num_topk=int(num_topk),\n activation_precision=activation_precision,\n )\n if backend == \"dynamic\":\n return allocate_sm120_dynamic_workspace(\n state_E=state_E,\n weight_E=weight_E,\n routed_rows=capacity_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation_precision=activation_precision,\n )\n if backend == \"static\":\n return allocate_sm120_static_workspace(\n state_E=state_E,\n weight_E=weight_E,\n max_rows=capacity_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n activation_precision=activation_precision,\n )\n raise ValueError(f\"unsupported SM120 MoE backend {backend!r}\")\n\n\ndef _get_cached_workspace(\n *,\n backend: str,\n state_E: int,\n weight_E: int,\n routed_rows: int,\n k: int,\n n: int,\n num_topk: int,\n device: torch.device,\n activation_precision: str = \"fp4\",\n quant_mode: str | None = None,\n activation: str = \"silu\",\n) -> _Sm120Workspace:\n \"\"\"Get or allocate a cached workspace for the given problem shape.\n\n Reuses the cached workspace if it has enough capacity for the requested\n routed_rows. For static workspaces, max_rows is the direct capacity.\n For dynamic workspaces, routed_rows_capacity is used because the dynamic\n geometry (physical tiles, task queue slots) depends on the original\n routed_rows, not just max_rows.\n \"\"\"\n quant_mode = _normalize_quant_mode(quant_mode, activation_precision)\n activation_precision = _activation_precision_from_quant_mode(quant_mode)\n cache_key = (\n state_E,\n weight_E,\n k,\n n,\n num_topk,\n str(device),\n backend,\n quant_mode,\n activation,\n )\n cached = _WORKSPACE_CACHE.get(cache_key)\n\n if cached is not None:\n if isinstance(cached, (Sm120DynamicMoEWorkspace, Sm120W4A16MoEWorkspace)):\n if cached.routed_rows_capacity >= max(1, routed_rows): # type: ignore[union-attr]\n return cached\n else:\n if cached.max_rows >= max(1, routed_rows):\n return cached\n\n if quant_mode == \"w4a16\" and _is_cuda_graph_capturing():\n raise RuntimeError(\n \"W4A16 workspace is not initialized for CUDA graph capture; \"\n \"provide a preallocated workspace from \"\n \"allocate_sm120_moe_workspace(..., quant_mode='w4a16') or warm the \"\n \"functional path before capture.\"\n )\n workspace = allocate_sm120_moe_workspace(\n state_E=state_E,\n weight_E=weight_E,\n routed_rows=routed_rows,\n k=k,\n n=n,\n num_topk=num_topk,\n device=device,\n quant_mode=quant_mode,\n activation_precision=activation_precision,\n backend=backend,\n activation=activation,\n )\n\n _WORKSPACE_CACHE[cache_key] = workspace\n return workspace\n\n\n# ==========================================================================\n# Unified dispatch\n# ==========================================================================\n_PADDED_WEIGHT_CACHE: Dict[Tuple, Tuple] = {}\n\n\ndef _pad_intermediate_to_tile(\n w1_weight,\n w1_weight_sf,\n w2_weight,\n w2_weight_sf,\n fc2_input_scale,\n n,\n tile,\n h,\n num_experts,\n is_gated,\n):\n \"\"\"Zero-pad NVFP4 weights + scale factors so the intermediate size is a\n multiple of ``tile`` (gate/up tile-split requirement); padded channels are\n zero, so the result is numerically identical.\n \"\"\"\n n_pad = ((n + tile - 1) // tile) * tile\n if n_pad == n:\n return w1_weight, w1_weight_sf, w2_weight, w2_weight_sf, fc2_input_scale, n\n E = int(num_experts)\n fc2_input_scale_src = fc2_input_scale\n key = (\n n,\n tile,\n h,\n E,\n bool(is_gated),\n w1_weight.data_ptr(),\n w1_weight_sf.data_ptr(),\n w2_weight.data_ptr(),\n w2_weight_sf.data_ptr(),\n fc2_input_scale_src.data_ptr() if fc2_input_scale_src is not None else 0,\n )\n cached = _PADDED_WEIGHT_CACHE.get(key)\n if cached is not None:\n return cached\n\n def mma_to_logical(sf, m, k):\n sw = convert_sf_from_mma_layout(sf, m=m, k=k, num_groups=E)\n m_pad = ((m + 127) // 128) * 128\n sw = sw.reshape(E, m_pad, -1)\n cb = (k + SF_VEC_SIZE - 1) // SF_VEC_SIZE\n return torch.stack(\n [unswizzle_block_scale(sw[e], rows=m, cols_blocks=cb) for e in range(E)], 0\n )\n\n def logical_to_mma(log, m, k):\n sw = torch.stack([swizzle_block_scale(log[e]) for e in range(E)], 0)\n sw2d = sw.reshape(E * sw.shape[1], sw.shape[2]).to(torch.float8_e4m3fn)\n return convert_sf_to_mma_layout(sw2d, m=m, k=k, num_groups=E)\n\n def pad_dim(t, dim, old, new):\n if new == old:\n return t\n shp = list(t.shape)\n shp[dim] = new - old\n return torch.cat([t, t.new_zeros(shp)], dim=dim)\n\n if is_gated:\n # w1 packs [up(0:n), gate(n:2n)] rows; pad each half so the split stays\n # tile-aligned, then re-concat.\n up, gate = w1_weight[:, :n, :], w1_weight[:, n : 2 * n, :]\n w1p = torch.cat([pad_dim(up, 1, n, n_pad), pad_dim(gate, 1, n, n_pad)], dim=1)\n log1 = mma_to_logical(w1_weight_sf, m=2 * n, k=h)\n up_sf, gate_sf = log1[:, :n, :], log1[:, n : 2 * n, :]\n log1p = torch.cat(\n [pad_dim(up_sf, 1, n, n_pad), pad_dim(gate_sf, 1, n, n_pad)], dim=1\n )\n w1_sf_p = logical_to_mma(log1p, m=2 * n_pad, k=h)\n else:\n w1p = pad_dim(w1_weight, 1, n, n_pad)\n log1 = mma_to_logical(w1_weight_sf, m=n, k=h)\n w1_sf_p = logical_to_mma(pad_dim(log1, 1, n, n_pad), m=n_pad, k=h)\n\n # w2 reduces over the intermediate dim: pad its packed columns + SF columns.\n w2p = pad_dim(w2_weight, 2, n // 2, n_pad // 2)\n log2 = mma_to_logical(w2_weight_sf, m=h, k=n)\n cb_n = (n + SF_VEC_SIZE - 1) // SF_VEC_SIZE\n cb_np = (n_pad + SF_VEC_SIZE - 1) // SF_VEC_SIZE\n w2_sf_p = logical_to_mma(pad_dim(log2, 2, cb_n, cb_np), m=h, k=n_pad)\n\n if fc2_input_scale_src is not None and fc2_input_scale_src.numel() == n:\n fc2_input_scale = pad_dim(fc2_input_scale_src, 0, n, n_pad)\n result = (w1p, w1_sf_p, w2p, w2_sf_p, fc2_input_scale, n_pad)\n _PADDED_WEIGHT_CACHE[key] = result\n _register_cache_eviction(\n _PADDED_WEIGHT_CACHE,\n key,\n w1_weight,\n w1_weight_sf,\n w2_weight,\n w2_weight_sf,\n fc2_input_scale_src,\n )\n return result\n\n\ndef launch_sm120_moe(\n *,\n a: torch.Tensor,\n topk_ids: torch.Tensor,\n topk_weights: torch.Tensor,\n w1_weight: torch.Tensor,\n w1_weight_sf: torch.Tensor,\n w1_alpha: torch.Tensor,\n fc2_input_scale: Optional[torch.Tensor] = None,\n input_global_scale: Optional[torch.Tensor] = None,\n w2_weight: torch.Tensor,\n w2_weight_sf: torch.Tensor,\n w2_alpha: torch.Tensor,\n num_experts: int,\n top_k: int,\n num_local_experts: int,\n scatter_output: torch.Tensor,\n input_scales_are_reciprocal: bool = False,\n fast_math: bool = True,\n activation: str = \"silu\",\n swiglu_alpha: float = 1.702,\n swiglu_beta: float = 1.0,\n swiglu_limit: float | None = None,\n activation_precision: str = \"fp4\",\n quant_mode: str | None = None,\n source_format: str = \"modelopt\",\n _workspace=None,\n _weight_views=None,\n _prepared_weights=None,\n) -> torch.Tensor:\n \"\"\"Unified SM120 MoE dispatch — selects static or dynamic by token count.\n\n input_global_scale overrides w1_alpha as the FC1 input-quant scale and\n is folded into the multiplier internally. With _weight_views supplied,\n w1_alpha must already contain the fold.\n\n Optional _workspace and _weight_views can be pre-allocated and reused\n across calls to avoid per-call allocation overhead (wrapper path).\n When not provided (functional API path), a module-level workspace cache\n is used to avoid re-allocating on every call.\n \"\"\"\n quant_mode = _normalize_quant_mode(quant_mode, activation_precision)\n source_format = _normalize_source_format_for_quant_mode(source_format, quant_mode)\n activation_precision = _activation_precision_from_quant_mode(quant_mode)\n\n num_tokens = topk_ids.size(0)\n k = a.size(1) # hidden_size\n is_gated = is_gated_activation(activation)\n # w1_weight.size(1) is 2*n for gated or n for non-gated\n intermediate_size = w1_weight.size(1) // 2 if is_gated else w1_weight.size(1)\n n = intermediate_size\n\n # NVFP4 kernels need padded intermediate size.\n if quant_mode != \"w4a16\" and n % _LEVEL_TILE_N != 0 and _weight_views is None:\n (\n w1_weight,\n w1_weight_sf,\n w2_weight,\n w2_weight_sf,\n fc2_input_scale,\n n,\n ) = _pad_intermediate_to_tile(\n w1_weight,\n w1_weight_sf,\n w2_weight,\n w2_weight_sf,\n fc2_input_scale,\n n,\n _LEVEL_TILE_N,\n k,\n w1_weight.size(0),\n is_gated,\n )\n\n routed_rows = num_tokens * top_k\n\n if quant_mode == \"w4a16\":\n return _launch_sm120_w4a16_moe(\n a=a,\n topk_ids=topk_ids,\n topk_weights=topk_weights,\n w1_weight=w1_weight,\n w1_weight_sf=w1_weight_sf,\n w1_alpha=w1_alpha,\n w2_weight=w2_weight,\n w2_weight_sf=w2_weight_sf,\n w2_alpha=w2_alpha,\n num_experts=num_experts,\n top_k=top_k,\n num_local_experts=num_local_experts,\n scatter_output=scatter_output,\n fast_math=fast_math,\n activation=activation,\n source_format=source_format,\n _workspace=_workspace,\n _prepared_weights=_prepared_weights,\n )\n\n if fc2_input_scale is None:\n raise ValueError(\"fc2_input_scale is required when quant_mode='nvfp4'.\")\n down_input_scale = fc2_input_scale\n if input_global_scale is not None:\n input_gs = input_global_scale\n if _weight_views is None:\n # Alpha must carry input_gs back or the output magnitude is wrong.\n # The wrapper folds before building _weight_views; don't fold twice.\n w1_alpha = (\n w1_alpha.to(torch.float32) * input_global_scale.to(torch.float32)\n ).contiguous()\n else:\n input_gs = w1_alpha\n\n weights = (\n _weight_views\n if _weight_views is not None\n else _get_weight_views(\n w1_fp4=w1_weight,\n w1_blockscale=w1_weight_sf,\n w2_fp4=w2_weight,\n w2_blockscale=w2_weight_sf,\n w1_alphas=w1_alpha,\n w2_alphas=w2_alpha,\n n=n,\n k=k,\n activation_precision=activation_precision,\n )\n )\n\n # Resolve workspace and backend selection.\n # When a pre-allocated workspace is provided (CUDA graph wrapper path),\n # infer the backend from the workspace type so they stay in sync —\n # the caller already committed to a backend at allocation time.\n if _workspace is not None:\n workspace = _workspace\n workspace_activation_precision = getattr(\n workspace, \"activation_precision\", activation_precision\n )\n if workspace_activation_precision != activation_precision:\n raise ValueError(\n \"pre-allocated workspace activation_precision does not match \"\n f\"requested activation_precision={activation_precision!r}.\"\n )\n if isinstance(workspace, Sm120DynamicMoEWorkspace):\n if num_local_experts != num_experts:\n raise ValueError(\n \"pre-allocated dynamic SM120 MoE workspace requires \"\n \"num_local_experts == num_experts because dynamic expert \"\n \"buffers are indexed by global topk ids.\"\n )\n backend = \"dynamic\"\n else:\n backend = \"static\"\n else:\n backend = select_sm120_moe_backend(\n num_tokens=num_tokens,\n num_topk=top_k,\n activation_precision=activation_precision,\n )\n # The dynamic kernel indexes row_counts/expert_write_rows directly with\n # topk_ids but those buffers are sized with num_local_experts. Unless\n # num_local_experts == num_experts, fall back to the static backend which\n # has global-to-local expert remapping.\n if backend == \"dynamic\" and num_local_experts != num_experts:\n backend = \"static\"\n workspace = _get_cached_workspace(\n backend=backend,\n state_E=num_local_experts,\n weight_E=num_experts,\n routed_rows=routed_rows,\n k=k,\n n=n,\n num_topk=top_k,\n device=a.device,\n activation_precision=activation_precision,\n quant_mode=quant_mode,\n activation=activation,\n )\n\n if backend == \"dynamic\":\n return launch_sm120_dynamic_moe(\n workspace=workspace,\n weights=weights,\n a=a,\n topk_ids=topk_ids,\n topk_weights=topk_weights,\n input_gs=input_gs,\n down_input_scale=down_input_scale,\n scatter_output=scatter_output,\n num_experts=num_experts,\n num_tokens=num_tokens,\n k=k,\n n=n,\n top_k=top_k,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n activation_precision=activation_precision,\n )\n else:\n return launch_sm120_static_moe(\n workspace=workspace,\n weights=weights,\n a=a,\n topk_ids=topk_ids,\n topk_weights=topk_weights,\n input_gs=input_gs,\n down_input_scale=down_input_scale,\n scatter_output=scatter_output,\n num_experts=num_experts,\n num_tokens=num_tokens,\n k=k,\n n=n,\n top_k=top_k,\n input_scales_are_reciprocal=input_scales_are_reciprocal,\n fast_math=fast_math,\n activation=activation,\n swiglu_alpha=swiglu_alpha,\n swiglu_beta=swiglu_beta,\n swiglu_limit=swiglu_limit,\n activation_precision=activation_precision,\n )\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## 📌 Description\n\nSyncs the SM12x NVFP4 (W4A4) fused-MoE kernels behind `b12x_fused_moe` and `B12xMoEWrapper` with upstream [b12x](https://github.com/local-inference-lab/sparkinfer) at `f9be272`, reaching backend parity.\n\nThe module now has four kernels. `MoEDirectMicroKernel` takes the smallest decode batches, `MoEMicroKernel` and `MoEStaticKernel` cover the rest of decode with tile assignments fixed at launch, and `MoEDynamicKernel` covers prefill by distributing tiles through an in-kernel work queue.\n\nChanges:\n\n- Adopt upstream's current `MoEDirectMicroKernel`, replacing a stale copy in `moe_direct_micro_kernel.py` that was never routed to. It reads the top-k ids directly, so the smallest batches skip the routing pre-pass that dominates their runtime, and it now supports gelu_tanh.\n- Let `MoEDynamicKernel` use tiles smaller than 128 rows, so sparse routing stops padding every expert up to 128.\n- Launch all kernels cooperatively. They synchronize the whole grid between phases, which deadlocks if concurrent work keeps part of the grid off the GPU.\n- Simplify `MoEDynamicKernel`'s work queue and size its pipeline stages from the real shared-memory footprint.\n- Vectorize `MoEStaticKernel`'s scatter epilogue and refresh the decode tile heuristics.\n- Restrict the fast FP4 quantizer to gated activations, since relu2's squared outputs need the exact one.\n\nPublic API and behavior changes: none.\n\n## 📊 Performance\n\nVersus main, measured over 38 target-model MoE shapes on three GPUs. Geomean speedup per shape group:\n\n| shape group | DGX Spark | RTX 5080 | RTX Pro 6000 SE |\n|---|---|---|---|\n| decode, batch 1-2 | 1.06x | 1.30x | 1.40x |\n| decode, batch 4-40 | 1.00x | 1.00x | 1.00x |\n| prefill, batch 512-2048 | 1.10x | 1.10x | 1.09x |\n| prefill, batch 8192 | 1.00x | 1.00x | 1.00x |\n\n- The batch 1-2 gains come from the new `MoEDirectMicroKernel`; the shapes it serves win up to 2.3x.\n- The prefill gains come from `MoEDynamicKernel` picking tiles smaller than 128 rows; those shapes win up to 1.26x.\n\n## 🔍 Related Issues\n\n#4223 (item 2).\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n## 🧪 Tests\n\n- On SM121 (DGX Spark GB10): `tests/moe/test_b12x_fused_moe.py` (157 cases) and `tests/moe/test_unified_moe_b12x.py` (58 cases) pass, including tests that force each backend and a test that a smaller tile is picked again after a large-batch call.\n\n## Reviewer Notes\n\nDeviations from the b12x source, beyond import plumbing:\n\n- gelu_tanh added to `MoEDirectMicroKernel`, matching the activation coverage of the module's other kernels.\n- The module's API accepts reciprocal-form scales but upstream's kernel only takes multipliers, so dispatch inverts them before launch.\n- `MoEDirectMicroKernel`'s cutover is re-measured: upstream's only alternative is its counterpart of `MoEDynamicKernel`, while here it competes with `MoEMicroKernel` and `MoEStaticKernel`.\n- Upstream sizes scratch and builds the kernel together inside one plan object, so their tile sizes always match. FlashInfer has no plan object, so the workspace cache is keyed by tile size to give the same guarantee.\n\n🤖 Generated with [Claude Code](https://claude.com/claude-code)\n\n"},"gains":{"kind":"string","value":"[{\"scope\": \"e2e\", \"hardware\": \"DGX Spark\", \"model\": null, \"shape\": \"decode, batch 1-2\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.06, \"speedup\": 1.06}, {\"scope\": \"e2e\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"decode, batch 1-2\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.3, \"speedup\": 1.3}, {\"scope\": \"e2e\", \"hardware\": \"RTX Pro 6000 SE\", \"model\": null, \"shape\": \"decode, batch 1-2\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.4, \"speedup\": 1.4}, {\"scope\": \"e2e\", \"hardware\": \"DGX Spark\", \"model\": null, \"shape\": \"decode, batch 4-40\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.0, \"speedup\": 1.0}, {\"scope\": \"e2e\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"decode, batch 4-40\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.0, \"speedup\": 1.0}, {\"scope\": \"e2e\", \"hardware\": \"RTX Pro 6000 SE\", \"model\": null, \"shape\": \"decode, batch 4-40\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.0, \"speedup\": 1.0}, {\"scope\": \"e2e\", \"hardware\": \"DGX Spark\", \"model\": null, \"shape\": \"prefill, batch 512-2048\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.1, \"speedup\": 1.1}, {\"scope\": \"e2e\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"prefill, batch 512-2048\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.1, \"speedup\": 1.1}, {\"scope\": \"e2e\", \"hardware\": \"RTX Pro 6000 SE\", \"model\": null, \"shape\": \"prefill, batch 512-2048\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.09, \"speedup\": 1.09}, {\"scope\": \"e2e\", \"hardware\": \"DGX Spark\", \"model\": null, \"shape\": \"prefill, batch 8192\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.0, \"speedup\": 1.0}, {\"scope\": \"e2e\", \"hardware\": \"RTX 5080\", \"model\": null, \"shape\": \"prefill, batch 8192\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.0, \"speedup\": 1.0}, {\"scope\": \"e2e\", \"hardware\": \"RTX Pro 6000 SE\", \"model\": null, \"shape\": \"prefill, batch 8192\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.0, \"speedup\": 1.0}]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"number","value":1.03,"string":"1.03"}}}],"truncated":false,"partial":false},"paginationData":{"pageIndex":10,"numItemsPerPage":100,"numTotalItems":1365,"offset":1000,"length":100}},"jwt":"eyJhbGciOiJFZERTQSIsImtpZCI6IjVHZDBvd0g5MTM2eDZjc1FvbE1zcktNWUZoRVFoUm5PVVVybEpjOUhaUEEifQ.eyJyZWFkIjp0cnVlLCJwZXJtaXNzaW9ucyI6eyJyZXBvLmNvbnRlbnQucmVhZCI6dHJ1ZX0sInJlcG9JZHMiOlsiNmFkYjE3ZGJmZDFkOTk5NTg0YWY2M2I5Il0sImlhdCI6MTc5NDE0OTMyMiwianRpIjoiMGEwNjQyMGUtZjI0OS00ZmNhLWExMjEtNWVkNjBiMmM1Y2NlIiwic3ViIjoiL2RhdGFzZXRzL2d1eWNodWsva2VybmVsLW9wdC1ybCIsImV4cCI6MTc5NDE1MjkyMiwiaXNzIjoiaHR0cHM6Ly9odWdnaW5nZmFjZS5jbyJ9.yqnlMIMnzaKJwLUBeH4yNaleUeALGMscV2XSn9vUAGbiD6-UOdGQ8gNrwmK-RXVsyEpdkiOmntgtIFZ5pY35BQ","displayUrls":true,"splitSizeSummaries":[{"config":"kernel_commits","split":"train","numRows":1365,"numBytesParquet":42213599},{"config":"kernel_commits","split":"test","numRows":152,"numBytesParquet":5808547},{"config":"tuned_configs","split":"train","numRows":17561,"numBytesParquet":24732360},{"config":"tuned_configs","split":"test","numRows":1726,"numBytesParquet":2111842}]},"discussionsStats":{"closed":0,"open":0,"total":0},"fullWidth":true,"hasGatedAccess":true,"hasFullAccess":true,"isEmbedded":false,"savedQueries":{"community":[],"user":[]}}">
repo stringclasses 3
values | commit stringlengths 40 40 | date stringdate 2023-04-02 02:30:17-0500 2026-10-18 07:42:16-0500 | pr_number int64 20 61.9k ⌀ | pr_url stringlengths 44 53 ⌀ | title stringlengths 8 263 | message stringlengths 8 8k | path stringlengths 10 155 | language stringclasses 4
values | license stringclasses 4
values | before_code stringlengths 160 118k | after_code stringlengths 340 120k | diff stringlengths 149 51k | lines_added int64 0 729 | lines_removed int64 0 488 | files_in_commit int64 1 10 | models_mentioned listlengths 0 4 | hardware_mentioned listlengths 0 16 | speedup_claims listlengths 0 10 | prompt stringlengths 569 119k | pr_body stringlengths 0 24k | gains stringlengths 2 197k | kernel_speedup float64 0.78 150 ⌀ | e2e_speedup float64 0.76 136 ⌀ |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
flashinfer | 911cb09d0981c38d15b775b7820e4a76c72fcfa0 | 2026-10-04T10:47:29-07:00 | 6,045 | https://github.com/flashinfer-ai/flashinfer/pull/6045 | perf(cake_sparse_mla): rounds 7-17 DSv4 sparse-MLA Cake programs for SM100/SM103 on the #5920 layout (cumulative) (#6045) | perf(cake_sparse_mla): rounds 7-17 DSv4 sparse-MLA Cake programs for SM100/SM103 on the #5920 layout (cumulative) (#6045)
## Summary
Rounds 7-17 of the DSv4 sparse-MLA Cake backend (`backend="cake"`, SM100
+ SM103) as one cumulative change on the #5920 layout (per-variant
bindings taking their checks from `tvm_ffi_ut... | csrc/cake_dsv4/common/cake_dsv4_split_reduce_binding.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/cake_dsv4/common/cake_dsv4_split_reduce_binding.cu
+++ csrc/cake_dsv4/common/cake_dsv4_split_reduce_binding.cu
@@ -15,35 +15,43 @@
*/
// Generated by the Cake source exporter — do not edit.
-// tvm-ffi direct-source launcher for Cake kernel 'kernel_cake_dsv4_d50dd820272ad24f7027'.
-#include "cake_dsv4_hos... | 29 | 21 | 7 | [
"deepseek"
] | [
"B200",
"CPU",
"GB300",
"SM100",
"SM103",
"SM120"
] | [
"4 x",
"0.9578x",
"0.9820x",
"6 x"
] | Optimize this cuda kernel file from flashinfer (csrc/cake_dsv4/common/cake_dsv4_split_reduce_binding.cu).
Goal: perf(cake_sparse_mla): rounds 7-17 DSv4 sparse-MLA Cake programs for SM100/SM103 on the #5920 layout (cumulative)
Target hardware: B200, CPU, GB300, SM100, SM103, SM120
Target models: deepseek
Current file:... | ## Summary
Rounds 7-17 of the DSv4 sparse-MLA Cake backend (`backend="cake"`, SM100 + SM103) as one cumulative change on the #5920 layout (per-variant bindings taking their checks from `tvm_ffi_utils.h`, shared sources under `common/`, `run_sequence`, the host's direct variant launches). Main carries round 6 (#5700) f... | [{"scope": "kernel", "hardware": "GB300", "model": null, "shape": null, "batch_size": null, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 6.53, "optimized": 6.88, "stated_speedup": null, "speedup": 0.9491}, {"scope": "kernel", "hardware": "B200", "model": null, "shape": null, "batch_size": n... | 1.022 | null |
flashinfer | 911cb09d0981c38d15b775b7820e4a76c72fcfa0 | 2026-10-04T10:47:29-07:00 | 6,045 | https://github.com/flashinfer-ai/flashinfer/pull/6045 | perf(cake_sparse_mla): rounds 7-17 DSv4 sparse-MLA Cake programs for SM100/SM103 on the #5920 layout (cumulative) (#6045) | perf(cake_sparse_mla): rounds 7-17 DSv4 sparse-MLA Cake programs for SM100/SM103 on the #5920 layout (cumulative) (#6045)
## Summary
Rounds 7-17 of the DSv4 sparse-MLA Cake backend (`backend="cake"`, SM100
+ SM103) as one cumulative change on the #5920 layout (per-variant
bindings taking their checks from `tvm_ffi_ut... | csrc/cake_dsv4/common/cake_dsv4_split_reduce_kernel.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/cake_dsv4/common/cake_dsv4_split_reduce_kernel.cu
+++ csrc/cake_dsv4/common/cake_dsv4_split_reduce_kernel.cu
@@ -26,7 +26,6 @@
static_assert(sizeof(uint64_t) == 8, "Cake requires an LP64 CUDA host ABI");
typedef signed int int32_t;
typedef short int int16_t;
-struct __align__(128) CakeTenso... | 2 | 5 | 7 | [
"deepseek"
] | [
"B200",
"CPU",
"GB300",
"SM100",
"SM103",
"SM120"
] | [
"4 x",
"0.9578x",
"0.9820x",
"6 x"
] | Optimize this cuda kernel file from flashinfer (csrc/cake_dsv4/common/cake_dsv4_split_reduce_kernel.cu).
Goal: perf(cake_sparse_mla): rounds 7-17 DSv4 sparse-MLA Cake programs for SM100/SM103 on the #5920 layout (cumulative)
Target hardware: B200, CPU, GB300, SM100, SM103, SM120
Target models: deepseek
Current file:
... | ## Summary
Rounds 7-17 of the DSv4 sparse-MLA Cake backend (`backend="cake"`, SM100 + SM103) as one cumulative change on the #5920 layout (per-variant bindings taking their checks from `tvm_ffi_utils.h`, shared sources under `common/`, `run_sequence`, the host's direct variant launches). Main carries round 6 (#5700) f... | [{"scope": "kernel", "hardware": "GB300", "model": null, "shape": null, "batch_size": null, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 6.53, "optimized": 6.88, "stated_speedup": null, "speedup": 0.9491}, {"scope": "kernel", "hardware": "B200", "model": null, "shape": null, "batch_size": n... | 1.022 | null |
flashinfer | eafe816df2fea3d40d03e61842d8f7a383992292 | 2026-10-03T14:03:36-07:00 | 5,709 | https://github.com/flashinfer-ai/flashinfer/pull/5709 | perf(mla): prefetch split partials in the CuTe DSL MLA decode reducer (#5709) | perf(mla): prefetch split partials in the CuTe DSL MLA decode reducer (#5709)
## 📌 Description
The monolithic CuTe DSL MLA decode reducer (FP8 and FP16/BF16) walks the
splits in a runtime loop with one dependent L2 load per split, so its
cost grows with the split count (3.7 → 5.5 µs from 32 to 64 splits for
12 heads... | flashinfer/cute_dsl/attention/monolithic/mla_decode.py | cute_dsl | Apache-2.0 | # Copyright (c) 2026 by FlashInfer team.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in... | # Copyright (c) 2026 by FlashInfer team.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in... | --- flashinfer/cute_dsl/attention/monolithic/mla_decode.py
+++ flashinfer/cute_dsl/attention/monolithic/mla_decode.py
@@ -43,8 +43,7 @@
_CUDA_GRID_Y_MAX = 65_535
-_REDUCER_D_TILE_CANDIDATES = (1, 2, 4)
-_STATIC_REDUCER_MAX_SPLITS = 32
+_STATIC_REDUCER_MAX_SPLITS = 48
def _validate_nonpersistent_grid_y(
@@ -67... | 20 | 29 | 4 | [] | [
"SM100",
"SM103",
"SM107"
] | [] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/cute_dsl/attention/monolithic/mla_decode.py).
Goal: perf(mla): prefetch split partials in the CuTe DSL MLA decode reducer
Target hardware: SM100, SM103, SM107
Target models: unspecified
Current file:
```python
# Copyright (c) 2026 by FlashInfer team.
#
# ... | ## 📌 Description
The monolithic CuTe DSL MLA decode reducer (FP8 and FP16/BF16) walks the splits in a runtime loop with one dependent L2 load per split, so its cost grows with the split count (3.7 → 5.5 µs from 32 to 64 splits for 12 heads × 8 query tokens on SM107) and splitting long KV further does not pay off.
**... | [{"scope": "e2e", "hardware": "SM107", "model": null, "shape": "q_len=8,heads=12", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 9.11, "optimized": 8.03, "stated_speedup": null, "speedup": 1.1345}, {"scope": "e2e", "hardware": "SM107", "model": null, "shape": "q_len=8,heads=... | null | 1.1432 |
flashinfer | b8a3c20827d5e5dfb35e79310eb20c90a91416d2 | 2026-10-02T23:03:44-07:00 | 6,005 | https://github.com/flashinfer-ai/flashinfer/pull/6005 | perf(cake kda): serve explicit T=1 cu_seqlens decode on the frozen Cake route and memoize schedule selection (#6005) | perf(cake kda): serve explicit T=1 cu_seqlens decode on the frozen Cake route and memoize schedule selection (#6005)
<!-- .github/PULL_REQUEST_TEMPLATE.md -->
## 📌 Description
Follow-up to #5760, which measured the frozen Cake schedule to be the
faster one for explicit T=1 `cu_seqlens` decode and stopped `"auto"`
f... | flashinfer/kda_kernels/recurrent_kda.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/kda_kernels/recurrent_kda.py
+++ flashinfer/kda_kernels/recurrent_kda.py
@@ -1295,10 +1295,12 @@
return begin, begin + (last_element + 1) * tensor.element_size()
+def _byte_ranges_overlap(lhs: tuple[int, int], rhs: tuple[int, int]) -> bool:
+ return lhs[0] < rhs[1] and rhs[0] < lhs[1]
+
+
de... | 210 | 67 | 1 | [] | [
"B200",
"CPU"
] | [] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/kda_kernels/recurrent_kda.py).
Goal: perf(cake kda): serve explicit T=1 cu_seqlens decode on the frozen Cake route and memoize schedule selection
Target hardware: B200, CPU
Target models: unspecified
Current file:
```python
"""
Copyright (c) 2025 by Flash... | <!-- .github/PULL_REQUEST_TEMPLATE.md -->
## 📌 Description
Follow-up to #5760, which measured the frozen Cake schedule to be the faster one for explicit T=1 `cu_seqlens` decode and stopped `"auto"` from probing it only because selection was too expensive. This PR removes the two host-side costs that made that necess... | [{"scope": "kernel", "hardware": "B200", "model": null, "shape": "H=16,K=128", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 111.5, "optimized": 34.0, "stated_speedup": null, "speedup": 3.2794}, {"scope": "kernel", "hardware": "B200", "model": null, "shape": "H=16,K=128", "b... | 1.6643 | null |
flashinfer | 4af32c083c1af82d0fef65d318c05b05b3bb8122 | 2026-10-02T16:14:23-07:00 | 5,760 | https://github.com/flashinfer-ai/flashinfer/pull/5760 | perf(kda): stop probing Cake for explicit T=1 cu_seqlens decode under "auto" (#5760) | perf(kda): stop probing Cake for explicit T=1 cu_seqlens decode under "auto" (#5760)
<!-- .github/PULL_REQUEST_TEMPLATE.md -->
## 📌 Description
`backend="cake"` refuses explicit T=1 `cu_seqlens` decode outright — it
raises in `run_recurrent_kda` before the selector runs. `backend="auto"`
did not. Because `auto_unbo... | flashinfer/kda_kernels/recurrent_kda.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/kda_kernels/recurrent_kda.py
+++ flashinfer/kda_kernels/recurrent_kda.py
@@ -2081,6 +2081,7 @@
auto_unbounded_softplus_candidate = (
backend == "auto"
and num_spec_tokens is None
+ and cu_seqlens is None
and H > 0
and HV == H
and K == 128 | 1 | 0 | 1 | [] | [
"B200"
] | [
"1.4x",
"1.37x",
"1.49x",
"1.39x",
"1.87x",
"4.03x",
"1.67x",
"8.0x",
"3.8x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/kda_kernels/recurrent_kda.py).
Goal: perf(kda): stop probing Cake for explicit T=1 cu_seqlens decode under "auto"
Target hardware: B200
Target models: unspecified
Current file:
```python
"""
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apach... | <!-- .github/PULL_REQUEST_TEMPLATE.md -->
## 📌 Description
`backend="cake"` refuses explicit T=1 `cu_seqlens` decode outright — it raises in `run_recurrent_kda` before the selector runs. `backend="auto"` did not. Because `auto_unbounded_softplus_candidate` never tested `cu_seqlens`, `auto` probed the Cake selector o... | [{"scope": "kernel", "hardware": "B200", "model": null, "shape": "H=16,K=128,V=128", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 88.06, "optimized": 24.54, "stated_speedup": null, "speedup": 3.5884}, {"scope": "kernel", "hardware": "B200", "model": null, "shape": "H=16,K=1... | 2.4044 | null |
flashinfer | 3dea41055e232fddca253ea814913d41b0e3727b | 2026-10-02T13:22:53-07:00 | 5,950 | https://github.com/flashinfer-ai/flashinfer/pull/5950 | perf(cake_sampling): round 8 -- slab-tail twins of the sample builds, pushed-coarse-sums twin of the cluster-8 default build, Hopper whole-CTA tail policy (#5950) | perf(cake_sampling): round 8 -- slab-tail twins of the sample builds, pushed-coarse-sums twin of the cluster-8 default build, Hopper whole-CTA tail policy (#5950)
## Cake radix sampling, round 8: slab-tail twins of the sample builds
and a pushed-coarse-sums twin of the cluster-8 default build
Follow-up of #5439, #548... | csrc/cake_sampling/cake_sampling_binding.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2026 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2026 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/cake_sampling/cake_sampling_binding.cuh
+++ csrc/cake_sampling/cake_sampling_binding.cuh
@@ -27,7 +27,8 @@
// warps) CAKE_SAMPLING_FUSED_BLOCK_TAIL_KCAP largest top-k the whole-CTA stage-2/3 tail serves
// (the slab row) CAKE_SAMPLING_STAGE1_TABLE(X) X(symbol, cluster, ept, stream, threads,
// smem_b... | 65 | 11 | 5 | [
"qwen"
] | [
"B200",
"GB300",
"H100",
"HOPPER",
"SM100",
"SM103",
"SM107",
"SM120",
"SM90"
] | [
"3.1x",
"9.2x",
"2.1x",
"4.5x",
"3.1x",
"9.5x",
"2.3x",
"4.6x",
"2.9x",
"7.8x"
] | Optimize this cuda kernel file from flashinfer (csrc/cake_sampling/cake_sampling_binding.cuh).
Goal: perf(cake_sampling): round 8 -- slab-tail twins of the sample builds, pushed-coarse-sums twin of the cluster-8 default build, Hopper whole-CTA tail policy
Target hardware: B200, GB300, H100, HOPPER, SM100, SM103, SM107... | > Developed by the **CAKE team**, the kernels in this PR **outperform** the relevant **SOTA baselines at the time of merge** on the **vast majority of performance benchmark shapes**, matching them otherwise.
## Cake radix sampling, round 8: slab-tail twins of the sample builds and a pushed-coarse-sums twin of the clus... | [{"scope": "kernel", "hardware": "B200", "model": null, "shape": "k=10", "batch_size": 32, "metric": "time", "unit": null, "higher_is_better": false, "baseline": 1.0, "optimized": 0.972, "stated_speedup": null, "speedup": 1.0288}, {"scope": "kernel", "hardware": "B200", "model": null, "shape": "k=10", "batch_size": 32,... | 1.002 | null |
flashinfer | 3dea41055e232fddca253ea814913d41b0e3727b | 2026-10-02T13:22:53-07:00 | 5,950 | https://github.com/flashinfer-ai/flashinfer/pull/5950 | perf(cake_sampling): round 8 -- slab-tail twins of the sample builds, pushed-coarse-sums twin of the cluster-8 default build, Hopper whole-CTA tail policy (#5950) | perf(cake_sampling): round 8 -- slab-tail twins of the sample builds, pushed-coarse-sums twin of the cluster-8 default build, Hopper whole-CTA tail policy (#5950)
## Cake radix sampling, round 8: slab-tail twins of the sample builds
and a pushed-coarse-sums twin of the cluster-8 default build
Follow-up of #5439, #548... | csrc/cake_sampling/generated/cake_sampling_kernels.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2026 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2026 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/cake_sampling/generated/cake_sampling_kernels.cu
+++ csrc/cake_sampling/generated/cake_sampling_kernels.cu
@@ -28,3 +28,6 @@
#include "cake_sampling_kernels_part4.cuh"
#include "cake_sampling_kernels_part5.cuh"
#include "cake_sampling_kernels_part6.cuh"
+#include "cake_sampling_kernels_part7.cuh"
+#include ... | 3 | 0 | 5 | [
"qwen"
] | [
"B200",
"GB300",
"H100",
"HOPPER",
"SM100",
"SM103",
"SM107",
"SM120",
"SM90"
] | [
"3.1x",
"9.2x",
"2.1x",
"4.5x",
"3.1x",
"9.5x",
"2.3x",
"4.6x",
"2.9x",
"7.8x"
] | Optimize this cuda kernel file from flashinfer (csrc/cake_sampling/generated/cake_sampling_kernels.cu).
Goal: perf(cake_sampling): round 8 -- slab-tail twins of the sample builds, pushed-coarse-sums twin of the cluster-8 default build, Hopper whole-CTA tail policy
Target hardware: B200, GB300, H100, HOPPER, SM100, SM1... | > Developed by the **CAKE team**, the kernels in this PR **outperform** the relevant **SOTA baselines at the time of merge** on the **vast majority of performance benchmark shapes**, matching them otherwise.
## Cake radix sampling, round 8: slab-tail twins of the sample builds and a pushed-coarse-sums twin of the clus... | [{"scope": "kernel", "hardware": "B200", "model": null, "shape": "k=10", "batch_size": 32, "metric": "time", "unit": null, "higher_is_better": false, "baseline": 1.0, "optimized": 0.972, "stated_speedup": null, "speedup": 1.0288}, {"scope": "kernel", "hardware": "B200", "model": null, "shape": "k=10", "batch_size": 32,... | 1.002 | null |
flashinfer | b730d5f6f5929fe666b24b466144a57f5587ba4b | 2026-10-01T22:59:19-07:00 | 5,319 | https://github.com/flashinfer-ai/flashinfer/pull/5319 | perf: optimize CuTe DSL W4A4 and W4A16 unfused finalize (#5319) | perf: optimize CuTe DSL W4A4 and W4A16 unfused finalize (#5319)
<!-- .github/pull_request_template.md -->
## 📌 Description
@humansand
Reduce the cost of deterministic CuTe DSL MoE finalize for W4A4
per-tensor/per-token NVFP4 activation scaling and W4A16 BF16 activations
when `use_fused_finalize=False`.
- **Reduct... | flashinfer/fused_moe/cute_dsl/blackwell/moe_w4a16.py | cute_dsl | Apache-2.0 | # Copyright (c) 2026 FlashInfer contributors.
# SPDX-License-Identifier: Apache-2.0
"""SM100 NVFP4-weight, BF16-activation fused MoE launcher."""
from dataclasses import dataclass
from typing import Dict, Optional, Tuple
import cutlass
import cutlass.cute as cute
import torch
from flashinfer.cute_dsl.utils import (... | # Copyright (c) 2026 FlashInfer contributors.
# SPDX-License-Identifier: Apache-2.0
"""SM100 NVFP4-weight, BF16-activation fused MoE launcher."""
from dataclasses import dataclass
from typing import Dict, Optional, Tuple
import cutlass
import cutlass.cute as cute
import torch
from flashinfer.cute_dsl.utils import (... | --- flashinfer/fused_moe/cute_dsl/blackwell/moe_w4a16.py
+++ flashinfer/fused_moe/cute_dsl/blackwell/moe_w4a16.py
@@ -21,7 +21,6 @@
moe_output_memset_inplace,
moe_permute,
moe_sort,
- moe_unpermute,
normalize_cute_dsl_moe_activation_type,
validate_cute_dsl_moe_situ_config,
)
@@ -32,6 +31,7 ... | 1 | 1 | 4 | [
"deepseek"
] | [
"A10G",
"B300",
"BLACKWELL",
"H100",
"SM100",
"SM103"
] | [
"1.1118×",
"1.0745×",
"1.0783×",
"1.1396×",
"1.0644×",
"1.0519×",
"1.0606×",
"1.0414×",
"1.0356×",
"1.0432×"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/fused_moe/cute_dsl/blackwell/moe_w4a16.py).
Goal: perf: optimize CuTe DSL W4A4 and W4A16 unfused finalize
Target hardware: A10G, B300, BLACKWELL, H100, SM100, SM103
Target models: deepseek
Current file:
```python
# Copyright (c) 2026 FlashInfer contributo... | <!-- .github/pull_request_template.md -->
## 📌 Description
@humansand
Reduce the cost of deterministic CuTe DSL MoE finalize for W4A4 per-tensor/per-token NVFP4 activation scaling and W4A16 BF16 activations when `use_fused_finalize=False`.
- **Reduction:** replace the native standalone finalizer with a shared CuTe... | [{"scope": "kernel", "hardware": "B300", "model": null, "shape": "W4A4 per-tensor", "batch_size": 1, "metric": "latency speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.1118, "speedup": 1.1118}, {"scope": "kernel", "hardware": "B300", "model": null, "shape": "W4... | 1.0194 | 0.9832 |
flashinfer | b730d5f6f5929fe666b24b466144a57f5587ba4b | 2026-10-01T22:59:19-07:00 | 5,319 | https://github.com/flashinfer-ai/flashinfer/pull/5319 | perf: optimize CuTe DSL W4A4 and W4A16 unfused finalize (#5319) | perf: optimize CuTe DSL W4A4 and W4A16 unfused finalize (#5319)
<!-- .github/pull_request_template.md -->
## 📌 Description
@humansand
Reduce the cost of deterministic CuTe DSL MoE finalize for W4A4
per-tensor/per-token NVFP4 activation scaling and W4A16 BF16 activations
when `use_fused_finalize=False`.
- **Reduct... | flashinfer/fused_moe/cute_dsl/blackwell/moe_w4a16_kernel.py | cute_dsl | BSD-3-Clause | # Copyright (c) 2025 - 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Identifier: BSD-3-Clause
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# 1. Redistributions of source code must retain t... | # Copyright (c) 2025 - 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Identifier: BSD-3-Clause
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# 1. Redistributions of source code must retain t... | --- flashinfer/fused_moe/cute_dsl/blackwell/moe_w4a16_kernel.py
+++ flashinfer/fused_moe/cute_dsl/blackwell/moe_w4a16_kernel.py
@@ -1429,6 +1429,13 @@
)
if cutlass.const_expr(self.enable_pdl):
griddepcontrol_wait()
+ # Let the standalone finalizer prepare routin... | 10 | 1 | 4 | [
"deepseek"
] | [
"A10G",
"B300",
"BLACKWELL",
"H100",
"SM100",
"SM103"
] | [
"1.1118×",
"1.0745×",
"1.0783×",
"1.1396×",
"1.0644×",
"1.0519×",
"1.0606×",
"1.0414×",
"1.0356×",
"1.0432×"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/fused_moe/cute_dsl/blackwell/moe_w4a16_kernel.py).
Goal: perf: optimize CuTe DSL W4A4 and W4A16 unfused finalize
Target hardware: A10G, B300, BLACKWELL, H100, SM100, SM103
Target models: deepseek
Current file:
```python
# Copyright (c) 2025 - 2026 NVIDIA ... | <!-- .github/pull_request_template.md -->
## 📌 Description
@humansand
Reduce the cost of deterministic CuTe DSL MoE finalize for W4A4 per-tensor/per-token NVFP4 activation scaling and W4A16 BF16 activations when `use_fused_finalize=False`.
- **Reduction:** replace the native standalone finalizer with a shared CuTe... | [{"scope": "kernel", "hardware": "B300", "model": null, "shape": "W4A4 per-tensor", "batch_size": 1, "metric": "latency speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.1118, "speedup": 1.1118}, {"scope": "kernel", "hardware": "B300", "model": null, "shape": "W4... | 1.0194 | 0.9832 |
flashinfer | 9f58370546a51b09325d1485cfc359d9d35b4319 | 2026-10-01T18:12:09-07:00 | 4,941 | https://github.com/flashinfer-ai/flashinfer/pull/4941 | perf(gemm): cute-dsl bf16-nvfp4 dense gemm fix to include no-autotune fallback tactic (#4941) | perf(gemm): cute-dsl bf16-nvfp4 dense gemm fix to include no-autotune fallback tactic (#4941)
## 📌 Description
Two fixes to the SM100/SM103 CuTe-DSL dense W4A16 (`mm_bf16_fp4`) path.
Both affect only the no-autotune path; autotuned callers are untouched
by change 2 and lose ~2.7% from change 1 (see below).
### 1. R... | flashinfer/gemm/gemm_bf16_fp4_cute_dsl.py | cute_dsl | Apache-2.0 | # SPDX-FileCopyrightText: Copyright (c) 2025 by FlashInfer team.
# SPDX-License-Identifier: Apache-2.0
"""Architecture-specific CuTe-DSL backend for the BF16 x NVFP4 GEMM."""
import functools
from typing import Dict, List, Optional, Tuple, cast
import torch
from ..autotuner import (
AutoTuner,
ConstraintSpec... | # SPDX-FileCopyrightText: Copyright (c) 2025 by FlashInfer team.
# SPDX-License-Identifier: Apache-2.0
"""Architecture-specific CuTe-DSL backend for the BF16 x NVFP4 GEMM."""
import functools
from typing import Dict, List, Optional, Tuple, cast
import torch
from ..autotuner import (
AutoTuner,
ConstraintSpec... | --- flashinfer/gemm/gemm_bf16_fp4_cute_dsl.py
+++ flashinfer/gemm/gemm_bf16_fp4_cute_dsl.py
@@ -639,6 +639,47 @@
_SM100_BF16_FP4_TACTICS = tuple(_sm100_bf16_fp4_tactic_configs())
+_SM100_BF16_FP4_TACTIC_ORDER = {t: i for i, t in enumerate(_SM100_BF16_FP4_TACTICS)}
+
+# Untuned pick, memoized on (m, n, k, sm_count)... | 57 | 9 | 1 | [] | [
"B200",
"B300",
"GB300",
"SM100",
"SM103"
] | [
"1.8x",
"1.81x",
"1.03x",
"1.8x",
"5.1x",
"9.1x",
"10.2x",
"1.00x",
"1.00x",
"1.00x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/gemm/gemm_bf16_fp4_cute_dsl.py).
Goal: perf(gemm): cute-dsl bf16-nvfp4 dense gemm fix to include no-autotune fallback tactic
Target hardware: B200, B300, GB300, SM100, SM103
Target models: unspecified
Current file:
```python
# SPDX-FileCopyrightText: Copy... | ## 📌 Description
Two fixes to the SM100/SM103 CuTe-DSL dense W4A16 (`mm_bf16_fp4`) path. Both affect only the no-autotune path; autotuned callers are untouched by change 2 and lose ~2.7% from change 1 (see below).
### 1. Restore `--opt-level 2` (regression from #4686)
#4686 dropped this path's explicit `--opt-level... | [{"scope": "kernel", "hardware": "B300", "model": null, "shape": "m=256", "batch_size": 256, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 0.0952, "optimized": 0.0523, "stated_speedup": null, "speedup": 1.8203}, {"scope": "kernel", "hardware": "B300", "model": null, "shape": "m=1", "batch_si... | 1.6726 | 5.185 |
flashinfer | 1cad38165e5fe9d3007a07f79b3d5a2d73d6fce4 | 2026-10-01T04:34:16-07:00 | 5,847 | https://github.com/flashinfer-ai/flashinfer/pull/5847 | perf(cake_sampling): round 7 -- speculative-sample stage-1 twin, whole-CTA tail for cluster-8 streams, capability-keyed host policy (#5847) | perf(cake_sampling): round 7 -- speculative-sample stage-1 twin, whole-CTA tail for cluster-8 streams, capability-keyed host policy (#5847)
## cake_sampling round 7: speculative-sample stage-1 twin, whole-CTA
tail for cluster-8 streams, capability-keyed host policy
Follow-up to #5439, #5482, #5585, #5607, #5636, #568... | csrc/cake_sampling/cake_sampling_binding.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2026 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2026 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/cake_sampling/cake_sampling_binding.cuh
+++ csrc/cake_sampling/cake_sampling_binding.cuh
@@ -27,7 +27,7 @@
// warps) CAKE_SAMPLING_FUSED_BLOCK_TAIL_KCAP largest top-k the whole-CTA stage-2/3 tail serves
// (the slab row) CAKE_SAMPLING_STAGE1_TABLE(X) X(symbol, cluster, ept, stream, threads,
// smem_b... | 30 | 9 | 7 | [
"qwen"
] | [
"B200",
"GB300",
"H100",
"HOPPER",
"SM107",
"SM120"
] | [
"1.81x",
"3.52x",
"8.89x",
"1.81x",
"4.07x",
"8.71x",
"1.53x",
"4.22x",
"15.93x",
"1.59x"
] | Optimize this cuda kernel file from flashinfer (csrc/cake_sampling/cake_sampling_binding.cuh).
Goal: perf(cake_sampling): round 7 -- speculative-sample stage-1 twin, whole-CTA tail for cluster-8 streams, capability-keyed host policy
Target hardware: B200, GB300, H100, HOPPER, SM107, SM120
Target models: qwen
Current ... | > Developed by the **CAKE team**, the kernels in this PR **outperform** the relevant **SOTA baselines at the time of merge** on the **vast majority of performance benchmark shapes**, matching them otherwise.
## cake_sampling round 7: speculative-sample stage-1 twin, whole-CTA tail for cluster-8 streams, capability-key... | [{"scope": "kernel", "hardware": "H100 SXM", "model": null, "shape": "k = 1000, V = 262144, B = 1", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 34.1, "optimized": 30.9, "stated_speedup": null, "speedup": 1.1036}, {"scope": "kernel", "hardware": "H100 SXM", "model": null, "... | 1.0195 | 2.1015 |
flashinfer | 1cad38165e5fe9d3007a07f79b3d5a2d73d6fce4 | 2026-10-01T04:34:16-07:00 | 5,847 | https://github.com/flashinfer-ai/flashinfer/pull/5847 | perf(cake_sampling): round 7 -- speculative-sample stage-1 twin, whole-CTA tail for cluster-8 streams, capability-keyed host policy (#5847) | perf(cake_sampling): round 7 -- speculative-sample stage-1 twin, whole-CTA tail for cluster-8 streams, capability-keyed host policy (#5847)
## cake_sampling round 7: speculative-sample stage-1 twin, whole-CTA
tail for cluster-8 streams, capability-keyed host policy
Follow-up to #5439, #5482, #5585, #5607, #5636, #568... | csrc/cake_sampling/generated/cake_sampling_kernels.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2026 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2026 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/cake_sampling/generated/cake_sampling_kernels.cu
+++ csrc/cake_sampling/generated/cake_sampling_kernels.cu
@@ -25,3 +25,6 @@
#include "cake_sampling_kernels_part1.cuh"
#include "cake_sampling_kernels_part2.cuh"
#include "cake_sampling_kernels_part3.cuh"
+#include "cake_sampling_kernels_part4.cuh"
+#include ... | 3 | 0 | 7 | [
"qwen"
] | [
"B200",
"GB300",
"H100",
"HOPPER",
"SM107",
"SM120"
] | [
"1.81x",
"3.52x",
"8.89x",
"1.81x",
"4.07x",
"8.71x",
"1.53x",
"4.22x",
"15.93x",
"1.59x"
] | Optimize this cuda kernel file from flashinfer (csrc/cake_sampling/generated/cake_sampling_kernels.cu).
Goal: perf(cake_sampling): round 7 -- speculative-sample stage-1 twin, whole-CTA tail for cluster-8 streams, capability-keyed host policy
Target hardware: B200, GB300, H100, HOPPER, SM107, SM120
Target models: qwen
... | > Developed by the **CAKE team**, the kernels in this PR **outperform** the relevant **SOTA baselines at the time of merge** on the **vast majority of performance benchmark shapes**, matching them otherwise.
## cake_sampling round 7: speculative-sample stage-1 twin, whole-CTA tail for cluster-8 streams, capability-key... | [{"scope": "kernel", "hardware": "H100 SXM", "model": null, "shape": "k = 1000, V = 262144, B = 1", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 34.1, "optimized": 30.9, "stated_speedup": null, "speedup": 1.1036}, {"scope": "kernel", "hardware": "H100 SXM", "model": null, "... | 1.0195 | 2.1015 |
flashinfer | 192842b4952a4e86c6da427ccf9c0d917efb18c1 | 2026-09-30T19:00:32-07:00 | 5,750 | https://github.com/flashinfer-ai/flashinfer/pull/5750 | perf(cake_gqa): serve BF16/page-16 and E4M3/page-64 (head_dim 128/256) DCP speculative decode on SM100/SM103 with the on-device load-balanced programs (#5750) | perf(cake_gqa): serve BF16/page-16 and E4M3/page-64 (head_dim 128/256) DCP speculative decode on SM100/SM103 with the on-device load-balanced programs (#5750)
## Summary
Round 3 of the on-device load-balanced varlen scheduler (sibling rounds:
#5634 round 1, #5688 round 2) brings the scheduler to the Cake DCP
speculat... | csrc/cake_fmha/include/cake_fmha.h | cpp | Apache-2.0 | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <cuda_runtime_api.h>
#include <cuda_bf16.h>
#include <cuda_fp16.h>
#include <stdint.h>
#include "cake_fmha_hd256_support.h"
struct __align__(128) CakeFmhaTensorMap { uint64_t opaque[16... | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <cuda_runtime_api.h>
#include <cuda_bf16.h>
#include <cuda_fp16.h>
#include <stdint.h>
#include "cake_fmha_hd256_support.h"
struct __align__(128) CakeFmhaTensorMap { uint64_t opaque[16... | --- csrc/cake_fmha/include/cake_fmha.h
+++ csrc/cake_fmha/include/cake_fmha.h
@@ -341,6 +341,330 @@
cudaStream_t stream
);
+extern "C" cudaError_t cake_fmha_launch_decode_balanced_bf16(
+ CakeFmhaTensorMap const* Qt,
+ CakeFmhaTensorMap const* K,
+ CakeFmhaTensorMap const* V,
+ __nv_bfloat16* O_ptr,... | 407 | 0 | 6 | [] | [
"B200",
"BLACKWELL",
"GB300",
"SM100",
"SM103",
"SM107"
] | [
"64 x",
"1.0x",
"1.009x",
"6.7x",
"1.006x",
"7.6x",
"1.038x",
"6.68x",
"3.41x",
"3.55x"
] | Optimize this cpp kernel file from flashinfer (csrc/cake_fmha/include/cake_fmha.h).
Goal: perf(cake_gqa): serve BF16/page-16 and E4M3/page-64 (head_dim 128/256) DCP speculative decode on SM100/SM103 with the on-device load-balanced programs
Target hardware: B200, BLACKWELL, GB300, SM100, SM103, SM107
Target models: un... | > Developed by the **CAKE team**, the kernels in this PR **outperform** the relevant **SOTA baselines at the time of merge** on the **vast majority of performance benchmark shapes**, matching them otherwise.
## Summary
Round 3 of the on-device load-balanced varlen scheduler (sibling rounds: #5634 round 1, #5688 round... | [{"scope": "e2e", "hardware": "GB300", "model": null, "shape": "BF16 cache, page 16, head_dim 128", "batch_size": null, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": 1.0, "optimized": null, "stated_speedup": 1.122, "speedup": 1.122}, {"scope": "e2e", "hardware": "GB300", "model": null, "shape... | 2.0091 | 1.67 |
flashinfer | 5ce4ef801f3606ff38779ca9f88a344779f21c82 | 2026-09-30T13:12:08-07:00 | 5,703 | https://github.com/flashinfer-ai/flashinfer/pull/5703 | perf(mla): deepen FP8 and FP16/BF16 decode load pipelines on SM107 (#5703) | perf(mla): deepen FP8 and FP16/BF16 decode load pipelines on SM107 (#5703)
## 📌 Description
The monolithic CuTe DSL FP8 MLA decode kernel (the default path of
`trtllm_batch_decode_with_kv_cache_mla(backend="cute-dsl")` for FP8 KV)
keeps 3 K and 2 V load stages. That is about 224 KB of shared memory per
CTA, right at... | flashinfer/cute_dsl/attention/monolithic/mla_decode.py | cute_dsl | Apache-2.0 | # Copyright (c) 2026 by FlashInfer team.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in... | # Copyright (c) 2026 by FlashInfer team.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in... | --- flashinfer/cute_dsl/attention/monolithic/mla_decode.py
+++ flashinfer/cute_dsl/attention/monolithic/mla_decode.py
@@ -28,13 +28,14 @@
import torch
from cutlass import Float32, Int32
-from flashinfer.utils import device_support_pdl
+from flashinfer.utils import device_support_pdl, get_compute_capability
from ... | 6 | 2 | 4 | [] | [
"SM100",
"SM103",
"SM107"
] | [] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/cute_dsl/attention/monolithic/mla_decode.py).
Goal: perf(mla): deepen FP8 and FP16/BF16 decode load pipelines on SM107
Target hardware: SM100, SM103, SM107
Target models: unspecified
Current file:
```python
# Copyright (c) 2026 by FlashInfer team.
#
# Lic... | ## 📌 Description
The monolithic CuTe DSL FP8 MLA decode kernel (the default path of `trtllm_batch_decode_with_kv_cache_mla(backend="cute-dsl")` for FP8 KV) keeps 3 K and 2 V load stages. That is about 224 KB of shared memory per CTA, right at the default 227 KB limit.
sm_107 allows 327 KB per CTA: CuTe DSL >= 4.8 li... | [{"scope": "e2e", "hardware": "SM107", "model": null, "shape": "H=12,Q=8", "batch_size": 16, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 298.11, "optimized": 283.08, "stated_speedup": null, "speedup": 1.0531}, {"scope": "e2e", "hardware": "SM107", "model": null, "shape": "H=12,Q=8", "batch... | null | 1.0202 |
flashinfer | 70bafa8014b3222f42732ba4fc68ed8b2fb594dd | 2026-09-29T22:31:30-07:00 | 5,684 | https://github.com/flashinfer-ai/flashinfer/pull/5684 | perf(cake_sampling): round-5 kernels (software-pipelined sampled pass, ballot-gated filter, two-level cluster select, two-warp fused tail, ept-32 streams, per-architecture stage-2/3 forms) and chain-aware dispatch (#5684) | perf(cake_sampling): round-5 kernels (software-pipelined sampled pass, ballot-gated filter, two-level cluster select, two-warp fused tail, ept-32 streams, per-architecture stage-2/3 forms) and chain-aware dispatch (#5684)
Developed by the **CAKE team**, the kernels in this PR **outperform**
the relevant **SOTA baselin... | csrc/cake_sampling/cake_sampling_binding.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2026 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2026 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/cake_sampling/cake_sampling_binding.cuh
+++ csrc/cake_sampling/cake_sampling_binding.cuh
@@ -17,13 +17,18 @@
// TVM-FFI binding for the frozen radix top-k / sparse top-p sampling bundle.
//
// The JIT module (flashinfer/jit/cake_sampling.py) generates a small .cu that defines:
-// CAKE_SAMPLING_BODY_FILE ... | 73 | 26 | 4 | [
"qwen"
] | [
"B200",
"BLACKWELL",
"GB300",
"H100",
"SM100",
"SM103",
"SM107",
"SM120",
"SM90"
] | [
"512 x",
"128 x",
"1.73x",
"3.44x",
"9.09x",
"1.02x",
"1.15x",
"1.75x",
"1.02x",
"1.09x"
] | Optimize this cuda kernel file from flashinfer (csrc/cake_sampling/cake_sampling_binding.cuh).
Goal: perf(cake_sampling): round-5 kernels (software-pipelined sampled pass, ballot-gated filter, two-level cluster select, two-warp fused tail, ept-32 streams, per-architecture stage-2/3 forms) and chain-aware dispatch
Targ... | Developed by the **CAKE team**, the kernels in this PR **outperform** the relevant **SOTA baselines at the time of merge** on the **vast majority of performance benchmark shapes**, matching them otherwise.
## Summary
Round 5 of the radix top-k -> sparse top-p -> sampling pipeline (`flashinfer.cake_sampling`): a new f... | [{"scope": "kernel", "hardware": "H100", "model": null, "shape": "V=256K,B=128", "batch_size": 128, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": null, "optimized": null, "stated_speedup": 0.81, "speedup": 0.81}, {"scope": "kernel", "hardware": "H100", "model": null, "shape": "V=256K,B=128",... | 0.915 | 1.0739 |
flashinfer | c3f7334d43072684c25456659551446f8a75120b | 2026-09-29T19:34:14-04:00 | 3,542 | https://github.com/flashinfer-ai/flashinfer/pull/3542 | perf(moe_bgmv): coalesced 128-bit loads for expand kernel (1.8–3× at batch≥256) (#3542) | perf(moe_bgmv): coalesced 128-bit loads for expand kernel (1.8–3× at batch≥256) (#3542)
## 📌 Description
Adds a faster, memory-coalesced kernel for the MoE BGMV expand op
(`moe_bgmv_expand_sliced`),
gated so it only runs where it's measured to win.
The op is memory-bound (each `(token, expert)` pair reads a `feat_o... | csrc/bgmv_moe/moe_bgmv_impl.cuh | cuda | Apache-2.0 | #pragma once
/*
* Multi-LoRA MoE BGMV CUDA Kernel Implementation.
*
* Two kernels:
* 1. Shrink: y[slice, pair, rank] += x[token] @ lora_a[expert, lora_id]
* - Compute-bound, uses async pipeline, RANK_TILE tiling, multi-pair blocking
* 2. Expand: y[token, feat] += shrink_out[pair, rank] @ lora_b[expert, ... | #pragma once
/*
* Multi-LoRA MoE BGMV CUDA Kernel Implementation.
*
* Two kernels:
* 1. Shrink: y[slice, pair, rank] += x[token] @ lora_a[expert, lora_id]
* - Compute-bound, uses async pipeline, RANK_TILE tiling, multi-pair blocking
* 2. Expand: y[token, feat] += shrink_out[pair, rank] @ lora_b[expert, ... | --- csrc/bgmv_moe/moe_bgmv_impl.cuh
+++ csrc/bgmv_moe/moe_bgmv_impl.cuh
@@ -474,6 +474,87 @@
}
// ============================================================
+// MoE BGMV Expand Kernel: coalesced 128-bit W loads.
+//
+// Each thread loads a contiguous 128-bit (uint4 = 8xbf16) chunk of W per pass, so a warp reads
+... | 100 | 0 | 1 | [] | [
"H200"
] | [
"3×",
"4×",
"1.0×",
"4.09×",
"0.98×",
"1.03×",
"2.05×",
"1.07×",
"1.98×",
"3.71×"
] | Optimize this cuda kernel file from flashinfer (csrc/bgmv_moe/moe_bgmv_impl.cuh).
Goal: perf(moe_bgmv): coalesced 128-bit loads for expand kernel (1.8–3× at batch≥256)
Target hardware: H200
Target models: unspecified
Current file:
```cuda
#pragma once
/*
* Multi-LoRA MoE BGMV CUDA Kernel Implementation.
*
* Two k... | ## 📌 Description
Adds a faster, memory-coalesced kernel for the MoE BGMV expand op (`moe_bgmv_expand_sliced`),
gated so it only runs where it's measured to win.
The op is memory-bound (each `(token, expert)` pair reads a `feat_out × feat_in` LoRA-B slice).
The new `moe_bgmv_expand_opt_kernel`:
- Loads W in **128-bit... | [{"scope": "e2e", "hardware": "H200", "model": null, "shape": null, "batch_size": 16, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 0.98, "speedup": 0.98}, {"scope": "e2e", "hardware": "H200", "model": null, "shape": null, "batch_size": 16, "metric":... | null | 1.98 |
flashinfer | 4301247a6938b8f010ee44569c64b80a2cd967b6 | 2026-09-29T13:09:03-07:00 | 5,687 | https://github.com/flashinfer-ai/flashinfer/pull/5687 | perf(cake_vsa_sm90): queue-scheduled persistent stage for long uniform plans (#5687) | perf(cake_vsa_sm90): queue-scheduled persistent stage for long uniform plans (#5687)
## Summary
Second persistent stage `attention_queue` for `backend="cake"` and
`backend="cake_cute"` (`VariableBlockSparseAttentionWrapper`, SM90):
every CTA runs its planned tile list except its last two tiles, which a
global tile qu... | flashinfer/experimental/cake_vsa_sm90_cute/__init__.py | cute_dsl | Apache-2.0 | # Copyright (c) 2026 by FlashInfer team.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in... | # Copyright (c) 2026 by FlashInfer team.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in... | --- flashinfer/experimental/cake_vsa_sm90_cute/__init__.py
+++ flashinfer/experimental/cake_vsa_sm90_cute/__init__.py
@@ -59,6 +59,7 @@
STAGES = (
"attention",
+ "attention_queue",
"small_k1",
"small_k3",
"small_k4", | 1 | 0 | 3 | [] | [
"H100",
"SM90"
] | [] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/experimental/cake_vsa_sm90_cute/__init__.py).
Goal: perf(cake_vsa_sm90): queue-scheduled persistent stage for long uniform plans
Target hardware: H100, SM90
Target models: unspecified
Current file:
```python
# Copyright (c) 2026 by FlashInfer team.
#
# Li... | > Developed by the **CAKE team**, the kernels in this PR **outperform** the relevant **SOTA baselines at the time of merge** on the **vast majority of performance benchmark shapes**, matching them otherwise.
Developed by the **CAKE team**, the SM90 VSA kernels in this PR outperform the reported reference baseline on n... | [{"scope": "e2e", "hardware": "H100", "model": null, "shape": "long video rows (m \u2265 32k)", "batch_size": null, "metric": "geomean performance", "unit": null, "higher_is_better": true, "baseline": 1.0, "optimized": 1.0045, "stated_speedup": null, "speedup": 1.0045}, {"scope": "e2e", "hardware": "H100", "model": nul... | null | 1.0005 |
flashinfer | 99c158c60469df0396cd9f982a093dfbb9fdcec2 | 2026-09-29T10:13:19-07:00 | 5,329 | https://github.com/flashinfer-ai/flashinfer/pull/5329 | perf: specialize persistent BatchAttention for equal KV strides (#5329) | perf: specialize persistent BatchAttention for equal KV strides (#5329)
<!-- .github/pull_request_template.md -->
## 📌 Description
Persistent BatchAttention computes separate K/V offsets even when their
strides match. Add an equal-stride specialization that shares offset
calculation and prefetch while preserving se... | csrc/batch_attention.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/batch_attention.cu
+++ csrc/batch_attention.cu
@@ -27,7 +27,7 @@
using tvm::ffi::Optional;
template <uint32_t CTA_TILE_Q_1, uint32_t CTA_TILE_Q_2, uint32_t HEAD_DIM_QK, uint32_t HEAD_DIM_VO,
- MaskMode MASK_MODE, typename AttentionVariant, typename Params>
+ MaskMode MASK_MODE, bool EQUAL... | 30 | 3 | 8 | [] | [
"B200",
"H100",
"SM100",
"SM90"
] | [
"1.0456x",
"1.0207x",
"1.0707x"
] | Optimize this cuda kernel file from flashinfer (csrc/batch_attention.cu).
Goal: perf: specialize persistent BatchAttention for equal KV strides
Target hardware: B200, H100, SM100, SM90
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License... | <!-- .github/pull_request_template.md -->
## 📌 Description
Persistent BatchAttention computes separate K/V offsets even when their strides match. Add an equal-stride specialization that shares offset calculation and prefetch while preserving separate K/V pointers and independent NVFP4 scale addressing.
The wrapper ... | [{"scope": "kernel", "hardware": "B200", "model": null, "shape": "NHD, page=16, hq=32, hk=8, dim=128, causal", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 23.936, "optimized": 23.872, "stated_speedup": null, "speedup": 1.0027}, {"scope": "kernel", "hardware": "H100", "mode... | 1.0249 | 1.0157 |
flashinfer | 99c158c60469df0396cd9f982a093dfbb9fdcec2 | 2026-09-29T10:13:19-07:00 | 5,329 | https://github.com/flashinfer-ai/flashinfer/pull/5329 | perf: specialize persistent BatchAttention for equal KV strides (#5329) | perf: specialize persistent BatchAttention for equal KV strides (#5329)
<!-- .github/pull_request_template.md -->
## 📌 Description
Persistent BatchAttention computes separate K/V offsets even when their
strides match. Add an equal-stride specialization that shares offset
calculation and prefetch while preserving se... | include/flashinfer/attention/persistent.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/attention/persistent.cuh
+++ include/flashinfer/attention/persistent.cuh
@@ -175,7 +175,7 @@
}
}
-template <typename KTraits_, typename Params_>
+template <typename KTraits_, typename Params_, bool EQUAL_KV_STRIDES>
struct BlockBatchPagedAttentionPersistent {
using KTraits = KTraits_;
... | 22 | 15 | 8 | [] | [
"B200",
"H100",
"SM100",
"SM90"
] | [
"1.0456x",
"1.0207x",
"1.0707x"
] | Optimize this cuda kernel file from flashinfer (include/flashinfer/attention/persistent.cuh).
Goal: perf: specialize persistent BatchAttention for equal KV strides
Target hardware: B200, H100, SM100, SM90
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed unde... | <!-- .github/pull_request_template.md -->
## 📌 Description
Persistent BatchAttention computes separate K/V offsets even when their strides match. Add an equal-stride specialization that shares offset calculation and prefetch while preserving separate K/V pointers and independent NVFP4 scale addressing.
The wrapper ... | [{"scope": "kernel", "hardware": "B200", "model": null, "shape": "NHD, page=16, hq=32, hk=8, dim=128, causal", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 23.936, "optimized": 23.872, "stated_speedup": null, "speedup": 1.0027}, {"scope": "kernel", "hardware": "H100", "mode... | 1.0249 | 1.0157 |
flashinfer | 43218730b7c957966ecca091cd800ba373171dc1 | 2026-09-29T02:55:14-07:00 | 5,674 | https://github.com/flashinfer-ai/flashinfer/pull/5674 | perf(cake_xqa): per-GQA-ratio tmem kernels and the cta_group::2 pair routes for experimental SM110 XQA (#5674) | perf(cake_xqa): per-GQA-ratio tmem kernels and the cta_group::2 pair routes for experimental SM110 XQA (#5674)
## Summary
Round 9 of the SM110 XQA D512 tree kernels: per-GQA-ratio traces for the
`tmem` routes (lifting the ratio-8 freeze of #5658) and a new `pair`
kernel family, the same tcgen05/TMEM schedule run as t... | flashinfer/experimental/sm110_xqa/csrc/sm110_xqa/sm_110a/sm110_xqa_tree_fp16_contiguous_tmem_binding.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES.
* SPDX-License-Identifier: Apache-2.0
*/
#include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_fp16.h>
#include <cstdint>
#include <cmath>
#include <initializer_list>
#include <limits>
#include "tvm_ffi_utils.h"
namespace {
using OptionalTensor = tvm::f... | /*
* Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES.
* SPDX-License-Identifier: Apache-2.0
*/
#include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_fp16.h>
#include <cstdint>
#include <cmath>
#include <initializer_list>
#include <limits>
#include "tvm_ffi_utils.h"
namespace {
using OptionalTensor = tvm::f... | --- flashinfer/experimental/sm110_xqa/csrc/sm110_xqa/sm_110a/sm110_xqa_tree_fp16_contiguous_tmem_binding.cu
+++ flashinfer/experimental/sm110_xqa/csrc/sm110_xqa/sm_110a/sm110_xqa_tree_fp16_contiguous_tmem_binding.cu
@@ -149,10 +149,119 @@
}
}
}
-
// 3D TMA descriptor for buffer 'Q' — compiled from the
// des... | 211 | 8 | 6 | [] | [
"SM110"
] | [
"1.069x",
"1.043x"
] | Optimize this cuda kernel file from flashinfer (flashinfer/experimental/sm110_xqa/csrc/sm110_xqa/sm_110a/sm110_xqa_tree_fp16_contiguous_tmem_binding.cu).
Goal: perf(cake_xqa): per-GQA-ratio tmem kernels and the cta_group::2 pair routes for experimental SM110 XQA
Target hardware: SM110
Target models: unspecified
Curre... | Developed by the **CAKE team**, the kernels in this PR **outperform** the relevant **SOTA baselines at the time of merge** on the **vast majority of performance benchmark shapes**, matching them otherwise.
## Summary
Round 9 of the SM110 XQA D512 tree kernels: per-GQA-ratio traces for the `tmem` routes (lifting the r... | [{"scope": "kernel", "hardware": "Thor", "model": null, "shape": "batch=1,q_len=20,q_heads=32,kv_heads=4,head_dim=512,capacity=256,causal", "batch_size": 1, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.049, "note": "FP8 page128 vs previous tmem ke... | 1.0485 | null |
flashinfer | 43218730b7c957966ecca091cd800ba373171dc1 | 2026-09-29T02:55:14-07:00 | 5,674 | https://github.com/flashinfer-ai/flashinfer/pull/5674 | perf(cake_xqa): per-GQA-ratio tmem kernels and the cta_group::2 pair routes for experimental SM110 XQA (#5674) | perf(cake_xqa): per-GQA-ratio tmem kernels and the cta_group::2 pair routes for experimental SM110 XQA (#5674)
## Summary
Round 9 of the SM110 XQA D512 tree kernels: per-GQA-ratio traces for the
`tmem` routes (lifting the ratio-8 freeze of #5658) and a new `pair`
kernel family, the same tcgen05/TMEM schedule run as t... | flashinfer/experimental/sm110_xqa/csrc/sm110_xqa/sm_110a/sm110_xqa_tree_fp16_paged_tmem_binding.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES.
* SPDX-License-Identifier: Apache-2.0
*/
#include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_fp16.h>
#include <cstdint>
#include <cmath>
#include <initializer_list>
#include <limits>
#include "tvm_ffi_utils.h"
namespace {
using OptionalTensor = tvm::f... | /*
* Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES.
* SPDX-License-Identifier: Apache-2.0
*/
#include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_fp16.h>
#include <cstdint>
#include <cmath>
#include <initializer_list>
#include <limits>
#include "tvm_ffi_utils.h"
namespace {
using OptionalTensor = tvm::f... | --- flashinfer/experimental/sm110_xqa/csrc/sm110_xqa/sm_110a/sm110_xqa_tree_fp16_paged_tmem_binding.cu
+++ flashinfer/experimental/sm110_xqa/csrc/sm110_xqa/sm_110a/sm110_xqa_tree_fp16_paged_tmem_binding.cu
@@ -149,10 +149,119 @@
}
}
}
-
// 3D TMA descriptor for buffer 'Q' — compiled from the
// descriptor's ... | 211 | 8 | 6 | [] | [
"SM110"
] | [
"1.069x",
"1.043x"
] | Optimize this cuda kernel file from flashinfer (flashinfer/experimental/sm110_xqa/csrc/sm110_xqa/sm_110a/sm110_xqa_tree_fp16_paged_tmem_binding.cu).
Goal: perf(cake_xqa): per-GQA-ratio tmem kernels and the cta_group::2 pair routes for experimental SM110 XQA
Target hardware: SM110
Target models: unspecified
Current fi... | Developed by the **CAKE team**, the kernels in this PR **outperform** the relevant **SOTA baselines at the time of merge** on the **vast majority of performance benchmark shapes**, matching them otherwise.
## Summary
Round 9 of the SM110 XQA D512 tree kernels: per-GQA-ratio traces for the `tmem` routes (lifting the r... | [{"scope": "kernel", "hardware": "Thor", "model": null, "shape": "batch=1,q_len=20,q_heads=32,kv_heads=4,head_dim=512,capacity=256,causal", "batch_size": 1, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.049, "note": "FP8 page128 vs previous tmem ke... | 1.0485 | null |
flashinfer | 43218730b7c957966ecca091cd800ba373171dc1 | 2026-09-29T02:55:14-07:00 | 5,674 | https://github.com/flashinfer-ai/flashinfer/pull/5674 | perf(cake_xqa): per-GQA-ratio tmem kernels and the cta_group::2 pair routes for experimental SM110 XQA (#5674) | perf(cake_xqa): per-GQA-ratio tmem kernels and the cta_group::2 pair routes for experimental SM110 XQA (#5674)
## Summary
Round 9 of the SM110 XQA D512 tree kernels: per-GQA-ratio traces for the
`tmem` routes (lifting the ratio-8 freeze of #5658) and a new `pair`
kernel family, the same tcgen05/TMEM schedule run as t... | flashinfer/experimental/sm110_xqa/csrc/sm110_xqa/sm_110a/sm110_xqa_tree_fp8_contiguous_tmem_binding.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES.
* SPDX-License-Identifier: Apache-2.0
*/
#include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_fp16.h>
#include <cstdint>
#include <cmath>
#include <initializer_list>
#include <limits>
#include "tvm_ffi_utils.h"
namespace {
using OptionalTensor = tvm::f... | /*
* Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES.
* SPDX-License-Identifier: Apache-2.0
*/
#include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_fp16.h>
#include <cstdint>
#include <cmath>
#include <initializer_list>
#include <limits>
#include "tvm_ffi_utils.h"
namespace {
using OptionalTensor = tvm::f... | --- flashinfer/experimental/sm110_xqa/csrc/sm110_xqa/sm_110a/sm110_xqa_tree_fp8_contiguous_tmem_binding.cu
+++ flashinfer/experimental/sm110_xqa/csrc/sm110_xqa/sm_110a/sm110_xqa_tree_fp8_contiguous_tmem_binding.cu
@@ -149,10 +149,119 @@
}
}
}
-
// 3D TMA descriptor for buffer 'Q' — compiled from the
// descr... | 211 | 8 | 6 | [] | [
"SM110"
] | [
"1.069x",
"1.043x"
] | Optimize this cuda kernel file from flashinfer (flashinfer/experimental/sm110_xqa/csrc/sm110_xqa/sm_110a/sm110_xqa_tree_fp8_contiguous_tmem_binding.cu).
Goal: perf(cake_xqa): per-GQA-ratio tmem kernels and the cta_group::2 pair routes for experimental SM110 XQA
Target hardware: SM110
Target models: unspecified
Curren... | Developed by the **CAKE team**, the kernels in this PR **outperform** the relevant **SOTA baselines at the time of merge** on the **vast majority of performance benchmark shapes**, matching them otherwise.
## Summary
Round 9 of the SM110 XQA D512 tree kernels: per-GQA-ratio traces for the `tmem` routes (lifting the r... | [{"scope": "kernel", "hardware": "Thor", "model": null, "shape": "batch=1,q_len=20,q_heads=32,kv_heads=4,head_dim=512,capacity=256,causal", "batch_size": 1, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.049, "note": "FP8 page128 vs previous tmem ke... | 1.0485 | null |
flashinfer | 43218730b7c957966ecca091cd800ba373171dc1 | 2026-09-29T02:55:14-07:00 | 5,674 | https://github.com/flashinfer-ai/flashinfer/pull/5674 | perf(cake_xqa): per-GQA-ratio tmem kernels and the cta_group::2 pair routes for experimental SM110 XQA (#5674) | perf(cake_xqa): per-GQA-ratio tmem kernels and the cta_group::2 pair routes for experimental SM110 XQA (#5674)
## Summary
Round 9 of the SM110 XQA D512 tree kernels: per-GQA-ratio traces for the
`tmem` routes (lifting the ratio-8 freeze of #5658) and a new `pair`
kernel family, the same tcgen05/TMEM schedule run as t... | flashinfer/experimental/sm110_xqa/csrc/sm110_xqa/sm_110a/sm110_xqa_tree_fp8_paged_tmem_binding.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES.
* SPDX-License-Identifier: Apache-2.0
*/
#include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_fp16.h>
#include <cstdint>
#include <cmath>
#include <initializer_list>
#include <limits>
#include "tvm_ffi_utils.h"
namespace {
using OptionalTensor = tvm::f... | /*
* Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES.
* SPDX-License-Identifier: Apache-2.0
*/
#include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_fp16.h>
#include <cstdint>
#include <cmath>
#include <initializer_list>
#include <limits>
#include "tvm_ffi_utils.h"
namespace {
using OptionalTensor = tvm::f... | --- flashinfer/experimental/sm110_xqa/csrc/sm110_xqa/sm_110a/sm110_xqa_tree_fp8_paged_tmem_binding.cu
+++ flashinfer/experimental/sm110_xqa/csrc/sm110_xqa/sm_110a/sm110_xqa_tree_fp8_paged_tmem_binding.cu
@@ -149,10 +149,119 @@
}
}
}
-
// 3D TMA descriptor for buffer 'Q' — compiled from the
// descriptor's st... | 211 | 8 | 6 | [] | [
"SM110"
] | [
"1.069x",
"1.043x"
] | Optimize this cuda kernel file from flashinfer (flashinfer/experimental/sm110_xqa/csrc/sm110_xqa/sm_110a/sm110_xqa_tree_fp8_paged_tmem_binding.cu).
Goal: perf(cake_xqa): per-GQA-ratio tmem kernels and the cta_group::2 pair routes for experimental SM110 XQA
Target hardware: SM110
Target models: unspecified
Current fil... | Developed by the **CAKE team**, the kernels in this PR **outperform** the relevant **SOTA baselines at the time of merge** on the **vast majority of performance benchmark shapes**, matching them otherwise.
## Summary
Round 9 of the SM110 XQA D512 tree kernels: per-GQA-ratio traces for the `tmem` routes (lifting the r... | [{"scope": "kernel", "hardware": "Thor", "model": null, "shape": "batch=1,q_len=20,q_heads=32,kv_heads=4,head_dim=512,capacity=256,causal", "batch_size": 1, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.049, "note": "FP8 page128 vs previous tmem ke... | 1.0485 | null |
flashinfer | 436526608e05eda8925091a078cf8616382bf51e | 2026-09-28T17:47:59-07:00 | 5,636 | https://github.com/flashinfer-ai/flashinfer/pull/5636 | perf(cake_sampling): round-4 kernels (streaming candidate-list stage 1, fused small-k tail, host-decided PDL trigger) and k-aware dispatch (#5636) | perf(cake_sampling): round-4 kernels (streaming candidate-list stage 1, fused small-k tail, host-decided PDL trigger) and k-aware dispatch (#5636)
Developed by the **CAKE team**, the kernels in this PR **outperform**
the relevant **SOTA baselines at the time of merge** on the **vast
majority of performance benchmark s... | csrc/cake_sampling/cake_sampling_binding.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2026 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2026 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/cake_sampling/cake_sampling_binding.cuh
+++ csrc/cake_sampling/cake_sampling_binding.cuh
@@ -21,6 +21,7 @@
// CAKE_SAMPLING_MIN_MAJOR / CAKE_SAMPLING_MIN_MINOR oldest compute capability the frozen body
// supports (manifest min_compute_capability)
// ... | 119 | 9 | 4 | [] | [
"B200",
"BLACKWELL",
"GB300",
"H100",
"HOPPER",
"SM100",
"SM103",
"SM107",
"SM120",
"SM90"
] | [
"2.5x",
"128 x",
"1.65x",
"3.04x",
"7.50x",
"0.98x",
"1.11x",
"1.56x",
"0.98x",
"1.15x"
] | Optimize this cuda kernel file from flashinfer (csrc/cake_sampling/cake_sampling_binding.cuh).
Goal: perf(cake_sampling): round-4 kernels (streaming candidate-list stage 1, fused small-k tail, host-decided PDL trigger) and k-aware dispatch
Target hardware: B200, BLACKWELL, GB300, H100, HOPPER, SM100, SM103, SM107, SM1... | Developed by the **CAKE team**, the kernels in this PR **outperform** the relevant **SOTA baselines at the time of merge** on the **vast majority of performance benchmark shapes**, matching them otherwise.
## Summary
Round 4 of the radix top-k -> sparse top-p -> sampling pipeline (`flashinfer.cake_sampling`): a new f... | [{"scope": "kernel", "hardware": "R200", "model": null, "shape": "B=128,V=256K", "batch_size": 128, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 58.6, "optimized": 56.0, "stated_speedup": null, "speedup": 1.0464}, {"scope": "kernel", "hardware": "H100", "model": null, "shape": "V=151936,B=1... | 1.1082 | 1.0233 |
flashinfer | 97b3bd80f0b9869b591a6732d871e6d09549388c | 2026-09-27T12:17:08-07:00 | 5,609 | https://github.com/flashinfer-ai/flashinfer/pull/5609 | perf(cake_mm_fp4): faster NVFP4 per-token path (register-resident per-token quantize, per-tile alpha epilogue, low-M split-K, L2 eviction policies) (#5609) | perf(cake_mm_fp4): faster NVFP4 per-token path (register-resident per-token quantize, per-tile alpha epilogue, low-M split-K, L2 eviction policies) (#5609)
<!-- .github/pull_request_template.md -->
## 📌 Description
Follow-up to #5504 (per-token alpha for NVFP4 `mm_fp4` + `out_scale`
fold in per-token `nvfp4_quantiz... | flashinfer/gemm/gemm_mm_fp4_cute_dsl.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2026 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2026 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/gemm/gemm_mm_fp4_cute_dsl.py
+++ flashinfer/gemm/gemm_mm_fp4_cute_dsl.py
@@ -139,6 +139,7 @@
enable_pdl,
out_dtype,
per_token_alpha,
+ l2_policy,
) = cache_key
# On SM107 the use_tma_store slot is repurposed to carry the Rubin kernel
# shape (inst_m, inst_... | 61 | 4 | 5 | [] | [
"B200",
"GB300",
"SM100",
"SM103"
] | [
"7168x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/gemm/gemm_mm_fp4_cute_dsl.py).
Goal: perf(cake_mm_fp4): faster NVFP4 per-token path (register-resident per-token quantize, per-tile alpha epilogue, low-M split-K, L2 eviction policies)
Target hardware: B200, GB300, SM100, SM103
Target models: unspecified
... | Developed by the **CAKE team**, the kernels in this PR **outperform** the relevant **SOTA baselines at the time of merge** on the **vast majority of performance benchmark shapes**, matching them otherwise.
<!-- .github/pull_request_template.md -->
## 📌 Description
Follow-up to #5504 (per-token alpha for NVFP4 `mm_f... | [] | null | null |
flashinfer | 97b3bd80f0b9869b591a6732d871e6d09549388c | 2026-09-27T12:17:08-07:00 | 5,609 | https://github.com/flashinfer-ai/flashinfer/pull/5609 | perf(cake_mm_fp4): faster NVFP4 per-token path (register-resident per-token quantize, per-tile alpha epilogue, low-M split-K, L2 eviction policies) (#5609) | perf(cake_mm_fp4): faster NVFP4 per-token path (register-resident per-token quantize, per-tile alpha epilogue, low-M split-K, L2 eviction policies) (#5609)
<!-- .github/pull_request_template.md -->
## 📌 Description
Follow-up to #5504 (per-token alpha for NVFP4 `mm_fp4` + `out_scale`
fold in per-token `nvfp4_quantiz... | flashinfer/gemm/kernels/dense_blockscaled_gemm_sm100.py | cute_dsl | BSD-3-Clause | # Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Identifier: BSD-3-Clause
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# 1. Redistributions of source code must retain the abov... | # Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Identifier: BSD-3-Clause
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# 1. Redistributions of source code must retain the abov... | --- flashinfer/gemm/kernels/dense_blockscaled_gemm_sm100.py
+++ flashinfer/gemm/kernels/dense_blockscaled_gemm_sm100.py
@@ -38,13 +38,85 @@
import cutlass.pipeline as pipeline
import cutlass.utils as utils
import cutlass.utils.blackwell_helpers as sm100_utils
+from cutlass._mlir.dialects import llvm
+from cutlass.cu... | 207 | 21 | 5 | [] | [
"B200",
"GB300",
"SM100",
"SM103"
] | [
"7168x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/gemm/kernels/dense_blockscaled_gemm_sm100.py).
Goal: perf(cake_mm_fp4): faster NVFP4 per-token path (register-resident per-token quantize, per-tile alpha epilogue, low-M split-K, L2 eviction policies)
Target hardware: B200, GB300, SM100, SM103
Target model... | Developed by the **CAKE team**, the kernels in this PR **outperform** the relevant **SOTA baselines at the time of merge** on the **vast majority of performance benchmark shapes**, matching them otherwise.
<!-- .github/pull_request_template.md -->
## 📌 Description
Follow-up to #5504 (per-token alpha for NVFP4 `mm_f... | [] | null | null |
flashinfer | 97b3bd80f0b9869b591a6732d871e6d09549388c | 2026-09-27T12:17:08-07:00 | 5,609 | https://github.com/flashinfer-ai/flashinfer/pull/5609 | perf(cake_mm_fp4): faster NVFP4 per-token path (register-resident per-token quantize, per-tile alpha epilogue, low-M split-K, L2 eviction policies) (#5609) | perf(cake_mm_fp4): faster NVFP4 per-token path (register-resident per-token quantize, per-tile alpha epilogue, low-M split-K, L2 eviction policies) (#5609)
<!-- .github/pull_request_template.md -->
## 📌 Description
Follow-up to #5504 (per-token alpha for NVFP4 `mm_fp4` + `out_scale`
fold in per-token `nvfp4_quantiz... | flashinfer/gemm/kernels/dense_blockscaled_gemm_sm100_splitk.py | cute_dsl | BSD-3-Clause | # Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Identifier: BSD-3-Clause
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# 1. Redistributions of source code must retain the abov... | # Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Identifier: BSD-3-Clause
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# 1. Redistributions of source code must retain the abov... | --- flashinfer/gemm/kernels/dense_blockscaled_gemm_sm100_splitk.py
+++ flashinfer/gemm/kernels/dense_blockscaled_gemm_sm100_splitk.py
@@ -44,6 +44,7 @@
from cutlass.pipeline import PipelineTmaUmma, PipelineUmmaAsync
from cutlass import Float32, Int32
from cutlass._mlir.dialects import llvm
+from .dense_blockscaled_g... | 174 | 7 | 5 | [] | [
"B200",
"GB300",
"SM100",
"SM103"
] | [
"7168x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/gemm/kernels/dense_blockscaled_gemm_sm100_splitk.py).
Goal: perf(cake_mm_fp4): faster NVFP4 per-token path (register-resident per-token quantize, per-tile alpha epilogue, low-M split-K, L2 eviction policies)
Target hardware: B200, GB300, SM100, SM103
Targe... | Developed by the **CAKE team**, the kernels in this PR **outperform** the relevant **SOTA baselines at the time of merge** on the **vast majority of performance benchmark shapes**, matching them otherwise.
<!-- .github/pull_request_template.md -->
## 📌 Description
Follow-up to #5504 (per-token alpha for NVFP4 `mm_f... | [] | null | null |
flashinfer | 97b3bd80f0b9869b591a6732d871e6d09549388c | 2026-09-27T12:17:08-07:00 | 5,609 | https://github.com/flashinfer-ai/flashinfer/pull/5609 | perf(cake_mm_fp4): faster NVFP4 per-token path (register-resident per-token quantize, per-tile alpha epilogue, low-M split-K, L2 eviction policies) (#5609) | perf(cake_mm_fp4): faster NVFP4 per-token path (register-resident per-token quantize, per-tile alpha epilogue, low-M split-K, L2 eviction policies) (#5609)
<!-- .github/pull_request_template.md -->
## 📌 Description
Follow-up to #5504 (per-token alpha for NVFP4 `mm_fp4` + `out_scale`
fold in per-token `nvfp4_quantiz... | flashinfer/quantization/kernels/nvfp4_quantize.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/quantization/kernels/nvfp4_quantize.py
+++ flashinfer/quantization/kernels/nvfp4_quantize.py
@@ -77,6 +77,8 @@
bfloat2x8_to_e2m1x16_packed,
process_nvfp4_block_half,
process_nvfp4_block_bfloat,
+ _quantize_nvfp4_from_h2x8_bfloat,
+ _quantize_nvfp4_from_h2x8_half,
process_nvfp4_b... | 217 | 13 | 5 | [] | [
"B200",
"GB300",
"SM100",
"SM103"
] | [
"7168x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/quantization/kernels/nvfp4_quantize.py).
Goal: perf(cake_mm_fp4): faster NVFP4 per-token path (register-resident per-token quantize, per-tile alpha epilogue, low-M split-K, L2 eviction policies)
Target hardware: B200, GB300, SM100, SM103
Target models: uns... | Developed by the **CAKE team**, the kernels in this PR **outperform** the relevant **SOTA baselines at the time of merge** on the **vast majority of performance benchmark shapes**, matching them otherwise.
<!-- .github/pull_request_template.md -->
## 📌 Description
Follow-up to #5504 (per-token alpha for NVFP4 `mm_f... | [] | null | null |
flashinfer | 316a70578a90749113ab375e9fa88b323034f9a0 | 2026-09-26T14:00:47-07:00 | 5,574 | https://github.com/flashinfer-ai/flashinfer/pull/5574 | perf(cake_warp_decode): route the SM103 Qwen3-30B-A3B num_tokens=8 warp-decode row onto the fused route-pack K256 path (#5574) | perf(cake_warp_decode): route the SM103 Qwen3-30B-A3B num_tokens=8 warp-decode row onto the fused route-pack K256 path (#5574)
## NVFP4 warp-decode: sm_103a Qwen3-30B-A3B num_tokens 8 joins the fused
route-pack rows
Policy-only update of the public-model NVFP4 warp-decode portfolio
(SM100 / SM103, num_tokens 1–32). O... | csrc/fused_moe/warp_decode/cake_warp_decode_contract.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required... | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required... | --- csrc/fused_moe/warp_decode/cake_warp_decode_contract.cuh
+++ csrc/fused_moe/warp_decode/cake_warp_decode_contract.cuh
@@ -139,11 +139,11 @@
}
// Rows whose route packing runs inside the FC1 prologue (RoutePacker::kFusedFc1).
-// Only the Qwen3-30B geometry participates: sm_103a T9..T32 and sm_100a T10..T32
-// ... | 20 | 7 | 2 | [
"qwen"
] | [
"B300",
"SM100",
"SM103"
] | [] | Optimize this cuda kernel file from flashinfer (csrc/fused_moe/warp_decode/cake_warp_decode_contract.cuh).
Goal: perf(cake_warp_decode): route the SM103 Qwen3-30B-A3B num_tokens=8 warp-decode row onto the fused route-pack K256 path
Target hardware: B300, SM100, SM103
Target models: qwen
Current file:
```cuda
/*
* Co... | Developed by the **CAKE team**, the kernels in this PR **outperform** the relevant **SOTA baselines at the time of merge** on the **vast majority of performance benchmark shapes**, matching them otherwise.
## NVFP4 warp-decode: sm_103a Qwen3-30B-A3B num_tokens 8 joins the fused route-pack rows
Policy-only update of t... | [] | null | null |
flashinfer | ea728cb558c32a3c58ec8fbd5a154ff676b9ab70 | 2026-09-23T16:49:21-07:00 | 5,431 | https://github.com/flashinfer-ai/flashinfer/pull/5431 | perf(cake_megamoe_topk_reduce): regenerate the SM100a reducer from the current Cake exporter (#5431) | perf(cake_megamoe_topk_reduce): regenerate the SM100a reducer from the current Cake exporter (#5431)
## 📌 Description
Regenerate
`csrc/cake_megamoe_topk_reduce/cake_megamoe_topk_reduce_kernels.cu` and
its `manifest.json` from the current Cake exporter so the public bytes
are reproducible with the exporter's `--check... | csrc/cake_megamoe_topk_reduce/cake_megamoe_topk_reduce_kernels.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2026 by FlashInfer team.
* SPDX-License-Identifier: Apache-2.0
*/
typedef signed char int8_t;
typedef unsigned char uint8_t;
typedef unsigned short uint16_t;
typedef unsigned int uint32_t;
#if defined(__CUDACC_RTC__)
typedef unsigned long long uint64_t;
#else
typedef unsigne... | /*
* Copyright (c) 2026 by FlashInfer team.
* SPDX-License-Identifier: Apache-2.0
*/
typedef signed char int8_t;
typedef unsigned char uint8_t;
typedef unsigned short uint16_t;
typedef unsigned int uint32_t;
#if defined(__CUDACC_RTC__)
typedef unsigned long long uint64_t;
#else
typedef unsigne... | --- csrc/cake_megamoe_topk_reduce/cake_megamoe_topk_reduce_kernels.cu
+++ csrc/cake_megamoe_topk_reduce/cake_megamoe_topk_reduce_kernels.cu
@@ -40,10 +40,6 @@
return result;
}
-#define CAKE_INF CUDART_INF_F
-#define NUM_MAIN_STAGES 1
-#define THREADS 256
-
#include <math_constants.h>
__device__ __forceinlin... | 114 | 109 | 2 | [] | [
"B200",
"CPU",
"SM100"
] | [] | Optimize this cuda kernel file from flashinfer (csrc/cake_megamoe_topk_reduce/cake_megamoe_topk_reduce_kernels.cu).
Goal: perf(cake_megamoe_topk_reduce): regenerate the SM100a reducer from the current Cake exporter
Target hardware: B200, CPU, SM100
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) ... | > Developed by the **CAKE team**, the kernels in this PR **outperform** the relevant **SOTA baselines at the time of merge** on the **vast majority of performance benchmark shapes**, matching them otherwise.
This PR refreshes the generated-source packaging for the **CAKE team's** existing MegaMoE reducer; the kernel b... | [] | null | null |
flashinfer | 87f80a75557b8ff4db77288e39ed40b6aecb9684 | 2026-09-23T00:16:13+08:00 | 5,125 | https://github.com/flashinfer-ai/flashinfer/pull/5125 | fix(cute-dsl): use has_side_effects to prevent wrong llvm optimisation (#5125) | fix(cute-dsl): use has_side_effects to prevent wrong llvm optimisation (#5125)
PLEASE ANALYSE THE ATTACHED ZIP FILES, WHICH IS SELF-CONTAINED. (You can
ask an agent to do it.)
[flashinfer-inline-asm-evidence.zip](https://github.com/user-attachments/files/32085057/flashinfer-inline-asm-evidence.zip)
# [CuTeDSL] Sha... | flashinfer/cute_dsl/fp4_common.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/cute_dsl/fp4_common.py
+++ flashinfer/cute_dsl/fp4_common.py
@@ -318,7 +318,7 @@
[Int32(smem_addr).ir_value(loc=loc, ip=ip)],
"ld.shared.v2.u32 {$0, $1}, [$2];",
"=r,=r,r",
- has_side_effects=False,
+ has_side_effects=True,
is_align_stack=False,
... | 2 | 2 | 1 | [] | [
"B200",
"SM80"
] | [] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/cute_dsl/fp4_common.py).
Goal: fix(cute-dsl): use has_side_effects to prevent wrong llvm optimisation
Target hardware: B200, SM80
Target models: unspecified
Current file:
```python
"""
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache Lice... | PLEASE ANALYSE THE ATTACHED ZIP FILES, WHICH IS SELF-CONTAINED. (You can ask an agent to do it.)
[flashinfer-inline-asm-evidence.zip](https://github.com/user-attachments/files/32085057/flashinfer-inline-asm-evidence.zip)
# [CuTeDSL] Shared-load inline-asm helpers omit effects, allowing stale-load reuse
`ld_shared_v... | [] | null | null |
flashinfer | dc04f50c9aa3eabcdaa5feb0934edb3d85e9529a | 2026-09-18T18:31:07-07:00 | 5,288 | https://github.com/flashinfer-ai/flashinfer/pull/5288 | perf(topk_varlen, attn_scores): upstream sync — gvr_2 hint-free engines (TRT-LLM #18410) + paged-MQA relu epilogue (DKG !27837) (#5288) | perf(topk_varlen, attn_scores): upstream sync — gvr_2 hint-free engines (TRT-LLM #18410) + paged-MQA relu epilogue (DKG !27837) (#5288)
<!-- .github/pull_request_template.md kept; sections filled -->
## 📌 Description
Upstream sync of two kernel families FlashInfer vendors from NVIDIA
sources, with every change measu... | flashinfer/topk_varlen/kernels/radix_topk.py | cute_dsl | Apache-2.0 | # Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applic... | # Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applic... | --- flashinfer/topk_varlen/kernels/radix_topk.py
+++ flashinfer/topk_varlen/kernels/radix_topk.py
@@ -1163,6 +1163,11 @@
# next_n adjustment is in token units, so it must happen before
# dividing by compress_ratio; when compress_ratio=1 this is a no-op.
length = (seq_len - next_n ... | 5 | 0 | 8 | [] | [
"A100",
"B200",
"B300",
"H100",
"L40S",
"RTX5080",
"SM100",
"SM103",
"SM107"
] | [] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/topk_varlen/kernels/radix_topk.py).
Goal: perf(topk_varlen, attn_scores): upstream sync — gvr_2 hint-free engines (TRT-LLM #18410) + paged-MQA relu epilogue (DKG !27837)
Target hardware: A100, B200, B300, H100, L40S, RTX5080, SM100, SM103, SM107
Target mod... | <!-- .github/pull_request_template.md kept; sections filled -->
## 📌 Description
Upstream sync of two kernel families FlashInfer vendors from NVIDIA sources, with every change measured same-node against the current tree before adoption (and two upstream heuristics rejected on measurement).
**1. Paged-MQA logits (`at... | [{"scope": "kernel", "hardware": "B200", "model": null, "shape": "K=2048, n_rows<=1024", "batch_size": null, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 1.1, "optimized": 0.85, "stated_speedup": null, "speedup": 1.2941}, {"scope": "kernel", "hardware": "B200", "model": null, "shape": "VPT>... | 1.145 | null |
flashinfer | dc04f50c9aa3eabcdaa5feb0934edb3d85e9529a | 2026-09-18T18:31:07-07:00 | 5,288 | https://github.com/flashinfer-ai/flashinfer/pull/5288 | perf(topk_varlen, attn_scores): upstream sync — gvr_2 hint-free engines (TRT-LLM #18410) + paged-MQA relu epilogue (DKG !27837) (#5288) | perf(topk_varlen, attn_scores): upstream sync — gvr_2 hint-free engines (TRT-LLM #18410) + paged-MQA relu epilogue (DKG !27837) (#5288)
<!-- .github/pull_request_template.md kept; sections filled -->
## 📌 Description
Upstream sync of two kernel families FlashInfer vendors from NVIDIA
sources, with every change measu... | flashinfer/topk_varlen/topk_varlen.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/topk_varlen/topk_varlen.py
+++ flashinfer/topk_varlen/topk_varlen.py
@@ -34,9 +34,9 @@
ladders; TRT-LLM PR #17821 port). Requires a datacentre
Blackwell-class GPU (sm_100/103, or Rubin sm_107),
nvidia-cutlass-dsl and fp32 logits; ``p... | 67 | 42 | 8 | [] | [
"A100",
"B200",
"B300",
"H100",
"L40S",
"RTX5080",
"SM100",
"SM103",
"SM107"
] | [] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/topk_varlen/topk_varlen.py).
Goal: perf(topk_varlen, attn_scores): upstream sync — gvr_2 hint-free engines (TRT-LLM #18410) + paged-MQA relu epilogue (DKG !27837)
Target hardware: A100, B200, B300, H100, L40S, RTX5080, SM100, SM103, SM107
Target models: un... | <!-- .github/pull_request_template.md kept; sections filled -->
## 📌 Description
Upstream sync of two kernel families FlashInfer vendors from NVIDIA sources, with every change measured same-node against the current tree before adoption (and two upstream heuristics rejected on measurement).
**1. Paged-MQA logits (`at... | [{"scope": "kernel", "hardware": "B200", "model": null, "shape": "K=2048, n_rows<=1024", "batch_size": null, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 1.1, "optimized": 0.85, "stated_speedup": null, "speedup": 1.2941}, {"scope": "kernel", "hardware": "B200", "model": null, "shape": "VPT>... | 1.145 | null |
flashinfer | d207165a34290f6464cd33a233e8fe067b0f4fee | 2026-09-18T22:00:55+03:00 | 4,825 | https://github.com/flashinfer-ai/flashinfer/pull/4825 | perf(cute-dsl): skip inactive pages in windowed decode (#4825) | perf(cute-dsl): skip inactive pages in windowed decode (#4825)
<!-- .github/pull_request_template.md -->
## 📌 Description
Skip whole paged-KV pages that are entirely before a sliding-window
decode
request's earliest active key. The kernel advances the page-table origin
and
rebases the effective sequence length befo... | flashinfer/cute_dsl/attention/gqa_decode_paged.py | cute_dsl | BSD-3-Clause | # Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Identifier: BSD-3-Clause
import math
from typing import Literal, Type, cast
from functools import partial
import cuda.bindings.driver as cuda
import cutlass
import cutlass.cute as cute
from cutlass.cute.nvgpu import tcgen05, Op... | # Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Identifier: BSD-3-Clause
import math
from typing import Literal, Type, cast
from functools import partial
import cuda.bindings.driver as cuda
import cutlass
import cutlass.cute as cute
from cutlass.cute.nvgpu import tcgen05, Op... | --- flashinfer/cute_dsl/attention/gqa_decode_paged.py
+++ flashinfer/cute_dsl/attention/gqa_decode_paged.py
@@ -956,12 +956,28 @@
# Runtime control flow
if cutlass.const_expr(is_varlen):
seqlen = seqlen_smem[0]
- page_count = cute.ceil_div(seqlen, page_size)
table_... | 20 | 4 | 1 | [
"kimi"
] | [
"B300",
"SM103"
] | [] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/cute_dsl/attention/gqa_decode_paged.py).
Goal: perf(cute-dsl): skip inactive pages in windowed decode
Target hardware: B300, SM103
Target models: kimi
Current file:
```python
# Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPD... | <!-- .github/pull_request_template.md -->
## 📌 Description
Skip whole paged-KV pages that are entirely before a sliding-window decode
request's earliest active key. The kernel advances the page-table origin and
rebases the effective sequence length before constructing page and sequence
tile counts; the existing mask... | [{"scope": "kernel", "hardware": "NVIDIA B300", "model": null, "shape": "Page=16,K=1024", "batch_size": 16, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 42.185, "optimized": 42.237, "stated_speedup": null, "speedup": 0.9988}, {"scope": "kernel", "hardware": "NVIDIA B300", "model": null, "sh... | 3.6424 | null |
flashinfer | 012542c8523b7e0034fb24a65f0599c6f60b56ff | 2026-09-18T10:09:28-07:00 | 5,305 | https://github.com/flashinfer-ai/flashinfer/pull/5305 | perf(norm): tune CuTe-DSL qk_rmsnorm and fused_add_rmsnorm_quant tiling for SM100/103/107 (#5305) | perf(norm): tune CuTe-DSL qk_rmsnorm and fused_add_rmsnorm_quant tiling for SM100/103/107 (#5305)
<!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re
needed. -->
Two tiling adjustments to the CuTe-DSL norm kernels on Blackwell and
Rubin... | flashinfer/norm/kernels/fused_add_rmsnorm.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/norm/kernels/fused_add_rmsnorm.py
+++ flashinfer/norm/kernels/fused_add_rmsnorm.py
@@ -47,7 +47,7 @@
get_cutlass_dtype,
)
-from .rmsnorm import RMSNormKernel
+from .rmsnorm import _LATENCY_BOUND_SMS, RMSNormKernel
# ============================================================================... | 8 | 2 | 2 | [] | [
"B200",
"BLACKWELL",
"SM100",
"SM103",
"SM107"
] | [
"1.00×",
"1.41×",
"1.70×",
"1.09×",
"1.75×",
"2.13×",
"1.18×",
"1.93×",
"2.10×",
"1.35×"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/norm/kernels/fused_add_rmsnorm.py).
Goal: perf(norm): tune CuTe-DSL qk_rmsnorm and fused_add_rmsnorm_quant tiling for SM100/103/107
Target hardware: B200, BLACKWELL, SM100, SM103, SM107
Target models: unspecified
Current file:
```python
"""
Copyright (c) ... | <!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->
Two tiling adjustments to the CuTe-DSL norm kernels on Blackwell and Rubin (SM100, SM103, SM107), gated on an explicit architecture list (`_LATENCY_BOUND_SMS`) so all other ... | [{"scope": "kernel", "hardware": "SM107", "model": null, "shape": "heads=32,head_dim=64", "batch_size": 512, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.0, "speedup": 1.0}, {"scope": "kernel", "hardware": "SM107", "model": null, "shape": "heads=3... | 1.135 | null |
flashinfer | 012542c8523b7e0034fb24a65f0599c6f60b56ff | 2026-09-18T10:09:28-07:00 | 5,305 | https://github.com/flashinfer-ai/flashinfer/pull/5305 | perf(norm): tune CuTe-DSL qk_rmsnorm and fused_add_rmsnorm_quant tiling for SM100/103/107 (#5305) | perf(norm): tune CuTe-DSL qk_rmsnorm and fused_add_rmsnorm_quant tiling for SM100/103/107 (#5305)
<!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re
needed. -->
Two tiling adjustments to the CuTe-DSL norm kernels on Blackwell and
Rubin... | flashinfer/norm/kernels/rmsnorm.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/norm/kernels/rmsnorm.py
+++ flashinfer/norm/kernels/rmsnorm.py
@@ -419,6 +419,11 @@
# =============================================================================
+# Architectures where the norm kernels are bound by bytes in flight per SM;
+# the tiling adjustments below apply only to these.
+_LATE... | 30 | 4 | 2 | [] | [
"B200",
"BLACKWELL",
"SM100",
"SM103",
"SM107"
] | [
"1.00×",
"1.41×",
"1.70×",
"1.09×",
"1.75×",
"2.13×",
"1.18×",
"1.93×",
"2.10×",
"1.35×"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/norm/kernels/rmsnorm.py).
Goal: perf(norm): tune CuTe-DSL qk_rmsnorm and fused_add_rmsnorm_quant tiling for SM100/103/107
Target hardware: B200, BLACKWELL, SM100, SM103, SM107
Target models: unspecified
Current file:
```python
"""
Copyright (c) 2025 by Fl... | <!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->
Two tiling adjustments to the CuTe-DSL norm kernels on Blackwell and Rubin (SM100, SM103, SM107), gated on an explicit architecture list (`_LATENCY_BOUND_SMS`) so all other ... | [{"scope": "kernel", "hardware": "SM107", "model": null, "shape": "heads=32,head_dim=64", "batch_size": 512, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.0, "speedup": 1.0}, {"scope": "kernel", "hardware": "SM107", "model": null, "shape": "heads=3... | 1.135 | null |
flashinfer | 0ef005a2cdbd9cbcb70a818f66655205c8a7558e | 2026-09-17T23:24:50-07:00 | 5,186 | https://github.com/flashinfer-ai/flashinfer/pull/5186 | perf: reduce split W4A16 routing and output overhead (#5186) | perf: reduce split W4A16 routing and output overhead (#5186)
<!-- .github/pull_request_template.md -->
## 📌 Description
@humansand
Reduce split CuTe DSL W4A16 routing and bounds overhead, and use
complete output subtiles for ordinary scratch stores.
- **Routing:** mark top-k `cutlass.Constexpr`, include it in the... | flashinfer/fused_moe/cute_dsl/blackwell/moe_w4a16.py | cute_dsl | Apache-2.0 | # Copyright (c) 2026 FlashInfer contributors.
# SPDX-License-Identifier: Apache-2.0
"""SM100 NVFP4-weight, BF16-activation fused MoE launcher."""
from dataclasses import dataclass
from typing import Dict, Optional, Tuple
import cutlass
import cutlass.cute as cute
import torch
from flashinfer.cute_dsl.utils import (... | # Copyright (c) 2026 FlashInfer contributors.
# SPDX-License-Identifier: Apache-2.0
"""SM100 NVFP4-weight, BF16-activation fused MoE launcher."""
from dataclasses import dataclass
from typing import Dict, Optional, Tuple
import cutlass
import cutlass.cute as cute
import torch
from flashinfer.cute_dsl.utils import (... | --- flashinfer/fused_moe/cute_dsl/blackwell/moe_w4a16.py
+++ flashinfer/fused_moe/cute_dsl/blackwell/moe_w4a16.py
@@ -125,6 +125,8 @@
):
mma_tiler_m, route_tile, mma_tiler_k = mma_tiler_mnk
use_2cta_instrs = mma_tiler_m == 256
+ cta_tile_m = mma_tiler_m // (2 if use_2cta_instrs else 1)
+ m_cluster_alig... | 5 | 1 | 2 | [
"deepseek"
] | [
"B300",
"BLACKWELL"
] | [
"1.0056×",
"0.9983×",
"1.0033×",
"1.0005×",
"1.0023×",
"0.9977×",
"1.0008×",
"1.0040×",
"1.0027×",
"1.0011×"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/fused_moe/cute_dsl/blackwell/moe_w4a16.py).
Goal: perf: reduce split W4A16 routing and output overhead
Target hardware: B300, BLACKWELL
Target models: deepseek
Current file:
```python
# Copyright (c) 2026 FlashInfer contributors.
# SPDX-License-Identifier... | <!-- .github/pull_request_template.md -->
## 📌 Description
@humansand
Reduce split CuTe DSL W4A16 routing and bounds overhead, and use complete output subtiles for ordinary scratch stores.
- **Routing:** mark top-k `cutlass.Constexpr`, include it in the private kernel cache key, and omit the runtime argument. This... | [{"scope": "e2e", "hardware": "B300", "model": "DeepSeek-like", "shape": "H7168,I2048", "batch_size": 8, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 70.912, "optimized": 70.752, "stated_speedup": null, "speedup": 1.0023}, {"scope": "e2e", "hardware": "B300", "model": "DeepSeek-like", "shap... | null | 1.0047 |
flashinfer | 0ef005a2cdbd9cbcb70a818f66655205c8a7558e | 2026-09-17T23:24:50-07:00 | 5,186 | https://github.com/flashinfer-ai/flashinfer/pull/5186 | perf: reduce split W4A16 routing and output overhead (#5186) | perf: reduce split W4A16 routing and output overhead (#5186)
<!-- .github/pull_request_template.md -->
## 📌 Description
@humansand
Reduce split CuTe DSL W4A16 routing and bounds overhead, and use
complete output subtiles for ordinary scratch stores.
- **Routing:** mark top-k `cutlass.Constexpr`, include it in the... | flashinfer/fused_moe/cute_dsl/blackwell/moe_w4a16_kernel.py | cute_dsl | BSD-3-Clause | # Copyright (c) 2025 - 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Identifier: BSD-3-Clause
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# 1. Redistributions of source code must retain t... | # Copyright (c) 2025 - 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Identifier: BSD-3-Clause
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# 1. Redistributions of source code must retain t... | --- flashinfer/fused_moe/cute_dsl/blackwell/moe_w4a16_kernel.py
+++ flashinfer/fused_moe/cute_dsl/blackwell/moe_w4a16_kernel.py
@@ -96,6 +96,7 @@
use_clc_scheduler: bool,
raster_along_m: bool,
transform_fragment_size: int,
+ m_cluster_aligned: bool,
):
"""Initialize the W... | 32 | 14 | 2 | [
"deepseek"
] | [
"B300",
"BLACKWELL"
] | [
"1.0056×",
"0.9983×",
"1.0033×",
"1.0005×",
"1.0023×",
"0.9977×",
"1.0008×",
"1.0040×",
"1.0027×",
"1.0011×"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/fused_moe/cute_dsl/blackwell/moe_w4a16_kernel.py).
Goal: perf: reduce split W4A16 routing and output overhead
Target hardware: B300, BLACKWELL
Target models: deepseek
Current file:
```python
# Copyright (c) 2025 - 2026 NVIDIA CORPORATION & AFFILIATES. All... | <!-- .github/pull_request_template.md -->
## 📌 Description
@humansand
Reduce split CuTe DSL W4A16 routing and bounds overhead, and use complete output subtiles for ordinary scratch stores.
- **Routing:** mark top-k `cutlass.Constexpr`, include it in the private kernel cache key, and omit the runtime argument. This... | [{"scope": "e2e", "hardware": "B300", "model": "DeepSeek-like", "shape": "H7168,I2048", "batch_size": 8, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 70.912, "optimized": 70.752, "stated_speedup": null, "speedup": 1.0023}, {"scope": "e2e", "hardware": "B300", "model": "DeepSeek-like", "shap... | null | 1.0047 |
flashinfer | bbf39c559d3f4b09482c014e710a3402a67fef88 | 2026-09-17T16:28:08-07:00 | 5,300 | https://github.com/flashinfer-ai/flashinfer/pull/5300 | perf(quantization): SM107 dispatch tuning and 128x4 tile kernels for nvfp4/mxfp4/mxfp8 (#5300) | perf(quantization): SM107 dispatch tuning and 128x4 tile kernels for nvfp4/mxfp4/mxfp8 (#5300)
<!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re
needed. -->
Tunes the CuTe-DSL quantization kernels (`nvfp4_quantize`,
`mxfp4_quantize`, ... | flashinfer/quantization/kernels/mxfp4_quantize.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/quantization/kernels/mxfp4_quantize.py
+++ flashinfer/quantization/kernels/mxfp4_quantize.py
@@ -805,6 +805,220 @@
# =============================================================================
+# =============================================================================
+# CuTe-DSL Kernel Class... | 243 | 6 | 3 | [] | [
"SM100",
"SM103",
"SM107"
] | [
"1.02x",
"1.04x",
"1.08x",
"1.02x",
"1.04x",
"1.09x",
"0.99x",
"1.00x",
"1.03x",
"0.99x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/quantization/kernels/mxfp4_quantize.py).
Goal: perf(quantization): SM107 dispatch tuning and 128x4 tile kernels for nvfp4/mxfp4/mxfp8
Target hardware: SM100, SM103, SM107
Target models: unspecified
Current file:
```python
"""
Copyright (c) 2025 by FlashIn... | <!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->
Tunes the CuTe-DSL quantization kernels (`nvfp4_quantize`, `mxfp4_quantize`, `mxfp8_quantize`) for SM107. Every change is gated on `get_compute_capability() == (10, 7)`; SM1... | [{"scope": "kernel", "hardware": "Rubin (SM107)", "model": null, "shape": "1024\u00d78192 to 8192\u00d724576", "batch_size": null, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.08, "config": "nvfp4 bf16", "tile": "128x4", "speedup": 1.08}, {"scope"... | 1.03 | null |
flashinfer | bbf39c559d3f4b09482c014e710a3402a67fef88 | 2026-09-17T16:28:08-07:00 | 5,300 | https://github.com/flashinfer-ai/flashinfer/pull/5300 | perf(quantization): SM107 dispatch tuning and 128x4 tile kernels for nvfp4/mxfp4/mxfp8 (#5300) | perf(quantization): SM107 dispatch tuning and 128x4 tile kernels for nvfp4/mxfp4/mxfp8 (#5300)
<!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re
needed. -->
Tunes the CuTe-DSL quantization kernels (`nvfp4_quantize`,
`mxfp4_quantize`, ... | flashinfer/quantization/kernels/mxfp8_quantize.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/quantization/kernels/mxfp8_quantize.py
+++ flashinfer/quantization/kernels/mxfp8_quantize.py
@@ -96,6 +96,46 @@
SF_LAYOUT_LINEAR = 2
+# SM107 128x4 tile kernel (see MXFP8QuantizeTile128x4Kernel): 4-column groups
+# per tile, threads per CTA, and persistent CTAs per SM.
+_TILE128X4_COL_GROUPS = 1
+_T... | 362 | 12 | 3 | [] | [
"SM100",
"SM103",
"SM107"
] | [
"1.02x",
"1.04x",
"1.08x",
"1.02x",
"1.04x",
"1.09x",
"0.99x",
"1.00x",
"1.03x",
"0.99x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/quantization/kernels/mxfp8_quantize.py).
Goal: perf(quantization): SM107 dispatch tuning and 128x4 tile kernels for nvfp4/mxfp4/mxfp8
Target hardware: SM100, SM103, SM107
Target models: unspecified
Current file:
```python
"""
Copyright (c) 2025 by FlashIn... | <!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->
Tunes the CuTe-DSL quantization kernels (`nvfp4_quantize`, `mxfp4_quantize`, `mxfp8_quantize`) for SM107. Every change is gated on `get_compute_capability() == (10, 7)`; SM1... | [{"scope": "kernel", "hardware": "Rubin (SM107)", "model": null, "shape": "1024\u00d78192 to 8192\u00d724576", "batch_size": null, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.08, "config": "nvfp4 bf16", "tile": "128x4", "speedup": 1.08}, {"scope"... | 1.03 | null |
flashinfer | bbf39c559d3f4b09482c014e710a3402a67fef88 | 2026-09-17T16:28:08-07:00 | 5,300 | https://github.com/flashinfer-ai/flashinfer/pull/5300 | perf(quantization): SM107 dispatch tuning and 128x4 tile kernels for nvfp4/mxfp4/mxfp8 (#5300) | perf(quantization): SM107 dispatch tuning and 128x4 tile kernels for nvfp4/mxfp4/mxfp8 (#5300)
<!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re
needed. -->
Tunes the CuTe-DSL quantization kernels (`nvfp4_quantize`,
`mxfp4_quantize`, ... | flashinfer/quantization/kernels/nvfp4_quantize.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/quantization/kernels/nvfp4_quantize.py
+++ flashinfer/quantization/kernels/nvfp4_quantize.py
@@ -31,6 +31,7 @@
"""
import functools
+import os
from typing import Callable, Tuple, Union, cast
import cutlass
@@ -99,6 +100,18 @@
# Linear kernel: fixed 16 warps (512 threads), 1 SF block per thread
... | 595 | 102 | 3 | [] | [
"SM100",
"SM103",
"SM107"
] | [
"1.02x",
"1.04x",
"1.08x",
"1.02x",
"1.04x",
"1.09x",
"0.99x",
"1.00x",
"1.03x",
"0.99x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/quantization/kernels/nvfp4_quantize.py).
Goal: perf(quantization): SM107 dispatch tuning and 128x4 tile kernels for nvfp4/mxfp4/mxfp8
Target hardware: SM100, SM103, SM107
Target models: unspecified
Current file:
```python
"""
Copyright (c) 2025 by FlashIn... | <!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->
Tunes the CuTe-DSL quantization kernels (`nvfp4_quantize`, `mxfp4_quantize`, `mxfp8_quantize`) for SM107. Every change is gated on `get_compute_capability() == (10, 7)`; SM1... | [{"scope": "kernel", "hardware": "Rubin (SM107)", "model": null, "shape": "1024\u00d78192 to 8192\u00d724576", "batch_size": null, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.08, "config": "nvfp4 bf16", "tile": "128x4", "speedup": 1.08}, {"scope"... | 1.03 | null |
flashinfer | 46afca6a173c239aa33a3a087ec181efcab237c7 | 2026-09-15T23:15:17-07:00 | 4,730 | https://github.com/flashinfer-ai/flashinfer/pull/4730 | feat(cake_comm): add optimized Blackwell MoE all-reduce fusion backend (#4730) | feat(cake_comm): add optimized Blackwell MoE all-reduce fusion backend (#4730)
<!-- .github/pull_request_template.md -->
## 📌 Description
This PR adds the opt-in `backend="cake"` implementation to
`trtllm_moe_allreduce_fusion` on SM100 and SM103. It supports FP16/BF16,
world sizes 2/4/8, eager and CUDA Graph execut... | csrc/trtllm_alltoall_prepare.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/trtllm_alltoall_prepare.cu
+++ csrc/trtllm_alltoall_prepare.cu
@@ -198,6 +198,11 @@
__device__ __forceinline__ void recvCount(int* recvIndiceWorkspace, int* recvCounts,
int* sharedCountsBase, MoeCommWorkspace workspace,
int ... | 5 | 2 | 2 | [] | [
"B200",
"B300",
"BLACKWELL",
"CPU",
"H100",
"SM100",
"SM103",
"SM120"
] | [
"1.122930×",
"1.121959×",
"1.122930×",
"1.065517×",
"1.198880×",
"1.121959×",
"1.059156×",
"1.200922×",
"1.063248×",
"1.059156×"
] | Optimize this cuda kernel file from flashinfer (csrc/trtllm_alltoall_prepare.cu).
Goal: feat(cake_comm): add optimized Blackwell MoE all-reduce fusion backend
Target hardware: B200, B300, BLACKWELL, CPU, H100, SM100, SM103, SM120
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2022-2024, NVIDIA C... | Developed by the **CAKE team**, the kernels in this PR **outperform** the relevant **SOTA baselines at the time of merge** on the **vast majority of performance benchmark shapes**, matching them otherwise.
<!-- .github/pull_request_template.md -->
## 📌 Description
This PR adds the opt-in `backend="cake"` implementa... | [{"scope": "kernel", "hardware": "B200", "model": null, "shape": null, "batch_size": null, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 0.021321571, "optimized": 0.018987444, "stated_speedup": null, "speedup": 1.1229}, {"scope": "kernel", "hardware": "B200", "model": null, "shape": null, "b... | 1.122 | null |
flashinfer | 892b22dc5a5d48258e12434cfa045cb71fe9dad7 | 2026-09-16T10:32:53+08:00 | 4,917 | https://github.com/flashinfer-ai/flashinfer/pull/4917 | perf(gdn): optimize SM100 CP kernels (#4917) | perf(gdn): optimize SM100 CP kernels (#4917)
## Description
This PR ports the useful SM100 CP kernel optimizations identified while
comparing the CuTeDSL implementation with the CAKE-generated kernels in
#4539:
- vectorize state loads in the final prefill kernel;
- interleave fixup accumulators to expose instruction... | flashinfer/gdn_kernels/delta_rule_dsl/varlen_helper.py | cute_dsl | Apache-2.0 | import math
import torch
import cutlass
import cutlass.cute as cute
BLK = 64
CP_CHUNK_LEN_GRANULARITY = 512
CP_DEFAULT_SHORT_FIXUP_TO_PREFILL_WORKLOAD_RATIO_NUMERATOR = 1
CP_DEFAULT_SHORT_FIXUP_TO_PREFILL_WORKLOAD_RATIO_DENOMINATOR = 1
CP_SM120_SHORT_FIXUP_TO_PREFILL_WORKLOAD_RATIO_NUMERATOR = 1
CP_SM120_SHORT_FIXUP... | import math
import torch
import cutlass
import cutlass.cute as cute
BLK = 64
CP_CHUNK_LEN_GRANULARITY = 512
CP_DEFAULT_SHORT_FIXUP_TO_PREFILL_WORKLOAD_RATIO_NUMERATOR = 1
CP_DEFAULT_SHORT_FIXUP_TO_PREFILL_WORKLOAD_RATIO_DENOMINATOR = 1
CP_SM120_SHORT_FIXUP_TO_PREFILL_WORKLOAD_RATIO_NUMERATOR = 1
CP_SM120_SHORT_FIXUP... | --- flashinfer/gdn_kernels/delta_rule_dsl/varlen_helper.py
+++ flashinfer/gdn_kernels/delta_rule_dsl/varlen_helper.py
@@ -190,9 +190,7 @@
@cute.jit
-def chunk_bound(
- seq_idx: cutlass.Int32, total, chunk_size: cutlass.Int32
-) -> cutlass.Int32:
+def chunk_bound(seq_idx: cutlass.Int32, total, chunk_size) -> cut... | 7 | 6 | 3 | [] | [
"B200",
"SM100"
] | [
"1.07x",
"1.12x",
"1.18x",
"1.23x",
"1.24x",
"1.26x",
"1.02x",
"1.04x",
"1.07x",
"1.11x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/gdn_kernels/delta_rule_dsl/varlen_helper.py).
Goal: perf(gdn): optimize SM100 CP kernels
Target hardware: B200, SM100
Target models: unspecified
Current file:
```python
import math
import torch
import cutlass
import cutlass.cute as cute
BLK = 64
CP_CHU... | ## Description
This PR ports the useful SM100 CP kernel optimizations identified while comparing the CuTeDSL implementation with the CAKE-generated kernels in #4539:
- vectorize state loads in the final prefill kernel;
- interleave fixup accumulators to expose instruction-level parallelism;
- reuse gate factors and e... | [{"scope": "e2e", "hardware": "NVIDIA B200", "model": "397B/122B TP8", "shape": "h_qk=2,h_v=8", "batch_size": 1, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 0.353, "optimized": 0.33, "stated_speedup": 1.07, "speedup": 1.0697}, {"scope": "e2e", "hardware": "NVIDIA B200", "model": "397B/122B... | null | 1.0305 |
flashinfer | 5ed46a9ee125f167fd1070be9aa081d70e92b366 | 2026-09-14T14:22:24-07:00 | 4,737 | https://github.com/flashinfer-ai/flashinfer/pull/4737 | Paged-MQA logits: Rubin (SM107) enablement, FP4 next_n=4, and DKG epilogue/scheduler optimizations (#4737) | Paged-MQA logits: Rubin (SM107) enablement, FP4 next_n=4, and DKG epilogue/scheduler optimizations (#4737)
## 📌 Description
Three changes to the paged-MQA logits kernels
(`flashinfer.attn_scores`): enable them on Rubin (SM107), support FP4
`next_n=4` on both architectures — natively on Rubin, via an in-kernel
atom s... | flashinfer/attn_scores/kernels/schedule_kernel.py | cute_dsl | Apache-2.0 | # Copyright (c) 2025 by FlashInfer team.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in... | # Copyright (c) 2025 by FlashInfer team.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in... | --- flashinfer/attn_scores/kernels/schedule_kernel.py
+++ flashinfer/attn_scores/kernels/schedule_kernel.py
@@ -204,8 +204,11 @@
from ...jit.cute_dsl_core import build_and_load_cute_dsl_kernel
sym_B = cute.sym_int()
- cl_fake = cute.runtime.make_fake_compact_tensor(
- cutlass.Int32, (sym_B,), stri... | 5 | 2 | 8 | [] | [
"B200",
"BLACKWELL",
"SM100",
"SM103",
"SM107",
"SM80"
] | [
"1.26×",
"1.37×",
"1.20×",
"1.55×",
"1.7×",
"1.405×",
"2.4×"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/attn_scores/kernels/schedule_kernel.py).
Goal: Paged-MQA logits: Rubin (SM107) enablement, FP4 next_n=4, and DKG epilogue/scheduler optimizations
Target hardware: B200, BLACKWELL, SM100, SM103, SM107, SM80
Target models: unspecified
Current file:
```pytho... | ## 📌 Description
Three changes to the paged-MQA logits kernels (`flashinfer.attn_scores`): enable them on Rubin (SM107), support FP4 `next_n=4` on both architectures — natively on Rubin, via an in-kernel atom split on Blackwell — and port the epilogue/scheduler optimizations from DKG MR !26202.
### 1. Enable paged-M... | [{"scope": "kernel", "hardware": "B200", "model": null, "shape": null, "batch_size": null, "metric": "performance", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.047, "speedup": 1.047}, {"scope": "kernel", "hardware": "B200", "model": null, "shape": null, "batch_size":... | 1.55 | null |
flashinfer | db0cdc26b0060e7d2419013f9e55bc73ee4b4425 | 2026-09-14T10:31:18-07:00 | 4,736 | https://github.com/flashinfer-ai/flashinfer/pull/4736 | perf(attention): specialize paged FA2 equal-stride KV (#4736) | perf(attention): specialize paged FA2 equal-stride KV (#4736)
## 📌 Description
Paged FA2 currently computes and stores independent V offsets even when
K and V have identical strides. That extra address-generation work
regresses common equal-stride paged decode and prefill workloads.
This change:
- checks the relev... | csrc/batch_pod.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/batch_pod.cu
+++ csrc/batch_pod.cu
@@ -90,15 +90,10 @@
const auto q_stride_n_p = q_p.stride(0);
const auto q_stride_h_p = q_p.stride(1);
- // get kv_cache_strides
- const int64_t* kv_cache_strides_p = nullptr;
+ // get independent K/V cache strides
auto k_strides_p = paged_k_cache_p.strides();
... | 6 | 16 | 10 | [
"llama",
"gpt-oss"
] | [
"B300",
"SM103"
] | [] | Optimize this cuda kernel file from flashinfer (csrc/batch_pod.cu).
Goal: perf(attention): specialize paged FA2 equal-stride KV
Target hardware: B300, SM103
Target models: llama, gpt-oss
Current file:
```cuda
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "Licen... | ## 📌 Description
Paged FA2 currently computes and stores independent V offsets even when K and V have identical strides. That extra address-generation work regresses common equal-stride paged decode and prefill workloads.
This change:
- checks the relevant K/V strides once during host dispatch and selects a compile... | [] | null | null |
flashinfer | db0cdc26b0060e7d2419013f9e55bc73ee4b4425 | 2026-09-14T10:31:18-07:00 | 4,736 | https://github.com/flashinfer-ai/flashinfer/pull/4736 | perf(attention): specialize paged FA2 equal-stride KV (#4736) | perf(attention): specialize paged FA2 equal-stride KV (#4736)
## 📌 Description
Paged FA2 currently computes and stores independent V offsets even when
K and V have identical strides. That extra address-generation work
regresses common equal-stride paged decode and prefill workloads.
This change:
- checks the relev... | csrc/batch_prefill.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/batch_prefill.cu
+++ csrc/batch_prefill.cu
@@ -23,7 +23,7 @@
namespace flashinfer {
-template <uint32_t CTA_TILE_Q, uint32_t HEAD_DIM_QK, uint32_t HEAD_DIM_VO,
+template <bool SAME_KV_STRIDES, uint32_t CTA_TILE_Q, uint32_t HEAD_DIM_QK, uint32_t HEAD_DIM_VO,
PosEncodingMode POS_ENCODING_MODE, bo... | 2 | 136 | 10 | [
"llama",
"gpt-oss"
] | [
"B300",
"SM103"
] | [] | Optimize this cuda kernel file from flashinfer (csrc/batch_prefill.cu).
Goal: perf(attention): specialize paged FA2 equal-stride KV
Target hardware: B300, SM103
Target models: llama, gpt-oss
Current file:
```cuda
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "L... | ## 📌 Description
Paged FA2 currently computes and stores independent V offsets even when K and V have identical strides. That extra address-generation work regresses common equal-stride paged decode and prefill workloads.
This change:
- checks the relevant K/V strides once during host dispatch and selects a compile... | [] | null | null |
flashinfer | db0cdc26b0060e7d2419013f9e55bc73ee4b4425 | 2026-09-14T10:31:18-07:00 | 4,736 | https://github.com/flashinfer-ai/flashinfer/pull/4736 | perf(attention): specialize paged FA2 equal-stride KV (#4736) | perf(attention): specialize paged FA2 equal-stride KV (#4736)
## 📌 Description
Paged FA2 currently computes and stores independent V offsets even when
K and V have identical strides. That extra address-generation work
regresses common equal-stride paged decode and prefill workloads.
This change:
- checks the relev... | csrc/pod.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/pod.cu
+++ csrc/pod.cu
@@ -123,15 +123,10 @@
const auto q_stride_n_d = q_d.stride(0);
const auto q_stride_h_d = q_d.stride(1);
- // get kv_cache_strides
- const int64_t* kv_cache_strides_d = nullptr;
+ // get independent K/V cache strides
auto k_strides_d = paged_k_cache_d.strides();
auto v_st... | 3 | 8 | 10 | [
"llama",
"gpt-oss"
] | [
"B300",
"SM103"
] | [] | Optimize this cuda kernel file from flashinfer (csrc/pod.cu).
Goal: perf(attention): specialize paged FA2 equal-stride KV
Target hardware: B300, SM103
Target models: llama, gpt-oss
Current file:
```cuda
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
... | ## 📌 Description
Paged FA2 currently computes and stores independent V offsets even when K and V have identical strides. That extra address-generation work regresses common equal-stride paged decode and prefill workloads.
This change:
- checks the relevant K/V strides once during host dispatch and selects a compile... | [] | null | null |
flashinfer | e500442f83fe9aac7969eb1c8731b6921fa6f180 | 2026-09-13T10:58:37-07:00 | 5,169 | https://github.com/flashinfer-ai/flashinfer/pull/5169 | perf(cake_comm): reduce PCIe CE ring publication overhead on SM120 (#5169) | perf(cake_comm): reduce PCIe CE ring publication overhead on SM120 (#5169)
| GPU | Baseline mean (ms) | Candidate mean (ms) | Speedup |
|---|---:|---:|---:|
| H100 | 0.267771 | 0.268482 | 0.997351× |
| GB200 | 0.143053 | 0.143131 | 0.999452× |
| GB300 | 0.145567 | 0.145749 | 0.998749× |
| B200 | 0.171413 | 0.170973 | ... | csrc/pcie_ipc_all_reduce.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2026 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law o... | /*
* Copyright (c) 2026 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law o... | --- csrc/pcie_ipc_all_reduce.cu
+++ csrc/pcie_ipc_all_reduce.cu
@@ -30,7 +30,17 @@
using fptr_t = int64_t;
static_assert(sizeof(void*) == sizeof(fptr_t));
+// Local eligibility sizes this rank's optional region; the group still decides
+// whether the SM120 protocol may be enabled.
+bool pcie_ipc_memop_supported();... | 61 | 3 | 7 | [] | [
"A100",
"A10G",
"B200",
"B300",
"CPU",
"GB200",
"GB300",
"H100",
"SM100",
"SM103",
"SM120",
"SM121",
"SM80",
"SM86",
"SM89",
"SM90"
] | [
"0.997351×",
"0.999452×",
"0.998749×",
"1.002574×",
"1.003499×",
"0.949393×",
"1.020006×",
"1.15905×",
"1.020006x",
"1.039546x"
] | Optimize this cuda kernel file from flashinfer (csrc/pcie_ipc_all_reduce.cu).
Goal: perf(cake_comm): reduce PCIe CE ring publication overhead on SM120
Target hardware: A100, A10G, B200, B300, CPU, GB200, GB300, H100, SM100, SM103, SM120, SM121, SM80, SM86, SM89, SM90
Target models: unspecified
Current file:
```cuda
/... | > Developed by the **CAKE team**, the kernels in this PR **outperform** the relevant **SOTA baselines at the time of merge** on the **vast majority of performance benchmark shapes**, matching them otherwise.
| GPU | Baseline mean (ms) | Candidate mean (ms) | Speedup |
|---|---:|---:|---:|
| H100 | 0.267771 | 0.268482 ... | [{"scope": "kernel", "hardware": "H100", "model": null, "shape": "TP4,BF16,48MiB", "batch_size": null, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 0.26097, "optimized": 0.265741, "stated_speedup": 0.982047, "speedup": 0.982}, {"scope": "kernel", "hardware": "H100", "model": null, "shape": ... | 1.001 | null |
flashinfer | e500442f83fe9aac7969eb1c8731b6921fa6f180 | 2026-09-13T10:58:37-07:00 | 5,169 | https://github.com/flashinfer-ai/flashinfer/pull/5169 | perf(cake_comm): reduce PCIe CE ring publication overhead on SM120 (#5169) | perf(cake_comm): reduce PCIe CE ring publication overhead on SM120 (#5169)
| GPU | Baseline mean (ms) | Candidate mean (ms) | Speedup |
|---|---:|---:|---:|
| H100 | 0.267771 | 0.268482 | 0.997351× |
| GB200 | 0.143053 | 0.143131 | 0.999452× |
| GB300 | 0.145567 | 0.145749 | 0.998749× |
| B200 | 0.171413 | 0.170973 | ... | include/flashinfer/comm/pcie_ipc_all_reduce.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2026 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law o... | /*
* Copyright (c) 2026 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law o... | --- include/flashinfer/comm/pcie_ipc_all_reduce.cuh
+++ include/flashinfer/comm/pcie_ipc_all_reduce.cuh
@@ -101,10 +101,11 @@
// Copy-engine ring. Dispatched one level up, in csrc, not by all_reduce()
// below -- see the guard at the top of that function.
kCopyEngineRing = 4,
- kCopyEngineIsland = 5, // 4+4 ... | 5 | 3 | 7 | [] | [
"A100",
"A10G",
"B200",
"B300",
"CPU",
"GB200",
"GB300",
"H100",
"SM100",
"SM103",
"SM120",
"SM121",
"SM80",
"SM86",
"SM89",
"SM90"
] | [
"0.997351×",
"0.999452×",
"0.998749×",
"1.002574×",
"1.003499×",
"0.949393×",
"1.020006×",
"1.15905×",
"1.020006x",
"1.039546x"
] | Optimize this cuda kernel file from flashinfer (include/flashinfer/comm/pcie_ipc_all_reduce.cuh).
Goal: perf(cake_comm): reduce PCIe CE ring publication overhead on SM120
Target hardware: A100, A10G, B200, B300, CPU, GB200, GB300, H100, SM100, SM103, SM120, SM121, SM80, SM86, SM89, SM90
Target models: unspecified
Cur... | > Developed by the **CAKE team**, the kernels in this PR **outperform** the relevant **SOTA baselines at the time of merge** on the **vast majority of performance benchmark shapes**, matching them otherwise.
| GPU | Baseline mean (ms) | Candidate mean (ms) | Speedup |
|---|---:|---:|---:|
| H100 | 0.267771 | 0.268482 ... | [{"scope": "kernel", "hardware": "H100", "model": null, "shape": "TP4,BF16,48MiB", "batch_size": null, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 0.26097, "optimized": 0.265741, "stated_speedup": 0.982047, "speedup": 0.982}, {"scope": "kernel", "hardware": "H100", "model": null, "shape": ... | 1.001 | null |
flashinfer | e500442f83fe9aac7969eb1c8731b6921fa6f180 | 2026-09-13T10:58:37-07:00 | 5,169 | https://github.com/flashinfer-ai/flashinfer/pull/5169 | perf(cake_comm): reduce PCIe CE ring publication overhead on SM120 (#5169) | perf(cake_comm): reduce PCIe CE ring publication overhead on SM120 (#5169)
| GPU | Baseline mean (ms) | Candidate mean (ms) | Speedup |
|---|---:|---:|---:|
| H100 | 0.267771 | 0.268482 | 0.997351× |
| GB200 | 0.143053 | 0.143131 | 0.999452× |
| GB300 | 0.145567 | 0.145749 | 0.998749× |
| B200 | 0.171413 | 0.170973 | ... | include/flashinfer/comm/pcie_ipc_ce_ring.cuh | cuda | Apache-2.0 | /*!
* Copy-engine ring all-reduce: a second data plane beside the SM kernels.
*
* The seven kernels in pcie_ipc_all_reduce.cuh move every byte with SM
* load/store and synchronise through the payload itself: +0.0 means "not yet
* written", so a producer rewrites any real +0.0 to -0.0 and a consumer polls
* its ow... | /*!
* Copy-engine ring all-reduce: a second data plane beside the SM kernels.
*
* The seven kernels in pcie_ipc_all_reduce.cuh move every byte with SM
* load/store and synchronise through the payload itself: +0.0 means "not yet
* written", so a producer rewrites any real +0.0 to -0.0 and a consumer polls
* its ow... | --- include/flashinfer/comm/pcie_ipc_ce_ring.cuh
+++ include/flashinfer/comm/pcie_ipc_ce_ring.cuh
@@ -30,6 +30,7 @@
#define FLASHINFER_COMM_PCIE_IPC_CE_RING_CUH_
#include "pcie_ipc_all_reduce.cuh"
+#include "pcie_ipc_ce_memop.cuh"
// This file follows the surrounding style: plain cudaError_t returns, no
// fram... | 40 | 10 | 7 | [] | [
"A100",
"A10G",
"B200",
"B300",
"CPU",
"GB200",
"GB300",
"H100",
"SM100",
"SM103",
"SM120",
"SM121",
"SM80",
"SM86",
"SM89",
"SM90"
] | [
"0.997351×",
"0.999452×",
"0.998749×",
"1.002574×",
"1.003499×",
"0.949393×",
"1.020006×",
"1.15905×",
"1.020006x",
"1.039546x"
] | Optimize this cuda kernel file from flashinfer (include/flashinfer/comm/pcie_ipc_ce_ring.cuh).
Goal: perf(cake_comm): reduce PCIe CE ring publication overhead on SM120
Target hardware: A100, A10G, B200, B300, CPU, GB200, GB300, H100, SM100, SM103, SM120, SM121, SM80, SM86, SM89, SM90
Target models: unspecified
Curren... | > Developed by the **CAKE team**, the kernels in this PR **outperform** the relevant **SOTA baselines at the time of merge** on the **vast majority of performance benchmark shapes**, matching them otherwise.
| GPU | Baseline mean (ms) | Candidate mean (ms) | Speedup |
|---|---:|---:|---:|
| H100 | 0.267771 | 0.268482 ... | [{"scope": "kernel", "hardware": "H100", "model": null, "shape": "TP4,BF16,48MiB", "batch_size": null, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 0.26097, "optimized": 0.265741, "stated_speedup": 0.982047, "speedup": 0.982}, {"scope": "kernel", "hardware": "H100", "model": null, "shape": ... | 1.001 | null |
flashinfer | 7c51384819f9e78e22a703391fd871dc15ab2630 | 2026-09-11T12:22:12-04:00 | 2,808 | https://github.com/flashinfer-ai/flashinfer/pull/2808 | Fix bmm_fp8 cublasLt handle usage in autotuned cublas runner #26381 (#2808) | Fix bmm_fp8 cublasLt handle usage in autotuned cublas runner #26381 (#2808)
<!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re
needed. -->
## 🔍 Related Issues
https://github.com/vllm-project/vllm/issues/26381
Root cause:
torch.cuda.... | csrc/bmm_fp8.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/bmm_fp8.cu
+++ csrc/bmm_fp8.cu
@@ -17,11 +17,37 @@
#include <driver_types.h>
#include <flashinfer/gemm/bmm_fp8.cuh>
+#include <unordered_map>
#include "tvm_ffi_utils.h"
+namespace {
+
+// Handles are deliberately never destroyed. A thread_local destructor on the
+// main thread may run after CUDA tear... | 33 | 8 | 3 | [
"llama"
] | [
"BLACKWELL"
] | [] | Optimize this cuda kernel file from flashinfer (csrc/bmm_fp8.cu).
Goal: Fix bmm_fp8 cublasLt handle usage in autotuned cublas runner #26381
Target hardware: BLACKWELL
Target models: llama
Current file:
```cuda
/*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "Lic... | <!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->
## 🔍 Related Issues
https://github.com/vllm-project/vllm/issues/26381
Root cause:
torch.cuda.current_blas_handle() returns cublasHandle_t, but bmm_fp8 reinterpreted it as ... | [] | null | null |
flashinfer | 7c51384819f9e78e22a703391fd871dc15ab2630 | 2026-09-11T12:22:12-04:00 | 2,808 | https://github.com/flashinfer-ai/flashinfer/pull/2808 | Fix bmm_fp8 cublasLt handle usage in autotuned cublas runner #26381 (#2808) | Fix bmm_fp8 cublasLt handle usage in autotuned cublas runner #26381 (#2808)
<!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re
needed. -->
## 🔍 Related Issues
https://github.com/vllm-project/vllm/issues/26381
Root cause:
torch.cuda.... | csrc/flashinfer_gemm_binding.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/flashinfer_gemm_binding.cu
+++ csrc/flashinfer_gemm_binding.cu
@@ -17,15 +17,14 @@
#include "tvm_ffi_utils.h"
void bmm_fp8(TensorView A, TensorView B, TensorView D, TensorView A_scale, TensorView B_scale,
- TensorView workspace_buffer, int64_t cublas_handle);
+ TensorView workspace_... | 4 | 5 | 3 | [
"llama"
] | [
"BLACKWELL"
] | [] | Optimize this cuda kernel file from flashinfer (csrc/flashinfer_gemm_binding.cu).
Goal: Fix bmm_fp8 cublasLt handle usage in autotuned cublas runner #26381
Target hardware: BLACKWELL
Target models: llama
Current file:
```cuda
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Versi... | <!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->
## 🔍 Related Issues
https://github.com/vllm-project/vllm/issues/26381
Root cause:
torch.cuda.current_blas_handle() returns cublasHandle_t, but bmm_fp8 reinterpreted it as ... | [] | null | null |
flashinfer | 94b923486c9b74b59743b1dd50d32b100066fe0c | 2026-09-10T19:32:08-07:00 | 4,856 | https://github.com/flashinfer-ai/flashinfer/pull/4856 | fix(fp4_gemm autotune) SM107 kernel family excluded from autotune candidates and heuristics update (#4856) | fix(fp4_gemm autotune) SM107 kernel family excluded from autotune candidates and heuristics update (#4856)
<!-- .github/pull_request_template.md -->
## 📌 Description
1. SM107 kernel family is excluded from autotune candidates due to
silenced import error, fixes added
- Load the SM107 dense FP4 GEMM parent from Fla... | flashinfer/gemm/kernels/dense_blockscaled_gemm_sm100.py | cute_dsl | BSD-3-Clause | # Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Identifier: BSD-3-Clause
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# 1. Redistributions of source code must retain the abov... | # Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Identifier: BSD-3-Clause
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# 1. Redistributions of source code must retain the abov... | --- flashinfer/gemm/kernels/dense_blockscaled_gemm_sm100.py
+++ flashinfer/gemm/kernels/dense_blockscaled_gemm_sm100.py
@@ -135,6 +135,16 @@
self.cta_sync_bar_id = 0
self.epilog_sync_bar_id = 1
self.tmem_ptr_sync_bar_id = 2
+ # NamedBarrier equivalents of the two ids above, for subclas... | 10 | 0 | 4 | [] | [
"BLACKWELL",
"SM100",
"SM103",
"SM107"
] | [
"16 x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/gemm/kernels/dense_blockscaled_gemm_sm100.py).
Goal: fix(fp4_gemm autotune) SM107 kernel family excluded from autotune candidates and heuristics update
Target hardware: BLACKWELL, SM100, SM103, SM107
Target models: unspecified
Current file:
```python
# Co... | <!-- .github/pull_request_template.md -->
## 📌 Description
1. SM107 kernel family is excluded from autotune candidates due to silenced import error, fixes added
- Load the SM107 dense FP4 GEMM parent from FlashInfer's bundled CUTLASS
sources. The published `nvidia-cutlass-dsl` wheels do not package the
`nvidia_... | [] | null | null |
flashinfer | 7b40d3cb914cef34544a831994bd8d8a1a9987d2 | 2026-09-10T15:52:15-07:00 | 4,986 | https://github.com/flashinfer-ai/flashinfer/pull/4986 | perf(topk_varlen): gvr_2 dispatch rungs for 4K-8K rows, SM-count-aware register band, hint-free gvr_2 in auto (#4986) | perf(topk_varlen): gvr_2 dispatch rungs for 4K-8K rows, SM-count-aware register band, hint-free gvr_2 in auto (#4986)
<!-- .github/pull_request_template.md -->
## 📌 Description
Follow-up to #4811 (these two commits were pushed to its branch after
the squash-merge, so they never landed). Both are host-side changes t... | flashinfer/topk_varlen/topk_varlen.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/topk_varlen/topk_varlen.py
+++ flashinfer/topk_varlen/topk_varlen.py
@@ -33,7 +33,10 @@
``"gvr_2"`` — self-sampling GVR V2 (sample-calibrated threshold
ladders; TRT-LLM PR #17821 port). Requires a datacentre
Blackwell-class GPU (sm_100/103, or Rub... | 163 | 49 | 3 | [] | [
"A100",
"B200",
"B300",
"H100",
"L40S",
"RTX5080"
] | [
"1.7x",
"5x",
"1.3x",
"1.8x",
"12288 x",
"12288 x",
"131072 x",
"131072 x",
"4x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/topk_varlen/topk_varlen.py).
Goal: perf(topk_varlen): gvr_2 dispatch rungs for 4K-8K rows, SM-count-aware register band, hint-free gvr_2 in auto
Target hardware: A100, B200, B300, H100, L40S, RTX5080
Target models: unspecified
Current file:
```python
"""
... | <!-- .github/pull_request_template.md -->
## 📌 Description
Follow-up to #4811 (these two commits were pushed to its branch after the squash-merge, so they never landed). Both are host-side changes to the `gvr_2` self-sampling top-k backend; no kernel code changes.
**1. `gvr_2` dispatch rungs for compressed widths 4... | [{"scope": "e2e", "hardware": "B200", "model": null, "shape": "N=8192", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 4.46, "optimized": 3.62, "stated_speedup": null, "speedup": 1.232}, {"scope": "e2e", "hardware": "B200", "model": null, "shape": "N=8192", "batch_size": 128,... | 1.45 | 1.4 |
flashinfer | 72f6dfade4367ba6e68f6aee1b1393c0c902b474 | 2026-09-11T02:03:23+08:00 | 5,005 | https://github.com/flashinfer-ai/flashinfer/pull/5005 | perf(moe): improve SM90 mixed-input CUTLASS MoE backend performance (#5005) | perf(moe): improve SM90 mixed-input CUTLASS MoE backend performance (#5005)
## 📌 Description
This PR improves the SM90 CUTLASS mixed-input MoE backend in two areas.
First, it expands the MXFP4×FP8 Humming single-warpgroup tactic set with
the
`(128, 64, 128)` shape for both PrefillAll and RollingRefill. The N64
shap... | csrc/fused_moe/cutlass_backend/flashinfer_cutlass_fused_moe_binding.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/fused_moe/cutlass_backend/flashinfer_cutlass_fused_moe_binding.cu
+++ csrc/fused_moe/cutlass_backend/flashinfer_cutlass_fused_moe_binding.cu
@@ -922,7 +922,7 @@
tensorrt_llm::cutlass_extensions::MainloopScheduleType::SINGLE_WARPGROUP_ROLLING;
if (is_single_warpgroup) {
if (!mUseWfp4Afp... | 1 | 1 | 9 | [
"deepseek"
] | [
"H100",
"H20",
"H200",
"SM90"
] | [
"1.0064x",
"1.0923x",
"1.0470x",
"1.0211x",
"1.0857x",
"1.0515x",
"1.0014x",
"1.0277x",
"1.0123x",
"1.0096x"
] | Optimize this cuda kernel file from flashinfer (csrc/fused_moe/cutlass_backend/flashinfer_cutlass_fused_moe_binding.cu).
Goal: perf(moe): improve SM90 mixed-input CUTLASS MoE backend performance
Target hardware: H100, H20, H200, SM90
Target models: deepseek
Current file:
```cuda
/*
* Copyright (c) 2022-2024, NVIDIA ... | ## 📌 Description
This PR improves the SM90 CUTLASS mixed-input MoE backend in two areas.
First, it expands the MXFP4×FP8 Humming single-warpgroup tactic set with the
`(128, 64, 128)` shape for both PrefillAll and RollingRefill. The N64 shape is
registered alongside the existing N8/N16/N32/N40 shapes, routed through ... | [{"scope": "e2e", "hardware": "H20", "model": "DeepSeek-V4-Pro", "shape": null, "batch_size": 512, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 1416.928, "optimized": 1214.624, "stated_speedup": 1.1666, "speedup": 1.1666}, {"scope": "e2e", "hardware": "H20", "model": "DeepSeek-V4-Pro", "sha... | null | 1.0515 |
flashinfer | 72f6dfade4367ba6e68f6aee1b1393c0c902b474 | 2026-09-11T02:03:23+08:00 | 5,005 | https://github.com/flashinfer-ai/flashinfer/pull/5005 | perf(moe): improve SM90 mixed-input CUTLASS MoE backend performance (#5005) | perf(moe): improve SM90 mixed-input CUTLASS MoE backend performance (#5005)
## 📌 Description
This PR improves the SM90 CUTLASS mixed-input MoE backend in two areas.
First, it expands the MXFP4×FP8 Humming single-warpgroup tactic set with
the
`(128, 64, 128)` shape for both PrefillAll and RollingRefill. The N64
shap... | csrc/nv_internal/tensorrt_llm/cutlass_extensions/include/cutlass_extensions/epilogue/collective/sm90_epilogue_array_tma_warpspecialized_mixed_input.hpp | cpp | BSD-3-Clause | /***************************************************************************************************
* Copyright (c) 2023 - 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
*
* Redistribution and use in source and binary forms, with or without
* modification, are p... | /***************************************************************************************************
* Copyright (c) 2023 - 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
*
* Redistribution and use in source and binary forms, with or without
* modification, are p... | --- csrc/nv_internal/tensorrt_llm/cutlass_extensions/include/cutlass_extensions/epilogue/collective/sm90_epilogue_array_tma_warpspecialized_mixed_input.hpp
+++ csrc/nv_internal/tensorrt_llm/cutlass_extensions/include/cutlass_extensions/epilogue/collective/sm90_epilogue_array_tma_warpspecialized_mixed_input.hpp
@@ -66,7... | 75 | 40 | 9 | [
"deepseek"
] | [
"H100",
"H20",
"H200",
"SM90"
] | [
"1.0064x",
"1.0923x",
"1.0470x",
"1.0211x",
"1.0857x",
"1.0515x",
"1.0014x",
"1.0277x",
"1.0123x",
"1.0096x"
] | Optimize this cpp kernel file from flashinfer (csrc/nv_internal/tensorrt_llm/cutlass_extensions/include/cutlass_extensions/epilogue/collective/sm90_epilogue_array_tma_warpspecialized_mixed_input.hpp).
Goal: perf(moe): improve SM90 mixed-input CUTLASS MoE backend performance
Target hardware: H100, H20, H200, SM90
Targe... | ## 📌 Description
This PR improves the SM90 CUTLASS mixed-input MoE backend in two areas.
First, it expands the MXFP4×FP8 Humming single-warpgroup tactic set with the
`(128, 64, 128)` shape for both PrefillAll and RollingRefill. The N64 shape is
registered alongside the existing N8/N16/N32/N40 shapes, routed through ... | [{"scope": "e2e", "hardware": "H20", "model": "DeepSeek-V4-Pro", "shape": null, "batch_size": 512, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 1416.928, "optimized": 1214.624, "stated_speedup": 1.1666, "speedup": 1.1666}, {"scope": "e2e", "hardware": "H20", "model": "DeepSeek-V4-Pro", "sha... | null | 1.0515 |
flashinfer | 72f6dfade4367ba6e68f6aee1b1393c0c902b474 | 2026-09-11T02:03:23+08:00 | 5,005 | https://github.com/flashinfer-ai/flashinfer/pull/5005 | perf(moe): improve SM90 mixed-input CUTLASS MoE backend performance (#5005) | perf(moe): improve SM90 mixed-input CUTLASS MoE backend performance (#5005)
## 📌 Description
This PR improves the SM90 CUTLASS mixed-input MoE backend in two areas.
First, it expands the MXFP4×FP8 Humming single-warpgroup tactic set with
the
`(128, 64, 128)` shape for both PrefillAll and RollingRefill. The N64
shap... | csrc/nv_internal/tensorrt_llm/cutlass_extensions/include/cutlass_extensions/gemm/kernel/sm90_gemm_array_tma_warpspecialized_cooperative_precomputed.hpp | cpp | BSD-3-Clause | /***************************************************************************************************
* Copyright (c) 2023 - 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
*
* Redistribution and use in source and binary forms, with or without
* modification, are p... | /***************************************************************************************************
* Copyright (c) 2023 - 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
*
* Redistribution and use in source and binary forms, with or without
* modification, are p... | --- csrc/nv_internal/tensorrt_llm/cutlass_extensions/include/cutlass_extensions/gemm/kernel/sm90_gemm_array_tma_warpspecialized_cooperative_precomputed.hpp
+++ csrc/nv_internal/tensorrt_llm/cutlass_extensions/include/cutlass_extensions/gemm/kernel/sm90_gemm_array_tma_warpspecialized_cooperative_precomputed.hpp
@@ -808,... | 23 | 15 | 9 | [
"deepseek"
] | [
"H100",
"H20",
"H200",
"SM90"
] | [
"1.0064x",
"1.0923x",
"1.0470x",
"1.0211x",
"1.0857x",
"1.0515x",
"1.0014x",
"1.0277x",
"1.0123x",
"1.0096x"
] | Optimize this cpp kernel file from flashinfer (csrc/nv_internal/tensorrt_llm/cutlass_extensions/include/cutlass_extensions/gemm/kernel/sm90_gemm_array_tma_warpspecialized_cooperative_precomputed.hpp).
Goal: perf(moe): improve SM90 mixed-input CUTLASS MoE backend performance
Target hardware: H100, H20, H200, SM90
Targe... | ## 📌 Description
This PR improves the SM90 CUTLASS mixed-input MoE backend in two areas.
First, it expands the MXFP4×FP8 Humming single-warpgroup tactic set with the
`(128, 64, 128)` shape for both PrefillAll and RollingRefill. The N64 shape is
registered alongside the existing N8/N16/N32/N40 shapes, routed through ... | [{"scope": "e2e", "hardware": "H20", "model": "DeepSeek-V4-Pro", "shape": null, "batch_size": 512, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 1416.928, "optimized": 1214.624, "stated_speedup": 1.1666, "speedup": 1.1666}, {"scope": "e2e", "hardware": "H20", "model": "DeepSeek-V4-Pro", "sha... | null | 1.0515 |
flashinfer | 72f6dfade4367ba6e68f6aee1b1393c0c902b474 | 2026-09-11T02:03:23+08:00 | 5,005 | https://github.com/flashinfer-ai/flashinfer/pull/5005 | perf(moe): improve SM90 mixed-input CUTLASS MoE backend performance (#5005) | perf(moe): improve SM90 mixed-input CUTLASS MoE backend performance (#5005)
## 📌 Description
This PR improves the SM90 CUTLASS mixed-input MoE backend in two areas.
First, it expands the MXFP4×FP8 Humming single-warpgroup tactic set with
the
`(128, 64, 128)` shape for both PrefillAll and RollingRefill. The N64
shap... | csrc/nv_internal/tensorrt_llm/cutlass_extensions/include/cutlass_extensions/gemm/kernel/sm90_gemm_array_tma_warpspecialized_pingpong_precomputed.hpp | cpp | BSD-3-Clause | /***************************************************************************************************
* Copyright (c) 2023 - 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
*
* Redistribution and use in source and binary forms, with or without
* modification, are p... | /***************************************************************************************************
* Copyright (c) 2023 - 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
*
* Redistribution and use in source and binary forms, with or without
* modification, are p... | --- csrc/nv_internal/tensorrt_llm/cutlass_extensions/include/cutlass_extensions/gemm/kernel/sm90_gemm_array_tma_warpspecialized_pingpong_precomputed.hpp
+++ csrc/nv_internal/tensorrt_llm/cutlass_extensions/include/cutlass_extensions/gemm/kernel/sm90_gemm_array_tma_warpspecialized_pingpong_precomputed.hpp
@@ -846,24 +84... | 23 | 15 | 9 | [
"deepseek"
] | [
"H100",
"H20",
"H200",
"SM90"
] | [
"1.0064x",
"1.0923x",
"1.0470x",
"1.0211x",
"1.0857x",
"1.0515x",
"1.0014x",
"1.0277x",
"1.0123x",
"1.0096x"
] | Optimize this cpp kernel file from flashinfer (csrc/nv_internal/tensorrt_llm/cutlass_extensions/include/cutlass_extensions/gemm/kernel/sm90_gemm_array_tma_warpspecialized_pingpong_precomputed.hpp).
Goal: perf(moe): improve SM90 mixed-input CUTLASS MoE backend performance
Target hardware: H100, H20, H200, SM90
Target m... | ## 📌 Description
This PR improves the SM90 CUTLASS mixed-input MoE backend in two areas.
First, it expands the MXFP4×FP8 Humming single-warpgroup tactic set with the
`(128, 64, 128)` shape for both PrefillAll and RollingRefill. The N64 shape is
registered alongside the existing N8/N16/N32/N40 shapes, routed through ... | [{"scope": "e2e", "hardware": "H20", "model": "DeepSeek-V4-Pro", "shape": null, "batch_size": 512, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 1416.928, "optimized": 1214.624, "stated_speedup": 1.1666, "speedup": 1.1666}, {"scope": "e2e", "hardware": "H20", "model": "DeepSeek-V4-Pro", "sha... | null | 1.0515 |
flashinfer | 72f6dfade4367ba6e68f6aee1b1393c0c902b474 | 2026-09-11T02:03:23+08:00 | 5,005 | https://github.com/flashinfer-ai/flashinfer/pull/5005 | perf(moe): improve SM90 mixed-input CUTLASS MoE backend performance (#5005) | perf(moe): improve SM90 mixed-input CUTLASS MoE backend performance (#5005)
## 📌 Description
This PR improves the SM90 CUTLASS mixed-input MoE backend in two areas.
First, it expands the MXFP4×FP8 Humming single-warpgroup tactic set with
the
`(128, 64, 128)` shape for both PrefillAll and RollingRefill. The N64
shap... | csrc/nv_internal/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/launchers/moe_gemm_tma_ws_mixed_input_prebuild.h | cpp | Apache-2.0 | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/nv_internal/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/launchers/moe_gemm_tma_ws_mixed_input_prebuild.h
+++ csrc/nv_internal/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/launchers/moe_gemm_tma_ws_mixed_input_prebuild.h
@@ -41,6 +41,11 @@
static constexpr int kPrecomputedSchedulerThreads = 128;
static con... | 100 | 15 | 9 | [
"deepseek"
] | [
"H100",
"H20",
"H200",
"SM90"
] | [
"1.0064x",
"1.0923x",
"1.0470x",
"1.0211x",
"1.0857x",
"1.0515x",
"1.0014x",
"1.0277x",
"1.0123x",
"1.0096x"
] | Optimize this cpp kernel file from flashinfer (csrc/nv_internal/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/launchers/moe_gemm_tma_ws_mixed_input_prebuild.h).
Goal: perf(moe): improve SM90 mixed-input CUTLASS MoE backend performance
Target hardware: H100, H20, H200, SM90
Target models: deepseek
Current file:
```cpp... | ## 📌 Description
This PR improves the SM90 CUTLASS mixed-input MoE backend in two areas.
First, it expands the MXFP4×FP8 Humming single-warpgroup tactic set with the
`(128, 64, 128)` shape for both PrefillAll and RollingRefill. The N64 shape is
registered alongside the existing N8/N16/N32/N40 shapes, routed through ... | [{"scope": "e2e", "hardware": "H20", "model": "DeepSeek-V4-Pro", "shape": null, "batch_size": 512, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 1416.928, "optimized": 1214.624, "stated_speedup": 1.1666, "speedup": 1.1666}, {"scope": "e2e", "hardware": "H20", "model": "DeepSeek-V4-Pro", "sha... | null | 1.0515 |
flashinfer | 72f6dfade4367ba6e68f6aee1b1393c0c902b474 | 2026-09-11T02:03:23+08:00 | 5,005 | https://github.com/flashinfer-ai/flashinfer/pull/5005 | perf(moe): improve SM90 mixed-input CUTLASS MoE backend performance (#5005) | perf(moe): improve SM90 mixed-input CUTLASS MoE backend performance (#5005)
## 📌 Description
This PR improves the SM90 CUTLASS mixed-input MoE backend in two areas.
First, it expands the MXFP4×FP8 Humming single-warpgroup tactic set with
the
`(128, 64, 128)` shape for both PrefillAll and RollingRefill. The N64
shap... | csrc/nv_internal/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_gemm_template_dispatch.h | cpp | Apache-2.0 | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/nv_internal/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_gemm_template_dispatch.h
+++ csrc/nv_internal/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_gemm_template_dispatch.h
@@ -684,8 +684,9 @@
if (sm == 90) {
using Tile = cutlass_extensions::CutlassTileConfigSM90;
using Schedule = ... | 3 | 2 | 9 | [
"deepseek"
] | [
"H100",
"H20",
"H200",
"SM90"
] | [
"1.0064x",
"1.0923x",
"1.0470x",
"1.0211x",
"1.0857x",
"1.0515x",
"1.0014x",
"1.0277x",
"1.0123x",
"1.0096x"
] | Optimize this cpp kernel file from flashinfer (csrc/nv_internal/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_gemm_template_dispatch.h).
Goal: perf(moe): improve SM90 mixed-input CUTLASS MoE backend performance
Target hardware: H100, H20, H200, SM90
Target models: deepseek
Current file:
```cpp
/*
* Copyright (c)... | ## 📌 Description
This PR improves the SM90 CUTLASS mixed-input MoE backend in two areas.
First, it expands the MXFP4×FP8 Humming single-warpgroup tactic set with the
`(128, 64, 128)` shape for both PrefillAll and RollingRefill. The N64 shape is
registered alongside the existing N8/N16/N32/N40 shapes, routed through ... | [{"scope": "e2e", "hardware": "H20", "model": "DeepSeek-V4-Pro", "shape": null, "batch_size": 512, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 1416.928, "optimized": 1214.624, "stated_speedup": 1.1666, "speedup": 1.1666}, {"scope": "e2e", "hardware": "H20", "model": "DeepSeek-V4-Pro", "sha... | null | 1.0515 |
flashinfer | 72f6dfade4367ba6e68f6aee1b1393c0c902b474 | 2026-09-11T02:03:23+08:00 | 5,005 | https://github.com/flashinfer-ai/flashinfer/pull/5005 | perf(moe): improve SM90 mixed-input CUTLASS MoE backend performance (#5005) | perf(moe): improve SM90 mixed-input CUTLASS MoE backend performance (#5005)
## 📌 Description
This PR improves the SM90 CUTLASS mixed-input MoE backend in two areas.
First, it expands the MXFP4×FP8 Humming single-warpgroup tactic set with
the
`(128, 64, 128)` shape for both PrefillAll and RollingRefill. The N64
shap... | csrc/nv_internal/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_gemm_template_dispatch_tma_ws_mixed_dtype.h | cpp | Apache-2.0 | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/nv_internal/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_gemm_template_dispatch_tma_ws_mixed_dtype.h
+++ csrc/nv_internal/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_gemm_template_dispatch_tma_ws_mixed_dtype.h
@@ -306,7 +306,7 @@
DISPATCH_MIXED_DTYPE_MOE_TILE(CtaShape128x32x256B, 128, 32, 256);... | 1 | 1 | 9 | [
"deepseek"
] | [
"H100",
"H20",
"H200",
"SM90"
] | [
"1.0064x",
"1.0923x",
"1.0470x",
"1.0211x",
"1.0857x",
"1.0515x",
"1.0014x",
"1.0277x",
"1.0123x",
"1.0096x"
] | Optimize this cpp kernel file from flashinfer (csrc/nv_internal/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_gemm_template_dispatch_tma_ws_mixed_dtype.h).
Goal: perf(moe): improve SM90 mixed-input CUTLASS MoE backend performance
Target hardware: H100, H20, H200, SM90
Target models: deepseek
Current file:
```cpp
... | ## 📌 Description
This PR improves the SM90 CUTLASS mixed-input MoE backend in two areas.
First, it expands the MXFP4×FP8 Humming single-warpgroup tactic set with the
`(128, 64, 128)` shape for both PrefillAll and RollingRefill. The N64 shape is
registered alongside the existing N8/N16/N32/N40 shapes, routed through ... | [{"scope": "e2e", "hardware": "H20", "model": "DeepSeek-V4-Pro", "shape": null, "batch_size": 512, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 1416.928, "optimized": 1214.624, "stated_speedup": 1.1666, "speedup": 1.1666}, {"scope": "e2e", "hardware": "H20", "model": "DeepSeek-V4-Pro", "sha... | null | 1.0515 |
flashinfer | 75038cdf67a5ba577ef4b329badc301f185c5a95 | 2026-09-10T02:48:58+09:00 | 4,997 | https://github.com/flashinfer-ai/flashinfer/pull/4997 | perf(attention): Refresh DSL_FMHA cubins (#4997) | perf(attention): Refresh DSL_FMHA cubins (#4997)
<!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re
needed. -->
+ Refresh DSL_FMHA cubins
+ Minimal change to source code to keep backward compatibility (unlike
cubin builder, FlashInfer ... | flashinfer/attention/cute_dsl/fmha.py | cute_dsl | Apache-2.0 | # Copyright (c) 2026 by FlashInfer team.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in... | # Copyright (c) 2026 by FlashInfer team.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in... | --- flashinfer/attention/cute_dsl/fmha.py
+++ flashinfer/attention/cute_dsl/fmha.py
@@ -542,6 +542,11 @@
None, # skip_softmax_count
None, # total_softmax_count
enable_pdl,
+ None,
+ None,
+ None,
+ None,
+ None,
)
... | 10 | 0 | 5 | [] | [
"B300",
"BLACKWELL",
"CPU"
] | [
"1.0675x",
"1.0552x",
"1.0737x",
"1.0751x",
"1.0364x",
"0.9955x",
"1.0022x",
"0.9523x",
"1.0123x",
"1.0809x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/attention/cute_dsl/fmha.py).
Goal: perf(attention): Refresh DSL_FMHA cubins
Target hardware: B300, BLACKWELL, CPU
Target models: unspecified
Current file:
```python
# Copyright (c) 2026 by FlashInfer team.
#
# Licensed under the Apache License, Version 2.... | <!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->
+ Refresh DSL_FMHA cubins
+ Minimal change to source code to keep backward compatibility (unlike cubin builder, FlashInfer needs to ensure JIT source compatibility with mult... | [{"scope": "kernel", "hardware": "B300", "model": null, "shape": "S=2048", "batch_size": 2, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 0.0648, "optimized": 0.060704, "stated_speedup": 1.0675, "speedup": 1.0675}, {"scope": "kernel", "hardware": "B300", "model": null, "shape": "S=2048", "ba... | 1.0458 | null |
flashinfer | 75038cdf67a5ba577ef4b329badc301f185c5a95 | 2026-09-10T02:48:58+09:00 | 4,997 | https://github.com/flashinfer-ai/flashinfer/pull/4997 | perf(attention): Refresh DSL_FMHA cubins (#4997) | perf(attention): Refresh DSL_FMHA cubins (#4997)
<!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re
needed. -->
+ Refresh DSL_FMHA cubins
+ Minimal change to source code to keep backward compatibility (unlike
cubin builder, FlashInfer ... | flashinfer/cute_dsl/attention/fmha/compile.py | cute_dsl | Apache-2.0 | # SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Identifier: Apache-2.0
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# ht... | # SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Identifier: Apache-2.0
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# ht... | --- flashinfer/cute_dsl/attention/fmha/compile.py
+++ flashinfer/cute_dsl/attention/fmha/compile.py
@@ -117,6 +117,11 @@
mask_type=_mask_type(has_window_left or has_window_right),
enable_ex2_emulation=enable_ex2_emulation,
enable_skip_correction=True,
+ # Rescale threshold compresses t... | 16 | 2 | 5 | [] | [
"B300",
"BLACKWELL",
"CPU"
] | [
"1.0675x",
"1.0552x",
"1.0737x",
"1.0751x",
"1.0364x",
"0.9955x",
"1.0022x",
"0.9523x",
"1.0123x",
"1.0809x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/cute_dsl/attention/fmha/compile.py).
Goal: perf(attention): Refresh DSL_FMHA cubins
Target hardware: B300, BLACKWELL, CPU
Target models: unspecified
Current file:
```python
# SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All ... | <!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->
+ Refresh DSL_FMHA cubins
+ Minimal change to source code to keep backward compatibility (unlike cubin builder, FlashInfer needs to ensure JIT source compatibility with mult... | [{"scope": "kernel", "hardware": "B300", "model": null, "shape": "S=2048", "batch_size": 2, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 0.0648, "optimized": 0.060704, "stated_speedup": 1.0675, "speedup": 1.0675}, {"scope": "kernel", "hardware": "B300", "model": null, "shape": "S=2048", "ba... | 1.0458 | null |
flashinfer | af9b148e9133880154e33dc22205403b8b9698e6 | 2026-09-08T17:44:35+02:00 | 4,067 | https://github.com/flashinfer-ai/flashinfer/pull/4067 | perf(moe): phase NVFP4 dispatch payload copies at EP4/EP8/EP16 (#4067) | perf(moe): phase NVFP4 dispatch payload copies at EP4/EP8/EP16 (#4067)
## Summary
Follow-up to #3846. The generic dispatch kernel makes every CTA thread
build remote destination pointers for every payload before determining
whether that thread owns any bytes. NVFP4 has four predictably
asymmetric payloads, so this ch... | csrc/nv_internal/tensorrt_llm/kernels/communicationKernels/moeAlltoAllKernels.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless requi... | /*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless requi... | --- csrc/nv_internal/tensorrt_llm/kernels/communicationKernels/moeAlltoAllKernels.cu
+++ csrc/nv_internal/tensorrt_llm/kernels/communicationKernels/moeAlltoAllKernels.cu
@@ -35,8 +35,25 @@
#define DISABLE_SYNC_FOR_PROFILING 0
constexpr int kEp4Size = 4;
+// Two 32-thread warps can cover at most 64 16-byte activatio... | 200 | 21 | 1 | [
"nemotron"
] | [
"GB200"
] | [] | Optimize this cuda kernel file from flashinfer (csrc/nv_internal/tensorrt_llm/kernels/communicationKernels/moeAlltoAllKernels.cu).
Goal: perf(moe): phase NVFP4 dispatch payload copies at EP4/EP8/EP16
Target hardware: GB200
Target models: nemotron
Current file:
```cuda
/*
* Copyright (c) 2025, NVIDIA CORPORATION. Al... | ## Summary
Follow-up to #3846. The generic dispatch kernel makes every CTA thread build remote destination pointers for every payload before determining whether that thread owns any bytes. NVFP4 has four predictably asymmetric payloads, so this change gives each payload only the workers it needs:
- two warps for pack... | [{"scope": "kernel", "hardware": "GB200", "model": "H2048", "shape": "top-k=22", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 13.48, "optimized": 12.862, "stated_speedup": null, "speedup": 1.048}, {"scope": "kernel", "hardware": "GB200", "model": "H2048", "shape": "top-k=22... | 1.2244 | 1.0249 |
flashinfer | b255f54480b7754ea094a43575d0c2cfbd0bff18 | 2026-09-04T01:39:10+02:00 | 4,545 | https://github.com/flashinfer-ai/flashinfer/pull/4545 | Add ReplaySSM autotuning (#4545) | Add ReplaySSM autotuning (#4545)
## Summary
Adds framework-agnostic runtime autotuning for ReplaySSM checkpointing
SSU. For eligible dense decode workloads, FlashInfer profiles supported
monolithic and two-kernel launches and caches the fastest tactic for
reuse.
## What changes
- Exposes main-kernel pipeline stages... | csrc/checkpointing_ssu.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/checkpointing_ssu.cu
+++ csrc/checkpointing_ssu.cu
@@ -20,6 +20,8 @@
#include <flashinfer/mamba/checkpointing_ssu.cuh>
#include <flashinfer/mamba/launch_checkpointing_ssu.cuh>
// clang-format on
+#include <limits>
+
#include "tvm_ffi_utils.h"
using namespace flashinfer;
@@ -56,7 +58,9 @@
Optional<T... | 26 | 8 | 7 | [
"nemotron"
] | [
"H100"
] | [] | Optimize this cuda kernel file from flashinfer (csrc/checkpointing_ssu.cu).
Goal: Add ReplaySSM autotuning
Target hardware: H100
Target models: nemotron
Current file:
```cuda
/*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file... | ## Summary
Adds framework-agnostic runtime autotuning for ReplaySSM checkpointing SSU. For eligible dense decode workloads, FlashInfer profiles supported monolithic and two-kernel launches and caches the fastest tactic for reuse.
## What changes
- Exposes main-kernel pipeline stages and CTAs per SM as runtime launch... | [] | null | null |
flashinfer | b255f54480b7754ea094a43575d0c2cfbd0bff18 | 2026-09-04T01:39:10+02:00 | 4,545 | https://github.com/flashinfer-ai/flashinfer/pull/4545 | Add ReplaySSM autotuning (#4545) | Add ReplaySSM autotuning (#4545)
## Summary
Adds framework-agnostic runtime autotuning for ReplaySSM checkpointing
SSU. For eligible dense decode workloads, FlashInfer profiles supported
monolithic and two-kernel launches and caches the fastest tactic for
reuse.
## What changes
- Exposes main-kernel pipeline stages... | csrc/checkpointing_ssu_jit_binding.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/checkpointing_ssu_jit_binding.cu
+++ csrc/checkpointing_ssu_jit_binding.cu
@@ -41,14 +41,16 @@
bool dt_softplus,
Optional<TensorView> state_batch_indices, // (batch,) int32
int64_t pad_slot_id,
- Optional<TensorView> state_scale, // (cache, nheads, dim) f32
- Optional<TensorView> rand_s... | 10 | 8 | 7 | [
"nemotron"
] | [
"H100"
] | [] | Optimize this cuda kernel file from flashinfer (csrc/checkpointing_ssu_jit_binding.cu).
Goal: Add ReplaySSM autotuning
Target hardware: H100
Target models: nemotron
Current file:
```cuda
/*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not u... | ## Summary
Adds framework-agnostic runtime autotuning for ReplaySSM checkpointing SSU. For eligible dense decode workloads, FlashInfer profiles supported monolithic and two-kernel launches and caches the fastest tactic for reuse.
## What changes
- Exposes main-kernel pipeline stages and CTAs per SM as runtime launch... | [] | null | null |
flashinfer | b255f54480b7754ea094a43575d0c2cfbd0bff18 | 2026-09-04T01:39:10+02:00 | 4,545 | https://github.com/flashinfer-ai/flashinfer/pull/4545 | Add ReplaySSM autotuning (#4545) | Add ReplaySSM autotuning (#4545)
## Summary
Adds framework-agnostic runtime autotuning for ReplaySSM checkpointing
SSU. For eligible dense decode workloads, FlashInfer profiles supported
monolithic and two-kernel launches and caches the fastest tactic for
reuse.
## What changes
- Exposes main-kernel pipeline stages... | csrc/checkpointing_ssu_kernel_inst.cu | cuda | Apache-2.0 | // clang-format off
#include "checkpointing_ssu_config.inc"
#include <flashinfer/mamba/checkpointing_ssu.cuh>
#include <flashinfer/mamba/launch_checkpointing_ssu.cuh>
// clang-format on
namespace flashinfer::mamba::checkpointing {
template void launchCheckpointingSsu<input_t, dt_t, weight_t, matrixA_t, state_t, state... | // clang-format off
#include "checkpointing_ssu_config.inc"
#include <flashinfer/mamba/checkpointing_ssu.cuh>
#include <flashinfer/mamba/launch_checkpointing_ssu.cuh>
// clang-format on
namespace flashinfer::mamba::checkpointing {
template void launchCheckpointingSsu<input_t, dt_t, weight_t, matrixA_t, state_t, state... | --- csrc/checkpointing_ssu_kernel_inst.cu
+++ csrc/checkpointing_ssu_kernel_inst.cu
@@ -7,6 +7,7 @@
namespace flashinfer::mamba::checkpointing {
template void launchCheckpointingSsu<input_t, dt_t, weight_t, matrixA_t, state_t, stateIndex_t,
- state_scale_t>(CheckpointingSsuParams... | 2 | 1 | 7 | [
"nemotron"
] | [
"H100"
] | [] | Optimize this cuda kernel file from flashinfer (csrc/checkpointing_ssu_kernel_inst.cu).
Goal: Add ReplaySSM autotuning
Target hardware: H100
Target models: nemotron
Current file:
```cuda
// clang-format off
#include "checkpointing_ssu_config.inc"
#include <flashinfer/mamba/checkpointing_ssu.cuh>
#include <flashinfer/... | ## Summary
Adds framework-agnostic runtime autotuning for ReplaySSM checkpointing SSU. For eligible dense decode workloads, FlashInfer profiles supported monolithic and two-kernel launches and caches the fastest tactic for reuse.
## What changes
- Exposes main-kernel pipeline stages and CTAs per SM as runtime launch... | [] | null | null |
flashinfer | b255f54480b7754ea094a43575d0c2cfbd0bff18 | 2026-09-04T01:39:10+02:00 | 4,545 | https://github.com/flashinfer-ai/flashinfer/pull/4545 | Add ReplaySSM autotuning (#4545) | Add ReplaySSM autotuning (#4545)
## Summary
Adds framework-agnostic runtime autotuning for ReplaySSM checkpointing
SSU. For eligible dense decode workloads, FlashInfer profiles supported
monolithic and two-kernel launches and caches the fastest tactic for
reuse.
## What changes
- Exposes main-kernel pipeline stages... | include/flashinfer/mamba/launch_checkpointing_ssu.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/mamba/launch_checkpointing_ssu.cuh
+++ include/flashinfer/mamba/launch_checkpointing_ssu.cuh
@@ -62,6 +62,7 @@
template <typename input_t, typename dt_t, typename weight_t, typename matrixA_t, typename state_t,
typename stateIndex_t, typename state_scale_t, int D_SPLIT, bool VARLEN>
... | 12 | 3 | 7 | [
"mamba",
"nemotron"
] | [
"H100"
] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/mamba/launch_checkpointing_ssu.cuh).
Goal: Add ReplaySSM autotuning
Target hardware: H100
Target models: mamba, nemotron
Current file:
```cuda
/*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "Lice... | ## Summary
Adds framework-agnostic runtime autotuning for ReplaySSM checkpointing SSU. For eligible dense decode workloads, FlashInfer profiles supported monolithic and two-kernel launches and caches the fastest tactic for reuse.
## What changes
- Exposes main-kernel pipeline stages and CTAs per SM as runtime launch... | [] | null | null |
flashinfer | 6f9a513ab9046319d765dd8c6c7085439a29afbf | 2026-09-02T10:57:09-07:00 | 4,752 | https://github.com/flashinfer-ai/flashinfer/pull/4752 | perf(sparse mla): Update sparse MLA half-Q-tile heuristic to apply to short queries only (#4752) | perf(sparse mla): Update sparse MLA half-Q-tile heuristic to apply to short queries only (#4752)
## 📌 Description
### Summary
This PR restricts the sparse-MLA half-Q-tile heuristic to short queries
(`mMaxSeqLenQ <= 16`). Short decode/MTP queries retain the existing Q8
choice,
while long-query DeepSeek-V4 prefill us... | include/flashinfer/trtllm/fmha/fmhaKernels.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2020-2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless r... | /*
* Copyright (c) 2020-2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless r... | --- include/flashinfer/trtllm/fmha/fmhaKernels.cuh
+++ include/flashinfer/trtllm/fmha/fmhaKernels.cuh
@@ -794,10 +794,11 @@
SelectKernelParams& selectKernelParams) const {
// numHeadsQ <= 32 : SwapsMmaAbForGeneration
// Non-power-of-two head counts use one padded Q8/Q... | 13 | 8 | 1 | [
"deepseek"
] | [
"B200"
] | [
"1x",
"1.000x",
"1.002x",
"1.001x",
"1.162x",
"1.277x",
"1.662x",
"1.897x",
"1.886x",
"8x"
] | Optimize this cuda kernel file from flashinfer (include/flashinfer/trtllm/fmha/fmhaKernels.cuh).
Goal: perf(sparse mla): Update sparse MLA half-Q-tile heuristic to apply to short queries only
Target hardware: B200
Target models: deepseek
Current file:
```cuda
/*
* Copyright (c) 2020-2026, NVIDIA CORPORATION. All rig... | ## 📌 Description
### Summary
This PR restricts the sparse-MLA half-Q-tile heuristic to short queries
(`mMaxSeqLenQ <= 16`). Short decode/MTP queries retain the existing Q8 choice,
while long-query DeepSeek-V4 prefill uses Q16.
The existing heuristic considers the number of KV-split CTAs and batch size,
but not the ... | [{"scope": "kernel", "hardware": "B200", "model": "DeepSeek-V4", "shape": "N=16384,K=16384,num_qo_heads=16,num_kv_heads=1,head_dim=512", "batch_size": 1, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 4.931104, "optimized": 2.614256, "stated_speedup": 1.886, "speedup": 1.8862}, {"scope": "ker... | 1.7688 | 1.1039 |
flashinfer | 2c78870399f72bdeaf5dad4ee8939a10ff331c5b | 2026-08-31T23:31:41-07:00 | 4,773 | https://github.com/flashinfer-ai/flashinfer/pull/4773 | fix: skip SM107 low-latency GEMM cubins on Blackwell (#4773) (#4848) | fix: skip SM107 low-latency GEMM cubins on Blackwell (#4773) (#4848)
## 📌 Description
Port of #4786 (plus the #4792 `Sm100f`/sm107 allowance) onto `main`.
After #4648 the trtllm-gen GEMM pack is a single multi-arch artifact, so
`getValidTactics()` on the low-latency runner returned SM107 cubins on
Blackwell. Autotun... | csrc/trtllm_low_latency_gemm_runner.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/trtllm_low_latency_gemm_runner.cu
+++ csrc/trtllm_low_latency_gemm_runner.cu
@@ -19,6 +19,7 @@
#include <tvm/ffi/error.h>
#include <tvm_ffi_utils.h>
+#include <algorithm>
#include <vector>
#include "flashinfer/exception.h"
@@ -36,6 +37,29 @@
using tvm::ffi::Array;
using tvm::ffi::Optional;
+
+names... | 35 | 0 | 1 | [] | [
"B200",
"B300",
"BLACKWELL",
"SM100",
"SM103",
"SM107"
] | [] | Optimize this cuda kernel file from flashinfer (csrc/trtllm_low_latency_gemm_runner.cu).
Goal: fix: skip SM107 low-latency GEMM cubins on Blackwell (#4773)
Target hardware: B200, B300, BLACKWELL, SM100, SM103, SM107
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2020-2025, NVIDIA CORPORATION. A... | [] | null | null | |
flashinfer | 72e5c3ab632247eab680dd953a6debf72e141c2e | 2026-09-01T13:05:35+09:00 | 4,746 | https://github.com/flashinfer-ai/flashinfer/pull/4746 | perf(attention): cut NVFP4 KV dequant instructions on targets without native FP4/FP8 conversion (#4746) | perf(attention): cut NVFP4 KV dequant instructions on targets without native FP4/FP8 conversion (#4746)
<!-- .github/pull_request_template.md -->
## 📌 Description
NVFP4 KV cache works on pre-SM100 but was never performance-tuned there.
On sm_80 (head_dim 128, 32/8 heads, page_size 16) NVFP4 KV costs
**6.8–8.2x FP8 ... | include/flashinfer/vec_dtypes.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/vec_dtypes.cuh
+++ include/flashinfer/vec_dtypes.cuh
@@ -414,7 +414,82 @@
}
};
+// E2M1 nibble decoding helpers. These are plain integer and 16-bit bit manipulation with no
+// FP4 type in their signatures, so they sit outside the FP4 feature guard below: the tile
+// repack in attention/pr... | 107 | 0 | 2 | [] | [
"HOPPER",
"SM100",
"SM80",
"SM86",
"SM89",
"SM90"
] | [
"8.2x",
"5.4x",
"6.75x",
"1.0x",
"1.0x",
"6.76x",
"2.43x",
"8.17x",
"2.97x",
"6.78x"
] | Optimize this cuda kernel file from flashinfer (include/flashinfer/vec_dtypes.cuh).
Goal: perf(attention): cut NVFP4 KV dequant instructions on targets without native FP4/FP8 conversion
Target hardware: HOPPER, SM100, SM80, SM86, SM89, SM90
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2023 by ... | <!-- .github/pull_request_template.md -->
## 📌 Description
NVFP4 KV cache works on pre-SM100 but was never performance-tuned there. On sm_80 (head_dim 128, 32/8 heads, page_size 16) NVFP4 KV costs **6.8–8.2x FP8 KV in prefill and 4.4–5.4x in decode**, even though it reads *half* the bytes FP8 does. FP8 KV — which al... | [{"scope": "kernel", "hardware": "sm_80", "model": null, "shape": "head_dim=128,32/8 heads,page_size=16", "batch_size": 1, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 12.616, "optimized": 4.531, "stated_speedup": null, "speedup": 2.7844}, {"scope": "kernel", "hardware": "sm_80", "model": n... | 2.8778 | null |
flashinfer | 9caa4488a485bb34ac05a065b694b28ca21b2b4e | 2026-08-26T16:08:54-07:00 | 4,733 | https://github.com/flashinfer-ai/flashinfer/pull/4733 | perf(activation): cap act_and_mul_kernel block size for ~17-19% speedup at large hidden dims (#4733) | perf(activation): cap act_and_mul_kernel block size for ~17-19% speedup at large hidden dims (#4733)
## Description
**~17-19% faster `act_and_mul_kernel`** (used by `silu_and_mul` /
`gelu_and_mul` /
`gelu_tanh_and_mul`) **at large hidden dims** — measured 1.17x–1.19x at
`d=8192` on NVIDIA B200
(see Performance Result... | include/flashinfer/activation.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/activation.cuh
+++ include/flashinfer/activation.cuh
@@ -26,7 +26,9 @@
namespace activation {
template <typename T, float (*Activation)(const float&)>
-__global__ void act_and_mul_kernel(T* __restrict__ out, const T* __restrict__ input, const int d) {
+__global__ __launch_bounds__(256) void a... | 3 | 1 | 2 | [] | [
"B200",
"HOPPER",
"SM100",
"SM120",
"SM90"
] | [
"1.17x",
"1.19x",
"16384 ×",
"1.17x",
"4096 ×",
"1.19x"
] | Optimize this cuda kernel file from flashinfer (include/flashinfer/activation.cuh).
Goal: perf(activation): cap act_and_mul_kernel block size for ~17-19% speedup at large hidden dims
Target hardware: B200, HOPPER, SM100, SM120, SM90
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2024 by FlashInf... | ## Description
**~17-19% faster `act_and_mul_kernel`** (used by `silu_and_mul` / `gelu_and_mul` /
`gelu_tanh_and_mul`) **at large hidden dims** — measured 1.17x–1.19x at `d=8192` on NVIDIA B200
(see Performance Results below) — by capping the kernel's thread block size instead of letting it
scale up to 1024 threads.
... | [{"scope": "kernel", "hardware": "NVIDIA B200", "model": null, "shape": "tokens=16384,hidden=8192", "batch_size": 16384, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 139.3, "optimized": 119.3, "stated_speedup": 1.17, "speedup": 1.1676}, {"scope": "kernel", "hardware": "NVIDIA B200", "model"... | 1.1804 | null |
flashinfer | 8c5347726f30063fa1c17c4e81e75d509936d610 | 2026-08-25T22:12:51-04:00 | 4,030 | https://github.com/flashinfer-ai/flashinfer/pull/4030 | perf(msa): chunked top-k and in-kernel causal offsets for the SM12x indexer (#4030) | perf(msa): chunked top-k and in-kernel causal offsets for the SM12x indexer (#4030)
## 📌 Description
Follow-up to #3655, which enabled MiniMax Sparse Attention (MSA) on
SM120/SM121. The indexer (proxy score + top-k, the two ops that pick
each query's KV blocks) stayed behind vLLM in a few regimes there. All
of the g... | flashinfer/msa_ops/cute_dsl/proxy_score_fp4_sm12x.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2026 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2026 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/msa_ops/cute_dsl/proxy_score_fp4_sm12x.py
+++ flashinfer/msa_ops/cute_dsl/proxy_score_fp4_sm12x.py
@@ -651,6 +651,7 @@
paged: bool = False,
qhead_per_kv: int = _QHEAD_PER_KV,
pack_q_len: int = _PACK_Q_LEN,
+ qoff_default: bool = False,
):
super().__init__(h... | 10 | 3 | 7 | [
"minimax"
] | [
"RTX5080",
"SM120",
"SM121"
] | [
"2.2x",
"2.1x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/msa_ops/cute_dsl/proxy_score_fp4_sm12x.py).
Goal: perf(msa): chunked top-k and in-kernel causal offsets for the SM12x indexer
Target hardware: RTX5080, SM120, SM121
Target models: minimax
Current file:
```python
"""
Copyright (c) 2026 by FlashInfer team.
... | ## 📌 Description
Follow-up to #3655, which enabled MiniMax Sparse Attention (MSA) on SM120/SM121. The indexer (proxy score + top-k, the two ops that pick each query's KV blocks) stayed behind vLLM in a few regimes there. All of the gaps traced to `msa_topk_select` and its wrapper rather than to the proxy kernel:
- A... | [{"scope": "kernel", "hardware": "RTX PRO 6000 Server", "model": null, "shape": "S=2k", "batch_size": 1, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 1.31, "optimized": 1.31, "stated_speedup": null, "speedup": 1.0}, {"scope": "kernel", "hardware": "RTX 5080", "model": null, "shape": "S=2k",... | 0.8972 | null |
flashinfer | 8c5347726f30063fa1c17c4e81e75d509936d610 | 2026-08-25T22:12:51-04:00 | 4,030 | https://github.com/flashinfer-ai/flashinfer/pull/4030 | perf(msa): chunked top-k and in-kernel causal offsets for the SM12x indexer (#4030) | perf(msa): chunked top-k and in-kernel causal offsets for the SM12x indexer (#4030)
## 📌 Description
Follow-up to #3655, which enabled MiniMax Sparse Attention (MSA) on
SM120/SM121. The indexer (proxy score + top-k, the two ops that pick
each query's KV blocks) stayed behind vLLM in a few regimes there. All
of the g... | flashinfer/msa_ops/cute_dsl/proxy_score_sm12x.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2026 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2026 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/msa_ops/cute_dsl/proxy_score_sm12x.py
+++ flashinfer/msa_ops/cute_dsl/proxy_score_sm12x.py
@@ -531,6 +531,7 @@
kv_fp8: bool = False,
qhead_per_kv: int = 4,
pack_q_len: int = 16,
+ qoff_default: bool = False,
):
super().__init__(
head_dim=head_d... | 17 | 6 | 7 | [
"minimax"
] | [
"RTX5080",
"SM120",
"SM121"
] | [
"2.2x",
"2.1x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/msa_ops/cute_dsl/proxy_score_sm12x.py).
Goal: perf(msa): chunked top-k and in-kernel causal offsets for the SM12x indexer
Target hardware: RTX5080, SM120, SM121
Target models: minimax
Current file:
```python
"""
Copyright (c) 2026 by FlashInfer team.
Lic... | ## 📌 Description
Follow-up to #3655, which enabled MiniMax Sparse Attention (MSA) on SM120/SM121. The indexer (proxy score + top-k, the two ops that pick each query's KV blocks) stayed behind vLLM in a few regimes there. All of the gaps traced to `msa_topk_select` and its wrapper rather than to the proxy kernel:
- A... | [{"scope": "kernel", "hardware": "RTX PRO 6000 Server", "model": null, "shape": "S=2k", "batch_size": 1, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 1.31, "optimized": 1.31, "stated_speedup": null, "speedup": 1.0}, {"scope": "kernel", "hardware": "RTX 5080", "model": null, "shape": "S=2k",... | 0.8972 | null |
flashinfer | 8c5347726f30063fa1c17c4e81e75d509936d610 | 2026-08-25T22:12:51-04:00 | 4,030 | https://github.com/flashinfer-ai/flashinfer/pull/4030 | perf(msa): chunked top-k and in-kernel causal offsets for the SM12x indexer (#4030) | perf(msa): chunked top-k and in-kernel causal offsets for the SM12x indexer (#4030)
## 📌 Description
Follow-up to #3655, which enabled MiniMax Sparse Attention (MSA) on
SM120/SM121. The indexer (proxy score + top-k, the two ops that pick
each query's KV blocks) stayed behind vLLM in a few regimes there. All
of the g... | flashinfer/msa_ops/cute_dsl/topk_select_countrank_sm12x.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2026 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2026 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/msa_ops/cute_dsl/topk_select_countrank_sm12x.py
+++ flashinfer/msa_ops/cute_dsl/topk_select_countrank_sm12x.py
@@ -21,7 +21,7 @@
import cutlass
import cutlass.cute as cute
-from .topk_select_radix_sm12x import _atomic_add_i32
+from .topk_select_radix_sm12x import _atomic_add_i32, _radix_key
# SMEM... | 2 | 10 | 7 | [
"minimax"
] | [
"RTX5080",
"SM120",
"SM121"
] | [
"2.2x",
"2.1x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/msa_ops/cute_dsl/topk_select_countrank_sm12x.py).
Goal: perf(msa): chunked top-k and in-kernel causal offsets for the SM12x indexer
Target hardware: RTX5080, SM120, SM121
Target models: minimax
Current file:
```python
"""
Copyright (c) 2026 by FlashInfer ... | ## 📌 Description
Follow-up to #3655, which enabled MiniMax Sparse Attention (MSA) on SM120/SM121. The indexer (proxy score + top-k, the two ops that pick each query's KV blocks) stayed behind vLLM in a few regimes there. All of the gaps traced to `msa_topk_select` and its wrapper rather than to the proxy kernel:
- A... | [{"scope": "kernel", "hardware": "RTX PRO 6000 Server", "model": null, "shape": "S=2k", "batch_size": 1, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 1.31, "optimized": 1.31, "stated_speedup": null, "speedup": 1.0}, {"scope": "kernel", "hardware": "RTX 5080", "model": null, "shape": "S=2k",... | 0.8972 | null |
flashinfer | 8c5347726f30063fa1c17c4e81e75d509936d610 | 2026-08-25T22:12:51-04:00 | 4,030 | https://github.com/flashinfer-ai/flashinfer/pull/4030 | perf(msa): chunked top-k and in-kernel causal offsets for the SM12x indexer (#4030) | perf(msa): chunked top-k and in-kernel causal offsets for the SM12x indexer (#4030)
## 📌 Description
Follow-up to #3655, which enabled MiniMax Sparse Attention (MSA) on
SM120/SM121. The indexer (proxy score + top-k, the two ops that pick
each query's KV blocks) stayed behind vLLM in a few regimes there. All
of the g... | flashinfer/msa_ops/cute_dsl/topk_select_radix_sm12x.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2026 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2026 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/msa_ops/cute_dsl/topk_select_radix_sm12x.py
+++ flashinfer/msa_ops/cute_dsl/topk_select_radix_sm12x.py
@@ -48,6 +48,19 @@
res=av.type, op=nvvm.AtomicOpKind.ADD, ptr=ptr.llvm_ptr, a=av
)
return nvvm.atomicrmw(op=nvvm.AtomicOpKind.ADD, ptr=ptr.llvm_ptr, a=av)
+
+
+@cute.jit
+def ... | 15 | 10 | 7 | [
"minimax"
] | [
"RTX5080",
"SM120",
"SM121"
] | [
"2.2x",
"2.1x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/msa_ops/cute_dsl/topk_select_radix_sm12x.py).
Goal: perf(msa): chunked top-k and in-kernel causal offsets for the SM12x indexer
Target hardware: RTX5080, SM120, SM121
Target models: minimax
Current file:
```python
"""
Copyright (c) 2026 by FlashInfer team... | ## 📌 Description
Follow-up to #3655, which enabled MiniMax Sparse Attention (MSA) on SM120/SM121. The indexer (proxy score + top-k, the two ops that pick each query's KV blocks) stayed behind vLLM in a few regimes there. All of the gaps traced to `msa_topk_select` and its wrapper rather than to the proxy kernel:
- A... | [{"scope": "kernel", "hardware": "RTX PRO 6000 Server", "model": null, "shape": "S=2k", "batch_size": 1, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 1.31, "optimized": 1.31, "stated_speedup": null, "speedup": 1.0}, {"scope": "kernel", "hardware": "RTX 5080", "model": null, "shape": "S=2k",... | 0.8972 | null |
flashinfer | 8c5347726f30063fa1c17c4e81e75d509936d610 | 2026-08-25T22:12:51-04:00 | 4,030 | https://github.com/flashinfer-ai/flashinfer/pull/4030 | perf(msa): chunked top-k and in-kernel causal offsets for the SM12x indexer (#4030) | perf(msa): chunked top-k and in-kernel causal offsets for the SM12x indexer (#4030)
## 📌 Description
Follow-up to #3655, which enabled MiniMax Sparse Attention (MSA) on
SM120/SM121. The indexer (proxy score + top-k, the two ops that pick
each query's KV blocks) stayed behind vLLM in a few regimes there. All
of the g... | flashinfer/msa_ops/proxy_score.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2026 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2026 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/msa_ops/proxy_score.py
+++ flashinfer/msa_ops/proxy_score.py
@@ -477,10 +477,10 @@
q = q.to(torch.bfloat16)
q_fp8 = False
- # Right-aligned decode on the stream and key-major paths computes the
- # causal limit in-kernel, so no offset tensor (and its build kernels,
- # which ... | 26 | 10 | 7 | [
"minimax"
] | [
"RTX5080",
"SM120",
"SM121"
] | [
"2.2x",
"2.1x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/msa_ops/proxy_score.py).
Goal: perf(msa): chunked top-k and in-kernel causal offsets for the SM12x indexer
Target hardware: RTX5080, SM120, SM121
Target models: minimax
Current file:
```python
"""
Copyright (c) 2026 by FlashInfer team.
Licensed under the... | ## 📌 Description
Follow-up to #3655, which enabled MiniMax Sparse Attention (MSA) on SM120/SM121. The indexer (proxy score + top-k, the two ops that pick each query's KV blocks) stayed behind vLLM in a few regimes there. All of the gaps traced to `msa_topk_select` and its wrapper rather than to the proxy kernel:
- A... | [{"scope": "kernel", "hardware": "RTX PRO 6000 Server", "model": null, "shape": "S=2k", "batch_size": 1, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 1.31, "optimized": 1.31, "stated_speedup": null, "speedup": 1.0}, {"scope": "kernel", "hardware": "RTX 5080", "model": null, "shape": "S=2k",... | 0.8972 | null |
flashinfer | 8c5347726f30063fa1c17c4e81e75d509936d610 | 2026-08-25T22:12:51-04:00 | 4,030 | https://github.com/flashinfer-ai/flashinfer/pull/4030 | perf(msa): chunked top-k and in-kernel causal offsets for the SM12x indexer (#4030) | perf(msa): chunked top-k and in-kernel causal offsets for the SM12x indexer (#4030)
## 📌 Description
Follow-up to #3655, which enabled MiniMax Sparse Attention (MSA) on
SM120/SM121. The indexer (proxy score + top-k, the two ops that pick
each query's KV blocks) stayed behind vLLM in a few regimes there. All
of the g... | flashinfer/msa_ops/sparse_topk_select.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2026 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2026 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/msa_ops/sparse_topk_select.py
+++ flashinfer/msa_ops/sparse_topk_select.py
@@ -20,6 +20,7 @@
import torch
from ..api_logging import flashinfer_api
+from ..trace.templates.msa import msa_topk_select_trace
from ..utils import is_sm12x_supported
from ._blackwell_sm100 import blackwell_msa_topk_select,... | 93 | 1 | 7 | [
"minimax"
] | [
"RTX5080",
"SM120",
"SM121"
] | [
"2.2x",
"2.1x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/msa_ops/sparse_topk_select.py).
Goal: perf(msa): chunked top-k and in-kernel causal offsets for the SM12x indexer
Target hardware: RTX5080, SM120, SM121
Target models: minimax
Current file:
```python
"""
Copyright (c) 2026 by FlashInfer team.
Licensed un... | ## 📌 Description
Follow-up to #3655, which enabled MiniMax Sparse Attention (MSA) on SM120/SM121. The indexer (proxy score + top-k, the two ops that pick each query's KV blocks) stayed behind vLLM in a few regimes there. All of the gaps traced to `msa_topk_select` and its wrapper rather than to the proxy kernel:
- A... | [{"scope": "kernel", "hardware": "RTX PRO 6000 Server", "model": null, "shape": "S=2k", "batch_size": 1, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 1.31, "optimized": 1.31, "stated_speedup": null, "speedup": 1.0}, {"scope": "kernel", "hardware": "RTX 5080", "model": null, "shape": "S=2k",... | 0.8972 | null |
flashinfer | 75e834d633bc87267accc6e3f9749d18e459566a | 2026-08-25T09:23:27-07:00 | 4,708 | https://github.com/flashinfer-ai/flashinfer/pull/4708 | (perf) add fused_GDN_step support for Qwen 3.6 35B A3B on sm120 (#4708) | (perf) add fused_GDN_step support for Qwen 3.6 35B A3B on sm120 (#4708)
<!-- .github/pull_request_template.md -->
## 📌 Description
Follow up with #4481
- Adds Qwen3.6-35B-A3B support at batches 1/2/4 for both CUDA and
CuTe-DSL implementations.
- Generates one geometry-specific CUDA JIT module using FI_GDN_* compil... | flashinfer/gdn_kernels/experimental/kernel/gdn_fused_decode_cutedsl_sm120_pdl.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2026 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2026 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/gdn_kernels/experimental/kernel/gdn_fused_decode_cutedsl_sm120_pdl.py
+++ flashinfer/gdn_kernels/experimental/kernel/gdn_fused_decode_cutedsl_sm120_pdl.py
@@ -18,8 +18,8 @@
Host and kernel side of the ``cutedsl_sm120_pdl`` registry impl: a
two-launch CuTe-DSL implementation of the fused GDN decode st... | 168 | 53 | 6 | [
"qwen"
] | [
"SM120"
] | [] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/gdn_kernels/experimental/kernel/gdn_fused_decode_cutedsl_sm120_pdl.py).
Goal: (perf) add fused_GDN_step support for Qwen 3.6 35B A3B on sm120
Target hardware: SM120
Target models: qwen
Current file:
```python
"""
Copyright (c) 2026 by FlashInfer team.
Li... | <!-- .github/pull_request_template.md -->
## 📌 Description
Follow up with #4481
- Adds Qwen3.6-35B-A3B support at batches 1/2/4 for both CUDA and CuTe-DSL implementations.
- Generates one geometry-specific CUDA JIT module using FI_GDN_* compile definitions.
- Passes geometry as cutlass.Constexpr to CuTe-DSL k... | [] | null | null |
flashinfer | 75e834d633bc87267accc6e3f9749d18e459566a | 2026-08-25T09:23:27-07:00 | 4,708 | https://github.com/flashinfer-ai/flashinfer/pull/4708 | (perf) add fused_GDN_step support for Qwen 3.6 35B A3B on sm120 (#4708) | (perf) add fused_GDN_step support for Qwen 3.6 35B A3B on sm120 (#4708)
<!-- .github/pull_request_template.md -->
## 📌 Description
Follow up with #4481
- Adds Qwen3.6-35B-A3B support at batches 1/2/4 for both CUDA and
CuTe-DSL implementations.
- Generates one geometry-specific CUDA JIT module using FI_GDN_* compil... | flashinfer/gdn_kernels/experimental/kernel/gdn_fused_decode_sm120.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2026 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2026 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- flashinfer/gdn_kernels/experimental/kernel/gdn_fused_decode_sm120.cu
+++ flashinfer/gdn_kernels/experimental/kernel/gdn_fused_decode_sm120.cu
@@ -24,23 +24,54 @@
namespace {
-// Fused GDN decode step for a fixed traced layer geometry: one persistent
-// kernel covering the in_proj_ba GEMV, the depthwise causal... | 48 | 17 | 6 | [
"qwen"
] | [
"SM120"
] | [] | Optimize this cuda kernel file from flashinfer (flashinfer/gdn_kernels/experimental/kernel/gdn_fused_decode_sm120.cu).
Goal: (perf) add fused_GDN_step support for Qwen 3.6 35B A3B on sm120
Target hardware: SM120
Target models: qwen
Current file:
```cuda
/*
* Copyright (c) 2026 by FlashInfer team.
*
* Licensed unde... | <!-- .github/pull_request_template.md -->
## 📌 Description
Follow up with #4481
- Adds Qwen3.6-35B-A3B support at batches 1/2/4 for both CUDA and CuTe-DSL implementations.
- Generates one geometry-specific CUDA JIT module using FI_GDN_* compile definitions.
- Passes geometry as cutlass.Constexpr to CuTe-DSL k... | [] | null | null |
flashinfer | f47f2d254d78afb7bf4600170f007edd4a6b556e | 2026-08-24T19:31:00+08:00 | 4,699 | https://github.com/flashinfer-ai/flashinfer/pull/4699 | perf(gdn): reduce non-CP CuTeDSL launch overhead (#4699) | perf(gdn): reduce non-CP CuTeDSL launch overhead (#4699)
Cache SM90 and SM120 non-CP kernel objects and compile options, and
construct CuTe tensor wrappers only during compilation. Replay compiled
kernels through raw TVM-FFI arguments to remove repeated launch
preparation from the eager path.
follow up of #4374 for n... | flashinfer/gdn_kernels/delta_rule_dsl/delta_rule_sm120.py | cute_dsl | Apache-2.0 | from enum import IntEnum
import torch
import cutlass
import cutlass.cute as cute
import cutlass.pipeline as pipeline
from cutlass.cute.nvgpu import warp, warpgroup, cpasync
from ...utils import get_device_sm_count, _get_cache_buf
from .alpha import AlphaProcessor
from .collective_store_tma import CollectiveStoreTma
fr... | import functools
from enum import IntEnum
import torch
import cutlass
import cutlass.cute as cute
import cutlass.pipeline as pipeline
from cutlass.cute.nvgpu import warp, warpgroup, cpasync
from ...utils import get_device_sm_count, _get_cache_buf
from .alpha import AlphaProcessor
from .collective_store_tma import Coll... | --- flashinfer/gdn_kernels/delta_rule_dsl/delta_rule_sm120.py
+++ flashinfer/gdn_kernels/delta_rule_dsl/delta_rule_sm120.py
@@ -1,3 +1,4 @@
+import functools
from enum import IntEnum
import torch
@@ -11,12 +12,18 @@
from .custom_compile_cache import (
KeyedCompileMixin,
cached_compile,
+ get_cached_co... | 135 | 88 | 2 | [] | [
"SM120",
"SM90"
] | [] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/gdn_kernels/delta_rule_dsl/delta_rule_sm120.py).
Goal: perf(gdn): reduce non-CP CuTeDSL launch overhead
Target hardware: SM120, SM90
Target models: unspecified
Current file:
```python
from enum import IntEnum
import torch
import cutlass
import cutlass.cu... | ## 📌 Description
Cache SM90 and SM120 non-CP kernel objects and compile options, and construct CuTe tensor wrappers only during compilation. Replay compiled kernels through raw TVM-FFI arguments to remove repeated launch preparation from the eager path.
follow up of #4374 for non-CP launch path.
## 🔍 Related Issue... | [] | null | null |
flashinfer | f47f2d254d78afb7bf4600170f007edd4a6b556e | 2026-08-24T19:31:00+08:00 | 4,699 | https://github.com/flashinfer-ai/flashinfer/pull/4699 | perf(gdn): reduce non-CP CuTeDSL launch overhead (#4699) | perf(gdn): reduce non-CP CuTeDSL launch overhead (#4699)
Cache SM90 and SM120 non-CP kernel objects and compile options, and
construct CuTe tensor wrappers only during compilation. Replay compiled
kernels through raw TVM-FFI arguments to remove repeated launch
preparation from the eager path.
follow up of #4374 for n... | flashinfer/gdn_kernels/delta_rule_dsl/delta_rule_sm90.py | cute_dsl | Apache-2.0 | from enum import IntEnum
import torch
import cutlass
import cutlass.cute as cute
import cutlass.pipeline as pipeline
from cutlass.cute.nvgpu import warp, warpgroup, cpasync
from ...utils import get_device_sm_count, _get_cache_buf
from .alpha import AlphaProcessor
from .collective_store_tma import CollectiveStoreTma
fr... | import functools
from enum import IntEnum
import torch
import cutlass
import cutlass.cute as cute
import cutlass.pipeline as pipeline
from cutlass.cute.nvgpu import warp, warpgroup, cpasync
from ...utils import get_device_sm_count, _get_cache_buf
from .alpha import AlphaProcessor
from .collective_store_tma import Coll... | --- flashinfer/gdn_kernels/delta_rule_dsl/delta_rule_sm90.py
+++ flashinfer/gdn_kernels/delta_rule_dsl/delta_rule_sm90.py
@@ -1,3 +1,4 @@
+import functools
from enum import IntEnum
import torch
@@ -8,11 +9,14 @@
from ...utils import get_device_sm_count, _get_cache_buf
from .alpha import AlphaProcessor
from .coll... | 134 | 89 | 2 | [] | [
"SM120",
"SM90"
] | [] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/gdn_kernels/delta_rule_dsl/delta_rule_sm90.py).
Goal: perf(gdn): reduce non-CP CuTeDSL launch overhead
Target hardware: SM120, SM90
Target models: unspecified
Current file:
```python
from enum import IntEnum
import torch
import cutlass
import cutlass.cut... | ## 📌 Description
Cache SM90 and SM120 non-CP kernel objects and compile options, and construct CuTe tensor wrappers only during compilation. Replay compiled kernels through raw TVM-FFI arguments to remove repeated launch preparation from the eager path.
follow up of #4374 for non-CP launch path.
## 🔍 Related Issue... | [] | null | null |
flashinfer | b5993208e1ff5b86330e449ef270de15033e048f | 2026-08-23T14:59:58-07:00 | 4,686 | https://github.com/flashinfer-ai/flashinfer/pull/4686 | perf(gemm): optimize CuTe DSL W4A16 dense GEMM (#4686) | perf(gemm): optimize CuTe DSL W4A16 dense GEMM (#4686)
<!-- .github/pull_request_template.md -->
## 📌 Description
@humansand
This optimizes the SM100/SM103 CuTe DSL dense W4A16 `mm_bf16_fp4` path
added by #4466.
- Compile the SM100/SM103 dense kernel at CuTe optimizer level 3 instead
of its explicit level-2 overr... | flashinfer/gemm/gemm_bf16_fp4_cute_dsl.py | cute_dsl | Apache-2.0 | # SPDX-FileCopyrightText: Copyright (c) 2025 by FlashInfer team.
# SPDX-License-Identifier: Apache-2.0
"""Architecture-specific CuTe-DSL backend for the BF16 x NVFP4 GEMM."""
import functools
from typing import Dict, List, Optional, Tuple, cast
import torch
from ..autotuner import (
AutoTuner,
ConstraintSpec... | # SPDX-FileCopyrightText: Copyright (c) 2025 by FlashInfer team.
# SPDX-License-Identifier: Apache-2.0
"""Architecture-specific CuTe-DSL backend for the BF16 x NVFP4 GEMM."""
import functools
from typing import Dict, List, Optional, Tuple, cast
import torch
from ..autotuner import (
AutoTuner,
ConstraintSpec... | --- flashinfer/gemm/gemm_bf16_fp4_cute_dsl.py
+++ flashinfer/gemm/gemm_bf16_fp4_cute_dsl.py
@@ -606,7 +606,6 @@
_SM100_BF16_FP4_N_TILES = (8, 16, 32, 64, 128, 192)
_SM100_BF16_FP4_K_TILE = 256
-_SM100_BF16_FP4_RASTER_ALONG_M = True
def _sm100_bf16_fp4_tactic_configs() -> List[Tuple]:
@@ -627,13 +626,14 @@
... | 8 | 8 | 1 | [] | [
"B200",
"B300",
"SM100",
"SM103"
] | [
"8 x",
"1.0x",
"1.059962x",
"1.058944x",
"1.060623x",
"1.058814x",
"1.021585x",
"1.023894x",
"1.003731x",
"1.004513x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/gemm/gemm_bf16_fp4_cute_dsl.py).
Goal: perf(gemm): optimize CuTe DSL W4A16 dense GEMM
Target hardware: B200, B300, SM100, SM103
Target models: unspecified
Current file:
```python
# SPDX-FileCopyrightText: Copyright (c) 2025 by FlashInfer team.
# SPDX-Lice... | <!-- .github/pull_request_template.md -->
## 📌 Description
@humansand
This optimizes the SM100/SM103 CuTe DSL dense W4A16 `mm_bf16_fp4` path added by #4466.
- Compile the SM100/SM103 dense kernel at CuTe optimizer level 3 instead of its explicit level-2 override. SM12x compilation is unchanged.
- Make raster direc... | [{"scope": "kernel", "hardware": "B300", "model": null, "shape": "N=6656,K=19968", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 57.441, "optimized": 54.176, "stated_speedup": 1.059962, "speedup": 1.0603}, {"scope": "kernel", "hardware": "B300", "model": null, "shape": "N=66... | 1.0248 | null |
flashinfer | 6cbe7f17da27e3b8e497b9569aa7d1159313132f | 2026-08-19T19:20:33-07:00 | 4,587 | https://github.com/flashinfer-ai/flashinfer/pull/4587 | feat(cake_backend): accelerate DeepSeek fused routing (#4587) | feat(cake_backend): accelerate DeepSeek fused routing (#4587)
| Shape
([#4254](https://github.com/flashinfer-ai/flashinfer/issues/4254)) |
B200 Cake/FlashInfer | GB300 Cake/FlashInfer (original) |
Cake/Sonic-derived exact graph (B200 / GB300; upstream native exact API
unsupported) |
| --- | ---: | ---: | ---: |
| T1 E... | csrc/fused_moe/noAuxTcKernels.cu | cuda | Apache-2.0 | #include <cooperative_groups.h>
#include <cooperative_groups/reduce.h>
#include <cmath>
#include "flashinfer/trtllm/fused_moe/noAuxTcKernels.h"
#include "moeTopKFuncs.cuh"
#include "tensorrt_llm/common/cudaTypeUtils.cuh"
#include "tensorrt_llm/common/envUtils.h"
#include "tvm_ffi_utils.h"
using tvm::ffi::Optional;
... | #include <cooperative_groups.h>
#include <cooperative_groups/reduce.h>
#include <cmath>
#include "flashinfer/trtllm/fused_moe/noAuxTcKernels.h"
#include "moeTopKFuncs.cuh"
#include "tensorrt_llm/common/cudaTypeUtils.cuh"
#include "tensorrt_llm/common/envUtils.h"
#include "tvm_ffi_utils.h"
#ifdef FLASHINFER_CAKE_BACK... | --- csrc/fused_moe/noAuxTcKernels.cu
+++ csrc/fused_moe/noAuxTcKernels.cu
@@ -8,6 +8,11 @@
#include "tensorrt_llm/common/cudaTypeUtils.cuh"
#include "tensorrt_llm/common/envUtils.h"
#include "tvm_ffi_utils.h"
+
+#ifdef FLASHINFER_CAKE_BACKEND
+#include "cake_deepseek_fused_routing/cake_deepseek_fused_routing_kernels... | 30 | 0 | 3 | [
"deepseek"
] | [
"B200",
"GB300"
] | [
"1.1829x",
"1.5522x",
"7.6589x",
"9.3881x",
"1.1059x",
"1.3919x",
"14.4118x",
"18.3243x",
"1.0440x",
"1.3158x"
] | Optimize this cuda kernel file from flashinfer (csrc/fused_moe/noAuxTcKernels.cu).
Goal: feat(cake_backend): accelerate DeepSeek fused routing
Target hardware: B200, GB300
Target models: deepseek
Current file:
```cuda
#include <cooperative_groups.h>
#include <cooperative_groups/reduce.h>
#include <cmath>
#include "... | Developed by the **CAKE team**, the kernels in this PR **outperform** the relevant **SOTA baselines at the time of merge** on the **vast majority of performance benchmark shapes**, matching them otherwise.
| Shape ([#4254](https://github.com/flashinfer-ai/flashinfer/issues/4254)) | B200 CAKE speedup vs FlashInfer base... | [{"scope": "kernel", "hardware": "B200", "model": null, "shape": "T1 E384 k1 G1 kg1 f32/f32", "batch_size": 1, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.1829, "speedup": 1.1829}, {"scope": "kernel", "hardware": "GB300", "model": null, "shape": ... | 1.2101 | 1.0006 |
flashinfer | 7319c448b7a62fb8deb3de2c878794194cb23558 | 2026-08-18T13:37:43-07:00 | 4,540 | https://github.com/flashinfer-ai/flashinfer/pull/4540 | perf(moe): fold W4A16 SiTU reciprocals (#4540) | perf(moe): fold W4A16 SiTU reciprocals (#4540)
<!-- .github/pull_request_template.md -->
## 📌 Description
@humansand
This is a focused follow-up to #4394 and #4506 for the CuTe DSL W4A16
SiTU path.
- Preserve `situ_beta` as a Python scalar so the existing shared
`situ_f32` helper folds its FP32 reciprocal while t... | flashinfer/fused_moe/cute_dsl/blackwell/moe_w4a16_kernel.py | cute_dsl | BSD-3-Clause | # Copyright (c) 2025 - 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Identifier: BSD-3-Clause
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# 1. Redistributions of source code must retain t... | # Copyright (c) 2025 - 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Identifier: BSD-3-Clause
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# 1. Redistributions of source code must retain t... | --- flashinfer/fused_moe/cute_dsl/blackwell/moe_w4a16_kernel.py
+++ flashinfer/fused_moe/cute_dsl/blackwell/moe_w4a16_kernel.py
@@ -59,6 +59,7 @@
from .moe_w4a16_utils import decode_nvfp4_fragment_to_bf16
from .utils import (
blk_reduce_bf16,
+ f32_reciprocal,
fmin,
gelu_tanh_f32,
griddepcontro... | 10 | 3 | 1 | [
"kimi"
] | [
"B200",
"B300",
"BLACKWELL",
"SM103"
] | [
"8 x",
"1.0x",
"1.0064x",
"1.0067x",
"1.0099x",
"1.0018x",
"1.0421x",
"1.0914x",
"1.0644x",
"1.0421x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/fused_moe/cute_dsl/blackwell/moe_w4a16_kernel.py).
Goal: perf(moe): fold W4A16 SiTU reciprocals
Target hardware: B200, B300, BLACKWELL, SM103
Target models: kimi
Current file:
```python
# Copyright (c) 2025 - 2026 NVIDIA CORPORATION & AFFILIATES. All righ... | <!-- .github/pull_request_template.md -->
## 📌 Description
@humansand
This is a focused follow-up to #4394 and #4506 for the CuTe DSL W4A16 SiTU path.
- Preserve `situ_beta` as a Python scalar so the existing shared `situ_f32` helper folds its FP32 reciprocal while tracing.
- Precompute the optional up-branch reci... | [{"scope": "kernel", "hardware": "B200", "model": null, "shape": "E=896,H=3584,I=3072,situ_beta=4.0,situ_linear_beta=25.0", "batch_size": 2048, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 5.683264, "optimized": 5.453744, "stated_speedup": 1.0421, "speedup": 1.0421}, {"scope": "kernel", "ha... | 1.0621 | null |
flashinfer | 3f5acea9cf8a738724f7a07b4d8b1ae4a4fa25e5 | 2026-08-14T13:39:52-07:00 | 4,506 | https://github.com/flashinfer-ai/flashinfer/pull/4506 | perf(moe): fold the SiTU beta reciprocal in the CuTe DSL MoE epilogue (#4506) | perf(moe): fold the SiTU beta reciprocal in the CuTe DSL MoE epilogue (#4506)
`x / beta` in the SiTU gate and up branches lowers to a per-element
`div.rn.f32`: folding it to `x * (1/beta)` is only legal when `1/beta`
is
exact, which the SiTU betas (e.g. Kimi-K3's 25.0) are not. Compute the
reciprocal at trace time an... | flashinfer/fused_moe/cute_dsl/blackwell/utils.py | cute_dsl | Apache-2.0 | # Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Identifier: Apache-2.0
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/lice... | # Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Identifier: Apache-2.0
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/lice... | --- flashinfer/fused_moe/cute_dsl/blackwell/utils.py
+++ flashinfer/fused_moe/cute_dsl/blackwell/utils.py
@@ -252,6 +252,18 @@
) - cutlass.Float32(1.0)
+def f32_reciprocal(value: float) -> float:
+ """Return ``1 / fp32(value)``, rounded to fp32.
+
+ The reciprocal must come from the same fp32 value the k... | 19 | 1 | 2 | [
"kimi"
] | [
"B200",
"BLACKWELL"
] | [] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/fused_moe/cute_dsl/blackwell/utils.py).
Goal: perf(moe): fold the SiTU beta reciprocal in the CuTe DSL MoE epilogue
Target hardware: B200, BLACKWELL
Target models: kimi
Current file:
```python
# Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All righ... | `x / beta` in the SiTU gate and up branches lowers to a per-element
`div.rn.f32`: folding it to `x * (1/beta)` is only legal when `1/beta` is
exact, which the SiTU betas (e.g. Kimi-K3's 25.0) are not. Compute the
reciprocal at trace time and multiply instead.
`f32_reciprocal` derives it from the fp32 beta the kernel ... | [{"scope": "kernel", "hardware": "B200", "model": "Kimi-K3 MoE", "shape": "E=896,topK=16,hidden=3584,intermediate=3072", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 123, "optimized": 77, "stated_speedup": null, "speedup": 1.5974}, {"scope": "kernel", "hardware": "B200", "m... | 1.64 | null |
flashinfer | ba6bf4e5b63b299952afaa768c1caa863829f309 | 2026-08-14T01:59:27+08:00 | 4,444 | https://github.com/flashinfer-ai/flashinfer/pull/4444 | perf(gdn): reuse pretranspose kernels across pool capacity and stride (#4444) | perf(gdn): reuse pretranspose kernels across pool capacity and stride (#4444)
## 📌 Description
Make the leading pool dimension of the GDN pretranspose path dynamic:
- Treat pool capacity and `stride[0]` as runtime values.
- Keep `HV/V/K` and inner strides compile-time static.
- Remove pool capacity and leading stri... | flashinfer/gdn_kernels/gdn_decode_pretranspose.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/gdn_kernels/gdn_decode_pretranspose.py
+++ flashinfer/gdn_kernels/gdn_decode_pretranspose.py
@@ -905,8 +905,6 @@
scale: float,
use_qk_l2norm: bool,
use_pool_indexing: bool = False,
- pool_size: int = 0,
- stride0: int = 0,
stride1: int = 0,
stride2: int = 0,
stride3: i... | 19 | 8 | 1 | [] | [
"H800",
"RTX5090",
"SM120",
"SM90"
] | [] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/gdn_kernels/gdn_decode_pretranspose.py).
Goal: perf(gdn): reuse pretranspose kernels across pool capacity and stride
Target hardware: H800, RTX5090, SM120, SM90
Target models: unspecified
Current file:
```python
"""
Copyright (c) 2025 by FlashInfer team.
... | ## 📌 Description
Make the leading pool dimension of the GDN pretranspose path dynamic:
- Treat pool capacity and `stride[0]` as runtime values.
- Keep `HV/V/K` and inner strides compile-time static.
- Remove pool capacity and leading stride from the compilation cache key.
- Preserve 64-bit pool-offset arithmetic.
T... | [{"scope": "e2e", "hardware": "H800/SM90a and RTX 5090/SM120", "model": null, "shape": null, "batch_size": null, "metric": "cold compilation time", "unit": null, "higher_is_better": false, "baseline": null, "optimized": null, "stated_speedup": 1.62, "speedup": 1.62}] | null | 1.62 |
flashinfer | 53a1c3bd7a3f384d3a8fd1261cc99d80bcf9d188 | 2026-08-12T20:56:49-07:00 | 4,038 | https://github.com/flashinfer-ai/flashinfer/pull/4038 | perf(gemm): split-K, occupancy, and m=1 stream-GEMV decode tactics for mm_bf16_fp4 (#4038) | perf(gemm): split-K, occupancy, and m=1 stream-GEMV decode tactics for mm_bf16_fp4 (#4038)
## 📌 Description
#3597 added `mm_bf16_fp4` (bf16 activations x nvfp4 weights) so vLLM can
replace Marlin, its default W4A16 backend, with a FlashInfer kernel; DGX
Spark is the lead target. On decode shapes the kernel trailed M... | flashinfer/gemm/gemm_bf16_fp4_cute_dsl.py | cute_dsl | Apache-2.0 | # SPDX-FileCopyrightText: Copyright (c) 2025 by FlashInfer team.
# SPDX-License-Identifier: Apache-2.0
"""CuTe-DSL backend for the bf16 x fp4 GEMM (weight repack / kernel launch)."""
from typing import List, Optional, Tuple, cast
import torch
from ..autotuner import (
AutoTuner,
ConstraintSpec,
DynamicTe... | # SPDX-FileCopyrightText: Copyright (c) 2025 by FlashInfer team.
# SPDX-License-Identifier: Apache-2.0
"""CuTe-DSL backend for the bf16 x fp4 GEMM (weight repack / kernel launch)."""
import functools
from typing import List, Optional, Tuple, cast
import torch
from ..autotuner import (
AutoTuner,
ConstraintSp... | --- flashinfer/gemm/gemm_bf16_fp4_cute_dsl.py
+++ flashinfer/gemm/gemm_bf16_fp4_cute_dsl.py
@@ -2,6 +2,7 @@
# SPDX-License-Identifier: Apache-2.0
"""CuTe-DSL backend for the bf16 x fp4 GEMM (weight repack / kernel launch)."""
+import functools
from typing import List, Optional, Tuple, cast
import torch
@@ -18,6... | 306 | 16 | 2 | [
"qwen",
"llama"
] | [
"RTX5080"
] | [
"1.011x",
"1.11x",
"1.014x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/gemm/gemm_bf16_fp4_cute_dsl.py).
Goal: perf(gemm): split-K, occupancy, and m=1 stream-GEMV decode tactics for mm_bf16_fp4
Target hardware: RTX5080
Target models: qwen, llama
Current file:
```python
# SPDX-FileCopyrightText: Copyright (c) 2025 by FlashInfe... | ## 📌 Description
#3597 added `mm_bf16_fp4` (bf16 activations x nvfp4 weights) so vLLM can replace Marlin, its default W4A16 backend, with a FlashInfer kernel; DGX Spark is the lead target. On decode shapes the kernel trailed Marlin for two reasons: small-n grids underfill the GPU, and at single-token batches (m=1) to... | [{"scope": "kernel", "hardware": "RTX PRO 6000", "model": null, "shape": "n=2048,k=7168", "batch_size": 1, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": 0.57, "optimized": 1.36, "stated_speedup": null, "speedup": 2.386}, {"scope": "kernel", "hardware": "DGX Spark", "model": null, "shape": "n=... | 1.3857 | 1.08 |
flashinfer | 53a1c3bd7a3f384d3a8fd1261cc99d80bcf9d188 | 2026-08-12T20:56:49-07:00 | 4,038 | https://github.com/flashinfer-ai/flashinfer/pull/4038 | perf(gemm): split-K, occupancy, and m=1 stream-GEMV decode tactics for mm_bf16_fp4 (#4038) | perf(gemm): split-K, occupancy, and m=1 stream-GEMV decode tactics for mm_bf16_fp4 (#4038)
## 📌 Description
#3597 added `mm_bf16_fp4` (bf16 activations x nvfp4 weights) so vLLM can
replace Marlin, its default W4A16 backend, with a FlashInfer kernel; DGX
Spark is the lead target. On decode shapes the kernel trailed M... | flashinfer/gemm/kernels/cute_dsl/dense_gemm_bf16_fp4_blackwell.py | cute_dsl | BSD-3-Clause | # Copyright (c) 2025 - 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Identifier: BSD-3-Clause
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain... | # Copyright (c) 2025 - 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Identifier: BSD-3-Clause
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain... | --- flashinfer/gemm/kernels/cute_dsl/dense_gemm_bf16_fp4_blackwell.py
+++ flashinfer/gemm/kernels/cute_dsl/dense_gemm_bf16_fp4_blackwell.py
@@ -161,6 +161,8 @@
enable_pdl: bool = True,
tile_swizzle: int = 1,
raster_along_m: bool = True,
+ k_splits: int = 1,
+ occupancy: int = 1,... | 270 | 138 | 2 | [
"qwen",
"llama"
] | [
"RTX5080"
] | [
"1.011x",
"1.11x",
"1.014x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/gemm/kernels/cute_dsl/dense_gemm_bf16_fp4_blackwell.py).
Goal: perf(gemm): split-K, occupancy, and m=1 stream-GEMV decode tactics for mm_bf16_fp4
Target hardware: RTX5080
Target models: qwen, llama
Current file:
```python
# Copyright (c) 2025 - 2026 NVIDI... | ## 📌 Description
#3597 added `mm_bf16_fp4` (bf16 activations x nvfp4 weights) so vLLM can replace Marlin, its default W4A16 backend, with a FlashInfer kernel; DGX Spark is the lead target. On decode shapes the kernel trailed Marlin for two reasons: small-n grids underfill the GPU, and at single-token batches (m=1) to... | [{"scope": "kernel", "hardware": "RTX PRO 6000", "model": null, "shape": "n=2048,k=7168", "batch_size": 1, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": 0.57, "optimized": 1.36, "stated_speedup": null, "speedup": 2.386}, {"scope": "kernel", "hardware": "DGX Spark", "model": null, "shape": "n=... | 1.3857 | 1.08 |
flashinfer | e9fb62b74e47444eba83da71a573c9437e71cb3b | 2026-08-11T18:29:38+08:00 | 3,761 | https://github.com/flashinfer-ai/flashinfer/pull/3761 | perf(moe): optimize CUTLASS fused MoE mem-bound kernels (#3761) | perf(moe): optimize CUTLASS fused MoE mem-bound kernels (#3761)
<!-- .github/pull_request_template.md -->
## 📌 Description
### Key Findings
We observed that the Triton implementation outperforms the FlashInfer
CUTLASS fused MoE backend on Hopper for BF16 data types (#3521), and
thus we started investigating kernel... | csrc/nv_internal/include/tensorrt_llm/common/cudaUtils.h | cpp | Apache-2.0 | /*
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights
* reserved. SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the Lic... | /*
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights
* reserved. SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the Lic... | --- csrc/nv_internal/include/tensorrt_llm/common/cudaUtils.h
+++ csrc/nv_internal/include/tensorrt_llm/common/cudaUtils.h
@@ -388,12 +388,16 @@
return (tmp_a + tmp_b - 1) / tmp_b;
}
-inline int roundUp(int a, int b) { return divUp(a, b) * b; }
-
template <typename T, typename U, typename = std::enable_if_t<std::... | 6 | 2 | 3 | [
"deepseek",
"qwen",
"mixtral"
] | [
"HOPPER",
"SM100"
] | [
"4×",
"4×",
"1×",
"1×",
"4×",
"1×",
"8×",
"2×",
"1.08x",
"1.00x"
] | Optimize this cpp kernel file from flashinfer (csrc/nv_internal/include/tensorrt_llm/common/cudaUtils.h).
Goal: perf(moe): optimize CUTLASS fused MoE mem-bound kernels
Target hardware: HOPPER, SM100
Target models: deepseek, qwen, mixtral
Current file:
```cpp
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDI... | <!-- .github/pull_request_template.md -->
## 📌 Description
### Key Findings
We observed that the Triton implementation outperforms the FlashInfer CUTLASS fused MoE backend on Hopper for BF16 data types (#3521), and thus we started investigating kernel optimization opportunities related to the associated kernels. He... | [{"scope": "e2e", "hardware": "B100", "model": "qwen3_tp1", "shape": null, "batch_size": 1, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": 1.0, "optimized": 1.0, "stated_speedup": 1.0, "speedup": 1.0}, {"scope": "e2e", "hardware": "B100", "model": "qwen3_tp1", "shape": null, "batch_size": 16, ... | null | 1 |
flashinfer | e9fb62b74e47444eba83da71a573c9437e71cb3b | 2026-08-11T18:29:38+08:00 | 3,761 | https://github.com/flashinfer-ai/flashinfer/pull/3761 | perf(moe): optimize CUTLASS fused MoE mem-bound kernels (#3761) | perf(moe): optimize CUTLASS fused MoE mem-bound kernels (#3761)
<!-- .github/pull_request_template.md -->
## 📌 Description
### Key Findings
We observed that the Triton implementation outperforms the FlashInfer
CUTLASS fused MoE backend on Hopper for BF16 data types (#3521), and
thus we started investigating kernel... | include/flashinfer/trtllm/common/cudaUtils.h | cpp | Apache-2.0 | /*
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights
* reserved. SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the Lic... | /*
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights
* reserved. SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the Lic... | --- include/flashinfer/trtllm/common/cudaUtils.h
+++ include/flashinfer/trtllm/common/cudaUtils.h
@@ -154,12 +154,16 @@
return (tmp_a + tmp_b - 1) / tmp_b;
}
-inline int roundUp(int a, int b) { return divUp(a, b) * b; }
-
template <typename T, typename U, typename = std::enable_if_t<std::is_integral<T>::value>,
... | 6 | 2 | 3 | [
"deepseek",
"qwen",
"mixtral"
] | [
"HOPPER",
"SM100"
] | [
"4×",
"4×",
"1×",
"1×",
"4×",
"1×",
"8×",
"2×",
"1.08x",
"1.00x"
] | Optimize this cpp kernel file from flashinfer (include/flashinfer/trtllm/common/cudaUtils.h).
Goal: perf(moe): optimize CUTLASS fused MoE mem-bound kernels
Target hardware: HOPPER, SM100
Target models: deepseek, qwen, mixtral
Current file:
```cpp
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATIO... | <!-- .github/pull_request_template.md -->
## 📌 Description
### Key Findings
We observed that the Triton implementation outperforms the FlashInfer CUTLASS fused MoE backend on Hopper for BF16 data types (#3521), and thus we started investigating kernel optimization opportunities related to the associated kernels. He... | [{"scope": "e2e", "hardware": "B100", "model": "qwen3_tp1", "shape": null, "batch_size": 1, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": 1.0, "optimized": 1.0, "stated_speedup": 1.0, "speedup": 1.0}, {"scope": "e2e", "hardware": "B100", "model": "qwen3_tp1", "shape": null, "batch_size": 16, ... | null | 1 |
flashinfer | f527314b25b9701a4d23ba0bf89e225be62780a0 | 2026-08-11T01:05:12-04:00 | 4,416 | https://github.com/flashinfer-ai/flashinfer/pull/4416 | perf(norm): speed up fused add RMSNorm FP4 quantization (#4416) | perf(norm): speed up fused add RMSNorm FP4 quantization (#4416)
<!-- .github/pull_request_template.md -->
## 📌 Description
This PR improves the fused add + RMSNorm + FP4 quantization kernel by:
- Deriving row parallelism from the number of FP4 scale-factor blocks.
- Using vectorized shared-memory loads and pac... | flashinfer/cute_dsl/add_rmsnorm_fp4quant.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/cute_dsl/add_rmsnorm_fp4quant.py
+++ flashinfer/cute_dsl/add_rmsnorm_fp4quant.py
@@ -54,6 +54,8 @@
# PTX intrinsics - basic ops
st_global_u64,
get_ptr_as_int64,
+ get_smem_ptr_as_int32,
+ ld_shared_v4_u32,
rcp_approx_ftz,
fmin_f32,
fmax_f32,
@@ -88,6 +90,31 @@
)
+... | 93 | 30 | 1 | [] | [] | [] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/cute_dsl/add_rmsnorm_fp4quant.py).
Goal: perf(norm): speed up fused add RMSNorm FP4 quantization
Target hardware: unspecified
Target models: unspecified
Current file:
```python
"""
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License,... | <!-- .github/pull_request_template.md -->
## 📌 Description
This PR improves the fused add + RMSNorm + FP4 quantization kernel by:
- Deriving row parallelism from the number of FP4 scale-factor blocks.
- Using vectorized shared-memory loads and packed BF16/FP16 operations for the block-size-16 single-CTA path.... | [] | null | null |
flashinfer | 29196cf437778906c72630dc5d9850de547501de | 2026-08-08T23:41:33+08:00 | 4,331 | https://github.com/flashinfer-ai/flashinfer/pull/4331 | perf(moe): persist b12x MoE CuTe-DSL kernels to the disk cache (#4331) | perf(moe): persist b12x MoE CuTe-DSL kernels to the disk cache (#4331)
## 📌 Description
Rolls the on-disk CuTe-DSL kernel cache out to the three sm12x NVFP4
fused-MoE kernels (micro,
static, dynamic), addressing #4317. The infrastructure landed in #3874 /
#4029; @bkryu noted in
#4317 that it still had to reach indiv... | flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_dispatch.py | cute_dsl | Apache-2.0 | """SM120/SM121 MoE dispatch layer — workspace, compilation, and launch.
Ported from b12x's integration/tp_moe.py. Supports micro (tiny decode),
static (decode), and dynamic (prefill) backends with token-count-based
selection.
"""
from __future__ import annotations
import os
import weakref
from dataclasses import dat... | """SM120/SM121 MoE dispatch layer — workspace, compilation, and launch.
Ported from b12x's integration/tp_moe.py. Supports micro (tiny decode),
static (decode), and dynamic (prefill) backends with token-count-based
selection.
"""
from __future__ import annotations
import hashlib
import os
import weakref
from datacla... | --- flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_dispatch.py
+++ flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_dispatch.py
@@ -7,6 +7,7 @@
from __future__ import annotations
+import hashlib
import os
import weakref
from dataclasses import dataclass
@@ -19,11 +20,11 @@
from flashinfer.cute_dsl.utils im... | 371 | 156 | 1 | [] | [
"SM120",
"SM121"
] | [
"135×"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_dispatch.py).
Goal: perf(moe): persist b12x MoE CuTe-DSL kernels to the disk cache
Target hardware: SM120, SM121
Target models: unspecified
Current file:
```python
"""SM120/SM121 MoE dispatch layer — workspace, compi... | ## 📌 Description
Rolls the on-disk CuTe-DSL kernel cache out to the three sm12x NVFP4 fused-MoE kernels (micro,
static, dynamic), addressing #4317. The infrastructure landed in #3874 / #4029; @bkryu noted in
#4317 that it still had to reach individual kernels and that the core team lacked bandwidth, so this
applies i... | [{"scope": "e2e", "hardware": "GB10", "model": null, "shape": null, "batch_size": null, "metric": "compile + load time", "unit": "s", "higher_is_better": false, "baseline": 17.92, "optimized": 0.13, "stated_speedup": 135, "speedup": 137.8462}, {"scope": "e2e", "hardware": "GB10", "model": null, "shape": null, "batch_si... | null | 135.9007 |
flashinfer | 553c2280a88581c7ede39aa571a54d1232854b81 | 2026-08-07T18:17:26+08:00 | 4,329 | https://github.com/flashinfer-ai/flashinfer/pull/4329 | feat: optimize gated SM12x dynamic NVFP4 MoE (#4329) | feat: optimize gated SM12x dynamic NVFP4 MoE (#4329)
Route gated activations through the optimized branch-paired dynamic
kernel while preserving the generic fallback for non-gated activations.
Support SiLU, GELU-tanh, and SwiGLU-OAI without an environment toggle.
<!-- .github/pull_request_template.md -->
## 📌 Descri... | flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_dispatch.py | cute_dsl | Apache-2.0 | """SM120/SM121 MoE dispatch layer — workspace, compilation, and launch.
Ported from b12x's integration/tp_moe.py. Supports micro (tiny decode),
static (decode), and dynamic (prefill) backends with token-count-based
selection.
"""
from __future__ import annotations
import os
import weakref
from dataclasses import dat... | """SM120/SM121 MoE dispatch layer — workspace, compilation, and launch.
Ported from b12x's integration/tp_moe.py. Supports micro (tiny decode),
static (decode), and dynamic (prefill) backends with token-count-based
selection.
"""
from __future__ import annotations
import os
import weakref
from dataclasses import dat... | --- flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_dispatch.py
+++ flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_dispatch.py
@@ -31,7 +31,11 @@
compile_direct_micro_kernel,
compiled_direct_micro_accepts_block_dim,
)
-from .moe_dynamic_kernel import _TASK_SLICE_CHUNK, MoEDynamicKernel
+from .moe_dynami... | 14 | 2 | 2 | [
"qwen"
] | [
"BLACKWELL",
"SM120",
"SM121"
] | [] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_dispatch.py).
Goal: feat: optimize gated SM12x dynamic NVFP4 MoE
Target hardware: BLACKWELL, SM120, SM121
Target models: qwen
Current file:
```python
"""SM120/SM121 MoE dispatch layer — workspace, compilation, and la... | Route gated activations through the optimized branch-paired dynamic kernel while preserving the generic fallback for non-gated activations. Support SiLU, GELU-tanh, and SwiGLU-OAI without an environment toggle.
<!-- .github/pull_request_template.md -->
## 📌 Description
This PR integrates an optimized branch-paired d... | [{"scope": "e2e", "hardware": "NVIDIA RTX PRO 5000 72GB Blackwell, SM120", "model": "Qwen3.5-35B TP1", "shape": null, "batch_size": 4096, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 1012.692, "optimized": 586.782, "stated_speedup": null, "speedup": 1.7258}, {"scope": "e2e", "hardware": "NV... | null | 1.5078 |
flashinfer | d9c97ac13247a30f5bbc29d39f88d6a415bb7dca | 2026-08-05T10:19:40-07:00 | 4,295 | https://github.com/flashinfer-ai/flashinfer/pull/4295 | perf(topk): skip output index sort for tie-break selection (#4295) | perf(topk): skip output index sort for tie-break selection (#4295)
<!-- .github/pull_request_template.md -->
## 📌 Description
@humansand
Follow-up to #3095.
`tie_break` determines which equal-valued elements are selected at the
top-k boundary. Today, requesting a tie-break also promotes the public
`deterministic`... | csrc/topk.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/topk.cu
+++ csrc/topk.cu
@@ -57,9 +57,6 @@
cudaError_t status;
auto dtype = input.dtype();
sampling::TopKTieBreak tie_break_mode = ParseTopKTieBreak(tie_break);
- if (tie_break_mode != sampling::TopKTieBreak::None) {
- deterministic = true;
- }
// Get row_states_buffer if provided (for multi-C... | 0 | 9 | 3 | [
"deepseek"
] | [
"B200",
"SM100"
] | [
"1.141x",
"1.123x",
"1.182x",
"1.135x",
"1.071x",
"1.170x",
"1.080x",
"1.034x",
"1.145x",
"1.078x"
] | Optimize this cuda kernel file from flashinfer (csrc/topk.cu).
Goal: perf(topk): skip output index sort for tie-break selection
Target hardware: B200, SM100
Target models: deepseek
Current file:
```cuda
/*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
... | <!-- .github/pull_request_template.md -->
## 📌 Description
@humansand
Follow-up to #3095.
`tie_break` determines which equal-valued elements are selected at the top-k boundary. Today, requesting a tie-break also promotes the public `deterministic` flag, which runs the index-ordering finalizer even though the defau... | [{"scope": "kernel", "hardware": "NVIDIA B200", "model": null, "shape": "case=decode_b1_q1_l128k,k=2048", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 83.17, "optimized": 74.08, "stated_speedup": 1.123, "speedup": 1.1227}, {"scope": "kernel", "hardware": "NVIDIA B200", "mod... | 1.102 | null |
flashinfer | 67f76379a145f19793896394974e29e610cda912 | 2026-08-04T15:17:59+08:00 | 4,210 | https://github.com/flashinfer-ai/flashinfer/pull/4210 | perf: remove NVFP4 TMA input padding copy (#4210) | perf: remove NVFP4 TMA input padding copy (#4210)
## 📌 Description
Remove the temporary padded input allocation and full-tensor copy from
the CuTe DSL NVFP4 TMA path. The TMA tensor map now describes the
physical `M` rows and relies on G2S TMA out-of-bounds zero fill for row
tiles that extend into the padded scale l... | flashinfer/quantization/kernels/nvfp4_quantize.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/quantization/kernels/nvfp4_quantize.py
+++ flashinfer/quantization/kernels/nvfp4_quantize.py
@@ -1065,13 +1065,12 @@
global_scale: Union[Float32, cute.Tensor],
stream,
):
- # 3D global tensor: [padded_M, K/64, 64] so each warp's 64-col
- # stripe is the contiguous inn... | 5 | 14 | 1 | [] | [
"B200"
] | [] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/quantization/kernels/nvfp4_quantize.py).
Goal: perf: remove NVFP4 TMA input padding copy
Target hardware: B200
Target models: unspecified
Current file:
```python
"""
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (t... | ## 📌 Description
Remove the temporary padded input allocation and full-tensor copy from the CuTe DSL NVFP4 TMA path. The TMA tensor map now describes the physical `M` rows and relies on G2S TMA out-of-bounds zero fill for row tiles that extend into the padded scale layout. The FP4 output remains bounded by `M`, while... | [{"scope": "kernel", "hardware": "B200", "model": null, "shape": "K=4096", "batch_size": 32283, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 212.446, "optimized": 59.248, "stated_speedup": null, "speedup": 3.5857}, {"scope": "kernel", "hardware": "B200", "model": null, "shape": "K=4096", "b... | 1.045 | null |
flashinfer | 496cc1dac3adefb26cb599bd74e2d5efe3a8fcd7 | 2026-08-03T22:00:20-04:00 | 3,523 | https://github.com/flashinfer-ai/flashinfer/pull/3523 | perf: remove dead cudaGetDeviceProperties in sm120 groupwise GEMM (#3523) | perf: remove dead cudaGetDeviceProperties in sm120 groupwise GEMM (#3523)
<!-- .github/pull_request_template.md -->
## 📌 Description
`CutlassGroupwiseScaledGEMMSM120`
(`include/flashinfer/gemm/gemm_groupwise_sm120.cuh`) calls
`cudaGetDevice` + `cudaGetDeviceProperties` on every invocation, but the
resulting `device... | include/flashinfer/gemm/gemm_groupwise_sm120.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/gemm/gemm_groupwise_sm120.cuh
+++ include/flashinfer/gemm/gemm_groupwise_sm120.cuh
@@ -135,12 +135,6 @@
arguments.epilogue.thread.alpha = 1.0f;
arguments.epilogue.thread.beta = 0.0f;
- // Check device compute capability first
- int device_id = 0;
- cudaGetDevice(&device_id);
- cudaDev... | 0 | 6 | 1 | [] | [
"H200",
"SM120"
] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/gemm/gemm_groupwise_sm120.cuh).
Goal: perf: remove dead cudaGetDeviceProperties in sm120 groupwise GEMM
Target hardware: H200, SM120
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the... | <!-- .github/pull_request_template.md -->
## 📌 Description
`CutlassGroupwiseScaledGEMMSM120` (`include/flashinfer/gemm/gemm_groupwise_sm120.cuh`) calls `cudaGetDevice` + `cudaGetDeviceProperties` on every invocation, but the resulting `device_id` and `props` are never read afterwards — the values are dead (a capabil... | [] | null | null |
flashinfer | 5a4b54bed1dfe6f112cd4ec9bc196da517369f46 | 2026-08-03T14:43:37-07:00 | 4,285 | https://github.com/flashinfer-ai/flashinfer/pull/4285 | perf(moe): sync SM12x NVFP4 fused-MoE kernels to b12x HEAD (#4285) | perf(moe): sync SM12x NVFP4 fused-MoE kernels to b12x HEAD (#4285)
## 📌 Description
Syncs the SM12x NVFP4 (W4A4) fused-MoE kernels behind `b12x_fused_moe`
and `B12xMoEWrapper` with upstream
[b12x](https://github.com/local-inference-lab/sparkinfer) at `f9be272`,
reaching backend parity.
The module now has four kerne... | flashinfer/cute_dsl/fp4_common.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/cute_dsl/fp4_common.py
+++ flashinfer/cute_dsl/fp4_common.py
@@ -223,6 +223,22 @@
@dsl_user_op
+def prefetch_global_l2(base_ptr: Int64, *, loc=None, ip=None) -> None:
+ """Prefetch a global memory line into L2."""
+ llvm.inline_asm(
+ None,
+ [Int64(base_ptr).ir_value(loc=loc, ip... | 226 | 2 | 8 | [] | [
"RTX5080",
"SM121"
] | [
"1.06x",
"1.30x",
"1.40x",
"1.00x",
"1.00x",
"1.00x",
"1.10x",
"1.10x",
"1.09x",
"1.00x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/cute_dsl/fp4_common.py).
Goal: perf(moe): sync SM12x NVFP4 fused-MoE kernels to b12x HEAD
Target hardware: RTX5080, SM121
Target models: unspecified
Current file:
```python
"""
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Ver... | ## 📌 Description
Syncs the SM12x NVFP4 (W4A4) fused-MoE kernels behind `b12x_fused_moe` and `B12xMoEWrapper` with upstream [b12x](https://github.com/local-inference-lab/sparkinfer) at `f9be272`, reaching backend parity.
The module now has four kernels. `MoEDirectMicroKernel` takes the smallest decode batches, `MoEMi... | [{"scope": "e2e", "hardware": "DGX Spark", "model": null, "shape": "decode, batch 1-2", "batch_size": null, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.06, "speedup": 1.06}, {"scope": "e2e", "hardware": "RTX 5080", "model": null, "shape": "decode... | null | 1.03 |
flashinfer | 5a4b54bed1dfe6f112cd4ec9bc196da517369f46 | 2026-08-03T14:43:37-07:00 | 4,285 | https://github.com/flashinfer-ai/flashinfer/pull/4285 | perf(moe): sync SM12x NVFP4 fused-MoE kernels to b12x HEAD (#4285) | perf(moe): sync SM12x NVFP4 fused-MoE kernels to b12x HEAD (#4285)
## 📌 Description
Syncs the SM12x NVFP4 (W4A4) fused-MoE kernels behind `b12x_fused_moe`
and `B12xMoEWrapper` with upstream
[b12x](https://github.com/local-inference-lab/sparkinfer) at `f9be272`,
reaching backend parity.
The module now has four kerne... | flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_activation.py | cute_dsl | Apache-2.0 | """Activation helper functions for the b12x fused-MoE kernels."""
from __future__ import annotations
import cutlass
import cutlass.cute as cute
from cutlass import Float32
from flashinfer.cute_dsl.fp4_common import fmax_f32, fmin_f32
def is_gated_activation(activation: str) -> bool:
return activation in ("silu... | """Activation helper functions and metadata for the b12x fused-MoE kernels."""
from __future__ import annotations
import math
import cutlass
import cutlass.cute as cute
from cutlass import Float32
from flashinfer.cute_dsl.fp4_common import fmax_f32, fmin_f32
SWIGLUOAI_UNINTERLEAVE = "swigluoai_uninterleave"
SWIGL... | --- flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_activation.py
+++ flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_activation.py
@@ -1,6 +1,8 @@
-"""Activation helper functions for the b12x fused-MoE kernels."""
+"""Activation helper functions and metadata for the b12x fused-MoE kernels."""
from __future__ im... | 83 | 2 | 8 | [] | [
"RTX5080",
"SM121"
] | [
"1.06x",
"1.30x",
"1.40x",
"1.00x",
"1.00x",
"1.00x",
"1.10x",
"1.10x",
"1.09x",
"1.00x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_activation.py).
Goal: perf(moe): sync SM12x NVFP4 fused-MoE kernels to b12x HEAD
Target hardware: RTX5080, SM121
Target models: unspecified
Current file:
```python
"""Activation helper functions for the b12x fused-Mo... | ## 📌 Description
Syncs the SM12x NVFP4 (W4A4) fused-MoE kernels behind `b12x_fused_moe` and `B12xMoEWrapper` with upstream [b12x](https://github.com/local-inference-lab/sparkinfer) at `f9be272`, reaching backend parity.
The module now has four kernels. `MoEDirectMicroKernel` takes the smallest decode batches, `MoEMi... | [{"scope": "e2e", "hardware": "DGX Spark", "model": null, "shape": "decode, batch 1-2", "batch_size": null, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.06, "speedup": 1.06}, {"scope": "e2e", "hardware": "RTX 5080", "model": null, "shape": "decode... | null | 1.03 |
flashinfer | 5a4b54bed1dfe6f112cd4ec9bc196da517369f46 | 2026-08-03T14:43:37-07:00 | 4,285 | https://github.com/flashinfer-ai/flashinfer/pull/4285 | perf(moe): sync SM12x NVFP4 fused-MoE kernels to b12x HEAD (#4285) | perf(moe): sync SM12x NVFP4 fused-MoE kernels to b12x HEAD (#4285)
## 📌 Description
Syncs the SM12x NVFP4 (W4A4) fused-MoE kernels behind `b12x_fused_moe`
and `B12xMoEWrapper` with upstream
[b12x](https://github.com/local-inference-lab/sparkinfer) at `f9be272`,
reaching backend parity.
The module now has four kerne... | flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_dispatch.py | cute_dsl | Apache-2.0 | """SM120/SM121 MoE dispatch layer — workspace, compilation, and launch.
Ported from b12x's integration/tp_moe.py. Supports micro (tiny decode),
static (decode), and dynamic (prefill) backends with token-count-based
selection.
"""
from __future__ import annotations
import os
import weakref
from dataclasses import dat... | """SM120/SM121 MoE dispatch layer — workspace, compilation, and launch.
Ported from b12x's integration/tp_moe.py. Supports micro (tiny decode),
static (decode), and dynamic (prefill) backends with token-count-based
selection.
"""
from __future__ import annotations
import os
import weakref
from dataclasses import dat... | --- flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_dispatch.py
+++ flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_dispatch.py
@@ -24,8 +24,14 @@
get_num_sm,
make_ptr,
)
-from .moe_activation import is_gated_activation
-from .moe_dynamic_kernel import MoEDynamicKernel
+from .moe_activation import SWIGLU... | 410 | 128 | 8 | [] | [
"RTX5080",
"SM121"
] | [
"1.06x",
"1.30x",
"1.40x",
"1.00x",
"1.00x",
"1.00x",
"1.10x",
"1.10x",
"1.09x",
"1.00x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_dispatch.py).
Goal: perf(moe): sync SM12x NVFP4 fused-MoE kernels to b12x HEAD
Target hardware: RTX5080, SM121
Target models: unspecified
Current file:
```python
"""SM120/SM121 MoE dispatch layer — workspace, compila... | ## 📌 Description
Syncs the SM12x NVFP4 (W4A4) fused-MoE kernels behind `b12x_fused_moe` and `B12xMoEWrapper` with upstream [b12x](https://github.com/local-inference-lab/sparkinfer) at `f9be272`, reaching backend parity.
The module now has four kernels. `MoEDirectMicroKernel` takes the smallest decode batches, `MoEMi... | [{"scope": "e2e", "hardware": "DGX Spark", "model": null, "shape": "decode, batch 1-2", "batch_size": null, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.06, "speedup": 1.06}, {"scope": "e2e", "hardware": "RTX 5080", "model": null, "shape": "decode... | null | 1.03 |
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